Skip to content
View 0sama-Mirza's full-sized avatar
😶‍🌫️
Yo!
😶‍🌫️
Yo!
8 followers · 67 following

Achievements

Achievement: Pull SharkAchievement: YOLO

Achievements

Achievement: Pull SharkAchievement: YOLO

Block or report 0sama-Mirza

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Stars

2 stars written in Verilog
Clear filter

FPGAwars / apio

🌱 Open source ecosystem for open FPGA boards

Verilog 813 140 Updated Jan 13, 2025

barrettotte / Subarashii-CPU

A 16-bit RISC CPU inspired by MIPS. I designed this to learn more about computer architecture/organization.

Verilog 8 1 Updated Aug 3, 2020