From 7b6c767838d88e6985b932e092af833d332832f2 Mon Sep 17 00:00:00 2001
From: taimur-10xe <92528065+taimur-10xe@users.noreply.github.com>
Date: Fri, 13 Oct 2023 16:21:19 +0500
Subject: [PATCH] added description for FPGA binaries

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 README.md | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/README.md b/README.md
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 # Infinite-ISP
-Infinite-ISP is a one stop solution for all your ISP development needs - from algorithms to an FPGA prototype and associated firmware, tools, etc. Its primary goal is to offer a unified platform that empowers ISP developers to accelerate ISP innovation. It includes a complete collection of camera pipeline modules written in Python, an FPGA bit-stream & the associated firmware for the implementation of the pipeline on the Kria KV260 development board and lastly a stand-alone Python based Tuning tool application for the pipeline.  The main components of the Infinite-ISP project are listed below:
+Infinite-ISP is a one stop solution for all your ISP development needs - from algorithms to an FPGA prototype and associated firmware, tools, etc. Its primary goal is to offer a unified platform that empowers ISP developers to accelerate ISP innovation. It includes a complete collection of camera pipeline modules written in Python, an FPGA bitstream & the associated Firmware for the implementation of the pipeline on the Kria KV260 development board and lastly a stand-alone Python based Tuning Tool application for the pipeline.  The main components of the Infinite-ISP project are listed below:
 
 | Repository name        | Description      | 
 | -------------  | ------------- |
 | **[Infinite-ISP_AlgorithmDesign](https://github.com/xx-isp/infinite-isp)**                        | Python based model of the Infinite-ISP pipeline for algorithm development |
 | **[Infinite-ISP_ReferenceModel](https://github.com/10xEngineersTech/Infinite-ISP_ReferenceModel)**                       | Python based fixed-point model of the Infinite-ISP pipeline for hardware implementation |
-| **[Infinite-ISP_FPGABinaries](https://github.com/10xEngineersTech/Infinite-ISP_FPGA_Binaries)** :anchor:                                     | FPGA binaries for the Kria KV260’s Xilinx® XCK26 Ultrascale FPGA|
+| **[Infinite-ISP_FPGABinaries](https://github.com/10xEngineersTech/Infinite-ISP_FPGA_Binaries)** :anchor:                                     | FPGA binaries (bitstream + firmware executable) for the Kria KV260’s Xilinx® XCK26 Ultrascale FPGA |
 | **[Infinite-ISP_Firmware](https://github.com/10xEngineersTech/Infinite-ISP_Firmware)**                                      | Firmware for the Kria KV260’s embedded Arm® Cortex®A53 processor|
 | **[Infinite-ISP_TuningTool](https://github.com/10xEngineersTech/Infinite-ISP_TuningTool)**                              | Collection of calibration and analysis tools for the Infinite-ISP |
 
 
-# Infinite-ISP_FPGA_Binaries
-Infinite-ISP Image Signal Processing Pipeline FPGA binaries for XCK26 Zynq® UltraScale+™ MPSoC present on Xilinx® Kria™ KV260 Vision AI Starter Kit
+# Infinite-ISP FPGA Binaries
+Infinite-ISP Image Signal Processing Pipeline FPGA binaries for XCK26 Zynq® UltraScale+™ MPSoC present on Xilinx® Kria™ KV260 Vision AI Starter Kit. Each binary file includes an FPGA bitstream paired with its firmware executable.
 
 # How to use the FPGA Binary Files
 1. Connect AR1335 IAS image sensor module (included in Xilinx Kria KV260 Accessory Pack) to the IAS1 port on Kria KV260 AI Starter Kit.