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vcpu.c
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/*
* Copyright (c) 2009 Intel Corporation
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include "../include/hax.h"
#include "include/compiler.h"
#include "include/ia32_defs.h"
#include "include/vcpu.h"
#include "include/mtrr.h"
#include "include/vmx.h"
#include "include/cpu.h"
#include "include/cpuid.h"
#include "include/vm.h"
#include "include/debug.h"
#include "include/dump.h"
#include "include/intr.h"
#include "include/vtlb.h"
#include "include/ept.h"
#include "include/paging.h"
#include "include/hax_core_interface.h"
#include "include/hax_driver.h"
uint64_t gmsr_list[NR_GMSR] = {
IA32_STAR,
IA32_LSTAR,
IA32_CSTAR,
IA32_SF_MASK,
IA32_KERNEL_GS_BASE
};
uint64_t hmsr_list[NR_HMSR] = {
IA32_EFER,
IA32_STAR,
IA32_LSTAR,
IA32_CSTAR,
IA32_SF_MASK,
IA32_KERNEL_GS_BASE
};
uint64_t emt64_msr[NR_EMT64MSR] = {
IA32_STAR,
IA32_LSTAR,
IA32_CSTAR,
IA32_SF_MASK,
IA32_KERNEL_GS_BASE
};
extern uint32_t pw_reserved_bits_high_mask;
static void vcpu_init(struct vcpu_t *vcpu);
static void vcpu_prepare(struct vcpu_t *vcpu);
static void vcpu_init_emulator(struct vcpu_t *vcpu);
static void vmread_cr(struct vcpu_t *vcpu);
static void vmwrite_cr(struct vcpu_t *vcpu);
static int exit_exc_nmi(struct vcpu_t *vcpu, struct hax_tunnel *htun);
static int exit_interrupt(struct vcpu_t *vcpu, struct hax_tunnel *htun);
static int exit_triple_fault(struct vcpu_t *vcpu, struct hax_tunnel *htun);
static int exit_interrupt_window(struct vcpu_t *vcpu, struct hax_tunnel *htun);
static int exit_taskswitch(struct vcpu_t *vcpu, struct hax_tunnel *htun);
static int exit_cpuid(struct vcpu_t *vcpu, struct hax_tunnel *htun);
static int exit_hlt(struct vcpu_t *vcpu, struct hax_tunnel *htun);
static int exit_invlpg(struct vcpu_t *vcpu, struct hax_tunnel *htun);
static int exit_rdtsc(struct vcpu_t *vcpu, struct hax_tunnel *htun);
static int exit_cr_access(struct vcpu_t *vcpu, struct hax_tunnel *htun);
static int exit_dr_access(struct vcpu_t *vcpu, struct hax_tunnel *htun);
static int exit_io_access(struct vcpu_t *vcpu, struct hax_tunnel *htun);
static int exit_msr_read(struct vcpu_t *vcpu, struct hax_tunnel *htun);
static int exit_msr_write(struct vcpu_t *vcpu, struct hax_tunnel *htun);
static int exit_invalid_guest_state(struct vcpu_t *vcpu,
struct hax_tunnel *htun);
static int exit_ept_misconfiguration(struct vcpu_t *vcpu,
struct hax_tunnel *htun);
static int exit_ept_violation(struct vcpu_t *vcpu, struct hax_tunnel *htun);
static int exit_unsupported_instruction(struct vcpu_t *vcpu,
struct hax_tunnel *htun);
static int null_handler(struct vcpu_t *vcpu, struct hax_tunnel *hun);
static void advance_rip(struct vcpu_t *vcpu);
static void handle_machine_check(struct vcpu_t *vcpu);
static void handle_cpuid_virtual(struct vcpu_t *vcpu, uint32_t eax, uint32_t ecx);
static void handle_mem_fault(struct vcpu_t *vcpu, struct hax_tunnel *htun);
static void check_flush(struct vcpu_t *vcpu, uint32_t bits);
static void vmwrite_efer(struct vcpu_t *vcpu);
static int handle_msr_read(struct vcpu_t *vcpu, uint32_t msr, uint64_t *val);
static int handle_msr_write(struct vcpu_t *vcpu, uint32_t msr, uint64_t val,
bool by_host);
static void handle_cpuid(struct vcpu_t *vcpu, struct hax_tunnel *htun);
static void vcpu_dump(struct vcpu_t *vcpu, uint32_t mask, const char *caption);
static void vcpu_state_dump(struct vcpu_t *vcpu);
static void vcpu_enter_fpu_state(struct vcpu_t *vcpu);
static int vcpu_set_apic_base(struct vcpu_t *vcpu, uint64_t val);
static bool vcpu_is_bsp(struct vcpu_t *vcpu);
static uint32_t get_seg_present(uint32_t seg)
{
mword ldtr_base;
struct seg_desc_t *seg_desc;
struct hstate *hstate = &get_cpu_data(hax_cpu_id())->hstate;
ldtr_base = get_kernel_ldtr_base();
seg_desc = (struct seg_desc_t *)ldtr_base + (seg >> 3);
if (seg_desc->_present) {
hstate->fake_gs = seg_desc->_raw;
}
return seg_desc->_present;
}
static void fake_seg_gs_entry(struct hstate *hstate)
{
mword ldtr_base;
struct seg_desc_t *seg_desc = NULL;
uint16_t seg = hstate->gs;
ldtr_base = get_kernel_ldtr_base();
seg_desc = (struct seg_desc_t *)ldtr_base + (seg >> 3);
if (seg_desc->_present == 0)
seg_desc->_raw = hstate->fake_gs;
set_kernel_gs(seg);
ia32_wrmsr(IA32_GS_BASE, hstate->gs_base);
seg_desc->_raw = 0;
}
static void get_segment_desc_t(segment_desc_t *sdt, uint32_t s, uint64_t b,
uint32_t l, uint32_t a)
{
sdt->selector = s;
sdt->base = b;
sdt->limit = l;
sdt->ar = a;
}
static inline void set_gdt(struct vcpu_state_t *state, uint64_t base,
uint64_t limit)
{
state->_gdt.base = base;
state->_gdt.limit = limit;
}
static inline void set_idt(struct vcpu_state_t *state, uint64_t base,
uint64_t limit)
{
state->_idt.base = base;
state->_idt.limit = limit;
}
static uint64_t vcpu_read_cr(struct vcpu_state_t *state, uint32_t n)
{
uint64_t val = 0;
switch (n) {
case 0: {
val = state->_cr0;
break;
}
case 2: {
val = state->_cr2;
break;
}
case 3: {
val = state->_cr3;
break;
}
case 4: {
val = state->_cr4;
break;
}
default: {
hax_log(HAX_LOGW, "Ignored unsupported CR%d read, returning 0\n",
n);
break;
}
}
hax_log(HAX_LOGD, "vcpu_read_cr cr %x val %llx\n", n, val);
return val;
}
static void vcpu_write_cr(struct vcpu_state_t *state, uint32_t n, uint64_t val)
{
hax_log(HAX_LOGD, "vcpu_write_cr cr %x val %llx\n", n, val);
switch (n) {
case 0: {
state->_cr0 = val;
break;
}
case 2: {
state->_cr2 = val;
break;
}
case 3: {
state->_cr3 = val;
break;
}
case 4: {
state->_cr4 = val;
break;
}
default: {
hax_log(HAX_LOGE, "write_cr: Unsupported CR%d access\n", n);
break;
}
}
}
void * vcpu_vmcs_va(struct vcpu_t *vcpu)
{
return hax_page_va(vcpu->vmcs_page);
}
hax_paddr_t vcpu_vmcs_pa(struct vcpu_t *vcpu)
{
return hax_page_pa(vcpu->vmcs_page);
}
static void set_activity_state(struct vcpu_state_t *vcpu_state, uint state)
{
vcpu_state->_activity_state = state;
}
static uint get_activity_state(struct vcpu_state_t *state)
{
return state->_activity_state;
}
void * get_vcpu_host(struct vcpu_t *vcpu)
{
return vcpu ? vcpu->vcpu_host : NULL;
}
int set_vcpu_host(struct vcpu_t *vcpu, void *vcpu_host)
{
if (!vcpu || (vcpu->vcpu_host && vcpu->vcpu_host != vcpu_host))
return -1;
vcpu->vcpu_host = vcpu_host;
return 0;
}
int set_vcpu_tunnel(struct vcpu_t *vcpu, struct hax_tunnel *tunnel,
uint8_t *iobuf)
{
if (!vcpu || (vcpu->tunnel && tunnel && vcpu->tunnel != tunnel) ||
(vcpu->io_buf && iobuf && vcpu->io_buf != iobuf))
return -1;
vcpu->tunnel = tunnel;
vcpu->io_buf = iobuf;
return 0;
}
struct hax_tunnel * get_vcpu_tunnel(struct vcpu_t *vcpu)
{
return vcpu ? vcpu->tunnel : NULL;
}
/*
* vcpu_vpid_alloc()
*
* Allocate a non-zero unique VPID for virtual processor.
* The allocated VPID is stored in vcpu->vpid.
* In the case of allocating failure, the vcpu->vpid will keeps zero, which
* means "do not enable VPID feature".
*
* Param: vcpu - specify the virtual processor who will get the VPID
* Return Value: 0 - means success. Negative value - means failure.
*/
static int vcpu_vpid_alloc(struct vcpu_t *vcpu)
{
uint32_t vpid_seed_bits = sizeof(vcpu->vm->vpid_seed) * 8;
uint8_t bit, max_bit;
max_bit = vpid_seed_bits > 0xff ? 0xff : vpid_seed_bits;
if (0 != vcpu->vpid) {
hax_log(HAX_LOGW, "vcpu_vpid_alloc: vcpu %u in vm %d already has a "
"valid VPID 0x%x.\n", vcpu->vcpu_id, vcpu->vm->vm_id,
vcpu->vpid);
return -1;
}
for (bit = 0; bit < max_bit; bit++) {
if (!hax_test_and_set_bit(bit, (uint64_t *)vcpu->vm->vpid_seed))
break;
}
if (bit == max_bit) {
// No available VPID resource
hax_log(HAX_LOGE, "vcpu_vpid_alloc: no available vpid resource. "
"vcpu: %u, vm: %d\n", vcpu->vcpu_id, vcpu->vm->vm_id);
return -2;
}
/*
* We split vpid as high byte and low byte, the vpid seed is used to
* generate low byte. We use the index of first zero bit in vpid seed plus 1
* as the value of low_byte, and use vcpu->vm->vm_id as the value of high
* byte.
* Note: vpid can't be zero.
*/
vcpu->vpid = (uint16_t)(vcpu->vm->vm_id << 8) + (uint16_t)(bit + 1);
hax_log(HAX_LOGI, "vcpu_vpid_alloc: succeed! vpid: 0x%x. vcpu_id: %u, "
"vm_id: %d.\n", vcpu->vpid, vcpu->vcpu_id, vcpu->vm->vm_id);
return 0;
}
/*
* vcpu_vpid_free()
*
* Free the VPID that stored in vcpu->vpid for virtual processor.
* The value of vcpu->vpid will be reset to zero after freeing.
*
* Param: vcpu - specify the virtual processor whose VPID will be freed.
* Return Value: 0 - means success.
* Negative value - means vcpu->vpid has been already freed.
*/
static int vcpu_vpid_free(struct vcpu_t *vcpu)
{
uint8_t bit = (vcpu->vpid & 0xff) - 1;
if (0 == vcpu->vpid) {
hax_log(HAX_LOGW, "vcpu_vpid_free: vcpu %u in vm %d does not have a "
"valid VPID.\n", vcpu->vcpu_id, vcpu->vm->vm_id);
return -1;
}
hax_log(HAX_LOGI, "vcpu_vpid_free: Clearing bit: 0x%x, vpid_seed: 0x%llx. "
"vcpu_id: %u, vm_id: %d.\n", bit, *(uint64_t *)vcpu->vm->vpid_seed,
vcpu->vcpu_id, vcpu->vm->vm_id);
if (0 != hax_test_and_clear_bit(bit, (uint64_t *)(vcpu->vm->vpid_seed))) {
hax_log(HAX_LOGW, "vcpu_vpid_free: bit for vpid 0x%x of vcpu %u in vm "
"%d was already clear.\n", vcpu->vpid, vcpu->vcpu_id,
vcpu->vm->vm_id);
}
vcpu->vpid = 0;
return 0;
}
static int (*handler_funcs[])(struct vcpu_t *vcpu, struct hax_tunnel *htun) = {
[VMX_EXIT_INT_EXCEPTION_NMI] = exit_exc_nmi,
[VMX_EXIT_EXT_INTERRUPT] = exit_interrupt,
[VMX_EXIT_TRIPLE_FAULT] = exit_triple_fault,
[VMX_EXIT_PENDING_INTERRUPT] = exit_interrupt_window,
[VMX_EXIT_PENDING_NMI] = exit_interrupt_window,
[VMX_EXIT_CPUID] = exit_cpuid,
[VMX_EXIT_HLT] = exit_hlt,
[VMX_EXIT_INVLPG] = exit_invlpg,
[VMX_EXIT_RDTSC] = exit_rdtsc,
[VMX_EXIT_CR_ACCESS] = exit_cr_access,
[VMX_EXIT_DR_ACCESS] = exit_dr_access,
[VMX_EXIT_IO] = exit_io_access,
[VMX_EXIT_MSR_READ] = exit_msr_read,
[VMX_EXIT_MSR_WRITE] = exit_msr_write,
[VMX_EXIT_FAILED_VMENTER_GS] = exit_invalid_guest_state,
[VMX_EXIT_EPT_VIOLATION] = exit_ept_violation,
[VMX_EXIT_EPT_MISCONFIG] = exit_ept_misconfiguration,
[VMX_EXIT_GETSEC] = exit_unsupported_instruction,
[VMX_EXIT_INVD] = exit_unsupported_instruction,
[VMX_EXIT_VMCALL] = exit_unsupported_instruction,
[VMX_EXIT_VMCLEAR] = exit_unsupported_instruction,
[VMX_EXIT_VMLAUNCH] = exit_unsupported_instruction,
[VMX_EXIT_VMPTRLD] = exit_unsupported_instruction,
[VMX_EXIT_VMPTRST] = exit_unsupported_instruction,
//VMREAD and VMWRITE vm-exits are conditional. When "VMCS shadowing" bit
//in secondary CPU VM-execution control is 0, these exit. This condition
//holds in haxm.
[VMX_EXIT_VMREAD] = exit_unsupported_instruction,
[VMX_EXIT_VMWRITE] = exit_unsupported_instruction,
[VMX_EXIT_VMRESUME] = exit_unsupported_instruction,
[VMX_EXIT_VMXOFF] = exit_unsupported_instruction,
[VMX_EXIT_VMXON] = exit_unsupported_instruction,
[VMX_EXIT_XSETBV] = exit_unsupported_instruction,
};
static int nr_handlers = ARRAY_ELEMENTS(handler_funcs);
struct vcpu_t *vcpu_create(struct vm_t *vm, void *vm_host, int vcpu_id)
{
struct hax_tunnel_info info;
struct vcpu_t *vcpu;
hax_log(HAX_LOGD, "vcpu_create vcpu_id %x\n", vcpu_id);
if (!valid_vcpu_id(vcpu_id))
return NULL;
vcpu = (struct vcpu_t *)hax_vmalloc(sizeof(struct vcpu_t), HAX_MEM_NONPAGE);
if (!vcpu)
goto fail_0;
hax_clear_panic_log(vcpu);
memset(vcpu, 0, sizeof(struct vcpu_t));
if (hax_vcpu_setup_hax_tunnel(vcpu, &info) < 0) {
hax_log(HAX_LOGE, "cannot setup hax_tunnel for vcpu.\n");
goto fail_1;
}
vcpu->vmcs_page = (struct hax_page *)hax_alloc_page(0, 1);
if (!vcpu->vmcs_page)
goto fail_2;
vcpu->gstate.gfxpage = (struct hax_page *)hax_alloc_page(0, 1);
if (!vcpu->gstate.gfxpage)
goto fail_3;
hax_clear_page(vcpu->gstate.gfxpage);
hax_clear_page(vcpu->vmcs_page);
vcpu->state = (struct vcpu_state_t *)hax_vmalloc(
sizeof(struct vcpu_state_t), HAX_MEM_NONPAGE);
if (!vcpu->state)
goto fail_4;
memset(vcpu->state, 0, sizeof(struct vcpu_state_t));
vcpu->tmutex = hax_mutex_alloc_init();
if (!vcpu->tmutex)
goto fail_5;
if (!vcpu_vtlb_alloc(vcpu))
goto fail_6;
if (hax_vcpu_create_host(vcpu, vm_host, vm->vm_id, vcpu_id))
goto fail_7;
vcpu->prev_cpu_id = (uint32_t)(~0ULL);
vcpu->cpu_id = hax_cpu_id();
vcpu->vcpu_id = vcpu_id;
vcpu->is_running = 0;
vcpu->vm = vm;
// Must ensure it is called before fill_common_vmcs is called
vcpu_vpid_alloc(vcpu);
// Prepare guest environment
vcpu_init(vcpu);
// First time vmclear/vmptrld on current CPU
vcpu_prepare(vcpu);
// Publish the vcpu
hax_mutex_lock(vm->vm_lock);
hax_list_add(&vcpu->vcpu_list, &vm->vcpu_list);
// The caller should get_vm thus no race with vm destroy
hax_atomic_add(&vm->ref_count, 1);
hax_mutex_unlock(vm->vm_lock);
// Initialize emulator
vcpu_init_emulator(vcpu);
hax_log(HAX_LOGD, "vcpu %d is created.\n", vcpu->vcpu_id);
return vcpu;
fail_7:
vcpu_vtlb_free(vcpu);
fail_6:
hax_mutex_free(vcpu->tmutex);
fail_5:
hax_vfree(vcpu->state, sizeof(struct vcpu_state_t));
fail_4:
if (vcpu->gstate.gfxpage) {
hax_free_pages(vcpu->gstate.gfxpage);
}
fail_3:
hax_free_pages(vcpu->vmcs_page);
fail_2:
hax_vcpu_destroy_hax_tunnel(vcpu);
fail_1:
hax_vfree(vcpu, sizeof(struct vcpu_t));
fail_0:
hax_log(HAX_LOGE, "Cannot allocate memory to create vcpu.\n");
return NULL;
}
/*
* We don't need corresponding vcpu_core_close because once closed, the VM will
* be destroyed
*/
int hax_vcpu_core_open(struct vcpu_t *vcpu)
{
if (!vcpu)
return -ENODEV;
if (hax_test_and_set_bit(VCPU_STATE_FLAGS_OPENED, &(vcpu->flags)))
return -EBUSY;
return 0;
}
static int _vcpu_teardown(struct vcpu_t *vcpu)
{
int vcpu_id = vcpu->vcpu_id;
if (vcpu->mmio_fetch.kva) {
gpa_space_unmap_page(&vcpu->vm->gpa_space, &vcpu->mmio_fetch.kmap);
}
// TODO: we should call invvpid after calling vcpu_vpid_free().
vcpu_vpid_free(vcpu);
if (vcpu->gstate.gfxpage) {
hax_free_pages(vcpu->gstate.gfxpage);
}
hax_free_pages(vcpu->vmcs_page);
hax_vfree(vcpu->state, sizeof(struct vcpu_state_t));
vcpu_vtlb_free(vcpu);
hax_mutex_free(vcpu->tmutex);
hax_vfree(vcpu, sizeof(struct vcpu_t));
hax_log(HAX_LOGI, "vcpu %d is teardown.\n", vcpu_id);
return 0;
}
int vcpu_teardown(struct vcpu_t *vcpu)
{
struct vm_t *vm = vcpu->vm;
int ret;
hax_mutex_lock(vm->vm_lock);
hax_list_del(&vcpu->vcpu_list);
hax_mutex_unlock(vm->vm_lock);
ret = _vcpu_teardown(vcpu);
// Should not hold the vmlock here
// Trying to put vm again
hax_put_vm(vm);
return ret;
}
static void vcpu_init(struct vcpu_t *vcpu)
{
// TODO: Need to decide which mode guest will start
struct vcpu_state_t *state = vcpu->state;
int i;
hax_mutex_lock(vcpu->tmutex);
// TODO: mtrr ?
vcpu->cr_pat = 0x0007040600070406ULL;
vcpu->cpuid_features_flag_mask = 0xffffffffffffffffULL;
vcpu->cur_state = GS_VALID;
vmx(vcpu, entry_exception_vector) = ~0u;
vmx(vcpu, cr0_mask) = 0;
vmx(vcpu, cr0_shadow) = 0;
vmx(vcpu, cr4_mask) = 0;
vmx(vcpu, cr4_shadow) = 0;
vcpu->ref_count = 1;
vcpu->tsc_offset = 0ULL - ia32_rdtsc();
// Prepare the vcpu state to Power-up
state->_rflags = 2;
state->_rip = 0x0000fff0;
state->_cr0 = 0x60000010;
get_segment_desc_t(&state->_cs, 0xf000, 0xffff0000, 0xffff, 0x93);
get_segment_desc_t(&state->_ss, 0, 0, 0xffff, 0x93);
get_segment_desc_t(&state->_ds, 0, 0, 0xffff, 0x93);
get_segment_desc_t(&state->_es, 0, 0, 0xffff, 0x93);
get_segment_desc_t(&state->_fs, 0, 0, 0xffff, 0x93);
get_segment_desc_t(&state->_gs, 0, 0, 0xffff, 0x93);
set_gdt(state, 0, 0xffff);
set_idt(state, 0, 0xffff);
get_segment_desc_t(&state->_ldt, 0, 0, 0xffff, 0x82);
get_segment_desc_t(&state->_tr, 0, 0, 0xffff, 0x83);
state->_dr0 = state->_dr1 = state->_dr2 = state->_dr3 = 0x0;
state->_dr6 = DR6_SETBITS;
state->_dr7 = DR7_SETBITS;
vcpu->dr_dirty = 1;
// Initialize guest MSR state, i.e. a list of MSRs and their initial values.
// Note that all zeros is not a valid state (see below). At the first VM
// entry, these MSRs will be loaded with these values, unless QEMU has
// overridden them using HAX_VCPU_IOCTL_SET_MSRS.
// TODO: Enable hardware-assisted MSR save/restore (cf. IA SDM Vol. 3C
// 31.10.2-31.10.3: Using VM-Exit/VM-Entry Controls for MSRs).
for (i = 0; i < NR_GMSR; i++) {
// Without this initialization, |entry| defaults to 0, which is also
// a valid MSR (IA32_P5_MC_ADDR, often implemented as an alias for
// IA32_MC0_CTL), but which is not one that HAXM should tamper with.
// In fact, writing 0 to it has serious consequences, including
// disabling SGX (cf. IA SDM Vol. 3D 42.15.2: Machine Check Enables).
vcpu->gstate.gmsr[i].entry = gmsr_list[i];
// 0 is an appropriate initial value for all MSRs in gmsr_list[]
vcpu->gstate.gmsr[i].value = 0;
}
// Initialize IA32_APIC_BASE MSR
vcpu->gstate.apic_base = APIC_BASE_DEFAULT_ADDR | APIC_BASE_ENABLE;
if (vcpu_is_bsp(vcpu)) {
vcpu->gstate.apic_base |= APIC_BASE_BSP;
}
hax_mutex_unlock(vcpu->tmutex);
}
#ifdef DEBUG_HOST_STATE
static int check_panic(void)
{
char *kernel_panic = NULL;
return 0;
}
// Code to check the host state between vmluanch and vmexit
static uint32_t get_seg_avail(uint32_t seg)
{
mword gdtr_base;
struct seg_desc_t *sd;
gdtr_base = get_kernel_gdtr_base();
sd = (struct seg_desc_t *)gdtr_base + (seg >> 3);
return sd->_avl;
}
static void dump_segment(uint32_t seg)
{
struct seg_desc_t *sd;
mword gdtr_base;
gdtr_base = get_kernel_gdtr_base();
sd = (struct seg_desc_t *)gdtr_base + (seg >> 3);
hax_log(HAX_LOGD, "seg %x value %llx\n", seg, sd->_raw);
}
static int check_cs(uint32_t seg)
{
mword gdtr_base;
mword desc_base;
struct seg_desc_t *sd;
gdtr_base = get_kernel_gdtr_base();
sd = (struct seg_desc_t *)gdtr_base + (seg >> 3);
if (sd->_base0 != 0 || sd->_base1 != 0)
return 1;
if (sd->_limit1 != 0xf || sd->_limit0 != 0xffff)
return 1;
if (sd->_type != 0xb)
return 1;
if (sd->_s != 1)
return 1;
if (sd->_dpl != 0)
return 1;
if (sd->_present != 1)
return 1;
if (sd->_longmode != 0x1)
return 1;
if (sd->_d != 0x0)
return 1;
if (sd->_granularity != 1)
return 1;
return 0;
}
static int check_data_seg(uint32_t seg)
{
mword gdtr_base;
mword desc_base;
struct seg_desc_t *sd;
gdtr_base = get_kernel_gdtr_base();
sd = (struct seg_desc_t *)gdtr_base + (seg >> 3);
if (sd->_base0 != 0 || sd->_base1 != 0)
return 1;
if (sd->_limit1 != 0xf || sd->_limit0 != 0xffff)
return 1;
if (sd->_type != 0x3)
return 1;
if (sd->_s != 1)
return 1;
if (sd->_dpl != 0) {
// The DPL is wrong for Mac return 0 now
return 0;
}
if (sd->_present != 1)
return 1;
// if (sd->_longmode != 0x1)
// return 1;
if (sd->_d != 0x1)
return 1;
if (sd->_granularity != 1)
return 1;
return 0;
}
static int check_stack_seg(uint32_t seg)
{
mword gdtr_base;
mword desc_base;
struct seg_desc_t *sd;
gdtr_base = get_kernel_gdtr_base();
sd = (struct seg_desc_t *)gdtr_base + (seg >> 3);
if (sd->_base0 != 0 || sd->_base1 != 0)
return 1;
if (sd->_limit1 != 0xf || sd->_limit0 != 0xffff)
return 1;
if (sd->_type != 0x3)
return 1;
if (sd->_s != 1)
return 1;
if (sd->_dpl != 0)
return 1;
if (sd->_present != 1)
return 1;
// if (sd->_longmode != 0x1)
// return 1;
if (sd->_d != 0x1)
return 1;
if (sd->_granularity != 1)
return 1;
return 0;
}
static int check_tr_seg(uint32_t seg)
{
mword gdtr_base;
struct seg_desc_t *sd;
gdtr_base = get_kernel_gdtr_base();
sd = (struct seg_desc_t *)gdtr_base + (seg >> 3);
// if (sd->_base0 != 0 || sd->_base1 != 0)
// return 1;
if (sd->_limit1 != 0x0 || sd->_limit0 != 0x67)
return 1;
if (sd->_type != 0xb)
return 1;
if (sd->_s != 0)
return 1;
if (sd->_dpl != 0)
return 1;
if (sd->_present != 1)
return 1;
// if (sd->_longmode != 0x1)
// return 1;
if (sd->_d != 0x0)
return 1;
if (sd->_granularity != 0)
return 1;
return 0;
}
static int check_fgs_seg(uint32_t seg, uint fs)
{
mword gdtr_base;
mword desc_base;
struct seg_desc_t *sd;
mword base;
if (seg == 0) {
hax_log(HAX_LOGD, "fgs_seg seg is %x fs %x\n", seg, fs);
return 0;
}
gdtr_base = get_kernel_gdtr_base();
sd = (struct seg_desc_t *)gdtr_base + (seg >> 3);
if (fs) {
base = ia32_rdmsr(IA32_FS_BASE);
} else {
base = ia32_rdmsr(IA32_GS_BASE);
}
if ((base & 0xffffff) != sd->_base0 ||
((base >> 24) & 0xff) != sd->_base1) {
// hax_log(HAX_LOGD, "%s base address mismatch base %llx sd %llx\n",
// fs ? "fs" : "gs", base, sd->_raw);
// return 1;
return 0;
}
if (sd->_base0 != 0 || sd->_base1 != 0)
return 1;
if (sd->_limit1 != 0xf || sd->_limit0 != 0xffff)
return 1;
if (sd->_type != 0x3)
return 1;
if (sd->_s != 1)
return 1;
if (sd->_dpl != 0)
return 1;
if (sd->_present != 1)
return 1;
// if (sd->_longmode != 0x1)
// return 1;
if (sd->_d != 0x1)
return 1;
if (sd->_granularity != 1)
return 1;
return 0;
}
int vcpu_get_host_state(struct vcpu_t *vcpu, int pre)
{
uint64_t value;
struct host_state_compare *hsc;
hsc = pre ? &vcpu->hsc_pre : &vcpu->hsc_post;
memset(hsc, 0, sizeof(struct host_state_compare));
hsc->cr0 = get_cr0();
hsc->cr2 = get_cr2();
hsc->cr3 = get_cr3();
hsc->cr4 = get_cr4();
// Check segmentation
hsc->cs = get_kernel_cs();
hsc->cs_avail = get_seg_avail(hsc->cs);
hsc->ds = get_kernel_ds();
hsc->ds_avail = get_seg_avail(hsc->ds);
hsc->es = get_kernel_es();
hsc->es_avail = get_seg_avail(hsc->es);
hsc->ss = get_kernel_ss();
hsc->ss_avail = get_seg_avail(hsc->ss);
hsc->fs = get_kernel_fs();
hsc->fs_avail = get_seg_avail(hsc->fs);
hsc->gs = get_kernel_gs();
hsc->gs_avail = get_seg_avail(hsc->gs);
hsc->tr = get_kernel_tr_selector();
hsc->tr_avail = get_seg_avail(hsc->tr);
hsc->ldt = get_kernel_ldt();
hsc->efer = ia32_rdmsr(IA32_EFER);
hsc->sysenter_cs = ia32_rdmsr(IA32_SYSENTER_CS);
hsc->sysenter_eip = ia32_rdmsr(IA32_SYSENTER_EIP);
hsc->sysenter_esp = ia32_rdmsr(IA32_SYSENTER_ESP);
hsc->pat_msr = ia32_rdmsr(IA32_CR_PAT);
hsc->fs_msr = ia32_rdmsr(IA32_FS_BASE);
hsc->gs_msr = ia32_rdmsr(IA32_GS_BASE);
hsc->rflags = get_kernel_rflags();
if (pre) {
if (check_cs(hsc->cs)) {
hax_log(HAX_LOGD, "CS does not pass the check.\n");
dump_segment(hsc->cs);
// check_panic();
}
if (check_stack_seg(hsc->ss)) {
hax_log(HAX_LOGD, "SS does not pass the check.\n");
dump_segment(hsc->ss);
// check_panic();
}
if (check_fgs_seg(hsc->fs, 1)) {
hax_log(HAX_LOGD, "FS does not pass the check.\n");
dump_segment(hsc->fs);
// check_panic();
}
if (check_fgs_seg(hsc->gs, 0)) {
hax_log(HAX_LOGD, "GS does not pass the check.\n");
dump_segment(hsc->gs);
// check_panic();
}
if (check_data_seg(hsc->ds) || check_data_seg(hsc->es)) {
hax_log(HAX_LOGD, "DS or ES does not pass the check.\n");
dump_segment(hsc->ds);
dump_segment(hsc->es);
// check_panic();
}
if (check_tr_seg(hsc->tr)) {
hax_log(HAX_LOGD, "TR does not pass the check.\n");
dump_segment(hsc->tr);
// check_panic();
}
}
return 0;
}
static int dump_hsc_state(struct host_state_compare *hsc)
{
return 0;
}
int compare_host_state(struct vcpu_t *vcpu)
{
struct host_state_compare *pre, *post;
pre = &vcpu->hsc_pre;
post = &vcpu->hsc_post;
if (memcmp(pre, post, sizeof(struct host_state_compare))) {
hax_log(HAX_LOGD, "The previous and next is not same.\n");
dump_hsc_state(pre);
dump_hsc_state(post);
check_panic();
}
return 0;
}
#endif
static int is_emt64_msr(uint64_t entry)
{
int i = 0;
for (i = 0; i < NR_EMT64MSR; i++) {
if (entry == emt64_msr[i])
return 1;
}
return 0;
}
void save_guest_msr(struct vcpu_t *vcpu)
{
int i;
struct gstate *gstate = &vcpu->gstate;
bool em64t_support = cpu_has_feature(X86_FEATURE_EM64T);
for (i = 0; i < NR_GMSR; i++) {
gstate->gmsr[i].entry = gmsr_list[i];
if (em64t_support || !is_emt64_msr(gmsr_list[i])) {
gstate->gmsr[i].value = ia32_rdmsr(gstate->gmsr[i].entry);
}
}
if (cpu_has_feature(X86_FEATURE_RDTSCP)) {
gstate->tsc_aux = ia32_rdmsr(IA32_TSC_AUX);
}
if (!hax->apm_version)
return;
// APM v1: save IA32_PMCx and IA32_PERFEVTSELx
for (i = 0; i < (int)hax->apm_general_count; i++) {
uint32_t msr = (uint32_t)(IA32_PMC0 + i);
gstate->apm_pmc_msrs[i] = ia32_rdmsr(msr);
msr = (uint32_t)(IA32_PERFEVTSEL0 + i);
gstate->apm_pes_msrs[i] = ia32_rdmsr(msr);
}
}
void load_guest_msr(struct vcpu_t *vcpu)
{
int i;
struct gstate *gstate = &vcpu->gstate;
bool em64t_support = cpu_has_feature(X86_FEATURE_EM64T);
for (i = 0; i < NR_GMSR; i++) {
if (em64t_support || !is_emt64_msr(gstate->gmsr[i].entry)) {
ia32_wrmsr(gstate->gmsr[i].entry, gstate->gmsr[i].value);
}
}
if (cpu_has_feature(X86_FEATURE_RDTSCP)) {
ia32_wrmsr(IA32_TSC_AUX, gstate->tsc_aux);
}
if (!hax->apm_version)
return;
// APM v1: restore IA32_PMCx and IA32_PERFEVTSELx
for (i = 0; i < (int)hax->apm_general_count; i++) {
uint32_t msr = (uint32_t)(IA32_PMC0 + i);
ia32_wrmsr(msr, gstate->apm_pmc_msrs[i]);
msr = (uint32_t)(IA32_PERFEVTSEL0 + i);
ia32_wrmsr(msr, gstate->apm_pes_msrs[i]);
}