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brw_disasm.c
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/*
* Copyright © 2008 Keith Packard
*
* Permission to use, copy, modify, distribute, and sell this software and its
* documentation for any purpose is hereby granted without fee, provided that
* the above copyright notice appear in all copies and that both that copyright
* notice and this permission notice appear in supporting documentation, and
* that the name of the copyright holders not be used in advertising or
* publicity pertaining to distribution of the software without specific,
* written prior permission. The copyright holders make no representations
* about the suitability of this software for any purpose. It is provided "as
* is" without express or implied warranty.
*
* THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
* EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
* OF THIS SOFTWARE.
*/
#include <stdio.h>
#include <string.h>
#include <stdarg.h>
#include "brw_eu_defines.h"
#include "brw_inst.h"
#include "brw_shader.h"
#include "brw_reg.h"
#include "brw_inst.h"
#include "brw_eu.h"
#include "util/half_float.h"
bool
brw_has_jip(const struct intel_device_info *devinfo, enum opcode opcode)
{
if (devinfo->ver < 6)
return false;
return opcode == BRW_OPCODE_IF ||
opcode == BRW_OPCODE_ELSE ||
opcode == BRW_OPCODE_ENDIF ||
opcode == BRW_OPCODE_WHILE ||
opcode == BRW_OPCODE_BREAK ||
opcode == BRW_OPCODE_CONTINUE ||
opcode == BRW_OPCODE_HALT;
}
bool
brw_has_uip(const struct intel_device_info *devinfo, enum opcode opcode)
{
if (devinfo->ver < 6)
return false;
return (devinfo->ver >= 7 && opcode == BRW_OPCODE_IF) ||
(devinfo->ver >= 8 && opcode == BRW_OPCODE_ELSE) ||
opcode == BRW_OPCODE_BREAK ||
opcode == BRW_OPCODE_CONTINUE ||
opcode == BRW_OPCODE_HALT;
}
static bool
has_branch_ctrl(const struct intel_device_info *devinfo, enum opcode opcode)
{
if (devinfo->ver < 8)
return false;
return opcode == BRW_OPCODE_IF ||
opcode == BRW_OPCODE_ELSE;
/* opcode == BRW_OPCODE_GOTO; */
}
static bool
is_logic_instruction(unsigned opcode)
{
return opcode == BRW_OPCODE_AND ||
opcode == BRW_OPCODE_NOT ||
opcode == BRW_OPCODE_OR ||
opcode == BRW_OPCODE_XOR;
}
static bool
is_send(unsigned opcode)
{
return opcode == BRW_OPCODE_SEND ||
opcode == BRW_OPCODE_SENDC ||
opcode == BRW_OPCODE_SENDS ||
opcode == BRW_OPCODE_SENDSC;
}
static bool
is_split_send(UNUSED const struct intel_device_info *devinfo, unsigned opcode)
{
if (devinfo->ver >= 12)
return is_send(opcode);
else
return opcode == BRW_OPCODE_SENDS ||
opcode == BRW_OPCODE_SENDSC;
}
const char *const conditional_modifier[16] = {
[BRW_CONDITIONAL_NONE] = "",
[BRW_CONDITIONAL_Z] = ".z",
[BRW_CONDITIONAL_NZ] = ".nz",
[BRW_CONDITIONAL_G] = ".g",
[BRW_CONDITIONAL_GE] = ".ge",
[BRW_CONDITIONAL_L] = ".l",
[BRW_CONDITIONAL_LE] = ".le",
[BRW_CONDITIONAL_R] = ".r",
[BRW_CONDITIONAL_O] = ".o",
[BRW_CONDITIONAL_U] = ".u",
};
static const char *const m_negate[2] = {
[0] = "",
[1] = "-",
};
static const char *const _abs[2] = {
[0] = "",
[1] = "(abs)",
};
static const char *const m_bitnot[2] = { "", "~" };
static const char *const vert_stride[16] = {
[0] = "0",
[1] = "1",
[2] = "2",
[3] = "4",
[4] = "8",
[5] = "16",
[6] = "32",
[15] = "VxH",
};
static const char *const width[8] = {
[0] = "1",
[1] = "2",
[2] = "4",
[3] = "8",
[4] = "16",
};
static const char *const horiz_stride[4] = {
[0] = "0",
[1] = "1",
[2] = "2",
[3] = "4"
};
static const char *const chan_sel[4] = {
[0] = "x",
[1] = "y",
[2] = "z",
[3] = "w",
};
static const char *const debug_ctrl[2] = {
[0] = "",
[1] = ".breakpoint"
};
static const char *const saturate[2] = {
[0] = "",
[1] = ".sat"
};
static const char *const cmpt_ctrl[2] = {
[0] = "",
[1] = "compacted"
};
static const char *const accwr[2] = {
[0] = "",
[1] = "AccWrEnable"
};
static const char *const branch_ctrl[2] = {
[0] = "",
[1] = "BranchCtrl"
};
static const char *const wectrl[2] = {
[0] = "",
[1] = "WE_all"
};
static const char *const exec_size[8] = {
[0] = "1",
[1] = "2",
[2] = "4",
[3] = "8",
[4] = "16",
[5] = "32"
};
static const char *const pred_inv[2] = {
[0] = "+",
[1] = "-"
};
const char *const pred_ctrl_align16[16] = {
[1] = "",
[2] = ".x",
[3] = ".y",
[4] = ".z",
[5] = ".w",
[6] = ".any4h",
[7] = ".all4h",
};
static const char *const pred_ctrl_align1[16] = {
[BRW_PREDICATE_NORMAL] = "",
[BRW_PREDICATE_ALIGN1_ANYV] = ".anyv",
[BRW_PREDICATE_ALIGN1_ALLV] = ".allv",
[BRW_PREDICATE_ALIGN1_ANY2H] = ".any2h",
[BRW_PREDICATE_ALIGN1_ALL2H] = ".all2h",
[BRW_PREDICATE_ALIGN1_ANY4H] = ".any4h",
[BRW_PREDICATE_ALIGN1_ALL4H] = ".all4h",
[BRW_PREDICATE_ALIGN1_ANY8H] = ".any8h",
[BRW_PREDICATE_ALIGN1_ALL8H] = ".all8h",
[BRW_PREDICATE_ALIGN1_ANY16H] = ".any16h",
[BRW_PREDICATE_ALIGN1_ALL16H] = ".all16h",
[BRW_PREDICATE_ALIGN1_ANY32H] = ".any32h",
[BRW_PREDICATE_ALIGN1_ALL32H] = ".all32h",
};
static const char *const thread_ctrl[4] = {
[BRW_THREAD_NORMAL] = "",
[BRW_THREAD_ATOMIC] = "atomic",
[BRW_THREAD_SWITCH] = "switch",
};
static const char *const compr_ctrl[4] = {
[0] = "",
[1] = "sechalf",
[2] = "compr",
[3] = "compr4",
};
static const char *const dep_ctrl[4] = {
[0] = "",
[1] = "NoDDClr",
[2] = "NoDDChk",
[3] = "NoDDClr,NoDDChk",
};
static const char *const mask_ctrl[4] = {
[0] = "",
[1] = "nomask",
};
static const char *const access_mode[2] = {
[0] = "align1",
[1] = "align16",
};
static const char *const reg_file[4] = {
[0] = "A",
[1] = "g",
[2] = "m",
[3] = "imm",
};
static const char *const writemask[16] = {
[0x0] = ".",
[0x1] = ".x",
[0x2] = ".y",
[0x3] = ".xy",
[0x4] = ".z",
[0x5] = ".xz",
[0x6] = ".yz",
[0x7] = ".xyz",
[0x8] = ".w",
[0x9] = ".xw",
[0xa] = ".yw",
[0xb] = ".xyw",
[0xc] = ".zw",
[0xd] = ".xzw",
[0xe] = ".yzw",
[0xf] = "",
};
static const char *const end_of_thread[2] = {
[0] = "",
[1] = "EOT"
};
/* SFIDs on Gfx4-5 */
static const char *const gfx4_sfid[16] = {
[BRW_SFID_NULL] = "null",
[BRW_SFID_MATH] = "math",
[BRW_SFID_SAMPLER] = "sampler",
[BRW_SFID_MESSAGE_GATEWAY] = "gateway",
[BRW_SFID_DATAPORT_READ] = "read",
[BRW_SFID_DATAPORT_WRITE] = "write",
[BRW_SFID_URB] = "urb",
[BRW_SFID_THREAD_SPAWNER] = "thread_spawner",
[BRW_SFID_VME] = "vme",
};
static const char *const gfx6_sfid[16] = {
[BRW_SFID_NULL] = "null",
[BRW_SFID_MATH] = "math",
[BRW_SFID_SAMPLER] = "sampler",
[BRW_SFID_MESSAGE_GATEWAY] = "gateway",
[BRW_SFID_URB] = "urb",
[BRW_SFID_THREAD_SPAWNER] = "thread_spawner",
[GFX6_SFID_DATAPORT_SAMPLER_CACHE] = "dp_sampler",
[GFX6_SFID_DATAPORT_RENDER_CACHE] = "render",
[GFX6_SFID_DATAPORT_CONSTANT_CACHE] = "const",
[GFX7_SFID_DATAPORT_DATA_CACHE] = "data",
[GFX7_SFID_PIXEL_INTERPOLATOR] = "pixel interp",
[HSW_SFID_DATAPORT_DATA_CACHE_1] = "dp data 1",
[HSW_SFID_CRE] = "cre",
[GEN_RT_SFID_RAY_TRACE_ACCELERATOR] = "rt accel",
[GFX12_SFID_SLM] = "slm",
[GFX12_SFID_TGM] = "tgm",
[GFX12_SFID_UGM] = "ugm",
};
static const char *const gfx7_gateway_subfuncid[8] = {
[BRW_MESSAGE_GATEWAY_SFID_OPEN_GATEWAY] = "open",
[BRW_MESSAGE_GATEWAY_SFID_CLOSE_GATEWAY] = "close",
[BRW_MESSAGE_GATEWAY_SFID_FORWARD_MSG] = "forward msg",
[BRW_MESSAGE_GATEWAY_SFID_GET_TIMESTAMP] = "get timestamp",
[BRW_MESSAGE_GATEWAY_SFID_BARRIER_MSG] = "barrier msg",
[BRW_MESSAGE_GATEWAY_SFID_UPDATE_GATEWAY_STATE] = "update state",
[BRW_MESSAGE_GATEWAY_SFID_MMIO_READ_WRITE] = "mmio read/write",
};
static const char *const gfx4_dp_read_port_msg_type[4] = {
[0b00] = "OWord Block Read",
[0b01] = "OWord Dual Block Read",
[0b10] = "Media Block Read",
[0b11] = "DWord Scattered Read",
};
static const char *const g45_dp_read_port_msg_type[8] = {
[0b000] = "OWord Block Read",
[0b010] = "OWord Dual Block Read",
[0b100] = "Media Block Read",
[0b110] = "DWord Scattered Read",
[0b001] = "Render Target UNORM Read",
[0b011] = "AVC Loop Filter Read",
};
static const char *const dp_write_port_msg_type[8] = {
[0b000] = "OWord block write",
[0b001] = "OWord dual block write",
[0b010] = "media block write",
[0b011] = "DWord scattered write",
[0b100] = "RT write",
[0b101] = "streamed VB write",
[0b110] = "RT UNORM write", /* G45+ */
[0b111] = "flush render cache",
};
static const char *const dp_rc_msg_type_gfx6[16] = {
[BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ] = "OWORD block read",
[GFX6_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ] = "RT UNORM read",
[GFX6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ] = "OWORD dual block read",
[GFX6_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ] = "media block read",
[GFX6_DATAPORT_READ_MESSAGE_OWORD_UNALIGN_BLOCK_READ] =
"OWORD unaligned block read",
[GFX6_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ] = "DWORD scattered read",
[GFX6_DATAPORT_WRITE_MESSAGE_DWORD_ATOMIC_WRITE] = "DWORD atomic write",
[GFX6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE] = "OWORD block write",
[GFX6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE] =
"OWORD dual block write",
[GFX6_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE] = "media block write",
[GFX6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE] =
"DWORD scattered write",
[GFX6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE] = "RT write",
[GFX6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE] = "streamed VB write",
[GFX6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE] = "RT UNORM write",
};
static const char *const dp_rc_msg_type_gfx7[16] = {
[GFX7_DATAPORT_RC_MEDIA_BLOCK_READ] = "media block read",
[GFX7_DATAPORT_RC_TYPED_SURFACE_READ] = "typed surface read",
[GFX7_DATAPORT_RC_TYPED_ATOMIC_OP] = "typed atomic op",
[GFX7_DATAPORT_RC_MEMORY_FENCE] = "memory fence",
[GFX7_DATAPORT_RC_MEDIA_BLOCK_WRITE] = "media block write",
[GFX7_DATAPORT_RC_RENDER_TARGET_WRITE] = "RT write",
[GFX7_DATAPORT_RC_TYPED_SURFACE_WRITE] = "typed surface write"
};
static const char *const dp_rc_msg_type_gfx9[16] = {
[GFX9_DATAPORT_RC_RENDER_TARGET_WRITE] = "RT write",
[GFX9_DATAPORT_RC_RENDER_TARGET_READ] = "RT read"
};
static const char *const *
dp_rc_msg_type(const struct intel_device_info *devinfo)
{
return (devinfo->ver >= 9 ? dp_rc_msg_type_gfx9 :
devinfo->ver >= 7 ? dp_rc_msg_type_gfx7 :
devinfo->ver >= 6 ? dp_rc_msg_type_gfx6 :
dp_write_port_msg_type);
}
static const char *const m_rt_write_subtype[] = {
[0b000] = "SIMD16",
[0b001] = "SIMD16/RepData",
[0b010] = "SIMD8/DualSrcLow",
[0b011] = "SIMD8/DualSrcHigh",
[0b100] = "SIMD8",
[0b101] = "SIMD8/ImageWrite", /* Gfx6+ */
[0b111] = "SIMD16/RepData-111", /* no idea how this is different than 1 */
};
static const char *const dp_dc0_msg_type_gfx7[16] = {
[GFX7_DATAPORT_DC_OWORD_BLOCK_READ] = "DC OWORD block read",
[GFX7_DATAPORT_DC_UNALIGNED_OWORD_BLOCK_READ] =
"DC unaligned OWORD block read",
[GFX7_DATAPORT_DC_OWORD_DUAL_BLOCK_READ] = "DC OWORD dual block read",
[GFX7_DATAPORT_DC_DWORD_SCATTERED_READ] = "DC DWORD scattered read",
[GFX7_DATAPORT_DC_BYTE_SCATTERED_READ] = "DC byte scattered read",
[GFX7_DATAPORT_DC_UNTYPED_SURFACE_READ] = "DC untyped surface read",
[GFX7_DATAPORT_DC_UNTYPED_ATOMIC_OP] = "DC untyped atomic",
[GFX7_DATAPORT_DC_MEMORY_FENCE] = "DC mfence",
[GFX7_DATAPORT_DC_OWORD_BLOCK_WRITE] = "DC OWORD block write",
[GFX7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE] = "DC OWORD dual block write",
[GFX7_DATAPORT_DC_DWORD_SCATTERED_WRITE] = "DC DWORD scatterd write",
[GFX7_DATAPORT_DC_BYTE_SCATTERED_WRITE] = "DC byte scattered write",
[GFX7_DATAPORT_DC_UNTYPED_SURFACE_WRITE] = "DC untyped surface write",
};
static const char *const dp_oword_block_rw[8] = {
[BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW] = "1-low",
[BRW_DATAPORT_OWORD_BLOCK_1_OWORDHIGH] = "1-high",
[BRW_DATAPORT_OWORD_BLOCK_2_OWORDS] = "2",
[BRW_DATAPORT_OWORD_BLOCK_4_OWORDS] = "4",
[BRW_DATAPORT_OWORD_BLOCK_8_OWORDS] = "8",
};
static const char *const dp_dc1_msg_type_hsw[32] = {
[HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ] = "untyped surface read",
[HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP] = "DC untyped atomic op",
[HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2] =
"DC untyped 4x2 atomic op",
[HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_READ] = "DC media block read",
[HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ] = "DC typed surface read",
[HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP] = "DC typed atomic",
[HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2] = "DC typed 4x2 atomic op",
[HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE] = "DC untyped surface write",
[HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_WRITE] = "DC media block write",
[HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP] = "DC atomic counter op",
[HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP_SIMD4X2] =
"DC 4x2 atomic counter op",
[HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE] = "DC typed surface write",
[GFX9_DATAPORT_DC_PORT1_A64_SCATTERED_READ] = "DC A64 scattered read",
[GFX8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_READ] = "DC A64 untyped surface read",
[GFX8_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_OP] = "DC A64 untyped atomic op",
[GFX9_DATAPORT_DC_PORT1_A64_OWORD_BLOCK_READ] = "DC A64 oword block read",
[GFX9_DATAPORT_DC_PORT1_A64_OWORD_BLOCK_WRITE] = "DC A64 oword block write",
[GFX8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_WRITE] = "DC A64 untyped surface write",
[GFX8_DATAPORT_DC_PORT1_A64_SCATTERED_WRITE] = "DC A64 scattered write",
[GFX9_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_FLOAT_OP] =
"DC untyped atomic float op",
[GFX9_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_FLOAT_OP] =
"DC A64 untyped atomic float op",
[GFX12_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_HALF_INT_OP] =
"DC A64 untyped atomic half-integer op",
[GFX12_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_HALF_FLOAT_OP] =
"DC A64 untyped atomic half-float op",
};
static const char *const aop[16] = {
[BRW_AOP_AND] = "and",
[BRW_AOP_OR] = "or",
[BRW_AOP_XOR] = "xor",
[BRW_AOP_MOV] = "mov",
[BRW_AOP_INC] = "inc",
[BRW_AOP_DEC] = "dec",
[BRW_AOP_ADD] = "add",
[BRW_AOP_SUB] = "sub",
[BRW_AOP_REVSUB] = "revsub",
[BRW_AOP_IMAX] = "imax",
[BRW_AOP_IMIN] = "imin",
[BRW_AOP_UMAX] = "umax",
[BRW_AOP_UMIN] = "umin",
[BRW_AOP_CMPWR] = "cmpwr",
[BRW_AOP_PREDEC] = "predec",
};
static const char *const aop_float[5] = {
[BRW_AOP_FMAX] = "fmax",
[BRW_AOP_FMIN] = "fmin",
[BRW_AOP_FCMPWR] = "fcmpwr",
[BRW_AOP_FADD] = "fadd",
};
static const char * const pixel_interpolator_msg_types[4] = {
[GFX7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET] = "per_message_offset",
[GFX7_PIXEL_INTERPOLATOR_LOC_SAMPLE] = "sample_position",
[GFX7_PIXEL_INTERPOLATOR_LOC_CENTROID] = "centroid",
[GFX7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET] = "per_slot_offset",
};
static const char *const math_function[16] = {
[BRW_MATH_FUNCTION_INV] = "inv",
[BRW_MATH_FUNCTION_LOG] = "log",
[BRW_MATH_FUNCTION_EXP] = "exp",
[BRW_MATH_FUNCTION_SQRT] = "sqrt",
[BRW_MATH_FUNCTION_RSQ] = "rsq",
[BRW_MATH_FUNCTION_SIN] = "sin",
[BRW_MATH_FUNCTION_COS] = "cos",
[BRW_MATH_FUNCTION_SINCOS] = "sincos",
[BRW_MATH_FUNCTION_FDIV] = "fdiv",
[BRW_MATH_FUNCTION_POW] = "pow",
[BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER] = "intdivmod",
[BRW_MATH_FUNCTION_INT_DIV_QUOTIENT] = "intdiv",
[BRW_MATH_FUNCTION_INT_DIV_REMAINDER] = "intmod",
[GFX8_MATH_FUNCTION_INVM] = "invm",
[GFX8_MATH_FUNCTION_RSQRTM] = "rsqrtm",
};
static const char *const sync_function[16] = {
[TGL_SYNC_NOP] = "nop",
[TGL_SYNC_ALLRD] = "allrd",
[TGL_SYNC_ALLWR] = "allwr",
[TGL_SYNC_BAR] = "bar",
[TGL_SYNC_HOST] = "host",
};
static const char *const math_saturate[2] = {
[0] = "",
[1] = "sat"
};
static const char *const math_signed[2] = {
[0] = "",
[1] = "signed"
};
static const char *const math_scalar[2] = {
[0] = "",
[1] = "scalar"
};
static const char *const math_precision[2] = {
[0] = "",
[1] = "partial_precision"
};
static const char *const gfx5_urb_opcode[] = {
[0] = "urb_write",
[1] = "ff_sync",
};
static const char *const gfx7_urb_opcode[] = {
[BRW_URB_OPCODE_WRITE_HWORD] = "write HWord",
[BRW_URB_OPCODE_WRITE_OWORD] = "write OWord",
[BRW_URB_OPCODE_READ_HWORD] = "read HWord",
[BRW_URB_OPCODE_READ_OWORD] = "read OWord",
[GFX7_URB_OPCODE_ATOMIC_MOV] = "atomic mov", /* Gfx7+ */
[GFX7_URB_OPCODE_ATOMIC_INC] = "atomic inc", /* Gfx7+ */
[GFX8_URB_OPCODE_ATOMIC_ADD] = "atomic add", /* Gfx8+ */
[GFX8_URB_OPCODE_SIMD8_WRITE] = "SIMD8 write", /* Gfx8+ */
[GFX8_URB_OPCODE_SIMD8_READ] = "SIMD8 read", /* Gfx8+ */
[GFX125_URB_OPCODE_FENCE] = "fence", /* Gfx12.5+ */
/* [10-15] - reserved */
};
static const char *const urb_swizzle[4] = {
[BRW_URB_SWIZZLE_NONE] = "",
[BRW_URB_SWIZZLE_INTERLEAVE] = "interleave",
[BRW_URB_SWIZZLE_TRANSPOSE] = "transpose",
};
static const char *const urb_allocate[2] = {
[0] = "",
[1] = "allocate"
};
static const char *const urb_used[2] = {
[0] = "",
[1] = "used"
};
static const char *const urb_complete[2] = {
[0] = "",
[1] = "complete"
};
static const char *const gfx5_sampler_msg_type[] = {
[GFX5_SAMPLER_MESSAGE_SAMPLE] = "sample",
[GFX5_SAMPLER_MESSAGE_SAMPLE_BIAS] = "sample_b",
[GFX5_SAMPLER_MESSAGE_SAMPLE_LOD] = "sample_l",
[GFX5_SAMPLER_MESSAGE_SAMPLE_COMPARE] = "sample_c",
[GFX5_SAMPLER_MESSAGE_SAMPLE_DERIVS] = "sample_d",
[GFX5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE] = "sample_b_c",
[GFX5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE] = "sample_l_c",
[GFX5_SAMPLER_MESSAGE_SAMPLE_LD] = "ld",
[GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4] = "gather4",
[GFX5_SAMPLER_MESSAGE_LOD] = "lod",
[GFX5_SAMPLER_MESSAGE_SAMPLE_RESINFO] = "resinfo",
[GFX6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO] = "sampleinfo",
[GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C] = "gather4_c",
[GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO] = "gather4_po",
[GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C] = "gather4_po_c",
[HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE] = "sample_d_c",
[GFX9_SAMPLER_MESSAGE_SAMPLE_LZ] = "sample_lz",
[GFX9_SAMPLER_MESSAGE_SAMPLE_C_LZ] = "sample_c_lz",
[GFX9_SAMPLER_MESSAGE_SAMPLE_LD_LZ] = "ld_lz",
[GFX9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W] = "ld2dms_w",
[GFX7_SAMPLER_MESSAGE_SAMPLE_LD_MCS] = "ld_mcs",
[GFX7_SAMPLER_MESSAGE_SAMPLE_LD2DMS] = "ld2dms",
[GFX7_SAMPLER_MESSAGE_SAMPLE_LD2DSS] = "ld2dss",
};
static const char *const gfx5_sampler_simd_mode[7] = {
[BRW_SAMPLER_SIMD_MODE_SIMD4X2] = "SIMD4x2",
[BRW_SAMPLER_SIMD_MODE_SIMD8] = "SIMD8",
[BRW_SAMPLER_SIMD_MODE_SIMD16] = "SIMD16",
[BRW_SAMPLER_SIMD_MODE_SIMD32_64] = "SIMD32/64",
[GFX10_SAMPLER_SIMD_MODE_SIMD8H] = "SIMD8H",
[GFX10_SAMPLER_SIMD_MODE_SIMD16H] = "SIMD16H",
};
static const char *const sampler_target_format[4] = {
[0] = "F",
[2] = "UD",
[3] = "D"
};
static const char *const lsc_operation[] = {
[LSC_OP_LOAD] = "load",
[LSC_OP_LOAD_CMASK] = "load_cmask",
[LSC_OP_STORE] = "store",
[LSC_OP_STORE_CMASK] = "store_cmask",
[LSC_OP_FENCE] = "fence",
[LSC_OP_ATOMIC_INC] = "atomic_inc",
[LSC_OP_ATOMIC_DEC] = "atomic_dec",
[LSC_OP_ATOMIC_LOAD] = "atomic_load",
[LSC_OP_ATOMIC_STORE] = "atomic_store",
[LSC_OP_ATOMIC_ADD] = "atomic_add",
[LSC_OP_ATOMIC_SUB] = "atomic_sub",
[LSC_OP_ATOMIC_MIN] = "atomic_min",
[LSC_OP_ATOMIC_MAX] = "atomic_max",
[LSC_OP_ATOMIC_UMIN] = "atomic_umin",
[LSC_OP_ATOMIC_UMAX] = "atomic_umax",
[LSC_OP_ATOMIC_CMPXCHG] = "atomic_cmpxchg",
[LSC_OP_ATOMIC_FADD] = "atomic_fadd",
[LSC_OP_ATOMIC_FSUB] = "atomic_fsub",
[LSC_OP_ATOMIC_FMIN] = "atomic_fmin",
[LSC_OP_ATOMIC_FMAX] = "atomic_fmax",
[LSC_OP_ATOMIC_FCMPXCHG] = "atomic_fcmpxchg",
[LSC_OP_ATOMIC_AND] = "atomic_and",
[LSC_OP_ATOMIC_OR] = "atomic_or",
[LSC_OP_ATOMIC_XOR] = "atomic_xor",
};
static const char *const lsc_addr_surface_type[] = {
[LSC_ADDR_SURFTYPE_FLAT] = "flat",
[LSC_ADDR_SURFTYPE_BSS] = "bss",
[LSC_ADDR_SURFTYPE_SS] = "ss",
[LSC_ADDR_SURFTYPE_BTI] = "bti",
};
static const char* const lsc_fence_scope[] = {
[LSC_FENCE_THREADGROUP] = "threadgroup",
[LSC_FENCE_LOCAL] = "local",
[LSC_FENCE_TILE] = "tile",
[LSC_FENCE_GPU] = "gpu",
[LSC_FENCE_ALL_GPU] = "all_gpu",
[LSC_FENCE_SYSTEM_RELEASE] = "system_release",
[LSC_FENCE_SYSTEM_ACQUIRE] = "system_acquire",
};
static const char* const lsc_flush_type[] = {
[LSC_FLUSH_TYPE_NONE] = "none",
[LSC_FLUSH_TYPE_EVICT] = "evict",
[LSC_FLUSH_TYPE_INVALIDATE] = "invalidate",
[LSC_FLUSH_TYPE_DISCARD] = "discard",
[LSC_FLUSH_TYPE_CLEAN] = "clean",
[LSC_FLUSH_TYPE_L3ONLY] = "l3only",
[LSC_FLUSH_TYPE_NONE_6] = "none_6",
};
static const char* const lsc_addr_size[] = {
[LSC_ADDR_SIZE_A16] = "a16",
[LSC_ADDR_SIZE_A32] = "a32",
[LSC_ADDR_SIZE_A64] = "a64",
};
static const char* const lsc_backup_fence_routing[] = {
[LSC_NORMAL_ROUTING] = "normal_routing",
[LSC_ROUTE_TO_LSC] = "route_to_lsc",
};
static const char* const lsc_data_size[] = {
[LSC_DATA_SIZE_D8] = "d8",
[LSC_DATA_SIZE_D16] = "d16",
[LSC_DATA_SIZE_D32] = "d32",
[LSC_DATA_SIZE_D64] = "d64",
[LSC_DATA_SIZE_D8U32] = "d8u32",
[LSC_DATA_SIZE_D16U32] = "d16u32",
[LSC_DATA_SIZE_D16BF32] = "d16bf32",
};
static const char* const lsc_vect_size_str[] = {
[LSC_VECT_SIZE_V1] = "V1",
[LSC_VECT_SIZE_V2] = "V2",
[LSC_VECT_SIZE_V3] = "V3",
[LSC_VECT_SIZE_V4] = "V4",
[LSC_VECT_SIZE_V8] = "V8",
[LSC_VECT_SIZE_V16] = "V16",
[LSC_VECT_SIZE_V32] = "V32",
[LSC_VECT_SIZE_V64] = "V64",
};
static const char* const lsc_cmask_str[] = {
[LSC_CMASK_X] = "x",
[LSC_CMASK_Y] = "y",
[LSC_CMASK_XY] = "xy",
[LSC_CMASK_Z] = "z",
[LSC_CMASK_XZ] = "xz",
[LSC_CMASK_YZ] = "yz",
[LSC_CMASK_XYZ] = "xyz",
[LSC_CMASK_W] = "w",
[LSC_CMASK_XW] = "xw",
[LSC_CMASK_YW] = "yw",
[LSC_CMASK_XYW] = "xyw",
[LSC_CMASK_ZW] = "zw",
[LSC_CMASK_XZW] = "xzw",
[LSC_CMASK_YZW] = "yzw",
[LSC_CMASK_XYZW] = "xyzw",
};
static const char* const lsc_cache_load[] = {
[LSC_CACHE_LOAD_L1STATE_L3MOCS] = "L1STATE_L3MOCS",
[LSC_CACHE_LOAD_L1UC_L3UC] = "L1UC_L3UC",
[LSC_CACHE_LOAD_L1UC_L3C] = "L1UC_L3C",
[LSC_CACHE_LOAD_L1C_L3UC] = "L1C_L3UC",
[LSC_CACHE_LOAD_L1C_L3C] = "L1C_L3C",
[LSC_CACHE_LOAD_L1S_L3UC] = "L1S_L3UC",
[LSC_CACHE_LOAD_L1S_L3C] = "L1S_L3C",
[LSC_CACHE_LOAD_L1IAR_L3C] = "L1IAR_L3C",
};
static const char* const lsc_cache_store[] = {
[LSC_CACHE_STORE_L1STATE_L3MOCS] = "L1STATE_L3MOCS",
[LSC_CACHE_STORE_L1UC_L3UC] = "L1UC_L3UC",
[LSC_CACHE_STORE_L1UC_L3WB] = "L1UC_L3WB",
[LSC_CACHE_STORE_L1WT_L3UC] = "L1WT_L3UC",
[LSC_CACHE_STORE_L1WT_L3WB] = "L1WT_L3WB",
[LSC_CACHE_STORE_L1S_L3UC] = "L1S_L3UC",
[LSC_CACHE_STORE_L1S_L3WB] = "L1S_L3WB",
[LSC_CACHE_STORE_L1WB_L3WB] = "L1WB_L3WB",
};
static int column;
static int
string(FILE *file, const char *string)
{
fputs(string, file);
column += strlen(string);
return 0;
}
static int
format(FILE *f, const char *format, ...) PRINTFLIKE(2, 3);
static int
format(FILE *f, const char *format, ...)
{
char buf[1024];
va_list args;
va_start(args, format);
vsnprintf(buf, sizeof(buf) - 1, format, args);
va_end(args);
string(f, buf);
return 0;
}
static int
newline(FILE *f)
{
putc('\n', f);
column = 0;
return 0;
}
static int
pad(FILE *f, int c)
{
do
string(f, " ");
while (column < c);
return 0;
}
static int
control(FILE *file, const char *name, const char *const ctrl[],
unsigned id, int *space)
{
if (!ctrl[id]) {
fprintf(file, "*** invalid %s value %d ", name, id);
return 1;
}
if (ctrl[id][0]) {
if (space && *space)
string(file, " ");
string(file, ctrl[id]);
if (space)
*space = 1;
}
return 0;
}
static int
print_opcode(FILE *file, const struct brw_isa_info *isa,
enum opcode id)
{
const struct opcode_desc *desc = brw_opcode_desc(isa, id);
if (!desc) {
format(file, "*** invalid opcode value %d ", id);
return 1;
}
string(file, desc->name);
return 0;
}
static int
reg(FILE *file, unsigned _reg_file, unsigned _reg_nr)
{
int err = 0;
/* Clear the Compr4 instruction compression bit. */
if (_reg_file == BRW_MESSAGE_REGISTER_FILE)
_reg_nr &= ~BRW_MRF_COMPR4;
if (_reg_file == BRW_ARCHITECTURE_REGISTER_FILE) {
switch (_reg_nr & 0xf0) {
case BRW_ARF_NULL:
string(file, "null");
break;
case BRW_ARF_ADDRESS:
format(file, "a%d", _reg_nr & 0x0f);
break;
case BRW_ARF_ACCUMULATOR:
format(file, "acc%d", _reg_nr & 0x0f);
break;
case BRW_ARF_FLAG:
format(file, "f%d", _reg_nr & 0x0f);
break;
case BRW_ARF_MASK:
format(file, "mask%d", _reg_nr & 0x0f);
break;
case BRW_ARF_MASK_STACK:
format(file, "ms%d", _reg_nr & 0x0f);
break;
case BRW_ARF_MASK_STACK_DEPTH:
format(file, "msd%d", _reg_nr & 0x0f);
break;
case BRW_ARF_STATE:
format(file, "sr%d", _reg_nr & 0x0f);
break;
case BRW_ARF_CONTROL:
format(file, "cr%d", _reg_nr & 0x0f);
break;
case BRW_ARF_NOTIFICATION_COUNT:
format(file, "n%d", _reg_nr & 0x0f);
break;
case BRW_ARF_IP:
string(file, "ip");
return -1;
break;
case BRW_ARF_TDR:
format(file, "tdr0");
return -1;
case BRW_ARF_TIMESTAMP:
format(file, "tm%d", _reg_nr & 0x0f);
break;
default:
format(file, "ARF%d", _reg_nr);
break;
}
} else {
err |= control(file, "src reg file", reg_file, _reg_file, NULL);
format(file, "%d", _reg_nr);
}
return err;
}
static int
dest(FILE *file, const struct brw_isa_info *isa, const brw_inst *inst)
{
const struct intel_device_info *devinfo = isa->devinfo;
enum brw_reg_type type = brw_inst_dst_type(devinfo, inst);
unsigned elem_size = brw_reg_type_to_size(type);
int err = 0;
if (is_split_send(devinfo, brw_inst_opcode(isa, inst))) {
/* These are fixed for split sends */
type = BRW_REGISTER_TYPE_UD;
elem_size = 4;
if (devinfo->ver >= 12) {
err |= reg(file, brw_inst_send_dst_reg_file(devinfo, inst),
brw_inst_dst_da_reg_nr(devinfo, inst));
string(file, brw_reg_type_to_letters(type));
} else if (brw_inst_dst_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) {
err |= reg(file, brw_inst_send_dst_reg_file(devinfo, inst),
brw_inst_dst_da_reg_nr(devinfo, inst));
unsigned subreg_nr = brw_inst_dst_da16_subreg_nr(devinfo, inst);
if (subreg_nr)
format(file, ".%u", subreg_nr);
string(file, brw_reg_type_to_letters(type));
} else {
string(file, "g[a0");
if (brw_inst_dst_ia_subreg_nr(devinfo, inst))
format(file, ".%"PRIu64, brw_inst_dst_ia_subreg_nr(devinfo, inst) /
elem_size);
if (brw_inst_send_dst_ia16_addr_imm(devinfo, inst))
format(file, " %d", brw_inst_send_dst_ia16_addr_imm(devinfo, inst));
string(file, "]<");
string(file, brw_reg_type_to_letters(type));
}
} else if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
if (brw_inst_dst_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) {
err |= reg(file, brw_inst_dst_reg_file(devinfo, inst),
brw_inst_dst_da_reg_nr(devinfo, inst));
if (err == -1)
return 0;
if (brw_inst_dst_da1_subreg_nr(devinfo, inst))
format(file, ".%"PRIu64, brw_inst_dst_da1_subreg_nr(devinfo, inst) /
elem_size);
string(file, "<");
err |= control(file, "horiz stride", horiz_stride,
brw_inst_dst_hstride(devinfo, inst), NULL);
string(file, ">");
string(file, brw_reg_type_to_letters(type));
} else {
string(file, "g[a0");
if (brw_inst_dst_ia_subreg_nr(devinfo, inst))
format(file, ".%"PRIu64, brw_inst_dst_ia_subreg_nr(devinfo, inst) /
elem_size);
if (brw_inst_dst_ia1_addr_imm(devinfo, inst))
format(file, " %d", brw_inst_dst_ia1_addr_imm(devinfo, inst));
string(file, "]<");
err |= control(file, "horiz stride", horiz_stride,
brw_inst_dst_hstride(devinfo, inst), NULL);
string(file, ">");
string(file, brw_reg_type_to_letters(type));
}
} else {
if (brw_inst_dst_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) {
err |= reg(file, brw_inst_dst_reg_file(devinfo, inst),
brw_inst_dst_da_reg_nr(devinfo, inst));
if (err == -1)
return 0;
if (brw_inst_dst_da16_subreg_nr(devinfo, inst))
format(file, ".%u", 16 / elem_size);
string(file, "<1>");
err |= control(file, "writemask", writemask,
brw_inst_da16_writemask(devinfo, inst), NULL);
string(file, brw_reg_type_to_letters(type));
} else {
err = 1;
string(file, "Indirect align16 address mode not supported");
}
}
return 0;
}
static int
dest_3src(FILE *file, const struct intel_device_info *devinfo,
const brw_inst *inst)
{
bool is_align1 = brw_inst_3src_access_mode(devinfo, inst) == BRW_ALIGN_1;
int err = 0;
uint32_t reg_file;
unsigned subreg_nr;
enum brw_reg_type type;
if (devinfo->ver < 10 && is_align1)
return 0;
if (devinfo->ver == 6 && brw_inst_3src_a16_dst_reg_file(devinfo, inst))
reg_file = BRW_MESSAGE_REGISTER_FILE;
else if (devinfo->ver >= 12)
reg_file = brw_inst_3src_a1_dst_reg_file(devinfo, inst);
else if (is_align1 && brw_inst_3src_a1_dst_reg_file(devinfo, inst))
reg_file = BRW_ARCHITECTURE_REGISTER_FILE;
else
reg_file = BRW_GENERAL_REGISTER_FILE;
err |= reg(file, reg_file, brw_inst_3src_dst_reg_nr(devinfo, inst));
if (err == -1)
return 0;
if (is_align1) {