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Copy pathnv50_ir_lowering_nvc0.cpp
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nv50_ir_lowering_nvc0.cpp
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/*
* Copyright 2011 Christoph Bumiller
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "nv50_ir.h"
#include "nv50_ir_build_util.h"
#include "nv50_ir_target_nvc0.h"
#include "nv50_ir_lowering_nvc0.h"
#include <limits>
namespace nv50_ir {
#define QOP_ADD 0
#define QOP_SUBR 1
#define QOP_SUB 2
#define QOP_MOV2 3
// UL UR LL LR
#define QUADOP(q, r, s, t) \
((QOP_##q << 6) | (QOP_##r << 4) | \
(QOP_##s << 2) | (QOP_##t << 0))
void
NVC0LegalizeSSA::handleDIV(Instruction *i)
{
FlowInstruction *call;
int builtin;
bld.setPosition(i, false);
// Generate movs to the input regs for the call we want to generate
for (int s = 0; i->srcExists(s); ++s) {
Instruction *ld = i->getSrc(s)->getInsn();
// check if we are moving an immediate, propagate it in that case
if (!ld || ld->fixed || (ld->op != OP_LOAD && ld->op != OP_MOV) ||
!(ld->src(0).getFile() == FILE_IMMEDIATE))
bld.mkMovToReg(s, i->getSrc(s));
else {
assert(ld->getSrc(0) != NULL);
bld.mkMovToReg(s, ld->getSrc(0));
// Clear the src, to make code elimination possible here before we
// delete the instruction i later
i->setSrc(s, NULL);
if (ld->isDead())
delete_Instruction(prog, ld);
}
}
switch (i->dType) {
case TYPE_U32: builtin = NVC0_BUILTIN_DIV_U32; break;
case TYPE_S32: builtin = NVC0_BUILTIN_DIV_S32; break;
default:
return;
}
call = bld.mkFlow(OP_CALL, NULL, CC_ALWAYS, NULL);
bld.mkMovFromReg(i->getDef(0), i->op == OP_DIV ? 0 : 1);
bld.mkClobber(FILE_GPR, (i->op == OP_DIV) ? 0xe : 0xd, 2);
bld.mkClobber(FILE_PREDICATE, (i->dType == TYPE_S32) ? 0xf : 0x3, 0);
call->fixed = 1;
call->absolute = call->builtin = 1;
call->target.builtin = builtin;
delete_Instruction(prog, i);
}
void
NVC0LegalizeSSA::handleRCPRSQLib(Instruction *i, Value *src[])
{
FlowInstruction *call;
Value *def[2];
int builtin;
def[0] = bld.mkMovToReg(0, src[0])->getDef(0);
def[1] = bld.mkMovToReg(1, src[1])->getDef(0);
if (i->op == OP_RCP)
builtin = NVC0_BUILTIN_RCP_F64;
else
builtin = NVC0_BUILTIN_RSQ_F64;
call = bld.mkFlow(OP_CALL, NULL, CC_ALWAYS, NULL);
def[0] = bld.getSSA();
def[1] = bld.getSSA();
bld.mkMovFromReg(def[0], 0);
bld.mkMovFromReg(def[1], 1);
bld.mkClobber(FILE_GPR, 0x3fc, 2);
bld.mkClobber(FILE_PREDICATE, i->op == OP_RSQ ? 0x3 : 0x1, 0);
bld.mkOp2(OP_MERGE, TYPE_U64, i->getDef(0), def[0], def[1]);
call->fixed = 1;
call->absolute = call->builtin = 1;
call->target.builtin = builtin;
delete_Instruction(prog, i);
prog->fp64 = true;
}
void
NVC0LegalizeSSA::handleRCPRSQ(Instruction *i)
{
assert(i->dType == TYPE_F64);
// There are instructions that will compute the high 32 bits of the 64-bit
// float. We will just stick 0 in the bottom 32 bits.
bld.setPosition(i, false);
// 1. Take the source and it up.
Value *src[2], *dst[2], *def = i->getDef(0);
bld.mkSplit(src, 4, i->getSrc(0));
int chip = prog->getTarget()->getChipset();
if (chip >= NVISA_GK104_CHIPSET) {
handleRCPRSQLib(i, src);
return;
}
// 2. We don't care about the low 32 bits of the destination. Stick a 0 in.
dst[0] = bld.loadImm(NULL, 0);
dst[1] = bld.getSSA();
// 3. The new version of the instruction takes the high 32 bits of the
// source and outputs the high 32 bits of the destination.
i->setSrc(0, src[1]);
i->setDef(0, dst[1]);
i->setType(TYPE_F32);
i->subOp = NV50_IR_SUBOP_RCPRSQ_64H;
// 4. Recombine the two dst pieces back into the original destination.
bld.setPosition(i, true);
bld.mkOp2(OP_MERGE, TYPE_U64, def, dst[0], dst[1]);
}
void
NVC0LegalizeSSA::handleFTZ(Instruction *i)
{
// Only want to flush float inputs
assert(i->sType == TYPE_F32);
// If we're already flushing denorms (and NaN's) to zero, no need for this.
if (i->dnz)
return;
// Only certain classes of operations can flush
OpClass cls = prog->getTarget()->getOpClass(i->op);
if (cls != OPCLASS_ARITH && cls != OPCLASS_COMPARE &&
cls != OPCLASS_CONVERT)
return;
i->ftz = true;
}
void
NVC0LegalizeSSA::handleTEXLOD(TexInstruction *i)
{
if (i->tex.levelZero)
return;
ImmediateValue lod;
// The LOD argument comes right after the coordinates (before depth bias,
// offsets, etc).
int arg = i->tex.target.getArgCount();
// SM30+ stores the indirect handle as a separate arg, which comes before
// the LOD.
if (prog->getTarget()->getChipset() >= NVISA_GK104_CHIPSET &&
i->tex.rIndirectSrc >= 0)
arg++;
// SM20 stores indirect handle combined with array coordinate
if (prog->getTarget()->getChipset() < NVISA_GK104_CHIPSET &&
!i->tex.target.isArray() &&
i->tex.rIndirectSrc >= 0)
arg++;
if (!i->src(arg).getImmediate(lod) || !lod.isInteger(0))
return;
if (i->op == OP_TXL)
i->op = OP_TEX;
i->tex.levelZero = true;
i->moveSources(arg + 1, -1);
}
void
NVC0LegalizeSSA::handleShift(Instruction *lo)
{
Value *shift = lo->getSrc(1);
Value *dst64 = lo->getDef(0);
Value *src[2], *dst[2];
operation op = lo->op;
bld.setPosition(lo, false);
bld.mkSplit(src, 4, lo->getSrc(0));
// SM30 and prior don't have the fancy new SHF.L/R ops. So the logic has to
// be completely emulated. For SM35+, we can use the more directed SHF
// operations.
if (prog->getTarget()->getChipset() < NVISA_GK20A_CHIPSET) {
// The strategy here is to handle shifts >= 32 and less than 32 as
// separate parts.
//
// For SHL:
// If the shift is <= 32, then
// (HI,LO) << x = (HI << x | (LO >> (32 - x)), LO << x)
// If the shift is > 32, then
// (HI,LO) << x = (LO << (x - 32), 0)
//
// For SHR:
// If the shift is <= 32, then
// (HI,LO) >> x = (HI >> x, (HI << (32 - x)) | LO >> x)
// If the shift is > 32, then
// (HI,LO) >> x = (0, HI >> (x - 32))
//
// Note that on NVIDIA hardware, a shift > 32 yields a 0 value, which we
// can use to our advantage. Also note the structural similarities
// between the right/left cases. The main difference is swapping hi/lo
// on input and output.
Value *x32_minus_shift, *pred, *hi1, *hi2;
DataType type = isSignedIntType(lo->dType) ? TYPE_S32 : TYPE_U32;
operation antiop = op == OP_SHR ? OP_SHL : OP_SHR;
if (op == OP_SHR)
std::swap(src[0], src[1]);
bld.mkOp2(OP_ADD, TYPE_U32, (x32_minus_shift = bld.getSSA()), shift, bld.mkImm(0x20))
->src(0).mod = Modifier(NV50_IR_MOD_NEG);
bld.mkCmp(OP_SET, CC_LE, TYPE_U8, (pred = bld.getSSA(1, FILE_PREDICATE)),
TYPE_U32, shift, bld.mkImm(32));
// Compute HI (shift <= 32)
bld.mkOp2(OP_OR, TYPE_U32, (hi1 = bld.getSSA()),
bld.mkOp2v(op, TYPE_U32, bld.getSSA(), src[1], shift),
bld.mkOp2v(antiop, TYPE_U32, bld.getSSA(), src[0], x32_minus_shift))
->setPredicate(CC_P, pred);
// Compute LO (all shift values)
bld.mkOp2(op, type, (dst[0] = bld.getSSA()), src[0], shift);
// Compute HI (shift > 32)
bld.mkOp2(op, type, (hi2 = bld.getSSA()), src[0],
bld.mkOp1v(OP_NEG, TYPE_S32, bld.getSSA(), x32_minus_shift))
->setPredicate(CC_NOT_P, pred);
bld.mkOp2(OP_UNION, TYPE_U32, (dst[1] = bld.getSSA()), hi1, hi2);
if (op == OP_SHR)
std::swap(dst[0], dst[1]);
bld.mkOp2(OP_MERGE, TYPE_U64, dst64, dst[0], dst[1]);
delete_Instruction(prog, lo);
return;
}
Instruction *hi = new_Instruction(func, op, TYPE_U32);
lo->bb->insertAfter(lo, hi);
hi->sType = lo->sType;
lo->dType = TYPE_U32;
hi->setDef(0, (dst[1] = bld.getSSA()));
if (lo->op == OP_SHR)
hi->subOp |= NV50_IR_SUBOP_SHIFT_HIGH;
lo->setDef(0, (dst[0] = bld.getSSA()));
bld.setPosition(hi, true);
if (lo->op == OP_SHL)
std::swap(hi, lo);
hi->setSrc(0, new_ImmediateValue(prog, 0u));
hi->setSrc(1, shift);
hi->setSrc(2, lo->op == OP_SHL ? src[0] : src[1]);
lo->setSrc(0, src[0]);
lo->setSrc(1, shift);
lo->setSrc(2, src[1]);
bld.mkOp2(OP_MERGE, TYPE_U64, dst64, dst[0], dst[1]);
}
void
NVC0LegalizeSSA::handleSET(CmpInstruction *cmp)
{
DataType hTy = cmp->sType == TYPE_S64 ? TYPE_S32 : TYPE_U32;
Value *carry;
Value *src0[2], *src1[2];
bld.setPosition(cmp, false);
bld.mkSplit(src0, 4, cmp->getSrc(0));
bld.mkSplit(src1, 4, cmp->getSrc(1));
bld.mkOp2(OP_SUB, hTy, NULL, src0[0], src1[0])
->setFlagsDef(0, (carry = bld.getSSA(1, FILE_FLAGS)));
cmp->setFlagsSrc(cmp->srcCount(), carry);
cmp->setSrc(0, src0[1]);
cmp->setSrc(1, src1[1]);
cmp->sType = hTy;
}
void
NVC0LegalizeSSA::handleBREV(Instruction *i)
{
i->op = OP_EXTBF;
i->subOp = NV50_IR_SUBOP_EXTBF_REV;
i->setSrc(1, bld.mkImm(0x2000));
}
bool
NVC0LegalizeSSA::visit(Function *fn)
{
bld.setProgram(fn->getProgram());
return true;
}
bool
NVC0LegalizeSSA::visit(BasicBlock *bb)
{
Instruction *next;
for (Instruction *i = bb->getEntry(); i; i = next) {
next = i->next;
if (i->sType == TYPE_F32 && prog->getType() != Program::TYPE_COMPUTE)
handleFTZ(i);
switch (i->op) {
case OP_DIV:
case OP_MOD:
if (i->sType != TYPE_F32)
handleDIV(i);
break;
case OP_RCP:
case OP_RSQ:
if (i->dType == TYPE_F64)
handleRCPRSQ(i);
break;
case OP_TXL:
case OP_TXF:
handleTEXLOD(i->asTex());
break;
case OP_SHR:
case OP_SHL:
if (typeSizeof(i->sType) == 8)
handleShift(i);
break;
case OP_SET:
case OP_SET_AND:
case OP_SET_OR:
case OP_SET_XOR:
if (typeSizeof(i->sType) == 8 && i->sType != TYPE_F64)
handleSET(i->asCmp());
break;
case OP_BREV:
handleBREV(i);
break;
default:
break;
}
}
return true;
}
NVC0LegalizePostRA::NVC0LegalizePostRA(const Program *prog)
: rZero(NULL),
carry(NULL),
pOne(NULL),
needTexBar(prog->getTarget()->getChipset() >= 0xe0 &&
prog->getTarget()->getChipset() < 0x110)
{
}
bool
NVC0LegalizePostRA::insnDominatedBy(const Instruction *later,
const Instruction *early) const
{
if (early->bb == later->bb)
return early->serial < later->serial;
return later->bb->dominatedBy(early->bb);
}
void
NVC0LegalizePostRA::addTexUse(std::list<TexUse> &uses,
Instruction *usei, const Instruction *texi)
{
bool add = true;
bool dominated = insnDominatedBy(usei, texi);
// Uses before the tex have to all be included. Just because an earlier
// instruction dominates another instruction doesn't mean that there's no
// way to get from the tex to the later instruction. For example you could
// have nested loops, with the tex in the inner loop, and uses before it in
// both loops - even though the outer loop's instruction would dominate the
// inner's, we still want a texbar before the inner loop's instruction.
//
// However we can still use the eliding logic between uses dominated by the
// tex instruction, as that is unambiguously correct.
if (dominated) {
for (std::list<TexUse>::iterator it = uses.begin(); it != uses.end();) {
if (it->after) {
if (insnDominatedBy(usei, it->insn)) {
add = false;
break;
}
if (insnDominatedBy(it->insn, usei)) {
it = uses.erase(it);
continue;
}
}
++it;
}
}
if (add)
uses.push_back(TexUse(usei, texi, dominated));
}
// While it might be tempting to use the an algorithm that just looks at tex
// uses, not all texture results are guaranteed to be used on all paths. In
// the case where along some control flow path a texture result is never used,
// we might reuse that register for something else, creating a
// write-after-write hazard. So we have to manually look through all
// instructions looking for ones that reference the registers in question.
void
NVC0LegalizePostRA::findFirstUses(
Instruction *texi, std::list<TexUse> &uses)
{
int minGPR = texi->def(0).rep()->reg.data.id;
int maxGPR = minGPR + texi->def(0).rep()->reg.size / 4 - 1;
std::unordered_set<const BasicBlock *> visited;
findFirstUsesBB(minGPR, maxGPR, texi->next, texi, uses, visited);
}
void
NVC0LegalizePostRA::findFirstUsesBB(
int minGPR, int maxGPR, Instruction *start,
const Instruction *texi, std::list<TexUse> &uses,
std::unordered_set<const BasicBlock *> &visited)
{
const BasicBlock *bb = start->bb;
// We don't process the whole bb the first time around. This is correct,
// however we might be in a loop and hit this BB again, and need to process
// the full thing. So only mark a bb as visited if we processed it from the
// beginning.
if (start == bb->getEntry()) {
if (visited.find(bb) != visited.end())
return;
visited.insert(bb);
}
for (Instruction *insn = start; insn != bb->getExit(); insn = insn->next) {
if (insn->isNop())
continue;
for (int d = 0; insn->defExists(d); ++d) {
const Value *def = insn->def(d).rep();
if (insn->def(d).getFile() != FILE_GPR ||
def->reg.data.id + def->reg.size / 4 - 1 < minGPR ||
def->reg.data.id > maxGPR)
continue;
addTexUse(uses, insn, texi);
return;
}
for (int s = 0; insn->srcExists(s); ++s) {
const Value *src = insn->src(s).rep();
if (insn->src(s).getFile() != FILE_GPR ||
src->reg.data.id + src->reg.size / 4 - 1 < minGPR ||
src->reg.data.id > maxGPR)
continue;
addTexUse(uses, insn, texi);
return;
}
}
for (Graph::EdgeIterator ei = bb->cfg.outgoing(); !ei.end(); ei.next()) {
findFirstUsesBB(minGPR, maxGPR, BasicBlock::get(ei.getNode())->getEntry(),
texi, uses, visited);
}
}
// Texture barriers:
// This pass is a bit long and ugly and can probably be optimized.
//
// 1. obtain a list of TEXes and their outputs' first use(s)
// 2. calculate the barrier level of each first use (minimal number of TEXes,
// over all paths, between the TEX and the use in question)
// 3. for each barrier, if all paths from the source TEX to that barrier
// contain a barrier of lesser level, it can be culled
bool
NVC0LegalizePostRA::insertTextureBarriers(Function *fn)
{
std::list<TexUse> *uses;
std::vector<Instruction *> texes;
std::vector<int> bbFirstTex;
std::vector<int> bbFirstUse;
std::vector<int> texCounts;
std::vector<TexUse> useVec;
ArrayList insns;
fn->orderInstructions(insns);
texCounts.resize(fn->allBBlocks.getSize(), 0);
bbFirstTex.resize(fn->allBBlocks.getSize(), insns.getSize());
bbFirstUse.resize(fn->allBBlocks.getSize(), insns.getSize());
// tag BB CFG nodes by their id for later
for (ArrayList::Iterator i = fn->allBBlocks.iterator(); !i.end(); i.next()) {
BasicBlock *bb = reinterpret_cast<BasicBlock *>(i.get());
if (bb)
bb->cfg.tag = bb->getId();
}
// gather the first uses for each TEX
for (int i = 0; i < insns.getSize(); ++i) {
Instruction *tex = reinterpret_cast<Instruction *>(insns.get(i));
if (isTextureOp(tex->op)) {
texes.push_back(tex);
if (!texCounts.at(tex->bb->getId()))
bbFirstTex[tex->bb->getId()] = texes.size() - 1;
texCounts[tex->bb->getId()]++;
}
}
insns.clear();
if (texes.empty())
return false;
uses = new std::list<TexUse>[texes.size()];
if (!uses)
return false;
for (size_t i = 0; i < texes.size(); ++i) {
findFirstUses(texes[i], uses[i]);
}
// determine the barrier level at each use
for (size_t i = 0; i < texes.size(); ++i) {
for (std::list<TexUse>::iterator u = uses[i].begin(); u != uses[i].end();
++u) {
BasicBlock *tb = texes[i]->bb;
BasicBlock *ub = u->insn->bb;
if (tb == ub) {
u->level = 0;
for (size_t j = i + 1; j < texes.size() &&
texes[j]->bb == tb && texes[j]->serial < u->insn->serial;
++j)
u->level++;
} else {
u->level = fn->cfg.findLightestPathWeight(&tb->cfg,
&ub->cfg, texCounts);
if (u->level < 0) {
WARN("Failed to find path TEX -> TEXBAR\n");
u->level = 0;
continue;
}
// this counted all TEXes in the origin block, correct that
u->level -= i - bbFirstTex.at(tb->getId()) + 1 /* this TEX */;
// and did not count the TEXes in the destination block, add those
for (size_t j = bbFirstTex.at(ub->getId()); j < texes.size() &&
texes[j]->bb == ub && texes[j]->serial < u->insn->serial;
++j)
u->level++;
}
assert(u->level >= 0);
useVec.push_back(*u);
}
}
delete[] uses;
// insert the barriers
for (size_t i = 0; i < useVec.size(); ++i) {
Instruction *prev = useVec[i].insn->prev;
if (useVec[i].level < 0)
continue;
if (prev && prev->op == OP_TEXBAR) {
if (prev->subOp > useVec[i].level)
prev->subOp = useVec[i].level;
prev->setSrc(prev->srcCount(), useVec[i].tex->getDef(0));
} else {
Instruction *bar = new_Instruction(func, OP_TEXBAR, TYPE_NONE);
bar->fixed = 1;
bar->subOp = useVec[i].level;
// make use explicit to ease latency calculation
bar->setSrc(bar->srcCount(), useVec[i].tex->getDef(0));
useVec[i].insn->bb->insertBefore(useVec[i].insn, bar);
}
}
if (fn->getProgram()->optLevel < 3)
return true;
std::vector<Limits> limitT, limitB, limitS; // entry, exit, single
limitT.resize(fn->allBBlocks.getSize(), Limits(0, 0));
limitB.resize(fn->allBBlocks.getSize(), Limits(0, 0));
limitS.resize(fn->allBBlocks.getSize());
// cull unneeded barriers (should do that earlier, but for simplicity)
IteratorRef bi = fn->cfg.iteratorCFG();
// first calculate min/max outstanding TEXes for each BB
for (bi->reset(); !bi->end(); bi->next()) {
Graph::Node *n = reinterpret_cast<Graph::Node *>(bi->get());
BasicBlock *bb = BasicBlock::get(n);
int min = 0;
int max = std::numeric_limits<int>::max();
for (Instruction *i = bb->getFirst(); i; i = i->next) {
if (isTextureOp(i->op)) {
min++;
if (max < std::numeric_limits<int>::max())
max++;
} else
if (i->op == OP_TEXBAR) {
min = MIN2(min, i->subOp);
max = MIN2(max, i->subOp);
}
}
// limits when looking at an isolated block
limitS[bb->getId()].min = min;
limitS[bb->getId()].max = max;
}
// propagate the min/max values
for (unsigned int l = 0; l <= fn->loopNestingBound; ++l) {
for (bi->reset(); !bi->end(); bi->next()) {
Graph::Node *n = reinterpret_cast<Graph::Node *>(bi->get());
BasicBlock *bb = BasicBlock::get(n);
const int bbId = bb->getId();
for (Graph::EdgeIterator ei = n->incident(); !ei.end(); ei.next()) {
BasicBlock *in = BasicBlock::get(ei.getNode());
const int inId = in->getId();
limitT[bbId].min = MAX2(limitT[bbId].min, limitB[inId].min);
limitT[bbId].max = MAX2(limitT[bbId].max, limitB[inId].max);
}
// I just hope this is correct ...
if (limitS[bbId].max == std::numeric_limits<int>::max()) {
// no barrier
limitB[bbId].min = limitT[bbId].min + limitS[bbId].min;
limitB[bbId].max = limitT[bbId].max + limitS[bbId].min;
} else {
// block contained a barrier
limitB[bbId].min = MIN2(limitS[bbId].max,
limitT[bbId].min + limitS[bbId].min);
limitB[bbId].max = MIN2(limitS[bbId].max,
limitT[bbId].max + limitS[bbId].min);
}
}
}
// finally delete unnecessary barriers
for (bi->reset(); !bi->end(); bi->next()) {
Graph::Node *n = reinterpret_cast<Graph::Node *>(bi->get());
BasicBlock *bb = BasicBlock::get(n);
Instruction *prev = NULL;
Instruction *next;
int max = limitT[bb->getId()].max;
for (Instruction *i = bb->getFirst(); i; i = next) {
next = i->next;
if (i->op == OP_TEXBAR) {
if (i->subOp >= max) {
delete_Instruction(prog, i);
i = NULL;
} else {
max = i->subOp;
if (prev && prev->op == OP_TEXBAR && prev->subOp >= max) {
delete_Instruction(prog, prev);
prev = NULL;
}
}
} else
if (isTextureOp(i->op)) {
max++;
}
if (i && !i->isNop())
prev = i;
}
}
return true;
}
bool
NVC0LegalizePostRA::visit(Function *fn)
{
if (needTexBar)
insertTextureBarriers(fn);
rZero = new_LValue(fn, FILE_GPR);
pOne = new_LValue(fn, FILE_PREDICATE);
carry = new_LValue(fn, FILE_FLAGS);
rZero->reg.data.id = (prog->getTarget()->getChipset() >= NVISA_GK20A_CHIPSET) ? 255 : 63;
carry->reg.data.id = 0;
pOne->reg.data.id = 7;
return true;
}
void
NVC0LegalizePostRA::replaceZero(Instruction *i)
{
for (int s = 0; i->srcExists(s); ++s) {
if (s == 2 && i->op == OP_SUCLAMP)
continue;
if (s == 1 && i->op == OP_SHLADD)
continue;
ImmediateValue *imm = i->getSrc(s)->asImm();
if (imm) {
if (i->op == OP_SELP && s == 2) {
i->setSrc(s, pOne);
if (imm->reg.data.u64 == 0)
i->src(s).mod = i->src(s).mod ^ Modifier(NV50_IR_MOD_NOT);
} else if (imm->reg.data.u64 == 0) {
i->setSrc(s, rZero);
}
}
}
}
// replace CONT with BRA for single unconditional continue
bool
NVC0LegalizePostRA::tryReplaceContWithBra(BasicBlock *bb)
{
if (bb->cfg.incidentCount() != 2 || bb->getEntry()->op != OP_PRECONT)
return false;
Graph::EdgeIterator ei = bb->cfg.incident();
if (ei.getType() != Graph::Edge::BACK)
ei.next();
if (ei.getType() != Graph::Edge::BACK)
return false;
BasicBlock *contBB = BasicBlock::get(ei.getNode());
if (!contBB->getExit() || contBB->getExit()->op != OP_CONT ||
contBB->getExit()->getPredicate())
return false;
contBB->getExit()->op = OP_BRA;
bb->remove(bb->getEntry()); // delete PRECONT
ei.next();
assert(ei.end() || ei.getType() != Graph::Edge::BACK);
return true;
}
// replace branches to join blocks with join ops
void
NVC0LegalizePostRA::propagateJoin(BasicBlock *bb)
{
if (bb->getEntry()->op != OP_JOIN || bb->getEntry()->asFlow()->limit)
return;
for (Graph::EdgeIterator ei = bb->cfg.incident(); !ei.end(); ei.next()) {
BasicBlock *in = BasicBlock::get(ei.getNode());
Instruction *exit = in->getExit();
if (!exit) {
in->insertTail(new FlowInstruction(func, OP_JOIN, bb));
// there should always be a terminator instruction
WARN("inserted missing terminator in BB:%i\n", in->getId());
} else
if (exit->op == OP_BRA) {
exit->op = OP_JOIN;
exit->asFlow()->limit = 1; // must-not-propagate marker
}
}
bb->remove(bb->getEntry());
}
// replaces instructions which would end up as f2f or i2i with faster
// alternatives:
// - fabs(a) -> fadd(0, abs a)
// - fneg(a) -> fadd(neg 0, neg a)
// - ineg(a) -> iadd(0, neg a)
// - fneg(abs a) -> fadd(neg 0, neg abs a)
// - sat(a) -> sat add(0, a)
void
NVC0LegalizePostRA::replaceCvt(Instruction *cvt)
{
if (!isFloatType(cvt->sType) && typeSizeof(cvt->sType) != 4)
return;
if (cvt->sType != cvt->dType)
return;
// we could make it work, but in this case we have optimizations disabled
// and we don't really care either way.
if (cvt->src(0).getFile() != FILE_GPR &&
cvt->src(0).getFile() != FILE_MEMORY_CONST)
return;
Modifier mod0, mod1;
switch (cvt->op) {
case OP_ABS:
if (cvt->src(0).mod)
return;
if (!isFloatType(cvt->sType))
return;
mod0 = 0;
mod1 = NV50_IR_MOD_ABS;
break;
case OP_NEG:
if (!isFloatType(cvt->sType) && cvt->src(0).mod)
return;
if (isFloatType(cvt->sType) &&
(cvt->src(0).mod && cvt->src(0).mod != Modifier(NV50_IR_MOD_ABS)))
return;
mod0 = isFloatType(cvt->sType) ? NV50_IR_MOD_NEG : 0;
mod1 = cvt->src(0).mod == Modifier(NV50_IR_MOD_ABS) ?
NV50_IR_MOD_NEG_ABS : NV50_IR_MOD_NEG;
break;
case OP_SAT:
if (!isFloatType(cvt->sType) && cvt->src(0).mod.abs())
return;
mod0 = 0;
mod1 = cvt->src(0).mod;
cvt->saturate = true;
break;
default:
return;
}
cvt->op = OP_ADD;
cvt->moveSources(0, 1);
cvt->setSrc(0, rZero);
cvt->src(0).mod = mod0;
cvt->src(1).mod = mod1;
}
bool
NVC0LegalizePostRA::visit(BasicBlock *bb)
{
Instruction *i, *next;
// remove pseudo operations and non-fixed no-ops, split 64 bit operations
for (i = bb->getFirst(); i; i = next) {
next = i->next;
if (i->op == OP_EMIT || i->op == OP_RESTART) {
if (!i->getDef(0)->refCount())
i->setDef(0, NULL);
if (i->src(0).getFile() == FILE_IMMEDIATE)
i->setSrc(0, rZero); // initial value must be 0
replaceZero(i);
} else
if (i->isNop()) {
bb->remove(i);
} else
if (i->op == OP_BAR && i->subOp == NV50_IR_SUBOP_BAR_SYNC &&
prog->getType() != Program::TYPE_COMPUTE) {
// It seems like barriers are never required for tessellation since
// the warp size is 32, and there are always at most 32 tcs threads.
bb->remove(i);
} else
if (i->op == OP_LOAD && i->subOp == NV50_IR_SUBOP_LDC_IS) {
int offset = i->src(0).get()->reg.data.offset;
if (abs(offset) >= 0x10000)
i->src(0).get()->reg.fileIndex += offset >> 16;
i->src(0).get()->reg.data.offset = (int)(short)offset;
} else {
// TODO: Move this to before register allocation for operations that
// need the $c register !
if (typeSizeof(i->sType) == 8 || typeSizeof(i->dType) == 8) {
Instruction *hi;
hi = BuildUtil::split64BitOpPostRA(func, i, rZero, carry);
if (hi)
next = hi;
}
if (i->op != OP_MOV && i->op != OP_PFETCH)
replaceZero(i);
if (i->op == OP_SAT || i->op == OP_NEG || i->op == OP_ABS)
replaceCvt(i);
}
}
if (!bb->getEntry())
return true;
if (!tryReplaceContWithBra(bb))
propagateJoin(bb);
return true;
}
NVC0LoweringPass::NVC0LoweringPass(Program *prog) : targ(prog->getTarget()),
gpEmitAddress(NULL)
{
bld.setProgram(prog);
}
bool
NVC0LoweringPass::visit(Function *fn)
{
if (prog->getType() == Program::TYPE_GEOMETRY) {
assert(!strncmp(fn->getName(), "MAIN", 4));
// TODO: when we generate actual functions pass this value along somehow
bld.setPosition(BasicBlock::get(fn->cfg.getRoot()), false);
gpEmitAddress = bld.loadImm(NULL, 0)->asLValue();
if (fn->cfgExit) {
bld.setPosition(BasicBlock::get(fn->cfgExit)->getExit(), false);
if (prog->getTarget()->getChipset() >= NVISA_GV100_CHIPSET)
bld.mkOp1(OP_FINAL, TYPE_NONE, NULL, gpEmitAddress)->fixed = 1;
bld.mkMovToReg(0, gpEmitAddress);
}
}
return true;
}
bool
NVC0LoweringPass::visit(BasicBlock *bb)
{
return true;
}
inline Value *
NVC0LoweringPass::loadTexHandle(Value *ptr, unsigned int slot)
{
uint8_t b = prog->driver->io.auxCBSlot;
uint32_t off = prog->driver->io.texBindBase + slot * 4;
if (ptr)
ptr = bld.mkOp2v(OP_SHL, TYPE_U32, bld.getSSA(), ptr, bld.mkImm(2));
return bld.
mkLoadv(TYPE_U32, bld.mkSymbol(FILE_MEMORY_CONST, b, TYPE_U32, off), ptr);
}
// move array source to first slot, convert to u16, add indirections
bool
NVC0LoweringPass::handleTEX(TexInstruction *i)
{
const int dim = i->tex.target.getDim() + i->tex.target.isCube();
const int arg = i->tex.target.getArgCount();
const int lyr = arg - (i->tex.target.isMS() ? 2 : 1);
const int chipset = prog->getTarget()->getChipset();
/* Only normalize in the non-explicit derivatives case. For explicit
* derivatives, this is handled in handleManualTXD.
*/
if (i->tex.target.isCube() && i->dPdx[0].get() == NULL) {
Value *src[3], *val;
int c;
for (c = 0; c < 3; ++c)
src[c] = bld.mkOp1v(OP_ABS, TYPE_F32, bld.getSSA(), i->getSrc(c));
val = bld.getScratch();
bld.mkOp2(OP_MAX, TYPE_F32, val, src[0], src[1]);
bld.mkOp2(OP_MAX, TYPE_F32, val, src[2], val);
bld.mkOp1(OP_RCP, TYPE_F32, val, val);
for (c = 0; c < 3; ++c) {
i->setSrc(c, bld.mkOp2v(OP_MUL, TYPE_F32, bld.getSSA(),
i->getSrc(c), val));
}
}
// Arguments to the TEX instruction are a little insane. Even though the
// encoding is identical between SM20 and SM30, the arguments mean
// different things between Fermi and Kepler+. A lot of arguments are
// optional based on flags passed to the instruction. This summarizes the
// order of things.
//
// Fermi:
// array/indirect
// coords
// sample
// lod bias
// depth compare
// offsets:
// - tg4: 8 bits each, either 2 (1 offset reg) or 8 (2 offset reg)
// - other: 4 bits each, single reg
//
// Kepler+:
// indirect handle
// array (+ offsets for txd in upper 16 bits)
// coords
// sample
// lod bias
// depth compare
// offsets (same as fermi, except txd which takes it with array)
//
// Maxwell (tex):
// array
// coords
// indirect handle
// sample
// lod bias
// depth compare
// offsets
//
// Maxwell (txd):
// indirect handle
// coords
// array + offsets
// derivatives
if (chipset >= NVISA_GK104_CHIPSET) {
if (i->tex.rIndirectSrc >= 0 || i->tex.sIndirectSrc >= 0) {
// XXX this ignores tsc, and assumes a 1:1 mapping
assert(i->tex.rIndirectSrc >= 0);
if (!i->tex.bindless) {