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R600/SI: Enable subreg liveness by default
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228228 91177308-0d34-0410-b5e6-96231b3b80d8
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@tstellarAMD
tstellarAMD committed Feb 4, 2015
1 parent 18c8166 commit 26bfda9
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Showing 5 changed files with 42 additions and 38 deletions.
4 changes: 4 additions & 0 deletions lib/Target/R600/AMDGPUSubtarget.h
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Original file line number Diff line number Diff line change
Expand Up @@ -243,6 +243,10 @@ class AMDGPUSubtarget : public AMDGPUGenSubtargetInfo {
// FIXME: Not sure what this is for other subtagets.
llvm_unreachable("do not know max waves per CU for this subtarget.");
}

bool enableSubRegLiveness() const override {
return true;
}
};

} // End namespace llvm
Expand Down
60 changes: 30 additions & 30 deletions test/CodeGen/R600/imm.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -24,87 +24,87 @@ entry:

; CHECK-LABEL: {{^}}store_inline_imm_0.0_f32
; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0{{$}}
; CHECK-NEXT: buffer_store_dword [[REG]]
; CHECK: buffer_store_dword [[REG]]
define void @store_inline_imm_0.0_f32(float addrspace(1)* %out) {
store float 0.0, float addrspace(1)* %out
ret void
}

; CHECK-LABEL: {{^}}store_imm_neg_0.0_f32
; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80000000
; CHECK-NEXT: buffer_store_dword [[REG]]
; CHECK: buffer_store_dword [[REG]]
define void @store_imm_neg_0.0_f32(float addrspace(1)* %out) {
store float -0.0, float addrspace(1)* %out
ret void
}

; CHECK-LABEL: {{^}}store_inline_imm_0.5_f32
; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0.5{{$}}
; CHECK-NEXT: buffer_store_dword [[REG]]
; CHECK: buffer_store_dword [[REG]]
define void @store_inline_imm_0.5_f32(float addrspace(1)* %out) {
store float 0.5, float addrspace(1)* %out
ret void
}

; CHECK-LABEL: {{^}}store_inline_imm_m_0.5_f32
; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], -0.5{{$}}
; CHECK-NEXT: buffer_store_dword [[REG]]
; CHECK: buffer_store_dword [[REG]]
define void @store_inline_imm_m_0.5_f32(float addrspace(1)* %out) {
store float -0.5, float addrspace(1)* %out
ret void
}

; CHECK-LABEL: {{^}}store_inline_imm_1.0_f32
; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0{{$}}
; CHECK-NEXT: buffer_store_dword [[REG]]
; CHECK: buffer_store_dword [[REG]]
define void @store_inline_imm_1.0_f32(float addrspace(1)* %out) {
store float 1.0, float addrspace(1)* %out
ret void
}

; CHECK-LABEL: {{^}}store_inline_imm_m_1.0_f32
; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], -1.0{{$}}
; CHECK-NEXT: buffer_store_dword [[REG]]
; CHECK: buffer_store_dword [[REG]]
define void @store_inline_imm_m_1.0_f32(float addrspace(1)* %out) {
store float -1.0, float addrspace(1)* %out
ret void
}

; CHECK-LABEL: {{^}}store_inline_imm_2.0_f32
; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 2.0{{$}}
; CHECK-NEXT: buffer_store_dword [[REG]]
; CHECK: buffer_store_dword [[REG]]
define void @store_inline_imm_2.0_f32(float addrspace(1)* %out) {
store float 2.0, float addrspace(1)* %out
ret void
}

; CHECK-LABEL: {{^}}store_inline_imm_m_2.0_f32
; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], -2.0{{$}}
; CHECK-NEXT: buffer_store_dword [[REG]]
; CHECK: buffer_store_dword [[REG]]
define void @store_inline_imm_m_2.0_f32(float addrspace(1)* %out) {
store float -2.0, float addrspace(1)* %out
ret void
}

; CHECK-LABEL: {{^}}store_inline_imm_4.0_f32
; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 4.0{{$}}
; CHECK-NEXT: buffer_store_dword [[REG]]
; CHECK: buffer_store_dword [[REG]]
define void @store_inline_imm_4.0_f32(float addrspace(1)* %out) {
store float 4.0, float addrspace(1)* %out
ret void
}

; CHECK-LABEL: {{^}}store_inline_imm_m_4.0_f32
; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], -4.0{{$}}
; CHECK-NEXT: buffer_store_dword [[REG]]
; CHECK: buffer_store_dword [[REG]]
define void @store_inline_imm_m_4.0_f32(float addrspace(1)* %out) {
store float -4.0, float addrspace(1)* %out
ret void
}

; CHECK-LABEL: {{^}}store_literal_imm_f32:
; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0x45800000
; CHECK-NEXT: buffer_store_dword [[REG]]
; CHECK: buffer_store_dword [[REG]]
define void @store_literal_imm_f32(float addrspace(1)* %out) {
store float 4096.0, float addrspace(1)* %out
ret void
Expand All @@ -113,7 +113,7 @@ define void @store_literal_imm_f32(float addrspace(1)* %out) {
; CHECK-LABEL: {{^}}add_inline_imm_0.0_f32
; CHECK: s_load_dword [[VAL:s[0-9]+]]
; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 0, [[VAL]]{{$}}
; CHECK-NEXT: buffer_store_dword [[REG]]
; CHECK: buffer_store_dword [[REG]]
define void @add_inline_imm_0.0_f32(float addrspace(1)* %out, float %x) {
%y = fadd float %x, 0.0
store float %y, float addrspace(1)* %out
Expand All @@ -123,7 +123,7 @@ define void @add_inline_imm_0.0_f32(float addrspace(1)* %out, float %x) {
; CHECK-LABEL: {{^}}add_inline_imm_0.5_f32
; CHECK: s_load_dword [[VAL:s[0-9]+]]
; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 0.5, [[VAL]]{{$}}
; CHECK-NEXT: buffer_store_dword [[REG]]
; CHECK: buffer_store_dword [[REG]]
define void @add_inline_imm_0.5_f32(float addrspace(1)* %out, float %x) {
%y = fadd float %x, 0.5
store float %y, float addrspace(1)* %out
Expand All @@ -133,7 +133,7 @@ define void @add_inline_imm_0.5_f32(float addrspace(1)* %out, float %x) {
; CHECK-LABEL: {{^}}add_inline_imm_neg_0.5_f32
; CHECK: s_load_dword [[VAL:s[0-9]+]]
; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -0.5, [[VAL]]{{$}}
; CHECK-NEXT: buffer_store_dword [[REG]]
; CHECK: buffer_store_dword [[REG]]
define void @add_inline_imm_neg_0.5_f32(float addrspace(1)* %out, float %x) {
%y = fadd float %x, -0.5
store float %y, float addrspace(1)* %out
Expand All @@ -143,7 +143,7 @@ define void @add_inline_imm_neg_0.5_f32(float addrspace(1)* %out, float %x) {
; CHECK-LABEL: {{^}}add_inline_imm_1.0_f32
; CHECK: s_load_dword [[VAL:s[0-9]+]]
; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 1.0, [[VAL]]{{$}}
; CHECK-NEXT: buffer_store_dword [[REG]]
; CHECK: buffer_store_dword [[REG]]
define void @add_inline_imm_1.0_f32(float addrspace(1)* %out, float %x) {
%y = fadd float %x, 1.0
store float %y, float addrspace(1)* %out
Expand All @@ -153,7 +153,7 @@ define void @add_inline_imm_1.0_f32(float addrspace(1)* %out, float %x) {
; CHECK-LABEL: {{^}}add_inline_imm_neg_1.0_f32
; CHECK: s_load_dword [[VAL:s[0-9]+]]
; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -1.0, [[VAL]]{{$}}
; CHECK-NEXT: buffer_store_dword [[REG]]
; CHECK: buffer_store_dword [[REG]]
define void @add_inline_imm_neg_1.0_f32(float addrspace(1)* %out, float %x) {
%y = fadd float %x, -1.0
store float %y, float addrspace(1)* %out
Expand All @@ -163,7 +163,7 @@ define void @add_inline_imm_neg_1.0_f32(float addrspace(1)* %out, float %x) {
; CHECK-LABEL: {{^}}add_inline_imm_2.0_f32
; CHECK: s_load_dword [[VAL:s[0-9]+]]
; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 2.0, [[VAL]]{{$}}
; CHECK-NEXT: buffer_store_dword [[REG]]
; CHECK: buffer_store_dword [[REG]]
define void @add_inline_imm_2.0_f32(float addrspace(1)* %out, float %x) {
%y = fadd float %x, 2.0
store float %y, float addrspace(1)* %out
Expand All @@ -173,7 +173,7 @@ define void @add_inline_imm_2.0_f32(float addrspace(1)* %out, float %x) {
; CHECK-LABEL: {{^}}add_inline_imm_neg_2.0_f32
; CHECK: s_load_dword [[VAL:s[0-9]+]]
; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -2.0, [[VAL]]{{$}}
; CHECK-NEXT: buffer_store_dword [[REG]]
; CHECK: buffer_store_dword [[REG]]
define void @add_inline_imm_neg_2.0_f32(float addrspace(1)* %out, float %x) {
%y = fadd float %x, -2.0
store float %y, float addrspace(1)* %out
Expand All @@ -183,7 +183,7 @@ define void @add_inline_imm_neg_2.0_f32(float addrspace(1)* %out, float %x) {
; CHECK-LABEL: {{^}}add_inline_imm_4.0_f32
; CHECK: s_load_dword [[VAL:s[0-9]+]]
; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 4.0, [[VAL]]{{$}}
; CHECK-NEXT: buffer_store_dword [[REG]]
; CHECK: buffer_store_dword [[REG]]
define void @add_inline_imm_4.0_f32(float addrspace(1)* %out, float %x) {
%y = fadd float %x, 4.0
store float %y, float addrspace(1)* %out
Expand All @@ -193,7 +193,7 @@ define void @add_inline_imm_4.0_f32(float addrspace(1)* %out, float %x) {
; CHECK-LABEL: {{^}}add_inline_imm_neg_4.0_f32
; CHECK: s_load_dword [[VAL:s[0-9]+]]
; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -4.0, [[VAL]]{{$}}
; CHECK-NEXT: buffer_store_dword [[REG]]
; CHECK: buffer_store_dword [[REG]]
define void @add_inline_imm_neg_4.0_f32(float addrspace(1)* %out, float %x) {
%y = fadd float %x, -4.0
store float %y, float addrspace(1)* %out
Expand All @@ -203,7 +203,7 @@ define void @add_inline_imm_neg_4.0_f32(float addrspace(1)* %out, float %x) {
; CHECK-LABEL: @commute_add_inline_imm_0.5_f32
; CHECK: buffer_load_dword [[VAL:v[0-9]+]]
; CHECK: v_add_f32_e32 [[REG:v[0-9]+]], 0.5, [[VAL]]
; CHECK-NEXT: buffer_store_dword [[REG]]
; CHECK: buffer_store_dword [[REG]]
define void @commute_add_inline_imm_0.5_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
%x = load float addrspace(1)* %in
%y = fadd float %x, 0.5
Expand All @@ -214,7 +214,7 @@ define void @commute_add_inline_imm_0.5_f32(float addrspace(1)* %out, float addr
; CHECK-LABEL: @commute_add_literal_f32
; CHECK: buffer_load_dword [[VAL:v[0-9]+]]
; CHECK: v_add_f32_e32 [[REG:v[0-9]+]], 0x44800000, [[VAL]]
; CHECK-NEXT: buffer_store_dword [[REG]]
; CHECK: buffer_store_dword [[REG]]
define void @commute_add_literal_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
%x = load float addrspace(1)* %in
%y = fadd float %x, 1024.0
Expand All @@ -225,7 +225,7 @@ define void @commute_add_literal_f32(float addrspace(1)* %out, float addrspace(1
; CHECK-LABEL: {{^}}add_inline_imm_1_f32
; CHECK: s_load_dword [[VAL:s[0-9]+]]
; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 1, [[VAL]]{{$}}
; CHECK-NEXT: buffer_store_dword [[REG]]
; CHECK: buffer_store_dword [[REG]]
define void @add_inline_imm_1_f32(float addrspace(1)* %out, float %x) {
%y = fadd float %x, 0x36a0000000000000
store float %y, float addrspace(1)* %out
Expand All @@ -235,7 +235,7 @@ define void @add_inline_imm_1_f32(float addrspace(1)* %out, float %x) {
; CHECK-LABEL: {{^}}add_inline_imm_2_f32
; CHECK: s_load_dword [[VAL:s[0-9]+]]
; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 2, [[VAL]]{{$}}
; CHECK-NEXT: buffer_store_dword [[REG]]
; CHECK: buffer_store_dword [[REG]]
define void @add_inline_imm_2_f32(float addrspace(1)* %out, float %x) {
%y = fadd float %x, 0x36b0000000000000
store float %y, float addrspace(1)* %out
Expand All @@ -245,7 +245,7 @@ define void @add_inline_imm_2_f32(float addrspace(1)* %out, float %x) {
; CHECK-LABEL: {{^}}add_inline_imm_16_f32
; CHECK: s_load_dword [[VAL:s[0-9]+]]
; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 16, [[VAL]]
; CHECK-NEXT: buffer_store_dword [[REG]]
; CHECK: buffer_store_dword [[REG]]
define void @add_inline_imm_16_f32(float addrspace(1)* %out, float %x) {
%y = fadd float %x, 0x36e0000000000000
store float %y, float addrspace(1)* %out
Expand All @@ -255,7 +255,7 @@ define void @add_inline_imm_16_f32(float addrspace(1)* %out, float %x) {
; CHECK-LABEL: {{^}}add_inline_imm_neg_1_f32
; CHECK: s_load_dword [[VAL:s[0-9]+]]
; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -1, [[VAL]]
; CHECK-NEXT: buffer_store_dword [[REG]]
; CHECK: buffer_store_dword [[REG]]
define void @add_inline_imm_neg_1_f32(float addrspace(1)* %out, float %x) {
%y = fadd float %x, 0xffffffffe0000000
store float %y, float addrspace(1)* %out
Expand All @@ -265,7 +265,7 @@ define void @add_inline_imm_neg_1_f32(float addrspace(1)* %out, float %x) {
; CHECK-LABEL: {{^}}add_inline_imm_neg_2_f32
; CHECK: s_load_dword [[VAL:s[0-9]+]]
; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -2, [[VAL]]
; CHECK-NEXT: buffer_store_dword [[REG]]
; CHECK: buffer_store_dword [[REG]]
define void @add_inline_imm_neg_2_f32(float addrspace(1)* %out, float %x) {
%y = fadd float %x, 0xffffffffc0000000
store float %y, float addrspace(1)* %out
Expand All @@ -275,7 +275,7 @@ define void @add_inline_imm_neg_2_f32(float addrspace(1)* %out, float %x) {
; CHECK-LABEL: {{^}}add_inline_imm_neg_16_f32
; CHECK: s_load_dword [[VAL:s[0-9]+]]
; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -16, [[VAL]]
; CHECK-NEXT: buffer_store_dword [[REG]]
; CHECK: buffer_store_dword [[REG]]
define void @add_inline_imm_neg_16_f32(float addrspace(1)* %out, float %x) {
%y = fadd float %x, 0xfffffffe00000000
store float %y, float addrspace(1)* %out
Expand All @@ -285,7 +285,7 @@ define void @add_inline_imm_neg_16_f32(float addrspace(1)* %out, float %x) {
; CHECK-LABEL: {{^}}add_inline_imm_63_f32
; CHECK: s_load_dword [[VAL:s[0-9]+]]
; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 63, [[VAL]]
; CHECK-NEXT: buffer_store_dword [[REG]]
; CHECK: buffer_store_dword [[REG]]
define void @add_inline_imm_63_f32(float addrspace(1)* %out, float %x) {
%y = fadd float %x, 0x36ff800000000000
store float %y, float addrspace(1)* %out
Expand All @@ -295,7 +295,7 @@ define void @add_inline_imm_63_f32(float addrspace(1)* %out, float %x) {
; CHECK-LABEL: {{^}}add_inline_imm_64_f32
; CHECK: s_load_dword [[VAL:s[0-9]+]]
; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 64, [[VAL]]
; CHECK-NEXT: buffer_store_dword [[REG]]
; CHECK: buffer_store_dword [[REG]]
define void @add_inline_imm_64_f32(float addrspace(1)* %out, float %x) {
%y = fadd float %x, 0x3700000000000000
store float %y, float addrspace(1)* %out
Expand Down
2 changes: 1 addition & 1 deletion test/CodeGen/R600/llvm.AMDGPU.class.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -472,7 +472,7 @@ define void @test_no_fold_or_class_f32_0(i32 addrspace(1)* %out, float addrspace
; SI-LABEL: {{^}}test_class_0_f32:
; SI-NOT: v_cmp_class
; SI: v_mov_b32_e32 [[RESULT:v[0-9]+]], 0{{$}}
; SI-NEXT: buffer_store_dword [[RESULT]]
; SI: buffer_store_dword [[RESULT]]
; SI: s_endpgm
define void @test_class_0_f32(i32 addrspace(1)* %out, float %a) #0 {
%result = call i1 @llvm.AMDGPU.class.f32(float %a, i32 0) #1
Expand Down
6 changes: 3 additions & 3 deletions test/CodeGen/R600/setcc-opt.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -199,7 +199,7 @@ define void @cmp_sext_k_neg1_i8_arg(i1 addrspace(1)* %out, i8 %b) nounwind {

; FUNC-LABEL: {{^}}cmp_zext_k_neg1:
; SI: v_mov_b32_e32 [[RESULT:v[0-9]+]], 1{{$}}
; SI-NEXT: buffer_store_byte [[RESULT]]
; SI: buffer_store_byte [[RESULT]]
; SI: s_endpgm
define void @cmp_zext_k_neg1(i1 addrspace(1)* %out, i8 %b) nounwind {
%b.ext = zext i8 %b to i32
Expand All @@ -210,7 +210,7 @@ define void @cmp_zext_k_neg1(i1 addrspace(1)* %out, i8 %b) nounwind {

; FUNC-LABEL: {{^}}zext_bool_icmp_ne_k:
; SI: v_mov_b32_e32 [[RESULT:v[0-9]+]], 1{{$}}
; SI-NEXT: buffer_store_byte [[RESULT]]
; SI: buffer_store_byte [[RESULT]]
; SI-NEXT: s_endpgm
define void @zext_bool_icmp_ne_k(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
%icmp0 = icmp ne i32 %a, %b
Expand All @@ -222,7 +222,7 @@ define void @zext_bool_icmp_ne_k(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind

; FUNC-LABEL: {{^}}zext_bool_icmp_eq_k:
; SI: v_mov_b32_e32 [[RESULT:v[0-9]+]], 0{{$}}
; SI-NEXT: buffer_store_byte [[RESULT]]
; SI: buffer_store_byte [[RESULT]]
; SI-NEXT: s_endpgm
define void @zext_bool_icmp_eq_k(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
%icmp0 = icmp ne i32 %a, %b
Expand Down
8 changes: 4 additions & 4 deletions test/CodeGen/R600/trunc-cmp-constant.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -34,7 +34,7 @@ define void @zextload_i1_to_i32_trunc_cmp_eq_0(i1 addrspace(1)* %out, i1 addrspa

; FUNC-LABEL: {{^}}sextload_i1_to_i32_trunc_cmp_eq_1:
; SI: v_mov_b32_e32 [[RESULT:v[0-9]+]], 0{{$}}
; SI-NEXT: buffer_store_byte [[RESULT]]
; SI: buffer_store_byte [[RESULT]]
define void @sextload_i1_to_i32_trunc_cmp_eq_1(i1 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind {
%load = load i1 addrspace(1)* %in
%ext = sext i1 %load to i32
Expand Down Expand Up @@ -69,7 +69,7 @@ define void @sextload_i1_to_i32_trunc_cmp_eq_neg1(i1 addrspace(1)* %out, i1 addr

; FUNC-LABEL: {{^}}zextload_i1_to_i32_trunc_cmp_eq_neg1:
; SI: v_mov_b32_e32 [[RESULT:v[0-9]+]], 0{{$}}
; SI-NEXT: buffer_store_byte [[RESULT]]
; SI: buffer_store_byte [[RESULT]]
define void @zextload_i1_to_i32_trunc_cmp_eq_neg1(i1 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind {
%load = load i1 addrspace(1)* %in
%ext = zext i1 %load to i32
Expand Down Expand Up @@ -105,7 +105,7 @@ define void @zextload_i1_to_i32_trunc_cmp_ne_0(i1 addrspace(1)* %out, i1 addrspa

; FUNC-LABEL: {{^}}sextload_i1_to_i32_trunc_cmp_ne_1:
; SI: v_mov_b32_e32 [[RESULT:v[0-9]+]], 1{{$}}
; SI-NEXT: buffer_store_byte [[RESULT]]
; SI: buffer_store_byte [[RESULT]]
define void @sextload_i1_to_i32_trunc_cmp_ne_1(i1 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind {
%load = load i1 addrspace(1)* %in
%ext = sext i1 %load to i32
Expand Down Expand Up @@ -146,7 +146,7 @@ define void @sextload_i1_to_i32_trunc_cmp_ne_neg1(i1 addrspace(1)* %out, i1 addr

; FUNC-LABEL: {{^}}zextload_i1_to_i32_trunc_cmp_ne_neg1:
; SI: v_mov_b32_e32 [[RESULT:v[0-9]+]], 1{{$}}
; SI-NEXT: buffer_store_byte [[RESULT]]
; SI: buffer_store_byte [[RESULT]]
define void @zextload_i1_to_i32_trunc_cmp_ne_neg1(i1 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind {
%load = load i1 addrspace(1)* %in
%ext = zext i1 %load to i32
Expand Down

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