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rme96.c
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/*
* ALSA driver for RME Digi96, Digi96/8 and Digi96/8 PRO/PAD/PST audio
* interfaces
*
* Copyright (c) 2000, 2001 Anders Torger <[email protected]>
*
* Thanks to Henk Hesselink <[email protected]> for the analog volume control
* code.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/module.h>
#include <linux/vmalloc.h>
#include <linux/io.h>
#include <sound/core.h>
#include <sound/info.h>
#include <sound/control.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/asoundef.h>
#include <sound/initval.h>
/* note, two last pcis should be equal, it is not a bug */
MODULE_AUTHOR("Anders Torger <[email protected]>");
MODULE_DESCRIPTION("RME Digi96, Digi96/8, Digi96/8 PRO, Digi96/8 PST, "
"Digi96/8 PAD");
MODULE_LICENSE("GPL");
MODULE_SUPPORTED_DEVICE("{{RME,Digi96},"
"{RME,Digi96/8},"
"{RME,Digi96/8 PRO},"
"{RME,Digi96/8 PST},"
"{RME,Digi96/8 PAD}}");
static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
module_param_array(index, int, NULL, 0444);
MODULE_PARM_DESC(index, "Index value for RME Digi96 soundcard.");
module_param_array(id, charp, NULL, 0444);
MODULE_PARM_DESC(id, "ID string for RME Digi96 soundcard.");
module_param_array(enable, bool, NULL, 0444);
MODULE_PARM_DESC(enable, "Enable RME Digi96 soundcard.");
/*
* Defines for RME Digi96 series, from internal RME reference documents
* dated 12.01.00
*/
#define RME96_SPDIF_NCHANNELS 2
/* Playback and capture buffer size */
#define RME96_BUFFER_SIZE 0x10000
/* IO area size */
#define RME96_IO_SIZE 0x60000
/* IO area offsets */
#define RME96_IO_PLAY_BUFFER 0x0
#define RME96_IO_REC_BUFFER 0x10000
#define RME96_IO_CONTROL_REGISTER 0x20000
#define RME96_IO_ADDITIONAL_REG 0x20004
#define RME96_IO_CONFIRM_PLAY_IRQ 0x20008
#define RME96_IO_CONFIRM_REC_IRQ 0x2000C
#define RME96_IO_SET_PLAY_POS 0x40000
#define RME96_IO_RESET_PLAY_POS 0x4FFFC
#define RME96_IO_SET_REC_POS 0x50000
#define RME96_IO_RESET_REC_POS 0x5FFFC
#define RME96_IO_GET_PLAY_POS 0x20000
#define RME96_IO_GET_REC_POS 0x30000
/* Write control register bits */
#define RME96_WCR_START (1 << 0)
#define RME96_WCR_START_2 (1 << 1)
#define RME96_WCR_GAIN_0 (1 << 2)
#define RME96_WCR_GAIN_1 (1 << 3)
#define RME96_WCR_MODE24 (1 << 4)
#define RME96_WCR_MODE24_2 (1 << 5)
#define RME96_WCR_BM (1 << 6)
#define RME96_WCR_BM_2 (1 << 7)
#define RME96_WCR_ADAT (1 << 8)
#define RME96_WCR_FREQ_0 (1 << 9)
#define RME96_WCR_FREQ_1 (1 << 10)
#define RME96_WCR_DS (1 << 11)
#define RME96_WCR_PRO (1 << 12)
#define RME96_WCR_EMP (1 << 13)
#define RME96_WCR_SEL (1 << 14)
#define RME96_WCR_MASTER (1 << 15)
#define RME96_WCR_PD (1 << 16)
#define RME96_WCR_INP_0 (1 << 17)
#define RME96_WCR_INP_1 (1 << 18)
#define RME96_WCR_THRU_0 (1 << 19)
#define RME96_WCR_THRU_1 (1 << 20)
#define RME96_WCR_THRU_2 (1 << 21)
#define RME96_WCR_THRU_3 (1 << 22)
#define RME96_WCR_THRU_4 (1 << 23)
#define RME96_WCR_THRU_5 (1 << 24)
#define RME96_WCR_THRU_6 (1 << 25)
#define RME96_WCR_THRU_7 (1 << 26)
#define RME96_WCR_DOLBY (1 << 27)
#define RME96_WCR_MONITOR_0 (1 << 28)
#define RME96_WCR_MONITOR_1 (1 << 29)
#define RME96_WCR_ISEL (1 << 30)
#define RME96_WCR_IDIS (1 << 31)
#define RME96_WCR_BITPOS_GAIN_0 2
#define RME96_WCR_BITPOS_GAIN_1 3
#define RME96_WCR_BITPOS_FREQ_0 9
#define RME96_WCR_BITPOS_FREQ_1 10
#define RME96_WCR_BITPOS_INP_0 17
#define RME96_WCR_BITPOS_INP_1 18
#define RME96_WCR_BITPOS_MONITOR_0 28
#define RME96_WCR_BITPOS_MONITOR_1 29
/* Read control register bits */
#define RME96_RCR_AUDIO_ADDR_MASK 0xFFFF
#define RME96_RCR_IRQ_2 (1 << 16)
#define RME96_RCR_T_OUT (1 << 17)
#define RME96_RCR_DEV_ID_0 (1 << 21)
#define RME96_RCR_DEV_ID_1 (1 << 22)
#define RME96_RCR_LOCK (1 << 23)
#define RME96_RCR_VERF (1 << 26)
#define RME96_RCR_F0 (1 << 27)
#define RME96_RCR_F1 (1 << 28)
#define RME96_RCR_F2 (1 << 29)
#define RME96_RCR_AUTOSYNC (1 << 30)
#define RME96_RCR_IRQ (1 << 31)
#define RME96_RCR_BITPOS_F0 27
#define RME96_RCR_BITPOS_F1 28
#define RME96_RCR_BITPOS_F2 29
/* Additional register bits */
#define RME96_AR_WSEL (1 << 0)
#define RME96_AR_ANALOG (1 << 1)
#define RME96_AR_FREQPAD_0 (1 << 2)
#define RME96_AR_FREQPAD_1 (1 << 3)
#define RME96_AR_FREQPAD_2 (1 << 4)
#define RME96_AR_PD2 (1 << 5)
#define RME96_AR_DAC_EN (1 << 6)
#define RME96_AR_CLATCH (1 << 7)
#define RME96_AR_CCLK (1 << 8)
#define RME96_AR_CDATA (1 << 9)
#define RME96_AR_BITPOS_F0 2
#define RME96_AR_BITPOS_F1 3
#define RME96_AR_BITPOS_F2 4
/* Monitor tracks */
#define RME96_MONITOR_TRACKS_1_2 0
#define RME96_MONITOR_TRACKS_3_4 1
#define RME96_MONITOR_TRACKS_5_6 2
#define RME96_MONITOR_TRACKS_7_8 3
/* Attenuation */
#define RME96_ATTENUATION_0 0
#define RME96_ATTENUATION_6 1
#define RME96_ATTENUATION_12 2
#define RME96_ATTENUATION_18 3
/* Input types */
#define RME96_INPUT_OPTICAL 0
#define RME96_INPUT_COAXIAL 1
#define RME96_INPUT_INTERNAL 2
#define RME96_INPUT_XLR 3
#define RME96_INPUT_ANALOG 4
/* Clock modes */
#define RME96_CLOCKMODE_SLAVE 0
#define RME96_CLOCKMODE_MASTER 1
#define RME96_CLOCKMODE_WORDCLOCK 2
/* Block sizes in bytes */
#define RME96_SMALL_BLOCK_SIZE 2048
#define RME96_LARGE_BLOCK_SIZE 8192
/* Volume control */
#define RME96_AD1852_VOL_BITS 14
#define RME96_AD1855_VOL_BITS 10
/* Defines for snd_rme96_trigger */
#define RME96_TB_START_PLAYBACK 1
#define RME96_TB_START_CAPTURE 2
#define RME96_TB_STOP_PLAYBACK 4
#define RME96_TB_STOP_CAPTURE 8
#define RME96_TB_RESET_PLAYPOS 16
#define RME96_TB_RESET_CAPTUREPOS 32
#define RME96_TB_CLEAR_PLAYBACK_IRQ 64
#define RME96_TB_CLEAR_CAPTURE_IRQ 128
#define RME96_RESUME_PLAYBACK (RME96_TB_START_PLAYBACK)
#define RME96_RESUME_CAPTURE (RME96_TB_START_CAPTURE)
#define RME96_RESUME_BOTH (RME96_RESUME_PLAYBACK \
| RME96_RESUME_CAPTURE)
#define RME96_START_PLAYBACK (RME96_TB_START_PLAYBACK \
| RME96_TB_RESET_PLAYPOS)
#define RME96_START_CAPTURE (RME96_TB_START_CAPTURE \
| RME96_TB_RESET_CAPTUREPOS)
#define RME96_START_BOTH (RME96_START_PLAYBACK \
| RME96_START_CAPTURE)
#define RME96_STOP_PLAYBACK (RME96_TB_STOP_PLAYBACK \
| RME96_TB_CLEAR_PLAYBACK_IRQ)
#define RME96_STOP_CAPTURE (RME96_TB_STOP_CAPTURE \
| RME96_TB_CLEAR_CAPTURE_IRQ)
#define RME96_STOP_BOTH (RME96_STOP_PLAYBACK \
| RME96_STOP_CAPTURE)
struct rme96 {
spinlock_t lock;
int irq;
unsigned long port;
void __iomem *iobase;
u32 wcreg; /* cached write control register value */
u32 wcreg_spdif; /* S/PDIF setup */
u32 wcreg_spdif_stream; /* S/PDIF setup (temporary) */
u32 rcreg; /* cached read control register value */
u32 areg; /* cached additional register value */
u16 vol[2]; /* cached volume of analog output */
u8 rev; /* card revision number */
#ifdef CONFIG_PM_SLEEP
u32 playback_pointer;
u32 capture_pointer;
void *playback_suspend_buffer;
void *capture_suspend_buffer;
#endif
struct snd_pcm_substream *playback_substream;
struct snd_pcm_substream *capture_substream;
int playback_frlog; /* log2 of framesize */
int capture_frlog;
size_t playback_periodsize; /* in bytes, zero if not used */
size_t capture_periodsize; /* in bytes, zero if not used */
struct snd_card *card;
struct snd_pcm *spdif_pcm;
struct snd_pcm *adat_pcm;
struct pci_dev *pci;
struct snd_kcontrol *spdif_ctl;
};
static const struct pci_device_id snd_rme96_ids[] = {
{ PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96), 0, },
{ PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8), 0, },
{ PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PRO), 0, },
{ PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST), 0, },
{ 0, }
};
MODULE_DEVICE_TABLE(pci, snd_rme96_ids);
#define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START)
#define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2)
#define RME96_HAS_ANALOG_IN(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
#define RME96_HAS_ANALOG_OUT(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO || \
(rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
#define RME96_DAC_IS_1852(rme96) (RME96_HAS_ANALOG_OUT(rme96) && (rme96)->rev >= 4)
#define RME96_DAC_IS_1855(rme96) (((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && (rme96)->rev < 4) || \
((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO && (rme96)->rev == 2))
#define RME96_185X_MAX_OUT(rme96) ((1 << (RME96_DAC_IS_1852(rme96) ? RME96_AD1852_VOL_BITS : RME96_AD1855_VOL_BITS)) - 1)
static int
snd_rme96_playback_prepare(struct snd_pcm_substream *substream);
static int
snd_rme96_capture_prepare(struct snd_pcm_substream *substream);
static int
snd_rme96_playback_trigger(struct snd_pcm_substream *substream,
int cmd);
static int
snd_rme96_capture_trigger(struct snd_pcm_substream *substream,
int cmd);
static snd_pcm_uframes_t
snd_rme96_playback_pointer(struct snd_pcm_substream *substream);
static snd_pcm_uframes_t
snd_rme96_capture_pointer(struct snd_pcm_substream *substream);
static void snd_rme96_proc_init(struct rme96 *rme96);
static int
snd_rme96_create_switches(struct snd_card *card,
struct rme96 *rme96);
static int
snd_rme96_getinputtype(struct rme96 *rme96);
static inline unsigned int
snd_rme96_playback_ptr(struct rme96 *rme96)
{
return (readl(rme96->iobase + RME96_IO_GET_PLAY_POS)
& RME96_RCR_AUDIO_ADDR_MASK) >> rme96->playback_frlog;
}
static inline unsigned int
snd_rme96_capture_ptr(struct rme96 *rme96)
{
return (readl(rme96->iobase + RME96_IO_GET_REC_POS)
& RME96_RCR_AUDIO_ADDR_MASK) >> rme96->capture_frlog;
}
static int
snd_rme96_playback_silence(struct snd_pcm_substream *substream,
int channel, unsigned long pos, unsigned long count)
{
struct rme96 *rme96 = snd_pcm_substream_chip(substream);
memset_io(rme96->iobase + RME96_IO_PLAY_BUFFER + pos,
0, count);
return 0;
}
static int
snd_rme96_playback_copy(struct snd_pcm_substream *substream,
int channel, unsigned long pos,
void __user *src, unsigned long count)
{
struct rme96 *rme96 = snd_pcm_substream_chip(substream);
return copy_from_user_toio(rme96->iobase + RME96_IO_PLAY_BUFFER + pos,
src, count);
}
static int
snd_rme96_playback_copy_kernel(struct snd_pcm_substream *substream,
int channel, unsigned long pos,
void *src, unsigned long count)
{
struct rme96 *rme96 = snd_pcm_substream_chip(substream);
memcpy_toio(rme96->iobase + RME96_IO_PLAY_BUFFER + pos, src, count);
return 0;
}
static int
snd_rme96_capture_copy(struct snd_pcm_substream *substream,
int channel, unsigned long pos,
void __user *dst, unsigned long count)
{
struct rme96 *rme96 = snd_pcm_substream_chip(substream);
return copy_to_user_fromio(dst,
rme96->iobase + RME96_IO_REC_BUFFER + pos,
count);
}
static int
snd_rme96_capture_copy_kernel(struct snd_pcm_substream *substream,
int channel, unsigned long pos,
void *dst, unsigned long count)
{
struct rme96 *rme96 = snd_pcm_substream_chip(substream);
memcpy_fromio(dst, rme96->iobase + RME96_IO_REC_BUFFER + pos, count);
return 0;
}
/*
* Digital output capabilities (S/PDIF)
*/
static const struct snd_pcm_hardware snd_rme96_playback_spdif_info =
{
.info = (SNDRV_PCM_INFO_MMAP_IOMEM |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_SYNC_START |
SNDRV_PCM_INFO_RESUME |
SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_PAUSE),
.formats = (SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S32_LE),
.rates = (SNDRV_PCM_RATE_32000 |
SNDRV_PCM_RATE_44100 |
SNDRV_PCM_RATE_48000 |
SNDRV_PCM_RATE_64000 |
SNDRV_PCM_RATE_88200 |
SNDRV_PCM_RATE_96000),
.rate_min = 32000,
.rate_max = 96000,
.channels_min = 2,
.channels_max = 2,
.buffer_bytes_max = RME96_BUFFER_SIZE,
.period_bytes_min = RME96_SMALL_BLOCK_SIZE,
.period_bytes_max = RME96_LARGE_BLOCK_SIZE,
.periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
.periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
.fifo_size = 0,
};
/*
* Digital input capabilities (S/PDIF)
*/
static const struct snd_pcm_hardware snd_rme96_capture_spdif_info =
{
.info = (SNDRV_PCM_INFO_MMAP_IOMEM |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_SYNC_START |
SNDRV_PCM_INFO_RESUME |
SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_PAUSE),
.formats = (SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S32_LE),
.rates = (SNDRV_PCM_RATE_32000 |
SNDRV_PCM_RATE_44100 |
SNDRV_PCM_RATE_48000 |
SNDRV_PCM_RATE_64000 |
SNDRV_PCM_RATE_88200 |
SNDRV_PCM_RATE_96000),
.rate_min = 32000,
.rate_max = 96000,
.channels_min = 2,
.channels_max = 2,
.buffer_bytes_max = RME96_BUFFER_SIZE,
.period_bytes_min = RME96_SMALL_BLOCK_SIZE,
.period_bytes_max = RME96_LARGE_BLOCK_SIZE,
.periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
.periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
.fifo_size = 0,
};
/*
* Digital output capabilities (ADAT)
*/
static const struct snd_pcm_hardware snd_rme96_playback_adat_info =
{
.info = (SNDRV_PCM_INFO_MMAP_IOMEM |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_SYNC_START |
SNDRV_PCM_INFO_RESUME |
SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_PAUSE),
.formats = (SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S32_LE),
.rates = (SNDRV_PCM_RATE_44100 |
SNDRV_PCM_RATE_48000),
.rate_min = 44100,
.rate_max = 48000,
.channels_min = 8,
.channels_max = 8,
.buffer_bytes_max = RME96_BUFFER_SIZE,
.period_bytes_min = RME96_SMALL_BLOCK_SIZE,
.period_bytes_max = RME96_LARGE_BLOCK_SIZE,
.periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
.periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
.fifo_size = 0,
};
/*
* Digital input capabilities (ADAT)
*/
static const struct snd_pcm_hardware snd_rme96_capture_adat_info =
{
.info = (SNDRV_PCM_INFO_MMAP_IOMEM |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_SYNC_START |
SNDRV_PCM_INFO_RESUME |
SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_PAUSE),
.formats = (SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S32_LE),
.rates = (SNDRV_PCM_RATE_44100 |
SNDRV_PCM_RATE_48000),
.rate_min = 44100,
.rate_max = 48000,
.channels_min = 8,
.channels_max = 8,
.buffer_bytes_max = RME96_BUFFER_SIZE,
.period_bytes_min = RME96_SMALL_BLOCK_SIZE,
.period_bytes_max = RME96_LARGE_BLOCK_SIZE,
.periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
.periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
.fifo_size = 0,
};
/*
* The CDATA, CCLK and CLATCH bits can be used to write to the SPI interface
* of the AD1852 or AD1852 D/A converter on the board. CDATA must be set up
* on the falling edge of CCLK and be stable on the rising edge. The rising
* edge of CLATCH after the last data bit clocks in the whole data word.
* A fast processor could probably drive the SPI interface faster than the
* DAC can handle (3MHz for the 1855, unknown for the 1852). The udelay(1)
* limits the data rate to 500KHz and only causes a delay of 33 microsecs.
*
* NOTE: increased delay from 1 to 10, since there where problems setting
* the volume.
*/
static void
snd_rme96_write_SPI(struct rme96 *rme96, u16 val)
{
int i;
for (i = 0; i < 16; i++) {
if (val & 0x8000) {
rme96->areg |= RME96_AR_CDATA;
} else {
rme96->areg &= ~RME96_AR_CDATA;
}
rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CLATCH);
writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
udelay(10);
rme96->areg |= RME96_AR_CCLK;
writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
udelay(10);
val <<= 1;
}
rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CDATA);
rme96->areg |= RME96_AR_CLATCH;
writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
udelay(10);
rme96->areg &= ~RME96_AR_CLATCH;
writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
}
static void
snd_rme96_apply_dac_volume(struct rme96 *rme96)
{
if (RME96_DAC_IS_1852(rme96)) {
snd_rme96_write_SPI(rme96, (rme96->vol[0] << 2) | 0x0);
snd_rme96_write_SPI(rme96, (rme96->vol[1] << 2) | 0x2);
} else if (RME96_DAC_IS_1855(rme96)) {
snd_rme96_write_SPI(rme96, (rme96->vol[0] & 0x3FF) | 0x000);
snd_rme96_write_SPI(rme96, (rme96->vol[1] & 0x3FF) | 0x400);
}
}
static void
snd_rme96_reset_dac(struct rme96 *rme96)
{
writel(rme96->wcreg | RME96_WCR_PD,
rme96->iobase + RME96_IO_CONTROL_REGISTER);
writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
}
static int
snd_rme96_getmontracks(struct rme96 *rme96)
{
return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) +
(((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1);
}
static int
snd_rme96_setmontracks(struct rme96 *rme96,
int montracks)
{
if (montracks & 1) {
rme96->wcreg |= RME96_WCR_MONITOR_0;
} else {
rme96->wcreg &= ~RME96_WCR_MONITOR_0;
}
if (montracks & 2) {
rme96->wcreg |= RME96_WCR_MONITOR_1;
} else {
rme96->wcreg &= ~RME96_WCR_MONITOR_1;
}
writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
return 0;
}
static int
snd_rme96_getattenuation(struct rme96 *rme96)
{
return ((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_0) & 1) +
(((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_1) & 1) << 1);
}
static int
snd_rme96_setattenuation(struct rme96 *rme96,
int attenuation)
{
switch (attenuation) {
case 0:
rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) &
~RME96_WCR_GAIN_1;
break;
case 1:
rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) &
~RME96_WCR_GAIN_1;
break;
case 2:
rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) |
RME96_WCR_GAIN_1;
break;
case 3:
rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) |
RME96_WCR_GAIN_1;
break;
default:
return -EINVAL;
}
writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
return 0;
}
static int
snd_rme96_capture_getrate(struct rme96 *rme96,
int *is_adat)
{
int n, rate;
*is_adat = 0;
if (rme96->areg & RME96_AR_ANALOG) {
/* Analog input, overrides S/PDIF setting */
n = ((rme96->areg >> RME96_AR_BITPOS_F0) & 1) +
(((rme96->areg >> RME96_AR_BITPOS_F1) & 1) << 1);
switch (n) {
case 1:
rate = 32000;
break;
case 2:
rate = 44100;
break;
case 3:
rate = 48000;
break;
default:
return -1;
}
return (rme96->areg & RME96_AR_BITPOS_F2) ? rate << 1 : rate;
}
rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
if (rme96->rcreg & RME96_RCR_LOCK) {
/* ADAT rate */
*is_adat = 1;
if (rme96->rcreg & RME96_RCR_T_OUT) {
return 48000;
}
return 44100;
}
if (rme96->rcreg & RME96_RCR_VERF) {
return -1;
}
/* S/PDIF rate */
n = ((rme96->rcreg >> RME96_RCR_BITPOS_F0) & 1) +
(((rme96->rcreg >> RME96_RCR_BITPOS_F1) & 1) << 1) +
(((rme96->rcreg >> RME96_RCR_BITPOS_F2) & 1) << 2);
switch (n) {
case 0:
if (rme96->rcreg & RME96_RCR_T_OUT) {
return 64000;
}
return -1;
case 3: return 96000;
case 4: return 88200;
case 5: return 48000;
case 6: return 44100;
case 7: return 32000;
default:
break;
}
return -1;
}
static int
snd_rme96_playback_getrate(struct rme96 *rme96)
{
int rate, dummy;
if (!(rme96->wcreg & RME96_WCR_MASTER) &&
snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
(rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
{
/* slave clock */
return rate;
}
rate = ((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_0) & 1) +
(((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_1) & 1) << 1);
switch (rate) {
case 1:
rate = 32000;
break;
case 2:
rate = 44100;
break;
case 3:
rate = 48000;
break;
default:
return -1;
}
return (rme96->wcreg & RME96_WCR_DS) ? rate << 1 : rate;
}
static int
snd_rme96_playback_setrate(struct rme96 *rme96,
int rate)
{
int ds;
ds = rme96->wcreg & RME96_WCR_DS;
switch (rate) {
case 32000:
rme96->wcreg &= ~RME96_WCR_DS;
rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
~RME96_WCR_FREQ_1;
break;
case 44100:
rme96->wcreg &= ~RME96_WCR_DS;
rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
~RME96_WCR_FREQ_0;
break;
case 48000:
rme96->wcreg &= ~RME96_WCR_DS;
rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
RME96_WCR_FREQ_1;
break;
case 64000:
rme96->wcreg |= RME96_WCR_DS;
rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
~RME96_WCR_FREQ_1;
break;
case 88200:
rme96->wcreg |= RME96_WCR_DS;
rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
~RME96_WCR_FREQ_0;
break;
case 96000:
rme96->wcreg |= RME96_WCR_DS;
rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
RME96_WCR_FREQ_1;
break;
default:
return -EINVAL;
}
if ((!ds && rme96->wcreg & RME96_WCR_DS) ||
(ds && !(rme96->wcreg & RME96_WCR_DS)))
{
/* change to/from double-speed: reset the DAC (if available) */
snd_rme96_reset_dac(rme96);
return 1; /* need to restore volume */
} else {
writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
return 0;
}
}
static int
snd_rme96_capture_analog_setrate(struct rme96 *rme96,
int rate)
{
switch (rate) {
case 32000:
rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
~RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
break;
case 44100:
rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
break;
case 48000:
rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
break;
case 64000:
if (rme96->rev < 4) {
return -EINVAL;
}
rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
~RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
break;
case 88200:
if (rme96->rev < 4) {
return -EINVAL;
}
rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
break;
case 96000:
rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
break;
default:
return -EINVAL;
}
writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
return 0;
}
static int
snd_rme96_setclockmode(struct rme96 *rme96,
int mode)
{
switch (mode) {
case RME96_CLOCKMODE_SLAVE:
/* AutoSync */
rme96->wcreg &= ~RME96_WCR_MASTER;
rme96->areg &= ~RME96_AR_WSEL;
break;
case RME96_CLOCKMODE_MASTER:
/* Internal */
rme96->wcreg |= RME96_WCR_MASTER;
rme96->areg &= ~RME96_AR_WSEL;
break;
case RME96_CLOCKMODE_WORDCLOCK:
/* Word clock is a master mode */
rme96->wcreg |= RME96_WCR_MASTER;
rme96->areg |= RME96_AR_WSEL;
break;
default:
return -EINVAL;
}
writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
return 0;
}
static int
snd_rme96_getclockmode(struct rme96 *rme96)
{
if (rme96->areg & RME96_AR_WSEL) {
return RME96_CLOCKMODE_WORDCLOCK;
}
return (rme96->wcreg & RME96_WCR_MASTER) ? RME96_CLOCKMODE_MASTER :
RME96_CLOCKMODE_SLAVE;
}
static int
snd_rme96_setinputtype(struct rme96 *rme96,
int type)
{
int n;
switch (type) {
case RME96_INPUT_OPTICAL:
rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) &
~RME96_WCR_INP_1;
break;
case RME96_INPUT_COAXIAL:
rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) &
~RME96_WCR_INP_1;
break;
case RME96_INPUT_INTERNAL:
rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) |
RME96_WCR_INP_1;
break;
case RME96_INPUT_XLR:
if ((rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST &&
rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PRO) ||
(rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST &&
rme96->rev > 4))
{
/* Only Digi96/8 PRO and Digi96/8 PAD supports XLR */
return -EINVAL;
}
rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) |
RME96_WCR_INP_1;
break;
case RME96_INPUT_ANALOG:
if (!RME96_HAS_ANALOG_IN(rme96)) {
return -EINVAL;
}
rme96->areg |= RME96_AR_ANALOG;
writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
if (rme96->rev < 4) {
/*
* Revision less than 004 does not support 64 and
* 88.2 kHz
*/
if (snd_rme96_capture_getrate(rme96, &n) == 88200) {
snd_rme96_capture_analog_setrate(rme96, 44100);
}
if (snd_rme96_capture_getrate(rme96, &n) == 64000) {
snd_rme96_capture_analog_setrate(rme96, 32000);
}
}
return 0;
default:
return -EINVAL;
}
if (type != RME96_INPUT_ANALOG && RME96_HAS_ANALOG_IN(rme96)) {
rme96->areg &= ~RME96_AR_ANALOG;
writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
}
writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
return 0;
}
static int
snd_rme96_getinputtype(struct rme96 *rme96)
{
if (rme96->areg & RME96_AR_ANALOG) {
return RME96_INPUT_ANALOG;
}
return ((rme96->wcreg >> RME96_WCR_BITPOS_INP_0) & 1) +
(((rme96->wcreg >> RME96_WCR_BITPOS_INP_1) & 1) << 1);
}
static void
snd_rme96_setframelog(struct rme96 *rme96,
int n_channels,
int is_playback)
{
int frlog;
if (n_channels == 2) {
frlog = 1;
} else {
/* assume 8 channels */
frlog = 3;
}
if (is_playback) {
frlog += (rme96->wcreg & RME96_WCR_MODE24) ? 2 : 1;
rme96->playback_frlog = frlog;
} else {
frlog += (rme96->wcreg & RME96_WCR_MODE24_2) ? 2 : 1;
rme96->capture_frlog = frlog;
}
}
static int
snd_rme96_playback_setformat(struct rme96 *rme96, snd_pcm_format_t format)
{
switch (format) {
case SNDRV_PCM_FORMAT_S16_LE:
rme96->wcreg &= ~RME96_WCR_MODE24;
break;
case SNDRV_PCM_FORMAT_S32_LE:
rme96->wcreg |= RME96_WCR_MODE24;
break;
default:
return -EINVAL;
}
writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
return 0;
}
static int
snd_rme96_capture_setformat(struct rme96 *rme96, snd_pcm_format_t format)
{
switch (format) {
case SNDRV_PCM_FORMAT_S16_LE:
rme96->wcreg &= ~RME96_WCR_MODE24_2;
break;
case SNDRV_PCM_FORMAT_S32_LE:
rme96->wcreg |= RME96_WCR_MODE24_2;
break;
default:
return -EINVAL;
}
writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
return 0;
}
static void
snd_rme96_set_period_properties(struct rme96 *rme96,
size_t period_bytes)
{
switch (period_bytes) {
case RME96_LARGE_BLOCK_SIZE:
rme96->wcreg &= ~RME96_WCR_ISEL;
break;
case RME96_SMALL_BLOCK_SIZE:
rme96->wcreg |= RME96_WCR_ISEL;
break;
default:
snd_BUG();
break;
}
rme96->wcreg &= ~RME96_WCR_IDIS;
writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
}
static int
snd_rme96_playback_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct rme96 *rme96 = snd_pcm_substream_chip(substream);
struct snd_pcm_runtime *runtime = substream->runtime;
int err, rate, dummy;
bool apply_dac_volume = false;
runtime->dma_area = (void __force *)(rme96->iobase +