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deca_regs.h
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deca_regs.h
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/*! ---------------------------------------------------------------------------
* @file deca_regs.h
* @brief DW3000 Register Definitions
* This file supports Assembly and C development for DW3000 enabled devices
*
* @author Decawave Software
* @attention
* Copyright 2019 - 2020 (c) Decawave Ltd, Dublin, Ireland.
* All rights reserved.
*/
#ifndef __DECA_REGS_H
#define __DECA_REGS_H 1
#ifdef __cplusplus
extern "C" {
#endif
#include "deca_vals.h"
/******************************************************************************
* @brief Bit definitions for register DEV_ID
**/
#define DEV_ID_ID 0x0
#define DEV_ID_LEN (4U)
#define DEV_ID_MASK 0xFFFFFFFFUL
#define DEV_ID_RIDTAG_BIT_OFFSET (16U)
#define DEV_ID_RIDTAG_BIT_LEN (16U)
#define DEV_ID_RIDTAG_BIT_MASK 0xffff0000UL
#define DEV_ID_MODEL_BIT_OFFSET (8U)
#define DEV_ID_MODEL_BIT_LEN (8U)
#define DEV_ID_MODEL_BIT_MASK 0xff00U
#define DEV_ID_VER_BIT_OFFSET (4U)
#define DEV_ID_VER_BIT_LEN (4U)
#define DEV_ID_VER_BIT_MASK 0xf0U
#define DEV_ID_REV_BIT_OFFSET (0U)
#define DEV_ID_REV_BIT_LEN (4U)
#define DEV_ID_REV_BIT_MASK 0xfU
/******************************************************************************
* @brief Bit definitions for register EUI_64_LO
**/
#define EUI_64_LO_ID 0x4
#define EUI_64_LO_LEN (4U)
#define EUI_64_LO_MASK 0xFFFFFFFFUL
#define EUI_64_LO_EUI_64_BIT_OFFSET (0U)
#define EUI_64_LO_EUI_64_BIT_LEN (32U)
#define EUI_64_LO_EUI_64_BIT_MASK 0xffffffffUL
/******************************************************************************
* @brief Bit definitions for register EUI_64_HI
**/
#define EUI_64_HI_ID 0x8
#define EUI_64_HI_LEN (4U)
#define EUI_64_HI_MASK 0xFFFFFFFFUL
#define EUI_64_HI_EUI_64_BIT_OFFSET (0U)
#define EUI_64_HI_EUI_64_BIT_LEN (32U)
#define EUI_64_HI_EUI_64_BIT_MASK 0xffffffffUL
/******************************************************************************
* @brief Bit definitions for register PANADR
**/
#define PANADR_ID 0xc
#define PANADR_LEN (4U)
#define PANADR_MASK 0xFFFFFFFFUL
#define PANADR_PAN_ID_BIT_OFFSET (16U)
#define PANADR_PAN_ID_BIT_LEN (16U)
#define PANADR_PAN_ID_BIT_MASK 0xffff0000UL
#define PANADR_SHORTADDR_BIT_OFFSET (0U)
#define PANADR_SHORTADDR_BIT_LEN (16U)
#define PANADR_SHORTADDR_BIT_MASK 0xffffU
/******************************************************************************
* @brief Bit definitions for register SYS_CFG
**/
#define SYS_CFG_ID 0x10
#define SYS_CFG_LEN (4U)
#define SYS_CFG_MASK 0xFFFFFFFFUL
#define SYS_CFG_FAST_AAT_EN_BIT_OFFSET (18U)
#define SYS_CFG_FAST_AAT_EN_BIT_LEN (1U)
#define SYS_CFG_FAST_AAT_EN_BIT_MASK 0x40000UL
#define SYS_CFG_PDOA_MODE_BIT_OFFSET (16U)
#define SYS_CFG_PDOA_MODE_BIT_LEN (2U)
#define SYS_CFG_PDOA_MODE_BIT_MASK 0x30000UL
#define SYS_CFG_CP_SDC_BIT_OFFSET (15U)
#define SYS_CFG_CP_SDC_BIT_LEN (1U)
#define SYS_CFG_CP_SDC_BIT_MASK 0x8000U
#define SYS_CFG_CP_SPC_BIT_OFFSET (12U)
#define SYS_CFG_CP_SPC_BIT_LEN (2U)
#define SYS_CFG_CP_SPC_BIT_MASK 0x3000U
#define SYS_CFG_AUTO_ACK_BIT_OFFSET (11U)
#define SYS_CFG_AUTO_ACK_BIT_LEN (1U)
#define SYS_CFG_AUTO_ACK_BIT_MASK 0x800U
#define SYS_CFG_RXAUTR_BIT_OFFSET (10U)
#define SYS_CFG_RXAUTR_BIT_LEN (1U)
#define SYS_CFG_RXAUTR_BIT_MASK 0x400U
#define SYS_CFG_RXWTOE_BIT_OFFSET (9U)
#define SYS_CFG_RXWTOE_BIT_LEN (1U)
#define SYS_CFG_RXWTOE_BIT_MASK 0x200U
#define SYS_CFG_CIA_STS_BIT_OFFSET (8U)
#define SYS_CFG_CIA_STS_BIT_LEN (1U)
#define SYS_CFG_CIA_STS_BIT_MASK 0x100U
#define SYS_CFG_CIA_IPATOV_BIT_OFFSET (7U)
#define SYS_CFG_CIA_IPATOV_BIT_LEN (1U)
#define SYS_CFG_CIA_IPATOV_BIT_MASK 0x80U
#define SYS_CFG_SPI_CRC_BIT_OFFSET (6U)
#define SYS_CFG_SPI_CRC_BIT_LEN (1U)
#define SYS_CFG_SPI_CRC_BIT_MASK 0x40U
#define SYS_CFG_PHR_6M8_BIT_OFFSET (5U)
#define SYS_CFG_PHR_6M8_BIT_LEN (1U)
#define SYS_CFG_PHR_6M8_BIT_MASK 0x20U
#define SYS_CFG_PHR_MODE_BIT_OFFSET (4U)
#define SYS_CFG_PHR_MODE_BIT_LEN (1U)
#define SYS_CFG_PHR_MODE_BIT_MASK 0x10U
#define SYS_CFG_DIS_DRXB_BIT_OFFSET (3U)
#define SYS_CFG_DIS_DRXB_BIT_LEN (1U)
#define SYS_CFG_DIS_DRXB_BIT_MASK 0x8U
#define SYS_CFG_DIS_FCE_BIT_OFFSET (2U)
#define SYS_CFG_DIS_FCE_BIT_LEN (1U)
#define SYS_CFG_DIS_FCE_BIT_MASK 0x4U
#define SYS_CFG_DIS_FCS_TX_BIT_OFFSET (1U)
#define SYS_CFG_DIS_FCS_TX_BIT_LEN (1U)
#define SYS_CFG_DIS_FCS_TX_BIT_MASK 0x2U
#define SYS_CFG_FFEN_BIT_OFFSET (0U)
#define SYS_CFG_FFEN_BIT_LEN (1U)
#define SYS_CFG_FFEN_BIT_MASK 0x1U
/******************************************************************************
* @brief Bit definitions for register ADR_FILT_CFG
**/
#define ADR_FILT_CFG_ID 0x14
#define ADR_FILT_CFG_LEN (4U)
#define ADR_FILT_CFG_MASK 0xFFFFFFFFUL
#define ADR_FILT_CFG_LSADRAPE_BIT_OFFSET (15U)
#define ADR_FILT_CFG_LSADRAPE_BIT_LEN (1U)
#define ADR_FILT_CFG_LSADRAPE_BIT_MASK 0x8000U
#define ADR_FILT_CFG_SSADRAPE_BIT_OFFSET (14U)
#define ADR_FILT_CFG_SSADRAPE_BIT_LEN (1U)
#define ADR_FILT_CFG_SSADRAPE_BIT_MASK 0x4000U
#define ADR_FILT_CFG_LE3_PEND_BIT_OFFSET (13U)
#define ADR_FILT_CFG_LE3_PEND_BIT_LEN (1U)
#define ADR_FILT_CFG_LE3_PEND_BIT_MASK 0x2000U
#define ADR_FILT_CFG_LE2_PEND_BIT_OFFSET (12U)
#define ADR_FILT_CFG_LE2_PEND_BIT_LEN (1U)
#define ADR_FILT_CFG_LE2_PEND_BIT_MASK 0x1000U
#define ADR_FILT_CFG_LE1_PEND_BIT_OFFSET (11U)
#define ADR_FILT_CFG_LE1_PEND_BIT_LEN (1U)
#define ADR_FILT_CFG_LE1_PEND_BIT_MASK 0x800U
#define ADR_FILT_CFG_LE0_PEND_BIT_OFFSET (10U)
#define ADR_FILT_CFG_LE0_PEND_BIT_LEN (1U)
#define ADR_FILT_CFG_LE0_PEND_BIT_MASK 0x400U
#define ADR_FILT_CFG_FFIB_BIT_OFFSET (9U)
#define ADR_FILT_CFG_FFIB_BIT_LEN (1U)
#define ADR_FILT_CFG_FFIB_BIT_MASK 0x200U
#define ADR_FILT_CFG_FFBC_BIT_OFFSET (8U)
#define ADR_FILT_CFG_FFBC_BIT_LEN (1U)
#define ADR_FILT_CFG_FFBC_BIT_MASK 0x100U
#define ADR_FILT_CFG_FFAE_BIT_OFFSET (7U)
#define ADR_FILT_CFG_FFAE_BIT_LEN (1U)
#define ADR_FILT_CFG_FFAE_BIT_MASK 0x80U
#define ADR_FILT_CFG_FFAF_BIT_OFFSET (6U)
#define ADR_FILT_CFG_FFAF_BIT_LEN (1U)
#define ADR_FILT_CFG_FFAF_BIT_MASK 0x40U
#define ADR_FILT_CFG_FFAMULTI_BIT_OFFSET (5U)
#define ADR_FILT_CFG_FFAMULTI_BIT_LEN (1U)
#define ADR_FILT_CFG_FFAMULTI_BIT_MASK 0x20U
#define ADR_FILT_CFG_FFAR_BIT_OFFSET (4U)
#define ADR_FILT_CFG_FFAR_BIT_LEN (1U)
#define ADR_FILT_CFG_FFAR_BIT_MASK 0x10U
#define ADR_FILT_CFG_FFAM_BIT_OFFSET (3U)
#define ADR_FILT_CFG_FFAM_BIT_LEN (1U)
#define ADR_FILT_CFG_FFAM_BIT_MASK 0x8U
#define ADR_FILT_CFG_FFAA_BIT_OFFSET (2U)
#define ADR_FILT_CFG_FFAA_BIT_LEN (1U)
#define ADR_FILT_CFG_FFAA_BIT_MASK 0x4U
#define ADR_FILT_CFG_FFAD_BIT_OFFSET (1U)
#define ADR_FILT_CFG_FFAD_BIT_LEN (1U)
#define ADR_FILT_CFG_FFAD_BIT_MASK 0x2U
#define ADR_FILT_CFG_FFAB_BIT_OFFSET (0U)
#define ADR_FILT_CFG_FFAB_BIT_LEN (1U)
#define ADR_FILT_CFG_FFAB_BIT_MASK 0x1U
/******************************************************************************
* @brief Bit definitions for register SPICRC_CFG
**/
#define SPICRC_CFG_ID 0x18
#define SPICRC_CFG_LEN (4U)
#define SPICRC_CFG_MASK 0xFFFFFFFFUL
#define SPICRC_CFG_SPI_RD_CRC_BIT_OFFSET (0U)
#define SPICRC_CFG_SPI_RD_CRC_BIT_LEN (8U)
#define SPICRC_CFG_SPI_RD_CRC_BIT_MASK 0xffU
/******************************************************************************
* @brief Bit definitions for register SYS_TIME
**/
#define SYS_TIME_ID 0x1c
#define SYS_TIME_LEN (4U)
#define SYS_TIME_MASK 0xFFFFFFFFUL
#define SYS_TIME_SYS_TIME_BIT_OFFSET (1U)
#define SYS_TIME_SYS_TIME_BIT_LEN (31U)
#define SYS_TIME_SYS_TIME_BIT_MASK 0xfffffffeUL
/******************************************************************************
* @brief Bit definitions for register TX_FCTRL
**/
#define TX_FCTRL_ID 0x24
#define TX_FCTRL_LEN (4U)
#define TX_FCTRL_MASK 0xFFFFFFFFUL
#define TX_FCTRL_TXB_OFFSET_BIT_OFFSET (16U)
#define TX_FCTRL_TXB_OFFSET_BIT_LEN (10U)
#define TX_FCTRL_TXB_OFFSET_BIT_MASK 0x3ff0000UL
#define TX_FCTRL_TXPSR_BIT_OFFSET (12U)
#define TX_FCTRL_TXPSR_BIT_LEN (4U)
#define TX_FCTRL_TXPSR_BIT_MASK 0xf000U
#define TX_FCTRL_TR_BIT_OFFSET (11U)
#define TX_FCTRL_TR_BIT_LEN (1U)
#define TX_FCTRL_TR_BIT_MASK 0x800U
#define TX_FCTRL_TXBR_BIT_OFFSET (10U)
#define TX_FCTRL_TXBR_BIT_LEN (1U)
#define TX_FCTRL_TXBR_BIT_MASK 0x400U
#define TX_FCTRL_TXFLEN_BIT_OFFSET (0U)
#define TX_FCTRL_TXFLEN_BIT_LEN (10U)
#define TX_FCTRL_TXFLEN_BIT_MASK 0x3ffU
/******************************************************************************
* @brief Bit definitions for register TX_FCTRL_HI
**/
#define TX_FCTRL_HI_ID 0x28
#define TX_FCTRL_HI_LEN (4U)
#define TX_FCTRL_HI_MASK 0xFFFFFFFFUL
#define TX_FCTRL_HI_FINE_PLEN_BIT_OFFSET (8U)
#define TX_FCTRL_HI_FINE_PLEN_BIT_LEN (8U)
#define TX_FCTRL_HI_FINE_PLEN_BIT_MASK 0xff00U
/******************************************************************************
* @brief Bit definitions for register DX_TIME
**/
#define DX_TIME_ID 0x2c
#define DX_TIME_LEN (4U)
#define DX_TIME_MASK 0xFFFFFFFFUL
#define DX_TIME_DX_TIME_BIT_OFFSET (1U)
#define DX_TIME_DX_TIME_BIT_LEN (31U)
#define DX_TIME_DX_TIME_BIT_MASK 0xfffffffeUL
/******************************************************************************
* @brief Bit definitions for register DREF_TIME
**/
#define DREF_TIME_ID 0x30
#define DREF_TIME_LEN (4U)
#define DREF_TIME_MASK 0xFFFFFFFFUL
#define DREF_TIME_DREF_BIT_OFFSET (1U)
#define DREF_TIME_DREF_BIT_LEN (31U)
#define DREF_TIME_DREF_BIT_MASK 0xfffffffeUL
/******************************************************************************
* @brief Bit definitions for register RX_FWTO
**/
#define RX_FWTO_ID 0x34
#define RX_FWTO_LEN (4U)
#define RX_FWTO_MASK 0xFFFFFFFFUL
#define RX_FWTO_FWTO_BIT_OFFSET (0U)
#define RX_FWTO_FWTO_BIT_LEN (20U)
#define RX_FWTO_FWTO_BIT_MASK 0xfffffUL
/******************************************************************************
* @brief Bit definitions for register SYS_ENABLE_LO
**/
#define SYS_ENABLE_LO_ID 0x3c
#define SYS_ENABLE_LO_LEN (4U)
#define SYS_ENABLE_LO_MASK 0xFFFFFFFFUL
#define SYS_ENABLE_LO_ARFE_ENABLE_BIT_OFFSET (29U)
#define SYS_ENABLE_LO_ARFE_ENABLE_BIT_LEN (1U)
#define SYS_ENABLE_LO_ARFE_ENABLE_BIT_MASK 0x20000000UL
#define SYS_ENABLE_LO_CPERR_ENABLE_BIT_OFFSET (28U)
#define SYS_ENABLE_LO_CPERR_ENABLE_BIT_LEN (1U)
#define SYS_ENABLE_LO_CPERR_ENABLE_BIT_MASK 0x10000000UL
#define SYS_ENABLE_LO_HPDWARN_ENABLE_BIT_OFFSET (27U)
#define SYS_ENABLE_LO_HPDWARN_ENABLE_BIT_LEN (1U)
#define SYS_ENABLE_LO_HPDWARN_ENABLE_BIT_MASK 0x8000000UL
#define SYS_ENABLE_LO_RXSTO_ENABLE_BIT_OFFSET (26U)
#define SYS_ENABLE_LO_RXSTO_ENABLE_BIT_LEN (1U)
#define SYS_ENABLE_LO_RXSTO_ENABLE_BIT_MASK 0x4000000UL
#define SYS_ENABLE_LO_PLL_HILO_ENABLE_BIT_OFFSET (25U)
#define SYS_ENABLE_LO_PLL_HILO_ENABLE_BIT_LEN (1U)
#define SYS_ENABLE_LO_PLL_HILO_ENABLE_BIT_MASK 0x2000000UL
#define SYS_ENABLE_LO_RCINIT_ENABLE_BIT_OFFSET (24U)
#define SYS_ENABLE_LO_RCINIT_ENABLE_BIT_LEN (1U)
#define SYS_ENABLE_LO_RCINIT_ENABLE_BIT_MASK 0x1000000UL
#define SYS_ENABLE_LO_SPIRDY_ENABLE_BIT_OFFSET (23U)
#define SYS_ENABLE_LO_SPIRDY_ENABLE_BIT_LEN (1U)
#define SYS_ENABLE_LO_SPIRDY_ENABLE_BIT_MASK 0x800000UL
#define SYS_ENABLE_LO_RXPTO_ENABLE_BIT_OFFSET (21U)
#define SYS_ENABLE_LO_RXPTO_ENABLE_BIT_LEN (1U)
#define SYS_ENABLE_LO_RXPTO_ENABLE_BIT_MASK 0x200000UL
#define SYS_ENABLE_LO_RXOVRR_ENABLE_BIT_OFFSET (20U)
#define SYS_ENABLE_LO_RXOVRR_ENABLE_BIT_LEN (1U)
#define SYS_ENABLE_LO_RXOVRR_ENABLE_BIT_MASK 0x100000UL
#define SYS_ENABLE_LO_VWARN_ENABLE_BIT_OFFSET (19U)
#define SYS_ENABLE_LO_VWARN_ENABLE_BIT_LEN (1U)
#define SYS_ENABLE_LO_VWARN_ENABLE_BIT_MASK 0x80000UL
#define SYS_ENABLE_LO_CIAERR_ENABLE_BIT_OFFSET (18U)
#define SYS_ENABLE_LO_CIAERR_ENABLE_BIT_LEN (1U)
#define SYS_ENABLE_LO_CIAERR_ENABLE_BIT_MASK 0x40000UL
#define SYS_ENABLE_LO_RXFTO_ENABLE_BIT_OFFSET (17U)
#define SYS_ENABLE_LO_RXFTO_ENABLE_BIT_LEN (1U)
#define SYS_ENABLE_LO_RXFTO_ENABLE_BIT_MASK 0x20000UL
#define SYS_ENABLE_LO_RXFSL_ENABLE_BIT_OFFSET (16U)
#define SYS_ENABLE_LO_RXFSL_ENABLE_BIT_LEN (1U)
#define SYS_ENABLE_LO_RXFSL_ENABLE_BIT_MASK 0x10000UL
#define SYS_ENABLE_LO_RXFCE_ENABLE_BIT_OFFSET (15U)
#define SYS_ENABLE_LO_RXFCE_ENABLE_BIT_LEN (1U)
#define SYS_ENABLE_LO_RXFCE_ENABLE_BIT_MASK 0x8000U
#define SYS_ENABLE_LO_RXFCG_ENABLE_BIT_OFFSET (14U)
#define SYS_ENABLE_LO_RXFCG_ENABLE_BIT_LEN (1U)
#define SYS_ENABLE_LO_RXFCG_ENABLE_BIT_MASK 0x4000U
#define SYS_ENABLE_LO_RXFR_ENABLE_BIT_OFFSET (13U)
#define SYS_ENABLE_LO_RXFR_ENABLE_BIT_LEN (1U)
#define SYS_ENABLE_LO_RXFR_ENABLE_BIT_MASK 0x2000U
#define SYS_ENABLE_LO_RXPHE_ENABLE_BIT_OFFSET (12U)
#define SYS_ENABLE_LO_RXPHE_ENABLE_BIT_LEN (1U)
#define SYS_ENABLE_LO_RXPHE_ENABLE_BIT_MASK 0x1000U
#define SYS_ENABLE_LO_RXPHD_ENABLE_BIT_OFFSET (11U)
#define SYS_ENABLE_LO_RXPHD_ENABLE_BIT_LEN (1U)
#define SYS_ENABLE_LO_RXPHD_ENABLE_BIT_MASK 0x800U
#define SYS_ENABLE_LO_CIADONE_ENABLE_BIT_OFFSET (10U)
#define SYS_ENABLE_LO_CIADONE_ENABLE_BIT_LEN (1U)
#define SYS_ENABLE_LO_CIADONE_ENABLE_BIT_MASK 0x400U
#define SYS_ENABLE_LO_RXSFDD_ENABLE_BIT_OFFSET (9U)
#define SYS_ENABLE_LO_RXSFDD_ENABLE_BIT_LEN (1U)
#define SYS_ENABLE_LO_RXSFDD_ENABLE_BIT_MASK 0x200U
#define SYS_ENABLE_LO_RXPRD_ENABLE_BIT_OFFSET (8U)
#define SYS_ENABLE_LO_RXPRD_ENABLE_BIT_LEN (1U)
#define SYS_ENABLE_LO_RXPRD_ENABLE_BIT_MASK 0x100U
#define SYS_ENABLE_LO_TXFRS_ENABLE_BIT_OFFSET (7U)
#define SYS_ENABLE_LO_TXFRS_ENABLE_BIT_LEN (1U)
#define SYS_ENABLE_LO_TXFRS_ENABLE_BIT_MASK 0x80U
#define SYS_ENABLE_LO_TXPHS_ENABLE_BIT_OFFSET (6U)
#define SYS_ENABLE_LO_TXPHS_ENABLE_BIT_LEN (1U)
#define SYS_ENABLE_LO_TXPHS_ENABLE_BIT_MASK 0x40U
#define SYS_ENABLE_LO_TXPRS_ENABLE_BIT_OFFSET (5U)
#define SYS_ENABLE_LO_TXPRS_ENABLE_BIT_LEN (1U)
#define SYS_ENABLE_LO_TXPRS_ENABLE_BIT_MASK 0x20U
#define SYS_ENABLE_LO_TXFRB_ENABLE_BIT_OFFSET (4U)
#define SYS_ENABLE_LO_TXFRB_ENABLE_BIT_LEN (1U)
#define SYS_ENABLE_LO_TXFRB_ENABLE_BIT_MASK 0x10U
#define SYS_ENABLE_LO_AAT_ENABLE_BIT_OFFSET (3U)
#define SYS_ENABLE_LO_AAT_ENABLE_BIT_LEN (1U)
#define SYS_ENABLE_LO_AAT_ENABLE_BIT_MASK 0x8U
#define SYS_ENABLE_LO_SPICRCE_ENABLE_BIT_OFFSET (2U)
#define SYS_ENABLE_LO_SPICRCE_ENABLE_BIT_LEN (1U)
#define SYS_ENABLE_LO_SPICRCE_ENABLE_BIT_MASK 0x4U
#define SYS_ENABLE_LO_CP_LOCK_ENABLE_BIT_OFFSET (1U)
#define SYS_ENABLE_LO_CP_LOCK_ENABLE_BIT_LEN (1U)
#define SYS_ENABLE_LO_CP_LOCK_ENABLE_BIT_MASK 0x2U
/******************************************************************************
* @brief Bit definitions for register SYS_ENABLE_HI
**/
#define SYS_ENABLE_HI_ID 0x40
#define SYS_ENABLE_HI_LEN (4U)
#define SYS_ENABLE_HI_MASK 0xFFFFFFFFUL
#define SYS_ENABLE_HI_CCA_FAIL_ENABLE_BIT_OFFSET (12U)
#define SYS_ENABLE_HI_CCA_FAIL_ENABLE_BIT_LEN (1U)
#define SYS_ENABLE_HI_CCA_FAIL_ENABLE_BIT_MASK 0x1000U
#define SYS_ENABLE_HI_SPIERR_ENABLE_BIT_OFFSET (11U)
#define SYS_ENABLE_HI_SPIERR_ENABLE_BIT_LEN (1U)
#define SYS_ENABLE_HI_SPIERR_ENABLE_BIT_MASK 0x800U
#define SYS_ENABLE_HI_SPI_UNF_ENABLE_BIT_OFFSET (10U)
#define SYS_ENABLE_HI_SPI_UNF_ENABLE_BIT_LEN (1U)
#define SYS_ENABLE_HI_SPI_UNF_ENABLE_BIT_MASK 0x400U
#define SYS_ENABLE_HI_SPI_OVF_ENABLE_BIT_OFFSET (9U)
#define SYS_ENABLE_HI_SPI_OVF_ENABLE_BIT_LEN (1U)
#define SYS_ENABLE_HI_SPI_OVF_ENABLE_BIT_MASK 0x200U
#define SYS_ENABLE_HI_CMD_ERR_ENABLE_BIT_OFFSET (8U)
#define SYS_ENABLE_HI_CMD_ERR_ENABLE_BIT_LEN (1U)
#define SYS_ENABLE_HI_CMD_ERR_ENABLE_BIT_MASK 0x100U
#define SYS_ENABLE_HI_AES_ERR_ENABLE_BIT_OFFSET (7U)
#define SYS_ENABLE_HI_AES_ERR_ENABLE_BIT_LEN (1U)
#define SYS_ENABLE_HI_AES_ERR_ENABLE_BIT_MASK 0x80U
#define SYS_ENABLE_HI_AES_DONE_ENABLE_BIT_OFFSET (6U)
#define SYS_ENABLE_HI_AES_DONE_ENABLE_BIT_LEN (1U)
#define SYS_ENABLE_HI_AES_DONE_ENABLE_BIT_MASK 0x40U
#define SYS_ENABLE_HI_GPIOIRQ_ENABLE_BIT_OFFSET (5U)
#define SYS_ENABLE_HI_GPIOIRQ_ENABLE_BIT_LEN (1U)
#define SYS_ENABLE_HI_GPIOIRQ_ENABLE_BIT_MASK 0x20U
#define SYS_ENABLE_HI_VT_DET_ENABLE_BIT_OFFSET (4U)
#define SYS_ENABLE_HI_VT_DET_ENABLE_BIT_LEN (1U)
#define SYS_ENABLE_HI_VT_DET_ENABLE_BIT_MASK 0x10U
#define SYS_ENABLE_HI_RXPREJ_ENABLE_BIT_OFFSET (1U)
#define SYS_ENABLE_HI_RXPREJ_ENABLE_BIT_LEN (1U)
#define SYS_ENABLE_HI_RXPREJ_ENABLE_BIT_MASK 0x2U
/******************************************************************************
* @brief Bit definitions for register SYS_STATUS
**/
#define SYS_STATUS_ID 0x44
#define SYS_STATUS_LEN (4U)
#define SYS_STATUS_MASK 0xFFFFFFFFUL
#define SYS_STATUS_ARFE_BIT_OFFSET (29U)
#define SYS_STATUS_ARFE_BIT_LEN (1U)
#define SYS_STATUS_ARFE_BIT_MASK 0x20000000UL
#define SYS_STATUS_CPERR_BIT_OFFSET (28U)
#define SYS_STATUS_CPERR_BIT_LEN (1U)
#define SYS_STATUS_CPERR_BIT_MASK 0x10000000UL
#define SYS_STATUS_HPDWARN_BIT_OFFSET (27U)
#define SYS_STATUS_HPDWARN_BIT_LEN (1U)
#define SYS_STATUS_HPDWARN_BIT_MASK 0x08000000UL
#define SYS_STATUS_RXSTO_BIT_OFFSET (26U)
#define SYS_STATUS_RXSTO_BIT_LEN (1U)
#define SYS_STATUS_RXSTO_BIT_MASK 0x04000000UL
#define SYS_STATUS_PLL_HILO_BIT_OFFSET (25U)
#define SYS_STATUS_PLL_HILO_BIT_LEN (1U)
#define SYS_STATUS_PLL_HILO_BIT_MASK 0x02000000UL
#define SYS_STATUS_RCINIT_BIT_OFFSET (24U)
#define SYS_STATUS_RCINIT_BIT_LEN (1U)
#define SYS_STATUS_RCINIT_BIT_MASK 0x01000000UL
#define SYS_STATUS_SPIRDY_BIT_OFFSET (23U)
#define SYS_STATUS_SPIRDY_BIT_LEN (1U)
#define SYS_STATUS_SPIRDY_BIT_MASK 0x00800000UL
#define SYS_STATUS_RXPTO_BIT_OFFSET (21U)
#define SYS_STATUS_RXPTO_BIT_LEN (1U)
#define SYS_STATUS_RXPTO_BIT_MASK 0x00200000UL
#define SYS_STATUS_RXOVRR_BIT_OFFSET (20U)
#define SYS_STATUS_RXOVRR_BIT_LEN (1U)
#define SYS_STATUS_RXOVRR_BIT_MASK 0x00100000UL
#define SYS_STATUS_VWARN_BIT_OFFSET (19U)
#define SYS_STATUS_VWARN_BIT_LEN (1U)
#define SYS_STATUS_VWARN_BIT_MASK 0x00080000UL
#define SYS_STATUS_CIAERR_BIT_OFFSET (18U)
#define SYS_STATUS_CIAERR_BIT_LEN (1U)
#define SYS_STATUS_CIAERR_BIT_MASK 0x00040000UL
#define SYS_STATUS_RXFTO_BIT_OFFSET (17U)
#define SYS_STATUS_RXFTO_BIT_LEN (1U)
#define SYS_STATUS_RXFTO_BIT_MASK 0x00020000UL
#define SYS_STATUS_RXFSL_BIT_OFFSET (16U)
#define SYS_STATUS_RXFSL_BIT_LEN (1U)
#define SYS_STATUS_RXFSL_BIT_MASK 0x00010000UL
#define SYS_STATUS_RXFCE_BIT_OFFSET (15U)
#define SYS_STATUS_RXFCE_BIT_LEN (1U)
#define SYS_STATUS_RXFCE_BIT_MASK 0x00008000U
#define SYS_STATUS_RXFCG_BIT_OFFSET (14U)
#define SYS_STATUS_RXFCG_BIT_LEN (1U)
#define SYS_STATUS_RXFCG_BIT_MASK 0x00004000U
#define SYS_STATUS_RXFR_BIT_OFFSET (13U)
#define SYS_STATUS_RXFR_BIT_LEN (1U)
#define SYS_STATUS_RXFR_BIT_MASK 0x00002000U
#define SYS_STATUS_RXPHE_BIT_OFFSET (12U)
#define SYS_STATUS_RXPHE_BIT_LEN (1U)
#define SYS_STATUS_RXPHE_BIT_MASK 0x00001000U
#define SYS_STATUS_RXPHD_BIT_OFFSET (11U)
#define SYS_STATUS_RXPHD_BIT_LEN (1U)
#define SYS_STATUS_RXPHD_BIT_MASK 0x00000800U
#define SYS_STATUS_CIADONE_BIT_OFFSET (10U)
#define SYS_STATUS_CIADONE_BIT_LEN (1U)
#define SYS_STATUS_CIADONE_BIT_MASK 0x00000400U
#define SYS_STATUS_RXSFDD_BIT_OFFSET (9U)
#define SYS_STATUS_RXSFDD_BIT_LEN (1U)
#define SYS_STATUS_RXSFDD_BIT_MASK 0x00000200U
#define SYS_STATUS_RXPRD_BIT_OFFSET (8U)
#define SYS_STATUS_RXPRD_BIT_LEN (1U)
#define SYS_STATUS_RXPRD_BIT_MASK 0x00000100U
#define SYS_STATUS_TXFRS_BIT_OFFSET (7U)
#define SYS_STATUS_TXFRS_BIT_LEN (1U)
#define SYS_STATUS_TXFRS_BIT_MASK 0x00000080U
#define SYS_STATUS_TXPHS_BIT_OFFSET (6U)
#define SYS_STATUS_TXPHS_BIT_LEN (1U)
#define SYS_STATUS_TXPHS_BIT_MASK 0x00000040U
#define SYS_STATUS_TXPRS_BIT_OFFSET (5U)
#define SYS_STATUS_TXPRS_BIT_LEN (1U)
#define SYS_STATUS_TXPRS_BIT_MASK 0x00000020U
#define SYS_STATUS_TXFRB_BIT_OFFSET (4U)
#define SYS_STATUS_TXFRB_BIT_LEN (1U)
#define SYS_STATUS_TXFRB_BIT_MASK 0x00000010U
#define SYS_STATUS_AAT_BIT_OFFSET (3U)
#define SYS_STATUS_AAT_BIT_LEN (1U)
#define SYS_STATUS_AAT_BIT_MASK 0x00000008U
#define SYS_STATUS_SPICRCE_BIT_OFFSET (2U)
#define SYS_STATUS_SPICRCE_BIT_LEN (1U)
#define SYS_STATUS_SPICRCE_BIT_MASK 0x00000004U
#define SYS_STATUS_CP_LOCK_BIT_OFFSET (1U)
#define SYS_STATUS_CP_LOCK_BIT_LEN (1U)
#define SYS_STATUS_CP_LOCK_BIT_MASK 0x00000002U
#define SYS_STATUS_IRQS_BIT_OFFSET (0U)
#define SYS_STATUS_IRQS_BIT_LEN (1U)
#define SYS_STATUS_IRQS_BIT_MASK 0x00000001U
/******************************************************************************
* @brief Bit definitions for register SYS_STATUS_HI
**/
#define SYS_STATUS_HI_ID 0x48
#define SYS_STATUS_HI_LEN (4U)
#define SYS_STATUS_HI_MASK 0xFFFFFFFFUL
#define SYS_STATUS_HI_CCA_FAIL_BIT_OFFSET (12U)
#define SYS_STATUS_HI_CCA_FAIL_BIT_LEN (1U)
#define SYS_STATUS_HI_CCA_FAIL_BIT_MASK 0x1000U
#define SYS_STATUS_HI_SPIERR_BIT_OFFSET (11U)
#define SYS_STATUS_HI_SPIERR_BIT_LEN (1U)
#define SYS_STATUS_HI_SPIERR_BIT_MASK 0x800U
#define SYS_STATUS_HI_SPI_UNF_BIT_OFFSET (10U)
#define SYS_STATUS_HI_SPI_UNF_BIT_LEN (1U)
#define SYS_STATUS_HI_SPI_UNF_BIT_MASK 0x400U
#define SYS_STATUS_HI_SPI_OVF_BIT_OFFSET (9U)
#define SYS_STATUS_HI_SPI_OVF_BIT_LEN (1U)
#define SYS_STATUS_HI_SPI_OVF_BIT_MASK 0x200U
#define SYS_STATUS_HI_CMD_ERR_BIT_OFFSET (8U)
#define SYS_STATUS_HI_CMD_ERR_BIT_LEN (1U)
#define SYS_STATUS_HI_CMD_ERR_BIT_MASK 0x100U
#define SYS_STATUS_HI_AES_ERR_BIT_OFFSET (7U)
#define SYS_STATUS_HI_AES_ERR_BIT_LEN (1U)
#define SYS_STATUS_HI_AES_ERR_BIT_MASK 0x80U
#define SYS_STATUS_HI_AES_DONE_BIT_OFFSET (6U)
#define SYS_STATUS_HI_AES_DONE_BIT_LEN (1U)
#define SYS_STATUS_HI_AES_DONE_BIT_MASK 0x40U
#define SYS_STATUS_HI_GPIO_IRQ_BIT_OFFSET (5U)
#define SYS_STATUS_HI_GPIO_IRQ_BIT_LEN (1U)
#define SYS_STATUS_HI_GPIO_IRQ_BIT_MASK 0x20U
#define SYS_STATUS_HI_VT_DET_BIT_OFFSET (4U)
#define SYS_STATUS_HI_VT_DET_BIT_LEN (1U)
#define SYS_STATUS_HI_VT_DET_BIT_MASK 0x10U
#define SYS_STATUS_HI_RXPREJ_BIT_OFFSET (1U)
#define SYS_STATUS_HI_RXPREJ_BIT_LEN (1U)
#define SYS_STATUS_HI_RXPREJ_BIT_MASK 0x2U
/******************************************************************************
* @brief Bit definitions for register RX_FINFO
**/
#define RX_FINFO_ID 0x4c
#define RX_FINFO_LEN (4U)
#define RX_FINFO_MASK 0xFFFFFFFFUL
#define RX_FINFO_RXPACC_BIT_OFFSET (20U)
#define RX_FINFO_RXPACC_BIT_LEN (12U)
#define RX_FINFO_RXPACC_BIT_MASK 0xfff00000UL
#define RX_FINFO_RXPSR_BIT_OFFSET (18U)
#define RX_FINFO_RXPSR_BIT_LEN (2U)
#define RX_FINFO_RXPSR_BIT_MASK 0xc0000UL
#define RX_FINFO_RXPRF_BIT_OFFSET (16U)
#define RX_FINFO_RXPRF_BIT_LEN (2U)
#define RX_FINFO_RXPRF_BIT_MASK 0x30000UL
#define RX_FINFO_RNG_BIT_OFFSET (15U)
#define RX_FINFO_RNG_BIT_LEN (1U)
#define RX_FINFO_RNG_BIT_MASK 0x8000U
#define RX_FINFO_RXBR_BIT_OFFSET (13U)
#define RX_FINFO_RXBR_BIT_LEN (1U)
#define RX_FINFO_RXBR_BIT_MASK 0x2000U
#define RX_FINFO_RXNSPL_BIT_OFFSET (11U)
#define RX_FINFO_RXNSPL_BIT_LEN (2U)
#define RX_FINFO_RXNSPL_BIT_MASK 0x1800U
#define RX_FINFO_RXFLEN_BIT_OFFSET (0U)
#define RX_FINFO_RXFLEN_BIT_LEN (10U)
#define RX_FINFO_RXFLEN_BIT_MASK 0x3ffU
/******************************************************************************
* @brief Bit definitions for register RX_TIME_0
**/
#define RX_TIME_0_ID 0x64
#define RX_TIME_0_LEN (4U)
#define RX_TIME_0_MASK 0xFFFFFFFFUL
/******************************************************************************
* @brief Bit definitions for register RX_TIME_RAW
**/
#define RX_TIME_RAW_ID 0x70
#define RX_TIME_RAW_LEN (4U)
#define RX_TIME_RAW_MASK 0xFFFFFFFFUL
#define RX_TIME_RX_RAWST_BIT_OFFSET (0U)
#define RX_TIME_RX_RAWST_BIT_LEN (32U)
#define RX_TIME_RX_RAWST_BIT_MASK 0xffffffffUL
/******************************************************************************
* @brief Bit definitions for register TX_TIME_LO
**/
#define TX_TIME_LO_ID 0x74
#define TX_TIME_LO_LEN (4U)
#define TX_TIME_LO_MASK 0xFFFFFFFFUL
/******************************************************************************
* @brief Bit definitions for register TX_TIME_RAW
**/
#define TX_TIME_RAW_ID 0x10000
#define TX_TIME_RAW_LEN (4U)
#define TX_TIME_RAW_MASK 0xFFFFFFFFUL
#define TX_TIME_TX_RAWST_BIT_OFFSET (0U)
#define TX_TIME_TX_RAWST_BIT_LEN (32U)
#define TX_TIME_TX_RAWST_BIT_MASK 0xffffffffUL
/******************************************************************************
* @brief Bit definitions for register TX_ANTD
**/
#define TX_ANTD_ID 0x10004
#define TX_ANTD_LEN (4U)
#define TX_ANTD_MASK 0xFFFFFFFFUL
/******************************************************************************
* @brief Bit definitions for register ACK_RESP
**/
#define ACK_RESP_ID 0x10008
#define ACK_RESP_LEN (4U)
#define ACK_RESP_MASK 0xFFFFFFFFUL
#define ACK_RESP_W4R_TIM_BIT_OFFSET (0U)
#define ACK_RESP_W4R_TIM_BIT_LEN (20U)
#define ACK_RESP_W4R_TIM_BIT_MASK 0xfffffUL
/******************************************************************************
* @brief Bit definitions for register TX_POWER
**/
#define TX_POWER_ID 0x1000c
#define TX_POWER_LEN (4U)
#define TX_POWER_MASK 0xFFFFFFFFUL
/******************************************************************************
* @brief Bit definitions for register CHAN_CTRL
**/
#define CHAN_CTRL_ID 0x10014
#define CHAN_CTRL_LEN (4U)
#define CHAN_CTRL_MASK 0xFFFFFFFFUL
#define CHAN_CTRL_RX_PCODE_BIT_OFFSET (8U)
#define CHAN_CTRL_RX_PCODE_BIT_LEN (5U)
#define CHAN_CTRL_RX_PCODE_BIT_MASK 0x1f00U
#define CHAN_CTRL_TX_PCODE_BIT_OFFSET (3U)
#define CHAN_CTRL_TX_PCODE_BIT_LEN (5U)
#define CHAN_CTRL_TX_PCODE_BIT_MASK 0xf8U
#define CHAN_CTRL_SFD_TYPE_BIT_OFFSET (1U)
#define CHAN_CTRL_SFD_TYPE_BIT_LEN (2U)
#define CHAN_CTRL_SFD_TYPE_BIT_MASK 0x6U
#define CHAN_CTRL_RF_CHAN_BIT_OFFSET (0U)
#define CHAN_CTRL_RF_CHAN_BIT_LEN (1U)
#define CHAN_CTRL_RF_CHAN_BIT_MASK 0x1U
/******************************************************************************
* @brief Bit definitions for register LE_PEND_01
**/
#define LE_PEND_01_ID 0x10018
#define LE_PEND_01_LEN (4U)
#define LE_PEND_01_MASK 0xFFFFFFFFUL
/******************************************************************************
* @brief Bit definitions for register LE_PEND_23
**/
#define LE_PEND_23_ID 0x1001c
#define LE_PEND_23_LEN (4U)
#define LE_PEND_23_MASK 0xFFFFFFFFUL
/******************************************************************************
* @brief Bit definitions for register RDB_STATUS
**/
#define RDB_STATUS_ID 0x10024
#define RDB_STATUS_LEN (4U)
#define RDB_STATUS_MASK 0xFFFFFFFFUL
#define RDB_STATUS_CP_ERR1_BIT_OFFSET (7U)
#define RDB_STATUS_CP_ERR1_BIT_LEN (1U)
#define RDB_STATUS_CP_ERR1_BIT_MASK 0x80U
#define RDB_STATUS_CIADONE1_BIT_OFFSET (6U)
#define RDB_STATUS_CIADONE1_BIT_LEN (1U)
#define RDB_STATUS_CIADONE1_BIT_MASK 0x40U
#define RDB_STATUS_RXFR1_BIT_OFFSET (5U)
#define RDB_STATUS_RXFR1_BIT_LEN (1U)
#define RDB_STATUS_RXFR1_BIT_MASK 0x20U
#define RDB_STATUS_RXFCG1_BIT_OFFSET (4U)
#define RDB_STATUS_RXFCG1_BIT_LEN (1U)
#define RDB_STATUS_RXFCG1_BIT_MASK 0x10U
#define RDB_STATUS_CP_ERR0_BIT_OFFSET (3U)
#define RDB_STATUS_CP_ERR0_BIT_LEN (1U)
#define RDB_STATUS_CP_ERR0_BIT_MASK 0x8U
#define RDB_STATUS_CIADONE0_BIT_OFFSET (2U)
#define RDB_STATUS_CIADONE0_BIT_LEN (1U)
#define RDB_STATUS_CIADONE0_BIT_MASK 0x4U
#define RDB_STATUS_RXFR0_BIT_OFFSET (1U)
#define RDB_STATUS_RXFR0_BIT_LEN (1U)
#define RDB_STATUS_RXFR0_BIT_MASK 0x2U
#define RDB_STATUS_RXFCG0_BIT_OFFSET (0U)
#define RDB_STATUS_RXFCG0_BIT_LEN (1U)
#define RDB_STATUS_RXFCG0_BIT_MASK 0x1U
/******************************************************************************
* @brief Bit definitions for register RDB_DIAG_MODE
**/
#define RDB_DIAG_MODE_ID 0x10028
#define RDB_DIAG_MODE_LEN (4U)
#define RDB_DIAG_MODE_MASK 0xFFFFFFFFUL
#define RDB_DIAG_MODE_RDB_DMODE_BIT_OFFSET (0U)
#define RDB_DIAG_MODE_RDB_DMODE_BIT_LEN (3U)
#define RDB_DIAG_MODE_RDB_DMODE_BIT_MASK 0x7U
/******************************************************************************
* @brief Bit definitions for register AES_CFG
**/
#define AES_CFG_ID 0x10030
#define AES_CFG_LEN (4U)
#define AES_CFG_MASK 0xFFFFFFFFUL
#define AES_CFG_KEY_OTP_BIT_OFFSET (12U)
#define AES_CFG_KEY_OTP_BIT_LEN (1U)
#define AES_CFG_KEY_OTP_BIT_MASK 0x1000U
#define AES_CFG_CORE_SEL_BIT_OFFSET (11U)
#define AES_CFG_CORE_SEL_BIT_LEN (1U)
#define AES_CFG_CORE_SEL_BIT_MASK 0x800U
#define AES_CFG_TAG_SIZE_BIT_OFFSET (8U)
#define AES_CFG_TAG_SIZE_BIT_LEN (3U)
#define AES_CFG_TAG_SIZE_BIT_MASK 0x700U
#define AES_CFG_KEY_SRC_BIT_OFFSET (7U)
#define AES_CFG_KEY_SRC_BIT_LEN (1U)
#define AES_CFG_KEY_SRC_BIT_MASK 0x80U
#define AES_CFG_KEY_LOAD_BIT_OFFSET (6U)
#define AES_CFG_KEY_LOAD_BIT_LEN (1U)
#define AES_CFG_KEY_LOAD_BIT_MASK 0x40U
#define AES_CFG_KEY_ADDR_BIT_OFFSET (3U)
#define AES_CFG_KEY_ADDR_BIT_LEN (3U)
#define AES_CFG_KEY_ADDR_BIT_MASK 0x38U
#define AES_CFG_KEY_SIZE_BIT_OFFSET (1U)
#define AES_CFG_KEY_SIZE_BIT_LEN (2U)
#define AES_CFG_KEY_SIZE_BIT_MASK 0x6U
#define AES_CFG_MODE_BIT_OFFSET (0U)
#define AES_CFG_MODE_BIT_LEN (1U)
#define AES_CFG_MODE_BIT_MASK 0x1U
/******************************************************************************
* @brief Bit definitions for register AES_IV0
**/
#define AES_IV0_ID 0x10034
#define AES_IV0_LEN (4U)
#define AES_IV0_MASK 0xFFFFFFFFUL
/******************************************************************************
* @brief Bit definitions for register AES_IV1
**/
#define AES_IV1_ID 0x10038
#define AES_IV1_LEN (4U)
#define AES_IV1_MASK 0xFFFFFFFFUL
/******************************************************************************
* @brief Bit definitions for register AES_IV2
**/
#define AES_IV2_ID 0x1003c
#define AES_IV2_LEN (4U)
#define AES_IV2_MASK 0xFFFFFFFFUL
/******************************************************************************
* @brief Bit definitions for register AES_IV3
**/
#define AES_IV3_ID 0x10040
#define AES_IV3_LEN (4U)
#define AES_IV3_MASK 0xFFFFFFFFUL
/******************************************************************************
* @brief Bit definitions for register DMA_CFG0
**/
#define DMA_CFG0_ID 0x10044
#define DMA_CFG0_LEN (4U)
#define DMA_CFG0_MASK 0xFFFFFFFFUL
#define DMA_CFG0_CP_END_SEL_BIT_OFFSET (26U)
#define DMA_CFG0_CP_END_SEL_BIT_LEN (1U)
#define DMA_CFG0_CP_END_SEL_BIT_MASK 0x4000000UL
#define DMA_CFG0_DST_ADDR_BIT_OFFSET (16U)
#define DMA_CFG0_DST_ADDR_BIT_LEN (10U)
#define DMA_CFG0_DST_ADDR_BIT_MASK 0x3ff0000UL
#define DMA_CFG0_DST_PORT_BIT_OFFSET (13U)
#define DMA_CFG0_DST_PORT_BIT_LEN (3U)
#define DMA_CFG0_DST_PORT_BIT_MASK 0xe000U
#define DMA_CFG0_SRC_ADDR_BIT_OFFSET (3U)
#define DMA_CFG0_SRC_ADDR_BIT_LEN (10U)
#define DMA_CFG0_SRC_ADDR_BIT_MASK 0x1ff8U
#define DMA_CFG0_SRC_PORT_BIT_OFFSET (0U)
#define DMA_CFG0_SRC_PORT_BIT_LEN (3U)
#define DMA_CFG0_SRC_PORT_BIT_MASK 0x7U
/******************************************************************************
* @brief Bit definitions for register DMA_CFG1
**/
#define DMA_CFG1_ID 0x10048
#define DMA_CFG1_LEN (4U)
#define DMA_CFG1_MASK 0xFFFFFFFFUL
#define DMA_CFG1_PYLD_SIZE_BIT_OFFSET (7U)
#define DMA_CFG1_PYLD_SIZE_BIT_LEN (10U)
#define DMA_CFG1_PYLD_SIZE_BIT_MASK 0x1ff80UL
#define DMA_CFG1_HDR_SIZE_BIT_OFFSET (0U)
#define DMA_CFG1_HDR_SIZE_BIT_LEN (7U)
#define DMA_CFG1_HDR_SIZE_BIT_MASK 0x7fU
/******************************************************************************
* @brief Bit definitions for register AES_START
**/
#define AES_START_ID 0x1004c
#define AES_START_LEN (4U)
#define AES_START_MASK 0xFFFFFFFFUL
#define AES_START_AES_START_BIT_OFFSET (0U)
#define AES_START_AES_START_BIT_LEN (1U)
#define AES_START_AES_START_BIT_MASK 0x1U
/******************************************************************************
* @brief Bit definitions for register AES_STS
**/
#define AES_STS_ID 0x10050
#define AES_STS_LEN (4U)
#define AES_STS_MASK 0xFFFFFFFFUL
#define AES_STS_RAM_FULL_BIT_OFFSET (5U)
#define AES_STS_RAM_FULL_BIT_LEN (1U)
#define AES_STS_RAM_FULL_BIT_MASK 0x20U
#define AES_STS_RAM_EMPTY_BIT_OFFSET (4U)
#define AES_STS_RAM_EMPTY_BIT_LEN (1U)
#define AES_STS_RAM_EMPTY_BIT_MASK 0x10U
#define AES_STS_MEM_CONF_BIT_OFFSET (3U)
#define AES_STS_MEM_CONF_BIT_LEN (1U)
#define AES_STS_MEM_CONF_BIT_MASK 0x8U
#define AES_STS_TRANS_ERR_BIT_OFFSET (2U)
#define AES_STS_TRANS_ERR_BIT_LEN (1U)
#define AES_STS_TRANS_ERR_BIT_MASK 0x4U
#define AES_STS_AUTH_ERR_BIT_OFFSET (1U)
#define AES_STS_AUTH_ERR_BIT_LEN (1U)
#define AES_STS_AUTH_ERR_BIT_MASK 0x2U
#define AES_STS_AES_DONE_BIT_OFFSET (0U)
#define AES_STS_AES_DONE_BIT_LEN (1U)
#define AES_STS_AES_DONE_BIT_MASK 0x1U
/******************************************************************************
* @brief Bit definitions for register AES_KEY0
**/
#define AES_KEY0_ID 0x10054
#define AES_KEY0_LEN (4U)
#define AES_KEY0_MASK 0xFFFFFFFFUL
/******************************************************************************
* @brief Bit definitions for register AES_KEY1
**/
#define AES_KEY1_ID 0x10058
#define AES_KEY1_LEN (4U)
#define AES_KEY1_MASK 0xFFFFFFFFUL
/******************************************************************************
* @brief Bit definitions for register AES_KEY2
**/
#define AES_KEY2_ID 0x1005c
#define AES_KEY2_LEN (4U)
#define AES_KEY2_MASK 0xFFFFFFFFUL
/******************************************************************************
* @brief Bit definitions for register AES_KEY3
**/
#define AES_KEY3_ID 0x10060
#define AES_KEY3_LEN (4U)
#define AES_KEY3_MASK 0xFFFFFFFFUL
/******************************************************************************
* @brief Bit definitions for register STS_CFG0
**/
#define STS_CFG0_ID 0x20000
#define STS_CFG0_LEN (4U)
#define STS_CFG0_MASK 0xFFFFFFFFUL
#define STS_CFG0_CPS_LEN_BIT_OFFSET (0U)
#define STS_CFG0_CPS_LEN_BIT_LEN (8U)
#define STS_CFG0_CPS_LEN_BIT_MASK 0xffU
/******************************************************************************
* @brief Bit definitions for register STS_CTRL
**/
#define STS_CTRL_ID 0x20004
#define STS_CTRL_LEN (4U)
#define STS_CTRL_MASK 0xFFFFFFFFUL
#define STS_CTRL_RST_LAST_BIT_OFFSET (1U)
#define STS_CTRL_RST_LAST_BIT_LEN (1U)
#define STS_CTRL_RST_LAST_BIT_MASK 0x2U
#define STS_CTRL_LOAD_IV_BIT_OFFSET (0U)
#define STS_CTRL_LOAD_IV_BIT_LEN (1U)
#define STS_CTRL_LOAD_IV_BIT_MASK 0x1U
/******************************************************************************
* @brief Bit definitions for register STS_STS
**/
#define STS_STS_ID 0x20008
#define STS_STS_LEN (4U)
#define STS_STS_MASK 0xFFFFFFFFUL
#define STS_STS_ACC_QUAL_BIT_OFFSET (0U)
#define STS_STS_ACC_QUAL_BIT_LEN (12U)
#define STS_STS_ACC_QUAL_BIT_MASK 0xfffU
/******************************************************************************
* @brief Bit definitions for register STS_KEY0
**/
#define STS_KEY0_ID 0x2000c
#define STS_KEY0_LEN (4U)
#define STS_KEY0_MASK 0xFFFFFFFFUL
/******************************************************************************
* @brief Bit definitions for register STS_KEY1
**/
#define STS_KEY1_ID 0x20010
#define STS_KEY1_LEN (4U)
#define STS_KEY1_MASK 0xFFFFFFFFUL
/******************************************************************************
* @brief Bit definitions for register STS_KEY2
**/
#define STS_KEY2_ID 0x20014
#define STS_KEY2_LEN (4U)
#define STS_KEY2_MASK 0xFFFFFFFFUL
/******************************************************************************
* @brief Bit definitions for register STS_KEY3
**/
#define STS_KEY3_ID 0x20018
#define STS_KEY3_LEN (4U)
#define STS_KEY3_MASK 0xFFFFFFFFUL
/******************************************************************************
* @brief Bit definitions for register STS_IV0
**/
#define STS_IV0_ID 0x2001c
#define STS_IV0_LEN (4U)
#define STS_IV0_MASK 0xFFFFFFFFUL
/******************************************************************************
* @brief Bit definitions for register STS_IV1
**/
#define STS_IV1_ID 0x20020
#define STS_IV1_LEN (4U)
#define STS_IV1_MASK 0xFFFFFFFFUL
/******************************************************************************
* @brief Bit definitions for register STS_IV2
**/
#define STS_IV2_ID 0x20024
#define STS_IV2_LEN (4U)
#define STS_IV2_MASK 0xFFFFFFFFUL
/******************************************************************************
* @brief Bit definitions for register STS_IV3
**/
#define STS_IV3_ID 0x20028
#define STS_IV3_LEN (4U)
#define STS_IV3_MASK 0xFFFFFFFFUL
/******************************************************************************
* @brief Bit definitions for register LCSS_MARGIN
**/
#define LCSS_MARGIN_ID 0x20034
/******************************************************************************
* @brief Bit definitions for register DGC_CFG
**/
#define DGC_CFG_ID 0x30018
#define DGC_CFG_LEN (4U)
#define DGC_CFG_MASK 0xFFFFFFFFUL
#define DGC_CFG_THR_64_BIT_OFFSET (9U)
#define DGC_CFG_THR_64_BIT_LEN (6U)
#define DGC_CFG_THR_64_BIT_MASK 0x7e00U
#define DGC_CFG_RX_TUNE_EN_BIT_OFFSET (0U)
#define DGC_CFG_RX_TUNE_EN_BIT_LEN (1U)
#define DGC_CFG_RX_TUNE_EN_BIT_MASK 0x1U
/******************************************************************************
* @brief Bit definitions for register DGC_CFG0
**/
#define DGC_CFG0_ID 0x3001c
#define DGC_CFG0_LEN (4U)
#define DGC_CFG0_MASK 0xFFFFFFFFUL
/******************************************************************************
* @brief Bit definitions for register DGC_CFG1
**/
#define DGC_CFG1_ID 0x30020
#define DGC_CFG1_LEN (4U)
#define DGC_CFG1_MASK 0xFFFFFFFFUL
/******************************************************************************
* @brief Bit definitions for register DGC_LUT_0_CFG
**/
#define DGC_LUT_0_CFG_ID 0x30038
#define DGC_LUT_0_CFG_LEN (4U)
#define DGC_LUT_0_CFG_MASK 0xFFFFFFFFUL
/******************************************************************************
* @brief Bit definitions for register DGC_LUT_1_CFG
**/
#define DGC_LUT_1_CFG_ID 0x3003c
#define DGC_LUT_1_CFG_LEN (4U)
#define DGC_LUT_1_CFG_MASK 0xFFFFFFFFUL
/******************************************************************************
* @brief Bit definitions for register DGC_LUT_2_CFG
**/
#define DGC_LUT_2_CFG_ID 0x30040
#define DGC_LUT_2_CFG_LEN (4U)
#define DGC_LUT_2_CFG_MASK 0xFFFFFFFFUL
/******************************************************************************
* @brief Bit definitions for register DGC_LUT_3_CFG
**/
#define DGC_LUT_3_CFG_ID 0x30044
#define DGC_LUT_3_CFG_LEN (4U)
#define DGC_LUT_3_CFG_MASK 0xFFFFFFFFUL
/******************************************************************************
* @brief Bit definitions for register DGC_LUT_4_CFG
**/