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written in Verilog
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CNN acceleration on virtex-7 FPGA with verilog HDL
Implementation of CNN using Verilog
通过学习《自己动手写CPU》，将书中实现的兼容MIPS32指令集架构的处理器——OpenMIPS（五级流水线结构），简化成单指令周期实现的处理器
The final project of computer architecture and it is a 5-stage mips CPU implemented by Verilog.
Final project of Fall 2017 Digital Logic at Tongji Univ.
codes for my juniors majored in computer science in Tongji University