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Starred repositories

5 stars written in Verilog
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olofk / serv

SERV - The SErial RISC-V CPU

Verilog 1,462 193 Updated Dec 18, 2024

Wren6991 / Hazard3

3-stage RV32IMACZb* processor with debug

Verilog 746 50 Updated Dec 25, 2024

zephray / VerilogBoy

A Pi emulating a GameBoy sounds cheap. What about an FPGA?

Verilog 467 57 Updated Dec 10, 2022

open-fpga / core-template

A template for getting started with FPGA core development

Verilog 112 16 Updated May 4, 2023

tomverbeure / panologic

PanoLogic Zero Client G1 reverse engineering info

Verilog 72 11 Updated Apr 2, 2024

Starred topics