PicoRV32 - A Size-Optimized RISC-V CPU

SERV - The SErial RISC-V CPU

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

Project Apicula 🐝: bitstream documentation for Gowin FPGAs

current focus on Colorlight i5 and i9 & i9plus module

Various iCE40 cores / projects to play around with (mostly targeted at the icebreaker)

PACoGen: Posit Arithmetic Core Generator

Experiments with Yosys cxxrtl backend

Implementation of the SHA256 Algorithm in Verilog

EVEREST: e-Versatile Research Stick for peoples

Mega/Xmega soft core RTL design.