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README
README
 
 
contrib
contrib
 
 
contrib.out
contrib.out
 
 
contrib_inst.v
contrib_inst.v
 
 
contrib_mem.v
contrib_mem.v
 
 
contrib_mux.v
contrib_mux.v
 
 
contrib_net1.v
contrib_net1.v
 
 
contrib_psrn.v
contrib_psrn.v
 
 
counter.v
counter.v
 
 
dec
dec
 
 
dec.out
dec.out
 
 
dec001_delay.v
dec001_delay.v
 
 
dec002_posneg.v
dec002_posneg.v
 
 
dec003_posneg.v
dec003_posneg.v
 
 
expr
expr
 
 
expr.out
expr.out
 
 
expr_add.v
expr_add.v
 
 
expr_andand.v
expr_andand.v
 
 
expr_concat.v
expr_concat.v
 
 
expr_eqeq.v
expr_eqeq.v
 
 
expr_eqeqeq.v
expr_eqeqeq.v
 
 
expr_grteq.v
expr_grteq.v
 
 
expr_grtthan.v
expr_grtthan.v
 
 
expr_invert.v
expr_invert.v
 
 
expr_leseq.v
expr_leseq.v
 
 
expr_lesthan.v
expr_lesthan.v
 
 
expr_logand.v
expr_logand.v
 
 
expr_logor.v
expr_logor.v
 
 
expr_logxor.v
expr_logxor.v
 
 
expr_lshift.v
expr_lshift.v
 
 
expr_mintypmax.v
expr_mintypmax.v
 
 
expr_not.v
expr_not.v
 
 
expr_noteq.v
expr_noteq.v
 
 
expr_noteqeq.v
expr_noteqeq.v
 
 
expr_oror.v
expr_oror.v
 
 
expr_qstr.v
expr_qstr.v
 
 
expr_rshift.v
expr_rshift.v
 
 
expr_sub.v
expr_sub.v
 
 
expr_ternary.v
expr_ternary.v
 
 
mi
mi
 
 
mi.out
mi.out
 
 
mi001_regdecl.v
mi001_regdecl.v
 
 
mi002_always.v
mi002_always.v
 
 
mi003_modinst.v
mi003_modinst.v
 
 
mi004_function.v
mi004_function.v
 
 
mi005_task.v
mi005_task.v
 
 
mi006_assign.v
mi006_assign.v
 
 
mi007_intdecl.v
mi007_intdecl.v
 
 
mi008_memdecl.v
mi008_memdecl.v
 
 
mi009_paramdecl.v
mi009_paramdecl.v
 
 
mi010_paramdecl.v
mi010_paramdecl.v
 
 
minsim.v
minsim.v
 
 
ripple.v
ripple.v
 
 
sio85.v
sio85.v
 
 
stmt
stmt
 
 
stmt.out
stmt.out
 
 
stmt001_task.v
stmt001_task.v
 
 
stmt002_bassign.v
stmt002_bassign.v
 
 
stmt003_if.v
stmt003_if.v
 
 
stmt004_ifelse.v
stmt004_ifelse.v
 
 
stmt005_case.v
stmt005_case.v
 
 
stmt006_for.v
stmt006_for.v
 
 
stmt007_forever.v
stmt007_forever.v
 
 
stmt008_repeat.v
stmt008_repeat.v
 
 
stmt009_while.v
stmt009_while.v
 
 
stmt010_nbassign.v
stmt010_nbassign.v
 
 
vbs_output
vbs_output
 
 
vectors.v
vectors.v
 
 
wt_4_3p03p03p03p0.v
wt_4_3p03p03p03p0.v
 
 
wt_4_3p03p03p03p0_test.v
wt_4_3p03p03p03p0_test.v
 
 
x
x
 
 
x.out
x.out
 
 
x_allev.v
x_allev.v
 
 
x_allexpr.v
x_allexpr.v
 
 
x_bases.v
x_bases.v
 
 
x_bit.v
x_bit.v
 
 
x_comment.v
x_comment.v
 
 
x_counter.v
x_counter.v
 
 
x_cport.v
x_cport.v
 
 
x_dae.v
x_dae.v
 
 
x_delayedloop.v
x_delayedloop.v
 
 
x_dividev1.v
x_dividev1.v
 
 
x_dividev2.v
x_dividev2.v
 
 
x_fifo.v
x_fifo.v
 
 
x_inflp.v
x_inflp.v
 
 
x_lpevctl.v
x_lpevctl.v
 
 
x_monitor.v
x_monitor.v
 
 
x_multv1.v
x_multv1.v
 
 
x_multv2.v
x_multv2.v
 
 
x_nds.v
x_nds.v
 
 
x_nested.v
x_nested.v
 
 
x_range.v
x_range.v
 
 

README

The examples in this directory were obtainied from these sources:

1) The vbs-1.3.7 release.  This is another simulator, written by Jimen
   Ching <[email protected]> and others.  The vbs project web site is
   www.seul.org.  The vbs code is available from www.flex.com/~jching.

   The shell script files were added.  The results can be compared to
   the vbs_output file, which contains the corresponding results
   from vbs.

   files: contrib_*, dec00?_*, expr_*, mi00?_*, stmt00?_*, wt*, x_*

   NOTE: the contrib_mem.v test taks a long time and lots of memory.

2) The "free" Verilog simulator from VeriWell.  This is a commercial
   simulator evailable as a free evaluation verion.  Do a web search
   for "veriwell" to find the current distribution point.

   files: minsim.v, sio85.v, vectors.v

   note: the sio85.v simulation seems to loop forever, or at least
   longer than my patience.

3) Unknown
   files: ripple.v, counter.v