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top.rpt
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cpldfit: version P.20131013 Xilinx Inc.
Fitter Report
Design Name: top Date: 11- 8-2018, 11:20AM
Device Used: XC9572XL-10-PC44
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
8 /72 ( 11%) 14 /360 ( 4%) 15 /216 ( 7%) 3 /72 ( 4%) 12 /34 ( 35%)
** Function Block Resources **
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 3/18 6/54 6/90 3/ 9
FB2 1/18 3/54 2/90 5/ 9
FB3 3/18 6/54 6/90 2/ 9
FB4 1/18 0/54 0/90 2/ 7
----- ----- ----- -----
8/72 15/216 14/360 12/34
* - Resource is exhausted
** Global Control Resources **
Signal 'clk' mapped onto global clock net GCK1.
Global output enable net(s) unused.
Signal 'reset' mapped onto global set/reset net GSR.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Input : 4 4 | I/O : 9 28
Output : 6 6 | GCK/IO : 1 3
Bidirectional : 0 0 | GTS/IO : 1 2
GCK : 1 1 | GSR/IO : 1 1
GTS : 0 0 |
GSR : 1 1 |
---- ----
Total 12 12
** Power Data **
There are 8 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
************************** Errors and Warnings ***************************
WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
use the default filename of 'top.ise'.
************************* Summary of Mapped Logic ************************
** 6 Outputs **
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
SW1 2 3 FB1_2 1 I/O O STD FAST
DB<0> 1 3 FB1_8 4 I/O O STD FAST
SW2 2 3 FB2_2 35 I/O O STD FAST
DA<0> 2 5 FB3_2 11 I/O O STD FAST SET
DA<1> 0 0 FB3_14 19 I/O O STD FAST
DB<1> 0 0 FB4_2 25 I/O O STD FAST
** 2 Buried Nodes **
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
estado_FSM_FFd2 3 6 FB1_18 STD RESET
estado_FSM_FFd3 4 6 FB3_18 STD RESET
** 6 Inputs **
Signal Loc Pin Pin Pin
Name No. Type Use
clk FB1_9 5~ GCK/I/O GCK
S1 FB2_6 37 I/O I
reset FB2_9 39~ GSR/I/O GSR
S3 FB2_11 40 GTS/I/O I
S4 FB2_17 44 I/O I
S2 FB4_8 27 I/O I
Legend:
Pin No. - ~ - User Assigned
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X - Signal used as input to the macrocell logic.
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 6/48
Number of signals used by logic mapping into function block: 6
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB1_1 (b)
SW1 2 0 0 3 FB1_2 1 I/O O
(unused) 0 0 0 5 FB1_3 (b)
(unused) 0 0 0 5 FB1_4 (b)
(unused) 0 0 0 5 FB1_5 2 I/O
(unused) 0 0 0 5 FB1_6 3 I/O
(unused) 0 0 0 5 FB1_7 (b)
DB<0> 1 0 0 4 FB1_8 4 I/O O
(unused) 0 0 0 5 FB1_9 5 GCK/I/O GCK
(unused) 0 0 0 5 FB1_10 (b)
(unused) 0 0 0 5 FB1_11 6 GCK/I/O
(unused) 0 0 0 5 FB1_12 (b)
(unused) 0 0 0 5 FB1_13 (b)
(unused) 0 0 0 5 FB1_14 7 GCK/I/O
(unused) 0 0 0 5 FB1_15 8 I/O
(unused) 0 0 0 5 FB1_16 (b)
(unused) 0 0 0 5 FB1_17 9 I/O
estado_FSM_FFd2 3 0 0 2 FB1_18 (b) (b)
Signals Used by Logic in Function Block
1: DA<0> 3: S3 5: estado_FSM_FFd2
2: S1 4: S4 6: estado_FSM_FFd3
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
SW1 X...XX.................................. 3
DB<0> X...XX.................................. 3
estado_FSM_FFd2 XXXXXX.................................. 6
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 3/51
Number of signals used by logic mapping into function block: 3
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB2_1 (b)
SW2 2 0 0 3 FB2_2 35 I/O O
(unused) 0 0 0 5 FB2_3 (b)
(unused) 0 0 0 5 FB2_4 (b)
(unused) 0 0 0 5 FB2_5 36 I/O
(unused) 0 0 0 5 FB2_6 37 I/O I
(unused) 0 0 0 5 FB2_7 (b)
(unused) 0 0 0 5 FB2_8 38 I/O
(unused) 0 0 0 5 FB2_9 39 GSR/I/O GSR
(unused) 0 0 0 5 FB2_10 (b)
(unused) 0 0 0 5 FB2_11 40 GTS/I/O I
(unused) 0 0 0 5 FB2_12 (b)
(unused) 0 0 0 5 FB2_13 (b)
(unused) 0 0 0 5 FB2_14 42 GTS/I/O
(unused) 0 0 0 5 FB2_15 43 I/O
(unused) 0 0 0 5 FB2_16 (b)
(unused) 0 0 0 5 FB2_17 44 I/O I
(unused) 0 0 0 5 FB2_18 (b)
Signals Used by Logic in Function Block
1: DA<0> 2: estado_FSM_FFd2 3: estado_FSM_FFd3
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
SW2 XXX..................................... 3
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 6/48
Number of signals used by logic mapping into function block: 6
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB3_1 (b)
DA<0> 2 0 0 3 FB3_2 11 I/O O
(unused) 0 0 0 5 FB3_3 (b)
(unused) 0 0 0 5 FB3_4 (b)
(unused) 0 0 0 5 FB3_5 12 I/O
(unused) 0 0 0 5 FB3_6 (b)
(unused) 0 0 0 5 FB3_7 (b)
(unused) 0 0 0 5 FB3_8 13 I/O
(unused) 0 0 0 5 FB3_9 14 I/O
(unused) 0 0 0 5 FB3_10 (b)
(unused) 0 0 0 5 FB3_11 18 I/O
(unused) 0 0 0 5 FB3_12 (b)
(unused) 0 0 0 5 FB3_13 (b)
DA<1> 0 0 0 5 FB3_14 19 I/O O
(unused) 0 0 0 5 FB3_15 20 I/O
(unused) 0 0 0 5 FB3_16 24 I/O
(unused) 0 0 0 5 FB3_17 22 I/O
estado_FSM_FFd3 4 0 0 1 FB3_18 (b) (b)
Signals Used by Logic in Function Block
1: DA<0> 3: S2 5: estado_FSM_FFd2
2: S1 4: S3 6: estado_FSM_FFd3
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
DA<0> XX.XXX.................................. 5
DA<1> ........................................ 0
estado_FSM_FFd3 XXXXXX.................................. 6
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 0/54
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB4_1 (b)
DB<1> 0 0 0 5 FB4_2 25 I/O O
(unused) 0 0 0 5 FB4_3 (b)
(unused) 0 0 0 5 FB4_4 (b)
(unused) 0 0 0 5 FB4_5 26 I/O
(unused) 0 0 0 5 FB4_6 (b)
(unused) 0 0 0 5 FB4_7 (b)
(unused) 0 0 0 5 FB4_8 27 I/O I
(unused) 0 0 0 5 FB4_9 (b)
(unused) 0 0 0 5 FB4_10 (b)
(unused) 0 0 0 5 FB4_11 28 I/O
(unused) 0 0 0 5 FB4_12 (b)
(unused) 0 0 0 5 FB4_13 (b)
(unused) 0 0 0 5 FB4_14 29 I/O
(unused) 0 0 0 5 FB4_15 33 I/O
(unused) 0 0 0 5 FB4_16 (b)
(unused) 0 0 0 5 FB4_17 34 I/O
(unused) 0 0 0 5 FB4_18 (b)
Signals Used by Logic in Function Block
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
DB<1> ........................................ 0
0----+----1----+----2----+----3----+----4
0 0 0 0
******************************* Equations ********************************
********** Mapped Logic **********
FDCPE_DA0: FDCPE port map (DA(0),DA_D(0),clk,'0',reset);
DA_D(0) <= ((NOT S3 AND NOT DA(0))
OR (estado_FSM_FFd3 AND NOT estado_FSM_FFd2 AND S1 AND NOT S3));
DA(1) <= '0';
DB(0) <= NOT ((estado_FSM_FFd3 AND estado_FSM_FFd2 AND DA(0)));
DB(1) <= '0';
SW1 <= ((NOT DA(0))
OR (estado_FSM_FFd3 AND NOT estado_FSM_FFd2));
SW2 <= ((NOT DA(0))
OR (estado_FSM_FFd3 AND NOT estado_FSM_FFd2));
FDCPE_estado_FSM_FFd2: FDCPE port map (estado_FSM_FFd2,estado_FSM_FFd2_D,clk,reset,'0');
estado_FSM_FFd2_D <= ((estado_FSM_FFd2 AND NOT S4)
OR (S3 AND NOT DA(0))
OR (estado_FSM_FFd3 AND NOT estado_FSM_FFd2 AND S1 AND S3));
FDCPE_estado_FSM_FFd3: FDCPE port map (estado_FSM_FFd3,estado_FSM_FFd3_D,clk,reset,'0');
estado_FSM_FFd3_D <= ((NOT estado_FSM_FFd3 AND NOT S2)
OR (NOT estado_FSM_FFd2 AND S1)
OR (estado_FSM_FFd3 AND NOT estado_FSM_FFd2 AND S3)
OR (NOT estado_FSM_FFd3 AND NOT estado_FSM_FFd2 AND NOT DA(0)));
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE);
FTCPE (Q,D,C,CLR,PRE,CE);
LDCP (Q,D,G,CLR,PRE);
****************************** Device Pin Out *****************************
Device : XC9572XL-10-PC44
--------------------------------
/6 5 4 3 2 1 44 43 42 41 40 \
| 7 39 |
| 8 38 |
| 9 37 |
| 10 36 |
| 11 XC9572XL-10-PC44 35 |
| 12 34 |
| 13 33 |
| 14 32 |
| 15 31 |
| 16 30 |
| 17 29 |
\ 18 19 20 21 22 23 24 25 26 27 28 /
--------------------------------
Pin Signal Pin Signal
No. Name No. Name
1 SW1 23 GND
2 KPR 24 KPR
3 KPR 25 DB<1>
4 DB<0> 26 KPR
5 clk 27 S2
6 KPR 28 KPR
7 KPR 29 KPR
8 KPR 30 TDO
9 KPR 31 GND
10 GND 32 VCC
11 DA<0> 33 KPR
12 KPR 34 KPR
13 KPR 35 SW2
14 KPR 36 KPR
15 TDI 37 S1
16 TMS 38 KPR
17 TCK 39 reset
18 KPR 40 S3
19 DA<1> 41 VCC
20 KPR 42 KPR
21 VCC 43 KPR
22 KPR 44 S4
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
KPR = Unused I/O with weak keeper (leave unconnected)
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xc9572xl-10-PC44
Optimization Method : SPEED
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : FAST
Power Mode : STD
Ground on Unused IOs : OFF
Set I/O Pin Termination : KEEPER
Global Clock Optimization : ON
Global Set/Reset Optimization : ON
Global Ouput Enable Optimization : ON
Input Limit : 54
Pterm Limit : 25