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webtalk_pn.xml
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webtalk_pn.xml
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<?xml version="1.0" encoding="UTF-8" ?>
<document>
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Thu Nov 08 11:19:37 2018">
<section name="Project Information" visible="false">
<property name="ProjectID" value="654CE3B48F76419AAF5B59FE2723A844" type="project"/>
<property name="ProjectIteration" value="0" type="project"/>
<property name="ProjectFile" value="C:/Users/igna_/Documents/Tecnicas Digitales I/trenes/trenes.xise" type="project"/>
<property name="ProjectCreationTimestamp" value="2018-11-08T01:36:36" type="project"/>
</section>
<section name="Project Statistics" visible="true">
<property name="PROP_Enable_Message_Filtering" value="false" type="design"/>
<property name="PROP_FitterReportFormat" value="HTML" type="process"/>
<property name="PROP_LastAppliedGoal" value="Balanced" type="design"/>
<property name="PROP_LastAppliedStrategy" value="Xilinx Default (unlocked)" type="design"/>
<property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
<property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/>
<property name="PROP_SelectedInstanceHierarchicalPath" value="/testbench" type="process"/>
<property name="PROP_Simulator" value="ISim (VHDL/Verilog)" type="design"/>
<property name="PROP_SynthTopFile" value="changed" type="process"/>
<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/>
<property name="PROP_UseSmartGuide" value="false" type="design"/>
<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
<property name="PROP_intProjectCreationTimestamp" value="2018-11-08T01:36:36" type="design"/>
<property name="PROP_intWbtProjectID" value="654CE3B48F76419AAF5B59FE2723A844" type="design"/>
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
<property name="PROP_intWorkingDirUsed" value="No" type="design"/>
<property name="PROP_selectedSimRootSourceNode_behav" value="work.testbench" type="process"/>
<property name="PROP_xilxSynthMaxFanout" value="100000" type="process"/>
<property name="PROP_AutoTop" value="true" type="design"/>
<property name="PROP_DevFamily" value="XC9500XL CPLDs" type="design"/>
<property name="PROP_DevDevice" value="xc9572xl" type="design"/>
<property name="PROP_DevFamilyPMName" value="xc9500xl" type="design"/>
<property name="PROP_DevPackage" value="PC44" type="design"/>
<property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/>
<property name="PROP_DevSpeed" value="-10" type="design"/>
<property name="PROP_PreferredLanguage" value="Verilog" type="design"/>
<property name="FILE_VERILOG" value="2" type="source"/>
</section>
</application>
</document>