Lab3 Axilite Access GPIO pins

Design presentation

全端 IC 設計工程師伴學松 第十一次 Lab3
報告投影片

Run Compiling of Vitis HLS and Vivado

source run_main.sh

Run on FPGA

1. connect to remote PYNQ-Z2
2. create axi2gpio folder on jupyter notebook and upload bitstream, hex and ipynb files to axi2gpio folder
3. open axi2gpio_test.ipynb and run