The Back End (BE) comprises the execution engine for RISC-V instructions in a BlackParrot multicore processor. It contains the true architectural state for the processor and logically controls the FE's speculative execution.
Diagrams for the BE blocks can be found here. (Diagrams are WIP as of 1/30/2019)
The file bp_be_top.v defines the top level Back End module. This module is instantiated once per core in a BlackParrot multicore processor. This module consists of three major components: the Calculator and the Checker and the MMU. The Calculator is responsible for performing RISC-V instructions as well as detecting exception conditions. The Checker is reponsible for scheduling instruction execution by interfacing with the FE, preventing hazards from affecting correctness by determining the true next PC, gating incorrect PCs from entering the pipeline, as well as monitoring dependency information from the Calculator. The MMU handles virtual address translation and L1 caching, as well as interface with the ME.