iiitb_sqd_synth.v

/* Generated by Yosys 0.9 (git sha1 1979e0b) */

module Sequence_Detector_MOORE_Verilog(sequence_in, clock, reset, detector_out);
  wire _00_;
  wire _01_;
  wire _02_;
  wire _03_;
  wire _04_;
  wire [4:0] _05_;
  input clock;
  output detector_out;
  reg detector_out;
  input reset;
  input sequence_in;
  sky130_fd_sc_hd__clkinv_1 _06_ (
    .A(sequence_in),
    .Y(_04_)
  );
  sky130_fd_sc_hd__and2_0 _07_ (
    .A(sequence_in),
    .B(_05_[3]),
    .X(_03_)
  );
  sky130_fd_sc_hd__and2_0 _08_ (
    .A(sequence_in),
    .B(_05_[0]),
    .X(_02_)
  );
  sky130_fd_sc_hd__o21a_1 _09_ (
    .A1(detector_out),
    .A2(_05_[1]),
    .B1(sequence_in),
    .X(_01_)
  );
  sky130_fd_sc_hd__and2_0 _10_ (
    .A(sequence_in),
    .B(_05_[4]),
    .X(_00_)
  );
  reg _11_;
  always @(posedge clock or posedge reset)
    if (reset)
      _11_ <= 1;
    else
      _11_ <= _04_;
  assign _05_[0] = _11_;
  reg _12_;
  always @(posedge clock or posedge reset)
    if (reset)
      _12_ <= 0;
    else
      _12_ <= _00_;
  assign _05_[1] = _12_;
  always @(posedge clock or posedge reset)
    if (reset)
      detector_out <= 0;
    else
      detector_out <= _01_;
  reg _14_;
  always @(posedge clock or posedge reset)
    if (reset)
      _14_ <= 0;
    else
      _14_ <= _02_;
  assign _05_[3] = _14_;
  reg _15_;
  always @(posedge clock or posedge reset)
    if (reset)
      _15_ <= 0;
    else
      _15_ <= _03_;
  assign _05_[4] = _15_;
  assign _05_[2] = detector_out;
endmodule