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| 1 | +/* |
| 2 | + * Copyright (c) 2006-2025 RT-Thread Development Team |
| 3 | + * |
| 4 | + * SPDX-License-Identifier: Apache-2.0 |
| 5 | + * |
| 6 | + * Change Logs: |
| 7 | + * Date Author Notes |
| 8 | + * 2019-04-14 whj4674672 first version |
| 9 | + */ |
| 10 | +#include <rtthread.h> |
| 11 | +#include "stm32h7xx.h" |
| 12 | +#include "board.h" |
| 13 | +int mpu_init(void) |
| 14 | +{ |
| 15 | + MPU_Region_InitTypeDef MPU_InitStruct; |
| 16 | + |
| 17 | + /* Disable the MPU */ |
| 18 | + HAL_MPU_Disable(); |
| 19 | + |
| 20 | + /* Configure the MPU attributes as WT for AXI SRAM */ |
| 21 | + MPU_InitStruct.Enable = MPU_REGION_ENABLE; |
| 22 | + MPU_InitStruct.BaseAddress = 0x24000000; |
| 23 | + MPU_InitStruct.Size = MPU_REGION_SIZE_512KB; |
| 24 | + MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS; |
| 25 | + MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE; |
| 26 | + MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE; |
| 27 | + MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE; |
| 28 | + MPU_InitStruct.Number = MPU_REGION_NUMBER0; |
| 29 | + MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0; |
| 30 | + MPU_InitStruct.SubRegionDisable = 0X00; |
| 31 | + MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE; |
| 32 | + |
| 33 | + HAL_MPU_ConfigRegion(&MPU_InitStruct); |
| 34 | + |
| 35 | +#ifdef BSP_USING_SDRAM |
| 36 | + /* Configure the MPU attributes as WT for SDRAM */ |
| 37 | + MPU_InitStruct.Enable = MPU_REGION_ENABLE; |
| 38 | + MPU_InitStruct.BaseAddress = 0xC0000000; |
| 39 | + MPU_InitStruct.Size = MPU_REGION_SIZE_32MB; |
| 40 | + MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS; |
| 41 | + MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE; |
| 42 | + MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE; |
| 43 | + MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE; |
| 44 | + MPU_InitStruct.Number = MPU_REGION_NUMBER1; |
| 45 | + MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0; |
| 46 | + MPU_InitStruct.SubRegionDisable = 0x00; |
| 47 | + MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE; |
| 48 | + |
| 49 | + HAL_MPU_ConfigRegion(&MPU_InitStruct); |
| 50 | +#endif |
| 51 | + |
| 52 | +#ifdef BSP_USING_ETH_H750 |
| 53 | + /* Configure the MPU attributes as Device not cacheable |
| 54 | + for ETH DMA descriptors and RX Buffers*/ |
| 55 | + MPU_InitStruct.Enable = MPU_REGION_ENABLE; |
| 56 | + MPU_InitStruct.BaseAddress = 0x30040000; |
| 57 | + MPU_InitStruct.Size = MPU_REGION_SIZE_32KB; |
| 58 | + MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS; |
| 59 | + MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE; |
| 60 | + MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE; |
| 61 | + MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE; |
| 62 | + MPU_InitStruct.Number = MPU_REGION_NUMBER2; |
| 63 | + MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1; |
| 64 | + MPU_InitStruct.SubRegionDisable = 0x00; |
| 65 | + MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE; |
| 66 | + |
| 67 | + HAL_MPU_ConfigRegion(&MPU_InitStruct); |
| 68 | +#endif |
| 69 | + |
| 70 | + /* Configure the MPU attributes as WT for QSPI */ |
| 71 | + MPU_InitStruct.Enable = MPU_REGION_ENABLE; |
| 72 | + MPU_InitStruct.BaseAddress = 0x90000000; |
| 73 | + MPU_InitStruct.Size = MPU_REGION_SIZE_8MB; |
| 74 | + MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS; |
| 75 | + MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE; |
| 76 | + MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE; |
| 77 | + MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE; |
| 78 | + MPU_InitStruct.Number = MPU_REGION_NUMBER3; |
| 79 | + MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0; |
| 80 | + MPU_InitStruct.SubRegionDisable = 0X00; |
| 81 | + MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE; |
| 82 | + |
| 83 | + HAL_MPU_ConfigRegion(&MPU_InitStruct); |
| 84 | + |
| 85 | + /* Enable the MPU */ |
| 86 | + HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT); |
| 87 | + |
| 88 | + /* Enable CACHE */ |
| 89 | + SCB_EnableICache(); |
| 90 | + SCB_EnableDCache(); |
| 91 | + |
| 92 | + return RT_EOK; |
| 93 | + |
| 94 | +} |
| 95 | +INIT_BOARD_EXPORT(mpu_init); |
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