From 3de914eef55351e2e7395a8e8ae57553f6218516 Mon Sep 17 00:00:00 2001 From: Allan Sandfeld Jensen Date: Tue, 1 Oct 2024 12:06:14 +0200 Subject: [PATCH] Add ARM SVE detection Limited to ARM64 and little-endian to keep our code simple. Change-Id: Ie65f71a31ca98d6929561d4b2ee1e9332b3a82d8 Reviewed-by: Thiago Macieira --- cmake/QtCompilerOptimization.cmake | 1 + config.tests/arch/arch.cpp | 3 +++ configure.cmake | 7 +++++++ src/corelib/global/qsimd.cpp | 18 ++++++++++++++++-- src/corelib/global/qsimd_p.h | 7 +++++++ 5 files changed, 34 insertions(+), 2 deletions(-) diff --git a/cmake/QtCompilerOptimization.cmake b/cmake/QtCompilerOptimization.cmake index ac542e94510..3df4d777dce 100644 --- a/cmake/QtCompilerOptimization.cmake +++ b/cmake/QtCompilerOptimization.cmake @@ -66,6 +66,7 @@ if(GCC OR CLANG OR QCC) if(NOT UIKIT AND NOT QT_64BIT) set(QT_CFLAGS_NEON "${__prefix}-mfpu=neon") endif() + set(QT_CFLAGS_ARM_SVE "${__prefix}-march=armv8-a+sve") set(QT_CFLAGS_MIPS_DSP "${__prefix}-mdsp") set(QT_CFLAGS_MIPS_DSPR2 "${__prefix}-mdspr2") unset(__prefix) diff --git a/config.tests/arch/arch.cpp b/config.tests/arch/arch.cpp index ad9ef34039c..58595f0a2ec 100644 --- a/config.tests/arch/arch.cpp +++ b/config.tests/arch/arch.cpp @@ -251,6 +251,9 @@ const char msg2[] = "==Qt=magic=Qt== Sub-architecture:" #if defined(__ARM_FEATURE_CRYPTO) || (defined(_M_ARM64) && __ARM_ARCH >= 800) " crypto" #endif +#ifdef __ARM_FEATURE_SVE +" sve" +#endif // -- SPARC -- #ifdef __VIS__ diff --git a/configure.cmake b/configure.cmake index 0c77640598f..c748de32ed6 100644 --- a/configure.cmake +++ b/configure.cmake @@ -929,6 +929,13 @@ qt_feature_definition("arm_crypto" "QT_COMPILER_SUPPORTS_CRYPTO" VALUE "1") qt_feature_definition("arm_crypto" "QT_COMPILER_SUPPORTS_AES" VALUE "1") qt_feature_config("arm_crypto" QMAKE_PRIVATE_CONFIG) +qt_feature("arm_sve" PRIVATE + LABEL "SVE" + CONDITION ( TEST_architecture_arch STREQUAL arm64 ) AND TEST_arch_${TEST_architecture_arch}_subarch_sve +) +qt_feature_definition("arm_sve" "QT_COMPILER_SUPPORTS_SVE" VALUE "1") +qt_feature_config("arm_sve" QMAKE_PRIVATE_CONFIG) + qt_feature("wasm-simd128" PUBLIC LABEL "WebAssembly SIMD128" PURPOSE "Enables WebAssembly SIMD" diff --git a/src/corelib/global/qsimd.cpp b/src/corelib/global/qsimd.cpp index 28d25b5baca..b4fff814e6c 100644 --- a/src/corelib/global/qsimd.cpp +++ b/src/corelib/global/qsimd.cpp @@ -49,6 +49,7 @@ // copied from (Aarch64) #define HWCAP_AES (1 << 3) #define HWCAP_CRC32 (1 << 7) +#define HWCAP_SVE (1 << 22) // copied from #define AT_HWCAP 16 /* arch dependent hints at CPU capabilities */ @@ -75,13 +76,15 @@ uint arraysize(T (&)[N]) neon crc32 aes + sve */ static const char features_string[] = "\0" " neon\0" " crc32\0" - " aes\0"; -static const int features_indices[] = { 0, 1, 7, 14 }; + " aes\0" + " sve\0"; +static const int features_indices[] = { 0, 1, 7, 14, 19 }; #elif defined(Q_PROCESSOR_MIPS) /* Data: dsp @@ -118,6 +121,8 @@ static inline quint64 detectProcessorFeatures() features |= CpuFeatureCRC32; if (auxvHwCap & HWCAP_AES) features |= CpuFeatureAES; + if (auxvHwCap & HWCAP_SVE) + features |= CpuFeatureSVE; # else // For ARM32: if (auxvHwCap & HWCAP_NEON) @@ -155,6 +160,12 @@ static inline quint64 detectProcessorFeatures() #else if (sysctlbyname("hw.optional.arm.FEAT_AES", &feature, &len, nullptr, 0) == 0) features |= feature ? CpuFeatureAES : 0; +#endif +#if defined(__ARM_FEATURE_SVE) + features |= CpuFeatureSVE; +#else + if (sysctlbyname("hw.optional.arm.FEAT_SVE", &feature, &len, nullptr, 0) == 0) + features |= feature ? CpuFeatureSVE : 0; #endif return features; #elif defined(Q_OS_WIN) && defined(Q_PROCESSOR_ARM_64) @@ -174,6 +185,9 @@ static inline quint64 detectProcessorFeatures() #if defined(__ARM_FEATURE_CRYPTO) features |= CpuFeatureAES; #endif +#if defined(__ARM_FEATURE_SVE) + features |= CpuFeatureSVE; +#endif return features; } diff --git a/src/corelib/global/qsimd_p.h b/src/corelib/global/qsimd_p.h index b613e04985e..99786d92a0c 100644 --- a/src/corelib/global/qsimd_p.h +++ b/src/corelib/global/qsimd_p.h @@ -347,12 +347,15 @@ inline uint32x4_t qvsetq_n_u32(uint32_t a, uint32_t b, uint32_t c, uint32_t d) #if defined(Q_CC_CLANG) #define QT_FUNCTION_TARGET_STRING_AES "crypto" #define QT_FUNCTION_TARGET_STRING_CRC32 "crc" +#define QT_FUNCTION_TARGET_STRING_SVE "sve" #elif defined(Q_CC_GNU) #define QT_FUNCTION_TARGET_STRING_AES "+crypto" #define QT_FUNCTION_TARGET_STRING_CRC32 "+crc" +#define QT_FUNCTION_TARGET_STRING_SVE "+sve" #elif defined(Q_CC_MSVC) #define QT_FUNCTION_TARGET_STRING_AES #define QT_FUNCTION_TARGET_STRING_CRC32 +#define QT_FUNCTION_TARGET_STRING_SVE #endif #elif defined(Q_PROCESSOR_ARM_32) #if defined(Q_CC_CLANG) @@ -372,6 +375,7 @@ enum CPUFeatures { CpuFeatureCRC32 = 4, CpuFeatureAES = 8, CpuFeatureARM_CRYPTO = CpuFeatureAES, + CpuFeatureSVE = 16, #elif defined(Q_PROCESSOR_MIPS) CpuFeatureDSP = 2, CpuFeatureDSPR2 = 4, @@ -395,6 +399,9 @@ static const uint64_t qCompilerCpuFeatures = 0 | CpuFeatureAES #endif #endif // Q_OS_LINUX && Q_PROCESSOR_ARM64 +#if defined(__ARM_FEATURE_SVE) && defined(Q_PROCESSOR_ARM_64) + | CpuFeatureSVE +#endif #if defined __mips_dsp | CpuFeatureDSP #endif