forked from devbisme/skidl
-
Notifications
You must be signed in to change notification settings - Fork 0
/
index.html
2194 lines (1948 loc) · 202 KB
/
index.html
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
<!DOCTYPE html>
<html lang="en">
<head>
<title>SKiDL — SKiDL</title>
<meta charset="utf-8" />
<link rel="profile" href="http://gmpg.org/xfn/11" />
<link rel="stylesheet" type="text/css" href="/skidl/theme/css/style.css" />
<link rel='stylesheet' id='oswald-css' href='http://fonts.googleapis.com/css?family=Oswald&ver=3.3.2' type='text/css' media='all' />
<link rel="preconnect" href="https://fonts.googleapis.com">
<link rel="preconnect" href="https://fonts.gstatic.com" crossorigin>
<link href="https://fonts.googleapis.com/css2?family=Oswald&family=Roboto+Condensed&display=swap" rel="stylesheet">
<!-- <style type="text/css">
body.custom-background { background-color: #f5f5f5; }
</style> -->
<link rel="alternate" type="application/atom+xml"
title="SKiDL — Flux Atom"
href="/skidl/" />
<!--[if lte IE 8]><script src="/skidl/theme/js/html5shiv.js"></script><![endif]-->
</head>
<body class="home blog custom-background " >
<div id="container">
<div id="header">
<h1 id="site-title"><a href="/skidl"><img src="/skidl/images/banner.png" width="100%"></a></h1>
<!-- <h1 id="site-title"><a href="/skidl">SKiDL</a></h1> -->
</div><!-- /#banner -->
<div id="menu">
<div class="menu-navigation-container">
<ul id="menu-navigation" class="menu">
<li class="menu-item menu-item-type-post_type menu-item-object-page"><a href="https://github.com/devbisme/skidl">Github</a></li>
<li class="menu-item menu-item-type-post_type menu-item-object-page"><a href="https://github.com/devbisme/skidl/discussions">Forum</a></li>
<li class="menu-item menu-item-type-post_type menu-item-object-page"><a href="/skidl/category/posts.html">Blog</a></li>
<li class="menu-item menu-item-type-post_type menu-item-object-page"><a href="/skidl/api/html/index.html">API</a></li>
<li class="menu-item menu-item-type-post_type menu-item-object-page"><a href="/skidl/">Home</a></li>
</ul>
</div> <!--/#menu-navigation-container-->
</div><!-- /#menu -->
<div class="page-title">
</div>
<div id="contents">
<div class="page type-page status-publish hentry" id="post">
<div class="entry-meta">
<!-- <div class="comments"><a href="/skidl/pages/skidl.html#disqus_thread" title="Comment on SKiDL">Leave a comment</a></div> -->
<span class="cat-links"></span>
</div> <!-- /#entry-meta -->
<div class="main">
<h2 class="entry-title"><a href="/skidl/pages/skidl.html" title="Permalink to SKiDL" rel="bookmark">SKiDL</a></h2>
<div class="entry-content">
<h1 id="tldr">TL;DR</h1>
<p><strong>Never use a lousy schematic editor again!</strong>
SKiDL is a simple module that lets you describe electronic circuits using Python.
The resulting Python program outputs a netlist that a PCB layout tool uses to
create a finished circuit board.</p>
<h3 id="contents">Contents</h3>
<ul>
<li><a href="#tldr">TL;DR</a><ul>
<li><a href="#contents">Contents</a></li>
</ul>
</li>
<li><a href="#introduction">Introduction</a></li>
<li><a href="#installation">Installation</a></li>
<li><a href="#basic-usage">Basic Usage</a></li>
<li><a href="#accessing-skidl">Accessing SKiDL</a></li>
<li><a href="#finding-parts">Finding Parts</a><ul>
<li><a href="#command-line-searching">Command-line Searching</a></li>
<li><a href="#zyc-a-gui-search-tool">Zyc: A GUI Search Tool</a></li>
</ul>
</li>
<li><a href="#instantiating-parts">Instantiating Parts</a></li>
<li><a href="#connecting-pins">Connecting Pins</a></li>
<li><a href="#checking-for-errors">Checking for Errors</a></li>
<li><a href="#generating-a-netlist-or-pcb">Generating a Netlist or PCB</a></li>
<li><a href="#going-deeper">Going Deeper</a></li>
<li><a href="#basic-skidl-objects-parts-pins-nets-buses">Basic SKiDL Objects: Parts, Pins, Nets, Buses</a></li>
<li><a href="#creating-skidl-objects">Creating SKiDL Objects</a></li>
<li><a href="#finding-skidl-objects">Finding SKiDL Objects</a></li>
<li><a href="#copying-skidl-objects">Copying SKiDL Objects</a></li>
<li><a href="#accessing-part-pins-and-bus-lines">Accessing Part Pins and Bus Lines</a><ul>
<li><a href="#accessing-part-pins">Accessing Part Pins</a></li>
<li><a href="#accessing-bus-lines">Accessing Bus Lines</a></li>
</ul>
</li>
<li><a href="#making-connections">Making Connections</a></li>
<li><a href="#making-serial-parallel-and-tee-networks">Making Serial, Parallel, and Tee Networks</a></li>
<li><a href="#aliases">Aliases</a></li>
<li><a href="#units-within-parts">Units Within Parts</a></li>
<li><a href="#part-fields">Part Fields</a></li>
<li><a href="#hierarchy">Hierarchy</a><ul>
<li><a href="#subcircuits">Subcircuits</a></li>
<li><a href="#packages">Packages</a></li>
<li><a href="#groups">Groups</a></li>
</ul>
</li>
<li><a href="#interfaces">Interfaces</a></li>
<li><a href="#libraries">Libraries</a></li>
<li><a href="#doodads">Doodads</a><ul>
<li><a href="#no-connects">No Connects</a></li>
<li><a href="#net-and-pin-drive-levels">Net and Pin Drive Levels</a></li>
<li><a href="#pin-net-bus-equivalencies">Pin, Net, Bus Equivalencies</a></li>
<li><a href="#selectively-supressing-erc-messages">Selectively Supressing ERC Messages</a></li>
<li><a href="#customizable-erc-using-erc_assert">Customizable ERC Using <code>erc_assert()</code></a></li>
<li><a href="#handling-empty-footprints">Handling Empty Footprints</a></li>
<li><a href="#tags">Tags</a></li>
</ul>
</li>
<li><a href="#going-really-deep">Going Really Deep</a></li>
<li><a href="#circuit-objects">Circuit Objects</a></li>
<li><a href="#generating-a-schematic">Generating a Schematic</a></li>
<li><a href="#svg-schematics">SVG Schematics</a></li>
<li><a href="#kicad-schematics">KiCad Schematics</a></li>
<li><a href="#dot-graphs">DOT Graphs</a></li>
<li><a href="#converting-existing-designs-to-skidl">Converting Existing Designs to SKiDL</a></li>
<li><a href="#spice-simulations">SPICE Simulations</a></li>
</ul>
<h1 id="introduction">Introduction</h1>
<p>SKiDL is a module that allows you to compactly describe the interconnection of
electronic circuits and components using Python.
The resulting Python program performs electrical rules checking
for common mistakes and outputs a netlist that serves as input to
a PCB layout tool.</p>
<p>First, let's look at a "normal" design flow in <a href="https://kicad-pcb.org">KiCad</a>:</p>
<p><img alt="Schematic-based PCB design flow" src="images/schematic-process-flow.png"></p>
<p>Here, you start off in a <em>schematic editor</em> (for KiCad, that's Eeschema) and
draw a schematic. From that, Eeschema generates
a <em>netlist file</em> that lists what components are used and how their pins are interconnected.
Then you'll use a <em>PCB layout tool</em> (like KiCad's PCBNEW) to arrange the part footprints
and draw the wire traces that connect the pins as specified in the netlist.
Once that is done, PCBNEW outputs a set of <em>Gerber files</em> that are sent to a
<em>PCB fabricator</em> who will create a physical PCB and ship it to you.
Then you'll post a picture of them on Twitter and promptly dump them
in a drawer for a few years because you got bored with the project.</p>
<p>In the SKiDL-based design flow, you use a <em>text editor</em> to create a <em>Python code file</em>
that employs the SKiDL library to describe interconnections of components.
This code file is executed by a <em>Python interpreter</em> and a netlist file is output.
From there, the design flow is identical to the schematic-based one
(including dumping the PCBs in a drawer).</p>
<p><img alt="Schematic-based PCB design flow" src="images/skidl-process-flow.png"></p>
<p>So, why would you <em>want</em> to use SKiDL?
Here are some of the features SKiDL brings to electronic design:</p>
<ul>
<li>Requires only a text editor and Python.</li>
<li>Has a powerful, flexible syntax (because it <em>is</em> Python).</li>
<li>Permits compact descriptions of electronic circuits (think about <em>not</em> tracing
signals through a multi-page schematic).</li>
<li>Allows textual descriptions of electronic circuits (think about using
<code>diff</code> and <a href="https://en.wikipedia.org/wiki/Git">git</a> for circuits).</li>
<li>Performs electrical rules checking (ERC) for common mistakes (e.g., unconnected device I/O pins).</li>
<li>Supports linear / hierarchical / mixed descriptions of electronic designs.</li>
<li>Fosters design reuse (think about using <a href="pypi.org">PyPi</a> and <a href="github.com">Github</a>
to distribute electronic designs).</li>
<li>Makes possible the creation of <em>smart circuit modules</em> whose behavior / structure are changed parametrically
(think about filters whose component values are automatically adjusted based on your
desired cutoff frequency).</li>
<li>Can work with any ECAD tool (for basic use, only two methods are needed: one for reading the part libraries and another
for outputing the correct netlist format).</li>
<li>Takes advantage of all the benefits of the Python ecosystem (because it <em>is</em> Python).</li>
<li>Free software: MIT license.</li>
<li>Open source: <a href="https://github.com/devbisme/skidl">https://github.com/devbisme/skidl</a></li>
</ul>
<p>As a very simple example, the SKiDL program below describes a circuit that
takes an input voltage, divides it by three, and outputs it:</p>
<div class="highlight"><pre><span></span><code><span class="kn">from</span> <span class="nn">skidl</span> <span class="kn">import</span> <span class="o">*</span>
<span class="c1"># Create input & output voltages and ground reference.</span>
<span class="n">vin</span><span class="p">,</span> <span class="n">vout</span><span class="p">,</span> <span class="n">gnd</span> <span class="o">=</span> <span class="n">Net</span><span class="p">(</span><span class="s1">'VI'</span><span class="p">),</span> <span class="n">Net</span><span class="p">(</span><span class="s1">'VO'</span><span class="p">),</span> <span class="n">Net</span><span class="p">(</span><span class="s1">'GND'</span><span class="p">)</span>
<span class="c1"># Create two resistors.</span>
<span class="n">r1</span><span class="p">,</span> <span class="n">r2</span> <span class="o">=</span> <span class="mi">2</span> <span class="o">*</span> <span class="n">Part</span><span class="p">(</span><span class="s2">"Device"</span><span class="p">,</span> <span class="s1">'R'</span><span class="p">,</span> <span class="n">TEMPLATE</span><span class="p">,</span> <span class="n">footprint</span><span class="o">=</span><span class="s1">'Resistor_SMD.pretty:R_0805_2012Metric'</span><span class="p">)</span>
<span class="n">r1</span><span class="o">.</span><span class="n">value</span> <span class="o">=</span> <span class="s1">'1K'</span> <span class="c1"># Set upper resistor value.</span>
<span class="n">r2</span><span class="o">.</span><span class="n">value</span> <span class="o">=</span> <span class="s1">'500'</span> <span class="c1"># Set lower resistor value.</span>
<span class="c1"># Connect the nets and resistors.</span>
<span class="n">vin</span> <span class="o">+=</span> <span class="n">r1</span><span class="p">[</span><span class="mi">1</span><span class="p">]</span> <span class="c1"># Connect the input to the upper resistor.</span>
<span class="n">gnd</span> <span class="o">+=</span> <span class="n">r2</span><span class="p">[</span><span class="mi">2</span><span class="p">]</span> <span class="c1"># Connect the lower resistor to ground.</span>
<span class="n">vout</span> <span class="o">+=</span> <span class="n">r1</span><span class="p">[</span><span class="mi">2</span><span class="p">],</span> <span class="n">r2</span><span class="p">[</span><span class="mi">1</span><span class="p">]</span> <span class="c1"># Output comes from the connection of the two resistors.</span>
<span class="c1"># Or you could do it with a single line of code:</span>
<span class="c1"># vin && r1 && vout && r2 && gnd</span>
<span class="c1"># Output the netlist to a file.</span>
<span class="n">generate_netlist</span><span class="p">(</span><span class="n">tool</span><span class="o">=</span><span class="n">KICAD8</span><span class="p">)</span>
</code></pre></div>
<p>And this is the netlist output that is passed to <code>PCBNEW</code> to
do the PCB layout:</p>
<div class="highlight"><pre><span></span><code>(export (version D)
(design
(source "/media/devb/Main/devbisme/KiCad/tools/skidl/skidl/circuit.py")
(date "04/21/2021 10:43 AM")
(tool "SKiDL (0.0.31)"))
(components
(comp (ref R1)
(value 1K)
(footprint Resistor_SMD.pretty:R_0805_2012Metric)
(fields
(field (name F0) R)
(field (name F1) R))
(libsource (lib Device) (part R))
(sheetpath (names /top/15380172755090775681) (tstamps /top/15380172755090775681)))
(comp (ref R2)
(value 500)
(footprint Resistor_SMD.pretty:R_0805_2012Metric)
(fields
(field (name F0) R)
(field (name F1) R))
(libsource (lib Device) (part R))
(sheetpath (names /top/3019747424092552385) (tstamps /top/3019747424092552385))))
(nets
(net (code 1) (name GND)
(node (ref R2) (pin 2)))
(net (code 2) (name VI)
(node (ref R1) (pin 1)))
(net (code 3) (name VO)
(node (ref R1) (pin 2))
(node (ref R2) (pin 1))))
)
</code></pre></div>
<h1 id="installation">Installation</h1>
<p>SKiDL is pure Python so it's easy to install:</p>
<div class="highlight"><pre><span></span><code>$<span class="w"> </span>pip<span class="w"> </span>install<span class="w"> </span>skidl
</code></pre></div>
<p>To give SKiDL some part libraries to work with,
you'll also need to install <a href="http://kicad.org/">KiCad</a>.
Then, you'll need to set an environment variable so SKiDL can find the libraries.
For Windows, do this:</p>
<div class="highlight"><pre><span></span><code>set KICAD_SYMBOL_DIR=C:\Program Files\KiCad\share\kicad\kicad-symbols
</code></pre></div>
<p>And for linux-type OSes, define the environment variable in your <code>.bashrc</code> like so:</p>
<div class="highlight"><pre><span></span><code><span class="nb">export</span><span class="w"> </span><span class="nv">KICAD_SYMBOL_DIR</span><span class="o">=</span><span class="s2">"/usr/share/kicad/library"</span>
</code></pre></div>
<p><strong>These paths are OS-dependent</strong>, so launch KiCAD and click <code>Preferences->Configure Paths</code>
to reveal the needed paths.</p>
<h1 id="basic-usage">Basic Usage</h1>
<p>This is the minimum that you need to know to design electronic circuitry
using SKiDL:</p>
<ul>
<li>How to get access to SKiDL.</li>
<li>How to find and instantiate a component (or <em>part</em>).</li>
<li>How to connect <em>pins</em> of the parts to each other using <em>nets</em>.</li>
<li>How to run an ERC on the circuit.</li>
<li>How to generate a <em>netlist</em> for the circuit that serves as input to a PCB layout tool.</li>
</ul>
<p>I'll demonstrate these steps using SKiDL in an interactive Python session,
but normally the statements that are shown would be entered into a file and
executed as a Python script.</p>
<h2 id="accessing-skidl">Accessing SKiDL</h2>
<p>To use skidl in a project, just place the following at the top of your file:</p>
<div class="highlight"><pre><span></span><code><span class="kn">import</span> <span class="nn">skidl</span>
</code></pre></div>
<p>But for this tutorial, I'll just import everything:</p>
<div class="highlight"><pre><span></span><code><span class="kn">from</span> <span class="nn">skidl</span> <span class="kn">import</span> <span class="o">*</span>
</code></pre></div>
<h2 id="finding-parts">Finding Parts</h2>
<h3 id="command-line-searching">Command-line Searching</h3>
<p>SKiDL provides a convenience function for searching for parts called
(naturally) <code>search</code>.
For example, if you need an operational amplifier, then the following command would
pull up a long list of likely candidates:</p>
<div class="highlight"><pre><span></span><code><span class="o">>></span><span class="p">></span><span class="w"> </span><span class="nx">search</span><span class="p">(</span><span class="err">'</span><span class="nx">opamp</span><span class="err">'</span><span class="p">)</span>
<span class="nx">Amplifier_Audio</span><span class="p">.</span><span class="nx">lib</span><span class="p">:</span><span class="w"> </span><span class="nx">OPA1622</span><span class="w"> </span><span class="p">(</span><span class="nx">High</span><span class="o">-</span><span class="nx">Fidelity</span><span class="p">,</span><span class="w"> </span><span class="nx">Bipolar</span><span class="o">-</span><span class="nx">Input</span><span class="p">,</span><span class="w"> </span><span class="nx">Audio</span><span class="w"> </span><span class="nx">Operational</span><span class="w"> </span><span class="nx">Amplifier</span><span class="p">,</span><span class="w"> </span><span class="nx">VSON</span><span class="o">-</span><span class="mi">10</span><span class="p">)</span>
<span class="nx">Amplifier_Audio</span><span class="p">.</span><span class="nx">lib</span><span class="p">:</span><span class="w"> </span><span class="nx">LM386</span><span class="w"> </span><span class="p">(</span><span class="nx">Low</span><span class="w"> </span><span class="nx">Voltage</span><span class="w"> </span><span class="nx">Audio</span><span class="w"> </span><span class="nx">Power</span><span class="w"> </span><span class="nx">Amplifier</span><span class="p">,</span><span class="w"> </span><span class="nx">DIP</span><span class="o">-</span><span class="mi">8</span><span class="o">/</span><span class="nx">SOIC</span><span class="o">-</span><span class="mi">8</span><span class="o">/</span><span class="nx">SSOP</span><span class="o">-</span><span class="mi">8</span><span class="p">)</span>
<span class="nx">Amplifier_Difference</span><span class="p">.</span><span class="nx">lib</span><span class="p">:</span><span class="w"> </span><span class="nx">LM733CH</span><span class="w"> </span><span class="p">(</span><span class="nx">Single</span><span class="w"> </span><span class="nx">Differential</span><span class="w"> </span><span class="nx">Amplifier</span><span class="p">,</span><span class="w"> </span><span class="nx">TO</span><span class="o">-</span><span class="mi">5</span><span class="o">-</span><span class="mi">10</span><span class="p">)</span>
<span class="nx">Amplifier_Difference</span><span class="p">.</span><span class="nx">lib</span><span class="p">:</span><span class="w"> </span><span class="nx">LM733H</span><span class="w"> </span><span class="p">(</span><span class="nx">Single</span><span class="w"> </span><span class="nx">Differential</span><span class="w"> </span><span class="nx">Amplifier</span><span class="p">,</span><span class="w"> </span><span class="nx">TO</span><span class="o">-</span><span class="mi">5</span><span class="o">-</span><span class="mi">10</span><span class="p">)</span>
<span class="nx">Amplifier_Difference</span><span class="p">.</span><span class="nx">lib</span><span class="p">:</span><span class="w"> </span><span class="nx">LM733CN</span><span class="w"> </span><span class="p">(</span><span class="nx">Single</span><span class="w"> </span><span class="nx">Differential</span><span class="w"> </span><span class="nx">Amplifier</span><span class="p">,</span><span class="w"> </span><span class="nx">DIP</span><span class="o">-</span><span class="mi">14</span><span class="p">)</span>
<span class="nx">Amplifier_Instrumentation</span><span class="p">.</span><span class="nx">lib</span><span class="p">:</span><span class="w"> </span><span class="nx">INA326</span><span class="w"> </span><span class="p">(</span><span class="nx">Precision</span><span class="p">,</span><span class="w"> </span><span class="nx">Rail</span><span class="o">-</span><span class="nx">to</span><span class="o">-</span><span class="nx">Rail</span><span class="w"> </span><span class="nx">I</span><span class="o">/</span><span class="nx">O</span><span class="w"> </span><span class="nx">Instrumentation</span><span class="w"> </span><span class="nx">Amplifier</span><span class="p">,</span><span class="w"> </span><span class="nx">MSOP</span><span class="o">-</span><span class="mi">8</span><span class="w"> </span><span class="kn">package</span><span class="p">)</span>
<span class="nx">Amplifier_Instrumentation</span><span class="p">.</span><span class="nx">lib</span><span class="p">:</span><span class="w"> </span><span class="nx">INA327</span><span class="w"> </span><span class="p">(</span><span class="nx">Precision</span><span class="p">,</span><span class="w"> </span><span class="nx">Rail</span><span class="o">-</span><span class="nx">to</span><span class="o">-</span><span class="nx">Rail</span><span class="w"> </span><span class="nx">I</span><span class="o">/</span><span class="nx">O</span><span class="w"> </span><span class="nx">Instrumentation</span><span class="w"> </span><span class="nx">Amplifier</span><span class="p">,</span><span class="w"> </span><span class="nx">MSOP</span><span class="o">-</span><span class="mi">10</span><span class="w"> </span><span class="kn">package</span><span class="p">)</span>
<span class="nx">Amplifier_Instrumentation</span><span class="p">.</span><span class="nx">lib</span><span class="p">:</span><span class="w"> </span><span class="nx">INA129</span><span class="w"> </span><span class="p">(</span><span class="nx">Precision</span><span class="p">,</span><span class="w"> </span><span class="nx">Low</span><span class="w"> </span><span class="nx">Power</span><span class="w"> </span><span class="nx">Instrumentation</span><span class="w"> </span><span class="nx">Amplifier</span><span class="w"> </span><span class="nx">G</span><span class="w"> </span><span class="p">=</span><span class="w"> </span><span class="mi">1</span><span class="w"> </span><span class="o">+</span><span class="w"> </span><span class="m m-Double">49.4</span><span class="nx">kOhm</span><span class="o">/</span><span class="nx">Rg</span><span class="p">,</span><span class="w"> </span><span class="nx">DIP</span><span class="o">-</span><span class="mi">8</span><span class="o">/</span><span class="nx">SOIC</span><span class="o">-</span><span class="mi">8</span><span class="p">)</span>
<span class="nx">Amplifier_Instrumentation</span><span class="p">.</span><span class="nx">lib</span><span class="p">:</span><span class="w"> </span><span class="nx">INA128</span><span class="w"> </span><span class="p">(</span><span class="nx">Precision</span><span class="p">,</span><span class="w"> </span><span class="nx">Low</span><span class="w"> </span><span class="nx">Power</span><span class="w"> </span><span class="nx">Instrumentation</span><span class="w"> </span><span class="nx">Amplifier</span><span class="w"> </span><span class="nx">G</span><span class="w"> </span><span class="p">=</span><span class="w"> </span><span class="mi">1</span><span class="w"> </span><span class="o">+</span><span class="w"> </span><span class="m m-Double">49.4</span><span class="nx">kOhm</span><span class="o">/</span><span class="nx">Rg</span><span class="p">,</span><span class="w"> </span><span class="nx">DIP</span><span class="o">-</span><span class="mi">8</span><span class="o">/</span><span class="nx">SOIC</span><span class="o">-</span><span class="mi">8</span><span class="p">)</span>
<span class="nx">Amplifier_Operational</span><span class="p">.</span><span class="nx">lib</span><span class="p">:</span><span class="w"> </span><span class="nx">OPA842xD</span><span class="w"> </span><span class="p">(</span><span class="nx">Single</span><span class="w"> </span><span class="nx">rail</span><span class="o">-</span><span class="nx">to</span><span class="o">-</span><span class="nx">rail</span><span class="w"> </span><span class="nx">input</span><span class="o">/</span><span class="nx">output</span><span class="w"> </span><span class="mi">8</span><span class="w"> </span><span class="nx">MHz</span><span class="w"> </span><span class="nx">operational</span><span class="w"> </span><span class="nx">amplifiers</span><span class="p">,</span><span class="w"> </span><span class="nx">SOIC</span><span class="o">-</span><span class="mi">8</span><span class="p">)</span>
<span class="nx">Amplifier_Operational</span><span class="p">.</span><span class="nx">lib</span><span class="p">:</span><span class="w"> </span><span class="nx">OPA188xxD</span><span class="w"> </span><span class="p">(</span><span class="nx">Single</span><span class="w"> </span><span class="nx">rail</span><span class="o">-</span><span class="nx">to</span><span class="o">-</span><span class="nx">rail</span><span class="w"> </span><span class="nx">input</span><span class="o">/</span><span class="nx">output</span><span class="w"> </span><span class="mi">8</span><span class="w"> </span><span class="nx">MHz</span><span class="w"> </span><span class="nx">operational</span><span class="w"> </span><span class="nx">amplifiers</span><span class="p">,</span><span class="w"> </span><span class="nx">SOIC</span><span class="o">-</span><span class="mi">8</span><span class="p">)</span>
<span class="nx">Amplifier_Operational</span><span class="p">.</span><span class="nx">lib</span><span class="p">:</span><span class="w"> </span><span class="nx">OPA855xDSG</span><span class="w"> </span><span class="p">(</span><span class="m m-Double">1.8</span><span class="w"> </span><span class="nx">GHz</span><span class="w"> </span><span class="nx">Unity</span><span class="o">-</span><span class="nx">Gain</span><span class="w"> </span><span class="nx">Bandwidth</span><span class="w"> </span><span class="nx">FET</span><span class="w"> </span><span class="nx">Input</span><span class="w"> </span><span class="nx">Amplifier</span><span class="p">,</span><span class="w"> </span><span class="nx">WSON</span><span class="o">-</span><span class="mi">8</span><span class="p">)</span>
<span class="nx">Amplifier_Operational</span><span class="p">.</span><span class="nx">lib</span><span class="p">:</span><span class="w"> </span><span class="nx">SA5534</span><span class="w"> </span><span class="p">(</span><span class="nx">Single</span><span class="w"> </span><span class="nx">Low</span><span class="o">-</span><span class="nx">Noise</span><span class="w"> </span><span class="nx">Operational</span><span class="w"> </span><span class="nx">Amplifiers</span><span class="p">,</span><span class="w"> </span><span class="nx">DIP</span><span class="o">-</span><span class="mi">8</span><span class="o">/</span><span class="nx">SOIC</span><span class="o">-</span><span class="mi">8</span><span class="p">)</span>
<span class="o">...</span>
</code></pre></div>
<p><code>search</code> accepts keywords and scans for them <em>anywhere</em> within the
name, description and keywords of all the parts in the library path.
(You can read more about how SKiDL handles libraries <a href="#libraries">here</a>.)
If you want search for an <em>exact</em> match, then use a regular expression like the following:</p>
<div class="highlight"><pre><span></span><code>>>> search('^lm386$')
Amplifier_Audio.lib: LM386 (Low Voltage Audio Power Amplifier, DIP-8/SOIC-8/SSOP-8)
</code></pre></div>
<p>If you give <code>search</code> multiple terms, then it will find parts that contain <em>all</em>
those terms:</p>
<div class="highlight"><pre><span></span><code>>>> search('opamp low-noise dip-8')
Amplifier_Operational.lib: AD797 (Single Low-Noise Operational Amplifiers, DIP-8/SOIC-8)
Amplifier_Operational.lib: LM101 (Single Low-Noise Operational Amplifiers, DIP-8/SOIC-8)
Amplifier_Operational.lib: LM301 (Single Low-Noise Operational Amplifiers, DIP-8/SOIC-8)
Amplifier_Operational.lib: LT1012 (Single Low-Noise Operational Amplifiers, DIP-8/SOIC-8)
Amplifier_Operational.lib: SA5534 (Single Low-Noise Operational Amplifiers, DIP-8/SOIC-8)
Amplifier_Operational.lib: NE5534 (Single Low-Noise Operational Amplifiers, DIP-8/SOIC-8)
Amplifier_Operational.lib: LM201 (Single Low-Noise Operational Amplifiers, DIP-8/SOIC-8)
</code></pre></div>
<p>You may also use the <code>|</code> character to find parts that contain at least one of a set
of choices:</p>
<div class="highlight"><pre><span></span><code>>>> search('opamp (low-noise|dip-8)')
Amplifier_Audio.lib: LM386 (Low Voltage Audio Power Amplifier, DIP-8/SOIC-8/SSOP-8)
Amplifier_Operational.lib: TLV2371P (Rail-to-Rail Input/Output Operational Amplifier, PDIP-8)
Amplifier_Operational.lib: MAX4239ASA (Ultra-Low Offset/Drift, Low-Noise, Precision Amplifiers, SOIC-8)
Amplifier_Operational.lib: LM4250 (Programmable Operational Amplifier, DIP-8/SOIC-8)
Amplifier_Operational.lib: LF256 (Single JFET-Input Operational Amplifiers, DIP-8/SOIC-8)
Amplifier_Operational.lib: MAX4239AUT (Ultra-Low Offset/Drift, Low-Noise, Precision Amplifiers, SOT-23-6)
Amplifier_Operational.lib: LM6361 (Single High Speed Operational Amplifier, DIP-8/SOIC-8)
Amplifier_Operational.lib: LF257 (Single JFET-Input Operational Amplifiers, DIP-8/SOIC-8)
Amplifier_Operational.lib: AD8603 (Zero-Drift, Precision, Low-Noise, Rail-to-Rail Output, 36-V Operational Amplifier, TSOT-23-5)
...
</code></pre></div>
<p>If you need to search for a string containing spaces, just enclose it in quotes:</p>
<div class="highlight"><pre><span></span><code>>>> search('opamp "high performance"')
Amplifier_Operational.lib: OP77 (Single SoundPlus High Performance Audio Operational Amplifiers, DIP-8/SOIC-8)
Amplifier_Operational.lib: LT1363 (Single SoundPlus High Performance Audio Operational Amplifiers, DIP-8/SOIC-8)
Amplifier_Operational.lib: OP07 (Single SoundPlus High Performance Audio Operational Amplifiers, DIP-8/SOIC-8)
Amplifier_Operational.lib: OPA134 (Single SoundPlus High Performance Audio Operational Amplifiers, DIP-8/SOIC-8)
</code></pre></div>
<p>Once you have the part name and library, you can see the part's pin numbers, names
and their functions using the <code>show</code> function:</p>
<div class="highlight"><pre><span></span><code>>>> show('Amplifier_Audio', 'lm386')
LM386 (): Low Voltage Audio Power Amplifier, DIP-8/SOIC-8/SSOP-8
Pin None/1/GAIN/INPUT
Pin None/2/-/INPUT
Pin None/3/+/INPUT
Pin None/4/GND/POWER-IN
Pin None/5/~/OUTPUT
Pin None/6/V+/POWER-IN
Pin None/7/BYPASS/INPUT
Pin None/8/GAIN/INPUT
</code></pre></div>
<p><code>show</code> looks for <em>exact matches</em> of the part name in a library, so the following
command raises an error:</p>
<div class="highlight"><pre><span></span><code><span class="o">>></span><span class="p">></span><span class="w"> </span><span class="nx">show</span><span class="p">(</span><span class="err">'</span><span class="nx">Amplifier_Audio</span><span class="err">'</span><span class="p">,</span><span class="w"> </span><span class="err">'</span><span class="nx">lm38</span><span class="err">'</span><span class="p">)</span>
<span class="nx">ERROR</span><span class="p">:</span><span class="w"> </span><span class="nx">Unable</span><span class="w"> </span><span class="nx">to</span><span class="w"> </span><span class="nx">find</span><span class="w"> </span><span class="nx">part</span><span class="w"> </span><span class="nx">lm38</span><span class="w"> </span><span class="k">in</span><span class="w"> </span><span class="kn">library</span><span class="w"> </span><span class="nx">linear</span><span class="p">.</span>
</code></pre></div>
<p>In addition to searching for parts, you may also search for footprints using the
<code>search_footprints</code> command. It works similarly to the <code>search</code> command:</p>
<div class="highlight"><pre><span></span><code>>>> search_footprints('QFN-48')
Package_DFN_QFN: QFN-48-1EP_5x5mm_P0.35mm_EP3.7x3.7mm ("QFN, 48 Pin (https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf#page=38), generated with kicad-footprint-generator ipc_noLead_generator.py" - "QFN NoLead")
Package_DFN_QFN: QFN-48-1EP_5x5mm_P0.35mm_EP3.7x3.7mm_ThermalVias ("QFN, 48 Pin (https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf#page=38), generated with kicad-footprint-generator ipc_noLead_generator.py" - "QFN NoLead")
Package_DFN_QFN: QFN-48-1EP_6x6mm_P0.4mm_EP4.2x4.2mm ("QFN, 48 Pin (https://static.dev.sifive.com/SiFive-FE310-G000-datasheet-v1p5.pdf#page=20), generated with kicad-footprint-generator ipc_noLead_generator.py" - "QFN NoLead")
Package_DFN_QFN: QFN-48-1EP_6x6mm_P0.4mm_EP4.2x4.2mm_ThermalVias ("QFN, 48 Pin (https://static.dev.sifive.com/SiFive-FE310-G000-datasheet-v1p5.pdf#page=20), generated with kicad-footprint-generator ipc_noLead_generator.py" - "QFN NoLead")
...
</code></pre></div>
<h3 id="zyc-a-gui-search-tool">Zyc: A GUI Search Tool</h3>
<p>If you want to avoid using command-line tools,
<a href="https://devbisme.github.io/zyc"><code>zyc</code></a> lets you search for parts and footprints using a GUI.
You can read more about it <a href="https://devbisme.github.io/skidl/docs/_site/blog/worst-part-of-skidl">here</a>.</p>
<h2 id="instantiating-parts">Instantiating Parts</h2>
<p>You instantiate a part using its name and the library that contains it:</p>
<div class="highlight"><pre><span></span><code>>>> resistor = Part('Device','R')
</code></pre></div>
<p>You may customize the resistor by setting its <code>value</code> attribute:</p>
<div class="highlight"><pre><span></span><code>>>> resistor.value = '1K'
>>> resistor.value
'1K'
</code></pre></div>
<p>It's also possible to set attributes when creating a part:</p>
<div class="highlight"><pre><span></span><code>>>> resistor = Part('Device', 'R', value='2K')
>>> resistor.value
'2K'
</code></pre></div>
<p>The <code>ref</code> attribute holds the part <em>reference</em>. It's set automatically
when you create the part:</p>
<div class="highlight"><pre><span></span><code>>>> resistor.ref
'R1'
</code></pre></div>
<p>Since this was the first resistor we created, it has the honor of being named <code>R1</code>.
But you can easily change that:</p>
<div class="highlight"><pre><span></span><code>>>> resistor.ref = 'R5'
>>> resistor.ref
'R5'
</code></pre></div>
<p>Now what happens if we create another resistor?:</p>
<div class="highlight"><pre><span></span><code>>>> another_res = Part('Device','R')
>>> another_res.ref
'R1'
</code></pre></div>
<p>Since the <code>R1</code> reference wasn't being used, the new resistor got it.
What if we tried renaming the first resistor back to <code>R1</code>:</p>
<div class="highlight"><pre><span></span><code>>>> resistor.ref = 'R1'
>>> resistor.ref
'R1_1'
</code></pre></div>
<p>Since the <code>R1</code> reference was already taken, SKiDL tried to give us
something close to what we wanted.
SKiDL won't let different parts have the same reference because
that would be confusing.</p>
<p>The <code>ref</code>, <code>value</code>, and <code>footprint</code> attributes are necessary when generating
a final netlist for your circuit.
Since a part is stored in a Python object, you may add any
other attributes you want using <code>setattr()</code>.
But if you want those attributes to be passed on within the netlist, then you
should probably add them as <a href="#part-fields">part fields</a>.</p>
<h2 id="connecting-pins">Connecting Pins</h2>
<p>Parts are great, but not very useful if they aren't connected to anything.
The connections between parts are called <em>nets</em> (think of them as wires)
and every net has one or more part <em>pins</em> attached to it.
SKiDL makes it easy to create nets and connect pins to them.
To demonstrate, let's build the voltage divider circuit
shown in the introduction.</p>
<p>First, start by creating two resistors (note that I've also added the
<code>footprint</code> attribute that describes the physical package for the resistors):</p>
<div class="highlight"><pre><span></span><code><span class="o">>>></span> <span class="n">rup</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="s2">"Device"</span><span class="p">,</span> <span class="s1">'R'</span><span class="p">,</span> <span class="n">value</span><span class="o">=</span><span class="s1">'1K'</span><span class="p">,</span> <span class="n">footprint</span><span class="o">=</span><span class="s1">'Resistor_SMD.pretty:R_0805_2012Metric'</span><span class="p">)</span>
<span class="o">>>></span> <span class="n">rlow</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="s2">"Device"</span><span class="p">,</span> <span class="s1">'R'</span><span class="p">,</span> <span class="n">value</span><span class="o">=</span><span class="s1">'500'</span><span class="p">,</span> <span class="n">footprint</span><span class="o">=</span><span class="s1">'Resistor_SMD.pretty:R_0805_2012Metric'</span><span class="p">)</span>
<span class="o">>>></span> <span class="n">rup</span><span class="o">.</span><span class="n">ref</span><span class="p">,</span> <span class="n">rlow</span><span class="o">.</span><span class="n">ref</span>
<span class="p">(</span><span class="s1">'R1'</span><span class="p">,</span> <span class="s1">'R2'</span><span class="p">)</span>
<span class="o">>>></span> <span class="n">rup</span><span class="o">.</span><span class="n">value</span><span class="p">,</span> <span class="n">rlow</span><span class="o">.</span><span class="n">value</span>
<span class="p">(</span><span class="s1">'1K'</span><span class="p">,</span> <span class="s1">'500'</span><span class="p">)</span>
</code></pre></div>
<p>To bring the voltage that will be divided into the circuit, let's create a net:</p>
<div class="highlight"><pre><span></span><code>>>> v_in = Net('VIN')
>>> v_in.name
'VIN'
</code></pre></div>
<p>Now attach the net to one of the pins of the <code>rup</code> resistor
(resistors are bidirectional which means it doesn't matter which pin, so pick pin 1):</p>
<div class="highlight"><pre><span></span><code>>>> rup[1] += v_in
</code></pre></div>
<p>You can verify that the net is attached to pin 1 of the resistor like this:</p>
<div class="highlight"><pre><span></span><code>>>> rup[1].net
VIN: Pin R1/1/~/PASSIVE
</code></pre></div>
<p>Next, create a ground reference net and attach it to <code>rlow</code>:</p>
<div class="highlight"><pre><span></span><code>>>> gnd = Net('GND')
>>> rlow[1] += gnd
>>> rlow[1].net
GND: Pin R2/1/~/PASSIVE
</code></pre></div>
<p>Finally, the divided voltage has to come out of the circuit on a net.
This can be done in several ways.
The first way is to define the output net and then attach the unconnected
pins of both resistors to it:</p>
<div class="highlight"><pre><span></span><code>>>> v_out = Net('VO')
>>> v_out += rup[2], rlow[2]
>>> rup[2].net, rlow[2].net
(VO: Pin R1/2/~/PASSIVE, Pin R2/2/~/PASSIVE, VO: Pin R1/2/~/PASSIVE, Pin R2/2/~/PASSIVE)
</code></pre></div>
<p>An alternate method is to connect the resistors and then attach their
junction to the output net:</p>
<div class="highlight"><pre><span></span><code>>>> rup[2] += rlow[2]
>>> v_out = Net('VO')
>>> v_out += rlow[2]
>>> rup[2].net, rlow[2].net
(VO: Pin R1/2/~/PASSIVE, Pin R2/2/~/PASSIVE, VO: Pin R1/2/~/PASSIVE, Pin R2/2/~/PASSIVE)
</code></pre></div>
<p>Either way works! Sometimes pin-to-pin connections are easier when you're
just wiring two devices together, while the pin-to-net connection method
excels when three or more pins have a common connection.</p>
<p>With more complicated parts, the code is often clearer if you use pin names instead
of numbers. Check out <a href="#accessing-part-pins">this section</a> for how to do that.</p>
<h2 id="checking-for-errors">Checking for Errors</h2>
<p>Once the parts are wired together, you may do simple electrical rules checking
like this:</p>
<div class="highlight"><pre><span></span><code>>>> ERC()
2 warnings found during ERC.
0 errors found during ERC.
</code></pre></div>
<p>Since this is an interactive session, the ERC warnings and errors are stored
in the file <code>skidl.erc</code>. (Normally, your SKiDL circuit description is stored
as a Python script such as <code>my_circuit.py</code> and the <code>ERC()</code> function will
dump its messages to <code>my_circuit.erc</code>.)
The ERC messages are:</p>
<div class="highlight"><pre><span></span><code><span class="n">WARNING</span><span class="o">:</span><span class="w"> </span><span class="n">Only</span><span class="w"> </span><span class="n">one</span><span class="w"> </span><span class="n">pin</span><span class="w"> </span><span class="o">(</span><span class="n">PASSIVE</span><span class="w"> </span><span class="n">pin</span><span class="w"> </span><span class="mi">1</span><span class="sr">/~ of R/</span><span class="n">R1</span><span class="o">)</span><span class="w"> </span><span class="n">attached</span><span class="w"> </span><span class="n">to</span><span class="w"> </span><span class="n">net</span><span class="w"> </span><span class="n">VIN</span><span class="o">.</span>
<span class="n">WARNING</span><span class="o">:</span><span class="w"> </span><span class="n">Only</span><span class="w"> </span><span class="n">one</span><span class="w"> </span><span class="n">pin</span><span class="w"> </span><span class="o">(</span><span class="n">PASSIVE</span><span class="w"> </span><span class="n">pin</span><span class="w"> </span><span class="mi">1</span><span class="sr">/~ of R/</span><span class="n">R2</span><span class="o">)</span><span class="w"> </span><span class="n">attached</span><span class="w"> </span><span class="n">to</span><span class="w"> </span><span class="n">net</span><span class="w"> </span><span class="n">GND</span><span class="o">.</span>
</code></pre></div>
<p>These messages are generated because the <code>VIN</code> and <code>GND</code> nets each have only
a single pin on them and this usually indicates a problem.
But it's OK for this simple example, so the ERC can be turned off for
these two nets to prevent the spurious messages:</p>
<div class="highlight"><pre><span></span><code>>>> v_in.do_erc = False
>>> gnd.do_erc = False
>>> ERC()
No ERC errors or warnings found.
</code></pre></div>
<h2 id="generating-a-netlist-or-pcb">Generating a Netlist or PCB</h2>
<p>The end goal of using SKiDL is to generate a netlist that can be used
with a layout tool to generate a PCB. The netlist is output as follows:</p>
<div class="highlight"><pre><span></span><code>>>> generate_netlist()
</code></pre></div>
<p>Like the ERC output, the netlist shown below is stored in the file <code>skidl.net</code>.
But if your SKiDL circuit description is in the <code>my_circuit.py</code> file,
then the netlist will be stored in <code>my_circuit.net</code>.</p>
<div class="highlight"><pre><span></span><code>(export (version D)
(design
(source "/media/devb/Main/devbisme/KiCad/tools/skidl/skidl/circuit.py")
(date "04/22/2021 01:50 PM")
(tool "SKiDL (0.0.31dev)"))
(components
(comp (ref R1)
(value 1K)
(footprint Resistor_SMD.pretty:R_0805_2012Metric)
(fields
(field (name F0) R)
(field (name F1) R))
(libsource (lib Device) (part R))
(sheetpath (names /top/16316864629425674383) (tstamps /top/16316864629425674383)))
(comp (ref R2)
(value 500)
(footprint Resistor_SMD.pretty:R_0805_2012Metric)
(fields
(field (name F0) R)
(field (name F1) R))
(libsource (lib Device) (part R))
(sheetpath (names /top/8136002053123588309) (tstamps /top/8136002053123588309))))
(nets
(net (code 1) (name GND)
(node (ref R2) (pin 1)))
(net (code 2) (name VIN)
(node (ref R1) (pin 1)))
(net (code 3) (name VO)
(node (ref R1) (pin 2))
(node (ref R2) (pin 2))))
)
</code></pre></div>
<p>You can also generate the netlist in XML format:</p>
<div class="highlight"><pre><span></span><code>>>> generate_xml()
</code></pre></div>
<p>This is useful in a KiCad environment where the XML file is used as the
input to BOM-generation tools.</p>
<p>If you're designing with KiCad and want to skip some steps, you may go
directly to a PCB like this:</p>
<div class="highlight"><pre><span></span><code>>>> generate_pcb()
</code></pre></div>
<p>This outputs a <code>.kicad_pcb</code> file that you can open in PCBNEW without
having to import the netlist.
(Note that you will need to have KiCad installed since <code>generate_pcb</code> uses its
<code>pcbnew</code> Python library to create the PCB.)</p>
<p>The <code>generate_pcb()</code> function accepts the following optional arguments:</p>
<ul>
<li><code>pcb_file</code>: Either a file object that can be written to, or a string containing a file name, or <code>None</code>.</li>
<li><code>fp_libs</code>: List of paths to directories containing footprint libraries.</li>
</ul>
<h1 id="going-deeper">Going Deeper</h1>
<p>This section will talk about more advanced SKiDL features
that make designing complicated circuits easier.</p>
<h2 id="basic-skidl-objects-parts-pins-nets-buses">Basic SKiDL Objects: Parts, Pins, Nets, Buses</h2>
<p>SKiDL uses four types of objects to represent a circuit: <code>Part</code>, <code>Pin</code>,
<code>Net</code>, and <code>Bus</code>.</p>
<p>The <code>Part</code> object represents an electronic component, which SKiDL thinks of as a simple
bag of <code>Pin</code> objects with a few other attributes attached
(like the part number, name, reference, value, footprint, etc.).</p>
<p>The <code>Pin</code> object represents a terminal that brings an electronic signal into
and out of the part. Each <code>Pin</code> object stores information on which part it belongs to
and which nets it is attached to.</p>
<p>A <code>Net</code> object is kind of like a <code>Part</code>: it's a simple bag of pins.
But unlike a part, pins can be added to a net when a pin on some part is attached
or when it is merged with another net.</p>
<p>Finally, a <code>Bus</code> is just a collection of multiple <code>Net</code> objects.
A bus of a certain width can be created from a number of existing nets,
newly-created nets, or both.</p>
<h2 id="creating-skidl-objects">Creating SKiDL Objects</h2>
<p>Here's the most common way to create a part in your circuit:</p>
<div class="highlight"><pre><span></span><code><span class="n">my_part</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="s1">'some_library'</span><span class="p">,</span> <span class="s1">'some_part_name'</span><span class="p">)</span>
</code></pre></div>
<p>When this is processed, the current directory will be checked for a file
called <code>some_library.lib</code> or <code>some_library.kicad_sym</code>
which will be opened and scanned for a part with the
name <code>some_part_name</code>. If the file is not found or it doesn't contain
the requested part, then the process will be repeated using KiCad's default
library directory.
(You may change SKiDL's library search by changing the list of directories
stored in the <code>skidl.lib_search_paths_kicad</code> list.)</p>
<p>You're not restricted to using only the current directory or the KiCad default
directory to search for parts. You can also search any file for a part by
using a full file name:</p>
<div class="highlight"><pre><span></span><code><span class="n">my_part</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="s1">'C:/my_libs/my_great_parts.lib'</span><span class="p">,</span> <span class="s1">'my_super_regulator'</span><span class="p">)</span>
</code></pre></div>
<p>You're also not restricted to getting an exact match on the part name: you may
use a <em>regular expression</em> instead. For example, this will find a part
with "358" anywhere in a part name or alias:</p>
<div class="highlight"><pre><span></span><code><span class="n">my_part</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="s1">'Amplifier_Audio'</span><span class="p">,</span> <span class="s1">'.*386.*'</span><span class="p">)</span>
</code></pre></div>
<p>If the regular expression matches more than one part, then you'll only get the
first match and a warning that multiple parts were found.</p>
<p>Once you have the part, you can <a href="#instantiating-parts">set its attributes</a>
as was described previously.</p>
<p>Creating nets and buses is straightforward:</p>
<div class="highlight"><pre><span></span><code><span class="n">my_net</span> <span class="o">=</span> <span class="n">Net</span><span class="p">()</span> <span class="c1"># An unnamed net.</span>
<span class="n">my_other_net</span> <span class="o">=</span> <span class="n">Net</span><span class="p">(</span><span class="s1">'Fred'</span><span class="p">)</span> <span class="c1"># A named net.</span>
<span class="n">my_bus</span> <span class="o">=</span> <span class="n">Bus</span><span class="p">(</span><span class="s1">'bus_name'</span><span class="p">,</span> <span class="mi">8</span><span class="p">)</span> <span class="c1"># Named, byte-wide bus with nets bus_name0, bus_name1, ...</span>
<span class="n">anon_bus</span> <span class="o">=</span> <span class="n">Bus</span><span class="p">(</span><span class="mi">4</span><span class="p">)</span> <span class="c1"># Four-bit bus with an automatically-assigned name.</span>
</code></pre></div>
<p>As with parts, SKiDL will alter the name you assign if it collides with another net or bus
having the same name.</p>
<p>You may also create a bus by combining existing nets, buses, or the pins of parts
in any combination:</p>
<div class="highlight"><pre><span></span><code><span class="n">my_part</span> <span class="o">=</span> <span class="n">Part</span><span class="p">(</span><span class="s1">'Amplifier_Audio'</span><span class="p">,</span> <span class="s1">'LM386'</span><span class="p">)</span>
<span class="n">a_net</span> <span class="o">=</span> <span class="n">Net</span><span class="p">()</span>
<span class="n">b_net</span> <span class="o">=</span> <span class="n">Net</span><span class="p">()</span>
<span class="n">bus_nets</span> <span class="o">=</span> <span class="n">Bus</span><span class="p">(</span><span class="s1">'net_bus'</span><span class="p">,</span> <span class="n">a_net</span><span class="p">,</span> <span class="n">b_net</span><span class="p">)</span> <span class="c1"># A 2-bit bus from nets.</span>
<span class="n">bus_pins</span> <span class="o">=</span> <span class="n">Bus</span><span class="p">(</span><span class="s1">'pin_bus'</span><span class="p">,</span> <span class="n">my_part</span><span class="p">[</span><span class="mi">1</span><span class="p">],</span> <span class="n">my_part</span><span class="p">[</span><span class="mi">3</span><span class="p">])</span> <span class="c1"># A 2-bit bus from pins.</span>
<span class="n">bus_buses</span> <span class="o">=</span> <span class="n">Bus</span><span class="p">(</span><span class="s1">'bus_bus'</span><span class="p">,</span> <span class="n">my_bus</span><span class="p">)</span> <span class="c1"># An 8-bit bus.</span>
<span class="n">bus_combo</span> <span class="o">=</span> <span class="n">Bus</span><span class="p">(</span><span class="s1">'mongrel'</span><span class="p">,</span> <span class="mi">8</span><span class="p">,</span> <span class="n">a_net</span><span class="p">,</span> <span class="n">my_bus</span><span class="p">,</span> <span class="n">my_part</span><span class="p">[</span><span class="mi">2</span><span class="p">])</span> <span class="c1"># 8+1+8+1 = 18-bit bus.</span>
</code></pre></div>
<p>You can also build a bus incrementally by inserting or extending it with
widths, nets, buses or pins:</p>
<div class="highlight"><pre><span></span><code><span class="n">bus</span> <span class="o">=</span> <span class="n">Bus</span><span class="p">(</span><span class="s1">'A'</span><span class="p">,</span> <span class="mi">8</span><span class="p">)</span> <span class="c1"># Eight-bit bus.</span>
<span class="n">bus</span><span class="o">.</span><span class="n">insert</span><span class="p">(</span><span class="mi">4</span><span class="p">,</span> <span class="n">Bus</span><span class="p">(</span><span class="s1">'I'</span><span class="p">,</span> <span class="mi">3</span><span class="p">))</span> <span class="c1"># Insert 3-bit bus before bus line bus[4].</span>
<span class="n">bus</span><span class="o">.</span><span class="n">extend</span><span class="p">(</span><span class="mi">5</span><span class="p">,</span> <span class="n">Pin</span><span class="p">(),</span> <span class="n">Net</span><span class="p">())</span> <span class="c1"># Extend bus with another 5-bit bus, a pin, and a net.</span>
</code></pre></div>
<p>And finally, you may create a <code>Pin</code> object although you'll probably never do this
unless you're building a <code>Part</code> object from scratch:</p>
<div class="highlight"><pre><span></span><code>>>> p = Pin(num=1, name='my_pin', func=Pin.TRISTATE)
>>> p
Pin ???/1/my_pin/TRISTATE
</code></pre></div>
<h2 id="finding-skidl-objects">Finding SKiDL Objects</h2>
<p>If you want to access a bus, net, or part that's already been created,
use the <code>get()</code> class method:</p>
<div class="highlight"><pre><span></span><code><span class="n">n</span> <span class="o">=</span> <span class="n">Net</span><span class="o">.</span><span class="n">get</span><span class="p">(</span><span class="s1">'Fred'</span><span class="p">)</span> <span class="c1"># Find the existing Net object named 'Fred'.</span>
<span class="n">b</span> <span class="o">=</span> <span class="n">Bus</span><span class="o">.</span><span class="n">get</span><span class="p">(</span><span class="s1">'A'</span><span class="p">)</span> <span class="c1"># Find the existing Bus object named 'A'.</span>
<span class="n">p</span> <span class="o">=</span> <span class="n">Part</span><span class="o">.</span><span class="n">get</span><span class="p">(</span><span class="s1">'AS6C1616'</span><span class="p">)</span> <span class="c1"># Find all parts with this part name.</span>
</code></pre></div>
<p>If a net or bus with the exact name is found (no wild-card searches using regular expressions are allowed),
then that SKiDL object is returned.
Otherwise, <code>None</code> is returned.</p>
<p>For parts, the search is performed using string matching on part names,
references (e.g., <code>R4</code>), and aliases.
In addition, regular expression matching is used to search within the
part descriptions, so you could search for all parts with "ram" in their description.</p>
<p>If you want to access a particular bus or net and
create it if it doesn't already exist, then use the <code>fetch()</code> class method:</p>
<div class="highlight"><pre><span></span><code><span class="n">n</span> <span class="o">=</span> <span class="n">Net</span><span class="o">.</span><span class="n">fetch</span><span class="p">(</span><span class="s1">'Fred'</span><span class="p">)</span> <span class="c1"># Find the existing Net object named 'Fred' or create it if not found.</span>
<span class="n">b</span> <span class="o">=</span> <span class="n">Bus</span><span class="o">.</span><span class="n">fetch</span><span class="p">(</span><span class="s1">'A'</span><span class="p">,</span> <span class="mi">8</span><span class="p">)</span> <span class="c1"># Find the existing Bus object named 'A' or create it if not found.</span>
</code></pre></div>
<p>Note that with the <code>Bus.fetch()</code> method, you also have to provide the arguments to
build the bus (such as its width) in case it doesn't exist.</p>
<h2 id="copying-skidl-objects">Copying SKiDL Objects</h2>
<p>Instead of creating a SKiDL object from scratch, sometimes it's easier to just
copy an existing object. Here are some examples of creating a resistor and then making
some copies of it:</p>
<div class="highlight"><pre><span></span><code>>>> r1 = Part('Device', 'R', value=500) # Add a resistor to the circuit.
>>> r2 = r1.copy() # Make a single copy of the resistor.
>>> r2_lst = r1.copy(1) # Make a single copy, but return it in a list.
>>> r3 = r1.copy(value='1K') # Make a single copy, but give it a different value.
>>> r4 = r1(value='1K') # You can also call the object directly to make copies.
>>> r5, r6, r7 = r1(3, value='1K') # Make three copies of a 1-KOhm resistor.
>>> r8, r9, r10 = r1(value=[110,220,330]) # Make three copies, each with a different value.
>>> r11, r12 = 2 <span class="gs">* r1 # Make copies using the '*</span>' operator.
>>> r13, r14 = 2 * r1(value='1K') # This actually makes three 1-KOhm resistors!!!
</code></pre></div>
<p>The last example demonstrates an unexpected result when using the <code>*</code> operator:</p>
<ol>
<li>The resistor is called with a value of 1-KOhm, creating a copy of the resistor with that value of resistance.</li>
<li>The <code>*</code> operator is applied to the resistor <em>copy</em>, returning two more 1-KOhm resistors. Now the original resistor has been copied <em>three</em> times.</li>
<li>The two new resistors returned by the <code>*</code> operator are assigned to <code>r13</code> and <code>r14</code>.</li>
</ol>
<p>After these operations, the second and third copies can be referenced, but any reference to
the first copy has been lost so it just floats around, unconnected to anything, only to raise
errors later when the ERC is run.</p>
<p>In some cases it's clearer to create parts by copying a <em>template part</em> that
doesn't actually get included in the netlist for the circuitry:</p>
<div class="highlight"><pre><span></span><code><span class="o">>>></span><span class="w"> </span><span class="nv">rt</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="nv">Part</span><span class="ss">(</span><span class="s1">'Device'</span>,<span class="w"> </span><span class="s1">'R'</span>,<span class="w"> </span><span class="nv">dest</span><span class="o">=</span><span class="nv">TEMPLATE</span><span class="ss">)</span><span class="w"> </span>#<span class="w"> </span><span class="nv">Create</span><span class="w"> </span><span class="nv">a</span><span class="w"> </span><span class="nv">resistor</span><span class="w"> </span><span class="nv">just</span><span class="w"> </span><span class="k">for</span><span class="w"> </span><span class="nv">copying</span>.<span class="w"> </span><span class="nv">It</span><span class="err">'s not added to the circuit.</span>
<span class="o">>>></span><span class="w"> </span><span class="nv">r1</span>,<span class="w"> </span><span class="nv">r2</span>,<span class="w"> </span><span class="nv">r3</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="nv">rt</span><span class="ss">(</span><span class="mi">3</span>,<span class="w"> </span><span class="nv">value</span><span class="o">=</span><span class="s1">'1K'</span><span class="ss">)</span><span class="w"> </span>#<span class="w"> </span><span class="nv">Make</span><span class="w"> </span><span class="nv">three</span><span class="w"> </span><span class="mi">1</span><span class="o">-</span><span class="nv">KOhm</span><span class="w"> </span><span class="nv">copies</span><span class="w"> </span><span class="nv">that</span><span class="w"> </span><span class="nv">become</span><span class="w"> </span><span class="nv">part</span><span class="w"> </span><span class="nv">of</span><span class="w"> </span><span class="nv">the</span><span class="w"> </span><span class="nv">actual</span><span class="w"> </span><span class="nv">circuitry</span>.
</code></pre></div>
<h2 id="accessing-part-pins-and-bus-lines">Accessing Part Pins and Bus Lines</h2>
<h3 id="accessing-part-pins">Accessing Part Pins</h3>
<p>You may access the pins on a part or the individual nets of a bus
using numbers, slices, strings, and regular expressions, either singly or in any combination.</p>
<p>Suppose you have a PIC10 processor in a six-pin package:</p>
<div class="highlight"><pre><span></span><code>>>> pic10 = Part('MCU_Microchip_PIC10', 'pic10f220-iot')
>>> pic10
PIC10F220-IOT (PIC10F222-IOT): 512W Flash, 24B SRAM, SOT-23-6
Pin U3/1/GP0/BIDIRECTIONAL
Pin U3/2/VSS/POWER-IN
Pin U3/3/GP1/BIDIRECTIONAL
Pin U3/4/GP2/BIDIRECTIONAL
Pin U3/5/VDD/POWER-IN
Pin U3/6/GP3/INPUT
</code></pre></div>
<p>The most natural way to access one of its pins is to give the pin number
in brackets:</p>
<div class="highlight"><pre><span></span><code>>>> pic10[3]
Pin U1/3/GP1/BIDIRECTIONAL
</code></pre></div>
<p>(If you have a part in a BGA package with pins numbers like <code>C11</code>, then
you'll have to enter the pin number as a quoted string like <code>'C11'</code>.)</p>
<p>You can also get several pins at once in a list:</p>
<div class="highlight"><pre><span></span><code>>>> pic10[3,1,6]
[Pin U1/3/GP1/BIDIRECTIONAL, Pin U1/1/GP0/BIDIRECTIONAL, Pin U1/6/GP3/INPUT]
</code></pre></div>
<p>You can even use Python slice notation:</p>
<div class="highlight"><pre><span></span><code>>>> pic10[2:4] # Get pins 2 through 4.
[Pin U1/2/VSS/POWER-IN, Pin U1/3/GP1/BIDIRECTIONAL, Pin U1/4/GP2/BIDIRECTIONAL]
>>> pic10[4:2] # Get pins 4 through 2.
[Pin U1/4/GP2/BIDIRECTIONAL, Pin U1/3/GP1/BIDIRECTIONAL, Pin U1/2/VSS/POWER-IN]
>>> pic10[:] # Get all the pins.
[Pin U1/1/GP0/BIDIRECTIONAL,
Pin U1/2/VSS/POWER-IN,
Pin U1/3/GP1/BIDIRECTIONAL,
Pin U1/4/GP2/BIDIRECTIONAL,
Pin U1/5/VDD/POWER-IN,
Pin U1/6/GP3/INPUT]
</code></pre></div>
<p>(It's important to note that the slice notation used by SKiDL for parts is slightly
different than standard Python. In Python, a slice <code>n:m</code> would fetch indices
<code>n</code>, <code>n+1</code>, <code>...</code>, <code>m-1</code>. With SKiDL, it actually fetches all the
way up to the last number: <code>n</code>, <code>n+1</code>, <code>...</code>, <code>m-1</code>, <code>m</code>.
The reason for doing this is that most electronics designers are used to
the bounds on a slice including both endpoints. Perhaps it is a mistake to
do it this way. We'll see...)</p>
<p>In addition to the bracket notation, you may also get a single pin using an attribute name
that begins with a '<code>p</code>' followed by the pin number:</p>
<div class="highlight"><pre><span></span><code>>>> pic10.p2
Pin U1/2/VSS/POWER-IN
</code></pre></div>
<p>Instead of pin numbers, sometimes it makes the design intent more clear to
access pins by their names.
For example, it's more obvious that a voltage supply net is being
attached to the power pin of the processor when it's expressed like this:</p>
<div class="highlight"><pre><span></span><code><span class="n">pic10</span><span class="p">[</span><span class="s1">'VDD'</span><span class="p">]</span> <span class="o">+=</span> <span class="n">Net</span><span class="p">(</span><span class="s1">'supply_5V'</span><span class="p">)</span>
</code></pre></div>
<p>Like pin numbers, pin names can also be used as attributes to access the pin:</p>
<div class="highlight"><pre><span></span><code>>>> pic10.VDD
Pin U1/5/VDD/POWER-IN
</code></pre></div>
<p>You can use multiple names to get more than one pin:</p>
<div class="highlight"><pre><span></span><code>>>> pic10['VDD','VSS']
[Pin U1/5/VDD/POWER-IN, Pin U1/2/VSS/POWER-IN]
</code></pre></div>
<p>It can be tedious and error prone entering all the quote marks if you're accessing
many pin names. SKiDL lets you enter a single, comma or space-delimited string of
pin names:</p>
<div class="highlight"><pre><span></span><code>>>> pic10['GP0 GP1 GP2']
[Pin U1/1/GP0/BIDIRECTIONAL, Pin U1/3/GP1/BIDIRECTIONAL, Pin U1/4/GP2/BIDIRECTIONAL]
</code></pre></div>
<p>Some parts have sequentially-numbered sets of pins like the address and data buses of a RAM.
SKiDL lets you access these pins using a slice-like notation in a string like so:</p>
<div class="highlight"><pre><span></span><code>>>> ram = Part('Memory_RAM', 'AS6C1616')
>>> ram['DQ[0:2]']
[Pin U2/29/DQ0/BIDIRECTIONAL, Pin U2/31/DQ1/BIDIRECTIONAL, Pin U2/33/DQ2/BIDIRECTIONAL]
</code></pre></div>
<p>Or you may access the pins in the reverse order:</p>
<div class="highlight"><pre><span></span><code>>>> ram = Part('memory', 'sram_512ko')
>>> ram['DQ[2:0]']
[Pin U2/33/DQ2/BIDIRECTIONAL, Pin U2/31/DQ1/BIDIRECTIONAL, Pin U2/29/DQ0/BIDIRECTIONAL]
</code></pre></div>
<p>Some parts (like microcontrollers) have long pin names that list every function a pin
supports (e.g. <code>GP1/AN1/ICSPCLK</code>).
Employing the complete pin name is tedious to enter correctly and
obfuscates which particular function is being used.
SKiDL offers two ways to deal with this: 1) split the pin names into a set of shorter aliases, or
2) match pin names using regular expressions.</p>
<p>If a part has pin names where the subnames are separated by delimiters such as <code>/</code>,
then the subnames for each pin can be assigned as aliases:</p>
<div class="highlight"><pre><span></span><code>>>> pic10[3].name = 'GP1/AN1/ICSPCLK' # Give pin 3 a long name.
>>> pic10[3].split_name('/') # Split pin 3 name into aliases.
>>> pic10.split_pin_names('/') # Split all pin names into aliases.
>>> pic10[3].aliases # Show aliases for pin 3.
{'AN1', 'GP1', 'ICSPCLK'}
>>> pic10['AN1'] += Net('analog1') # Connect a net using the pin alias.
>>> pic10.AN1 += Net('analog2') # Or access the alias thru an attribute.
</code></pre></div>
<p>You can also split the pin names when you create the part by supplying a string
of delimiter characters:</p>
<div class="highlight"><pre><span></span><code>>>> pic10 = Part('MCU_Microchip_PIC10', 'pic10f220-iot', pin_splitters='/')
</code></pre></div>
<p>The other way to access a pin with a long name is to use a regular expression.
You'll have to enable regular expression matching for a particular part (it's off by default),
and you'll have to use an odd-looking expression, but here's how it's done:</p>
<div class="highlight"><pre><span></span><code><span class="o">>>></span><span class="w"> </span><span class="n">pic10</span><span class="p">[</span><span class="mh">3</span><span class="p">].</span><span class="n">name</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="p">'</span><span class="n">GP1</span><span class="o">/</span><span class="n">AN1</span><span class="o">/</span><span class="n">ICSPCLK</span><span class="p">'</span>
<span class="o">>>></span><span class="w"> </span><span class="n">pic10</span><span class="p">.</span><span class="n">match_pin_regex</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="n">True</span><span class="w"> </span><span class="p">#</span><span class="w"> </span><span class="n">Enable</span><span class="w"> </span><span class="n">regular</span><span class="w"> </span><span class="n">expression</span><span class="w"> </span><span class="n">matching</span><span class="p">.</span>
<span class="o">>>></span><span class="w"> </span><span class="n">pic10</span><span class="p">['.</span><span class="o">*/</span><span class="n">AN1</span><span class="o">/</span><span class="p">.</span><span class="o">*</span><span class="p">']</span><span class="w"> </span><span class="o">+=</span><span class="w"> </span><span class="n">Net</span><span class="p">('</span><span class="n">analog1</span><span class="p">')</span><span class="w"> </span><span class="p">#</span><span class="w"> </span><span class="n">I</span><span class="w"> </span><span class="n">told</span><span class="w"> </span><span class="n">you</span><span class="w"> </span><span class="n">the</span><span class="w"> </span><span class="n">expression</span><span class="w"> </span><span class="n">was</span><span class="w"> </span><span class="n">strange</span><span class="o">!</span>
</code></pre></div>
<p>You can avoid explicitly enabling regular expression matching by just creating the expression as
an <code>Rgx</code> like this:</p>
<div class="highlight"><pre><span></span><code><span class="o">>>></span><span class="w"> </span><span class="n">pic10</span><span class="err">[</span><span class="mi">3</span><span class="err">]</span><span class="p">.</span><span class="k">name</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="s1">'GP1/AN1/ICSPCLK'</span>
<span class="o">>>></span><span class="w"> </span><span class="n">pic10</span><span class="err">[</span><span class="n">Rgx</span><span class="p">(</span><span class="s1">'.*/AN1/.*'</span><span class="p">)</span><span class="err">]</span><span class="w"> </span><span class="o">+=</span><span class="w"> </span><span class="n">Net</span><span class="p">(</span><span class="s1">'analog1'</span><span class="p">)</span><span class="w"> </span><span class="c1"># No need to manually enable regular expression matching!</span>
<span class="n n-Quoted">`</span><span class="n n-Quoted n-Quoted-Escape">````</span><span class="n n-Quoted">`</span>
<span class="n">Since</span><span class="w"> </span><span class="n">you</span><span class="w"> </span><span class="n">may</span><span class="w"> </span><span class="n">access</span><span class="w"> </span><span class="n">pins</span><span class="w"> </span><span class="k">by</span><span class="w"> </span><span class="k">number</span><span class="w"> </span><span class="k">or</span><span class="w"> </span><span class="k">by</span><span class="w"> </span><span class="k">name</span><span class="w"> </span><span class="k">using</span><span class="w"> </span><span class="n">strings</span><span class="w"> </span><span class="k">or</span><span class="w"> </span><span class="n">regular</span><span class="w"> </span><span class="n">expressions</span><span class="p">,</span><span class="w"> </span><span class="n">it</span><span class="s1">'s worth</span>
<span class="s1">discussing how SKiDL decides which one to select.</span>
<span class="s1">When given a pin index, SKiDL stops searching and returns the matching pins as soon as</span>
<span class="s1">one of the following conditions succeeds:</span>
<span class="s1">1. One or more pin numbers match the index.</span>
<span class="s1">2. One or more pin aliases match the index using standard string matching.</span>
<span class="s1">3. One or more pin names match the index using standard string matching.</span>
<span class="s1">4. One or more pin aliases match the index using regular expression matching.</span>
<span class="s1">5. One or more pin names match the index using regular expression matching.</span>
<span class="s1">Since SKiDL prioritizes pin number matches over name matches,</span>
<span class="s1">what happens when you use a name that is the same as the number of another pin?</span>
<span class="s1">For example, a memory chip in a BGA would have pin numbers `A1`, `A2`, `A3`, ... but might</span>
<span class="s1">also have address pins named `A1`, `A2`, `A3`, ... .</span>
<span class="s1">In order to specifically target either pin numbers or names,</span>
<span class="s1">SKiDL provides the `p` and `n` part attributes:</span>
<span class="s1">```py</span>
<span class="s1">ram['</span><span class="n">A1</span><span class="p">,</span><span class="w"> </span><span class="n">A2</span><span class="p">,</span><span class="w"> </span><span class="n">A3</span><span class="s1">'] # Selects pin numbers A1, A2 and A3 if the part is a BGA.</span>
<span class="s1">ram.p['</span><span class="n">A1</span><span class="p">,</span><span class="w"> </span><span class="n">A2</span><span class="p">,</span><span class="w"> </span><span class="n">A3</span><span class="s1">'] # Use the p attribute to specifically select pin numbers A1, A2 and A3.</span>
<span class="s1">ram.n['</span><span class="n">A1</span><span class="p">,</span><span class="w"> </span><span class="n">A2</span><span class="p">,</span><span class="w"> </span><span class="n">A3</span><span class="s1">'] # Use the n attribute to specifically select pin names A1, A2 and A3.</span>
</code></pre></div>
<p><code>Part</code> objects also provide the <code>get_pins()</code> function which can select pins in even more ways.
For example, this would get every bidirectional pin of the processor:</p>
<div class="highlight"><pre><span></span><code>>>> pic10.get_pins(func=Pin.BIDIR)
[Pin U1/1/GP0/BIDIRECTIONAL, Pin U1/3/GP1/BIDIRECTIONAL, Pin U1/4/GP2/BIDIRECTIONAL]
</code></pre></div>
<p>You can access part pins algorithmically in a loop like this:</p>
<div class="highlight"><pre><span></span><code><span class="k">for</span> <span class="n">p</span> <span class="ow">in</span> <span class="n">pic10</span><span class="o">.</span><span class="n">get_pins</span><span class="p">():</span>
<span class="o"><</span><span class="n">do</span> <span class="n">something</span> <span class="k">with</span> <span class="n">p</span><span class="o">></span>
</code></pre></div>
<p>Or do the same thing using a <code>Part</code> object as an iterator:</p>
<div class="highlight"><pre><span></span><code><span class="k">for</span> <span class="n">p</span> <span class="ow">in</span> <span class="n">pic10</span><span class="p">:</span>
<span class="o"><</span><span class="n">do</span> <span class="n">something</span> <span class="k">with</span> <span class="n">p</span><span class="o">></span>
</code></pre></div>
<p>It's possible that <code>get_pins</code> will not generate the part's pins in order of increasing pin number.
If that's needed, then use the <code>ordered_pins</code> property to get the
pin numbers of all the part's pins in ascending order:</p>
<div class="highlight"><pre><span></span><code><span class="k">for</span> <span class="n">num</span> <span class="ow">in</span> <span class="n">pic10</span><span class="o">.</span><span class="n">ordered_pins</span><span class="p">:</span>
<span class="o"><</span> <span class="n">do</span> <span class="n">something</span> <span class="k">with</span> <span class="n">pic10</span><span class="p">[</span><span class="n">num</span><span class="p">]</span><span class="o">></span>
</code></pre></div>
<h3 id="accessing-bus-lines">Accessing Bus Lines</h3>
<p>Accessing the individual lines of a bus works similarly to accessing part pins:</p>
<div class="highlight"><pre><span></span><code>>>> a = Net('NET_A') # Create a named net.
>>> b = Bus('BUS_B', 4, a) # Create a five-bit bus.
>>> b
BUS_B:
BUS_B0: # Note how the individual lines of the bus are named.
BUS_B1:
BUS_B2:
BUS_B3:
NET_A: # The last net retains its original name.
>>> b[0] # Get the first line of the bus.
BUS_B0:
>>> b[2,4] # Get the second and fourth bus lines.
[BUS_B2: , NET_A: ]
>>> b[3:0] # Get the first four bus lines in reverse order.
[BUS_B3: , BUS_B2: , BUS_B1: , BUS_B0: ]
>>> b[-1] # Get the last bus line.
NET_A:
>>> b['BUS_B.*'] # Get all the bus lines except the last one.
[BUS_B0: , BUS_B1: , BUS_B2: , BUS_B3: ]
>>> b['NET_A'] # Get the last bus line.
NET_A:
>>> for line in b: # Access lines in bus using bus as an iterator.
...: print(line)
...:
BUS_B0:
BUS_B1:
BUS_B2:
BUS_B3:
NET_A:
</code></pre></div>
<h2 id="making-connections">Making Connections</h2>
<p>Pins, nets, parts and buses can all be connected together in various ways, but
the <strong>primary rule</strong> of SKiDL connections is:</p>
<blockquote>
<p><strong>The <code>+=</code> operator is the only way to make connections!</strong></p>
</blockquote>
<p>At times you'll mistakenly try to make connections using the
assignment operator (<code>=</code>). In many cases, SKiDL warns you if you do that,
but there are situations where it can't (because
Python is a general-purpose programming language where
assignment is a necessary operation).
So remember the primary rule!</p>
<p>After the primary rule, the next thing to remember is that SKiDL's main
purpose is creating netlists. To that end, it handles four basic, connection operations:</p>
<p><strong>Net-to-Net</strong>:
Connecting one net to another <em>merges</em> the pins on both nets
into a single, larger net.</p>
<p><strong>Pin-to-Net</strong>:
A pin is connected to a net, adding it to the list of pins
connected to that net. If the pin is already attached to other nets,
then those nets are merged with this net.</p>
<p><strong>Net-to-Pin</strong>:
This is the same as doing a pin-to-net connection.</p>
<p><strong>Pin-to-Pin</strong>:
A net is created and both pins are attached to it. If one or
both pins are already connected to other nets, then those nets are merged
with the newly-created.</p>
<p>For each type of connection operation, there are three variants based on
the number of things being connected:</p>
<p><strong>One-to-One</strong>:
This is the most frequent type of connection, for example, connecting one
pin to another or connecting a pin to a net.</p>
<p><strong>One-to-Many</strong>:
This mainly occurs when multiple pins are connected to the same net, like
when multiple ground pins of a chip are connected to the circuit ground net.</p>
<p><strong>Many-to-Many</strong>:
This usually involves bus connections to a part, such as connecting
a bus to the data or address pins of a processor. For this variant, there must be the
same number of things to connect in each set, e.g. you can't connect
three pins to four nets.</p>
<p>As a first example, let's connect a net to a pin on a part:</p>
<div class="highlight"><pre><span></span><code>>>> pic10 = Part('MCU_Microchip_PIC10', 'pic10f220-iot') # Get a part.
>>> io = Net('IO_NET') # Create a net.
>>> pic10.GP0 += io # Connect the net to a part pin.
>>> io # Show the pins connected to the net.
IO_NET: Pin U5/1/GP0/BIDIRECTIONAL
</code></pre></div>
<p>You may do the same operation in reverse by connecting the part pin to the net
with the same result:</p>
<div class="highlight"><pre><span></span><code>>>> pic10 = Part('MCU_Microchip_PIC10', 'pic10f220-iot')
>>> io = Net('IO_NET')
>>> io += pic10.GP0 # Connect a part pin to the net.
>>> io
IO_NET_1: Pin U6/1/GP0/BIDIRECTIONAL
</code></pre></div>
<p>You may also connect a pin directly to another pin.
In this case, an <em>implicit net</em> will be created between the pins that you can
access using the <code>net</code> attribute of either part pin:</p>
<div class="highlight"><pre><span></span><code><span class="o">>>></span><span class="w"> </span><span class="nv">pic10</span>.<span class="nv">GP1</span><span class="w"> </span><span class="o">+=</span><span class="w"> </span><span class="nv">pic10</span>.<span class="nv">GP2</span><span class="w"> </span>#<span class="w"> </span><span class="k">Connect</span><span class="w"> </span><span class="nv">two</span><span class="w"> </span><span class="nv">pins</span><span class="w"> </span><span class="nv">together</span>.
<span class="o">>>></span><span class="w"> </span><span class="nv">pic10</span>.<span class="nv">GP1</span>.<span class="nv">net</span><span class="w"> </span>#<span class="w"> </span><span class="k">Show</span><span class="w"> </span><span class="nv">the</span><span class="w"> </span><span class="nv">net</span><span class="w"> </span><span class="nv">connected</span><span class="w"> </span><span class="nv">to</span><span class="w"> </span><span class="nv">the</span><span class="w"> </span><span class="nv">pin</span>.
<span class="nv">N</span><span class="mh">$1</span>:<span class="w"> </span><span class="nv">Pin</span><span class="w"> </span><span class="nv">U6</span><span class="o">/</span><span class="mi">3</span><span class="o">/</span><span class="nv">GP1</span><span class="o">/</span><span class="nv">BIDIRECTIONAL</span>,<span class="w"> </span><span class="nv">Pin</span><span class="w"> </span><span class="nv">U6</span><span class="o">/</span><span class="mi">4</span><span class="o">/</span><span class="nv">GP2</span><span class="o">/</span><span class="nv">BIDIRECTIONAL</span>
<span class="o">>>></span><span class="w"> </span><span class="nv">pic10</span>.<span class="nv">GP2</span>.<span class="nv">net</span><span class="w"> </span>#<span class="w"> </span><span class="k">Show</span><span class="w"> </span><span class="nv">the</span><span class="w"> </span><span class="nv">net</span><span class="w"> </span><span class="nv">connected</span><span class="w"> </span><span class="nv">to</span><span class="w"> </span><span class="nv">the</span><span class="w"> </span><span class="nv">other</span><span class="w"> </span><span class="nv">pin</span>.<span class="w"> </span><span class="nv">Same</span><span class="w"> </span><span class="nv">thing</span><span class="o">!</span>
<span class="nv">N</span><span class="mh">$1</span>:<span class="w"> </span><span class="nv">Pin</span><span class="w"> </span><span class="nv">U6</span><span class="o">/</span><span class="mi">3</span><span class="o">/</span><span class="nv">GP1</span><span class="o">/</span><span class="nv">BIDIRECTIONAL</span>,<span class="w"> </span><span class="nv">Pin</span><span class="w"> </span><span class="nv">U6</span><span class="o">/</span><span class="mi">4</span><span class="o">/</span><span class="nv">GP2</span><span class="o">/</span><span class="nv">BIDIRECTIONAL</span>
</code></pre></div>
<p>You can connect multiple pins, all at once:</p>
<div class="highlight"><pre><span></span><code>>>> pic10 = Part('MCU_Microchip_PIC10', 'pic10f220-iot')
>>> pic10[1] += pic10[2,3,6]
>>> pic10[1].net
N$1: Pin U7/1/GP0/BIDIRECTIONAL, Pin U7/2/VSS/POWER-IN, Pin U7/3/GP1/BIDIRECTIONAL, Pin U7/6/GP3/INPUT
</code></pre></div>