-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathvax_sysdev.c
1899 lines (1564 loc) · 65.6 KB
/
vax_sysdev.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/* vax_sysdev.c: VAX 3900 system-specific logic
Copyright (c) 1998-2013, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of Robert M Supnik shall not be
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
This module contains the CVAX chip and VAX 3900 system-specific registers
and devices.
rom bootstrap ROM (no registers)
nvr non-volatile ROM (no registers)
csi console storage input
cso console storage output
cmctl memory controller
sysd system devices (SSC miscellany)
20-Dec-13 RMS Added unaligned register space access routines
23-Dec-10 RMS Added power clear call to boot routine (Mark Pizzolato)
25-Oct-05 RMS Automated CMCTL extended memory
16-Aug-05 RMS Fixed C++ declaration and cast problems
10-Mar-05 RMS Fixed bug in timer schedule routine (Mark Hittinger)
30-Sep-04 RMS Moved CADR, MSER, CONPC, CONPSL, machine_check, cpu_boot,
con_halt here from vax_cpu.c
Moved model-specific IPR's here from vax_cpu1.c
09-Sep-04 RMS Integrated powerup into RESET (with -p)
Added model-specific registers and routines from CPU
23-Jan-04 MP Added extended physical memory support (Mark Pizzolato)
07-Jun-03 MP Added calibrated delay to ROM reads (Mark Pizzolato)
Fixed calibration problems interval timer (Mark Pizzolato)
12-May-03 RMS Fixed compilation warnings from VC.Net
23-Apr-03 RMS Revised for 32b/64b t_addr
19-Aug-02 RMS Removed unused variables (David Hittner)
Allowed NVR to be attached to file
30-May-02 RMS Widened POS to 32b
28-Feb-02 RMS Fixed bug, missing end of table (Lars Brinkhoff)
*/
#include "vax_defs.h"
#include <math.h>
#ifdef DONT_USE_INTERNAL_ROM
#define BOOT_CODE_FILENAME "ka655x.bin"
#else /* !DONT_USE_INTERNAL_ROM */
#include "vax_ka655x_bin.h" /* Defines BOOT_CODE_FILENAME and BOOT_CODE_ARRAY, etc */
#endif /* DONT_USE_INTERNAL_ROM */
#define UNIT_V_NODELAY (UNIT_V_UF + 0) /* ROM access equal to RAM access */
#define UNIT_NODELAY (1u << UNIT_V_NODELAY)
t_stat vax_boot (int32 flag, CONST char *ptr);
int32 sys_model = 0;
/* Special boot command, overrides regular boot */
CTAB vax_cmd[] = {
{ "BOOT", &vax_boot, RU_BOOT,
"bo{ot} boot simulator\n", NULL, &run_cmd_message },
{ NULL }
};
/* Console storage control/status */
#define CSICSR_IMP (CSR_DONE + CSR_IE) /* console input */
#define CSICSR_RW (CSR_IE)
#define CSOCSR_IMP (CSR_DONE + CSR_IE) /* console output */
#define CSOCSR_RW (CSR_IE)
/* CMCTL configuration registers */
#define CMCNF_VLD 0x80000000 /* addr valid */
#define CMCNF_BA 0x1FF00000 /* base addr */
#define CMCNF_LOCK 0x00000040 /* lock NI */
#define CMCNF_SRQ 0x00000020 /* sig req WO */
#define CMCNF_SIG 0x0000001F /* signature */
#define CMCNF_RW (CMCNF_VLD | CMCNF_BA) /* read/write */
#define CMCNF_MASK (CMCNF_RW | CMCNF_SIG)
#define MEM_BANK (1 << 22) /* bank size 4MB */
#define MEM_SIG (0x17) /* ECC, 4 x 4MB */
/* CMCTL error register */
#define CMERR_RDS 0x80000000 /* uncorr err NI */
#define CMERR_FRQ 0x40000000 /* 2nd RDS NI */
#define CMERR_CRD 0x20000000 /* CRD err NI */
#define CMERR_PAG 0x1FFFFC00 /* page addr NI */
#define CMERR_DMA 0x00000100 /* DMA err NI */
#define CMERR_BUS 0x00000080 /* bus err NI */
#define CMERR_SYN 0x0000007F /* syndrome NI */
#define CMERR_W1C (CMERR_RDS | CMERR_FRQ | CMERR_CRD | \
CMERR_DMA | CMERR_BUS)
/* CMCTL control/status register */
#define CMCSR_PMI 0x00002000 /* PMI speed NI */
#define CMCSR_CRD 0x00001000 /* enb CRD int NI */
#define CMCSR_FRF 0x00000800 /* force ref WONI */
#define CMCSR_DET 0x00000400 /* dis err NI */
#define CMCSR_FDT 0x00000200 /* fast diag NI */
#define CMCSR_DCM 0x00000080 /* diag mode NI */
#define CMCSR_SYN 0x0000007F /* syndrome NI */
#define CMCSR_MASK (CMCSR_PMI | CMCSR_CRD | CMCSR_DET | \
CMCSR_FDT | CMCSR_DCM | CMCSR_SYN)
/* KA655 boot/diagnostic register */
#define BDR_BRKENB 0x00000080 /* break enable */
/* KA655 cache control register */
#define CACR_DRO 0x00FFFF00 /* diag bits RO */
#define CACR_V_DPAR 24 /* data parity */
#define CACR_FIXED 0x00000040 /* fixed bits */
#define CACR_CPE 0x00000020 /* parity err W1C */
#define CACR_CEN 0x00000010 /* enable */
#define CACR_DPE 0x00000004 /* disable par NI */
#define CACR_WWP 0x00000002 /* write wrong par NI */
#define CACR_DIAG 0x00000001 /* diag mode */
#define CACR_W1C (CACR_CPE)
#define CACR_RW (CACR_CEN | CACR_DPE | CACR_WWP | CACR_DIAG)
/* SSC base register */
#define SSCBASE_MBO 0x20000000 /* must be one */
#define SSCBASE_RW 0x1FFFFC00 /* base address */
/* SSC configuration register */
#define SSCCNF_BLO 0x80000000 /* batt low W1C */
#define SSCCNF_IVD 0x08000000 /* int dsbl NI */
#define SSCCNF_IPL 0x03000000 /* int IPL NI */
#define SSCCNF_ROM 0x00F70000 /* ROM param NI */
#define SSCCNF_CTLP 0x00008000 /* ctrl P enb */
#define SSCCNF_BAUD 0x00007700 /* baud rates NI */
#define SSCCNF_ADS 0x00000077 /* addr strb NI */
#define SSCCNF_W1C SSCCNF_BLO
#define SSCCNF_RW 0x0BF7F777
static BITFIELD ssc_cnf_bits[] = {
BITF(ADS1,3), /* addr strb-1 NI */
BITNC, /* unused */
BITF(ADS2,3), /* addr strb-2 NI */
BITNC, /* unused */
BITF(BAUD1,3), /* baud rate-1 NI */
BITNC, /* unused */
BITF(BAUD2,3), /* baud rate-2 NI */
BIT(CTLP), /* ctrl P enb */
BITF(ROM,8), /* ROM param NI */
BITF(IPL,2), /* int IPL NI */
BITNC, /* unused */
BIT(IVD), /* int dsbl NI */
BITNCF(3), /* unused */
BIT(BLO), /* batt low W1C */
ENDBITS
};
/* SSC timeout register */
#define SSCBTO_BTO 0x80000000 /* timeout W1C */
#define SSCBTO_RWT 0x40000000 /* read/write W1C */
#define SSCBTO_INTV 0x00FFFFFF /* interval NI */
#define SSCBTO_W1C (SSCBTO_BTO | SSCBTO_RWT)
#define SSCBTO_RW SSCBTO_INTV
/* SSC output port */
#define SSCOTP_MASK 0x0000000F /* output port */
/* SSC timer control/status */
#define TMR_CSR_ERR 0x80000000 /* error W1C */
#define TMR_CSR_DON 0x00000080 /* done W1C */
#define TMR_CSR_IE 0x00000040 /* int enb */
#define TMR_CSR_SGL 0x00000020 /* single WO */
#define TMR_CSR_XFR 0x00000010 /* xfer WO */
#define TMR_CSR_STP 0x00000004 /* stop */
#define TMR_CSR_RUN 0x00000001 /* run */
#define TMR_CSR_W1C (TMR_CSR_ERR | TMR_CSR_DON)
#define TMR_CSR_RW (TMR_CSR_IE | TMR_CSR_STP | TMR_CSR_RUN)
static BITFIELD tmr_csr_bits[] = {
BIT(RUN), /* run */
BITNC, /* unused */
BIT(STP), /* stop */
BITNC, /* unused */
BIT(XFR), /* xfer */
BIT(SGL), /* Single */
BIT(IE), /* Interrupt Enable */
BIT(DON), /* Xmit Ready */
BITNCF(23), /* unused */
BIT(ERR), /* Xmit Ready */
ENDBITS
};
/* SSC timer intervals */
#define TMR_INC 10000U /* usec/interval */
/* SSC timer vector */
#define TMR_VEC_MASK 0x000003FC /* vector */
/* SSC address strobes */
#define SSCADS_MASK 0x3FFFFFFC /* match or mask */
extern UNIT clk_unit;
extern int32 MSER;
extern int32 tmr_poll;
extern DEVICE vc_dev, lk_dev, vs_dev;
uint32 *rom = NULL; /* boot ROM */
uint32 *nvr = NULL; /* non-volatile mem */
int32 CADR = 0; /* cache disable reg */
int32 MSER = 0; /* mem sys error reg */
int32 conpc, conpsl; /* console reg */
int32 csi_csr = 0; /* control/status */
int32 cso_csr = 0; /* control/status */
int32 cmctl_reg[CMCTLSIZE >> 2] = { 0 }; /* CMCTL reg */
int32 ka_cacr = 0; /* KA655 cache ctl */
int32 ka_bdr = BDR_BRKENB; /* KA655 boot diag */
t_bool ka_hltenab = 1; /* Halt Enable / Autoboot flag */
int32 ssc_base = SSCBASE; /* SSC base */
int32 ssc_cnf = 0; /* SSC conf */
int32 ssc_bto = 0; /* SSC timeout */
int32 ssc_otp = 0; /* SSC output port */
int32 tmr_csr[2] = { 0 }; /* SSC timers */
uint32 tmr_tir[2] = { 0 }; /* curr interval */
uint32 tmr_tnir[2] = { 0 }; /* next interval */
int32 tmr_tivr[2] = { 0 }; /* vector */
t_bool tmr_inst[2] = { 0 }; /* wait instructions vs usecs */
int32 ssc_adsm[2] = { 0 }; /* addr strobes */
int32 ssc_adsk[2] = { 0 };
int32 cdg_dat[CDASIZE >> 2]; /* cache data */
t_stat rom_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw);
t_stat rom_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw);
t_stat rom_reset (DEVICE *dptr);
t_stat rom_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr);
const char *rom_description (DEVICE *dptr);
t_stat nvr_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw);
t_stat nvr_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw);
t_stat nvr_reset (DEVICE *dptr);
t_stat nvr_attach (UNIT *uptr, CONST char *cptr);
t_stat nvr_detach (UNIT *uptr);
t_stat nvr_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr);
const char *nvr_description (DEVICE *dptr);
t_stat csi_reset (DEVICE *dptr);
const char *csi_description (DEVICE *dptr);
t_stat cso_reset (DEVICE *dptr);
t_stat cso_svc (UNIT *uptr);
const char *cso_description (DEVICE *dptr);
t_stat tmr_svc (UNIT *uptr);
t_stat sysd_reset (DEVICE *dptr);
t_stat sysd_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr);
const char *sysd_description (DEVICE *dptr);
int32 rom_rd (int32 pa);
int32 nvr_rd (int32 pa);
void nvr_wr (int32 pa, int32 val, int32 lnt);
int32 csrs_rd (void);
int32 csrd_rd (void);
int32 csts_rd (void);
void csrs_wr (int32 dat);
void csts_wr (int32 dat);
void cstd_wr (int32 dat);
int32 cmctl_rd (int32 pa);
void cmctl_wr (int32 pa, int32 val, int32 lnt);
int32 ka_rd (int32 pa);
void ka_wr (int32 pa, int32 val, int32 lnt);
int32 cdg_rd (int32 pa);
void cdg_wr (int32 pa, int32 val, int32 lnt);
int32 ssc_rd (int32 pa);
void ssc_wr (int32 pa, int32 val, int32 lnt);
int32 tmr_tir_rd (int32 tmr);
void tmr_csr_wr (int32 tmr, int32 val);
int32 tmr_csr_rd (int32 tmr);
void tmr_sched (int32 tmr);
void tmr_incr (int32 tmr, uint32 inc);
int32 tmr0_inta (void);
int32 tmr1_inta (void);
int32 parity (int32 val, int32 odd);
t_stat sysd_powerup (void);
extern int32 intexc (int32 vec, int32 cc, int32 ipl, int ei);
extern int32 cqmap_rd (int32 pa);
extern void cqmap_wr (int32 pa, int32 val, int32 lnt);
extern int32 cqipc_rd (int32 pa);
extern void cqipc_wr (int32 pa, int32 val, int32 lnt);
extern int32 cqbic_rd (int32 pa);
extern void cqbic_wr (int32 pa, int32 val, int32 lnt);
extern int32 cqmem_rd (int32 pa);
extern void cqmem_wr (int32 pa, int32 val, int32 lnt);
extern int32 iccs_rd (void);
extern int32 todr_rd (void);
extern int32 rxcs_rd (void);
extern int32 rxdb_rd (void);
extern int32 txcs_rd (void);
extern void iccs_wr (int32 dat);
extern void todr_wr (int32 dat);
extern void rxcs_wr (int32 dat);
extern void txcs_wr (int32 dat);
extern void txdb_wr (int32 dat);
extern void ioreset_wr (int32 dat);
extern void cpu_idle (void);
/* ROM data structures
rom_dev ROM device descriptor
rom_unit ROM units
rom_reg ROM register list
*/
UNIT rom_unit = { UDATA (NULL, UNIT_FIX+UNIT_BINK, ROMSIZE) };
REG rom_reg[] = {
{ NULL }
};
MTAB rom_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0, "ADDRESS", NULL, NULL, &show_mapped_addr, (void *)ROMBASE, "Display base address" },
{ UNIT_NODELAY, UNIT_NODELAY, "fast access", "NODELAY", NULL, NULL, NULL, "Disable calibrated delay - ROM runs like RAM" },
{ UNIT_NODELAY, 0, "1usec calibrated access", "DELAY", NULL, NULL, NULL, "Enable calibrated ROM delay - ROM runs slowly" },
{ 0 }
};
DEVICE rom_dev = {
"ROM", &rom_unit, rom_reg, rom_mod,
1, 16, ROMAWIDTH, 4, 16, 32,
&rom_ex, &rom_dep, &rom_reset,
NULL, NULL, NULL,
NULL, 0, 0, NULL, NULL, NULL, &rom_help, NULL, NULL,
&rom_description
};
/* NVR data structures
nvr_dev NVR device descriptor
nvr_unit NVR units
nvr_reg NVR register list
*/
UNIT nvr_unit =
{ UDATA (NULL, UNIT_FIX+UNIT_BINK, NVRSIZE) };
REG nvr_reg[] = {
{ NULL }
};
MTAB nvr_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0, "ADDRESS", NULL, NULL, &show_mapped_addr, (void *)NVRBASE, "Display base address" },
{ 0 }
};
DEVICE nvr_dev = {
"NVR", &nvr_unit, nvr_reg, nvr_mod,
1, 16, NVRAWIDTH, 4, 16, 32,
&nvr_ex, &nvr_dep, &nvr_reset,
NULL, &nvr_attach, &nvr_detach,
NULL, 0, 0, NULL, NULL, NULL, &nvr_help, NULL, NULL,
&nvr_description
};
/* CSI data structures
csi_dev CSI device descriptor
csi_unit CSI unit descriptor
csi_reg CSI register list
*/
DIB csi_dib = { 0, 0, NULL, NULL, 1, IVCL (CSI), SCB_CSI, { NULL } };
UNIT csi_unit = { UDATA (NULL, 0, 0), KBD_POLL_WAIT };
REG csi_reg[] = {
{ ORDATAD (BUF, csi_unit.buf, 8, "last data item processed") },
{ ORDATAD (CSR, csi_csr, 16, "control/status register") },
{ FLDATAD (INT, int_req[IPL_CSI], INT_V_CSI, "interrupt pending flag") },
{ FLDATAD (DONE, csi_csr, CSR_V_DONE, "device done flag (CSR<7>)") },
{ FLDATAD (ERR, csi_csr, CSR_V_ERR, "error flag (CSR<15>)") },
{ FLDATAD (IE, csi_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") },
{ DRDATAD (POS, csi_unit.pos, 32, "number of characters input"), PV_LEFT },
{ DRDATAD (TIME, csi_unit.wait, 24, "input polling interval"), REG_NZ + PV_LEFT },
{ NULL }
};
MTAB csi_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL, NULL, &show_vec, NULL, "Display interrupt vector" },
{ 0 }
};
DEVICE csi_dev = {
"CSI", &csi_unit, csi_reg, csi_mod,
1, 10, 31, 1, 8, 8,
NULL, NULL, &csi_reset,
NULL, NULL, NULL,
&csi_dib, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL
};
/* CSO data structures
cso_dev CSO device descriptor
cso_unit CSO unit descriptor
cso_reg CSO register list
*/
DIB cso_dib = { 0, 0, NULL, NULL, 1, IVCL (CSO), SCB_CSO, { NULL } };
UNIT cso_unit = { UDATA (&cso_svc, UNIT_SEQ+UNIT_ATTABLE, 0), SERIAL_OUT_WAIT };
REG cso_reg[] = {
{ ORDATAD (BUF, cso_unit.buf, 8, "last data item processed") },
{ ORDATAD (CSR, cso_csr, 16, "control/status register") },
{ FLDATAD (INT, int_req[IPL_CSO], INT_V_CSO, "interrupt pending flag") },
{ FLDATAD (ERR, cso_csr, CSR_V_ERR, "error flag (CSR<15>)") },
{ FLDATAD (DONE, cso_csr, CSR_V_DONE, "device done flag (CSR<7>)") },
{ FLDATAD (IE, cso_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") },
{ DRDATAD (POS, cso_unit.pos, 32, "number of characters output"), PV_LEFT },
{ DRDATAD (TIME, cso_unit.wait, 24, "time from I/O initiation to interrupt"), PV_LEFT },
{ NULL }
};
MTAB cso_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL, NULL, &show_vec, NULL, "Display interrupt vector" },
{ 0 }
};
DEVICE cso_dev = {
"CSO", &cso_unit, cso_reg, cso_mod,
1, 10, 31, 1, 8, 8,
NULL, NULL, &cso_reset,
NULL, NULL, NULL,
&cso_dib, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL
};
/* SYSD data structures
sysd_dev SYSD device descriptor
sysd_unit SYSD units
sysd_reg SYSD register list
*/
DIB sysd_dib[] = {
{0, 0, NULL, NULL,
2, IVCL (TMR0), 0, { &tmr0_inta, &tmr1_inta } }
};
UNIT sysd_unit[] = {
{ UDATA (&tmr_svc, 0, 0) },
{ UDATA (&tmr_svc, 0, 0) }
};
REG sysd_reg[] = {
{ HRDATAD (CADR, CADR, 8, "cache disable register") },
{ HRDATAD (MSER, MSER, 8, "memory system error register") },
{ HRDATAD (CONPC, conpc, 32, "PC at console halt") },
{ HRDATAD (CONPSL, conpsl, 32, "PSL at console halt") },
{ BRDATAD (CMCSR, cmctl_reg, 16, 32, CMCTLSIZE >> 2, "CMCTL control and status registers") },
{ HRDATAD (CACR, ka_cacr, 8, "second-level cache control register") },
{ HRDATAD (BDR, ka_bdr, 8, "front panel jumper register") },
{ HRDATAD (BASE, ssc_base, 29, "SSC base address register") },
{ HRDATADF (CNF, ssc_cnf, 32, "SSC configuration register", ssc_cnf_bits) },
{ HRDATAD (BTO, ssc_bto, 32, "SSC bus timeout register") },
{ HRDATAD (OTP, ssc_otp, 4, "SSC output port") },
{ HRDATADF (TCSR0, tmr_csr[0], 32, "SSC timer 0 control/status register", tmr_csr_bits) },
{ HRDATAD (TIR0, tmr_tir[0], 32, "SSC timer 0 interval register") },
{ HRDATAD (TNIR0, tmr_tnir[0], 32, "SSC timer 0 next interval register") },
{ HRDATAD (TIVEC0, tmr_tivr[0], 9, "SSC timer 0 interrupt vector register") },
{ FLDATAD (TINST0, tmr_inst[0], 0, "SSC timer 0 last wait instructions") },
{ HRDATADF (TCSR1, tmr_csr[1], 32, "SSC timer 1 control/status register", tmr_csr_bits) },
{ HRDATAD (TIR1, tmr_tir[1], 32, "SSC timer 1 interval register") },
{ HRDATAD (TNIR1, tmr_tnir[1], 32, "SSC timer 1 next interval register") },
{ HRDATAD (TIVEC1, tmr_tivr[1], 9, "SSC timer 1 interrupt vector register") },
{ FLDATAD (TINST1, tmr_inst[1], 0, "SSC timer 1 last wait instructions") },
{ HRDATAD (ADSM0, ssc_adsm[0], 32, "SSC address match 0 address") },
{ HRDATAD (ADSK0, ssc_adsk[0], 32, "SSC address match 0 mask") },
{ HRDATAD (ADSM1, ssc_adsm[1], 32, "SSC address match 1 address") },
{ HRDATAD (ADSK1, ssc_adsk[1], 32, "SSC address match 1 mask") },
{ BRDATAD (CDGDAT, cdg_dat, 16, 32, CDASIZE >> 2, "cache diagnostic data store") },
{ FLDATAD (HLTENAB, ka_hltenab, 0, "KA655 Autoboot/Halt Enable") },
{ NULL }
};
#define DBG_REGR 0x0001 /* Interval TMR register read access */
#define DBG_REGW 0x0002 /* Interval TMR register write access */
#define DBG_INT 0x0004 /* Interval TMR Interrupt */
#define DBG_SCHD 0x0008 /* Interval TMR Scheduling */
#define DBG_TODR 0x0010 /* TODR register access */
#define DBG_CNF 0x0020 /* CNF register access */
DEBTAB sysd_debug[] = {
{"REGR", DBG_REGR, "Interval TMR register read access"},
{"REGW", DBG_REGW, "Interval TMR register write access"},
{"INT", DBG_INT, "Interval TMR Interrupt"},
{"SCHD", DBG_SCHD, "Interval TMR Scheduling"},
{"TODR", DBG_TODR, "TODR register access"},
{"CNF", DBG_CNF, "CNF register access"},
{0}
};
DEVICE sysd_dev = {
"SYSD", sysd_unit, sysd_reg, NULL,
2, 16, 16, 1, 16, 8,
NULL, NULL, &sysd_reset,
NULL, NULL, NULL,
&sysd_dib, DEV_DEBUG, 0, sysd_debug, NULL, NULL, &sysd_help, NULL, NULL,
&sysd_description
};
/* ROM: read only memory - stored in a buffered file
Register space access routines see ROM twice
ROM access has been 'regulated' to about 1Mhz to avoid issues
with testing the interval timers in self-test. Specifically,
the VAX boot ROM (ka655.bin) contains code which presumes that
the VAX runs at a particular slower speed when code is running
from ROM (which is not cached). These assumptions are built
into instruction based timing loops. As the host platform gets
much faster than the original VAX, the assumptions embedded in
these code loops are no longer valid.
Code has been added to the ROM implementation to limit CPU speed
to about 500K instructions per second. This heads off any future
issues with the embedded timing loops.
*/
int32 rom_rd (int32 pa)
{
int32 rg = ((pa - ROMBASE) & ROMAMASK) >> 2;
int32 val = rom[rg];
if (rom_unit.flags & UNIT_NODELAY)
return val;
return sim_rom_read_with_delay (val);
}
void rom_wr_B (int32 pa, int32 val)
{
int32 rg = ((pa - ROMBASE) & ROMAMASK) >> 2;
int32 sc = (pa & 3) << 3;
rom[rg] = ((val & 0xFF) << sc) | (rom[rg] & ~(0xFF << sc));
}
/* ROM examine */
t_stat rom_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw)
{
uint32 addr = (uint32) exta;
if ((vptr == NULL) || (addr & 03))
return SCPE_ARG;
if (addr >= ROMSIZE)
return SCPE_NXM;
*vptr = rom[addr >> 2];
return SCPE_OK;
}
/* ROM deposit */
t_stat rom_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw)
{
uint32 addr = (uint32) exta;
if (addr & 03)
return SCPE_ARG;
if (addr >= ROMSIZE)
return SCPE_NXM;
rom[addr >> 2] = (uint32) val;
return SCPE_OK;
}
/* ROM reset */
t_stat rom_reset (DEVICE *dptr)
{
if (rom == NULL)
rom = (uint32 *) calloc (ROMSIZE >> 2, sizeof (uint32));
if (rom == NULL)
return SCPE_MEM;
return SCPE_OK;
}
t_stat rom_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr)
{
fprintf (st, "Read-only memory (ROM)\n\n");
fprintf (st, "The boot ROM consists of a single unit, simulating the 128KB boot ROM. It\n");
fprintf (st, "has no registers. The boot ROM can be loaded with a binary byte stream\n");
fprintf (st, "using the LOAD -r command:\n\n");
fprintf (st, " LOAD -r KA655X.BIN load ROM image KA655X.BIN\n\n");
fprintf (st, "When the simulator starts running (via the BOOT command), if the ROM has\n");
fprintf (st, "not yet been loaded, an attempt will be made to automatically load the\n");
fprintf (st, "ROM image from the file ka655x.bin in the current working directory.\n");
fprintf (st, "If that load attempt fails, then a copy of the missing ROM file is\n");
fprintf (st, "written to the current directory and the load attempt is retried.\n\n");
fprintf (st, "ROM accesses a use a calibrated delay that slows ROM-based execution to\n");
fprintf (st, "about 500K instructions per second. This delay is required to make the\n");
fprintf (st, "power-up self-test routines run correctly on very fast hosts.\n");
fprint_set_help (st, dptr);
return SCPE_OK;
}
const char *rom_description (DEVICE *dptr)
{
return "read-only memory";
}
/* NVR: non-volatile RAM - stored in a buffered file */
int32 nvr_rd (int32 pa)
{
int32 rg = (pa - NVRBASE) >> 2;
return nvr[rg];
}
void nvr_wr (int32 pa, int32 val, int32 lnt)
{
int32 rg = (pa - NVRBASE) >> 2;
if (lnt < L_LONG) { /* byte or word? */
int32 sc = (pa & 3) << 3; /* merge */
int32 mask = (lnt == L_WORD)? 0xFFFF: 0xFF;
nvr[rg] = ((val & mask) << sc) | (nvr[rg] & ~(mask << sc));
}
else
nvr[rg] = val;
}
/* NVR examine */
t_stat nvr_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw)
{
uint32 addr = (uint32) exta;
if ((vptr == NULL) || (addr & 03))
return SCPE_ARG;
if (addr >= NVRSIZE)
return SCPE_NXM;
*vptr = nvr[addr >> 2];
return SCPE_OK;
}
/* NVR deposit */
t_stat nvr_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw)
{
uint32 addr = (uint32) exta;
if (addr & 03)
return SCPE_ARG;
if (addr >= NVRSIZE)
return SCPE_NXM;
nvr[addr >> 2] = (uint32) val;
return SCPE_OK;
}
/* NVR reset */
t_stat nvr_reset (DEVICE *dptr)
{
if (nvr == NULL) {
nvr = (uint32 *) calloc (NVRSIZE >> 2, sizeof (uint32));
nvr_unit.filebuf = nvr;
ssc_cnf = ssc_cnf | SSCCNF_BLO;
}
if (nvr == NULL)
return SCPE_MEM;
return SCPE_OK;
}
/* NVR attach */
t_stat nvr_attach (UNIT *uptr, CONST char *cptr)
{
t_stat r;
uptr->flags = uptr->flags | (UNIT_ATTABLE | UNIT_BUFABLE);
r = attach_unit (uptr, cptr);
if (r != SCPE_OK)
uptr->flags = uptr->flags & ~(UNIT_ATTABLE | UNIT_BUFABLE);
else {
uptr->hwmark = (uint32) uptr->capac;
ssc_cnf = ssc_cnf & ~SSCCNF_BLO;
}
return r;
}
/* NVR detach */
t_stat nvr_detach (UNIT *uptr)
{
t_stat r;
r = detach_unit (uptr);
if ((uptr->flags & UNIT_ATT) == 0)
uptr->flags = uptr->flags & ~(UNIT_ATTABLE | UNIT_BUFABLE);
return r;
}
t_stat nvr_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr)
{
fprintf (st, "Non-volatile Memory (NVR)\n\n");
fprintf (st, "The NVR consists of a single unit, simulating 1KB of battery-backed up memory\n");
fprintf (st, "in the SSC chip. When the simulator starts, NVR is cleared to 0, and the SSC\n");
fprintf (st, "battery-low indicator is set. Normally, NVR is saved and restored like other\n");
fprintf (st, "memory in the system. Alternately, NVR can be attached to a file. This\n");
fprintf (st, "allows its contents to be saved and restored independently of other memories,\n");
fprintf (st, "so that NVR state can be preserved across simulator runs.\n\n");
fprintf (st, "Successfully loading an NVR image clears the SSC battery-low indicator.\n\n");
return SCPE_OK;
}
const char *nvr_description (DEVICE *dptr)
{
return "non-volatile memory";
}
/* CSI: console storage input */
int32 csrs_rd (void)
{
return (csi_csr & CSICSR_IMP);
}
int32 csrd_rd (void)
{
csi_csr = csi_csr & ~CSR_DONE;
CLR_INT (CSI);
return (csi_unit.buf & 0377);
}
void csrs_wr (int32 data)
{
if ((data & CSR_IE) == 0)
CLR_INT (CSI);
else if ((csi_csr & (CSR_DONE + CSR_IE)) == CSR_DONE)
SET_INT (CSI);
csi_csr = (csi_csr & ~CSICSR_RW) | (data & CSICSR_RW);
}
t_stat csi_reset (DEVICE *dptr)
{
csi_unit.buf = 0;
csi_csr = 0;
CLR_INT (CSI);
return SCPE_OK;
}
const char *csi_description (DEVICE *dptr)
{
return "console storage input";
}
/* CSO: console storage output */
int32 csts_rd (void)
{
return (cso_csr & CSOCSR_IMP);
}
void csts_wr (int32 data)
{
if ((data & CSR_IE) == 0)
CLR_INT (CSO);
else
if ((cso_csr & (CSR_DONE + CSR_IE)) == CSR_DONE)
SET_INT (CSO);
cso_csr = (cso_csr & ~CSOCSR_RW) | (data & CSOCSR_RW);
}
void cstd_wr (int32 data)
{
cso_unit.buf = data & 0377;
cso_csr = cso_csr & ~CSR_DONE;
CLR_INT (CSO);
sim_activate (&cso_unit, cso_unit.wait);
}
t_stat cso_svc (UNIT *uptr)
{
cso_csr = cso_csr | CSR_DONE;
if (cso_csr & CSR_IE)
SET_INT (CSO);
if ((cso_unit.flags & UNIT_ATT) == 0)
return SCPE_OK;
if (putc (cso_unit.buf, cso_unit.fileref) == EOF) {
sim_perror ("CSO I/O error");
clearerr (cso_unit.fileref);
return SCPE_IOERR;
}
cso_unit.pos = cso_unit.pos + 1;
return SCPE_OK;
}
t_stat cso_reset (DEVICE *dptr)
{
cso_unit.buf = 0;
cso_csr = CSR_DONE;
CLR_INT (CSO);
sim_cancel (&cso_unit); /* deactivate unit */
return SCPE_OK;
}
const char *cso_description (DEVICE *dptr)
{
return "console storage output";
}
/* SYSD: SSC access mechanisms and devices
- IPR space read/write routines
- register space read/write routines
- SSC local register read/write routines
- SSC console storage UART
- SSC timers
- CMCTL local register read/write routines
*/
/* Read/write IPR register space
These routines implement the SSC's response to IPR's which are
sent off the CPU chip for processing.
*/
int32 ReadIPR (int32 rg)
{
int32 val;
switch (rg) {
case MT_ICCS: /* ICCS */
val = iccs_rd ();
break;
case MT_CSRS: /* CSRS */
val = csrs_rd ();
break;
case MT_CSRD: /* CSRD */
val = csrd_rd ();
break;
case MT_CSTS: /* CSTS */
val = csts_rd ();
break;
case MT_CSTD: /* CSTD */
val = 0;
break;
case MT_RXCS: /* RXCS */
val = rxcs_rd ();
break;
case MT_RXDB: /* RXDB */
val = rxdb_rd ();
break;
case MT_TXCS: /* TXCS */
val = txcs_rd ();
break;
case MT_TXDB: /* TXDB */
val = 0;
break;
case MT_TODR: /* TODR */
val = todr_rd ();
sim_debug (DBG_TODR, &sysd_dev, "ReadIPR() = 0x%X\n", val);
break;
case MT_CADR: /* CADR */
val = CADR & 0xFF;
break;
case MT_MSER: /* MSER */
val = MSER & 0xFF;
break;
case MT_CONPC: /* console PC */
val = conpc;
break;
case MT_CONPSL: /* console PSL */
val = conpsl;
break;
case MT_SID: /* SID */
val = CVAX_SID | CVAX_UREV;
break;
default:
ssc_bto = ssc_bto | SSCBTO_BTO; /* set BTO */
val = 0;
break;
}
return val;
}
void WriteIPR (int32 rg, int32 val)
{
switch (rg) {
case MT_ICCS: /* ICCS */
iccs_wr (val);
break;
case MT_TODR: /* TODR */
sim_debug (DBG_TODR, &sysd_dev, "WriteIPR(val=0x%X)\n", val);
todr_wr (val);
break;
case MT_CSRS: /* CSRS */
csrs_wr (val);
break;
case MT_CSRD: /* CSRD */
break;
case MT_CSTS: /* CSTS */
csts_wr (val);
break;
case MT_CSTD: /* CSTD */
cstd_wr (val);
break;
case MT_RXCS: /* RXCS */
rxcs_wr (val);
break;
case MT_RXDB: /* RXDB */
break;
case MT_TXCS: /* TXCS */
txcs_wr (val);
break;
case MT_TXDB: /* TXDB */
txdb_wr (val);
break;
case MT_CADR: /* CADR */
CADR = (val & CADR_RW) | CADR_MBO;
break;
case MT_MSER: /* MSER */
MSER = MSER & MSER_HM;
break;
case MT_IORESET: /* IORESET */
ioreset_wr (val);
break;
case MT_SID:
case MT_CONPC:
case MT_CONPSL: /* halt reg */
RSVD_OPND_FAULT;
default:
ssc_bto = ssc_bto | SSCBTO_BTO; /* set BTO */
break;
}
}
/* Read/write I/O register space
These routines are the 'catch all' for address space map. Any
address that doesn't explicitly belong to memory, I/O, or ROM
is given to these routines for processing.
*/
struct reglink { /* register linkage */
uint32 low; /* low addr */
uint32 high; /* high addr */
int32 (*read)(int32 pa); /* read routine */