diff --git a/config/Config-kernel.in b/config/Config-kernel.in
index 4c43190e40df5e..78155eb5926d74 100644
--- a/config/Config-kernel.in
+++ b/config/Config-kernel.in
@@ -1184,21 +1184,6 @@ config KERNEL_XDP_SOCKETS
 	  XDP sockets allows a channel between XDP programs and
 	  userspace applications.
 
-config KERNEL_WIRELESS_EXT
-	def_bool n
-
-config KERNEL_WEXT_CORE
-	def_bool KERNEL_WIRELESS_EXT
-
-config KERNEL_WEXT_PRIV
-	def_bool KERNEL_WIRELESS_EXT
-
-config KERNEL_WEXT_PROC
-	def_bool KERNEL_WIRELESS_EXT
-
-config KERNEL_WEXT_SPY
-	def_bool KERNEL_WIRELESS_EXT
-
 config KERNEL_PAGE_POOL
 	def_bool n
 
diff --git a/include/image-commands.mk b/include/image-commands.mk
index 41a5e1198a95a0..79a64f4bc13997 100644
--- a/include/image-commands.mk
+++ b/include/image-commands.mk
@@ -152,6 +152,20 @@ define Build/append-ubi
 		$(call Build/check-size,$(UBI_NAND_SIZE_LIMIT)))
 endef
 
+define Build/ubinize-image
+	sh $(TOPDIR)/scripts/ubinize-image.sh \
+		$(if $(UBOOTENV_IN_UBI),--uboot-env) \
+		$(foreach part,$(UBINIZE_PARTS),--part $(part)) \
+		--part $(word 1,$(1))="$(BIN_DIR)/$(DEVICE_IMG_PREFIX)-$(word 2,$(1))" \
+		$@.tmp \
+		-p $(BLOCKSIZE:%k=%KiB) -m $(PAGESIZE) \
+		$(if $(SUBPAGESIZE),-s $(SUBPAGESIZE)) \
+		$(if $(VID_HDR_OFFSET),-O $(VID_HDR_OFFSET)) \
+		$(UBINIZE_OPTS)
+	cat $@.tmp >> $@
+	rm $@.tmp
+endef
+
 define Build/ubinize-kernel
 	cp $@ $@.tmp
 	sh $(TOPDIR)/scripts/ubinize-image.sh \
diff --git a/include/image.mk b/include/image.mk
index f5ab1d7953c5ae..4b6acbe1aad6ac 100644
--- a/include/image.mk
+++ b/include/image.mk
@@ -582,7 +582,7 @@ define Device/Build/dtb
   $(KDIR)/image-$(1).dtb: FORCE
 	$(call Image/BuildDTB,$(strip $(2))/$(strip $(3)).dts,$$@)
 
-  image_prepare: $(KDIR)/image-$(1).dtb
+  compile-dtb: $(KDIR)/image-$(1).dtb
   endif
 
 endef
@@ -593,7 +593,7 @@ define Device/Build/dtbo
   $(KDIR)/image-$(1).dtbo: FORCE
 	$(call Image/BuildDTBO,$(strip $(2))/$(strip $(3)).dtso,$$@)
 
-  image_prepare: $(KDIR)/image-$(1).dtbo
+  compile-dtb: $(KDIR)/image-$(1).dtbo
   endif
 
 endef
@@ -841,18 +841,20 @@ define BuildImage
   download:
   prepare:
   compile:
+  compile-dtb:
   clean:
   image_prepare:
 
   ifeq ($(IB),)
-    .PHONY: download prepare compile clean image_prepare kernel_prepare install install-images
+    .PHONY: download prepare compile compile-dtb clean image_prepare kernel_prepare install install-images
     compile:
 		$(call Build/Compile)
 
     clean:
 		$(call Build/Clean)
 
-    image_prepare: compile
+    compile-dtb:
+    image_prepare: compile compile-dtb
 		mkdir -p $(BIN_DIR) $(KDIR)/tmp
 		rm -rf $(BUILD_DIR)/json_info_files
 		$(call Image/Prepare)
diff --git a/include/kernel-5.15 b/include/kernel-5.15
index 5cc07434b2a6cd..d93ae194b8aa1c 100644
--- a/include/kernel-5.15
+++ b/include/kernel-5.15
@@ -1,2 +1,2 @@
-LINUX_VERSION-5.15 = .147
-LINUX_KERNEL_HASH-5.15.147 = 56c1e65625d201db431efda7a3816e7b424071e7cb0245b2ba594d15b1fdfcd4
+LINUX_VERSION-5.15 = .148
+LINUX_KERNEL_HASH-5.15.148 = c48575c97fd9f4767cbe50a13b1b2b40ee42830aba3182fabd35a03259a6e5d8
diff --git a/include/kernel-6.1 b/include/kernel-6.1
index 87c6bf50977fe0..6c05ca0236eed2 100644
--- a/include/kernel-6.1
+++ b/include/kernel-6.1
@@ -1,2 +1,2 @@
-LINUX_VERSION-6.1 = .74
-LINUX_KERNEL_HASH-6.1.74 = b7fbd1d79faed2ce3570ef79dc1223e4e19c868b86326b14a435db56ebbb2022
+LINUX_VERSION-6.1 = .79
+LINUX_KERNEL_HASH-6.1.79 = faa49ca22fb55ed4d5ca2a55e07dd10e4e171cfc3b92568a631453cd2068b39b
diff --git a/include/kernel-build.mk b/include/kernel-build.mk
index b9513ec41435fb..c42dae0049ba4f 100644
--- a/include/kernel-build.mk
+++ b/include/kernel-build.mk
@@ -156,6 +156,10 @@ define BuildKernel
   compile: $(LINUX_DIR)/.modules
 	$(MAKE) -C image compile TARGET_BUILD=
 
+  dtb: $(STAMP_CONFIGURED)
+	$(_SINGLE)$(KERNEL_MAKE) scripts_dtc
+	$(MAKE) -C image compile-dtb TARGET_BUILD=
+
   oldconfig menuconfig nconfig xconfig: $(STAMP_PREPARED) $(STAMP_CHECKED) FORCE
 	rm -f $(LINUX_DIR)/.config.prev
 	rm -f $(STAMP_CONFIGURED)
diff --git a/include/package-defaults.mk b/include/package-defaults.mk
index 30b112c7d8cc9c..392aad0d5db8e0 100644
--- a/include/package-defaults.mk
+++ b/include/package-defaults.mk
@@ -20,7 +20,7 @@ define Package/Default
   PROVIDES:=
   EXTRA_DEPENDS:=
   MAINTAINER:=$(PKG_MAINTAINER)
-  SOURCE:=$(patsubst $(TOPDIR)/%,%,$(CURDIR))
+  SOURCE:=$(patsubst $(TOPDIR)/%,%,$(patsubst $(TOPDIR)/package/%,feeds/base/%,$(CURDIR)))
   ifneq ($(PKG_VERSION),)
     ifneq ($(PKG_RELEASE),)
       VERSION:=$(PKG_VERSION)-$(PKG_RELEASE)
diff --git a/include/rootfs.mk b/include/rootfs.mk
index f2ed648d2f3eb5..2128aefc2abda8 100644
--- a/include/rootfs.mk
+++ b/include/rootfs.mk
@@ -87,6 +87,11 @@ define prepare_rootfs
 			fi; \
 		done || true \
 	)
+	awk -i inplace \
+		'/^Status:/ { \
+			if ($$3 == "user") { $$3 = "ok" } \
+			else { sub(/,\<user\>|\<user\>,/, "", $$3) } \
+		}1' $(1)/usr/lib/opkg/status
 	$(if $(SOURCE_DATE_EPOCH),sed -i "s/Installed-Time: .*/Installed-Time: $(SOURCE_DATE_EPOCH)/" $(1)/usr/lib/opkg/status)
 	@-find $(1) -name CVS -o -name .svn -o -name .git -o -name '.#*' | $(XARGS) rm -rf
 	rm -rf \
diff --git a/include/subdir.mk b/include/subdir.mk
index 95009f814e29d4..b4edbf8b96c784 100644
--- a/include/subdir.mk
+++ b/include/subdir.mk
@@ -5,6 +5,9 @@
 ifeq ($(MAKECMDGOALS),prereq)
   SUBTARGETS:=prereq
   PREREQ_ONLY:=1
+# For target/linux related target add dtb to selectively compile dtbs
+else ifneq ($(filter target/linux/%,$(MAKECMDGOALS)),)
+  SUBTARGETS:=$(DEFAULT_SUBDIR_TARGETS) dtb
 else
   SUBTARGETS:=$(DEFAULT_SUBDIR_TARGETS)
 endif
diff --git a/include/toplevel.mk b/include/toplevel.mk
index f2dfde60cff929..4ec99b30de30fd 100644
--- a/include/toplevel.mk
+++ b/include/toplevel.mk
@@ -77,7 +77,8 @@ _ignore = $(foreach p,$(IGNORE_PACKAGES),--ignore $(p))
 
 prepare-tmpinfo: FORCE
 	@+$(MAKE) -r -s $(STAGING_DIR_HOST)/.prereq-build $(PREP_MK)
-	mkdir -p tmp/info
+	mkdir -p tmp/info feeds
+	[ -e $(TOPDIR)/feeds/base ] || ln -sf $(TOPDIR)/package $(TOPDIR)/feeds/base
 	$(_SINGLE)$(NO_TRACE_MAKE) -j1 -r -s -f include/scan.mk SCAN_TARGET="packageinfo" SCAN_DIR="package" SCAN_NAME="package" SCAN_DEPTH=5 SCAN_EXTRA=""
 	$(_SINGLE)$(NO_TRACE_MAKE) -j1 -r -s -f include/scan.mk SCAN_TARGET="targetinfo" SCAN_DIR="target/linux" SCAN_NAME="target" SCAN_DEPTH=3 SCAN_EXTRA="" SCAN_MAKEOPTS="TARGET_BUILD=1"
 	for type in package target; do \
diff --git a/include/u-boot.mk b/include/u-boot.mk
index 06867a70e426b6..454880989b5ec0 100644
--- a/include/u-boot.mk
+++ b/include/u-boot.mk
@@ -69,6 +69,7 @@ endef
 TARGET_DEP = TARGET_$(BUILD_TARGET)$(if $(BUILD_SUBTARGET),_$(BUILD_SUBTARGET))
 
 UBOOT_MAKE_FLAGS = \
+	PATH=$(STAGING_DIR_HOST)/bin:$(PATH) \
 	HOSTCC="$(HOSTCC)" \
 	HOSTCFLAGS="$(HOST_CFLAGS) $(HOST_CPPFLAGS) -std=gnu11" \
 	HOSTLDFLAGS="$(HOST_LDFLAGS)" \
diff --git a/package/base-files/files/etc/init.d/led b/package/base-files/files/etc/init.d/led
index 08a1e6df3bbaf6..ea2688cab29efa 100755
--- a/package/base-files/files/etc/init.d/led
+++ b/package/base-files/files/etc/init.d/led
@@ -3,6 +3,39 @@
 
 START=96
 
+led_color_set() {
+	local cfg="$1"
+	local sysfs="$2"
+
+	local max_b
+	local colors
+	local color
+	local multi_intensity
+	local value
+	local write
+
+	[ -e /sys/class/leds/${sysfs}/multi_intensity ] || return
+	[ -e /sys/class/leds/${sysfs}/multi_index ] || return
+
+	max_b="$(cat /sys/class/leds/${sysfs}/max_brightness)"
+	colors="$(cat /sys/class/leds/${sysfs}/multi_index | tr " " "\n")"
+	multi_intensity=""
+	for color in $colors; do
+		config_get value $1 "color_${color}" "0"
+		[ "$value" -gt 0 ] && write=1
+		[ "$value" -gt "$max_b" ] && value="$max_b"
+		multi_intensity="${multi_intensity}${value} "
+	done
+
+	# Check if any color is configured
+	[ "$write" = 1 ] || return
+	# Remove last whitespace
+	multi_intensity="${multi_intensity:0:-1}"
+
+	echo "setting '${name}' led color to '${multi_intensity}'"
+	echo "${multi_intensity}" > /sys/class/leds/${sysfs}/multi_intensity
+}
+
 load_led() {
 	local name
 	local sysfs
@@ -49,21 +82,29 @@ load_led() {
 	[ -e /sys/class/leds/${sysfs}/brightness ] && {
 		echo "setting up led ${name}"
 
-		printf "%s %s %d\n" \
+		printf "%s %s %d" \
 			"$sysfs" \
 			"$(sed -ne 's/^.*\[\(.*\)\].*$/\1/p' /sys/class/leds/${sysfs}/trigger)" \
 			"$(cat /sys/class/leds/${sysfs}/brightness)" \
 				>> /var/run/led.state
+		# Save default color if supported
+		[ -e /sys/class/leds/${sysfs}/multi_intensity ] && {
+			printf " %s" \
+				"$(sed 's/\ /:/g' /sys/class/leds/${sysfs}/multi_intensity)" \
+				>> /var/run/led.state
+		}
+		printf "\n" >> /var/run/led.state
 
 		[ "$default" = 0 ] &&
 			echo 0 >/sys/class/leds/${sysfs}/brightness
 
-		echo $trigger > /sys/class/leds/${sysfs}/trigger 2> /dev/null
-		ret="$?"
-
 		[ $default = 1 ] &&
 			cat /sys/class/leds/${sysfs}/max_brightness > /sys/class/leds/${sysfs}/brightness
 
+		led_color_set "$1" "$sysfs"
+
+		echo $trigger > /sys/class/leds/${sysfs}/trigger 2> /dev/null
+		ret="$?"
 		[ $ret = 0 ] || {
 			echo >&2 "Skipping trigger '$trigger' for led '$name' due to missing kernel module"
 			return 1
@@ -128,13 +169,17 @@ load_led() {
 start() {
 	[ -e /sys/class/leds/ ] && {
 		[ -s /var/run/led.state ] && {
-			local led trigger brightness
-			while read led trigger brightness; do
+			local led trigger brightness color
+			while read led trigger brightness color; do
 				[ -e "/sys/class/leds/$led/trigger" ] && \
 					echo "$trigger" > "/sys/class/leds/$led/trigger"
 
 				[ -e "/sys/class/leds/$led/brightness" ] && \
 					echo "$brightness" > "/sys/class/leds/$led/brightness"
+
+				[ -e "/sys/class/leds/$led/multi_intensity" ] && \
+					echo "$color" | sed 's/:/\ /g' > \
+						"/sys/class/leds/$led/multi_intensity"
 			done < /var/run/led.state
 			rm /var/run/led.state
 		}
diff --git a/package/base-files/files/lib/functions/uci-defaults.sh b/package/base-files/files/lib/functions/uci-defaults.sh
index a75bd116525b7e..b89cc8e9e309ab 100644
--- a/package/base-files/files/lib/functions/uci-defaults.sh
+++ b/package/base-files/files/lib/functions/uci-defaults.sh
@@ -654,6 +654,17 @@ ucidef_set_ntpserver() {
 	json_select ..
 }
 
+ucidef_set_poe() {
+	json_select_object poe
+		json_add_string "budget" "$1"
+		json_select_array ports
+			for port in $2; do
+				json_add_string "" "$port"
+			done
+		json_select ..
+	json_select ..
+}
+
 ucidef_add_wlan() {
 	local path="$1"; shift
 
diff --git a/package/base-files/files/lib/upgrade/common.sh b/package/base-files/files/lib/upgrade/common.sh
index af1182cb16a383..ef8d01e16896f3 100644
--- a/package/base-files/files/lib/upgrade/common.sh
+++ b/package/base-files/files/lib/upgrade/common.sh
@@ -165,6 +165,23 @@ part_magic_fat() {
 	[ "$magic" = "FAT" ] || [ "$magic_fat32" = "FAT32" ]
 }
 
+fitblk_get_bootdev() {
+	[ -e /sys/firmware/devicetree/base/chosen/rootdisk ] || return
+
+	local rootdisk="$(cat /sys/firmware/devicetree/base/chosen/rootdisk)"
+	local handle bootdev
+	for handle in /sys/class/block/*/of_node/phandle /sys/class/block/*/device/of_node/phandle; do
+		[ ! -e "$handle" ] && continue
+		if [ "$rootdisk" = "$(cat $handle)" ]; then
+			bootdev="${handle%/of_node/phandle}"
+			bootdev="${bootdev%/device}"
+			bootdev="${bootdev#/sys/class/block/}"
+			echo "$bootdev"
+			break
+		fi
+	done
+}
+
 export_bootdevice() {
 	local cmdline uuid blockdev uevent line class
 	local MAJOR MINOR DEVNAME DEVTYPE
@@ -196,6 +213,7 @@ export_bootdevice() {
 			done
 		;;
 		/dev/*)
+			[ "$rootpart" = "/dev/fit0" ] && rootpart="$(fitblk_get_bootdev)"
 			uevent="/sys/class/block/${rootpart##*/}/../uevent"
 		;;
 		0x[a-f0-9][a-f0-9][a-f0-9] | 0x[a-f0-9][a-f0-9][a-f0-9][a-f0-9] | \
diff --git a/package/base-files/files/lib/upgrade/nand.sh b/package/base-files/files/lib/upgrade/nand.sh
index d910bf17915982..0a6fd8432d4623 100644
--- a/package/base-files/files/lib/upgrade/nand.sh
+++ b/package/base-files/files/lib/upgrade/nand.sh
@@ -111,7 +111,7 @@ nand_remove_ubiblock() {
 
 	local ubiblk="ubiblock${ubivol:3}"
 	if [ -e "/dev/$ubiblk" ]; then
-		umount "/dev/$ubiblk" && echo "unmounted /dev/$ubiblk" || :
+		umount "/dev/$ubiblk" 2>/dev/null && echo "unmounted /dev/$ubiblk" || :
 		if ! ubiblock -r "/dev/$ubivol"; then
 			echo "cannot remove $ubiblk"
 			return 1
diff --git a/package/base-files/files/lib/upgrade/tar.sh b/package/base-files/files/lib/upgrade/tar.sh
new file mode 100644
index 00000000000000..a9d1d559e6f7dd
--- /dev/null
+++ b/package/base-files/files/lib/upgrade/tar.sh
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+# Example usage:
+#
+# {
+#         tar_print_member "date.txt" "It's $(date +"%Y")"
+#         tar_print_trailer
+# } > test.tar
+
+__tar_print_padding() {
+	dd if=/dev/zero bs=1 count=$1 2>/dev/null
+}
+
+tar_print_member() {
+	local name="$1"
+	local content="$2"
+	local mtime="${3:-$(date +%s)}"
+	local mode=644
+	local uid=0
+	local gid=0
+	local size=${#content}
+	local type=0
+	local link=""
+	local username="root"
+	local groupname="root"
+
+	# 100 byte of padding bytes, using 0x01 since the shell does not tolerate null bytes in strings
+	local pad=$'\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1'
+
+	# validate name (strip leading slash if present)
+	name=${name#/}
+
+	# truncate string header values to their maximum length
+	name=${name:0:100}
+	link=${link:0:100}
+	username=${username:0:32}
+	groupname=${groupname:0:32}
+
+	# construct header part before checksum field
+	local header1="${name}${pad:0:$((100 - ${#name}))}"
+	header1="${header1}$(printf '%07d\1' $mode)"
+	header1="${header1}$(printf '%07o\1' $uid)"
+	header1="${header1}$(printf '%07o\1' $gid)"
+	header1="${header1}$(printf '%011o\1' $size)"
+	header1="${header1}$(printf '%011o\1' $mtime)"
+
+	# construct header part after checksum field
+	local header2="$(printf '%d' $type)"
+	header2="${header2}${link}${pad:0:$((100 - ${#link}))}"
+	header2="${header2}ustar  ${pad:0:1}"
+	header2="${header2}${username}${pad:0:$((32 - ${#username}))}"
+	header2="${header2}${groupname}${pad:0:$((32 - ${#groupname}))}"
+
+	# calculate checksum over header fields
+	local checksum=0
+	for byte in $(printf '%s%8s%s' "$header1" "" "$header2" | tr '\1' '\0' | hexdump -ve '1/1 "%u "'); do
+		checksum=$((checksum + byte))
+	done
+
+	# print member header, padded to 512 byte
+	printf '%s%06o\0 %s' "$header1" $checksum "$header2" | tr '\1' '\0'
+	__tar_print_padding 183
+
+	# print content data, padded to multiple of 512 byte
+	printf "%s" "$content"
+	__tar_print_padding $((512 - (size % 512)))
+}
+
+tar_print_trailer() {
+	__tar_print_padding 1024
+}
diff --git a/package/base-files/files/sbin/sysupgrade b/package/base-files/files/sbin/sysupgrade
index 93150913024fb7..78ec455067910a 100755
--- a/package/base-files/files/sbin/sysupgrade
+++ b/package/base-files/files/sbin/sysupgrade
@@ -4,27 +4,35 @@
 . /lib/functions/system.sh
 . /usr/share/libubox/jshn.sh
 
-# initialize defaults
+# File-local constants
+CONF_TAR=/tmp/sysupgrade.tgz
+ETCBACKUP_DIR=/etc/backup
+INSTALLED_PACKAGES=${ETCBACKUP_DIR}/installed_packages.txt
+COMMAND=/lib/upgrade/do_stage2
+
+# File-local globals
+SAVE_OVERLAY=0
+SAVE_OVERLAY_PATH=
+SAVE_PARTITIONS=1
+SAVE_INSTALLED_PKGS=0
+SKIP_UNCHANGED=0
+CONF_IMAGE=
+CONF_BACKUP_LIST=0
+CONF_BACKUP=
+CONF_RESTORE=
+NEED_IMAGE=
+HELP=0
+TEST=0
+
+# Globals accessed in other files
 export MTD_ARGS=""
 export MTD_CONFIG_ARGS=""
 export INTERACTIVE=0
 export VERBOSE=1
 export SAVE_CONFIG=1
-export SAVE_OVERLAY=0
-export SAVE_OVERLAY_PATH=
-export SAVE_PARTITIONS=1
-export SAVE_INSTALLED_PKGS=0
-export SKIP_UNCHANGED=0
-export CONF_IMAGE=
-export CONF_BACKUP_LIST=0
-export CONF_BACKUP=
-export CONF_RESTORE=
 export IGNORE_MINOR_COMPAT=0
-export NEED_IMAGE=
-export HELP=0
 export FORCE=0
-export TEST=0
-export UMOUNT_ETCBACKUP_DIR=0
+export CONFFILES=/tmp/sysupgrade.conffiles
 
 # parse options
 while [ -n "$1" ]; do
@@ -33,18 +41,18 @@ while [ -n "$1" ]; do
 		-v) export VERBOSE="$(($VERBOSE + 1))";;
 		-q) export VERBOSE="$(($VERBOSE - 1))";;
 		-n) export SAVE_CONFIG=0;;
-		-c) export SAVE_OVERLAY=1 SAVE_OVERLAY_PATH=/etc;;
-		-o) export SAVE_OVERLAY=1 SAVE_OVERLAY_PATH=/;;
-		-p) export SAVE_PARTITIONS=0;;
-		-k) export SAVE_INSTALLED_PKGS=1;;
-		-u) export SKIP_UNCHANGED=1;;
-		-b|--create-backup) export CONF_BACKUP="$2" NEED_IMAGE=1; shift;;
-		-r|--restore-backup) export CONF_RESTORE="$2" NEED_IMAGE=1; shift;;
-		-l|--list-backup) export CONF_BACKUP_LIST=1;;
-		-f) export CONF_IMAGE="$2"; shift;;
+		-c) SAVE_OVERLAY=1 SAVE_OVERLAY_PATH=/etc;;
+		-o) SAVE_OVERLAY=1 SAVE_OVERLAY_PATH=/;;
+		-p) SAVE_PARTITIONS=0;;
+		-k) SAVE_INSTALLED_PKGS=1;;
+		-u) SKIP_UNCHANGED=1;;
+		-b|--create-backup) CONF_BACKUP="$2" NEED_IMAGE=1; shift;;
+		-r|--restore-backup) CONF_RESTORE="$2" NEED_IMAGE=1; shift;;
+		-l|--list-backup) CONF_BACKUP_LIST=1;;
+		-f) CONF_IMAGE="$2"; shift;;
 		-F|--force) export FORCE=1;;
-		-T|--test) export TEST=1;;
-		-h|--help) export HELP=1; break;;
+		-T|--test) TEST=1;;
+		-h|--help) HELP=1; break;;
 		--ignore-minor-compat-version) export IGNORE_MINOR_COMPAT=1;;
 		-*)
 			echo "Invalid option: $1" >&2
@@ -55,14 +63,7 @@ while [ -n "$1" ]; do
 	shift;
 done
 
-export CONFFILES=/tmp/sysupgrade.conffiles
-export CONF_TAR=/tmp/sysupgrade.tgz
-export ETCBACKUP_DIR=/etc/backup
-export INSTALLED_PACKAGES=${ETCBACKUP_DIR}/installed_packages.txt
-
-IMAGE="$1"
-
-[ -z "$IMAGE" -a -z "$NEED_IMAGE" -a $CONF_BACKUP_LIST -eq 0 -o $HELP -gt 0 ] && {
+print_help() {
 	cat <<EOF
 Usage: $0 [<upgrade-option>...] <image file or URL>
        $0 [-q] [-i] [-c] [-u] [-o] [-k] <backup-command> <file>
@@ -102,9 +103,20 @@ backup-command:
 	             sysupgrade -b. Does not create a backup file.
 
 EOF
-	exit 1
 }
 
+IMAGE="$1"
+
+if [ $HELP -gt 0 ]; then
+	print_help
+	exit 0
+fi
+
+if [ -z "$IMAGE" -a -z "$NEED_IMAGE" -a $CONF_BACKUP_LIST -eq 0 ]; then
+	print_help
+	exit 1
+fi
+
 [ -n "$IMAGE" -a -n "$NEED_IMAGE" ] && {
 	cat <<-EOF
 		-b|--create-backup and -r|--restore-backup do not perform a firmware upgrade.
@@ -143,7 +155,7 @@ list_static_conffiles() {
 		\( -type f -o -type l \) $filter 2>/dev/null
 }
 
-add_conffiles() {
+build_list_of_backup_config_files() {
 	local file="$1"
 
 	( list_static_conffiles "$find_filter"; list_changed_conffiles ) |
@@ -151,7 +163,7 @@ add_conffiles() {
 	return 0
 }
 
-add_overlayfiles() {
+build_list_of_backup_overlay_files() {
 	local file="$1"
 
 	local packagesfiles=$1.packagesfiles
@@ -203,12 +215,12 @@ add_overlayfiles() {
 
 if [ $SAVE_OVERLAY = 1 ]; then
 	[ ! -d /overlay/upper/etc ] && {
-		echo "Cannot find '/overlay/upper/etc', required for '-c'" >&2
+		echo "Cannot find '/overlay/upper/etc', required for '-c' or '-o'" >&2
 		exit 1
 	}
-	sysupgrade_init_conffiles="add_overlayfiles"
+	sysupgrade_init_conffiles="build_list_of_backup_overlay_files"
 else
-	sysupgrade_init_conffiles="add_conffiles"
+	sysupgrade_init_conffiles="build_list_of_backup_config_files"
 fi
 
 find_filter=""
@@ -222,8 +234,9 @@ fi
 
 include /lib/upgrade
 
-do_save_conffiles() {
+create_backup_archive() {
 	local conf_tar="$1"
+	local disabled
 
 	[ "$(rootfs_type)" = "tmpfs" ] && {
 		echo "Cannot save config while running from ramdisk." >&2
@@ -234,41 +247,42 @@ do_save_conffiles() {
 	run_hooks "$CONFFILES" $sysupgrade_init_conffiles
 	ask_bool 0 "Edit config file list" && vi "$CONFFILES"
 
-	if [ "$SAVE_INSTALLED_PKGS" -eq 1 ]; then
-		echo "${INSTALLED_PACKAGES}" >> "$CONFFILES"
-		mkdir -p "$ETCBACKUP_DIR"
-		# Avoid touching filesystem on each backup
-		RAMFS="$(mktemp -d -t sysupgrade.XXXXXX)"
-		mkdir -p "$RAMFS/upper" "$RAMFS/work"
-		mount -t overlay overlay -o lowerdir=$ETCBACKUP_DIR,upperdir=$RAMFS/upper,workdir=$RAMFS/work $ETCBACKUP_DIR &&
-			UMOUNT_ETCBACKUP_DIR=1 || {
-				echo "Cannot mount '$ETCBACKUP_DIR' as tmpfs to avoid touching disk while saving the list of installed packages." >&2
-				ask_bool 0 "Abort" && exit
-			}
-
-		# Format: pkg-name<TAB>{rom,overlay,unkown}
-		# rom is used for pkgs in /rom, even if updated later
-		find /usr/lib/opkg/info -name "*.control" \( \
-			\( -exec test -f /rom/{} \; -exec echo {} rom \; \) -o \
-			\( -exec test -f /overlay/upper/{} \; -exec echo {} overlay \; \) -o \
-			\( -exec echo {} unknown \; \) \
-			\) | sed -e 's,.*/,,;s/\.control /\t/' > ${INSTALLED_PACKAGES}
-	fi
-
 	v "Saving config files..."
 	[ "$VERBOSE" -gt 1 ] && TAR_V="v" || TAR_V=""
-	tar c${TAR_V}zf "$conf_tar" -T "$CONFFILES" 2>/dev/null
-	if [ "$?" -ne 0 ]; then
+	sed -i -e 's,^/,,' "$CONFFILES"
+	{
+		for service in /etc/init.d/*; do
+			if ! $service enabled; then
+				disabled="$disabled$service disable\n"
+			fi
+		done
+		disabled="$disabled\nexit 0"
+		tar_print_member "/etc/uci-defaults/10_disable_services" "$(echo -e $disabled)"
+
+		# Part of archive with installed packages info
+		if [ "$SAVE_INSTALLED_PKGS" -eq 1 ]; then
+			# Format: pkg-name<TAB>{rom,overlay,unknown}
+			# rom is used for pkgs in /rom, even if updated later
+			tar_print_member "$INSTALLED_PACKAGES" "$(find /usr/lib/opkg/info -name "*.control" \( \
+				\( -exec test -f /rom/{} \; -exec echo {} rom \; \) -o \
+				\( -exec test -f /overlay/upper/{} \; -exec echo {} overlay \; \) -o \
+				\( -exec echo {} unknown \; \) \
+				\) | sed -e 's,.*/,,;s/\.control /\t/')"
+		fi
+
+		# Rest of archive with config files and ending padding
+		tar c${TAR_V} -C / -T "$CONFFILES"
+	} | gzip > "$conf_tar"
+
+	local err=$?
+	if [ "$err" -ne 0 ]; then
 		echo "Failed to create the configuration backup."
 		rm -f "$conf_tar"
-		exit 1
 	fi
 
-	[ "$UMOUNT_ETCBACKUP_DIR" -eq 1 ] && {
-		umount "$ETCBACKUP_DIR"
-		rm -rf "$RAMFS"
-	}
 	rm -f "$CONFFILES"
+
+	return "$err"
 }
 
 if [ $CONF_BACKUP_LIST -eq 1 ]; then
@@ -280,8 +294,8 @@ if [ $CONF_BACKUP_LIST -eq 1 ]; then
 fi
 
 if [ -n "$CONF_BACKUP" ]; then
-	do_save_conffiles "$CONF_BACKUP"
-	exit $?
+	create_backup_archive "$CONF_BACKUP"
+	exit
 fi
 
 if [ -n "$CONF_RESTORE" ]; then
@@ -350,7 +364,7 @@ if [ -n "$CONF_IMAGE" ]; then
 	get_image "$CONF_IMAGE" "cat" > "$CONF_TAR"
 	export SAVE_CONFIG=1
 elif ask_bool $SAVE_CONFIG "Keep config files over reflash"; then
-	[ $TEST -eq 1 ] || do_save_conffiles "$CONF_TAR"
+	[ $TEST -eq 1 ] || create_backup_archive "$CONF_TAR" || exit
 	export SAVE_CONFIG=1
 else
 	[ $TEST -eq 1 ] || rm -f "$CONF_TAR"
@@ -364,8 +378,6 @@ fi
 install_bin /sbin/upgraded
 v "Commencing upgrade. Closing all shell sessions."
 
-COMMAND='/lib/upgrade/do_stage2'
-
 if [ -n "$FAILSAFE" ]; then
 	printf '%s\x00%s\x00%s' "$RAM_ROOT" "$IMAGE" "$COMMAND" >/tmp/sysupgrade
 	lock -u /tmp/.failsafe
diff --git a/package/boot/arm-trusted-firmware-mediatek/Makefile b/package/boot/arm-trusted-firmware-mediatek/Makefile
index 259a987e6bf94f..abdd6e7e4a3895 100644
--- a/package/boot/arm-trusted-firmware-mediatek/Makefile
+++ b/package/boot/arm-trusted-firmware-mediatek/Makefile
@@ -26,12 +26,14 @@ include $(INCLUDE_DIR)/package.mk
 define Trusted-Firmware-A/Default
   BUILD_TARGET:=mediatek
   TFA_IMAGE:=bl2.img bl31.bin
+  HIDDEN:=y
   BOOT_DEVICE:=
   DDR3_FLYBY:=
   DDR_TYPE:=
   NAND_TYPE:=
   BOARD_QFN:=
   DRAM_USE_COMB:=
+  USE_UBI:=
 endef
 
 define Trusted-Firmware-A/mt7622-nor-1ddr
@@ -56,6 +58,14 @@ define Trusted-Firmware-A/mt7622-snand-1ddr
   BOOT_DEVICE:=snand
 endef
 
+define Trusted-Firmware-A/mt7622-snand-ubi-1ddr
+  NAME:=MediaTek MT7622 (SPI-NAND using UBI, 1x DDR3)
+  BUILD_SUBTARGET:=mt7622
+  PLAT:=mt7622
+  BOOT_DEVICE:=snand
+  USE_UBI:=1
+endef
+
 define Trusted-Firmware-A/mt7622-snand-2ddr
   NAME:=MediaTek MT7622 (SPI-NAND, 2x DDR3)
   BUILD_SUBTARGET:=mt7622
@@ -64,6 +74,15 @@ define Trusted-Firmware-A/mt7622-snand-2ddr
   DDR3_FLYBY:=1
 endef
 
+define Trusted-Firmware-A/mt7622-snand-ubi-2ddr
+  NAME:=MediaTek MT7622 (SPI-NAND using UBI, 2x DDR3)
+  BUILD_SUBTARGET:=mt7622
+  PLAT:=mt7622
+  BOOT_DEVICE:=snand
+  DDR3_FLYBY:=1
+  USE_UBI:=1
+endef
+
 define Trusted-Firmware-A/mt7622-emmc-1ddr
   NAME:=MediaTek MT7622 (eMMC, 1x DDR3)
   BUILD_SUBTARGET:=mt7622
@@ -191,6 +210,16 @@ define Trusted-Firmware-A/mt7986-spim-nand-ddr4
   NAND_TYPE:=spim:2k+64
 endef
 
+define Trusted-Firmware-A/mt7986-spim-nand-ubi-ddr4
+  NAME:=MediaTek MT7986 (SPI-NAND via SPIM using UBI, DDR4)
+  BOOT_DEVICE:=spim-nand
+  BUILD_SUBTARGET:=filogic
+  PLAT:=mt7986
+  DDR_TYPE:=ddr4
+  NAND_TYPE:=spim:2k+64
+  USE_UBI:=1
+endef
+
 define Trusted-Firmware-A/mt7986-spim-nand-4k-ddr4
   NAME:=MediaTek MT7986 (SPI-NAND via SPIM, DDR4)
   BOOT_DEVICE:=spim-nand
@@ -352,6 +381,15 @@ define Trusted-Firmware-A/mt7988-snand-comb
   DRAM_USE_COMB:=1
 endef
 
+define Trusted-Firmware-A/mt7988-snand-ubi-comb
+  NAME:=MediaTek MT7988 (SPI-NAND via SNFI, UBI)
+  BOOT_DEVICE:=snand
+  BUILD_SUBTARGET:=filogic
+  PLAT:=mt7988
+  DRAM_USE_COMB:=1
+  USE_UBI:=1
+endef
+
 define Trusted-Firmware-A/mt7988-spim-nand-comb
   NAME:=MediaTek MT7988 (SPI-NAND via SPIM)
   BOOT_DEVICE:=spim-nand
@@ -360,11 +398,22 @@ define Trusted-Firmware-A/mt7988-spim-nand-comb
   DRAM_USE_COMB:=1
 endef
 
+define Trusted-Firmware-A/mt7988-spim-nand-ubi-comb
+  NAME:=MediaTek MT7988 (SPI-NAND via SPIM, UBI)
+  BOOT_DEVICE:=spim-nand
+  BUILD_SUBTARGET:=filogic
+  PLAT:=mt7988
+  DRAM_USE_COMB:=1
+  USE_UBI:=1
+endef
+
 TFA_TARGETS:= \
 	mt7622-nor-1ddr \
 	mt7622-nor-2ddr \
 	mt7622-snand-1ddr \
+	mt7622-snand-ubi-1ddr \
 	mt7622-snand-2ddr \
+	mt7622-snand-ubi-2ddr \
 	mt7622-emmc-1ddr \
 	mt7622-emmc-2ddr \
 	mt7622-sdmmc-1ddr \
@@ -386,6 +435,7 @@ TFA_TARGETS:= \
 	mt7986-sdmmc-ddr4 \
 	mt7986-snand-ddr4 \
 	mt7986-spim-nand-ddr4 \
+	mt7986-spim-nand-ubi-ddr4 \
 	mt7986-spim-nand-4k-ddr4 \
 	mt7988-emmc-ddr3 \
 	mt7988-nor-ddr3 \
@@ -401,7 +451,9 @@ TFA_TARGETS:= \
 	mt7988-nor-comb \
 	mt7988-sdmmc-comb \
 	mt7988-snand-comb \
-	mt7988-spim-nand-comb
+	mt7988-snand-ubi-comb \
+	mt7988-spim-nand-comb \
+	mt7988-spim-nand-ubi-comb
 
 TFA_MAKE_FLAGS += \
 	BOOT_DEVICE=$(BOOT_DEVICE) \
@@ -412,6 +464,7 @@ TFA_MAKE_FLAGS += \
 	HAVE_DRAM_OBJ_FILE=yes \
 	$(if $(DDR3_FLYBY),DDR3_FLYBY=1) \
 	$(if $(DRAM_USE_COMB),DRAM_USE_COMB=1) \
+	$(if $(USE_UBI),UBI=1 $(if $(findstring mt7622,$(PLAT)),OVERRIDE_UBI_START_ADDR=0x80000)) \
 	all
 
 define Package/trusted-firmware-a/install
diff --git a/package/boot/kexec-tools/Makefile b/package/boot/kexec-tools/Makefile
index 7f06ec7d642f9f..702ae009030091 100644
--- a/package/boot/kexec-tools/Makefile
+++ b/package/boot/kexec-tools/Makefile
@@ -8,12 +8,12 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=kexec-tools
-PKG_VERSION:=2.0.26
+PKG_VERSION:=2.0.28
 PKG_RELEASE:=1
 
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
 PKG_SOURCE_URL:=@KERNEL/linux/utils/kernel/kexec
-PKG_HASH:=7fe36a064101cd5c515e41b2be393dce3ca88adce59d6ee668e0af7c0c4570cd
+PKG_HASH:=d2f0ef872f39e2fe4b1b01feb62b0001383207239b9f8041f98a95564161d053
 
 PKG_CONFIG_DEPENDS := CONFIG_KEXEC_ZLIB CONFIG_KEXEC_LZMA
 
diff --git a/package/boot/opensbi/Makefile b/package/boot/opensbi/Makefile
index 01348e50aad4a8..6bb33ad2aa02ac 100644
--- a/package/boot/opensbi/Makefile
+++ b/package/boot/opensbi/Makefile
@@ -29,7 +29,7 @@ include $(INCLUDE_DIR)/package.mk
 define Package/opensbi
     SECTION:=boot
     CATEGORY:=Boot Loaders
-    DEPENDS:=@TARGET_sifiveu
+    DEPENDS:=@(TARGET_sifiveu||TARGET_d1)
     URL:=https://github.com/riscv/opensbi/blob/master/README.md
     VARIANT:=$(subst _,/,$(subst opensbi_,,$(1)))
     TITLE:=OpenSBI generic
diff --git a/package/boot/rkbin/Makefile b/package/boot/rkbin/Makefile
index affdd7b4e19206..bb116bdcd2b8de 100644
--- a/package/boot/rkbin/Makefile
+++ b/package/boot/rkbin/Makefile
@@ -25,6 +25,12 @@ define Trusted-Firmware-A/Default
   BUILD_TARGET:=rockchip
 endef
 
+define Trusted-Firmware-A/rk3566
+  BUILD_SUBTARGET:=armv8
+  ATF:=rk35/rk3568_bl31_v1.43.elf
+  TPL:=rk35/rk3566_ddr_1056MHz_v1.18.bin
+endef
+
 define Trusted-Firmware-A/rk3568
   BUILD_SUBTARGET:=armv8
   ATF:=rk35/rk3568_bl31_v1.43.elf
@@ -32,6 +38,7 @@ define Trusted-Firmware-A/rk3568
 endef
 
 TFA_TARGETS:= \
+	rk3566 \
 	rk3568
 
 define Build/Compile
diff --git a/package/boot/uboot-d1/Makefile b/package/boot/uboot-d1/Makefile
new file mode 100644
index 00000000000000..610dc5b49856dc
--- /dev/null
+++ b/package/boot/uboot-d1/Makefile
@@ -0,0 +1,84 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Copyright (C) 2023 OpenWrt.org
+#
+
+include $(TOPDIR)/rules.mk
+include $(INCLUDE_DIR)/kernel.mk
+
+PKG_VERSION:=2023.01
+PKG_RELEASE:=1
+
+PKG_HASH:=69423bad380f89a0916636e89e6dcbd2e4512d584308d922d1039d1e4331950f
+
+include $(INCLUDE_DIR)/u-boot.mk
+include $(INCLUDE_DIR)/package.mk
+
+include $(INCLUDE_DIR)/u-boot.mk
+include $(INCLUDE_DIR)/package.mk
+
+define U-Boot/Default
+  BUILD_TARGET:=d1
+  UBOOT_IMAGE:=u-boot-sunxi-with-spl.bin
+  UENV:=default
+  DTS_DIR:=arch/riscv/dts
+endef
+
+define U-Boot/dongshan_nezha_stu
+  NAME:=Dongshan Nezha STU
+  OPENSBI:=generic
+  DEPENDS:=+opensbi_generic
+  UBOOT_DTS:=sun20i-d1-dongshan-nezha-stu.dtb
+  BUILD_DEVICES:=dongshan_nezha_stu
+endef
+
+define U-Boot/lichee_rv_dock
+  NAME:=LicheePi RV (dock)
+  OPENSBI:=generic
+  DEPENDS:=+opensbi_generic
+  UBOOT_DTS:=sun20i-d1-lichee-rv-dock.dtb
+  BUILD_DEVICES:=lichee_rv_dock
+endef
+
+define U-Boot/mangopi_mq_pro
+  NAME:=MangoPi MQ Pro
+  OPENSBI:=generic
+  DEPENDS:=+opensbi_generic
+  UBOOT_DTS:=sun20i-d1-mangopi-mq-pro.dtb
+  BUILD_DEVICES:=mangopi_mq_pro
+endef
+
+define U-Boot/nezha
+  NAME:=Nezha D1
+  OPENSBI:=generic
+  DEPENDS:=+opensbi_generic
+  UBOOT_DTS:=sun20i-d1-nezha.dtb
+  BUILD_DEVICES:=nezha
+endef
+
+UBOOT_TARGETS := \
+	dongshan_nezha_stu \
+	lichee_rv_dock \
+	mangopi_mq_pro \
+	nezha \
+
+UBOOT_MAKE_FLAGS += \
+	OPENSBI=$(STAGING_DIR_IMAGE)/fw_dynamic-${OPENSBI}.bin
+
+define Build/Configure
+	$(call Build/Configure/U-Boot)
+	sed -i 's/CONFIG_TOOLS_LIBCRYPTO=y/# CONFIG_TOOLS_LIBCRYPTO is not set/' $(PKG_BUILD_DIR)/.config
+endef
+
+define Build/InstallDev
+	$(INSTALL_DIR) $(STAGING_DIR_IMAGE)
+	$(INSTALL_BIN) $(PKG_BUILD_DIR)/$(DTS_DIR)/$(UBOOT_DTS) $(STAGING_DIR_IMAGE)/$(UBOOT_DTS)
+	$(INSTALL_BIN) $(PKG_BUILD_DIR)/$(UBOOT_IMAGE) $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-$(UBOOT_IMAGE)
+	mkimage -C none -A riscv -T script -d uEnv-$(UENV).txt \
+		$(STAGING_DIR_IMAGE)/$(BUILD_DEVICES)-boot.scr
+endef
+
+define Package/u-boot/install/default
+endef
+
+$(eval $(call BuildPackage/U-Boot))
diff --git a/package/boot/uboot-d1/patches/0001-ARM-dts-sun8i-A33-Add-iNet-U70B-REV01.patch b/package/boot/uboot-d1/patches/0001-ARM-dts-sun8i-A33-Add-iNet-U70B-REV01.patch
new file mode 100644
index 00000000000000..1dc6468c4b4e1b
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0001-ARM-dts-sun8i-A33-Add-iNet-U70B-REV01.patch
@@ -0,0 +1,197 @@
+From d45e64aad18e5e324425b9efbe6a0ec9e1a343da Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 20 Nov 2021 13:19:13 -0600
+Subject: [PATCH 01/90] ARM: dts: sun8i: A33: Add iNet U70B REV01
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm/dts/Makefile                     |   1 +
+ arch/arm/dts/sun8i-a33-inet-u70b-rev1.dts | 172 ++++++++++++++++++++++
+ 2 files changed, 173 insertions(+)
+ create mode 100644 arch/arm/dts/sun8i-a33-inet-u70b-rev1.dts
+
+--- a/arch/arm/dts/Makefile
++++ b/arch/arm/dts/Makefile
+@@ -644,6 +644,7 @@ dtb-$(CONFIG_MACH_SUN8I_A33) += \
+ 	sun8i-a33-et-q8-v1.6.dtb \
+ 	sun8i-a33-ga10h-v1.1.dtb \
+ 	sun8i-a33-inet-d978-rev2.dtb \
++	sun8i-a33-inet-u70b-rev1.dtb \
+ 	sun8i-a33-ippo-q8h-v1.2.dtb \
+ 	sun8i-a33-olinuxino.dtb \
+ 	sun8i-a33-q8-tablet.dtb \
+--- /dev/null
++++ b/arch/arm/dts/sun8i-a33-inet-u70b-rev1.dts
+@@ -0,0 +1,172 @@
++// SPDX-License-Identifier: (GPL-2.0+ or MIT)
++
++/dts-v1/;
++
++#include "sun8i-a33.dtsi"
++#include "sun8i-reference-design-tablet.dtsi"
++
++/ {
++	model = "iNet U70B REV01";
++	compatible = "inet-tek,inet-u70b-rev01", "allwinner,sun8i-a33";
++
++	aliases {
++		ethernet0 = &rtl8723cs;
++	};
++
++	panel: panel {
++		compatible = "panel-dpi";
++		backlight = <&backlight>;
++		enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
++		power-supply = <&reg_dc1sw>;
++
++		panel-timing {
++			clock-frequency = <51000000>;
++			hactive = <1024>;
++			vactive = <600>;
++			hfront-porch = <162>;
++			hback-porch = <158>;
++			hsync-len = <20>;
++			vback-porch = <25>;
++			vfront-porch = <10>;
++			vsync-len = <3>;
++			hsync-active = <1>;
++			vsync-active = <1>;
++		};
++
++		port {
++			panel_in_tcon0: endpoint {
++				remote-endpoint = <&tcon0_out_panel>;
++			};
++		};
++	};
++
++	speaker_amp: audio-amplifier {
++		compatible = "simple-audio-amplifier";
++		enable-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */
++		sound-name-prefix = "Speaker Amp";
++	};
++
++	wifi_pwrseq: wifi-pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL6 */
++		post-power-on-delay-ms = <200>;
++	};
++};
++
++&codec {
++	status = "okay";
++};
++
++&dai {
++	status = "okay";
++};
++
++&de {
++	status = "okay";
++};
++
++&i2c1 {
++	clock-frequency = <400000>;
++
++	accelerometer@18 {
++		compatible = "bosch,bma250";
++		reg = <0x18>;
++		interrupt-parent = <&pio>;
++		interrupts = <7 10 IRQ_TYPE_EDGE_RISING>; /* PH10 / EINT10 */
++	};
++};
++
++&mmc1 {
++	pinctrl-0 = <&mmc1_pg_pins>;
++	pinctrl-names = "default";
++	bus-width = <4>;
++	non-removable;
++	vmmc-supply = <&reg_dldo1>;
++	vqmmc-supply = <&reg_dldo2>;
++	status = "okay";
++
++	rtl8723cs: wifi@1 {
++		reg = <1>;
++		interrupt-parent = <&r_pio>;
++		interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */
++	};
++};
++
++&nfc {
++	status = "okay";
++
++	nand@0 {
++		reg = <0>;
++		allwinner,rb = <0>;
++		nand-ecc-maximize;
++	};
++};
++
++&r_uart {
++	status = "disabled";
++};
++
++&reg_dldo2 {
++	regulator-min-microvolt = <3300000>;
++	regulator-max-microvolt = <3300000>;
++	regulator-name = "vcc-wifi-io";
++};
++
++&simplefb_lcd {
++	status = "okay";
++};
++
++&sound {
++	simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>;
++	simple-audio-card,widgets = "Headphone", "Headphone Jack",
++				    "Microphone", "Internal Microphone",
++				    "Speaker", "Internal Speaker";
++	simple-audio-card,routing = "Headphone Jack", "HP",
++				    "Internal Speaker", "Speaker Amp OUTL",
++				    "Internal Speaker", "Speaker Amp OUTR",
++				    "Speaker Amp INL", "HP", /* PHONEOUT ??? */
++				    "Speaker Amp INR", "HP", /* PHONEOUT ??? */
++				    "Left DAC", "DACL",
++				    "Right DAC", "DACR",
++				    "ADCL", "Left ADC",
++				    "ADCR", "Right ADC",
++				    "MIC1", "Internal Microphone",
++				    "MIC2", "Headset Microphone",
++				    "Headset Microphone", "HBIAS",
++				    "Internal Microphone", "MBIAS";
++	status = "okay";
++};
++
++&tcon0 {
++	pinctrl-0 = <&lcd_rgb666_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
++&tcon0_out {
++	tcon0_out_panel: endpoint {
++		remote-endpoint = <&panel_in_tcon0>;
++	};
++};
++
++&touchscreen {
++	reg = <0x40>;
++	compatible = "silead,gsl1680";
++	avdd-supply = <&reg_ldo_io1>;
++	touchscreen-size-x = <1024>;
++	touchscreen-size-y = <600>;
++	status = "okay";
++};
++
++&uart1 {
++	pinctrl-0 = <&uart1_pg_pins>, <&uart1_cts_rts_pg_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++
++	bluetooth {
++		compatible = "realtek,rtl8723cs-bt";
++		device-wake-gpios = <&r_pio 0 10 GPIO_ACTIVE_LOW>; /* PL10 */
++		enable-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
++		host-wake-gpios = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */
++	};
++};
diff --git a/package/boot/uboot-d1/patches/0002-sunxi-Add-iNet_U70B_rev1_defconfig.patch b/package/boot/uboot-d1/patches/0002-sunxi-Add-iNet_U70B_rev1_defconfig.patch
new file mode 100644
index 00000000000000..40f649b7fe25da
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0002-sunxi-Add-iNet_U70B_rev1_defconfig.patch
@@ -0,0 +1,46 @@
+From ddb1f06d1c7758c538e286c0c7a9c8545d2af6b1 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 20 Nov 2021 13:26:36 -0600
+Subject: [PATCH 02/90] sunxi: Add iNet_U70B_rev1_defconfig
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ configs/iNet_U70B_rev1_defconfig | 32 ++++++++++++++++++++++++++++++++
+ 1 file changed, 32 insertions(+)
+ create mode 100644 configs/iNet_U70B_rev1_defconfig
+
+--- /dev/null
++++ b/configs/iNet_U70B_rev1_defconfig
+@@ -0,0 +1,32 @@
++CONFIG_ARM=y
++CONFIG_ARCH_SUNXI=y
++CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-inet-u70b-rev1"
++# CONFIG_SPL_SERIAL is not set
++CONFIG_SPL=y
++CONFIG_MACH_SUN8I_A33=y
++CONFIG_DRAM_CLK=480
++CONFIG_DRAM_ZQ=31675
++CONFIG_DRAM_ODT_EN=y
++CONFIG_MMC0_CD_PIN="PB4"
++CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:51000,le:158,ri:162,up:25,lo:10,hs:20,vs:3,sync:3,vmode:0"
++CONFIG_VIDEO_LCD_DCLK_PHASE=0
++CONFIG_VIDEO_LCD_POWER="PH7"
++CONFIG_VIDEO_LCD_BL_EN="PH6"
++CONFIG_VIDEO_LCD_BL_PWM="PH0"
++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
++CONFIG_CMD_BIND=y
++CONFIG_CMD_CLK=y
++CONFIG_CMD_PWM=y
++CONFIG_CMD_I2C=y
++CONFIG_CMD_WDT=y
++CONFIG_CMD_PMIC=y
++CONFIG_CMD_REGULATOR=y
++# CONFIG_NET is not set
++CONFIG_AXP_GPIO=y
++CONFIG_REGULATOR_AXP=y
++CONFIG_REGULATOR_AXP_USB_POWER=y
++CONFIG_AXP_DLDO1_VOLT=3300
++CONFIG_DM_PWM=y
++CONFIG_PWM_SUNXI=y
++# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
++CONFIG_USB_MUSB_HOST=y
diff --git a/package/boot/uboot-d1/patches/0003-Adapt-iNet-U70B-REV01-for-development-FEL-serial.patch b/package/boot/uboot-d1/patches/0003-Adapt-iNet-U70B-REV01-for-development-FEL-serial.patch
new file mode 100644
index 00000000000000..03f1ca11754645
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0003-Adapt-iNet-U70B-REV01-for-development-FEL-serial.patch
@@ -0,0 +1,85 @@
+From ef808412055d1ef6fe77ff130d3f5a9432fef2d7 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Tue, 3 May 2022 22:35:12 -0500
+Subject: [PATCH 03/90] Adapt iNet U70B REV01 for development (FEL + serial)
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm/dts/sun8i-a33-inet-u70b-rev1.dts | 11 +++++++++++
+ configs/iNet_U70B_rev1_defconfig          | 14 +++++---------
+ 2 files changed, 16 insertions(+), 9 deletions(-)
+
+--- a/arch/arm/dts/sun8i-a33-inet-u70b-rev1.dts
++++ b/arch/arm/dts/sun8i-a33-inet-u70b-rev1.dts
+@@ -11,6 +11,7 @@
+ 
+ 	aliases {
+ 		ethernet0 = &rtl8723cs;
++		serial0 = &uart0;
+ 	};
+ 
+ 	panel: panel {
+@@ -76,6 +77,10 @@
+ 	};
+ };
+ 
++&mmc0 {
++	status = "disabled";
++};
++
+ &mmc1 {
+ 	pinctrl-0 = <&mmc1_pg_pins>;
+ 	pinctrl-names = "default";
+@@ -158,6 +163,12 @@
+ 	status = "okay";
+ };
+ 
++&uart0 {
++	pinctrl-0 = <&uart0_pf_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
+ &uart1 {
+ 	pinctrl-0 = <&uart1_pg_pins>, <&uart1_cts_rts_pg_pins>;
+ 	pinctrl-names = "default";
+--- a/configs/iNet_U70B_rev1_defconfig
++++ b/configs/iNet_U70B_rev1_defconfig
+@@ -1,12 +1,12 @@
+ CONFIG_ARM=y
+ CONFIG_ARCH_SUNXI=y
+ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-inet-u70b-rev1"
+-# CONFIG_SPL_SERIAL is not set
+ CONFIG_SPL=y
+ CONFIG_MACH_SUN8I_A33=y
+ CONFIG_DRAM_CLK=480
+ CONFIG_DRAM_ZQ=31675
+ CONFIG_DRAM_ODT_EN=y
++CONFIG_UART0_PORT_F=y
+ CONFIG_MMC0_CD_PIN="PB4"
+ CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:51000,le:158,ri:162,up:25,lo:10,hs:20,vs:3,sync:3,vmode:0"
+ CONFIG_VIDEO_LCD_DCLK_PHASE=0
+@@ -14,19 +14,15 @@ CONFIG_VIDEO_LCD_POWER="PH7"
+ CONFIG_VIDEO_LCD_BL_EN="PH6"
+ CONFIG_VIDEO_LCD_BL_PWM="PH0"
+ # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+-CONFIG_CMD_BIND=y
+-CONFIG_CMD_CLK=y
+-CONFIG_CMD_PWM=y
+-CONFIG_CMD_I2C=y
+-CONFIG_CMD_WDT=y
++CONFIG_PREBOOT="fastboot usb 0"
+ CONFIG_CMD_PMIC=y
+ CONFIG_CMD_REGULATOR=y
+-# CONFIG_NET is not set
+ CONFIG_AXP_GPIO=y
+ CONFIG_REGULATOR_AXP=y
+ CONFIG_REGULATOR_AXP_USB_POWER=y
+ CONFIG_AXP_DLDO1_VOLT=3300
+ CONFIG_DM_PWM=y
+ CONFIG_PWM_SUNXI=y
+-# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
+-CONFIG_USB_MUSB_HOST=y
++CONFIG_REMOTEPROC_SUN6I_AR100=y
++CONFIG_USB_MUSB_GADGET=y
++CONFIG_WATCHDOG_AUTOSTART=y
diff --git a/package/boot/uboot-d1/patches/0004-ARM-dts-sun6i-mixtile-loftq-Add-USB1-VBUS-regulator.patch b/package/boot/uboot-d1/patches/0004-ARM-dts-sun6i-mixtile-loftq-Add-USB1-VBUS-regulator.patch
new file mode 100644
index 00000000000000..b6685936ad44fb
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0004-ARM-dts-sun6i-mixtile-loftq-Add-USB1-VBUS-regulator.patch
@@ -0,0 +1,54 @@
+From 40a0ec0fdb6a110d69151de5480148772877f267 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Thu, 26 Aug 2021 20:39:33 -0500
+Subject: [PATCH 04/90] ARM: dts: sun6i: mixtile-loftq: Add USB1 VBUS regulator
+
+This board is configured with CONFIG_USB1_VBUS_PIN="PH24", but no
+regulator exists in its device tree. Add the regulator, so USB will
+continue to work when the PHY driver switches to using the regulator
+uclass instead of a GPIO.
+
+Update the device tree here because it does not exist in Linux.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm/dts/sun6i-a31-mixtile-loftq.dts | 17 +++++++++++++++++
+ 1 file changed, 17 insertions(+)
+
+--- a/arch/arm/dts/sun6i-a31-mixtile-loftq.dts
++++ b/arch/arm/dts/sun6i-a31-mixtile-loftq.dts
+@@ -6,6 +6,9 @@
+  */
+ 
+ /dts-v1/;
++
++#include <dt-bindings/gpio/gpio.h>
++
+ #include "sun6i-a31.dtsi"
+ 
+ / {
+@@ -19,6 +22,15 @@
+ 	chosen {
+ 		stdout-path = "serial0:115200n8";
+ 	};
++
++	reg_usb1_vbus: usb1-vbus {
++		compatible = "regulator-fixed";
++		regulator-name = "usb1-vbus";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		enable-active-high;
++		gpio = <&pio 7 24 GPIO_ACTIVE_HIGH>; /* PH24 */
++	};
+ };
+ 
+ &ehci0 {
+@@ -56,3 +68,8 @@
+ 	pinctrl-0 = <&uart0_ph_pins>;
+ 	status = "okay";
+ };
++
++&usbphy {
++	usb1_vbus-supply = <&reg_usb1_vbus>;
++	status = "okay";
++};
diff --git a/package/boot/uboot-d1/patches/0005-power-regulator-Add-a-driver-for-the-AXP-USB-power-s.patch b/package/boot/uboot-d1/patches/0005-power-regulator-Add-a-driver-for-the-AXP-USB-power-s.patch
new file mode 100644
index 00000000000000..62f81e3cd6137a
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0005-power-regulator-Add-a-driver-for-the-AXP-USB-power-s.patch
@@ -0,0 +1,97 @@
+From e07c1d516c1a7842510d22a7cf88666d500a9a9a Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 22 Aug 2021 21:35:45 -0500
+Subject: [PATCH 05/90] power: regulator: Add a driver for the AXP USB power
+ supply
+
+This driver reports the presence/absence of voltage on the PMIC's USB
+VBUS pin. This information is used by the USB PHY driver. The
+corresponding Linux driver uses the power supply class, which does not
+exist in U-Boot. UCLASS_REGULATOR seems to be the closest match.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/power/regulator/Kconfig         |  7 ++++
+ drivers/power/regulator/Makefile        |  1 +
+ drivers/power/regulator/axp_usb_power.c | 49 +++++++++++++++++++++++++
+ 3 files changed, 57 insertions(+)
+ create mode 100644 drivers/power/regulator/axp_usb_power.c
+
+--- a/drivers/power/regulator/Kconfig
++++ b/drivers/power/regulator/Kconfig
+@@ -43,6 +43,13 @@ config REGULATOR_AS3722
+ 	  but does not yet support change voltages. Currently this must be
+ 	  done using direct register writes to the PMIC.
+ 
++config REGULATOR_AXP_USB_POWER
++	bool "Enable driver for X-Powers AXP PMIC USB power supply"
++	depends on DM_REGULATOR && PMIC_AXP
++	help
++	  Enable support for reading the USB power supply status from
++	  X-Powers AXP2xx and AXP8xx PMICs.
++
+ config DM_REGULATOR_BD71837
+ 	bool "Enable Driver Model for ROHM BD71837/BD71847 regulators"
+ 	depends on DM_REGULATOR && DM_PMIC_BD71837
+--- a/drivers/power/regulator/Makefile
++++ b/drivers/power/regulator/Makefile
+@@ -7,6 +7,7 @@
+ obj-$(CONFIG_$(SPL_)DM_REGULATOR) += regulator-uclass.o
+ obj-$(CONFIG_REGULATOR_ACT8846) += act8846.o
+ obj-$(CONFIG_REGULATOR_AS3722)	+= as3722_regulator.o
++obj-$(CONFIG_$(SPL_)REGULATOR_AXP_USB_POWER) += axp_usb_power.o
+ obj-$(CONFIG_$(SPL_)DM_REGULATOR_DA9063) += da9063.o
+ obj-$(CONFIG_DM_REGULATOR_MAX77686) += max77686.o
+ obj-$(CONFIG_DM_REGULATOR_NPCM8XX) += npcm8xx_regulator.o
+--- /dev/null
++++ b/drivers/power/regulator/axp_usb_power.c
+@@ -0,0 +1,49 @@
++// SPDX-License-Identifier: GPL-2.0+
++
++#include <dm/device.h>
++#include <errno.h>
++#include <power/pmic.h>
++#include <power/regulator.h>
++
++#define AXP_POWER_STATUS		0x00
++#define AXP_POWER_STATUS_VBUS_PRESENT		BIT(5)
++
++static int axp_usb_power_get_enable(struct udevice *dev)
++{
++	int ret;
++
++	ret = pmic_reg_read(dev->parent, AXP_POWER_STATUS);
++	if (ret < 0)
++		return ret;
++
++	return !!(ret & AXP_POWER_STATUS_VBUS_PRESENT);
++}
++
++static const struct dm_regulator_ops axp_usb_power_ops = {
++	.get_enable		= axp_usb_power_get_enable,
++};
++
++static int axp_usb_power_probe(struct udevice *dev)
++{
++	struct dm_regulator_uclass_plat *uc_plat = dev_get_uclass_plat(dev);
++
++	uc_plat->type = REGULATOR_TYPE_FIXED;
++
++	return 0;
++}
++
++static const struct udevice_id axp_usb_power_ids[] = {
++	{ .compatible = "x-powers,axp202-usb-power-supply" },
++	{ .compatible = "x-powers,axp221-usb-power-supply" },
++	{ .compatible = "x-powers,axp223-usb-power-supply" },
++	{ .compatible = "x-powers,axp813-usb-power-supply" },
++	{ }
++};
++
++U_BOOT_DRIVER(axp_usb_power) = {
++	.name		= "axp_usb_power",
++	.id		= UCLASS_REGULATOR,
++	.of_match	= axp_usb_power_ids,
++	.probe		= axp_usb_power_probe,
++	.ops		= &axp_usb_power_ops,
++};
diff --git a/package/boot/uboot-d1/patches/0006-gpio-axp-sunxi-Remove-virtual-VBUS-detection-GPIO.patch b/package/boot/uboot-d1/patches/0006-gpio-axp-sunxi-Remove-virtual-VBUS-detection-GPIO.patch
new file mode 100644
index 00000000000000..e890583beae996
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0006-gpio-axp-sunxi-Remove-virtual-VBUS-detection-GPIO.patch
@@ -0,0 +1,122 @@
+From c750151e1107a8d46ca0f9bd30c1da276b142ec1 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Thu, 26 Aug 2021 18:02:54 -0500
+Subject: [PATCH 06/90] gpio: axp/sunxi: Remove virtual VBUS detection GPIO
+
+Now that this functionality is modeled using the device tree and
+regulator uclass, the named GPIO is not referenced anywhere. Remove it.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm/include/asm/arch-sunxi/gpio.h |  1 -
+ drivers/gpio/axp_gpio.c                | 21 ++++-----------------
+ drivers/gpio/sunxi_gpio.c              |  6 +-----
+ include/axp209.h                       |  1 -
+ include/axp221.h                       |  1 -
+ include/axp809.h                       |  1 -
+ include/axp818.h                       |  1 -
+ 7 files changed, 5 insertions(+), 27 deletions(-)
+
+--- a/arch/arm/include/asm/arch-sunxi/gpio.h
++++ b/arch/arm/include/asm/arch-sunxi/gpio.h
+@@ -209,7 +209,6 @@ enum sunxi_gpio_number {
+ 
+ /* Virtual AXP0 GPIOs */
+ #define SUNXI_GPIO_AXP0_PREFIX "AXP0-"
+-#define SUNXI_GPIO_AXP0_VBUS_DETECT	4
+ #define SUNXI_GPIO_AXP0_VBUS_ENABLE	5
+ #define SUNXI_GPIO_AXP0_GPIO_COUNT	6
+ 
+--- a/drivers/gpio/axp_gpio.c
++++ b/drivers/gpio/axp_gpio.c
+@@ -36,18 +36,11 @@ static int axp_gpio_direction_input(stru
+ {
+ 	u8 reg;
+ 
+-	switch (pin) {
+-#ifndef CONFIG_AXP152_POWER /* NA on axp152 */
+-	case SUNXI_GPIO_AXP0_VBUS_DETECT:
+-		return 0;
+-#endif
+-	default:
+-		reg = axp_get_gpio_ctrl_reg(pin);
+-		if (reg == 0)
+-			return -EINVAL;
++	reg = axp_get_gpio_ctrl_reg(pin);
++	if (reg == 0)
++		return -EINVAL;
+ 
+-		return pmic_bus_write(reg, AXP_GPIO_CTRL_INPUT);
+-	}
++	return pmic_bus_write(reg, AXP_GPIO_CTRL_INPUT);
+ }
+ 
+ static int axp_gpio_direction_output(struct udevice *dev, unsigned pin,
+@@ -83,12 +76,6 @@ static int axp_gpio_get_value(struct ude
+ 	int ret;
+ 
+ 	switch (pin) {
+-#ifndef CONFIG_AXP152_POWER /* NA on axp152 */
+-	case SUNXI_GPIO_AXP0_VBUS_DETECT:
+-		ret = pmic_bus_read(AXP_POWER_STATUS, &val);
+-		mask = AXP_POWER_STATUS_VBUS_PRESENT;
+-		break;
+-#endif
+ #ifdef AXP_MISC_CTRL_N_VBUSEN_FUNC
+ 	/* Only available on later PMICs */
+ 	case SUNXI_GPIO_AXP0_VBUS_ENABLE:
+--- a/drivers/gpio/sunxi_gpio.c
++++ b/drivers/gpio/sunxi_gpio.c
+@@ -117,11 +117,7 @@ int sunxi_name_to_gpio(const char *name)
+ #if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO
+ 	char lookup[8];
+ 
+-	if (strcasecmp(name, "AXP0-VBUS-DETECT") == 0) {
+-		sprintf(lookup, SUNXI_GPIO_AXP0_PREFIX "%d",
+-			SUNXI_GPIO_AXP0_VBUS_DETECT);
+-		name = lookup;
+-	} else if (strcasecmp(name, "AXP0-VBUS-ENABLE") == 0) {
++	if (strcasecmp(name, "AXP0-VBUS-ENABLE") == 0) {
+ 		sprintf(lookup, SUNXI_GPIO_AXP0_PREFIX "%d",
+ 			SUNXI_GPIO_AXP0_VBUS_ENABLE);
+ 		name = lookup;
+--- a/include/axp209.h
++++ b/include/axp209.h
+@@ -77,7 +77,6 @@ enum axp209_reg {
+ #ifdef CONFIG_AXP209_POWER
+ #define AXP_POWER_STATUS		0x00
+ #define AXP_POWER_STATUS_ALDO_IN		BIT(0)
+-#define AXP_POWER_STATUS_VBUS_PRESENT		BIT(5)
+ #define AXP_GPIO0_CTRL			0x90
+ #define AXP_GPIO1_CTRL			0x92
+ #define AXP_GPIO2_CTRL			0x93
+--- a/include/axp221.h
++++ b/include/axp221.h
+@@ -53,7 +53,6 @@
+ #ifdef CONFIG_AXP221_POWER
+ #define AXP_POWER_STATUS		0x00
+ #define AXP_POWER_STATUS_ALDO_IN		BIT(0)
+-#define AXP_POWER_STATUS_VBUS_PRESENT		BIT(5)
+ #define AXP_VBUS_IPSOUT			0x30
+ #define AXP_VBUS_IPSOUT_DRIVEBUS		(1 << 2)
+ #define AXP_MISC_CTRL			0x8f
+--- a/include/axp809.h
++++ b/include/axp809.h
+@@ -47,7 +47,6 @@
+ #ifdef CONFIG_AXP809_POWER
+ #define AXP_POWER_STATUS		0x00
+ #define AXP_POWER_STATUS_ALDO_IN		BIT(0)
+-#define AXP_POWER_STATUS_VBUS_PRESENT		BIT(5)
+ #define AXP_VBUS_IPSOUT			0x30
+ #define AXP_VBUS_IPSOUT_DRIVEBUS		(1 << 2)
+ #define AXP_MISC_CTRL			0x8f
+--- a/include/axp818.h
++++ b/include/axp818.h
+@@ -61,7 +61,6 @@
+ #ifdef CONFIG_AXP818_POWER
+ #define AXP_POWER_STATUS		0x00
+ #define AXP_POWER_STATUS_ALDO_IN		BIT(0)
+-#define AXP_POWER_STATUS_VBUS_PRESENT		BIT(5)
+ #define AXP_VBUS_IPSOUT			0x30
+ #define AXP_VBUS_IPSOUT_DRIVEBUS		(1 << 2)
+ #define AXP_MISC_CTRL			0x8f
diff --git a/package/boot/uboot-d1/patches/0007-power-regulator-Add-a-driver-for-the-AXP-PMIC-drivev.patch b/package/boot/uboot-d1/patches/0007-power-regulator-Add-a-driver-for-the-AXP-PMIC-drivev.patch
new file mode 100644
index 00000000000000..35b4597f9851c7
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0007-power-regulator-Add-a-driver-for-the-AXP-PMIC-drivev.patch
@@ -0,0 +1,111 @@
+From 25434a394705d2de92c50981e31347db4074204a Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Thu, 26 Aug 2021 21:32:15 -0500
+Subject: [PATCH 07/90] power: regulator: Add a driver for the AXP PMIC
+ drivevbus
+
+The first AXP regulator converted to use the regulator uclass is the
+drivevbus switch, since it is used by the USB PHY driver.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/power/regulator/Kconfig         | 14 ++++++
+ drivers/power/regulator/Makefile        |  1 +
+ drivers/power/regulator/axp_regulator.c | 58 +++++++++++++++++++++++++
+ 3 files changed, 73 insertions(+)
+ create mode 100644 drivers/power/regulator/axp_regulator.c
+
+--- a/drivers/power/regulator/Kconfig
++++ b/drivers/power/regulator/Kconfig
+@@ -43,6 +43,20 @@ config REGULATOR_AS3722
+ 	  but does not yet support change voltages. Currently this must be
+ 	  done using direct register writes to the PMIC.
+ 
++config REGULATOR_AXP
++	bool "Enable driver for X-Powers AXP PMIC regulators"
++	depends on DM_REGULATOR && PMIC_AXP
++	help
++	  Enable support for the regulators (DCDCs, LDOs) in the
++	  X-Powers AXP152, AXP2xx, and AXP8xx PMICs.
++
++config SPL_REGULATOR_AXP
++	bool "Enable driver for X-Powers AXP PMIC regulators in SPL"
++	depends on SPL_DM_REGULATOR && SPL_PMIC_AXP
++	help
++	  Enable support in SPL for the regulators (DCDCs, LDOs) in the
++	  X-Powers AXP152, AXP2xx, and AXP8xx PMICs.
++
+ config REGULATOR_AXP_USB_POWER
+ 	bool "Enable driver for X-Powers AXP PMIC USB power supply"
+ 	depends on DM_REGULATOR && PMIC_AXP
+--- a/drivers/power/regulator/Makefile
++++ b/drivers/power/regulator/Makefile
+@@ -7,6 +7,7 @@
+ obj-$(CONFIG_$(SPL_)DM_REGULATOR) += regulator-uclass.o
+ obj-$(CONFIG_REGULATOR_ACT8846) += act8846.o
+ obj-$(CONFIG_REGULATOR_AS3722)	+= as3722_regulator.o
++obj-$(CONFIG_$(SPL_)REGULATOR_AXP) += axp_regulator.o
+ obj-$(CONFIG_$(SPL_)REGULATOR_AXP_USB_POWER) += axp_usb_power.o
+ obj-$(CONFIG_$(SPL_)DM_REGULATOR_DA9063) += da9063.o
+ obj-$(CONFIG_DM_REGULATOR_MAX77686) += max77686.o
+--- /dev/null
++++ b/drivers/power/regulator/axp_regulator.c
+@@ -0,0 +1,58 @@
++// SPDX-License-Identifier: GPL-2.0+
++
++#include <dm.h>
++#include <errno.h>
++#include <power/pmic.h>
++#include <power/regulator.h>
++
++#define AXP_VBUS_IPSOUT			0x30
++#define AXP_VBUS_IPSOUT_DRIVEBUS		BIT(2)
++#define AXP_MISC_CTRL			0x8f
++#define AXP_MISC_CTRL_N_VBUSEN_FUNC		BIT(4)
++
++static int axp_drivevbus_get_enable(struct udevice *dev)
++{
++	int ret;
++
++	ret = pmic_reg_read(dev->parent, AXP_VBUS_IPSOUT);
++	if (ret < 0)
++		return ret;
++
++	return !!(ret & AXP_VBUS_IPSOUT_DRIVEBUS);
++}
++
++static int axp_drivevbus_set_enable(struct udevice *dev, bool enable)
++{
++	return pmic_clrsetbits(dev->parent, AXP_VBUS_IPSOUT,
++			       AXP_VBUS_IPSOUT_DRIVEBUS,
++			       enable ? AXP_VBUS_IPSOUT_DRIVEBUS : 0);
++}
++
++static const struct dm_regulator_ops axp_drivevbus_ops = {
++	.get_enable		= axp_drivevbus_get_enable,
++	.set_enable		= axp_drivevbus_set_enable,
++};
++
++static int axp_drivevbus_probe(struct udevice *dev)
++{
++	struct dm_regulator_uclass_plat *uc_plat = dev_get_uclass_plat(dev);
++	int ret;
++
++	uc_plat->type = REGULATOR_TYPE_FIXED;
++
++	if (dev_read_bool(dev->parent, "x-powers,drive-vbus-en")) {
++		ret = pmic_clrsetbits(dev->parent, AXP_MISC_CTRL,
++				      AXP_MISC_CTRL_N_VBUSEN_FUNC, 0);
++		if (ret)
++			return ret;
++	}
++
++	return 0;
++}
++
++U_BOOT_DRIVER(axp_drivevbus) = {
++	.name		= "axp_drivevbus",
++	.id		= UCLASS_REGULATOR,
++	.probe		= axp_drivevbus_probe,
++	.ops		= &axp_drivevbus_ops,
++};
diff --git a/package/boot/uboot-d1/patches/0008-power-pmic-axp-Probe-the-drivevbus-regulator-from-th.patch b/package/boot/uboot-d1/patches/0008-power-pmic-axp-Probe-the-drivevbus-regulator-from-th.patch
new file mode 100644
index 00000000000000..2e8ed790ded419
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0008-power-pmic-axp-Probe-the-drivevbus-regulator-from-th.patch
@@ -0,0 +1,41 @@
+From a588c97f146b67bae47099bc419cf10c02eca169 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Thu, 26 Aug 2021 21:34:33 -0500
+Subject: [PATCH 08/90] power: pmic: axp: Probe the drivevbus regulator from
+ the DT
+
+Now that some regulator driver exists for this PMIC, add support for
+probing regulator drivers from the device tree subnodes.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/power/pmic/axp.c | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+--- a/drivers/power/pmic/axp.c
++++ b/drivers/power/pmic/axp.c
+@@ -45,14 +45,24 @@ static struct dm_pmic_ops axp_pmic_ops =
+ 	.write		= dm_i2c_write,
+ };
+ 
++static const struct pmic_child_info axp_pmic_child_info[] = {
++	{ "drivevbus",	"axp_drivevbus"	},
++	{ }
++};
++
+ static int axp_pmic_bind(struct udevice *dev)
+ {
++	ofnode regulators_node;
+ 	int ret;
+ 
+ 	ret = dm_scan_fdt_dev(dev);
+ 	if (ret)
+ 		return ret;
+ 
++	regulators_node = dev_read_subnode(dev, "regulators");
++	if (ofnode_valid(regulators_node))
++		pmic_bind_children(dev, regulators_node, axp_pmic_child_info);
++
+ 	if (CONFIG_IS_ENABLED(SYSRESET)) {
+ 		ret = device_bind_driver_to_node(dev, "axp_sysreset", "axp_sysreset",
+ 						 dev_ofnode(dev), NULL);
diff --git a/package/boot/uboot-d1/patches/0009-phy-sun4i-usb-Control-USB-supplies-via-regulator-ucl.patch b/package/boot/uboot-d1/patches/0009-phy-sun4i-usb-Control-USB-supplies-via-regulator-ucl.patch
new file mode 100644
index 00000000000000..bbbfd58617429e
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0009-phy-sun4i-usb-Control-USB-supplies-via-regulator-ucl.patch
@@ -0,0 +1,162 @@
+From e8fb34342dfb79cd2059431dd1a0f03202a244ca Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Thu, 26 Aug 2021 22:11:37 -0500
+Subject: [PATCH 09/90] phy: sun4i-usb: Control USB supplies via regulator
+ uclass
+
+The device tree binding for the PHY provides VBUS supplies as regulator
+references. Now that all boards have the appropriate regulator uclass
+drivers enabled, the PHY driver can switch to using them. This replaces
+direct GPIO usage, which in some cases needed a special DM-incompatible
+"virtual" GPIO from the PMIC.
+
+The following boards provided a value for CONFIG_USB0_VBUS_PIN, but are
+missing the "usb0_vbus-supply" property in their device tree. None of
+them have the MUSB controller enabled in host or OTG mode, so they
+should see no impact:
+ - Ainol_AW1_defconfig / sun7i-a20-ainol-aw1
+ - Ampe_A76_defconfig / sun5i-a13-ampe-a76
+ - CHIP_pro_defconfig / sun5i-gr8-chip-pro
+ - Cubieboard4_defconfig / sun9i-a80-cubieboard4
+ - Merrii_A80_Optimus_defconfig / sun9i-a80-optimus
+ - Sunchip_CX-A99_defconfig / sun9i-a80-cx-a99
+ - Yones_Toptech_BD1078_defconfig / sun7i-a20-yones-toptech-bd1078
+ - Yones_Toptech_BS1078_V2_defconfig /
+   sun6i-a31s-yones-toptech-bs1078-v2
+ - iNet_3F_defconfig / sun4i-a10-inet-3f
+ - iNet_3W_defconfig / sun4i-a10-inet-3w
+ - iNet_86VS_defconfig / sun5i-a13-inet-86vs
+ - iNet_D978_rev2_defconfig / sun8i-a33-inet-d978-rev2
+ - icnova-a20-swac_defconfig / sun7i-a20-icnova-swac
+ - sun8i_a23_evb_defconfig / sun8i-a23-evb
+
+Similarly, the following boards set CONFIG_USB1_VBUS_PIN, but do not
+have "usb1_vbus-supply" in their device tree. Neither of them have USB
+enabled at all, so again there should be no impact:
+ - Cubieboard4_defconfig / sun9i-a80-cubieboard4 (also for USB3)
+ - sun8i_a23_evb_defconfig / sun8i-a23-evb
+
+The following boards use a different pin for USB1 VBUS between their
+defconfig and their device tree. Depending on which is correct, they
+may be broken:
+ - Linksprite_pcDuino3_Nano_defconfig (PH11) /
+   sun7i-a20-pcduino3-nano (PD2)
+ - icnova-a20-swac_defconfig (PG10) / sun7i-a20-icnova-swac (PH6)
+
+Finally, this board has conflicting pins given for its USB2 VBUS:
+ - Lamobo_R1_defconfig (PH3) / sun7i-a20-lamobo-r1 (PH12)
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/phy/allwinner/phy-sun4i-usb.c | 41 +++++++++++++--------------
+ 1 file changed, 19 insertions(+), 22 deletions(-)
+
+--- a/drivers/phy/allwinner/phy-sun4i-usb.c
++++ b/drivers/phy/allwinner/phy-sun4i-usb.c
+@@ -97,27 +97,22 @@ struct sun4i_usb_phy_cfg {
+ };
+ 
+ struct sun4i_usb_phy_info {
+-	const char *gpio_vbus;
+ 	const char *gpio_vbus_det;
+ 	const char *gpio_id_det;
+ } phy_info[] = {
+ 	{
+-		.gpio_vbus = CONFIG_USB0_VBUS_PIN,
+ 		.gpio_vbus_det = CONFIG_USB0_VBUS_DET,
+ 		.gpio_id_det = CONFIG_USB0_ID_DET,
+ 	},
+ 	{
+-		.gpio_vbus = CONFIG_USB1_VBUS_PIN,
+ 		.gpio_vbus_det = NULL,
+ 		.gpio_id_det = NULL,
+ 	},
+ 	{
+-		.gpio_vbus = CONFIG_USB2_VBUS_PIN,
+ 		.gpio_vbus_det = NULL,
+ 		.gpio_id_det = NULL,
+ 	},
+ 	{
+-		.gpio_vbus = CONFIG_USB3_VBUS_PIN,
+ 		.gpio_vbus_det = NULL,
+ 		.gpio_id_det = NULL,
+ 	},
+@@ -125,11 +120,11 @@ struct sun4i_usb_phy_info {
+ 
+ struct sun4i_usb_phy_plat {
+ 	void __iomem *pmu;
+-	struct gpio_desc gpio_vbus;
+ 	struct gpio_desc gpio_vbus_det;
+ 	struct gpio_desc gpio_id_det;
+ 	struct clk clocks;
+ 	struct reset_ctl resets;
++	struct udevice *vbus;
+ 	int id;
+ };
+ 
+@@ -218,14 +213,18 @@ static int sun4i_usb_phy_power_on(struct
+ {
+ 	struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
+ 	struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
++	int ret;
+ 
+ 	if (initial_usb_scan_delay) {
+ 		mdelay(initial_usb_scan_delay);
+ 		initial_usb_scan_delay = 0;
+ 	}
+ 
+-	if (dm_gpio_is_valid(&usb_phy->gpio_vbus))
+-		dm_gpio_set_value(&usb_phy->gpio_vbus, 1);
++	if (usb_phy->vbus) {
++		ret = regulator_set_enable(usb_phy->vbus, true);
++		if (ret && ret != -ENOSYS)
++			return ret;
++	}
+ 
+ 	return 0;
+ }
+@@ -234,9 +233,13 @@ static int sun4i_usb_phy_power_off(struc
+ {
+ 	struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
+ 	struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
++	int ret;
+ 
+-	if (dm_gpio_is_valid(&usb_phy->gpio_vbus))
+-		dm_gpio_set_value(&usb_phy->gpio_vbus, 0);
++	if (usb_phy->vbus) {
++		ret = regulator_set_enable(usb_phy->vbus, false);
++		if (ret && ret != -ENOSYS)
++			return ret;
++	}
+ 
+ 	return 0;
+ }
+@@ -450,22 +453,16 @@ static int sun4i_usb_phy_probe(struct ud
+ 	for (i = 0; i < data->cfg->num_phys; i++) {
+ 		struct sun4i_usb_phy_plat *phy = &plat[i];
+ 		struct sun4i_usb_phy_info *info = &phy_info[i];
+-		char name[16];
++		char name[20];
+ 
+ 		if (data->cfg->missing_phys & BIT(i))
+ 			continue;
+ 
+-		ret = dm_gpio_lookup_name(info->gpio_vbus, &phy->gpio_vbus);
+-		if (ret == 0) {
+-			ret = dm_gpio_request(&phy->gpio_vbus, "usb_vbus");
+-			if (ret)
+-				return ret;
+-			ret = dm_gpio_set_dir_flags(&phy->gpio_vbus,
+-						    GPIOD_IS_OUT);
+-			if (ret)
+-				return ret;
+-			ret = dm_gpio_set_value(&phy->gpio_vbus, 0);
+-			if (ret)
++		snprintf(name, sizeof(name), "usb%d_vbus-supply", i);
++		ret = device_get_supply_regulator(dev, name, &phy->vbus);
++		if (phy->vbus) {
++			ret = regulator_set_enable(phy->vbus, false);
++			if (ret && ret != -ENOSYS)
+ 				return ret;
+ 		}
+ 
diff --git a/package/boot/uboot-d1/patches/0010-sunxi-Remove-obsolete-USBx_VBUS_PIN-Kconfig-symbols.patch b/package/boot/uboot-d1/patches/0010-sunxi-Remove-obsolete-USBx_VBUS_PIN-Kconfig-symbols.patch
new file mode 100644
index 00000000000000..edeae405eaf0aa
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0010-sunxi-Remove-obsolete-USBx_VBUS_PIN-Kconfig-symbols.patch
@@ -0,0 +1,58 @@
+From 649bb7845e30805c66f62fc5725c4dbf350f21cb Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Thu, 26 Aug 2021 22:26:40 -0500
+Subject: [PATCH 10/90] sunxi: Remove obsolete USBx_VBUS_PIN Kconfig symbols
+
+Now that the USB PHY driver uses the device tree to get VBUS supply
+regulators, these Kconfig symbols are unused. Remove them.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm/mach-sunxi/Kconfig | 29 -----------------------------
+ 1 file changed, 29 deletions(-)
+
+--- a/arch/arm/mach-sunxi/Kconfig
++++ b/arch/arm/mach-sunxi/Kconfig
+@@ -693,13 +693,6 @@ config MMC_SUNXI_SLOT_EXTRA
+ 	slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
+ 	support for this.
+ 
+-config USB0_VBUS_PIN
+-	string "Vbus enable pin for usb0 (otg)"
+-	default ""
+-	---help---
+-	Set the Vbus enable pin for usb0 (otg). This takes a string in the
+-	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
+-
+ config USB0_VBUS_DET
+ 	string "Vbus detect pin for usb0 (otg)"
+ 	default ""
+@@ -714,28 +707,6 @@ config USB0_ID_DET
+ 	Set the ID detect pin for usb0 (otg). This takes a string in the
+ 	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
+ 
+-config USB1_VBUS_PIN
+-	string "Vbus enable pin for usb1 (ehci0)"
+-	default "PH6" if MACH_SUN4I || MACH_SUN7I
+-	default "PH27" if MACH_SUN6I
+-	---help---
+-	Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
+-	a string in the format understood by sunxi_name_to_gpio, e.g.
+-	PH1 for pin 1 of port H.
+-
+-config USB2_VBUS_PIN
+-	string "Vbus enable pin for usb2 (ehci1)"
+-	default "PH3" if MACH_SUN4I || MACH_SUN7I
+-	default "PH24" if MACH_SUN6I
+-	---help---
+-	See USB1_VBUS_PIN help text.
+-
+-config USB3_VBUS_PIN
+-	string "Vbus enable pin for usb3 (ehci2)"
+-	default ""
+-	---help---
+-	See USB1_VBUS_PIN help text.
+-
+ config I2C0_ENABLE
+ 	bool "Enable I2C/TWI controller 0"
+ 	default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
diff --git a/package/boot/uboot-d1/patches/0011-clk-sunxi-Add-support-for-the-D1-CCU.patch b/package/boot/uboot-d1/patches/0011-clk-sunxi-Add-support-for-the-D1-CCU.patch
new file mode 100644
index 00000000000000..faa7f64327ba26
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0011-clk-sunxi-Add-support-for-the-D1-CCU.patch
@@ -0,0 +1,393 @@
+From 73d6c82e34e89cfde880d1948b3e0dc714adead8 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 30 Apr 2022 22:34:19 -0500
+Subject: [PATCH 11/90] clk: sunxi: Add support for the D1 CCU
+
+Since the D1 CCU binding is defined, we can add support for its
+gates/resets, following the pattern of the existing drivers.
+
+Series-to: sunxi
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/clk/sunxi/Kconfig                 |   6 +
+ drivers/clk/sunxi/Makefile                |   1 +
+ drivers/clk/sunxi/clk_d1.c                |  82 ++++++++++++
+ drivers/clk/sunxi/clk_sunxi.c             |   5 +
+ include/dt-bindings/clock/sun20i-d1-ccu.h | 156 ++++++++++++++++++++++
+ include/dt-bindings/reset/sun20i-d1-ccu.h |  77 +++++++++++
+ 6 files changed, 327 insertions(+)
+ create mode 100644 drivers/clk/sunxi/clk_d1.c
+ create mode 100644 include/dt-bindings/clock/sun20i-d1-ccu.h
+ create mode 100644 include/dt-bindings/reset/sun20i-d1-ccu.h
+
+--- a/drivers/clk/sunxi/Kconfig
++++ b/drivers/clk/sunxi/Kconfig
+@@ -87,6 +87,12 @@ config CLK_SUN8I_H3
+ 	  This enables common clock driver support for platforms based
+ 	  on Allwinner H3/H5 SoC.
+ 
++config CLK_SUN20I_D1
++	bool "Clock driver for Allwinner D1"
++	help
++	  This enables common clock driver support for platforms based
++	  on Allwinner D1 SoC.
++
+ config CLK_SUN50I_H6
+ 	bool "Clock driver for Allwinner H6"
+ 	default MACH_SUN50I_H6
+--- a/drivers/clk/sunxi/Makefile
++++ b/drivers/clk/sunxi/Makefile
+@@ -19,6 +19,7 @@ obj-$(CONFIG_CLK_SUN8I_R40) += clk_r40.o
+ obj-$(CONFIG_CLK_SUN8I_V3S) += clk_v3s.o
+ obj-$(CONFIG_CLK_SUN9I_A80) += clk_a80.o
+ obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
++obj-$(CONFIG_CLK_SUN20I_D1) += clk_d1.o
+ obj-$(CONFIG_CLK_SUN50I_H6) += clk_h6.o
+ obj-$(CONFIG_CLK_SUN50I_H6_R) += clk_h6_r.o
+ obj-$(CONFIG_CLK_SUN50I_H616) += clk_h616.o
+--- /dev/null
++++ b/drivers/clk/sunxi/clk_d1.c
+@@ -0,0 +1,82 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
++ */
++
++#include <common.h>
++#include <clk-uclass.h>
++#include <dm.h>
++#include <errno.h>
++#include <clk/sunxi.h>
++#include <dt-bindings/clock/sun20i-d1-ccu.h>
++#include <dt-bindings/reset/sun20i-d1-ccu.h>
++#include <linux/bitops.h>
++
++static struct ccu_clk_gate d1_gates[] = {
++	[CLK_BUS_MMC0]		= GATE(0x84c, BIT(0)),
++	[CLK_BUS_MMC1]		= GATE(0x84c, BIT(1)),
++	[CLK_BUS_MMC2]		= GATE(0x84c, BIT(2)),
++	[CLK_BUS_UART0]		= GATE(0x90c, BIT(0)),
++	[CLK_BUS_UART1]		= GATE(0x90c, BIT(1)),
++	[CLK_BUS_UART2]		= GATE(0x90c, BIT(2)),
++	[CLK_BUS_UART3]		= GATE(0x90c, BIT(3)),
++	[CLK_BUS_UART4]		= GATE(0x90c, BIT(4)),
++	[CLK_BUS_UART5]		= GATE(0x90c, BIT(5)),
++	[CLK_BUS_I2C0]		= GATE(0x91c, BIT(0)),
++	[CLK_BUS_I2C1]		= GATE(0x91c, BIT(1)),
++	[CLK_BUS_I2C2]		= GATE(0x91c, BIT(2)),
++	[CLK_BUS_I2C3]		= GATE(0x91c, BIT(3)),
++	[CLK_SPI0]		= GATE(0x940, BIT(31)),
++	[CLK_SPI1]		= GATE(0x944, BIT(31)),
++	[CLK_BUS_SPI0]		= GATE(0x96c, BIT(0)),
++	[CLK_BUS_SPI1]		= GATE(0x96c, BIT(1)),
++
++	[CLK_BUS_EMAC]		= GATE(0x97c, BIT(0)),
++
++	[CLK_USB_OHCI0]		= GATE(0xa70, BIT(31)),
++	[CLK_USB_OHCI1]		= GATE(0xa74, BIT(31)),
++	[CLK_BUS_OHCI0]		= GATE(0xa8c, BIT(0)),
++	[CLK_BUS_OHCI1]		= GATE(0xa8c, BIT(1)),
++	[CLK_BUS_EHCI0]		= GATE(0xa8c, BIT(4)),
++	[CLK_BUS_EHCI1]		= GATE(0xa8c, BIT(5)),
++	[CLK_BUS_OTG]		= GATE(0xa8c, BIT(8)),
++	[CLK_BUS_LRADC]		= GATE(0xa9c, BIT(0)),
++
++	[CLK_RISCV]		= GATE(0xd04, BIT(31)),
++};
++
++static struct ccu_reset d1_resets[] = {
++	[RST_BUS_MMC0]		= RESET(0x84c, BIT(16)),
++	[RST_BUS_MMC1]		= RESET(0x84c, BIT(17)),
++	[RST_BUS_MMC2]		= RESET(0x84c, BIT(18)),
++	[RST_BUS_UART0]		= RESET(0x90c, BIT(16)),
++	[RST_BUS_UART1]		= RESET(0x90c, BIT(17)),
++	[RST_BUS_UART2]		= RESET(0x90c, BIT(18)),
++	[RST_BUS_UART3]		= RESET(0x90c, BIT(19)),
++	[RST_BUS_UART4]		= RESET(0x90c, BIT(20)),
++	[RST_BUS_UART5]		= RESET(0x90c, BIT(21)),
++	[RST_BUS_I2C0]		= RESET(0x91c, BIT(16)),
++	[RST_BUS_I2C1]		= RESET(0x91c, BIT(17)),
++	[RST_BUS_I2C2]		= RESET(0x91c, BIT(18)),
++	[RST_BUS_I2C3]		= RESET(0x91c, BIT(19)),
++	[RST_BUS_SPI0]		= RESET(0x96c, BIT(16)),
++	[RST_BUS_SPI1]		= RESET(0x96c, BIT(17)),
++
++	[RST_BUS_EMAC]		= RESET(0x97c, BIT(16)),
++
++	[RST_USB_PHY0]		= RESET(0xa70, BIT(30)),
++	[RST_USB_PHY1]		= RESET(0xa74, BIT(30)),
++	[RST_BUS_OHCI0]		= RESET(0xa8c, BIT(16)),
++	[RST_BUS_OHCI1]		= RESET(0xa8c, BIT(17)),
++	[RST_BUS_EHCI0]		= RESET(0xa8c, BIT(20)),
++	[RST_BUS_EHCI1]		= RESET(0xa8c, BIT(21)),
++	[RST_BUS_OTG]		= RESET(0xa8c, BIT(24)),
++	[RST_BUS_LRADC]		= RESET(0xa9c, BIT(16)),
++};
++
++const struct ccu_desc d1_ccu_desc = {
++	.gates	= d1_gates,
++	.resets	= d1_resets,
++	.num_gates = ARRAY_SIZE(d1_gates),
++	.num_resets = ARRAY_SIZE(d1_resets),
++};
+--- a/drivers/clk/sunxi/clk_sunxi.c
++++ b/drivers/clk/sunxi/clk_sunxi.c
+@@ -118,6 +118,7 @@ extern const struct ccu_desc a64_ccu_des
+ extern const struct ccu_desc a80_ccu_desc;
+ extern const struct ccu_desc a80_mmc_clk_desc;
+ extern const struct ccu_desc a83t_ccu_desc;
++extern const struct ccu_desc d1_ccu_desc;
+ extern const struct ccu_desc f1c100s_ccu_desc;
+ extern const struct ccu_desc h3_ccu_desc;
+ extern const struct ccu_desc h6_ccu_desc;
+@@ -183,6 +184,10 @@ static const struct udevice_id sunxi_clk
+ 	{ .compatible = "allwinner,sun9i-a80-mmc-config-clk",
+ 	  .data = (ulong)&a80_mmc_clk_desc },
+ #endif
++#ifdef CONFIG_CLK_SUN20I_D1
++	{ .compatible = "allwinner,sun20i-d1-ccu",
++	  .data = (ulong)&d1_ccu_desc },
++#endif
+ #ifdef CONFIG_CLK_SUN50I_A64
+ 	{ .compatible = "allwinner,sun50i-a64-ccu",
+ 	  .data = (ulong)&a64_ccu_desc },
+--- /dev/null
++++ b/include/dt-bindings/clock/sun20i-d1-ccu.h
+@@ -0,0 +1,156 @@
++/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
++/*
++ * Copyright (C) 2020 huangzhenwei@allwinnertech.com
++ * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
++ */
++
++#ifndef _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_
++#define _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_
++
++#define CLK_PLL_CPUX		0
++#define CLK_PLL_DDR0		1
++#define CLK_PLL_PERIPH0_4X	2
++#define CLK_PLL_PERIPH0_2X	3
++#define CLK_PLL_PERIPH0_800M	4
++#define CLK_PLL_PERIPH0		5
++#define CLK_PLL_PERIPH0_DIV3	6
++#define CLK_PLL_VIDEO0_4X	7
++#define CLK_PLL_VIDEO0_2X	8
++#define CLK_PLL_VIDEO0		9
++#define CLK_PLL_VIDEO1_4X	10
++#define CLK_PLL_VIDEO1_2X	11
++#define CLK_PLL_VIDEO1		12
++#define CLK_PLL_VE		13
++#define CLK_PLL_AUDIO0_4X	14
++#define CLK_PLL_AUDIO0_2X	15
++#define CLK_PLL_AUDIO0		16
++#define CLK_PLL_AUDIO1		17
++#define CLK_PLL_AUDIO1_DIV2	18
++#define CLK_PLL_AUDIO1_DIV5	19
++#define CLK_CPUX		20
++#define CLK_CPUX_AXI		21
++#define CLK_CPUX_APB		22
++#define CLK_PSI_AHB		23
++#define CLK_APB0		24
++#define CLK_APB1		25
++#define CLK_MBUS		26
++#define CLK_DE			27
++#define CLK_BUS_DE		28
++#define CLK_DI			29
++#define CLK_BUS_DI		30
++#define CLK_G2D			31
++#define CLK_BUS_G2D		32
++#define CLK_CE			33
++#define CLK_BUS_CE		34
++#define CLK_VE			35
++#define CLK_BUS_VE		36
++#define CLK_BUS_DMA		37
++#define CLK_BUS_MSGBOX0		38
++#define CLK_BUS_MSGBOX1		39
++#define CLK_BUS_MSGBOX2		40
++#define CLK_BUS_SPINLOCK	41
++#define CLK_BUS_HSTIMER		42
++#define CLK_AVS			43
++#define CLK_BUS_DBG		44
++#define CLK_BUS_PWM		45
++#define CLK_BUS_IOMMU		46
++#define CLK_DRAM		47
++#define CLK_MBUS_DMA		48
++#define CLK_MBUS_VE		49
++#define CLK_MBUS_CE		50
++#define CLK_MBUS_TVIN		51
++#define CLK_MBUS_CSI		52
++#define CLK_MBUS_G2D		53
++#define CLK_MBUS_RISCV		54
++#define CLK_BUS_DRAM		55
++#define CLK_MMC0		56
++#define CLK_MMC1		57
++#define CLK_MMC2		58
++#define CLK_BUS_MMC0		59
++#define CLK_BUS_MMC1		60
++#define CLK_BUS_MMC2		61
++#define CLK_BUS_UART0		62
++#define CLK_BUS_UART1		63
++#define CLK_BUS_UART2		64
++#define CLK_BUS_UART3		65
++#define CLK_BUS_UART4		66
++#define CLK_BUS_UART5		67
++#define CLK_BUS_I2C0		68
++#define CLK_BUS_I2C1		69
++#define CLK_BUS_I2C2		70
++#define CLK_BUS_I2C3		71
++#define CLK_SPI0		72
++#define CLK_SPI1		73
++#define CLK_BUS_SPI0		74
++#define CLK_BUS_SPI1		75
++#define CLK_EMAC_25M		76
++#define CLK_BUS_EMAC		77
++#define CLK_IR_TX		78
++#define CLK_BUS_IR_TX		79
++#define CLK_BUS_GPADC		80
++#define CLK_BUS_THS		81
++#define CLK_I2S0		82
++#define CLK_I2S1		83
++#define CLK_I2S2		84
++#define CLK_I2S2_ASRC		85
++#define CLK_BUS_I2S0		86
++#define CLK_BUS_I2S1		87
++#define CLK_BUS_I2S2		88
++#define CLK_SPDIF_TX		89
++#define CLK_SPDIF_RX		90
++#define CLK_BUS_SPDIF		91
++#define CLK_DMIC		92
++#define CLK_BUS_DMIC		93
++#define CLK_AUDIO_DAC		94
++#define CLK_AUDIO_ADC		95
++#define CLK_BUS_AUDIO		96
++#define CLK_USB_OHCI0		97
++#define CLK_USB_OHCI1		98
++#define CLK_BUS_OHCI0		99
++#define CLK_BUS_OHCI1		100
++#define CLK_BUS_EHCI0		101
++#define CLK_BUS_EHCI1		102
++#define CLK_BUS_OTG		103
++#define CLK_BUS_LRADC		104
++#define CLK_BUS_DPSS_TOP	105
++#define CLK_HDMI_24M		106
++#define CLK_HDMI_CEC_32K	107
++#define CLK_HDMI_CEC		108
++#define CLK_BUS_HDMI		109
++#define CLK_MIPI_DSI		110
++#define CLK_BUS_MIPI_DSI	111
++#define CLK_TCON_LCD0		112
++#define CLK_BUS_TCON_LCD0	113
++#define CLK_TCON_TV		114
++#define CLK_BUS_TCON_TV		115
++#define CLK_TVE			116
++#define CLK_BUS_TVE_TOP		117
++#define CLK_BUS_TVE		118
++#define CLK_TVD			119
++#define CLK_BUS_TVD_TOP		120
++#define CLK_BUS_TVD		121
++#define CLK_LEDC		122
++#define CLK_BUS_LEDC		123
++#define CLK_CSI_TOP		124
++#define CLK_CSI_MCLK		125
++#define CLK_BUS_CSI		126
++#define CLK_TPADC		127
++#define CLK_BUS_TPADC		128
++#define CLK_BUS_TZMA		129
++#define CLK_DSP			130
++#define CLK_BUS_DSP_CFG		131
++#define CLK_RISCV		132
++#define CLK_RISCV_AXI		133
++#define CLK_BUS_RISCV_CFG	134
++#define CLK_FANOUT_24M		135
++#define CLK_FANOUT_12M		136
++#define CLK_FANOUT_16M		137
++#define CLK_FANOUT_25M		138
++#define CLK_FANOUT_32K		139
++#define CLK_FANOUT_27M		140
++#define CLK_FANOUT_PCLK		141
++#define CLK_FANOUT0		142
++#define CLK_FANOUT1		143
++#define CLK_FANOUT2		144
++
++#endif /* _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_ */
+--- /dev/null
++++ b/include/dt-bindings/reset/sun20i-d1-ccu.h
+@@ -0,0 +1,77 @@
++/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
++/*
++ * Copyright (c) 2020 huangzhenwei@allwinnertech.com
++ * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
++ */
++
++#ifndef _DT_BINDINGS_RST_SUN20I_D1_CCU_H_
++#define _DT_BINDINGS_RST_SUN20I_D1_CCU_H_
++
++#define RST_MBUS		0
++#define RST_BUS_DE		1
++#define RST_BUS_DI		2
++#define RST_BUS_G2D		3
++#define RST_BUS_CE		4
++#define RST_BUS_VE		5
++#define RST_BUS_DMA		6
++#define RST_BUS_MSGBOX0		7
++#define RST_BUS_MSGBOX1		8
++#define RST_BUS_MSGBOX2		9
++#define RST_BUS_SPINLOCK	10
++#define RST_BUS_HSTIMER		11
++#define RST_BUS_DBG		12
++#define RST_BUS_PWM		13
++#define RST_BUS_DRAM		14
++#define RST_BUS_MMC0		15
++#define RST_BUS_MMC1		16
++#define RST_BUS_MMC2		17
++#define RST_BUS_UART0		18
++#define RST_BUS_UART1		19
++#define RST_BUS_UART2		20
++#define RST_BUS_UART3		21
++#define RST_BUS_UART4		22
++#define RST_BUS_UART5		23
++#define RST_BUS_I2C0		24
++#define RST_BUS_I2C1		25
++#define RST_BUS_I2C2		26
++#define RST_BUS_I2C3		27
++#define RST_BUS_SPI0		28
++#define RST_BUS_SPI1		29
++#define RST_BUS_EMAC		30
++#define RST_BUS_IR_TX		31
++#define RST_BUS_GPADC		32
++#define RST_BUS_THS		33
++#define RST_BUS_I2S0		34
++#define RST_BUS_I2S1		35
++#define RST_BUS_I2S2		36
++#define RST_BUS_SPDIF		37
++#define RST_BUS_DMIC		38
++#define RST_BUS_AUDIO		39
++#define RST_USB_PHY0		40
++#define RST_USB_PHY1		41
++#define RST_BUS_OHCI0		42
++#define RST_BUS_OHCI1		43
++#define RST_BUS_EHCI0		44
++#define RST_BUS_EHCI1		45
++#define RST_BUS_OTG		46
++#define RST_BUS_LRADC		47
++#define RST_BUS_DPSS_TOP	48
++#define RST_BUS_HDMI_SUB	49
++#define RST_BUS_HDMI_MAIN	50
++#define RST_BUS_MIPI_DSI	51
++#define RST_BUS_TCON_LCD0	52
++#define RST_BUS_TCON_TV		53
++#define RST_BUS_LVDS0		54
++#define RST_BUS_TVE		55
++#define RST_BUS_TVE_TOP		56
++#define RST_BUS_TVD		57
++#define RST_BUS_TVD_TOP		58
++#define RST_BUS_LEDC		59
++#define RST_BUS_CSI		60
++#define RST_BUS_TPADC		61
++#define RST_DSP			62
++#define RST_BUS_DSP_CFG		63
++#define RST_BUS_DSP_DBG		64
++#define RST_BUS_RISCV_CFG	65
++
++#endif /* _DT_BINDINGS_RST_SUN20I_D1_CCU_H_ */
diff --git a/package/boot/uboot-d1/patches/0012-gpio-axp-Remove-virtual-VBUS-enable-GPIO.patch b/package/boot/uboot-d1/patches/0012-gpio-axp-Remove-virtual-VBUS-enable-GPIO.patch
new file mode 100644
index 00000000000000..53f893c0ff7b73
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0012-gpio-axp-Remove-virtual-VBUS-enable-GPIO.patch
@@ -0,0 +1,227 @@
+From cbb281e0ec847b9de41970e470348b3534bb9a9f Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Thu, 26 Aug 2021 18:02:54 -0500
+Subject: [PATCH 12/90] gpio: axp: Remove virtual VBUS enable GPIO
+
+Now that this functionality is modeled using the device tree and
+regulator uclass, the named GPIO is not referenced anywhere. Remove
+it, along with the rest of the support for AXP virtual GPIOs.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm/include/asm/arch-sunxi/gpio.h |  8 ---
+ drivers/gpio/axp_gpio.c                | 75 ++++++++------------------
+ drivers/gpio/sunxi_gpio.c              |  8 ---
+ include/axp221.h                       |  4 --
+ include/axp809.h                       |  4 --
+ include/axp818.h                       |  4 --
+ 6 files changed, 21 insertions(+), 82 deletions(-)
+
+--- a/arch/arm/include/asm/arch-sunxi/gpio.h
++++ b/arch/arm/include/asm/arch-sunxi/gpio.h
+@@ -111,7 +111,6 @@ enum sunxi_gpio_number {
+ 	SUNXI_GPIO_L_START = 352,
+ 	SUNXI_GPIO_M_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_L),
+ 	SUNXI_GPIO_N_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_M),
+-	SUNXI_GPIO_AXP0_START = 1024,
+ };
+ 
+ /* SUNXI GPIO number definitions */
+@@ -128,8 +127,6 @@ enum sunxi_gpio_number {
+ #define SUNXI_GPM(_nr)	(SUNXI_GPIO_M_START + (_nr))
+ #define SUNXI_GPN(_nr)	(SUNXI_GPIO_N_START + (_nr))
+ 
+-#define SUNXI_GPAXP0(_nr)	(SUNXI_GPIO_AXP0_START + (_nr))
+-
+ /* GPIO pin function config */
+ #define SUNXI_GPIO_INPUT	0
+ #define SUNXI_GPIO_OUTPUT	1
+@@ -207,11 +204,6 @@ enum sunxi_gpio_number {
+ #define SUNXI_GPIO_PULL_UP	1
+ #define SUNXI_GPIO_PULL_DOWN	2
+ 
+-/* Virtual AXP0 GPIOs */
+-#define SUNXI_GPIO_AXP0_PREFIX "AXP0-"
+-#define SUNXI_GPIO_AXP0_VBUS_ENABLE	5
+-#define SUNXI_GPIO_AXP0_GPIO_COUNT	6
+-
+ struct sunxi_gpio_plat {
+ 	struct sunxi_gpio	*regs;
+ 	char			bank_name[3];
+--- a/drivers/gpio/axp_gpio.c
++++ b/drivers/gpio/axp_gpio.c
+@@ -15,6 +15,9 @@
+ #include <dm/root.h>
+ #include <errno.h>
+ 
++#define AXP_GPIO_PREFIX			"AXP0-"
++#define AXP_GPIO_COUNT			4
++
+ static int axp_gpio_set_value(struct udevice *dev, unsigned pin, int val);
+ 
+ static u8 axp_get_gpio_ctrl_reg(unsigned pin)
+@@ -46,28 +49,14 @@ static int axp_gpio_direction_input(stru
+ static int axp_gpio_direction_output(struct udevice *dev, unsigned pin,
+ 				     int val)
+ {
+-	__maybe_unused int ret;
+ 	u8 reg;
+ 
+-	switch (pin) {
+-#ifdef AXP_MISC_CTRL_N_VBUSEN_FUNC
+-	/* Only available on later PMICs */
+-	case SUNXI_GPIO_AXP0_VBUS_ENABLE:
+-		ret = pmic_bus_clrbits(AXP_MISC_CTRL,
+-				       AXP_MISC_CTRL_N_VBUSEN_FUNC);
+-		if (ret)
+-			return ret;
+-
+-		return axp_gpio_set_value(dev, pin, val);
+-#endif
+-	default:
+-		reg = axp_get_gpio_ctrl_reg(pin);
+-		if (reg == 0)
+-			return -EINVAL;
++	reg = axp_get_gpio_ctrl_reg(pin);
++	if (reg == 0)
++		return -EINVAL;
+ 
+-		return pmic_bus_write(reg, val ? AXP_GPIO_CTRL_OUTPUT_HIGH :
+-						 AXP_GPIO_CTRL_OUTPUT_LOW);
+-	}
++	return pmic_bus_write(reg, val ? AXP_GPIO_CTRL_OUTPUT_HIGH :
++					 AXP_GPIO_CTRL_OUTPUT_LOW);
+ }
+ 
+ static int axp_gpio_get_value(struct udevice *dev, unsigned pin)
+@@ -75,25 +64,16 @@ static int axp_gpio_get_value(struct ude
+ 	u8 reg, val, mask;
+ 	int ret;
+ 
+-	switch (pin) {
+-#ifdef AXP_MISC_CTRL_N_VBUSEN_FUNC
+-	/* Only available on later PMICs */
+-	case SUNXI_GPIO_AXP0_VBUS_ENABLE:
+-		ret = pmic_bus_read(AXP_VBUS_IPSOUT, &val);
+-		mask = AXP_VBUS_IPSOUT_DRIVEBUS;
+-		break;
+-#endif
+-	default:
+-		reg = axp_get_gpio_ctrl_reg(pin);
+-		if (reg == 0)
+-			return -EINVAL;
++	reg = axp_get_gpio_ctrl_reg(pin);
++	if (reg == 0)
++		return -EINVAL;
+ 
+-		ret = pmic_bus_read(AXP_GPIO_STATE, &val);
+-		mask = 1 << (pin + AXP_GPIO_STATE_OFFSET);
+-	}
++	ret = pmic_bus_read(AXP_GPIO_STATE, &val);
+ 	if (ret)
+ 		return ret;
+ 
++	mask = 1 << (pin + AXP_GPIO_STATE_OFFSET);
++
+ 	return (val & mask) ? 1 : 0;
+ }
+ 
+@@ -101,25 +81,12 @@ static int axp_gpio_set_value(struct ude
+ {
+ 	u8 reg;
+ 
+-	switch (pin) {
+-#ifdef AXP_MISC_CTRL_N_VBUSEN_FUNC
+-	/* Only available on later PMICs */
+-	case SUNXI_GPIO_AXP0_VBUS_ENABLE:
+-		if (val)
+-			return pmic_bus_setbits(AXP_VBUS_IPSOUT,
+-						AXP_VBUS_IPSOUT_DRIVEBUS);
+-		else
+-			return pmic_bus_clrbits(AXP_VBUS_IPSOUT,
+-						AXP_VBUS_IPSOUT_DRIVEBUS);
+-#endif
+-	default:
+-		reg = axp_get_gpio_ctrl_reg(pin);
+-		if (reg == 0)
+-			return -EINVAL;
++	reg = axp_get_gpio_ctrl_reg(pin);
++	if (reg == 0)
++		return -EINVAL;
+ 
+-		return pmic_bus_write(reg, val ? AXP_GPIO_CTRL_OUTPUT_HIGH :
+-						 AXP_GPIO_CTRL_OUTPUT_LOW);
+-	}
++	return pmic_bus_write(reg, val ? AXP_GPIO_CTRL_OUTPUT_HIGH :
++					 AXP_GPIO_CTRL_OUTPUT_LOW);
+ }
+ 
+ static const struct dm_gpio_ops gpio_axp_ops = {
+@@ -134,8 +101,8 @@ static int gpio_axp_probe(struct udevice
+ 	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ 
+ 	/* Tell the uclass how many GPIOs we have */
+-	uc_priv->bank_name = strdup(SUNXI_GPIO_AXP0_PREFIX);
+-	uc_priv->gpio_count = SUNXI_GPIO_AXP0_GPIO_COUNT;
++	uc_priv->bank_name = AXP_GPIO_PREFIX;
++	uc_priv->gpio_count = AXP_GPIO_COUNT;
+ 
+ 	return 0;
+ }
+--- a/drivers/gpio/sunxi_gpio.c
++++ b/drivers/gpio/sunxi_gpio.c
+@@ -114,15 +114,7 @@ int sunxi_name_to_gpio(const char *name)
+ {
+ 	unsigned int gpio;
+ 	int ret;
+-#if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO
+-	char lookup[8];
+ 
+-	if (strcasecmp(name, "AXP0-VBUS-ENABLE") == 0) {
+-		sprintf(lookup, SUNXI_GPIO_AXP0_PREFIX "%d",
+-			SUNXI_GPIO_AXP0_VBUS_ENABLE);
+-		name = lookup;
+-	}
+-#endif
+ 	ret = gpio_lookup_name(name, NULL, NULL, &gpio);
+ 
+ 	return ret ? ret : gpio;
+--- a/include/axp221.h
++++ b/include/axp221.h
+@@ -53,10 +53,6 @@
+ #ifdef CONFIG_AXP221_POWER
+ #define AXP_POWER_STATUS		0x00
+ #define AXP_POWER_STATUS_ALDO_IN		BIT(0)
+-#define AXP_VBUS_IPSOUT			0x30
+-#define AXP_VBUS_IPSOUT_DRIVEBUS		(1 << 2)
+-#define AXP_MISC_CTRL			0x8f
+-#define AXP_MISC_CTRL_N_VBUSEN_FUNC		(1 << 4)
+ #define AXP_GPIO0_CTRL			0x90
+ #define AXP_GPIO1_CTRL			0x92
+ #define AXP_GPIO_CTRL_OUTPUT_LOW		0x00 /* Drive pin low */
+--- a/include/axp809.h
++++ b/include/axp809.h
+@@ -47,10 +47,6 @@
+ #ifdef CONFIG_AXP809_POWER
+ #define AXP_POWER_STATUS		0x00
+ #define AXP_POWER_STATUS_ALDO_IN		BIT(0)
+-#define AXP_VBUS_IPSOUT			0x30
+-#define AXP_VBUS_IPSOUT_DRIVEBUS		(1 << 2)
+-#define AXP_MISC_CTRL			0x8f
+-#define AXP_MISC_CTRL_N_VBUSEN_FUNC		(1 << 4)
+ #define AXP_GPIO0_CTRL			0x90
+ #define AXP_GPIO1_CTRL			0x92
+ #define AXP_GPIO_CTRL_OUTPUT_LOW	0x00 /* Drive pin low */
+--- a/include/axp818.h
++++ b/include/axp818.h
+@@ -61,10 +61,6 @@
+ #ifdef CONFIG_AXP818_POWER
+ #define AXP_POWER_STATUS		0x00
+ #define AXP_POWER_STATUS_ALDO_IN		BIT(0)
+-#define AXP_VBUS_IPSOUT			0x30
+-#define AXP_VBUS_IPSOUT_DRIVEBUS		(1 << 2)
+-#define AXP_MISC_CTRL			0x8f
+-#define AXP_MISC_CTRL_N_VBUSEN_FUNC		(1 << 4)
+ #define AXP_GPIO0_CTRL			0x90
+ #define AXP_GPIO1_CTRL			0x92
+ #define AXP_GPIO_CTRL_OUTPUT_LOW	0x00 /* Drive pin low */
diff --git a/package/boot/uboot-d1/patches/0013-clk-sunxi-Add-a-driver-for-the-legacy-A31-A23-A33-PR.patch b/package/boot/uboot-d1/patches/0013-clk-sunxi-Add-a-driver-for-the-legacy-A31-A23-A33-PR.patch
new file mode 100644
index 00000000000000..2c0029a29b8b37
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0013-clk-sunxi-Add-a-driver-for-the-legacy-A31-A23-A33-PR.patch
@@ -0,0 +1,160 @@
+From 5a909f4d4d10f3a7a59b3b75eee502937e166891 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Mon, 2 May 2022 22:00:05 -0500
+Subject: [PATCH 13/90] clk: sunxi: Add a driver for the legacy A31/A23/A33
+ PRCM
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/clk/sunxi/Kconfig        | 13 ++++-
+ drivers/clk/sunxi/Makefile       |  1 +
+ drivers/clk/sunxi/clk_a31_apb0.c | 97 ++++++++++++++++++++++++++++++++
+ include/clk/sunxi.h              |  1 +
+ 4 files changed, 110 insertions(+), 2 deletions(-)
+ create mode 100644 drivers/clk/sunxi/clk_a31_apb0.c
+
+--- a/drivers/clk/sunxi/Kconfig
++++ b/drivers/clk/sunxi/Kconfig
+@@ -38,12 +38,21 @@ config CLK_SUN6I_A31
+ 	  This enables common clock driver support for platforms based
+ 	  on Allwinner A31/A31s SoC.
+ 
++config CLK_SUN6I_A31_APB0
++	bool "Clock driver for Allwinner A31 generation PRCM (legacy)"
++	default MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33
++	help
++	  This enables common clock driver support for the PRCM
++	  in Allwinner A31/A31s/A23/A33 SoCs using the legacy PRCM
++	  MFD binding.
++
+ config CLK_SUN6I_A31_R
+-	bool "Clock driver for Allwinner A31 generation PRCM"
++	bool "Clock driver for Allwinner A31 generation PRCM (CCU)"
+ 	default SUNXI_GEN_SUN6I
+ 	help
+ 	  This enables common clock driver support for the PRCM
+-	  in Allwinner A31/A31s/A23/A33/A83T/H3/A64/H5 SoCs.
++	  in Allwinner A31/A31s/A23/A33/A83T/H3/A64/H5 SoCs using
++	  the new CCU binding.
+ 
+ config CLK_SUN8I_A23
+ 	bool "Clock driver for Allwinner A23/A33"
+--- a/drivers/clk/sunxi/Makefile
++++ b/drivers/clk/sunxi/Makefile
+@@ -12,6 +12,7 @@ obj-$(CONFIG_CLK_SUNIV_F1C100S) += clk_f
+ obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o
+ obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o
+ obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o
++obj-$(CONFIG_CLK_SUN6I_A31_APB0) += clk_a31_apb0.o
+ obj-$(CONFIG_CLK_SUN6I_A31_R) += clk_a31_r.o
+ obj-$(CONFIG_CLK_SUN8I_A23) += clk_a23.o
+ obj-$(CONFIG_CLK_SUN8I_A83T) += clk_a83t.o
+--- /dev/null
++++ b/drivers/clk/sunxi/clk_a31_apb0.c
+@@ -0,0 +1,97 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (C) Samuel Holland <samuel@sholland.org>
++ */
++
++#include <clk-uclass.h>
++#include <dm.h>
++#include <clk/sunxi.h>
++#include <linux/bitops.h>
++
++static struct ccu_clk_gate sun6i_apb0_gates[] = {
++	[0]	= GATE(0x028, BIT(0)),
++	[1]	= GATE(0x028, BIT(1)),
++	[2]	= GATE(0x028, BIT(2)),
++	[3]	= GATE(0x028, BIT(3)),
++	[4]	= GATE(0x028, BIT(4)),
++	[5]	= GATE(0x028, BIT(5)),
++	[6]	= GATE(0x028, BIT(6)),
++	[7]	= GATE(0x028, BIT(7)),
++};
++
++static struct ccu_reset sun6i_apb0_resets[] = {
++	[0]	= RESET(0x0b0, BIT(0)),
++	[1]	= RESET(0x0b0, BIT(1)),
++	[2]	= RESET(0x0b0, BIT(2)),
++	[3]	= RESET(0x0b0, BIT(3)),
++	[4]	= RESET(0x0b0, BIT(4)),
++	[5]	= RESET(0x0b0, BIT(5)),
++	[6]	= RESET(0x0b0, BIT(6)),
++	[7]	= RESET(0x0b0, BIT(7)),
++};
++
++const struct ccu_desc sun6i_apb0_clk_desc = {
++	.gates = sun6i_apb0_gates,
++	.resets = sun6i_apb0_resets,
++	.num_gates = ARRAY_SIZE(sun6i_apb0_gates),
++	.num_resets = ARRAY_SIZE(sun6i_apb0_resets),
++};
++
++static int sun6i_apb0_of_to_plat(struct udevice *dev)
++{
++	struct ccu_plat *plat = dev_get_plat(dev);
++
++	plat->base = dev_read_addr_ptr(dev->parent);
++	if (!plat->base)
++		return -ENOMEM;
++
++	plat->desc = (const struct ccu_desc *)dev_get_driver_data(dev);
++	if (!plat->desc)
++		return -EINVAL;
++
++	return 0;
++}
++
++static const struct udevice_id sun6i_apb0_clk_ids[] = {
++	{ .compatible = "allwinner,sun6i-a31-apb0-gates-clk",
++	  .data = (ulong)&sun6i_apb0_clk_desc },
++	{ .compatible = "allwinner,sun8i-a23-apb0-gates-clk",
++	  .data = (ulong)&sun6i_apb0_clk_desc },
++	{ }
++};
++
++U_BOOT_DRIVER(sun6i_apb0_clk) = {
++	.name		= "sun6i_apb0_clk",
++	.id		= UCLASS_CLK,
++	.of_match	= sun6i_apb0_clk_ids,
++	.of_to_plat	= sun6i_apb0_of_to_plat,
++	.plat_auto	= sizeof(struct ccu_plat),
++	.ops		= &sunxi_clk_ops,
++};
++
++static const struct udevice_id sun6i_apb0_reset_ids[] = {
++	{ .compatible = "allwinner,sun6i-a31-clock-reset",
++	  .data = (ulong)&sun6i_apb0_clk_desc },
++	{ }
++};
++
++U_BOOT_DRIVER(sun6i_apb0_reset) = {
++	.name		= "sun6i_apb0_reset",
++	.id		= UCLASS_RESET,
++	.of_match	= sun6i_apb0_reset_ids,
++	.of_to_plat	= sun6i_apb0_of_to_plat,
++	.plat_auto	= sizeof(struct ccu_plat),
++	.ops		= &sunxi_reset_ops,
++};
++
++static const struct udevice_id sun6i_prcm_mfd_ids[] = {
++	{ .compatible = "allwinner,sun6i-a31-prcm" },
++	{ .compatible = "allwinner,sun8i-a23-prcm" },
++	{ }
++};
++
++U_BOOT_DRIVER(sun6i_prcm_mfd) = {
++	.name		= "sun6i_prcm_mfd",
++	.id		= UCLASS_SIMPLE_BUS,
++	.of_match	= sun6i_prcm_mfd_ids,
++};
+--- a/include/clk/sunxi.h
++++ b/include/clk/sunxi.h
+@@ -86,5 +86,6 @@ struct ccu_plat {
+ };
+ 
+ extern struct clk_ops sunxi_clk_ops;
++extern struct reset_ops sunxi_reset_ops;
+ 
+ #endif /* _CLK_SUNXI_H */
diff --git a/package/boot/uboot-d1/patches/0014-clk-sunxi-Use-the-right-symbol-in-the-Makefile.patch b/package/boot/uboot-d1/patches/0014-clk-sunxi-Use-the-right-symbol-in-the-Makefile.patch
new file mode 100644
index 00000000000000..858af896aa5ff0
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0014-clk-sunxi-Use-the-right-symbol-in-the-Makefile.patch
@@ -0,0 +1,21 @@
+From 3d97f99cb173422ee8a15b7ec1df83ff61e68204 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 30 Oct 2022 14:28:23 -0500
+Subject: [PATCH 14/90] clk: sunxi: Use the right symbol in the Makefile
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/clk/Makefile | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/clk/Makefile
++++ b/drivers/clk/Makefile
+@@ -25,7 +25,7 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
+ obj-$(CONFIG_ARCH_SOCFPGA) += altera/
+ obj-$(CONFIG_ARCH_STM32) += stm32/
+ obj-$(CONFIG_ARCH_STM32MP) += stm32/
+-obj-$(CONFIG_ARCH_SUNXI) += sunxi/
++obj-$(CONFIG_CLK_SUNXI) += sunxi/
+ obj-$(CONFIG_CLK_AT91) += at91/
+ obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o
+ obj-$(CONFIG_CLK_BOSTON) += clk_boston.o
diff --git a/package/boot/uboot-d1/patches/0015-net-sun8i-emac-Use-common-syscon-setup-for-R40.patch b/package/boot/uboot-d1/patches/0015-net-sun8i-emac-Use-common-syscon-setup-for-R40.patch
new file mode 100644
index 00000000000000..41e72bdd2f1193
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0015-net-sun8i-emac-Use-common-syscon-setup-for-R40.patch
@@ -0,0 +1,100 @@
+From 9766169812418aee10dbc8d40aca27c1c576f521 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Thu, 14 Jul 2022 23:39:46 -0500
+Subject: [PATCH 15/90] net: sun8i-emac: Use common syscon setup for R40
+
+While R40 puts the EMAC syscon register at a different address from
+other variants, the relevant portion of the register's layout is the
+same. Factor out the register offset so the same code can be shared
+by all variants. This matches what the Linux driver does.
+
+This change provides two benefits beyond the simplification:
+ - R40 boards now respect the RX delays from the devicetree
+ - This resolves a warning on architectures where readl/writel
+   expect the address to have a pointer type, not phys_addr_t.
+
+Series-to: sunxi
+
+Cover-letter:
+net: sun8i-emac: Allwinner D1 Support
+D1 is a RISC-V SoC containing an EMAC compatible with the A64 EMAC.
+However, there are a couple of issues with the driver preventing it
+being built for RISC-V. These are resolved by patches 2-3. Patch 1 is
+a general cleanup.
+END
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/net/sun8i_emac.c | 29 ++++++++++++-----------------
+ 1 file changed, 12 insertions(+), 17 deletions(-)
+
+--- a/drivers/net/sun8i_emac.c
++++ b/drivers/net/sun8i_emac.c
+@@ -162,7 +162,7 @@ struct emac_eth_dev {
+ 
+ 	enum emac_variant variant;
+ 	void *mac_reg;
+-	phys_addr_t sysctl_reg;
++	void *sysctl_reg;
+ 	struct phy_device *phydev;
+ 	struct mii_dev *bus;
+ 	struct clk tx_clk;
+@@ -317,18 +317,7 @@ static int sun8i_emac_set_syscon(struct
+ {
+ 	u32 reg;
+ 
+-	if (priv->variant == R40_GMAC) {
+-		/* Select RGMII for R40 */
+-		reg = readl(priv->sysctl_reg + 0x164);
+-		reg |= SC_ETCS_INT_GMII |
+-		       SC_EPIT |
+-		       (CONFIG_GMAC_TX_DELAY << SC_ETXDC_OFFSET);
+-
+-		writel(reg, priv->sysctl_reg + 0x164);
+-		return 0;
+-	}
+-
+-	reg = readl(priv->sysctl_reg + 0x30);
++	reg = readl(priv->sysctl_reg);
+ 
+ 	reg = sun8i_emac_set_syscon_ephy(priv, reg);
+ 
+@@ -369,7 +358,7 @@ static int sun8i_emac_set_syscon(struct
+ 		reg |= ((pdata->rx_delay_ps / 100) << SC_ERXDC_OFFSET)
+ 			 & SC_ERXDC_MASK;
+ 
+-	writel(reg, priv->sysctl_reg + 0x30);
++	writel(reg, priv->sysctl_reg);
+ 
+ 	return 0;
+ }
+@@ -792,6 +781,7 @@ static int sun8i_emac_eth_of_to_plat(str
+ 	struct sun8i_eth_pdata *sun8i_pdata = dev_get_plat(dev);
+ 	struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
+ 	struct emac_eth_dev *priv = dev_get_priv(dev);
++	phys_addr_t syscon_base;
+ 	const fdt32_t *reg;
+ 	int node = dev_of_offset(dev);
+ 	int offset = 0;
+@@ -837,13 +827,18 @@ static int sun8i_emac_eth_of_to_plat(str
+ 		      __func__);
+ 		return -EINVAL;
+ 	}
+-	priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob,
+-						 offset, reg);
+-	if (priv->sysctl_reg == FDT_ADDR_T_NONE) {
++
++	syscon_base = fdt_translate_address((void *)gd->fdt_blob, offset, reg);
++	if (syscon_base == FDT_ADDR_T_NONE) {
+ 		debug("%s: Cannot find syscon base address\n", __func__);
+ 		return -EINVAL;
+ 	}
+ 
++	if (priv->variant == R40_GMAC)
++		priv->sysctl_reg = (void *)syscon_base + 0x164;
++	else
++		priv->sysctl_reg = (void *)syscon_base + 0x30;
++
+ 	pdata->phy_interface = -1;
+ 	priv->phyaddr = -1;
+ 	priv->use_internal_phy = false;
diff --git a/package/boot/uboot-d1/patches/0016-sunxi-mmc-ignore-card-detect-in-SPL.patch b/package/boot/uboot-d1/patches/0016-sunxi-mmc-ignore-card-detect-in-SPL.patch
new file mode 100644
index 00000000000000..a8fe0cb8302dc1
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0016-sunxi-mmc-ignore-card-detect-in-SPL.patch
@@ -0,0 +1,92 @@
+From 2cde6c8a7c41c13137298c19b4e104e4f5d6851c Mon Sep 17 00:00:00 2001
+From: Andre Przywara <andre.przywara@arm.com>
+Date: Wed, 13 Jul 2022 17:21:43 +0100
+Subject: [PATCH 16/90] sunxi: mmc: ignore card detect in SPL
+
+The sunxi MMC code does not use the DM in the SPL, as we don't have a
+device tree available that early, also no space for it.
+This also means we cannot access the card-detect GPIO information from
+there, so we have Kconfig symbols called CONFIG_MMCx_CD_PIN, which each
+board has to define. This is a burden, also requires extra GPIO code in
+the SPL.
+As the SPL is the natural successor of the BootROM (from which we are
+loaded), we can actually ignore the CD pin completely, as this is what
+the BootROM does as well: CD GPIOs are board specific, but the BootROM
+is not, so accesses the MMC devices anyway.
+
+Remove the card detect code from the non-DM implementation of the sunxi
+MMC driver, to get rid of this unneeded code.
+
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+---
+ drivers/mmc/sunxi_mmc.c | 37 ++-----------------------------------
+ 1 file changed, 2 insertions(+), 35 deletions(-)
+
+--- a/drivers/mmc/sunxi_mmc.c
++++ b/drivers/mmc/sunxi_mmc.c
+@@ -44,22 +44,10 @@ struct sunxi_mmc_priv {
+ /* support 4 mmc hosts */
+ struct sunxi_mmc_priv mmc_host[4];
+ 
+-static int sunxi_mmc_getcd_gpio(int sdc_no)
+-{
+-	switch (sdc_no) {
+-	case 0: return sunxi_name_to_gpio(CONFIG_MMC0_CD_PIN);
+-	case 1: return sunxi_name_to_gpio(CONFIG_MMC1_CD_PIN);
+-	case 2: return sunxi_name_to_gpio(CONFIG_MMC2_CD_PIN);
+-	case 3: return sunxi_name_to_gpio(CONFIG_MMC3_CD_PIN);
+-	}
+-	return -EINVAL;
+-}
+-
+ static int mmc_resource_init(int sdc_no)
+ {
+ 	struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
+ 	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+-	int cd_pin, ret = 0;
+ 
+ 	debug("init mmc %d resource\n", sdc_no);
+ 
+@@ -90,16 +78,7 @@ static int mmc_resource_init(int sdc_no)
+ 	}
+ 	priv->mmc_no = sdc_no;
+ 
+-	cd_pin = sunxi_mmc_getcd_gpio(sdc_no);
+-	if (cd_pin >= 0) {
+-		ret = gpio_request(cd_pin, "mmc_cd");
+-		if (!ret) {
+-			sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP);
+-			ret = gpio_direction_input(cd_pin);
+-		}
+-	}
+-
+-	return ret;
++	return 0;
+ }
+ #endif
+ 
+@@ -523,23 +502,11 @@ static int sunxi_mmc_send_cmd_legacy(str
+ 	return sunxi_mmc_send_cmd_common(priv, mmc, cmd, data);
+ }
+ 
+-static int sunxi_mmc_getcd_legacy(struct mmc *mmc)
+-{
+-	struct sunxi_mmc_priv *priv = mmc->priv;
+-	int cd_pin;
+-
+-	cd_pin = sunxi_mmc_getcd_gpio(priv->mmc_no);
+-	if (cd_pin < 0)
+-		return 1;
+-
+-	return !gpio_get_value(cd_pin);
+-}
+-
++/* .get_cd is not needed by the SPL */
+ static const struct mmc_ops sunxi_mmc_ops = {
+ 	.send_cmd	= sunxi_mmc_send_cmd_legacy,
+ 	.set_ios	= sunxi_mmc_set_ios_legacy,
+ 	.init		= sunxi_mmc_core_init,
+-	.getcd		= sunxi_mmc_getcd_legacy,
+ };
+ 
+ struct mmc *sunxi_mmc_init(int sdc_no)
diff --git a/package/boot/uboot-d1/patches/0017-sunxi-mmc-group-non-DM-specific-functions.patch b/package/boot/uboot-d1/patches/0017-sunxi-mmc-group-non-DM-specific-functions.patch
new file mode 100644
index 00000000000000..6161c33187a45c
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0017-sunxi-mmc-group-non-DM-specific-functions.patch
@@ -0,0 +1,177 @@
+From 74afc3a4e0ff780eddd859a25de7142e4baeeed5 Mon Sep 17 00:00:00 2001
+From: Andre Przywara <andre.przywara@arm.com>
+Date: Wed, 13 Jul 2022 17:21:44 +0100
+Subject: [PATCH 17/90] sunxi: mmc: group non-DM specific functions
+
+As the SPL code for sunxi boards does not use the driver model, we have
+two mmc_ops structures, one for DM, one for non-DM. The actual hardware
+access code is shared, with the respective callback functions using that
+common code.
+
+To make this more obvious and easier to read, reorder the functions to
+group them: we first have the common code, then the non-DM bits, and
+the proper DM implementation at the end.
+Also document this structure in the comment at the beginning of the file.
+
+No functional change intended.
+
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+---
+ drivers/mmc/sunxi_mmc.c | 117 +++++++++++++++++++++-------------------
+ 1 file changed, 61 insertions(+), 56 deletions(-)
+
+--- a/drivers/mmc/sunxi_mmc.c
++++ b/drivers/mmc/sunxi_mmc.c
+@@ -5,6 +5,12 @@
+  * Aaron <leafy.myeh@allwinnertech.com>
+  *
+  * MMC driver for allwinner sunxi platform.
++ *
++ * This driver is used by the (ARM) SPL with the legacy MMC interface, and
++ * by U-Boot proper using the full DM interface. The actual hardware access
++ * code is common, and comes first in this file.
++ * The legacy MMC interface implementation comes next, followed by the
++ * proper DM_MMC implementation at the end.
+  */
+ 
+ #include <common.h>
+@@ -40,48 +46,6 @@ struct sunxi_mmc_priv {
+ 	struct mmc_config cfg;
+ };
+ 
+-#if !CONFIG_IS_ENABLED(DM_MMC)
+-/* support 4 mmc hosts */
+-struct sunxi_mmc_priv mmc_host[4];
+-
+-static int mmc_resource_init(int sdc_no)
+-{
+-	struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
+-	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+-
+-	debug("init mmc %d resource\n", sdc_no);
+-
+-	switch (sdc_no) {
+-	case 0:
+-		priv->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE;
+-		priv->mclkreg = &ccm->sd0_clk_cfg;
+-		break;
+-	case 1:
+-		priv->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE;
+-		priv->mclkreg = &ccm->sd1_clk_cfg;
+-		break;
+-#ifdef SUNXI_MMC2_BASE
+-	case 2:
+-		priv->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
+-		priv->mclkreg = &ccm->sd2_clk_cfg;
+-		break;
+-#endif
+-#ifdef SUNXI_MMC3_BASE
+-	case 3:
+-		priv->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
+-		priv->mclkreg = &ccm->sd3_clk_cfg;
+-		break;
+-#endif
+-	default:
+-		printf("Wrong mmc number %d\n", sdc_no);
+-		return -1;
+-	}
+-	priv->mmc_no = sdc_no;
+-
+-	return 0;
+-}
+-#endif
+-
+ /*
+  * All A64 and later MMC controllers feature auto-calibration. This would
+  * normally be detected via the compatible string, but we need something
+@@ -269,19 +233,6 @@ static int sunxi_mmc_set_ios_common(stru
+ 	return 0;
+ }
+ 
+-#if !CONFIG_IS_ENABLED(DM_MMC)
+-static int sunxi_mmc_core_init(struct mmc *mmc)
+-{
+-	struct sunxi_mmc_priv *priv = mmc->priv;
+-
+-	/* Reset controller */
+-	writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
+-	udelay(1000);
+-
+-	return 0;
+-}
+-#endif
+-
+ static int mmc_trans_data_by_cpu(struct sunxi_mmc_priv *priv, struct mmc *mmc,
+ 				 struct mmc_data *data)
+ {
+@@ -486,7 +437,60 @@ out:
+ 	return error;
+ }
+ 
++/* non-DM code here is used by the (ARM) SPL only */
++
+ #if !CONFIG_IS_ENABLED(DM_MMC)
++/* support 4 mmc hosts */
++struct sunxi_mmc_priv mmc_host[4];
++
++static int mmc_resource_init(int sdc_no)
++{
++	struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
++	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
++
++	debug("init mmc %d resource\n", sdc_no);
++
++	switch (sdc_no) {
++	case 0:
++		priv->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE;
++		priv->mclkreg = &ccm->sd0_clk_cfg;
++		break;
++	case 1:
++		priv->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE;
++		priv->mclkreg = &ccm->sd1_clk_cfg;
++		break;
++#ifdef SUNXI_MMC2_BASE
++	case 2:
++		priv->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
++		priv->mclkreg = &ccm->sd2_clk_cfg;
++		break;
++#endif
++#ifdef SUNXI_MMC3_BASE
++	case 3:
++		priv->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
++		priv->mclkreg = &ccm->sd3_clk_cfg;
++		break;
++#endif
++	default:
++		printf("Wrong mmc number %d\n", sdc_no);
++		return -1;
++	}
++	priv->mmc_no = sdc_no;
++
++	return 0;
++}
++
++static int sunxi_mmc_core_init(struct mmc *mmc)
++{
++	struct sunxi_mmc_priv *priv = mmc->priv;
++
++	/* Reset controller */
++	writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
++	udelay(1000);
++
++	return 0;
++}
++
+ static int sunxi_mmc_set_ios_legacy(struct mmc *mmc)
+ {
+ 	struct sunxi_mmc_priv *priv = mmc->priv;
+@@ -562,7 +566,8 @@ struct mmc *sunxi_mmc_init(int sdc_no)
+ 
+ 	return mmc_create(cfg, priv);
+ }
+-#else
++
++#else /* CONFIG_DM_MMC code below, as used by U-Boot proper */
+ 
+ static int sunxi_mmc_set_ios(struct udevice *dev)
+ {
diff --git a/package/boot/uboot-d1/patches/0018-sunxi-remove-CONFIG_MMC-_CD_PIN.patch b/package/boot/uboot-d1/patches/0018-sunxi-remove-CONFIG_MMC-_CD_PIN.patch
new file mode 100644
index 00000000000000..a87b6e26ce3bc1
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0018-sunxi-remove-CONFIG_MMC-_CD_PIN.patch
@@ -0,0 +1,509 @@
+From bcc2e01668041c146d964ed5f77b819dcc35b3e2 Mon Sep 17 00:00:00 2001
+From: Zoltan HERPAI <wigyori@uid0.hu>
+Date: Tue, 6 Jun 2023 15:07:47 +0000
+Subject: [PATCH 18/90] sunxi: remove CONFIG_MMC?_CD_PIN
+
+For legacy reasons we were defining the card detect GPIO for all sunxi
+boards in each board's defconfig.
+There is actually no need for a card-detect check in the SPL code (which
+consequently has been removed already), and also in U-Boot proper we
+have DM code to query the CD GPIO name from the device tree.
+
+That means we don't have any user of that information left, so can
+remove the definitions from the defconfigs.
+
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
+---
+ arch/arm/mach-sunxi/Kconfig                  | 27 --------------------
+ configs/A10-OLinuXino-Lime_defconfig         |  1 -
+ configs/A10s-OLinuXino-M_defconfig           |  2 --
+ configs/A13-OLinuXino_defconfig              |  1 -
+ configs/A20-OLinuXino-Lime2-eMMC_defconfig   |  1 -
+ configs/A20-OLinuXino-Lime_defconfig         |  1 -
+ configs/A20-OLinuXino_MICRO-eMMC_defconfig   |  1 -
+ configs/A20-OLinuXino_MICRO_defconfig        |  2 --
+ configs/A20-Olimex-SOM-EVB_defconfig         |  2 --
+ configs/A20-Olimex-SOM204-EVB-eMMC_defconfig |  1 -
+ configs/Bananapi_M2_Ultra_defconfig          |  1 -
+ configs/Bananapi_m2m_defconfig               |  1 -
+ configs/Cubieboard2_defconfig                |  1 -
+ configs/Cubieboard4_defconfig                |  1 -
+ configs/Cubieboard_defconfig                 |  1 -
+ configs/Itead_Ibox_A20_defconfig             |  1 -
+ configs/Lamobo_R1_defconfig                  |  1 -
+ configs/Mele_M3_defconfig                    |  1 -
+ configs/Mele_M5_defconfig                    |  1 -
+ configs/Merrii_A80_Optimus_defconfig         |  1 -
+ configs/Orangepi_mini_defconfig              |  2 --
+ configs/Sinlinx_SinA31s_defconfig            |  1 -
+ configs/Sinlinx_SinA33_defconfig             |  1 -
+ configs/Sunchip_CX-A99_defconfig             |  1 -
+ configs/UTOO_P66_defconfig                   |  1 -
+ configs/Yones_Toptech_BD1078_defconfig       |  2 --
+ configs/bananapi_m2_zero_defconfig           |  1 -
+ configs/bananapi_m64_defconfig               |  1 -
+ configs/beelink_gs1_defconfig                |  1 -
+ configs/nanopi_m1_plus_defconfig             |  1 -
+ configs/oceanic_5205_5inmfd_defconfig        |  1 -
+ configs/orangepi_3_defconfig                 |  1 -
+ configs/orangepi_lite2_defconfig             |  1 -
+ configs/orangepi_one_plus_defconfig          |  1 -
+ configs/orangepi_zero2_defconfig             |  1 -
+ configs/orangepi_zero_plus2_defconfig        |  1 -
+ configs/orangepi_zero_plus2_h3_defconfig     |  1 -
+ configs/parrot_r16_defconfig                 |  1 -
+ configs/pine64-lts_defconfig                 |  1 -
+ configs/pine_h64_defconfig                   |  1 -
+ configs/sopine_baseboard_defconfig           |  1 -
+ configs/tanix_tx6_defconfig                  |  1 -
+ 42 files changed, 73 deletions(-)
+
+--- a/arch/arm/mach-sunxi/Kconfig
++++ b/arch/arm/mach-sunxi/Kconfig
+@@ -652,33 +652,6 @@ config MACPWR
+ 	  Set the pin used to power the MAC. This takes a string in the format
+ 	  understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
+ 
+-config MMC0_CD_PIN
+-	string "Card detect pin for mmc0"
+-	default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
+-	default ""
+-	---help---
+-	Set the card detect pin for mmc0, leave empty to not use cd. This
+-	takes a string in the format understood by sunxi_name_to_gpio, e.g.
+-	PH1 for pin 1 of port H.
+-
+-config MMC1_CD_PIN
+-	string "Card detect pin for mmc1"
+-	default ""
+-	---help---
+-	See MMC0_CD_PIN help text.
+-
+-config MMC2_CD_PIN
+-	string "Card detect pin for mmc2"
+-	default ""
+-	---help---
+-	See MMC0_CD_PIN help text.
+-
+-config MMC3_CD_PIN
+-	string "Card detect pin for mmc3"
+-	default ""
+-	---help---
+-	See MMC0_CD_PIN help text.
+-
+ config MMC1_PINS_PH
+ 	bool "Pins for mmc1 are on Port H"
+ 	depends on MACH_SUN4I || MACH_SUN7I || MACH_SUN8I_R40
+--- a/configs/A10-OLinuXino-Lime_defconfig
++++ b/configs/A10-OLinuXino-Lime_defconfig
+@@ -6,7 +6,6 @@ CONFIG_MACH_SUN4I=y
+ CONFIG_DRAM_CLK=480
+ CONFIG_DRAM_EMR1=4
+ CONFIG_SYS_CLK_FREQ=912000000
+-CONFIG_MMC0_CD_PIN="PH1"
+ CONFIG_I2C1_ENABLE=y
+ CONFIG_SATAPWR="PC3"
+ CONFIG_AHCI=y
+--- a/configs/A10s-OLinuXino-M_defconfig
++++ b/configs/A10s-OLinuXino-M_defconfig
+@@ -4,8 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-o
+ CONFIG_SPL=y
+ CONFIG_MACH_SUN5I=y
+ CONFIG_DRAM_CLK=432
+-CONFIG_MMC0_CD_PIN="PG1"
+-CONFIG_MMC1_CD_PIN="PG13"
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=1
+ CONFIG_USB1_VBUS_PIN="PB10"
+ # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+--- a/configs/A13-OLinuXino_defconfig
++++ b/configs/A13-OLinuXino_defconfig
+@@ -5,7 +5,6 @@ CONFIG_SPL=y
+ CONFIG_MACH_SUN5I=y
+ CONFIG_DRAM_CLK=408
+ CONFIG_DRAM_EMR1=0
+-CONFIG_MMC0_CD_PIN="PG0"
+ CONFIG_USB0_VBUS_DET="PG1"
+ CONFIG_USB1_VBUS_PIN="PG11"
+ CONFIG_AXP_GPIO=y
+--- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig
++++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
+@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-ol
+ CONFIG_SPL=y
+ CONFIG_MACH_SUN7I=y
+ CONFIG_DRAM_CLK=384
+-CONFIG_MMC0_CD_PIN="PH1"
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+ CONFIG_USB0_VBUS_PIN="PC17"
+ CONFIG_USB0_VBUS_DET="PH5"
+--- a/configs/A20-OLinuXino-Lime_defconfig
++++ b/configs/A20-OLinuXino-Lime_defconfig
+@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-ol
+ CONFIG_SPL=y
+ CONFIG_MACH_SUN7I=y
+ CONFIG_DRAM_CLK=384
+-CONFIG_MMC0_CD_PIN="PH1"
+ CONFIG_I2C1_ENABLE=y
+ CONFIG_SATAPWR="PC3"
+ CONFIG_AHCI=y
+--- a/configs/A20-OLinuXino_MICRO-eMMC_defconfig
++++ b/configs/A20-OLinuXino_MICRO-eMMC_defconfig
+@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-ol
+ CONFIG_SPL=y
+ CONFIG_MACH_SUN7I=y
+ CONFIG_DRAM_CLK=384
+-CONFIG_MMC0_CD_PIN="PH1"
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+ CONFIG_I2C1_ENABLE=y
+ CONFIG_VIDEO_VGA=y
+--- a/configs/A20-OLinuXino_MICRO_defconfig
++++ b/configs/A20-OLinuXino_MICRO_defconfig
+@@ -4,8 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-ol
+ CONFIG_SPL=y
+ CONFIG_MACH_SUN7I=y
+ CONFIG_DRAM_CLK=384
+-CONFIG_MMC0_CD_PIN="PH1"
+-CONFIG_MMC3_CD_PIN="PH11"
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=3
+ CONFIG_I2C1_ENABLE=y
+ CONFIG_VIDEO_VGA=y
+--- a/configs/A20-Olimex-SOM-EVB_defconfig
++++ b/configs/A20-Olimex-SOM-EVB_defconfig
+@@ -4,8 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-ol
+ CONFIG_SPL=y
+ CONFIG_MACH_SUN7I=y
+ CONFIG_DRAM_CLK=384
+-CONFIG_MMC0_CD_PIN="PH1"
+-CONFIG_MMC3_CD_PIN="PH0"
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=3
+ CONFIG_USB0_VBUS_PIN="PB9"
+ CONFIG_USB0_VBUS_DET="PH5"
+--- a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
++++ b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
+@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-ol
+ CONFIG_SPL=y
+ CONFIG_MACH_SUN7I=y
+ CONFIG_DRAM_CLK=384
+-CONFIG_MMC0_CD_PIN="PH1"
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+ CONFIG_USB0_VBUS_PIN="PC17"
+ CONFIG_USB0_VBUS_DET="PH5"
+--- a/configs/Bananapi_M2_Ultra_defconfig
++++ b/configs/Bananapi_M2_Ultra_defconfig
+@@ -5,7 +5,6 @@ CONFIG_SPL=y
+ CONFIG_MACH_SUN8I_R40=y
+ CONFIG_DRAM_CLK=576
+ CONFIG_MACPWR="PA17"
+-CONFIG_MMC0_CD_PIN="PH13"
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+ CONFIG_USB1_VBUS_PIN="PH23"
+ CONFIG_USB2_VBUS_PIN="PH23"
+--- a/configs/Bananapi_m2m_defconfig
++++ b/configs/Bananapi_m2m_defconfig
+@@ -6,7 +6,6 @@ CONFIG_MACH_SUN8I_A33=y
+ CONFIG_DRAM_CLK=600
+ CONFIG_DRAM_ZQ=15291
+ CONFIG_DRAM_ODT_EN=y
+-CONFIG_MMC0_CD_PIN="PB4"
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+ CONFIG_USB0_ID_DET="PH8"
+ # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+--- a/configs/Cubieboard2_defconfig
++++ b/configs/Cubieboard2_defconfig
+@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cu
+ CONFIG_SPL=y
+ CONFIG_MACH_SUN7I=y
+ CONFIG_DRAM_CLK=480
+-CONFIG_MMC0_CD_PIN="PH1"
+ CONFIG_SATAPWR="PB8"
+ CONFIG_AHCI=y
+ # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+--- a/configs/Cubieboard4_defconfig
++++ b/configs/Cubieboard4_defconfig
+@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun9i-a80-cu
+ CONFIG_SPL=y
+ CONFIG_MACH_SUN9I=y
+ CONFIG_DRAM_CLK=672
+-CONFIG_MMC0_CD_PIN="PH18"
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+ CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
+ CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
+--- a/configs/Cubieboard_defconfig
++++ b/configs/Cubieboard_defconfig
+@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-cu
+ CONFIG_SPL=y
+ CONFIG_MACH_SUN4I=y
+ CONFIG_DRAM_CLK=480
+-CONFIG_MMC0_CD_PIN="PH1"
+ CONFIG_SATAPWR="PB8"
+ CONFIG_AHCI=y
+ # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+--- a/configs/Itead_Ibox_A20_defconfig
++++ b/configs/Itead_Ibox_A20_defconfig
+@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-it
+ CONFIG_SPL=y
+ CONFIG_MACH_SUN7I=y
+ CONFIG_DRAM_CLK=480
+-CONFIG_MMC0_CD_PIN="PH1"
+ CONFIG_SATAPWR="PB8"
+ CONFIG_AHCI=y
+ # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+--- a/configs/Lamobo_R1_defconfig
++++ b/configs/Lamobo_R1_defconfig
+@@ -5,7 +5,6 @@ CONFIG_SPL=y
+ CONFIG_MACH_SUN7I=y
+ CONFIG_DRAM_CLK=432
+ CONFIG_MACPWR="PH23"
+-CONFIG_MMC0_CD_PIN="PH10"
+ CONFIG_SATAPWR="PB3"
+ CONFIG_GMAC_TX_DELAY=4
+ CONFIG_AHCI=y
+--- a/configs/Mele_M3_defconfig
++++ b/configs/Mele_M3_defconfig
+@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m3
+ CONFIG_SPL=y
+ CONFIG_MACH_SUN7I=y
+ CONFIG_DRAM_CLK=384
+-CONFIG_MMC0_CD_PIN="PH1"
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+ CONFIG_VIDEO_VGA=y
+ CONFIG_VIDEO_COMPOSITE=y
+--- a/configs/Mele_M5_defconfig
++++ b/configs/Mele_M5_defconfig
+@@ -5,7 +5,6 @@ CONFIG_SPL=y
+ CONFIG_MACH_SUN7I=y
+ CONFIG_DRAM_CLK=432
+ CONFIG_DRAM_ZQ=122
+-CONFIG_MMC0_CD_PIN="PH1"
+ CONFIG_VIDEO_COMPOSITE=y
+ CONFIG_AHCI=y
+ # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+--- a/configs/Merrii_A80_Optimus_defconfig
++++ b/configs/Merrii_A80_Optimus_defconfig
+@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun9i-a80-op
+ CONFIG_SPL=y
+ CONFIG_MACH_SUN9I=y
+ CONFIG_DRAM_CLK=672
+-CONFIG_MMC0_CD_PIN="PH18"
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+ CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
+ CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
+--- a/configs/Orangepi_mini_defconfig
++++ b/configs/Orangepi_mini_defconfig
+@@ -5,8 +5,6 @@ CONFIG_SPL=y
+ CONFIG_MACH_SUN7I=y
+ CONFIG_DRAM_CLK=432
+ CONFIG_MACPWR="PH23"
+-CONFIG_MMC0_CD_PIN="PH10"
+-CONFIG_MMC3_CD_PIN="PH11"
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=3
+ CONFIG_USB1_VBUS_PIN="PH26"
+ CONFIG_USB2_VBUS_PIN="PH22"
+--- a/configs/Sinlinx_SinA31s_defconfig
++++ b/configs/Sinlinx_SinA31s_defconfig
+@@ -5,7 +5,6 @@ CONFIG_SPL=y
+ CONFIG_MACH_SUN6I=y
+ CONFIG_DRAM_CLK=432
+ CONFIG_DRAM_ZQ=251
+-CONFIG_MMC0_CD_PIN="PA4"
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=3
+ CONFIG_USB1_VBUS_PIN=""
+ CONFIG_USB2_VBUS_PIN=""
+--- a/configs/Sinlinx_SinA33_defconfig
++++ b/configs/Sinlinx_SinA33_defconfig
+@@ -5,7 +5,6 @@ CONFIG_SPL=y
+ CONFIG_MACH_SUN8I_A33=y
+ CONFIG_DRAM_CLK=552
+ CONFIG_DRAM_ZQ=15291
+-CONFIG_MMC0_CD_PIN="PB4"
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+ CONFIG_USB0_ID_DET="PH8"
+ CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:66000,le:90,ri:160,up:3,lo:127,hs:70,vs:20,sync:3,vmode:0"
+--- a/configs/Sunchip_CX-A99_defconfig
++++ b/configs/Sunchip_CX-A99_defconfig
+@@ -6,7 +6,6 @@ CONFIG_MACH_SUN9I=y
+ CONFIG_DRAM_CLK=600
+ CONFIG_DRAM_ZQ=3881915
+ CONFIG_DRAM_ODT_EN=y
+-CONFIG_MMC0_CD_PIN="PH17"
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+ CONFIG_USB0_VBUS_PIN="PH15"
+ CONFIG_USB1_VBUS_PIN="PL7"
+--- a/configs/UTOO_P66_defconfig
++++ b/configs/UTOO_P66_defconfig
+@@ -5,7 +5,6 @@ CONFIG_SPL=y
+ CONFIG_MACH_SUN5I=y
+ CONFIG_DRAM_CLK=432
+ CONFIG_DRAM_EMR1=0
+-CONFIG_MMC0_CD_PIN="PG0"
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+ CONFIG_USB0_VBUS_PIN="PB04"
+ CONFIG_USB0_VBUS_DET="PG01"
+--- a/configs/Yones_Toptech_BD1078_defconfig
++++ b/configs/Yones_Toptech_BD1078_defconfig
+@@ -4,8 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-yo
+ CONFIG_SPL=y
+ CONFIG_MACH_SUN7I=y
+ CONFIG_DRAM_CLK=408
+-CONFIG_MMC0_CD_PIN="PH1"
+-CONFIG_MMC1_CD_PIN="PH2"
+ CONFIG_MMC1_PINS_PH=y
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=1
+ CONFIG_USB0_VBUS_PIN="PB9"
+--- a/configs/bananapi_m2_zero_defconfig
++++ b/configs/bananapi_m2_zero_defconfig
+@@ -4,5 +4,4 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plu
+ CONFIG_SPL=y
+ CONFIG_MACH_SUN8I_H3=y
+ CONFIG_DRAM_CLK=408
+-CONFIG_MMC0_CD_PIN=""
+ # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+--- a/configs/bananapi_m64_defconfig
++++ b/configs/bananapi_m64_defconfig
+@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-b
+ CONFIG_SPL=y
+ CONFIG_MACH_SUN50I=y
+ CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
+-CONFIG_MMC0_CD_PIN="PH13"
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+ # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+ CONFIG_SUPPORT_EMMC_BOOT=y
+--- a/configs/beelink_gs1_defconfig
++++ b/configs/beelink_gs1_defconfig
+@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-be
+ CONFIG_SPL=y
+ CONFIG_MACH_SUN50I_H6=y
+ CONFIG_SUNXI_DRAM_H6_LPDDR3=y
+-CONFIG_MMC0_CD_PIN="PF6"
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+ # CONFIG_PSCI_RESET is not set
+ # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+--- a/configs/nanopi_m1_plus_defconfig
++++ b/configs/nanopi_m1_plus_defconfig
+@@ -5,7 +5,6 @@ CONFIG_SPL=y
+ CONFIG_MACH_SUN8I_H3=y
+ CONFIG_DRAM_CLK=408
+ CONFIG_MACPWR="PD6"
+-CONFIG_MMC0_CD_PIN="PH13"
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+ # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+ CONFIG_SUN8I_EMAC=y
+--- a/configs/oceanic_5205_5inmfd_defconfig
++++ b/configs/oceanic_5205_5inmfd_defconfig
+@@ -7,7 +7,6 @@ CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
+ CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y
+ CONFIG_DRAM_CLK=552
+ CONFIG_DRAM_ZQ=3881949
+-CONFIG_MMC0_CD_PIN=""
+ CONFIG_SPL_SPI_SUNXI=y
+ # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+ CONFIG_SUN8I_EMAC=y
+--- a/configs/orangepi_3_defconfig
++++ b/configs/orangepi_3_defconfig
+@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-or
+ CONFIG_SPL=y
+ CONFIG_MACH_SUN50I_H6=y
+ CONFIG_SUNXI_DRAM_H6_LPDDR3=y
+-CONFIG_MMC0_CD_PIN="PF6"
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+ CONFIG_BLUETOOTH_DT_DEVICE_FIXUP="brcm,bcm4345c5"
+ # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+--- a/configs/orangepi_lite2_defconfig
++++ b/configs/orangepi_lite2_defconfig
+@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-or
+ CONFIG_SPL=y
+ CONFIG_MACH_SUN50I_H6=y
+ CONFIG_SUNXI_DRAM_H6_LPDDR3=y
+-CONFIG_MMC0_CD_PIN="PF6"
+ # CONFIG_PSCI_RESET is not set
+ # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+ CONFIG_USB_EHCI_HCD=y
+--- a/configs/orangepi_one_plus_defconfig
++++ b/configs/orangepi_one_plus_defconfig
+@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-or
+ CONFIG_SPL=y
+ CONFIG_MACH_SUN50I_H6=y
+ CONFIG_SUNXI_DRAM_H6_LPDDR3=y
+-CONFIG_MMC0_CD_PIN="PF6"
+ # CONFIG_PSCI_RESET is not set
+ # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+ CONFIG_USB_EHCI_HCD=y
+--- a/configs/orangepi_zero2_defconfig
++++ b/configs/orangepi_zero2_defconfig
+@@ -7,7 +7,6 @@ CONFIG_DRAM_SUN50I_H616_READ_CALIBRATION
+ CONFIG_DRAM_SUN50I_H616_READ_TRAINING=y
+ CONFIG_DRAM_SUN50I_H616_WRITE_TRAINING=y
+ CONFIG_MACH_SUN50I_H616=y
+-CONFIG_MMC0_CD_PIN="PF6"
+ CONFIG_R_I2C_ENABLE=y
+ CONFIG_SPL_SPI_SUNXI=y
+ # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+--- a/configs/orangepi_zero_plus2_defconfig
++++ b/configs/orangepi_zero_plus2_defconfig
+@@ -6,7 +6,6 @@ CONFIG_MACH_SUN50I_H5=y
+ CONFIG_DRAM_CLK=672
+ CONFIG_DRAM_ZQ=3881977
+ # CONFIG_DRAM_ODT_EN is not set
+-CONFIG_MMC0_CD_PIN="PH13"
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+ # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+ CONFIG_SUN8I_EMAC=y
+--- a/configs/orangepi_zero_plus2_h3_defconfig
++++ b/configs/orangepi_zero_plus2_h3_defconfig
+@@ -5,7 +5,6 @@ CONFIG_SPL=y
+ CONFIG_MACH_SUN8I_H3=y
+ CONFIG_DRAM_CLK=672
+ # CONFIG_DRAM_ODT_EN is not set
+-CONFIG_MMC0_CD_PIN="PH13"
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+ # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+ CONFIG_SUN8I_EMAC=y
+--- a/configs/parrot_r16_defconfig
++++ b/configs/parrot_r16_defconfig
+@@ -5,7 +5,6 @@ CONFIG_SPL=y
+ CONFIG_MACH_SUN8I_A33=y
+ CONFIG_DRAM_CLK=600
+ CONFIG_DRAM_ZQ=15291
+-CONFIG_MMC0_CD_PIN="PD14"
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+ CONFIG_USB0_ID_DET="PD10"
+ CONFIG_USB1_VBUS_PIN="PD12"
+--- a/configs/pine64-lts_defconfig
++++ b/configs/pine64-lts_defconfig
+@@ -6,7 +6,6 @@ CONFIG_MACH_SUN50I=y
+ CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y
+ CONFIG_DRAM_CLK=552
+ CONFIG_DRAM_ZQ=3881949
+-CONFIG_MMC0_CD_PIN=""
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+ CONFIG_SPL_SPI_SUNXI=y
+ # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+--- a/configs/pine_h64_defconfig
++++ b/configs/pine_h64_defconfig
+@@ -5,7 +5,6 @@ CONFIG_SPL=y
+ CONFIG_MACH_SUN50I_H6=y
+ CONFIG_SUNXI_DRAM_H6_LPDDR3=y
+ CONFIG_MACPWR="PC16"
+-CONFIG_MMC0_CD_PIN="PF6"
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+ CONFIG_USB3_VBUS_PIN="PL5"
+ CONFIG_SPL_SPI_SUNXI=y
+--- a/configs/sopine_baseboard_defconfig
++++ b/configs/sopine_baseboard_defconfig
+@@ -7,7 +7,6 @@ CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
+ CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y
+ CONFIG_DRAM_CLK=552
+ CONFIG_DRAM_ZQ=3881949
+-CONFIG_MMC0_CD_PIN=""
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+ CONFIG_SPL_SPI_SUNXI=y
+ # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+--- a/configs/tanix_tx6_defconfig
++++ b/configs/tanix_tx6_defconfig
+@@ -5,6 +5,5 @@ CONFIG_SPL=y
+ CONFIG_MACH_SUN50I_H6=y
+ CONFIG_SUNXI_DRAM_H6_DDR3_1333=y
+ CONFIG_DRAM_CLK=648
+-CONFIG_MMC0_CD_PIN="PF6"
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+ # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/package/boot/uboot-d1/patches/0019-sunxi-mmc-Move-header-to-the-driver-directory.patch b/package/boot/uboot-d1/patches/0019-sunxi-mmc-Move-header-to-the-driver-directory.patch
new file mode 100644
index 00000000000000..3299ad49dea0a0
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0019-sunxi-mmc-Move-header-to-the-driver-directory.patch
@@ -0,0 +1,323 @@
+From 4c0c00e7131baf410702555342337c178dd0de98 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 30 Oct 2022 16:04:47 -0500
+Subject: [PATCH 19/90] sunxi: mmc: Move header to the driver directory
+
+The MMC controller driver is (and ought to be) the only user of these
+register definitions. Put them in a header next to the driver to remove
+the dependency on a specific ARM platform's headers.
+
+Due to the sunxi_mmc_init() prototype, the file was not renamed. None of
+the register definitions were changed.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm/include/asm/arch-sunxi/mmc.h | 139 +-------------------------
+ drivers/mmc/sunxi_mmc.c               |   4 +
+ drivers/mmc/sunxi_mmc.h               | 138 +++++++++++++++++++++++++
+ 3 files changed, 146 insertions(+), 135 deletions(-)
+ create mode 100644 drivers/mmc/sunxi_mmc.h
+
+--- a/arch/arm/include/asm/arch-sunxi/mmc.h
++++ b/arch/arm/include/asm/arch-sunxi/mmc.h
+@@ -1,139 +1,8 @@
+ /* SPDX-License-Identifier: GPL-2.0+ */
+-/*
+- * (C) Copyright 2007-2011
+- * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+- * Aaron <leafy.myeh@allwinnertech.com>
+- *
+- * MMC register definition for allwinner sunxi platform.
+- */
+ 
+-#ifndef _SUNXI_MMC_H
+-#define _SUNXI_MMC_H
+-
+-#include <linux/types.h>
+-
+-struct sunxi_mmc {
+-	u32 gctrl;		/* 0x00 global control */
+-	u32 clkcr;		/* 0x04 clock control */
+-	u32 timeout;		/* 0x08 time out */
+-	u32 width;		/* 0x0c bus width */
+-	u32 blksz;		/* 0x10 block size */
+-	u32 bytecnt;		/* 0x14 byte count */
+-	u32 cmd;		/* 0x18 command */
+-	u32 arg;		/* 0x1c argument */
+-	u32 resp0;		/* 0x20 response 0 */
+-	u32 resp1;		/* 0x24 response 1 */
+-	u32 resp2;		/* 0x28 response 2 */
+-	u32 resp3;		/* 0x2c response 3 */
+-	u32 imask;		/* 0x30 interrupt mask */
+-	u32 mint;		/* 0x34 masked interrupt status */
+-	u32 rint;		/* 0x38 raw interrupt status */
+-	u32 status;		/* 0x3c status */
+-	u32 ftrglevel;		/* 0x40 FIFO threshold watermark*/
+-	u32 funcsel;		/* 0x44 function select */
+-	u32 cbcr;		/* 0x48 CIU byte count */
+-	u32 bbcr;		/* 0x4c BIU byte count */
+-	u32 dbgc;		/* 0x50 debug enable */
+-	u32 res0;		/* 0x54 reserved */
+-	u32 a12a;		/* 0x58 Auto command 12 argument */
+-	u32 ntsr;		/* 0x5c	New timing set register */
+-	u32 res1[8];
+-	u32 dmac;		/* 0x80 internal DMA control */
+-	u32 dlba;		/* 0x84 internal DMA descr list base address */
+-	u32 idst;		/* 0x88 internal DMA status */
+-	u32 idie;		/* 0x8c internal DMA interrupt enable */
+-	u32 chda;		/* 0x90 */
+-	u32 cbda;		/* 0x94 */
+-	u32 res2[26];
+-#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
+-	u32 res3[17];
+-	u32 samp_dl;
+-	u32 res4[46];
+-#endif
+-	u32 fifo;		/* 0x100 / 0x200 FIFO access address */
+-};
+-
+-#define SUNXI_MMC_CLK_POWERSAVE		(0x1 << 17)
+-#define SUNXI_MMC_CLK_ENABLE		(0x1 << 16)
+-#define SUNXI_MMC_CLK_DIVIDER_MASK	(0xff)
+-
+-#define SUNXI_MMC_GCTRL_SOFT_RESET	(0x1 << 0)
+-#define SUNXI_MMC_GCTRL_FIFO_RESET	(0x1 << 1)
+-#define SUNXI_MMC_GCTRL_DMA_RESET	(0x1 << 2)
+-#define SUNXI_MMC_GCTRL_RESET		(SUNXI_MMC_GCTRL_SOFT_RESET|\
+-					 SUNXI_MMC_GCTRL_FIFO_RESET|\
+-					 SUNXI_MMC_GCTRL_DMA_RESET)
+-#define SUNXI_MMC_GCTRL_DMA_ENABLE	(0x1 << 5)
+-#define SUNXI_MMC_GCTRL_ACCESS_BY_AHB   (0x1 << 31)
+-
+-#define SUNXI_MMC_CMD_RESP_EXPIRE	(0x1 << 6)
+-#define SUNXI_MMC_CMD_LONG_RESPONSE	(0x1 << 7)
+-#define SUNXI_MMC_CMD_CHK_RESPONSE_CRC	(0x1 << 8)
+-#define SUNXI_MMC_CMD_DATA_EXPIRE	(0x1 << 9)
+-#define SUNXI_MMC_CMD_WRITE		(0x1 << 10)
+-#define SUNXI_MMC_CMD_AUTO_STOP		(0x1 << 12)
+-#define SUNXI_MMC_CMD_WAIT_PRE_OVER	(0x1 << 13)
+-#define SUNXI_MMC_CMD_SEND_INIT_SEQ	(0x1 << 15)
+-#define SUNXI_MMC_CMD_UPCLK_ONLY	(0x1 << 21)
+-#define SUNXI_MMC_CMD_START		(0x1 << 31)
+-
+-#define SUNXI_MMC_RINT_RESP_ERROR		(0x1 << 1)
+-#define SUNXI_MMC_RINT_COMMAND_DONE		(0x1 << 2)
+-#define SUNXI_MMC_RINT_DATA_OVER		(0x1 << 3)
+-#define SUNXI_MMC_RINT_TX_DATA_REQUEST		(0x1 << 4)
+-#define SUNXI_MMC_RINT_RX_DATA_REQUEST		(0x1 << 5)
+-#define SUNXI_MMC_RINT_RESP_CRC_ERROR		(0x1 << 6)
+-#define SUNXI_MMC_RINT_DATA_CRC_ERROR		(0x1 << 7)
+-#define SUNXI_MMC_RINT_RESP_TIMEOUT		(0x1 << 8)
+-#define SUNXI_MMC_RINT_DATA_TIMEOUT		(0x1 << 9)
+-#define SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE	(0x1 << 10)
+-#define SUNXI_MMC_RINT_FIFO_RUN_ERROR		(0x1 << 11)
+-#define SUNXI_MMC_RINT_HARD_WARE_LOCKED		(0x1 << 12)
+-#define SUNXI_MMC_RINT_START_BIT_ERROR		(0x1 << 13)
+-#define SUNXI_MMC_RINT_AUTO_COMMAND_DONE	(0x1 << 14)
+-#define SUNXI_MMC_RINT_END_BIT_ERROR		(0x1 << 15)
+-#define SUNXI_MMC_RINT_SDIO_INTERRUPT		(0x1 << 16)
+-#define SUNXI_MMC_RINT_CARD_INSERT		(0x1 << 30)
+-#define SUNXI_MMC_RINT_CARD_REMOVE		(0x1 << 31)
+-#define SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT      \
+-	(SUNXI_MMC_RINT_RESP_ERROR |		\
+-	 SUNXI_MMC_RINT_RESP_CRC_ERROR |	\
+-	 SUNXI_MMC_RINT_DATA_CRC_ERROR |	\
+-	 SUNXI_MMC_RINT_RESP_TIMEOUT |		\
+-	 SUNXI_MMC_RINT_DATA_TIMEOUT |		\
+-	 SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE |	\
+-	 SUNXI_MMC_RINT_FIFO_RUN_ERROR |	\
+-	 SUNXI_MMC_RINT_HARD_WARE_LOCKED |	\
+-	 SUNXI_MMC_RINT_START_BIT_ERROR |	\
+-	 SUNXI_MMC_RINT_END_BIT_ERROR) /* 0xbfc2 */
+-#define SUNXI_MMC_RINT_INTERRUPT_DONE_BIT	\
+-	(SUNXI_MMC_RINT_AUTO_COMMAND_DONE |	\
+-	 SUNXI_MMC_RINT_DATA_OVER |		\
+-	 SUNXI_MMC_RINT_COMMAND_DONE |		\
+-	 SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE)
+-
+-#define SUNXI_MMC_STATUS_RXWL_FLAG		(0x1 << 0)
+-#define SUNXI_MMC_STATUS_TXWL_FLAG		(0x1 << 1)
+-#define SUNXI_MMC_STATUS_FIFO_EMPTY		(0x1 << 2)
+-#define SUNXI_MMC_STATUS_FIFO_FULL		(0x1 << 3)
+-#define SUNXI_MMC_STATUS_CARD_PRESENT		(0x1 << 8)
+-#define SUNXI_MMC_STATUS_CARD_DATA_BUSY		(0x1 << 9)
+-#define SUNXI_MMC_STATUS_DATA_FSM_BUSY		(0x1 << 10)
+-#define SUNXI_MMC_STATUS_FIFO_LEVEL(reg)	(((reg) >> 17) & 0x3fff)
+-
+-#define SUNXI_MMC_NTSR_MODE_SEL_NEW		(0x1 << 31)
+-
+-#define SUNXI_MMC_IDMAC_RESET		(0x1 << 0)
+-#define SUNXI_MMC_IDMAC_FIXBURST	(0x1 << 1)
+-#define SUNXI_MMC_IDMAC_ENABLE		(0x1 << 7)
+-
+-#define SUNXI_MMC_IDIE_TXIRQ		(0x1 << 0)
+-#define SUNXI_MMC_IDIE_RXIRQ		(0x1 << 1)
+-
+-#define SUNXI_MMC_COMMON_CLK_GATE		(1 << 16)
+-#define SUNXI_MMC_COMMON_RESET			(1 << 18)
+-
+-#define SUNXI_MMC_CAL_DL_SW_EN		(0x1 << 7)
++#ifndef _ASM_ARCH_MMC_H_
++#define _ASM_ARCH_MMC_H_
+ 
+ struct mmc *sunxi_mmc_init(int sdc_no);
+-#endif /* _SUNXI_MMC_H */
++
++#endif /* _ASM_ARCH_MMC_H_ */
+--- a/drivers/mmc/sunxi_mmc.c
++++ b/drivers/mmc/sunxi_mmc.c
+@@ -25,9 +25,13 @@
+ #include <asm/io.h>
+ #include <asm/arch/clock.h>
+ #include <asm/arch/cpu.h>
++#if !CONFIG_IS_ENABLED(DM_MMC)
+ #include <asm/arch/mmc.h>
++#endif
+ #include <linux/delay.h>
+ 
++#include "sunxi_mmc.h"
++
+ #ifndef CCM_MMC_CTRL_MODE_SEL_NEW
+ #define CCM_MMC_CTRL_MODE_SEL_NEW	0
+ #endif
+--- /dev/null
++++ b/drivers/mmc/sunxi_mmc.h
+@@ -0,0 +1,138 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * (C) Copyright 2007-2011
++ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
++ * Aaron <leafy.myeh@allwinnertech.com>
++ *
++ * MMC register definition for allwinner sunxi platform.
++ */
++
++#ifndef _SUNXI_MMC_H
++#define _SUNXI_MMC_H
++
++#include <linux/types.h>
++
++struct sunxi_mmc {
++	u32 gctrl;		/* 0x00 global control */
++	u32 clkcr;		/* 0x04 clock control */
++	u32 timeout;		/* 0x08 time out */
++	u32 width;		/* 0x0c bus width */
++	u32 blksz;		/* 0x10 block size */
++	u32 bytecnt;		/* 0x14 byte count */
++	u32 cmd;		/* 0x18 command */
++	u32 arg;		/* 0x1c argument */
++	u32 resp0;		/* 0x20 response 0 */
++	u32 resp1;		/* 0x24 response 1 */
++	u32 resp2;		/* 0x28 response 2 */
++	u32 resp3;		/* 0x2c response 3 */
++	u32 imask;		/* 0x30 interrupt mask */
++	u32 mint;		/* 0x34 masked interrupt status */
++	u32 rint;		/* 0x38 raw interrupt status */
++	u32 status;		/* 0x3c status */
++	u32 ftrglevel;		/* 0x40 FIFO threshold watermark*/
++	u32 funcsel;		/* 0x44 function select */
++	u32 cbcr;		/* 0x48 CIU byte count */
++	u32 bbcr;		/* 0x4c BIU byte count */
++	u32 dbgc;		/* 0x50 debug enable */
++	u32 res0;		/* 0x54 reserved */
++	u32 a12a;		/* 0x58 Auto command 12 argument */
++	u32 ntsr;		/* 0x5c	New timing set register */
++	u32 res1[8];
++	u32 dmac;		/* 0x80 internal DMA control */
++	u32 dlba;		/* 0x84 internal DMA descr list base address */
++	u32 idst;		/* 0x88 internal DMA status */
++	u32 idie;		/* 0x8c internal DMA interrupt enable */
++	u32 chda;		/* 0x90 */
++	u32 cbda;		/* 0x94 */
++	u32 res2[26];
++#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
++	u32 res3[17];
++	u32 samp_dl;
++	u32 res4[46];
++#endif
++	u32 fifo;		/* 0x100 / 0x200 FIFO access address */
++};
++
++#define SUNXI_MMC_CLK_POWERSAVE		(0x1 << 17)
++#define SUNXI_MMC_CLK_ENABLE		(0x1 << 16)
++#define SUNXI_MMC_CLK_DIVIDER_MASK	(0xff)
++
++#define SUNXI_MMC_GCTRL_SOFT_RESET	(0x1 << 0)
++#define SUNXI_MMC_GCTRL_FIFO_RESET	(0x1 << 1)
++#define SUNXI_MMC_GCTRL_DMA_RESET	(0x1 << 2)
++#define SUNXI_MMC_GCTRL_RESET		(SUNXI_MMC_GCTRL_SOFT_RESET|\
++					 SUNXI_MMC_GCTRL_FIFO_RESET|\
++					 SUNXI_MMC_GCTRL_DMA_RESET)
++#define SUNXI_MMC_GCTRL_DMA_ENABLE	(0x1 << 5)
++#define SUNXI_MMC_GCTRL_ACCESS_BY_AHB   (0x1 << 31)
++
++#define SUNXI_MMC_CMD_RESP_EXPIRE	(0x1 << 6)
++#define SUNXI_MMC_CMD_LONG_RESPONSE	(0x1 << 7)
++#define SUNXI_MMC_CMD_CHK_RESPONSE_CRC	(0x1 << 8)
++#define SUNXI_MMC_CMD_DATA_EXPIRE	(0x1 << 9)
++#define SUNXI_MMC_CMD_WRITE		(0x1 << 10)
++#define SUNXI_MMC_CMD_AUTO_STOP		(0x1 << 12)
++#define SUNXI_MMC_CMD_WAIT_PRE_OVER	(0x1 << 13)
++#define SUNXI_MMC_CMD_SEND_INIT_SEQ	(0x1 << 15)
++#define SUNXI_MMC_CMD_UPCLK_ONLY	(0x1 << 21)
++#define SUNXI_MMC_CMD_START		(0x1 << 31)
++
++#define SUNXI_MMC_RINT_RESP_ERROR		(0x1 << 1)
++#define SUNXI_MMC_RINT_COMMAND_DONE		(0x1 << 2)
++#define SUNXI_MMC_RINT_DATA_OVER		(0x1 << 3)
++#define SUNXI_MMC_RINT_TX_DATA_REQUEST		(0x1 << 4)
++#define SUNXI_MMC_RINT_RX_DATA_REQUEST		(0x1 << 5)
++#define SUNXI_MMC_RINT_RESP_CRC_ERROR		(0x1 << 6)
++#define SUNXI_MMC_RINT_DATA_CRC_ERROR		(0x1 << 7)
++#define SUNXI_MMC_RINT_RESP_TIMEOUT		(0x1 << 8)
++#define SUNXI_MMC_RINT_DATA_TIMEOUT		(0x1 << 9)
++#define SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE	(0x1 << 10)
++#define SUNXI_MMC_RINT_FIFO_RUN_ERROR		(0x1 << 11)
++#define SUNXI_MMC_RINT_HARD_WARE_LOCKED		(0x1 << 12)
++#define SUNXI_MMC_RINT_START_BIT_ERROR		(0x1 << 13)
++#define SUNXI_MMC_RINT_AUTO_COMMAND_DONE	(0x1 << 14)
++#define SUNXI_MMC_RINT_END_BIT_ERROR		(0x1 << 15)
++#define SUNXI_MMC_RINT_SDIO_INTERRUPT		(0x1 << 16)
++#define SUNXI_MMC_RINT_CARD_INSERT		(0x1 << 30)
++#define SUNXI_MMC_RINT_CARD_REMOVE		(0x1 << 31)
++#define SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT      \
++	(SUNXI_MMC_RINT_RESP_ERROR |		\
++	 SUNXI_MMC_RINT_RESP_CRC_ERROR |	\
++	 SUNXI_MMC_RINT_DATA_CRC_ERROR |	\
++	 SUNXI_MMC_RINT_RESP_TIMEOUT |		\
++	 SUNXI_MMC_RINT_DATA_TIMEOUT |		\
++	 SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE |	\
++	 SUNXI_MMC_RINT_FIFO_RUN_ERROR |	\
++	 SUNXI_MMC_RINT_HARD_WARE_LOCKED |	\
++	 SUNXI_MMC_RINT_START_BIT_ERROR |	\
++	 SUNXI_MMC_RINT_END_BIT_ERROR) /* 0xbfc2 */
++#define SUNXI_MMC_RINT_INTERRUPT_DONE_BIT	\
++	(SUNXI_MMC_RINT_AUTO_COMMAND_DONE |	\
++	 SUNXI_MMC_RINT_DATA_OVER |		\
++	 SUNXI_MMC_RINT_COMMAND_DONE |		\
++	 SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE)
++
++#define SUNXI_MMC_STATUS_RXWL_FLAG		(0x1 << 0)
++#define SUNXI_MMC_STATUS_TXWL_FLAG		(0x1 << 1)
++#define SUNXI_MMC_STATUS_FIFO_EMPTY		(0x1 << 2)
++#define SUNXI_MMC_STATUS_FIFO_FULL		(0x1 << 3)
++#define SUNXI_MMC_STATUS_CARD_PRESENT		(0x1 << 8)
++#define SUNXI_MMC_STATUS_CARD_DATA_BUSY		(0x1 << 9)
++#define SUNXI_MMC_STATUS_DATA_FSM_BUSY		(0x1 << 10)
++#define SUNXI_MMC_STATUS_FIFO_LEVEL(reg)	(((reg) >> 17) & 0x3fff)
++
++#define SUNXI_MMC_NTSR_MODE_SEL_NEW		(0x1 << 31)
++
++#define SUNXI_MMC_IDMAC_RESET		(0x1 << 0)
++#define SUNXI_MMC_IDMAC_FIXBURST	(0x1 << 1)
++#define SUNXI_MMC_IDMAC_ENABLE		(0x1 << 7)
++
++#define SUNXI_MMC_IDIE_TXIRQ		(0x1 << 0)
++#define SUNXI_MMC_IDIE_RXIRQ		(0x1 << 1)
++
++#define SUNXI_MMC_COMMON_CLK_GATE		(1 << 16)
++#define SUNXI_MMC_COMMON_RESET			(1 << 18)
++
++#define SUNXI_MMC_CAL_DL_SW_EN		(0x1 << 7)
++
++#endif /* _SUNXI_MMC_H */
diff --git a/package/boot/uboot-d1/patches/0020-pinctrl-sunxi-Add-support-for-the-D1.patch b/package/boot/uboot-d1/patches/0020-pinctrl-sunxi-Add-support-for-the-D1.patch
new file mode 100644
index 00000000000000..383db83d171b59
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0020-pinctrl-sunxi-Add-support-for-the-D1.patch
@@ -0,0 +1,72 @@
+From fdf871a6089ee2f56439880b69d33a7d0d707d15 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 28 Aug 2021 22:24:28 -0500
+Subject: [PATCH 20/90] pinctrl: sunxi: Add support for the D1
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/pinctrl/sunxi/Kconfig         |  5 +++++
+ drivers/pinctrl/sunxi/pinctrl-sunxi.c | 31 +++++++++++++++++++++++++++
+ 2 files changed, 36 insertions(+)
+
+--- a/drivers/pinctrl/sunxi/Kconfig
++++ b/drivers/pinctrl/sunxi/Kconfig
+@@ -89,6 +89,11 @@ config PINCTRL_SUN9I_A80_R
+ 	default MACH_SUN9I
+ 	select PINCTRL_SUNXI
+ 
++config PINCTRL_SUN20I_D1
++	bool "Support for the Allwinner D1 PIO"
++	default TARGET_SUN20I_D1
++	select PINCTRL_SUNXI
++
+ config PINCTRL_SUN50I_A64
+ 	bool "Support for the Allwinner A64 PIO"
+ 	default MACH_SUN50I
+--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
++++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+@@ -588,6 +588,31 @@ static const struct sunxi_pinctrl_desc _
+ 	.num_banks	= 3,
+ };
+ 
++static const struct sunxi_pinctrl_function sun20i_d1_pinctrl_functions[] = {
++	{ "emac",	8 },	/* PE0-PE15 */
++	{ "gpio_in",	0 },
++	{ "gpio_out",	1 },
++	{ "i2c0",	4 },	/* PB10-PB11 */
++	{ "mmc0",	2 },	/* PF0-PF5 */
++	{ "mmc1",	2 },	/* PG0-PG5 */
++	{ "mmc2",	3 },	/* PC2-PC7 */
++	{ "spi0",	2 },	/* PC2-PC7 */
++#if IS_ENABLED(CONFIG_UART0_PORT_F)
++	{ "uart0",	3 },	/* PF2-PF4 */
++#else
++	{ "uart0",	6 },	/* PB8-PB9 */
++#endif
++	{ "uart1",	2 },	/* PG6-PG7 */
++	{ "uart2",	7 },	/* PB0-PB1 */
++};
++
++static const struct sunxi_pinctrl_desc __maybe_unused sun20i_d1_pinctrl_desc = {
++	.functions	= sun20i_d1_pinctrl_functions,
++	.num_functions	= ARRAY_SIZE(sun20i_d1_pinctrl_functions),
++	.first_bank	= SUNXI_GPIO_A,
++	.num_banks	= 7,
++};
++
+ static const struct sunxi_pinctrl_function sun50i_a64_pinctrl_functions[] = {
+ 	{ "emac",	4 },	/* PD8-PD23 */
+ 	{ "gpio_in",	0 },
+@@ -849,6 +874,12 @@ static const struct udevice_id sunxi_pin
+ 		.data = (ulong)&sun9i_a80_r_pinctrl_desc,
+ 	},
+ #endif
++#ifdef CONFIG_PINCTRL_SUN20I_D1
++	{
++		.compatible = "allwinner,sun20i-d1-pinctrl",
++		.data = (ulong)&sun20i_d1_pinctrl_desc,
++	},
++#endif
+ #ifdef CONFIG_PINCTRL_SUN50I_A64
+ 	{
+ 		.compatible = "allwinner,sun50i-a64-pinctrl",
diff --git a/package/boot/uboot-d1/patches/0021-serial-ns16550-Enable-clocks-during-probe.patch b/package/boot/uboot-d1/patches/0021-serial-ns16550-Enable-clocks-during-probe.patch
new file mode 100644
index 00000000000000..0e28782287f0b2
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0021-serial-ns16550-Enable-clocks-during-probe.patch
@@ -0,0 +1,34 @@
+From 8fde85b609273f8389178d4c0d066390a0e0773d Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 30 Oct 2022 14:56:10 -0500
+Subject: [PATCH 21/90] serial: ns16550: Enable clocks during probe
+
+If the UART bus or baud clock has a gate, it must be enabled before the
+UART can be used.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/serial/ns16550.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/drivers/serial/ns16550.c
++++ b/drivers/serial/ns16550.c
+@@ -506,6 +506,7 @@ int ns16550_serial_probe(struct udevice
+ 	struct ns16550_plat *plat = dev_get_plat(dev);
+ 	struct ns16550 *const com_port = dev_get_priv(dev);
+ 	struct reset_ctl_bulk reset_bulk;
++	struct clk_bulk clk_bulk;
+ 	fdt_addr_t addr;
+ 	int ret;
+ 
+@@ -524,6 +525,10 @@ int ns16550_serial_probe(struct udevice
+ 	if (!ret)
+ 		reset_deassert_bulk(&reset_bulk);
+ 
++	ret = clk_get_bulk(dev, &clk_bulk);
++	if (!ret)
++		clk_enable_bulk(&clk_bulk);
++
+ 	com_port->plat = dev_get_plat(dev);
+ 	ns16550_init(com_port, -1);
+ 
diff --git a/package/boot/uboot-d1/patches/0022-fdt-Fix-bounds-check-in-devfdt_get_addr_index.patch b/package/boot/uboot-d1/patches/0022-fdt-Fix-bounds-check-in-devfdt_get_addr_index.patch
new file mode 100644
index 00000000000000..88d4d670faf04a
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0022-fdt-Fix-bounds-check-in-devfdt_get_addr_index.patch
@@ -0,0 +1,28 @@
+From 0e4edc3a01f179337bb0bd0d31855dbce338a23e Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 30 Oct 2022 14:53:45 -0500
+Subject: [PATCH 22/90] fdt: Fix bounds check in devfdt_get_addr_index
+
+reg must contain enough cells for the entire next address/size pair
+after skipping `index` pairs. The previous code allows an out-of-bounds
+read when na + ns > 1.
+
+Series-to: Simon Glass <sjg@chromium.org>
+
+Fixes: 69b41388ba45 ("dm: core: Add a new api to get indexed device address")
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/core/fdtaddr.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/core/fdtaddr.c
++++ b/drivers/core/fdtaddr.c
+@@ -43,7 +43,7 @@ fdt_addr_t devfdt_get_addr_index(const s
+ 		}
+ 
+ 		reg = fdt_getprop(gd->fdt_blob, offset, "reg", &len);
+-		if (!reg || (len <= (index * sizeof(fdt32_t) * (na + ns)))) {
++		if (!reg || (len < ((index + 1) * sizeof(fdt32_t) * (na + ns)))) {
+ 			debug("Req index out of range\n");
+ 			return FDT_ADDR_T_NONE;
+ 		}
diff --git a/package/boot/uboot-d1/patches/0023-Kconfig-Remove-an-impossible-condition.patch b/package/boot/uboot-d1/patches/0023-Kconfig-Remove-an-impossible-condition.patch
new file mode 100644
index 00000000000000..285fd1e04042a9
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0023-Kconfig-Remove-an-impossible-condition.patch
@@ -0,0 +1,25 @@
+From 2d85df851c590b454749ac989a778bb226637bfc Mon Sep 17 00:00:00 2001
+From: Zoltan HERPAI <wigyori@uid0.hu>
+Date: Tue, 6 Jun 2023 15:08:39 +0000
+Subject: [PATCH 23/90] Kconfig: Remove an impossible condition
+
+ARCH_SUNXI selects BINMAN, so the condition "!BINMAN && ARCH_SUNXI"
+is impossible to satisfy.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
+---
+ Kconfig | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/Kconfig
++++ b/Kconfig
+@@ -459,7 +459,7 @@ config BUILD_TARGET
+ 	default "u-boot-with-spl.kwb" if ARCH_MVEBU && SPL
+ 	default "u-boot-elf.srec" if RCAR_GEN3
+ 	default "u-boot.itb" if !BINMAN && SPL_LOAD_FIT && (ARCH_ROCKCHIP || \
+-				ARCH_SUNXI || RISCV || ARCH_ZYNQMP)
++				RISCV || ARCH_ZYNQMP)
+ 	default "u-boot.kwb" if ARCH_KIRKWOOD
+ 	default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
+ 	default "u-boot-with-spl.imx" if ARCH_MX6 && SPL
diff --git a/package/boot/uboot-d1/patches/0024-binman-Prevent-entries-in-a-section-from-overlapping.patch b/package/boot/uboot-d1/patches/0024-binman-Prevent-entries-in-a-section-from-overlapping.patch
new file mode 100644
index 00000000000000..2a7e544a7f4a6d
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0024-binman-Prevent-entries-in-a-section-from-overlapping.patch
@@ -0,0 +1,33 @@
+From b7150f7dd885012868c94b29ac4fe6152c065a95 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 9 Oct 2021 10:43:56 -0500
+Subject: [PATCH 24/90] binman: Prevent entries in a section from overlapping
+
+Currently, if the "offset" property is given for an entry, the section's
+running offset is completely ignored. This causes entries to overlap if
+the provided offset is less than the size of the entries earlier in the
+section. Avoid the overlap by only using the provided offset when it is
+greater than the running offset.
+
+The motivation for this change is the rule used by SPL to find U-Boot on
+sunxi boards: U-Boot starts 32 KiB after the start of SPL, unless SPL is
+larger than 32 KiB, in which case U-Boot immediately follows SPL.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ tools/binman/entry.py | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+--- a/tools/binman/entry.py
++++ b/tools/binman/entry.py
+@@ -483,7 +483,9 @@ class Entry(object):
+             if self.offset_unset:
+                 self.Raise('No offset set with offset-unset: should another '
+                            'entry provide this correct offset?')
+-            self.offset = tools.align(offset, self.align)
++        elif self.offset > offset:
++            offset = self.offset
++        self.offset = tools.align(offset, self.align)
+         needed = self.pad_before + self.contents_size + self.pad_after
+         needed = tools.align(needed, self.align_size)
+         size = self.size
diff --git a/package/boot/uboot-d1/patches/0025-sunxi-binman-Enable-SPL-FIT-loading-for-32-bit-SoCs.patch b/package/boot/uboot-d1/patches/0025-sunxi-binman-Enable-SPL-FIT-loading-for-32-bit-SoCs.patch
new file mode 100644
index 00000000000000..7deee7a4691254
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0025-sunxi-binman-Enable-SPL-FIT-loading-for-32-bit-SoCs.patch
@@ -0,0 +1,192 @@
+From b641ca5f4d272b83ef77ebcf5c75678cf139c69a Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 17 Apr 2021 13:33:54 -0500
+Subject: [PATCH 25/90] sunxi: binman: Enable SPL FIT loading for 32-bit SoCs
+
+Now that Crust (SCP firmware) has support for H3, we need a FIT image to
+load it. H3 also needs to load a SoC-specific eGon blob to support CPU 0
+hotplug. Let's first enable FIT support before adding extra firmware.
+
+Update the binman description to work on either 32-bit or 64-bit SoCs:
+ - Make BL31 optional, since it is not used on 32-bit SoCs (though BL32
+   may be used in the future).
+ - Explicitly set the minimum offset of the FIT to 32 KiB, since SPL on
+   some boards is still only 24 KiB large even with FIT support enabled.
+   CONFIG_SPL_PAD_TO cannot be used because it is not defined for H616.
+
+FIT unlocks more features (signatures, multiple DTBs, etc.), so enable
+it by default. A10 (sun4i) only has 24 KiB of SRAM A1, so it needs
+SPL_FIT_IMAGE_TINY. For simplicity, enable that option everywhere.
+
+Cover-letter:
+sunxi: SPL FIT support for 32-bit sunxi SoCs
+This series makes the necessary changes so 32-bit sunxi SoCs can load
+additional device trees or firmware from SPL along with U-Boot proper.
+
+There was no existing binman entry property that put the FIT at the
+right offset. The minimum offset is 32k, but this matches neither the
+SPL size (which is no more than 24k on some SoCs) nor the FIT alignment
+(which is 512 bytes in practice due to SPL size constraints). So instead
+of adding a new property, I fixed what is arguably a bug in the offset
+property -- though this strategy will not work if someone is
+intentionally creating overlapping entries.
+END
+Series-to: sunxi
+Series-to: sjg
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm/Kconfig               |  1 +
+ arch/arm/dts/sunxi-u-boot.dtsi | 46 ++++++++++++++++++++++------------
+ common/spl/Kconfig             |  9 +++----
+ 3 files changed, 35 insertions(+), 21 deletions(-)
+
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -1135,6 +1135,7 @@ config ARCH_SUNXI
+ 	imply SPL_GPIO
+ 	imply SPL_LIBCOMMON_SUPPORT
+ 	imply SPL_LIBGENERIC_SUPPORT
++	imply SPL_LOAD_FIT
+ 	imply SPL_MMC if MMC
+ 	imply SPL_POWER
+ 	imply SPL_SERIAL
+--- a/arch/arm/dts/sunxi-u-boot.dtsi
++++ b/arch/arm/dts/sunxi-u-boot.dtsi
+@@ -1,13 +1,19 @@
+ #include <config.h>
+ 
+-#ifdef CONFIG_MACH_SUN50I_H6
+-#define BL31_ADDR 0x104000
+-#define  SCP_ADDR 0x114000
+-#elif defined(CONFIG_MACH_SUN50I_H616)
+-#define BL31_ADDR 0x40000000
++#ifdef CONFIG_ARM64
++#define ARCH "arm64"
+ #else
+-#define BL31_ADDR  0x44000
+-#define  SCP_ADDR  0x50000
++#define ARCH "arm"
++#endif
++
++#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN50I_H5)
++#define BL31_ADDR	0x00044000
++#define SCP_ADDR	0x00050000
++#elif defined(CONFIG_MACH_SUN50I_H6)
++#define BL31_ADDR	0x00104000
++#define SCP_ADDR	0x00114000
++#elif defined(CONFIG_MACH_SUN50I_H616)
++#define BL31_ADDR	0x40000000
+ #endif
+ 
+ / {
+@@ -34,30 +40,33 @@
+ 			filename = "spl/sunxi-spl.bin";
+ 		};
+ 
+-#ifdef CONFIG_ARM64
++#ifdef CONFIG_SPL_LOAD_FIT
+ 		fit {
+-			description = "Configuration to load ATF before U-Boot";
++			description = "Configuration to load U-Boot and firmware";
++			offset = <32768>;
+ 			#address-cells = <1>;
+ 			fit,fdt-list = "of-list";
+ 
+ 			images {
+ 				uboot {
+-					description = "U-Boot (64-bit)";
++					description = "U-Boot";
+ 					type = "standalone";
+ 					os = "u-boot";
+-					arch = "arm64";
++					arch = ARCH;
+ 					compression = "none";
+ 					load = <CONFIG_TEXT_BASE>;
++					entry = <CONFIG_TEXT_BASE>;
+ 
+ 					u-boot-nodtb {
+ 					};
+ 				};
+ 
++#ifdef BL31_ADDR
+ 				atf {
+ 					description = "ARM Trusted Firmware";
+ 					type = "firmware";
+ 					os = "arm-trusted-firmware";
+-					arch = "arm64";
++					arch = ARCH;
+ 					compression = "none";
+ 					load = <BL31_ADDR>;
+ 					entry = <BL31_ADDR>;
+@@ -67,6 +76,7 @@
+ 						missing-msg = "atf-bl31-sunxi";
+ 					};
+ 				};
++#endif
+ 
+ #ifdef SCP_ADDR
+ 				scp {
+@@ -95,19 +105,23 @@
+ 
+ 				@config-SEQ {
+ 					description = "NAME";
++#ifdef BL31_ADDR
+ 					firmware = "atf";
+-#ifndef SCP_ADDR
+-					loadables = "uboot";
+ #else
+-					loadables = "scp", "uboot";
++					firmware = "uboot";
++#endif
++					loadables =
++#ifdef SCP_ADDR
++						    "scp",
+ #endif
++						    "uboot";
+ 					fdt = "fdt-SEQ";
+ 				};
+ 			};
+ 		};
+ #else
+ 		u-boot-img {
+-			offset = <CONFIG_SPL_PAD_TO>;
++			offset = <32768>;
+ 		};
+ #endif
+ 	};
+--- a/common/spl/Kconfig
++++ b/common/spl/Kconfig
+@@ -76,12 +76,12 @@ config SPL_SIZE_LIMIT_PROVIDE_STACK
+ 
+ config SPL_MAX_SIZE
+ 	hex "Maximum size of the SPL image, excluding BSS"
++	default 0x37fa0 if MACH_SUN50I_H616
+ 	default 0x30000 if ARCH_MX6 && MX6_OCRAM_256KB
++	default 0x25fa0 if MACH_SUN50I_H6
+ 	default 0x1b000 if AM33XX && !TI_SECURE_DEVICE
+ 	default 0x10000 if ARCH_MX6 && !MX6_OCRAM_256KB
+ 	default 0x7fa0 if SUNXI_SRAM_ADDRESS = 0x10000
+-	default 0x7fa0 if SUNXI_SRAM_ADDRESS = 0x20000 && !MACH_SUN50I_H616
+-	default 0xbfa0 if MACH_SUN50I_H616
+ 	default 0x7000 if RCAR_GEN3
+ 	default 0x5fa0 if SUNXI_SRAM_ADDRESS = 0x0
+ 	default 0x10000 if ASPEED_AST2600
+@@ -97,7 +97,7 @@ config SPL_PAD_TO
+ 	default 0x31000 if ARCH_MX6 && MX6_OCRAM_256KB
+ 	default 0x11000 if ARCH_MX7 || (ARCH_MX6 && !MX6_OCRAM_256KB)
+ 	default 0x10000 if ARCH_KEYSTONE
+-	default 0x8000 if ARCH_SUNXI && !MACH_SUN50I_H616
++	default 0x0 if ARCH_SUNXI
+ 	default 0x0 if ARCH_MTMIPS
+ 	default TPL_MAX_SIZE if TPL_MAX_SIZE > SPL_MAX_SIZE
+ 	default SPL_MAX_SIZE
+@@ -575,8 +575,7 @@ config SPL_MD5
+ config SPL_FIT_IMAGE_TINY
+ 	bool "Remove functionality from SPL FIT loading to reduce size"
+ 	depends on SPL_FIT
+-	default y if MACH_SUN50I || MACH_SUN50I_H5 || SUN50I_GEN_H6
+-	default y if ARCH_IMX8M || ARCH_IMX9
++	default y if ARCH_IMX8M || ARCH_IMX9 || ARCH_SUNXI
+ 	help
+ 	  Enable this to reduce the size of the FIT image loading code
+ 	  in SPL, if space for the SPL binary is very tight.
diff --git a/package/boot/uboot-d1/patches/0026-sunxi-psci-Avoid-hanging-when-CPU-0-is-hot-unplugged.patch b/package/boot/uboot-d1/patches/0026-sunxi-psci-Avoid-hanging-when-CPU-0-is-hot-unplugged.patch
new file mode 100644
index 00000000000000..e440351b0abecc
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0026-sunxi-psci-Avoid-hanging-when-CPU-0-is-hot-unplugged.patch
@@ -0,0 +1,51 @@
+From ca1e6f4491981432c3e88441131c8e25067da95e Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 9 Oct 2021 22:00:22 -0500
+Subject: [PATCH 26/90] sunxi: psci: Avoid hanging when CPU 0 is hot-unplugged
+
+Do not try to send an SGI from CPU 0 to itself. Since FIQs are masked
+when entering monitor mode, this will hang. Plus, CPU 0 cannot fully
+power itself off anyway. Instead, have it turn FIQs back on and continue
+servicing SGIs from other cores.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm/cpu/armv7/sunxi/psci.c | 20 +++++++++++++++++---
+ 1 file changed, 17 insertions(+), 3 deletions(-)
+
+--- a/arch/arm/cpu/armv7/sunxi/psci.c
++++ b/arch/arm/cpu/armv7/sunxi/psci.c
+@@ -38,6 +38,15 @@
+ #define SUN8I_R40_PWR_CLAMP(cpu)		(0x120 + (cpu) * 0x4)
+ #define SUN8I_R40_SRAMC_SOFT_ENTRY_REG0		(0xbc)
+ 
++static inline u32 __secure cp15_read_mpidr(void)
++{
++	u32 val;
++
++	asm volatile ("mrc p15, 0, %0, c0, c0, 5" : "=r" (val));
++
++	return val;
++}
++
+ static void __secure cp15_write_cntp_tval(u32 tval)
+ {
+ 	asm volatile ("mcr p15, 0, %0, c14, c2, 0" : : "r" (tval));
+@@ -281,9 +290,14 @@ s32 __secure psci_cpu_off(void)
+ {
+ 	psci_cpu_off_common();
+ 
+-	/* Ask CPU0 via SGI15 to pull the rug... */
+-	writel(BIT(16) | 15, GICD_BASE + GICD_SGIR);
+-	dsb();
++	if (cp15_read_mpidr() & 3) {
++		/* Ask CPU0 via SGI15 to pull the rug... */
++		writel(BIT(16) | 15, GICD_BASE + GICD_SGIR);
++		dsb();
++	} else {
++		/* Unmask FIQs to service SGI15. */
++		asm volatile ("cpsie f");
++	}
+ 
+ 	/* Wait to be turned off */
+ 	while (1)
diff --git a/package/boot/uboot-d1/patches/0027-clk-sunxi-Add-NAND-clocks-and-resets.patch b/package/boot/uboot-d1/patches/0027-clk-sunxi-Add-NAND-clocks-and-resets.patch
new file mode 100644
index 00000000000000..157c3cd4a25309
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0027-clk-sunxi-Add-NAND-clocks-and-resets.patch
@@ -0,0 +1,295 @@
+From 2f48dfc23d612f6f1798ff761854fd3141d0671f Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 15 May 2022 21:29:22 -0500
+Subject: [PATCH 27/90] clk: sunxi: Add NAND clocks and resets
+
+Currently NAND clock setup is done in board code, both in SPL and in
+U-Boot proper. Add the NAND clocks/resets here so they can be used by
+the "full" NAND driver once it is converted to the driver model.
+
+The bit locations are copied from the Linux CCU drivers.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/clk/sunxi/clk_a10.c  | 2 ++
+ drivers/clk/sunxi/clk_a10s.c | 2 ++
+ drivers/clk/sunxi/clk_a23.c  | 3 +++
+ drivers/clk/sunxi/clk_a31.c  | 6 ++++++
+ drivers/clk/sunxi/clk_a64.c  | 3 +++
+ drivers/clk/sunxi/clk_a80.c  | 8 ++++++++
+ drivers/clk/sunxi/clk_a83t.c | 3 +++
+ drivers/clk/sunxi/clk_h3.c   | 3 +++
+ drivers/clk/sunxi/clk_h6.c   | 6 ++++++
+ drivers/clk/sunxi/clk_h616.c | 6 ++++++
+ drivers/clk/sunxi/clk_r40.c  | 3 +++
+ 11 files changed, 45 insertions(+)
+
+--- a/drivers/clk/sunxi/clk_a10.c
++++ b/drivers/clk/sunxi/clk_a10.c
+@@ -23,6 +23,7 @@ static struct ccu_clk_gate a10_gates[] =
+ 	[CLK_AHB_MMC1]		= GATE(0x060, BIT(9)),
+ 	[CLK_AHB_MMC2]		= GATE(0x060, BIT(10)),
+ 	[CLK_AHB_MMC3]		= GATE(0x060, BIT(11)),
++	[CLK_AHB_NAND]		= GATE(0x060, BIT(13)),
+ 	[CLK_AHB_EMAC]		= GATE(0x060, BIT(17)),
+ 	[CLK_AHB_SPI0]		= GATE(0x060, BIT(20)),
+ 	[CLK_AHB_SPI1]		= GATE(0x060, BIT(21)),
+@@ -47,6 +48,7 @@ static struct ccu_clk_gate a10_gates[] =
+ 	[CLK_APB1_UART6]	= GATE(0x06c, BIT(22)),
+ 	[CLK_APB1_UART7]	= GATE(0x06c, BIT(23)),
+ 
++	[CLK_NAND]		= GATE(0x080, BIT(31)),
+ 	[CLK_SPI0]		= GATE(0x0a0, BIT(31)),
+ 	[CLK_SPI1]		= GATE(0x0a4, BIT(31)),
+ 	[CLK_SPI2]		= GATE(0x0a8, BIT(31)),
+--- a/drivers/clk/sunxi/clk_a10s.c
++++ b/drivers/clk/sunxi/clk_a10s.c
+@@ -20,6 +20,7 @@ static struct ccu_clk_gate a10s_gates[]
+ 	[CLK_AHB_MMC0]		= GATE(0x060, BIT(8)),
+ 	[CLK_AHB_MMC1]		= GATE(0x060, BIT(9)),
+ 	[CLK_AHB_MMC2]		= GATE(0x060, BIT(10)),
++	[CLK_AHB_NAND]		= GATE(0x060, BIT(13)),
+ 	[CLK_AHB_EMAC]		= GATE(0x060, BIT(17)),
+ 	[CLK_AHB_SPI0]		= GATE(0x060, BIT(20)),
+ 	[CLK_AHB_SPI1]		= GATE(0x060, BIT(21)),
+@@ -35,6 +36,7 @@ static struct ccu_clk_gate a10s_gates[]
+ 	[CLK_APB1_UART2]	= GATE(0x06c, BIT(18)),
+ 	[CLK_APB1_UART3]	= GATE(0x06c, BIT(19)),
+ 
++	[CLK_NAND]		= GATE(0x080, BIT(31)),
+ 	[CLK_SPI0]		= GATE(0x0a0, BIT(31)),
+ 	[CLK_SPI1]		= GATE(0x0a4, BIT(31)),
+ 	[CLK_SPI2]		= GATE(0x0a8, BIT(31)),
+--- a/drivers/clk/sunxi/clk_a23.c
++++ b/drivers/clk/sunxi/clk_a23.c
+@@ -17,6 +17,7 @@ static struct ccu_clk_gate a23_gates[] =
+ 	[CLK_BUS_MMC0]		= GATE(0x060, BIT(8)),
+ 	[CLK_BUS_MMC1]		= GATE(0x060, BIT(9)),
+ 	[CLK_BUS_MMC2]		= GATE(0x060, BIT(10)),
++	[CLK_BUS_NAND]		= GATE(0x060, BIT(13)),
+ 	[CLK_BUS_SPI0]		= GATE(0x060, BIT(20)),
+ 	[CLK_BUS_SPI1]		= GATE(0x060, BIT(21)),
+ 	[CLK_BUS_OTG]		= GATE(0x060, BIT(24)),
+@@ -34,6 +35,7 @@ static struct ccu_clk_gate a23_gates[] =
+ 	[CLK_BUS_UART3]		= GATE(0x06c, BIT(19)),
+ 	[CLK_BUS_UART4]		= GATE(0x06c, BIT(20)),
+ 
++	[CLK_NAND]		= GATE(0x080, BIT(31)),
+ 	[CLK_SPI0]		= GATE(0x0a0, BIT(31)),
+ 	[CLK_SPI1]		= GATE(0x0a4, BIT(31)),
+ 
+@@ -52,6 +54,7 @@ static struct ccu_reset a23_resets[] = {
+ 	[RST_BUS_MMC0]		= RESET(0x2c0, BIT(8)),
+ 	[RST_BUS_MMC1]		= RESET(0x2c0, BIT(9)),
+ 	[RST_BUS_MMC2]		= RESET(0x2c0, BIT(10)),
++	[RST_BUS_NAND]		= RESET(0x2c0, BIT(13)),
+ 	[RST_BUS_SPI0]		= RESET(0x2c0, BIT(20)),
+ 	[RST_BUS_SPI1]		= RESET(0x2c0, BIT(21)),
+ 	[RST_BUS_OTG]		= RESET(0x2c0, BIT(24)),
+--- a/drivers/clk/sunxi/clk_a31.c
++++ b/drivers/clk/sunxi/clk_a31.c
+@@ -18,6 +18,8 @@ static struct ccu_clk_gate a31_gates[] =
+ 	[CLK_AHB1_MMC1]		= GATE(0x060, BIT(9)),
+ 	[CLK_AHB1_MMC2]		= GATE(0x060, BIT(10)),
+ 	[CLK_AHB1_MMC3]		= GATE(0x060, BIT(11)),
++	[CLK_AHB1_NAND1]	= GATE(0x060, BIT(12)),
++	[CLK_AHB1_NAND0]	= GATE(0x060, BIT(13)),
+ 	[CLK_AHB1_EMAC]		= GATE(0x060, BIT(17)),
+ 	[CLK_AHB1_SPI0]		= GATE(0x060, BIT(20)),
+ 	[CLK_AHB1_SPI1]		= GATE(0x060, BIT(21)),
+@@ -43,6 +45,8 @@ static struct ccu_clk_gate a31_gates[] =
+ 	[CLK_APB2_UART4]	= GATE(0x06c, BIT(20)),
+ 	[CLK_APB2_UART5]	= GATE(0x06c, BIT(21)),
+ 
++	[CLK_NAND0]		= GATE(0x080, BIT(31)),
++	[CLK_NAND1]		= GATE(0x084, BIT(31)),
+ 	[CLK_SPI0]		= GATE(0x0a0, BIT(31)),
+ 	[CLK_SPI1]		= GATE(0x0a4, BIT(31)),
+ 	[CLK_SPI2]		= GATE(0x0a8, BIT(31)),
+@@ -65,6 +69,8 @@ static struct ccu_reset a31_resets[] = {
+ 	[RST_AHB1_MMC1]		= RESET(0x2c0, BIT(9)),
+ 	[RST_AHB1_MMC2]		= RESET(0x2c0, BIT(10)),
+ 	[RST_AHB1_MMC3]		= RESET(0x2c0, BIT(11)),
++	[RST_AHB1_NAND1]	= RESET(0x2c0, BIT(12)),
++	[RST_AHB1_NAND0]	= RESET(0x2c0, BIT(13)),
+ 	[RST_AHB1_EMAC]		= RESET(0x2c0, BIT(17)),
+ 	[RST_AHB1_SPI0]		= RESET(0x2c0, BIT(20)),
+ 	[RST_AHB1_SPI1]		= RESET(0x2c0, BIT(21)),
+--- a/drivers/clk/sunxi/clk_a64.c
++++ b/drivers/clk/sunxi/clk_a64.c
+@@ -19,6 +19,7 @@ static const struct ccu_clk_gate a64_gat
+ 	[CLK_BUS_MMC0]		= GATE(0x060, BIT(8)),
+ 	[CLK_BUS_MMC1]		= GATE(0x060, BIT(9)),
+ 	[CLK_BUS_MMC2]		= GATE(0x060, BIT(10)),
++	[CLK_BUS_NAND]		= GATE(0x060, BIT(13)),
+ 	[CLK_BUS_EMAC]		= GATE(0x060, BIT(17)),
+ 	[CLK_BUS_SPI0]		= GATE(0x060, BIT(20)),
+ 	[CLK_BUS_SPI1]		= GATE(0x060, BIT(21)),
+@@ -39,6 +40,7 @@ static const struct ccu_clk_gate a64_gat
+ 	[CLK_BUS_UART3]		= GATE(0x06c, BIT(19)),
+ 	[CLK_BUS_UART4]		= GATE(0x06c, BIT(20)),
+ 
++	[CLK_NAND]		= GATE(0x080, BIT(31)),
+ 	[CLK_SPI0]		= GATE(0x0a0, BIT(31)),
+ 	[CLK_SPI1]		= GATE(0x0a4, BIT(31)),
+ 
+@@ -58,6 +60,7 @@ static const struct ccu_reset a64_resets
+ 	[RST_BUS_MMC0]		= RESET(0x2c0, BIT(8)),
+ 	[RST_BUS_MMC1]		= RESET(0x2c0, BIT(9)),
+ 	[RST_BUS_MMC2]		= RESET(0x2c0, BIT(10)),
++	[RST_BUS_NAND]		= RESET(0x2c0, BIT(13)),
+ 	[RST_BUS_EMAC]		= RESET(0x2c0, BIT(17)),
+ 	[RST_BUS_SPI0]		= RESET(0x2c0, BIT(20)),
+ 	[RST_BUS_SPI1]		= RESET(0x2c0, BIT(21)),
+--- a/drivers/clk/sunxi/clk_a80.c
++++ b/drivers/clk/sunxi/clk_a80.c
+@@ -14,12 +14,18 @@
+ #include <linux/bitops.h>
+ 
+ static const struct ccu_clk_gate a80_gates[] = {
++	[CLK_NAND0_0]		= GATE(0x400, BIT(31)),
++	[CLK_NAND0_1]		= GATE(0x404, BIT(31)),
++	[CLK_NAND1_0]		= GATE(0x408, BIT(31)),
++	[CLK_NAND1_1]		= GATE(0x40c, BIT(31)),
+ 	[CLK_SPI0]		= GATE(0x430, BIT(31)),
+ 	[CLK_SPI1]		= GATE(0x434, BIT(31)),
+ 	[CLK_SPI2]		= GATE(0x438, BIT(31)),
+ 	[CLK_SPI3]		= GATE(0x43c, BIT(31)),
+ 
+ 	[CLK_BUS_MMC]		= GATE(0x580, BIT(8)),
++	[CLK_BUS_NAND0]		= GATE(0x580, BIT(12)),
++	[CLK_BUS_NAND1]		= GATE(0x580, BIT(13)),
+ 	[CLK_BUS_SPI0]		= GATE(0x580, BIT(20)),
+ 	[CLK_BUS_SPI1]		= GATE(0x580, BIT(21)),
+ 	[CLK_BUS_SPI2]		= GATE(0x580, BIT(22)),
+@@ -42,6 +48,8 @@ static const struct ccu_clk_gate a80_gat
+ 
+ static const struct ccu_reset a80_resets[] = {
+ 	[RST_BUS_MMC]		= RESET(0x5a0, BIT(8)),
++	[RST_BUS_NAND0]		= RESET(0x5a0, BIT(12)),
++	[RST_BUS_NAND1]		= RESET(0x5a0, BIT(13)),
+ 	[RST_BUS_SPI0]		= RESET(0x5a0, BIT(20)),
+ 	[RST_BUS_SPI1]		= RESET(0x5a0, BIT(21)),
+ 	[RST_BUS_SPI2]		= RESET(0x5a0, BIT(22)),
+--- a/drivers/clk/sunxi/clk_a83t.c
++++ b/drivers/clk/sunxi/clk_a83t.c
+@@ -17,6 +17,7 @@ static struct ccu_clk_gate a83t_gates[]
+ 	[CLK_BUS_MMC0]		= GATE(0x060, BIT(8)),
+ 	[CLK_BUS_MMC1]		= GATE(0x060, BIT(9)),
+ 	[CLK_BUS_MMC2]		= GATE(0x060, BIT(10)),
++	[CLK_BUS_NAND]		= GATE(0x060, BIT(13)),
+ 	[CLK_BUS_EMAC]		= GATE(0x060, BIT(17)),
+ 	[CLK_BUS_SPI0]		= GATE(0x060, BIT(20)),
+ 	[CLK_BUS_SPI1]		= GATE(0x060, BIT(21)),
+@@ -36,6 +37,7 @@ static struct ccu_clk_gate a83t_gates[]
+ 	[CLK_BUS_UART3]		= GATE(0x06c, BIT(19)),
+ 	[CLK_BUS_UART4]		= GATE(0x06c, BIT(20)),
+ 
++	[CLK_NAND]		= GATE(0x080, BIT(31)),
+ 	[CLK_SPI0]		= GATE(0x0a0, BIT(31)),
+ 	[CLK_SPI1]		= GATE(0x0a4, BIT(31)),
+ 
+@@ -54,6 +56,7 @@ static struct ccu_reset a83t_resets[] =
+ 	[RST_BUS_MMC0]		= RESET(0x2c0, BIT(8)),
+ 	[RST_BUS_MMC1]		= RESET(0x2c0, BIT(9)),
+ 	[RST_BUS_MMC2]		= RESET(0x2c0, BIT(10)),
++	[RST_BUS_NAND]		= RESET(0x2c0, BIT(13)),
+ 	[RST_BUS_EMAC]		= RESET(0x2c0, BIT(17)),
+ 	[RST_BUS_SPI0]		= RESET(0x2c0, BIT(20)),
+ 	[RST_BUS_SPI1]		= RESET(0x2c0, BIT(21)),
+--- a/drivers/clk/sunxi/clk_h3.c
++++ b/drivers/clk/sunxi/clk_h3.c
+@@ -19,6 +19,7 @@ static struct ccu_clk_gate h3_gates[] =
+ 	[CLK_BUS_MMC0]		= GATE(0x060, BIT(8)),
+ 	[CLK_BUS_MMC1]		= GATE(0x060, BIT(9)),
+ 	[CLK_BUS_MMC2]		= GATE(0x060, BIT(10)),
++	[CLK_BUS_NAND]		= GATE(0x060, BIT(13)),
+ 	[CLK_BUS_EMAC]		= GATE(0x060, BIT(17)),
+ 	[CLK_BUS_SPI0]		= GATE(0x060, BIT(20)),
+ 	[CLK_BUS_SPI1]		= GATE(0x060, BIT(21)),
+@@ -44,6 +45,7 @@ static struct ccu_clk_gate h3_gates[] =
+ 
+ 	[CLK_BUS_EPHY]		= GATE(0x070, BIT(0)),
+ 
++	[CLK_NAND]		= GATE(0x080, BIT(31)),
+ 	[CLK_SPI0]		= GATE(0x0a0, BIT(31)),
+ 	[CLK_SPI1]		= GATE(0x0a4, BIT(31)),
+ 
+@@ -66,6 +68,7 @@ static struct ccu_reset h3_resets[] = {
+ 	[RST_BUS_MMC0]		= RESET(0x2c0, BIT(8)),
+ 	[RST_BUS_MMC1]		= RESET(0x2c0, BIT(9)),
+ 	[RST_BUS_MMC2]		= RESET(0x2c0, BIT(10)),
++	[RST_BUS_NAND]		= RESET(0x2c0, BIT(13)),
+ 	[RST_BUS_EMAC]		= RESET(0x2c0, BIT(17)),
+ 	[RST_BUS_SPI0]		= RESET(0x2c0, BIT(20)),
+ 	[RST_BUS_SPI1]		= RESET(0x2c0, BIT(21)),
+--- a/drivers/clk/sunxi/clk_h6.c
++++ b/drivers/clk/sunxi/clk_h6.c
+@@ -18,6 +18,10 @@ static struct ccu_clk_gate h6_gates[] =
+ 
+ 	[CLK_APB1]		= GATE_DUMMY,
+ 
++	[CLK_NAND0]		= GATE(0x810, BIT(31)),
++	[CLK_NAND1]		= GATE(0x814, BIT(31)),
++	[CLK_BUS_NAND]		= GATE(0x82c, BIT(0)),
++
+ 	[CLK_BUS_MMC0]		= GATE(0x84c, BIT(0)),
+ 	[CLK_BUS_MMC1]		= GATE(0x84c, BIT(1)),
+ 	[CLK_BUS_MMC2]		= GATE(0x84c, BIT(2)),
+@@ -58,6 +62,8 @@ static struct ccu_clk_gate h6_gates[] =
+ };
+ 
+ static struct ccu_reset h6_resets[] = {
++	[RST_BUS_NAND]		= RESET(0x82c, BIT(16)),
++
+ 	[RST_BUS_MMC0]		= RESET(0x84c, BIT(16)),
+ 	[RST_BUS_MMC1]		= RESET(0x84c, BIT(17)),
+ 	[RST_BUS_MMC2]		= RESET(0x84c, BIT(18)),
+--- a/drivers/clk/sunxi/clk_h616.c
++++ b/drivers/clk/sunxi/clk_h616.c
+@@ -17,6 +17,10 @@ static struct ccu_clk_gate h616_gates[]
+ 
+ 	[CLK_APB1]		= GATE_DUMMY,
+ 
++	[CLK_NAND0]		= GATE(0x810, BIT(31)),
++	[CLK_NAND1]		= GATE(0x814, BIT(31)),
++	[CLK_BUS_NAND]		= GATE(0x82c, BIT(0)),
++
+ 	[CLK_BUS_MMC0]		= GATE(0x84c, BIT(0)),
+ 	[CLK_BUS_MMC1]		= GATE(0x84c, BIT(1)),
+ 	[CLK_BUS_MMC2]		= GATE(0x84c, BIT(2)),
+@@ -67,6 +71,8 @@ static struct ccu_clk_gate h616_gates[]
+ };
+ 
+ static struct ccu_reset h616_resets[] = {
++	[RST_BUS_NAND]		= RESET(0x82c, BIT(16)),
++
+ 	[RST_BUS_MMC0]		= RESET(0x84c, BIT(16)),
+ 	[RST_BUS_MMC1]		= RESET(0x84c, BIT(17)),
+ 	[RST_BUS_MMC2]		= RESET(0x84c, BIT(18)),
+--- a/drivers/clk/sunxi/clk_r40.c
++++ b/drivers/clk/sunxi/clk_r40.c
+@@ -18,6 +18,7 @@ static struct ccu_clk_gate r40_gates[] =
+ 	[CLK_BUS_MMC1]		= GATE(0x060, BIT(9)),
+ 	[CLK_BUS_MMC2]		= GATE(0x060, BIT(10)),
+ 	[CLK_BUS_MMC3]		= GATE(0x060, BIT(11)),
++	[CLK_BUS_NAND]		= GATE(0x060, BIT(13)),
+ 	[CLK_BUS_SPI0]		= GATE(0x060, BIT(20)),
+ 	[CLK_BUS_SPI1]		= GATE(0x060, BIT(21)),
+ 	[CLK_BUS_SPI2]		= GATE(0x060, BIT(22)),
+@@ -48,6 +49,7 @@ static struct ccu_clk_gate r40_gates[] =
+ 	[CLK_BUS_UART6]		= GATE(0x06c, BIT(22)),
+ 	[CLK_BUS_UART7]		= GATE(0x06c, BIT(23)),
+ 
++	[CLK_NAND]		= GATE(0x080, BIT(31)),
+ 	[CLK_SPI0]		= GATE(0x0a0, BIT(31)),
+ 	[CLK_SPI1]		= GATE(0x0a4, BIT(31)),
+ 	[CLK_SPI2]		= GATE(0x0a8, BIT(31)),
+@@ -70,6 +72,7 @@ static struct ccu_reset r40_resets[] = {
+ 	[RST_BUS_MMC1]		= RESET(0x2c0, BIT(9)),
+ 	[RST_BUS_MMC2]		= RESET(0x2c0, BIT(10)),
+ 	[RST_BUS_MMC3]		= RESET(0x2c0, BIT(11)),
++	[RST_BUS_NAND]		= RESET(0x2c0, BIT(13)),
+ 	[RST_BUS_SPI0]		= RESET(0x2c0, BIT(20)),
+ 	[RST_BUS_SPI1]		= RESET(0x2c0, BIT(21)),
+ 	[RST_BUS_SPI2]		= RESET(0x2c0, BIT(22)),
diff --git a/package/boot/uboot-d1/patches/0028-pinctrl-sunxi-Add-NAND-pinmuxes.patch b/package/boot/uboot-d1/patches/0028-pinctrl-sunxi-Add-NAND-pinmuxes.patch
new file mode 100644
index 00000000000000..6ecba35890db80
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0028-pinctrl-sunxi-Add-NAND-pinmuxes.patch
@@ -0,0 +1,120 @@
+From 7be2405244565973cff0a40196bbed08df90f6a3 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Mon, 16 May 2022 00:31:36 -0500
+Subject: [PATCH 28/90] pinctrl: sunxi: Add NAND pinmuxes
+
+NAND is always at function 2 on port C.
+
+Pin lists and mux values were taken from the Linux drivers.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/pinctrl/sunxi/pinctrl-sunxi.c | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
++++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+@@ -269,6 +269,7 @@ static const struct sunxi_pinctrl_functi
+ #endif
+ 	{ "mmc2",	3 },	/* PC6-PC15 */
+ 	{ "mmc3",	2 },	/* PI4-PI9 */
++	{ "nand0",	2 },	/* PC0-PC24 */
+ 	{ "spi0",	3 },	/* PC0-PC2, PC23 */
+ #if IS_ENABLED(CONFIG_UART0_PORT_F)
+ 	{ "uart0",	4 },	/* PF2-PF4 */
+@@ -293,6 +294,7 @@ static const struct sunxi_pinctrl_functi
+ 	{ "mmc0",	2 },	/* PF0-PF5 */
+ 	{ "mmc1",	2 },	/* PG3-PG8 */
+ 	{ "mmc2",	3 },	/* PC6-PC15 */
++	{ "nand0",	2 },	/* PC0-PC19 */
+ 	{ "spi0",	3 },	/* PC0-PC3 */
+ #if IS_ENABLED(CONFIG_UART0_PORT_F)
+ 	{ "uart0",	4 },	/* PF2-PF4 */
+@@ -319,6 +321,7 @@ static const struct sunxi_pinctrl_functi
+ 	{ "mmc1",	2 },	/* PG0-PG5 */
+ 	{ "mmc2",	3 },	/* PC6-PC15, PC24 */
+ 	{ "mmc3",	4 },	/* PC6-PC15, PC24 */
++	{ "nand0",	2 },	/* PC0-PC26 */
+ 	{ "spi0",	3 },	/* PC0-PC2, PC27 */
+ #if IS_ENABLED(CONFIG_UART0_PORT_F)
+ 	{ "uart0",	3 },	/* PF2-PF4 */
+@@ -363,6 +366,7 @@ static const struct sunxi_pinctrl_functi
+ 	{ "mmc1",	4 },	/* PG0-PG5 */
+ #endif
+ 	{ "mmc2",	3 },	/* PC5-PC15, PC24 */
++	{ "nand0",	2 },	/* PC0-PC24 */
+ 	{ "spi0",	3 },	/* PC0-PC2, PC23 */
+ #if IS_ENABLED(CONFIG_UART0_PORT_F)
+ 	{ "uart0",	4 },	/* PF2-PF4 */
+@@ -386,6 +390,7 @@ static const struct sunxi_pinctrl_functi
+ 	{ "mmc0",	2 },	/* PF0-PF5 */
+ 	{ "mmc1",	2 },	/* PG0-PG5 */
+ 	{ "mmc2",	3 },	/* PC5-PC16 */
++	{ "nand0",	2 },	/* PC0-PC16 */
+ 	{ "spi0",	3 },	/* PC0-PC3 */
+ #if IS_ENABLED(CONFIG_UART0_PORT_F)
+ 	{ "uart0",	3 },	/* PF2-PF4 */
+@@ -424,6 +429,7 @@ static const struct sunxi_pinctrl_functi
+ 	{ "mmc0",	2 },	/* PF0-PF5 */
+ 	{ "mmc1",	2 },	/* PG0-PG5 */
+ 	{ "mmc2",	3 },	/* PC5-PC16 */
++	{ "nand0",	2 },	/* PC0-PC16 */
+ 	{ "spi0",	3 },	/* PC0-PC3 */
+ #if IS_ENABLED(CONFIG_UART0_PORT_F)
+ 	{ "uart0",	3 },	/* PF2-PF4 */
+@@ -450,6 +456,7 @@ static const struct sunxi_pinctrl_functi
+ 	{ "mmc0",	2 },	/* PF0-PF5 */
+ 	{ "mmc1",	2 },	/* PG0-PG5 */
+ 	{ "mmc2",	3 },	/* PC5-PC16 */
++	{ "nand0",	2 },	/* PC0-PC18 */
+ 	{ "spi0",	3 },	/* PC0-PC3 */
+ #if IS_ENABLED(CONFIG_UART0_PORT_F)
+ 	{ "uart0",	3 },	/* PF2-PF4 */
+@@ -491,6 +498,7 @@ static const struct sunxi_pinctrl_functi
+ 	{ "mmc0",	2 },	/* PF0-PF5 */
+ 	{ "mmc1",	2 },	/* PG0-PG5 */
+ 	{ "mmc2",	3 },	/* PC5-PC16 */
++	{ "nand0",	2 },	/* PC0-PC16 */
+ 	{ "spi0",	3 },	/* PC0-PC3 */
+ #if IS_ENABLED(CONFIG_UART0_PORT_F)
+ 	{ "uart0",	3 },	/* PF2-PF4 */
+@@ -557,6 +565,7 @@ static const struct sunxi_pinctrl_functi
+ 	{ "mmc0",	2 },	/* PF0-PF5 */
+ 	{ "mmc1",	2 },	/* PG0-PG5 */
+ 	{ "mmc2",	3 },	/* PC6-PC16 */
++	{ "nand0",	2 },	/* PC0-PC18 */
+ 	{ "spi0",	3 },	/* PC0-PC2, PC19 */
+ #if IS_ENABLED(CONFIG_UART0_PORT_F)
+ 	{ "uart0",	4 },	/* PF2-PF4 */
+@@ -622,6 +631,7 @@ static const struct sunxi_pinctrl_functi
+ 	{ "mmc0",	2 },	/* PF0-PF5 */
+ 	{ "mmc1",	2 },	/* PG0-PG5 */
+ 	{ "mmc2",	3 },	/* PC1-PC16 */
++	{ "nand0",	2 },	/* PC0-PC16 */
+ 	{ "pwm",	2 },	/* PD22 */
+ 	{ "spi0",	4 },	/* PC0-PC3 */
+ #if IS_ENABLED(CONFIG_UART0_PORT_F)
+@@ -664,6 +674,7 @@ static const struct sunxi_pinctrl_functi
+ 	{ "mmc0",	2 },	/* PF0-PF5 */
+ 	{ "mmc1",	2 },	/* PG0-PG5 */
+ 	{ "mmc2",	3 },	/* PC1-PC16 */
++	{ "nand0",	2 },	/* PC0-PC16 */
+ 	{ "spi0",	3 },	/* PC0-PC3 */
+ #if IS_ENABLED(CONFIG_UART0_PORT_F)
+ 	{ "uart0",	3 },	/* PF2-PF4 */
+@@ -690,6 +701,7 @@ static const struct sunxi_pinctrl_functi
+ 	{ "mmc0",	2 },	/* PF0-PF5 */
+ 	{ "mmc1",	2 },	/* PG0-PG5 */
+ 	{ "mmc2",	3 },	/* PC1-PC14 */
++	{ "nand0",	2 },	/* PC0-PC16 */
+ 	{ "spi0",	4 },	/* PC0-PC7 */
+ #if IS_ENABLED(CONFIG_UART0_PORT_F)
+ 	{ "uart0",	3 },	/* PF2-PF4 */
+@@ -728,6 +740,7 @@ static const struct sunxi_pinctrl_functi
+ 	{ "mmc0",	2 },	/* PF0-PF5 */
+ 	{ "mmc1",	2 },	/* PG0-PG5 */
+ 	{ "mmc2",	3 },	/* PC0-PC16 */
++	{ "nand0",	2 },	/* PC0-PC16 */
+ 	{ "spi0",	4 },	/* PC0-PC7, PC15-PC16 */
+ #if IS_ENABLED(CONFIG_UART0_PORT_F)
+ 	{ "uart0",	3 },	/* PF2-PF4 */
diff --git a/package/boot/uboot-d1/patches/0029-mtd-nand-sunxi-Remove-an-unnecessary-check.patch b/package/boot/uboot-d1/patches/0029-mtd-nand-sunxi-Remove-an-unnecessary-check.patch
new file mode 100644
index 00000000000000..807c31d922fad1
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0029-mtd-nand-sunxi-Remove-an-unnecessary-check.patch
@@ -0,0 +1,32 @@
+From 8e793af8598a8429c9dc0f096c72a92adb360a57 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 15 May 2022 21:51:47 -0500
+Subject: [PATCH 29/90] mtd: nand: sunxi: Remove an unnecessary check
+
+Each chip is required to have a unique CS number ("reg" property) in the
+range 0-7, so there is no need to separately count the number of chips.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/mtd/nand/raw/sunxi_nand.c | 10 ----------
+ 1 file changed, 10 deletions(-)
+
+--- a/drivers/mtd/nand/raw/sunxi_nand.c
++++ b/drivers/mtd/nand/raw/sunxi_nand.c
+@@ -1767,16 +1767,6 @@ static int sunxi_nand_chips_init(int nod
+ 	int ret, i = 0;
+ 
+ 	for (nand_node = fdt_first_subnode(blob, node); nand_node >= 0;
+-	     nand_node = fdt_next_subnode(blob, nand_node))
+-		i++;
+-
+-	if (i > 8) {
+-		dev_err(nfc->dev, "too many NAND chips: %d (max = 8)\n", i);
+-		return -EINVAL;
+-	}
+-
+-	i = 0;
+-	for (nand_node = fdt_first_subnode(blob, node); nand_node >= 0;
+ 	     nand_node = fdt_next_subnode(blob, nand_node)) {
+ 		ret = sunxi_nand_chip_init(nand_node, nfc, i++);
+ 		if (ret)
diff --git a/package/boot/uboot-d1/patches/0030-mtd-nand-sunxi-Convert-from-fdtdec-to-ofnode.patch b/package/boot/uboot-d1/patches/0030-mtd-nand-sunxi-Convert-from-fdtdec-to-ofnode.patch
new file mode 100644
index 00000000000000..c88fef4f966d9a
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0030-mtd-nand-sunxi-Convert-from-fdtdec-to-ofnode.patch
@@ -0,0 +1,203 @@
+From 61b63cbb3526e19a0e299f95a3435a237c7c4b4b Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 15 May 2022 21:54:25 -0500
+Subject: [PATCH 30/90] mtd: nand: sunxi: Convert from fdtdec to ofnode
+
+As a first step toward converting this driver to the driver model, use
+the ofnode abstraction to replace direct references to the FDT blob.
+
+Using ofnode_read_u32_index removes an extra pair of loops and makes the
+allwinner,rb property optional, matching the devicetree binding.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/mtd/nand/raw/sunxi_nand.c | 73 +++++++++++--------------------
+ include/fdtdec.h                  |  1 -
+ lib/fdtdec.c                      |  1 -
+ 3 files changed, 26 insertions(+), 49 deletions(-)
+
+--- a/drivers/mtd/nand/raw/sunxi_nand.c
++++ b/drivers/mtd/nand/raw/sunxi_nand.c
+@@ -25,11 +25,10 @@
+  */
+ 
+ #include <common.h>
+-#include <fdtdec.h>
++#include <dm.h>
+ #include <malloc.h>
+ #include <memalign.h>
+ #include <nand.h>
+-#include <asm/global_data.h>
+ #include <dm/device_compat.h>
+ #include <dm/devres.h>
+ #include <linux/bitops.h>
+@@ -45,8 +44,6 @@
+ #include <asm/gpio.h>
+ #include <asm/arch/clock.h>
+ 
+-DECLARE_GLOBAL_DATA_PTR;
+-
+ #define NFC_REG_CTL		0x0000
+ #define NFC_REG_ST		0x0004
+ #define NFC_REG_INT		0x0008
+@@ -1605,19 +1602,18 @@ static int sunxi_nand_ecc_init(struct mt
+ 	return 0;
+ }
+ 
+-static int sunxi_nand_chip_init(int node, struct sunxi_nfc *nfc, int devnum)
++static int sunxi_nand_chip_init(ofnode np, struct sunxi_nfc *nfc, int devnum)
+ {
+ 	const struct nand_sdr_timings *timings;
+-	const void *blob = gd->fdt_blob;
+ 	struct sunxi_nand_chip *chip;
+ 	struct mtd_info *mtd;
+ 	struct nand_chip *nand;
+ 	int nsels;
+ 	int ret;
+ 	int i;
+-	u32 cs[8], rb[8];
++	u32 tmp;
+ 
+-	if (!fdt_getprop(blob, node, "reg", &nsels))
++	if (!ofnode_get_property(np, "reg", &nsels))
+ 		return -EINVAL;
+ 
+ 	nsels /= sizeof(u32);
+@@ -1638,25 +1634,12 @@ static int sunxi_nand_chip_init(int node
+ 	chip->selected = -1;
+ 
+ 	for (i = 0; i < nsels; i++) {
+-		cs[i] = -1;
+-		rb[i] = -1;
+-	}
+-
+-	ret = fdtdec_get_int_array(gd->fdt_blob, node, "reg", cs, nsels);
+-	if (ret) {
+-		dev_err(nfc->dev, "could not retrieve reg property: %d\n", ret);
+-		return ret;
+-	}
+-
+-	ret = fdtdec_get_int_array(gd->fdt_blob, node, "allwinner,rb", rb,
+-				   nsels);
+-	if (ret) {
+-		dev_err(nfc->dev, "could not retrieve reg property: %d\n", ret);
+-		return ret;
+-	}
+-
+-	for (i = 0; i < nsels; i++) {
+-		int tmp = cs[i];
++		ret = ofnode_read_u32_index(np, "reg", i, &tmp);
++		if (ret) {
++			dev_err(nfc->dev, "could not retrieve reg property: %d\n",
++				ret);
++			return ret;
++		}
+ 
+ 		if (tmp > NFC_MAX_CS) {
+ 			dev_err(nfc->dev,
+@@ -1671,15 +1654,14 @@ static int sunxi_nand_chip_init(int node
+ 
+ 		chip->sels[i].cs = tmp;
+ 
+-		tmp = rb[i];
+-		if (tmp >= 0 && tmp < 2) {
++		if (!ofnode_read_u32_index(np, "allwinner,rb", i, &tmp) &&
++		    tmp < 2) {
+ 			chip->sels[i].rb.type = RB_NATIVE;
+ 			chip->sels[i].rb.info.nativeid = tmp;
+ 		} else {
+-			ret = gpio_request_by_name_nodev(offset_to_ofnode(node),
+-						"rb-gpios", i,
+-						&chip->sels[i].rb.info.gpio,
+-						GPIOD_IS_IN);
++			ret = gpio_request_by_name_nodev(np, "rb-gpios", i,
++							 &chip->sels[i].rb.info.gpio,
++							 GPIOD_IS_IN);
+ 			if (ret)
+ 				chip->sels[i].rb.type = RB_GPIO;
+ 			else
+@@ -1711,7 +1693,7 @@ static int sunxi_nand_chip_init(int node
+ 	 * in the DT.
+ 	 */
+ 	nand->ecc.mode = NAND_ECC_HW;
+-	nand->flash_node = offset_to_ofnode(node);
++	nand->flash_node = np;
+ 	nand->select_chip = sunxi_nfc_select_chip;
+ 	nand->cmd_ctrl = sunxi_nfc_cmd_ctrl;
+ 	nand->read_buf = sunxi_nfc_read_buf;
+@@ -1760,15 +1742,13 @@ static int sunxi_nand_chip_init(int node
+ 	return 0;
+ }
+ 
+-static int sunxi_nand_chips_init(int node, struct sunxi_nfc *nfc)
++static int sunxi_nand_chips_init(ofnode node, struct sunxi_nfc *nfc)
+ {
+-	const void *blob = gd->fdt_blob;
+-	int nand_node;
++	ofnode nand_np;
+ 	int ret, i = 0;
+ 
+-	for (nand_node = fdt_first_subnode(blob, node); nand_node >= 0;
+-	     nand_node = fdt_next_subnode(blob, nand_node)) {
+-		ret = sunxi_nand_chip_init(nand_node, nfc, i++);
++	ofnode_for_each_subnode(nand_np, node) {
++		ret = sunxi_nand_chip_init(nand_np, nfc, i++);
+ 		if (ret)
+ 			return ret;
+ 	}
+@@ -1794,10 +1774,9 @@ static void sunxi_nand_chips_cleanup(str
+ 
+ void sunxi_nand_init(void)
+ {
+-	const void *blob = gd->fdt_blob;
+ 	struct sunxi_nfc *nfc;
+-	fdt_addr_t regs;
+-	int node;
++	phys_addr_t regs;
++	ofnode node;
+ 	int ret;
+ 
+ 	nfc = kzalloc(sizeof(*nfc), GFP_KERNEL);
+@@ -1808,18 +1787,18 @@ void sunxi_nand_init(void)
+ 	init_waitqueue_head(&nfc->controller.wq);
+ 	INIT_LIST_HEAD(&nfc->chips);
+ 
+-	node = fdtdec_next_compatible(blob, 0, COMPAT_SUNXI_NAND);
+-	if (node < 0) {
++	node = ofnode_by_compatible(ofnode_null(), "allwinner,sun4i-a10-nand");
++	if (!ofnode_valid(node)) {
+ 		pr_err("unable to find nfc node in device tree\n");
+ 		goto err;
+ 	}
+ 
+-	if (!fdtdec_get_is_enabled(blob, node)) {
++	if (!ofnode_is_enabled(node)) {
+ 		pr_err("nfc disabled in device tree\n");
+ 		goto err;
+ 	}
+ 
+-	regs = fdtdec_get_addr(blob, node, "reg");
++	regs = ofnode_get_addr(node);
+ 	if (regs == FDT_ADDR_T_NONE) {
+ 		pr_err("unable to find nfc address in device tree\n");
+ 		goto err;
+--- a/include/fdtdec.h
++++ b/include/fdtdec.h
+@@ -187,7 +187,6 @@ enum fdt_compat_id {
+ 	COMPAT_INTEL_BAYTRAIL_FSP,	/* Intel Bay Trail FSP */
+ 	COMPAT_INTEL_BAYTRAIL_FSP_MDP,	/* Intel FSP memory-down params */
+ 	COMPAT_INTEL_IVYBRIDGE_FSP,	/* Intel Ivy Bridge FSP */
+-	COMPAT_SUNXI_NAND,		/* SUNXI NAND controller */
+ 	COMPAT_ALTERA_SOCFPGA_CLK,	/* SoCFPGA Clock initialization */
+ 	COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE,	/* SoCFPGA pinctrl-single */
+ 	COMPAT_ALTERA_SOCFPGA_H2F_BRG,          /* SoCFPGA hps2fpga bridge */
+--- a/lib/fdtdec.c
++++ b/lib/fdtdec.c
+@@ -64,7 +64,6 @@ static const char * const compat_names[C
+ 	COMPAT(INTEL_BAYTRAIL_FSP, "intel,baytrail-fsp"),
+ 	COMPAT(INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
+ 	COMPAT(INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),
+-	COMPAT(COMPAT_SUNXI_NAND, "allwinner,sun4i-a10-nand"),
+ 	COMPAT(ALTERA_SOCFPGA_CLK, "altr,clk-mgr"),
+ 	COMPAT(ALTERA_SOCFPGA_PINCTRL_SINGLE, "pinctrl-single"),
+ 	COMPAT(ALTERA_SOCFPGA_H2F_BRG, "altr,socfpga-hps2fpga-bridge"),
diff --git a/package/boot/uboot-d1/patches/0031-mtd-nand-sunxi-Convert-to-the-driver-model.patch b/package/boot/uboot-d1/patches/0031-mtd-nand-sunxi-Convert-to-the-driver-model.patch
new file mode 100644
index 00000000000000..d1bec458af6540
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0031-mtd-nand-sunxi-Convert-to-the-driver-model.patch
@@ -0,0 +1,172 @@
+From 3411a9a1be9a8d8fef236a81edbce2a1a8218a32 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Mon, 16 May 2022 00:16:48 -0500
+Subject: [PATCH 31/90] mtd: nand: sunxi: Convert to the driver model
+
+Clocks, resets, and pinmuxes are now handled by the driver model, so the
+only thing the "board" code needs to do is load the driver. This matches
+the pattern used by other DM raw NAND drivers (there is no NAND uclass).
+
+The actual board code is now only needed in SPL.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ board/sunxi/board.c               |  5 +-
+ drivers/mtd/nand/raw/sunxi_nand.c | 81 ++++++++++++++++++-------------
+ 2 files changed, 49 insertions(+), 37 deletions(-)
+
+--- a/board/sunxi/board.c
++++ b/board/sunxi/board.c
+@@ -311,7 +311,7 @@ int dram_init(void)
+ 	return 0;
+ }
+ 
+-#if defined(CONFIG_NAND_SUNXI)
++#if defined(CONFIG_NAND_SUNXI) && defined(CONFIG_SPL_BUILD)
+ static void nand_pinmux_setup(void)
+ {
+ 	unsigned int pin;
+@@ -347,9 +347,6 @@ void board_nand_init(void)
+ {
+ 	nand_pinmux_setup();
+ 	nand_clock_setup();
+-#ifndef CONFIG_SPL_BUILD
+-	sunxi_nand_init();
+-#endif
+ }
+ #endif /* CONFIG_NAND_SUNXI */
+ 
+--- a/drivers/mtd/nand/raw/sunxi_nand.c
++++ b/drivers/mtd/nand/raw/sunxi_nand.c
+@@ -24,11 +24,13 @@
+  * GNU General Public License for more details.
+  */
+ 
++#include <clk.h>
+ #include <common.h>
+ #include <dm.h>
+ #include <malloc.h>
+ #include <memalign.h>
+ #include <nand.h>
++#include <reset.h>
+ #include <dm/device_compat.h>
+ #include <dm/devres.h>
+ #include <linux/bitops.h>
+@@ -260,7 +262,7 @@ static inline struct sunxi_nand_chip *to
+  * NAND Controller structure: stores sunxi NAND controller information
+  *
+  * @controller:		base controller structure
+- * @dev:		parent device (used to print error messages)
++ * @dev:		DM device (used to print error messages)
+  * @regs:		NAND controller registers
+  * @ahb_clk:		NAND Controller AHB clock
+  * @mod_clk:		NAND Controller mod clock
+@@ -273,7 +275,7 @@ static inline struct sunxi_nand_chip *to
+  */
+ struct sunxi_nfc {
+ 	struct nand_hw_control controller;
+-	struct device *dev;
++	struct udevice *dev;
+ 	void __iomem *regs;
+ 	struct clk *ahb_clk;
+ 	struct clk *mod_clk;
+@@ -1772,54 +1774,67 @@ static void sunxi_nand_chips_cleanup(str
+ }
+ #endif /* __UBOOT__ */
+ 
+-void sunxi_nand_init(void)
++static int sunxi_nand_probe(struct udevice *dev)
+ {
+-	struct sunxi_nfc *nfc;
+-	phys_addr_t regs;
+-	ofnode node;
++	struct sunxi_nfc *nfc = dev_get_priv(dev);
++	struct reset_ctl_bulk rst_bulk;
++	struct clk_bulk clk_bulk;
+ 	int ret;
+ 
+-	nfc = kzalloc(sizeof(*nfc), GFP_KERNEL);
+-	if (!nfc)
+-		return;
+-
++	nfc->dev = dev;
+ 	spin_lock_init(&nfc->controller.lock);
+ 	init_waitqueue_head(&nfc->controller.wq);
+ 	INIT_LIST_HEAD(&nfc->chips);
+ 
+-	node = ofnode_by_compatible(ofnode_null(), "allwinner,sun4i-a10-nand");
+-	if (!ofnode_valid(node)) {
+-		pr_err("unable to find nfc node in device tree\n");
+-		goto err;
+-	}
+-
+-	if (!ofnode_is_enabled(node)) {
+-		pr_err("nfc disabled in device tree\n");
+-		goto err;
+-	}
+-
+-	regs = ofnode_get_addr(node);
+-	if (regs == FDT_ADDR_T_NONE) {
+-		pr_err("unable to find nfc address in device tree\n");
+-		goto err;
+-	}
++	nfc->regs = dev_read_addr_ptr(dev);
++	if (!nfc->regs)
++		return -EINVAL;
+ 
+-	nfc->regs = (void *)regs;
++	ret = reset_get_bulk(dev, &rst_bulk);
++	if (!ret)
++		reset_deassert_bulk(&rst_bulk);
++
++	ret = clk_get_bulk(dev, &clk_bulk);
++	if (!ret)
++		clk_enable_bulk(&clk_bulk);
+ 
+ 	ret = sunxi_nfc_rst(nfc);
+ 	if (ret)
+-		goto err;
++		return ret;
+ 
+-	ret = sunxi_nand_chips_init(node, nfc);
++	ret = sunxi_nand_chips_init(dev_ofnode(dev), nfc);
+ 	if (ret) {
+-		dev_err(nfc->dev, "failed to init nand chips\n");
+-		goto err;
++		dev_err(dev, "failed to init nand chips\n");
++		return ret;
+ 	}
+ 
+-	return;
++	return 0;
++}
+ 
+-err:
+-	kfree(nfc);
++static const struct udevice_id sunxi_nand_ids[] = {
++	{
++		.compatible = "allwinner,sun4i-a10-nand",
++	},
++	{ }
++};
++
++U_BOOT_DRIVER(sunxi_nand) = {
++	.name		= "sunxi_nand",
++	.id		= UCLASS_MTD,
++	.of_match	= sunxi_nand_ids,
++	.probe		= sunxi_nand_probe,
++	.priv_auto	= sizeof(struct sunxi_nfc),
++};
++
++void board_nand_init(void)
++{
++	struct udevice *dev;
++	int ret;
++
++	ret = uclass_get_device_by_driver(UCLASS_MTD,
++					  DM_DRIVER_GET(sunxi_nand), &dev);
++	if (ret && ret != -ENODEV)
++		pr_err("Failed to initialize sunxi NAND controller: %d\n", ret);
+ }
+ 
+ MODULE_LICENSE("GPL v2");
diff --git a/package/boot/uboot-d1/patches/0032-sunxi-DT-H6-Add-USB3-to-Pine-H64-DTS.patch b/package/boot/uboot-d1/patches/0032-sunxi-DT-H6-Add-USB3-to-Pine-H64-DTS.patch
new file mode 100644
index 00000000000000..87c9da924ceb42
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0032-sunxi-DT-H6-Add-USB3-to-Pine-H64-DTS.patch
@@ -0,0 +1,31 @@
+From 6fdd7e8d2758f69f5c8e3cb2a0f06da47c1f2cb4 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 17 Apr 2021 14:21:45 -0500
+Subject: [PATCH 32/90] sunxi: DT: H6: Add USB3 to Pine H64 DTS
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm/dts/sun50i-h6-pine-h64.dts | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/arch/arm/dts/sun50i-h6-pine-h64.dts
++++ b/arch/arm/dts/sun50i-h6-pine-h64.dts
+@@ -89,6 +89,10 @@
+ 	status = "okay";
+ };
+ 
++&dwc3 {
++	status = "okay";
++};
++
+ &ehci0 {
+ 	status = "okay";
+ };
+@@ -332,3 +336,7 @@
+ 	usb3_vbus-supply = <&reg_usb_vbus>;
+ 	status = "okay";
+ };
++
++&usb3phy {
++	status = "okay";
++};
diff --git a/package/boot/uboot-d1/patches/0033-tools-mkimage-Add-Allwinner-TOC1-support.patch b/package/boot/uboot-d1/patches/0033-tools-mkimage-Add-Allwinner-TOC1-support.patch
new file mode 100644
index 00000000000000..d443cdf36987a9
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0033-tools-mkimage-Add-Allwinner-TOC1-support.patch
@@ -0,0 +1,441 @@
+From ff0e952a3a380ba191375d5f68609cdbe026d535 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 7 Aug 2021 19:55:20 -0500
+Subject: [PATCH 33/90] tools: mkimage: Add Allwinner TOC1 support
+
+TOC1 is an container format used by Allwinner's boot0 that can hold
+multiple images. It supports encryption and signatures, but that
+functionality is not implemented, only the basic "non-secure" subset.
+
+A config file is used to provide the list of data files to include. Its
+path is passed as the argument to "-d". It contains sections of the
+following form:
+
+  [name]
+  file = /path/to/file
+  addr = 0x12345678
+
+Specific well-known names, such as "dtb", "opensbi", and "u-boot", are
+used by the bootloader to distinguish the items inside the image.
+
+Cover-letter:
+tools: mkimage: Add Allwinner TOC1 support
+
+The SPL port for the Allwinner D1 RISC-V SoC will probably take a while
+longer than porting U-Boot proper, as none of the relevant drivers are
+set up for DM in SPL. In the meantime, we are using[1][2] a fork[3] of
+Allwinner's boot0 loader, which they also call "spl" in their BSP. boot0
+uses this TOC1 image format.
+
+The vendor tools for generating TOC1 images require a binary config file
+generated by their FEX compiler. Instead of trying to support that, I
+made up a simple human-readable config file format. I didn't see any
+existing platform-agnostic parser for multi-image containers in mkimage.
+
+I am sending this as RFC because it is only of temporary/limited use.
+It only works with one specific fork of boot0 which was modified to
+"behave" (the the original vendor version monkey-patches a custom header
+inside the U-Boot image during boot). So it will be obsolete once U-Boot
+SPL is ported. And it is Yet Another Image Format. On the other hand, it
+does work, and it is currently being used.
+
+[1]: https://linux-sunxi.org/Allwinner_Nezha#U-Boot
+[2]: https://fedoraproject.org/wiki/Architectures/RISC-V/Allwinner
+[3]: https://github.com/smaeul/sun20i_d1_spl
+END
+Series-prefix: RFC
+Series-to: sunxi
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ boot/image.c          |   1 +
+ include/image.h       |   1 +
+ include/sunxi_image.h |  26 ++++
+ tools/Makefile        |   1 +
+ tools/sunxi_toc1.c    | 318 ++++++++++++++++++++++++++++++++++++++++++
+ 5 files changed, 347 insertions(+)
+ create mode 100644 tools/sunxi_toc1.c
+
+--- a/boot/image.c
++++ b/boot/image.c
+@@ -180,6 +180,7 @@ static const table_entry_t uimage_type[]
+ 	{	IH_TYPE_COPRO, "copro", "Coprocessor Image"},
+ 	{	IH_TYPE_SUNXI_EGON, "sunxi_egon",  "Allwinner eGON Boot Image" },
+ 	{	IH_TYPE_SUNXI_TOC0, "sunxi_toc0",  "Allwinner TOC0 Boot Image" },
++	{	IH_TYPE_SUNXI_TOC1, "sunxi_toc1",  "Allwinner TOC1 Boot Image" },
+ 	{	-1,		    "",		  "",			},
+ };
+ 
+--- a/include/image.h
++++ b/include/image.h
+@@ -229,6 +229,7 @@ enum image_type_t {
+ 	IH_TYPE_COPRO,			/* Coprocessor Image for remoteproc*/
+ 	IH_TYPE_SUNXI_EGON,		/* Allwinner eGON Boot Image */
+ 	IH_TYPE_SUNXI_TOC0,		/* Allwinner TOC0 Boot Image */
++	IH_TYPE_SUNXI_TOC1,		/* Allwinner TOC1 Boot Image */
+ 
+ 	IH_TYPE_COUNT,			/* Number of image types */
+ };
+--- a/include/sunxi_image.h
++++ b/include/sunxi_image.h
+@@ -116,4 +116,30 @@ struct __packed toc0_item_info {
+ #define TOC0_ITEM_INFO_NAME_KEY		0x00010303
+ #define TOC0_ITEM_INFO_END		"IIE;"
+ 
++struct __packed toc1_main_info {
++	uint8_t name[16];
++	__le32  magic;
++	__le32  checksum;
++	__le32  serial;
++	__le32  status;
++	__le32  num_items;
++	__le32  length;
++	__le32	major_version;
++	__le32	minor_version;
++	__le32	reserved[3];
++	uint8_t end[4];
++};
++
++struct __packed toc1_item_info {
++	uint8_t name[64];
++	__le32  offset;
++	__le32  length;
++	__le32  encryption;
++	__le32  type;
++	__le32  load_addr;
++	__le32  index;
++	__le32	reserved[69];
++	uint8_t end[4];
++};
++
+ #endif
+--- a/tools/Makefile
++++ b/tools/Makefile
+@@ -132,6 +132,7 @@ dumpimage-mkimage-objs := aisimage.o \
+ 			$(ROCKCHIP_OBS) \
+ 			socfpgaimage.o \
+ 			sunxi_egon.o \
++			sunxi_toc1.o \
+ 			lib/crc16-ccitt.o \
+ 			lib/hash-checksum.o \
+ 			lib/sha1.o \
+--- /dev/null
++++ b/tools/sunxi_toc1.c
+@@ -0,0 +1,318 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * (C) Copyright 2018 Arm Ltd.
++ * (C) Copyright 2020-2021 Samuel Holland <samuel@sholland.org>
++ */
++
++#include <assert.h>
++#include <stdint.h>
++#include <stdio.h>
++#include <stdlib.h>
++#include <string.h>
++
++#include <image.h>
++#include <sunxi_image.h>
++
++#include "imagetool.h"
++#include "mkimage.h"
++
++#define SECTOR_SIZE			512
++
++struct item_desc {
++	const char	*name;
++	const char	*file;
++	unsigned long	addr;
++	long		length;
++};
++
++static uint32_t toc1_header_length(uint32_t num_items)
++{
++	return ALIGN(sizeof(struct toc1_main_info) +
++		     sizeof(struct toc1_item_info) * num_items, SECTOR_SIZE);
++}
++
++static int toc1_parse_cfg(const char *file, struct item_desc **desc,
++			  uint32_t *main_length, uint32_t *num_items)
++{
++	struct item_desc *descs = NULL;
++	int ret = EXIT_FAILURE;
++	FILE *cfg, *fp = NULL;
++	uint32_t ndescs = 0;
++	char *line = NULL;
++	size_t len = 0;
++
++	*desc = NULL;
++	*main_length = 0;
++	*num_items = 0;
++
++	cfg = fopen(file, "r");
++	if (!cfg)
++		return ret;
++
++	while (getline(&line, &len, cfg) > 0) {
++		char *end, *s;
++
++		if (line[0] == '[') {
++			s = line + 1;
++			end = strchr(s, ']');
++			if (!end || end[1] != '\n')
++				goto err;
++			end[0] = '\0';
++
++			ndescs++;
++			descs = reallocarray(descs, ndescs, sizeof(*descs));
++			if (!descs)
++				goto err;
++
++			descs[ndescs - 1].name = strdup(s);
++		} else if (line[0] != '#' && line[0] != '\n') {
++			s = strchr(line, '=');
++			if (!s)
++				goto err;
++			while ((++s)[0] == ' ')
++				;
++			end = strchr(s, '\n');
++			if (!end)
++				goto err;
++			end[0] = '\0';
++
++			if (!strncmp(line, "file", strlen("file"))) {
++				fp = fopen(s, "rb");
++				if (!fp)
++					goto err;
++				if (fseek(fp, 0, SEEK_END) < 0)
++					goto err;
++				descs[ndescs - 1].file = strdup(s);
++				descs[ndescs - 1].length = ftell(fp);
++				*main_length += ALIGN(descs[ndescs - 1].length,
++						      SECTOR_SIZE);
++				fclose(fp);
++				fp = NULL;
++			} else if (!strncmp(line, "addr", strlen("addr"))) {
++				descs[ndescs - 1].addr = strtoul(s, NULL, 0);
++			} else {
++				goto err;
++			}
++		}
++	}
++
++	*desc = descs;
++	*main_length += toc1_header_length(ndescs);
++	*num_items = ndescs;
++
++	ret = EXIT_SUCCESS;
++
++err:
++	if (fp)
++		fclose(fp);
++	if (ret)
++		free(descs);
++	free(line);
++	fclose(cfg);
++
++	return ret;
++}
++
++static int toc1_create(uint8_t *buf, uint32_t len,
++		       const struct item_desc *desc, uint32_t num_items)
++{
++	struct toc1_main_info *main = (void *)buf;
++	struct toc1_item_info *item = (void *)(main + 1);
++	uint32_t item_offset, item_length;
++	uint32_t *buf32 = (void *)buf;
++	int ret = EXIT_FAILURE;
++	uint32_t checksum = 0;
++	FILE *fp = NULL;
++	int i;
++
++	/* Create the main TOC1 header. */
++	main->magic	= cpu_to_le32(TOC0_MAIN_INFO_MAGIC);
++	main->checksum	= cpu_to_le32(BROM_STAMP_VALUE);
++	main->num_items	= cpu_to_le32(num_items);
++	memcpy(main->end, TOC0_MAIN_INFO_END, sizeof(main->end));
++
++	item_offset = 0;
++	item_length = toc1_header_length(num_items);
++
++	for (i = 0; i < num_items; ++i, ++item, ++desc) {
++		item_offset = item_offset + item_length;
++		item_length = desc->length;
++
++		/* Create the item header. */
++		memcpy(item->name, desc->name,
++		       strnlen(desc->name, sizeof(item->name)));
++		item->offset = cpu_to_le32(item_offset);
++		item->length = cpu_to_le32(item_length);
++		item->load_addr = cpu_to_le32(desc->addr);
++		memcpy(item->end, TOC0_ITEM_INFO_END, sizeof(item->end));
++
++		/* Read in the data. */
++		fp = fopen(desc->file, "rb");
++		if (!fp)
++			goto err;
++		if (!fread(buf + item_offset, item_length, 1, fp))
++			goto err;
++		fclose(fp);
++		fp = NULL;
++
++		/* Pad the sectors with 0xff to be flash-friendly. */
++		item_offset = item_offset + item_length;
++		item_length = ALIGN(item_offset, SECTOR_SIZE) - item_offset;
++		memset(buf + item_offset, 0xff, item_length);
++	}
++
++	/* Fill in the total padded file length. */
++	item_offset = item_offset + item_length;
++	main->length = cpu_to_le32(item_offset);
++
++	/* Verify enough space was provided when creating the image. */
++	assert(len >= item_offset);
++
++	/* Calculate the checksum. Yes, it's that simple. */
++	for (i = 0; i < item_offset / 4; ++i)
++		checksum += le32_to_cpu(buf32[i]);
++	main->checksum = cpu_to_le32(checksum);
++
++	ret = EXIT_SUCCESS;
++
++err:
++	if (fp)
++		fclose(fp);
++
++	return ret;
++}
++
++static int toc1_verify(const uint8_t *buf, uint32_t len)
++{
++	const struct toc1_main_info *main = (void *)buf;
++	const struct toc1_item_info *item = (void *)(main + 1);
++	uint32_t checksum = BROM_STAMP_VALUE;
++	uint32_t main_length, num_items;
++	uint32_t *buf32 = (void *)buf;
++	int ret = EXIT_FAILURE;
++	int i;
++
++	num_items   = le32_to_cpu(main->num_items);
++	main_length = le32_to_cpu(main->length);
++
++	if (len < main_length || main_length < toc1_header_length(num_items))
++		goto err;
++
++	/* Verify the main header. */
++	if (le32_to_cpu(main->magic) != TOC0_MAIN_INFO_MAGIC)
++		goto err;
++	/* Verify the checksum without modifying the buffer. */
++	for (i = 0; i < main_length / 4; ++i)
++		checksum += le32_to_cpu(buf32[i]);
++	if (checksum != 2 * le32_to_cpu(main->checksum))
++		goto err;
++	/* The length must be at least 512 byte aligned. */
++	if (main_length % SECTOR_SIZE)
++		goto err;
++	if (memcmp(main->end, TOC0_MAIN_INFO_END, sizeof(main->end)))
++		goto err;
++
++	/* Verify each item header. */
++	for (i = 0; i < num_items; ++i, ++item)
++		if (memcmp(item->end, TOC0_ITEM_INFO_END, sizeof(item->end)))
++			goto err;
++
++	ret = EXIT_SUCCESS;
++
++err:
++	return ret;
++}
++
++static int toc1_check_params(struct image_tool_params *params)
++{
++	if (!params->dflag)
++		return -EINVAL;
++
++	return 0;
++}
++
++static int toc1_verify_header(unsigned char *buf, int image_size,
++			      struct image_tool_params *params)
++{
++	return toc1_verify(buf, image_size);
++}
++
++static void toc1_print_header(const void *buf)
++{
++	const struct toc1_main_info *main = buf;
++	const struct toc1_item_info *item = (void *)(main + 1);
++	uint32_t head_length, main_length, num_items;
++	uint32_t item_offset, item_length, item_addr;
++	int i;
++
++	num_items   = le32_to_cpu(main->num_items);
++	head_length = sizeof(*main) + num_items * sizeof(*item);
++	main_length = le32_to_cpu(main->length);
++
++	printf("Allwinner TOC1 Image\n"
++	       "Size: %d bytes\n"
++	       "Contents: %d items\n"
++	       " 00000000:%08x Headers\n",
++	       main_length, num_items, head_length);
++
++	for (i = 0; i < num_items; ++i, ++item) {
++		item_offset = le32_to_cpu(item->offset);
++		item_length = le32_to_cpu(item->length);
++		item_addr   = le32_to_cpu(item->load_addr);
++
++		printf(" %08x:%08x => %08x %s\n",
++		       item_offset, item_length, item_addr, item->name);
++	}
++}
++
++static void toc1_set_header(void *buf, struct stat *sbuf, int ifd,
++			    struct image_tool_params *params)
++{
++	/* Image is already written below. */
++}
++
++static int toc1_check_image_type(uint8_t type)
++{
++	return type == IH_TYPE_SUNXI_TOC1 ? 0 : 1;
++}
++
++static int toc1_vrec_header(struct image_tool_params *params,
++			    struct image_type_params *tparams)
++{
++	uint32_t main_length, num_items;
++	struct item_desc *desc;
++	int ret;
++
++	/* This "header" contains the entire image. */
++	params->skipcpy = 1;
++
++	ret = toc1_parse_cfg(params->datafile, &desc, &main_length, &num_items);
++	if (ret)
++		exit(ret);
++
++	tparams->header_size = main_length;
++	tparams->hdr = calloc(tparams->header_size, 1);
++	if (!tparams->hdr)
++		exit(ret);
++
++	ret = toc1_create(tparams->hdr, tparams->header_size, desc, num_items);
++	if (ret)
++		exit(ret);
++
++	return 0;
++}
++
++U_BOOT_IMAGE_TYPE(
++	sunxi_toc1,
++	"Allwinner TOC1 Boot Image support",
++	0,
++	NULL,
++	toc1_check_params,
++	toc1_verify_header,
++	toc1_print_header,
++	toc1_set_header,
++	NULL,
++	toc1_check_image_type,
++	NULL,
++	toc1_vrec_header
++);
diff --git a/package/boot/uboot-d1/patches/0034-phy-sun4i-usb-Do-not-drive-VBUS-with-external-VBUS-p.patch b/package/boot/uboot-d1/patches/0034-phy-sun4i-usb-Do-not-drive-VBUS-with-external-VBUS-p.patch
new file mode 100644
index 00000000000000..5a2efb16dc196c
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0034-phy-sun4i-usb-Do-not-drive-VBUS-with-external-VBUS-p.patch
@@ -0,0 +1,33 @@
+From 79f7d883d980beea9989d06f9fba4fcc0430176a Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Thu, 14 Jul 2022 22:14:38 -0500
+Subject: [PATCH 34/90] phy: sun4i-usb: Do not drive VBUS with external VBUS
+ present
+
+It is possible to use host-side USB with externally-provided VBUS. For
+example, some USB OTG cables have an extra power input which powers
+both the board and the USB peripheral.
+
+To support this setup, skip enabling the VBUS switch/regulator if VBUS
+voltage is already present. This behavior matches the Linux PHY driver.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/phy/allwinner/phy-sun4i-usb.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/drivers/phy/allwinner/phy-sun4i-usb.c
++++ b/drivers/phy/allwinner/phy-sun4i-usb.c
+@@ -220,6 +220,12 @@ static int sun4i_usb_phy_power_on(struct
+ 		initial_usb_scan_delay = 0;
+ 	}
+ 
++	/* For phy0 only turn on Vbus if we don't have an ext. Vbus */
++	if (phy->id == 0 && sun4i_usb_phy_vbus_detect(phy)) {
++		dev_warn(phy->dev, "External vbus detected, not enabling our own vbus\n");
++		return 0;
++	}
++
+ 	if (usb_phy->vbus) {
+ 		ret = regulator_set_enable(usb_phy->vbus, true);
+ 		if (ret && ret != -ENOSYS)
diff --git a/package/boot/uboot-d1/patches/0035-mtd-nand-sunxi-Pass-the-device-to-the-init-function.patch b/package/boot/uboot-d1/patches/0035-mtd-nand-sunxi-Pass-the-device-to-the-init-function.patch
new file mode 100644
index 00000000000000..4963fbfd71a775
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0035-mtd-nand-sunxi-Pass-the-device-to-the-init-function.patch
@@ -0,0 +1,163 @@
+From 4bc5cec5361dd6a2ae3bd044c79a4b5227bb9627 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Mon, 16 May 2022 00:47:32 -0500
+Subject: [PATCH 35/90] mtd: nand: sunxi: Pass the device to the init function
+
+This more closely matches the U-Boot driver to the Linux version.
+
+Series-to: sunxi
+
+Cover-letter:
+mtd: nand: sunxi: Convert to devicetree and the driver model
+This series converts the sunxi NAND driver to get its resources (clocks,
+resets, pins) from the devicetree, and probe using the driver model.
+
+In addition to the immediate cleanup, this allows backporting more
+patches (bugfixes, newer SoC support) from the Linux driver.
+END
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/mtd/nand/raw/sunxi_nand.c | 39 ++++++++++++++++---------------
+ 1 file changed, 20 insertions(+), 19 deletions(-)
+
+--- a/drivers/mtd/nand/raw/sunxi_nand.c
++++ b/drivers/mtd/nand/raw/sunxi_nand.c
+@@ -1604,7 +1604,8 @@ static int sunxi_nand_ecc_init(struct mt
+ 	return 0;
+ }
+ 
+-static int sunxi_nand_chip_init(ofnode np, struct sunxi_nfc *nfc, int devnum)
++static int sunxi_nand_chip_init(struct udevice *dev, struct sunxi_nfc *nfc,
++				ofnode np, int devnum)
+ {
+ 	const struct nand_sdr_timings *timings;
+ 	struct sunxi_nand_chip *chip;
+@@ -1620,7 +1621,7 @@ static int sunxi_nand_chip_init(ofnode n
+ 
+ 	nsels /= sizeof(u32);
+ 	if (!nsels || nsels > 8) {
+-		dev_err(nfc->dev, "invalid reg property size\n");
++		dev_err(dev, "invalid reg property size\n");
+ 		return -EINVAL;
+ 	}
+ 
+@@ -1628,7 +1629,7 @@ static int sunxi_nand_chip_init(ofnode n
+ 		       (nsels * sizeof(struct sunxi_nand_chip_sel)),
+ 		       GFP_KERNEL);
+ 	if (!chip) {
+-		dev_err(nfc->dev, "could not allocate chip\n");
++		dev_err(dev, "could not allocate chip\n");
+ 		return -ENOMEM;
+ 	}
+ 
+@@ -1638,19 +1639,19 @@ static int sunxi_nand_chip_init(ofnode n
+ 	for (i = 0; i < nsels; i++) {
+ 		ret = ofnode_read_u32_index(np, "reg", i, &tmp);
+ 		if (ret) {
+-			dev_err(nfc->dev, "could not retrieve reg property: %d\n",
++			dev_err(dev, "could not retrieve reg property: %d\n",
+ 				ret);
+ 			return ret;
+ 		}
+ 
+ 		if (tmp > NFC_MAX_CS) {
+-			dev_err(nfc->dev,
++			dev_err(dev,
+ 				"invalid reg value: %u (max CS = 7)\n", tmp);
+ 			return -EINVAL;
+ 		}
+ 
+ 		if (test_and_set_bit(tmp, &nfc->assigned_cs)) {
+-			dev_err(nfc->dev, "CS %d already assigned\n", tmp);
++			dev_err(dev, "CS %d already assigned\n", tmp);
+ 			return -EINVAL;
+ 		}
+ 
+@@ -1661,9 +1662,9 @@ static int sunxi_nand_chip_init(ofnode n
+ 			chip->sels[i].rb.type = RB_NATIVE;
+ 			chip->sels[i].rb.info.nativeid = tmp;
+ 		} else {
+-			ret = gpio_request_by_name_nodev(np, "rb-gpios", i,
+-							 &chip->sels[i].rb.info.gpio,
+-							 GPIOD_IS_IN);
++			ret = gpio_request_by_name(dev, "rb-gpios", i,
++						   &chip->sels[i].rb.info.gpio,
++						   GPIOD_IS_IN);
+ 			if (ret)
+ 				chip->sels[i].rb.type = RB_GPIO;
+ 			else
+@@ -1674,7 +1675,7 @@ static int sunxi_nand_chip_init(ofnode n
+ 	timings = onfi_async_timing_mode_to_sdr_timings(0);
+ 	if (IS_ERR(timings)) {
+ 		ret = PTR_ERR(timings);
+-		dev_err(nfc->dev,
++		dev_err(dev,
+ 			"could not retrieve timings for ONFI mode 0: %d\n",
+ 			ret);
+ 		return ret;
+@@ -1682,7 +1683,7 @@ static int sunxi_nand_chip_init(ofnode n
+ 
+ 	ret = sunxi_nand_chip_set_timings(nfc, chip, timings);
+ 	if (ret) {
+-		dev_err(nfc->dev, "could not configure chip timings: %d\n", ret);
++		dev_err(dev, "could not configure chip timings: %d\n", ret);
+ 		return ret;
+ 	}
+ 
+@@ -1717,25 +1718,25 @@ static int sunxi_nand_chip_init(ofnode n
+ 
+ 	ret = sunxi_nand_chip_init_timings(nfc, chip);
+ 	if (ret) {
+-		dev_err(nfc->dev, "could not configure chip timings: %d\n", ret);
++		dev_err(dev, "could not configure chip timings: %d\n", ret);
+ 		return ret;
+ 	}
+ 
+ 	ret = sunxi_nand_ecc_init(mtd, &nand->ecc);
+ 	if (ret) {
+-		dev_err(nfc->dev, "ECC init failed: %d\n", ret);
++		dev_err(dev, "ECC init failed: %d\n", ret);
+ 		return ret;
+ 	}
+ 
+ 	ret = nand_scan_tail(mtd);
+ 	if (ret) {
+-		dev_err(nfc->dev, "nand_scan_tail failed: %d\n", ret);
++		dev_err(dev, "nand_scan_tail failed: %d\n", ret);
+ 		return ret;
+ 	}
+ 
+ 	ret = nand_register(devnum, mtd);
+ 	if (ret) {
+-		dev_err(nfc->dev, "failed to register mtd device: %d\n", ret);
++		dev_err(dev, "failed to register mtd device: %d\n", ret);
+ 		return ret;
+ 	}
+ 
+@@ -1744,13 +1745,13 @@ static int sunxi_nand_chip_init(ofnode n
+ 	return 0;
+ }
+ 
+-static int sunxi_nand_chips_init(ofnode node, struct sunxi_nfc *nfc)
++static int sunxi_nand_chips_init(struct udevice *dev, struct sunxi_nfc *nfc)
+ {
+ 	ofnode nand_np;
+ 	int ret, i = 0;
+ 
+-	ofnode_for_each_subnode(nand_np, node) {
+-		ret = sunxi_nand_chip_init(nand_np, nfc, i++);
++	dev_for_each_subnode(nand_np, dev) {
++		ret = sunxi_nand_chip_init(dev, nfc, nand_np, i++);
+ 		if (ret)
+ 			return ret;
+ 	}
+@@ -1802,7 +1803,7 @@ static int sunxi_nand_probe(struct udevi
+ 	if (ret)
+ 		return ret;
+ 
+-	ret = sunxi_nand_chips_init(dev_ofnode(dev), nfc);
++	ret = sunxi_nand_chips_init(dev, nfc);
+ 	if (ret) {
+ 		dev_err(dev, "failed to init nand chips\n");
+ 		return ret;
diff --git a/package/boot/uboot-d1/patches/0036-sunxi-Enable-PHY_SUN4I_USB-by-default-for-new-SoCs.patch b/package/boot/uboot-d1/patches/0036-sunxi-Enable-PHY_SUN4I_USB-by-default-for-new-SoCs.patch
new file mode 100644
index 00000000000000..0d0bfc0fb41551
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0036-sunxi-Enable-PHY_SUN4I_USB-by-default-for-new-SoCs.patch
@@ -0,0 +1,120 @@
+From b13140a914199dcdd80331fef6f33d47f008f1b4 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Fri, 5 Aug 2022 23:40:22 -0500
+Subject: [PATCH 36/90] sunxi: Enable PHY_SUN4I_USB by default for new SoCs
+
+With one exception (sun9i), all sunxi SoCs released to date use variants
+of the same USB PHY. Instead of requiring each new SoC to duplicate the
+PHY driver selection, enable it by default.
+
+Series-to: Andre Przywara <andre.przywara@arm.com>
+Series-to: Jagan Teki <jagan@amarulasolutions.com>
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm/mach-sunxi/Kconfig   | 11 -----------
+ drivers/phy/allwinner/Kconfig |  3 ++-
+ 2 files changed, 2 insertions(+), 12 deletions(-)
+
+--- a/arch/arm/mach-sunxi/Kconfig
++++ b/arch/arm/mach-sunxi/Kconfig
+@@ -162,7 +162,6 @@ endif
+ 
+ config MACH_SUNXI_H3_H5
+ 	bool
+-	select PHY_SUN4I_USB
+ 	select SUNXI_DE2
+ 	select SUNXI_DRAM_DW
+ 	select SUNXI_DRAM_DW_32BIT
+@@ -191,7 +190,6 @@ config MACH_SUNIV
+ config MACH_SUN4I
+ 	bool "sun4i (Allwinner A10)"
+ 	select CPU_V7A
+-	select PHY_SUN4I_USB
+ 	select DRAM_SUN4I
+ 	select SUNXI_GEN_SUN4I
+ 	select SUPPORT_SPL
+@@ -202,7 +200,6 @@ config MACH_SUN5I
+ 	bool "sun5i (Allwinner A13)"
+ 	select CPU_V7A
+ 	select DRAM_SUN4I
+-	select PHY_SUN4I_USB
+ 	select SUNXI_GEN_SUN4I
+ 	select SUPPORT_SPL
+ 	imply SPL_SYS_I2C_LEGACY
+@@ -216,7 +213,6 @@ config MACH_SUN6I
+ 	select ARCH_SUPPORT_PSCI
+ 	select SPL_ARMV7_SET_CORTEX_SMPEN
+ 	select DRAM_SUN6I
+-	select PHY_SUN4I_USB
+ 	select SPL_I2C
+ 	select SUN6I_PRCM
+ 	select SUNXI_GEN_SUN6I
+@@ -232,7 +228,6 @@ config MACH_SUN7I
+ 	select ARCH_SUPPORT_PSCI
+ 	select SPL_ARMV7_SET_CORTEX_SMPEN
+ 	select DRAM_SUN4I
+-	select PHY_SUN4I_USB
+ 	select SUNXI_GEN_SUN4I
+ 	select SUPPORT_SPL
+ 	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
+@@ -246,7 +241,6 @@ config MACH_SUN8I_A23
+ 	select CPU_V7_HAS_VIRT
+ 	select ARCH_SUPPORT_PSCI
+ 	select DRAM_SUN8I_A23
+-	select PHY_SUN4I_USB
+ 	select SPL_I2C
+ 	select SUNXI_GEN_SUN6I
+ 	select SUPPORT_SPL
+@@ -260,7 +254,6 @@ config MACH_SUN8I_A33
+ 	select CPU_V7_HAS_VIRT
+ 	select ARCH_SUPPORT_PSCI
+ 	select DRAM_SUN8I_A33
+-	select PHY_SUN4I_USB
+ 	select SPL_I2C
+ 	select SUNXI_GEN_SUN6I
+ 	select SUPPORT_SPL
+@@ -271,7 +264,6 @@ config MACH_SUN8I_A83T
+ 	bool "sun8i (Allwinner A83T)"
+ 	select CPU_V7A
+ 	select DRAM_SUN8I_A83T
+-	select PHY_SUN4I_USB
+ 	select SPL_I2C
+ 	select SUNXI_GEN_SUN6I
+ 	select MMC_SUNXI_HAS_NEW_MODE
+@@ -299,7 +291,6 @@ config MACH_SUN8I_R40
+ 	select SUPPORT_SPL
+ 	select SUNXI_DRAM_DW
+ 	select SUNXI_DRAM_DW_32BIT
+-	select PHY_SUN4I_USB
+ 	imply SPL_SYS_I2C_LEGACY
+ 
+ config MACH_SUN8I_V3S
+@@ -327,7 +318,6 @@ config MACH_SUN9I
+ config MACH_SUN50I
+ 	bool "sun50i (Allwinner A64)"
+ 	select ARM64
+-	select PHY_SUN4I_USB
+ 	select SUN6I_PRCM
+ 	select SUNXI_DE2
+ 	select SUNXI_GEN_SUN6I
+@@ -350,7 +340,6 @@ config MACH_SUN50I_H5
+ config MACH_SUN50I_H6
+ 	bool "sun50i (Allwinner H6)"
+ 	select ARM64
+-	select PHY_SUN4I_USB
+ 	select DRAM_SUN50I_H6
+ 	select SUN50I_GEN_H6
+ 
+--- a/drivers/phy/allwinner/Kconfig
++++ b/drivers/phy/allwinner/Kconfig
+@@ -3,7 +3,8 @@
+ #
+ config PHY_SUN4I_USB
+ 	bool "Allwinner Sun4I USB PHY driver"
+-	depends on ARCH_SUNXI
++	depends on ARCH_SUNXI && !MACH_SUN9I
++	default y
+ 	select DM_REGULATOR
+ 	select PHY
+ 	help
diff --git a/package/boot/uboot-d1/patches/0037-sunxi-psci-Add-support-for-H3-CPU-0-hotplug.patch b/package/boot/uboot-d1/patches/0037-sunxi-psci-Add-support-for-H3-CPU-0-hotplug.patch
new file mode 100644
index 00000000000000..040bce409d6d66
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0037-sunxi-psci-Add-support-for-H3-CPU-0-hotplug.patch
@@ -0,0 +1,183 @@
+From d11c5971f60d482c05f807c24f3ccd37cf7d0f70 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 9 Oct 2021 17:12:57 -0500
+Subject: [PATCH 37/90] sunxi: psci: Add support for H3 CPU 0 hotplug
+
+Due to a bug in the H3 SoC, where the CPU 0 hotplug flag cannot be
+written, resuming CPU 0 requires using the "Super Standby" code path in
+the BROM instead of the hotplug path. This path requires jumping to an
+eGON image in SRAM.
+
+Add support to the build system to generate this eGON image and include
+it in the FIT, and add code to direct the BROM to its location in SRAM.
+
+Since the Super Standby code path in the BROM initializes the CPU and
+AHB1 clocks to 24 MHz, those registers need to be restored after control
+passes back to U-Boot. Furthermore, because the BROM lowers the AHB1
+clock divider to /1 before switching to the lower-frequency parent,
+PLL_PERIPH0 must be bypassed to prevent AHB1 from temporarily running at
+600 MHz. Otherwise, this locks up the SoC.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ Makefile                        | 17 +++++++++++++++++
+ arch/arm/cpu/armv7/sunxi/psci.c | 31 +++++++++++++++++++++++++++++++
+ arch/arm/dts/sunxi-u-boot.dtsi  | 23 ++++++++++++++++++++++-
+ include/configs/sun8i.h         |  4 ++++
+ 4 files changed, 74 insertions(+), 1 deletion(-)
+
+--- a/Makefile
++++ b/Makefile
+@@ -1013,6 +1013,23 @@ INPUTS-y += u-boot.img
+ endif
+ endif
+ 
++ifeq ($(CONFIG_MACH_SUN8I_H3)$(CONFIG_ARMV7_PSCI),yy)
++INPUTS-$(CONFIG_ARMV7_PSCI) += u-boot-resume.img
++
++MKIMAGEFLAGS_u-boot-resume.img := -B 0x400 -T sunxi_egon
++
++u-boot-resume.img: u-boot-resume.bin
++	$(call if_changed,mkimage)
++
++OBJCOPYFLAGS_u-boot-resume.bin := -O binary
++
++u-boot-resume.bin: u-boot-resume.o
++	$(call if_changed,objcopy)
++
++u-boot-resume.S: u-boot
++	@sed -En 's/(0x[[:xdigit:]]+) +psci_cpu_entry/ldr pc, =\1/p' $<.map > $@
++endif
++
+ INPUTS-$(CONFIG_X86) += u-boot-x86-start16.bin u-boot-x86-reset16.bin \
+ 	$(if $(CONFIG_SPL_X86_16BIT_INIT),spl/u-boot-spl.bin) \
+ 	$(if $(CONFIG_TPL_X86_16BIT_INIT),tpl/u-boot-tpl.bin)
+--- a/arch/arm/cpu/armv7/sunxi/psci.c
++++ b/arch/arm/cpu/armv7/sunxi/psci.c
+@@ -10,6 +10,7 @@
+ #include <common.h>
+ #include <asm/cache.h>
+ 
++#include <asm/arch/clock.h>
+ #include <asm/arch/cpu.h>
+ #include <asm/arch/cpucfg.h>
+ #include <asm/arch/prcm.h>
+@@ -141,6 +142,13 @@ static void __secure sunxi_set_entry_add
+ 		(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
+ 
+ 	writel((u32)entry, &cpucfg->priv0);
++
++#ifdef CONFIG_MACH_SUN8I_H3
++	/* Redirect CPU 0 to the secure monitor via the resume shim. */
++	writel(0x16aaefe8, &cpucfg->super_standy_flag);
++	writel(0xaa16efe8, &cpucfg->super_standy_flag);
++	writel(SUNXI_RESUME_BASE, &cpucfg->priv1);
++#endif
+ }
+ #endif
+ 
+@@ -255,9 +263,12 @@ out:
+ int __secure psci_cpu_on(u32 __always_unused unused, u32 mpidr, u32 pc,
+ 			 u32 context_id)
+ {
++	struct sunxi_ccm_reg *ccu = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ 	struct sunxi_cpucfg_reg *cpucfg =
+ 		(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
+ 	u32 cpu = (mpidr & 0x3);
++	u32 cpu_clk;
++	u32 bus_clk;
+ 
+ 	/* store target PC and context id */
+ 	psci_save(cpu, pc, context_id);
+@@ -274,12 +285,32 @@ int __secure psci_cpu_on(u32 __always_un
+ 	/* Lock CPU (Disable external debug access) */
+ 	clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
+ 
++	if (IS_ENABLED(CONFIG_MACH_SUN8I_H3) && cpu == 0) {
++		/* Save registers that will be clobbered by the BROM. */
++		cpu_clk = readl(&ccu->cpu_axi_cfg);
++		bus_clk = readl(&ccu->ahb1_apb1_div);
++
++		/* Bypass PLL_PERIPH0 so AHB1 frequency does not spike. */
++		setbits_le32(&ccu->pll6_cfg, BIT(25));
++	}
++
+ 	/* Power up target CPU */
+ 	sunxi_cpu_set_power(cpu, true);
+ 
+ 	/* De-assert reset on target CPU */
+ 	writel(BIT(1) | BIT(0), &cpucfg->cpu[cpu].rst);
+ 
++	if (IS_ENABLED(CONFIG_MACH_SUN8I_H3) && cpu == 0) {
++		/* Spin until the BROM has clobbered the clock registers. */
++		while (readl(&ccu->ahb1_apb1_div) != 0x00001100);
++
++		/* Restore the registers and turn off PLL_PERIPH0 bypass. */
++		writel(cpu_clk, &ccu->cpu_axi_cfg);
++		writel(bus_clk, &ccu->ahb1_apb1_div);
++
++		clrbits_le32(&ccu->pll6_cfg, BIT(25));
++	}
++
+ 	/* Unlock CPU (Disable external debug access) */
+ 	setbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
+ 
+--- a/arch/arm/dts/sunxi-u-boot.dtsi
++++ b/arch/arm/dts/sunxi-u-boot.dtsi
+@@ -6,7 +6,11 @@
+ #define ARCH "arm"
+ #endif
+ 
+-#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN50I_H5)
++#if defined(CONFIG_MACH_SUN8I_H3)
++#ifdef CONFIG_ARMV7_PSCI
++#define RESUME_ADDR	SUNXI_RESUME_BASE
++#endif
++#elif defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN50I_H5)
+ #define BL31_ADDR	0x00044000
+ #define SCP_ADDR	0x00050000
+ #elif defined(CONFIG_MACH_SUN50I_H6)
+@@ -78,6 +82,20 @@
+ 				};
+ #endif
+ 
++#ifdef RESUME_ADDR
++				resume {
++					description = "Super Standby resume image";
++					type = "standalone";
++					arch = ARCH;
++					compression = "none";
++					load = <RESUME_ADDR>;
++
++					blob-ext {
++						filename = "u-boot-resume.img";
++					};
++				};
++#endif
++
+ #ifdef SCP_ADDR
+ 				scp {
+ 					description = "SCP firmware";
+@@ -111,6 +129,9 @@
+ 					firmware = "uboot";
+ #endif
+ 					loadables =
++#ifdef RESUME_ADDR
++						    "resume",
++#endif
+ #ifdef SCP_ADDR
+ 						    "scp",
+ #endif
+--- a/include/configs/sun8i.h
++++ b/include/configs/sun8i.h
+@@ -8,6 +8,10 @@
+ #ifndef __CONFIG_H
+ #define __CONFIG_H
+ 
++#define SUNXI_RESUME_BASE		(CONFIG_ARMV7_SECURE_BASE + \
++					 CONFIG_ARMV7_SECURE_MAX_SIZE)
++#define SUNXI_RESUME_SIZE		1024
++
+ #include <configs/sunxi-common.h>
+ 
+ #endif /* __CONFIG_H */
diff --git a/package/boot/uboot-d1/patches/0038-remoteproc-Add-a-driver-for-the-Allwinner-AR100.patch b/package/boot/uboot-d1/patches/0038-remoteproc-Add-a-driver-for-the-Allwinner-AR100.patch
new file mode 100644
index 00000000000000..1b0e002ee9f5fd
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0038-remoteproc-Add-a-driver-for-the-Allwinner-AR100.patch
@@ -0,0 +1,155 @@
+From 7585a12ffec6e42c62222d8ee4085413b3a197f7 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 9 Oct 2021 14:58:27 -0500
+Subject: [PATCH 38/90] remoteproc: Add a driver for the Allwinner AR100
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/remoteproc/Kconfig             |   9 ++
+ drivers/remoteproc/Makefile            |   1 +
+ drivers/remoteproc/sun6i_ar100_rproc.c | 111 +++++++++++++++++++++++++
+ 3 files changed, 121 insertions(+)
+ create mode 100644 drivers/remoteproc/sun6i_ar100_rproc.c
+
+--- a/drivers/remoteproc/Kconfig
++++ b/drivers/remoteproc/Kconfig
+@@ -41,6 +41,15 @@ config REMOTEPROC_STM32_COPRO
+ 	  Say 'y' here to add support for STM32 Cortex-M4 coprocessors via the
+ 	  remoteproc framework.
+ 
++config REMOTEPROC_SUN6I_AR100
++	bool "Support for Allwinner AR100 SCP"
++	select REMOTEPROC
++	depends on ARCH_SUNXI
++	help
++	  Say 'y' here to support Allwinner's AR100 System Control Processor
++	  (SCP), found in various sun6i/sun8i/sun50i family SoCs, through the
++	  remoteproc framework.
++
+ config REMOTEPROC_TI_K3_ARM64
+ 	bool "Support for TI's K3 based ARM64 remoteproc driver"
+ 	select REMOTEPROC
+--- a/drivers/remoteproc/Makefile
++++ b/drivers/remoteproc/Makefile
+@@ -10,6 +10,7 @@ obj-$(CONFIG_$(SPL_)REMOTEPROC) += rproc
+ obj-$(CONFIG_K3_SYSTEM_CONTROLLER) += k3_system_controller.o
+ obj-$(CONFIG_REMOTEPROC_SANDBOX) += sandbox_testproc.o
+ obj-$(CONFIG_REMOTEPROC_STM32_COPRO) += stm32_copro.o
++obj-$(CONFIG_REMOTEPROC_SUN6I_AR100) += sun6i_ar100_rproc.o
+ obj-$(CONFIG_REMOTEPROC_TI_K3_ARM64) += ti_k3_arm64_rproc.o
+ obj-$(CONFIG_REMOTEPROC_TI_K3_DSP) += ti_k3_dsp_rproc.o
+ obj-$(CONFIG_REMOTEPROC_TI_K3_R5F) += ti_k3_r5f_rproc.o
+--- /dev/null
++++ b/drivers/remoteproc/sun6i_ar100_rproc.c
+@@ -0,0 +1,111 @@
++// SPDX-License-Identifier: GPL-2.0
++
++#include <dm.h>
++#include <errno.h>
++#include <remoteproc.h>
++#include <asm/io.h>
++
++#define SUNXI_SCP_MAGIC			0xb4400012
++
++#define OR1K_VEC_FIRST			0x01
++#define OR1K_VEC_LAST			0x0e
++#define OR1K_VEC_ADDR(n)		(0x100 * (n))
++
++struct sun6i_ar100_rproc_priv {
++	void	*cfg_base;
++	ulong	sram_base;
++};
++
++static int sun6i_ar100_rproc_load(struct udevice *dev, ulong addr, ulong size)
++{
++	struct sun6i_ar100_rproc_priv *priv = dev_get_priv(dev);
++
++	/* Check for a valid SCP firmware. */
++	if (readl_relaxed(addr) != SUNXI_SCP_MAGIC)
++		return -ENOENT;
++
++	/* Program exception vectors to the firmware entry point. */
++	for (u32 i = OR1K_VEC_FIRST; i <= OR1K_VEC_LAST; ++i) {
++		ulong vector = priv->sram_base + OR1K_VEC_ADDR(i);
++		ulong offset = addr - vector;
++
++		writel_relaxed(offset >> 2, vector);
++	}
++
++	return 0;
++}
++
++static int sun6i_ar100_rproc_start(struct udevice *dev)
++{
++	struct sun6i_ar100_rproc_priv *priv = dev_get_priv(dev);
++
++	setbits_le32(priv->cfg_base, BIT(0));
++
++	return 0;
++}
++
++static int sun6i_ar100_rproc_stop(struct udevice *dev)
++{
++	struct sun6i_ar100_rproc_priv *priv = dev_get_priv(dev);
++
++	clrbits_le32(priv->cfg_base, BIT(0));
++
++	return 0;
++}
++
++static int sun6i_ar100_rproc_reset(struct udevice *dev)
++{
++	int ret;
++
++	ret = sun6i_ar100_rproc_stop(dev);
++	if (ret)
++		return ret;
++
++	return sun6i_ar100_rproc_start(dev);
++}
++
++static int sun6i_ar100_rproc_is_running(struct udevice *dev)
++{
++	struct sun6i_ar100_rproc_priv *priv = dev_get_priv(dev);
++
++	return !(readl_relaxed(priv->cfg_base) & BIT(0));
++}
++
++static const struct dm_rproc_ops sun6i_ar100_rproc_ops = {
++	.load		= sun6i_ar100_rproc_load,
++	.start		= sun6i_ar100_rproc_start,
++	.stop		= sun6i_ar100_rproc_stop,
++	.reset		= sun6i_ar100_rproc_reset,
++	.is_running	= sun6i_ar100_rproc_is_running,
++};
++
++static int sun6i_ar100_rproc_probe(struct udevice *dev)
++{
++	struct sun6i_ar100_rproc_priv *priv = dev_get_priv(dev);
++	struct ofnode_phandle_args sram_handle;
++	int ret;
++
++	priv->cfg_base = dev_read_addr_ptr(dev);
++
++	ret = dev_read_phandle_with_args(dev, "sram", NULL, 0, 0, &sram_handle);
++	if (ret)
++		return ret;
++
++	priv->sram_base = ofnode_get_addr(sram_handle.node);
++
++	return 0;
++}
++
++static const struct udevice_id sun6i_ar100_rproc_ids[] = {
++	{ .compatible = "allwinner,sun6i-a31-ar100" },
++	{ }
++};
++
++U_BOOT_DRIVER(sun6i_ar100_rproc) = {
++	.name		= "sun6i_ar100_rproc",
++	.id		= UCLASS_REMOTEPROC,
++	.of_match	= sun6i_ar100_rproc_ids,
++	.probe		= sun6i_ar100_rproc_probe,
++	.priv_auto	= sizeof(struct sun6i_ar100_rproc_priv),
++	.ops		= &sun6i_ar100_rproc_ops,
++};
diff --git a/package/boot/uboot-d1/patches/0039-arm-dts-sunxi-h3-Add-nodes-for-AR100-remoteproc.patch b/package/boot/uboot-d1/patches/0039-arm-dts-sunxi-h3-Add-nodes-for-AR100-remoteproc.patch
new file mode 100644
index 00000000000000..8efaee955c7cc6
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0039-arm-dts-sunxi-h3-Add-nodes-for-AR100-remoteproc.patch
@@ -0,0 +1,40 @@
+From 2fdd94449c2668b4ff69326ff8d5daabdf2c9f00 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 9 Oct 2021 15:04:16 -0500
+Subject: [PATCH 39/90] arm: dts: sunxi: h3: Add nodes for AR100 remoteproc
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm/dts/sun8i-h3.dtsi | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+--- a/arch/arm/dts/sun8i-h3.dtsi
++++ b/arch/arm/dts/sun8i-h3.dtsi
+@@ -170,6 +170,14 @@
+ 			#size-cells = <1>;
+ 			ranges;
+ 
++			sram_a2: sram@40000 {
++				compatible = "mmio-sram";
++				reg = <0x00040000 0xc000>;
++				#address-cells = <1>;
++				#size-cells = <1>;
++				ranges = <0 0x00040000 0xc000>;
++			};
++
+ 			sram_c: sram@1d00000 {
+ 				compatible = "mmio-sram";
+ 				reg = <0x01d00000 0x80000>;
+@@ -239,6 +247,12 @@
+ 			nvmem-cell-names = "calibration";
+ 			#thermal-sensor-cells = <0>;
+ 		};
++
++		remoteproc@1f01c00 {
++			compatible = "allwinner,sun6i-a31-ar100";
++			reg = <0x01f01c00 0x400>;
++			sram = <&sram_a2>;
++		};
+ 	};
+ 
+ 	thermal-zones {
diff --git a/package/boot/uboot-d1/patches/0040-sunxi-Enable-support-for-SCP-firmware-on-H3.patch b/package/boot/uboot-d1/patches/0040-sunxi-Enable-support-for-SCP-firmware-on-H3.patch
new file mode 100644
index 00000000000000..12773fc6a88e30
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0040-sunxi-Enable-support-for-SCP-firmware-on-H3.patch
@@ -0,0 +1,63 @@
+From aefe751d6f23c9d526bca447c6c28da97e45e528 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 17 Apr 2021 13:33:54 -0500
+Subject: [PATCH 40/90] sunxi: Enable support for SCP firmware on H3
+
+Now that issues with the BROM have been sorted out, we can implement
+PSCI system suspend on H3 by delegating to SCP firmware. Let's start by
+including the firmware in the FIT image and starting the coprocessor if
+valid firmware is loaded.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm/dts/sunxi-u-boot.dtsi | 1 +
+ board/sunxi/board.c            | 8 ++++++++
+ include/configs/sun8i.h        | 3 +++
+ 3 files changed, 12 insertions(+)
+
+--- a/arch/arm/dts/sunxi-u-boot.dtsi
++++ b/arch/arm/dts/sunxi-u-boot.dtsi
+@@ -9,6 +9,7 @@
+ #if defined(CONFIG_MACH_SUN8I_H3)
+ #ifdef CONFIG_ARMV7_PSCI
+ #define RESUME_ADDR	SUNXI_RESUME_BASE
++#define SCP_ADDR	SUNXI_SCP_BASE
+ #endif
+ #elif defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN50I_H5)
+ #define BL31_ADDR	0x00044000
+--- a/board/sunxi/board.c
++++ b/board/sunxi/board.c
+@@ -19,6 +19,7 @@
+ #include <init.h>
+ #include <log.h>
+ #include <mmc.h>
++#include <remoteproc.h>
+ #include <axp_pmic.h>
+ #include <generic-phy.h>
+ #include <phy-sun4i-usb.h>
+@@ -867,6 +868,13 @@ int board_late_init(void)
+ 	usb_ether_init();
+ #endif
+ 
++#ifdef CONFIG_REMOTEPROC_SUN6I_AR100
++	if (!rproc_load(0, SUNXI_SCP_BASE, SUNXI_SCP_MAX_SIZE)) {
++		puts("Starting SCP...\n");
++		rproc_start(0);
++	}
++#endif
++
+ 	return 0;
+ }
+ 
+--- a/include/configs/sun8i.h
++++ b/include/configs/sun8i.h
+@@ -12,6 +12,9 @@
+ 					 CONFIG_ARMV7_SECURE_MAX_SIZE)
+ #define SUNXI_RESUME_SIZE		1024
+ 
++#define SUNXI_SCP_BASE			(SUNXI_RESUME_BASE + SUNXI_RESUME_SIZE)
++#define SUNXI_SCP_MAX_SIZE		(16 * 1024)
++
+ #include <configs/sunxi-common.h>
+ 
+ #endif /* __CONFIG_H */
diff --git a/package/boot/uboot-d1/patches/0041-arm-psci-Add-definitions-for-PSCI-v1.1.patch b/package/boot/uboot-d1/patches/0041-arm-psci-Add-definitions-for-PSCI-v1.1.patch
new file mode 100644
index 00000000000000..535c156199d662
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0041-arm-psci-Add-definitions-for-PSCI-v1.1.patch
@@ -0,0 +1,115 @@
+From f73116f62647c74eb0f06f0d8c29e5993d961d82 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 9 Oct 2021 22:43:26 -0500
+Subject: [PATCH 41/90] arm: psci: Add definitions for PSCI v1.1
+
+Add the new option, function IDs, and prototypes for PSCI v1.1
+implementations. In the process, fix some issues with the existing
+definitions:
+ - Fix the incorrectly-named ARM_PSCI_0_2_FN64_SYSTEM_RESET2.
+ - Replace the deprecated "affinity_level" naming with "power_level".
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm/cpu/armv7/Kconfig    |  3 +++
+ arch/arm/cpu/armv8/fwcall.c   |  2 +-
+ arch/arm/include/asm/psci.h   |  9 +++++++--
+ arch/arm/include/asm/system.h | 14 +++++++++-----
+ arch/arm/lib/psci-dt.c        |  2 ++
+ 5 files changed, 22 insertions(+), 8 deletions(-)
+
+--- a/arch/arm/cpu/armv7/Kconfig
++++ b/arch/arm/cpu/armv7/Kconfig
+@@ -80,6 +80,9 @@ choice
+ 	help
+ 	  Select the supported PSCI version.
+ 
++config ARMV7_PSCI_1_1
++	bool "PSCI V1.1"
++
+ config ARMV7_PSCI_1_0
+ 	bool "PSCI V1.0"
+ 
+--- a/arch/arm/cpu/armv8/fwcall.c
++++ b/arch/arm/cpu/armv8/fwcall.c
+@@ -103,7 +103,7 @@ void __noreturn psci_system_reset2(u32 r
+ {
+ 	struct pt_regs regs;
+ 
+-	regs.regs[0] = ARM_PSCI_0_2_FN64_SYSTEM_RESET2;
++	regs.regs[0] = ARM_PSCI_1_1_FN64_SYSTEM_RESET2;
+ 	regs.regs[1] = PSCI_RESET2_TYPE_VENDOR | reset_level;
+ 	regs.regs[2] = cookie;
+ 	if (use_smc_for_psci)
+--- a/arch/arm/include/asm/psci.h
++++ b/arch/arm/include/asm/psci.h
+@@ -22,8 +22,9 @@
+ #include <linux/bitops.h>
+ #endif
+ 
+-#define ARM_PSCI_VER_1_0		(0x00010000)
+ #define ARM_PSCI_VER_0_2		(0x00000002)
++#define ARM_PSCI_VER_1_0		(0x00010000)
++#define ARM_PSCI_VER_1_1		(0x00010001)
+ 
+ /* PSCI 0.1 interface */
+ #define ARM_PSCI_FN_BASE		0x95c1ba5e
+@@ -68,7 +69,6 @@
+ #define ARM_PSCI_0_2_FN64_AFFINITY_INFO		ARM_PSCI_0_2_FN64(4)
+ #define ARM_PSCI_0_2_FN64_MIGRATE		ARM_PSCI_0_2_FN64(5)
+ #define ARM_PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU	ARM_PSCI_0_2_FN64(7)
+-#define ARM_PSCI_0_2_FN64_SYSTEM_RESET2		ARM_PSCI_0_2_FN64(18)
+ 
+ /* PSCI 1.0 interface */
+ #define ARM_PSCI_1_0_FN_PSCI_FEATURES		ARM_PSCI_0_2_FN(10)
+@@ -86,6 +86,11 @@
+ #define ARM_PSCI_1_0_FN64_STAT_RESIDENCY	ARM_PSCI_0_2_FN64(16)
+ #define ARM_PSCI_1_0_FN64_STAT_COUNT		ARM_PSCI_0_2_FN64(17)
+ 
++/* PSCI 1.1 interface */
++#define ARM_PSCI_1_1_FN_SYSTEM_RESET2		ARM_PSCI_0_2_FN(18)
++
++#define ARM_PSCI_1_1_FN64_SYSTEM_RESET2		ARM_PSCI_0_2_FN64(18)
++
+ /* 1KB stack per core */
+ #define ARM_PSCI_STACK_SHIFT	10
+ #define ARM_PSCI_STACK_SIZE	(1 << ARM_PSCI_STACK_SHIFT)
+--- a/arch/arm/include/asm/system.h
++++ b/arch/arm/include/asm/system.h
+@@ -557,16 +557,20 @@ void mmu_page_table_flush(unsigned long
+ #ifdef CONFIG_ARMV7_PSCI
+ void psci_arch_cpu_entry(void);
+ void psci_arch_init(void);
++
+ u32 psci_version(void);
+-s32 psci_features(u32 function_id, u32 psci_fid);
++s32 psci_cpu_suspend(u32 function_id, u32 power_state, u32 pc, u32 context_id);
+ s32 psci_cpu_off(void);
+-s32 psci_cpu_on(u32 function_id, u32 target_cpu, u32 pc,
+-		u32 context_id);
+-s32 psci_affinity_info(u32 function_id, u32 target_affinity,
+-		       u32  lowest_affinity_level);
++s32 psci_cpu_on(u32 function_id, u32 target_cpu, u32 pc, u32 context_id);
++s32 psci_affinity_info(u32 function_id, u32 target_affinity, u32 power_level);
+ u32 psci_migrate_info_type(void);
+ void psci_system_off(void);
+ void psci_system_reset(void);
++s32 psci_features(u32 function_id, u32 psci_fid);
++s32 psci_cpu_default_suspend(u32 function_id, u32 pc, u32 context_id);
++s32 psci_node_hw_state(u32 function_id, u32 target_cpu, u32 power_level);
++s32 psci_system_suspend(u32 function_id, u32 pc, u32 context_id);
++s32 psci_system_reset2(u32 function_id, u32 reset_type, u32 cookie);
+ #endif
+ 
+ #endif /* __ASSEMBLY__ */
+--- a/arch/arm/lib/psci-dt.c
++++ b/arch/arm/lib/psci-dt.c
+@@ -66,6 +66,8 @@ int fdt_psci(void *fdt)
+ init_psci_node:
+ #if CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT)
+ 	psci_ver = sec_firmware_support_psci_version();
++#elif defined(CONFIG_ARMV7_PSCI_1_1)
++	psci_ver = ARM_PSCI_VER_1_1;
+ #elif defined(CONFIG_ARMV7_PSCI_1_0) || defined(CONFIG_ARMV8_PSCI)
+ 	psci_ver = ARM_PSCI_VER_1_0;
+ #elif defined(CONFIG_ARMV7_PSCI_0_2)
diff --git a/package/boot/uboot-d1/patches/0042-sunxi-Enable-remoteproc-on-some-H3-boards.patch b/package/boot/uboot-d1/patches/0042-sunxi-Enable-remoteproc-on-some-H3-boards.patch
new file mode 100644
index 00000000000000..9aaee317a24503
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0042-sunxi-Enable-remoteproc-on-some-H3-boards.patch
@@ -0,0 +1,29 @@
+From 6dc0da83dba9570740365d0f1b32f91ae8ba0998 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Mon, 11 Oct 2021 03:20:28 -0500
+Subject: [PATCH 42/90] sunxi: Enable remoteproc on some H3 boards
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ configs/orangepi_one_defconfig    | 1 +
+ configs/orangepi_plus2e_defconfig | 1 +
+ 2 files changed, 2 insertions(+)
+
+--- a/configs/orangepi_one_defconfig
++++ b/configs/orangepi_one_defconfig
+@@ -6,5 +6,6 @@ CONFIG_MACH_SUN8I_H3=y
+ CONFIG_DRAM_CLK=672
+ # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+ CONFIG_SUN8I_EMAC=y
++CONFIG_REMOTEPROC_SUN6I_AR100=y
+ CONFIG_USB_EHCI_HCD=y
+ CONFIG_USB_OHCI_HCD=y
+--- a/configs/orangepi_plus2e_defconfig
++++ b/configs/orangepi_plus2e_defconfig
+@@ -12,5 +12,6 @@ CONFIG_SPL_SYS_I2C_LEGACY=y
+ CONFIG_SYS_I2C_MVTWSI=y
+ CONFIG_SUN8I_EMAC=y
+ CONFIG_SY8106A_POWER=y
++CONFIG_REMOTEPROC_SUN6I_AR100=y
+ CONFIG_USB_EHCI_HCD=y
+ CONFIG_USB_OHCI_HCD=y
diff --git a/package/boot/uboot-d1/patches/0043-sunxi-psci-Delegate-PSCI-to-SCPI.patch b/package/boot/uboot-d1/patches/0043-sunxi-psci-Delegate-PSCI-to-SCPI.patch
new file mode 100644
index 00000000000000..6d0c2b49d1b8ae
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0043-sunxi-psci-Delegate-PSCI-to-SCPI.patch
@@ -0,0 +1,497 @@
+From 650fab5c589a883b139b4164527101f9c849f1a5 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 9 Oct 2021 23:01:05 -0500
+Subject: [PATCH 43/90] sunxi: psci: Delegate PSCI to SCPI
+
+This adds a new PSCI implementation which communicates with SCP firmware
+running on the AR100 using the SCPI protocol. This allows it to support
+the full set of PSCI v1.1 features, including CPU idle states, system
+suspend, and multiple reset methods.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm/cpu/armv7/Kconfig           |   1 +
+ arch/arm/cpu/armv7/sunxi/Makefile    |   4 +
+ arch/arm/cpu/armv7/sunxi/psci-scpi.c | 451 +++++++++++++++++++++++++++
+ 3 files changed, 456 insertions(+)
+ create mode 100644 arch/arm/cpu/armv7/sunxi/psci-scpi.c
+
+--- a/arch/arm/cpu/armv7/Kconfig
++++ b/arch/arm/cpu/armv7/Kconfig
+@@ -75,6 +75,7 @@ config ARMV7_PSCI
+ choice
+ 	prompt "Supported PSCI version"
+ 	depends on ARMV7_PSCI
++	default ARMV7_PSCI_1_1 if MACH_SUN8I_H3
+ 	default ARMV7_PSCI_0_1 if ARCH_SUNXI
+ 	default ARMV7_PSCI_1_0
+ 	help
+--- a/arch/arm/cpu/armv7/sunxi/Makefile
++++ b/arch/arm/cpu/armv7/sunxi/Makefile
+@@ -13,8 +13,12 @@ obj-$(CONFIG_MACH_SUN6I)	+= sram.o
+ obj-$(CONFIG_MACH_SUN8I)	+= sram.o
+ 
+ ifndef CONFIG_SPL_BUILD
++ifdef CONFIG_MACH_SUN8I_H3
++obj-$(CONFIG_ARMV7_PSCI)	+= psci-scpi.o
++else
+ obj-$(CONFIG_ARMV7_PSCI)	+= psci.o
+ endif
++endif
+ 
+ ifdef CONFIG_SPL_BUILD
+ obj-y	+= fel_utils.o
+--- /dev/null
++++ b/arch/arm/cpu/armv7/sunxi/psci-scpi.c
+@@ -0,0 +1,451 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
++ * Copyright (C) 2018-2021 Samuel Holland <samuel@sholland.org>
++ */
++
++#include <common.h>
++#include <asm/arch/cpu.h>
++#include <asm/arch/cpucfg.h>
++#include <asm/armv7.h>
++#include <asm/gic.h>
++#include <asm/io.h>
++#include <asm/psci.h>
++#include <asm/secure.h>
++#include <asm/system.h>
++
++#define	GICD_BASE		(SUNXI_GIC400_BASE + GIC_DIST_OFFSET)
++#define	GICC_BASE		(SUNXI_GIC400_BASE + GIC_CPU_OFFSET_A15)
++
++#define HW_ON			0
++#define HW_OFF			1
++#define HW_STANDBY		2
++
++#define MPIDR_AFFLVL0(mpidr)	(mpidr & 0xf)
++#define MPIDR_AFFLVL1(mpidr)	(mpidr >> 8 & 0xf)
++
++#define SCPI_SHMEM_BASE		0x0004be00
++#define SCPI_SHMEM		((struct scpi_shmem *)SCPI_SHMEM_BASE)
++
++#define SCPI_RX_CHANNEL		1
++#define SCPI_TX_CHANNEL		0
++#define SCPI_VIRTUAL_CHANNEL	BIT(0)
++
++#define SCPI_MESSAGE_SIZE	0x100
++#define SCPI_PAYLOAD_SIZE	(SCPI_MESSAGE_SIZE - sizeof(struct scpi_header))
++
++#define SUNXI_MSGBOX_BASE	0x01c17000
++#define REMOTE_IRQ_STAT_REG	(SUNXI_MSGBOX_BASE + 0x0050)
++#define LOCAL_IRQ_STAT_REG	(SUNXI_MSGBOX_BASE + 0x0070)
++#define MSG_STAT_REG(n)		(SUNXI_MSGBOX_BASE + 0x0140 + 0x4 * (n))
++#define MSG_DATA_REG(n)		(SUNXI_MSGBOX_BASE + 0x0180 + 0x4 * (n))
++
++#define RX_IRQ(n)		BIT(0 + 2 * (n))
++#define TX_IRQ(n)		BIT(1 + 2 * (n))
++
++enum {
++	CORE_POWER_LEVEL		= 0,
++	CLUSTER_POWER_LEVEL		= 1,
++	CSS_POWER_LEVEL			= 2,
++};
++
++enum {
++	SCPI_CMD_SCP_READY		= 0x01,
++	SCPI_CMD_SET_CSS_POWER_STATE	= 0x03,
++	SCPI_CMD_GET_CSS_POWER_STATE	= 0x04,
++	SCPI_CMD_SET_SYS_POWER_STATE	= 0x05,
++};
++
++enum {
++	SCPI_E_OK			= 0,
++	SCPI_E_PARAM			= 1,
++	SCPI_E_ALIGN			= 2,
++	SCPI_E_SIZE			= 3,
++	SCPI_E_HANDLER			= 4,
++	SCPI_E_ACCESS			= 5,
++	SCPI_E_RANGE			= 6,
++	SCPI_E_TIMEOUT			= 7,
++	SCPI_E_NOMEM			= 8,
++	SCPI_E_PWRSTATE			= 9,
++	SCPI_E_SUPPORT			= 10,
++	SCPI_E_DEVICE			= 11,
++	SCPI_E_BUSY			= 12,
++	SCPI_E_OS			= 13,
++	SCPI_E_DATA			= 14,
++	SCPI_E_STATE			= 15,
++};
++
++enum {
++	SCPI_POWER_ON			= 0x00,
++	SCPI_POWER_RETENTION		= 0x01,
++	SCPI_POWER_OFF			= 0x03,
++};
++
++enum {
++	SCPI_SYSTEM_SHUTDOWN		= 0x00,
++	SCPI_SYSTEM_REBOOT		= 0x01,
++	SCPI_SYSTEM_RESET		= 0x02,
++};
++
++struct scpi_header {
++	u8			command;
++	u8			sender;
++	u16			size;
++	u32			status;
++};
++
++struct scpi_message {
++	struct scpi_header	header;
++	u8			payload[SCPI_PAYLOAD_SIZE];
++};
++
++struct scpi_shmem {
++	struct scpi_message	rx;
++	struct scpi_message	tx;
++};
++
++static bool __secure_data gic_dist_init;
++
++static u32 __secure_data lock;
++
++static inline u32 __secure read_mpidr(void)
++{
++	u32 val;
++
++	asm volatile ("mrc p15, 0, %0, c0, c0, 5" : "=r" (val));
++
++	return val;
++}
++
++static void __secure scpi_begin_command(void)
++{
++	u32 mpidr = read_mpidr();
++
++	do {
++		while (readl(&lock));
++		writel(mpidr, &lock);
++		dsb();
++	} while (readl(&lock) != mpidr);
++	while (readl(REMOTE_IRQ_STAT_REG) & RX_IRQ(SCPI_TX_CHANNEL));
++}
++
++static void __secure scpi_send_command(void)
++{
++	writel(SCPI_VIRTUAL_CHANNEL, MSG_DATA_REG(SCPI_TX_CHANNEL));
++}
++
++static void __secure scpi_wait_response(void)
++{
++	while (!readl(MSG_STAT_REG(SCPI_RX_CHANNEL)));
++}
++
++static void __secure scpi_end_command(void)
++{
++	while (readl(MSG_STAT_REG(SCPI_RX_CHANNEL)))
++		readl(MSG_DATA_REG(SCPI_RX_CHANNEL));
++	writel(RX_IRQ(SCPI_RX_CHANNEL), LOCAL_IRQ_STAT_REG);
++	writel(0, &lock);
++}
++
++static void __secure scpi_set_css_power_state(u32 target_cpu, u32 core_state,
++					      u32 cluster_state, u32 css_state)
++{
++	struct scpi_shmem *shmem = SCPI_SHMEM;
++
++	scpi_begin_command();
++
++	shmem->tx.header.command = SCPI_CMD_SET_CSS_POWER_STATE;
++	shmem->tx.header.size = 4;
++
++	shmem->tx.payload[0] = target_cpu    >> 4 | target_cpu;
++	shmem->tx.payload[1] = cluster_state << 4 | core_state;
++	shmem->tx.payload[2] = css_state;
++	shmem->tx.payload[3] = 0;
++
++	scpi_send_command();
++	scpi_end_command();
++}
++
++static s32 __secure scpi_get_css_power_state(u32 target_cpu, u8 *core_states,
++					     u8 *cluster_state)
++{
++	struct scpi_shmem *shmem = SCPI_SHMEM;
++	u32 cluster = MPIDR_AFFLVL1(target_cpu);
++	u32 offset;
++	s32 ret;
++
++	scpi_begin_command();
++
++	shmem->tx.header.command = SCPI_CMD_GET_CSS_POWER_STATE;
++	shmem->tx.header.size = 0;
++
++	scpi_send_command();
++	scpi_wait_response();
++
++	for (offset = 0; offset < shmem->rx.header.size; offset += 2) {
++		if ((shmem->rx.payload[offset] & 0xf) == cluster) {
++			*cluster_state = shmem->rx.payload[offset+0] >> 4;
++			*core_states   = shmem->rx.payload[offset+1];
++
++			break;
++		}
++	}
++
++	ret = shmem->rx.header.status;
++
++	scpi_end_command();
++
++	return ret;
++}
++
++static s32 __secure scpi_set_sys_power_state(u32 sys_state)
++{
++	struct scpi_shmem *shmem = SCPI_SHMEM;
++	s32 ret;
++
++	scpi_begin_command();
++
++	shmem->tx.header.command = SCPI_CMD_SET_SYS_POWER_STATE;
++	shmem->tx.header.size = 1;
++
++	shmem->tx.payload[0] = sys_state;
++
++	scpi_send_command();
++	scpi_wait_response();
++
++	ret = shmem->rx.header.status;
++
++	scpi_end_command();
++
++	return ret;
++}
++
++void psci_enable_smp(void);
++
++static s32 __secure psci_suspend_common(u32 pc, u32 context_id, u32 core_state,
++					u32 cluster_state, u32 css_state)
++
++{
++	u32 target_cpu = read_mpidr();
++
++	if (core_state == SCPI_POWER_OFF)
++		psci_save(MPIDR_AFFLVL0(target_cpu), pc, context_id);
++	if (css_state == SCPI_POWER_OFF)
++		gic_dist_init = true;
++
++	scpi_set_css_power_state(target_cpu, core_state,
++				 cluster_state, css_state);
++
++	psci_cpu_off_common();
++
++	wfi();
++
++	psci_enable_smp();
++
++	return ARM_PSCI_RET_SUCCESS;
++}
++
++u32 __secure psci_version(void)
++{
++	return ARM_PSCI_VER_1_1;
++}
++
++s32 __secure psci_cpu_suspend(u32 __always_unused function_id,
++			      u32 power_state, u32 pc, u32 context_id)
++{
++	return psci_suspend_common(pc, context_id,
++				   power_state >> 0 & 0xf,
++				   power_state >> 4 & 0xf,
++				   power_state >> 8 & 0xf);
++}
++
++s32 __secure psci_cpu_off(void)
++{
++	u32 pc = 0, context_id = 0;
++
++	return psci_suspend_common(pc, context_id, SCPI_POWER_OFF,
++				   SCPI_POWER_OFF, SCPI_POWER_ON);
++}
++
++s32 __secure psci_cpu_on(u32 __always_unused function_id,
++			 u32 target_cpu, u32 pc, u32 context_id)
++{
++	psci_save(MPIDR_AFFLVL0(target_cpu), pc, context_id);
++
++	scpi_set_css_power_state(target_cpu, SCPI_POWER_ON,
++				 SCPI_POWER_ON, SCPI_POWER_ON);
++
++	return ARM_PSCI_RET_SUCCESS;
++}
++
++s32 __secure psci_affinity_info(u32 function_id,
++				u32 target_cpu, u32 power_level)
++{
++	if (power_level != CORE_POWER_LEVEL)
++		return ARM_PSCI_RET_INVAL;
++
++	/* This happens to have the same HW_ON/HW_OFF encoding. */
++	return psci_node_hw_state(function_id, target_cpu, power_level);
++}
++
++void __secure psci_system_off(void)
++{
++	scpi_set_sys_power_state(SCPI_SYSTEM_SHUTDOWN);
++
++	/* Wait to be turned off. */
++	for (;;) wfi();
++}
++
++void __secure psci_system_reset(void)
++{
++	scpi_set_sys_power_state(SCPI_SYSTEM_REBOOT);
++
++	/* Wait to be turned off. */
++	for (;;) wfi();
++}
++
++s32 __secure psci_features(u32 __always_unused function_id,
++			   u32 psci_fid)
++{
++	switch (psci_fid) {
++	case ARM_PSCI_0_2_FN_PSCI_VERSION:
++	case ARM_PSCI_0_2_FN_CPU_SUSPEND:
++	case ARM_PSCI_0_2_FN_CPU_OFF:
++	case ARM_PSCI_0_2_FN_CPU_ON:
++	case ARM_PSCI_0_2_FN_AFFINITY_INFO:
++	case ARM_PSCI_0_2_FN_SYSTEM_OFF:
++	case ARM_PSCI_0_2_FN_SYSTEM_RESET:
++	case ARM_PSCI_1_0_FN_PSCI_FEATURES:
++	case ARM_PSCI_1_0_FN_CPU_DEFAULT_SUSPEND:
++	case ARM_PSCI_1_0_FN_NODE_HW_STATE:
++	case ARM_PSCI_1_0_FN_SYSTEM_SUSPEND:
++	case ARM_PSCI_1_1_FN_SYSTEM_RESET2:
++		return ARM_PSCI_RET_SUCCESS;
++	default:
++		return ARM_PSCI_RET_NI;
++	}
++}
++
++s32 __secure psci_cpu_default_suspend(u32 __always_unused function_id,
++				      u32 pc, u32 context_id)
++{
++	return psci_suspend_common(pc, context_id, SCPI_POWER_OFF,
++				   SCPI_POWER_OFF, SCPI_POWER_RETENTION);
++}
++
++s32 __secure psci_node_hw_state(u32 __always_unused function_id,
++				u32 target_cpu, u32 power_level)
++{
++	u32 core = MPIDR_AFFLVL0(target_cpu);
++	u8 core_states, cluster_state;
++
++	if (power_level >= CSS_POWER_LEVEL)
++		return HW_ON;
++	if (scpi_get_css_power_state(target_cpu, &core_states, &cluster_state))
++		return ARM_PSCI_RET_NI;
++	if (power_level == CLUSTER_POWER_LEVEL) {
++		if (cluster_state == SCPI_POWER_ON)
++			return HW_ON;
++		if (cluster_state < SCPI_POWER_OFF)
++			return HW_STANDBY;
++		return HW_OFF;
++	}
++
++	return (core_states & BIT(core)) ? HW_ON : HW_OFF;
++}
++
++s32 __secure psci_system_suspend(u32 __always_unused function_id,
++				 u32 pc, u32 context_id)
++{
++	return psci_suspend_common(pc, context_id, SCPI_POWER_OFF,
++				   SCPI_POWER_OFF, SCPI_POWER_OFF);
++}
++
++s32 __secure psci_system_reset2(u32 __always_unused function_id,
++				u32 reset_type, u32 cookie)
++{
++	s32 ret;
++
++	if (reset_type)
++		return ARM_PSCI_RET_INVAL;
++
++	ret = scpi_set_sys_power_state(SCPI_SYSTEM_RESET);
++	if (ret)
++		return ARM_PSCI_RET_INVAL;
++
++	/* Wait to be turned off. */
++	for (;;) wfi();
++}
++
++/*
++ * R40 is different from other single cluster SoCs. The secondary core
++ * entry address register is in the SRAM controller address range.
++ */
++#define SUN8I_R40_SRAMC_SOFT_ENTRY_REG0		(0xbc)
++
++#ifdef CONFIG_MACH_SUN8I_R40
++/* secondary core entry address is programmed differently on R40 */
++static void __secure sunxi_set_entry_address(void *entry)
++{
++	writel((u32)entry,
++	       SUNXI_SRAMC_BASE + SUN8I_R40_SRAMC_SOFT_ENTRY_REG0);
++}
++#else
++static void __secure sunxi_set_entry_address(void *entry)
++{
++	struct sunxi_cpucfg_reg *cpucfg =
++		(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
++
++	writel((u32)entry, &cpucfg->priv0);
++
++#ifdef CONFIG_MACH_SUN8I_H3
++	/* Redirect CPU 0 to the secure monitor via the resume shim. */
++	writel(0x16aaefe8, &cpucfg->super_standy_flag);
++	writel(0xaa16efe8, &cpucfg->super_standy_flag);
++	writel(SUNXI_RESUME_BASE, &cpucfg->priv1);
++#endif
++}
++#endif
++
++void __secure psci_arch_init(void)
++{
++	static bool __secure_data one_time_init = true;
++
++	if (one_time_init) {
++		/* Set secondary core power-on PC. */
++		sunxi_set_entry_address(psci_cpu_entry);
++
++		/* Wait for the SCP firmware to boot. */
++		scpi_begin_command();
++		scpi_wait_response();
++		scpi_end_command();
++
++		one_time_init = false;
++	}
++
++	/*
++	 * Copied from arch/arm/cpu/armv7/virt-v7.c
++	 * See also gic_resume() in arch/arm/mach-imx/mx7/psci-mx7.c
++	 */
++	if (gic_dist_init) {
++		u32 i, itlinesnr;
++
++		/* enable the GIC distributor */
++		writel(readl(GICD_BASE + GICD_CTLR) | 0x03, GICD_BASE + GICD_CTLR);
++
++		/* TYPER[4:0] contains an encoded number of available interrupts */
++		itlinesnr = readl(GICD_BASE + GICD_TYPER) & 0x1f;
++
++		/* set all bits in the GIC group registers to one to allow access
++		 * from non-secure state. The first 32 interrupts are private per
++		 * CPU and will be set later when enabling the GIC for each core
++		 */
++		for (i = 1; i <= itlinesnr; i++)
++			writel((unsigned)-1, GICD_BASE + GICD_IGROUPRn + 4 * i);
++
++		gic_dist_init = false;
++	}
++
++	/* Be cool with non-secure. */
++	writel(0xff, GICC_BASE + GICC_PMR);
++}
diff --git a/package/boot/uboot-d1/patches/0044-sunxi-Enable-SCP-SCPI-on-A33-as-well.patch b/package/boot/uboot-d1/patches/0044-sunxi-Enable-SCP-SCPI-on-A33-as-well.patch
new file mode 100644
index 00000000000000..1c677a449f4d1d
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0044-sunxi-Enable-SCP-SCPI-on-A33-as-well.patch
@@ -0,0 +1,95 @@
+From 5a7a91bf9a78a3a73e26d6de975261e62f9fb127 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Wed, 8 Jun 2022 07:55:54 -0500
+Subject: [PATCH 44/90] sunxi: Enable SCP/SCPI on A33 as well
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm/cpu/armv7/Kconfig           |  2 +-
+ arch/arm/cpu/armv7/sunxi/Makefile    |  2 +-
+ arch/arm/cpu/armv7/sunxi/psci-scpi.c |  4 ++++
+ arch/arm/dts/sun8i-a23-a33.dtsi      | 14 ++++++++++++++
+ arch/arm/dts/sunxi-u-boot.dtsi       |  4 ++--
+ 5 files changed, 22 insertions(+), 4 deletions(-)
+
+--- a/arch/arm/cpu/armv7/Kconfig
++++ b/arch/arm/cpu/armv7/Kconfig
+@@ -75,7 +75,7 @@ config ARMV7_PSCI
+ choice
+ 	prompt "Supported PSCI version"
+ 	depends on ARMV7_PSCI
+-	default ARMV7_PSCI_1_1 if MACH_SUN8I_H3
++	default ARMV7_PSCI_1_1 if MACH_SUN8I_A33 || MACH_SUN8I_H3
+ 	default ARMV7_PSCI_0_1 if ARCH_SUNXI
+ 	default ARMV7_PSCI_1_0
+ 	help
+--- a/arch/arm/cpu/armv7/sunxi/Makefile
++++ b/arch/arm/cpu/armv7/sunxi/Makefile
+@@ -13,7 +13,7 @@ obj-$(CONFIG_MACH_SUN6I)	+= sram.o
+ obj-$(CONFIG_MACH_SUN8I)	+= sram.o
+ 
+ ifndef CONFIG_SPL_BUILD
+-ifdef CONFIG_MACH_SUN8I_H3
++ifneq ($(CONFIG_MACH_SUN8I_A33)$(CONFIG_MACH_SUN8I_H3),)
+ obj-$(CONFIG_ARMV7_PSCI)	+= psci-scpi.o
+ else
+ obj-$(CONFIG_ARMV7_PSCI)	+= psci.o
+--- a/arch/arm/cpu/armv7/sunxi/psci-scpi.c
++++ b/arch/arm/cpu/armv7/sunxi/psci-scpi.c
+@@ -24,7 +24,11 @@
+ #define MPIDR_AFFLVL0(mpidr)	(mpidr & 0xf)
+ #define MPIDR_AFFLVL1(mpidr)	(mpidr >> 8 & 0xf)
+ 
++#if defined(CONFIG_MACH_SUN8I_H3)
+ #define SCPI_SHMEM_BASE		0x0004be00
++#else
++#define SCPI_SHMEM_BASE		0x00053e00
++#endif
+ #define SCPI_SHMEM		((struct scpi_shmem *)SCPI_SHMEM_BASE)
+ 
+ #define SCPI_RX_CHANNEL		1
+--- a/arch/arm/dts/sun8i-a23-a33.dtsi
++++ b/arch/arm/dts/sun8i-a23-a33.dtsi
+@@ -138,6 +138,14 @@
+ 			#size-cells = <1>;
+ 			ranges;
+ 
++			sram_a2: sram@40000 {
++				compatible = "mmio-sram";
++				reg = <0x00040000 0x14000>;
++				#address-cells = <1>;
++				#size-cells = <1>;
++				ranges = <0 0x00040000 0x14000>;
++			};
++
+ 			sram_c: sram@1d00000 {
+ 				compatible = "mmio-sram";
+ 				reg = <0x01d00000 0x80000>;
+@@ -847,5 +855,11 @@
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+ 		};
++
++		remoteproc@1f01c00 {
++			compatible = "allwinner,sun6i-a31-ar100";
++			reg = <0x01f01c00 0x400>;
++			sram = <&sram_a2>;
++		};
+ 	};
+ };
+--- a/arch/arm/dts/sunxi-u-boot.dtsi
++++ b/arch/arm/dts/sunxi-u-boot.dtsi
+@@ -6,11 +6,11 @@
+ #define ARCH "arm"
+ #endif
+ 
++#if defined(CONFIG_ARMV7_PSCI) && (defined(CONFIG_MACH_SUN8I_A33) || defined(CONFIG_MACH_SUN8I_H3))
+ #if defined(CONFIG_MACH_SUN8I_H3)
+-#ifdef CONFIG_ARMV7_PSCI
+ #define RESUME_ADDR	SUNXI_RESUME_BASE
+-#define SCP_ADDR	SUNXI_SCP_BASE
+ #endif
++#define SCP_ADDR	SUNXI_SCP_BASE
+ #elif defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN50I_H5)
+ #define BL31_ADDR	0x00044000
+ #define SCP_ADDR	0x00050000
diff --git a/package/boot/uboot-d1/patches/0045-phy-sun4i-usb-Use-DM_GPIO-for-id-vbus_det-GPIOs.patch b/package/boot/uboot-d1/patches/0045-phy-sun4i-usb-Use-DM_GPIO-for-id-vbus_det-GPIOs.patch
new file mode 100644
index 00000000000000..8da5fdb3e1ac71
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0045-phy-sun4i-usb-Use-DM_GPIO-for-id-vbus_det-GPIOs.patch
@@ -0,0 +1,216 @@
+From afa281decfbb174f57341897e0ad50ee9ad3564f Mon Sep 17 00:00:00 2001
+From: Zoltan HERPAI <wigyori@uid0.hu>
+Date: Tue, 6 Jun 2023 17:59:24 +0000
+Subject: [PATCH 45/90] phy: sun4i-usb: Use DM_GPIO for id/vbus_det GPIOs
+
+Now that the sunxi_gpio driver handles pull-up/down via the driver
+model, we can switch to DM_GPIO for these pins with no loss in
+functionality. Since the driver now gets its pin configuration from
+the device tree, we can remove the Kconfig symbols.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+
+Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
+---
+ arch/arm/dts/sun5i-a13-ampe-a76.dts           |  6 ++
+ .../sun6i-a31s-yones-toptech-bs1078-v2.dts    |  1 +
+ arch/arm/dts/sun8i-a33-sinlinx-sina33.dts     |  1 +
+ arch/arm/mach-sunxi/Kconfig                   | 14 ----
+ drivers/phy/allwinner/phy-sun4i-usb.c         | 71 ++++---------------
+ 5 files changed, 22 insertions(+), 71 deletions(-)
+
+--- a/arch/arm/dts/sun5i-a13-ampe-a76.dts
++++ b/arch/arm/dts/sun5i-a13-ampe-a76.dts
+@@ -8,6 +8,8 @@
+ /dts-v1/;
+ #include "sun5i-a13.dtsi"
+ 
++#include <dt-bindings/gpio/gpio.h>
++
+ / {
+ 	model = "Ampe A76";
+ 	compatible = "ampe,a76", "allwinner,sun5i-a13";
+@@ -26,3 +28,7 @@
+ 	pinctrl-0 = <&uart1_pg_pins>;
+ 	status = "okay";
+ };
++
++&usbphy {
++	usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
++};
+--- a/arch/arm/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts
++++ b/arch/arm/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts
+@@ -176,6 +176,7 @@
+ };
+ 
+ &usbphy {
++	usb0_id_det-gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */
+ 	usb1_vbus-supply = <&reg_dldo1>;
+ 	usb2_vbus-supply = <&reg_dc1sw>;
+ 	status = "okay";
+--- a/arch/arm/dts/sun8i-a33-sinlinx-sina33.dts
++++ b/arch/arm/dts/sun8i-a33-sinlinx-sina33.dts
+@@ -271,5 +271,6 @@
+ 
+ &usbphy {
+ 	status = "okay";
++	usb0_id_det-gpios = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */
+ 	usb1_vbus-supply = <&reg_vcc5v0>; /* USB1 VBUS is always on */
+ };
+--- a/arch/arm/mach-sunxi/Kconfig
++++ b/arch/arm/mach-sunxi/Kconfig
+@@ -655,20 +655,6 @@ config MMC_SUNXI_SLOT_EXTRA
+ 	slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
+ 	support for this.
+ 
+-config USB0_VBUS_DET
+-	string "Vbus detect pin for usb0 (otg)"
+-	default ""
+-	---help---
+-	Set the Vbus detect pin for usb0 (otg). This takes a string in the
+-	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
+-
+-config USB0_ID_DET
+-	string "ID detect pin for usb0 (otg)"
+-	default ""
+-	---help---
+-	Set the ID detect pin for usb0 (otg). This takes a string in the
+-	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
+-
+ config I2C0_ENABLE
+ 	bool "Enable I2C/TWI controller 0"
+ 	default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
+--- a/drivers/phy/allwinner/phy-sun4i-usb.c
++++ b/drivers/phy/allwinner/phy-sun4i-usb.c
+@@ -96,32 +96,8 @@ struct sun4i_usb_phy_cfg {
+ 	int missing_phys;
+ };
+ 
+-struct sun4i_usb_phy_info {
+-	const char *gpio_vbus_det;
+-	const char *gpio_id_det;
+-} phy_info[] = {
+-	{
+-		.gpio_vbus_det = CONFIG_USB0_VBUS_DET,
+-		.gpio_id_det = CONFIG_USB0_ID_DET,
+-	},
+-	{
+-		.gpio_vbus_det = NULL,
+-		.gpio_id_det = NULL,
+-	},
+-	{
+-		.gpio_vbus_det = NULL,
+-		.gpio_id_det = NULL,
+-	},
+-	{
+-		.gpio_vbus_det = NULL,
+-		.gpio_id_det = NULL,
+-	},
+-};
+-
+ struct sun4i_usb_phy_plat {
+ 	void __iomem *pmu;
+-	struct gpio_desc gpio_vbus_det;
+-	struct gpio_desc gpio_id_det;
+ 	struct clk clocks;
+ 	struct reset_ctl resets;
+ 	struct udevice *vbus;
+@@ -132,6 +108,8 @@ struct sun4i_usb_phy_data {
+ 	void __iomem *base;
+ 	const struct sun4i_usb_phy_cfg *cfg;
+ 	struct sun4i_usb_phy_plat *usb_phy;
++	struct gpio_desc id_det_gpio;
++	struct gpio_desc vbus_det_gpio;
+ 	struct udevice *vbus_power_supply;
+ };
+ 
+@@ -393,11 +371,10 @@ static int sun4i_usb_phy_xlate(struct ph
+ int sun4i_usb_phy_vbus_detect(struct phy *phy)
+ {
+ 	struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
+-	struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
+ 	int err = 1, retries = 3;
+ 
+-	if (dm_gpio_is_valid(&usb_phy->gpio_vbus_det)) {
+-		err = dm_gpio_get_value(&usb_phy->gpio_vbus_det);
++	if (dm_gpio_is_valid(&data->vbus_det_gpio)) {
++		err = dm_gpio_get_value(&data->vbus_det_gpio);
+ 		/*
+ 		 * Vbus may have been provided by the board and just turned off
+ 		 * some milliseconds ago on reset. What we're measuring then is
+@@ -405,7 +382,7 @@ int sun4i_usb_phy_vbus_detect(struct phy
+ 		 */
+ 		while (err > 0 && retries--) {
+ 			mdelay(100);
+-			err = dm_gpio_get_value(&usb_phy->gpio_vbus_det);
++			err = dm_gpio_get_value(&data->vbus_det_gpio);
+ 		}
+ 	} else if (data->vbus_power_supply) {
+ 		err = regulator_get_enable(data->vbus_power_supply);
+@@ -417,12 +394,11 @@ int sun4i_usb_phy_vbus_detect(struct phy
+ int sun4i_usb_phy_id_detect(struct phy *phy)
+ {
+ 	struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
+-	struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
+ 
+-	if (!dm_gpio_is_valid(&usb_phy->gpio_id_det))
+-		return -1;
++	if (!dm_gpio_is_valid(&data->id_det_gpio))
++		return -EOPNOTSUPP;
+ 
+-	return dm_gpio_get_value(&usb_phy->gpio_id_det);
++	return dm_gpio_get_value(&data->id_det_gpio);
+ }
+ 
+ void sun4i_usb_phy_set_squelch_detect(struct phy *phy, bool enabled)
+@@ -452,13 +428,18 @@ static int sun4i_usb_phy_probe(struct ud
+ 	if (IS_ERR(data->base))
+ 		return PTR_ERR(data->base);
+ 
++	gpio_request_by_name(dev, "usb0_id_det-gpios", 0, &data->id_det_gpio,
++			     GPIOD_IS_IN | GPIOD_PULL_UP);
++
++	gpio_request_by_name(dev, "usb0_vbus_det-gpios", 0, &data->vbus_det_gpio,
++			     GPIOD_IS_IN);
++
+ 	device_get_supply_regulator(dev, "usb0_vbus_power-supply",
+ 				    &data->vbus_power_supply);
+ 
+ 	data->usb_phy = plat;
+ 	for (i = 0; i < data->cfg->num_phys; i++) {
+ 		struct sun4i_usb_phy_plat *phy = &plat[i];
+-		struct sun4i_usb_phy_info *info = &phy_info[i];
+ 		char name[20];
+ 
+ 		if (data->cfg->missing_phys & BIT(i))
+@@ -472,30 +453,6 @@ static int sun4i_usb_phy_probe(struct ud
+ 				return ret;
+ 		}
+ 
+-		ret = dm_gpio_lookup_name(info->gpio_vbus_det,
+-					  &phy->gpio_vbus_det);
+-		if (ret == 0) {
+-			ret = dm_gpio_request(&phy->gpio_vbus_det,
+-					      "usb_vbus_det");
+-			if (ret)
+-				return ret;
+-			ret = dm_gpio_set_dir_flags(&phy->gpio_vbus_det,
+-						    GPIOD_IS_IN);
+-			if (ret)
+-				return ret;
+-		}
+-
+-		ret = dm_gpio_lookup_name(info->gpio_id_det, &phy->gpio_id_det);
+-		if (ret == 0) {
+-			ret = dm_gpio_request(&phy->gpio_id_det, "usb_id_det");
+-			if (ret)
+-				return ret;
+-			ret = dm_gpio_set_dir_flags(&phy->gpio_id_det,
+-						GPIOD_IS_IN | GPIOD_PULL_UP);
+-			if (ret)
+-				return ret;
+-		}
+-
+ 		if (data->cfg->dedicated_clocks)
+ 			snprintf(name, sizeof(name), "usb%d_phy", i);
+ 		else
diff --git a/package/boot/uboot-d1/patches/0046-ARM-dts-sunxi-Add-AXP221-and-AXP809-GPIO-nodes.patch b/package/boot/uboot-d1/patches/0046-ARM-dts-sunxi-Add-AXP221-and-AXP809-GPIO-nodes.patch
new file mode 100644
index 00000000000000..97b421eb9d1159
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0046-ARM-dts-sunxi-Add-AXP221-and-AXP809-GPIO-nodes.patch
@@ -0,0 +1,45 @@
+From 9e34036e651528df9575c2ffb38d78ae1f613481 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 21 Aug 2021 17:11:54 -0500
+Subject: [PATCH 46/90] ARM: dts: sunxi: Add AXP221 and AXP809 GPIO nodes
+
+These PMICs each have two GPIO pins, and are supported by the axp_gpio
+driver. In order to convert the axp_gpio driver to probe using the
+device tree, the corresponding device tree nodes must be present. Add
+them, following the same binding as the AXP209 and AXP813.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm/dts/axp22x.dtsi | 6 ++++++
+ arch/arm/dts/axp809.dtsi | 7 +++++++
+ 2 files changed, 13 insertions(+)
+
+--- a/arch/arm/dts/axp22x.dtsi
++++ b/arch/arm/dts/axp22x.dtsi
+@@ -67,6 +67,12 @@
+ 		status = "disabled";
+ 	};
+ 
++	axp_gpio: gpio {
++		compatible = "x-powers,axp221-gpio";
++		gpio-controller;
++		#gpio-cells = <2>;
++	};
++
+ 	regulators {
+ 		/* Default work frequency for buck regulators */
+ 		x-powers,dcdc-freq = <3000>;
+--- a/arch/arm/dts/axp809.dtsi
++++ b/arch/arm/dts/axp809.dtsi
+@@ -50,4 +50,11 @@
+ 	compatible = "x-powers,axp809";
+ 	interrupt-controller;
+ 	#interrupt-cells = <1>;
++
++	axp_gpio: gpio {
++		compatible = "x-powers,axp809-gpio",
++			     "x-powers,axp221-gpio";
++		gpio-controller;
++		#gpio-cells = <2>;
++	};
+ };
diff --git a/package/boot/uboot-d1/patches/0047-gpio-axp-Consistently-use-the-axp_gpio-order.patch b/package/boot/uboot-d1/patches/0047-gpio-axp-Consistently-use-the-axp_gpio-order.patch
new file mode 100644
index 00000000000000..2deaadd584b3e2
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0047-gpio-axp-Consistently-use-the-axp_gpio-order.patch
@@ -0,0 +1,58 @@
+From 7e85c2d6516e47b537b27132d1946d1eab3b8923 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Fri, 27 Aug 2021 17:39:36 -0500
+Subject: [PATCH 47/90] gpio: axp: Consistently use the "axp_gpio" order
+
+This is less confusing than half of the driver using "axp_gpio" and the
+other half using "gpio_axp".
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/gpio/axp_gpio.c | 16 ++++++++--------
+ 1 file changed, 8 insertions(+), 8 deletions(-)
+
+--- a/drivers/gpio/axp_gpio.c
++++ b/drivers/gpio/axp_gpio.c
+@@ -89,14 +89,14 @@ static int axp_gpio_set_value(struct ude
+ 					 AXP_GPIO_CTRL_OUTPUT_LOW);
+ }
+ 
+-static const struct dm_gpio_ops gpio_axp_ops = {
++static const struct dm_gpio_ops axp_gpio_ops = {
+ 	.direction_input	= axp_gpio_direction_input,
+ 	.direction_output	= axp_gpio_direction_output,
+ 	.get_value		= axp_gpio_get_value,
+ 	.set_value		= axp_gpio_set_value,
+ };
+ 
+-static int gpio_axp_probe(struct udevice *dev)
++static int axp_gpio_probe(struct udevice *dev)
+ {
+ 	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ 
+@@ -107,11 +107,11 @@ static int gpio_axp_probe(struct udevice
+ 	return 0;
+ }
+ 
+-U_BOOT_DRIVER(gpio_axp) = {
+-	.name	= "gpio_axp",
+-	.id	= UCLASS_GPIO,
+-	.ops	= &gpio_axp_ops,
+-	.probe	= gpio_axp_probe,
++U_BOOT_DRIVER(axp_gpio) = {
++	.name		= "axp_gpio",
++	.id		= UCLASS_GPIO,
++	.probe		= axp_gpio_probe,
++	.ops		= &axp_gpio_ops,
+ };
+ 
+ int axp_gpio_init(void)
+@@ -124,7 +124,7 @@ int axp_gpio_init(void)
+ 		return ret;
+ 
+ 	/* There is no devicetree support for the axp yet, so bind directly */
+-	ret = device_bind_driver(dm_root(), "gpio_axp", "AXP-gpio", &dev);
++	ret = device_bind_driver(dm_root(), "axp_gpio", "AXP-gpio", &dev);
+ 	if (ret)
+ 		return ret;
+ 
diff --git a/package/boot/uboot-d1/patches/0048-gpio-axp-Bind-via-device-tree.patch b/package/boot/uboot-d1/patches/0048-gpio-axp-Bind-via-device-tree.patch
new file mode 100644
index 00000000000000..dbc61875d2cb77
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0048-gpio-axp-Bind-via-device-tree.patch
@@ -0,0 +1,139 @@
+From a39b1bd1ad0babb355a5cb6f6a3bd8e378433b54 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Fri, 27 Aug 2021 21:43:19 -0500
+Subject: [PATCH 48/90] gpio: axp: Bind via device tree
+
+Now that the PMIC has a DM driver and binds device tree subnodes, the
+GPIO device can be bound that way, instead of from inside board code.
+
+Since the driver still uses the single set of register definitions from
+axpXXX.h (as selected by AXPxxx_POWER), it does not differentiate among
+the supported compatibles.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm/include/asm/arch-sunxi/gpio.h |  6 -----
+ arch/arm/mach-sunxi/Kconfig            |  6 -----
+ board/sunxi/board.c                    |  4 ---
+ drivers/gpio/Kconfig                   |  8 ++++++
+ drivers/gpio/axp_gpio.c                | 34 +++++++++++---------------
+ 5 files changed, 22 insertions(+), 36 deletions(-)
+
+--- a/arch/arm/include/asm/arch-sunxi/gpio.h
++++ b/arch/arm/include/asm/arch-sunxi/gpio.h
+@@ -219,10 +219,4 @@ void sunxi_gpio_set_pull(u32 pin, u32 va
+ void sunxi_gpio_set_pull_bank(struct sunxi_gpio *pio, int bank_offset, u32 val);
+ int sunxi_name_to_gpio(const char *name);
+ 
+-#if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO
+-int axp_gpio_init(void);
+-#else
+-static inline int axp_gpio_init(void) { return 0; }
+-#endif
+-
+ #endif /* _SUNXI_GPIO_H */
+--- a/arch/arm/mach-sunxi/Kconfig
++++ b/arch/arm/mach-sunxi/Kconfig
+@@ -682,12 +682,6 @@ config R_I2C_ENABLE
+ 	Set this to y to enable the I2C controller which is part of the PRCM.
+ endif
+ 
+-config AXP_GPIO
+-	bool "Enable support for gpio-s on axp PMICs"
+-	depends on AXP_PMIC_BUS
+-	---help---
+-	Say Y here to enable support for the gpio pins of the axp PMIC ICs.
+-
+ config AXP_DISABLE_BOOT_ON_POWERON
+ 	bool "Disable device boot on power plug-in"
+ 	depends on AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER
+--- a/board/sunxi/board.c
++++ b/board/sunxi/board.c
+@@ -221,10 +221,6 @@ int board_init(void)
+ 	}
+ #endif /* !CONFIG_ARM64 && !CONFIG_MACH_SUNIV */
+ 
+-	ret = axp_gpio_init();
+-	if (ret)
+-		return ret;
+-
+ 	/* strcmp() would look better, but doesn't get optimised away. */
+ 	if (CONFIG_SATAPWR[0]) {
+ 		satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
+--- a/drivers/gpio/Kconfig
++++ b/drivers/gpio/Kconfig
+@@ -104,6 +104,14 @@ config ALTERA_PIO
+ 	  Select this to enable PIO for Altera devices. Please find
+ 	  details on the "Embedded Peripherals IP User Guide" of Altera.
+ 
++config AXP_GPIO
++	bool "X-Powers AXP PMICs GPIO driver"
++	depends on DM_GPIO && PMIC_AXP
++	depends on AXP_PMIC_BUS
++	help
++	  This driver supports the GPIO pins on
++	  X-Powers AXP152, AXP2xx, and AXP8xx PMICs.
++
+ config BCM2835_GPIO
+ 	bool "BCM2835 GPIO driver"
+ 	depends on DM_GPIO
+--- a/drivers/gpio/axp_gpio.c
++++ b/drivers/gpio/axp_gpio.c
+@@ -10,9 +10,6 @@
+ #include <asm/gpio.h>
+ #include <axp_pmic.h>
+ #include <dm.h>
+-#include <dm/device-internal.h>
+-#include <dm/lists.h>
+-#include <dm/root.h>
+ #include <errno.h>
+ 
+ #define AXP_GPIO_PREFIX			"AXP0-"
+@@ -99,6 +96,11 @@ static const struct dm_gpio_ops axp_gpio
+ static int axp_gpio_probe(struct udevice *dev)
+ {
+ 	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
++	int ret;
++
++	ret = pmic_bus_init();
++	if (ret)
++		return ret;
+ 
+ 	/* Tell the uclass how many GPIOs we have */
+ 	uc_priv->bank_name = AXP_GPIO_PREFIX;
+@@ -107,26 +109,18 @@ static int axp_gpio_probe(struct udevice
+ 	return 0;
+ }
+ 
++static const struct udevice_id axp_gpio_ids[] = {
++	{ .compatible = "x-powers,axp152-gpio" },
++	{ .compatible = "x-powers,axp209-gpio" },
++	{ .compatible = "x-powers,axp221-gpio" },
++	{ .compatible = "x-powers,axp813-gpio" },
++	{ }
++};
++
+ U_BOOT_DRIVER(axp_gpio) = {
+ 	.name		= "axp_gpio",
+ 	.id		= UCLASS_GPIO,
++	.of_match	= axp_gpio_ids,
+ 	.probe		= axp_gpio_probe,
+ 	.ops		= &axp_gpio_ops,
+ };
+-
+-int axp_gpio_init(void)
+-{
+-	struct udevice *dev;
+-	int ret;
+-
+-	ret = pmic_bus_init();
+-	if (ret)
+-		return ret;
+-
+-	/* There is no devicetree support for the axp yet, so bind directly */
+-	ret = device_bind_driver(dm_root(), "axp_gpio", "AXP-gpio", &dev);
+-	if (ret)
+-		return ret;
+-
+-	return 0;
+-}
diff --git a/package/boot/uboot-d1/patches/0049-gpio-axp-Use-DM_PMIC-functions-for-register-access.patch b/package/boot/uboot-d1/patches/0049-gpio-axp-Use-DM_PMIC-functions-for-register-access.patch
new file mode 100644
index 00000000000000..c95e81ac4630ca
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0049-gpio-axp-Use-DM_PMIC-functions-for-register-access.patch
@@ -0,0 +1,99 @@
+From 532b81ac600b6a70a1421f86503cb6d8543edf1b Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Tue, 17 Aug 2021 20:01:55 -0500
+Subject: [PATCH 49/90] gpio: axp: Use DM_PMIC functions for register access
+
+Now that the PMIC driver implements the DM_PMIC uclass, those functions
+can be used instead of the platform-specific "pmic_bus" functions.
+
+Since the driver still uses the single set of register definitions from
+axpXXX.h (as selected by AXPxxx_POWER), it still depends on one of those
+choices, and therefore also AXP_PMIC_BUS.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/gpio/axp_gpio.c | 27 ++++++++++++---------------
+ 1 file changed, 12 insertions(+), 15 deletions(-)
+
+--- a/drivers/gpio/axp_gpio.c
++++ b/drivers/gpio/axp_gpio.c
+@@ -6,11 +6,11 @@
+  */
+ 
+ #include <common.h>
+-#include <asm/arch/pmic_bus.h>
+ #include <asm/gpio.h>
+ #include <axp_pmic.h>
+ #include <dm.h>
+ #include <errno.h>
++#include <power/pmic.h>
+ 
+ #define AXP_GPIO_PREFIX			"AXP0-"
+ #define AXP_GPIO_COUNT			4
+@@ -40,7 +40,7 @@ static int axp_gpio_direction_input(stru
+ 	if (reg == 0)
+ 		return -EINVAL;
+ 
+-	return pmic_bus_write(reg, AXP_GPIO_CTRL_INPUT);
++	return pmic_reg_write(dev->parent, reg, AXP_GPIO_CTRL_INPUT);
+ }
+ 
+ static int axp_gpio_direction_output(struct udevice *dev, unsigned pin,
+@@ -52,26 +52,27 @@ static int axp_gpio_direction_output(str
+ 	if (reg == 0)
+ 		return -EINVAL;
+ 
+-	return pmic_bus_write(reg, val ? AXP_GPIO_CTRL_OUTPUT_HIGH :
+-					 AXP_GPIO_CTRL_OUTPUT_LOW);
++	return pmic_reg_write(dev->parent, reg,
++			      val ? AXP_GPIO_CTRL_OUTPUT_HIGH :
++				    AXP_GPIO_CTRL_OUTPUT_LOW);
+ }
+ 
+ static int axp_gpio_get_value(struct udevice *dev, unsigned pin)
+ {
+-	u8 reg, val, mask;
++	u8 reg, mask;
+ 	int ret;
+ 
+ 	reg = axp_get_gpio_ctrl_reg(pin);
+ 	if (reg == 0)
+ 		return -EINVAL;
+ 
+-	ret = pmic_bus_read(AXP_GPIO_STATE, &val);
+-	if (ret)
++	ret = pmic_reg_read(dev->parent, AXP_GPIO_STATE);
++	if (ret < 0)
+ 		return ret;
+ 
+ 	mask = 1 << (pin + AXP_GPIO_STATE_OFFSET);
+ 
+-	return (val & mask) ? 1 : 0;
++	return (ret & mask) ? 1 : 0;
+ }
+ 
+ static int axp_gpio_set_value(struct udevice *dev, unsigned pin, int val)
+@@ -82,8 +83,9 @@ static int axp_gpio_set_value(struct ude
+ 	if (reg == 0)
+ 		return -EINVAL;
+ 
+-	return pmic_bus_write(reg, val ? AXP_GPIO_CTRL_OUTPUT_HIGH :
+-					 AXP_GPIO_CTRL_OUTPUT_LOW);
++	return pmic_reg_write(dev->parent, reg,
++			      val ? AXP_GPIO_CTRL_OUTPUT_HIGH :
++				    AXP_GPIO_CTRL_OUTPUT_LOW);
+ }
+ 
+ static const struct dm_gpio_ops axp_gpio_ops = {
+@@ -96,11 +98,6 @@ static const struct dm_gpio_ops axp_gpio
+ static int axp_gpio_probe(struct udevice *dev)
+ {
+ 	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+-	int ret;
+-
+-	ret = pmic_bus_init();
+-	if (ret)
+-		return ret;
+ 
+ 	/* Tell the uclass how many GPIOs we have */
+ 	uc_priv->bank_name = AXP_GPIO_PREFIX;
diff --git a/package/boot/uboot-d1/patches/0050-gpio-axp-Select-variant-from-compatible-at-runtime.patch b/package/boot/uboot-d1/patches/0050-gpio-axp-Select-variant-from-compatible-at-runtime.patch
new file mode 100644
index 00000000000000..c4dfcc94a67fb1
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0050-gpio-axp-Select-variant-from-compatible-at-runtime.patch
@@ -0,0 +1,375 @@
+From 697eb56ed8c9b3814ddbd87ae0c6e749ccafc9e3 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 28 Aug 2021 00:27:19 -0500
+Subject: [PATCH 50/90] gpio: axp: Select variant from compatible at runtime
+
+There are three major variants of the AXP PMIC GPIO functionality (plus
+PMICs with no GPIOs at all). Except for GPIO3 on the AXP209, which uses
+a different register layout, it is straightforward to support all three
+variants with a single driver. Do this, and in the process remove the
+GPIO-related definitions from the PMIC-specific headers, and therefore
+the dependency on AXP_PMIC_BUS.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/gpio/Kconfig    |   1 -
+ drivers/gpio/axp_gpio.c | 137 +++++++++++++++++++++-------------------
+ drivers/power/axp209.c  |   6 +-
+ drivers/power/axp221.c  |   4 +-
+ include/axp152.h        |  10 ---
+ include/axp209.h        |  16 ++---
+ include/axp221.h        |  13 ++--
+ include/axp809.h        |   8 ---
+ include/axp818.h        |   8 ---
+ 9 files changed, 89 insertions(+), 114 deletions(-)
+
+--- a/drivers/gpio/Kconfig
++++ b/drivers/gpio/Kconfig
+@@ -107,7 +107,6 @@ config ALTERA_PIO
+ config AXP_GPIO
+ 	bool "X-Powers AXP PMICs GPIO driver"
+ 	depends on DM_GPIO && PMIC_AXP
+-	depends on AXP_PMIC_BUS
+ 	help
+ 	  This driver supports the GPIO pins on
+ 	  X-Powers AXP152, AXP2xx, and AXP8xx PMICs.
+--- a/drivers/gpio/axp_gpio.c
++++ b/drivers/gpio/axp_gpio.c
+@@ -7,110 +7,117 @@
+ 
+ #include <common.h>
+ #include <asm/gpio.h>
+-#include <axp_pmic.h>
+ #include <dm.h>
++#include <dm/device-internal.h>
+ #include <errno.h>
+ #include <power/pmic.h>
+ 
+ #define AXP_GPIO_PREFIX			"AXP0-"
+ #define AXP_GPIO_COUNT			4
+ 
+-static int axp_gpio_set_value(struct udevice *dev, unsigned pin, int val);
+-
+-static u8 axp_get_gpio_ctrl_reg(unsigned pin)
+-{
+-	switch (pin) {
+-	case 0: return AXP_GPIO0_CTRL;
+-	case 1: return AXP_GPIO1_CTRL;
+-#ifdef AXP_GPIO2_CTRL
+-	case 2: return AXP_GPIO2_CTRL;
+-#endif
+-#ifdef AXP_GPIO3_CTRL
+-	case 3: return AXP_GPIO3_CTRL;
+-#endif
+-	}
+-	return 0;
+-}
+-
+-static int axp_gpio_direction_input(struct udevice *dev, unsigned pin)
+-{
+-	u8 reg;
+-
+-	reg = axp_get_gpio_ctrl_reg(pin);
+-	if (reg == 0)
+-		return -EINVAL;
+-
+-	return pmic_reg_write(dev->parent, reg, AXP_GPIO_CTRL_INPUT);
+-}
+-
+-static int axp_gpio_direction_output(struct udevice *dev, unsigned pin,
+-				     int val)
+-{
+-	u8 reg;
+-
+-	reg = axp_get_gpio_ctrl_reg(pin);
+-	if (reg == 0)
+-		return -EINVAL;
+-
+-	return pmic_reg_write(dev->parent, reg,
+-			      val ? AXP_GPIO_CTRL_OUTPUT_HIGH :
+-				    AXP_GPIO_CTRL_OUTPUT_LOW);
+-}
++#define AXP_GPIO_CTRL_MASK		0x7
++#define AXP_GPIO_CTRL_OUTPUT_LOW	0
++#define AXP_GPIO_CTRL_OUTPUT_HIGH	1
++
++struct axp_gpio_desc {
++	const u8	*pins;
++	u8		npins;
++	u8		status_reg;
++	u8		status_offset;
++	u8		input_mux;
++};
+ 
+ static int axp_gpio_get_value(struct udevice *dev, unsigned pin)
+ {
+-	u8 reg, mask;
++	const struct axp_gpio_desc *desc = dev_get_priv(dev);
+ 	int ret;
+ 
+-	reg = axp_get_gpio_ctrl_reg(pin);
+-	if (reg == 0)
+-		return -EINVAL;
+-
+-	ret = pmic_reg_read(dev->parent, AXP_GPIO_STATE);
++	ret = pmic_reg_read(dev->parent, desc->status_reg);
+ 	if (ret < 0)
+ 		return ret;
+ 
+-	mask = 1 << (pin + AXP_GPIO_STATE_OFFSET);
+-
+-	return (ret & mask) ? 1 : 0;
++	return !!(ret & BIT(desc->status_offset + pin));
+ }
+ 
+-static int axp_gpio_set_value(struct udevice *dev, unsigned pin, int val)
++static int axp_gpio_set_flags(struct udevice *dev, unsigned pin, ulong flags)
+ {
+-	u8 reg;
++	const struct axp_gpio_desc *desc = dev_get_priv(dev);
++	u8 mux;
+ 
+-	reg = axp_get_gpio_ctrl_reg(pin);
+-	if (reg == 0)
++	if (flags & (GPIOD_MASK_DSTYPE | GPIOD_MASK_PULL))
+ 		return -EINVAL;
+ 
+-	return pmic_reg_write(dev->parent, reg,
+-			      val ? AXP_GPIO_CTRL_OUTPUT_HIGH :
+-				    AXP_GPIO_CTRL_OUTPUT_LOW);
++	if (flags & GPIOD_IS_IN)
++		mux = desc->input_mux;
++	else if (flags & GPIOD_IS_OUT_ACTIVE)
++		mux = AXP_GPIO_CTRL_OUTPUT_HIGH;
++	else
++		mux = AXP_GPIO_CTRL_OUTPUT_LOW;
++
++	return pmic_clrsetbits(dev->parent, desc->pins[pin],
++			       AXP_GPIO_CTRL_MASK, mux);
+ }
+ 
+ static const struct dm_gpio_ops axp_gpio_ops = {
+-	.direction_input	= axp_gpio_direction_input,
+-	.direction_output	= axp_gpio_direction_output,
+ 	.get_value		= axp_gpio_get_value,
+-	.set_value		= axp_gpio_set_value,
++	.xlate			= gpio_xlate_offs_flags,
++	.set_flags		= axp_gpio_set_flags,
+ };
+ 
+ static int axp_gpio_probe(struct udevice *dev)
+ {
++	struct axp_gpio_desc *desc = (void *)dev_get_driver_data(dev);
+ 	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ 
++	dev_set_priv(dev, desc);
++
+ 	/* Tell the uclass how many GPIOs we have */
+ 	uc_priv->bank_name = AXP_GPIO_PREFIX;
+-	uc_priv->gpio_count = AXP_GPIO_COUNT;
++	uc_priv->gpio_count = desc->npins;
+ 
+ 	return 0;
+ }
+ 
++static const u8 axp152_gpio_pins[] = {
++	0x90, 0x91, 0x92, 0x93,
++};
++
++static const struct axp_gpio_desc axp152_gpio_desc = {
++	.pins		= axp152_gpio_pins,
++	.npins		= ARRAY_SIZE(axp152_gpio_pins),
++	.status_reg	= 0x97,
++	.status_offset	= 4,
++	.input_mux	= 3,
++};
++
++static const u8 axp209_gpio_pins[] = {
++	0x90, 0x92, 0x93,
++};
++
++static const struct axp_gpio_desc axp209_gpio_desc = {
++	.pins		= axp209_gpio_pins,
++	.npins		= ARRAY_SIZE(axp209_gpio_pins),
++	.status_reg	= 0x94,
++	.status_offset	= 4,
++	.input_mux	= 2,
++};
++
++static const u8 axp221_gpio_pins[] = {
++	0x90, 0x92,
++};
++
++static const struct axp_gpio_desc axp221_gpio_desc = {
++	.pins		= axp221_gpio_pins,
++	.npins		= ARRAY_SIZE(axp221_gpio_pins),
++	.status_reg	= 0x94,
++	.input_mux	= 2,
++};
++
+ static const struct udevice_id axp_gpio_ids[] = {
+-	{ .compatible = "x-powers,axp152-gpio" },
+-	{ .compatible = "x-powers,axp209-gpio" },
+-	{ .compatible = "x-powers,axp221-gpio" },
+-	{ .compatible = "x-powers,axp813-gpio" },
++	{ .compatible = "x-powers,axp152-gpio", .data = (ulong)&axp152_gpio_desc },
++	{ .compatible = "x-powers,axp209-gpio", .data = (ulong)&axp209_gpio_desc },
++	{ .compatible = "x-powers,axp221-gpio", .data = (ulong)&axp221_gpio_desc },
++	{ .compatible = "x-powers,axp813-gpio", .data = (ulong)&axp221_gpio_desc },
+ 	{ }
+ };
+ 
+--- a/drivers/power/axp209.c
++++ b/drivers/power/axp209.c
+@@ -215,15 +215,15 @@ int axp_init(void)
+ 	 * Turn off LDOIO regulators / tri-state GPIO pins, when rebooting
+ 	 * from android these are sometimes on.
+ 	 */
+-	rc = pmic_bus_write(AXP_GPIO0_CTRL, AXP_GPIO_CTRL_INPUT);
++	rc = pmic_bus_write(AXP209_GPIO0_CTRL, AXP209_GPIO_CTRL_INPUT);
+ 	if (rc)
+ 		return rc;
+ 
+-	rc = pmic_bus_write(AXP_GPIO1_CTRL, AXP_GPIO_CTRL_INPUT);
++	rc = pmic_bus_write(AXP209_GPIO1_CTRL, AXP209_GPIO_CTRL_INPUT);
+ 	if (rc)
+ 		return rc;
+ 
+-	rc = pmic_bus_write(AXP_GPIO2_CTRL, AXP_GPIO_CTRL_INPUT);
++	rc = pmic_bus_write(AXP209_GPIO2_CTRL, AXP209_GPIO_CTRL_INPUT);
+ 	if (rc)
+ 		return rc;
+ 
+--- a/drivers/power/axp221.c
++++ b/drivers/power/axp221.c
+@@ -226,11 +226,11 @@ int axp_init(void)
+ 	 * Turn off LDOIO regulators / tri-state GPIO pins, when rebooting
+ 	 * from android these are sometimes on.
+ 	 */
+-	ret = pmic_bus_write(AXP_GPIO0_CTRL, AXP_GPIO_CTRL_INPUT);
++	ret = pmic_bus_write(AXP221_GPIO0_CTRL, AXP221_GPIO_CTRL_INPUT);
+ 	if (ret)
+ 		return ret;
+ 
+-	ret = pmic_bus_write(AXP_GPIO1_CTRL, AXP_GPIO_CTRL_INPUT);
++	ret = pmic_bus_write(AXP221_GPIO1_CTRL, AXP221_GPIO_CTRL_INPUT);
+ 	if (ret)
+ 		return ret;
+ 
+--- a/include/axp152.h
++++ b/include/axp152.h
+@@ -14,17 +14,7 @@ enum axp152_reg {
+ 
+ #define AXP152_POWEROFF			(1 << 7)
+ 
+-/* For axp_gpio.c */
+ #ifdef CONFIG_AXP152_POWER
+ #define AXP_POWER_STATUS		0x00
+ #define AXP_POWER_STATUS_ALDO_IN		BIT(0)
+-#define AXP_GPIO0_CTRL			0x90
+-#define AXP_GPIO1_CTRL			0x91
+-#define AXP_GPIO2_CTRL			0x92
+-#define AXP_GPIO3_CTRL			0x93
+-#define AXP_GPIO_CTRL_OUTPUT_LOW		0x00 /* Drive pin low */
+-#define AXP_GPIO_CTRL_OUTPUT_HIGH		0x01 /* Drive pin high */
+-#define AXP_GPIO_CTRL_INPUT			0x02 /* Input */
+-#define AXP_GPIO_STATE			0x97
+-#define AXP_GPIO_STATE_OFFSET			0
+ #endif
+--- a/include/axp209.h
++++ b/include/axp209.h
+@@ -21,6 +21,9 @@ enum axp209_reg {
+ 	AXP209_IRQ_ENABLE5 = 0x44,
+ 	AXP209_IRQ_STATUS5 = 0x4c,
+ 	AXP209_SHUTDOWN = 0x32,
++	AXP209_GPIO0_CTRL = 0x90,
++	AXP209_GPIO1_CTRL = 0x92,
++	AXP209_GPIO2_CTRL = 0x93,
+ };
+ 
+ #define AXP209_POWER_STATUS_ON_BY_DC	BIT(0)
+@@ -73,16 +76,11 @@ enum axp209_reg {
+ 
+ #define AXP209_POWEROFF			BIT(7)
+ 
+-/* For axp_gpio.c */
++#define AXP209_GPIO_CTRL_OUTPUT_LOW	0x00
++#define AXP209_GPIO_CTRL_OUTPUT_HIGH	0x01
++#define AXP209_GPIO_CTRL_INPUT		0x02
++
+ #ifdef CONFIG_AXP209_POWER
+ #define AXP_POWER_STATUS		0x00
+ #define AXP_POWER_STATUS_ALDO_IN		BIT(0)
+-#define AXP_GPIO0_CTRL			0x90
+-#define AXP_GPIO1_CTRL			0x92
+-#define AXP_GPIO2_CTRL			0x93
+-#define AXP_GPIO_CTRL_OUTPUT_LOW	0x00 /* Drive pin low */
+-#define AXP_GPIO_CTRL_OUTPUT_HIGH	0x01 /* Drive pin high */
+-#define AXP_GPIO_CTRL_INPUT		0x02 /* Input */
+-#define AXP_GPIO_STATE			0x94
+-#define AXP_GPIO_STATE_OFFSET		4
+ #endif
+--- a/include/axp221.h
++++ b/include/axp221.h
+@@ -44,20 +44,17 @@
+ #define AXP221_ALDO3_CTRL	0x2a
+ #define AXP221_SHUTDOWN		0x32
+ #define AXP221_SHUTDOWN_POWEROFF	(1 << 7)
++#define AXP221_GPIO0_CTRL	0x90
++#define AXP221_GPIO1_CTRL	0x92
++#define AXP221_GPIO_CTRL_OUTPUT_LOW	0x00
++#define AXP221_GPIO_CTRL_OUTPUT_HIGH	0x01
++#define AXP221_GPIO_CTRL_INPUT		0x02
+ #define AXP221_PAGE		0xff
+ 
+ /* Page 1 addresses */
+ #define AXP221_SID		0x20
+ 
+-/* For axp_gpio.c */
+ #ifdef CONFIG_AXP221_POWER
+ #define AXP_POWER_STATUS		0x00
+ #define AXP_POWER_STATUS_ALDO_IN		BIT(0)
+-#define AXP_GPIO0_CTRL			0x90
+-#define AXP_GPIO1_CTRL			0x92
+-#define AXP_GPIO_CTRL_OUTPUT_LOW		0x00 /* Drive pin low */
+-#define AXP_GPIO_CTRL_OUTPUT_HIGH		0x01 /* Drive pin high */
+-#define AXP_GPIO_CTRL_INPUT			0x02 /* Input */
+-#define AXP_GPIO_STATE			0x94
+-#define AXP_GPIO_STATE_OFFSET			0
+ #endif
+--- a/include/axp809.h
++++ b/include/axp809.h
+@@ -43,15 +43,7 @@
+ #define AXP809_SHUTDOWN		0x32
+ #define AXP809_SHUTDOWN_POWEROFF	(1 << 7)
+ 
+-/* For axp_gpio.c */
+ #ifdef CONFIG_AXP809_POWER
+ #define AXP_POWER_STATUS		0x00
+ #define AXP_POWER_STATUS_ALDO_IN		BIT(0)
+-#define AXP_GPIO0_CTRL			0x90
+-#define AXP_GPIO1_CTRL			0x92
+-#define AXP_GPIO_CTRL_OUTPUT_LOW	0x00 /* Drive pin low */
+-#define AXP_GPIO_CTRL_OUTPUT_HIGH	0x01 /* Drive pin high */
+-#define AXP_GPIO_CTRL_INPUT		0x02 /* Input */
+-#define AXP_GPIO_STATE			0x94
+-#define AXP_GPIO_STATE_OFFSET		0
+ #endif
+--- a/include/axp818.h
++++ b/include/axp818.h
+@@ -57,15 +57,7 @@
+ #define AXP818_SHUTDOWN		0x32
+ #define AXP818_SHUTDOWN_POWEROFF	(1 << 7)
+ 
+-/* For axp_gpio.c */
+ #ifdef CONFIG_AXP818_POWER
+ #define AXP_POWER_STATUS		0x00
+ #define AXP_POWER_STATUS_ALDO_IN		BIT(0)
+-#define AXP_GPIO0_CTRL			0x90
+-#define AXP_GPIO1_CTRL			0x92
+-#define AXP_GPIO_CTRL_OUTPUT_LOW	0x00 /* Drive pin low */
+-#define AXP_GPIO_CTRL_OUTPUT_HIGH	0x01 /* Drive pin high */
+-#define AXP_GPIO_CTRL_INPUT		0x02 /* Input */
+-#define AXP_GPIO_STATE			0x94
+-#define AXP_GPIO_STATE_OFFSET		0
+ #endif
diff --git a/package/boot/uboot-d1/patches/0051-gpio-axp-Add-support-for-getting-the-pin-function.patch b/package/boot/uboot-d1/patches/0051-gpio-axp-Add-support-for-getting-the-pin-function.patch
new file mode 100644
index 00000000000000..b8ede75c2a51b9
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0051-gpio-axp-Add-support-for-getting-the-pin-function.patch
@@ -0,0 +1,49 @@
+From 37e19d9b8a23c88413dd845dbb3dd58dd3636a6d Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 28 Aug 2021 00:36:33 -0500
+Subject: [PATCH 51/90] gpio: axp: Add support for getting the pin function
+
+Implement the .get_function operation, so the gpio command can report
+the current function. Since the GPIOF_FUNC (versus GPIOF_UNUSED) mux
+values vary among the PMICs, report all non-GPIO mux values as UNKNOWN.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/gpio/axp_gpio.c | 19 +++++++++++++++++++
+ 1 file changed, 19 insertions(+)
+
+--- a/drivers/gpio/axp_gpio.c
++++ b/drivers/gpio/axp_gpio.c
+@@ -39,6 +39,24 @@ static int axp_gpio_get_value(struct ude
+ 	return !!(ret & BIT(desc->status_offset + pin));
+ }
+ 
++static int axp_gpio_get_function(struct udevice *dev, unsigned pin)
++{
++	const struct axp_gpio_desc *desc = dev_get_priv(dev);
++	int ret;
++
++	ret = pmic_reg_read(dev->parent, desc->pins[pin]);
++	if (ret < 0)
++		return ret;
++
++	ret &= AXP_GPIO_CTRL_MASK;
++	if (ret == desc->input_mux)
++		return GPIOF_INPUT;
++	if (ret == AXP_GPIO_CTRL_OUTPUT_HIGH || ret == AXP_GPIO_CTRL_OUTPUT_LOW)
++		return GPIOF_OUTPUT;
++
++	return GPIOF_UNKNOWN;
++}
++
+ static int axp_gpio_set_flags(struct udevice *dev, unsigned pin, ulong flags)
+ {
+ 	const struct axp_gpio_desc *desc = dev_get_priv(dev);
+@@ -60,6 +78,7 @@ static int axp_gpio_set_flags(struct ude
+ 
+ static const struct dm_gpio_ops axp_gpio_ops = {
+ 	.get_value		= axp_gpio_get_value,
++	.get_function		= axp_gpio_get_function,
+ 	.xlate			= gpio_xlate_offs_flags,
+ 	.set_flags		= axp_gpio_set_flags,
+ };
diff --git a/package/boot/uboot-d1/patches/0052-gpio-axp-Add-pull-down-support-for-AXP22x-AXP8xx-var.patch b/package/boot/uboot-d1/patches/0052-gpio-axp-Add-pull-down-support-for-AXP22x-AXP8xx-var.patch
new file mode 100644
index 00000000000000..771e5c3866c69c
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0052-gpio-axp-Add-pull-down-support-for-AXP22x-AXP8xx-var.patch
@@ -0,0 +1,56 @@
+From 4be9f9082b0a2ac2626ae20b7e07006139827442 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 28 Aug 2021 00:34:54 -0500
+Subject: [PATCH 52/90] gpio: axp: Add pull-down support for AXP22x/AXP8xx
+ variant
+
+The AXP221 and newer PMICs support a pull-down function on their GPIOs.
+Add support for it.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/gpio/axp_gpio.c | 15 ++++++++++++++-
+ 1 file changed, 14 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpio/axp_gpio.c
++++ b/drivers/gpio/axp_gpio.c
+@@ -24,6 +24,7 @@ struct axp_gpio_desc {
+ 	u8		npins;
+ 	u8		status_reg;
+ 	u8		status_offset;
++	u8		pull_reg;
+ 	u8		input_mux;
+ };
+ 
+@@ -60,11 +61,22 @@ static int axp_gpio_get_function(struct
+ static int axp_gpio_set_flags(struct udevice *dev, unsigned pin, ulong flags)
+ {
+ 	const struct axp_gpio_desc *desc = dev_get_priv(dev);
++	bool pull_down = flags & GPIOD_PULL_DOWN;
++	int ret;
+ 	u8 mux;
+ 
+-	if (flags & (GPIOD_MASK_DSTYPE | GPIOD_MASK_PULL))
++	if (flags & (GPIOD_MASK_DSTYPE | GPIOD_PULL_UP))
++		return -EINVAL;
++	if (pull_down && !desc->pull_reg)
+ 		return -EINVAL;
+ 
++	if (desc->pull_reg) {
++		ret = pmic_clrsetbits(dev->parent, desc->pull_reg,
++				      BIT(pin), pull_down ? BIT(pin) : 0);
++		if (ret)
++			return ret;
++	}
++
+ 	if (flags & GPIOD_IS_IN)
+ 		mux = desc->input_mux;
+ 	else if (flags & GPIOD_IS_OUT_ACTIVE)
+@@ -129,6 +141,7 @@ static const struct axp_gpio_desc axp221
+ 	.pins		= axp221_gpio_pins,
+ 	.npins		= ARRAY_SIZE(axp221_gpio_pins),
+ 	.status_reg	= 0x94,
++	.pull_reg	= 0x97,
+ 	.input_mux	= 2,
+ };
+ 
diff --git a/package/boot/uboot-d1/patches/0053-gpio-axp-Report-the-correct-value-for-outputs.patch b/package/boot/uboot-d1/patches/0053-gpio-axp-Report-the-correct-value-for-outputs.patch
new file mode 100644
index 00000000000000..a6d0eb4526e8bd
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0053-gpio-axp-Report-the-correct-value-for-outputs.patch
@@ -0,0 +1,28 @@
+From 52c172782d659750b447572281cd11835d1edf58 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 31 Jul 2022 18:19:39 -0500
+Subject: [PATCH 53/90] gpio: axp: Report the correct value for outputs
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/gpio/axp_gpio.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+--- a/drivers/gpio/axp_gpio.c
++++ b/drivers/gpio/axp_gpio.c
+@@ -33,6 +33,15 @@ static int axp_gpio_get_value(struct ude
+ 	const struct axp_gpio_desc *desc = dev_get_priv(dev);
+ 	int ret;
+ 
++	ret = pmic_reg_read(dev->parent, desc->pins[pin]);
++	if (ret < 0)
++		return ret;
++
++	if (ret == AXP_GPIO_CTRL_OUTPUT_LOW)
++		return 0;
++	if (ret == AXP_GPIO_CTRL_OUTPUT_HIGH)
++		return 1;
++
+ 	ret = pmic_reg_read(dev->parent, desc->status_reg);
+ 	if (ret < 0)
+ 		return ret;
diff --git a/package/boot/uboot-d1/patches/0054-sunxi-Fix-default-enablement-of-USB-host-drivers.patch b/package/boot/uboot-d1/patches/0054-sunxi-Fix-default-enablement-of-USB-host-drivers.patch
new file mode 100644
index 00000000000000..52825dce21e62b
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0054-sunxi-Fix-default-enablement-of-USB-host-drivers.patch
@@ -0,0 +1,47 @@
+From 64de4fd71d35c6154a0f7b4c7c02cb24e978a4ce Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Fri, 5 Aug 2022 23:45:19 -0500
+Subject: [PATCH 54/90] sunxi: Fix default-enablement of USB host drivers
+
+We tried to enable USB_EHCI_GENERIC and USB_OHCI_GENERIC by default.
+This did not work because those symbols depend on USB_EHCI_HCD and
+USB_OHCI_HCD, which were not enabled. Fix this by implying all four.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm/Kconfig         | 4 ++++
+ drivers/usb/host/Kconfig | 2 --
+ 2 files changed, 4 insertions(+), 2 deletions(-)
+
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -1142,7 +1142,11 @@ config ARCH_SUNXI
+ 	imply SYSRESET
+ 	imply SYSRESET_WATCHDOG
+ 	imply SYSRESET_WATCHDOG_AUTO
++	imply USB_EHCI_GENERIC
++	imply USB_EHCI_HCD
+ 	imply USB_GADGET
++	imply USB_OHCI_GENERIC
++	imply USB_OHCI_HCD
+ 	imply WDT
+ 
+ config ARCH_U8500
+--- a/drivers/usb/host/Kconfig
++++ b/drivers/usb/host/Kconfig
+@@ -281,7 +281,6 @@ config USB_EHCI_ZYNQ
+ config USB_EHCI_GENERIC
+ 	bool "Support for generic EHCI USB controller"
+ 	depends on DM_USB
+-	default ARCH_SUNXI
+ 	---help---
+ 	  Enables support for generic EHCI controller.
+ 
+@@ -343,7 +342,6 @@ config USB_OHCI_PCI
+ 
+ config USB_OHCI_GENERIC
+ 	bool "Support for generic OHCI USB controller"
+-	default ARCH_SUNXI
+ 	---help---
+ 	  Enables support for generic OHCI controller.
+ 
diff --git a/package/boot/uboot-d1/patches/0055-sunxi-Remove-unnecessary-Kconfig-selections.patch b/package/boot/uboot-d1/patches/0055-sunxi-Remove-unnecessary-Kconfig-selections.patch
new file mode 100644
index 00000000000000..6fd4ffdae330b6
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0055-sunxi-Remove-unnecessary-Kconfig-selections.patch
@@ -0,0 +1,36 @@
+From 891fef47500dbf4aecb16e08c1d8ade3fbc8caec Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Thu, 4 Aug 2022 23:22:05 -0500
+Subject: [PATCH 55/90] sunxi: Remove unnecessary Kconfig selections
+
+Two of these selections are redundant and have no effect:
+ - DM_KEYBOARD is selected by USB_KEYBOARD
+ - DM_MMC is selected by MMC
+
+This selection has no effect by default and is unnecessarily strong:
+ - USB_STORAGE is implied by DISTRO_DEFAULTS
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm/Kconfig | 3 ---
+ 1 file changed, 3 deletions(-)
+
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -1100,8 +1100,6 @@ config ARCH_SUNXI
+ 	select DM_I2C if I2C
+ 	select DM_SPI if SPI
+ 	select DM_SPI_FLASH if SPI
+-	select DM_KEYBOARD
+-	select DM_MMC if MMC
+ 	select DM_SCSI if SCSI
+ 	select DM_SERIAL
+ 	select GPIO_EXTRA_HEADER
+@@ -1119,7 +1117,6 @@ config ARCH_SUNXI
+ 	select SYS_THUMB_BUILD if !ARM64
+ 	select USB if DISTRO_DEFAULTS
+ 	select USB_KEYBOARD if DISTRO_DEFAULTS && USB_HOST
+-	select USB_STORAGE if DISTRO_DEFAULTS && USB_HOST
+ 	select SPL_USE_TINY_PRINTF
+ 	select USE_PREBOOT
+ 	select SYS_RELOC_GD_ENV_ADDR
diff --git a/package/boot/uboot-d1/patches/0056-sunxi-Add-missing-dependencies-to-Kconfig-selections.patch b/package/boot/uboot-d1/patches/0056-sunxi-Add-missing-dependencies-to-Kconfig-selections.patch
new file mode 100644
index 00000000000000..6adeeaef2b3e26
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0056-sunxi-Add-missing-dependencies-to-Kconfig-selections.patch
@@ -0,0 +1,55 @@
+From 9e12a7fd80276092da3a43b7dbaf572bad294419 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Thu, 4 Aug 2022 23:29:13 -0500
+Subject: [PATCH 56/90] sunxi: Add missing dependencies to Kconfig selections
+
+Some of the selected symbols have a user-visible dependency. Make the
+selections conditional on that dependency to avoid creating invalid
+configurations.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm/Kconfig | 16 ++++++++--------
+ 1 file changed, 8 insertions(+), 8 deletions(-)
+
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -1090,30 +1090,30 @@ config ARCH_SOCFPGA
+ config ARCH_SUNXI
+ 	bool "Support sunxi (Allwinner) SoCs"
+ 	select BINMAN
+-	select CMD_GPIO
++	select CMD_GPIO if GPIO
+ 	select CMD_MMC if MMC
+ 	select CMD_USB if DISTRO_DEFAULTS && USB_HOST
+ 	select CLK
+ 	select DM
+-	select DM_ETH
+-	select DM_GPIO
++	select DM_ETH if NET
++	select DM_GPIO if GPIO
+ 	select DM_I2C if I2C
++	select DM_SCSI if BLK && SCSI
++	select DM_SERIAL if SERIAL
+ 	select DM_SPI if SPI
+ 	select DM_SPI_FLASH if SPI
+-	select DM_SCSI if SCSI
+-	select DM_SERIAL
+ 	select GPIO_EXTRA_HEADER
+ 	select OF_BOARD_SETUP
+ 	select OF_CONTROL
+ 	select OF_SEPARATE
+ 	select PINCTRL
+-	select SPECIFY_CONSOLE_INDEX
++	select SPECIFY_CONSOLE_INDEX if SERIAL
+ 	select SPL_SEPARATE_BSS if SPL
+ 	select SPL_STACK_R if SPL
+ 	select SPL_SYS_MALLOC_SIMPLE if SPL
+ 	select SPL_SYS_THUMB_BUILD if !ARM64
+-	select SUNXI_GPIO
+-	select SYS_NS16550
++	select SUNXI_GPIO if GPIO
++	select SYS_NS16550 if SERIAL
+ 	select SYS_THUMB_BUILD if !ARM64
+ 	select USB if DISTRO_DEFAULTS
+ 	select USB_KEYBOARD if DISTRO_DEFAULTS && USB_HOST
diff --git a/package/boot/uboot-d1/patches/0057-sunxi-Hide-image-type-selection-if-SPL-is-disabled.patch b/package/boot/uboot-d1/patches/0057-sunxi-Hide-image-type-selection-if-SPL-is-disabled.patch
new file mode 100644
index 00000000000000..314720197e14dd
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0057-sunxi-Hide-image-type-selection-if-SPL-is-disabled.patch
@@ -0,0 +1,22 @@
+From 2ba626d36e622f29528ce953618dde9a01bdacd6 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Fri, 5 Aug 2022 21:56:43 -0500
+Subject: [PATCH 57/90] sunxi: Hide image type selection if SPL is disabled
+
+This choice is meaningless when SPL is disabled. Hide it to avoid any
+possible confusion.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ board/sunxi/Kconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/board/sunxi/Kconfig
++++ b/board/sunxi/Kconfig
+@@ -1,5 +1,6 @@
+ choice
+ 	prompt "SPL Image Type"
++	depends on SPL
+ 	default SPL_IMAGE_TYPE_SUNXI_EGON
+ 
+ config SPL_IMAGE_TYPE_SUNXI_EGON
diff --git a/package/boot/uboot-d1/patches/0058-sunxi-Share-the-board-Kconfig-across-architectures.patch b/package/boot/uboot-d1/patches/0058-sunxi-Share-the-board-Kconfig-across-architectures.patch
new file mode 100644
index 00000000000000..dfae082cf5c85f
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0058-sunxi-Share-the-board-Kconfig-across-architectures.patch
@@ -0,0 +1,75 @@
+From 5d197433cd54085306e369ac260e09fe6077bfbb Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Thu, 4 Aug 2022 21:30:57 -0500
+Subject: [PATCH 58/90] sunxi: Share the board Kconfig across architectures
+
+With the introduction of the Allwinner D1, the sunxi board family now
+spans multiple architectures (ARM and RISC-V). Since ARCH_SUNXI depends
+on ARM, it cannot be used to gate architecture-independent options.
+Specifically, this means the board Kconfig file cannot be sourced from
+inside the "if ARCH_SUNXI" block.
+
+Introduce a new BOARD_SUNXI symbol that can be selected by both
+ARCH_SUNXI now and the new RISC-V SoC symbols when they are added, and
+use it to gate the architecture-independent board options.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/Kconfig                |  1 +
+ arch/arm/Kconfig            |  1 +
+ arch/arm/mach-sunxi/Kconfig |  2 --
+ board/sunxi/Kconfig         | 11 +++++++++++
+ 4 files changed, 13 insertions(+), 2 deletions(-)
+
+--- a/arch/Kconfig
++++ b/arch/Kconfig
+@@ -482,6 +482,7 @@ source "arch/Kconfig.nxp"
+ endif
+ 
+ source "board/keymile/Kconfig"
++source "board/sunxi/Kconfig"
+ 
+ if MIPS || MICROBLAZE
+ 
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -1090,6 +1090,7 @@ config ARCH_SOCFPGA
+ config ARCH_SUNXI
+ 	bool "Support sunxi (Allwinner) SoCs"
+ 	select BINMAN
++	select BOARD_SUNXI
+ 	select CMD_GPIO if GPIO
+ 	select CMD_MMC if MMC
+ 	select CMD_USB if DISTRO_DEFAULTS && USB_HOST
+--- a/arch/arm/mach-sunxi/Kconfig
++++ b/arch/arm/mach-sunxi/Kconfig
+@@ -959,8 +959,6 @@ config BLUETOOTH_DT_DEVICE_FIXUP
+ 	  The used address is "bdaddr" if set, and "ethaddr" with the LSB
+ 	  flipped elsewise.
+ 
+-source "board/sunxi/Kconfig"
+-
+ endif
+ 
+ config CHIP_DIP_SCAN
+--- a/board/sunxi/Kconfig
++++ b/board/sunxi/Kconfig
+@@ -1,3 +1,10 @@
++config BOARD_SUNXI
++	bool
++
++if BOARD_SUNXI
++
++menu "sunxi board options"
++
+ choice
+ 	prompt "SPL Image Type"
+ 	depends on SPL
+@@ -23,3 +30,7 @@ config SPL_IMAGE_TYPE
+ 	string
+ 	default "sunxi_egon" if SPL_IMAGE_TYPE_SUNXI_EGON
+ 	default "sunxi_toc0" if SPL_IMAGE_TYPE_SUNXI_TOC0
++
++endmenu
++
++endif
diff --git a/package/boot/uboot-d1/patches/0059-sunxi-Move-most-Kconfig-selections-to-the-board-Kcon.patch b/package/boot/uboot-d1/patches/0059-sunxi-Move-most-Kconfig-selections-to-the-board-Kcon.patch
new file mode 100644
index 00000000000000..e576d137e83c16
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0059-sunxi-Move-most-Kconfig-selections-to-the-board-Kcon.patch
@@ -0,0 +1,140 @@
+From 963331be1cc924ad7c928f88b3ee46bc20a41bcd Mon Sep 17 00:00:00 2001
+From: Zoltan HERPAI <wigyori@uid0.hu>
+Date: Tue, 6 Jun 2023 18:06:20 +0000
+Subject: [PATCH 59/90] sunxi: Move most Kconfig selections to the board
+ Kconfig
+
+To maintain consistent behavior across architectures, most of the
+options selected by ARCH_SUNXI should be selected for the D1 SoC as
+well. To accomplish this, select them from BOARD_SUNXI instead.
+
+No functional change here. Lines are only moved and alphabetized.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+
+Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
+---
+ arch/arm/Kconfig    | 47 ---------------------------------------------
+ board/sunxi/Kconfig | 46 ++++++++++++++++++++++++++++++++++++++++++++
+ 2 files changed, 46 insertions(+), 47 deletions(-)
+
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -1089,63 +1089,16 @@ config ARCH_SOCFPGA
+ 
+ config ARCH_SUNXI
+ 	bool "Support sunxi (Allwinner) SoCs"
+-	select BINMAN
+ 	select BOARD_SUNXI
+-	select CMD_GPIO if GPIO
+-	select CMD_MMC if MMC
+-	select CMD_USB if DISTRO_DEFAULTS && USB_HOST
+-	select CLK
+-	select DM
+-	select DM_ETH if NET
+-	select DM_GPIO if GPIO
+-	select DM_I2C if I2C
+-	select DM_SCSI if BLK && SCSI
+-	select DM_SERIAL if SERIAL
+-	select DM_SPI if SPI
+-	select DM_SPI_FLASH if SPI
+ 	select GPIO_EXTRA_HEADER
+-	select OF_BOARD_SETUP
+ 	select OF_CONTROL
+ 	select OF_SEPARATE
+-	select PINCTRL
+ 	select SPECIFY_CONSOLE_INDEX if SERIAL
+-	select SPL_SEPARATE_BSS if SPL
+ 	select SPL_STACK_R if SPL
+ 	select SPL_SYS_MALLOC_SIMPLE if SPL
+ 	select SPL_SYS_THUMB_BUILD if !ARM64
+-	select SUNXI_GPIO if GPIO
+-	select SYS_NS16550 if SERIAL
+ 	select SYS_THUMB_BUILD if !ARM64
+-	select USB if DISTRO_DEFAULTS
+-	select USB_KEYBOARD if DISTRO_DEFAULTS && USB_HOST
+ 	select SPL_USE_TINY_PRINTF
+-	select USE_PREBOOT
+-	select SYS_RELOC_GD_ENV_ADDR
+-	imply BOARD_LATE_INIT
+-	imply CMD_DM
+-	imply CMD_GPT
+-	imply CMD_UBI if MTD_RAW_NAND
+-	imply DISTRO_DEFAULTS
+-	imply FAT_WRITE
+-	imply FIT
+-	imply OF_LIBFDT_OVERLAY
+-	imply PRE_CONSOLE_BUFFER
+-	imply SPL_GPIO
+-	imply SPL_LIBCOMMON_SUPPORT
+-	imply SPL_LIBGENERIC_SUPPORT
+-	imply SPL_LOAD_FIT
+-	imply SPL_MMC if MMC
+-	imply SPL_POWER
+-	imply SPL_SERIAL
+-	imply SYSRESET
+-	imply SYSRESET_WATCHDOG
+-	imply SYSRESET_WATCHDOG_AUTO
+-	imply USB_EHCI_GENERIC
+-	imply USB_EHCI_HCD
+-	imply USB_GADGET
+-	imply USB_OHCI_GENERIC
+-	imply USB_OHCI_HCD
+-	imply WDT
+ 
+ config ARCH_U8500
+ 	bool "ST-Ericsson U8500 Series"
+--- a/board/sunxi/Kconfig
++++ b/board/sunxi/Kconfig
+@@ -1,5 +1,51 @@
+ config BOARD_SUNXI
+ 	bool
++	select BINMAN
++	select CLK
++	select CMD_GPIO if GPIO
++	select CMD_MMC if MMC
++	select CMD_USB if DISTRO_DEFAULTS && USB_HOST
++	select DM
++	select DM_ETH if NET
++	select DM_GPIO if GPIO
++	select DM_I2C if I2C
++	select DM_SCSI if BLK && SCSI
++	select DM_SERIAL if SERIAL
++	select DM_SPI if SPI
++	select DM_SPI_FLASH if SPI
++	select OF_BOARD_SETUP
++	select PINCTRL
++	select SPL_SEPARATE_BSS if SPL
++	select SUNXI_GPIO if GPIO
++	select SYS_NS16550 if SERIAL
++	select SYS_RELOC_GD_ENV_ADDR
++	select USB if DISTRO_DEFAULTS
++	select USB_KEYBOARD if DISTRO_DEFAULTS && USB_HOST
++	select USE_PREBOOT
++	imply BOARD_LATE_INIT
++	imply CMD_DM
++	imply CMD_GPT
++	imply CMD_UBI if MTD_RAW_NAND
++	imply DISTRO_DEFAULTS
++	imply FAT_WRITE
++	imply FIT
++	imply OF_LIBFDT_OVERLAY
++	imply PRE_CONSOLE_BUFFER
++	imply SPL_GPIO
++	imply SPL_LIBCOMMON_SUPPORT
++	imply SPL_LIBGENERIC_SUPPORT
++	imply SPL_MMC if MMC
++	imply SPL_POWER
++	imply SPL_SERIAL
++	imply SYSRESET
++	imply SYSRESET_WATCHDOG
++	imply SYSRESET_WATCHDOG_AUTO
++	imply USB_EHCI_GENERIC
++	imply USB_EHCI_HCD
++	imply USB_GADGET
++	imply USB_OHCI_GENERIC
++	imply USB_OHCI_HCD
++	imply WDT
+ 
+ if BOARD_SUNXI
+ 
diff --git a/package/boot/uboot-d1/patches/0060-sunxi-Globally-enable-SUPPORT_SPL.patch b/package/boot/uboot-d1/patches/0060-sunxi-Globally-enable-SUPPORT_SPL.patch
new file mode 100644
index 00000000000000..0b59906f440c91
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0060-sunxi-Globally-enable-SUPPORT_SPL.patch
@@ -0,0 +1,147 @@
+From 5838fd3a53e613312d46ab4cb6015a502c4c45d0 Mon Sep 17 00:00:00 2001
+From: Zoltan HERPAI <wigyori@uid0.hu>
+Date: Tue, 6 Jun 2023 18:07:24 +0000
+Subject: [PATCH 60/90] sunxi: Globally enable SUPPORT_SPL
+
+This was already supported by every machine type. It is unlikely that
+any new SoC support will be added without SPL support.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
+---
+ arch/arm/mach-sunxi/Kconfig | 14 --------------
+ board/sunxi/Kconfig         |  2 ++
+ 2 files changed, 2 insertions(+), 14 deletions(-)
+
+--- a/arch/arm/mach-sunxi/Kconfig
++++ b/arch/arm/mach-sunxi/Kconfig
+@@ -133,7 +133,6 @@ config SUN50I_GEN_H6
+ 	select FIT
+ 	select SPL_LOAD_FIT
+ 	select MMC_SUNXI_HAS_NEW_MODE
+-	select SUPPORT_SPL
+ 	---help---
+ 	Select this for sunxi SoCs which have H6 like peripherals, clocks
+ 	and memory map.
+@@ -166,7 +165,6 @@ config MACH_SUNXI_H3_H5
+ 	select SUNXI_DRAM_DW
+ 	select SUNXI_DRAM_DW_32BIT
+ 	select SUNXI_GEN_SUN6I
+-	select SUPPORT_SPL
+ 
+ # TODO: try out A80's 8GiB DRAM space
+ config SUNXI_DRAM_MAX_SIZE
+@@ -183,7 +181,6 @@ config MACH_SUNIV
+ 	bool "suniv (Allwinner F1C100s/F1C200s/F1C600/R6)"
+ 	select CPU_ARM926EJS
+ 	select SUNXI_GEN_SUN6I
+-	select SUPPORT_SPL
+ 	select SKIP_LOWLEVEL_INIT_ONLY
+ 	select SPL_SKIP_LOWLEVEL_INIT_ONLY
+ 
+@@ -192,7 +189,6 @@ config MACH_SUN4I
+ 	select CPU_V7A
+ 	select DRAM_SUN4I
+ 	select SUNXI_GEN_SUN4I
+-	select SUPPORT_SPL
+ 	imply SPL_SYS_I2C_LEGACY
+ 	imply SYS_I2C_LEGACY
+ 
+@@ -201,7 +197,6 @@ config MACH_SUN5I
+ 	select CPU_V7A
+ 	select DRAM_SUN4I
+ 	select SUNXI_GEN_SUN4I
+-	select SUPPORT_SPL
+ 	imply SPL_SYS_I2C_LEGACY
+ 	imply SYS_I2C_LEGACY
+ 
+@@ -216,7 +211,6 @@ config MACH_SUN6I
+ 	select SPL_I2C
+ 	select SUN6I_PRCM
+ 	select SUNXI_GEN_SUN6I
+-	select SUPPORT_SPL
+ 	select SYS_I2C_SUN6I_P2WI
+ 	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
+ 
+@@ -229,7 +223,6 @@ config MACH_SUN7I
+ 	select SPL_ARMV7_SET_CORTEX_SMPEN
+ 	select DRAM_SUN4I
+ 	select SUNXI_GEN_SUN4I
+-	select SUPPORT_SPL
+ 	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
+ 	imply SPL_SYS_I2C_LEGACY
+ 	imply SYS_I2C_LEGACY
+@@ -243,7 +236,6 @@ config MACH_SUN8I_A23
+ 	select DRAM_SUN8I_A23
+ 	select SPL_I2C
+ 	select SUNXI_GEN_SUN6I
+-	select SUPPORT_SPL
+ 	select SYS_I2C_SUN8I_RSB
+ 	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
+ 
+@@ -256,7 +248,6 @@ config MACH_SUN8I_A33
+ 	select DRAM_SUN8I_A33
+ 	select SPL_I2C
+ 	select SUNXI_GEN_SUN6I
+-	select SUPPORT_SPL
+ 	select SYS_I2C_SUN8I_RSB
+ 	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
+ 
+@@ -268,7 +259,6 @@ config MACH_SUN8I_A83T
+ 	select SUNXI_GEN_SUN6I
+ 	select MMC_SUNXI_HAS_NEW_MODE
+ 	select MMC_SUNXI_HAS_MODE_SWITCH
+-	select SUPPORT_SPL
+ 	select SYS_I2C_SUN8I_RSB
+ 
+ config MACH_SUN8I_H3
+@@ -288,7 +278,6 @@ config MACH_SUN8I_R40
+ 	select ARCH_SUPPORT_PSCI
+ 	select SUNXI_GEN_SUN6I
+ 	select MMC_SUNXI_HAS_NEW_MODE
+-	select SUPPORT_SPL
+ 	select SUNXI_DRAM_DW
+ 	select SUNXI_DRAM_DW_32BIT
+ 	imply SPL_SYS_I2C_LEGACY
+@@ -302,7 +291,6 @@ config MACH_SUN8I_V3S
+ 	select SUNXI_GEN_SUN6I
+ 	select SUNXI_DRAM_DW
+ 	select SUNXI_DRAM_DW_16BIT
+-	select SUPPORT_SPL
+ 	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
+ 
+ config MACH_SUN9I
+@@ -313,7 +301,6 @@ config MACH_SUN9I
+ 	select SPL_I2C
+ 	select SUN6I_PRCM
+ 	select SUNXI_GEN_SUN6I
+-	select SUPPORT_SPL
+ 
+ config MACH_SUN50I
+ 	bool "sun50i (Allwinner A64)"
+@@ -322,7 +309,6 @@ config MACH_SUN50I
+ 	select SUNXI_DE2
+ 	select SUNXI_GEN_SUN6I
+ 	select MMC_SUNXI_HAS_NEW_MODE
+-	select SUPPORT_SPL
+ 	select SUNXI_DRAM_DW
+ 	select SUNXI_DRAM_DW_32BIT
+ 	select FIT
+--- a/board/sunxi/Kconfig
++++ b/board/sunxi/Kconfig
+@@ -18,6 +18,7 @@ config BOARD_SUNXI
+ 	select SPL_SEPARATE_BSS if SPL
+ 	select SUNXI_GPIO if GPIO
+ 	select SYS_NS16550 if SERIAL
++	select SUPPORT_SPL
+ 	select SYS_RELOC_GD_ENV_ADDR
+ 	select USB if DISTRO_DEFAULTS
+ 	select USB_KEYBOARD if DISTRO_DEFAULTS && USB_HOST
+@@ -31,6 +32,7 @@ config BOARD_SUNXI
+ 	imply FIT
+ 	imply OF_LIBFDT_OVERLAY
+ 	imply PRE_CONSOLE_BUFFER
++	imply SPL
+ 	imply SPL_GPIO
+ 	imply SPL_LIBCOMMON_SUPPORT
+ 	imply SPL_LIBGENERIC_SUPPORT
diff --git a/package/boot/uboot-d1/patches/0061-sunxi-Downgrade-driver-selections-to-implications.patch b/package/boot/uboot-d1/patches/0061-sunxi-Downgrade-driver-selections-to-implications.patch
new file mode 100644
index 00000000000000..e77c5cb080fa4f
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0061-sunxi-Downgrade-driver-selections-to-implications.patch
@@ -0,0 +1,33 @@
+From 6c8707fcd3372015829a1e8b8d5e8030c5806382 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 6 Aug 2022 00:10:46 -0500
+Subject: [PATCH 61/90] sunxi: Downgrade driver selections to implications
+
+While not especially likely, it is plausible that someone wants to build
+U-Boot without GPIO or UART support. Don't force building these drivers.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ board/sunxi/Kconfig | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/board/sunxi/Kconfig
++++ b/board/sunxi/Kconfig
+@@ -16,8 +16,6 @@ config BOARD_SUNXI
+ 	select OF_BOARD_SETUP
+ 	select PINCTRL
+ 	select SPL_SEPARATE_BSS if SPL
+-	select SUNXI_GPIO if GPIO
+-	select SYS_NS16550 if SERIAL
+ 	select SUPPORT_SPL
+ 	select SYS_RELOC_GD_ENV_ADDR
+ 	select USB if DISTRO_DEFAULTS
+@@ -39,6 +37,8 @@ config BOARD_SUNXI
+ 	imply SPL_MMC if MMC
+ 	imply SPL_POWER
+ 	imply SPL_SERIAL
++	imply SUNXI_GPIO
++	imply SYS_NS16550
+ 	imply SYSRESET
+ 	imply SYSRESET_WATCHDOG
+ 	imply SYSRESET_WATCHDOG_AUTO
diff --git a/package/boot/uboot-d1/patches/0062-sunxi-Enable-the-I2C-driver-by-default.patch b/package/boot/uboot-d1/patches/0062-sunxi-Enable-the-I2C-driver-by-default.patch
new file mode 100644
index 00000000000000..e6d963e812a888
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0062-sunxi-Enable-the-I2C-driver-by-default.patch
@@ -0,0 +1,23 @@
+From ad619478827b825d7b88dce22eb9b5e1c6ea7eb0 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 6 Aug 2022 00:11:54 -0500
+Subject: [PATCH 62/90] sunxi: Enable the I2C driver by default
+
+This is used by quite a large number of boards, for PMIC/regulator or
+LCD panel control.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ board/sunxi/Kconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/board/sunxi/Kconfig
++++ b/board/sunxi/Kconfig
+@@ -38,6 +38,7 @@ config BOARD_SUNXI
+ 	imply SPL_POWER
+ 	imply SPL_SERIAL
+ 	imply SUNXI_GPIO
++	imply SYS_I2C_MVTWSI
+ 	imply SYS_NS16550
+ 	imply SYSRESET
+ 	imply SYSRESET_WATCHDOG
diff --git a/package/boot/uboot-d1/patches/0063-sunxi-Move-default-values-to-the-board-Kconfig.patch b/package/boot/uboot-d1/patches/0063-sunxi-Move-default-values-to-the-board-Kconfig.patch
new file mode 100644
index 00000000000000..17bf8cb3ace5ed
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0063-sunxi-Move-default-values-to-the-board-Kconfig.patch
@@ -0,0 +1,190 @@
+From fde804c2ece090eb7802a218781e38c7c6d6f00d Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Fri, 5 Aug 2022 23:10:11 -0500
+Subject: [PATCH 63/90] sunxi: Move default values to the board Kconfig
+
+This keeps all of the defaults for sunxi platforms in one place. Most of
+these only depend on architecture-independent features of the SoC (clock
+tree or SRAM layout) anyway.
+
+No functional change; just some minor help text cleanup.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm/mach-sunxi/Kconfig | 67 ------------------------------------
+ board/sunxi/Kconfig         | 68 +++++++++++++++++++++++++++++++++++++
+ 2 files changed, 68 insertions(+), 67 deletions(-)
+
+--- a/arch/arm/mach-sunxi/Kconfig
++++ b/arch/arm/mach-sunxi/Kconfig
+@@ -1,8 +1,5 @@
+ if ARCH_SUNXI
+ 
+-config IDENT_STRING
+-	default " Allwinner Technology"
+-
+ config DRAM_SUN4I
+ 	bool
+ 	help
+@@ -99,17 +96,6 @@ config AXP_PMIC_BUS
+ 	  Select this PMIC bus access helpers for Sunxi platform PRCM or other
+ 	  AXP family PMIC devices.
+ 
+-config SUNXI_SRAM_ADDRESS
+-	hex
+-	default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5
+-	default 0x20000 if SUN50I_GEN_H6
+-	default 0x0
+-	---help---
+-	Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
+-	with the first SRAM region being located at address 0.
+-	Some newer SoCs map the boot ROM at address 0 instead and move the
+-	SRAM to a different address.
+-
+ config SUNXI_A64_TIMER_ERRATUM
+ 	bool
+ 
+@@ -562,48 +548,6 @@ config DRAM_ODT_CORRECTION
+ 	then the correction is negative. Usually the value for this is 0.
+ endif
+ 
+-config SYS_CLK_FREQ
+-	default 408000000 if MACH_SUNIV
+-	default 1008000000 if MACH_SUN4I
+-	default 1008000000 if MACH_SUN5I
+-	default 1008000000 if MACH_SUN6I
+-	default 912000000 if MACH_SUN7I
+-	default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
+-	default 1008000000 if MACH_SUN8I
+-	default 1008000000 if MACH_SUN9I
+-	default 888000000 if MACH_SUN50I_H6
+-	default 1008000000 if MACH_SUN50I_H616
+-
+-config SYS_CONFIG_NAME
+-	default "suniv" if MACH_SUNIV
+-	default "sun4i" if MACH_SUN4I
+-	default "sun5i" if MACH_SUN5I
+-	default "sun6i" if MACH_SUN6I
+-	default "sun7i" if MACH_SUN7I
+-	default "sun8i" if MACH_SUN8I
+-	default "sun9i" if MACH_SUN9I
+-	default "sun50i" if MACH_SUN50I
+-	default "sun50i" if MACH_SUN50I_H6
+-	default "sun50i" if MACH_SUN50I_H616
+-
+-config SYS_BOARD
+-	default "sunxi"
+-
+-config SYS_SOC
+-	default "sunxi"
+-
+-config SUNXI_MINIMUM_DRAM_MB
+-	int "minimum DRAM size"
+-	default 32 if MACH_SUNIV
+-	default 64 if MACH_SUN8I_V3S
+-	default 256
+-	---help---
+-	Minimum DRAM size expected on the board. Traditionally we assumed
+-	256 MB, so that U-Boot would load at 160MB. With co-packaged DRAM
+-	we have smaller sizes, though, so that U-Boot's own load address and
+-	the default payload addresses must be shifted down.
+-	This is expected to be fixed by the SoC selection.
+-
+ config UART0_PORT_F
+ 	bool "UART0 on MicroSD breakout board"
+ 	---help---
+@@ -898,17 +842,6 @@ config GMAC_TX_DELAY
+ 	---help---
+ 	Set the GMAC Transmit Clock Delay Chain value.
+ 
+-config SPL_STACK_R_ADDR
+-	default 0x81e00000 if MACH_SUNIV
+-	default 0x4fe00000 if MACH_SUN4I
+-	default 0x4fe00000 if MACH_SUN5I
+-	default 0x4fe00000 if MACH_SUN6I
+-	default 0x4fe00000 if MACH_SUN7I
+-	default 0x4fe00000 if MACH_SUN8I
+-	default 0x2fe00000 if MACH_SUN9I
+-	default 0x4fe00000 if MACH_SUN50I
+-	default 0x4fe00000 if SUN50I_GEN_H6
+-
+ config SPL_SPI_SUNXI
+ 	bool "Support for SPI Flash on Allwinner SoCs in SPL"
+ 	depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || SUN50I_GEN_H6 || MACH_SUNIV
+--- a/board/sunxi/Kconfig
++++ b/board/sunxi/Kconfig
+@@ -52,6 +52,74 @@ config BOARD_SUNXI
+ 
+ if BOARD_SUNXI
+ 
++config IDENT_STRING
++	default " Allwinner Technology"
++
++config SPL_STACK_R_ADDR
++	default 0x81e00000 if MACH_SUNIV
++	default 0x4fe00000 if MACH_SUN4I
++	default 0x4fe00000 if MACH_SUN5I
++	default 0x4fe00000 if MACH_SUN6I
++	default 0x4fe00000 if MACH_SUN7I
++	default 0x4fe00000 if MACH_SUN8I
++	default 0x2fe00000 if MACH_SUN9I
++	default 0x4fe00000 if MACH_SUN50I
++	default 0x4fe00000 if SUN50I_GEN_H6
++
++config SUNXI_MINIMUM_DRAM_MB
++	int "minimum DRAM size"
++	default 32 if MACH_SUNIV
++	default 64 if MACH_SUN8I_V3S
++	default 256
++	help
++	  Minimum DRAM size expected on the board. Traditionally we
++	  assumed 256 MB, so that U-Boot would load at 160MB. With
++	  co-packaged DRAM we have smaller sizes, though, so U-Boot's
++	  own load address and the default payload addresses must be
++	  shifted down. This is expected to be fixed by the SoC
++	  selection.
++
++config SUNXI_SRAM_ADDRESS
++	hex
++	default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5
++	default 0x20000 if SUN50I_GEN_H6
++	default 0x0
++	help
++	  Older Allwinner SoCs have their boot mask ROM mapped just
++	  below 4GB, with the first SRAM region located at address 0.
++	  Newer SoCs map the boot ROM at address 0 instead and move the
++	  SRAM to a different address.
++
++config SYS_BOARD
++	default "sunxi"
++
++config SYS_CLK_FREQ
++	default  408000000 if MACH_SUNIV
++	default 1008000000 if MACH_SUN4I
++	default 1008000000 if MACH_SUN5I
++	default 1008000000 if MACH_SUN6I
++	default  912000000 if MACH_SUN7I
++	default 1008000000 if MACH_SUN8I
++	default 1008000000 if MACH_SUN9I
++	default  816000000 if MACH_SUN50I || MACH_SUN50I_H5
++	default  888000000 if MACH_SUN50I_H6
++	default 1008000000 if MACH_SUN50I_H616
++
++config SYS_CONFIG_NAME
++	default "suniv"  if MACH_SUNIV
++	default "sun4i"  if MACH_SUN4I
++	default "sun5i"  if MACH_SUN5I
++	default "sun6i"  if MACH_SUN6I
++	default "sun7i"  if MACH_SUN7I
++	default "sun8i"  if MACH_SUN8I
++	default "sun9i"  if MACH_SUN9I
++	default "sun50i" if MACH_SUN50I
++	default "sun50i" if MACH_SUN50I_H6
++	default "sun50i" if MACH_SUN50I_H616
++
++config SYS_SOC
++	default "sunxi"
++
+ menu "sunxi board options"
+ 
+ choice
diff --git a/package/boot/uboot-d1/patches/0064-sunxi-Hide-the-SUNXI_MINIMUM_DRAM_MB-symbol.patch b/package/boot/uboot-d1/patches/0064-sunxi-Hide-the-SUNXI_MINIMUM_DRAM_MB-symbol.patch
new file mode 100644
index 00000000000000..76486485971bd2
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0064-sunxi-Hide-the-SUNXI_MINIMUM_DRAM_MB-symbol.patch
@@ -0,0 +1,24 @@
+From 8377aa2162d0a7fda76597eae59725a298dda5e6 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Mon, 31 Oct 2022 22:14:36 -0500
+Subject: [PATCH 64/90] sunxi: Hide the SUNXI_MINIMUM_DRAM_MB symbol
+
+This option affects the ABI between SPL/U-Boot and U-Boot/scripts, so it
+should not normally be changed by the user.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ board/sunxi/Kconfig | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/board/sunxi/Kconfig
++++ b/board/sunxi/Kconfig
+@@ -67,7 +67,7 @@ config SPL_STACK_R_ADDR
+ 	default 0x4fe00000 if SUN50I_GEN_H6
+ 
+ config SUNXI_MINIMUM_DRAM_MB
+-	int "minimum DRAM size"
++	int
+ 	default 32 if MACH_SUNIV
+ 	default 64 if MACH_SUN8I_V3S
+ 	default 256
diff --git a/package/boot/uboot-d1/patches/0065-sunxi-Clean-up-the-SPL_STACK_R_ADDR-defaults.patch b/package/boot/uboot-d1/patches/0065-sunxi-Clean-up-the-SPL_STACK_R_ADDR-defaults.patch
new file mode 100644
index 00000000000000..1a662bea2c32ab
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0065-sunxi-Clean-up-the-SPL_STACK_R_ADDR-defaults.patch
@@ -0,0 +1,33 @@
+From 41e5a94533e9744b8eac718dd2c359eca57573f8 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Fri, 5 Aug 2022 23:25:26 -0500
+Subject: [PATCH 65/90] sunxi: Clean up the SPL_STACK_R_ADDR defaults
+
+Update this option to be based on SUNXI_MINIMUM_DRAM_MB. This corrects
+the value used on V3s, which previously was the MACH_SUN8I default, and
+so relied on addresses wrapping modulo the DRAM size.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ board/sunxi/Kconfig | 9 ++-------
+ 1 file changed, 2 insertions(+), 7 deletions(-)
+
+--- a/board/sunxi/Kconfig
++++ b/board/sunxi/Kconfig
+@@ -57,14 +57,9 @@ config IDENT_STRING
+ 
+ config SPL_STACK_R_ADDR
+ 	default 0x81e00000 if MACH_SUNIV
+-	default 0x4fe00000 if MACH_SUN4I
+-	default 0x4fe00000 if MACH_SUN5I
+-	default 0x4fe00000 if MACH_SUN6I
+-	default 0x4fe00000 if MACH_SUN7I
+-	default 0x4fe00000 if MACH_SUN8I
+ 	default 0x2fe00000 if MACH_SUN9I
+-	default 0x4fe00000 if MACH_SUN50I
+-	default 0x4fe00000 if SUN50I_GEN_H6
++	default 0x4fe00000 if SUNXI_MINIMUM_DRAM_MB >= 256
++	default 0x43e00000 if SUNXI_MINIMUM_DRAM_MB >= 64
+ 
+ config SUNXI_MINIMUM_DRAM_MB
+ 	int
diff --git a/package/boot/uboot-d1/patches/0066-sunxi-Move-PRE_CON_BUF_ADDR-to-the-board-Kconfig.patch b/package/boot/uboot-d1/patches/0066-sunxi-Move-PRE_CON_BUF_ADDR-to-the-board-Kconfig.patch
new file mode 100644
index 00000000000000..daaf0b5fc60ddd
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0066-sunxi-Move-PRE_CON_BUF_ADDR-to-the-board-Kconfig.patch
@@ -0,0 +1,42 @@
+From e947c7377b90897e4c638dad6e64201361dc8a9e Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 6 Aug 2022 00:45:10 -0500
+Subject: [PATCH 66/90] sunxi: Move PRE_CON_BUF_ADDR to the board Kconfig
+
+This provides a default value for RISC-V when that is added, and it
+makes sense to put this option next to the other DRAM layout options.
+
+While at it, provide sensible values for platforms with less DRAM.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ board/sunxi/Kconfig | 6 ++++++
+ common/Kconfig      | 2 --
+ 2 files changed, 6 insertions(+), 2 deletions(-)
+
+--- a/board/sunxi/Kconfig
++++ b/board/sunxi/Kconfig
+@@ -55,6 +55,12 @@ if BOARD_SUNXI
+ config IDENT_STRING
+ 	default " Allwinner Technology"
+ 
++config PRE_CON_BUF_ADDR
++	default 0x81000000 if MACH_SUNIV
++	default 0x2f000000 if MACH_SUN9I
++	default 0x4f000000 if SUNXI_MINIMUM_DRAM_MB >= 256
++	default 0x43000000 if SUNXI_MINIMUM_DRAM_MB >= 64
++
+ config SPL_STACK_R_ADDR
+ 	default 0x81e00000 if MACH_SUNIV
+ 	default 0x2fe00000 if MACH_SUN9I
+--- a/common/Kconfig
++++ b/common/Kconfig
+@@ -195,8 +195,6 @@ config PRE_CON_BUF_SZ
+ config PRE_CON_BUF_ADDR
+ 	hex "Address of the pre-console buffer"
+ 	depends on PRE_CONSOLE_BUFFER
+-	default 0x2f000000 if ARCH_SUNXI && MACH_SUN9I
+-	default 0x4f000000 if ARCH_SUNXI && !MACH_SUN9I
+ 	default 0x0f000000 if ROCKCHIP_RK3288
+ 	default 0x0f200000 if ROCKCHIP_RK3399
+ 	help
diff --git a/package/boot/uboot-d1/patches/0067-sunxi-Move-SPL_BSS_START_ADDR-to-the-board-Kconfig.patch b/package/boot/uboot-d1/patches/0067-sunxi-Move-SPL_BSS_START_ADDR-to-the-board-Kconfig.patch
new file mode 100644
index 00000000000000..286b2b976b20f6
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0067-sunxi-Move-SPL_BSS_START_ADDR-to-the-board-Kconfig.patch
@@ -0,0 +1,43 @@
+From 71796f9d47a6b7e0dd6bb276436950463039c1b8 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Mon, 31 Oct 2022 00:08:26 -0500
+Subject: [PATCH 67/90] sunxi: Move SPL_BSS_START_ADDR to the board Kconfig
+
+This provides a default value for RISC-V when that is added, and it
+makes sense to put this option next to the other DRAM layout options.
+
+While at it, provide sensible values for platforms with less DRAM.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ board/sunxi/Kconfig | 6 ++++++
+ common/spl/Kconfig  | 3 ---
+ 2 files changed, 6 insertions(+), 3 deletions(-)
+
+--- a/board/sunxi/Kconfig
++++ b/board/sunxi/Kconfig
+@@ -61,6 +61,12 @@ config PRE_CON_BUF_ADDR
+ 	default 0x4f000000 if SUNXI_MINIMUM_DRAM_MB >= 256
+ 	default 0x43000000 if SUNXI_MINIMUM_DRAM_MB >= 64
+ 
++config SPL_BSS_START_ADDR
++	default 0x81f80000 if MACH_SUNIV
++	default 0x2ff80000 if MACH_SUN9I
++	default 0x4ff80000 if SUNXI_MINIMUM_DRAM_MB >= 256
++	default 0x43f80000 if SUNXI_MINIMUM_DRAM_MB >= 64
++
+ config SPL_STACK_R_ADDR
+ 	default 0x81e00000 if MACH_SUNIV
+ 	default 0x2fe00000 if MACH_SUN9I
+--- a/common/spl/Kconfig
++++ b/common/spl/Kconfig
+@@ -119,9 +119,6 @@ config SPL_BSS_START_ADDR
+ 	default 0x88200000 if (ARCH_MX6 && (MX6SX || MX6SL || MX6UL || MX6ULL)) || ARCH_MX7
+ 	default 0x18200000 if ARCH_MX6 && !(MX6SX || MX6SL || MX6UL || MX6ULL)
+ 	default 0x80a00000 if ARCH_OMAP2PLUS
+-	default 0x81f80000 if ARCH_SUNXI && MACH_SUNIV
+-	default 0x4ff80000 if ARCH_SUNXI && !(MACH_SUN9I || MACH_SUNIV)
+-	default 0x2ff80000 if ARCH_SUNXI && MACH_SUN9I
+ 	default 0x1000 if ARCH_ZYNQMP
+ 
+ choice
diff --git a/package/boot/uboot-d1/patches/0068-sunxi-Move-SPL_TEXT_BASE-to-the-board-Kconfig.patch b/package/boot/uboot-d1/patches/0068-sunxi-Move-SPL_TEXT_BASE-to-the-board-Kconfig.patch
new file mode 100644
index 00000000000000..77aa5929435261
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0068-sunxi-Move-SPL_TEXT_BASE-to-the-board-Kconfig.patch
@@ -0,0 +1,39 @@
+From 5d60490d0f0ca0a5d414ba9a4e41ceea8a98b4d2 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 6 Aug 2022 00:07:47 -0500
+Subject: [PATCH 68/90] sunxi: Move SPL_TEXT_BASE to the board Kconfig
+
+It makes sense to put this near the definition of SUNXI_SRAM_ADDRESS.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ board/sunxi/Kconfig | 5 +++++
+ common/spl/Kconfig  | 3 ---
+ 2 files changed, 5 insertions(+), 3 deletions(-)
+
+--- a/board/sunxi/Kconfig
++++ b/board/sunxi/Kconfig
+@@ -73,6 +73,11 @@ config SPL_STACK_R_ADDR
+ 	default 0x4fe00000 if SUNXI_MINIMUM_DRAM_MB >= 256
+ 	default 0x43e00000 if SUNXI_MINIMUM_DRAM_MB >= 64
+ 
++config SPL_TEXT_BASE
++	default 0x10060 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5
++	default 0x20060 if SUN50I_GEN_H6
++	default 0x00060
++
+ config SUNXI_MINIMUM_DRAM_MB
+ 	int
+ 	default 32 if MACH_SUNIV
+--- a/common/spl/Kconfig
++++ b/common/spl/Kconfig
+@@ -261,9 +261,6 @@ config SPL_TEXT_BASE
+ 	default 0x402F4000 if AM43XX
+ 	default 0x402F0400 if AM33XX
+ 	default 0x40301350 if OMAP54XX
+-	default 0x10060 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN9I
+-	default 0x20060 if SUN50I_GEN_H6
+-	default 0x00060 if ARCH_SUNXI
+ 	default 0xfffc0000 if ARCH_ZYNQMP
+ 	default 0x0
+ 	help
diff --git a/package/boot/uboot-d1/patches/0069-sunxi-Move-SYS_LOAD_ADDR-to-the-board-Kconfig.patch b/package/boot/uboot-d1/patches/0069-sunxi-Move-SYS_LOAD_ADDR-to-the-board-Kconfig.patch
new file mode 100644
index 00000000000000..3d6e3018daeca3
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0069-sunxi-Move-SYS_LOAD_ADDR-to-the-board-Kconfig.patch
@@ -0,0 +1,40 @@
+From 03f3ba82e9dfb67f1ae0812f72aea6559aa61bb4 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Fri, 5 Aug 2022 23:23:34 -0500
+Subject: [PATCH 69/90] sunxi: Move SYS_LOAD_ADDR to the board Kconfig
+
+This will provide a default value for RISC-V when that is added, and it
+makes sense to put this option next to the other DRAM layout options.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ Kconfig             | 3 ---
+ board/sunxi/Kconfig | 5 +++++
+ 2 files changed, 5 insertions(+), 3 deletions(-)
+
+--- a/Kconfig
++++ b/Kconfig
+@@ -508,9 +508,6 @@ config SYS_LOAD_ADDR
+ 	hex "Address in memory to use by default"
+ 	default 0x01000000 if ARCH_SOCFPGA
+ 	default 0x02000000 if PPC || X86
+-	default 0x81000000 if MACH_SUNIV
+-	default 0x22000000 if MACH_SUN9I
+-	default 0x42000000 if ARCH_SUNXI
+ 	default 0x82000000 if ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_K3
+ 	default 0x82000000 if ARCH_MX6 && (MX6SL || MX6SLL  || MX6SX || MX6UL || MX6ULL)
+ 	default 0x12000000 if ARCH_MX6 && !(MX6SL || MX6SLL  || MX6SX || MX6UL || MX6ULL)
+--- a/board/sunxi/Kconfig
++++ b/board/sunxi/Kconfig
+@@ -129,6 +129,11 @@ config SYS_CONFIG_NAME
+ 	default "sun50i" if MACH_SUN50I_H6
+ 	default "sun50i" if MACH_SUN50I_H616
+ 
++config SYS_LOAD_ADDR
++	default 0x81000000 if MACH_SUNIV
++	default 0x22000000 if MACH_SUN9I
++	default 0x42000000
++
+ config SYS_SOC
+ 	default "sunxi"
+ 
diff --git a/package/boot/uboot-d1/patches/0070-sunxi-Move-TEXT_BASE-to-the-board-Kconfig.patch b/package/boot/uboot-d1/patches/0070-sunxi-Move-TEXT_BASE-to-the-board-Kconfig.patch
new file mode 100644
index 00000000000000..910e02c0d27ed3
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0070-sunxi-Move-TEXT_BASE-to-the-board-Kconfig.patch
@@ -0,0 +1,42 @@
+From 08b45a89c7b25eb7828589360cf4ca2d9910cc59 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Fri, 5 Aug 2022 21:48:53 -0500
+Subject: [PATCH 70/90] sunxi: Move TEXT_BASE to the board Kconfig
+
+This is how the vast majority of platforms provided TEXT_BASE.
+sunxi was the exception here.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ board/sunxi/Kconfig | 6 ++++++
+ boot/Kconfig        | 4 ----
+ 2 files changed, 6 insertions(+), 4 deletions(-)
+
+--- a/board/sunxi/Kconfig
++++ b/board/sunxi/Kconfig
+@@ -137,6 +137,12 @@ config SYS_LOAD_ADDR
+ config SYS_SOC
+ 	default "sunxi"
+ 
++config TEXT_BASE
++	default 0x81700000 if MACH_SUNIV
++	default 0x2a000000 if MACH_SUN9I
++	default 0x4a000000 if SUNXI_MINIMUM_DRAM_MB >= 256
++	default 0x42e00000 if SUNXI_MINIMUM_DRAM_MB >= 64
++
+ menu "sunxi board options"
+ 
+ choice
+--- a/boot/Kconfig
++++ b/boot/Kconfig
+@@ -633,10 +633,6 @@ config TEXT_BASE
+ 	depends on HAVE_TEXT_BASE
+ 	default 0x0 if POSITION_INDEPENDENT
+ 	default 0x80800000 if ARCH_OMAP2PLUS || ARCH_K3
+-	default 0x81700000 if MACH_SUNIV
+-	default 0x2a000000 if MACH_SUN9I
+-	default 0x4a000000 if SUNXI_MINIMUM_DRAM_MB >= 256
+-	default 0x42e00000 if SUNXI_MINIMUM_DRAM_MB >= 64
+ 	hex "Text Base"
+ 	help
+ 	  The address in memory that U-Boot will be running from, initially.
diff --git a/package/boot/uboot-d1/patches/0071-sunxi-Move-most-board-options-to-the-board-Kconfig.patch b/package/boot/uboot-d1/patches/0071-sunxi-Move-most-board-options-to-the-board-Kconfig.patch
new file mode 100644
index 00000000000000..fdcd72568766cf
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0071-sunxi-Move-most-board-options-to-the-board-Kconfig.patch
@@ -0,0 +1,197 @@
+From 6a1b660a83b262237b6bebed26e44db923a86a6b Mon Sep 17 00:00:00 2001
+From: Zoltan HERPAI <wigyori@uid0.hu>
+Date: Tue, 6 Jun 2023 18:09:19 +0000
+Subject: [PATCH 71/90] sunxi: Move most board options to the board Kconfig
+
+This excludes options that are inherently ARM-specific or are specific
+to legacy non-DM drivers.
+
+Some help text is cleaned up along the way.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
+---
+ arch/arm/mach-sunxi/Kconfig | 71 ------------------------------------
+ board/sunxi/Kconfig         | 72 +++++++++++++++++++++++++++++++++++++
+ 2 files changed, 72 insertions(+), 71 deletions(-)
+
+--- a/arch/arm/mach-sunxi/Kconfig
++++ b/arch/arm/mach-sunxi/Kconfig
+@@ -548,16 +548,6 @@ config DRAM_ODT_CORRECTION
+ 	then the correction is negative. Usually the value for this is 0.
+ endif
+ 
+-config UART0_PORT_F
+-	bool "UART0 on MicroSD breakout board"
+-	---help---
+-	Repurpose the SD card slot for getting access to the UART0 serial
+-	console. Primarily useful only for low level u-boot debugging on
+-	tablets, where normal UART0 is difficult to access and requires
+-	device disassembly and/or soldering. As the SD card can't be used
+-	at the same time, the system can be only booted in the FEL mode.
+-	Only enable this if you really know what you are doing.
+-
+ config OLD_SUNXI_KERNEL_COMPAT
+ 	bool "Enable workarounds for booting old kernels"
+ 	---help---
+@@ -571,20 +561,6 @@ config MACPWR
+ 	  Set the pin used to power the MAC. This takes a string in the format
+ 	  understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
+ 
+-config MMC1_PINS_PH
+-	bool "Pins for mmc1 are on Port H"
+-	depends on MACH_SUN4I || MACH_SUN7I || MACH_SUN8I_R40
+-	---help---
+-	Select this option for boards where mmc1 uses the Port H pinmux.
+-
+-config MMC_SUNXI_SLOT_EXTRA
+-	int "mmc extra slot number"
+-	default -1
+-	---help---
+-	sunxi builds always enable mmc0, some boards also have a second sdcard
+-	slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
+-	support for this.
+-
+ config I2C0_ENABLE
+ 	bool "Enable I2C/TWI controller 0"
+ 	default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
+@@ -612,16 +588,6 @@ config R_I2C_ENABLE
+ 	Set this to y to enable the I2C controller which is part of the PRCM.
+ endif
+ 
+-config AXP_DISABLE_BOOT_ON_POWERON
+-	bool "Disable device boot on power plug-in"
+-	depends on AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER
+-	default n
+-	---help---
+-	  Say Y here to prevent the device from booting up because of a plug-in
+-	  event. When set, the device will boot into the SPL briefly to
+-	  determine why it was powered on, and if it was determined because of
+-	  a plug-in event instead of a button press event it will shut back off.
+-
+ config VIDEO_SUNXI
+ 	bool "Enable graphical uboot console on HDMI, LCD or VGA"
+ 	depends on !MACH_SUN8I_A83T
+@@ -850,41 +816,4 @@ config SPL_SPI_SUNXI
+ 	  sunxi SPI Flash. It uses the same method as the boot ROM, so does
+ 	  not need any extra configuration.
+ 
+-config PINE64_DT_SELECTION
+-	bool "Enable Pine64 device tree selection code"
+-	depends on MACH_SUN50I
+-	help
+-	  The original Pine A64 and Pine A64+ are similar but different
+-	  boards and can be differed by the DRAM size. Pine A64 has
+-	  512MiB DRAM, and Pine A64+ has 1GiB or 2GiB. By selecting this
+-	  option, the device tree selection code specific to Pine64 which
+-	  utilizes the DRAM size will be enabled.
+-
+-config PINEPHONE_DT_SELECTION
+-	bool "Enable PinePhone device tree selection code"
+-	depends on MACH_SUN50I
+-	help
+-	  Enable this option to automatically select the device tree for the
+-	  correct PinePhone hardware revision during boot.
+-
+-config BLUETOOTH_DT_DEVICE_FIXUP
+-	string "Fixup the Bluetooth controller address"
+-	default ""
+-	help
+-	  This option specifies the DT compatible name of the Bluetooth
+-	  controller for which to set the "local-bd-address" property.
+-	  Set this option if your device ships with the Bluetooth controller
+-	  default address.
+-	  The used address is "bdaddr" if set, and "ethaddr" with the LSB
+-	  flipped elsewise.
+-
+ endif
+-
+-config CHIP_DIP_SCAN
+-	bool "Enable DIPs detection for CHIP board"
+-	select SUPPORT_EXTENSION_SCAN
+-	select W1
+-	select W1_GPIO
+-	select W1_EEPROM
+-	select W1_EEPROM_DS24XXX
+-	select CMD_EXTENSION
+--- a/board/sunxi/Kconfig
++++ b/board/sunxi/Kconfig
+@@ -171,6 +171,78 @@ config SPL_IMAGE_TYPE
+ 	default "sunxi_egon" if SPL_IMAGE_TYPE_SUNXI_EGON
+ 	default "sunxi_toc0" if SPL_IMAGE_TYPE_SUNXI_TOC0
+ 
++config MMC_SUNXI_SLOT_EXTRA
++	int "MMC extra slot number"
++	default -1
++	help
++	  sunxi builds always enable mmc0. Some boards also have a
++	  second SD card slot or eMMC on mmc1 - mmc3. Setting this to 1,
++	  2 or 3 will enable support for this.
++
++config MMC1_PINS_PH
++	bool "MMC1 pins are on Port H"
++	depends on MACH_SUN4I || MACH_SUN7I || MACH_SUN8I_R40
++	help
++	  Select this option on boards where mmc1 uses the Port H pinmux.
++
++config UART0_PORT_F
++	bool "UART0 pins are on Port F (MicroSD breakout board)"
++	help
++	  Repurpose the SD card slot for getting access to the UART0
++	  serial console. Primarily useful only for low level u-boot
++	  debugging on tablets, where normal UART0 is difficult to
++	  access and requires device disassembly and/or soldering. As
++	  the SD card can't be used at the same time, the system can be
++	  only booted in FEL mode. Only enable this if you really know
++	  what you are doing.
++
++config AXP_DISABLE_BOOT_ON_POWERON
++	bool "Disable device boot on power plug-in"
++	depends on AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER
++	help
++	  Say Y here to prevent the device from booting up because of a
++	  plug-in event. When set, the device will boot into the SPL
++	  briefly to determine why it was powered on, and if the board
++	  was powered on because of a plug-in event instead of a button
++	  press event, it will shut back off.
++
++config CHIP_DIP_SCAN
++	bool "Enable DIPs detection for CHIP board"
++	select SUPPORT_EXTENSION_SCAN
++	select W1
++	select W1_GPIO
++	select W1_EEPROM
++	select W1_EEPROM_DS24XXX
++	select CMD_EXTENSION
++
++config PINE64_DT_SELECTION
++	bool "Enable Pine64 device tree selection code"
++	depends on MACH_SUN50I
++	help
++	  The original Pine A64 and Pine A64+ are similar but different
++	  boards and can be differed by the DRAM size. Pine A64 has
++	  512MiB DRAM, and Pine A64+ has 1GiB or 2GiB. By selecting this
++	  option, the device tree selection code specific to Pine64 which
++	  utilizes the DRAM size will be enabled.
++
++config PINEPHONE_DT_SELECTION
++	bool "Enable PinePhone device tree selection code"
++	depends on MACH_SUN50I
++	help
++	  Enable this option to automatically select the device tree for the
++	  correct PinePhone hardware revision during boot.
++
++config BLUETOOTH_DT_DEVICE_FIXUP
++	string "Fixup the Bluetooth controller address"
++	default ""
++	help
++	  This option specifies the DT compatible name of the Bluetooth
++	  controller for which to set the "local-bd-address" property.
++	  Set this option if your device ships with the Bluetooth controller
++	  default address.
++	  The used address is "bdaddr" if set, and "ethaddr" with the LSB
++	  flipped elsewise.
++
+ endmenu
+ 
+ endif
diff --git a/package/boot/uboot-d1/patches/0072-env-sunxi-Replace-ARCH_SUNXI-with-BOARD_SUNXI.patch b/package/boot/uboot-d1/patches/0072-env-sunxi-Replace-ARCH_SUNXI-with-BOARD_SUNXI.patch
new file mode 100644
index 00000000000000..3fcfc205953e2c
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0072-env-sunxi-Replace-ARCH_SUNXI-with-BOARD_SUNXI.patch
@@ -0,0 +1,69 @@
+From 27834df51087a005b0330f094492b984cc225f6a Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Fri, 5 Aug 2022 23:28:54 -0500
+Subject: [PATCH 72/90] env: sunxi: Replace ARCH_SUNXI with BOARD_SUNXI
+
+This ensures the same environment layout will be used across all sunxi
+boards, regardless of CPU architecture.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ env/Kconfig | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+--- a/env/Kconfig
++++ b/env/Kconfig
+@@ -92,7 +92,7 @@ config ENV_IS_IN_FAT
+ 	bool "Environment is in a FAT filesystem"
+ 	depends on !CHAIN_OF_TRUST
+ 	default y if ARCH_BCM283X
+-	default y if ARCH_SUNXI && MMC
++	default y if BOARD_SUNXI && MMC
+ 	default y if MMC_OMAP_HS && TI_COMMON_CMD_OPTIONS
+ 	select FS_FAT
+ 	select FAT_WRITE
+@@ -338,7 +338,7 @@ config ENV_IS_IN_SPI_FLASH
+ 	default y if NORTHBRIDGE_INTEL_IVYBRIDGE
+ 	default y if INTEL_QUARK
+ 	default y if INTEL_QUEENSBAY
+-	default y if ARCH_SUNXI
++	default y if BOARD_SUNXI
+ 	help
+ 	  Define this if you have a SPI Flash memory device which you
+ 	  want to use for the environment.
+@@ -461,7 +461,7 @@ config ENV_FAT_DEVICE_AND_PART
+ 	depends on ENV_IS_IN_FAT
+ 	default "0:1" if TI_COMMON_CMD_OPTIONS
+ 	default "0:auto" if ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL
+-	default ":auto" if ARCH_SUNXI
++	default ":auto" if BOARD_SUNXI
+ 	default "0" if ARCH_AT91
+ 	help
+ 	  Define this to a string to specify the partition of the device. It can
+@@ -555,7 +555,7 @@ config ENV_OFFSET
+ 		    ENV_IS_IN_SPI_FLASH
+ 	default 0x3f8000 if ARCH_ROCKCHIP && ENV_IS_IN_MMC
+ 	default 0x140000 if ARCH_ROCKCHIP && ENV_IS_IN_SPI_FLASH
+-	default 0xF0000 if ARCH_SUNXI
++	default 0xF0000 if BOARD_SUNXI
+ 	default 0xE0000 if ARCH_ZYNQ
+ 	default 0x1E00000 if ARCH_ZYNQMP
+ 	default 0x7F40000 if ARCH_VERSAL || ARCH_VERSAL_NET
+@@ -580,7 +580,7 @@ config ENV_SIZE
+ 	hex "Environment Size"
+ 	default 0x40000 if ENV_IS_IN_SPI_FLASH && ARCH_ZYNQMP
+ 	default 0x20000 if ARCH_ZYNQ || ARCH_OMAP2PLUS || ARCH_AT91
+-	default 0x10000 if ARCH_SUNXI
++	default 0x10000 if BOARD_SUNXI
+ 	default 0x8000 if ARCH_ROCKCHIP && ENV_IS_IN_MMC
+ 	default 0x2000 if ARCH_ROCKCHIP && ENV_IS_IN_SPI_FLASH
+ 	default 0x8000 if ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET
+@@ -596,7 +596,7 @@ config ENV_SECT_SIZE
+ 	default 0x40000 if ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET
+ 	default 0x20000 if ARCH_ZYNQ || ARCH_OMAP2PLUS || ARCH_AT91
+ 	default 0x20000 if MICROBLAZE && ENV_IS_IN_SPI_FLASH
+-	default 0x10000 if ARCH_SUNXI && ENV_IS_IN_SPI_FLASH
++	default 0x10000 if BOARD_SUNXI && ENV_IS_IN_SPI_FLASH
+ 	help
+ 	  Size of the sector containing the environment.
+ 
diff --git a/package/boot/uboot-d1/patches/0073-drivers-sunxi-Replace-ARCH_SUNXI-with-BOARD_SUNXI.patch b/package/boot/uboot-d1/patches/0073-drivers-sunxi-Replace-ARCH_SUNXI-with-BOARD_SUNXI.patch
new file mode 100644
index 00000000000000..4e2386304037da
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0073-drivers-sunxi-Replace-ARCH_SUNXI-with-BOARD_SUNXI.patch
@@ -0,0 +1,264 @@
+From 666d3c2bc058268a976397ec3e258f532edcfeb2 Mon Sep 17 00:00:00 2001
+From: Zoltan HERPAI <wigyori@uid0.hu>
+Date: Tue, 6 Jun 2023 18:12:11 +0000
+Subject: [PATCH 73/90] drivers: sunxi: Replace ARCH_SUNXI with BOARD_SUNXI
+
+This provides a unified configuration across all sunxi boards,
+regardless of CPU architecture.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
+---
+ drivers/clk/sunxi/Kconfig     |  2 +-
+ drivers/fastboot/Kconfig      | 13 ++++++-------
+ drivers/gpio/Kconfig          |  2 +-
+ drivers/mmc/Kconfig           |  2 +-
+ drivers/net/phy/Kconfig       |  4 ++--
+ drivers/phy/allwinner/Kconfig |  2 +-
+ drivers/pinctrl/sunxi/Kconfig |  2 +-
+ drivers/reset/Kconfig         |  2 +-
+ drivers/spi/Kconfig           |  2 +-
+ drivers/usb/Kconfig           |  2 +-
+ drivers/usb/gadget/Kconfig    |  8 ++++----
+ drivers/usb/musb-new/Kconfig  |  2 +-
+ drivers/video/Kconfig         |  2 +-
+ drivers/watchdog/Kconfig      |  4 ++--
+ 14 files changed, 24 insertions(+), 25 deletions(-)
+
+--- a/drivers/clk/sunxi/Kconfig
++++ b/drivers/clk/sunxi/Kconfig
+@@ -1,6 +1,6 @@
+ config CLK_SUNXI
+ 	bool "Clock support for Allwinner SoCs"
+-	depends on CLK && ARCH_SUNXI
++	depends on CLK && BOARD_SUNXI
+ 	select DM_RESET
+ 	select SPL_DM_RESET if SPL_CLK
+ 	default y
+--- a/drivers/fastboot/Kconfig
++++ b/drivers/fastboot/Kconfig
+@@ -8,7 +8,7 @@ config FASTBOOT
+ config USB_FUNCTION_FASTBOOT
+ 	bool "Enable USB fastboot gadget"
+ 	depends on USB_GADGET
+-	default y if ARCH_SUNXI && USB_MUSB_GADGET
++	default y if BOARD_SUNXI && USB_MUSB_GADGET
+ 	select FASTBOOT
+ 	select USB_GADGET_DOWNLOAD
+ 	help
+@@ -32,10 +32,9 @@ if FASTBOOT
+ 
+ config FASTBOOT_BUF_ADDR
+ 	hex "Define FASTBOOT buffer address"
++	default SYS_LOAD_ADDR if BOARD_SUNXI
+ 	default 0x82000000 if MX6SX || MX6SL || MX6UL || MX6SLL
+ 	default 0x81000000 if ARCH_OMAP2PLUS
+-	default 0x42000000 if ARCH_SUNXI && !MACH_SUN9I
+-	default 0x22000000 if ARCH_SUNXI && MACH_SUN9I
+ 	default 0x60800800 if ROCKCHIP_RK3036 || ROCKCHIP_RK3188 || \
+ 				ROCKCHIP_RK322X
+ 	default 0x800800 if ROCKCHIP_RK3288 || ROCKCHIP_RK3329 || \
+@@ -52,7 +51,7 @@ config FASTBOOT_BUF_SIZE
+ 	hex "Define FASTBOOT buffer size"
+ 	default 0x8000000 if ARCH_ROCKCHIP
+ 	default 0x6000000 if ARCH_ZYNQMP
+-	default 0x2000000 if ARCH_SUNXI
++	default 0x2000000 if BOARD_SUNXI
+ 	default 0x8192 if SANDBOX
+ 	default 0x7000000
+ 	help
+@@ -71,7 +70,7 @@ config FASTBOOT_USB_DEV
+ 
+ config FASTBOOT_FLASH
+ 	bool "Enable FASTBOOT FLASH command"
+-	default y if ARCH_SUNXI || ARCH_ROCKCHIP
++	default y if BOARD_SUNXI || ARCH_ROCKCHIP
+ 	depends on MMC || (MTD_RAW_NAND && CMD_MTDPARTS)
+ 	select IMAGE_SPARSE
+ 	help
+@@ -105,8 +104,8 @@ config FASTBOOT_FLASH_MMC_DEV
+ 	int "Define FASTBOOT MMC FLASH default device"
+ 	depends on FASTBOOT_FLASH_MMC
+ 	default 0 if ARCH_ROCKCHIP
+-	default 0 if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA = -1
+-	default 1 if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA != -1
++	default 0 if BOARD_SUNXI && MMC_SUNXI_SLOT_EXTRA = -1
++	default 1 if BOARD_SUNXI && MMC_SUNXI_SLOT_EXTRA != -1
+ 	help
+ 	  The fastboot "flash" command requires additional information
+ 	  regarding the non-volatile storage device. Define this to
+--- a/drivers/gpio/Kconfig
++++ b/drivers/gpio/Kconfig
+@@ -370,7 +370,7 @@ config SANDBOX_GPIO_COUNT
+ 
+ config SUNXI_GPIO
+ 	bool "Allwinner GPIO driver"
+-	depends on ARCH_SUNXI
++	depends on BOARD_SUNXI
+ 	select SPL_STRTO if SPL
+ 	help
+ 	  Support the GPIO device in Allwinner SoCs.
+--- a/drivers/mmc/Kconfig
++++ b/drivers/mmc/Kconfig
+@@ -756,7 +756,7 @@ config ZYNQ_HISPD_BROKEN
+ 
+ config MMC_SUNXI
+ 	bool "Allwinner sunxi SD/MMC Host Controller support"
+-	depends on ARCH_SUNXI
++	depends on BOARD_SUNXI
+ 	default y
+ 	help
+ 	  This selects support for the SD/MMC Host Controller on
+--- a/drivers/net/phy/Kconfig
++++ b/drivers/net/phy/Kconfig
+@@ -19,14 +19,14 @@ if PHYLIB
+ 
+ config PHY_ADDR_ENABLE
+ 	bool "Limit phy address"
+-	default y if ARCH_SUNXI
++	default y if BOARD_SUNXI
+ 	help
+ 	  Select this if you want to control which phy address is used
+ 
+ if PHY_ADDR_ENABLE
+ config PHY_ADDR
+ 	int "PHY address"
+-	default 1 if ARCH_SUNXI
++	default 1 if BOARD_SUNXI
+ 	default 0
+ 	help
+ 	  The address of PHY on MII bus. Usually in range of 0 to 31.
+--- a/drivers/phy/allwinner/Kconfig
++++ b/drivers/phy/allwinner/Kconfig
+@@ -3,7 +3,7 @@
+ #
+ config PHY_SUN4I_USB
+ 	bool "Allwinner Sun4I USB PHY driver"
+-	depends on ARCH_SUNXI && !MACH_SUN9I
++	depends on depends on BOARD_SUNXI
+ 	default y
+ 	select DM_REGULATOR
+ 	select PHY
+--- a/drivers/pinctrl/sunxi/Kconfig
++++ b/drivers/pinctrl/sunxi/Kconfig
+@@ -1,6 +1,6 @@
+ # SPDX-License-Identifier: GPL-2.0
+ 
+-if ARCH_SUNXI
++if BOARD_SUNXI
+ 
+ config PINCTRL_SUNXI
+ 	select PINCTRL_FULL
+--- a/drivers/reset/Kconfig
++++ b/drivers/reset/Kconfig
+@@ -137,7 +137,7 @@ config RESET_MTMIPS
+ 
+ config RESET_SUNXI
+ 	bool "RESET support for Allwinner SoCs"
+-	depends on DM_RESET && ARCH_SUNXI
++	depends on DM_RESET && BOARD_SUNXI
+ 	default y
+ 	help
+ 	  This enables support for common reset driver for
+--- a/drivers/spi/Kconfig
++++ b/drivers/spi/Kconfig
+@@ -453,7 +453,7 @@ config SOFT_SPI
+ 
+ config SPI_SUNXI
+ 	bool "Allwinner SoC SPI controllers"
+-	default ARCH_SUNXI
++	default BOARD_SUNXI
+ 	help
+ 	  Enable the Allwinner SoC SPi controller driver.
+ 
+--- a/drivers/usb/Kconfig
++++ b/drivers/usb/Kconfig
+@@ -116,7 +116,7 @@ config USB_KEYBOARD_FN_KEYS
+ 
+ choice
+ 	prompt "USB keyboard polling"
+-	default SYS_USB_EVENT_POLL_VIA_INT_QUEUE if ARCH_SUNXI
++	default SYS_USB_EVENT_POLL_VIA_INT_QUEUE if BOARD_SUNXI
+ 	default SYS_USB_EVENT_POLL
+ 	---help---
+ 	  Enable a polling mechanism for USB keyboard.
+--- a/drivers/usb/gadget/Kconfig
++++ b/drivers/usb/gadget/Kconfig
+@@ -40,7 +40,7 @@ if USB_GADGET
+ 
+ config USB_GADGET_MANUFACTURER
+ 	string "Vendor name of the USB device"
+-	default "Allwinner Technology" if ARCH_SUNXI
++	default "Allwinner Technology" if BOARD_SUNXI
+ 	default "Rockchip" if ARCH_ROCKCHIP
+ 	default "U-Boot"
+ 	help
+@@ -49,7 +49,7 @@ config USB_GADGET_MANUFACTURER
+ 
+ config USB_GADGET_VENDOR_NUM
+ 	hex "Vendor ID of the USB device"
+-	default 0x1f3a if ARCH_SUNXI
++	default 0x1f3a if BOARD_SUNXI
+ 	default 0x2207 if ARCH_ROCKCHIP
+ 	default 0x0
+ 	help
+@@ -59,7 +59,7 @@ config USB_GADGET_VENDOR_NUM
+ 
+ config USB_GADGET_PRODUCT_NUM
+ 	hex "Product ID of the USB device"
+-	default 0x1010 if ARCH_SUNXI
++	default 0x1010 if BOARD_SUNXI
+ 	default 0x310a if ROCKCHIP_RK3036
+ 	default 0x300a if ROCKCHIP_RK3066
+ 	default 0x310c if ROCKCHIP_RK3128
+@@ -202,7 +202,7 @@ endif # USB_GADGET_DOWNLOAD
+ config USB_ETHER
+ 	bool "USB Ethernet Gadget"
+ 	depends on NET
+-	default y if ARCH_SUNXI && USB_MUSB_GADGET
++	default y if BOARD_SUNXI && USB_MUSB_GADGET
+ 	help
+ 	  Creates an Ethernet network device through a USB peripheral
+ 	  controller. This will create a network interface on both the device
+--- a/drivers/usb/musb-new/Kconfig
++++ b/drivers/usb/musb-new/Kconfig
+@@ -67,7 +67,7 @@ config USB_MUSB_PIC32
+ 
+ config USB_MUSB_SUNXI
+ 	bool "Enable sunxi OTG / DRC USB controller"
+-	depends on ARCH_SUNXI
++	depends on BOARD_SUNXI
+ 	select USB_MUSB_PIO_ONLY
+ 	default y
+ 	---help---
+--- a/drivers/video/Kconfig
++++ b/drivers/video/Kconfig
+@@ -183,7 +183,7 @@ config CONSOLE_TRUETYPE_MAX_METRICS
+ 
+ config SYS_WHITE_ON_BLACK
+ 	bool "Display console as white on a black background"
+-	default y if ARCH_AT91 || ARCH_EXYNOS || ARCH_ROCKCHIP || ARCH_TEGRA || X86 || ARCH_SUNXI
++	default y if ARCH_AT91 || ARCH_EXYNOS || ARCH_ROCKCHIP || ARCH_TEGRA || X86 || BOARD_SUNXI
+ 	help
+ 	 Normally the display is black on a white background, Enable this
+ 	 option to invert this, i.e. white on a black background. This can be
+--- a/drivers/watchdog/Kconfig
++++ b/drivers/watchdog/Kconfig
+@@ -29,7 +29,7 @@ config WATCHDOG_TIMEOUT_MSECS
+ 	default 128000 if ARCH_MX31 || ARCH_MX5 || ARCH_MX6
+ 	default 128000 if ARCH_MX7 || ARCH_VF610
+ 	default 30000 if ARCH_SOCFPGA
+-	default 16000 if ARCH_SUNXI
++	default 16000 if BOARD_SUNXI
+ 	default 60000
+ 	help
+ 	  Watchdog timeout in msec
+@@ -321,7 +321,7 @@ config WDT_STM32MP
+ 
+ config WDT_SUNXI
+ 	bool "Allwinner sunxi watchdog timer support"
+-	depends on WDT && ARCH_SUNXI
++	depends on WDT && BOARD_SUNXI
+ 	default y
+ 	help
+ 	  Enable support for the watchdog timer in Allwinner sunxi SoCs.
diff --git a/package/boot/uboot-d1/patches/0074-disk-sunxi-Replace-ARCH_SUNXI-with-BOARD_SUNXI.patch b/package/boot/uboot-d1/patches/0074-disk-sunxi-Replace-ARCH_SUNXI-with-BOARD_SUNXI.patch
new file mode 100644
index 00000000000000..68a3a684e02690
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0074-disk-sunxi-Replace-ARCH_SUNXI-with-BOARD_SUNXI.patch
@@ -0,0 +1,42 @@
+From 98fb93ceb936b375d7f8f2908f0703a93e27fbc4 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 6 Aug 2022 00:05:52 -0500
+Subject: [PATCH 74/90] disk: sunxi: Replace ARCH_SUNXI with BOARD_SUNXI
+
+This provides a unified configuration across all sunxi boards,
+regardless of CPU architecture.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ disk/Kconfig | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+--- a/disk/Kconfig
++++ b/disk/Kconfig
+@@ -61,7 +61,7 @@ config SPL_DOS_PARTITION
+ 	bool "Enable MS Dos partition table for SPL"
+ 	depends on SPL
+ 	default n if ARCH_MVEBU
+-	default n if ARCH_SUNXI
++	default n if BOARD_SUNXI
+ 	default y if DOS_PARTITION
+ 	select SPL_PARTITIONS
+ 
+@@ -104,7 +104,7 @@ config EFI_PARTITION
+ config EFI_PARTITION_ENTRIES_NUMBERS
+ 	int "Number of the EFI partition entries"
+ 	depends on EFI_PARTITION
+-	default 56 if ARCH_SUNXI
++	default 56 if BOARD_SUNXI
+ 	default 128
+ 	help
+ 	  Specify the number of partition entries in the GPT. This is
+@@ -132,7 +132,7 @@ config SPL_EFI_PARTITION
+ 	bool "Enable EFI GPT partition table for SPL"
+ 	depends on  SPL
+ 	default n if ARCH_MVEBU
+-	default n if ARCH_SUNXI
++	default n if BOARD_SUNXI
+ 	default y if EFI_PARTITION
+ 	select SPL_PARTITIONS
+ 
diff --git a/package/boot/uboot-d1/patches/0075-spl-sunxi-Replace-ARCH_SUNXI-with-BOARD_SUNXI.patch b/package/boot/uboot-d1/patches/0075-spl-sunxi-Replace-ARCH_SUNXI-with-BOARD_SUNXI.patch
new file mode 100644
index 00000000000000..81b6b45c7312af
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0075-spl-sunxi-Replace-ARCH_SUNXI-with-BOARD_SUNXI.patch
@@ -0,0 +1,81 @@
+From 7f06dca4df9302a22a8d27af887da50a67b7dd1d Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 6 Aug 2022 00:09:38 -0500
+Subject: [PATCH 75/90] spl: sunxi: Replace ARCH_SUNXI with BOARD_SUNXI
+
+This provides a unified configuration across all sunxi boards,
+regardless of CPU architecture.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ common/spl/Kconfig   | 12 ++++++------
+ scripts/Makefile.spl |  2 +-
+ 2 files changed, 7 insertions(+), 7 deletions(-)
+
+--- a/common/spl/Kconfig
++++ b/common/spl/Kconfig
+@@ -111,7 +111,7 @@ config SPL_PAD_TO
+ config SPL_HAS_BSS_LINKER_SECTION
+ 	depends on SPL_FRAMEWORK
+ 	bool "Use a specific address for the BSS via the linker script"
+-	default y if ARCH_SUNXI || ARCH_MX6 || ARCH_OMAP2PLUS || MIPS || RISCV || ARCH_ZYNQMP
++	default y if ARCH_MX6 || ARCH_OMAP2PLUS || ARCH_ZYNQMP || BOARD_SUNXI || MIPS || RISCV
+ 
+ config SPL_BSS_START_ADDR
+ 	hex "Link address for the BSS within the SPL binary"
+@@ -335,7 +335,7 @@ config SPL_SYS_MALLOC_SIMPLE
+ config SPL_SHARES_INIT_SP_ADDR
+ 	bool "SPL and U-Boot use the same initial stack pointer location"
+ 	depends on (ARM || ARCH_JZ47XX || MICROBLAZE || RISCV) && SPL_FRAMEWORK
+-	default n if ARCH_SUNXI || ARCH_MX6 || ARCH_MX7
++	default n if BOARD_SUNXI || ARCH_MX6 || ARCH_MX7
+ 	default y
+ 	help
+ 	  In many cases, we can use the same initial stack pointer address for
+@@ -453,7 +453,7 @@ config SPL_DISPLAY_PRINT
+ 
+ config SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+ 	bool "MMC raw mode: by sector"
+-	default y if ARCH_SUNXI || ARCH_DAVINCI || ARCH_UNIPHIER || \
++	default y if BOARD_SUNXI || ARCH_DAVINCI || ARCH_UNIPHIER || \
+ 		     ARCH_MX6 || ARCH_MX7 || \
+ 		     ARCH_ROCKCHIP || ARCH_MVEBU ||  ARCH_SOCFPGA || \
+ 		     ARCH_AT91 || ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || \
+@@ -466,7 +466,7 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_USE_SEC
+ config SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
+ 	hex "Address on the MMC to load U-Boot from"
+ 	depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+-	default 0x40 if ARCH_SUNXI
++	default 0x40 if BOARD_SUNXI
+ 	default 0x75 if ARCH_DAVINCI
+ 	default 0x8a if ARCH_MX6 || ARCH_MX7
+ 	default 0x100 if ARCH_UNIPHIER
+@@ -483,7 +483,7 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
+ config SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET
+ 	hex "U-Boot main hardware partition image offset"
+ 	depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+-	default 0x10 if ARCH_SUNXI
++	default 0x10 if BOARD_SUNXI
+ 	default 0x0
+ 	help
+ 	  On some platforms SPL location depends on hardware partition. The ROM
+@@ -1308,7 +1308,7 @@ endif # SPL_SPI_FLASH_SUPPORT
+ 
+ config SYS_SPI_U_BOOT_OFFS
+ 	hex "address of u-boot payload in SPI flash"
+-	default 0x8000 if ARCH_SUNXI
++	default 0x8000 if BOARD_SUNXI
+ 	default 0x0
+ 	depends on SPL_SPI_LOAD || SPL_SPI_SUNXI
+ 	help
+--- a/scripts/Makefile.spl
++++ b/scripts/Makefile.spl
+@@ -264,7 +264,7 @@ endif
+ 
+ INPUTS-$(CONFIG_TARGET_SOCFPGA_SOC64) += $(obj)/u-boot-spl-dtb.hex
+ 
+-ifdef CONFIG_ARCH_SUNXI
++ifdef CONFIG_BOARD_SUNXI
+ INPUTS-y	+= $(obj)/sunxi-spl.bin
+ 
+ ifdef CONFIG_NAND_SUNXI
diff --git a/package/boot/uboot-d1/patches/0076-riscv-cpu-Add-cache-operations-for-T-HEAD-CPUs.patch b/package/boot/uboot-d1/patches/0076-riscv-cpu-Add-cache-operations-for-T-HEAD-CPUs.patch
new file mode 100644
index 00000000000000..0555b6d9b409d8
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0076-riscv-cpu-Add-cache-operations-for-T-HEAD-CPUs.patch
@@ -0,0 +1,153 @@
+From b6da98cd39612bb5660afbcad06e3a6bac43563e Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 11 Sep 2021 23:27:42 -0500
+Subject: [PATCH 76/90] riscv: cpu: Add cache operations for T-HEAD CPUs
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/riscv/cpu/Makefile      |   1 +
+ arch/riscv/cpu/thead/cache.c | 119 +++++++++++++++++++++++++++++++++++
+ arch/riscv/lib/cache.c       |   2 +-
+ 3 files changed, 121 insertions(+), 1 deletion(-)
+ create mode 100644 arch/riscv/cpu/thead/cache.c
+
+--- a/arch/riscv/cpu/Makefile
++++ b/arch/riscv/cpu/Makefile
+@@ -5,3 +5,4 @@
+ extra-y = start.o
+ 
+ obj-y += cpu.o mtrap.o
++obj-y += thead/cache.o
+--- /dev/null
++++ b/arch/riscv/cpu/thead/cache.c
+@@ -0,0 +1,119 @@
++// SPDX-License-Identifier: GPL-2.0+
++
++#include <asm/cache.h>
++#include <asm/csr.h>
++
++#define CSR_MHCR		0x7c1
++#define CSR_MCOR		0x7c2
++#define CSR_MHINT		0x7c5
++
++#define MHCR_IE			BIT(0)	/* icache enable */
++#define MHCR_DE			BIT(1)	/* dcache enable */
++#define MHCR_WA			BIT(2)	/* dcache write allocate */
++#define MHCR_WB			BIT(3)	/* dcache write back */
++#define MHCR_RS			BIT(4)	/* return stack enable */
++#define MHCR_BPE		BIT(5)	/* branch prediction enable */
++#define MHCR_BTB		BIT(6)	/* branch target prediction enable */
++#define MHCR_WBR		BIT(8)	/* write burst enable */
++#define MHCR_L0BTB		BIT(12)
++
++#define MCOR_CACHE_SEL_ICACHE	(0x1 << 0)
++#define MCOR_CACHE_SEL_DCACHE	(0x2 << 0)
++#define MCOR_CACHE_SEL_BOTH	(0x3 << 0)
++#define MCOR_INV		BIT(4)
++#define MCOR_CLR		BIT(5)
++#define MCOR_BHT_INV		BIT(16)
++#define MCOR_BTB_INV		BIT(17)
++
++#define MHINT_DPLD		BIT(2)	/* dcache prefetch enable */
++#define MHINT_AMR_PAGE		(0x0 << 3)
++#define MHINT_AMR_LIMIT_3	(0x1 << 3)
++#define MHINT_AMR_LIMIT_64	(0x2 << 3)
++#define MHINT_AMR_LIMIT_128	(0x3 << 3)
++#define MHINT_IPLD		BIT(8)	/* icache prefetch enable */
++#define MHINT_IWPE		BIT(9)	/* icache prediction enable */
++#define MHINT_DIS_PREFETCH_2	(0x0 << 13)
++#define MHINT_DIS_PREFETCH_4	(0x1 << 13)
++#define MHINT_DIS_PREFETCH_8	(0x2 << 13)
++#define MHINT_DIS_PREFETCH_16	(0x3 << 13)
++
++#define sync_i()		asm volatile (".long 0x01a0000b" ::: "memory")
++
++void flush_dcache_all(void)
++{
++	asm volatile (".long 0x0030000b" ::: "memory"); /* dcache.ciall */
++	sync_i();
++}
++
++void flush_dcache_range(unsigned long start, unsigned long end)
++{
++	register unsigned long i asm("a0") = start & -CONFIG_SYS_CACHELINE_SIZE;
++
++	for (; i < end; i += CONFIG_SYS_CACHELINE_SIZE)
++		asm volatile (".long 0x02b5000b" ::: "memory"); /* dcache.cipa a0 */
++	sync_i();
++}
++
++void invalidate_icache_range(unsigned long start, unsigned long end)
++{
++	register unsigned long i asm("a0") = start & -CONFIG_SYS_CACHELINE_SIZE;
++
++	for (; i < end; i += CONFIG_SYS_CACHELINE_SIZE)
++		asm volatile (".long 0x0385000b" ::: "memory"); /* icache.ipa a0 */
++	sync_i();
++}
++
++void invalidate_dcache_range(unsigned long start, unsigned long end)
++{
++	register unsigned long i asm("a0") = start & -CONFIG_SYS_CACHELINE_SIZE;
++
++	for (; i < end; i += CONFIG_SYS_CACHELINE_SIZE)
++		asm volatile (".long 0x02a5000b" ::: "memory"); /* dcache.ipa a0 */
++	sync_i();
++}
++
++#if 0
++void icache_enable(void)
++{
++	asm volatile (".long 0x0100000b" ::: "memory"); /* icache.iall */
++	sync_i();
++	csr_set(CSR_MHCR, MHCR_IE | MHCR_RS | MHCR_BPE | MHCR_BTB | MHCR_L0BTB);
++	csr_set(CSR_MHINT, MHINT_IPLD | MHINT_IWPE);
++}
++
++void icache_disable(void)
++{
++	csr_clear(CSR_MHCR, MHCR_IE);
++}
++
++int icache_status(void)
++{
++	return csr_read(CSR_MHCR) & MHCR_IE;
++}
++
++void dcache_enable(void)
++{
++	asm volatile (".long 0x0020000b" ::: "memory"); /* dcache.iall */
++	sync_i();
++	csr_set(CSR_MHCR, MHCR_DE | MHCR_WA | MHCR_WB | MHCR_WBR);
++	csr_set(CSR_MHINT, MHINT_DPLD | MHINT_AMR_LIMIT_3);
++}
++
++void dcache_disable(void)
++{
++	asm volatile (".long 0x0010000b" ::: "memory"); /* dcache.call */
++	sync_i();
++	csr_clear(CSR_MHCR, MHCR_DE);
++}
++
++int dcache_status(void)
++{
++	return csr_read(CSR_MHCR) & MHCR_DE;
++}
++
++void enable_caches(void)
++{
++	icache_enable();
++	dcache_enable();
++}
++#endif
+--- a/arch/riscv/lib/cache.c
++++ b/arch/riscv/lib/cache.c
+@@ -20,7 +20,7 @@ __weak void flush_dcache_range(unsigned
+ {
+ }
+ 
+-void invalidate_icache_range(unsigned long start, unsigned long end)
++__weak void invalidate_icache_range(unsigned long start, unsigned long end)
+ {
+ 	/*
+ 	 * RISC-V does not have an instruction for invalidating parts of the
diff --git a/package/boot/uboot-d1/patches/0077-riscv-Sort-target-configs-alphabetically.patch b/package/boot/uboot-d1/patches/0077-riscv-Sort-target-configs-alphabetically.patch
new file mode 100644
index 00000000000000..64577d8bd64424
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0077-riscv-Sort-target-configs-alphabetically.patch
@@ -0,0 +1,43 @@
+From 35da34adec7b5b06ad81455a21c67a9c1152e2c9 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 7 Aug 2021 12:09:35 -0500
+Subject: [PATCH 77/90] riscv: Sort target configs alphabetically
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/riscv/Kconfig | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+--- a/arch/riscv/Kconfig
++++ b/arch/riscv/Kconfig
+@@ -14,6 +14,9 @@ config TARGET_AX25_AE350
+ config TARGET_MICROCHIP_ICICLE
+ 	bool "Support Microchip PolarFire-SoC Icicle Board"
+ 
++config TARGET_OPENPITON_RISCV64
++	bool "Support RISC-V cores on OpenPiton SoC"
++
+ config TARGET_QEMU_VIRT
+ 	bool "Support QEMU Virt Board"
+ 
+@@ -28,9 +31,6 @@ config TARGET_SIPEED_MAIX
+ 	bool "Support Sipeed Maix Board"
+ 	select SYS_CACHE_SHIFT_6
+ 
+-config TARGET_OPENPITON_RISCV64
+-	bool "Support RISC-V cores on OpenPiton SoC"
+-
+ endchoice
+ 
+ config SYS_ICACHE_OFF
+@@ -61,9 +61,9 @@ config SPL_SYS_DCACHE_OFF
+ source "board/AndesTech/ax25-ae350/Kconfig"
+ source "board/emulation/qemu-riscv/Kconfig"
+ source "board/microchip/mpfs_icicle/Kconfig"
++source "board/openpiton/riscv64/Kconfig"
+ source "board/sifive/unleashed/Kconfig"
+ source "board/sifive/unmatched/Kconfig"
+-source "board/openpiton/riscv64/Kconfig"
+ source "board/sipeed/maix/Kconfig"
+ 
+ # platform-specific options below
diff --git a/package/boot/uboot-d1/patches/0078-riscv-Add-Allwinner-D1-devicetrees.patch b/package/boot/uboot-d1/patches/0078-riscv-Add-Allwinner-D1-devicetrees.patch
new file mode 100644
index 00000000000000..09054d7455d934
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0078-riscv-Add-Allwinner-D1-devicetrees.patch
@@ -0,0 +1,2138 @@
+From ce792f7abd4294ebba76f76d9d7aa90c7970de8e Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Thu, 4 Aug 2022 23:35:09 -0500
+Subject: [PATCH 78/90] riscv: Add Allwinner D1 devicetrees
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/riscv/dts/Makefile                       |   9 +
+ .../riscv/dts/sun20i-d1-clockworkpi-v3.14.dts | 242 +++++
+ .../dts/sun20i-d1-common-regulators.dtsi      |  51 +
+ arch/riscv/dts/sun20i-d1-devterm-v3.14.dts    |  37 +
+ .../dts/sun20i-d1-dongshan-nezha-stu.dts      | 114 +++
+ .../dts/sun20i-d1-lichee-rv-86-panel-480p.dts |  29 +
+ .../dts/sun20i-d1-lichee-rv-86-panel-720p.dts |  10 +
+ .../dts/sun20i-d1-lichee-rv-86-panel.dtsi     |  92 ++
+ arch/riscv/dts/sun20i-d1-lichee-rv-dock.dts   |  74 ++
+ arch/riscv/dts/sun20i-d1-lichee-rv.dts        |  84 ++
+ arch/riscv/dts/sun20i-d1-mangopi-mq-pro.dts   | 128 +++
+ arch/riscv/dts/sun20i-d1-nezha.dts            | 171 ++++
+ arch/riscv/dts/sun20i-d1.dtsi                 | 900 ++++++++++++++++++
+ arch/riscv/dts/sunxi-u-boot.dtsi              |  68 ++
+ include/dt-bindings/clock/sun20i-d1-r-ccu.h   |  19 +
+ include/dt-bindings/reset/sun20i-d1-r-ccu.h   |  16 +
+ 16 files changed, 2044 insertions(+)
+ create mode 100644 arch/riscv/dts/sun20i-d1-clockworkpi-v3.14.dts
+ create mode 100644 arch/riscv/dts/sun20i-d1-common-regulators.dtsi
+ create mode 100644 arch/riscv/dts/sun20i-d1-devterm-v3.14.dts
+ create mode 100644 arch/riscv/dts/sun20i-d1-dongshan-nezha-stu.dts
+ create mode 100644 arch/riscv/dts/sun20i-d1-lichee-rv-86-panel-480p.dts
+ create mode 100644 arch/riscv/dts/sun20i-d1-lichee-rv-86-panel-720p.dts
+ create mode 100644 arch/riscv/dts/sun20i-d1-lichee-rv-86-panel.dtsi
+ create mode 100644 arch/riscv/dts/sun20i-d1-lichee-rv-dock.dts
+ create mode 100644 arch/riscv/dts/sun20i-d1-lichee-rv.dts
+ create mode 100644 arch/riscv/dts/sun20i-d1-mangopi-mq-pro.dts
+ create mode 100644 arch/riscv/dts/sun20i-d1-nezha.dts
+ create mode 100644 arch/riscv/dts/sun20i-d1.dtsi
+ create mode 100644 arch/riscv/dts/sunxi-u-boot.dtsi
+ create mode 100644 include/dt-bindings/clock/sun20i-d1-r-ccu.h
+ create mode 100644 include/dt-bindings/reset/sun20i-d1-r-ccu.h
+
+--- a/arch/riscv/dts/Makefile
++++ b/arch/riscv/dts/Makefile
+@@ -7,6 +7,15 @@ dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) +
+ dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
+ dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
+ dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
++dtb-$(CONFIG_TARGET_SUN20I_D1) += sun20i-d1-clockworkpi-v3.14.dtb
++dtb-$(CONFIG_TARGET_SUN20I_D1) += sun20i-d1-devterm-v3.14.dtb
++dtb-$(CONFIG_TARGET_SUN20I_D1) += sun20i-d1-dongshan-nezha-stu.dtb
++dtb-$(CONFIG_TARGET_SUN20I_D1) += sun20i-d1-lichee-rv-86-panel-480p.dtb
++dtb-$(CONFIG_TARGET_SUN20I_D1) += sun20i-d1-lichee-rv-86-panel-720p.dtb
++dtb-$(CONFIG_TARGET_SUN20I_D1) += sun20i-d1-lichee-rv-dock.dtb
++dtb-$(CONFIG_TARGET_SUN20I_D1) += sun20i-d1-lichee-rv.dtb
++dtb-$(CONFIG_TARGET_SUN20I_D1) += sun20i-d1-mangopi-mq-pro.dtb
++dtb-$(CONFIG_TARGET_SUN20I_D1) += sun20i-d1-nezha.dtb
+ 
+ include $(srctree)/scripts/Makefile.dts
+ 
+--- /dev/null
++++ b/arch/riscv/dts/sun20i-d1-clockworkpi-v3.14.dts
+@@ -0,0 +1,242 @@
++// SPDX-License-Identifier: (GPL-2.0+ or MIT)
++// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
++
++/dts-v1/;
++
++#include <dt-bindings/gpio/gpio.h>
++
++#include "sun20i-d1.dtsi"
++#include "sun20i-d1-common-regulators.dtsi"
++
++/ {
++	model = "ClockworkPi v3.14 (R-01)";
++	compatible = "clockwork,r-01-clockworkpi-v3.14", "allwinner,sun20i-d1";
++
++	aliases {
++		ethernet0 = &ap6256;
++		mmc0 = &mmc0;
++		serial0 = &uart0;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	/*
++	 * This regulator is PWM-controlled, but the PWM controller is not
++	 * yet supported, so fix the regulator to its default voltage.
++	 */
++	reg_vdd_cpu: vdd-cpu {
++		compatible = "regulator-fixed";
++		regulator-name = "vdd-cpu";
++		regulator-min-microvolt = <1100000>;
++		regulator-max-microvolt = <1100000>;
++		vin-supply = <&reg_vcc>;
++	};
++
++	wifi_pwrseq: wifi-pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		reset-gpios = <&pio 6 11 GPIO_ACTIVE_LOW>; /* PG11/GPIO3 */
++	};
++};
++
++&cpu0 {
++	cpu-supply = <&reg_vdd_cpu>;
++};
++
++&ehci1 {
++	status = "okay";
++};
++
++&i2c0 {
++	pinctrl-0 = <&i2c0_pb10_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++
++	axp221: pmic@34 {
++		compatible = "x-powers,axp228", "x-powers,axp221";
++		reg = <0x34>;
++		interrupt-parent = <&pio>;
++		interrupts = <4 9 IRQ_TYPE_LEVEL_LOW>; /* PE9/GPIO2 */
++		interrupt-controller;
++		#interrupt-cells = <1>;
++
++		ac_power_supply: ac-power {
++			compatible = "x-powers,axp221-ac-power-supply";
++		};
++
++		axp_adc: adc {
++			compatible = "x-powers,axp221-adc";
++			#io-channel-cells = <1>;
++		};
++
++		battery_power_supply: battery-power {
++			compatible = "x-powers,axp221-battery-power-supply";
++		};
++
++		regulators {
++			x-powers,dcdc-freq = <3000>;
++
++			reg_dcdc1: dcdc1 {
++				regulator-name = "sys-3v3";
++				regulator-always-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++			};
++
++			reg_dcdc3: dcdc3 {
++				regulator-name = "sys-1v8";
++				regulator-always-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++			};
++
++			reg_aldo1: aldo1 {
++				regulator-name = "aud-3v3";
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++			};
++
++			reg_aldo2: aldo2 {
++				regulator-name = "disp-3v3";
++				regulator-always-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++			};
++
++			reg_aldo3: aldo3 {
++				regulator-name = "vdd-wifi";
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++			};
++
++			/* DLDO1 and ELDO1-3 are connected in parallel. */
++			reg_dldo1: dldo1 {
++				regulator-name = "vbat-wifi-a";
++				regulator-always-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++			};
++
++			/* DLDO2-DLDO4 are connected in parallel. */
++			reg_dldo2: dldo2 {
++				regulator-name = "vcc-3v3-ext-a";
++				regulator-always-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++			};
++
++			reg_dldo3: dldo3 {
++				regulator-name = "vcc-3v3-ext-b";
++				regulator-always-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++			};
++
++			reg_dldo4: dldo4 {
++				regulator-name = "vcc-3v3-ext-c";
++				regulator-always-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++			};
++
++			reg_eldo1: eldo1 {
++				regulator-name = "vbat-wifi-b";
++				regulator-always-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++			};
++
++			reg_eldo2: eldo2 {
++				regulator-name = "vbat-wifi-c";
++				regulator-always-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++			};
++
++			reg_eldo3: eldo3 {
++				regulator-name = "vbat-wifi-d";
++				regulator-always-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++			};
++		};
++
++		usb_power_supply: usb-power {
++			compatible = "x-powers,axp221-usb-power-supply";
++			status = "disabled";
++		};
++	};
++};
++
++&mmc0 {
++	broken-cd;
++	bus-width = <4>;
++	disable-wp;
++	vmmc-supply = <&reg_dcdc1>;
++	vqmmc-supply = <&reg_vcc_3v3>;
++	pinctrl-0 = <&mmc0_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
++&mmc1 {
++	bus-width = <4>;
++	mmc-pwrseq = <&wifi_pwrseq>;
++	non-removable;
++	vmmc-supply = <&reg_dldo1>;
++	vqmmc-supply = <&reg_aldo3>;
++	pinctrl-0 = <&mmc1_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++
++	ap6256: wifi@1 {
++		compatible = "brcm,bcm43456-fmac", "brcm,bcm4329-fmac";
++		reg = <1>;
++		interrupt-parent = <&pio>;
++		interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10/GPIO4 */
++		interrupt-names = "host-wake";
++	};
++};
++
++&ohci1 {
++	status = "okay";
++};
++
++&pio {
++	vcc-pg-supply = <&reg_ldoa>;
++};
++
++&uart0 {
++	pinctrl-0 = <&uart0_pb8_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
++&uart1 {
++	uart-has-rtscts;
++	pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++
++	bluetooth {
++		compatible = "brcm,bcm4345c5";
++		interrupt-parent = <&pio>;
++		interrupts = <6 17 IRQ_TYPE_LEVEL_HIGH>; /* PG17/GPIO6 */
++		device-wakeup-gpios = <&pio 6 16 GPIO_ACTIVE_HIGH>; /* PG16/GPIO7 */
++		shutdown-gpios = <&pio 6 18 GPIO_ACTIVE_HIGH>; /* PG18/GPIO5 */
++		max-speed = <1500000>;
++		vbat-supply = <&reg_dldo1>;
++		vddio-supply = <&reg_aldo3>;
++	};
++};
++
++&usb_otg {
++	dr_mode = "peripheral";
++	status = "okay";
++};
++
++&usbphy {
++	usb0_vbus_power-supply = <&ac_power_supply>;
++	status = "okay";
++};
+--- /dev/null
++++ b/arch/riscv/dts/sun20i-d1-common-regulators.dtsi
+@@ -0,0 +1,51 @@
++// SPDX-License-Identifier: (GPL-2.0+ or MIT)
++// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
++
++/ {
++	reg_vcc: vcc {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++	};
++
++	reg_vcc_3v3: vcc-3v3 {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc-3v3";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		vin-supply = <&reg_vcc>;
++	};
++};
++
++&lradc {
++	vref-supply = <&reg_aldo>;
++};
++
++&pio {
++	vcc-pb-supply = <&reg_vcc_3v3>;
++	vcc-pc-supply = <&reg_vcc_3v3>;
++	vcc-pd-supply = <&reg_vcc_3v3>;
++	vcc-pe-supply = <&reg_vcc_3v3>;
++	vcc-pf-supply = <&reg_vcc_3v3>;
++	vcc-pg-supply = <&reg_vcc_3v3>;
++};
++
++&reg_aldo {
++	regulator-min-microvolt = <1800000>;
++	regulator-max-microvolt = <1800000>;
++	vdd33-supply = <&reg_vcc_3v3>;
++};
++
++&reg_hpldo {
++	regulator-min-microvolt = <1800000>;
++	regulator-max-microvolt = <1800000>;
++	hpldoin-supply = <&reg_vcc_3v3>;
++};
++
++&reg_ldoa {
++	regulator-always-on;
++	regulator-min-microvolt = <1800000>;
++	regulator-max-microvolt = <1800000>;
++	ldo-in-supply = <&reg_vcc_3v3>;
++};
+--- /dev/null
++++ b/arch/riscv/dts/sun20i-d1-devterm-v3.14.dts
+@@ -0,0 +1,37 @@
++// SPDX-License-Identifier: (GPL-2.0+ or MIT)
++// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
++
++/dts-v1/;
++
++#include "sun20i-d1-clockworkpi-v3.14.dts"
++
++/ {
++	model = "Clockwork DevTerm (R-01)";
++	compatible = "clockwork,r-01-devterm-v3.14",
++		     "clockwork,r-01-clockworkpi-v3.14",
++		     "allwinner,sun20i-d1";
++
++	fan {
++		compatible = "gpio-fan";
++		gpios = <&pio 3 10 GPIO_ACTIVE_HIGH>; /* PD10/GPIO41 */
++		gpio-fan,speed-map = <0    0>,
++				     <6000 1>;
++		#cooling-cells = <2>;
++	};
++
++	i2c-gpio-0 {
++		compatible = "i2c-gpio";
++		sda-gpios = <&pio 3 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PD14/GPIO44 */
++		scl-gpios = <&pio 3 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PD15/GPIO45 */
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		adc@54 {
++			compatible = "ti,adc101c";
++			reg = <0x54>;
++			interrupt-parent = <&pio>;
++			interrupts = <4 12 IRQ_TYPE_LEVEL_LOW>; /* PE12/GPIO35 */
++			vref-supply = <&reg_dldo2>;
++		};
++	};
++};
+--- /dev/null
++++ b/arch/riscv/dts/sun20i-d1-dongshan-nezha-stu.dts
+@@ -0,0 +1,114 @@
++// SPDX-License-Identifier: (GPL-2.0+ or MIT)
++// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
++
++/dts-v1/;
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/leds/common.h>
++
++#include "sun20i-d1.dtsi"
++#include "sun20i-d1-common-regulators.dtsi"
++
++/ {
++	model = "Dongshan Nezha STU";
++	compatible = "100ask,dongshan-nezha-stu", "allwinner,sun20i-d1";
++
++	aliases {
++		ethernet0 = &emac;
++		mmc0 = &mmc0;
++		serial0 = &uart0;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		led-0 {
++			color = <LED_COLOR_ID_GREEN>;
++			function = LED_FUNCTION_STATUS;
++			gpios = <&pio 2 1 GPIO_ACTIVE_HIGH>; /* PC1 */
++		};
++	};
++
++	reg_usbvbus: usbvbus {
++		compatible = "regulator-fixed";
++		regulator-name = "usbvbus";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		gpio = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */
++		enable-active-high;
++		vin-supply = <&reg_vcc>;
++	};
++
++	/*
++	 * This regulator is PWM-controlled, but the PWM controller is not
++	 * yet supported, so fix the regulator to its default voltage.
++	 */
++	reg_vdd_cpu: vdd-cpu {
++		compatible = "regulator-fixed";
++		regulator-name = "vdd-cpu";
++		regulator-min-microvolt = <1100000>;
++		regulator-max-microvolt = <1100000>;
++		vin-supply = <&reg_vcc>;
++	};
++};
++
++&cpu0 {
++	cpu-supply = <&reg_vdd_cpu>;
++};
++
++&ehci0 {
++	status = "okay";
++};
++
++&emac {
++	pinctrl-0 = <&rgmii_pe_pins>;
++	pinctrl-names = "default";
++	phy-handle = <&ext_rgmii_phy>;
++	phy-mode = "rgmii-id";
++	phy-supply = <&reg_vcc_3v3>;
++	status = "okay";
++};
++
++&mdio {
++	ext_rgmii_phy: ethernet-phy@1 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <1>;
++	};
++};
++
++&mmc0 {
++	broken-cd;
++	bus-width = <4>;
++	disable-wp;
++	vmmc-supply = <&reg_vcc_3v3>;
++	vqmmc-supply = <&reg_vcc_3v3>;
++	pinctrl-0 = <&mmc0_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
++&ohci0 {
++	status = "okay";
++};
++
++&uart0 {
++	pinctrl-0 = <&uart0_pb8_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
++&usb_otg {
++	dr_mode = "otg";
++	status = "okay";
++};
++
++&usbphy {
++	usb0_id_det-gpios = <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21 */
++	usb0_vbus_det-gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */
++	usb0_vbus-supply = <&reg_usbvbus>;
++	status = "okay";
++};
+--- /dev/null
++++ b/arch/riscv/dts/sun20i-d1-lichee-rv-86-panel-480p.dts
+@@ -0,0 +1,29 @@
++// SPDX-License-Identifier: (GPL-2.0+ or MIT)
++// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
++
++#include "sun20i-d1-lichee-rv-86-panel.dtsi"
++
++/ {
++	model = "Sipeed Lichee RV 86 Panel (480p)";
++	compatible = "sipeed,lichee-rv-86-panel-480p", "sipeed,lichee-rv",
++		     "allwinner,sun20i-d1";
++};
++
++&i2c2 {
++	pinctrl-0 = <&i2c2_pb0_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++
++	touchscreen@48 {
++		compatible = "focaltech,ft6236";
++		reg = <0x48>;
++		interrupt-parent = <&pio>;
++		interrupts = <6 14 IRQ_TYPE_LEVEL_LOW>; /* PG14 */
++		iovcc-supply = <&reg_vcc_3v3>;
++		reset-gpios = <&pio 6 15 GPIO_ACTIVE_LOW>; /* PG15 */
++		touchscreen-size-x = <480>;
++		touchscreen-size-y = <480>;
++		vcc-supply = <&reg_vcc_3v3>;
++		wakeup-source;
++	};
++};
+--- /dev/null
++++ b/arch/riscv/dts/sun20i-d1-lichee-rv-86-panel-720p.dts
+@@ -0,0 +1,10 @@
++// SPDX-License-Identifier: (GPL-2.0+ or MIT)
++// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
++
++#include "sun20i-d1-lichee-rv-86-panel.dtsi"
++
++/ {
++	model = "Sipeed Lichee RV 86 Panel (720p)";
++	compatible = "sipeed,lichee-rv-86-panel-720p", "sipeed,lichee-rv",
++		     "allwinner,sun20i-d1";
++};
+--- /dev/null
++++ b/arch/riscv/dts/sun20i-d1-lichee-rv-86-panel.dtsi
+@@ -0,0 +1,92 @@
++// SPDX-License-Identifier: (GPL-2.0+ or MIT)
++// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
++
++#include "sun20i-d1-lichee-rv.dts"
++
++/ {
++	aliases {
++		ethernet0 = &emac;
++		ethernet1 = &xr829;
++	};
++
++	/* PC1 is repurposed as BT_WAKE_AP */
++	/delete-node/ leds;
++
++	wifi_pwrseq: wifi-pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		clocks = <&ccu CLK_FANOUT1>;
++		clock-names = "ext_clock";
++		reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
++		assigned-clocks = <&ccu CLK_FANOUT1>;
++		assigned-clock-rates = <32768>;
++		pinctrl-0 = <&clk_pg11_pin>;
++		pinctrl-names = "default";
++	};
++};
++
++&ehci1 {
++	status = "okay";
++};
++
++&emac {
++	pinctrl-0 = <&rmii_pe_pins>;
++	pinctrl-names = "default";
++	phy-handle = <&ext_rmii_phy>;
++	phy-mode = "rmii";
++	phy-supply = <&reg_vcc_3v3>;
++	status = "okay";
++};
++
++&mdio {
++	ext_rmii_phy: ethernet-phy@1 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <1>;
++		reset-gpios = <&pio 4 16 GPIO_ACTIVE_LOW>; /* PE16 */
++	};
++};
++
++&mmc1 {
++	bus-width = <4>;
++	mmc-pwrseq = <&wifi_pwrseq>;
++	non-removable;
++	vmmc-supply = <&reg_vcc_3v3>;
++	vqmmc-supply = <&reg_vcc_3v3>;
++	pinctrl-0 = <&mmc1_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++
++	xr829: wifi@1 {
++		reg = <1>;
++	};
++};
++
++&ohci1 {
++	status = "okay";
++};
++
++&pio {
++	clk_pg11_pin: clk-pg11-pin {
++		pins = "PG11";
++		function = "clk";
++	};
++};
++
++&uart1 {
++	uart-has-rtscts;
++	pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++
++	/* XR829 bluetooth is connected here */
++};
++
++&usb_otg {
++	status = "disabled";
++};
++
++&usbphy {
++	/* PD20 and PD21 are repurposed for the LCD panel */
++	/delete-property/ usb0_id_det-gpios;
++	/delete-property/ usb0_vbus_det-gpios;
++	usb1_vbus-supply = <&reg_vcc>;
++};
+--- /dev/null
++++ b/arch/riscv/dts/sun20i-d1-lichee-rv-dock.dts
+@@ -0,0 +1,74 @@
++// SPDX-License-Identifier: (GPL-2.0+ or MIT)
++// Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org>
++// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
++
++#include <dt-bindings/input/input.h>
++
++#include "sun20i-d1-lichee-rv.dts"
++
++/ {
++	model = "Sipeed Lichee RV Dock";
++	compatible = "sipeed,lichee-rv-dock", "sipeed,lichee-rv",
++		     "allwinner,sun20i-d1";
++
++	aliases {
++		ethernet1 = &rtl8723ds;
++	};
++
++	wifi_pwrseq: wifi-pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
++	};
++};
++
++&ehci1 {
++	status = "okay";
++};
++
++&lradc {
++	status = "okay";
++
++	button-220 {
++		label = "OK";
++		linux,code = <KEY_OK>;
++		channel = <0>;
++		voltage = <220000>;
++	};
++};
++
++&mmc1 {
++	bus-width = <4>;
++	mmc-pwrseq = <&wifi_pwrseq>;
++	non-removable;
++	vmmc-supply = <&reg_vcc_3v3>;
++	vqmmc-supply = <&reg_vcc_3v3>;
++	pinctrl-0 = <&mmc1_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++
++	rtl8723ds: wifi@1 {
++		reg = <1>;
++	};
++};
++
++&ohci1 {
++	status = "okay";
++};
++
++&uart1 {
++	uart-has-rtscts;
++	pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++
++	bluetooth {
++		compatible = "realtek,rtl8723ds-bt";
++		device-wake-gpios = <&pio 6 15 GPIO_ACTIVE_HIGH>; /* PG16 */
++		enable-gpios = <&pio 6 18 GPIO_ACTIVE_HIGH>; /* PG18 */
++		host-wake-gpios = <&pio 6 17 GPIO_ACTIVE_HIGH>; /* PG17 */
++	};
++};
++
++&usbphy {
++	usb1_vbus-supply = <&reg_vcc>;
++};
+--- /dev/null
++++ b/arch/riscv/dts/sun20i-d1-lichee-rv.dts
+@@ -0,0 +1,84 @@
++// SPDX-License-Identifier: (GPL-2.0+ or MIT)
++// Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org>
++// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
++
++/dts-v1/;
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/leds/common.h>
++
++#include "sun20i-d1.dtsi"
++#include "sun20i-d1-common-regulators.dtsi"
++
++/ {
++	model = "Sipeed Lichee RV";
++	compatible = "sipeed,lichee-rv", "allwinner,sun20i-d1";
++
++	aliases {
++		mmc0 = &mmc0;
++		serial0 = &uart0;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		led-0 {
++			color = <LED_COLOR_ID_GREEN>;
++			function = LED_FUNCTION_STATUS;
++			gpios = <&pio 2 1 GPIO_ACTIVE_HIGH>; /* PC1 */
++		};
++	};
++
++	reg_vdd_cpu: vdd-cpu {
++		compatible = "regulator-fixed";
++		regulator-name = "vdd-cpu";
++		regulator-min-microvolt = <900000>;
++		regulator-max-microvolt = <900000>;
++		vin-supply = <&reg_vcc>;
++	};
++};
++
++&cpu0 {
++	cpu-supply = <&reg_vdd_cpu>;
++};
++
++&ehci0 {
++	status = "okay";
++};
++
++&mmc0 {
++	broken-cd;
++	bus-width = <4>;
++	disable-wp;
++	vmmc-supply = <&reg_vcc_3v3>;
++	vqmmc-supply = <&reg_vcc_3v3>;
++	pinctrl-0 = <&mmc0_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
++&ohci0 {
++	status = "okay";
++};
++
++&uart0 {
++	pinctrl-0 = <&uart0_pb8_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
++&usb_otg {
++	dr_mode = "otg";
++	status = "okay";
++};
++
++&usbphy {
++	usb0_id_det-gpios = <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21 */
++	usb0_vbus_det-gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */
++	usb0_vbus-supply = <&reg_vcc>;
++	status = "okay";
++};
+--- /dev/null
++++ b/arch/riscv/dts/sun20i-d1-mangopi-mq-pro.dts
+@@ -0,0 +1,128 @@
++// SPDX-License-Identifier: (GPL-2.0+ or MIT)
++// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
++
++/dts-v1/;
++
++#include <dt-bindings/gpio/gpio.h>
++
++#include "sun20i-d1.dtsi"
++#include "sun20i-d1-common-regulators.dtsi"
++
++/ {
++	model = "MangoPi MQ Pro";
++	compatible = "widora,mangopi-mq-pro", "allwinner,sun20i-d1";
++
++	aliases {
++		ethernet0 = &rtl8723ds;
++		mmc0 = &mmc0;
++		serial0 = &uart0;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	reg_avdd2v8: avdd2v8 {
++		compatible = "regulator-fixed";
++		regulator-name = "avdd2v8";
++		regulator-min-microvolt = <2800000>;
++		regulator-max-microvolt = <2800000>;
++		vin-supply = <&reg_vcc_3v3>;
++	};
++
++	reg_dvdd: dvdd {
++		compatible = "regulator-fixed";
++		regulator-name = "dvdd";
++		regulator-min-microvolt = <1200000>;
++		regulator-max-microvolt = <1200000>;
++		vin-supply = <&reg_vcc_3v3>;
++	};
++
++	reg_vdd_cpu: vdd-cpu {
++		compatible = "regulator-fixed";
++		regulator-name = "vdd-cpu";
++		regulator-min-microvolt = <1100000>;
++		regulator-max-microvolt = <1100000>;
++		vin-supply = <&reg_vcc>;
++	};
++
++	wifi_pwrseq: wifi-pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		reset-gpios = <&pio 6 17 GPIO_ACTIVE_LOW>; /* PG17 */
++	};
++};
++
++&cpu0 {
++	cpu-supply = <&reg_vdd_cpu>;
++};
++
++&ehci1 {
++	status = "okay";
++};
++
++&mmc0 {
++	bus-width = <4>;
++	cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
++	disable-wp;
++	vmmc-supply = <&reg_vcc_3v3>;
++	vqmmc-supply = <&reg_vcc_3v3>;
++	pinctrl-0 = <&mmc0_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
++&mmc1 {
++	bus-width = <4>;
++	mmc-pwrseq = <&wifi_pwrseq>;
++	non-removable;
++	vmmc-supply = <&reg_vcc_3v3>;
++	vqmmc-supply = <&reg_vcc_3v3>;
++	pinctrl-0 = <&mmc1_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++
++	rtl8723ds: wifi@1 {
++		reg = <1>;
++		interrupt-parent = <&pio>;
++		interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 */
++		interrupt-names = "host-wake";
++	};
++};
++
++&ohci1 {
++	status = "okay";
++};
++
++&pio {
++	vcc-pe-supply = <&reg_avdd2v8>;
++};
++
++&uart0 {
++	pinctrl-0 = <&uart0_pb8_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
++&uart1 {
++	uart-has-rtscts;
++	pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++
++	bluetooth {
++		compatible = "realtek,rtl8723ds-bt";
++		device-wake-gpios = <&pio 6 18 GPIO_ACTIVE_HIGH>; /* PG18 */
++		enable-gpios = <&pio 6 15 GPIO_ACTIVE_HIGH>; /* PG15 */
++		host-wake-gpios = <&pio 6 14 GPIO_ACTIVE_HIGH>; /* PG14 */
++	};
++};
++
++&usb_otg {
++	dr_mode = "peripheral";
++	status = "okay";
++};
++
++&usbphy {
++	usb0_vbus-supply = <&reg_vcc>;
++	status = "okay";
++};
+--- /dev/null
++++ b/arch/riscv/dts/sun20i-d1-nezha.dts
+@@ -0,0 +1,171 @@
++// SPDX-License-Identifier: (GPL-2.0+ or MIT)
++// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
++
++/dts-v1/;
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
++
++#include "sun20i-d1.dtsi"
++#include "sun20i-d1-common-regulators.dtsi"
++
++/ {
++	model = "Allwinner D1 Nezha";
++	compatible = "allwinner,d1-nezha", "allwinner,sun20i-d1";
++
++	aliases {
++		ethernet0 = &emac;
++		ethernet1 = &xr829;
++		mmc0 = &mmc0;
++		serial0 = &uart0;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	reg_usbvbus: usbvbus {
++		compatible = "regulator-fixed";
++		regulator-name = "usbvbus";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		gpio = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */
++		enable-active-high;
++		vin-supply = <&reg_vcc>;
++	};
++
++	/*
++	 * This regulator is PWM-controlled, but the PWM controller is not
++	 * yet supported, so fix the regulator to its default voltage.
++	 */
++	reg_vdd_cpu: vdd-cpu {
++		compatible = "regulator-fixed";
++		regulator-name = "vdd-cpu";
++		regulator-min-microvolt = <1100000>;
++		regulator-max-microvolt = <1100000>;
++		vin-supply = <&reg_vcc>;
++	};
++
++	wifi_pwrseq: wifi-pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
++	};
++};
++
++&cpu0 {
++	cpu-supply = <&reg_vdd_cpu>;
++};
++
++&ehci0 {
++	status = "okay";
++};
++
++&ehci1 {
++	status = "okay";
++};
++
++&emac {
++	pinctrl-0 = <&rgmii_pe_pins>;
++	pinctrl-names = "default";
++	phy-handle = <&ext_rgmii_phy>;
++	phy-mode = "rgmii-id";
++	phy-supply = <&reg_vcc_3v3>;
++	status = "okay";
++};
++
++&i2c2 {
++	pinctrl-0 = <&i2c2_pb0_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++
++	pcf8574a: gpio@38 {
++		compatible = "nxp,pcf8574a";
++		reg = <0x38>;
++		interrupt-parent = <&pio>;
++		interrupts = <1 2 IRQ_TYPE_LEVEL_LOW>; /* PB2 */
++		interrupt-controller;
++		gpio-controller;
++		#gpio-cells = <2>;
++		#interrupt-cells = <2>;
++	};
++};
++
++&lradc {
++	status = "okay";
++
++	button-160 {
++		label = "OK";
++		linux,code = <KEY_OK>;
++		channel = <0>;
++		voltage = <160000>;
++	};
++};
++
++&mdio {
++	ext_rgmii_phy: ethernet-phy@1 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <1>;
++	};
++};
++
++&mmc0 {
++	bus-width = <4>;
++	cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
++	disable-wp;
++	vmmc-supply = <&reg_vcc_3v3>;
++	vqmmc-supply = <&reg_vcc_3v3>;
++	pinctrl-0 = <&mmc0_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
++&mmc1 {
++	bus-width = <4>;
++	mmc-pwrseq = <&wifi_pwrseq>;
++	non-removable;
++	vmmc-supply = <&reg_vcc_3v3>;
++	vqmmc-supply = <&reg_vcc_3v3>;
++	pinctrl-0 = <&mmc1_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++
++	xr829: wifi@1 {
++		reg = <1>;
++	};
++};
++
++&ohci0 {
++	status = "okay";
++};
++
++&ohci1 {
++	status = "okay";
++};
++
++&uart0 {
++	pinctrl-0 = <&uart0_pb8_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
++&uart1 {
++	uart-has-rtscts;
++	pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++
++	/* XR829 bluetooth is connected here */
++};
++
++&usb_otg {
++	dr_mode = "otg";
++	status = "okay";
++};
++
++&usbphy {
++	usb0_id_det-gpios = <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21 */
++	usb0_vbus_det-gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */
++	usb0_vbus-supply = <&reg_usbvbus>;
++	usb1_vbus-supply = <&reg_vcc>;
++	status = "okay";
++};
+--- /dev/null
++++ b/arch/riscv/dts/sun20i-d1.dtsi
+@@ -0,0 +1,900 @@
++// SPDX-License-Identifier: (GPL-2.0+ or MIT)
++// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
++
++#include <dt-bindings/clock/sun6i-rtc.h>
++#include <dt-bindings/clock/sun8i-de2.h>
++#include <dt-bindings/clock/sun8i-tcon-top.h>
++#include <dt-bindings/clock/sun20i-d1-ccu.h>
++#include <dt-bindings/clock/sun20i-d1-r-ccu.h>
++#include <dt-bindings/interrupt-controller/irq.h>
++#include <dt-bindings/reset/sun8i-de2.h>
++#include <dt-bindings/reset/sun20i-d1-ccu.h>
++#include <dt-bindings/reset/sun20i-d1-r-ccu.h>
++#include <dt-bindings/thermal/thermal.h>
++
++/ {
++	#address-cells = <1>;
++	#size-cells = <1>;
++
++	cpus {
++		timebase-frequency = <24000000>;
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		cpu0: cpu@0 {
++			compatible = "thead,c906", "riscv";
++			device_type = "cpu";
++			reg = <0>;
++			clocks = <&ccu CLK_RISCV>;
++			clock-frequency = <24000000>;
++			d-cache-block-size = <64>;
++			d-cache-sets = <256>;
++			d-cache-size = <32768>;
++			i-cache-block-size = <64>;
++			i-cache-sets = <128>;
++			i-cache-size = <32768>;
++			mmu-type = "riscv,sv39";
++			riscv,isa = "rv64imafdc";
++			#cooling-cells = <2>;
++
++			cpu0_intc: interrupt-controller {
++				compatible = "riscv,cpu-intc";
++				interrupt-controller;
++				#address-cells = <0>;
++				#interrupt-cells = <1>;
++			};
++		};
++	};
++
++	de: display-engine {
++		compatible = "allwinner,sun20i-d1-display-engine";
++		allwinner,pipelines = <&mixer0>, <&mixer1>;
++		status = "disabled";
++	};
++
++	osc24M: osc24M-clk {
++		compatible = "fixed-clock";
++		clock-frequency = <24000000>;
++		clock-output-names = "osc24M";
++		#clock-cells = <0>;
++	};
++
++	soc {
++		compatible = "simple-bus";
++		ranges;
++		interrupt-parent = <&plic>;
++		dma-noncoherent;
++		#address-cells = <1>;
++		#size-cells = <1>;
++
++		dsp_wdt: watchdog@1700400 {
++			compatible = "allwinner,sun20i-d1-wdt";
++			reg = <0x1700400 0x20>;
++			interrupts = <138 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&osc24M>, <&rtc CLK_OSC32K>;
++			clock-names = "hosc", "losc";
++			status = "reserved";
++		};
++
++		pio: pinctrl@2000000 {
++			compatible = "allwinner,sun20i-d1-pinctrl";
++			reg = <0x2000000 0x800>;
++			interrupts = <85 IRQ_TYPE_LEVEL_HIGH>,
++				     <87 IRQ_TYPE_LEVEL_HIGH>,
++				     <89 IRQ_TYPE_LEVEL_HIGH>,
++				     <91 IRQ_TYPE_LEVEL_HIGH>,
++				     <93 IRQ_TYPE_LEVEL_HIGH>,
++				     <95 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_APB0>,
++				 <&osc24M>,
++				 <&rtc CLK_OSC32K>;
++			clock-names = "apb", "hosc", "losc";
++			gpio-controller;
++			interrupt-controller;
++			#gpio-cells = <3>;
++			#interrupt-cells = <3>;
++
++			/omit-if-no-ref/
++			i2c0_pb10_pins: i2c0-pb10-pins {
++				pins = "PB10", "PB11";
++				function = "i2c0";
++			};
++
++			/omit-if-no-ref/
++			i2c2_pb0_pins: i2c2-pb0-pins {
++				pins = "PB0", "PB1";
++				function = "i2c2";
++			};
++
++			/omit-if-no-ref/
++			lcd_rgb666_pins: lcd-rgb666-pins {
++				pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
++				       "PD6", "PD7", "PD8", "PD9", "PD10", "PD11",
++				       "PD12", "PD13", "PD14", "PD15", "PD16", "PD17",
++				       "PD18", "PD19", "PD20", "PD21";
++				function = "lcd0";
++			};
++
++			/omit-if-no-ref/
++			mmc0_pins: mmc0-pins {
++				pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
++				function = "mmc0";
++			};
++
++			/omit-if-no-ref/
++			mmc1_pins: mmc1-pins {
++				pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5";
++				function = "mmc1";
++			};
++
++			/omit-if-no-ref/
++			mmc2_pins: mmc2-pins {
++				pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7";
++				function = "mmc2";
++			};
++
++			/omit-if-no-ref/
++			rgmii_pe_pins: rgmii-pe-pins {
++				pins = "PE0", "PE1", "PE2", "PE3", "PE4",
++				       "PE5", "PE6", "PE7", "PE8", "PE9",
++				       "PE11", "PE12", "PE13", "PE14", "PE15";
++				function = "emac";
++			};
++
++			/omit-if-no-ref/
++			rmii_pe_pins: rmii-pe-pins {
++				pins = "PE0", "PE1", "PE2", "PE3", "PE4",
++				       "PE5", "PE6", "PE7", "PE8", "PE9";
++				function = "emac";
++			};
++
++			/omit-if-no-ref/
++			uart0_pb8_pins: uart0-pb8-pins {
++				pins = "PB8", "PB9";
++				function = "uart0";
++			};
++
++			/omit-if-no-ref/
++			uart1_pg6_pins: uart1-pg6-pins {
++				pins = "PG6", "PG7";
++				function = "uart1";
++			};
++
++			/omit-if-no-ref/
++			uart1_pg8_rts_cts_pins: uart1-pg8-rts-cts-pins {
++				pins = "PG8", "PG9";
++				function = "uart1";
++			};
++		};
++
++		ccu: clock-controller@2001000 {
++			compatible = "allwinner,sun20i-d1-ccu";
++			reg = <0x2001000 0x1000>;
++			clocks = <&osc24M>,
++				 <&rtc CLK_OSC32K>,
++				 <&rtc CLK_IOSC>;
++			clock-names = "hosc", "losc", "iosc";
++			#clock-cells = <1>;
++			#reset-cells = <1>;
++		};
++
++		lradc: keys@2009800 {
++			compatible = "allwinner,sun20i-d1-lradc",
++				     "allwinner,sun50i-r329-lradc";
++			reg = <0x2009800 0x400>;
++			interrupts = <77 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_LRADC>;
++			resets = <&ccu RST_BUS_LRADC>;
++			status = "disabled";
++		};
++
++		codec: audio-codec@2030000 {
++			compatible = "simple-mfd", "syscon";
++			reg = <0x2030000 0x1000>;
++			#address-cells = <1>;
++			#size-cells = <1>;
++
++			regulators@2030348 {
++				compatible = "allwinner,sun20i-d1-analog-ldos";
++				reg = <0x2030348 0x4>;
++				nvmem-cells = <&bg_trim>;
++				nvmem-cell-names = "bg_trim";
++
++				reg_aldo: aldo {
++				};
++
++				reg_hpldo: hpldo {
++				};
++			};
++		};
++
++		i2s0: i2s@2032000 {
++			compatible = "allwinner,sun20i-d1-i2s",
++				     "allwinner,sun50i-r329-i2s";
++			reg = <0x2032000 0x1000>;
++			interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_I2S0>,
++				 <&ccu CLK_I2S0>;
++			clock-names = "apb", "mod";
++			resets = <&ccu RST_BUS_I2S0>;
++			dmas = <&dma 3>, <&dma 3>;
++			dma-names = "rx", "tx";
++			status = "disabled";
++			#sound-dai-cells = <0>;
++		};
++
++		i2s1: i2s@2033000 {
++			compatible = "allwinner,sun20i-d1-i2s",
++				     "allwinner,sun50i-r329-i2s";
++			reg = <0x2033000 0x1000>;
++			interrupts = <43 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_I2S1>,
++				 <&ccu CLK_I2S1>;
++			clock-names = "apb", "mod";
++			resets = <&ccu RST_BUS_I2S1>;
++			dmas = <&dma 4>, <&dma 4>;
++			dma-names = "rx", "tx";
++			status = "disabled";
++			#sound-dai-cells = <0>;
++		};
++
++		i2s2: i2s@2034000 {
++			compatible = "allwinner,sun20i-d1-i2s",
++				     "allwinner,sun50i-r329-i2s";
++			reg = <0x2034000 0x1000>;
++			interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_I2S2>,
++				 <&ccu CLK_I2S2>;
++			clock-names = "apb", "mod";
++			resets = <&ccu RST_BUS_I2S2>;
++			dmas = <&dma 5>, <&dma 5>;
++			dma-names = "rx", "tx";
++			status = "disabled";
++			#sound-dai-cells = <0>;
++		};
++
++		timer: timer@2050000 {
++			compatible = "allwinner,sun20i-d1-timer",
++				     "allwinner,sun8i-a23-timer";
++			reg = <0x2050000 0xa0>;
++			interrupts = <75 IRQ_TYPE_LEVEL_HIGH>,
++				     <76 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&osc24M>;
++		};
++
++		wdt: watchdog@20500a0 {
++			compatible = "allwinner,sun20i-d1-wdt-reset",
++				     "allwinner,sun20i-d1-wdt";
++			reg = <0x20500a0 0x20>;
++			interrupts = <79 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&osc24M>, <&rtc CLK_OSC32K>;
++			clock-names = "hosc", "losc";
++			status = "reserved";
++		};
++
++		uart0: serial@2500000 {
++			compatible = "snps,dw-apb-uart";
++			reg = <0x2500000 0x400>;
++			reg-io-width = <4>;
++			reg-shift = <2>;
++			interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_UART0>;
++			resets = <&ccu RST_BUS_UART0>;
++			dmas = <&dma 14>, <&dma 14>;
++			dma-names = "rx", "tx";
++			status = "disabled";
++		};
++
++		uart1: serial@2500400 {
++			compatible = "snps,dw-apb-uart";
++			reg = <0x2500400 0x400>;
++			reg-io-width = <4>;
++			reg-shift = <2>;
++			interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_UART1>;
++			resets = <&ccu RST_BUS_UART1>;
++			dmas = <&dma 15>, <&dma 15>;
++			dma-names = "rx", "tx";
++			status = "disabled";
++		};
++
++		uart2: serial@2500800 {
++			compatible = "snps,dw-apb-uart";
++			reg = <0x2500800 0x400>;
++			reg-io-width = <4>;
++			reg-shift = <2>;
++			interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_UART2>;
++			resets = <&ccu RST_BUS_UART2>;
++			dmas = <&dma 16>, <&dma 16>;
++			dma-names = "rx", "tx";
++			status = "disabled";
++		};
++
++		uart3: serial@2500c00 {
++			compatible = "snps,dw-apb-uart";
++			reg = <0x2500c00 0x400>;
++			reg-io-width = <4>;
++			reg-shift = <2>;
++			interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_UART3>;
++			resets = <&ccu RST_BUS_UART3>;
++			dmas = <&dma 17>, <&dma 17>;
++			dma-names = "rx", "tx";
++			status = "disabled";
++		};
++
++		uart4: serial@2501000 {
++			compatible = "snps,dw-apb-uart";
++			reg = <0x2501000 0x400>;
++			reg-io-width = <4>;
++			reg-shift = <2>;
++			interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_UART4>;
++			resets = <&ccu RST_BUS_UART4>;
++			dmas = <&dma 18>, <&dma 18>;
++			dma-names = "rx", "tx";
++			status = "disabled";
++		};
++
++		uart5: serial@2501400 {
++			compatible = "snps,dw-apb-uart";
++			reg = <0x2501400 0x400>;
++			reg-io-width = <4>;
++			reg-shift = <2>;
++			interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_UART5>;
++			resets = <&ccu RST_BUS_UART5>;
++			dmas = <&dma 19>, <&dma 19>;
++			dma-names = "rx", "tx";
++			status = "disabled";
++		};
++
++		i2c0: i2c@2502000 {
++			compatible = "allwinner,sun20i-d1-i2c",
++				     "allwinner,sun8i-v536-i2c",
++				     "allwinner,sun6i-a31-i2c";
++			reg = <0x2502000 0x400>;
++			interrupts = <25 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_I2C0>;
++			resets = <&ccu RST_BUS_I2C0>;
++			dmas = <&dma 43>, <&dma 43>;
++			dma-names = "rx", "tx";
++			status = "disabled";
++			#address-cells = <1>;
++			#size-cells = <0>;
++		};
++
++		i2c1: i2c@2502400 {
++			compatible = "allwinner,sun20i-d1-i2c",
++				     "allwinner,sun8i-v536-i2c",
++				     "allwinner,sun6i-a31-i2c";
++			reg = <0x2502400 0x400>;
++			interrupts = <26 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_I2C1>;
++			resets = <&ccu RST_BUS_I2C1>;
++			dmas = <&dma 44>, <&dma 44>;
++			dma-names = "rx", "tx";
++			status = "disabled";
++			#address-cells = <1>;
++			#size-cells = <0>;
++		};
++
++		i2c2: i2c@2502800 {
++			compatible = "allwinner,sun20i-d1-i2c",
++				     "allwinner,sun8i-v536-i2c",
++				     "allwinner,sun6i-a31-i2c";
++			reg = <0x2502800 0x400>;
++			interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_I2C2>;
++			resets = <&ccu RST_BUS_I2C2>;
++			dmas = <&dma 45>, <&dma 45>;
++			dma-names = "rx", "tx";
++			status = "disabled";
++			#address-cells = <1>;
++			#size-cells = <0>;
++		};
++
++		i2c3: i2c@2502c00 {
++			compatible = "allwinner,sun20i-d1-i2c",
++				     "allwinner,sun8i-v536-i2c",
++				     "allwinner,sun6i-a31-i2c";
++			reg = <0x2502c00 0x400>;
++			interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_I2C3>;
++			resets = <&ccu RST_BUS_I2C3>;
++			dmas = <&dma 46>, <&dma 46>;
++			dma-names = "rx", "tx";
++			status = "disabled";
++			#address-cells = <1>;
++			#size-cells = <0>;
++		};
++
++		syscon: syscon@3000000 {
++			compatible = "allwinner,sun20i-d1-system-control";
++			reg = <0x3000000 0x1000>;
++			ranges;
++			#address-cells = <1>;
++			#size-cells = <1>;
++
++			regulators@3000150 {
++				compatible = "allwinner,sun20i-d1-system-ldos";
++				reg = <0x3000150 0x4>;
++
++				reg_ldoa: ldoa {
++				};
++
++				reg_ldob: ldob {
++				};
++			};
++		};
++
++		dma: dma-controller@3002000 {
++			compatible = "allwinner,sun20i-d1-dma";
++			reg = <0x3002000 0x1000>;
++			interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
++			clock-names = "bus", "mbus";
++			resets = <&ccu RST_BUS_DMA>;
++			dma-channels = <16>;
++			dma-requests = <48>;
++			#dma-cells = <1>;
++		};
++
++		sid: efuse@3006000 {
++			compatible = "allwinner,sun20i-d1-sid";
++			reg = <0x3006000 0x1000>;
++			#address-cells = <1>;
++			#size-cells = <1>;
++
++			ths_calib: ths-calib@14 {
++				reg = <0x14 0x4>;
++			};
++
++			bg_trim: bg-trim@28 {
++				reg = <0x28 0x4>;
++				bits = <16 8>;
++			};
++		};
++
++		mbus: dram-controller@3102000 {
++			compatible = "allwinner,sun20i-d1-mbus";
++			reg = <0x3102000 0x1000>,
++			      <0x3103000 0x1000>;
++			reg-names = "mbus", "dram";
++			interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_MBUS>,
++				 <&ccu CLK_DRAM>,
++				 <&ccu CLK_BUS_DRAM>;
++			clock-names = "mbus", "dram", "bus";
++			dma-ranges = <0 0x40000000 0x80000000>;
++			#address-cells = <1>;
++			#size-cells = <1>;
++			#interconnect-cells = <1>;
++		};
++
++		mmc0: mmc@4020000 {
++			compatible = "allwinner,sun20i-d1-mmc";
++			reg = <0x4020000 0x1000>;
++			interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
++			clock-names = "ahb", "mmc";
++			resets = <&ccu RST_BUS_MMC0>;
++			reset-names = "ahb";
++			cap-sd-highspeed;
++			max-frequency = <150000000>;
++			no-mmc;
++			status = "disabled";
++			#address-cells = <1>;
++			#size-cells = <0>;
++		};
++
++		mmc1: mmc@4021000 {
++			compatible = "allwinner,sun20i-d1-mmc";
++			reg = <0x4021000 0x1000>;
++			interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
++			clock-names = "ahb", "mmc";
++			resets = <&ccu RST_BUS_MMC1>;
++			reset-names = "ahb";
++			cap-sd-highspeed;
++			max-frequency = <150000000>;
++			no-mmc;
++			status = "disabled";
++			#address-cells = <1>;
++			#size-cells = <0>;
++		};
++
++		mmc2: mmc@4022000 {
++			compatible = "allwinner,sun20i-d1-emmc",
++				     "allwinner,sun50i-a100-emmc";
++			reg = <0x4022000 0x1000>;
++			interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
++			clock-names = "ahb", "mmc";
++			resets = <&ccu RST_BUS_MMC2>;
++			reset-names = "ahb";
++			cap-mmc-highspeed;
++			max-frequency = <150000000>;
++			mmc-ddr-1_8v;
++			mmc-ddr-3_3v;
++			no-sd;
++			no-sdio;
++			status = "disabled";
++			#address-cells = <1>;
++			#size-cells = <0>;
++		};
++
++		usb_otg: usb@4100000 {
++			compatible = "allwinner,sun20i-d1-musb",
++				     "allwinner,sun8i-a33-musb";
++			reg = <0x4100000 0x400>;
++			interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "mc";
++			clocks = <&ccu CLK_BUS_OTG>;
++			resets = <&ccu RST_BUS_OTG>;
++			extcon = <&usbphy 0>;
++			phys = <&usbphy 0>;
++			phy-names = "usb";
++			status = "disabled";
++		};
++
++		usbphy: phy@4100400 {
++			compatible = "allwinner,sun20i-d1-usb-phy";
++			reg = <0x4100400 0x100>,
++			      <0x4101800 0x100>,
++			      <0x4200800 0x100>;
++			reg-names = "phy_ctrl",
++				    "pmu0",
++				    "pmu1";
++			clocks = <&osc24M>,
++				 <&osc24M>;
++			clock-names = "usb0_phy",
++				      "usb1_phy";
++			resets = <&ccu RST_USB_PHY0>,
++				 <&ccu RST_USB_PHY1>;
++			reset-names = "usb0_reset",
++				      "usb1_reset";
++			status = "disabled";
++			#phy-cells = <1>;
++		};
++
++		ehci0: usb@4101000 {
++			compatible = "allwinner,sun20i-d1-ehci",
++				     "generic-ehci";
++			reg = <0x4101000 0x100>;
++			interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_OHCI0>,
++				 <&ccu CLK_BUS_EHCI0>,
++				 <&ccu CLK_USB_OHCI0>;
++			resets = <&ccu RST_BUS_OHCI0>,
++				 <&ccu RST_BUS_EHCI0>;
++			phys = <&usbphy 0>;
++			phy-names = "usb";
++			status = "disabled";
++		};
++
++		ohci0: usb@4101400 {
++			compatible = "allwinner,sun20i-d1-ohci",
++				     "generic-ohci";
++			reg = <0x4101400 0x100>;
++			interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_OHCI0>,
++				 <&ccu CLK_USB_OHCI0>;
++			resets = <&ccu RST_BUS_OHCI0>;
++			phys = <&usbphy 0>;
++			phy-names = "usb";
++			status = "disabled";
++		};
++
++		ehci1: usb@4200000 {
++			compatible = "allwinner,sun20i-d1-ehci",
++				     "generic-ehci";
++			reg = <0x4200000 0x100>;
++			interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_OHCI1>,
++				 <&ccu CLK_BUS_EHCI1>,
++				 <&ccu CLK_USB_OHCI1>;
++			resets = <&ccu RST_BUS_OHCI1>,
++				 <&ccu RST_BUS_EHCI1>;
++			phys = <&usbphy 1>;
++			phy-names = "usb";
++			status = "disabled";
++		};
++
++		ohci1: usb@4200400 {
++			compatible = "allwinner,sun20i-d1-ohci",
++				     "generic-ohci";
++			reg = <0x4200400 0x100>;
++			interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_OHCI1>,
++				 <&ccu CLK_USB_OHCI1>;
++			resets = <&ccu RST_BUS_OHCI1>;
++			phys = <&usbphy 1>;
++			phy-names = "usb";
++			status = "disabled";
++		};
++
++		emac: ethernet@4500000 {
++			compatible = "allwinner,sun20i-d1-emac",
++				     "allwinner,sun50i-a64-emac";
++			reg = <0x4500000 0x10000>;
++			interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "macirq";
++			clocks = <&ccu CLK_BUS_EMAC>;
++			clock-names = "stmmaceth";
++			resets = <&ccu RST_BUS_EMAC>;
++			reset-names = "stmmaceth";
++			syscon = <&syscon>;
++			status = "disabled";
++
++			mdio: mdio {
++				compatible = "snps,dwmac-mdio";
++				#address-cells = <1>;
++				#size-cells = <0>;
++			};
++		};
++
++		display_clocks: clock-controller@5000000 {
++			compatible = "allwinner,sun20i-d1-de2-clk",
++				     "allwinner,sun50i-h5-de2-clk";
++			reg = <0x5000000 0x10000>;
++			clocks = <&ccu CLK_BUS_DE>, <&ccu CLK_DE>;
++			clock-names = "bus", "mod";
++			resets = <&ccu RST_BUS_DE>;
++			#clock-cells = <1>;
++			#reset-cells = <1>;
++		};
++
++		mixer0: mixer@5100000 {
++			compatible = "allwinner,sun20i-d1-de2-mixer-0";
++			reg = <0x5100000 0x100000>;
++			clocks = <&display_clocks CLK_BUS_MIXER0>,
++				 <&display_clocks CLK_MIXER0>;
++			clock-names = "bus", "mod";
++			resets = <&display_clocks RST_MIXER0>;
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				mixer0_out: port@1 {
++					reg = <1>;
++
++					mixer0_out_tcon_top_mixer0: endpoint {
++						remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
++					};
++				};
++			};
++		};
++
++		mixer1: mixer@5200000 {
++			compatible = "allwinner,sun20i-d1-de2-mixer-1";
++			reg = <0x5200000 0x100000>;
++			clocks = <&display_clocks CLK_BUS_MIXER1>,
++				 <&display_clocks CLK_MIXER1>;
++			clock-names = "bus", "mod";
++			resets = <&display_clocks RST_MIXER1>;
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				mixer1_out: port@1 {
++					reg = <1>;
++
++					mixer1_out_tcon_top_mixer1: endpoint {
++						remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
++					};
++				};
++			};
++		};
++
++		tcon_top: tcon-top@5460000 {
++			compatible = "allwinner,sun20i-d1-tcon-top";
++			reg = <0x5460000 0x1000>;
++			clocks = <&ccu CLK_BUS_DPSS_TOP>,
++				 <&ccu CLK_TCON_TV>,
++				 <&ccu CLK_TVE>,
++				 <&ccu CLK_TCON_LCD0>;
++			clock-names = "bus", "tcon-tv0", "tve0", "dsi";
++			clock-output-names = "tcon-top-tv0", "tcon-top-dsi";
++			resets = <&ccu RST_BUS_DPSS_TOP>;
++			#clock-cells = <1>;
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				tcon_top_mixer0_in: port@0 {
++					reg = <0>;
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					tcon_top_mixer0_in_mixer0: endpoint@0 {
++						reg = <0>;
++						remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
++					};
++				};
++
++				tcon_top_mixer0_out: port@1 {
++					reg = <1>;
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
++						reg = <0>;
++						remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer0>;
++					};
++
++					tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
++						reg = <2>;
++						remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
++					};
++				};
++
++				tcon_top_mixer1_in: port@2 {
++					reg = <2>;
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					tcon_top_mixer1_in_mixer1: endpoint@1 {
++						reg = <1>;
++						remote-endpoint = <&mixer1_out_tcon_top_mixer1>;
++					};
++				};
++
++				tcon_top_mixer1_out: port@3 {
++					reg = <3>;
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
++						reg = <0>;
++						remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer1>;
++					};
++
++					tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
++						reg = <2>;
++						remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
++					};
++				};
++
++				tcon_top_hdmi_in: port@4 {
++					reg = <4>;
++
++					tcon_top_hdmi_in_tcon_tv0: endpoint {
++						remote-endpoint = <&tcon_tv0_out_tcon_top_hdmi>;
++					};
++				};
++
++				tcon_top_hdmi_out: port@5 {
++					reg = <5>;
++				};
++			};
++		};
++
++		tcon_lcd0: lcd-controller@5461000 {
++			compatible = "allwinner,sun20i-d1-tcon-lcd";
++			reg = <0x5461000 0x1000>;
++			interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_TCON_LCD0>,
++				 <&ccu CLK_TCON_LCD0>;
++			clock-names = "ahb", "tcon-ch0";
++			clock-output-names = "tcon-pixel-clock";
++			resets = <&ccu RST_BUS_TCON_LCD0>,
++				 <&ccu RST_BUS_LVDS0>;
++			reset-names = "lcd", "lvds";
++			#clock-cells = <0>;
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				tcon_lcd0_in: port@0 {
++					reg = <0>;
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					tcon_lcd0_in_tcon_top_mixer0: endpoint@0 {
++						reg = <0>;
++						remote-endpoint = <&tcon_top_mixer0_out_tcon_lcd0>;
++					};
++
++					tcon_lcd0_in_tcon_top_mixer1: endpoint@1 {
++						reg = <1>;
++						remote-endpoint = <&tcon_top_mixer1_out_tcon_lcd0>;
++					};
++				};
++
++				tcon_lcd0_out: port@1 {
++					reg = <1>;
++				};
++			};
++		};
++
++		tcon_tv0: lcd-controller@5470000 {
++			compatible = "allwinner,sun20i-d1-tcon-tv";
++			reg = <0x5470000 0x1000>;
++			interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_TCON_TV>,
++				 <&tcon_top CLK_TCON_TOP_TV0>;
++			clock-names = "ahb", "tcon-ch1";
++			resets = <&ccu RST_BUS_TCON_TV>;
++			reset-names = "lcd";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				tcon_tv0_in: port@0 {
++					reg = <0>;
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
++						reg = <0>;
++						remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
++					};
++
++					tcon_tv0_in_tcon_top_mixer1: endpoint@1 {
++						reg = <1>;
++						remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
++					};
++				};
++
++				tcon_tv0_out: port@1 {
++					reg = <1>;
++
++					tcon_tv0_out_tcon_top_hdmi: endpoint {
++						remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
++					};
++				};
++			};
++		};
++
++		riscv_wdt: watchdog@6011000 {
++			compatible = "allwinner,sun20i-d1-wdt";
++			reg = <0x6011000 0x20>;
++			interrupts = <147 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&osc24M>, <&rtc CLK_OSC32K>;
++			clock-names = "hosc", "losc";
++		};
++
++		r_ccu: clock-controller@7010000 {
++			compatible = "allwinner,sun20i-d1-r-ccu";
++			reg = <0x7010000 0x400>;
++			clocks = <&osc24M>,
++				 <&rtc CLK_OSC32K>,
++				 <&rtc CLK_IOSC>,
++				 <&ccu CLK_PLL_PERIPH0_DIV3>;
++			clock-names = "hosc", "losc", "iosc", "pll-periph";
++			#clock-cells = <1>;
++			#reset-cells = <1>;
++		};
++
++		rtc: rtc@7090000 {
++			compatible = "allwinner,sun20i-d1-rtc",
++				     "allwinner,sun50i-r329-rtc";
++			reg = <0x7090000 0x400>;
++			interrupts = <160 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&r_ccu CLK_BUS_R_RTC>,
++				 <&osc24M>,
++				 <&r_ccu CLK_R_AHB>;
++			clock-names = "bus", "hosc", "ahb";
++			#clock-cells = <1>;
++		};
++
++		plic: interrupt-controller@10000000 {
++			compatible = "allwinner,sun20i-d1-plic",
++				     "thead,c900-plic";
++			reg = <0x10000000 0x4000000>;
++			interrupts-extended = <&cpu0_intc 11>,
++					      <&cpu0_intc 9>;
++			interrupt-controller;
++			riscv,ndev = <176>;
++			#address-cells = <0>;
++			#interrupt-cells = <2>;
++		};
++	};
++};
+--- /dev/null
++++ b/arch/riscv/dts/sunxi-u-boot.dtsi
+@@ -0,0 +1,68 @@
++// SPDX-License-Identifier: (GPL-2.0 OR MIT)
++
++#include "binman.dtsi"
++
++/ {
++	cpus {
++		u-boot,dm-spl;
++	};
++
++	soc {
++		u-boot,dm-spl;
++	};
++};
++
++&binman {
++	u-boot-sunxi-with-spl {
++		filename = "u-boot-sunxi-with-spl.bin";
++		pad-byte = <0xff>;
++
++		blob@0 {
++			filename = "spl/sunxi-spl.bin";
++		};
++
++		blob@1 {
++			filename = "u-boot.itb";
++		};
++	};
++};
++
++&ccu {
++	u-boot,dm-spl;
++};
++
++&cpu0 {
++	u-boot,dm-spl;
++};
++
++&mbus {
++	u-boot,dm-spl;
++};
++
++&mmc0 {
++	u-boot,dm-spl;
++};
++
++&mmc0_pins {
++	u-boot,dm-spl;
++};
++
++&osc24M {
++	u-boot,dm-spl;
++};
++
++&pio {
++	u-boot,dm-spl;
++};
++
++&rtc {
++	u-boot,dm-spl;
++};
++
++&uart0 {
++	u-boot,dm-spl;
++};
++
++&uart0_pb8_pins {
++	u-boot,dm-spl;
++};
+--- /dev/null
++++ b/include/dt-bindings/clock/sun20i-d1-r-ccu.h
+@@ -0,0 +1,19 @@
++/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
++/*
++ * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
++ */
++
++#ifndef _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_
++#define _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_
++
++#define CLK_R_AHB		0
++
++#define CLK_BUS_R_TIMER		2
++#define CLK_BUS_R_TWD		3
++#define CLK_BUS_R_PPU		4
++#define CLK_R_IR_RX		5
++#define CLK_BUS_R_IR_RX		6
++#define CLK_BUS_R_RTC		7
++#define CLK_BUS_R_CPUCFG	8
++
++#endif /* _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_ */
+--- /dev/null
++++ b/include/dt-bindings/reset/sun20i-d1-r-ccu.h
+@@ -0,0 +1,16 @@
++/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
++/*
++ * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
++ */
++
++#ifndef _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_
++#define _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_
++
++#define RST_BUS_R_TIMER		0
++#define RST_BUS_R_TWD		1
++#define RST_BUS_R_PPU		2
++#define RST_BUS_R_IR_RX		3
++#define RST_BUS_R_RTC		4
++#define RST_BUS_R_CPUCFG	5
++
++#endif /* _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_ */
diff --git a/package/boot/uboot-d1/patches/0079-riscv-Add-CONFIG_TARGET_SUN20I_D1.patch b/package/boot/uboot-d1/patches/0079-riscv-Add-CONFIG_TARGET_SUN20I_D1.patch
new file mode 100644
index 00000000000000..a3678243c14523
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0079-riscv-Add-CONFIG_TARGET_SUN20I_D1.patch
@@ -0,0 +1,169 @@
+From 6b0c83a5c7b9189fb1c5cf56145ec4882d9e5588 Mon Sep 17 00:00:00 2001
+From: Zoltan HERPAI <wigyori@uid0.hu>
+Date: Tue, 6 Jun 2023 18:13:34 +0000
+Subject: [PATCH 79/90] riscv: Add CONFIG_TARGET_SUN20I_D1
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
+---
+ arch/riscv/Kconfig        |  5 +++++
+ board/sunxi/Kconfig       | 30 +++++++++++++++++++++++++++---
+ common/spl/Kconfig        |  1 +
+ drivers/clk/sunxi/Kconfig |  1 +
+ include/configs/sun20i.h  | 11 +++++++++++
+ 5 files changed, 45 insertions(+), 3 deletions(-)
+ create mode 100644 include/configs/sun20i.h
+
+--- a/arch/riscv/Kconfig
++++ b/arch/riscv/Kconfig
+@@ -31,6 +31,11 @@ config TARGET_SIPEED_MAIX
+ 	bool "Support Sipeed Maix Board"
+ 	select SYS_CACHE_SHIFT_6
+ 
++config TARGET_SUN20I_D1
++	bool "Support Allwinner D1 Boards"
++	select BOARD_SUNXI
++	select SYS_CACHE_SHIFT_6
++
+ endchoice
+ 
+ config SYS_ICACHE_OFF
+--- a/board/sunxi/Kconfig
++++ b/board/sunxi/Kconfig
+@@ -13,8 +13,18 @@ config BOARD_SUNXI
+ 	select DM_SERIAL if SERIAL
+ 	select DM_SPI if SPI
+ 	select DM_SPI_FLASH if SPI
++	select GENERIC_RISCV if RISCV
+ 	select OF_BOARD_SETUP
+ 	select PINCTRL
++	select RAM if SPL_DM
++	select SPL_CLK if SPL_DM
++	select SPL_DM if RISCV && SPL
++	select SPL_DM_SPI if SPL_DM && SPL_SPI
++	select SPL_DM_SPI_FLASH if SPL_DM && SPL_SPI
++	select SPL_OF_CONTROL if SPL_DM
++	select SPL_PINCTRL if SPL_DM
++	select SPL_PINCONF if SPL_DM
++	select SPL_RAM if SPL_DM
+ 	select SPL_SEPARATE_BSS if SPL
+ 	select SUPPORT_SPL
+ 	select SYS_RELOC_GD_ENV_ADDR
+@@ -28,12 +38,14 @@ config BOARD_SUNXI
+ 	imply DISTRO_DEFAULTS
+ 	imply FAT_WRITE
+ 	imply FIT
++	imply MMC
+ 	imply OF_LIBFDT_OVERLAY
+ 	imply PRE_CONSOLE_BUFFER
+ 	imply SPL
+ 	imply SPL_GPIO
+ 	imply SPL_LIBCOMMON_SUPPORT
+ 	imply SPL_LIBGENERIC_SUPPORT
++	imply SPL_LOAD_FIT
+ 	imply SPL_MMC if MMC
+ 	imply SPL_POWER
+ 	imply SPL_SERIAL
+@@ -41,6 +53,7 @@ config BOARD_SUNXI
+ 	imply SYS_I2C_MVTWSI
+ 	imply SYS_NS16550
+ 	imply SYSRESET
++	imply SYSRESET_SBI
+ 	imply SYSRESET_WATCHDOG
+ 	imply SYSRESET_WATCHDOG_AUTO
+ 	imply USB_EHCI_GENERIC
+@@ -67,6 +80,12 @@ config SPL_BSS_START_ADDR
+ 	default 0x4ff80000 if SUNXI_MINIMUM_DRAM_MB >= 256
+ 	default 0x43f80000 if SUNXI_MINIMUM_DRAM_MB >= 64
+ 
++config SPL_OPENSBI_LOAD_ADDR
++	default 0x40000000 if RISCV
++
++config SPL_STACK
++	default 0x48000 if TARGET_SUN20I_D1
++
+ config SPL_STACK_R_ADDR
+ 	default 0x81e00000 if MACH_SUNIV
+ 	default 0x2fe00000 if MACH_SUN9I
+@@ -75,13 +94,13 @@ config SPL_STACK_R_ADDR
+ 
+ config SPL_TEXT_BASE
+ 	default 0x10060 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5
+-	default 0x20060 if SUN50I_GEN_H6
++	default 0x20060 if SUN50I_GEN_H6 || TARGET_SUN20I_D1
+ 	default 0x00060
+ 
+ config SUNXI_MINIMUM_DRAM_MB
+ 	int
+ 	default 32 if MACH_SUNIV
+-	default 64 if MACH_SUN8I_V3S
++	default 64 if MACH_SUN8I_V3S || TARGET_SUN20I_D1
+ 	default 256
+ 	help
+ 	  Minimum DRAM size expected on the board. Traditionally we
+@@ -94,7 +113,7 @@ config SUNXI_MINIMUM_DRAM_MB
+ config SUNXI_SRAM_ADDRESS
+ 	hex
+ 	default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5
+-	default 0x20000 if SUN50I_GEN_H6
++	default 0x20000 if SUN50I_GEN_H6 || TARGET_SUN20I_D1
+ 	default 0x0
+ 	help
+ 	  Older Allwinner SoCs have their boot mask ROM mapped just
+@@ -113,6 +132,7 @@ config SYS_CLK_FREQ
+ 	default  912000000 if MACH_SUN7I
+ 	default 1008000000 if MACH_SUN8I
+ 	default 1008000000 if MACH_SUN9I
++	default 1008000000 if TARGET_SUN20I_D1
+ 	default  816000000 if MACH_SUN50I || MACH_SUN50I_H5
+ 	default  888000000 if MACH_SUN50I_H6
+ 	default 1008000000 if MACH_SUN50I_H616
+@@ -125,10 +145,14 @@ config SYS_CONFIG_NAME
+ 	default "sun7i"  if MACH_SUN7I
+ 	default "sun8i"  if MACH_SUN8I
+ 	default "sun9i"  if MACH_SUN9I
++	default "sun20i" if TARGET_SUN20I_D1
+ 	default "sun50i" if MACH_SUN50I
+ 	default "sun50i" if MACH_SUN50I_H6
+ 	default "sun50i" if MACH_SUN50I_H616
+ 
++config SYS_CPU
++	default "generic" if TARGET_SUN20I_D1
++
+ config SYS_LOAD_ADDR
+ 	default 0x81000000 if MACH_SUNIV
+ 	default 0x22000000 if MACH_SUN9I
+--- a/common/spl/Kconfig
++++ b/common/spl/Kconfig
+@@ -78,6 +78,7 @@ config SPL_MAX_SIZE
+ 	hex "Maximum size of the SPL image, excluding BSS"
+ 	default 0x37fa0 if MACH_SUN50I_H616
+ 	default 0x30000 if ARCH_MX6 && MX6_OCRAM_256KB
++	default 0x27fa0 if TARGET_SUN20I_D1
+ 	default 0x25fa0 if MACH_SUN50I_H6
+ 	default 0x1b000 if AM33XX && !TI_SECURE_DEVICE
+ 	default 0x10000 if ARCH_MX6 && !MX6_OCRAM_256KB
+--- a/drivers/clk/sunxi/Kconfig
++++ b/drivers/clk/sunxi/Kconfig
+@@ -98,6 +98,7 @@ config CLK_SUN8I_H3
+ 
+ config CLK_SUN20I_D1
+ 	bool "Clock driver for Allwinner D1"
++	default TARGET_SUN20I_D1
+ 	help
+ 	  This enables common clock driver support for platforms based
+ 	  on Allwinner D1 SoC.
+--- /dev/null
++++ b/include/configs/sun20i.h
+@@ -0,0 +1,11 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * Placeholder wrapper to allow addressing Allwinner D1 (and later) sun20i
++ * CPU based devices separately. Please do not add anything in here.
++ */
++#ifndef __CONFIG_H
++#define __CONFIG_H
++
++#include <configs/sunxi-common.h>
++
++#endif /* __CONFIG_H */
diff --git a/package/boot/uboot-d1/patches/0080-gpio-sunxi-Hack-up-the-driver-for-the-D1.patch b/package/boot/uboot-d1/patches/0080-gpio-sunxi-Hack-up-the-driver-for-the-D1.patch
new file mode 100644
index 00000000000000..42a5c28584499a
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0080-gpio-sunxi-Hack-up-the-driver-for-the-D1.patch
@@ -0,0 +1,134 @@
+From 28682ca027b9fa64f3de4cea99373642f36c4e6c Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 8 Aug 2021 19:32:14 -0500
+Subject: [PATCH 80/90] gpio: sunxi: Hack up the driver for the D1
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm/include/asm/arch-sunxi/gpio.h | 12 ++++++++++--
+ arch/arm/mach-sunxi/pinmux.c           |  8 +++++++-
+ drivers/gpio/sunxi_gpio.c              |  3 +++
+ 3 files changed, 20 insertions(+), 3 deletions(-)
+
+--- a/arch/arm/include/asm/arch-sunxi/gpio.h
++++ b/arch/arm/include/asm/arch-sunxi/gpio.h
+@@ -9,7 +9,9 @@
+ #define _SUNXI_GPIO_H
+ 
+ #include <linux/types.h>
++#if 0
+ #include <asm/arch/cpu.h>
++#endif
+ 
+ /*
+  * sunxi has 9 banks of gpio, they are:
+@@ -55,30 +57,36 @@
+ struct sunxi_gpio {
+ 	u32 cfg[4];
+ 	u32 dat;
+-	u32 drv[2];
++	u32 drv[4];
+ 	u32 pull[2];
++	u32 reserved;
+ };
+ 
+ /* gpio interrupt control */
+ struct sunxi_gpio_int {
+-	u32 cfg[3];
++	u32 cfg[4];
+ 	u32 ctl;
+ 	u32 sta;
+ 	u32 deb;		/* interrupt debounce */
++	u32 reserved;
+ };
+ 
++#if 0
+ struct sunxi_gpio_reg {
+ 	struct sunxi_gpio gpio_bank[SUNXI_GPIO_BANKS];
+ 	u8 res[0xbc];
+ 	struct sunxi_gpio_int gpio_int;
+ };
++#endif
+ 
+ #define SUN50I_H6_GPIO_POW_MOD_SEL	0x340
+ #define SUN50I_H6_GPIO_POW_MOD_VAL	0x348
+ 
++#if 0
+ #define BANK_TO_GPIO(bank)	(((bank) < SUNXI_GPIO_L) ? \
+ 	&((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank] : \
+ 	&((struct sunxi_gpio_reg *)SUNXI_R_PIO_BASE)->gpio_bank[(bank) - SUNXI_GPIO_L])
++#endif
+ 
+ #define GPIO_BANK(pin)		((pin) >> 5)
+ #define GPIO_NUM(pin)		((pin) & 0x1f)
+--- a/arch/arm/mach-sunxi/pinmux.c
++++ b/arch/arm/mach-sunxi/pinmux.c
+@@ -7,7 +7,7 @@
+ 
+ #include <common.h>
+ #include <asm/io.h>
+-#include <asm/arch/gpio.h>
++//#include <asm/arch/gpio.h>
+ 
+ void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val)
+ {
+@@ -17,6 +17,7 @@ void sunxi_gpio_set_cfgbank(struct sunxi
+ 	clrsetbits_le32(&pio->cfg[index], 0xf << offset, val << offset);
+ }
+ 
++#if !CONFIG_IS_ENABLED(DM_GPIO)
+ void sunxi_gpio_set_cfgpin(u32 pin, u32 val)
+ {
+ 	u32 bank = GPIO_BANK(pin);
+@@ -24,6 +25,7 @@ void sunxi_gpio_set_cfgpin(u32 pin, u32
+ 
+ 	sunxi_gpio_set_cfgbank(pio, pin, val);
+ }
++#endif
+ 
+ int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset)
+ {
+@@ -37,6 +39,7 @@ int sunxi_gpio_get_cfgbank(struct sunxi_
+ 	return cfg & 0xf;
+ }
+ 
++#if !CONFIG_IS_ENABLED(DM_GPIO)
+ int sunxi_gpio_get_cfgpin(u32 pin)
+ {
+ 	u32 bank = GPIO_BANK(pin);
+@@ -52,6 +55,7 @@ void sunxi_gpio_set_drv(u32 pin, u32 val
+ 
+ 	sunxi_gpio_set_drv_bank(pio, pin, val);
+ }
++#endif
+ 
+ void sunxi_gpio_set_drv_bank(struct sunxi_gpio *pio, u32 bank_offset, u32 val)
+ {
+@@ -61,6 +65,7 @@ void sunxi_gpio_set_drv_bank(struct sunx
+ 	clrsetbits_le32(&pio->drv[index], 0x3 << offset, val << offset);
+ }
+ 
++#if !CONFIG_IS_ENABLED(DM_GPIO)
+ void sunxi_gpio_set_pull(u32 pin, u32 val)
+ {
+ 	u32 bank = GPIO_BANK(pin);
+@@ -68,6 +73,7 @@ void sunxi_gpio_set_pull(u32 pin, u32 va
+ 
+ 	sunxi_gpio_set_pull_bank(pio, pin, val);
+ }
++#endif
+ 
+ void sunxi_gpio_set_pull_bank(struct sunxi_gpio *pio, int bank_offset, u32 val)
+ {
+--- a/drivers/gpio/sunxi_gpio.c
++++ b/drivers/gpio/sunxi_gpio.c
+@@ -18,6 +18,9 @@
+ #include <asm/gpio.h>
+ #include <dt-bindings/gpio/gpio.h>
+ 
++#include "../../arch/arm/include/asm/arch-sunxi/gpio.h"
++#include "../../arch/arm/mach-sunxi/pinmux.c"
++
+ #if !CONFIG_IS_ENABLED(DM_GPIO)
+ static int sunxi_gpio_output(u32 pin, u32 val)
+ {
diff --git a/package/boot/uboot-d1/patches/0081-mmc-sunxi-Hack-up-the-driver-for-the-D1.patch b/package/boot/uboot-d1/patches/0081-mmc-sunxi-Hack-up-the-driver-for-the-D1.patch
new file mode 100644
index 00000000000000..3d8ddf45838e83
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0081-mmc-sunxi-Hack-up-the-driver-for-the-D1.patch
@@ -0,0 +1,118 @@
+From 4df80766531bc35510981ebc5ea0bb07264beac9 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 8 Aug 2021 19:31:20 -0500
+Subject: [PATCH 81/90] mmc: sunxi: Hack up the driver for the D1
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/riscv/include/asm/io.h |  1 +
+ drivers/mmc/sunxi_mmc.c     | 29 +++++++++++++++++++++++++----
+ drivers/mmc/sunxi_mmc.h     |  2 --
+ 3 files changed, 26 insertions(+), 6 deletions(-)
+
+--- a/arch/riscv/include/asm/io.h
++++ b/arch/riscv/include/asm/io.h
+@@ -85,6 +85,7 @@ static inline u16 readw(const volatile v
+ 	return val;
+ }
+ 
++#define readl_relaxed readl
+ static inline u32 readl(const volatile void __iomem *addr)
+ {
+ 	u32	val;
+--- a/drivers/mmc/sunxi_mmc.c
++++ b/drivers/mmc/sunxi_mmc.c
+@@ -23,9 +23,9 @@
+ #include <reset.h>
+ #include <asm/gpio.h>
+ #include <asm/io.h>
++#if !CONFIG_IS_ENABLED(DM_MMC)
+ #include <asm/arch/clock.h>
+ #include <asm/arch/cpu.h>
+-#if !CONFIG_IS_ENABLED(DM_MMC)
+ #include <asm/arch/mmc.h>
+ #endif
+ #include <linux/delay.h>
+@@ -36,6 +36,23 @@
+ #define CCM_MMC_CTRL_MODE_SEL_NEW	0
+ #endif
+ 
++#include "../../arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h"
++
++unsigned int clock_get_pll6(void)
++{
++	uint32_t rval = readl((void *)0x2001020);
++
++	int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
++	int m = ((rval >> 1) & 0x1) + 1;
++	int p0 = ((rval >> 16) & 0x7) + 1;
++	/* The register defines PLL6-2X, not plain PLL6 */
++	uint32_t freq = 24000000UL * n / m / p0;
++
++	printf("PLL reg = 0x%08x, freq = %d\n", rval, freq);
++
++	return freq;
++}
++
+ struct sunxi_mmc_plat {
+ 	struct mmc_config cfg;
+ 	struct mmc mmc;
+@@ -60,7 +77,8 @@ static bool sunxi_mmc_can_calibrate(void
+ 	return IS_ENABLED(CONFIG_MACH_SUN50I) ||
+ 	       IS_ENABLED(CONFIG_MACH_SUN50I_H5) ||
+ 	       IS_ENABLED(CONFIG_SUN50I_GEN_H6) ||
+-	       IS_ENABLED(CONFIG_MACH_SUN8I_R40);
++	       IS_ENABLED(CONFIG_MACH_SUN8I_R40) ||
++	       IS_ENABLED(CONFIG_TARGET_SUN20I_D1);
+ }
+ 
+ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
+@@ -194,7 +212,7 @@ static int mmc_config_clock(struct sunxi
+ 	rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
+ 	writel(rval, &priv->reg->clkcr);
+ 
+-#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
++#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_TARGET_SUN20I_D1)
+ 	/* A64 supports calibration of delays on MMC controller and we
+ 	 * have to set delay of zero before starting calibration.
+ 	 * Allwinner BSP driver sets a delay only in the case of
+@@ -622,7 +640,8 @@ static unsigned get_mclk_offset(void)
+ 	if (IS_ENABLED(CONFIG_MACH_SUN9I_A80))
+ 		return 0x410;
+ 
+-	if (IS_ENABLED(CONFIG_SUN50I_GEN_H6))
++	if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) ||
++	    IS_ENABLED(CONFIG_TARGET_SUN20I_D1))
+ 		return 0x830;
+ 
+ 	return 0x88;
+@@ -662,6 +681,7 @@ static int sunxi_mmc_probe(struct udevic
+ 		return ret;
+ 	ccu_reg = (u32 *)(uintptr_t)ofnode_get_addr(args.node);
+ 
++#define SUNXI_MMC0_BASE 0x4020000
+ 	priv->mmc_no = ((uintptr_t)priv->reg - SUNXI_MMC0_BASE) / 0x1000;
+ 	priv->mclkreg = (void *)ccu_reg + get_mclk_offset() + priv->mmc_no * 4;
+ 
+@@ -703,6 +723,7 @@ static const struct udevice_id sunxi_mmc
+ 	{ .compatible = "allwinner,sun7i-a20-mmc" },
+ 	{ .compatible = "allwinner,sun8i-a83t-emmc" },
+ 	{ .compatible = "allwinner,sun9i-a80-mmc" },
++	{ .compatible = "allwinner,sun20i-d1-mmc" },
+ 	{ .compatible = "allwinner,sun50i-a64-mmc" },
+ 	{ .compatible = "allwinner,sun50i-a64-emmc" },
+ 	{ .compatible = "allwinner,sun50i-h6-mmc" },
+--- a/drivers/mmc/sunxi_mmc.h
++++ b/drivers/mmc/sunxi_mmc.h
+@@ -45,11 +45,9 @@ struct sunxi_mmc {
+ 	u32 chda;		/* 0x90 */
+ 	u32 cbda;		/* 0x94 */
+ 	u32 res2[26];
+-#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
+ 	u32 res3[17];
+ 	u32 samp_dl;
+ 	u32 res4[46];
+-#endif
+ 	u32 fifo;		/* 0x100 / 0x200 FIFO access address */
+ };
+ 
diff --git a/package/boot/uboot-d1/patches/0082-pinctrl-sunxi-Hack-up-the-driver-for-the-D1.patch b/package/boot/uboot-d1/patches/0082-pinctrl-sunxi-Hack-up-the-driver-for-the-D1.patch
new file mode 100644
index 00000000000000..06502d3186d801
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0082-pinctrl-sunxi-Hack-up-the-driver-for-the-D1.patch
@@ -0,0 +1,29 @@
+From c33ca5c6a5be74711460756bf86c45b6c6fd0a3f Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Thu, 4 Nov 2021 17:49:15 -0500
+Subject: [PATCH 82/90] pinctrl: sunxi: Hack up the driver for the D1
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/pinctrl/sunxi/pinctrl-sunxi.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
++++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+@@ -9,6 +9,7 @@
+ #include <malloc.h>
+ 
+ #include <asm/gpio.h>
++#include "../../../arch/arm/include/asm/arch-sunxi/gpio.h"
+ 
+ extern U_BOOT_DRIVER(gpio_sunxi);
+ 
+@@ -49,7 +50,7 @@ static const char *sunxi_pinctrl_get_pin
+ 					      uint pin_selector)
+ {
+ 	const struct sunxi_pinctrl_desc *desc = dev_get_priv(dev);
+-	static char pin_name[sizeof("PN31")];
++	static char pin_name[sizeof("PN31")] __section(".data");
+ 
+ 	snprintf(pin_name, sizeof(pin_name), "P%c%d",
+ 		 pin_selector / SUNXI_GPIOS_PER_BANK + desc->first_bank + 'A',
diff --git a/package/boot/uboot-d1/patches/0083-ram-sunxi-Add-Allwinner-D1-DRAM-driver.patch b/package/boot/uboot-d1/patches/0083-ram-sunxi-Add-Allwinner-D1-DRAM-driver.patch
new file mode 100644
index 00000000000000..73e3b1060d4e53
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0083-ram-sunxi-Add-Allwinner-D1-DRAM-driver.patch
@@ -0,0 +1,1943 @@
+From 9f612f3a1fd3d0759abca3720d488a17d159aa17 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 30 Oct 2022 14:54:08 -0500
+Subject: [PATCH 83/90] ram: sunxi: Add Allwinner D1 DRAM driver
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/ram/Kconfig                     |    1 +
+ drivers/ram/Makefile                    |    1 +
+ drivers/ram/sunxi/Kconfig               |    6 +
+ drivers/ram/sunxi/Makefile              |    3 +
+ drivers/ram/sunxi/dram_v2.h             |   65 +
+ drivers/ram/sunxi/mctl_hal-sun20iw1p1.c | 1771 +++++++++++++++++++++++
+ drivers/ram/sunxi/sdram.h               |   46 +
+ 7 files changed, 1893 insertions(+)
+ create mode 100644 drivers/ram/sunxi/Kconfig
+ create mode 100644 drivers/ram/sunxi/Makefile
+ create mode 100644 drivers/ram/sunxi/dram_v2.h
+ create mode 100644 drivers/ram/sunxi/mctl_hal-sun20iw1p1.c
+ create mode 100644 drivers/ram/sunxi/sdram.h
+
+--- a/drivers/ram/Kconfig
++++ b/drivers/ram/Kconfig
+@@ -101,3 +101,4 @@ source "drivers/ram/rockchip/Kconfig"
+ source "drivers/ram/sifive/Kconfig"
+ source "drivers/ram/stm32mp1/Kconfig"
+ source "drivers/ram/octeon/Kconfig"
++source "drivers/ram/sunxi/Kconfig"
+--- a/drivers/ram/Makefile
++++ b/drivers/ram/Makefile
+@@ -20,5 +20,6 @@ obj-$(CONFIG_K3_DDRSS) += k3-ddrss/
+ obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o
+ 
+ obj-$(CONFIG_RAM_SIFIVE) += sifive/
++obj-$(CONFIG_RAM_SUNXI) += sunxi/
+ 
+ obj-$(CONFIG_ARCH_OCTEON) += octeon/
+--- /dev/null
++++ b/drivers/ram/sunxi/Kconfig
+@@ -0,0 +1,6 @@
++config RAM_SUNXI
++	bool "Ram drivers support for sunxi SoCs"
++	depends on RAM && BOARD_SUNXI
++	default y
++	help
++	  This enables support for ram drivers of sunxi SoCs.
+--- /dev/null
++++ b/drivers/ram/sunxi/Makefile
+@@ -0,0 +1,3 @@
++# SPDX-License-Identifier: GPL-2.0+
++
++obj-$(CONFIG_RAM_SUNXI) += mctl_hal-sun20iw1p1.o
+--- /dev/null
++++ b/drivers/ram/sunxi/dram_v2.h
+@@ -0,0 +1,65 @@
++/*
++ * (C) Copyright 2007-2013
++* SPDX-License-Identifier:	GPL-2.0+
++ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
++ * Jerry Wang <wangflord@allwinnertech.com>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#ifndef  __dram_head_h__
++#define  __dram_head_h__
++
++struct dram_para_t
++{
++	//normal configuration
++	unsigned int        dram_clk;
++	unsigned int        dram_type;		//dram_type			DDR2: 2				DDR3: 3		LPDDR2: 6	LPDDR3: 7	DDR3L: 31
++	//unsigned int        lpddr2_type;	//LPDDR2 type		S4:0	S2:1 	NVM:2
++	unsigned int        dram_zq;		//do not need
++	unsigned int		dram_odt_en;
++
++	//control configuration
++	unsigned int		dram_para1;
++	unsigned int		dram_para2;
++
++	//timing configuration
++	unsigned int		dram_mr0;
++	unsigned int		dram_mr1;
++	unsigned int		dram_mr2;
++	unsigned int		dram_mr3;
++	unsigned int		dram_tpr0;	//DRAMTMG0
++	unsigned int		dram_tpr1;	//DRAMTMG1
++	unsigned int		dram_tpr2;	//DRAMTMG2
++	unsigned int		dram_tpr3;	//DRAMTMG3
++	unsigned int		dram_tpr4;	//DRAMTMG4
++	unsigned int		dram_tpr5;	//DRAMTMG5
++   	unsigned int		dram_tpr6;	//DRAMTMG8
++	//reserved for future use
++	unsigned int		dram_tpr7;
++	unsigned int		dram_tpr8;
++	unsigned int		dram_tpr9;
++	unsigned int		dram_tpr10;
++	unsigned int		dram_tpr11;
++	unsigned int		dram_tpr12;
++	unsigned int		dram_tpr13;
++
++};
++
++#endif
+--- /dev/null
++++ b/drivers/ram/sunxi/mctl_hal-sun20iw1p1.c
+@@ -0,0 +1,1771 @@
++// SPDX-License-Identifier: GPL-2.0+
++
++#include <common.h>
++#include <dm.h>
++#include <ram.h>
++#include <linux/delay.h>
++
++#include "dram_v2.h"
++#include "sdram.h"
++
++#define readl rv_readl
++#define writel rv_writel
++#include <asm/io.h>
++#undef readl
++#undef writel
++
++#define readl(x)	rv_readl((const volatile void __iomem *)(u64)(x))
++#define writel(x, v)	rv_writel(v, (volatile void __iomem *)(u64)(x))
++
++#if defined(CONFIG_SPL_BUILD)
++
++char* memcpy_self(char* dst, char* src, int len)
++{
++	int i;
++	for(i=0; i!=len; i++) {
++		dst[i] = src[i];
++	}
++	return dst;
++}
++
++void dram_vol_set(struct dram_para_t *para)
++{
++	int reg, vol = 0;
++
++	switch( para->dram_type ) {
++	case 2:  vol = 47; break;
++	case 3:  vol = 25; break;
++	default: vol = 0;
++	}
++vol = 25; // XXX
++	reg = readl(0x3000150);
++	reg &= ~(0xff00);
++	reg |= vol << 8;
++	reg &= ~(0x200000);
++	writel(0x3000150, reg);
++
++	udelay(1);
++}
++
++void paraconfig(unsigned int *para, unsigned int mask, unsigned int value)
++{
++	*para &= ~(mask);
++	*para |= value;
++}
++
++
++void dram_enable_all_master(void)
++{
++	writel(0x3102020, -1);
++	writel(0x3102024, 0xff);
++	writel(0x3102028, 0xffff);
++	udelay(10);
++}
++
++
++void dram_disable_all_master(void)
++{
++	writel(0x3102020, 1);
++	writel(0x3102024, 0);
++	writel(0x3102028, 0);
++	udelay(10);
++}
++
++
++void eye_delay_compensation(struct dram_para_t *para) // s1
++{
++	unsigned int val, ptr;
++
++	// DATn0IOCR, n =  0...7
++	for (ptr = 0x3103310; ptr != 0x3103334; ptr += 4) {
++		val  = readl(ptr);
++		val |= (para->dram_tpr11 << 9) & 0x1e00;
++		val |= (para->dram_tpr12 << 1) & 0x001e;
++		writel(ptr, val);
++	}
++
++	// DATn1IOCR, n =  0...7
++	for (ptr = 0x3103390; ptr != 0x31033b4; ptr += 4) {
++		val = readl(ptr);
++		val |= ((para->dram_tpr11 >> 4) << 9) & 0x1e00;
++		val |= ((para->dram_tpr12 >> 4) << 1) & 0x001e;
++		writel(ptr, val);
++	}
++
++	// PGCR0: assert AC loopback FIFO reset
++	val  = readl(0x3103100);
++	val &= 0xfbffffff;
++	writel(0x3103100, val);
++
++	// ??
++	val  = readl(0x3103334);
++	val |= ((para->dram_tpr11 >> 16) << 9) & 0x1e00;
++	val |= ((para->dram_tpr12 >> 16) << 1) & 0x001e;
++	writel(0x3103334, val);
++
++	val  = readl(0x3103338);
++	val |= ((para->dram_tpr11 >> 16) << 9) & 0x1e00;
++	val |= ((para->dram_tpr12 >> 16) << 1) & 0x001e;
++	writel(0x3103338, val);
++
++	val  = readl(0x31033b4);
++	val |= ((para->dram_tpr11 >> 20) << 9) & 0x1e00;
++	val |= ((para->dram_tpr12 >> 20) << 1) & 0x001e;
++	writel(0x31033b4, val);
++
++	val  = readl(0x31033b8);
++	val |= ((para->dram_tpr11 >> 20) << 9) & 0x1e00;
++	val |= ((para->dram_tpr12 >> 20) << 1) & 0x001e;
++	writel(0x31033b8, val);
++
++	val  = readl(0x310333c);
++	val |= ((para->dram_tpr11 >> 16) << 25) & 0x1e000000;
++	writel(0x310333c, val);
++
++	val  = readl(0x31033bc);
++	val |= ((para->dram_tpr11 >> 20) << 25) & 0x1e000000;
++	writel(0x31033bc, val);
++
++	// PGCR0: release AC loopback FIFO reset
++	val  = readl(0x3103100);
++	val |= 0x04000000;
++	writel(0x3103100, val);
++
++	udelay(1);
++
++	for (ptr = 0x3103240; ptr != 0x310327c; ptr += 4) {
++		val = readl(ptr);
++		val |= ((para->dram_tpr10 >> 4) << 8) & 0x0f00;
++		writel(ptr, val);
++	}
++
++	for (ptr = 0x3103228; ptr != 0x3103240; ptr += 4) {
++		val = readl(ptr);
++		val |= ((para->dram_tpr10 >> 4) << 8) & 0x0f00;
++		writel(ptr, val);
++	}
++
++	val  = readl(0x3103218);
++	val |= (para->dram_tpr10 << 8) & 0x0f00;
++	writel(0x3103218, val);
++
++	val  = readl(0x310321c);
++	val |= (para->dram_tpr10 << 8) & 0x0f00;
++	writel(0x310321c, val);
++
++	val  = readl(0x3103280);
++	val |= ((para->dram_tpr10 >> 12) << 8) & 0x0f00;
++	writel(0x3103280, val);
++}
++
++
++// Not used ??
++//
++void bit_delay_compensation(void)
++{
++	const unsigned int data0[44] = {
++		0, 1, 2, 3, 2, 3, 3, 3, 0, 0, 0,
++		6, 6, 6, 5, 5, 5, 5, 5, 0, 0, 0,
++		0, 2, 4, 2, 6, 5, 5, 5, 0, 0, 0,
++		3, 3, 3, 2, 2, 1, 1, 1, 0, 0, 0,
++	};
++	const unsigned int data1[44] = {
++		0, 1, 3, 3, 3, 3, 3, 4, 3, 3, 3,
++		3, 3, 4, 4, 3, 3, 3, 3, 3, 3, 3,
++		0, 3, 3, 1, 6, 6, 5, 6, 3, 3, 3,
++		5, 5, 6, 6, 4, 5, 3, 3, 3, 3, 3,
++	};
++
++	unsigned int *start = (unsigned int *)0x3102310; // DATX0IOCR
++	unsigned int *end   = (unsigned int *)0x3102510; // DATX0IOCR x + 4 * size
++	unsigned int *datxiocr;
++	unsigned int i, j, k, rval;
++
++	rval = readl(0x3102100) & 0x03ffffff;
++	writel(0x3102100, rval);
++
++	// Fill DATX0IOCR - DATX3IOCR, 11 registers per block, blocks 0x20 words apart
++	for(i = 0, datxiocr = start; datxiocr != end; i += 11, datxiocr += 0x20) {
++		for(j = 0, k = i; j != 11; j++, k++) {
++			rval  = readl((unsigned int)datxiocr[j]);
++			rval += data1[k] << 8;
++			rval += data0[k];
++			writel((unsigned int)datxiocr[j], rval);
++		}
++	}
++
++	rval = readl(0x3102100) | 0x04000000;
++	writel(0x3102100, rval);
++}
++
++// Not used ??
++//
++void set_master_priority_pad(struct dram_para_t *para)
++{
++	unsigned int val;
++
++	val = readl(0x310200c) & 0xfffff000;
++	val |= (para->dram_clk >> 1) - 1;
++	writel(0x310200c, val);
++
++	writel(0x3102200, 0x00001000);
++	writel(0x3102210, 0x01000009);
++	writel(0x3102214, 0x00500100);
++	writel(0x3102230, 0x0200000d);
++	writel(0x3102234, 0x00600100);
++	writel(0x3102240, 0x01000009);
++	writel(0x3102244, 0x00500100);
++	writel(0x3102260, 0x00640209);
++	writel(0x3102264, 0x00200040);
++	writel(0x3102290, 0x01000009);
++	writel(0x3102294, 0x00400080);
++	writel(0x3102470, 0);
++	writel(0x3102474, 0);
++
++	writel(0x31031c0, 0x0f802f05);
++	writel(0x31031c8, 0x0f0000ff);
++	writel(0x31031d0, 0x3f00005f);
++}
++
++int auto_cal_timing(unsigned int time, unsigned int freq)
++{
++	unsigned int t = time*freq;
++	return t/1000 + ( ((t%1000) != 0) ? 1 : 0);
++}
++
++// Main purpose of the auto_set_timing routine seems to be to calculate all
++// timing settings for the specific type of sdram used. Read together with
++// an sdram datasheet for context on the various variables.
++//
++void auto_set_timing_para(struct dram_para_t *para) // s5
++{
++	unsigned int   freq;	// s4
++	unsigned int   type;	// s8
++	unsigned int   tpr13;	// 80(sp)
++	unsigned int   reg_val;
++
++	unsigned char  tccd;	// 88(sp)
++	unsigned char  trrd;	// s7
++	unsigned char  trcd;	// s3
++	unsigned char  trc;	// s9
++	unsigned char  tfaw;	// s10
++	unsigned char  tras;	// s11
++	unsigned char  trp;	// 0(sp)
++	unsigned char  twtr;	// s1
++	unsigned char  twr;	// s6
++	unsigned char  trtp;	// 64(sp)
++	unsigned char  txp;	// a6
++	unsigned short trefi;	// s2
++	unsigned short trfc;	// a5 / 8(sp)
++
++	freq  = para->dram_clk;
++	type  = para->dram_type;
++	tpr13 = para->dram_tpr13;
++
++	//printf("type  = %d\n", type);
++	//printf("tpr13 = %p\n", tpr13);
++
++	if (para->dram_tpr13 & 0x2)
++	{
++		//dram_tpr0
++		tccd = ( (para->dram_tpr0 >> 21) & 0x7  ); // [23:21]
++		tfaw = ( (para->dram_tpr0 >> 15) & 0x3f ); // [20:15]
++		trrd = ( (para->dram_tpr0 >> 11) & 0xf  ); // [14:11]
++		trcd = ( (para->dram_tpr0 >>  6) & 0x1f ); // [10:6 ]
++		trc  = ( (para->dram_tpr0 >>  0) & 0x3f ); // [ 5:0 ]
++		//dram_tpr1
++		txp =  ( (para->dram_tpr1 >> 23) & 0x1f ); // [27:23]
++		twtr = ( (para->dram_tpr1 >> 20) & 0x7  ); // [22:20]
++		trtp = ( (para->dram_tpr1 >> 15) & 0x1f ); // [19:15]
++		twr =  ( (para->dram_tpr1 >> 11) & 0xf  ); // [14:11]
++		trp =  ( (para->dram_tpr1 >>  6) & 0x1f ); // [10:6 ]
++		tras = ( (para->dram_tpr1 >>  0) & 0x3f ); // [ 5:0 ]
++		//dram_tpr2
++		trfc  = ( (para->dram_tpr2 >> 12)& 0x1ff); // [20:12]
++		trefi = ( (para->dram_tpr2 >> 0) & 0xfff); // [11:0 ]
++	}
++	else {
++		unsigned int frq2 = freq >> 1; // s0
++
++		if (type == 3) {
++			// DDR3
++			trfc  = auto_cal_timing( 350, frq2);
++			trefi = auto_cal_timing(7800, frq2) / 32 + 1; // XXX
++			twr   = auto_cal_timing(   8, frq2);
++			trcd  = auto_cal_timing(  15, frq2);
++			twtr  = twr + 2; // + 2 ? XXX
++			if (twr < 2) twtr = 2;
++			twr = trcd;
++			if (trcd < 2) twr = 2;
++			if (freq <= 800) {
++				tfaw = auto_cal_timing(50, frq2);
++				trrd = auto_cal_timing(10, frq2);
++				if (trrd < 2) trrd = 2;
++				trc  = auto_cal_timing(53, frq2);
++				tras = auto_cal_timing(38, frq2);
++				txp  = trrd; // 10
++				trp  = trcd; // 15
++			}
++			else {
++				tfaw = auto_cal_timing(35, frq2);
++				trrd = auto_cal_timing(10, frq2);
++				if (trrd < 2) trrd = 2;
++				trcd = auto_cal_timing(14, frq2);
++				trc  = auto_cal_timing(48, frq2);
++				tras = auto_cal_timing(34, frq2);
++				txp  = trrd; // 10
++				trp  = trcd; // 14
++			}
++		}
++		else if (type == 2) {
++			// DDR2
++			tfaw  = auto_cal_timing(  50, frq2);
++			trrd  = auto_cal_timing(  10, frq2);
++			trcd  = auto_cal_timing(  20, frq2);
++			trc   = auto_cal_timing(  65, frq2);
++			twtr  = auto_cal_timing(   8, frq2);
++			trp   = auto_cal_timing(  15, frq2);
++			tras  = auto_cal_timing(  45, frq2);
++			trefi = auto_cal_timing(7800, frq2) / 32;
++			trfc  = auto_cal_timing( 328, frq2);
++			txp   = 2;
++			twr   = trp; // 15
++		}
++		else if (type == 6) {
++			// LPDDR2
++			tfaw  = auto_cal_timing(  50, frq2);
++			if (tfaw < 4) tfaw = 4;
++			trrd  = auto_cal_timing(  10, frq2);
++			if (trrd == 0) trrd = 1;
++			trcd  = auto_cal_timing(  24, frq2);
++			if (trcd < 2) trcd = 2;
++			trc   = auto_cal_timing(  70, frq2);
++			txp   = auto_cal_timing(   8, frq2);
++			if (txp == 0) {
++				txp  = 1;
++				twtr = 2;
++			}
++			else {
++				twtr = txp;
++				if (txp < 2) {
++					txp  = 2;
++					twtr = 2;
++				}
++			}
++			twr   = auto_cal_timing(  15, frq2);
++			if (twr < 2) twr = 2;
++			trp   = auto_cal_timing(  17, frq2);
++			tras  = auto_cal_timing(  42, frq2);
++			trefi = auto_cal_timing(3900, frq2) / 32;
++			trfc  = auto_cal_timing( 210, frq2);
++		}
++		else if (type == 7) {
++			// LPDDR3
++			tfaw  = auto_cal_timing(  50, frq2);
++			if (tfaw < 4) tfaw = 4;
++			trrd  = auto_cal_timing(  10, frq2);
++			if (trrd == 0) trrd = 1;
++			trcd  = auto_cal_timing(  24, frq2);
++			if (trcd < 2) trcd = 2;
++			trc   = auto_cal_timing(  70, frq2);
++			twtr   = auto_cal_timing(  8, frq2);
++			if (twtr < 2) twtr = 2;
++			twr   = auto_cal_timing(  15, frq2);
++			if (twr < 2) twr = 2;
++			trp   = auto_cal_timing(  17, frq2);
++			tras  = auto_cal_timing(  42, frq2);
++			trefi = auto_cal_timing(3900, frq2) / 32;
++			trfc  = auto_cal_timing( 210, frq2);
++			txp = twtr;
++		}
++		else {
++			// default
++			trfc  = 128;
++			trp   =   6;
++			trefi =  98;
++			txp   =  10;
++			twr   =   8;
++			twtr  =   3;
++			tras  =  14;
++			tfaw  =  16;
++			trc   =  20;
++			trcd  =   6;
++			trrd  =   3;
++		}
++		//assign the value back to the DRAM structure
++		tccd = 2;
++		trtp = 4; // not in .S ?
++		para->dram_tpr0 = (trc<<0) | (trcd<<6) | (trrd<<11) | (tfaw<<15) | (tccd<<21);
++		para->dram_tpr1 = (tras<<0) | (trp<<6) | (twr<<11) | (trtp<<15) | (twtr<<20) | (txp<<23);
++		para->dram_tpr2 = (trefi<<0) | (trfc<<12);
++	}
++
++	unsigned int tcksrx;	// t1
++	unsigned int tckesr;	// t4;
++	unsigned int trd2wr;	// t6
++	unsigned int trasmax;	// t3;
++	unsigned int twtp;	// s6 (was twr!)
++	unsigned int tcke;	// s8
++	unsigned int tmod;	// t0
++	unsigned int tmrd;	// t5
++	unsigned int tmrw;	// a1
++	unsigned int t_rdata_en;// a4 (was tcwl!)
++	unsigned int tcl;	// a0
++	unsigned int wr_latency;// a7
++	unsigned int tcwl;	// first a4, then a5
++	unsigned int mr3;	// s0
++	unsigned int mr2;	// t2
++	unsigned int mr1;	// s1
++	unsigned int mr0;	// a3
++	unsigned int dmr3;	// 72(sp)
++	//unsigned int trtp;	// 64(sp)
++	unsigned int dmr1;	// 56(sp)
++	unsigned int twr2rd;	// 48(sp)
++	unsigned int tdinit3;	// 40(sp)
++	unsigned int tdinit2;	// 32(sp)
++	unsigned int tdinit1;	// 24(sp)
++	unsigned int tdinit0;	// 16(sp)
++
++	dmr1 = para->dram_mr1;
++	dmr3 = para->dram_mr3;
++
++	switch (type) {
++
++	case 2:	// DDR2
++		{
++		trasmax = freq / 30;
++		if (freq < 409) {
++			tcl        = 3;
++			t_rdata_en = 1;
++			mr0        = 0x06a3;
++		}
++		else {
++			t_rdata_en = 2;
++			tcl        = 4;
++			mr0        = 0x0e73;
++		}
++		tmrd       =  2;
++		twtp       =  twr + 5;
++		tcksrx     =  5;
++		tckesr     =  4;
++		trd2wr     =  4;
++		tcke       =  3;
++		tmod       = 12;
++		wr_latency =  1;
++		mr3        =  0;
++		mr2        =  0;
++		tdinit0    = 200*freq + 1;
++		tdinit1    = 100*freq / 1000 + 1;
++		tdinit2    = 200*freq + 1;
++		tdinit3    =   1*freq + 1;
++		tmrw       =  0;
++		twr2rd     = twtr + 5;
++		tcwl       =  0;
++		mr1        = dmr1;
++		break;
++	}
++
++	case 3:	// DDR3
++		{
++		trasmax = freq / 30;
++		if (freq <= 800) {
++			mr0        = 0x1c70;
++			tcl        =  6;
++			wr_latency =  2;
++			tcwl       =  4;
++			mr2        = 24;
++		}
++		else {
++			mr0        = 0x1e14;
++			tcl        =  7;
++			wr_latency =  3;
++			tcwl       =  5;
++			mr2        = 32;
++		}
++
++		twtp    = tcwl + 2 + twtr;	// WL+BL/2+tWTR
++		trd2wr  = tcwl + 2 + twr;	// WL+BL/2+tWR
++		twr2rd  = tcwl + twtr;		// WL+tWTR
++
++		tdinit0 = 500*freq + 1;		// 500 us
++		tdinit1 = 360*freq / 1000 + 1;	// 360 ns
++		tdinit2 = 200*freq + 1;		// 200 us
++		tdinit3 =   1*freq + 1;		//   1 us
++
++		if (((tpr13>>2) & 0x03) == 0x01 || freq < 912) {
++			mr1    = dmr1;
++			t_rdata_en = tcwl;	// a5 <- a4
++			tcksrx = 5;
++			tckesr = 4;
++			trd2wr = 5;
++		}
++		else {
++			mr1    = dmr1;
++			t_rdata_en = tcwl;	// a5 <- a4
++			tcksrx = 5;
++			tckesr = 4;
++			trd2wr = 6;
++		}
++		tcke =  3; // not in .S ?
++		tmod = 12;
++		tmrd =  4;
++		tmrw =  0;
++		mr3  =  0;
++		break;
++		}
++
++	case 6:	// LPDDR2
++		{
++		trasmax	   = freq / 60;
++		mr3	   = dmr3;
++		twtp       =  twr + 5;
++		mr2	   =  6;
++		mr1	   =  5;
++		tcksrx     =  5;
++		tckesr	   =  5;
++		trd2wr	   = 10;
++		tcke	   =  2;
++		tmod	   =  5;
++		tmrd	   =  5;
++		tmrw	   =  3;
++		tcl        =  4;
++		wr_latency =  1;
++		t_rdata_en =  1;
++		tdinit0    = 200*freq + 1;
++		tdinit1    = 100*freq / 1000 + 1;
++		tdinit2    =  11*freq + 1;
++		tdinit3    =   1*freq + 1;
++		twr2rd	   = twtr + 5;
++		tcwl       =   2;
++		mr1	   = 195;
++		mr0	   =   0;
++		break;
++	}
++
++	case 7:	// LPDDR3
++		{
++		trasmax = freq / 60;
++		if (freq < 800) {
++			tcwl       =  4;
++			wr_latency =  3;
++			t_rdata_en =  6;
++			mr2        = 12;
++		}
++		else {
++			tcwl       =  3;
++			tcke	   =  6;
++			wr_latency =  2;
++			t_rdata_en =  5;
++			mr2        = 10;
++		}
++		twtp    = tcwl + 5;
++		tcl     = 7;
++		mr3     = dmr3;
++		tcksrx  = 5;
++		tckesr  = 5;
++		trd2wr  = 13;
++		tcke    = 3;
++		tmod    = 12;
++		tdinit0 = 400*freq + 1;
++		tdinit1 = 500*freq / 1000 + 1;
++		tdinit2 =  11*freq + 1;
++		tdinit3 =   1*freq + 1;
++		tmrd	= 5;
++		tmrw    = 5;
++		twr2rd  = tcwl + twtr + 5;
++		mr1	= 195;
++		mr0	= 0;
++		break;
++	}
++
++	default:
++		twr2rd		= 8;	// 48(sp)
++		tcksrx		= 4;	// t1
++		tckesr		= 3;	// t4
++		trd2wr		= 4;	// t6
++		trasmax		= 27;	// t3
++		twtp		= 12;	// s6
++		tcke		= 2;	// s8
++		tmod		= 6;	// t0
++		tmrd		= 2;	// t5
++		tmrw		= 0;	// a1
++		tcwl		= 3;	// a5
++		tcl		= 3;	// a0
++		wr_latency	= 1;	// a7
++		t_rdata_en	= 1;	// a4
++		mr3		= 0;	// s0
++		mr2		= 0;	// t2
++		mr1		= 0;	// s1
++		mr0		= 0;	// a3
++		tdinit3		= 0;	// 40(sp)
++		tdinit2		= 0;	// 32(sp)
++		tdinit1		= 0;	// 24(sp)
++		tdinit0		= 0;	// 16(sp)
++		break;
++	}
++	if (trtp < tcl - trp + 2) {
++		trtp = tcl - trp + 2;
++	}
++	trtp = 4;
++
++	// Update mode block when permitted
++	if ((para->dram_mr0 & 0xffff0000) == 0) para->dram_mr0 = mr0;
++	if ((para->dram_mr1 & 0xffff0000) == 0) para->dram_mr1 = mr1;
++	if ((para->dram_mr2 & 0xffff0000) == 0) para->dram_mr2 = mr2;
++	if ((para->dram_mr3 & 0xffff0000) == 0) para->dram_mr3 = mr3;
++
++	// Set mode registers
++	writel(0x3103030, para->dram_mr0);
++	writel(0x3103034, para->dram_mr1);
++	writel(0x3103038, para->dram_mr2);
++	writel(0x310303c, para->dram_mr3);
++	writel(0x310302c, (para->dram_odt_en >> 4) & 0x3); // ??
++
++	// Set dram timing DRAMTMG0 - DRAMTMG5
++	reg_val= (twtp<<24) | (tfaw<<16) | (trasmax<<8) | (tras<<0);
++	writel(0x3103058, reg_val);
++	reg_val= (txp<<16) | (trtp<<8) | (trc<<0);
++	writel(0x310305c, reg_val);
++	reg_val= (tcwl<<24) | (tcl<<16) | (trd2wr<<8) | (twr2rd<<0);
++	writel(0x3103060, reg_val);
++	reg_val= (tmrw<<16) | (tmrd<<12) | (tmod<<0);
++	writel(0x3103064, reg_val);
++	reg_val= (trcd<<24) | (tccd<<16) | (trrd<<8) | (trp<<0);
++	writel(0x3103068, reg_val);
++	reg_val= (tcksrx<<24) | (tcksrx<<16) | (tckesr<<8) | (tcke<<0);
++	writel(0x310306c, reg_val);
++
++	// Set two rank timing
++	reg_val  = readl(0x3103078);
++	reg_val &= 0x0fff0000;
++	reg_val |= (para->dram_clk < 800) ? 0xf0006600 : 0xf0007600;
++	reg_val |= 0x10;
++	writel(0x3103078, reg_val);
++
++	// Set phy interface time PITMG0, PTR3, PTR4
++	reg_val = (0x2<<24) | (t_rdata_en<<16) | (0x1<<8) | (wr_latency<<0);
++	writel(0x3103080, reg_val);
++	writel(0x3103050, ((tdinit0<<0)|(tdinit1<<20)));
++	writel(0x3103054, ((tdinit2<<0)|(tdinit3<<20)));
++
++	// Set refresh timing and mode
++	reg_val = (trefi<<16) | (trfc<<0);
++	writel(0x3103090, reg_val);
++	reg_val = 0x0fff0000 & (trefi<<15);
++	writel(0x3103094, reg_val);
++}
++
++// Not used ?
++//
++void ccm_get_sscg(void)
++{
++	// NOTE: function is present in the assembly, but was not translated.
++}
++
++// Not used ?
++//
++void ccm_set_pll_sscg(void)
++{
++	// NOTE: function is present in the assembly, but was not translated.
++}
++
++// Purpose of this routine seems to be to initialize the PLL driving
++// the MBUS and sdram.
++//
++int ccm_set_pll_ddr_clk(int index, struct dram_para_t *para)
++{
++	unsigned int val, clk, n;
++
++	clk = (para->dram_tpr13 & (1 << 6)) ? para->dram_tpr9
++					    : para->dram_clk;
++
++	// set VCO clock divider
++	n = (clk * 2) / 24;
++	val = readl(0x2001010);
++	val &= 0xfff800fc;   // clear dividers
++	val |= (n - 1) << 8; // set PLL division
++	val |= 0xc0000000;   // enable PLL and LDO
++	writel(0x2001010, val);
++
++	// Restart PLL locking
++	val &= 0xdfffffff;   // disbable lock
++	val |= 0xc0000000;   // enable PLL and LDO
++	writel(0x2001010, val);
++	val |= 0xe0000000;   // re-enable lock
++	writel(0x2001010, val);
++
++	// wait for PLL to lock
++	while ((readl(0x2001010) & 0x10000000) == 0) {;}
++
++	udelay(20);
++
++	// enable PLL output
++	val = readl(0x2001000);
++	val |= 0x08000000;
++	writel(0x2001000, val);
++
++	// turn clock gate on
++	val = readl(0x2001800);
++	val &= 0xfcfffcfc; // select DDR clk source, n=1, m=1
++	val |= 0x80000000; // turn clock on
++	writel(0x2001800, val);
++
++	return n * 24;
++}
++
++// Main purpose of sys_init seems to be to initalise the clocks for
++// the sdram controller.
++//
++void mctl_sys_init(struct dram_para_t *para)
++{
++	unsigned int val;
++
++	// s1 = 0x02001000
++
++	// assert MBUS reset
++	val  = readl(0x2001540);
++	val &= 0xbfffffff;
++	writel(0x2001540, val);
++
++	// turn off sdram clock gate, assert sdram reset
++	val  = readl(0x200180c);
++	val &= 0xfffffffe;
++	writel(0x200180c, val);
++	val &= 0xfffefffe;
++	writel(0x200180c, val);
++
++	// turn of bit 30 [??]
++	val  = readl(0x2001800);
++	writel(0x2001800, val & 0xbfffffff);
++	// and toggle dram clock gating off + trigger update
++	val &= 0x7fffffff;
++	writel(0x2001800, val);
++	val |= 0x08000000;
++	writel(0x2001800, val);
++	udelay(10);
++
++	// set ddr pll clock
++	val = ccm_set_pll_ddr_clk(0, para);
++	para->dram_clk = val >> 1;
++	udelay(100);
++	dram_disable_all_master();
++
++	// release sdram reset
++	val  = readl(0x200180c);
++	val |= 0x00010000;
++	writel(0x200180c, val);
++
++	// release MBUS reset
++	val  = readl(0x2001540);
++	val |= 0x40000000;
++	writel(0x2001540, val);
++
++	// turn bit 30 back on [?]
++	val  = readl(0x2001800);
++	val |= 0x40000000;
++	writel(0x2001800, val);
++	udelay(5);
++
++	// turn on sdram clock gate
++	val  = readl(0x200180c);
++	val |= 0x0000001; // (1<<0)
++	writel(0x200180c, val);
++
++	// turn dram clock gate on, trigger sdr clock update
++	val  = readl(0x2001800);
++	val |= 0x80000000;
++	writel(0x2001800, val);
++	val |= 0x88000000;
++	writel(0x2001800, val);
++	udelay(5);
++
++	// mCTL clock enable
++	writel(0x310300c, 0x00008000);
++	udelay(10);
++}
++
++// The main purpose of this routine seems to be to copy an address configuration
++// from the dram_para1 and dram_para2 fields to the PHY configuration registers
++// (0x3102000, 0x3102004).
++//
++void mctl_com_init(struct dram_para_t *para)
++{
++	unsigned int val, end, ptr;
++	int i;
++
++	// purpose ??
++	val = readl(0x3102008) & 0xffffc0ff;
++	val |= 0x2000;
++	writel(0x3102008, val);
++
++	// Set sdram type and word width
++	val  = readl(0x3102000) & 0xff000fff;
++	val |= (para->dram_type &0x7) << 16;			// DRAM type
++	val |= (~para->dram_para2 & 0x1) << 12;			// DQ width
++	if((para->dram_type) != 6 && (para->dram_type) != 7) {
++		val |= ((para->dram_tpr13 >> 5) & 0x1) << 19;	// 2T or 1T
++		val |= 0x400000;
++	}
++	else {
++		val |= 0x480000;	// type 6 and 7 must use 1T
++	}
++	writel(0x3102000, val);
++
++	// init rank / bank / row for single/dual or two different ranks
++	val = para->dram_para2;
++	end = ((val & 0x100) && (((val >> 12) & 0xf) != 1)) ? 32 : 16;
++	ptr = 0x3102000;
++
++	for (i = 0 ; i != end; i += 16) {
++
++		val = readl(ptr) & 0xfffff000;
++
++		val |=   (para->dram_para2 >> 12) & 0x3;		   // rank
++		val |=  ((para->dram_para1 >> (i + 12)) << 2) & 0x4;	   // bank - 2
++		val |= (((para->dram_para1 >> (i +  4)) - 1) << 4) & 0xff; // row - 1
++
++		// convert from page size to column addr width - 3
++		switch ((para->dram_para1 >> i) & 0xf) {
++		case 8:  val |= 0xa00; break;
++		case 4:  val |= 0x900; break;
++		case 2:  val |= 0x800; break;
++		case 1:  val |= 0x700; break;
++		default: val |= 0x600; break;
++		}
++		writel(ptr, val);
++		ptr += 4;
++	}
++
++	// set ODTMAP based on number of ranks in use
++	val = (readl(0x3102000) & 0x1) ? 0x303 : 0x201;
++	writel(0x3103120, val);
++
++	// set mctl reg 3c4 to zero when using half DQ
++	if (para->dram_para2 & (1 << 0)) {
++		writel(0x31033c4, 0);
++	}
++
++	// purpose ??
++	if (para->dram_tpr4) {
++		val  = readl(0x3102000);
++		val |= (para->dram_tpr4 << 25) & 0x06000000;
++		writel(0x3102000, val);
++
++		val  = readl(0x3102004);
++		val |= ((para->dram_tpr4 >> 2) << 12) & 0x001ff000;
++		writel(0x3102004, val);
++	}
++}
++
++// This routine seems to have several remapping tables for 22 lines.
++// It is unclear which lines are being remapped. It seems to pick
++// table cfg7 for the Nezha board.
++//
++void mctl_phy_ac_remapping(struct dram_para_t *para)
++{
++	char cfg0[] = {  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
++			 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0 };
++	static char cfg1[] = {  1,  9,  3,  7,  8, 18,  4, 13,  5,  6, 10,
++			 2, 14, 12,  0,  0, 21, 17, 20, 19, 11, 22 };
++	static char cfg2[] = {  4,  9,  3,  7,  8, 18,  1, 13,  2,  6, 10,
++			 5, 14, 12,  0,  0, 21, 17, 20, 19, 11, 22 };
++	static char cfg3[] = {  1,  7,  8, 12, 10, 18,  4, 13,  5,  6,  3,
++			 2,  9,  0,  0,  0, 21, 17, 20, 19, 11, 22 };
++	static char cfg4[] = {  4, 12, 10,  7,  8, 18,  1, 13,  2,  6,  3,
++			 5,  9,  0,  0,  0, 21, 17, 20, 19, 11, 22 };
++	static char cfg5[] = { 13,  2,  7,  9, 12, 19,  5,  1,  6,  3,  4,
++			 8, 10,  0,  0,  0, 21, 22, 18, 17, 11, 20 };
++	static char cfg6[] = {  3, 10,  7, 13,  9, 11,  1,  2,  4,  6,  8,
++			 5, 12,  0,  0,  0, 20,  1,  0, 21, 22, 17 };
++	static char cfg7[] = {  3,  2,  4,  7,  9,  1, 17, 12, 18, 14, 13,
++			 8, 15,  6, 10,  5, 19, 22, 16, 21, 20, 11 };
++
++	unsigned int fuse, val;
++
++	// read SID info @ 0x228
++	fuse = (readl(0x3002228) >> 8) & 0x4;
++	printf("ddr_efuse_type: 0x%x\n", fuse);
++
++	if ((para->dram_tpr13 >> 18) & 0x3) {
++		memcpy_self(cfg0, cfg7, 22);
++	}
++	else {
++		switch (fuse) {
++		case  8: memcpy_self(cfg0, cfg2, 22); break;
++		case  9: memcpy_self(cfg0, cfg3, 22); break;
++		case 10: memcpy_self(cfg0, cfg5, 22); break;
++		case 11: memcpy_self(cfg0, cfg4, 22); break;
++		default:
++		case 12: memcpy_self(cfg0, cfg1, 22); break;
++		case 13:
++		case 14: break;
++		}
++	}
++	if (para->dram_type == 2) {
++		if (fuse == 15) return;
++		memcpy_self(cfg0, cfg6, 22);
++	}
++	if ( para->dram_type == 2 || para->dram_type == 3) {
++
++		val = (cfg0[ 4] << 25) | (cfg0[ 3] << 20) | (cfg0[ 2] << 15) |
++		      (cfg0[ 1] << 10) | (cfg0[ 0] <<  5);
++		writel(0x3102500, val);
++
++		val = (cfg0[10] << 25) | (cfg0[ 9] << 20) | (cfg0[ 8] << 15) |
++		      (cfg0[ 7] << 10) | (cfg0[ 6] <<  5) |  cfg0[ 5];
++		writel(0x3102504, val);
++
++		val =                    (cfg0[15] << 20) | (cfg0[14] << 15) |
++		      (cfg0[13] << 10) | (cfg0[12] <<  5) |  cfg0[11];
++		writel(0x3102508, val);
++
++		val = (cfg0[21] << 25) | (cfg0[20] << 20) | (cfg0[19] << 15) |
++		      (cfg0[18] << 10) | (cfg0[17] <<  5) |  cfg0[16];
++		writel(0x310250c, val);
++
++		val = (cfg0[ 4] << 25) | (cfg0 [3] << 20) | (cfg0[2] << 15) |
++		      (cfg0[ 1] << 10) | (cfg0 [0] <<  5) |  1;
++		writel(0x3102500, val);
++	}
++}
++
++// Init the controller channel. The key part is placing commands in the main
++// command register (PIR, 0x3103000) and checking command status (PGSR0, 0x3103010).
++//
++unsigned int mctl_channel_init(unsigned int ch_index, struct dram_para_t *para)
++{
++	unsigned int val, dqs_gating_mode;
++
++	dqs_gating_mode = (para->dram_tpr13 >> 2) & 0x3;
++
++	// set DDR clock to half of CPU clock
++	val  = readl(0x310200c) & 0xfffff000;
++	val |= (para->dram_clk >> 1 ) - 1;
++	writel(0x310200c, val);
++
++	// MRCTRL0 nibble 3 undocumented
++	val  = readl(0x3103108) & 0xfffff0ff;
++	val |= 0x300;
++	writel(0x3103108, val);
++
++	// DX0GCR0
++	val = readl(0x3103344) & 0xffffffcf;
++	val |= ((~para->dram_odt_en) << 5) & 0x20;
++	if (para->dram_clk > 672) {
++		val &= 0xffff09f1;
++		val |= 0x00000400;
++	}
++	else {
++		val &= 0xffff0ff1;
++	}
++	writel(0x3103344, val);
++
++	// DX1GCR0
++	val  = readl(0x31033c4) & 0xffffffcf;
++	val |= ((~para->dram_odt_en) << 5) & 0x20;
++	if (para->dram_clk > 672) {
++		val &= 0xffff09f1;
++		val |= 0x00000400;
++	}
++	else {
++		val &= 0xffff0ff1;
++	}
++	writel(0x31033c4, val);
++
++	// 0x3103208 undocumented
++	val  = readl(0x3103208);
++	val |= 0x2;
++	writel(0x3103208, val);
++
++	eye_delay_compensation(para);
++
++	//set PLL SSCG ?
++	//
++	val  = readl(0x3103108);
++	if (dqs_gating_mode == 1) {
++
++		val &= ~(0xc0);
++		writel(0x3103108, val);
++
++		val  = readl(0x31030bc);
++		val &= 0xfffffef8;
++		writel(0x31030bc, val);
++	}
++	else if (dqs_gating_mode == 2) {
++
++		val &= ~(0xc0);
++		val |= 0x80;
++		writel(0x3103108, val);
++
++		val  = readl(0x31030bc);
++		val &= 0xfffffef8;
++		val |= ((para->dram_tpr13 >> 16) & 0x1f) - 2;
++		val |= 0x100;
++		writel(0x31030bc, val);
++
++		val  = readl(0x310311c) & 0x7fffffff;
++		val |= 0x08000000;
++		writel(0x310311c, val);
++	}
++	else {
++		val &= ~(0x40);
++		writel(0x3103108, val);
++
++		udelay(10);
++
++		val  = readl(0x3103108);
++		val |= 0xc0;
++		writel(0x3103108, val);
++	}
++
++	if (para->dram_type == 6 || para->dram_type == 7) {
++		val = readl(0x310311c);
++		if (dqs_gating_mode == 1) {
++			val &= 0xf7ffff3f;
++			val |= 0x80000000;
++		}
++		else {
++			val &= 0x88ffffff;
++			val |= 0x22000000;
++		}
++		writel(0x310311c, val);
++	}
++
++	val  = readl(0x31030c0);
++	val &= 0xf0000000;
++	val |= (para->dram_para2 & (1 << 12)) ? 0x03000001 : 0x01000007; // 0x01003087 XXX
++	writel(0x31030c0, val);
++
++	if (readl(0x70005d4) & (1 << 16)) {
++		val = readl(0x7010250);
++		val &= 0xfffffffd;
++		writel(0x7010250, val);
++
++		udelay(10);
++	}
++
++	// Set ZQ config
++	val  = readl(0x3103140) & 0xfc000000;
++	val |= para->dram_zq & 0x00ffffff;
++	val |= 0x02000000;
++	writel(0x3103140, val);
++
++	// Initialise DRAM controller
++	if (dqs_gating_mode == 1) {
++		writel(0x3103000, 0x52); // prep PHY reset + PLL init + z-cal
++		writel(0x3103000, 0x53); // Go
++
++		while ((readl(0x3103010) & 0x1) == 0) {;} // wait for IDONE
++		udelay(10);
++
++		// 0x520 = prep DQS gating + DRAM init + d-cal
++		val = (para->dram_type == 3) ? 0x5a0	// + DRAM reset
++					     : 0x520;
++	}
++	else {
++		if ((readl(0x70005d4) & (1 << 16)) == 0) {
++			// prep DRAM init + PHY reset + d-cal + PLL init + z-cal
++			val = (para->dram_type == 3) ? 0x1f2	// + DRAM reset
++						     : 0x172;
++		}
++		else {
++			// prep PHY reset + d-cal + z-cal
++			val = 0x62;
++		}
++	}
++
++	writel(0x3103000, val); // Prep
++	val |= 1;
++	writel(0x3103000, val); // Go
++
++	udelay(10);
++	while ((readl(0x3103010) & 0x1) == 0) {;} // wait for IDONE
++
++	if (readl(0x70005d4) & (1 << 16)) {
++
++		val  = readl(0x310310c);
++		val &= 0xf9ffffff;
++		val |= 0x04000000;
++		writel(0x310310c, val);
++
++		udelay(10);
++
++		val  = readl(0x3103004);
++		val |= 0x1;
++		writel(0x3103004, val);
++
++		while ((readl(0x3103018) & 0x7) != 0x3) {;}
++
++		val  = readl(0x7010250);
++		val &= 0xfffffffe;
++		writel(0x7010250, val);
++
++		udelay(10);
++
++		val  = readl(0x3103004);
++		val &= 0xfffffffe;
++		writel(0x3103004, val);
++
++		while ((readl(0x3103018) & 0x7) != 0x1) {;}
++
++		udelay(15);
++
++		if (dqs_gating_mode == 1) {
++
++			val  = readl(0x3103108);
++			val &= 0xffffff3f;
++			writel(0x3103108, val);
++
++			val  = readl(0x310310c);
++			val &= 0xf9ffffff;
++			val |= 0x02000000;
++			writel(0x310310c, val);
++
++			udelay(1);
++			writel(0x3103000, 0x401);
++
++			while ((readl(0x3103010) & 0x1) == 0) {;}
++		}
++	}
++
++	// Check for training error
++	val = readl(0x3103010);
++	if (((val >> 20) & 0xff) && (val & 0x100000)) {
++		printf("ZQ calibration error, check external 240 ohm resistor.\n");
++		return 0;
++	}
++
++	// STATR = Zynq STAT? Wait for status 'normal'?
++	while ((readl(0x3103018) & 0x1) == 0) {;}
++
++	val  = readl(0x310308c);
++	val |= 0x80000000;
++	writel(0x310308c, val);
++
++	udelay(10);
++
++	val  = readl(0x310308c);
++	val &= 0x7fffffff;
++	writel(0x310308c, val);
++
++	udelay(10);
++
++	val  = readl(0x3102014);
++	val |= 0x80000000;
++	writel(0x3102014, val);
++
++	udelay(10);
++
++	val  = readl(0x310310c);
++	val &= 0xf9ffffff;
++	writel(0x310310c, val);
++
++	if (dqs_gating_mode == 1) {
++		val  = readl(0x310311c);
++		val &= 0xffffff3f;
++		val |= 0x00000040;
++		writel(0x310311c, val);
++	}
++	return 1;
++}
++
++// The below routine reads the dram config registers and extracts
++// the number of address bits in each rank available. It then calculates
++// total memory size in MB.
++//
++int DRAMC_get_dram_size(void)
++{
++	unsigned int rval, temp, size0, size1;
++
++	rval = readl(0x3102000);	// MC_WORK_MODE0
++
++	temp  = (rval>>8) & 0xf;	// page size - 3
++	temp += (rval>>4) & 0xf;	// row width - 1
++	temp += (rval>>2) & 0x3;	// bank count - 2
++	temp -= 14;			// 1MB = 20 bits, minus above 6 = 14
++	size0 = 1 << temp;
++
++	temp = rval & 0x3;		// rank count = 0? -> done
++	if (temp == 0) {
++		return size0;
++	}
++
++	rval = readl(0x3102004);	// MC_WORK_MODE1
++
++	temp = rval & 0x3;
++	if (temp == 0) {		// two identical ranks
++		return 2 * size0;
++	}
++
++	temp  = (rval>>8) & 0xf;	// page size - 3
++	temp += (rval>>4) & 0xf;	// row width - 1
++	temp += (rval>>2) & 0x3;	// bank number - 2
++	temp -= 14;			// 1MB = 20 bits, minus above 6 = 14
++	size1 = 1 << temp;
++
++	return size0 + size1;		// add size of each rank
++}
++
++// The below routine reads the command status register to extract
++// DQ width and rank count. This follows the DQS training command in
++// channel_init. If error bit 22 is reset, we have two ranks and full DQ.
++// If there was an error, figure out whether it was half DQ, single rank,
++// or both. Set bit 12 and 0 in dram_para2 with the results.
++//
++int dqs_gate_detect(struct dram_para_t *para)
++{
++	unsigned int rval, dx0, dx1;
++
++	if (readl(0x3103010) & (1 << 22)) {
++
++		dx0 = (readl(0x3103348) >> 24) & 0x3;
++		dx1 = (readl(0x31033c8) >> 24) & 0x3;
++
++		if (dx0 == 2) {
++			rval  = para->dram_para2;
++			rval &= 0xffff0ff0;
++			if (dx0 != dx1) {
++				rval |= 0x1;
++				para->dram_para2 = rval;
++				printf("[AUTO DEBUG] single rank and half DQ!\n");
++				return 1;
++			}
++			para->dram_para2 = rval;
++			printf("[AUTO DEBUG] single rank and full DQ!\n");
++			return 1;
++		}
++		else if (dx0 == 0) {
++			rval  = para->dram_para2;
++			rval &= 0xfffffff0;
++			rval |= 0x00001001;
++			para->dram_para2 = rval;
++			printf("[AUTO DEBUG] dual rank and half DQ!\n");
++			return 1;
++		}
++		else {
++			if (para->dram_tpr13 & (1 << 29)) {
++				printf("DX0 state:%d\n", dx0);
++				printf("DX1 state:%d\n", dx1);
++			}
++			return 0;
++		}
++	}
++	else {
++		rval  = para->dram_para2;
++		rval &= 0xfffffff0;
++		rval |= 0x00001000;
++		para->dram_para2 = rval;
++		printf("[AUTO DEBUG] two rank and full DQ!\n");
++		return 1;
++	}
++}
++
++
++#define SDRAM_BASE	((unsigned int *)0x40000000)
++#define uint		unsigned int
++
++int dramc_simple_wr_test(uint mem_mb, int len)
++{
++	unsigned int  offs = (mem_mb >> 1) << 18; // half of memory size
++	unsigned int  patt1 = 0x01234567;
++	unsigned int  patt2 = 0xfedcba98;
++	unsigned int *addr, v1, v2, i;
++
++	addr = SDRAM_BASE;
++	for (i = 0; i != len; i++, addr++) {
++		writel(addr,        patt1 + i);
++		writel(addr + offs, patt2 + i);
++	}
++
++	addr = SDRAM_BASE;
++	for (i = 0; i != len; i++) {
++		v1 = readl(addr+i);
++		v2 = patt1 + i;
++		if (v1 != v2) {
++			printf("DRAM simple test FAIL.\n");
++			printf("%x != %x at address %p\n", v1, v2, addr+i);
++			return 1;
++		}
++		v1 = readl(addr+offs+i);
++		v2 = patt2 + i;
++		if (v1 != v2) {
++			printf("DRAM simple test FAIL.\n");
++			printf("%x != %x at address %p\n", v1, v2, addr+offs+i);
++			return 1;
++		}
++	}
++	printf("DRAM simple test OK.\n");
++	return 0;
++}
++
++// Set the Vref mode for the controller
++//
++void mctl_vrefzq_init(struct dram_para_t *para)
++{
++	unsigned int val;
++
++	if ((para->dram_tpr13 & (1 << 17)) == 0) {
++		val  = readl(0x3103110) & 0x80808080;	// IOCVR0
++		val |= para->dram_tpr5;
++		writel(0x3103110, val);
++
++		if ((para->dram_tpr13 & (1 << 16)) == 0) {
++			val  = readl(0x3103114) & 0xffffff80; // IOCVR1
++			val |= para->dram_tpr6 & 0x7f;
++			writel(0x3103114, val);
++		}
++	}
++}
++
++// Perform an init of the controller. This is actually done 3 times. The first
++// time to establish the number of ranks and DQ width. The second time to
++// establish the actual ram size. The third time is final one, with the final
++// settings.
++//
++int mctl_core_init(struct dram_para_t *para)
++{
++	mctl_sys_init(para);
++	mctl_vrefzq_init(para);
++	mctl_com_init(para);
++	mctl_phy_ac_remapping(para);
++	auto_set_timing_para(para);
++	return mctl_channel_init(0, para);
++}
++
++
++#define RAM_BASE	(0x40000000)
++
++// Autoscan sizes a dram device by cycling through address lines and figuring
++// out if it is connected to a real address line, or if the address is a mirror.
++// First the column and bank bit allocations are set to low values (2 and 9 address
++// lines. Then a maximum allocation (16 lines) is set for rows and this is tested.
++// Next the BA2 line is checked. This seems to be placed above the column, BA0-1 and
++// row addresses. Finally, the column address is allocated 13 lines and these are
++// tested. The results are placed in dram_para1 and dram_para2.
++//
++int auto_scan_dram_size(struct dram_para_t *para) // s7
++{
++	unsigned int	rval, i, j, rank, maxrank, offs, mc_work_mode;
++	unsigned int	chk, ptr, shft, banks;
++
++	if (mctl_core_init(para) == 0) {
++		printf("[ERROR DEBUG] DRAM initialisation error : 0!\n");
++		return 0;
++	}
++
++	maxrank = (para->dram_para2 & 0xf000) ? 2 : 1;
++	mc_work_mode = 0x3102000;
++	offs = 0;
++
++	// write test pattern
++	for (i = 0, ptr = RAM_BASE; i < 64; i++, ptr += 4) {
++		writel(ptr, (i & 1) ? ptr : ~ptr);
++	}
++
++	for (rank = 0; rank < maxrank; ) {
++
++		// Set row mode
++		rval  = readl(mc_work_mode);
++		rval &= 0xfffff0f3;
++		rval |= 0x000006f0;
++		writel(mc_work_mode, rval);
++		while (readl(mc_work_mode) != rval);
++
++		// Scan per address line, until address wraps (i.e. see shadow)
++		for(i = 11; i < 17; i++) {
++			chk = RAM_BASE + (1 << (i + 11));
++			ptr = RAM_BASE;
++			for (j = 0; j < 64; j++) {
++				if (readl(chk) != ((j & 1) ? ptr : ~ptr))
++					goto out1;
++				ptr += 4;
++				chk += 4;
++			}
++			break;
++		out1: ;
++		}
++		if (i > 16) i = 16;
++		printf("[AUTO DEBUG] rank %d row = %d\n", rank, i);
++
++		// Store rows in para 1
++		shft = 4 + offs;
++		rval = para->dram_para1;
++		rval &= ~(0xff << shft);
++		rval |= i << shft;
++		para->dram_para1 = rval;
++
++		if (rank == 1) {
++			// Set bank mode for rank0
++			rval  = readl(0x3102000);
++			rval &= 0xfffff003;
++			rval |= 0x000006a4;
++			writel(0x3102000, rval);
++		}
++
++		// Set bank mode for current rank
++		rval  = readl(mc_work_mode);
++		rval &= 0xfffff003;
++		rval |= 0x000006a4;
++		writel(mc_work_mode, rval);
++		while (readl(mc_work_mode) != rval);
++
++		// Test if bit A23 is BA2 or mirror XXX A22?
++		chk = RAM_BASE + (1 << 22);
++		ptr = RAM_BASE;
++		for (i = 0, j = 0; i < 64; i++) {
++			if (readl(chk) != ((i & 1) ? ptr : ~ptr)) {
++				j = 1;
++				break;
++			}
++			ptr += 4;
++			chk += 4;
++		}
++		banks = (j + 1) << 2; // 4 or 8
++		printf("[AUTO DEBUG] rank %d bank = %d\n", rank, banks);
++
++		// Store banks in para 1
++		shft = 12 + offs;
++		rval  = para->dram_para1;
++		rval &= ~(0xf << shft);
++		rval |= j << shft;
++		para->dram_para1 = rval;
++
++		if (rank == 1) {
++			// Set page mode for rank0
++			rval  = readl(0x3102000);
++			rval &= 0xfffff003;
++			rval |= 0x00000aa0;
++			writel(0x3102000, rval);
++		}
++
++		// Set page mode for current rank
++		rval  = readl(mc_work_mode);
++		rval &= 0xfffff003;
++		rval |= 0x00000aa0;
++		writel(mc_work_mode, rval);
++		while (readl(mc_work_mode) != rval);
++
++		// Scan per address line, until address wraps (i.e. see shadow)
++		for(i = 9; i < 14; i++) {
++			chk = RAM_BASE + (1 << i);
++			ptr = RAM_BASE;
++			for (j = 0; j < 64; j++) {
++				if (readl(chk) != ((j & 1) ? ptr : ~ptr))
++					goto out2;
++				ptr += 4;
++				chk += 4;
++			}
++			break;
++		out2:;
++		}
++		if (i > 13) i = 13;
++		int pgsize = (i==9) ? 0 : (1 << (i-10));
++		printf("[AUTO DEBUG] rank %d page size = %d KB\n", rank, pgsize);
++
++		// Store page size
++		shft = offs;
++		rval  = para->dram_para1;
++		rval &= ~(0xf << shft);
++		rval |= pgsize << shft;
++		para->dram_para1 = rval;
++
++		// Move to next rank
++		rank++;
++		if (rank != maxrank) {
++			if (rank == 1) {
++				rval  = readl(0x3202000); // MC_WORK_MODE
++				rval &= 0xfffff003;
++				rval |= 0x000006f0;
++				writel(0x3202000, rval);
++
++				rval  = readl(0x3202004); // MC_WORK_MODE2
++				rval &= 0xfffff003;
++				rval |= 0x000006f0;
++				writel(0x3202004, rval);
++			}
++			offs += 16; // store rank1 config in upper half of para1
++			mc_work_mode +=  4; // move to MC_WORK_MODE2
++		}
++	}
++	if (maxrank == 2) {
++		para->dram_para2 &= 0xfffff0ff;
++		// note: rval is equal to para->dram_para1 here
++		if ((rval & 0xffff) == ((rval >> 16) & 0xffff)) {
++			printf("rank1 config same as rank0\n");
++		}
++		else {
++			para->dram_para2 |= 0x00000100;
++			printf("rank1 config different from rank0\n");
++		}
++	}
++	return 1;
++}
++
++// This routine sets up parameters with dqs_gating_mode equal to 1 and two
++// ranks enabled. It then configures the core and tests for 1 or 2 ranks and
++// full or half DQ width. it then resets the parameters to the original values.
++// dram_para2 is updated with the rank & width findings.
++//
++int auto_scan_dram_rank_width(struct dram_para_t *para)
++{
++	unsigned int s1 = para->dram_tpr13;
++	unsigned int s2 = para->dram_para1;
++	unsigned int v;
++
++	para->dram_para1 = 0x00b000b0;
++	v = (para->dram_para2 & 0xfffffff0) | 0x1000;
++	para->dram_para2 = v;
++
++	v = (s1 & 0xfffffff7) | 0x5; // set DQS probe mode
++	para->dram_tpr13 = v;
++
++	mctl_core_init(para);
++	if (readl(0x3103010) & (1 << 20)) {
++		return 0;
++	}
++	if (dqs_gate_detect(para) == 0) {
++		return 0;
++	}
++
++	para->dram_tpr13 = s1;
++	para->dram_para1 = s2;
++	return 1;
++}
++
++// This routine determines the sdram topology. It first establishes the number
++// of ranks and the DQ width. Then it scans the sdram address lines to establish
++// the size of each rank. It then updates dram_tpr13 to reflect that the sizes
++// are now known: a re-init will not repeat the autoscan.
++//
++int auto_scan_dram_config(struct dram_para_t *para)
++{
++	if (((para->dram_tpr13 & (1 << 14)) == 0) &&
++	    (auto_scan_dram_rank_width(para) == 0))
++	{
++		printf("[ERROR DEBUG] auto scan dram rank & width failed !\n");
++		return 0;
++	}
++	if (((para->dram_tpr13 & (1 << 0)) == 0)  &&
++	    (auto_scan_dram_size(para) == 0 ))
++	{
++		printf("[ERROR DEBUG] auto scan dram size failed !\n");
++		return 0;
++	}
++	if ((para->dram_tpr13 & (1 << 15)) == 0) {
++		para->dram_tpr13 |= 0x6003;
++	}
++	return 1;
++}
++
++
++signed int init_DRAM(int type, struct dram_para_t *para) // s0
++{
++	int rc, mem_size;
++
++	// Test ZQ status
++	if (para->dram_tpr13 & (1 << 16)) {
++		printf("DRAM only have internal ZQ!!\n");
++		writel(0x3000160, readl(0x3000160) |  0x100);
++		writel(0x3000168, 0);
++		udelay(10);
++	}
++	else {
++		writel(0x7010254, 0);
++		writel(0x3000160, readl(0x3000160) & ~0x003);
++		udelay(10);
++		writel(0x3000160, readl(0x3000160) & ~0x108);
++		udelay(10);
++		writel(0x3000160, readl(0x3000160) |  0x001);
++		udelay(20);
++		printf("ZQ value = 0x%x***********\n", readl(0x3000172));
++	}
++
++	// Set voltage
++	dram_vol_set(para);
++
++	// Set SDRAM controller auto config
++	if ( (para->dram_tpr13 & 0x1)==0 ) {
++		if ( auto_scan_dram_config(para)==0 ) {
++			return 0;
++		}
++	}
++
++	// Print header message (too late)
++	printf("DRAM BOOT DRIVE INFO: %s\n", "V0.24");
++	printf("DRAM CLK = %d MHz\n", para->dram_clk);
++	printf("DRAM Type = %d (2:DDR2,3:DDR3)\n", para->dram_type);
++	if ( (para->dram_odt_en & 0x1) == 0 ) {
++		printf("DRAMC read ODT  off.\n");
++	}
++	else {
++		printf("DRAMC ZQ value: 0x%x\n", para->dram_zq);
++	}
++
++	// report ODT
++	rc = para->dram_mr1;
++	if ( (rc & 0x44)==0 ) {
++		printf("DRAM ODT off.\n");
++	}
++	else {
++		printf("DRAM ODT value: 0x%x.\n", rc);
++	}
++
++	// Init core, final run
++	if ( mctl_core_init(para)==0 ) {
++		printf("DRAM initialisation error : 1 !\n");
++		return 0;
++	}
++
++	// Get sdram size
++	rc = para->dram_para2;
++	if ( rc<0 ) {
++		rc = (rc & 0x7fff0000U) >> 16;
++	}
++	else {
++		rc = DRAMC_get_dram_size();
++		printf("DRAM SIZE =%d M\n", rc);
++		para->dram_para2 = (para->dram_para2 & 0xffffu) | rc << 16;
++	}
++	mem_size = rc;
++
++	// Purpose ??
++	if ( para->dram_tpr13 & (1 << 30) ) {
++		rc = readl(&para->dram_tpr8);
++		if ( rc==0 ) {
++			rc = 0x10000200;
++		}
++		writel(0x31030a0, rc);
++		writel(0x310309c, 0x40a);
++		writel(0x3103004, readl(0x3103004) | 1 );
++		printf("Enable Auto SR");
++	}
++	else {
++		writel(0x31030a0, readl(0x31030a0) & 0xffff0000);
++		writel(0x3103004, readl(0x3103004) & (~0x1) );
++	}
++
++	// Pupose ??
++	rc = readl(0x3103100) & ~(0xf000);
++	if ( (para->dram_tpr13 & 0x200)==0 ) {
++		if ( para->dram_type != 6 ) {
++			writel(0x3103100, rc);
++		}
++	}
++	else {
++		writel(0x3103100, rc | 0x5000);
++	}
++
++	writel(0x3103140, readl(0x3103140) | (1 << 31));
++	if (para->dram_tpr13 & (1 << 8)) {
++		writel(0x31030b8, readl(0x3103140) | 0x300);
++	}
++
++	rc = readl(0x3103108);
++	if (para->dram_tpr13 & (1 << 16)) {
++		rc &= 0xffffdfff;
++	}
++	else {
++		rc |= 0x00002000;
++	}
++	writel(0x3103108, rc);
++
++
++	// Purpose ??
++	if (para->dram_type == 7) {
++		rc  = readl(0x310307c) & 0xfff0ffff;
++		rc |= 0x0001000;
++		writel(0x310307c, rc);
++	}
++
++	dram_enable_all_master();
++	//if (dramc_simple_wr_test(mem_size, 64)) return 0;
++	if (para->dram_tpr13 & (1 << 28)) {
++		rc = readl(0x70005d4);
++		if ( (rc & (1 << 16)) || dramc_simple_wr_test(mem_size, 4096) ) {
++			return 0;
++		}
++	}
++
++	return mem_size;
++}
++
++struct sunxi_ram_priv {
++	size_t size;
++};
++
++static struct dram_para_t dram_para = {
++	0x00000318,
++	0x00000003,
++	0x007b7bfb,
++	0x00000001,
++	0x000010d2,
++	0x00000000,
++	0x00001c70,
++	0x00000042,
++	0x00000018,
++	0x00000000,
++	0x004a2195,
++	0x02423190,
++	0x0008b061,
++	0xb4787896,
++	0x00000000,
++	0x48484848,
++	0x00000048,
++	0x1620121e,
++	0x00000000,
++	0x00000000,
++	0x00000000,
++	0x00870000,
++	0x00000024,
++	0x34050100,
++};
++
++static int sunxi_ram_probe(struct udevice *dev)
++{
++	struct sunxi_ram_priv *priv = dev_get_priv(dev);
++	int ret;
++
++	printf("%s: %s: probing\n", __func__, dev->name);
++
++	ret = init_DRAM(0, &dram_para);
++	if (ret <= 0) {
++		printf("DRAM init failed: %d\n", ret);
++		return ret;
++	}
++
++	priv->size = ret * 1024 * 1024;
++
++	return 0;
++}
++
++static int sunxi_ram_get_info(struct udevice *dev, struct ram_info *info)
++{
++	struct sunxi_ram_priv *priv = dev_get_priv(dev);
++
++	printf("%s: %s: getting info\n", __func__, dev->name);
++
++	info->base = CONFIG_SYS_SDRAM_BASE;
++	info->size = priv->size;
++
++	return 0;
++}
++
++static struct ram_ops sunxi_ram_ops = {
++	.get_info = sunxi_ram_get_info,
++};
++
++static const struct udevice_id sunxi_ram_ids[] = {
++	{ .compatible = "allwinner,sun20i-d1-mbus" },
++	{ }
++};
++
++U_BOOT_DRIVER(sunxi_ram) = {
++	.name = "sunxi_ram",
++	.id = UCLASS_RAM,
++	.of_match = sunxi_ram_ids,
++	.ops = &sunxi_ram_ops,
++	.probe = sunxi_ram_probe,
++	.priv_auto = sizeof(struct sunxi_ram_priv),
++};
++
++#endif
+--- /dev/null
++++ b/drivers/ram/sunxi/sdram.h
+@@ -0,0 +1,46 @@
++// SPDX-License-Identifier: GPL-2.0+
++
++/*
++ * dram_para1 bits:
++ *  16-19 = page size
++ *  20-27 = row count
++ *     28 = banks 4 or 8
++ *
++ * dram_para2 bits:
++ *      0 = DQ width
++ *      4 = CS1 control
++ *   8-11 = rank flags? bit 8 = ranks differ in config
++ *  12-13 = rank
++ */
++
++/* MC_WORK_MODE bits
++ *   0- 1 = ranks code
++ *   2- 3 = banks, log2 - 2		 2	 3	 2
++ *   4- 7 = row width, log2 - 1		 16	11	11
++ *   8-11 = page size, log2 - 3		 9	 9	13
++ *  12-15 = DQ width (or 12-14?)
++ *  16-18 = dram type (2=DDR2, 3=DDR3, 6=LPDDR2, 7=LPDDR3)
++ *     19 = 2T or 1T
++ *  23-24 = ranks code (again?)
++ */
++
++#define DRAM_MR0	((void*)0x3103030)
++#define DRAM_MR1	((void*)0x3103034)
++#define DRAM_MR2	((void*)0x3103038)
++#define DRAM_MR3	((void*)0x310303c)
++
++#define DRAMTMG0	((void*)0x3103058)
++#define DRAMTMG1	((void*)0x310305c)
++#define DRAMTMG2	((void*)0x3103060)
++#define DRAMTMG3	((void*)0x3103064)
++#define DRAMTMG4	((void*)0x3103068)
++#define DRAMTMG5	((void*)0x310306c)
++#define DRAMTMG6	((void*)0x3103070)
++#define DRAMTMG7	((void*)0x3103074)
++#define DRAMTMG8	((void*)0x3103078)
++
++#define PITMG0		((void*)0x3103080)
++#define PTR3           	((void*)0x3103050)
++#define PTR4           	((void*)0x3103054)
++#define RFSHTMG        	((void*)0x3103090)
++#define RFSHCTL1       	((void*)0x3103094)
diff --git a/package/boot/uboot-d1/patches/0084-spi-sunxi-Hack-up-the-driver-for-the-D1.patch b/package/boot/uboot-d1/patches/0084-spi-sunxi-Hack-up-the-driver-for-the-D1.patch
new file mode 100644
index 00000000000000..1ce106e987909f
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0084-spi-sunxi-Hack-up-the-driver-for-the-D1.patch
@@ -0,0 +1,29 @@
+From 46f73ce33478734dabd5a93d425f7148b60198e1 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Wed, 8 Sep 2021 21:31:06 -0500
+Subject: [PATCH 84/90] spi: sunxi: Hack up the driver for the D1
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/spi/spi-sunxi.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/spi/spi-sunxi.c
++++ b/drivers/spi/spi-sunxi.c
+@@ -30,6 +30,7 @@
+ #include <asm/global_data.h>
+ #include <dm/device_compat.h>
+ #include <linux/bitops.h>
++#include <linux/log2.h>
+ 
+ #include <asm/bitops.h>
+ #include <asm/io.h>
+@@ -85,7 +86,7 @@ DECLARE_GLOBAL_DATA_PTR;
+ #define SUN4I_SPI_DEFAULT_RATE		1000000
+ #define SUN4I_SPI_TIMEOUT_MS		1000
+ 
+-#define SPI_REG(priv, reg)		((priv)->base + \
++#define SPI_REG(priv, reg)		(void *)((priv)->base + \
+ 					(priv)->variant->regs[reg])
+ #define SPI_BIT(priv, bit)		((priv)->variant->bits[bit])
+ #define SPI_CS(priv, cs)		(((cs) << SPI_BIT(priv, SPI_TCR_CS_SEL)) & \
diff --git a/package/boot/uboot-d1/patches/0085-spi-sunxi-Add-support-for-the-D1.patch b/package/boot/uboot-d1/patches/0085-spi-sunxi-Add-support-for-the-D1.patch
new file mode 100644
index 00000000000000..9ae2c144eb2ebd
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0085-spi-sunxi-Add-support-for-the-D1.patch
@@ -0,0 +1,23 @@
+From 4993c31d314d5c7ebad1d08e3e3f79694dca8738 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 11 Sep 2021 23:12:06 -0500
+Subject: [PATCH 85/90] spi: sunxi: Add support for the D1
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/spi/spi-sunxi.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/drivers/spi/spi-sunxi.c
++++ b/drivers/spi/spi-sunxi.c
+@@ -558,6 +558,10 @@ static const struct udevice_id sun4i_spi
+ 	  .compatible = "allwinner,sun8i-h3-spi",
+ 	  .data = (ulong)&sun8i_h3_spi_variant,
+ 	},
++	{
++	  .compatible = "allwinner,sun50i-r329-spi",
++	  .data = (ulong)&sun8i_h3_spi_variant,
++	},
+ 	{ /* sentinel */ }
+ };
+ 
diff --git a/package/boot/uboot-d1/patches/0086-usb-musb-new-Hack-up-the-driver-for-the-D1.patch b/package/boot/uboot-d1/patches/0086-usb-musb-new-Hack-up-the-driver-for-the-D1.patch
new file mode 100644
index 00000000000000..f76cb86131eb29
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0086-usb-musb-new-Hack-up-the-driver-for-the-D1.patch
@@ -0,0 +1,91 @@
+From eb0cf5922cf0656a7e9f96d6b83397469a26825a Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 11 Sep 2021 10:12:24 -0500
+Subject: [PATCH 86/90] usb: musb-new: Hack up the driver for the D1
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/riscv/include/asm/bitops.h    | 1 +
+ arch/riscv/include/asm/io.h        | 2 +-
+ arch/riscv/include/asm/processor.h | 2 ++
+ drivers/usb/musb-new/musb_io.h     | 2 +-
+ drivers/usb/musb-new/sunxi.c       | 6 ++++--
+ 5 files changed, 9 insertions(+), 4 deletions(-)
+
+--- a/arch/riscv/include/asm/bitops.h
++++ b/arch/riscv/include/asm/bitops.h
+@@ -78,6 +78,7 @@ static inline int __test_and_set_bit(int
+ 	return retval;
+ }
+ 
++#define test_and_clear_bit __test_and_clear_bit
+ static inline int __test_and_clear_bit(int nr, void *addr)
+ {
+ 	int mask, retval;
+--- a/arch/riscv/include/asm/io.h
++++ b/arch/riscv/include/asm/io.h
+@@ -218,6 +218,7 @@ static inline u64 readq(const volatile v
+ #define insb(p, d, l)			readsb(__io(p), d, l)
+ #define insw(p, d, l)			readsw(__io(p), d, l)
+ #define insl(p, d, l)			readsl(__io(p), d, l)
++#endif
+ 
+ static inline void readsb(unsigned int *addr, void *data, int bytelen)
+ {
+@@ -308,7 +309,6 @@ static inline void writesl(unsigned int
+ 		longlen--;
+ 	}
+ }
+-#endif
+ 
+ #define outb_p(val, port)		outb((val), (port))
+ #define outw_p(val, port)		outw((val), (port))
+--- a/arch/riscv/include/asm/processor.h
++++ b/arch/riscv/include/asm/processor.h
+@@ -23,4 +23,6 @@
+  *     no one uses the macros defined in this head file.
+  **************************************************************/
+ 
++#define cpu_relax()			barrier()
++
+ #endif /* __ASM_RISCV_PROCESSOR_H */
+--- a/drivers/usb/musb-new/musb_io.h
++++ b/drivers/usb/musb-new/musb_io.h
+@@ -23,7 +23,7 @@
+ #if !defined(CONFIG_ARM) && !defined(CONFIG_SUPERH) \
+ 	&& !defined(CONFIG_PPC32) \
+ 	&& !defined(CONFIG_PPC64) && !defined(CONFIG_MIPS) \
+-	&& !defined(CONFIG_M68K)
++	&& !defined(CONFIG_M68K) && !defined(CONFIG_RISCV)
+ static inline void readsl(const void __iomem *addr, void *buf, int len)
+ 	{ insl((unsigned long)addr, buf, len); }
+ static inline void readsw(const void __iomem *addr, void *buf, int len)
+--- a/drivers/usb/musb-new/sunxi.c
++++ b/drivers/usb/musb-new/sunxi.c
+@@ -23,8 +23,8 @@
+ #include <malloc.h>
+ #include <phy-sun4i-usb.h>
+ #include <reset.h>
+-#include <asm/arch/cpu.h>
+-#include <asm/arch/clock.h>
++//#include <asm/arch/cpu.h>
++//#include <asm/arch/clock.h>
+ #include <dm/device_compat.h>
+ #include <dm/lists.h>
+ #include <dm/root.h>
+@@ -174,6 +174,7 @@ static void USBC_ForceVbusValidToHigh(__
+ 
+ static void USBC_ConfigFIFO_Base(void)
+ {
++#if 0
+ 	u32 reg_value;
+ 
+ 	/* config usb fifo, 8kb mode */
+@@ -181,6 +182,7 @@ static void USBC_ConfigFIFO_Base(void)
+ 	reg_value &= ~(0x03 << 0);
+ 	reg_value |= BIT(0);
+ 	writel(reg_value, SUNXI_SRAMC_BASE + 0x04);
++#endif
+ }
+ 
+ /******************************************************************************
diff --git a/package/boot/uboot-d1/patches/0087-sunxi-Add-temporary-RISC-V-version-of-board-code.patch b/package/boot/uboot-d1/patches/0087-sunxi-Add-temporary-RISC-V-version-of-board-code.patch
new file mode 100644
index 00000000000000..c066f291628bd6
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0087-sunxi-Add-temporary-RISC-V-version-of-board-code.patch
@@ -0,0 +1,725 @@
+From e3152c690732fb141500379f32fbe2203fa47059 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 6 Aug 2022 00:48:38 -0500
+Subject: [PATCH 87/90] sunxi: Add temporary RISC-V version of board code
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ board/sunxi/Makefile           |   3 +-
+ board/sunxi/board-riscv.c      | 687 +++++++++++++++++++++++++++++++++
+ include/configs/sunxi-common.h |   1 -
+ 3 files changed, 689 insertions(+), 2 deletions(-)
+ create mode 100644 board/sunxi/board-riscv.c
+
+--- a/board/sunxi/Makefile
++++ b/board/sunxi/Makefile
+@@ -6,7 +6,8 @@
+ #
+ # (C) Copyright 2000-2003
+ # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+-obj-y	+= board.o
++obj-$(CONFIG_ARM)		+= board.o
++obj-$(CONFIG_RISCV)		+= board-riscv.o
+ obj-$(CONFIG_SUN7I_GMAC)	+= gmac.o
+ obj-$(CONFIG_MACH_SUN4I)	+= dram_sun4i_auto.o
+ obj-$(CONFIG_MACH_SUN5I)	+= dram_sun5i_auto.o
+--- /dev/null
++++ b/board/sunxi/board-riscv.c
+@@ -0,0 +1,687 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
++ * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
++ *
++ * (C) Copyright 2007-2011
++ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
++ * Tom Cubie <tangliang@allwinnertech.com>
++ *
++ * Some board init for the Allwinner A10-evb board.
++ */
++
++#include <dm.h>
++#include <cpu.h>
++#include <env.h>
++#include <env_internal.h>
++#include <fdt_support.h>
++#include <generic-phy.h>
++#include <image.h>
++#include <init.h>
++#include <net.h>
++#include <phy-sun4i-usb.h>
++#include <ram.h>
++#include <remoteproc.h>
++#include <spl.h>
++#include <status_led.h>
++#include <sunxi_image.h>
++#include <u-boot/crc.h>
++#include <asm/csr.h>
++#include <asm/global_data.h>
++#include <asm/io.h>
++
++#ifdef CONFIG_RISCV
++int board_init(void)
++{
++	/* https://lore.kernel.org/u-boot/31587574-4cd1-02da-9761-0134ac82b94b@sholland.org/ */
++	return cpu_probe_all();
++}
++
++int sunxi_get_sid(unsigned int *sid)
++{
++	return -ENODEV;
++}
++
++#define SPL_ADDR		CONFIG_SUNXI_SRAM_ADDRESS
++
++/* The low 8-bits of the 'boot_media' field in the SPL header */
++#define SUNXI_BOOTED_FROM_MMC0	0
++#define SUNXI_BOOTED_FROM_NAND	1
++#define SUNXI_BOOTED_FROM_MMC2	2
++#define SUNXI_BOOTED_FROM_SPI	3
++#define SUNXI_BOOTED_FROM_MMC0_HIGH	0x10
++#define SUNXI_BOOTED_FROM_MMC2_HIGH	0x12
++
++#define SUNXI_INVALID_BOOT_SOURCE	-1
++
++static int sunxi_egon_valid(struct boot_file_head *egon_head)
++{
++	return !memcmp(egon_head->magic, BOOT0_MAGIC, 8); /* eGON.BT0 */
++}
++
++static int sunxi_toc0_valid(struct toc0_main_info *toc0_info)
++{
++	return !memcmp(toc0_info->name, TOC0_MAIN_INFO_NAME, 8); /* TOC0.GLH */
++}
++
++static int sunxi_get_boot_source(void)
++{
++	struct boot_file_head *egon_head = (void *)SPL_ADDR;
++	struct toc0_main_info *toc0_info = (void *)SPL_ADDR;
++
++	/*
++	 * On the ARMv5 SoCs, the SPL header in SRAM is overwritten by the
++	 * exception vectors in U-Boot proper, so we won't find any
++	 * information there. Also the FEL stash is only valid in the SPL,
++	 * so we can't use that either. So if this is called from U-Boot
++	 * proper, just return MMC0 as a placeholder, for now.
++	 */
++	if (IS_ENABLED(CONFIG_MACH_SUNIV) &&
++	    !IS_ENABLED(CONFIG_SPL_BUILD))
++		return SUNXI_BOOTED_FROM_MMC0;
++
++	if (sunxi_egon_valid(egon_head))
++		return readb(&egon_head->boot_media);
++	if (sunxi_toc0_valid(toc0_info))
++		return readb(&toc0_info->platform[0]);
++
++	/* Not a valid image, so we must have been booted via FEL. */
++	return SUNXI_INVALID_BOOT_SOURCE;
++}
++
++/* The sunxi internal brom will try to loader external bootloader
++ * from mmc0, nand flash, mmc2.
++ */
++uint32_t sunxi_get_boot_device(void)
++{
++	int boot_source = sunxi_get_boot_source();
++
++	/*
++	 * When booting from the SD card or NAND memory, the "eGON.BT0"
++	 * signature is expected to be found in memory at the address 0x0004
++	 * (see the "mksunxiboot" tool, which generates this header).
++	 *
++	 * When booting in the FEL mode over USB, this signature is patched in
++	 * memory and replaced with something else by the 'fel' tool. This other
++	 * signature is selected in such a way, that it can't be present in a
++	 * valid bootable SD card image (because the BROM would refuse to
++	 * execute the SPL in this case).
++	 *
++	 * This checks for the signature and if it is not found returns to
++	 * the FEL code in the BROM to wait and receive the main u-boot
++	 * binary over USB. If it is found, it determines where SPL was
++	 * read from.
++	 */
++	switch (boot_source) {
++	case SUNXI_INVALID_BOOT_SOURCE:
++		return BOOT_DEVICE_BOARD;
++	case SUNXI_BOOTED_FROM_MMC0:
++	case SUNXI_BOOTED_FROM_MMC0_HIGH:
++		return BOOT_DEVICE_MMC1;
++	case SUNXI_BOOTED_FROM_NAND:
++		return BOOT_DEVICE_NAND;
++	case SUNXI_BOOTED_FROM_MMC2:
++	case SUNXI_BOOTED_FROM_MMC2_HIGH:
++		return BOOT_DEVICE_MMC2;
++	case SUNXI_BOOTED_FROM_SPI:
++		return BOOT_DEVICE_SPI;
++	}
++
++	panic("Unknown boot source %d\n", boot_source);
++	return -1;		/* Never reached */
++}
++
++uint32_t sunxi_get_spl_size(void)
++{
++	struct boot_file_head *egon_head = (void *)SPL_ADDR;
++	struct toc0_main_info *toc0_info = (void *)SPL_ADDR;
++
++	if (sunxi_egon_valid(egon_head))
++		return readl(&egon_head->length);
++	if (sunxi_toc0_valid(toc0_info))
++		return readl(&toc0_info->length);
++
++	/* Not a valid image, so use the default U-Boot offset. */
++	return 0;
++}
++
++/*
++ * The eGON SPL image can be located at 8KB or at 128KB into an SD card or
++ * an eMMC device. The boot source has bit 4 set in the latter case.
++ * By adding 120KB to the normal offset when booting from a "high" location
++ * we can support both cases.
++ * Also U-Boot proper is located at least 32KB after the SPL, but will
++ * immediately follow the SPL if that is bigger than that.
++ */
++unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
++					   unsigned long raw_sect)
++{
++	unsigned long spl_size = sunxi_get_spl_size();
++	unsigned long sector;
++
++	sector = max(raw_sect, spl_size / 512);
++
++	switch (sunxi_get_boot_source()) {
++	case SUNXI_BOOTED_FROM_MMC0_HIGH:
++	case SUNXI_BOOTED_FROM_MMC2_HIGH:
++		sector += (128 - 8) * 2;
++		break;
++	}
++
++	printf("SPL size = %lu, sector = %lu\n", spl_size, sector);
++
++	return sector;
++}
++
++u32 spl_boot_device(void)
++{
++	return sunxi_get_boot_device();
++}
++
++#define CSR_MXSTATUS		0x7c0
++#define CSR_MHCR		0x7c1
++#define CSR_MCOR		0x7c2
++#define CSR_MHINT		0x7c5
++
++int spl_board_init_f(void)
++{
++	int ret;
++	struct udevice *dev;
++
++	/* DDR init */
++	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
++	if (ret) {
++		debug("DRAM init failed: %d\n", ret);
++		return ret;
++	}
++
++	/* Initialize extension CSRs. */
++	printf("mxstatus=0x%08lx mhcr=0x%08lx mcor=0x%08lx mhint=0x%08lx\n",
++	       csr_read(CSR_MXSTATUS),
++	       csr_read(CSR_MHCR),
++	       csr_read(CSR_MCOR),
++	       csr_read(CSR_MHINT));
++
++	csr_set(CSR_MXSTATUS, 0x638000);
++	csr_write(CSR_MCOR, 0x70013);
++	csr_write(CSR_MHCR, 0x11ff);
++	csr_write(CSR_MHINT, 0x16e30c);
++
++	return 0;
++}
++
++#ifdef CONFIG_SPL_BUILD
++void spl_perform_fixups(struct spl_image_info *spl_image)
++{
++	struct ram_info info;
++	struct udevice *dev;
++	int ret;
++
++	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
++	if (ret)
++		panic("No RAM device");
++
++	ret = ram_get_info(dev, &info);
++	if (ret)
++		panic("No RAM info");
++
++	ret = fdt_fixup_memory(spl_image->fdt_addr, info.base, info.size);
++	if (ret)
++		panic("Failed to update DTB");
++}
++#endif
++#endif
++
++DECLARE_GLOBAL_DATA_PTR;
++
++/*
++ * Try to use the environment from the boot source first.
++ * For MMC, this means a FAT partition on the boot device (SD or eMMC).
++ * If the raw MMC environment is also enabled, this is tried next.
++ * When booting from NAND we try UBI first, then NAND directly.
++ * SPI flash falls back to FAT (on SD card).
++ */
++enum env_location env_get_location(enum env_operation op, int prio)
++{
++	if (prio > 1)
++		return ENVL_UNKNOWN;
++
++	/* NOWHERE is exclusive, no other option can be defined. */
++	if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE))
++		return ENVL_NOWHERE;
++
++	switch (sunxi_get_boot_device()) {
++	case BOOT_DEVICE_MMC1:
++	case BOOT_DEVICE_MMC2:
++		if (prio == 0 && IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
++			return ENVL_FAT;
++		if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC))
++			return ENVL_MMC;
++		break;
++	case BOOT_DEVICE_NAND:
++		if (prio == 0 && IS_ENABLED(CONFIG_ENV_IS_IN_UBI))
++			return ENVL_UBI;
++		if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND))
++			return ENVL_NAND;
++		break;
++	case BOOT_DEVICE_SPI:
++		if (prio == 0 && IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
++			return ENVL_SPI_FLASH;
++		if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
++			return ENVL_FAT;
++		break;
++	case BOOT_DEVICE_BOARD:
++		break;
++	default:
++		break;
++	}
++
++	/*
++	 * If we come here for the first time, we *must* return a valid
++	 * environment location other than ENVL_UNKNOWN, or the setup sequence
++	 * in board_f() will silently hang. This is arguably a bug in
++	 * env_init(), but for now pick one environment for which we know for
++	 * sure to have a driver for. For all defconfigs this is either FAT
++	 * or UBI, or NOWHERE, which is already handled above.
++	 */
++	if (prio == 0) {
++		if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
++			return ENVL_FAT;
++		if (IS_ENABLED(CONFIG_ENV_IS_IN_UBI))
++			return ENVL_UBI;
++	}
++
++	return ENVL_UNKNOWN;
++}
++
++/*
++ * On older SoCs the SPL is actually at address zero, so using NULL as
++ * an error value does not work.
++ */
++#define INVALID_SPL_HEADER ((void *)~0UL)
++
++static struct boot_file_head * get_spl_header(uint8_t req_version)
++{
++	struct boot_file_head *spl = (void *)(ulong)SPL_ADDR;
++	uint8_t spl_header_version = spl->spl_signature[3];
++
++	/* Is there really the SPL header (still) there? */
++	if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0)
++		return INVALID_SPL_HEADER;
++
++	if (spl_header_version < req_version) {
++		printf("sunxi SPL version mismatch: expected %u, got %u\n",
++		       req_version, spl_header_version);
++		return INVALID_SPL_HEADER;
++	}
++
++	return spl;
++}
++
++static const char *get_spl_dt_name(void)
++{
++	struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
++
++	/* Check if there is a DT name stored in the SPL header. */
++	if (spl != INVALID_SPL_HEADER && spl->dt_name_offset)
++		return (char *)spl + spl->dt_name_offset;
++
++	return NULL;
++}
++
++#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
++int mmc_get_env_dev(void)
++{
++	switch (sunxi_get_boot_device()) {
++	case BOOT_DEVICE_MMC1:
++		return 0;
++	case BOOT_DEVICE_MMC2:
++		return 1;
++	default:
++		return CONFIG_SYS_MMC_ENV_DEV;
++	}
++}
++#endif
++
++#ifdef CONFIG_SPL_BUILD
++void sunxi_board_init(void)
++{
++#ifdef CONFIG_LED_STATUS
++	if (IS_ENABLED(CONFIG_SPL_DRIVERS_MISC))
++		status_led_init();
++#endif
++}
++#endif
++
++#ifdef CONFIG_USB_GADGET
++int g_dnl_board_usb_cable_connected(void)
++{
++	struct udevice *dev;
++	struct phy phy;
++	int ret;
++
++	ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev);
++	if (ret) {
++		pr_err("%s: Cannot find USB device\n", __func__);
++		return ret;
++	}
++
++	ret = generic_phy_get_by_name(dev, "usb", &phy);
++	if (ret) {
++		pr_err("failed to get %s USB PHY\n", dev->name);
++		return ret;
++	}
++
++	ret = generic_phy_init(&phy);
++	if (ret) {
++		pr_debug("failed to init %s USB PHY\n", dev->name);
++		return ret;
++	}
++
++	return sun4i_usb_phy_vbus_detect(&phy);
++}
++#endif
++
++#ifdef CONFIG_SERIAL_TAG
++void get_board_serial(struct tag_serialnr *serialnr)
++{
++	char *serial_string;
++	unsigned long long serial;
++
++	serial_string = env_get("serial#");
++
++	if (serial_string) {
++		serial = simple_strtoull(serial_string, NULL, 16);
++
++		serialnr->high = (unsigned int) (serial >> 32);
++		serialnr->low = (unsigned int) (serial & 0xffffffff);
++	} else {
++		serialnr->high = 0;
++		serialnr->low = 0;
++	}
++}
++#endif
++
++/*
++ * Check the SPL header for the "sunxi" variant. If found: parse values
++ * that might have been passed by the loader ("fel" utility), and update
++ * the environment accordingly.
++ */
++static void parse_spl_header(const uint32_t spl_addr)
++{
++	struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
++
++	if (spl == INVALID_SPL_HEADER)
++		return;
++
++	if (!spl->fel_script_address)
++		return;
++
++	if (spl->fel_uEnv_length != 0) {
++		/*
++		 * data is expected in uEnv.txt compatible format, so "env
++		 * import -t" the string(s) at fel_script_address right away.
++		 */
++		himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address,
++			  spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL);
++		return;
++	}
++	/* otherwise assume .scr format (mkimage-type script) */
++	env_set_hex("fel_scriptaddr", spl->fel_script_address);
++}
++
++static bool get_unique_sid(unsigned int *sid)
++{
++	if (sunxi_get_sid(sid) != 0)
++		return false;
++
++	if (!sid[0])
++		return false;
++
++	/*
++	 * The single words 1 - 3 of the SID have quite a few bits
++	 * which are the same on many models, so we take a crc32
++	 * of all 3 words, to get a more unique value.
++	 *
++	 * Note we only do this on newer SoCs as we cannot change
++	 * the algorithm on older SoCs since those have been using
++	 * fixed mac-addresses based on only using word 3 for a
++	 * long time and changing a fixed mac-address with an
++	 * u-boot update is not good.
++	 */
++#if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
++    !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
++    !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
++	sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
++#endif
++
++	/* Ensure the NIC specific bytes of the mac are not all 0 */
++	if ((sid[3] & 0xffffff) == 0)
++		sid[3] |= 0x800000;
++
++	return true;
++}
++
++/*
++ * Note this function gets called multiple times.
++ * It must not make any changes to env variables which already exist.
++ */
++static void setup_environment(const void *fdt)
++{
++	char serial_string[17] = { 0 };
++	unsigned int sid[4];
++	uint8_t mac_addr[6];
++	char ethaddr[16];
++	int i;
++
++	if (!get_unique_sid(sid))
++		return;
++
++	for (i = 0; i < 4; i++) {
++		sprintf(ethaddr, "ethernet%d", i);
++		if (!fdt_get_alias(fdt, ethaddr))
++			continue;
++
++		if (i == 0)
++			strcpy(ethaddr, "ethaddr");
++		else
++			sprintf(ethaddr, "eth%daddr", i);
++
++		if (env_get(ethaddr))
++			continue;
++
++		/* Non OUI / registered MAC address */
++		mac_addr[0] = (i << 4) | 0x02;
++		mac_addr[1] = (sid[0] >>  0) & 0xff;
++		mac_addr[2] = (sid[3] >> 24) & 0xff;
++		mac_addr[3] = (sid[3] >> 16) & 0xff;
++		mac_addr[4] = (sid[3] >>  8) & 0xff;
++		mac_addr[5] = (sid[3] >>  0) & 0xff;
++
++		eth_env_set_enetaddr(ethaddr, mac_addr);
++	}
++
++	if (!env_get("serial#")) {
++		snprintf(serial_string, sizeof(serial_string),
++			"%08x%08x", sid[0], sid[3]);
++
++		env_set("serial#", serial_string);
++	}
++}
++
++int misc_init_r(void)
++{
++	const char *spl_dt_name;
++	uint boot;
++
++	env_set("fel_booted", NULL);
++	env_set("fel_scriptaddr", NULL);
++	env_set("mmc_bootdev", NULL);
++
++	boot = sunxi_get_boot_device();
++	/* determine if we are running in FEL mode */
++	if (boot == BOOT_DEVICE_BOARD) {
++		env_set("fel_booted", "1");
++		parse_spl_header(SPL_ADDR);
++	/* or if we booted from MMC, and which one */
++	} else if (boot == BOOT_DEVICE_MMC1) {
++		env_set("mmc_bootdev", "0");
++	} else if (boot == BOOT_DEVICE_MMC2) {
++		env_set("mmc_bootdev", "1");
++	}
++
++	/* Set fdtfile to match the FIT configuration chosen in SPL. */
++	spl_dt_name = get_spl_dt_name();
++	if (spl_dt_name) {
++		char *prefix = IS_ENABLED(CONFIG_ARM64) ? "allwinner/" : "";
++		char str[64];
++
++		snprintf(str, sizeof(str), "%s%s.dtb", prefix, spl_dt_name);
++		env_set("fdtfile", str);
++	}
++
++	setup_environment(gd->fdt_blob);
++
++	return 0;
++}
++
++int board_late_init(void)
++{
++#ifdef CONFIG_USB_ETHER
++	usb_ether_init();
++#endif
++
++#ifdef SUNXI_SCP_BASE
++	if (!rproc_load(0, SUNXI_SCP_BASE, SUNXI_SCP_MAX_SIZE)) {
++		puts("Starting SCP...\n");
++		rproc_start(0);
++	}
++#endif
++
++	return 0;
++}
++
++static void bluetooth_dt_fixup(void *blob)
++{
++	/* Some devices ship with a Bluetooth controller default address.
++	 * Set a valid address through the device tree.
++	 */
++	uchar tmp[ETH_ALEN], bdaddr[ETH_ALEN];
++	unsigned int sid[4];
++	int i;
++
++	if (!CONFIG_BLUETOOTH_DT_DEVICE_FIXUP[0])
++		return;
++
++	if (eth_env_get_enetaddr("bdaddr", tmp)) {
++		/* Convert between the binary formats of the corresponding stacks */
++		for (i = 0; i < ETH_ALEN; ++i)
++			bdaddr[i] = tmp[ETH_ALEN - i - 1];
++	} else {
++		if (!get_unique_sid(sid))
++			return;
++
++		bdaddr[0] = ((sid[3] >>  0) & 0xff) ^ 1;
++		bdaddr[1] = (sid[3] >>  8) & 0xff;
++		bdaddr[2] = (sid[3] >> 16) & 0xff;
++		bdaddr[3] = (sid[3] >> 24) & 0xff;
++		bdaddr[4] = (sid[0] >>  0) & 0xff;
++		bdaddr[5] = 0x02;
++	}
++
++	do_fixup_by_compat(blob, CONFIG_BLUETOOTH_DT_DEVICE_FIXUP,
++			   "local-bd-address", bdaddr, ETH_ALEN, 1);
++}
++
++int ft_board_setup(void *blob, struct bd_info *bd)
++{
++	int __maybe_unused r;
++
++	/*
++	 * Call setup_environment and fdt_fixup_ethernet again
++	 * in case the boot fdt has ethernet aliases the u-boot
++	 * copy does not have.
++	 */
++	setup_environment(blob);
++	fdt_fixup_ethernet(blob);
++
++	bluetooth_dt_fixup(blob);
++
++#ifdef CONFIG_VIDEO_DT_SIMPLEFB
++	r = sunxi_simplefb_setup(blob);
++	if (r)
++		return r;
++#endif
++	return 0;
++}
++
++#ifdef CONFIG_SPL_LOAD_FIT
++
++static void set_spl_dt_name(const char *name)
++{
++	struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
++
++	if (spl == INVALID_SPL_HEADER)
++		return;
++
++	/* Promote the header version for U-Boot proper, if needed. */
++	if (spl->spl_signature[3] < SPL_DT_HEADER_VERSION)
++		spl->spl_signature[3] = SPL_DT_HEADER_VERSION;
++
++	strcpy((char *)&spl->string_pool, name);
++	spl->dt_name_offset = offsetof(struct boot_file_head, string_pool);
++}
++
++int board_fit_config_name_match(const char *name)
++{
++	const char *best_dt_name = get_spl_dt_name();
++	int ret;
++
++#ifdef CONFIG_DEFAULT_DEVICE_TREE
++	if (best_dt_name == NULL)
++		best_dt_name = CONFIG_DEFAULT_DEVICE_TREE;
++#endif
++
++	if (best_dt_name == NULL) {
++		/* No DT name was provided, so accept the first config. */
++		return 0;
++	}
++#ifdef CONFIG_PINE64_DT_SELECTION
++	if (strstr(best_dt_name, "-pine64-plus")) {
++		/* Differentiate the Pine A64 boards by their DRAM size. */
++		if ((gd->ram_size == 512 * 1024 * 1024))
++			best_dt_name = "sun50i-a64-pine64";
++	}
++#endif
++#ifdef CONFIG_PINEPHONE_DT_SELECTION
++	if (strstr(best_dt_name, "-pinephone")) {
++		/* Differentiate the PinePhone revisions by GPIO inputs. */
++		prcm_apb0_enable(PRCM_APB0_GATE_PIO);
++		sunxi_gpio_set_pull(SUNXI_GPL(6), SUNXI_GPIO_PULL_UP);
++		sunxi_gpio_set_cfgpin(SUNXI_GPL(6), SUNXI_GPIO_INPUT);
++		udelay(100);
++
++		/* PL6 is pulled low by the modem on v1.2. */
++		if (gpio_get_value(SUNXI_GPL(6)) == 0)
++			best_dt_name = "sun50i-a64-pinephone-1.2";
++		else
++			best_dt_name = "sun50i-a64-pinephone-1.1";
++
++		sunxi_gpio_set_cfgpin(SUNXI_GPL(6), SUNXI_GPIO_DISABLE);
++		sunxi_gpio_set_pull(SUNXI_GPL(6), SUNXI_GPIO_PULL_DISABLE);
++		prcm_apb0_disable(PRCM_APB0_GATE_PIO);
++	}
++#endif
++
++	ret = strcmp(name, best_dt_name);
++
++	/*
++	 * If one of the FIT configurations matches the most accurate DT name,
++	 * update the SPL header to provide that DT name to U-Boot proper.
++	 */
++	if (ret == 0)
++		set_spl_dt_name(best_dt_name);
++
++	return ret;
++}
++#endif
+--- a/include/configs/sunxi-common.h
++++ b/include/configs/sunxi-common.h
+@@ -12,7 +12,6 @@
+ #ifndef _SUNXI_COMMON_CONFIG_H
+ #define _SUNXI_COMMON_CONFIG_H
+ 
+-#include <asm/arch/cpu.h>
+ #include <linux/stringify.h>
+ 
+ /* Serial & console */
diff --git a/package/boot/uboot-d1/patches/0088-sunxi-riscv-Copy-in-WIP-version-of-devicetrees.patch b/package/boot/uboot-d1/patches/0088-sunxi-riscv-Copy-in-WIP-version-of-devicetrees.patch
new file mode 100644
index 00000000000000..95ed7b202718e6
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0088-sunxi-riscv-Copy-in-WIP-version-of-devicetrees.patch
@@ -0,0 +1,1327 @@
+From 197d4096c697bcde8f9833b1d04b17eb2b232b85 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Mon, 31 Oct 2022 22:59:00 -0500
+Subject: [PATCH 88/90] sunxi: riscv: Copy in WIP version of devicetrees
+
+While the bindings still are not stable, this should help things work
+out of the box.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ .../riscv/dts/sun20i-d1-clockworkpi-v3.14.dts | 134 +++++++-
+ .../dts/sun20i-d1-common-regulators.dtsi      |  13 +
+ arch/riscv/dts/sun20i-d1-devterm-v3.14.dts    |  16 +
+ .../dts/sun20i-d1-dongshan-nezha-stu.dts      |  48 ++-
+ .../dts/sun20i-d1-lichee-rv-86-panel-480p.dts |  51 +++
+ .../dts/sun20i-d1-lichee-rv-86-panel.dtsi     |  64 ++++
+ arch/riscv/dts/sun20i-d1-lichee-rv-dock.dts   |  98 ++++++
+ arch/riscv/dts/sun20i-d1-lichee-rv.dts        |   6 +
+ arch/riscv/dts/sun20i-d1-mangopi-mq-pro.dts   |  41 +++
+ arch/riscv/dts/sun20i-d1-nezha.dts            | 117 ++++++-
+ arch/riscv/dts/sun20i-d1.dtsi                 | 314 +++++++++++++++++-
+ 11 files changed, 881 insertions(+), 21 deletions(-)
+
+--- a/arch/riscv/dts/sun20i-d1-clockworkpi-v3.14.dts
++++ b/arch/riscv/dts/sun20i-d1-clockworkpi-v3.14.dts
+@@ -22,16 +22,78 @@
+ 		stdout-path = "serial0:115200n8";
+ 	};
+ 
++	audio_amplifier: audio-amplifier {
++		compatible = "simple-audio-amplifier";
++		enable-gpios = <&pio 4 1 GPIO_ACTIVE_HIGH>; /* PE1/GPIO11 */
++		sound-name-prefix = "Amplifier";
++		VCC-supply = <&reg_vcc>;
++	};
++
++	/*
++	 * FIXME: This is not really an amplifier, but the amplifier binding
++	 * has the needed properties and behavior.
++	 */
++	audio_switch: audio-switch {
++		compatible = "simple-audio-amplifier";
++		enable-gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2/AUD_SWITCH */
++		sound-name-prefix = "Switch";
++		VCC-supply = <&reg_aldo1>;
++	};
++
++	backlight: backlight {
++		compatible = "pwm-backlight";
++		power-supply = <&reg_vcc>;
++		pwms = <&pwm 4 50000 0>; /* PD20/GPIO9 */
++	};
++
++	bt_sco_codec: bt-sco-codec {
++		#sound-dai-cells = <0>;
++		compatible = "linux,bt-sco";
++	};
++
++	bt-sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,name = "Bluetooth";
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		simple-audio-card,dai-link@0 {
++			format = "dsp_a";
++			frame-master = <&bt_sound_cpu>;
++			bitclock-master = <&bt_sound_cpu>;
++
++			bt_sound_cpu: cpu {
++				sound-dai = <&i2s1>;
++			};
++
++			codec {
++				sound-dai = <&bt_sco_codec>;
++			};
++		};
++	};
++
++	hdmi_connector: connector {
++		compatible = "hdmi-connector";
++		type = "d";
++
++		port {
++			hdmi_connector_in: endpoint {
++				remote-endpoint = <&hdmi_out_connector>;
++			};
++		};
++	};
++
+ 	/*
+ 	 * This regulator is PWM-controlled, but the PWM controller is not
+ 	 * yet supported, so fix the regulator to its default voltage.
+ 	 */
+ 	reg_vdd_cpu: vdd-cpu {
+-		compatible = "regulator-fixed";
++		compatible = "pwm-regulator";
++		pwms = <&pwm 0 50000 0>;
++		pwm-supply = <&reg_vcc>;
+ 		regulator-name = "vdd-cpu";
+-		regulator-min-microvolt = <1100000>;
+-		regulator-max-microvolt = <1100000>;
+-		vin-supply = <&reg_vcc>;
++		regulator-min-microvolt = <810000>;
++		regulator-max-microvolt = <1160000>;
+ 	};
+ 
+ 	wifi_pwrseq: wifi-pwrseq {
+@@ -40,14 +102,51 @@
+ 	};
+ };
+ 
++&codec {
++	aux-devs = <&audio_amplifier>, <&audio_switch>;
++	hp-det-gpio = <&pio 1 12 GPIO_ACTIVE_HIGH>; /* PB12/GPIO10 */
++	pin-switches = "Internal Speakers";
++	routing = "Internal Speakers", "Amplifier OUTL",
++		  "Internal Speakers", "Amplifier OUTR",
++		  "Amplifier INL", "Switch OUTL",
++		  "Amplifier INR", "Switch OUTR",
++		  "Headphone Jack", "Switch OUTL",
++		  "Headphone Jack", "Switch OUTR",
++		  "Switch INL", "HPOUTL",
++		  "Switch INR", "HPOUTR",
++		  "MICIN3", "Headset Microphone",
++		  "Headset Microphone", "HBIAS";
++	widgets = "Microphone", "Headset Microphone",
++		  "Headphone", "Headphone Jack",
++		  "Speaker", "Internal Speakers";
++};
++
+ &cpu0 {
+ 	cpu-supply = <&reg_vdd_cpu>;
+ };
+ 
++&de {
++	status = "okay";
++};
++
+ &ehci1 {
+ 	status = "okay";
+ };
+ 
++&hdmi {
++	status = "okay";
++};
++
++&hdmi_out {
++	hdmi_out_connector: endpoint {
++		remote-endpoint = <&hdmi_connector_in>;
++	};
++};
++
++&hdmi_phy {
++	status = "okay";
++};
++
+ &i2c0 {
+ 	pinctrl-0 = <&i2c0_pb10_pins>;
+ 	pinctrl-names = "default";
+@@ -169,6 +268,12 @@
+ 	};
+ };
+ 
++&i2s1 {
++	pinctrl-0 = <&i2s1_clk_pins>, <&i2s1_din_pin>, <&i2s1_dout_pin>;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
+ &mmc0 {
+ 	broken-cd;
+ 	bus-width = <4>;
+@@ -205,6 +310,27 @@
+ 
+ &pio {
+ 	vcc-pg-supply = <&reg_ldoa>;
++
++	i2s1_clk_pins: i2s1-clk-pins {
++		pins = "PG12", "PG13";
++		function = "i2s1";
++	};
++
++	i2s1_din_pin: i2s1-din-pin {
++		pins = "PG14";
++		function = "i2s1_din";
++	};
++
++	i2s1_dout_pin: i2s1-dout-pin {
++		pins = "PG15";
++		function = "i2s1_dout";
++	};
++};
++
++&pwm {
++	pinctrl-0 = <&pwm0_pd16_pin>, <&pwm4_pd20_pin>;
++	pinctrl-names = "default";
++	status = "okay";
+ };
+ 
+ &uart0 {
+--- a/arch/riscv/dts/sun20i-d1-common-regulators.dtsi
++++ b/arch/riscv/dts/sun20i-d1-common-regulators.dtsi
+@@ -18,6 +18,15 @@
+ 	};
+ };
+ 
++&codec {
++	avcc-supply = <&reg_aldo>;
++	hpvcc-supply = <&reg_hpldo>;
++};
++
++&hdmi {
++	hvcc-supply = <&reg_ldoa>;
++};
++
+ &lradc {
+ 	vref-supply = <&reg_aldo>;
+ };
+@@ -49,3 +58,7 @@
+ 	regulator-max-microvolt = <1800000>;
+ 	ldo-in-supply = <&reg_vcc_3v3>;
+ };
++
++&ths {
++	vref-supply = <&reg_aldo>;
++};
+--- a/arch/riscv/dts/sun20i-d1-devterm-v3.14.dts
++++ b/arch/riscv/dts/sun20i-d1-devterm-v3.14.dts
+@@ -35,3 +35,19 @@
+ 		};
+ 	};
+ };
++
++&dsi {
++	pinctrl-0 = <&dsi_4lane_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++
++	panel@0 {
++		compatible = "clockwork,cwd686";
++		reg = <0>;
++		backlight = <&backlight>;
++		reset-gpios = <&pio 3 19 GPIO_ACTIVE_LOW>; /* PD19/GPIO8 */
++		rotation = <90>;
++		iovcc-supply = <&reg_dcdc3>;
++		vci-supply = <&reg_aldo2>;
++	};
++};
+--- a/arch/riscv/dts/sun20i-d1-dongshan-nezha-stu.dts
++++ b/arch/riscv/dts/sun20i-d1-dongshan-nezha-stu.dts
+@@ -23,6 +23,17 @@
+ 		stdout-path = "serial0:115200n8";
+ 	};
+ 
++	hdmi_connector: connector {
++		compatible = "hdmi-connector";
++		type = "a";
++
++		port {
++			hdmi_connector_in: endpoint {
++				remote-endpoint = <&hdmi_out_connector>;
++			};
++		};
++	};
++
+ 	leds {
+ 		compatible = "gpio-leds";
+ 
+@@ -43,16 +54,13 @@
+ 		vin-supply = <&reg_vcc>;
+ 	};
+ 
+-	/*
+-	 * This regulator is PWM-controlled, but the PWM controller is not
+-	 * yet supported, so fix the regulator to its default voltage.
+-	 */
+ 	reg_vdd_cpu: vdd-cpu {
+-		compatible = "regulator-fixed";
++		compatible = "pwm-regulator";
++		pwms = <&pwm 0 50000 0>;
++		pwm-supply = <&reg_vcc>;
+ 		regulator-name = "vdd-cpu";
+-		regulator-min-microvolt = <1100000>;
+-		regulator-max-microvolt = <1100000>;
+-		vin-supply = <&reg_vcc>;
++		regulator-min-microvolt = <810000>;
++		regulator-max-microvolt = <1160000>;
+ 	};
+ };
+ 
+@@ -60,6 +68,10 @@
+ 	cpu-supply = <&reg_vdd_cpu>;
+ };
+ 
++&de {
++	status = "okay";
++};
++
+ &ehci0 {
+ 	status = "okay";
+ };
+@@ -73,6 +85,20 @@
+ 	status = "okay";
+ };
+ 
++&hdmi {
++	status = "okay";
++};
++
++&hdmi_out {
++	hdmi_out_connector: endpoint {
++		remote-endpoint = <&hdmi_connector_in>;
++	};
++};
++
++&hdmi_phy {
++	status = "okay";
++};
++
+ &mdio {
+ 	ext_rgmii_phy: ethernet-phy@1 {
+ 		compatible = "ethernet-phy-ieee802.3-c22";
+@@ -95,6 +121,12 @@
+ 	status = "okay";
+ };
+ 
++&pwm {
++	pinctrl-0 = <&pwm0_pd16_pin>;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-0 = <&uart0_pb8_pins>;
+ 	pinctrl-names = "default";
+--- a/arch/riscv/dts/sun20i-d1-lichee-rv-86-panel-480p.dts
++++ b/arch/riscv/dts/sun20i-d1-lichee-rv-86-panel-480p.dts
+@@ -7,6 +7,40 @@
+ 	model = "Sipeed Lichee RV 86 Panel (480p)";
+ 	compatible = "sipeed,lichee-rv-86-panel-480p", "sipeed,lichee-rv",
+ 		     "allwinner,sun20i-d1";
++
++	backlight: backlight {
++		compatible = "pwm-backlight";
++		power-supply = <&reg_vcc>;
++		pwms = <&pwm 7 50000 0>;
++	};
++
++	spi {
++		compatible = "spi-gpio";
++		cs-gpios = <&pio 4 14 GPIO_ACTIVE_LOW>; /* PE14 */
++		mosi-gpios = <&pio 4 12 GPIO_ACTIVE_HIGH>; /* PE12 */
++		sck-gpios = <&pio 4 15 GPIO_ACTIVE_HIGH>; /* PE15 */
++		num-chipselects = <1>;
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		panel@0 {
++			compatible = "sitronix,st7701s";
++			reg = <0>;
++			backlight = <&backlight>;
++			reset-gpios = <&pio 6 13 GPIO_ACTIVE_LOW>; /* PG13 */
++			spi-3wire;
++
++			port {
++				panel_in_tcon_lcd0: endpoint {
++					remote-endpoint = <&tcon_lcd0_out_panel>;
++				};
++			};
++		};
++	};
++};
++
++&de {
++	status = "okay";
+ };
+ 
+ &i2c2 {
+@@ -27,3 +61,20 @@
+ 		wakeup-source;
+ 	};
+ };
++
++&pwm {
++	pinctrl-0 = <&pwm7_pd22_pin>;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
++&tcon_lcd0 {
++	pinctrl-0 = <&lcd_rgb666_pins>;
++	pinctrl-names = "default";
++};
++
++&tcon_lcd0_out {
++	tcon_lcd0_out_panel: endpoint {
++		remote-endpoint = <&panel_in_tcon_lcd0>;
++	};
++};
+--- a/arch/riscv/dts/sun20i-d1-lichee-rv-86-panel.dtsi
++++ b/arch/riscv/dts/sun20i-d1-lichee-rv-86-panel.dtsi
+@@ -9,6 +9,39 @@
+ 		ethernet1 = &xr829;
+ 	};
+ 
++	audio_amplifier: audio-amplifier {
++		compatible = "simple-audio-amplifier";
++		enable-gpios = <&pio 1 10 GPIO_ACTIVE_HIGH>; /* PB10 */
++		sound-name-prefix = "Amplifier";
++	};
++
++	dmic_codec: dmic-codec {
++		compatible = "dmic-codec";
++		num-channels = <2>;
++		#sound-dai-cells = <0>;
++	};
++
++	dmic-sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,name = "DMIC";
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		simple-audio-card,dai-link@0 {
++			format = "pdm";
++			frame-master = <&link0_cpu>;
++			bitclock-master = <&link0_cpu>;
++
++			link0_cpu: cpu {
++				sound-dai = <&dmic>;
++			};
++
++			link0_codec: codec {
++				sound-dai = <&dmic_codec>;
++			};
++		};
++	};
++
+ 	/* PC1 is repurposed as BT_WAKE_AP */
+ 	/delete-node/ leds;
+ 
+@@ -24,6 +57,27 @@
+ 	};
+ };
+ 
++&codec {
++	aux-devs = <&audio_amplifier>;
++	routing = "Internal Speaker", "Amplifier OUTL",
++		  "Internal Speaker", "Amplifier OUTR",
++		  "Amplifier INL", "HPOUTL",
++		  "Amplifier INR", "HPOUTR",
++		  "LINEINL", "HPOUTL",
++		  "LINEINR", "HPOUTR",
++		  "MICIN3", "Internal Microphone",
++		  "Internal Microphone", "HBIAS";
++	widgets = "Microphone", "Internal Microphone",
++		  "Speaker", "Internal Speaker";
++	status = "okay";
++};
++
++&dmic {
++	pinctrl-0 = <&dmic_pb11_d0_pin>, <&dmic_pe17_clk_pin>;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
+ &ehci1 {
+ 	status = "okay";
+ };
+@@ -69,6 +123,16 @@
+ 		pins = "PG11";
+ 		function = "clk";
+ 	};
++
++	dmic_pb11_d0_pin: dmic-pb11-d0-pin {
++		pins = "PB11";
++		function = "dmic";
++	};
++
++	dmic_pe17_clk_pin: dmic-pe17-clk-pin {
++		pins = "PE17";
++		function = "dmic";
++	};
+ };
+ 
+ &uart1 {
+--- a/arch/riscv/dts/sun20i-d1-lichee-rv-dock.dts
++++ b/arch/riscv/dts/sun20i-d1-lichee-rv-dock.dts
+@@ -15,16 +15,102 @@
+ 		ethernet1 = &rtl8723ds;
+ 	};
+ 
++	dmic_codec: dmic-codec {
++		compatible = "dmic-codec";
++		num-channels = <2>;
++		#sound-dai-cells = <0>;
++	};
++
++	dmic-sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,name = "DMIC";
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		simple-audio-card,dai-link@0 {
++			format = "pdm";
++			frame-master = <&link0_cpu>;
++			bitclock-master = <&link0_cpu>;
++
++			link0_cpu: cpu {
++				sound-dai = <&dmic>;
++			};
++
++			link0_codec: codec {
++				sound-dai = <&dmic_codec>;
++			};
++		};
++	};
++
++	hdmi_connector: connector {
++		compatible = "hdmi-connector";
++		type = "a";
++
++		port {
++			hdmi_connector_in: endpoint {
++				remote-endpoint = <&hdmi_out_connector>;
++			};
++		};
++	};
++
+ 	wifi_pwrseq: wifi-pwrseq {
+ 		compatible = "mmc-pwrseq-simple";
+ 		reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
+ 	};
+ };
+ 
++&codec {
++	routing = "Internal Speaker", "HPOUTL",
++		  "Internal Speaker", "HPOUTR",
++		  "LINEINL", "HPOUTL",
++		  "LINEINR", "HPOUTR",
++		  "MICIN3", "Internal Microphone",
++		  "Internal Microphone", "HBIAS";
++	widgets = "Microphone", "Internal Microphone",
++		  "Speaker", "Internal Speaker";
++	status = "okay";
++};
++
++&de {
++	status = "okay";
++};
++
++&dmic {
++	pinctrl-0 = <&dmic_pb11_d0_pin>, <&dmic_pe17_clk_pin>;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
+ &ehci1 {
+ 	status = "okay";
+ };
+ 
++&hdmi {
++	status = "okay";
++};
++
++&hdmi_out {
++	hdmi_out_connector: endpoint {
++		remote-endpoint = <&hdmi_connector_in>;
++	};
++};
++
++&hdmi_phy {
++	status = "okay";
++};
++
++&ledc {
++	pinctrl-0 = <&ledc_pc0_pin>;
++	pinctrl-names = "default";
++	status = "okay";
++
++	multi-led@0 {
++		reg = <0x0>;
++		color = <LED_COLOR_ID_RGB>;
++		function = LED_FUNCTION_STATUS;
++	};
++};
++
+ &lradc {
+ 	status = "okay";
+ 
+@@ -55,6 +141,18 @@
+ 	status = "okay";
+ };
+ 
++&pio {
++	dmic_pb11_d0_pin: dmic-pb11-d0-pin {
++		pins = "PB11";
++		function = "dmic";
++	};
++
++	dmic_pe17_clk_pin: dmic-pe17-clk-pin {
++		pins = "PE17";
++		function = "dmic";
++	};
++};
++
+ &uart1 {
+ 	uart-has-rtscts;
+ 	pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
+--- a/arch/riscv/dts/sun20i-d1-lichee-rv.dts
++++ b/arch/riscv/dts/sun20i-d1-lichee-rv.dts
+@@ -65,6 +65,12 @@
+ 	status = "okay";
+ };
+ 
++&spi0 {
++	pinctrl-0 = <&spi0_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-0 = <&uart0_pb8_pins>;
+ 	pinctrl-names = "default";
+--- a/arch/riscv/dts/sun20i-d1-mangopi-mq-pro.dts
++++ b/arch/riscv/dts/sun20i-d1-mangopi-mq-pro.dts
+@@ -4,6 +4,7 @@
+ /dts-v1/;
+ 
+ #include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/leds/common.h>
+ 
+ #include "sun20i-d1.dtsi"
+ #include "sun20i-d1-common-regulators.dtsi"
+@@ -22,6 +23,28 @@
+ 		stdout-path = "serial0:115200n8";
+ 	};
+ 
++	hdmi_connector: connector {
++		compatible = "hdmi-connector";
++		type = "c";
++
++		port {
++			hdmi_connector_in: endpoint {
++				remote-endpoint = <&hdmi_out_connector>;
++			};
++		};
++	};
++
++	leds {
++		compatible = "pwm-leds";
++
++		led {
++			color = <LED_COLOR_ID_BLUE>;
++			function = LED_FUNCTION_STATUS;
++			max-brightness = <255>;
++			pwms = <&pwm 2 50000 0>;
++		};
++	};
++
+ 	reg_avdd2v8: avdd2v8 {
+ 		compatible = "regulator-fixed";
+ 		regulator-name = "avdd2v8";
+@@ -56,10 +79,28 @@
+ 	cpu-supply = <&reg_vdd_cpu>;
+ };
+ 
++&de {
++	status = "okay";
++};
++
+ &ehci1 {
+ 	status = "okay";
+ };
+ 
++&hdmi {
++	status = "okay";
++};
++
++&hdmi_out {
++	hdmi_out_connector: endpoint {
++		remote-endpoint = <&hdmi_connector_in>;
++	};
++};
++
++&hdmi_phy {
++	status = "okay";
++};
++
+ &mmc0 {
+ 	bus-width = <4>;
+ 	cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+--- a/arch/riscv/dts/sun20i-d1-nezha.dts
++++ b/arch/riscv/dts/sun20i-d1-nezha.dts
+@@ -5,6 +5,7 @@
+ 
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/input/input.h>
++#include <dt-bindings/leds/common.h>
+ 
+ #include "sun20i-d1.dtsi"
+ #include "sun20i-d1-common-regulators.dtsi"
+@@ -18,12 +19,24 @@
+ 		ethernet1 = &xr829;
+ 		mmc0 = &mmc0;
+ 		serial0 = &uart0;
++		spi0 = &spi0;
+ 	};
+ 
+ 	chosen {
+ 		stdout-path = "serial0:115200n8";
+ 	};
+ 
++	hdmi_connector: connector {
++		compatible = "hdmi-connector";
++		type = "a";
++
++		port {
++			hdmi_connector_in: endpoint {
++				remote-endpoint = <&hdmi_out_connector>;
++			};
++		};
++	};
++
+ 	reg_usbvbus: usbvbus {
+ 		compatible = "regulator-fixed";
+ 		regulator-name = "usbvbus";
+@@ -34,16 +47,13 @@
+ 		vin-supply = <&reg_vcc>;
+ 	};
+ 
+-	/*
+-	 * This regulator is PWM-controlled, but the PWM controller is not
+-	 * yet supported, so fix the regulator to its default voltage.
+-	 */
+ 	reg_vdd_cpu: vdd-cpu {
+-		compatible = "regulator-fixed";
++		compatible = "pwm-regulator";
++		pwms = <&pwm 0 50000 0>;
++		pwm-supply = <&reg_vcc>;
+ 		regulator-name = "vdd-cpu";
+-		regulator-min-microvolt = <1100000>;
+-		regulator-max-microvolt = <1100000>;
+-		vin-supply = <&reg_vcc>;
++		regulator-min-microvolt = <810000>;
++		regulator-max-microvolt = <1160000>;
+ 	};
+ 
+ 	wifi_pwrseq: wifi-pwrseq {
+@@ -52,10 +62,26 @@
+ 	};
+ };
+ 
++&codec {
++	routing = "Headphone Jack", "HPOUTL",
++		  "Headphone Jack", "HPOUTR",
++		  "LINEINL", "HPOUTL",
++		  "LINEINR", "HPOUTR",
++		  "MICIN3", "Headset Microphone",
++		  "Headset Microphone", "HBIAS";
++	widgets = "Microphone", "Headset Microphone",
++		  "Headphone", "Headphone Jack";
++	status = "okay";
++};
++
+ &cpu0 {
+ 	cpu-supply = <&reg_vdd_cpu>;
+ };
+ 
++&de {
++	status = "okay";
++};
++
+ &ehci0 {
+ 	status = "okay";
+ };
+@@ -73,6 +99,20 @@
+ 	status = "okay";
+ };
+ 
++&hdmi {
++	status = "okay";
++};
++
++&hdmi_out {
++	hdmi_out_connector: endpoint {
++		remote-endpoint = <&hdmi_connector_in>;
++	};
++};
++
++&hdmi_phy {
++	status = "okay";
++};
++
+ &i2c2 {
+ 	pinctrl-0 = <&i2c2_pb0_pins>;
+ 	pinctrl-names = "default";
+@@ -90,6 +130,18 @@
+ 	};
+ };
+ 
++&ledc {
++	pinctrl-0 = <&ledc_pc0_pin>;
++	pinctrl-names = "default";
++	status = "okay";
++
++	multi-led@0 {
++		reg = <0x0>;
++		color = <LED_COLOR_ID_RGB>;
++		function = LED_FUNCTION_STATUS;
++	};
++};
++
+ &lradc {
+ 	status = "okay";
+ 
+@@ -142,6 +194,55 @@
+ 	status = "okay";
+ };
+ 
++&pwm {
++	pinctrl-0 = <&pwm0_pd16_pin>;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
++&spi0 {
++	pinctrl-0 = <&spi0_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++
++	flash@0 {
++		compatible = "spi-nand";
++		reg = <0>;
++
++		partitions {
++			compatible = "fixed-partitions";
++			#address-cells = <1>;
++			#size-cells = <1>;
++
++			partition@0 {
++				label = "boot0";
++				reg = <0x00000000 0x00100000>;
++			};
++
++			partition@100000 {
++				label = "uboot";
++				reg = <0x00100000 0x00300000>;
++			};
++
++			partition@400000 {
++				label = "secure_storage";
++				reg = <0x00400000 0x00100000>;
++			};
++
++			partition@500000 {
++				label = "sys";
++				reg = <0x00500000 0x0fb00000>;
++			};
++		};
++	};
++};
++
++&spi1 {
++	pinctrl-0 = <&spi1_pd_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-0 = <&uart0_pb8_pins>;
+ 	pinctrl-names = "default";
+--- a/arch/riscv/dts/sun20i-d1.dtsi
++++ b/arch/riscv/dts/sun20i-d1.dtsi
+@@ -59,6 +59,35 @@
+ 		#clock-cells = <0>;
+ 	};
+ 
++	thermal-zones {
++		cpu-thermal {
++			polling-delay = <0>;
++			polling-delay-passive = <0>;
++			thermal-sensors = <&ths>;
++
++			trips {
++				cpu_target: cpu-target {
++					hysteresis = <3000>;
++					temperature = <85000>;
++					type = "passive";
++				};
++
++				cpu-crit {
++					hysteresis = <0>;
++					temperature = <110000>;
++					type = "critical";
++				};
++			};
++
++			cooling-maps {
++				map0 {
++					trip = <&cpu_target>;
++					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
++				};
++			};
++		};
++	};
++
+ 	soc {
+ 		compatible = "simple-bus";
+ 		ranges;
+@@ -95,6 +124,14 @@
+ 			#interrupt-cells = <3>;
+ 
+ 			/omit-if-no-ref/
++			dsi_4lane_pins: dsi-4lane-pins {
++				pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
++				       "PD6", "PD7", "PD8", "PD9";
++				drive-strength = <30>;
++				function = "dsi";
++			};
++
++			/omit-if-no-ref/
+ 			i2c0_pb10_pins: i2c0-pb10-pins {
+ 				pins = "PB10", "PB11";
+ 				function = "i2c0";
+@@ -116,6 +153,12 @@
+ 			};
+ 
+ 			/omit-if-no-ref/
++			ledc_pc0_pin: ledc-pc0-pin {
++				pins = "PC0";
++				function = "ledc";
++			};
++
++			/omit-if-no-ref/
+ 			mmc0_pins: mmc0-pins {
+ 				pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
+ 				function = "mmc0";
+@@ -149,6 +192,48 @@
+ 			};
+ 
+ 			/omit-if-no-ref/
++			pwm0_pd16_pin: pwm0-pd16-pin {
++				pins = "PD16";
++				function = "pwm0";
++			};
++
++			/omit-if-no-ref/
++			pwm2_pd18_pin: pwm2-pd18-pin {
++				pins = "PD18";
++				function = "pwm2";
++			};
++
++			/omit-if-no-ref/
++			pwm4_pd20_pin: pwm4-pd20-pin {
++				pins = "PD20";
++				function = "pwm4";
++			};
++
++			/omit-if-no-ref/
++			pwm7_pd22_pin: pwm7-pd22-pin {
++				pins = "PD22";
++				function = "pwm7";
++			};
++
++			/omit-if-no-ref/
++			spi0_pins: spi0-pins {
++				pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7";
++				function = "spi0";
++			};
++
++			/omit-if-no-ref/
++			spi1_pb_pins: spi1-pb-pins {
++				pins = "PB0", "PB8", "PB9", "PB10", "PB11", "PB12";
++				function = "spi1";
++			};
++
++			/omit-if-no-ref/
++			spi1_pd_pins: spi1-pd-pins {
++				pins = "PD10", "PD11", "PD12", "PD13", "PD14", "PD15";
++				function = "spi1";
++			};
++
++			/omit-if-no-ref/
+ 			uart0_pb8_pins: uart0-pb8-pins {
+ 				pins = "PB8", "PB9";
+ 				function = "uart0";
+@@ -167,6 +252,17 @@
+ 			};
+ 		};
+ 
++		pwm: pwm@2000c00 {
++			compatible = "allwinner,sun20i-d1-pwm";
++			reg = <0x2000c00 0x400>;
++			interrupts = <34 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_PWM>, <&osc24M>;
++			clock-names = "bus", "mod";
++			resets = <&ccu RST_BUS_PWM>;
++			status = "disabled";
++			#pwm-cells = <3>;
++		};
++
+ 		ccu: clock-controller@2001000 {
+ 			compatible = "allwinner,sun20i-d1-ccu";
+ 			reg = <0x2001000 0x1000>;
+@@ -178,6 +274,33 @@
+ 			#reset-cells = <1>;
+ 		};
+ 
++		ledc: led-controller@2008000 {
++			compatible = "allwinner,sun20i-d1-ledc",
++				     "allwinner,sun50i-a100-ledc";
++			reg = <0x2008000 0x400>;
++			interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_LEDC>, <&ccu CLK_LEDC>;
++			clock-names = "bus", "mod";
++			resets = <&ccu RST_BUS_LEDC>;
++			dmas = <&dma 42>;
++			dma-names = "tx";
++			status = "disabled";
++			#address-cells = <1>;
++			#size-cells = <0>;
++		};
++
++		ths: temperature-sensor@2009400 {
++			compatible = "allwinner,sun20i-d1-ths";
++			reg = <0x2009400 0x400>;
++			interrupts = <74 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_THS>, <&osc24M>;
++			clock-names = "bus", "mod";
++			resets = <&ccu RST_BUS_THS>;
++			nvmem-cells = <&ths_calib>;
++			nvmem-cell-names = "calibration";
++			#thermal-sensor-cells = <0>;
++		};
++
+ 		lradc: keys@2009800 {
+ 			compatible = "allwinner,sun20i-d1-lradc",
+ 				     "allwinner,sun50i-r329-lradc";
+@@ -188,11 +311,30 @@
+ 			status = "disabled";
+ 		};
+ 
++		iommu: iommu@2010000 {
++			compatible = "allwinner,sun20i-d1-iommu";
++			reg = <0x2010000 0x10000>;
++			interrupts = <80 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_IOMMU>;
++			#iommu-cells = <1>;
++		};
++
+ 		codec: audio-codec@2030000 {
+-			compatible = "simple-mfd", "syscon";
++			compatible = "allwinner,sun20i-d1-codec", "simple-mfd", "syscon";
+ 			reg = <0x2030000 0x1000>;
++			interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_AUDIO>,
++				 <&ccu CLK_AUDIO_ADC>,
++				 <&ccu CLK_AUDIO_DAC>,
++				 <&osc24M>,
++				 <&rtc CLK_OSC32K>;
++			clock-names = "bus", "adc", "dac", "hosc", "losc";
++			resets = <&ccu RST_BUS_AUDIO>;
++			dmas = <&dma 7>, <&dma 7>;
++			dma-names = "rx", "tx";
+ 			#address-cells = <1>;
+ 			#size-cells = <1>;
++			#sound-dai-cells = <0>;
+ 
+ 			regulators@2030348 {
+ 				compatible = "allwinner,sun20i-d1-analog-ldos";
+@@ -208,6 +350,21 @@
+ 			};
+ 		};
+ 
++		dmic: dmic@2031000 {
++			compatible = "allwinner,sun20i-d1-dmic",
++				     "allwinner,sun50i-h6-dmic";
++			reg = <0x2031000 0x400>;
++			interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_DMIC>,
++				 <&ccu CLK_DMIC>;
++			clock-names = "bus", "mod";
++			resets = <&ccu RST_BUS_DMIC>;
++			dmas = <&dma 8>;
++			dma-names = "rx";
++			status = "disabled";
++			#sound-dai-cells = <0>;
++		};
++
+ 		i2s0: i2s@2032000 {
+ 			compatible = "allwinner,sun20i-d1-i2s",
+ 				     "allwinner,sun50i-r329-i2s";
+@@ -238,6 +395,7 @@
+ 			#sound-dai-cells = <0>;
+ 		};
+ 
++		// TODO: how to integrate ASRC? same or separate node?
+ 		i2s2: i2s@2034000 {
+ 			compatible = "allwinner,sun20i-d1-i2s",
+ 				     "allwinner,sun50i-r329-i2s";
+@@ -253,6 +411,22 @@
+ 			#sound-dai-cells = <0>;
+ 		};
+ 
++		// TODO: add receive functionality
++		spdif: spdif@2036000 {
++			compatible = "allwinner,sun20i-d1-spdif";
++			reg = <0x2036000 0x400>;
++			interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_SPDIF>,
++				 <&ccu CLK_SPDIF_RX>,
++				 <&ccu CLK_SPDIF_TX>;
++			clock-names = "apb", "rx", "tx";
++			resets = <&ccu RST_BUS_SPDIF>;
++			dmas = <&dma 2>, <&dma 2>;
++			dma-names = "rx", "tx";
++			status = "disabled";
++			#sound-dai-cells = <0>;
++		};
++
+ 		timer: timer@2050000 {
+ 			compatible = "allwinner,sun20i-d1-timer",
+ 				     "allwinner,sun8i-a23-timer";
+@@ -457,6 +631,18 @@
+ 			};
+ 		};
+ 
++		crypto: crypto@3040000 {
++			compatible = "allwinner,sun20i-d1-crypto";
++			reg = <0x3040000 0x800>;
++			interrupts = <68 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_CE>,
++				 <&ccu CLK_CE>,
++				 <&ccu CLK_MBUS_CE>,
++				 <&rtc CLK_IOSC>;
++			clock-names = "bus", "mod", "ram", "trng";
++			resets = <&ccu RST_BUS_CE>;
++		};
++
+ 		mbus: dram-controller@3102000 {
+ 			compatible = "allwinner,sun20i-d1-mbus";
+ 			reg = <0x3102000 0x1000>,
+@@ -525,6 +711,39 @@
+ 			#size-cells = <0>;
+ 		};
+ 
++		spi0: spi@4025000 {
++			compatible = "allwinner,sun20i-d1-spi",
++				     "allwinner,sun50i-r329-spi";
++			reg = <0x4025000 0x1000>;
++			interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
++			clock-names = "ahb", "mod";
++			resets = <&ccu RST_BUS_SPI0>;
++			dmas = <&dma 22>, <&dma 22>;
++			dma-names = "rx", "tx";
++			num-cs = <1>;
++			status = "disabled";
++			#address-cells = <1>;
++			#size-cells = <0>;
++		};
++
++		spi1: spi@4026000 {
++			compatible = "allwinner,sun20i-d1-spi-dbi",
++				     "allwinner,sun50i-r329-spi-dbi",
++				     "allwinner,sun50i-r329-spi";
++			reg = <0x4026000 0x1000>;
++			interrupts = <32 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
++			clock-names = "ahb", "mod";
++			resets = <&ccu RST_BUS_SPI1>;
++			dmas = <&dma 23>, <&dma 23>;
++			dma-names = "rx", "tx";
++			num-cs = <1>;
++			status = "disabled";
++			#address-cells = <1>;
++			#size-cells = <0>;
++		};
++
+ 		usb_otg: usb@4100000 {
+ 			compatible = "allwinner,sun20i-d1-musb",
+ 				     "allwinner,sun8i-a33-musb";
+@@ -653,6 +872,7 @@
+ 				 <&display_clocks CLK_MIXER0>;
+ 			clock-names = "bus", "mod";
+ 			resets = <&display_clocks RST_MIXER0>;
++			iommus = <&iommu 2>;
+ 
+ 			ports {
+ 				#address-cells = <1>;
+@@ -675,6 +895,7 @@
+ 				 <&display_clocks CLK_MIXER1>;
+ 			clock-names = "bus", "mod";
+ 			resets = <&display_clocks RST_MIXER1>;
++			iommus = <&iommu 2>;
+ 
+ 			ports {
+ 				#address-cells = <1>;
+@@ -690,6 +911,40 @@
+ 			};
+ 		};
+ 
++		dsi: dsi@5450000 {
++			compatible = "allwinner,sun20i-d1-mipi-dsi",
++				     "allwinner,sun50i-a100-mipi-dsi";
++			reg = <0x5450000 0x1000>;
++			interrupts = <108 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_MIPI_DSI>,
++				 <&tcon_top CLK_TCON_TOP_DSI>;
++			clock-names = "bus", "mod";
++			resets = <&ccu RST_BUS_MIPI_DSI>;
++			phys = <&dphy>;
++			phy-names = "dphy";
++			status = "disabled";
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			port {
++				dsi_in_tcon_lcd0: endpoint {
++					remote-endpoint = <&tcon_lcd0_out_dsi>;
++				};
++			};
++		};
++
++		dphy: phy@5451000 {
++			compatible = "allwinner,sun20i-d1-mipi-dphy",
++				     "allwinner,sun50i-a100-mipi-dphy";
++			reg = <0x5451000 0x1000>;
++			interrupts = <108 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_MIPI_DSI>,
++				 <&ccu CLK_MIPI_DSI>;
++			clock-names = "bus", "mod";
++			resets = <&ccu RST_BUS_MIPI_DSI>;
++			#phy-cells = <0>;
++		};
++
+ 		tcon_top: tcon-top@5460000 {
+ 			compatible = "allwinner,sun20i-d1-tcon-top";
+ 			reg = <0x5460000 0x1000>;
+@@ -770,6 +1025,10 @@
+ 
+ 				tcon_top_hdmi_out: port@5 {
+ 					reg = <5>;
++
++					tcon_top_hdmi_out_hdmi: endpoint {
++						remote-endpoint = <&hdmi_in_tcon_top>;
++					};
+ 				};
+ 			};
+ 		};
+@@ -785,6 +1044,8 @@
+ 			resets = <&ccu RST_BUS_TCON_LCD0>,
+ 				 <&ccu RST_BUS_LVDS0>;
+ 			reset-names = "lcd", "lvds";
++			phys = <&dphy>;
++			phy-names = "lvds0";
+ 			#clock-cells = <0>;
+ 
+ 			ports {
+@@ -809,6 +1070,13 @@
+ 
+ 				tcon_lcd0_out: port@1 {
+ 					reg = <1>;
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					tcon_lcd0_out_dsi: endpoint@1 {
++						reg = <1>;
++						remote-endpoint = <&dsi_in_tcon_lcd0>;
++					};
+ 				};
+ 			};
+ 		};
+@@ -853,6 +1121,50 @@
+ 			};
+ 		};
+ 
++		hdmi: hdmi@5500000 {
++			compatible = "allwinner,sun20i-d1-dw-hdmi";
++			reg = <0x5500000 0x10000>;
++			reg-io-width = <1>;
++			interrupts = <109 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_HDMI>,
++				 <&ccu CLK_HDMI_24M>,
++				 <&ccu CLK_HDMI_CEC>;
++			clock-names = "iahb", "isfr", "cec";
++			resets = <&ccu RST_BUS_HDMI_SUB>;
++			reset-names = "ctrl";
++			phys = <&hdmi_phy>;
++			phy-names = "phy";
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@0 {
++					reg = <0>;
++
++					hdmi_in_tcon_top: endpoint {
++						remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
++					};
++				};
++
++				hdmi_out: port@1 {
++					reg = <1>;
++				};
++			};
++		};
++
++		hdmi_phy: phy@5510000 {
++			compatible = "allwinner,sun20i-d1-hdmi-phy";
++			reg = <0x5510000 0x10000>;
++			clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_24M>;
++			clock-names = "bus", "mod";
++			resets = <&ccu RST_BUS_HDMI_MAIN>;
++			reset-names = "phy";
++			status = "disabled";
++			#phy-cells = <0>;
++		};
++
+ 		riscv_wdt: watchdog@6011000 {
+ 			compatible = "allwinner,sun20i-d1-wdt";
+ 			reg = <0x6011000 0x20>;
diff --git a/package/boot/uboot-d1/patches/0089-sunxi-riscv-Add-defconfigs-for-several-boards.patch b/package/boot/uboot-d1/patches/0089-sunxi-riscv-Add-defconfigs-for-several-boards.patch
new file mode 100644
index 00000000000000..a1c2ac9ad90d92
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0089-sunxi-riscv-Add-defconfigs-for-several-boards.patch
@@ -0,0 +1,108 @@
+From 0a4e7a1a19dd505bc5b6ff887b2ce39983aaa92d Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Mon, 31 Oct 2022 23:27:08 -0500
+Subject: [PATCH 89/90] sunxi: riscv: Add defconfigs for several boards
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ configs/devterm_r_01_defconfig       | 10 ++++++++++
+ configs/dongshan_nezha_stu_defconfig | 13 +++++++++++++
+ configs/lichee_rv_86_panel_defconfig | 13 +++++++++++++
+ configs/lichee_rv_dock_defconfig     | 10 ++++++++++
+ configs/mangopi_mq_pro_defconfig     | 10 ++++++++++
+ configs/nezha_defconfig              | 13 +++++++++++++
+ 6 files changed, 69 insertions(+)
+ create mode 100644 configs/devterm_r_01_defconfig
+ create mode 100644 configs/dongshan_nezha_stu_defconfig
+ create mode 100644 configs/lichee_rv_86_panel_defconfig
+ create mode 100644 configs/lichee_rv_dock_defconfig
+ create mode 100644 configs/mangopi_mq_pro_defconfig
+ create mode 100644 configs/nezha_defconfig
+
+--- /dev/null
++++ b/configs/devterm_r_01_defconfig
+@@ -0,0 +1,10 @@
++CONFIG_RISCV=y
++CONFIG_DEFAULT_DEVICE_TREE="sun20i-d1-devterm-v3.14"
++CONFIG_TARGET_SUN20I_D1=y
++CONFIG_ARCH_RV64I=y
++CONFIG_RISCV_SMODE=y
++# CONFIG_SPL_SMP is not set
++CONFIG_SYS_SPL_MALLOC=y
++CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0
++# CONFIG_SYS_I2C_MVTWSI is not set
++CONFIG_DM_REGULATOR_FIXED=y
+--- /dev/null
++++ b/configs/dongshan_nezha_stu_defconfig
+@@ -0,0 +1,13 @@
++CONFIG_RISCV=y
++CONFIG_DEFAULT_DEVICE_TREE="sun20i-d1-dongshan-nezha-stu"
++CONFIG_TARGET_SUN20I_D1=y
++CONFIG_ARCH_RV64I=y
++CONFIG_RISCV_SMODE=y
++# CONFIG_SPL_SMP is not set
++CONFIG_SYS_SPL_MALLOC=y
++CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0
++CONFIG_NET_RANDOM_ETHADDR=y
++# CONFIG_SYS_I2C_MVTWSI is not set
++CONFIG_PHY_REALTEK=y
++CONFIG_SUN8I_EMAC=y
++CONFIG_DM_REGULATOR_FIXED=y
+--- /dev/null
++++ b/configs/lichee_rv_86_panel_defconfig
+@@ -0,0 +1,13 @@
++CONFIG_RISCV=y
++CONFIG_DEFAULT_DEVICE_TREE="sun20i-d1-lichee-rv-86-panel-480p"
++CONFIG_TARGET_SUN20I_D1=y
++CONFIG_ARCH_RV64I=y
++CONFIG_RISCV_SMODE=y
++# CONFIG_SPL_SMP is not set
++CONFIG_SYS_SPL_MALLOC=y
++CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0
++CONFIG_NET_RANDOM_ETHADDR=y
++# CONFIG_SYS_I2C_MVTWSI is not set
++CONFIG_PHY_REALTEK=y
++CONFIG_SUN8I_EMAC=y
++CONFIG_DM_REGULATOR_FIXED=y
+--- /dev/null
++++ b/configs/lichee_rv_dock_defconfig
+@@ -0,0 +1,10 @@
++CONFIG_RISCV=y
++CONFIG_DEFAULT_DEVICE_TREE="sun20i-d1-lichee-rv-dock"
++CONFIG_TARGET_SUN20I_D1=y
++CONFIG_ARCH_RV64I=y
++CONFIG_RISCV_SMODE=y
++# CONFIG_SPL_SMP is not set
++CONFIG_SYS_SPL_MALLOC=y
++CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0
++# CONFIG_SYS_I2C_MVTWSI is not set
++CONFIG_DM_REGULATOR_FIXED=y
+--- /dev/null
++++ b/configs/mangopi_mq_pro_defconfig
+@@ -0,0 +1,10 @@
++CONFIG_RISCV=y
++CONFIG_DEFAULT_DEVICE_TREE="sun20i-d1-mangopi-mq-pro"
++CONFIG_TARGET_SUN20I_D1=y
++CONFIG_ARCH_RV64I=y
++CONFIG_RISCV_SMODE=y
++# CONFIG_SPL_SMP is not set
++CONFIG_SYS_SPL_MALLOC=y
++CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0
++# CONFIG_SYS_I2C_MVTWSI is not set
++CONFIG_DM_REGULATOR_FIXED=y
+--- /dev/null
++++ b/configs/nezha_defconfig
+@@ -0,0 +1,13 @@
++CONFIG_RISCV=y
++CONFIG_DEFAULT_DEVICE_TREE="sun20i-d1-nezha"
++CONFIG_TARGET_SUN20I_D1=y
++CONFIG_ARCH_RV64I=y
++CONFIG_RISCV_SMODE=y
++# CONFIG_SPL_SMP is not set
++CONFIG_SYS_SPL_MALLOC=y
++CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0
++CONFIG_NET_RANDOM_ETHADDR=y
++# CONFIG_SYS_I2C_MVTWSI is not set
++CONFIG_PHY_REALTEK=y
++CONFIG_SUN8I_EMAC=y
++CONFIG_DM_REGULATOR_FIXED=y
diff --git a/package/boot/uboot-d1/patches/0090-drivers-phy-fix-typo.patch b/package/boot/uboot-d1/patches/0090-drivers-phy-fix-typo.patch
new file mode 100644
index 00000000000000..c9c3b9b959e8d5
--- /dev/null
+++ b/package/boot/uboot-d1/patches/0090-drivers-phy-fix-typo.patch
@@ -0,0 +1,21 @@
+From 62419798c137c9eec2d2c1011e417d1520aecffb Mon Sep 17 00:00:00 2001
+From: Zoltan HERPAI <wigyori@uid0.hu>
+Date: Tue, 6 Jun 2023 19:46:30 +0000
+Subject: [PATCH 90/90] drivers: phy: fix typo
+
+Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
+---
+ drivers/phy/allwinner/Kconfig | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/phy/allwinner/Kconfig
++++ b/drivers/phy/allwinner/Kconfig
+@@ -3,7 +3,7 @@
+ #
+ config PHY_SUN4I_USB
+ 	bool "Allwinner Sun4I USB PHY driver"
+-	depends on depends on BOARD_SUNXI
++	depends on BOARD_SUNXI
+ 	default y
+ 	select DM_REGULATOR
+ 	select PHY
diff --git a/package/boot/uboot-d1/patches/100-mkimage-check-environment-for-dtc-binary-location.patch b/package/boot/uboot-d1/patches/100-mkimage-check-environment-for-dtc-binary-location.patch
new file mode 100644
index 00000000000000..789172f21b41e3
--- /dev/null
+++ b/package/boot/uboot-d1/patches/100-mkimage-check-environment-for-dtc-binary-location.patch
@@ -0,0 +1,35 @@
+From 637800493945ffed2f454756300437a4ec86e3b1 Mon Sep 17 00:00:00 2001
+From: Hauke Mehrtens <hauke@hauke-m.de>
+Date: Wed, 19 Jul 2017 22:23:15 +0200
+Subject: mkimage: check environment for dtc binary location
+
+Currently mkimage assumes the dtc binary is in the path and fails
+otherwise. This patch makes it check the DTC environment variable first
+for the dtc binary and then fall back to the default path. This makes
+it possible to call the u-boot build with make DTC=... and build a fit
+image with the dtc binary not being the the default path.
+
+Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
+Cc: Simon Glass <sjg@chromium.org>
+---
+ tools/fit_image.c | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+--- a/tools/fit_image.c
++++ b/tools/fit_image.c
+@@ -729,9 +729,14 @@ static int fit_handle_file(struct image_
+ 		}
+ 		*cmd = '\0';
+ 	} else if (params->datafile) {
++		const char* dtc = getenv("DTC");
++
++		if (!dtc)
++			dtc = MKIMAGE_DTC;
++
+ 		/* dtc -I dts -O dtb -p 500 -o tmpfile datafile */
+ 		snprintf(cmd, sizeof(cmd), "%s %s -o \"%s\" \"%s\"",
+-			 MKIMAGE_DTC, params->dtc, tmpfile, params->datafile);
++			 dtc, params->dtc, tmpfile, params->datafile);
+ 		debug("Trying to execute \"%s\"\n", cmd);
+ 	} else {
+ 		snprintf(cmd, sizeof(cmd), "cp \"%s\" \"%s\"",
diff --git a/package/boot/uboot-d1/patches/130-fix-mkimage-host-build.patch b/package/boot/uboot-d1/patches/130-fix-mkimage-host-build.patch
new file mode 100644
index 00000000000000..cd65c1321fc320
--- /dev/null
+++ b/package/boot/uboot-d1/patches/130-fix-mkimage-host-build.patch
@@ -0,0 +1,24 @@
+--- a/tools/image-host.c
++++ b/tools/image-host.c
+@@ -1125,6 +1125,7 @@ static int fit_config_add_verification_d
+  * 2) get public key (X509_get_pubkey)
+  * 3) provide der format (d2i_RSAPublicKey)
+  */
++#ifdef CONFIG_TOOLS_LIBCRYPTO
+ static int read_pub_key(const char *keydir, const void *name,
+ 			unsigned char **pubkey, int *pubkey_len)
+ {
+@@ -1178,6 +1179,13 @@ err_cert:
+ 	fclose(f);
+ 	return ret;
+ }
++#else
++static int read_pub_key(const char *keydir, const void *name,
++			unsigned char **pubkey, int *pubkey_len)
++{
++	return -ENOSYS;
++}
++#endif
+ 
+ int fit_pre_load_data(const char *keydir, void *keydest, void *fit)
+ {
diff --git a/package/boot/uboot-d1/patches/211-no-kwbimage.patch b/package/boot/uboot-d1/patches/211-no-kwbimage.patch
new file mode 100644
index 00000000000000..65d14f5bece8bd
--- /dev/null
+++ b/package/boot/uboot-d1/patches/211-no-kwbimage.patch
@@ -0,0 +1,10 @@
+--- a/tools/Makefile
++++ b/tools/Makefile
+@@ -119,7 +119,6 @@ dumpimage-mkimage-objs := aisimage.o \
+ 			imximage.o \
+ 			imx8image.o \
+ 			imx8mimage.o \
+-			kwbimage.o \
+ 			lib/md5.o \
+ 			lpc32xximage.o \
+ 			mxsimage.o \
diff --git a/package/boot/uboot-d1/patches/300-force-pylibfdt-build.patch b/package/boot/uboot-d1/patches/300-force-pylibfdt-build.patch
new file mode 100644
index 00000000000000..e2312eaa5a59f9
--- /dev/null
+++ b/package/boot/uboot-d1/patches/300-force-pylibfdt-build.patch
@@ -0,0 +1,30 @@
+--- a/Makefile
++++ b/Makefile
+@@ -2045,26 +2045,7 @@ endif
+ # Check dtc and pylibfdt, if DTC is provided, else build them
+ PHONY += scripts_dtc
+ scripts_dtc: scripts_basic
+-	$(Q)if test "$(DTC)" = "$(DTC_INTREE)"; then \
+-		$(MAKE) $(build)=scripts/dtc; \
+-	else \
+-		if ! $(DTC) -v >/dev/null; then \
+-			echo '*** Failed to check dtc version: $(DTC)'; \
+-			false; \
+-		else \
+-			if test "$(call dtc-version)" -lt $(DTC_MIN_VERSION); then \
+-				echo '*** Your dtc is too old, please upgrade to dtc $(DTC_MIN_VERSION) or newer'; \
+-				false; \
+-			else \
+-				if [ -n "$(CONFIG_PYLIBFDT)" ]; then \
+-					if ! echo "import libfdt" | $(PYTHON3) 2>/dev/null; then \
+-						echo '*** pylibfdt does not seem to be available with $(PYTHON3)'; \
+-						false; \
+-					fi; \
+-				fi; \
+-			fi; \
+-		fi; \
+-	fi
++	$(MAKE) $(build)=scripts/dtc
+ 
+ # ---------------------------------------------------------------------------
+ quiet_cmd_cpp_lds = LDS     $@
diff --git a/package/boot/uboot-d1/uEnv-default.txt b/package/boot/uboot-d1/uEnv-default.txt
new file mode 100644
index 00000000000000..4f6f5fa172f69b
--- /dev/null
+++ b/package/boot/uboot-d1/uEnv-default.txt
@@ -0,0 +1,4 @@
+setenv loadkernel fatload mmc 0:1 \$kernel_addr_r Image
+setenv bootargs console=ttyS0,115200 earlycon=sbi root=/dev/mmcblk0p2 rootwait
+setenv uenvcmd run loadkernel \&\& booti \$kernel_addr_r - \$fdtcontroladdr
+run uenvcmd
diff --git a/package/boot/uboot-envtools/Makefile b/package/boot/uboot-envtools/Makefile
index 9647b38385308f..00aa4241625f52 100644
--- a/package/boot/uboot-envtools/Makefile
+++ b/package/boot/uboot-envtools/Makefile
@@ -9,15 +9,15 @@ include $(TOPDIR)/rules.mk
 
 PKG_NAME:=uboot-envtools
 PKG_DISTNAME:=u-boot
-PKG_VERSION:=2023.07.02
-PKG_RELEASE:=3
+PKG_VERSION:=2024.01
+PKG_RELEASE:=2
 
 PKG_SOURCE:=$(PKG_DISTNAME)-$(PKG_VERSION).tar.bz2
 PKG_SOURCE_URL:= \
     https://ftp.denx.de/pub/u-boot \
     https://mirror.cyberbits.eu/u-boot \
     ftp://ftp.denx.de/pub/u-boot
-PKG_HASH:=6b6a48581c14abb0f95bd87c1af4d740922406d7b801002a9f94727fdde021d5
+PKG_HASH:=b99611f1ed237bf3541bdc8434b68c96a6e05967061f992443cb30aabebef5b3
 PKG_SOURCE_SUBDIR:=$(PKG_DISTNAME)-$(PKG_VERSION)
 PKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_DISTNAME)-$(PKG_VERSION)
 
diff --git a/package/boot/uboot-envtools/files/ipq40xx b/package/boot/uboot-envtools/files/ipq40xx
index 8d993fae3668b3..8cada7334b326d 100644
--- a/package/boot/uboot-envtools/files/ipq40xx
+++ b/package/boot/uboot-envtools/files/ipq40xx
@@ -53,7 +53,8 @@ aruba,ap-303)
 aruba,ap-365)
 	ubootenv_add_uci_config "/dev/mtd8" "0x0" "0x10000" "0x10000"
 	;;
-buffalo,wtr-m2133hp)
+buffalo,wtr-m2133hp|\
+netgear,lbr20)
 	ubootenv_add_uci_config "/dev/mtd8" "0x0" "0x40000" "0x20000"
 	;;
 linksys,ea6350v3)
diff --git a/package/boot/uboot-envtools/files/mediatek_filogic b/package/boot/uboot-envtools/files/mediatek_filogic
index 7bbeb2fd5dcfa3..08d2bf782bdb1f 100644
--- a/package/boot/uboot-envtools/files/mediatek_filogic
+++ b/package/boot/uboot-envtools/files/mediatek_filogic
@@ -11,53 +11,62 @@ touch /etc/config/ubootenv
 
 board=$(board_name)
 
+ubootenv_add_mmc_default() {
+	local envdev="$(find_mmc_part "ubootenv" "${1:-mmcblk0}")"
+	ubootenv_add_uci_config "$envdev" "0x0" "0x40000" "0x40000" "1"
+	ubootenv_add_uci_config "$envdev" "0x40000" "0x40000" "0x40000" "1"
+}
+
+ubootenv_add_nor_default() {
+	local envdev="/dev/mtd$(find_mtd_index "u-boot-env")"
+	ubootenv_add_uci_config "$envdev" "0x0" "0x20000" "0x20000" "1"
+	ubootenv_add_uci_config "$envdev" "0x20000" "0x20000" "0x20000" "1"
+}
+
+ubootenv_add_ubi_default() {
+	. /lib/upgrade/nand.sh
+	local envubi=$(nand_find_ubi ubi)
+	local envdev=/dev/$(nand_find_volume $envubi ubootenv)
+	local envdev2=/dev/$(nand_find_volume $envubi ubootenv2)
+	ubootenv_add_uci_config "$envdev" "0x0" "0x1f000" "0x1f000" "1"
+	ubootenv_add_uci_config "$envdev2" "0x0" "0x1f000" "0x1f000" "1"
+}
+
 case "$board" in
 asus,rt-ax59u)
 	ubootenv_add_uci_config "/dev/mtd0" "0x100000" "0x20000" "0x20000"
 	;;
 bananapi,bpi-r3|\
-bananapi,bpi-r3-mini)
-	rootdev="$(cmdline_get_var root)"
-	rootdev="${rootdev##*/}"
-	rootdev="${rootdev%%p[0-9]*}"
-	case "$rootdev" in
+bananapi,bpi-r3-mini|\
+bananapi,bpi-r4)
+	. /lib/upgrade/common.sh
+
+	bootdev="$(fitblk_get_bootdev)"
+	case "$bootdev" in
+	ubi*)
+		ubootenv_add_ubi_default
+		;;
 	mmc*)
-		local envdev=$(find_mmc_part "ubootenv" $rootdev)
-		ubootenv_add_uci_config "$envdev" "0x0" "0x40000" "0x40000" "1"
-		ubootenv_add_uci_config "$envdev" "0x40000" "0x40000" "0x40000" "1"
+		ubootenv_add_mmc_default "${bootdev%%p[0-9]*}"
 		;;
 	mtd*)
-		local envdev=/dev/mtd$(find_mtd_index "u-boot-env")
-		ubootenv_add_uci_config "$envdev" "0x0" "0x20000" "0x20000" "1"
-		ubootenv_add_uci_config "$envdev" "0x20000" "0x20000" "0x20000" "1"
-		;;
-	ubi*)
-		. /lib/upgrade/nand.sh
-		local envubi=$(nand_find_ubi ubi)
-		local envdev=/dev/$(nand_find_volume $envubi ubootenv)
-		local envdev2=/dev/$(nand_find_volume $envubi ubootenv2)
-		ubootenv_add_uci_config "$envdev" "0x0" "0x1f000" "0x1f000" "1"
-		ubootenv_add_uci_config "$envdev2" "0x0" "0x1f000" "0x1f000" "1"
+		ubootenv_add_nor_default
 		;;
 	esac
 	;;
 cmcc,rax3000m)
 	case "$(cmdline_get_var root)" in
 	/dev/mmc*)
-		local envdev=$(find_mmc_part "ubootenv" "mmcblk0")
-		ubootenv_add_uci_config "$envdev" "0x0" "0x40000" "0x40000" "1"
-		ubootenv_add_uci_config "$envdev" "0x40000" "0x40000" "0x40000" "1"
+		ubootenv_add_mmc_default
 		;;
 	*)
-		. /lib/upgrade/nand.sh
-		local envubi=$(nand_find_ubi ubi)
-		local envdev=/dev/$(nand_find_volume $envubi ubootenv)
-		local envdev2=/dev/$(nand_find_volume $envubi ubootenv2)
-		ubootenv_add_uci_config "$envdev" "0x0" "0x1f000" "0x1f000" "1"
-		ubootenv_add_uci_config "$envdev2" "0x0" "0x1f000" "0x1f000" "1"
+		ubootenv_add_ubi_default
 		;;
 	esac
 	;;
+comfast,cf-e393ax)
+	ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x20000" "0x80000"
+	;;
 cetron,ct3003|\
 netgear,wax220|\
 zbtlink,zbt-z8102ax|\
@@ -72,13 +81,9 @@ tplink,tl-xdr6086|\
 tplink,tl-xdr6088|\
 xiaomi,mi-router-ax3000t-ubootmod|\
 xiaomi,mi-router-wr30u-ubootmod|\
-xiaomi,redmi-router-ax6000-ubootmod)
-	. /lib/upgrade/nand.sh
-	local envubi=$(nand_find_ubi ubi)
-	local envdev=/dev/$(nand_find_volume $envubi ubootenv)
-	local envdev2=/dev/$(nand_find_volume $envubi ubootenv2)
-	ubootenv_add_uci_config "$envdev" "0x0" "0x1f000" "0x20000" "1"
-	ubootenv_add_uci_config "$envdev2" "0x0" "0x1f000" "0x20000" "1"
+xiaomi,redmi-router-ax6000-ubootmod|\
+zyxel,ex5601-t0-ubootmod)
+	ubootenv_add_ubi_default
 	;;
 glinet,gl-mt2500|\
 glinet,gl-mt6000)
@@ -111,14 +116,6 @@ zyxel,ex5601-t0)
 	local envdev=/dev/mtd$(find_mtd_index "u-boot-env")
 	ubootenv_add_uci_config "$envdev" "0x0" "0x20000" "0x40000" "2"
 	;;
-zyxel,ex5601-t0-ubootmod)
-        . /lib/upgrade/nand.sh
-        local envubi=$(nand_find_ubi ubi)
-        local envdev=/dev/$(nand_find_volume $envubi ubootenv)
-        local envdev2=/dev/$(nand_find_volume $envubi ubootenv2)
-        ubootenv_add_uci_config "$envdev" "0x0" "0x1f000" "0x20000" "1"
-        ubootenv_add_uci_config "$envdev2" "0x0" "0x1f000" "0x20000" "1"
-        ;;
 zyxel,ex5700-telenor)
 	ubootenv_add_uci_config "/dev/ubootenv" "0x0" "0x4000" "0x4000" "1"
 	;;
diff --git a/package/boot/uboot-envtools/files/mediatek_mt7622 b/package/boot/uboot-envtools/files/mediatek_mt7622
index fdf0d331fc569b..c8d385748449f3 100644
--- a/package/boot/uboot-envtools/files/mediatek_mt7622
+++ b/package/boot/uboot-envtools/files/mediatek_mt7622
@@ -9,6 +9,21 @@ touch /etc/config/ubootenv
 . /lib/uboot-envtools.sh
 . /lib/functions.sh
 
+ubootenv_add_mmc_default() {
+	local envdev="$(find_mmc_part "ubootenv" "${1:-mmcblk0}")"
+	ubootenv_add_uci_config "$envdev" "0x0" "0x80000" "0x80000" "1"
+	ubootenv_add_uci_config "$envdev" "0x80000" "0x80000" "0x80000" "1"
+}
+
+ubootenv_add_ubi_default() {
+	. /lib/upgrade/nand.sh
+	local envubi=$(nand_find_ubi ubi)
+	local envdev=/dev/$(nand_find_volume $envubi ubootenv)
+	local envdev2=/dev/$(nand_find_volume $envubi ubootenv2)
+	ubootenv_add_uci_config "$envdev" "0x0" "0x1f000" "0x1f000" "1"
+	ubootenv_add_uci_config "$envdev2" "0x0" "0x1f000" "0x1f000" "1"
+}
+
 board=$(board_name)
 
 case "$board" in
@@ -17,22 +32,17 @@ dlink,eagle-pro-ai-r32-a1)
 	ubootenv_add_uci_config "/dev/mtd3" "0x0" "0x2000" "0x2000"
 	;;
 linksys,e8450-ubi)
-	ubootenv_add_uci_config "/dev/ubi0_0" "0x0" "0x1f000" "0x1f000" "1"
-	ubootenv_add_uci_config "/dev/ubi0_1" "0x0" "0x1f000" "0x1f000" "1"
+	ubootenv_add_ubi_default
 	;;
 bananapi,bpi-r64)
-	rootdev="$(cmdline_get_var root)"
-	rootdev="${rootdev##*/}"
-	rootdev="${rootdev%%p[0-9]*}"
-	case "$rootdev" in
+	. /lib/upgrade/common.sh
+	bootdev="$(fitblk_get_bootdev)"
+	case "$bootdev" in
 	mmc*)
-		local envdev=$(find_mmc_part "ubootenv" $rootdev)
-		ubootenv_add_uci_config "$envdev" "0x0" "0x80000" "0x80000" "1"
-		ubootenv_add_uci_config "$envdev" "0x80000" "0x80000" "0x80000" "1"
+		ubootenv_add_mmc_default "${bootdev%p[0-9]*}"
 		;;
 	ubi*)
-		ubootenv_add_uci_config "/dev/ubi0_0" "0x0" "0x1f000" "0x1f000" "1"
-		ubootenv_add_uci_config "/dev/ubi0_1" "0x0" "0x1f000" "0x1f000" "1"
+		ubootenv_add_ubi_default
 		;;
 	esac
 	;;
@@ -42,8 +52,10 @@ buffalo,wsr-2533dhp2)
 ruijie,rg-ew3200gx-pro)
 	ubootenv_add_uci_config "/dev/mtd3" "0x0" "0x20000" "0x20000"
 	;;
-ubnt,unifi-6-lr-ubootmod)
-	ubootenv_add_uci_config "/dev/mtd2" "0x0" "0x4000" "0x1000"
+ubnt,unifi-6-lr-v1-ubootmod|\
+ubnt,unifi-6-lr-v2-ubootmod|\
+ubnt,unifi-6-lr-v3-ubootmod)
+	ubootenv_add_uci_config "/dev/mtd$(find_mtd_index "u-boot-env")" "0x0" "0x4000" "0x1000"
 	;;
 xiaomi,redmi-router-ax6s)
 	ubootenv_add_uci_config "/dev/mtd3" "0x0" "0x10000" "0x40000"
diff --git a/package/boot/uboot-envtools/files/mediatek_mt7623 b/package/boot/uboot-envtools/files/mediatek_mt7623
index fd2a01006a8e08..008aff57853c6d 100644
--- a/package/boot/uboot-envtools/files/mediatek_mt7623
+++ b/package/boot/uboot-envtools/files/mediatek_mt7623
@@ -14,9 +14,8 @@ board=$(board_name)
 case "$board" in
 bananapi,bpi-r2)
 	. /lib/upgrade/common.sh
-	export_bootdevice
-	export_partdevice ubootpart 1
-	ubootenv_add_uci_config "/dev/$ubootpart" "0xb0000" "0x10000" "0x10000" "1"
+	bootdev="$(fitblk_get_bootdev)"
+	ubootenv_add_uci_config "/dev/${bootdev%p[0-9]*}p1" "0xb0000" "0x10000" "0x10000" "1"
 	;;
 unielec,u7623-02)
 	ubootenv_add_uci_config "/dev/mmcblk0p1" "0xc0000" "0x10000" "0x10000" "1"
diff --git a/package/boot/uboot-envtools/files/qualcommax_ipq60xx b/package/boot/uboot-envtools/files/qualcommax_ipq60xx
new file mode 100644
index 00000000000000..df19a3033577b2
--- /dev/null
+++ b/package/boot/uboot-envtools/files/qualcommax_ipq60xx
@@ -0,0 +1,22 @@
+[ -e /etc/config/ubootenv ] && exit 0
+
+touch /etc/config/ubootenv
+
+. /lib/uboot-envtools.sh
+. /lib/functions.sh
+
+board=$(board_name)
+
+case "$board" in
+8devices,mango-dvk|\
+8devices,mango-dvk-sfp)
+	idx="$(find_mtd_index 0:APPSBLENV)"
+	[ -n "$idx" ] && \
+		ubootenv_add_uci_config "/dev/mtd$idx" "0x0" "0x10000" "0x10000"
+	;;
+esac
+
+config_load ubootenv
+config_foreach ubootenv_add_app_config
+
+exit 0
diff --git a/package/boot/uboot-envtools/files/qualcommax_ipq807x b/package/boot/uboot-envtools/files/qualcommax_ipq807x
index bcedfd9adc91ce..86e7062cfc3f47 100644
--- a/package/boot/uboot-envtools/files/qualcommax_ipq807x
+++ b/package/boot/uboot-envtools/files/qualcommax_ipq807x
@@ -30,7 +30,8 @@ edimax,cax1800)
 		ubootenv_add_uci_config "/dev/mtd$idx" "0x0" "0x10000" "0x20000"
 	;;
 linksys,mx4200v1|\
-linksys,mx4200v2)
+linksys,mx4200v2|\
+linksys,mx5300)
 	idx="$(find_mtd_index u_env)"
 	[ -n "$idx" ] && \
 		ubootenv_add_uci_config "/dev/mtd$idx" "0x0" "0x40000" "0x20000" "2"
diff --git a/package/boot/uboot-envtools/patches/002-Revert-tools-env-use-run-to-store-lockfile.patch b/package/boot/uboot-envtools/patches/002-Revert-tools-env-use-run-to-store-lockfile.patch
index ace7cdc68107e7..e843e4252bb430 100644
--- a/package/boot/uboot-envtools/patches/002-Revert-tools-env-use-run-to-store-lockfile.patch
+++ b/package/boot/uboot-envtools/patches/002-Revert-tools-env-use-run-to-store-lockfile.patch
@@ -10,8 +10,6 @@ This reverts upstream commit
  tools/env/fw_env_main.c | 6 +++---
  1 file changed, 3 insertions(+), 3 deletions(-)
 
-diff --git a/tools/env/fw_env_main.c b/tools/env/fw_env_main.c
-index 0b201b9e62..1d193bd437 100644
 --- a/tools/env/fw_env_main.c
 +++ b/tools/env/fw_env_main.c
 @@ -73,7 +73,7 @@ void usage_printenv(void)
@@ -32,7 +30,7 @@ index 0b201b9e62..1d193bd437 100644
  		" -s, --script         batch mode to minimize writes\n"
  		"\n"
  		"Examples:\n"
-@@ -206,7 +206,7 @@ int parse_setenv_args(int argc, char *argv[])
+@@ -206,7 +206,7 @@ int parse_setenv_args(int argc, char *ar
  
  int main(int argc, char *argv[])
  {
@@ -41,4 +39,3 @@ index 0b201b9e62..1d193bd437 100644
  	int lockfd = -1;
  	int retval = EXIT_SUCCESS;
  	char *_cmdname;
-
diff --git a/package/boot/uboot-envtools/patches/011-fw_env-keep-calling-read-until-whole-flash-block-is-.patch b/package/boot/uboot-envtools/patches/011-fw_env-keep-calling-read-until-whole-flash-block-is-.patch
new file mode 100644
index 00000000000000..af1c32fe91cb9f
--- /dev/null
+++ b/package/boot/uboot-envtools/patches/011-fw_env-keep-calling-read-until-whole-flash-block-is-.patch
@@ -0,0 +1,75 @@
+From 9e3003f79d168eac7ee65cd457e3904e2fb4eea8 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Wed, 13 Dec 2023 13:13:54 +0100
+Subject: [PATCH] fw_env: keep calling read() until whole flash block is read
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+It's totally valid for read() to provide less bytes than requested
+maximum. It may happen if there is no more data available yet or source
+pushes data in small chunks.
+
+This actually happens when trying to read env data from NVMEM device.
+Kernel may provide NVMEM content in page size parts (like 4096 B).
+
+This fixes warnings like:
+Warning on /sys/bus/nvmem/devices/u-boot-env0/nvmem: Attempted to read 16384 bytes but got 4096
+Warning on /sys/bus/nvmem/devices/u-boot-env0/nvmem: Attempted to read 12288 bytes but got 4096
+Warning on /sys/bus/nvmem/devices/u-boot-env0/nvmem: Attempted to read 8192 bytes but got 4096
+
+Since the main loop in flash_read_buf() is used to read blocks this
+patch adds a new nested one.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+---
+ tools/env/fw_env.c | 34 +++++++++++++++-------------------
+ 1 file changed, 15 insertions(+), 19 deletions(-)
+
+--- a/tools/env/fw_env.c
++++ b/tools/env/fw_env.c
+@@ -948,29 +948,25 @@ static int flash_read_buf(int dev, int f
+ 		 */
+ 		lseek(fd, blockstart + block_seek, SEEK_SET);
+ 
+-		rc = read(fd, buf + processed, readlen);
+-		if (rc == -1) {
+-			fprintf(stderr, "Read error on %s: %s\n",
+-				DEVNAME(dev), strerror(errno));
+-			return -1;
+-		}
++		while (readlen) {
++			rc = read(fd, buf + processed, readlen);
++			if (rc == -1) {
++				fprintf(stderr, "Read error on %s: %s\n",
++					DEVNAME(dev), strerror(errno));
++				return -1;
++			}
+ #ifdef DEBUG
+-		fprintf(stderr, "Read 0x%x bytes at 0x%llx on %s\n",
+-			rc, (unsigned long long)blockstart + block_seek,
+-			DEVNAME(dev));
++			fprintf(stderr, "Read 0x%x bytes at 0x%llx on %s\n",
++				rc, (unsigned long long)blockstart + block_seek,
++				DEVNAME(dev));
+ #endif
+-		processed += rc;
+-		if (rc != readlen) {
+-			fprintf(stderr,
+-				"Warning on %s: Attempted to read %zd bytes but got %d\n",
+-				DEVNAME(dev), readlen, rc);
++			processed += rc;
+ 			readlen -= rc;
+-			block_seek += rc;
+-		} else {
+-			blockstart += blocklen;
+-			readlen = min(blocklen, count - processed);
+-			block_seek = 0;
+ 		}
++
++		blockstart += blocklen;
++		readlen = min(blocklen, count - processed);
++		block_seek = 0;
+ 	}
+ 
+ 	return processed;
diff --git a/package/boot/uboot-envtools/patches/012-fw_env-autodetect-NAND-erase-size-and-env-sectors.patch b/package/boot/uboot-envtools/patches/012-fw_env-autodetect-NAND-erase-size-and-env-sectors.patch
new file mode 100644
index 00000000000000..78f555fb1f3aed
--- /dev/null
+++ b/package/boot/uboot-envtools/patches/012-fw_env-autodetect-NAND-erase-size-and-env-sectors.patch
@@ -0,0 +1,49 @@
+From d73a6641868029b5cae53ed00c5766921c9d8b1f Mon Sep 17 00:00:00 2001
+From: Anthony Loiseau <anthony.loiseau@allcircuits.com>
+Date: Thu, 21 Dec 2023 23:44:38 +0100
+Subject: [PATCH] fw_env: autodetect NAND erase size and env sectors
+
+As already done for NOR chips, if device ESIZE and ENVSECTORS static
+configurations are both zero, then autodetect them at runtime.
+
+Cc: Joe Hershberger <joe.hershberger@ni.com>
+cc: Stefan Agner <stefan@agner.ch>
+cc: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
+Signed-off-by: Anthony Loiseau <anthony.loiseau@allcircuits.com>
+---
+ tools/env/README   |  3 +++
+ tools/env/fw_env.c | 11 +++++++++--
+ 2 files changed, 12 insertions(+), 2 deletions(-)
+
+--- a/tools/env/README
++++ b/tools/env/README
+@@ -58,6 +58,9 @@ DEVICEx_ENVSECTORS defines the number of
+ this environment instance. On NAND this is used to limit the range
+ within which bad blocks are skipped, on NOR it is not used.
+ 
++If DEVICEx_ESIZE and DEVICEx_ENVSECTORS are both zero, then a runtime
++detection is attempted for NOR and NAND mtd types.
++
+ To prevent losing changes to the environment and to prevent confusing the MTD
+ drivers, a lock file at /run/fw_printenv.lock is used to serialize access
+ to the environment.
+--- a/tools/env/fw_env.c
++++ b/tools/env/fw_env.c
+@@ -1655,8 +1655,15 @@ static int check_device_config(int dev)
+ 		}
+ 		DEVTYPE(dev) = mtdinfo.type;
+ 		if (DEVESIZE(dev) == 0 && ENVSECTORS(dev) == 0 &&
+-		    mtdinfo.type == MTD_NORFLASH)
+-			DEVESIZE(dev) = mtdinfo.erasesize;
++		    mtdinfo.erasesize > 0) {
++			if (mtdinfo.type == MTD_NORFLASH)
++				DEVESIZE(dev) = mtdinfo.erasesize;
++			else if (mtdinfo.type == MTD_NANDFLASH) {
++				DEVESIZE(dev) = mtdinfo.erasesize;
++				ENVSECTORS(dev) =
++				    mtdinfo.size / mtdinfo.erasesize;
++			}
++		}
+ 		if (DEVESIZE(dev) == 0)
+ 			/* Assume the erase size is the same as the env-size */
+ 			DEVESIZE(dev) = ENVSIZE(dev);
diff --git a/package/boot/uboot-mediatek/Makefile b/package/boot/uboot-mediatek/Makefile
index c4f4e8c2d746fa..810f4d3a861159 100644
--- a/package/boot/uboot-mediatek/Makefile
+++ b/package/boot/uboot-mediatek/Makefile
@@ -1,8 +1,8 @@
 include $(TOPDIR)/rules.mk
 include $(INCLUDE_DIR)/kernel.mk
 
-PKG_VERSION:=2023.07.02
-PKG_HASH:=6b6a48581c14abb0f95bd87c1af4d740922406d7b801002a9f94727fdde021d5
+PKG_VERSION:=2024.01
+PKG_HASH:=b99611f1ed237bf3541bdc8434b68c96a6e05967061f992443cb30aabebef5b3
 PKG_BUILD_DEPENDS:=!(TARGET_ramips||TARGET_mediatek_mt7623):arm-trusted-firmware-tools/host
 
 UBOOT_USE_INTREE_DTC:=1
@@ -75,6 +75,15 @@ define U-Boot/mt7621_nand_rfb
   UBOOT_IMAGE:=u-boot-mt7621.bin
 endef
 
+define U-Boot/mt7621_zbtlink_zbt-wg3526-16m
+  NAME:=Zbtlink ZBT-WG3526-16m
+  UBOOT_CONFIG:=mt7621_zbtlink_zbt-wg3526-16m
+  BUILD_DEVICES:=zbtlink_zbt-wg3526-16m
+  BUILD_TARGET:=ramips
+  BUILD_SUBTARGET:=mt7621
+  UBOOT_IMAGE:=u-boot-mt7621.bin
+endef
+
 define U-Boot/mt7622_rfb1
   NAME:=MT7622 Reference Board 1
   UBOOT_CONFIG:=mt7622_rfb
@@ -88,9 +97,9 @@ define U-Boot/mt7622_linksys_e8450
   BUILD_DEVICES:=linksys_e8450-ubi
   BUILD_SUBTARGET:=mt7622
   UBOOT_IMAGE:=u-boot.fip
-  BL2_BOOTDEV:=snand
+  BL2_BOOTDEV:=snand-ubi
   BL2_DDRBLOB:=1
-  DEPENDS:=+trusted-firmware-a-mt7622-snand-1ddr
+  DEPENDS:=+trusted-firmware-a-mt7622-snand-ubi-1ddr
 endef
 
 define U-Boot/mt7622_bananapi_bpi-r64-emmc
@@ -121,9 +130,9 @@ define U-Boot/mt7622_bananapi_bpi-r64-snand
   BUILD_DEVICES:=bananapi_bpi-r64
   BUILD_SUBTARGET:=mt7622
   UBOOT_IMAGE:=u-boot.fip
-  BL2_BOOTDEV:=snand
+  BL2_BOOTDEV:=snand-ubi
   BL2_DDRBLOB:=2
-  DEPENDS:=+trusted-firmware-a-mt7622-snand-2ddr
+  DEPENDS:=+trusted-firmware-a-mt7622-snand-ubi-2ddr
 endef
 
 define U-Boot/mt7622_ubnt_unifi-6-lr-v1
@@ -186,7 +195,7 @@ define U-Boot/mt7628_rfb
   UBOOT_IMAGE:=u-boot-with-spl.bin
 endef
 
-define U-Boot/ravpower_rp-wd009
+define U-Boot/mt7628_ravpower_rp-wd009
   NAME:=RAVPower RP-WD009
   BUILD_TARGET:=ramips
   BUILD_DEVICES:=ravpower_rp-wd009
@@ -388,10 +397,10 @@ define U-Boot/mt7986_bananapi_bpi-r3-snand
   BUILD_DEVICES:=bananapi_bpi-r3
   UBOOT_CONFIG:=mt7986a_bpi-r3-snand
   UBOOT_IMAGE:=u-boot.fip
-  BL2_BOOTDEV:=spim-nand
+  BL2_BOOTDEV:=spim-nand-ubi
   BL2_SOC:=mt7986
   BL2_DDRTYPE:=ddr4
-  DEPENDS:=+trusted-firmware-a-mt7986-spim-nand-ddr4
+  DEPENDS:=+trusted-firmware-a-mt7986-spim-nand-ubi-ddr4
 endef
 
 define U-Boot/mt7986_bananapi_bpi-r3-nor
@@ -408,7 +417,7 @@ define U-Boot/mt7986_bananapi_bpi-r3-nor
 endef
 
 define U-Boot/mt7986_bananapi_bpi-r3-mini-emmc
-  NAME:=BananaPi BPi-R3 mini
+  NAME:=BananaPi BPi-R3 Mini
   BUILD_SUBTARGET:=filogic
   BUILD_DEVICES:=bananapi_bpi-r3-mini
   UBOOT_CONFIG:=mt7986a_bpi-r3-mini-emmc
@@ -420,15 +429,15 @@ define U-Boot/mt7986_bananapi_bpi-r3-mini-emmc
 endef
 
 define U-Boot/mt7986_bananapi_bpi-r3-mini-snand
-  NAME:=BananaPi BPi-R3 mini
+  NAME:=BananaPi BPi-R3 Mini
   BUILD_SUBTARGET:=filogic
   BUILD_DEVICES:=bananapi_bpi-r3-mini
   UBOOT_CONFIG:=mt7986a_bpi-r3-mini-snand
   UBOOT_IMAGE:=u-boot.fip
-  BL2_BOOTDEV:=spim-nand
+  BL2_BOOTDEV:=spim-nand-ubi
   BL2_SOC:=mt7986
   BL2_DDRTYPE:=ddr4
-  DEPENDS:=+trusted-firmware-a-mt7986-spim-nand-ddr4
+  DEPENDS:=+trusted-firmware-a-mt7986-spim-nand-ubi-ddr4
 endef
 
 define U-Boot/mt7986_glinet_gl-mt6000
@@ -515,6 +524,42 @@ define U-Boot/mt7986_zyxel_ex5601-t0
   DEPENDS:=+trusted-firmware-a-mt7986-spim-nand-4k-ddr4
 endef
 
+define U-Boot/mt7988_bananapi_bpi-r4-emmc
+  NAME:=BananaPi BPi-R4
+  BUILD_SUBTARGET:=filogic
+  BUILD_DEVICES:=bananapi_bpi-r4
+  UBOOT_CONFIG:=mt7988a_bananapi_bpi-r4-emmc
+  UBOOT_IMAGE:=u-boot.fip
+  BL2_BOOTDEV:=emmc
+  BL2_SOC:=mt7988
+  BL2_DDRTYPE:=comb
+  DEPENDS:=+trusted-firmware-a-mt7988-emmc-comb
+endef
+
+define U-Boot/mt7988_bananapi_bpi-r4-sdmmc
+  NAME:=BananaPi BPi-R4
+  BUILD_SUBTARGET:=filogic
+  BUILD_DEVICES:=bananapi_bpi-r4
+  UBOOT_CONFIG:=mt7988a_bananapi_bpi-r4-sdmmc
+  UBOOT_IMAGE:=u-boot.fip
+  BL2_BOOTDEV:=sdmmc
+  BL2_SOC:=mt7988
+  BL2_DDRTYPE:=comb
+  DEPENDS:=+trusted-firmware-a-mt7988-sdmmc-comb
+endef
+
+define U-Boot/mt7988_bananapi_bpi-r4-snand
+  NAME:=BananaPi BPi-R4
+  BUILD_SUBTARGET:=filogic
+  BUILD_DEVICES:=bananapi_bpi-r4
+  UBOOT_CONFIG:=mt7988a_bananapi_bpi-r4-snand
+  UBOOT_IMAGE:=u-boot.fip
+  BL2_BOOTDEV:=spim-nand-ubi
+  BL2_SOC:=mt7988
+  BL2_DDRTYPE:=comb
+  DEPENDS:=+trusted-firmware-a-mt7988-spim-nand-ubi-comb
+endef
+
 define U-Boot/mt7988_rfb-spim-nand
   NAME:=MT7988 Reference Board
   BUILD_SUBTARGET:=filogic
@@ -581,6 +626,7 @@ UBOOT_TARGETS := \
 	mt7620_rfb \
 	mt7621_nand_rfb \
 	mt7621_rfb \
+	mt7621_zbtlink_zbt-wg3526-16m \
 	mt7622_bananapi_bpi-r64-emmc \
 	mt7622_bananapi_bpi-r64-sdmmc \
 	mt7622_bananapi_bpi-r64-snand \
@@ -592,7 +638,7 @@ UBOOT_TARGETS := \
 	mt7623n_bpir2 \
 	mt7623a_unielec_u7623 \
 	mt7628_rfb \
-	ravpower_rp-wd009 \
+	mt7628_ravpower_rp-wd009 \
 	mt7629_rfb \
 	mt7981_cmcc_rax3000m-emmc \
 	mt7981_cmcc_rax3000m-nand \
@@ -610,6 +656,8 @@ UBOOT_TARGETS := \
 	mt7986_bananapi_bpi-r3-sdmmc \
 	mt7986_bananapi_bpi-r3-snand \
 	mt7986_bananapi_bpi-r3-nor \
+	mt7986_bananapi_bpi-r3-mini-emmc \
+	mt7986_bananapi_bpi-r3-mini-snand \
 	mt7986_glinet_gl-mt6000 \
 	mt7986_bananapi_bpi-r3-mini-emmc \
 	mt7986_bananapi_bpi-r3-mini-snand \
@@ -620,6 +668,9 @@ UBOOT_TARGETS := \
 	mt7986_xiaomi_redmi-router-ax6000 \
 	mt7986_zyxel_ex5601-t0 \
 	mt7986_rfb \
+	mt7988_bananapi_bpi-r4-emmc \
+	mt7988_bananapi_bpi-r4-sdmmc \
+	mt7988_bananapi_bpi-r4-snand \
 	mt7988_rfb-spim-nand \
 	mt7988_rfb-snand \
 	mt7988_rfb-nor \
diff --git a/package/boot/uboot-mediatek/patches/000-mtk-20-configs-mt7622-enable-environment-for-mt7622_rfb.patch b/package/boot/uboot-mediatek/patches/000-mtk-20-configs-mt7622-enable-environment-for-mt7622_rfb.patch
index 60eda91124b18e..dcbf8b953fa8d1 100644
--- a/package/boot/uboot-mediatek/patches/000-mtk-20-configs-mt7622-enable-environment-for-mt7622_rfb.patch
+++ b/package/boot/uboot-mediatek/patches/000-mtk-20-configs-mt7622-enable-environment-for-mt7622_rfb.patch
@@ -18,9 +18,9 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  CONFIG_DEFAULT_DEVICE_TREE="mt7622-rfb"
 +CONFIG_ENV_SIZE=0x20000
 +CONFIG_ENV_OFFSET=0x280000
- CONFIG_SYS_PROMPT="MT7622> "
  CONFIG_DEBUG_UART_BASE=0x11002000
  CONFIG_DEBUG_UART_CLOCK=25000000
+ CONFIG_SYS_LOAD_ADDR=0x4007ff28
 @@ -25,6 +27,9 @@ CONFIG_CMD_SF_TEST=y
  CONFIG_CMD_PING=y
  CONFIG_CMD_SMC=y
diff --git a/package/boot/uboot-mediatek/patches/100-00-clk-remove-log_ret-from-clk_get_rate.patch b/package/boot/uboot-mediatek/patches/100-00-clk-remove-log_ret-from-clk_get_rate.patch
deleted file mode 100644
index d5f6f7376224f1..00000000000000
--- a/package/boot/uboot-mediatek/patches/100-00-clk-remove-log_ret-from-clk_get_rate.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From 19f2aa053d5531a9ca0ece04dca172a522d58b90 Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Fri, 29 Jul 2022 11:32:28 +0800
-Subject: [PATCH 32/71] clk: remove log_ret from clk_get_rate
-
-The return value of clk_get_rate is ulong, an unsigned type. The size of
-ulong depends on the cpu architecture, i.e. 4 bytes on 32-bit CPUs and
-8 bytes on 64-bit CPUs.
-
-However log_ret only accepts and returns value in int type, a fixed 4-byte
-type. This may truncate the real clock value and cause unexpected error on
-64-bit platforms.
-
-This patch removes log_ret to solve this issue.
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- drivers/clk/clk-uclass.c | 7 +------
- 1 file changed, 1 insertion(+), 6 deletions(-)
-
---- a/drivers/clk/clk-uclass.c
-+++ b/drivers/clk/clk-uclass.c
-@@ -471,7 +471,6 @@ void clk_free(struct clk *clk)
- ulong clk_get_rate(struct clk *clk)
- {
- 	const struct clk_ops *ops;
--	int ret;
- 
- 	debug("%s(clk=%p)\n", __func__, clk);
- 	if (!clk_valid(clk))
-@@ -481,11 +480,7 @@ ulong clk_get_rate(struct clk *clk)
- 	if (!ops->get_rate)
- 		return -ENOSYS;
- 
--	ret = ops->get_rate(clk);
--	if (ret)
--		return log_ret(ret);
--
--	return 0;
-+	return ops->get_rate(clk);
- }
- 
- struct clk *clk_get_parent(struct clk *clk)
diff --git a/package/boot/uboot-mediatek/patches/100-04-env-add-support-for-generic-MTD-device.patch b/package/boot/uboot-mediatek/patches/100-04-env-add-support-for-generic-MTD-device.patch
index da87978aef31bb..9b02b4dc6305e8 100644
--- a/package/boot/uboot-mediatek/patches/100-04-env-add-support-for-generic-MTD-device.patch
+++ b/package/boot/uboot-mediatek/patches/100-04-env-add-support-for-generic-MTD-device.patch
@@ -17,37 +17,18 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  7 files changed, 299 insertions(+), 3 deletions(-)
  create mode 100644 env/mtd.c
 
---- a/cmd/nvedit.c
-+++ b/cmd/nvedit.c
-@@ -48,6 +48,7 @@ DECLARE_GLOBAL_DATA_PTR;
- 	defined(CONFIG_ENV_IS_IN_MMC)		|| \
- 	defined(CONFIG_ENV_IS_IN_FAT)		|| \
- 	defined(CONFIG_ENV_IS_IN_EXT4)		|| \
-+	defined(CONFIG_ENV_IS_IN_MTD)		|| \
- 	defined(CONFIG_ENV_IS_IN_NAND)		|| \
- 	defined(CONFIG_ENV_IS_IN_NVRAM)		|| \
- 	defined(CONFIG_ENV_IS_IN_ONENAND)	|| \
-@@ -61,7 +62,7 @@ DECLARE_GLOBAL_DATA_PTR;
- 
- #if	!defined(ENV_IS_IN_DEVICE)		&& \
- 	!defined(CONFIG_ENV_IS_NOWHERE)
--# error Define one of CONFIG_ENV_IS_IN_{EEPROM|FLASH|MMC|FAT|EXT4|\
-+# error Define one of CONFIG_ENV_IS_IN_{EEPROM|FLASH|MMC|FAT|EXT4|MTD|\
- NAND|NVRAM|ONENAND|SATA|SPI_FLASH|REMOTE|UBI} or CONFIG_ENV_IS_NOWHERE
- #endif
- 
 --- a/env/Kconfig
 +++ b/env/Kconfig
-@@ -62,7 +62,7 @@ config ENV_IS_NOWHERE
+@@ -61,7 +61,7 @@ config ENV_IS_DEFAULT
  		     !ENV_IS_IN_MMC && !ENV_IS_IN_NAND && \
  		     !ENV_IS_IN_NVRAM && !ENV_IS_IN_ONENAND && \
  		     !ENV_IS_IN_REMOTE && !ENV_IS_IN_SPI_FLASH && \
 -		     !ENV_IS_IN_UBI
 +		     !ENV_IS_IN_UBI && !ENV_IS_IN_MTD
- 	help
- 	  Define this if you don't want to or can't have an environment stored
- 	  on a storage medium. In this case the environment will still exist
-@@ -251,6 +251,27 @@ config ENV_IS_IN_MMC
+ 	select ENV_IS_NOWHERE
+ 
+ config ENV_IS_NOWHERE
+@@ -254,6 +254,27 @@ config ENV_IS_IN_MMC
  	  offset: "u-boot,mmc-env-offset", "u-boot,mmc-env-offset-redundant".
  	  CONFIG_ENV_OFFSET and CONFIG_ENV_OFFSET_REDUND are not used.
  
@@ -75,7 +56,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  config ENV_IS_IN_NAND
  	bool "Environment in a NAND device"
  	depends on !CHAIN_OF_TRUST
-@@ -558,10 +579,16 @@ config ENV_ADDR_REDUND
+@@ -561,10 +582,16 @@ config ENV_ADDR_REDUND
  	  Offset from the start of the device (or partition) of the redundant
  	  environment location.
  
@@ -93,7 +74,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  	default 0x3f8000 if ARCH_ROCKCHIP && ENV_IS_IN_MMC
  	default 0x140000 if ARCH_ROCKCHIP && ENV_IS_IN_SPI_FLASH
  	default 0xF0000 if ARCH_SUNXI
-@@ -609,6 +636,12 @@ config ENV_SECT_SIZE
+@@ -622,6 +649,12 @@ config ENV_SECT_SIZE
  	help
  	  Size of the sector containing the environment.
  
@@ -118,7 +99,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_FLASH) += flash.o
 --- a/env/env.c
 +++ b/env/env.c
-@@ -69,6 +69,9 @@ static enum env_location env_locations[]
+@@ -46,6 +46,9 @@ static enum env_location env_locations[]
  #ifdef CONFIG_ENV_IS_IN_MMC
  	ENVL_MMC,
  #endif
diff --git a/package/boot/uboot-mediatek/patches/100-08-common-board_r-add-support-to-initialize-NMBM-after-.patch b/package/boot/uboot-mediatek/patches/100-08-common-board_r-add-support-to-initialize-NMBM-after-.patch
index 93fc32cf9ec502..da4dce917ba87e 100644
--- a/package/boot/uboot-mediatek/patches/100-08-common-board_r-add-support-to-initialize-NMBM-after-.patch
+++ b/package/boot/uboot-mediatek/patches/100-08-common-board_r-add-support-to-initialize-NMBM-after-.patch
@@ -13,7 +13,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 
 --- a/common/board_r.c
 +++ b/common/board_r.c
-@@ -388,6 +388,20 @@ static int initr_nand(void)
+@@ -373,6 +373,20 @@ static int initr_nand(void)
  }
  #endif
  
@@ -34,7 +34,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  #if defined(CONFIG_CMD_ONENAND)
  /* go init the NAND */
  static int initr_onenand(void)
-@@ -696,6 +710,9 @@ static init_fnc_t init_sequence_r[] = {
+@@ -675,6 +689,9 @@ static init_fnc_t init_sequence_r[] = {
  #ifdef CONFIG_CMD_ONENAND
  	initr_onenand,
  #endif
diff --git a/package/boot/uboot-mediatek/patches/100-09-cmd-add-nmbm-command.patch b/package/boot/uboot-mediatek/patches/100-09-cmd-add-nmbm-command.patch
index 35d8f115f60e0c..4eb2bc9ccfe063 100644
--- a/package/boot/uboot-mediatek/patches/100-09-cmd-add-nmbm-command.patch
+++ b/package/boot/uboot-mediatek/patches/100-09-cmd-add-nmbm-command.patch
@@ -15,7 +15,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 
 --- a/cmd/Kconfig
 +++ b/cmd/Kconfig
-@@ -1353,6 +1353,12 @@ config CMD_NAND_TORTURE
+@@ -1392,6 +1392,12 @@ config CMD_NAND_TORTURE
  
  endif # CMD_NAND
  
@@ -30,7 +30,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  	depends on NVME
 --- a/cmd/Makefile
 +++ b/cmd/Makefile
-@@ -125,6 +125,7 @@ obj-y += legacy-mtd-utils.o
+@@ -127,6 +127,7 @@ obj-y += legacy-mtd-utils.o
  endif
  obj-$(CONFIG_CMD_MUX) += mux.o
  obj-$(CONFIG_CMD_NAND) += nand.o
diff --git a/package/boot/uboot-mediatek/patches/100-10-cmd-mtd-add-markbad-subcommand-for-NMBM-testing.patch b/package/boot/uboot-mediatek/patches/100-10-cmd-mtd-add-markbad-subcommand-for-NMBM-testing.patch
index 6336fb33f57f8e..c6358f328775ed 100644
--- a/package/boot/uboot-mediatek/patches/100-10-cmd-mtd-add-markbad-subcommand-for-NMBM-testing.patch
+++ b/package/boot/uboot-mediatek/patches/100-10-cmd-mtd-add-markbad-subcommand-for-NMBM-testing.patch
@@ -63,7 +63,7 @@ Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
  #ifdef CONFIG_AUTO_COMPLETE
  static int mtd_name_complete(int argc, char *const argv[], char last_char,
  			     int maxv, char *cmdv[])
-@@ -552,6 +588,7 @@ static char mtd_help_text[] =
+@@ -551,6 +587,7 @@ U_BOOT_LONGHELP(mtd,
  	"\n"
  	"Specific functions:\n"
  	"mtd bad                               <name>\n"
@@ -71,7 +71,7 @@ Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
  	"\n"
  	"With:\n"
  	"\t<name>: NAND partition/chip name (or corresponding DM device name or OF path)\n"
-@@ -577,4 +614,6 @@ U_BOOT_CMD_WITH_SUBCMDS(mtd, "MTD utils"
+@@ -575,4 +612,6 @@ U_BOOT_CMD_WITH_SUBCMDS(mtd, "MTD utils"
  		U_BOOT_SUBCMD_MKENT_COMPLETE(erase, 4, 0, do_mtd_erase,
  					     mtd_name_complete),
  		U_BOOT_SUBCMD_MKENT_COMPLETE(bad, 2, 1, do_mtd_bad,
diff --git a/package/boot/uboot-mediatek/patches/100-11-env-add-support-for-NMBM-upper-MTD-layer.patch b/package/boot/uboot-mediatek/patches/100-11-env-add-support-for-NMBM-upper-MTD-layer.patch
index 0b4ee32b625261..dbb1e2e59d2510 100644
--- a/package/boot/uboot-mediatek/patches/100-11-env-add-support-for-NMBM-upper-MTD-layer.patch
+++ b/package/boot/uboot-mediatek/patches/100-11-env-add-support-for-NMBM-upper-MTD-layer.patch
@@ -17,37 +17,17 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  7 files changed, 180 insertions(+), 3 deletions(-)
  create mode 100644 env/nmbm.c
 
---- a/cmd/nvedit.c
-+++ b/cmd/nvedit.c
-@@ -50,6 +50,7 @@ DECLARE_GLOBAL_DATA_PTR;
- 	defined(CONFIG_ENV_IS_IN_EXT4)		|| \
- 	defined(CONFIG_ENV_IS_IN_MTD)		|| \
- 	defined(CONFIG_ENV_IS_IN_NAND)		|| \
-+	defined(CONFIG_ENV_IS_IN_NMBM)		|| \
- 	defined(CONFIG_ENV_IS_IN_NVRAM)		|| \
- 	defined(CONFIG_ENV_IS_IN_ONENAND)	|| \
- 	defined(CONFIG_ENV_IS_IN_SPI_FLASH)	|| \
-@@ -63,7 +64,7 @@ DECLARE_GLOBAL_DATA_PTR;
- #if	!defined(ENV_IS_IN_DEVICE)		&& \
- 	!defined(CONFIG_ENV_IS_NOWHERE)
- # error Define one of CONFIG_ENV_IS_IN_{EEPROM|FLASH|MMC|FAT|EXT4|MTD|\
--NAND|NVRAM|ONENAND|SATA|SPI_FLASH|REMOTE|UBI} or CONFIG_ENV_IS_NOWHERE
-+NAND|NMBM|NVRAM|ONENAND|SATA|SPI_FLASH|REMOTE|UBI} or CONFIG_ENV_IS_NOWHERE
- #endif
- 
- /*
 --- a/env/Kconfig
 +++ b/env/Kconfig
-@@ -62,7 +62,7 @@ config ENV_IS_NOWHERE
+@@ -59,6 +59,7 @@ config ENV_IS_DEFAULT
+ 	def_bool y if !ENV_IS_IN_EEPROM && !ENV_IS_IN_EXT4 && \
+ 		     !ENV_IS_IN_FAT && !ENV_IS_IN_FLASH && \
  		     !ENV_IS_IN_MMC && !ENV_IS_IN_NAND && \
++		     !ENV_IS_IN_NMBM && \
  		     !ENV_IS_IN_NVRAM && !ENV_IS_IN_ONENAND && \
  		     !ENV_IS_IN_REMOTE && !ENV_IS_IN_SPI_FLASH && \
--		     !ENV_IS_IN_UBI && !ENV_IS_IN_MTD
-+		     !ENV_IS_IN_UBI && !ENV_IS_IN_NMBM && !ENV_IS_IN_MTD
- 	help
- 	  Define this if you don't want to or can't have an environment stored
- 	  on a storage medium. In this case the environment will still exist
-@@ -312,6 +312,21 @@ config ENV_RANGE
+ 		     !ENV_IS_IN_UBI && !ENV_IS_IN_MTD
+@@ -315,6 +316,21 @@ config ENV_RANGE
  	  Specifying a range with more erase blocks than are needed to hold
  	  CONFIG_ENV_SIZE allows bad blocks within the range to be avoided.
  
@@ -69,7 +49,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  config ENV_IS_IN_NVRAM
  	bool "Environment in a non-volatile RAM"
  	depends on !CHAIN_OF_TRUST
-@@ -588,7 +603,7 @@ config ENV_MTD_NAME
+@@ -591,7 +607,7 @@ config ENV_MTD_NAME
  config ENV_OFFSET
  	hex "Environment offset"
  	depends on ENV_IS_IN_EEPROM || ENV_IS_IN_MMC || ENV_IS_IN_NAND || \
@@ -90,7 +70,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  
 --- a/env/env.c
 +++ b/env/env.c
-@@ -75,6 +75,9 @@ static enum env_location env_locations[]
+@@ -52,6 +52,9 @@ static enum env_location env_locations[]
  #ifdef CONFIG_ENV_IS_IN_NAND
  	ENVL_NAND,
  #endif
diff --git a/package/boot/uboot-mediatek/patches/100-13-cmd-add-a-new-command-for-NAND-flash-debugging.patch b/package/boot/uboot-mediatek/patches/100-13-cmd-add-a-new-command-for-NAND-flash-debugging.patch
index f3831e07f7dfbe..e6e12ae24cdcbc 100644
--- a/package/boot/uboot-mediatek/patches/100-13-cmd-add-a-new-command-for-NAND-flash-debugging.patch
+++ b/package/boot/uboot-mediatek/patches/100-13-cmd-add-a-new-command-for-NAND-flash-debugging.patch
@@ -26,7 +26,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 
 --- a/cmd/Kconfig
 +++ b/cmd/Kconfig
-@@ -1353,6 +1353,14 @@ config CMD_NAND_TORTURE
+@@ -1392,6 +1392,14 @@ config CMD_NAND_TORTURE
  
  endif # CMD_NAND
  
@@ -43,7 +43,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  	bool "nmbm"
 --- a/cmd/Makefile
 +++ b/cmd/Makefile
-@@ -125,6 +125,7 @@ obj-y += legacy-mtd-utils.o
+@@ -127,6 +127,7 @@ obj-y += legacy-mtd-utils.o
  endif
  obj-$(CONFIG_CMD_MUX) += mux.o
  obj-$(CONFIG_CMD_NAND) += nand.o
diff --git a/package/boot/uboot-mediatek/patches/100-14-mtd-spi-nor-add-support-to-read-flash-unique-ID.patch b/package/boot/uboot-mediatek/patches/100-14-mtd-spi-nor-add-support-to-read-flash-unique-ID.patch
index d9a645d20efec9..da09cd9c088322 100644
--- a/package/boot/uboot-mediatek/patches/100-14-mtd-spi-nor-add-support-to-read-flash-unique-ID.patch
+++ b/package/boot/uboot-mediatek/patches/100-14-mtd-spi-nor-add-support-to-read-flash-unique-ID.patch
@@ -13,7 +13,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 
 --- a/drivers/mtd/spi/spi-nor-core.c
 +++ b/drivers/mtd/spi/spi-nor-core.c
-@@ -2848,6 +2848,100 @@ static int spi_nor_init_params(struct sp
+@@ -2854,6 +2854,100 @@ static int spi_nor_init_params(struct sp
  	return 0;
  }
  
@@ -114,7 +114,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size)
  {
  	size_t i;
-@@ -4045,6 +4139,7 @@ int spi_nor_scan(struct spi_nor *nor)
+@@ -4051,6 +4145,7 @@ int spi_nor_scan(struct spi_nor *nor)
  	nor->write = spi_nor_write_data;
  	nor->read_reg = spi_nor_read_reg;
  	nor->write_reg = spi_nor_write_reg;
diff --git a/package/boot/uboot-mediatek/patches/100-15-cmd-sf-add-support-to-read-flash-unique-ID.patch b/package/boot/uboot-mediatek/patches/100-15-cmd-sf-add-support-to-read-flash-unique-ID.patch
index ce59cc73aef051..f7cbd8d052c3aa 100644
--- a/package/boot/uboot-mediatek/patches/100-15-cmd-sf-add-support-to-read-flash-unique-ID.patch
+++ b/package/boot/uboot-mediatek/patches/100-15-cmd-sf-add-support-to-read-flash-unique-ID.patch
@@ -12,7 +12,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 
 --- a/cmd/sf.c
 +++ b/cmd/sf.c
-@@ -407,6 +407,14 @@ static int do_spi_protect(int argc, char
+@@ -412,6 +412,14 @@ static int do_spi_protect(int argc, char
  	return ret == 0 ? 0 : 1;
  }
  
@@ -27,22 +27,20 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  enum {
  	STAGE_ERASE,
  	STAGE_CHECK,
-@@ -601,6 +609,8 @@ static int do_spi_flash(struct cmd_tbl *
+@@ -606,6 +614,8 @@ static int do_spi_flash(struct cmd_tbl *
  		ret = do_spi_flash_erase(argc, argv);
- 	else if (strcmp(cmd, "protect") == 0)
+ 	else if (IS_ENABLED(CONFIG_SPI_FLASH_LOCK) && strcmp(cmd, "protect") == 0)
  		ret = do_spi_protect(argc, argv);
 +	else if (strcmp(cmd, "uuid") == 0)
 +		ret = do_spi_flash_read_uuid();
  	else if (IS_ENABLED(CONFIG_CMD_SF_TEST) && !strcmp(cmd, "test"))
  		ret = do_spi_flash_test(argc, argv);
  	else
-@@ -626,7 +636,8 @@ static const char long_help[] =
- 	"					  at `addr' to flash at `offset'\n"
- 	"					  or to start of mtd `partition'\n"
- 	"sf protect lock/unlock sector len	- protect/unprotect 'len' bytes starting\n"
--	"					  at address 'sector'"
-+	"					  at address 'sector'\n"
-+	"sf uuid					- read uuid from flash"
+@@ -636,6 +646,7 @@ U_BOOT_LONGHELP(sf,
  #ifdef CONFIG_CMD_SF_TEST
  	"\nsf test offset len		- run a very basic destructive test"
  #endif
++	"sf uuid				- read uuid from flash"
+ 	);
+ 
+ U_BOOT_CMD(
diff --git a/package/boot/uboot-mediatek/patches/100-16-cmd-bootmenu-add-ability-to-select-item-by-shortkey.patch b/package/boot/uboot-mediatek/patches/100-16-cmd-bootmenu-add-ability-to-select-item-by-shortkey.patch
index 315f7f92a3d794..0438895fdbaaab 100644
--- a/package/boot/uboot-mediatek/patches/100-16-cmd-bootmenu-add-ability-to-select-item-by-shortkey.patch
+++ b/package/boot/uboot-mediatek/patches/100-16-cmd-bootmenu-add-ability-to-select-item-by-shortkey.patch
@@ -255,15 +255,15 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  };
  
  /** enum bootmenu_key - keys that can be returned by the bootmenu */
-@@ -54,6 +59,7 @@ enum bootmenu_key {
- 	BKEY_MINUS,
- 	BKEY_SPACE,
+@@ -51,6 +56,7 @@ enum bootmenu_key {
+ 	BKEY_SELECT,
+ 	BKEY_QUIT,
  	BKEY_SAVE,
 +	BKEY_CHOICE,
  
- 	BKEY_COUNT,
- };
-@@ -76,7 +82,7 @@ enum bootmenu_key {
+ 	/* 'extra' keys, which are used by menus but not cedit */
+ 	BKEY_PLUS,
+@@ -81,7 +87,7 @@ enum bootmenu_key {
   *	anything else: KEY_NONE
   */
  enum bootmenu_key bootmenu_autoboot_loop(struct bootmenu_data *menu,
@@ -272,7 +272,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  
  /**
   * bootmenu_loop() - handle waiting for a keypress when autoboot is disabled
-@@ -102,7 +108,7 @@ enum bootmenu_key bootmenu_autoboot_loop
+@@ -107,7 +113,7 @@ enum bootmenu_key bootmenu_autoboot_loop
   *	Space: BKEY_SPACE
   */
  enum bootmenu_key bootmenu_loop(struct bootmenu_data *menu,
@@ -281,7 +281,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  
  /**
   * bootmenu_conv_key() - Convert a U-Boot keypress into a menu key
-@@ -110,6 +116,7 @@ enum bootmenu_key bootmenu_loop(struct b
+@@ -115,6 +121,7 @@ enum bootmenu_key bootmenu_loop(struct b
   * @ichar: Keypress to convert (ASCII, including control characters)
   * Returns: Menu key that corresponds to @ichar, or BKEY_NONE if none
   */
@@ -301,7 +301,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  
  		switch (key) {
  		case BKEY_UP:
-@@ -1937,7 +1937,7 @@ char *eficonfig_choice_change_boot_order
+@@ -1838,7 +1838,7 @@ char *eficonfig_choice_change_boot_order
  
  	cli_ch_init(cch);
  	while (1) {
@@ -312,7 +312,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  		case BKEY_PLUS:
 --- a/boot/bootflow_menu.c
 +++ b/boot/bootflow_menu.c
-@@ -231,7 +231,7 @@ int bootflow_menu_run(struct bootstd_pri
+@@ -235,7 +235,7 @@ int bootflow_menu_run(struct bootstd_pri
  
  		key = 0;
  		if (ichar) {
diff --git a/package/boot/uboot-mediatek/patches/100-17-common-spl-spl_nand-enable-CONFIG_SYS_NAND_U_BOOT_OF.patch b/package/boot/uboot-mediatek/patches/100-17-common-spl-spl_nand-enable-CONFIG_SYS_NAND_U_BOOT_OF.patch
index 149a156ba26bae..f017ce92ade363 100644
--- a/package/boot/uboot-mediatek/patches/100-17-common-spl-spl_nand-enable-CONFIG_SYS_NAND_U_BOOT_OF.patch
+++ b/package/boot/uboot-mediatek/patches/100-17-common-spl-spl_nand-enable-CONFIG_SYS_NAND_U_BOOT_OF.patch
@@ -14,7 +14,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 
 --- a/common/spl/spl_nand.c
 +++ b/common/spl/spl_nand.c
-@@ -16,7 +16,11 @@
+@@ -17,7 +17,11 @@
  
  uint32_t __weak spl_nand_get_uboot_raw_page(void)
  {
diff --git a/package/boot/uboot-mediatek/patches/100-18-board-mt7629-add-support-for-booting-from-SPI-NAND.patch b/package/boot/uboot-mediatek/patches/100-18-board-mt7629-add-support-for-booting-from-SPI-NAND.patch
index 93a940b943f7c8..ef20c2dfb6c6cb 100644
--- a/package/boot/uboot-mediatek/patches/100-18-board-mt7629-add-support-for-booting-from-SPI-NAND.patch
+++ b/package/boot/uboot-mediatek/patches/100-18-board-mt7629-add-support-for-booting-from-SPI-NAND.patch
@@ -89,14 +89,14 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  		reg = <0x11014000 0x1000>;
 --- a/arch/arm/mach-mediatek/Kconfig
 +++ b/arch/arm/mach-mediatek/Kconfig
-@@ -133,9 +133,11 @@ config SYS_CONFIG_NAME
+@@ -144,9 +144,11 @@ config SYS_CONFIG_NAME
  
  config MTK_BROM_HEADER_INFO
  	string
 -	default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 || TARGET_MT7622
 +	default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7622
  	default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183
- 	default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986
+ 	default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986 || TARGET_MT7988
  	default "lk=1" if TARGET_MT7623
  
 +source "board/mediatek/mt7629/Kconfig"
diff --git a/package/boot/uboot-mediatek/patches/100-20-board-mt7981-add-reference-board-using-new-spi-nand-.patch b/package/boot/uboot-mediatek/patches/100-20-board-mt7981-add-reference-board-using-new-spi-nand-.patch
index cb3f1ff2af5182..9dc1a577228bcf 100644
--- a/package/boot/uboot-mediatek/patches/100-20-board-mt7981-add-reference-board-using-new-spi-nand-.patch
+++ b/package/boot/uboot-mediatek/patches/100-20-board-mt7981-add-reference-board-using-new-spi-nand-.patch
@@ -18,7 +18,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 
 --- a/arch/arm/dts/Makefile
 +++ b/arch/arm/dts/Makefile
-@@ -1308,6 +1308,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
+@@ -1425,6 +1425,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
  	mt7623n-bananapi-bpi-r2.dtb \
  	mt7629-rfb.dtb \
  	mt7981-rfb.dtb \
diff --git a/package/boot/uboot-mediatek/patches/100-21-mtd-spi-nor-add-more-flash-ids.patch b/package/boot/uboot-mediatek/patches/100-21-mtd-spi-nor-add-more-flash-ids.patch
index bd68677eb063f0..15e943b1c020ad 100644
--- a/package/boot/uboot-mediatek/patches/100-21-mtd-spi-nor-add-more-flash-ids.patch
+++ b/package/boot/uboot-mediatek/patches/100-21-mtd-spi-nor-add-more-flash-ids.patch
@@ -13,7 +13,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 
 --- a/drivers/mtd/spi/spi-nor-core.c
 +++ b/drivers/mtd/spi/spi-nor-core.c
-@@ -673,6 +673,7 @@ static int set_4byte(struct spi_nor *nor
+@@ -674,6 +674,7 @@ static int set_4byte(struct spi_nor *nor
  	case SNOR_MFR_ISSI:
  	case SNOR_MFR_MACRONIX:
  	case SNOR_MFR_WINBOND:
@@ -45,7 +45,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  		INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256,
  			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
-@@ -468,6 +474,16 @@ const struct flash_info spi_nor_ids[] =
+@@ -474,6 +480,16 @@ const struct flash_info spi_nor_ids[] =
  			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  	},
  	{
@@ -62,7 +62,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  		INFO("w25q128jw", 0xef8018, 0, 64 * 1024, 256,
  			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
-@@ -517,6 +533,11 @@ const struct flash_info spi_nor_ids[] =
+@@ -523,6 +539,11 @@ const struct flash_info spi_nor_ids[] =
  			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  	},
  	{ INFO("w25q256", 0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
diff --git a/package/boot/uboot-mediatek/patches/100-22-mtd-spi-nand-backport-from-upstream-kernel.patch b/package/boot/uboot-mediatek/patches/100-22-mtd-spi-nand-backport-from-upstream-kernel.patch
index 0e233bb1d2903e..20489d87266744 100644
--- a/package/boot/uboot-mediatek/patches/100-22-mtd-spi-nand-backport-from-upstream-kernel.patch
+++ b/package/boot/uboot-mediatek/patches/100-22-mtd-spi-nand-backport-from-upstream-kernel.patch
@@ -20,66 +20,17 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  10 files changed, 923 insertions(+), 225 deletions(-)
  create mode 100644 drivers/mtd/nand/spi/etron.c
 
---- a/drivers/mtd/nand/spi/Kconfig
-+++ b/drivers/mtd/nand/spi/Kconfig
-@@ -5,3 +5,4 @@ menuconfig MTD_SPI_NAND
- 	select SPI_MEM
- 	help
- 	  This is the framework for the SPI NAND device drivers.
-+
 --- a/drivers/mtd/nand/spi/Makefile
 +++ b/drivers/mtd/nand/spi/Makefile
 @@ -1,4 +1,4 @@
  # SPDX-License-Identifier: GPL-2.0
  
--spinand-objs := core.o gigadevice.o macronix.o micron.o toshiba.o winbond.o
-+spinand-objs := core.o gigadevice.o macronix.o micron.o toshiba.o winbond.o etron.o
+-spinand-objs := core.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o
++spinand-objs := core.o etron.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o
  obj-$(CONFIG_MTD_SPI_NAND) += spinand.o
 --- a/drivers/mtd/nand/spi/core.c
 +++ b/drivers/mtd/nand/spi/core.c
-@@ -17,6 +17,7 @@
- #include <linux/mtd/spinand.h>
- #include <linux/of.h>
- #include <linux/slab.h>
-+#include <linux/string.h>
- #include <linux/spi/spi.h>
- #include <linux/spi/spi-mem.h>
- #else
-@@ -451,10 +452,11 @@ out:
- 	return status & STATUS_BUSY ? -ETIMEDOUT : 0;
- }
- 
--static int spinand_read_id_op(struct spinand_device *spinand, u8 *buf)
-+static int spinand_read_id_op(struct spinand_device *spinand, u8 naddr,
-+			      u8 ndummy, u8 *buf)
- {
--	struct spi_mem_op op = SPINAND_READID_OP(0, spinand->scratchbuf,
--						 SPINAND_MAX_ID_LEN);
-+	struct spi_mem_op op = SPINAND_READID_OP(
-+		naddr, ndummy, spinand->scratchbuf, SPINAND_MAX_ID_LEN);
- 	int ret;
- 
- 	ret = spi_mem_exec_op(spinand->slave, &op);
-@@ -464,18 +466,6 @@ static int spinand_read_id_op(struct spi
- 	return ret;
- }
- 
--static int spinand_reset_op(struct spinand_device *spinand)
--{
--	struct spi_mem_op op = SPINAND_RESET_OP;
--	int ret;
--
--	ret = spi_mem_exec_op(spinand->slave, &op);
--	if (ret)
--		return ret;
--
--	return spinand_wait(spinand, NULL);
--}
--
- static int spinand_lock_block(struct spinand_device *spinand, u8 lock)
- {
- 	return spinand_write_reg_op(spinand, REG_BLOCK_LOCK, lock);
-@@ -829,6 +819,7 @@ static const struct nand_ops spinand_ops
+@@ -822,6 +822,7 @@ static const struct nand_ops spinand_ops
  };
  
  static const struct spinand_manufacturer *spinand_manufacturers[] = {
@@ -87,140 +38,6 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  	&gigadevice_spinand_manufacturer,
  	&macronix_spinand_manufacturer,
  	&micron_spinand_manufacturer,
-@@ -836,24 +827,63 @@ static const struct spinand_manufacturer
- 	&winbond_spinand_manufacturer,
- };
- 
--static int spinand_manufacturer_detect(struct spinand_device *spinand)
-+static int spinand_manufacturer_match(struct spinand_device *spinand,
-+				      enum spinand_readid_method rdid_method)
- {
-+	u8 *id = spinand->id.data;
- 	unsigned int i;
- 	int ret;
- 
- 	for (i = 0; i < ARRAY_SIZE(spinand_manufacturers); i++) {
--		ret = spinand_manufacturers[i]->ops->detect(spinand);
--		if (ret > 0) {
--			spinand->manufacturer = spinand_manufacturers[i];
--			return 0;
--		} else if (ret < 0) {
--			return ret;
--		}
-+		const struct spinand_manufacturer *manufacturer =
-+			spinand_manufacturers[i];
-+
-+		if (id[0] != manufacturer->id)
-+			continue;
-+
-+		ret = spinand_match_and_init(spinand,
-+					     manufacturer->chips,
-+					     manufacturer->nchips,
-+					     rdid_method);
-+		if (ret < 0)
-+			continue;
-+
-+		spinand->manufacturer = manufacturer;
-+		return 0;
- 	}
- 
- 	return -ENOTSUPP;
- }
- 
-+static int spinand_id_detect(struct spinand_device *spinand)
-+{
-+	u8 *id = spinand->id.data;
-+	int ret;
-+
-+	ret = spinand_read_id_op(spinand, 0, 0, id);
-+	if (ret)
-+		return ret;
-+	ret = spinand_manufacturer_match(spinand, SPINAND_READID_METHOD_OPCODE);
-+	if (!ret)
-+		return 0;
-+
-+	ret = spinand_read_id_op(spinand, 1, 0, id);
-+	if (ret)
-+		return ret;
-+	ret = spinand_manufacturer_match(spinand,
-+					 SPINAND_READID_METHOD_OPCODE_ADDR);
-+	if (!ret)
-+		return 0;
-+
-+	ret = spinand_read_id_op(spinand, 0, 1, id);
-+	if (ret)
-+		return ret;
-+	ret = spinand_manufacturer_match(spinand,
-+					 SPINAND_READID_METHOD_OPCODE_DUMMY);
-+
-+	return ret;
-+}
-+
- static int spinand_manufacturer_init(struct spinand_device *spinand)
- {
- 	if (spinand->manufacturer->ops->init)
-@@ -909,9 +939,9 @@ spinand_select_op_variant(struct spinand
-  * @spinand: SPI NAND object
-  * @table: SPI NAND device description table
-  * @table_size: size of the device description table
-+ * @rdid_method: read id method to match
-  *
-- * Should be used by SPI NAND manufacturer drivers when they want to find a
-- * match between a device ID retrieved through the READ_ID command and an
-+ * Match between a device ID retrieved through the READ_ID command and an
-  * entry in the SPI NAND description table. If a match is found, the spinand
-  * object will be initialized with information provided by the matching
-  * spinand_info entry.
-@@ -920,8 +950,10 @@ spinand_select_op_variant(struct spinand
-  */
- int spinand_match_and_init(struct spinand_device *spinand,
- 			   const struct spinand_info *table,
--			   unsigned int table_size, u8 devid)
-+			   unsigned int table_size,
-+			   enum spinand_readid_method rdid_method)
- {
-+	u8 *id = spinand->id.data;
- 	struct nand_device *nand = spinand_to_nand(spinand);
- 	unsigned int i;
- 
-@@ -929,13 +961,17 @@ int spinand_match_and_init(struct spinan
- 		const struct spinand_info *info = &table[i];
- 		const struct spi_mem_op *op;
- 
--		if (devid != info->devid)
-+		if (rdid_method != info->devid.method)
-+			continue;
-+
-+		if (memcmp(id + 1, info->devid.id, info->devid.len))
- 			continue;
- 
- 		nand->memorg = table[i].memorg;
- 		nand->eccreq = table[i].eccreq;
- 		spinand->eccinfo = table[i].eccinfo;
- 		spinand->flags = table[i].flags;
-+		spinand->id.len = 1 + table[i].devid.len;
- 		spinand->select_target = table[i].select_target;
- 
- 		op = spinand_select_op_variant(spinand,
-@@ -967,17 +1003,7 @@ static int spinand_detect(struct spinand
- 	struct nand_device *nand = spinand_to_nand(spinand);
- 	int ret;
- 
--	ret = spinand_reset_op(spinand);
--	if (ret)
--		return ret;
--
--	ret = spinand_read_id_op(spinand, spinand->id.data);
--	if (ret)
--		return ret;
--
--	spinand->id.len = SPINAND_MAX_ID_LEN;
--
--	ret = spinand_manufacturer_detect(spinand);
-+	ret = spinand_id_detect(spinand);
- 	if (ret) {
- 		dev_err(spinand->slave->dev, "unknown raw ID %02x %02x %02x %02x\n",
- 			spinand->id.data[0], spinand->id.data[1],
 --- /dev/null
 +++ b/drivers/mtd/nand/spi/etron.c
 @@ -0,0 +1,181 @@
@@ -320,7 +137,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +	/* EM73C 1Gb 3.3V */
 +	SPINAND_INFO("EM73C044VCF",
 +		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x25),
-+		     NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
++		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
 +		     NAND_ECCREQ(4, 512),
 +		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
 +					      &write_cache_variants,
@@ -330,7 +147,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +	/* EM7xD 2Gb */
 +	SPINAND_INFO("EM73D044VCR",
 +		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x41),
-+		     NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1),
++		     NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
 +		     NAND_ECCREQ(4, 512),
 +		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
 +					      &write_cache_variants,
@@ -339,7 +156,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +		     SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
 +	SPINAND_INFO("EM73D044VCO",
 +		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x3A),
-+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
++		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
 +		     NAND_ECCREQ(8, 512),
 +		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
 +					      &write_cache_variants,
@@ -348,7 +165,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +		     SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
 +	SPINAND_INFO("EM78D044VCM",
 +		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x8E),
-+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
++		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
 +		     NAND_ECCREQ(8, 512),
 +		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
 +					      &write_cache_variants,
@@ -358,7 +175,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +	/* EM7xE 4Gb */
 +	SPINAND_INFO("EM73E044VCE",
 +		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x3B),
-+		     NAND_MEMORG(1, 2048, 128, 64, 4096, 1, 1, 1),
++		     NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
 +		     NAND_ECCREQ(8, 512),
 +		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
 +					      &write_cache_variants,
@@ -367,7 +184,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +		     SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
 +	SPINAND_INFO("EM78E044VCD",
 +		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x8F),
-+		     NAND_MEMORG(1, 2048, 128, 64, 4096, 1, 1, 1),
++		     NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
 +		     NAND_ECCREQ(8, 512),
 +		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
 +					      &write_cache_variants,
@@ -377,7 +194,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +	/* EM7xF044VCA 8Gb */
 +	SPINAND_INFO("EM73F044VCA",
 +		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x15),
-+		     NAND_MEMORG(1, 4096, 256, 64, 4096, 1, 1, 1),
++		     NAND_MEMORG(1, 4096, 256, 64, 4096, 80, 1, 1, 1),
 +		     NAND_ECCREQ(8, 512),
 +		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
 +					      &write_cache_variants,
@@ -386,7 +203,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +		     SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
 +	SPINAND_INFO("EM78F044VCA",
 +		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x8D),
-+		     NAND_MEMORG(1, 4096, 256, 64, 4096, 1, 1, 1),
++		     NAND_MEMORG(1, 4096, 256, 64, 4096, 80, 1, 1, 1),
 +		     NAND_ECCREQ(8, 512),
 +		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
 +					      &write_cache_variants,
@@ -407,45 +224,19 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +};
 --- a/drivers/mtd/nand/spi/gigadevice.c
 +++ b/drivers/mtd/nand/spi/gigadevice.c
-@@ -22,8 +22,13 @@
- 
- #define GD5FXGQXXEXXG_REG_STATUS2		0xf0
- 
-+#define GD5FXGQ4UXFXXG_STATUS_ECC_MASK		(7 << 4)
-+#define GD5FXGQ4UXFXXG_STATUS_ECC_NO_BITFLIPS	(0 << 4)
-+#define GD5FXGQ4UXFXXG_STATUS_ECC_1_3_BITFLIPS	(1 << 4)
-+#define GD5FXGQ4UXFXXG_STATUS_ECC_UNCOR_ERROR	(7 << 4)
-+
- /* Q4 devices, QUADIO: Dummy bytes valid for 1 and 2 GBit variants */
--static SPINAND_OP_VARIANTS(gd5fxgq4_read_cache_variants,
-+static SPINAND_OP_VARIANTS(read_cache_variants,
- 		SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0),
- 		SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
- 		SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
-@@ -31,8 +36,17 @@ static SPINAND_OP_VARIANTS(gd5fxgq4_read
- 		SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
- 		SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+@@ -43,6 +43,24 @@ static SPINAND_OP_VARIANTS(read_cache_va
+ 		SPINAND_PAGE_READ_FROM_CACHE_OP_3A(true, 0, 1, NULL, 0),
+ 		SPINAND_PAGE_READ_FROM_CACHE_OP_3A(false, 0, 0, NULL, 0));
  
--/* Q5 devices, QUADIO: Dummy bytes only valid for 1 GBit variants */
--static SPINAND_OP_VARIANTS(gd5f1gq5_read_cache_variants,
-+static SPINAND_OP_VARIANTS(read_cache_variants_f,
-+		SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0),
-+		SPINAND_PAGE_READ_FROM_CACHE_X4_OP_3A(0, 1, NULL, 0),
-+		SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
-+		SPINAND_PAGE_READ_FROM_CACHE_X2_OP_3A(0, 1, NULL, 0),
-+		SPINAND_PAGE_READ_FROM_CACHE_OP_3A(true, 0, 1, NULL, 0),
-+		SPINAND_PAGE_READ_FROM_CACHE_OP_3A(false, 0, 0, NULL, 0));
-+
-+/* For Q5 devices, QUADIO use different dummy byte settings */
 +/* Q5 1Gb */
 +static SPINAND_OP_VARIANTS(dummy2_read_cache_variants,
- 		SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
- 		SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
- 		SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
-@@ -40,6 +54,15 @@ static SPINAND_OP_VARIANTS(gd5f1gq5_read
- 		SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
- 		SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
- 
++		SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
++		SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
++		SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
++		SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
++		SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
++		SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
++
 +/* Q5 2Gb & 4Gb */
 +static SPINAND_OP_VARIANTS(dummy4_read_cache_variants,
 +		SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 4, NULL, 0),
@@ -458,124 +249,10 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  static SPINAND_OP_VARIANTS(write_cache_variants,
  		SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
  		SPINAND_PROG_LOAD(true, 0, NULL, 0));
-@@ -48,7 +71,65 @@ static SPINAND_OP_VARIANTS(update_cache_
- 		SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
- 		SPINAND_PROG_LOAD(false, 0, NULL, 0));
- 
--static int gd5fxgqxxexxg_ooblayout_ecc(struct mtd_info *mtd, int section,
-+static int gd5fxgq4xa_ooblayout_ecc(struct mtd_info *mtd, int section,
-+				  struct mtd_oob_region *region)
-+{
-+	if (section > 3)
-+		return -ERANGE;
-+
-+	region->offset = (16 * section) + 8;
-+	region->length = 8;
-+
-+	return 0;
-+}
-+
-+static int gd5fxgq4xa_ooblayout_free(struct mtd_info *mtd, int section,
-+				   struct mtd_oob_region *region)
-+{
-+	if (section > 3)
-+		return -ERANGE;
-+
-+	if (section) {
-+		region->offset = 16 * section;
-+		region->length = 8;
-+	} else {
-+		/* section 0 has one byte reserved for bad block mark */
-+		region->offset = 1;
-+		region->length = 7;
-+	}
-+	return 0;
-+}
-+
-+static const struct mtd_ooblayout_ops gd5fxgq4xa_ooblayout = {
-+	.ecc = gd5fxgq4xa_ooblayout_ecc,
-+	.rfree = gd5fxgq4xa_ooblayout_free,
-+};
-+
-+static int gd5fxgq4xa_ecc_get_status(struct spinand_device *spinand,
-+					 u8 status)
-+{
-+	switch (status & STATUS_ECC_MASK) {
-+	case STATUS_ECC_NO_BITFLIPS:
-+		return 0;
-+
-+	case GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS:
-+		/* 1-7 bits are flipped. return the maximum. */
-+		return 7;
-+
-+	case GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS:
-+		return 8;
-+
-+	case STATUS_ECC_UNCOR_ERROR:
-+		return -EBADMSG;
-+
-+	default:
-+		break;
-+	}
-+
-+	return -EINVAL;
-+}
-+
-+static int gd5fxgqx_variant2_ooblayout_ecc(struct mtd_info *mtd, int section,
- 				       struct mtd_oob_region *region)
- {
- 	if (section)
-@@ -60,7 +141,7 @@ static int gd5fxgqxxexxg_ooblayout_ecc(s
- 	return 0;
- }
- 
--static int gd5fxgqxxexxg_ooblayout_free(struct mtd_info *mtd, int section,
-+static int gd5fxgqx_variant2_ooblayout_free(struct mtd_info *mtd, int section,
- 					struct mtd_oob_region *region)
- {
- 	if (section)
-@@ -73,7 +154,13 @@ static int gd5fxgqxxexxg_ooblayout_free(
- 	return 0;
- }
- 
--static int gd5fxgq4xexxg_ecc_get_status(struct spinand_device *spinand,
-+/* Valid for Q4/Q5 and Q6 (untested) devices */
-+static const struct mtd_ooblayout_ops gd5fxgqx_variant2_ooblayout = {
-+	.ecc = gd5fxgqx_variant2_ooblayout_ecc,
-+	.rfree = gd5fxgqx_variant2_ooblayout_free,
-+};
-+
-+static int gd5fxgq4uexxg_ecc_get_status(struct spinand_device *spinand,
- 					u8 status)
- {
- 	u8 status2;
-@@ -152,59 +239,214 @@ static int gd5fxgq5xexxg_ecc_get_status(
+@@ -268,7 +286,45 @@ static int gd5fxgq4ufxxg_ecc_get_status(
  	return -EINVAL;
  }
  
--static const struct mtd_ooblayout_ops gd5fxgqxxexxg_ooblayout = {
--	.ecc = gd5fxgqxxexxg_ooblayout_ecc,
--	.rfree = gd5fxgqxxexxg_ooblayout_free,
-+static int gd5fxgq4ufxxg_ecc_get_status(struct spinand_device *spinand,
-+					u8 status)
-+{
-+	switch (status & GD5FXGQ4UXFXXG_STATUS_ECC_MASK) {
-+	case GD5FXGQ4UXFXXG_STATUS_ECC_NO_BITFLIPS:
-+		return 0;
-+
-+	case GD5FXGQ4UXFXXG_STATUS_ECC_1_3_BITFLIPS:
-+		return 3;
-+
-+	case GD5FXGQ4UXFXXG_STATUS_ECC_UNCOR_ERROR:
-+		return -EBADMSG;
-+
-+	default: /* (2 << 4) through (6 << 4) are 4-8 corrected errors */
-+		return ((status & GD5FXGQ4UXFXXG_STATUS_ECC_MASK) >> 4) + 2;
-+	}
-+
-+	return -EINVAL;
-+}
-+
 +static int esmt_1_ooblayout_ecc(struct mtd_info *mtd, int section,
 +				  struct mtd_oob_region *region)
 +{
@@ -603,90 +280,28 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +static const struct mtd_ooblayout_ops esmt_1_ooblayout = {
 +	.ecc = esmt_1_ooblayout_ecc,
 +	.rfree = esmt_1_ooblayout_free,
- };
- 
++ };
++
  static const struct spinand_info gigadevice_spinand_table[] = {
--	SPINAND_INFO("GD5F1GQ4UExxG", 0xd1,
--		     NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
 +	SPINAND_INFO("F50L1G41LB",
 +		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x01),
-+		     NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
--		     SPINAND_INFO_OP_VARIANTS(&gd5fxgq4_read_cache_variants,
-+		     SPINAND_INFO_OP_VARIANTS(&dummy2_read_cache_variants,
- 					      &write_cache_variants,
- 					      &update_cache_variants),
- 		     0,
--		     SPINAND_ECCINFO(&gd5fxgqxxexxg_ooblayout,
--				     gd5fxgq4xexxg_ecc_get_status)),
--	SPINAND_INFO("GD5F1GQ5UExxG", 0x51,
-+		     SPINAND_ECCINFO(&esmt_1_ooblayout, NULL)),
-+	SPINAND_INFO("GD5F1GQ4xA",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf1),
-+		     NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
-+				     gd5fxgq4xa_ecc_get_status)),
-+	SPINAND_INFO("GD5F2GQ4xA",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf2),
-+		     NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
-+				     gd5fxgq4xa_ecc_get_status)),
-+	SPINAND_INFO("GD5F4GQ4xA",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf4),
-+		     NAND_MEMORG(1, 2048, 64, 64, 4096, 1, 1, 1),
++		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
 +		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
-+				     gd5fxgq4xa_ecc_get_status)),
-+	SPINAND_INFO("GD5F1GQ4UExxG",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xd1),
-+		     NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
-+				     gd5fxgq4uexxg_ecc_get_status)),
-+	SPINAND_INFO("GD5F1GQ4UFxxG",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xb1, 0x48),
-+		     NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
-+				     gd5fxgq4ufxxg_ecc_get_status)),
-+	SPINAND_INFO("GD5F1GQ5UExxG",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x51),
- 		     NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
- 		     NAND_ECCREQ(4, 512),
--		     SPINAND_INFO_OP_VARIANTS(&gd5f1gq5_read_cache_variants,
 +		     SPINAND_INFO_OP_VARIANTS(&dummy2_read_cache_variants,
- 					      &write_cache_variants,
- 					      &update_cache_variants),
--		     0,
--		     SPINAND_ECCINFO(&gd5fxgqxxexxg_ooblayout,
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
-+				     gd5fxgq5xexxg_ecc_get_status)),
++		          &write_cache_variants,
++		          &update_cache_variants),
++		     0,
++		     SPINAND_ECCINFO(&esmt_1_ooblayout, NULL)),
+ 	SPINAND_INFO("GD5F1GQ4xA",
+ 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf1),
+ 		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
+@@ -349,6 +405,87 @@ static const struct spinand_info gigadev
+ 		     SPINAND_HAS_QE_BIT,
+ 		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ 				     gd5fxgq5xexxg_ecc_get_status)),
 +	SPINAND_INFO("GD5F2GQ5UExxG",
 +		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x52),
-+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
++		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
 +		     NAND_ECCREQ(4, 512),
 +		     SPINAND_INFO_OP_VARIANTS(&dummy4_read_cache_variants,
 +					      &write_cache_variants,
@@ -696,7 +311,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +				     gd5fxgq5xexxg_ecc_get_status)),
 +	SPINAND_INFO("GD5F4GQ6UExxG",
 +		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x55),
-+		     NAND_MEMORG(1, 2048, 128, 64, 4096, 1, 1, 1),
++		     NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
 +		     NAND_ECCREQ(4, 512),
 +		     SPINAND_INFO_OP_VARIANTS(&dummy4_read_cache_variants,
 +					      &write_cache_variants,
@@ -706,7 +321,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +				     gd5fxgq5xexxg_ecc_get_status)),
 +	SPINAND_INFO("GD5F1GM7UExxG",
 +		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x91),
-+		     NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
++		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
 +		     NAND_ECCREQ(8, 512),
 +		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
 +					      &write_cache_variants,
@@ -716,7 +331,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +				     gd5fxgq4uexxg_ecc_get_status)),
 +	SPINAND_INFO("GD5F2GM7UExxG",
 +		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x92),
-+			 NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
++			 NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
 +			 NAND_ECCREQ(8, 512),
 +			 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
 +					      &write_cache_variants,
@@ -726,7 +341,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +				     gd5fxgq4uexxg_ecc_get_status)),
 +	SPINAND_INFO("GD5F4GM8UExxG",
 +		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x95),
-+			 NAND_MEMORG(1, 2048, 128, 64, 4096, 1, 1, 1),
++			 NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
 +			 NAND_ECCREQ(8, 512),
 +			 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
 +					      &write_cache_variants,
@@ -736,7 +351,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +				     gd5fxgq4uexxg_ecc_get_status)),
 +	SPINAND_INFO("GD5F1GQ5UExxH",
 +		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x31),
-+			 NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
++			 NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
 +			 NAND_ECCREQ(4, 512),
 +			 SPINAND_INFO_OP_VARIANTS(&dummy2_read_cache_variants,
 +					      &write_cache_variants,
@@ -746,7 +361,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +				     gd5fxgq5xexxg_ecc_get_status)),
 +	SPINAND_INFO("GD5F2GQ5UExxH",
 +		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x32),
-+			 NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1),
++			 NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
 +			 NAND_ECCREQ(4, 512),
 +			 SPINAND_INFO_OP_VARIANTS(&dummy4_read_cache_variants,
 +					      &write_cache_variants,
@@ -756,600 +371,21 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +				     gd5fxgq5xexxg_ecc_get_status)),
 +	SPINAND_INFO("GD5F4GQ6UExxH",
 +		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35),
-+			 NAND_MEMORG(1, 2048, 64, 64, 4096, 1, 1, 1),
++			 NAND_MEMORG(1, 2048, 64, 64, 4096, 40, 1, 1, 1),
 +			 NAND_ECCREQ(4, 512),
 +			 SPINAND_INFO_OP_VARIANTS(&dummy4_read_cache_variants,
 +					      &write_cache_variants,
 +					      &update_cache_variants),
 +			 SPINAND_HAS_QE_BIT,
 +			 SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
- 				     gd5fxgq5xexxg_ecc_get_status)),
- };
- 
--static int gigadevice_spinand_detect(struct spinand_device *spinand)
--{
--	u8 *id = spinand->id.data;
--	int ret;
--
--	/*
--	 * For GD NANDs, There is an address byte needed to shift in before IDs
--	 * are read out, so the first byte in raw_id is dummy.
--	 */
--	if (id[1] != SPINAND_MFR_GIGADEVICE)
--		return 0;
--
--	ret = spinand_match_and_init(spinand, gigadevice_spinand_table,
--				     ARRAY_SIZE(gigadevice_spinand_table),
--				     id[2]);
--	if (ret)
--		return ret;
--
--	return 1;
--}
--
- static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = {
--	.detect = gigadevice_spinand_detect,
- };
- 
- const struct spinand_manufacturer gigadevice_spinand_manufacturer = {
- 	.id = SPINAND_MFR_GIGADEVICE,
- 	.name = "GigaDevice",
-+	.chips = gigadevice_spinand_table,
-+	.nchips = ARRAY_SIZE(gigadevice_spinand_table),
- 	.ops = &gigadevice_spinand_manuf_ops,
- };
---- a/drivers/mtd/nand/spi/macronix.c
-+++ b/drivers/mtd/nand/spi/macronix.c
-@@ -105,7 +105,8 @@ static int mx35lf1ge4ab_ecc_get_status(s
- }
- 
- static const struct spinand_info macronix_spinand_table[] = {
--	SPINAND_INFO("MX35LF1GE4AB", 0x12,
-+	SPINAND_INFO("MX35LF1GE4AB",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x12),
- 		     NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
- 		     NAND_ECCREQ(4, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -114,7 +115,8 @@ static const struct spinand_info macroni
- 		     SPINAND_HAS_QE_BIT,
- 		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
- 				     mx35lf1ge4ab_ecc_get_status)),
--	SPINAND_INFO("MX35LF2GE4AB", 0x22,
-+	SPINAND_INFO("MX35LF2GE4AB",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x22),
- 		     NAND_MEMORG(1, 2048, 64, 64, 2048, 2, 1, 1),
- 		     NAND_ECCREQ(4, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -122,7 +124,96 @@ static const struct spinand_info macroni
- 					      &update_cache_variants),
- 		     SPINAND_HAS_QE_BIT,
- 		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)),
--	SPINAND_INFO("MX35UF4GE4AD", 0xb7,
-+	SPINAND_INFO("MX35LF2GE4AD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x26),
-+		     NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
-+				     mx35lf1ge4ab_ecc_get_status)),
-+	SPINAND_INFO("MX35LF4GE4AD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x37),
-+		     NAND_MEMORG(1, 4096, 128, 64, 2048, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
-+				     mx35lf1ge4ab_ecc_get_status)),
-+	SPINAND_INFO("MX35LF1G24AD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x14),
-+		     NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)),
-+	SPINAND_INFO("MX35LF2G24AD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x24),
-+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)),
-+	SPINAND_INFO("MX35LF4G24AD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35),
-+		     NAND_MEMORG(1, 4096, 256, 64, 2048, 2, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)),
-+	SPINAND_INFO("MX31LF1GE4BC",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x1e),
-+		     NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
-+				     mx35lf1ge4ab_ecc_get_status)),
-+	SPINAND_INFO("MX31UF1GE4BC",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x9e),
-+		     NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
-+				     mx35lf1ge4ab_ecc_get_status)),
++			     gd5fxgq5xexxg_ecc_get_status)),
 +
-+	SPINAND_INFO("MX35LF2G14AC",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x20),
-+		     NAND_MEMORG(1, 2048, 64, 64, 2048, 2, 1, 1),
-+		     NAND_ECCREQ(4, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
-+				     mx35lf1ge4ab_ecc_get_status)),
-+	SPINAND_INFO("MX35UF4G24AD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xb5),
-+		     NAND_MEMORG(1, 4096, 256, 64, 2048, 2, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
-+				     mx35lf1ge4ab_ecc_get_status)),
-+	SPINAND_INFO("MX35UF4GE4AD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xb7),
- 		     NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -131,7 +222,28 @@ static const struct spinand_info macroni
- 		     SPINAND_HAS_QE_BIT,
- 		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
- 				     mx35lf1ge4ab_ecc_get_status)),
--	SPINAND_INFO("MX35UF2GE4AD", 0xa6,
-+	SPINAND_INFO("MX35UF2G14AC",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa0),
-+		     NAND_MEMORG(1, 2048, 64, 64, 2048, 2, 1, 1),
-+		     NAND_ECCREQ(4, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
-+				     mx35lf1ge4ab_ecc_get_status)),
-+	SPINAND_INFO("MX35UF2G24AD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa4),
-+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
-+				     mx35lf1ge4ab_ecc_get_status)),
-+	SPINAND_INFO("MX35UF2GE4AD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa6),
- 		     NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -140,16 +252,28 @@ static const struct spinand_info macroni
- 		     SPINAND_HAS_QE_BIT,
- 		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
- 				     mx35lf1ge4ab_ecc_get_status)),
--	SPINAND_INFO("MX35UF2GE4AC", 0xa2,
-+	SPINAND_INFO("MX35UF2GE4AC",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa2),
- 		     NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1),
- 		     NAND_ECCREQ(4, 512),
-+			 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
-+				     mx35lf1ge4ab_ecc_get_status)),
-+	SPINAND_INFO("MX35UF1G14AC",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x90),
-+		     NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
-+		     NAND_ECCREQ(4, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
- 					      &write_cache_variants,
- 					      &update_cache_variants),
- 		     SPINAND_HAS_QE_BIT,
- 		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
- 				     mx35lf1ge4ab_ecc_get_status)),
--	SPINAND_INFO("MX35UF1GE4AD", 0x96,
-+	SPINAND_INFO("MX35UF1G24AD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x94),
- 		     NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -158,7 +282,18 @@ static const struct spinand_info macroni
- 		     SPINAND_HAS_QE_BIT,
- 		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
- 				     mx35lf1ge4ab_ecc_get_status)),
--	SPINAND_INFO("MX35UF1GE4AC", 0x92,
-+	SPINAND_INFO("MX35UF1GE4AD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x96),
-+		     NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
-+				     mx35lf1ge4ab_ecc_get_status)),
-+	SPINAND_INFO("MX35UF1GE4AC",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x92),
- 		     NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
- 		     NAND_ECCREQ(4, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -170,33 +305,13 @@ static const struct spinand_info macroni
- 
- };
- 
--static int macronix_spinand_detect(struct spinand_device *spinand)
--{
--	u8 *id = spinand->id.data;
--	int ret;
--
--	/*
--	 * Macronix SPI NAND read ID needs a dummy byte, so the first byte in
--	 * raw_id is garbage.
--	 */
--	if (id[1] != SPINAND_MFR_MACRONIX)
--		return 0;
--
--	ret = spinand_match_and_init(spinand, macronix_spinand_table,
--				     ARRAY_SIZE(macronix_spinand_table),
--				     id[2]);
--	if (ret)
--		return ret;
--
--	return 1;
--}
--
- static const struct spinand_manufacturer_ops macronix_spinand_manuf_ops = {
--	.detect = macronix_spinand_detect,
- };
- 
- const struct spinand_manufacturer macronix_spinand_manufacturer = {
- 	.id = SPINAND_MFR_MACRONIX,
- 	.name = "Macronix",
-+	.chips = macronix_spinand_table,
-+	.nchips = ARRAY_SIZE(macronix_spinand_table),
- 	.ops = &macronix_spinand_manuf_ops,
  };
---- a/drivers/mtd/nand/spi/micron.c
-+++ b/drivers/mtd/nand/spi/micron.c
-@@ -120,7 +120,8 @@ static int micron_8_ecc_get_status(struc
  
- static const struct spinand_info micron_spinand_table[] = {
- 	/* M79A 2Gb 3.3V */
--	SPINAND_INFO("MT29F2G01ABAGD", 0x24,
-+	SPINAND_INFO("MT29F2G01ABAGD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x24),
- 		     NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -130,7 +131,8 @@ static const struct spinand_info micron_
- 		     SPINAND_ECCINFO(&micron_8_ooblayout,
- 				     micron_8_ecc_get_status)),
- 	/* M79A 2Gb 1.8V */
--	SPINAND_INFO("MT29F2G01ABBGD", 0x25,
-+	SPINAND_INFO("MT29F2G01ABBGD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x25),
- 		     NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -140,7 +142,8 @@ static const struct spinand_info micron_
- 		     SPINAND_ECCINFO(&micron_8_ooblayout,
- 				     micron_8_ecc_get_status)),
- 	/* M78A 1Gb 3.3V */
--	SPINAND_INFO("MT29F1G01ABAFD", 0x14,
-+	SPINAND_INFO("MT29F1G01ABAFD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x14),
- 		     NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -150,7 +153,8 @@ static const struct spinand_info micron_
- 		     SPINAND_ECCINFO(&micron_8_ooblayout,
- 				     micron_8_ecc_get_status)),
- 	/* M78A 1Gb 1.8V */
--	SPINAND_INFO("MT29F1G01ABAFD", 0x15,
-+	SPINAND_INFO("MT29F1G01ABAFD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x15),
- 		     NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -160,7 +164,8 @@ static const struct spinand_info micron_
- 		     SPINAND_ECCINFO(&micron_8_ooblayout,
- 				     micron_8_ecc_get_status)),
- 	/* M79A 4Gb 3.3V */
--	SPINAND_INFO("MT29F4G01ADAGD", 0x36,
-+	SPINAND_INFO("MT29F4G01ADAGD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x36),
- 		     NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 2),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -171,7 +176,8 @@ static const struct spinand_info micron_
- 				     micron_8_ecc_get_status),
- 		     SPINAND_SELECT_TARGET(micron_select_target)),
- 	/* M70A 4Gb 3.3V */
--	SPINAND_INFO("MT29F4G01ABAFD", 0x34,
-+	SPINAND_INFO("MT29F4G01ABAFD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x34),
- 		     NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -181,7 +187,8 @@ static const struct spinand_info micron_
- 		     SPINAND_ECCINFO(&micron_8_ooblayout,
- 				     micron_8_ecc_get_status)),
- 	/* M70A 4Gb 1.8V */
--	SPINAND_INFO("MT29F4G01ABBFD", 0x35,
-+	SPINAND_INFO("MT29F4G01ABBFD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35),
- 		     NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -191,7 +198,8 @@ static const struct spinand_info micron_
- 		     SPINAND_ECCINFO(&micron_8_ooblayout,
- 				     micron_8_ecc_get_status)),
- 	/* M70A 8Gb 3.3V */
--	SPINAND_INFO("MT29F8G01ADAFD", 0x46,
-+	SPINAND_INFO("MT29F8G01ADAFD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x46),
- 		     NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 2),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -202,7 +210,8 @@ static const struct spinand_info micron_
- 				     micron_8_ecc_get_status),
- 		     SPINAND_SELECT_TARGET(micron_select_target)),
- 	/* M70A 8Gb 1.8V */
--	SPINAND_INFO("MT29F8G01ADBFD", 0x47,
-+	SPINAND_INFO("MT29F8G01ADBFD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x47),
- 		     NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 2),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -214,26 +223,6 @@ static const struct spinand_info micron_
- 		     SPINAND_SELECT_TARGET(micron_select_target)),
- };
- 
--static int micron_spinand_detect(struct spinand_device *spinand)
--{
--	u8 *id = spinand->id.data;
--	int ret;
--
--	/*
--	 * Micron SPI NAND read ID need a dummy byte,
--	 * so the first byte in raw_id is dummy.
--	 */
--	if (id[1] != SPINAND_MFR_MICRON)
--		return 0;
--
--	ret = spinand_match_and_init(spinand, micron_spinand_table,
--				     ARRAY_SIZE(micron_spinand_table), id[2]);
--	if (ret)
--		return ret;
--
--	return 1;
--}
--
- static int micron_spinand_init(struct spinand_device *spinand)
- {
- 	/*
-@@ -248,12 +237,13 @@ static int micron_spinand_init(struct sp
- }
- 
- static const struct spinand_manufacturer_ops micron_spinand_manuf_ops = {
--	.detect = micron_spinand_detect,
- 	.init = micron_spinand_init,
- };
- 
- const struct spinand_manufacturer micron_spinand_manufacturer = {
- 	.id = SPINAND_MFR_MICRON,
- 	.name = "Micron",
-+	.chips = micron_spinand_table,
-+	.nchips = ARRAY_SIZE(micron_spinand_table),
- 	.ops = &micron_spinand_manuf_ops,
- };
---- a/drivers/mtd/nand/spi/toshiba.c
-+++ b/drivers/mtd/nand/spi/toshiba.c
-@@ -111,7 +111,8 @@ static int tx58cxgxsxraix_ecc_get_status
- 
- static const struct spinand_info toshiba_spinand_table[] = {
- 	/* 3.3V 1Gb (1st generation) */
--	SPINAND_INFO("TC58CVG0S3HRAIG", 0xC2,
-+	SPINAND_INFO("TC58CVG0S3HRAIG",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xC2),
- 		     NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -121,7 +122,8 @@ static const struct spinand_info toshiba
- 		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
- 				     tx58cxgxsxraix_ecc_get_status)),
- 	/* 3.3V 2Gb (1st generation) */
--	SPINAND_INFO("TC58CVG1S3HRAIG", 0xCB,
-+	SPINAND_INFO("TC58CVG1S3HRAIG",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xCB),
- 		     NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -131,7 +133,8 @@ static const struct spinand_info toshiba
- 		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
- 				     tx58cxgxsxraix_ecc_get_status)),
- 	/* 3.3V 4Gb (1st generation) */
--	SPINAND_INFO("TC58CVG2S0HRAIG", 0xCD,
-+	SPINAND_INFO("TC58CVG2S0HRAIG",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xCD),
- 		     NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -141,7 +144,8 @@ static const struct spinand_info toshiba
- 		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
- 				     tx58cxgxsxraix_ecc_get_status)),
- 	/* 1.8V 1Gb (1st generation) */
--	SPINAND_INFO("TC58CYG0S3HRAIG", 0xB2,
-+	SPINAND_INFO("TC58CYG0S3HRAIG",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xB2),
- 		     NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -151,7 +155,8 @@ static const struct spinand_info toshiba
- 		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
- 				     tx58cxgxsxraix_ecc_get_status)),
- 	/* 1.8V 2Gb (1st generation) */
--	SPINAND_INFO("TC58CYG1S3HRAIG", 0xBB,
-+	SPINAND_INFO("TC58CYG1S3HRAIG",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xBB),
- 		     NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -161,7 +166,8 @@ static const struct spinand_info toshiba
- 		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
- 				     tx58cxgxsxraix_ecc_get_status)),
- 	/* 1.8V 4Gb (1st generation) */
--	SPINAND_INFO("TC58CYG2S0HRAIG", 0xBD,
-+	SPINAND_INFO("TC58CYG2S0HRAIG",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xBD),
- 		     NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -176,7 +182,8 @@ static const struct spinand_info toshiba
- 	 * QE_BIT.
- 	 */
- 	/* 3.3V 1Gb (2nd generation) */
--	SPINAND_INFO("TC58CVG0S3HRAIJ", 0xE2,
-+	SPINAND_INFO("TC58CVG0S3HRAIJ",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xE2),
- 		     NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -186,7 +193,8 @@ static const struct spinand_info toshiba
- 		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
- 				     tx58cxgxsxraix_ecc_get_status)),
- 	/* 3.3V 2Gb (2nd generation) */
--	SPINAND_INFO("TC58CVG1S3HRAIJ", 0xEB,
-+	SPINAND_INFO("TC58CVG1S3HRAIJ",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xEB),
- 		     NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -196,7 +204,8 @@ static const struct spinand_info toshiba
- 		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
- 				     tx58cxgxsxraix_ecc_get_status)),
- 	/* 3.3V 4Gb (2nd generation) */
--	SPINAND_INFO("TC58CVG2S0HRAIJ", 0xED,
-+	SPINAND_INFO("TC58CVG2S0HRAIJ",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xED),
- 		     NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -206,7 +215,8 @@ static const struct spinand_info toshiba
- 		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
- 				     tx58cxgxsxraix_ecc_get_status)),
- 	/* 3.3V 8Gb (2nd generation) */
--	SPINAND_INFO("TH58CVG3S0HRAIJ", 0xE4,
-+	SPINAND_INFO("TH58CVG3S0HRAIJ",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xE4),
- 		     NAND_MEMORG(1, 4096, 256, 64, 4096, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -216,7 +226,8 @@ static const struct spinand_info toshiba
- 		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
- 				     tx58cxgxsxraix_ecc_get_status)),
- 	/* 1.8V 1Gb (2nd generation) */
--	SPINAND_INFO("TC58CYG0S3HRAIJ", 0xD2,
-+	SPINAND_INFO("TC58CYG0S3HRAIJ",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xD2),
- 		     NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -226,7 +237,8 @@ static const struct spinand_info toshiba
- 		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
- 				     tx58cxgxsxraix_ecc_get_status)),
- 	/* 1.8V 2Gb (2nd generation) */
--	SPINAND_INFO("TC58CYG1S3HRAIJ", 0xDB,
-+	SPINAND_INFO("TC58CYG1S3HRAIJ",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xDB),
- 		     NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -236,7 +248,8 @@ static const struct spinand_info toshiba
- 		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
- 				     tx58cxgxsxraix_ecc_get_status)),
- 	/* 1.8V 4Gb (2nd generation) */
--	SPINAND_INFO("TC58CYG2S0HRAIJ", 0xDD,
-+	SPINAND_INFO("TC58CYG2S0HRAIJ",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xDD),
- 		     NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -246,7 +259,8 @@ static const struct spinand_info toshiba
- 		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
- 				     tx58cxgxsxraix_ecc_get_status)),
- 	/* 1.8V 8Gb (2nd generation) */
--	SPINAND_INFO("TH58CYG3S0HRAIJ", 0xD4,
-+	SPINAND_INFO("TH58CYG3S0HRAIJ",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xD4),
- 		     NAND_MEMORG(1, 4096, 256, 64, 4096, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -257,33 +271,13 @@ static const struct spinand_info toshiba
- 				     tx58cxgxsxraix_ecc_get_status)),
- };
- 
--static int toshiba_spinand_detect(struct spinand_device *spinand)
--{
--	u8 *id = spinand->id.data;
--	int ret;
--
--	/*
--	 * Toshiba SPI NAND read ID needs a dummy byte,
--	 * so the first byte in id is garbage.
--	 */
--	if (id[1] != SPINAND_MFR_TOSHIBA)
--		return 0;
--
--	ret = spinand_match_and_init(spinand, toshiba_spinand_table,
--				     ARRAY_SIZE(toshiba_spinand_table),
--				     id[2]);
--	if (ret)
--		return ret;
--
--	return 1;
--}
--
- static const struct spinand_manufacturer_ops toshiba_spinand_manuf_ops = {
--	.detect = toshiba_spinand_detect,
- };
- 
- const struct spinand_manufacturer toshiba_spinand_manufacturer = {
- 	.id = SPINAND_MFR_TOSHIBA,
- 	.name = "Toshiba",
-+	.chips = toshiba_spinand_table,
-+	.nchips = ARRAY_SIZE(toshiba_spinand_table),
- 	.ops = &toshiba_spinand_manuf_ops,
- };
+ static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = {
 --- a/drivers/mtd/nand/spi/winbond.c
 +++ b/drivers/mtd/nand/spi/winbond.c
-@@ -19,6 +19,23 @@
+@@ -18,6 +18,23 @@
  
  #define WINBOND_CFG_BUF_READ		BIT(3)
  
@@ -1373,7 +409,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  static SPINAND_OP_VARIANTS(read_cache_variants,
  		SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
  		SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
-@@ -35,6 +52,35 @@ static SPINAND_OP_VARIANTS(update_cache_
+@@ -34,6 +51,35 @@ static SPINAND_OP_VARIANTS(update_cache_
  		SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
  		SPINAND_PROG_LOAD(false, 0, NULL, 0));
  
@@ -1409,9 +445,9 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  static int w25m02gv_ooblayout_ecc(struct mtd_info *mtd, int section,
  				  struct mtd_oob_region *region)
  {
-@@ -78,8 +124,61 @@ static int w25m02gv_select_target(struct
- 	return spi_mem_exec_op(spinand->slave, &op);
- }
+@@ -106,6 +152,58 @@ static const struct mtd_ooblayout_ops w2
+ 	.rfree = w25n02kv_ooblayout_free,
+ };
  
 +static int w25n01kv_ecc_get_status(struct spinand_device *spinand,
 +					u8 status)
@@ -1465,77 +501,32 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +	return -EINVAL;
 +}
 +
- static const struct spinand_info winbond_spinand_table[] = {
--	SPINAND_INFO("W25M02GV", 0xAB,
-+	SPINAND_INFO("W25M02GV",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xab, 0x21),
- 		     NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 2),
- 		     NAND_ECCREQ(1, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -88,7 +187,17 @@ static const struct spinand_info winbond
+ static int w25n02kv_ecc_get_status(struct spinand_device *spinand,
+ 				   u8 status)
+ {
+@@ -163,6 +261,15 @@ static const struct spinand_info winbond
+ 					      &update_cache_variants),
  		     0,
- 		     SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL),
- 		     SPINAND_SELECT_TARGET(w25m02gv_select_target)),
--	SPINAND_INFO("W25N01GV", 0xAA,
+ 		     SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL)),
 +	SPINAND_INFO("W25N01KV",
 +		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xae, 0x21),
-+		     NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
++		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
 +		     NAND_ECCREQ(4, 512),
 +		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
 +					      &write_cache_variants,
 +					      &update_cache_variants),
 +		     0,
 +		     SPINAND_ECCINFO(&w25n02kv_n04kv_ooblayout, w25n01kv_ecc_get_status)),
-+	SPINAND_INFO("W25N01GV",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x21),
- 		     NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
- 		     NAND_ECCREQ(1, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -96,32 +205,30 @@ static const struct spinand_info winbond
+ 	SPINAND_INFO("W25N02KV",
+ 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x22),
+ 		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+@@ -172,6 +279,16 @@ static const struct spinand_info winbond
  					      &update_cache_variants),
  		     0,
- 		     SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL)),
--};
--
--/**
-- * winbond_spinand_detect - initialize device related part in spinand_device
-- * struct if it is a Winbond device.
-- * @spinand: SPI NAND device structure
-- */
--static int winbond_spinand_detect(struct spinand_device *spinand)
--{
--	u8 *id = spinand->id.data;
--	int ret;
--
--	/*
--	 * Winbond SPI NAND read ID need a dummy byte,
--	 * so the first byte in raw_id is dummy.
-+	SPINAND_INFO("W25N02KV",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x22),
-+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1),
-+		     NAND_ECCREQ(4, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     0,
-+		     SPINAND_ECCINFO(&w25n02kv_n04kv_ooblayout,
-+				     w25n02kv_n04kv_ecc_get_status)),
-+	/* W25N04KV has 2-die(lun), however, it can select die automatically.
-+	 * Treat it as single die here and double block size.
- 	 */
--	if (id[1] != SPINAND_MFR_WINBOND)
--		return 0;
--
--	ret = spinand_match_and_init(spinand, winbond_spinand_table,
--				     ARRAY_SIZE(winbond_spinand_table), id[2]);
--	if (ret)
--		return ret;
--
--	return 1;
--}
+ 		     SPINAND_ECCINFO(&w25n02kv_ooblayout, w25n02kv_ecc_get_status)),
 +	SPINAND_INFO("W25N04KV",
 +		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x23),
-+		     NAND_MEMORG(1, 2048, 128, 64, 4096, 2, 1, 1),
++		     NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 2, 1, 1),
 +		     NAND_ECCREQ(4, 512),
 +		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
 +					      &write_cache_variants,
@@ -1543,162 +534,12 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +		     0,
 +		     SPINAND_ECCINFO(&w25n02kv_n04kv_ooblayout,
 +				     w25n02kv_n04kv_ecc_get_status)),
-+};
- 
- static int winbond_spinand_init(struct spinand_device *spinand)
- {
-@@ -142,12 +249,13 @@ static int winbond_spinand_init(struct s
- }
- 
- static const struct spinand_manufacturer_ops winbond_spinand_manuf_ops = {
--	.detect = winbond_spinand_detect,
- 	.init = winbond_spinand_init,
  };
  
- const struct spinand_manufacturer winbond_spinand_manufacturer = {
- 	.id = SPINAND_MFR_WINBOND,
- 	.name = "Winbond",
-+	.chips = winbond_spinand_table,
-+	.nchips = ARRAY_SIZE(winbond_spinand_table),
- 	.ops = &winbond_spinand_manuf_ops,
- };
+ static int winbond_spinand_init(struct spinand_device *spinand)
 --- a/include/linux/mtd/spinand.h
 +++ b/include/linux/mtd/spinand.h
-@@ -39,15 +39,15 @@
- 		   SPI_MEM_OP_NO_DUMMY,					\
- 		   SPI_MEM_OP_NO_DATA)
- 
--#define SPINAND_READID_OP(ndummy, buf, len)				\
-+#define SPINAND_READID_OP(naddr, ndummy, buf, len)			\
- 	SPI_MEM_OP(SPI_MEM_OP_CMD(0x9f, 1),				\
--		   SPI_MEM_OP_NO_ADDR,					\
-+		   SPI_MEM_OP_ADDR(naddr, 0, 1),			\
- 		   SPI_MEM_OP_DUMMY(ndummy, 1),				\
- 		   SPI_MEM_OP_DATA_IN(len, buf, 1))
- 
- #define SPINAND_SET_FEATURE_OP(reg, valptr)				\
- 	SPI_MEM_OP(SPI_MEM_OP_CMD(0x1f, 1),				\
--		   SPI_MEM_OP_ADDR(1, reg, 1),				\
-+		   SPI_MEM_OP_ADDR(1, reg, 1),					\
- 		   SPI_MEM_OP_NO_DUMMY,					\
- 		   SPI_MEM_OP_DATA_OUT(1, valptr, 1))
- 
-@@ -75,18 +75,36 @@
- 		   SPI_MEM_OP_DUMMY(ndummy, 1),				\
- 		   SPI_MEM_OP_DATA_IN(len, buf, 1))
- 
-+#define SPINAND_PAGE_READ_FROM_CACHE_OP_3A(fast, addr, ndummy, buf, len)\
-+	SPI_MEM_OP(SPI_MEM_OP_CMD(fast ? 0x0b : 0x03, 1),		\
-+		   SPI_MEM_OP_ADDR(3, addr, 1),				\
-+		   SPI_MEM_OP_DUMMY(ndummy, 1),				\
-+		   SPI_MEM_OP_DATA_IN(len, buf, 1))
-+
- #define SPINAND_PAGE_READ_FROM_CACHE_X2_OP(addr, ndummy, buf, len)	\
- 	SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1),				\
- 		   SPI_MEM_OP_ADDR(2, addr, 1),				\
- 		   SPI_MEM_OP_DUMMY(ndummy, 1),				\
- 		   SPI_MEM_OP_DATA_IN(len, buf, 2))
- 
-+#define SPINAND_PAGE_READ_FROM_CACHE_X2_OP_3A(addr, ndummy, buf, len)	\
-+	SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1),				\
-+		   SPI_MEM_OP_ADDR(3, addr, 1),				\
-+		   SPI_MEM_OP_DUMMY(ndummy, 1),				\
-+		   SPI_MEM_OP_DATA_IN(len, buf, 2))
-+
- #define SPINAND_PAGE_READ_FROM_CACHE_X4_OP(addr, ndummy, buf, len)	\
- 	SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1),				\
- 		   SPI_MEM_OP_ADDR(2, addr, 1),				\
- 		   SPI_MEM_OP_DUMMY(ndummy, 1),				\
- 		   SPI_MEM_OP_DATA_IN(len, buf, 4))
- 
-+#define SPINAND_PAGE_READ_FROM_CACHE_X4_OP_3A(addr, ndummy, buf, len)	\
-+	SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1),				\
-+		   SPI_MEM_OP_ADDR(3, addr, 1),				\
-+		   SPI_MEM_OP_DUMMY(ndummy, 1),				\
-+		   SPI_MEM_OP_DATA_IN(len, buf, 4))
-+
- #define SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(addr, ndummy, buf, len)	\
- 	SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1),				\
- 		   SPI_MEM_OP_ADDR(2, addr, 2),				\
-@@ -153,37 +171,46 @@ struct spinand_device;
-  * @data: buffer containing the id bytes. Currently 4 bytes large, but can
-  *	  be extended if required
-  * @len: ID length
-- *
-- * struct_spinand_id->data contains all bytes returned after a READ_ID command,
-- * including dummy bytes if the chip does not emit ID bytes right after the
-- * READ_ID command. The responsibility to extract real ID bytes is left to
-- * struct_manufacurer_ops->detect().
-  */
- struct spinand_id {
- 	u8 data[SPINAND_MAX_ID_LEN];
- 	int len;
- };
- 
-+enum spinand_readid_method {
-+	SPINAND_READID_METHOD_OPCODE,
-+	SPINAND_READID_METHOD_OPCODE_ADDR,
-+	SPINAND_READID_METHOD_OPCODE_DUMMY,
-+};
-+
-+/**
-+ * struct spinand_devid - SPI NAND device id structure
-+ * @id: device id of current chip
-+ * @len: number of bytes in device id
-+ * @method: method to read chip id
-+ *	    There are 3 possible variants:
-+ *	    SPINAND_READID_METHOD_OPCODE: chip id is returned immediately
-+ *	    after read_id opcode.
-+ *	    SPINAND_READID_METHOD_OPCODE_ADDR: chip id is returned after
-+ *	    read_id opcode + 1-byte address.
-+ *	    SPINAND_READID_METHOD_OPCODE_DUMMY: chip id is returned after
-+ *	    read_id opcode + 1 dummy byte.
-+ */
-+struct spinand_devid {
-+	const u8 *id;
-+	const u8 len;
-+	const enum spinand_readid_method method;
-+};
-+
- /**
-  * struct manufacurer_ops - SPI NAND manufacturer specific operations
-- * @detect: detect a SPI NAND device. Every time a SPI NAND device is probed
-- *	    the core calls the struct_manufacurer_ops->detect() hook of each
-- *	    registered manufacturer until one of them return 1. Note that
-- *	    the first thing to check in this hook is that the manufacturer ID
-- *	    in struct_spinand_device->id matches the manufacturer whose
-- *	    ->detect() hook has been called. Should return 1 if there's a
-- *	    match, 0 if the manufacturer ID does not match and a negative
-- *	    error code otherwise. When true is returned, the core assumes
-- *	    that properties of the NAND chip (spinand->base.memorg and
-- *	    spinand->base.eccreq) have been filled
-  * @init: initialize a SPI NAND device
-  * @cleanup: cleanup a SPI NAND device
-  *
-  * Each SPI NAND manufacturer driver should implement this interface so that
-- * NAND chips coming from this vendor can be detected and initialized properly.
-+ * NAND chips coming from this vendor can be initialized properly.
-  */
- struct spinand_manufacturer_ops {
--	int (*detect)(struct spinand_device *spinand);
- 	int (*init)(struct spinand_device *spinand);
- 	void (*cleanup)(struct spinand_device *spinand);
- };
-@@ -192,15 +219,21 @@ struct spinand_manufacturer_ops {
-  * struct spinand_manufacturer - SPI NAND manufacturer instance
-  * @id: manufacturer ID
-  * @name: manufacturer name
-+ * @devid_len: number of bytes in device ID
-+ * @chips: supported SPI NANDs under current manufacturer
-+ * @nchips: number of SPI NANDs available in chips array
-  * @ops: manufacturer operations
-  */
- struct spinand_manufacturer {
- 	u8 id;
- 	char *name;
-+	const struct spinand_info *chips;
-+	const size_t nchips;
- 	const struct spinand_manufacturer_ops *ops;
+@@ -245,6 +245,7 @@ struct spinand_manufacturer {
  };
  
  /* SPI NAND manufacturers */
@@ -1706,39 +547,3 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;
  extern const struct spinand_manufacturer macronix_spinand_manufacturer;
  extern const struct spinand_manufacturer micron_spinand_manufacturer;
-@@ -268,7 +301,7 @@ struct spinand_ecc_info {
-  */
- struct spinand_info {
- 	const char *model;
--	u8 devid;
-+	struct spinand_devid devid;
- 	u32 flags;
- 	struct nand_memory_organization memorg;
- 	struct nand_ecc_req eccreq;
-@@ -282,6 +315,13 @@ struct spinand_info {
- 			     unsigned int target);
- };
- 
-+#define SPINAND_ID(__method, ...)					\
-+	{								\
-+		.id = (const u8[]){ __VA_ARGS__ },			\
-+		.len = sizeof((u8[]){ __VA_ARGS__ }),			\
-+		.method = __method,					\
-+	}
-+
- #define SPINAND_INFO_OP_VARIANTS(__read, __write, __update)		\
- 	{								\
- 		.read_cache = __read,					\
-@@ -440,9 +480,10 @@ static inline void spinand_set_ofnode(st
- }
- #endif /* __UBOOT__ */
- 
--int spinand_match_and_init(struct spinand_device *dev,
-+int spinand_match_and_init(struct spinand_device *spinand,
- 			   const struct spinand_info *table,
--			   unsigned int table_size, u8 devid);
-+			   unsigned int table_size,
-+			   enum spinand_readid_method rdid_method);
- 
- int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val);
- int spinand_select_target(struct spinand_device *spinand, unsigned int target);
diff --git a/package/boot/uboot-mediatek/patches/100-23-mmc-mtk-sd-add-support-to-display-verbose-error-log.patch b/package/boot/uboot-mediatek/patches/100-23-mmc-mtk-sd-add-support-to-display-verbose-error-log.patch
index 0c68f429c6b0c4..5c90e24ebf51e7 100644
--- a/package/boot/uboot-mediatek/patches/100-23-mmc-mtk-sd-add-support-to-display-verbose-error-log.patch
+++ b/package/boot/uboot-mediatek/patches/100-23-mmc-mtk-sd-add-support-to-display-verbose-error-log.patch
@@ -15,7 +15,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 
 --- a/drivers/mmc/Kconfig
 +++ b/drivers/mmc/Kconfig
-@@ -820,6 +820,14 @@ config MMC_MTK
+@@ -815,6 +815,14 @@ config MMC_MTK
  	  This is needed if support for any SD/SDIO/MMC devices is required.
  	  If unsure, say N.
  
@@ -32,7 +32,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  config FSL_SDHC_V2_3
 --- a/drivers/mmc/Makefile
 +++ b/drivers/mmc/Makefile
-@@ -83,3 +83,7 @@ obj-$(CONFIG_RENESAS_SDHI)		+= tmio-comm
+@@ -82,3 +82,7 @@ obj-$(CONFIG_RENESAS_SDHI)		+= tmio-comm
  obj-$(CONFIG_MMC_BCM2835)		+= bcm2835_sdhost.o
  obj-$(CONFIG_MMC_MTK)			+= mtk-sd.o
  obj-$(CONFIG_MMC_SDHCI_F_SDH30)		+= f_sdh30.o
@@ -42,7 +42,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +endif
 --- a/drivers/mmc/mtk-sd.c
 +++ b/drivers/mmc/mtk-sd.c
-@@ -778,18 +778,24 @@ static int msdc_ops_send_cmd(struct udev
+@@ -779,18 +779,24 @@ static int msdc_ops_send_cmd(struct udev
  	if (cmd_ret &&
  	    !(cmd_ret == -EIO &&
  	    (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
diff --git a/package/boot/uboot-mediatek/patches/100-26-env-ubi-add-support-to-create-environment-volume-if-.patch b/package/boot/uboot-mediatek/patches/100-26-env-ubi-add-support-to-create-environment-volume-if-.patch
index 98c81acdcfdb60..fb8d15ddf9b03b 100644
--- a/package/boot/uboot-mediatek/patches/100-26-env-ubi-add-support-to-create-environment-volume-if-.patch
+++ b/package/boot/uboot-mediatek/patches/100-26-env-ubi-add-support-to-create-environment-volume-if-.patch
@@ -14,7 +14,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 
 --- a/env/Kconfig
 +++ b/env/Kconfig
-@@ -675,6 +675,12 @@ config ENV_UBI_VOLUME_REDUND
+@@ -689,6 +689,12 @@ config ENV_UBI_VOLUME_REDUND
  	help
  	  Name of the redundant volume that you want to store the environment in.
  
diff --git a/package/boot/uboot-mediatek/patches/100-27-mtd-ubi-add-support-for-UBI-end-of-filesystem-marker.patch b/package/boot/uboot-mediatek/patches/100-27-mtd-ubi-add-support-for-UBI-end-of-filesystem-marker.patch
index cd1794f0d119e6..9c83e6cc25daf3 100644
--- a/package/boot/uboot-mediatek/patches/100-27-mtd-ubi-add-support-for-UBI-end-of-filesystem-marker.patch
+++ b/package/boot/uboot-mediatek/patches/100-27-mtd-ubi-add-support-for-UBI-end-of-filesystem-marker.patch
@@ -15,7 +15,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 
 --- a/drivers/mtd/ubi/attach.c
 +++ b/drivers/mtd/ubi/attach.c
-@@ -802,6 +802,13 @@ out_unlock:
+@@ -803,6 +803,13 @@ out_unlock:
  	return err;
  }
  
@@ -29,7 +29,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  /**
   * scan_peb - scan and process UBI headers of a PEB.
   * @ubi: UBI device description object
-@@ -832,9 +839,21 @@ static int scan_peb(struct ubi_device *u
+@@ -833,9 +840,21 @@ static int scan_peb(struct ubi_device *u
  		return 0;
  	}
  
@@ -56,7 +56,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  		break;
 --- a/drivers/mtd/ubi/ubi.h
 +++ b/drivers/mtd/ubi/ubi.h
-@@ -745,6 +745,7 @@ struct ubi_attach_info {
+@@ -746,6 +746,7 @@ struct ubi_attach_info {
  	int mean_ec;
  	uint64_t ec_sum;
  	int ec_count;
diff --git a/package/boot/uboot-mediatek/patches/100-29-board-mediatek-wire-up-NMBM-support.patch b/package/boot/uboot-mediatek/patches/100-29-board-mediatek-wire-up-NMBM-support.patch
index b561a799444108..f22449ae76fd0c 100644
--- a/package/boot/uboot-mediatek/patches/100-29-board-mediatek-wire-up-NMBM-support.patch
+++ b/package/boot/uboot-mediatek/patches/100-29-board-mediatek-wire-up-NMBM-support.patch
@@ -24,7 +24,7 @@ Subject: [PATCH] board: mediatek: wire-up NMBM support
  DECLARE_GLOBAL_DATA_PTR;
  
  int board_init(void)
-@@ -24,3 +29,36 @@ int board_late_init(void)
+@@ -23,3 +28,36 @@ int board_late_init(void)
  	env_relocate();
  	return 0;
  }
diff --git a/package/boot/uboot-mediatek/patches/101-01-arm-mediatek-retrieve-ram_base-from-dts-node-for-arm.patch b/package/boot/uboot-mediatek/patches/101-01-arm-mediatek-retrieve-ram_base-from-dts-node-for-arm.patch
deleted file mode 100644
index 645b7801c8b8e0..00000000000000
--- a/package/boot/uboot-mediatek/patches/101-01-arm-mediatek-retrieve-ram_base-from-dts-node-for-arm.patch
+++ /dev/null
@@ -1,297 +0,0 @@
-From 63336ec7fd7d480ac58a91f3b20d08bf1b3a13ad Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:15:41 +0800
-Subject: [PATCH 01/29] arm: mediatek: retrieve ram_base from dts node for
- armv8 platform
-
-Now we use fdtdec_setup_mem_size_base() to get DRAM base from fdt ram node
-and update gd->ram_base. CFG_SYS_SDRAM_BASE is unused and will be removed.
-
-Also, since mt7622 always passes fdt to linux kernel, there's no need to
-assign value to gd->bd->bi_boot_params.
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- arch/arm/dts/mt7981-emmc-rfb.dts     |  5 +++++
- arch/arm/dts/mt7981-rfb.dts          |  5 +++++
- arch/arm/dts/mt7981-sd-rfb.dts       |  5 +++++
- arch/arm/dts/mt7986a-bpi-r3-sd.dts   |  5 +++++
- arch/arm/dts/mt7986a-rfb.dts         |  5 +++++
- arch/arm/dts/mt7986a-sd-rfb.dts      |  5 +++++
- arch/arm/dts/mt7986b-rfb.dts         |  5 +++++
- arch/arm/dts/mt7986b-sd-rfb.dts      |  5 +++++
- arch/arm/mach-mediatek/mt7622/init.c | 13 +++++++++----
- arch/arm/mach-mediatek/mt7981/init.c | 11 +++++++++--
- arch/arm/mach-mediatek/mt7986/init.c | 11 +++++++++--
- board/mediatek/mt7622/mt7622_rfb.c   |  1 -
- include/configs/mt7622.h             | 10 ----------
- include/configs/mt7981.h             |  9 ---------
- include/configs/mt7986.h             |  9 ---------
- 15 files changed, 67 insertions(+), 37 deletions(-)
-
---- a/arch/arm/dts/mt7981-emmc-rfb.dts
-+++ b/arch/arm/dts/mt7981-emmc-rfb.dts
-@@ -18,6 +18,11 @@
- 		tick-timer = &timer0;
- 	};
- 
-+	memory@40000000 {
-+		device_type = "memory";
-+		reg = <0x40000000 0x10000000>;
-+	};
-+
- 	reg_3p3v: regulator-3p3v {
- 		  compatible = "regulator-fixed";
- 		  regulator-name = "fixed-3.3V";
---- a/arch/arm/dts/mt7981-rfb.dts
-+++ b/arch/arm/dts/mt7981-rfb.dts
-@@ -17,6 +17,11 @@
- 		stdout-path = &uart0;
- 		tick-timer = &timer0;
- 	};
-+
-+	memory@40000000 {
-+		device_type = "memory";
-+		reg = <0x40000000 0x10000000>;
-+	};
- };
- 
- &uart0 {
---- a/arch/arm/dts/mt7981-sd-rfb.dts
-+++ b/arch/arm/dts/mt7981-sd-rfb.dts
-@@ -18,6 +18,11 @@
- 		tick-timer = &timer0;
- 	};
- 
-+	memory@40000000 {
-+		device_type = "memory";
-+		reg = <0x40000000 0x10000000>;
-+	};
-+
- 	reg_3p3v: regulator-3p3v {
- 		  compatible = "regulator-fixed";
- 		  regulator-name = "fixed-3.3V";
---- a/arch/arm/dts/mt7986a-bpi-r3-sd.dts
-+++ b/arch/arm/dts/mt7986a-bpi-r3-sd.dts
-@@ -19,6 +19,11 @@
- 		tick-timer = &timer0;
- 	};
- 
-+	memory@40000000 {
-+		device_type = "memory";
-+		reg = <0x40000000 0x80000000>;
-+	};
-+
- 	reg_3p3v: regulator-3p3v {
- 		compatible = "regulator-fixed";
- 		regulator-name = "fixed-3.3V";
---- a/arch/arm/dts/mt7986a-rfb.dts
-+++ b/arch/arm/dts/mt7986a-rfb.dts
-@@ -18,6 +18,11 @@
- 		tick-timer = &timer0;
- 	};
- 
-+	memory@40000000 {
-+		device_type = "memory";
-+		reg = <0x40000000 0x10000000>;
-+	};
-+
- 	reg_1p8v: regulator-1p8v {
- 		compatible = "regulator-fixed";
- 		regulator-name = "fixed-1.8V";
---- a/arch/arm/dts/mt7986a-sd-rfb.dts
-+++ b/arch/arm/dts/mt7986a-sd-rfb.dts
-@@ -19,6 +19,11 @@
- 		tick-timer = &timer0;
- 	};
- 
-+	memory@40000000 {
-+		device_type = "memory";
-+		reg = <0x40000000 0x10000000>;
-+	};
-+
- 	reg_3p3v: regulator-3p3v {
- 		compatible = "regulator-fixed";
- 		regulator-name = "fixed-3.3V";
---- a/arch/arm/dts/mt7986b-rfb.dts
-+++ b/arch/arm/dts/mt7986b-rfb.dts
-@@ -18,6 +18,11 @@
- 		tick-timer = &timer0;
- 	};
- 
-+	memory@40000000 {
-+		device_type = "memory";
-+		reg = <0x40000000 0x10000000>;
-+	};
-+
- 	reg_3p3v: regulator-3p3v {
- 		compatible = "regulator-fixed";
- 		regulator-name = "fixed-3.3V";
---- a/arch/arm/dts/mt7986b-sd-rfb.dts
-+++ b/arch/arm/dts/mt7986b-sd-rfb.dts
-@@ -19,6 +19,11 @@
- 		tick-timer = &timer0;
- 	};
- 
-+	memory@40000000 {
-+		device_type = "memory";
-+		reg = <0x40000000 0x10000000>;
-+	};
-+
- 	reg_3p3v: regulator-3p3v {
- 		compatible = "regulator-fixed";
- 		regulator-name = "fixed-3.3V";
---- a/arch/arm/mach-mediatek/mt7622/init.c
-+++ b/arch/arm/mach-mediatek/mt7622/init.c
-@@ -4,11 +4,14 @@
-  * Author: Sam Shih <sam.shih@mediatek.com>
-  */
- 
--#include <common.h>
- #include <fdtdec.h>
- #include <init.h>
- #include <asm/armv8/mmu.h>
--#include <asm/cache.h>
-+#include <asm/global_data.h>
-+#include <asm/u-boot.h>
-+#include <linux/sizes.h>
-+
-+DECLARE_GLOBAL_DATA_PTR;
- 
- int print_cpuinfo(void)
- {
-@@ -20,11 +23,13 @@ int dram_init(void)
- {
- 	int ret;
- 
--	ret = fdtdec_setup_memory_banksize();
-+	ret = fdtdec_setup_mem_size_base();
- 	if (ret)
- 		return ret;
--	return fdtdec_setup_mem_size_base();
- 
-+	gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_2G);
-+
-+	return 0;
- }
- 
- void reset_cpu(void)
---- a/arch/arm/mach-mediatek/mt7981/init.c
-+++ b/arch/arm/mach-mediatek/mt7981/init.c
-@@ -4,18 +4,25 @@
-  * Author: Sam Shih <sam.shih@mediatek.com>
-  */
- 
--#include <cpu_func.h>
-+#include <fdtdec.h>
- #include <init.h>
- #include <asm/armv8/mmu.h>
- #include <asm/system.h>
- #include <asm/global_data.h>
-+#include <asm/u-boot.h>
- #include <linux/sizes.h>
- 
- DECLARE_GLOBAL_DATA_PTR;
- 
- int dram_init(void)
- {
--	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_2G);
-+	int ret;
-+
-+	ret = fdtdec_setup_mem_size_base();
-+	if (ret)
-+		return ret;
-+
-+	gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_1G);
- 
- 	return 0;
- }
---- a/arch/arm/mach-mediatek/mt7986/init.c
-+++ b/arch/arm/mach-mediatek/mt7986/init.c
-@@ -4,18 +4,25 @@
-  * Author: Sam Shih <sam.shih@mediatek.com>
-  */
- 
--#include <cpu_func.h>
-+#include <fdtdec.h>
- #include <init.h>
- #include <asm/armv8/mmu.h>
- #include <asm/system.h>
- #include <asm/global_data.h>
-+#include <asm/u-boot.h>
- #include <linux/sizes.h>
- 
- DECLARE_GLOBAL_DATA_PTR;
- 
- int dram_init(void)
- {
--	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_2G);
-+	int ret;
-+
-+	ret = fdtdec_setup_mem_size_base();
-+	if (ret)
-+		return ret;
-+
-+	gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_2G);
- 
- 	return 0;
- }
---- a/board/mediatek/mt7622/mt7622_rfb.c
-+++ b/board/mediatek/mt7622/mt7622_rfb.c
-@@ -19,7 +19,6 @@ DECLARE_GLOBAL_DATA_PTR;
- 
- int board_init(void)
- {
--	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
- 	return 0;
- }
- 
---- a/include/configs/mt7622.h
-+++ b/include/configs/mt7622.h
-@@ -9,14 +9,4 @@
- #ifndef __MT7622_H
- #define __MT7622_H
- 
--/* Uboot definition */
--#define CFG_SYS_UBOOT_BASE                   CONFIG_TEXT_BASE
--
--/* SPL -> Uboot */
--#define CFG_SYS_UBOOT_START		CONFIG_TEXT_BASE
--/* DRAM */
--#define CFG_SYS_SDRAM_BASE		0x40000000
--
--/* Ethernet */
--
- #endif
---- a/include/configs/mt7981.h
-+++ b/include/configs/mt7981.h
-@@ -9,13 +9,4 @@
- #ifndef __MT7981_H
- #define __MT7981_H
- 
--/* Uboot definition */
--#define CFG_SYS_UBOOT_BASE		CONFIG_TEXT_BASE
--
--/* SPL -> Uboot */
--#define CFG_SYS_UBOOT_START		CONFIG_TEXT_BASE
--
--/* DRAM */
--#define CFG_SYS_SDRAM_BASE		0x40000000
--
- #endif
---- a/include/configs/mt7986.h
-+++ b/include/configs/mt7986.h
-@@ -9,13 +9,4 @@
- #ifndef __MT7986_H
- #define __MT7986_H
- 
--/* Uboot definition */
--#define CFG_SYS_UBOOT_BASE		CONFIG_TEXT_BASE
--
--/* SPL -> Uboot */
--#define CFG_SYS_UBOOT_START		CONFIG_TEXT_BASE
--
--/* DRAM */
--#define CFG_SYS_SDRAM_BASE		0x40000000
--
- #endif
diff --git a/package/boot/uboot-mediatek/patches/101-02-board-mediatek-update-config-headers.patch b/package/boot/uboot-mediatek/patches/101-02-board-mediatek-update-config-headers.patch
deleted file mode 100644
index b64ee15171fa3d..00000000000000
--- a/package/boot/uboot-mediatek/patches/101-02-board-mediatek-update-config-headers.patch
+++ /dev/null
@@ -1,129 +0,0 @@
-From df3a0091b249ea82198ea019d145d05a7cf49c0d Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:15:47 +0800
-Subject: [PATCH 02/29] board: mediatek: update config headers
-
-Remove unused information from include/configs/mtxxxx.h
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- include/configs/mt7620.h |  3 +--
- include/configs/mt7621.h |  6 ++----
- include/configs/mt7623.h |  8 --------
- include/configs/mt7628.h |  5 ++---
- include/configs/mt7629.h | 13 +------------
- 5 files changed, 6 insertions(+), 29 deletions(-)
-
---- a/include/configs/mt7620.h
-+++ b/include/configs/mt7620.h
-@@ -10,10 +10,9 @@
- 
- #define CFG_SYS_SDRAM_BASE		0x80000000
- 
--#define CFG_SYS_INIT_SP_OFFSET	0x400000
-+#define CFG_SYS_INIT_SP_OFFSET		0x400000
- 
- /* SPL */
--
- #define CFG_SYS_UBOOT_START		CONFIG_TEXT_BASE
- 
- /* Dummy value */
---- a/include/configs/mt7621.h
-+++ b/include/configs/mt7621.h
-@@ -12,13 +12,11 @@
- 
- #define CFG_MAX_MEM_MAPPED		0x1c000000
- 
--#define CFG_SYS_INIT_SP_OFFSET	0x800000
-+#define CFG_SYS_INIT_SP_OFFSET		0x800000
- 
- /* MMC */
- #define MMC_SUPPORTS_TUNING
- 
--/* NAND */
--
- /* Serial SPL */
- #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)
- #define CFG_SYS_NS16550_CLK		50000000
-@@ -26,7 +24,7 @@
- #endif
- 
- /* Serial common */
--#define CFG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, \
-+#define CFG_SYS_BAUDRATE_TABLE		{ 9600, 19200, 38400, 57600, 115200, \
- 					  230400, 460800, 921600 }
- 
- /* Dummy value */
---- a/include/configs/mt7623.h
-+++ b/include/configs/mt7623.h
-@@ -11,12 +11,6 @@
- 
- #include <linux/sizes.h>
- 
--/* Miscellaneous configurable options */
--
--/* Environment */
--
--/* Preloader -> Uboot */
--
- /* MMC */
- #define MMC_SUPPORTS_TUNING
- 
-@@ -32,8 +26,6 @@
- 	"fdt_addr_r=" FDT_HIGH "\0"			\
- 	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0"
- 
--/* Ethernet */
--
- #ifdef CONFIG_DISTRO_DEFAULTS
- 
- #define BOOT_TARGET_DEVICES(func)	\
---- a/include/configs/mt7628.h
-+++ b/include/configs/mt7628.h
-@@ -10,7 +10,7 @@
- 
- #define CFG_SYS_SDRAM_BASE		0x80000000
- 
--#define CFG_SYS_INIT_SP_OFFSET	0x80000
-+#define CFG_SYS_INIT_SP_OFFSET		0x80000
- 
- /* Serial SPL */
- #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)
-@@ -19,11 +19,10 @@
- #endif
- 
- /* Serial common */
--#define CFG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, \
-+#define CFG_SYS_BAUDRATE_TABLE		{ 9600, 19200, 38400, 57600, 115200, \
- 					  230400, 460800, 921600 }
- 
- /* SPL */
--
- #define CFG_SYS_UBOOT_START		CONFIG_TEXT_BASE
- 
- /* Dummy value */
---- a/include/configs/mt7629.h
-+++ b/include/configs/mt7629.h
-@@ -9,21 +9,10 @@
- #ifndef __MT7629_H
- #define __MT7629_H
- 
--#include <linux/sizes.h>
--
--/* Miscellaneous configurable options */
--
--/* Environment */
--
-+/* SPL */
- #define CFG_SYS_UBOOT_BASE		(0x30000000 + CONFIG_SPL_PAD_TO)
- 
--/* SPL -> Uboot */
--
--/* UBoot -> Kernel */
--
- /* DRAM */
- #define CFG_SYS_SDRAM_BASE		0x40000000
- 
--/* Ethernet */
--
- #endif
diff --git a/package/boot/uboot-mediatek/patches/101-03-spi-mtk_spim-get-spi-clk-rate-only-once.patch b/package/boot/uboot-mediatek/patches/101-03-spi-mtk_spim-get-spi-clk-rate-only-once.patch
deleted file mode 100644
index 323bb249332ccb..00000000000000
--- a/package/boot/uboot-mediatek/patches/101-03-spi-mtk_spim-get-spi-clk-rate-only-once.patch
+++ /dev/null
@@ -1,84 +0,0 @@
-From 0d6d8a408f80358dd47984320ea9c65e555ac4c9 Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:15:54 +0800
-Subject: [PATCH 03/29] spi: mtk_spim: get spi clk rate only once
-
-We don't really need to switch clk rate during operating SPIM controller.
-Get clk rate only once at driver probing.
-
-Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
-Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
----
- drivers/spi/mtk_spim.c | 21 +++++++++++++--------
- 1 file changed, 13 insertions(+), 8 deletions(-)
-
---- a/drivers/spi/mtk_spim.c
-+++ b/drivers/spi/mtk_spim.c
-@@ -137,6 +137,8 @@ struct mtk_spim_capability {
-  * @state:		Controller state
-  * @sel_clk:		Pad clock
-  * @spi_clk:		Core clock
-+ * @pll_clk_rate:	Controller's PLL source clock rate, which is different
-+ *			from SPI bus clock rate
-  * @xfer_len:		Current length of data for transfer
-  * @hw_cap:		Controller capabilities
-  * @tick_dly:		Used to postpone SPI sampling time
-@@ -149,6 +151,7 @@ struct mtk_spim_priv {
- 	void __iomem *base;
- 	u32 state;
- 	struct clk sel_clk, spi_clk;
-+	u32 pll_clk_rate;
- 	u32 xfer_len;
- 	struct mtk_spim_capability hw_cap;
- 	u32 tick_dly;
-@@ -253,11 +256,10 @@ static int mtk_spim_hw_init(struct spi_s
- static void mtk_spim_prepare_transfer(struct mtk_spim_priv *priv,
- 				      u32 speed_hz)
- {
--	u32 spi_clk_hz, div, sck_time, cs_time, reg_val;
-+	u32 div, sck_time, cs_time, reg_val;
- 
--	spi_clk_hz = clk_get_rate(&priv->spi_clk);
--	if (speed_hz <= spi_clk_hz / 4)
--		div = DIV_ROUND_UP(spi_clk_hz, speed_hz);
-+	if (speed_hz <= priv->pll_clk_rate / 4)
-+		div = DIV_ROUND_UP(priv->pll_clk_rate, speed_hz);
- 	else
- 		div = 4;
- 
-@@ -404,7 +406,7 @@ static int mtk_spim_transfer_wait(struct
- {
- 	struct udevice *bus = dev_get_parent(slave->dev);
- 	struct mtk_spim_priv *priv = dev_get_priv(bus);
--	u32 sck_l, sck_h, spi_bus_clk, clk_count, reg;
-+	u32 sck_l, sck_h, clk_count, reg;
- 	ulong us = 1;
- 	int ret = 0;
- 
-@@ -413,12 +415,11 @@ static int mtk_spim_transfer_wait(struct
- 	else
- 		clk_count = op->data.nbytes;
- 
--	spi_bus_clk = clk_get_rate(&priv->spi_clk);
- 	sck_l = readl(priv->base + SPI_CFG2_REG) >> SPI_CFG2_SCK_LOW_OFFSET;
- 	sck_h = readl(priv->base + SPI_CFG2_REG) & SPI_CFG2_SCK_HIGH_MASK;
--	do_div(spi_bus_clk, sck_l + sck_h + 2);
-+	do_div(priv->pll_clk_rate, sck_l + sck_h + 2);
- 
--	us = CLK_TO_US(spi_bus_clk, clk_count * 8);
-+	us = CLK_TO_US(priv->pll_clk_rate, clk_count * 8);
- 	us += 1000 * 1000; /* 1s tolerance */
- 
- 	if (us > UINT_MAX)
-@@ -662,6 +663,10 @@ static int mtk_spim_probe(struct udevice
- 	clk_enable(&priv->sel_clk);
- 	clk_enable(&priv->spi_clk);
- 
-+	priv->pll_clk_rate = clk_get_rate(&priv->spi_clk);
-+	if (priv->pll_clk_rate == 0)
-+		return -EINVAL;
-+
- 	return 0;
- }
- 
diff --git a/package/boot/uboot-mediatek/patches/101-04-spi-mtk_spim-clear-IRQ-enable-bits.patch b/package/boot/uboot-mediatek/patches/101-04-spi-mtk_spim-clear-IRQ-enable-bits.patch
deleted file mode 100644
index e8577f63bf1f41..00000000000000
--- a/package/boot/uboot-mediatek/patches/101-04-spi-mtk_spim-clear-IRQ-enable-bits.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From a7b630f02bb12f71f23866aee6f9a1a07497d475 Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:16:02 +0800
-Subject: [PATCH 04/29] spi: mtk_spim: clear IRQ enable bits
-
-In u-boot we don't use IRQ. Instead, we poll busy bit in SPI_STATUS.
-
-However these IRQ enable bits may be set in previous boot stage (BootROM).
-
-If we leave these bits not cleared, although u-boot has disabled IRQ and
-nothing will happen, the linux kernel may encounter panic during
-initializing the spim driver due to IRQ event happens before IRQ handler
-is properly setup.
-
-This patch clear IRQ bits to prevent this from happening.
-
-Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
-Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
----
- drivers/spi/mtk_spim.c | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/drivers/spi/mtk_spim.c
-+++ b/drivers/spi/mtk_spim.c
-@@ -242,6 +242,9 @@ static int mtk_spim_hw_init(struct spi_s
- 			reg_val &= ~SPI_CMD_SAMPLE_SEL;
- 	}
- 
-+	/* Disable interrupt enable for pause mode & normal mode */
-+	reg_val &= ~(SPI_CMD_PAUSE_IE | SPI_CMD_FINISH_IE);
-+
- 	/* disable dma mode */
- 	reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA);
- 
diff --git a/package/boot/uboot-mediatek/patches/101-05-serial-mtk-initial-priv-data-before-using.patch b/package/boot/uboot-mediatek/patches/101-05-serial-mtk-initial-priv-data-before-using.patch
deleted file mode 100644
index 6f805765c1fdfb..00000000000000
--- a/package/boot/uboot-mediatek/patches/101-05-serial-mtk-initial-priv-data-before-using.patch
+++ /dev/null
@@ -1,25 +0,0 @@
-From 73060da8b54e74c51ef6c1fd31c4fac6ad6b8d0e Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:16:07 +0800
-Subject: [PATCH 05/29] serial: mtk: initial priv data before using
-
-This patch ensures driver private data being fully initialized in
-_debug_uart_init which is not covered by .priv_auto ops.
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
-Reviewed-by: Stefan Roese <sr@denx.de>
----
- drivers/serial/serial_mtk.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/serial/serial_mtk.c
-+++ b/drivers/serial/serial_mtk.c
-@@ -439,6 +439,7 @@ static inline void _debug_uart_init(void
- {
- 	struct mtk_serial_priv priv;
- 
-+	memset(&priv, 0, sizeof(struct mtk_serial_priv));
- 	priv.regs = (void *) CONFIG_VAL(DEBUG_UART_BASE);
- 	priv.fixed_clk_rate = CONFIG_DEBUG_UART_CLOCK;
- 
diff --git a/package/boot/uboot-mediatek/patches/101-06-reset-mediatek-check-malloc-return-valaue-before-use.patch b/package/boot/uboot-mediatek/patches/101-06-reset-mediatek-check-malloc-return-valaue-before-use.patch
deleted file mode 100644
index b319f5e27eb61e..00000000000000
--- a/package/boot/uboot-mediatek/patches/101-06-reset-mediatek-check-malloc-return-valaue-before-use.patch
+++ /dev/null
@@ -1,26 +0,0 @@
-From 06e6d224f7d564a34407eba21b51797da7f22628 Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:16:11 +0800
-Subject: [PATCH 06/29] reset: mediatek: check malloc return valaue before use
-
-This patch add missing return value check for allocating the driver's
-private data. -ENOMEM will be returned if malloc() fails.
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- drivers/reset/reset-mediatek.c | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/drivers/reset/reset-mediatek.c
-+++ b/drivers/reset/reset-mediatek.c
-@@ -79,6 +79,9 @@ int mediatek_reset_bind(struct udevice *
- 		return ret;
- 
- 	priv = malloc(sizeof(struct mediatek_reset_priv));
-+	if (!priv)
-+		return -ENOMEM;
-+
- 	priv->regofs = regofs;
- 	priv->nr_resets = num_regs * 32;
- 	dev_set_priv(rst_dev, priv);
diff --git a/package/boot/uboot-mediatek/patches/101-07-i2c-mediatek-fix-I2C-usability-for-MT7981.patch b/package/boot/uboot-mediatek/patches/101-07-i2c-mediatek-fix-I2C-usability-for-MT7981.patch
deleted file mode 100644
index dd00104c391ec2..00000000000000
--- a/package/boot/uboot-mediatek/patches/101-07-i2c-mediatek-fix-I2C-usability-for-MT7981.patch
+++ /dev/null
@@ -1,125 +0,0 @@
-From 77898faf6ce56eb08109cdb853f074bad5acee55 Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:16:15 +0800
-Subject: [PATCH 07/29] i2c: mediatek: fix I2C usability for MT7981
-
-MT7981 actually uses MediaTek I2C controller v3 instead of v1.
-This patch adds support for I2C controller v3 fix fixes the I2C usability
-for MT7981.
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- drivers/i2c/mtk_i2c.c | 45 +++++++++++++++++++++++++++++++++++++++++--
- 1 file changed, 43 insertions(+), 2 deletions(-)
-
---- a/drivers/i2c/mtk_i2c.c
-+++ b/drivers/i2c/mtk_i2c.c
-@@ -183,9 +183,36 @@ static const uint mt_i2c_regs_v2[] = {
- 	[REG_DCM_EN] = 0xf88,
- };
- 
-+static const uint mt_i2c_regs_v3[] = {
-+	[REG_PORT] = 0x0,
-+	[REG_INTR_MASK] = 0x8,
-+	[REG_INTR_STAT] = 0xc,
-+	[REG_CONTROL] = 0x10,
-+	[REG_TRANSFER_LEN] = 0x14,
-+	[REG_TRANSAC_LEN] = 0x18,
-+	[REG_DELAY_LEN] = 0x1c,
-+	[REG_TIMING] = 0x20,
-+	[REG_START] = 0x24,
-+	[REG_EXT_CONF] = 0x28,
-+	[REG_LTIMING] = 0x2c,
-+	[REG_HS] = 0x30,
-+	[REG_IO_CONFIG] = 0x34,
-+	[REG_FIFO_ADDR_CLR] = 0x38,
-+	[REG_TRANSFER_LEN_AUX] = 0x44,
-+	[REG_CLOCK_DIV] = 0x48,
-+	[REG_SOFTRESET] = 0x50,
-+	[REG_SLAVE_ADDR] = 0x94,
-+	[REG_DEBUGSTAT] = 0xe4,
-+	[REG_DEBUGCTRL] = 0xe8,
-+	[REG_FIFO_STAT] = 0xf4,
-+	[REG_FIFO_THRESH] = 0xf8,
-+	[REG_DCM_EN] = 0xf88,
-+};
-+
- struct mtk_i2c_soc_data {
- 	const uint *regs;
- 	uint dma_sync: 1;
-+	uint ltiming_adjust: 1;
- };
- 
- struct mtk_i2c_priv {
-@@ -401,6 +428,10 @@ static int mtk_i2c_set_speed(struct udev
- 				(sample_cnt << HS_SAMPLE_OFFSET) |
- 				(step_cnt << HS_STEP_OFFSET);
- 		i2c_writel(priv, REG_HS, high_speed_reg);
-+		if (priv->soc_data->ltiming_adjust) {
-+			timing_reg = (sample_cnt << 12) | (step_cnt << 9);
-+			i2c_writel(priv, REG_LTIMING, timing_reg);
-+		}
- 	} else {
- 		ret = mtk_i2c_calculate_speed(clk_src, priv->speed,
- 					      &step_cnt, &sample_cnt);
-@@ -412,7 +443,12 @@ static int mtk_i2c_set_speed(struct udev
- 		high_speed_reg = I2C_TIME_CLR_VALUE;
- 		i2c_writel(priv, REG_TIMING, timing_reg);
- 		i2c_writel(priv, REG_HS, high_speed_reg);
-+		if (priv->soc_data->ltiming_adjust) {
-+			timing_reg = (sample_cnt << 6) | step_cnt;
-+			i2c_writel(priv, REG_LTIMING, timing_reg);
-+		}
- 	}
-+
- exit:
- 	if (mtk_i2c_clk_disable(priv))
- 		return log_msg_ret("set_speed disable clk", -1);
-@@ -725,7 +761,6 @@ static int mtk_i2c_probe(struct udevice
- 		return log_msg_ret("probe enable clk", -1);
- 
- 	mtk_i2c_init_hw(priv);
--
- 	if (mtk_i2c_clk_disable(priv))
- 		return log_msg_ret("probe disable clk", -1);
- 
-@@ -750,31 +785,37 @@ static int mtk_i2c_deblock(struct udevic
- static const struct mtk_i2c_soc_data mt76xx_soc_data = {
- 	.regs = mt_i2c_regs_v1,
- 	.dma_sync = 0,
-+	.ltiming_adjust = 0,
- };
- 
- static const struct mtk_i2c_soc_data mt7981_soc_data = {
--	.regs = mt_i2c_regs_v1,
-+	.regs = mt_i2c_regs_v3,
- 	.dma_sync = 1,
-+	.ltiming_adjust = 1,
- };
- 
- static const struct mtk_i2c_soc_data mt7986_soc_data = {
- 	.regs = mt_i2c_regs_v1,
- 	.dma_sync = 1,
-+	.ltiming_adjust = 0,
- };
- 
- static const struct mtk_i2c_soc_data mt8183_soc_data = {
- 	.regs = mt_i2c_regs_v2,
- 	.dma_sync = 1,
-+	.ltiming_adjust = 0,
- };
- 
- static const struct mtk_i2c_soc_data mt8518_soc_data = {
- 	.regs = mt_i2c_regs_v1,
- 	.dma_sync = 0,
-+	.ltiming_adjust = 0,
- };
- 
- static const struct mtk_i2c_soc_data mt8512_soc_data = {
- 	.regs = mt_i2c_regs_v1,
- 	.dma_sync = 1,
-+	.ltiming_adjust = 0,
- };
- 
- static const struct dm_i2c_ops mtk_i2c_ops = {
diff --git a/package/boot/uboot-mediatek/patches/101-08-arm-dts-enable-i2c-support-for-MediaTek-MT7981.patch b/package/boot/uboot-mediatek/patches/101-08-arm-dts-enable-i2c-support-for-MediaTek-MT7981.patch
deleted file mode 100644
index 77c4023493ad96..00000000000000
--- a/package/boot/uboot-mediatek/patches/101-08-arm-dts-enable-i2c-support-for-MediaTek-MT7981.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From e9467f40d4327cfcb80944a0f12ae195b0d7cd40 Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:16:19 +0800
-Subject: [PATCH 08/29] arm: dts: enable i2c support for MediaTek MT7981
-
-This patch enables i2c support for MediaTek MT7981
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- arch/arm/dts/mt7981.dtsi | 14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
---- a/arch/arm/dts/mt7981.dtsi
-+++ b/arch/arm/dts/mt7981.dtsi
-@@ -181,6 +181,20 @@
- 		status = "disabled";
- 	};
- 
-+	i2c0: i2c@11007000 {
-+		compatible = "mediatek,mt7981-i2c";
-+		reg = <0x11007000 0x1000>,
-+		      <0x10217080 0x80>;
-+		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
-+		clock-div = <1>;
-+		clocks = <&infracfg_ao CK_INFRA_I2CO_CK>,
-+			 <&infracfg_ao CK_INFRA_AP_DMA_CK>;
-+		clock-names = "main", "dma";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		status = "disabled";
-+	};
-+
- 	uart0: serial@11002000 {
- 		compatible = "mediatek,hsuart";
- 		reg = <0x11002000 0x400>;
diff --git a/package/boot/uboot-mediatek/patches/101-09-pwm-mtk-add-support-for-MediaTek-MT7988-SoC.patch b/package/boot/uboot-mediatek/patches/101-09-pwm-mtk-add-support-for-MediaTek-MT7988-SoC.patch
deleted file mode 100644
index 6ef62811cb1fa9..00000000000000
--- a/package/boot/uboot-mediatek/patches/101-09-pwm-mtk-add-support-for-MediaTek-MT7988-SoC.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From 646dab4a8e853b2d0789fa2ff64e7c48f5396cfa Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:16:24 +0800
-Subject: [PATCH 09/29] pwm: mtk: add support for MediaTek MT7988 SoC
-
-This patch adds PWM support for MediaTek MT7988 SoC.
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- drivers/pwm/pwm-mtk.c | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/drivers/pwm/pwm-mtk.c
-+++ b/drivers/pwm/pwm-mtk.c
-@@ -205,12 +205,19 @@ static const struct mtk_pwm_soc mt7986_d
- 	.reg_ver = PWM_REG_V1,
- };
- 
-+static const struct mtk_pwm_soc mt7988_data = {
-+	.num_pwms = 8,
-+	.pwm45_fixup = false,
-+	.reg_ver = PWM_REG_V2,
-+};
-+
- static const struct udevice_id mtk_pwm_ids[] = {
- 	{ .compatible = "mediatek,mt7622-pwm", .data = (ulong)&mt7622_data },
- 	{ .compatible = "mediatek,mt7623-pwm", .data = (ulong)&mt7623_data },
- 	{ .compatible = "mediatek,mt7629-pwm", .data = (ulong)&mt7629_data },
- 	{ .compatible = "mediatek,mt7981-pwm", .data = (ulong)&mt7981_data },
- 	{ .compatible = "mediatek,mt7986-pwm", .data = (ulong)&mt7986_data },
-+	{ .compatible = "mediatek,mt7988-pwm", .data = (ulong)&mt7988_data },
- 	{ }
- };
- 
diff --git a/package/boot/uboot-mediatek/patches/101-10-clk-mediatek-add-clock-driver-support-for-MediaTek-M.patch b/package/boot/uboot-mediatek/patches/101-10-clk-mediatek-add-clock-driver-support-for-MediaTek-M.patch
deleted file mode 100644
index 12eda828fa9b9e..00000000000000
--- a/package/boot/uboot-mediatek/patches/101-10-clk-mediatek-add-clock-driver-support-for-MediaTek-M.patch
+++ /dev/null
@@ -1,1505 +0,0 @@
-From 94306126baa215c39e9fd5328550586dedf00230 Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:16:28 +0800
-Subject: [PATCH 10/29] clk: mediatek: add clock driver support for MediaTek
- MT7988 SoC
-
-This patch adds clock driver support for MediaTek MT7988 SoC
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- drivers/clk/mediatek/Makefile          |    1 +
- drivers/clk/mediatek/clk-mt7988.c      | 1123 ++++++++++++++++++++++++
- include/dt-bindings/clock/mt7988-clk.h |  349 ++++++++
- 3 files changed, 1473 insertions(+)
- create mode 100644 drivers/clk/mediatek/clk-mt7988.c
- create mode 100644 include/dt-bindings/clock/mt7988-clk.h
-
---- a/drivers/clk/mediatek/Makefile
-+++ b/drivers/clk/mediatek/Makefile
-@@ -9,6 +9,7 @@ obj-$(CONFIG_TARGET_MT7622) += clk-mt762
- obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o
- obj-$(CONFIG_TARGET_MT7986) += clk-mt7986.o
- obj-$(CONFIG_TARGET_MT7981) += clk-mt7981.o
-+obj-$(CONFIG_TARGET_MT7988) += clk-mt7988.o
- obj-$(CONFIG_TARGET_MT8183) += clk-mt8183.o
- obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o
- obj-$(CONFIG_TARGET_MT8518) += clk-mt8518.o
---- /dev/null
-+++ b/drivers/clk/mediatek/clk-mt7988.c
-@@ -0,0 +1,1123 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * MediaTek clock driver for MT7988 SoC
-+ *
-+ * Copyright (C) 2022 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ */
-+
-+#include <dm.h>
-+#include <log.h>
-+#include <asm/arch-mediatek/reset.h>
-+#include <asm/io.h>
-+#include <dt-bindings/clock/mt7988-clk.h>
-+#include <linux/bitops.h>
-+
-+#include "clk-mtk.h"
-+
-+#define MT7988_CLK_PDN		0x250
-+#define MT7988_CLK_PDN_EN_WRITE BIT(31)
-+
-+#define MT7988_ETHDMA_RST_CTRL_OFS	0x34
-+#define MT7988_ETHWARP_RST_CTRL_OFS	0x8
-+
-+#define XTAL_FACTOR(_id, _name, _parent, _mult, _div)                          \
-+	FACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL)
-+
-+#define PLL_FACTOR(_id, _name, _parent, _mult, _div)                           \
-+	FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
-+
-+#define TOP_FACTOR(_id, _name, _parent, _mult, _div)                           \
-+	FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
-+
-+#define INFRA_FACTOR(_id, _name, _parent, _mult, _div)                         \
-+	FACTOR(_id, _parent, _mult, _div, CLK_PARENT_INFRASYS)
-+
-+/* FIXED PLLS */
-+static const struct mtk_fixed_clk apmixedsys_mtk_plls[] = {
-+	FIXED_CLK(CK_APMIXED_NETSYSPLL, CLK_XTAL, 850000000),
-+	FIXED_CLK(CK_APMIXED_MPLL, CLK_XTAL, 416000000),
-+	FIXED_CLK(CK_APMIXED_MMPLL, CLK_XTAL, 720000000),
-+	FIXED_CLK(CK_APMIXED_APLL2, CLK_XTAL, 196608000),
-+	FIXED_CLK(CK_APMIXED_NET1PLL, CLK_XTAL, 2500000000),
-+	FIXED_CLK(CK_APMIXED_NET2PLL, CLK_XTAL, 800000000),
-+	FIXED_CLK(CK_APMIXED_WEDMCUPLL, CLK_XTAL, 208000000),
-+	FIXED_CLK(CK_APMIXED_SGMPLL, CLK_XTAL, 325000000),
-+	FIXED_CLK(CK_APMIXED_ARM_B, CLK_XTAL, 1500000000),
-+	FIXED_CLK(CK_APMIXED_CCIPLL2_B, CLK_XTAL, 960000000),
-+	FIXED_CLK(CK_APMIXED_USXGMIIPLL, CLK_XTAL, 644533000),
-+	FIXED_CLK(CK_APMIXED_MSDCPLL, CLK_XTAL, 400000000),
-+};
-+
-+/* TOPCKGEN FIXED DIV */
-+static const struct mtk_fixed_factor topckgen_mtk_fixed_factors[] = {
-+	XTAL_FACTOR(CK_TOP_CB_CKSQ_40M, "cb_cksq_40m", CLK_XTAL, 1, 1),
-+	PLL_FACTOR(CK_TOP_CB_M_416M, "cb_m_416m", CK_APMIXED_MPLL, 1, 1),
-+	PLL_FACTOR(CK_TOP_CB_M_D2, "cb_m_d2", CK_APMIXED_MPLL, 1, 2),
-+	PLL_FACTOR(CK_TOP_M_D3_D2, "m_d3_d2", CK_APMIXED_MPLL, 1, 2),
-+	PLL_FACTOR(CK_TOP_CB_M_D4, "cb_m_d4", CK_APMIXED_MPLL, 1, 4),
-+	PLL_FACTOR(CK_TOP_CB_M_D8, "cb_m_d8", CK_APMIXED_MPLL, 1, 8),
-+	PLL_FACTOR(CK_TOP_M_D8_D2, "m_d8_d2", CK_APMIXED_MPLL, 1, 16),
-+	PLL_FACTOR(CK_TOP_CB_MM_720M, "cb_mm_720m", CK_APMIXED_MMPLL, 1, 1),
-+	PLL_FACTOR(CK_TOP_CB_MM_D2, "cb_mm_d2", CK_APMIXED_MMPLL, 1, 2),
-+	PLL_FACTOR(CK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", CK_APMIXED_MMPLL, 1, 15),
-+	PLL_FACTOR(CK_TOP_CB_MM_D4, "cb_mm_d4", CK_APMIXED_MMPLL, 1, 4),
-+	PLL_FACTOR(CK_TOP_MM_D6_D2, "mm_d6_d2", CK_APMIXED_MMPLL, 1, 12),
-+	PLL_FACTOR(CK_TOP_CB_MM_D8, "cb_mm_d8", CK_APMIXED_MMPLL, 1, 8),
-+	PLL_FACTOR(CK_TOP_CB_APLL2_196M, "cb_apll2_196m", CK_APMIXED_APLL2, 1,
-+		   1),
-+	PLL_FACTOR(CK_TOP_CB_APLL2_D4, "cb_apll2_d4", CK_APMIXED_APLL2, 1, 4),
-+	PLL_FACTOR(CK_TOP_CB_NET1_D4, "cb_net1_d4", CK_APMIXED_NET1PLL, 1, 4),
-+	PLL_FACTOR(CK_TOP_CB_NET1_D5, "cb_net1_d5", CK_APMIXED_NET1PLL, 1, 5),
-+	PLL_FACTOR(CK_TOP_NET1_D5_D2, "net1_d5_d2", CK_APMIXED_NET1PLL, 1, 10),
-+	PLL_FACTOR(CK_TOP_NET1_D5_D4, "net1_d5_d4", CK_APMIXED_NET1PLL, 1, 20),
-+	PLL_FACTOR(CK_TOP_CB_NET1_D8, "cb_net1_d8", CK_APMIXED_NET1PLL, 1, 8),
-+	PLL_FACTOR(CK_TOP_NET1_D8_D2, "net1_d8_d2", CK_APMIXED_NET1PLL, 1, 16),
-+	PLL_FACTOR(CK_TOP_NET1_D8_D4, "net1_d8_d4", CK_APMIXED_NET1PLL, 1, 32),
-+	PLL_FACTOR(CK_TOP_NET1_D8_D8, "net1_d8_d8", CK_APMIXED_NET1PLL, 1, 64),
-+	PLL_FACTOR(CK_TOP_NET1_D8_D16, "net1_d8_d16", CK_APMIXED_NET1PLL, 1,
-+		   128),
-+	PLL_FACTOR(CK_TOP_CB_NET2_800M, "cb_net2_800m", CK_APMIXED_NET2PLL, 1,
-+		   1),
-+	PLL_FACTOR(CK_TOP_CB_NET2_D2, "cb_net2_d2", CK_APMIXED_NET2PLL, 1, 2),
-+	PLL_FACTOR(CK_TOP_CB_NET2_D4, "cb_net2_d4", CK_APMIXED_NET2PLL, 1, 4),
-+	PLL_FACTOR(CK_TOP_NET2_D4_D4, "net2_d4_d4", CK_APMIXED_NET2PLL, 1, 16),
-+	PLL_FACTOR(CK_TOP_NET2_D4_D8, "net2_d4_d8", CK_APMIXED_NET2PLL, 1, 32),
-+	PLL_FACTOR(CK_TOP_CB_NET2_D6, "cb_net2_d6", CK_APMIXED_NET2PLL, 1, 6),
-+	PLL_FACTOR(CK_TOP_CB_NET2_D8, "cb_net2_d8", CK_APMIXED_NET2PLL, 1, 8),
-+	PLL_FACTOR(CK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m",
-+		   CK_APMIXED_WEDMCUPLL, 1, 1),
-+	PLL_FACTOR(CK_TOP_CB_SGM_325M, "cb_sgm_325m", CK_APMIXED_SGMPLL, 1, 1),
-+	PLL_FACTOR(CK_TOP_CB_NETSYS_850M, "cb_netsys_850m",
-+		   CK_APMIXED_NETSYSPLL, 1, 1),
-+	PLL_FACTOR(CK_TOP_CB_MSDC_400M, "cb_msdc_400m", CK_APMIXED_MSDCPLL, 1,
-+		   1),
-+	TOP_FACTOR(CK_TOP_CKSQ_40M_D2, "cksq_40m_d2", CK_TOP_CB_CKSQ_40M, 1, 2),
-+	TOP_FACTOR(CK_TOP_CB_RTC_32K, "cb_rtc_32k", CK_TOP_CB_CKSQ_40M, 1,
-+		   1250),
-+	TOP_FACTOR(CK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", CK_TOP_CB_CKSQ_40M, 1,
-+		   1220),
-+	TOP_FACTOR(CK_TOP_INFRA_F32K, "csw_infra_f32k", CK_TOP_CB_RTC_32P7K, 1,
-+		   1),
-+	XTAL_FACTOR(CK_TOP_CKSQ_SRC, "cksq_src", CLK_XTAL, 1, 1),
-+	TOP_FACTOR(CK_TOP_NETSYS_2X, "netsys_2x", CK_TOP_NETSYS_2X_SEL, 1, 1),
-+	TOP_FACTOR(CK_TOP_NETSYS_GSW, "netsys_gsw", CK_TOP_NETSYS_GSW_SEL, 1,
-+		   1),
-+	TOP_FACTOR(CK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu",
-+		   CK_TOP_NETSYS_MCU_SEL, 1, 1),
-+	TOP_FACTOR(CK_TOP_EIP197, "eip197", CK_TOP_EIP197_SEL, 1, 1),
-+	TOP_FACTOR(CK_TOP_EMMC_250M, "emmc_250m", CK_TOP_EMMC_250M_SEL, 1, 1),
-+	TOP_FACTOR(CK_TOP_EMMC_400M, "emmc_400m", CK_TOP_EMMC_400M_SEL, 1, 1),
-+	TOP_FACTOR(CK_TOP_SPI, "spi", CK_TOP_SPI_SEL, 1, 1),
-+	TOP_FACTOR(CK_TOP_SPIM_MST, "spim_mst", CK_TOP_SPIM_MST_SEL, 1, 1),
-+	TOP_FACTOR(CK_TOP_NFI1X, "nfi1x", CK_TOP_NFI1X_SEL, 1, 1),
-+	TOP_FACTOR(CK_TOP_SPINFI_BCK, "spinfi_bck", CK_TOP_SPINFI_SEL, 1, 1),
-+	TOP_FACTOR(CK_TOP_I2C_BCK, "i2c_bck", CK_TOP_I2C_SEL, 1, 1),
-+	TOP_FACTOR(CK_TOP_USB_SYS, "usb_sys", CK_TOP_USB_SYS_SEL, 1, 1),
-+	TOP_FACTOR(CK_TOP_USB_SYS_P1, "usb_sys_p1", CK_TOP_USB_SYS_P1_SEL, 1,
-+		   1),
-+	TOP_FACTOR(CK_TOP_USB_XHCI, "usb_xhci", CK_TOP_USB_XHCI_SEL, 1, 1),
-+	TOP_FACTOR(CK_TOP_USB_XHCI_P1, "usb_xhci_p1", CK_TOP_USB_XHCI_P1_SEL, 1,
-+		   1),
-+	TOP_FACTOR(CK_TOP_USB_FRMCNT, "usb_frmcnt", CK_TOP_USB_FRMCNT_SEL, 1,
-+		   1),
-+	TOP_FACTOR(CK_TOP_USB_FRMCNT_P1, "usb_frmcnt_p1",
-+		   CK_TOP_USB_FRMCNT_P1_SEL, 1, 1),
-+	TOP_FACTOR(CK_TOP_AUD, "aud", CK_TOP_AUD_SEL, 1, 1),
-+	TOP_FACTOR(CK_TOP_A1SYS, "a1sys", CK_TOP_A1SYS_SEL, 1, 1),
-+	TOP_FACTOR(CK_TOP_AUD_L, "aud_l", CK_TOP_AUD_L_SEL, 1, 1),
-+	TOP_FACTOR(CK_TOP_A_TUNER, "a_tuner", CK_TOP_A_TUNER_SEL, 1, 1),
-+	TOP_FACTOR(CK_TOP_SYSAXI, "sysaxi", CK_TOP_SYSAXI_SEL, 1, 1),
-+	TOP_FACTOR(CK_TOP_INFRA_F26M, "csw_infra_f26m", CK_TOP_INFRA_F26M_SEL,
-+		   1, 1),
-+	TOP_FACTOR(CK_TOP_USB_REF, "usb_ref", CK_TOP_CKSQ_SRC, 1, 1),
-+	TOP_FACTOR(CK_TOP_USB_CK_P1, "usb_ck_p1", CK_TOP_CKSQ_SRC, 1, 1),
-+};
-+
-+/* TOPCKGEN MUX PARENTS */
-+static const int netsys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_D2,
-+				      CK_TOP_CB_MM_D2 };
-+
-+static const int netsys_500m_parents[] = { CK_TOP_CB_CKSQ_40M,
-+					   CK_TOP_CB_NET1_D5,
-+					   CK_TOP_NET1_D5_D2 };
-+
-+static const int netsys_2x_parents[] = { CK_TOP_CB_CKSQ_40M,
-+					 CK_TOP_CB_NET2_800M,
-+					 CK_TOP_CB_MM_720M };
-+
-+static const int netsys_gsw_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET1_D4,
-+					  CK_TOP_CB_NET1_D5 };
-+
-+static const int eth_gmii_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4 };
-+
-+static const int netsys_mcu_parents[] = {
-+	CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_800M, CK_TOP_CB_MM_720M,
-+	CK_TOP_CB_NET1_D4,  CK_TOP_CB_NET1_D5,   CK_TOP_CB_M_416M
-+};
-+
-+static const int eip197_parents[] = {
-+	CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NETSYS_850M, CK_TOP_CB_NET2_800M,
-+	CK_TOP_CB_MM_720M,  CK_TOP_CB_NET1_D4,     CK_TOP_CB_NET1_D5
-+};
-+
-+static const int axi_infra_parents[] = { CK_TOP_CB_CKSQ_40M,
-+					 CK_TOP_NET1_D8_D2 };
-+
-+static const int uart_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D8,
-+				    CK_TOP_M_D8_D2 };
-+
-+static const int emmc_250m_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D2,
-+					 CK_TOP_CB_MM_D4 };
-+
-+static const int emmc_400m_parents[] = {
-+	CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MSDC_400M, CK_TOP_CB_MM_D2,
-+	CK_TOP_CB_M_D2,     CK_TOP_CB_MM_D4,     CK_TOP_NET1_D8_D2
-+};
-+
-+static const int spi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2,
-+				   CK_TOP_CB_MM_D4,    CK_TOP_NET1_D8_D2,
-+				   CK_TOP_CB_NET2_D6,  CK_TOP_NET1_D5_D4,
-+				   CK_TOP_CB_M_D4,     CK_TOP_NET1_D8_D4 };
-+
-+static const int nfi1x_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_D4,
-+				     CK_TOP_NET1_D8_D2,  CK_TOP_CB_NET2_D6,
-+				     CK_TOP_CB_M_D4,     CK_TOP_CB_MM_D8,
-+				     CK_TOP_NET1_D8_D4,  CK_TOP_CB_M_D8 };
-+
-+static const int spinfi_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_CB_CKSQ_40M,
-+				      CK_TOP_NET1_D5_D4,  CK_TOP_CB_M_D4,
-+				      CK_TOP_CB_MM_D8,    CK_TOP_NET1_D8_D4,
-+				      CK_TOP_MM_D6_D2,    CK_TOP_CB_M_D8 };
-+
-+static const int pwm_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2,
-+				   CK_TOP_NET1_D5_D4,  CK_TOP_CB_M_D4,
-+				   CK_TOP_M_D8_D2,     CK_TOP_CB_RTC_32K };
-+
-+static const int i2c_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4,
-+				   CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 };
-+
-+static const int pcie_mbist_250m_parents[] = { CK_TOP_CB_CKSQ_40M,
-+					       CK_TOP_NET1_D5_D2 };
-+
-+static const int pextp_tl_ck_parents[] = { CK_TOP_CB_CKSQ_40M,
-+					   CK_TOP_CB_NET2_D6, CK_TOP_CB_MM_D8,
-+					   CK_TOP_M_D8_D2, CK_TOP_CB_RTC_32K };
-+
-+static const int usb_frmcnt_parents[] = { CK_TOP_CB_CKSQ_40M,
-+					  CK_TOP_CB_MM_D3_D5 };
-+
-+static const int aud_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M };
-+
-+static const int a1sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_D4 };
-+
-+static const int aud_l_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M,
-+				     CK_TOP_M_D8_D2 };
-+
-+static const int sspxtp_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_M_D8_D2 };
-+
-+static const int usxgmii_sbus_0_parents[] = { CK_TOP_CB_CKSQ_40M,
-+					      CK_TOP_NET1_D8_D4 };
-+
-+static const int sgm_0_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_SGM_325M };
-+
-+static const int sysapb_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D3_D2 };
-+
-+static const int eth_refck_50m_parents[] = { CK_TOP_CB_CKSQ_40M,
-+					     CK_TOP_NET2_D4_D4 };
-+
-+static const int eth_sys_200m_parents[] = { CK_TOP_CB_CKSQ_40M,
-+					    CK_TOP_CB_NET2_D4 };
-+
-+static const int eth_xgmii_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_NET1_D8_D8,
-+					 CK_TOP_NET1_D8_D16 };
-+
-+static const int bus_tops_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET1_D5,
-+					CK_TOP_CB_NET2_D2 };
-+
-+static const int npu_tops_parents[] = { CK_TOP_CB_CKSQ_40M,
-+					CK_TOP_CB_NET2_800M };
-+
-+static const int dramc_md32_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2,
-+					  CK_TOP_CB_WEDMCU_208M };
-+
-+static const int da_xtp_glb_p0_parents[] = { CK_TOP_CB_CKSQ_40M,
-+					     CK_TOP_CB_NET2_D8 };
-+
-+static const int mcusys_backup_625m_parents[] = { CK_TOP_CB_CKSQ_40M,
-+						  CK_TOP_CB_NET1_D4 };
-+
-+static const int macsec_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_SGM_325M,
-+				      CK_TOP_CB_NET1_D8 };
-+
-+static const int netsys_tops_400m_parents[] = { CK_TOP_CB_CKSQ_40M,
-+						CK_TOP_CB_NET2_D2 };
-+
-+static const int eth_mii_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_NET2_D4_D8 };
-+
-+#define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs,    \
-+		_shift, _width, _gate, _upd_ofs, _upd)                         \
-+	{                                                                      \
-+		.id = _id, .mux_reg = _mux_ofs, .mux_set_reg = _mux_set_ofs,   \
-+		.mux_clr_reg = _mux_clr_ofs, .upd_reg = _upd_ofs,              \
-+		.upd_shift = _upd, .mux_shift = _shift,                        \
-+		.mux_mask = BIT(_width) - 1, .gate_reg = _mux_ofs,             \
-+		.gate_shift = _gate, .parent = _parents,                       \
-+		.num_parents = ARRAY_SIZE(_parents),                           \
-+		.flags = CLK_MUX_SETCLR_UPD,                                   \
-+	}
-+
-+/* TOPCKGEN MUX_GATE */
-+static const struct mtk_composite topckgen_mtk_muxes[] = {
-+	TOP_MUX(CK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x0, 0x4, 0x8,
-+		0, 2, 7, 0x1c0, 0),
-+	TOP_MUX(CK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents,
-+		0x0, 0x4, 0x8, 8, 2, 15, 0x1c0, 1),
-+	TOP_MUX(CK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x0,
-+		0x4, 0x8, 16, 2, 23, 0x1c0, 2),
-+	TOP_MUX(CK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel", netsys_gsw_parents,
-+		0x0, 0x4, 0x8, 24, 2, 31, 0x1c0, 3),
-+	TOP_MUX(CK_TOP_ETH_GMII_SEL, "eth_gmii_sel", eth_gmii_parents, 0x10,
-+		0x14, 0x18, 0, 1, 7, 0x1c0, 4),
-+	TOP_MUX(CK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents,
-+		0x10, 0x14, 0x18, 8, 3, 15, 0x1c0, 5),
-+	TOP_MUX(CK_TOP_NETSYS_PAO_2X_SEL, "netsys_pao_2x_sel",
-+		netsys_mcu_parents, 0x10, 0x14, 0x18, 16, 3, 23, 0x1c0, 6),
-+	TOP_MUX(CK_TOP_EIP197_SEL, "eip197_sel", eip197_parents, 0x10, 0x14,
-+		0x18, 24, 3, 31, 0x1c0, 7),
-+	TOP_MUX(CK_TOP_AXI_INFRA_SEL, "axi_infra_sel", axi_infra_parents, 0x20,
-+		0x24, 0x28, 0, 1, 7, 0x1c0, 8),
-+	TOP_MUX(CK_TOP_UART_SEL, "uart_sel", uart_parents, 0x20, 0x24, 0x28, 8,
-+		2, 15, 0x1c0, 9),
-+	TOP_MUX(CK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, 0x20,
-+		0x24, 0x28, 16, 2, 23, 0x1c0, 10),
-+	TOP_MUX(CK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents, 0x20,
-+		0x24, 0x28, 24, 3, 31, 0x1c0, 11),
-+	TOP_MUX(CK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x30, 0x34, 0x38, 0, 3,
-+		7, 0x1c0, 12),
-+	TOP_MUX(CK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x30, 0x34,
-+		0x38, 8, 3, 15, 0x1c0, 13),
-+	TOP_MUX(CK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x30, 0x34, 0x38,
-+		16, 3, 23, 0x1c0, 14),
-+	TOP_MUX(CK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x30, 0x34,
-+		0x38, 24, 3, 31, 0x1c0, 15),
-+	TOP_MUX(CK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x40, 0x44, 0x48, 0, 3,
-+		7, 0x1c0, 16),
-+	TOP_MUX(CK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x40, 0x44, 0x48, 8, 2,
-+		15, 0x1c0, 17),
-+	TOP_MUX(CK_TOP_PCIE_MBIST_250M_SEL, "pcie_mbist_250m_sel",
-+		pcie_mbist_250m_parents, 0x40, 0x44, 0x48, 16, 1, 23, 0x1c0,
-+		18),
-+	TOP_MUX(CK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents,
-+		0x40, 0x44, 0x48, 24, 3, 31, 0x1c0, 19),
-+	TOP_MUX(CK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_ck_p1_sel",
-+		pextp_tl_ck_parents, 0x50, 0x54, 0x58, 0, 3, 7, 0x1c0, 20),
-+	TOP_MUX(CK_TOP_PEXTP_TL_P2_SEL, "pextp_tl_ck_p2_sel",
-+		pextp_tl_ck_parents, 0x50, 0x54, 0x58, 8, 3, 15, 0x1c0, 21),
-+	TOP_MUX(CK_TOP_PEXTP_TL_P3_SEL, "pextp_tl_ck_p3_sel",
-+		pextp_tl_ck_parents, 0x50, 0x54, 0x58, 16, 3, 23, 0x1c0, 22),
-+	TOP_MUX(CK_TOP_USB_SYS_SEL, "usb_sys_sel", eth_gmii_parents, 0x50, 0x54,
-+		0x58, 24, 1, 31, 0x1c0, 23),
-+	TOP_MUX(CK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel", eth_gmii_parents, 0x60,
-+		0x64, 0x68, 0, 1, 7, 0x1c0, 24),
-+	TOP_MUX(CK_TOP_USB_XHCI_SEL, "usb_xhci_sel", eth_gmii_parents, 0x60,
-+		0x64, 0x68, 8, 1, 15, 0x1c0, 25),
-+	TOP_MUX(CK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel", eth_gmii_parents,
-+		0x60, 0x64, 0x68, 16, 1, 23, 0x1c0, 26),
-+	TOP_MUX(CK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", usb_frmcnt_parents,
-+		0x60, 0x64, 0x68, 24, 1, 31, 0x1c0, 27),
-+	TOP_MUX(CK_TOP_USB_FRMCNT_P1_SEL, "usb_frmcnt_p1_sel",
-+		usb_frmcnt_parents, 0x70, 0x74, 0x78, 0, 1, 7, 0x1c0, 28),
-+	TOP_MUX(CK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x70, 0x74, 0x78, 8, 1,
-+		15, 0x1c0, 29),
-+	TOP_MUX(CK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x70, 0x74, 0x78,
-+		16, 1, 23, 0x1c0, 30),
-+	TOP_MUX(CK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x70, 0x74, 0x78,
-+		24, 2, 31, 0x1c4, 0),
-+	TOP_MUX(CK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents, 0x80, 0x84,
-+		0x88, 0, 1, 7, 0x1c4, 1),
-+	TOP_MUX(CK_TOP_SSPXTP_SEL, "sspxtp_sel", sspxtp_parents, 0x80, 0x84,
-+		0x88, 8, 1, 15, 0x1c4, 2),
-+	TOP_MUX(CK_TOP_USB_PHY_SEL, "usb_phy_sel", sspxtp_parents, 0x80, 0x84,
-+		0x88, 16, 1, 23, 0x1c4, 3),
-+	TOP_MUX(CK_TOP_USXGMII_SBUS_0_SEL, "usxgmii_sbus_0_sel",
-+		usxgmii_sbus_0_parents, 0x80, 0x84, 0x88, 24, 1, 31, 0x1c4, 4),
-+	TOP_MUX(CK_TOP_USXGMII_SBUS_1_SEL, "usxgmii_sbus_1_sel",
-+		usxgmii_sbus_0_parents, 0x90, 0x94, 0x98, 0, 1, 7, 0x1c4, 5),
-+	TOP_MUX(CK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents, 0x90, 0x94, 0x98,
-+		8, 1, 15, 0x1c4, 6),
-+	TOP_MUX(CK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel", usxgmii_sbus_0_parents,
-+		0x90, 0x94, 0x98, 16, 1, 23, 0x1c4, 7),
-+	TOP_MUX(CK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents, 0x90, 0x94, 0x98,
-+		24, 1, 31, 0x1c4, 8),
-+	TOP_MUX(CK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel", usxgmii_sbus_0_parents,
-+		0xa0, 0xa4, 0xa8, 0, 1, 7, 0x1c4, 9),
-+	TOP_MUX(CK_TOP_XFI_PHY_0_XTAL_SEL, "xfi_phy_0_xtal_sel", sspxtp_parents,
-+		0xa0, 0xa4, 0xa8, 8, 1, 15, 0x1c4, 10),
-+	TOP_MUX(CK_TOP_XFI_PHY_1_XTAL_SEL, "xfi_phy_1_xtal_sel", sspxtp_parents,
-+		0xa0, 0xa4, 0xa8, 16, 1, 23, 0x1c4, 11),
-+	TOP_MUX(CK_TOP_SYSAXI_SEL, "sysaxi_sel", axi_infra_parents, 0xa0, 0xa4,
-+		0xa8, 24, 1, 31, 0x1c4, 12),
-+	TOP_MUX(CK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0xb0, 0xb4,
-+		0xb8, 0, 1, 7, 0x1c4, 13),
-+	TOP_MUX(CK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel",
-+		eth_refck_50m_parents, 0xb0, 0xb4, 0xb8, 8, 1, 15, 0x1c4, 14),
-+	TOP_MUX(CK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel",
-+		eth_sys_200m_parents, 0xb0, 0xb4, 0xb8, 16, 1, 23, 0x1c4, 15),
-+	TOP_MUX(CK_TOP_ETH_SYS_SEL, "eth_sys_sel", pcie_mbist_250m_parents,
-+		0xb0, 0xb4, 0xb8, 24, 1, 31, 0x1c4, 16),
-+	TOP_MUX(CK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel", eth_xgmii_parents, 0xc0,
-+		0xc4, 0xc8, 0, 2, 7, 0x1c4, 17),
-+	TOP_MUX(CK_TOP_BUS_TOPS_SEL, "bus_tops_sel", bus_tops_parents, 0xc0,
-+		0xc4, 0xc8, 8, 2, 15, 0x1c4, 18),
-+	TOP_MUX(CK_TOP_NPU_TOPS_SEL, "npu_tops_sel", npu_tops_parents, 0xc0,
-+		0xc4, 0xc8, 16, 1, 23, 0x1c4, 19),
-+	TOP_MUX(CK_TOP_DRAMC_SEL, "dramc_sel", sspxtp_parents, 0xc0, 0xc4, 0xc8,
-+		24, 1, 31, 0x1c4, 20),
-+	TOP_MUX(CK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents,
-+		0xd0, 0xd4, 0xd8, 0, 2, 7, 0x1c4, 21),
-+	TOP_MUX(CK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", sspxtp_parents,
-+		0xd0, 0xd4, 0xd8, 8, 1, 15, 0x1c4, 22),
-+	TOP_MUX(CK_TOP_PEXTP_P0_SEL, "pextp_p0_sel", sspxtp_parents, 0xd0, 0xd4,
-+		0xd8, 16, 1, 23, 0x1c4, 23),
-+	TOP_MUX(CK_TOP_PEXTP_P1_SEL, "pextp_p1_sel", sspxtp_parents, 0xd0, 0xd4,
-+		0xd8, 24, 1, 31, 0x1c4, 24),
-+	TOP_MUX(CK_TOP_PEXTP_P2_SEL, "pextp_p2_sel", sspxtp_parents, 0xe0, 0xe4,
-+		0xe8, 0, 1, 7, 0x1c4, 25),
-+	TOP_MUX(CK_TOP_PEXTP_P3_SEL, "pextp_p3_sel", sspxtp_parents, 0xe0, 0xe4,
-+		0xe8, 8, 1, 15, 0x1c4, 26),
-+	TOP_MUX(CK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel",
-+		da_xtp_glb_p0_parents, 0xe0, 0xe4, 0xe8, 16, 1, 23, 0x1c4, 27),
-+	TOP_MUX(CK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel",
-+		da_xtp_glb_p0_parents, 0xe0, 0xe4, 0xe8, 24, 1, 31, 0x1c4, 28),
-+	TOP_MUX(CK_TOP_DA_XTP_GLB_P2_SEL, "da_xtp_glb_p2_sel",
-+		da_xtp_glb_p0_parents, 0xf0, 0xf4, 0xf8, 0, 1, 7, 0x1c4, 29),
-+	TOP_MUX(CK_TOP_DA_XTP_GLB_P3_SEL, "da_xtp_glb_p3_sel",
-+		da_xtp_glb_p0_parents, 0xf0, 0xf4, 0xf8, 8, 1, 15, 0x1c4, 30),
-+	TOP_MUX(CK_TOP_CKM_SEL, "ckm_sel", sspxtp_parents, 0xf0, 0xf4, 0xf8, 16,
-+		1, 23, 0x1c8, 0),
-+	TOP_MUX(CK_TOP_DA_SELM_XTAL_SEL, "da_selm_xtal_sel", sspxtp_parents,
-+		0xf0, 0xf4, 0xf8, 24, 1, 31, 0x1c8, 1),
-+	TOP_MUX(CK_TOP_PEXTP_SEL, "pextp_sel", sspxtp_parents, 0x100, 0x104,
-+		0x108, 0, 1, 7, 0x1c8, 2),
-+	TOP_MUX(CK_TOP_TOPS_P2_26M_SEL, "tops_p2_26m_sel", sspxtp_parents,
-+		0x100, 0x104, 0x108, 8, 1, 15, 0x1c8, 3),
-+	TOP_MUX(CK_TOP_MCUSYS_BACKUP_625M_SEL, "mcusys_backup_625m_sel",
-+		mcusys_backup_625m_parents, 0x100, 0x104, 0x108, 16, 1, 23,
-+		0x1c8, 4),
-+	TOP_MUX(CK_TOP_NETSYS_SYNC_250M_SEL, "netsys_sync_250m_sel",
-+		pcie_mbist_250m_parents, 0x100, 0x104, 0x108, 24, 1, 31, 0x1c8,
-+		5),
-+	TOP_MUX(CK_TOP_MACSEC_SEL, "macsec_sel", macsec_parents, 0x110, 0x114,
-+		0x118, 0, 2, 7, 0x1c8, 6),
-+	TOP_MUX(CK_TOP_NETSYS_TOPS_400M_SEL, "netsys_tops_400m_sel",
-+		netsys_tops_400m_parents, 0x110, 0x114, 0x118, 8, 1, 15, 0x1c8,
-+		7),
-+	TOP_MUX(CK_TOP_NETSYS_PPEFB_250M_SEL, "netsys_ppefb_250m_sel",
-+		pcie_mbist_250m_parents, 0x110, 0x114, 0x118, 16, 1, 23, 0x1c8,
-+		8),
-+	TOP_MUX(CK_TOP_NETSYS_WARP_SEL, "netsys_warp_sel", netsys_parents,
-+		0x110, 0x114, 0x118, 24, 2, 31, 0x1c8, 9),
-+	TOP_MUX(CK_TOP_ETH_MII_SEL, "eth_mii_sel", eth_mii_parents, 0x120,
-+		0x124, 0x128, 0, 1, 7, 0x1c8, 10),
-+	TOP_MUX(CK_TOP_CK_NPU_SEL_CM_TOPS_SEL, "ck_npu_sel_cm_tops_sel",
-+		netsys_2x_parents, 0x120, 0x124, 0x128, 8, 2, 15, 0x1c8, 11),
-+};
-+
-+/* INFRA FIXED DIV */
-+static const struct mtk_fixed_factor infracfg_mtk_fixed_factor[] = {
-+	TOP_FACTOR(CK_INFRA_CK_F26M, "infra_ck_f26m", CK_TOP_INFRA_F26M_SEL, 1,
-+		   1),
-+	TOP_FACTOR(CK_INFRA_PWM_O, "infra_pwm_o", CK_TOP_PWM_SEL, 1, 1),
-+	TOP_FACTOR(CK_INFRA_PCIE_OCC_P0, "infra_pcie_ck_occ_p0",
-+		   CK_TOP_PEXTP_TL_SEL, 1, 1),
-+	TOP_FACTOR(CK_INFRA_PCIE_OCC_P1, "infra_pcie_ck_occ_p1",
-+		   CK_TOP_PEXTP_TL_P1_SEL, 1, 1),
-+	TOP_FACTOR(CK_INFRA_PCIE_OCC_P2, "infra_pcie_ck_occ_p2",
-+		   CK_TOP_PEXTP_TL_P2_SEL, 1, 1),
-+	TOP_FACTOR(CK_INFRA_PCIE_OCC_P3, "infra_pcie_ck_occ_p3",
-+		   CK_TOP_PEXTP_TL_P3_SEL, 1, 1),
-+	TOP_FACTOR(CK_INFRA_133M_HCK, "infra_133m_hck", CK_TOP_SYSAXI, 1, 1),
-+	INFRA_FACTOR(CK_INFRA_133M_PHCK, "infra_133m_phck", CK_INFRA_133M_HCK,
-+		     1, 1),
-+	INFRA_FACTOR(CK_INFRA_66M_PHCK, "infra_66m_phck", CK_INFRA_133M_HCK, 1,
-+		     1),
-+	TOP_FACTOR(CK_INFRA_FAUD_L_O, "infra_faud_l_o", CK_TOP_AUD_L, 1, 1),
-+	TOP_FACTOR(CK_INFRA_FAUD_AUD_O, "infra_faud_aud_o", CK_TOP_A1SYS, 1, 1),
-+	TOP_FACTOR(CK_INFRA_FAUD_EG2_O, "infra_faud_eg2_o", CK_TOP_A_TUNER, 1,
-+		   1),
-+	TOP_FACTOR(CK_INFRA_I2C_O, "infra_i2c_o", CK_TOP_I2C_BCK, 1, 1),
-+	TOP_FACTOR(CK_INFRA_UART_O0, "infra_uart_o0", CK_TOP_UART_SEL, 1, 1),
-+	TOP_FACTOR(CK_INFRA_UART_O1, "infra_uart_o1", CK_TOP_UART_SEL, 1, 1),
-+	TOP_FACTOR(CK_INFRA_UART_O2, "infra_uart_o2", CK_TOP_UART_SEL, 1, 1),
-+	TOP_FACTOR(CK_INFRA_NFI_O, "infra_nfi_o", CK_TOP_NFI1X, 1, 1),
-+	TOP_FACTOR(CK_INFRA_SPINFI_O, "infra_spinfi_o", CK_TOP_SPINFI_BCK, 1,
-+		   1),
-+	TOP_FACTOR(CK_INFRA_SPI0_O, "infra_spi0_o", CK_TOP_SPI, 1, 1),
-+	TOP_FACTOR(CK_INFRA_SPI1_O, "infra_spi1_o", CK_TOP_SPIM_MST, 1, 1),
-+	INFRA_FACTOR(CK_INFRA_LB_MUX_FRTC, "infra_lb_mux_frtc", CK_INFRA_FRTC,
-+		     1, 1),
-+	TOP_FACTOR(CK_INFRA_FRTC, "infra_frtc", CK_TOP_CB_RTC_32K, 1, 1),
-+	TOP_FACTOR(CK_INFRA_FMSDC400_O, "infra_fmsdc400_o", CK_TOP_EMMC_400M, 1,
-+		   1),
-+	TOP_FACTOR(CK_INFRA_FMSDC2_HCK_OCC, "infra_fmsdc2_hck_occ",
-+		   CK_TOP_EMMC_250M, 1, 1),
-+	TOP_FACTOR(CK_INFRA_PERI_133M, "infra_peri_133m", CK_TOP_SYSAXI, 1, 1),
-+	TOP_FACTOR(CK_INFRA_USB_O, "infra_usb_o", CK_TOP_USB_REF, 1, 1),
-+	TOP_FACTOR(CK_INFRA_USB_O_P1, "infra_usb_o_p1", CK_TOP_USB_CK_P1, 1, 1),
-+	TOP_FACTOR(CK_INFRA_USB_FRMCNT_O, "infra_usb_frmcnt_o",
-+		   CK_TOP_USB_FRMCNT, 1, 1),
-+	TOP_FACTOR(CK_INFRA_USB_FRMCNT_O_P1, "infra_usb_frmcnt_o_p1",
-+		   CK_TOP_USB_FRMCNT_P1, 1, 1),
-+	TOP_FACTOR(CK_INFRA_USB_XHCI_O, "infra_usb_xhci_o", CK_TOP_USB_XHCI, 1,
-+		   1),
-+	TOP_FACTOR(CK_INFRA_USB_XHCI_O_P1, "infra_usb_xhci_o_p1",
-+		   CK_TOP_USB_XHCI_P1, 1, 1),
-+	XTAL_FACTOR(CK_INFRA_USB_PIPE_O, "infra_usb_pipe_o", CLK_XTAL, 1, 1),
-+	XTAL_FACTOR(CK_INFRA_USB_PIPE_O_P1, "infra_usb_pipe_o_p1", CLK_XTAL, 1,
-+		    1),
-+	XTAL_FACTOR(CK_INFRA_USB_UTMI_O, "infra_usb_utmi_o", CLK_XTAL, 1, 1),
-+	XTAL_FACTOR(CK_INFRA_USB_UTMI_O_P1, "infra_usb_utmi_o_p1", CLK_XTAL, 1,
-+		    1),
-+	XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P0, "infra_pcie_pipe_ck_occ_p0",
-+		    CLK_XTAL, 1, 1),
-+	XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P1, "infra_pcie_pipe_ck_occ_p1",
-+		    CLK_XTAL, 1, 1),
-+	XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P2, "infra_pcie_pipe_ck_occ_p2",
-+		    CLK_XTAL, 1, 1),
-+	XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P3, "infra_pcie_pipe_ck_occ_p3",
-+		    CLK_XTAL, 1, 1),
-+	TOP_FACTOR(CK_INFRA_F26M_O0, "infra_f26m_o0", CK_TOP_INFRA_F26M, 1, 1),
-+	TOP_FACTOR(CK_INFRA_F26M_O1, "infra_f26m_o1", CK_TOP_INFRA_F26M, 1, 1),
-+	TOP_FACTOR(CK_INFRA_133M_MCK, "infra_133m_mck", CK_TOP_SYSAXI, 1, 1),
-+	TOP_FACTOR(CK_INFRA_66M_MCK, "infra_66m_mck", CK_TOP_SYSAXI, 1, 1),
-+	TOP_FACTOR(CK_INFRA_PERI_66M_O, "infra_peri_66m_o", CK_TOP_SYSAXI, 1,
-+		   1),
-+	TOP_FACTOR(CK_INFRA_USB_SYS_O, "infra_usb_sys_o", CK_TOP_USB_SYS, 1, 1),
-+	TOP_FACTOR(CK_INFRA_USB_SYS_O_P1, "infra_usb_sys_o_p1",
-+		   CK_TOP_USB_SYS_P1, 1, 1),
-+};
-+
-+/* INFRASYS MUX PARENTS */
-+static const int infra_mux_uart0_parents[] = { CK_INFRA_CK_F26M,
-+					       CK_INFRA_UART_O0 };
-+
-+static const int infra_mux_uart1_parents[] = { CK_INFRA_CK_F26M,
-+					       CK_INFRA_UART_O1 };
-+
-+static const int infra_mux_uart2_parents[] = { CK_INFRA_CK_F26M,
-+					       CK_INFRA_UART_O2 };
-+
-+static const int infra_mux_spi0_parents[] = { CK_INFRA_I2C_O, CK_INFRA_SPI0_O };
-+
-+static const int infra_mux_spi1_parents[] = { CK_INFRA_I2C_O, CK_INFRA_SPI1_O };
-+
-+static const int infra_pwm_bck_parents[] = { CK_TOP_INFRA_F32K,
-+					     CK_INFRA_CK_F26M, CK_INFRA_66M_MCK,
-+					     CK_INFRA_PWM_O };
-+
-+static const int infra_pcie_gfmux_tl_ck_o_p0_parents[] = {
-+	CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M,
-+	CK_INFRA_PCIE_OCC_P0
-+};
-+
-+static const int infra_pcie_gfmux_tl_ck_o_p1_parents[] = {
-+	CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M,
-+	CK_INFRA_PCIE_OCC_P1
-+};
-+
-+static const int infra_pcie_gfmux_tl_ck_o_p2_parents[] = {
-+	CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M,
-+	CK_INFRA_PCIE_OCC_P2
-+};
-+
-+static const int infra_pcie_gfmux_tl_ck_o_p3_parents[] = {
-+	CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M,
-+	CK_INFRA_PCIE_OCC_P3
-+};
-+
-+#define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width)                  \
-+	{                                                                      \
-+		.id = _id, .mux_reg = _reg + 0x8, .mux_set_reg = _reg + 0x0,   \
-+		.mux_clr_reg = _reg + 0x4, .mux_shift = _shift,                \
-+		.mux_mask = BIT(_width) - 1, .parent = _parents,               \
-+		.num_parents = ARRAY_SIZE(_parents),                           \
-+		.flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_INFRASYS,             \
-+	}
-+
-+/* INFRA MUX */
-+static const struct mtk_composite infracfg_mtk_mux[] = {
-+	INFRA_MUX(CK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel",
-+		  infra_mux_uart0_parents, 0x10, 0, 1),
-+	INFRA_MUX(CK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel",
-+		  infra_mux_uart1_parents, 0x10, 1, 1),
-+	INFRA_MUX(CK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel",
-+		  infra_mux_uart2_parents, 0x10, 2, 1),
-+	INFRA_MUX(CK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel",
-+		  infra_mux_spi0_parents, 0x10, 4, 1),
-+	INFRA_MUX(CK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel",
-+		  infra_mux_spi1_parents, 0x10, 5, 1),
-+	INFRA_MUX(CK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel",
-+		  infra_mux_spi0_parents, 0x10, 6, 1),
-+	INFRA_MUX(CK_INFRA_PWM_SEL, "infra_pwm_sel", infra_pwm_bck_parents,
-+		  0x10, 14, 2),
-+	INFRA_MUX(CK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel",
-+		  infra_pwm_bck_parents, 0x10, 16, 2),
-+	INFRA_MUX(CK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel",
-+		  infra_pwm_bck_parents, 0x10, 18, 2),
-+	INFRA_MUX(CK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel",
-+		  infra_pwm_bck_parents, 0x10, 20, 2),
-+	INFRA_MUX(CK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel",
-+		  infra_pwm_bck_parents, 0x10, 22, 2),
-+	INFRA_MUX(CK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel",
-+		  infra_pwm_bck_parents, 0x10, 24, 2),
-+	INFRA_MUX(CK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel",
-+		  infra_pwm_bck_parents, 0x10, 26, 2),
-+	INFRA_MUX(CK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel",
-+		  infra_pwm_bck_parents, 0x10, 28, 2),
-+	INFRA_MUX(CK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel",
-+		  infra_pwm_bck_parents, 0x10, 30, 2),
-+	INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL,
-+		  "infra_pcie_gfmux_tl_o_p0_sel",
-+		  infra_pcie_gfmux_tl_ck_o_p0_parents, 0x20, 0, 2),
-+	INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL,
-+		  "infra_pcie_gfmux_tl_o_p1_sel",
-+		  infra_pcie_gfmux_tl_ck_o_p1_parents, 0x20, 2, 2),
-+	INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL,
-+		  "infra_pcie_gfmux_tl_o_p2_sel",
-+		  infra_pcie_gfmux_tl_ck_o_p2_parents, 0x20, 4, 2),
-+	INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL,
-+		  "infra_pcie_gfmux_tl_o_p3_sel",
-+		  infra_pcie_gfmux_tl_ck_o_p3_parents, 0x20, 6, 2),
-+};
-+
-+static const struct mtk_gate_regs infra_0_cg_regs = {
-+	.set_ofs = 0x10,
-+	.clr_ofs = 0x14,
-+	.sta_ofs = 0x18,
-+};
-+
-+static const struct mtk_gate_regs infra_1_cg_regs = {
-+	.set_ofs = 0x40,
-+	.clr_ofs = 0x44,
-+	.sta_ofs = 0x48,
-+};
-+
-+static const struct mtk_gate_regs infra_2_cg_regs = {
-+	.set_ofs = 0x50,
-+	.clr_ofs = 0x54,
-+	.sta_ofs = 0x58,
-+};
-+
-+static const struct mtk_gate_regs infra_3_cg_regs = {
-+	.set_ofs = 0x60,
-+	.clr_ofs = 0x64,
-+	.sta_ofs = 0x68,
-+};
-+
-+#define GATE_INFRA0(_id, _name, _parent, _shift)                               \
-+	{                                                                      \
-+		.id = _id, .parent = _parent, .regs = &infra_0_cg_regs,        \
-+		.shift = _shift,                                               \
-+		.flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS,                \
-+	}
-+
-+#define GATE_INFRA1(_id, _name, _parent, _shift)                               \
-+	{                                                                      \
-+		.id = _id, .parent = _parent, .regs = &infra_1_cg_regs,        \
-+		.shift = _shift,                                               \
-+		.flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS,                \
-+	}
-+
-+#define GATE_INFRA2(_id, _name, _parent, _shift)                               \
-+	{                                                                      \
-+		.id = _id, .parent = _parent, .regs = &infra_2_cg_regs,        \
-+		.shift = _shift,                                               \
-+		.flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS,                \
-+	}
-+
-+#define GATE_INFRA3(_id, _name, _parent, _shift)                               \
-+	{                                                                      \
-+		.id = _id, .parent = _parent, .regs = &infra_3_cg_regs,        \
-+		.shift = _shift,                                               \
-+		.flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS,                \
-+	}
-+
-+/* INFRA GATE */
-+static const struct mtk_gate infracfg_mtk_gates[] = {
-+	GATE_INFRA1(CK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck",
-+		    CK_INFRA_66M_MCK, 0),
-+	GATE_INFRA1(CK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck",
-+		    CK_INFRA_66M_MCK, 1),
-+	GATE_INFRA1(CK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck",
-+		    CK_INFRA_PWM_SEL, 2),
-+	GATE_INFRA1(CK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1",
-+		    CK_INFRA_PWM_CK1_SEL, 3),
-+	GATE_INFRA1(CK_INFRA_66M_PWM_CK2, "infra_hf_66m_pwm_ck2",
-+		    CK_INFRA_PWM_CK2_SEL, 4),
-+	GATE_INFRA1(CK_INFRA_66M_PWM_CK3, "infra_hf_66m_pwm_ck3",
-+		    CK_INFRA_PWM_CK3_SEL, 5),
-+	GATE_INFRA1(CK_INFRA_66M_PWM_CK4, "infra_hf_66m_pwm_ck4",
-+		    CK_INFRA_PWM_CK4_SEL, 6),
-+	GATE_INFRA1(CK_INFRA_66M_PWM_CK5, "infra_hf_66m_pwm_ck5",
-+		    CK_INFRA_PWM_CK5_SEL, 7),
-+	GATE_INFRA1(CK_INFRA_66M_PWM_CK6, "infra_hf_66m_pwm_ck6",
-+		    CK_INFRA_PWM_CK6_SEL, 8),
-+	GATE_INFRA1(CK_INFRA_66M_PWM_CK7, "infra_hf_66m_pwm_ck7",
-+		    CK_INFRA_PWM_CK7_SEL, 9),
-+	GATE_INFRA1(CK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8",
-+		    CK_INFRA_PWM_CK8_SEL, 10),
-+	GATE_INFRA1(CK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck",
-+		    CK_INFRA_133M_MCK, 12),
-+	GATE_INFRA1(CK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck",
-+		    CK_INFRA_66M_PHCK, 13),
-+	GATE_INFRA1(CK_INFRA_AUD_26M, "infra_f_faud_26m", CK_INFRA_CK_F26M, 14),
-+	GATE_INFRA1(CK_INFRA_AUD_L, "infra_f_faud_l", CK_INFRA_FAUD_L_O, 15),
-+	GATE_INFRA1(CK_INFRA_AUD_AUD, "infra_f_aud_aud", CK_INFRA_FAUD_AUD_O,
-+		    16),
-+	GATE_INFRA1(CK_INFRA_AUD_EG2, "infra_f_faud_eg2", CK_INFRA_FAUD_EG2_O,
-+		    18),
-+	GATE_INFRA1(CK_INFRA_DRAMC_F26M, "infra_dramc_f26m", CK_INFRA_CK_F26M,
-+		    19),
-+	GATE_INFRA1(CK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm",
-+		    CK_INFRA_133M_MCK, 20),
-+	GATE_INFRA1(CK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck",
-+		    CK_INFRA_66M_MCK, 21),
-+	GATE_INFRA1(CK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck",
-+		    CK_INFRA_66M_MCK, 29),
-+	GATE_INFRA1(CK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m",
-+		    CK_INFRA_CK_F26M, 30),
-+	GATE_INFRA1(CK_INFRA_66M_TRNG, "infra_hf_66m_trng", CK_INFRA_PERI_66M_O,
-+		    31),
-+	GATE_INFRA2(CK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system",
-+		    CK_INFRA_CK_F26M, 0),
-+	GATE_INFRA2(CK_INFRA_I2C_BCK, "infra_i2c_bck", CK_INFRA_I2C_O, 1),
-+	GATE_INFRA2(CK_INFRA_66M_UART0_PCK, "infra_hf_66m_uart0_pck",
-+		    CK_INFRA_66M_MCK, 3),
-+	GATE_INFRA2(CK_INFRA_66M_UART1_PCK, "infra_hf_66m_uart1_pck",
-+		    CK_INFRA_66M_MCK, 4),
-+	GATE_INFRA2(CK_INFRA_66M_UART2_PCK, "infra_hf_66m_uart2_pck",
-+		    CK_INFRA_66M_MCK, 5),
-+	GATE_INFRA2(CK_INFRA_52M_UART0_CK, "infra_f_52m_uart0",
-+		    CK_INFRA_MUX_UART0_SEL, 3),
-+	GATE_INFRA2(CK_INFRA_52M_UART1_CK, "infra_f_52m_uart1",
-+		    CK_INFRA_MUX_UART1_SEL, 4),
-+	GATE_INFRA2(CK_INFRA_52M_UART2_CK, "infra_f_52m_uart2",
-+		    CK_INFRA_MUX_UART2_SEL, 5),
-+	GATE_INFRA2(CK_INFRA_NFI, "infra_f_fnfi", CK_INFRA_NFI_O, 9),
-+	GATE_INFRA2(CK_INFRA_SPINFI, "infra_f_fspinfi", CK_INFRA_SPINFI_O, 10),
-+	GATE_INFRA2(CK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck",
-+		    CK_INFRA_66M_MCK, 11),
-+	GATE_INFRA2(CK_INFRA_104M_SPI0, "infra_hf_104m_spi0",
-+		    CK_INFRA_MUX_SPI0_SEL, 12),
-+	GATE_INFRA2(CK_INFRA_104M_SPI1, "infra_hf_104m_spi1",
-+		    CK_INFRA_MUX_SPI1_SEL, 13),
-+	GATE_INFRA2(CK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck",
-+		    CK_INFRA_MUX_SPI2_SEL, 14),
-+	GATE_INFRA2(CK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck",
-+		    CK_INFRA_66M_MCK, 15),
-+	GATE_INFRA2(CK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck",
-+		    CK_INFRA_66M_MCK, 16),
-+	GATE_INFRA2(CK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck",
-+		    CK_INFRA_66M_MCK, 17),
-+	GATE_INFRA2(CK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi",
-+		    CK_INFRA_66M_MCK, 18),
-+	GATE_INFRA2(CK_INFRA_RTC, "infra_f_frtc", CK_INFRA_LB_MUX_FRTC, 19),
-+	GATE_INFRA2(CK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck",
-+		    CK_INFRA_F26M_O1, 20),
-+	GATE_INFRA2(CK_INFRA_RC_ADC, "infra_f_frc_adc", CK_INFRA_26M_ADC_BCK,
-+		    21),
-+	GATE_INFRA2(CK_INFRA_MSDC400, "infra_f_fmsdc400", CK_INFRA_FMSDC400_O,
-+		    22),
-+	GATE_INFRA2(CK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck",
-+		    CK_INFRA_FMSDC2_HCK_OCC, 23),
-+	GATE_INFRA2(CK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck",
-+		    CK_INFRA_PERI_133M, 24),
-+	GATE_INFRA2(CK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck",
-+		    CK_INFRA_66M_PHCK, 25),
-+	GATE_INFRA2(CK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck",
-+		    CK_INFRA_133M_MCK, 26),
-+	GATE_INFRA2(CK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", CK_INFRA_NFI_O,
-+		    27),
-+	GATE_INFRA2(CK_INFRA_I2C_X16W_MCK_CK_P1, "infra_hf_i2c_x16w_mck_ck_p1",
-+		    CK_INFRA_133M_MCK, 29),
-+	GATE_INFRA2(CK_INFRA_I2C_X16W_PCK_CK_P1, "infra_hf_i2c_x16w_pck_ck_p1",
-+		    CK_INFRA_66M_PHCK, 31),
-+	GATE_INFRA3(CK_INFRA_133M_USB_HCK, "infra_133m_usb_hck",
-+		    CK_INFRA_133M_PHCK, 0),
-+	GATE_INFRA3(CK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1",
-+		    CK_INFRA_133M_PHCK, 1),
-+	GATE_INFRA3(CK_INFRA_66M_USB_HCK, "infra_66m_usb_hck",
-+		    CK_INFRA_66M_PHCK, 2),
-+	GATE_INFRA3(CK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1",
-+		    CK_INFRA_66M_PHCK, 3),
-+	GATE_INFRA3(CK_INFRA_USB_SYS, "infra_usb_sys", CK_INFRA_USB_SYS_O, 4),
-+	GATE_INFRA3(CK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1",
-+		    CK_INFRA_USB_SYS_O_P1, 5),
-+	GATE_INFRA3(CK_INFRA_USB_REF, "infra_usb_ref", CK_INFRA_USB_O, 6),
-+	GATE_INFRA3(CK_INFRA_USB_CK_P1, "infra_usb_ck_p1", CK_INFRA_USB_O_P1,
-+		    7),
-+	GATE_INFRA3(CK_INFRA_USB_FRMCNT, "infra_usb_frmcnt",
-+		    CK_INFRA_USB_FRMCNT_O, 8),
-+	GATE_INFRA3(CK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1",
-+		    CK_INFRA_USB_FRMCNT_O_P1, 9),
-+	GATE_INFRA3(CK_INFRA_USB_PIPE, "infra_usb_pipe", CK_INFRA_USB_PIPE_O,
-+		    10),
-+	GATE_INFRA3(CK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1",
-+		    CK_INFRA_USB_PIPE_O_P1, 11),
-+	GATE_INFRA3(CK_INFRA_USB_UTMI, "infra_usb_utmi", CK_INFRA_USB_UTMI_O,
-+		    12),
-+	GATE_INFRA3(CK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1",
-+		    CK_INFRA_USB_UTMI_O_P1, 13),
-+	GATE_INFRA3(CK_INFRA_USB_XHCI, "infra_usb_xhci", CK_INFRA_USB_XHCI_O,
-+		    14),
-+	GATE_INFRA3(CK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1",
-+		    CK_INFRA_USB_XHCI_O_P1, 15),
-+	GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0",
-+		    CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, 20),
-+	GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1",
-+		    CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, 21),
-+	GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P2, "infra_pcie_gfmux_tl_ck_p2",
-+		    CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, 22),
-+	GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3",
-+		    CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, 23),
-+	GATE_INFRA3(CK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0",
-+		    CK_INFRA_PCIE_PIPE_OCC_P0, 24),
-+	GATE_INFRA3(CK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1",
-+		    CK_INFRA_PCIE_PIPE_OCC_P1, 25),
-+	GATE_INFRA3(CK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2",
-+		    CK_INFRA_PCIE_PIPE_OCC_P2, 26),
-+	GATE_INFRA3(CK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3",
-+		    CK_INFRA_PCIE_PIPE_OCC_P3, 27),
-+	GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0",
-+		    CK_INFRA_133M_PHCK, 28),
-+	GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1",
-+		    CK_INFRA_133M_PHCK, 29),
-+	GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2",
-+		    CK_INFRA_133M_PHCK, 30),
-+	GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3",
-+		    CK_INFRA_133M_PHCK, 31),
-+	GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P0,
-+		    "infra_pcie_peri_ck_26m_ck_p0", CK_INFRA_F26M_O0, 7),
-+	GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P1,
-+		    "infra_pcie_peri_ck_26m_ck_p1", CK_INFRA_F26M_O0, 8),
-+	GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P2,
-+		    "infra_pcie_peri_ck_26m_ck_p2", CK_INFRA_F26M_O0, 9),
-+	GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P3,
-+		    "infra_pcie_peri_ck_26m_ck_p3", CK_INFRA_F26M_O0, 10),
-+};
-+
-+static const struct mtk_clk_tree mt7988_fixed_pll_clk_tree = {
-+	.fdivs_offs = ARRAY_SIZE(apmixedsys_mtk_plls),
-+	.fclks = apmixedsys_mtk_plls,
-+	.xtal_rate = 40 * MHZ,
-+};
-+
-+static const struct mtk_clk_tree mt7988_topckgen_clk_tree = {
-+	.fdivs_offs = CK_TOP_CB_CKSQ_40M,
-+	.muxes_offs = CK_TOP_NETSYS_SEL,
-+	.fdivs = topckgen_mtk_fixed_factors,
-+	.muxes = topckgen_mtk_muxes,
-+	.flags = CLK_BYPASS_XTAL,
-+	.xtal_rate = 40 * MHZ,
-+};
-+
-+static const struct mtk_clk_tree mt7988_infracfg_clk_tree = {
-+	.fdivs_offs = CK_INFRA_CK_F26M,
-+	.muxes_offs = CK_INFRA_MUX_UART0_SEL,
-+	.fdivs = infracfg_mtk_fixed_factor,
-+	.muxes = infracfg_mtk_mux,
-+	.flags = CLK_BYPASS_XTAL,
-+	.xtal_rate = 40 * MHZ,
-+};
-+
-+static const struct udevice_id mt7988_fixed_pll_compat[] = {
-+	{ .compatible = "mediatek,mt7988-fixed-plls" },
-+	{}
-+};
-+
-+static const struct udevice_id mt7988_topckgen_compat[] = {
-+	{ .compatible = "mediatek,mt7988-topckgen" },
-+	{}
-+};
-+
-+static int mt7988_fixed_pll_probe(struct udevice *dev)
-+{
-+	return mtk_common_clk_init(dev, &mt7988_fixed_pll_clk_tree);
-+}
-+
-+static int mt7988_topckgen_probe(struct udevice *dev)
-+{
-+	struct mtk_clk_priv *priv = dev_get_priv(dev);
-+
-+	priv->base = dev_read_addr_ptr(dev);
-+	if (!priv->base)
-+		return -ENOENT;
-+
-+	writel(MT7988_CLK_PDN_EN_WRITE, priv->base + MT7988_CLK_PDN);
-+	return mtk_common_clk_init(dev, &mt7988_topckgen_clk_tree);
-+}
-+
-+U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
-+	.name = "mt7988-clock-fixed-pll",
-+	.id = UCLASS_CLK,
-+	.of_match = mt7988_fixed_pll_compat,
-+	.probe = mt7988_fixed_pll_probe,
-+	.priv_auto = sizeof(struct mtk_clk_priv),
-+	.ops = &mtk_clk_topckgen_ops,
-+	.flags = DM_FLAG_PRE_RELOC,
-+};
-+
-+U_BOOT_DRIVER(mtk_clk_topckgen) = {
-+	.name = "mt7988-clock-topckgen",
-+	.id = UCLASS_CLK,
-+	.of_match = mt7988_topckgen_compat,
-+	.probe = mt7988_topckgen_probe,
-+	.priv_auto = sizeof(struct mtk_clk_priv),
-+	.ops = &mtk_clk_topckgen_ops,
-+	.flags = DM_FLAG_PRE_RELOC,
-+};
-+
-+static const struct udevice_id mt7988_infracfg_compat[] = {
-+	{ .compatible = "mediatek,mt7988-infracfg" },
-+	{}
-+};
-+
-+static const struct udevice_id mt7988_infracfg_ao_cgs_compat[] = {
-+	{ .compatible = "mediatek,mt7988-infracfg_ao_cgs" },
-+	{}
-+};
-+
-+static int mt7988_infracfg_probe(struct udevice *dev)
-+{
-+	return mtk_common_clk_init(dev, &mt7988_infracfg_clk_tree);
-+}
-+
-+static int mt7988_infracfg_ao_cgs_probe(struct udevice *dev)
-+{
-+	return mtk_common_clk_gate_init(dev, &mt7988_infracfg_clk_tree,
-+					infracfg_mtk_gates);
-+}
-+
-+U_BOOT_DRIVER(mtk_clk_infracfg) = {
-+	.name = "mt7988-clock-infracfg",
-+	.id = UCLASS_CLK,
-+	.of_match = mt7988_infracfg_compat,
-+	.probe = mt7988_infracfg_probe,
-+	.priv_auto = sizeof(struct mtk_clk_priv),
-+	.ops = &mtk_clk_infrasys_ops,
-+	.flags = DM_FLAG_PRE_RELOC,
-+};
-+
-+U_BOOT_DRIVER(mtk_clk_infracfg_ao_cgs) = {
-+	.name = "mt7988-clock-infracfg_ao_cgs",
-+	.id = UCLASS_CLK,
-+	.of_match = mt7988_infracfg_ao_cgs_compat,
-+	.probe = mt7988_infracfg_ao_cgs_probe,
-+	.priv_auto = sizeof(struct mtk_cg_priv),
-+	.ops = &mtk_clk_gate_ops,
-+	.flags = DM_FLAG_PRE_RELOC,
-+};
-+
-+/* ETHDMA */
-+
-+static const struct mtk_gate_regs ethdma_cg_regs = {
-+	.set_ofs = 0x30,
-+	.clr_ofs = 0x30,
-+	.sta_ofs = 0x30,
-+};
-+
-+#define GATE_ETHDMA(_id, _name, _parent, _shift)                               \
-+	{                                                                      \
-+		.id = _id, .parent = _parent, .regs = &ethdma_cg_regs,         \
-+		.shift = _shift,                                               \
-+		.flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN,         \
-+	}
-+
-+static const struct mtk_gate ethdma_mtk_gate[] = {
-+	GATE_ETHDMA(CK_ETHDMA_FE_EN, "ethdma_fe_en", CK_TOP_NETSYS_2X, 6),
-+};
-+
-+static int mt7988_ethdma_probe(struct udevice *dev)
-+{
-+	return mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree,
-+					ethdma_mtk_gate);
-+}
-+
-+static int mt7988_ethdma_bind(struct udevice *dev)
-+{
-+	int ret = 0;
-+
-+	if (CONFIG_IS_ENABLED(RESET_MEDIATEK)) {
-+		ret = mediatek_reset_bind(dev, MT7988_ETHDMA_RST_CTRL_OFS, 1);
-+		if (ret)
-+			debug("Warning: failed to bind reset controller\n");
-+	}
-+
-+	return ret;
-+}
-+
-+static const struct udevice_id mt7988_ethdma_compat[] = {
-+	{
-+		.compatible = "mediatek,mt7988-ethdma",
-+	},
-+	{}
-+};
-+
-+U_BOOT_DRIVER(mtk_clk_ethdma) = {
-+	.name = "mt7988-clock-ethdma",
-+	.id = UCLASS_CLK,
-+	.of_match = mt7988_ethdma_compat,
-+	.probe = mt7988_ethdma_probe,
-+	.bind = mt7988_ethdma_bind,
-+	.priv_auto = sizeof(struct mtk_cg_priv),
-+	.ops = &mtk_clk_gate_ops,
-+};
-+
-+/* SGMIISYS_0 */
-+
-+static const struct mtk_gate_regs sgmii0_cg_regs = {
-+	.set_ofs = 0xE4,
-+	.clr_ofs = 0xE4,
-+	.sta_ofs = 0xE4,
-+};
-+
-+#define GATE_SGMII0(_id, _name, _parent, _shift)                               \
-+	{                                                                      \
-+		.id = _id, .parent = _parent, .regs = &sgmii0_cg_regs,         \
-+		.shift = _shift,                                               \
-+		.flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN,         \
-+	}
-+
-+static const struct mtk_gate sgmiisys_0_mtk_gate[] = {
-+	/* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */
-+	GATE_SGMII0(CK_SGM0_TX_EN, "sgm0_tx_en", CK_TOP_CB_CKSQ_40M, 2),
-+	/* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */
-+	GATE_SGMII0(CK_SGM0_RX_EN, "sgm0_rx_en", CK_TOP_CB_CKSQ_40M, 3),
-+};
-+
-+static int mt7988_sgmiisys_0_probe(struct udevice *dev)
-+{
-+	return mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree,
-+					sgmiisys_0_mtk_gate);
-+}
-+
-+static const struct udevice_id mt7988_sgmiisys_0_compat[] = {
-+	{
-+		.compatible = "mediatek,mt7988-sgmiisys_0",
-+	},
-+	{}
-+};
-+
-+U_BOOT_DRIVER(mtk_clk_sgmiisys_0) = {
-+	.name = "mt7988-clock-sgmiisys_0",
-+	.id = UCLASS_CLK,
-+	.of_match = mt7988_sgmiisys_0_compat,
-+	.probe = mt7988_sgmiisys_0_probe,
-+	.priv_auto = sizeof(struct mtk_cg_priv),
-+	.ops = &mtk_clk_gate_ops,
-+};
-+
-+/* SGMIISYS_1 */
-+
-+static const struct mtk_gate_regs sgmii1_cg_regs = {
-+	.set_ofs = 0xE4,
-+	.clr_ofs = 0xE4,
-+	.sta_ofs = 0xE4,
-+};
-+
-+#define GATE_SGMII1(_id, _name, _parent, _shift)                               \
-+	{                                                                      \
-+		.id = _id, .parent = _parent, .regs = &sgmii1_cg_regs,         \
-+		.shift = _shift,                                               \
-+		.flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN,         \
-+	}
-+
-+static const struct mtk_gate sgmiisys_1_mtk_gate[] = {
-+	/* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */
-+	GATE_SGMII1(CK_SGM1_TX_EN, "sgm1_tx_en", CK_TOP_CB_CKSQ_40M, 2),
-+	/* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */
-+	GATE_SGMII1(CK_SGM1_RX_EN, "sgm1_rx_en", CK_TOP_CB_CKSQ_40M, 3),
-+};
-+
-+static int mt7988_sgmiisys_1_probe(struct udevice *dev)
-+{
-+	return mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree,
-+					sgmiisys_1_mtk_gate);
-+}
-+
-+static const struct udevice_id mt7988_sgmiisys_1_compat[] = {
-+	{
-+		.compatible = "mediatek,mt7988-sgmiisys_1",
-+	},
-+	{}
-+};
-+
-+U_BOOT_DRIVER(mtk_clk_sgmiisys_1) = {
-+	.name = "mt7988-clock-sgmiisys_1",
-+	.id = UCLASS_CLK,
-+	.of_match = mt7988_sgmiisys_1_compat,
-+	.probe = mt7988_sgmiisys_1_probe,
-+	.priv_auto = sizeof(struct mtk_cg_priv),
-+	.ops = &mtk_clk_gate_ops,
-+};
-+
-+/* ETHWARP */
-+
-+static const struct mtk_gate_regs ethwarp_cg_regs = {
-+	.set_ofs = 0x14,
-+	.clr_ofs = 0x14,
-+	.sta_ofs = 0x14,
-+};
-+
-+#define GATE_ETHWARP(_id, _name, _parent, _shift)                              \
-+	{                                                                      \
-+		.id = _id, .parent = _parent, .regs = &ethwarp_cg_regs,        \
-+		.shift = _shift,                                               \
-+		.flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN,         \
-+	}
-+
-+static const struct mtk_gate ethwarp_mtk_gate[] = {
-+	GATE_ETHWARP(CK_ETHWARP_WOCPU2_EN, "ethwarp_wocpu2_en",
-+		     CK_TOP_NETSYS_WED_MCU, 13),
-+	GATE_ETHWARP(CK_ETHWARP_WOCPU1_EN, "ethwarp_wocpu1_en",
-+		     CK_TOP_NETSYS_WED_MCU, 14),
-+	GATE_ETHWARP(CK_ETHWARP_WOCPU0_EN, "ethwarp_wocpu0_en",
-+		     CK_TOP_NETSYS_WED_MCU, 15),
-+};
-+
-+static int mt7988_ethwarp_probe(struct udevice *dev)
-+{
-+	return mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree,
-+					ethwarp_mtk_gate);
-+}
-+
-+static int mt7988_ethwarp_bind(struct udevice *dev)
-+{
-+	int ret = 0;
-+
-+	if (CONFIG_IS_ENABLED(RESET_MEDIATEK)) {
-+		ret = mediatek_reset_bind(dev, MT7988_ETHWARP_RST_CTRL_OFS, 2);
-+		if (ret)
-+			debug("Warning: failed to bind reset controller\n");
-+	}
-+
-+	return ret;
-+}
-+
-+static const struct udevice_id mt7988_ethwarp_compat[] = {
-+	{
-+		.compatible = "mediatek,mt7988-ethwarp",
-+	},
-+	{}
-+};
-+
-+U_BOOT_DRIVER(mtk_clk_ethwarp) = {
-+	.name = "mt7988-clock-ethwarp",
-+	.id = UCLASS_CLK,
-+	.of_match = mt7988_ethwarp_compat,
-+	.probe = mt7988_ethwarp_probe,
-+	.bind = mt7988_ethwarp_bind,
-+	.priv_auto = sizeof(struct mtk_cg_priv),
-+	.ops = &mtk_clk_gate_ops,
-+};
---- /dev/null
-+++ b/include/dt-bindings/clock/mt7988-clk.h
-@@ -0,0 +1,349 @@
-+/* SPDX-License-Identifier: GPL-2.0 */
-+/*
-+ * Copyright (C) 2022 MediaTek Inc. All rights reserved.
-+ *
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ */
-+
-+#ifndef _DT_BINDINGS_CLK_MT7988_H
-+#define _DT_BINDINGS_CLK_MT7988_H
-+
-+/* INFRACFG */
-+/* mtk_fixed_factor */
-+#define CK_INFRA_CK_F26M	  0
-+#define CK_INFRA_PWM_O		  1
-+#define CK_INFRA_PCIE_OCC_P0	  2
-+#define CK_INFRA_PCIE_OCC_P1	  3
-+#define CK_INFRA_PCIE_OCC_P2	  4
-+#define CK_INFRA_PCIE_OCC_P3	  5
-+#define CK_INFRA_133M_HCK	  6
-+#define CK_INFRA_133M_PHCK	  7
-+#define CK_INFRA_66M_PHCK	  8
-+#define CK_INFRA_FAUD_L_O	  9
-+#define CK_INFRA_FAUD_AUD_O	  10
-+#define CK_INFRA_FAUD_EG2_O	  11
-+#define CK_INFRA_I2C_O		  12
-+#define CK_INFRA_UART_O0	  13
-+#define CK_INFRA_UART_O1	  14
-+#define CK_INFRA_UART_O2	  15
-+#define CK_INFRA_NFI_O		  16
-+#define CK_INFRA_SPINFI_O	  17
-+#define CK_INFRA_SPI0_O		  18
-+#define CK_INFRA_SPI1_O		  19
-+#define CK_INFRA_LB_MUX_FRTC	  20
-+#define CK_INFRA_FRTC		  21
-+#define CK_INFRA_FMSDC400_O	  22
-+#define CK_INFRA_FMSDC2_HCK_OCC	  23
-+#define CK_INFRA_PERI_133M	  24
-+#define CK_INFRA_USB_O		  25
-+#define CK_INFRA_USB_O_P1	  26
-+#define CK_INFRA_USB_FRMCNT_O	  27
-+#define CK_INFRA_USB_FRMCNT_O_P1  28
-+#define CK_INFRA_USB_XHCI_O	  29
-+#define CK_INFRA_USB_XHCI_O_P1	  30
-+#define CK_INFRA_USB_PIPE_O	  31
-+#define CK_INFRA_USB_PIPE_O_P1	  32
-+#define CK_INFRA_USB_UTMI_O	  33
-+#define CK_INFRA_USB_UTMI_O_P1	  34
-+#define CK_INFRA_PCIE_PIPE_OCC_P0 35
-+#define CK_INFRA_PCIE_PIPE_OCC_P1 36
-+#define CK_INFRA_PCIE_PIPE_OCC_P2 37
-+#define CK_INFRA_PCIE_PIPE_OCC_P3 38
-+#define CK_INFRA_F26M_O0	  39
-+#define CK_INFRA_F26M_O1	  40
-+#define CK_INFRA_133M_MCK	  41
-+#define CK_INFRA_66M_MCK	  42
-+#define CK_INFRA_PERI_66M_O	  43
-+#define CK_INFRA_USB_SYS_O	  44
-+#define CK_INFRA_USB_SYS_O_P1	  45
-+
-+/* INFRACFG_AO */
-+#define GATE_OFFSET 65
-+/* mtk_mux */
-+#define CK_INFRA_MUX_UART0_SEL		46 /* Linux CLK ID (0) */
-+#define CK_INFRA_MUX_UART1_SEL		47 /* Linux CLK ID (1) */
-+#define CK_INFRA_MUX_UART2_SEL		48 /* Linux CLK ID (2) */
-+#define CK_INFRA_MUX_SPI0_SEL		49 /* Linux CLK ID (3) */
-+#define CK_INFRA_MUX_SPI1_SEL		50 /* Linux CLK ID (4) */
-+#define CK_INFRA_MUX_SPI2_SEL		51 /* Linux CLK ID (5) */
-+#define CK_INFRA_PWM_SEL		52 /* Linux CLK ID (6) */
-+#define CK_INFRA_PWM_CK1_SEL		53 /* Linux CLK ID (7) */
-+#define CK_INFRA_PWM_CK2_SEL		54 /* Linux CLK ID (8) */
-+#define CK_INFRA_PWM_CK3_SEL		55 /* Linux CLK ID (9) */
-+#define CK_INFRA_PWM_CK4_SEL		56 /* Linux CLK ID (10) */
-+#define CK_INFRA_PWM_CK5_SEL		57 /* Linux CLK ID (11) */
-+#define CK_INFRA_PWM_CK6_SEL		58 /* Linux CLK ID (12) */
-+#define CK_INFRA_PWM_CK7_SEL		59 /* Linux CLK ID (13) */
-+#define CK_INFRA_PWM_CK8_SEL		60 /* Linux CLK ID (14) */
-+#define CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 61 /* Linux CLK ID (15) */
-+#define CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 62 /* Linux CLK ID (16) */
-+#define CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 63 /* Linux CLK ID (17) */
-+#define CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 64 /* Linux CLK ID (18) */
-+/* mtk_gate */
-+#define CK_INFRA_66M_GPT_BCK	     (65 - GATE_OFFSET) /* Linux CLK ID (19) */
-+#define CK_INFRA_66M_PWM_HCK	     (66 - GATE_OFFSET) /* Linux CLK ID (20) */
-+#define CK_INFRA_66M_PWM_BCK	     (67 - GATE_OFFSET) /* Linux CLK ID (21) */
-+#define CK_INFRA_66M_PWM_CK1	     (68 - GATE_OFFSET) /* Linux CLK ID (22) */
-+#define CK_INFRA_66M_PWM_CK2	     (69 - GATE_OFFSET) /* Linux CLK ID (23) */
-+#define CK_INFRA_66M_PWM_CK3	     (70 - GATE_OFFSET) /* Linux CLK ID (24) */
-+#define CK_INFRA_66M_PWM_CK4	     (71 - GATE_OFFSET) /* Linux CLK ID (25) */
-+#define CK_INFRA_66M_PWM_CK5	     (72 - GATE_OFFSET) /* Linux CLK ID (26) */
-+#define CK_INFRA_66M_PWM_CK6	     (73 - GATE_OFFSET) /* Linux CLK ID (27) */
-+#define CK_INFRA_66M_PWM_CK7	     (74 - GATE_OFFSET) /* Linux CLK ID (28) */
-+#define CK_INFRA_66M_PWM_CK8	     (75 - GATE_OFFSET) /* Linux CLK ID (29) */
-+#define CK_INFRA_133M_CQDMA_BCK	     (76 - GATE_OFFSET) /* Linux CLK ID (30) */
-+#define CK_INFRA_66M_AUD_SLV_BCK     (77 - GATE_OFFSET) /* Linux CLK ID (31) */
-+#define CK_INFRA_AUD_26M	     (78 - GATE_OFFSET) /* Linux CLK ID (32) */
-+#define CK_INFRA_AUD_L		     (79 - GATE_OFFSET) /* Linux CLK ID (33) */
-+#define CK_INFRA_AUD_AUD	     (80 - GATE_OFFSET) /* Linux CLK ID (34) */
-+#define CK_INFRA_AUD_EG2	     (81 - GATE_OFFSET) /* Linux CLK ID (35) */
-+#define CK_INFRA_DRAMC_F26M	     (82 - GATE_OFFSET) /* Linux CLK ID (36) */
-+#define CK_INFRA_133M_DBG_ACKM	     (83 - GATE_OFFSET) /* Linux CLK ID (37) */
-+#define CK_INFRA_66M_AP_DMA_BCK	     (84 - GATE_OFFSET) /* Linux CLK ID (38) */
-+#define CK_INFRA_66M_SEJ_BCK	     (85 - GATE_OFFSET) /* Linux CLK ID (39) */
-+#define CK_INFRA_PRE_CK_SEJ_F13M     (86 - GATE_OFFSET) /* Linux CLK ID (40) */
-+#define CK_INFRA_66M_TRNG	     (87 - GATE_OFFSET) /* Linux CLK ID (41) */
-+#define CK_INFRA_26M_THERM_SYSTEM    (88 - GATE_OFFSET) /* Linux CLK ID (42) */
-+#define CK_INFRA_I2C_BCK	     (89 - GATE_OFFSET) /* Linux CLK ID (43) */
-+#define CK_INFRA_66M_UART0_PCK	     (90 - GATE_OFFSET) /* Linux CLK ID (44) */
-+#define CK_INFRA_66M_UART1_PCK	     (91 - GATE_OFFSET) /* Linux CLK ID (45) */
-+#define CK_INFRA_66M_UART2_PCK	     (92 - GATE_OFFSET) /* Linux CLK ID (46) */
-+#define CK_INFRA_52M_UART0_CK	     (93 - GATE_OFFSET) /* Linux CLK ID (47) */
-+#define CK_INFRA_52M_UART1_CK	     (94 - GATE_OFFSET) /* Linux CLK ID (48) */
-+#define CK_INFRA_52M_UART2_CK	     (95 - GATE_OFFSET) /* Linux CLK ID (49) */
-+#define CK_INFRA_NFI		     (96 - GATE_OFFSET) /* Linux CLK ID (50) */
-+#define CK_INFRA_SPINFI		     (97 - GATE_OFFSET) /* Linux CLK ID (51) */
-+#define CK_INFRA_66M_NFI_HCK	     (98 - GATE_OFFSET) /* Linux CLK ID (52) */
-+#define CK_INFRA_104M_SPI0	     (99 - GATE_OFFSET) /* Linux CLK ID (53) */
-+#define CK_INFRA_104M_SPI1	     (100 - GATE_OFFSET) /* Linux CLK ID (54) */
-+#define CK_INFRA_104M_SPI2_BCK	     (101 - GATE_OFFSET) /* Linux CLK ID (55) */
-+#define CK_INFRA_66M_SPI0_HCK	     (102 - GATE_OFFSET) /* Linux CLK ID (56) */
-+#define CK_INFRA_66M_SPI1_HCK	     (103 - GATE_OFFSET) /* Linux CLK ID (57) */
-+#define CK_INFRA_66M_SPI2_HCK	     (104 - GATE_OFFSET) /* Linux CLK ID (58) */
-+#define CK_INFRA_66M_FLASHIF_AXI     (105 - GATE_OFFSET) /* Linux CLK ID (59) */
-+#define CK_INFRA_RTC		     (106 - GATE_OFFSET) /* Linux CLK ID (60) */
-+#define CK_INFRA_26M_ADC_BCK	     (107 - GATE_OFFSET) /* Linux CLK ID (61) */
-+#define CK_INFRA_RC_ADC		     (108 - GATE_OFFSET) /* Linux CLK ID (62) */
-+#define CK_INFRA_MSDC400	     (109 - GATE_OFFSET) /* Linux CLK ID (63) */
-+#define CK_INFRA_MSDC2_HCK	     (110 - GATE_OFFSET) /* Linux CLK ID (64) */
-+#define CK_INFRA_133M_MSDC_0_HCK     (111 - GATE_OFFSET) /* Linux CLK ID (65) */
-+#define CK_INFRA_66M_MSDC_0_HCK	     (112 - GATE_OFFSET) /* Linux CLK ID (66) */
-+#define CK_INFRA_133M_CPUM_BCK	     (113 - GATE_OFFSET) /* Linux CLK ID (67) */
-+#define CK_INFRA_BIST2FPC	     (114 - GATE_OFFSET) /* Linux CLK ID (68) */
-+#define CK_INFRA_I2C_X16W_MCK_CK_P1  (115 - GATE_OFFSET) /* Linux CLK ID (69) */
-+#define CK_INFRA_I2C_X16W_PCK_CK_P1  (116 - GATE_OFFSET) /* Linux CLK ID (70) */
-+#define CK_INFRA_133M_USB_HCK	     (117 - GATE_OFFSET) /* Linux CLK ID (71) */
-+#define CK_INFRA_133M_USB_HCK_CK_P1  (118 - GATE_OFFSET) /* Linux CLK ID (72) */
-+#define CK_INFRA_66M_USB_HCK	     (119 - GATE_OFFSET) /* Linux CLK ID (73) */
-+#define CK_INFRA_66M_USB_HCK_CK_P1   (120 - GATE_OFFSET) /* Linux CLK ID (74) */
-+#define CK_INFRA_USB_SYS	     (121 - GATE_OFFSET) /* Linux CLK ID (75) */
-+#define CK_INFRA_USB_SYS_CK_P1	     (122 - GATE_OFFSET) /* Linux CLK ID (76) */
-+#define CK_INFRA_USB_REF	     (123 - GATE_OFFSET) /* Linux CLK ID (77) */
-+#define CK_INFRA_USB_CK_P1	     (124 - GATE_OFFSET) /* Linux CLK ID (78) */
-+#define CK_INFRA_USB_FRMCNT	     (125 - GATE_OFFSET) /* Linux CLK ID (79) */
-+#define CK_INFRA_USB_FRMCNT_CK_P1    (126 - GATE_OFFSET) /* Linux CLK ID (80) */
-+#define CK_INFRA_USB_PIPE	     (127 - GATE_OFFSET) /* Linux CLK ID (81) */
-+#define CK_INFRA_USB_PIPE_CK_P1	     (128 - GATE_OFFSET) /* Linux CLK ID (82) */
-+#define CK_INFRA_USB_UTMI	     (129 - GATE_OFFSET) /* Linux CLK ID (83) */
-+#define CK_INFRA_USB_UTMI_CK_P1	     (130 - GATE_OFFSET) /* Linux CLK ID (84) */
-+#define CK_INFRA_USB_XHCI	     (131 - GATE_OFFSET) /* Linux CLK ID (85) */
-+#define CK_INFRA_USB_XHCI_CK_P1	     (132 - GATE_OFFSET) /* Linux CLK ID (86) */
-+#define CK_INFRA_PCIE_GFMUX_TL_P0    (133 - GATE_OFFSET) /* Linux CLK ID (87) */
-+#define CK_INFRA_PCIE_GFMUX_TL_P1    (134 - GATE_OFFSET) /* Linux CLK ID (88) */
-+#define CK_INFRA_PCIE_GFMUX_TL_P2    (135 - GATE_OFFSET) /* Linux CLK ID (89) */
-+#define CK_INFRA_PCIE_GFMUX_TL_P3    (136 - GATE_OFFSET) /* Linux CLK ID (90) */
-+#define CK_INFRA_PCIE_PIPE_P0	     (137 - GATE_OFFSET) /* Linux CLK ID (91) */
-+#define CK_INFRA_PCIE_PIPE_P1	     (138 - GATE_OFFSET) /* Linux CLK ID (92) */
-+#define CK_INFRA_PCIE_PIPE_P2	     (139 - GATE_OFFSET) /* Linux CLK ID (93) */
-+#define CK_INFRA_PCIE_PIPE_P3	     (140 - GATE_OFFSET) /* Linux CLK ID (94) */
-+#define CK_INFRA_133M_PCIE_CK_P0     (141 - GATE_OFFSET) /* Linux CLK ID (95) */
-+#define CK_INFRA_133M_PCIE_CK_P1     (142 - GATE_OFFSET) /* Linux CLK ID (96) */
-+#define CK_INFRA_133M_PCIE_CK_P2     (143 - GATE_OFFSET) /* Linux CLK ID (97) */
-+#define CK_INFRA_133M_PCIE_CK_P3     (144 - GATE_OFFSET) /* Linux CLK ID (98) */
-+#define CK_INFRA_PCIE_PERI_26M_CK_P0 (145 - GATE_OFFSET) /* Linux CLK ID (99) */
-+#define CK_INFRA_PCIE_PERI_26M_CK_P1                                           \
-+	(146 - GATE_OFFSET) /* Linux CLK ID (100) */
-+#define CK_INFRA_PCIE_PERI_26M_CK_P2                                           \
-+	(147 - GATE_OFFSET) /* Linux CLK ID (101) */
-+#define CK_INFRA_PCIE_PERI_26M_CK_P3                                           \
-+	(148 - GATE_OFFSET) /* Linux CLK ID (102) */
-+
-+/* TOPCKGEN */
-+/* mtk_fixed_factor */
-+#define CK_TOP_CB_CKSQ_40M    0 /* Linux CLK ID (74) */
-+#define CK_TOP_CB_M_416M      1 /* Linux CLK ID (75) */
-+#define CK_TOP_CB_M_D2	      2 /* Linux CLK ID (76) */
-+#define CK_TOP_M_D3_D2	      3 /* Linux CLK ID (77) */
-+#define CK_TOP_CB_M_D4	      4 /* Linux CLK ID (78) */
-+#define CK_TOP_CB_M_D8	      5 /* Linux CLK ID (79) */
-+#define CK_TOP_M_D8_D2	      6 /* Linux CLK ID (80) */
-+#define CK_TOP_CB_MM_720M     7 /* Linux CLK ID (81) */
-+#define CK_TOP_CB_MM_D2	      8 /* Linux CLK ID (82) */
-+#define CK_TOP_CB_MM_D3_D5    9 /* Linux CLK ID (83) */
-+#define CK_TOP_CB_MM_D4	      10 /* Linux CLK ID (84) */
-+#define CK_TOP_MM_D6_D2	      11 /* Linux CLK ID (85) */
-+#define CK_TOP_CB_MM_D8	      12 /* Linux CLK ID (86) */
-+#define CK_TOP_CB_APLL2_196M  13 /* Linux CLK ID (87) */
-+#define CK_TOP_CB_APLL2_D4    14 /* Linux CLK ID (88) */
-+#define CK_TOP_CB_NET1_D4     15 /* Linux CLK ID (89) */
-+#define CK_TOP_CB_NET1_D5     16 /* Linux CLK ID (90) */
-+#define CK_TOP_NET1_D5_D2     17 /* Linux CLK ID (91) */
-+#define CK_TOP_NET1_D5_D4     18 /* Linux CLK ID (92) */
-+#define CK_TOP_CB_NET1_D8     19 /* Linux CLK ID (93) */
-+#define CK_TOP_NET1_D8_D2     20 /* Linux CLK ID (94) */
-+#define CK_TOP_NET1_D8_D4     21 /* Linux CLK ID (95) */
-+#define CK_TOP_NET1_D8_D8     22 /* Linux CLK ID (96) */
-+#define CK_TOP_NET1_D8_D16    23 /* Linux CLK ID (97) */
-+#define CK_TOP_CB_NET2_800M   24 /* Linux CLK ID (98) */
-+#define CK_TOP_CB_NET2_D2     25 /* Linux CLK ID (99) */
-+#define CK_TOP_CB_NET2_D4     26 /* Linux CLK ID (100) */
-+#define CK_TOP_NET2_D4_D4     27 /* Linux CLK ID (101) */
-+#define CK_TOP_NET2_D4_D8     28 /* Linux CLK ID (102) */
-+#define CK_TOP_CB_NET2_D6     29 /* Linux CLK ID (103) */
-+#define CK_TOP_CB_NET2_D8     30 /* Linux CLK ID (104) */
-+#define CK_TOP_CB_WEDMCU_208M 31 /* Linux CLK ID (105) */
-+#define CK_TOP_CB_SGM_325M    32 /* Linux CLK ID (106) */
-+#define CK_TOP_CB_NETSYS_850M 33 /* Linux CLK ID (107) */
-+#define CK_TOP_CB_MSDC_400M   34 /* Linux CLK ID (108) */
-+#define CK_TOP_CKSQ_40M_D2    35 /* Linux CLK ID (109) */
-+#define CK_TOP_CB_RTC_32K     36 /* Linux CLK ID (110) */
-+#define CK_TOP_CB_RTC_32P7K   37 /* Linux CLK ID (111) */
-+#define CK_TOP_INFRA_F32K     38 /* Linux CLK ID (112) */
-+#define CK_TOP_CKSQ_SRC	      39 /* Linux CLK ID (113) */
-+#define CK_TOP_NETSYS_2X      40 /* Linux CLK ID (114) */
-+#define CK_TOP_NETSYS_GSW     41 /* Linux CLK ID (115) */
-+#define CK_TOP_NETSYS_WED_MCU 42 /* Linux CLK ID (116) */
-+#define CK_TOP_EIP197	      43 /* Linux CLK ID (117) */
-+#define CK_TOP_EMMC_250M      44 /* Linux CLK ID (118) */
-+#define CK_TOP_EMMC_400M      45 /* Linux CLK ID (119) */
-+#define CK_TOP_SPI	      46 /* Linux CLK ID (120) */
-+#define CK_TOP_SPIM_MST	      47 /* Linux CLK ID (121) */
-+#define CK_TOP_NFI1X	      48 /* Linux CLK ID (122) */
-+#define CK_TOP_SPINFI_BCK     49 /* Linux CLK ID (123) */
-+#define CK_TOP_I2C_BCK	      50 /* Linux CLK ID (124) */
-+#define CK_TOP_USB_SYS	      51 /* Linux CLK ID (125) */
-+#define CK_TOP_USB_SYS_P1     52 /* Linux CLK ID (126) */
-+#define CK_TOP_USB_XHCI	      53 /* Linux CLK ID (127) */
-+#define CK_TOP_USB_XHCI_P1    54 /* Linux CLK ID (128) */
-+#define CK_TOP_USB_FRMCNT     55 /* Linux CLK ID (129) */
-+#define CK_TOP_USB_FRMCNT_P1  56 /* Linux CLK ID (130) */
-+#define CK_TOP_AUD	      57 /* Linux CLK ID (131) */
-+#define CK_TOP_A1SYS	      58 /* Linux CLK ID (132) */
-+#define CK_TOP_AUD_L	      59 /* Linux CLK ID (133) */
-+#define CK_TOP_A_TUNER	      60 /* Linux CLK ID (134) */
-+#define CK_TOP_SYSAXI	      61 /* Linux CLK ID (135) */
-+#define CK_TOP_INFRA_F26M     62 /* Linux CLK ID (136) */
-+#define CK_TOP_USB_REF	      63 /* Linux CLK ID (137) */
-+#define CK_TOP_USB_CK_P1      64 /* Linux CLK ID (138) */
-+/* mtk_mux */
-+#define CK_TOP_NETSYS_SEL	      65 /* Linux CLK ID (0) */
-+#define CK_TOP_NETSYS_500M_SEL	      66 /* Linux CLK ID (1) */
-+#define CK_TOP_NETSYS_2X_SEL	      67 /* Linux CLK ID (2) */
-+#define CK_TOP_NETSYS_GSW_SEL	      68 /* Linux CLK ID (3) */
-+#define CK_TOP_ETH_GMII_SEL	      69 /* Linux CLK ID (4) */
-+#define CK_TOP_NETSYS_MCU_SEL	      70 /* Linux CLK ID (5) */
-+#define CK_TOP_NETSYS_PAO_2X_SEL      71 /* Linux CLK ID (6) */
-+#define CK_TOP_EIP197_SEL	      72 /* Linux CLK ID (7) */
-+#define CK_TOP_AXI_INFRA_SEL	      73 /* Linux CLK ID (8) */
-+#define CK_TOP_UART_SEL		      74 /* Linux CLK ID (9) */
-+#define CK_TOP_EMMC_250M_SEL	      75 /* Linux CLK ID (10) */
-+#define CK_TOP_EMMC_400M_SEL	      76 /* Linux CLK ID (11) */
-+#define CK_TOP_SPI_SEL		      77 /* Linux CLK ID (12) */
-+#define CK_TOP_SPIM_MST_SEL	      78 /* Linux CLK ID (13) */
-+#define CK_TOP_NFI1X_SEL	      79 /* Linux CLK ID (14) */
-+#define CK_TOP_SPINFI_SEL	      80 /* Linux CLK ID (15) */
-+#define CK_TOP_PWM_SEL		      81 /* Linux CLK ID (16) */
-+#define CK_TOP_I2C_SEL		      82 /* Linux CLK ID (17) */
-+#define CK_TOP_PCIE_MBIST_250M_SEL    83 /* Linux CLK ID (18) */
-+#define CK_TOP_PEXTP_TL_SEL	      84 /* Linux CLK ID (19) */
-+#define CK_TOP_PEXTP_TL_P1_SEL	      85 /* Linux CLK ID (20) */
-+#define CK_TOP_PEXTP_TL_P2_SEL	      86 /* Linux CLK ID (21) */
-+#define CK_TOP_PEXTP_TL_P3_SEL	      87 /* Linux CLK ID (22) */
-+#define CK_TOP_USB_SYS_SEL	      88 /* Linux CLK ID (23) */
-+#define CK_TOP_USB_SYS_P1_SEL	      89 /* Linux CLK ID (24) */
-+#define CK_TOP_USB_XHCI_SEL	      90 /* Linux CLK ID (25) */
-+#define CK_TOP_USB_XHCI_P1_SEL	      91 /* Linux CLK ID (26) */
-+#define CK_TOP_USB_FRMCNT_SEL	      92 /* Linux CLK ID (27) */
-+#define CK_TOP_USB_FRMCNT_P1_SEL      93 /* Linux CLK ID (28) */
-+#define CK_TOP_AUD_SEL		      94 /* Linux CLK ID (29) */
-+#define CK_TOP_A1SYS_SEL	      95 /* Linux CLK ID (30) */
-+#define CK_TOP_AUD_L_SEL	      96 /* Linux CLK ID (31) */
-+#define CK_TOP_A_TUNER_SEL	      97 /* Linux CLK ID (32) */
-+#define CK_TOP_SSPXTP_SEL	      98 /* Linux CLK ID (33) */
-+#define CK_TOP_USB_PHY_SEL	      99 /* Linux CLK ID (34) */
-+#define CK_TOP_USXGMII_SBUS_0_SEL     100 /* Linux CLK ID (35) */
-+#define CK_TOP_USXGMII_SBUS_1_SEL     101 /* Linux CLK ID (36) */
-+#define CK_TOP_SGM_0_SEL	      102 /* Linux CLK ID (37) */
-+#define CK_TOP_SGM_SBUS_0_SEL	      103 /* Linux CLK ID (38) */
-+#define CK_TOP_SGM_1_SEL	      104 /* Linux CLK ID (39) */
-+#define CK_TOP_SGM_SBUS_1_SEL	      105 /* Linux CLK ID (40) */
-+#define CK_TOP_XFI_PHY_0_XTAL_SEL     106 /* Linux CLK ID (41) */
-+#define CK_TOP_XFI_PHY_1_XTAL_SEL     107 /* Linux CLK ID (42) */
-+#define CK_TOP_SYSAXI_SEL	      108 /* Linux CLK ID (43) */
-+#define CK_TOP_SYSAPB_SEL	      109 /* Linux CLK ID (44) */
-+#define CK_TOP_ETH_REFCK_50M_SEL      110 /* Linux CLK ID (45) */
-+#define CK_TOP_ETH_SYS_200M_SEL	      111 /* Linux CLK ID (46) */
-+#define CK_TOP_ETH_SYS_SEL	      112 /* Linux CLK ID (47) */
-+#define CK_TOP_ETH_XGMII_SEL	      113 /* Linux CLK ID (48) */
-+#define CK_TOP_BUS_TOPS_SEL	      114 /* Linux CLK ID (49) */
-+#define CK_TOP_NPU_TOPS_SEL	      115 /* Linux CLK ID (50) */
-+#define CK_TOP_DRAMC_SEL	      116 /* Linux CLK ID (51) */
-+#define CK_TOP_DRAMC_MD32_SEL	      117 /* Linux CLK ID (52) */
-+#define CK_TOP_INFRA_F26M_SEL	      118 /* Linux CLK ID (53) */
-+#define CK_TOP_PEXTP_P0_SEL	      119 /* Linux CLK ID (54) */
-+#define CK_TOP_PEXTP_P1_SEL	      120 /* Linux CLK ID (55) */
-+#define CK_TOP_PEXTP_P2_SEL	      121 /* Linux CLK ID (56) */
-+#define CK_TOP_PEXTP_P3_SEL	      122 /* Linux CLK ID (57) */
-+#define CK_TOP_DA_XTP_GLB_P0_SEL      123 /* Linux CLK ID (58) */
-+#define CK_TOP_DA_XTP_GLB_P1_SEL      124 /* Linux CLK ID (59) */
-+#define CK_TOP_DA_XTP_GLB_P2_SEL      125 /* Linux CLK ID (60) */
-+#define CK_TOP_DA_XTP_GLB_P3_SEL      126 /* Linux CLK ID (61) */
-+#define CK_TOP_CKM_SEL		      127 /* Linux CLK ID (62) */
-+#define CK_TOP_DA_SELM_XTAL_SEL	      128 /* Linux CLK ID (63) */
-+#define CK_TOP_PEXTP_SEL	      129 /* Linux CLK ID (64) */
-+#define CK_TOP_TOPS_P2_26M_SEL	      130 /* Linux CLK ID (65) */
-+#define CK_TOP_MCUSYS_BACKUP_625M_SEL 131 /* Linux CLK ID (66) */
-+#define CK_TOP_NETSYS_SYNC_250M_SEL   132 /* Linux CLK ID (67) */
-+#define CK_TOP_MACSEC_SEL	      133 /* Linux CLK ID (68) */
-+#define CK_TOP_NETSYS_TOPS_400M_SEL   134 /* Linux CLK ID (69) */
-+#define CK_TOP_NETSYS_PPEFB_250M_SEL  135 /* Linux CLK ID (70) */
-+#define CK_TOP_NETSYS_WARP_SEL	      136 /* Linux CLK ID (71) */
-+#define CK_TOP_ETH_MII_SEL	      137 /* Linux CLK ID (72) */
-+#define CK_TOP_CK_NPU_SEL_CM_TOPS_SEL 138 /* Linux CLK ID (73) */
-+
-+/* APMIXEDSYS */
-+/* mtk_pll_data */
-+#define CK_APMIXED_NETSYSPLL  0
-+#define CK_APMIXED_MPLL	      1
-+#define CK_APMIXED_MMPLL      2
-+#define CK_APMIXED_APLL2      3
-+#define CK_APMIXED_NET1PLL    4
-+#define CK_APMIXED_NET2PLL    5
-+#define CK_APMIXED_WEDMCUPLL  6
-+#define CK_APMIXED_SGMPLL     7
-+#define CK_APMIXED_ARM_B      8
-+#define CK_APMIXED_CCIPLL2_B  9
-+#define CK_APMIXED_USXGMIIPLL 10
-+#define CK_APMIXED_MSDCPLL    11
-+
-+/* ETHSYS ETH DMA  */
-+/* mtk_gate */
-+#define CK_ETHDMA_FE_EN 0
-+
-+/* SGMIISYS_0 */
-+/* mtk_gate */
-+#define CK_SGM0_TX_EN 0
-+#define CK_SGM0_RX_EN 1
-+
-+/* SGMIISYS_1 */
-+/* mtk_gate */
-+#define CK_SGM1_TX_EN 0
-+#define CK_SGM1_RX_EN 1
-+
-+/* ETHWARP */
-+/* mtk_gate */
-+#define CK_ETHWARP_WOCPU2_EN 0
-+#define CK_ETHWARP_WOCPU1_EN 1
-+#define CK_ETHWARP_WOCPU0_EN 2
-+
-+#endif /* _DT_BINDINGS_CLK_MT7988_H */
diff --git a/package/boot/uboot-mediatek/patches/101-11-reset-mediatek-add-reset-definition-for-MediaTek-MT7.patch b/package/boot/uboot-mediatek/patches/101-11-reset-mediatek-add-reset-definition-for-MediaTek-MT7.patch
deleted file mode 100644
index f14c38363874bf..00000000000000
--- a/package/boot/uboot-mediatek/patches/101-11-reset-mediatek-add-reset-definition-for-MediaTek-MT7.patch
+++ /dev/null
@@ -1,49 +0,0 @@
-From b4a308dd31a7c6754be230849a5e430052268b9c Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:16:33 +0800
-Subject: [PATCH 11/29] reset: mediatek: add reset definition for MediaTek
- MT7988 SoC
-
-This patch adds reset bits for MediaTek MT7988
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- include/dt-bindings/reset/mt7988-reset.h | 31 ++++++++++++++++++++++++
- 1 file changed, 31 insertions(+)
- create mode 100644 include/dt-bindings/reset/mt7988-reset.h
-
---- /dev/null
-+++ b/include/dt-bindings/reset/mt7988-reset.h
-@@ -0,0 +1,31 @@
-+/* SPDX-License-Identifier: GPL-2.0 */
-+/*
-+ * Copyright (C) 2023 MediaTek Inc.
-+ */
-+
-+#ifndef _DT_BINDINGS_MTK_RESET_H_
-+#define _DT_BINDINGS_MTK_RESET_H_
-+
-+/* ETHDMA Subsystem resets */
-+#define ETHDMA_FE_RST			6
-+#define ETHDMA_PMTR_RST			8
-+#define ETHDMA_GMAC_RST			23
-+#define ETHDMA_WDMA0_RST		24
-+#define ETHDMA_WDMA1_RST		25
-+#define ETHDMA_WDMA2_RST		26
-+#define ETHDMA_PPE0_RST			29
-+#define ETHDMA_PPE1_RST			30
-+#define ETHDMA_PPE2_RST			31
-+
-+/* ETHWARP Subsystem resets */
-+#define ETHWARP_GSW_RST			9
-+#define ETHWARP_EIP197_RST		10
-+#define ETHWARP_WOCPU0_RST		32
-+#define ETHWARP_WOCPU1_RST		33
-+#define ETHWARP_WOCPU2_RST		34
-+#define ETHWARP_WOX_NET_MUX_RST		35
-+#define ETHWARP_WED0_RST		36
-+#define ETHWARP_WED1_RST		37
-+#define ETHWARP_WED2_RST		38
-+
-+#endif /* _DT_BINDINGS_MTK_RESET_H_ */
diff --git a/package/boot/uboot-mediatek/patches/101-12-pinctrl-mediatek-convert-most-definitions-to-const.patch b/package/boot/uboot-mediatek/patches/101-12-pinctrl-mediatek-convert-most-definitions-to-const.patch
deleted file mode 100644
index 4085f1154199ce..00000000000000
--- a/package/boot/uboot-mediatek/patches/101-12-pinctrl-mediatek-convert-most-definitions-to-const.patch
+++ /dev/null
@@ -1,2267 +0,0 @@
-From 30227fcf55ac95ad6778de2fc3e6d1e00cf82566 Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:16:37 +0800
-Subject: [PATCH 12/29] pinctrl: mediatek: convert most definitions to const
-
-There exists a situation of the mediatek pinctrl driver that may return
-wrong pin function value for the pinmux driver:
-- All pin function arrays are defined without const
-- Some pin function arrays contain all-zero value, e.g.:
-  static int mt7622_spi_funcs[] = { 0, 0, 0, 0, 0, 0, };
-- These arrays will be put into .bss section during compilation
-- .bss section has no "a" attribute and does not exist in the final binary
-  file after objcopy.
-- FDT binary blob is appended to the u-boot binary, which occupies the
-  .bss section.
-- During board_f stage, .bss has not been initialized, and contains the
-  data of FDT, which is not full-zero data.
-- pinctrl driver is initialized in board_f stage, and it will get wrong
-  data if another driver is going to set default pinctrl.
-
-Since pinmux information and soc data are only meant to be read-only, thus
-should be declared as const. This will force all pinctrl data being put
-into .rodata section. Since .rodata has "a" attribute, even the all-zero
-data will be allocated and filled with correct value in to u-boot binary.
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- drivers/pinctrl/mediatek/pinctrl-mt7622.c     | 474 ++++++-------
- drivers/pinctrl/mediatek/pinctrl-mt7623.c     | 650 +++++++++---------
- drivers/pinctrl/mediatek/pinctrl-mt7629.c     | 174 ++---
- drivers/pinctrl/mediatek/pinctrl-mt7981.c     | 270 ++++----
- drivers/pinctrl/mediatek/pinctrl-mt7986.c     | 145 ++--
- drivers/pinctrl/mediatek/pinctrl-mt8512.c     |  24 +-
- drivers/pinctrl/mediatek/pinctrl-mt8516.c     |  18 +-
- drivers/pinctrl/mediatek/pinctrl-mt8518.c     |  20 +-
- drivers/pinctrl/mediatek/pinctrl-mtk-common.c |   4 +-
- drivers/pinctrl/mediatek/pinctrl-mtk-common.h |   8 +-
- 10 files changed, 898 insertions(+), 889 deletions(-)
-
---- a/drivers/pinctrl/mediatek/pinctrl-mt7622.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt7622.c
-@@ -233,283 +233,285 @@ static const struct mtk_pin_desc mt7622_
-  */
- 
- /* EMMC */
--static int mt7622_emmc_pins[] = { 40, 41, 42, 43, 44, 45, 47, 48, 49, 50, };
--static int mt7622_emmc_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
-+static const int mt7622_emmc_pins[] = {
-+	40, 41, 42, 43, 44, 45, 47, 48, 49, 50, };
-+static const int mt7622_emmc_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
- 
--static int mt7622_emmc_rst_pins[] = { 37, };
--static int mt7622_emmc_rst_funcs[] = { 1, };
-+static const int mt7622_emmc_rst_pins[] = { 37, };
-+static const int mt7622_emmc_rst_funcs[] = { 1, };
- 
- /* LED for EPHY */
--static int mt7622_ephy_leds_pins[] = { 86, 91, 92, 93, 94, };
--static int mt7622_ephy_leds_funcs[] = { 0, 0, 0, 0, 0, };
--static int mt7622_ephy0_led_pins[] = { 86, };
--static int mt7622_ephy0_led_funcs[] = { 0, };
--static int mt7622_ephy1_led_pins[] = { 91, };
--static int mt7622_ephy1_led_funcs[] = { 2, };
--static int mt7622_ephy2_led_pins[] = { 92, };
--static int mt7622_ephy2_led_funcs[] = { 2, };
--static int mt7622_ephy3_led_pins[] = { 93, };
--static int mt7622_ephy3_led_funcs[] = { 2, };
--static int mt7622_ephy4_led_pins[] = { 94, };
--static int mt7622_ephy4_led_funcs[] = { 2, };
-+static const int mt7622_ephy_leds_pins[] = { 86, 91, 92, 93, 94, };
-+static const int mt7622_ephy_leds_funcs[] = { 0, 0, 0, 0, 0, };
-+static const int mt7622_ephy0_led_pins[] = { 86, };
-+static const int mt7622_ephy0_led_funcs[] = { 0, };
-+static const int mt7622_ephy1_led_pins[] = { 91, };
-+static const int mt7622_ephy1_led_funcs[] = { 2, };
-+static const int mt7622_ephy2_led_pins[] = { 92, };
-+static const int mt7622_ephy2_led_funcs[] = { 2, };
-+static const int mt7622_ephy3_led_pins[] = { 93, };
-+static const int mt7622_ephy3_led_funcs[] = { 2, };
-+static const int mt7622_ephy4_led_pins[] = { 94, };
-+static const int mt7622_ephy4_led_funcs[] = { 2, };
- 
- /* Embedded Switch */
--static int mt7622_esw_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61,
--				 62, 63, 64, 65, 66, 67, 68, 69, 70, };
--static int mt7622_esw_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
--				  0, 0, 0, 0, 0, 0, 0, 0, 0, };
--static int mt7622_esw_p0_p1_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, };
--static int mt7622_esw_p0_p1_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
--static int mt7622_esw_p2_p3_p4_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66, 67,
--					  68, 69, 70, };
--static int mt7622_esw_p2_p3_p4_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0,
--					   0, 0, 0, };
-+static const int mt7622_esw_pins[] = {
-+	51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68,
-+	69, 70, };
-+static const int mt7622_esw_funcs[] = {
-+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
-+static const int mt7622_esw_p0_p1_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, };
-+static const int mt7622_esw_p0_p1_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
-+static const int mt7622_esw_p2_p3_p4_pins[] = {
-+	59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, };
-+static const int mt7622_esw_p2_p3_p4_funcs[] = {
-+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
- /* RGMII via ESW */
--static int mt7622_rgmii_via_esw_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66,
--					   67, 68, 69, 70, };
--static int mt7622_rgmii_via_esw_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
--					    0, };
-+static const int mt7622_rgmii_via_esw_pins[] = {
-+	59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, };
-+static const int mt7622_rgmii_via_esw_funcs[] = {
-+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
- 
- /* RGMII via GMAC1 */
--static int mt7622_rgmii_via_gmac1_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66,
--					     67, 68, 69, 70, };
--static int mt7622_rgmii_via_gmac1_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
--					      2, };
-+static const int mt7622_rgmii_via_gmac1_pins[] = {
-+	59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, };
-+static const int mt7622_rgmii_via_gmac1_funcs[] = {
-+	2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
- 
- /* RGMII via GMAC2 */
--static int mt7622_rgmii_via_gmac2_pins[] = { 25, 26, 27, 28, 29, 30, 31, 32,
--					     33, 34, 35, 36, };
--static int mt7622_rgmii_via_gmac2_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
--					      0, };
-+static const int mt7622_rgmii_via_gmac2_pins[] = {
-+	25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, };
-+static const int mt7622_rgmii_via_gmac2_funcs[] = {
-+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
- 
- /* I2C */
--static int mt7622_i2c0_pins[] = { 14, 15, };
--static int mt7622_i2c0_funcs[] = { 0, 0, };
--static int mt7622_i2c1_0_pins[] = { 55, 56, };
--static int mt7622_i2c1_0_funcs[] = { 0, 0, };
--static int mt7622_i2c1_1_pins[] = { 73, 74, };
--static int mt7622_i2c1_1_funcs[] = { 3, 3, };
--static int mt7622_i2c1_2_pins[] = { 87, 88, };
--static int mt7622_i2c1_2_funcs[] = { 0, 0, };
--static int mt7622_i2c2_0_pins[] = { 57, 58, };
--static int mt7622_i2c2_0_funcs[] = { 0, 0, };
--static int mt7622_i2c2_1_pins[] = { 75, 76, };
--static int mt7622_i2c2_1_funcs[] = { 3, 3, };
--static int mt7622_i2c2_2_pins[] = { 89, 90, };
--static int mt7622_i2c2_2_funcs[] = { 0, 0, };
-+static const int mt7622_i2c0_pins[] = { 14, 15, };
-+static const int mt7622_i2c0_funcs[] = { 0, 0, };
-+static const int mt7622_i2c1_0_pins[] = { 55, 56, };
-+static const int mt7622_i2c1_0_funcs[] = { 0, 0, };
-+static const int mt7622_i2c1_1_pins[] = { 73, 74, };
-+static const int mt7622_i2c1_1_funcs[] = { 3, 3, };
-+static const int mt7622_i2c1_2_pins[] = { 87, 88, };
-+static const int mt7622_i2c1_2_funcs[] = { 0, 0, };
-+static const int mt7622_i2c2_0_pins[] = { 57, 58, };
-+static const int mt7622_i2c2_0_funcs[] = { 0, 0, };
-+static const int mt7622_i2c2_1_pins[] = { 75, 76, };
-+static const int mt7622_i2c2_1_funcs[] = { 3, 3, };
-+static const int mt7622_i2c2_2_pins[] = { 89, 90, };
-+static const int mt7622_i2c2_2_funcs[] = { 0, 0, };
- 
- /* I2S */
--static int mt7622_i2s_in_mclk_bclk_ws_pins[] = { 3, 4, 5, };
--static int mt7622_i2s_in_mclk_bclk_ws_funcs[] = { 3, 3, 0, };
--static int mt7622_i2s1_in_data_pins[] = { 1, };
--static int mt7622_i2s1_in_data_funcs[] = { 0, };
--static int mt7622_i2s2_in_data_pins[] = { 16, };
--static int mt7622_i2s2_in_data_funcs[] = { 0, };
--static int mt7622_i2s3_in_data_pins[] = { 17, };
--static int mt7622_i2s3_in_data_funcs[] = { 0, };
--static int mt7622_i2s4_in_data_pins[] = { 18, };
--static int mt7622_i2s4_in_data_funcs[] = { 0, };
--static int mt7622_i2s_out_mclk_bclk_ws_pins[] = { 3, 4, 5, };
--static int mt7622_i2s_out_mclk_bclk_ws_funcs[] = { 0, 0, 0, };
--static int mt7622_i2s1_out_data_pins[] = { 2, };
--static int mt7622_i2s1_out_data_funcs[] = { 0, };
--static int mt7622_i2s2_out_data_pins[] = { 19, };
--static int mt7622_i2s2_out_data_funcs[] = { 0, };
--static int mt7622_i2s3_out_data_pins[] = { 20, };
--static int mt7622_i2s3_out_data_funcs[] = { 0, };
--static int mt7622_i2s4_out_data_pins[] = { 21, };
--static int mt7622_i2s4_out_data_funcs[] = { 0, };
-+static const int mt7622_i2s_in_mclk_bclk_ws_pins[] = { 3, 4, 5, };
-+static const int mt7622_i2s_in_mclk_bclk_ws_funcs[] = { 3, 3, 0, };
-+static const int mt7622_i2s1_in_data_pins[] = { 1, };
-+static const int mt7622_i2s1_in_data_funcs[] = { 0, };
-+static const int mt7622_i2s2_in_data_pins[] = { 16, };
-+static const int mt7622_i2s2_in_data_funcs[] = { 0, };
-+static const int mt7622_i2s3_in_data_pins[] = { 17, };
-+static const int mt7622_i2s3_in_data_funcs[] = { 0, };
-+static const int mt7622_i2s4_in_data_pins[] = { 18, };
-+static const int mt7622_i2s4_in_data_funcs[] = { 0, };
-+static const int mt7622_i2s_out_mclk_bclk_ws_pins[] = { 3, 4, 5, };
-+static const int mt7622_i2s_out_mclk_bclk_ws_funcs[] = { 0, 0, 0, };
-+static const int mt7622_i2s1_out_data_pins[] = { 2, };
-+static const int mt7622_i2s1_out_data_funcs[] = { 0, };
-+static const int mt7622_i2s2_out_data_pins[] = { 19, };
-+static const int mt7622_i2s2_out_data_funcs[] = { 0, };
-+static const int mt7622_i2s3_out_data_pins[] = { 20, };
-+static const int mt7622_i2s3_out_data_funcs[] = { 0, };
-+static const int mt7622_i2s4_out_data_pins[] = { 21, };
-+static const int mt7622_i2s4_out_data_funcs[] = { 0, };
- 
- /* IR */
--static int mt7622_ir_0_tx_pins[] = { 16, };
--static int mt7622_ir_0_tx_funcs[] = { 4, };
--static int mt7622_ir_1_tx_pins[] = { 59, };
--static int mt7622_ir_1_tx_funcs[] = { 5, };
--static int mt7622_ir_2_tx_pins[] = { 99, };
--static int mt7622_ir_2_tx_funcs[] = { 3, };
--static int mt7622_ir_0_rx_pins[] = { 17, };
--static int mt7622_ir_0_rx_funcs[] = { 4, };
--static int mt7622_ir_1_rx_pins[] = { 60, };
--static int mt7622_ir_1_rx_funcs[] = { 5, };
--static int mt7622_ir_2_rx_pins[] = { 100, };
--static int mt7622_ir_2_rx_funcs[] = { 3, };
-+static const int mt7622_ir_0_tx_pins[] = { 16, };
-+static const int mt7622_ir_0_tx_funcs[] = { 4, };
-+static const int mt7622_ir_1_tx_pins[] = { 59, };
-+static const int mt7622_ir_1_tx_funcs[] = { 5, };
-+static const int mt7622_ir_2_tx_pins[] = { 99, };
-+static const int mt7622_ir_2_tx_funcs[] = { 3, };
-+static const int mt7622_ir_0_rx_pins[] = { 17, };
-+static const int mt7622_ir_0_rx_funcs[] = { 4, };
-+static const int mt7622_ir_1_rx_pins[] = { 60, };
-+static const int mt7622_ir_1_rx_funcs[] = { 5, };
-+static const int mt7622_ir_2_rx_pins[] = { 100, };
-+static const int mt7622_ir_2_rx_funcs[] = { 3, };
- 
- /* MDIO */
--static int mt7622_mdc_mdio_pins[] = { 23, 24, };
--static int mt7622_mdc_mdio_funcs[] = { 0, 0, };
-+static const int mt7622_mdc_mdio_pins[] = { 23, 24, };
-+static const int mt7622_mdc_mdio_funcs[] = { 0, 0, };
- 
- /* PCIE */
--static int mt7622_pcie0_0_waken_pins[] = { 14, };
--static int mt7622_pcie0_0_waken_funcs[] = { 2, };
--static int mt7622_pcie0_0_clkreq_pins[] = { 15, };
--static int mt7622_pcie0_0_clkreq_funcs[] = { 2, };
--static int mt7622_pcie0_1_waken_pins[] = { 79, };
--static int mt7622_pcie0_1_waken_funcs[] = { 4, };
--static int mt7622_pcie0_1_clkreq_pins[] = { 80, };
--static int mt7622_pcie0_1_clkreq_funcs[] = { 4, };
--static int mt7622_pcie1_0_waken_pins[] = { 14, };
--static int mt7622_pcie1_0_waken_funcs[] = { 3, };
--static int mt7622_pcie1_0_clkreq_pins[] = { 15, };
--static int mt7622_pcie1_0_clkreq_funcs[] = { 3, };
--
--static int mt7622_pcie0_pad_perst_pins[] = { 83, };
--static int mt7622_pcie0_pad_perst_funcs[] = { 0, };
--static int mt7622_pcie1_pad_perst_pins[] = { 84, };
--static int mt7622_pcie1_pad_perst_funcs[] = { 0, };
-+static const int mt7622_pcie0_0_waken_pins[] = { 14, };
-+static const int mt7622_pcie0_0_waken_funcs[] = { 2, };
-+static const int mt7622_pcie0_0_clkreq_pins[] = { 15, };
-+static const int mt7622_pcie0_0_clkreq_funcs[] = { 2, };
-+static const int mt7622_pcie0_1_waken_pins[] = { 79, };
-+static const int mt7622_pcie0_1_waken_funcs[] = { 4, };
-+static const int mt7622_pcie0_1_clkreq_pins[] = { 80, };
-+static const int mt7622_pcie0_1_clkreq_funcs[] = { 4, };
-+static const int mt7622_pcie1_0_waken_pins[] = { 14, };
-+static const int mt7622_pcie1_0_waken_funcs[] = { 3, };
-+static const int mt7622_pcie1_0_clkreq_pins[] = { 15, };
-+static const int mt7622_pcie1_0_clkreq_funcs[] = { 3, };
-+
-+static const int mt7622_pcie0_pad_perst_pins[] = { 83, };
-+static const int mt7622_pcie0_pad_perst_funcs[] = { 0, };
-+static const int mt7622_pcie1_pad_perst_pins[] = { 84, };
-+static const int mt7622_pcie1_pad_perst_funcs[] = { 0, };
- 
- /* PMIC bus */
--static int mt7622_pmic_bus_pins[] = { 71, 72, };
--static int mt7622_pmic_bus_funcs[] = { 0, 0, };
-+static const int mt7622_pmic_bus_pins[] = { 71, 72, };
-+static const int mt7622_pmic_bus_funcs[] = { 0, 0, };
- 
- /* Parallel NAND */
--static int mt7622_pnand_pins[] = { 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
--				   48, 49, 50, };
--static int mt7622_pnand_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
--				    0, };
-+static const int mt7622_pnand_pins[] = {
-+	37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, };
-+static const int mt7622_pnand_funcs[] = {
-+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
- 
- /* PWM */
--static int mt7622_pwm_ch1_0_pins[] = { 51, };
--static int mt7622_pwm_ch1_0_funcs[] = { 3, };
--static int mt7622_pwm_ch1_1_pins[] = { 73, };
--static int mt7622_pwm_ch1_1_funcs[] = { 4, };
--static int mt7622_pwm_ch1_2_pins[] = { 95, };
--static int mt7622_pwm_ch1_2_funcs[] = { 0, };
--static int mt7622_pwm_ch2_0_pins[] = { 52, };
--static int mt7622_pwm_ch2_0_funcs[] = { 3, };
--static int mt7622_pwm_ch2_1_pins[] = { 74, };
--static int mt7622_pwm_ch2_1_funcs[] = { 4, };
--static int mt7622_pwm_ch2_2_pins[] = { 96, };
--static int mt7622_pwm_ch2_2_funcs[] = { 0, };
--static int mt7622_pwm_ch3_0_pins[] = { 53, };
--static int mt7622_pwm_ch3_0_funcs[] = { 3, };
--static int mt7622_pwm_ch3_1_pins[] = { 75, };
--static int mt7622_pwm_ch3_1_funcs[] = { 4, };
--static int mt7622_pwm_ch3_2_pins[] = { 97, };
--static int mt7622_pwm_ch3_2_funcs[] = { 0, };
--static int mt7622_pwm_ch4_0_pins[] = { 54, };
--static int mt7622_pwm_ch4_0_funcs[] = { 3, };
--static int mt7622_pwm_ch4_1_pins[] = { 67, };
--static int mt7622_pwm_ch4_1_funcs[] = { 3, };
--static int mt7622_pwm_ch4_2_pins[] = { 76, };
--static int mt7622_pwm_ch4_2_funcs[] = { 4, };
--static int mt7622_pwm_ch4_3_pins[] = { 98, };
--static int mt7622_pwm_ch4_3_funcs[] = { 0, };
--static int mt7622_pwm_ch5_0_pins[] = { 68, };
--static int mt7622_pwm_ch5_0_funcs[] = { 3, };
--static int mt7622_pwm_ch5_1_pins[] = { 77, };
--static int mt7622_pwm_ch5_1_funcs[] = { 4, };
--static int mt7622_pwm_ch5_2_pins[] = { 99, };
--static int mt7622_pwm_ch5_2_funcs[] = { 0, };
--static int mt7622_pwm_ch6_0_pins[] = { 69, };
--static int mt7622_pwm_ch6_0_funcs[] = { 3, };
--static int mt7622_pwm_ch6_1_pins[] = { 78, };
--static int mt7622_pwm_ch6_1_funcs[] = { 4, };
--static int mt7622_pwm_ch6_2_pins[] = { 81, };
--static int mt7622_pwm_ch6_2_funcs[] = { 4, };
--static int mt7622_pwm_ch6_3_pins[] = { 100, };
--static int mt7622_pwm_ch6_3_funcs[] = { 0, };
--static int mt7622_pwm_ch7_0_pins[] = { 70, };
--static int mt7622_pwm_ch7_0_funcs[] = { 3, };
--static int mt7622_pwm_ch7_1_pins[] = { 82, };
--static int mt7622_pwm_ch7_1_funcs[] = { 4, };
--static int mt7622_pwm_ch7_2_pins[] = { 101, };
--static int mt7622_pwm_ch7_2_funcs[] = { 0, };
-+static const int mt7622_pwm_ch1_0_pins[] = { 51, };
-+static const int mt7622_pwm_ch1_0_funcs[] = { 3, };
-+static const int mt7622_pwm_ch1_1_pins[] = { 73, };
-+static const int mt7622_pwm_ch1_1_funcs[] = { 4, };
-+static const int mt7622_pwm_ch1_2_pins[] = { 95, };
-+static const int mt7622_pwm_ch1_2_funcs[] = { 0, };
-+static const int mt7622_pwm_ch2_0_pins[] = { 52, };
-+static const int mt7622_pwm_ch2_0_funcs[] = { 3, };
-+static const int mt7622_pwm_ch2_1_pins[] = { 74, };
-+static const int mt7622_pwm_ch2_1_funcs[] = { 4, };
-+static const int mt7622_pwm_ch2_2_pins[] = { 96, };
-+static const int mt7622_pwm_ch2_2_funcs[] = { 0, };
-+static const int mt7622_pwm_ch3_0_pins[] = { 53, };
-+static const int mt7622_pwm_ch3_0_funcs[] = { 3, };
-+static const int mt7622_pwm_ch3_1_pins[] = { 75, };
-+static const int mt7622_pwm_ch3_1_funcs[] = { 4, };
-+static const int mt7622_pwm_ch3_2_pins[] = { 97, };
-+static const int mt7622_pwm_ch3_2_funcs[] = { 0, };
-+static const int mt7622_pwm_ch4_0_pins[] = { 54, };
-+static const int mt7622_pwm_ch4_0_funcs[] = { 3, };
-+static const int mt7622_pwm_ch4_1_pins[] = { 67, };
-+static const int mt7622_pwm_ch4_1_funcs[] = { 3, };
-+static const int mt7622_pwm_ch4_2_pins[] = { 76, };
-+static const int mt7622_pwm_ch4_2_funcs[] = { 4, };
-+static const int mt7622_pwm_ch4_3_pins[] = { 98, };
-+static const int mt7622_pwm_ch4_3_funcs[] = { 0, };
-+static const int mt7622_pwm_ch5_0_pins[] = { 68, };
-+static const int mt7622_pwm_ch5_0_funcs[] = { 3, };
-+static const int mt7622_pwm_ch5_1_pins[] = { 77, };
-+static const int mt7622_pwm_ch5_1_funcs[] = { 4, };
-+static const int mt7622_pwm_ch5_2_pins[] = { 99, };
-+static const int mt7622_pwm_ch5_2_funcs[] = { 0, };
-+static const int mt7622_pwm_ch6_0_pins[] = { 69, };
-+static const int mt7622_pwm_ch6_0_funcs[] = { 3, };
-+static const int mt7622_pwm_ch6_1_pins[] = { 78, };
-+static const int mt7622_pwm_ch6_1_funcs[] = { 4, };
-+static const int mt7622_pwm_ch6_2_pins[] = { 81, };
-+static const int mt7622_pwm_ch6_2_funcs[] = { 4, };
-+static const int mt7622_pwm_ch6_3_pins[] = { 100, };
-+static const int mt7622_pwm_ch6_3_funcs[] = { 0, };
-+static const int mt7622_pwm_ch7_0_pins[] = { 70, };
-+static const int mt7622_pwm_ch7_0_funcs[] = { 3, };
-+static const int mt7622_pwm_ch7_1_pins[] = { 82, };
-+static const int mt7622_pwm_ch7_1_funcs[] = { 4, };
-+static const int mt7622_pwm_ch7_2_pins[] = { 101, };
-+static const int mt7622_pwm_ch7_2_funcs[] = { 0, };
- 
- /* SD */
--static int mt7622_sd_0_pins[] = { 16, 17, 18, 19, 20, 21, };
--static int mt7622_sd_0_funcs[] = { 2, 2, 2, 2, 2, 2, };
--static int mt7622_sd_1_pins[] = { 25, 26, 27, 28, 29, 30, };
--static int mt7622_sd_1_funcs[] = { 2, 2, 2, 2, 2, 2, };
-+static const int mt7622_sd_0_pins[] = { 16, 17, 18, 19, 20, 21, };
-+static const int mt7622_sd_0_funcs[] = { 2, 2, 2, 2, 2, 2, };
-+static const int mt7622_sd_1_pins[] = { 25, 26, 27, 28, 29, 30, };
-+static const int mt7622_sd_1_funcs[] = { 2, 2, 2, 2, 2, 2, };
- 
- /* Serial NAND */
--static int mt7622_snfi_pins[] = { 8, 9, 10, 11, 12, 13, };
--static int mt7622_snfi_funcs[] = { 2, 2, 2, 2, 2, 2, };
-+static const int mt7622_snfi_pins[] = { 8, 9, 10, 11, 12, 13, };
-+static const int mt7622_snfi_funcs[] = { 2, 2, 2, 2, 2, 2, };
- 
- /* SPI NOR */
--static int mt7622_spi_pins[] = { 8, 9, 10, 11, 12, 13 };
--static int mt7622_spi_funcs[] = { 0, 0, 0, 0, 0, 0, };
-+static const int mt7622_spi_pins[] = { 8, 9, 10, 11, 12, 13 };
-+static const int mt7622_spi_funcs[] = { 0, 0, 0, 0, 0, 0, };
- 
- /* SPIC */
--static int mt7622_spic0_0_pins[] = { 63, 64, 65, 66, };
--static int mt7622_spic0_0_funcs[] = { 4, 4, 4, 4, };
--static int mt7622_spic0_1_pins[] = { 79, 80, 81, 82, };
--static int mt7622_spic0_1_funcs[] = { 3, 3, 3, 3, };
--static int mt7622_spic1_0_pins[] = { 67, 68, 69, 70, };
--static int mt7622_spic1_0_funcs[] = { 4, 4, 4, 4, };
--static int mt7622_spic1_1_pins[] = { 73, 74, 75, 76, };
--static int mt7622_spic1_1_funcs[] = { 0, 0, 0, 0, };
--static int mt7622_spic2_0_pins[] = { 10, 11, 12, 13, };
--static int mt7622_spic2_0_funcs[] = { 0, 0, 0, 0, };
--static int mt7622_spic2_0_wp_hold_pins[] = { 8, 9, };
--static int mt7622_spic2_0_wp_hold_funcs[] = { 0, 0, };
-+static const int mt7622_spic0_0_pins[] = { 63, 64, 65, 66, };
-+static const int mt7622_spic0_0_funcs[] = { 4, 4, 4, 4, };
-+static const int mt7622_spic0_1_pins[] = { 79, 80, 81, 82, };
-+static const int mt7622_spic0_1_funcs[] = { 3, 3, 3, 3, };
-+static const int mt7622_spic1_0_pins[] = { 67, 68, 69, 70, };
-+static const int mt7622_spic1_0_funcs[] = { 4, 4, 4, 4, };
-+static const int mt7622_spic1_1_pins[] = { 73, 74, 75, 76, };
-+static const int mt7622_spic1_1_funcs[] = { 0, 0, 0, 0, };
-+static const int mt7622_spic2_0_pins[] = { 10, 11, 12, 13, };
-+static const int mt7622_spic2_0_funcs[] = { 0, 0, 0, 0, };
-+static const int mt7622_spic2_0_wp_hold_pins[] = { 8, 9, };
-+static const int mt7622_spic2_0_wp_hold_funcs[] = { 0, 0, };
- 
- /* TDM */
--static int mt7622_tdm_0_out_mclk_bclk_ws_pins[] = { 8, 9, 10, };
--static int mt7622_tdm_0_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
--static int mt7622_tdm_0_in_mclk_bclk_ws_pins[] = { 11, 12, 13, };
--static int mt7622_tdm_0_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
--static int mt7622_tdm_0_out_data_pins[] = { 20, };
--static int mt7622_tdm_0_out_data_funcs[] = { 3, };
--static int mt7622_tdm_0_in_data_pins[] = { 21, };
--static int mt7622_tdm_0_in_data_funcs[] = { 3, };
--static int mt7622_tdm_1_out_mclk_bclk_ws_pins[] = { 57, 58, 59, };
--static int mt7622_tdm_1_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
--static int mt7622_tdm_1_in_mclk_bclk_ws_pins[] = { 60, 61, 62, };
--static int mt7622_tdm_1_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
--static int mt7622_tdm_1_out_data_pins[] = { 55, };
--static int mt7622_tdm_1_out_data_funcs[] = { 3, };
--static int mt7622_tdm_1_in_data_pins[] = { 56, };
--static int mt7622_tdm_1_in_data_funcs[] = { 3, };
-+static const int mt7622_tdm_0_out_mclk_bclk_ws_pins[] = { 8, 9, 10, };
-+static const int mt7622_tdm_0_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
-+static const int mt7622_tdm_0_in_mclk_bclk_ws_pins[] = { 11, 12, 13, };
-+static const int mt7622_tdm_0_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
-+static const int mt7622_tdm_0_out_data_pins[] = { 20, };
-+static const int mt7622_tdm_0_out_data_funcs[] = { 3, };
-+static const int mt7622_tdm_0_in_data_pins[] = { 21, };
-+static const int mt7622_tdm_0_in_data_funcs[] = { 3, };
-+static const int mt7622_tdm_1_out_mclk_bclk_ws_pins[] = { 57, 58, 59, };
-+static const int mt7622_tdm_1_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
-+static const int mt7622_tdm_1_in_mclk_bclk_ws_pins[] = { 60, 61, 62, };
-+static const int mt7622_tdm_1_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
-+static const int mt7622_tdm_1_out_data_pins[] = { 55, };
-+static const int mt7622_tdm_1_out_data_funcs[] = { 3, };
-+static const int mt7622_tdm_1_in_data_pins[] = { 56, };
-+static const int mt7622_tdm_1_in_data_funcs[] = { 3, };
- 
- /* UART */
--static int mt7622_uart0_0_tx_rx_pins[] = { 6, 7, };
--static int mt7622_uart0_0_tx_rx_funcs[] = { 0, 0, };
--static int mt7622_uart1_0_tx_rx_pins[] = { 55, 56, };
--static int mt7622_uart1_0_tx_rx_funcs[] = { 2, 2, };
--static int mt7622_uart1_0_rts_cts_pins[] = { 57, 58, };
--static int mt7622_uart1_0_rts_cts_funcs[] = { 2, 2, };
--static int mt7622_uart1_1_tx_rx_pins[] = { 73, 74, };
--static int mt7622_uart1_1_tx_rx_funcs[] = { 2, 2, };
--static int mt7622_uart1_1_rts_cts_pins[] = { 75, 76, };
--static int mt7622_uart1_1_rts_cts_funcs[] = { 2, 2, };
--static int mt7622_uart2_0_tx_rx_pins[] = { 3, 4, };
--static int mt7622_uart2_0_tx_rx_funcs[] = { 2, 2, };
--static int mt7622_uart2_0_rts_cts_pins[] = { 1, 2, };
--static int mt7622_uart2_0_rts_cts_funcs[] = { 2, 2, };
--static int mt7622_uart2_1_tx_rx_pins[] = { 51, 52, };
--static int mt7622_uart2_1_tx_rx_funcs[] = { 0, 0, };
--static int mt7622_uart2_1_rts_cts_pins[] = { 53, 54, };
--static int mt7622_uart2_1_rts_cts_funcs[] = { 0, 0, };
--static int mt7622_uart2_2_tx_rx_pins[] = { 59, 60, };
--static int mt7622_uart2_2_tx_rx_funcs[] = { 4, 4, };
--static int mt7622_uart2_2_rts_cts_pins[] = { 61, 62, };
--static int mt7622_uart2_2_rts_cts_funcs[] = { 4, 4, };
--static int mt7622_uart2_3_tx_rx_pins[] = { 95, 96, };
--static int mt7622_uart2_3_tx_rx_funcs[] = { 3, 3, };
--static int mt7622_uart3_0_tx_rx_pins[] = { 57, 58, };
--static int mt7622_uart3_0_tx_rx_funcs[] = { 5, 5, };
--static int mt7622_uart3_1_tx_rx_pins[] = { 81, 82, };
--static int mt7622_uart3_1_tx_rx_funcs[] = { 0, 0, };
--static int mt7622_uart3_1_rts_cts_pins[] = { 79, 80, };
--static int mt7622_uart3_1_rts_cts_funcs[] = { 0, 0, };
--static int mt7622_uart4_0_tx_rx_pins[] = { 61, 62, };
--static int mt7622_uart4_0_tx_rx_funcs[] = { 5, 5, };
--static int mt7622_uart4_1_tx_rx_pins[] = { 91, 92, };
--static int mt7622_uart4_1_tx_rx_funcs[] = { 0, 0, };
--static int mt7622_uart4_1_rts_cts_pins[] = { 93, 94 };
--static int mt7622_uart4_1_rts_cts_funcs[] = { 0, 0, };
--static int mt7622_uart4_2_tx_rx_pins[] = { 97, 98, };
--static int mt7622_uart4_2_tx_rx_funcs[] = { 2, 2, };
--static int mt7622_uart4_2_rts_cts_pins[] = { 95, 96 };
--static int mt7622_uart4_2_rts_cts_funcs[] = { 2, 2, };
-+static const int mt7622_uart0_0_tx_rx_pins[] = { 6, 7, };
-+static const int mt7622_uart0_0_tx_rx_funcs[] = { 0, 0, };
-+static const int mt7622_uart1_0_tx_rx_pins[] = { 55, 56, };
-+static const int mt7622_uart1_0_tx_rx_funcs[] = { 2, 2, };
-+static const int mt7622_uart1_0_rts_cts_pins[] = { 57, 58, };
-+static const int mt7622_uart1_0_rts_cts_funcs[] = { 2, 2, };
-+static const int mt7622_uart1_1_tx_rx_pins[] = { 73, 74, };
-+static const int mt7622_uart1_1_tx_rx_funcs[] = { 2, 2, };
-+static const int mt7622_uart1_1_rts_cts_pins[] = { 75, 76, };
-+static const int mt7622_uart1_1_rts_cts_funcs[] = { 2, 2, };
-+static const int mt7622_uart2_0_tx_rx_pins[] = { 3, 4, };
-+static const int mt7622_uart2_0_tx_rx_funcs[] = { 2, 2, };
-+static const int mt7622_uart2_0_rts_cts_pins[] = { 1, 2, };
-+static const int mt7622_uart2_0_rts_cts_funcs[] = { 2, 2, };
-+static const int mt7622_uart2_1_tx_rx_pins[] = { 51, 52, };
-+static const int mt7622_uart2_1_tx_rx_funcs[] = { 0, 0, };
-+static const int mt7622_uart2_1_rts_cts_pins[] = { 53, 54, };
-+static const int mt7622_uart2_1_rts_cts_funcs[] = { 0, 0, };
-+static const int mt7622_uart2_2_tx_rx_pins[] = { 59, 60, };
-+static const int mt7622_uart2_2_tx_rx_funcs[] = { 4, 4, };
-+static const int mt7622_uart2_2_rts_cts_pins[] = { 61, 62, };
-+static const int mt7622_uart2_2_rts_cts_funcs[] = { 4, 4, };
-+static const int mt7622_uart2_3_tx_rx_pins[] = { 95, 96, };
-+static const int mt7622_uart2_3_tx_rx_funcs[] = { 3, 3, };
-+static const int mt7622_uart3_0_tx_rx_pins[] = { 57, 58, };
-+static const int mt7622_uart3_0_tx_rx_funcs[] = { 5, 5, };
-+static const int mt7622_uart3_1_tx_rx_pins[] = { 81, 82, };
-+static const int mt7622_uart3_1_tx_rx_funcs[] = { 0, 0, };
-+static const int mt7622_uart3_1_rts_cts_pins[] = { 79, 80, };
-+static const int mt7622_uart3_1_rts_cts_funcs[] = { 0, 0, };
-+static const int mt7622_uart4_0_tx_rx_pins[] = { 61, 62, };
-+static const int mt7622_uart4_0_tx_rx_funcs[] = { 5, 5, };
-+static const int mt7622_uart4_1_tx_rx_pins[] = { 91, 92, };
-+static const int mt7622_uart4_1_tx_rx_funcs[] = { 0, 0, };
-+static const int mt7622_uart4_1_rts_cts_pins[] = { 93, 94 };
-+static const int mt7622_uart4_1_rts_cts_funcs[] = { 0, 0, };
-+static const int mt7622_uart4_2_tx_rx_pins[] = { 97, 98, };
-+static const int mt7622_uart4_2_tx_rx_funcs[] = { 2, 2, };
-+static const int mt7622_uart4_2_rts_cts_pins[] = { 95, 96 };
-+static const int mt7622_uart4_2_rts_cts_funcs[] = { 2, 2, };
- 
- /* Watchdog */
--static int mt7622_watchdog_pins[] = { 78, };
--static int mt7622_watchdog_funcs[] = { 0, };
-+static const int mt7622_watchdog_pins[] = { 78, };
-+static const int mt7622_watchdog_funcs[] = { 0, };
- 
- /* WLAN LED */
--static int mt7622_wled_pins[] = { 85, };
--static int mt7622_wled_funcs[] = { 0, };
-+static const int mt7622_wled_pins[] = { 85, };
-+static const int mt7622_wled_funcs[] = { 0, };
- 
- static const struct mtk_group_desc mt7622_groups[] = {
- 	PINCTRL_PIN_GROUP("emmc", mt7622_emmc),
-@@ -719,7 +721,7 @@ static const struct mtk_function_desc mt
- 	{"watchdog", mt7622_wdt_groups, ARRAY_SIZE(mt7622_wdt_groups)},
- };
- 
--static struct mtk_pinctrl_soc mt7622_data = {
-+static const struct mtk_pinctrl_soc mt7622_data = {
- 	.name = "mt7622_pinctrl",
- 	.reg_cal = mt7622_reg_cals,
- 	.pins = mt7622_pins,
---- a/drivers/pinctrl/mediatek/pinctrl-mt7623.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt7623.c
-@@ -692,377 +692,377 @@ static const struct mtk_pin_desc mt7623_
-  */
- 
- /* AUDIO EXT CLK */
--static int mt7623_aud_ext_clk0_pins[] = { 208, };
--static int mt7623_aud_ext_clk0_funcs[] = { 1, };
--static int mt7623_aud_ext_clk1_pins[] = { 209, };
--static int mt7623_aud_ext_clk1_funcs[] = { 1, };
-+static const int mt7623_aud_ext_clk0_pins[] = { 208, };
-+static const int mt7623_aud_ext_clk0_funcs[] = { 1, };
-+static const int mt7623_aud_ext_clk1_pins[] = { 209, };
-+static const int mt7623_aud_ext_clk1_funcs[] = { 1, };
- 
- /* DISP PWM */
--static int mt7623_disp_pwm_0_pins[] = { 72, };
--static int mt7623_disp_pwm_0_funcs[] = { 5, };
--static int mt7623_disp_pwm_1_pins[] = { 203, };
--static int mt7623_disp_pwm_1_funcs[] = { 2, };
--static int mt7623_disp_pwm_2_pins[] = { 208, };
--static int mt7623_disp_pwm_2_funcs[] = { 5, };
-+static const int mt7623_disp_pwm_0_pins[] = { 72, };
-+static const int mt7623_disp_pwm_0_funcs[] = { 5, };
-+static const int mt7623_disp_pwm_1_pins[] = { 203, };
-+static const int mt7623_disp_pwm_1_funcs[] = { 2, };
-+static const int mt7623_disp_pwm_2_pins[] = { 208, };
-+static const int mt7623_disp_pwm_2_funcs[] = { 5, };
- 
- /* ESW */
--static int mt7623_esw_int_pins[] = { 273, };
--static int mt7623_esw_int_funcs[] = { 1, };
--static int mt7623_esw_rst_pins[] = { 277, };
--static int mt7623_esw_rst_funcs[] = { 1, };
-+static const int mt7623_esw_int_pins[] = { 273, };
-+static const int mt7623_esw_int_funcs[] = { 1, };
-+static const int mt7623_esw_rst_pins[] = { 277, };
-+static const int mt7623_esw_rst_funcs[] = { 1, };
- 
- /* EPHY */
--static int mt7623_ephy_pins[] = { 262, 263, 264, 265, 266, 267, 268,
--				  269, 270, 271, 272, 274, };
--static int mt7623_ephy_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
-+static const int mt7623_ephy_pins[] = { 262, 263, 264, 265, 266, 267, 268,
-+					269, 270, 271, 272, 274, };
-+static const int mt7623_ephy_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
- 
- /* EXT_SDIO */
--static int mt7623_ext_sdio_pins[] = { 236, 237, 238, 239, 240, 241, };
--static int mt7623_ext_sdio_funcs[] = { 1, 1, 1, 1, 1, 1, };
-+static const int mt7623_ext_sdio_pins[] = { 236, 237, 238, 239, 240, 241, };
-+static const int mt7623_ext_sdio_funcs[] = { 1, 1, 1, 1, 1, 1, };
- 
- /* HDMI RX */
--static int mt7623_hdmi_rx_pins[] = { 247, 248, };
--static int mt7623_hdmi_rx_funcs[] = { 1, 1 };
--static int mt7623_hdmi_rx_i2c_pins[] = { 244, 245, };
--static int mt7623_hdmi_rx_i2c_funcs[] = { 1, 1 };
-+static const int mt7623_hdmi_rx_pins[] = { 247, 248, };
-+static const int mt7623_hdmi_rx_funcs[] = { 1, 1 };
-+static const int mt7623_hdmi_rx_i2c_pins[] = { 244, 245, };
-+static const int mt7623_hdmi_rx_i2c_funcs[] = { 1, 1 };
- 
- /* HDMI TX */
--static int mt7623_hdmi_cec_pins[] = { 122, };
--static int mt7623_hdmi_cec_funcs[] = { 1, };
--static int mt7623_hdmi_htplg_pins[] = { 123, };
--static int mt7623_hdmi_htplg_funcs[] = { 1, };
--static int mt7623_hdmi_i2c_pins[] = { 124, 125, };
--static int mt7623_hdmi_i2c_funcs[] = { 1, 1 };
-+static const int mt7623_hdmi_cec_pins[] = { 122, };
-+static const int mt7623_hdmi_cec_funcs[] = { 1, };
-+static const int mt7623_hdmi_htplg_pins[] = { 123, };
-+static const int mt7623_hdmi_htplg_funcs[] = { 1, };
-+static const int mt7623_hdmi_i2c_pins[] = { 124, 125, };
-+static const int mt7623_hdmi_i2c_funcs[] = { 1, 1 };
- 
- /* I2C */
--static int mt7623_i2c0_pins[] = { 75, 76, };
--static int mt7623_i2c0_funcs[] = { 1, 1, };
--static int mt7623_i2c1_0_pins[] = { 57, 58, };
--static int mt7623_i2c1_0_funcs[] = { 1, 1, };
--static int mt7623_i2c1_1_pins[] = { 242, 243, };
--static int mt7623_i2c1_1_funcs[] = { 4, 4, };
--static int mt7623_i2c1_2_pins[] = { 85, 86, };
--static int mt7623_i2c1_2_funcs[] = { 3, 3, };
--static int mt7623_i2c1_3_pins[] = { 105, 106, };
--static int mt7623_i2c1_3_funcs[] = { 3, 3, };
--static int mt7623_i2c1_4_pins[] = { 124, 125, };
--static int mt7623_i2c1_4_funcs[] = { 4, 4, };
--static int mt7623_i2c2_0_pins[] = { 77, 78, };
--static int mt7623_i2c2_0_funcs[] = { 1, 1, };
--static int mt7623_i2c2_1_pins[] = { 89, 90, };
--static int mt7623_i2c2_1_funcs[] = { 3, 3, };
--static int mt7623_i2c2_2_pins[] = { 109, 110, };
--static int mt7623_i2c2_2_funcs[] = { 3, 3, };
--static int mt7623_i2c2_3_pins[] = { 122, 123, };
--static int mt7623_i2c2_3_funcs[] = { 4, 4, };
-+static const int mt7623_i2c0_pins[] = { 75, 76, };
-+static const int mt7623_i2c0_funcs[] = { 1, 1, };
-+static const int mt7623_i2c1_0_pins[] = { 57, 58, };
-+static const int mt7623_i2c1_0_funcs[] = { 1, 1, };
-+static const int mt7623_i2c1_1_pins[] = { 242, 243, };
-+static const int mt7623_i2c1_1_funcs[] = { 4, 4, };
-+static const int mt7623_i2c1_2_pins[] = { 85, 86, };
-+static const int mt7623_i2c1_2_funcs[] = { 3, 3, };
-+static const int mt7623_i2c1_3_pins[] = { 105, 106, };
-+static const int mt7623_i2c1_3_funcs[] = { 3, 3, };
-+static const int mt7623_i2c1_4_pins[] = { 124, 125, };
-+static const int mt7623_i2c1_4_funcs[] = { 4, 4, };
-+static const int mt7623_i2c2_0_pins[] = { 77, 78, };
-+static const int mt7623_i2c2_0_funcs[] = { 1, 1, };
-+static const int mt7623_i2c2_1_pins[] = { 89, 90, };
-+static const int mt7623_i2c2_1_funcs[] = { 3, 3, };
-+static const int mt7623_i2c2_2_pins[] = { 109, 110, };
-+static const int mt7623_i2c2_2_funcs[] = { 3, 3, };
-+static const int mt7623_i2c2_3_pins[] = { 122, 123, };
-+static const int mt7623_i2c2_3_funcs[] = { 4, 4, };
- 
- /* I2S */
--static int mt7623_i2s0_pins[] = { 49, 72, 73, 74, 126, };
--static int mt7623_i2s0_funcs[] = { 1, 1, 1, 1, 1, };
--static int mt7623_i2s1_pins[] = { 33, 34, 35, 36, 37, };
--static int mt7623_i2s1_funcs[] = { 1, 1, 1, 1, 1, };
--static int mt7623_i2s2_bclk_lrclk_mclk_pins[] = { 50, 52, 188, };
--static int mt7623_i2s2_bclk_lrclk_mclk_funcs[] = { 1, 1, 1, };
--static int mt7623_i2s2_data_in_pins[] = { 51, };
--static int mt7623_i2s2_data_in_funcs[] = { 1, };
--static int mt7623_i2s2_data_0_pins[] = { 203, };
--static int mt7623_i2s2_data_0_funcs[] = { 9, };
--static int mt7623_i2s2_data_1_pins[] = { 38,  };
--static int mt7623_i2s2_data_1_funcs[] = { 4, };
--static int mt7623_i2s3_bclk_lrclk_mclk_pins[] = { 191, 192, 193, };
--static int mt7623_i2s3_bclk_lrclk_mclk_funcs[] = { 1, 1, 1, };
--static int mt7623_i2s3_data_in_pins[] = { 190, };
--static int mt7623_i2s3_data_in_funcs[] = { 1, };
--static int mt7623_i2s3_data_0_pins[] = { 204, };
--static int mt7623_i2s3_data_0_funcs[] = { 9, };
--static int mt7623_i2s3_data_1_pins[] = { 2, };
--static int mt7623_i2s3_data_1_funcs[] = { 0, };
--static int mt7623_i2s4_pins[] = { 194, 195, 196, 197, 198, };
--static int mt7623_i2s4_funcs[] = { 1, 1, 1, 1, 1, };
--static int mt7623_i2s5_pins[] = { 16, 17, 30, 31, 32, };
--static int mt7623_i2s5_funcs[] = { 1, 1, 1, 1, 1, };
-+static const int mt7623_i2s0_pins[] = { 49, 72, 73, 74, 126, };
-+static const int mt7623_i2s0_funcs[] = { 1, 1, 1, 1, 1, };
-+static const int mt7623_i2s1_pins[] = { 33, 34, 35, 36, 37, };
-+static const int mt7623_i2s1_funcs[] = { 1, 1, 1, 1, 1, };
-+static const int mt7623_i2s2_bclk_lrclk_mclk_pins[] = { 50, 52, 188, };
-+static const int mt7623_i2s2_bclk_lrclk_mclk_funcs[] = { 1, 1, 1, };
-+static const int mt7623_i2s2_data_in_pins[] = { 51, };
-+static const int mt7623_i2s2_data_in_funcs[] = { 1, };
-+static const int mt7623_i2s2_data_0_pins[] = { 203, };
-+static const int mt7623_i2s2_data_0_funcs[] = { 9, };
-+static const int mt7623_i2s2_data_1_pins[] = { 38,  };
-+static const int mt7623_i2s2_data_1_funcs[] = { 4, };
-+static const int mt7623_i2s3_bclk_lrclk_mclk_pins[] = { 191, 192, 193, };
-+static const int mt7623_i2s3_bclk_lrclk_mclk_funcs[] = { 1, 1, 1, };
-+static const int mt7623_i2s3_data_in_pins[] = { 190, };
-+static const int mt7623_i2s3_data_in_funcs[] = { 1, };
-+static const int mt7623_i2s3_data_0_pins[] = { 204, };
-+static const int mt7623_i2s3_data_0_funcs[] = { 9, };
-+static const int mt7623_i2s3_data_1_pins[] = { 2, };
-+static const int mt7623_i2s3_data_1_funcs[] = { 0, };
-+static const int mt7623_i2s4_pins[] = { 194, 195, 196, 197, 198, };
-+static const int mt7623_i2s4_funcs[] = { 1, 1, 1, 1, 1, };
-+static const int mt7623_i2s5_pins[] = { 16, 17, 30, 31, 32, };
-+static const int mt7623_i2s5_funcs[] = { 1, 1, 1, 1, 1, };
- 
- /* IR */
--static int mt7623_ir_pins[] = { 46, };
--static int mt7623_ir_funcs[] = { 1, };
-+static const int mt7623_ir_pins[] = { 46, };
-+static const int mt7623_ir_funcs[] = { 1, };
- 
- /* LCD */
--static int mt7623_mipi_tx_pins[] = { 91, 92, 93, 94, 95, 96, 97, 98,
--				     99, 100, };
--static int mt7623_mipi_tx_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
--static int mt7623_dsi_te_pins[] = { 84, };
--static int mt7623_dsi_te_funcs[] = { 1, };
--static int mt7623_lcm_rst_pins[] = { 83, };
--static int mt7623_lcm_rst_funcs[] = { 1, };
-+static const int mt7623_mipi_tx_pins[] = { 91, 92, 93, 94, 95, 96, 97, 98,
-+					   99, 100, };
-+static const int mt7623_mipi_tx_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
-+static const int mt7623_dsi_te_pins[] = { 84, };
-+static const int mt7623_dsi_te_funcs[] = { 1, };
-+static const int mt7623_lcm_rst_pins[] = { 83, };
-+static const int mt7623_lcm_rst_funcs[] = { 1, };
- 
- /* MDC/MDIO */
--static int mt7623_mdc_mdio_pins[] = { 275, 276, };
--static int mt7623_mdc_mdio_funcs[] = { 1, 1, };
-+static const int mt7623_mdc_mdio_pins[] = { 275, 276, };
-+static const int mt7623_mdc_mdio_funcs[] = { 1, 1, };
- 
- /* MSDC */
--static int mt7623_msdc0_pins[] = { 111, 112, 113, 114, 115, 116, 117, 118,
--				   119, 120, 121, };
--static int mt7623_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
--static int mt7623_msdc1_pins[] = { 105, 106, 107, 108, 109, 110, };
--static int mt7623_msdc1_funcs[] = { 1, 1, 1, 1, 1, 1, };
--static int mt7623_msdc1_ins_pins[] = { 261, };
--static int mt7623_msdc1_ins_funcs[] = { 1, };
--static int mt7623_msdc1_wp_0_pins[] = { 29, };
--static int mt7623_msdc1_wp_0_funcs[] = { 1, };
--static int mt7623_msdc1_wp_1_pins[] = { 55, };
--static int mt7623_msdc1_wp_1_funcs[] = { 3, };
--static int mt7623_msdc1_wp_2_pins[] = { 209, };
--static int mt7623_msdc1_wp_2_funcs[] = { 2, };
--static int mt7623_msdc2_pins[] = { 85, 86, 87, 88, 89, 90, };
--static int mt7623_msdc2_funcs[] = { 1, 1, 1, 1, 1, 1, };
--static int mt7623_msdc3_pins[] = { 249, 250, 251, 252, 253, 254, 255, 256,
--				   257, 258, 259, 260, };
--static int mt7623_msdc3_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
-+static const int mt7623_msdc0_pins[] = { 111, 112, 113, 114, 115, 116, 117, 118,
-+					 119, 120, 121, };
-+static const int mt7623_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
-+static const int mt7623_msdc1_pins[] = { 105, 106, 107, 108, 109, 110, };
-+static const int mt7623_msdc1_funcs[] = { 1, 1, 1, 1, 1, 1, };
-+static const int mt7623_msdc1_ins_pins[] = { 261, };
-+static const int mt7623_msdc1_ins_funcs[] = { 1, };
-+static const int mt7623_msdc1_wp_0_pins[] = { 29, };
-+static const int mt7623_msdc1_wp_0_funcs[] = { 1, };
-+static const int mt7623_msdc1_wp_1_pins[] = { 55, };
-+static const int mt7623_msdc1_wp_1_funcs[] = { 3, };
-+static const int mt7623_msdc1_wp_2_pins[] = { 209, };
-+static const int mt7623_msdc1_wp_2_funcs[] = { 2, };
-+static const int mt7623_msdc2_pins[] = { 85, 86, 87, 88, 89, 90, };
-+static const int mt7623_msdc2_funcs[] = { 1, 1, 1, 1, 1, 1, };
-+static const int mt7623_msdc3_pins[] = { 249, 250, 251, 252, 253, 254, 255, 256,
-+					 257, 258, 259, 260, };
-+static const int mt7623_msdc3_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
- 
- /* NAND */
--static int mt7623_nandc_pins[] = { 43, 47, 48, 111, 112, 113, 114, 115,
--				   116, 117, 118, 119, 120, 121, };
--static int mt7623_nandc_funcs[] = { 1, 1, 1, 4, 4, 4, 4, 4, 4, 4, 4, 4,
--				   4, 4, };
--static int mt7623_nandc_ceb0_pins[] = { 45, };
--static int mt7623_nandc_ceb0_funcs[] = { 1, };
--static int mt7623_nandc_ceb1_pins[] = { 44, };
--static int mt7623_nandc_ceb1_funcs[] = { 1, };
-+static const int mt7623_nandc_pins[] = { 43, 47, 48, 111, 112, 113, 114, 115,
-+					 116, 117, 118, 119, 120, 121, };
-+static const int mt7623_nandc_funcs[] = { 1, 1, 1, 4, 4, 4, 4, 4, 4, 4, 4, 4,
-+					  4, 4, };
-+static const int mt7623_nandc_ceb0_pins[] = { 45, };
-+static const int mt7623_nandc_ceb0_funcs[] = { 1, };
-+static const int mt7623_nandc_ceb1_pins[] = { 44, };
-+static const int mt7623_nandc_ceb1_funcs[] = { 1, };
- 
- /* RTC */
--static int mt7623_rtc_pins[] = { 10, };
--static int mt7623_rtc_funcs[] = { 1, };
-+static const int mt7623_rtc_pins[] = { 10, };
-+static const int mt7623_rtc_funcs[] = { 1, };
- 
- /* OTG */
--static int mt7623_otg_iddig0_0_pins[] = { 29, };
--static int mt7623_otg_iddig0_0_funcs[] = { 1, };
--static int mt7623_otg_iddig0_1_pins[] = { 44, };
--static int mt7623_otg_iddig0_1_funcs[] = { 2, };
--static int mt7623_otg_iddig0_2_pins[] = { 236, };
--static int mt7623_otg_iddig0_2_funcs[] = { 2, };
--static int mt7623_otg_iddig1_0_pins[] = { 27, };
--static int mt7623_otg_iddig1_0_funcs[] = { 2, };
--static int mt7623_otg_iddig1_1_pins[] = { 47, };
--static int mt7623_otg_iddig1_1_funcs[] = { 2, };
--static int mt7623_otg_iddig1_2_pins[] = { 238, };
--static int mt7623_otg_iddig1_2_funcs[] = { 2, };
--static int mt7623_otg_drv_vbus0_0_pins[] = { 28, };
--static int mt7623_otg_drv_vbus0_0_funcs[] = { 1, };
--static int mt7623_otg_drv_vbus0_1_pins[] = { 45, };
--static int mt7623_otg_drv_vbus0_1_funcs[] = { 2, };
--static int mt7623_otg_drv_vbus0_2_pins[] = { 237, };
--static int mt7623_otg_drv_vbus0_2_funcs[] = { 2, };
--static int mt7623_otg_drv_vbus1_0_pins[] = { 26, };
--static int mt7623_otg_drv_vbus1_0_funcs[] = { 2, };
--static int mt7623_otg_drv_vbus1_1_pins[] = { 48, };
--static int mt7623_otg_drv_vbus1_1_funcs[] = { 2, };
--static int mt7623_otg_drv_vbus1_2_pins[] = { 239, };
--static int mt7623_otg_drv_vbus1_2_funcs[] = { 2, };
-+static const int mt7623_otg_iddig0_0_pins[] = { 29, };
-+static const int mt7623_otg_iddig0_0_funcs[] = { 1, };
-+static const int mt7623_otg_iddig0_1_pins[] = { 44, };
-+static const int mt7623_otg_iddig0_1_funcs[] = { 2, };
-+static const int mt7623_otg_iddig0_2_pins[] = { 236, };
-+static const int mt7623_otg_iddig0_2_funcs[] = { 2, };
-+static const int mt7623_otg_iddig1_0_pins[] = { 27, };
-+static const int mt7623_otg_iddig1_0_funcs[] = { 2, };
-+static const int mt7623_otg_iddig1_1_pins[] = { 47, };
-+static const int mt7623_otg_iddig1_1_funcs[] = { 2, };
-+static const int mt7623_otg_iddig1_2_pins[] = { 238, };
-+static const int mt7623_otg_iddig1_2_funcs[] = { 2, };
-+static const int mt7623_otg_drv_vbus0_0_pins[] = { 28, };
-+static const int mt7623_otg_drv_vbus0_0_funcs[] = { 1, };
-+static const int mt7623_otg_drv_vbus0_1_pins[] = { 45, };
-+static const int mt7623_otg_drv_vbus0_1_funcs[] = { 2, };
-+static const int mt7623_otg_drv_vbus0_2_pins[] = { 237, };
-+static const int mt7623_otg_drv_vbus0_2_funcs[] = { 2, };
-+static const int mt7623_otg_drv_vbus1_0_pins[] = { 26, };
-+static const int mt7623_otg_drv_vbus1_0_funcs[] = { 2, };
-+static const int mt7623_otg_drv_vbus1_1_pins[] = { 48, };
-+static const int mt7623_otg_drv_vbus1_1_funcs[] = { 2, };
-+static const int mt7623_otg_drv_vbus1_2_pins[] = { 239, };
-+static const int mt7623_otg_drv_vbus1_2_funcs[] = { 2, };
- 
- /* PCIE */
--static int mt7623_pcie0_0_perst_pins[] = { 208, };
--static int mt7623_pcie0_0_perst_funcs[] = { 3, };
--static int mt7623_pcie0_1_perst_pins[] = { 22, };
--static int mt7623_pcie0_1_perst_funcs[] = { 2, };
--static int mt7623_pcie1_0_perst_pins[] = { 209, };
--static int mt7623_pcie1_0_perst_funcs[] = { 3, };
--static int mt7623_pcie1_1_perst_pins[] = { 23, };
--static int mt7623_pcie1_1_perst_funcs[] = { 2, };
--static int mt7623_pcie2_0_perst_pins[] = { 24, };
--static int mt7623_pcie2_0_perst_funcs[] = { 2, };
--static int mt7623_pcie2_1_perst_pins[] = { 29, };
--static int mt7623_pcie2_1_perst_funcs[] = { 6, };
--static int mt7623_pcie0_0_wake_pins[] = { 28, };
--static int mt7623_pcie0_0_wake_funcs[] = { 6, };
--static int mt7623_pcie0_1_wake_pins[] = { 251, };
--static int mt7623_pcie0_1_wake_funcs[] = { 6, };
--static int mt7623_pcie1_0_wake_pins[] = { 27, };
--static int mt7623_pcie1_0_wake_funcs[] = { 6, };
--static int mt7623_pcie1_1_wake_pins[] = { 253, };
--static int mt7623_pcie1_1_wake_funcs[] = { 6, };
--static int mt7623_pcie2_0_wake_pins[] = { 26, };
--static int mt7623_pcie2_0_wake_funcs[] = { 6, };
--static int mt7623_pcie2_1_wake_pins[] = { 255, };
--static int mt7623_pcie2_1_wake_funcs[] = { 6, };
--static int mt7623_pcie0_clkreq_pins[] = { 250, };
--static int mt7623_pcie0_clkreq_funcs[] = { 6, };
--static int mt7623_pcie1_clkreq_pins[] = { 252, };
--static int mt7623_pcie1_clkreq_funcs[] = { 6, };
--static int mt7623_pcie2_clkreq_pins[] = { 254, };
--static int mt7623_pcie2_clkreq_funcs[] = { 6, };
-+static const int mt7623_pcie0_0_perst_pins[] = { 208, };
-+static const int mt7623_pcie0_0_perst_funcs[] = { 3, };
-+static const int mt7623_pcie0_1_perst_pins[] = { 22, };
-+static const int mt7623_pcie0_1_perst_funcs[] = { 2, };
-+static const int mt7623_pcie1_0_perst_pins[] = { 209, };
-+static const int mt7623_pcie1_0_perst_funcs[] = { 3, };
-+static const int mt7623_pcie1_1_perst_pins[] = { 23, };
-+static const int mt7623_pcie1_1_perst_funcs[] = { 2, };
-+static const int mt7623_pcie2_0_perst_pins[] = { 24, };
-+static const int mt7623_pcie2_0_perst_funcs[] = { 2, };
-+static const int mt7623_pcie2_1_perst_pins[] = { 29, };
-+static const int mt7623_pcie2_1_perst_funcs[] = { 6, };
-+static const int mt7623_pcie0_0_wake_pins[] = { 28, };
-+static const int mt7623_pcie0_0_wake_funcs[] = { 6, };
-+static const int mt7623_pcie0_1_wake_pins[] = { 251, };
-+static const int mt7623_pcie0_1_wake_funcs[] = { 6, };
-+static const int mt7623_pcie1_0_wake_pins[] = { 27, };
-+static const int mt7623_pcie1_0_wake_funcs[] = { 6, };
-+static const int mt7623_pcie1_1_wake_pins[] = { 253, };
-+static const int mt7623_pcie1_1_wake_funcs[] = { 6, };
-+static const int mt7623_pcie2_0_wake_pins[] = { 26, };
-+static const int mt7623_pcie2_0_wake_funcs[] = { 6, };
-+static const int mt7623_pcie2_1_wake_pins[] = { 255, };
-+static const int mt7623_pcie2_1_wake_funcs[] = { 6, };
-+static const int mt7623_pcie0_clkreq_pins[] = { 250, };
-+static const int mt7623_pcie0_clkreq_funcs[] = { 6, };
-+static const int mt7623_pcie1_clkreq_pins[] = { 252, };
-+static const int mt7623_pcie1_clkreq_funcs[] = { 6, };
-+static const int mt7623_pcie2_clkreq_pins[] = { 254, };
-+static const int mt7623_pcie2_clkreq_funcs[] = { 6, };
- /* the pcie_*_rev are only used for MT7623 */
--static int mt7623_pcie0_0_rev_perst_pins[] = { 208, };
--static int mt7623_pcie0_0_rev_perst_funcs[] = { 11, };
--static int mt7623_pcie0_1_rev_perst_pins[] = { 22, };
--static int mt7623_pcie0_1_rev_perst_funcs[] = { 10, };
--static int mt7623_pcie1_0_rev_perst_pins[] = { 209, };
--static int mt7623_pcie1_0_rev_perst_funcs[] = { 11, };
--static int mt7623_pcie1_1_rev_perst_pins[] = { 23, };
--static int mt7623_pcie1_1_rev_perst_funcs[] = { 10, };
--static int mt7623_pcie2_0_rev_perst_pins[] = { 24, };
--static int mt7623_pcie2_0_rev_perst_funcs[] = { 11, };
--static int mt7623_pcie2_1_rev_perst_pins[] = { 29, };
--static int mt7623_pcie2_1_rev_perst_funcs[] = { 14, };
-+static const int mt7623_pcie0_0_rev_perst_pins[] = { 208, };
-+static const int mt7623_pcie0_0_rev_perst_funcs[] = { 11, };
-+static const int mt7623_pcie0_1_rev_perst_pins[] = { 22, };
-+static const int mt7623_pcie0_1_rev_perst_funcs[] = { 10, };
-+static const int mt7623_pcie1_0_rev_perst_pins[] = { 209, };
-+static const int mt7623_pcie1_0_rev_perst_funcs[] = { 11, };
-+static const int mt7623_pcie1_1_rev_perst_pins[] = { 23, };
-+static const int mt7623_pcie1_1_rev_perst_funcs[] = { 10, };
-+static const int mt7623_pcie2_0_rev_perst_pins[] = { 24, };
-+static const int mt7623_pcie2_0_rev_perst_funcs[] = { 11, };
-+static const int mt7623_pcie2_1_rev_perst_pins[] = { 29, };
-+static const int mt7623_pcie2_1_rev_perst_funcs[] = { 14, };
- 
- /* PCM */
--static int mt7623_pcm_clk_0_pins[] = { 18, };
--static int mt7623_pcm_clk_0_funcs[] = { 1, };
--static int mt7623_pcm_clk_1_pins[] = { 17, };
--static int mt7623_pcm_clk_1_funcs[] = { 3, };
--static int mt7623_pcm_clk_2_pins[] = { 35, };
--static int mt7623_pcm_clk_2_funcs[] = { 3, };
--static int mt7623_pcm_clk_3_pins[] = { 50, };
--static int mt7623_pcm_clk_3_funcs[] = { 3, };
--static int mt7623_pcm_clk_4_pins[] = { 74, };
--static int mt7623_pcm_clk_4_funcs[] = { 3, };
--static int mt7623_pcm_clk_5_pins[] = { 191, };
--static int mt7623_pcm_clk_5_funcs[] = { 3, };
--static int mt7623_pcm_clk_6_pins[] = { 196, };
--static int mt7623_pcm_clk_6_funcs[] = { 3, };
--static int mt7623_pcm_sync_0_pins[] = { 19, };
--static int mt7623_pcm_sync_0_funcs[] = { 1, };
--static int mt7623_pcm_sync_1_pins[] = { 30, };
--static int mt7623_pcm_sync_1_funcs[] = { 3, };
--static int mt7623_pcm_sync_2_pins[] = { 36, };
--static int mt7623_pcm_sync_2_funcs[] = { 3, };
--static int mt7623_pcm_sync_3_pins[] = { 52, };
--static int mt7623_pcm_sync_3_funcs[] = { 31, };
--static int mt7623_pcm_sync_4_pins[] = { 73, };
--static int mt7623_pcm_sync_4_funcs[] = { 3, };
--static int mt7623_pcm_sync_5_pins[] = { 192, };
--static int mt7623_pcm_sync_5_funcs[] = { 3, };
--static int mt7623_pcm_sync_6_pins[] = { 197, };
--static int mt7623_pcm_sync_6_funcs[] = { 3, };
--static int mt7623_pcm_rx_0_pins[] = { 20, };
--static int mt7623_pcm_rx_0_funcs[] = { 1, };
--static int mt7623_pcm_rx_1_pins[] = { 16, };
--static int mt7623_pcm_rx_1_funcs[] = { 3, };
--static int mt7623_pcm_rx_2_pins[] = { 34, };
--static int mt7623_pcm_rx_2_funcs[] = { 3, };
--static int mt7623_pcm_rx_3_pins[] = { 51, };
--static int mt7623_pcm_rx_3_funcs[] = { 3, };
--static int mt7623_pcm_rx_4_pins[] = { 72, };
--static int mt7623_pcm_rx_4_funcs[] = { 3, };
--static int mt7623_pcm_rx_5_pins[] = { 190, };
--static int mt7623_pcm_rx_5_funcs[] = { 3, };
--static int mt7623_pcm_rx_6_pins[] = { 195, };
--static int mt7623_pcm_rx_6_funcs[] = { 3, };
--static int mt7623_pcm_tx_0_pins[] = { 21, };
--static int mt7623_pcm_tx_0_funcs[] = { 1, };
--static int mt7623_pcm_tx_1_pins[] = { 32, };
--static int mt7623_pcm_tx_1_funcs[] = { 3, };
--static int mt7623_pcm_tx_2_pins[] = { 33, };
--static int mt7623_pcm_tx_2_funcs[] = { 3, };
--static int mt7623_pcm_tx_3_pins[] = { 38, };
--static int mt7623_pcm_tx_3_funcs[] = { 3, };
--static int mt7623_pcm_tx_4_pins[] = { 49, };
--static int mt7623_pcm_tx_4_funcs[] = { 3, };
--static int mt7623_pcm_tx_5_pins[] = { 189, };
--static int mt7623_pcm_tx_5_funcs[] = { 3, };
--static int mt7623_pcm_tx_6_pins[] = { 194, };
--static int mt7623_pcm_tx_6_funcs[] = { 3, };
-+static const int mt7623_pcm_clk_0_pins[] = { 18, };
-+static const int mt7623_pcm_clk_0_funcs[] = { 1, };
-+static const int mt7623_pcm_clk_1_pins[] = { 17, };
-+static const int mt7623_pcm_clk_1_funcs[] = { 3, };
-+static const int mt7623_pcm_clk_2_pins[] = { 35, };
-+static const int mt7623_pcm_clk_2_funcs[] = { 3, };
-+static const int mt7623_pcm_clk_3_pins[] = { 50, };
-+static const int mt7623_pcm_clk_3_funcs[] = { 3, };
-+static const int mt7623_pcm_clk_4_pins[] = { 74, };
-+static const int mt7623_pcm_clk_4_funcs[] = { 3, };
-+static const int mt7623_pcm_clk_5_pins[] = { 191, };
-+static const int mt7623_pcm_clk_5_funcs[] = { 3, };
-+static const int mt7623_pcm_clk_6_pins[] = { 196, };
-+static const int mt7623_pcm_clk_6_funcs[] = { 3, };
-+static const int mt7623_pcm_sync_0_pins[] = { 19, };
-+static const int mt7623_pcm_sync_0_funcs[] = { 1, };
-+static const int mt7623_pcm_sync_1_pins[] = { 30, };
-+static const int mt7623_pcm_sync_1_funcs[] = { 3, };
-+static const int mt7623_pcm_sync_2_pins[] = { 36, };
-+static const int mt7623_pcm_sync_2_funcs[] = { 3, };
-+static const int mt7623_pcm_sync_3_pins[] = { 52, };
-+static const int mt7623_pcm_sync_3_funcs[] = { 31, };
-+static const int mt7623_pcm_sync_4_pins[] = { 73, };
-+static const int mt7623_pcm_sync_4_funcs[] = { 3, };
-+static const int mt7623_pcm_sync_5_pins[] = { 192, };
-+static const int mt7623_pcm_sync_5_funcs[] = { 3, };
-+static const int mt7623_pcm_sync_6_pins[] = { 197, };
-+static const int mt7623_pcm_sync_6_funcs[] = { 3, };
-+static const int mt7623_pcm_rx_0_pins[] = { 20, };
-+static const int mt7623_pcm_rx_0_funcs[] = { 1, };
-+static const int mt7623_pcm_rx_1_pins[] = { 16, };
-+static const int mt7623_pcm_rx_1_funcs[] = { 3, };
-+static const int mt7623_pcm_rx_2_pins[] = { 34, };
-+static const int mt7623_pcm_rx_2_funcs[] = { 3, };
-+static const int mt7623_pcm_rx_3_pins[] = { 51, };
-+static const int mt7623_pcm_rx_3_funcs[] = { 3, };
-+static const int mt7623_pcm_rx_4_pins[] = { 72, };
-+static const int mt7623_pcm_rx_4_funcs[] = { 3, };
-+static const int mt7623_pcm_rx_5_pins[] = { 190, };
-+static const int mt7623_pcm_rx_5_funcs[] = { 3, };
-+static const int mt7623_pcm_rx_6_pins[] = { 195, };
-+static const int mt7623_pcm_rx_6_funcs[] = { 3, };
-+static const int mt7623_pcm_tx_0_pins[] = { 21, };
-+static const int mt7623_pcm_tx_0_funcs[] = { 1, };
-+static const int mt7623_pcm_tx_1_pins[] = { 32, };
-+static const int mt7623_pcm_tx_1_funcs[] = { 3, };
-+static const int mt7623_pcm_tx_2_pins[] = { 33, };
-+static const int mt7623_pcm_tx_2_funcs[] = { 3, };
-+static const int mt7623_pcm_tx_3_pins[] = { 38, };
-+static const int mt7623_pcm_tx_3_funcs[] = { 3, };
-+static const int mt7623_pcm_tx_4_pins[] = { 49, };
-+static const int mt7623_pcm_tx_4_funcs[] = { 3, };
-+static const int mt7623_pcm_tx_5_pins[] = { 189, };
-+static const int mt7623_pcm_tx_5_funcs[] = { 3, };
-+static const int mt7623_pcm_tx_6_pins[] = { 194, };
-+static const int mt7623_pcm_tx_6_funcs[] = { 3, };
- 
- /* PWM */
--static int mt7623_pwm_ch1_0_pins[] = { 203, };
--static int mt7623_pwm_ch1_0_funcs[] = { 1, };
--static int mt7623_pwm_ch1_1_pins[] = { 208, };
--static int mt7623_pwm_ch1_1_funcs[] = { 2, };
--static int mt7623_pwm_ch1_2_pins[] = { 72, };
--static int mt7623_pwm_ch1_2_funcs[] = { 4, };
--static int mt7623_pwm_ch1_3_pins[] = { 88, };
--static int mt7623_pwm_ch1_3_funcs[] = { 3, };
--static int mt7623_pwm_ch1_4_pins[] = { 108, };
--static int mt7623_pwm_ch1_4_funcs[] = { 3, };
--static int mt7623_pwm_ch2_0_pins[] = { 204, };
--static int mt7623_pwm_ch2_0_funcs[] = { 1, };
--static int mt7623_pwm_ch2_1_pins[] = { 53, };
--static int mt7623_pwm_ch2_1_funcs[] = { 5, };
--static int mt7623_pwm_ch2_2_pins[] = { 88, };
--static int mt7623_pwm_ch2_2_funcs[] = { 6, };
--static int mt7623_pwm_ch2_3_pins[] = { 108, };
--static int mt7623_pwm_ch2_3_funcs[] = { 6, };
--static int mt7623_pwm_ch2_4_pins[] = { 209, };
--static int mt7623_pwm_ch2_4_funcs[] = { 5, };
--static int mt7623_pwm_ch3_0_pins[] = { 205, };
--static int mt7623_pwm_ch3_0_funcs[] = { 1, };
--static int mt7623_pwm_ch3_1_pins[] = { 55, };
--static int mt7623_pwm_ch3_1_funcs[] = { 5, };
--static int mt7623_pwm_ch3_2_pins[] = { 89, };
--static int mt7623_pwm_ch3_2_funcs[] = { 6, };
--static int mt7623_pwm_ch3_3_pins[] = { 109, };
--static int mt7623_pwm_ch3_3_funcs[] = { 6, };
--static int mt7623_pwm_ch4_0_pins[] = { 206, };
--static int mt7623_pwm_ch4_0_funcs[] = { 1, };
--static int mt7623_pwm_ch4_1_pins[] = { 90, };
--static int mt7623_pwm_ch4_1_funcs[] = { 6, };
--static int mt7623_pwm_ch4_2_pins[] = { 110, };
--static int mt7623_pwm_ch4_2_funcs[] = { 6, };
--static int mt7623_pwm_ch4_3_pins[] = { 124, };
--static int mt7623_pwm_ch4_3_funcs[] = { 5, };
--static int mt7623_pwm_ch5_0_pins[] = { 207, };
--static int mt7623_pwm_ch5_0_funcs[] = { 1, };
--static int mt7623_pwm_ch5_1_pins[] = { 125, };
--static int mt7623_pwm_ch5_1_funcs[] = { 5, };
-+static const int mt7623_pwm_ch1_0_pins[] = { 203, };
-+static const int mt7623_pwm_ch1_0_funcs[] = { 1, };
-+static const int mt7623_pwm_ch1_1_pins[] = { 208, };
-+static const int mt7623_pwm_ch1_1_funcs[] = { 2, };
-+static const int mt7623_pwm_ch1_2_pins[] = { 72, };
-+static const int mt7623_pwm_ch1_2_funcs[] = { 4, };
-+static const int mt7623_pwm_ch1_3_pins[] = { 88, };
-+static const int mt7623_pwm_ch1_3_funcs[] = { 3, };
-+static const int mt7623_pwm_ch1_4_pins[] = { 108, };
-+static const int mt7623_pwm_ch1_4_funcs[] = { 3, };
-+static const int mt7623_pwm_ch2_0_pins[] = { 204, };
-+static const int mt7623_pwm_ch2_0_funcs[] = { 1, };
-+static const int mt7623_pwm_ch2_1_pins[] = { 53, };
-+static const int mt7623_pwm_ch2_1_funcs[] = { 5, };
-+static const int mt7623_pwm_ch2_2_pins[] = { 88, };
-+static const int mt7623_pwm_ch2_2_funcs[] = { 6, };
-+static const int mt7623_pwm_ch2_3_pins[] = { 108, };
-+static const int mt7623_pwm_ch2_3_funcs[] = { 6, };
-+static const int mt7623_pwm_ch2_4_pins[] = { 209, };
-+static const int mt7623_pwm_ch2_4_funcs[] = { 5, };
-+static const int mt7623_pwm_ch3_0_pins[] = { 205, };
-+static const int mt7623_pwm_ch3_0_funcs[] = { 1, };
-+static const int mt7623_pwm_ch3_1_pins[] = { 55, };
-+static const int mt7623_pwm_ch3_1_funcs[] = { 5, };
-+static const int mt7623_pwm_ch3_2_pins[] = { 89, };
-+static const int mt7623_pwm_ch3_2_funcs[] = { 6, };
-+static const int mt7623_pwm_ch3_3_pins[] = { 109, };
-+static const int mt7623_pwm_ch3_3_funcs[] = { 6, };
-+static const int mt7623_pwm_ch4_0_pins[] = { 206, };
-+static const int mt7623_pwm_ch4_0_funcs[] = { 1, };
-+static const int mt7623_pwm_ch4_1_pins[] = { 90, };
-+static const int mt7623_pwm_ch4_1_funcs[] = { 6, };
-+static const int mt7623_pwm_ch4_2_pins[] = { 110, };
-+static const int mt7623_pwm_ch4_2_funcs[] = { 6, };
-+static const int mt7623_pwm_ch4_3_pins[] = { 124, };
-+static const int mt7623_pwm_ch4_3_funcs[] = { 5, };
-+static const int mt7623_pwm_ch5_0_pins[] = { 207, };
-+static const int mt7623_pwm_ch5_0_funcs[] = { 1, };
-+static const int mt7623_pwm_ch5_1_pins[] = { 125, };
-+static const int mt7623_pwm_ch5_1_funcs[] = { 5, };
- 
- /* PWRAP */
--static int mt7623_pwrap_pins[] = { 0, 1, 2, 3, 4, 5, 6, };
--static int mt7623_pwrap_funcs[] = { 1, 1, 1, 1, 1, 1, 1, };
-+static const int mt7623_pwrap_pins[] = { 0, 1, 2, 3, 4, 5, 6, };
-+static const int mt7623_pwrap_funcs[] = { 1, 1, 1, 1, 1, 1, 1, };
- 
- /* SPDIF */
--static int mt7623_spdif_in0_0_pins[] = { 56, };
--static int mt7623_spdif_in0_0_funcs[] = { 3, };
--static int mt7623_spdif_in0_1_pins[] = { 201, };
--static int mt7623_spdif_in0_1_funcs[] = { 1, };
--static int mt7623_spdif_in1_0_pins[] = { 54, };
--static int mt7623_spdif_in1_0_funcs[] = { 3, };
--static int mt7623_spdif_in1_1_pins[] = { 202, };
--static int mt7623_spdif_in1_1_funcs[] = { 1, };
--static int mt7623_spdif_out_pins[] = { 202, };
--static int mt7623_spdif_out_funcs[] = { 1, };
-+static const int mt7623_spdif_in0_0_pins[] = { 56, };
-+static const int mt7623_spdif_in0_0_funcs[] = { 3, };
-+static const int mt7623_spdif_in0_1_pins[] = { 201, };
-+static const int mt7623_spdif_in0_1_funcs[] = { 1, };
-+static const int mt7623_spdif_in1_0_pins[] = { 54, };
-+static const int mt7623_spdif_in1_0_funcs[] = { 3, };
-+static const int mt7623_spdif_in1_1_pins[] = { 202, };
-+static const int mt7623_spdif_in1_1_funcs[] = { 1, };
-+static const int mt7623_spdif_out_pins[] = { 202, };
-+static const int mt7623_spdif_out_funcs[] = { 1, };
- 
- /* SPI */
--static int mt7623_spi0_pins[] = { 53, 54, 55, 56, };
--static int mt7623_spi0_funcs[] = { 1, 1, 1, 1, };
--static int mt7623_spi1_pins[] = { 7, 199, 8, 9, };
--static int mt7623_spi1_funcs[] = { 1, 1, 1, 1, };
--static int mt7623_spi2_pins[] = { 101, 104, 102, 103, };
--static int mt7623_spi2_funcs[] = { 1, 1, 1, 1, };
-+static const int mt7623_spi0_pins[] = { 53, 54, 55, 56, };
-+static const int mt7623_spi0_funcs[] = { 1, 1, 1, 1, };
-+static const int mt7623_spi1_pins[] = { 7, 199, 8, 9, };
-+static const int mt7623_spi1_funcs[] = { 1, 1, 1, 1, };
-+static const int mt7623_spi2_pins[] = { 101, 104, 102, 103, };
-+static const int mt7623_spi2_funcs[] = { 1, 1, 1, 1, };
- 
- /* UART */
--static int mt7623_uart0_0_txd_rxd_pins[] = { 79, 80, };
--static int mt7623_uart0_0_txd_rxd_funcs[] = { 1, 1, };
--static int mt7623_uart0_1_txd_rxd_pins[] = { 87, 88, };
--static int mt7623_uart0_1_txd_rxd_funcs[] = { 5, 5, };
--static int mt7623_uart0_2_txd_rxd_pins[] = { 107, 108, };
--static int mt7623_uart0_2_txd_rxd_funcs[] = { 5, 5, };
--static int mt7623_uart0_3_txd_rxd_pins[] = { 123, 122, };
--static int mt7623_uart0_3_txd_rxd_funcs[] = { 5, 5, };
--static int mt7623_uart0_rts_cts_pins[] = { 22, 23, };
--static int mt7623_uart0_rts_cts_funcs[] = { 1, 1, };
--static int mt7623_uart1_0_txd_rxd_pins[] = { 81, 82, };
--static int mt7623_uart1_0_txd_rxd_funcs[] = { 1, 1, };
--static int mt7623_uart1_1_txd_rxd_pins[] = { 89, 90, };
--static int mt7623_uart1_1_txd_rxd_funcs[] = { 5, 5, };
--static int mt7623_uart1_2_txd_rxd_pins[] = { 109, 110, };
--static int mt7623_uart1_2_txd_rxd_funcs[] = { 5, 5, };
--static int mt7623_uart1_rts_cts_pins[] = { 24, 25, };
--static int mt7623_uart1_rts_cts_funcs[] = { 1, 1, };
--static int mt7623_uart2_0_txd_rxd_pins[] = { 14, 15, };
--static int mt7623_uart2_0_txd_rxd_funcs[] = { 1, 1, };
--static int mt7623_uart2_1_txd_rxd_pins[] = { 200, 201, };
--static int mt7623_uart2_1_txd_rxd_funcs[] = { 6, 6, };
--static int mt7623_uart2_rts_cts_pins[] = { 242, 243, };
--static int mt7623_uart2_rts_cts_funcs[] = { 1, 1, };
--static int mt7623_uart3_txd_rxd_pins[] = { 242, 243, };
--static int mt7623_uart3_txd_rxd_funcs[] = { 2, 2, };
--static int mt7623_uart3_rts_cts_pins[] = { 26, 27, };
--static int mt7623_uart3_rts_cts_funcs[] = { 1, 1, };
-+static const int mt7623_uart0_0_txd_rxd_pins[] = { 79, 80, };
-+static const int mt7623_uart0_0_txd_rxd_funcs[] = { 1, 1, };
-+static const int mt7623_uart0_1_txd_rxd_pins[] = { 87, 88, };
-+static const int mt7623_uart0_1_txd_rxd_funcs[] = { 5, 5, };
-+static const int mt7623_uart0_2_txd_rxd_pins[] = { 107, 108, };
-+static const int mt7623_uart0_2_txd_rxd_funcs[] = { 5, 5, };
-+static const int mt7623_uart0_3_txd_rxd_pins[] = { 123, 122, };
-+static const int mt7623_uart0_3_txd_rxd_funcs[] = { 5, 5, };
-+static const int mt7623_uart0_rts_cts_pins[] = { 22, 23, };
-+static const int mt7623_uart0_rts_cts_funcs[] = { 1, 1, };
-+static const int mt7623_uart1_0_txd_rxd_pins[] = { 81, 82, };
-+static const int mt7623_uart1_0_txd_rxd_funcs[] = { 1, 1, };
-+static const int mt7623_uart1_1_txd_rxd_pins[] = { 89, 90, };
-+static const int mt7623_uart1_1_txd_rxd_funcs[] = { 5, 5, };
-+static const int mt7623_uart1_2_txd_rxd_pins[] = { 109, 110, };
-+static const int mt7623_uart1_2_txd_rxd_funcs[] = { 5, 5, };
-+static const int mt7623_uart1_rts_cts_pins[] = { 24, 25, };
-+static const int mt7623_uart1_rts_cts_funcs[] = { 1, 1, };
-+static const int mt7623_uart2_0_txd_rxd_pins[] = { 14, 15, };
-+static const int mt7623_uart2_0_txd_rxd_funcs[] = { 1, 1, };
-+static const int mt7623_uart2_1_txd_rxd_pins[] = { 200, 201, };
-+static const int mt7623_uart2_1_txd_rxd_funcs[] = { 6, 6, };
-+static const int mt7623_uart2_rts_cts_pins[] = { 242, 243, };
-+static const int mt7623_uart2_rts_cts_funcs[] = { 1, 1, };
-+static const int mt7623_uart3_txd_rxd_pins[] = { 242, 243, };
-+static const int mt7623_uart3_txd_rxd_funcs[] = { 2, 2, };
-+static const int mt7623_uart3_rts_cts_pins[] = { 26, 27, };
-+static const int mt7623_uart3_rts_cts_funcs[] = { 1, 1, };
- 
- /* Watchdog */
--static int mt7623_watchdog_0_pins[] = { 11, };
--static int mt7623_watchdog_0_funcs[] = { 1, };
--static int mt7623_watchdog_1_pins[] = { 121, };
--static int mt7623_watchdog_1_funcs[] = { 5, };
-+static const int mt7623_watchdog_0_pins[] = { 11, };
-+static const int mt7623_watchdog_0_funcs[] = { 1, };
-+static const int mt7623_watchdog_1_pins[] = { 121, };
-+static const int mt7623_watchdog_1_funcs[] = { 5, };
- 
- static const struct mtk_group_desc mt7623_groups[] = {
- 	PINCTRL_PIN_GROUP("aud_ext_clk0", mt7623_aud_ext_clk0),
-@@ -1362,7 +1362,7 @@ static const struct mtk_function_desc mt
- 	{"watchdog", mt7623_wdt_groups, ARRAY_SIZE(mt7623_wdt_groups)},
- };
- 
--static struct mtk_pinctrl_soc mt7623_data = {
-+static const struct mtk_pinctrl_soc mt7623_data = {
- 	.name = "mt7623_pinctrl",
- 	.reg_cal = mt7623_reg_cals,
- 	.pins = mt7623_pins,
---- a/drivers/pinctrl/mediatek/pinctrl-mt7629.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt7629.c
-@@ -180,118 +180,118 @@ static const struct mtk_pin_desc mt7629_
-  */
- 
- /* WF 5G */
--static int mt7629_wf0_5g_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, };
--static int mt7629_wf0_5g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
-+static const int mt7629_wf0_5g_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, };
-+static const int mt7629_wf0_5g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
- 
- /* LED for EPHY */
--static int mt7629_ephy_leds_pins[] = { 12, 13, 14, 15, 16, 17, 18, };
--static int mt7629_ephy_leds_funcs[] = { 1, 1, 1, 1, 1, 1, 1, };
--static int mt7629_ephy_led0_pins[] = { 12, };
--static int mt7629_ephy_led0_funcs[] = { 1, };
--static int mt7629_ephy_led1_pins[] = { 13, };
--static int mt7629_ephy_led1_funcs[] = { 1, };
--static int mt7629_ephy_led2_pins[] = { 14, };
--static int mt7629_ephy_led2_funcs[] = { 1, };
--static int mt7629_ephy_led3_pins[] = { 15, };
--static int mt7629_ephy_led3_funcs[] = { 1, };
--static int mt7629_ephy_led4_pins[] = { 16, };
--static int mt7629_ephy_led4_funcs[] = { 1, };
--static int mt7629_wf2g_led_pins[] = { 17, };
--static int mt7629_wf2g_led_funcs[] = { 1, };
--static int mt7629_wf5g_led_pins[] = { 18, };
--static int mt7629_wf5g_led_funcs[] = { 1, };
-+static const int mt7629_ephy_leds_pins[] = { 12, 13, 14, 15, 16, 17, 18, };
-+static const int mt7629_ephy_leds_funcs[] = { 1, 1, 1, 1, 1, 1, 1, };
-+static const int mt7629_ephy_led0_pins[] = { 12, };
-+static const int mt7629_ephy_led0_funcs[] = { 1, };
-+static const int mt7629_ephy_led1_pins[] = { 13, };
-+static const int mt7629_ephy_led1_funcs[] = { 1, };
-+static const int mt7629_ephy_led2_pins[] = { 14, };
-+static const int mt7629_ephy_led2_funcs[] = { 1, };
-+static const int mt7629_ephy_led3_pins[] = { 15, };
-+static const int mt7629_ephy_led3_funcs[] = { 1, };
-+static const int mt7629_ephy_led4_pins[] = { 16, };
-+static const int mt7629_ephy_led4_funcs[] = { 1, };
-+static const int mt7629_wf2g_led_pins[] = { 17, };
-+static const int mt7629_wf2g_led_funcs[] = { 1, };
-+static const int mt7629_wf5g_led_pins[] = { 18, };
-+static const int mt7629_wf5g_led_funcs[] = { 1, };
- 
- /* LED for EPHY used as JTAG */
--static int mt7629_ephy_leds_jtag_pins[] = { 12, 13, 14, 15, 16, };
--static int mt7629_ephy_leds_jtag_funcs[] = { 7, 7, 7, 7, 7, };
-+static const int mt7629_ephy_leds_jtag_pins[] = { 12, 13, 14, 15, 16, };
-+static const int mt7629_ephy_leds_jtag_funcs[] = { 7, 7, 7, 7, 7, };
- 
- /* Watchdog */
--static int mt7629_watchdog_pins[] = { 11, };
--static int mt7629_watchdog_funcs[] = { 1, };
-+static const int mt7629_watchdog_pins[] = { 11, };
-+static const int mt7629_watchdog_funcs[] = { 1, };
- 
- /* LED for GPHY */
--static int mt7629_gphy_leds_0_pins[] = { 21, 22, 23, };
--static int mt7629_gphy_leds_0_funcs[] = { 2, 2, 2, };
--static int mt7629_gphy_led1_0_pins[] = { 21, };
--static int mt7629_gphy_led1_0_funcs[] = { 2, };
--static int mt7629_gphy_led2_0_pins[] = { 22, };
--static int mt7629_gphy_led2_0_funcs[] = { 2, };
--static int mt7629_gphy_led3_0_pins[] = { 23, };
--static int mt7629_gphy_led3_0_funcs[] = { 2, };
--static int mt7629_gphy_leds_1_pins[] = { 57, 58, 59, };
--static int mt7629_gphy_leds_1_funcs[] = { 1, 1, 1, };
--static int mt7629_gphy_led1_1_pins[] = { 57, };
--static int mt7629_gphy_led1_1_funcs[] = { 1, };
--static int mt7629_gphy_led2_1_pins[] = { 58, };
--static int mt7629_gphy_led2_1_funcs[] = { 1, };
--static int mt7629_gphy_led3_1_pins[] = { 59, };
--static int mt7629_gphy_led3_1_funcs[] = { 1, };
-+static const int mt7629_gphy_leds_0_pins[] = { 21, 22, 23, };
-+static const int mt7629_gphy_leds_0_funcs[] = { 2, 2, 2, };
-+static const int mt7629_gphy_led1_0_pins[] = { 21, };
-+static const int mt7629_gphy_led1_0_funcs[] = { 2, };
-+static const int mt7629_gphy_led2_0_pins[] = { 22, };
-+static const int mt7629_gphy_led2_0_funcs[] = { 2, };
-+static const int mt7629_gphy_led3_0_pins[] = { 23, };
-+static const int mt7629_gphy_led3_0_funcs[] = { 2, };
-+static const int mt7629_gphy_leds_1_pins[] = { 57, 58, 59, };
-+static const int mt7629_gphy_leds_1_funcs[] = { 1, 1, 1, };
-+static const int mt7629_gphy_led1_1_pins[] = { 57, };
-+static const int mt7629_gphy_led1_1_funcs[] = { 1, };
-+static const int mt7629_gphy_led2_1_pins[] = { 58, };
-+static const int mt7629_gphy_led2_1_funcs[] = { 1, };
-+static const int mt7629_gphy_led3_1_pins[] = { 59, };
-+static const int mt7629_gphy_led3_1_funcs[] = { 1, };
- 
- /* I2C */
--static int mt7629_i2c_0_pins[] = { 19, 20, };
--static int mt7629_i2c_0_funcs[] = { 1, 1, };
--static int mt7629_i2c_1_pins[] = { 53, 54, };
--static int mt7629_i2c_1_funcs[] = { 1, 1, };
-+static const int mt7629_i2c_0_pins[] = { 19, 20, };
-+static const int mt7629_i2c_0_funcs[] = { 1, 1, };
-+static const int mt7629_i2c_1_pins[] = { 53, 54, };
-+static const int mt7629_i2c_1_funcs[] = { 1, 1, };
- 
- /* SPI */
--static int mt7629_spi_0_pins[] = { 21, 22, 23, 24, };
--static int mt7629_spi_0_funcs[] = { 1, 1, 1, 1, };
--static int mt7629_spi_1_pins[] = { 62, 63, 64, 65, };
--static int mt7629_spi_1_funcs[] = { 1, 1, 1, 1, };
--static int mt7629_spi_wp_pins[] = { 66, };
--static int mt7629_spi_wp_funcs[] = { 1, };
--static int mt7629_spi_hold_pins[] = { 67, };
--static int mt7629_spi_hold_funcs[] = { 1, };
-+static const int mt7629_spi_0_pins[] = { 21, 22, 23, 24, };
-+static const int mt7629_spi_0_funcs[] = { 1, 1, 1, 1, };
-+static const int mt7629_spi_1_pins[] = { 62, 63, 64, 65, };
-+static const int mt7629_spi_1_funcs[] = { 1, 1, 1, 1, };
-+static const int mt7629_spi_wp_pins[] = { 66, };
-+static const int mt7629_spi_wp_funcs[] = { 1, };
-+static const int mt7629_spi_hold_pins[] = { 67, };
-+static const int mt7629_spi_hold_funcs[] = { 1, };
- 
- /* UART */
--static int mt7629_uart1_0_txd_rxd_pins[] = { 25, 26, };
--static int mt7629_uart1_0_txd_rxd_funcs[] = { 1, 1, };
--static int mt7629_uart1_1_txd_rxd_pins[] = { 53, 54, };
--static int mt7629_uart1_1_txd_rxd_funcs[] = { 2, 2, };
--static int mt7629_uart2_0_txd_rxd_pins[] = { 29, 30, };
--static int mt7629_uart2_0_txd_rxd_funcs[] = { 1, 1, };
--static int mt7629_uart2_1_txd_rxd_pins[] = { 57, 58, };
--static int mt7629_uart2_1_txd_rxd_funcs[] = { 2, 2, };
--static int mt7629_uart1_0_cts_rts_pins[] = { 27, 28, };
--static int mt7629_uart1_0_cts_rts_funcs[] = { 1, 1, };
--static int mt7629_uart1_1_cts_rts_pins[] = { 55, 56, };
--static int mt7629_uart1_1_cts_rts_funcs[] = { 2, 2, };
--static int mt7629_uart2_0_cts_rts_pins[] = { 31, 32, };
--static int mt7629_uart2_0_cts_rts_funcs[] = { 1, 1, };
--static int mt7629_uart2_1_cts_rts_pins[] = { 59, 60, };
--static int mt7629_uart2_1_cts_rts_funcs[] = { 2, 2, };
--static int mt7629_uart0_txd_rxd_pins[] = { 68, 69, };
--static int mt7629_uart0_txd_rxd_funcs[] = { 1, 1, };
-+static const int mt7629_uart1_0_txd_rxd_pins[] = { 25, 26, };
-+static const int mt7629_uart1_0_txd_rxd_funcs[] = { 1, 1, };
-+static const int mt7629_uart1_1_txd_rxd_pins[] = { 53, 54, };
-+static const int mt7629_uart1_1_txd_rxd_funcs[] = { 2, 2, };
-+static const int mt7629_uart2_0_txd_rxd_pins[] = { 29, 30, };
-+static const int mt7629_uart2_0_txd_rxd_funcs[] = { 1, 1, };
-+static const int mt7629_uart2_1_txd_rxd_pins[] = { 57, 58, };
-+static const int mt7629_uart2_1_txd_rxd_funcs[] = { 2, 2, };
-+static const int mt7629_uart1_0_cts_rts_pins[] = { 27, 28, };
-+static const int mt7629_uart1_0_cts_rts_funcs[] = { 1, 1, };
-+static const int mt7629_uart1_1_cts_rts_pins[] = { 55, 56, };
-+static const int mt7629_uart1_1_cts_rts_funcs[] = { 2, 2, };
-+static const int mt7629_uart2_0_cts_rts_pins[] = { 31, 32, };
-+static const int mt7629_uart2_0_cts_rts_funcs[] = { 1, 1, };
-+static const int mt7629_uart2_1_cts_rts_pins[] = { 59, 60, };
-+static const int mt7629_uart2_1_cts_rts_funcs[] = { 2, 2, };
-+static const int mt7629_uart0_txd_rxd_pins[] = { 68, 69, };
-+static const int mt7629_uart0_txd_rxd_funcs[] = { 1, 1, };
- 
- /* MDC/MDIO */
--static int mt7629_mdc_mdio_pins[] = { 49, 50, };
--static int mt7629_mdc_mdio_funcs[] = { 1, 1, };
-+static const int mt7629_mdc_mdio_pins[] = { 49, 50, };
-+static const int mt7629_mdc_mdio_funcs[] = { 1, 1, };
- 
- /* PCIE */
--static int mt7629_pcie_pereset_pins[] = { 51, };
--static int mt7629_pcie_pereset_funcs[] = { 1, };
--static int mt7629_pcie_wake_pins[] = { 55, };
--static int mt7629_pcie_wake_funcs[] = { 1, };
--static int mt7629_pcie_clkreq_pins[] = { 56, };
--static int mt7629_pcie_clkreq_funcs[] = { 1, };
-+static const int mt7629_pcie_pereset_pins[] = { 51, };
-+static const int mt7629_pcie_pereset_funcs[] = { 1, };
-+static const int mt7629_pcie_wake_pins[] = { 55, };
-+static const int mt7629_pcie_wake_funcs[] = { 1, };
-+static const int mt7629_pcie_clkreq_pins[] = { 56, };
-+static const int mt7629_pcie_clkreq_funcs[] = { 1, };
- 
- /* PWM */
--static int mt7629_pwm_0_pins[] = { 52, };
--static int mt7629_pwm_0_funcs[] = { 1, };
--static int mt7629_pwm_1_pins[] = { 61, };
--static int mt7629_pwm_1_funcs[] = { 2, };
-+static const int mt7629_pwm_0_pins[] = { 52, };
-+static const int mt7629_pwm_0_funcs[] = { 1, };
-+static const int mt7629_pwm_1_pins[] = { 61, };
-+static const int mt7629_pwm_1_funcs[] = { 2, };
- 
- /* WF 2G */
--static int mt7629_wf0_2g_pins[] = { 70, 71, 72, 73, 74, 75, 76, 77, 78, };
--static int mt7629_wf0_2g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, };
-+static const int mt7629_wf0_2g_pins[] = { 70, 71, 72, 73, 74, 75, 76, 77, 78, };
-+static const int mt7629_wf0_2g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, };
- 
- /* SNFI */
--static int mt7629_snfi_pins[] = { 62, 63, 64, 65, 66, 67 };
--static int mt7629_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 };
-+static const int mt7629_snfi_pins[] = { 62, 63, 64, 65, 66, 67 };
-+static const int mt7629_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 };
- 
- /* SPI NOR */
--static int mt7629_snor_pins[] = { 62, 63, 64, 65, 66, 67 };
--static int mt7629_snor_funcs[] = { 1, 1, 1, 1, 1, 1 };
-+static const int mt7629_snor_pins[] = { 62, 63, 64, 65, 66, 67 };
-+static const int mt7629_snor_funcs[] = { 1, 1, 1, 1, 1, 1 };
- 
- static const struct mtk_group_desc mt7629_groups[] = {
- 	PINCTRL_PIN_GROUP("wf0_5g", mt7629_wf0_5g),
-@@ -385,7 +385,7 @@ static const struct mtk_function_desc mt
- 	{"jtag", mt7629_jtag_groups, ARRAY_SIZE(mt7629_jtag_groups)},
- };
- 
--static struct mtk_pinctrl_soc mt7629_data = {
-+static const struct mtk_pinctrl_soc mt7629_data = {
- 	.name = "mt7629_pinctrl",
- 	.reg_cal = mt7629_reg_cals,
- 	.pins = mt7629_pins,
---- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c
-@@ -570,242 +570,246 @@ static const struct mtk_pin_desc mt7981_
- };
- 
- /* WA_AICE */
--static int mt7981_wa_aice1_pins[] = { 0, 1, };
--static int mt7981_wa_aice1_funcs[] = { 2, 2, };
-+static const int mt7981_wa_aice1_pins[] = { 0, 1, };
-+static const int mt7981_wa_aice1_funcs[] = { 2, 2, };
- 
--static int mt7981_wa_aice2_pins[] = { 0, 1, };
--static int mt7981_wa_aice2_funcs[] = { 3, 3, };
-+static const int mt7981_wa_aice2_pins[] = { 0, 1, };
-+static const int mt7981_wa_aice2_funcs[] = { 3, 3, };
- 
--static int mt7981_wa_aice3_pins[] = { 28, 29, };
--static int mt7981_wa_aice3_funcs[] = { 3, 3, };
-+static const int mt7981_wa_aice3_pins[] = { 28, 29, };
-+static const int mt7981_wa_aice3_funcs[] = { 3, 3, };
- 
--static int mt7981_wm_aice1_pins[] = { 9, 10, };
--static int mt7981_wm_aice1_funcs[] = { 2, 2, };
-+static const int mt7981_wm_aice1_pins[] = { 9, 10, };
-+static const int mt7981_wm_aice1_funcs[] = { 2, 2, };
- 
--static int mt7981_wm_aice2_pins[] = { 30, 31, };
--static int mt7981_wm_aice2_funcs[] = { 5, 5, };
-+static const int mt7981_wm_aice2_pins[] = { 30, 31, };
-+static const int mt7981_wm_aice2_funcs[] = { 5, 5, };
- 
- /* WM_UART */
--static int mt7981_wm_uart_0_pins[] = { 0, 1, };
--static int mt7981_wm_uart_0_funcs[] = { 5, 5, };
-+static const int mt7981_wm_uart_0_pins[] = { 0, 1, };
-+static const int mt7981_wm_uart_0_funcs[] = { 5, 5, };
- 
--static int mt7981_wm_uart_1_pins[] = { 20, 21, };
--static int mt7981_wm_uart_1_funcs[] = { 4, 4, };
-+static const int mt7981_wm_uart_1_pins[] = { 20, 21, };
-+static const int mt7981_wm_uart_1_funcs[] = { 4, 4, };
- 
--static int mt7981_wm_uart_2_pins[] = { 30, 31, };
--static int mt7981_wm_uart_2_funcs[] = { 3, 3, };
-+static const int mt7981_wm_uart_2_pins[] = { 30, 31, };
-+static const int mt7981_wm_uart_2_funcs[] = { 3, 3, };
- 
- /* DFD */
--static int mt7981_dfd_pins[] = { 0, 1, 4, 5, };
--static int mt7981_dfd_funcs[] = { 5, 5, 6, 6, };
-+static const int mt7981_dfd_pins[] = { 0, 1, 4, 5, };
-+static const int mt7981_dfd_funcs[] = { 5, 5, 6, 6, };
- 
- /* SYS_WATCHDOG */
--static int mt7981_watchdog_pins[] = { 2, };
--static int mt7981_watchdog_funcs[] = { 1, };
-+static const int mt7981_watchdog_pins[] = { 2, };
-+static const int mt7981_watchdog_funcs[] = { 1, };
- 
--static int mt7981_watchdog1_pins[] = { 13, };
--static int mt7981_watchdog1_funcs[] = { 5, };
-+static const int mt7981_watchdog1_pins[] = { 13, };
-+static const int mt7981_watchdog1_funcs[] = { 5, };
- 
- /* PCIE_PERESET_N */
--static int mt7981_pcie_pereset_pins[] = { 3, };
--static int mt7981_pcie_pereset_funcs[] = { 1, };
-+static const int mt7981_pcie_pereset_pins[] = { 3, };
-+static const int mt7981_pcie_pereset_funcs[] = { 1, };
- 
- /* JTAG */
--static int mt7981_jtag_pins[] = { 4, 5, 6, 7, 8, };
--static int mt7981_jtag_funcs[] = { 1, 1, 1, 1, 1, };
-+static const int mt7981_jtag_pins[] = { 4, 5, 6, 7, 8, };
-+static const int mt7981_jtag_funcs[] = { 1, 1, 1, 1, 1, };
- 
- /* WM_JTAG */
--static int mt7981_wm_jtag_0_pins[] = { 4, 5, 6, 7, 8, };
--static int mt7981_wm_jtag_0_funcs[] = { 2, 2, 2, 2, 2, };
-+static const int mt7981_wm_jtag_0_pins[] = { 4, 5, 6, 7, 8, };
-+static const int mt7981_wm_jtag_0_funcs[] = { 2, 2, 2, 2, 2, };
- 
--static int mt7981_wm_jtag_1_pins[] = { 20, 21, 22, 23, 24, };
--static int mt7981_wm_jtag_1_funcs[] = { 5, 5, 5, 5, 5, };
-+static const int mt7981_wm_jtag_1_pins[] = { 20, 21, 22, 23, 24, };
-+static const int mt7981_wm_jtag_1_funcs[] = { 5, 5, 5, 5, 5, };
- 
- /* WO0_JTAG */
--static int mt7981_wo0_jtag_0_pins[] = { 9, 10, 11, 12, 13, };
--static int mt7981_wo0_jtag_0_funcs[] = { 1, 1, 1, 1, 1, };
-+static const int mt7981_wo0_jtag_0_pins[] = { 9, 10, 11, 12, 13, };
-+static const int mt7981_wo0_jtag_0_funcs[] = { 1, 1, 1, 1, 1, };
- 
--static int mt7981_wo0_jtag_1_pins[] = { 25, 26, 27, 28, 29, };
--static int mt7981_wo0_jtag_1_funcs[] = { 5, 5, 5, 5, 5, };
-+static const int mt7981_wo0_jtag_1_pins[] = { 25, 26, 27, 28, 29, };
-+static const int mt7981_wo0_jtag_1_funcs[] = { 5, 5, 5, 5, 5, };
- 
- /* UART2 */
--static int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, };
--static int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, };
-+static const int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, };
-+static const int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, };
- 
- /* GBE_LED0 */
--static int mt7981_gbe_led0_pins[] = { 8, };
--static int mt7981_gbe_led0_funcs[] = { 3, };
-+static const int mt7981_gbe_led0_pins[] = { 8, };
-+static const int mt7981_gbe_led0_funcs[] = { 3, };
- 
- /* PTA_EXT */
--static int mt7981_pta_ext_0_pins[] = { 4, 5, 6, };
--static int mt7981_pta_ext_0_funcs[] = { 4, 4, 4, };
-+static const int mt7981_pta_ext_0_pins[] = { 4, 5, 6, };
-+static const int mt7981_pta_ext_0_funcs[] = { 4, 4, 4, };
- 
--static int mt7981_pta_ext_1_pins[] = { 22, 23, 24, };
--static int mt7981_pta_ext_1_funcs[] = { 4, 4, 4, };
-+static const int mt7981_pta_ext_1_pins[] = { 22, 23, 24, };
-+static const int mt7981_pta_ext_1_funcs[] = { 4, 4, 4, };
- 
- /* PWM2 */
--static int mt7981_pwm2_pins[] = { 7, };
--static int mt7981_pwm2_funcs[] = { 4, };
-+static const int mt7981_pwm2_pins[] = { 7, };
-+static const int mt7981_pwm2_funcs[] = { 4, };
- 
- /* NET_WO0_UART_TXD */
--static int mt7981_net_wo0_uart_txd_0_pins[] = { 8, };
--static int mt7981_net_wo0_uart_txd_0_funcs[] = { 4, };
-+static const int mt7981_net_wo0_uart_txd_0_pins[] = { 8, };
-+static const int mt7981_net_wo0_uart_txd_0_funcs[] = { 4, };
- 
--static int mt7981_net_wo0_uart_txd_1_pins[] = { 14, };
--static int mt7981_net_wo0_uart_txd_1_funcs[] = { 3, };
-+static const int mt7981_net_wo0_uart_txd_1_pins[] = { 14, };
-+static const int mt7981_net_wo0_uart_txd_1_funcs[] = { 3, };
- 
--static int mt7981_net_wo0_uart_txd_2_pins[] = { 15, };
--static int mt7981_net_wo0_uart_txd_2_funcs[] = { 4, };
-+static const int mt7981_net_wo0_uart_txd_2_pins[] = { 15, };
-+static const int mt7981_net_wo0_uart_txd_2_funcs[] = { 4, };
- 
- /* SPI1 */
--static int mt7981_spi1_0_pins[] = { 4, 5, 6, 7, };
--static int mt7981_spi1_0_funcs[] = { 5, 5, 5, 5, };
-+static const int mt7981_spi1_0_pins[] = { 4, 5, 6, 7, };
-+static const int mt7981_spi1_0_funcs[] = { 5, 5, 5, 5, };
- 
- /* I2C */
--static int mt7981_i2c0_0_pins[] = { 6, 7, };
--static int mt7981_i2c0_0_funcs[] = { 6, 6, };
-+static const int mt7981_i2c0_0_pins[] = { 6, 7, };
-+static const int mt7981_i2c0_0_funcs[] = { 6, 6, };
- 
--static int mt7981_i2c0_1_pins[] = { 30, 31, };
--static int mt7981_i2c0_1_funcs[] = { 4, 4, };
-+static const int mt7981_i2c0_1_pins[] = { 30, 31, };
-+static const int mt7981_i2c0_1_funcs[] = { 4, 4, };
- 
--static int mt7981_i2c0_2_pins[] = { 36, 37, };
--static int mt7981_i2c0_2_funcs[] = { 2, 2, };
-+static const int mt7981_i2c0_2_pins[] = { 36, 37, };
-+static const int mt7981_i2c0_2_funcs[] = { 2, 2, };
- 
--static int mt7981_u2_phy_i2c_pins[] = { 30, 31, };
--static int mt7981_u2_phy_i2c_funcs[] = { 6, 6, };
-+static const int mt7981_u2_phy_i2c_pins[] = { 30, 31, };
-+static const int mt7981_u2_phy_i2c_funcs[] = { 6, 6, };
- 
--static int mt7981_u3_phy_i2c_pins[] = { 32, 33, };
--static int mt7981_u3_phy_i2c_funcs[] = { 3, 3, };
-+static const int mt7981_u3_phy_i2c_pins[] = { 32, 33, };
-+static const int mt7981_u3_phy_i2c_funcs[] = { 3, 3, };
- 
--static int mt7981_sgmii1_phy_i2c_pins[] = { 32, 33, };
--static int mt7981_sgmii1_phy_i2c_funcs[] = { 2, 2, };
-+static const int mt7981_sgmii1_phy_i2c_pins[] = { 32, 33, };
-+static const int mt7981_sgmii1_phy_i2c_funcs[] = { 2, 2, };
- 
--static int mt7981_sgmii0_phy_i2c_pins[] = { 32, 33, };
--static int mt7981_sgmii0_phy_i2c_funcs[] = { 5, 5, };
-+static const int mt7981_sgmii0_phy_i2c_pins[] = { 32, 33, };
-+static const int mt7981_sgmii0_phy_i2c_funcs[] = { 5, 5, };
- 
- /* DFD_NTRST */
--static int mt7981_dfd_ntrst_pins[] = { 8, };
--static int mt7981_dfd_ntrst_funcs[] = { 6, };
-+static const int mt7981_dfd_ntrst_pins[] = { 8, };
-+static const int mt7981_dfd_ntrst_funcs[] = { 6, };
- 
- /* PWM0 */
--static int mt7981_pwm0_0_pins[] = { 13, };
--static int mt7981_pwm0_0_funcs[] = { 2, };
-+static const int mt7981_pwm0_0_pins[] = { 13, };
-+static const int mt7981_pwm0_0_funcs[] = { 2, };
- 
--static int mt7981_pwm0_1_pins[] = { 15, };
--static int mt7981_pwm0_1_funcs[] = { 1, };
-+static const int mt7981_pwm0_1_pins[] = { 15, };
-+static const int mt7981_pwm0_1_funcs[] = { 1, };
- 
- /* PWM1 */
--static int mt7981_pwm1_0_pins[] = { 14, };
--static int mt7981_pwm1_0_funcs[] = { 2, };
-+static const int mt7981_pwm1_0_pins[] = { 14, };
-+static const int mt7981_pwm1_0_funcs[] = { 2, };
- 
--static int mt7981_pwm1_1_pins[] = { 15, };
--static int mt7981_pwm1_1_funcs[] = { 3, };
-+static const int mt7981_pwm1_1_pins[] = { 15, };
-+static const int mt7981_pwm1_1_funcs[] = { 3, };
- 
- /* GBE_LED1 */
--static int mt7981_gbe_led1_pins[] = { 13, };
--static int mt7981_gbe_led1_funcs[] = { 3, };
-+static const int mt7981_gbe_led1_pins[] = { 13, };
-+static const int mt7981_gbe_led1_funcs[] = { 3, };
- 
- /* PCM */
--static int mt7981_pcm_pins[] = { 9, 10, 11, 12, 13, 25 };
--static int mt7981_pcm_funcs[] = { 4, 4, 4, 4, 4, 4, };
-+static const int mt7981_pcm_pins[] = { 9, 10, 11, 12, 13, 25 };
-+static const int mt7981_pcm_funcs[] = { 4, 4, 4, 4, 4, 4, };
- 
- /* UDI */
--static int mt7981_udi_pins[] = { 9, 10, 11, 12, 13, };
--static int mt7981_udi_funcs[] = { 6, 6, 6, 6, 6, };
-+static const int mt7981_udi_pins[] = { 9, 10, 11, 12, 13, };
-+static const int mt7981_udi_funcs[] = { 6, 6, 6, 6, 6, };
- 
- /* DRV_VBUS */
--static int mt7981_drv_vbus_pins[] = { 14, };
--static int mt7981_drv_vbus_funcs[] = { 1, };
-+static const int mt7981_drv_vbus_pins[] = { 14, };
-+static const int mt7981_drv_vbus_funcs[] = { 1, };
- 
- /* EMMC */
--static int mt7981_emmc_45_pins[] = { 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, };
--static int mt7981_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
-+static const int mt7981_emmc_45_pins[] = {
-+	15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, };
-+static const int mt7981_emmc_45_funcs[] = {
-+	2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
- 
- /* SNFI */
--static int mt7981_snfi_pins[] = { 16, 17, 18, 19, 20, 21, };
--static int mt7981_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, };
-+static const int mt7981_snfi_pins[] = { 16, 17, 18, 19, 20, 21, };
-+static const int mt7981_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, };
- 
- /* SPI0 */
--static int mt7981_spi0_pins[] = { 16, 17, 18, 19, };
--static int mt7981_spi0_funcs[] = { 1, 1, 1, 1, };
-+static const int mt7981_spi0_pins[] = { 16, 17, 18, 19, };
-+static const int mt7981_spi0_funcs[] = { 1, 1, 1, 1, };
- 
- /* SPI0 */
--static int mt7981_spi0_wp_hold_pins[] = { 20, 21, };
--static int mt7981_spi0_wp_hold_funcs[] = { 1, 1, };
-+static const int mt7981_spi0_wp_hold_pins[] = { 20, 21, };
-+static const int mt7981_spi0_wp_hold_funcs[] = { 1, 1, };
- 
- /* SPI1 */
--static int mt7981_spi1_1_pins[] = { 22, 23, 24, 25, };
--static int mt7981_spi1_1_funcs[] = { 1, 1, 1, 1, };
-+static const int mt7981_spi1_1_pins[] = { 22, 23, 24, 25, };
-+static const int mt7981_spi1_1_funcs[] = { 1, 1, 1, 1, };
- 
- /* SPI2 */
--static int mt7981_spi2_pins[] = { 26, 27, 28, 29, };
--static int mt7981_spi2_funcs[] = { 1, 1, 1, 1, };
-+static const int mt7981_spi2_pins[] = { 26, 27, 28, 29, };
-+static const int mt7981_spi2_funcs[] = { 1, 1, 1, 1, };
- 
- /* SPI2 */
--static int mt7981_spi2_wp_hold_pins[] = { 30, 31, };
--static int mt7981_spi2_wp_hold_funcs[] = { 1, 1, };
-+static const int mt7981_spi2_wp_hold_pins[] = { 30, 31, };
-+static const int mt7981_spi2_wp_hold_funcs[] = { 1, 1, };
- 
- /* UART1 */
--static int mt7981_uart1_0_pins[] = { 16, 17, 18, 19, };
--static int mt7981_uart1_0_funcs[] = { 4, 4, 4, 4, };
-+static const int mt7981_uart1_0_pins[] = { 16, 17, 18, 19, };
-+static const int mt7981_uart1_0_funcs[] = { 4, 4, 4, 4, };
- 
--static int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, };
--static int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, };
-+static const int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, };
-+static const int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, };
- 
- /* UART2 */
--static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, };
--static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, };
-+static const int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, };
-+static const int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, };
- 
- /* UART0 */
--static int mt7981_uart0_pins[] = { 32, 33, };
--static int mt7981_uart0_funcs[] = { 1, 1, };
-+static const int mt7981_uart0_pins[] = { 32, 33, };
-+static const int mt7981_uart0_funcs[] = { 1, 1, };
- 
- /* PCIE_CLK_REQ */
--static int mt7981_pcie_clk_pins[] = { 34, };
--static int mt7981_pcie_clk_funcs[] = { 2, };
-+static const int mt7981_pcie_clk_pins[] = { 34, };
-+static const int mt7981_pcie_clk_funcs[] = { 2, };
- 
- /* PCIE_WAKE_N */
--static int mt7981_pcie_wake_pins[] = { 35, };
--static int mt7981_pcie_wake_funcs[] = { 2, };
-+static const int mt7981_pcie_wake_pins[] = { 35, };
-+static const int mt7981_pcie_wake_funcs[] = { 2, };
- 
- /* MDC_MDIO */
--static int mt7981_smi_mdc_mdio_pins[] = { 36, 37, };
--static int mt7981_smi_mdc_mdio_funcs[] = { 1, 1, };
-+static const int mt7981_smi_mdc_mdio_pins[] = { 36, 37, };
-+static const int mt7981_smi_mdc_mdio_funcs[] = { 1, 1, };
- 
--static int mt7981_gbe_ext_mdc_mdio_pins[] = { 36, 37, };
--static int mt7981_gbe_ext_mdc_mdio_funcs[] = { 3, 3, };
-+static const int mt7981_gbe_ext_mdc_mdio_pins[] = { 36, 37, };
-+static const int mt7981_gbe_ext_mdc_mdio_funcs[] = { 3, 3, };
- 
- /* WF0_MODE1 */
--static int mt7981_wf0_mode1_pins[] = { 40, 41, 42, 43, 44, 45, 46, 47, 48, 49,
--				       50, 51, 52, 53, 54, 55, 56 };
--static int mt7981_wf0_mode1_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
--					1, 1, 1, 1 };
-+static const int mt7981_wf0_mode1_pins[] = {
-+	40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56 };
-+static const int mt7981_wf0_mode1_funcs[] = {
-+	1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
- 
- /* WF0_MODE3 */
--static int mt7981_wf0_mode3_pins[] = { 45, 46, 47, 48, 49, 51 };
--static int mt7981_wf0_mode3_funcs[] = { 2, 2, 2, 2, 2, 2 };
-+static const int mt7981_wf0_mode3_pins[] = { 45, 46, 47, 48, 49, 51 };
-+static const int mt7981_wf0_mode3_funcs[] = { 2, 2, 2, 2, 2, 2 };
- 
- /* WF2G_LED */
--static int mt7981_wf2g_led0_pins[] = { 30, };
--static int mt7981_wf2g_led0_funcs[] = { 2, };
-+static const int mt7981_wf2g_led0_pins[] = { 30, };
-+static const int mt7981_wf2g_led0_funcs[] = { 2, };
- 
--static int mt7981_wf2g_led1_pins[] = { 34, };
--static int mt7981_wf2g_led1_funcs[] = { 1, };
-+static const int mt7981_wf2g_led1_pins[] = { 34, };
-+static const int mt7981_wf2g_led1_funcs[] = { 1, };
- 
- /* WF5G_LED */
--static int mt7981_wf5g_led0_pins[] = { 31, };
--static int mt7981_wf5g_led0_funcs[] = { 2, };
-+static const int mt7981_wf5g_led0_pins[] = { 31, };
-+static const int mt7981_wf5g_led0_funcs[] = { 2, };
- 
--static int mt7981_wf5g_led1_pins[] = { 35, };
--static int mt7981_wf5g_led1_funcs[] = { 1, };
-+static const int mt7981_wf5g_led1_pins[] = { 35, };
-+static const int mt7981_wf5g_led1_funcs[] = { 1, };
- 
- /* MT7531_INT */
--static int mt7981_mt7531_int_pins[] = { 38, };
--static int mt7981_mt7531_int_funcs[] = { 1, };
-+static const int mt7981_mt7531_int_pins[] = { 38, };
-+static const int mt7981_mt7531_int_funcs[] = { 1, };
- 
- /* ANT_SEL */
--static int mt7981_ant_sel_pins[] = { 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 34, 35 };
--static int mt7981_ant_sel_funcs[] = { 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6 };
-+static const int mt7981_ant_sel_pins[] = {
-+	14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 34, 35 };
-+static const int mt7981_ant_sel_funcs[] = {
-+	6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6 };
- 
- static const struct mtk_group_desc mt7981_groups[] = {
- 	/* @GPIO(0,1): WA_AICE(2) */
-@@ -1012,7 +1016,7 @@ static const char *const mt7981_pinctrl_
- 	"iocfg_lb_base", "iocfg_bl_base", "iocfg_tm_base", "iocfg_tl_base",
- };
- 
--static struct mtk_pinctrl_soc mt7981_data = {
-+static const struct mtk_pinctrl_soc mt7981_data = {
- 	.name = "mt7981_pinctrl",
- 	.reg_cal = mt7981_reg_cals,
- 	.pins = mt7981_pins,
---- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c
-@@ -554,114 +554,117 @@ static const struct mtk_io_type_desc mt7
-  * The hardware probably has multiple combinations of these pinouts.
-  */
- 
--static int mt7986_watchdog_pins[] = { 0, };
--static int mt7986_watchdog_funcs[] = { 1, };
-+static const int mt7986_watchdog_pins[] = { 0, };
-+static const int mt7986_watchdog_funcs[] = { 1, };
- 
--static int mt7986_wifi_led_pins[] = { 1, 2, };
--static int mt7986_wifi_led_funcs[] = { 1, 1, };
-+static const int mt7986_wifi_led_pins[] = { 1, 2, };
-+static const int mt7986_wifi_led_funcs[] = { 1, 1, };
- 
--static int mt7986_i2c_pins[] = { 3, 4, };
--static int mt7986_i2c_funcs[] = { 1, 1, };
-+static const int mt7986_i2c_pins[] = { 3, 4, };
-+static const int mt7986_i2c_funcs[] = { 1, 1, };
- 
--static int mt7986_uart1_0_pins[] = { 7, 8, 9, 10, };
--static int mt7986_uart1_0_funcs[] = { 3, 3, 3, 3, };
-+static const int mt7986_uart1_0_pins[] = { 7, 8, 9, 10, };
-+static const int mt7986_uart1_0_funcs[] = { 3, 3, 3, 3, };
- 
--static int mt7986_spi1_0_pins[] = { 11, 12, 13, 14, };
--static int mt7986_spi1_0_funcs[] = { 3, 3, 3, 3, };
-+static const int mt7986_spi1_0_pins[] = { 11, 12, 13, 14, };
-+static const int mt7986_spi1_0_funcs[] = { 3, 3, 3, 3, };
- 
--static int mt7986_pwm1_1_pins[] = { 20, };
--static int mt7986_pwm1_1_funcs[] = { 2, };
-+static const int mt7986_pwm1_1_pins[] = { 20, };
-+static const int mt7986_pwm1_1_funcs[] = { 2, };
- 
--static int mt7986_pwm0_pins[] = { 21, };
--static int mt7986_pwm0_funcs[] = { 1, };
-+static const int mt7986_pwm0_pins[] = { 21, };
-+static const int mt7986_pwm0_funcs[] = { 1, };
- 
--static int mt7986_pwm1_0_pins[] = { 22, };
--static int mt7986_pwm1_0_funcs[] = { 1, };
-+static const int mt7986_pwm1_0_pins[] = { 22, };
-+static const int mt7986_pwm1_0_funcs[] = { 1, };
- 
--static int mt7986_emmc_45_pins[] = {
-+static const int mt7986_emmc_45_pins[] = {
- 	22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, };
--static int mt7986_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
-+static const int mt7986_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
- 
--static int mt7986_snfi_pins[] = { 23, 24, 25, 26, 27, 28, };
--static int mt7986_snfi_funcs[] = { 1, 1, 1, 1, 1, 1, };
-+static const int mt7986_snfi_pins[] = { 23, 24, 25, 26, 27, 28, };
-+static const int mt7986_snfi_funcs[] = { 1, 1, 1, 1, 1, 1, };
- 
--static int mt7986_spi1_1_pins[] = { 23, 24, 25, 26, };
--static int mt7986_spi1_1_funcs[] = { 3, 3, 3, 3, };
-+static const int mt7986_spi1_1_pins[] = { 23, 24, 25, 26, };
-+static const int mt7986_spi1_1_funcs[] = { 3, 3, 3, 3, };
- 
--static int mt7986_uart1_1_pins[] = { 23, 24, 25, 26, };
--static int mt7986_uart1_1_funcs[] = { 4, 4, 4, 4, };
-+static const int mt7986_uart1_1_pins[] = { 23, 24, 25, 26, };
-+static const int mt7986_uart1_1_funcs[] = { 4, 4, 4, 4, };
- 
--static int mt7986_spi1_2_pins[] = { 29, 30, 31, 32, };
--static int mt7986_spi1_2_funcs[] = { 1, 1, 1, 1, };
-+static const int mt7986_spi1_2_pins[] = { 29, 30, 31, 32, };
-+static const int mt7986_spi1_2_funcs[] = { 1, 1, 1, 1, };
- 
--static int mt7986_uart1_2_pins[] = { 29, 30, 31, 32, };
--static int mt7986_uart1_2_funcs[] = { 3, 3, 3, 3, };
-+static const int mt7986_uart1_2_pins[] = { 29, 30, 31, 32, };
-+static const int mt7986_uart1_2_funcs[] = { 3, 3, 3, 3, };
- 
--static int mt7986_uart2_0_pins[] = { 29, 30, 31, 32, };
--static int mt7986_uart2_0_funcs[] = { 4, 4, 4, 4, };
-+static const int mt7986_uart2_0_pins[] = { 29, 30, 31, 32, };
-+static const int mt7986_uart2_0_funcs[] = { 4, 4, 4, 4, };
- 
--static int mt7986_spi0_pins[] = { 33, 34, 35, 36, };
--static int mt7986_spi0_funcs[] = { 1, 1, 1, 1, };
-+static const int mt7986_spi0_pins[] = { 33, 34, 35, 36, };
-+static const int mt7986_spi0_funcs[] = { 1, 1, 1, 1, };
- 
--static int mt7986_spi0_wp_hold_pins[] = { 37, 38, };
--static int mt7986_spi0_wp_hold_funcs[] = { 1, 1, };
-+static const int mt7986_spi0_wp_hold_pins[] = { 37, 38, };
-+static const int mt7986_spi0_wp_hold_funcs[] = { 1, 1, };
- 
--static int mt7986_uart2_1_pins[] = { 33, 34, 35, 36, };
--static int mt7986_uart2_1_funcs[] = { 3, 3, 3, 3, };
-+static const int mt7986_uart2_1_pins[] = { 33, 34, 35, 36, };
-+static const int mt7986_uart2_1_funcs[] = { 3, 3, 3, 3, };
- 
--static int mt7986_uart1_3_rx_tx_pins[] = { 35, 36, };
--static int mt7986_uart1_3_rx_tx_funcs[] = { 2, 2, };
-+static const int mt7986_uart1_3_rx_tx_pins[] = { 35, 36, };
-+static const int mt7986_uart1_3_rx_tx_funcs[] = { 2, 2, };
- 
--static int mt7986_uart1_3_cts_rts_pins[] = { 37, 38, };
--static int mt7986_uart1_3_cts_rts_funcs[] = { 2, 2, };
-+static const int mt7986_uart1_3_cts_rts_pins[] = { 37, 38, };
-+static const int mt7986_uart1_3_cts_rts_funcs[] = { 2, 2, };
- 
--static int mt7986_spi1_3_pins[] = { 33, 34, 35, 36, };
--static int mt7986_spi1_3_funcs[] = { 4, 4, 4, 4, };
-+static const int mt7986_spi1_3_pins[] = { 33, 34, 35, 36, };
-+static const int mt7986_spi1_3_funcs[] = { 4, 4, 4, 4, };
- 
--static int mt7986_uart0_pins[] = { 39, 40, };
--static int mt7986_uart0_funcs[] = { 1, 1, };
-+static const int mt7986_uart0_pins[] = { 39, 40, };
-+static const int mt7986_uart0_funcs[] = { 1, 1, };
- 
--static int mt7986_pcie_reset_pins[] = { 41, };
--static int mt7986_pcie_reset_funcs[] = { 1, };
-+static const int mt7986_pcie_reset_pins[] = { 41, };
-+static const int mt7986_pcie_reset_funcs[] = { 1, };
- 
--static int mt7986_uart1_pins[] = { 42, 43, 44, 45, };
--static int mt7986_uart1_funcs[] = { 1, 1, 1, 1, };
-+static const int mt7986_uart1_pins[] = { 42, 43, 44, 45, };
-+static const int mt7986_uart1_funcs[] = { 1, 1, 1, 1, };
- 
--static int mt7986_uart2_pins[] = { 46, 47, 48, 49, };
--static int mt7986_uart2_funcs[] = { 1, 1, 1, 1, };
-+static const int mt7986_uart2_pins[] = { 46, 47, 48, 49, };
-+static const int mt7986_uart2_funcs[] = { 1, 1, 1, 1, };
- 
--static int mt7986_emmc_51_pins[] = {
-+static const int mt7986_emmc_51_pins[] = {
- 	50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, };
--static int mt7986_emmc_51_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
-+static const int mt7986_emmc_51_funcs[] = {
-+	1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
- 
--static int mt7986_pcm_pins[] = { 62, 63, 64, 65, };
--static int mt7986_pcm_funcs[] = { 1, 1, 1, 1, };
-+static const int mt7986_pcm_pins[] = { 62, 63, 64, 65, };
-+static const int mt7986_pcm_funcs[] = { 1, 1, 1, 1, };
- 
--static int mt7986_i2s_pins[] = { 62, 63, 64, 65, };
--static int mt7986_i2s_funcs[] = { 1, 1, 1, 1, };
-+static const int mt7986_i2s_pins[] = { 62, 63, 64, 65, };
-+static const int mt7986_i2s_funcs[] = { 1, 1, 1, 1, };
- 
--static int mt7986_switch_int_pins[] = { 66, };
--static int mt7986_switch_int_funcs[] = { 1, };
-+static const int mt7986_switch_int_pins[] = { 66, };
-+static const int mt7986_switch_int_funcs[] = { 1, };
- 
--static int mt7986_mdc_mdio_pins[] = { 67, 68, };
--static int mt7986_mdc_mdio_funcs[] = { 1, 1, };
-+static const int mt7986_mdc_mdio_pins[] = { 67, 68, };
-+static const int mt7986_mdc_mdio_funcs[] = { 1, 1, };
- 
--static int mt7986_wf_2g_pins[] = {74, 75, 76, 77, 78, 79, 80, 81, 82, 83, };
--static int mt7986_wf_2g_funcs[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
-+static const int mt7986_wf_2g_pins[] = {
-+	74, 75, 76, 77, 78, 79, 80, 81, 82, 83, };
-+static const int mt7986_wf_2g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
- 
--static int mt7986_wf_5g_pins[] = {91, 92, 93, 94, 95, 96, 97, 98, 99, 100, };
--static int mt7986_wf_5g_funcs[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
-+static const int mt7986_wf_5g_pins[] = {
-+	91, 92, 93, 94, 95, 96, 97, 98, 99, 100, };
-+static const int mt7986_wf_5g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
- 
--static int mt7986_wf_dbdc_pins[] = {
-+static const int mt7986_wf_dbdc_pins[] = {
- 	74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, };
--static int mt7986_wf_dbdc_funcs[] = {
-+static const int mt7986_wf_dbdc_funcs[] = {
- 	2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
- 
--static int mt7986_pcie_clk_pins[] = { 9, };
--static int mt7986_pcie_clk_funcs[] = { 1, };
-+static const int mt7986_pcie_clk_pins[] = { 9, };
-+static const int mt7986_pcie_clk_funcs[] = { 1, };
- 
--static int mt7986_pcie_wake_pins[] = { 10, };
--static int mt7986_pcie_wake_funcs[] = { 1, };
-+static const int mt7986_pcie_wake_pins[] = { 10, };
-+static const int mt7986_pcie_wake_funcs[] = { 1, };
- 
- static const struct mtk_group_desc mt7986_groups[] = {
- 	PINCTRL_PIN_GROUP("watchdog", mt7986_watchdog),
-@@ -738,7 +741,7 @@ static const struct mtk_function_desc mt
- 	{"wifi", mt7986_wf_groups, ARRAY_SIZE(mt7986_wf_groups)},
- };
- 
--static struct mtk_pinctrl_soc mt7986_data = {
-+static const struct mtk_pinctrl_soc mt7986_data = {
- 	.name = "mt7986_pinctrl",
- 	.reg_cal = mt7986_reg_cals,
- 	.pins = mt7986_pins,
---- a/drivers/pinctrl/mediatek/pinctrl-mt8512.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt8512.c
-@@ -315,12 +315,12 @@ static const struct mtk_pin_desc mt8512_
-  */
- 
- /* UART */
--static int mt8512_uart0_0_rxd_txd_pins[]		= { 52, 53, };
--static int mt8512_uart0_0_rxd_txd_funcs[]		= {  1,  1, };
--static int mt8512_uart1_0_rxd_txd_pins[]		= { 54, 55, };
--static int mt8512_uart1_0_rxd_txd_funcs[]		= {  1,  1, };
--static int mt8512_uart2_0_rxd_txd_pins[]		= { 28, 29, };
--static int mt8512_uart2_0_rxd_txd_funcs[]		= {  1,  1, };
-+static const int mt8512_uart0_0_rxd_txd_pins[]		= { 52, 53, };
-+static const int mt8512_uart0_0_rxd_txd_funcs[]		= {  1,  1, };
-+static const int mt8512_uart1_0_rxd_txd_pins[]		= { 54, 55, };
-+static const int mt8512_uart1_0_rxd_txd_funcs[]		= {  1,  1, };
-+static const int mt8512_uart2_0_rxd_txd_pins[]		= { 28, 29, };
-+static const int mt8512_uart2_0_rxd_txd_funcs[]		= {  1,  1, };
- 
- /* Joint those groups owning the same capability in user point of view which
-  * allows that people tend to use through the device tree.
-@@ -330,13 +330,13 @@ static const char *const mt8512_uart_gro
- 						"uart2_0_rxd_txd", };
- 
- /* SNAND */
--static int mt8512_snfi_pins[] = { 71, 76, 77, 78, 79, 80, };
--static int mt8512_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, };
-+static const int mt8512_snfi_pins[] = { 71, 76, 77, 78, 79, 80, };
-+static const int mt8512_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, };
- 
- /* MMC0 */
--static int mt8512_msdc0_pins[] = { 76, 77, 78, 79, 80, 81, 82, 83, 84,
--				   85, 86, };
--static int mt8512_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
-+static const int mt8512_msdc0_pins[] = { 76, 77, 78, 79, 80, 81, 82, 83, 84,
-+					 85, 86, };
-+static const int mt8512_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
- 
- static const struct mtk_group_desc mt8512_groups[] = {
- 	PINCTRL_PIN_GROUP("uart0_0_rxd_txd", mt8512_uart0_0_rxd_txd),
-@@ -356,7 +356,7 @@ static const struct mtk_function_desc mt
- 	{"snand", mt8512_msdc_groups, ARRAY_SIZE(mt8512_msdc_groups)},
- };
- 
--static struct mtk_pinctrl_soc mt8512_data = {
-+static const struct mtk_pinctrl_soc mt8512_data = {
- 	.name = "mt8512_pinctrl",
- 	.reg_cal = mt8512_reg_cals,
- 	.pins = mt8512_pins,
---- a/drivers/pinctrl/mediatek/pinctrl-mt8516.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt8516.c
-@@ -326,12 +326,12 @@ static const struct mtk_pin_desc mt8516_
-  */
- 
- /* UART */
--static int mt8516_uart0_0_rxd_txd_pins[]		= { 62, 63, };
--static int mt8516_uart0_0_rxd_txd_funcs[]		= {  1,  1, };
--static int mt8516_uart1_0_rxd_txd_pins[]		= { 64, 65, };
--static int mt8516_uart1_0_rxd_txd_funcs[]		= {  1,  1, };
--static int mt8516_uart2_0_rxd_txd_pins[]		= { 34, 35, };
--static int mt8516_uart2_0_rxd_txd_funcs[]		= {  1,  1, };
-+static const int mt8516_uart0_0_rxd_txd_pins[]		= { 62, 63, };
-+static const int mt8516_uart0_0_rxd_txd_funcs[]		= {  1,  1, };
-+static const int mt8516_uart1_0_rxd_txd_pins[]		= { 64, 65, };
-+static const int mt8516_uart1_0_rxd_txd_funcs[]		= {  1,  1, };
-+static const int mt8516_uart2_0_rxd_txd_pins[]		= { 34, 35, };
-+static const int mt8516_uart2_0_rxd_txd_funcs[]		= {  1,  1, };
- 
- /* Joint those groups owning the same capability in user point of view which
-  * allows that people tend to use through the device tree.
-@@ -341,9 +341,9 @@ static const char *const mt8516_uart_gro
- 						"uart2_0_rxd_txd", };
- 
- /* MMC0 */
--static int mt8516_msdc0_pins[] = { 110, 111, 112, 113, 114, 115, 116, 117, 118,
--				   119, 120, };
--static int mt8516_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
-+static const int mt8516_msdc0_pins[] = { 110, 111, 112, 113, 114, 115, 116, 117,
-+					 118, 119, 120, };
-+static const int mt8516_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
- 
- static const struct mtk_group_desc mt8516_groups[] = {
- 	PINCTRL_PIN_GROUP("uart0_0_rxd_txd", mt8516_uart0_0_rxd_txd),
---- a/drivers/pinctrl/mediatek/pinctrl-mt8518.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt8518.c
-@@ -346,12 +346,12 @@ static const struct mtk_pin_desc mt8518_
-  */
- 
- /* UART */
--static int mt8518_uart0_0_rxd_txd_pins[]		= { 104, 105, };
--static int mt8518_uart0_0_rxd_txd_funcs[]		= {  1,  1, };
--static int mt8518_uart1_0_rxd_txd_pins[]		= { 52, 53, };
--static int mt8518_uart1_0_rxd_txd_funcs[]		= {  1,  1, };
--static int mt8518_uart2_0_rxd_txd_pins[]		= { 106, 107, };
--static int mt8518_uart2_0_rxd_txd_funcs[]		= {  1,  1, };
-+static const int mt8518_uart0_0_rxd_txd_pins[]		= { 104, 105, };
-+static const int mt8518_uart0_0_rxd_txd_funcs[]		= {  1,  1, };
-+static const int mt8518_uart1_0_rxd_txd_pins[]		= { 52, 53, };
-+static const int mt8518_uart1_0_rxd_txd_funcs[]		= {  1,  1, };
-+static const int mt8518_uart2_0_rxd_txd_pins[]		= { 106, 107, };
-+static const int mt8518_uart2_0_rxd_txd_funcs[]		= {  1,  1, };
- 
- /* Joint those groups owning the same capability in user point of view which
-  * allows that people tend to use through the device tree.
-@@ -361,9 +361,9 @@ static const char *const mt8518_uart_gro
- 						"uart2_0_rxd_txd", };
- 
- /* MMC0 */
--static int mt8518_msdc0_pins[] = { 3, 4, 5, 6, 7, 8, 9, 10, 11,
--				   12, 13, };
--static int mt8518_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
-+static const int mt8518_msdc0_pins[] = { 3, 4, 5, 6, 7, 8, 9, 10, 11,
-+					 12, 13, };
-+static const int mt8518_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
- 
- static const struct mtk_group_desc mt8518_groups[] = {
- 	PINCTRL_PIN_GROUP("uart0_0_rxd_txd", mt8518_uart0_0_rxd_txd),
-@@ -380,7 +380,7 @@ static const struct mtk_function_desc mt
- 	{"msdc", mt8518_msdc_groups, ARRAY_SIZE(mt8518_msdc_groups)},
- };
- 
--static struct mtk_pinctrl_soc mt8518_data = {
-+static const struct mtk_pinctrl_soc mt8518_data = {
- 	.name = "mt8518_pinctrl",
- 	.reg_cal = mt8518_reg_cals,
- 	.pins = mt8518_pins,
---- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
-@@ -314,7 +314,7 @@ static int mtk_pinmux_group_set(struct u
- 	int i;
- 
- 	for (i = 0; i < grp->num_pins; i++) {
--		int *pin_modes = grp->data;
-+		const int *pin_modes = grp->data;
- 
- 		mtk_hw_set_value(dev, grp->pins[i], PINCTRL_PIN_REG_MODE,
- 				 pin_modes[i]);
-@@ -769,7 +769,7 @@ static int mtk_gpiochip_register(struct
- #endif
- 
- int mtk_pinctrl_common_probe(struct udevice *dev,
--			     struct mtk_pinctrl_soc *soc)
-+			     const struct mtk_pinctrl_soc *soc)
- {
- 	struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
- 	int ret = 0;
---- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
-+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
-@@ -174,9 +174,9 @@ struct mtk_pin_desc {
-  */
- struct mtk_group_desc {
- 	const char *name;
--	int *pins;
-+	const int *pins;
- 	int num_pins;
--	void *data;
-+	const void *data;
- };
- 
- /**
-@@ -233,7 +233,7 @@ struct mtk_pinctrl_soc {
-  */
- struct mtk_pinctrl_priv {
- 	void __iomem *base[MAX_BASE_CALC];
--	struct mtk_pinctrl_soc *soc;
-+	const struct mtk_pinctrl_soc *soc;
- };
- 
- extern const struct pinctrl_ops mtk_pinctrl_ops;
-@@ -242,7 +242,7 @@ extern const struct pinctrl_ops mtk_pinc
- void mtk_rmw(struct udevice *dev, u32 reg, u32 mask, u32 set);
- void mtk_i_rmw(struct udevice *dev, u8 i, u32 reg, u32 mask, u32 set);
- int mtk_pinctrl_common_probe(struct udevice *dev,
--			     struct mtk_pinctrl_soc *soc);
-+			     const struct mtk_pinctrl_soc *soc);
- 
- #if CONFIG_IS_ENABLED(PINCONF)
- 
diff --git a/package/boot/uboot-mediatek/patches/101-13-pinctrl-mediatek-fix-the-return-value-in-driving-con.patch b/package/boot/uboot-mediatek/patches/101-13-pinctrl-mediatek-fix-the-return-value-in-driving-con.patch
deleted file mode 100644
index d83a89ab37e205..00000000000000
--- a/package/boot/uboot-mediatek/patches/101-13-pinctrl-mediatek-fix-the-return-value-in-driving-con.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From 783c46d29f8b186bd65f3e83f38ad883e8bcec69 Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:16:42 +0800
-Subject: [PATCH 13/29] pinctrl: mediatek: fix the return value in driving
- configuration functions
-
-The original mediatek pinctrl functions for driving configuration
-'mtk_pinconf_drive_set_*' do not return -ENOSUPP even if input
-parameters are not supported.
-This patch fixes the return value in those functions.
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
-@@ -513,7 +513,7 @@ int mtk_pinconf_drive_set_v0(struct udev
- 			return err;
- 	}
- 
--	return 0;
-+	return err;
- }
- 
- int mtk_pinconf_drive_set_v1(struct udevice *dev, u32 pin, u32 arg)
-@@ -531,7 +531,7 @@ int mtk_pinconf_drive_set_v1(struct udev
- 			return err;
- 	}
- 
--	return 0;
-+	return err;
- }
- 
- int mtk_pinconf_drive_set(struct udevice *dev, u32 pin, u32 arg)
diff --git a/package/boot/uboot-mediatek/patches/101-14-pinctrl-mediatek-add-pinmux_set-ops-support.patch b/package/boot/uboot-mediatek/patches/101-14-pinctrl-mediatek-add-pinmux_set-ops-support.patch
deleted file mode 100644
index 7cb185ff42c342..00000000000000
--- a/package/boot/uboot-mediatek/patches/101-14-pinctrl-mediatek-add-pinmux_set-ops-support.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From 090351b416e57e0f7b5d1a4c87d4ed9ab4f5c89b Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:16:46 +0800
-Subject: [PATCH 14/29] pinctrl: mediatek: add pinmux_set ops support
-
-This patch adds pinmux_set ops for mediatek pinctrl framework
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
---- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
-@@ -304,6 +304,19 @@ static const char *mtk_get_function_name
- 	return priv->soc->funcs[selector].name;
- }
- 
-+static int mtk_pinmux_set(struct udevice *dev, unsigned int pin_selector,
-+			  unsigned int func_selector)
-+{
-+	int err;
-+
-+	err = mtk_hw_set_value(dev, pin_selector, PINCTRL_PIN_REG_MODE,
-+			       func_selector);
-+	if (err)
-+		return err;
-+
-+	return 0;
-+}
-+
- static int mtk_pinmux_group_set(struct udevice *dev,
- 				unsigned int group_selector,
- 				unsigned int func_selector)
-@@ -647,6 +660,7 @@ const struct pinctrl_ops mtk_pinctrl_ops
- 	.get_group_name = mtk_get_group_name,
- 	.get_functions_count = mtk_get_functions_count,
- 	.get_function_name = mtk_get_function_name,
-+	.pinmux_set = mtk_pinmux_set,
- 	.pinmux_group_set = mtk_pinmux_group_set,
- #if CONFIG_IS_ENABLED(PINCONF)
- 	.pinconf_num_params = ARRAY_SIZE(mtk_conf_params),
diff --git a/package/boot/uboot-mediatek/patches/101-15-pinctrl-mediatek-add-pinctrl-driver-for-MT7988-SoC.patch b/package/boot/uboot-mediatek/patches/101-15-pinctrl-mediatek-add-pinctrl-driver-for-MT7988-SoC.patch
deleted file mode 100644
index cfc7c32ba317e3..00000000000000
--- a/package/boot/uboot-mediatek/patches/101-15-pinctrl-mediatek-add-pinctrl-driver-for-MT7988-SoC.patch
+++ /dev/null
@@ -1,1315 +0,0 @@
-From 5e821f4ebd9da4ccf3c8871e402996f6a6eb8d1c Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:16:50 +0800
-Subject: [PATCH 15/29] pinctrl: mediatek: add pinctrl driver for MT7988 SoC
-
-This patch adds pinctrl and gpio support for MT7988 SoC
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- drivers/pinctrl/mediatek/Kconfig          |    4 +
- drivers/pinctrl/mediatek/Makefile         |    1 +
- drivers/pinctrl/mediatek/pinctrl-mt7988.c | 1274 +++++++++++++++++++++
- 3 files changed, 1279 insertions(+)
- create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7988.c
-
---- a/drivers/pinctrl/mediatek/Kconfig
-+++ b/drivers/pinctrl/mediatek/Kconfig
-@@ -24,6 +24,10 @@ config PINCTRL_MT7986
- 	bool "MT7986 SoC pinctrl driver"
- 	select PINCTRL_MTK
- 
-+config PINCTRL_MT7988
-+	bool "MT7988 SoC pinctrl driver"
-+	select PINCTRL_MTK
-+
- config PINCTRL_MT8512
- 	bool "MT8512 SoC pinctrl driver"
- 	select PINCTRL_MTK
---- a/drivers/pinctrl/mediatek/Makefile
-+++ b/drivers/pinctrl/mediatek/Makefile
-@@ -8,6 +8,7 @@ obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-
- obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
- obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o
- obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o
-+obj-$(CONFIG_PINCTRL_MT7988) += pinctrl-mt7988.o
- obj-$(CONFIG_PINCTRL_MT8512) += pinctrl-mt8512.o
- obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o
- obj-$(CONFIG_PINCTRL_MT8518) += pinctrl-mt8518.o
---- /dev/null
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt7988.c
-@@ -0,0 +1,1274 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (C) 2022 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ */
-+
-+#include <dm.h>
-+#include "pinctrl-mtk-common.h"
-+
-+enum MT7988_PINCTRL_REG_PAGE {
-+	GPIO_BASE,
-+	IOCFG_TR_BASE,
-+	IOCFG_BR_BASE,
-+	IOCFG_RB_BASE,
-+	IOCFG_LB_BASE,
-+	IOCFG_TL_BASE,
-+};
-+
-+#define MT7988_TYPE0_PIN(_number, _name)                                       \
-+	MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP0)
-+
-+#define MT7988_TYPE1_PIN(_number, _name)                                       \
-+	MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP1)
-+
-+#define MT7988_TYPE2_PIN(_number, _name)                                       \
-+	MTK_TYPED_PIN(_number, _name, DRV_FIXED, IO_TYPE_GRP2)
-+
-+#define PIN_FIELD_GPIO(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits)     \
-+	PIN_FIELD_BASE_CALC(_s_pin, _e_pin, GPIO_BASE, _s_addr, _x_addrs,      \
-+			    _s_bit, _x_bits, 32, 0)
-+
-+#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,     \
-+		       _x_bits)                                                \
-+	PIN_FIELD_BASE_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs,        \
-+			    _s_bit, _x_bits, 32, 0)
-+
-+#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,    \
-+			_x_bits)                                               \
-+	PIN_FIELD_BASE_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs,        \
-+			    _s_bit, _x_bits, 32, 1)
-+
-+static const struct mtk_pin_field_calc mt7988_pin_mode_range[] = {
-+	PIN_FIELD_GPIO(0, 83, 0x300, 0x10, 0, 4),
-+};
-+
-+static const struct mtk_pin_field_calc mt7988_pin_dir_range[] = {
-+	PIN_FIELD_GPIO(0, 83, 0x0, 0x10, 0, 1),
-+};
-+
-+static const struct mtk_pin_field_calc mt7988_pin_di_range[] = {
-+	PIN_FIELD_GPIO(0, 83, 0x200, 0x10, 0, 1),
-+};
-+
-+static const struct mtk_pin_field_calc mt7988_pin_do_range[] = {
-+	PIN_FIELD_GPIO(0, 83, 0x100, 0x10, 0, 1),
-+};
-+
-+static const struct mtk_pin_field_calc mt7988_pin_ies_range[] = {
-+	PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0x30, 0x10, 13, 1),
-+	PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0x30, 0x10, 14, 1),
-+	PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0x30, 0x10, 11, 1),
-+	PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x30, 0x10, 12, 1),
-+	PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x30, 0x10, 0, 1),
-+	PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x30, 0x10, 9, 1),
-+	PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x30, 0x10, 10, 1),
-+
-+	PIN_FIELD_BASE(7, 7, IOCFG_LB_BASE, 0x30, 0x10, 8, 1),
-+	PIN_FIELD_BASE(8, 8, IOCFG_LB_BASE, 0x30, 0x10, 6, 1),
-+	PIN_FIELD_BASE(9, 9, IOCFG_LB_BASE, 0x30, 0x10, 5, 1),
-+	PIN_FIELD_BASE(10, 10, IOCFG_LB_BASE, 0x30, 0x10, 3, 1),
-+
-+	PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0x40, 0x10, 0, 1),
-+	PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0x40, 0x10, 21, 1),
-+	PIN_FIELD_BASE(13, 13, IOCFG_TR_BASE, 0x40, 0x10, 1, 1),
-+	PIN_FIELD_BASE(14, 14, IOCFG_TR_BASE, 0x40, 0x10, 2, 1),
-+
-+	PIN_FIELD_BASE(15, 15, IOCFG_TL_BASE, 0x30, 0x10, 7, 1),
-+	PIN_FIELD_BASE(16, 16, IOCFG_TL_BASE, 0x30, 0x10, 8, 1),
-+	PIN_FIELD_BASE(17, 17, IOCFG_TL_BASE, 0x30, 0x10, 3, 1),
-+	PIN_FIELD_BASE(18, 18, IOCFG_TL_BASE, 0x30, 0x10, 4, 1),
-+
-+	PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0x30, 0x10, 7, 1),
-+	PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0x30, 0x10, 4, 1),
-+
-+	PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0x50, 0x10, 17, 1),
-+	PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0x50, 0x10, 23, 1),
-+	PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0x50, 0x10, 20, 1),
-+	PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0x50, 0x10, 19, 1),
-+	PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0x50, 0x10, 21, 1),
-+	PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0x50, 0x10, 22, 1),
-+	PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0x50, 0x10, 18, 1),
-+	PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0x50, 0x10, 25, 1),
-+	PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0x50, 0x10, 26, 1),
-+	PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0x50, 0x10, 27, 1),
-+	PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0x50, 0x10, 24, 1),
-+	PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0x50, 0x10, 28, 1),
-+	PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0x60, 0x10, 0, 1),
-+	PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0x50, 0x10, 31, 1),
-+	PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0x50, 0x10, 29, 1),
-+	PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0x50, 0x10, 30, 1),
-+	PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0x60, 0x10, 1, 1),
-+	PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0x50, 0x10, 11, 1),
-+	PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x50, 0x10, 10, 1),
-+	PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x50, 0x10, 0, 1),
-+	PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x50, 0x10, 1, 1),
-+	PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x50, 0x10, 9, 1),
-+	PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x50, 0x10, 8, 1),
-+	PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x50, 0x10, 7, 1),
-+	PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x50, 0x10, 6, 1),
-+	PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x50, 0x10, 5, 1),
-+	PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x50, 0x10, 4, 1),
-+	PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x50, 0x10, 3, 1),
-+	PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x50, 0x10, 2, 1),
-+	PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0x50, 0x10, 15, 1),
-+	PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0x50, 0x10, 12, 1),
-+	PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0x50, 0x10, 13, 1),
-+	PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0x50, 0x10, 14, 1),
-+	PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0x50, 0x10, 16, 1),
-+
-+	PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0x40, 0x10, 14, 1),
-+	PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0x40, 0x10, 15, 1),
-+	PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0x40, 0x10, 13, 1),
-+	PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0x40, 0x10, 4, 1),
-+	PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0x40, 0x10, 5, 1),
-+	PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0x40, 0x10, 6, 1),
-+	PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0x40, 0x10, 3, 1),
-+	PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0x40, 0x10, 7, 1),
-+	PIN_FIELD_BASE(63, 63, IOCFG_TR_BASE, 0x40, 0x10, 20, 1),
-+	PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0x40, 0x10, 8, 1),
-+	PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0x40, 0x10, 9, 1),
-+	PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0x40, 0x10, 10, 1),
-+	PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0x40, 0x10, 11, 1),
-+	PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0x40, 0x10, 12, 1),
-+
-+	PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0x30, 0x10, 1, 1),
-+	PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0x30, 0x10, 2, 1),
-+	PIN_FIELD_BASE(71, 71, IOCFG_TL_BASE, 0x30, 0x10, 5, 1),
-+	PIN_FIELD_BASE(72, 72, IOCFG_TL_BASE, 0x30, 0x10, 6, 1),
-+
-+	PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0x30, 0x10, 10, 1),
-+	PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0x30, 0x10, 1, 1),
-+	PIN_FIELD_BASE(75, 75, IOCFG_LB_BASE, 0x30, 0x10, 11, 1),
-+	PIN_FIELD_BASE(76, 76, IOCFG_LB_BASE, 0x30, 0x10, 9, 1),
-+	PIN_FIELD_BASE(77, 77, IOCFG_LB_BASE, 0x30, 0x10, 2, 1),
-+	PIN_FIELD_BASE(78, 78, IOCFG_LB_BASE, 0x30, 0x10, 0, 1),
-+	PIN_FIELD_BASE(79, 79, IOCFG_LB_BASE, 0x30, 0x10, 12, 1),
-+
-+	PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x40, 0x10, 18, 1),
-+	PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x40, 0x10, 19, 1),
-+	PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x40, 0x10, 16, 1),
-+	PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x40, 0x10, 17, 1),
-+};
-+
-+static const struct mtk_pin_field_calc mt7988_pin_smt_range[] = {
-+	PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0xc0, 0x10, 13, 1),
-+	PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0xc0, 0x10, 14, 1),
-+	PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0xc0, 0x10, 11, 1),
-+	PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0xc0, 0x10, 12, 1),
-+	PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0xc0, 0x10, 0, 1),
-+	PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0xc0, 0x10, 9, 1),
-+	PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0xc0, 0x10, 10, 1),
-+
-+	PIN_FIELD_BASE(7, 7, IOCFG_LB_BASE, 0xb0, 0x10, 8, 1),
-+	PIN_FIELD_BASE(8, 8, IOCFG_LB_BASE, 0xb0, 0x10, 6, 1),
-+	PIN_FIELD_BASE(9, 9, IOCFG_LB_BASE, 0xb0, 0x10, 5, 1),
-+	PIN_FIELD_BASE(10, 10, IOCFG_LB_BASE, 0xb0, 0x10, 3, 1),
-+
-+	PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0xe0, 0x10, 0, 1),
-+	PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0xe0, 0x10, 21, 1),
-+	PIN_FIELD_BASE(13, 13, IOCFG_TR_BASE, 0xe0, 0x10, 1, 1),
-+	PIN_FIELD_BASE(14, 14, IOCFG_TR_BASE, 0xe0, 0x10, 2, 1),
-+
-+	PIN_FIELD_BASE(15, 15, IOCFG_TL_BASE, 0xc0, 0x10, 7, 1),
-+	PIN_FIELD_BASE(16, 16, IOCFG_TL_BASE, 0xc0, 0x10, 8, 1),
-+	PIN_FIELD_BASE(17, 17, IOCFG_TL_BASE, 0xc0, 0x10, 3, 1),
-+	PIN_FIELD_BASE(18, 18, IOCFG_TL_BASE, 0xc0, 0x10, 4, 1),
-+
-+	PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0xb0, 0x10, 7, 1),
-+	PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0xb0, 0x10, 4, 1),
-+
-+	PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0x140, 0x10, 17, 1),
-+	PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0x140, 0x10, 23, 1),
-+	PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0x140, 0x10, 20, 1),
-+	PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0x140, 0x10, 19, 1),
-+	PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0x140, 0x10, 21, 1),
-+	PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0x140, 0x10, 22, 1),
-+	PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0x140, 0x10, 18, 1),
-+	PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0x140, 0x10, 25, 1),
-+	PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0x140, 0x10, 26, 1),
-+	PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0x140, 0x10, 27, 1),
-+	PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0x140, 0x10, 24, 1),
-+	PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0x140, 0x10, 28, 1),
-+	PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0x150, 0x10, 0, 1),
-+	PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0x140, 0x10, 31, 1),
-+	PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0x140, 0x10, 29, 1),
-+	PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0x140, 0x10, 30, 1),
-+	PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0x150, 0x10, 1, 1),
-+	PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0x140, 0x10, 11, 1),
-+	PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x140, 0x10, 10, 1),
-+	PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x140, 0x10, 0, 1),
-+	PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x140, 0x10, 1, 1),
-+	PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x140, 0x10, 9, 1),
-+	PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x140, 0x10, 8, 1),
-+	PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x140, 0x10, 7, 1),
-+	PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x140, 0x10, 6, 1),
-+	PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x140, 0x10, 5, 1),
-+	PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x140, 0x10, 4, 1),
-+	PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x140, 0x10, 3, 1),
-+	PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x140, 0x10, 2, 1),
-+	PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0x140, 0x10, 15, 1),
-+	PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0x140, 0x10, 12, 1),
-+	PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0x140, 0x10, 13, 1),
-+	PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0x140, 0x10, 14, 1),
-+	PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0x140, 0x10, 16, 1),
-+
-+	PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0xe0, 0x10, 14, 1),
-+	PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0xe0, 0x10, 15, 1),
-+	PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0xe0, 0x10, 13, 1),
-+	PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0xe0, 0x10, 4, 1),
-+	PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0xe0, 0x10, 5, 1),
-+	PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0xe0, 0x10, 6, 1),
-+	PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0xe0, 0x10, 3, 1),
-+	PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0xe0, 0x10, 7, 1),
-+	PIN_FIELD_BASE(63, 63, IOCFG_TR_BASE, 0xe0, 0x10, 20, 1),
-+	PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0xe0, 0x10, 8, 1),
-+	PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0xe0, 0x10, 9, 1),
-+	PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0xe0, 0x10, 10, 1),
-+	PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0xe0, 0x10, 11, 1),
-+	PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0xe0, 0x10, 12, 1),
-+
-+	PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0xc0, 0x10, 1, 1),
-+	PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0xc0, 0x10, 2, 1),
-+	PIN_FIELD_BASE(71, 71, IOCFG_TL_BASE, 0xc0, 0x10, 5, 1),
-+	PIN_FIELD_BASE(72, 72, IOCFG_TL_BASE, 0xc0, 0x10, 6, 1),
-+
-+	PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0xb0, 0x10, 10, 1),
-+	PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0xb0, 0x10, 1, 1),
-+	PIN_FIELD_BASE(75, 75, IOCFG_LB_BASE, 0xb0, 0x10, 11, 1),
-+	PIN_FIELD_BASE(76, 76, IOCFG_LB_BASE, 0xb0, 0x10, 9, 1),
-+	PIN_FIELD_BASE(77, 77, IOCFG_LB_BASE, 0xb0, 0x10, 2, 1),
-+	PIN_FIELD_BASE(78, 78, IOCFG_LB_BASE, 0xb0, 0x10, 0, 1),
-+	PIN_FIELD_BASE(79, 79, IOCFG_LB_BASE, 0xb0, 0x10, 12, 1),
-+
-+	PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0xe0, 0x10, 18, 1),
-+	PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0xe0, 0x10, 19, 1),
-+	PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0xe0, 0x10, 16, 1),
-+	PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0xe0, 0x10, 17, 1),
-+};
-+
-+static const struct mtk_pin_field_calc mt7988_pin_pu_range[] = {
-+	PIN_FIELD_BASE(7, 7, IOCFG_LB_BASE, 0x60, 0x10, 5, 1),
-+	PIN_FIELD_BASE(8, 8, IOCFG_LB_BASE, 0x60, 0x10, 4, 1),
-+	PIN_FIELD_BASE(9, 9, IOCFG_LB_BASE, 0x60, 0x10, 3, 1),
-+	PIN_FIELD_BASE(10, 10, IOCFG_LB_BASE, 0x60, 0x10, 2, 1),
-+
-+	PIN_FIELD_BASE(13, 13, IOCFG_TR_BASE, 0x70, 0x10, 0, 1),
-+	PIN_FIELD_BASE(14, 14, IOCFG_TR_BASE, 0x70, 0x10, 1, 1),
-+	PIN_FIELD_BASE(63, 63, IOCFG_TR_BASE, 0x70, 0x10, 2, 1),
-+
-+	PIN_FIELD_BASE(75, 75, IOCFG_LB_BASE, 0x60, 0x10, 7, 1),
-+	PIN_FIELD_BASE(76, 76, IOCFG_LB_BASE, 0x60, 0x10, 6, 1),
-+	PIN_FIELD_BASE(77, 77, IOCFG_LB_BASE, 0x60, 0x10, 1, 1),
-+	PIN_FIELD_BASE(78, 78, IOCFG_LB_BASE, 0x60, 0x10, 0, 1),
-+	PIN_FIELD_BASE(79, 79, IOCFG_LB_BASE, 0x60, 0x10, 8, 1),
-+};
-+
-+static const struct mtk_pin_field_calc mt7988_pin_pd_range[] = {
-+	PIN_FIELD_BASE(7, 7, IOCFG_LB_BASE, 0x40, 0x10, 5, 1),
-+	PIN_FIELD_BASE(8, 8, IOCFG_LB_BASE, 0x40, 0x10, 4, 1),
-+	PIN_FIELD_BASE(9, 9, IOCFG_LB_BASE, 0x40, 0x10, 3, 1),
-+	PIN_FIELD_BASE(10, 10, IOCFG_LB_BASE, 0x40, 0x10, 2, 1),
-+
-+	PIN_FIELD_BASE(13, 13, IOCFG_TR_BASE, 0x50, 0x10, 0, 1),
-+	PIN_FIELD_BASE(14, 14, IOCFG_TR_BASE, 0x50, 0x10, 1, 1),
-+
-+	PIN_FIELD_BASE(15, 15, IOCFG_TL_BASE, 0x40, 0x10, 4, 1),
-+	PIN_FIELD_BASE(16, 16, IOCFG_TL_BASE, 0x40, 0x10, 5, 1),
-+	PIN_FIELD_BASE(17, 17, IOCFG_TL_BASE, 0x40, 0x10, 0, 1),
-+	PIN_FIELD_BASE(18, 18, IOCFG_TL_BASE, 0x40, 0x10, 1, 1),
-+
-+	PIN_FIELD_BASE(63, 63, IOCFG_TR_BASE, 0x50, 0x10, 2, 1),
-+	PIN_FIELD_BASE(71, 71, IOCFG_TL_BASE, 0x40, 0x10, 2, 1),
-+	PIN_FIELD_BASE(72, 72, IOCFG_TL_BASE, 0x40, 0x10, 3, 1),
-+
-+	PIN_FIELD_BASE(75, 75, IOCFG_LB_BASE, 0x40, 0x10, 7, 1),
-+	PIN_FIELD_BASE(76, 76, IOCFG_LB_BASE, 0x40, 0x10, 6, 1),
-+	PIN_FIELD_BASE(77, 77, IOCFG_LB_BASE, 0x40, 0x10, 1, 1),
-+	PIN_FIELD_BASE(78, 78, IOCFG_LB_BASE, 0x40, 0x10, 0, 1),
-+	PIN_FIELD_BASE(79, 79, IOCFG_LB_BASE, 0x40, 0x10, 8, 1),
-+};
-+
-+static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = {
-+	PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0x00, 0x10, 21, 3),
-+	PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0x00, 0x10, 24, 3),
-+	PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0x00, 0x10, 15, 3),
-+	PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x00, 0x10, 18, 3),
-+	PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x00, 0x10, 0, 3),
-+	PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x00, 0x10, 9, 3),
-+	PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x00, 0x10, 12, 3),
-+
-+	PIN_FIELD_BASE(7, 7, IOCFG_LB_BASE, 0x00, 0x10, 24, 3),
-+	PIN_FIELD_BASE(8, 8, IOCFG_LB_BASE, 0x00, 0x10, 28, 3),
-+	PIN_FIELD_BASE(9, 9, IOCFG_LB_BASE, 0x00, 0x10, 15, 3),
-+	PIN_FIELD_BASE(10, 10, IOCFG_LB_BASE, 0x00, 0x10, 9, 3),
-+
-+	PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0x00, 0x10, 0, 3),
-+	PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0x20, 0x10, 3, 3),
-+	PIN_FIELD_BASE(13, 13, IOCFG_TR_BASE, 0x00, 0x10, 3, 3),
-+	PIN_FIELD_BASE(14, 14, IOCFG_TR_BASE, 0x00, 0x10, 6, 3),
-+
-+	PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0x00, 0x10, 21, 3),
-+	PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0x00, 0x10, 12, 3),
-+
-+	PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0x10, 0x10, 21, 3),
-+	PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0x20, 0x10, 9, 3),
-+	PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0x20, 0x10, 0, 3),
-+	PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0x10, 0x10, 27, 3),
-+	PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0x20, 0x10, 3, 3),
-+	PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0x20, 0x10, 6, 3),
-+	PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0x10, 0x10, 24, 3),
-+	PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0x20, 0x10, 15, 3),
-+	PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0x20, 0x10, 18, 3),
-+	PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0x20, 0x10, 21, 3),
-+	PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0x20, 0x10, 12, 3),
-+	PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0x20, 0x10, 24, 3),
-+	PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0x30, 0x10, 6, 3),
-+	PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0x30, 0x10, 3, 3),
-+	PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0x20, 0x10, 27, 3),
-+	PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0x30, 0x10, 0, 3),
-+	PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0x30, 0x10, 9, 3),
-+	PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0x10, 0x10, 3, 3),
-+	PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x10, 0x10, 0, 3),
-+	PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x00, 0x10, 0, 3),
-+	PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x00, 0x10, 3, 3),
-+	PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x00, 0x10, 27, 3),
-+	PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x00, 0x10, 24, 3),
-+	PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x00, 0x10, 21, 3),
-+	PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x00, 0x10, 18, 3),
-+	PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x00, 0x10, 15, 3),
-+	PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x00, 0x10, 12, 3),
-+	PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x00, 0x10, 9, 3),
-+	PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x00, 0x10, 6, 3),
-+	PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0x10, 0x10, 15, 3),
-+	PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0x10, 0x10, 6, 3),
-+	PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0x10, 0x10, 9, 3),
-+	PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0x10, 0x10, 12, 3),
-+	PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0x10, 0x10, 18, 3),
-+
-+	PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0x10, 0x10, 12, 3),
-+	PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0x10, 0x10, 15, 3),
-+	PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0x10, 0x10, 9, 3),
-+	PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0x00, 0x10, 12, 3),
-+	PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0x00, 0x10, 15, 3),
-+	PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0x00, 0x10, 18, 3),
-+	PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0x00, 0x10, 9, 3),
-+	PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0x00, 0x10, 21, 3),
-+	PIN_FIELD_BASE(63, 63, IOCFG_TR_BASE, 0x20, 0x10, 0, 3),
-+	PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0x00, 0x10, 24, 3),
-+	PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0x00, 0x10, 27, 3),
-+	PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0x10, 0x10, 0, 3),
-+	PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0x10, 0x10, 3, 3),
-+	PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0x10, 0x10, 6, 3),
-+
-+	PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0x00, 0x10, 3, 3),
-+	PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0x00, 0x10, 6, 3),
-+
-+	PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0x10, 0x10, 0, 3),
-+	PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0x00, 0x10, 3, 3),
-+	PIN_FIELD_BASE(75, 75, IOCFG_LB_BASE, 0x10, 0x10, 3, 3),
-+	PIN_FIELD_BASE(76, 76, IOCFG_LB_BASE, 0x00, 0x10, 27, 3),
-+	PIN_FIELD_BASE(77, 77, IOCFG_LB_BASE, 0x00, 0x10, 6, 3),
-+	PIN_FIELD_BASE(78, 78, IOCFG_LB_BASE, 0x00, 0x10, 0, 3),
-+	PIN_FIELD_BASE(79, 79, IOCFG_LB_BASE, 0x10, 0x10, 6, 3),
-+
-+	PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x10, 0x10, 24, 3),
-+	PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x10, 0x10, 27, 3),
-+	PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x10, 0x10, 18, 3),
-+	PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x10, 0x10, 21, 3),
-+};
-+
-+static const struct mtk_pin_field_calc mt7988_pin_pupd_range[] = {
-+	PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0x50, 0x10, 7, 1),
-+	PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0x50, 0x10, 8, 1),
-+	PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0x50, 0x10, 5, 1),
-+	PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x50, 0x10, 6, 1),
-+	PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x50, 0x10, 0, 1),
-+	PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x50, 0x10, 3, 1),
-+	PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x50, 0x10, 4, 1),
-+
-+	PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0x60, 0x10, 0, 1),
-+	PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0x60, 0x10, 18, 1),
-+
-+	PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0x50, 0x10, 2, 1),
-+	PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0x50, 0x10, 1, 1),
-+
-+	PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0x70, 0x10, 17, 1),
-+	PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0x70, 0x10, 23, 1),
-+	PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0x70, 0x10, 20, 1),
-+	PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0x70, 0x10, 19, 1),
-+	PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0x70, 0x10, 21, 1),
-+	PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0x70, 0x10, 22, 1),
-+	PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0x70, 0x10, 18, 1),
-+	PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0x70, 0x10, 25, 1),
-+	PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0x70, 0x10, 26, 1),
-+	PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0x70, 0x10, 27, 1),
-+	PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0x70, 0x10, 24, 1),
-+	PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0x70, 0x10, 28, 1),
-+	PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0x80, 0x10, 0, 1),
-+	PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0x70, 0x10, 31, 1),
-+	PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0x70, 0x10, 29, 1),
-+	PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0x70, 0x10, 30, 1),
-+	PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0x80, 0x10, 1, 1),
-+	PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0x70, 0x10, 11, 1),
-+	PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x70, 0x10, 10, 1),
-+	PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x70, 0x10, 0, 1),
-+	PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x70, 0x10, 1, 1),
-+	PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x70, 0x10, 9, 1),
-+	PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x70, 0x10, 8, 1),
-+	PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x70, 0x10, 7, 1),
-+	PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x70, 0x10, 6, 1),
-+	PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x70, 0x10, 5, 1),
-+	PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x70, 0x10, 4, 1),
-+	PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x70, 0x10, 3, 1),
-+	PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x70, 0x10, 2, 1),
-+	PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0x70, 0x10, 15, 1),
-+	PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0x70, 0x10, 12, 1),
-+	PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0x70, 0x10, 13, 1),
-+	PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0x70, 0x10, 14, 1),
-+	PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0x70, 0x10, 16, 1),
-+
-+	PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0x60, 0x10, 12, 1),
-+	PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0x60, 0x10, 13, 1),
-+	PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0x60, 0x10, 11, 1),
-+	PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0x60, 0x10, 2, 1),
-+	PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0x60, 0x10, 3, 1),
-+	PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0x60, 0x10, 4, 1),
-+	PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0x60, 0x10, 1, 1),
-+	PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0x60, 0x10, 5, 1),
-+	PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0x60, 0x10, 6, 1),
-+	PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0x60, 0x10, 7, 1),
-+	PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0x60, 0x10, 8, 1),
-+	PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0x60, 0x10, 9, 1),
-+	PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0x60, 0x10, 10, 1),
-+
-+	PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0x50, 0x10, 1, 1),
-+	PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0x50, 0x10, 2, 1),
-+
-+	PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0x50, 0x10, 3, 1),
-+	PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0x50, 0x10, 0, 1),
-+
-+	PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x60, 0x10, 16, 1),
-+	PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x60, 0x10, 17, 1),
-+	PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x60, 0x10, 14, 1),
-+	PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x60, 0x10, 15, 1),
-+};
-+
-+static const struct mtk_pin_field_calc mt7988_pin_r0_range[] = {
-+	PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0x60, 0x10, 7, 1),
-+	PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0x60, 0x10, 8, 1),
-+	PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0x60, 0x10, 5, 1),
-+	PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x60, 0x10, 6, 1),
-+	PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x60, 0x10, 0, 1),
-+	PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x60, 0x10, 3, 1),
-+	PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x60, 0x10, 4, 1),
-+
-+	PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0x80, 0x10, 0, 1),
-+	PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0x80, 0x10, 18, 1),
-+
-+	PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0x70, 0x10, 2, 1),
-+	PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0x70, 0x10, 1, 1),
-+
-+	PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0x90, 0x10, 17, 1),
-+	PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0x90, 0x10, 23, 1),
-+	PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0x90, 0x10, 20, 1),
-+	PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0x90, 0x10, 19, 1),
-+	PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0x90, 0x10, 21, 1),
-+	PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0x90, 0x10, 22, 1),
-+	PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0x90, 0x10, 18, 1),
-+	PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0x90, 0x10, 25, 1),
-+	PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0x90, 0x10, 26, 1),
-+	PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0x90, 0x10, 27, 1),
-+	PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0x90, 0x10, 24, 1),
-+	PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0x90, 0x10, 28, 1),
-+	PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0xa0, 0x10, 0, 1),
-+	PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0x90, 0x10, 31, 1),
-+	PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0x90, 0x10, 29, 1),
-+	PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0x90, 0x10, 30, 1),
-+	PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0xa0, 0x10, 1, 1),
-+	PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0x90, 0x10, 11, 1),
-+	PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x90, 0x10, 10, 1),
-+	PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x90, 0x10, 0, 1),
-+	PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x90, 0x10, 1, 1),
-+	PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x90, 0x10, 9, 1),
-+	PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x90, 0x10, 8, 1),
-+	PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x90, 0x10, 7, 1),
-+	PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x90, 0x10, 6, 1),
-+	PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x90, 0x10, 5, 1),
-+	PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x90, 0x10, 4, 1),
-+	PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x90, 0x10, 3, 1),
-+	PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x90, 0x10, 2, 1),
-+	PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0x90, 0x10, 15, 1),
-+	PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0x90, 0x10, 12, 1),
-+	PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0x90, 0x10, 13, 1),
-+	PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0x90, 0x10, 14, 1),
-+	PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0x90, 0x10, 16, 1),
-+
-+	PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0x80, 0x10, 12, 1),
-+	PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0x80, 0x10, 13, 1),
-+	PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0x80, 0x10, 11, 1),
-+	PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0x80, 0x10, 2, 1),
-+	PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0x80, 0x10, 3, 1),
-+	PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0x80, 0x10, 4, 1),
-+	PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0x80, 0x10, 1, 1),
-+	PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0x80, 0x10, 5, 1),
-+	PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0x80, 0x10, 6, 1),
-+	PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0x80, 0x10, 7, 1),
-+	PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0x80, 0x10, 8, 1),
-+	PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0x80, 0x10, 9, 1),
-+	PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0x80, 0x10, 10, 1),
-+
-+	PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0x60, 0x10, 1, 1),
-+	PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0x60, 0x10, 2, 1),
-+
-+	PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0x70, 0x10, 3, 1),
-+	PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0x70, 0x10, 0, 1),
-+
-+	PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x80, 0x10, 16, 1),
-+	PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x80, 0x10, 17, 1),
-+	PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x80, 0x10, 14, 1),
-+	PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x80, 0x10, 15, 1),
-+};
-+
-+static const struct mtk_pin_field_calc mt7988_pin_r1_range[] = {
-+	PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0x70, 0x10, 7, 1),
-+	PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0x70, 0x10, 8, 1),
-+	PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0x70, 0x10, 5, 1),
-+	PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x70, 0x10, 6, 1),
-+	PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x70, 0x10, 0, 1),
-+	PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x70, 0x10, 3, 1),
-+	PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x70, 0x10, 4, 1),
-+
-+	PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0x90, 0x10, 0, 1),
-+	PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0x90, 0x10, 18, 1),
-+
-+	PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0x80, 0x10, 2, 1),
-+	PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0x80, 0x10, 1, 1),
-+
-+	PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0xb0, 0x10, 17, 1),
-+	PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0xb0, 0x10, 23, 1),
-+	PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0xb0, 0x10, 20, 1),
-+	PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0xb0, 0x10, 19, 1),
-+	PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0xb0, 0x10, 21, 1),
-+	PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0xb0, 0x10, 22, 1),
-+	PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0xb0, 0x10, 18, 1),
-+	PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0xb0, 0x10, 25, 1),
-+	PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0xb0, 0x10, 26, 1),
-+	PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0xb0, 0x10, 27, 1),
-+	PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0xb0, 0x10, 24, 1),
-+	PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0xb0, 0x10, 28, 1),
-+	PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0xc0, 0x10, 0, 1),
-+	PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0xb0, 0x10, 31, 1),
-+	PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0xb0, 0x10, 29, 1),
-+	PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0xb0, 0x10, 30, 1),
-+	PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0xc0, 0x10, 1, 1),
-+	PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0xb0, 0x10, 11, 1),
-+	PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0xb0, 0x10, 10, 1),
-+	PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0xb0, 0x10, 0, 1),
-+	PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0xb0, 0x10, 1, 1),
-+	PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0xb0, 0x10, 9, 1),
-+	PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0xb0, 0x10, 8, 1),
-+	PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0xb0, 0x10, 7, 1),
-+	PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0xb0, 0x10, 6, 1),
-+	PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0xb0, 0x10, 5, 1),
-+	PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0xb0, 0x10, 4, 1),
-+	PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0xb0, 0x10, 3, 1),
-+	PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0xb0, 0x10, 2, 1),
-+	PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0xb0, 0x10, 15, 1),
-+	PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0xb0, 0x10, 12, 1),
-+	PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0xb0, 0x10, 13, 1),
-+	PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0xb0, 0x10, 14, 1),
-+	PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0xb0, 0x10, 16, 1),
-+
-+	PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0x90, 0x10, 12, 1),
-+	PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0x90, 0x10, 13, 1),
-+	PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0x90, 0x10, 11, 1),
-+	PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0x90, 0x10, 2, 1),
-+	PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0x90, 0x10, 3, 1),
-+	PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0x90, 0x10, 4, 1),
-+	PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0x90, 0x10, 1, 1),
-+	PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0x90, 0x10, 5, 1),
-+	PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0x90, 0x10, 6, 1),
-+	PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0x90, 0x10, 7, 1),
-+	PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0x90, 0x10, 8, 1),
-+	PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0x90, 0x10, 9, 1),
-+	PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0x90, 0x10, 10, 1),
-+
-+	PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0x70, 0x10, 1, 1),
-+	PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0x70, 0x10, 2, 1),
-+
-+	PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0x80, 0x10, 3, 1),
-+	PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0x80, 0x10, 0, 1),
-+
-+	PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x90, 0x10, 16, 1),
-+	PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x90, 0x10, 17, 1),
-+	PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x90, 0x10, 14, 1),
-+	PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x90, 0x10, 15, 1),
-+};
-+
-+static const struct mtk_pin_reg_calc mt7988_reg_cals[] = {
-+	[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7988_pin_mode_range),
-+	[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7988_pin_dir_range),
-+	[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7988_pin_di_range),
-+	[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7988_pin_do_range),
-+	[PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7988_pin_smt_range),
-+	[PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7988_pin_ies_range),
-+	[PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7988_pin_pu_range),
-+	[PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7988_pin_pd_range),
-+	[PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7988_pin_drv_range),
-+	[PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7988_pin_pupd_range),
-+	[PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7988_pin_r0_range),
-+	[PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7988_pin_r1_range),
-+};
-+
-+static const struct mtk_pin_desc mt7988_pins[] = {
-+	MT7988_TYPE0_PIN(0, "UART2_RXD"),
-+	MT7988_TYPE0_PIN(1, "UART2_TXD"),
-+	MT7988_TYPE0_PIN(2, "UART2_CTS"),
-+	MT7988_TYPE0_PIN(3, "UART2_RTS"),
-+	MT7988_TYPE0_PIN(4, "GPIO_A"),
-+	MT7988_TYPE0_PIN(5, "SMI_0_MDC"),
-+	MT7988_TYPE0_PIN(6, "SMI_0_MDIO"),
-+	MT7988_TYPE1_PIN(7, "PCIE30_2L_0_WAKE_N"),
-+	MT7988_TYPE1_PIN(8, "PCIE30_2L_0_CLKREQ_N"),
-+	MT7988_TYPE1_PIN(9, "PCIE30_1L_1_WAKE_N"),
-+	MT7988_TYPE1_PIN(10, "PCIE30_1L_1_CLKREQ_N"),
-+	MT7988_TYPE0_PIN(11, "GPIO_P"),
-+	MT7988_TYPE0_PIN(12, "WATCHDOG"),
-+	MT7988_TYPE1_PIN(13, "GPIO_RESET"),
-+	MT7988_TYPE1_PIN(14, "GPIO_WPS"),
-+	MT7988_TYPE2_PIN(15, "PMIC_I2C_SCL"),
-+	MT7988_TYPE2_PIN(16, "PMIC_I2C_SDA"),
-+	MT7988_TYPE2_PIN(17, "I2C_1_SCL"),
-+	MT7988_TYPE2_PIN(18, "I2C_1_SDA"),
-+	MT7988_TYPE0_PIN(19, "PCIE30_2L_0_PRESET_N"),
-+	MT7988_TYPE0_PIN(20, "PCIE30_1L_1_PRESET_N"),
-+	MT7988_TYPE0_PIN(21, "PWMD1"),
-+	MT7988_TYPE0_PIN(22, "SPI0_WP"),
-+	MT7988_TYPE0_PIN(23, "SPI0_HOLD"),
-+	MT7988_TYPE0_PIN(24, "SPI0_CSB"),
-+	MT7988_TYPE0_PIN(25, "SPI0_MISO"),
-+	MT7988_TYPE0_PIN(26, "SPI0_MOSI"),
-+	MT7988_TYPE0_PIN(27, "SPI0_CLK"),
-+	MT7988_TYPE0_PIN(28, "SPI1_CSB"),
-+	MT7988_TYPE0_PIN(29, "SPI1_MISO"),
-+	MT7988_TYPE0_PIN(30, "SPI1_MOSI"),
-+	MT7988_TYPE0_PIN(31, "SPI1_CLK"),
-+	MT7988_TYPE0_PIN(32, "SPI2_CLK"),
-+	MT7988_TYPE0_PIN(33, "SPI2_MOSI"),
-+	MT7988_TYPE0_PIN(34, "SPI2_MISO"),
-+	MT7988_TYPE0_PIN(35, "SPI2_CSB"),
-+	MT7988_TYPE0_PIN(36, "SPI2_HOLD"),
-+	MT7988_TYPE0_PIN(37, "SPI2_WP"),
-+	MT7988_TYPE0_PIN(38, "EMMC_RSTB"),
-+	MT7988_TYPE0_PIN(39, "EMMC_DSL"),
-+	MT7988_TYPE0_PIN(40, "EMMC_CK"),
-+	MT7988_TYPE0_PIN(41, "EMMC_CMD"),
-+	MT7988_TYPE0_PIN(42, "EMMC_DATA_7"),
-+	MT7988_TYPE0_PIN(43, "EMMC_DATA_6"),
-+	MT7988_TYPE0_PIN(44, "EMMC_DATA_5"),
-+	MT7988_TYPE0_PIN(45, "EMMC_DATA_4"),
-+	MT7988_TYPE0_PIN(46, "EMMC_DATA_3"),
-+	MT7988_TYPE0_PIN(47, "EMMC_DATA_2"),
-+	MT7988_TYPE0_PIN(48, "EMMC_DATA_1"),
-+	MT7988_TYPE0_PIN(49, "EMMC_DATA_0"),
-+	MT7988_TYPE0_PIN(50, "PCM_FS_I2S_LRCK"),
-+	MT7988_TYPE0_PIN(51, "PCM_CLK_I2S_BCLK"),
-+	MT7988_TYPE0_PIN(52, "PCM_DRX_I2S_DIN"),
-+	MT7988_TYPE0_PIN(53, "PCM_DTX_I2S_DOUT"),
-+	MT7988_TYPE0_PIN(54, "PCM_MCK_I2S_MCLK"),
-+	MT7988_TYPE0_PIN(55, "UART0_RXD"),
-+	MT7988_TYPE0_PIN(56, "UART0_TXD"),
-+	MT7988_TYPE0_PIN(57, "PWMD0"),
-+	MT7988_TYPE0_PIN(58, "JTAG_JTDI"),
-+	MT7988_TYPE0_PIN(59, "JTAG_JTDO"),
-+	MT7988_TYPE0_PIN(60, "JTAG_JTMS"),
-+	MT7988_TYPE0_PIN(61, "JTAG_JTCLK"),
-+	MT7988_TYPE0_PIN(62, "JTAG_JTRST_N"),
-+	MT7988_TYPE1_PIN(63, "USB_DRV_VBUS_P1"),
-+	MT7988_TYPE0_PIN(64, "LED_A"),
-+	MT7988_TYPE0_PIN(65, "LED_B"),
-+	MT7988_TYPE0_PIN(66, "LED_C"),
-+	MT7988_TYPE0_PIN(67, "LED_D"),
-+	MT7988_TYPE0_PIN(68, "LED_E"),
-+	MT7988_TYPE0_PIN(69, "GPIO_B"),
-+	MT7988_TYPE0_PIN(70, "GPIO_C"),
-+	MT7988_TYPE2_PIN(71, "I2C_2_SCL"),
-+	MT7988_TYPE2_PIN(72, "I2C_2_SDA"),
-+	MT7988_TYPE0_PIN(73, "PCIE30_2L_1_PRESET_N"),
-+	MT7988_TYPE0_PIN(74, "PCIE30_1L_0_PRESET_N"),
-+	MT7988_TYPE1_PIN(75, "PCIE30_2L_1_WAKE_N"),
-+	MT7988_TYPE1_PIN(76, "PCIE30_2L_1_CLKREQ_N"),
-+	MT7988_TYPE1_PIN(77, "PCIE30_1L_0_WAKE_N"),
-+	MT7988_TYPE1_PIN(78, "PCIE30_1L_0_CLKREQ_N"),
-+	MT7988_TYPE1_PIN(79, "USB_DRV_VBUS_P0"),
-+	MT7988_TYPE0_PIN(80, "UART1_RXD"),
-+	MT7988_TYPE0_PIN(81, "UART1_TXD"),
-+	MT7988_TYPE0_PIN(82, "UART1_CTS"),
-+	MT7988_TYPE0_PIN(83, "UART1_RTS"),
-+};
-+
-+/* jtag */
-+static const int mt7988_tops_jtag0_0_pins[] = { 0, 1, 2, 3, 4 };
-+static const int mt7988_tops_jtag0_0_funcs[] = { 2, 2, 2, 2, 2 };
-+
-+static const int mt7988_wo0_jtag_pins[] = { 50, 51, 52, 53, 54 };
-+static const int mt7988_wo0_jtag_funcs[] = { 3, 3, 3, 3, 3 };
-+
-+static const int mt7988_wo1_jtag_pins[] = { 50, 51, 52, 53, 54 };
-+static const int mt7988_wo1_jtag_funcs[] = { 4, 4, 4, 4, 4 };
-+
-+static const int mt7988_wo2_jtag_pins[] = { 50, 51, 52, 53, 54 };
-+static const int mt7988_wo2_jtag_funcs[] = { 5, 5, 5, 5, 5 };
-+
-+static const int mt7988_jtag_pins[] = { 58, 59, 60, 61, 62 };
-+static const int mt7988_jtag_funcs[] = { 1, 1, 1, 1, 1 };
-+
-+static const int mt7988_tops_jtag0_1_pins[] = { 58, 59, 60, 61, 62 };
-+static const int mt7988_tops_jtag0_1_funcs[] = { 4, 4, 4, 4, 4 };
-+
-+/* int_usxgmii */
-+static const int mt7988_int_usxgmii_pins[] = { 2, 3 };
-+static const int mt7988_int_usxgmii_funcs[] = { 3, 3 };
-+
-+/* pwm */
-+static const int mt7988_pwm0_pins[] = { 57 };
-+static const int mt7988_pwm0_funcs[] = { 1 };
-+
-+static const int mt7988_pwm1_pins[] = { 21 };
-+static const int mt7988_pwm1_funcs[] = { 1 };
-+
-+static const int mt7988_pwm2_pins[] = { 80 };
-+static const int mt7988_pwm2_funcs[] = { 2 };
-+
-+static const int mt7988_pwm3_pins[] = { 81 };
-+static const int mt7988_pwm3_funcs[] = { 2 };
-+
-+static const int mt7988_pwm4_pins[] = { 82 };
-+static const int mt7988_pwm4_funcs[] = { 2 };
-+
-+static const int mt7988_pwm5_pins[] = { 83 };
-+static const int mt7988_pwm5_funcs[] = { 2 };
-+
-+static const int mt7988_pwm6_pins[] = { 69 };
-+static const int mt7988_pwm6_funcs[] = { 3 };
-+
-+static const int mt7988_pwm7_pins[] = { 70 };
-+static const int mt7988_pwm7_funcs[] = { 3 };
-+
-+/* dfd */
-+static const int mt7988_dfd_pins[] = { 0, 1, 2, 3, 4 };
-+static const int mt7988_dfd_funcs[] = { 4, 4, 4, 4, 4 };
-+
-+/* i2c */
-+static const int mt7988_xfi_phy0_i2c0_pins[] = { 0, 1 };
-+static const int mt7988_xfi_phy0_i2c0_funcs[] = { 5, 5 };
-+
-+static const int mt7988_xfi_phy1_i2c0_pins[] = { 0, 1 };
-+static const int mt7988_xfi_phy1_i2c0_funcs[] = { 6, 6 };
-+
-+static const int mt7988_xfi_phy_pll_i2c0_pins[] = { 3, 4 };
-+static const int mt7988_xfi_phy_pll_i2c0_funcs[] = { 5, 5 };
-+
-+static const int mt7988_xfi_phy_pll_i2c1_pins[] = { 3, 4 };
-+static const int mt7988_xfi_phy_pll_i2c1_funcs[] = { 6, 6 };
-+
-+static const int mt7988_i2c0_0_pins[] = { 5, 6 };
-+static const int mt7988_i2c0_0_funcs[] = { 2, 2 };
-+
-+static const int mt7988_i2c1_sfp_pins[] = { 5, 6 };
-+static const int mt7988_i2c1_sfp_funcs[] = { 4, 4 };
-+
-+static const int mt7988_xfi_pextp_phy0_i2c_pins[] = { 5, 6 };
-+static const int mt7988_xfi_pextp_phy0_i2c_funcs[] = { 5, 5 };
-+
-+static const int mt7988_xfi_pextp_phy1_i2c_pins[] = { 5, 6 };
-+static const int mt7988_xfi_pextp_phy1_i2c_funcs[] = { 6, 6 };
-+
-+static const int mt7988_i2c0_1_pins[] = { 15, 16 };
-+static const int mt7988_i2c0_1_funcs[] = { 1, 1 };
-+
-+static const int mt7988_u30_phy_i2c0_pins[] = { 15, 16 };
-+static const int mt7988_u30_phy_i2c0_funcs[] = { 2, 2 };
-+
-+static const int mt7988_u32_phy_i2c0_pins[] = { 15, 16 };
-+static const int mt7988_u32_phy_i2c0_funcs[] = { 3, 3 };
-+
-+static const int mt7988_xfi_phy0_i2c1_pins[] = { 15, 16 };
-+static const int mt7988_xfi_phy0_i2c1_funcs[] = { 5, 5 };
-+
-+static const int mt7988_xfi_phy1_i2c1_pins[] = { 15, 16 };
-+static const int mt7988_xfi_phy1_i2c1_funcs[] = { 6, 6 };
-+
-+static const int mt7988_xfi_phy_pll_i2c2_pins[] = { 15, 16 };
-+static const int mt7988_xfi_phy_pll_i2c2_funcs[] = { 7, 7 };
-+
-+static const int mt7988_i2c1_0_pins[] = { 17, 18 };
-+static const int mt7988_i2c1_0_funcs[] = { 1, 1 };
-+
-+static const int mt7988_u30_phy_i2c1_pins[] = { 17, 18 };
-+static const int mt7988_u30_phy_i2c1_funcs[] = { 2, 2 };
-+
-+static const int mt7988_u32_phy_i2c1_pins[] = { 17, 18 };
-+static const int mt7988_u32_phy_i2c1_funcs[] = { 3, 3 };
-+
-+static const int mt7988_xfi_phy_pll_i2c3_pins[] = { 17, 18 };
-+static const int mt7988_xfi_phy_pll_i2c3_funcs[] = { 4, 4 };
-+
-+static const int mt7988_sgmii0_i2c_pins[] = { 17, 18 };
-+static const int mt7988_sgmii0_i2c_funcs[] = { 5, 5 };
-+
-+static const int mt7988_sgmii1_i2c_pins[] = { 17, 18 };
-+static const int mt7988_sgmii1_i2c_funcs[] = { 6, 6 };
-+
-+static const int mt7988_i2c1_2_pins[] = { 69, 70 };
-+static const int mt7988_i2c1_2_funcs[] = { 2, 2 };
-+
-+static const int mt7988_i2c2_0_pins[] = { 69, 70 };
-+static const int mt7988_i2c2_0_funcs[] = { 4, 4 };
-+
-+static const int mt7988_i2c2_1_pins[] = { 71, 72 };
-+static const int mt7988_i2c2_1_funcs[] = { 1, 1 };
-+
-+/* eth */
-+static const int mt7988_mdc_mdio0_pins[] = { 5, 6 };
-+static const int mt7988_mdc_mdio0_funcs[] = { 1, 1 };
-+
-+static const int mt7988_2p5g_ext_mdio_pins[] = { 28, 29 };
-+static const int mt7988_2p5g_ext_mdio_funcs[] = { 6, 6 };
-+
-+static const int mt7988_gbe_ext_mdio_pins[] = { 30, 31 };
-+static const int mt7988_gbe_ext_mdio_funcs[] = { 6, 6 };
-+
-+static const int mt7988_mdc_mdio1_pins[] = { 69, 70 };
-+static const int mt7988_mdc_mdio1_funcs[] = { 1, 1 };
-+
-+/* pcie */
-+static const int mt7988_pcie_wake_n0_0_pins[] = { 7 };
-+static const int mt7988_pcie_wake_n0_0_funcs[] = { 1 };
-+
-+static const int mt7988_pcie_clk_req_n0_0_pins[] = { 8 };
-+static const int mt7988_pcie_clk_req_n0_0_funcs[] = { 1 };
-+
-+static const int mt7988_pcie_wake_n3_0_pins[] = { 9 };
-+static const int mt7988_pcie_wake_n3_0_funcs[] = { 1 };
-+
-+static const int mt7988_pcie_clk_req_n3_pins[] = { 10 };
-+static const int mt7988_pcie_clk_req_n3_funcs[] = { 1 };
-+
-+static const int mt7988_pcie_clk_req_n0_1_pins[] = { 10 };
-+static const int mt7988_pcie_clk_req_n0_1_funcs[] = { 2 };
-+
-+static const int mt7988_pcie_p0_phy_i2c_pins[] = { 7, 8 };
-+static const int mt7988_pcie_p0_phy_i2c_funcs[] = { 3, 3 };
-+
-+static const int mt7988_pcie_p1_phy_i2c_pins[] = { 7, 8 };
-+static const int mt7988_pcie_p1_phy_i2c_funcs[] = { 4, 4 };
-+
-+static const int mt7988_pcie_p3_phy_i2c_pins[] = { 9, 10 };
-+static const int mt7988_pcie_p3_phy_i2c_funcs[] = { 4, 4 };
-+
-+static const int mt7988_pcie_p2_phy_i2c_pins[] = { 7, 8 };
-+static const int mt7988_pcie_p2_phy_i2c_funcs[] = { 5, 5 };
-+
-+static const int mt7988_ckm_phy_i2c_pins[] = { 9, 10 };
-+static const int mt7988_ckm_phy_i2c_funcs[] = { 5, 5 };
-+
-+static const int mt7988_pcie_wake_n0_1_pins[] = { 13 };
-+static const int mt7988_pcie_wake_n0_1_funcs[] = { 2 };
-+
-+static const int mt7988_pcie_wake_n3_1_pins[] = { 14 };
-+static const int mt7988_pcie_wake_n3_1_funcs[] = { 2 };
-+
-+static const int mt7988_pcie_2l_0_pereset_pins[] = { 19 };
-+static const int mt7988_pcie_2l_0_pereset_funcs[] = { 1 };
-+
-+static const int mt7988_pcie_1l_1_pereset_pins[] = { 20 };
-+static const int mt7988_pcie_1l_1_pereset_funcs[] = { 1 };
-+
-+static const int mt7988_pcie_clk_req_n2_1_pins[] = { 63 };
-+static const int mt7988_pcie_clk_req_n2_1_funcs[] = { 2 };
-+
-+static const int mt7988_pcie_2l_1_pereset_pins[] = { 73 };
-+static const int mt7988_pcie_2l_1_pereset_funcs[] = { 1 };
-+
-+static const int mt7988_pcie_1l_0_pereset_pins[] = { 74 };
-+static const int mt7988_pcie_1l_0_pereset_funcs[] = { 1 };
-+
-+static const int mt7988_pcie_wake_n1_0_pins[] = { 75 };
-+static const int mt7988_pcie_wake_n1_0_funcs[] = { 1 };
-+
-+static const int mt7988_pcie_clk_req_n1_pins[] = { 76 };
-+static const int mt7988_pcie_clk_req_n1_funcs[] = { 1 };
-+
-+static const int mt7988_pcie_wake_n2_0_pins[] = { 77 };
-+static const int mt7988_pcie_wake_n2_0_funcs[] = { 1 };
-+
-+static const int mt7988_pcie_clk_req_n2_0_pins[] = { 78 };
-+static const int mt7988_pcie_clk_req_n2_0_funcs[] = { 1 };
-+
-+static const int mt7988_pcie_wake_n2_1_pins[] = { 79 };
-+static const int mt7988_pcie_wake_n2_1_funcs[] = { 2 };
-+
-+/* pmic */
-+static const int mt7988_pmic_pins[] = { 11 };
-+static const int mt7988_pmic_funcs[] = { 1 };
-+
-+/* watchdog */
-+static const int mt7988_watchdog_pins[] = { 12 };
-+static const int mt7988_watchdog_funcs[] = { 1 };
-+
-+/* spi */
-+static const int mt7988_spi0_wp_hold_pins[] = { 22, 23 };
-+static const int mt7988_spi0_wp_hold_funcs[] = { 1, 1 };
-+
-+static const int mt7988_spi0_pins[] = { 24, 25, 26, 27 };
-+static const int mt7988_spi0_funcs[] = { 1, 1, 1, 1 };
-+
-+static const int mt7988_spi1_pins[] = { 28, 29, 30, 31 };
-+static const int mt7988_spi1_funcs[] = { 1, 1, 1, 1 };
-+
-+static const int mt7988_spi2_pins[] = { 32, 33, 34, 35 };
-+static const int mt7988_spi2_funcs[] = { 1, 1, 1, 1 };
-+
-+static const int mt7988_spi2_wp_hold_pins[] = { 36, 37 };
-+static const int mt7988_spi2_wp_hold_funcs[] = { 1, 1 };
-+
-+/* flash */
-+static const int mt7988_snfi_pins[] = { 22, 23, 24, 25, 26, 27 };
-+static const int mt7988_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 };
-+
-+static const int mt7988_emmc_45_pins[] = {
-+	21, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37 };
-+static const int mt7988_emmc_45_funcs[] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5 };
-+
-+static const int mt7988_emmc_51_pins[] = {
-+	38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49 };
-+static const int mt7988_emmc_51_funcs[] = {
-+	1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
-+
-+/* uart */
-+static const int mt7988_uart2_pins[] = { 0, 1, 2, 3 };
-+static const int mt7988_uart2_funcs[] = { 1, 1, 1, 1 };
-+
-+static const int mt7988_tops_uart0_0_pins[] = { 22, 23 };
-+static const int mt7988_tops_uart0_0_funcs[] = { 3, 3 };
-+
-+static const int mt7988_uart2_0_pins[] = { 28, 29, 30, 31 };
-+static const int mt7988_uart2_0_funcs[] = { 2, 2, 2, 2 };
-+
-+static const int mt7988_uart1_0_pins[] = { 32, 33, 34, 35 };
-+static const int mt7988_uart1_0_funcs[] = { 2, 2, 2, 2 };
-+
-+static const int mt7988_uart2_1_pins[] = { 32, 33, 34, 35 };
-+static const int mt7988_uart2_1_funcs[] = { 3, 3, 3, 3 };
-+
-+static const int mt7988_net_wo0_uart_txd_0_pins[] = { 28 };
-+static const int mt7988_net_wo0_uart_txd_0_funcs[] = { 3 };
-+
-+static const int mt7988_net_wo1_uart_txd_0_pins[] = { 29 };
-+static const int mt7988_net_wo1_uart_txd_0_funcs[] = { 3 };
-+
-+static const int mt7988_net_wo2_uart_txd_0_pins[] = { 30 };
-+static const int mt7988_net_wo2_uart_txd_0_funcs[] = { 3 };
-+
-+static const int mt7988_tops_uart1_0_pins[] = { 28, 29 };
-+static const int mt7988_tops_uart1_0_funcs[] = { 4, 4 };
-+
-+static const int mt7988_tops_uart0_1_pins[] = { 30, 31 };
-+static const int mt7988_tops_uart0_1_funcs[] = { 4, 4 };
-+
-+static const int mt7988_tops_uart1_1_pins[] = { 36, 37 };
-+static const int mt7988_tops_uart1_1_funcs[] = { 3, 3 };
-+
-+static const int mt7988_uart0_pins[] = { 55, 56 };
-+static const int mt7988_uart0_funcs[] = { 1, 1 };
-+
-+static const int mt7988_tops_uart0_2_pins[] = { 55, 56 };
-+static const int mt7988_tops_uart0_2_funcs[] = { 2, 2 };
-+
-+static const int mt7988_uart2_2_pins[] = { 50, 51, 52, 53 };
-+static const int mt7988_uart2_2_funcs[] = { 2, 2, 2, 2 };
-+
-+static const int mt7988_uart1_1_pins[] = { 58, 59, 60, 61 };
-+static const int mt7988_uart1_1_funcs[] = { 2, 2, 2, 2 };
-+
-+static const int mt7988_uart2_3_pins[] = { 58, 59, 60, 61 };
-+static const int mt7988_uart2_3_funcs[] = { 3, 3, 3, 3 };
-+
-+static const int mt7988_uart1_2_pins[] = { 80, 81, 82, 83 };
-+static const int mt7988_uart1_2_funcs[] = { 1, 1, 1, 1 };
-+
-+static const int mt7988_tops_uart1_2_pins[] = { 80, 81 };
-+static const int mt7988_tops_uart1_2_funcs[] = { 4, 4, };
-+
-+static const int mt7988_net_wo0_uart_txd_1_pins[] = { 80 };
-+static const int mt7988_net_wo0_uart_txd_1_funcs[] = { 3 };
-+
-+static const int mt7988_net_wo1_uart_txd_1_pins[] = { 81 };
-+static const int mt7988_net_wo1_uart_txd_1_funcs[] = { 3 };
-+
-+static const int mt7988_net_wo2_uart_txd_1_pins[] = { 82 };
-+static const int mt7988_net_wo2_uart_txd_1_funcs[] = { 3 };
-+
-+/* udi */
-+static const int mt7988_udi_pins[] = { 32, 33, 34, 35, 36 };
-+static const int mt7988_udi_funcs[] = { 4, 4, 4, 4, 4 };
-+
-+/* pcm */
-+static const int mt7988_pcm_pins[] = { 50, 51, 52, 53, 54 };
-+static const int mt7988_pcm_funcs[] = { 1, 1, 1, 1, 1 };
-+
-+/* led */
-+static const int mt7988_gbe_led1_pins[] = { 58, 59, 60, 61 };
-+static const int mt7988_gbe_led1_funcs[] = { 6, 6, 6, 6 };
-+
-+static const int mt7988_2p5gbe_led1_pins[] = { 62 };
-+static const int mt7988_2p5gbe_led1_funcs[] = { 6 };
-+
-+static const int mt7988_gbe_led0_pins[] = { 64, 65, 66, 67 };
-+static const int mt7988_gbe_led0_funcs[] = { 1, 1, 1, 1 };
-+
-+static const int mt7988_2p5gbe_led0_pins[] = { 68 };
-+static const int mt7988_2p5gbe_led0_funcs[] = { 1 };
-+
-+/* usb */
-+static const int mt7988_drv_vbus_p1_pins[] = { 63 };
-+static const int mt7988_drv_vbus_p1_funcs[] = { 1 };
-+
-+static const int mt7988_drv_vbus_pins[] = { 79 };
-+static const int mt7988_drv_vbus_funcs[] = { 1 };
-+
-+static const struct mtk_group_desc mt7988_groups[] = {
-+	PINCTRL_PIN_GROUP("uart2", mt7988_uart2),
-+	PINCTRL_PIN_GROUP("tops_jtag0_0", mt7988_tops_jtag0_0),
-+	PINCTRL_PIN_GROUP("int_usxgmii", mt7988_int_usxgmii),
-+	PINCTRL_PIN_GROUP("dfd", mt7988_dfd),
-+	PINCTRL_PIN_GROUP("xfi_phy0_i2c0", mt7988_xfi_phy0_i2c0),
-+	PINCTRL_PIN_GROUP("xfi_phy1_i2c0", mt7988_xfi_phy1_i2c0),
-+	PINCTRL_PIN_GROUP("xfi_phy_pll_i2c0", mt7988_xfi_phy_pll_i2c0),
-+	PINCTRL_PIN_GROUP("xfi_phy_pll_i2c1", mt7988_xfi_phy_pll_i2c1),
-+	PINCTRL_PIN_GROUP("i2c0_0", mt7988_i2c0_0),
-+	PINCTRL_PIN_GROUP("i2c1_sfp", mt7988_i2c1_sfp),
-+	PINCTRL_PIN_GROUP("xfi_pextp_phy0_i2c", mt7988_xfi_pextp_phy0_i2c),
-+	PINCTRL_PIN_GROUP("xfi_pextp_phy1_i2c", mt7988_xfi_pextp_phy1_i2c),
-+	PINCTRL_PIN_GROUP("mdc_mdio0", mt7988_mdc_mdio0),
-+	PINCTRL_PIN_GROUP("pcie_wake_n0_0", mt7988_pcie_wake_n0_0),
-+	PINCTRL_PIN_GROUP("pcie_clk_req_n0_0", mt7988_pcie_clk_req_n0_0),
-+	PINCTRL_PIN_GROUP("pcie_wake_n3_0", mt7988_pcie_wake_n3_0),
-+	PINCTRL_PIN_GROUP("pcie_clk_req_n3", mt7988_pcie_clk_req_n3),
-+	PINCTRL_PIN_GROUP("pcie_clk_req_n0_1", mt7988_pcie_clk_req_n0_1),
-+	PINCTRL_PIN_GROUP("pcie_p0_phy_i2c", mt7988_pcie_p0_phy_i2c),
-+	PINCTRL_PIN_GROUP("pcie_p1_phy_i2c", mt7988_pcie_p1_phy_i2c),
-+	PINCTRL_PIN_GROUP("pcie_p2_phy_i2c", mt7988_pcie_p2_phy_i2c),
-+	PINCTRL_PIN_GROUP("pcie_p3_phy_i2c", mt7988_pcie_p3_phy_i2c),
-+	PINCTRL_PIN_GROUP("ckm_phy_i2c", mt7988_ckm_phy_i2c),
-+	PINCTRL_PIN_GROUP("pcie_pmic", mt7988_pmic),
-+	PINCTRL_PIN_GROUP("watchdog", mt7988_watchdog),
-+	PINCTRL_PIN_GROUP("pcie_wake_n0_1", mt7988_pcie_wake_n0_1),
-+	PINCTRL_PIN_GROUP("pcie_wake_n3_1", mt7988_pcie_wake_n3_1),
-+	PINCTRL_PIN_GROUP("i2c0_1", mt7988_i2c0_1),
-+	PINCTRL_PIN_GROUP("u30_phy_i2c0", mt7988_u30_phy_i2c0),
-+	PINCTRL_PIN_GROUP("u32_phy_i2c0", mt7988_u32_phy_i2c0),
-+	PINCTRL_PIN_GROUP("xfi_phy0_i2c1", mt7988_xfi_phy0_i2c1),
-+	PINCTRL_PIN_GROUP("xfi_phy1_i2c1", mt7988_xfi_phy1_i2c1),
-+	PINCTRL_PIN_GROUP("xfi_phy_pll_i2c2", mt7988_xfi_phy_pll_i2c2),
-+	PINCTRL_PIN_GROUP("i2c1_0", mt7988_i2c1_0),
-+	PINCTRL_PIN_GROUP("u30_phy_i2c1", mt7988_u30_phy_i2c1),
-+	PINCTRL_PIN_GROUP("u32_phy_i2c1", mt7988_u32_phy_i2c1),
-+	PINCTRL_PIN_GROUP("xfi_phy_pll_i2c3", mt7988_xfi_phy_pll_i2c3),
-+	PINCTRL_PIN_GROUP("sgmii0_i2c", mt7988_sgmii0_i2c),
-+	PINCTRL_PIN_GROUP("sgmii1_i2c", mt7988_sgmii1_i2c),
-+	PINCTRL_PIN_GROUP("pcie_2l_0_pereset", mt7988_pcie_2l_0_pereset),
-+	PINCTRL_PIN_GROUP("pcie_1l_1_pereset", mt7988_pcie_1l_1_pereset),
-+	PINCTRL_PIN_GROUP("pwm1", mt7988_pwm1),
-+	PINCTRL_PIN_GROUP("spi0_wp_hold", mt7988_spi0_wp_hold),
-+	PINCTRL_PIN_GROUP("spi0", mt7988_spi0),
-+	PINCTRL_PIN_GROUP("spi1", mt7988_spi1),
-+	PINCTRL_PIN_GROUP("spi2", mt7988_spi2),
-+	PINCTRL_PIN_GROUP("spi2_wp_hold", mt7988_spi2_wp_hold),
-+	PINCTRL_PIN_GROUP("snfi", mt7988_snfi),
-+	PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart0_0),
-+	PINCTRL_PIN_GROUP("uart2_0", mt7988_uart2_0),
-+	PINCTRL_PIN_GROUP("uart1_0", mt7988_uart1_0),
-+	PINCTRL_PIN_GROUP("uart2_1", mt7988_uart2_1),
-+	PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0),
-+	PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0),
-+	PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0),
-+	PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart1_0),
-+	PINCTRL_PIN_GROUP("tops_uart0_1", mt7988_tops_uart0_1),
-+	PINCTRL_PIN_GROUP("tops_uart1_1", mt7988_tops_uart1_1),
-+	PINCTRL_PIN_GROUP("udi", mt7988_udi),
-+	PINCTRL_PIN_GROUP("emmc_45", mt7988_emmc_45),
-+	PINCTRL_PIN_GROUP("emmc_51", mt7988_emmc_51),
-+	PINCTRL_PIN_GROUP("2p5g_ext_mdio", mt7988_2p5g_ext_mdio),
-+	PINCTRL_PIN_GROUP("gbe_ext_mdio", mt7988_gbe_ext_mdio),
-+	PINCTRL_PIN_GROUP("pcm", mt7988_pcm),
-+	PINCTRL_PIN_GROUP("uart0", mt7988_uart0),
-+	PINCTRL_PIN_GROUP("tops_uart0_2", mt7988_tops_uart0_2),
-+	PINCTRL_PIN_GROUP("uart2_2", mt7988_uart2_2),
-+	PINCTRL_PIN_GROUP("wo0_jtag", mt7988_wo0_jtag),
-+	PINCTRL_PIN_GROUP("wo1_jtag", mt7988_wo1_jtag),
-+	PINCTRL_PIN_GROUP("wo2_jtag", mt7988_wo2_jtag),
-+	PINCTRL_PIN_GROUP("pwm0", mt7988_pwm0),
-+	PINCTRL_PIN_GROUP("jtag", mt7988_jtag),
-+	PINCTRL_PIN_GROUP("tops_jtag0_1", mt7988_tops_jtag0_1),
-+	PINCTRL_PIN_GROUP("uart2_3", mt7988_uart2_3),
-+	PINCTRL_PIN_GROUP("uart1_1", mt7988_uart1_1),
-+	PINCTRL_PIN_GROUP("gbe_led1", mt7988_gbe_led1),
-+	PINCTRL_PIN_GROUP("2p5gbe_led1", mt7988_2p5gbe_led1),
-+	PINCTRL_PIN_GROUP("gbe_led0", mt7988_gbe_led0),
-+	PINCTRL_PIN_GROUP("2p5gbe_led0", mt7988_2p5gbe_led0),
-+	PINCTRL_PIN_GROUP("drv_vbus_p1", mt7988_drv_vbus_p1),
-+	PINCTRL_PIN_GROUP("pcie_clk_req_n2_1", mt7988_pcie_clk_req_n2_1),
-+	PINCTRL_PIN_GROUP("mdc_mdio1", mt7988_mdc_mdio1),
-+	PINCTRL_PIN_GROUP("i2c1_2", mt7988_i2c1_2),
-+	PINCTRL_PIN_GROUP("pwm6", mt7988_pwm6),
-+	PINCTRL_PIN_GROUP("pwm7", mt7988_pwm7),
-+	PINCTRL_PIN_GROUP("i2c2_0", mt7988_i2c2_0),
-+	PINCTRL_PIN_GROUP("i2c2_1", mt7988_i2c2_1),
-+	PINCTRL_PIN_GROUP("pcie_2l_1_pereset", mt7988_pcie_2l_1_pereset),
-+	PINCTRL_PIN_GROUP("pcie_1l_0_pereset", mt7988_pcie_1l_0_pereset),
-+	PINCTRL_PIN_GROUP("pcie_wake_n1_0", mt7988_pcie_wake_n1_0),
-+	PINCTRL_PIN_GROUP("pcie_clk_req_n1", mt7988_pcie_clk_req_n1),
-+	PINCTRL_PIN_GROUP("pcie_wake_n2_0", mt7988_pcie_wake_n2_0),
-+	PINCTRL_PIN_GROUP("pcie_clk_req_n2_0", mt7988_pcie_clk_req_n2_0),
-+	PINCTRL_PIN_GROUP("drv_vbus", mt7988_drv_vbus),
-+	PINCTRL_PIN_GROUP("pcie_wake_n2_1", mt7988_pcie_wake_n2_1),
-+	PINCTRL_PIN_GROUP("uart1_2", mt7988_uart1_2),
-+	PINCTRL_PIN_GROUP("pwm2", mt7988_pwm2),
-+	PINCTRL_PIN_GROUP("pwm3", mt7988_pwm3),
-+	PINCTRL_PIN_GROUP("pwm4", mt7988_pwm4),
-+	PINCTRL_PIN_GROUP("pwm5", mt7988_pwm5),
-+	PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0),
-+	PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0),
-+	PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0),
-+	PINCTRL_PIN_GROUP("tops_uart1_2", mt7988_tops_uart1_2),
-+	PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7988_net_wo0_uart_txd_1),
-+	PINCTRL_PIN_GROUP("net_wo1_uart_txd_1", mt7988_net_wo1_uart_txd_1),
-+	PINCTRL_PIN_GROUP("net_wo2_uart_txd_1", mt7988_net_wo2_uart_txd_1),
-+};
-+
-+static const struct mtk_io_type_desc mt7988_io_type_desc[] = {
-+	[IO_TYPE_GRP0] = {
-+		.name = "18OD33",
-+		.bias_set = mtk_pinconf_bias_set_pupd_r1_r0,
-+		.drive_set = mtk_pinconf_drive_set_v1,
-+		.input_enable = mtk_pinconf_input_enable_v1,
-+	},
-+	[IO_TYPE_GRP1] = {
-+		.name = "18A01",
-+		.bias_set = mtk_pinconf_bias_set_pu_pd,
-+		.drive_set = mtk_pinconf_drive_set_v1,
-+		.input_enable = mtk_pinconf_input_enable_v1,
-+	},
-+	[IO_TYPE_GRP2] = {
-+		.name = "I2C",
-+		.input_enable = mtk_pinconf_input_enable_v1,
-+	},
-+};
-+
-+/* Joint those groups owning the same capability in user point of view which
-+ * allows that people tend to use through the device tree.
-+ */
-+static const char *const mt7988_jtag_groups[] = { "tops_jtag0_0", "wo0_jtag",
-+	"wo1_jtag", "wo2_jtag", "jtag", "tops_jtag0_1", };
-+static const char *const mt7988_int_usxgmii_groups[] = { "int_usxgmii", };
-+static const char *const mt7988_pwm_groups[] = { "pwm0", "pwm1", "pwm2", "pwm3",
-+	"pwm4", "pwm5", "pwm6", "pwm7" };
-+static const char *const mt7988_dfd_groups[] = { "dfd", };
-+static const char *const mt7988_i2c_groups[] = { "xfi_phy0_i2c0",
-+	"xfi_phy1_i2c0", "xfi_phy_pll_i2c0", "xfi_phy_pll_i2c1", "i2c0_0",
-+	"i2c1_sfp", "xfi_pextp_phy0_i2c", "xfi_pextp_phy1_i2c", "i2c0_1",
-+	"u30_phy_i2c0", "u32_phy_i2c0", "xfi_phy0_i2c1", "xfi_phy1_i2c1",
-+	"xfi_phy_pll_i2c2", "i2c1_0", "u30_phy_i2c1", "u32_phy_i2c1",
-+	"xfi_phy_pll_i2c3", "sgmii0_i2c", "sgmii1_i2c", "i2c1_2", "i2c2_0",
-+	"i2c2_1", };
-+static const char *const mt7988_ethernet_groups[] = { "mdc_mdio0",
-+	"2p5g_ext_mdio", "gbe_ext_mdio", "mdc_mdio1", };
-+static const char *const mt7988_pcie_groups[] = { "pcie_wake_n0_0",
-+	"pcie_clk_req_n0_0", "pcie_wake_n3_0", "pcie_clk_req_n3",
-+	"pcie_p0_phy_i2c", "pcie_p1_phy_i2c", "pcie_p3_phy_i2",
-+	"pcie_p2_phy_i2c", "ckm_phy_i2c", "pcie_wake_n0_1", "pcie_wake_n3_1",
-+	"pcie_2l_0_pereset", "pcie_1l_1_pereset", "pcie_clk_req_n2_1",
-+	"pcie_2l_1_perese", "pcie_1l_0_pereset", "pcie_wake_n1_0",
-+	"cie_clk_req_n1", "pcie_wake_n2_0", "pcie_wake_n2_1", };
-+static const char *const mt7988_pmic_groups[] = { "pmic", };
-+static const char *const mt7988_wdt_groups[] = { "watchdog", };
-+static const char *const mt7988_spi_groups[] = { "spi0", "spi0_wp_hold",
-+	"spi1", "spi2", "spi2_wp_hold", };
-+static const char *const mt7988_flash_groups[] = { "emmc_45", "snfi",
-+	"emmc_51" };
-+static const char *const mt7988_uart_groups[] = { "uart2", "tops_uart0_0",
-+	"uart2_0", "uart1_0", "uart2_1",
-+	"net_wo0_uart_txd_0", "net_wo1_uart_txd_0", "net_wo2_uart_txd_0",
-+	"tops_uart1_0", "ops_uart0_1", "ops_uart1_1",
-+	"uart0", "tops_uart0_2", "uart1_1",
-+	"uart2_3", "uart1_2", "tops_uart1_2",
-+	"net_wo0_uart_txd_1", "net_wo1_uart_txd_1", "net_wo2_uart_txd_1", };
-+static const char *const mt7988_udi_groups[] = { "udi", };
-+static const char *const mt7988_pcm_groups[] = { "pcm", };
-+static const char *const mt7988_led_groups[] = { "gbe_led1", "2p5gbe_led1",
-+	"gbe_led0", "2p5gbe_led0", "wf5g_led0", "wf5g_led1", };
-+static const char *const mt7988_usb_groups[] = { "drv_vbus", "drv_vbus_p1", };
-+
-+static const struct mtk_function_desc mt7988_functions[] = {
-+	{"jtag", mt7988_jtag_groups, ARRAY_SIZE(mt7988_jtag_groups)},
-+	{"int_usxgmii", mt7988_int_usxgmii_groups,
-+			ARRAY_SIZE(mt7988_int_usxgmii_groups)},
-+	{"pwm", mt7988_pwm_groups, ARRAY_SIZE(mt7988_pwm_groups)},
-+	{"dfd", mt7988_dfd_groups, ARRAY_SIZE(mt7988_dfd_groups)},
-+	{"i2c", mt7988_i2c_groups, ARRAY_SIZE(mt7988_i2c_groups)},
-+	{"eth", mt7988_ethernet_groups, ARRAY_SIZE(mt7988_ethernet_groups)},
-+	{"pcie", mt7988_pcie_groups, ARRAY_SIZE(mt7988_pcie_groups)},
-+	{"pmic", mt7988_pmic_groups, ARRAY_SIZE(mt7988_pmic_groups)},
-+	{"watchdog", mt7988_wdt_groups, ARRAY_SIZE(mt7988_wdt_groups)},
-+	{"spi", mt7988_spi_groups, ARRAY_SIZE(mt7988_spi_groups)},
-+	{"flash", mt7988_flash_groups, ARRAY_SIZE(mt7988_flash_groups)},
-+	{"uart", mt7988_uart_groups, ARRAY_SIZE(mt7988_uart_groups)},
-+	{"udi", mt7988_udi_groups, ARRAY_SIZE(mt7988_udi_groups)},
-+	{"pcm", mt7988_pcm_groups, ARRAY_SIZE(mt7988_pcm_groups)},
-+	{"usb", mt7988_usb_groups, ARRAY_SIZE(mt7988_usb_groups)},
-+	{"led", mt7988_led_groups, ARRAY_SIZE(mt7988_led_groups)},
-+};
-+
-+static const char *const mt7988_pinctrl_register_base_names[] = {
-+	"gpio_base", "iocfg_tr_base", "iocfg_br_base", "iocfg_rb_base",
-+	"iocfg_lb_base", "iocfg_tl_base",
-+};
-+
-+static const struct mtk_pinctrl_soc mt7988_data = {
-+	.name = "mt7988_pinctrl",
-+	.reg_cal = mt7988_reg_cals,
-+	.pins = mt7988_pins,
-+	.npins = ARRAY_SIZE(mt7988_pins),
-+	.grps = mt7988_groups,
-+	.ngrps = ARRAY_SIZE(mt7988_groups),
-+	.funcs = mt7988_functions,
-+	.nfuncs = ARRAY_SIZE(mt7988_functions),
-+	.io_type = mt7988_io_type_desc,
-+	.ntype = ARRAY_SIZE(mt7988_io_type_desc),
-+	.gpio_mode = 0,
-+	.base_names = mt7988_pinctrl_register_base_names,
-+	.nbase_names = ARRAY_SIZE(mt7988_pinctrl_register_base_names),
-+	.base_calc = 1,
-+};
-+
-+static int mtk_pinctrl_mt7988_probe(struct udevice *dev)
-+{
-+	return mtk_pinctrl_common_probe(dev, &mt7988_data);
-+}
-+
-+static const struct udevice_id mt7988_pctrl_match[] = {
-+	{.compatible = "mediatek,mt7988-pinctrl"},
-+	{ /* sentinel */ }
-+};
-+
-+U_BOOT_DRIVER(mt7988_pinctrl) = {
-+	.name = "mt7988_pinctrl",
-+	.id = UCLASS_PINCTRL,
-+	.of_match = mt7988_pctrl_match,
-+	.ops = &mtk_pinctrl_ops,
-+	.probe = mtk_pinctrl_mt7988_probe,
-+	.priv_auto = sizeof(struct mtk_pinctrl_priv),
-+};
diff --git a/package/boot/uboot-mediatek/patches/101-16-net-mediatek-connect-switch-to-PSE-only-when-startin.patch b/package/boot/uboot-mediatek/patches/101-16-net-mediatek-connect-switch-to-PSE-only-when-startin.patch
deleted file mode 100644
index e3e6212742b6f5..00000000000000
--- a/package/boot/uboot-mediatek/patches/101-16-net-mediatek-connect-switch-to-PSE-only-when-startin.patch
+++ /dev/null
@@ -1,138 +0,0 @@
-From a0405999ebecf21ed9f76f1dc9420682cd3feba0 Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:16:54 +0800
-Subject: [PATCH 16/29] net: mediatek: connect switch to PSE only when starting
- eth is requested
-
-So far the switch is initialized in probe stage and is connected to PSE
-unconditionally. This will cause all packets being flooded to PSE and may
-cause PSE hang before entering linux.
-
-This patch changes the connection between switch and PSE:
-- Still initialize switch in probe stage, but disconnect it with PSE
-- Connect switch with PSE on eth start
-- Disconnect on eth stop
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- drivers/net/mtk_eth.c | 44 ++++++++++++++++++++++++++++++++++++++++---
- 1 file changed, 41 insertions(+), 3 deletions(-)
-
---- a/drivers/net/mtk_eth.c
-+++ b/drivers/net/mtk_eth.c
-@@ -123,8 +123,10 @@ struct mtk_eth_priv {
- 
- 	enum mtk_switch sw;
- 	int (*switch_init)(struct mtk_eth_priv *priv);
-+	void (*switch_mac_control)(struct mtk_eth_priv *priv, bool enable);
- 	u32 mt753x_smi_addr;
- 	u32 mt753x_phy_base;
-+	u32 mt753x_pmcr;
- 
- 	struct gpio_desc rst_gpio;
- 	int mcm;
-@@ -613,6 +615,16 @@ static int mt7530_pad_clk_setup(struct m
- 	return 0;
- }
- 
-+static void mt7530_mac_control(struct mtk_eth_priv *priv, bool enable)
-+{
-+	u32 pmcr = FORCE_MODE;
-+
-+	if (enable)
-+		pmcr = priv->mt753x_pmcr;
-+
-+	mt753x_reg_write(priv, PMCR_REG(6), pmcr);
-+}
-+
- static int mt7530_setup(struct mtk_eth_priv *priv)
- {
- 	u16 phy_addr, phy_val;
-@@ -663,11 +675,14 @@ static int mt7530_setup(struct mtk_eth_p
- 	      FORCE_DPX | FORCE_LINK;
- 
- 	/* MT7530 Port6: Forced 1000M/FD, FC disabled */
--	mt753x_reg_write(priv, PMCR_REG(6), val);
-+	priv->mt753x_pmcr = val;
- 
- 	/* MT7530 Port5: Forced link down */
- 	mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE);
- 
-+	/* Keep MAC link down before starting eth */
-+	mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE);
-+
- 	/* MT7530 Port6: Set to RGMII */
- 	mt753x_reg_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_M, P6_INTF_MODE_RGMII);
- 
-@@ -823,6 +838,17 @@ static void mt7531_phy_setting(struct mt
- 	}
- }
- 
-+static void mt7531_mac_control(struct mtk_eth_priv *priv, bool enable)
-+{
-+	u32 pmcr = FORCE_MODE_LNK;
-+
-+	if (enable)
-+		pmcr = priv->mt753x_pmcr;
-+
-+	mt753x_reg_write(priv, PMCR_REG(5), pmcr);
-+	mt753x_reg_write(priv, PMCR_REG(6), pmcr);
-+}
-+
- static int mt7531_setup(struct mtk_eth_priv *priv)
- {
- 	u16 phy_addr, phy_val;
-@@ -882,8 +908,11 @@ static int mt7531_setup(struct mtk_eth_p
- 	       (SPEED_1000M << FORCE_SPD_S) | FORCE_DPX |
- 	       FORCE_LINK;
- 
--	mt753x_reg_write(priv, PMCR_REG(5), pmcr);
--	mt753x_reg_write(priv, PMCR_REG(6), pmcr);
-+	priv->mt753x_pmcr = pmcr;
-+
-+	/* Keep MAC link down before starting eth */
-+	mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE_LNK);
-+	mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK);
- 
- 	/* Turn on PHYs */
- 	for (i = 0; i < MT753X_NUM_PHYS; i++) {
-@@ -1227,6 +1256,9 @@ static int mtk_eth_start(struct udevice
- 
- 	mtk_eth_fifo_init(priv);
- 
-+	if (priv->switch_mac_control)
-+		priv->switch_mac_control(priv, true);
-+
- 	/* Start PHY */
- 	if (priv->sw == SW_NONE) {
- 		ret = mtk_phy_start(priv);
-@@ -1245,6 +1277,9 @@ static void mtk_eth_stop(struct udevice
- {
- 	struct mtk_eth_priv *priv = dev_get_priv(dev);
- 
-+	if (priv->switch_mac_control)
-+		priv->switch_mac_control(priv, false);
-+
- 	mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG,
- 		     TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN, 0);
- 	udelay(500);
-@@ -1484,16 +1519,19 @@ static int mtk_eth_of_to_plat(struct ude
- 	/* check for switch first, otherwise phy will be used */
- 	priv->sw = SW_NONE;
- 	priv->switch_init = NULL;
-+	priv->switch_mac_control = NULL;
- 	str = dev_read_string(dev, "mediatek,switch");
- 
- 	if (str) {
- 		if (!strcmp(str, "mt7530")) {
- 			priv->sw = SW_MT7530;
- 			priv->switch_init = mt7530_setup;
-+			priv->switch_mac_control = mt7530_mac_control;
- 			priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR;
- 		} else if (!strcmp(str, "mt7531")) {
- 			priv->sw = SW_MT7531;
- 			priv->switch_init = mt7531_setup;
-+			priv->switch_mac_control = mt7531_mac_control;
- 			priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR;
- 		} else {
- 			printf("error: unsupported switch\n");
diff --git a/package/boot/uboot-mediatek/patches/101-17-net-mediatek-optimize-the-switch-reset-delay-wait-ti.patch b/package/boot/uboot-mediatek/patches/101-17-net-mediatek-optimize-the-switch-reset-delay-wait-ti.patch
deleted file mode 100644
index c8823ac545ce4a..00000000000000
--- a/package/boot/uboot-mediatek/patches/101-17-net-mediatek-optimize-the-switch-reset-delay-wait-ti.patch
+++ /dev/null
@@ -1,56 +0,0 @@
-From d9a52701f6677889cc3332ab7a888f35cd69cc76 Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:16:59 +0800
-Subject: [PATCH 17/29] net: mediatek: optimize the switch reset delay wait
- time
-
-Not all switches requires 1 second delay after deasserting reset.
-MT7531 requires only maximum 200ms.
-
-This patch defines dedicated reset wait time for each switch chip, and will
-significantly improve the boot time for boards using MT7531.
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- drivers/net/mtk_eth.c | 7 +++++--
- 1 file changed, 5 insertions(+), 2 deletions(-)
-
---- a/drivers/net/mtk_eth.c
-+++ b/drivers/net/mtk_eth.c
-@@ -127,6 +127,7 @@ struct mtk_eth_priv {
- 	u32 mt753x_smi_addr;
- 	u32 mt753x_phy_base;
- 	u32 mt753x_pmcr;
-+	u32 mt753x_reset_wait_time;
- 
- 	struct gpio_desc rst_gpio;
- 	int mcm;
-@@ -943,12 +944,12 @@ int mt753x_switch_init(struct mtk_eth_pr
- 		reset_assert(&priv->rst_mcm);
- 		udelay(1000);
- 		reset_deassert(&priv->rst_mcm);
--		mdelay(1000);
-+		mdelay(priv->mt753x_reset_wait_time);
- 	} else if (dm_gpio_is_valid(&priv->rst_gpio)) {
- 		dm_gpio_set_value(&priv->rst_gpio, 0);
- 		udelay(1000);
- 		dm_gpio_set_value(&priv->rst_gpio, 1);
--		mdelay(1000);
-+		mdelay(priv->mt753x_reset_wait_time);
- 	}
- 
- 	ret = priv->switch_init(priv);
-@@ -1528,11 +1529,13 @@ static int mtk_eth_of_to_plat(struct ude
- 			priv->switch_init = mt7530_setup;
- 			priv->switch_mac_control = mt7530_mac_control;
- 			priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR;
-+			priv->mt753x_reset_wait_time = 1000;
- 		} else if (!strcmp(str, "mt7531")) {
- 			priv->sw = SW_MT7531;
- 			priv->switch_init = mt7531_setup;
- 			priv->switch_mac_control = mt7531_mac_control;
- 			priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR;
-+			priv->mt753x_reset_wait_time = 200;
- 		} else {
- 			printf("error: unsupported switch\n");
- 			return -EINVAL;
diff --git a/package/boot/uboot-mediatek/patches/101-18-net-mediatek-fix-direct-MDIO-clause-45-access-via-So.patch b/package/boot/uboot-mediatek/patches/101-18-net-mediatek-fix-direct-MDIO-clause-45-access-via-So.patch
deleted file mode 100644
index 5214e842c82656..00000000000000
--- a/package/boot/uboot-mediatek/patches/101-18-net-mediatek-fix-direct-MDIO-clause-45-access-via-So.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From c44f6ac1a31961b0d4faf982ee42167de5ac1672 Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:17:03 +0800
-Subject: [PATCH 18/29] net: mediatek: fix direct MDIO clause 45 access via SoC
-
-The original direct MDIO clause 45 access via SoC is missing the
-data output. This patch adds it back to ensure MDIO clause 45 can
-work properly for external PHYs.
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- drivers/net/mtk_eth.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/drivers/net/mtk_eth.c
-+++ b/drivers/net/mtk_eth.c
-@@ -198,7 +198,7 @@ static int mtk_mii_rw(struct mtk_eth_pri
- 	      (((u32)phy << MDIO_PHY_ADDR_S) & MDIO_PHY_ADDR_M) |
- 	      (((u32)reg << MDIO_REG_ADDR_S) & MDIO_REG_ADDR_M);
- 
--	if (cmd == MDIO_CMD_WRITE)
-+	if (cmd == MDIO_CMD_WRITE || cmd == MDIO_CMD_ADDR)
- 		val |= data & MDIO_RW_DATA_M;
- 
- 	mtk_gmac_write(priv, GMAC_PIAC_REG, val | PHY_ACS_ST);
-@@ -210,7 +210,7 @@ static int mtk_mii_rw(struct mtk_eth_pri
- 		return ret;
- 	}
- 
--	if (cmd == MDIO_CMD_READ) {
-+	if (cmd == MDIO_CMD_READ || cmd == MDIO_CMD_READ_C45) {
- 		val = mtk_gmac_read(priv, GMAC_PIAC_REG);
- 		return val & MDIO_RW_DATA_M;
- 	}
diff --git a/package/boot/uboot-mediatek/patches/101-19-net-mediatek-add-missing-static-qualifier.patch b/package/boot/uboot-mediatek/patches/101-19-net-mediatek-add-missing-static-qualifier.patch
deleted file mode 100644
index 9350ca04dc26c8..00000000000000
--- a/package/boot/uboot-mediatek/patches/101-19-net-mediatek-add-missing-static-qualifier.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From 9d35558bedfb82860c63cc11d3426afcbd82cb5c Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:17:07 +0800
-Subject: [PATCH 19/29] net: mediatek: add missing static qualifier
-
-mt7531_mmd_ind_read and mt753x_switch_init are defined without static.
-Since they're not used outside this file, we should add them back.
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
-
-fixup to add static qualifier
----
- drivers/net/mtk_eth.c | 5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
---- a/drivers/net/mtk_eth.c
-+++ b/drivers/net/mtk_eth.c
-@@ -436,7 +436,8 @@ static int mt7531_mii_ind_write(struct m
- 			     MDIO_ST_C22);
- }
- 
--int mt7531_mmd_ind_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg)
-+static int mt7531_mmd_ind_read(struct mtk_eth_priv *priv, u8 addr, u8 devad,
-+			       u16 reg)
- {
- 	u8 phy_addr;
- 	int ret;
-@@ -934,7 +935,7 @@ static int mt7531_setup(struct mtk_eth_p
- 	return 0;
- }
- 
--int mt753x_switch_init(struct mtk_eth_priv *priv)
-+static int mt753x_switch_init(struct mtk_eth_priv *priv)
- {
- 	int ret;
- 	int i;
diff --git a/package/boot/uboot-mediatek/patches/101-20-net-mediatek-add-support-for-SGMII-1Gbps-auto-negoti.patch b/package/boot/uboot-mediatek/patches/101-20-net-mediatek-add-support-for-SGMII-1Gbps-auto-negoti.patch
deleted file mode 100644
index 45acbc36ac1bac..00000000000000
--- a/package/boot/uboot-mediatek/patches/101-20-net-mediatek-add-support-for-SGMII-1Gbps-auto-negoti.patch
+++ /dev/null
@@ -1,149 +0,0 @@
-From 8e59c3cc700a6efb8db574f3c8e18b6181b4a07d Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:17:13 +0800
-Subject: [PATCH 20/29] net: mediatek: add support for SGMII 1Gbps
- auto-negotiation mode
-
-Existing SGMII support of mtk-eth is actually a MediaTek-specific
-2.5Gbps high-speed SGMII (HSGMII) which does not support
-auto-negotiation mode.
-
-This patch adds SGMII 1Gbps auto-negotiation mode and rename the
-existing HSGMII to 2500basex.
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- drivers/net/mtk_eth.c | 46 +++++++++++++++++++++++++++++++++++++------
- drivers/net/mtk_eth.h |  2 ++
- 2 files changed, 42 insertions(+), 6 deletions(-)
-
---- a/drivers/net/mtk_eth.c
-+++ b/drivers/net/mtk_eth.c
-@@ -893,7 +893,7 @@ static int mt7531_setup(struct mtk_eth_p
- 		if (!port5_sgmii)
- 			mt7531_port_rgmii_init(priv, 5);
- 		break;
--	case PHY_INTERFACE_MODE_SGMII:
-+	case PHY_INTERFACE_MODE_2500BASEX:
- 		mt7531_port_sgmii_init(priv, 6);
- 		if (port5_sgmii)
- 			mt7531_port_sgmii_init(priv, 5);
-@@ -986,6 +986,7 @@ static void mtk_phy_link_adjust(struct m
- 	      (MAC_RX_PKT_LEN_1536 << MAC_RX_PKT_LEN_S) |
- 	      MAC_MODE | FORCE_MODE |
- 	      MAC_TX_EN | MAC_RX_EN |
-+	      DEL_RXFIFO_CLR |
- 	      BKOFF_EN | BACKPR_EN;
- 
- 	switch (priv->phydev->speed) {
-@@ -996,6 +997,7 @@ static void mtk_phy_link_adjust(struct m
- 		mcr |= (SPEED_100M << FORCE_SPD_S);
- 		break;
- 	case SPEED_1000:
-+	case SPEED_2500:
- 		mcr |= (SPEED_1000M << FORCE_SPD_S);
- 		break;
- 	};
-@@ -1048,7 +1050,8 @@ static int mtk_phy_start(struct mtk_eth_
- 		return 0;
- 	}
- 
--	mtk_phy_link_adjust(priv);
-+	if (!priv->force_mode)
-+		mtk_phy_link_adjust(priv);
- 
- 	debug("Speed: %d, %s duplex%s\n", phydev->speed,
- 	      (phydev->duplex) ? "full" : "half",
-@@ -1076,7 +1079,31 @@ static int mtk_phy_probe(struct udevice
- 	return 0;
- }
- 
--static void mtk_sgmii_init(struct mtk_eth_priv *priv)
-+static void mtk_sgmii_an_init(struct mtk_eth_priv *priv)
-+{
-+	/* Set SGMII GEN1 speed(1G) */
-+	clrsetbits_le32(priv->sgmii_base + priv->soc->ana_rgc3,
-+			SGMSYS_SPEED_2500, 0);
-+
-+	/* Enable SGMII AN */
-+	setbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1,
-+		     SGMII_AN_ENABLE);
-+
-+	/* SGMII AN mode setting */
-+	writel(SGMII_AN_MODE, priv->sgmii_base + SGMSYS_SGMII_MODE);
-+
-+	/* SGMII PN SWAP setting */
-+	if (priv->pn_swap) {
-+		setbits_le32(priv->sgmii_base + SGMSYS_QPHY_WRAP_CTRL,
-+			     SGMII_PN_SWAP_TX_RX);
-+	}
-+
-+	/* Release PHYA power down state */
-+	clrsetbits_le32(priv->sgmii_base + SGMSYS_QPHY_PWR_STATE_CTRL,
-+			SGMII_PHYA_PWD, 0);
-+}
-+
-+static void mtk_sgmii_force_init(struct mtk_eth_priv *priv)
- {
- 	/* Set SGMII GEN2 speed(2.5G) */
- 	setbits_le32(priv->sgmii_base + priv->soc->ana_rgc3,
-@@ -1111,10 +1138,14 @@ static void mtk_mac_init(struct mtk_eth_
- 		ge_mode = GE_MODE_RGMII;
- 		break;
- 	case PHY_INTERFACE_MODE_SGMII:
-+	case PHY_INTERFACE_MODE_2500BASEX:
- 		ge_mode = GE_MODE_RGMII;
- 		mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG, SYSCFG0_SGMII_SEL_M,
- 			       SYSCFG0_SGMII_SEL(priv->gmac_id));
--		mtk_sgmii_init(priv);
-+		if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII)
-+			mtk_sgmii_an_init(priv);
-+		else
-+			mtk_sgmii_force_init(priv);
- 		break;
- 	case PHY_INTERFACE_MODE_MII:
- 	case PHY_INTERFACE_MODE_GMII:
-@@ -1148,6 +1179,7 @@ static void mtk_mac_init(struct mtk_eth_
- 			mcr |= SPEED_100M << FORCE_SPD_S;
- 			break;
- 		case SPEED_1000:
-+		case SPEED_2500:
- 			mcr |= SPEED_1000M << FORCE_SPD_S;
- 			break;
- 		}
-@@ -1490,13 +1522,15 @@ static int mtk_eth_of_to_plat(struct ude
- 		priv->duplex = ofnode_read_bool(subnode, "full-duplex");
- 
- 		if (priv->speed != SPEED_10 && priv->speed != SPEED_100 &&
--		    priv->speed != SPEED_1000) {
-+		    priv->speed != SPEED_1000 && priv->speed != SPEED_2500 &&
-+		    priv->speed != SPEED_10000) {
- 			printf("error: no valid speed set in fixed-link\n");
- 			return -EINVAL;
- 		}
- 	}
- 
--	if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII) {
-+	if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII ||
-+	    priv->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
- 		/* get corresponding sgmii phandle */
- 		ret = dev_read_phandle_with_args(dev, "mediatek,sgmiisys",
- 						 NULL, 0, 0, &args);
---- a/drivers/net/mtk_eth.h
-+++ b/drivers/net/mtk_eth.h
-@@ -69,6 +69,7 @@ enum mkt_eth_capabilities {
- #define SGMII_AN_RESTART		BIT(9)
- 
- #define SGMSYS_SGMII_MODE		0x20
-+#define SGMII_AN_MODE			0x31120103
- #define SGMII_FORCE_MODE		0x31120019
- 
- #define SGMSYS_QPHY_PWR_STATE_CTRL	0xe8
-@@ -168,6 +169,7 @@ enum mkt_eth_capabilities {
- #define FORCE_MODE			BIT(15)
- #define MAC_TX_EN			BIT(14)
- #define MAC_RX_EN			BIT(13)
-+#define DEL_RXFIFO_CLR			BIT(12)
- #define BKOFF_EN			BIT(9)
- #define BACKPR_EN			BIT(8)
- #define FORCE_RX_FC			BIT(5)
diff --git a/package/boot/uboot-mediatek/patches/101-21-arm-dts-medaitek-convert-gmac-link-mode-to-2500base-.patch b/package/boot/uboot-mediatek/patches/101-21-arm-dts-medaitek-convert-gmac-link-mode-to-2500base-.patch
deleted file mode 100644
index 27612fd9e4e87c..00000000000000
--- a/package/boot/uboot-mediatek/patches/101-21-arm-dts-medaitek-convert-gmac-link-mode-to-2500base-.patch
+++ /dev/null
@@ -1,214 +0,0 @@
-From 64ef7e977767e3b1305fb94a5169d8b7d3b19b6c Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:17:18 +0800
-Subject: [PATCH 21/29] arm: dts: mediatek: convert gmac link mode to
- 2500base-x
-
-Now that individual 2.5Gbps SGMII support has been added to
-mtk-eth, all boards that use 2.5Gbps link with mt7531 must be
-converted to use "2500base-x" instead of "sgmii".
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
-[also convert BPi-R3]
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- arch/arm/dts/mt7622-bananapi-bpi-r64.dts | 4 ++--
- arch/arm/dts/mt7622-rfb.dts              | 4 ++--
- arch/arm/dts/mt7629-rfb.dts              | 4 ++--
- arch/arm/dts/mt7981-emmc-rfb.dts         | 4 ++--
- arch/arm/dts/mt7981-rfb.dts              | 4 ++--
- arch/arm/dts/mt7981-sd-rfb.dts           | 4 ++--
- arch/arm/dts/mt7986a-bpi-r3-sd.dts       | 4 ++--
- arch/arm/dts/mt7986a-rfb.dts             | 4 ++--
- arch/arm/dts/mt7986a-sd-rfb.dts          | 4 ++--
- arch/arm/dts/mt7986b-rfb.dts             | 4 ++--
- arch/arm/dts/mt7986b-sd-rfb.dts          | 4 ++--
- 11 files changed, 22 insertions(+), 22 deletions(-)
-
---- a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
-@@ -224,12 +224,12 @@
- &eth {
- 	status = "okay";
- 	mediatek,gmac-id = <0>;
--	phy-mode = "sgmii";
-+	phy-mode = "2500base-x";
- 	mediatek,switch = "mt7531";
- 	reset-gpios = <&gpio 54 GPIO_ACTIVE_HIGH>;
- 
- 	fixed-link {
--		speed = <1000>;
-+		speed = <2500>;
- 		full-duplex;
- 	};
- };
---- a/arch/arm/dts/mt7622-rfb.dts
-+++ b/arch/arm/dts/mt7622-rfb.dts
-@@ -240,12 +240,12 @@
- &eth {
- 	status = "okay";
- 	mediatek,gmac-id = <0>;
--	phy-mode = "sgmii";
-+	phy-mode = "2500base-x";
- 	mediatek,switch = "mt7531";
- 	reset-gpios = <&gpio 54 GPIO_ACTIVE_HIGH>;
- 
- 	fixed-link {
--		speed = <1000>;
-+		speed = <2500>;
- 		full-duplex;
- 	};
- };
---- a/arch/arm/dts/mt7629-rfb.dts
-+++ b/arch/arm/dts/mt7629-rfb.dts
-@@ -25,12 +25,12 @@
- &eth {
- 	status = "okay";
- 	mediatek,gmac-id = <0>;
--	phy-mode = "sgmii";
-+	phy-mode = "2500base-x";
- 	mediatek,switch = "mt7531";
- 	reset-gpios = <&gpio 28 GPIO_ACTIVE_HIGH>;
- 
- 	fixed-link {
--		speed = <1000>;
-+		speed = <2500>;
- 		full-duplex;
- 	};
- };
---- a/arch/arm/dts/mt7981-emmc-rfb.dts
-+++ b/arch/arm/dts/mt7981-emmc-rfb.dts
-@@ -46,12 +46,12 @@
- &eth {
- 	status = "okay";
- 	mediatek,gmac-id = <0>;
--	phy-mode = "sgmii";
-+	phy-mode = "2500base-x";
- 	mediatek,switch = "mt7531";
- 	reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
- 
- 	fixed-link {
--		speed = <1000>;
-+		speed = <2500>;
- 		full-duplex;
- 	};
- };
---- a/arch/arm/dts/mt7981-rfb.dts
-+++ b/arch/arm/dts/mt7981-rfb.dts
-@@ -37,12 +37,12 @@
- &eth {
- 	status = "okay";
- 	mediatek,gmac-id = <0>;
--	phy-mode = "sgmii";
-+	phy-mode = "2500base-x";
- 	mediatek,switch = "mt7531";
- 	reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
- 
- 	fixed-link {
--		speed = <1000>;
-+		speed = <2500>;
- 		full-duplex;
- 	};
- };
---- a/arch/arm/dts/mt7981-sd-rfb.dts
-+++ b/arch/arm/dts/mt7981-sd-rfb.dts
-@@ -46,12 +46,12 @@
- &eth {
- 	status = "okay";
- 	mediatek,gmac-id = <0>;
--	phy-mode = "sgmii";
-+	phy-mode = "2500base-x";
- 	mediatek,switch = "mt7531";
- 	reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
- 
- 	fixed-link {
--		speed = <1000>;
-+		speed = <2500>;
- 		full-duplex;
- 	};
- };
---- a/arch/arm/dts/mt7986a-bpi-r3-sd.dts
-+++ b/arch/arm/dts/mt7986a-bpi-r3-sd.dts
-@@ -76,12 +76,12 @@
- &eth {
- 	status = "okay";
- 	mediatek,gmac-id = <0>;
--	phy-mode = "sgmii";
-+	phy-mode = "2500base-x";
- 	mediatek,switch = "mt7531";
- 	reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
- 
- 	fixed-link {
--		speed = <1000>;
-+		speed = <2500>;
- 		full-duplex;
- 	};
- };
---- a/arch/arm/dts/mt7986a-rfb.dts
-+++ b/arch/arm/dts/mt7986a-rfb.dts
-@@ -55,12 +55,12 @@
- &eth {
- 	status = "okay";
- 	mediatek,gmac-id = <0>;
--	phy-mode = "sgmii";
-+	phy-mode = "2500base-x";
- 	mediatek,switch = "mt7531";
- 	reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
- 
- 	fixed-link {
--		speed = <1000>;
-+		speed = <2500>;
- 		full-duplex;
- 	};
- };
---- a/arch/arm/dts/mt7986a-sd-rfb.dts
-+++ b/arch/arm/dts/mt7986a-sd-rfb.dts
-@@ -47,12 +47,12 @@
- &eth {
- 	status = "okay";
- 	mediatek,gmac-id = <0>;
--	phy-mode = "sgmii";
-+	phy-mode = "2500base-x";
- 	mediatek,switch = "mt7531";
- 	reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
- 
- 	fixed-link {
--		speed = <1000>;
-+		speed = <2500>;
- 		full-duplex;
- 	};
- };
---- a/arch/arm/dts/mt7986b-rfb.dts
-+++ b/arch/arm/dts/mt7986b-rfb.dts
-@@ -46,12 +46,12 @@
- &eth {
- 	status = "okay";
- 	mediatek,gmac-id = <0>;
--	phy-mode = "sgmii";
-+	phy-mode = "2500base-x";
- 	mediatek,switch = "mt7531";
- 	reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
- 
- 	fixed-link {
--		speed = <1000>;
-+		speed = <2500>;
- 		full-duplex;
- 	};
- };
---- a/arch/arm/dts/mt7986b-sd-rfb.dts
-+++ b/arch/arm/dts/mt7986b-sd-rfb.dts
-@@ -47,12 +47,12 @@
- &eth {
- 	status = "okay";
- 	mediatek,gmac-id = <0>;
--	phy-mode = "sgmii";
-+	phy-mode = "2500base-x";
- 	mediatek,switch = "mt7531";
- 	reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
- 
- 	fixed-link {
--		speed = <1000>;
-+		speed = <2500>;
- 		full-duplex;
- 	};
- };
diff --git a/package/boot/uboot-mediatek/patches/101-22-net-mediatek-add-support-for-GMAC-USB3-PHY-mux-mode-.patch b/package/boot/uboot-mediatek/patches/101-22-net-mediatek-add-support-for-GMAC-USB3-PHY-mux-mode-.patch
deleted file mode 100644
index c7e49ff304ddc2..00000000000000
--- a/package/boot/uboot-mediatek/patches/101-22-net-mediatek-add-support-for-GMAC-USB3-PHY-mux-mode-.patch
+++ /dev/null
@@ -1,138 +0,0 @@
-From 542d455466bdf32e1bb70230ebcdefd8ed09643b Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:17:22 +0800
-Subject: [PATCH 22/29] net: mediatek: add support for GMAC/USB3 PHY mux mode
- for MT7981
-
-MT7981 has its GMAC2 PHY shared with USB3. To enable GMAC2, mux
-register must be set to connect the SGMII phy to GMAC2.
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- drivers/net/mtk_eth.c | 33 ++++++++++++++++++++++++++++++++-
- drivers/net/mtk_eth.h | 16 ++++++++++++++++
- 2 files changed, 48 insertions(+), 1 deletion(-)
-
---- a/drivers/net/mtk_eth.c
-+++ b/drivers/net/mtk_eth.c
-@@ -103,6 +103,8 @@ struct mtk_eth_priv {
- 
- 	struct regmap *ethsys_regmap;
- 
-+	struct regmap *infra_regmap;
-+
- 	struct mii_dev *mdio_bus;
- 	int (*mii_read)(struct mtk_eth_priv *priv, u8 phy, u8 reg);
- 	int (*mii_write)(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 val);
-@@ -186,6 +188,17 @@ static void mtk_ethsys_rmw(struct mtk_et
- 	regmap_write(priv->ethsys_regmap, reg, val);
- }
- 
-+static void mtk_infra_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr,
-+			  u32 set)
-+{
-+	uint val;
-+
-+	regmap_read(priv->infra_regmap, reg, &val);
-+	val &= ~clr;
-+	val |= set;
-+	regmap_write(priv->infra_regmap, reg, val);
-+}
-+
- /* Direct MDIO clause 22/45 access via SoC */
- static int mtk_mii_rw(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data,
- 		      u32 cmd, u32 st)
-@@ -1139,6 +1152,11 @@ static void mtk_mac_init(struct mtk_eth_
- 		break;
- 	case PHY_INTERFACE_MODE_SGMII:
- 	case PHY_INTERFACE_MODE_2500BASEX:
-+		if (MTK_HAS_CAPS(priv->soc->caps, MTK_GMAC2_U3_QPHY)) {
-+			mtk_infra_rmw(priv, USB_PHY_SWITCH_REG, QPHY_SEL_MASK,
-+				      SGMII_QPHY_SEL);
-+		}
-+
- 		ge_mode = GE_MODE_RGMII;
- 		mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG, SYSCFG0_SGMII_SEL_M,
- 			       SYSCFG0_SGMII_SEL(priv->gmac_id));
-@@ -1497,6 +1515,19 @@ static int mtk_eth_of_to_plat(struct ude
- 	if (IS_ERR(priv->ethsys_regmap))
- 		return PTR_ERR(priv->ethsys_regmap);
- 
-+	if (MTK_HAS_CAPS(priv->soc->caps, MTK_INFRA)) {
-+		/* get corresponding infracfg phandle */
-+		ret = dev_read_phandle_with_args(dev, "mediatek,infracfg",
-+						 NULL, 0, 0, &args);
-+
-+		if (ret)
-+			return ret;
-+
-+		priv->infra_regmap = syscon_node_to_regmap(args.node);
-+		if (IS_ERR(priv->infra_regmap))
-+			return PTR_ERR(priv->infra_regmap);
-+	}
-+
- 	/* Reset controllers */
- 	ret = reset_get_by_name(dev, "fe", &priv->rst_fe);
- 	if (ret) {
-@@ -1614,7 +1645,7 @@ static const struct mtk_soc_data mt7986_
- };
- 
- static const struct mtk_soc_data mt7981_data = {
--	.caps = MT7986_CAPS,
-+	.caps = MT7981_CAPS,
- 	.ana_rgc3 = 0x128,
- 	.pdma_base = PDMA_V2_BASE,
- 	.txd_size = sizeof(struct mtk_tx_dma_v2),
---- a/drivers/net/mtk_eth.h
-+++ b/drivers/net/mtk_eth.h
-@@ -15,27 +15,38 @@
- enum mkt_eth_capabilities {
- 	MTK_TRGMII_BIT,
- 	MTK_TRGMII_MT7621_CLK_BIT,
-+	MTK_U3_COPHY_V2_BIT,
-+	MTK_INFRA_BIT,
- 	MTK_NETSYS_V2_BIT,
- 
- 	/* PATH BITS */
- 	MTK_ETH_PATH_GMAC1_TRGMII_BIT,
-+	MTK_ETH_PATH_GMAC2_SGMII_BIT,
- };
- 
- #define MTK_TRGMII			BIT(MTK_TRGMII_BIT)
- #define MTK_TRGMII_MT7621_CLK		BIT(MTK_TRGMII_MT7621_CLK_BIT)
-+#define MTK_U3_COPHY_V2			BIT(MTK_U3_COPHY_V2_BIT)
-+#define MTK_INFRA			BIT(MTK_INFRA_BIT)
- #define MTK_NETSYS_V2			BIT(MTK_NETSYS_V2_BIT)
- 
- /* Supported path present on SoCs */
- #define MTK_ETH_PATH_GMAC1_TRGMII	BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT)
- 
-+#define MTK_ETH_PATH_GMAC2_SGMII	BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT)
-+
- #define MTK_GMAC1_TRGMII	(MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
- 
-+#define MTK_GMAC2_U3_QPHY	(MTK_ETH_PATH_GMAC2_SGMII | MTK_U3_COPHY_V2 | MTK_INFRA)
-+
- #define MTK_HAS_CAPS(caps, _x)		(((caps) & (_x)) == (_x))
- 
- #define MT7621_CAPS  (MTK_GMAC1_TRGMII | MTK_TRGMII_MT7621_CLK)
- 
- #define MT7623_CAPS  (MTK_GMAC1_TRGMII)
- 
-+#define MT7981_CAPS  (MTK_GMAC2_U3_QPHY | MTK_NETSYS_V2)
-+
- #define MT7986_CAPS  (MTK_NETSYS_V2)
- 
- /* Frame Engine Register Bases */
-@@ -56,6 +67,11 @@ enum mkt_eth_capabilities {
- #define ETHSYS_CLKCFG0_REG		0x2c
- #define ETHSYS_TRGMII_CLK_SEL362_5	BIT(11)
- 
-+/* Top misc registers */
-+#define USB_PHY_SWITCH_REG		0x218
-+#define QPHY_SEL_MASK			0x3
-+#define SGMII_QPHY_SEL			0x2
-+
- /* SYSCFG0_GE_MODE: GE Modes */
- #define GE_MODE_RGMII			0
- #define GE_MODE_MII			1
diff --git a/package/boot/uboot-mediatek/patches/101-23-arm-dts-mediatek-add-infracfg-registers-to-support-G.patch b/package/boot/uboot-mediatek/patches/101-23-arm-dts-mediatek-add-infracfg-registers-to-support-G.patch
deleted file mode 100644
index 63c25304a06cdc..00000000000000
--- a/package/boot/uboot-mediatek/patches/101-23-arm-dts-mediatek-add-infracfg-registers-to-support-G.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From 64dab5fc8405005a78bdf1e0035d8b754cdf0c7e Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:17:27 +0800
-Subject: [PATCH 23/29] arm: dts: mediatek: add infracfg registers to support
- GMAC/USB3 Co-PHY
-
-This patch adds infracfg to eth node to support enabling GMAC2.
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- arch/arm/dts/mt7981.dtsi | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/arch/arm/dts/mt7981.dtsi
-+++ b/arch/arm/dts/mt7981.dtsi
-@@ -266,6 +266,7 @@
- 		reset-names = "fe";
- 		mediatek,ethsys = <&ethsys>;
- 		mediatek,sgmiisys = <&sgmiisys0>;
-+		mediatek,infracfg = <&topmisc>;
- 		#address-cells = <1>;
- 		#size-cells = <0>;
- 		status = "disabled";
-@@ -284,6 +285,12 @@
- 		#clock-cells = <1>;
- 	};
- 
-+	topmisc: topmisc@11d10000 {
-+		compatible = "mediatek,mt7981-topmisc", "syscon";
-+		reg = <0x11d10000 0x10000>;
-+		#clock-cells = <1>;
-+	};
-+
- 	spi0: spi@1100a000 {
- 		compatible = "mediatek,ipm-spi";
- 		reg = <0x1100a000 0x100>;
diff --git a/package/boot/uboot-mediatek/patches/101-24-net-mediatek-add-USXGMII-support.patch b/package/boot/uboot-mediatek/patches/101-24-net-mediatek-add-USXGMII-support.patch
deleted file mode 100644
index 67288c749e4435..00000000000000
--- a/package/boot/uboot-mediatek/patches/101-24-net-mediatek-add-USXGMII-support.patch
+++ /dev/null
@@ -1,341 +0,0 @@
-From d62b483092035bc86d1db83ea4ac29bfa7bba77d Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:17:31 +0800
-Subject: [PATCH 24/29] net: mediatek: add USXGMII support
-
-This patch adds support for USXGMII of SoC.
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- drivers/net/mtk_eth.c | 230 +++++++++++++++++++++++++++++++++++++++++-
- drivers/net/mtk_eth.h |  24 +++++
- 2 files changed, 251 insertions(+), 3 deletions(-)
-
---- a/drivers/net/mtk_eth.c
-+++ b/drivers/net/mtk_eth.c
-@@ -105,6 +105,11 @@ struct mtk_eth_priv {
- 
- 	struct regmap *infra_regmap;
- 
-+	struct regmap *usxgmii_regmap;
-+	struct regmap *xfi_pextp_regmap;
-+	struct regmap *xfi_pll_regmap;
-+	struct regmap *toprgu_regmap;
-+
- 	struct mii_dev *mdio_bus;
- 	int (*mii_read)(struct mtk_eth_priv *priv, u8 phy, u8 reg);
- 	int (*mii_write)(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 val);
-@@ -989,6 +994,42 @@ static int mt753x_switch_init(struct mtk
- 	return 0;
- }
- 
-+static void mtk_xphy_link_adjust(struct mtk_eth_priv *priv)
-+{
-+	u16 lcl_adv = 0, rmt_adv = 0;
-+	u8 flowctrl;
-+	u32 mcr;
-+
-+	mcr = mtk_gmac_read(priv, XGMAC_PORT_MCR(priv->gmac_id));
-+	mcr &= ~(XGMAC_FORCE_TX_FC | XGMAC_FORCE_RX_FC);
-+
-+	if (priv->phydev->duplex) {
-+		if (priv->phydev->pause)
-+			rmt_adv = LPA_PAUSE_CAP;
-+		if (priv->phydev->asym_pause)
-+			rmt_adv |= LPA_PAUSE_ASYM;
-+
-+		if (priv->phydev->advertising & ADVERTISED_Pause)
-+			lcl_adv |= ADVERTISE_PAUSE_CAP;
-+		if (priv->phydev->advertising & ADVERTISED_Asym_Pause)
-+			lcl_adv |= ADVERTISE_PAUSE_ASYM;
-+
-+		flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
-+
-+		if (flowctrl & FLOW_CTRL_TX)
-+			mcr |= XGMAC_FORCE_TX_FC;
-+		if (flowctrl & FLOW_CTRL_RX)
-+			mcr |= XGMAC_FORCE_RX_FC;
-+
-+		debug("rx pause %s, tx pause %s\n",
-+		      flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled",
-+		      flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled");
-+	}
-+
-+	mcr &= ~(XGMAC_TRX_DISABLE);
-+	mtk_gmac_write(priv, XGMAC_PORT_MCR(priv->gmac_id), mcr);
-+}
-+
- static void mtk_phy_link_adjust(struct mtk_eth_priv *priv)
- {
- 	u16 lcl_adv = 0, rmt_adv = 0;
-@@ -1063,8 +1104,12 @@ static int mtk_phy_start(struct mtk_eth_
- 		return 0;
- 	}
- 
--	if (!priv->force_mode)
--		mtk_phy_link_adjust(priv);
-+	if (!priv->force_mode) {
-+		if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII)
-+			mtk_xphy_link_adjust(priv);
-+		else
-+			mtk_phy_link_adjust(priv);
-+	}
- 
- 	debug("Speed: %d, %s duplex%s\n", phydev->speed,
- 	      (phydev->duplex) ? "full" : "half",
-@@ -1140,6 +1185,112 @@ static void mtk_sgmii_force_init(struct
- 			SGMII_PHYA_PWD, 0);
- }
- 
-+static void mtk_xfi_pll_enable(struct mtk_eth_priv *priv)
-+{
-+	u32 val = 0;
-+
-+	/* Add software workaround for USXGMII PLL TCL issue */
-+	regmap_write(priv->xfi_pll_regmap, XFI_PLL_ANA_GLB8,
-+		     RG_XFI_PLL_ANA_SWWA);
-+
-+	regmap_read(priv->xfi_pll_regmap, XFI_PLL_DIG_GLB8, &val);
-+	val |= RG_XFI_PLL_EN;
-+	regmap_write(priv->xfi_pll_regmap, XFI_PLL_DIG_GLB8, val);
-+}
-+
-+static void mtk_usxgmii_reset(struct mtk_eth_priv *priv)
-+{
-+	switch (priv->gmac_id) {
-+	case 1:
-+		regmap_write(priv->toprgu_regmap, 0xFC, 0x0000A004);
-+		regmap_write(priv->toprgu_regmap, 0x18, 0x88F0A004);
-+		regmap_write(priv->toprgu_regmap, 0xFC, 0x00000000);
-+		regmap_write(priv->toprgu_regmap, 0x18, 0x88F00000);
-+		regmap_write(priv->toprgu_regmap, 0x18, 0x00F00000);
-+		break;
-+	case 2:
-+		regmap_write(priv->toprgu_regmap, 0xFC, 0x00005002);
-+		regmap_write(priv->toprgu_regmap, 0x18, 0x88F05002);
-+		regmap_write(priv->toprgu_regmap, 0xFC, 0x00000000);
-+		regmap_write(priv->toprgu_regmap, 0x18, 0x88F00000);
-+		regmap_write(priv->toprgu_regmap, 0x18, 0x00F00000);
-+		break;
-+	}
-+
-+	mdelay(10);
-+}
-+
-+static void mtk_usxgmii_setup_phya_an_10000(struct mtk_eth_priv *priv)
-+{
-+	regmap_write(priv->usxgmii_regmap, 0x810, 0x000FFE6D);
-+	regmap_write(priv->usxgmii_regmap, 0x818, 0x07B1EC7B);
-+	regmap_write(priv->usxgmii_regmap, 0x80C, 0x30000000);
-+	ndelay(1020);
-+	regmap_write(priv->usxgmii_regmap, 0x80C, 0x10000000);
-+	ndelay(1020);
-+	regmap_write(priv->usxgmii_regmap, 0x80C, 0x00000000);
-+
-+	regmap_write(priv->xfi_pextp_regmap, 0x9024, 0x00C9071C);
-+	regmap_write(priv->xfi_pextp_regmap, 0x2020, 0xAA8585AA);
-+	regmap_write(priv->xfi_pextp_regmap, 0x2030, 0x0C020707);
-+	regmap_write(priv->xfi_pextp_regmap, 0x2034, 0x0E050F0F);
-+	regmap_write(priv->xfi_pextp_regmap, 0x2040, 0x00140032);
-+	regmap_write(priv->xfi_pextp_regmap, 0x50F0, 0x00C014AA);
-+	regmap_write(priv->xfi_pextp_regmap, 0x50E0, 0x3777C12B);
-+	regmap_write(priv->xfi_pextp_regmap, 0x506C, 0x005F9CFF);
-+	regmap_write(priv->xfi_pextp_regmap, 0x5070, 0x9D9DFAFA);
-+	regmap_write(priv->xfi_pextp_regmap, 0x5074, 0x27273F3F);
-+	regmap_write(priv->xfi_pextp_regmap, 0x5078, 0xA7883C68);
-+	regmap_write(priv->xfi_pextp_regmap, 0x507C, 0x11661166);
-+	regmap_write(priv->xfi_pextp_regmap, 0x5080, 0x0E000AAF);
-+	regmap_write(priv->xfi_pextp_regmap, 0x5084, 0x08080D0D);
-+	regmap_write(priv->xfi_pextp_regmap, 0x5088, 0x02030909);
-+	regmap_write(priv->xfi_pextp_regmap, 0x50E4, 0x0C0C0000);
-+	regmap_write(priv->xfi_pextp_regmap, 0x50E8, 0x04040000);
-+	regmap_write(priv->xfi_pextp_regmap, 0x50EC, 0x0F0F0C06);
-+	regmap_write(priv->xfi_pextp_regmap, 0x50A8, 0x506E8C8C);
-+	regmap_write(priv->xfi_pextp_regmap, 0x6004, 0x18190000);
-+	regmap_write(priv->xfi_pextp_regmap, 0x00F8, 0x01423342);
-+	regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F20);
-+	regmap_write(priv->xfi_pextp_regmap, 0x0030, 0x00050C00);
-+	regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x02002800);
-+	ndelay(1020);
-+	regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000020);
-+	regmap_write(priv->xfi_pextp_regmap, 0x3028, 0x00008A01);
-+	regmap_write(priv->xfi_pextp_regmap, 0x302C, 0x0000A884);
-+	regmap_write(priv->xfi_pextp_regmap, 0x3024, 0x00083002);
-+	regmap_write(priv->xfi_pextp_regmap, 0x3010, 0x00022220);
-+	regmap_write(priv->xfi_pextp_regmap, 0x5064, 0x0F020A01);
-+	regmap_write(priv->xfi_pextp_regmap, 0x50B4, 0x06100600);
-+	regmap_write(priv->xfi_pextp_regmap, 0x3048, 0x40704000);
-+	regmap_write(priv->xfi_pextp_regmap, 0x3050, 0xA8000000);
-+	regmap_write(priv->xfi_pextp_regmap, 0x3054, 0x000000AA);
-+	regmap_write(priv->xfi_pextp_regmap, 0x306C, 0x00000F00);
-+	regmap_write(priv->xfi_pextp_regmap, 0xA060, 0x00040000);
-+	regmap_write(priv->xfi_pextp_regmap, 0x90D0, 0x00000001);
-+	regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200E800);
-+	udelay(150);
-+	regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C111);
-+	ndelay(1020);
-+	regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C101);
-+	udelay(15);
-+	regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C111);
-+	ndelay(1020);
-+	regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C101);
-+	udelay(100);
-+	regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000030);
-+	regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F00);
-+	regmap_write(priv->xfi_pextp_regmap, 0x3040, 0x30000000);
-+	udelay(400);
-+}
-+
-+static void mtk_usxgmii_an_init(struct mtk_eth_priv *priv)
-+{
-+	mtk_xfi_pll_enable(priv);
-+	mtk_usxgmii_reset(priv);
-+	mtk_usxgmii_setup_phya_an_10000(priv);
-+}
-+
- static void mtk_mac_init(struct mtk_eth_priv *priv)
- {
- 	int i, ge_mode = 0;
-@@ -1222,6 +1373,36 @@ static void mtk_mac_init(struct mtk_eth_
- 	}
- }
- 
-+static void mtk_xmac_init(struct mtk_eth_priv *priv)
-+{
-+	u32 sts;
-+
-+	switch (priv->phy_interface) {
-+	case PHY_INTERFACE_MODE_USXGMII:
-+		mtk_usxgmii_an_init(priv);
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	/* Set GMAC to the correct mode */
-+	mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG,
-+		       SYSCFG0_GE_MODE_M << SYSCFG0_GE_MODE_S(priv->gmac_id),
-+		       0);
-+
-+	if (priv->gmac_id == 1) {
-+		mtk_infra_rmw(priv, TOPMISC_NETSYS_PCS_MUX,
-+			      NETSYS_PCS_MUX_MASK, MUX_G2_USXGMII_SEL);
-+	} else if (priv->gmac_id == 2) {
-+		sts = mtk_gmac_read(priv, XGMAC_STS(priv->gmac_id));
-+		sts |= XGMAC_FORCE_LINK;
-+		mtk_gmac_write(priv, XGMAC_STS(priv->gmac_id), sts);
-+	}
-+
-+	/* Force GMAC link down */
-+	mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), FORCE_MODE);
-+}
-+
- static void mtk_eth_fifo_init(struct mtk_eth_priv *priv)
- {
- 	char *pkt_base = priv->pkt_pool;
-@@ -1463,7 +1644,10 @@ static int mtk_eth_probe(struct udevice
- 				ARCH_DMA_MINALIGN);
- 
- 	/* Set MAC mode */
--	mtk_mac_init(priv);
-+	if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII)
-+		mtk_xmac_init(priv);
-+	else
-+		mtk_mac_init(priv);
- 
- 	/* Probe phy if switch is not specified */
- 	if (priv->sw == SW_NONE)
-@@ -1581,6 +1765,46 @@ static int mtk_eth_of_to_plat(struct ude
- 		}
- 
- 		priv->pn_swap = ofnode_read_bool(args.node, "pn_swap");
-+	} else if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII) {
-+		/* get corresponding usxgmii phandle */
-+		ret = dev_read_phandle_with_args(dev, "mediatek,usxgmiisys",
-+						 NULL, 0, 0, &args);
-+		if (ret)
-+			return ret;
-+
-+		priv->usxgmii_regmap = syscon_node_to_regmap(args.node);
-+		if (IS_ERR(priv->usxgmii_regmap))
-+			return PTR_ERR(priv->usxgmii_regmap);
-+
-+		/* get corresponding xfi_pextp phandle */
-+		ret = dev_read_phandle_with_args(dev, "mediatek,xfi_pextp",
-+						 NULL, 0, 0, &args);
-+		if (ret)
-+			return ret;
-+
-+		priv->xfi_pextp_regmap = syscon_node_to_regmap(args.node);
-+		if (IS_ERR(priv->xfi_pextp_regmap))
-+			return PTR_ERR(priv->xfi_pextp_regmap);
-+
-+		/* get corresponding xfi_pll phandle */
-+		ret = dev_read_phandle_with_args(dev, "mediatek,xfi_pll",
-+						 NULL, 0, 0, &args);
-+		if (ret)
-+			return ret;
-+
-+		priv->xfi_pll_regmap = syscon_node_to_regmap(args.node);
-+		if (IS_ERR(priv->xfi_pll_regmap))
-+			return PTR_ERR(priv->xfi_pll_regmap);
-+
-+		/* get corresponding toprgu phandle */
-+		ret = dev_read_phandle_with_args(dev, "mediatek,toprgu",
-+						 NULL, 0, 0, &args);
-+		if (ret)
-+			return ret;
-+
-+		priv->toprgu_regmap = syscon_node_to_regmap(args.node);
-+		if (IS_ERR(priv->toprgu_regmap))
-+			return PTR_ERR(priv->toprgu_regmap);
- 	}
- 
- 	/* check for switch first, otherwise phy will be used */
---- a/drivers/net/mtk_eth.h
-+++ b/drivers/net/mtk_eth.h
-@@ -68,6 +68,11 @@ enum mkt_eth_capabilities {
- #define ETHSYS_TRGMII_CLK_SEL362_5	BIT(11)
- 
- /* Top misc registers */
-+#define TOPMISC_NETSYS_PCS_MUX		0x84
-+#define NETSYS_PCS_MUX_MASK		GENMASK(1, 0)
-+#define MUX_G2_USXGMII_SEL		BIT(1)
-+#define MUX_HSGMII1_G1_SEL		BIT(0)
-+
- #define USB_PHY_SWITCH_REG		0x218
- #define QPHY_SEL_MASK			0x3
- #define SGMII_QPHY_SEL			0x2
-@@ -98,6 +103,15 @@ enum mkt_eth_capabilities {
- #define SGMSYS_GEN2_SPEED_V2		0x128
- #define SGMSYS_SPEED_2500		BIT(2)
- 
-+/* USXGMII subsystem config registers */
-+/* Register to control USXGMII XFI PLL digital */
-+#define XFI_PLL_DIG_GLB8		0x08
-+#define RG_XFI_PLL_EN			BIT(31)
-+
-+/* Register to control USXGMII XFI PLL analog */
-+#define XFI_PLL_ANA_GLB8		0x108
-+#define RG_XFI_PLL_ANA_SWWA		0x02283248
-+
- /* Frame Engine Registers */
- #define FE_GLO_MISC_REG			0x124
- #define PDMA_VER_V2			BIT(4)
-@@ -221,6 +235,16 @@ enum mkt_eth_capabilities {
- #define TD_DM_DRVP_S			0
- #define TD_DM_DRVP_M			0x0f
- 
-+/* XGMAC Status Registers */
-+#define XGMAC_STS(x)			(((x) == 2) ? 0x001C : 0x000C)
-+#define XGMAC_FORCE_LINK		BIT(15)
-+
-+/* XGMAC Registers */
-+#define XGMAC_PORT_MCR(x)		(0x2000 + (((x) - 1) * 0x1000))
-+#define XGMAC_TRX_DISABLE		0xf
-+#define XGMAC_FORCE_TX_FC		BIT(5)
-+#define XGMAC_FORCE_RX_FC		BIT(4)
-+
- /* MT7530 Registers */
- 
- #define PCR_REG(p)			(0x2004 + (p) * 0x100)
diff --git a/package/boot/uboot-mediatek/patches/101-25-net-mediatek-add-support-for-NETSYS-v3.patch b/package/boot/uboot-mediatek/patches/101-25-net-mediatek-add-support-for-NETSYS-v3.patch
deleted file mode 100644
index 691b59faed8ec4..00000000000000
--- a/package/boot/uboot-mediatek/patches/101-25-net-mediatek-add-support-for-NETSYS-v3.patch
+++ /dev/null
@@ -1,221 +0,0 @@
-From 7d201749cc49a58fb5e791d1e099ec3e3489e16d Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:17:37 +0800
-Subject: [PATCH 25/29] net: mediatek: add support for NETSYS v3
-
-This patch adds support for NETSYS v3 hardware.
-Comparing to NETSYS v2, NETSYS v3 has three GMACs.
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- drivers/net/mtk_eth.c | 49 ++++++++++++++++++++++++++++++++-----------
- drivers/net/mtk_eth.h |  7 +++++++
- 2 files changed, 44 insertions(+), 12 deletions(-)
-
---- a/drivers/net/mtk_eth.c
-+++ b/drivers/net/mtk_eth.c
-@@ -76,6 +76,7 @@ enum mtk_switch {
-  * @caps			Flags shown the extra capability for the SoC
-  * @ana_rgc3:			The offset for register ANA_RGC3 related to
-  *				sgmiisys syscon
-+ * @gdma_count:			Number of GDMAs
-  * @pdma_base:			Register base of PDMA block
-  * @txd_size:			Tx DMA descriptor size.
-  * @rxd_size:			Rx DMA descriptor size.
-@@ -83,6 +84,7 @@ enum mtk_switch {
- struct mtk_soc_data {
- 	u32 caps;
- 	u32 ana_rgc3;
-+	u32 gdma_count;
- 	u32 pdma_base;
- 	u32 txd_size;
- 	u32 rxd_size;
-@@ -159,7 +161,9 @@ static void mtk_gdma_write(struct mtk_et
- {
- 	u32 gdma_base;
- 
--	if (no == 1)
-+	if (no == 2)
-+		gdma_base = GDMA3_BASE;
-+	else if (no == 1)
- 		gdma_base = GDMA2_BASE;
- 	else
- 		gdma_base = GDMA1_BASE;
-@@ -1429,7 +1433,10 @@ static void mtk_eth_fifo_init(struct mtk
- 		txd->txd1 = virt_to_phys(pkt_base);
- 		txd->txd2 = PDMA_TXD2_DDONE | PDMA_TXD2_LS0;
- 
--		if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
-+		if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
-+			txd->txd5 = PDMA_V2_TXD5_FPORT_SET(priv->gmac_id == 2 ?
-+							   15 : priv->gmac_id + 1);
-+		else if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
- 			txd->txd5 = PDMA_V2_TXD5_FPORT_SET(priv->gmac_id + 1);
- 		else
- 			txd->txd4 = PDMA_V1_TXD4_FPORT_SET(priv->gmac_id + 1);
-@@ -1442,7 +1449,8 @@ static void mtk_eth_fifo_init(struct mtk
- 
- 		rxd->rxd1 = virt_to_phys(pkt_base);
- 
--		if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
-+		if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
-+		    MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
- 			rxd->rxd2 = PDMA_V2_RXD2_PLEN0_SET(PKTSIZE_ALIGN);
- 		else
- 			rxd->rxd2 = PDMA_V1_RXD2_PLEN0_SET(PKTSIZE_ALIGN);
-@@ -1466,7 +1474,7 @@ static void mtk_eth_fifo_init(struct mtk
- static int mtk_eth_start(struct udevice *dev)
- {
- 	struct mtk_eth_priv *priv = dev_get_priv(dev);
--	int ret;
-+	int i, ret;
- 
- 	/* Reset FE */
- 	reset_assert(&priv->rst_fe);
-@@ -1474,16 +1482,24 @@ static int mtk_eth_start(struct udevice
- 	reset_deassert(&priv->rst_fe);
- 	mdelay(10);
- 
--	if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
-+	if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
-+	    MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
- 		setbits_le32(priv->fe_base + FE_GLO_MISC_REG, PDMA_VER_V2);
- 
- 	/* Packets forward to PDMA */
- 	mtk_gdma_write(priv, priv->gmac_id, GDMA_IG_CTRL_REG, GDMA_FWD_TO_CPU);
- 
--	if (priv->gmac_id == 0)
--		mtk_gdma_write(priv, 1, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD);
--	else
--		mtk_gdma_write(priv, 0, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD);
-+	for (i = 0; i < priv->soc->gdma_count; i++) {
-+		if (i == priv->gmac_id)
-+			continue;
-+
-+		mtk_gdma_write(priv, i, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD);
-+	}
-+
-+	if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) {
-+		mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG,
-+			       GDMA_CPU_BRIDGE_EN);
-+	}
- 
- 	udelay(500);
- 
-@@ -1557,7 +1573,8 @@ static int mtk_eth_send(struct udevice *
- 	flush_dcache_range((ulong)pkt_base, (ulong)pkt_base +
- 			   roundup(length, ARCH_DMA_MINALIGN));
- 
--	if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
-+	if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
-+	    MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
- 		txd->txd2 = PDMA_TXD2_LS0 | PDMA_V2_TXD2_SDL0_SET(length);
- 	else
- 		txd->txd2 = PDMA_TXD2_LS0 | PDMA_V1_TXD2_SDL0_SET(length);
-@@ -1583,7 +1600,8 @@ static int mtk_eth_recv(struct udevice *
- 		return -EAGAIN;
- 	}
- 
--	if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
-+	if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
-+	    MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
- 		length = PDMA_V2_RXD2_PLEN0_GET(rxd->rxd2);
- 	else
- 		length = PDMA_V1_RXD2_PLEN0_GET(rxd->rxd2);
-@@ -1606,7 +1624,8 @@ static int mtk_eth_free_pkt(struct udevi
- 
- 	rxd = priv->rx_ring_noc + idx * priv->soc->rxd_size;
- 
--	if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
-+	if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
-+	    MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
- 		rxd->rxd2 = PDMA_V2_RXD2_PLEN0_SET(PKTSIZE_ALIGN);
- 	else
- 		rxd->rxd2 = PDMA_V1_RXD2_PLEN0_SET(PKTSIZE_ALIGN);
-@@ -1863,6 +1882,7 @@ static int mtk_eth_of_to_plat(struct ude
- static const struct mtk_soc_data mt7986_data = {
- 	.caps = MT7986_CAPS,
- 	.ana_rgc3 = 0x128,
-+	.gdma_count = 2,
- 	.pdma_base = PDMA_V2_BASE,
- 	.txd_size = sizeof(struct mtk_tx_dma_v2),
- 	.rxd_size = sizeof(struct mtk_rx_dma_v2),
-@@ -1871,6 +1891,7 @@ static const struct mtk_soc_data mt7986_
- static const struct mtk_soc_data mt7981_data = {
- 	.caps = MT7981_CAPS,
- 	.ana_rgc3 = 0x128,
-+	.gdma_count = 2,
- 	.pdma_base = PDMA_V2_BASE,
- 	.txd_size = sizeof(struct mtk_tx_dma_v2),
- 	.rxd_size = sizeof(struct mtk_rx_dma_v2),
-@@ -1878,6 +1899,7 @@ static const struct mtk_soc_data mt7981_
- 
- static const struct mtk_soc_data mt7629_data = {
- 	.ana_rgc3 = 0x128,
-+	.gdma_count = 2,
- 	.pdma_base = PDMA_V1_BASE,
- 	.txd_size = sizeof(struct mtk_tx_dma),
- 	.rxd_size = sizeof(struct mtk_rx_dma),
-@@ -1885,6 +1907,7 @@ static const struct mtk_soc_data mt7629_
- 
- static const struct mtk_soc_data mt7623_data = {
- 	.caps = MT7623_CAPS,
-+	.gdma_count = 2,
- 	.pdma_base = PDMA_V1_BASE,
- 	.txd_size = sizeof(struct mtk_tx_dma),
- 	.rxd_size = sizeof(struct mtk_rx_dma),
-@@ -1892,6 +1915,7 @@ static const struct mtk_soc_data mt7623_
- 
- static const struct mtk_soc_data mt7622_data = {
- 	.ana_rgc3 = 0x2028,
-+	.gdma_count = 2,
- 	.pdma_base = PDMA_V1_BASE,
- 	.txd_size = sizeof(struct mtk_tx_dma),
- 	.rxd_size = sizeof(struct mtk_rx_dma),
-@@ -1899,6 +1923,7 @@ static const struct mtk_soc_data mt7622_
- 
- static const struct mtk_soc_data mt7621_data = {
- 	.caps = MT7621_CAPS,
-+	.gdma_count = 2,
- 	.pdma_base = PDMA_V1_BASE,
- 	.txd_size = sizeof(struct mtk_tx_dma),
- 	.rxd_size = sizeof(struct mtk_rx_dma),
---- a/drivers/net/mtk_eth.h
-+++ b/drivers/net/mtk_eth.h
-@@ -18,6 +18,7 @@ enum mkt_eth_capabilities {
- 	MTK_U3_COPHY_V2_BIT,
- 	MTK_INFRA_BIT,
- 	MTK_NETSYS_V2_BIT,
-+	MTK_NETSYS_V3_BIT,
- 
- 	/* PATH BITS */
- 	MTK_ETH_PATH_GMAC1_TRGMII_BIT,
-@@ -29,6 +30,7 @@ enum mkt_eth_capabilities {
- #define MTK_U3_COPHY_V2			BIT(MTK_U3_COPHY_V2_BIT)
- #define MTK_INFRA			BIT(MTK_INFRA_BIT)
- #define MTK_NETSYS_V2			BIT(MTK_NETSYS_V2_BIT)
-+#define MTK_NETSYS_V3			BIT(MTK_NETSYS_V3_BIT)
- 
- /* Supported path present on SoCs */
- #define MTK_ETH_PATH_GMAC1_TRGMII	BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT)
-@@ -52,8 +54,10 @@ enum mkt_eth_capabilities {
- /* Frame Engine Register Bases */
- #define PDMA_V1_BASE			0x0800
- #define PDMA_V2_BASE			0x6000
-+#define PDMA_V3_BASE			0x6800
- #define GDMA1_BASE			0x0500
- #define GDMA2_BASE			0x1500
-+#define GDMA3_BASE			0x0540
- #define GMAC_BASE			0x10000
- 
- /* Ethernet subsystem registers */
-@@ -153,6 +157,9 @@ enum mkt_eth_capabilities {
- #define UN_DP_S				0
- #define UN_DP_M				0x0f
- 
-+#define GDMA_EG_CTRL_REG		0x004
-+#define GDMA_CPU_BRIDGE_EN		BIT(31)
-+
- #define GDMA_MAC_LSB_REG		0x008
- 
- #define GDMA_MAC_MSB_REG		0x00c
diff --git a/package/boot/uboot-mediatek/patches/101-26-net-mediatek-add-support-for-MediaTek-MT7988-SoC.patch b/package/boot/uboot-mediatek/patches/101-26-net-mediatek-add-support-for-MediaTek-MT7988-SoC.patch
deleted file mode 100644
index 29e86490521502..00000000000000
--- a/package/boot/uboot-mediatek/patches/101-26-net-mediatek-add-support-for-MediaTek-MT7988-SoC.patch
+++ /dev/null
@@ -1,327 +0,0 @@
-From 59dba9d87c9caf04a5d797af46699055a53870f4 Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:17:41 +0800
-Subject: [PATCH 26/29] net: mediatek: add support for MediaTek MT7988 SoC
-
-This patch adds support for MediaTek MT7988.
-
-MT7988 features MediaTek NETSYS v3, including three GMACs, and two
-of them supports 10Gbps USXGMII.
-
-MT7988 embeds a MT7531 switch (not MCM) which supports accessing
-internal registers through MMIO instead of MDIO.
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- drivers/net/mtk_eth.c | 158 +++++++++++++++++++++++++++++++++++++++++-
- drivers/net/mtk_eth.h |  20 ++++++
- 2 files changed, 177 insertions(+), 1 deletion(-)
-
---- a/drivers/net/mtk_eth.c
-+++ b/drivers/net/mtk_eth.c
-@@ -54,6 +54,16 @@
- 	(DP_PDMA << MC_DP_S) | \
- 	(DP_PDMA << UN_DP_S))
- 
-+#define GDMA_BRIDGE_TO_CPU \
-+	(0xC0000000 | \
-+	GDM_ICS_EN | \
-+	GDM_TCS_EN | \
-+	GDM_UCS_EN | \
-+	(DP_PDMA << MYMAC_DP_S) | \
-+	(DP_PDMA << BC_DP_S) | \
-+	(DP_PDMA << MC_DP_S) | \
-+	(DP_PDMA << UN_DP_S))
-+
- #define GDMA_FWD_DISCARD \
- 	(0x20000000 | \
- 	GDM_ICS_EN | \
-@@ -68,7 +78,8 @@
- enum mtk_switch {
- 	SW_NONE,
- 	SW_MT7530,
--	SW_MT7531
-+	SW_MT7531,
-+	SW_MT7988,
- };
- 
- /* struct mtk_soc_data -	This is the structure holding all differences
-@@ -102,6 +113,7 @@ struct mtk_eth_priv {
- 	void __iomem *fe_base;
- 	void __iomem *gmac_base;
- 	void __iomem *sgmii_base;
-+	void __iomem *gsw_base;
- 
- 	struct regmap *ethsys_regmap;
- 
-@@ -171,6 +183,11 @@ static void mtk_gdma_write(struct mtk_et
- 	writel(val, priv->fe_base + gdma_base + reg);
- }
- 
-+static void mtk_fe_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set)
-+{
-+	clrsetbits_le32(priv->fe_base + reg, clr, set);
-+}
-+
- static u32 mtk_gmac_read(struct mtk_eth_priv *priv, u32 reg)
- {
- 	return readl(priv->gmac_base + reg);
-@@ -208,6 +225,16 @@ static void mtk_infra_rmw(struct mtk_eth
- 	regmap_write(priv->infra_regmap, reg, val);
- }
- 
-+static u32 mtk_gsw_read(struct mtk_eth_priv *priv, u32 reg)
-+{
-+	return readl(priv->gsw_base + reg);
-+}
-+
-+static void mtk_gsw_write(struct mtk_eth_priv *priv, u32 reg, u32 val)
-+{
-+	writel(val, priv->gsw_base + reg);
-+}
-+
- /* Direct MDIO clause 22/45 access via SoC */
- static int mtk_mii_rw(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data,
- 		      u32 cmd, u32 st)
-@@ -342,6 +369,11 @@ static int mt753x_reg_read(struct mtk_et
- {
- 	int ret, low_word, high_word;
- 
-+	if (priv->sw == SW_MT7988) {
-+		*data = mtk_gsw_read(priv, reg);
-+		return 0;
-+	}
-+
- 	/* Write page address */
- 	ret = mtk_mii_write(priv, priv->mt753x_smi_addr, 0x1f, reg >> 6);
- 	if (ret)
-@@ -367,6 +399,11 @@ static int mt753x_reg_write(struct mtk_e
- {
- 	int ret;
- 
-+	if (priv->sw == SW_MT7988) {
-+		mtk_gsw_write(priv, reg, data);
-+		return 0;
-+	}
-+
- 	/* Write page address */
- 	ret = mtk_mii_write(priv, priv->mt753x_smi_addr, 0x1f, reg >> 6);
- 	if (ret)
-@@ -537,6 +574,7 @@ static int mtk_mdio_register(struct udev
- 		priv->mmd_write = mtk_mmd_ind_write;
- 		break;
- 	case SW_MT7531:
-+	case SW_MT7988:
- 		priv->mii_read = mt7531_mii_ind_read;
- 		priv->mii_write = mt7531_mii_ind_write;
- 		priv->mmd_read = mt7531_mmd_ind_read;
-@@ -957,6 +995,103 @@ static int mt7531_setup(struct mtk_eth_p
- 	return 0;
- }
- 
-+static void mt7988_phy_setting(struct mtk_eth_priv *priv)
-+{
-+	u16 val;
-+	u32 i;
-+
-+	for (i = 0; i < MT753X_NUM_PHYS; i++) {
-+		/* Enable HW auto downshift */
-+		priv->mii_write(priv, i, 0x1f, 0x1);
-+		val = priv->mii_read(priv, i, PHY_EXT_REG_14);
-+		val |= PHY_EN_DOWN_SHFIT;
-+		priv->mii_write(priv, i, PHY_EXT_REG_14, val);
-+
-+		/* PHY link down power saving enable */
-+		val = priv->mii_read(priv, i, PHY_EXT_REG_17);
-+		val |= PHY_LINKDOWN_POWER_SAVING_EN;
-+		priv->mii_write(priv, i, PHY_EXT_REG_17, val);
-+	}
-+}
-+
-+static void mt7988_mac_control(struct mtk_eth_priv *priv, bool enable)
-+{
-+	u32 pmcr = FORCE_MODE_LNK;
-+
-+	if (enable)
-+		pmcr = priv->mt753x_pmcr;
-+
-+	mt753x_reg_write(priv, PMCR_REG(6), pmcr);
-+}
-+
-+static int mt7988_setup(struct mtk_eth_priv *priv)
-+{
-+	u16 phy_addr, phy_val;
-+	u32 pmcr;
-+	int i;
-+
-+	priv->gsw_base = regmap_get_range(priv->ethsys_regmap, 0) + GSW_BASE;
-+
-+	priv->mt753x_phy_base = (priv->mt753x_smi_addr + 1) &
-+				MT753X_SMI_ADDR_MASK;
-+
-+	/* Turn off PHYs */
-+	for (i = 0; i < MT753X_NUM_PHYS; i++) {
-+		phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i);
-+		phy_val = priv->mii_read(priv, phy_addr, MII_BMCR);
-+		phy_val |= BMCR_PDOWN;
-+		priv->mii_write(priv, phy_addr, MII_BMCR, phy_val);
-+	}
-+
-+	switch (priv->phy_interface) {
-+	case PHY_INTERFACE_MODE_USXGMII:
-+		/* Use CPU bridge instead of actual USXGMII path */
-+
-+		/* Set GDM1 no drop */
-+		mtk_fe_rmw(priv, PSE_NO_DROP_CFG_REG, 0, PSE_NO_DROP_GDM1);
-+
-+		/* Enable GDM1 to GSW CPU bridge */
-+		mtk_gmac_rmw(priv, GMAC_MAC_MISC_REG, 0, BIT(0));
-+
-+		/* XGMAC force link up */
-+		mtk_gmac_rmw(priv, GMAC_XGMAC_STS_REG, 0, P1_XGMAC_FORCE_LINK);
-+
-+		/* Setup GSW CPU bridge IPG */
-+		mtk_gmac_rmw(priv, GMAC_GSW_CFG_REG, GSWTX_IPG_M | GSWRX_IPG_M,
-+			     (0xB << GSWTX_IPG_S) | (0xB << GSWRX_IPG_S));
-+		break;
-+	default:
-+		printf("Error: MT7988 GSW does not support %s interface\n",
-+		       phy_string_for_interface(priv->phy_interface));
-+		break;
-+	}
-+
-+	pmcr = MT7988_FORCE_MODE |
-+	       (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) |
-+	       MAC_MODE | MAC_TX_EN | MAC_RX_EN |
-+	       BKOFF_EN | BACKPR_EN |
-+	       FORCE_RX_FC | FORCE_TX_FC |
-+	       (SPEED_1000M << FORCE_SPD_S) | FORCE_DPX |
-+	       FORCE_LINK;
-+
-+	priv->mt753x_pmcr = pmcr;
-+
-+	/* Keep MAC link down before starting eth */
-+	mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK);
-+
-+	/* Turn on PHYs */
-+	for (i = 0; i < MT753X_NUM_PHYS; i++) {
-+		phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i);
-+		phy_val = priv->mii_read(priv, phy_addr, MII_BMCR);
-+		phy_val &= ~BMCR_PDOWN;
-+		priv->mii_write(priv, phy_addr, MII_BMCR, phy_val);
-+	}
-+
-+	mt7988_phy_setting(priv);
-+
-+	return 0;
-+}
-+
- static int mt753x_switch_init(struct mtk_eth_priv *priv)
- {
- 	int ret;
-@@ -1497,6 +1632,11 @@ static int mtk_eth_start(struct udevice
- 	}
- 
- 	if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) {
-+		if (priv->sw == SW_MT7988 && priv->gmac_id == 0) {
-+			mtk_gdma_write(priv, priv->gmac_id, GDMA_IG_CTRL_REG,
-+				       GDMA_BRIDGE_TO_CPU);
-+		}
-+
- 		mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG,
- 			       GDMA_CPU_BRIDGE_EN);
- 	}
-@@ -1845,6 +1985,12 @@ static int mtk_eth_of_to_plat(struct ude
- 			priv->switch_mac_control = mt7531_mac_control;
- 			priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR;
- 			priv->mt753x_reset_wait_time = 200;
-+		} else if (!strcmp(str, "mt7988")) {
-+			priv->sw = SW_MT7988;
-+			priv->switch_init = mt7988_setup;
-+			priv->switch_mac_control = mt7988_mac_control;
-+			priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR;
-+			priv->mt753x_reset_wait_time = 50;
- 		} else {
- 			printf("error: unsupported switch\n");
- 			return -EINVAL;
-@@ -1879,6 +2025,15 @@ static int mtk_eth_of_to_plat(struct ude
- 	return 0;
- }
- 
-+static const struct mtk_soc_data mt7988_data = {
-+	.caps = MT7988_CAPS,
-+	.ana_rgc3 = 0x128,
-+	.gdma_count = 3,
-+	.pdma_base = PDMA_V3_BASE,
-+	.txd_size = sizeof(struct mtk_tx_dma_v2),
-+	.rxd_size = sizeof(struct mtk_rx_dma_v2),
-+};
-+
- static const struct mtk_soc_data mt7986_data = {
- 	.caps = MT7986_CAPS,
- 	.ana_rgc3 = 0x128,
-@@ -1930,6 +2085,7 @@ static const struct mtk_soc_data mt7621_
- };
- 
- static const struct udevice_id mtk_eth_ids[] = {
-+	{ .compatible = "mediatek,mt7988-eth", .data = (ulong)&mt7988_data },
- 	{ .compatible = "mediatek,mt7986-eth", .data = (ulong)&mt7986_data },
- 	{ .compatible = "mediatek,mt7981-eth", .data = (ulong)&mt7981_data },
- 	{ .compatible = "mediatek,mt7629-eth", .data = (ulong)&mt7629_data },
---- a/drivers/net/mtk_eth.h
-+++ b/drivers/net/mtk_eth.h
-@@ -51,6 +51,8 @@ enum mkt_eth_capabilities {
- 
- #define MT7986_CAPS  (MTK_NETSYS_V2)
- 
-+#define MT7988_CAPS  (MTK_NETSYS_V3 | MTK_INFRA)
-+
- /* Frame Engine Register Bases */
- #define PDMA_V1_BASE			0x0800
- #define PDMA_V2_BASE			0x6000
-@@ -59,6 +61,7 @@ enum mkt_eth_capabilities {
- #define GDMA2_BASE			0x1500
- #define GDMA3_BASE			0x0540
- #define GMAC_BASE			0x10000
-+#define GSW_BASE			0x20000
- 
- /* Ethernet subsystem registers */
- 
-@@ -117,6 +120,9 @@ enum mkt_eth_capabilities {
- #define RG_XFI_PLL_ANA_SWWA		0x02283248
- 
- /* Frame Engine Registers */
-+#define PSE_NO_DROP_CFG_REG		0x108
-+#define PSE_NO_DROP_GDM1		BIT(1)
-+
- #define FE_GLO_MISC_REG			0x124
- #define PDMA_VER_V2			BIT(4)
- 
-@@ -187,6 +193,17 @@ enum mkt_eth_capabilities {
- #define MDIO_RW_DATA_S			0
- #define MDIO_RW_DATA_M			0xffff
- 
-+#define GMAC_XGMAC_STS_REG		0x000c
-+#define P1_XGMAC_FORCE_LINK		BIT(15)
-+
-+#define GMAC_MAC_MISC_REG		0x0010
-+
-+#define GMAC_GSW_CFG_REG		0x0080
-+#define GSWTX_IPG_M			0xF0000
-+#define GSWTX_IPG_S			16
-+#define GSWRX_IPG_M			0xF
-+#define GSWRX_IPG_S			0
-+
- /* MDIO_CMD: MDIO commands */
- #define MDIO_CMD_ADDR			0
- #define MDIO_CMD_WRITE			1
-@@ -285,6 +302,9 @@ enum mkt_eth_capabilities {
- 					FORCE_MODE_TX_FC | FORCE_MODE_RX_FC | \
- 					FORCE_MODE_DPX   | FORCE_MODE_SPD | \
- 					FORCE_MODE_LNK
-+#define MT7988_FORCE_MODE		FORCE_MODE_TX_FC | FORCE_MODE_RX_FC | \
-+					FORCE_MODE_DPX   | FORCE_MODE_SPD | \
-+					FORCE_MODE_LNK
- 
- /* MT7531 SGMII Registers */
- #define MT7531_SGMII_REG_BASE		0x5000
diff --git a/package/boot/uboot-mediatek/patches/101-27-tools-mtk_image-use-uint32_t-for-ghf-header-magic-an.patch b/package/boot/uboot-mediatek/patches/101-27-tools-mtk_image-use-uint32_t-for-ghf-header-magic-an.patch
deleted file mode 100644
index 07620f77b31400..00000000000000
--- a/package/boot/uboot-mediatek/patches/101-27-tools-mtk_image-use-uint32_t-for-ghf-header-magic-an.patch
+++ /dev/null
@@ -1,55 +0,0 @@
-From 757b997f1f5a958e6fec3d5aee1ff5cdf5766711 Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:17:45 +0800
-Subject: [PATCH 27/29] tools: mtk_image: use uint32_t for ghf header magic and
- version
-
-This patch converts magic and version fields of ghf common header
-to one field with the type of uint32_t to make this header flexible
-for futher updates.
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- tools/mtk_image.c | 10 ++++++----
- tools/mtk_image.h |  6 +++---
- 2 files changed, 9 insertions(+), 7 deletions(-)
-
---- a/tools/mtk_image.c
-+++ b/tools/mtk_image.c
-@@ -542,11 +542,13 @@ static void put_brom_layout_header(struc
- 	hdr->type = cpu_to_le32(type);
- }
- 
--static void put_ghf_common_header(struct gfh_common_header *gfh, int size,
--				  int type, int ver)
-+static void put_ghf_common_header(struct gfh_common_header *gfh, uint16_t size,
-+				  uint16_t type, uint8_t ver)
- {
--	memcpy(gfh->magic, GFH_HEADER_MAGIC, sizeof(gfh->magic));
--	gfh->version = ver;
-+	uint32_t magic_version = GFH_HEADER_MAGIC |
-+				 (uint32_t)ver << GFH_HEADER_VERSION_SHIFT;
-+
-+	gfh->magic_version = cpu_to_le32(magic_version);
- 	gfh->size = cpu_to_le16(size);
- 	gfh->type = cpu_to_le16(type);
- }
---- a/tools/mtk_image.h
-+++ b/tools/mtk_image.h
-@@ -63,13 +63,13 @@ struct gen_device_header {
- 
- /* BootROM header definitions */
- struct gfh_common_header {
--	uint8_t magic[3];
--	uint8_t version;
-+	uint32_t magic_version;
- 	uint16_t size;
- 	uint16_t type;
- };
- 
--#define GFH_HEADER_MAGIC	"MMM"
-+#define GFH_HEADER_MAGIC		0x4D4D4D
-+#define GFH_HEADER_VERSION_SHIFT	24
- 
- #define GFH_TYPE_FILE_INFO	0
- #define GFH_TYPE_BL_INFO	1
diff --git a/package/boot/uboot-mediatek/patches/101-28-arm-mediatek-add-support-for-MediaTek-MT7988-SoC.patch b/package/boot/uboot-mediatek/patches/101-28-arm-mediatek-add-support-for-MediaTek-MT7988-SoC.patch
deleted file mode 100644
index f54a028b4262b8..00000000000000
--- a/package/boot/uboot-mediatek/patches/101-28-arm-mediatek-add-support-for-MediaTek-MT7988-SoC.patch
+++ /dev/null
@@ -1,606 +0,0 @@
-From 884430dadcc2c5d0a2b248795001955a9fa5a1a9 Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:17:49 +0800
-Subject: [PATCH 28/29] arm: mediatek: add support for MediaTek MT7988 SoC
-
-This patch adds basic support for MediaTek MT7988 SoC.
-This includes files that will initialize the SoC after boot and
-its device tree.
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- arch/arm/dts/mt7988-u-boot.dtsi               |  25 ++
- arch/arm/dts/mt7988.dtsi                      | 391 ++++++++++++++++++
- arch/arm/mach-mediatek/Kconfig                |  13 +-
- arch/arm/mach-mediatek/Makefile               |   1 +
- arch/arm/mach-mediatek/mt7988/Makefile        |   4 +
- arch/arm/mach-mediatek/mt7988/init.c          |  63 +++
- arch/arm/mach-mediatek/mt7988/lowlevel_init.S |  30 ++
- 7 files changed, 526 insertions(+), 1 deletion(-)
- create mode 100644 arch/arm/dts/mt7988-u-boot.dtsi
- create mode 100644 arch/arm/dts/mt7988.dtsi
- create mode 100644 arch/arm/mach-mediatek/mt7988/Makefile
- create mode 100644 arch/arm/mach-mediatek/mt7988/init.c
- create mode 100644 arch/arm/mach-mediatek/mt7988/lowlevel_init.S
-
---- /dev/null
-+++ b/arch/arm/dts/mt7988-u-boot.dtsi
-@@ -0,0 +1,25 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2022 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ */
-+
-+&system_clk {
-+	bootph-all;
-+};
-+
-+&spi_clk {
-+	bootph-all;
-+};
-+
-+&uart0 {
-+	bootph-all;
-+};
-+
-+&uart1 {
-+	bootph-all;
-+};
-+
-+&uart2 {
-+	bootph-all;
-+};
---- /dev/null
-+++ b/arch/arm/dts/mt7988.dtsi
-@@ -0,0 +1,391 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2022 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ */
-+
-+#include <dt-bindings/interrupt-controller/irq.h>
-+#include <dt-bindings/interrupt-controller/arm-gic.h>
-+#include <dt-bindings/clock/mt7988-clk.h>
-+#include <dt-bindings/reset/mt7988-reset.h>
-+#include <dt-bindings/gpio/gpio.h>
-+
-+/ {
-+	compatible = "mediatek,mt7988-rfb";
-+	interrupt-parent = <&gic>;
-+	#address-cells = <2>;
-+	#size-cells = <2>;
-+
-+	cpus {
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+
-+		cpu0: cpu@0 {
-+			device_type = "cpu";
-+			compatible = "arm,cortex-a73";
-+			reg = <0x0>;
-+			mediatek,hwver = <&hwver>;
-+		};
-+
-+		cpu1: cpu@1 {
-+			device_type = "cpu";
-+			compatible = "arm,cortex-a73";
-+			reg = <0x1>;
-+			mediatek,hwver = <&hwver>;
-+		};
-+
-+		cpu2: cpu@2 {
-+			device_type = "cpu";
-+			compatible = "arm,cortex-a73";
-+			reg = <0x2>;
-+			mediatek,hwver = <&hwver>;
-+		};
-+
-+		cpu3: cpu@3 {
-+			device_type = "cpu";
-+			compatible = "arm,cortex-a73";
-+			reg = <0x3>;
-+			mediatek,hwver = <&hwver>;
-+		};
-+	};
-+
-+	system_clk: dummy40m {
-+		compatible = "fixed-clock";
-+		clock-frequency = <40000000>;
-+		#clock-cells = <0>;
-+	};
-+
-+	spi_clk: dummy208m {
-+		compatible = "fixed-clock";
-+		clock-frequency = <208000000>;
-+		#clock-cells = <0>;
-+	};
-+
-+	hwver: hwver {
-+		compatible = "mediatek,hwver", "syscon";
-+		reg = <0 0x8000000 0 0x1000>;
-+	};
-+
-+	timer {
-+		compatible = "arm,armv8-timer";
-+		interrupt-parent = <&gic>;
-+		clock-frequency = <13000000>;
-+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
-+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
-+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
-+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
-+	};
-+
-+	watchdog: watchdog@1001c000 {
-+		compatible = "mediatek,mt7622-wdt",
-+			     "mediatek,mt6589-wdt",
-+			     "syscon";
-+		reg = <0 0x1001c000 0 0x1000>;
-+		interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
-+		#reset-cells = <1>;
-+	};
-+
-+	gic: interrupt-controller@c000000 {
-+		compatible = "arm,gic-v3";
-+		#interrupt-cells = <3>;
-+		interrupt-parent = <&gic>;
-+		interrupt-controller;
-+		reg = <0 0x0c000000 0 0x40000>,  /* GICD */
-+		      <0 0x0c080000 0 0x200000>; /* GICR */
-+		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
-+	};
-+
-+	infracfg_ao_cgs: infracfg_ao_cgs@10001000 {
-+		compatible = "mediatek,mt7988-infracfg_ao_cgs", "syscon";
-+		reg = <0 0x10001000 0 0x1000>;
-+		clock-parent = <&infracfg_ao>;
-+		#clock-cells = <1>;
-+	};
-+
-+	apmixedsys: apmixedsys@1001e000 {
-+		compatible = "mediatek,mt7988-fixed-plls", "syscon";
-+		reg = <0 0x1001e000 0 0x1000>;
-+		#clock-cells = <1>;
-+	};
-+
-+	topckgen: topckgen@1001b000 {
-+		compatible = "mediatek,mt7988-topckgen", "syscon";
-+		reg = <0 0x1001b000 0 0x1000>;
-+		clock-parent = <&apmixedsys>;
-+		#clock-cells = <1>;
-+	};
-+
-+	pinctrl: pinctrl@1001f000 {
-+		compatible = "mediatek,mt7988-pinctrl";
-+		reg = <0 0x1001f000 0 0x1000>,
-+		      <0 0x11c10000 0 0x1000>,
-+		      <0 0x11d00000 0 0x1000>,
-+		      <0 0x11d20000 0 0x1000>,
-+		      <0 0x11e00000 0 0x1000>,
-+		      <0 0x11f00000 0 0x1000>,
-+		      <0 0x1000b000 0 0x1000>;
-+		reg-names = "gpio_base", "iocfg_tr_base", "iocfg_br_base",
-+			    "iocfg_rb_base", "iocfg_lb_base", "iocfg_tl_base",
-+			    "eint";
-+		gpio: gpio-controller {
-+			gpio-controller;
-+			#gpio-cells = <2>;
-+		};
-+	};
-+
-+	sgmiisys0: syscon@10060000 {
-+		compatible = "mediatek,mt7988-sgmiisys_0", "syscon";
-+		reg = <0 0x10060000 0 0x1000>;
-+		clock-parent = <&topckgen>;
-+		#clock-cells = <1>;
-+	};
-+
-+	sgmiisys1: syscon@10070000 {
-+		compatible = "mediatek,mt7988-sgmiisys_1", "syscon";
-+		reg = <0 0x10070000 0 0x1000>;
-+		clock-parent = <&topckgen>;
-+		#clock-cells = <1>;
-+	};
-+
-+	usxgmiisys0: syscon@10080000 {
-+		compatible = "mediatek,mt7988-usxgmiisys_0", "syscon";
-+		reg = <0 0x10080000 0 0x1000>;
-+		clock-parent = <&topckgen>;
-+		#clock-cells = <1>;
-+	};
-+
-+	usxgmiisys1: syscon@10081000 {
-+		compatible = "mediatek,mt7988-usxgmiisys_1", "syscon";
-+		reg = <0 0x10081000 0 0x1000>;
-+		clock-parent = <&topckgen>;
-+		#clock-cells = <1>;
-+	};
-+
-+	xfi_pextp0: syscon@11f20000 {
-+		compatible = "mediatek,mt7988-xfi_pextp_0", "syscon";
-+		reg = <0 0x11f20000 0 0x10000>;
-+		clock-parent = <&topckgen>;
-+		#clock-cells = <1>;
-+	};
-+
-+	xfi_pextp1: syscon@11f30000 {
-+		compatible = "mediatek,mt7988-xfi_pextp_1", "syscon";
-+		reg = <0 0x11f30000 0 0x10000>;
-+		clock-parent = <&topckgen>;
-+		#clock-cells = <1>;
-+	};
-+
-+	xfi_pll: syscon@11f40000 {
-+		compatible = "mediatek,mt7988-xfi_pll", "syscon";
-+		reg = <0 0x11f40000 0 0x1000>;
-+		clock-parent = <&topckgen>;
-+		#clock-cells = <1>;
-+	};
-+
-+	topmisc: topmisc@11d10000 {
-+		compatible = "mediatek,mt7988-topmisc", "syscon",
-+			     "mediatek,mt7988-power-controller";
-+		reg = <0 0x11d10000 0 0x10000>;
-+		clock-parent = <&topckgen>;
-+		#clock-cells = <1>;
-+	};
-+
-+	infracfg_ao: infracfg@10001000 {
-+		compatible = "mediatek,mt7988-infracfg", "syscon";
-+		reg = <0 0x10001000 0 0x1000>;
-+		clock-parent = <&topckgen>;
-+		#clock-cells = <1>;
-+	};
-+
-+	uart0: serial@11000000 {
-+		compatible = "mediatek,hsuart";
-+		reg = <0 0x11000000 0 0x100>;
-+		interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
-+		clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART0_CK>;
-+		assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
-+				  <&infracfg_ao CK_INFRA_MUX_UART0_SEL>;
-+		assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
-+					 <&infracfg_ao CK_INFRA_UART_O0>;
-+		status = "disabled";
-+	};
-+
-+	uart1: serial@11000100 {
-+		compatible = "mediatek,hsuart";
-+		reg = <0 0x11000100 0 0x100>;
-+		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
-+		clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART1_CK>;
-+		assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
-+				  <&infracfg_ao CK_INFRA_MUX_UART1_SEL>;
-+		assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
-+					 <&infracfg_ao CK_INFRA_UART_O1>;
-+		status = "disabled";
-+	};
-+
-+	uart2: serial@11000200 {
-+		compatible = "mediatek,hsuart";
-+		reg = <0 0x11000200 0 0x100>;
-+		interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
-+		clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART2_CK>;
-+		assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
-+				  <&infracfg_ao CK_INFRA_MUX_UART2_SEL>;
-+		assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
-+					 <&infracfg_ao CK_INFRA_UART_O2>;
-+		status = "disabled";
-+	};
-+
-+	i2c0: i2c@11003000 {
-+		compatible = "mediatek,mt7988-i2c",
-+			     "mediatek,mt7981-i2c";
-+		reg = <0 0x11003000 0 0x1000>,
-+		      <0 0x10217080 0 0x80>;
-+		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
-+		clock-div = <1>;
-+		clocks = <&infracfg_ao CK_INFRA_I2C_BCK>,
-+			 <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>;
-+		clock-names = "main", "dma";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		status = "disabled";
-+	};
-+
-+	i2c1: i2c@11004000 {
-+		compatible = "mediatek,mt7988-i2c",
-+			     "mediatek,mt7981-i2c";
-+		reg = <0 0x11004000 0 0x1000>,
-+		      <0 0x10217100 0 0x80>;
-+		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
-+		clock-div = <1>;
-+		clocks = <&infracfg_ao CK_INFRA_I2C_BCK>,
-+			 <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>;
-+		clock-names = "main", "dma";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		status = "disabled";
-+	};
-+
-+	i2c2: i2c@11005000 {
-+		compatible = "mediatek,mt7988-i2c",
-+			     "mediatek,mt7981-i2c";
-+		reg = <0 0x11005000 0 0x1000>,
-+		      <0 0x10217180 0 0x80>;
-+		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
-+		clock-div = <1>;
-+		clocks = <&infracfg_ao CK_INFRA_I2C_BCK>,
-+			 <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>;
-+		clock-names = "main", "dma";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		status = "disabled";
-+	};
-+
-+	pwm: pwm@10048000 {
-+		compatible = "mediatek,mt7988-pwm";
-+		reg = <0 0x10048000 0 0x1000>;
-+		#pwm-cells = <2>;
-+		clocks = <&infracfg_ao CK_INFRA_66M_PWM_BCK>,
-+			 <&infracfg_ao CK_INFRA_66M_PWM_HCK>,
-+			 <&infracfg_ao CK_INFRA_66M_PWM_CK1>,
-+			 <&infracfg_ao CK_INFRA_66M_PWM_CK2>,
-+			 <&infracfg_ao CK_INFRA_66M_PWM_CK3>,
-+			 <&infracfg_ao CK_INFRA_66M_PWM_CK4>,
-+			 <&infracfg_ao CK_INFRA_66M_PWM_CK5>,
-+			 <&infracfg_ao CK_INFRA_66M_PWM_CK6>,
-+			 <&infracfg_ao CK_INFRA_66M_PWM_CK7>,
-+			 <&infracfg_ao CK_INFRA_66M_PWM_CK8>;
-+		clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
-+			      "pwm4","pwm5","pwm6","pwm7","pwm8";
-+		status = "disabled";
-+	};
-+
-+	snand: snand@11001000 {
-+		compatible = "mediatek,mt7988-snand",
-+			     "mediatek,mt7986-snand";
-+		reg = <0 0x11001000 0 0x1000>,
-+		      <0 0x11002000 0 0x1000>;
-+		reg-names = "nfi", "ecc";
-+		interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
-+		clocks = <&infracfg_ao CK_INFRA_SPINFI>,
-+			 <&infracfg_ao CK_INFRA_NFI>,
-+			 <&infracfg_ao CK_INFRA_66M_NFI_HCK>;
-+		clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
-+		assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>,
-+				  <&topckgen CK_TOP_NFI1X_SEL>;
-+		assigned-clock-parents = <&topckgen CK_TOP_CB_M_D8>,
-+					 <&topckgen CK_TOP_CB_M_D8>;
-+		status = "disabled";
-+	};
-+
-+	spi0: spi@1100a000 {
-+		compatible = "mediatek,ipm-spi";
-+		reg = <0 0x11007000 0 0x100>;
-+		clocks = <&spi_clk>,
-+			 <&spi_clk>;
-+		clock-names = "sel-clk", "spi-clk";
-+		interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
-+		status = "disabled";
-+	};
-+
-+	spi1: spi@1100b000 {
-+		compatible = "mediatek,ipm-spi";
-+		reg = <0 0x11008000 0 0x100>;
-+		interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
-+		status = "disabled";
-+	};
-+
-+	spi2: spi@11009000 {
-+		compatible = "mediatek,ipm-spi";
-+		reg = <0 0x11009000 0 0x100>;
-+		clocks = <&spi_clk>,
-+			 <&spi_clk>;
-+		clock-names = "sel-clk", "spi-clk";
-+		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
-+		status = "disabled";
-+	};
-+
-+	mmc0: mmc@11230000 {
-+		compatible = "mediatek,mt7988-mmc",
-+			     "mediatek,mt7986-mmc";
-+		reg = <0 0x11230000 0 0x1000>;
-+		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
-+		clocks = <&infracfg_ao_cgs CK_INFRA_MSDC400>,
-+			 <&infracfg_ao_cgs CK_INFRA_MSDC2_HCK>,
-+			 <&infracfg_ao_cgs CK_INFRA_133M_MSDC_0_HCK>,
-+			 <&infracfg_ao_cgs CK_INFRA_66M_MSDC_0_HCK>;
-+		clock-names = "source", "hclk", "source_cg", "axi_cg";
-+		status = "disabled";
-+	};
-+
-+	ethdma: syscon@15000000 {
-+		compatible = "mediatek,mt7988-ethdma", "syscon";
-+		reg = <0 0x15000000 0 0x20000>;
-+		clock-parent = <&topckgen>;
-+		#clock-cells = <1>;
-+		#reset-cells = <1>;
-+	};
-+
-+	ethwarp: syscon@15031000 {
-+		compatible = "mediatek,mt7988-ethwarp", "syscon";
-+		reg = <0 0x15031000 0 0x1000>;
-+		clock-parent = <&topckgen>;
-+		#clock-cells = <1>;
-+		#reset-cells = <1>;
-+	};
-+
-+	eth: ethernet@15100000 {
-+		compatible = "mediatek,mt7988-eth", "syscon";
-+		reg = <0 0x15100000 0 0x20000>;
-+		mediatek,ethsys = <&ethdma>;
-+		mediatek,sgmiisys = <&sgmiisys0>;
-+		mediatek,usxgmiisys = <&usxgmiisys0>;
-+		mediatek,xfi_pextp = <&xfi_pextp0>;
-+		mediatek,xfi_pll = <&xfi_pll>;
-+		mediatek,infracfg = <&topmisc>;
-+		mediatek,toprgu = <&watchdog>;
-+		resets = <&ethdma ETHDMA_FE_RST>, <&ethwarp ETHWARP_GSW_RST>;
-+		reset-names = "fe", "mcm";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		mediatek,mcm;
-+		status = "disabled";
-+	};
-+};
---- a/arch/arm/mach-mediatek/Kconfig
-+++ b/arch/arm/mach-mediatek/Kconfig
-@@ -58,6 +58,15 @@ config TARGET_MT7986
- 	  including UART, SPI, SPI flash, USB3.0, MMC, NAND, SNFI, PWM, PCIe,
- 	  Gigabit Ethernet, I2C, built-in 4x4 Wi-Fi, and PCIe.
- 
-+config TARGET_MT7988
-+	bool "MediaTek MT7988 SoC"
-+	select ARM64
-+	select CPU
-+	help
-+	  The MediaTek MT7988 is a ARM64-based SoC with a quad-core Cortex-A73.
-+	  including UART, SPI, SPI flash, USB3.0, MMC, NAND, SNFI, PWM, PCIe,
-+	  10 Gigabit Ethernet , I2C, and PCIe.
-+
- config TARGET_MT8183
- 	bool "MediaTek MT8183 SoC"
- 	select ARM64
-@@ -104,6 +113,7 @@ config SYS_BOARD
- 	default "mt7629" if TARGET_MT7629
- 	default "mt7981" if TARGET_MT7981
- 	default "mt7986" if TARGET_MT7986
-+	default "mt7988" if TARGET_MT7988
- 	default "mt8183" if TARGET_MT8183
- 	default "mt8512" if TARGET_MT8512
- 	default "mt8516" if TARGET_MT8516
-@@ -121,6 +131,7 @@ config SYS_CONFIG_NAME
- 	default "mt7629" if TARGET_MT7629
- 	default "mt7981" if TARGET_MT7981
- 	default "mt7986" if TARGET_MT7986
-+	default "mt7988" if TARGET_MT7988
- 	default "mt8183" if TARGET_MT8183
- 	default "mt8512" if TARGET_MT8512
- 	default "mt8516" if TARGET_MT8516
-@@ -135,7 +146,7 @@ config MTK_BROM_HEADER_INFO
- 	string
- 	default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7622
- 	default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183
--	default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986
-+	default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986 || TARGET_MT7988
- 	default "lk=1" if TARGET_MT7623
- 
- source "board/mediatek/mt7629/Kconfig"
---- a/arch/arm/mach-mediatek/Makefile
-+++ b/arch/arm/mach-mediatek/Makefile
-@@ -9,6 +9,7 @@ obj-$(CONFIG_TARGET_MT7623) += mt7623/
- obj-$(CONFIG_TARGET_MT7629) += mt7629/
- obj-$(CONFIG_TARGET_MT7981) += mt7981/
- obj-$(CONFIG_TARGET_MT7986) += mt7986/
-+obj-$(CONFIG_TARGET_MT7988) += mt7988/
- obj-$(CONFIG_TARGET_MT8183) += mt8183/
- obj-$(CONFIG_TARGET_MT8516) += mt8516/
- obj-$(CONFIG_TARGET_MT8518) += mt8518/
---- /dev/null
-+++ b/arch/arm/mach-mediatek/mt7988/Makefile
-@@ -0,0 +1,4 @@
-+# SPDX-License-Identifier:	GPL-2.0
-+
-+obj-y += init.o
-+obj-y += lowlevel_init.o
---- /dev/null
-+++ b/arch/arm/mach-mediatek/mt7988/init.c
-@@ -0,0 +1,63 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (C) 2022 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ */
-+
-+#include <fdtdec.h>
-+#include <init.h>
-+#include <asm/armv8/mmu.h>
-+#include <asm/global_data.h>
-+#include <asm/u-boot.h>
-+#include <asm/system.h>
-+
-+DECLARE_GLOBAL_DATA_PTR;
-+
-+#define SZ_8G				_AC(0x200000000, ULL)
-+
-+int dram_init(void)
-+{
-+	int ret;
-+
-+	ret = fdtdec_setup_mem_size_base();
-+	if (ret)
-+		return ret;
-+
-+	gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_8G);
-+
-+	return 0;
-+}
-+
-+int dram_init_banksize(void)
-+{
-+	gd->bd->bi_dram[0].start = gd->ram_base;
-+	gd->bd->bi_dram[0].size = gd->ram_size;
-+
-+	return 0;
-+}
-+
-+void reset_cpu(ulong addr)
-+{
-+	psci_system_reset();
-+}
-+
-+static struct mm_region mt7988_mem_map[] = {
-+	{
-+		/* DDR */
-+		.virt = 0x40000000UL,
-+		.phys = 0x40000000UL,
-+		.size = 0x200000000ULL,
-+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
-+	}, {
-+		.virt = 0x00000000UL,
-+		.phys = 0x00000000UL,
-+		.size = 0x40000000UL,
-+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-+			 PTE_BLOCK_NON_SHARE |
-+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
-+	}, {
-+		0,
-+	}
-+};
-+
-+struct mm_region *mem_map = mt7988_mem_map;
---- /dev/null
-+++ b/arch/arm/mach-mediatek/mt7988/lowlevel_init.S
-@@ -0,0 +1,30 @@
-+/* SPDX-License-Identifier: GPL-2.0 */
-+/*
-+ * Copyright (C) 2020 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ */
-+
-+/*
-+ * Switch from AArch64 EL2 to AArch32 EL2
-+ * @param inputs:
-+ * x0: argument, zero
-+ * x1: machine nr
-+ * x2: fdt address
-+ * x3: input argument
-+ * x4: kernel entry point
-+ * @param outputs for secure firmware:
-+ * x0: function id
-+ * x1: kernel entry point
-+ * x2: machine nr
-+ * x3: fdt address
-+*/
-+
-+.global armv8_el2_to_aarch32
-+armv8_el2_to_aarch32:
-+	mov     x3, x2
-+	mov     x2, x1
-+	mov     x1, x4
-+	mov	x4, #0
-+	ldr x0, =0x82000200
-+	SMC #0
-+	ret
diff --git a/package/boot/uboot-mediatek/patches/101-29-board-mediatek-add-MT7988-reference-boards.patch b/package/boot/uboot-mediatek/patches/101-29-board-mediatek-add-MT7988-reference-boards.patch
deleted file mode 100644
index ef41f4d56a0e77..00000000000000
--- a/package/boot/uboot-mediatek/patches/101-29-board-mediatek-add-MT7988-reference-boards.patch
+++ /dev/null
@@ -1,575 +0,0 @@
-From fd7d9124ffa6761f27747daeea599e0ab874c1fa Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:17:54 +0800
-Subject: [PATCH 29/29] board: mediatek: add MT7988 reference boards
-
-This patch adds general board files based on MT7988 SoCs.
-
-MT7988 uses one mmc controller for booting from both SD and eMMC,
-and the pins of mmc controller booting from SD are also shared with
-one of spi controllers.
-So two configs are need for these boot types:
-
-1. mt7988_rfb_defconfig - SPI-NOR, SPI-NAND and eMMC
-2. mt7988_sd_rfb_defconfig - SPI-NAND and SD
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- arch/arm/dts/Makefile              |   2 +
- arch/arm/dts/mt7988-rfb.dts        | 182 +++++++++++++++++++++++++++++
- arch/arm/dts/mt7988-sd-rfb.dts     | 134 +++++++++++++++++++++
- board/mediatek/mt7988/MAINTAINERS  |   7 ++
- board/mediatek/mt7988/Makefile     |   3 +
- board/mediatek/mt7988/mt7988_rfb.c |  10 ++
- configs/mt7988_rfb_defconfig       |  83 +++++++++++++
- configs/mt7988_sd_rfb_defconfig    |  71 +++++++++++
- include/configs/mt7988.h           |  14 +++
- 9 files changed, 506 insertions(+)
- create mode 100644 arch/arm/dts/mt7988-rfb.dts
- create mode 100644 arch/arm/dts/mt7988-sd-rfb.dts
- create mode 100644 board/mediatek/mt7988/MAINTAINERS
- create mode 100644 board/mediatek/mt7988/Makefile
- create mode 100644 board/mediatek/mt7988/mt7988_rfb.c
- create mode 100644 configs/mt7988_rfb_defconfig
- create mode 100644 configs/mt7988_sd_rfb_defconfig
- create mode 100644 include/configs/mt7988.h
-
---- a/arch/arm/dts/Makefile
-+++ b/arch/arm/dts/Makefile
-@@ -1319,6 +1319,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
- 	mt7986b-sd-rfb.dtb \
- 	mt7986a-emmc-rfb.dtb \
- 	mt7986b-emmc-rfb.dtb \
-+	mt7988-rfb.dtb \
-+	mt7988-sd-rfb.dtb \
- 	mt8183-pumpkin.dtb \
- 	mt8512-bm1-emmc.dtb \
- 	mt8516-pumpkin.dtb \
---- /dev/null
-+++ b/arch/arm/dts/mt7988-rfb.dts
-@@ -0,0 +1,182 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2022 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ */
-+
-+/dts-v1/;
-+#include "mt7988.dtsi"
-+#include <dt-bindings/gpio/gpio.h>
-+
-+/ {
-+	model = "mt7988-rfb";
-+	compatible = "mediatek,mt7988-rfb";
-+
-+	chosen {
-+		stdout-path = &uart0;
-+	};
-+
-+	memory@40000000 {
-+		device_type = "memory";
-+		reg = <0 0x40000000 0 0x10000000>;
-+	};
-+
-+	reg_3p3v: regulator-3p3v {
-+		compatible = "regulator-fixed";
-+		regulator-name = "fixed-3.3V";
-+		regulator-min-microvolt = <3300000>;
-+		regulator-max-microvolt = <3300000>;
-+		regulator-boot-on;
-+		regulator-always-on;
-+	};
-+
-+	reg_1p8v: regulator-1p8v {
-+		compatible = "regulator-fixed";
-+		regulator-name = "fixed-1.8V";
-+		regulator-min-microvolt = <1800000>;
-+		regulator-max-microvolt = <1800000>;
-+		regulator-boot-on;
-+		regulator-always-on;
-+	};
-+};
-+
-+&uart0 {
-+	status = "okay";
-+};
-+
-+&i2c1 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&i2c1_pins>;
-+	status = "okay";
-+};
-+
-+&eth {
-+	status = "okay";
-+	mediatek,gmac-id = <0>;
-+	phy-mode = "usxgmii";
-+	mediatek,switch = "mt7988";
-+
-+	fixed-link {
-+		speed = <1000>;
-+		full-duplex;
-+		pause;
-+	};
-+};
-+
-+&pinctrl {
-+	i2c1_pins: i2c1-pins {
-+		mux {
-+			function = "i2c";
-+			groups = "i2c1_0";
-+		};
-+	};
-+
-+	pwm_pins: pwm-pins {
-+		mux {
-+			function = "pwm";
-+			groups = "pwm0", "pwm1", "pwm2", "pwm3", "pwm4",
-+				 "pwm5", "pwm6", "pwm7";
-+		};
-+	};
-+
-+	spi0_pins: spi0-pins {
-+		mux {
-+			function = "spi";
-+			groups = "spi0", "spi0_wp_hold";
-+		};
-+	};
-+
-+	spi2_pins: spi2-pins {
-+		mux {
-+			function = "spi";
-+			groups = "spi2", "spi2_wp_hold";
-+		};
-+	};
-+
-+	mmc0_pins_default: mmc0default {
-+		mux {
-+			function = "flash";
-+			groups =  "emmc_51";
-+		};
-+
-+		conf-cmd-dat {
-+			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
-+			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
-+			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
-+			input-enable;
-+		};
-+
-+		conf-clk {
-+			pins = "EMMC_CK";
-+		};
-+
-+		conf-dsl {
-+			pins = "EMMC_DSL";
-+		};
-+
-+		conf-rst {
-+			pins = "EMMC_RSTB";
-+		};
-+	};
-+};
-+
-+&pwm {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&pwm_pins>;
-+	status = "okay";
-+};
-+
-+&spi0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&spi0_pins>;
-+	#address-cells = <1>;
-+	#size-cells = <0>;
-+	status = "okay";
-+	must_tx;
-+	enhance_timing;
-+	dma_ext;
-+	ipm_design;
-+	support_quad;
-+	tick_dly = <2>;
-+	sample_sel = <0>;
-+
-+	spi_nand@0 {
-+		compatible = "spi-nand";
-+		reg = <0>;
-+		spi-max-frequency = <52000000>;
-+	};
-+};
-+
-+&spi2 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&spi2_pins>;
-+	#address-cells = <1>;
-+	#size-cells = <0>;
-+	status = "okay";
-+	must_tx;
-+	enhance_timing;
-+	dma_ext;
-+	ipm_design;
-+	support_quad;
-+	tick_dly = <2>;
-+	sample_sel = <0>;
-+
-+	spi_nor@0 {
-+		compatible = "jedec,spi-nor";
-+		reg = <0>;
-+		spi-max-frequency = <52000000>;
-+	};
-+};
-+
-+&mmc0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&mmc0_pins_default>;
-+	max-frequency = <52000000>;
-+	bus-width = <8>;
-+	cap-mmc-highspeed;
-+	cap-mmc-hw-reset;
-+	vmmc-supply = <&reg_3p3v>;
-+	vqmmc-supply = <&reg_1p8v>;
-+	non-removable;
-+	status = "okay";
-+};
---- /dev/null
-+++ b/arch/arm/dts/mt7988-sd-rfb.dts
-@@ -0,0 +1,134 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2022 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ */
-+
-+/dts-v1/;
-+#include "mt7988.dtsi"
-+#include <dt-bindings/gpio/gpio.h>
-+
-+/ {
-+	model = "mt7988-rfb";
-+	compatible = "mediatek,mt7988-rfb", "mediatek,mt7988-sd-rfb";
-+
-+	chosen {
-+		stdout-path = &uart0;
-+	};
-+
-+	memory@40000000 {
-+		device_type = "memory";
-+		reg = <0 0x40000000 0 0x10000000>;
-+	};
-+
-+	reg_3p3v: regulator-3p3v {
-+		compatible = "regulator-fixed";
-+		regulator-name = "fixed-3.3V";
-+		regulator-min-microvolt = <3300000>;
-+		regulator-max-microvolt = <3300000>;
-+		regulator-boot-on;
-+		regulator-always-on;
-+	};
-+};
-+
-+&uart0 {
-+	status = "okay";
-+};
-+
-+&i2c1 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&i2c1_pins>;
-+	status = "okay";
-+};
-+
-+&eth {
-+	status = "okay";
-+	mediatek,gmac-id = <0>;
-+	phy-mode = "usxgmii";
-+	mediatek,switch = "mt7988";
-+
-+	fixed-link {
-+		speed = <1000>;
-+		full-duplex;
-+		pause;
-+	};
-+};
-+
-+&pinctrl {
-+	i2c1_pins: i2c1-pins {
-+		mux {
-+			function = "i2c";
-+			groups = "i2c1_0";
-+		};
-+	};
-+
-+	pwm_pins: pwm-pins {
-+		mux {
-+			function = "pwm";
-+			groups = "pwm0", "pwm1", "pwm2", "pwm3", "pwm4",
-+				 "pwm5", "pwm6", "pwm7";
-+		};
-+	};
-+
-+	spi0_pins: spi0-pins {
-+		mux {
-+			function = "spi";
-+			groups = "spi0", "spi0_wp_hold";
-+		};
-+	};
-+
-+	mmc1_pins_default: mmc1default {
-+		mux {
-+			function = "flash";
-+			groups =  "emmc_45";
-+		};
-+
-+		conf-cmd-dat {
-+			pins = "SPI2_CSB", "SPI2_MISO", "SPI2_MOSI",
-+			       "SPI2_CLK", "SPI2_HOLD";
-+			input-enable;
-+		};
-+
-+		conf-clk {
-+			pins = "SPI2_WP";
-+		};
-+	};
-+};
-+
-+&pwm {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&pwm_pins>;
-+	status = "okay";
-+};
-+
-+&spi0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&spi0_pins>;
-+	#address-cells = <1>;
-+	#size-cells = <0>;
-+	status = "okay";
-+	must_tx;
-+	enhance_timing;
-+	dma_ext;
-+	ipm_design;
-+	support_quad;
-+	tick_dly = <2>;
-+	sample_sel = <0>;
-+
-+	spi_nand@0 {
-+		compatible = "spi-nand";
-+		reg = <0>;
-+		spi-max-frequency = <52000000>;
-+	};
-+};
-+
-+&mmc0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&mmc1_pins_default>;
-+	max-frequency = <52000000>;
-+	bus-width = <4>;
-+	cap-sd-highspeed;
-+	vmmc-supply = <&reg_3p3v>;
-+	vqmmc-supply = <&reg_3p3v>;
-+	status = "okay";
-+};
---- /dev/null
-+++ b/board/mediatek/mt7988/MAINTAINERS
-@@ -0,0 +1,7 @@
-+MT7988
-+M:	Sam Shih <sam.shih@mediatek.com>
-+S:	Maintained
-+F:	board/mediatek/mt7988
-+F:	include/configs/mt7988.h
-+F:	configs/mt7988_rfb_defconfig
-+F:	configs/mt7988_sd_rfb_defconfig
---- /dev/null
-+++ b/board/mediatek/mt7988/Makefile
-@@ -0,0 +1,3 @@
-+# SPDX-License-Identifier:	GPL-2.0
-+
-+obj-y	+= mt7988_rfb.o
---- /dev/null
-+++ b/board/mediatek/mt7988/mt7988_rfb.c
-@@ -0,0 +1,10 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (C) 2022 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ */
-+
-+int board_init(void)
-+{
-+	return 0;
-+}
---- /dev/null
-+++ b/configs/mt7988_rfb_defconfig
-@@ -0,0 +1,83 @@
-+CONFIG_ARM=y
-+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
-+CONFIG_POSITION_INDEPENDENT=y
-+CONFIG_ARCH_MEDIATEK=y
-+CONFIG_TEXT_BASE=0x41e00000
-+CONFIG_SYS_MALLOC_F_LEN=0x4000
-+CONFIG_NR_DRAM_BANKS=1
-+CONFIG_DEFAULT_DEVICE_TREE="mt7988-rfb"
-+CONFIG_SYS_PROMPT="MT7988> "
-+CONFIG_TARGET_MT7988=y
-+CONFIG_DEBUG_UART_BASE=0x11000000
-+CONFIG_DEBUG_UART_CLOCK=40000000
-+CONFIG_SYS_LOAD_ADDR=0x50000000
-+CONFIG_DEBUG_UART=y
-+# CONFIG_AUTOBOOT is not set
-+CONFIG_DEFAULT_FDT_FILE="mt7988-rfb"
-+CONFIG_LOGLEVEL=7
-+CONFIG_LOG=y
-+CONFIG_SYS_CBSIZE=512
-+CONFIG_SYS_PBSIZE=1049
-+# CONFIG_BOOTM_NETBSD is not set
-+# CONFIG_BOOTM_PLAN9 is not set
-+# CONFIG_BOOTM_RTEMS is not set
-+# CONFIG_BOOTM_VXWORKS is not set
-+# CONFIG_CMD_ELF is not set
-+CONFIG_CMD_CLK=y
-+CONFIG_CMD_DM=y
-+CONFIG_CMD_GPIO=y
-+CONFIG_CMD_PWM=y
-+CONFIG_CMD_MMC=y
-+CONFIG_CMD_MTD=y
-+CONFIG_CMD_PING=y
-+CONFIG_CMD_SMC=y
-+CONFIG_DOS_PARTITION=y
-+CONFIG_EFI_PARTITION=y
-+CONFIG_PARTITION_TYPE_GUID=y
-+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-+CONFIG_NET_RANDOM_ETHADDR=y
-+CONFIG_USE_IPADDR=y
-+CONFIG_IPADDR="192.168.1.1"
-+CONFIG_USE_NETMASK=y
-+CONFIG_NETMASK="255.255.255.0"
-+CONFIG_USE_SERVERIP=y
-+CONFIG_SERVERIP="192.168.1.2"
-+CONFIG_PROT_TCP=y
-+CONFIG_REGMAP=y
-+CONFIG_SYSCON=y
-+CONFIG_CLK=y
-+CONFIG_MMC_HS200_SUPPORT=y
-+CONFIG_MMC_MTK=y
-+CONFIG_MTD=y
-+CONFIG_DM_MTD=y
-+CONFIG_MTD_SPI_NAND=y
-+CONFIG_DM_SPI_FLASH=y
-+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
-+CONFIG_SPI_FLASH_EON=y
-+CONFIG_SPI_FLASH_GIGADEVICE=y
-+CONFIG_SPI_FLASH_ISSI=y
-+CONFIG_SPI_FLASH_MACRONIX=y
-+CONFIG_SPI_FLASH_SPANSION=y
-+CONFIG_SPI_FLASH_STMICRO=y
-+CONFIG_SPI_FLASH_WINBOND=y
-+CONFIG_SPI_FLASH_XMC=y
-+CONFIG_SPI_FLASH_XTX=y
-+CONFIG_SPI_FLASH_MTD=y
-+CONFIG_PHY_FIXED=y
-+CONFIG_MEDIATEK_ETH=y
-+CONFIG_PINCTRL=y
-+CONFIG_PINCONF=y
-+CONFIG_PINCTRL_MT7988=y
-+CONFIG_POWER_DOMAIN=y
-+CONFIG_MTK_POWER_DOMAIN=y
-+CONFIG_DM_PWM=y
-+CONFIG_PWM_MTK=y
-+CONFIG_RAM=y
-+CONFIG_DM_SERIAL=y
-+CONFIG_MTK_SERIAL=y
-+CONFIG_SPI=y
-+CONFIG_DM_SPI=y
-+CONFIG_MTK_SPIM=y
-+CONFIG_LZO=y
-+CONFIG_HEXDUMP=y
-+# CONFIG_EFI_LOADER is not set
---- /dev/null
-+++ b/configs/mt7988_sd_rfb_defconfig
-@@ -0,0 +1,71 @@
-+CONFIG_ARM=y
-+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
-+CONFIG_POSITION_INDEPENDENT=y
-+CONFIG_ARCH_MEDIATEK=y
-+CONFIG_TEXT_BASE=0x41e00000
-+CONFIG_SYS_MALLOC_F_LEN=0x4000
-+CONFIG_NR_DRAM_BANKS=1
-+CONFIG_DEFAULT_DEVICE_TREE="mt7988-sd-rfb"
-+CONFIG_SYS_PROMPT="MT7988> "
-+CONFIG_TARGET_MT7988=y
-+CONFIG_DEBUG_UART_BASE=0x11000000
-+CONFIG_DEBUG_UART_CLOCK=40000000
-+CONFIG_SYS_LOAD_ADDR=0x50000000
-+CONFIG_DEBUG_UART=y
-+# CONFIG_AUTOBOOT is not set
-+CONFIG_DEFAULT_FDT_FILE="mt7988-sd-rfb"
-+CONFIG_LOGLEVEL=7
-+CONFIG_LOG=y
-+CONFIG_SYS_CBSIZE=512
-+CONFIG_SYS_PBSIZE=1049
-+# CONFIG_BOOTM_NETBSD is not set
-+# CONFIG_BOOTM_PLAN9 is not set
-+# CONFIG_BOOTM_RTEMS is not set
-+# CONFIG_BOOTM_VXWORKS is not set
-+# CONFIG_CMD_ELF is not set
-+CONFIG_CMD_CLK=y
-+CONFIG_CMD_DM=y
-+CONFIG_CMD_GPIO=y
-+CONFIG_CMD_PWM=y
-+CONFIG_CMD_MMC=y
-+CONFIG_CMD_MTD=y
-+CONFIG_CMD_PING=y
-+CONFIG_CMD_SMC=y
-+CONFIG_DOS_PARTITION=y
-+CONFIG_EFI_PARTITION=y
-+CONFIG_PARTITION_TYPE_GUID=y
-+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-+CONFIG_NET_RANDOM_ETHADDR=y
-+CONFIG_USE_IPADDR=y
-+CONFIG_IPADDR="192.168.1.1"
-+CONFIG_USE_NETMASK=y
-+CONFIG_NETMASK="255.255.255.0"
-+CONFIG_USE_SERVERIP=y
-+CONFIG_SERVERIP="192.168.1.2"
-+CONFIG_PROT_TCP=y
-+CONFIG_REGMAP=y
-+CONFIG_SYSCON=y
-+CONFIG_CLK=y
-+CONFIG_MMC_HS200_SUPPORT=y
-+CONFIG_MMC_MTK=y
-+CONFIG_MTD=y
-+CONFIG_DM_MTD=y
-+CONFIG_MTD_SPI_NAND=y
-+CONFIG_PHY_FIXED=y
-+CONFIG_MEDIATEK_ETH=y
-+CONFIG_PINCTRL=y
-+CONFIG_PINCONF=y
-+CONFIG_PINCTRL_MT7988=y
-+CONFIG_POWER_DOMAIN=y
-+CONFIG_MTK_POWER_DOMAIN=y
-+CONFIG_DM_PWM=y
-+CONFIG_PWM_MTK=y
-+CONFIG_RAM=y
-+CONFIG_DM_SERIAL=y
-+CONFIG_MTK_SERIAL=y
-+CONFIG_SPI=y
-+CONFIG_DM_SPI=y
-+CONFIG_MTK_SPIM=y
-+CONFIG_LZO=y
-+CONFIG_HEXDUMP=y
-+# CONFIG_EFI_LOADER is not set
---- /dev/null
-+++ b/include/configs/mt7988.h
-@@ -0,0 +1,14 @@
-+/* SPDX-License-Identifier: GPL-2.0 */
-+/*
-+ * Configuration for MediaTek MT7988 SoC
-+ *
-+ * Copyright (C) 2022 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ */
-+
-+#ifndef __MT7988_H
-+#define __MT7988_H
-+
-+#define CFG_MAX_MEM_MAPPED		0xC0000000
-+
-+#endif
diff --git a/package/boot/uboot-mediatek/patches/102-ram-mediatek-include-linux-sizes.h-for-SZ_-macros.patch b/package/boot/uboot-mediatek/patches/102-ram-mediatek-include-linux-sizes.h-for-SZ_-macros.patch
deleted file mode 100644
index 3cfc6849563092..00000000000000
--- a/package/boot/uboot-mediatek/patches/102-ram-mediatek-include-linux-sizes.h-for-SZ_-macros.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From 4bd66fd5b69eda41b4320fd6f8db50a7b7fa7bf7 Mon Sep 17 00:00:00 2001
-Message-ID: <4bd66fd5b69eda41b4320fd6f8db50a7b7fa7bf7.1690828424.git.daniel@makrotopia.org>
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Mon, 31 Jul 2023 19:25:04 +0100
-Subject: [PATCH] ram: mediatek: include <linux/sizes.h> for SZ_* macros
-To: Ryder Lee <ryder.lee@mediatek.com>,
-    Weijie Gao <weijie.gao@mediatek.com>,
-    Chunfeng Yun <chunfeng.yun@mediatek.com>,
-    GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>,
-    u-boot@lists.denx.de
-
-Something between U-Boot 2023.04 and 2023.07.02 resulted in no longer
-implicitely including <linux/sizes.h> in the DDR3 RAM driver for the
-MT7929 SoC. The result is a build failure:
-drivers/ram/mediatek/ddr3-mt7629.c: In function 'mtk_ddr3_get_info':
-drivers/ram/mediatek/ddr3-mt7629.c:734:30: error: 'SZ_128M' undeclared (first use in this function)
-  734 |                 info->size = SZ_128M;
-      |                              ^~~~~~~
-drivers/ram/mediatek/ddr3-mt7629.c:734:30: note: each undeclared identifier is reported only once for each function it appears in
-drivers/ram/mediatek/ddr3-mt7629.c:737:30: error: 'SZ_256M' undeclared (first use in this function)
-  737 |                 info->size = SZ_256M;
-      |                              ^~~~~~~
-drivers/ram/mediatek/ddr3-mt7629.c:740:30: error: 'SZ_512M' undeclared (first use in this function)
-  740 |                 info->size = SZ_512M;
-      |                              ^~~~~~~
-drivers/ram/mediatek/ddr3-mt7629.c:743:30: error: 'SZ_1G' undeclared (first use in this function)
-  743 |                 info->size = SZ_1G;
-      |                              ^~~~~
-
-Include <linux/sizes.h> so SZ_* is defined.
-
-Reported-by: Tianling Shen <cnsztl@immortalwrt.org>
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/ram/mediatek/ddr3-mt7629.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/ram/mediatek/ddr3-mt7629.c
-+++ b/drivers/ram/mediatek/ddr3-mt7629.c
-@@ -14,6 +14,7 @@
- #include <asm/io.h>
- #include <linux/bitops.h>
- #include <linux/delay.h>
-+#include <linux/sizes.h>
- 
- /* EMI */
- #define EMI_CONA			0x000
diff --git a/package/boot/uboot-mediatek/patches/103-mt7988-enable-pstore.patch b/package/boot/uboot-mediatek/patches/103-mt7988-enable-pstore.patch
index a34dcddd71bc79..747aa2e5daccc6 100644
--- a/package/boot/uboot-mediatek/patches/103-mt7988-enable-pstore.patch
+++ b/package/boot/uboot-mediatek/patches/103-mt7988-enable-pstore.patch
@@ -1,6 +1,6 @@
 --- a/arch/arm/dts/mt7988.dtsi
 +++ b/arch/arm/dts/mt7988.dtsi
-@@ -61,6 +61,30 @@
+@@ -62,6 +62,30 @@
  		#clock-cells = <0>;
  	};
  
diff --git a/package/boot/uboot-mediatek/patches/104-configs-set-CONFIG_LMB_MAX_REGIONS-64-for-MT7988-boards.patch b/package/boot/uboot-mediatek/patches/104-configs-set-CONFIG_LMB_MAX_REGIONS-64-for-MT7988-boards.patch
deleted file mode 100644
index f0475188524c84..00000000000000
--- a/package/boot/uboot-mediatek/patches/104-configs-set-CONFIG_LMB_MAX_REGIONS-64-for-MT7988-boards.patch
+++ /dev/null
@@ -1,69 +0,0 @@
-From patchwork Mon Aug 21 19:38:23 2023
-Content-Type: text/plain; charset="utf-8"
-MIME-Version: 1.0
-Content-Transfer-Encoding: 7bit
-X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
-X-Patchwork-Id: 1823742
-X-Patchwork-Delegate: trini@ti.com
-Return-Path: <u-boot-bounces@lists.denx.de>
-X-Original-To: incoming@patchwork.ozlabs.org
-Delivered-To: patchwork-incoming@legolas.ozlabs.org
-Date: Mon, 21 Aug 2023 20:38:23 +0100
-From: Daniel Golle <daniel@makrotopia.org>
-To: Sam Shih <sam.shih@mediatek.com>, Weijie Gao <weijie.gao@mediatek.com>,
- Lorenzo Bianconi <lorenzo@kernel.org>, u-boot@lists.denx.de
-Subject: [PATCH] configs: set CONFIG_LMB_MAX_REGIONS=64 for MT7988 boards
-Message-ID: 
- <568a8030acf9056266b5c96055cea54f810496c9.1692646620.git.daniel@makrotopia.org>
-MIME-Version: 1.0
-Content-Disposition: inline
-X-BeenThere: u-boot@lists.denx.de
-X-Mailman-Version: 2.1.39
-Precedence: list
-List-Id: U-Boot discussion <u-boot.lists.denx.de>
-List-Unsubscribe: <https://lists.denx.de/options/u-boot>,
- <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>
-List-Archive: <https://lists.denx.de/pipermail/u-boot/>
-List-Post: <mailto:u-boot@lists.denx.de>
-List-Help: <mailto:u-boot-request@lists.denx.de?subject=help>
-List-Subscribe: <https://lists.denx.de/listinfo/u-boot>,
- <mailto:u-boot-request@lists.denx.de?subject=subscribe>
-Errors-To: u-boot-bounces@lists.denx.de
-Sender: "U-Boot" <u-boot-bounces@lists.denx.de>
-
-Similar to MT7981 and MT7986 also MT7988 can have a high number of
-reserved-memory regions used by the various hardware offloading
-subsystems.
-
-Raise CONFIG_LMB_MAX_REGIONS to 64 to avoid errors when trying to boot
-Linux with more then 6 reserved regions:
-
-ERROR: reserving fdt memory region failed (addr=4f700000 size=240000 flags=4)
-ERROR: reserving fdt memory region failed (addr=15194000 size=1000 flags=4)
-ERROR: reserving fdt memory region failed (addr=15294000 size=1000 flags=4)
-ERROR: reserving fdt memory region failed (addr=15394000 size=1000 flags=4)
-ERROR: Failed to allocate 0xb161 bytes below 0x80000000.
-device tree - allocation error
-
-Fixes: bc4adc97cfb ("board: mediatek: add MT7988 reference boards")
-Reported-by: Lorenzo Bianconi <lorenzo@kernel.org>
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- configs/mt7988_rfb_defconfig    | 1 +
- configs/mt7988_sd_rfb_defconfig | 1 +
- 2 files changed, 2 insertions(+)
-
---- a/configs/mt7988_rfb_defconfig
-+++ b/configs/mt7988_rfb_defconfig
-@@ -81,3 +81,4 @@ CONFIG_MTK_SPIM=y
- CONFIG_LZO=y
- CONFIG_HEXDUMP=y
- # CONFIG_EFI_LOADER is not set
-+CONFIG_LMB_MAX_REGIONS=64
---- a/configs/mt7988_sd_rfb_defconfig
-+++ b/configs/mt7988_sd_rfb_defconfig
-@@ -69,3 +69,4 @@ CONFIG_MTK_SPIM=y
- CONFIG_LZO=y
- CONFIG_HEXDUMP=y
- # CONFIG_EFI_LOADER is not set
-+CONFIG_LMB_MAX_REGIONS=64
diff --git a/package/boot/uboot-mediatek/patches/105-configs-add-usefull-stuff-to-mt7988-rfb.patch b/package/boot/uboot-mediatek/patches/105-configs-add-usefull-stuff-to-mt7988-rfb.patch
index c7dcf9a1ba7d98..da1d985688b981 100644
--- a/package/boot/uboot-mediatek/patches/105-configs-add-usefull-stuff-to-mt7988-rfb.patch
+++ b/package/boot/uboot-mediatek/patches/105-configs-add-usefull-stuff-to-mt7988-rfb.patch
@@ -1,8 +1,8 @@
 --- a/configs/mt7988_sd_rfb_defconfig
 +++ b/configs/mt7988_sd_rfb_defconfig
-@@ -12,6 +12,24 @@ CONFIG_DEBUG_UART_BASE=0x11000000
+@@ -11,6 +11,24 @@ CONFIG_DEBUG_UART_BASE=0x11000000
  CONFIG_DEBUG_UART_CLOCK=40000000
- CONFIG_SYS_LOAD_ADDR=0x50000000
+ CONFIG_SYS_LOAD_ADDR=0x46000000
  CONFIG_DEBUG_UART=y
 +CONFIG_OF_LIBFDT_OVERLAY=y
 +CONFIG_SMBIOS_PRODUCT_NAME=""
@@ -157,9 +157,9 @@
  CONFIG_MTD=y
 --- a/configs/mt7988_rfb_defconfig
 +++ b/configs/mt7988_rfb_defconfig
-@@ -12,6 +12,24 @@ CONFIG_DEBUG_UART_BASE=0x11000000
+@@ -11,6 +11,24 @@ CONFIG_DEBUG_UART_BASE=0x11000000
  CONFIG_DEBUG_UART_CLOCK=40000000
- CONFIG_SYS_LOAD_ADDR=0x50000000
+ CONFIG_SYS_LOAD_ADDR=0x46000000
  CONFIG_DEBUG_UART=y
 +CONFIG_OF_LIBFDT_OVERLAY=y
 +CONFIG_SMBIOS_PRODUCT_NAME=""
diff --git a/package/boot/uboot-mediatek/patches/107-configs-add-useful-options-to-mt7981-rfb.patch b/package/boot/uboot-mediatek/patches/107-configs-add-useful-options-to-mt7981-rfb.patch
index f5234ea0859d23..bd4c6b55f03c7d 100644
--- a/package/boot/uboot-mediatek/patches/107-configs-add-useful-options-to-mt7981-rfb.patch
+++ b/package/boot/uboot-mediatek/patches/107-configs-add-useful-options-to-mt7981-rfb.patch
@@ -1,6 +1,6 @@
 --- a/configs/mt7981_emmc_rfb_defconfig
 +++ b/configs/mt7981_emmc_rfb_defconfig
-@@ -14,7 +14,22 @@ CONFIG_DEBUG_UART_BASE=0x11002000
+@@ -13,7 +13,22 @@ CONFIG_DEBUG_UART_BASE=0x11002000
  CONFIG_DEBUG_UART_CLOCK=40000000
  CONFIG_SYS_LOAD_ADDR=0x46000000
  CONFIG_DEBUG_UART=y
@@ -87,7 +87,7 @@
  CONFIG_CLK=y
 --- a/configs/mt7981_rfb_defconfig
 +++ b/configs/mt7981_rfb_defconfig
-@@ -12,7 +12,23 @@ CONFIG_DEBUG_UART_BASE=0x11002000
+@@ -11,7 +11,23 @@ CONFIG_DEBUG_UART_BASE=0x11002000
  CONFIG_DEBUG_UART_CLOCK=40000000
  CONFIG_SYS_LOAD_ADDR=0x46000000
  CONFIG_DEBUG_UART=y
@@ -191,7 +191,7 @@
  CONFIG_MTD_SPI_NAND=y
 --- a/configs/mt7981_sd_rfb_defconfig
 +++ b/configs/mt7981_sd_rfb_defconfig
-@@ -14,7 +14,22 @@ CONFIG_DEBUG_UART_BASE=0x11002000
+@@ -13,7 +13,22 @@ CONFIG_DEBUG_UART_BASE=0x11002000
  CONFIG_DEBUG_UART_CLOCK=40000000
  CONFIG_SYS_LOAD_ADDR=0x46000000
  CONFIG_DEBUG_UART=y
diff --git a/package/boot/uboot-mediatek/patches/110-no-kwbimage.patch b/package/boot/uboot-mediatek/patches/110-no-kwbimage.patch
index 2d61d6f4a7ecb3..3bf033f8143243 100644
--- a/package/boot/uboot-mediatek/patches/110-no-kwbimage.patch
+++ b/package/boot/uboot-mediatek/patches/110-no-kwbimage.patch
@@ -5,6 +5,6 @@
  			imx8image.o \
  			imx8mimage.o \
 -			kwbimage.o \
- 			lib/md5.o \
+ 			generated/lib/md5.o \
  			lpc32xximage.o \
  			mxsimage.o \
diff --git a/package/boot/uboot-mediatek/patches/120-use-xz-instead-of-lzma.patch b/package/boot/uboot-mediatek/patches/120-use-xz-instead-of-lzma.patch
index 411f99467b74d0..9a9224963d49ea 100644
--- a/package/boot/uboot-mediatek/patches/120-use-xz-instead-of-lzma.patch
+++ b/package/boot/uboot-mediatek/patches/120-use-xz-instead-of-lzma.patch
@@ -1,6 +1,6 @@
 --- a/Makefile
 +++ b/Makefile
-@@ -1070,7 +1070,7 @@ quiet_cmd_pad_cat = CAT     $@
+@@ -1083,7 +1083,7 @@ quiet_cmd_pad_cat = CAT     $@
  cmd_pad_cat = $(cmd_objcopy) && $(append) || { rm -f $@; false; }
  
  quiet_cmd_lzma = LZMA    $@
diff --git a/package/boot/uboot-mediatek/patches/130-fix-mkimage-host-build.patch b/package/boot/uboot-mediatek/patches/130-fix-mkimage-host-build.patch
index cd65c1321fc320..86a424e8b769d3 100644
--- a/package/boot/uboot-mediatek/patches/130-fix-mkimage-host-build.patch
+++ b/package/boot/uboot-mediatek/patches/130-fix-mkimage-host-build.patch
@@ -1,6 +1,6 @@
 --- a/tools/image-host.c
 +++ b/tools/image-host.c
-@@ -1125,6 +1125,7 @@ static int fit_config_add_verification_d
+@@ -1137,6 +1137,7 @@ static int fit_config_add_verification_d
   * 2) get public key (X509_get_pubkey)
   * 3) provide der format (d2i_RSAPublicKey)
   */
@@ -8,7 +8,7 @@
  static int read_pub_key(const char *keydir, const void *name,
  			unsigned char **pubkey, int *pubkey_len)
  {
-@@ -1178,6 +1179,13 @@ err_cert:
+@@ -1190,6 +1191,13 @@ err_cert:
  	fclose(f);
  	return ret;
  }
diff --git a/package/boot/uboot-mediatek/patches/131-spi-mtk_spim-prevent-global-pll-clock-override.patch b/package/boot/uboot-mediatek/patches/131-spi-mtk_spim-prevent-global-pll-clock-override.patch
deleted file mode 100644
index c4e0fff921f453..00000000000000
--- a/package/boot/uboot-mediatek/patches/131-spi-mtk_spim-prevent-global-pll-clock-override.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From 41f225dae30ea6ddcff10f120a9e732f994d3a07 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Nicol=C3=B2=20Veronese?= <nicveronese@gmail.com>
-Date: Tue, 3 Oct 2023 23:46:52 +0200
-Subject: [PATCH] spi: mtk_spim: prevent global pll clock override
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-With commit 793e6230118032a099ec42a1ea67f434721edcc0
- a new system to calculate the SPI clocks has been added.
-
-Unfortunately, the do_div macro overrides the global
- priv->pll_clk_rate field. This will cause to have a reduced
- clock rate on each subsequent SPI call.
-
-Signed-off-by: Valerio 'ftp21' Mancini <ftp21@ftp21.eu>
-Signed-off-by: Nicolò Veronese <nicveronese@gmail.com>
----
- drivers/spi/mtk_spim.c | 7 ++++---
- 1 file changed, 4 insertions(+), 3 deletions(-)
-
---- a/drivers/spi/mtk_spim.c
-+++ b/drivers/spi/mtk_spim.c
-@@ -409,7 +409,7 @@ static int mtk_spim_transfer_wait(struct
- {
- 	struct udevice *bus = dev_get_parent(slave->dev);
- 	struct mtk_spim_priv *priv = dev_get_priv(bus);
--	u32 sck_l, sck_h, clk_count, reg;
-+	u32 pll_clk, sck_l, sck_h, clk_count, reg;
- 	ulong us = 1;
- 	int ret = 0;
- 
-@@ -418,11 +418,12 @@ static int mtk_spim_transfer_wait(struct
- 	else
- 		clk_count = op->data.nbytes;
- 
-+	pll_clk = priv->pll_clk_rate;
- 	sck_l = readl(priv->base + SPI_CFG2_REG) >> SPI_CFG2_SCK_LOW_OFFSET;
- 	sck_h = readl(priv->base + SPI_CFG2_REG) & SPI_CFG2_SCK_HIGH_MASK;
--	do_div(priv->pll_clk_rate, sck_l + sck_h + 2);
-+	do_div(pll_clk, sck_l + sck_h + 2);
- 
--	us = CLK_TO_US(priv->pll_clk_rate, clk_count * 8);
-+	us = CLK_TO_US(pll_clk, clk_count * 8);
- 	us += 1000 * 1000; /* 1s tolerance */
- 
- 	if (us > UINT_MAX)
diff --git a/package/boot/uboot-mediatek/patches/160-net-phy-add-support-for-Airoha-ethernet-PHY-driver.patch b/package/boot/uboot-mediatek/patches/160-net-phy-add-support-for-Airoha-ethernet-PHY-driver.patch
new file mode 100644
index 00000000000000..f8e86599527825
--- /dev/null
+++ b/package/boot/uboot-mediatek/patches/160-net-phy-add-support-for-Airoha-ethernet-PHY-driver.patch
@@ -0,0 +1,1929 @@
+From 70157a6148ad47734f1dc646b4157ca83cc5df9f Mon Sep 17 00:00:00 2001
+From: Weijie Gao <weijie.gao@mediatek.com>
+Date: Thu, 13 Jul 2023 16:34:48 +0800
+Subject: [PATCH] net: phy: add support for Airoha ethernet PHY driver
+
+This patch adds support for Airoha ethernet PHY driver.
+
+If GMAC2 of your board connects to Airoha EN8801S, please change the eth
+node as follow:
+
+&eth {
+        status = "okay";
+        mediatek,gmac-id = <1>;
+        mediatek,sgmiisys = <&sgmiisys1>;
+        phy-mode = "sgmii";
+        phy-handle = <&phy5>;
+
+        phy5: eth-phy@5 {
+                reg = <24>;
+        };
+};
+
+If GMAC2 of your board connects to Airoha EN8811H, please change the eth
+node as follow:
+
+&eth {
+        status = "okay";
+        mediatek,gmac-id = <1>;
+        mediatek,sgmiisys = <&sgmiisys1>;
+        phy-mode = "2500base-x";
+        phy-handle = <&phy5>;
+
+        fixed-link {
+                speed = <2500>;
+                full-duplex;
+        };
+
+        phy5: eth-phy@5 {
+                reg = <15>;
+        };
+};
+
+Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+---
+ .../drivers/net/phy/Kconfig                   |   15 +
+ .../drivers/net/phy/Makefile                  |    2 +
+ .../drivers/net/phy/air_en8801s.c             |  633 ++
+ .../drivers/net/phy/air_en8801s.h             |  267 +
+ .../drivers/net/phy/air_en8811h.c             |  649 ++
+ .../drivers/net/phy/air_en8811h.h             |  160 +
+ .../drivers/net/phy/air_en8811h_fw.h          | 9227 +++++++++++++++++
+ 7 files changed, 10953 insertions(+)
+ create mode 100644 drivers/net/phy/air_en8801s.c
+ create mode 100644 drivers/net/phy/air_en8801s.h
+ create mode 100644 drivers/net/phy/air_en8811h.c
+ create mode 100644 drivers/net/phy/air_en8811h.h
+ create mode 100644 drivers/net/phy/air_en8811h_fw.h
+
+--- a/drivers/net/phy/Kconfig
++++ b/drivers/net/phy/Kconfig
+@@ -77,6 +77,37 @@ config PHY_ADIN
+ 	help
+ 		Add support for configuring RGMII on Analog Devices ADIN PHYs.
+ 
++menuconfig PHY_AIROHA
++	bool "Airoha Ethernet PHYs support"
++
++config PHY_AIROHA_EN8801S
++	bool "Airoha Ethernet EN8801S support"
++	depends on PHY_AIROHA
++	help
++		AIROHA EN8801S supported.
++
++config PHY_AIROHA_EN8811H
++	bool "Airoha Ethernet EN8811H support"
++	depends on PHY_AIROHA
++	help
++		AIROHA EN8811H supported.
++
++choice
++	prompt "Location of the Airoha PHY firmware"
++	default PHY_AIROHA_FW_IN_UBI
++	depends on PHY_AIROHA_EN8811H
++
++config PHY_AIROHA_FW_IN_MMC
++	bool "Airoha firmware in MMC boot1 partition"
++
++config PHY_AIROHA_FW_IN_UBI
++	bool "Airoha firmware in UBI volume en8811h-fw on NAND flash"
++
++config PHY_AIROHA_FW_IN_MTD
++	bool "Airoha firmware in MTD partition on raw flash"
++
++endchoice
++
+ menuconfig PHY_AQUANTIA
+ 	bool "Aquantia Ethernet PHYs support"
+ 	select PHY_GIGE
+--- a/drivers/net/phy/Makefile
++++ b/drivers/net/phy/Makefile
+@@ -11,6 +11,8 @@ obj-$(CONFIG_MV88E6352_SWITCH) += mv88e6
+ obj-$(CONFIG_PHYLIB) += phy.o
+ obj-$(CONFIG_PHYLIB_10G) += generic_10g.o
+ obj-$(CONFIG_PHY_ADIN) += adin.o
++obj-$(CONFIG_PHY_AIROHA_EN8801S) += air_en8801s.o
++obj-$(CONFIG_PHY_AIROHA_EN8811H) += air_en8811h.o
+ obj-$(CONFIG_PHY_AQUANTIA) += aquantia.o
+ obj-$(CONFIG_PHY_ATHEROS) += atheros.o
+ obj-$(CONFIG_PHY_BROADCOM) += broadcom.o
+--- /dev/null
++++ b/drivers/net/phy/air_en8801s.c
+@@ -0,0 +1,633 @@
++// SPDX-License-Identifier: GPL-2.0
++/*************************************************
++ * FILE NAME:  air_en8801s.c
++ * PURPOSE:
++ *      EN8801S PHY Driver for Uboot
++ * NOTES:
++ *
++ *  Copyright (C) 2023 Airoha Technology Corp.
++ *************************************************/
++
++/* INCLUDE FILE DECLARATIONS
++ */
++#include <common.h>
++#include <phy.h>
++#include <errno.h>
++#include <version.h>
++#include "air_en8801s.h"
++
++#if AIR_UBOOT_REVISION > 0x202004
++#include <linux/delay.h>
++#endif
++
++static struct phy_device *s_phydev = 0;
++/******************************************************
++ * The following led_cfg example is for reference only.
++ * LED5 1000M/LINK/ACT   (GPIO5)  <-> BASE_T_LED0,
++ * LED6 10/100M/LINK/ACT (GPIO9)  <-> BASE_T_LED1,
++ * LED4 100M/LINK/ACT    (GPIO8)  <-> BASE_T_LED2,
++ ******************************************************/
++/* User-defined.B */
++#define AIR_LED_SUPPORT
++#ifdef AIR_LED_SUPPORT
++static const AIR_BASE_T_LED_CFG_T led_cfg[4] =
++{
++    /*
++     *    LED Enable,     GPIO,       LED Polarity,            LED ON,               LED Blink
++     */
++         {LED_ENABLE,       5,       AIR_ACTIVE_LOW,      BASE_T_LED0_ON_CFG,    BASE_T_LED0_BLK_CFG}, /* BASE-T LED0 */
++         {LED_ENABLE,       9,       AIR_ACTIVE_LOW,      BASE_T_LED1_ON_CFG,    BASE_T_LED1_BLK_CFG}, /* BASE-T LED1 */
++         {LED_ENABLE,       8,       AIR_ACTIVE_LOW,      BASE_T_LED2_ON_CFG,    BASE_T_LED2_BLK_CFG}, /* BASE-T LED2 */
++         {LED_DISABLE,      1,       AIR_ACTIVE_LOW,      BASE_T_LED3_ON_CFG,    BASE_T_LED3_BLK_CFG}  /* BASE-T LED3 */
++};
++static const u16 led_dur = UNIT_LED_BLINK_DURATION << AIR_LED_BLK_DUR_64M;
++#endif
++/* User-defined.E */
++/************************************************************************
++ *                  F U N C T I O N S
++ ************************************************************************/
++/* Airoha MII read function */
++static int airoha_cl22_read(struct mii_dev *bus, int phy_addr, int phy_register)
++{
++    int read_data = bus->read(bus, phy_addr, MDIO_DEVAD_NONE, phy_register);
++
++    if (read_data < 0)
++        return -EIO;
++    return read_data;
++}
++
++/* Airoha MII write function */
++static int airoha_cl22_write(struct mii_dev *bus, int phy_addr, int phy_register, int write_data)
++{
++    int ret = bus->write(bus, phy_addr, MDIO_DEVAD_NONE, phy_register, write_data);
++
++    return ret;
++}
++
++static int airoha_cl45_write(struct phy_device *phydev, int devad, int reg, int val)
++{
++    int ret = 0;
++
++    ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_ACC_CTL_REG, devad);
++    AIR_RTN_ERR(ret);
++    ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_ADDR_DATA_REG, reg);
++    AIR_RTN_ERR(ret);
++    ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_ACC_CTL_REG, MMD_OP_MODE_DATA | devad);
++    AIR_RTN_ERR(ret);
++    ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_ADDR_DATA_REG, val);
++    AIR_RTN_ERR(ret);
++    return ret;
++}
++
++static int airoha_cl45_read(struct phy_device *phydev, int devad, int reg)
++{
++    int read_data, ret;
++
++    ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_ACC_CTL_REG, devad);
++    AIR_RTN_ERR(ret);
++    ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_ADDR_DATA_REG, reg);
++    AIR_RTN_ERR(ret);
++    ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_ACC_CTL_REG, MMD_OP_MODE_DATA | devad);
++    AIR_RTN_ERR(ret);
++    read_data = phy_read(phydev, MDIO_DEVAD_NONE, MII_MMD_ADDR_DATA_REG);
++    if (read_data < 0)
++        return -EIO;
++    return read_data;
++}
++
++/* EN8801 PBUS write function */
++int airoha_pbus_write(struct mii_dev *bus, int pbus_addr, int pbus_reg, unsigned long pbus_data)
++{
++    int ret = 0;
++
++    ret = airoha_cl22_write(bus, pbus_addr, 0x1F, (pbus_reg >> 6));
++    AIR_RTN_ERR(ret);
++    ret = airoha_cl22_write(bus, pbus_addr, ((pbus_reg >> 2) & 0xf), (pbus_data & 0xFFFF));
++    AIR_RTN_ERR(ret);
++    ret = airoha_cl22_write(bus, pbus_addr, 0x10, (pbus_data >> 16));
++    AIR_RTN_ERR(ret);
++    return ret;
++}
++
++/* EN8801 PBUS read function */
++unsigned long airoha_pbus_read(struct mii_dev *bus, int pbus_addr, int pbus_reg)
++{
++    unsigned long pbus_data;
++    unsigned int pbus_data_low, pbus_data_high;
++
++    airoha_cl22_write(bus, pbus_addr, 0x1F, (pbus_reg >> 6));
++    pbus_data_low = airoha_cl22_read(bus, pbus_addr, ((pbus_reg >> 2) & 0xf));
++    pbus_data_high = airoha_cl22_read(bus, pbus_addr, 0x10);
++    pbus_data = (pbus_data_high << 16) + pbus_data_low;
++    return pbus_data;
++}
++
++/* Airoha Token Ring Write function */
++static int airoha_tr_reg_write(struct phy_device *phydev, unsigned long tr_address, unsigned long tr_data)
++{
++    int ret;
++
++    ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x1F, 0x52b5);       /* page select */
++    AIR_RTN_ERR(ret);
++    ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x11, (int)(tr_data & 0xffff));
++    AIR_RTN_ERR(ret);
++    ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x12, (int)(tr_data >> 16));
++    AIR_RTN_ERR(ret);
++    ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x10, (int)(tr_address | TrReg_WR));
++    AIR_RTN_ERR(ret);
++    ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x1F, 0x0);          /* page resetore */
++    AIR_RTN_ERR(ret);
++    return ret;
++}
++
++int airoha_phy_process(void)
++{
++    int ret = 0, pbus_addr = EN8801S_PBUS_PHY_ID;
++    unsigned long pbus_data;
++    struct mii_dev *mbus;
++
++    mbus = s_phydev->bus;
++    pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x19e0);
++    pbus_data |= BIT(0);
++    ret = airoha_pbus_write(mbus, pbus_addr, 0x19e0, pbus_data);
++    if(ret)
++        printf("error: airoha_pbus_write fail ret: %d\n", ret);
++    pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x19e0);
++    pbus_data &= ~BIT(0);
++    ret = airoha_pbus_write(mbus, pbus_addr, 0x19e0, pbus_data);
++    if(ret)
++        printf("error: airoha_pbus_write fail ret: %d\n", ret);
++
++    if(ret)
++        printf("error: FCM regs reset fail, ret: %d\n", ret);
++    else
++        debug("FCM regs reset successful\n");
++    return ret;
++}
++
++#ifdef  AIR_LED_SUPPORT
++static int airoha_led_set_usr_def(struct phy_device *phydev, u8 entity, int polar,
++                                   u16 on_evt, u16 blk_evt)
++{
++    int ret = 0;
++
++    if (AIR_ACTIVE_HIGH == polar) {
++        on_evt |= LED_ON_POL;
++    } else {
++        on_evt &= ~LED_ON_POL;
++    }
++    ret = airoha_cl45_write(phydev, 0x1f, LED_ON_CTRL(entity), on_evt | LED_ON_EN);
++    AIR_RTN_ERR(ret);
++    ret = airoha_cl45_write(phydev, 0x1f, LED_BLK_CTRL(entity), blk_evt);
++    AIR_RTN_ERR(ret);
++    return 0;
++}
++
++static int airoha_led_set_mode(struct phy_device *phydev, u8 mode)
++{
++    u16 cl45_data;
++    int err = 0;
++
++    cl45_data = airoha_cl45_read(phydev, 0x1f, LED_BCR);
++    switch (mode) {
++    case AIR_LED_MODE_DISABLE:
++        cl45_data &= ~LED_BCR_EXT_CTRL;
++        cl45_data &= ~LED_BCR_MODE_MASK;
++        cl45_data |= LED_BCR_MODE_DISABLE;
++        break;
++    case AIR_LED_MODE_USER_DEFINE:
++        cl45_data |= LED_BCR_EXT_CTRL;
++		cl45_data |= LED_BCR_CLK_EN;
++        break;
++    default:
++        printf("LED mode%d is not supported!\n", mode);
++        return -EINVAL;
++    }
++    err = airoha_cl45_write(phydev, 0x1f, LED_BCR, cl45_data);
++    AIR_RTN_ERR(err);
++    return 0;
++}
++
++static int airoha_led_set_state(struct phy_device *phydev, u8 entity, u8 state)
++{
++    u16 cl45_data;
++    int err;
++
++    cl45_data = airoha_cl45_read(phydev, 0x1f, LED_ON_CTRL(entity));
++    if (LED_ENABLE == state) {
++        cl45_data |= LED_ON_EN;
++    } else {
++        cl45_data &= ~LED_ON_EN;
++    }
++
++    err = airoha_cl45_write(phydev, 0x1f, LED_ON_CTRL(entity), cl45_data);
++    AIR_RTN_ERR(err);
++    return 0;
++}
++
++static int en8801s_led_init(struct phy_device *phydev)
++{
++
++    unsigned long led_gpio = 0, reg_value = 0;
++    int ret = 0, led_id;
++    struct mii_dev *mbus = phydev->bus;
++    int gpio_led_rg[3] = {0x1870, 0x1874, 0x1878};
++    u16 cl45_data = led_dur;
++
++    ret = airoha_cl45_write(phydev, 0x1f, LED_BLK_DUR, cl45_data);
++    AIR_RTN_ERR(ret);
++    cl45_data >>= 1;
++    ret = airoha_cl45_write(phydev, 0x1f, LED_ON_DUR, cl45_data);
++    AIR_RTN_ERR(ret);
++    ret = airoha_led_set_mode(phydev, AIR_LED_MODE_USER_DEFINE);
++    if (ret != 0) {
++        printf("LED fail to set mode, ret %d !\n", ret);
++        return ret;
++    }
++    for(led_id = 0; led_id < EN8801S_LED_COUNT; led_id++) {
++        reg_value = 0;
++        ret = airoha_led_set_state(phydev, led_id, led_cfg[led_id].en);
++        if (ret != 0) {
++            printf("LED fail to set state, ret %d !\n", ret);
++            return ret;
++        }
++        if (LED_ENABLE == led_cfg[led_id].en) {
++            if ( (led_cfg[led_id].gpio < 0) || led_cfg[led_id].gpio > 9) {
++                printf("GPIO%d is out of range!! GPIO number is 0~9.\n", led_cfg[led_id].gpio);
++                return -EIO;
++            }
++            led_gpio |= BIT(led_cfg[led_id].gpio);
++            reg_value = airoha_pbus_read(mbus, EN8801S_PBUS_PHY_ID, gpio_led_rg[led_cfg[led_id].gpio / 4]);
++            LED_SET_GPIO_SEL(led_cfg[led_id].gpio, led_id, reg_value);
++            debug("[Airoha] gpio%d, reg_value 0x%lx\n", led_cfg[led_id].gpio, reg_value);
++            ret = airoha_pbus_write(mbus, EN8801S_PBUS_PHY_ID, gpio_led_rg[led_cfg[led_id].gpio / 4], reg_value);
++            AIR_RTN_ERR(ret);
++            ret = airoha_led_set_usr_def(phydev, led_id, led_cfg[led_id].pol, led_cfg[led_id].on_cfg, led_cfg[led_id].blk_cfg);
++            if (ret != 0) {
++                printf("LED fail to set usr def, ret %d !\n", ret);
++                return ret;
++            }
++        }
++    }
++    reg_value = (airoha_pbus_read(mbus, EN8801S_PBUS_PHY_ID, 0x1880) & ~led_gpio);
++    ret = airoha_pbus_write(mbus, EN8801S_PBUS_PHY_ID, 0x1880, reg_value);
++    AIR_RTN_ERR(ret);
++    ret = airoha_pbus_write(mbus, EN8801S_PBUS_PHY_ID, 0x186c, led_gpio);
++    AIR_RTN_ERR(ret);
++
++    printf("LED initialize OK !\n");
++    return 0;
++}
++#endif /* AIR_LED_SUPPORT */
++
++static int en8801s_config(struct phy_device *phydev)
++{
++    int reg_value = 0, ret = 0;
++    struct mii_dev *mbus = phydev->bus;
++    int retry, pbus_addr = EN8801S_PBUS_DEFAULT_ID;
++    int phy_addr = EN8801S_MDIO_PHY_ID;
++    unsigned long pbus_data = 0;
++    gephy_all_REG_LpiReg1Ch      GPHY_RG_LPI_1C;
++    gephy_all_REG_dev1Eh_reg324h GPHY_RG_1E_324;
++    gephy_all_REG_dev1Eh_reg012h GPHY_RG_1E_012;
++    gephy_all_REG_dev1Eh_reg017h GPHY_RG_1E_017;
++
++    s_phydev = phydev;
++    retry = MAX_OUI_CHECK;
++    while (1) {
++        /* PHY OUI */
++        pbus_data = airoha_pbus_read(mbus, pbus_addr, EN8801S_RG_ETHER_PHY_OUI);
++        if (EN8801S_PBUS_OUI == pbus_data) {
++            printf("PBUS addr 0x%x: Start initialized.\n", pbus_addr);
++            ret = airoha_pbus_write(mbus, pbus_addr, EN8801S_RG_BUCK_CTL, 0x03);
++            AIR_RTN_ERR(ret);
++            break;
++        } else
++            pbus_addr = EN8801S_PBUS_PHY_ID;
++
++        if (0 == --retry) {
++            printf("EN8801S Probe fail !\n");
++            return 0;
++        }
++    }
++
++    /* SMI ADDR */
++    pbus_data = airoha_pbus_read(mbus, pbus_addr, EN8801S_RG_SMI_ADDR);
++    pbus_data = (pbus_data & 0xffff0000) | (unsigned long)(pbus_addr << 8) | (unsigned long)(EN8801S_MDIO_DEFAULT_ID);
++    ret = airoha_pbus_write(mbus, pbus_addr, EN8801S_RG_SMI_ADDR, pbus_data);
++    AIR_RTN_ERR(ret);
++    mdelay(10);
++
++    pbus_data = (airoha_pbus_read(mbus, pbus_addr, EN8801S_RG_LTR_CTL) & (~0x3)) | BIT(2) ;
++    ret = airoha_pbus_write(mbus, pbus_addr, EN8801S_RG_LTR_CTL, pbus_data);
++    AIR_RTN_ERR(ret);
++    mdelay(500);
++    pbus_data = (pbus_data & ~BIT(2)) | EN8801S_RX_POLARITY_NORMAL | EN8801S_TX_POLARITY_NORMAL;
++    ret = airoha_pbus_write(mbus, pbus_addr, EN8801S_RG_LTR_CTL, pbus_data);
++    AIR_RTN_ERR(ret);
++    mdelay(500);
++    /* SMI ADDR */
++    pbus_data = airoha_pbus_read(mbus, pbus_addr, EN8801S_RG_SMI_ADDR);
++    pbus_data = (pbus_data & 0xffff0000) | (unsigned long)(EN8801S_PBUS_PHY_ID << 8) | (unsigned long)(EN8801S_MDIO_PHY_ID);
++    ret = airoha_pbus_write(mbus, pbus_addr, EN8801S_RG_SMI_ADDR, pbus_data);
++    pbus_addr = EN8801S_PBUS_PHY_ID;
++    AIR_RTN_ERR(ret);
++    mdelay(10);
++
++    /* Optimze 10M IoT */
++    pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x1690);
++    pbus_data |= (1 << 31);
++    ret = airoha_pbus_write(mbus, pbus_addr, 0x1690, pbus_data);
++    AIR_RTN_ERR(ret);
++    /* set SGMII Base Page */
++    ret = airoha_pbus_write(mbus, pbus_addr, 0x0600, 0x0c000c00);
++    AIR_RTN_ERR(ret);
++    ret = airoha_pbus_write(mbus, pbus_addr, 0x10, 0xD801);
++    AIR_RTN_ERR(ret);
++    ret = airoha_pbus_write(mbus, pbus_addr, 0x0,  0x9140);
++    AIR_RTN_ERR(ret);
++    ret = airoha_pbus_write(mbus, pbus_addr, 0x0A14, 0x0003);
++    AIR_RTN_ERR(ret);
++    ret = airoha_pbus_write(mbus, pbus_addr, 0x0600, 0x0c000c00);
++    AIR_RTN_ERR(ret);
++    /* Set FCM control */
++    ret = airoha_pbus_write(mbus, pbus_addr, 0x1404, 0x004b);
++    AIR_RTN_ERR(ret);
++    ret = airoha_pbus_write(mbus, pbus_addr, 0x140c, 0x0007);
++    AIR_RTN_ERR(ret);
++
++    ret = airoha_pbus_write(mbus, pbus_addr, 0x142c, 0x05050505);
++    AIR_RTN_ERR(ret);
++    pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x1440);
++    ret = airoha_pbus_write(mbus, pbus_addr, 0x1440, pbus_data & ~BIT(11));
++    AIR_RTN_ERR(ret);
++
++    pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x1408);
++    ret = airoha_pbus_write(mbus, pbus_addr, 0x1408, pbus_data | BIT(5));
++    AIR_RTN_ERR(ret);
++
++    /* Set GPHY Perfomance*/
++    /* Token Ring */
++    ret = airoha_tr_reg_write(phydev, RgAddr_R1000DEC_15h, 0x0055A0);
++    AIR_RTN_ERR(ret);
++    ret = airoha_tr_reg_write(phydev, RgAddr_R1000DEC_17h, 0x07FF3F);
++    AIR_RTN_ERR(ret);
++    ret = airoha_tr_reg_write(phydev, RgAddr_PMA_00h,      0x00001E);
++    AIR_RTN_ERR(ret);
++    ret = airoha_tr_reg_write(phydev, RgAddr_PMA_01h,      0x6FB90A);
++    AIR_RTN_ERR(ret);
++    ret = airoha_tr_reg_write(phydev, RgAddr_PMA_17h,      0x060671);
++    AIR_RTN_ERR(ret);
++    ret = airoha_tr_reg_write(phydev, RgAddr_PMA_18h,      0x0E2F00);
++    AIR_RTN_ERR(ret);
++    ret = airoha_tr_reg_write(phydev, RgAddr_TR_26h,       0x444444);
++    AIR_RTN_ERR(ret);
++    ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_03h,     0x000000);
++    AIR_RTN_ERR(ret);
++    ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_06h,     0x2EBAEF);
++    AIR_RTN_ERR(ret);
++    ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_08h,     0x00000B);
++    AIR_RTN_ERR(ret);
++    ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_0Ch,     0x00504D);
++    AIR_RTN_ERR(ret);
++    ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_0Dh,     0x02314F);
++    AIR_RTN_ERR(ret);
++    ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_0Fh,     0x003028);
++    AIR_RTN_ERR(ret);
++    ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_10h,     0x005010);
++    AIR_RTN_ERR(ret);
++    ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_11h,     0x040001);
++    AIR_RTN_ERR(ret);
++    ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_13h,     0x018670);
++    AIR_RTN_ERR(ret);
++    ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_14h,     0x00024A);
++    AIR_RTN_ERR(ret);
++    ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_1Bh,     0x000072);
++    AIR_RTN_ERR(ret);
++    ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_1Ch,     0x003210);
++    AIR_RTN_ERR(ret);
++    /* CL22 & CL45 */
++    ret = airoha_cl22_write(mbus, phy_addr, 0x1f, 0x03);
++    AIR_RTN_ERR(ret);
++    GPHY_RG_LPI_1C.DATA = airoha_cl22_read(mbus, phy_addr, RgAddr_LPI_1Ch);
++    if (GPHY_RG_LPI_1C.DATA < 0)
++        return -EIO;
++    GPHY_RG_LPI_1C.DataBitField.smi_deton_th = 0x0C;
++    ret = airoha_cl22_write(mbus, phy_addr, RgAddr_LPI_1Ch, GPHY_RG_LPI_1C.DATA);
++    AIR_RTN_ERR(ret);
++    ret = airoha_cl22_write(mbus, phy_addr, RgAddr_LPI_1Ch, 0xC92);
++    AIR_RTN_ERR(ret);
++    ret = airoha_cl22_write(mbus, phy_addr, RgAddr_AUXILIARY_1Dh, 0x1);
++    AIR_RTN_ERR(ret);
++    ret = airoha_cl22_write(mbus, phy_addr, 0x1f, 0x0);
++    AIR_RTN_ERR(ret);
++    ret = airoha_cl45_write(phydev, 0x1E, 0x120, 0x8014);
++    AIR_RTN_ERR(ret);
++    ret = airoha_cl45_write(phydev, 0x1E, 0x122, 0xffff);
++    AIR_RTN_ERR(ret);
++    ret = airoha_cl45_write(phydev, 0x1E, 0x123, 0xffff);
++    AIR_RTN_ERR(ret);
++    ret = airoha_cl45_write(phydev, 0x1E, 0x144, 0x0200);
++    AIR_RTN_ERR(ret);
++    ret = airoha_cl45_write(phydev, 0x1E, 0x14A, 0xEE20);
++    AIR_RTN_ERR(ret);
++    ret = airoha_cl45_write(phydev, 0x1E, 0x189, 0x0110);
++    AIR_RTN_ERR(ret);
++    ret = airoha_cl45_write(phydev, 0x1E, 0x19B, 0x0111);
++    AIR_RTN_ERR(ret);
++    ret = airoha_cl45_write(phydev, 0x1E, 0x234, 0x0181);
++    AIR_RTN_ERR(ret);
++    ret = airoha_cl45_write(phydev, 0x1E, 0x238, 0x0120);
++    AIR_RTN_ERR(ret);
++    ret = airoha_cl45_write(phydev, 0x1E, 0x239, 0x0117);
++    AIR_RTN_ERR(ret);
++    ret = airoha_cl45_write(phydev, 0x1E, 0x268, 0x07F4);
++    AIR_RTN_ERR(ret);
++    ret = airoha_cl45_write(phydev, 0x1E, 0x2D1, 0x0733);
++    AIR_RTN_ERR(ret);
++    ret = airoha_cl45_write(phydev, 0x1E, 0x323, 0x0011);
++    AIR_RTN_ERR(ret);
++    ret = airoha_cl45_write(phydev, 0x1E, 0x324, 0x013F);
++    AIR_RTN_ERR(ret);
++    ret = airoha_cl45_write(phydev, 0x1E, 0x326, 0x0037);
++    AIR_RTN_ERR(ret);
++
++    reg_value = airoha_cl45_read(phydev, 0x1E, 0x324);
++    if (reg_value < 0)
++        return -EIO;
++    GPHY_RG_1E_324.DATA = (int)reg_value;
++    GPHY_RG_1E_324.DataBitField.smi_det_deglitch_off = 0;
++    ret = airoha_cl45_write(phydev, 0x1E, 0x324, GPHY_RG_1E_324.DATA);
++    AIR_RTN_ERR(ret);
++    ret = airoha_cl45_write(phydev, 0x1E, 0x19E, 0xC2);
++    AIR_RTN_ERR(ret);
++    ret = airoha_cl45_write(phydev, 0x1E, 0x013, 0x0);
++    AIR_RTN_ERR(ret);
++
++    /* EFUSE */
++    airoha_pbus_write(mbus, pbus_addr, 0x1C08, 0x40000040);
++    retry = MAX_RETRY;
++    while (0 != retry) {
++        mdelay(1);
++        pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x1C08);
++        if ((pbus_data & (1 << 30)) == 0) {
++            break;
++        }
++        retry--;
++    }
++    pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x1C38);          /* RAW#2 */
++    reg_value = airoha_cl45_read(phydev, 0x1E, 0x12);
++    if (reg_value < 0)
++        return -EIO;
++    GPHY_RG_1E_012.DATA = reg_value;
++    GPHY_RG_1E_012.DataBitField.da_tx_i2mpb_a_tbt = pbus_data & 0x03f;
++    ret = airoha_cl45_write(phydev, 0x1E, 0x12, GPHY_RG_1E_012.DATA);
++    AIR_RTN_ERR(ret);
++    reg_value = airoha_cl45_read(phydev, 0x1E, 0x17);
++    if (reg_value < 0)
++        return -EIO;
++    GPHY_RG_1E_017.DataBitField.da_tx_i2mpb_b_tbt = (reg_value >> 8) & 0x03f;
++    ret = airoha_cl45_write(phydev, 0x1E, 0x17, GPHY_RG_1E_017.DATA);
++    AIR_RTN_ERR(ret);
++
++    ret = airoha_pbus_write(mbus, pbus_addr, 0x1C08, 0x40400040);
++    AIR_RTN_ERR(ret);
++    retry = MAX_RETRY;
++    while (0 != retry) {
++        mdelay(1);
++        reg_value = airoha_pbus_read(mbus, pbus_addr, 0x1C08);
++        if ((reg_value & (1 << 30)) == 0) {
++            break;
++        }
++        retry--;
++    }
++    pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x1C30);          /* RAW#16 */
++    GPHY_RG_1E_324.DataBitField.smi_det_deglitch_off = (pbus_data >> 12) & 0x01;
++    ret = airoha_cl45_write(phydev, 0x1E, 0x324, GPHY_RG_1E_324.DATA);
++    AIR_RTN_ERR(ret);
++#ifdef AIR_LED_SUPPORT
++    ret = en8801s_led_init(phydev);
++    if (ret != 0){
++        printf("en8801s_led_init fail (ret:%d) !\n", ret);
++    }
++#endif
++    printf("EN8801S initialize OK ! (%s)\n", EN8801S_DRIVER_VERSION);
++    return 0;
++}
++
++int en8801s_read_status(struct phy_device *phydev)
++{
++    int ret, pbus_addr = EN8801S_PBUS_PHY_ID;
++    struct mii_dev *mbus;
++    unsigned long pbus_data;
++
++    mbus = phydev->bus;
++    if (SPEED_10 == phydev->speed) {
++        /* set the bit for Optimze 10M IoT */
++        debug("[Airoha] SPEED_10 0x1694\n");
++        pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x1694);
++        pbus_data |= (1 << 31);
++        ret = airoha_pbus_write(mbus, pbus_addr, 0x1694, pbus_data);
++        AIR_RTN_ERR(ret);
++    } else {
++        debug("[Airoha] SPEED_1000/100 0x1694\n");
++        /* clear the bit for other speeds */
++        pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x1694);
++        pbus_data &= ~(1 << 31);
++        ret = airoha_pbus_write(mbus, pbus_addr, 0x1694, pbus_data);
++        AIR_RTN_ERR(ret);
++    }
++
++    airoha_pbus_write(mbus, pbus_addr, 0x0600, 0x0c000c00);
++    if(SPEED_1000 == phydev->speed) {
++        debug("[Airoha] SPEED_1000\n");
++        ret = airoha_pbus_write(mbus, pbus_addr, 0x10, 0xD801);
++        AIR_RTN_ERR(ret);
++        ret = airoha_pbus_write(mbus, pbus_addr, 0x0,  0x9140);
++        AIR_RTN_ERR(ret);
++
++        ret = airoha_pbus_write(mbus, pbus_addr, 0x0A14, 0x0003);
++        AIR_RTN_ERR(ret);
++        ret = airoha_pbus_write(mbus, pbus_addr, 0x0600, 0x0c000c00);
++        AIR_RTN_ERR(ret);
++        mdelay(2);  /* delay 2 ms */
++        ret = airoha_pbus_write(mbus, pbus_addr, 0x1404, 0x004b);
++        AIR_RTN_ERR(ret);
++        ret = airoha_pbus_write(mbus, pbus_addr, 0x140c, 0x0007);
++        AIR_RTN_ERR(ret);
++    }
++    else if (SPEED_100 == phydev->speed) {
++        debug("[Airoha] SPEED_100\n");
++        ret = airoha_pbus_write(mbus, pbus_addr, 0x10, 0xD401);
++        AIR_RTN_ERR(ret);
++        ret = airoha_pbus_write(mbus, pbus_addr, 0x0,  0x9140);
++        AIR_RTN_ERR(ret);
++        ret = airoha_pbus_write(mbus, pbus_addr, 0x0A14, 0x0007);
++        AIR_RTN_ERR(ret);
++        ret = airoha_pbus_write(mbus, pbus_addr, 0x0600, 0x0c11);
++        AIR_RTN_ERR(ret);
++        mdelay(2);  /* delay 2 ms */
++        ret = airoha_pbus_write(mbus, pbus_addr, 0x1404, 0x0027);
++        AIR_RTN_ERR(ret);
++        ret = airoha_pbus_write(mbus, pbus_addr, 0x140c, 0x0007);
++        AIR_RTN_ERR(ret);
++    }
++    else {
++        debug("[Airoha] SPEED_10\n");
++        ret = airoha_pbus_write(mbus, pbus_addr, 0x10, 0xD001);
++        AIR_RTN_ERR(ret);
++        ret = airoha_pbus_write(mbus, pbus_addr, 0x0,  0x9140);
++        AIR_RTN_ERR(ret);
++
++        ret = airoha_pbus_write(mbus, pbus_addr, 0x0A14, 0x000b);
++        AIR_RTN_ERR(ret);
++        ret = airoha_pbus_write(mbus, pbus_addr, 0x0600, 0x0c11);
++        AIR_RTN_ERR(ret);
++         mdelay(2);  /* delay 2 ms */
++        ret = airoha_pbus_write(mbus, pbus_addr, 0x1404, 0x0047);
++        AIR_RTN_ERR(ret);
++        ret = airoha_pbus_write(mbus, pbus_addr, 0x140c, 0x0007);
++        AIR_RTN_ERR(ret);
++    }
++    return 0;
++}
++
++static int en8801s_startup(struct phy_device *phydev)
++{
++    int ret;
++
++    ret = genphy_update_link(phydev);
++    if (ret)
++        return ret;
++    ret = genphy_parse_link(phydev);
++    if (ret)
++        return ret;
++    return en8801s_read_status(phydev);
++}
++#if AIR_UBOOT_REVISION > 0x202303
++U_BOOT_PHY_DRIVER(en8801s) = {
++    .name = "Airoha EN8801S",
++    .uid = EN8801S_PHY_ID,
++    .mask = 0x0ffffff0,
++    .features = PHY_GBIT_FEATURES,
++    .config = &en8801s_config,
++    .startup = &en8801s_startup,
++    .shutdown = &genphy_shutdown,
++};
++#else
++static struct phy_driver AIR_EN8801S_driver = {
++    .name = "Airoha EN8801S",
++    .uid = EN8801S_PHY_ID,
++    .mask = 0x0ffffff0,
++    .features = PHY_GBIT_FEATURES,
++    .config = &en8801s_config,
++    .startup = &en8801s_startup,
++    .shutdown = &genphy_shutdown,
++};
++
++int phy_air_en8801s_init(void)
++{
++    phy_register(&AIR_EN8801S_driver);
++    return 0;
++}
++#endif
+--- /dev/null
++++ b/drivers/net/phy/air_en8801s.h
+@@ -0,0 +1,267 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++/*************************************************
++ * FILE NAME:  air_en8801s.h
++ * PURPOSE:
++ *      EN8801S PHY Driver for Uboot
++ * NOTES:
++ *
++ *  Copyright (C) 2023 Airoha Technology Corp.
++ *************************************************/
++
++#ifndef __EN8801S_H
++#define __EN8801S_H
++
++/************************************************************************
++*                  D E F I N E S
++************************************************************************/
++#define AIR_UBOOT_REVISION ((((U_BOOT_VERSION_NUM / 1000) % 10) << 20) | \
++		      (((U_BOOT_VERSION_NUM / 100) % 10) << 16) | \
++		      (((U_BOOT_VERSION_NUM / 10) % 10) << 12) | \
++		      ((U_BOOT_VERSION_NUM % 10) << 8) | \
++		      (((U_BOOT_VERSION_NUM_PATCH / 10) % 10) << 4) | \
++		      ((U_BOOT_VERSION_NUM_PATCH % 10) << 0))
++
++#define EN8801S_MDIO_DEFAULT_ID 0x1d
++#define EN8801S_PBUS_DEFAULT_ID (EN8801S_MDIO_DEFAULT_ID + 1)
++#define EN8801S_MDIO_PHY_ID     0x18       /* Range PHY_ADDRESS_RANGE .. 0x1e */
++#define EN8801S_PBUS_PHY_ID     (EN8801S_MDIO_PHY_ID + 1)
++#define EN8801S_DRIVER_VERSION      "v1.1.3"
++
++#define EN8801S_RG_ETHER_PHY_OUI    0x19a4
++#define EN8801S_RG_SMI_ADDR         0x19a8
++#define EN8801S_PBUS_OUI            0x17a5
++#define EN8801S_RG_BUCK_CTL         0x1a20
++#define EN8801S_RG_LTR_CTL          0x0cf8
++
++#define EN8801S_PHY_ID1         0x03a2
++#define EN8801S_PHY_ID2         0x9461
++#define EN8801S_PHY_ID          (unsigned long)((EN8801S_PHY_ID1 << 16) | EN8801S_PHY_ID2)
++
++/*
++SFP Sample for verification
++Tx Reverse, Rx Reverse
++*/
++#define EN8801S_TX_POLARITY_NORMAL   0x0
++#define EN8801S_TX_POLARITY_REVERSE  0x1
++
++#define EN8801S_RX_POLARITY_NORMAL   (0x1 << 1)
++#define EN8801S_RX_POLARITY_REVERSE  (0x0 << 1)
++
++#ifndef BIT
++#define BIT(nr)			(1UL << (nr))
++#endif
++
++#define MAX_RETRY               5
++#define MAX_OUI_CHECK           2
++
++/* CL45 MDIO control */
++#define MII_MMD_ACC_CTL_REG     0x0d
++#define MII_MMD_ADDR_DATA_REG   0x0e
++#define MMD_OP_MODE_DATA        BIT(14)
++
++#define MAX_TRG_COUNTER         5
++
++/* TokenRing Reg Access */
++#define TrReg_PKT_XMT_STA       0x8000
++#define TrReg_WR                0x8000
++#define TrReg_RD                0xA000
++
++#define RgAddr_LPI_1Ch       0x1c
++#define RgAddr_AUXILIARY_1Dh 0x1d
++#define RgAddr_PMA_00h       0x0f80
++#define RgAddr_PMA_01h       0x0f82
++#define RgAddr_PMA_17h       0x0fae
++#define RgAddr_PMA_18h       0x0fb0
++#define RgAddr_DSPF_03h      0x1686
++#define RgAddr_DSPF_06h      0x168c
++#define RgAddr_DSPF_08h      0x1690
++#define RgAddr_DSPF_0Ch      0x1698
++#define RgAddr_DSPF_0Dh      0x169a
++#define RgAddr_DSPF_0Fh      0x169e
++#define RgAddr_DSPF_10h      0x16a0
++#define RgAddr_DSPF_11h      0x16a2
++#define RgAddr_DSPF_13h      0x16a6
++#define RgAddr_DSPF_14h      0x16a8
++#define RgAddr_DSPF_1Bh      0x16b6
++#define RgAddr_DSPF_1Ch      0x16b8
++#define RgAddr_TR_26h        0x0ecc
++#define RgAddr_R1000DEC_15h  0x03aa
++#define RgAddr_R1000DEC_17h  0x03ae
++
++/*
++The following led_cfg example is for reference only.
++LED5 1000M/LINK/ACT  (GPIO5)  <-> BASE_T_LED0,
++LED6 10/100M/LINK/ACT(GPIO9)  <-> BASE_T_LED1,
++LED4 100M/LINK/ACT   (GPIO8)  <-> BASE_T_LED2,
++*/
++/* User-defined.B */
++#define BASE_T_LED0_ON_CFG      (LED_ON_EVT_LINK_1000M)
++#define BASE_T_LED0_BLK_CFG     (LED_BLK_EVT_1000M_TX_ACT | LED_BLK_EVT_1000M_RX_ACT)
++#define BASE_T_LED1_ON_CFG      (LED_ON_EVT_LINK_100M | LED_ON_EVT_LINK_10M)
++#define BASE_T_LED1_BLK_CFG     (LED_BLK_EVT_100M_TX_ACT | LED_BLK_EVT_100M_RX_ACT | \
++                                 LED_BLK_EVT_10M_TX_ACT | LED_BLK_EVT_10M_RX_ACT )
++#define BASE_T_LED2_ON_CFG      (LED_ON_EVT_LINK_100M)
++#define BASE_T_LED2_BLK_CFG     (LED_BLK_EVT_100M_TX_ACT | LED_BLK_EVT_100M_RX_ACT)
++#define BASE_T_LED3_ON_CFG      (0x0)
++#define BASE_T_LED3_BLK_CFG     (0x0)
++/* User-defined.E */
++
++#define EN8801S_LED_COUNT       4
++
++#define LED_BCR                     (0x021)
++#define LED_BCR_EXT_CTRL            (1 << 15)
++#define LED_BCR_CLK_EN              (1 << 3)
++#define LED_BCR_TIME_TEST           (1 << 2)
++#define LED_BCR_MODE_MASK           (3)
++#define LED_BCR_MODE_DISABLE        (0)
++#define LED_ON_CTRL(i)              (0x024 + ((i)*2))
++#define LED_ON_EN                   (1 << 15)
++#define LED_ON_POL                  (1 << 14)
++#define LED_ON_EVT_MASK             (0x7f)
++/* LED ON Event Option.B */
++#define LED_ON_EVT_FORCE            (1 << 6)
++#define LED_ON_EVT_LINK_DOWN        (1 << 3)
++#define LED_ON_EVT_LINK_10M         (1 << 2)
++#define LED_ON_EVT_LINK_100M        (1 << 1)
++#define LED_ON_EVT_LINK_1000M       (1 << 0)
++/* LED ON Event Option.E */
++#define LED_BLK_CTRL(i)             (0x025 + ((i)*2))
++#define LED_BLK_EVT_MASK            (0x3ff)
++/* LED Blinking Event Option.B*/
++#define LED_BLK_EVT_FORCE           (1 << 9)
++#define LED_BLK_EVT_10M_RX_ACT      (1 << 5)
++#define LED_BLK_EVT_10M_TX_ACT      (1 << 4)
++#define LED_BLK_EVT_100M_RX_ACT     (1 << 3)
++#define LED_BLK_EVT_100M_TX_ACT     (1 << 2)
++#define LED_BLK_EVT_1000M_RX_ACT    (1 << 1)
++#define LED_BLK_EVT_1000M_TX_ACT    (1 << 0)
++/* LED Blinking Event Option.E*/
++#define LED_ON_DUR                  (0x022)
++#define LED_ON_DUR_MASK             (0xffff)
++#define LED_BLK_DUR                 (0x023)
++#define LED_BLK_DUR_MASK            (0xffff)
++
++#define LED_ENABLE                  1
++#define LED_DISABLE                 0
++
++#define UNIT_LED_BLINK_DURATION     1024
++
++#define AIR_RTN_ON_ERR(cond, err)  \
++    do { if ((cond)) return (err); } while(0)
++
++#define AIR_RTN_ERR(err)                       AIR_RTN_ON_ERR(err < 0, err)
++
++#define LED_SET_EVT(reg, cod, result, bit) do         \
++    {                                                 \
++        if(reg & cod) {                               \
++            result |= bit;                            \
++        }                                             \
++    } while(0)
++
++#define LED_SET_GPIO_SEL(gpio, led, val) do           \
++    {                                                 \
++            val |= (led << (8 * (gpio % 4)));         \
++    } while(0)
++
++/* DATA TYPE DECLARATIONS
++ */
++typedef struct
++{
++    int DATA_Lo;
++    int DATA_Hi;
++}TR_DATA_T;
++
++typedef union
++{
++    struct
++    {
++        /* b[15:00] */
++        int smi_deton_wt                             : 3;
++        int smi_det_mdi_inv                          : 1;
++        int smi_detoff_wt                            : 3;
++        int smi_sigdet_debouncing_en                 : 1;
++        int smi_deton_th                             : 6;
++        int rsv_14                                   : 2;
++    } DataBitField;
++    int DATA;
++} gephy_all_REG_LpiReg1Ch, *Pgephy_all_REG_LpiReg1Ch;
++
++typedef union
++{
++    struct
++    {
++        /* b[15:00] */
++        int rg_smi_detcnt_max                        : 6;
++        int rsv_6                                    : 2;
++        int rg_smi_det_max_en                        : 1;
++        int smi_det_deglitch_off                     : 1;
++        int rsv_10                                   : 6;
++    } DataBitField;
++    int DATA;
++} gephy_all_REG_dev1Eh_reg324h, *Pgephy_all_REG_dev1Eh_reg324h;
++
++typedef union
++{
++    struct
++    {
++        /* b[15:00] */
++        int da_tx_i2mpb_a_tbt                        : 6;
++        int rsv_6                                    : 4;
++        int da_tx_i2mpb_a_gbe                        : 6;
++    } DataBitField;
++    int DATA;
++} gephy_all_REG_dev1Eh_reg012h, *Pgephy_all_REG_dev1Eh_reg012h;
++
++typedef union
++{
++    struct
++    {
++        /* b[15:00] */
++        int da_tx_i2mpb_b_tbt                        : 6;
++        int rsv_6                                    : 2;
++        int da_tx_i2mpb_b_gbe                        : 6;
++        int rsv_14                                   : 2;
++    } DataBitField;
++    int DATA;
++} gephy_all_REG_dev1Eh_reg017h, *Pgephy_all_REG_dev1Eh_reg017h;
++
++typedef struct AIR_BASE_T_LED_CFG_S
++{
++    u16 en;
++    u16 gpio;
++    u16 pol;
++    u16 on_cfg;
++    u16 blk_cfg;
++}AIR_BASE_T_LED_CFG_T;
++
++typedef enum
++{
++    AIR_LED_BLK_DUR_32M,
++    AIR_LED_BLK_DUR_64M,
++    AIR_LED_BLK_DUR_128M,
++    AIR_LED_BLK_DUR_256M,
++    AIR_LED_BLK_DUR_512M,
++    AIR_LED_BLK_DUR_1024M,
++    AIR_LED_BLK_DUR_LAST
++} AIR_LED_BLK_DUT_T;
++
++typedef enum
++{
++    AIR_ACTIVE_LOW,
++    AIR_ACTIVE_HIGH,
++} AIR_LED_POLARITY;
++typedef enum
++{
++    AIR_LED_MODE_DISABLE,
++    AIR_LED_MODE_USER_DEFINE,
++    AIR_LED_MODE_LAST
++} AIR_LED_MODE_T;
++
++/************************************************************************
++*                  F U N C T I O N    P R O T O T Y P E S
++************************************************************************/
++
++unsigned long airoha_pbus_read(struct mii_dev *bus, int pbus_addr, int pbus_reg);
++int airoha_pbus_write(struct mii_dev *bus, int pbus_addr, int pbus_reg, unsigned long pbus_data);
++int airoha_phy_process(void);
++#endif /* __EN8801S_H */
+--- /dev/null
++++ b/drivers/net/phy/air_en8811h.c
+@@ -0,0 +1,725 @@
++// SPDX-License-Identifier: GPL-2.0
++/*************************************************
++ * FILE NAME:  air_en8811h.c
++ * PURPOSE:
++ *      EN8811H PHY Driver for Uboot
++ * NOTES:
++ *
++ *  Copyright (C) 2023 Airoha Technology Corp.
++ *************************************************/
++
++/* INCLUDE FILE DECLARATIONS
++*/
++#include <common.h>
++#include <eth_phy.h>
++#include <phy.h>
++#include <errno.h>
++#include <malloc.h>
++#include <version.h>
++#include "air_en8811h.h"
++
++#ifdef CONFIG_PHY_AIROHA_FW_IN_UBI
++#include <ubi_uboot.h>
++#endif
++
++#ifdef CONFIG_PHY_AIROHA_FW_IN_MMC
++#include <mmc.h>
++#endif
++
++#ifdef CONFIG_PHY_AIROHA_FW_IN_MTD
++#include <mtd.h>
++#endif
++
++#if AIR_UBOOT_REVISION > 0x202004
++#include <linux/delay.h>
++#endif
++
++/**************************
++ * GPIO5  <-> BASE_T_LED0,
++ * GPIO4  <-> BASE_T_LED1,
++ * GPIO3  <-> BASE_T_LED2,
++ **************************/
++/* User-defined.B */
++#define AIR_LED_SUPPORT
++#ifdef AIR_LED_SUPPORT
++static const struct air_base_t_led_cfg_s led_cfg[3] = {
++/*********************************************************************
++ *Enable,   GPIO,        LED Polarity,     LED ON,      LED Blink
++**********************************************************************/
++    {1, AIR_LED0_GPIO5, AIR_ACTIVE_HIGH, AIR_LED0_ON, AIR_LED0_BLK},
++    {1, AIR_LED1_GPIO4, AIR_ACTIVE_HIGH, AIR_LED1_ON, AIR_LED1_BLK},
++    {1, AIR_LED2_GPIO3, AIR_ACTIVE_HIGH, AIR_LED2_ON, AIR_LED2_BLK},
++};
++static const u16 led_dur = UNIT_LED_BLINK_DURATION << AIR_LED_BLK_DUR_64M;
++#endif
++/* User-defined.E */
++/*************************************************************
++ *                       F U N C T I O N S
++ **************************************************************/
++/* Airoha MII read function */
++static int air_mii_cl22_read(struct mii_dev *bus, int phy_addr, int phy_register)
++{
++    int read_data = bus->read(bus, phy_addr, MDIO_DEVAD_NONE, phy_register);
++
++    if (read_data < 0)
++        return -EIO;
++    return read_data;
++}
++
++/* Airoha MII write function */
++static int air_mii_cl22_write(struct mii_dev *bus, int phy_addr, int phy_register, int write_data)
++{
++    int ret = 0;
++
++    ret = bus->write(bus, phy_addr, MDIO_DEVAD_NONE, phy_register, write_data);
++    if (ret < 0) {
++        printf("bus->write, ret: %d\n", ret);
++        return ret;
++    }
++    return ret;
++}
++
++static int air_mii_cl45_read(struct phy_device *phydev, int devad, u16 reg)
++{
++    int ret = 0;
++    int data;
++
++    ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_ACC_CTL_REG, devad);
++    if (ret < 0) {
++        printf("phy_write, ret: %d\n", ret);
++        return INVALID_DATA;
++    }
++    ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_ADDR_DATA_REG, reg);
++    if (ret < 0) {
++        printf("phy_write, ret: %d\n", ret);
++        return INVALID_DATA;
++    }
++    ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_ACC_CTL_REG, MMD_OP_MODE_DATA | devad);
++    if (ret < 0) {
++        printf("phy_write, ret: %d\n", ret);
++        return INVALID_DATA;
++    }
++    data = phy_read(phydev, MDIO_DEVAD_NONE, MII_MMD_ADDR_DATA_REG);
++    return data;
++}
++
++static int air_mii_cl45_write(struct phy_device *phydev, int devad, u16 reg, u16 write_data)
++{
++    int ret = 0;
++
++    ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_ACC_CTL_REG, devad);
++    if (ret < 0) {
++        printf("phy_write, ret: %d\n", ret);
++        return ret;
++    }
++    ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_ADDR_DATA_REG, reg);
++    if (ret < 0) {
++        printf("phy_write, ret: %d\n", ret);
++        return ret;
++    }
++    ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_ACC_CTL_REG, MMD_OP_MODE_DATA | devad);
++    if (ret < 0) {
++        printf("phy_write, ret: %d\n", ret);
++        return ret;
++    }
++    ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_ADDR_DATA_REG, write_data);
++    if (ret < 0) {
++        printf("phy_write, ret: %d\n", ret);
++        return ret;
++    }
++    return 0;
++}
++/* Use default PBUS_PHY_ID */
++/* EN8811H PBUS write function */
++static int air_pbus_reg_write(struct phy_device *phydev, unsigned long pbus_address, unsigned long pbus_data)
++{
++    int ret = 0;
++    struct mii_dev *mbus = phydev->bus;
++
++    ret = air_mii_cl22_write(mbus, ((phydev->addr) + 8), 0x1F, (unsigned int)(pbus_address >> 6));
++    if (ret < 0)
++        return ret;
++    ret = air_mii_cl22_write(mbus, ((phydev->addr) + 8), (unsigned int)((pbus_address >> 2) & 0xf), (unsigned int)(pbus_data & 0xFFFF));
++    if (ret < 0)
++        return ret;
++    ret = air_mii_cl22_write(mbus, ((phydev->addr) + 8), 0x10, (unsigned int)(pbus_data >> 16));
++    if (ret < 0)
++        return ret;
++    return 0;
++}
++
++/* EN8811H BUCK write function */
++static int air_buckpbus_reg_write(struct phy_device *phydev, unsigned long pbus_address, unsigned int pbus_data)
++{
++    int ret = 0;
++
++    /* page 4 */
++    ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x1F, (unsigned int)4);
++    if (ret < 0) {
++        printf("phy_write, ret: %d\n", ret);
++        return ret;
++    }
++    ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x10, (unsigned int)0);
++    if (ret < 0) {
++        printf("phy_write, ret: %d\n", ret);
++        return ret;
++    }
++    ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x11, (unsigned int)((pbus_address >> 16) & 0xffff));
++    if (ret < 0) {
++        printf("phy_write, ret: %d\n", ret);
++        return ret;
++    }
++    ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x12, (unsigned int)(pbus_address & 0xffff));
++    if (ret < 0) {
++        printf("phy_write, ret: %d\n", ret);
++        return ret;
++    }
++    ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x13, (unsigned int)((pbus_data >> 16) & 0xffff));
++    if (ret < 0) {
++        printf("phy_write, ret: %d\n", ret);
++        return ret;
++    }
++    ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, (unsigned int)(pbus_data & 0xffff));
++    if (ret < 0) {
++        printf("phy_write, ret: %d\n", ret);
++        return ret;
++    }
++    return 0;
++}
++
++/* EN8811H BUCK read function */
++static unsigned int air_buckpbus_reg_read(struct phy_device *phydev, unsigned long pbus_address)
++{
++    unsigned int pbus_data = 0, pbus_data_low, pbus_data_high;
++    int ret = 0;
++
++    ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x1F, (unsigned int)4);        /* page 4 */
++    if (ret < 0) {
++        printf("phy_write, ret: %d\n", ret);
++        return PBUS_INVALID_DATA;
++    }
++    ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x10, (unsigned int)0);
++    if (ret < 0) {
++        printf("phy_write, ret: %d\n", ret);
++        return PBUS_INVALID_DATA;
++    }
++    ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x15, (unsigned int)((pbus_address >> 16) & 0xffff));
++    if (ret < 0) {
++        printf("phy_write, ret: %d\n", ret);
++        return PBUS_INVALID_DATA;
++    }
++    ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x16, (unsigned int)(pbus_address & 0xffff));
++    if (ret < 0) {
++        printf("phy_write, ret: %d\n", ret);
++        return PBUS_INVALID_DATA;
++    }
++
++    pbus_data_high = phy_read(phydev, MDIO_DEVAD_NONE, 0x17);
++    pbus_data_low = phy_read(phydev, MDIO_DEVAD_NONE, 0x18);
++    pbus_data = (pbus_data_high << 16) + pbus_data_low;
++    ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x1F, (unsigned int)0);
++    if (ret < 0) {
++        printf("phy_write, ret: %d\n", ret);
++        return ret;
++    }
++    return pbus_data;
++}
++
++static int MDIOWriteBuf(struct phy_device *phydev, unsigned long address, unsigned long array_size, const unsigned char *buffer)
++{
++    unsigned int write_data, offset ;
++    int ret = 0;
++
++    /* page 4 */
++    ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x1F, (unsigned int)4);
++    if (ret < 0) {
++        printf("phy_write, ret: %d\n", ret);
++        return ret;
++    }
++    /* address increment*/
++    ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x10, (unsigned int)0x8000);
++    if (ret < 0) {
++        printf("phy_write, ret: %d\n", ret);
++        return ret;
++    }
++    ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x11, (unsigned int)((address >> 16) & 0xffff));
++    if (ret < 0) {
++        printf("phy_write, ret: %d\n", ret);
++        return ret;
++    }
++    ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x12, (unsigned int)(address & 0xffff));
++    if (ret < 0) {
++        printf("phy_write, ret: %d\n", ret);
++        return ret;
++    }
++
++    for (offset = 0; offset < array_size; offset += 4) {
++        write_data = (buffer[offset + 3] << 8) | buffer[offset + 2];
++        ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x13, write_data);
++        if (ret < 0) {
++            printf("phy_write, ret: %d\n", ret);
++            return ret;
++        }
++        write_data = (buffer[offset + 1] << 8) | buffer[offset];
++        ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, write_data);
++        if (ret < 0) {
++            printf("phy_write, ret: %d\n", ret);
++            return ret;
++        }
++    }
++    ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x1F, (unsigned int)0);
++    if (ret < 0) {
++        printf("phy_write, ret: %d\n", ret);
++        return ret;
++    }
++    return 0;
++}
++
++#ifdef  AIR_LED_SUPPORT
++static int airoha_led_set_usr_def(struct phy_device *phydev, u8 entity, int polar,
++                                   u16 on_evt, u16 blk_evt)
++{
++    int ret = 0;
++
++    if (AIR_ACTIVE_HIGH == polar)
++        on_evt |= LED_ON_POL;
++    else
++        on_evt &= ~LED_ON_POL;
++
++    ret = air_mii_cl45_write(phydev, 0x1f, LED_ON_CTRL(entity), on_evt | LED_ON_EN);
++    if (ret < 0)
++        return ret;
++    ret = air_mii_cl45_write(phydev, 0x1f, LED_BLK_CTRL(entity), blk_evt);
++    if (ret < 0)
++        return ret;
++    return 0;
++}
++
++static int airoha_led_set_mode(struct phy_device *phydev, u8 mode)
++{
++    u16 cl45_data;
++    int err = 0;
++
++    cl45_data = air_mii_cl45_read(phydev, 0x1f, LED_BCR);
++    switch (mode) {
++    case AIR_LED_MODE_DISABLE:
++        cl45_data &= ~LED_BCR_EXT_CTRL;
++        cl45_data &= ~LED_BCR_MODE_MASK;
++        cl45_data |= LED_BCR_MODE_DISABLE;
++        break;
++    case AIR_LED_MODE_USER_DEFINE:
++        cl45_data |= LED_BCR_EXT_CTRL;
++        cl45_data |= LED_BCR_CLK_EN;
++        break;
++    default:
++        printf("LED mode%d is not supported!\n", mode);
++        return -EINVAL;
++    }
++    err = air_mii_cl45_write(phydev, 0x1f, LED_BCR, cl45_data);
++    if (err < 0)
++        return err;
++    return 0;
++}
++
++static int airoha_led_set_state(struct phy_device *phydev, u8 entity, u8 state)
++{
++    u16 cl45_data;
++    int err;
++
++    cl45_data = air_mii_cl45_read(phydev, 0x1f, LED_ON_CTRL(entity));
++    if (LED_ENABLE == state)
++        cl45_data |= LED_ON_EN;
++    else
++        cl45_data &= ~LED_ON_EN;
++
++    err = air_mii_cl45_write(phydev, 0x1f, LED_ON_CTRL(entity), cl45_data);
++    if (err < 0)
++        return err;
++    return 0;
++}
++
++static int en8811h_led_init(struct phy_device *phydev)
++{
++    unsigned int led_gpio = 0, reg_value = 0;
++    u16 cl45_data = led_dur;
++    int ret, led_id;
++
++    cl45_data = UNIT_LED_BLINK_DURATION << AIR_LED_BLK_DUR_64M;
++    ret = air_mii_cl45_write(phydev, 0x1f, LED_BLK_DUR, cl45_data);
++    if (ret < 0)
++        return ret;
++    cl45_data >>= 1;
++    ret = air_mii_cl45_write(phydev, 0x1f, LED_ON_DUR, cl45_data);
++    if (ret < 0)
++        return ret;
++
++    ret = airoha_led_set_mode(phydev, AIR_LED_MODE_USER_DEFINE);
++    if (ret != 0) {
++        printf("LED fail to set mode, ret %d !\n", ret);
++        return ret;
++    }
++    for(led_id = 0; led_id < EN8811H_LED_COUNT; led_id++)
++    {
++        /* LED0 <-> GPIO5, LED1 <-> GPIO4, LED0 <-> GPIO3 */
++        if ( led_cfg[led_id].gpio != (led_id + (AIR_LED0_GPIO5 - (2 * led_id)))) {
++            printf("LED%d uses incorrect GPIO%d !\n", led_id, led_cfg[led_id].gpio);
++            return -EINVAL;
++        }
++        reg_value = 0;
++        if (led_cfg[led_id].en == LED_ENABLE)
++        {
++            led_gpio |= BIT(led_cfg[led_id].gpio);
++            ret = airoha_led_set_state(phydev, led_id, led_cfg[led_id].en);
++            if (ret != 0) {
++                printf("LED fail to set state, ret %d !\n", ret);
++                return ret;
++            }
++            ret = airoha_led_set_usr_def(phydev, led_id, led_cfg[led_id].pol, led_cfg[led_id].on_cfg, led_cfg[led_id].blk_cfg);
++            if (ret != 0) {
++                printf("LED fail to set default, ret %d !\n", ret);
++                return ret;
++            }
++        }
++    }
++    ret = air_buckpbus_reg_write(phydev, 0xcf8b8, led_gpio);
++    if (ret < 0)
++        return ret;
++    printf("LED initialize OK !\n");
++    return 0;
++}
++#endif /* AIR_LED_SUPPORT */
++
++static char *firmware_buf;
++static int en8811h_load_firmware(struct phy_device *phydev)
++{
++    u32 pbus_value;
++    int ret = 0;
++
++    if (!firmware_buf) {
++        firmware_buf = malloc(EN8811H_MD32_DM_SIZE + EN8811H_MD32_DSP_SIZE);
++        if (!firmware_buf) {
++            printf("[Airoha] cannot allocated buffer for firmware.\n");
++            return -ENOMEM;
++        }
++
++#ifdef CONFIG_PHY_AIROHA_FW_IN_UBI
++        ret = ubi_volume_read("en8811h-fw", firmware_buf, EN8811H_MD32_DM_SIZE + EN8811H_MD32_DSP_SIZE);
++        if (ret) {
++            printf("[Airoha] read firmware from UBI failed.\n");
++            free(firmware_buf);
++            firmware_buf = NULL;
++            return ret;
++        }
++#elif defined(CONFIG_PHY_AIROHA_FW_IN_MMC)
++        struct mmc *mmc = find_mmc_device(0);
++        if (!mmc) {
++            printf("[Airoha] opening MMC device failed.\n");
++            free(firmware_buf);
++            firmware_buf = NULL;
++            return -ENODEV;
++        }
++        if (mmc_init(mmc)) {
++            printf("[Airoha] initializing MMC device failed.\n");
++            free(firmware_buf);
++            firmware_buf = NULL;
++            return -ENODEV;
++        }
++        if (IS_SD(mmc)) {
++            printf("[Airoha] SD card is not supported.\n");
++            free(firmware_buf);
++            firmware_buf = NULL;
++            return -EINVAL;
++        }
++        ret = mmc_set_part_conf(mmc, 1, 2, 2);
++        if (ret) {
++            printf("[Airoha] cannot access eMMC boot1 hw partition.\n");
++            free(firmware_buf);
++            firmware_buf = NULL;
++            return ret;
++        }
++        ret = blk_dread(mmc_get_blk_desc(mmc), 0, 0x120, firmware_buf);
++        mmc_set_part_conf(mmc, 1, 1, 0);
++        if (ret != 0x120) {
++            printf("[Airoha] cannot read firmware from eMMC.\n");
++            free(firmware_buf);
++            firmware_buf = NULL;
++            return -EIO;
++        }
++#else
++#warning EN8811H firmware loading not implemented
++        free(firmware_buf);
++        firmware_buf = NULL;
++        return -EOPNOTSUPP;
++#endif
++    }
++
++    ret = air_buckpbus_reg_write(phydev, 0x0f0018, 0x0);
++    if (ret < 0)
++        return ret;
++    pbus_value = air_buckpbus_reg_read(phydev, 0x800000);
++    pbus_value |= BIT(11);
++    ret = air_buckpbus_reg_write(phydev, 0x800000, pbus_value);
++    if (ret < 0)
++        return ret;
++    /* Download DM */
++    ret = MDIOWriteBuf(phydev, 0x00000000, EN8811H_MD32_DM_SIZE, firmware_buf);
++    if (ret < 0) {
++        printf("[Airoha] MDIOWriteBuf 0x00000000 fail.\n");
++        return ret;
++    }
++    /* Download PM */
++    ret = MDIOWriteBuf(phydev, 0x00100000, EN8811H_MD32_DSP_SIZE, firmware_buf + EN8811H_MD32_DM_SIZE);
++    if (ret < 0) {
++        printf("[Airoha] MDIOWriteBuf 0x00100000 fail.\n");
++        return ret;
++    }
++    pbus_value = air_buckpbus_reg_read(phydev, 0x800000);
++    pbus_value &= ~BIT(11);
++    ret = air_buckpbus_reg_write(phydev, 0x800000, pbus_value);
++    if (ret < 0)
++        return ret;
++    ret = air_buckpbus_reg_write(phydev, 0x0f0018, 0x01);
++    if (ret < 0)
++        return ret;
++    return 0;
++}
++
++static int en8811h_config(struct phy_device *phydev)
++{
++    int ret = 0;
++    int pid1 = 0, pid2 = 0;
++
++    ret = air_pbus_reg_write(phydev, 0xcf928 , 0x0);
++    if (ret < 0)
++        return ret;
++
++    pid1 = phy_read(phydev, MDIO_DEVAD_NONE, MII_PHYSID1);
++    pid2 = phy_read(phydev, MDIO_DEVAD_NONE, MII_PHYSID2);
++    if ((EN8811H_PHY_ID1 != pid1) || (EN8811H_PHY_ID2 != pid2)) {
++        printf("EN8811H does not exist !\n");
++        return -ENODEV;
++    }
++
++    return 0;
++}
++
++static int en8811h_get_autonego(struct phy_device *phydev, int *an)
++{
++    int reg;
++    reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
++    if (reg < 0)
++        return -EINVAL;
++    if (reg & BMCR_ANENABLE)
++        *an = AUTONEG_ENABLE;
++    else
++        *an = AUTONEG_DISABLE;
++    return 0;
++}
++
++static int en8811h_startup(struct phy_device *phydev)
++{
++    ofnode node = phy_get_ofnode(phydev);
++    int ret = 0, lpagb = 0, lpa = 0, common_adv_gb = 0, common_adv = 0, advgb = 0, adv = 0, reg = 0, an = AUTONEG_DISABLE, bmcr = 0, reg_value;
++    int old_link = phydev->link;
++    u32 pbus_value = 0, retry;
++
++    eth_phy_reset(phydev->dev, 1);
++    mdelay(10);
++    eth_phy_reset(phydev->dev, 0);
++    mdelay(1);
++
++    ret = en8811h_load_firmware(phydev);
++    if (ret) {
++        printf("EN8811H load firmware fail.\n");
++        return ret;
++    }
++    retry = MAX_RETRY;
++    do {
++        mdelay(300);
++        reg_value = air_mii_cl45_read(phydev, 0x1e, 0x8009);
++        if (EN8811H_PHY_READY == reg_value) {
++            printf("EN8811H PHY ready!\n");
++            break;
++        }
++        retry--;
++    } while (retry);
++    if (0 == retry) {
++        printf("EN8811H PHY is not ready. (MD32 FW Status reg: 0x%x)\n", reg_value);
++        pbus_value = air_buckpbus_reg_read(phydev, 0x3b3c);
++        printf("Check MD32 FW Version(0x3b3c) : %08x\n", pbus_value);
++        printf("EN8811H initialize fail!\n");
++        return 0;
++    }
++    /* Mode selection*/
++    printf("EN8811H Mode 1 !\n");
++    ret = air_mii_cl45_write(phydev, 0x1e, 0x800c, 0x0);
++    if (ret < 0)
++        return ret;
++    ret = air_mii_cl45_write(phydev, 0x1e, 0x800d, 0x0);
++    if (ret < 0)
++        return ret;
++    ret = air_mii_cl45_write(phydev, 0x1e, 0x800e, 0x1101);
++    if (ret < 0)
++        return ret;
++    ret = air_mii_cl45_write(phydev, 0x1e, 0x800f, 0x0002);
++    if (ret < 0)
++        return ret;
++
++    /* Serdes polarity */
++    pbus_value = air_buckpbus_reg_read(phydev, 0xca0f8);
++    pbus_value &= 0xfffffffc;
++    pbus_value |= ofnode_read_bool(node, "airoha,rx-pol-reverse") ?
++            EN8811H_RX_POLARITY_REVERSE : EN8811H_RX_POLARITY_NORMAL;
++    pbus_value |= ofnode_read_bool(node, "airoha,tx-pol-reverse") ?
++            EN8811H_TX_POLARITY_REVERSE : EN8811H_TX_POLARITY_NORMAL;
++    ret = air_buckpbus_reg_write(phydev, 0xca0f8, pbus_value);
++    if (ret < 0)
++        return ret;
++    pbus_value = air_buckpbus_reg_read(phydev, 0xca0f8);
++    printf("Tx, Rx Polarity(0xca0f8): %08x\n", pbus_value);
++    pbus_value = air_buckpbus_reg_read(phydev, 0x3b3c);
++    printf("MD32 FW Version(0x3b3c) : %08x\n", pbus_value);
++#if defined(AIR_LED_SUPPORT)
++    ret = en8811h_led_init(phydev);
++    if (ret < 0) {
++        printf("en8811h_led_init fail\n");
++    }
++#endif
++    printf("EN8811H initialize OK ! (%s)\n", EN8811H_DRIVER_VERSION);
++
++    ret = genphy_update_link(phydev);
++    if (ret)
++    {
++        printf("ret %d!\n", ret);
++        return ret;
++    }
++
++    ret = genphy_parse_link(phydev);
++    if (ret)
++    {
++        printf("ret %d!\n", ret);
++        return ret;
++    }
++
++    if (old_link && phydev->link)
++       return 0;
++
++    phydev->speed = SPEED_100;
++    phydev->duplex = DUPLEX_FULL;
++    phydev->pause = 0;
++    phydev->asym_pause = 0;
++
++    reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
++    if (reg < 0)
++    {
++        printf("MII_BMSR reg %d!\n", reg);
++        return reg;
++    }
++    reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
++    if (reg < 0)
++    {
++        printf("MII_BMSR reg %d!\n", reg);
++        return reg;
++    }
++    if(reg & BMSR_LSTATUS)
++    {
++        pbus_value = air_buckpbus_reg_read(phydev, 0x109D4);
++        if (0x10 & pbus_value) {
++            phydev->speed = SPEED_2500;
++            phydev->duplex = DUPLEX_FULL;
++        }
++        else
++        {
++            ret = en8811h_get_autonego(phydev, &an);
++            if ((AUTONEG_ENABLE == an) && (0 == ret))
++            {
++                printf("AN mode!\n");
++                printf("SPEED 1000/100!\n");
++                lpagb = phy_read(phydev, MDIO_DEVAD_NONE, MII_STAT1000);
++                if (lpagb < 0 )
++                    return lpagb;
++                advgb = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000);
++                if (adv < 0 )
++                    return adv;
++                common_adv_gb = (lpagb & (advgb << 2));
++
++                lpa = phy_read(phydev, MDIO_DEVAD_NONE, MII_LPA);
++                if (lpa < 0 )
++                    return lpa;
++                adv = phy_read(phydev, MDIO_DEVAD_NONE, MII_ADVERTISE);
++                if (adv < 0 )
++                    return adv;
++                common_adv = (lpa & adv);
++
++                phydev->speed = SPEED_10;
++                phydev->duplex = DUPLEX_HALF;
++                if (common_adv_gb & (LPA_1000FULL | LPA_1000HALF))
++                {
++                    phydev->speed = SPEED_1000;
++                    if (common_adv_gb & LPA_1000FULL)
++
++                        phydev->duplex = DUPLEX_FULL;
++                }
++                else if (common_adv & (LPA_100FULL | LPA_100HALF))
++                {
++                    phydev->speed = SPEED_100;
++                    if (common_adv & LPA_100FULL)
++                        phydev->duplex = DUPLEX_FULL;
++                }
++                else
++                {
++                    if (common_adv & LPA_10FULL)
++                        phydev->duplex = DUPLEX_FULL;
++                }
++            }
++            else
++            {
++                printf("Force mode!\n");
++                bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
++
++                if (bmcr < 0)
++                    return bmcr;
++
++                if (bmcr & BMCR_FULLDPLX)
++                    phydev->duplex = DUPLEX_FULL;
++                else
++                    phydev->duplex = DUPLEX_HALF;
++
++                if (bmcr & BMCR_SPEED1000)
++                    phydev->speed = SPEED_1000;
++                else if (bmcr & BMCR_SPEED100)
++                    phydev->speed = SPEED_100;
++                else
++                    phydev->speed = SPEED_100;
++            }
++        }
++    }
++
++    return ret;
++}
++
++#if AIR_UBOOT_REVISION > 0x202303
++U_BOOT_PHY_DRIVER(en8811h) = {
++    .name = "Airoha EN8811H",
++    .uid = EN8811H_PHY_ID,
++    .mask = 0x0ffffff0,
++    .config = &en8811h_config,
++    .startup = &en8811h_startup,
++    .shutdown = &genphy_shutdown,
++};
++#else
++static struct phy_driver AIR_EN8811H_driver = {
++    .name = "Airoha EN8811H",
++    .uid = EN8811H_PHY_ID,
++    .mask = 0x0ffffff0,
++    .config = &en8811h_config,
++    .startup = &en8811h_startup,
++    .shutdown = &genphy_shutdown,
++};
++
++int phy_air_en8811h_init(void)
++{
++    phy_register(&AIR_EN8811H_driver);
++    return 0;
++}
++#endif
+--- /dev/null
++++ b/drivers/net/phy/air_en8811h.h
+@@ -0,0 +1,163 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++/*************************************************
++ * FILE NAME:  air_en8811h.h
++ * PURPOSE:
++ *      EN8811H PHY Driver for Uboot
++ * NOTES:
++ *
++ *  Copyright (C) 2023 Airoha Technology Corp.
++ *************************************************/
++
++#ifndef __EN8811H_H
++#define __EN8811H_H
++
++#define AIR_UBOOT_REVISION ((((U_BOOT_VERSION_NUM / 1000) % 10) << 20) | \
++			(((U_BOOT_VERSION_NUM / 100) % 10) << 16) | \
++			(((U_BOOT_VERSION_NUM / 10) % 10) << 12) | \
++			((U_BOOT_VERSION_NUM % 10) << 8) | \
++			(((U_BOOT_VERSION_NUM_PATCH / 10) % 10) << 4) | \
++			((U_BOOT_VERSION_NUM_PATCH % 10) << 0))
++
++#define EN8811H_PHY_ID1             0x03a2
++#define EN8811H_PHY_ID2             0xa411
++#define EN8811H_PHY_ID              ((EN8811H_PHY_ID1 << 16) | EN8811H_PHY_ID2)
++#define EN8811H_SPEED_2500          0x03
++#define EN8811H_PHY_READY           0x02
++#define MAX_RETRY                   5
++
++#define EN8811H_MD32_DM_SIZE   0x4000
++#define EN8811H_MD32_DSP_SIZE  0x20000
++
++#define EN8811H_TX_POLARITY_NORMAL   0x1
++#define EN8811H_TX_POLARITY_REVERSE  0x0
++
++#define EN8811H_RX_POLARITY_NORMAL  (0x0 << 1)
++#define EN8811H_RX_POLARITY_REVERSE (0x1 << 1)
++
++#ifndef BIT
++#define BIT(nr)			(1UL << (nr))
++#endif
++
++/* CL45 MDIO control */
++#define MII_MMD_ACC_CTL_REG         0x0d
++#define MII_MMD_ADDR_DATA_REG       0x0e
++#define MMD_OP_MODE_DATA            BIT(14)
++/* MultiGBASE-T AN register */
++#define MULTIG_ANAR_2500M           (0x0080)
++#define MULTIG_LPAR_2500M           (0x0020)
++
++#define EN8811H_DRIVER_VERSION  "v1.0.4"
++
++/************************************************************
++ * For reference only
++ * LED0 Link 2500/Blink 2500 TxRx (GPIO5)    <-> BASE_T_LED0,
++ * LED1 Link 1000/Blink 1000 TxRx (GPIO4)    <-> BASE_T_LED1,
++ * LED2 Link 100/Blink 100 TxRx   (GPIO3)    <-> BASE_T_LED2,
++ ************************************************************/
++/* User-defined.B */
++#define AIR_LED0_ON      (LED_ON_EVT_LINK_2500M)
++#define AIR_LED0_BLK     (LED_BLK_EVT_2500M_TX_ACT | LED_BLK_EVT_2500M_RX_ACT)
++#define AIR_LED1_ON      (LED_ON_EVT_LINK_1000M)
++#define AIR_LED1_BLK    (LED_BLK_EVT_1000M_TX_ACT | LED_BLK_EVT_1000M_RX_ACT)
++#define AIR_LED2_ON      (LED_ON_EVT_LINK_100M)
++#define AIR_LED2_BLK     (LED_BLK_EVT_100M_TX_ACT | LED_BLK_EVT_100M_RX_ACT)
++/* User-defined.E */
++
++#define LED_ON_CTRL(i)              (0x024 + ((i)*2))
++#define LED_ON_EN                   (1 << 15)
++#define LED_ON_POL                  (1 << 14)
++#define LED_ON_EVT_MASK             (0x1ff)
++/* LED ON Event Option.B */
++#define LED_ON_EVT_LINK_2500M       (1 << 8)
++#define LED_ON_EVT_FORCE            (1 << 6)
++#define LED_ON_EVT_HDX              (1 << 5)
++#define LED_ON_EVT_FDX              (1 << 4)
++#define LED_ON_EVT_LINK_DOWN        (1 << 3)
++#define LED_ON_EVT_LINK_100M        (1 << 1)
++#define LED_ON_EVT_LINK_1000M       (1 << 0)
++/* LED ON Event Option.E */
++
++#define LED_BLK_CTRL(i)             (0x025 + ((i)*2))
++#define LED_BLK_EVT_MASK            (0xfff)
++/* LED Blinking Event Option.B*/
++#define LED_BLK_EVT_2500M_RX_ACT    (1 << 11)
++#define LED_BLK_EVT_2500M_TX_ACT    (1 << 10)
++#define LED_BLK_EVT_FORCE           (1 << 9)
++#define LED_BLK_EVT_100M_RX_ACT     (1 << 3)
++#define LED_BLK_EVT_100M_TX_ACT     (1 << 2)
++#define LED_BLK_EVT_1000M_RX_ACT    (1 << 1)
++#define LED_BLK_EVT_1000M_TX_ACT    (1 << 0)
++/* LED Blinking Event Option.E*/
++#define LED_ENABLE                  1
++#define LED_DISABLE                 0
++
++#define EN8811H_LED_COUNT       3
++
++#define LED_BCR                     (0x021)
++#define LED_BCR_EXT_CTRL            (1 << 15)
++#define LED_BCR_CLK_EN              (1 << 3)
++#define LED_BCR_TIME_TEST           (1 << 2)
++#define LED_BCR_MODE_MASK           (3)
++#define LED_BCR_MODE_DISABLE        (0)
++#define LED_BCR_MODE_2LED           (1)
++#define LED_BCR_MODE_3LED_1         (2)
++#define LED_BCR_MODE_3LED_2         (3)
++
++#define LED_ON_DUR                  (0x022)
++#define LED_ON_DUR_MASK             (0xffff)
++
++#define LED_BLK_DUR                 (0x023)
++#define LED_BLK_DUR_MASK            (0xffff)
++
++#define LED_GPIO_SEL_MASK           0x7FFFFFF
++
++#define UNIT_LED_BLINK_DURATION     1024
++
++#define INVALID_DATA                0xffff
++#define PBUS_INVALID_DATA           0xffffffff
++
++struct air_base_t_led_cfg_s {
++    u16 en;
++    u16 gpio;
++    u16 pol;
++    u16 on_cfg;
++    u16 blk_cfg;
++};
++
++enum {
++    AIR_LED2_GPIO3 = 3,
++    AIR_LED1_GPIO4,
++    AIR_LED0_GPIO5,
++    AIR_LED_LAST
++};
++
++enum {
++    AIR_BASE_T_LED0,
++    AIR_BASE_T_LED1,
++    AIR_BASE_T_LED2,
++    AIR_BASE_T_LED3
++};
++
++enum {
++    AIR_LED_BLK_DUR_32M,
++    AIR_LED_BLK_DUR_64M,
++    AIR_LED_BLK_DUR_128M,
++    AIR_LED_BLK_DUR_256M,
++    AIR_LED_BLK_DUR_512M,
++    AIR_LED_BLK_DUR_1024M,
++    AIR_LED_BLK_DUR_LAST
++};
++
++enum {
++    AIR_ACTIVE_LOW,
++    AIR_ACTIVE_HIGH,
++};
++
++enum {
++    AIR_LED_MODE_DISABLE,
++    AIR_LED_MODE_USER_DEFINE,
++    AIR_LED_MODE_LAST
++};
++
++#endif /* End of __EN8811H_MD32_H */
++
+--- a/drivers/net/eth-phy-uclass.c
++++ b/drivers/net/eth-phy-uclass.c
+@@ -155,7 +155,7 @@ static int eth_phy_of_to_plat(struct ude
+ 	return 0;
+ }
+ 
+-static void eth_phy_reset(struct udevice *dev, int value)
++void eth_phy_reset(struct udevice *dev, int value)
+ {
+ 	struct eth_phy_device_priv *uc_priv = dev_get_uclass_priv(dev);
+ 	u32 delay;
+--- a/include/eth_phy.h
++++ b/include/eth_phy.h
+@@ -14,5 +14,6 @@ int eth_phy_binds_nodes(struct udevice *
+ int eth_phy_set_mdio_bus(struct udevice *eth_dev, struct mii_dev *mdio_bus);
+ struct mii_dev *eth_phy_get_mdio_bus(struct udevice *eth_dev);
+ int eth_phy_get_addr(struct udevice *dev);
++void eth_phy_reset(struct udevice *dev, int value);
+ 
+ #endif
diff --git a/package/boot/uboot-mediatek/patches/200-cmd-add-imsz-and-imszb.patch b/package/boot/uboot-mediatek/patches/200-cmd-add-imsz-and-imszb.patch
index ae7623086e4475..28175e02e87fd0 100644
--- a/package/boot/uboot-mediatek/patches/200-cmd-add-imsz-and-imszb.patch
+++ b/package/boot/uboot-mediatek/patches/200-cmd-add-imsz-and-imszb.patch
@@ -1,6 +1,6 @@
 --- a/cmd/bootm.c
 +++ b/cmd/bootm.c
-@@ -259,6 +259,67 @@ U_BOOT_CMD(
+@@ -245,6 +245,67 @@ U_BOOT_CMD(
  /* iminfo - print header info for a requested image */
  /*******************************************************************/
  #if defined(CONFIG_CMD_IMI)
@@ -120,7 +120,7 @@
  		   int arch, int ph_type, int bootstage_id,
 --- a/include/image.h
 +++ b/include/image.h
-@@ -1047,6 +1047,7 @@ int fit_parse_subimage(const char *spec,
+@@ -1049,6 +1049,7 @@ int fit_parse_subimage(const char *spec,
  		ulong *addr, const char **image_name);
  
  int fit_get_subimage_count(const void *fit, int images_noffset);
diff --git a/package/boot/uboot-mediatek/patches/220-cmd-env-readmem.patch b/package/boot/uboot-mediatek/patches/220-cmd-env-readmem.patch
index d91b9904cbd0e9..7bf87ef7b5aebf 100644
--- a/package/boot/uboot-mediatek/patches/220-cmd-env-readmem.patch
+++ b/package/boot/uboot-mediatek/patches/220-cmd-env-readmem.patch
@@ -1,6 +1,6 @@
 --- a/cmd/Kconfig
 +++ b/cmd/Kconfig
-@@ -602,6 +602,12 @@ config CMD_ENV_EXISTS
+@@ -622,6 +622,12 @@ config CMD_ENV_EXISTS
  	  Check if a variable is defined in the environment for use in
  	  shell scripting.
  
@@ -15,7 +15,7 @@
  	help
 --- a/cmd/nvedit.c
 +++ b/cmd/nvedit.c
-@@ -408,6 +408,60 @@ int do_env_ask(struct cmd_tbl *cmdtp, in
+@@ -385,6 +385,60 @@ int do_env_ask(struct cmd_tbl *cmdtp, in
  }
  #endif
  
@@ -76,7 +76,7 @@
  #if defined(CONFIG_CMD_ENV_CALLBACK)
  static int print_static_binding(const char *var_name, const char *callback_name,
  				void *priv)
-@@ -1228,6 +1282,9 @@ static struct cmd_tbl cmd_env_sub[] = {
+@@ -1201,6 +1255,9 @@ static struct cmd_tbl cmd_env_sub[] = {
  	U_BOOT_CMD_MKENT(load, 1, 0, do_env_load, "", ""),
  #endif
  	U_BOOT_CMD_MKENT(print, CONFIG_SYS_MAXARGS, 1, do_env_print, "", ""),
@@ -86,7 +86,7 @@
  #if defined(CONFIG_CMD_RUN)
  	U_BOOT_CMD_MKENT(run, CONFIG_SYS_MAXARGS, 1, do_run, "", ""),
  #endif
-@@ -1319,6 +1376,9 @@ static char env_help_text[] =
+@@ -1284,6 +1341,9 @@ U_BOOT_LONGHELP(env,
  #if defined(CONFIG_CMD_NVEDIT_EFI)
  	"env print -e [-guid guid] [-n] [name ...] - print UEFI environment\n"
  #endif
@@ -96,7 +96,7 @@
  #if defined(CONFIG_CMD_RUN)
  	"env run var [...] - run commands in an environment variable\n"
  #endif
-@@ -1428,6 +1488,17 @@ U_BOOT_CMD(
+@@ -1392,6 +1452,17 @@ U_BOOT_CMD(
  );
  #endif
  
diff --git a/package/boot/uboot-mediatek/patches/230-cmd-add-pstore-check.patch b/package/boot/uboot-mediatek/patches/230-cmd-add-pstore-check.patch
index d0abcb1acc2b22..48556937bd8bb7 100644
--- a/package/boot/uboot-mediatek/patches/230-cmd-add-pstore-check.patch
+++ b/package/boot/uboot-mediatek/patches/230-cmd-add-pstore-check.patch
@@ -67,7 +67,7 @@
  	U_BOOT_CMD_MKENT(display, 3, 0, pstore_display, "", ""),
  	U_BOOT_CMD_MKENT(save, 4, 0, pstore_save, "", ""),
  };
-@@ -560,6 +613,8 @@ U_BOOT_CMD(pstore, 10, 0, do_pstore,
+@@ -566,6 +619,8 @@ U_BOOT_CMD(pstore, 10, 0, do_pstore,
  	   "  'pmsg-size' is the size of the user space logs record.\n"
  	   "  'ecc-size' enables/disables ECC support and specifies ECC buffer size in\n"
  	   "  bytes (0 disables it, 1 is a special value, means 16 bytes ECC).\n"
diff --git a/package/boot/uboot-mediatek/patches/250-fix-mmc-erase-timeout.patch b/package/boot/uboot-mediatek/patches/250-fix-mmc-erase-timeout.patch
new file mode 100644
index 00000000000000..fd5fdd814b8c35
--- /dev/null
+++ b/package/boot/uboot-mediatek/patches/250-fix-mmc-erase-timeout.patch
@@ -0,0 +1,11 @@
+--- a/drivers/mmc/mmc_write.c
++++ b/drivers/mmc/mmc_write.c
+@@ -80,7 +80,7 @@ ulong mmc_berase(struct blk_desc *block_
+ 	u32 start_rem, blkcnt_rem, erase_args = 0;
+ 	struct mmc *mmc = find_mmc_device(dev_num);
+ 	lbaint_t blk = 0, blk_r = 0;
+-	int timeout_ms = 1000;
++	int timeout_ms = blkcnt;
+ 
+ 	if (!mmc)
+ 		return -1;
diff --git a/package/boot/uboot-mediatek/patches/300-mt7623-fix-mmc-get-env-dev.patch b/package/boot/uboot-mediatek/patches/300-mt7623-fix-mmc-get-env-dev.patch
new file mode 100644
index 00000000000000..86c48badda9706
--- /dev/null
+++ b/package/boot/uboot-mediatek/patches/300-mt7623-fix-mmc-get-env-dev.patch
@@ -0,0 +1,46 @@
+--- a/board/mediatek/mt7623/mt7623_rfb.c
++++ b/board/mediatek/mt7623/mt7623_rfb.c
+@@ -5,6 +5,7 @@
+ 
+ #include <common.h>
+ #include <mmc.h>
++#include <part.h>
+ #include <asm/global_data.h>
+ 
+ DECLARE_GLOBAL_DATA_PTR;
+@@ -22,8 +23,9 @@ int mmc_get_boot_dev(void)
+ {
+ 	int g_mmc_devid = -1;
+ 	char *uflag = (char *)0x81DFFFF0;
++	struct blk_desc *desc;
+ 
+-	if (!find_mmc_device(1))
++	if (blk_get_device_by_str("mmc", "1", &desc) < 0)
+ 		return 0;
+ 
+ 	if (strncmp(uflag,"eMMC",4)==0) {
+@@ -38,6 +40,23 @@ int mmc_get_boot_dev(void)
+ 
+ int mmc_get_env_dev(void)
+ {
+-	return mmc_get_boot_dev();
++	struct udevice *dev;
++	const char *mmcdev;
++
++	switch (mmc_get_boot_dev()) {
++	case 0:
++		mmcdev = "mmc@11230000";
++		break;
++	case 1:
++		mmcdev = "mmc@11240000";
++		break;
++	default:
++		return -1;
++	}
++
++	if (uclass_get_device_by_name(UCLASS_MMC, mmcdev, &dev))
++		return -1;
++
++	return dev_seq(dev);
+ }
+ #endif
diff --git a/package/boot/uboot-mediatek/patches/302-mt7623-generic-reset-button-ignore-env.patch b/package/boot/uboot-mediatek/patches/302-mt7623-generic-reset-button-ignore-env.patch
index 928dfe8428a3de..b8d89058a2e93a 100644
--- a/package/boot/uboot-mediatek/patches/302-mt7623-generic-reset-button-ignore-env.patch
+++ b/package/boot/uboot-mediatek/patches/302-mt7623-generic-reset-button-ignore-env.patch
@@ -1,6 +1,6 @@
 --- a/board/mediatek/mt7623/mt7623_rfb.c
 +++ b/board/mediatek/mt7623/mt7623_rfb.c
-@@ -4,8 +4,17 @@
+@@ -4,9 +4,18 @@
   */
  
  #include <common.h>
@@ -9,6 +9,7 @@
 +#include <env.h>
 +#include <init.h>
  #include <mmc.h>
+ #include <part.h>
  #include <asm/global_data.h>
 +#include <linux/delay.h>
 +
@@ -18,8 +19,8 @@
  
  DECLARE_GLOBAL_DATA_PTR;
  
-@@ -41,3 +50,25 @@ int mmc_get_env_dev(void)
- 	return mmc_get_boot_dev();
+@@ -60,3 +69,25 @@ int mmc_get_env_dev(void)
+ 	return dev_seq(dev);
  }
  #endif
 +
diff --git a/package/boot/uboot-mediatek/patches/310-mt7988-select-rootdisk.patch b/package/boot/uboot-mediatek/patches/310-mt7988-select-rootdisk.patch
new file mode 100644
index 00000000000000..28d7e0a3f6e5cb
--- /dev/null
+++ b/package/boot/uboot-mediatek/patches/310-mt7988-select-rootdisk.patch
@@ -0,0 +1,67 @@
+--- a/board/mediatek/mt7988/mt7988_rfb.c
++++ b/board/mediatek/mt7988/mt7988_rfb.c
+@@ -11,7 +11,9 @@
+ #include <env.h>
+ #include <init.h>
+ #include <asm/global_data.h>
++#include <asm/io.h>
+ #include <linux/delay.h>
++#include <linux/libfdt.h>
+ 
+ #ifndef CONFIG_RESET_BUTTON_LABEL
+ #define CONFIG_RESET_BUTTON_LABEL "reset"
+@@ -44,3 +46,54 @@ int board_late_init(void)
+ 	env_relocate();
+ 	return 0;
+ }
++
++#define	MT7988_BOOT_NOR		0
++#define	MT7988_BOOT_SPIM_NAND	1
++#define	MT7988_BOOT_EMMC	2
++#define	MT7988_BOOT_SNFI_NAND	3
++
++int ft_system_setup(void *blob, struct bd_info *bd)
++{
++	const u32 *media_handle_p;
++	int chosen, len, ret;
++	const char *media;
++	u32 media_handle;
++
++	switch ((readl(0x1001f6f0) & 0xc00) >> 10) {
++	case MT7988_BOOT_NOR:
++		media = "rootdisk-nor";
++		break
++		;;
++	case MT7988_BOOT_SPIM_NAND:
++		media = "rootdisk-spim-nand";
++		break
++		;;
++	case MT7988_BOOT_EMMC:
++		media = "rootdisk-emmc";
++		break
++		;;
++	case MT7988_BOOT_SNFI_NAND:
++		media = "rootdisk-sd";
++		break
++		;;
++	}
++
++	chosen = fdt_path_offset(blob, "/chosen");
++	if (chosen <= 0)
++		return 0;
++
++	media_handle_p = fdt_getprop(blob, chosen, media, &len);
++	if (media_handle_p <= 0 || len != 4)
++		return 0;
++
++	media_handle = *media_handle_p;
++	ret = fdt_setprop(blob, chosen, "rootdisk", &media_handle, sizeof(media_handle));
++	if (ret) {
++		printf("cannot set media phandle %s as rootdisk /chosen node\n", media);
++		return ret;
++	}
++
++	printf("set /chosen/rootdisk to bootrom media: %s (phandle 0x%08x)\n", media, fdt32_to_cpu(media_handle));
++
++	return 0;
++}
diff --git a/package/boot/uboot-mediatek/patches/311-mt7986-select-roodisk.patch b/package/boot/uboot-mediatek/patches/311-mt7986-select-roodisk.patch
new file mode 100644
index 00000000000000..33121627655d4d
--- /dev/null
+++ b/package/boot/uboot-mediatek/patches/311-mt7986-select-roodisk.patch
@@ -0,0 +1,67 @@
+--- a/board/mediatek/mt7986/mt7986_rfb.c
++++ b/board/mediatek/mt7986/mt7986_rfb.c
+@@ -11,7 +11,9 @@
+ #include <env.h>
+ #include <init.h>
+ #include <asm/global_data.h>
++#include <asm/io.h>
+ #include <linux/delay.h>
++#include <linux/libfdt.h>
+ 
+ #ifndef CONFIG_RESET_BUTTON_LABEL
+ #define CONFIG_RESET_BUTTON_LABEL "reset"
+@@ -83,3 +85,54 @@ int board_nmbm_init(void)
+ 
+ 	return 0;
+ }
++
++#define	MT7986_BOOT_NOR		0
++#define	MT7986_BOOT_SPIM_NAND	1
++#define	MT7986_BOOT_EMMC	2
++#define	MT7986_BOOT_SNFI_NAND	3
++
++int ft_system_setup(void *blob, struct bd_info *bd)
++{
++	const u32 *media_handle_p;
++	int chosen, len, ret;
++	const char *media;
++	u32 media_handle;
++
++	switch ((readl(0x1001f6f0) & 0x300) >> 8) {
++	case MT7986_BOOT_NOR:
++		media = "rootdisk-nor";
++		break
++		;;
++	case MT7986_BOOT_SPIM_NAND:
++		media = "rootdisk-spim-nand";
++		break
++		;;
++	case MT7986_BOOT_EMMC:
++		media = "rootdisk-emmc";
++		break
++		;;
++	case MT7986_BOOT_SNFI_NAND:
++		media = "rootdisk-sd";
++		break
++		;;
++	}
++
++	chosen = fdt_path_offset(blob, "/chosen");
++	if (chosen <= 0)
++		return 0;
++
++	media_handle_p = fdt_getprop(blob, chosen, media, &len);
++	if (media_handle_p <= 0 || len != 4)
++		return 0;
++
++	media_handle = *media_handle_p;
++	ret = fdt_setprop(blob, chosen, "rootdisk", &media_handle, sizeof(media_handle));
++	if (ret) {
++		printf("cannot set media phandle %s as rootdisk /chosen node\n", media);
++		return ret;
++	}
++
++	printf("set /chosen/rootdisk to bootrom media: %s (phandle 0x%08x)\n", media, fdt32_to_cpu(media_handle));
++
++	return 0;
++}
diff --git a/package/boot/uboot-mediatek/patches/312-mt7622-select-rootdisk.patch b/package/boot/uboot-mediatek/patches/312-mt7622-select-rootdisk.patch
new file mode 100644
index 00000000000000..70cbf6b46300e2
--- /dev/null
+++ b/package/boot/uboot-mediatek/patches/312-mt7622-select-rootdisk.patch
@@ -0,0 +1,141 @@
+--- a/board/mediatek/mt7622/mt7622_rfb.c
++++ b/board/mediatek/mt7622/mt7622_rfb.c
+@@ -11,7 +11,9 @@
+ #include <env.h>
+ #include <init.h>
+ #include <asm/global_data.h>
++#include <asm/io.h>
+ #include <linux/delay.h>
++#include <linux/libfdt.h>
+ 
+ #ifndef CONFIG_RESET_BUTTON_LABEL
+ #define CONFIG_RESET_BUTTON_LABEL "reset"
+@@ -22,10 +24,43 @@
+ #include <nmbm/nmbm.h>
+ #include <nmbm/nmbm-mtd.h>
+ 
++#define MT7622_TOPRGUSTRAP_PAR			0x10212060
++#define MT7622_BOOT_SEQ_MASK			0x18
++#define MT7622_BOOT_SEQ_SHIFT			3
++#define MT7622_BOOT_SEQ_NOR_EMMC_SDXC		0x0
++#define MT7622_BOOT_SEQ_SPI_NAND_EMMC_SDXC	0x1
++#define MT7622_BOOT_SEQ_NAND_EMMC_SDXC		0x2
++#define MT7622_BOOT_SEQ_SDXC_EMMC_NAND		0x3
++
++#define MT7622_GPIO_MODE0			0x10211300
++#define MT7622_GPIO_NAND_MODE_MASK		0x00f00000
++#define MT7622_GPIO_NAND_MODE_SHIFT		20
++#define MT7622_GPIO_NAND_MODE_EMMC		0x2
++#define MT7622_GPIO_RGMII_MODE_MASK		0x0000f000
++#define MT7622_GPIO_RGMII_MODE_SHIFT		12
++#define MT7622_GPIO_RGMII_MODE_SDCX		0x2
++#define MT7622_GPIO_SPI_MODE_MASK		0x00000f00
++#define MT7622_GPIO_SPI_MODE_SHIFT		8
++#define MT7622_GPIO_SPI_MODE_NAND		0x2
++
++#define MT7622_MSDC_INT				0x1124000C
++#define MT7622_MSDC_INT_BD_CS_ERR		0x200
++
+ DECLARE_GLOBAL_DATA_PTR;
+ 
++static int	gpio_mode0;
++static int	msdc_int;
++
+ int board_init(void)
+ {
++	/*
++	 * Save content of GPIO_MODE0 as left behind by the BootROM.
++	 * Also grab MSDC1 INT status to see if BootROM has been reading
++	 * from SD card.
++	 * Together this will allow to infer the device used for booting.
++	 */
++	gpio_mode0 = readl(MT7622_GPIO_MODE0);
++	msdc_int = readl(MT7622_MSDC_INT);
+ 	return 0;
+ }
+ 
+@@ -83,3 +118,84 @@ int board_nmbm_init(void)
+ 
+ 	return 0;
+ }
++
++int ft_system_setup(void *blob, struct bd_info *bd)
++{
++	bool pinctrl_set_mmc = false;
++	bool pinctrl_set_snfi = false;
++	bool pinctrl_set_emmc = false;
++	bool msdc_bd_cs_err = false;
++
++	const u32 *media_handle_p;
++	int chosen, len, ret;
++	const char *media;
++	u32 media_handle, strap;
++
++	if ((gpio_mode0 & MT7622_GPIO_RGMII_MODE_MASK) >>
++	    MT7622_GPIO_RGMII_MODE_SHIFT == MT7622_GPIO_RGMII_MODE_SDCX)
++		pinctrl_set_mmc = true;
++
++	if ((gpio_mode0 & MT7622_GPIO_SPI_MODE_MASK) >>
++	    MT7622_GPIO_SPI_MODE_SHIFT == MT7622_GPIO_SPI_MODE_NAND)
++		pinctrl_set_snfi = true;
++
++	if ((gpio_mode0 & MT7622_GPIO_NAND_MODE_MASK) >>
++	    MT7622_GPIO_NAND_MODE_SHIFT == MT7622_GPIO_NAND_MODE_EMMC)
++		pinctrl_set_emmc = true;
++
++	if (msdc_int & MT7622_MSDC_INT_BD_CS_ERR)
++		msdc_bd_cs_err = true;
++
++	strap = readl(MT7622_TOPRGUSTRAP_PAR);
++	strap &= MT7622_BOOT_SEQ_MASK;
++	strap >>= MT7622_BOOT_SEQ_SHIFT;
++	switch (strap) {
++	case MT7622_BOOT_SEQ_NOR_EMMC_SDXC:
++		if (!pinctrl_set_emmc)
++			media = "rootdisk-nor";
++		else if (pinctrl_set_mmc)
++			media = "rootdisk-emmc";
++		else
++			media = "rootdisk-sd";
++		break
++		;;
++	case MT7622_BOOT_SEQ_SPI_NAND_EMMC_SDXC:
++		if (pinctrl_set_snfi)
++			media = "rootdisk-snfi";
++		else if (pinctrl_set_emmc)
++			media = "rootdisk-emmc";
++		else
++			media = "rootdisk-sd";
++		break
++		;;
++	case MT7622_BOOT_SEQ_NAND_EMMC_SDXC:
++	case MT7622_BOOT_SEQ_SDXC_EMMC_NAND:
++		if (!pinctrl_set_emmc && pinctrl_set_mmc)
++			media = "rootdisk-nand";
++		else if (pinctrl_set_emmc)
++			media = "rootdisk-emmc";
++		else
++			media = "rootdisk-sd";
++		break
++		;;
++	}
++
++	chosen = fdt_path_offset(blob, "/chosen");
++	if (chosen <= 0)
++		return 0;
++
++	media_handle_p = fdt_getprop(blob, chosen, media, &len);
++	if (media_handle_p <= 0 || len != 4)
++		return 0;
++
++	media_handle = *media_handle_p;
++	ret = fdt_setprop(blob, chosen, "rootdisk", &media_handle, sizeof(media_handle));
++	if (ret) {
++		printf("cannot set media phandle %s as rootdisk /chosen node\n", media);
++		return ret;
++	}
++
++	printf("set /chosen/rootdisk to bootrom media: %s (phandle 0x%08x)\n", media, fdt32_to_cpu(media_handle));
++
++	return 0;
++}
diff --git a/package/boot/uboot-mediatek/patches/313-mt7623-select-rootdisk.patch b/package/boot/uboot-mediatek/patches/313-mt7623-select-rootdisk.patch
new file mode 100644
index 00000000000000..0089307bbd6b84
--- /dev/null
+++ b/package/boot/uboot-mediatek/patches/313-mt7623-select-rootdisk.patch
@@ -0,0 +1,46 @@
+--- a/board/mediatek/mt7623/mt7623_rfb.c
++++ b/board/mediatek/mt7623/mt7623_rfb.c
+@@ -91,3 +91,43 @@ int board_late_init(void)
+ 	env_relocate();
+ 	return 0;
+ }
++
++int ft_system_setup(void *blob, struct bd_info *bd)
++{
++	const u32 *media_handle_p;
++	int chosen, len, ret;
++	const char *media;
++	u32 media_handle;
++
++#ifdef CONFIG_MMC
++	switch (mmc_get_boot_dev()) {
++	case 0:
++		media = "rootdisk-emmc";
++		break
++		;;
++	case 1:
++		media = "rootdisk-sd";
++		break
++		;;
++	}
++
++	chosen = fdt_path_offset(blob, "/chosen");
++	if (chosen <= 0)
++		return 0;
++
++	media_handle_p = fdt_getprop(blob, chosen, media, &len);
++	if (media_handle_p <= 0 || len != 4)
++		return 0;
++
++	media_handle = *media_handle_p;
++	ret = fdt_setprop(blob, chosen, "rootdisk", &media_handle, sizeof(media_handle));
++	if (ret) {
++		printf("cannot set media phandle %s as rootdisk /chosen node\n", media);
++		return ret;
++	}
++
++	printf("set /chosen/rootdisk to bootrom media: %s (phandle 0x%08x)\n", media, fdt32_to_cpu(media_handle));
++#endif
++
++	return 0;
++}
diff --git a/package/boot/uboot-mediatek/patches/400-update-bpir2-defconfig.patch b/package/boot/uboot-mediatek/patches/400-update-bpir2-defconfig.patch
index 7ebe5c0fc7a6d9..ab3424e6b591ba 100644
--- a/package/boot/uboot-mediatek/patches/400-update-bpir2-defconfig.patch
+++ b/package/boot/uboot-mediatek/patches/400-update-bpir2-defconfig.patch
@@ -1,6 +1,6 @@
 --- a/configs/mt7623n_bpir2_defconfig
 +++ b/configs/mt7623n_bpir2_defconfig
-@@ -7,35 +7,105 @@ CONFIG_SYS_MALLOC_F_LEN=0x4000
+@@ -7,34 +7,106 @@ CONFIG_SYS_MALLOC_F_LEN=0x4000
  CONFIG_NR_DRAM_BANKS=1
  CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
  CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x81ffff10
@@ -8,19 +8,17 @@
 +CONFIG_ENV_SIZE=0x10000
  CONFIG_ENV_OFFSET=0x100000
  CONFIG_DEFAULT_DEVICE_TREE="mt7623n-bananapi-bpi-r2"
--CONFIG_SYS_PROMPT="U-Boot> "
-+CONFIG_USE_DEFAULT_ENV_FILE=y
-+CONFIG_SYS_PROMPT="MT7623> "
  CONFIG_TARGET_MT7623=y
  CONFIG_SYS_LOAD_ADDR=0x84000000
  CONFIG_FIT=y
--CONFIG_FIT_VERBOSE=y
+ CONFIG_FIT_VERBOSE=y
 +CONFIG_FIT_ENABLE_SHA256_SUPPORT=y
 +CONFIG_LED=y
 +CONFIG_LED_BLINK=y
 +CONFIG_LED_GPIO=y
 +CONFIG_LOGLEVEL=7
 +CONFIG_LOG=y
++CONFIG_OF_SYSTEM_SETUP=y
 +CONFIG_AUTOBOOT_KEYED=y
 +CONFIG_AUTOBOOT_MENU_SHOW=y
 +CONFIG_BOARD_LATE_INIT=y
@@ -38,6 +36,9 @@
 +CONFIG_CFB_CONSOLE_ANSI=y
 +CONFIG_CMD_ENV_FLAGS=y
  # CONFIG_DISPLAY_BOARDINFO is not set
+-CONFIG_SYS_PROMPT="U-Boot> "
++CONFIG_USE_DEFAULT_ENV_FILE=y
++CONFIG_SYS_PROMPT="MT7623> "
  CONFIG_SYS_MAXARGS=8
  CONFIG_SYS_PBSIZE=1049
  CONFIG_SYS_BOOTM_LEN=0x4000000
@@ -70,7 +71,6 @@
  CONFIG_CMD_MMC=y
  CONFIG_CMD_READ=y
 -# CONFIG_CMD_SETEXPR is not set
- # CONFIG_CMD_NFS is not set
 +CONFIG_CMD_SF_TEST=y
 +CONFIG_CMD_PING=y
 +CONFIG_CMD_PXE=y
@@ -111,7 +111,7 @@
  CONFIG_USE_IPADDR=y
  CONFIG_IPADDR="192.168.1.1"
  CONFIG_USE_SERVERIP=y
-@@ -47,6 +117,12 @@ CONFIG_CLK=y
+@@ -46,6 +118,12 @@ CONFIG_CLK=y
  CONFIG_SUPPORT_EMMC_BOOT=y
  CONFIG_MMC_HS400_SUPPORT=y
  CONFIG_MMC_MTK=y
@@ -124,7 +124,7 @@
  CONFIG_PHY_FIXED=y
  CONFIG_MEDIATEK_ETH=y
  CONFIG_PINCTRL=y
-@@ -56,10 +132,13 @@ CONFIG_POWER_DOMAIN=y
+@@ -55,10 +133,13 @@ CONFIG_POWER_DOMAIN=y
  CONFIG_MTK_POWER_DOMAIN=y
  CONFIG_DM_SERIAL=y
  CONFIG_MTK_SERIAL=y
@@ -140,7 +140,7 @@
  # CONFIG_EFI_GRUB_ARM32_WORKAROUND is not set
 --- /dev/null
 +++ b/bananapi_bpi-r2_env
-@@ -0,0 +1,70 @@
+@@ -0,0 +1,69 @@
 +ipaddr=192.168.1.1
 +serverip=192.168.1.254
 +loadaddr=0x88000000
@@ -193,14 +193,13 @@
 +sdmmc_write_recovery=iminfo $fileaddr && mmc dev 1 && part start mmc 1 $part_recovery part_addr && part size mmc 1 $part_recovery part_size && run mmc_write_vol
 +_checkbootedfrom=setenv _checkbootedfrom ; if itest.l *81dffff0 == 434d4d65 ; then setenv bootedfrom eMMC ; else setenv bootedfrom SD ; fi
 +_init_env=setenv _init_env ; setenv _create_env ; saveenv ; saveenv
-+_firstboot=setenv _firstboot ; led $bootled_pwr off ;led $bootled_rec on ; run _checkbootedfrom _switch_to_menu _update_bootdev _update_bootcmd _update_bootcmd2 _init_env boot_first
++_firstboot=setenv _firstboot ; led $bootled_pwr off ;led $bootled_rec on ; run _checkbootedfrom _switch_to_menu _update_bootcmd _update_bootcmd2 _init_env boot_first
 +_set_bootcmd_sdmmc=setenv boot_production "led $bootled_rec off ; led $bootled_pwr on ; run sdmmc_read_production && bootm $loadaddr ; led $bootled_pwr off"
 +_set_bootcmd_emmc=setenv boot_production "led $bootled_rec off ; led $bootled_pwr on ; run emmc_read_production && bootm $loadaddr ; led $bootled_pwr off"
 +_update_bootcmd=setenv _update_bootcmd ; if test "$bootedfrom" = "SD" ; then run _set_bootcmd_sdmmc ; else run _set_bootcmd_emmc ; fi ; setenv _set_bootcmd_sdmmc ; setenv _set_bootcmd_emmc
 +_set_bootcmd2_sdmmc=setenv boot_recovery "led $bootled_pwr off ; led $bootled_rec on ; run sdmmc_read_recovery && bootm $loadaddr ; led $bootled_rec off"
 +_set_bootcmd2_emmc=setenv boot_recovery "led $bootled_pwr off ; led $bootled_rec on ; run emmc_read_recovery && bootm $loadaddr ; led $bootled_rec off"
 +_update_bootcmd2=setenv _update_bootcmd2 ; if test "$bootedfrom" = "SD" ; then run _set_bootcmd2_sdmmc ; else run _set_bootcmd2_emmc ; fi ; setenv _set_bootcmd2_sdmmc ; setenv _set_bootcmd2_emmc
-+_update_bootdev=setenv _update_bootdev ; if test "$bootedfrom" = "SD" ; then setenv bootargs "$console root=/dev/mmcblk1p65" ; else setenv bootargs "$console root=/dev/mmcblk0p65" ; fi
 +_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
 +_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title  [$bootedfrom]    $ver" ; run _set_bm2
 +_set_bm2=setenv _set_bm2 ; setenv bootmenu_2 "Boot production system from $bootedfrom.=run boot_production ; run bootmenu_confirm_return" ; run _set_bm3
diff --git a/package/boot/uboot-mediatek/patches/401-update-u7623-defconfig.patch b/package/boot/uboot-mediatek/patches/401-update-u7623-defconfig.patch
index 453456c94f92b2..6528b165f522d8 100644
--- a/package/boot/uboot-mediatek/patches/401-update-u7623-defconfig.patch
+++ b/package/boot/uboot-mediatek/patches/401-update-u7623-defconfig.patch
@@ -1,6 +1,6 @@
 --- a/configs/mt7623a_unielec_u7623_02_defconfig
 +++ b/configs/mt7623a_unielec_u7623_02_defconfig
-@@ -7,34 +7,110 @@ CONFIG_SYS_MALLOC_F_LEN=0x4000
+@@ -7,33 +7,109 @@ CONFIG_SYS_MALLOC_F_LEN=0x4000
  CONFIG_NR_DRAM_BANKS=1
  CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
  CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x81ffff10
@@ -8,13 +8,10 @@
 +CONFIG_ENV_SIZE=0x10000
  CONFIG_ENV_OFFSET=0x100000
  CONFIG_DEFAULT_DEVICE_TREE="mt7623a-unielec-u7623-02-emmc"
--CONFIG_SYS_PROMPT="U-Boot> "
-+CONFIG_USE_DEFAULT_ENV_FILE=y
-+CONFIG_SYS_PROMPT="MT7623> "
  CONFIG_TARGET_MT7623=y
  CONFIG_SYS_LOAD_ADDR=0x84000000
  CONFIG_FIT=y
--CONFIG_FIT_VERBOSE=y
+ CONFIG_FIT_VERBOSE=y
 +CONFIG_FIT_ENABLE_SHA256_SUPPORT=y
 +CONFIG_LED=y
 +CONFIG_LED_BLINK=y
@@ -38,6 +35,9 @@
 +CONFIG_CFB_CONSOLE_ANSI=y
 +CONFIG_CMD_ENV_FLAGS=y
  # CONFIG_DISPLAY_BOARDINFO is not set
+-CONFIG_SYS_PROMPT="U-Boot> "
++CONFIG_USE_DEFAULT_ENV_FILE=y
++CONFIG_SYS_PROMPT="MT7623> "
  CONFIG_SYS_MAXARGS=8
  CONFIG_SYS_PBSIZE=1049
  CONFIG_SYS_BOOTM_LEN=0x4000000
@@ -71,7 +71,6 @@
  CONFIG_CMD_MMC=y
  CONFIG_CMD_READ=y
 -# CONFIG_CMD_SETEXPR is not set
- # CONFIG_CMD_NFS is not set
 +CONFIG_CMD_SF_TEST=y
 +CONFIG_CMD_PING=y
 +CONFIG_CMD_PXE=y
@@ -110,13 +109,12 @@
  CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 +CONFIG_SYS_MMC_ENV_DEV=0
 +CONFIG_ENV_OVERWRITE=y
-+CONFIG_ENV_IS_IN_MMC=y
  CONFIG_NET_RANDOM_ETHADDR=y
 +CONFIG_NETCONSOLE=y
  CONFIG_USE_IPADDR=y
  CONFIG_IPADDR="192.168.1.1"
  CONFIG_USE_SERVERIP=y
-@@ -46,6 +122,11 @@ CONFIG_CLK=y
+@@ -45,6 +121,11 @@ CONFIG_CLK=y
  CONFIG_SUPPORT_EMMC_BOOT=y
  CONFIG_MMC_HS400_SUPPORT=y
  CONFIG_MMC_MTK=y
@@ -128,7 +126,7 @@
  CONFIG_PHY_FIXED=y
  CONFIG_MEDIATEK_ETH=y
  CONFIG_PINCTRL=y
-@@ -55,9 +136,12 @@ CONFIG_POWER_DOMAIN=y
+@@ -54,9 +135,12 @@ CONFIG_POWER_DOMAIN=y
  CONFIG_MTK_POWER_DOMAIN=y
  CONFIG_DM_SERIAL=y
  CONFIG_MTK_SERIAL=y
diff --git a/package/boot/uboot-mediatek/patches/403-add-bananapi_bpi-r64-snand.patch b/package/boot/uboot-mediatek/patches/403-add-bananapi_bpi-r64-snand.patch
index c9da03c725400d..2ec57708067ba6 100644
--- a/package/boot/uboot-mediatek/patches/403-add-bananapi_bpi-r64-snand.patch
+++ b/package/boot/uboot-mediatek/patches/403-add-bananapi_bpi-r64-snand.patch
@@ -9,7 +9,7 @@
  		ethernet0 = &eth;
  	};
  
-@@ -208,17 +208,11 @@
+@@ -208,16 +208,27 @@
  	};
  };
  
@@ -22,12 +22,26 @@
 +	pinctrl-0 = <&snfi_pins>;
 +	quad-spi;
  	status = "okay";
--
+ 
 -	spi-flash@0{
 -		compatible = "jedec,spi-nor";
 -		reg = <0>;
 -		bootph-all;
--	};
++	partitions {
++		compatible = "fixed-partitions";
++		#address-cells = <1>;
++		#size-cells = <1>;
++
++		partition@0 {
++			label = "bl2";
++			reg = <0x0 0x80000>;
++		};
++
++		partition@80000 {
++			label = "ubi";
++			reg = <0x80000 0x7f80000>;
++			compatible = "linux,ubi";
++		};
+ 	};
  };
  
- &uart0 {
diff --git a/package/boot/uboot-mediatek/patches/404-add-bananapi_bpi-r64_defconfigs.patch b/package/boot/uboot-mediatek/patches/404-add-bananapi_bpi-r64_defconfigs.patch
index f3d9499e171db0..04411d79bcd054 100644
--- a/package/boot/uboot-mediatek/patches/404-add-bananapi_bpi-r64_defconfigs.patch
+++ b/package/boot/uboot-mediatek/patches/404-add-bananapi_bpi-r64_defconfigs.patch
@@ -17,6 +17,7 @@
 +CONFIG_DEBUG_UART_CLOCK=25000000
 +CONFIG_DEFAULT_DEVICE_TREE="mt7622-bananapi-bpi-r64"
 +CONFIG_OF_LIBFDT_OVERLAY=y
++CONFIG_OF_SYSTEM_SETUP=y
 +CONFIG_DEBUG_UART=y
 +CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r64-sdmmc_env"
 +CONFIG_NET_RANDOM_ETHADDR=y
@@ -126,7 +127,6 @@
 +CONFIG_PCI=y
 +CONFIG_MTD=y
 +CONFIG_MTD_UBI_FASTMAP=y
-+CONFIG_MTDPARTS_DEFAULT="mtdparts=spi-nand0:512k(bl2),2048k(fip),-(ubi)"
 +CONFIG_DM_PCI=y
 +CONFIG_PCIE_MEDIATEK=y
 +CONFIG_PINCTRL=y
@@ -167,11 +167,11 @@
 +CONFIG_SERVERIP="192.168.1.254"
 --- /dev/null
 +++ b/bananapi_bpi-r64-sdmmc_env
-@@ -0,0 +1,82 @@
+@@ -0,0 +1,81 @@
 +ipaddr=192.168.1.1
 +serverip=192.168.1.254
 +loadaddr=0x48000000
-+bootargs=root=/dev/mmcblk1p65
++bootargs=root=/dev/fit0
 +bootcmd=if pstore check ; then run boot_recovery ; else run boot_sdmmc ; fi
 +bootconf=config-1#mt7622-bananapi-bpi-r64-pcie1
 +bootconf_pcie=config-1#mt7622-bananapi-bpi-r64-pcie1
@@ -210,7 +210,6 @@
 +boot_ubi=ubi part ubi && setenv bootargs && run boot_ubi_production ; run boot_ubi_recovery
 +boot_ubi_production=led $bootled_pwr on ; run ubi_read_production && bootm $loadaddr ; led $bootled_pwr off
 +boot_ubi_recovery=led $bootled_rec on ; run ubi_read_recovery ; bootm $loadaddr#$bootconf ; ubi remove recovery ; led $bootled_rec off
-+check_ubi=ubi part ubi || run ubi_format
 +emmc_init=run emmc_init_bl && run emmc_init_openwrt ; env default bootcmd ; saveenv ; saveenv
 +emmc_init_bl=run sdmmc_read_emmc_bl2 && run emmc_write_bl2 && run sdmmc_read_emmc_hdr && run emmc_write_hdr && run sdmmc_read_emmc_fip && run emmc_write_fip
 +emmc_init_openwrt=run sdmmc_read_recovery && iminfo $loadaddr && run emmc_write_recovery ; run sdmmc_read_production && iminfo $loadaddr && run emmc_write_production
@@ -220,7 +219,7 @@
 +emmc_write_production=mmc dev 0 && part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_write_vol
 +emmc_write_recovery=mmc dev 0 && part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_write_vol
 +mmc_write_vol=imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$image_size && mmc write $loadaddr 0x$part_addr 0x$image_size
-+mmc_read_vol=mmc read $loadaddr $part_addr 0x8 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr 0x$part_addr 0x$image_size && setexpr filesize $image_size * 0x200
++mmc_read_vol=mmc read $loadaddr $part_addr 0x100 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr 0x$part_addr 0x$image_size && setexpr filesize $image_size * 0x200
 +part_default=production
 +part_recovery=recovery
 +reset_factory=eraseenv && reset
@@ -233,26 +232,26 @@
 +sdmmc_read_snand_fip=mmc dev 1 && part start mmc 1 install part_addr && setexpr offset $part_addr + 0x2400 && mmc read $loadaddr $offset 0x1000
 +sdmmc_write_production=mmc dev 1 && part start mmc 1 $part_default part_addr && part size mmc 1 $part_default part_size && run mmc_write_vol
 +sdmmc_write_recovery=mmc dev 1 && part start mmc 1 $part_recovery part_addr && part size mmc 1 $part_recovery part_size && run mmc_write_vol
-+snand_write_fip=mtd erase fip && mtd write fip $loadaddr
-+snand_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr
-+ubi_create_env=ubi create ubootenv 0x100000 dynamic 0 ; ubi create ubootenv2 0x100000 dynamic 1 ; ubi create fit 0x100000 dynamic 2 ; ubi create recovery 0x100000 dynamic 3
-+ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset
-+ubi_init=run ubi_init_bl && ubi detach && mtd erase ubi && ubi part ubi && run ubi_create_env && run ubi_init_openwrt
++snand_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr 0x0 0x20000 && mtd write bl2 $loadaddr 0x20000 0x20000 && mtd write bl2 $loadaddr 0x40000 0x20000 && mtd write bl2 $loadaddr 0x60000 0x20000
++ubi_create_env=ubi create ubootenv 0x1f000 dynamic ; ubi create ubootenv2 0x1f000 dynamic
++ubi_format=ubi detach ; mtd erase ubi && ubi part ubi
++ubi_init=run ubi_format && run ubi_init_bl && run ubi_create_env && run ubi_init_openwrt
 +ubi_init_openwrt=run sdmmc_read_recovery && iminfo $loadaddr && run ubi_write_recovery ; run sdmmc_read_production && iminfo $loadaddr && run ubi_write_production
-+ubi_init_bl=run sdmmc_read_snand_bl2 && run snand_write_bl2 && run sdmmc_read_snand_fip && run snand_write_fip
++ubi_init_bl=run sdmmc_read_snand_bl2 && run snand_write_bl2 && run sdmmc_read_snand_fip && run ubi_write_fip
 +ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi
 +ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs
 +ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery
 +ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data
-+ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic 2 && ubi write $loadaddr fit $filesize
-+ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic 3 && ubi write $loadaddr recovery $filesize
++ubi_write_fip=run ubi_remove_rootfs ; ubi check fip && ubi remove fip ; ubi create fip 0x200000 static ; ubi write $loadaddr fip 0x200000
++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize
++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize
 +_init_env=setenv _init_env ; setenv _create_env ; saveenv ; saveenv
 +_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first
 +_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
 +_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title       $ver"
 --- /dev/null
 +++ b/configs/mt7622_bananapi_bpi-r64-emmc_defconfig
-@@ -0,0 +1,151 @@
+@@ -0,0 +1,152 @@
 +CONFIG_ARM=y
 +CONFIG_POSITION_INDEPENDENT=y
 +CONFIG_ARCH_MEDIATEK=y
@@ -269,6 +268,7 @@
 +CONFIG_DEBUG_UART_CLOCK=25000000
 +CONFIG_DEFAULT_DEVICE_TREE="mt7622-bananapi-bpi-r64"
 +CONFIG_OF_LIBFDT_OVERLAY=y
++CONFIG_OF_SYSTEM_SETUP=y
 +CONFIG_DEBUG_UART=y
 +CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r64-emmc_env"
 +CONFIG_NET_RANDOM_ETHADDR=y
@@ -411,7 +411,7 @@
 +serverip=192.168.1.254
 +loadaddr=0x48000000
 +bootcmd=if pstore check ; then run boot_recovery ; else run boot_emmc ; fi
-+bootargs=root=/dev/mmcblk0p65
++bootargs=root=/dev/fit0
 +bootconf=config-1#mt7622-bananapi-bpi-r64-pcie1
 +bootconf_pcie=config-1#mt7622-bananapi-bpi-r64-pcie1
 +bootconf_sata=config-1#mt7622-bananapi-bpi-r64-sata
@@ -455,7 +455,7 @@
 +emmc_read_production=mmc dev 0 && part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_read_vol
 +emmc_read_recovery=mmc dev 0 && part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_read_vol
 +mmc_write_vol=imszb $fileaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$image_size && mmc write $fileaddr 0x$part_addr 0x$image_size
-+mmc_read_vol=mmc read $loadaddr $part_addr 0x8 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr 0x$part_addr 0x$image_size
++mmc_read_vol=mmc read $loadaddr $part_addr 0x100 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr 0x$part_addr 0x$image_size
 +part_default=production
 +part_recovery=recovery
 +reset_factory=eraseenv && reset
@@ -481,6 +481,7 @@
 +CONFIG_DEBUG_UART_CLOCK=25000000
 +CONFIG_DEFAULT_DEVICE_TREE="mt7622-bananapi-bpi-r64"
 +CONFIG_OF_LIBFDT_OVERLAY=y
++CONFIG_OF_SYSTEM_SETUP=y
 +CONFIG_DEBUG_UART=y
 +CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r64-snand_env"
 +CONFIG_DISTRO_DEFAULTS=y
@@ -574,7 +575,6 @@
 +CONFIG_PCI=y
 +CONFIG_MTD=y
 +CONFIG_MTD_UBI_FASTMAP=y
-+CONFIG_MTDPARTS_DEFAULT="mtdparts=spi-nand0:512k(bl2),2048k(fip),-(ubi)"
 +CONFIG_DM_PCI=y
 +CONFIG_PCIE_MEDIATEK=y
 +CONFIG_PINCTRL=y
@@ -613,11 +613,11 @@
 +CONFIG_SERVERIP="192.168.1.3"
 --- /dev/null
 +++ b/bananapi_bpi-r64-snand_env
-@@ -0,0 +1,57 @@
+@@ -0,0 +1,56 @@
 +ipaddr=192.168.1.1
 +serverip=192.168.1.254
 +loadaddr=0x48000000
-+bootargs=root=/dev/ubiblock0_2p1
++bootargs=ubi.block=0,fit root=/dev/fit0
 +bootcmd=if pstore check ; then run boot_recovery ; else run boot_ubi ; fi
 +bootconf=config-1#mt7622-bananapi-bpi-r64-pcie1
 +bootconf_pcie=config-1#mt7622-bananapi-bpi-r64-pcie1
@@ -652,22 +652,21 @@
 +boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done
 +boot_tftp_production=tftpboot $loadaddr $bootfile_upg && iminfo $loadaddr && ubi part ubi && run ubi_write_production ubi_prepare_rootfs ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi
 +boot_tftp_recovery=tftpboot $loadaddr $bootfile && iminfo $loadaddr && ubi part ubi && run ubi_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi
-+boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run boot_write_bl2
-+boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run boot_write_fip
++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run snand_write_bl2
++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run ubi_write_fip
 +boot_ubi=ubi part ubi && run boot_production ; run boot_recovery
-+boot_write_bl2=mtd erase bl2 && mtd write spi-nand0 $loadaddr 0x0 0x20000 && mtd write spi-nand0 $loadaddr 0x20000 0x20000 && mtd write spi-nand0 $loadaddr 0x40000 0x20000 && mtd write spi-nand0 $loadaddr 0x60000 0x20000
-+boot_write_fip=mtd erase fip && mtd write fip $loadaddr
++snand_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr 0x0 0x20000 && mtd write bl2 $loadaddr 0x20000 0x20000 && mtd write bl2 $loadaddr 0x40000 0x20000 && mtd write bl2 $loadaddr 0x60000 0x20000
 +check_ubi=ubi part ubi || run ubi_format
-+reset_factory=mw $loadaddr 0x0 0x100000 ; ubi part ubi ; ubi write $loadaddr ubootenv 0x100000 ; ubi write $loadaddr ubootenv2 0x100000 ; ubi remove rootfs_data
-+ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset
++reset_factory=mw $loadaddr 0x0 0x1f000 ; ubi part ubi ; ubi write $loadaddr ubootenv 0x1f000 ; ubi write $loadaddr ubootenv2 0x1f000 ; ubi remove rootfs_data
 +ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi
 +ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs
 +ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery
 +ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data
++ubi_write_fip=run ubi_remove_rootfs ; ubi check fip && ubi remove fip ; ubi create fip 0x200000 static ; ubi write $loadaddr fip 0x200000
 +ubi_write_production=ubi check fit && env exists replacevol && ubi remove fit ; if ubi check fit ; then else run ubi_remove_rootfs ; ubi create fit $filesize dynamic 2 && ubi write $loadaddr fit $filesize ; fi
 +ubi_write_recovery=ubi check recovery && env exists replacevol && ubi remove recovery ; if ubi check recovery ; then else run ubi_remove_rootfs ; ubi create recovery $filesize dynamic 3 && ubi write $loadaddr recovery $filesize ; fi
-+_create_env=ubi create ubootenv 0x100000 dynamic 0 ; ubi create ubootenv2 0x100000 dynamic 1 ; ubi create fit 0x100000 dynamic 2 ; ubi create recovery 0x100000 dynamic 3
-+_init_env=setenv _init_env ; if ubi check ubootenv && ubi check ubootenv2 ; then else run _create_env ; fi ; setenv _create_env ; saveenv || run ubi_format ; saveenv || run ubi_format
-+_firstboot=setenv _firstboot ; run _switch_to_menu ; run check_ubi ; run _init_env ; run boot_first
++_create_env=ubi create ubootenv 0x1f000 dynamic ; ubi create ubootenv2 0x1f000 dynamic
++_init_env=setenv _init_env ; if ubi check ubootenv && ubi check ubootenv2 ; then else run _create_env ; fi ; setenv _create_env ; saveenv ; saveenv
++_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first
 +_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
 +_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title       $ver"
diff --git a/package/boot/uboot-mediatek/patches/410-add-linksys-e8450.patch b/package/boot/uboot-mediatek/patches/410-add-linksys-e8450.patch
index 363509efc1b344..ca8fb32bead132 100644
--- a/package/boot/uboot-mediatek/patches/410-add-linksys-e8450.patch
+++ b/package/boot/uboot-mediatek/patches/410-add-linksys-e8450.patch
@@ -1,6 +1,6 @@
 --- /dev/null
 +++ b/configs/mt7622_linksys_e8450_defconfig
-@@ -0,0 +1,141 @@
+@@ -0,0 +1,140 @@
 +CONFIG_ARM=y
 +CONFIG_POSITION_INDEPENDENT=y
 +CONFIG_ARCH_MEDIATEK=y
@@ -17,7 +17,6 @@
 +CONFIG_DEBUG_UART_CLOCK=25000000
 +CONFIG_DEFAULT_DEVICE_TREE="mt7622-linksys-e8450-ubi"
 +CONFIG_DEBUG_UART=y
-+CONFIG_MTDPARTS_DEFAULT="mtdparts=spi-nand0:512k(bl2),1280k(fip),1024k(factory),256k(reserved),-(ubi)"
 +CONFIG_SMBIOS_PRODUCT_NAME=""
 +CONFIG_AUTOBOOT_KEYED=y
 +CONFIG_BOOTDELAY=30
@@ -144,7 +143,7 @@
 +CONFIG_USB_STORAGE=y
 --- /dev/null
 +++ b/arch/arm/dts/mt7622-linksys-e8450-ubi.dts
-@@ -0,0 +1,197 @@
+@@ -0,0 +1,214 @@
 +// SPDX-License-Identifier: GPL-2.0
 +/*
 + * Copyright (c) 2019 MediaTek Inc.
@@ -307,6 +306,23 @@
 +	pinctrl-0 = <&snfi_pins>;
 +	status = "okay";
 +	quad-spi;
++
++	partitions {
++		compatible = "fixed-partitions";
++		#address-cells = <1>;
++		#size-cells = <1>;
++
++		partition@0 {
++			label = "bl2";
++			reg = <0x0 0x80000>;
++		};
++
++		partition@80000 {
++			label = "ubi";
++			reg = <0x80000 0x7f80000>;
++			compatible = "linux,ubi";
++		};
++	};
 +};
 +
 +&uart0 {
@@ -344,7 +360,7 @@
 +};
 --- a/arch/arm/dts/Makefile
 +++ b/arch/arm/dts/Makefile
-@@ -1305,6 +1305,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
+@@ -1422,6 +1422,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
  	mt7622-rfb.dtb \
  	mt7623a-unielec-u7623-02-emmc.dtb \
  	mt7622-bananapi-bpi-r64.dtb \
@@ -354,8 +370,8 @@
  	mt7981-rfb.dtb \
 --- /dev/null
 +++ b/linksys_e8450_env
-@@ -0,0 +1,57 @@
-+ethaddr_factory=mtd read spi-nand0 0x40080000 0x220000 0x20000 && env readmem -b ethaddr 0x4009fff4 0x6 ; setenv ethaddr_factory
+@@ -0,0 +1,55 @@
++ethaddr_factory=ubi read 0x40080000 factory && env readmem -b ethaddr 0x400ffff4 0x6 ; setenv ethaddr_factory
 +ipaddr=192.168.1.1
 +serverip=192.168.1.254
 +loadaddr=0x48000000
@@ -387,28 +403,26 @@
 +boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever
 +boot_production=led $bootled_pwr on ; run ubi_read_production && bootm $loadaddr#$bootconf ; led $bootled_pwr off
 +boot_recovery=led $bootled_rec on ; run ubi_read_recovery ; bootm $loadaddr#$bootconf ; ubi remove recovery ; led $bootled_rec off
-+boot_serial_write_bl2=loadx $loadaddr 115200 && run boot_write_bl2
-+boot_serial_write_fip=loadx $loadaddr 115200 && run boot_write_fip
++boot_serial_write_bl2=loadx $loadaddr 115200 && run snand_write_bl2
++boot_serial_write_fip=loadx $loadaddr 115200 && run ubi_write_fip
 +boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf
 +boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done
 +boot_tftp_production=tftpboot $loadaddr $bootfile_upg && iminfo $loadaddr && ubi part ubi && run ubi_write_production ubi_prepare_rootfs ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi
 +boot_tftp_recovery=tftpboot $loadaddr $bootfile && iminfo $loadaddr && ubi part ubi && run ubi_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi
-+boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run boot_write_bl2
-+boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run boot_write_fip
++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run snand_write_bl2
++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run ubi_write_fip
 +boot_ubi=ubi part ubi && run boot_production ; run boot_recovery
-+boot_write_bl2=mtd erase bl2 && mtd write spi-nand0 $loadaddr 0x0 0x20000 && mtd write spi-nand0 $loadaddr 0x20000 0x20000 && mtd write spi-nand0 $loadaddr 0x40000 0x20000 && mtd write spi-nand0 $loadaddr 0x60000 0x20000
-+boot_write_fip=mtd erase fip && mtd write fip $loadaddr
-+check_ubi=ubi part ubi || run ubi_format
-+reset_factory=mw $loadaddr 0x0 0x100000 ; ubi part ubi ; ubi write $loadaddr ubootenv 0x100000 ; ubi write $loadaddr ubootenv2 0x100000 ; ubi remove rootfs_data
-+ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset
++snand_write_bl2=mtd erase bl2 && mtd write spi-nand0 $loadaddr 0x0 0x20000 && mtd write spi-nand0 $loadaddr 0x20000 0x20000 && mtd write spi-nand0 $loadaddr 0x40000 0x20000 && mtd write spi-nand0 $loadaddr 0x60000 0x20000
++reset_factory=mw $loadaddr 0xff 0x1f000 ; ubi part ubi ; ubi write $loadaddr ubootenv 0x1f000 ; ubi write $loadaddr ubootenv2 0x1f000 ; ubi remove rootfs_data
 +ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi
 +ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs
 +ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery
 +ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data
++ubi_write_fip=run ubi_remove_rootfs ; ubi check fip && ubi remove fip ; ubi create fip 0x200000 static ; ubi write $loadaddr fip 0x200000
 +ubi_write_production=ubi check fit && env exists replacevol && ubi remove fit ; if ubi check fit ; then else run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize ; fi
 +ubi_write_recovery=ubi check recovery && env exists replacevol && ubi remove recovery ; if ubi check recovery ; then else run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize ; fi
-+_create_env=ubi create ubootenv 0x100000 dynamic ; ubi create ubootenv2 0x100000 dynamic
++_create_env=ubi create ubootenv 0x1f000 dynamic ; ubi create ubootenv2 0x1f000 dynamic
 +_init_env=setenv _init_env ; if ubi check ubootenv && ubi check ubootenv2 ; then else run _create_env ; fi ; setenv _create_env ; saveenv || run ubi_format ; saveenv || run ubi_format
-+_firstboot=setenv _firstboot ; run _switch_to_menu ; run ethaddr_factory ; run check_ubi ; run _init_env ; run boot_first
++_firstboot=setenv _firstboot ; run _switch_to_menu ; run ethaddr_factory ; run _init_env ; run boot_first
 +_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
 +_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title       $ver"
diff --git a/package/boot/uboot-mediatek/patches/412-add-ubnt-unifi-6-lr.patch b/package/boot/uboot-mediatek/patches/412-add-ubnt-unifi-6-lr.patch
index aad6c53b9bb929..bbd05fe41f99e8 100644
--- a/package/boot/uboot-mediatek/patches/412-add-ubnt-unifi-6-lr.patch
+++ b/package/boot/uboot-mediatek/patches/412-add-ubnt-unifi-6-lr.patch
@@ -841,7 +841,7 @@
 +};
 --- a/arch/arm/dts/Makefile
 +++ b/arch/arm/dts/Makefile
-@@ -1306,6 +1306,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
+@@ -1423,6 +1423,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
  	mt7623a-unielec-u7623-02-emmc.dtb \
  	mt7622-bananapi-bpi-r64.dtb \
  	mt7622-linksys-e8450-ubi.dtb \
@@ -1019,7 +1019,7 @@
  
  DECLARE_GLOBAL_DATA_PTR;
  
-@@ -412,6 +413,20 @@ static int initr_onenand(void)
+@@ -397,6 +398,20 @@ static int initr_onenand(void)
  }
  #endif
  
@@ -1040,7 +1040,7 @@
  #ifdef CONFIG_MMC
  static int initr_mmc(void)
  {
-@@ -713,6 +728,9 @@ static init_fnc_t init_sequence_r[] = {
+@@ -692,6 +707,9 @@ static init_fnc_t init_sequence_r[] = {
  #ifdef CONFIG_NMBM_MTD
  	initr_nmbm,
  #endif
diff --git a/package/boot/uboot-mediatek/patches/420-add-support-for-RAVPower-RP-WD009.patch b/package/boot/uboot-mediatek/patches/420-add-support-for-RAVPower-RP-WD009.patch
index 3cd4d1b2df3253..4ee87ce3d2252c 100644
--- a/package/boot/uboot-mediatek/patches/420-add-support-for-RAVPower-RP-WD009.patch
+++ b/package/boot/uboot-mediatek/patches/420-add-support-for-RAVPower-RP-WD009.patch
@@ -22,7 +22,7 @@ Subject: [PATCH] add support for RAVPower RP-WD009
 
 --- a/arch/mips/dts/Makefile
 +++ b/arch/mips/dts/Makefile
-@@ -25,6 +25,7 @@ dtb-$(CONFIG_TARGET_OCTEON_EBB7304) += m
+@@ -26,6 +26,7 @@ dtb-$(CONFIG_TARGET_OCTEON_EBB7304) += m
  dtb-$(CONFIG_TARGET_OCTEON_NIC23) += mrvl,octeon-nic23.dtb
  dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb
  dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb
diff --git a/package/boot/uboot-mediatek/patches/421-zbtlink_zbt-wg3526-16m.patch b/package/boot/uboot-mediatek/patches/421-zbtlink_zbt-wg3526-16m.patch
new file mode 100644
index 00000000000000..b9b241a51d494f
--- /dev/null
+++ b/package/boot/uboot-mediatek/patches/421-zbtlink_zbt-wg3526-16m.patch
@@ -0,0 +1,314 @@
+--- /dev/null
++++ b/configs/mt7621_zbtlink_zbt-wg3526-16m_defconfig
+@@ -0,0 +1,138 @@
++CONFIG_MIPS=y
++CONFIG_SYS_HAS_NONCACHED_MEMORY=y
++CONFIG_SYS_MALLOC_LEN=0x100000
++CONFIG_SPL_LIBCOMMON_SUPPORT=y
++CONFIG_SPL_LIBGENERIC_SUPPORT=y
++CONFIG_NR_DRAM_BANKS=1
++CONFIG_ENV_SIZE=0x1000
++CONFIG_ENV_IS_IN_MTD=y
++CONFIG_ENV_MTD_NAME="nor0"
++CONFIG_ENV_SIZE_REDUND=0x10000
++CONFIG_ENV_SIZE=0x10000
++CONFIG_ENV_OFFSET=0x30000
++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
++CONFIG_RESET_BUTTON_SETTLE_DELAY=400
++CONFIG_BOOTP_SEND_HOSTNAME=y
++# CONFIG_BOOTSTD is not set
++CONFIG_DEFAULT_ENV_FILE="zbtlink_zbt-wg3526-16m_env"
++CONFIG_DEFAULT_DEVICE_TREE="zbtlink,zbt-wg3526"
++CONFIG_SPL_BSS_MAX_SIZE=0x80000
++CONFIG_SPL_BSS_START_ADDR=0x80140000
++CONFIG_SPL_SERIAL=y
++CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000
++CONFIG_SPL=y
++CONFIG_DEBUG_UART_BASE=0xbe000c00
++CONFIG_DEBUG_UART_CLOCK=50000000
++CONFIG_SYS_HAS_NONCACHED_MEMORY=y
++CONFIG_SYS_LOAD_ADDR=0x83000000
++CONFIG_SYS_MIPS_TIMER_FREQ=440000000
++CONFIG_ARCH_MTMIPS=y
++CONFIG_SOC_MT7621=y
++# CONFIG_MIPS_CACHE_SETUP is not set
++# CONFIG_MIPS_CACHE_DISABLE is not set
++CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y
++CONFIG_MIPS_BOOT_FDT=y
++CONFIG_DEBUG_UART=y
++CONFIG_TPL_SYS_MALLOC_F_LEN=0x1000
++CONFIG_AUTOBOOT_KEYED=y
++CONFIG_BOOTDELAY=30
++CONFIG_AUTOBOOT_MENU_SHOW=y
++CONFIG_CFB_CONSOLE_ANSI=y
++CONFIG_BUTTON=y
++CONFIG_BUTTON_GPIO=y
++CONFIG_GPIO_HOG=y
++CONFIG_CMD_ENV_FLAGS=y
++CONFIG_FIT=y
++# CONFIG_FIT_ENABLE_SHA256_SUPPORT is not set
++CONFIG_HUSH_PARSER=y
++CONFIG_LOGLEVEL=6
++# CONFIG_LOG is not set
++# CONFIG_SYS_LONGHELP is not set
++# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
++CONFIG_SYS_CONSOLE_INFO_QUIET=y
++CONFIG_SPL_SYS_MALLOC_SIMPLE=y
++CONFIG_SPL_NOR_SUPPORT=y
++CONFIG_TPL=y
++# CONFIG_TPL_FRAMEWORK is not set
++CONFIG_LEGACY_IMAGE_FORMAT=y
++# CONFIG_BOOTM_NETBSD is not set
++# CONFIG_BOOTM_PLAN9 is not set
++# CONFIG_BOOTM_RTEMS is not set
++# CONFIG_BOOTM_VXWORKS is not set
++# CONFIG_EFI is not set
++# CONFIG_EFI_LOADER is not set
++CONFIG_CMD_BOOTMENU=y
++# CONFIG_CMD_BOOTEFI is not set
++# CONFIG_CMD_BOOTD is not set
++# CONFIG_CMD_BOOTP is not set
++CONFIG_CMD_BOOTM=y
++# CONFIG_CMD_BOOTDEV is not set
++# CONFIG_CMD_BOOTFLOW is not set
++CONFIG_CMD_BUTTON=y
++CONFIG_CMD_ECHO=y
++# CONFIG_CMD_ELF is not set
++# CONFIG_CMD_BOOTEFI_BOOTMGR is not set
++CONFIG_CMD_ENV_READMEM=y
++CONFIG_CMD_ERASEENV=y
++CONFIG_CMD_GPIO=y
++CONFIG_CMD_HASH=y
++CONFIG_CMD_ITEST=y
++CONFIG_CMD_LED=y
++# CONFIG_CMD_MBR is not set
++CONFIG_CMD_MMC=y
++CONFIG_CMD_MTD=y
++CONFIG_CMD_MTDPART=y
++# CONFIG_CMD_PCI is not set
++CONFIG_CMD_SF_TEST=y
++CONFIG_CMD_PING=y
++CONFIG_CMD_TFTPBOOT=y
++# CONFIG_CMD_UNLZ4 is not set
++CONFIG_CMD_ASKENV=y
++CONFIG_CMD_SETEXPR=y
++CONFIG_CMD_SLEEP=y
++CONFIG_CMD_SOURCE=y
++CONFIG_DOS_PARTITION=y
++# CONFIG_SPL_DOS_PARTITION is not set
++# CONFIG_ISO_PARTITION is not set
++# CONFIG_EFI_PARTITION is not set
++# CONFIG_SPL_EFI_PARTITION is not set
++CONFIG_PARTITION_TYPE_GUID=y
++CONFIG_SYS_RELOC_GD_ENV_ADDR=y
++# CONFIG_NET_RANDOM_ETHADDR is not set
++# CONFIG_I2C is not set
++# CONFIG_INPUT is not set
++CONFIG_MMC=y
++# CONFIG_MMC_QUIRKS is not set
++# CONFIG_MMC_HW_PARTITIONING is not set
++CONFIG_MMC_MTK=y
++CONFIG_MTD=y
++CONFIG_DM_MTD=y
++CONFIG_SF_DEFAULT_SPEED=20000000
++# CONFIG_SPI_FLASH_BAR is not set
++# CONFIG_SPI_FLASH_EON is not set
++# CONFIG_SPI_FLASH_GIGADEVICE is not set
++# CONFIG_SPI_FLASH_ISSI is not set
++# CONFIG_SPI_FLASH_MACRONIX is not set
++# CONFIG_SPI_FLASH_SPANSION is not set
++# CONFIG_SPI_FLASH_STMICRO is not set
++CONFIG_SPI_FLASH_WINBOND=y
++# CONFIG_SPI_FLASH_XMC is not set
++# CONFIG_SPI_FLASH_XTX is not set
++CONFIG_SPI_FLASH_MTD=y
++CONFIG_MEDIATEK_ETH=y
++CONFIG_PHY=y
++CONFIG_PHY_MTK_TPHY=y
++CONFIG_DEBUG_UART_SHIFT=2
++CONFIG_SPI=y
++CONFIG_MT7621_SPI=y
++CONFIG_SYSRESET=y
++CONFIG_SYSRESET_RESETCTL=y
++# CONFIG_SYS_XTRACE is not set
++CONFIG_USE_DEFAULT_ENV_FILE=y
++CONFIG_VERSION_VARIABLE=y
++CONFIG_WDT=y
++CONFIG_WDT_MT7621=y
++# CONFIG_BINMAN_FDT is not set
++CONFIG_LZMA=y
++CONFIG_SPL_LZMA=y
++# CONFIG_GZIP is not set
+--- /dev/null
++++ b/zbtlink_zbt-wg3526-16m_env
+@@ -0,0 +1,36 @@
++ethaddr_factory=mtd read factory $loadaddr 0x0 0x10000 ; setexpr macoffs $loadaddr + 0xe000 ; env readmem -b ethaddr $macoffs 0x6 ; setenv ethaddr_factory
++ipaddr=192.168.1.1
++serverip=192.168.1.254
++loadaddr=0x83000000
++bootcmd=run boot_nor
++bootdelay=0
++bootfile=openwrt-ramips-mt7621-zbtlink_zbt-wg3526-16m-initramfs-kernel.bin
++bootfile_uboot=u-boot-mt7621.bin
++bootfile_upg=openwrt-ramips-mt7621-zbtlink_zbt-wg3526-16m-squashfs-sysupgrade.bin
++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60
++bootmenu_default=0
++bootmenu_delay=0
++bootmenu_title=      ( ( ( OpenWrt ) ) )
++bootmenu_0=Initialize environment.=run _firstboot
++bootmenu_0d=Run default boot command.=run boot_default
++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return
++bootmenu_2=Boot system from flash.=run boot_nor ; run bootmenu_confirm_return
++bootmenu_3=Load system via TFTP then write to flash.=run boot_tftp_sysupgrade ; run bootmenu_confirm_return
++bootmenu_4=Load U-Boot via TFTP then write to flash.=run boot_tftp_write_uboot ; run bootmenu_confirm_return
++bootmenu_5=Reset all settings to factory defaults.=run reset_factory ; reset
++bootmenu_6=Reboot.=reset
++boot_first=if button reset ; then run boot_tftp ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu
++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_tftp_forever
++boot_nor=bootm 0x1fc50000
++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr
++boot_tftp_forever=while true ; do run boot_tftp ; sleep 1 ; done
++boot_tftp_sysupgrade=tftpboot $loadaddr $bootfile_upg && iminfo $loadaddr && run nor_write_production
++boot_tftp_write_uboot=tftpboot $loadaddr $bootfile_uboot && run nor_write_uboot
++reset_factory=mtd erase u-boot-env 0x0 0x10000 && reset
++nor_pad_size=setexpr image_eb $filesize / 0x1000 ; setexpr tmp1 image_size % 0x1000 ; test 0x$tmp1 -gt 0 && setexpr image_eb $image_eb + 1 ; setexpr image_eb $image_eb * 0x1000
++nor_write_production=run nor_pad_size ; test 0x$image_eb -le 0xfb0000 && mtd erase firmware 0x0 0x$image_eb && mtd write firmware $loadaddr 0x0 $filesize
++nor_write_uboot=mtd erase u-boot 0x0 0x30000 && mtd write u-boot $loadaddr 0x0 0x30000
++_init_env=setenv _init_env ; saveenv
++_firstboot=setenv _firstboot ; run _switch_to_menu ; run ethaddr_factory ; run _init_env ; run boot_first
++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title       $ver"
+--- /dev/null
++++ b/arch/mips/dts/zbtlink,zbt-wg3526.dts
+@@ -0,0 +1,131 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) 2022 MediaTek Inc. All rights reserved.
++ *
++ * Author: Weijie Gao <weijie.gao@mediatek.com>
++ */
++
++/dts-v1/;
++
++#include "mt7621.dtsi"
++#include <dt-bindings/gpio/gpio.h>
++
++/ {
++	compatible = "zbtlink,zbt-wg3526", "mediatek,mt7621-rfb", "mediatek,mt7621-soc";
++	model = "Zbtlink WG3526";
++
++	aliases {
++		ethernet0 = &eth;
++		serial0 = &uart0;
++		spi0 = &spi;
++	};
++
++	chosen {
++		stdout-path = &uart0;
++	};
++
++	keys {
++		compatible = "gpio-keys";
++
++		reset {
++			label = "reset";
++			gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
++		};
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		led_status: status {
++			label = "green:status";
++			gpios = <&gpio 24 GPIO_ACTIVE_LOW>;
++		};
++	};
++};
++
++&pinctrl {
++	state_default: pin_state {
++		gpios {
++			groups = "i2c", "uart3", "pcie reset";
++			function = "gpio";
++		};
++
++		wdt {
++			groups = "wdt";
++			function = "wdt rst";
++		};
++
++		jtag {
++			groups = "jtag";
++			function = "jtag";
++		};
++	};
++};
++
++&uart0 {
++	status = "okay";
++};
++
++&gpio {
++	status = "okay";
++};
++
++&spi {
++	status = "okay";
++	num-cs = <2>;
++
++	spi-flash@0 {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		compatible = "jedec,spi-nor";
++		spi-max-frequency = <25000000>;
++		reg = <0>;
++
++
++		partitions {
++			compatible = "fixed-partitions";
++			#address-cells = <1>;
++			#size-cells = <1>;
++
++			partition@0 {
++				label = "u-boot";
++				reg = <0x0 0x30000>;
++			};
++
++			partition@30000 {
++				label = "u-boot-env";
++				reg = <0x30000 0x10000>;
++			};
++
++			factory: partition@40000 {
++				label = "factory";
++				reg = <0x40000 0x10000>;
++				read-only;
++			};
++
++			firmware: partition@50000 {
++				compatible = "denx,uimage";
++				label = "firmware";
++				reg = <0x50000 0xfb0000>;
++			};
++		};
++	};
++};
++
++&eth {
++	status = "okay";
++};
++
++&mmc {
++	cap-sd-highspeed;
++
++	status = "okay";
++};
++
++&ssusb {
++	status = "okay";
++};
++
++&u3phy {
++	status = "okay";
++};
diff --git a/package/boot/uboot-mediatek/patches/430-add-bpi-r3.patch b/package/boot/uboot-mediatek/patches/430-add-bpi-r3.patch
index 1567ba537c052a..c48a934b7440c3 100644
--- a/package/boot/uboot-mediatek/patches/430-add-bpi-r3.patch
+++ b/package/boot/uboot-mediatek/patches/430-add-bpi-r3.patch
@@ -1,6 +1,6 @@
 --- /dev/null
 +++ b/configs/mt7986a_bpi-r3-emmc_defconfig
-@@ -0,0 +1,196 @@
+@@ -0,0 +1,197 @@
 +CONFIG_ARM=y
 +CONFIG_POSITION_INDEPENDENT=y
 +CONFIG_ARCH_MEDIATEK=y
@@ -13,6 +13,7 @@
 +CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r3_emmc_env"
 +CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-bpi-r3-emmc.dtb"
 +CONFIG_OF_LIBFDT_OVERLAY=y
++CONFIG_OF_SYSTEM_SETUP=y
 +CONFIG_DEBUG_UART_BASE=0x11002000
 +CONFIG_DEBUG_UART_CLOCK=40000000
 +CONFIG_DEBUG_UART=y
@@ -199,7 +200,7 @@
 +CONFIG_SERVERIP="192.168.1.254"
 --- /dev/null
 +++ b/configs/mt7986a_bpi-r3-nor_defconfig
-@@ -0,0 +1,195 @@
+@@ -0,0 +1,193 @@
 +CONFIG_ARM=y
 +CONFIG_POSITION_INDEPENDENT=y
 +CONFIG_ARCH_MEDIATEK=y
@@ -212,6 +213,7 @@
 +CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r3_nor_env"
 +CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-bpi-r3-emmc.dtb"
 +CONFIG_OF_LIBFDT_OVERLAY=y
++CONFIG_OF_SYSTEM_SETUP=y
 +CONFIG_DEBUG_UART_BASE=0x11002000
 +CONFIG_DEBUG_UART_CLOCK=40000000
 +CONFIG_DEBUG_UART=y
@@ -271,9 +273,6 @@
 +CONFIG_CMD_SMC=y
 +CONFIG_CMD_TFTPBOOT=y
 +CONFIG_CMD_TFTPSRV=y
-+CONFIG_CMD_UBI=y
-+CONFIG_CMD_UBI_RENAME=y
-+CONFIG_CMD_UBIFS=y
 +CONFIG_CMD_ASKENV=y
 +CONFIG_CMD_PART=y
 +CONFIG_CMD_RARP=y
@@ -397,7 +396,7 @@
 +CONFIG_SERVERIP="192.168.1.254"
 --- /dev/null
 +++ b/configs/mt7986a_bpi-r3-sd_defconfig
-@@ -0,0 +1,196 @@
+@@ -0,0 +1,197 @@
 +CONFIG_ARM=y
 +CONFIG_POSITION_INDEPENDENT=y
 +CONFIG_ARCH_MEDIATEK=y
@@ -410,6 +409,7 @@
 +CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r3_sdmmc_env"
 +CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-bpi-r3-sd.dtb"
 +CONFIG_OF_LIBFDT_OVERLAY=y
++CONFIG_OF_SYSTEM_SETUP=y
 +CONFIG_DEBUG_UART_BASE=0x11002000
 +CONFIG_DEBUG_UART_CLOCK=40000000
 +CONFIG_DEBUG_UART=y
@@ -596,7 +596,7 @@
 +CONFIG_SERVERIP="192.168.1.254"
 --- /dev/null
 +++ b/configs/mt7986a_bpi-r3-snand_defconfig
-@@ -0,0 +1,197 @@
+@@ -0,0 +1,198 @@
 +CONFIG_ARM=y
 +CONFIG_POSITION_INDEPENDENT=y
 +CONFIG_ARCH_MEDIATEK=y
@@ -609,6 +609,7 @@
 +CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r3_snand_env"
 +CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-bpi-r3-emmc.dtb"
 +CONFIG_OF_LIBFDT_OVERLAY=y
++CONFIG_OF_SYSTEM_SETUP=y
 +CONFIG_DEBUG_UART_BASE=0x11002000
 +CONFIG_DEBUG_UART_CLOCK=40000000
 +CONFIG_DEBUG_UART=y
@@ -796,12 +797,12 @@
 +CONFIG_SERVERIP="192.168.1.254"
 --- /dev/null
 +++ b/bananapi_bpi-r3_sdmmc_env
-@@ -0,0 +1,80 @@
+@@ -0,0 +1,81 @@
 +ipaddr=192.168.1.1
 +serverip=192.168.1.254
 +loadaddr=0x46000000
 +console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0
-+bootargs=root=/dev/mmcblk0p65
++bootargs=root=/dev/fit0
 +bootcmd=if pstore check ; then run boot_recovery ; else run boot_sdmmc ; fi
 +bootconf=config-mt7986a-bananapi-bpi-r3
 +bootconf_base=config-mt7986a-bananapi-bpi-r3
@@ -853,26 +854,27 @@
 +sdmmc_read_emmc_install=part start mmc 0 install part_addr && setexpr offset $part_addr + 0x3800 && mmc read $loadaddr $offset 0x4000
 +sdmmc_write_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_write_vol
 +sdmmc_write_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_write_vol
-+mtd_write_fip=mtd erase fip && mtd write fip $loadaddr
-+mtd_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr
++snand_write_bl2=mtd erase bl2 0x0 0x100000 && mtd write bl2 $loadaddr 0x0 0x40000 && mtd write bl2 $loadaddr 0x40000 0x40000 && mtd write bl2 $loadaddr 0x80000 0x40000 && mtd write bl2 $loadaddr 0xc0000 0x40000
++nor_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr
++nor_write_fip=mtd erase fip && mtd write fip $loadaddr
 +nor_pad_size=imsz $loadaddr image_size ; setexpr image_eb 0x$image_size / 0x10000 ; setexpr tmp1 0x$image_size % 0x10000 ; test 0x$tmp1 -gt 0 && setexpr image_eb 0x$image_eb + 1 ; setexpr image_eb $image_eb * 0x10000
 +nor_erase_env=mtd erase u-boot-env
 +nor_write_production=run nor_pad_size ; test 0x$image_eb -le 0x3000000 && mtd erase fit && mtd write fit $loadaddr 0x0 $image_eb
 +nor_write_recovery=run nor_pad_size ; test 0x$image_eb -le 0x900000 && mtd erase recovery 0x0 0x$image_eb && mtd write recovery $loadaddr 0x0 $image_eb
 +nor_init=run nor_init_bl && run nor_init_openwrt
-+nor_init_bl=run sdmmc_read_nor_bl2 && run mtd_write_bl2 && run sdmmc_read_nor_fip && run mtd_write_fip && run nor_erase_env
++nor_init_bl=run sdmmc_read_nor_bl2 && run nor_write_bl2 && run sdmmc_read_nor_fip && run nor_write_fip && run nor_erase_env
 +nor_init_openwrt=run sdmmc_read_recovery && iminfo $loadaddr && run nor_write_recovery ; run sdmmc_read_production && iminfo $loadaddr && run nor_write_production
-+ubi_create_env=ubi create ubootenv 0x100000 dynamic 0 ; ubi create ubootenv2 0x100000 dynamic 1
 +ubi_format=ubi detach ; mtd erase ubi && ubi part ubi
-+ubi_init=run ubi_init_bl && run ubi_format && run ubi_create_env && run ubi_init_openwrt && run ubi_init_emmc_install
++ubi_init=run ubi_format && run ubi_init_bl && run ubi_init_openwrt && run ubi_init_emmc_install
 +ubi_init_openwrt=run sdmmc_read_recovery && iminfo $loadaddr && run ubi_write_recovery ; run sdmmc_read_production && iminfo $loadaddr && run ubi_write_production
-+ubi_init_bl=run sdmmc_read_snand_bl2 && run mtd_write_bl2 && run sdmmc_read_snand_fip && run mtd_write_fip
++ubi_init_bl=run sdmmc_read_snand_bl2 && run snand_write_bl2 && run sdmmc_read_snand_fip && run ubi_write_fip
 +ubi_init_emmc_install=run sdmmc_read_emmc_install && run ubi_write_emmc_install
 +ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi
 +ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data
++ubi_write_fip=run ubi_remove_rootfs ; ubi check fip && ubi remove fip ; ubi create fip 0x200000 static ; ubi write $loadaddr fip 0x200000
 +ubi_write_emmc_install=ubi check emmc_install && ubi remove emmc_install ; ubi create emmc_install 0x800000 dynamic ; ubi write $loadaddr emmc_install 0x800000
-+ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic 2 && ubi write $loadaddr fit $filesize
-+ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic 3 && ubi write $loadaddr recovery $filesize
++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize
++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize
 +_init_env=setenv _init_env ; setenv _create_env ; saveenv ; saveenv
 +_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first
 +_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
@@ -884,7 +886,7 @@
 +serverip=192.168.1.254
 +loadaddr=0x46000000
 +console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0
-+bootargs=root=/dev/mtdblock0p1
++bootargs=root=/dev/fit0
 +bootcmd=if pstore check ; then run boot_recovery ; else run boot_nor ; fi
 +bootconf=config-mt7986a-bananapi-bpi-r3
 +bootconf_base=config-mt7986a-bananapi-bpi-r3
@@ -911,7 +913,7 @@
 +bootmenu_4=Load production system via TFTP then write to flash.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return
 +bootmenu_5=Load recovery system via TFTP then write to flash.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return
 +bootmenu_6=Load BL31+U-Boot FIP via TFTP then write to flash.=run boot_tftp_write_fip ; run bootmenu_confirm_return
-+bootmenu_7=Load BL2 preloader via TFTP then write to flash.=run boot_tftp_write_preloader ; run bootmenu_confirm_return
++bootmenu_7=Load BL2 preloader via TFTP then write to flash.=run boot_tftp_write_bl2 ; run bootmenu_confirm_return
 +bootmenu_8=Reboot.=reset
 +bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset
 +boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu
@@ -924,13 +926,13 @@
 +boot_tftp_production=run boot_update_conf ; tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run nor_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi
 +boot_tftp_recovery=run boot_update_conf ; tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run nor_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi
 +boot_tftp=run boot_update_conf ; tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf
-+boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run boot_write_fip
-+boot_tftp_write_preloader=tftpboot $loadaddr $bootfile_bl2 && run boot_write_preloader
++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run nor_write_fip
++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run nor_write_bl2
 +boot_update_conf=if mmc partconf 0 ; then setenv bootconf $bootconf_base#$bootconf_nor#$bootconf_emmc ; else setenv bootconf $bootconf_base#$bootconf_nor#$bootconf_sd ; fi
 +boot_nor=run boot_production ; run boot_recovery
-+boot_write_fip=mtd erase fip && mtd write fip $loadaddr
-+boot_write_preloader=mtd erase bl2 && mtd write bl2 $loadaddr
 +reset_factory=mtd erase u-boot-env
++nor_write_fip=mtd erase fip && mtd write fip $loadaddr
++nor_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr
 +nor_read_production=mtd read fit $loadaddr 0x0 0x20000 && imsz $loadaddr image_size && mtd read fit $loadaddr 0x0 $image_size
 +nor_read_recovery=mtd read recovery $loadaddr 0x0 0x20000 && imsz $loadaddr image_size && mtd read recovery $loadaddr 0x0 $image_size
 +nor_pad_size=imsz $loadaddr image_size ; setexpr image_eb 0x$image_size / 0x10000 ; setexpr tmp1 0x$image_size % 0x10000 ; test 0x$tmp1 -gt 0 && setexpr image_eb 0x$image_eb + 1 ; setexpr image_eb $image_eb * 0x10000
@@ -942,12 +944,12 @@
 +_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title       $ver"
 --- /dev/null
 +++ b/bananapi_bpi-r3_snand_env
-@@ -0,0 +1,74 @@
+@@ -0,0 +1,73 @@
 +ipaddr=192.168.1.1
 +serverip=192.168.1.254
 +loadaddr=0x46000000
 +console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0
-+bootargs=root=/dev/ubiblock0_2p1
++bootargs=root=/dev/fit0
 +bootconf=config-mt7986a-bananapi-bpi-r3
 +bootconf_base=config-mt7986a-bananapi-bpi-r3
 +bootconf_nor=mt7986a-bananapi-bpi-r3-nor
@@ -982,28 +984,27 @@
 +boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever
 +boot_production=run boot_update_conf ; led $bootled_pwr on ; run ubi_read_production && bootm $loadaddr#$bootconf ; led $bootled_pwr off
 +boot_recovery=run boot_update_conf ; led $bootled_rec on ; run ubi_read_recovery && bootm $loadaddr#$bootconf ; led $bootled_rec off
-+boot_ubi=run boot_update_conf ; run boot_production ; run boot_recovery
++boot_ubi=run boot_production ; run boot_recovery
 +boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done
 +boot_tftp_production=run boot_update_conf ; tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run ubi_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi
 +boot_tftp_recovery=run boot_update_conf ; tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run ubi_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi
 +boot_tftp=run boot_update_conf ; tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf
-+boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run mtd_write_fip && run reset_factory
-+boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run mtd_write_bl2
-+boot_update_conf=if mmc partconf 0 ; then setenv bootconf $bootconf_base#$bootconf_nand#$bootconf_emmc ; else setenv bootconf  $bootconf_base#$bootconf_nand#$bootconf_sd ; fi
++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run ubi_write_fip && run reset_factory
++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run snand_write_bl2
++boot_update_conf=if mmc partconf 0 ; then setenv bootconf $bootconf_base#$bootconf_nand#$bootconf_emmc ; else setenv bootconf $bootconf_base#$bootconf_nand#$bootconf_sd ; fi
 +part_default=production
 +part_recovery=recovery
-+reset_factory=ubi part ubi ; mw $loadaddr 0x0 0x800 ; ubi write $loadaddr ubootenv 0x800 ; ubi write $loadaddr ubootenv2 0x800
-+mtd_write_fip=mtd erase fip && mtd write fip $loadaddr
-+mtd_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr
-+ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic 0 ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic 1
-+ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset
++reset_factory=ubi part ubi ; mw $loadaddr 0xff 0x1f000 ; ubi write $loadaddr ubootenv 0x1f000 ; ubi write $loadaddr ubootenv2 0x1f000
++snand_write_bl2=mtd erase bl2 0x0 0x100000 && mtd write bl2 $loadaddr 0x0 0x40000 && mtd write bl2 $loadaddr 0x40000 0x40000 && mtd write bl2 $loadaddr 0x80000 0x40000 && mtd write bl2 $loadaddr 0xc0000 0x40000
++ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x1f000 dynamic ; ubi check ubootenv2 || ubi create ubootenv2 0x1f000 dynamic
 +ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi
 +ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs
 +ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery
 +ubi_read_emmc_install=ubi check emmc_install && ubi read $loadaddr emmc_install
 +ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data
-+ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic 2 && ubi write $loadaddr fit $filesize
-+ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic 3 && ubi write $loadaddr recovery $filesize
++ubi_write_fip=run ubi_remove_rootfs ; ubi check fip && ubi remove fip ; ubi create fip 0x200000 static ; ubi write $loadaddr fip 0x200000
++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize
++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize
 +mmc_write_vol=imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$image_size && mmc write $loadaddr 0x$part_addr 0x$image_size
 +emmc_init=mmc dev 0 && mmc bootbus 0 0 0 0 && run emmc_init_bl && run emmc_init_openwrt ; env default bootcmd ; saveenv ; saveenv
 +emmc_init_bl=run ubi_read_emmc_install && setenv fileaddr $loadaddr && run emmc_write_bl2 && setexpr fileaddr $loadaddr + 0x100000 && run emmc_write_fip && setexpr fileaddr $loadaddr + 0x500000 && run emmc_write_hdr
@@ -1024,7 +1025,7 @@
 +serverip=192.168.1.254
 +loadaddr=0x46000000
 +console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0
-+bootargs=root=/dev/mmcblk0p65
++bootargs=root=/dev/fit0
 +bootcmd=if pstore check ; then run boot_recovery ; else run boot_emmc ; fi
 +bootconf=config-mt7986a-bananapi-bpi-r3
 +bootconf_base=config-mt7986a-bananapi-bpi-r3
@@ -1058,7 +1059,7 @@
 +boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever
 +boot_production=run boot_update_conf ; led $bootled_pwr on ; run emmc_read_production && bootm $loadaddr#$bootconf ; led $bootled_pwr off
 +boot_recovery=run boot_update_conf ; led $bootled_rec on ; run emmc_read_recovery && bootm $loadaddr#$bootconf ; led $bootled_rec off
-+boot_emmc=run boot_update_conf ; run boot_production ; run boot_recovery
++boot_emmc=run boot_production ; run boot_recovery
 +boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done
 +boot_tftp_production=run boot_update_conf ; tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run emmc_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi
 +boot_tftp_recovery=run boot_update_conf ; tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run emmc_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi
@@ -1081,3 +1082,32 @@
 +_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first
 +_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
 +_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title       $ver"
+--- a/arch/arm/dts/mt7986a-bpi-r3-sd.dts
++++ b/arch/arm/dts/mt7986a-bpi-r3-sd.dts
+@@ -235,22 +235,13 @@
+ 
+ 			partition@0 {
+ 				label = "bl2";
+-				reg = <0x0 0x80000>;
++				reg = <0x0 0x200000>;
+ 			};
+ 
+-			partition@80000 {
+-				label = "factory";
+-				reg = <0x80000 0x300000>;
+-			};
+-
+-			partition@380000 {
+-				label = "fip";
+-				reg = <0x380000 0x200000>;
+-			};
+-
+-			partition@580000 {
++			partition@200000 {
+ 				label = "ubi";
+-				reg = <0x580000 0x7a80000>;
++				reg = <0x200000 0x7e00000>;
++				compatible = "linux,ubi";
+ 			};
+ 		};
+ 	};
diff --git a/package/boot/uboot-mediatek/patches/442-add-bpi-r3-mini.patch b/package/boot/uboot-mediatek/patches/442-add-bpi-r3-mini.patch
new file mode 100644
index 00000000000000..667b7570ac2e82
--- /dev/null
+++ b/package/boot/uboot-mediatek/patches/442-add-bpi-r3-mini.patch
@@ -0,0 +1,779 @@
+--- /dev/null
++++ b/configs/mt7986a_bpi-r3-mini-emmc_defconfig
+@@ -0,0 +1,203 @@
++CONFIG_ARM=y
++CONFIG_POSITION_INDEPENDENT=y
++CONFIG_ARCH_MEDIATEK=y
++CONFIG_TARGET_MT7986=y
++CONFIG_TEXT_BASE=0x41e00000
++CONFIG_SYS_MALLOC_F_LEN=0x4000
++CONFIG_SYS_HAS_NONCACHED_MEMORY=y
++CONFIG_NR_DRAM_BANKS=1
++CONFIG_DEFAULT_DEVICE_TREE="mt7986a-bpi-r3-mini"
++CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r3-mini_emmc_env"
++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-bpi-r3-mini.dtb"
++CONFIG_OF_LIBFDT_OVERLAY=y
++CONFIG_OF_SYSTEM_SETUP=y
++CONFIG_DEBUG_UART_BASE=0x11002000
++CONFIG_DEBUG_UART_CLOCK=40000000
++CONFIG_DEBUG_UART=y
++CONFIG_SYS_LOAD_ADDR=0x46000000
++CONFIG_SMBIOS_PRODUCT_NAME=""
++CONFIG_AUTOBOOT_KEYED=y
++CONFIG_BOOTDELAY=30
++CONFIG_AUTOBOOT_MENU_SHOW=y
++CONFIG_CFB_CONSOLE_ANSI=y
++CONFIG_BOARD_LATE_INIT=y
++CONFIG_BUTTON=y
++CONFIG_BUTTON_GPIO=y
++CONFIG_GPIO_HOG=y
++CONFIG_CMD_ENV_FLAGS=y
++CONFIG_FIT=y
++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y
++CONFIG_LED=y
++CONFIG_LED_BLINK=y
++CONFIG_LED_GPIO=y
++CONFIG_LOGLEVEL=7
++CONFIG_LOG=y
++CONFIG_SYS_PROMPT="MT7986> "
++CONFIG_CMD_BOOTMENU=y
++CONFIG_CMD_BOOTP=y
++CONFIG_CMD_BUTTON=y
++CONFIG_CMD_CACHE=y
++CONFIG_CMD_CDP=y
++CONFIG_CMD_CPU=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_DM=y
++CONFIG_CMD_DNS=y
++CONFIG_CMD_ECHO=y
++CONFIG_CMD_ENV_READMEM=y
++CONFIG_CMD_ERASEENV=y
++CONFIG_CMD_EXT4=y
++CONFIG_CMD_FAT=y
++CONFIG_CMD_FDT=y
++CONFIG_CMD_FS_GENERIC=y
++CONFIG_CMD_FS_UUID=y
++CONFIG_CMD_GPIO=y
++CONFIG_CMD_GPT=y
++CONFIG_CMD_HASH=y
++CONFIG_CMD_ITEST=y
++CONFIG_CMD_LED=y
++CONFIG_CMD_LICENSE=y
++CONFIG_CMD_LINK_LOCAL=y
++# CONFIG_CMD_MBR is not set
++CONFIG_CMD_MDIO=y
++CONFIG_CMD_MII=y
++CONFIG_CMD_MMC=y
++CONFIG_CMD_MTD=y
++CONFIG_CMD_PCI=y
++CONFIG_CMD_PSTORE=y
++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000
++CONFIG_CMD_SF_TEST=y
++CONFIG_CMD_PING=y
++CONFIG_CMD_PXE=y
++CONFIG_CMD_PWM=y
++CONFIG_CMD_SMC=y
++CONFIG_CMD_TFTPBOOT=y
++CONFIG_CMD_TFTPSRV=y
++CONFIG_CMD_UBI=y
++CONFIG_CMD_UBI_RENAME=y
++CONFIG_CMD_UBIFS=y
++CONFIG_CMD_ASKENV=y
++CONFIG_CMD_PART=y
++CONFIG_CMD_RARP=y
++CONFIG_CMD_SETEXPR=y
++CONFIG_CMD_SLEEP=y
++CONFIG_CMD_SNTP=y
++CONFIG_CMD_SOURCE=y
++CONFIG_CMD_STRINGS=y
++CONFIG_CMD_USB=y
++CONFIG_CMD_UUID=y
++CONFIG_DISPLAY_CPUINFO=y
++CONFIG_DM_MDIO=y
++CONFIG_DM_MMC=y
++CONFIG_DM_MTD=y
++CONFIG_DM_REGULATOR=y
++CONFIG_DM_REGULATOR_FIXED=y
++CONFIG_DM_REGULATOR_GPIO=y
++CONFIG_DM_USB=y
++CONFIG_DM_PWM=y
++CONFIG_PWM_MTK=y
++CONFIG_HUSH_PARSER=y
++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
++CONFIG_SYS_RELOC_GD_ENV_ADDR=y
++CONFIG_VERSION_VARIABLE=y
++CONFIG_PARTITION_UUIDS=y
++CONFIG_NETCONSOLE=y
++CONFIG_REGMAP=y
++CONFIG_SYSCON=y
++CONFIG_CLK=y
++CONFIG_DM_GPIO=y
++CONFIG_DM_SCSI=y
++CONFIG_AHCI=y
++CONFIG_AHCI_PCI=y
++CONFIG_SCSI_AHCI=y
++CONFIG_SCSI=y
++CONFIG_CMD_SCSI=y
++CONFIG_PHY=y
++CONFIG_PHY_MTK_TPHY=y
++CONFIG_PHY_ETHERNET_ID=y
++CONFIG_PHY_FIXED=y
++CONFIG_MTK_AHCI=y
++CONFIG_DM_ETH=y
++CONFIG_DM_ETH_PHY=y
++CONFIG_MEDIATEK_ETH=y
++CONFIG_PHY_AIROHA=y
++CONFIG_PHY_AIROHA_EN8811H=y
++CONFIG_PHY_AIROHA_FW_IN_MMC=y
++CONFIG_PCI=y
++CONFIG_MTD=y
++CONFIG_MTD_UBI_FASTMAP=y
++CONFIG_DM_PCI=y
++CONFIG_PCIE_MEDIATEK=y
++CONFIG_PINCTRL=y
++CONFIG_PINCONF=y
++CONFIG_PINCTRL_MT7622=y
++CONFIG_POWER_DOMAIN=y
++CONFIG_PRE_CONSOLE_BUFFER=y
++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
++CONFIG_MTK_POWER_DOMAIN=y
++CONFIG_RAM=y
++CONFIG_DM_SERIAL=y
++CONFIG_MTK_SERIAL=y
++CONFIG_MMC=y
++CONFIG_MMC_DEFAULT_DEV=1
++CONFIG_MMC_HS200_SUPPORT=y
++CONFIG_MMC_MTK=y
++CONFIG_MMC_SUPPORTS_TUNING=y
++CONFIG_SUPPORT_EMMC_BOOT=y
++CONFIG_SPI=y
++CONFIG_DM_SPI=y
++CONFIG_MTK_SPI_NAND=y
++CONFIG_MTK_SPI_NAND_MTD=y
++CONFIG_SYSRESET_WATCHDOG=y
++CONFIG_WDT_MTK=y
++CONFIG_LZO=y
++CONFIG_ZSTD=y
++CONFIG_HEXDUMP=y
++CONFIG_RANDOM_UUID=y
++CONFIG_REGEX=y
++CONFIG_USB=y
++CONFIG_USB_HOST=y
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_XHCI_MTK=y
++CONFIG_USB_STORAGE=y
++CONFIG_OF_EMBED=y
++CONFIG_ENV_OVERWRITE=y
++CONFIG_ENV_IS_IN_MMC=y
++CONFIG_ENV_OFFSET=0x400000
++CONFIG_ENV_OFFSET_REDUND=0x440000
++CONFIG_ENV_SIZE=0x40000
++CONFIG_ENV_SIZE_REDUND=0x40000
++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
++CONFIG_NET_RANDOM_ETHADDR=y
++CONFIG_REGMAP=y
++CONFIG_SYSCON=y
++CONFIG_CLK=y
++CONFIG_SUPPORT_EMMC_BOOT=y
++CONFIG_MMC_HS200_SUPPORT=y
++CONFIG_MMC_MTK=y
++CONFIG_MEDIATEK_ETH=y
++CONFIG_PINCTRL=y
++CONFIG_PINCONF=y
++CONFIG_PINCTRL_MT7986=y
++CONFIG_POWER_DOMAIN=y
++CONFIG_MTK_POWER_DOMAIN=y
++CONFIG_DM_REGULATOR=y
++CONFIG_DM_REGULATOR_FIXED=y
++CONFIG_DM_SERIAL=y
++CONFIG_MTK_SERIAL=y
++CONFIG_HEXDUMP=y
++CONFIG_USE_DEFAULT_ENV_FILE=y
++CONFIG_MTD_SPI_NAND=y
++CONFIG_MTK_SPIM=y
++#CONFIG_MTK_SNOR=y
++CONFIG_DM_SPI_FLASH=y
++CONFIG_SPI_FLASH_MTD=y
++CONFIG_SPI_FLASH_WINBOND=y
++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
++CONFIG_CMD_SF=y
++CONFIG_CMD_NAND=y
++CONFIG_CMD_NAND_TRIMFFS=y
++CONFIG_LMB_MAX_REGIONS=64
++CONFIG_USE_IPADDR=y
++CONFIG_IPADDR="192.168.1.1"
++CONFIG_USE_SERVERIP=y
++CONFIG_SERVERIP="192.168.1.254"
+--- /dev/null
++++ b/configs/mt7986a_bpi-r3-mini-snand_defconfig
+@@ -0,0 +1,203 @@
++CONFIG_ARM=y
++CONFIG_POSITION_INDEPENDENT=y
++CONFIG_ARCH_MEDIATEK=y
++CONFIG_TARGET_MT7986=y
++CONFIG_TEXT_BASE=0x41e00000
++CONFIG_SYS_MALLOC_F_LEN=0x4000
++CONFIG_SYS_HAS_NONCACHED_MEMORY=y
++CONFIG_NR_DRAM_BANKS=1
++CONFIG_DEFAULT_DEVICE_TREE="mt7986a-bpi-r3-mini"
++CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r3-mini_snand_env"
++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-bpi-r3-mini.dtb"
++CONFIG_OF_LIBFDT_OVERLAY=y
++CONFIG_OF_SYSTEM_SETUP=y
++CONFIG_DEBUG_UART_BASE=0x11002000
++CONFIG_DEBUG_UART_CLOCK=40000000
++CONFIG_DEBUG_UART=y
++CONFIG_SYS_LOAD_ADDR=0x46000000
++CONFIG_SMBIOS_PRODUCT_NAME=""
++CONFIG_AUTOBOOT_KEYED=y
++CONFIG_BOOTDELAY=30
++CONFIG_AUTOBOOT_MENU_SHOW=y
++CONFIG_CFB_CONSOLE_ANSI=y
++CONFIG_BOARD_LATE_INIT=y
++CONFIG_BUTTON=y
++CONFIG_BUTTON_GPIO=y
++CONFIG_GPIO_HOG=y
++CONFIG_CMD_ENV_FLAGS=y
++CONFIG_FIT=y
++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y
++CONFIG_LED=y
++CONFIG_LED_BLINK=y
++CONFIG_LED_GPIO=y
++CONFIG_LOGLEVEL=7
++CONFIG_LOG=y
++CONFIG_SYS_PROMPT="MT7986> "
++CONFIG_CMD_BOOTMENU=y
++CONFIG_CMD_BOOTP=y
++CONFIG_CMD_BUTTON=y
++CONFIG_CMD_CACHE=y
++CONFIG_CMD_CDP=y
++CONFIG_CMD_CPU=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_DM=y
++CONFIG_CMD_DNS=y
++CONFIG_CMD_ECHO=y
++CONFIG_CMD_ENV_READMEM=y
++CONFIG_CMD_ERASEENV=y
++CONFIG_CMD_EXT4=y
++CONFIG_CMD_FAT=y
++CONFIG_CMD_FDT=y
++CONFIG_CMD_FS_GENERIC=y
++CONFIG_CMD_FS_UUID=y
++CONFIG_CMD_GPIO=y
++CONFIG_CMD_GPT=y
++CONFIG_CMD_HASH=y
++CONFIG_CMD_ITEST=y
++CONFIG_CMD_LED=y
++CONFIG_CMD_LICENSE=y
++CONFIG_CMD_LINK_LOCAL=y
++# CONFIG_CMD_MBR is not set
++CONFIG_CMD_MDIO=y
++CONFIG_CMD_MII=y
++CONFIG_CMD_MMC=y
++CONFIG_CMD_MTD=y
++CONFIG_CMD_PCI=y
++CONFIG_CMD_PSTORE=y
++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000
++CONFIG_CMD_SF_TEST=y
++CONFIG_CMD_PING=y
++CONFIG_CMD_PXE=y
++CONFIG_CMD_PWM=y
++CONFIG_CMD_SMC=y
++CONFIG_CMD_TFTPBOOT=y
++CONFIG_CMD_TFTPSRV=y
++CONFIG_CMD_UBI=y
++CONFIG_CMD_UBI_RENAME=y
++CONFIG_CMD_UBIFS=y
++CONFIG_CMD_ASKENV=y
++CONFIG_CMD_PART=y
++CONFIG_CMD_RARP=y
++CONFIG_CMD_SETEXPR=y
++CONFIG_CMD_SLEEP=y
++CONFIG_CMD_SNTP=y
++CONFIG_CMD_SOURCE=y
++CONFIG_CMD_STRINGS=y
++CONFIG_CMD_USB=y
++CONFIG_CMD_UUID=y
++CONFIG_DISPLAY_CPUINFO=y
++CONFIG_DM_MMC=y
++CONFIG_DM_MTD=y
++CONFIG_DM_REGULATOR=y
++CONFIG_DM_REGULATOR_FIXED=y
++CONFIG_DM_REGULATOR_GPIO=y
++CONFIG_DM_USB=y
++CONFIG_DM_PWM=y
++CONFIG_PWM_MTK=y
++CONFIG_HUSH_PARSER=y
++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
++CONFIG_SYS_RELOC_GD_ENV_ADDR=y
++CONFIG_VERSION_VARIABLE=y
++CONFIG_PARTITION_UUIDS=y
++CONFIG_NETCONSOLE=y
++CONFIG_REGMAP=y
++CONFIG_SYSCON=y
++CONFIG_CLK=y
++CONFIG_DM_GPIO=y
++CONFIG_DM_SCSI=y
++CONFIG_AHCI=y
++CONFIG_AHCI_PCI=y
++CONFIG_SCSI_AHCI=y
++CONFIG_SCSI=y
++CONFIG_CMD_SCSI=y
++CONFIG_DM_MDIO=y
++CONFIG_PHY=y
++CONFIG_PHY_MTK_TPHY=y
++CONFIG_PHY_ETHERNET_ID=y
++CONFIG_PHY_FIXED=y
++CONFIG_MTK_AHCI=y
++CONFIG_DM_ETH=y
++CONFIG_DM_ETH_PHY=y
++CONFIG_MEDIATEK_ETH=y
++CONFIG_PCI=y
++CONFIG_MTD=y
++CONFIG_MTD_UBI_FASTMAP=y
++CONFIG_DM_PCI=y
++CONFIG_PCIE_MEDIATEK=y
++CONFIG_PINCTRL=y
++CONFIG_PINCONF=y
++CONFIG_PINCTRL_MT7622=y
++CONFIG_POWER_DOMAIN=y
++CONFIG_PRE_CONSOLE_BUFFER=y
++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
++CONFIG_MTK_POWER_DOMAIN=y
++CONFIG_RAM=y
++CONFIG_DM_SERIAL=y
++CONFIG_MTK_SERIAL=y
++CONFIG_MMC=y
++CONFIG_MMC_DEFAULT_DEV=1
++CONFIG_MMC_HS200_SUPPORT=y
++CONFIG_MMC_MTK=y
++CONFIG_MMC_SUPPORTS_TUNING=y
++CONFIG_SUPPORT_EMMC_BOOT=y
++CONFIG_SPI=y
++CONFIG_DM_SPI=y
++CONFIG_MTK_SPI_NAND=y
++CONFIG_MTK_SPI_NAND_MTD=y
++CONFIG_SYSRESET_WATCHDOG=y
++CONFIG_WDT_MTK=y
++CONFIG_LZO=y
++CONFIG_ZSTD=y
++CONFIG_HEXDUMP=y
++CONFIG_RANDOM_UUID=y
++CONFIG_REGEX=y
++CONFIG_USB=y
++CONFIG_USB_HOST=y
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_XHCI_MTK=y
++CONFIG_USB_STORAGE=y
++CONFIG_OF_EMBED=y
++CONFIG_ENV_OVERWRITE=y
++CONFIG_ENV_IS_IN_UBI=y
++CONFIG_ENV_UBI_PART="ubi"
++CONFIG_ENV_SIZE=0x1f000
++CONFIG_ENV_SIZE_REDUND=0x1f000
++CONFIG_ENV_UBI_VOLUME="ubootenv"
++CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2"
++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
++CONFIG_NET_RANDOM_ETHADDR=y
++CONFIG_REGMAP=y
++CONFIG_SYSCON=y
++CONFIG_CLK=y
++CONFIG_SUPPORT_EMMC_BOOT=y
++CONFIG_MMC_HS200_SUPPORT=y
++CONFIG_MMC_MTK=y
++CONFIG_MEDIATEK_ETH=y
++CONFIG_PHY_AIROHA=y
++CONFIG_PHY_AIROHA_EN8811H=y
++CONFIG_PHY_AIROHA_FW_IN_UBI=y
++CONFIG_PINCTRL=y
++CONFIG_PINCONF=y
++CONFIG_PINCTRL_MT7986=y
++CONFIG_POWER_DOMAIN=y
++CONFIG_MTK_POWER_DOMAIN=y
++CONFIG_DM_REGULATOR=y
++CONFIG_DM_REGULATOR_FIXED=y
++CONFIG_DM_SERIAL=y
++CONFIG_MTK_SERIAL=y
++CONFIG_HEXDUMP=y
++CONFIG_USE_DEFAULT_ENV_FILE=y
++CONFIG_MTD_SPI_NAND=y
++CONFIG_MTK_SPIM=y
++#CONFIG_MTK_SNOR=y
++#CONFIG_DM_SPI_FLASH=y
++#CONFIG_SPI_FLASH_MTD=y
++#CONFIG_SPI_FLASH_WINBOND=y
++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
++#CONFIG_CMD_SF=y
++CONFIG_CMD_NAND=y
++CONFIG_CMD_NAND_TRIMFFS=y
++CONFIG_LMB_MAX_REGIONS=64
++CONFIG_USE_IPADDR=y
++CONFIG_IPADDR="192.168.1.1"
++CONFIG_USE_SERVERIP=y
+--- /dev/null
++++ b/bananapi_bpi-r3-mini_snand_env
+@@ -0,0 +1,61 @@
++ipaddr=192.168.1.1
++serverip=192.168.1.254
++loadaddr=0x46000000
++console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0
++bootargs=root=ubi.block=0,fit root=/dev/fit0
++bootcmd=if pstore check ; then run boot_recovery ; else run boot_ubi ; fi
++bootconf=config-mt7986a-bananapi-bpi-r3-mini
++bootdelay=0
++bootfile=openwrt-mediatek-filogic-bananapi_bpi-r3-mini-initramfs-recovery.itb
++bootfile_bl2=openwrt-mediatek-filogic-bananapi_bpi-r3-mini-snand-preloader.bin
++bootfile_fip=openwrt-mediatek-filogic-bananapi_bpi-r3-mini-snand-bl31-uboot.fip
++bootfile_upg=openwrt-mediatek-filogic-bananapi_bpi-r3-mini-squashfs-sysupgrade.itb
++bootfile_en8811h_fw=EthMD32.bin
++bootled_pwr=green:status
++bootled_rec=blue:status
++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60
++bootmenu_default=0
++bootmenu_delay=0
++bootmenu_title=      ( ( ( OpenWrt ) ) )  [SPI-NAND]
++bootmenu_0=Initialize environment.=run _firstboot
++bootmenu_0d=Run default boot command.=run boot_default
++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return
++bootmenu_2=Boot production system from NAND.=run boot_production ; run bootmenu_confirm_return
++bootmenu_3=Boot recovery system from NAND.=run boot_recovery ; run bootmenu_confirm_return
++bootmenu_4=Load production system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return
++bootmenu_5=Load recovery system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return
++bootmenu_6=Load Airoha EN8811H firmware via TFTP then write to NAND.=run boot_tftp_write_en8811h_fw ; run bootmenu_confirm_return
++bootmenu_7=Load BL31+U-Boot FIP via TFTP then write to NAND.=run boot_tftp_write_fip ; run bootmenu_confirm_return
++bootmenu_8=Load BL2 preloader via TFTP then write to NAND.=run boot_tftp_write_bl2 ; run bootmenu_confirm_return
++bootmenu_9=Reboot.=reset
++bootmenu_10=Reset all settings to factory defaults.=run reset_factory ; reset
++boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu
++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever
++boot_production=led $bootled_pwr on ; run ubi_read_production && bootm $loadaddr#$bootconf ; led $bootled_pwr off
++boot_recovery=led $bootled_rec on ; run ubi_read_recovery && bootm $loadaddr#$bootconf ; led $bootled_rec off
++boot_ubi=run boot_production ; run boot_recovery
++boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done
++boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run ubi_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi
++boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run ubi_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi
++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf
++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run ubi_write_fip && run reset_factory
++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run snand_write_bl2
++boot_tftp_write_en8811h_fw=tftpboot $loadaddr $bootfile_en8811h_fw && run ubi_write_en8811h_fw
++part_default=production
++part_recovery=recovery
++reset_factory=mw $loadaddr 0xff 0x1f000 ; ubi write $loadaddr ubootenv 0x1f000 ; ubi write $loadaddr ubootenv2 0x1f000 ; ubi remove rootfs_data
++snand_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr 0x0 0x40000 && mtd write bl2 $loadaddr 0x40000 0x40000 && mtd write bl2 $loadaddr 0x80000 0x40000 && mtd write bl2 $loadaddr 0xc0000 0x40000
++ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x1f000 dynamic ; ubi check ubootenv2 || ubi create ubootenv2 0x1f000 dynamic
++ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi
++ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs
++ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery
++ubi_read_emmc_install=ubi check emmc_install && ubi read $loadaddr emmc_install
++ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data
++ubi_write_fip=run ubi_remove_rootfs ; ubi check fip && ubi remove fip ; ubi create fip 0x200000 static ; ubi write $loadaddr fip 0x200000
++ubi_write_en8811h_fw=ubi check en8811h-fw && ubi remove en8811h-fw ; ubi create en8811h-fw 0x24000 static ; ubi write $loadaddr en8811h-fw 0x24000
++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize
++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize
++_init_env=setenv _init_env ; run ubi_create_env ; saveenv ; saveenv
++_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first
++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title       $ver"
+--- /dev/null
++++ b/bananapi_bpi-r3-mini_emmc_env
+@@ -0,0 +1,59 @@
++ipaddr=192.168.1.1
++serverip=192.168.1.254
++loadaddr=0x46000000
++console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0
++bootargs=root=/dev/fit0
++bootcmd=if pstore check ; then run boot_recovery ; else run boot_emmc ; fi
++bootconf=config-mt7986a-bananapi-bpi-r3-mini
++bootdelay=0
++bootfile=openwrt-mediatek-filogic-bananapi_bpi-r3-mini-initramfs-recovery.itb
++bootfile_bl2=openwrt-mediatek-filogic-bananapi_bpi-r3-mini-emmc-preloader.bin
++bootfile_fip=openwrt-mediatek-filogic-bananapi_bpi-r3-mini-emmc-bl31-uboot.fip
++bootfile_upg=openwrt-mediatek-filogic-bananapi_bpi-r3-mini-squashfs-sysupgrade.itb
++bootfile_en8811h_fw=EthMD32.bin
++bootled_pwr=green:status
++bootled_rec=blue:status
++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60
++bootmenu_default=0
++bootmenu_delay=0
++bootmenu_title=      ( ( ( OpenWrt ) ) )  [eMMC]
++bootmenu_0=Initialize environment.=run _firstboot
++bootmenu_0d=Run default boot command.=run boot_default
++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return
++bootmenu_2=Boot production system from eMMC.=run boot_production ; run bootmenu_confirm_return
++bootmenu_3=Boot recovery system from eMMC.=run boot_recovery ; run bootmenu_confirm_return
++bootmenu_4=Load production system via TFTP then write to eMMC.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return
++bootmenu_5=Load recovery system via TFTP then write to eMMC.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return
++bootmenu_6=Load Airoha EN8811H firmware via TFTP then write to eMMC.=run boot_tftp_write_en8811h_fw ; run bootmenu_confirm_return
++bootmenu_7=Load BL31+U-Boot FIP via TFTP then write to eMMC.=run boot_tftp_write_fip ; run bootmenu_confirm_return
++bootmenu_8=Load BL2 preloader via TFTP then write to eMMC.=run boot_tftp_write_bl2 ; run bootmenu_confirm_return
++bootmenu_9=Reboot.=reset
++bootmenu_10=Reset all settings to factory defaults.=run reset_factory ; reset
++boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu
++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever
++boot_production=led $bootled_pwr on ; run emmc_read_production && bootm $loadaddr#$bootconf ; led $bootled_pwr off
++boot_recovery=led $bootled_rec on ; run emmc_read_recovery && bootm $loadaddr#$bootconf ; led $bootled_rec off
++boot_emmc=run boot_production ; run boot_recovery
++boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done
++boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run emmc_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi
++boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run emmc_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi
++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run emmc_write_fip
++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run emmc_write_bl2
++boot_tftp_write_en8811h_fw=tftpboot $loadaddr $bootfile_en8811h_fw && run emmc_write_en8811h_fw
++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf
++mmc_write_vol=imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$image_size && mmc write $loadaddr 0x$part_addr 0x$image_size
++mmc_read_vol=mmc read $loadaddr $part_addr 0x100 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr 0x$part_addr 0x$image_size && setexpr filesize $image_size * 0x200
++part_default=production
++part_recovery=recovery
++reset_factory=eraseenv && reset
++emmc_read_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_read_vol
++emmc_read_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_read_vol
++emmc_write_en8811h_fw=mmc partconf 0 1 2 2 && mmc erase 0x0 0x120 && mmc write $fileaddr 0x0 0x120 ; mmc partconf 0 1 1 0
++emmc_write_bl2=mmc partconf 0 1 1 1 && mmc erase 0x0 0x400 && mmc write $fileaddr 0x0 0x400 ; mmc partconf 0 1 1 0
++emmc_write_fip=mmc erase 0x3400 0x2000 && mmc write $fileaddr 0x3400 0x2000 && mmc erase 0x2000 0x800
++emmc_write_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_write_vol
++emmc_write_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_write_vol
++_init_env=setenv _init_env ; setenv _create_env ; saveenv ; saveenv
++_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first
++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title       $ver"
+--- /dev/null
++++ b/arch/arm/dts/mt7986a-bpi-r3-mini.dts
+@@ -0,0 +1,238 @@
++// SPDX-License-Identifier: GPL-2.0-or-later
++
++/dts-v1/;
++#include "mt7986.dtsi"
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/linux-event-codes.h>
++
++/ {
++	#address-cells = <1>;
++	#size-cells = <1>;
++	model = "Bananapi BPi-R3 Mini";
++	compatible = "mediatek,mt7986", "mediatek,mt7986-rfb";
++
++	chosen {
++		stdout-path = &uart0;
++		tick-timer = &timer0;
++	};
++
++	memory@40000000 {
++		device_type = "memory";
++		reg = <0x40000000 0x80000000>;
++	};
++
++	gpio-keys {
++		compatible = "gpio-keys";
++
++		button-reset {
++			label = "reset";
++			linux,code = <KEY_RESTART>;
++			gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
++		};
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		status_led: led-0 {
++			label = "green:status";
++			gpios = <&gpio 19 GPIO_ACTIVE_HIGH>;
++		};
++
++		led-1 {
++			label = "blue:wlan2g";
++			gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
++		};
++
++		led-2 {
++			label = "blue:wlan5g";
++			gpios = <&gpio 2 GPIO_ACTIVE_HIGH>;
++		};
++	};
++
++	reg_1p8v: regulator-1p8v {
++		compatible = "regulator-fixed";
++		regulator-name = "fixed-1.8V";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		regulator-boot-on;
++		regulator-always-on;
++	};
++
++	reg_3p3v: regulator-3p3v {
++		compatible = "regulator-fixed";
++		regulator-name = "fixed-3.3V";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		regulator-boot-on;
++		regulator-always-on;
++	};
++};
++
++&eth {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&mdio_pins>;
++
++	mediatek,gmac-id = <0>;
++	phy-mode = "2500base-x";
++	phy-handle = <&phy14>;
++
++	phy14: eth-phy@e {
++		compatible = "ethernet-phy-id03a2.a411";
++		reg = <14>;
++
++		airoha,rx-pol-reverse;
++
++		reset-gpios = <&gpio 49 GPIO_ACTIVE_LOW>;
++		reset-assert-us = <10000>;
++		reset-deassert-us = <20000>;
++	};
++};
++
++&mmc0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&mmc0_pins_default>;
++	bus-width = <8>;
++	max-frequency = <200000000>;
++	cap-mmc-highspeed;
++	cap-mmc-hw-reset;
++	vmmc-supply = <&reg_3p3v>;
++	vqmmc-supply = <&reg_1p8v>;
++	non-removable;
++	status = "okay";
++};
++
++&pinctrl {
++	mdio_pins: mdio-pins {
++		mux {
++			function = "eth";
++			groups = "mdc_mdio";
++		};
++
++		conf-en8811-pwr-a {
++			pins = "GPIO_11";
++			drive-strength = <MTK_DRIVE_8mA>;
++			bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
++			output-low;
++		};
++
++		conf-en8811-pwr-b {
++			pins = "GPIO_12";
++			drive-strength = <MTK_DRIVE_8mA>;
++			bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
++			output-low;
++		};
++	};
++
++	mmc0_pins_default: mmc0default {
++		mux {
++			function = "flash";
++			groups =  "emmc_51";
++		};
++
++		conf-cmd-dat {
++			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
++			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
++			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
++			input-enable;
++			drive-strength = <MTK_DRIVE_4mA>;
++			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
++		};
++
++		conf-clk {
++			pins = "EMMC_CK";
++			drive-strength = <MTK_DRIVE_6mA>;
++			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
++		};
++
++		conf-dsl {
++			pins = "EMMC_DSL";
++			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
++		};
++
++		conf-rst {
++			pins = "EMMC_RSTB";
++			drive-strength = <MTK_DRIVE_4mA>;
++			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
++		};
++	};
++
++	spi_flash_pins: spi0-pins-func-1 {
++		mux {
++			function = "flash";
++			groups = "spi0", "spi0_wp_hold";
++		};
++
++		conf-pu {
++			pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
++			drive-strength = <MTK_DRIVE_8mA>;
++			bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
++		};
++
++		conf-pd {
++			pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
++			drive-strength = <MTK_DRIVE_8mA>;
++			bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
++		};
++	};
++
++	pwm_pins: pwm0-pins-func-1 {
++		mux {
++			function = "pwm";
++			groups = "pwm0";
++		};
++	};
++};
++
++&pwm {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pwm_pins>;
++	status = "okay";
++};
++
++&spi0 {
++	#address-cells = <1>;
++	#size-cells = <0>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&spi_flash_pins>;
++	status = "okay";
++	must_tx;
++	enhance_timing;
++	dma_ext;
++	ipm_design;
++	support_quad;
++	tick_dly = <1>;
++	sample_sel = <0>;
++
++	spi_nand@0 {
++		compatible = "spi-nand";
++		reg = <0>;
++		spi-max-frequency = <20000000>;
++
++		partitions {
++			compatible = "fixed-partitions";
++			#address-cells = <1>;
++			#size-cells = <1>;
++
++			partition@0 {
++				label = "bl2";
++				reg = <0x0 0x200000>;
++			};
++
++			partition@200000 {
++				label = "ubi";
++				reg = <0x200000 0x7e00000>;
++			};
++		};
++	};
++
++};
++
++&uart0 {
++	status = "okay";
++};
++
++&watchdog {
++	status = "disabled";
++};
diff --git a/package/boot/uboot-mediatek/patches/450-add-bpi-r4.patch b/package/boot/uboot-mediatek/patches/450-add-bpi-r4.patch
new file mode 100644
index 00000000000000..c3c21fe2f50dba
--- /dev/null
+++ b/package/boot/uboot-mediatek/patches/450-add-bpi-r4.patch
@@ -0,0 +1,998 @@
+--- /dev/null
++++ b/configs/mt7988a_bananapi_bpi-r4-emmc_defconfig
+@@ -0,0 +1,180 @@
++CONFIG_ARM=y
++CONFIG_SYS_HAS_NONCACHED_MEMORY=y
++CONFIG_POSITION_INDEPENDENT=y
++CONFIG_ARCH_MEDIATEK=y
++CONFIG_TEXT_BASE=0x41e00000
++CONFIG_SYS_MALLOC_F_LEN=0x4000
++CONFIG_NR_DRAM_BANKS=1
++CONFIG_SYS_PROMPT="MT7988> "
++CONFIG_TARGET_MT7988=y
++CONFIG_DEBUG_UART_BASE=0x11000000
++CONFIG_DEBUG_UART_CLOCK=40000000
++CONFIG_SYS_LOAD_ADDR=0x50000000
++CONFIG_DEBUG_UART=y
++CONFIG_SYS_CBSIZE=512
++CONFIG_SYS_PBSIZE=1049
++CONFIG_DEFAULT_DEVICE_TREE="mt7988a-bananapi-bpi-r4-emmc"
++CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r4_emmc_env"
++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7988a-bpi-r4-emmc.dtb"
++CONFIG_OF_LIBFDT_OVERLAY=y
++CONFIG_OF_SYSTEM_SETUP=y
++CONFIG_SMBIOS_PRODUCT_NAME=""
++CONFIG_AUTOBOOT_KEYED=y
++CONFIG_BOOTDELAY=30
++CONFIG_AUTOBOOT_MENU_SHOW=y
++CONFIG_CFB_CONSOLE_ANSI=y
++CONFIG_BOARD_LATE_INIT=y
++CONFIG_BUTTON=y
++CONFIG_BUTTON_GPIO=y
++CONFIG_GPIO_HOG=y
++CONFIG_CMD_ENV_FLAGS=y
++CONFIG_FIT=y
++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y
++CONFIG_LED=y
++CONFIG_LED_BLINK=y
++CONFIG_LED_GPIO=y
++CONFIG_LOGLEVEL=7
++CONFIG_LOG=y
++CONFIG_CMD_BOOTMENU=y
++CONFIG_CMD_BOOTP=y
++CONFIG_CMD_BUTTON=y
++CONFIG_CMD_CACHE=y
++CONFIG_CMD_CDP=y
++CONFIG_CMD_CPU=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_DM=y
++CONFIG_CMD_DNS=y
++CONFIG_CMD_ECHO=y
++CONFIG_CMD_ENV_READMEM=y
++CONFIG_CMD_ERASEENV=y
++CONFIG_CMD_EXT4=y
++CONFIG_CMD_FAT=y
++CONFIG_CMD_FDT=y
++CONFIG_CMD_FS_GENERIC=y
++CONFIG_CMD_FS_UUID=y
++CONFIG_CMD_GPIO=y
++CONFIG_CMD_GPT=y
++CONFIG_CMD_HASH=y
++CONFIG_CMD_ITEST=y
++CONFIG_CMD_LED=y
++CONFIG_CMD_LICENSE=y
++CONFIG_CMD_LINK_LOCAL=y
++# CONFIG_CMD_MBR is not set
++CONFIG_CMD_MMC=y
++CONFIG_CMD_MTD=y
++CONFIG_CMD_PCI=y
++CONFIG_CMD_PSTORE=y
++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000
++CONFIG_CMD_SF_TEST=y
++CONFIG_CMD_PING=y
++CONFIG_CMD_PXE=y
++CONFIG_CMD_PWM=y
++CONFIG_CMD_SMC=y
++CONFIG_CMD_TFTPBOOT=y
++CONFIG_CMD_TFTPSRV=y
++CONFIG_CMD_UBI=y
++CONFIG_CMD_UBI_RENAME=y
++CONFIG_CMD_UBIFS=y
++CONFIG_CMD_ASKENV=y
++CONFIG_CMD_PART=y
++CONFIG_CMD_RARP=y
++CONFIG_CMD_SETEXPR=y
++CONFIG_CMD_SLEEP=y
++CONFIG_CMD_SNTP=y
++CONFIG_CMD_SOURCE=y
++CONFIG_CMD_STRINGS=y
++CONFIG_CMD_USB=y
++CONFIG_CMD_UUID=y
++CONFIG_DISPLAY_CPUINFO=y
++CONFIG_DM_MMC=y
++CONFIG_DM_MTD=y
++CONFIG_DM_REGULATOR=y
++CONFIG_DM_REGULATOR_FIXED=y
++CONFIG_DM_REGULATOR_GPIO=y
++CONFIG_DM_USB=y
++CONFIG_DM_PWM=y
++CONFIG_PWM_MTK=y
++CONFIG_HUSH_PARSER=y
++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
++CONFIG_SYS_RELOC_GD_ENV_ADDR=y
++CONFIG_VERSION_VARIABLE=y
++CONFIG_PARTITION_UUIDS=y
++CONFIG_NETCONSOLE=y
++CONFIG_DM_GPIO=y
++CONFIG_DM_SCSI=y
++CONFIG_AHCI=y
++CONFIG_AHCI_PCI=y
++CONFIG_SCSI_AHCI=y
++CONFIG_SCSI=y
++CONFIG_CMD_SCSI=y
++CONFIG_PHY=y
++CONFIG_PHY_MTK_TPHY=y
++CONFIG_MTK_AHCI=y
++CONFIG_PCI=y
++CONFIG_MTD=y
++CONFIG_MTD_UBI_FASTMAP=y
++CONFIG_DM_PCI=y
++CONFIG_PCIE_MEDIATEK=y
++CONFIG_PRE_CONSOLE_BUFFER=y
++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
++CONFIG_RAM=y
++CONFIG_DM_SERIAL=y
++CONFIG_MTK_SERIAL=y
++CONFIG_MMC=y
++CONFIG_MMC_DEFAULT_DEV=1
++CONFIG_MMC_SUPPORTS_TUNING=y
++CONFIG_SPI=y
++CONFIG_DM_SPI=y
++CONFIG_MTK_SPI_NAND=y
++CONFIG_MTK_SPI_NAND_MTD=y
++CONFIG_SYSRESET_WATCHDOG=y
++CONFIG_WDT_MTK=y
++CONFIG_LZO=y
++CONFIG_ZSTD=y
++CONFIG_HEXDUMP=y
++CONFIG_RANDOM_UUID=y
++CONFIG_REGEX=y
++CONFIG_USB=y
++CONFIG_USB_HOST=y
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_XHCI_MTK=y
++CONFIG_USB_STORAGE=y
++CONFIG_OF_EMBED=y
++CONFIG_ENV_OVERWRITE=y
++CONFIG_ENV_IS_IN_MMC=y
++CONFIG_ENV_OFFSET=0x400000
++CONFIG_ENV_OFFSET_REDUND=0x440000
++CONFIG_ENV_SIZE=0x40000
++CONFIG_ENV_SIZE_REDUND=0x40000
++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
++CONFIG_NET_RANDOM_ETHADDR=y
++CONFIG_REGMAP=y
++CONFIG_SYSCON=y
++CONFIG_CLK=y
++CONFIG_SUPPORT_EMMC_BOOT=y
++CONFIG_MMC_HS200_SUPPORT=y
++CONFIG_MMC_MTK=y
++CONFIG_PHY_FIXED=y
++CONFIG_DM_ETH=y
++CONFIG_MEDIATEK_ETH=y
++CONFIG_PINCTRL=y
++CONFIG_PINCONF=y
++CONFIG_PINCTRL_MT7988=y
++CONFIG_POWER_DOMAIN=y
++CONFIG_MTK_POWER_DOMAIN=y
++CONFIG_USE_DEFAULT_ENV_FILE=y
++CONFIG_MTD_SPI_NAND=y
++CONFIG_MTK_SPIM=y
++#CONFIG_MTK_SNOR=y
++CONFIG_DM_SPI_FLASH=y
++CONFIG_SPI_FLASH_MTD=y
++CONFIG_SPI_FLASH_WINBOND=y
++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
++CONFIG_CMD_SF=y
++CONFIG_CMD_NAND=y
++CONFIG_CMD_NAND_TRIMFFS=y
++CONFIG_LMB_MAX_REGIONS=64
++CONFIG_USE_IPADDR=y
++CONFIG_IPADDR="192.168.1.1"
++CONFIG_USE_SERVERIP=y
++CONFIG_SERVERIP="192.168.1.254"
+--- /dev/null
++++ b/configs/mt7988a_bananapi_bpi-r4-sdmmc_defconfig
+@@ -0,0 +1,180 @@
++CONFIG_ARM=y
++CONFIG_SYS_HAS_NONCACHED_MEMORY=y
++CONFIG_POSITION_INDEPENDENT=y
++CONFIG_ARCH_MEDIATEK=y
++CONFIG_TEXT_BASE=0x41e00000
++CONFIG_SYS_MALLOC_F_LEN=0x4000
++CONFIG_NR_DRAM_BANKS=1
++CONFIG_SYS_PROMPT="MT7988> "
++CONFIG_TARGET_MT7988=y
++CONFIG_DEBUG_UART_BASE=0x11000000
++CONFIG_DEBUG_UART_CLOCK=40000000
++CONFIG_SYS_LOAD_ADDR=0x50000000
++CONFIG_DEBUG_UART=y
++CONFIG_SYS_CBSIZE=512
++CONFIG_SYS_PBSIZE=1049
++CONFIG_DEFAULT_DEVICE_TREE="mt7988a-bananapi-bpi-r4-sd"
++CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r4_sdmmc_env"
++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7988a-bpi-r4-sd.dtb"
++CONFIG_OF_LIBFDT_OVERLAY=y
++CONFIG_OF_SYSTEM_SETUP=y
++CONFIG_SMBIOS_PRODUCT_NAME=""
++CONFIG_AUTOBOOT_KEYED=y
++CONFIG_BOOTDELAY=30
++CONFIG_AUTOBOOT_MENU_SHOW=y
++CONFIG_CFB_CONSOLE_ANSI=y
++CONFIG_BOARD_LATE_INIT=y
++CONFIG_BUTTON=y
++CONFIG_BUTTON_GPIO=y
++CONFIG_GPIO_HOG=y
++CONFIG_CMD_ENV_FLAGS=y
++CONFIG_FIT=y
++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y
++CONFIG_LED=y
++CONFIG_LED_BLINK=y
++CONFIG_LED_GPIO=y
++CONFIG_LOGLEVEL=7
++CONFIG_LOG=y
++CONFIG_CMD_BOOTMENU=y
++CONFIG_CMD_BOOTP=y
++CONFIG_CMD_BUTTON=y
++CONFIG_CMD_CACHE=y
++CONFIG_CMD_CDP=y
++CONFIG_CMD_CPU=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_DM=y
++CONFIG_CMD_DNS=y
++CONFIG_CMD_ECHO=y
++CONFIG_CMD_ENV_READMEM=y
++CONFIG_CMD_ERASEENV=y
++CONFIG_CMD_EXT4=y
++CONFIG_CMD_FAT=y
++CONFIG_CMD_FDT=y
++CONFIG_CMD_FS_GENERIC=y
++CONFIG_CMD_FS_UUID=y
++CONFIG_CMD_GPIO=y
++CONFIG_CMD_GPT=y
++CONFIG_CMD_HASH=y
++CONFIG_CMD_ITEST=y
++CONFIG_CMD_LED=y
++CONFIG_CMD_LICENSE=y
++CONFIG_CMD_LINK_LOCAL=y
++# CONFIG_CMD_MBR is not set
++CONFIG_CMD_MMC=y
++CONFIG_CMD_MTD=y
++CONFIG_CMD_PCI=y
++CONFIG_CMD_PSTORE=y
++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000
++CONFIG_CMD_SF_TEST=y
++CONFIG_CMD_PING=y
++CONFIG_CMD_PXE=y
++CONFIG_CMD_PWM=y
++CONFIG_CMD_SMC=y
++CONFIG_CMD_TFTPBOOT=y
++CONFIG_CMD_TFTPSRV=y
++CONFIG_CMD_UBI=y
++CONFIG_CMD_UBI_RENAME=y
++CONFIG_CMD_UBIFS=y
++CONFIG_CMD_ASKENV=y
++CONFIG_CMD_PART=y
++CONFIG_CMD_RARP=y
++CONFIG_CMD_SETEXPR=y
++CONFIG_CMD_SLEEP=y
++CONFIG_CMD_SNTP=y
++CONFIG_CMD_SOURCE=y
++CONFIG_CMD_STRINGS=y
++CONFIG_CMD_USB=y
++CONFIG_CMD_UUID=y
++CONFIG_DISPLAY_CPUINFO=y
++CONFIG_DM_MMC=y
++CONFIG_DM_MTD=y
++CONFIG_DM_REGULATOR=y
++CONFIG_DM_REGULATOR_FIXED=y
++CONFIG_DM_REGULATOR_GPIO=y
++CONFIG_DM_USB=y
++CONFIG_DM_PWM=y
++CONFIG_PWM_MTK=y
++CONFIG_HUSH_PARSER=y
++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
++CONFIG_SYS_RELOC_GD_ENV_ADDR=y
++CONFIG_VERSION_VARIABLE=y
++CONFIG_PARTITION_UUIDS=y
++CONFIG_NETCONSOLE=y
++CONFIG_DM_GPIO=y
++CONFIG_DM_SCSI=y
++CONFIG_AHCI=y
++CONFIG_AHCI_PCI=y
++CONFIG_SCSI_AHCI=y
++CONFIG_SCSI=y
++CONFIG_CMD_SCSI=y
++CONFIG_PHY=y
++CONFIG_PHY_MTK_TPHY=y
++CONFIG_MTK_AHCI=y
++CONFIG_PCI=y
++CONFIG_MTD=y
++CONFIG_MTD_UBI_FASTMAP=y
++CONFIG_DM_PCI=y
++CONFIG_PCIE_MEDIATEK=y
++CONFIG_PRE_CONSOLE_BUFFER=y
++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
++CONFIG_RAM=y
++CONFIG_DM_SERIAL=y
++CONFIG_MTK_SERIAL=y
++CONFIG_MMC=y
++CONFIG_MMC_DEFAULT_DEV=1
++CONFIG_MMC_SUPPORTS_TUNING=y
++CONFIG_SPI=y
++CONFIG_DM_SPI=y
++CONFIG_MTK_SPI_NAND=y
++CONFIG_MTK_SPI_NAND_MTD=y
++CONFIG_SYSRESET_WATCHDOG=y
++CONFIG_WDT_MTK=y
++CONFIG_LZO=y
++CONFIG_ZSTD=y
++CONFIG_HEXDUMP=y
++CONFIG_RANDOM_UUID=y
++CONFIG_REGEX=y
++CONFIG_USB=y
++CONFIG_USB_HOST=y
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_XHCI_MTK=y
++CONFIG_USB_STORAGE=y
++CONFIG_OF_EMBED=y
++CONFIG_ENV_OVERWRITE=y
++CONFIG_ENV_IS_IN_MMC=y
++CONFIG_ENV_OFFSET=0x400000
++CONFIG_ENV_OFFSET_REDUND=0x440000
++CONFIG_ENV_SIZE=0x40000
++CONFIG_ENV_SIZE_REDUND=0x40000
++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
++CONFIG_NET_RANDOM_ETHADDR=y
++CONFIG_REGMAP=y
++CONFIG_SYSCON=y
++CONFIG_CLK=y
++CONFIG_SUPPORT_EMMC_BOOT=y
++CONFIG_MMC_HS200_SUPPORT=y
++CONFIG_MMC_MTK=y
++CONFIG_PHY_FIXED=y
++CONFIG_DM_ETH=y
++CONFIG_MEDIATEK_ETH=y
++CONFIG_PINCTRL=y
++CONFIG_PINCONF=y
++CONFIG_PINCTRL_MT7988=y
++CONFIG_POWER_DOMAIN=y
++CONFIG_MTK_POWER_DOMAIN=y
++CONFIG_USE_DEFAULT_ENV_FILE=y
++CONFIG_MTD_SPI_NAND=y
++CONFIG_MTK_SPIM=y
++#CONFIG_MTK_SNOR=y
++CONFIG_DM_SPI_FLASH=y
++CONFIG_SPI_FLASH_MTD=y
++CONFIG_SPI_FLASH_WINBOND=y
++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
++CONFIG_CMD_SF=y
++CONFIG_CMD_NAND=y
++CONFIG_CMD_NAND_TRIMFFS=y
++CONFIG_LMB_MAX_REGIONS=64
++CONFIG_USE_IPADDR=y
++CONFIG_IPADDR="192.168.1.1"
++CONFIG_USE_SERVERIP=y
++CONFIG_SERVERIP="192.168.1.254"
+--- /dev/null
++++ b/configs/mt7988a_bananapi_bpi-r4-snand_defconfig
+@@ -0,0 +1,182 @@
++CONFIG_ARM=y
++CONFIG_SYS_HAS_NONCACHED_MEMORY=y
++CONFIG_POSITION_INDEPENDENT=y
++CONFIG_ARCH_MEDIATEK=y
++CONFIG_TEXT_BASE=0x41e00000
++CONFIG_SYS_MALLOC_F_LEN=0x4000
++CONFIG_NR_DRAM_BANKS=1
++CONFIG_SYS_PROMPT="MT7988> "
++CONFIG_TARGET_MT7988=y
++CONFIG_DEBUG_UART_BASE=0x11000000
++CONFIG_DEBUG_UART_CLOCK=40000000
++CONFIG_SYS_LOAD_ADDR=0x50000000
++CONFIG_DEBUG_UART=y
++CONFIG_SYS_CBSIZE=512
++CONFIG_SYS_PBSIZE=1049
++CONFIG_DEFAULT_DEVICE_TREE="mt7988a-bananapi-bpi-r4-emmc"
++CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r4_snand_env"
++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7988a-bpi-r4-emmc.dtb"
++CONFIG_OF_LIBFDT_OVERLAY=y
++CONFIG_OF_SYSTEM_SETUP=y
++CONFIG_SMBIOS_PRODUCT_NAME=""
++CONFIG_AUTOBOOT_KEYED=y
++CONFIG_BOOTDELAY=30
++CONFIG_AUTOBOOT_MENU_SHOW=y
++CONFIG_CFB_CONSOLE_ANSI=y
++CONFIG_BOARD_LATE_INIT=y
++CONFIG_BUTTON=y
++CONFIG_BUTTON_GPIO=y
++CONFIG_GPIO_HOG=y
++CONFIG_CMD_ENV_FLAGS=y
++CONFIG_FIT=y
++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y
++CONFIG_LED=y
++CONFIG_LED_BLINK=y
++CONFIG_LED_GPIO=y
++CONFIG_LOGLEVEL=7
++CONFIG_LOG=y
++CONFIG_CMD_BOOTMENU=y
++CONFIG_CMD_BOOTP=y
++CONFIG_CMD_BUTTON=y
++CONFIG_CMD_CACHE=y
++CONFIG_CMD_CDP=y
++CONFIG_CMD_CPU=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_DM=y
++CONFIG_CMD_DNS=y
++CONFIG_CMD_ECHO=y
++CONFIG_CMD_ENV_READMEM=y
++CONFIG_CMD_ERASEENV=y
++CONFIG_CMD_EXT4=y
++CONFIG_CMD_FAT=y
++CONFIG_CMD_FDT=y
++CONFIG_CMD_FS_GENERIC=y
++CONFIG_CMD_FS_UUID=y
++CONFIG_CMD_GPIO=y
++CONFIG_CMD_GPT=y
++CONFIG_CMD_HASH=y
++CONFIG_CMD_ITEST=y
++CONFIG_CMD_LED=y
++CONFIG_CMD_LICENSE=y
++CONFIG_CMD_LINK_LOCAL=y
++# CONFIG_CMD_MBR is not set
++CONFIG_CMD_MMC=y
++CONFIG_CMD_MTD=y
++CONFIG_CMD_PCI=y
++CONFIG_CMD_PSTORE=y
++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000
++CONFIG_CMD_SF_TEST=y
++CONFIG_CMD_PING=y
++CONFIG_CMD_PXE=y
++CONFIG_CMD_PWM=y
++CONFIG_CMD_SMC=y
++CONFIG_CMD_TFTPBOOT=y
++CONFIG_CMD_TFTPSRV=y
++CONFIG_CMD_UBI=y
++CONFIG_CMD_UBI_RENAME=y
++CONFIG_CMD_UBIFS=y
++CONFIG_CMD_ASKENV=y
++CONFIG_CMD_PART=y
++CONFIG_CMD_RARP=y
++CONFIG_CMD_SETEXPR=y
++CONFIG_CMD_SLEEP=y
++CONFIG_CMD_SNTP=y
++CONFIG_CMD_SOURCE=y
++CONFIG_CMD_STRINGS=y
++CONFIG_CMD_USB=y
++CONFIG_CMD_UUID=y
++CONFIG_DISPLAY_CPUINFO=y
++CONFIG_DM_MMC=y
++CONFIG_DM_MTD=y
++CONFIG_DM_REGULATOR=y
++CONFIG_DM_REGULATOR_FIXED=y
++CONFIG_DM_REGULATOR_GPIO=y
++CONFIG_DM_USB=y
++CONFIG_DM_PWM=y
++CONFIG_PWM_MTK=y
++CONFIG_HUSH_PARSER=y
++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
++CONFIG_SYS_RELOC_GD_ENV_ADDR=y
++CONFIG_VERSION_VARIABLE=y
++CONFIG_PARTITION_UUIDS=y
++CONFIG_NETCONSOLE=y
++CONFIG_DM_GPIO=y
++CONFIG_DM_SCSI=y
++CONFIG_AHCI=y
++CONFIG_AHCI_PCI=y
++CONFIG_SCSI_AHCI=y
++CONFIG_SCSI=y
++CONFIG_CMD_SCSI=y
++CONFIG_PHY=y
++CONFIG_PHY_MTK_TPHY=y
++CONFIG_MTK_AHCI=y
++CONFIG_PCI=y
++CONFIG_MTD=y
++CONFIG_MTD_UBI_FASTMAP=y
++CONFIG_DM_PCI=y
++CONFIG_PCIE_MEDIATEK=y
++CONFIG_PINCTRL_MT7988=y
++CONFIG_PRE_CONSOLE_BUFFER=y
++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
++CONFIG_RAM=y
++CONFIG_DM_SERIAL=y
++CONFIG_MTK_SERIAL=y
++CONFIG_MMC=y
++CONFIG_MMC_DEFAULT_DEV=1
++CONFIG_MMC_SUPPORTS_TUNING=y
++CONFIG_SPI=y
++CONFIG_DM_SPI=y
++CONFIG_MTK_SPI_NAND=y
++CONFIG_MTK_SPI_NAND_MTD=y
++CONFIG_SYSRESET_WATCHDOG=y
++CONFIG_WDT_MTK=y
++CONFIG_LZO=y
++CONFIG_ZSTD=y
++CONFIG_HEXDUMP=y
++CONFIG_RANDOM_UUID=y
++CONFIG_REGEX=y
++CONFIG_USB=y
++CONFIG_USB_HOST=y
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_XHCI_MTK=y
++CONFIG_USB_STORAGE=y
++CONFIG_OF_EMBED=y
++CONFIG_ENV_OVERWRITE=y
++CONFIG_ENV_IS_IN_UBI=y
++CONFIG_ENV_UBI_PART="ubi"
++CONFIG_ENV_SIZE=0x1f000
++CONFIG_ENV_SIZE_REDUND=0x1f000
++CONFIG_ENV_UBI_VOLUME="ubootenv"
++CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2"
++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
++CONFIG_NET_RANDOM_ETHADDR=y
++CONFIG_REGMAP=y
++CONFIG_SYSCON=y
++CONFIG_CLK=y
++CONFIG_SUPPORT_EMMC_BOOT=y
++CONFIG_MMC_HS200_SUPPORT=y
++CONFIG_MMC_MTK=y
++CONFIG_PHY_FIXED=y
++CONFIG_DM_ETH=y
++CONFIG_MEDIATEK_ETH=y
++CONFIG_PINCTRL=y
++CONFIG_PINCONF=y
++CONFIG_PINCTRL_MT7988=y
++CONFIG_POWER_DOMAIN=y
++CONFIG_MTK_POWER_DOMAIN=y
++CONFIG_USE_DEFAULT_ENV_FILE=y
++CONFIG_MTD_SPI_NAND=y
++CONFIG_MTK_SPIM=y
++#CONFIG_MTK_SNOR=y
++CONFIG_DM_SPI_FLASH=y
++CONFIG_SPI_FLASH_MTD=y
++CONFIG_SPI_FLASH_WINBOND=y
++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
++CONFIG_CMD_SF=y
++CONFIG_CMD_NAND=y
++CONFIG_CMD_NAND_TRIMFFS=y
++CONFIG_LMB_MAX_REGIONS=64
++CONFIG_USE_IPADDR=y
++CONFIG_IPADDR="192.168.1.1"
++CONFIG_USE_SERVERIP=y
++CONFIG_SERVERIP="192.168.1.254"
+--- /dev/null
++++ b/bananapi_bpi-r4_sdmmc_env
+@@ -0,0 +1,66 @@
++ipaddr=192.168.1.1
++serverip=192.168.1.254
++loadaddr=0x50000000
++bootargs=console=ttyS0,115200n1 pci=pcie_bus_perf root=/dev/fit0
++bootcmd=if pstore check ; then run boot_recovery ; else run boot_sdmmc ; fi
++bootconf=config-mt7988a-bananapi-bpi-r4
++bootconf_sd=mt7988a-bananapi-bpi-r4-sd
++bootconf_emmc=mt7988a-bananapi-bpi-r4-emmc
++bootconf_extra=
++bootdelay=0
++bootfile=openwrt-mediatek-filogic-bananapi_bpi-r4-initramfs-recovery.itb
++bootfile_upg=openwrt-mediatek-filogic-bananapi_bpi-r4-squashfs-sysupgrade.itb
++bootled_pwr=green:status
++bootled_rec=blue:status
++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60
++bootmenu_default=0
++bootmenu_delay=0
++bootmenu_title=      ( ( ( OpenWrt ) ) )  [SD card]
++bootmenu_0=Initialize environment.=run _firstboot
++bootmenu_0d=Run default boot command.=run boot_default
++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return
++bootmenu_2=Boot production system from SD card.=run boot_production ; run bootmenu_confirm_return
++bootmenu_3=Boot recovery system from SD card.=run boot_recovery ; run bootmenu_confirm_return
++bootmenu_4=Load production system via TFTP then write to SD card.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return
++bootmenu_5=Load recovery system via TFTP then write to SD card.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return
++bootmenu_6=Install bootloader, recovery and production to NAND.=if nand info ; then run ubi_init ; else echo "NAND not detected" ; fi ; run bootmenu_confirm_return
++bootmenu_7=Reboot.=reset
++bootmenu_8=Reset all settings to factory defaults.=run reset_factory ; reset
++boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu
++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever
++boot_production=led $bootled_pwr on ; run sdmmc_read_production && bootm $loadaddr#$bootconf#$bootconf_sd#$bootconf_extra ; led $bootled_pwr off
++boot_recovery=led $bootled_rec on ; run sdmmc_read_recovery && bootm $loadaddr#$bootconf#$bootconf_emmc ; led $bootled_rec off
++boot_sdmmc=run boot_production ; run boot_recovery
++boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done
++boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run sdmmc_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf#$bootconf_sd#$bootconf_extra ; fi
++boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run sdmmc_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf#$bootconf_sd ; fi
++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf#$bootconf_sd
++mmc_write_vol=imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$image_size && mmc write $loadaddr 0x$part_addr 0x$image_size
++mmc_read_vol=mmc read $loadaddr $part_addr 0x100 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr 0x$part_addr 0x$image_size && setexpr filesize $image_size * 0x200
++part_default=production
++part_recovery=recovery
++reset_factory=eraseenv && reset
++sdmmc_read_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_read_vol
++sdmmc_read_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_read_vol
++sdmmc_read_snand_bl2=part start mmc 0 install part_addr && mmc read $loadaddr $part_addr 0x400
++sdmmc_read_snand_fip=part start mmc 0 install part_addr && setexpr offset $part_addr + 0x800 && mmc read $loadaddr $offset 0x1000
++sdmmc_read_emmc_install=part start mmc 0 install part_addr && setexpr offset $part_addr + 0x3800 && mmc read $loadaddr $offset 0x4000
++sdmmc_write_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_write_vol
++sdmmc_write_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_write_vol
++snand_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr 0x0 0x80000 && mtd write bl2 $loadaddr 0x80000 0x80000 && mtd write bl2 $loadaddr 0x100000 0x80000 && mtd write bl2 $loadaddr 0x180000 0x80000
++ubi_create_env=ubi create ubootenv 0x100000 dynamic 1 ; ubi create ubootenv2 0x100000 dynamic 2
++ubi_format=ubi detach ; mtd erase ubi && ubi part ubi
++ubi_init=run ubi_format && run ubi_init_bl && run ubi_create_env && run ubi_init_openwrt && run ubi_init_emmc_install
++ubi_init_openwrt=run sdmmc_read_recovery && iminfo $loadaddr && run ubi_write_recovery ; run sdmmc_read_production && iminfo $loadaddr && run ubi_write_production
++ubi_init_bl=run sdmmc_read_snand_bl2 && run snand_write_bl2 && run sdmmc_read_snand_fip && run ubi_write_fip
++ubi_init_emmc_install=run sdmmc_read_emmc_install && run ubi_write_emmc_install
++ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi
++ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data
++ubi_write_fip=run ubi_remove_rootfs ; ubi check fip && ubi remove fip ; ubi create fip 0x200000 static ; ubi write $loadaddr fip 0x200000
++ubi_write_emmc_install=ubi check emmc_install && ubi remove emmc_install ; ubi create emmc_install 0x800000 dynamic ; ubi write $loadaddr emmc_install 0x800000
++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize
++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize
++_init_env=setenv _init_env ; setenv _create_env ; saveenv ; saveenv
++_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first
++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title       $ver"
+--- /dev/null
++++ b/bananapi_bpi-r4_snand_env
+@@ -0,0 +1,67 @@
++ipaddr=192.168.1.1
++serverip=192.168.1.254
++loadaddr=0x50000000
++bootargs=console=ttyS0,115200n1 pci=pcie_bus_perf root=/dev/fit0 ubi.block=0,fit
++bootconf=config-mt7988a-bananapi-bpi-r4
++bootconf_extra=mt7988a-bananapi-bpi-r4-emmc
++bootcmd=if pstore check ; then run boot_recovery ; else run boot_ubi ; fi
++bootdelay=0
++bootfile=openwrt-mediatek-filogic-bananapi_bpi-r4-initramfs-recovery.itb
++bootfile_bl2=openwrt-mediatek-filogic-bananapi_bpi-r4-snand-preloader.bin
++bootfile_fip=openwrt-mediatek-filogic-bananapi_bpi-r4-snand-bl31-uboot.fip
++bootfile_upg=openwrt-mediatek-filogic-bananapi_bpi-r4-squashfs-sysupgrade.itb
++bootled_pwr=green:status
++bootled_rec=blue:status
++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60
++bootmenu_default=0
++bootmenu_delay=0
++bootmenu_title=      ( ( ( OpenWrt ) ) )  [SPI-NAND]
++bootmenu_0=Initialize environment.=run _firstboot
++bootmenu_0d=Run default boot command.=run boot_default
++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return
++bootmenu_2=Boot production system from NAND.=run boot_production ; run bootmenu_confirm_return
++bootmenu_3=Boot recovery system from NAND.=run boot_recovery ; run bootmenu_confirm_return
++bootmenu_4=Load production system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return
++bootmenu_5=Load recovery system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return
++bootmenu_6=Load BL31+U-Boot FIP via TFTP then write to NAND.=run boot_tftp_write_fip ; run bootmenu_confirm_return
++bootmenu_7=Load BL2 preloader via TFTP then write to NAND.=run boot_tftp_write_bl2 ; run bootmenu_confirm_return
++bootmenu_8=Install bootloader, recovery and production to eMMC.=if mmc partconf 0 ; then run emmc_init ; else echo "eMMC not detected" ; fi ; run bootmenu_confirm_return
++bootmenu_9=Reboot.=reset
++bootmenu_10=Reset all settings to factory defaults.=run reset_factory ; reset
++boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu
++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever
++boot_production=led $bootled_pwr on ; run ubi_read_production && bootm $loadaddr#$bootconf#$bootconf_extra ; led $bootled_pwr off
++boot_recovery=led $bootled_rec on ; run ubi_read_recovery && bootm $loadaddr#$bootconf ; led $bootled_rec off
++boot_ubi=run boot_production ; run boot_recovery
++boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done
++boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run ubi_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf#$bootconf_extra ; fi
++boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run ubi_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi
++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf
++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run ubi_write_fip && run reset_factory
++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run snand_write_bl2
++part_default=production
++part_recovery=recovery
++reset_factory=ubi part ubi ; mw $loadaddr 0x0 0x800 ; ubi write $loadaddr ubootenv 0x800 ; ubi write $loadaddr ubootenv2 0x800
++snand_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr 0x0 0x80000 && mtd write bl2 $loadaddr 0x80000 0x80000 && mtd write bl2 $loadaddr 0x100000 0x80000 && mtd write bl2 $loadaddr 0x180000 0x80000
++ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic 1 ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic 2
++ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi
++ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs
++ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery
++ubi_read_emmc_install=ubi check emmc_install && ubi read $loadaddr emmc_install
++ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data
++ubi_write_fip=run ubi_remove_rootfs ; ubi check fip && ubi remove fip ; ubi create fip 0x200000 static ; ubi write $loadaddr fip 0x200000
++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize
++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize
++mmc_write_vol=imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$image_size && mmc write $loadaddr 0x$part_addr 0x$image_size
++emmc_init=mmc dev 0 && mmc bootbus 0 0 0 0 && run emmc_init_bl && run emmc_init_openwrt ; env default bootcmd ; saveenv ; saveenv
++emmc_init_bl=run ubi_read_emmc_install && setenv fileaddr $loadaddr && run emmc_write_bl2 && setexpr fileaddr $loadaddr + 0x100000 && run emmc_write_fip && setexpr fileaddr $loadaddr + 0x500000 && run emmc_write_hdr
++emmc_init_openwrt=run ubi_read_recovery && iminfo $loadaddr && run emmc_write_recovery ; run ubi_read_production && iminfo $loadaddr && run emmc_write_production
++emmc_write_bl2=mmc partconf 0 1 1 1 && mmc erase 0x0 0x400 && mmc write $fileaddr 0x0 0x400 ; mmc partconf 0 1 1 0
++emmc_write_fip=mmc erase 0x3400 0x2000 && mmc write $fileaddr 0x3400 0x2000 && mmc erase 0x2000 0x800
++emmc_write_hdr=mmc erase 0x0 0x40 && mmc write $fileaddr 0x0 0x40
++emmc_write_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_write_vol
++emmc_write_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_write_vol
++_init_env=setenv _init_env ; run ubi_create_env ; saveenv ; saveenv
++_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first
++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title       $ver"
+--- /dev/null
++++ b/bananapi_bpi-r4_emmc_env
+@@ -0,0 +1,57 @@
++ipaddr=192.168.1.1
++serverip=192.168.1.254
++loadaddr=0x50000000
++bootargs=console=ttyS0,115200n1 pci=pcie_bus_perf root=/dev/fit0
++bootcmd=if pstore check ; then run boot_recovery ; else run boot_emmc ; fi
++bootconf=config-mt7988a-bananapi-bpi-r4
++bootconf_base=config-mt7988a-bananapi-bpi-r4
++bootconf_emmc=mt7988a-bananapi-bpi-r4-emmc
++bootconf_extra=
++bootdelay=0
++bootfile=openwrt-mediatek-filogic-bananapi_bpi-r4-initramfs-recovery.itb
++bootfile_bl2=openwrt-mediatek-filogic-bananapi_bpi-r4-emmc-preloader.bin
++bootfile_fip=openwrt-mediatek-filogic-bananapi_bpi-r4-emmc-bl31-uboot.fip
++bootfile_upg=openwrt-mediatek-filogic-bananapi_bpi-r4-squashfs-sysupgrade.itb
++bootled_pwr=green:status
++bootled_rec=blue:status
++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60
++bootmenu_default=0
++bootmenu_delay=0
++bootmenu_title=      ( ( ( OpenWrt ) ) )  [eMMC]
++bootmenu_0=Initialize environment.=run _firstboot
++bootmenu_0d=Run default boot command.=run boot_default
++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return
++bootmenu_2=Boot production system from eMMC.=run boot_production ; run bootmenu_confirm_return
++bootmenu_3=Boot recovery system from eMMC.=run boot_recovery ; run bootmenu_confirm_return
++bootmenu_4=Load production system via TFTP then write to eMMC.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return
++bootmenu_5=Load recovery system via TFTP then write to eMMC.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return
++bootmenu_6=Load BL31+U-Boot FIP via TFTP then write to eMMC.=run boot_tftp_write_fip ; run bootmenu_confirm_return
++bootmenu_7=Load BL2 preloader via TFTP then write to eMMC.=run boot_tftp_write_bl2 ; run bootmenu_confirm_return
++bootmenu_8=Reboot.=reset
++bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset
++boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu
++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever
++boot_production=led $bootled_pwr on ; run emmc_read_production && bootm $loadaddr#$bootconf#$bootconf_emmc#$bootconf_extra ; led $bootled_pwr off
++boot_recovery=led $bootled_rec on ; run emmc_read_recovery && bootm $loadaddr#$bootconf#$bootconf_emmc#$bootconf_extra ; led $bootled_rec off
++boot_emmc=run boot_production ; run boot_recovery
++boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done
++boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run emmc_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf#$bootconf_emmc#$bootconf_extra ; fi
++boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run emmc_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf#$bootconf_emmc ; fi
++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run emmc_write_fip
++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run emmc_write_bl2
++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf
++mmc_write_vol=imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$image_size && mmc write $loadaddr 0x$part_addr 0x$image_size
++mmc_read_vol=mmc read $loadaddr $part_addr 0x100 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr 0x$part_addr 0x$image_size && setexpr filesize $image_size * 0x200
++part_default=production
++part_recovery=recovery
++reset_factory=eraseenv && reset
++emmc_read_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_read_vol
++emmc_read_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_read_vol
++emmc_write_bl2=mmc partconf 0 1 1 1 && mmc erase 0x0 0x400 && mmc write $fileaddr 0x0 0x400 ; mmc partconf 0 1 1 0
++emmc_write_fip=mmc erase 0x3400 0x2000 && mmc write $fileaddr 0x3400 0x2000 && mmc erase 0x2000 0x800
++emmc_write_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_write_vol
++emmc_write_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_write_vol
++_init_env=setenv _init_env ; setenv _create_env ; saveenv ; saveenv
++_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first
++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title       $ver"
+--- /dev/null
++++ b/arch/arm/dts/mt7988a-bananapi-bpi-r4.dtsi
+@@ -0,0 +1,199 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2022 MediaTek Inc.
++ * Author: Sam Shih <sam.shih@mediatek.com>
++ */
++
++/dts-v1/;
++#include "mt7988.dtsi"
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/linux-event-codes.h>
++
++/ {
++	model = "Bananapi BPI-R4";
++	compatible = "bananapi,bpi-r4", "mediatek,mt7988";
++
++	chosen {
++		stdout-path = &uart0;
++	};
++
++	memory@40000000 {
++		device_type = "memory";
++		reg = <0 0x40000000 0 0x10000000>;
++	};
++
++	reg_3p3v: regulator-3p3v {
++		compatible = "regulator-fixed";
++		regulator-name = "fixed-3.3V";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		regulator-boot-on;
++		regulator-always-on;
++	};
++
++	reg_1p8v: regulator-1p8v {
++		compatible = "regulator-fixed";
++		regulator-name = "fixed-1.8V";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		regulator-boot-on;
++		regulator-always-on;
++	};
++
++	keys {
++		compatible = "gpio-keys";
++
++		wps {
++			label = "reset";
++			linux,code = <KEY_RESTART>;
++			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
++		};
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		led_status_green: led-green {
++			label = "green:status";
++			gpios = <&gpio 79 GPIO_ACTIVE_HIGH>;
++		};
++
++		led_status_blue: led-blue {
++			label = "blue:status";
++			gpios = <&gpio 63 GPIO_ACTIVE_HIGH>;
++		};
++	};
++};
++
++&uart0 {
++	status = "okay";
++};
++
++&i2c1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c1_pins>;
++	status = "okay";
++};
++
++&eth {
++	status = "okay";
++	mediatek,gmac-id = <0>;
++	phy-mode = "usxgmii";
++	mediatek,switch = "mt7988";
++
++	fixed-link {
++		speed = <1000>;
++		full-duplex;
++		pause;
++	};
++};
++
++&pinctrl {
++	i2c1_pins: i2c1-pins {
++		mux {
++			function = "i2c";
++			groups = "i2c1_0";
++		};
++	};
++
++	pwm_pins: pwm-pins {
++		mux {
++			function = "pwm";
++			groups = "pwm0", "pwm1", "pwm2", "pwm3", "pwm4",
++				 "pwm5", "pwm6", "pwm7";
++		};
++	};
++
++	spi0_pins: spi0-pins {
++		mux {
++			function = "spi";
++			groups = "spi0", "spi0_wp_hold";
++		};
++	};
++
++	mmc0_pins_default: mmc0default {
++		mux {
++			function = "flash";
++			groups =  "emmc_51";
++		};
++
++		conf-cmd-dat {
++			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
++			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
++			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
++			input-enable;
++		};
++
++		conf-clk {
++			pins = "EMMC_CK";
++		};
++
++		conf-dsl {
++			pins = "EMMC_DSL";
++		};
++
++		conf-rst {
++			pins = "EMMC_RSTB";
++		};
++	};
++
++	mmc1_pins_default: mmc1default {
++		mux {
++			function = "flash";
++			groups =  "emmc_45";
++		};
++
++		conf-cmd-dat {
++			pins = "SPI2_CSB", "SPI2_MISO", "SPI2_MOSI",
++			       "SPI2_CLK", "SPI2_HOLD";
++			input-enable;
++		};
++
++		conf-clk {
++			pins = "SPI2_WP";
++		};
++	};
++};
++
++&pwm {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pwm_pins>;
++	status = "okay";
++};
++
++&spi0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&spi0_pins>;
++	#address-cells = <1>;
++	#size-cells = <0>;
++	status = "okay";
++	must_tx;
++	enhance_timing;
++	dma_ext;
++	ipm_design;
++	support_quad;
++	tick_dly = <2>;
++	sample_sel = <0>;
++
++	spi_nand@0 {
++		compatible = "spi-nand";
++		reg = <0>;
++		spi-max-frequency = <52000000>;
++		partitions {
++			compatible = "fixed-partitions";
++			#address-cells = <1>;
++			#size-cells = <1>;
++
++			partition@0 {
++				label = "bl2";
++				reg = <0x0 0x200000>;
++			};
++
++			partition@200000 {
++				label = "ubi";
++				reg = <0x200000 0x7e00000>;
++				compatible = "linux,ubi";
++			};
++		};
++	};
++};
+--- /dev/null
++++ b/arch/arm/dts/mt7988a-bananapi-bpi-r4-sd.dts
+@@ -0,0 +1,19 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2022 MediaTek Inc.
++ * Author: Sam Shih <sam.shih@mediatek.com>
++ */
++
++/dts-v1/;
++#include "mt7988a-bananapi-bpi-r4.dtsi"
++
++&mmc0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&mmc1_pins_default>;
++	max-frequency = <52000000>;
++	bus-width = <4>;
++	cap-sd-highspeed;
++	vmmc-supply = <&reg_3p3v>;
++	vqmmc-supply = <&reg_3p3v>;
++	status = "okay";
++};
+--- /dev/null
++++ b/arch/arm/dts/mt7988a-bananapi-bpi-r4-emmc.dts
+@@ -0,0 +1,21 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2022 MediaTek Inc.
++ * Author: Sam Shih <sam.shih@mediatek.com>
++ */
++
++/dts-v1/;
++#include "mt7988a-bananapi-bpi-r4.dtsi"
++
++&mmc0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&mmc0_pins_default>;
++	max-frequency = <52000000>;
++	bus-width = <8>;
++	cap-mmc-highspeed;
++	cap-mmc-hw-reset;
++	vmmc-supply = <&reg_3p3v>;
++	vqmmc-supply = <&reg_1p8v>;
++	non-removable;
++	status = "okay";
++};
diff --git a/package/boot/uboot-mediatek/patches/500-board-mt7623-fix-mmc-detect.patch b/package/boot/uboot-mediatek/patches/500-board-mt7623-fix-mmc-detect.patch
deleted file mode 100644
index 2f0ed85e53f22d..00000000000000
--- a/package/boot/uboot-mediatek/patches/500-board-mt7623-fix-mmc-detect.patch
+++ /dev/null
@@ -1,21 +0,0 @@
---- a/board/mediatek/mt7623/mt7623_rfb.c
-+++ b/board/mediatek/mt7623/mt7623_rfb.c
-@@ -9,6 +9,7 @@
- #include <env.h>
- #include <init.h>
- #include <mmc.h>
-+#include <part.h>
- #include <asm/global_data.h>
- #include <linux/delay.h>
- 
-@@ -31,8 +32,9 @@ int mmc_get_boot_dev(void)
- {
- 	int g_mmc_devid = -1;
- 	char *uflag = (char *)0x81DFFFF0;
-+	struct blk_desc *desc;
- 
--	if (!find_mmc_device(1))
-+	if (blk_get_device_by_str("mmc", "1", &desc) < 0)
- 		return 0;
- 
- 	if (strncmp(uflag,"eMMC",4)==0) {
diff --git a/package/boot/uboot-rockchip/Makefile b/package/boot/uboot-rockchip/Makefile
index 71eac09d98ba39..c9b3bbd3ac1f2a 100644
--- a/package/boot/uboot-rockchip/Makefile
+++ b/package/boot/uboot-rockchip/Makefile
@@ -39,6 +39,13 @@ define U-Boot/nanopi-r2c-rk3328
     friendlyarm_nanopi-r2c
 endef
 
+define U-Boot/nanopi-r2c-plus-rk3328
+  $(U-Boot/rk3328/Default)
+  NAME:=NanoPi R2C Plus
+  BUILD_DEVICES:= \
+    friendlyarm_nanopi-r2c-plus
+endef
+
 define U-Boot/nanopi-r2s-rk3328
   $(U-Boot/rk3328/Default)
   NAME:=NanoPi R2S
@@ -100,7 +107,8 @@ define U-Boot/nanopi-r4s-rk3399
   $(U-Boot/rk3399/Default)
   NAME:=NanoPi R4S
   BUILD_DEVICES:= \
-    friendlyarm_nanopi-r4s
+    friendlyarm_nanopi-r4s \
+    friendlyarm_nanopi-r4s-enterprise
 endef
 
 define U-Boot/rock-pi-4-rk3399
@@ -118,6 +126,22 @@ define U-Boot/rockpro64-rk3399
 endef
 
 
+# RK3566 boards
+
+define U-Boot/rk3566/Default
+  BUILD_SUBTARGET:=armv8
+  DEPENDS:=+PACKAGE_u-boot-$(1):trusted-firmware-a-rk3566
+  ATF:=rk3568_bl31_v1.43.elf
+  TPL:=rk3566_ddr_1056MHz_v1.18.bin
+endef
+
+define U-Boot/radxa-cm3-io-rk3566
+  $(U-Boot/rk3566/Default)
+  NAME:=CM3 IO
+  BUILD_DEVICES:= \
+    radxa_cm3-io
+endef
+
 # RK3568 boards
 
 define U-Boot/rk3568/Default
@@ -147,12 +171,14 @@ UBOOT_TARGETS := \
   rock-pi-4-rk3399 \
   rockpro64-rk3399 \
   nanopi-r2c-rk3328 \
+  nanopi-r2c-plus-rk3328 \
   nanopi-r2s-rk3328 \
   orangepi-r1-plus-rk3328 \
   orangepi-r1-plus-lts-rk3328 \
   roc-cc-rk3328 \
   rock64-rk3328 \
   rock-pi-e-rk3328 \
+  radxa-cm3-io-rk3566 \
   nanopi-r5c-rk3568 \
   nanopi-r5s-rk3568
 
@@ -164,7 +190,6 @@ UBOOT_CUSTOMIZE_CONFIG := \
 	--set-str MKIMAGE_DTC_PATH $(PKG_BUILD_DIR)/scripts/dtc/dtc
 
 UBOOT_MAKE_FLAGS += \
-  PATH=$(STAGING_DIR_HOST)/bin:$(PATH) \
   BL31=$(STAGING_DIR_IMAGE)/$(ATF) \
   $(if $(TPL),ROCKCHIP_TPL=$(STAGING_DIR_IMAGE)/$(TPL))
 
diff --git a/package/boot/uboot-rockchip/patches/001-board-rockchip-Add-support-for-FriendlyARM-NanoPi-R2C-Plu.patch b/package/boot/uboot-rockchip/patches/001-board-rockchip-Add-support-for-FriendlyARM-NanoPi-R2C-Plu.patch
new file mode 100644
index 00000000000000..25e063bfa98c94
--- /dev/null
+++ b/package/boot/uboot-rockchip/patches/001-board-rockchip-Add-support-for-FriendlyARM-NanoPi-R2C-Plu.patch
@@ -0,0 +1,213 @@
+From 0bc16c6a8744a1c0293a31253020205b312895d3 Mon Sep 17 00:00:00 2001
+From: Tianling Shen <cnsztl@gmail.com>
+Date: Sat, 23 Dec 2023 12:00:07 +0800
+Subject: [PATCH] board: rockchip: Add support for FriendlyARM NanoPi R2C Plus
+
+The NanoPi R2C Plus is a small variant of NanoPi R2C with a on-board
+eMMC flash (8G) included.
+
+The device tree is taken from the kernel v6.5.
+
+Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
+---
+ arch/arm/dts/Makefile                         |   1 +
+ .../dts/rk3328-nanopi-r2c-plus-u-boot.dtsi    |   9 ++
+ arch/arm/dts/rk3328-nanopi-r2c-plus.dts       |  33 +++++
+ board/rockchip/evb_rk3328/MAINTAINERS         |   6 +
+ configs/nanopi-r2c-plus-rk3328_defconfig      | 114 ++++++++++++++++++
+ 5 files changed, 163 insertions(+)
+ create mode 100644 arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi
+ create mode 100644 arch/arm/dts/rk3328-nanopi-r2c-plus.dts
+ create mode 100644 configs/nanopi-r2c-plus-rk3328_defconfig
+
+--- a/arch/arm/dts/Makefile
++++ b/arch/arm/dts/Makefile
+@@ -126,6 +126,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \
+ dtb-$(CONFIG_ROCKCHIP_RK3328) += \
+ 	rk3328-evb.dtb \
+ 	rk3328-nanopi-r2c.dtb \
++	rk3328-nanopi-r2c-plus.dtb \
+ 	rk3328-nanopi-r2s.dtb \
+ 	rk3328-orangepi-r1-plus.dtb \
+ 	rk3328-orangepi-r1-plus-lts.dtb \
+--- /dev/null
++++ b/arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi
+@@ -0,0 +1,9 @@
++// SPDX-License-Identifier: GPL-2.0-or-later
++
++#include "rk3328-nanopi-r2c-u-boot.dtsi"
++
++/ {
++	chosen {
++		u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
++	};
++};
+--- /dev/null
++++ b/arch/arm/dts/rk3328-nanopi-r2c-plus.dts
+@@ -0,0 +1,33 @@
++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
++/*
++ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
++ * (http://www.friendlyarm.com)
++ *
++ * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
++ */
++
++/dts-v1/;
++#include "rk3328-nanopi-r2c.dts"
++
++/ {
++	model = "FriendlyElec NanoPi R2C Plus";
++	compatible = "friendlyarm,nanopi-r2c-plus", "rockchip,rk3328";
++
++	aliases {
++		mmc1 = &emmc;
++	};
++};
++
++&emmc {
++	bus-width = <8>;
++	cap-mmc-highspeed;
++	max-frequency = <150000000>;
++	mmc-ddr-1_8v;
++	mmc-hs200-1_8v;
++	non-removable;
++	pinctrl-names = "default";
++	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
++	vmmc-supply = <&vcc_io_33>;
++	vqmmc-supply = <&vcc18_emmc>;
++	status = "okay";
++};
+--- a/board/rockchip/evb_rk3328/MAINTAINERS
++++ b/board/rockchip/evb_rk3328/MAINTAINERS
+@@ -11,6 +11,12 @@ S:      Maintained
+ F:      configs/nanopi-r2c-rk3328_defconfig
+ F:      arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi
+ 
++NANOPI-R2C-PLUS-RK3328
++M:      Tianling Shen <cnsztl@gmail.com>
++S:      Maintained
++F:      configs/nanopi-r2c-plus-rk3328_defconfig
++F:      arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi
++
+ NANOPI-R2S-RK3328
+ M:      David Bauer <mail@david-bauer.net>
+ S:      Maintained
+--- /dev/null
++++ b/configs/nanopi-r2c-plus-rk3328_defconfig
+@@ -0,0 +1,114 @@
++CONFIG_ARM=y
++CONFIG_SKIP_LOWLEVEL_INIT=y
++CONFIG_COUNTER_FREQUENCY=24000000
++CONFIG_ARCH_ROCKCHIP=y
++CONFIG_TEXT_BASE=0x00200000
++CONFIG_SPL_GPIO=y
++CONFIG_NR_DRAM_BANKS=1
++CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
++CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
++CONFIG_SF_DEFAULT_SPEED=20000000
++CONFIG_ENV_OFFSET=0x3F8000
++CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2c-plus"
++CONFIG_DM_RESET=y
++CONFIG_ROCKCHIP_RK3328=y
++CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
++CONFIG_TPL_LIBCOMMON_SUPPORT=y
++CONFIG_TPL_LIBGENERIC_SUPPORT=y
++CONFIG_SPL_DRIVERS_MISC=y
++CONFIG_SPL_STACK_R_ADDR=0x600000
++CONFIG_SPL_STACK=0x400000
++CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
++CONFIG_DEBUG_UART_BASE=0xFF130000
++CONFIG_DEBUG_UART_CLOCK=24000000
++CONFIG_SYS_LOAD_ADDR=0x800800
++CONFIG_DEBUG_UART=y
++# CONFIG_ANDROID_BOOT_IMAGE is not set
++CONFIG_FIT=y
++CONFIG_FIT_VERBOSE=y
++CONFIG_SPL_LOAD_FIT=y
++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2c-plus.dtb"
++# CONFIG_DISPLAY_CPUINFO is not set
++CONFIG_DISPLAY_BOARDINFO_LATE=y
++CONFIG_MISC_INIT_R=y
++CONFIG_SPL_MAX_SIZE=0x40000
++CONFIG_SPL_PAD_TO=0x7f8000
++CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
++CONFIG_SPL_BSS_START_ADDR=0x2000000
++CONFIG_SPL_BSS_MAX_SIZE=0x2000
++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
++# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
++CONFIG_SPL_STACK_R=y
++CONFIG_SPL_I2C=y
++CONFIG_SPL_POWER=y
++CONFIG_SPL_ATF=y
++CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
++CONFIG_TPL_SYS_MALLOC_SIMPLE=y
++CONFIG_CMD_BOOTZ=y
++CONFIG_CMD_GPT=y
++CONFIG_CMD_MMC=y
++CONFIG_CMD_USB=y
++# CONFIG_CMD_SETEXPR is not set
++CONFIG_CMD_TIME=y
++CONFIG_SPL_OF_CONTROL=y
++CONFIG_TPL_OF_CONTROL=y
++CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
++CONFIG_TPL_OF_PLATDATA=y
++CONFIG_ENV_IS_IN_MMC=y
++CONFIG_SYS_RELOC_GD_ENV_ADDR=y
++CONFIG_SYS_MMC_ENV_DEV=1
++CONFIG_NET_RANDOM_ETHADDR=y
++CONFIG_TPL_DM=y
++CONFIG_REGMAP=y
++CONFIG_SPL_REGMAP=y
++CONFIG_TPL_REGMAP=y
++CONFIG_SYSCON=y
++CONFIG_SPL_SYSCON=y
++CONFIG_TPL_SYSCON=y
++CONFIG_CLK=y
++CONFIG_SPL_CLK=y
++CONFIG_FASTBOOT_BUF_ADDR=0x800800
++CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
++CONFIG_ROCKCHIP_GPIO=y
++CONFIG_SYS_I2C_ROCKCHIP=y
++CONFIG_MISC=y
++CONFIG_MMC_DW=y
++CONFIG_MMC_DW_ROCKCHIP=y
++CONFIG_ETH_DESIGNWARE=y
++CONFIG_GMAC_ROCKCHIP=y
++CONFIG_PHY_ROCKCHIP_INNO_USB2=y
++CONFIG_PINCTRL=y
++CONFIG_SPL_PINCTRL=y
++CONFIG_DM_PMIC=y
++CONFIG_PMIC_RK8XX=y
++CONFIG_SPL_PMIC_RK8XX=y
++CONFIG_SPL_DM_REGULATOR=y
++CONFIG_REGULATOR_PWM=y
++CONFIG_DM_REGULATOR_FIXED=y
++CONFIG_SPL_DM_REGULATOR_FIXED=y
++CONFIG_REGULATOR_RK8XX=y
++CONFIG_PWM_ROCKCHIP=y
++CONFIG_RAM=y
++CONFIG_SPL_RAM=y
++CONFIG_TPL_RAM=y
++CONFIG_BAUDRATE=1500000
++CONFIG_DEBUG_UART_SHIFT=2
++CONFIG_SYS_NS16550_MEM32=y
++CONFIG_SYSINFO=y
++CONFIG_SYSRESET=y
++# CONFIG_TPL_SYSRESET is not set
++CONFIG_USB=y
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_EHCI_HCD=y
++CONFIG_USB_EHCI_GENERIC=y
++CONFIG_USB_OHCI_HCD=y
++CONFIG_USB_OHCI_GENERIC=y
++CONFIG_USB_DWC2=y
++CONFIG_USB_DWC3=y
++# CONFIG_USB_DWC3_GADGET is not set
++CONFIG_USB_DWC3_GENERIC=y
++CONFIG_USB_GADGET=y
++CONFIG_USB_GADGET_DWC2_OTG=y
++CONFIG_SPL_TINY_MEMSET=y
++CONFIG_TPL_TINY_MEMSET=y
++CONFIG_ERRNO_STR=y
diff --git a/package/devel/binutils/Makefile b/package/devel/binutils/Makefile
index 3a54a0be92c672..3fb281c2edd3b5 100644
--- a/package/devel/binutils/Makefile
+++ b/package/devel/binutils/Makefile
@@ -8,13 +8,13 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=binutils
-PKG_VERSION:=2.41
+PKG_VERSION:=2.42
 PKG_RELEASE:=1
 
 PKG_SOURCE_URL:=@GNU/binutils
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
 PKG_VERSION:=$(PKG_VERSION)
-PKG_HASH:=ae9a5789e23459e59606e6714723f2d3ffc31c03174191ef0d015bdf06007450
+PKG_HASH:=f6e4d41fd5fc778b06b7891457b3620da5ecea1006c6a4a41ae998109f85a800
 
 PKG_FIXUP:=patch-libtool
 PKG_LIBTOOL_PATHS:=. gas bfd opcodes gprof gprofng binutils ld libiberty gold intl libctf libsframe
diff --git a/package/devel/binutils/patches/001-replace-attribute_const.patch b/package/devel/binutils/patches/001-replace-attribute_const.patch
index 5fd855efd16423..dac641de110e80 100644
--- a/package/devel/binutils/patches/001-replace-attribute_const.patch
+++ b/package/devel/binutils/patches/001-replace-attribute_const.patch
@@ -28,8 +28,8 @@ unwind.c:490:3: note: in expansion of macro 'FILL_CONTEXT'
  	     unsigned int *ecx ATTRIBUTE_UNUSED, unsigned int *edx ATTRIBUTE_UNUSED)
 --- a/gprofng/libcollector/unwind.c
 +++ b/gprofng/libcollector/unwind.c
-@@ -233,7 +233,7 @@ memory_error_func (int status ATTRIBUTE_
- #elif ARCH(Aarch64)
+@@ -237,7 +237,7 @@ typedef uint64_t __u64;
+ 
  #define FILL_CONTEXT(context) \
      { CALL_UTIL (getcontext) (context);  \
 -      context->uc_mcontext.sp = (__u64) __builtin_frame_address(0); \
@@ -37,7 +37,7 @@ unwind.c:490:3: note: in expansion of macro 'FILL_CONTEXT'
      }
  
  #endif /* ARCH() */
-@@ -4579,11 +4579,11 @@ stack_unwind (char *buf, int size, void
+@@ -4583,11 +4583,11 @@ stack_unwind (char *buf, int size, void
    if (buf && bptr && eptr && context && size + mode > 0)
      getByteInstruction ((unsigned char *) eptr);
    int ind = 0;
@@ -54,7 +54,7 @@ unwind.c:490:3: note: in expansion of macro 'FILL_CONTEXT'
    unsigned long tbgn = 0;
    unsigned long tend = 0;
  
-@@ -4594,7 +4594,7 @@ stack_unwind (char *buf, int size, void
+@@ -4598,7 +4598,7 @@ stack_unwind (char *buf, int size, void
      {
        stack_base = sp + 0x100000;
        if (stack_base < sp)  // overflow
@@ -63,7 +63,7 @@ unwind.c:490:3: note: in expansion of macro 'FILL_CONTEXT'
      }
    DprintfT (SP_DUMP_UNWIND,
      "unwind.c:%d stack_unwind %2d pc=0x%llx  sp=0x%llx  stack_base=0x%llx\n",
-@@ -4625,17 +4625,17 @@ stack_unwind (char *buf, int size, void
+@@ -4629,17 +4629,17 @@ stack_unwind (char *buf, int size, void
  		      __LINE__, (unsigned long) sp);
  	    break;
  	  }
diff --git a/package/devel/strace/Makefile b/package/devel/strace/Makefile
index 8ff0ead807c78f..c4c395566b82a2 100644
--- a/package/devel/strace/Makefile
+++ b/package/devel/strace/Makefile
@@ -9,12 +9,12 @@ include $(TOPDIR)/rules.mk
 include $(INCLUDE_DIR)/kernel.mk
 
 PKG_NAME:=strace
-PKG_VERSION:=6.6
+PKG_VERSION:=6.7
 PKG_RELEASE:=1
 
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
 PKG_SOURCE_URL:=https://strace.io/files/$(PKG_VERSION)
-PKG_HASH:=421b4186c06b705163e64dc85f271ebdcf67660af8667283147d5e859fc8a96c
+PKG_HASH:=2090201e1a3ff32846f4fe421c1163b15f440bb38e31355d09f82d3949922af7
 
 PKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>
 PKG_LICENSE:=LGPL-2.1-or-later
diff --git a/package/firmware/ath11k-firmware/Makefile b/package/firmware/ath11k-firmware/Makefile
index ea4977aa68ca1e..384595f10d07c9 100644
--- a/package/firmware/ath11k-firmware/Makefile
+++ b/package/firmware/ath11k-firmware/Makefile
@@ -11,7 +11,7 @@ PKG_NAME:=ath11k-firmware
 PKG_SOURCE_DATE:=2023-08-22
 PKG_SOURCE_VERSION:=d8f82a98ff1aef330d65d8b5660b46d1a9809ee3
 PKG_MIRROR_HASH:=3dba19449758c3b17f117990d7ad4086554e012b579f1de16e9d9196a7fbaaa7
-PKG_RELEASE:=1
+PKG_RELEASE:=2
 
 PKG_SOURCE_PROTO:=git
 PKG_SOURCE_URL:=https://github.com/quic/upstream-wifi-fw.git
@@ -32,6 +32,11 @@ define Package/ath11k-firmware-default
   DEPENDS:=
 endef
 
+define Package/ath11k-firmware-ipq6018
+$(Package/ath11k-firmware-default)
+  TITLE:=IPQ6018 ath11k firmware
+endef
+
 define Package/ath11k-firmware-ipq8074
 $(Package/ath11k-firmware-default)
   TITLE:=IPQ8074 ath11k firmware
@@ -57,6 +62,28 @@ define Download/qcn9074-board
 endef
 $(eval $(call Download,qcn9074-board))
 
+define Download/ath11k-firmware-old
+  URL:=https://github.com/kvalo/ath11k-firmware.git
+  VERSION:=540105aa5c0903b5f773d4e80b8501e8da5217e7
+  PROTO:=git
+  FILE:=ath11k-firmware-old.tar.xz
+  SUBDIR:=ath11k-firmware-old
+  MIRROR_HASH:=a35a164726fab2adc4ad447c974c06746355ba74deab9b849d39f06b5187bb6d
+endef
+$(eval $(call Download,ath11k-firmware-old))
+
+define Build/Prepare
+	$(call Build/Prepare/Default)
+	xzcat $(DL_DIR)/ath11k-firmware-old.tar.xz | tar -C $(PKG_BUILD_DIR)/ -xf -
+endef
+
+define Package/ath11k-firmware-ipq6018/install
+	$(INSTALL_DIR) $(1)/lib/firmware/IPQ6018
+	$(INSTALL_DATA) \
+		$(PKG_BUILD_DIR)/ath11k-firmware-old/IPQ6018/hw1.0/2.4.0.1/WLAN.HK.2.4.0.1-01746-QCAHKSWPL_SILICONZ-1/* \
+		$(1)/lib/firmware/IPQ6018/
+endef
+
 define Package/ath11k-firmware-ipq8074/install
 	$(INSTALL_DIR) $(1)/lib/firmware/IPQ8074
 	$(INSTALL_DATA) \
@@ -73,5 +100,6 @@ define Package/ath11k-firmware-qcn9074/install
 		$(DL_DIR)/$(QCN9074_BOARD_FILE) $(1)/lib/firmware/ath11k/QCN9074/hw1.0/board-2.bin
 endef
 
+$(eval $(call BuildPackage,ath11k-firmware-ipq6018))
 $(eval $(call BuildPackage,ath11k-firmware-ipq8074))
 $(eval $(call BuildPackage,ath11k-firmware-qcn9074))
diff --git a/package/firmware/ipq-wifi/Makefile b/package/firmware/ipq-wifi/Makefile
index 5806654ecfb676..0da6b58b2c167b 100644
--- a/package/firmware/ipq-wifi/Makefile
+++ b/package/firmware/ipq-wifi/Makefile
@@ -6,9 +6,9 @@ PKG_RELEASE:=1
 
 PKG_SOURCE_PROTO:=git
 PKG_SOURCE_URL=$(PROJECT_GIT)/project/firmware/qca-wireless.git
-PKG_SOURCE_DATE:=2024-01-06
-PKG_SOURCE_VERSION:=71f45cff8944405b7cc2bf5c19df2bd8fe7f2421
-PKG_MIRROR_HASH:=90c3c1659c54cdb4685d0a71633746c1000230e459801eb8ce12c805a994cc37
+PKG_SOURCE_DATE:=2024-02-25
+PKG_SOURCE_VERSION:=fc30aeeb8ec5d069710a446f4eb5e30fc26145c1
+PKG_MIRROR_HASH:=7fe83e3f36541444e0385a56fa8a048772d0531e16787cc10bce29775c7db235
 
 PKG_FLAGS:=nonshared
 
@@ -28,13 +28,17 @@ endef
 # <https://wireless.wiki.kernel.org/en/users/drivers/ath10k/boardfiles>
 
 ALLWIFIBOARDS:= \
+	8devices_mango \
 	arcadyan_aw1000 \
 	buffalo_wxr-5950ax12 \
+	cmcc_rm2-6 \
 	compex_wpq873 \
 	dynalink_dl-wrx36 \
 	edgecore_eap102 \
 	edimax_cax1800 \
 	linksys_mx4200 \
+	linksys_mx5300 \
+	netgear_lbr20 \
 	netgear_rax120v2 \
 	netgear_wax218 \
 	netgear_wax620 \
@@ -84,12 +88,14 @@ define ipq-wifi-install-one
     $(call ipq-wifi-install-one-to,$(1),$(2),QCA9984/hw1.0),\
   $(if $(filter $(suffix $(1)),.QCA99X0 .qca99x0),\
     $(call ipq-wifi-install-one-to,$(1),$(2),QCA99X0/hw2.0),\
-  $(if $(filter $(suffix $(1)),.IPQ8074 .ipq8074 .ipq8174),\
+  $(if $(filter $(suffix $(1)),.IPQ6018 .ipq6018),\
+    $(call ipq-wifi-install-ath11-one-to,$(1),$(2),IPQ6018/hw1.0),\
+  $(if $(filter $(suffix $(1)),.IPQ8074 .ipq8074),\
     $(call ipq-wifi-install-ath11-one-to,$(1),$(2),IPQ8074/hw2.0),\
   $(if $(filter $(suffix $(1)),.QCN9074 .qcn9074),\
     $(call ipq-wifi-install-ath11-one-to,$(1),$(2),QCN9074/hw1.0),\
     $(error Unrecognized board-file suffix '$(suffix $(1))' for '$(1)')\
-  )))))))
+  ))))))))
 
 endef
 # Blank line required at end of above define due to foreach context
@@ -139,13 +145,17 @@ endef
 # Board files should follow this name structure:
 #   board-<devicename>.<qca4019|qca9888|qca9889|qca9984|qca99x0|ipq8074>
 
+$(eval $(call generate-ipq-wifi-package,8devices_mango,8devices Mango))
 $(eval $(call generate-ipq-wifi-package,arcadyan_aw1000,Arcadyan AW1000))
 $(eval $(call generate-ipq-wifi-package,buffalo_wxr-5950ax12,Buffalo WXR-5950AX12))
+$(eval $(call generate-ipq-wifi-package,cmcc_rm2-6,CMCC RM2-6))
 $(eval $(call generate-ipq-wifi-package,compex_wpq873,Compex WPQ-873))
 $(eval $(call generate-ipq-wifi-package,dynalink_dl-wrx36,Dynalink DL-WRX36))
 $(eval $(call generate-ipq-wifi-package,edgecore_eap102,Edgecore EAP102))
 $(eval $(call generate-ipq-wifi-package,edimax_cax1800,Edimax CAX1800))
 $(eval $(call generate-ipq-wifi-package,linksys_mx4200,Linksys MX4200))
+$(eval $(call generate-ipq-wifi-package,linksys_mx5300,Linksys MX5300))
+$(eval $(call generate-ipq-wifi-package,netgear_lbr20,Netgear LBR20))
 $(eval $(call generate-ipq-wifi-package,netgear_rax120v2,Netgear RAX120v2))
 $(eval $(call generate-ipq-wifi-package,netgear_wax218,Netgear WAX218))
 $(eval $(call generate-ipq-wifi-package,netgear_wax620,Netgear WAX620))
diff --git a/package/firmware/layerscape/ls-dpl/Makefile b/package/firmware/layerscape/ls-dpl/Makefile
index 6c53b4541700fa..7ceba620bb9538 100644
--- a/package/firmware/layerscape/ls-dpl/Makefile
+++ b/package/firmware/layerscape/ls-dpl/Makefile
@@ -8,13 +8,13 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=ls-dpl
-PKG_VERSION:=21.08
-PKG_RELEASE:=3
+PKG_VERSION:=10.38.0
+PKG_RELEASE:=1
 
 PKG_SOURCE_PROTO:=git
 PKG_SOURCE_URL:=https://github.com/nxp-qoriq/mc-utils
-PKG_SOURCE_VERSION:=LSDK-21.08
-PKG_MIRROR_HASH:=372498ff4b5c8a1ac64ead5856d03ee021332f57771989ed6fe066745372b242
+PKG_SOURCE_VERSION:=mc_release_10.38.0
+PKG_MIRROR_HASH:=c5032ad73a04cf7fa23a2afeee85108677e665871a6c48ca352f415eea9b6390
 
 PKG_FLAGS:=nonshared
 
diff --git a/package/firmware/layerscape/ls-mc/Makefile b/package/firmware/layerscape/ls-mc/Makefile
index 49cdfdc0625790..3ef5a783272cb3 100644
--- a/package/firmware/layerscape/ls-mc/Makefile
+++ b/package/firmware/layerscape/ls-mc/Makefile
@@ -8,13 +8,13 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=ls-mc
-PKG_VERSION:=21.08
-PKG_RELEASE:=3
+PKG_VERSION:=10.38.0
+PKG_RELEASE:=1
 
 PKG_SOURCE_PROTO:=git
 PKG_SOURCE_URL:=https://github.com/NXP/qoriq-mc-binary.git
-PKG_SOURCE_VERSION:=LSDK-21.08
-PKG_MIRROR_HASH:=ab22c16b2bce37886c15ffeed7b068e5b46d619eae58e5a6a005028f5ddb06b6
+PKG_SOURCE_VERSION:=mc_release_10.38.0
+PKG_MIRROR_HASH:=b4482690246f9bd6a8728c482fd391ccf9b25a104b02f08add6e5c5d43a5ad75
 
 PKG_FLAGS:=nonshared
 
@@ -32,11 +32,11 @@ endef
 
 define Build/InstallDev
 	$(INSTALL_DIR) $(STAGING_DIR_IMAGE)
-	$(CP) $(PKG_BUILD_DIR)/ls1088a/mc_ls1088a_10.28.1.itb \
+	$(CP) $(PKG_BUILD_DIR)/ls1088a/mc_ls1088a_$(PKG_VERSION).itb \
 		$(STAGING_DIR_IMAGE)/fsl_ls1088a-rdb-mc.itb
-	$(CP) $(PKG_BUILD_DIR)/ls2088a/mc_ls2088a_10.28.1.itb \
+	$(CP) $(PKG_BUILD_DIR)/ls2088a/mc_ls2088a_$(PKG_VERSION).itb \
 		$(STAGING_DIR_IMAGE)/fsl_ls2088a-rdb-mc.itb
-	$(CP) $(PKG_BUILD_DIR)/lx216xa/mc_lx2160a_10.28.1.itb \
+	$(CP) $(PKG_BUILD_DIR)/lx216xa/mc_lx2160a_$(PKG_VERSION).itb \
 		$(STAGING_DIR_IMAGE)/fsl_lx2160a-rdb-mc.itb
 endef
 
diff --git a/package/firmware/linux-firmware/airoha.mk b/package/firmware/linux-firmware/airoha.mk
new file mode 100644
index 00000000000000..ac64d11e41c03b
--- /dev/null
+++ b/package/firmware/linux-firmware/airoha.mk
@@ -0,0 +1,17 @@
+Package/airoha-en8811h-firmware = $(call Package/firmware-default,Airoha EN8811H 2.5G Ethernet PHY firmware)
+define Package/airoha-en8811h-firmware/install
+	$(INSTALL_DIR) $(1)/lib/firmware/airoha
+	$(CP) \
+		$(PKG_BUILD_DIR)/airoha/EthMD32.dm.bin \
+		$(PKG_BUILD_DIR)/airoha/EthMD32.DSP.bin \
+		$(1)/lib/firmware/airoha
+ifneq ($(CONFIG_TARGET_mediatek_filogic),)
+	$(INSTALL_DIR) $(STAGING_DIR_IMAGE)
+	cat \
+		$(PKG_BUILD_DIR)/airoha/EthMD32.dm.bin \
+		$(PKG_BUILD_DIR)/airoha/EthMD32.DSP.bin \
+		> $(STAGING_DIR_IMAGE)/EthMD32.bin
+endif
+endef
+
+$(eval $(call BuildPackage,airoha-en8811h-firmware))
diff --git a/package/firmware/linux-firmware/intel.mk b/package/firmware/linux-firmware/intel.mk
index 27b0d8ce64c456..19a96b2c85a09e 100644
--- a/package/firmware/linux-firmware/intel.mk
+++ b/package/firmware/linux-firmware/intel.mk
@@ -192,6 +192,14 @@ define Package/iwlwifi-firmware-ax210/install
 endef
 $(eval $(call BuildPackage,iwlwifi-firmware-ax210))
 
+Package/iwlwifi-firmware-be200 = $(call Package/firmware-default,Intel BE200 firmware)
+define Package/iwlwifi-firmware-be200/install
+	$(INSTALL_DIR) $(1)/lib/firmware
+	$(INSTALL_DATA) $(PKG_BUILD_DIR)/iwlwifi-gl-c0-fm-c0-83.ucode $(1)/lib/firmware
+	$(INSTALL_DATA) $(PKG_BUILD_DIR)/iwlwifi-gl-c0-fm-c0.pnvm $(1)/lib/firmware
+endef
+$(eval $(call BuildPackage,iwlwifi-firmware-be200))
+
 Package/e100-firmware = $(call Package/firmware-default,Intel e100)
 define Package/e100-firmware/install
 	$(INSTALL_DIR) $(1)/lib/firmware/e100
diff --git a/package/firmware/linux-firmware/mediatek.mk b/package/firmware/linux-firmware/mediatek.mk
index a0eccb8f4d5811..bf6bef22a6416c 100644
--- a/package/firmware/linux-firmware/mediatek.mk
+++ b/package/firmware/linux-firmware/mediatek.mk
@@ -87,3 +87,12 @@ define Package/mt7986-wo-firmware/install
 		$(1)/lib/firmware/mediatek
 endef
 $(eval $(call BuildPackage,mt7986-wo-firmware))
+
+Package/mt7988-2p5g-phy-firmware = $(call Package/firmware-default,MT7988 built-in 2.5G Ethernet PHY firmware)
+define Package/mt7988-2p5g-phy-firmware/install
+	$(INSTALL_DIR) $(1)/lib/firmware/mediatek/mt7988
+	$(INSTALL_DATA) \
+		$(PKG_BUILD_DIR)/mediatek/mt7988/i2p5ge-phy-pmb.bin \
+		$(1)/lib/firmware/mediatek/mt7988
+endef
+$(eval $(call BuildPackage,mt7988-2p5g-phy-firmware))
diff --git a/package/firmware/wireless-regdb/Makefile b/package/firmware/wireless-regdb/Makefile
index dfff35ff4d7edc..431d07c35b8cac 100644
--- a/package/firmware/wireless-regdb/Makefile
+++ b/package/firmware/wireless-regdb/Makefile
@@ -1,12 +1,12 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=wireless-regdb
-PKG_VERSION:=2023.09.01
+PKG_VERSION:=2024.01.23
 PKG_RELEASE:=1
 
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
 PKG_SOURCE_URL:=@KERNEL/software/network/wireless-regdb/
-PKG_HASH:=26d4c2a727cc59239b84735aad856b7c7d0b04e30aa5c235c4f7f47f5f053491
+PKG_HASH:=c8a61c9acf76fa7eb4239e89f640dee3e87098d9f69b4d3518c9c60fc6d20c55
 
 PKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>
 
@@ -16,7 +16,7 @@ define Package/wireless-regdb
   PKGARCH:=all
   SECTION:=firmware
   CATEGORY:=Firmware
-  URL:=https://git.kernel.org/pub/scm/linux/kernel/git/sforshee/wireless-regdb.git/
+  URL:=https://git.kernel.org/pub/scm/linux/kernel/git/wens/wireless-regdb.git/
   TITLE:=Wireless Regulatory Database
 endef
 
diff --git a/package/kernel/broadcom-wl/Makefile b/package/kernel/broadcom-wl/Makefile
deleted file mode 100644
index a1feacbe2901a4..00000000000000
--- a/package/kernel/broadcom-wl/Makefile
+++ /dev/null
@@ -1,192 +0,0 @@
-#
-# Copyright (C) 2006-2014 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-include $(TOPDIR)/rules.mk
-include $(INCLUDE_DIR)/kernel.mk
-
-PKG_NAME:=broadcom-wl
-PKG_VERSION:=5.10.56.27.3
-PKG_RELEASE:=10
-
-PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION)_$(ARCH).tar.bz2
-PKG_SOURCE_URL:=@OPENWRT
-
-ifeq ($(ARCH),mipsel)
-PKG_HASH:=26a8c370f48fc129d0731cfd751c36cae1419b0bc8ca35781126744e60eae009
-endif
-ifeq ($(ARCH),mips)
-PKG_HASH:=ca6a86ca3e3e9c85b6dbb665b35bcbf338c37829c1b2f1994487d55664886045
-endif
-
-PKG_EXTMOD_SUBDIRS:=driver driver-mini glue
-
-PKG_BUILD_FLAGS:=no-mips16
-PKG_FLAGS:=nonshared
-
-include $(INCLUDE_DIR)/package.mk
-
-define Package/broadcom-wl/Default
-  SECTION:=kernel
-  CATEGORY:=Kernel modules
-  DEPENDS:=@(PACKAGE_kmod-brcm-wl||PACKAGE_kmod-brcm-wl-mini)
-  SUBMENU:=Proprietary BCM43xx WiFi driver
-  SUBMENUDEP:=(TARGET_bcm47xx||TARGET_bcm63xx)
-endef
-
-define KernelPackage/brcm-wl/Default
-  $(call Package/broadcom-wl/Default)
-  SECTION:=kernel
-  DEPENDS:=@(TARGET_bcm47xx||TARGET_bcm63xx) +wireless-tools +@KERNEL_WIRELESS_EXT
-  TITLE:=Kernel driver for BCM43xx chipsets
-  FILES:=$(PKG_BUILD_DIR)/driver$(1)/wl.ko $(PKG_BUILD_DIR)/glue/wl_glue.ko
-  AUTOLOAD:=$(call AutoProbe,wl)
-endef
-
-define KernelPackage/brcm-wl/Default/description
- This package contains the proprietary wireless driver for the Broadcom 
- BCM43xx chipset.
-endef
-
-define KernelPackage/brcm-wl
-$(call KernelPackage/brcm-wl/Default,)
-  TITLE+= (normal version)
-endef
-
-define KernelPackage/brcm-wl/description
-$(call KernelPackage/brcm-wl/Default/description)
-endef
-
-define KernelPackage/brcm-wl-mini
-$(call KernelPackage/brcm-wl/Default,-mini)
-  TITLE+= (Legacy version)
-endef
-
-define KernelPackage/brcm-wl-mini/description
-$(call KernelPackage/brcm-wl/Default/description)
-endef
-
-define Package/wlc
-$(call Package/broadcom-wl/Default)
-  TITLE:=wl driver setup utility
-endef
-
-define Package/wlc/description
- This package contains an utility for initializing the proprietary Broadcom 
- wl driver.
-endef
-
-define Package/wl
-$(call Package/broadcom-wl/Default)
-  TITLE:=Proprietary Broadcom wl driver config utility
-endef
-
-define Package/wl/description
- This package contains the proprietary utility (wl) for configuring the 
- proprietary Broadcom wl driver.
-endef
-
-define Package/nas
-$(call Package/broadcom-wl/Default)
-  TITLE:=Proprietary Broadcom WPA/WPA2 authenticator
-endef
-
-define Package/nas/description
- This package contains the proprietary WPA/WPA2 authenticator (nas) for the 
- proprietary Broadcom wl driver.
-endef
-
-MAKE_KMOD := $(KERNEL_MAKE) \
-		PATH="$(TARGET_PATH)" \
-		M="$(PKG_BUILD_DIR)/kmod" \
-
-define Build/Prepare
-	$(call Build/Prepare/Default)
-
-	# New kernel version changed the sysmbol exported from printk to _printk
-	# The object file provided by broadcom require modification to correctly
-	# modprobe and generate a .ko
-	$(TARGET_CROSS)objcopy $(PKG_BUILD_DIR)/driver/wl_apsta/wl_prebuilt.o \
-	  --redefine-sym printk=_printk
-	$(TARGET_CROSS)objcopy $(PKG_BUILD_DIR)/driver/wl_apsta_mini/wl_prebuilt.o \
-	  --redefine-sym printk=_printk
-
-	$(CP) $(PKG_BUILD_DIR)/driver $(PKG_BUILD_DIR)/driver-mini
-	$(CP) ./src/glue $(PKG_BUILD_DIR)/glue
-endef
-
-define Build/Compile
-	# Compile glue driver
-	$(MAKE_KMOD) -C "$(LINUX_DIR)" \
-		M="$(PKG_BUILD_DIR)/glue" \
-		modules
-
-	# Compile the kernel part
-	$(MAKE_KMOD) \
-		M="$(PKG_BUILD_DIR)/driver" \
-		MODFLAGS="-DMODULE -mlong-calls" \
-		KBUILD_EXTRA_SYMBOLS="$(PKG_BUILD_DIR)/glue/Module.symvers" \
-		modules
-
-	$(MAKE_KMOD) \
-		M="$(PKG_BUILD_DIR)/driver-mini" \
-		MODFLAGS="-DMODULE -mlong-calls" \
-		BUILD_TYPE="wl_apsta_mini" \
-		KBUILD_EXTRA_SYMBOLS="$(PKG_BUILD_DIR)/glue/Module.symvers" \
-		modules
-
-	# Compile libshared
-	$(MAKE) -C $(PKG_BUILD_DIR)/shared \
-		$(TARGET_CONFIGURE_OPTS) \
-		CFLAGS="$(TARGET_CFLAGS) -I. -I$(PKG_BUILD_DIR)/driver/include" \
-		all
-
-	$(TARGET_CC) -o $(PKG_BUILD_DIR)/wlc \
-		-I$(PKG_BUILD_DIR)/shared -I$(PKG_BUILD_DIR)/driver/include \
-		./src/wlc.c $(PKG_BUILD_DIR)/shared/libshared.a
-
-	$(TARGET_CC) -o $(PKG_BUILD_DIR)/nas \
-		$(PKG_BUILD_DIR)/nas_exe.o \
-		$(PKG_BUILD_DIR)/shared/libshared.a
-
-	$(TARGET_CC) -o $(PKG_BUILD_DIR)/wl \
-		$(PKG_BUILD_DIR)/wl_exe.o \
-		$(PKG_BUILD_DIR)/shared/libshared.a
-endef
-
-define Build/InstallDev
-	$(INSTALL_DIR) $(1)/usr/lib
-	$(CP) $(PKG_BUILD_DIR)/shared/libshared.a $(1)/usr/lib/
-endef
-
-define Package/wlc/install
-	$(CP) ./files/* $(1)/
-	$(INSTALL_DIR) $(1)/sbin
-	$(INSTALL_BIN) $(PKG_BUILD_DIR)/wlc $(1)/sbin/
-endef
-
-define Package/wlc/postinst
-#!/bin/sh
-[ -n "$${IPKG_INSTROOT}" ] || /etc/init.d/wlunbind enable || true
-endef
-
-define Package/wl/install
-	$(INSTALL_DIR) $(1)/usr/sbin
-	$(INSTALL_BIN) $(PKG_BUILD_DIR)/wl $(1)/usr/sbin/
-endef
-
-define Package/nas/install
-	$(INSTALL_DIR) $(1)/usr/sbin
-	$(INSTALL_BIN) $(PKG_BUILD_DIR)/nas $(1)/usr/sbin/
-	$(LN) nas $(1)/usr/sbin/nas4not
-	$(LN) nas $(1)/usr/sbin/nas4wds
-endef
-
-$(eval $(call KernelPackage,brcm-wl))
-$(eval $(call KernelPackage,brcm-wl-mini))
-$(eval $(call BuildPackage,wlc))
-$(eval $(call BuildPackage,wl))
-$(eval $(call BuildPackage,nas))
diff --git a/package/kernel/broadcom-wl/files/etc/hotplug.d/net/00-broadcom-wifi-detect b/package/kernel/broadcom-wl/files/etc/hotplug.d/net/00-broadcom-wifi-detect
deleted file mode 100644
index a63d6bce60fb60..00000000000000
--- a/package/kernel/broadcom-wl/files/etc/hotplug.d/net/00-broadcom-wifi-detect
+++ /dev/null
@@ -1,5 +0,0 @@
-#!/bin/sh
-
-[ "${ACTION}" = "add" ] && [ "${INTERFACE%%[0-9]}" = "wl" ] && {
-	/sbin/wifi config
-}
diff --git a/package/kernel/broadcom-wl/files/etc/hotplug.d/net/20-broadcom_wds b/package/kernel/broadcom-wl/files/etc/hotplug.d/net/20-broadcom_wds
deleted file mode 100644
index 35c4218e03a966..00000000000000
--- a/package/kernel/broadcom-wl/files/etc/hotplug.d/net/20-broadcom_wds
+++ /dev/null
@@ -1,61 +0,0 @@
-include /lib/wifi
-
-setup_broadcom_wds() {
-	local iface="$1"
-	local remote="$(wlc ifname "$iface" wdsmac)"
-
-	[ -z "$remote" ] && return
-	
-	config_cb() {
-		[ -z "$CONFIG_SECTION" ] && return
-	
-		config_get type "$CONFIG_SECTION" TYPE
-		[ "$type" = "wifi-iface" ] || return
-		
-		config_get network "$CONFIG_SECTION" network
-		[ -z "$network" ] && return
-		
-		config_get addr "$CONFIG_SECTION" bssid
-		addr=$(echo "$addr" | tr 'A-F' 'a-f')
-		[ "$addr" = "$remote" ] && {
-			local cfg="$CONFIG_SECTION"
-			
-			include /lib/network
-			scan_interfaces
-
-			for network in $network; do
-				setup_interface "$iface" "$network"
-			done
-			
-			config_get encryption "$cfg" encryption
-			config_get key "$cfg" key
-			config_get ssid "$cfg" ssid
-		
-			[ "$encryption" != "none" ] && {
-				sleep 5
-				case "$encryption" in
-					psk|PSK)
-						nas4not "$network" "$iface" up auto tkip psk "$key" "$ssid"
-						;;
-					psk2|PSK2)
-						nas4not "$network" "$iface" up auto aes psk "$key" "$ssid"
-						;;
-					psk+psk2|psk2+psk|PSK+PSK2|PSK2+PSK)
-						nas4not "$network" "$iface" up auto aes+tkip psk "$key" "$ssid"
-						;;
-					*)
-						nas4not lan "$iface" up auto aes "$encryption" "$key" "$ssid"
-						;;
-					esac
-			}
-		}
-	}
-
-	config_load wireless
-}
-
-case "$ACTION" in
-	add|register)
-		[ "${INTERFACE%%[0-1]-*}" = wds ] && setup_broadcom_wds "$INTERFACE"
-	;;
-esac
diff --git a/package/kernel/broadcom-wl/files/etc/init.d/wlunbind b/package/kernel/broadcom-wl/files/etc/init.d/wlunbind
deleted file mode 100755
index 0a29db565fb91e..00000000000000
--- a/package/kernel/broadcom-wl/files/etc/init.d/wlunbind
+++ /dev/null
@@ -1,29 +0,0 @@
-#!/bin/sh /etc/rc.common
-# Copyright (C) 2010-2011 OpenWrt.org
-
-START=09
-
-unbind_driver() {
-	local driver="$1"
-	local sysfs="/sys/bus/pci/drivers/$driver"
-	if [ -d "$sysfs" ]; then
-		local lnk
-		for lnk in $sysfs/*; do
-			[ -h "$lnk" ] || continue
-			case "${lnk##*/}" in
-				*:*:*.*)
-					logger "Unbinding WL PCI device ${lnk##*/} from $driver"
-					echo -n "${lnk##*/}" > "$sysfs/unbind"
-				;;
-			esac
-		done
-	fi
-}
-
-boot() {
-	unbind_driver b43-pci-bridge
-	unbind_driver bcma-pci-bridge
-}
-
-start() { :; }
-stop() { :; }
diff --git a/package/kernel/broadcom-wl/files/lib/wifi/broadcom.sh b/package/kernel/broadcom-wl/files/lib/wifi/broadcom.sh
deleted file mode 100644
index 352c365f275217..00000000000000
--- a/package/kernel/broadcom-wl/files/lib/wifi/broadcom.sh
+++ /dev/null
@@ -1,480 +0,0 @@
-append DRIVERS "broadcom"
-
-scan_broadcom() {
-	local device="$1"
-	local vif vifs wds
-	local adhoc sta apmode mon disabled
-	local adhoc_if sta_if ap_if mon_if
-
-	config_get vifs "$device" vifs
-	for vif in $vifs; do
-		config_get_bool disabled "$vif" disabled 0
-		[ $disabled -eq 0 ] || continue
-
-		local mode
-		config_get mode "$vif" mode
-		case "$mode" in
-			adhoc)
-				adhoc=1
-				adhoc_if="$vif"
-			;;
-			sta)
-				sta=1
-				sta_if="$vif"
-			;;
-			ap)
-				apmode=1
-				ap_if="${ap_if:+$ap_if }$vif"
-			;;
-			wds)
-				local addr
-				config_get addr "$vif" bssid
-				[ -z "$addr" ] || {
-					addr=$(echo "$addr" | tr 'A-F' 'a-f')
-					append wds "$addr"
-				}
-			;;
-			monitor)
-				mon=1
-				mon_if="$vif"
-			;;
-			*) echo "$device($vif): Invalid mode";;
-		esac
-	done
-	config_set "$device" wds "$wds"
-
-	local _c=
-	for vif in ${adhoc_if:-$sta_if $ap_if $mon_if}; do
-		config_set "$vif" ifname "${device}${_c:+-$_c}"
-		_c=$((${_c:-0} + 1))
-	done
-	config_set "$device" vifs "${adhoc_if:-$sta_if $ap_if $mon_if}"
-
-	ap=1
-	infra=1
-	if [ "$_c" -gt 1 ]; then
-		mssid=1
-	else
-		mssid=
-	fi
-	apsta=0
-	radio=1
-	monitor=0
-	case "$adhoc:$sta:$apmode:$mon" in
-		1*)
-			ap=0
-			mssid=
-			infra=0
-		;;
-		:1:1:)
-			apsta=1
-			wet=1
-		;;
-		:1::)
-			wet=1
-			ap=0
-			mssid=
-		;;
-		:::1)
-			wet=1
-			ap=0
-			mssid=
-			monitor=1
-		;;
-		::)
-			radio=0
-		;;
-	esac
-}
-
-disable_broadcom() {
-	local device="$1"
-	set_wifi_down "$device"
-	(
-		include /lib/network
-
-		local pid_file=/var/run/nas.$device.pid
-		[ -e $pid_file ] && start-stop-daemon -K -q -s SIGKILL -p $pid_file && rm $pid_file
-
-		# make sure the interfaces are down and removed from all bridges
-		local dev ifname
-		for dev in /sys/class/net/wds${device##wl}-* /sys/class/net/${device}-* /sys/class/net/${device}; do
-			if [ -e "$dev" ]; then
-				ifname=${dev##/sys/class/net/}
-				ip link set dev "$ifname" down
-				unbridge "$ifname"
-			fi
-		done
-
-		# make sure all of the devices are disabled in the driver
-		local ifdown=
-		local bssmax=$(wlc ifname "$device" bssmax)
-		local vif=$((${bssmax:-4} - 1))
-		append ifdown "down" "$N"
-		append ifdown "wds none" "$N"
-		while [ $vif -ge 0 ]; do
-			append ifdown "vif $vif" "$N"
-			append ifdown "enabled 0" "$N"
-			vif=$(($vif - 1))
-		done
-
-		wlc ifname "$device" stdin <<EOF
-$ifdown
-leddc 0xffff
-EOF
-	)
-	true
-}
-
-enable_broadcom() {
-	local device="$1"
-	local channel country maxassoc wds vifs distance slottime rxantenna txantenna
-	local frameburst macfilter maclist macaddr txpower frag rts hwmode htmode
-	config_get channel "$device" channel
-	config_get country "$device" country
-	config_get maxassoc "$device" maxassoc
-	config_get wds "$device" wds
-	config_get vifs "$device" vifs
-	config_get distance "$device" distance
-	config_get slottime "$device" slottime
-	config_get rxantenna "$device" rxantenna
-	config_get txantenna "$device" txantenna
-	config_get_bool frameburst "$device" frameburst
-	config_get macfilter "$device" macfilter
-	config_get maclist "$device" maclist
-	config_get macaddr "$device" macaddr $(wlc ifname "$device" default_bssid)
-	config_get txpower "$device" txpower
-	config_get frag "$device" frag
-	config_get rts "$device" rts
-	config_get hwmode "$device" hwmode
-	config_get htmode "$device" htmode
-	local doth=0
-	local wmm=1
-
-	[ -z "$slottime" ] && {
-		[ -n "$distance" ] && {
-			# slottime = 9 + (distance / 150) + (distance % 150 ? 1 : 0)
-			slottime="$((9 + ($distance / 150) + 1 - (150 - ($distance % 150)) / 150 ))"
-		}
-	} || {
-		slottime="${slottime:--1}"
-	}
-
-	case "$macfilter" in
-		allow|2)
-			macfilter=2;
-		;;
-		deny|1)
-			macfilter=1;
-		;;
-		disable|none|0)
-			macfilter=0;
-		;;
-	esac
-
-	local gmode=2 nmode=0 nreqd=
-	case "$hwmode" in
-		*a)	gmode=;;
-		*b)	gmode=0;;
-		*bg)	gmode=1;;
-		*g)	gmode=2;;
-		*gst)	gmode=4;;
-		*lrs)	gmode=5;;
-		*)	nmode=1; nreqd=0;;
-	esac
-
-	case "$hwmode" in
-		n|11n)	nmode=1; nreqd=1;;
-		*n*)	nmode=1; nreqd=0;;
-	esac
-
-        # Use 'nmode' for N-Phy only
-	[ "$(wlc ifname "$device" phytype)" = 4 ] || nmode=
-
-	local band chanspec
-	[ ${channel:-0} -ge 1 -a ${channel:-0} -le 14 ] && band=2
-	[ ${channel:-0} -ge 36 ] && {
-		band=1
-		gmode=
-	}
-
-	# Use 'chanspec' instead of 'channel' for 'N' modes (See bcmwifi.h)
-	[ -n "$nmode" -a -n "$band" -a -n "$channel" ] && {
-		case "$htmode" in
-			HT40)
-				if [ -n "$gmode" ]; then
-					[ $channel -lt 7 ] && htmode="HT40+" || htmode="HT40-"
-				else
-					[ $(( ($channel / 4) % 2 )) -eq 1 ] && htmode="HT40+" || htmode="HT40-"
-				fi
-			;;
-		esac
-		case "$htmode" in
-			HT40-)	chanspec=$(printf 0x%x%x%02x $band 0xe $(($channel - 2))); nmode=1; channel=;;
-			HT40+)	chanspec=$(printf 0x%x%x%02x $band 0xd $(($channel + 2))); nmode=1; channel=;;
-			HT20)	chanspec=$(printf 0x%x%x%02x $band 0xb $channel); nmode=1; channel=;;
-			*) ;;
-		esac
-	}
-
-	local leddc=$(wlc ifname "$device" leddc)
-	[ $((leddc)) -eq $((0xffff)) ] && {
-		leddc=0x005a000a;
-	}
-
-	local _c=0
-	local nas="$(command -v nas)"
-	local if_pre_up if_up nas_cmd
-	local vif vif_pre_up vif_post_up vif_do_up vif_txpower
-	local bssmax=$(wlc ifname "$device" bssmax)
-	bssmax=${bssmax:-4}
-
-	for vif in $vifs; do
-		[ $_c -ge $bssmax ] && break
-
-		config_get vif_txpower "$vif" txpower
-
-		local mode
-		config_get mode "$vif" mode
-		append vif_pre_up "vif $_c" "$N"
-		append vif_post_up "vif $_c" "$N"
-		append vif_do_up "vif $_c" "$N"
-
-		config_get_bool wmm "$vif" wmm "$wmm"
-		config_get_bool doth "$vif" doth "$doth"
-
-		[ "$mode" = "sta" ] || {
-			local hidden isolate
-			config_get_bool hidden "$vif" hidden 0
-			append vif_pre_up "closed $hidden" "$N"
-			config_get_bool isolate "$vif" isolate 0
-			append vif_pre_up "ap_isolate $isolate" "$N"
-		}
-
-		local wsec_r=0
-		local eap_r=0
-		local wsec=0
-		local auth=0
-		local nasopts=
-		local enc key rekey
-
-		config_get enc "$vif" encryption
-		case "$enc" in
-			*wep*)
-				local def defkey k knr
-				wsec_r=1
-				wsec=1
-				defkey=1
-				config_get key "$vif" key
-				case "$enc" in
-					*shared*) append vif_do_up "wepauth 1" "$N";;
-					*) append vif_do_up "wepauth 0" "$N";;
-				esac
-				case "$key" in
-					[1234])
-						defkey="$key"
-						for knr in 1 2 3 4; do
-							config_get k "$vif" key$knr
-							[ -n "$k" ] || continue
-							[ "$defkey" = "$knr" ] && def="=" || def=""
-							append vif_do_up "wepkey $def$knr,$k" "$N"
-						done
-					;;
-					"");;
-					*) append vif_do_up "wepkey =1,$key" "$N";;
-				esac
-			;;
-			*psk*)
-				wsec_r=1
-				config_get key "$vif" key
-
-				# psk version + default cipher
-				case "$enc" in
-					*mixed*|*psk+psk2*) auth=132; wsec=6;;
-					*psk2*) auth=128; wsec=4;;
-					*) auth=4; wsec=2;;
-				esac
-
-				# cipher override
-				case "$enc" in
-					*tkip+aes*|*tkip+ccmp*|*aes+tkip*|*ccmp+tkip*) wsec=6;;
-					*aes*|*ccmp*) wsec=4;;
-					*tkip*) wsec=2;;
-				esac
-
-				# group rekey interval
-				config_get rekey "$vif" wpa_group_rekey
-
-				eval "${vif}_key=\"\$key\""
-				nasopts="-k \"\$${vif}_key\"${rekey:+ -g $rekey}"
-			;;
-			*wpa*)
-				local auth_port auth_secret auth_server
-				wsec_r=1
-				eap_r=1
-				config_get auth_server "$vif" auth_server
-				[ -z "$auth_server" ] && config_get auth_server "$vif" server
-				config_get auth_port "$vif" auth_port
-				[ -z "$auth_port" ] && config_get auth_port "$vif" port
-				config_get auth_secret "$vif" auth_secret
-				[ -z "$auth_secret" ] && config_get auth_secret "$vif" key
-
-				# wpa version + default cipher
-				case "$enc" in
-					*mixed*|*wpa+wpa2*) auth=66; wsec=6;;
-					*wpa2*) auth=64; wsec=4;;
-					*) auth=2; wsec=2;;
-				esac
-
-				# cipher override
-				case "$enc" in
-					*tkip+aes*|*tkip+ccmp*|*aes+tkip*|*ccmp+tkip*) wsec=6;;
-					*aes*|*ccmp*) wsec=4;;
-					*tkip*) wsec=2;;
-				esac
-
-				# group rekey interval
-				config_get rekey "$vif" wpa_group_rekey
-
-				eval "${vif}_key=\"\$auth_secret\""
-				nasopts="-r \"\$${vif}_key\" -h $auth_server -p ${auth_port:-1812}${rekey:+ -g $rekey}"
-			;;
-		esac
-		append vif_do_up "wsec $wsec" "$N"
-		append vif_do_up "wpa_auth $auth" "$N"
-		append vif_do_up "wsec_restrict $wsec_r" "$N"
-		append vif_do_up "eap_restrict $eap_r" "$N"
-
-		local ssid
-		config_get ssid "$vif" ssid
-		append vif_post_up "vlan_mode 0" "$N"
-		append vif_pre_up "ssid $ssid" "$N"
-
-		[ "$mode" = "monitor" ] && {
-			append vif_post_up "monitor $monitor" "$N"
-		}
-
-		[ "$mode" = "adhoc" ] && {
-			local bssid
-			config_get bssid "$vif" bssid
-			[ -n "$bssid" ] && {
-				append vif_pre_up "bssid $bssid" "$N"
-				append vif_pre_up "ibss_merge 0" "$N"
-			} || {
-				append vif_pre_up "ibss_merge 1" "$N"
-			}
-		}
-
-		append vif_post_up "enabled 1" "$N"
-
-		local ifname
-		config_get ifname "$vif" ifname
-		local if_cmd="if_pre_up"
-		[ "$ifname" != "${ifname##${device}-}" ] && if_cmd="if_up"
-		append $if_cmd "macaddr=\$(wlc ifname '$ifname' cur_etheraddr)" ";$N"
-		append $if_cmd "ip link set dev '$ifname' address \$macaddr" ";$N"
-		append if_up "ip link set dev '$ifname' up" ";$N"
-
-		local net_cfg="$(find_net_config "$vif")"
-		[ -z "$net_cfg" ] || {
-			ubus -t 30 wait_for network.interface."$net_cfg"
-			append if_up "set_wifi_up '$vif' '$ifname'" ";$N"
-			append if_up "start_net '$ifname' '$net_cfg'" ";$N"
-		}
-		[ -z "$nas" -o -z "$nasopts" ] || {
-			eval "${vif}_ssid=\"\$ssid\""
-			local nas_mode="-A"
-			[ "$mode" = "sta" ] && nas_mode="-S"
-			[ -z "$nas_cmd" ] && {
-				local pid_file=/var/run/nas.$device.pid
-				nas_cmd="start-stop-daemon -S -b -p $pid_file -x $nas -- -P $pid_file -H 34954"
-			}
-			append nas_cmd "-i $ifname $nas_mode -m $auth -w $wsec -s \"\$${vif}_ssid\" -g 3600 -F $nasopts"
-		}
-		_c=$(($_c + 1))
-	done
-	wlc ifname "$device" stdin <<EOF
-${macaddr:+bssid $macaddr}
-${macaddr:+cur_etheraddr $macaddr}
-band ${band:-0}
-${nmode:+nmode $nmode}
-${nmode:+${nreqd:+nreqd $nreqd}}
-${gmode:+gmode $gmode}
-leddc $leddc
-apsta $apsta
-ap $ap
-${mssid:+mssid $mssid}
-infra $infra
-${wet:+wet 1}
-802.11d 0
-802.11h ${doth:-0}
-wme ${wmm:-1}
-rxant ${rxantenna:-3}
-txant ${txantenna:-3}
-fragthresh ${frag:-2346}
-rtsthresh ${rts:-2347}
-monitor ${monitor:-0}
-
-radio ${radio:-1}
-macfilter ${macfilter:-0}
-maclist ${maclist:-none}
-${wds:+wds $wds}
-country ${country:-US}
-${channel:+channel $channel}
-${chanspec:+chanspec $chanspec}
-maxassoc ${maxassoc:-128}
-slottime ${slottime:--1}
-${frameburst:+frameburst $frameburst}
-
-$vif_pre_up
-EOF
-	eval "$if_pre_up"
-	wlc ifname "$device" stdin <<EOF
-up
-$vif_post_up
-EOF
-	eval "$if_up"
-	wlc ifname "$device" stdin <<EOF
-$vif_do_up
-EOF
-
-	# use vif_txpower (from last wifi-iface) instead of txpower (from
-	# wifi-device) if the latter does not exist
-	txpower=${txpower:-$vif_txpower}
-	[ -z "$txpower" ] || iwconfig $device txpower ${txpower}dBm
-
-	# fd 1000 is an inherited lock file descriptor for preventing concurrent
-	# init script executions. Close it here to prevent the nas daemon from
-	# inheriting it further to avoid holding the lock indefinitely.
-	eval "$nas_cmd 1000>&-"
-}
-
-
-detect_broadcom() {
-	local i=-1
-
-	while grep -qs "^ *wl$((++i)):" /proc/net/dev; do
-		local channel type
-
-		config_get type wl${i} type
-		[ "$type" = broadcom ] && continue
-		channel=`wlc ifname wl${i} channel`
-
-		uci -q batch <<-EOF
-			set wireless.wl${i}=wifi-device
-			set wireless.wl${i}.type=broadcom
-			set wireless.wl${i}.channel=${channel:-11}
-			set wireless.wl${i}.txantenna=3
-			set wireless.wl${i}.rxantenna=3
-			set wireless.wl${i}.disabled=1
-
-			set wireless.default_wl${i}=wifi-iface
-			set wireless.default_wl${i}.device=wl${i}
-			set wireless.default_wl${i}.network=lan
-			set wireless.default_wl${i}.mode=ap
-			set wireless.default_wl${i}.ssid=OpenWrt${i#0}
-			set wireless.default_wl${i}.encryption=none
-EOF
-		uci -q commit wireless
-	done
-}
diff --git a/package/kernel/broadcom-wl/patches/003-compat-2.6.35.patch b/package/kernel/broadcom-wl/patches/003-compat-2.6.35.patch
deleted file mode 100644
index 89b665371d1392..00000000000000
--- a/package/kernel/broadcom-wl/patches/003-compat-2.6.35.patch
+++ /dev/null
@@ -1,39 +0,0 @@
---- a/driver/wl_linux.c
-+++ b/driver/wl_linux.c
-@@ -2082,7 +2082,11 @@ static void
- _wl_set_multicast_list(struct net_device *dev)
- {
- 	wl_info_t *wl;
-+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
- 	struct dev_mc_list *mclist;
-+#else
-+	struct netdev_hw_addr *ha;
-+#endif
- 	int i;
- 
- 	if (!dev)
-@@ -2098,14 +2102,24 @@ _wl_set_multicast_list(struct net_device
- 		wl->pub->allmulti = (dev->flags & IFF_ALLMULTI)? TRUE: FALSE;
- 
- 		/* copy the list of multicasts into our private table */
-+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
- 		for (i = 0, mclist = dev->mc_list; mclist && (i < dev->mc_count);
- 			i++, mclist = mclist->next) {
-+#else
-+		i = 0;
-+		netdev_for_each_mc_addr(ha, dev) {
-+#endif
- 			if (i >= MAXMULTILIST) {
- 				wl->pub->allmulti = TRUE;
- 				i = 0;
- 				break;
- 			}
-+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
- 			wl->pub->multicast[i] = *((struct ether_addr*) mclist->dmi_addr);
-+#else
-+			wl->pub->multicast[i] = *((struct ether_addr*) ha->addr);
-+			i++;
-+#endif
- 		}
- 		wl->pub->nmulticast = i;
- 		wlc_set(wl->wlc, WLC_SET_PROMISC, (dev->flags & IFF_PROMISC));
diff --git a/package/kernel/broadcom-wl/patches/004-remove-pcmcia.patch b/package/kernel/broadcom-wl/patches/004-remove-pcmcia.patch
deleted file mode 100644
index 36dda47e10a572..00000000000000
--- a/package/kernel/broadcom-wl/patches/004-remove-pcmcia.patch
+++ /dev/null
@@ -1,22 +0,0 @@
---- a/driver/include/linuxver.h
-+++ b/driver/include/linuxver.h
-@@ -111,7 +111,7 @@ typedef irqreturn_t(*FN_ISR) (int irq, v
- #endif /* not SANDGATE2G */
- #endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 5, 67) */
- 
--#if defined(CONFIG_PCMCIA) || defined(CONFIG_PCMCIA_MODULE)
-+#if 0
- 
- #include <pcmcia/cs_types.h>
- #include <pcmcia/cs.h>
---- a/driver/linux_osl.c
-+++ b/driver/linux_osl.c
-@@ -62,7 +62,7 @@ struct osl_info {
- };
- 
- /* PCMCIA attribute space access macros */
--#if defined(CONFIG_PCMCIA) || defined(CONFIG_PCMCIA_MODULE)
-+#if 0
- struct pcmcia_dev {
- 	dev_link_t link;	/* PCMCIA device pointer */
- 	dev_node_t node;	/* PCMCIA node structure */
diff --git a/package/kernel/broadcom-wl/patches/005-fix-mem-leak-on-unload.patch b/package/kernel/broadcom-wl/patches/005-fix-mem-leak-on-unload.patch
deleted file mode 100644
index 41c246ff804e9a..00000000000000
--- a/package/kernel/broadcom-wl/patches/005-fix-mem-leak-on-unload.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From: George Kashperko <george@znau.edu.ua>
-
-Release nvram variables buffer.
-Prevent block reserved by alloc_etherdev from being freed.
-Signed-off-by: George Kashperko <george@znau.edu.ua>
----
----
---- a/driver/siutils.c
-+++ b/driver/siutils.c
-@@ -647,7 +647,10 @@ si_detach(si_t *sih)
- #if !defined(BCMBUSTYPE) || (BCMBUSTYPE == SI_BUS)
- 	if (sii != &ksii)
- #endif	/* !BCMBUSTYPE || (BCMBUSTYPE == SI_BUS) */
--		MFREE(sii->osh, sii, sizeof(si_info_t));
-+		do {
-+			MFREE(sii->osh, sii, sizeof(si_info_t));
-+			nvram_exit((void *)&(sii->pub));
-+		} while (0);
- }
- 
- void *
---- a/driver/wl_linux.c
-+++ b/driver/wl_linux.c
-@@ -1477,7 +1477,6 @@ wl_free_if(wl_info_t *wl, wl_if_t *wlif)
- 		free_netdev(wlif->dev);
- #endif
- 	}
--	MFREE(wl->osh, wlif, sizeof(wl_if_t));
- }
- 
- #ifdef AP
diff --git a/package/kernel/broadcom-wl/patches/006-generic-dma-api.patch b/package/kernel/broadcom-wl/patches/006-generic-dma-api.patch
deleted file mode 100644
index d6dd5f0aaeadf1..00000000000000
--- a/package/kernel/broadcom-wl/patches/006-generic-dma-api.patch
+++ /dev/null
@@ -1,88 +0,0 @@
-From: George Kashperko <george@znau.edu.ua>
-
-broadcom-wl driver bound to ssb device with ssb driver probe
-have osh handle struct pdev pointer value initialized with
-ssb_device pointer. Later on pdev is used with legacy pci
-dma api as pci_dev thus causing oops sometimes.
-
-The patch replaces legacy pci dma api and pass relevant
-device struct pointer to avoid crashes.
-Signed-off-by: George Kashperko <george@znau.edu.ua>
----
- driver/linux_osl.c |   28 +++++++++++++++++++++++-----
- 1 file changed, 23 insertions(+), 5 deletions(-)
---- a/driver/linux_osl.c
-+++ b/driver/linux_osl.c
-@@ -25,6 +25,9 @@
- #include <asm/paccess.h>
- #endif /* mips */
- #include <pcicfg.h>
-+#ifdef CONFIG_SSB
-+#include <linux/ssb/ssb.h>
-+#endif
- 
- #define PCI_CFG_RETRY 		10
- 
-@@ -364,12 +367,27 @@ osl_dma_consistent_align(void)
- 	return (PAGE_SIZE);
- }
- 
-+static struct device *
-+osl_get_dmadev(osl_t *osh)
-+{
-+#ifdef CONFIG_SSB
-+	if (osh->bustype == SI_BUS) {
-+		/* This can be SiliconBackplane emulated as pci with Broadcom or
-+		 * ssb device. Less harmful is to check for pci_bus_type and if
-+		 * no match then assume we got ssb */
-+		if (((struct pci_dev *)osh->pdev)->dev.bus != &pci_bus_type)
-+			return ((struct ssb_device *)osh->pdev)->dma_dev;
-+	}
-+#endif
-+	return &((struct pci_dev *)osh->pdev)->dev;
-+}
-+
- void*
- osl_dma_alloc_consistent(osl_t *osh, uint size, ulong *pap)
- {
- 	ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
- 
--	return (pci_alloc_consistent(osh->pdev, size, (dma_addr_t*)pap));
-+	return (dma_alloc_coherent(osl_get_dmadev(osh), size, (dma_addr_t*)pap, GFP_ATOMIC));
- }
- 
- void
-@@ -377,7 +395,7 @@ osl_dma_free_consistent(osl_t *osh, void
- {
- 	ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
- 
--	pci_free_consistent(osh->pdev, size, va, (dma_addr_t)pa);
-+	dma_free_coherent(osl_get_dmadev(osh), size, va, (dma_addr_t)pa);
- }
- 
- uint BCMFASTPATH
-@@ -386,13 +404,13 @@ osl_dma_map(osl_t *osh, void *va, uint s
- 	ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
- 
- 	if (direction == DMA_TX)
--		return (pci_map_single(osh->pdev, va, size, PCI_DMA_TODEVICE));
-+		return (dma_map_single(osl_get_dmadev(osh), va, size, PCI_DMA_TODEVICE));
- 	else {
- #ifdef mips
- 		dma_cache_inv((uint)va, size);
- 		return (virt_to_phys(va));
- #else /* mips */
--		return (pci_map_single(osh->pdev, va, size, PCI_DMA_FROMDEVICE));
-+		return (dma_map_single(osl_get_dmadev(osh), va, size, PCI_DMA_FROMDEVICE));
- #endif /* mips */
- 	}
- }
-@@ -404,7 +422,7 @@ osl_dma_unmap(osl_t *osh, uint pa, uint
- 
- 	ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
- 	dir = (direction == DMA_TX)? PCI_DMA_TODEVICE: PCI_DMA_FROMDEVICE;
--	pci_unmap_single(osh->pdev, (uint32)pa, size, dir);
-+	dma_unmap_single(osl_get_dmadev(osh), (uint32)pa, size, dir);
- }
- 
- 
diff --git a/package/kernel/broadcom-wl/patches/007-use-glue-driver.patch b/package/kernel/broadcom-wl/patches/007-use-glue-driver.patch
deleted file mode 100644
index a30dcc4edf372f..00000000000000
--- a/package/kernel/broadcom-wl/patches/007-use-glue-driver.patch
+++ /dev/null
@@ -1,188 +0,0 @@
---- a/driver/wl_linux.c
-+++ b/driver/wl_linux.c
-@@ -85,10 +85,9 @@ typedef void wlc_hw_info_t;
- #include <bcmjtag.h>
- #endif	/* BCMJTAG */
- 
--
--#ifdef CONFIG_SSB
--#include <linux/ssb/ssb.h>
--#endif
-+#if defined(CONFIG_SSB) || defined(CONFIG_BCMA)
-+#include <wl_glue.h>
-+#endif /* defined(CONFIG_SSB) || defined(CONFIG_BCMA) */
- 
- /* Linux wireless extension support */
- #ifdef CONFIG_WIRELESS_EXT
-@@ -997,62 +996,32 @@ static struct pci_driver wl_pci_driver =
- #endif	/* CONFIG_PCI */
- #endif  
- 
-+#ifdef BCMJTAG
-+static bcmjtag_driver_t wl_jtag_driver = {
-+		wl_jtag_probe,
-+		wl_jtag_detach,
-+		wl_jtag_poll,
-+		};
-+#endif	/* BCMJTAG */
- 
--static int wl_ssb_probe(struct ssb_device *dev, const struct ssb_device_id *id)
-+#if defined(CONFIG_SSB) || defined(CONFIG_BCMA)
-+static void * glue_attach_cb(u16 vendor, u16 device,
-+                                ulong mmio, void *dev, u32 irq)
- {
--	wl_info_t *wl;
--	void *mmio;
--
--	if (dev->bus->bustype != SSB_BUSTYPE_SSB) {
--		printk("Attaching to SSB behind PCI is not supported. Please remove the b43 ssb bridge\n");
--		return -EINVAL;
--	}
--
--	mmio = (void *) 0x18000000 + dev->core_index * 0x1000;
--	wl = wl_attach(id->vendor, id->coreid, (ulong) mmio, SI_BUS, dev, dev->irq);
--	if (!wl) {
--		printk("wl_attach failed\n");
--		return -ENODEV;
--	}
--
--	ssb_set_drvdata(dev, wl);
--
--	return 0;
-+	return wl_attach(vendor, device, mmio, SI_BUS, dev, irq);
- }
- 
--static void wl_ssb_remove(struct ssb_device *dev)
-+static void glue_remove_cb(void *wldev)
- {
--	wl_info_t *wl = (wl_info_t *) ssb_get_drvdata(dev);
-+	wl_info_t *wl = (wl_info_t *)wldev;
- 
- 	WL_LOCK(wl);
- 	WL_APSTA_UPDN(("wl%d (%s): wl_remove() -> wl_down()\n", wl->pub->unit, wl->dev->name));
- 	wl_down(wl);
- 	WL_UNLOCK(wl);
- 	wl_free(wl);
--	ssb_set_drvdata(dev, NULL);
- }
--
--static const struct ssb_device_id wl_ssb_tbl[] = {
--	SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, SSB_ANY_REV),
--	SSB_DEVTABLE_END
--};
--
--#ifdef CONFIG_SSB
--static struct ssb_driver wl_ssb_driver = {
--	.name	= KBUILD_MODNAME,
--	.id_table = wl_ssb_tbl,
--	.probe = wl_ssb_probe,
--	.remove = wl_ssb_remove,
--};
--#endif
--
--#ifdef BCMJTAG
--static bcmjtag_driver_t wl_jtag_driver = {
--		wl_jtag_probe,
--		wl_jtag_detach,
--		wl_jtag_poll,
--		};
--#endif	/* BCMJTAG */
-+#endif/* defined(CONFIG_SSB) || defined(CONFIG_BCMA) */
- 
- 
- /** 
-@@ -1067,11 +1036,13 @@ wl_module_init(void)
- {
- 	int error = -ENODEV;
- 
--#ifdef CONFIG_SSB
--	error = ssb_driver_register(&wl_ssb_driver);
-+#if defined(CONFIG_SSB) || defined(CONFIG_BCMA)
-+	wl_glue_set_attach_callback(&glue_attach_cb);
-+	wl_glue_set_remove_callback(&glue_remove_cb);
-+	error = wl_glue_register();
- 	if (error)
- 		return error;
--#endif	/* CONFIG_SSB */
-+#endif /* defined(CONFIG_SSB) || defined(CONFIG_BCMA) */
- 
- #ifdef CONFIG_PCI
- 	error = pci_register_driver(&wl_pci_driver);
-@@ -1082,7 +1053,11 @@ wl_module_init(void)
- 	return 0;
- 
- error_pci:
--	ssb_driver_unregister(&wl_ssb_driver);
-+#if defined(CONFIG_SSB) || defined(CONFIG_BCMA)
-+	wl_glue_unregister();
-+	wl_glue_set_attach_callback(NULL);
-+	wl_glue_set_remove_callback(NULL);
-+#endif /* defined(CONFIG_SSB) || defined(CONFIG_BCMA) */
- 	return error;
- }
- 
-@@ -1099,9 +1074,11 @@ wl_module_exit(void)
- #ifdef CONFIG_PCI
- 	pci_unregister_driver(&wl_pci_driver);
- #endif	/* CONFIG_PCI */
--#ifdef CONFIG_SSB
--	ssb_driver_unregister(&wl_ssb_driver);
--#endif	/* CONFIG_SSB */
-+#if defined(CONFIG_SSB) || defined(CONFIG_BCMA)
-+	wl_glue_unregister();
-+	wl_glue_set_attach_callback(NULL);
-+	wl_glue_set_remove_callback(NULL);
-+#endif /* defined(CONFIG_SSB) || defined(CONFIG_BCMA) */
- }
- 
- module_init(wl_module_init);
---- a/driver/linux_osl.c
-+++ b/driver/linux_osl.c
-@@ -25,9 +25,9 @@
- #include <asm/paccess.h>
- #endif /* mips */
- #include <pcicfg.h>
--#ifdef CONFIG_SSB
--#include <linux/ssb/ssb.h>
--#endif
-+#if defined(CONFIG_SSB) || defined(CONFIG_BCMA)
-+#include <wl_glue.h>
-+#endif /* defined(CONFIG_SSB) || defined(CONFIG_BCMA) */
- 
- #define PCI_CFG_RETRY 		10
- 
-@@ -370,15 +370,17 @@ osl_dma_consistent_align(void)
- static struct device *
- osl_get_dmadev(osl_t *osh)
- {
--#ifdef CONFIG_SSB
-+#if defined(CONFIG_SSB) || defined(CONFIG_BCMA)
- 	if (osh->bustype == SI_BUS) {
--		/* This can be SiliconBackplane emulated as pci with Broadcom or
--		 * ssb device. Less harmful is to check for pci_bus_type and if
--		 * no match then assume we got ssb */
-+		/* This can be SiliconBackplane emulated as pci with Broadcom,
-+		 * ssb or bcma device. Less harmful is to check for pci_bus_type and if
-+		 * no match then assume we got either ssb or bcma */
- 		if (((struct pci_dev *)osh->pdev)->dev.bus != &pci_bus_type)
--			return ((struct ssb_device *)osh->pdev)->dma_dev;
-+		{
-+			return wl_glue_get_dmadev(osh->pdev);
-+		}
- 	}
--#endif
-+#endif /* defined(CONFIG_SSB) || defined(CONFIG_BCMA) */
- 	return &((struct pci_dev *)osh->pdev)->dev;
- }
- 
---- a/driver/Makefile
-+++ b/driver/Makefile
-@@ -1,7 +1,7 @@
- BUILD_TYPE=wl_apsta
- include $(src)/$(BUILD_TYPE)/buildflags.mk
- 
--EXTRA_CFLAGS += -I$(src)/include -I$(src) -DBCMDRIVER $(WLFLAGS)
-+EXTRA_CFLAGS += -I$(src)/include -I$(src) -I$(realpath $(src)/../glue) -DBCMDRIVER $(WLFLAGS)
- 
- wl-objs := $(BUILD_TYPE)/wl_prebuilt.o wl_iw.o wl_linux.o linux_osl.o siutils.o aiutils.o hndpmu.o bcmutils.o sbutils.o nicpci.o hnddma.o bcmsrom.o nvram_stub.o
- 
diff --git a/package/kernel/broadcom-wl/patches/008-fix_virtual_interfaces.patch b/package/kernel/broadcom-wl/patches/008-fix_virtual_interfaces.patch
deleted file mode 100644
index 23831df5ba6a9c..00000000000000
--- a/package/kernel/broadcom-wl/patches/008-fix_virtual_interfaces.patch
+++ /dev/null
@@ -1,132 +0,0 @@
---- a/driver/wl_linux.c
-+++ b/driver/wl_linux.c
-@@ -354,6 +354,7 @@ static int wl_read_proc(char *buffer, ch
- static int wl_dump(wl_info_t *wl, struct bcmstrbuf *b);
- #endif /* BCMDBG */
- struct wl_if *wl_alloc_if(wl_info_t *wl, int iftype, uint unit, struct wlc_if* wlc_if);
-+static void wl_link_if(wl_info_t *wl, wl_if_t *wlif);
- static void wl_free_if(wl_info_t *wl, wl_if_t *wlif);
- 
- 
-@@ -566,6 +567,9 @@ wl_attach(uint16 vendor, uint16 device,
- 	wl->dev = dev;
- 	wl_if_setup(dev);
- 
-+	/* add the interface to the interface linked list */
-+	wl_link_if(wl, wlif);
-+
- 	/* map chip registers (47xx: and sprom) */
- 	dev->base_addr = regs;
- 
-@@ -1106,10 +1110,14 @@ wl_free(wl_info_t *wl)
- 			free_irq(wl->dev->irq, wl);
- 	}
- 
--	if (wl->dev) {
--		wl_free_if(wl, WL_DEV_IF(wl->dev));
--		wl->dev = NULL;
-+	/* free all interfaces */
-+	while (wl->if_list) {
-+        	if ((wl->if_list->dev != wl->dev) || wl->if_list->next == NULL)
-+			wl_free_if(wl, wl->if_list);
-+		else
-+			wl_free_if(wl, wl->if_list->next);
- 	}
-+	wl->dev = NULL;
- 
- #ifdef TOE
- 	wl_toe_detach(wl->toei);
-@@ -1355,10 +1363,12 @@ wl_txflowcontrol(wl_info_t *wl, bool sta
- 
- 	ASSERT(prio == ALLPRIO);
- 	for (wlif = wl->if_list; wlif != NULL; wlif = wlif->next) {
--		if (state == ON)
--			netif_stop_queue(wlif->dev);
--		else
--			netif_wake_queue(wlif->dev);
-+		if (wlif->dev_registed) {
-+			if (state == ON)
-+				netif_stop_queue(wlif->dev);
-+			else
-+				netif_wake_queue(wlif->dev);
-+		}
- 	}
- }
- 
-@@ -1398,7 +1408,6 @@ wl_alloc_if(wl_info_t *wl, int iftype, u
- {
- 	struct net_device *dev;
- 	wl_if_t *wlif;
--	wl_if_t *p;
- 
- 	dev = alloc_etherdev(sizeof(wl_if_t));
- 	wlif = netdev_priv(dev);
-@@ -1411,9 +1420,13 @@ wl_alloc_if(wl_info_t *wl, int iftype, u
- 	wlif->wlcif = wlcif;
- 	wlif->subunit = subunit;
- 
--	/* match current flow control state */
--	if (iftype != WL_IFTYPE_MON && wl->dev && netif_queue_stopped(wl->dev))
--		netif_stop_queue(dev);
-+	return wlif;
-+}
-+
-+static void
-+wl_link_if(wl_info_t *wl, wl_if_t *wlif)
-+{
-+	wl_if_t *p;
- 
- 	/* add the interface to the interface linked list */
- 	if (wl->if_list == NULL)
-@@ -1424,7 +1437,6 @@ wl_alloc_if(wl_info_t *wl, int iftype, u
- 			p = p->next;
- 		p->next = wlif;
- 	}
--	return wlif;
- }
- 
- static void
-@@ -1504,6 +1516,9 @@ _wl_add_if(wl_task_t *task)
- 	wl_info_t *wl = wlif->wl;
- 	struct net_device *dev = wlif->dev;
- 
-+	/* add the interface to the interface linked list */
-+	wl_link_if(wl, wlif);
-+
- 	if (wlif->type == WL_IFTYPE_WDS)
- 		dev->netdev_ops = &wl_wds_ops;
- 
-@@ -1516,6 +1531,14 @@ _wl_add_if(wl_task_t *task)
- 	}
- 	wlif->dev_registed = TRUE;
- 
-+	/* match current flow control state */
-+	if (wl->dev) {
-+		if (netif_queue_stopped(wl->dev))
-+			netif_stop_queue(dev);
-+		else
-+			netif_wake_queue(dev);
-+	}
-+
- done:
- 	MFREE(wl->osh, task, sizeof(wl_task_t));
- 	atomic_dec(&wl->callbacks);
-@@ -1545,6 +1568,8 @@ wl_add_if(wl_info_t *wl, struct wlc_if*
- 		return NULL;
- 	}
- 
-+	wl_if_setup(wlif->dev);
-+
- 	sprintf(wlif->dev->name, "%s%d.%d", devname, wl->pub->unit, wlif->subunit);
- 	if (remote)
- 		bcopy(remote, &wlif->remote, ETHER_ADDR_LEN);
-@@ -2778,6 +2803,9 @@ wl_add_monitor(wl_task_t *task)
- 	dev = wlif->dev;
- 	wl->monitor = dev;
- 
-+	/* add the interface to the interface linked list */
-+	wl_link_if(wl, wlif);
-+
- 	/* override some fields */
- 	sprintf(dev->name, "prism%d", wl->pub->unit);
- 	bcopy(wl->dev->dev_addr, dev->dev_addr, ETHER_ADDR_LEN);
diff --git a/package/kernel/broadcom-wl/patches/009-fix_compile_3_2.patch b/package/kernel/broadcom-wl/patches/009-fix_compile_3_2.patch
deleted file mode 100644
index cb388a11255b0b..00000000000000
--- a/package/kernel/broadcom-wl/patches/009-fix_compile_3_2.patch
+++ /dev/null
@@ -1,27 +0,0 @@
---- a/driver/wl_linux.c
-+++ b/driver/wl_linux.c
-@@ -463,6 +463,16 @@ wl_schedule_fn(wl_info_t *wl, void (*fn)
- }
- #endif /* DSLCPE_DELAY */
- 
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0)
-+#define WL_DEFAULT_OPS \
-+	.ndo_open = wl_open, \
-+	.ndo_stop = wl_close, \
-+	.ndo_start_xmit = wl_start, \
-+	.ndo_get_stats = wl_get_stats, \
-+	.ndo_set_mac_address = wl_set_mac_address, \
-+	.ndo_set_rx_mode = wl_set_multicast_list, \
-+	.ndo_do_ioctl = wl_ioctl
-+#else
- #define WL_DEFAULT_OPS \
- 	.ndo_open = wl_open, \
- 	.ndo_stop = wl_close, \
-@@ -471,6 +481,7 @@ wl_schedule_fn(wl_info_t *wl, void (*fn)
- 	.ndo_set_mac_address = wl_set_mac_address, \
- 	.ndo_set_multicast_list = wl_set_multicast_list, \
- 	.ndo_do_ioctl = wl_ioctl
-+#endif
- 
- static const struct net_device_ops wl_ops = {
- 	WL_DEFAULT_OPS,
diff --git a/package/kernel/broadcom-wl/patches/010-remove_irqf_samble_random.patch b/package/kernel/broadcom-wl/patches/010-remove_irqf_samble_random.patch
deleted file mode 100644
index 7b60873ebb8a0d..00000000000000
--- a/package/kernel/broadcom-wl/patches/010-remove_irqf_samble_random.patch
+++ /dev/null
@@ -1,11 +0,0 @@
---- a/driver/wl_linux.c
-+++ b/driver/wl_linux.c
-@@ -695,7 +695,7 @@ wl_attach(uint16 vendor, uint16 device,
- 	if (wl->bustype != JTAG_BUS)
- #endif	/* BCMJTAG */
- 	{
--		if (request_irq(irq, wl_isr, IRQF_SHARED|IRQF_SAMPLE_RANDOM, dev->name, wl)) {
-+		if (request_irq(irq, wl_isr, IRQF_SHARED, dev->name, wl)) {
- 			WL_ERROR(("wl%d: request_irq() failed\n", unit));
- 			goto fail;
- 		}
diff --git a/package/kernel/broadcom-wl/patches/011-fix_compile_3_4.patch b/package/kernel/broadcom-wl/patches/011-fix_compile_3_4.patch
deleted file mode 100644
index 585d53c7df29ce..00000000000000
--- a/package/kernel/broadcom-wl/patches/011-fix_compile_3_4.patch
+++ /dev/null
@@ -1,12 +0,0 @@
---- a/driver/wl_linux.c
-+++ b/driver/wl_linux.c
-@@ -49,7 +49,9 @@
- #include <linux/ieee80211.h>
- #endif
- 
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,4,0)
- #include <asm/system.h>
-+#endif
- #include <asm/io.h>
- #include <asm/irq.h>
- #include <asm/pgtable.h>
diff --git a/package/kernel/broadcom-wl/patches/012-compat-3.10.patch b/package/kernel/broadcom-wl/patches/012-compat-3.10.patch
deleted file mode 100644
index e36028a634a232..00000000000000
--- a/package/kernel/broadcom-wl/patches/012-compat-3.10.patch
+++ /dev/null
@@ -1,47 +0,0 @@
---- a/driver/wl_linux.c
-+++ b/driver/wl_linux.c
-@@ -349,7 +349,7 @@ static void wl_mic_error(wl_info_t *wl,
- 	defined(WL_MONITOR)
- static int wl_schedule_task(wl_info_t *wl, void (*fn)(struct wl_task *), void *context);
- #endif
--#if defined(CONFIG_PROC_FS)
-+#if defined(CONFIG_PROC_FS) && (LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0))
- static int wl_read_proc(char *buffer, char **start, off_t offset, int length, int *eof, void *data);
- #endif /* defined(CONFIG_PROC_FS) */
- #ifdef BCMDBG
-@@ -517,7 +517,7 @@ wl_attach(uint16 vendor, uint16 device,
- 	struct net_device *dev;
- 	wl_if_t *wlif;
- 	wl_info_t *wl;
--#if defined(CONFIG_PROC_FS)
-+#if defined(CONFIG_PROC_FS) && (LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0))
- 	char tmp[128];
- #endif
- 	osl_t *osh;
-@@ -664,7 +664,7 @@ wl_attach(uint16 vendor, uint16 device,
- 			WL_ERROR(("wl%d: Error setting MPC variable to 0\n", unit));
- 		}
- 	}
--#if defined(CONFIG_PROC_FS)
-+#if defined(CONFIG_PROC_FS) && (LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0))
- 	/* create /proc/net/wl<unit> */
- 	sprintf(tmp, "net/wl%d", wl->pub->unit);
- 	create_proc_read_entry(tmp, 0, 0, wl_read_proc, (void*)wl);
-@@ -810,7 +810,7 @@ wl_dbus_disconnect_cb(void *arg)
- }
- #endif /* BCMDBUS */
- 
--#if defined(CONFIG_PROC_FS)
-+#if defined(CONFIG_PROC_FS) && (LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0))
- static int
- wl_read_proc(char *buffer, char **start, off_t offset, int length, int *eof, void *data)
- {
-@@ -1149,7 +1149,7 @@ wl_free(wl_info_t *wl)
- 
- 	/* free common resources */
- 	if (wl->wlc) {
--#if defined(CONFIG_PROC_FS)
-+#if defined(CONFIG_PROC_FS) && (LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0))
- 		char tmp[128];
- 		/* remove /proc/net/wl<unit> */
- 		sprintf(tmp, "net/wl%d", wl->pub->unit);
diff --git a/package/kernel/broadcom-wl/patches/013-interface-name.patch b/package/kernel/broadcom-wl/patches/013-interface-name.patch
deleted file mode 100644
index dbe1bdb89a67c8..00000000000000
--- a/package/kernel/broadcom-wl/patches/013-interface-name.patch
+++ /dev/null
@@ -1,11 +0,0 @@
---- a/driver/wl_linux.c
-+++ b/driver/wl_linux.c
-@@ -1583,7 +1583,7 @@ wl_add_if(wl_info_t *wl, struct wlc_if*
- 
- 	wl_if_setup(wlif->dev);
- 
--	sprintf(wlif->dev->name, "%s%d.%d", devname, wl->pub->unit, wlif->subunit);
-+	sprintf(wlif->dev->name, "%s%d-%d", devname, wl->pub->unit, wlif->subunit);
- 	if (remote)
- 		bcopy(remote, &wlif->remote, ETHER_ADDR_LEN);
- 
diff --git a/package/kernel/broadcom-wl/patches/014-fix-band-reporting.patch b/package/kernel/broadcom-wl/patches/014-fix-band-reporting.patch
deleted file mode 100644
index b231fed98db63f..00000000000000
--- a/package/kernel/broadcom-wl/patches/014-fix-band-reporting.patch
+++ /dev/null
@@ -1,41 +0,0 @@
---- a/driver/wl_iw.c
-+++ b/driver/wl_iw.c
-@@ -314,7 +314,7 @@ wl_iw_get_name(
- )
- {
- 	int phytype, err;
--	uint band[3];
-+	uint i, band[3], bands;
- 	char cap[5];
- 
- 	WL_TRACE(("%s: SIOCGIWNAME\n", dev->name));
-@@ -335,16 +335,20 @@ wl_iw_get_name(
- 			break;
- 		case WLC_PHY_TYPE_LP:
- 		case WLC_PHY_TYPE_G:
--			if (band[0] >= 2)
--				strcpy(cap, "abg");
--			else
--				strcpy(cap, "bg");
--			break;
- 		case WLC_PHY_TYPE_N:
--			if (band[0] >= 2)
--				strcpy(cap, "abgn");
--			else
--				strcpy(cap, "bgn");
-+			bands = 0;
-+			for (i = 1; i <= band[0]; i++) {
-+				bands |= dtoh32(band[i]);
-+			}
-+			strcpy(cap, "");
-+			if (bands & WLC_BAND_5G)
-+				strcat(cap, "a");
-+			if (bands & WLC_BAND_2G)
-+				strcat(cap, "bg");
-+			if (phytype == WLC_PHY_TYPE_N)
-+				strcat(cap, "n");
-+			break;
-+		default:
- 			break;
- 	}
- done:
diff --git a/package/kernel/broadcom-wl/patches/015-support-probe-of-wds-interfaces.patch b/package/kernel/broadcom-wl/patches/015-support-probe-of-wds-interfaces.patch
deleted file mode 100644
index f44921a9547cdc..00000000000000
--- a/package/kernel/broadcom-wl/patches/015-support-probe-of-wds-interfaces.patch
+++ /dev/null
@@ -1,11 +0,0 @@
---- a/shared/wl.c
-+++ b/shared/wl.c
-@@ -27,7 +27,7 @@ wl_probe(char *name)
- {
- 	int ret, val;
- 
--	if ((name[0] != 'w') || (name[1] != 'l'))
-+	if ((name[0] != 'w') || ((name[1] != 'l') && ((name[1] != 'd') || (name[2] != 's'))))
- 		return -1;
- 
- 	/* Check interface */
diff --git a/package/kernel/broadcom-wl/patches/020-musl-fixes.patch b/package/kernel/broadcom-wl/patches/020-musl-fixes.patch
deleted file mode 100644
index a985b9c24a4245..00000000000000
--- a/package/kernel/broadcom-wl/patches/020-musl-fixes.patch
+++ /dev/null
@@ -1,75 +0,0 @@
---- a/shared/wl_linux.c
-+++ b/shared/wl_linux.c
-@@ -13,6 +13,7 @@
-  */
- 
- #include <stdio.h>
-+#include <stdint.h>
- #include <unistd.h>
- #include <string.h>
- #include <errno.h>
-@@ -20,10 +21,10 @@
- #include <net/if.h>
- #include <linux/types.h>
- 
--typedef u_int64_t u64;
--typedef u_int32_t u32;
--typedef u_int16_t u16;
--typedef u_int8_t u8;
-+typedef uint64_t u64;
-+typedef uint32_t u32;
-+typedef uint16_t u16;
-+typedef uint8_t u8;
- #include <linux/sockios.h>
- #include <linux/ethtool.h>
- 
---- a/shared/linux_timer.c
-+++ b/shared/linux_timer.c
-@@ -125,7 +125,7 @@ void unblock_timer();
- 
- static struct event *event_queue = NULL;
- static struct event *event_freelist;
--static uint g_granularity;
-+static unsigned int g_granularity;
- static int g_maxevents = 0;
- 
- uclock_t uclock()
---- a/shared/wl.c
-+++ b/shared/wl.c
-@@ -14,6 +14,7 @@
- #include <typedefs.h>
- #include <string.h>
- #include <stdio.h>
-+#include <stdlib.h>
- #include <unistd.h>
- #include <errno.h>
- #include <sys/ioctl.h>
-@@ -263,3 +264,28 @@ wl_printlasterror(char *name)
- 		fprintf(stderr, err_buf);
- }
- */
-+
-+static int in_assert;			/* bss inits to 0. */
-+
-+void __assert(const char *assertion, const char * filename,
-+	      unsigned int linenumber, register const char * function)
-+{
-+	if (!in_assert) {
-+		in_assert = 1;
-+
-+		fprintf(stderr,
-+#ifdef ASSERT_SHOW_PROGNAME
-+				"%s: %s: %d: %s: Assertion `%s' failed.\n", __uclibc_progname,
-+#else
-+				"%s: %d: %s: Assertion `%s' failed.\n",
-+#endif
-+				filename,
-+				linenumber,
-+				/* Function name isn't available with some compilers. */
-+				((function == NULL) ? "?function?" : function),
-+				assertion
-+				);
-+	}
-+	/* shouldn't we? fflush(stderr); */
-+	abort();
-+}
diff --git a/package/kernel/broadcom-wl/patches/030-remove_devinit_devexit.patch b/package/kernel/broadcom-wl/patches/030-remove_devinit_devexit.patch
deleted file mode 100644
index ead108e5b2cef7..00000000000000
--- a/package/kernel/broadcom-wl/patches/030-remove_devinit_devexit.patch
+++ /dev/null
@@ -1,74 +0,0 @@
---- a/driver/include/linuxver.h
-+++ b/driver/include/linuxver.h
-@@ -139,22 +139,6 @@ typedef	struct pcmcia_device dev_link_t;
- 
- #endif /* CONFIG_PCMCIA */
- 
--#ifndef __exit
--#define __exit
--#endif
--#ifndef __devexit
--#define __devexit
--#endif
--#ifndef __devinit
--#define __devinit	__init
--#endif
--#ifndef __devinitdata
--#define __devinitdata
--#endif
--#ifndef __devexit_p
--#define __devexit_p(x)	x
--#endif
--
- #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 0))
- 
- #define pci_get_drvdata(dev)		(dev)->sysdata
---- a/driver/wl_linux.c
-+++ b/driver/wl_linux.c
-@@ -854,7 +854,7 @@ wl_read_proc(char *buffer, char **start,
-  */
- #if !defined(BCMJTAG)
- #ifdef CONFIG_PCI
--static void __devexit wl_remove(struct pci_dev *pdev);
-+static void wl_remove(struct pci_dev *pdev);
- /** 
-  * determines if a device is a WL device, and if so, attaches it.
-  *
-@@ -862,7 +862,7 @@ static void __devexit wl_remove(struct p
-  * and if so, performs a wl_attach() on it.
-  *
-  */
--int __devinit
-+int
- wl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
- {
- 	int rc;
-@@ -976,7 +976,7 @@ wl_resume(struct pci_dev *pdev)
- }
- #endif /* LINUXSTA_PS */
- 
--static void __devexit
-+static void
- wl_remove(struct pci_dev *pdev)
- {
- 	wl_info_t *wl = (wl_info_t *) pci_get_drvdata(pdev);
-@@ -1007,7 +1007,7 @@ static struct pci_driver wl_pci_driver =
- 	suspend:	wl_suspend,
- 	resume:		wl_resume,
- #endif /* LINUXSTA_PS */
--	remove:		__devexit_p(wl_remove),
-+	remove:		wl_remove,
- 	id_table:	wl_id_table,
- 	};
- #endif	/* CONFIG_PCI */
---- a/driver/wl_linux.h
-+++ b/driver/wl_linux.h
-@@ -33,7 +33,7 @@ extern irqreturn_t wl_isr(int irq, void
- extern irqreturn_t wl_isr(int irq, void *dev_id, struct pt_regs *ptregs);
- #endif
- 
--extern int __devinit wl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
-+extern int wl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
- extern void wl_free(wl_info_t *wl);
- extern int  wl_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
- extern struct net_device * wl_netdev_get(wl_info_t *wl);
diff --git a/package/kernel/broadcom-wl/patches/040-remove_last_rx_usage.patch b/package/kernel/broadcom-wl/patches/040-remove_last_rx_usage.patch
deleted file mode 100644
index 5c3e72a229a803..00000000000000
--- a/package/kernel/broadcom-wl/patches/040-remove_last_rx_usage.patch
+++ /dev/null
@@ -1,10 +0,0 @@
---- a/driver/wl_linux.c
-+++ b/driver/wl_linux.c
-@@ -2762,7 +2762,6 @@ wl_monitor(wl_info_t *wl, wl_rxsts_t *rx
- 	bcopy(oskb->data + D11_PHY_HDR_LEN, pdata, oskb->len - D11_PHY_HDR_LEN);
- 
- 	skb->dev = wl->monitor;
--	skb->dev->last_rx = jiffies;
- #if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 22)
- 	skb_reset_mac_header(skb);
- #else
diff --git a/package/kernel/broadcom-wl/patches/100-fix_nvram_two_devices.patch b/package/kernel/broadcom-wl/patches/100-fix_nvram_two_devices.patch
deleted file mode 100644
index 6cf6faeddd1478..00000000000000
--- a/package/kernel/broadcom-wl/patches/100-fix_nvram_two_devices.patch
+++ /dev/null
@@ -1,32 +0,0 @@
---- a/driver/nvram_stub.c
-+++ b/driver/nvram_stub.c
-@@ -22,6 +22,7 @@ typedef struct _vars {
- #define	VARS_T_OH	sizeof(vars_t)
- 
- static vars_t *vars = NULL;
-+static int nvram_init_done = 0;
- extern char *nvram_buf[];
- 
- int
-@@ -33,6 +34,10 @@ BCMATTACHFN(nvram_init)(void *si)
- 	uint nvs, bufsz;
- 	vars_t *new;
- 
-+	nvram_init_done++;
-+	if (nvram_init_done != 1)
-+		return 0;
-+
- 	osh = si_osh(sih);
- 
- 	nvs = R_REG(osh, &nvh->len) - sizeof(struct nvram_header);
-@@ -79,6 +84,10 @@ BCMATTACHFN(nvram_exit)(void *si)
- 	vars_t *this, *next;
- 	si_t *sih;
- 
-+	nvram_init_done--;
-+	if (nvram_init_done != 0)
-+		return;
-+
- 	sih = (si_t *)si;
- 	this = vars;
- 	while (this) {
diff --git a/package/kernel/broadcom-wl/patches/101-wl_id-fix-compilation-warning-if-does-not-guard.patch b/package/kernel/broadcom-wl/patches/101-wl_id-fix-compilation-warning-if-does-not-guard.patch
deleted file mode 100644
index e5c17cb9b9b3de..00000000000000
--- a/package/kernel/broadcom-wl/patches/101-wl_id-fix-compilation-warning-if-does-not-guard.patch
+++ /dev/null
@@ -1,15 +0,0 @@
---- a/driver/wl_iw.c
-+++ a/driver/wl_iw.c
-@@ -381,9 +381,9 @@ wl_iw_set_freq(
- 			while (fwrq->e++ < 6)
- 				fwrq->m /= 10;
- 		}
--	/* handle 4.9GHz frequencies as Japan 4 GHz based channelization */
--	if (fwrq->m > 4000 && fwrq->m < 5000)
--		sf = WF_CHAN_FACTOR_4_G; /* start factor for 4 GHz */
-+		/* handle 4.9GHz frequencies as Japan 4 GHz based channelization */
-+		if (fwrq->m > 4000 && fwrq->m < 5000)
-+			sf = WF_CHAN_FACTOR_4_G; /* start factor for 4 GHz */
- 
- 		chan = wf_mhz2channel(fwrq->m, sf);
- 	}
diff --git a/package/kernel/broadcom-wl/patches/110-add_number_to_dev_name.patch b/package/kernel/broadcom-wl/patches/110-add_number_to_dev_name.patch
deleted file mode 100644
index 95f0beb73c9e00..00000000000000
--- a/package/kernel/broadcom-wl/patches/110-add_number_to_dev_name.patch
+++ /dev/null
@@ -1,11 +0,0 @@
---- a/driver/wl_linux.c
-+++ b/driver/wl_linux.c
-@@ -1425,7 +1425,7 @@ wl_alloc_if(wl_info_t *wl, int iftype, u
- 	dev = alloc_etherdev(sizeof(wl_if_t));
- 	wlif = netdev_priv(dev);
- 	bzero(wlif, sizeof(wl_if_t));
--	strncpy(dev->name, name, IFNAMSIZ);
-+	snprintf(dev->name, IFNAMSIZ, name, subunit);
- 
- 	wlif->type = iftype;
- 	wlif->dev = dev;
diff --git a/package/kernel/broadcom-wl/patches/120-fixup-mac-addresses.patch b/package/kernel/broadcom-wl/patches/120-fixup-mac-addresses.patch
deleted file mode 100644
index 422f7f784f57b3..00000000000000
--- a/package/kernel/broadcom-wl/patches/120-fixup-mac-addresses.patch
+++ /dev/null
@@ -1,93 +0,0 @@
---- a/driver/nvram_stub.c
-+++ b/driver/nvram_stub.c
-@@ -5,6 +5,8 @@
- #include <siutils.h>
- #include <bcmendian.h>
- #include <bcmnvram.h>
-+#include <proto/ethernet.h>
-+#include <linux/errno.h>
- 
- #ifdef BCMDBG_ERR
- #define NVR_MSG(x) printf x
-@@ -24,6 +26,7 @@ typedef struct _vars {
- static vars_t *vars = NULL;
- static int nvram_init_done = 0;
- extern char *nvram_buf[];
-+static void fixup_mac_addr(vars_t *new);
- 
- int
- BCMATTACHFN(nvram_init)(void *si)
-@@ -55,6 +58,7 @@ BCMATTACHFN(nvram_init)(void *si)
- 	vars = new;
- 
- 	bcopy((char *)(&nvh[1]), new->vars, nvs);
-+	fixup_mac_addr(new);
- 	return 0;
- }
- 
-@@ -164,3 +168,65 @@ nvram_getall(char *buf, int count)
- 	*buf = '\0';
- 	return 0;
- }
-+
-+static bool nvram_is_valid_mac(struct ether_addr *mac)
-+{
-+	return mac && !(mac->octet[0] == 0x00 && mac->octet[1] == 0x90 && mac->octet[2] == 0x4c);
-+}
-+
-+static int nvram_increase_mac_addr(struct ether_addr *mac, u8 num)
-+{
-+	u8 *oui = mac->octet + ETHER_ADDR_LEN/2 - 1;
-+	u8 *p = mac->octet + ETHER_ADDR_LEN - 1;
-+
-+	do {
-+		(*p) += num;
-+		if (*p > num)
-+			break;
-+		p--;
-+		num = 1;
-+	} while (p != oui);
-+
-+	if (p == oui) {
-+		pr_err("unable to fetch mac address\n");
-+		return -ENOENT;
-+	}
-+	return 0;
-+}
-+
-+static void nvram_change_mac_addr(vars_t *new, struct ether_addr *valid, const char *name)
-+{
-+	char *macaddr_c;
-+	struct ether_addr macaddr;
-+
-+	macaddr_c = findvar(new->vars, new->vars + new->size, name);
-+	if (!macaddr_c)
-+		return;
-+
-+	bcm_ether_atoe(macaddr_c, &macaddr);
-+	if (nvram_is_valid_mac(&macaddr))
-+		return;
-+	nvram_increase_mac_addr(valid, 1);
-+	bcm_ether_ntoa(valid, macaddr_c);
-+}
-+
-+static void fixup_mac_addr(vars_t *new)
-+{
-+	char *macaddr_base_c;
-+	struct ether_addr macaddr_base;
-+
-+	macaddr_base_c = findvar(new->vars, new->vars + new->size, "et0macaddr");
-+	if (!macaddr_base_c)
-+		return;
-+
-+	bcm_ether_atoe(macaddr_base_c, &macaddr_base);
-+	if (!nvram_is_valid_mac(&macaddr_base))
-+		return;
-+
-+	/* jump over the first free address so it can be used for wan */
-+	nvram_increase_mac_addr(&macaddr_base, 1);
-+	nvram_change_mac_addr(new, &macaddr_base, "sb/1/macaddr");
-+	nvram_change_mac_addr(new, &macaddr_base, "pci/1/1/macaddr");
-+	nvram_change_mac_addr(new, &macaddr_base, "pci/1/2/macaddr");
-+	nvram_change_mac_addr(new, &macaddr_base, "pci/2/1/macaddr");
-+}
diff --git a/package/kernel/broadcom-wl/patches/200-add_bcm_a8xx_support.patch b/package/kernel/broadcom-wl/patches/200-add_bcm_a8xx_support.patch
deleted file mode 100644
index c1d13440032edf..00000000000000
--- a/package/kernel/broadcom-wl/patches/200-add_bcm_a8xx_support.patch
+++ /dev/null
@@ -1,12 +0,0 @@
---- a/driver/wl_linux.c
-+++ b/driver/wl_linux.c
-@@ -876,7 +876,8 @@ wl_pci_probe(struct pci_dev *pdev, const
- 
- 	if ((pdev->vendor != PCI_VENDOR_ID_BROADCOM) ||
- 	    (((pdev->device & 0xff00) != 0x4300) &&
--	     ((pdev->device & 0xff00) != 0x4700)))
-+	     ((pdev->device & 0xff00) != 0x4700) &&
-+	     ((pdev->device & 0xff00) != 0xa800)))
- 		return (-ENODEV);
- 
- 	rc = pci_enable_device(pdev);
diff --git a/package/kernel/broadcom-wl/patches/910-fallback-sprom.patch b/package/kernel/broadcom-wl/patches/910-fallback-sprom.patch
deleted file mode 100644
index a85e40bc14019c..00000000000000
--- a/package/kernel/broadcom-wl/patches/910-fallback-sprom.patch
+++ /dev/null
@@ -1,78 +0,0 @@
---- a/driver/bcmsrom.c
-+++ b/driver/bcmsrom.c
-@@ -39,6 +39,11 @@
- #include <sbsdpcmdev.h>
- #endif 
- 
-+#if defined(CONFIG_SSB_PCIHOST) && defined(CONFIG_BOARD_BCM963XX)
-+#include <linux/ssb/ssb.h>
-+extern int bcm63xx_get_fallback_sprom(uint pci_bus, uint pci_slot, struct ssb_sprom *out);
-+#endif
-+
- #ifdef WLTEST
- #include <sbsprom.h>
- #endif /* WLTEST */
-@@ -2120,6 +2125,63 @@ BCMATTACHFN(initvars_srom_pci)(si_t *sih
- 			goto varscont;
- 		}
- 
-+#if defined(CONFIG_SSB_PCIHOST) && defined(CONFIG_BOARD_BCM963XX)
-+		base = vp = MALLOC(osh, MAXSZ_NVRAM_VARS);
-+
-+		if( base != NULL )
-+		{
-+			char eabuf[18];
-+			struct ssb_sprom bcm63xx_sprom;
-+			uint pci_bus = osl_pci_bus(osh), pci_slot = osl_pci_slot(osh);
-+
-+			bcm63xx_get_fallback_sprom(pci_bus, pci_slot, &bcm63xx_sprom);
-+			printk("BCM%X(%02x:%02x) using sprom version %i\n", sih->chip, pci_bus, pci_slot, bcm63xx_sprom.revision);
-+
-+			varbuf_init(&b, base, MAXSZ_NVRAM_VARS);
-+
-+			varbuf_append(&b, vstr_sromrev, bcm63xx_sprom.revision);
-+			varbuf_append(&b, vstr_boardrev, bcm63xx_sprom.board_rev);
-+
-+			/* ToDo: map bcm63xx_sprom.country_code */
-+			varbuf_append(&b, vstr_noccode);
-+
-+			varbuf_append(&b, vstr_aa2g, bcm63xx_sprom.ant_available_bg);
-+
-+			varbuf_append(&b, vstr_pa0b[0], bcm63xx_sprom.pa0b0);
-+			varbuf_append(&b, vstr_pa1b[0], bcm63xx_sprom.pa1b0);
-+			varbuf_append(&b, vstr_pa0b[1], bcm63xx_sprom.pa0b1);
-+			varbuf_append(&b, vstr_pa1b[1], bcm63xx_sprom.pa1b1);
-+			varbuf_append(&b, vstr_pa0b[2], bcm63xx_sprom.pa0b2);
-+			varbuf_append(&b, vstr_pa1b[2], bcm63xx_sprom.pa1b2);
-+
-+			varbuf_append(&b, vstr_pa0maxpwr, bcm63xx_sprom.maxpwr_bg);
-+			varbuf_append(&b, vstr_pa0itssit, bcm63xx_sprom.itssi_bg);
-+
-+			varbuf_append(&b, vstr_boardflags, (bcm63xx_sprom.boardflags_hi << 16) | bcm63xx_sprom.boardflags_lo);
-+			varbuf_append(&b, vstr_boardflags2, (bcm63xx_sprom.boardflags2_hi << 16) | bcm63xx_sprom.boardflags2_lo);
-+
-+			snprintf(eabuf, sizeof(eabuf), "%02x:%02x:%02x:%02x:%02x:%02x",
-+				bcm63xx_sprom.il0mac[0], bcm63xx_sprom.il0mac[1], bcm63xx_sprom.il0mac[2],
-+				bcm63xx_sprom.il0mac[3], bcm63xx_sprom.il0mac[4], bcm63xx_sprom.il0mac[5]
-+			);
-+
-+			varbuf_append(&b, vstr_macaddr, eabuf);
-+
-+			/* final nullbyte terminator */
-+			ASSERT(b.size >= 1);
-+			vp = b.buf;
-+			*vp++ = '\0';
-+
-+			ASSERT((vp - base) <= MAXSZ_NVRAM_VARS);
-+			goto varsdone;
-+		}
-+		else
-+		{
-+			err = -2;
-+			goto errout;
-+		}
-+#endif
-+
- 		BS_ERROR(("SROM CRC Error\n"));
- 
- #if defined(WLTEST)
diff --git a/package/kernel/broadcom-wl/patches/912-pci-bus-nvram-hack.patch b/package/kernel/broadcom-wl/patches/912-pci-bus-nvram-hack.patch
deleted file mode 100644
index 65e8bd39580485..00000000000000
--- a/package/kernel/broadcom-wl/patches/912-pci-bus-nvram-hack.patch
+++ /dev/null
@@ -1,11 +0,0 @@
---- a/driver/siutils.c
-+++ b/driver/siutils.c
-@@ -1859,7 +1859,7 @@ BCMINITFN(si_devpath)(si_t *sih, char *p
- 	case PCI_BUS:
- 		ASSERT((SI_INFO(sih))->osh != NULL);
- 		slen = snprintf(path, (size_t)size, "pci/%u/%u/",
--		                OSL_PCI_BUS((SI_INFO(sih))->osh),
-+		                OSL_PCI_BUS((SI_INFO(sih))->osh) + 1,
- 		                OSL_PCI_SLOT((SI_INFO(sih))->osh));
- 		break;
- 	case PCMCIA_BUS:
diff --git a/package/kernel/broadcom-wl/patches/913-avoid-dbe-on-ifs_ctl-readw-hack.patch b/package/kernel/broadcom-wl/patches/913-avoid-dbe-on-ifs_ctl-readw-hack.patch
deleted file mode 100644
index 412bce92c83b42..00000000000000
--- a/package/kernel/broadcom-wl/patches/913-avoid-dbe-on-ifs_ctl-readw-hack.patch
+++ /dev/null
@@ -1,12 +0,0 @@
---- a/driver/linux_osl.c
-+++ b/driver/linux_osl.c
-@@ -723,6 +723,9 @@ osl_readl(volatile uint32 *r)
- uint16
- osl_readw(volatile uint16 *r)
- {
-+	uint32 addr = (uintptr)r & 0xffff3fff;
-+	if (addr == 0xa8000688)	/* ifs_ctl */
-+		readl(r);
- 	return (readw(r));
- }
- 
diff --git a/package/kernel/broadcom-wl/patches/914-eliminate-date-time-error.patch b/package/kernel/broadcom-wl/patches/914-eliminate-date-time-error.patch
deleted file mode 100644
index 394a06d98c1086..00000000000000
--- a/package/kernel/broadcom-wl/patches/914-eliminate-date-time-error.patch
+++ /dev/null
@@ -1,21 +0,0 @@
---- a/driver/wl_linux.c
-+++ b/driver/wl_linux.c
-@@ -762,7 +762,7 @@ wl_attach(uint16 vendor, uint16 device,
- 		dev->name, device);
- 
- #ifdef BCMDBG
--	printf(" (Compiled in " SRCBASE " at " __TIME__ " on " __DATE__ ")");
-+	printf(" (Compiled in " SRCBASE ")");
- #endif /* BCMDBG */
- 	printf("\n");
- 
-@@ -2298,8 +2298,7 @@ wl_sendup(wl_info_t *wl, wl_if_t *wlif,
- void
- wl_dump_ver(wl_info_t *wl, struct bcmstrbuf *b)
- {
--	bcm_bprintf(b, "wl%d: %s %s version %s\n", wl->pub->unit,
--		__DATE__, __TIME__, EPI_VERSION_STR);
-+	bcm_bprintf(b, "wl%d: version %s\n", wl->pub->unit, EPI_VERSION_STR);
- }
- 
- #ifdef BCMDBG
diff --git a/package/kernel/broadcom-wl/patches/915-fix-wl_timer-for-4_15.patch b/package/kernel/broadcom-wl/patches/915-fix-wl_timer-for-4_15.patch
deleted file mode 100644
index 66eba968cf623b..00000000000000
--- a/package/kernel/broadcom-wl/patches/915-fix-wl_timer-for-4_15.patch
+++ /dev/null
@@ -1,55 +0,0 @@
---- a/driver/wl_linux.c
-+++ b/driver/wl_linux.c
-@@ -235,7 +235,11 @@ struct wl_info {
- 
- };
- 
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0)
-+static void wl_timer(struct timer_list *tl);
-+#else
- static void wl_timer(ulong data);
-+#endif
- static void _wl_timer(wl_timer_t *t);
- 
- #ifdef WLC_HIGH_ONLY
-@@ -2512,6 +2516,18 @@ wl_timer_task(wl_task_t *task)
- }
- #endif /* WLC_HIGH_ONLY */
- 
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0)
-+static void
-+wl_timer(struct timer_list *tl)
-+{
-+	wl_timer_t *t = from_timer(t, tl, timer);
-+#ifndef WLC_HIGH_ONLY
-+	_wl_timer(t);
-+#else
-+	wl_schedule_task(t->wl, wl_timer_task, t);
-+#endif /* WLC_HIGH_ONLY */
-+}
-+#else
- static void
- wl_timer(ulong data)
- {
-@@ -2522,6 +2538,7 @@ wl_timer(ulong data)
- 	wl_schedule_task(t->wl, wl_timer_task, t);
- #endif /* WLC_HIGH_ONLY */
- }
-+#endif /* linux >= 4.15.0 */
- 
- static void
- _wl_timer(wl_timer_t *t)
-@@ -2573,9 +2590,13 @@ wl_init_timer(wl_info_t *wl, void (*fn)(
- 
- 	bzero(t, sizeof(wl_timer_t));
- 
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0)
-+	timer_setup(&t->timer, wl_timer, 0);
-+#else
- 	init_timer(&t->timer);
- 	t->timer.data = (ulong) t;
- 	t->timer.function = wl_timer;
-+#endif
- 	t->wl = wl;
- 	t->fn = fn;
- 	t->arg = arg;
diff --git a/package/kernel/broadcom-wl/patches/916-fix-compilation-for-5_4.patch b/package/kernel/broadcom-wl/patches/916-fix-compilation-for-5_4.patch
deleted file mode 100644
index e59c95722c783f..00000000000000
--- a/package/kernel/broadcom-wl/patches/916-fix-compilation-for-5_4.patch
+++ /dev/null
@@ -1,18 +0,0 @@
---- a/driver/wl_iw.c
-+++ b/driver/wl_iw.c
-@@ -112,10 +112,14 @@ dev_wlc_ioctl(
- 	ifr.ifr_data = (caddr_t) &ioc;
- 
- 	/* Must be up for virtually all useful ioctls */
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 0, 0)
-+	dev_open(dev, NULL);
-+#else
- 	dev_open(dev);
-+#endif
- 
- 	fs = get_fs();
--	set_fs(get_ds());
-+	set_fs(KERNEL_DS);
- 	ret = dev->netdev_ops->ndo_do_ioctl(dev, &ifr, SIOCDEVPRIVATE);
- 	set_fs(fs);
- 
diff --git a/package/kernel/broadcom-wl/patches/917-fix-compilation-for-5_10.patch b/package/kernel/broadcom-wl/patches/917-fix-compilation-for-5_10.patch
deleted file mode 100644
index 98c0375be344fe..00000000000000
--- a/package/kernel/broadcom-wl/patches/917-fix-compilation-for-5_10.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-Index: broadcom-wl-5.10.56.27.3/driver/wl_linux.c
-===================================================================
---- broadcom-wl-5.10.56.27.3.orig/driver/wl_linux.c
-+++ broadcom-wl-5.10.56.27.3/driver/wl_linux.c
-@@ -74,6 +74,10 @@
- #error "No support for Kernel Rev <= 2.4.5, As the older kernel revs doesn't support Tasklets"
- #endif
- 
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 6, 0)
-+#define ioremap_nocache	ioremap
-+#endif
-+
- typedef void wlc_info_t;
- typedef void wlc_hw_info_t;
- #include <wlc_pub.h>
-@@ -1915,7 +1919,11 @@ wl_ioctl(struct net_device *dev, struct
- 	}
- 
- 	/* optimization for direct ioctl calls from kernel */
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 9, 0)
- 	if (segment_eq(get_fs(), KERNEL_DS))
-+#else
-+	if (uaccess_kernel())
-+#endif
- 		buf = ioc.buf;
- 
- 	else if (ioc.buf) {
-Index: broadcom-wl-5.10.56.27.3/driver/linux_osl.c
-===================================================================
---- broadcom-wl-5.10.56.27.3.orig/driver/linux_osl.c
-+++ broadcom-wl-5.10.56.27.3/driver/linux_osl.c
-@@ -34,6 +34,10 @@
- #define OS_HANDLE_MAGIC		0x1234abcd	/* Magic # to recognise osh */
- #define BCM_MEM_FILENAME_LEN 	24		/* Mem. filename length */
- 
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 6, 0)
-+#define ioremap_nocache	ioremap
-+#endif
-+
- typedef struct bcm_mem_link {
- 	struct bcm_mem_link *prev;
- 	struct bcm_mem_link *next;
diff --git a/package/kernel/broadcom-wl/patches/918-fix-warning-compilation-for-5_15.patch b/package/kernel/broadcom-wl/patches/918-fix-warning-compilation-for-5_15.patch
deleted file mode 100644
index 4ddb6433733cd3..00000000000000
--- a/package/kernel/broadcom-wl/patches/918-fix-warning-compilation-for-5_15.patch
+++ /dev/null
@@ -1,27 +0,0 @@
---- a/driver/wl_iw.c
-+++ a/driver/wl_iw.c
-@@ -100,7 +100,9 @@ dev_wlc_ioctl(
- {
- 	struct ifreq ifr;
- 	wl_ioctl_t ioc;
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 13, 0)
- 	mm_segment_t fs;
-+#endif
- 	int ret;
- 
- 	memset(&ioc, 0, sizeof(ioc));
-@@ -118,10 +120,14 @@ dev_wlc_ioctl(
- 	dev_open(dev);
- #endif
- 
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 13, 0)
- 	fs = get_fs();
- 	set_fs(KERNEL_DS);
-+#endif
- 	ret = dev->netdev_ops->ndo_do_ioctl(dev, &ifr, SIOCDEVPRIVATE);
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 13, 0)
- 	set_fs(fs);
-+#endif
- 
- 	return ret;
- }
diff --git a/package/kernel/broadcom-wl/patches/919-fix-compilation-warning-for-stack-limit.patch b/package/kernel/broadcom-wl/patches/919-fix-compilation-warning-for-stack-limit.patch
deleted file mode 100644
index 3149ce34b9180b..00000000000000
--- a/package/kernel/broadcom-wl/patches/919-fix-compilation-warning-for-stack-limit.patch
+++ /dev/null
@@ -1,297 +0,0 @@
---- a/driver/wl_iw.c
-+++ b/driver/wl_iw.c
-@@ -495,9 +495,9 @@ wl_iw_get_range(
- )
- {
- 	struct iw_range *range = (struct iw_range *) extra;
--	int channels[MAXCHANNEL+1];
--	wl_uint32_list_t *list = (wl_uint32_list_t *) channels;
--	wl_rateset_t rateset;
-+	int *channels;
-+	wl_uint32_list_t *list;
-+	wl_rateset_t *rateset;
- 	int error, i;
- 	uint sf, ch;
- 
-@@ -506,6 +506,17 @@ wl_iw_get_range(
- 	if (!extra)
- 		return -EINVAL;
- 
-+	channels = kcalloc(MAXCHANNEL+1, sizeof(*channels), GFP_KERNEL);
-+	if (!channels)
-+		return -ENOMEM;
-+	list = (wl_uint32_list_t *) channels;
-+
-+	rateset = kzalloc(sizeof(*rateset), GFP_KERNEL);
-+	if (!rateset) {
-+		error = -ENOMEM;
-+		goto free_channels;
-+	}
-+
- 	dwrq->length = sizeof(struct iw_range);
- 	memset(range, 0, sizeof(range));
- 
-@@ -514,8 +525,9 @@ wl_iw_get_range(
- 
- 	/* Set available channels/frequencies */
- 	list->count = htod32(MAXCHANNEL);
--	if ((error = dev_wlc_ioctl(dev, WLC_GET_VALID_CHANNELS, channels, sizeof(channels))))
--		return error;
-+	if ((error = dev_wlc_ioctl(dev, WLC_GET_VALID_CHANNELS, channels,
-+				   (MAXCHANNEL+1) * sizeof(*channels))))
-+		goto free_rateset;
- 	for (i = 0; i < dtoh32(list->count) && i < IW_MAX_FREQUENCIES; i++) {
- 		range->freq[i].i = dtoh32(list->element[i]);
- 
-@@ -549,19 +561,19 @@ wl_iw_get_range(
- #endif /* WIRELESS_EXT > 11 */
- 
- 	/* Set available bitrates */
--	if ((error = dev_wlc_ioctl(dev, WLC_GET_CURR_RATESET, &rateset, sizeof(rateset))))
--		return error;
--	rateset.count = dtoh32(rateset.count);
--	range->num_bitrates = rateset.count;
--	for (i = 0; i < rateset.count && i < IW_MAX_BITRATES; i++)
--		range->bitrate[i] = (rateset.rates[i] & 0x7f) * 500000; /* convert to bps */
-+	if ((error = dev_wlc_ioctl(dev, WLC_GET_CURR_RATESET, rateset, sizeof(*rateset))))
-+		goto free_rateset;
-+	rateset->count = dtoh32(rateset->count);
-+	range->num_bitrates = rateset->count;
-+	for (i = 0; i < rateset->count && i < IW_MAX_BITRATES; i++)
-+		range->bitrate[i] = (rateset->rates[i] & 0x7f) * 500000; /* convert to bps */
- 
- 	/* Set an indication of the max TCP throughput
- 	 * in bit/s that we can expect using this interface.
- 	 * May be use for QoS stuff... Jean II
- 	 */
- 	if ((error = dev_wlc_ioctl(dev, WLC_GET_PHYTYPE, &i, sizeof(i))))
--		return error;
-+		goto free_rateset;
- 	i = dtoh32(i);
- 	if (i == WLC_PHY_TYPE_A)
- 		range->throughput = 24000000;	/* 24 Mbits/s */
-@@ -624,7 +636,12 @@ wl_iw_get_range(
- #endif
- #endif /* WIRELESS_EXT > 17 */
- 
--	return 0;
-+free_rateset:
-+	kfree(rateset);
-+free_channels:
-+	kfree(channels);
-+
-+	return error;
- }
- 
- static int
---- a/driver/bcmsrom.c
-+++ b/driver/bcmsrom.c
-@@ -437,20 +437,37 @@ srom_write(si_t *sih, uint bustype, void *curmap, osl_t *osh,
-            uint byteoff, uint nbytes, uint16 *buf)
- {
- 	uint i, nw, crc_range;
--	uint16 old[SROM_MAXW], new[SROM_MAXW];
-+	uint16 *old, *new;
- 	uint8 crc;
- 	volatile uint32 val32;
-+	int rc = 0;
- 
- 	ASSERT(bustype == BUSTYPE(bustype));
- 
-+	old = MALLOC(osh, SROM_MAXW);
-+	ASSERT(old != NULL);
-+	if (!old)
-+		return -2;
-+
-+	new = MALLOC(osh, SROM_MAXW);
-+	ASSERT(new != NULL);
-+	if (!new) {
-+		rc = -2;
-+		goto free_old;
-+	}
-+
- 	/* check input - 16-bit access only. use byteoff 0x55aa to indicate
- 	 * srclear
- 	 */
--	if ((byteoff != 0x55aa) && ((byteoff & 1) || (nbytes & 1)))
--		return 1;
-+	if ((byteoff != 0x55aa) && ((byteoff & 1) || (nbytes & 1))) {
-+		rc = 1;
-+		goto free_new;
-+	}
- 
--	if ((byteoff != 0x55aa) && ((byteoff + nbytes) > SROM_MAX))
--		return 1;
-+	if ((byteoff != 0x55aa) && ((byteoff + nbytes) > SROM_MAX)) {
-+		rc = 1;
-+		goto free_new;
-+	}
- 
- 	if (BUSTYPE(bustype) == PCMCIA_BUS) {
- 		crc_range = SROM_MAX;
-@@ -467,8 +484,10 @@ srom_write(si_t *sih, uint bustype, void *curmap, osl_t *osh,
- 
- 	nw = crc_range / 2;
- 	/* read first small number words from srom, then adjust the length, read all */
--	if (srom_read(sih, bustype, curmap, osh, 0, crc_range, old, FALSE))
--		return 1;
-+	if (srom_read(sih, bustype, curmap, osh, 0, crc_range, old, FALSE)) {
-+		rc = 1;
-+		goto free_new;
-+	}
- 
- 	BS_ERROR(("%s: old[SROM4_SIGN] 0x%x, old[SROM8_SIGN] 0x%x\n",
- 	          __FUNCTION__, old[SROM4_SIGN], old[SROM8_SIGN]));
-@@ -481,10 +500,13 @@ srom_write(si_t *sih, uint bustype, void *curmap, osl_t *osh,
- 				__FUNCTION__, buf[SROM4_SIGN], buf[SROM8_SIGN]));
- 
- 			/* block invalid buffer size */
--			if (nbytes < SROM4_WORDS * 2)
--				return BCME_BUFTOOSHORT;
--			else if (nbytes > SROM4_WORDS * 2)
--				return BCME_BUFTOOLONG;
-+			if (nbytes < SROM4_WORDS * 2) {
-+				rc = BCME_BUFTOOSHORT;
-+				goto free_new;
-+			} else if (nbytes > SROM4_WORDS * 2) {
-+				rc = BCME_BUFTOOLONG;
-+				goto free_new;
-+			}
- 
- 			nw = SROM4_WORDS;
- 		} else if (nbytes == SROM_WORDS * 2){ /* the other possible SROM format */
-@@ -493,17 +515,22 @@ srom_write(si_t *sih, uint bustype, void *curmap, osl_t *osh,
- 			nw = SROM_WORDS;
- 		} else {
- 			BS_ERROR(("%s: Invalid input file signature\n", __FUNCTION__));
--			return BCME_BADARG;
-+			rc = BCME_BADARG;
-+			goto free_new;
- 		}
- 		crc_range = nw * 2;
--		if (srom_read(sih, bustype, curmap, osh, 0, crc_range, old, FALSE))
--			return 1;
-+		if (srom_read(sih, bustype, curmap, osh, 0, crc_range, old, FALSE)) {
-+			rc = 1;
-+			goto free_new;
-+		}
- 	} else if ((old[SROM4_SIGN] == SROM4_SIGNATURE) ||
- 	    (old[SROM8_SIGN] == SROM4_SIGNATURE)) {
- 		nw = SROM4_WORDS;
- 		crc_range = nw * 2;
--		if (srom_read(sih, bustype, curmap, osh, 0, crc_range, old, FALSE))
--			return 1;
-+		if (srom_read(sih, bustype, curmap, osh, 0, crc_range, old, FALSE)) {
-+			rc = 1;
-+			goto free_new;
-+		}
- 	} else {
- 		/* Assert that we have already read enough for sromrev 2 */
- 		ASSERT(crc_range >= SROM_WORDS * 2);
-@@ -562,8 +589,10 @@ srom_write(si_t *sih, uint bustype, void *curmap, osl_t *osh,
- 		}
- 	} else if (BUSTYPE(bustype) == PCMCIA_BUS) {
- 		/* enable writes to the SPROM */
--		if (sprom_cmd_pcmcia(osh, SROM_WEN))
--			return 1;
-+		if (sprom_cmd_pcmcia(osh, SROM_WEN)) {
-+			rc = 1;
-+			goto free_new;
-+		}
- 		bcm_mdelay(WRITE_ENABLE_DELAY);
- 		/* write srom */
- 		for (i = 0; i < nw; i++) {
-@@ -573,14 +602,15 @@ srom_write(si_t *sih, uint bustype, void *curmap, osl_t *osh,
- 			}
- 		}
- 		/* disable writes to the SPROM */
--		if (sprom_cmd_pcmcia(osh, SROM_WDS))
--			return 1;
-+		if (sprom_cmd_pcmcia(osh, SROM_WDS)) {
-+			rc = 1;
-+			goto free_new;
-+		}
- 	} else if (BUSTYPE(bustype) == SI_BUS) {
- #if defined(BCMUSBDEV)
- 		if (SPROMBUS == PCMCIA_BUS) {
- 			uint origidx;
- 			void *regs;
--			int rc;
- 			bool wasup;
- 
- 			origidx = si_coreidx(sih);
-@@ -596,16 +626,24 @@ srom_write(si_t *sih, uint bustype, void *curmap, osl_t *osh,
- 				si_core_disable(sih, 0);
- 
- 			si_setcoreidx(sih, origidx);
--			return rc;
-+			goto free_new;
- 		}
- #endif 
--		return 1;
-+		rc = 1;
-+		goto free_new;
- 	} else {
--		return 1;
-+		rc = 1;
-+		goto free_new;
- 	}
- 
- 	bcm_mdelay(WRITE_ENABLE_DELAY);
--	return 0;
-+	rc = 0;
-+
-+free_new:
-+	MFREE(osh, new, SROM_MAXW);
-+free_old:
-+	MFREE(osh, old, SROM_MAXW);
-+	return rc;
- }
- 
- #if defined(BCMUSBDEV)
---- a/driver/linux_osl.c
-+++ b/driver/linux_osl.c
-@@ -600,20 +600,29 @@ int
- osl_printf(const char *format, ...)
- {
- 	va_list args;
--	char buf[1024];
-+	char *buf;
- 	int len;
- 
-+	buf = kcalloc(1024, sizeof(*buf), GFP_KERNEL);
-+	if (!buf)
-+		return (-ENOMEM);
-+
- 	/* sprintf into a local buffer because there *is* no "vprintk()".. */
- 	va_start(args, format);
- 	len = vsnprintf(buf, 1024, format, args);
- 	va_end(args);
- 
--	if (len > sizeof(buf)) {
-+	if (len > (sizeof(*buf) * 1024)) {
- 		printk("osl_printf: buffer overrun\n");
--		return (0);
-+		goto exit;
- 	}
- 
--	return (printk(buf));
-+	printk(buf);
-+
-+exit:
-+	kfree(buf);
-+
-+	return (0);
- }
- 
- int
---- a/driver/bcmutils.c
-+++ b/driver/bcmutils.c
-@@ -13,6 +13,7 @@
- 
- #include <typedefs.h>
- #include <bcmdefs.h>
-+#define __need___va_list
- #include <stdarg.h>
- #include <bcmutils.h>
- #ifdef BCMDRIVER
diff --git a/package/kernel/broadcom-wl/patches/920-aiutils-fix-wrong-misleading-if.patch b/package/kernel/broadcom-wl/patches/920-aiutils-fix-wrong-misleading-if.patch
deleted file mode 100644
index c43dca9e896f01..00000000000000
--- a/package/kernel/broadcom-wl/patches/920-aiutils-fix-wrong-misleading-if.patch
+++ /dev/null
@@ -1,14 +0,0 @@
---- a/driver/aiutils.c
-+++ b/driver/aiutils.c
-@@ -228,9 +228,10 @@ ai_scan(si_t *sih, void *regs, uint devid)
- 		do {
- 			asd = get_asd(sih, &eromptr, 0, j, AD_ST_SLAVE, &addrl, &addrh,
- 			              &sizel, &sizeh);
--			if ((asd != 0) && (j == 1) && (sizel == SI_CORE_SIZE))
-+			if ((asd != 0) && (j == 1) && (sizel == SI_CORE_SIZE)) {
- 				sii->coresba2[idx] = addrl;
- 				sii->coresba2_size[idx] = sizel;
-+			}
- 			j++;
- 		} while (asd != 0);
- 
diff --git a/package/kernel/broadcom-wl/patches/921-fix-simple-compilation-warning.patch b/package/kernel/broadcom-wl/patches/921-fix-simple-compilation-warning.patch
deleted file mode 100644
index 2158dc67b80a5f..00000000000000
--- a/package/kernel/broadcom-wl/patches/921-fix-simple-compilation-warning.patch
+++ /dev/null
@@ -1,63 +0,0 @@
---- a/driver/hnddma.c
-+++ b/driver/hnddma.c
-@@ -1896,7 +1896,8 @@ dma64_txfast(dma_info_t *di, void *p0, bool commit)
- 	if (!(flags & D64_CTRL1_EOF)) {
- #if defined(linux) && defined(__mips__)
- 		if (CHIPID(di->sih->chip) == BCM5356_CHIP_ID && di->sih->chiprev == 0) {
--			uint32 ctrl1, ctrl2, addrlow, addrhigh;
-+			uint32 ctrl2, addrlow, addrhigh;
-+			// uint32 ctrl1;
- 
- 			addrlow = R_SM((volatile uint32 *)&di->txd64[PREVTXD(txout)].addrlow);
- 			addrhigh = R_SM((volatile uint32 *)&di->txd64[PREVTXD(txout)].addrhigh);
- 
---- a/driver/include/linux_osl.h
-+++ b/driver/include/linux_osl.h
-@@ -580,9 +580,9 @@ extern void osl_writew(uint16 v, volatile uint16 *r);
- extern void osl_writel(uint32 v, volatile uint32 *r);
- 
- /* uncached/cached virtual address */
--#define OSL_UNCACHED(va)	osl_uncached((va))
-+#define OSL_UNCACHED(va)	osl_uncached((void *)(va))
- extern void *osl_uncached(void *va);
--#define OSL_CACHED(va)		osl_cached((va))
-+#define OSL_CACHED(va)		osl_cached((void *)(va))
- extern void *osl_cached(void *va);
- 
- /* get processor cycle count */
---- a/driver/siutils.c
-+++ b/driver/siutils.c
-@@ -495,11 +495,13 @@ BCMATTACHFN(si_doattach)(si_info_t *sii, uint devid, osl_t *osh, void *regs,
- 	}
- 
- 	sih->bustype = bustype;
-+#ifdef BCMBUSTYPE
- 	if (bustype != BUSTYPE(bustype)) {
- 		SI_ERROR(("si_doattach: bus type %d does not match configured bus type %d\n",
- 			bustype, BUSTYPE(bustype)));
- 		return NULL;
- 	}
-+#endif
- 
- 	/* bus/core/clk setup for register access */
- 	if (!si_buscore_prep(sii, bustype, devid, sdh)) {
-@@ -1716,6 +1718,9 @@ si_clkctl_xtal(si_t *sih, uint what, bool on)
- 			                     outen);
- 		}
- 
-+		return (0);
-+
-+
- 	default:
- 		return (-1);
- 	}
---- a/driver/bcmsrom.c
-+++ b/driver/bcmsrom.c
-@@ -1005,6 +1043,7 @@ BCMNMIATTACHFN(srom_parsecis)(osl_t *osh, uint8 *pcis[], uint ciscnt, char **var
- 					break;
- 				}
- 
-+				fallthrough;
- 			case CISTPL_MANFID: FROMHOST();
- 				varbuf_append(&b, vstr_manfid, (cis[i + 1] << 8) + cis[i]);
- 				varbuf_append(&b, vstr_prodid, (cis[i + 3] << 8) + cis[i + 2]);
diff --git a/package/kernel/broadcom-wl/patches/930-wl_linux-set-module-license-Proprietary.patch b/package/kernel/broadcom-wl/patches/930-wl_linux-set-module-license-Proprietary.patch
deleted file mode 100644
index 6d0571711c474d..00000000000000
--- a/package/kernel/broadcom-wl/patches/930-wl_linux-set-module-license-Proprietary.patch
+++ /dev/null
@@ -1,10 +0,0 @@
---- a/driver/wl_linux.c
-+++ b/driver/wl_linux.c
-@@ -1109,6 +1109,7 @@ wl_module_exit(void)
- 
- module_init(wl_module_init);
- module_exit(wl_module_exit);
-+MODULE_LICENSE("Proprietary");
- 
- /** 
-  * This function frees the WL per-device resources.
diff --git a/package/kernel/broadcom-wl/src/glue/Makefile b/package/kernel/broadcom-wl/src/glue/Makefile
deleted file mode 100644
index f434d2430e1f8d..00000000000000
--- a/package/kernel/broadcom-wl/src/glue/Makefile
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# Makefile for wl_glue driver
-#
-# Copyright (C) 2011 Jo-Philipp Wich <jo@mein.io>
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# as published by the Free Software Foundation; either version
-# 2 of the License, or (at your option) any later version.
-#
-
-obj-m := wl_glue.o
-
-ifeq ($(MAKING_MODULES),1)
--include $(TOPDIR)/Rules.make
-endif
-
diff --git a/package/kernel/broadcom-wl/src/glue/wl_glue.c b/package/kernel/broadcom-wl/src/glue/wl_glue.c
deleted file mode 100644
index 7851f414dbce82..00000000000000
--- a/package/kernel/broadcom-wl/src/glue/wl_glue.c
+++ /dev/null
@@ -1,315 +0,0 @@
-/*
- * wl_glue.c: Broadcom WL support module providing a unified SSB/BCMA handling.
- * Copyright (C) 2011 Jo-Philipp Wich <jo@mein.io>
- */
-
-#include "wl_glue.h"
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/init.h>
-
-#ifdef CONFIG_BCM47XX
-#include <bcm47xx.h>
-#endif
-
-#ifdef CONFIG_SSB
-#include <linux/ssb/ssb.h>
-#endif
-
-#ifdef CONFIG_BCMA
-#include <linux/bcma/bcma.h>
-#endif
-
-MODULE_AUTHOR("Jo-Philipp Wich (jo@mein.io)");
-MODULE_DESCRIPTION("Broadcom WL SSB/BCMA compatibility layer");
-MODULE_LICENSE("GPL");
-
-static wl_glue_attach_cb_t attach_cb = NULL;
-static wl_glue_remove_cb_t remove_cb = NULL;
-static enum wl_glue_bus_type active_bus_type = WL_GLUE_BUS_TYPE_UNSPEC;
-static int wl_glue_attached = 0;
-
-
-#ifdef CONFIG_SSB
-static int wl_glue_ssb_probe(struct ssb_device *dev, const struct ssb_device_id *id)
-{
-	void *mmio;
-	void *wldev;
-
-	if (!attach_cb)
-	{
-		pr_err("No attach callback registered\n");
-		return -ENOSYS;
-	}
-
-	if (dev->bus->bustype != SSB_BUSTYPE_SSB)
-	{
-		pr_err("Attaching to SSB behind PCI is not supported. Please remove the b43 ssb bridge\n");
-		return -EINVAL;
-	}
-
-	mmio = (void *) 0x18000000 + dev->core_index * 0x1000;
-	wldev = attach_cb(id->vendor, id->coreid, (ulong)mmio, dev, dev->irq);
-
-	if (!wldev)
-	{
-		pr_err("The attach callback failed, SSB probe aborted\n");
-		return -ENODEV;
-	}
-
-	ssb_set_drvdata(dev, wldev);
-	return 0;
-}
-
-static void wl_glue_ssb_remove(struct ssb_device *dev)
-{
-	void *wldev = ssb_get_drvdata(dev);
-
-	if (remove_cb)
-		remove_cb(wldev);
-
-	ssb_set_drvdata(dev, NULL);
-}
-
-static const struct ssb_device_id wl_glue_ssb_tbl[] = {
-	SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, SSB_ANY_REV),
-	{},
-};
-
-static struct ssb_driver wl_glue_ssb_driver = {
-	.name     = KBUILD_MODNAME,
-	.id_table = wl_glue_ssb_tbl,
-	.probe    = wl_glue_ssb_probe,
-	.remove   = wl_glue_ssb_remove,
-};
-#endif /* CONFIG_SSB */
-
-#ifdef CONFIG_BCMA
-static int wl_glue_bcma_probe(struct bcma_device *dev)
-{
-	void *wldev;
-
-	if (!attach_cb)
-	{
-		pr_err("No attach callback registered\n");
-		return -ENOSYS;
-	}
-
-	if (dev->bus->hosttype != BCMA_HOSTTYPE_SOC)
-	{
-		pr_err("Unsupported BCMA bus type %d\n", dev->bus->hosttype);
-		return -EINVAL;
-	}
-
-	/*
-	 * NB:
-	 * 0x18000000 = BCMA_ADDR_BASE
-	 * 0x1000     = BCMA_CORE_SIZE
-	 */
-
-	wldev = attach_cb(dev->id.manuf, dev->id.id, (ulong)dev->addr, dev, dev->irq);
-
-	if (!wldev)
-	{
-		pr_err("The attach callback failed, BCMA probe aborted\n");
-		return -ENODEV;
-	}
-
-	bcma_set_drvdata(dev, wldev);
-	return 0;
-}
-
-static void wl_glue_bcma_remove(struct bcma_device *dev)
-{
-	void *wldev = bcma_get_drvdata(dev);
-
-	if (remove_cb)
-		remove_cb(wldev);
-
-	bcma_set_drvdata(dev, NULL);
-}
-
-static const struct bcma_device_id wl_glue_bcma_tbl[] = {
-	BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, BCMA_ANY_REV, BCMA_ANY_CLASS),
-	{},
-};
-
-static struct bcma_driver wl_glue_bcma_driver = {
-	.name     = KBUILD_MODNAME,
-	.id_table = wl_glue_bcma_tbl,
-	.probe    = wl_glue_bcma_probe,
-	.remove   = wl_glue_bcma_remove,
-};
-#endif /* CONFIG_BCMA */
-
-
-void wl_glue_set_attach_callback(wl_glue_attach_cb_t cb)
-{
-	attach_cb = cb;
-}
-EXPORT_SYMBOL(wl_glue_set_attach_callback);
-
-void wl_glue_set_remove_callback(wl_glue_remove_cb_t cb)
-{
-	remove_cb = cb;
-}
-EXPORT_SYMBOL(wl_glue_set_remove_callback);
-
-int wl_glue_register(void)
-{
-	int err;
-
-	switch(active_bus_type)
-	{
-#ifdef CONFIG_SSB
-	case WL_GLUE_BUS_TYPE_SSB:
-		err = ssb_driver_register(&wl_glue_ssb_driver);
-		break;
-#endif /* CONFIG_SSB */
-
-#ifdef CONFIG_BCMA
-	case WL_GLUE_BUS_TYPE_BCMA:
-		err = bcma_driver_register(&wl_glue_bcma_driver);
-		break;
-#endif /* CONFIG_BCMA */
-
-	default:
-		pr_err("Not attaching through glue driver due to unsupported bus\n");
-		err = -ENOSYS;
-		break;
-	}
-
-	if (!err)
-	{
-		pr_info("SSB/BCMA glue driver successfully attached\n");
-		wl_glue_attached = 1;
-	}
-
-	return err;
-}
-EXPORT_SYMBOL(wl_glue_register);
-
-int wl_glue_unregister(void)
-{
-	int err;
-
-	if (!wl_glue_attached)
-		return -ENOSYS;
-
-	switch (active_bus_type)
-	{
-#ifdef CONFIG_SSB
-	case WL_GLUE_BUS_TYPE_SSB:
-		ssb_driver_unregister(&wl_glue_ssb_driver);
-		err = 0;
-		break;
-#endif /* CONFIG_SSB */
-
-#ifdef CONFIG_BCMA
-	case WL_GLUE_BUS_TYPE_BCMA:
-		bcma_driver_unregister(&wl_glue_bcma_driver);
-		err = 0;
-		break;
-#endif /* CONFIG_BCMA */
-
-	default:
-		pr_err("Not removing glue driver due to unsupported bus\n");
-		err = -ENOSYS;
-		break;
-	}
-
-	if (!err)
-	{
-		pr_info("SSB/BCMA glue driver successfully detached\n");
-		wl_glue_attached = 0;
-	}
-
-	return err;
-}
-EXPORT_SYMBOL(wl_glue_unregister);
-
-struct device * wl_glue_get_dmadev(void *dev)
-{
-	struct device *dma_dev;
-
-	switch (active_bus_type)
-	{
-#ifdef CONFIG_SSB
-	case WL_GLUE_BUS_TYPE_SSB:
-		dma_dev = ((struct ssb_device *)dev)->dma_dev;
-		break;
-#endif /* CONFIG_SSB */
-
-#ifdef CONFIG_BCMA
-	case WL_GLUE_BUS_TYPE_BCMA:
-		dma_dev = ((struct bcma_device *)dev)->dma_dev;
-		break;
-#endif /* CONFIG_BCMA */
-
-	default:
-		BUG();
-		dma_dev = NULL;
-		break;
-	}
-
-	return dma_dev;
-}
-EXPORT_SYMBOL(wl_glue_get_dmadev);
-
-
-static int __init wl_glue_init(void)
-{
-#ifdef CONFIG_BCM47XX
-	/*
-	 * BCM47xx currently supports either SSB or BCMA bus,
-	 * determine the used one from the info set by the
-	 * platform setup code.
-	 */
-	switch (bcm47xx_bus_type)
-	{
-#ifdef CONFIG_BCM47XX_SSB
-	case BCM47XX_BUS_TYPE_SSB:
-		active_bus_type = WL_GLUE_BUS_TYPE_SSB;
-		break;
-#endif /* CONFIG_BCM47XX_SSB */
-
-#ifdef CONFIG_BCM47XX_BCMA
-	case BCM47XX_BUS_TYPE_BCMA:
-		active_bus_type = WL_GLUE_BUS_TYPE_BCMA;
-		break;
-#endif /* CONFIG_BCM47XX_BCMA */
-	}
-#endif /* CONFIG_BCM47XX */
-
-#ifdef CONFIG_BCM63XX
-#ifdef CONFIG_SSB
-	/*
-	 * BCM63xx currently only uses SSB, so assume that.
-	 */
-	active_bus_type = WL_GLUE_BUS_TYPE_SSB;
-#endif /* CONFIG_SSB */
-#endif /* CONFIG_BCM63XX */
-
-	/* do not fail here, let wl_glue_register() return -ENOSYS later */
-	if (active_bus_type == WL_GLUE_BUS_TYPE_UNSPEC)
-		pr_err("Unable to determine used system bus type\n");
-
-	return 0;
-}
-
-static void __exit wl_glue_exit(void)
-{
-	if (wl_glue_attached)
-	{
-		if (wl_glue_unregister())
-			pr_err("Failed to unregister glue driver\n");
-
-		wl_glue_attached = 0;
-	}
-
-	return;
-}
-
-module_init(wl_glue_init);
-module_exit(wl_glue_exit);
diff --git a/package/kernel/broadcom-wl/src/glue/wl_glue.h b/package/kernel/broadcom-wl/src/glue/wl_glue.h
deleted file mode 100644
index 49610ab90938be..00000000000000
--- a/package/kernel/broadcom-wl/src/glue/wl_glue.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * wl_glue.h: Broadcom WL support module providing a unified SSB/BCMA handling.
- * Copyright (C) 2011 Jo-Philipp Wich <jo@mein.io>
- */
-
-#include <linux/types.h>
-
-typedef void * (*wl_glue_attach_cb_t)(u16, u16, ulong, void *, u32);
-typedef void (*wl_glue_remove_cb_t)(void *);
-
-enum wl_glue_bus_type {
-	WL_GLUE_BUS_TYPE_UNSPEC,
-	WL_GLUE_BUS_TYPE_SSB,
-	WL_GLUE_BUS_TYPE_BCMA
-};
-
-extern void wl_glue_set_attach_callback(wl_glue_attach_cb_t cb);
-extern void wl_glue_set_remove_callback(wl_glue_remove_cb_t cb);
-extern int wl_glue_register(void);
-extern int wl_glue_unregister(void);
-extern struct device * wl_glue_get_dmadev(void *);
-
diff --git a/package/kernel/broadcom-wl/src/wlc.c b/package/kernel/broadcom-wl/src/wlc.c
deleted file mode 100644
index 46ccf94bffd1e0..00000000000000
--- a/package/kernel/broadcom-wl/src/wlc.c
+++ /dev/null
@@ -1,1181 +0,0 @@
-/*
- * wlc - Broadcom Wireless Driver Control Utility
- *
- * Copyright (C) 2006 Felix Fietkau <nbd@nbd.name>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <sys/types.h>
-#include <sys/stat.h>
-#include <unistd.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <fcntl.h>
-#include <glob.h>
-#include <ctype.h>
-
-#include <typedefs.h>
-#include <wlutils.h>
-#include <proto/802.11.h>
-
-#define VERSION "0.1"
-#define BUFSIZE 8192
-#define PTABLE_MAGIC 0xbadc0ded
-#define PTABLE_SLT1 1
-#define PTABLE_SLT2 2
-#define PTABLE_ACKW 3
-#define PTABLE_ADHM 4
-#define PTABLE_END 0xffffffff
-
-/* 
- * Copy each token in wordlist delimited by space into word 
- * Taken from Broadcom shutils.h
- */
-#define foreach(word, wordlist, next) \
-	for (next = &wordlist[strspn(wordlist, " ")], \
-		 strncpy(word, next, sizeof(word)), \
-		 word[strcspn(word, " ")] = '\0', \
-		 word[sizeof(word) - 1] = '\0', \
-		 next = strchr(next, ' '); \
-		 strlen(word); \
-		 next = next ? &next[strspn(next, " ")] : "", \
-		 strncpy(word, next, sizeof(word)), \
-		 word[strcspn(word, " ")] = '\0', \
-		 word[sizeof(word) - 1] = '\0', \
-		 next = strchr(next, ' '))
-
-static char wlbuf[8192];
-static char interface[16] = "wl0";
-static unsigned long kmem_offset = 0;
-static int vif = 0, debug = 1, fromstdin = 0;
-
-typedef enum {
-	NONE =   0x00,
-
-	/* types */
-	PARAM_TYPE =    0x00f,
-	INT =    0x001,
-	STRING = 0x002,
-	MAC =    0x003,
-
-	/* options */
-	PARAM_OPTIONS = 0x0f0,
-	NOARG =  0x010,
-
-	/* modes */
-	PARAM_MODE =    0xf00,
-	GET =    0x100,
-	SET =    0x200,
-} wlc_param;
-
-struct wlc_call {
-	const char *name;
-	wlc_param param;
-	int (*handler)(wlc_param param, void *data, void *value);
-	union {
-		int num;
-		char *str;
-		void *ptr;
-	} data;
-	const char *desc;
-};
-
-/* can't use the system include because of the stupid broadcom header files */
-extern struct ether_addr *ether_aton(const char *asc);
-static inline int my_ether_ntoa(unsigned char *ea, char *buf)
-{
-	return sprintf(buf, "%02x:%02x:%02x:%02x:%02x:%02x",
-		ea[0], ea[1], ea[2], ea[3], ea[4], ea[5]);
-}
-
-static int wlc_ioctl(wlc_param param, void *data, void *value)
-{
-	unsigned int *var = ((unsigned int *) data);
-	unsigned int ioc = *var;
-
-	if (param & NOARG) {
-		return wl_ioctl(interface, ioc, NULL, 0);
-	}
-	switch(param & PARAM_TYPE) {
-		case MAC:
-			return wl_ioctl(interface, ((param & SET) ? (ioc) : (ioc >> 16)) & 0xffff, value, 6);
-		case INT:
-			return wl_ioctl(interface, ((param & SET) ? (ioc) : (ioc >> 16)) & 0xffff, value, sizeof(int));
-		case STRING:
-			return wl_ioctl(interface, ((param & SET) ? (ioc) : (ioc >> 16)) & 0xffff, value, BUFSIZE);
-	}
-	return 0;
-}
-
-static int wlc_iovar(wlc_param param, void *data, void *value)
-{
-	int *val = (int *) value;
-	char *iov = *((char **) data);
-	int ret = 0;
-	
-	if (param & SET) {
-		switch(param & PARAM_TYPE) {
-			case INT:
-				ret = wl_iovar_setint(interface, iov, *val);
-				break;
-			case MAC:
-				ret = wl_iovar_set(interface, iov, value, 6);
-				break;
-		}
-	}
-	if (param & GET) {
-		switch(param & PARAM_TYPE) {
-			case INT:
-				ret = wl_iovar_get(interface, iov, val, sizeof(int));
-				break;
-			case MAC:
-				ret = wl_iovar_get(interface, iov, value, 6);
-				break;
-		}
-	}
-
-	return ret;
-}
-
-static int wlc_bssiovar(wlc_param param, void *data, void *value)
-{
-	int *val = (int *) value;
-	char *iov = *((char **) data);
-	int ret = 0;
-	
-	if (param & SET) {
-		switch(param & PARAM_TYPE) {
-			case INT:
-				ret = wl_bssiovar_setint(interface, iov, vif, *val);
-		}
-	}
-	if (param & GET) {
-		switch(param & PARAM_TYPE) {
-			case INT:
-				ret = wl_bssiovar_get(interface, iov, vif, val, sizeof(int));
-		}
-	}
-
-	return ret;
-}
-
-static int wlc_vif_enabled(wlc_param param, void *data, void *value)
-{
-	int *val = (int *) value;
-	int buf[3];
-	int ret = 0;
-	
-	sprintf((char *) buf, "bss");
-	buf[1] = vif;
-	if (param & SET) {
-		buf[2] = (*val ? 1 : 0);
-		ret = wl_ioctl(interface, WLC_SET_VAR, buf, sizeof(buf));
-	} else if (param & GET) {
-		ret = wl_ioctl(interface, WLC_GET_VAR, buf, sizeof(buf));
-		*val = buf[0];
-	}
-
-	return ret;
-}
-
-static int wlc_ssid(wlc_param param, void *data, void *value)
-{
-	int ret = -1, ret2 = -1;
-	char *dest = (char *) value;
-	wlc_ssid_t ssid;
-	
-	if ((param & PARAM_MODE) == GET) {
-		ret = wl_bssiovar_get(interface, "ssid", vif, &ssid, sizeof(ssid));
-
-		if (ret)
-			/* if we can't get the ssid through the bssiovar, try WLC_GET_SSID */
-			ret = wl_ioctl(interface, WLC_GET_SSID, &ssid, sizeof(ssid));
-		
-		if (!ret) {
-			memcpy(dest, ssid.SSID, ssid.SSID_len);
-			dest[ssid.SSID_len] = 0;
-		}
-	} else if ((param & PARAM_MODE) == SET) {
-		strncpy(ssid.SSID, value, 32);
-		ssid.SSID_len = strlen(value);
-		
-		if (ssid.SSID_len > 32)
-			ssid.SSID_len = 32;
-		
-		if (vif == 0) {
-			/* for the main interface, also try the WLC_SET_SSID call */
-			ret2 = wl_ioctl(interface, WLC_SET_SSID, &ssid, sizeof(ssid));
-		}
-		
-		ret = wl_bssiovar_set(interface, "ssid", vif, &ssid, sizeof(ssid));
-		ret = (!ret2 ? 0 : ret);
-	}
-	
-	return ret;
-}
-
-static int wlc_int(wlc_param param, void *data, void *value)
-{
-	int *var = *((int **) data);
-	int *val = (int *) value;
-
-	if ((param & PARAM_MODE) == SET) {
-		*var = *val;
-	} else if ((param & PARAM_MODE) == GET) {
-		*val = *var;
-	}
-
-	return 0;
-}
-
-static int wlc_flag(wlc_param param, void *data, void *value)
-{
-	int *var = *((int **) data);
-
-	*var = 1;
-
-	return 0;
-}
-
-static int wlc_string(wlc_param param, void *data, void *value)
-{
-	char *var = *((char **) data);
-	
-	if ((param & PARAM_MODE) == GET) {
-		strcpy(value, var);
-	}
-
-	return 0;
-}
-
-static int wlc_afterburner(wlc_param param, void *data, void *value)
-{
-	int *val = (int *) value;
-	int ret = 0;
-
-	if ((param & PARAM_MODE) == GET) {
-		ret = wl_iovar_get(interface, "afterburner", val, sizeof(int));
-	} else {
-		wl_iovar_setint(interface, "wlfeatureflag", (*val ? 3 : 0));
-		ret = wl_iovar_setint(interface, "afterburner", (*val ? 1 : 0));
-		wl_iovar_setint(interface, "afterburner_override", *val);
-	}
-
-	return ret;
-}
-
-static int wlc_maclist(wlc_param param, void *data, void *value)
-{
-	unsigned int *var = ((unsigned int *) data);
-	unsigned int ioc = *var;
-	int limit = (sizeof(wlbuf) - 4) / sizeof(struct ether_addr);
-	struct maclist *list = (struct maclist *) wlbuf;
-	char *str = (char *) value;
-	char astr[30], *p;
-	struct ether_addr *addr;
-	int isset = 0;
-	int ret;
-
-	if ((param & PARAM_MODE) == GET) {
-		list->count = limit;
-		ret = wl_ioctl(interface, (ioc >> 16) & 0xffff, wlbuf, sizeof(wlbuf));
-		
-		if (!ret) 
-			while (list->count) {
-				str += sprintf(str, "%s", ((((char *) value) == str) ? "" : " "));
-				str += my_ether_ntoa((unsigned char *) &list->ea[list->count-- - 1], str);
-			}
-		
-		return ret;
-	} else {
-		while (*str && isspace(*str))
-			*str++;
-		
-		if (*str == '+') {
-			str++;
-
-			list->count = limit;
-			if (wl_ioctl(interface, (ioc >> 16) & 0xffff, wlbuf, sizeof(wlbuf)) == 0)
-				isset = 1;
-
-			while (*str && isspace(*str))
-				str++;
-		}
-		
-		if (!isset)
-			memset(wlbuf, 0, sizeof(wlbuf));
-		
-		foreach(astr, str, p) {
-			if (list->count >= limit)
-				break;
-			
-			if ((addr = ether_aton(astr)) != NULL)
-				memcpy(&list->ea[list->count++], addr, sizeof(struct ether_addr));
-		}
-
-		return wl_ioctl(interface, ioc & 0xffff, wlbuf, sizeof(wlbuf));
-	}
-}
-
-static int wlc_radio(wlc_param param, void *data, void *value)
-{
-	int *val = (int *) value;
-	int ret;
-
-	if ((param & PARAM_MODE) == GET) {
-		ret = wl_ioctl(interface, WLC_GET_RADIO, val, sizeof(int));
-		*val = ((*val & 1) ? 0 : 1);
-	} else {
-		*val = (1 << 16) | (*val ? 0 : 1); 
-		ret = wl_ioctl(interface, WLC_SET_RADIO, val, sizeof(int));
-	}
-
-	return ret;
-}
-
-static int wlc_wsec_key(wlc_param param, void *null, void *value)
-{
-	wl_wsec_key_t wsec_key;
-	unsigned char *index = value;
-	unsigned char *key;
-	unsigned char *data;
-	unsigned char hex[3];
-	
-	if ((param & PARAM_MODE) != SET)
-		return 0;
-
-	memset(&wsec_key, 0, sizeof(wsec_key));
-	if (index[0] == '=') {
-		wsec_key.flags = WL_PRIMARY_KEY;
-		index++;
-	}
-	
-	if ((index[0] < '1') || (index[0] > '4') || (index[1] != ','))
-		return -1;
-	
-	key = index + 2;
-	if (strncmp(key, "d:", 2) == 0) { /* delete key */
-	} else if (strncmp(key, "s:", 2) == 0) { /* ascii key */
-		key += 2;
-		wsec_key.len = strlen(key);
-
-		if ((wsec_key.len != 5) && (wsec_key.len != 13))
-			return -1;
-		
-		strcpy(wsec_key.data, key);
-	} else { /* hex key */
-		wsec_key.len = strlen(key);
-		if ((wsec_key.len != 10) && (wsec_key.len != 26))
-			return -1;
-		
-		wsec_key.len /= 2;
-		data = wsec_key.data;
-		hex[2] = 0;
-		do {
-			hex[0] = *(key++);
-			hex[1] = *(key++);
-			*(data++) = (unsigned char) strtoul(hex, NULL, 16);
-		} while (*key != 0);
-	}
-
-	return wl_bssiovar_set(interface, "wsec_key", vif, &wsec_key, sizeof(wsec_key));
-}
-
-static int wlc_cap(wlc_param param, void *data, void *value)
-{
-	char *iov = *((char **) data);
-
-	if (param & GET)
-		return wl_iovar_get(interface, iov, value, BUFSIZE);
-
-	return -1;
-}
-
-static int wlc_bssmax(wlc_param param, void *data, void *value)
-{
-	int *val = (int *) value;
-	char *iov = *((char **) data);
-	int ret = -1;
-
-	if (param & GET) {
-		ret = wl_iovar_get(interface, iov, wlbuf, BUFSIZE);
-		if (!ret) {
-			if (strstr(wlbuf, "mbss4"))
-				*val = 4;
-			else if (strstr(wlbuf, "mbss16"))
-				*val = 16;
-			else
-				*val = 1;
-		}
-	}
-
-	return ret;
-}
-
-static inline int cw2ecw(int cw)
-{
-	int i;	
-	for (cw++, i = 0; cw; i++) cw >>=1;
-	return i - 1;
-}
-
-static int wlc_wme_ac(wlc_param param, void *data, void *value)
-{
-	char *type = *((char **) data);
-	char *settings = (char *) value;
-	char cmd[100], *p, *val;
-	edcf_acparam_t params[AC_COUNT];
-	int ret;
-	int intval;
-	int cur = -1;
-	char *buf = wlbuf;
-
-	if ((param & PARAM_MODE) != SET)
-		return -1;
-	
-	memset(params, 0, sizeof(params));
-	ret = wl_iovar_get(interface, type, params, sizeof(params));
-	memset(buf, 0, BUFSIZE);
-	strcpy(buf, type);
-	buf += strlen(buf) + 1;
-	
-	foreach(cmd, settings, p) {
-		val = strchr(cmd, '=');
-		if (val == NULL) {
-			if (strcmp(cmd, "be") == 0)
-				cur = AC_BE;
-			else if (strcmp(cmd, "bk") == 0)
-				cur = AC_BK;
-			else if (strcmp(cmd, "vi") == 0)
-				cur = AC_VI;
-			else if (strcmp(cmd, "vo") == 0)
-				cur = AC_VO;
-			else
-				return -1;
-
-			/* just in case */
-			params[cur].ACI = (params[cur].ACI & (0x3 << 5)) | (cur << 5);
-		} else {
-			*(val++) = 0;
-			
-			intval = strtoul(val, NULL, 10);
-			if (strcmp(cmd, "cwmin") == 0)
-				params[cur].ECW = (params[cur].ECW & ~(0xf)) | cw2ecw(intval);
-			else if (strcmp(cmd, "ecwmin") == 0)
-				params[cur].ECW = (params[cur].ECW & ~(0xf)) | (intval & 0xf);
-			else if (strcmp(cmd, "cwmax") == 0)
-				params[cur].ECW = (params[cur].ECW & ~(0xf << 4)) | (cw2ecw(intval) << 4);
-			else if (strcmp(cmd, "ecwmax") == 0)
-				params[cur].ECW = (params[cur].ECW & ~(0xf << 4)) | ((intval & 0xf) << 4);
-			else if (strcmp(cmd, "aifsn") == 0)
-				params[cur].ACI = (params[cur].ACI & ~(0xf)) | (intval & 0xf);
-			else if (strcmp(cmd, "txop") == 0)
-				params[cur].TXOP = intval >> 5;
-			else if (strcmp(cmd, "force") == 0)
-				params[cur].ACI = (params[cur].ACI & ~(1 << 4)) | ((intval) ? (1 << 4) : 0);
-			else return -1;
-			
-			memcpy(buf, &params[cur], sizeof(edcf_acparam_t));
-			wl_ioctl(interface, WLC_SET_VAR, wlbuf, BUFSIZE);
-		}
-	}
-	return ret;
-}
-
-static int wlc_ifname(wlc_param param, void *data, void *value)
-{
-	char *val = (char *) value;
-	int ret = 0;
-	
-	if (param & SET) {
-		if (strlen(val) < 16)
-			strcpy(interface, val);
-		else ret = -1;
-	}
-	if (param & GET) {
-		strcpy(val, interface);
-	}
-
-	return ret;
-}
-
-static int wlc_wdsmac(wlc_param param, void *data, void *value)
-{
-	unsigned char mac[6];
-	int ret = 0;
-	
-	ret = wl_ioctl(interface, WLC_WDS_GET_REMOTE_HWADDR, &mac, 6);
-	if (ret == 0)
-		my_ether_ntoa(mac, value);
-
-	return ret;
-}
-
-static int wlc_pmk(wlc_param param, void *data, void *value)
-{
-	int ret = -1;
-	char *str = (char *) value;
-	wsec_pmk_t pmk;
-	
-	/* driver doesn't support GET */
-
-	if ((param & PARAM_MODE) == SET) {
-		strncpy(pmk.key, str, WSEC_MAX_PSK_LEN);
-		pmk.key_len = strlen(str);
-
-		if (pmk.key_len > WSEC_MAX_PSK_LEN)
-			pmk.key_len = WSEC_MAX_PSK_LEN;
-
-		pmk.flags = WSEC_PASSPHRASE;
-
-		ret = wl_ioctl(interface, WLC_SET_WSEC_PMK, &pmk, sizeof(pmk));
-	}
-	
-	return ret;
-}
-
-static const struct wlc_call wlc_calls[] = {
-	{
-		.name = "version",
-		.param = STRING|NOARG,
-		.handler = wlc_string,
-		.data.str = VERSION,
-		.desc = "Version of this program"
-	},
-	{
-		.name = "debug",
-		.param = INT,
-		.handler = wlc_int,
-		.data.ptr = &debug,
-		.desc = "wlc debug level"
-	},
-	{
-		.name = "stdin",
-		.param = NOARG,
-		.handler = wlc_flag,
-		.data.ptr = &fromstdin,
-		.desc = "Accept input from stdin"
-	},
-	{
-		.name = "ifname",
-		.param = STRING,
-		.handler = wlc_ifname,
-		.desc = "interface to send commands to"
-	},
-	{
-		.name = "up",
-		.param = NOARG,
-		.handler = wlc_ioctl,
-		.data.num = WLC_UP,
-		.desc = "Bring the interface up"
-	},
-	{
-		.name = "down",
-		.param = NOARG,
-		.handler = wlc_ioctl,
-		.data.num = WLC_DOWN,
-		.desc = "Bring the interface down"
-	},
-	{
-		.name = "radio",
-		.param = INT,
-		.handler = wlc_radio,
-		.desc = "Radio enabled flag"
-	},
-	{
-		.name = "ap",
-		.param = INT,
-		.handler = wlc_ioctl,
-		.data.num = ((WLC_GET_AP << 16) | WLC_SET_AP),
-		.desc = "Access Point mode"
-	},
-	{
-		.name = "mssid",
-		.param = INT,
-		.handler = wlc_iovar,
-		.data.str = "mbss",
-		.desc = "Multi-ssid mode"
-	},
-	{
-		.name = "apsta",
-		.param = INT,
-		.handler = wlc_iovar,
-		.data.str = "apsta",
-		.desc = "AP+STA mode"
-	},
-	{
-		.name = "infra",
-		.param = INT,
-		.handler = wlc_ioctl,
-		.data.num = ((WLC_GET_INFRA << 16) | WLC_SET_INFRA),
-		.desc = "Infrastructure mode"
-	},
-	{
-		.name = "wet",
-		.param = INT,
-		.handler = wlc_ioctl,
-		.data.num = ((WLC_GET_WET << 16) | WLC_SET_WET),
-		.desc = "Wireless repeater mode",
-	},
-	{
-		.name = "statimeout",
-		.param = INT,
-		.handler = wlc_iovar,
-		.data.str = "sta_retry_time",
-		.desc = "STA connection timeout"
-	},
-	{
-		.name = "country",
-		.param = STRING,
-		.handler = wlc_ioctl,
-		.data.num = ((WLC_GET_COUNTRY << 16) | WLC_SET_COUNTRY),
-		.desc = "Country code"
-	},
-	{
-		.name = "channel",
-		.param = INT,
-		.handler = wlc_ioctl,
-		.data.num = ((WLC_GET_CHANNEL << 16) | WLC_SET_CHANNEL),
-		.desc = "Channel",
-	},
-	{
-		.name = "vlan_mode",
-		.param = INT,
-		.handler = wlc_bssiovar,
-		.data.str = "vlan_mode",
-		.desc = "Parse 802.1Q tags",
-	},
-	{
-		.name = "vif",
-		.param = INT,
-		.handler = wlc_int,
-		.data.ptr = &vif,
-		.desc = "Current vif index"
-	},
-	{
-		.name = "enabled",
-		.param = INT,
-		.handler = wlc_vif_enabled,
-		.desc = "vif enabled flag"
-	},
-	{
-		.name = "ssid",
-		.param = STRING,
-		.handler = wlc_ssid,
-		.desc = "Interface ESSID"
-	},
-	{
-		.name = "closed",
-		.param = INT,
-		.handler = wlc_bssiovar,
-		.data.str = "closednet",
-		.desc = "Hidden ESSID flag"
-	},
-	{
-		.name = "wsec",
-		.param = INT,
-		.handler = wlc_bssiovar,
-		.data.str = "wsec",
-		.desc = "Security mode flags"
-	},
-	{
-		.name = "wepkey",
-		.param = STRING,
-		.handler = wlc_wsec_key,
-		.desc = "Set/Remove WEP keys"
-	},
-	{
-		.name = "wepauth",
-		.param = INT,
-		.handler = wlc_ioctl,
-		.data.num = ((WLC_GET_AUTH << 16) | WLC_SET_AUTH),
-		.desc = "WEP authentication type. 0 = OpenSystem, 1 = SharedKey"
-	},
-	{
-		.name = "wsec_restrict",
-		.param = INT,
-		.handler = wlc_bssiovar,
-		.data.str = "wsec_restrict",
-		.desc = "Drop unencrypted traffic"
-	},
-	{
-		.name = "eap_restrict",
-		.param = INT,
-		.handler = wlc_bssiovar,
-		.data.str = "eap_restrict",
-		.desc = "Only allow 802.1X traffic until 802.1X authorized"
-	},
-	{
-		.name = "wpa_auth",
-		.param = INT,
-		.handler = wlc_bssiovar,
-		.data.str = "wpa_auth",
-		.desc = "WPA authentication modes"
-	},
-	{
-		.name = "ap_isolate",
-		.param = INT,
-		.handler = wlc_bssiovar,
-		.data.str = "ap_isolate",
-		.desc = "Isolate connected clients"
-	},
-	{
-		.name = "supplicant",
-		.param = INT,
-		.handler = wlc_iovar,
-		.data.str = "sup_wpa",
-		.desc = "Built-in WPA supplicant"
-	},
-	{
-		.name = "passphrase",
-		.param = STRING,
-		.handler = wlc_pmk,
-		.desc = "Passphrase for built-in WPA supplicant",
-	},
-	{
-		.name = "maxassoc",
-		.param = INT,
-		.handler = wlc_iovar,
-		.data.str = "maxassoc",
-		.desc = "Max. number of associated clients",
-	},
-	{
-		.name = "wme",
-		.param = INT,
-		.handler = wlc_iovar,
-		.data.str = "wme",
-		.desc = "WME enabled"
-	},
-	{
-		.name = "wme_ac_ap",
-		.param = STRING,
-		.handler = wlc_wme_ac,
-		.data.str = "wme_ac_ap",
-		.desc = "Set WME AC options for AP mode",
-	},
-	{
-		.name = "wme_ac_sta",
-		.param = STRING,
-		.handler = wlc_wme_ac,
-		.data.str = "wme_ac_sta",
-		.desc = "Set WME AC options for STA mode",
-	},
-	{
-		.name = "wme_noack",
-		.param = INT,
-		.handler = wlc_iovar,
-		.data.str = "wme_noack",
-		.desc = "WME ACK disable request",
-	},
-	{
-		.name = "802.11d",
-		.param = INT,
-		.handler = wlc_ioctl,
-		.data.num = ((WLC_GET_REGULATORY << 16) | WLC_SET_REGULATORY),
-		.desc = "Enable/disable 802.11d regulatory management",
-	},
-	{
-		.name = "802.11h",
-		.param = INT,
-		.handler = wlc_ioctl,
-		.data.num = ((WLC_GET_SPECT_MANAGMENT << 16) | WLC_SET_SPECT_MANAGMENT),
-		.desc = "Enable/disable 802.11h spectrum management",
-	},
-	{
-		.name = "fragthresh",
-		.param = INT,
-		.handler = wlc_iovar,
-		.data.str = "fragthresh",
-		.desc = "Fragmentation threshold",
-	},
-	{
-		.name = "rtsthresh",
-		.param = INT,
-		.handler = wlc_iovar,
-		.data.str = "rtsthresh",
-		.desc = "RTS threshold"
-	},
-	{
-		.name = "slottime",
-		.param = INT,
-		.handler = wlc_iovar,
-		.data.str = "acktiming",
-		.desc = "Slot time"
-	},
-	{
-		.name = "rxant",
-		.param = INT,
-		.handler = wlc_ioctl,
-		.data.num = ((WLC_GET_ANTDIV << 16) | WLC_SET_ANTDIV),
-		.desc = "Rx antenna selection"
-	},
-	{
-		.name = "txant",
-		.param = INT,
-		.handler = wlc_ioctl,
-		.data.num = ((WLC_GET_TXANT << 16) | WLC_SET_TXANT),
-		.desc = "Tx antenna selection"
-	},
-	{
-		.name = "dtim",
-		.param = INT,
-		.handler = wlc_ioctl,
-		.data.num = ((WLC_GET_DTIMPRD << 16) | WLC_SET_DTIMPRD),
-		.desc = "DTIM period",
-	},
-	{
-		.name = "bcn",
-		.param = INT,
-		.handler = wlc_ioctl,
-		.data.num = ((WLC_GET_BCNPRD << 16) | WLC_SET_BCNPRD),
-		.desc = "Beacon interval"
-	},
-	{
-		.name = "frameburst",
-		.param = INT,
-		.handler = wlc_ioctl,
-		.data.num = ((WLC_GET_FAKEFRAG << 16) | WLC_SET_FAKEFRAG),
-		.desc = "Framebursting"
-	},
-	{
-		.name = "monitor",
-		.param = INT,
-		.handler = wlc_ioctl,
-		.data.num = ((WLC_GET_MONITOR << 16) | WLC_SET_MONITOR),
-		.desc = "Monitor mode"
-	},
-	{
-		.name = "passive_scan",
-		.param = INT,
-		.handler = wlc_ioctl,
-		.data.num = ((WLC_GET_PASSIVE_SCAN << 16) | WLC_SET_PASSIVE_SCAN),
-		.desc = "Passive scan mode"
-	},
-	{
-		.name = "macfilter",
-		.param = INT,
-		.handler = wlc_ioctl,
-		.data.num = ((WLC_GET_MACMODE << 16) | WLC_SET_MACMODE),
-		.desc = "MAC filter mode (0:disabled, 1:deny, 2:allow)"
-	},
-	{
-		.name = "maclist",
-		.param = STRING,
-		.data.num = ((WLC_GET_MACLIST << 16) | WLC_SET_MACLIST),
-		.handler = wlc_maclist,
-		.desc = "MAC filter list"
-	},
-	{
-		.name = "autowds",
-		.param = INT,
-		.handler = wlc_ioctl,
-		.data.num = ((WLC_GET_LAZYWDS << 16) | WLC_SET_LAZYWDS),
-		.desc = "Automatic WDS"
-	},
-	{
-		.name = "wds",
-		.param = STRING,
-		.data.num = ((WLC_GET_WDSLIST << 16) | WLC_SET_WDSLIST),
-		.handler = wlc_maclist,
-		.desc = "WDS connection list"
-	},
-	{
-		.name = "wdstimeout",
-		.param = INT,
-		.handler = wlc_iovar,
-		.data.str = "wdstimeout",
-		.desc = "WDS link detection timeout"
-	},
-	{
-		.name = "wdsmac",
-		.param = STRING|NOARG,
-		.handler = wlc_wdsmac,
-		.desc = "MAC of the remote WDS endpoint (only with wds0.* interfaces)"
-	},
-	{
-		.name = "afterburner",
-		.param = INT,
-		.handler = wlc_afterburner,
-		.desc = "Broadcom Afterburner"
-	},
-	{
-		.name = "ibss_merge",
-		.param = INT,
-		.handler = wlc_iovar,
-		.data.str = "ibss_coalesce_allowed",
-		.desc = "Allow IBSS merges"
-	},
-	{
-		.name = "bssid",
-		.param = MAC,
-		.handler = wlc_ioctl,
-		.data.num = ((WLC_GET_BSSID << 16) | WLC_SET_BSSID),
-		.desc = "BSSID"
-	},
-	{
-		.name = "cur_etheraddr",
-		.param = MAC,
-		.handler = wlc_iovar,
-		.data.str = "cur_etheraddr",
-		.desc = "Current MAC Address"
-	},
-	{
-		.name = "default_bssid",
-		.param = MAC,
-		.handler = wlc_iovar,
-		.data.str = "perm_etheraddr",
-		.desc = "Default BSSID (read-only)"
-	},
-	{
-		.name = "assoclist",
-		.param = STRING,
-		.data.num = (WLC_GET_ASSOCLIST << 16),
-		.handler = wlc_maclist,
-		.desc = "MACs of associated stations"
-	},
-	{
-		.name = "gmode",
-		.param = INT,
-		.data.num = ((WLC_GET_GMODE << 16) | WLC_SET_GMODE),
-		.handler = wlc_ioctl,
-		.desc = "G Mode"
-	},
-	{
-		.name = "phytype",
-		.param = INT,
-		.data.num = (WLC_GET_PHYTYPE << 16),
-		.handler = wlc_ioctl,
-		.desc = "PHY Type (read-only)"
-	},
-	{
-		.name = "nmode",
-		.param = INT,
-		.handler = wlc_iovar,
-		.data.str = "nmode",
-		.desc = "N Mode"
-	},
-	{
-		.name = "nreqd",
-		.param = INT,
-		.handler = wlc_iovar,
-		.data.str = "nreqd",
-		.desc = "N Mode required"
-	},
-	{
-		.name = "chanspec",
-		.param = INT,
-		.handler = wlc_iovar,
-		.data.str = "chanspec",
-		.desc = "Channel Spec (See bcmwifi.h)"
-	},
-	{
-		.name = "band",
-		.param = INT,
-		.data.num = ((WLC_GET_BAND << 16) | WLC_SET_BAND),
-		.handler = wlc_ioctl,
-		.desc = "Band (0=auto, 1=5Ghz, 2=2.4GHz)"
-	},
-	{
-		.name = "cap",
-		.param = STRING|NOARG,
-		.handler = wlc_cap,
-		.data.str = "cap",
-		.desc = "Capabilities"
-	},
-	{
-		.name = "bssmax",
-		.param = INT|NOARG,
-		.handler = wlc_bssmax,
-		.data.str = "cap",
-		.desc = "Number of VIF's supported"
-	},
-	{
-		.name = "leddc",
-		.param = INT,
-		.handler = wlc_iovar,
-		.data.str = "leddc",
-		.desc = "LED Duty Cycle"
-	},
-	
-};
-#define wlc_calls_size (sizeof(wlc_calls) / sizeof(struct wlc_call))
-
-static void usage(char *cmd)
-{
-	int i;
-	fprintf(stderr, "Usage: %s <command> [<argument> ...]\n"
-					"\n"
-					"Available commands:\n", cmd);
-	for (i = 0; i < wlc_calls_size; i++) {
-		fprintf(stderr, "\t%-16s\t%s\n", wlc_calls[i].name ?: "", wlc_calls[i].desc ?: "");
-	}
-	fprintf(stderr, "\n");
-	exit(1);
-}
-
-static int do_command(const struct wlc_call *cmd, char *arg)
-{
-	static char buf[BUFSIZE];
-	int set;
-	int ret = 0;
-	char *format, *end;
-	int intval;
-	void *ptr = (void *) buf;
-
-	if (debug >= 10) {
-		fprintf(stderr, "do_command %-16s\t'%s'\n", cmd->name, arg);
-	}
-	
-	if ((arg == NULL) && ((cmd->param & PARAM_TYPE) != NONE)) {
-		set = 0;
-		ret = cmd->handler(cmd->param | GET, (void *) &cmd->data, (void *) buf);
-		if (ret == 0) {
-			switch(cmd->param & PARAM_TYPE) {
-				case INT:
-					intval = *((int *) buf);
-					
-					if (intval > 65535)
-						format = "0x%08x\n";
-					else if (intval > 255)
-						format = "0x%04x\n";
-					else
-						format = "%d\n";
-					
-					fprintf(stdout, format, intval);
-					break;
-				case STRING:
-					fprintf(stdout, "%s\n", buf);
-					break;
-				case MAC:
-					my_ether_ntoa(buf, buf + 6);
-					fprintf(stdout, "%s\n", buf + 6);
-					break;
-			}
-		}
-	} else { /* SET */
-		set = 1;
-		switch(cmd->param & PARAM_TYPE) {
-			case INT:
-				intval = strtoul(arg, &end, 0);
-				if (end && !(*end)) {
-					memcpy(buf, &intval, sizeof(intval));
-				} else {
-					fprintf(stderr, "%s: Invalid argument\n", cmd->name);
-					return -1;
-				}
-				break;
-			case STRING:
-				strncpy(buf, arg, BUFSIZE);
-				buf[BUFSIZE - 1] = 0;
-				break;
-			case MAC:
-				ptr = ether_aton(arg);
-				if (!ptr) {
-					fprintf(stderr, "%s: Invalid mac address '%s'\n", cmd->name, arg);
-					return -1;
-				}
-				break;
-		}
-
-		ret = cmd->handler(cmd->param | SET, (void *) &cmd->data, ptr);
-	}
-	
-	if ((debug > 0) && (ret != 0)) 
-		fprintf(stderr, "Command '%s %s' failed: %d\n", (set == 1 ? "set" : "get"), cmd->name, ret);
-	
-	return ret;
-}
-
-static struct wlc_call *find_cmd(char *name)
-{
-	int found = 0, i = 0;
-
-	while (!found && (i < wlc_calls_size)) {
-		if (strcmp(name, wlc_calls[i].name) == 0)
-			found = 1;
-		else
-			i++;
-	}
-
-	return (struct wlc_call *) (found ? &wlc_calls[i] : NULL);
-}
-
-int main(int argc, char **argv)
-{
-	static char buf[BUFSIZE];
-	char *s, *s2;
-	char *cmd = argv[0];
-	struct wlc_call *call;
-	int ret = 0;
-
-	if (argc < 2)
-		usage(argv[0]);
-
-	for(interface[2] = '0'; (interface[2] < '3') && (wl_probe(interface) != 0); interface[2]++);
-	if (interface[2] == '3') {
-		fprintf(stderr, "No Broadcom wl interface found!\n");
-		return -1;
-	}
-
-	argv++;
-	argc--;
-	while ((argc > 0) && (argv[0] != NULL)) {
-		if ((call = find_cmd(argv[0])) == NULL) {
-			fprintf(stderr, "Invalid command: %s\n\n", argv[0]);
-			usage(cmd);
-		}
-		if ((argc > 1) && (!(call->param & NOARG))) {
-			ret = do_command(call, argv[1]);
-			argv += 2;
-			argc -= 2;
-		} else {
-			ret = do_command(call, NULL);
-			argv++;
-			argc--;
-		}
-	}
-
-	while (fromstdin && !feof(stdin)) {
-		*buf = 0;
-		fgets(buf, BUFSIZE - 1, stdin);
-		
-		if (*buf == 0)
-			continue;
-		
-		if ((s = strchr(buf, '\r')) != NULL)
-			*s = 0;
-		if ((s = strchr(buf, '\n')) != NULL)
-			*s = 0;
-
-		s = buf;
-		while (isspace(*s))
-			s++;
-
-		if (!*s)
-			continue;
-	
-		if ((s2 = strchr(s, ' ')) != NULL)
-			*(s2++) = 0;
-		
-		while (s2 && isspace(*s2))
-			s2++;
-		
-		if ((call = find_cmd(s)) == NULL) {
-			fprintf(stderr, "Invalid command: %s\n", s);
-			ret = -1;
-		} else
-			ret = do_command(call, ((call->param & NOARG) ? NULL : s2));
-	}
-
-	return ret;
-}
diff --git a/package/kernel/gpio-button-hotplug/Makefile b/package/kernel/gpio-button-hotplug/Makefile
index 7ca6195a03ecff..04cbb69ada9001 100644
--- a/package/kernel/gpio-button-hotplug/Makefile
+++ b/package/kernel/gpio-button-hotplug/Makefile
@@ -15,7 +15,7 @@ PKG_LICENSE:=GPL-2.0
 include $(INCLUDE_DIR)/package.mk
 
 define KernelPackage/gpio-button-hotplug
-  SUBMENU:=Other modules
+  SUBMENU:=GPIO support
   TITLE:=Simple GPIO Button Hotplug driver
   FILES:=$(PKG_BUILD_DIR)/gpio-button-hotplug.ko
   AUTOLOAD:=$(call AutoLoad,30,gpio-button-hotplug,1)
diff --git a/package/kernel/gpio-nct5104d/Makefile b/package/kernel/gpio-nct5104d/Makefile
index 72b1d58e62ece2..bb6010d2d02537 100644
--- a/package/kernel/gpio-nct5104d/Makefile
+++ b/package/kernel/gpio-nct5104d/Makefile
@@ -17,7 +17,7 @@ PKG_LICENSE:=GPL-2.0
 include $(INCLUDE_DIR)/package.mk
 
 define KernelPackage/gpio-nct5104d
-  SUBMENU:=Other modules
+  SUBMENU:=GPIO support
   TITLE:= GPIO nct5104d support
   DEPENDS:= @GPIO_SUPPORT @TARGET_x86
   FILES:=$(PKG_BUILD_DIR)/gpio-nct5104d.ko
diff --git a/package/kernel/linux/modules/gpio-cascade.mk b/package/kernel/linux/modules/gpio-cascade.mk
deleted file mode 100644
index 3a559f19ef12ae..00000000000000
--- a/package/kernel/linux/modules/gpio-cascade.mk
+++ /dev/null
@@ -1,20 +0,0 @@
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-MENU_TITLE:=GPIO support
-
-define KernelPackage/gpio-cascade
-  SUBMENU:=$(MENU_TITLE)
-  TITLE:=Generic GPIO cascade
-  KCONFIG:=CONFIG_GPIO_CASCADE
-  DEPENDS:=@GPIO_SUPPORT +kmod-mux-core
-  FILES:=$(LINUX_DIR)/drivers/gpio/gpio-cascade.ko
-  AUTOLOAD:=$(call AutoLoad,29,gpio-cascade,1)
-endef
-
-define KernelPackage/gpio-cascade/description
-  Kernel module for Generic GPIO cascade
-endef
-
-$(eval $(call KernelPackage,gpio-cascade))
diff --git a/package/kernel/linux/modules/gpio.mk b/package/kernel/linux/modules/gpio.mk
new file mode 100644
index 00000000000000..511cd3af8ca221
--- /dev/null
+++ b/package/kernel/linux/modules/gpio.mk
@@ -0,0 +1,138 @@
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+GPIO_MENU:=GPIO support
+
+define KernelPackage/gpio-amd-fch
+  SUBMENU:=$(GPIO_MENU)
+  DEPENDS:=@GPIO_SUPPORT @TARGET_x86
+  TITLE:=GPIO support for AMD Fusion Controller Hub (G-series SOCs)
+  KCONFIG:=CONFIG_GPIO_AMD_FCH
+  FILES:=$(LINUX_DIR)/drivers/gpio/gpio-amd-fch.ko
+  AUTOLOAD:=$(call AutoLoad,25,gpio-amd-fch,1)
+endef
+
+define KernelPackage/gpio-amd-fch/description
+  This option enables driver for GPIO on AMDs Fusion Controller Hub,
+  as found on G-series SOCs (eg. GX-412TC)
+endef
+
+$(eval $(call KernelPackage,gpio-amd-fch))
+
+
+define KernelPackage/gpio-beeper
+  SUBMENU:=$(GPIO_MENU)
+  TITLE:=GPIO beeper support
+  DEPENDS:=+kmod-input-core
+  KCONFIG:= \
+	CONFIG_INPUT_MISC=y \
+	CONFIG_INPUT_GPIO_BEEPER
+  FILES:= \
+	$(LINUX_DIR)/drivers/input/misc/gpio-beeper.ko
+  AUTOLOAD:=$(call AutoLoad,50,gpio-beeper)
+endef
+
+define KernelPackage/gpio-beeper/description
+ This enables playing beeps through an GPIO-connected buzzer
+endef
+
+$(eval $(call KernelPackage,gpio-beeper))
+
+
+define KernelPackage/gpio-cascade
+  SUBMENU:=$(GPIO_MENU)
+  TITLE:=Generic GPIO cascade
+  KCONFIG:=CONFIG_GPIO_CASCADE
+  DEPENDS:=@GPIO_SUPPORT +kmod-mux-core
+  FILES:=$(LINUX_DIR)/drivers/gpio/gpio-cascade.ko
+  AUTOLOAD:=$(call AutoLoad,29,gpio-cascade,1)
+endef
+
+define KernelPackage/gpio-cascade/description
+  Kernel module for Generic GPIO cascade
+endef
+
+$(eval $(call KernelPackage,gpio-cascade))
+
+
+define KernelPackage/gpio-f7188x
+  SUBMENU:=$(GPIO_MENU)
+  TITLE:=Fintek F718xx/F818xx GPIO Support
+  DEPENDS:=@GPIO_SUPPORT @TARGET_x86
+  KCONFIG:=CONFIG_GPIO_F7188X
+  FILES:=$(LINUX_DIR)/drivers/gpio/gpio-f7188x.ko
+  AUTOLOAD:=$(call AutoProbe,gpio-f7188x)
+endef
+
+define KernelPackage/gpio-f7188x/description
+  Kernel module for the GPIOs found on many Fintek Super-IO chips.
+endef
+
+$(eval $(call KernelPackage,gpio-f7188x))
+
+
+define KernelPackage/gpio-it87
+  SUBMENU:=$(GPIO_MENU)
+  DEPENDS:=@GPIO_SUPPORT @TARGET_x86
+  TITLE:=GPIO support for IT87xx Super I/O chips
+  KCONFIG:=CONFIG_GPIO_IT87
+  FILES:=$(LINUX_DIR)/drivers/gpio/gpio-it87.ko
+  AUTOLOAD:=$(call AutoLoad,25,gpio-it87,1)
+endef
+
+define KernelPackage/gpio-it87/description
+  This driver is tested with ITE IT8728 and IT8732 Super I/O chips, and
+  supports the IT8761E, IT8613, IT8620E, and IT8628E Super I/O chips as
+  well.
+endef
+
+$(eval $(call KernelPackage,gpio-it87))
+
+
+define KernelPackage/gpio-nxp-74hc164
+  SUBMENU:=$(GPIO_MENU)
+  TITLE:=NXP 74HC164 GPIO expander support
+  KCONFIG:=CONFIG_GPIO_74X164
+  FILES:=$(LINUX_DIR)/drivers/gpio/gpio-74x164.ko
+  AUTOLOAD:=$(call AutoProbe,gpio-74x164)
+endef
+
+define KernelPackage/gpio-nxp-74hc164/description
+ Kernel module for NXP 74HC164 GPIO expander
+endef
+
+$(eval $(call KernelPackage,gpio-nxp-74hc164))
+
+
+define KernelPackage/gpio-pca953x
+  SUBMENU:=$(GPIO_MENU)
+  DEPENDS:=@GPIO_SUPPORT +kmod-i2c-core +kmod-regmap-i2c
+  TITLE:=PCA95xx, TCA64xx, and MAX7310 I/O ports
+  KCONFIG:=CONFIG_GPIO_PCA953X
+  FILES:=$(LINUX_DIR)/drivers/gpio/gpio-pca953x.ko
+  AUTOLOAD:=$(call AutoLoad,55,gpio-pca953x)
+endef
+
+define KernelPackage/gpio-pca953x/description
+ Kernel module for MAX731{0,2,3,5}, PCA6107, PCA953{4-9}, PCA955{4-7},
+ PCA957{4,5} and TCA64{08,16} I2C GPIO expanders
+endef
+
+$(eval $(call KernelPackage,gpio-pca953x))
+
+
+define KernelPackage/gpio-pcf857x
+  SUBMENU:=$(GPIO_MENU)
+  DEPENDS:=@GPIO_SUPPORT +kmod-i2c-core
+  TITLE:=PCX857x, PCA967x and MAX732X I2C GPIO expanders
+  KCONFIG:=CONFIG_GPIO_PCF857X
+  FILES:=$(LINUX_DIR)/drivers/gpio/gpio-pcf857x.ko
+  AUTOLOAD:=$(call AutoLoad,55,gpio-pcf857x)
+endef
+
+define KernelPackage/gpio-pcf857x/description
+ Kernel module for PCF857x, PCA{85,96}7x, and MAX732[89] I2C GPIO expanders
+endef
+
+$(eval $(call KernelPackage,gpio-pcf857x))
diff --git a/package/kernel/linux/modules/netdevices.mk b/package/kernel/linux/modules/netdevices.mk
index 63f75e959145b2..72504d8de7f4b6 100644
--- a/package/kernel/linux/modules/netdevices.mk
+++ b/package/kernel/linux/modules/netdevices.mk
@@ -375,6 +375,23 @@ endef
 $(eval $(call KernelPackage,phy-smsc))
 
 
+define KernelPackage/phy-airoha-en8811h
+  SUBMENU:=$(NETWORK_DEVICES_MENU)
+  TITLE:=Airoha EN8811H 2.5G Ethernet PHY
+  DEPENDS:=+airoha-en8811h-firmware +kmod-libphy @LINUX_6_1
+  KCONFIG:=CONFIG_AIR_EN8811H_PHY
+  FILES:= \
+   $(LINUX_DIR)/drivers/net/phy/air_en8811h.ko
+  AUTOLOAD:=$(call AutoLoad,18,air_en8811h,1)
+endef
+
+define KernelPackage/phy-airoha-en8811h/description
+  Kernel modules for Airoha EN8811H 2.5G Ethernet PHY
+endef
+
+$(eval $(call KernelPackage,phy-airoha-en8811h))
+
+
 define KernelPackage/phy-aquantia
   SUBMENU:=$(NETWORK_DEVICES_MENU)
   TITLE:=Aquantia Ethernet PHYs
diff --git a/package/kernel/linux/modules/other.mk b/package/kernel/linux/modules/other.mk
index face5794727736..e227fd6a0f98ad 100644
--- a/package/kernel/linux/modules/other.mk
+++ b/package/kernel/linux/modules/other.mk
@@ -228,22 +228,6 @@ endef
 $(eval $(call KernelPackage,google-firmware))
 
 
-define KernelPackage/gpio-f7188x
-  SUBMENU:=$(OTHER_MENU)
-  TITLE:=Fintek F718xx/F818xx GPIO Support
-  DEPENDS:=@GPIO_SUPPORT @TARGET_x86
-  KCONFIG:=CONFIG_GPIO_F7188X
-  FILES:=$(LINUX_DIR)/drivers/gpio/gpio-f7188x.ko
-  AUTOLOAD:=$(call AutoProbe,gpio-f7188x)
-endef
-
-define KernelPackage/gpio-f7188x/description
-  Kernel module for the GPIOs found on many Fintek Super-IO chips.
-endef
-
-$(eval $(call KernelPackage,gpio-f7188x))
-
-
 define KernelPackage/lkdtm
   SUBMENU:=$(OTHER_MENU)
   TITLE:=Linux Kernel Dump Test Tool Module
@@ -312,87 +296,6 @@ endef
 $(eval $(call KernelPackage,pinctrl-mcp23s08-spi))
 
 
-define KernelPackage/gpio-nxp-74hc164
-  SUBMENU:=$(OTHER_MENU)
-  TITLE:=NXP 74HC164 GPIO expander support
-  KCONFIG:=CONFIG_GPIO_74X164
-  FILES:=$(LINUX_DIR)/drivers/gpio/gpio-74x164.ko
-  AUTOLOAD:=$(call AutoProbe,gpio-74x164)
-endef
-
-define KernelPackage/gpio-nxp-74hc164/description
- Kernel module for NXP 74HC164 GPIO expander
-endef
-
-$(eval $(call KernelPackage,gpio-nxp-74hc164))
-
-define KernelPackage/gpio-pca953x
-  SUBMENU:=$(OTHER_MENU)
-  DEPENDS:=@GPIO_SUPPORT +kmod-i2c-core +kmod-regmap-i2c
-  TITLE:=PCA95xx, TCA64xx, and MAX7310 I/O ports
-  KCONFIG:=CONFIG_GPIO_PCA953X
-  FILES:=$(LINUX_DIR)/drivers/gpio/gpio-pca953x.ko
-  AUTOLOAD:=$(call AutoLoad,55,gpio-pca953x)
-endef
-
-define KernelPackage/gpio-pca953x/description
- Kernel module for MAX731{0,2,3,5}, PCA6107, PCA953{4-9}, PCA955{4-7},
- PCA957{4,5} and TCA64{08,16} I2C GPIO expanders
-endef
-
-$(eval $(call KernelPackage,gpio-pca953x))
-
-define KernelPackage/gpio-pcf857x
-  SUBMENU:=$(OTHER_MENU)
-  DEPENDS:=@GPIO_SUPPORT +kmod-i2c-core
-  TITLE:=PCX857x, PCA967x and MAX732X I2C GPIO expanders
-  KCONFIG:=CONFIG_GPIO_PCF857X
-  FILES:=$(LINUX_DIR)/drivers/gpio/gpio-pcf857x.ko
-  AUTOLOAD:=$(call AutoLoad,55,gpio-pcf857x)
-endef
-
-define KernelPackage/gpio-pcf857x/description
- Kernel module for PCF857x, PCA{85,96}7x, and MAX732[89] I2C GPIO expanders
-endef
-
-$(eval $(call KernelPackage,gpio-pcf857x))
-
-
-define KernelPackage/gpio-it87
-  SUBMENU:=$(OTHER_MENU)
-  DEPENDS:=@GPIO_SUPPORT @TARGET_x86
-  TITLE:=GPIO support for IT87xx Super I/O chips
-  KCONFIG:=CONFIG_GPIO_IT87
-  FILES:=$(LINUX_DIR)/drivers/gpio/gpio-it87.ko
-  AUTOLOAD:=$(call AutoLoad,25,gpio-it87,1)
-endef
-
-define KernelPackage/gpio-it87/description
-  This driver is tested with ITE IT8728 and IT8732 Super I/O chips, and
-  supports the IT8761E, IT8613, IT8620E, and IT8628E Super I/O chips as
-  well.
-endef
-
-$(eval $(call KernelPackage,gpio-it87))
-
-
-define KernelPackage/gpio-amd-fch
-  SUBMENU:=$(OTHER_MENU)
-  DEPENDS:=@GPIO_SUPPORT @TARGET_x86
-  TITLE:=GPIO support for AMD Fusion Controller Hub (G-series SOCs)
-  KCONFIG:=CONFIG_GPIO_AMD_FCH
-  FILES:=$(LINUX_DIR)/drivers/gpio/gpio-amd-fch.ko
-  AUTOLOAD:=$(call AutoLoad,25,gpio-amd-fch,1)
-endef
-
-define KernelPackage/gpio-amd-fch/description
-  This option enables driver for GPIO on AMDs Fusion Controller Hub,
-  as found on G-series SOCs (eg. GX-412TC)
-endef
-
-$(eval $(call KernelPackage,gpio-amd-fch))
-
-
 define KernelPackage/ppdev
   SUBMENU:=$(OTHER_MENU)
   TITLE:=Parallel port support
@@ -675,6 +578,23 @@ endef
 $(eval $(call KernelPackage,rtc-isl1208))
 
 
+define KernelPackage/rtc-mv
+  SUBMENU:=$(OTHER_MENU)
+  TITLE:=Marvell SoC RTC support
+  DEFAULT:=m if ALL_KMODS && RTC_SUPPORT
+  KCONFIG:=CONFIG_RTC_DRV_MV \
+	CONFIG_RTC_CLASS=y
+  FILES:=$(LINUX_DIR)/drivers/rtc/rtc-mv.ko
+  AUTOLOAD:=$(call AutoProbe,rtc-mv)
+endef
+
+define KernelPackage/rtc-mv/description
+ Kernel module for Marvell SoC RTC.
+endef
+
+$(eval $(call KernelPackage,rtc-mv))
+
+
 define KernelPackage/rtc-pcf8563
   SUBMENU:=$(OTHER_MENU)
   TITLE:=Philips PCF8563/Epson RTC8564 RTC support
@@ -1207,25 +1127,6 @@ endef
 $(eval $(call KernelPackage,thermal))
 
 
-define KernelPackage/gpio-beeper
-  SUBMENU:=$(OTHER_MENU)
-  TITLE:=GPIO beeper support
-  DEPENDS:=+kmod-input-core
-  KCONFIG:= \
-	CONFIG_INPUT_MISC=y \
-	CONFIG_INPUT_GPIO_BEEPER
-  FILES:= \
-	$(LINUX_DIR)/drivers/input/misc/gpio-beeper.ko
-  AUTOLOAD:=$(call AutoLoad,50,gpio-beeper)
-endef
-
-define KernelPackage/gpio-beeper/description
- This enables playing beeps through an GPIO-connected buzzer
-endef
-
-$(eval $(call KernelPackage,gpio-beeper))
-
-
 define KernelPackage/echo
   SUBMENU:=$(OTHER_MENU)
   TITLE:=Line Echo Canceller
diff --git a/package/kernel/linux/modules/usb.mk b/package/kernel/linux/modules/usb.mk
index 6218ec994c8357..7f9e627fdb473f 100644
--- a/package/kernel/linux/modules/usb.mk
+++ b/package/kernel/linux/modules/usb.mk
@@ -1739,6 +1739,7 @@ define KernelPackage/usb3
 	+TARGET_ramips_mt7621:kmod-usb-xhci-mtk \
 	+TARGET_mediatek:kmod-usb-xhci-mtk \
 	+TARGET_apm821xx_nand:kmod-usb-xhci-pci-renesas \
+	+TARGET_lantiq_xrx200:kmod-usb-xhci-pci-renesas \
 	+TARGET_mvebu_cortexa9:kmod-usb-xhci-pci-renesas
   KCONFIG:= \
 	CONFIG_USB_PCI=y \
diff --git a/package/kernel/linux/modules/video.mk b/package/kernel/linux/modules/video.mk
index cb96ae80f8de7d..982bcb1db00b76 100644
--- a/package/kernel/linux/modules/video.mk
+++ b/package/kernel/linux/modules/video.mk
@@ -380,6 +380,7 @@ define KernelPackage/drm-imx
 	CONFIG_DRM_IMX_HDMI=n
   FILES:= \
 	$(LINUX_DIR)/drivers/gpu/drm/imx/imxdrm.ko \
+	$(LINUX_DIR)/drivers/gpu/drm/drm_dma_helper.ko@ge6.1 \
 	$(LINUX_DIR)/drivers/gpu/ipu-v3/imx-ipu-v3.ko
   AUTOLOAD:=$(call AutoLoad,08,imxdrm imx-ipu-v3 imx-ipuv3-crtc)
 endef
@@ -393,7 +394,7 @@ $(eval $(call KernelPackage,drm-imx))
 define KernelPackage/drm-imx-hdmi
   SUBMENU:=$(VIDEO_MENU)
   TITLE:=Freescale i.MX HDMI DRM support
-  DEPENDS:=+kmod-sound-core kmod-drm-imx
+  DEPENDS:=+kmod-sound-core kmod-drm-imx +LINUX_6_1:kmod-drm-display-helper
   KCONFIG:=CONFIG_DRM_IMX_HDMI \
 	CONFIG_DRM_DW_HDMI_AHB_AUDIO \
 	CONFIG_DRM_DW_HDMI_I2S_AUDIO
@@ -426,7 +427,7 @@ define KernelPackage/drm-imx-ldb
 	CONFIG_DRM_PANEL_SITRONIX_ST7789V=n
   FILES:=$(LINUX_DIR)/drivers/gpu/drm/imx/imx-ldb.ko \
 	$(LINUX_DIR)/drivers/gpu/drm/panel/panel-simple.ko \
-	$(LINUX_DIR)/drivers/gpu/drm/drm_dp_aux_bus.ko
+	$(LINUX_DIR)/drivers/gpu/drm/drm_dp_aux_bus.ko@lt6.1
   AUTOLOAD:=$(call AutoLoad,08,imx-ldb)
 endef
 
@@ -465,10 +466,11 @@ define KernelPackage/video-core
 	CONFIG_MEDIA_SUPPORT \
 	CONFIG_MEDIA_CAMERA_SUPPORT=y \
 	CONFIG_VIDEO_DEV \
-	CONFIG_V4L_PLATFORM_DRIVERS=y
+	CONFIG_V4L_PLATFORM_DRIVERS=y \
+	CONFIG_MEDIA_PLATFORM_DRIVERS=y@ge6.1
   FILES:= \
 	$(LINUX_DIR)/drivers/media/$(V4L2_DIR)/videodev.ko
-  AUTOLOAD:=$(call AutoLoad,60, videodev v4l2-common)
+  AUTOLOAD:=$(call AutoLoad,60,videodev)
 endef
 
 define KernelPackage/video-core/description
@@ -500,6 +502,7 @@ define KernelPackage/video-videobuf2
   KCONFIG:= \
 	CONFIG_VIDEOBUF2_CORE \
 	CONFIG_VIDEOBUF2_MEMOPS \
+	CONFIG_VIDEOBUF2_V4L2 \
 	CONFIG_VIDEOBUF2_VMALLOC
   FILES:= \
 	$(LINUX_DIR)/drivers/media/common/videobuf2/videobuf2-common.ko \
@@ -1109,7 +1112,9 @@ define KernelPackage/video-mem2mem
   TITLE:=Memory 2 Memory device support
   HIDDEN:=1
   DEPENDS:=+kmod-video-videobuf2
-  KCONFIG:= CONFIG_V4L_MEM2MEM_DRIVERS=y
+  KCONFIG:= \
+    CONFIG_V4L_MEM2MEM_DRIVERS=y \
+    CONFIG_V4L2_MEM2MEM_DEV
   FILES:= $(LINUX_DIR)/drivers/media/$(V4L2_DIR)/v4l2-mem2mem.ko
   AUTOLOAD:=$(call AutoLoad,66,v4l2-mem2mem)
   $(call AddDepends/video)
@@ -1147,8 +1152,10 @@ define KernelPackage/video-coda
   	CONFIG_VIDEO_CODA \
   	CONFIG_VIDEO_IMX_VDOA
   FILES:= \
-  	$(LINUX_DIR)/drivers/media/$(V4L2_MEM2MEM_DIR)/coda/coda-vpu.ko \
-  	$(LINUX_DIR)/drivers/media/$(V4L2_MEM2MEM_DIR)/coda/imx-vdoa.ko \
+  	$(LINUX_DIR)/drivers/media/$(V4L2_MEM2MEM_DIR)/coda/coda-vpu.ko@lt6.1 \
+  	$(LINUX_DIR)/drivers/media/$(V4L2_MEM2MEM_DIR)/chips-media/coda-vpu.ko@ge6.1 \
+  	$(LINUX_DIR)/drivers/media/$(V4L2_MEM2MEM_DIR)/coda/imx-vdoa.ko@lt6.1 \
+  	$(LINUX_DIR)/drivers/media/$(V4L2_MEM2MEM_DIR)/chips-media/imx-vdoa.ko@ge6.1 \
  	$(LINUX_DIR)/drivers/media/$(V4L2_DIR)/v4l2-jpeg.ko
   AUTOLOAD:=$(call AutoProbe,coda-vpu imx-vdoa v4l2-jpeg)
   $(call AddDepends/video)
@@ -1164,7 +1171,8 @@ define KernelPackage/video-pxp
   TITLE:=i.MX PXP support
   DEPENDS:=@TARGET_imx +kmod-video-mem2mem +kmod-video-dma
   KCONFIG:= CONFIG_VIDEO_IMX_PXP
-  FILES:= $(LINUX_DIR)/drivers/media/$(V4L2_MEM2MEM_DIR)/imx-pxp.ko
+  FILES:= $(LINUX_DIR)/drivers/media/$(V4L2_MEM2MEM_DIR)/imx-pxp.ko@lt6.1 \
+	$(LINUX_DIR)/drivers/media/platform/nxp/imx-pxp.ko@ge6.1
   AUTOLOAD:=$(call AutoProbe,imx-pxp)
   $(call AddDepends/video)
 endef
diff --git a/package/kernel/mac80211/Makefile b/package/kernel/mac80211/Makefile
index 17e0d9451e1c4b..54a2bf4499273c 100644
--- a/package/kernel/mac80211/Makefile
+++ b/package/kernel/mac80211/Makefile
@@ -10,14 +10,13 @@ include $(INCLUDE_DIR)/kernel.mk
 
 PKG_NAME:=mac80211
 
-PKG_VERSION:=6.5
-PKG_RELEASE:=2
-# PKG_SOURCE_URL:=@KERNEL/linux/kernel/projects/backports/stable/v5.15.58/
+PKG_VERSION:=6.6.15
+PKG_RELEASE:=1
 PKG_SOURCE_URL:=http://mirror2.openwrt.org/sources/
-PKG_HASH:=908c22dceba185eab83caa5a1e58ce6b3ebdc58f099c3fd3e11c7352ebfab2d7
+PKG_HASH:=3bbc461121134fda9089c084a5eed577d05e7837a157edf9a3797937172a3ece
 
 PKG_SOURCE:=backports-$(PKG_VERSION).tar.xz
-PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/backports-$(PKG_VERSION)
+PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(if $(BUILD_VARIANT),$(PKG_NAME)-$(BUILD_VARIANT)/)backports-$(PKG_VERSION)
 PKG_BUILD_PARALLEL:=1
 
 PKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>
@@ -48,7 +47,13 @@ define KernelPackage/mac80211/Default
   MAINTAINER:=Felix Fietkau <nbd@nbd.name>
 endef
 
-config_package=$(if $(CONFIG_PACKAGE_kmod-$(1)),m)
+# config_pacakge:
+# 1 = OpenWrt KernelPackage name
+# 2 = Optional list of variants for which the module may be selected:
+#     If empty, the module is only selected with the first variant
+#     Use $(ALL_VARIANTS) to allow module selection in all variants
+config_package=$(if $(and $(CONFIG_PACKAGE_kmod-$(1)),$(call mac80211_variant_check,$(2))),m)
+mac80211_variant_check=$(if $(ALL_VARIANTS),$(filter $(BUILD_VARIANT),$(if $(1),$(1),$(firstword $(ALL_VARIANTS)))),y)
 
 config-y:= \
 	WLAN \
@@ -73,10 +78,10 @@ config-y:= \
 	WLAN_VENDOR_TI \
 	WLAN_VENDOR_ZYDAS \
 
-config-$(call config_package,cfg80211) += CFG80211
+config-$(call config_package,cfg80211,$(ALL_VARIANTS)) += CFG80211
 config-$(CONFIG_PACKAGE_CFG80211_TESTMODE) += NL80211_TESTMODE
 
-config-$(call config_package,mac80211) += MAC80211
+config-$(call config_package,mac80211,$(ALL_VARIANTS)) += MAC80211
 config-$(CONFIG_PACKAGE_MAC80211_MESH) += MAC80211_MESH
 
 include ath.mk
@@ -92,7 +97,7 @@ PKG_CONFIG_DEPENDS += \
 define KernelPackage/cfg80211
   $(call KernelPackage/mac80211/Default)
   TITLE:=cfg80211 - wireless configuration API
-  DEPENDS+= +iw +iwinfo +wireless-regdb +USE_RFKILL:kmod-rfkill
+  DEPENDS+= +iw +iwinfo +wifi-scripts +wireless-regdb +USE_RFKILL:kmod-rfkill
   ABI_VERSION:=$(PKG_VERSION)-$(PKG_RELEASE)
   FILES:= \
 	$(PKG_BUILD_DIR)/compat/compat.ko \
@@ -384,14 +389,6 @@ define Build/InstallDev
 endef
 
 
-define KernelPackage/cfg80211/install
-	$(INSTALL_DIR) $(1)/lib/wifi $(1)/lib/netifd/wireless
-	$(INSTALL_DATA) ./files/lib/wifi/mac80211.sh $(1)/lib/wifi
-	$(INSTALL_BIN) ./files/lib/netifd/wireless/mac80211.sh $(1)/lib/netifd/wireless
-	$(INSTALL_DIR) $(1)/etc/hotplug.d/ieee80211
-	$(INSTALL_DATA) ./files/mac80211.hotplug $(1)/etc/hotplug.d/ieee80211/10-wifi-detect
-endef
-
 $(eval $(foreach drv,$(PKG_DRIVERS),$(call KernelPackage,$(drv))))
 $(eval $(call KernelPackage,cfg80211))
 $(eval $(call KernelPackage,mac80211))
diff --git a/package/kernel/mac80211/ath.mk b/package/kernel/mac80211/ath.mk
index 881c89db253dc6..dd200a89d42c37 100644
--- a/package/kernel/mac80211/ath.mk
+++ b/package/kernel/mac80211/ath.mk
@@ -37,7 +37,7 @@ ifdef CONFIG_PACKAGE_MAC80211_TRACING
 	WIL6210_TRACING
 endif
 
-config-$(call config_package,ath) += ATH_CARDS ATH_COMMON
+config-$(call config_package,ath,regular smallbuffers) += ATH_CARDS ATH_COMMON
 config-$(CONFIG_PACKAGE_ATH_DEBUG) += ATH_DEBUG ATH10K_DEBUG ATH11K_DEBUG ATH9K_STATION_STATISTICS
 config-$(CONFIG_PACKAGE_ATH_DFS) += ATH9K_DFS_CERTIFIED ATH10K_DFS_CERTIFIED
 config-$(CONFIG_PACKAGE_ATH_SPECTRAL) += ATH9K_COMMON_SPECTRAL ATH10K_SPECTRAL ATH11K_SPECTRAL
@@ -58,8 +58,8 @@ config-$(CONFIG_ATH10K_THERMAL) += ATH10K_THERMAL
 config-$(CONFIG_ATH11K_THERMAL) += ATH11K_THERMAL
 
 config-$(call config_package,ath9k-htc) += ATH9K_HTC
-config-$(call config_package,ath10k) += ATH10K ATH10K_PCI
-config-$(call config_package,ath10k-smallbuffers) += ATH10K ATH10K_PCI ATH10K_SMALLBUFFERS
+config-$(call config_package,ath10k,regular) += ATH10K ATH10K_PCI
+config-$(call config_package,ath10k-smallbuffers,smallbuffers) += ATH10K ATH10K_PCI ATH10K_SMALLBUFFERS
 config-$(call config_package,ath11k) += ATH11K
 config-$(call config_package,ath11k-ahb) += ATH11K_AHB
 config-$(call config_package,ath11k-pci) += ATH11K_PCI
diff --git a/package/kernel/mac80211/patches/ath/100-wifi-ath-add-struct_group-for-struct-ath_cycle_count.patch b/package/kernel/mac80211/patches/ath/100-wifi-ath-add-struct_group-for-struct-ath_cycle_count.patch
index 6c476e90581172..f464072d75084d 100644
--- a/package/kernel/mac80211/patches/ath/100-wifi-ath-add-struct_group-for-struct-ath_cycle_count.patch
+++ b/package/kernel/mac80211/patches/ath/100-wifi-ath-add-struct_group-for-struct-ath_cycle_count.patch
@@ -71,7 +71,7 @@ Signed-off-by: Shiji Yang <yangshiji66@qq.com>
  	/*
 --- a/drivers/net/wireless/ath/ath5k/mac80211-ops.c
 +++ b/drivers/net/wireless/ath/ath5k/mac80211-ops.c
-@@ -665,7 +665,7 @@ ath5k_get_survey(struct ieee80211_hw *hw
+@@ -664,7 +664,7 @@ ath5k_get_survey(struct ieee80211_hw *hw
  		ah->survey.time_rx += cc->rx_frame / div;
  		ah->survey.time_tx += cc->tx_frame / div;
  	}
diff --git a/package/kernel/mac80211/patches/ath11k/0001-wifi-ath11k-fix-band-selection-for-ppdu-received-in-.patch b/package/kernel/mac80211/patches/ath11k/0001-wifi-ath11k-fix-band-selection-for-ppdu-received-in-.patch
deleted file mode 100644
index e6f9ac9e4c0aab..00000000000000
--- a/package/kernel/mac80211/patches/ath11k/0001-wifi-ath11k-fix-band-selection-for-ppdu-received-in-.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From 72c8caf904aed2caed5d6e75233294b6159ddb5d Mon Sep 17 00:00:00 2001
-From: Aditya Kumar Singh <quic_adisi@quicinc.com>
-Date: Wed, 26 Jul 2023 10:16:24 +0530
-Subject: [PATCH 1/5] wifi: ath11k: fix band selection for ppdu received in
- channel 177 of 5 GHz
-
-5 GHz band channel 177 support was added with the commit e5e94d10c856 ("wifi:
-ath11k: add channel 177 into 5 GHz channel list"). However, during processing
-for the received ppdu in ath11k_dp_rx_h_ppdu(), channel number is checked only
-till 173. This leads to driver code checking for channel and then fetching the
-band from it which is extra effort since firmware has already given the channel
-number in the metadata.
-
-Fix this issue by checking the channel number till 177 since we support
-it now.
-
-Found via code review. Compile tested only.
-
-Fixes: e5e94d10c856 ("wifi: ath11k: add channel 177 into 5 GHz channel list")
-Signed-off-by: Aditya Kumar Singh <quic_adisi@quicinc.com>
-Signed-off-by: Kalle Valo <quic_kvalo@quicinc.com>
-Link: https://lore.kernel.org/r/20230726044624.20507-1-quic_adisi@quicinc.com
----
- drivers/net/wireless/ath/ath11k/dp_rx.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/net/wireless/ath/ath11k/dp_rx.c
-+++ b/drivers/net/wireless/ath/ath11k/dp_rx.c
-@@ -2408,7 +2408,7 @@ static void ath11k_dp_rx_h_ppdu(struct a
- 		rx_status->freq = center_freq;
- 	} else if (channel_num >= 1 && channel_num <= 14) {
- 		rx_status->band = NL80211_BAND_2GHZ;
--	} else if (channel_num >= 36 && channel_num <= 173) {
-+	} else if (channel_num >= 36 && channel_num <= 177) {
- 		rx_status->band = NL80211_BAND_5GHZ;
- 	} else {
- 		spin_lock_bh(&ar->data_lock);
diff --git a/package/kernel/mac80211/patches/ath11k/0002-wifi-ath11k-simplify-ath11k_mac_validate_vht_he_fixe.patch b/package/kernel/mac80211/patches/ath11k/0002-wifi-ath11k-simplify-ath11k_mac_validate_vht_he_fixe.patch
deleted file mode 100644
index ad761e6a909098..00000000000000
--- a/package/kernel/mac80211/patches/ath11k/0002-wifi-ath11k-simplify-ath11k_mac_validate_vht_he_fixe.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From 6f092c98dcfa1e4cf37d45f9b8e4d4a3cbeb79d4 Mon Sep 17 00:00:00 2001
-From: Dmitry Antipov <dmantipov@yandex.ru>
-Date: Wed, 26 Jul 2023 12:21:02 +0300
-Subject: [PATCH 2/5] wifi: ath11k: simplify
- ath11k_mac_validate_vht_he_fixed_rate_settings()
-
-In ath11k_mac_validate_vht_he_fixed_rate_settings() ar->ab->peers
-list is not altered so list_for_each_entry() should be safe.
-
-Compile tested only.
-
-Signed-off-by: Dmitry Antipov <dmantipov@yandex.ru>
-Signed-off-by: Kalle Valo <quic_kvalo@quicinc.com>
-Link: https://lore.kernel.org/r/20230726092113.78794-1-dmantipov@yandex.ru
----
- drivers/net/wireless/ath/ath11k/mac.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/drivers/net/wireless/ath/ath11k/mac.c
-+++ b/drivers/net/wireless/ath/ath11k/mac.c
-@@ -8258,7 +8258,7 @@ ath11k_mac_validate_vht_he_fixed_rate_se
- 					       const struct cfg80211_bitrate_mask *mask)
- {
- 	bool he_fixed_rate = false, vht_fixed_rate = false;
--	struct ath11k_peer *peer, *tmp;
-+	struct ath11k_peer *peer;
- 	const u16 *vht_mcs_mask, *he_mcs_mask;
- 	struct ieee80211_link_sta *deflink;
- 	u8 vht_nss, he_nss;
-@@ -8281,7 +8281,7 @@ ath11k_mac_validate_vht_he_fixed_rate_se
- 
- 	rcu_read_lock();
- 	spin_lock_bh(&ar->ab->base_lock);
--	list_for_each_entry_safe(peer, tmp, &ar->ab->peers, list) {
-+	list_for_each_entry(peer, &ar->ab->peers, list) {
- 		if (peer->sta) {
- 			deflink = &peer->sta->deflink;
- 
diff --git a/package/kernel/mac80211/patches/ath11k/0003-wifi-ath11k-Split-coldboot-calibration-hw_param.patch b/package/kernel/mac80211/patches/ath11k/0003-wifi-ath11k-Split-coldboot-calibration-hw_param.patch
deleted file mode 100644
index f8c7c937eabfa8..00000000000000
--- a/package/kernel/mac80211/patches/ath11k/0003-wifi-ath11k-Split-coldboot-calibration-hw_param.patch
+++ /dev/null
@@ -1,180 +0,0 @@
-From 011e5a3052a22d3758d17442bf0c04c68bf79bea Mon Sep 17 00:00:00 2001
-From: Seevalamuthu Mariappan <quic_seevalam@quicinc.com>
-Date: Wed, 26 Jul 2023 19:40:30 +0530
-Subject: [PATCH 3/5] wifi: ath11k: Split coldboot calibration hw_param
-
-QCN9074 enables coldboot calibration only in Factory Test Mode (FTM).
-Hence, split cold_boot_calib to two hw_params for mission and FTM
-mode.
-
-Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1
-
-Signed-off-by: Seevalamuthu Mariappan <quic_seevalam@quicinc.com>
-Signed-off-by: Raj Kumar Bhagat <quic_rajkbhag@quicinc.com>
-Signed-off-by: Kalle Valo <quic_kvalo@quicinc.com>
-Link: https://lore.kernel.org/r/20230726141032.3061-2-quic_rajkbhag@quicinc.com
----
- drivers/net/wireless/ath/ath11k/ahb.c  |  3 +--
- drivers/net/wireless/ath/ath11k/core.c | 36 ++++++++++++++++++++------
- drivers/net/wireless/ath/ath11k/core.h |  1 +
- drivers/net/wireless/ath/ath11k/hw.h   |  3 ++-
- drivers/net/wireless/ath/ath11k/qmi.c  |  6 ++---
- 5 files changed, 35 insertions(+), 14 deletions(-)
-
---- a/drivers/net/wireless/ath/ath11k/ahb.c
-+++ b/drivers/net/wireless/ath/ath11k/ahb.c
-@@ -422,8 +422,7 @@ static int ath11k_ahb_fwreset_from_cold_
- {
- 	int timeout;
- 
--	if (ath11k_cold_boot_cal == 0 || ab->qmi.cal_done ||
--	    ab->hw_params.cold_boot_calib == 0 ||
-+	if (!ath11k_core_coldboot_cal_support(ab) || ab->qmi.cal_done ||
- 	    ab->hw_params.cbcal_restart_fw == 0)
- 		return 0;
- 
---- a/drivers/net/wireless/ath/ath11k/core.c
-+++ b/drivers/net/wireless/ath/ath11k/core.c
-@@ -86,7 +86,8 @@ static const struct ath11k_hw_params ath
- 		.supports_shadow_regs = false,
- 		.idle_ps = false,
- 		.supports_sta_ps = false,
--		.cold_boot_calib = true,
-+		.coldboot_cal_mm = true,
-+		.coldboot_cal_ftm = true,
- 		.cbcal_restart_fw = true,
- 		.fw_mem_mode = 0,
- 		.num_vdevs = 16 + 1,
-@@ -167,7 +168,8 @@ static const struct ath11k_hw_params ath
- 		.supports_shadow_regs = false,
- 		.idle_ps = false,
- 		.supports_sta_ps = false,
--		.cold_boot_calib = true,
-+		.coldboot_cal_mm = true,
-+		.coldboot_cal_ftm = true,
- 		.cbcal_restart_fw = true,
- 		.fw_mem_mode = 0,
- 		.num_vdevs = 16 + 1,
-@@ -248,7 +250,8 @@ static const struct ath11k_hw_params ath
- 		.supports_shadow_regs = true,
- 		.idle_ps = true,
- 		.supports_sta_ps = true,
--		.cold_boot_calib = false,
-+		.coldboot_cal_mm = false,
-+		.coldboot_cal_ftm = false,
- 		.cbcal_restart_fw = false,
- 		.fw_mem_mode = 0,
- 		.num_vdevs = 16 + 1,
-@@ -332,7 +335,8 @@ static const struct ath11k_hw_params ath
- 		.supports_shadow_regs = false,
- 		.idle_ps = false,
- 		.supports_sta_ps = false,
--		.cold_boot_calib = false,
-+		.coldboot_cal_mm = false,
-+		.coldboot_cal_ftm = false,
- 		.cbcal_restart_fw = false,
- 		.fw_mem_mode = 2,
- 		.num_vdevs = 8,
-@@ -413,7 +417,8 @@ static const struct ath11k_hw_params ath
- 		.supports_shadow_regs = true,
- 		.idle_ps = true,
- 		.supports_sta_ps = true,
--		.cold_boot_calib = false,
-+		.coldboot_cal_mm = false,
-+		.coldboot_cal_ftm = false,
- 		.cbcal_restart_fw = false,
- 		.fw_mem_mode = 0,
- 		.num_vdevs = 16 + 1,
-@@ -495,7 +500,8 @@ static const struct ath11k_hw_params ath
- 		.supports_shadow_regs = true,
- 		.idle_ps = true,
- 		.supports_sta_ps = true,
--		.cold_boot_calib = false,
-+		.coldboot_cal_mm = false,
-+		.coldboot_cal_ftm = false,
- 		.cbcal_restart_fw = false,
- 		.fw_mem_mode = 0,
- 		.num_vdevs = 16 + 1,
-@@ -578,7 +584,8 @@ static const struct ath11k_hw_params ath
- 		.supports_shadow_regs = true,
- 		.idle_ps = true,
- 		.supports_sta_ps = true,
--		.cold_boot_calib = true,
-+		.coldboot_cal_mm = true,
-+		.coldboot_cal_ftm = true,
- 		.cbcal_restart_fw = false,
- 		.fw_mem_mode = 0,
- 		.num_vdevs = 16 + 1,
-@@ -667,7 +674,8 @@ static const struct ath11k_hw_params ath
- 		.supports_suspend = false,
- 		.hal_params = &ath11k_hw_hal_params_ipq8074,
- 		.single_pdev_only = false,
--		.cold_boot_calib = true,
-+		.coldboot_cal_mm = true,
-+		.coldboot_cal_ftm = true,
- 		.cbcal_restart_fw = true,
- 		.fix_l1ss = true,
- 		.supports_dynamic_smps_6ghz = false,
-@@ -749,6 +757,18 @@ void ath11k_fw_stats_free(struct ath11k_
- 	ath11k_fw_stats_bcn_free(&stats->bcn);
- }
- 
-+bool ath11k_core_coldboot_cal_support(struct ath11k_base *ab)
-+{
-+	if (!ath11k_cold_boot_cal)
-+		return false;
-+
-+	if (ath11k_ftm_mode)
-+		return ab->hw_params.coldboot_cal_ftm;
-+
-+	else
-+		return ab->hw_params.coldboot_cal_mm;
-+}
-+
- int ath11k_core_suspend(struct ath11k_base *ab)
- {
- 	int ret;
---- a/drivers/net/wireless/ath/ath11k/core.h
-+++ b/drivers/net/wireless/ath/ath11k/core.h
-@@ -1186,6 +1186,7 @@ void ath11k_core_halt(struct ath11k *ar)
- int ath11k_core_resume(struct ath11k_base *ab);
- int ath11k_core_suspend(struct ath11k_base *ab);
- void ath11k_core_pre_reconfigure_recovery(struct ath11k_base *ab);
-+bool ath11k_core_coldboot_cal_support(struct ath11k_base *ab);
- 
- const struct firmware *ath11k_core_firmware_request(struct ath11k_base *ab,
- 						    const char *filename);
---- a/drivers/net/wireless/ath/ath11k/hw.h
-+++ b/drivers/net/wireless/ath/ath11k/hw.h
-@@ -187,7 +187,8 @@ struct ath11k_hw_params {
- 	bool supports_shadow_regs;
- 	bool idle_ps;
- 	bool supports_sta_ps;
--	bool cold_boot_calib;
-+	bool coldboot_cal_mm;
-+	bool coldboot_cal_ftm;
- 	bool cbcal_restart_fw;
- 	int fw_mem_mode;
- 	u32 num_vdevs;
---- a/drivers/net/wireless/ath/ath11k/qmi.c
-+++ b/drivers/net/wireless/ath/ath11k/qmi.c
-@@ -2079,7 +2079,7 @@ static int ath11k_qmi_assign_target_mem_
- 				return -EINVAL;
- 			}
- 
--			if (ath11k_cold_boot_cal && ab->hw_params.cold_boot_calib) {
-+			if (ath11k_core_coldboot_cal_support(ab)) {
- 				if (hremote_node) {
- 					ab->qmi.target_mem[idx].paddr =
- 							res.start + host_ddr_sz;
-@@ -3209,8 +3209,8 @@ static void ath11k_qmi_driver_event_work
- 				break;
- 			}
- 
--			if (ath11k_cold_boot_cal && ab->qmi.cal_done == 0 &&
--			    ab->hw_params.cold_boot_calib) {
-+			if (ab->qmi.cal_done == 0 &&
-+			    ath11k_core_coldboot_cal_support(ab)) {
- 				ath11k_qmi_process_coldboot_calibration(ab);
- 			} else {
- 				clear_bit(ATH11K_FLAG_CRASH_FLUSH,
diff --git a/package/kernel/mac80211/patches/ath11k/0004-wifi-ath11k-Add-coldboot-calibration-support-for-QCN.patch b/package/kernel/mac80211/patches/ath11k/0004-wifi-ath11k-Add-coldboot-calibration-support-for-QCN.patch
deleted file mode 100644
index 9d51c1c3eaaef5..00000000000000
--- a/package/kernel/mac80211/patches/ath11k/0004-wifi-ath11k-Add-coldboot-calibration-support-for-QCN.patch
+++ /dev/null
@@ -1,176 +0,0 @@
-From bdfc967bf5fcd762473a01d39edb81f1165ba290 Mon Sep 17 00:00:00 2001
-From: Anilkumar Kolli <quic_akolli@quicinc.com>
-Date: Wed, 26 Jul 2023 19:40:31 +0530
-Subject: [PATCH 4/5] wifi: ath11k: Add coldboot calibration support for
- QCN9074
-
-QCN9074 supports 6 GHz, which has increased number of channels
-compared to 5 GHz/2 GHz. So, to support coldboot calibration in
-QCN9074 ATH11K_COLD_BOOT_FW_RESET_DELAY extended to 60 seconds. To
-avoid code redundancy, fwreset_from_cold_boot moved to QMI and made
-common for both ahb and pci. Coldboot calibration is enabled only in
-FTM mode for QCN9074. QCN9074 requires firmware restart after coldboot,
-hence enable cbcal_restart_fw in hw_params.
-
-This support can be enabled/disabled using hw params for different
-hardware. Currently it is not enabled for QCA6390.
-
-Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1
-
-Signed-off-by: Anilkumar Kolli <quic_akolli@quicinc.com>
-Signed-off-by: Seevalamuthu Mariappan <quic_seevalam@quicinc.com>
-Signed-off-by: Raj Kumar Bhagat <quic_rajkbhag@quicinc.com>
-Signed-off-by: Kalle Valo <quic_kvalo@quicinc.com>
-Link: https://lore.kernel.org/r/20230726141032.3061-3-quic_rajkbhag@quicinc.com
----
- drivers/net/wireless/ath/ath11k/ahb.c  | 28 ++------------------------
- drivers/net/wireless/ath/ath11k/core.c |  4 ++--
- drivers/net/wireless/ath/ath11k/pci.c  |  2 ++
- drivers/net/wireless/ath/ath11k/qmi.c  | 28 ++++++++++++++++++++++++++
- drivers/net/wireless/ath/ath11k/qmi.h  |  3 ++-
- 5 files changed, 36 insertions(+), 29 deletions(-)
-
---- a/drivers/net/wireless/ath/ath11k/ahb.c
-+++ b/drivers/net/wireless/ath/ath11k/ahb.c
-@@ -14,6 +14,7 @@
- #include "ahb.h"
- #include "debug.h"
- #include "hif.h"
-+#include "qmi.h"
- #include <linux/remoteproc.h>
- #include "pcic.h"
- #include <linux/soc/qcom/smem.h>
-@@ -418,31 +419,6 @@ static void ath11k_ahb_power_down(struct
- 	rproc_shutdown(ab_ahb->tgt_rproc);
- }
- 
--static int ath11k_ahb_fwreset_from_cold_boot(struct ath11k_base *ab)
--{
--	int timeout;
--
--	if (!ath11k_core_coldboot_cal_support(ab) || ab->qmi.cal_done ||
--	    ab->hw_params.cbcal_restart_fw == 0)
--		return 0;
--
--	ath11k_dbg(ab, ATH11K_DBG_AHB, "wait for cold boot done\n");
--	timeout = wait_event_timeout(ab->qmi.cold_boot_waitq,
--				     (ab->qmi.cal_done  == 1),
--				     ATH11K_COLD_BOOT_FW_RESET_DELAY);
--	if (timeout <= 0) {
--		ath11k_cold_boot_cal = 0;
--		ath11k_warn(ab, "Coldboot Calibration failed timed out\n");
--	}
--
--	/* reset the firmware */
--	ath11k_ahb_power_down(ab);
--	ath11k_ahb_power_up(ab);
--
--	ath11k_dbg(ab, ATH11K_DBG_AHB, "exited from cold boot mode\n");
--	return 0;
--}
--
- static void ath11k_ahb_init_qmi_ce_config(struct ath11k_base *ab)
- {
- 	struct ath11k_qmi_ce_cfg *cfg = &ab->qmi.ce_cfg;
-@@ -1225,7 +1201,7 @@ static int ath11k_ahb_probe(struct platf
- 		goto err_ce_free;
- 	}
- 
--	ath11k_ahb_fwreset_from_cold_boot(ab);
-+	ath11k_qmi_fwreset_from_cold_boot(ab);
- 
- 	return 0;
- 
---- a/drivers/net/wireless/ath/ath11k/core.c
-+++ b/drivers/net/wireless/ath/ath11k/core.c
-@@ -336,8 +336,8 @@ static const struct ath11k_hw_params ath
- 		.idle_ps = false,
- 		.supports_sta_ps = false,
- 		.coldboot_cal_mm = false,
--		.coldboot_cal_ftm = false,
--		.cbcal_restart_fw = false,
-+		.coldboot_cal_ftm = true,
-+		.cbcal_restart_fw = true,
- 		.fw_mem_mode = 2,
- 		.num_vdevs = 8,
- 		.num_peers = 128,
---- a/drivers/net/wireless/ath/ath11k/pci.c
-+++ b/drivers/net/wireless/ath/ath11k/pci.c
-@@ -15,6 +15,7 @@
- #include "mhi.h"
- #include "debug.h"
- #include "pcic.h"
-+#include "qmi.h"
- 
- #define ATH11K_PCI_BAR_NUM		0
- #define ATH11K_PCI_DMA_MASK		32
-@@ -897,6 +898,7 @@ unsupported_wcn6855_soc:
- 		ath11k_err(ab, "failed to init core: %d\n", ret);
- 		goto err_irq_affinity_cleanup;
- 	}
-+	ath11k_qmi_fwreset_from_cold_boot(ab);
- 	return 0;
- 
- err_irq_affinity_cleanup:
---- a/drivers/net/wireless/ath/ath11k/qmi.c
-+++ b/drivers/net/wireless/ath/ath11k/qmi.c
-@@ -9,6 +9,7 @@
- #include "qmi.h"
- #include "core.h"
- #include "debug.h"
-+#include "hif.h"
- #include <linux/of.h>
- #include <linux/of_address.h>
- #include <linux/ioport.h>
-@@ -2839,6 +2840,33 @@ int ath11k_qmi_firmware_start(struct ath
- 	return 0;
- }
- 
-+int ath11k_qmi_fwreset_from_cold_boot(struct ath11k_base *ab)
-+{
-+	int timeout;
-+
-+	if (!ath11k_core_coldboot_cal_support(ab) || ab->qmi.cal_done ||
-+	    ab->hw_params.cbcal_restart_fw == 0)
-+		return 0;
-+
-+	ath11k_dbg(ab, ATH11K_DBG_QMI, "wait for cold boot done\n");
-+
-+	timeout = wait_event_timeout(ab->qmi.cold_boot_waitq,
-+				     (ab->qmi.cal_done == 1),
-+				     ATH11K_COLD_BOOT_FW_RESET_DELAY);
-+
-+	if (timeout <= 0) {
-+		ath11k_warn(ab, "Coldboot Calibration timed out\n");
-+		return -ETIMEDOUT;
-+	}
-+
-+	/* reset the firmware */
-+	ath11k_hif_power_down(ab);
-+	ath11k_hif_power_up(ab);
-+	ath11k_dbg(ab, ATH11K_DBG_QMI, "exit wait for cold boot done\n");
-+	return 0;
-+}
-+EXPORT_SYMBOL(ath11k_qmi_fwreset_from_cold_boot);
-+
- static int ath11k_qmi_process_coldboot_calibration(struct ath11k_base *ab)
- {
- 	int timeout;
---- a/drivers/net/wireless/ath/ath11k/qmi.h
-+++ b/drivers/net/wireless/ath/ath11k/qmi.h
-@@ -37,7 +37,7 @@
- 
- #define QMI_WLANFW_MAX_DATA_SIZE_V01		6144
- #define ATH11K_FIRMWARE_MODE_OFF		4
--#define ATH11K_COLD_BOOT_FW_RESET_DELAY		(40 * HZ)
-+#define ATH11K_COLD_BOOT_FW_RESET_DELAY		(60 * HZ)
- 
- #define ATH11K_QMI_DEVICE_BAR_SIZE		0x200000
- 
-@@ -519,5 +519,6 @@ void ath11k_qmi_msg_recv_work(struct wor
- void ath11k_qmi_deinit_service(struct ath11k_base *ab);
- int ath11k_qmi_init_service(struct ath11k_base *ab);
- void ath11k_qmi_free_resource(struct ath11k_base *ab);
-+int ath11k_qmi_fwreset_from_cold_boot(struct ath11k_base *ab);
- 
- #endif
diff --git a/package/kernel/mac80211/patches/ath11k/0005-wifi-ath11k-Remove-cal_done-check-during-probe.patch b/package/kernel/mac80211/patches/ath11k/0005-wifi-ath11k-Remove-cal_done-check-during-probe.patch
deleted file mode 100644
index 884fd58d75b0ff..00000000000000
--- a/package/kernel/mac80211/patches/ath11k/0005-wifi-ath11k-Remove-cal_done-check-during-probe.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From 13329d0cb7212b058bd8451a99d215a8f97645ea Mon Sep 17 00:00:00 2001
-From: Seevalamuthu Mariappan <quic_seevalam@quicinc.com>
-Date: Wed, 26 Jul 2023 19:40:32 +0530
-Subject: [PATCH 5/5] wifi: ath11k: Remove cal_done check during probe
-
-In some race conditions, calibration done QMI message is received even
-before host wait starts for calibration to be done.
-Due to this, resetting firmware was not performed after calibration.
-
-Hence, remove cal_done check in ath11k_qmi_fwreset_from_cold_boot()
-as this is called only from probe.
-
-Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1
-
-Signed-off-by: Seevalamuthu Mariappan <quic_seevalam@quicinc.com>
-Signed-off-by: Raj Kumar Bhagat <quic_rajkbhag@quicinc.com>
-Signed-off-by: Kalle Valo <quic_kvalo@quicinc.com>
-Link: https://lore.kernel.org/r/20230726141032.3061-4-quic_rajkbhag@quicinc.com
----
- drivers/net/wireless/ath/ath11k/qmi.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/net/wireless/ath/ath11k/qmi.c
-+++ b/drivers/net/wireless/ath/ath11k/qmi.c
-@@ -2844,7 +2844,7 @@ int ath11k_qmi_fwreset_from_cold_boot(st
- {
- 	int timeout;
- 
--	if (!ath11k_core_coldboot_cal_support(ab) || ab->qmi.cal_done ||
-+	if (!ath11k_core_coldboot_cal_support(ab) ||
- 	    ab->hw_params.cbcal_restart_fw == 0)
- 		return 0;
- 
diff --git a/package/kernel/mac80211/patches/ath11k/0006-wifi-ath11k-Don-t-drop-tx_status-when-peer-cannot-be.patch b/package/kernel/mac80211/patches/ath11k/0006-wifi-ath11k-Don-t-drop-tx_status-when-peer-cannot-be.patch
deleted file mode 100644
index e404a7849e63f2..00000000000000
--- a/package/kernel/mac80211/patches/ath11k/0006-wifi-ath11k-Don-t-drop-tx_status-when-peer-cannot-be.patch
+++ /dev/null
@@ -1,53 +0,0 @@
-From 400ece6c7f346b0a30867bd00b03b5b2563d4357 Mon Sep 17 00:00:00 2001
-From: Sven Eckelmann <sven@narfation.org>
-Date: Tue, 22 Aug 2023 16:42:24 +0300
-Subject: [PATCH] wifi: ath11k: Don't drop tx_status when peer cannot be found
-
-When a station idles for a long time, hostapd will try to send a QoS Null
-frame to the station as "poll". NL80211_CMD_PROBE_CLIENT is used for this
-purpose. And the skb will be added to ack_status_frame - waiting for a
-completion via ieee80211_report_ack_skb().
-
-But when the peer was already removed before the tx_complete arrives, the
-peer will be missing. And when using dev_kfree_skb_any (instead of going
-through mac80211), the entry will stay inside ack_status_frames. This IDR
-will therefore run full after 8K request were generated for such clients.
-At this point, the access point will then just stall and not allow any new
-clients because idr_alloc() for ack_status_frame will fail.
-
-ieee80211_free_txskb() on the other hand will (when required) call
-ieee80211_report_ack_skb() and make sure that (when required) remove the
-entry from the ack_status_frame.
-
-Tested-on: IPQ6018 hw1.0 WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1
-
-Fixes: 6257c702264c ("wifi: ath11k: fix tx status reporting in encap offload mode")
-Fixes: 94739d45c388 ("ath11k: switch to using ieee80211_tx_status_ext()")
-Cc: stable@vger.kernel.org
-Signed-off-by: Sven Eckelmann <sven@narfation.org>
-Signed-off-by: Kalle Valo <quic_kvalo@quicinc.com>
-Link: https://lore.kernel.org/r/20230802-ath11k-ack_status_leak-v2-1-c0af729d6229@narfation.org
----
- drivers/net/wireless/ath/ath11k/dp_tx.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/drivers/net/wireless/ath/ath11k/dp_tx.c
-+++ b/drivers/net/wireless/ath/ath11k/dp_tx.c
-@@ -369,7 +369,7 @@ ath11k_dp_tx_htt_tx_complete_buf(struct
- 			   "dp_tx: failed to find the peer with peer_id %d\n",
- 			    ts->peer_id);
- 		spin_unlock_bh(&ab->base_lock);
--		dev_kfree_skb_any(msdu);
-+		ieee80211_free_txskb(ar->hw, msdu);
- 		return;
- 	}
- 	spin_unlock_bh(&ab->base_lock);
-@@ -624,7 +624,7 @@ static void ath11k_dp_tx_complete_msdu(s
- 			   "dp_tx: failed to find the peer with peer_id %d\n",
- 			    ts->peer_id);
- 		spin_unlock_bh(&ab->base_lock);
--		dev_kfree_skb_any(msdu);
-+		ieee80211_free_txskb(ar->hw, msdu);
- 		return;
- 	}
- 	arsta = (struct ath11k_sta *)peer->sta->drv_priv;
diff --git a/package/kernel/mac80211/patches/ath11k/0007-wifi-ath11k-Cleanup-mac80211-references-on-failure-d.patch b/package/kernel/mac80211/patches/ath11k/0007-wifi-ath11k-Cleanup-mac80211-references-on-failure-d.patch
deleted file mode 100644
index ae9cd05dd6220e..00000000000000
--- a/package/kernel/mac80211/patches/ath11k/0007-wifi-ath11k-Cleanup-mac80211-references-on-failure-d.patch
+++ /dev/null
@@ -1,51 +0,0 @@
-From 29d15589f084d71a4ea8c544039c5839db0236e2 Mon Sep 17 00:00:00 2001
-From: Sven Eckelmann <sven@narfation.org>
-Date: Tue, 22 Aug 2023 16:42:24 +0300
-Subject: [PATCH] wifi: ath11k: Cleanup mac80211 references on failure during
- tx_complete
-
-When a function is using functions from mac80211 to free an skb then it
-should do it consistently and not switch to the generic dev_kfree_skb_any
-(or similar functions). Otherwise (like in the error handlers), mac80211
-will will not be aware of the freed skb and thus not clean up related
-information in its internal data structures.
-
-Not doing so lead in the past to filled up structure which then prevented
-new clients to connect.
-
-Fixes: d5c65159f289 ("ath11k: driver for Qualcomm IEEE 802.11ax devices")
-Fixes: 6257c702264c ("wifi: ath11k: fix tx status reporting in encap offload mode")
-Cc: stable@vger.kernel.org
-Signed-off-by: Sven Eckelmann <sven@narfation.org>
-Signed-off-by: Kalle Valo <quic_kvalo@quicinc.com>
-Link: https://lore.kernel.org/r/20230802-ath11k-ack_status_leak-v2-2-c0af729d6229@narfation.org
----
- drivers/net/wireless/ath/ath11k/dp_tx.c | 6 +++---
- 1 file changed, 3 insertions(+), 3 deletions(-)
-
---- a/drivers/net/wireless/ath/ath11k/dp_tx.c
-+++ b/drivers/net/wireless/ath/ath11k/dp_tx.c
-@@ -344,7 +344,7 @@ ath11k_dp_tx_htt_tx_complete_buf(struct
- 	dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
- 
- 	if (!skb_cb->vif) {
--		dev_kfree_skb_any(msdu);
-+		ieee80211_free_txskb(ar->hw, msdu);
- 		return;
- 	}
- 
-@@ -566,12 +566,12 @@ static void ath11k_dp_tx_complete_msdu(s
- 	dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
- 
- 	if (unlikely(!rcu_access_pointer(ab->pdevs_active[ar->pdev_idx]))) {
--		dev_kfree_skb_any(msdu);
-+		ieee80211_free_txskb(ar->hw, msdu);
- 		return;
- 	}
- 
- 	if (unlikely(!skb_cb->vif)) {
--		dev_kfree_skb_any(msdu);
-+		ieee80211_free_txskb(ar->hw, msdu);
- 		return;
- 	}
- 
diff --git a/package/kernel/mac80211/patches/ath11k/0008-wifi-ath11k-Consistently-use-ath11k_vif_to_arvif.patch b/package/kernel/mac80211/patches/ath11k/0008-wifi-ath11k-Consistently-use-ath11k_vif_to_arvif.patch
deleted file mode 100644
index 218b3ac35fc13b..00000000000000
--- a/package/kernel/mac80211/patches/ath11k/0008-wifi-ath11k-Consistently-use-ath11k_vif_to_arvif.patch
+++ /dev/null
@@ -1,316 +0,0 @@
-From 9476cda44c136089f14f8951ae5197d63e91735c Mon Sep 17 00:00:00 2001
-From: Jeff Johnson <quic_jjohnson@quicinc.com>
-Date: Mon, 21 Aug 2023 07:13:36 -0700
-Subject: [PATCH] wifi: ath11k: Consistently use ath11k_vif_to_arvif()
-
-Helper function ath11k_vif_to_arvif() exists to retrieve a struct
-ath11k_vif from a struct ieee80211_vif. However, in multiple places
-this logic is open-coded with inline typecasting. Since the
-typecasting prevents the compiler from type-checking the source and
-destination, update the driver to consistently use the helper
-function.
-
-No functional changes, compile tested only.
-
-Signed-off-by: Jeff Johnson <quic_jjohnson@quicinc.com>
-Signed-off-by: Kalle Valo <quic_kvalo@quicinc.com>
-Link: https://lore.kernel.org/r/20230821-ath11k_vif_to_arvif-v1-1-fa2c3b60b5cf@quicinc.com
----
- drivers/net/wireless/ath/ath11k/mac.c      | 64 +++++++++++-----------
- drivers/net/wireless/ath/ath11k/testmode.c |  2 +-
- 2 files changed, 33 insertions(+), 33 deletions(-)
-
---- a/drivers/net/wireless/ath/ath11k/mac.c
-+++ b/drivers/net/wireless/ath/ath11k/mac.c
-@@ -566,7 +566,7 @@ static void ath11k_get_arvif_iter(void *
- 				  struct ieee80211_vif *vif)
- {
- 	struct ath11k_vif_iter *arvif_iter = data;
--	struct ath11k_vif *arvif = (void *)vif->drv_priv;
-+	struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif);
- 
- 	if (arvif->vdev_id == arvif_iter->vdev_id)
- 		arvif_iter->arvif = arvif;
-@@ -1464,7 +1464,7 @@ static int ath11k_mac_setup_bcn_tmpl_ema
- 	u32 params = 0;
- 	u8 i = 0;
- 
--	tx_arvif = (void *)arvif->vif->mbssid_tx_vif->drv_priv;
-+	tx_arvif = ath11k_vif_to_arvif(arvif->vif->mbssid_tx_vif);
- 
- 	beacons = ieee80211_beacon_get_template_ema_list(tx_arvif->ar->hw,
- 							 tx_arvif->vif, 0);
-@@ -1520,8 +1520,8 @@ static int ath11k_mac_setup_bcn_tmpl_mbs
- 	struct sk_buff *bcn;
- 	int ret;
- 
--	if (arvif->vif->mbssid_tx_vif) {
--		tx_arvif = (void *)arvif->vif->mbssid_tx_vif->drv_priv;
-+	if (vif->mbssid_tx_vif) {
-+		tx_arvif = ath11k_vif_to_arvif(vif->mbssid_tx_vif);
- 		if (tx_arvif != arvif) {
- 			ar = tx_arvif->ar;
- 			ab = ar->ab;
-@@ -1562,7 +1562,7 @@ static int ath11k_mac_setup_bcn_tmpl(str
- 	 * non-transmitting interfaces, and results in a crash if sent.
- 	 */
- 	if (vif->mbssid_tx_vif &&
--	    arvif != (void *)vif->mbssid_tx_vif->drv_priv && arvif->is_up)
-+	    arvif != ath11k_vif_to_arvif(vif->mbssid_tx_vif) && arvif->is_up)
- 		return 0;
- 
- 	if (vif->bss_conf.ema_ap && vif->mbssid_tx_vif)
-@@ -1626,7 +1626,7 @@ static void ath11k_control_beaconing(str
- 	ether_addr_copy(arvif->bssid, info->bssid);
- 
- 	if (arvif->vif->mbssid_tx_vif)
--		tx_arvif = (struct ath11k_vif *)arvif->vif->mbssid_tx_vif->drv_priv;
-+		tx_arvif = ath11k_vif_to_arvif(arvif->vif->mbssid_tx_vif);
- 
- 	ret = ath11k_wmi_vdev_up(arvif->ar, arvif->vdev_id, arvif->aid,
- 				 arvif->bssid,
-@@ -1649,7 +1649,7 @@ static void ath11k_mac_handle_beacon_ite
- {
- 	struct sk_buff *skb = data;
- 	struct ieee80211_mgmt *mgmt = (void *)skb->data;
--	struct ath11k_vif *arvif = (void *)vif->drv_priv;
-+	struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif);
- 
- 	if (vif->type != NL80211_IFTYPE_STATION)
- 		return;
-@@ -1672,7 +1672,7 @@ static void ath11k_mac_handle_beacon_mis
- 					       struct ieee80211_vif *vif)
- {
- 	u32 *vdev_id = data;
--	struct ath11k_vif *arvif = (void *)vif->drv_priv;
-+	struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif);
- 	struct ath11k *ar = arvif->ar;
- 	struct ieee80211_hw *hw = ar->hw;
- 
-@@ -1718,7 +1718,7 @@ static void ath11k_peer_assoc_h_basic(st
- 				      struct ieee80211_sta *sta,
- 				      struct peer_assoc_params *arg)
- {
--	struct ath11k_vif *arvif = (void *)vif->drv_priv;
-+	struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif);
- 	u32 aid;
- 
- 	lockdep_assert_held(&ar->conf_mutex);
-@@ -1746,7 +1746,7 @@ static void ath11k_peer_assoc_h_crypto(s
- 	struct ieee80211_bss_conf *info = &vif->bss_conf;
- 	struct cfg80211_chan_def def;
- 	struct cfg80211_bss *bss;
--	struct ath11k_vif *arvif = (struct ath11k_vif *)vif->drv_priv;
-+	struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif);
- 	const u8 *rsnie = NULL;
- 	const u8 *wpaie = NULL;
- 
-@@ -1804,7 +1804,7 @@ static void ath11k_peer_assoc_h_rates(st
- 				      struct ieee80211_sta *sta,
- 				      struct peer_assoc_params *arg)
- {
--	struct ath11k_vif *arvif = (void *)vif->drv_priv;
-+	struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif);
- 	struct wmi_rate_set_arg *rateset = &arg->peer_legacy_rates;
- 	struct cfg80211_chan_def def;
- 	const struct ieee80211_supported_band *sband;
-@@ -1867,7 +1867,7 @@ static void ath11k_peer_assoc_h_ht(struc
- 				   struct peer_assoc_params *arg)
- {
- 	const struct ieee80211_sta_ht_cap *ht_cap = &sta->deflink.ht_cap;
--	struct ath11k_vif *arvif = (void *)vif->drv_priv;
-+	struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif);
- 	struct cfg80211_chan_def def;
- 	enum nl80211_band band;
- 	const u8 *ht_mcs_mask;
-@@ -2064,7 +2064,7 @@ static void ath11k_peer_assoc_h_vht(stru
- 				    struct peer_assoc_params *arg)
- {
- 	const struct ieee80211_sta_vht_cap *vht_cap = &sta->deflink.vht_cap;
--	struct ath11k_vif *arvif = (void *)vif->drv_priv;
-+	struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif);
- 	struct cfg80211_chan_def def;
- 	enum nl80211_band band;
- 	u16 *vht_mcs_mask;
-@@ -2261,7 +2261,7 @@ static void ath11k_peer_assoc_h_he(struc
- 				   struct ieee80211_sta *sta,
- 				   struct peer_assoc_params *arg)
- {
--	struct ath11k_vif *arvif = (void *)vif->drv_priv;
-+	struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif);
- 	struct cfg80211_chan_def def;
- 	const struct ieee80211_sta_he_cap *he_cap = &sta->deflink.he_cap;
- 	enum nl80211_band band;
-@@ -2584,7 +2584,7 @@ static void ath11k_peer_assoc_h_qos(stru
- 				    struct ieee80211_sta *sta,
- 				    struct peer_assoc_params *arg)
- {
--	struct ath11k_vif *arvif = (void *)vif->drv_priv;
-+	struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif);
- 
- 	switch (arvif->vdev_type) {
- 	case WMI_VDEV_TYPE_AP:
-@@ -2747,7 +2747,7 @@ static void ath11k_peer_assoc_h_phymode(
- 					struct ieee80211_sta *sta,
- 					struct peer_assoc_params *arg)
- {
--	struct ath11k_vif *arvif = (void *)vif->drv_priv;
-+	struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif);
- 	struct cfg80211_chan_def def;
- 	enum nl80211_band band;
- 	const u8 *ht_mcs_mask;
-@@ -2933,7 +2933,7 @@ static bool ath11k_mac_vif_recalc_sta_he
- 					      struct ieee80211_vif *vif,
- 					      struct ieee80211_sta_he_cap *he_cap)
- {
--	struct ath11k_vif *arvif = (void *)vif->drv_priv;
-+	struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif);
- 	struct ieee80211_he_cap_elem he_cap_elem = {0};
- 	struct ieee80211_sta_he_cap *cap_band = NULL;
- 	struct cfg80211_chan_def def;
-@@ -2995,7 +2995,7 @@ static void ath11k_bss_assoc(struct ieee
- 			     struct ieee80211_bss_conf *bss_conf)
- {
- 	struct ath11k *ar = hw->priv;
--	struct ath11k_vif *arvif = (void *)vif->drv_priv;
-+	struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif);
- 	struct peer_assoc_params peer_arg;
- 	struct ieee80211_sta *ap_sta;
- 	struct ath11k_peer *peer;
-@@ -3111,7 +3111,7 @@ static void ath11k_bss_disassoc(struct i
- 				struct ieee80211_vif *vif)
- {
- 	struct ath11k *ar = hw->priv;
--	struct ath11k_vif *arvif = (void *)vif->drv_priv;
-+	struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif);
- 	int ret;
- 
- 	lockdep_assert_held(&ar->conf_mutex);
-@@ -3160,7 +3160,7 @@ static void ath11k_recalculate_mgmt_rate
- 					 struct ieee80211_vif *vif,
- 					 struct cfg80211_chan_def *def)
- {
--	struct ath11k_vif *arvif = (void *)vif->drv_priv;
-+	struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif);
- 	const struct ieee80211_supported_band *sband;
- 	u8 basic_rate_idx;
- 	int hw_rate_code;
-@@ -4632,7 +4632,7 @@ static int ath11k_station_disassoc(struc
- 				   struct ieee80211_vif *vif,
- 				   struct ieee80211_sta *sta)
- {
--	struct ath11k_vif *arvif = (void *)vif->drv_priv;
-+	struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif);
- 	int ret = 0;
- 
- 	lockdep_assert_held(&ar->conf_mutex);
-@@ -5160,7 +5160,7 @@ static int ath11k_mac_op_sta_set_txpwr(s
- 				       struct ieee80211_sta *sta)
- {
- 	struct ath11k *ar = hw->priv;
--	struct ath11k_vif *arvif = (void *)vif->drv_priv;
-+	struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif);
- 	int ret = 0;
- 	s16 txpwr;
- 
-@@ -5210,7 +5210,7 @@ static void ath11k_mac_op_sta_rc_update(
- {
- 	struct ath11k *ar = hw->priv;
- 	struct ath11k_sta *arsta = (struct ath11k_sta *)sta->drv_priv;
--	struct ath11k_vif *arvif = (void *)vif->drv_priv;
-+	struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif);
- 	struct ath11k_peer *peer;
- 	u32 bw, smps;
- 
-@@ -5337,7 +5337,7 @@ static int ath11k_mac_op_conf_tx(struct
- 				 const struct ieee80211_tx_queue_params *params)
- {
- 	struct ath11k *ar = hw->priv;
--	struct ath11k_vif *arvif = (void *)vif->drv_priv;
-+	struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif);
- 	struct wmi_wmm_params_arg *p = NULL;
- 	int ret;
- 
-@@ -6458,7 +6458,7 @@ static int ath11k_mac_setup_vdev_params_
- 		return 0;
- 	}
- 
--	tx_arvif = (void *)tx_vif->drv_priv;
-+	tx_arvif = ath11k_vif_to_arvif(tx_vif);
- 
- 	if (arvif->vif->bss_conf.nontransmitted) {
- 		if (ar->hw->wiphy != ieee80211_vif_to_wdev(tx_vif)->wiphy)
-@@ -7411,7 +7411,7 @@ ath11k_mac_update_vif_chan(struct ath11k
- 	/* TODO: Update ar->rx_channel */
- 
- 	for (i = 0; i < n_vifs; i++) {
--		arvif = (void *)vifs[i].vif->drv_priv;
-+		arvif = ath11k_vif_to_arvif(vifs[i].vif);
- 
- 		if (WARN_ON(!arvif->is_started))
- 			continue;
-@@ -7453,7 +7453,7 @@ ath11k_mac_update_vif_chan(struct ath11k
- 
- 		mbssid_tx_vif = arvif->vif->mbssid_tx_vif;
- 		if (mbssid_tx_vif)
--			tx_arvif = (struct ath11k_vif *)mbssid_tx_vif->drv_priv;
-+			tx_arvif = ath11k_vif_to_arvif(mbssid_tx_vif);
- 
- 		ret = ath11k_wmi_vdev_up(arvif->ar, arvif->vdev_id, arvif->aid,
- 					 arvif->bssid,
-@@ -7549,7 +7549,7 @@ static int ath11k_start_vdev_delay(struc
- {
- 	struct ath11k *ar = hw->priv;
- 	struct ath11k_base *ab = ar->ab;
--	struct ath11k_vif *arvif = (void *)vif->drv_priv;
-+	struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif);
- 	int ret;
- 
- 	if (WARN_ON(arvif->is_started))
-@@ -7599,7 +7599,7 @@ ath11k_mac_op_assign_vif_chanctx(struct
- {
- 	struct ath11k *ar = hw->priv;
- 	struct ath11k_base *ab = ar->ab;
--	struct ath11k_vif *arvif = (void *)vif->drv_priv;
-+	struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif);
- 	int ret;
- 	struct peer_create_params param;
- 
-@@ -7689,7 +7689,7 @@ ath11k_mac_op_unassign_vif_chanctx(struc
- {
- 	struct ath11k *ar = hw->priv;
- 	struct ath11k_base *ab = ar->ab;
--	struct ath11k_vif *arvif = (void *)vif->drv_priv;
-+	struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif);
- 	struct ath11k_peer *peer;
- 	int ret;
- 
-@@ -8310,7 +8310,7 @@ ath11k_mac_op_set_bitrate_mask(struct ie
- 			       struct ieee80211_vif *vif,
- 			       const struct cfg80211_bitrate_mask *mask)
- {
--	struct ath11k_vif *arvif = (void *)vif->drv_priv;
-+	struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif);
- 	struct cfg80211_chan_def def;
- 	struct ath11k_pdev_cap *cap;
- 	struct ath11k *ar = arvif->ar;
-@@ -8907,7 +8907,7 @@ static int ath11k_mac_op_remain_on_chann
- 					   enum ieee80211_roc_type type)
- {
- 	struct ath11k *ar = hw->priv;
--	struct ath11k_vif *arvif = (void *)vif->drv_priv;
-+	struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif);
- 	struct scan_req_params arg;
- 	int ret;
- 	u32 scan_time_msec;
---- a/drivers/net/wireless/ath/ath11k/testmode.c
-+++ b/drivers/net/wireless/ath/ath11k/testmode.c
-@@ -350,7 +350,7 @@ static int ath11k_tm_cmd_wmi(struct ath1
- 	if (ar->ab->fw_mode != ATH11K_FIRMWARE_MODE_FTM &&
- 	    (tag == WMI_TAG_VDEV_SET_PARAM_CMD || tag == WMI_TAG_UNIT_TEST_CMD)) {
- 		if (vif) {
--			arvif = (struct ath11k_vif *)vif->drv_priv;
-+			arvif = ath11k_vif_to_arvif(vif);
- 			*ptr = arvif->vdev_id;
- 		} else {
- 			ret = -EINVAL;
diff --git a/package/kernel/mac80211/patches/ath11k/0009-wifi-ath11k-Fix-a-few-spelling-errors.patch b/package/kernel/mac80211/patches/ath11k/0009-wifi-ath11k-Fix-a-few-spelling-errors.patch
deleted file mode 100644
index b093f3e34211ba..00000000000000
--- a/package/kernel/mac80211/patches/ath11k/0009-wifi-ath11k-Fix-a-few-spelling-errors.patch
+++ /dev/null
@@ -1,50 +0,0 @@
-From d68a283bfc39aeed2a51c67804e014bf4b35c7e1 Mon Sep 17 00:00:00 2001
-From: Jeff Johnson <quic_jjohnson@quicinc.com>
-Date: Tue, 22 Aug 2023 07:50:49 -0700
-Subject: [PATCH] wifi: ath11k: Fix a few spelling errors
-
-Fix a few issues flagged by 'codespell'.
-
-Signed-off-by: Jeff Johnson <quic_jjohnson@quicinc.com>
-Acked-by: Randy Dunlap <rdunlap@infradead.org>
-Signed-off-by: Kalle Valo <quic_kvalo@quicinc.com>
-Link: https://lore.kernel.org/r/20230822-ath_spelling-v1-2-8e2698759564@quicinc.com
----
- drivers/net/wireless/ath/ath11k/dp.h    | 2 +-
- drivers/net/wireless/ath/ath11k/dp_rx.c | 2 +-
- drivers/net/wireless/ath/ath11k/dp_tx.c | 2 +-
- 3 files changed, 3 insertions(+), 3 deletions(-)
-
---- a/drivers/net/wireless/ath/ath11k/dp.h
-+++ b/drivers/net/wireless/ath/ath11k/dp.h
-@@ -635,7 +635,7 @@ enum htt_ppdu_stats_tag_type {
-  *          b'24    - status_swap: 1 is to swap status TLV
-  *          b'25    - pkt_swap:  1 is to swap packet TLV
-  *          b'26:31 - rsvd1:  reserved for future use
-- * dword1 - b'0:16  - ring_buffer_size: size of bufferes referenced by rx ring,
-+ * dword1 - b'0:16  - ring_buffer_size: size of buffers referenced by rx ring,
-  *                    in byte units.
-  *                    Valid only for HW_TO_SW_RING and SW_TO_HW_RING
-  *        - b'16:31 - rsvd2: Reserved for future use
---- a/drivers/net/wireless/ath/ath11k/dp_rx.c
-+++ b/drivers/net/wireless/ath/ath11k/dp_rx.c
-@@ -3423,7 +3423,7 @@ static int ath11k_dp_rx_h_defrag_reo_rei
- 	ath11k_hal_rx_buf_addr_info_set(msdu0, paddr, cookie,
- 					ab->hw_params.hal_params->rx_buf_rbm);
- 
--	/* Fill mpdu details into reo entrace ring */
-+	/* Fill mpdu details into reo entrance ring */
- 	srng = &ab->hal.srng_list[ab->dp.reo_reinject_ring.ring_id];
- 
- 	spin_lock_bh(&srng->lock);
---- a/drivers/net/wireless/ath/ath11k/dp_tx.c
-+++ b/drivers/net/wireless/ath/ath11k/dp_tx.c
-@@ -238,7 +238,7 @@ tcl_ring_sel:
- 		spin_unlock_bh(&tcl_ring->lock);
- 		ret = -ENOMEM;
- 
--		/* Checking for available tcl descritors in another ring in
-+		/* Checking for available tcl descriptors in another ring in
- 		 * case of failure due to full tcl ring now, is better than
- 		 * checking this ring earlier for each pkt tx.
- 		 * Restart ring selection if some rings are not checked yet.
diff --git a/package/kernel/mac80211/patches/ath11k/0010-wifi-ath11k-simplify-the-code-with-module_platform_d.patch b/package/kernel/mac80211/patches/ath11k/0010-wifi-ath11k-simplify-the-code-with-module_platform_d.patch
deleted file mode 100644
index 19873339b23741..00000000000000
--- a/package/kernel/mac80211/patches/ath11k/0010-wifi-ath11k-simplify-the-code-with-module_platform_d.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From 749a660b39030bfbacc366cd8670df2ee0e878b2 Mon Sep 17 00:00:00 2001
-From: Yang Yingliang <yangyingliang@huawei.com>
-Date: Fri, 4 Aug 2023 17:12:55 +0800
-Subject: [PATCH] wifi: ath11k: simplify the code with module_platform_driver
-
-The init/exit() of driver only calls platform_driver_register/unregister,
-it can be simpilfied with module_platform_driver.
-
-Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
-Signed-off-by: Kalle Valo <quic_kvalo@quicinc.com>
-Link: https://lore.kernel.org/r/20230804091255.1347178-1-yangyingliang@huawei.com
----
- drivers/net/wireless/ath/ath11k/ahb.c | 12 +-----------
- 1 file changed, 1 insertion(+), 11 deletions(-)
-
---- a/drivers/net/wireless/ath/ath11k/ahb.c
-+++ b/drivers/net/wireless/ath/ath11k/ahb.c
-@@ -1306,17 +1306,7 @@ static struct platform_driver ath11k_ahb
- 	.shutdown = ath11k_ahb_shutdown,
- };
- 
--static int ath11k_ahb_init(void)
--{
--	return platform_driver_register(&ath11k_ahb_driver);
--}
--module_init(ath11k_ahb_init);
--
--static void ath11k_ahb_exit(void)
--{
--	platform_driver_unregister(&ath11k_ahb_driver);
--}
--module_exit(ath11k_ahb_exit);
-+module_platform_driver(ath11k_ahb_driver);
- 
- MODULE_DESCRIPTION("Driver support for Qualcomm Technologies 802.11ax WLAN AHB devices");
- MODULE_LICENSE("Dual BSD/GPL");
diff --git a/package/kernel/mac80211/patches/ath11k/0011-wifi-ath11k-fix-Wvoid-pointer-to-enum-cast-warning.patch b/package/kernel/mac80211/patches/ath11k/0011-wifi-ath11k-fix-Wvoid-pointer-to-enum-cast-warning.patch
deleted file mode 100644
index f42b021375b654..00000000000000
--- a/package/kernel/mac80211/patches/ath11k/0011-wifi-ath11k-fix-Wvoid-pointer-to-enum-cast-warning.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From 6763ef191d672ff3c2db0622652d49b0c0a60c4a Mon Sep 17 00:00:00 2001
-From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Date: Thu, 10 Aug 2023 11:12:23 +0200
-Subject: [PATCH] wifi: ath11k: fix Wvoid-pointer-to-enum-cast warning
-
-'hw_rev' is an enum, thus cast of pointer on 64-bit compile test with W=1
-causes:
-
-  h11k/ahb.c:1124:11: error: cast to smaller integer type 'enum ath11k_hw_rev' from 'const void *' [-Werror,-Wvoid-pointer-to-enum-cast]
-
-Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Acked-by: Jeff Johnson <quic_jjohnson@quicinc.com>
-Signed-off-by: Kalle Valo <quic_kvalo@quicinc.com>
-Link: https://lore.kernel.org/r/20230810091224.70088-1-krzysztof.kozlowski@linaro.org
----
- drivers/net/wireless/ath/ath11k/ahb.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/net/wireless/ath/ath11k/ahb.c
-+++ b/drivers/net/wireless/ath/ath11k/ahb.c
-@@ -1096,7 +1096,7 @@ static int ath11k_ahb_probe(struct platf
- 		return -EINVAL;
- 	}
- 
--	hw_rev = (enum ath11k_hw_rev)of_id->data;
-+	hw_rev = (uintptr_t)of_id->data;
- 
- 	switch (hw_rev) {
- 	case ATH11K_HW_IPQ8074:
diff --git a/package/kernel/mac80211/patches/ath11k/0012-wifi-ath11k-Remove-unused-declarations.patch b/package/kernel/mac80211/patches/ath11k/0012-wifi-ath11k-Remove-unused-declarations.patch
deleted file mode 100644
index c318bbc3213e02..00000000000000
--- a/package/kernel/mac80211/patches/ath11k/0012-wifi-ath11k-Remove-unused-declarations.patch
+++ /dev/null
@@ -1,44 +0,0 @@
-From adb0b206709f4f2f1256a1ea20619ab98e99f2e7 Mon Sep 17 00:00:00 2001
-From: Yue Haibing <yuehaibing@huawei.com>
-Date: Fri, 11 Aug 2023 18:44:13 +0800
-Subject: [PATCH] wifi: ath11k: Remove unused declarations
-
-Commit 2c3960c2253d ("ath11k: setup ce tasklet for control path")
-declared but never implemented ath11k_ce_map_service_to_pipe().
-Commit e3396b8bddd2 ("ath11k: ce: support different CE configurations")
-declared but never implemented ath11k_ce_attr_attach().
-Commit d5c65159f289 ("ath11k: driver for Qualcomm IEEE 802.11ax devices")
-declared but never implemented ath11k_qmi_event_work()/ath11k_qmi_msg_recv_work().
-
-Signed-off-by: Yue Haibing <yuehaibing@huawei.com>
-Acked-by: Jeff Johnson <quic_jjohnson@quicinc.com>
-Signed-off-by: Kalle Valo <quic_kvalo@quicinc.com>
-Link: https://lore.kernel.org/r/20230811104413.33668-1-yuehaibing@huawei.com
----
- drivers/net/wireless/ath/ath11k/ce.h  | 3 ---
- drivers/net/wireless/ath/ath11k/qmi.h | 2 --
- 2 files changed, 5 deletions(-)
-
---- a/drivers/net/wireless/ath/ath11k/ce.h
-+++ b/drivers/net/wireless/ath/ath11k/ce.h
-@@ -203,9 +203,6 @@ int ath11k_ce_alloc_pipes(struct ath11k_
- void ath11k_ce_free_pipes(struct ath11k_base *ab);
- int ath11k_ce_get_attr_flags(struct ath11k_base *ab, int ce_id);
- void ath11k_ce_poll_send_completed(struct ath11k_base *ab, u8 pipe_id);
--int ath11k_ce_map_service_to_pipe(struct ath11k_base *ab, u16 service_id,
--				  u8 *ul_pipe, u8 *dl_pipe);
--int ath11k_ce_attr_attach(struct ath11k_base *ab);
- void ath11k_ce_get_shadow_config(struct ath11k_base *ab,
- 				 u32 **shadow_cfg, u32 *shadow_cfg_len);
- void ath11k_ce_stop_shadow_timers(struct ath11k_base *ab);
---- a/drivers/net/wireless/ath/ath11k/qmi.h
-+++ b/drivers/net/wireless/ath/ath11k/qmi.h
-@@ -514,8 +514,6 @@ struct qmi_wlanfw_wlan_ini_resp_msg_v01
- int ath11k_qmi_firmware_start(struct ath11k_base *ab,
- 			      u32 mode);
- void ath11k_qmi_firmware_stop(struct ath11k_base *ab);
--void ath11k_qmi_event_work(struct work_struct *work);
--void ath11k_qmi_msg_recv_work(struct work_struct *work);
- void ath11k_qmi_deinit_service(struct ath11k_base *ab);
- int ath11k_qmi_init_service(struct ath11k_base *ab);
- void ath11k_qmi_free_resource(struct ath11k_base *ab);
diff --git a/package/kernel/mac80211/patches/ath11k/0017-wifi-ath11k-fix-boot-failure-with-one-MSI-vector.patch b/package/kernel/mac80211/patches/ath11k/0017-wifi-ath11k-fix-boot-failure-with-one-MSI-vector.patch
deleted file mode 100644
index 9101a1ea1ce557..00000000000000
--- a/package/kernel/mac80211/patches/ath11k/0017-wifi-ath11k-fix-boot-failure-with-one-MSI-vector.patch
+++ /dev/null
@@ -1,103 +0,0 @@
-From 39564b475ac5a589e6c22c43a08cbd283c295d2c Mon Sep 17 00:00:00 2001
-From: Baochen Qiang <quic_bqiang@quicinc.com>
-Date: Thu, 7 Sep 2023 09:56:06 +0800
-Subject: [PATCH] wifi: ath11k: fix boot failure with one MSI vector
-
-Commit 5b32b6dd96633 ("ath11k: Remove core PCI references from
-PCI common code") breaks with one MSI vector because it moves
-affinity setting after IRQ request, see below log:
-
-[ 1417.278835] ath11k_pci 0000:02:00.0: failed to receive control response completion, polling..
-[ 1418.302829] ath11k_pci 0000:02:00.0: Service connect timeout
-[ 1418.302833] ath11k_pci 0000:02:00.0: failed to connect to HTT: -110
-[ 1418.303669] ath11k_pci 0000:02:00.0: failed to start core: -110
-
-The detail is, if do affinity request after IRQ activated,
-which is done in request_irq(), kernel caches that request and
-returns success directly. Later when a subsequent MHI interrupt is
-fired, kernel will do the real affinity setting work, as a result,
-changs the MSI vector. However at that time host has configured
-old vector to hardware, so host never receives CE or DP interrupts.
-
-Fix it by setting affinity before registering MHI controller
-where host is, for the first time, doing IRQ request.
-
-Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-03125-QCAHSPSWPL_V1_V2_SILICONZ_LITE-3
-Tested-on: WCN6855 hw2.1 PCI WLAN.HSP.1.1-03125-QCAHSPSWPL_V1_V2_SILICONZ_LITE-3.6510.23
-Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-01160-QCAMSLSWPLZ-1
-
-Fixes: 5b32b6dd9663 ("ath11k: Remove core PCI references from PCI common code")
-Signed-off-by: Baochen Qiang <quic_bqiang@quicinc.com>
-Acked-by: Jeff Johnson <quic_jjohnson@quicinc.com>
-Signed-off-by: Kalle Valo <quic_kvalo@quicinc.com>
-Link: https://lore.kernel.org/r/20230907015606.16297-1-quic_bqiang@quicinc.com
----
- drivers/net/wireless/ath/ath11k/pci.c | 24 ++++++++++++------------
- 1 file changed, 12 insertions(+), 12 deletions(-)
-
---- a/drivers/net/wireless/ath/ath11k/pci.c
-+++ b/drivers/net/wireless/ath/ath11k/pci.c
-@@ -852,10 +852,16 @@ unsupported_wcn6855_soc:
- 	if (ret)
- 		goto err_pci_disable_msi;
- 
-+	ret = ath11k_pci_set_irq_affinity_hint(ab_pci, cpumask_of(0));
-+	if (ret) {
-+		ath11k_err(ab, "failed to set irq affinity %d\n", ret);
-+		goto err_pci_disable_msi;
-+	}
-+
- 	ret = ath11k_mhi_register(ab_pci);
- 	if (ret) {
- 		ath11k_err(ab, "failed to register mhi: %d\n", ret);
--		goto err_pci_disable_msi;
-+		goto err_irq_affinity_cleanup;
- 	}
- 
- 	ret = ath11k_hal_srng_init(ab);
-@@ -876,12 +882,6 @@ unsupported_wcn6855_soc:
- 		goto err_ce_free;
- 	}
- 
--	ret = ath11k_pci_set_irq_affinity_hint(ab_pci, cpumask_of(0));
--	if (ret) {
--		ath11k_err(ab, "failed to set irq affinity %d\n", ret);
--		goto err_free_irq;
--	}
--
- 	/* kernel may allocate a dummy vector before request_irq and
- 	 * then allocate a real vector when request_irq is called.
- 	 * So get msi_data here again to avoid spurious interrupt
-@@ -890,20 +890,17 @@ unsupported_wcn6855_soc:
- 	ret = ath11k_pci_config_msi_data(ab_pci);
- 	if (ret) {
- 		ath11k_err(ab, "failed to config msi_data: %d\n", ret);
--		goto err_irq_affinity_cleanup;
-+		goto err_free_irq;
- 	}
- 
- 	ret = ath11k_core_init(ab);
- 	if (ret) {
- 		ath11k_err(ab, "failed to init core: %d\n", ret);
--		goto err_irq_affinity_cleanup;
-+		goto err_free_irq;
- 	}
- 	ath11k_qmi_fwreset_from_cold_boot(ab);
- 	return 0;
- 
--err_irq_affinity_cleanup:
--	ath11k_pci_set_irq_affinity_hint(ab_pci, NULL);
--
- err_free_irq:
- 	ath11k_pcic_free_irq(ab);
- 
-@@ -916,6 +913,9 @@ err_hal_srng_deinit:
- err_mhi_unregister:
- 	ath11k_mhi_unregister(ab_pci);
- 
-+err_irq_affinity_cleanup:
-+	ath11k_pci_set_irq_affinity_hint(ab_pci, NULL);
-+
- err_pci_disable_msi:
- 	ath11k_pci_free_msi(ab_pci);
- 
diff --git a/package/kernel/mac80211/patches/ath11k/0019-wifi-ath11k-drop-redundant-check-in-ath11k_dp_rx_mon.patch b/package/kernel/mac80211/patches/ath11k/0019-wifi-ath11k-drop-redundant-check-in-ath11k_dp_rx_mon.patch
index ace199315b2ff6..cf182739189275 100644
--- a/package/kernel/mac80211/patches/ath11k/0019-wifi-ath11k-drop-redundant-check-in-ath11k_dp_rx_mon.patch
+++ b/package/kernel/mac80211/patches/ath11k/0019-wifi-ath11k-drop-redundant-check-in-ath11k_dp_rx_mon.patch
@@ -22,7 +22,7 @@ Link: https://lore.kernel.org/r/20230824075121.121144-1-dmantipov@yandex.ru
 
 --- a/drivers/net/wireless/ath/ath11k/dp_rx.c
 +++ b/drivers/net/wireless/ath/ath11k/dp_rx.c
-@@ -5094,13 +5094,6 @@ static void ath11k_dp_rx_mon_dest_proces
+@@ -5100,13 +5100,6 @@ static void ath11k_dp_rx_mon_dest_proces
  
  	mon_dst_srng = &ar->ab->hal.srng_list[ring_id];
  
diff --git a/package/kernel/mac80211/patches/ath11k/0022-wifi-ath11k-remove-unnecessary-void-conversions.patch b/package/kernel/mac80211/patches/ath11k/0022-wifi-ath11k-remove-unnecessary-void-conversions.patch
index cbd664dad58d3c..81c1ca16b32036 100644
--- a/package/kernel/mac80211/patches/ath11k/0022-wifi-ath11k-remove-unnecessary-void-conversions.patch
+++ b/package/kernel/mac80211/patches/ath11k/0022-wifi-ath11k-remove-unnecessary-void-conversions.patch
@@ -44,7 +44,7 @@ Link: https://lore.kernel.org/r/20230919045150.524304-1-yunchuan@nfschina.com
  
  	switch (tag) {
  	case HTT_PPDU_STATS_TAG_COMMON:
-@@ -4486,8 +4486,7 @@ int ath11k_dp_rx_monitor_link_desc_retur
+@@ -4492,8 +4492,7 @@ int ath11k_dp_rx_monitor_link_desc_retur
  	src_srng_desc = ath11k_hal_srng_src_get_next_entry(ar->ab, hal_srng);
  
  	if (src_srng_desc) {
@@ -54,7 +54,7 @@ Link: https://lore.kernel.org/r/20230919045150.524304-1-yunchuan@nfschina.com
  
  		*src_desc = *((struct ath11k_buffer_addr *)p_last_buf_addr_info);
  	} else {
-@@ -4506,8 +4505,7 @@ void ath11k_dp_rx_mon_next_link_desc_get
+@@ -4512,8 +4511,7 @@ void ath11k_dp_rx_mon_next_link_desc_get
  					 u8 *rbm,
  					 void **pp_buf_addr_info)
  {
@@ -64,7 +64,7 @@ Link: https://lore.kernel.org/r/20230919045150.524304-1-yunchuan@nfschina.com
  	struct ath11k_buffer_addr *buf_addr_info;
  
  	buf_addr_info = (struct ath11k_buffer_addr *)&msdu_link->buf_addr_info;
-@@ -4548,7 +4546,7 @@ static void ath11k_hal_rx_msdu_list_get(
+@@ -4554,7 +4552,7 @@ static void ath11k_hal_rx_msdu_list_get(
  	u32 first = FIELD_PREP(RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU, 1);
  	u8  tmp  = 0;
  
@@ -73,7 +73,7 @@ Link: https://lore.kernel.org/r/20230919045150.524304-1-yunchuan@nfschina.com
  	msdu_details = &msdu_link->msdu_link[0];
  
  	for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) {
-@@ -4645,8 +4643,7 @@ ath11k_dp_rx_mon_mpdu_pop(struct ath11k
+@@ -4651,8 +4649,7 @@ ath11k_dp_rx_mon_mpdu_pop(struct ath11k
  	bool is_frag, is_first_msdu;
  	bool drop_mpdu = false;
  	struct ath11k_skb_rxcb *rxcb;
diff --git a/package/kernel/mac80211/patches/ath11k/0026-wifi-ath11k-fix-Tx-power-value-during-active-CAC.patch b/package/kernel/mac80211/patches/ath11k/0026-wifi-ath11k-fix-Tx-power-value-during-active-CAC.patch
index 79c1d735b8255f..c3aa8a49afd0bd 100644
--- a/package/kernel/mac80211/patches/ath11k/0026-wifi-ath11k-fix-Tx-power-value-during-active-CAC.patch
+++ b/package/kernel/mac80211/patches/ath11k/0026-wifi-ath11k-fix-Tx-power-value-during-active-CAC.patch
@@ -26,9 +26,9 @@ Link: https://lore.kernel.org/r/20230912051857.2284-4-quic_adisi@quicinc.com
 
 --- a/drivers/net/wireless/ath/ath11k/mac.c
 +++ b/drivers/net/wireless/ath/ath11k/mac.c
-@@ -9060,6 +9060,14 @@ static int ath11k_mac_op_get_txpower(str
- 	if (ar->state != ATH11K_STATE_ON)
- 		goto err_fallback;
+@@ -9068,6 +9068,14 @@ static int ath11k_mac_op_get_txpower(str
+ 		return -EAGAIN;
+ 	}
  
 +	/* Firmware doesn't provide Tx power during CAC hence no need to fetch
 +	 * the stats.
diff --git a/package/kernel/mac80211/patches/ath11k/0031-wifi-ath11k-Introduce-and-use-ath11k_sta_to_arsta.patch b/package/kernel/mac80211/patches/ath11k/0031-wifi-ath11k-Introduce-and-use-ath11k_sta_to_arsta.patch
index 59af3b929795b9..1a6a701eeccd1f 100644
--- a/package/kernel/mac80211/patches/ath11k/0031-wifi-ath11k-Introduce-and-use-ath11k_sta_to_arsta.patch
+++ b/package/kernel/mac80211/patches/ath11k/0031-wifi-ath11k-Introduce-and-use-ath11k_sta_to_arsta.patch
@@ -230,7 +230,7 @@ Link: https://lore.kernel.org/r/20231009-ath11k_sta_to_arsta-v1-1-1563e3a307e8@q
  
  	memset(&arsta->txrate, 0, sizeof(arsta->txrate));
  
-@@ -5242,7 +5242,7 @@ int ath11k_dp_rx_process_mon_status(stru
+@@ -5248,7 +5248,7 @@ int ath11k_dp_rx_process_mon_status(stru
  			goto next_skb;
  		}
  
diff --git a/package/kernel/mac80211/patches/ath11k/0906-wifi-ath11k-disable-coldboot-for-ipq6018.patch b/package/kernel/mac80211/patches/ath11k/0906-wifi-ath11k-disable-coldboot-for-ipq6018.patch
new file mode 100644
index 00000000000000..db646f7620e89b
--- /dev/null
+++ b/package/kernel/mac80211/patches/ath11k/0906-wifi-ath11k-disable-coldboot-for-ipq6018.patch
@@ -0,0 +1,26 @@
+From a3be23672b4a81256d275af31afc6edcce5c5a26 Mon Sep 17 00:00:00 2001
+From: Mantas Pucka <mantas@8devices.com>
+Date: Mon, 22 Jan 2024 11:38:28 +0200
+Subject: [PATCH] wifi: ath11k: disable coldboot for ipq6018
+
+Coldboot calibration does not work at the moment and causes failure during
+wifi startup.
+
+Signed-off-by: Mantas Pucka <mantas@8devices.com>
+---
+ drivers/net/wireless/ath/ath11k/core.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/wireless/ath/ath11k/core.c
++++ b/drivers/net/wireless/ath/ath11k/core.c
+@@ -168,8 +168,8 @@ static const struct ath11k_hw_params ath
+ 		.supports_shadow_regs = false,
+ 		.idle_ps = false,
+ 		.supports_sta_ps = false,
+-		.coldboot_cal_mm = true,
+-		.coldboot_cal_ftm = true,
++		.coldboot_cal_mm = false,
++		.coldboot_cal_ftm = false,
+ 		.cbcal_restart_fw = true,
+ 		.fw_mem_mode = 0,
+ 		.num_vdevs = 16 + 1,
diff --git a/package/kernel/mac80211/patches/ath5k/440-ath5k_channel_bw_debugfs.patch b/package/kernel/mac80211/patches/ath5k/440-ath5k_channel_bw_debugfs.patch
index a63f0c881bfc93..6ff95f95a30e37 100644
--- a/package/kernel/mac80211/patches/ath5k/440-ath5k_channel_bw_debugfs.patch
+++ b/package/kernel/mac80211/patches/ath5k/440-ath5k_channel_bw_debugfs.patch
@@ -109,7 +109,7 @@ drivers/net/wireless/ath/ath5k/debug.c |   86 ++++++++++++++++++++++++++++++++
  
  /* debugfs: queues etc */
  
-@@ -997,6 +1088,8 @@ ath5k_debug_init_device(struct ath5k_hw
+@@ -995,6 +1086,8 @@ ath5k_debug_init_device(struct ath5k_hw
  	debugfs_create_file("queue", 0600, phydir, ah, &fops_queue);
  	debugfs_create_bool("32khz_clock", 0600, phydir,
  			    &ah->ah_use_32khz_clock);
diff --git a/package/kernel/mac80211/patches/ath9k/500-ath9k_eeprom_debugfs.patch b/package/kernel/mac80211/patches/ath9k/500-ath9k_eeprom_debugfs.patch
index d23d70b2ce7d17..a0ec7ef972f023 100644
--- a/package/kernel/mac80211/patches/ath9k/500-ath9k_eeprom_debugfs.patch
+++ b/package/kernel/mac80211/patches/ath9k/500-ath9k_eeprom_debugfs.patch
@@ -1,6 +1,6 @@
 --- a/drivers/net/wireless/ath/ath9k/debug.c
 +++ b/drivers/net/wireless/ath/ath9k/debug.c
-@@ -1471,6 +1471,7 @@ int ath9k_init_debug(struct ath_hw *ah)
+@@ -1431,6 +1431,7 @@ int ath9k_init_debug(struct ath_hw *ah)
  
  	ath9k_cmn_debug_base_eeprom(sc->debug.debugfs_phy, sc->sc_ah);
  	ath9k_cmn_debug_modal_eeprom(sc->debug.debugfs_phy, sc->sc_ah);
@@ -82,7 +82,7 @@
  void ath9k_cmn_debug_recv(struct dentry *debugfs_phy,
 --- a/drivers/net/wireless/ath/ath9k/htc_drv_debug.c
 +++ b/drivers/net/wireless/ath/ath9k/htc_drv_debug.c
-@@ -519,6 +519,7 @@ int ath9k_htc_init_debug(struct ath_hw *
+@@ -514,6 +514,7 @@ int ath9k_htc_init_debug(struct ath_hw *
  
  	ath9k_cmn_debug_base_eeprom(priv->debug.debugfs_phy, priv->ah);
  	ath9k_cmn_debug_modal_eeprom(priv->debug.debugfs_phy, priv->ah);
diff --git a/package/kernel/mac80211/patches/ath9k/512-ath9k_channelbw_debugfs.patch b/package/kernel/mac80211/patches/ath9k/512-ath9k_channelbw_debugfs.patch
index 474fb3fdbeb006..3ec2d6ec6eb8df 100644
--- a/package/kernel/mac80211/patches/ath9k/512-ath9k_channelbw_debugfs.patch
+++ b/package/kernel/mac80211/patches/ath9k/512-ath9k_channelbw_debugfs.patch
@@ -1,6 +1,6 @@
 --- a/drivers/net/wireless/ath/ath9k/debug.c
 +++ b/drivers/net/wireless/ath/ath9k/debug.c
-@@ -1472,6 +1472,7 @@ int ath9k_init_debug(struct ath_hw *ah)
+@@ -1432,6 +1432,7 @@ int ath9k_init_debug(struct ath_hw *ah)
  	ath9k_cmn_debug_base_eeprom(sc->debug.debugfs_phy, sc->sc_ah);
  	ath9k_cmn_debug_modal_eeprom(sc->debug.debugfs_phy, sc->sc_ah);
  	ath9k_cmn_debug_eeprom(sc->debug.debugfs_phy, sc->sc_ah);
@@ -137,7 +137,7 @@
 +EXPORT_SYMBOL(ath9k_cmn_debug_chanbw);
 --- a/drivers/net/wireless/ath/ath9k/htc_drv_debug.c
 +++ b/drivers/net/wireless/ath/ath9k/htc_drv_debug.c
-@@ -520,6 +520,7 @@ int ath9k_htc_init_debug(struct ath_hw *
+@@ -515,6 +515,7 @@ int ath9k_htc_init_debug(struct ath_hw *
  	ath9k_cmn_debug_base_eeprom(priv->debug.debugfs_phy, priv->ah);
  	ath9k_cmn_debug_modal_eeprom(priv->debug.debugfs_phy, priv->ah);
  	ath9k_cmn_debug_eeprom(priv->debug.debugfs_phy, priv->ah);
diff --git a/package/kernel/mac80211/patches/ath9k/530-ath9k_extra_leds.patch b/package/kernel/mac80211/patches/ath9k/530-ath9k_extra_leds.patch
index 9568b091de3c13..1b2d4cb5d41b56 100644
--- a/package/kernel/mac80211/patches/ath9k/530-ath9k_extra_leds.patch
+++ b/package/kernel/mac80211/patches/ath9k/530-ath9k_extra_leds.patch
@@ -192,7 +192,7 @@
  #endif
 --- a/drivers/net/wireless/ath/ath9k/debug.c
 +++ b/drivers/net/wireless/ath/ath9k/debug.c
-@@ -128,6 +128,61 @@ static const struct file_operations fops
+@@ -123,6 +123,61 @@ static const struct file_operations fops
  
  #define DMA_BUF_LEN 1024
  
@@ -254,7 +254,7 @@
  
  static ssize_t read_file_ani(struct file *file, char __user *user_buf,
  			     size_t count, loff_t *ppos)
-@@ -1432,6 +1487,10 @@ int ath9k_init_debug(struct ath_hw *ah)
+@@ -1392,6 +1447,10 @@ int ath9k_init_debug(struct ath_hw *ah)
  	ath9k_tx99_init_debug(sc);
  	ath9k_cmn_spectral_init_debug(&sc->spec_priv, sc->debug.debugfs_phy);
  
diff --git a/package/kernel/mac80211/patches/ath9k/542-ath9k_debugfs_diag.patch b/package/kernel/mac80211/patches/ath9k/542-ath9k_debugfs_diag.patch
index c54dbbb1884521..f00ce5f3dca4a7 100644
--- a/package/kernel/mac80211/patches/ath9k/542-ath9k_debugfs_diag.patch
+++ b/package/kernel/mac80211/patches/ath9k/542-ath9k_debugfs_diag.patch
@@ -1,6 +1,6 @@
 --- a/drivers/net/wireless/ath/ath9k/debug.c
 +++ b/drivers/net/wireless/ath/ath9k/debug.c
-@@ -1468,6 +1468,50 @@ void ath9k_deinit_debug(struct ath_softc
+@@ -1428,6 +1428,50 @@ void ath9k_deinit_debug(struct ath_softc
  	ath9k_cmn_spectral_deinit_debug(&sc->spec_priv);
  }
  
@@ -51,7 +51,7 @@
  int ath9k_init_debug(struct ath_hw *ah)
  {
  	struct ath_common *common = ath9k_hw_common(ah);
-@@ -1491,6 +1535,8 @@ int ath9k_init_debug(struct ath_hw *ah)
+@@ -1451,6 +1495,8 @@ int ath9k_init_debug(struct ath_hw *ah)
  	debugfs_create_file("gpio_led", S_IWUSR,
  			   sc->debug.debugfs_phy, sc, &fops_gpio_led);
  #endif
diff --git a/package/kernel/mac80211/patches/build/060-no_local_ssb_bcma.patch b/package/kernel/mac80211/patches/build/060-no_local_ssb_bcma.patch
index 451d0b79fcc854..2a0f9ede420c30 100644
--- a/package/kernel/mac80211/patches/build/060-no_local_ssb_bcma.patch
+++ b/package/kernel/mac80211/patches/build/060-no_local_ssb_bcma.patch
@@ -1,6 +1,6 @@
 --- a/local-symbols
 +++ b/local-symbols
-@@ -491,43 +491,6 @@ USB_VL600=
+@@ -493,43 +493,6 @@ USB_VL600=
  USB_NET_CH9200=
  USB_NET_AQC111=
  USB_RTL8153_ECM=
@@ -171,7 +171,7 @@
  	depends on CORDIC
 --- a/Kconfig.local
 +++ b/Kconfig.local
-@@ -1477,117 +1477,6 @@ config BACKPORTED_USB_NET_AQC111
+@@ -1483,117 +1483,6 @@ config BACKPORTED_USB_NET_AQC111
  config BACKPORTED_USB_RTL8153_ECM
  	tristate
  	default USB_RTL8153_ECM
diff --git a/package/kernel/mac80211/patches/build/080-resv_start_op.patch b/package/kernel/mac80211/patches/build/080-resv_start_op.patch
index 802a0e3fc8af3c..bbd9018bdf0787 100644
--- a/package/kernel/mac80211/patches/build/080-resv_start_op.patch
+++ b/package/kernel/mac80211/patches/build/080-resv_start_op.patch
@@ -12,7 +12,7 @@
  };
 --- a/net/wireless/nl80211.c
 +++ b/net/wireless/nl80211.c
-@@ -17509,7 +17509,9 @@ static struct genl_family nl80211_fam __
+@@ -17551,7 +17551,9 @@ static struct genl_family nl80211_fam __
  	.n_ops = ARRAY_SIZE(nl80211_ops),
  	.small_ops = nl80211_small_ops,
  	.n_small_ops = ARRAY_SIZE(nl80211_small_ops),
diff --git a/package/kernel/mac80211/patches/build/210-revert-split-op.patch b/package/kernel/mac80211/patches/build/210-revert-split-op.patch
index a1fae5e07da561..4f1f8a7795a2eb 100644
--- a/package/kernel/mac80211/patches/build/210-revert-split-op.patch
+++ b/package/kernel/mac80211/patches/build/210-revert-split-op.patch
@@ -1,6 +1,6 @@
 --- a/net/wireless/nl80211.c
 +++ b/net/wireless/nl80211.c
-@@ -16400,8 +16400,7 @@ static u32 nl80211_internal_flags[] = {
+@@ -16442,8 +16442,7 @@ static u32 nl80211_internal_flags[] = {
  #undef SELECTOR
  };
  
@@ -10,7 +10,7 @@
  			    struct genl_info *info)
  {
  	struct cfg80211_registered_device *rdev = NULL;
-@@ -16502,8 +16501,7 @@ out_unlock:
+@@ -16544,8 +16543,7 @@ out_unlock:
  	return err;
  }
  
diff --git a/package/kernel/mac80211/patches/mwl/950-mwifiex-Print-stringified-name-of-command-in-error-l.patch b/package/kernel/mac80211/patches/mwl/950-mwifiex-Print-stringified-name-of-command-in-error-l.patch
index 628b9f8a1237cc..f4d97eeee2b9eb 100644
--- a/package/kernel/mac80211/patches/mwl/950-mwifiex-Print-stringified-name-of-command-in-error-l.patch
+++ b/package/kernel/mac80211/patches/mwl/950-mwifiex-Print-stringified-name-of-command-in-error-l.patch
@@ -152,7 +152,7 @@ Signed-off-by: Pali Rohár <pali@kernel.org>
  
 --- a/drivers/net/wireless/marvell/mwifiex/main.h
 +++ b/drivers/net/wireless/marvell/mwifiex/main.h
-@@ -1100,6 +1100,8 @@ void mwifiex_cancel_all_pending_cmd(stru
+@@ -1086,6 +1086,8 @@ void mwifiex_cancel_all_pending_cmd(stru
  void mwifiex_cancel_pending_scan_cmd(struct mwifiex_adapter *adapter);
  void mwifiex_cancel_scan(struct mwifiex_adapter *adapter);
  
@@ -177,7 +177,7 @@ Signed-off-by: Pali Rohár <pali@kernel.org>
  		adapter->cmd_wait_q.status = -1;
 --- a/drivers/net/wireless/marvell/mwifiex/uap_cmd.c
 +++ b/drivers/net/wireless/marvell/mwifiex/uap_cmd.c
-@@ -794,7 +794,8 @@ int mwifiex_uap_prepare_cmd(struct mwifi
+@@ -802,7 +802,8 @@ int mwifiex_uap_prepare_cmd(struct mwifi
  		break;
  	default:
  		mwifiex_dbg(priv->adapter, ERROR,
diff --git a/package/kernel/mac80211/patches/rt2x00/000-v6.6-wifi-rt2x00-correct-MAC_SYS_CTRL-register-RX-mask-i.patch b/package/kernel/mac80211/patches/rt2x00/000-v6.6-wifi-rt2x00-correct-MAC_SYS_CTRL-register-RX-mask-i.patch
deleted file mode 100644
index c84b5a140840e4..00000000000000
--- a/package/kernel/mac80211/patches/rt2x00/000-v6.6-wifi-rt2x00-correct-MAC_SYS_CTRL-register-RX-mask-i.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From 186f2432741f6d28d86ff723ac7830446affddfc Mon Sep 17 00:00:00 2001
-From: Shiji Yang <yangshiji66@outlook.com>
-Date: Sat, 5 Aug 2023 17:17:28 +0800
-Subject: wifi: rt2x00: correct MAC_SYS_CTRL register RX mask in R-Calibration
-
-For MAC_SYS_CTRL register, Bit[2] controls MAC_TX_EN and Bit[3]
-controls MAC_RX_EN (Bit index starts from 0). Therefore, 0x08 is
-the correct mask for RX.
-
-Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
-Acked-by: Stanislaw Gruszka <stf_xl@wp.pl>
-Signed-off-by: Kalle Valo <kvalo@kernel.org>
-Link: https://lore.kernel.org/r/TYAP286MB03150B571B67B896A504AC34BC0EA@TYAP286MB0315.JPNP286.PROD.OUTLOOK.COM
----
- drivers/net/wireless/ralink/rt2x00/rt2800lib.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
-+++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
-@@ -8561,7 +8561,7 @@ static void rt2800_r_calibration(struct
- 		rt2x00_warn(rt2x00dev, "Wait MAC Tx Status to MAX !!!\n");
- 
- 	maccfg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
--	maccfg &= (~0x04);
-+	maccfg &= (~0x08);
- 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, maccfg);
- 
- 	if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_RX)))
diff --git a/package/kernel/mac80211/patches/rt2x00/001-v6.6-wifi-rt2x00-limit-MT7620-TX-power-based-on-eeprom.patch b/package/kernel/mac80211/patches/rt2x00/001-v6.6-wifi-rt2x00-limit-MT7620-TX-power-based-on-eeprom.patch
deleted file mode 100644
index aa843d4219878d..00000000000000
--- a/package/kernel/mac80211/patches/rt2x00/001-v6.6-wifi-rt2x00-limit-MT7620-TX-power-based-on-eeprom.patch
+++ /dev/null
@@ -1,115 +0,0 @@
-From 821b5192c955144bd2f0aeea6cd153e1aedd16e1 Mon Sep 17 00:00:00 2001
-From: Shiji Yang <yangshiji66@outlook.com>
-Date: Fri, 11 Aug 2023 14:34:54 +0800
-Subject: wifi: rt2x00: limit MT7620 TX power based on eeprom calibration
-
-In the vendor driver, the current channel power is queried from
-EEPROM_TXPOWER_BG1 and EEPROM_TXPOWER_BG2. And then the mixed value
-will be written into the low half-word of the TX_ALC_CFG_0 register.
-The high half-word of the TX_ALC_CFG_0 is a fixed value 0x2f2f.
-
-We can't get the accurate TX power. Based on my tests and the new
-MediaTek mt76 driver source code, the real TX power is approximately
-equal to channel_power + (max) rate_power. Usually max rate_power is
-the gain of the OFDM 6M rate, which can be readed from the offset
-EEPROM_TXPOWER_BYRATE +1.
-
-Based on these eeprom values, this patch adds basic TX power control
-for the MT7620 and limits its maximum TX power. This can avoid the
-link speed decrease caused by chip overheating. rt2800_config_alc()
-function has also been renamed to rt2800_config_alc_rt6352() because
-it's only used by RT6352 (MT7620).
-
-Notice:
-It's still need some work to sync the max channel power to the user
-interface. This part is missing from the rt2x00 driver framework. If
-we set the power exceed the calibration value, it won't take effect.
-
-Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
-Acked-by: Stanislaw Gruszka <stf_xl@wp.pl>
-Signed-off-by: Kalle Valo <kvalo@kernel.org>
-Link: https://lore.kernel.org/r/TYAP286MB03159090ED14044215E59FD6BC10A@TYAP286MB0315.JPNP286.PROD.OUTLOOK.COM
----
- drivers/net/wireless/ralink/rt2x00/rt2800lib.c | 57 ++++++++++++++++++--------
- 1 file changed, 40 insertions(+), 17 deletions(-)
-
---- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
-+++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
-@@ -3865,28 +3865,51 @@ static void rt2800_config_channel_rf7620
- 	}
- }
- 
--static void rt2800_config_alc(struct rt2x00_dev *rt2x00dev,
--			      struct ieee80211_channel *chan,
--			      int power_level) {
--	u16 eeprom, target_power, max_power;
-+static void rt2800_config_alc_rt6352(struct rt2x00_dev *rt2x00dev,
-+				     struct ieee80211_channel *chan,
-+				     int power_level)
-+{
-+	int cur_channel = rt2x00dev->rf_channel;
-+	u16 eeprom, chan_power, rate_power, target_power;
-+	u16 tx_power[2];
-+	s8 *power_group[2];
- 	u32 mac_sys_ctrl;
--	u32 reg;
-+	u32 cnt, reg;
- 	u8 bbp;
- 
--	/* hardware unit is 0.5dBm, limited to 23.5dBm */
--	power_level *= 2;
--	if (power_level > 0x2f)
--		power_level = 0x2f;
--
--	max_power = chan->max_power * 2;
--	if (max_power > 0x2f)
--		max_power = 0x2f;
-+	if (WARN_ON(cur_channel < 1 || cur_channel > 14))
-+		return;
-+
-+	/* get per chain power, 2 chains in total, unit is 0.5dBm */
-+	power_level = (power_level - 3) * 2;
-+
-+	/* We can't get the accurate TX power. Based on some tests, the real
-+	 * TX power is approximately equal to channel_power + (max)rate_power.
-+	 * Usually max rate_power is the gain of the OFDM 6M rate. The antenna
-+	 * gain and externel PA gain are not included as we are unable to
-+	 * obtain these values.
-+	 */
-+	rate_power = rt2800_eeprom_read_from_array(rt2x00dev,
-+						   EEPROM_TXPOWER_BYRATE, 1);
-+	rate_power &= 0x3f;
-+	power_level -= rate_power;
-+	if (power_level < 1)
-+		power_level = 1;
-+
-+	power_group[0] = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
-+	power_group[1] = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
-+	for (cnt = 0; cnt < 2; cnt++) {
-+		chan_power = power_group[cnt][cur_channel - 1];
-+		if (chan_power >= 0x20 || chan_power == 0)
-+			chan_power = 0x10;
-+		tx_power[cnt] = power_level < chan_power ? power_level : chan_power;
-+	}
- 
- 	reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_0);
--	rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_0, power_level);
--	rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_1, power_level);
--	rt2x00_set_field32(&reg, TX_ALC_CFG_0_LIMIT_0, max_power);
--	rt2x00_set_field32(&reg, TX_ALC_CFG_0_LIMIT_1, max_power);
-+	rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_0, tx_power[0]);
-+	rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_1, tx_power[1]);
-+	rt2x00_set_field32(&reg, TX_ALC_CFG_0_LIMIT_0, 0x2f);
-+	rt2x00_set_field32(&reg, TX_ALC_CFG_0_LIMIT_1, 0x2f);
- 
- 	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
- 	if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_INTERNAL_TX_ALC)) {
-@@ -5268,7 +5291,7 @@ static void rt2800_config_txpower_rt6352
- 	rt2x00_set_field32(&pwreg, TX_PWR_CFG_9B_STBC_MCS7, t);
- 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, pwreg);
- 
--	rt2800_config_alc(rt2x00dev, chan, power_level);
-+	rt2800_config_alc_rt6352(rt2x00dev, chan, power_level);
- 
- 	/* TODO: temperature compensation code! */
- }
diff --git a/package/kernel/mac80211/patches/rt2x00/602-01-wifi-rt2x00-Add-support-for-loading-EEPROM-from-user.patch b/package/kernel/mac80211/patches/rt2x00/602-01-wifi-rt2x00-Add-support-for-loading-EEPROM-from-user.patch
index 5040b5af621ea1..8b04473dbe0191 100644
--- a/package/kernel/mac80211/patches/rt2x00/602-01-wifi-rt2x00-Add-support-for-loading-EEPROM-from-user.patch
+++ b/package/kernel/mac80211/patches/rt2x00/602-01-wifi-rt2x00-Add-support-for-loading-EEPROM-from-user.patch
@@ -21,7 +21,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
 
 --- a/local-symbols
 +++ b/local-symbols
-@@ -350,6 +350,7 @@ RT2X00_LIB_FIRMWARE=
+@@ -352,6 +352,7 @@ RT2X00_LIB_FIRMWARE=
  RT2X00_LIB_CRYPTO=
  RT2X00_LIB_LEDS=
  RT2X00_LIB_DEBUGFS=
diff --git a/package/kernel/mac80211/patches/subsys/001-wifi-mac80211-do-not-pass-ap_vlan-vif-pointer-to-dri.patch b/package/kernel/mac80211/patches/subsys/001-wifi-mac80211-do-not-pass-ap_vlan-vif-pointer-to-dri.patch
deleted file mode 100644
index 43724aee1aeb84..00000000000000
--- a/package/kernel/mac80211/patches/subsys/001-wifi-mac80211-do-not-pass-ap_vlan-vif-pointer-to-dri.patch
+++ /dev/null
@@ -1,64 +0,0 @@
-From ee0db868ee4d88493dfdc82f59e3b4e449ddddd5 Mon Sep 17 00:00:00 2001
-From: Oldřich Jedlička <oldium.pro@gmail.com>
-Date: Sat, 4 Nov 2023 15:13:33 +0100
-Subject: wifi: mac80211: do not pass AP_VLAN vif pointer to drivers during
- flush
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-[ Upstream commit 3e3a2b645c043f7e3e488d5011478cefb69bbe8b ]
-
-This fixes WARN_ONs when using AP_VLANs after station removal. The flush
-call passed AP_VLAN vif to driver, but because these vifs are virtual and
-not registered with drivers, we need to translate to the correct AP vif
-first.
-
-Closes: https://github.com/openwrt/openwrt/issues/12420
-Fixes: 0b75a1b1e42e ("wifi: mac80211: flush queues on STA removal")
-Fixes: d00800a289c9 ("wifi: mac80211: add flush_sta method")
-Tested-by: Konstantin Demin <rockdrilla@gmail.com>
-Tested-by: Koen Vandeputte <koen.vandeputte@citymesh.com>
-Signed-off-by: Oldřich Jedlička <oldium.pro@gmail.com>
-Link: https://lore.kernel.org/r/20231104141333.3710-1-oldium.pro@gmail.com
-Signed-off-by: Johannes Berg <johannes.berg@intel.com>
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- net/mac80211/driver-ops.h | 9 +++++++--
- 1 file changed, 7 insertions(+), 2 deletions(-)
-
---- a/net/mac80211/driver-ops.h
-+++ b/net/mac80211/driver-ops.h
-@@ -23,7 +23,7 @@
- static inline struct ieee80211_sub_if_data *
- get_bss_sdata(struct ieee80211_sub_if_data *sdata)
- {
--	if (sdata->vif.type == NL80211_IFTYPE_AP_VLAN)
-+	if (sdata && sdata->vif.type == NL80211_IFTYPE_AP_VLAN)
- 		sdata = container_of(sdata->bss, struct ieee80211_sub_if_data,
- 				     u.ap);
- 
-@@ -638,10 +638,13 @@ static inline void drv_flush(struct ieee
- 			     struct ieee80211_sub_if_data *sdata,
- 			     u32 queues, bool drop)
- {
--	struct ieee80211_vif *vif = sdata ? &sdata->vif : NULL;
-+	struct ieee80211_vif *vif;
- 
- 	might_sleep();
- 
-+	sdata = get_bss_sdata(sdata);
-+	vif = sdata ? &sdata->vif : NULL;
-+
- 	if (sdata && !check_sdata_in_driver(sdata))
- 		return;
- 
-@@ -657,6 +660,8 @@ static inline void drv_flush_sta(struct
- {
- 	might_sleep();
- 
-+	sdata = get_bss_sdata(sdata);
-+
- 	if (sdata && !check_sdata_in_driver(sdata))
- 		return;
- 
diff --git a/package/kernel/mac80211/patches/subsys/110-mac80211_keep_keys_on_stop_ap.patch b/package/kernel/mac80211/patches/subsys/110-mac80211_keep_keys_on_stop_ap.patch
index e3349dabd0b9c7..7bf99bec286674 100644
--- a/package/kernel/mac80211/patches/subsys/110-mac80211_keep_keys_on_stop_ap.patch
+++ b/package/kernel/mac80211/patches/subsys/110-mac80211_keep_keys_on_stop_ap.patch
@@ -9,7 +9,7 @@ Used for AP+STA support in OpenWrt - preserve AP mode keys across STA reconnect
 
 --- a/net/mac80211/cfg.c
 +++ b/net/mac80211/cfg.c
-@@ -1632,7 +1632,6 @@ static int ieee80211_stop_ap(struct wiph
+@@ -1635,7 +1635,6 @@ static int ieee80211_stop_ap(struct wiph
  	link_conf->bssid_indicator = 0;
  
  	__sta_info_flush(sdata, true);
diff --git a/package/kernel/mac80211/patches/subsys/130-disable_auto_vif.patch b/package/kernel/mac80211/patches/subsys/130-disable_auto_vif.patch
index 9d8f781ac41ffa..43507f2985e4bb 100644
--- a/package/kernel/mac80211/patches/subsys/130-disable_auto_vif.patch
+++ b/package/kernel/mac80211/patches/subsys/130-disable_auto_vif.patch
@@ -1,6 +1,6 @@
 --- a/net/mac80211/main.c
 +++ b/net/mac80211/main.c
-@@ -1396,24 +1396,6 @@ int ieee80211_register_hw(struct ieee802
+@@ -1393,24 +1393,6 @@ int ieee80211_register_hw(struct ieee802
  	debugfs_hw_add(local);
  	rate_control_add_debugfs(local);
  
diff --git a/package/kernel/mac80211/patches/subsys/210-ap_scan.patch b/package/kernel/mac80211/patches/subsys/210-ap_scan.patch
index 25b844a21b2ec9..1e9676fd0b69e8 100644
--- a/package/kernel/mac80211/patches/subsys/210-ap_scan.patch
+++ b/package/kernel/mac80211/patches/subsys/210-ap_scan.patch
@@ -8,7 +8,7 @@ Subject: [PATCH] mac80211: allow scans in access point mode (for site survey)
 
 --- a/net/mac80211/cfg.c
 +++ b/net/mac80211/cfg.c
-@@ -2843,6 +2843,8 @@ static int ieee80211_scan(struct wiphy *
+@@ -2847,6 +2847,8 @@ static int ieee80211_scan(struct wiphy *
  		 */
  		fallthrough;
  	case NL80211_IFTYPE_AP:
diff --git a/package/kernel/mac80211/patches/subsys/301-mac80211-sta-randomize-BA-session-dialog-token-alloc.patch b/package/kernel/mac80211/patches/subsys/301-mac80211-sta-randomize-BA-session-dialog-token-alloc.patch
index ffa5c17e487fe6..ec1e1d12ebbd67 100644
--- a/package/kernel/mac80211/patches/subsys/301-mac80211-sta-randomize-BA-session-dialog-token-alloc.patch
+++ b/package/kernel/mac80211/patches/subsys/301-mac80211-sta-randomize-BA-session-dialog-token-alloc.patch
@@ -28,7 +28,7 @@ Signed-off-by: Johannes Berg <johannes.berg@intel.com>
 
 --- a/net/mac80211/sta_info.c
 +++ b/net/mac80211/sta_info.c
-@@ -558,6 +558,7 @@ __sta_info_alloc(struct ieee80211_sub_if
+@@ -561,6 +561,7 @@ __sta_info_alloc(struct ieee80211_sub_if
  	INIT_WORK(&sta->drv_deliver_wk, sta_deliver_ps_frames);
  	INIT_WORK(&sta->ampdu_mlme.work, ieee80211_ba_session_work);
  	mutex_init(&sta->ampdu_mlme.mtx);
diff --git a/package/kernel/mac80211/patches/subsys/305-mac80211-increase-quantum-for-airtime-scheduler.patch b/package/kernel/mac80211/patches/subsys/305-mac80211-increase-quantum-for-airtime-scheduler.patch
index a27925e64ee77b..e4575ca7ba7452 100644
--- a/package/kernel/mac80211/patches/subsys/305-mac80211-increase-quantum-for-airtime-scheduler.patch
+++ b/package/kernel/mac80211/patches/subsys/305-mac80211-increase-quantum-for-airtime-scheduler.patch
@@ -23,7 +23,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
 --- a/net/mac80211/tx.c
 +++ b/net/mac80211/tx.c
-@@ -4059,7 +4059,7 @@ struct ieee80211_txq *ieee80211_next_txq
+@@ -4060,7 +4060,7 @@ struct ieee80211_txq *ieee80211_next_txq
  
  		if (deficit < 0)
  			sta->airtime[txqi->txq.ac].deficit +=
@@ -32,7 +32,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  		if (deficit < 0 || !aql_check) {
  			list_move_tail(&txqi->schedule_order,
-@@ -4202,7 +4202,8 @@ bool ieee80211_txq_may_transmit(struct i
+@@ -4203,7 +4203,8 @@ bool ieee80211_txq_may_transmit(struct i
  		}
  		sta = container_of(iter->txq.sta, struct sta_info, sta);
  		if (ieee80211_sta_deficit(sta, ac) < 0)
@@ -42,7 +42,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  		list_move_tail(&iter->schedule_order, &local->active_txqs[ac]);
  	}
  
-@@ -4210,7 +4211,7 @@ bool ieee80211_txq_may_transmit(struct i
+@@ -4211,7 +4212,7 @@ bool ieee80211_txq_may_transmit(struct i
  	if (sta->airtime[ac].deficit >= 0)
  		goto out;
  
diff --git a/package/kernel/mac80211/patches/subsys/310-mac80211-split-mesh-fast-tx-cache-into-local-proxied.patch b/package/kernel/mac80211/patches/subsys/310-mac80211-split-mesh-fast-tx-cache-into-local-proxied.patch
index f362751e0a3ba4..4853cef723171e 100644
--- a/package/kernel/mac80211/patches/subsys/310-mac80211-split-mesh-fast-tx-cache-into-local-proxied.patch
+++ b/package/kernel/mac80211/patches/subsys/310-mac80211-split-mesh-fast-tx-cache-into-local-proxied.patch
@@ -82,7 +82,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  	struct ieee80211_fast_tx fast_tx;
  	u8 hdr[sizeof(struct ieee80211s_hdr) + sizeof(rfc1042_header)];
-@@ -334,7 +358,8 @@ void mesh_path_tx_root_frame(struct ieee
+@@ -333,7 +357,8 @@ void mesh_path_tx_root_frame(struct ieee
  
  bool mesh_action_is_path_sel(struct ieee80211_mgmt *mgmt);
  struct ieee80211_mesh_fast_tx *
@@ -175,12 +175,12 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 +	ether_addr_copy(key.addr, addr);
  	cache = &sdata->u.mesh.tx_cache;
  	spin_lock_bh(&cache->walk_lock);
--	entry = rhashtable_lookup(&cache->rht, addr, fast_tx_rht_params);
+-	entry = rhashtable_lookup_fast(&cache->rht, addr, fast_tx_rht_params);
 -	if (entry)
 -		mesh_fast_tx_entry_free(cache, entry);
 +	for (i = MESH_FAST_TX_TYPE_LOCAL; i < MESH_FAST_TX_TYPE_FORWARDED; i++) {
 +		key.type = i;
-+		entry = rhashtable_lookup(&cache->rht, &key, fast_tx_rht_params);
++		entry = rhashtable_lookup_fast(&cache->rht, &key, fast_tx_rht_params);
 +		if (entry)
 +			mesh_fast_tx_entry_free(cache, entry);
 +	}
@@ -189,7 +189,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
 --- a/net/mac80211/rx.c
 +++ b/net/mac80211/rx.c
-@@ -2727,7 +2727,10 @@ ieee80211_rx_mesh_fast_forward(struct ie
+@@ -2726,7 +2726,10 @@ ieee80211_rx_mesh_fast_forward(struct ie
  			       struct sk_buff *skb, int hdrlen)
  {
  	struct ieee80211_if_mesh *ifmsh = &sdata->u.mesh;
@@ -201,7 +201,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	struct ieee80211s_hdr *mesh_hdr;
  	struct tid_ampdu_tx *tid_tx;
  	struct sta_info *sta;
-@@ -2736,9 +2739,13 @@ ieee80211_rx_mesh_fast_forward(struct ie
+@@ -2735,9 +2738,13 @@ ieee80211_rx_mesh_fast_forward(struct ie
  
  	mesh_hdr = (struct ieee80211s_hdr *)(skb->data + sizeof(eth));
  	if ((mesh_hdr->flags & MESH_FLAGS_AE) == MESH_FLAGS_AE_A5_A6)
diff --git a/package/kernel/mac80211/patches/subsys/311-mac80211-fix-mesh-id-corruption-on-32-bit-systems.patch b/package/kernel/mac80211/patches/subsys/311-mac80211-fix-mesh-id-corruption-on-32-bit-systems.patch
deleted file mode 100644
index c0c774a89d5bb9..00000000000000
--- a/package/kernel/mac80211/patches/subsys/311-mac80211-fix-mesh-id-corruption-on-32-bit-systems.patch
+++ /dev/null
@@ -1,62 +0,0 @@
-From: Felix Fietkau <nbd@nbd.name>
-Date: Tue, 12 Sep 2023 15:09:27 +0200
-Subject: [PATCH] mac80211: fix mesh id corruption on 32 bit systems
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Since the changed field size was increased to u64, mesh_bss_info_changed
-pulls invalid bits from the first 3 bytes of the mesh id, clears them, and
-passes them on to ieee80211_link_info_change_notify, because
-ifmsh->mbss_changed was not updated to match its size.
-Fix this by turning into ifmsh->mbss_changed into an unsigned long array with
-64 bit size.
-
-Fixes: 15ddba5f4311 ("wifi: mac80211: consistently use u64 for BSS changes")
-Reported-by: Thomas Hühn <thomas.huehn@hs-nordhausen.de>
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
-
---- a/net/mac80211/ieee80211_i.h
-+++ b/net/mac80211/ieee80211_i.h
-@@ -678,7 +678,7 @@ struct ieee80211_if_mesh {
- 	struct timer_list mesh_path_root_timer;
- 
- 	unsigned long wrkq_flags;
--	unsigned long mbss_changed;
-+	unsigned long mbss_changed[64 / BITS_PER_LONG];
- 
- 	bool userspace_handles_dfs;
- 
---- a/net/mac80211/mesh.c
-+++ b/net/mac80211/mesh.c
-@@ -1181,7 +1181,7 @@ void ieee80211_mbss_info_change_notify(s
- 
- 	/* if we race with running work, worst case this work becomes a noop */
- 	for_each_set_bit(bit, &bits, sizeof(changed) * BITS_PER_BYTE)
--		set_bit(bit, &ifmsh->mbss_changed);
-+		set_bit(bit, ifmsh->mbss_changed);
- 	set_bit(MESH_WORK_MBSS_CHANGED, &ifmsh->wrkq_flags);
- 	wiphy_work_queue(sdata->local->hw.wiphy, &sdata->work);
- }
-@@ -1263,7 +1263,7 @@ void ieee80211_stop_mesh(struct ieee8021
- 
- 	/* clear any mesh work (for next join) we may have accrued */
- 	ifmsh->wrkq_flags = 0;
--	ifmsh->mbss_changed = 0;
-+	memset(ifmsh->mbss_changed, 0, sizeof(ifmsh->mbss_changed));
- 
- 	local->fif_other_bss--;
- 	atomic_dec(&local->iff_allmultis);
-@@ -1730,9 +1730,9 @@ static void mesh_bss_info_changed(struct
- 	u32 bit;
- 	u64 changed = 0;
- 
--	for_each_set_bit(bit, &ifmsh->mbss_changed,
-+	for_each_set_bit(bit, ifmsh->mbss_changed,
- 			 sizeof(changed) * BITS_PER_BYTE) {
--		clear_bit(bit, &ifmsh->mbss_changed);
-+		clear_bit(bit, ifmsh->mbss_changed);
- 		changed |= BIT(bit);
- 	}
- 
diff --git a/package/kernel/mac80211/patches/subsys/312-wifi-cfg80211-annotate-iftype_data-pointer-with-spar.patch b/package/kernel/mac80211/patches/subsys/312-wifi-cfg80211-annotate-iftype_data-pointer-with-spar.patch
index 18420a80cf9e84..91ebfc6105f796 100644
--- a/package/kernel/mac80211/patches/subsys/312-wifi-cfg80211-annotate-iftype_data-pointer-with-spar.patch
+++ b/package/kernel/mac80211/patches/subsys/312-wifi-cfg80211-annotate-iftype_data-pointer-with-spar.patch
@@ -57,7 +57,7 @@ Signed-off-by: Johannes Berg <johannes.berg@intel.com>
  
 --- a/drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c
 +++ b/drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c
-@@ -1075,8 +1075,8 @@ static void iwl_init_he_hw_capab(struct
+@@ -1078,8 +1078,8 @@ static void iwl_init_he_hw_capab(struct
  
  	memcpy(iftype_data, iwl_he_eht_capa, sizeof(iwl_he_eht_capa));
  
@@ -70,7 +70,7 @@ Signed-off-by: Johannes Berg <johannes.berg@intel.com>
  		iwl_nvm_fixup_sband_iftd(trans, data, sband, &iftype_data[i],
 --- a/drivers/net/wireless/mediatek/mt76/mt7915/init.c
 +++ b/drivers/net/wireless/mediatek/mt76/mt7915/init.c
-@@ -1119,8 +1119,7 @@ void mt7915_set_stream_he_caps(struct mt
+@@ -1127,8 +1127,7 @@ void mt7915_set_stream_he_caps(struct mt
  		n = mt7915_init_he_caps(phy, NL80211_BAND_2GHZ, data);
  
  		band = &phy->mt76->sband_2g.sband;
@@ -80,7 +80,7 @@ Signed-off-by: Johannes Berg <johannes.berg@intel.com>
  	}
  
  	if (phy->mt76->cap.has_5ghz) {
-@@ -1128,8 +1127,7 @@ void mt7915_set_stream_he_caps(struct mt
+@@ -1136,8 +1135,7 @@ void mt7915_set_stream_he_caps(struct mt
  		n = mt7915_init_he_caps(phy, NL80211_BAND_5GHZ, data);
  
  		band = &phy->mt76->sband_5g.sband;
@@ -90,7 +90,7 @@ Signed-off-by: Johannes Berg <johannes.berg@intel.com>
  	}
  
  	if (phy->mt76->cap.has_6ghz) {
-@@ -1137,8 +1135,7 @@ void mt7915_set_stream_he_caps(struct mt
+@@ -1145,8 +1143,7 @@ void mt7915_set_stream_he_caps(struct mt
  		n = mt7915_init_he_caps(phy, NL80211_BAND_6GHZ, data);
  
  		band = &phy->mt76->sband_6g.sband;
@@ -133,7 +133,7 @@ Signed-off-by: Johannes Berg <johannes.berg@intel.com>
  }
 --- a/drivers/net/wireless/mediatek/mt76/mt7996/init.c
 +++ b/drivers/net/wireless/mediatek/mt76/mt7996/init.c
-@@ -823,8 +823,7 @@ __mt7996_set_stream_he_eht_caps(struct m
+@@ -828,8 +828,7 @@ __mt7996_set_stream_he_eht_caps(struct m
  		n++;
  	}
  
@@ -177,7 +177,7 @@ Signed-off-by: Johannes Berg <johannes.berg@intel.com>
  		kfree(wiphy->bands[band]->channels);
 --- a/drivers/net/wireless/realtek/rtw89/core.c
 +++ b/drivers/net/wireless/realtek/rtw89/core.c
-@@ -3328,8 +3328,7 @@ static void rtw89_init_he_cap(struct rtw
+@@ -3359,8 +3359,7 @@ static void rtw89_init_he_cap(struct rtw
  		idx++;
  	}
  
@@ -187,7 +187,7 @@ Signed-off-by: Johannes Berg <johannes.berg@intel.com>
  }
  
  static int rtw89_core_set_supported_band(struct rtw89_dev *rtwdev)
-@@ -3374,11 +3373,11 @@ err:
+@@ -3405,11 +3404,11 @@ err:
  	hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL;
  	hw->wiphy->bands[NL80211_BAND_6GHZ] = NULL;
  	if (sband_2ghz)
@@ -202,7 +202,7 @@ Signed-off-by: Johannes Berg <johannes.berg@intel.com>
  	kfree(sband_2ghz);
  	kfree(sband_5ghz);
  	kfree(sband_6ghz);
-@@ -3390,11 +3389,11 @@ static void rtw89_core_clr_supported_ban
+@@ -3421,11 +3420,11 @@ static void rtw89_core_clr_supported_ban
  	struct ieee80211_hw *hw = rtwdev->hw;
  
  	if (hw->wiphy->bands[NL80211_BAND_2GHZ])
@@ -219,7 +219,7 @@ Signed-off-by: Johannes Berg <johannes.berg@intel.com>
  	kfree(hw->wiphy->bands[NL80211_BAND_6GHZ]);
 --- a/drivers/net/wireless/realtek/rtw89/regd.c
 +++ b/drivers/net/wireless/realtek/rtw89/regd.c
-@@ -376,7 +376,7 @@ bottom:
+@@ -377,7 +377,7 @@ bottom:
  		return;
  
  	wiphy->bands[NL80211_BAND_6GHZ] = NULL;
@@ -230,7 +230,7 @@ Signed-off-by: Johannes Berg <johannes.berg@intel.com>
  
 --- a/drivers/net/wireless/virtual/mac80211_hwsim.c
 +++ b/drivers/net/wireless/virtual/mac80211_hwsim.c
-@@ -4900,25 +4900,19 @@ static const struct ieee80211_sband_ifty
+@@ -4899,25 +4899,19 @@ static const struct ieee80211_sband_ifty
  
  static void mac80211_hwsim_sband_capab(struct ieee80211_supported_band *sband)
  {
@@ -362,7 +362,7 @@ Signed-off-by: Johannes Berg <johannes.berg@intel.com>
  	}
 --- a/net/mac80211/main.c
 +++ b/net/mac80211/main.c
-@@ -1055,6 +1055,7 @@ int ieee80211_register_hw(struct ieee802
+@@ -1052,6 +1052,7 @@ int ieee80211_register_hw(struct ieee802
  	supp_he = false;
  	supp_eht = false;
  	for (band = 0; band < NUM_NL80211_BANDS; band++) {
@@ -370,7 +370,7 @@ Signed-off-by: Johannes Berg <johannes.berg@intel.com>
  		struct ieee80211_supported_band *sband;
  
  		sband = local->hw.wiphy->bands[band];
-@@ -1101,11 +1102,7 @@ int ieee80211_register_hw(struct ieee802
+@@ -1098,11 +1099,7 @@ int ieee80211_register_hw(struct ieee802
  		supp_ht = supp_ht || sband->ht_cap.ht_supported;
  		supp_vht = supp_vht || sband->vht_cap.vht_supported;
  
@@ -415,7 +415,7 @@ Signed-off-by: Johannes Berg <johannes.berg@intel.com>
   */
  
  #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
-@@ -817,6 +817,7 @@ int wiphy_register(struct wiphy *wiphy)
+@@ -819,6 +819,7 @@ int wiphy_register(struct wiphy *wiphy)
  
  	/* sanity check supported bands/channels */
  	for (band = 0; band < NUM_NL80211_BANDS; band++) {
@@ -423,7 +423,7 @@ Signed-off-by: Johannes Berg <johannes.berg@intel.com>
  		u16 types = 0;
  		bool have_he = false;
  
-@@ -873,14 +874,11 @@ int wiphy_register(struct wiphy *wiphy)
+@@ -875,14 +876,11 @@ int wiphy_register(struct wiphy *wiphy)
  				return -EINVAL;
  		}
  
@@ -441,7 +441,7 @@ Signed-off-by: Johannes Berg <johannes.berg@intel.com>
  			if (WARN_ON(types & iftd->types_mask))
 --- a/net/wireless/nl80211.c
 +++ b/net/wireless/nl80211.c
-@@ -1906,20 +1906,20 @@ static int nl80211_send_band_rateinfo(st
+@@ -1907,20 +1907,20 @@ static int nl80211_send_band_rateinfo(st
  		struct nlattr *nl_iftype_data =
  			nla_nest_start_noflag(msg,
  					      NL80211_BAND_ATTR_IFTYPE_DATA);
diff --git a/package/kernel/mac80211/patches/subsys/313-wifi-cfg80211-export-DFS-CAC-time-and-usable-state-h.patch b/package/kernel/mac80211/patches/subsys/313-wifi-cfg80211-export-DFS-CAC-time-and-usable-state-h.patch
index 78ec030e18b772..a41a906c3c4188 100644
--- a/package/kernel/mac80211/patches/subsys/313-wifi-cfg80211-export-DFS-CAC-time-and-usable-state-h.patch
+++ b/package/kernel/mac80211/patches/subsys/313-wifi-cfg80211-export-DFS-CAC-time-and-usable-state-h.patch
@@ -79,7 +79,7 @@ Signed-off-by: Johannes Berg <johannes.berg@intel.com>
  					u32 center_freq, u32 bandwidth,
 --- a/net/wireless/core.h
 +++ b/net/wireless/core.h
-@@ -469,29 +469,12 @@ int cfg80211_scan(struct cfg80211_regist
+@@ -476,29 +476,12 @@ int cfg80211_scan(struct cfg80211_regist
  
  extern struct work_struct cfg80211_disconnect_work;
  
diff --git a/package/kernel/mac80211/patches/subsys/314-wifi-mac80211-fix-race-condition-on-enabling-fast-xm.patch b/package/kernel/mac80211/patches/subsys/314-wifi-mac80211-fix-race-condition-on-enabling-fast-xm.patch
index 191eb67e8eac9e..12ed2142abca2c 100644
--- a/package/kernel/mac80211/patches/subsys/314-wifi-mac80211-fix-race-condition-on-enabling-fast-xm.patch
+++ b/package/kernel/mac80211/patches/subsys/314-wifi-mac80211-fix-race-condition-on-enabling-fast-xm.patch
@@ -13,7 +13,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/net/mac80211/sta_info.c
 +++ b/net/mac80211/sta_info.c
-@@ -911,6 +911,7 @@ static int sta_info_insert_finish(struct
+@@ -914,6 +914,7 @@ static int sta_info_insert_finish(struct
  
  	if (ieee80211_vif_is_mesh(&sdata->vif))
  		mesh_accept_plinks_update(sdata);
@@ -23,7 +23,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
   out_remove:
 --- a/net/mac80211/tx.c
 +++ b/net/mac80211/tx.c
-@@ -3033,7 +3033,7 @@ void ieee80211_check_fast_xmit(struct st
+@@ -3034,7 +3034,7 @@ void ieee80211_check_fast_xmit(struct st
  	    sdata->vif.type == NL80211_IFTYPE_STATION)
  		goto out;
  
diff --git a/package/kernel/mac80211/patches/subsys/320-cfg80211-allow-grace-period-for-DFS-available-after-.patch b/package/kernel/mac80211/patches/subsys/320-cfg80211-allow-grace-period-for-DFS-available-after-.patch
index 28e2144f7f51ba..ec381303cebe96 100644
--- a/package/kernel/mac80211/patches/subsys/320-cfg80211-allow-grace-period-for-DFS-available-after-.patch
+++ b/package/kernel/mac80211/patches/subsys/320-cfg80211-allow-grace-period-for-DFS-available-after-.patch
@@ -113,7 +113,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  {
 --- a/net/wireless/core.h
 +++ b/net/wireless/core.h
-@@ -474,6 +474,8 @@ void cfg80211_set_dfs_state(struct wiphy
+@@ -481,6 +481,8 @@ void cfg80211_set_dfs_state(struct wiphy
  			    enum nl80211_dfs_state dfs_state);
  
  void cfg80211_dfs_channels_update_work(struct work_struct *work);
@@ -124,7 +124,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
 --- a/net/wireless/mlme.c
 +++ b/net/wireless/mlme.c
-@@ -915,6 +915,8 @@ void cfg80211_dfs_channels_update_work(s
+@@ -930,6 +930,8 @@ void cfg80211_dfs_channels_update_work(s
  			if (c->dfs_state == NL80211_DFS_UNAVAILABLE) {
  				time_dfs_update = IEEE80211_DFS_MIN_NOP_TIME_MS;
  				radar_event = NL80211_RADAR_NOP_FINISHED;
@@ -133,7 +133,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  			} else {
  				if (regulatory_pre_cac_allowed(wiphy) ||
  				    cfg80211_any_wiphy_oper_chan(wiphy, c))
-@@ -922,11 +924,10 @@ void cfg80211_dfs_channels_update_work(s
+@@ -937,11 +939,10 @@ void cfg80211_dfs_channels_update_work(s
  
  				time_dfs_update = REG_PRE_CAC_EXPIRY_GRACE_MS;
  				radar_event = NL80211_RADAR_PRE_CAC_EXPIRED;
diff --git a/package/kernel/mac80211/patches/subsys/330-mac80211-add-AQL-support-for-broadcast-packets.patch b/package/kernel/mac80211/patches/subsys/330-mac80211-add-AQL-support-for-broadcast-packets.patch
new file mode 100644
index 00000000000000..6f64467b664149
--- /dev/null
+++ b/package/kernel/mac80211/patches/subsys/330-mac80211-add-AQL-support-for-broadcast-packets.patch
@@ -0,0 +1,226 @@
+From: Felix Fietkau <nbd@nbd.name>
+Date: Fri, 9 Feb 2024 19:43:40 +0100
+Subject: [PATCH] mac80211: add AQL support for broadcast packets
+
+Excessive broadcast traffic with little competing unicast traffic can easily
+flood hardware queues, leading to throughput issues. Additionally, filling
+the hardware queues with too many packets breaks FQ for broadcast data.
+Fix this by enabling AQL for broadcast packets.
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/include/net/cfg80211.h
++++ b/include/net/cfg80211.h
+@@ -3324,6 +3324,7 @@ enum wiphy_params_flags {
+ /* The per TXQ device queue limit in airtime */
+ #define IEEE80211_DEFAULT_AQL_TXQ_LIMIT_L	5000
+ #define IEEE80211_DEFAULT_AQL_TXQ_LIMIT_H	12000
++#define IEEE80211_DEFAULT_AQL_TXQ_LIMIT_BC	50000
+ 
+ /* The per interface airtime threshold to switch to lower queue limit */
+ #define IEEE80211_AQL_THRESHOLD			24000
+--- a/net/mac80211/debugfs.c
++++ b/net/mac80211/debugfs.c
+@@ -215,11 +215,13 @@ static ssize_t aql_pending_read(struct f
+ 			"VI     %u us\n"
+ 			"BE     %u us\n"
+ 			"BK     %u us\n"
++			"BC/MC  %u us\n"
+ 			"total  %u us\n",
+ 			atomic_read(&local->aql_ac_pending_airtime[IEEE80211_AC_VO]),
+ 			atomic_read(&local->aql_ac_pending_airtime[IEEE80211_AC_VI]),
+ 			atomic_read(&local->aql_ac_pending_airtime[IEEE80211_AC_BE]),
+ 			atomic_read(&local->aql_ac_pending_airtime[IEEE80211_AC_BK]),
++			atomic_read(&local->aql_bc_pending_airtime),
+ 			atomic_read(&local->aql_total_pending_airtime));
+ 	return simple_read_from_buffer(user_buf, count, ppos,
+ 				       buf, len);
+@@ -245,7 +247,8 @@ static ssize_t aql_txq_limit_read(struct
+ 			"VO	%u		%u\n"
+ 			"VI	%u		%u\n"
+ 			"BE	%u		%u\n"
+-			"BK	%u		%u\n",
++			"BK	%u		%u\n"
++			"BC/MC	%u\n",
+ 			local->aql_txq_limit_low[IEEE80211_AC_VO],
+ 			local->aql_txq_limit_high[IEEE80211_AC_VO],
+ 			local->aql_txq_limit_low[IEEE80211_AC_VI],
+@@ -253,7 +256,8 @@ static ssize_t aql_txq_limit_read(struct
+ 			local->aql_txq_limit_low[IEEE80211_AC_BE],
+ 			local->aql_txq_limit_high[IEEE80211_AC_BE],
+ 			local->aql_txq_limit_low[IEEE80211_AC_BK],
+-			local->aql_txq_limit_high[IEEE80211_AC_BK]);
++			local->aql_txq_limit_high[IEEE80211_AC_BK],
++			local->aql_txq_limit_bc);
+ 	return simple_read_from_buffer(user_buf, count, ppos,
+ 				       buf, len);
+ }
+@@ -279,6 +283,11 @@ static ssize_t aql_txq_limit_write(struc
+ 	else
+ 		buf[count] = '\0';
+ 
++	if (sscanf(buf, "mcast %u", &q_limit_low) == 1) {
++		local->aql_txq_limit_bc = q_limit_low;
++		return count;
++	}
++
+ 	if (sscanf(buf, "%u %u %u", &ac, &q_limit_low, &q_limit_high) != 3)
+ 		return -EINVAL;
+ 
+--- a/net/mac80211/ieee80211_i.h
++++ b/net/mac80211/ieee80211_i.h
+@@ -1328,10 +1328,12 @@ struct ieee80211_local {
+ 	spinlock_t handle_wake_tx_queue_lock;
+ 
+ 	u16 airtime_flags;
++	u32 aql_txq_limit_bc;
+ 	u32 aql_txq_limit_low[IEEE80211_NUM_ACS];
+ 	u32 aql_txq_limit_high[IEEE80211_NUM_ACS];
+ 	u32 aql_threshold;
+ 	atomic_t aql_total_pending_airtime;
++	atomic_t aql_bc_pending_airtime;
+ 	atomic_t aql_ac_pending_airtime[IEEE80211_NUM_ACS];
+ 
+ 	const struct ieee80211_ops *ops;
+--- a/net/mac80211/main.c
++++ b/net/mac80211/main.c
+@@ -788,6 +788,7 @@ struct ieee80211_hw *ieee80211_alloc_hw_
+ 	spin_lock_init(&local->rx_path_lock);
+ 	spin_lock_init(&local->queue_stop_reason_lock);
+ 
++	local->aql_txq_limit_bc = IEEE80211_DEFAULT_AQL_TXQ_LIMIT_BC;
+ 	for (i = 0; i < IEEE80211_NUM_ACS; i++) {
+ 		INIT_LIST_HEAD(&local->active_txqs[i]);
+ 		spin_lock_init(&local->active_txq_lock[i]);
+--- a/net/mac80211/sta_info.c
++++ b/net/mac80211/sta_info.c
+@@ -2341,28 +2341,27 @@ void ieee80211_sta_update_pending_airtim
+ 					  struct sta_info *sta, u8 ac,
+ 					  u16 tx_airtime, bool tx_completed)
+ {
++	atomic_t *counter;
+ 	int tx_pending;
+ 
+ 	if (!wiphy_ext_feature_isset(local->hw.wiphy, NL80211_EXT_FEATURE_AQL))
+ 		return;
+ 
+-	if (!tx_completed) {
+-		if (sta)
+-			atomic_add(tx_airtime,
+-				   &sta->airtime[ac].aql_tx_pending);
++	if (sta)
++		counter = &sta->airtime[ac].aql_tx_pending;
++	else
++		counter = &local->aql_bc_pending_airtime;
+ 
++	if (!tx_completed) {
++		atomic_add(tx_airtime, counter);
+ 		atomic_add(tx_airtime, &local->aql_total_pending_airtime);
+ 		atomic_add(tx_airtime, &local->aql_ac_pending_airtime[ac]);
+ 		return;
+ 	}
+ 
+-	if (sta) {
+-		tx_pending = atomic_sub_return(tx_airtime,
+-					       &sta->airtime[ac].aql_tx_pending);
+-		if (tx_pending < 0)
+-			atomic_cmpxchg(&sta->airtime[ac].aql_tx_pending,
+-				       tx_pending, 0);
+-	}
++	tx_pending = atomic_sub_return(tx_airtime, counter);
++	if (tx_pending < 0)
++		atomic_cmpxchg(counter, tx_pending, 0);
+ 
+ 	atomic_sub(tx_airtime, &local->aql_total_pending_airtime);
+ 	tx_pending = atomic_sub_return(tx_airtime,
+--- a/net/mac80211/tx.c
++++ b/net/mac80211/tx.c
+@@ -3958,9 +3958,8 @@ begin:
+ encap_out:
+ 	IEEE80211_SKB_CB(skb)->control.vif = vif;
+ 
+-	if (tx.sta &&
+-	    wiphy_ext_feature_isset(local->hw.wiphy, NL80211_EXT_FEATURE_AQL)) {
+-		bool ampdu = txq->ac != IEEE80211_AC_VO;
++	if (wiphy_ext_feature_isset(local->hw.wiphy, NL80211_EXT_FEATURE_AQL)) {
++		bool ampdu = txq->sta && txq->ac != IEEE80211_AC_VO;
+ 		u32 airtime;
+ 
+ 		airtime = ieee80211_calc_expected_tx_airtime(hw, vif, txq->sta,
+@@ -4026,6 +4025,7 @@ struct ieee80211_txq *ieee80211_next_txq
+ 	struct ieee80211_txq *ret = NULL;
+ 	struct txq_info *txqi = NULL, *head = NULL;
+ 	bool found_eligible_txq = false;
++	bool aql_check;
+ 
+ 	spin_lock_bh(&local->active_txq_lock[ac]);
+ 
+@@ -4049,26 +4049,26 @@ struct ieee80211_txq *ieee80211_next_txq
+ 	if (!head)
+ 		head = txqi;
+ 
++	aql_check = ieee80211_txq_airtime_check(hw, &txqi->txq);
++	if (aql_check)
++		found_eligible_txq = true;
++
+ 	if (txqi->txq.sta) {
+ 		struct sta_info *sta = container_of(txqi->txq.sta,
+ 						    struct sta_info, sta);
+-		bool aql_check = ieee80211_txq_airtime_check(hw, &txqi->txq);
+-		s32 deficit = ieee80211_sta_deficit(sta, txqi->txq.ac);
+-
+-		if (aql_check)
+-			found_eligible_txq = true;
+-
+-		if (deficit < 0)
++		if (ieee80211_sta_deficit(sta, txqi->txq.ac) < 0) {
+ 			sta->airtime[txqi->txq.ac].deficit +=
+ 				sta->airtime_weight << AIRTIME_QUANTUM_SHIFT;
+-
+-		if (deficit < 0 || !aql_check) {
+-			list_move_tail(&txqi->schedule_order,
+-				       &local->active_txqs[txqi->txq.ac]);
+-			goto begin;
++			aql_check = false;
+ 		}
+ 	}
+ 
++	if (!aql_check) {
++		list_move_tail(&txqi->schedule_order,
++				   &local->active_txqs[txqi->txq.ac]);
++		goto begin;
++	}
++
+ 	if (txqi->schedule_round == local->schedule_round[ac])
+ 		goto out;
+ 
+@@ -4133,7 +4133,8 @@ bool ieee80211_txq_airtime_check(struct
+ 		return true;
+ 
+ 	if (!txq->sta)
+-		return true;
++		return atomic_read(&local->aql_bc_pending_airtime) <
++		       local->aql_txq_limit_bc;
+ 
+ 	if (unlikely(txq->tid == IEEE80211_NUM_TIDS))
+ 		return true;
+@@ -4182,15 +4183,15 @@ bool ieee80211_txq_may_transmit(struct i
+ 
+ 	spin_lock_bh(&local->active_txq_lock[ac]);
+ 
+-	if (!txqi->txq.sta)
+-		goto out;
+-
+ 	if (list_empty(&txqi->schedule_order))
+ 		goto out;
+ 
+ 	if (!ieee80211_txq_schedule_airtime_check(local, ac))
+ 		goto out;
+ 
++	if (!txqi->txq.sta)
++		goto out;
++
+ 	list_for_each_entry_safe(iter, tmp, &local->active_txqs[ac],
+ 				 schedule_order) {
+ 		if (iter == txqi)
diff --git a/package/kernel/mac80211/patches/subsys/331-wifi-mac80211-only-call-drv_sta_rc_update-for-upload.patch b/package/kernel/mac80211/patches/subsys/331-wifi-mac80211-only-call-drv_sta_rc_update-for-upload.patch
new file mode 100644
index 00000000000000..167b9e3f7769ab
--- /dev/null
+++ b/package/kernel/mac80211/patches/subsys/331-wifi-mac80211-only-call-drv_sta_rc_update-for-upload.patch
@@ -0,0 +1,25 @@
+From: Felix Fietkau <nbd@nbd.name>
+Date: Wed, 21 Feb 2024 14:41:40 +0100
+Subject: [PATCH] wifi: mac80211: only call drv_sta_rc_update for uploaded
+ stations
+
+When a station has not been uploaded yet, receiving SMPS or channel width
+notification action frames can lead to rate_control_rate_update calling
+drv_sta_rc_update with uninitialized driver private data.
+Fix this by adding a missing check for sta->uploaded.
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/net/mac80211/rate.c
++++ b/net/mac80211/rate.c
+@@ -119,7 +119,8 @@ void rate_control_rate_update(struct iee
+ 		rcu_read_unlock();
+ 	}
+ 
+-	drv_sta_rc_update(local, sta->sdata, &sta->sta, changed);
++	if (sta->uploaded)
++		drv_sta_rc_update(local, sta->sdata, &sta->sta, changed);
+ }
+ 
+ int ieee80211_rate_control_register(const struct rate_control_ops *ops)
diff --git a/package/kernel/mac80211/patches/subsys/400-allow-ibss-mixed.patch b/package/kernel/mac80211/patches/subsys/400-allow-ibss-mixed.patch
index ad24dfda5a7775..7a96f9f2bec503 100644
--- a/package/kernel/mac80211/patches/subsys/400-allow-ibss-mixed.patch
+++ b/package/kernel/mac80211/patches/subsys/400-allow-ibss-mixed.patch
@@ -16,7 +16,7 @@ and we should ignore this.
 
 --- a/net/wireless/core.c
 +++ b/net/wireless/core.c
-@@ -649,21 +649,6 @@ static int wiphy_verify_combinations(str
+@@ -651,21 +651,6 @@ static int wiphy_verify_combinations(str
  				    c->limits[j].max > 1))
  				return -EINVAL;
  
diff --git a/package/kernel/mac80211/patches/subsys/780-avoid-crashing-missing-band.patch b/package/kernel/mac80211/patches/subsys/780-avoid-crashing-missing-band.patch
index 4bbd7860436ef2..6a1fc31d870124 100644
--- a/package/kernel/mac80211/patches/subsys/780-avoid-crashing-missing-band.patch
+++ b/package/kernel/mac80211/patches/subsys/780-avoid-crashing-missing-band.patch
@@ -18,7 +18,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
 
 --- a/net/mac80211/sta_info.c
 +++ b/net/mac80211/sta_info.c
-@@ -2423,6 +2423,13 @@ static void sta_stats_decode_rate(struct
+@@ -2426,6 +2426,13 @@ static void sta_stats_decode_rate(struct
  
  		sband = local->hw.wiphy->bands[band];
  
diff --git a/package/kernel/mt76/Makefile b/package/kernel/mt76/Makefile
index 1fea3bd0e91617..4f0fb5f69d046f 100644
--- a/package/kernel/mt76/Makefile
+++ b/package/kernel/mt76/Makefile
@@ -8,9 +8,9 @@ PKG_LICENSE_FILES:=
 
 PKG_SOURCE_URL:=https://github.com/openwrt/mt76
 PKG_SOURCE_PROTO:=git
-PKG_SOURCE_DATE:=2024-01-18
-PKG_SOURCE_VERSION:=f77188160441d5f77f08dd517632ae3f60c653b0
-PKG_MIRROR_HASH:=133a5e44624fe1933c893ee0b8ac75a847753f3490c26518c2ed9798f9ef53e0
+PKG_SOURCE_DATE:=2024-02-03
+PKG_SOURCE_VERSION:=6124ea9135ed512671933f5520c46842906c78bc
+PKG_MIRROR_HASH:=acc326d7b15c9c72b494ed601300be329553f896e65c7f045e6a09327304c34a
 
 PKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>
 PKG_USE_NINJA:=0
@@ -323,6 +323,12 @@ define KernelPackage/mt7996e
   AUTOLOAD:=$(call AutoProbe,mt7996e)
 endef
 
+define KernelPackage/mt7996-firmware
+  $(KernelPackage/mt76-default)
+  TITLE:=MediaTek MT7996 firmware
+  DEPENDS+=+kmod-mt7996e
+endef
+
 define KernelPackage/mt7925-common
   $(KernelPackage/mt76-default)
   TITLE:=MediaTek MT7925 wireless driver common code
@@ -610,6 +616,17 @@ define KernelPackage/mt7922-firmware/install
 		$(1)/lib/firmware/mediatek
 endef
 
+define KernelPackage/mt7996-firmware/install
+	$(INSTALL_DIR) $(1)/lib/firmware/mediatek/mt7996
+	cp \
+		$(PKG_BUILD_DIR)/firmware/mt7996/mt7996_dsp.bin \
+		$(PKG_BUILD_DIR)/firmware/mt7996/mt7996_eeprom.bin \
+		$(PKG_BUILD_DIR)/firmware/mt7996/mt7996_rom_patch.bin \
+		$(PKG_BUILD_DIR)/firmware/mt7996/mt7996_wa.bin \
+		$(PKG_BUILD_DIR)/firmware/mt7996/mt7996_wm.bin \
+		$(1)/lib/firmware/mediatek/mt7996
+endef
+
 define Package/mt76-test/install
 	mkdir -p $(1)/usr/sbin
 	$(INSTALL_BIN) $(PKG_BUILD_DIR)/tools/mt76-test $(1)/usr/sbin
@@ -654,5 +671,6 @@ $(eval $(call KernelPackage,mt7921e))
 $(eval $(call KernelPackage,mt7925u))
 $(eval $(call KernelPackage,mt7925e))
 $(eval $(call KernelPackage,mt7996e))
+$(eval $(call KernelPackage,mt7996-firmware))
 $(eval $(call KernelPackage,mt76))
 $(eval $(call BuildPackage,mt76-test))
diff --git a/package/kernel/qca-ssdk/Makefile b/package/kernel/qca-ssdk/Makefile
index 2517b80069c3f1..f1fb09c52a2863 100644
--- a/package/kernel/qca-ssdk/Makefile
+++ b/package/kernel/qca-ssdk/Makefile
@@ -1,7 +1,7 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=qca-ssdk
-PKG_RELEASE:=4
+PKG_RELEASE:=5
 
 PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/qca-ssdk.git
 PKG_SOURCE_PROTO:=git
@@ -46,13 +46,17 @@ MAKE_FLAGS+= \
 	SoC=$(CONFIG_TARGET_SUBTARGET) \
 	PTP_FEATURE=disable SWCONFIG_FEATURE=disable \
 	ISISC_ENABLE=disable IN_QCA803X_PHY=FALSE \
-	IN_QCA808X_PHY=FALSE \
+	IN_QCA808X_PHY=FALSE IN_MALIBU_PHY=FALSE \
 	$(LNX_CONFIG_OPTS)
 
 ifeq ($(CONFIG_TARGET_SUBTARGET), "ipq807x")
     MAKE_FLAGS+= CHIP_TYPE=HPPE
 endif
 
+ifeq ($(CONFIG_TARGET_SUBTARGET), "ipq60xx")
+    MAKE_FLAGS+= CHIP_TYPE=CPPE
+endif
+
 define Build/InstallDev
 	$(INSTALL_DIR) $(1)/usr/include/qca-ssdk
 	$(INSTALL_DIR) $(1)/usr/include/qca-ssdk/api
diff --git a/package/kernel/qca-ssdk/patches/0001-qca807x-add-a-LED-quirk-for-Xiaomi-AX9000.patch b/package/kernel/qca-ssdk/patches/0001-qca807x-add-a-LED-quirk-for-Xiaomi-AX9000.patch
deleted file mode 100644
index c627c828987b52..00000000000000
--- a/package/kernel/qca-ssdk/patches/0001-qca807x-add-a-LED-quirk-for-Xiaomi-AX9000.patch
+++ /dev/null
@@ -1,65 +0,0 @@
-From 1d37f4ee9b9588a62bfc87419c8a6d9ef989aa9c Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Tue, 7 Nov 2023 12:23:09 +0100
-Subject: [PATCH 1/3] qca807x: add a LED quirk for Xiaomi AX9000
-
-Xiaomi AX9000 has a single LED for each of 4 gigabit ethernet ports that
-are connected to QCA8075, and that LED is connected to the 100M LED pin.
-
-So, by default it will only work when in 10 or 100Mbit mode, this is quite
-annoying and makes no sense(If they have connected it to the 1000Mbit LED
-pin then it would have worked for 10/100 by default as well).
-
-So, to solve this add a check for system compatible as we cant parse if
-from DTS in any other way and set the 100M LED to blink on 1000Base-T
-as well.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- include/hsl/phy/malibu_phy.h | 2 ++
- src/hsl/phy/malibu_phy.c     | 9 +++++++++
- 2 files changed, 11 insertions(+)
-
---- a/include/hsl/phy/malibu_phy.h
-+++ b/include/hsl/phy/malibu_phy.h
-@@ -94,6 +94,7 @@ extern "C"
- #define MALIBU_DAC_CTRL_MASK  0x380
- #define MALIBU_DAC_CTRL_VALUE  0x280
- #define MALIBU_LED_1000_CTRL1_100_10_MASK  0x30
-+#define MALIBU_LED_100_CTRL1_1000_MASK  0x40
- 
- #define MALIBU_PHY_EEE_ADV_100M 0x0002
- #define MALIBU_PHY_EEE_ADV_1000M 0x0004
-@@ -118,6 +119,7 @@ extern "C"
- #define MALIBU_PHY_MMD7_EGRESS_COUNTER_HIGH       0x802d
- #define MALIBU_PHY_MMD7_EGRESS_COUNTER_LOW       0x802e
- #define MALIBU_PHY_MMD7_EGRESS_ERROR_COUNTER       0x802f
-+#define MALIBU_PHY_MMD7_LED_100_CTRL1       0x8074
- #define MALIBU_PHY_MMD7_LED_1000_CTRL1       0x8076
- 
- 
---- a/src/hsl/phy/malibu_phy.c
-+++ b/src/hsl/phy/malibu_phy.c
-@@ -15,6 +15,8 @@
-  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-  */
- 
-+#include <linux/of.h>
-+
- #include "sw.h"
- #include "fal_port_ctrl.h"
- #include "hsl_api.h"
-@@ -1809,6 +1811,13 @@ malibu_phy_hw_init(a_uint32_t dev_id, a_
- 			hsl_phy_modify_mmd(dev_id, phy_addr, A_FALSE, MALIBU_PHY_MMD7_NUM,
- 				MALIBU_PHY_MMD7_LED_1000_CTRL1, MALIBU_LED_1000_CTRL1_100_10_MASK,
- 				MALIBU_LED_1000_CTRL1_100_10_MASK);
-+			if (of_machine_is_compatible("xiaomi,ax9000")) {
-+				/* add 1000M link LED behavior for Xiaomi AX9000 */
-+				hsl_phy_modify_mmd(dev_id, phy_addr, A_FALSE, MALIBU_PHY_MMD7_NUM,
-+						   MALIBU_PHY_MMD7_LED_100_CTRL1,
-+						   MALIBU_LED_100_CTRL1_1000_MASK,
-+						   MALIBU_LED_100_CTRL1_1000_MASK);
-+			}
- 			/*disable Extended next page*/
- 			hsl_phy_modify_mii(dev_id, phy_addr, MALIBU_AUTONEG_ADVERT,
- 				MALIBU_EXTENDED_NEXT_PAGE_EN, 0);
diff --git a/package/kernel/qca-ssdk/patches/0002-qca807x-add-a-LED-quirk-for-Xiaomi-AX3600.patch b/package/kernel/qca-ssdk/patches/0002-qca807x-add-a-LED-quirk-for-Xiaomi-AX3600.patch
deleted file mode 100644
index cfbb6cc771351e..00000000000000
--- a/package/kernel/qca-ssdk/patches/0002-qca807x-add-a-LED-quirk-for-Xiaomi-AX3600.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From 957ee476ddec289973e0af07917da7bfee660af0 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Tue, 7 Nov 2023 12:24:17 +0100
-Subject: [PATCH 2/3] qca807x: add a LED quirk for Xiaomi AX3600
-
-AX3600 requires the same LED quirk so that PHY LED-s will blink even
-once Linux resets the PHY.
-
-So, just check for its compatible.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- src/hsl/phy/malibu_phy.c | 5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
---- a/src/hsl/phy/malibu_phy.c
-+++ b/src/hsl/phy/malibu_phy.c
-@@ -1811,8 +1811,9 @@ malibu_phy_hw_init(a_uint32_t dev_id, a_
- 			hsl_phy_modify_mmd(dev_id, phy_addr, A_FALSE, MALIBU_PHY_MMD7_NUM,
- 				MALIBU_PHY_MMD7_LED_1000_CTRL1, MALIBU_LED_1000_CTRL1_100_10_MASK,
- 				MALIBU_LED_1000_CTRL1_100_10_MASK);
--			if (of_machine_is_compatible("xiaomi,ax9000")) {
--				/* add 1000M link LED behavior for Xiaomi AX9000 */
-+			if (of_machine_is_compatible("xiaomi,ax9000") ||
-+			    of_machine_is_compatible("xiaomi,ax3600")) {
-+				/* add 1000M link LED behavior for Xiaomi boards */
- 				hsl_phy_modify_mmd(dev_id, phy_addr, A_FALSE, MALIBU_PHY_MMD7_NUM,
- 						   MALIBU_PHY_MMD7_LED_100_CTRL1,
- 						   MALIBU_LED_100_CTRL1_1000_MASK,
diff --git a/package/kernel/qca-ssdk/patches/100-malibu-phy-add-support-for-manual-define-of-first-ph.patch b/package/kernel/qca-ssdk/patches/100-malibu-phy-add-support-for-manual-define-of-first-ph.patch
deleted file mode 100644
index 6aaa579c09e33a..00000000000000
--- a/package/kernel/qca-ssdk/patches/100-malibu-phy-add-support-for-manual-define-of-first-ph.patch
+++ /dev/null
@@ -1,131 +0,0 @@
-From a651d10fbd880098d7b98dee27dfd1eb15146fb2 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Sun, 12 Nov 2023 18:40:22 +0100
-Subject: [PATCH] malibu-phy: add support for manual define of first phy addr
-
-The usage of first_phy_addr is EXTREMELY FRAGILE and results
-in dangerous results if the OEM (or anyone that by chance try to
-implement things in a logical manner) deviates from the default values
-from the "magical template".
-
-To be in more details. With QSDK 12.4, some tweaks were done to improve
-autoneg and now on every call of port status, the phydev is tried to
-add. This resulted in the call and log spam of an error with ports that
-are actually not present on the system with qsdk reporting phydev is
-NULL. This itself is not an error and printing the error is correct.
-
-What is actually an error from ages is setting generic bitmap reporting
-presence of port that are actually not present. This is very common on
-OEM where the switch_lan_bmp is always a variant of 0x1e (that on bitmap
-results in PORT1 PORT2 PORT3 PORT4 present) or 0x3e (PORT1 PORT2 PORT3
-PORT4 PORT5). Reality is that many device are used as AP with one LAN
-port or one WAN port. (or even exotic configuration with PORT1 not
-present and PORT2 PORT3 PORT4 present (Xiaomi 3600)
-
-With this finding one can say... ok nice, then lets update the DT and
-set the correct bitmap...
-
-Again world is a bad place and reality is that this cause wonderful
-regression in some case of by extreme luck the first ever connected
-port working and the rest of the switch dead.
-
-The problem has been bisected to all the device that doesn't have the
-PORT1 declared in any of the bitmap.
-
-With this prefaction in mind, on to the REAL problem.
-
-malibu_phy_hw_init FOR SOME REASON, set a global variable first_phy_addr
-to the first detected PHY addr that coincidentally is always PORT1.
-PORT1 addr is 0x0. The entire code in malibu_phy use this variable to
-derive the phy addrs in some function.
-
-Declaring a bitmap where the PORT1 is missing (or worse PORT4 the only
-one connected) result in first_phy_addr set to 1 or whatever phy addr is
-detected first setting wrong value all over the init stage.
-
-To fix this, introduce a new binding malibu_first_phy_addr to manually
-declare the first phy that the malibu PHY driver should use and permit
-to detach it from port bmp detection. The legacy detection is kept for
-compatibility reason.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- include/init/ssdk_dts.h  |  1 +
- include/init/ssdk_init.h |  2 ++
- src/hsl/phy/malibu_phy.c |  5 +++++
- src/init/ssdk_dts.c      | 15 +++++++++++++++
- 4 files changed, 23 insertions(+)
-
---- a/include/init/ssdk_dts.h
-+++ b/include/init/ssdk_dts.h
-@@ -146,6 +146,7 @@ a_uint32_t ssdk_wan_bmp_get(a_uint32_t d
- sw_error_t ssdk_lan_bmp_set(a_uint32_t dev_id, a_uint32_t lan_bmp);
- sw_error_t ssdk_wan_bmp_set(a_uint32_t dev_id, a_uint32_t wan_bmp);
- a_uint32_t ssdk_inner_bmp_get(a_uint32_t dev_id);
-+a_uint32_t ssdk_malibu_first_phy_addr_get(a_uint32_t dev_id);
- hsl_reg_mode ssdk_switch_reg_access_mode_get(a_uint32_t dev_id);
- void ssdk_switch_reg_map_info_get(a_uint32_t dev_id, ssdk_reg_map_info *info);
- a_uint32_t ssdk_switch_pcie_base_get(a_uint32_t dev_id);
---- a/include/init/ssdk_init.h
-+++ b/include/init/ssdk_init.h
-@@ -194,6 +194,7 @@ enum ssdk_port_wrapper_cfg {
- 		a_uint32_t lan_bmp;
- 		a_uint32_t wan_bmp;
- 		a_uint32_t inner_bmp;
-+		a_uint32_t malibu_first_phy_addr;
- 	} ssdk_port_cfg;
- 
- 	typedef struct
-@@ -384,6 +385,7 @@ ssdk_hsl_access_mode_set(a_uint32_t dev_
- 
- a_uint32_t ssdk_dt_global_get_mac_mode(a_uint32_t dev_id, a_uint32_t index);
- a_uint32_t ssdk_dt_global_set_mac_mode(a_uint32_t dev_id, a_uint32_t index, a_uint32_t mode);
-+a_uint32_t ssdk_malibu_first_phy_addr_get(a_uint32_t dev_id);
- 
- a_uint32_t
- qca_hppe_port_mac_type_get(a_uint32_t dev_id, a_uint32_t port_id);
---- a/src/hsl/phy/malibu_phy.c
-+++ b/src/hsl/phy/malibu_phy.c
-@@ -1945,6 +1945,11 @@ static int malibu_phy_api_ops_init(void)
- int malibu_phy_init(a_uint32_t dev_id, a_uint32_t port_bmp)
- {
- 	static a_uint32_t phy_ops_flag = 0;
-+	a_uint32_t malibu_first_phy_addr;
-+
-+	malibu_first_phy_addr = ssdk_malibu_first_phy_addr_get(dev_id);
-+	if (malibu_first_phy_addr != MAX_PHY_ADDR)
-+		first_phy_addr = malibu_first_phy_addr;
- 
- 	if(phy_ops_flag == 0) {
- 		malibu_phy_api_ops_init();
---- a/src/init/ssdk_dts.c
-+++ b/src/init/ssdk_dts.c
-@@ -186,6 +186,13 @@ a_uint32_t ssdk_inner_bmp_get(a_uint32_t
- 	return cfg->port_cfg.inner_bmp;
- }
- 
-+a_uint32_t ssdk_malibu_first_phy_addr_get(a_uint32_t dev_id)
-+{
-+	ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id];
-+
-+	return cfg->port_cfg.malibu_first_phy_addr;
-+}
-+
- hsl_reg_mode ssdk_switch_reg_access_mode_get(a_uint32_t dev_id)
- {
- 	ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id];
-@@ -1039,6 +1046,14 @@ static void ssdk_dt_parse_port_bmp(a_uin
- 				cfg->port_cfg.inner_bmp;
- 	}
- 
-+	/* Permit to manually declare start phy addr for malibu PHY. If not found set to legacy detection. */
-+	if (!of_property_read_u32(switch_node, "malibu_first_phy_addr", &cfg->port_cfg.malibu_first_phy_addr)) {
-+		ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->port_cfg.malibu_first_phy_addr =
-+				cfg->port_cfg.malibu_first_phy_addr;
-+	} else {
-+		ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->port_cfg.malibu_first_phy_addr = MAX_PHY_ADDR;
-+	}
-+
- 	ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->port_cfg.cpu_bmp = cfg->port_cfg.cpu_bmp;
- 	ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->port_cfg.lan_bmp = cfg->port_cfg.lan_bmp;
- 	ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->port_cfg.wan_bmp = cfg->port_cfg.wan_bmp;
diff --git a/package/kernel/qca-ssdk/patches/101-hsl_phy-add-support-for-detection-PSGMII-PHY-mode.patch b/package/kernel/qca-ssdk/patches/101-hsl_phy-add-support-for-detection-PSGMII-PHY-mode.patch
new file mode 100644
index 00000000000000..c27902c4ce1d8c
--- /dev/null
+++ b/package/kernel/qca-ssdk/patches/101-hsl_phy-add-support-for-detection-PSGMII-PHY-mode.patch
@@ -0,0 +1,25 @@
+From e3763fd77e41b2f2495672c6a5898d69892fbf9f Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Wed, 15 Nov 2023 00:57:41 +0100
+Subject: [PATCH] hsl_phy: add support for detection PSGMII PHY mode
+
+Add support for detection of PSGMII PHY mode to correctly detect qca807x
+PHY upstream driver.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ src/hsl/phy/hsl_phy.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/src/hsl/phy/hsl_phy.c
++++ b/src/hsl/phy/hsl_phy.c
+@@ -1335,6 +1335,9 @@ hsl_port_phydev_interface_mode_status_ge
+ 		case PHY_INTERFACE_MODE_10GKR:
+ 			*interface_mode_status = PORT_10GBASE_R;
+ 			break;
++		case PHY_INTERFACE_MODE_PSGMII:
++			*interface_mode_status = PHY_PSGMII_BASET;
++			break;
+ 		case PHY_INTERFACE_MODE_QSGMII:
+ 			*interface_mode_status = PORT_QSGMII;
+ 			break;
diff --git a/package/kernel/qca-ssdk/patches/102-qca-ssdk-support-selecting-PCS-channel-for-PORT3-on-.patch b/package/kernel/qca-ssdk/patches/102-qca-ssdk-support-selecting-PCS-channel-for-PORT3-on-.patch
new file mode 100644
index 00000000000000..a8863bf4630b74
--- /dev/null
+++ b/package/kernel/qca-ssdk/patches/102-qca-ssdk-support-selecting-PCS-channel-for-PORT3-on-.patch
@@ -0,0 +1,146 @@
+From 0116bb7359bd99c09bcad1b2051652cd1a04be3f Mon Sep 17 00:00:00 2001
+From: Mantas Pucka <mantas@8devices.com>
+Date: Mon, 12 Feb 2024 14:23:04 +0200
+Subject: [PATCH] qca-ssdk: support selecting PCS channel for PORT3 on IPQ6018
+
+When QCA8072 is used in PSGMII mode with IPQ6018, PCS used for second
+PHY port would overlap with one used by SGMII+ port. SoC has register
+to select different PCS in such case.
+
+Original code used PHY_ID for this decision, which also had other
+issues, but is no longer viable since we moved to upstream QCA807x
+driver.
+
+Introduce DT property port3_pcs_channel to allow describing this in DT.
+Default value is <2>, and for some QCA8072 designs <4> would be needed.
+
+Signed-off-by: Mantas Pucka <mantas@8devices.com>
+---
+ include/init/ssdk_dts.h            |  2 ++
+ src/adpt/cppe/adpt_cppe_portctrl.c |  4 ++--
+ src/adpt/hppe/adpt_hppe_uniphy.c   |  7 +------
+ src/init/ssdk_dts.c                | 27 +++++++++++++++++++++++++++
+ 4 files changed, 32 insertions(+), 8 deletions(-)
+
+diff --git a/include/init/ssdk_dts.h b/include/init/ssdk_dts.h
+index 00fa4c1..210c788 100755
+--- a/include/init/ssdk_dts.h
++++ b/include/init/ssdk_dts.h
+@@ -101,6 +101,7 @@ typedef struct
+ 	a_uint32_t emu_chip_ver; /*only valid when is_emulation is true*/
+ 	a_uint32_t clk_mode;
+ 	a_uint32_t pcie_hw_base;
++	a_uint32_t port3_pcs_channel;
+ } ssdk_dt_cfg;
+ 
+ #define SSDK_MAX_NR_ETH 6
+@@ -163,6 +164,7 @@ a_uint32_t ssdk_device_id_get(a_uint32_t index);
+ struct device_node *ssdk_dts_node_get(a_uint32_t dev_id);
+ struct clk *ssdk_dts_essclk_get(a_uint32_t dev_id);
+ struct clk *ssdk_dts_cmnclk_get(a_uint32_t dev_id);
++a_uint32_t ssdk_dts_port3_pcs_channel_get(a_uint32_t dev_id);
+ 
+ int ssdk_switch_device_num_init(void);
+ void ssdk_switch_device_num_exit(void);
+diff --git a/src/adpt/cppe/adpt_cppe_portctrl.c b/src/adpt/cppe/adpt_cppe_portctrl.c
+index 00d0404..6b32f79 100755
+--- a/src/adpt/cppe/adpt_cppe_portctrl.c
++++ b/src/adpt/cppe/adpt_cppe_portctrl.c
+@@ -33,6 +33,7 @@
+ #include "hsl_phy.h"
+ #include "hsl_port_prop.h"
+ #include "hppe_init.h"
++#include "ssdk_dts.h"
+ #include "adpt.h"
+ #include "adpt_hppe.h"
+ #include "adpt_cppe_portctrl.h"
+@@ -60,8 +61,7 @@ _adpt_cppe_port_mux_mac_set(a_uint32_t dev_id, fal_port_t port_id,
+ 		case SSDK_PHYSICAL_PORT3:
+ 		case SSDK_PHYSICAL_PORT4:
+ 			if (mode0 == PORT_WRAPPER_PSGMII) {
+-				if (hsl_port_phyid_get(dev_id,
+-					SSDK_PHYSICAL_PORT3) == MALIBU2PORT_PHY) {
++				if (ssdk_dts_port3_pcs_channel_get(dev_id) == 4) {
+ 					cppe_port_mux_ctrl.bf.port3_pcs_sel =
+ 						CPPE_PORT3_PCS_SEL_PCS0_CHANNEL4;
+ 					cppe_port_mux_ctrl.bf.port4_pcs_sel =
+diff --git a/src/adpt/hppe/adpt_hppe_uniphy.c b/src/adpt/hppe/adpt_hppe_uniphy.c
+index 5e36602..bad1eab 100644
+--- a/src/adpt/hppe/adpt_hppe_uniphy.c
++++ b/src/adpt/hppe/adpt_hppe_uniphy.c
+@@ -1122,9 +1122,6 @@ __adpt_hppe_uniphy_psgmii_mode_set(a_uint32_t dev_id, a_uint32_t uniphy_index)
+ {
+ 	a_uint32_t i;
+ 	sw_error_t rv = SW_OK;
+-#if defined(CPPE)
+-	a_uint32_t phy_type = 0;
+-#endif
+ 
+ 	union uniphy_mode_ctrl_u uniphy_mode_ctrl;
+ 
+@@ -1134,9 +1131,7 @@ __adpt_hppe_uniphy_psgmii_mode_set(a_uint32_t dev_id, a_uint32_t uniphy_index)
+ 	SSDK_DEBUG("uniphy %d is psgmii mode\n", uniphy_index);
+ #if defined(CPPE)
+ 	if (adpt_ppe_type_get(dev_id) == CPPE_TYPE) {
+-		phy_type = hsl_port_phyid_get(dev_id,
+-				SSDK_PHYSICAL_PORT3);
+-		if (phy_type == MALIBU2PORT_PHY) {
++		if (ssdk_dts_port3_pcs_channel_get(dev_id) == 4) {
+ 			SSDK_INFO("cypress uniphy %d is qca8072 psgmii mode\n", uniphy_index);
+ 			rv = __adpt_cppe_uniphy_mode_set(dev_id, uniphy_index,
+ 				PORT_WRAPPER_PSGMII);
+diff --git a/src/init/ssdk_dts.c b/src/init/ssdk_dts.c
+index 686b6d2..70b0a09 100644
+--- a/src/init/ssdk_dts.c
++++ b/src/init/ssdk_dts.c
+@@ -279,6 +279,13 @@ struct clk *ssdk_dts_cmnclk_get(a_uint32_t dev_id)
+ 	return cfg->cmnblk_clk;
+ }
+ 
++a_uint32_t ssdk_dts_port3_pcs_channel_get(a_uint32_t dev_id)
++{
++	ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id];
++	
++	return cfg->port3_pcs_channel;
++}
++
+ #ifndef BOARD_AR71XX
+ #if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0))
+ static void ssdk_dt_parse_mac_mode(a_uint32_t dev_id,
+@@ -313,6 +320,25 @@ static void ssdk_dt_parse_mac_mode(a_uint32_t dev_id,
+ 
+ 	return;
+ }
++
++static void ssdk_dt_parse_port3_pcs_channel(a_uint32_t dev_id,
++		struct device_node *switch_node, ssdk_init_cfg *cfg)
++{
++	const __be32 *port3_pcs_channel;
++	a_uint32_t len = 0;
++	
++	port3_pcs_channel = of_get_property(switch_node, "port3_pcs_channel", &len);
++	if (!port3_pcs_channel) {
++		ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->port3_pcs_channel = 2;
++	}
++	else {
++		ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->port3_pcs_channel =
++			be32_to_cpup(port3_pcs_channel);
++	}
++
++	return;
++}
++
+ #ifdef IN_UNIPHY
+ static void ssdk_dt_parse_uniphy(a_uint32_t dev_id)
+ {
+@@ -1307,6 +1333,7 @@ sw_error_t ssdk_dt_parse(ssdk_init_cfg *cfg, a_uint32_t num, a_uint32_t *dev_id)
+ 	rv = ssdk_dt_parse_access_mode(switch_node, ssdk_dt_priv);
+ 	SW_RTN_ON_ERROR(rv);
+ 	ssdk_dt_parse_mac_mode(*dev_id, switch_node, cfg);
++	ssdk_dt_parse_port3_pcs_channel(*dev_id, switch_node, cfg);
+ 	ssdk_dt_parse_mdio(*dev_id, switch_node, cfg);
+ 	ssdk_dt_parse_port_bmp(*dev_id, switch_node, cfg);
+ 	ssdk_dt_parse_interrupt(*dev_id, switch_node);
+-- 
+2.7.4
+
diff --git a/package/libs/libxml2/Makefile b/package/libs/libxml2/Makefile
index 030f7e45e8553b..86fa3707710f98 100644
--- a/package/libs/libxml2/Makefile
+++ b/package/libs/libxml2/Makefile
@@ -1,12 +1,12 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=libxml2
-PKG_VERSION:=2.12.4
+PKG_VERSION:=2.12.5
 PKG_RELEASE:=1
 
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
 PKG_SOURCE_URL:=@GNOME/libxml2/$(basename $(PKG_VERSION))
-PKG_HASH:=497360e423cf0bd99eacdb7c6215dea92e6d6e89ee940393c2bae0e77cb9b7d0
+PKG_HASH:=a972796696afd38073e0f59c283c3a2f5a560b5268b4babc391b286166526b21
 
 PKG_LICENSE:=MIT
 PKG_LICENSE_FILES:=COPYING
diff --git a/package/libs/openssl/Makefile b/package/libs/openssl/Makefile
index 4b1388e7af6d49..3bb60bc5ed7531 100644
--- a/package/libs/openssl/Makefile
+++ b/package/libs/openssl/Makefile
@@ -8,7 +8,7 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=openssl
-PKG_VERSION:=3.0.12
+PKG_VERSION:=3.0.13
 PKG_RELEASE:=1
 PKG_BUILD_FLAGS:=no-mips16 gc-sections no-lto
 
@@ -24,7 +24,7 @@ PKG_SOURCE_URL:= \
 	ftp://ftp.pca.dfn.de/pub/tools/net/openssl/source/ \
 	ftp://ftp.pca.dfn.de/pub/tools/net/openssl/source/old/$(PKG_BASE)/
 
-PKG_HASH:=f93c9e8edde5e9166119de31755fc87b4aa34863662f67ddfcba14d0b6b69b61
+PKG_HASH:=88525753f79d3bec27d2fa7c66aa0b92b3aa9498dafd93d7cfa4b3780cdae313
 
 PKG_LICENSE:=Apache-2.0
 PKG_LICENSE_FILES:=LICENSE
diff --git a/package/libs/openssl/patches/100-Configure-afalg-support.patch b/package/libs/openssl/patches/100-Configure-afalg-support.patch
index 307e23b80924da..e9cd7bf9c1afa6 100644
--- a/package/libs/openssl/patches/100-Configure-afalg-support.patch
+++ b/package/libs/openssl/patches/100-Configure-afalg-support.patch
@@ -10,7 +10,7 @@ Signed-off-by: Eneas U de Queiroz <cote2004-github@yahoo.com>
 
 --- a/Configure
 +++ b/Configure
-@@ -1674,7 +1674,9 @@ $config{CFLAGS} = [ map { $_ eq '--ossl-
+@@ -1677,7 +1677,9 @@ $config{CFLAGS} = [ map { $_ eq '--ossl-
  
  unless ($disabled{afalgeng}) {
      $config{afalgeng}="";
diff --git a/package/libs/openssl/patches/140-allow-prefer-chacha20.patch b/package/libs/openssl/patches/140-allow-prefer-chacha20.patch
index 43fd92e3886cff..fb7bc8436174c0 100644
--- a/package/libs/openssl/patches/140-allow-prefer-chacha20.patch
+++ b/package/libs/openssl/patches/140-allow-prefer-chacha20.patch
@@ -16,7 +16,7 @@ Signed-off-by: Eneas U de Queiroz <cote2004-github@yahoo.com>
 
 --- a/ssl/ssl_ciph.c
 +++ b/ssl/ssl_ciph.c
-@@ -1505,11 +1505,29 @@ STACK_OF(SSL_CIPHER) *ssl_create_cipher_
+@@ -1506,11 +1506,29 @@ STACK_OF(SSL_CIPHER) *ssl_create_cipher_
      ssl_cipher_apply_rule(0, SSL_kECDHE, 0, 0, 0, 0, 0, CIPHER_DEL, -1, &head,
                            &tail);
  
@@ -46,7 +46,7 @@ Signed-off-by: Eneas U de Queiroz <cote2004-github@yahoo.com>
  
      /*
       * ...and generally, our preferred cipher is AES.
-@@ -1564,7 +1582,7 @@ STACK_OF(SSL_CIPHER) *ssl_create_cipher_
+@@ -1565,7 +1583,7 @@ STACK_OF(SSL_CIPHER) *ssl_create_cipher_
       * Within each group, ciphers remain sorted by strength and previous
       * preference, i.e.,
       * 1) ECDHE > DHE
@@ -55,7 +55,7 @@ Signed-off-by: Eneas U de Queiroz <cote2004-github@yahoo.com>
       * 3) AES > rest
       * 4) TLS 1.2 > legacy
       *
-@@ -2235,7 +2253,13 @@ const char *OSSL_default_cipher_list(voi
+@@ -2236,7 +2254,13 @@ const char *OSSL_default_cipher_list(voi
   */
  const char *OSSL_default_ciphersuites(void)
  {
diff --git a/package/libs/zlib/Makefile b/package/libs/zlib/Makefile
index 5152c9735ea33e..2559fbba0d4cc7 100644
--- a/package/libs/zlib/Makefile
+++ b/package/libs/zlib/Makefile
@@ -8,12 +8,12 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=zlib
-PKG_VERSION:=1.3
+PKG_VERSION:=1.3.1
 PKG_RELEASE:=1
 
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
 PKG_SOURCE_URL:=https://github.com/madler/zlib/releases/download/v$(PKG_VERSION)
-PKG_HASH:=8a9ba2898e1d0d774eca6ba5b4627a11e5588ba85c8851336eb38de4683050a7
+PKG_HASH:=38ef96b8dfe510d42707d9c781877914792541133e1870841463bfa73f883e32
 
 PKG_LICENSE:=Zlib
 PKG_LICENSE_FILES:=README
diff --git a/package/libs/zlib/patches/004-attach-sourcefiles-in-patch-002-to-buildsystem.patch b/package/libs/zlib/patches/004-attach-sourcefiles-in-patch-002-to-buildsystem.patch
index 81816aed680d63..5181dcf41952e5 100644
--- a/package/libs/zlib/patches/004-attach-sourcefiles-in-patch-002-to-buildsystem.patch
+++ b/package/libs/zlib/patches/004-attach-sourcefiles-in-patch-002-to-buildsystem.patch
@@ -1,6 +1,6 @@
 --- a/CMakeLists.txt
 +++ b/CMakeLists.txt
-@@ -91,34 +91,67 @@ set(ZLIB_PUBLIC_HDRS
+@@ -93,34 +93,67 @@ set(ZLIB_PUBLIC_HDRS
      ${CMAKE_CURRENT_BINARY_DIR}/zconf.h
      zlib.h
  )
diff --git a/package/network/config/netifd/Makefile b/package/network/config/netifd/Makefile
index 558463e8ea5bc9..ba4516c1dc6cc7 100644
--- a/package/network/config/netifd/Makefile
+++ b/package/network/config/netifd/Makefile
@@ -43,7 +43,10 @@ define Package/netifd/install
 	$(INSTALL_BIN) $(PKG_BUILD_DIR)/netifd $(1)/sbin/
 	$(CP) ./files/* $(1)/
 	$(INSTALL_DIR) $(1)/etc/udhcpc.user.d/
-	$(CP) $(PKG_BUILD_DIR)/scripts/* $(1)/lib/netifd/
+	$(CP) \
+		$(PKG_BUILD_DIR)/scripts/utils.sh \
+		$(PKG_BUILD_DIR)/scripts/netifd-proto.sh \
+		$(1)/lib/netifd/
 endef
 
 $(eval $(call BuildPackage,netifd))
diff --git a/package/network/config/wifi-scripts/Makefile b/package/network/config/wifi-scripts/Makefile
new file mode 100644
index 00000000000000..085860d7c69f3f
--- /dev/null
+++ b/package/network/config/wifi-scripts/Makefile
@@ -0,0 +1,45 @@
+#
+# Copyright (C) 2024 OpenWrt.org
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+include $(TOPDIR)/rules.mk
+
+PKG_NAME:=wifi-scripts
+PKG_VERSION:=1.0
+PKG_RELEASE:=1
+PKG_LICENSE:=GPL-2.0
+
+PKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>
+
+include $(INCLUDE_DIR)/package.mk
+
+define Package/wifi-scripts
+  SECTION:=utils
+  CATEGORY:=Base system
+  DEPENDS:=+netifd +ucode +ucode-mod-nl80211 +ucode-mod-ubus
+  TITLE:=Wi-Fi configuration scripts
+  PKGARCH:=all
+endef
+
+define Package/wifi-scripts/description
+ A set of scripts that handle setup and configuration of Wi-Fi devices.
+endef
+
+define Build/Prepare
+endef
+
+define Build/Configure
+endef
+
+define Build/Compile
+endef
+
+define Package/wifi-scripts/install
+	$(INSTALL_DIR) $(1)
+	$(CP) ./files/* $(1)/
+endef
+
+$(eval $(call BuildPackage,wifi-scripts))
diff --git a/package/kernel/mac80211/files/mac80211.hotplug b/package/network/config/wifi-scripts/files/etc/hotplug.d/ieee80211/10-wifi-detect
similarity index 100%
rename from package/kernel/mac80211/files/mac80211.hotplug
rename to package/network/config/wifi-scripts/files/etc/hotplug.d/ieee80211/10-wifi-detect
diff --git a/package/network/services/hostapd/files/hostapd.sh b/package/network/config/wifi-scripts/files/lib/netifd/hostapd.sh
similarity index 99%
rename from package/network/services/hostapd/files/hostapd.sh
rename to package/network/config/wifi-scripts/files/lib/netifd/hostapd.sh
index 1a664abbf2f14e..763702e76b1a44 100644
--- a/package/network/services/hostapd/files/hostapd.sh
+++ b/package/network/config/wifi-scripts/files/lib/netifd/hostapd.sh
@@ -77,7 +77,7 @@ hostapd_append_wpa_key_mgmt() {
 
 	[ "$fils" -gt 0 ] && {
 		case "$auth_type" in
-			eap-192)
+			eap192)
 				append wpa_key_mgmt FILS-SHA384
 				[ "${ieee80211r:-0}" -gt 0 ] && append wpa_key_mgmt FT-FILS-SHA384
 			;;
diff --git a/package/network/config/wifi-scripts/files/lib/netifd/netifd-wireless.sh b/package/network/config/wifi-scripts/files/lib/netifd/netifd-wireless.sh
new file mode 100644
index 00000000000000..5b852e0937631a
--- /dev/null
+++ b/package/network/config/wifi-scripts/files/lib/netifd/netifd-wireless.sh
@@ -0,0 +1,439 @@
+NETIFD_MAIN_DIR="${NETIFD_MAIN_DIR:-/lib/netifd}"
+
+. /usr/share/libubox/jshn.sh
+. $NETIFD_MAIN_DIR/utils.sh
+
+CMD_UP=0
+CMD_SET_DATA=1
+CMD_PROCESS_ADD=2
+CMD_PROCESS_KILL_ALL=3
+CMD_SET_RETRY=4
+
+add_driver() {
+	return
+}
+
+wireless_setup_vif_failed() {
+	local error="$1"
+	echo "Interface $_w_iface setup failed: $error"
+}
+
+wireless_setup_failed() {
+	local error="$1"
+
+	echo "Device setup failed: $error"
+	wireless_set_retry 0
+}
+
+prepare_key_wep() {
+	local key="$1"
+	local hex=1
+
+	echo -n "$key" | grep -qE "[^a-fA-F0-9]" && hex=0
+	[ "${#key}" -eq 10 -a $hex -eq 1 ] || \
+	[ "${#key}" -eq 26 -a $hex -eq 1 ] || {
+		[ "${key:0:2}" = "s:" ] && key="${key#s:}"
+		key="$(echo -n "$key" | hexdump -ve '1/1 "%02x" ""')"
+	}
+	echo "$key"
+}
+
+_wdev_prepare_channel() {
+	json_get_vars channel band hwmode
+
+	auto_channel=0
+	enable_ht=0
+	htmode=
+	hwmode="${hwmode##11}"
+
+	case "$channel" in
+		""|0|auto)
+			channel=0
+			auto_channel=1
+		;;
+		[0-9]*) ;;
+		*)
+			wireless_setup_failed "INVALID_CHANNEL"
+		;;
+	esac
+
+	case "$hwmode" in
+		a|b|g|ad) ;;
+		*)
+			if [ "$channel" -gt 14 ]; then
+				hwmode=a
+			else
+				hwmode=g
+			fi
+		;;
+	esac
+
+	case "$band" in
+		2g) hwmode=g;;
+		5g|6g) hwmode=a;;
+		60g) hwmode=ad;;
+		*)
+			case "$hwmode" in
+				*a) band=5g;;
+				*ad) band=60g;;
+				*b|*g) band=2g;;
+			esac
+		;;
+	esac
+}
+
+_wdev_handler() {
+	json_load "$data"
+
+	json_select config
+	_wdev_prepare_channel
+	json_select ..
+
+	eval "drv_$1_$2 \"$interface\""
+}
+
+_wdev_msg_call() {
+	local old_cb
+
+	json_set_namespace wdev old_cb
+	"$@"
+	json_set_namespace $old_cb
+}
+
+_wdev_wrapper() {
+	while [ -n "$1" ]; do
+		eval "$1() { _wdev_msg_call _$1 \"\$@\"; }"
+		shift
+	done
+}
+
+_wdev_notify_init() {
+	local command="$1"; shift;
+
+	json_init
+	json_add_int "command" "$command"
+	json_add_string "device" "$__netifd_device"
+	while [ -n "$1" ]; do
+		local name="$1"; shift
+		local value="$1"; shift
+		json_add_string "$name" "$value"
+	done
+	json_add_object "data"
+}
+
+_wdev_notify() {
+	local options="$1"
+
+	json_close_object
+	ubus $options call network.wireless notify "$(json_dump)"
+}
+
+_wdev_add_variables() {
+	while [ -n "$1" ]; do
+		local var="${1%%=*}"
+		local val="$1"
+		shift
+		[[ "$var" = "$val" ]] && continue
+		val="${val#*=}"
+		json_add_string "$var" "$val"
+	done
+}
+
+_wireless_add_vif() {
+	local name="$1"; shift
+	local ifname="$1"; shift
+
+	_wdev_notify_init $CMD_SET_DATA "interface" "$name"
+	json_add_string "ifname" "$ifname"
+	_wdev_add_variables "$@"
+	_wdev_notify
+}
+
+_wireless_add_vlan() {
+	local name="$1"; shift
+	local ifname="$1"; shift
+
+	_wdev_notify_init $CMD_SET_DATA interface "$__cur_interface" "vlan" "$name"
+	json_add_string "ifname" "$ifname"
+	_wdev_add_variables "$@"
+	_wdev_notify
+}
+
+_wireless_set_up() {
+	_wdev_notify_init $CMD_UP
+	_wdev_notify
+}
+
+_wireless_set_data() {
+	_wdev_notify_init $CMD_SET_DATA
+	_wdev_add_variables "$@"
+	_wdev_notify
+}
+
+_wireless_add_process() {
+	_wdev_notify_init $CMD_PROCESS_ADD
+	local exe="$2"
+	[ -L "$exe" ] && exe="$(readlink -f "$exe")"
+	json_add_int pid "$1"
+	json_add_string exe "$exe"
+	[ -n "$3" ] && json_add_boolean required 1
+	[ -n "$4" ] && json_add_boolean keep 1
+	exe2="$(readlink -f /proc/$1/exe)"
+	[ "$exe" != "$exe2" ] && echo "WARNING (wireless_add_process): executable path $exe does not match process $1 path ($exe2)"
+	_wdev_notify
+}
+
+_wireless_process_kill_all() {
+	_wdev_notify_init $CMD_PROCESS_KILL_ALL
+	[ -n "$1" ] && json_add_int signal "$1"
+	_wdev_notify
+}
+
+_wireless_set_retry() {
+	_wdev_notify_init $CMD_SET_RETRY
+	json_add_int retry "$1"
+	_wdev_notify
+}
+
+_wdev_wrapper \
+	wireless_add_vif \
+	wireless_add_vlan \
+	wireless_set_up \
+	wireless_set_data \
+	wireless_add_process \
+	wireless_process_kill_all \
+	wireless_set_retry \
+
+wireless_vif_parse_encryption() {
+	json_get_vars encryption
+	set_default encryption none
+
+	auth_mode_open=1
+	auth_mode_shared=0
+	auth_type=none
+
+	if [ "$hwmode" = "ad" ]; then
+		wpa_cipher="GCMP"
+	else
+		wpa_cipher="CCMP"
+	fi
+
+	case "$encryption" in
+		*tkip+aes|*tkip+ccmp|*aes+tkip|*ccmp+tkip) wpa_cipher="CCMP TKIP";;
+		*ccmp256) wpa_cipher="CCMP-256";;
+		*aes|*ccmp) wpa_cipher="CCMP";;
+		*tkip) wpa_cipher="TKIP";;
+		*gcmp256) wpa_cipher="GCMP-256";;
+		*gcmp) wpa_cipher="GCMP";;
+		wpa3-192*) wpa_cipher="GCMP-256";;
+	esac
+
+	# 802.11n requires CCMP for WPA
+	[ "$enable_ht:$wpa_cipher" = "1:TKIP" ] && wpa_cipher="CCMP TKIP"
+
+	# Examples:
+	# psk-mixed/tkip    => WPA1+2 PSK, TKIP
+	# wpa-psk2/tkip+aes => WPA2 PSK, CCMP+TKIP
+	# wpa2/tkip+aes     => WPA2 RADIUS, CCMP+TKIP
+
+	case "$encryption" in
+		wpa2*|wpa3*|*psk2*|psk3*|sae*|owe*)
+			wpa=2
+		;;
+		wpa*mixed*|*psk*mixed*)
+			wpa=3
+		;;
+		wpa*|*psk*)
+			wpa=1
+		;;
+		*)
+			wpa=0
+			wpa_cipher=
+		;;
+	esac
+	wpa_pairwise="$wpa_cipher"
+
+	case "$encryption" in
+		owe*)
+			auth_type=owe
+		;;
+		wpa3-192*)
+			auth_type=eap192
+		;;
+		wpa3-mixed*)
+			auth_type=eap-eap2
+		;;
+		wpa3*)
+			auth_type=eap2
+		;;
+		psk3-mixed*|sae-mixed*)
+			auth_type=psk-sae
+		;;
+		psk3*|sae*)
+			auth_type=sae
+		;;
+		*psk*)
+			auth_type=psk
+		;;
+		*wpa*|*8021x*)
+			auth_type=eap
+		;;
+		*wep*)
+			auth_type=wep
+			case "$encryption" in
+				*shared*)
+					auth_mode_open=0
+					auth_mode_shared=1
+				;;
+				*mixed*)
+					auth_mode_shared=1
+				;;
+			esac
+		;;
+	esac
+
+	case "$encryption" in
+		*osen*)
+			auth_osen=1
+		;;
+	esac
+}
+
+_wireless_set_brsnoop_isolation() {
+	local multicast_to_unicast="$1"
+	local isolate
+
+	json_get_vars isolate proxy_arp
+
+	[ ${isolate:-0} -gt 0 -o -z "$network_bridge" ] && return
+	[ ${multicast_to_unicast:-1} -gt 0 -o ${proxy_arp:-0} -gt 0 ] && json_add_boolean isolate 1
+}
+
+for_each_interface() {
+	local _w_types="$1"; shift
+	local _w_ifaces _w_iface
+	local _w_type
+	local _w_found
+
+	local multicast_to_unicast
+
+	json_get_keys _w_ifaces interfaces
+	json_select interfaces
+	for _w_iface in $_w_ifaces; do
+		json_select "$_w_iface"
+		if [ -n "$_w_types" ]; then
+			json_get_var network_bridge bridge
+			json_get_var network_ifname bridge-ifname
+			json_get_var multicast_to_unicast multicast_to_unicast
+			json_select config
+			_wireless_set_brsnoop_isolation "$multicast_to_unicast"
+			json_get_var _w_type mode
+			json_select ..
+			_w_types=" $_w_types "
+			[[ "${_w_types%$_w_type*}" = "$_w_types" ]] && {
+				json_select ..
+				continue
+			}
+		fi
+		__cur_interface="$_w_iface"
+		"$@" "$_w_iface"
+		json_select ..
+	done
+	json_select ..
+}
+
+for_each_vlan() {
+	local _w_vlans _w_vlan
+
+	json_get_keys _w_vlans vlans
+	json_select vlans
+	for _w_vlan in $_w_vlans; do
+		json_select "$_w_vlan"
+		json_select config
+		"$@" "$_w_vlan"
+		json_select ..
+		json_select ..
+	done
+	json_select ..
+}
+
+for_each_station() {
+	local _w_stas _w_sta
+
+	json_get_keys _w_stas stas
+	json_select stas
+	for _w_sta in $_w_stas; do
+		json_select "$_w_sta"
+		json_select config
+		"$@" "$_w_sta"
+		json_select ..
+		json_select ..
+	done
+	json_select ..
+}
+
+_wdev_common_device_config() {
+	config_add_string channel hwmode band htmode noscan
+}
+
+_wdev_common_iface_config() {
+	config_add_string mode ssid encryption 'key:wpakey'
+	config_add_boolean bridge_isolate
+}
+
+_wdev_common_vlan_config() {
+	config_add_string name vid iface
+	config_add_boolean bridge_isolate
+}
+
+_wdev_common_station_config() {
+	config_add_string mac key vid iface
+}
+
+init_wireless_driver() {
+	name="$1"; shift
+	cmd="$1"; shift
+
+	case "$cmd" in
+		dump)
+			add_driver() {
+				eval "drv_$1_cleanup"
+
+				json_init
+				json_add_string name "$1"
+
+				json_add_array device
+				_wdev_common_device_config
+				eval "drv_$1_init_device_config"
+				json_close_array
+
+				json_add_array iface
+				_wdev_common_iface_config
+				eval "drv_$1_init_iface_config"
+				json_close_array
+
+				json_add_array vlan
+				_wdev_common_vlan_config
+				eval "drv_$1_init_vlan_config"
+				json_close_array
+
+				json_add_array station
+				_wdev_common_station_config
+				eval "drv_$1_init_station_config"
+				json_close_array
+
+				json_dump
+			}
+		;;
+		setup|teardown)
+			interface="$1"; shift
+			data="$1"; shift
+			export __netifd_device="$interface"
+
+			add_driver() {
+				[[ "$name" == "$1" ]] || return 0
+				_wdev_handler "$1" "$cmd"
+			}
+		;;
+	esac
+}
diff --git a/package/kernel/mac80211/files/lib/netifd/wireless/mac80211.sh b/package/network/config/wifi-scripts/files/lib/netifd/wireless/mac80211.sh
old mode 100644
new mode 100755
similarity index 99%
rename from package/kernel/mac80211/files/lib/netifd/wireless/mac80211.sh
rename to package/network/config/wifi-scripts/files/lib/netifd/wireless/mac80211.sh
index 49ffb219bcd3c4..55df71ee3d5857
--- a/package/kernel/mac80211/files/lib/netifd/wireless/mac80211.sh
+++ b/package/network/config/wifi-scripts/files/lib/netifd/wireless/mac80211.sh
@@ -432,9 +432,9 @@ mac80211_hostapd_setup_base() {
 			he_bss_color:128 \
 			he_bss_color_enabled:1
 
-		he_phy_cap=$(iw phy "$phy" info | sed -n '/HE Iftypes: AP/,$p' | awk -F "[()]" '/HE PHY Capabilities/ { print $2 }' | head -1)
+		he_phy_cap=$(iw phy "$phy" info | sed -n '/HE Iftypes: .*AP/,$p' | awk -F "[()]" '/HE PHY Capabilities/ { print $2 }' | head -1)
 		he_phy_cap=${he_phy_cap:2}
-		he_mac_cap=$(iw phy "$phy" info | sed -n '/HE Iftypes: AP/,$p' | awk -F "[()]" '/HE MAC Capabilities/ { print $2 }' | head -1)
+		he_mac_cap=$(iw phy "$phy" info | sed -n '/HE Iftypes: .*AP/,$p' | awk -F "[()]" '/HE MAC Capabilities/ { print $2 }' | head -1)
 		he_mac_cap=${he_mac_cap:2}
 
 		append base_cfg "ieee80211ax=1" "$N"
diff --git a/package/kernel/mac80211/files/lib/wifi/mac80211.sh b/package/network/config/wifi-scripts/files/lib/wifi/mac80211.sh
similarity index 100%
rename from package/kernel/mac80211/files/lib/wifi/mac80211.sh
rename to package/network/config/wifi-scripts/files/lib/wifi/mac80211.sh
diff --git a/package/base-files/files/sbin/wifi b/package/network/config/wifi-scripts/files/sbin/wifi
similarity index 99%
rename from package/base-files/files/sbin/wifi
rename to package/network/config/wifi-scripts/files/sbin/wifi
index 5231063a2b78f1..27cbad37811f63 100755
--- a/package/base-files/files/sbin/wifi
+++ b/package/network/config/wifi-scripts/files/sbin/wifi
@@ -176,6 +176,7 @@ wifi_detect_notice() {
 
 wifi_config() {
 	[ -e /tmp/.config_pending ] && return
+	ucode /usr/share/hostap/wifi-detect.uc
 	[ ! -f /etc/config/wireless ] && touch /etc/config/wireless
 
 	for driver in $DRIVERS; do (
diff --git a/package/network/services/hostapd/files/common.uc b/package/network/config/wifi-scripts/files/usr/share/hostap/common.uc
similarity index 99%
rename from package/network/services/hostapd/files/common.uc
rename to package/network/config/wifi-scripts/files/usr/share/hostap/common.uc
index 4c33779af935e1..750e3ae71c27da 100644
--- a/package/network/services/hostapd/files/common.uc
+++ b/package/network/config/wifi-scripts/files/usr/share/hostap/common.uc
@@ -49,7 +49,7 @@ function __phy_is_fullmac(phyidx)
 {
 	let data = nl80211.request(nl80211.const.NL80211_CMD_GET_WIPHY, 0, { wiphy: phyidx });
 
-	return !data.software_iftypes.ap_vlan;
+	return !data.software_iftypes.monitor;
 }
 
 function phy_is_fullmac(phy)
diff --git a/package/network/services/hostapd/files/wdev.uc b/package/network/config/wifi-scripts/files/usr/share/hostap/wdev.uc
similarity index 100%
rename from package/network/services/hostapd/files/wdev.uc
rename to package/network/config/wifi-scripts/files/usr/share/hostap/wdev.uc
diff --git a/package/network/config/wifi-scripts/files/usr/share/hostap/wifi-detect.uc b/package/network/config/wifi-scripts/files/usr/share/hostap/wifi-detect.uc
new file mode 100644
index 00000000000000..5f375880d2ba20
--- /dev/null
+++ b/package/network/config/wifi-scripts/files/usr/share/hostap/wifi-detect.uc
@@ -0,0 +1,155 @@
+#!/usr/bin/env ucode
+'use strict';
+import { readfile, writefile, realpath, glob, basename, unlink, open, rename } from "fs";
+import { is_equal } from "/usr/share/hostap/common.uc";
+let nl = require("nl80211");
+
+let board_file = "/etc/board.json";
+let prev_board_data = json(readfile(board_file));
+let board_data = json(readfile(board_file));
+
+function phy_idx(name) {
+	return +rtrim(readfile(`/sys/class/ieee80211/${name}/index`));
+}
+
+function phy_path(name) {
+	let devpath = realpath(`/sys/class/ieee80211/${name}/device`);
+
+	devpath = replace(devpath, /^\/sys\/devices\//, "");
+	if (match(devpath, /^platform\/.*\/pci/))
+		devpath = replace(devpath, /^platform\//, "");
+	let dev_phys = map(glob(`/sys/class/ieee80211/${name}/device/ieee80211/*`), basename);
+	sort(dev_phys, (a, b) => phy_idx(a) - phy_idx(b));
+
+	let ofs = index(dev_phys, name);
+	if (ofs > 0)
+		devpath += `+${ofs}`;
+
+	return devpath;
+}
+
+function cleanup() {
+	let wlan = board_data.wlan;
+
+	for (let name in wlan)
+		if (substr(name, 0, 3) == "phy")
+			delete wlan[name];
+		else
+			delete wlan[name].info;
+}
+
+function wiphy_get_entry(phy, path) {
+	board_data.wlan ??= {};
+
+	let wlan = board_data.wlan;
+	for (let name in wlan)
+		if (wlan[name].path == path)
+			return wlan[name];
+
+	wlan[phy] = {
+		path: path
+	};
+
+	return wlan[phy];
+}
+
+function wiphy_detect() {
+	let phys = nl.request(nl.const.NL80211_CMD_GET_WIPHY, nl.const.NLM_F_DUMP, { split_wiphy_dump: true });
+	if (!phys)
+		return;
+
+	for (let phy in phys) {
+		let name = phy.wiphy_name;
+		let path = phy_path(name);
+		let info = {
+			antenna_rx: phy.wiphy_antenna_avail_rx,
+			antenna_tx: phy.wiphy_antenna_avail_tx,
+			bands: {},
+		};
+
+		let bands = info.bands;
+		for (let band in phy.wiphy_bands) {
+			if (!band || !band.freqs)
+				continue;
+			let freq = band.freqs[0].freq;
+			let band_info = {};
+			let band_name;
+			if (freq > 50000)
+				band_name = "60G";
+			else if (freq > 5900)
+				band_name = "6G";
+			else if (freq > 4000)
+				band_name = "5G";
+			else
+				band_name = "2G";
+			bands[band_name] = band_info;
+			if (band.ht_capa > 0)
+				band_info.ht = true;
+			if (band.vht_capa > 0)
+				band_info.vht = true;
+			let he_phy_cap = 0;
+
+			for (let ift in band.iftype_data) {
+				if (!ift.he_cap_phy)
+					continue;
+
+				band_info.he = true;
+				he_phy_cap |= ift.he_cap_phy[0];
+				/* TODO: EHT */
+			}
+
+			if (band_name != "2G" &&
+			    (he_phy_cap & 0x18) || ((band.vht_capa >> 2) & 0x3))
+				band_info.max_width = 160;
+			else if (band_name != "2G" &&
+			         (he_phy_cap & 4) || band.vht_capa > 0)
+				band_info.max_width = 80;
+			else if ((band.ht_capa & 0x2) || (he_phy_cap & 0x2))
+				band_info.max_width = 40;
+			else
+				band_info.max_width = 20;
+
+			let modes = band_info.modes = [ "NOHT" ];
+			if (band_info.ht)
+				push(modes, "HT20");
+			if (band_info.vht)
+				push(modes, "VHT20");
+			if (band_info.he)
+				push(modes, "HE20");
+			if (band.ht_capa & 0x2) {
+				push(modes, "HT40");
+				if (band_info.vht)
+					push(modes, "VHT40")
+			}
+			if (he_phy_cap & 0x2)
+				push(modes, "HE40");
+
+			if (band_name == "2G")
+				continue;
+			if (band_info.vht)
+				push(modes, "VHT80");
+			if (he_phy_cap & 4)
+				push(modes, "HE80");
+			if ((band.vht_capa >> 2) & 0x3)
+				push(modes, "VHT160");
+			if (he_phy_cap & 0x18)
+				push(modes, "HE160");
+		}
+
+		let entry = wiphy_get_entry(name, path);
+		entry.info = info;
+	}
+}
+
+cleanup();
+wiphy_detect();
+if (!is_equal(prev_board_data, board_data)) {
+	let new_file = board_file + ".new";
+	unlink(new_file);
+	let f = open(new_file, "wx");
+	if (!f)
+		exit(1);
+	f.write(sprintf("%.J\n", board_data));
+	f.close();
+	rename(new_file, board_file);
+}
diff --git a/package/network/services/dnsmasq/Makefile b/package/network/services/dnsmasq/Makefile
index 241f3463e2fb1f..e33d866304fa92 100644
--- a/package/network/services/dnsmasq/Makefile
+++ b/package/network/services/dnsmasq/Makefile
@@ -10,7 +10,7 @@ include $(TOPDIR)/rules.mk
 PKG_NAME:=dnsmasq
 PKG_UPSTREAM_VERSION:=2.89
 PKG_VERSION:=$(subst test,~~test,$(subst rc,~rc,$(PKG_UPSTREAM_VERSION)))
-PKG_RELEASE:=7
+PKG_RELEASE:=8
 
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_UPSTREAM_VERSION).tar.xz
 PKG_SOURCE_URL:=https://thekelleys.org.uk/dnsmasq/
diff --git a/package/network/services/dnsmasq/files/dnsmasq.init b/package/network/services/dnsmasq/files/dnsmasq.init
index 510d328cd23bd1..138a913f87f3d9 100755
--- a/package/network/services/dnsmasq/files/dnsmasq.init
+++ b/package/network/services/dnsmasq/files/dnsmasq.init
@@ -502,7 +502,7 @@ dhcp_boot_add() {
 
 	[ -n "$serveraddress" ] && [ ! -n "$servername" ] && return 0
 
-	xappend "--dhcp-boot=${networkid:+net:$networkid,}${filename}${servername:+,$servername}${serveraddress:+,$serveraddress}"
+	xappend "--dhcp-boot=${networkid:+tag:$networkid,}${filename}${servername:+,$servername}${serveraddress:+,$serveraddress}"
 
 	config_get_bool force "$cfg" force 0
 
@@ -1244,10 +1244,11 @@ dnsmasq_stop()
 
 add_interface_trigger()
 {
-	local interface ignore
+	local interface ifname ignore
 
 	config_get interface "$1" interface
 	config_get_bool ignore "$1" ignore 0
+	network_get_device ifname "$interface" || ignore=0
 
 	[ -n "$interface" ] && [ $ignore -eq 0 ] && procd_add_interface_trigger "interface.*" "$interface" /etc/init.d/dnsmasq reload
 }
diff --git a/package/network/services/dropbear/Config.in b/package/network/services/dropbear/Config.in
index d4644fc88f9582..7ffe7684d4a47e 100644
--- a/package/network/services/dropbear/Config.in
+++ b/package/network/services/dropbear/Config.in
@@ -12,7 +12,6 @@ config DROPBEAR_CURVE25519
 
 config DROPBEAR_ECC
 	bool "Elliptic curve cryptography (ECC)"
-	default n
 	help
 		Enables basic support for elliptic curve cryptography (ECC)
 		in key exchange and public key authentication.
@@ -25,11 +24,10 @@ config DROPBEAR_ECC
 
 		Increases binary size by about 24 kB (MIPS).
 
-		If full ECC support is required, also select DROPBEAR_ECC_FULL.
+		Note: select DROPBEAR_ECC_FULL if full ECC support is required.
 
 config DROPBEAR_ECC_FULL
 	bool "Elliptic curve cryptography (ECC), full support"
-	default n
 	depends on DROPBEAR_ECC
 	help
 		Enables full support for elliptic curve cryptography (ECC)
@@ -67,46 +65,62 @@ config DROPBEAR_CHACHA20POLY1305
 
 		Increases binary size by about 4 kB (MIPS).
 
+config DROPBEAR_U2F
+	bool "U2F/FIDO support"
+	default y
+	help
+		This option itself doesn't enable any support for U2F/FIDO
+		but subordinate options do:
+
+		- DROPBEAR_ECDSA_SK   - ecdsa-sk keys support
+		  depends on DROPBEAR_ECC ("Elliptic curve cryptography (ECC)")
+		- DROPBEAR_ED25519_SK - ed25519-sk keys support
+		  depends on DROPBEAR_ED25519 ("Ed25519 support")
+
+config DROPBEAR_ECDSA_SK
+	bool "ECDSA-SK support"
+	default y
+	depends on DROPBEAR_U2F && DROPBEAR_ECC
+	help
+		This enables the following public key algorithm:
+		  sk-ecdsa-sha2-nistp256@openssh.com
+
+config DROPBEAR_ED25519_SK
+	bool "Ed25519-SK support"
+	default y
+	depends on DROPBEAR_U2F && DROPBEAR_ED25519
+	help
+		This enables the following public key algorithm:
+		  sk-ssh-ed25519@openssh.com
+
 config DROPBEAR_ZLIB
 	bool "Enable compression"
-	default n
 	help
 		Enables compression using shared zlib library.
 
-		Increases binary size by about 0.1 kB (MIPS) and requires additional 62 kB (MIPS)
-		for a shared zlib library.
+		Increases binary size by about 0.1 kB (MIPS) and requires
+		additional 62 kB (MIPS) for a shared zlib library.
 
 config DROPBEAR_UTMP
 	bool "Utmp support"
-	default n
 	depends on BUSYBOX_CONFIG_FEATURE_UTMP
 	help
-		This enables dropbear utmp support, the file /var/run/utmp is used to
-		track who is currently logged in.
+		This enables dropbear utmp support, the file /var/run/utmp is
+		used to track who is currently logged in.
 
 config DROPBEAR_PUTUTLINE
 	bool "Pututline support"
-	default n
 	depends on DROPBEAR_UTMP
 	help
-		Dropbear will use pututline() to write the utmp structure into the utmp file.
+		Dropbear will use pututline() to write the utmp structure into
+		the utmp file.
 
 config DROPBEAR_DBCLIENT
 	bool "Build dropbear with dbclient"
 	default y
 
-config DROPBEAR_DBCLIENT_AGENTFORWARD
-	bool "Enable agent forwarding in dbclient"
-	default y
-	depends on DROPBEAR_DBCLIENT
-
-config DROPBEAR_SCP
-	bool "Build dropbear with scp"
-	default y
-
 config DROPBEAR_ASKPASS
 	bool "Enable askpass helper support"
-	default n
 	depends on DROPBEAR_DBCLIENT
 	help
 		This enables support for ssh-askpass helper in dropbear client
@@ -114,8 +128,70 @@ config DROPBEAR_ASKPASS
 
 		Increases binary size by about 0.1 kB (MIPS).
 
+config DROPBEAR_DBCLIENT_AGENTFORWARD
+	bool "Enable agent forwarding in dbclient [LEGACY/SECURITY]"
+	default y
+	depends on DROPBEAR_DBCLIENT
+	help
+		Increases binary size by about 0.1 kB (MIPS).
+
+		Security notes:
+
+		SSH agent forwarding might cause security issues (locally and
+		on the jump machine).
+
+		Hovewer, it's enabled by default for compatibility with
+		previous OpenWrt/dropbear releases.
+
+		Consider DISABLING this option if you're building own OpenWrt
+		image.
+
+		Also see DROPBEAR_AGENTFORWARD (agent forwarding in dropbear
+		server itself).
+
+config DROPBEAR_SCP
+	bool "Build dropbear with scp"
+	default y
+
 config DROPBEAR_AGENTFORWARD
-	bool "Enable agent forwarding"
+	bool "Enable agent forwarding [LEGACY/SECURITY]"
 	default y
+	help
+		Increases binary size by about 0.1 kB (MIPS).
+
+		Security notes:
+
+		SSH agent forwarding might cause security issues (locally and
+		on the jump machine).
+
+		Hovewer, it's enabled by default for compatibility with
+		previous OpenWrt/dropbear releases.
+
+		Consider DISABLING this option if you're building own OpenWrt
+		image.
+
+		Also see DROPBEAR_DBCLIENT_AGENTFORWARD (agent forwarding in
+		dropbear client) if DROPBEAR_DBCLIENT is selected.
+
+config DROPBEAR_MODERN_ONLY
+	bool "Use modern crypto only [BREAKS COMPATIBILITY]"
+	select DROPBEAR_ED25519
+	select DROPBEAR_CURVE25519
+	select DROPBEAR_CHACHA20POLY1305
+	help
+		This option enables:
+		 - Chacha20-Poly1305
+		 - Curve25519
+		 - Ed25519
+		and disables:
+		 - AES
+		 - RSA
+		 - SHA1
+
+		Reduces binary size by about 64 kB (MIPS) from default
+		configuration.
+
+		Consider enabling this option if you're building own OpenWrt
+		image and using modern SSH software everywhere.
 
 endmenu
diff --git a/package/network/services/dropbear/Makefile b/package/network/services/dropbear/Makefile
index e98e995ba7b9a3..2d7ce75b8d0c75 100644
--- a/package/network/services/dropbear/Makefile
+++ b/package/network/services/dropbear/Makefile
@@ -8,14 +8,14 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=dropbear
-PKG_VERSION:=2022.82
-PKG_RELEASE:=5
+PKG_VERSION:=2022.83
+PKG_RELEASE:=1
 
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
 PKG_SOURCE_URL:= \
 	https://matt.ucc.asn.au/dropbear/releases/ \
 	https://dropbear.nl/mirror/releases/
-PKG_HASH:=3a038d2bbc02bf28bbdd20c012091f741a3ec5cbe460691811d714876aad75d1
+PKG_HASH:=bc5a121ffbc94b5171ad5ebe01be42746d50aa797c9549a4639894a16749443b
 
 PKG_LICENSE:=MIT
 PKG_LICENSE_FILES:=LICENSE libtomcrypt/LICENSE libtommath/LICENSE
@@ -31,9 +31,11 @@ PKG_CONFIG_DEPENDS:= \
 	CONFIG_TARGET_INIT_PATH CONFIG_DROPBEAR_ECC CONFIG_DROPBEAR_ECC_FULL \
 	CONFIG_DROPBEAR_CURVE25519 CONFIG_DROPBEAR_ZLIB \
 	CONFIG_DROPBEAR_ED25519 CONFIG_DROPBEAR_CHACHA20POLY1305 \
+	CONFIG_DROPBEAR_U2F CONFIG_DROPBEAR_ECDSA_SK CONFIG_DROPBEAR_ED25519_SK \
 	CONFIG_DROPBEAR_UTMP CONFIG_DROPBEAR_PUTUTLINE \
 	CONFIG_DROPBEAR_DBCLIENT CONFIG_DROPBEAR_SCP CONFIG_DROPBEAR_ASKPASS \
-	CONFIG_DROPBEAR_DBCLIENT_AGENTFORWARD CONFIG_DROPBEAR_AGENTFORWARD
+	CONFIG_DROPBEAR_DBCLIENT_AGENTFORWARD CONFIG_DROPBEAR_AGENTFORWARD \
+	CONFIG_DROPBEAR_MODERN_ONLY
 
 include $(INCLUDE_DIR)/package.mk
 
@@ -68,10 +70,11 @@ define Package/dropbear/description
 endef
 
 define Package/dropbear/conffiles
-$(if $(CONFIG_DROPBEAR_ED25519),/etc/dropbear/dropbear_ed25519_host_key)
-$(if $(CONFIG_DROPBEAR_ECC),/etc/dropbear/dropbear_ecdsa_host_key)
-/etc/dropbear/dropbear_rsa_host_key
 /etc/config/dropbear
+/etc/dropbear/authorized_keys
+/etc/dropbear/dropbear_ecdsa_host_key
+/etc/dropbear/dropbear_ed25519_host_key
+/etc/dropbear/dropbear_rsa_host_key
 endef
 
 define Package/dropbearconvert
@@ -99,79 +102,100 @@ CONFIGURE_ARGS += \
 
 ##############################################################################
 #
-#   option|value - add option to localoptions.h
-# !!option|value - replace option in sysoptions.h
+#   option,value - add option to localoptions.h
+# !!option,value - replace option in sysoptions.h
 #
 ##############################################################################
 
+# adjust allowed shell list (if getusershell(3) is missing):
+# - COMPAT_USER_SHELLS
 # remove protocol idented software version number:
 # - LOCAL_IDENT
 # disable legacy/unsafe methods and unused functionality:
 # - DROPBEAR_CLI_NETCAT
 # - DROPBEAR_DSS
 # - DO_MOTD
+# - DROPBEAR_DH_GROUP14_SHA1
+# - DROPBEAR_SHA1_HMAC
 DB_OPT_COMMON = \
-	DEFAULT_PATH|"$(TARGET_INIT_PATH)" \
-	!!LOCAL_IDENT|"SSH-2.0-dropbear" \
-	DROPBEAR_CLI_NETCAT|0 \
-	DROPBEAR_DSS|0 \
-	DO_MOTD|0 \
+	!!LOCAL_IDENT,"SSH-2.0-dropbear" \
+	COMPAT_USER_SHELLS,"/bin/ash","/bin/sh" \
+	DEFAULT_PATH,"$(TARGET_INIT_PATH)" \
+	DEFAULT_ROOT_PATH,"$(TARGET_INIT_PATH)" \
+	DROPBEAR_DSS,0 \
+	DROPBEAR_CLI_NETCAT,0 \
+	DO_MOTD,0 \
+	DROPBEAR_DH_GROUP14_SHA1,0 \
+	DROPBEAR_SHA1_HMAC,0 \
 
 
 ##############################################################################
 #
-#   option|config|enabled|disabled = add option to localoptions.h
-# !!option|config|enabled|disabled = replace option in sysoptions.h
+#   option,config,enabled,disabled = add option to localoptions.h
+# !!option,config,enabled,disabled = replace option in sysoptions.h
 #
 #   option := (config) ? enabled : disabled
 #
 ##############################################################################
 
 DB_OPT_CONFIG = \
-	DROPBEAR_CURVE25519|CONFIG_DROPBEAR_CURVE25519|1|0 \
-	DROPBEAR_ED25519|CONFIG_DROPBEAR_ED25519|1|0 \
-	DROPBEAR_SK_ED25519|CONFIG_DROPBEAR_ED25519|1|0 \
-	DROPBEAR_CHACHA20POLY1305|CONFIG_DROPBEAR_CHACHA20POLY1305|1|0 \
-	DROPBEAR_ECDSA|CONFIG_DROPBEAR_ECC|1|0 \
-	DROPBEAR_SK_ECDSA|CONFIG_DROPBEAR_ECC|1|0 \
-	DROPBEAR_ECDH|CONFIG_DROPBEAR_ECC|1|0 \
-	!!DROPBEAR_ECC_384|CONFIG_DROPBEAR_ECC_FULL|1|0 \
-	!!DROPBEAR_ECC_521|CONFIG_DROPBEAR_ECC_FULL|1|0 \
-	DROPBEAR_CLI_ASKPASS_HELPER|CONFIG_DROPBEAR_ASKPASS|1|0 \
-	DROPBEAR_CLI_AGENTFWD|CONFIG_DROPBEAR_DBCLIENT_AGENTFORWARD|1|0 \
-	DROPBEAR_SVR_AGENTFWD|CONFIG_DROPBEAR_AGENTFORWARD|1|0 \
+	!!DROPBEAR_ECC_384,CONFIG_DROPBEAR_ECC_FULL,1,0 \
+	!!DROPBEAR_ECC_521,CONFIG_DROPBEAR_ECC_FULL,1,0 \
+	DROPBEAR_CURVE25519,CONFIG_DROPBEAR_CURVE25519,1,0 \
+	DROPBEAR_CHACHA20POLY1305,CONFIG_DROPBEAR_CHACHA20POLY1305,1,0 \
+	DROPBEAR_ED25519,CONFIG_DROPBEAR_ED25519,1,0 \
+	DROPBEAR_ECDSA,CONFIG_DROPBEAR_ECC,1,0 \
+	DROPBEAR_ECDH,CONFIG_DROPBEAR_ECC,1,0 \
+	DROPBEAR_SK_KEYS,CONFIG_DROPBEAR_U2F,1,0 \
+	DROPBEAR_SK_ECDSA,CONFIG_DROPBEAR_ECDSA_SK,1,0 \
+	DROPBEAR_SK_ED25519,CONFIG_DROPBEAR_ED25519_SK,1,0 \
+	DROPBEAR_CLI_ASKPASS_HELPER,CONFIG_DROPBEAR_ASKPASS,1,0 \
+	DROPBEAR_CLI_AGENTFWD,CONFIG_DROPBEAR_DBCLIENT_AGENTFORWARD,1,0 \
+	DROPBEAR_SVR_AGENTFWD,CONFIG_DROPBEAR_AGENTFORWARD,1,0 \
+	DROPBEAR_AES128,CONFIG_DROPBEAR_MODERN_ONLY,0,1 \
+	DROPBEAR_AES256,CONFIG_DROPBEAR_MODERN_ONLY,0,1 \
+	DROPBEAR_ENABLE_CTR_MODE,CONFIG_DROPBEAR_MODERN_ONLY,0,1 \
+	DROPBEAR_RSA,CONFIG_DROPBEAR_MODERN_ONLY,0,1 \
+	DROPBEAR_RSA_SHA1,CONFIG_DROPBEAR_MODERN_ONLY,0,1 \
 
 
 TARGET_CFLAGS += -DARGTYPE=3
 
+xsedx:=$(shell printf '\027')
+
 db_opt_add     =echo '\#define $(1) $(2)' >> $(PKG_BUILD_DIR)/localoptions.h
-db_opt_replace =$(ESED) 's,^(\#define $(1)) .*$$$$,\1 $(2),g' $(PKG_BUILD_DIR)/sysoptions.h
+db_opt_replace =$(ESED) '/^\#define $(1) .*$$$$/{h;:a;$$$$!n;/^\#.+$$$$/bb;/^$$$$/bb;H;ba;:b;x;s$(xsedx)^.+$$$$$(xsedx)\#define $(1) $(2)$(xsedx)p;x};p' -n $(PKG_BUILD_DIR)/sysoptions.h
 
 define Build/Configure/dropbear_headers
 	$(strip $(foreach s,$(DB_OPT_COMMON), \
-	  $(if $(filter !!%,$(word 1,$(subst |, ,$(s)))), \
-	    $(call db_opt_replace,$(patsubst !!%,%,$(word 1,$(subst |, ,$(s)))),$(word 2,$(subst |, ,$(s)))), \
-	    $(call db_opt_add,$(word 1,$(subst |, ,$(s))),$(word 2,$(subst |, ,$(s)))) \
+	  $(if $(filter !!%,$(word 1,$(subst $(comma),$(space),$(s)))), \
+	    $(call db_opt_replace,$(patsubst !!%,%,$(word 1,$(subst $(comma),$(space),$(s)))),$(subst $(space),$(comma),$(wordlist 2,$(words $(subst $(comma),$(space),$(s))),$(subst $(comma),$(space),$(s))))), \
+	    $(call db_opt_add,$(word 1,$(subst $(comma),$(space),$(s))),$(subst $(space),$(comma),$(wordlist 2,$(words $(subst $(comma),$(space),$(s))),$(subst $(comma),$(space),$(s))))) \
 	  ) ; \
 	))
 
 	$(strip $(foreach s,$(DB_OPT_CONFIG), \
-	  $(if $(filter !!%,$(word 1,$(subst |, ,$(s)))), \
-	    $(call db_opt_replace,$(patsubst !!%,%,$(word 1,$(subst |, ,$(s)))),$(if $($(word 2,$(subst |, ,$(s)))),$(word 3,$(subst |, ,$(s))),$(word 4,$(subst |, ,$(s))))), \
-	    $(call db_opt_add,$(word 1,$(subst |, ,$(s))),$(if $($(word 2,$(subst |, ,$(s)))),$(word 3,$(subst |, ,$(s))),$(word 4,$(subst |, ,$(s))))) \
+	  $(if $(filter !!%,$(word 1,$(subst $(comma),$(space),$(s)))), \
+	    $(call db_opt_replace,$(patsubst !!%,%,$(word 1,$(subst $(comma),$(space),$(s)))),$(if $($(word 2,$(subst $(comma),$(space),$(s)))),$(word 3,$(subst $(comma),$(space),$(s))),$(word 4,$(subst $(comma),$(space),$(s))))), \
+	    $(call db_opt_add,$(word 1,$(subst $(comma),$(space),$(s))),$(if $($(word 2,$(subst $(comma),$(space),$(s)))),$(word 3,$(subst $(comma),$(space),$(s))),$(word 4,$(subst $(comma),$(space),$(s))))) \
 	  ) ; \
 	))
 endef
 
-define Build/Configure
-	: > $(PKG_BUILD_DIR)/localoptions.h
+define Build/Configure/dropbear_objects
+	grep -ERZl -e '($(subst $(space),|,$(strip $(sort $(patsubst !!%,%,$(foreach s,$(DB_OPT_COMMON) $(DB_OPT_CONFIG),$(word 1,$(subst $(comma),$(space),$(s)))))))))' \
+	$(PKG_BUILD_DIR)/ | sed -zE 's/^(.+)\.[^.]+$$$$/\1.o/' | sort -uV | xargs -0 -r rm -fv || :
+endef
 
+define Build/Configure
+	rm -f $(PKG_BUILD_DIR)/localoptions.h
 	$(Build/Configure/Default)
 
+	: > $(PKG_BUILD_DIR)/localoptions.h
 	$(Build/Configure/dropbear_headers)
 
-	# Enforce rebuild of svr-chansession.c
-	rm -f $(PKG_BUILD_DIR)/svr-chansession.o
+	# Enforce rebuild of files depending on configured options
+	$(Build/Configure/dropbear_objects)
 
 	# Rebuild them on config change
 	+$(MAKE) -C $(PKG_BUILD_DIR)/libtomcrypt clean
@@ -181,10 +205,12 @@ endef
 define Build/Compile
 	+$(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR) \
 		$(TARGET_CONFIGURE_OPTS) \
+		IGNORE_SPEED=1 \
 		PROGRAMS="dropbear $(if $(CONFIG_DROPBEAR_DBCLIENT),dbclient,) dropbearkey $(if $(CONFIG_DROPBEAR_SCP),scp,)" \
 		MULTI=1 SCPPROGRESS=1
 	+$(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR) \
 		$(TARGET_CONFIGURE_OPTS) \
+		IGNORE_SPEED=1 \
 		PROGRAMS="dropbearconvert"
 endef
 
@@ -202,9 +228,7 @@ define Package/dropbear/install
 	$(INSTALL_DIR) $(1)/etc/dropbear
 	$(INSTALL_DIR) $(1)/lib/preinit
 	$(INSTALL_DATA) ./files/dropbear.failsafe $(1)/lib/preinit/99_10_failsafe_dropbear
-	$(if $(CONFIG_DROPBEAR_ED25519),touch $(1)/etc/dropbear/dropbear_ed25519_host_key)
-	$(if $(CONFIG_DROPBEAR_ECC),touch $(1)/etc/dropbear/dropbear_ecdsa_host_key)
-	touch $(1)/etc/dropbear/dropbear_rsa_host_key
+	$(foreach f,$(filter /etc/dropbear/%,$(Package/dropbear/conffiles)),$(if $(wildcard $(TOPDIR)/files/$(f)),chmod 0600 $(TOPDIR)/files/$(f) || :; ))
 endef
 
 define Package/dropbearconvert/install
diff --git a/package/network/services/dropbear/files/dropbear.failsafe b/package/network/services/dropbear/files/dropbear.failsafe
index 97bd12d58a1891..417265babed6df 100755
--- a/package/network/services/dropbear/files/dropbear.failsafe
+++ b/package/network/services/dropbear/files/dropbear.failsafe
@@ -1,9 +1,61 @@
 #!/bin/sh
 
+_dropbear()
+{
+	/usr/sbin/dropbear "$@" </dev/null >/dev/null 2>&1
+}
+
+_dropbearkey()
+{
+	/usr/bin/dropbearkey "$@" </dev/null >/dev/null 2>&1
+}
+
+_ensurekey()
+{
+	_dropbearkey -y -f "$1" && return
+	rm -f "$1"
+	_dropbearkey -f "$@" || {
+		rm -f "$1"
+		return 1
+	}
+}
+
+ktype_all='ed25519 ecdsa rsa'
+
 failsafe_dropbear () {
-	dropbearkey -t rsa -s 1024 -f /tmp/dropbear_rsa_failsafe_host_key
-	dropbearkey -t ed25519 -f /tmp/dropbear_ed25519_failsafe_host_key
-	dropbear -r /tmp/dropbear_rsa_failsafe_host_key -r /tmp/dropbear_ed25519_failsafe_host_key <> /dev/null 2>&1
+	local kargs kcount ktype tkey
+
+	kargs=
+	kcount=0
+	for ktype in ${ktype_all} ; do
+		tkey="/tmp/dropbear_failsafe_${ktype}_host_key"
+
+		case "${ktype}" in
+		ed25519) _ensurekey "${tkey}" -t ed25519 ;;
+		ecdsa)   _ensurekey "${tkey}" -t ecdsa -s 256 ;;
+		rsa)     _ensurekey "${tkey}" -t rsa   -s 1024 ;;
+		*)
+			echo "unknown key type: ${ktype}" >&2
+			continue
+		;;
+		esac
+
+		[ -s "${tkey}" ] || {
+			rm -f "${tkey}"
+			continue
+		}
+
+		chmod 0400 "${tkey}"
+		kargs="${kargs}${kargs:+ }-r ${tkey}"
+		kcount=$((kcount+1))
+	done
+
+	[ "${kcount}" != 0 ] || {
+		echo 'DROPBEAR IS BROKEN' >&2
+		return 1
+	}
+
+	_dropbear ${kargs}
 }
 
 boot_hook_add failsafe failsafe_dropbear
diff --git a/package/network/services/dropbear/files/dropbear.init b/package/network/services/dropbear/files/dropbear.init
index a40b5f7baeea0f..21570987c439b1 100755
--- a/package/network/services/dropbear/files/dropbear.init
+++ b/package/network/services/dropbear/files/dropbear.init
@@ -12,28 +12,52 @@ PIDCOUNT=0
 
 extra_command "killclients" "Kill ${NAME} processes except servers and yourself"
 
+# most of time real_stat() will be failing
+# due to missing "stat" binary (by default)
+real_stat() { env stat -L "$@" 2>/dev/null ; }
+dumb_stat() { ls -Ldln "$1" | tr -s '\t ' ' ' ; }
+stat_perm()  { real_stat -c '%A' "$1" || dumb_stat "$1" | cut -d ' ' -f 1 ; }
+stat_owner() { real_stat -c '%u' "$1" || dumb_stat "$1" | cut -d ' ' -f 3 ; }
+
 _dropbearkey()
 {
-	/usr/bin/dropbearkey "$@" 0<&- 1>&- 2>&-
+	/usr/bin/dropbearkey "$@" </dev/null >/dev/null 2>&1
 }
 
-# $1 - host key file name
-hk_verify()
+# $1 - file name (host key or config)
+file_verify()
 {
 	[ -f "$1" ] || return 1
-	[ -s "$1" ] || return 2
-	_dropbearkey -y -f "$1" || return 3
+	# checking file ownership
+	[ "$(stat_owner "$1")" = "0" ] || {
+		chown 0 "$1"
+		[ "$(stat_owner "$1")" = "0" ] || return 2
+	}
+	# checking file permissions
+	[ "$(stat_perm "$1")" = "-rw-------" ] || {
+		chmod 0600 "$1"
+		[ "$(stat_perm "$1")" = "-rw-------" ] || return 3
+	}
+	# file is host key or not?
+	# if $2 is empty string - file is "host key"
+	# if $2 is non-empty string - file is "config"
+	[ -z "$2" ] || return 0
+	# checking file contents (finally)
+	[ -s "$1" ] || return 4
+	_dropbearkey -y -f "$1" || return 5
 	return 0
 }
 
-# $1 - hk_verify() return code
-hk_errmsg()
+# $1 - file_verify() return code
+file_errmsg()
 {
 	case "$1" in
 	0) ;;
 	1) echo "file does not exist" ;;
-	2) echo "file has zero length" ;;
-	3) echo "file is not valid host key or not supported" ;;
+	2) echo "file has wrong owner (must be owned by root)" ;;
+	3) echo "file has wrong permissions (must not have group/other write bit)" ;;
+	4) echo "file has zero length" ;;
+	5) echo "file is not valid host key or not supported" ;;
 	*) echo "unknown error" ;;
 	esac
 }
@@ -43,73 +67,97 @@ hk_errmsg()
 hk_config()
 {
 	local x m
-	hk_verify "$2"; x=$?
-	case "$x" in
-	0)	procd_append_param command -r "$2"
-		;;
-	*)	m=$(hk_errmsg "$x")
-		logger -t "${NAME}" -p daemon.warn \
-		  "option '$1', value '$2': $m, skipping"
-		;;
-	esac
+	file_verify "$2" ; x=$?
+	if [ "$x" = 0 ] ; then
+		procd_append_param command -r "$2"
+		return
+	fi
+	m=$(file_errmsg "$x")
+	logger -s -t "${NAME}" -p daemon.warn \
+	  "Option '$1', skipping '$2': $m"
 }
 
 # $1 - host key file name
-hk_config__keyfile()
-{
-	hk_config 'keyfile' "$1"
-}
+hk_config__keyfile() { hk_config keyfile "$1" ; }
+
+ktype_all='ed25519 ecdsa rsa'
 
 hk_generate_as_needed()
 {
-	local kdir kgen ktype tdir kcount tfile
-	kdir='/etc/dropbear'
+	local hk_cfg_dir kgen ktype kfile hk_tmp_dir
+	hk_cfg_dir='/etc/dropbear'
+
+	[ -d "${hk_cfg_dir}" ] || mkdir -p "${hk_cfg_dir}"
+
+	kgen=
+	for ktype in ${ktype_all} ; do
+		kfile="${hk_cfg_dir}/dropbear_${ktype}_host_key"
 
-	kgen=''
-	for ktype in ed25519 ecdsa rsa; do
-		hk_verify "${kdir}/dropbear_${ktype}_host_key" && continue
+		if file_verify "${kfile}" ; then continue ; fi
 
-		kgen="${kgen} ${ktype}"
+		kgen="${kgen}${kgen:+ }${ktype}"
 	done
 
-	[ -z "${kgen}" ] && return
+	# all keys are sane?
+	[ -n "${kgen}" ] || return 0
 
-	tdir=$(mktemp -d); chmod 0700 "${tdir}"
+	hk_tmp_dir=$(mktemp -d)
+	# system in bad state?
+	[ -n "${hk_tmp_dir}" ] || return 1
 
-	kcount=0
-	for ktype in ${kgen}; do
-		tfile="${tdir}/dropbear_${ktype}_host_key"
+	chmod 0700 "${hk_tmp_dir}"
 
-		if ! _dropbearkey -t ${ktype} -f "${tfile}"; then
+	for ktype in ${kgen} ; do
+		kfile="${hk_tmp_dir}/dropbear_${ktype}_host_key"
+
+		if ! _dropbearkey -t ${ktype} -f "${kfile}" ; then
 			# unsupported key type
-			rm -f "${tfile}"
+			rm -f "${kfile}"
 			continue
 		fi
 
-		kcount=$((kcount+1))
+		chmod 0600 "${kfile}"
+	done
+
+	kgen=
+	for ktype in ${ktype_all} ; do
+		kfile="${hk_tmp_dir}/dropbear_${ktype}_host_key"
+
+		[ -s "${kfile}" ] || continue
+
+		kgen="${kgen}${kgen:+ }${ktype}"
 	done
 
-	if [ ${kcount} -ne 0 ]; then
-		mkdir -p "${kdir}"; chmod 0700 "${kdir}"; chown root "${kdir}"
-		mv -f "${tdir}/"* "${kdir}/"
+	if [ -n "${kgen}" ] ; then
+		for ktype in ${kgen} ; do
+			kfile="${hk_tmp_dir}/dropbear_${ktype}_host_key"
+			[ -s "${kfile}" ] || continue
+			mv -f "${kfile}" "${hk_cfg_dir}/"
+		done
 	fi
 
-	rm -rf "${tdir}"
+	rm -rf "${hk_tmp_dir}"
+
+	# cleanup empty files
+	for ktype in ${ktype_all} ; do
+		kfile="${hk_cfg_dir}/dropbear_${ktype}_host_key"
+
+		[ -s "${kfile}" ] || rm -f "${kfile}"
+	done
 }
 
-append_ports()
+# $1 - list with whitespace-separated elements
+normalize_list()
 {
-	local ipaddrs="$1"
-	local port="$2"
-
-	[ -z "$ipaddrs" ] && {
-		procd_append_param command -p "$port"
-		return
-	}
+	printf '%s' "$1" | tr -s ' \r\n\t' ' ' | sed -E 's/^ //;s/ $//'
+}
 
-	for addr in $ipaddrs; do
-		procd_append_param command -p "$addr:$port"
-	done
+warn_multiple_interfaces()
+{
+	logger -t "${NAME}" -p daemon.warn \
+	  "Option '$1' should specify SINGLE interface but instead it lists interfaces: $2"
+	logger -t "${NAME}" -p daemon.warn \
+	  "Consider creating per-interface instances instead!"
 }
 
 validate_section_dropbear()
@@ -117,6 +165,7 @@ validate_section_dropbear()
 	uci_load_validate dropbear dropbear "$1" "$2" \
 		'PasswordAuth:bool:1' \
 		'enable:bool:1' \
+		'DirectInterface:string' \
 		'Interface:string' \
 		'GatewayPorts:bool:0' \
 		'ForceCommand:string' \
@@ -129,59 +178,181 @@ validate_section_dropbear()
 		'SSHKeepAlive:uinteger:300' \
 		'IdleTimeout:uinteger:0' \
 		'MaxAuthTries:uinteger:3' \
-		'RecvWindowSize:uinteger:0' \
+		'RecvWindowSize:uinteger:262144' \
 		'mdns:bool:1'
 }
 
 dropbear_instance()
 {
-	local ipaddrs
-
 	[ "$2" = 0 ] || {
 		echo "validation failed"
 		return 1
 	}
 
-	[ -n "${Interface}" ] && {
-		[ -n "${BOOT}" ] && return 0
+	[ "${enable}" = "1" ] || return 1
 
-		network_get_ipaddrs_all ipaddrs "${Interface}" || {
-			echo "interface ${Interface} has no physdev or physdev has no suitable ip"
-			return 1
-		}
-	}
+	local iface ndev ipaddrs
 
-	[ "${enable}" = "0" ] && return 1
-	PIDCOUNT="$(( ${PIDCOUNT} + 1))"
-	local pid_file="/var/run/${NAME}.${PIDCOUNT}.pid"
+	# 'DirectInterface' should specify single interface
+	# but end users may misinterpret this setting
+	DirectInterface=$(normalize_list "${DirectInterface}")
+
+	# 'Interface' should specify single interface
+	# but end users are often misinterpret this setting
+	Interface=$(normalize_list "${Interface}")
 
-	# Increase default receive window size to increase
-	# throughput on high latency links
-	if [ "${RecvWindowSize}" -eq "0" ]; then
-		RecvWindowSize="262144"
+	if [ -n "${Interface}" ] ; then
+		if [ -n "${DirectInterface}" ] ; then
+			logger -t "${NAME}" -p daemon.warn \
+			  "Option 'DirectInterface' takes precedence over 'Interface'"
+		else
+			logger -t "${NAME}" -p daemon.info \
+			  "Option 'Interface' binds to address(es) but not to interface"
+			logger -t "${NAME}" -p daemon.info \
+			  "Consider using option 'DirectInterface' to bind directly to interface"
+		fi
+	fi
+
+	# handle 'DirectInterface'
+	iface=$(echo "${DirectInterface}" | awk '{print $1}')
+	case "${DirectInterface}" in
+	*\ *)
+		warn_multiple_interfaces DirectInterface "${DirectInterface}"
+		logger -t "${NAME}" -p daemon.warn \
+		  "Using network interface '${iface}' for direct binding"
+	;;
+	esac
+	while [ -n "${iface}" ] ; do
+		# if network is available (even during boot) - proceed
+		if network_is_up "${iface}" ; then break ; fi
+		# skip during boot
+		[ -z "${BOOT}" ] || return 0
+
+		logger -t "${NAME}" -p daemon.crit \
+		  "Network interface '${iface}' is not available!"
+		return 1
+	done
+	while [ -n "${iface}" ] ; do
+		# ${iface} is logical (higher level) interface name
+		# ${ndev} is 'real' interface name
+		# e.g.: if ${iface} is 'lan' (default LAN interface) then ${ndev} is 'br-lan'
+		network_get_device ndev "${iface}"
+		[ -z "${ndev}" ] || break
+
+		logger -t "${NAME}" -p daemon.crit \
+		  "Missing network device for network interface '${iface}'!"
+		return 1
+	done
+	if [ -n "${iface}" ] ; then
+		logger -t "${NAME}" -p daemon.info \
+		  "Using network interface '${iface}' (network device '${ndev}') for direct binding"
 	fi
+	# handle 'Interface'
+	while [ -z "${iface}" ] ; do
+		[ -n "${Interface}" ] || break
+
+		# skip during boot
+		[ -z "${BOOT}" ] || return 0
+
+		case "${Interface}" in
+		*\ *)
+			warn_multiple_interfaces Interface "${Interface}"
+		;;
+		esac
+
+		local c=0
+		# sysoptions.h
+		local DROPBEAR_MAX_PORTS=10
+
+		local a n if_ipaddrs
+		for n in ${Interface} ; do
+			[ -n "$n" ] || continue
+
+			if_ipaddrs=
+			network_get_ipaddrs_all if_ipaddrs "$n"
+			[ -n "${if_ipaddrs}" ] || {
+				logger -s -t "${NAME}" -p daemon.err \
+				  "Network interface '$n' has no suitable IP address(es)!"
+				continue
+			}
+
+			[ $c -le ${DROPBEAR_MAX_PORTS} ] || {
+				logger -s -t "${NAME}" -p daemon.err \
+				  "Network interface '$n' is NOT listened due to option limit exceed!"
+				continue
+			}
+
+			for a in ${if_ipaddrs} ; do
+				[ -n "$a" ] || continue
+
+				c=$((c+1))
+				if [ $c -le ${DROPBEAR_MAX_PORTS} ] ; then
+					ipaddrs="${ipaddrs} $a"
+					continue
+				fi
+
+				logger -t "${NAME}" -p daemon.err \
+				  "Endpoint '$a:${Port}' on network interface '$n' is NOT listened due to option limit exceed!"
+			done
+		done
+		break
+	done
+
+	PIDCOUNT="$(( ${PIDCOUNT} + 1))"
+	local pid_file="/var/run/${NAME}.${PIDCOUNT}.pid"
 
 	procd_open_instance
 	procd_set_param command "$PROG" -F -P "$pid_file"
+	if [ -n "${iface}" ] ; then
+		# if ${iface} is non-empty then ${ndev} is non-empty too
+		procd_append_param command -l "${ndev}" -p "${Port}"
+	else
+		if [ -z "${ipaddrs}" ] ; then
+			procd_append_param command -p "${Port}"
+		else
+			local a
+			for a in ${ipaddrs} ; do
+				[ -n "$a" ] || continue
+				procd_append_param command -p "$a:${Port}"
+			done
+		fi
+	fi
 	[ "${PasswordAuth}" -eq 0 ] && procd_append_param command -s
 	[ "${GatewayPorts}" -eq 1 ] && procd_append_param command -a
 	[ -n "${ForceCommand}" ] && procd_append_param command -c "${ForceCommand}"
 	[ "${RootPasswordAuth}" -eq 0 ] && procd_append_param command -g
 	[ "${RootLogin}" -eq 0 ] && procd_append_param command -w
+	config_list_foreach "$1" 'keyfile' hk_config__keyfile
 	if [ -n "${rsakeyfile}" ]; then
-		logger -t ${NAME} -p daemon.warn \
-			"option 'rsakeyfile' is considered to be deprecated and" \
-			"will be removed in future releases, use 'keyfile' instead"
+		logger -s -t "${NAME}" -p daemon.crit \
+		  "Option 'rsakeyfile' is considered to be DEPRECATED and will be REMOVED in future releases, use 'keyfile' list instead"
+		sed -i.before-upgrade -E -e 's/option(\s+)rsakeyfile/list keyfile/' \
+		  "/etc/config/${NAME}"
+		logger -s -t "${NAME}" -p daemon.crit \
+		  "Auto-transition 'option rsakeyfile' => 'list keyfile' in /etc/config/${NAME} is done, please verify your configuration"
 		hk_config 'rsakeyfile' "${rsakeyfile}"
 	fi
-	config_list_foreach "$1" "keyfile" hk_config__keyfile
 	[ -n "${BannerFile}" ] && procd_append_param command -b "${BannerFile}"
-	append_ports "${ipaddrs}" "${Port}"
 	[ "${IdleTimeout}" -ne 0 ] && procd_append_param command -I "${IdleTimeout}"
 	[ "${SSHKeepAlive}" -ne 0 ] && procd_append_param command -K "${SSHKeepAlive}"
 	[ "${MaxAuthTries}" -ne 0 ] && procd_append_param command -T "${MaxAuthTries}"
-	[ "${RecvWindowSize}" -gt 0 -a "${RecvWindowSize}" -le 1048576 ] && \
+	[ "${RecvWindowSize}" -gt 0 ] && {
+		# NB: OpenWrt increases receive window size to increase throughput on high latency links
+		# ref: validate_section_dropbear()
+		# default receive window size is 24576 (DEFAULT_RECV_WINDOW in default_options.h)
+
+		# sysoptions.h
+		local MAX_RECV_WINDOW=10485760
+		if [ "${RecvWindowSize}" -gt ${MAX_RECV_WINDOW} ] ; then
+			# separate logging is required because syslog misses dropbear's message
+			#   Bad recv window '${RecvWindowSize}', using ${MAX_RECV_WINDOW}
+			# it's probably dropbear issue but we should handle this and notify user
+			logger -s -t "${NAME}" -p daemon.warn \
+			  "Option 'RecvWindowSize' is too high (${RecvWindowSize}), limiting to ${MAX_RECV_WINDOW}"
+			RecvWindowSize=${MAX_RECV_WINDOW}
+		fi
 		procd_append_param command -W "${RecvWindowSize}"
+	}
 	[ "${mdns}" -ne 0 ] && procd_add_mdns "ssh" "tcp" "$Port" "daemon=dropbear"
 	procd_set_param respawn
 	procd_close_instance
@@ -189,10 +360,21 @@ dropbear_instance()
 
 load_interfaces()
 {
-	config_get interface "$1" Interface
+	local enable
 	config_get enable "$1" enable 1
-
-	[ "${enable}" = "1" ] && interfaces=" ${interface} ${interfaces}"
+	[ "${enable}" = "1" ] || return 0
+
+	local direct_iface iface
+	config_get direct_iface "$1" DirectInterface
+	direct_iface=$(normalize_list "${direct_iface}")
+	# 'DirectInterface' takes precedence over 'Interface'
+	if [ -n "${direct_iface}" ] ; then
+		iface=$(echo "${direct_iface}" | awk '{print $1}')
+	else
+		config_get iface "$1" Interface
+		iface=$(normalize_list "${iface}")
+	fi
+	interfaces="${interfaces} ${iface}"
 }
 
 boot()
@@ -204,6 +386,7 @@ boot()
 start_service()
 {
 	hk_generate_as_needed
+	file_verify /etc/dropbear/authorized_keys config
 
 	. /lib/functions.sh
 	. /lib/functions/network.sh
@@ -216,13 +399,14 @@ service_triggers()
 {
 	local interfaces
 
-	procd_add_config_trigger "config.change" "dropbear" /etc/init.d/dropbear reload
+	procd_add_config_trigger "config.change" "${NAME}" /etc/init.d/dropbear reload
 
 	config_load "${NAME}"
-	config_foreach load_interfaces dropbear
+	config_foreach load_interfaces "${NAME}"
 
 	[ -n "${interfaces}" ] && {
-		for n in $interfaces ; do
+		local n
+		for n in $(printf '%s\n' ${interfaces} | sort -u) ; do
 			procd_add_interface_trigger "interface.*" $n /etc/init.d/dropbear reload
 		done
 	}
diff --git a/package/network/services/dropbear/patches/001-add-if-DROPBEAR_RSA-guards.patch b/package/network/services/dropbear/patches/001-add-if-DROPBEAR_RSA-guards.patch
new file mode 100644
index 00000000000000..ad1a20c520ff63
--- /dev/null
+++ b/package/network/services/dropbear/patches/001-add-if-DROPBEAR_RSA-guards.patch
@@ -0,0 +1,104 @@
+From 36a03132634a17c667c0fac0a8e1519b3d1b71c6 Mon Sep 17 00:00:00 2001
+From: Matt Johnston <matt@ucc.asn.au>
+Date: Mon, 28 Nov 2022 21:12:23 +0800
+Subject: Add #if DROPBEAR_RSA guards
+
+Fixes building with DROPBEAR_RSA disabled.
+Closes #197
+---
+ signkey.c    | 8 +++++++-
+ signkey.h    | 2 ++
+ sysoptions.h | 5 +----
+ 3 files changed, 10 insertions(+), 5 deletions(-)
+
+--- a/signkey.c
++++ b/signkey.c
+@@ -120,6 +120,7 @@ enum signkey_type signkey_type_from_name
+ /* Special case for rsa-sha2-256. This could be generalised if more 
+    signature names are added that aren't 1-1 with public key names */
+ const char* signature_name_from_type(enum signature_type type, unsigned int *namelen) {
++#if DROPBEAR_RSA
+ #if DROPBEAR_RSA_SHA256
+ 	if (type == DROPBEAR_SIGNATURE_RSA_SHA256) {
+ 		if (namelen) {
+@@ -136,11 +137,13 @@ const char* signature_name_from_type(enu
+ 		return SSH_SIGNKEY_RSA;
+ 	}
+ #endif
++#endif /* DROPBEAR_RSA */
+ 	return signkey_name_from_type((enum signkey_type)type, namelen);
+ }
+ 
+ /* Returns DROPBEAR_SIGNATURE_NONE if none match */
+ enum signature_type signature_type_from_name(const char* name, unsigned int namelen) {
++#if DROPBEAR_RSA
+ #if DROPBEAR_RSA_SHA256
+ 	if (namelen == strlen(SSH_SIGNATURE_RSA_SHA256) 
+ 		&& memcmp(name, SSH_SIGNATURE_RSA_SHA256, namelen) == 0) {
+@@ -153,10 +156,11 @@ enum signature_type signature_type_from_
+ 		return DROPBEAR_SIGNATURE_RSA_SHA1;
+ 	}
+ #endif
++#endif /* DROPBEAR_RSA */
+ 	return (enum signature_type)signkey_type_from_name(name, namelen);
+ }
+ 
+-/* Returns the signature type from a key type. Must not be called 
++/* Returns the signature type from a key type. Must not be called
+    with RSA keytype */
+ enum signature_type signature_type_from_signkey(enum signkey_type keytype) {
+ #if DROPBEAR_RSA
+@@ -167,6 +171,7 @@ enum signature_type signature_type_from_
+ }
+ 
+ enum signkey_type signkey_type_from_signature(enum signature_type sigtype) {
++#if DROPBEAR_RSA
+ #if DROPBEAR_RSA_SHA256
+ 	if (sigtype == DROPBEAR_SIGNATURE_RSA_SHA256) {
+ 		return DROPBEAR_SIGNKEY_RSA;
+@@ -177,6 +182,7 @@ enum signkey_type signkey_type_from_sign
+ 		return DROPBEAR_SIGNKEY_RSA;
+ 	}
+ #endif
++#endif /* DROPBEAR_RSA */
+ 	assert((int)sigtype < (int)DROPBEAR_SIGNKEY_NUM_NAMED);
+ 	return (enum signkey_type)sigtype;
+ }
+--- a/signkey.h
++++ b/signkey.h
+@@ -79,12 +79,14 @@ enum signature_type {
+ 	DROPBEAR_SIGNATURE_SK_ED25519 = DROPBEAR_SIGNKEY_SK_ED25519,
+ #endif
+ #endif
++#if DROPBEAR_RSA
+ #if DROPBEAR_RSA_SHA1
+ 	DROPBEAR_SIGNATURE_RSA_SHA1 = 100, /* ssh-rsa signature (sha1) */
+ #endif
+ #if DROPBEAR_RSA_SHA256
+ 	DROPBEAR_SIGNATURE_RSA_SHA256 = 101, /* rsa-sha2-256 signature. has a ssh-rsa key */
+ #endif
++#endif /* DROPBEAR_RSA */
+ 	DROPBEAR_SIGNATURE_NONE = DROPBEAR_SIGNKEY_NONE,
+ };
+ 
+--- a/sysoptions.h
++++ b/sysoptions.h
+@@ -137,7 +137,7 @@
+ 
+ /* Debian doesn't define this in system headers */
+ #if !defined(LTM_DESC) && (DROPBEAR_ECC)
+-#define LTM_DESC 
++#define LTM_DESC
+ #endif
+ 
+ #define DROPBEAR_ECC_256 (DROPBEAR_ECC)
+@@ -151,9 +151,6 @@
+  * signing operations slightly slower. */
+ #define DROPBEAR_RSA_BLINDING 1
+ 
+-#ifndef DROPBEAR_RSA_SHA1
+-#define DROPBEAR_RSA_SHA1 DROPBEAR_RSA
+-#endif
+ #ifndef DROPBEAR_RSA_SHA256
+ #define DROPBEAR_RSA_SHA256 DROPBEAR_RSA
+ #endif
diff --git a/package/network/services/dropbear/patches/001-fix-MAX_UNAUTH_CLIENTS-regression.patch b/package/network/services/dropbear/patches/001-fix-MAX_UNAUTH_CLIENTS-regression.patch
deleted file mode 100644
index e0dca544ecc92b..00000000000000
--- a/package/network/services/dropbear/patches/001-fix-MAX_UNAUTH_CLIENTS-regression.patch
+++ /dev/null
@@ -1,134 +0,0 @@
-From: Matt Johnston <matt@ucc.asn.au>
-Date: Wed, 8 Jun 2022 21:26:20 +0800
-Subject: Fix MAX_UNAUTH_CLIENTS regression
-
-Since re-exec change in 2022.82 Dropbear count
-treat authenticated sessions towards the unauthenticated
-session limit. This is fixed by passing the childpipe FD
-through to the re-execed process.
----
- runopts.h     |  5 +++--
- svr-main.c    | 21 +++++++++++----------
- svr-runopts.c | 15 ++++++++++++---
- 3 files changed, 26 insertions(+), 15 deletions(-)
-
---- a/runopts.h
-+++ b/runopts.h
-@@ -79,8 +79,9 @@ typedef struct svr_runopts {
- 	char *addresses[DROPBEAR_MAX_PORTS];
- 
- 	int inetdmode;
--	/* Hidden "-2" flag indicates it's re-executing itself */
--	int reexec_child;
-+	/* Hidden "-2 childpipe_fd" flag indicates it's re-executing itself,
-+	   stores the childpipe preauth file descriptor. Set to -1 otherwise. */
-+	int reexec_childpipe;
- 
- 	/* Flags indicating whether to use ipv4 and ipv6 */
- 	/* not used yet
---- a/svr-main.c
-+++ b/svr-main.c
-@@ -71,7 +71,7 @@ int main(int argc, char ** argv)
- #endif
- 
- #if DROPBEAR_DO_REEXEC
--	if (svr_opts.reexec_child) {
-+	if (svr_opts.reexec_childpipe >= 0) {
- #ifdef PR_SET_NAME
- 		/* Fix the "Name:" in /proc/pid/status, otherwise it's
- 		a FD number from fexecve.
-@@ -102,7 +102,7 @@ static void main_inetd() {
- 
- 	seedrandom();
- 
--	if (!svr_opts.reexec_child) {
-+	if (svr_opts.reexec_childpipe < 0) {
- 		/* In case our inetd was lax in logging source addresses */
- 		get_socket_address(0, NULL, NULL, &host, &port, 0);
- 			dropbear_log(LOG_INFO, "Child connection from %s:%s", host, port);
-@@ -115,10 +115,8 @@ static void main_inetd() {
- 		setsid();
- 	}
- 
--	/* Start service program 
--	 * -1 is a dummy childpipe, just something we can close() without 
--	 * mattering. */
--	svr_session(0, -1);
-+	/* -1 for childpipe in the inetd case is discarded */
-+	svr_session(0, svr_opts.reexec_childpipe);
- 
- 	/* notreached */
- }
-@@ -347,9 +345,10 @@ static void main_noinetd(int argc, char
- 
- 				if (execfd >= 0) {
- #if DROPBEAR_DO_REEXEC
--					/* Add "-2" to the args and re-execute ourself. */
--					char **new_argv = m_malloc(sizeof(char*) * (argc+3));
--					int pos0 = 0, new_argc = argc+1;
-+					/* Add "-2 childpipe[1]" to the args and re-execute ourself. */
-+					char **new_argv = m_malloc(sizeof(char*) * (argc+4));
-+					char buf[10];
-+					int pos0 = 0, new_argc = argc+2;
- 
- 					/* We need to specially handle "dropbearmulti dropbear". */
- 					if (multipath) {
-@@ -359,7 +358,9 @@ static void main_noinetd(int argc, char
- 					}
- 
- 					memcpy(&new_argv[pos0], argv, sizeof(char*) * argc);
--					new_argv[new_argc-1] = "-2";
-+					new_argv[new_argc-2] = "-2";
-+					snprintf(buf, sizeof(buf), "%d", childpipe[1]);
-+					new_argv[new_argc-1] = buf;
- 					new_argv[new_argc] = NULL;
- 
- 					if ((dup2(childsock, STDIN_FILENO) < 0)) {
---- a/svr-runopts.c
-+++ b/svr-runopts.c
-@@ -138,6 +138,7 @@ void svr_getopts(int argc, char ** argv)
- 	char* keepalive_arg = NULL;
- 	char* idle_timeout_arg = NULL;
- 	char* maxauthtries_arg = NULL;
-+	char* reexec_fd_arg = NULL;
- 	char* keyfile = NULL;
- 	char c;
- #if DROPBEAR_PLUGIN
-@@ -175,6 +176,7 @@ void svr_getopts(int argc, char ** argv)
-         svr_opts.pubkey_plugin_options = NULL;
- #endif
- 	svr_opts.pass_on_env = 0;
-+	svr_opts.reexec_childpipe = -1;
- 
- #ifndef DISABLE_ZLIB
- 	opts.compress_mode = DROPBEAR_COMPRESS_DELAYED;
-@@ -250,12 +252,12 @@ void svr_getopts(int argc, char ** argv)
- #if DROPBEAR_DO_REEXEC && NON_INETD_MODE
- 				/* For internal use by re-exec */
- 				case '2':
--					svr_opts.reexec_child = 1;
-+					next = &reexec_fd_arg;
- 					break;
- #endif
- 				case 'p':
--				  nextisport = 1;
--				  break;
-+					nextisport = 1;
-+					break;
- 				case 'P':
- 					next = &svr_opts.pidfile;
- 					break;
-@@ -426,6 +428,13 @@ void svr_getopts(int argc, char ** argv)
- 		dropbear_log(LOG_INFO, "Forced command set to '%s'", svr_opts.forced_command);
- 	}
- 
-+	if (reexec_fd_arg) {
-+		if (m_str_to_uint(reexec_fd_arg, &svr_opts.reexec_childpipe) == DROPBEAR_FAILURE
-+			|| svr_opts.reexec_childpipe < 0) {
-+			dropbear_exit("Bad -2");
-+		}
-+	}
-+
- #if INETD_MODE
- 	if (svr_opts.inetdmode && (
- 		opts.usingsyslog == 0
diff --git a/package/network/services/dropbear/patches/002-fix-y2038-issues.patch b/package/network/services/dropbear/patches/002-fix-y2038-issues.patch
new file mode 100644
index 00000000000000..0654e3b98b56e4
--- /dev/null
+++ b/package/network/services/dropbear/patches/002-fix-y2038-issues.patch
@@ -0,0 +1,198 @@
+From ec2215726cffb976019d08ebf569edd2229e9dba Mon Sep 17 00:00:00 2001
+From: Matt Johnston <matt@ucc.asn.au>
+Date: Thu, 1 Dec 2022 11:34:43 +0800
+Subject: Fix y2038 issues with time_t conversion
+
+These changes were identified by building with and without
+-D_TIME_BITS=64 -D_FILE_OFFSET_BITS=64
+on 32-bit arm, logging warnings to files.
+-Wconversion was added to CFLAGS in both builds.
+
+Then a "diff -I Wconversion log1 log2" shows new warnings that appear
+with the 64-bit time_t. There are a few false positives that have been
+fixed for quietness.
+
+struct logininfo and struct wtmp are still problematic, those will
+need to be handled by libc.
+---
+ common-session.c | 43 +++++++++++++++++++++++++++----------------
+ dbutil.c         |  2 +-
+ loginrec.c       |  2 ++
+ loginrec.h       |  4 ++--
+ runopts.h        |  4 ++--
+ svr-auth.c       |  2 +-
+ 6 files changed, 35 insertions(+), 22 deletions(-)
+
+--- a/common-session.c
++++ b/common-session.c
+@@ -519,15 +519,24 @@ static void send_msg_keepalive() {
+ 	ses.last_packet_time_idle = old_time_idle;
+ }
+ 
++/* Returns the difference in seconds, clamped to LONG_MAX */
++static long elapsed(time_t now, time_t prev) {
++	time_t del = now - prev;
++	if (del > LONG_MAX) {
++		return LONG_MAX;
++	}
++	return (long)del;
++}
++
+ /* Check all timeouts which are required. Currently these are the time for
+  * user authentication, and the automatic rekeying. */
+ static void checktimeouts() {
+ 
+ 	time_t now;
+ 	now = monotonic_now();
+-	
++
+ 	if (IS_DROPBEAR_SERVER && ses.connect_time != 0
+-		&& now - ses.connect_time >= AUTH_TIMEOUT) {
++		&& elapsed(now, ses.connect_time) >= AUTH_TIMEOUT) {
+ 			dropbear_close("Timeout before auth");
+ 	}
+ 
+@@ -537,45 +546,47 @@ static void checktimeouts() {
+ 	}
+ 
+ 	if (!ses.kexstate.sentkexinit
+-			&& (now - ses.kexstate.lastkextime >= KEX_REKEY_TIMEOUT
++			&& (elapsed(now, ses.kexstate.lastkextime) >= KEX_REKEY_TIMEOUT
+ 			|| ses.kexstate.datarecv+ses.kexstate.datatrans >= KEX_REKEY_DATA)) {
+ 		TRACE(("rekeying after timeout or max data reached"))
+ 		send_msg_kexinit();
+ 	}
+-	
++
+ 	if (opts.keepalive_secs > 0 && ses.authstate.authdone) {
+ 		/* Avoid sending keepalives prior to auth - those are
+ 		not valid pre-auth packet types */
+ 
+ 		/* Send keepalives if we've been idle */
+-		if (now - ses.last_packet_time_any_sent >= opts.keepalive_secs) {
++		if (elapsed(now, ses.last_packet_time_any_sent) >= opts.keepalive_secs) {
+ 			send_msg_keepalive();
+ 		}
+ 
+ 		/* Also send an explicit keepalive message to trigger a response
+ 		if the remote end hasn't sent us anything */
+-		if (now - ses.last_packet_time_keepalive_recv >= opts.keepalive_secs
+-			&& now - ses.last_packet_time_keepalive_sent >= opts.keepalive_secs) {
++		if (elapsed(now, ses.last_packet_time_keepalive_recv) >= opts.keepalive_secs
++			&& elapsed(now, ses.last_packet_time_keepalive_sent) >= opts.keepalive_secs) {
+ 			send_msg_keepalive();
+ 		}
+ 
+-		if (now - ses.last_packet_time_keepalive_recv 
++		if (elapsed(now, ses.last_packet_time_keepalive_recv)
+ 			>= opts.keepalive_secs * DEFAULT_KEEPALIVE_LIMIT) {
+ 			dropbear_exit("Keepalive timeout");
+ 		}
+ 	}
+ 
+-	if (opts.idle_timeout_secs > 0 
+-			&& now - ses.last_packet_time_idle >= opts.idle_timeout_secs) {
++	if (opts.idle_timeout_secs > 0
++			&& elapsed(now, ses.last_packet_time_idle) >= opts.idle_timeout_secs) {
+ 		dropbear_close("Idle timeout");
+ 	}
+ }
+ 
+-static void update_timeout(long limit, long now, long last_event, long * timeout) {
+-	TRACE2(("update_timeout limit %ld, now %ld, last %ld, timeout %ld",
+-		limit, now, last_event, *timeout))
++static void update_timeout(long limit, time_t now, time_t last_event, long * timeout) {
++	TRACE2(("update_timeout limit %ld, now %llu, last %llu, timeout %ld",
++		limit,
++		(unsigned long long)now,
++		(unsigned long long)last_event, *timeout))
+ 	if (last_event > 0 && limit > 0) {
+-		*timeout = MIN(*timeout, last_event+limit-now);
++		*timeout = MIN(*timeout, elapsed(now, last_event) + limit);
+ 		TRACE2(("new timeout %ld", *timeout))
+ 	}
+ }
+@@ -584,7 +595,7 @@ static long select_timeout() {
+ 	/* determine the minimum timeout that might be required, so
+ 	as to avoid waking when unneccessary */
+ 	long timeout = KEX_REKEY_TIMEOUT;
+-	long now = monotonic_now();
++	time_t now = monotonic_now();
+ 
+ 	if (!ses.kexstate.sentkexinit) {
+ 		update_timeout(KEX_REKEY_TIMEOUT, now, ses.kexstate.lastkextime, &timeout);
+@@ -596,7 +607,7 @@ static long select_timeout() {
+ 	}
+ 
+ 	if (ses.authstate.authdone) {
+-		update_timeout(opts.keepalive_secs, now, 
++		update_timeout(opts.keepalive_secs, now,
+ 			MAX(ses.last_packet_time_keepalive_recv, ses.last_packet_time_keepalive_sent),
+ 			&timeout);
+ 	}
+--- a/dbutil.c
++++ b/dbutil.c
+@@ -724,7 +724,7 @@ void gettime_wrapper(struct timespec *no
+ 	/* Fallback for everything else - this will sometimes go backwards */
+ 	gettimeofday(&tv, NULL);
+ 	now->tv_sec = tv.tv_sec;
+-	now->tv_nsec = 1000*tv.tv_usec;
++	now->tv_nsec = 1000*(long)tv.tv_usec;
+ }
+ 
+ /* second-resolution monotonic timestamp */
+--- a/loginrec.c
++++ b/loginrec.c
+@@ -459,6 +459,7 @@ line_abbrevname(char *dst, const char *s
+ void
+ set_utmp_time(struct logininfo *li, struct utmp *ut)
+ {
++	/* struct utmp in glibc isn't y2038 safe yet */
+ # ifdef HAVE_STRUCT_UTMP_UT_TV
+ 	ut->ut_tv.tv_sec = li->tv_sec;
+ 	ut->ut_tv.tv_usec = li->tv_usec;
+@@ -1272,6 +1273,7 @@ lastlog_construct(struct logininfo *li,
+ 	(void)line_stripname(last->ll_line, li->line, sizeof(last->ll_line));
+ 	strlcpy(last->ll_host, li->hostname,
+ 		MIN_SIZEOF(last->ll_host, li->hostname));
++	/* struct lastlog in glibc isn't y2038 safe yet */
+ 	last->ll_time = li->tv_sec;
+ }
+ 
+--- a/loginrec.h
++++ b/loginrec.h
+@@ -139,8 +139,8 @@ struct logininfo {
+ 	/* struct timeval (sys/time.h) isn't always available, if it isn't we'll
+ 	 * use time_t's value as tv_sec and set tv_usec to 0
+ 	 */
+-	unsigned int tv_sec;
+-	unsigned int tv_usec;
++	time_t tv_sec;
++	suseconds_t tv_usec;
+ 	union login_netinfo hostaddr;       /* caller's host address(es) */
+ }; /* struct logininfo */
+ 
+--- a/runopts.h
++++ b/runopts.h
+@@ -39,8 +39,8 @@ typedef struct runopts {
+ 	int listen_fwd_all;
+ #endif
+ 	unsigned int recv_window;
+-	time_t keepalive_secs; /* Time between sending keepalives. 0 is off */
+-	time_t idle_timeout_secs; /* Exit if no traffic is sent/received in this time */
++	long keepalive_secs; /* Time between sending keepalives. 0 is off */
++	long idle_timeout_secs; /* Exit if no traffic is sent/received in this time */
+ 	int usingsyslog;
+ 
+ #ifndef DISABLE_ZLIB
+--- a/svr-auth.c
++++ b/svr-auth.c
+@@ -389,7 +389,7 @@ void send_msg_userauth_failure(int parti
+ 		Beware of integer overflow if increasing these values */
+ 		const unsigned int mindelay = 250000000;
+ 		const unsigned int vardelay = 100000000;
+-		unsigned int rand_delay;
++		suseconds_t rand_delay;
+ 		struct timespec delay;
+ 
+ 		gettime_wrapper(&delay);
diff --git a/package/network/services/dropbear/patches/003-fix-DROPBEAR_DSS.patch b/package/network/services/dropbear/patches/003-fix-DROPBEAR_DSS.patch
new file mode 100644
index 00000000000000..6789800e120648
--- /dev/null
+++ b/package/network/services/dropbear/patches/003-fix-DROPBEAR_DSS.patch
@@ -0,0 +1,25 @@
+From c043efb47c3173072fa636ca0da0d19875d4511f Mon Sep 17 00:00:00 2001
+From: Matt Johnston <matt@ucc.asn.au>
+Date: Tue, 6 Dec 2022 22:34:11 +0800
+Subject: Fix so DROPBEAR_DSS is only forced for fuzzing
+
+Regression from 787391ea3b5af2acf5e3c83372510f0c79477ad7,
+was missing fuzzing conditional
+---
+ sysoptions.h | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/sysoptions.h
++++ b/sysoptions.h
+@@ -380,9 +380,11 @@
+ #endif
+ 
+ /* Fuzzing expects all key types to be enabled */
++#if DROPBEAR_FUZZ
+ #if defined(DROPBEAR_DSS)
+ #undef DROPBEAR_DSS
+ #endif
+ #define DROPBEAR_DSS 1
++#endif
+ 
+ /* no include guard for this file */
diff --git a/package/network/services/dropbear/patches/004-allow-users-s-own-gid-in-pty-permission-check.patch b/package/network/services/dropbear/patches/004-allow-users-s-own-gid-in-pty-permission-check.patch
new file mode 100644
index 00000000000000..bcb43aed2ae275
--- /dev/null
+++ b/package/network/services/dropbear/patches/004-allow-users-s-own-gid-in-pty-permission-check.patch
@@ -0,0 +1,24 @@
+From 860721558837441ab45019858e710a2625ffa46e Mon Sep 17 00:00:00 2001
+From: Matt Johnston <matt@ucc.asn.au>
+Date: Wed, 7 Dec 2022 13:04:10 +0800
+Subject: Allow users's own gid in pty permission check
+
+This allows non-root Dropbear to work even without devpts gid=5 mount
+option on Linux.
+---
+ sshpty.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+--- a/sshpty.c
++++ b/sshpty.c
+@@ -380,7 +380,9 @@ pty_setowner(struct passwd *pw, const ch
+ 				tty_name, strerror(errno));
+ 	}
+ 
+-	if (st.st_uid != pw->pw_uid || st.st_gid != gid) {
++	/* Allow either "tty" gid or user's own gid. On Linux with openpty()
++	 * this varies depending on the devpts mount options */
++	if (st.st_uid != pw->pw_uid || !(st.st_gid == gid || st.st_gid == pw->pw_gid)) {
+ 		if (chown(tty_name, pw->pw_uid, gid) < 0) {
+ 			if (errno == EROFS &&
+ 			    (st.st_uid == pw->pw_uid || st.st_uid == 0)) {
diff --git a/package/network/services/dropbear/patches/005-const-parameter-mp_int.patch b/package/network/services/dropbear/patches/005-const-parameter-mp_int.patch
new file mode 100644
index 00000000000000..0d23c9c41610dd
--- /dev/null
+++ b/package/network/services/dropbear/patches/005-const-parameter-mp_int.patch
@@ -0,0 +1,123 @@
+From 01415ef8269e594a647f67ea0729ca8b590679de Mon Sep 17 00:00:00 2001
+From: Francois Perrad <francois.perrad@gadz.org>
+Date: Thu, 22 Dec 2022 10:19:54 +0100
+Subject: const parameter mp_int
+
+---
+ bignum.c   | 2 +-
+ bignum.h   | 2 +-
+ buffer.c   | 2 +-
+ buffer.h   | 2 +-
+ dbrandom.c | 2 +-
+ dbrandom.h | 2 +-
+ dbutil.c   | 2 +-
+ dbutil.h   | 2 +-
+ genrsa.c   | 4 ++--
+ 9 files changed, 10 insertions(+), 10 deletions(-)
+
+--- a/bignum.c
++++ b/bignum.c
+@@ -93,7 +93,7 @@ void bytes_to_mp(mp_int *mp, const unsig
+ 
+ /* hash the ssh representation of the mp_int mp */
+ void hash_process_mp(const struct ltc_hash_descriptor *hash_desc, 
+-				hash_state *hs, mp_int *mp) {
++				hash_state *hs, const mp_int *mp) {
+ 	buffer * buf;
+ 
+ 	buf = buf_new(512 + 20); /* max buffer is a 4096 bit key, 
+--- a/bignum.h
++++ b/bignum.h
+@@ -33,6 +33,6 @@ void m_mp_alloc_init_multi(mp_int **mp,
+ void m_mp_free_multi(mp_int **mp, ...)  ATTRIB_SENTINEL;
+ void bytes_to_mp(mp_int *mp, const unsigned char* bytes, unsigned int len);
+ void hash_process_mp(const struct ltc_hash_descriptor *hash_desc, 
+-				hash_state *hs, mp_int *mp);
++				hash_state *hs, const mp_int *mp);
+ 
+ #endif /* DROPBEAR_BIGNUM_H_ */
+--- a/buffer.c
++++ b/buffer.c
+@@ -299,7 +299,7 @@ void buf_putbytes(buffer *buf, const uns
+ 
+ /* for our purposes we only need positive (or 0) numbers, so will
+  * fail if we get negative numbers */
+-void buf_putmpint(buffer* buf, mp_int * mp) {
++void buf_putmpint(buffer* buf, const mp_int * mp) {
+ 	size_t written;
+ 	unsigned int len, pad = 0;
+ 	TRACE2(("enter buf_putmpint"))
+--- a/buffer.h
++++ b/buffer.h
+@@ -65,7 +65,7 @@ void buf_putint(buffer* buf, unsigned in
+ void buf_putstring(buffer* buf, const char* str, unsigned int len);
+ void buf_putbufstring(buffer *buf, const buffer* buf_str);
+ void buf_putbytes(buffer *buf, const unsigned char *bytes, unsigned int len);
+-void buf_putmpint(buffer* buf, mp_int * mp);
++void buf_putmpint(buffer* buf, const mp_int * mp);
+ int buf_getmpint(buffer* buf, mp_int* mp);
+ unsigned int buf_getint(buffer* buf);
+ 
+--- a/dbrandom.c
++++ b/dbrandom.c
+@@ -347,7 +347,7 @@ void genrandom(unsigned char* buf, unsig
+  * rand must be an initialised *mp_int for the result.
+  * the result rand satisfies:  0 < rand < max 
+  * */
+-void gen_random_mpint(mp_int *max, mp_int *rand) {
++void gen_random_mpint(const mp_int *max, mp_int *rand) {
+ 
+ 	unsigned char *randbuf = NULL;
+ 	unsigned int len = 0;
+--- a/dbrandom.h
++++ b/dbrandom.h
+@@ -30,6 +30,6 @@
+ void seedrandom(void);
+ void genrandom(unsigned char* buf, unsigned int len);
+ void addrandom(const unsigned char * buf, unsigned int len);
+-void gen_random_mpint(mp_int *max, mp_int *rand);
++void gen_random_mpint(const mp_int *max, mp_int *rand);
+ 
+ #endif /* DROPBEAR_RANDOM_H_ */
+--- a/dbutil.c
++++ b/dbutil.c
+@@ -442,7 +442,7 @@ void printhex(const char * label, const
+ 	}
+ }
+ 
+-void printmpint(const char *label, mp_int *mp) {
++void printmpint(const char *label, const mp_int *mp) {
+ 	buffer *buf = buf_new(1000);
+ 	buf_putmpint(buf, mp);
+ 	fprintf(stderr, "%d bits ", mp_count_bits(mp));
+--- a/dbutil.h
++++ b/dbutil.h
+@@ -53,7 +53,7 @@ void dropbear_trace3(const char* format,
+ void dropbear_trace4(const char* format, ...) ATTRIB_PRINTF(1,2);
+ void dropbear_trace5(const char* format, ...) ATTRIB_PRINTF(1,2);
+ void printhex(const char * label, const unsigned char * buf, int len);
+-void printmpint(const char *label, mp_int *mp);
++void printmpint(const char *label, const mp_int *mp);
+ void debug_start_net(void);
+ extern int debug_trace;
+ #endif
+--- a/genrsa.c
++++ b/genrsa.c
+@@ -34,7 +34,7 @@
+ #if DROPBEAR_RSA
+ 
+ static void getrsaprime(mp_int* prime, mp_int *primeminus, 
+-		mp_int* rsa_e, unsigned int size_bytes);
++		const mp_int* rsa_e, unsigned int size_bytes);
+ 
+ /* mostly taken from libtomcrypt's rsa key generation routine */
+ dropbear_rsa_key * gen_rsa_priv_key(unsigned int size) {
+@@ -89,7 +89,7 @@ dropbear_rsa_key * gen_rsa_priv_key(unsi
+ 
+ /* return a prime suitable for p or q */
+ static void getrsaprime(mp_int* prime, mp_int *primeminus, 
+-		mp_int* rsa_e, unsigned int size_bytes) {
++		const mp_int* rsa_e, unsigned int size_bytes) {
+ 
+ 	unsigned char *buf;
+ 	int trials;
diff --git a/package/network/services/dropbear/patches/006-dropbearkey-add-missing-break-in-switch.patch b/package/network/services/dropbear/patches/006-dropbearkey-add-missing-break-in-switch.patch
new file mode 100644
index 00000000000000..c7011021c17811
--- /dev/null
+++ b/package/network/services/dropbear/patches/006-dropbearkey-add-missing-break-in-switch.patch
@@ -0,0 +1,21 @@
+From 39d955c49f31fc155e885447ee2be61c869d8c2d Mon Sep 17 00:00:00 2001
+From: Matt Johnston <matt@ucc.asn.au>
+Date: Tue, 3 Jan 2023 22:05:14 +0800
+Subject: Add missing break in switch
+
+Has no effect on execution, the fallthrough does nothing
+Closes #208
+---
+ dropbearkey.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/dropbearkey.c
++++ b/dropbearkey.c
+@@ -139,6 +139,7 @@ static void check_signkey_bits(enum sign
+ 				dropbear_exit("DSS keys have a fixed size of 1024 bits\n");
+ 				exit(EXIT_FAILURE);
+ 			}
++			break;
+ #endif
+ 		default:
+ 			(void)0; /* quiet, compiler. ecdsa handles checks itself */
diff --git a/package/network/services/dropbear/patches/007-fix-building-only-client-or-server.patch b/package/network/services/dropbear/patches/007-fix-building-only-client-or-server.patch
new file mode 100644
index 00000000000000..5fcfaad1809fdc
--- /dev/null
+++ b/package/network/services/dropbear/patches/007-fix-building-only-client-or-server.patch
@@ -0,0 +1,29 @@
+From 7a53c7f0f4b3eb23e002819553cb45558642c01d Mon Sep 17 00:00:00 2001
+From: Matt Johnston <matt@ucc.asn.au>
+Date: Wed, 4 Jan 2023 20:32:23 +0800
+Subject: Fix building only client or server
+
+Regressed when -Wundef was added
+
+Fixes #210
+---
+ sysoptions.h | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/sysoptions.h
++++ b/sysoptions.h
+@@ -10,6 +10,14 @@
+ #define LOCAL_IDENT "SSH-2.0-dropbear_" DROPBEAR_VERSION
+ #define PROGNAME "dropbear"
+ 
++#ifndef DROPBEAR_CLIENT
++#define DROPBEAR_CLIENT 0
++#endif
++
++#ifndef DROPBEAR_SERVER
++#define DROPBEAR_SERVER 0
++#endif
++
+ /* Spec recommends after one hour or 1 gigabyte of data. One hour
+  * is a bit too verbose, so we try 8 hours */
+ #ifndef KEX_REKEY_TIMEOUT
diff --git a/package/network/services/dropbear/patches/008-disable-rsa-signatures-when-no-rsa-hostkey.patch b/package/network/services/dropbear/patches/008-disable-rsa-signatures-when-no-rsa-hostkey.patch
new file mode 100644
index 00000000000000..4f675234ff9b89
--- /dev/null
+++ b/package/network/services/dropbear/patches/008-disable-rsa-signatures-when-no-rsa-hostkey.patch
@@ -0,0 +1,94 @@
+From a113381c12a2da3c9b7bd594f47a1b2657bdfdf2 Mon Sep 17 00:00:00 2001
+From: Matt Johnston <matt@ucc.asn.au>
+Date: Sun, 12 Feb 2023 22:44:32 +0800
+Subject: Disable rsa signatures when no rsa hostkey
+
+Otherwise Dropbear will offer RSA as a hostkey signature option, but the
+session will exit with an assertion or NULL pointer dereference once
+that algorithm is negotiated.
+
+This likely regressed in 2020.79 when signature vs key type enums were
+split, for rsa-sha256.
+
+Fixes #219 on github
+---
+ svr-runopts.c | 21 +++++++++++----------
+ 1 file changed, 11 insertions(+), 10 deletions(-)
+
+--- a/svr-runopts.c
++++ b/svr-runopts.c
+@@ -505,11 +505,11 @@ static void addportandaddress(const char
+ 	svr_opts.portcount++;
+ }
+ 
+-static void disablekey(int type) {
++static void disablekey(enum signature_type type) {
+ 	int i;
+ 	TRACE(("Disabling key type %d", type))
+ 	for (i = 0; sigalgs[i].name != NULL; i++) {
+-		if (sigalgs[i].val == type) {
++		if ((int)sigalgs[i].val == (int)type) {
+ 			sigalgs[i].usable = 0;
+ 			break;
+ 		}
+@@ -624,7 +624,8 @@ void load_all_hostkeys() {
+ 
+ #if DROPBEAR_RSA
+ 	if (!svr_opts.delay_hostkey && !svr_opts.hostkey->rsakey) {
+-		disablekey(DROPBEAR_SIGNKEY_RSA);
++		disablekey(DROPBEAR_SIGNATURE_RSA_SHA256);
++		disablekey(DROPBEAR_SIGNATURE_RSA_SHA1);
+ 	} else {
+ 		any_keys = 1;
+ 	}
+@@ -632,7 +633,7 @@ void load_all_hostkeys() {
+ 
+ #if DROPBEAR_DSS
+ 	if (!svr_opts.delay_hostkey && !svr_opts.hostkey->dsskey) {
+-		disablekey(DROPBEAR_SIGNKEY_DSS);
++		disablekey(DROPBEAR_SIGNATURE_DSS);
+ 	} else {
+ 		any_keys = 1;
+ 	}
+@@ -666,35 +667,35 @@ void load_all_hostkeys() {
+ #if DROPBEAR_ECC_256
+ 	if (!svr_opts.hostkey->ecckey256
+ 		&& (!svr_opts.delay_hostkey || loaded_any_ecdsa || ECDSA_DEFAULT_SIZE != 256 )) {
+-		disablekey(DROPBEAR_SIGNKEY_ECDSA_NISTP256);
++		disablekey(DROPBEAR_SIGNATURE_ECDSA_NISTP256);
+ 	}
+ #endif
+ #if DROPBEAR_ECC_384
+ 	if (!svr_opts.hostkey->ecckey384
+ 		&& (!svr_opts.delay_hostkey || loaded_any_ecdsa || ECDSA_DEFAULT_SIZE != 384 )) {
+-		disablekey(DROPBEAR_SIGNKEY_ECDSA_NISTP384);
++		disablekey(DROPBEAR_SIGNATURE_ECDSA_NISTP384);
+ 	}
+ #endif
+ #if DROPBEAR_ECC_521
+ 	if (!svr_opts.hostkey->ecckey521
+ 		&& (!svr_opts.delay_hostkey || loaded_any_ecdsa || ECDSA_DEFAULT_SIZE != 521 )) {
+-		disablekey(DROPBEAR_SIGNKEY_ECDSA_NISTP521);
++		disablekey(DROPBEAR_SIGNATURE_ECDSA_NISTP521);
+ 	}
+ #endif
+ #endif /* DROPBEAR_ECDSA */
+ 
+ #if DROPBEAR_ED25519
+ 	if (!svr_opts.delay_hostkey && !svr_opts.hostkey->ed25519key) {
+-		disablekey(DROPBEAR_SIGNKEY_ED25519);
++		disablekey(DROPBEAR_SIGNATURE_ED25519);
+ 	} else {
+ 		any_keys = 1;
+ 	}
+ #endif
+ #if DROPBEAR_SK_ECDSA
+-	disablekey(DROPBEAR_SIGNKEY_SK_ECDSA_NISTP256);
++	disablekey(DROPBEAR_SIGNATURE_SK_ECDSA_NISTP256);
+ #endif 
+ #if DROPBEAR_SK_ED25519
+-	disablekey(DROPBEAR_SIGNKEY_SK_ED25519);
++	disablekey(DROPBEAR_SIGNATURE_SK_ED25519);
+ #endif
+ 
+ 	if (!any_keys) {
diff --git a/package/network/services/dropbear/patches/009-use-write-rather-than-fprintf-in-segv-handler.patch b/package/network/services/dropbear/patches/009-use-write-rather-than-fprintf-in-segv-handler.patch
new file mode 100644
index 00000000000000..e1538a4c1f7329
--- /dev/null
+++ b/package/network/services/dropbear/patches/009-use-write-rather-than-fprintf-in-segv-handler.patch
@@ -0,0 +1,27 @@
+From 3292b8c6f1e5fcc405fa0f7a20e90a60f74037b2 Mon Sep 17 00:00:00 2001
+From: Matt Johnston <matt@ucc.asn.au>
+Date: Sun, 12 Feb 2023 23:00:00 +0800
+Subject: Use write() rather than fprintf() in segv handler
+
+fprintf isn't guaranteed safe (though hasn't had any problems reported).
+---
+ svr-main.c | 8 ++++++--
+ 1 file changed, 6 insertions(+), 2 deletions(-)
+
+--- a/svr-main.c
++++ b/svr-main.c
+@@ -420,8 +420,12 @@ static void sigchld_handler(int UNUSED(u
+ 
+ /* catch any segvs */
+ static void sigsegv_handler(int UNUSED(unused)) {
+-	fprintf(stderr, "Aiee, segfault! You should probably report "
+-			"this as a bug to the developer\n");
++	int i;
++	const char *msg = "Aiee, segfault! You should probably report "
++			"this as a bug to the developer\n";
++	i = write(STDERR_FILENO, msg, strlen(msg));
++	/* ignore short writes */
++	(void)i;
+ 	_exit(EXIT_FAILURE);
+ }
+ 
diff --git a/package/network/services/dropbear/patches/010-remove-SO_LINGER.patch b/package/network/services/dropbear/patches/010-remove-SO_LINGER.patch
new file mode 100644
index 00000000000000..12b1843ee26412
--- /dev/null
+++ b/package/network/services/dropbear/patches/010-remove-SO_LINGER.patch
@@ -0,0 +1,39 @@
+From 5040f21cb4ee6ade966e60c6d5a3c270d03de1f1 Mon Sep 17 00:00:00 2001
+From: Matt Johnston <matt@ucc.asn.au>
+Date: Mon, 1 May 2023 22:05:43 +0800
+Subject: Remove SO_LINGER
+
+It could cause channels to take up to 5 seconds to close(), which would block
+the entire process. On busy TCP forwarding sessions this would result in
+channels seeming stuck and new connections not being accepted.
+
+We don't need to monitor for flushing failures since we can't report errors, so
+SO_LINGER wasn't useful.
+
+Thanks to GektorUA for reporting and testing
+
+Fixes #230
+---
+ netio.c | 4 ----
+ 1 file changed, 4 deletions(-)
+
+--- a/netio.c
++++ b/netio.c
+@@ -472,7 +472,6 @@ int dropbear_listen(const char* address,
+ 	struct addrinfo hints, *res = NULL, *res0 = NULL;
+ 	int err;
+ 	unsigned int nsock;
+-	struct linger linger;
+ 	int val;
+ 	int sock;
+ 	uint16_t *allocated_lport_p = NULL;
+@@ -551,9 +550,6 @@ int dropbear_listen(const char* address,
+ 		val = 1;
+ 		/* set to reuse, quick timeout */
+ 		setsockopt(sock, SOL_SOCKET, SO_REUSEADDR, (void*) &val, sizeof(val));
+-		linger.l_onoff = 1;
+-		linger.l_linger = 5;
+-		setsockopt(sock, SOL_SOCKET, SO_LINGER, (void*)&linger, sizeof(linger));
+ 
+ #if defined(IPPROTO_IPV6) && defined(IPV6_V6ONLY)
+ 		if (res->ai_family == AF_INET6) {
diff --git a/package/network/services/dropbear/patches/011-add-option-to-bind-to-interface.patch b/package/network/services/dropbear/patches/011-add-option-to-bind-to-interface.patch
new file mode 100644
index 00000000000000..d1c1fa4ccedf38
--- /dev/null
+++ b/package/network/services/dropbear/patches/011-add-option-to-bind-to-interface.patch
@@ -0,0 +1,147 @@
+From fb64db9eac3fdc6434f2dc7b5ea407fe5df76e6f Mon Sep 17 00:00:00 2001
+From: Diederik De Coninck <diederik.deconinck_ext@softathome.com>
+Date: Tue, 11 Apr 2023 15:38:04 +0200
+Subject: Add option to bind to interface
+
+---
+ netio.c       | 13 +++++++++++--
+ netio.h       |  2 +-
+ runopts.h     |  1 +
+ svr-main.c    |  2 +-
+ svr-runopts.c |  9 +++++++++
+ svr-tcpfwd.c  |  1 +
+ tcp-accept.c  |  2 +-
+ tcpfwd.h      |  1 +
+ 8 files changed, 26 insertions(+), 5 deletions(-)
+
+--- a/netio.c
++++ b/netio.c
+@@ -467,7 +467,7 @@ int get_sock_port(int sock) {
+  * failure, if errstring wasn't NULL, it'll be a newly malloced error
+  * string.*/
+ int dropbear_listen(const char* address, const char* port,
+-		int *socks, unsigned int sockcount, char **errstring, int *maxfd) {
++		int *socks, unsigned int sockcount, char **errstring, int *maxfd, const char* interface) {
+ 
+ 	struct addrinfo hints, *res = NULL, *res0 = NULL;
+ 	int err;
+@@ -497,7 +497,11 @@ int dropbear_listen(const char* address,
+ 		TRACE(("dropbear_listen: local loopback"))
+ 	} else {
+ 		if (address[0] == '\0') {
+-			TRACE(("dropbear_listen: all interfaces"))
++			if (interface) {
++				TRACE(("dropbear_listen: %s", interface))
++			} else {
++				TRACE(("dropbear_listen: all interfaces"))
++			}
+ 			address = NULL;
+ 		}
+ 		hints.ai_flags = AI_PASSIVE;
+@@ -551,6 +555,11 @@ int dropbear_listen(const char* address,
+ 		/* set to reuse, quick timeout */
+ 		setsockopt(sock, SOL_SOCKET, SO_REUSEADDR, (void*) &val, sizeof(val));
+ 
++		if(interface && setsockopt(sock, SOL_SOCKET, SO_BINDTODEVICE, interface, strlen(interface)) < 0) {
++			dropbear_log(LOG_WARNING, "Couldn't set SO_BINDTODEVICE");
++			TRACE(("Failed setsockopt with errno failure, %d %s", errno, strerror(errno)))
++		}
++
+ #if defined(IPPROTO_IPV6) && defined(IPV6_V6ONLY)
+ 		if (res->ai_family == AF_INET6) {
+ 			int on = 1;
+--- a/netio.h
++++ b/netio.h
+@@ -19,7 +19,7 @@ void get_socket_address(int fd, char **l
+ void getaddrstring(struct sockaddr_storage* addr, 
+ 		char **ret_host, char **ret_port, int host_lookup);
+ int dropbear_listen(const char* address, const char* port,
+-		int *socks, unsigned int sockcount, char **errstring, int *maxfd);
++		int *socks, unsigned int sockcount, char **errstring, int *maxfd, const char* interface);
+ 
+ struct dropbear_progress_connection;
+ 
+--- a/runopts.h
++++ b/runopts.h
+@@ -128,6 +128,7 @@ typedef struct svr_runopts {
+ 	char * pidfile;
+ 
+ 	char * forced_command;
++	char* interface;
+ 
+ #if DROPBEAR_PLUGIN 
+ 	/* malloced */
+--- a/svr-main.c
++++ b/svr-main.c
+@@ -488,7 +488,7 @@ static size_t listensockets(int *socks,
+ 
+ 		nsock = dropbear_listen(svr_opts.addresses[i], svr_opts.ports[i], &socks[sockpos], 
+ 				sockcount - sockpos,
+-				&errstring, maxfd);
++				&errstring, maxfd, svr_opts.interface);
+ 
+ 		if (nsock < 0) {
+ 			dropbear_log(LOG_WARNING, "Failed listening on '%s': %s", 
+--- a/svr-runopts.c
++++ b/svr-runopts.c
+@@ -98,6 +98,8 @@ static void printhelp(const char * progn
+ 					"		(default port is %s if none specified)\n"
+ 					"-P PidFile	Create pid file PidFile\n"
+ 					"		(default %s)\n"
++					"-l <interface>\n"
++					"		interface to bind on\n"
+ #if INETD_MODE
+ 					"-i		Start for inetd\n"
+ #endif
+@@ -265,6 +267,9 @@ void svr_getopts(int argc, char ** argv)
+ 				case 'P':
+ 					next = &svr_opts.pidfile;
+ 					break;
++				case 'l':
++					next = &svr_opts.interface;
++					break;
+ #if DO_MOTD
+ 				/* motd is displayed by default, -m turns it off */
+ 				case 'm':
+@@ -438,6 +443,10 @@ void svr_getopts(int argc, char ** argv)
+ 		dropbear_log(LOG_INFO, "Forced command set to '%s'", svr_opts.forced_command);
+ 	}
+ 
++	if (svr_opts.interface) {
++		dropbear_log(LOG_INFO, "Binding to interface '%s'", svr_opts.interface);
++	}
++
+ 	if (reexec_fd_arg) {
+ 		if (m_str_to_uint(reexec_fd_arg, &svr_opts.reexec_childpipe) == DROPBEAR_FAILURE
+ 			|| svr_opts.reexec_childpipe < 0) {
+--- a/svr-tcpfwd.c
++++ b/svr-tcpfwd.c
+@@ -205,6 +205,7 @@ static int svr_remotetcpreq(int *allocat
+ 	tcpinfo->listenport = port;
+ 	tcpinfo->chantype = &svr_chan_tcpremote;
+ 	tcpinfo->tcp_type = forwarded;
++	tcpinfo->interface = svr_opts.interface;
+ 
+ 	tcpinfo->request_listenaddr = request_addr;
+ 	if (!opts.listen_fwd_all || (strcmp(request_addr, "localhost") == 0) ) {
+--- a/tcp-accept.c
++++ b/tcp-accept.c
+@@ -117,7 +117,7 @@ int listen_tcpfwd(struct TCPListener* tc
+ 	snprintf(portstring, sizeof(portstring), "%u", tcpinfo->listenport);
+ 
+ 	nsocks = dropbear_listen(tcpinfo->listenaddr, portstring, socks, 
+-			DROPBEAR_MAX_SOCKS, &errstring, &ses.maxfd);
++			DROPBEAR_MAX_SOCKS, &errstring, &ses.maxfd, tcpinfo->interface);
+ 	if (nsocks < 0) {
+ 		dropbear_log(LOG_INFO, "TCP forward failed: %s", errstring);
+ 		m_free(errstring);
+--- a/tcpfwd.h
++++ b/tcpfwd.h
+@@ -42,6 +42,7 @@ struct TCPListener {
+ 	unsigned int listenport;
+ 	/* The address that the remote host asked to listen on */
+ 	char *request_listenaddr;
++	char* interface;
+ 
+ 	const struct ChanType *chantype;
+ 	enum {direct, forwarded} tcp_type;
diff --git a/package/network/services/dropbear/patches/012-add-ifdef-guards-for-SO_BINDTODEVICE.patch b/package/network/services/dropbear/patches/012-add-ifdef-guards-for-SO_BINDTODEVICE.patch
new file mode 100644
index 00000000000000..11f902bf9070fb
--- /dev/null
+++ b/package/network/services/dropbear/patches/012-add-ifdef-guards-for-SO_BINDTODEVICE.patch
@@ -0,0 +1,50 @@
+From 031d09b47912b2401f4934667c0b6f857ede61ee Mon Sep 17 00:00:00 2001
+From: Matt Johnston <matt@ucc.asn.au>
+Date: Tue, 18 Jul 2023 23:20:16 +0800
+Subject: Add ifdef guards for SO_BINDTODEVICE
+
+---
+ netio.c       | 2 ++
+ svr-runopts.c | 4 ++++
+ 2 files changed, 6 insertions(+)
+
+--- a/netio.c
++++ b/netio.c
+@@ -555,10 +555,12 @@ int dropbear_listen(const char* address,
+ 		/* set to reuse, quick timeout */
+ 		setsockopt(sock, SOL_SOCKET, SO_REUSEADDR, (void*) &val, sizeof(val));
+ 
++#ifdef SO_BINDTODEVICE
+ 		if(interface && setsockopt(sock, SOL_SOCKET, SO_BINDTODEVICE, interface, strlen(interface)) < 0) {
+ 			dropbear_log(LOG_WARNING, "Couldn't set SO_BINDTODEVICE");
+ 			TRACE(("Failed setsockopt with errno failure, %d %s", errno, strerror(errno)))
+ 		}
++#endif
+ 
+ #if defined(IPPROTO_IPV6) && defined(IPV6_V6ONLY)
+ 		if (res->ai_family == AF_INET6) {
+--- a/svr-runopts.c
++++ b/svr-runopts.c
+@@ -98,8 +98,10 @@ static void printhelp(const char * progn
+ 					"		(default port is %s if none specified)\n"
+ 					"-P PidFile	Create pid file PidFile\n"
+ 					"		(default %s)\n"
++#ifdef SO_BINDTODEVICE
+ 					"-l <interface>\n"
+ 					"		interface to bind on\n"
++#endif
+ #if INETD_MODE
+ 					"-i		Start for inetd\n"
+ #endif
+@@ -267,9 +269,11 @@ void svr_getopts(int argc, char ** argv)
+ 				case 'P':
+ 					next = &svr_opts.pidfile;
+ 					break;
++#ifdef SO_BINDTODEVICE
+ 				case 'l':
+ 					next = &svr_opts.interface;
+ 					break;
++#endif
+ #if DO_MOTD
+ 				/* motd is displayed by default, -m turns it off */
+ 				case 'm':
diff --git a/package/network/services/dropbear/patches/013-make-banner-reading-failure-non-fatal.patch b/package/network/services/dropbear/patches/013-make-banner-reading-failure-non-fatal.patch
new file mode 100644
index 00000000000000..531215c757635c
--- /dev/null
+++ b/package/network/services/dropbear/patches/013-make-banner-reading-failure-non-fatal.patch
@@ -0,0 +1,74 @@
+From 62a06cd95f58060a59359f8769c3f35cd680d4fd Mon Sep 17 00:00:00 2001
+From: Matt Johnston <matt@ucc.asn.au>
+Date: Sun, 23 Jul 2023 21:01:48 +0800
+Subject: Make banner reading failure non-fatal
+
+---
+ svr-runopts.c | 45 ++++++++++++++++++++++++++++-----------------
+ 1 file changed, 28 insertions(+), 17 deletions(-)
+
+--- a/svr-runopts.c
++++ b/svr-runopts.c
+@@ -38,6 +38,7 @@ static void printhelp(const char * progn
+ static void addportandaddress(const char* spec);
+ static void loadhostkey(const char *keyfile, int fatal_duplicate);
+ static void addhostkey(const char *keyfile);
++static void load_banner();
+ 
+ static void printhelp(const char * progname) {
+ 
+@@ -382,23 +383,7 @@ void svr_getopts(int argc, char ** argv)
+ 	}
+ 
+ 	if (svr_opts.bannerfile) {
+-		struct stat buf;
+-		if (stat(svr_opts.bannerfile, &buf) != 0) {
+-			dropbear_exit("Error opening banner file '%s'",
+-					svr_opts.bannerfile);
+-		}
+-		
+-		if (buf.st_size > MAX_BANNER_SIZE) {
+-			dropbear_exit("Banner file too large, max is %d bytes",
+-					MAX_BANNER_SIZE);
+-		}
+-
+-		svr_opts.banner = buf_new(buf.st_size);
+-		if (buf_readfile(svr_opts.banner, svr_opts.bannerfile)!=DROPBEAR_SUCCESS) {
+-			dropbear_exit("Error reading banner file '%s'",
+-					svr_opts.bannerfile);
+-		}
+-		buf_setpos(svr_opts.banner, 0);
++		load_banner();
+ 	}
+ 
+ #ifdef HAVE_GETGROUPLIST
+@@ -715,3 +700,29 @@ void load_all_hostkeys() {
+ 		dropbear_exit("No hostkeys available. 'dropbear -R' may be useful or run dropbearkey.");
+ 	}
+ }
++
++static void load_banner() {
++	struct stat buf;
++	if (stat(svr_opts.bannerfile, &buf) != 0) {
++		dropbear_log(LOG_WARNING, "Error opening banner file '%s'",
++				svr_opts.bannerfile);
++		return;
++	}
++
++	if (buf.st_size > MAX_BANNER_SIZE) {
++		dropbear_log(LOG_WARNING, "Banner file too large, max is %d bytes",
++				MAX_BANNER_SIZE);
++		return;
++	}
++
++	svr_opts.banner = buf_new(buf.st_size);
++	if (buf_readfile(svr_opts.banner, svr_opts.bannerfile) != DROPBEAR_SUCCESS) {
++		dropbear_log(LOG_WARNING, "Error reading banner file '%s'",
++				svr_opts.bannerfile);
++		buf_free(svr_opts.banner);
++		svr_opts.banner = NULL;
++		return;
++	}
++	buf_setpos(svr_opts.banner, 0);
++
++}
diff --git a/package/network/services/dropbear/patches/014-dropbearkey-ignore-unsupported-command-line-option.patch b/package/network/services/dropbear/patches/014-dropbearkey-ignore-unsupported-command-line-option.patch
new file mode 100644
index 00000000000000..ff130f8be0a9bd
--- /dev/null
+++ b/package/network/services/dropbear/patches/014-dropbearkey-ignore-unsupported-command-line-option.patch
@@ -0,0 +1,60 @@
+From ec26975d442163b66d1646a48e022bc8c2f1607a Mon Sep 17 00:00:00 2001
+From: Sergey Ponomarev <stokito@gmail.com>
+Date: Sun, 27 Aug 2023 00:07:05 +0300
+Subject: dropbearkey.c Ignore unsupported command line options
+
+To generate non interactively a key with OpenSSH the simplest command is:
+
+ssh-keygen -t ed25519 -q -N '' -f ~/.ssh/id_ed25519
+
+The command has two options -q quiet and -N passphrase which aren't supported by the dropbearkey.
+
+To improve interoperability add explicit ignoring of the -q and -N with empty passphrase.
+Also ignore the -v even if the DEBUG_TRACE is not set.
+
+Signed-off-by: Sergey Ponomarev <stokito@gmail.com>
+---
+ dropbearkey.c | 15 +++++++++++++--
+ 1 file changed, 13 insertions(+), 2 deletions(-)
+
+--- a/dropbearkey.c
++++ b/dropbearkey.c
+@@ -159,6 +159,7 @@ int main(int argc, char ** argv) {
+ 	enum signkey_type keytype = DROPBEAR_SIGNKEY_NONE;
+ 	char * typetext = NULL;
+ 	char * sizetext = NULL;
++	char * passphrase = NULL;
+ 	unsigned int bits = 0, genbits;
+ 	int printpub = 0;
+ 
+@@ -194,11 +195,16 @@ int main(int argc, char ** argv) {
+ 					printhelp(argv[0]);
+ 					exit(EXIT_SUCCESS);
+ 					break;
+-#if DEBUG_TRACE
+ 				case 'v':
++#if DEBUG_TRACE
+ 					debug_trace = DROPBEAR_VERBOSE_LEVEL;
+-					break;
+ #endif
++					break;
++				case 'q':
++					break;  /* quiet is default */
++				case 'N':
++					next = &passphrase;
++					break;
+ 				default:
+ 					fprintf(stderr, "Unknown argument %s\n", argv[i]);
+ 					printhelp(argv[0]);
+@@ -266,6 +272,11 @@ int main(int argc, char ** argv) {
+ 		check_signkey_bits(keytype, bits);;
+ 	}
+ 
++	if (passphrase && *passphrase != '\0') {
++		fprintf(stderr, "Only empty passphrase is supported\n");
++		exit(EXIT_FAILURE);
++	}
++
+ 	genbits = signkey_generate_get_bits(keytype, bits);
+ 	fprintf(stderr, "Generating %u bit %s key, this may take a while...\n", genbits, typetext);
+ 	if (signkey_generate(keytype, bits, filename, 0) == DROPBEAR_FAILURE)
diff --git a/package/network/services/dropbear/patches/015-libtommath-fix-possible-integer-overflow.patch b/package/network/services/dropbear/patches/015-libtommath-fix-possible-integer-overflow.patch
new file mode 100644
index 00000000000000..f39417adb79482
--- /dev/null
+++ b/package/network/services/dropbear/patches/015-libtommath-fix-possible-integer-overflow.patch
@@ -0,0 +1,121 @@
+From 3b576d95dcf791d7b945e75f639da8f89c1685a2 Mon Sep 17 00:00:00 2001
+From: czurnieden <czurnieden@gmx.de>
+Date: Tue, 9 May 2023 17:17:12 +0200
+Subject: Fix possible integer overflow
+
+---
+ libtommath/bn_mp_2expt.c                | 4 ++++
+ libtommath/bn_mp_grow.c                 | 4 ++++
+ libtommath/bn_mp_init_size.c            | 5 +++++
+ libtommath/bn_mp_mul_2d.c               | 4 ++++
+ libtommath/bn_s_mp_mul_digs.c           | 4 ++++
+ libtommath/bn_s_mp_mul_digs_fast.c      | 4 ++++
+ libtommath/bn_s_mp_mul_high_digs.c      | 4 ++++
+ libtommath/bn_s_mp_mul_high_digs_fast.c | 4 ++++
+ 8 files changed, 33 insertions(+)
+
+--- a/libtommath/bn_mp_2expt.c
++++ b/libtommath/bn_mp_2expt.c
+@@ -12,6 +12,10 @@ mp_err mp_2expt(mp_int *a, int b)
+ {
+    mp_err    err;
+ 
++   if (b < 0) {
++      return MP_VAL;
++   }
++
+    /* zero a as per default */
+    mp_zero(a);
+ 
+--- a/libtommath/bn_mp_grow.c
++++ b/libtommath/bn_mp_grow.c
+@@ -9,6 +9,10 @@ mp_err mp_grow(mp_int *a, int size)
+    int     i;
+    mp_digit *tmp;
+ 
++   if (size < 0) {
++      return MP_VAL;
++   }
++
+    /* if the alloc size is smaller alloc more ram */
+    if (a->alloc < size) {
+       /* reallocate the array a->dp
+--- a/libtommath/bn_mp_init_size.c
++++ b/libtommath/bn_mp_init_size.c
+@@ -6,6 +6,11 @@
+ /* init an mp_init for a given size */
+ mp_err mp_init_size(mp_int *a, int size)
+ {
++
++   if (size < 0) {
++      return MP_VAL;
++   }
++
+    size = MP_MAX(MP_MIN_PREC, size);
+ 
+    /* alloc mem */
+--- a/libtommath/bn_mp_mul_2d.c
++++ b/libtommath/bn_mp_mul_2d.c
+@@ -9,6 +9,10 @@ mp_err mp_mul_2d(const mp_int *a, int b,
+    mp_digit d;
+    mp_err   err;
+ 
++   if (b < 0) {
++      return MP_VAL;
++   }
++
+    /* copy */
+    if (a != c) {
+       if ((err = mp_copy(a, c)) != MP_OKAY) {
+--- a/libtommath/bn_s_mp_mul_digs.c
++++ b/libtommath/bn_s_mp_mul_digs.c
+@@ -16,6 +16,10 @@ mp_err s_mp_mul_digs(const mp_int *a, co
+    mp_word r;
+    mp_digit tmpx, *tmpt, *tmpy;
+ 
++   if (digs < 0) {
++      return MP_VAL;
++   }
++
+    /* can we use the fast multiplier? */
+    if ((digs < MP_WARRAY) &&
+        (MP_MIN(a->used, b->used) < MP_MAXFAST)) {
+--- a/libtommath/bn_s_mp_mul_digs_fast.c
++++ b/libtommath/bn_s_mp_mul_digs_fast.c
+@@ -26,6 +26,10 @@ mp_err s_mp_mul_digs_fast(const mp_int *
+    mp_digit W[MP_WARRAY];
+    mp_word  _W;
+ 
++   if (digs < 0) {
++      return MP_VAL;
++   }
++
+    /* grow the destination as required */
+    if (c->alloc < digs) {
+       if ((err = mp_grow(c, digs)) != MP_OKAY) {
+--- a/libtommath/bn_s_mp_mul_high_digs.c
++++ b/libtommath/bn_s_mp_mul_high_digs.c
+@@ -15,6 +15,10 @@ mp_err s_mp_mul_high_digs(const mp_int *
+    mp_word  r;
+    mp_digit tmpx, *tmpt, *tmpy;
+ 
++   if (digs < 0) {
++      return MP_VAL;
++   }
++
+    /* can we use the fast multiplier? */
+    if (MP_HAS(S_MP_MUL_HIGH_DIGS_FAST)
+        && ((a->used + b->used + 1) < MP_WARRAY)
+--- a/libtommath/bn_s_mp_mul_high_digs_fast.c
++++ b/libtommath/bn_s_mp_mul_high_digs_fast.c
+@@ -19,6 +19,10 @@ mp_err s_mp_mul_high_digs_fast(const mp_
+    mp_digit W[MP_WARRAY];
+    mp_word  _W;
+ 
++   if (digs < 0) {
++      return MP_VAL;
++   }
++
+    /* grow the destination as required */
+    pa = a->used + b->used;
+    if (c->alloc < pa) {
diff --git a/package/network/services/dropbear/patches/016-src-svr-tcpfwd-Fix-noremotetcp-behavior.patch b/package/network/services/dropbear/patches/016-src-svr-tcpfwd-Fix-noremotetcp-behavior.patch
new file mode 100644
index 00000000000000..b6933120e6f86b
--- /dev/null
+++ b/package/network/services/dropbear/patches/016-src-svr-tcpfwd-Fix-noremotetcp-behavior.patch
@@ -0,0 +1,35 @@
+From 3cf8344769eda55e26eee53c1898b2c66544f188 Mon Sep 17 00:00:00 2001
+From: Justin Chen <justin.chen@broadcom.com>
+Date: Fri, 8 Sep 2023 11:35:18 -0700
+Subject: src: svr-tcpfwd: Fix noremotetcp behavior
+
+If noremotetcp is set, we should still reply with
+send_msg_request_failed. This matches the behavior
+of !DROPBEAR_SVR_REMOTETCPFWD.
+
+We were seeing keepalive packets being ignored when
+the "-k" option was used.
+---
+ svr-tcpfwd.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+--- a/svr-tcpfwd.c
++++ b/svr-tcpfwd.c
+@@ -79,14 +79,14 @@ void recv_msg_global_request_remotetcp()
+ 
+ 	TRACE(("enter recv_msg_global_request_remotetcp"))
+ 
++	reqname = buf_getstring(ses.payload, &namelen);
++	wantreply = buf_getbool(ses.payload);
++
+ 	if (svr_opts.noremotetcp || !svr_pubkey_allows_tcpfwd()) {
+ 		TRACE(("leave recv_msg_global_request_remotetcp: remote tcp forwarding disabled"))
+ 		goto out;
+ 	}
+ 
+-	reqname = buf_getstring(ses.payload, &namelen);
+-	wantreply = buf_getbool(ses.payload);
+-
+ 	if (namelen > MAX_NAME_LEN) {
+ 		TRACE(("name len is wrong: %d", namelen))
+ 		goto out;
diff --git a/package/network/services/dropbear/patches/017-Don-t-try-to-shutdown-a-pty.patch b/package/network/services/dropbear/patches/017-Don-t-try-to-shutdown-a-pty.patch
new file mode 100644
index 00000000000000..603c61d6fb1028
--- /dev/null
+++ b/package/network/services/dropbear/patches/017-Don-t-try-to-shutdown-a-pty.patch
@@ -0,0 +1,32 @@
+From e28ba1b9975eab48799aa3ed77d3cd91627d7b27 Mon Sep 17 00:00:00 2001
+From: Matt Johnston <matt@ucc.asn.au>
+Date: Sat, 9 Dec 2023 23:10:41 +0800
+Subject: Don't try to shutdown() a pty
+
+shutdown() of a pty doesn't work (ENOTSOCK), so we should close
+it instead.
+
+This will ensure that PTY controlling terminals are closed when a
+session exits, including when multiple sessions run over a single SSH
+connection.  In the normal case of a single session, the PTY controlling
+terminal would be closed when the Dropbear server process exits anyway.
+
+This possibly fixes #264 on github
+
+It is possible that there could be subtle changes to PTY flushing
+behaviour, though nothing caught by tests at present.
+---
+ svr-chansession.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/svr-chansession.c
++++ b/svr-chansession.c
+@@ -910,7 +910,7 @@ static int ptycommand(struct Channel *ch
+ 		channel->readfd = chansess->master;
+ 		/* don't need to set stderr here */
+ 		ses.maxfd = MAX(ses.maxfd, chansess->master);
+-		channel->bidir_fd = 1;
++		channel->bidir_fd = 0;
+ 
+ 		setnonblocking(chansess->master);
+ 
diff --git a/package/network/services/dropbear/patches/018-dropbearkey-add-alias-to-ssh-keygen.patch b/package/network/services/dropbear/patches/018-dropbearkey-add-alias-to-ssh-keygen.patch
new file mode 100644
index 00000000000000..9c70c3141c8d2d
--- /dev/null
+++ b/package/network/services/dropbear/patches/018-dropbearkey-add-alias-to-ssh-keygen.patch
@@ -0,0 +1,33 @@
+From 806586b585806cbe32013bcd3af3847278972060 Mon Sep 17 00:00:00 2001
+From: Sergey Ponomarev <stokito@gmail.com>
+Date: Sun, 10 Dec 2023 10:31:56 +0200
+Subject: dropbearkey: add alias to ssh-keygen
+
+The dropbearkey is partially compatible with ssh-keygen and can be used as an alias.
+
+Closes: #263
+---
+ dbmulti.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+--- a/dbmulti.c
++++ b/dbmulti.c
+@@ -41,7 +41,8 @@ static int runprog(const char *multipath
+ 		}
+ #endif
+ #ifdef DBMULTI_dropbearkey
+-		if (strcmp(progname, "dropbearkey") == 0) {
++		if (strcmp(progname, "dropbearkey") == 0
++				|| strcmp(progname, "ssh-keygen") == 0) {
+ 			return dropbearkey_main(argc, argv);
+ 		}
+ #endif
+@@ -88,7 +89,7 @@ int main(int argc, char ** argv) {
+ 			"'dbclient' or 'ssh' - the Dropbear client\n"
+ #endif
+ #ifdef DBMULTI_dropbearkey
+-			"'dropbearkey' - the key generator\n"
++			"'dropbearkey' or 'ssh-keygen' - the key generator\n"
+ #endif
+ #ifdef DBMULTI_dropbearconvert
+ 			"'dropbearconvert' - the key converter\n"
diff --git a/package/network/services/dropbear/patches/019-Allow-inetd-with-non-syslog.patch b/package/network/services/dropbear/patches/019-Allow-inetd-with-non-syslog.patch
new file mode 100644
index 00000000000000..3544f2123c62cf
--- /dev/null
+++ b/package/network/services/dropbear/patches/019-Allow-inetd-with-non-syslog.patch
@@ -0,0 +1,34 @@
+From 383cc8c97a9420aad9cf93d88e77ec636b183a9d Mon Sep 17 00:00:00 2001
+From: Matt Johnston <matt@ucc.asn.au>
+Date: Mon, 11 Dec 2023 23:18:09 +0800
+Subject: Allow inetd with non-syslog
+
+An inetd-alike should be able to distinguish stdout and stderr, so
+it's a valid configuration.
+
+Fixes #218 on github
+---
+ svr-runopts.c | 12 ------------
+ 1 file changed, 12 deletions(-)
+
+--- a/svr-runopts.c
++++ b/svr-runopts.c
+@@ -443,18 +443,6 @@ void svr_getopts(int argc, char ** argv)
+ 		}
+ 	}
+ 
+-#if INETD_MODE
+-	if (svr_opts.inetdmode && (
+-		opts.usingsyslog == 0
+-#if DEBUG_TRACE
+-		|| debug_trace
+-#endif
+-		)) {
+-		/* log output goes to stderr which would get sent over the inetd network socket */
+-		dropbear_exit("Dropbear inetd mode is incompatible with debug -v or non-syslog");
+-	}
+-#endif
+-
+ 	if (svr_opts.multiauthmethod && svr_opts.noauthpass) {
+ 		dropbear_exit("-t and -s are incompatible");
+ 	}
diff --git a/package/network/services/dropbear/patches/020-Fix-test-for-multiuser-kernels.patch b/package/network/services/dropbear/patches/020-Fix-test-for-multiuser-kernels.patch
new file mode 100644
index 00000000000000..8d016faa9c71d8
--- /dev/null
+++ b/package/network/services/dropbear/patches/020-Fix-test-for-multiuser-kernels.patch
@@ -0,0 +1,33 @@
+From 9ac650401ffc2fb05c9328d26e76a5e7ae39152a Mon Sep 17 00:00:00 2001
+From: Matt Johnston <matt@ucc.asn.au>
+Date: Mon, 11 Dec 2023 23:31:22 +0800
+Subject: Fix test for multiuser kernels
+
+getuid() succeeds even on non-multiuser kernels. Instead
+getgroups() is a valid test.
+
+Fixes #214 on github
+---
+ common-session.c | 11 +++++++----
+ 1 file changed, 7 insertions(+), 4 deletions(-)
+
+--- a/common-session.c
++++ b/common-session.c
+@@ -71,10 +71,13 @@ void common_session_init(int sock_in, in
+ #if !DROPBEAR_SVR_MULTIUSER
+ 	/* A sanity check to prevent an accidental configuration option
+ 	   leaving multiuser systems exposed */
+-	errno = 0;
+-	getuid();
+-	if (errno != ENOSYS) {
+-		dropbear_exit("Non-multiuser Dropbear requires a non-multiuser kernel");
++	{
++		int ret;
++		errno = 0;
++		ret = getgroups(0, NULL);
++		if (!(ret == -1 && errno == ENOSYS)) {
++			dropbear_exit("Non-multiuser Dropbear requires a non-multiuser kernel");
++		}
+ 	}
+ #endif
+ 
diff --git a/package/network/services/dropbear/patches/021-Implement-Strict-KEX-mode.patch b/package/network/services/dropbear/patches/021-Implement-Strict-KEX-mode.patch
new file mode 100644
index 00000000000000..d490d9545a2531
--- /dev/null
+++ b/package/network/services/dropbear/patches/021-Implement-Strict-KEX-mode.patch
@@ -0,0 +1,216 @@
+From 6e43be5c7b99dbee49dc72b6f989f29fdd7e9356 Mon Sep 17 00:00:00 2001
+From: Matt Johnston <matt@ucc.asn.au>
+Date: Mon, 20 Nov 2023 14:02:47 +0800
+Subject: Implement Strict KEX mode
+
+As specified by OpenSSH with kex-strict-c-v00@openssh.com and
+kex-strict-s-v00@openssh.com.
+---
+ cli-session.c    | 11 +++++++++++
+ common-algo.c    |  6 ++++++
+ common-kex.c     | 26 +++++++++++++++++++++++++-
+ kex.h            |  3 +++
+ process-packet.c | 34 +++++++++++++++++++---------------
+ ssh.h            |  4 ++++
+ svr-session.c    |  3 +++
+ 7 files changed, 71 insertions(+), 16 deletions(-)
+
+--- a/cli-session.c
++++ b/cli-session.c
+@@ -46,6 +46,7 @@ static void cli_finished(void) ATTRIB_NO
+ static void recv_msg_service_accept(void);
+ static void cli_session_cleanup(void);
+ static void recv_msg_global_request_cli(void);
++static void cli_algos_initialise(void);
+ 
+ struct clientsession cli_ses; /* GLOBAL */
+ 
+@@ -117,6 +118,7 @@ void cli_session(int sock_in, int sock_o
+ 	}
+ 
+ 	chaninitialise(cli_chantypes);
++	cli_algos_initialise();
+ 
+ 	/* Set up cli_ses vars */
+ 	cli_session_init(proxy_cmd_pid);
+@@ -487,3 +489,12 @@ void cli_dropbear_log(int priority, cons
+ 	fflush(stderr);
+ }
+ 
++static void cli_algos_initialise(void) {
++	algo_type *algo;
++	for (algo = sshkex; algo->name; algo++) {
++		if (strcmp(algo->name, SSH_STRICT_KEX_S) == 0) {
++			algo->usable = 0;
++		}
++	}
++}
++
+--- a/common-algo.c
++++ b/common-algo.c
+@@ -308,6 +308,12 @@ algo_type sshkex[] = {
+ 	{SSH_EXT_INFO_C, 0, NULL, 1, NULL},
+ #endif
+ #endif
++#if DROPBEAR_CLIENT
++	{SSH_STRICT_KEX_C, 0, NULL, 1, NULL},
++#endif
++#if DROPBEAR_SERVER
++	{SSH_STRICT_KEX_S, 0, NULL, 1, NULL},
++#endif
+ 	{NULL, 0, NULL, 0, NULL}
+ };
+ 
+--- a/common-kex.c
++++ b/common-kex.c
+@@ -183,6 +183,10 @@ void send_msg_newkeys() {
+ 	gen_new_keys();
+ 	switch_keys();
+ 
++	if (ses.kexstate.strict_kex) {
++		ses.transseq = 0;
++	}
++
+ 	TRACE(("leave send_msg_newkeys"))
+ }
+ 
+@@ -193,7 +197,11 @@ void recv_msg_newkeys() {
+ 
+ 	ses.kexstate.recvnewkeys = 1;
+ 	switch_keys();
+-	
++
++	if (ses.kexstate.strict_kex) {
++		ses.recvseq = 0;
++	}
++
+ 	TRACE(("leave recv_msg_newkeys"))
+ }
+ 
+@@ -550,6 +558,10 @@ void recv_msg_kexinit() {
+ 
+ 	ses.kexstate.recvkexinit = 1;
+ 
++	if (ses.kexstate.strict_kex && !ses.kexstate.donefirstkex && ses.recvseq != 1) {
++		dropbear_exit("First packet wasn't kexinit");
++	}
++
+ 	TRACE(("leave recv_msg_kexinit"))
+ }
+ 
+@@ -859,6 +871,18 @@ static void read_kex_algos() {
+ 	}
+ #endif
+ 
++	if (!ses.kexstate.donefirstkex) {
++		const char* strict_name;
++		if (IS_DROPBEAR_CLIENT) {
++			strict_name = SSH_STRICT_KEX_S;
++		} else {
++			strict_name = SSH_STRICT_KEX_C;
++		}
++		if (buf_has_algo(ses.payload, strict_name) == DROPBEAR_SUCCESS) {
++			ses.kexstate.strict_kex = 1;
++		}
++	}
++
+ 	algo = buf_match_algo(ses.payload, sshkex, kexguess2, &goodguess);
+ 	allgood &= goodguess;
+ 	if (algo == NULL || algo->data == NULL) {
+--- a/kex.h
++++ b/kex.h
+@@ -83,6 +83,9 @@ struct KEXState {
+ 
+ 	unsigned our_first_follows_matches : 1;
+ 
++	/* Boolean indicating that strict kex mode is in use */
++	unsigned int strict_kex;
++
+ 	time_t lastkextime; /* time of the last kex */
+ 	unsigned int datatrans; /* data transmitted since last kex */
+ 	unsigned int datarecv; /* data received since last kex */
+--- a/process-packet.c
++++ b/process-packet.c
+@@ -44,6 +44,7 @@ void process_packet() {
+ 
+ 	unsigned char type;
+ 	unsigned int i;
++	unsigned int first_strict_kex = ses.kexstate.strict_kex && !ses.kexstate.donefirstkex;
+ 	time_t now;
+ 
+ 	TRACE2(("enter process_packet"))
+@@ -54,22 +55,24 @@ void process_packet() {
+ 	now = monotonic_now();
+ 	ses.last_packet_time_keepalive_recv = now;
+ 
+-	/* These packets we can receive at any time */
+-	switch(type) {
+ 
+-		case SSH_MSG_IGNORE:
+-			goto out;
+-		case SSH_MSG_DEBUG:
+-			goto out;
+-
+-		case SSH_MSG_UNIMPLEMENTED:
+-			/* debugging XXX */
+-			TRACE(("SSH_MSG_UNIMPLEMENTED"))
+-			goto out;
+-			
+-		case SSH_MSG_DISCONNECT:
+-			/* TODO cleanup? */
+-			dropbear_close("Disconnect received");
++	if (type == SSH_MSG_DISCONNECT) {
++		/* Allowed at any time */
++		dropbear_close("Disconnect received");
++	}
++
++	/* These packets may be received at any time,
++	   except during first kex with strict kex */
++	if (!first_strict_kex) {
++		switch(type) {
++			case SSH_MSG_IGNORE:
++				goto out;
++			case SSH_MSG_DEBUG:
++				goto out;
++			case SSH_MSG_UNIMPLEMENTED:
++				TRACE(("SSH_MSG_UNIMPLEMENTED"))
++				goto out;
++		}
+ 	}
+ 
+ 	/* Ignore these packet types so that keepalives don't interfere with
+@@ -98,7 +101,8 @@ void process_packet() {
+ 			if (type >= 1 && type <= 49
+ 				&& type != SSH_MSG_SERVICE_REQUEST
+ 				&& type != SSH_MSG_SERVICE_ACCEPT
+-				&& type != SSH_MSG_KEXINIT)
++				&& type != SSH_MSG_KEXINIT
++				&& !first_strict_kex)
+ 			{
+ 				TRACE(("unknown allowed packet during kexinit"))
+ 				recv_unimplemented();
+--- a/ssh.h
++++ b/ssh.h
+@@ -100,6 +100,10 @@
+ #define SSH_EXT_INFO_C "ext-info-c"
+ #define SSH_SERVER_SIG_ALGS "server-sig-algs"
+ 
++/* OpenSSH strict KEX feature */
++#define SSH_STRICT_KEX_S "kex-strict-s-v00@openssh.com"
++#define SSH_STRICT_KEX_C "kex-strict-c-v00@openssh.com"
++
+ /* service types */
+ #define SSH_SERVICE_USERAUTH "ssh-userauth"
+ #define SSH_SERVICE_USERAUTH_LEN 12
+--- a/svr-session.c
++++ b/svr-session.c
+@@ -370,6 +370,9 @@ static void svr_algos_initialise(void) {
+ 			algo->usable = 0;
+ 		}
+ #endif
++		if (strcmp(algo->name, SSH_STRICT_KEX_C) == 0) {
++			algo->usable = 0;
++		}
+ 	}
+ }
+ 
diff --git a/package/network/services/dropbear/patches/100-pubkey_path.patch b/package/network/services/dropbear/patches/100-pubkey_path.patch
index 0403198062f316..b1075f84642ce7 100644
--- a/package/network/services/dropbear/patches/100-pubkey_path.patch
+++ b/package/network/services/dropbear/patches/100-pubkey_path.patch
@@ -1,6 +1,6 @@
 --- a/svr-authpubkey.c
 +++ b/svr-authpubkey.c
-@@ -77,6 +77,13 @@ static void send_msg_userauth_pk_ok(cons
+@@ -78,6 +78,13 @@ static void send_msg_userauth_pk_ok(cons
  		const unsigned char* keyblob, unsigned int keybloblen);
  static int checkfileperm(char * filename);
  
@@ -14,7 +14,7 @@
  /* process a pubkey auth request, sending success or failure message as
   * appropriate */
  void svr_auth_pubkey(int valid_user) {
-@@ -439,14 +446,21 @@ static int checkpubkey(const char* keyal
+@@ -462,14 +469,21 @@ static int checkpubkey(const char* keyal
  	if (checkpubkeyperms() == DROPBEAR_FAILURE) {
  		TRACE(("bad authorized_keys permissions, or file doesn't exist"))
  	} else {
@@ -44,7 +44,7 @@
  
  		authfile = fopen(filename, "r");
  		if (!authfile) {
-@@ -520,27 +534,41 @@ static int checkpubkeyperms() {
+@@ -543,27 +557,41 @@ static int checkpubkeyperms() {
  		goto out;
  	}
  
diff --git a/package/network/services/dropbear/patches/130-ssh_ignore_x_args.patch b/package/network/services/dropbear/patches/130-ssh_ignore_x_args.patch
index d7f589801dce2b..a26f33dfbcebca 100644
--- a/package/network/services/dropbear/patches/130-ssh_ignore_x_args.patch
+++ b/package/network/services/dropbear/patches/130-ssh_ignore_x_args.patch
@@ -1,8 +1,8 @@
 --- a/cli-runopts.c
 +++ b/cli-runopts.c
-@@ -325,6 +325,10 @@ void cli_getopts(int argc, char ** argv)
- 				case 'b':
- 					next = &bind_arg;
+@@ -329,6 +329,10 @@ void cli_getopts(int argc, char ** argv)
+ 				case 'z':
+ 					opts.disable_ip_tos = 1;
  					break;
 +				case 'x':
 +					/* compatibility with openssh cli
diff --git a/package/network/services/dropbear/patches/900-configure-hardening.patch b/package/network/services/dropbear/patches/900-configure-hardening.patch
index 4f806f8b2511f7..5dc84849befdc8 100644
--- a/package/network/services/dropbear/patches/900-configure-hardening.patch
+++ b/package/network/services/dropbear/patches/900-configure-hardening.patch
@@ -1,6 +1,6 @@
 --- a/configure.ac
 +++ b/configure.ac
-@@ -74,53 +74,6 @@ AC_ARG_ENABLE(harden,
+@@ -87,54 +87,6 @@ AC_ARG_ENABLE(harden,
  
  if test "$hardenbuild" -eq 1; then
  	AC_MSG_NOTICE(Checking for available hardened build flags:)
@@ -11,15 +11,15 @@
 -
 -		OLDLDFLAGS="$LDFLAGS"
 -		TESTFLAGS="-Wl,-pie"
--		LDFLAGS="$LDFLAGS $TESTFLAGS"
--		AC_LINK_IFELSE([AC_LANG_PROGRAM([])], 
--			[AC_MSG_NOTICE([Setting $TESTFLAGS])], 
+-		LDFLAGS="$TESTFLAGS $LDFLAGS"
+-		AC_LINK_IFELSE([AC_LANG_PROGRAM([])],
+-			[AC_MSG_NOTICE([Setting $TESTFLAGS])],
 -			[
 -				LDFLAGS="$OLDLDFLAGS"
 -				TESTFLAGS="-pie"
--				LDFLAGS="$LDFLAGS $TESTFLAGS"
--				AC_LINK_IFELSE([AC_LANG_PROGRAM([])], 
--					[AC_MSG_NOTICE([Setting $TESTFLAGS])], 
+-				LDFLAGS="$TESTFLAGS $LDFLAGS"
+-				AC_LINK_IFELSE([AC_LANG_PROGRAM([])],
+-					[AC_MSG_NOTICE([Setting $TESTFLAGS])],
 -					[AC_MSG_NOTICE([Not setting $TESTFLAGS]); LDFLAGS="$OLDLDFLAGS" ]
 -					)
 -			]
@@ -27,30 +27,31 @@
 -		# readonly elf relocation sections (relro)
 -		OLDLDFLAGS="$LDFLAGS"
 -		TESTFLAGS="-Wl,-z,now -Wl,-z,relro"
--		LDFLAGS="$LDFLAGS $TESTFLAGS"
--		AC_LINK_IFELSE([AC_LANG_PROGRAM([])], 
--			[AC_MSG_NOTICE([Setting $TESTFLAGS])], 
+-		LDFLAGS="$TESTFLAGS $LDFLAGS"
+-		AC_LINK_IFELSE([AC_LANG_PROGRAM([])],
+-			[AC_MSG_NOTICE([Setting $TESTFLAGS])],
 -			[AC_MSG_NOTICE([Not setting $TESTFLAGS]); LDFLAGS="$OLDLDFLAGS" ]
 -			)
 -	fi # non-static
 -	# stack protector. -strong is good but only in gcc 4.9 or later
 -	OLDCFLAGS="$CFLAGS"
 -	TESTFLAGS="-fstack-protector-strong"
--	CFLAGS="$CFLAGS $TESTFLAGS"
--	AC_COMPILE_IFELSE([AC_LANG_PROGRAM([])], 
--	    [AC_MSG_NOTICE([Setting $TESTFLAGS])], 
+-	CFLAGS="$TESTFLAGS $CFLAGS"
+-	AC_LINK_IFELSE([AC_LANG_PROGRAM([])],
+-	    [AC_MSG_NOTICE([Setting $TESTFLAGS])],
 -	    [
 -			CFLAGS="$OLDCFLAGS"
 -			TESTFLAGS="-fstack-protector --param=ssp-buffer-size=4"
--			CFLAGS="$CFLAGS $TESTFLAGS"
--			AC_COMPILE_IFELSE([AC_LANG_PROGRAM([])], 
--			    [AC_MSG_NOTICE([Setting $TESTFLAGS])], 
+-			CFLAGS="$TESTFLAGS $CFLAGS"
+-			AC_LINK_IFELSE([AC_LANG_PROGRAM([])],
+-			    [AC_MSG_NOTICE([Setting $TESTFLAGS])],
 -			    [AC_MSG_NOTICE([Not setting $TESTFLAGS]); CFLAGS="$OLDCFLAGS" ]
 -			    )
 -	    ]
 -	    )
 -	# FORTIFY_SOURCE
 -	DB_TRYADDCFLAGS([-D_FORTIFY_SOURCE=2])
- 
+-
  	# Spectre v2 mitigations
  	DB_TRYADDCFLAGS([-mfunction-return=thunk])
+ 	DB_TRYADDCFLAGS([-mindirect-branch=thunk])
diff --git a/package/network/services/dropbear/patches/901-bundled-libs-cflags.patch b/package/network/services/dropbear/patches/901-bundled-libs-cflags.patch
index 2432b4ef72eae7..a9a441ce76e69c 100644
--- a/package/network/services/dropbear/patches/901-bundled-libs-cflags.patch
+++ b/package/network/services/dropbear/patches/901-bundled-libs-cflags.patch
@@ -1,48 +1,29 @@
---- a/libtomcrypt/makefile_include.mk
-+++ b/libtomcrypt/makefile_include.mk
-@@ -94,6 +94,13 @@ endif
+--- a/configure.ac
++++ b/configure.ac
+@@ -45,11 +45,8 @@ fi
+ # LTM_CFLAGS is given to ./configure by the user, 
+ # DROPBEAR_LTM_CFLAGS is substituted in the LTM Makefile.in
+ DROPBEAR_LTM_CFLAGS="$LTM_CFLAGS"
+-if test -z "$DROPBEAR_LTM_CFLAGS"; then
+-	DROPBEAR_LTM_CFLAGS="-O3 -funroll-loops -fomit-frame-pointer"
+-fi
+-AC_MSG_NOTICE(Setting LTM_CFLAGS to $DROPBEAR_LTM_CFLAGS)
+-AC_ARG_VAR(LTM_CFLAGS, CFLAGS for bundled libtommath. Default -O3 -funroll-loops -fomit-frame-pointer)
++AC_MSG_NOTICE(Setting LTM_CFLAGS to '$DROPBEAR_LTM_CFLAGS')
++AC_ARG_VAR(LTM_CFLAGS, CFLAGS for bundled libtommath. Defaults to empty string)
+ AC_SUBST(DROPBEAR_LTM_CFLAGS)
  
- LTC_CFLAGS += -Wno-type-limits
+ AC_MSG_NOTICE([Checking if compiler '$CC' supports -Wno-pointer-sign])
+--- a/libtomcrypt/src/headers/tomcrypt_dropbear.h
++++ b/libtomcrypt/src/headers/tomcrypt_dropbear.h
+@@ -7,8 +7,10 @@
  
-+ifdef OPENWRT_BUILD
-+  ifeq (-Os,$(filter -Os,$(CFLAGS)))
-+    LTC_CFLAGS += -DLTC_SMALL_CODE
-+  endif
-+else
-+  ### ! OPENWRT_BUILD
-+
- ifdef LTC_DEBUG
- $(info Debug build)
- # compile for DEBUGGING (required for ccmalloc checking!!!)
-@@ -121,6 +128,9 @@ endif
- endif # COMPILE_SMALL
- endif # COMPILE_DEBUG
+ /* Use small code where possible */
+ #if DROPBEAR_SMALL_CODE
++#ifndef LTC_SMALL_CODE
+ #define LTC_SMALL_CODE
+ #endif
++#endif
  
-+  ### ! OPENWRT_BUILD
-+endif
-+
- 
- ifneq ($(findstring clang,$(CC)),)
- LTC_CFLAGS += -Wno-typedef-redefinition -Wno-tautological-compare -Wno-builtin-requires-header -Wno-missing-field-initializers
---- a/libtommath/makefile_include.mk
-+++ b/libtommath/makefile_include.mk
-@@ -70,6 +70,9 @@ else
- LTM_CFLAGS += -Wsystem-headers
- endif
- 
-+ifndef OPENWRT_BUILD
-+  ### ! OPENWRT_BUILD
-+
- ifdef COMPILE_DEBUG
- #debug
- LTM_CFLAGS += -g3
-@@ -90,6 +93,9 @@ endif
- 
- endif # COMPILE_SIZE
- 
-+  ### ! OPENWRT_BUILD
-+endif
-+
- ifneq ($(findstring clang,$(CC)),)
- LTM_CFLAGS += -Wno-typedef-redefinition -Wno-tautological-compare -Wno-builtin-requires-header
- endif
+ /* Fewer entries needed */
+ #define TAB_SIZE      5
diff --git a/package/network/services/dropbear/patches/910-signkey-fix-use-of-rsa-sha2-256-pubkeys.patch b/package/network/services/dropbear/patches/910-signkey-fix-use-of-rsa-sha2-256-pubkeys.patch
index f0788144038c24..059177a1c58174 100644
--- a/package/network/services/dropbear/patches/910-signkey-fix-use-of-rsa-sha2-256-pubkeys.patch
+++ b/package/network/services/dropbear/patches/910-signkey-fix-use-of-rsa-sha2-256-pubkeys.patch
@@ -21,7 +21,7 @@ Signed-off-by: Petr Štetiar <ynezz@true.cz>
 
 --- a/signkey.c
 +++ b/signkey.c
-@@ -646,8 +646,12 @@ int buf_verify(buffer * buf, sign_key *k
+@@ -652,10 +652,18 @@ int buf_verify(buffer * buf, sign_key *k
  	sigtype = signature_type_from_name(type_name, type_name_len);
  	m_free(type_name);
  
@@ -29,10 +29,16 @@ Signed-off-by: Petr Štetiar <ynezz@true.cz>
 -			dropbear_exit("Non-matching signing type");
 +	if (sigtype == DROPBEAR_SIGNATURE_NONE) {
 +		dropbear_exit("No signature type");
-+	}
-+
-+	if ((expect_sigtype != DROPBEAR_SIGNATURE_RSA_SHA256) && (expect_sigtype != sigtype)) {
-+		dropbear_exit("Non-matching signing type");
  	}
  
++#if DROPBEAR_RSA
++#if DROPBEAR_RSA_SHA256
++	if ((expect_sigtype != DROPBEAR_SIGNATURE_RSA_SHA256) && (expect_sigtype != sigtype)) {
++		dropbear_exit("Non-matching signing type");
++	}
++#endif
++#endif
++
  	keytype = signkey_type_from_signature(sigtype);
+ #if DROPBEAR_DSS
+ 	if (keytype == DROPBEAR_SIGNKEY_DSS) {
diff --git a/package/network/services/hostapd/Makefile b/package/network/services/hostapd/Makefile
index 17f9dcb581dbea..c8f476f7b8c88e 100644
--- a/package/network/services/hostapd/Makefile
+++ b/package/network/services/hostapd/Makefile
@@ -712,13 +712,10 @@ endef
 define Package/hostapd-common/install
 	$(INSTALL_DIR) $(1)/etc/capabilities $(1)/etc/rc.button $(1)/etc/hotplug.d/ieee80211 $(1)/etc/init.d $(1)/lib/netifd  $(1)/usr/share/acl.d $(1)/usr/share/hostap
 	$(INSTALL_BIN) ./files/dhcp-get-server.sh $(1)/lib/netifd/dhcp-get-server.sh
-	$(INSTALL_DATA) ./files/hostapd.sh $(1)/lib/netifd/hostapd.sh
 	$(INSTALL_BIN) ./files/wpad.init $(1)/etc/init.d/wpad
 	$(INSTALL_BIN) ./files/wps-hotplug.sh $(1)/etc/rc.button/wps
 	$(INSTALL_DATA) ./files/wpad_acl.json $(1)/usr/share/acl.d
 	$(INSTALL_DATA) ./files/wpad.json $(1)/etc/capabilities
-	$(INSTALL_DATA) ./files/common.uc $(1)/usr/share/hostap/
-	$(INSTALL_DATA) ./files/wdev.uc $(1)/usr/share/hostap/
 endef
 
 define Package/hostapd/install
diff --git a/package/network/services/lldpd/Makefile b/package/network/services/lldpd/Makefile
index 289adc55c9407b..1f8d1e546b0d5c 100644
--- a/package/network/services/lldpd/Makefile
+++ b/package/network/services/lldpd/Makefile
@@ -9,7 +9,7 @@ include $(TOPDIR)/rules.mk
 
 PKG_NAME:=lldpd
 PKG_VERSION:=1.0.17
-PKG_RELEASE:=1
+PKG_RELEASE:=2
 
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
 PKG_SOURCE_URL:=https://github.com/lldpd/lldpd/releases/download/$(PKG_VERSION)/
@@ -68,19 +68,28 @@ define Package/lldpd/install
 	$(INSTALL_BIN) ./files/lldpd.init $(1)/etc/init.d/lldpd
 	$(INSTALL_CONF) ./files/lldpd.config $(1)/etc/config/lldpd
 ifneq ($(CONFIG_LLDPD_WITH_CDP),y)
-	sed -i -e '/cdp/d' $(1)/etc/init.d/lldpd $(1)/etc/config/lldpd
+	sed -i -e 's/CONFIG_LLDPD_WITH_CDP=y/CONFIG_LLDPD_WITH_CDP=n/g' $(1)/etc/init.d/lldpd
+	sed -i -e '/cdp/d' $(1)/etc/config/lldpd
 endif
 ifneq ($(CONFIG_LLDPD_WITH_FDP),y)
-	sed -i -e '/fdp/d' $(1)/etc/init.d/lldpd $(1)/etc/config/lldpd
+	sed -i -e 's/CONFIG_LLDPD_WITH_FDP=y/CONFIG_LLDPD_WITH_FDP=n/g' $(1)/etc/init.d/lldpd
+	sed -i -e '/fdp/d' $(1)/etc/config/lldpd
 endif
 ifneq ($(CONFIG_LLDPD_WITH_EDP),y)
-	sed -i -e '/edp/d' $(1)/etc/init.d/lldpd $(1)/etc/config/lldpd
+	sed -i -e 's/CONFIG_LLDPD_WITH_EDP=y/CONFIG_LLDPD_WITH_EDP=n/g' $(1)/etc/init.d/lldpd
+	sed -i -e '/edp/d' $(1)/etc/config/lldpd
 endif
 ifneq ($(CONFIG_LLDPD_WITH_SONMP),y)
-	sed -i -e '/sonmp/d' $(1)/etc/init.d/lldpd $(1)/etc/config/lldpd
+	sed -i -e 's/CONFIG_LLDPD_WITH_SONMP=y/CONFIG_LLDPD_WITH_SONMP=n/g' $(1)/etc/init.d/lldpd
+	sed -i -e '/sonmp/d' $(1)/etc/config/lldpd
 endif
 ifneq ($(CONFIG_LLDPD_WITH_SNMP),y)
-	sed -i -e '/agentxsocket/d' $(1)/etc/init.d/lldpd $(1)/etc/config/lldpd
+	sed -i -e 's/CONFIG_LLDPD_WITH_SNMP=y/CONFIG_LLDPD_WITH_SNMP=n/g' $(1)/etc/init.d/lldpd
+	sed -i -e '/agentxsocket/d' $(1)/etc/config/lldpd
+endif
+ifneq ($(CONFIG_LLDPD_WITH_LLDPMED),y)
+	sed -i -e 's/CONFIG_LLDPD_WITH_LLDPMED=y/CONFIG_LLDPD_WITH_LLDPMED=n/g' $(1)/etc/init.d/lldpd
+	sed -i -e '/agentxsocket/d' $(1)/etc/config/lldpd
 endif
 endef
 
diff --git a/package/network/services/lldpd/files/lldpd.init b/package/network/services/lldpd/files/lldpd.init
index e1e8ac9fd4a5f7..f90b4a237cd0b6 100644
--- a/package/network/services/lldpd/files/lldpd.init
+++ b/package/network/services/lldpd/files/lldpd.init
@@ -4,12 +4,25 @@
 START=90
 STOP=01
 
+CONFIG_LLDPD_WITH_CDP=y
+CONFIG_LLDPD_WITH_EDP=y
+CONFIG_LLDPD_WITH_FDP=y
+CONFIG_LLDPD_WITH_LLDPMED=y
+CONFIG_LLDPD_WITH_SNMP=y
+CONFIG_LLDPD_WITH_SONMP=y
+
 USE_PROCD=1
+LLDPDBIN=/usr/sbin/lldpd
 LLDPCLI=/usr/sbin/lldpcli
 LLDPSOCKET=/var/run/lldpd.socket
 LLDPD_CONF=/tmp/lldpd.conf
 LLDPD_CONFS_DIR=/tmp/lldpd.d
 
+LLDPD_RUN=/var/run/lldpd
+LLDPD_RESTART_HASH=${LLDPD_RUN}/lldpd.restart_hash
+
+. "$IPKG_INSTROOT/lib/functions/network.sh"
+
 find_release_info()
 {
 	[ -s /etc/os-release ] && . /etc/os-release
@@ -19,10 +32,64 @@ find_release_info()
 	echo "${PRETTY_NAME:-Unknown OpenWrt release} @ $(cat /proc/sys/kernel/hostname)"
 }
 
+get_config_restart_hash() {
+	local var="$1"
+	local _string _hash v
+
+	config_load 'lldpd'
+
+	config_get      v 'config' 'lldp_class'; append _string "$v" ","
+	if [ "$CONFIG_LLDPD_WITH_SNMP" == "y" ]; then
+		config_get      v 'config' 'agentxsocket'; append _string "$v" ","
+	fi
+	config_get      v 'config' 'cid_interface'; append _string "$v" ","
+	config_get      v 'config' 'filter'; append _string "$v" ","
+	config_get_bool v 'config' 'readonly_mode'; append _string "$v" ","
+	config_get_bool v 'config' 'lldp_no_version'; append _string "$v" ","
+	if [ "$CONFIG_LLDPD_WITH_LLDPMED" == "y" ]; then
+		config_get_bool v 'config' 'lldpmed_no_inventory'; append _string "$v" ","
+	fi
+	config_get_bool v 'config' 'enable_lldp' 1; append _string "$v" ","
+	config_get_bool v 'config' 'force_lldp'; append _string "$v" ","
+	if [ "$CONFIG_LLDPD_WITH_CDP" == "y" ]; then
+		config_get_bool v 'config' 'enable_cdp'; append _string "$v" ","
+		config_get      v 'config' 'cdp_version'; append _string "$v" ","
+		config_get_bool v 'config' 'force_cdp'; append _string "$v" ","
+		config_get_bool v 'config' 'force_cdpv2'; append _string "$v" ","
+	fi
+	if [ "$CONFIG_LLDPD_WITH_EDP" == "y" ]; then
+		config_get_bool v 'config' 'enable_edp'; append _string "$v" ","
+		config_get_bool v 'config' 'force_edp'; append _string "$v" ","
+	fi
+	if [ "$CONFIG_LLDPD_WITH_FDP" == "y" ]; then
+		config_get_bool v 'config' 'enable_fdp'; append _string "$v" ","
+		config_get_bool v 'config' 'force_fdp'; append _string "$v" ","
+	fi
+	if [ "$CONFIG_LLDPD_WITH_SONMP" == "y" ]; then
+		config_get_bool v 'config' 'enable_sonmp'; append _string "$v" ","
+		config_get_bool v 'config' 'force_sonmp'; append _string "$v" ","
+	fi
+
+	_hash=`echo -n "${_string}" | md5sum | awk '{ print \$1 }'`
+	export -n "$var=$_hash"
+}
+
+get_config_cid_ifaces() {
+	local _ifacesCONFIG_LLDPD_WITH_FDP
+
+	local _iface _ifnames=""
+	for _iface in $_ifaces; do
+		local _ifname=""
+		if network_get_device _ifname "$_iface" || [ -e "/sys/class/net/$_iface" ]; then
+			append _ifnames "${_ifname:-$_iface}" ","
+		fi
+	done
+
+	export -n "${1}=$_ifnames"
+}
+
 write_lldpd_conf()
 {
-	. /lib/functions/network.sh
-
 	local lldp_description
 
 	config_load 'lldpd'
@@ -48,6 +115,29 @@ write_lldpd_conf()
 	local lldp_syscapabilities
 	config_get lldp_syscapabilities 'config' 'lldp_syscapabilities'
 
+	if [ "$CONFIG_LLDPD_WITH_LLDPMED" == "y" ]; then
+		local lldpmed_fast_start
+		config_get_bool lldpmed_fast_start 'config' 'lldpmed_fast_start' 0
+
+		local lldpmed_fast_start_tx_interval
+		config_get lldpmed_fast_start_tx_interval 'config' 'lldpmed_fast_start_tx_interval' 0
+	fi
+
+	local lldp_agenttype
+	config_get lldp_agenttype 'config' 'lldp_agenttype' 'nearest-bridge'
+
+	local lldp_portidsubtype
+	config_get lldp_portidsubtype 'config' 'lldp_portidsubtype' 'macaddress'
+
+	local lldp_platform
+	config_get lldp_platform 'config' 'lldp_platform' ""
+
+	local lldp_tx_interval
+	config_get lldp_tx_interval 'config' 'lldp_tx_interval' 0
+
+	local lldp_tx_hold
+	config_get lldp_tx_hold 'config' 'lldp_tx_hold' 0
+
 	# Clear out the config file first
 	echo -n > "$LLDPD_CONF"
 	[ -n "$ifnames" ] && echo "configure system interface pattern" "$ifnames" >> "$LLDPD_CONF"
@@ -55,60 +145,194 @@ write_lldpd_conf()
 	[ -n "$lldp_hostname" ] && echo "configure system hostname" "\"$lldp_hostname\"" >> "$LLDPD_CONF"
 	[ -n "$lldp_mgmt_ip" ] && echo "configure system ip management pattern" "\"$lldp_mgmt_ip\"" >> "$LLDPD_CONF"
 	[ -n "$lldp_syscapabilities" ] && echo "configure system capabilities enabled" "\"$lldp_syscapabilities\"" >> "$LLDPD_CONF"
+	if [ "$CONFIG_LLDPD_WITH_LLDPMED" == "y" ] && [ $lldpmed_fast_start -gt 0 ]; then
+		if [ $lldpmed_fast_start_tx_interval -gt 0 ]; then
+			echo "configure med fast-start tx-interval" "\"$lldpmed_fast_start_tx_interval\"" >> "$LLDPD_CONF"
+		else
+			echo "configure med fast-start" "enable" >> "$LLDPD_CONF"
+		fi
+	fi
+	[ -n "$lldp_agenttype" ] && echo "configure lldp agent-type" "\"$lldp_agenttype\"" >> "$LLDPD_CONF"
+	[ -n "$lldp_portidsubtype" ] && echo "configure lldp portidsubtype" "\"$lldp_portidsubtype\"" >> "$LLDPD_CONF"
+	[ -n "$lldp_platform" ] && echo "configure system platform" "\"$lldp_platform\"" >> "$LLDPD_CONF"
+	[ $lldp_tx_interval -gt 0 ] && echo "configure lldp tx-interval" "$lldp_tx_interval" >> "$LLDPD_CONF"
+	[ $lldp_tx_hold -gt 0 ] && echo "configure lldp tx-hold" "$lldp_tx_hold" >> "$LLDPD_CONF"
 
 	# Since lldpd's sysconfdir is /tmp, we'll symlink /etc/lldpd.d to /tmp/$LLDPD_CONFS_DIR
 	[ -e $LLDPD_CONFS_DIR ] || ln -s /etc/lldpd.d $LLDPD_CONFS_DIR
 }
 
-service_triggers() {
-	procd_add_reload_trigger "lldpd"
-}
-
 start_service() {
 
+	local enable_lldp
+	local force_lldp
 	local enable_cdp
+	local cdp_version
+	local force_cdp
+	local force_cdpv2
 	local enable_fdp
+	local force_fdp
 	local enable_sonmp
+	local force_sonmp
 	local enable_edp
+	local force_edp
 	local lldp_class
 	local lldp_location
+	local lldp_no_version
+	local lldpmed_no_inventory
 	local readonly_mode
 	local agentxsocket
+	local filter
 
 	config_load 'lldpd'
-	config_get_bool enable_cdp 'config' 'enable_cdp' 0
-	config_get_bool enable_fdp 'config' 'enable_fdp' 0
-	config_get_bool enable_sonmp 'config' 'enable_sonmp' 0
-	config_get_bool enable_edp 'config' 'enable_edp' 0
+	config_get_bool enable_lldp 'config' 'enable_lldp' 1
+	config_get_bool force_lldp 'config' 'force_lldp' 0
+	if [ "$CONFIG_LLDPD_WITH_CDP" == "y" ]; then
+		config_get_bool enable_cdp 'config' 'enable_cdp' 0
+		config_get cdp_version 'config' 'cdp_version' 'cdpv1v2'
+		config_get_bool force_cdp 'config' 'force_cdp' 0
+		config_get_bool force_cdpv2 'config' 'force_cdpv2' 0
+	fi
+	if [ "$CONFIG_LLDPD_WITH_FDP" == "y" ]; then
+		config_get_bool enable_fdp 'config' 'enable_fdp' 0
+		config_get_bool force_fdp 'config' 'force_fdp' 0
+	fi
+	if [ "$CONFIG_LLDPD_WITH_SONMP" == "y" ]; then
+		config_get_bool enable_sonmp 'config' 'enable_sonmp' 0
+		config_get_bool force_sonmp 'config' 'force_sonmp' 0
+	fi
+	if [ "$CONFIG_LLDPD_WITH_EDP" == "y" ]; then
+		config_get_bool enable_edp 'config' 'enable_edp' 0
+		config_get_bool force_edp 'config' 'force_edp' 0
+	fi
 	config_get lldp_class 'config' 'lldp_class'
 	config_get lldp_location 'config' 'lldp_location'
+	config_get_bool lldp_no_version 'config' 'lldp_no_version' 0
+	if [ "$CONFIG_LLDPD_WITH_LLDPMED" == "y" ]; then
+		config_get_bool lldpmed_no_inventory 'config' 'lldpmed_no_inventory' 0
+	fi
 	config_get_bool readonly_mode 'config' 'readonly_mode' 0
-	config_get agentxsocket 'config' 'agentxsocket'
+	if [ "$CONFIG_LLDPD_WITH_SNMP" == "y" ]; then
+		config_get agentxsocket 'config' 'agentxsocket'
+	fi
+	config_get filter 'config' 'filter' 15
 
-	mkdir -p /var/run/lldp
-	chown lldp:lldp /var/run/lldp
+	mkdir -p ${LLDPD_RUN}
+	chown lldp:lldp ${LLDPD_RUN}
 
 	# When lldpd starts, it also loads up what we write in this config file
 	write_lldpd_conf
 
 	procd_open_instance
-	procd_set_param command /usr/sbin/lldpd -d
+	procd_set_param command ${LLDPDBIN}
+	procd_append_param command -d
+
+	if [ $enable_lldp -gt 0 ]; then
+		if [ $force_lldp -gt 0 ]; then
+			procd_append_param command '-l'
+		fi
+	else
+		# Disable LLDP
+		procd_append_param command '-ll'
+	fi
+
+	if [ "$CONFIG_LLDPD_WITH_CDP" == "y" ] && [ $enable_cdp -gt 0 ]; then
+		if [ $cdp_version == "cdpv2" ]; then
+			if [ $force_cdp -gt 0 ]; then
+				# CDPv1 disabled, CDPv2 forced
+				procd_append_param command '-ccccc'
+			else
+				# CDPv1 disabled, CDPv2 enabled
+				procd_append_param command '-cccc'
+			fi
+		elif [ $cdp_version == "cdpv1v2" ]; then
+			if [ $force_cdp -gt 0 ] && [ $force_cdpv2 -gt 0 ]; then
+				# CDPv1 enabled, CDPv2 forced
+				procd_append_param command '-ccc'
+			elif [ $force_cdp -gt 0 ]; then
+				# CDPv1 forced, CDPv2 enabled
+				procd_append_param command '-cc'
+			else
+				# CDPv1 and CDPv2 enabled
+				procd_append_param command '-c'
+			fi
+		fi
+	fi
+
+	if [ "$CONFIG_LLDPD_WITH_FDP" == "y" ] && [ $enable_fdp -gt 0 ]; then
+		if [ $force_fdp -gt 0 ]; then
+			# FDP enbled and forced
+			procd_append_param command '-ff'
+		else
+			# FDP enabled
+			procd_append_param command '-f'
+		fi
+	fi
+
+	if [ "$CONFIG_LLDPD_WITH_SONMP" == "y" ] && [ $enable_sonmp -gt 0 ]; then
+		if [ $force_sonmp -gt 0 ]; then
+			# SONMP enabled and forced
+			procd_append_param command '-ss'
+		else
+			# SONMP enabled
+			procd_append_param command '-s'
+		fi
+	fi
+
+	if [ "$CONFIG_LLDPD_WITH_EDP" == "y" ] && [ $enable_edp -gt 0 ]; then
+		if [ $force_edp -gt 0 ]; then
+			# EDP enbled and forced
+			procd_append_param command '-ee'
+		else
+			# EDP enbled
+			procd_append_param command '-e'
+		fi
+	fi
 
-	[ $enable_cdp -gt 0 ] && procd_append_param command '-c'
-	[ $enable_fdp -gt 0 ] && procd_append_param command '-f'
-	[ $enable_sonmp -gt 0 ] && procd_append_param command '-s'
-	[ $enable_edp -gt 0 ] && procd_append_param command '-e'
 	[ $readonly_mode -gt 0 ] && procd_append_param command '-r'
+	[ $lldp_no_version -gt 0 ] && procd_append_param commanpackage/network/services/lldpd/Makefile package/network/services/lldpd/files/lldpd.initd '-k'
+	[ "$CONFIG_LLDPD_WITH_LLDPMED" == "y" ] && [ $lldpmed_no_inventory -gt 0 ] && procd_append_param command '-i'
 	[ -n "$lldp_class" ] && procd_append_param command -M "$lldp_class"
-	[ -n "$agentxsocket" ] && procd_append_param command -x -X "$agentxsocket"
+	[ "$CONFIG_LLDPD_WITH_SNMP" == "y" ] && [ -n "$agentxsocket" ] && procd_append_param command -x -X "$agentxsocket"
+	[ -n "$filter" ] && procd_append_param command -H "$filter"
+
+    # ChassisID interfaces
+	local ifnames
+	get_config_cid_ifaces ifnames
+	[ -n "$ifnames" ] && procd_append_param command -C "$ifnames"
+
+    # Overwrite default configuration locations processed by lldpcli at start
+	procd_append_param command -O "$LLDPD_CONF"
+
+	local restart_hash
+	get_config_restart_hash restart_hash
+	echo -n "$restart_hash" > $LLDPD_RESTART_HASH
 
 	# set auto respawn behavior
 	procd_set_param respawn
 	procd_close_instance
 }
 
+service_triggers() {
+	procd_add_config_trigger "config.change" "lldpd" /etc/init.d/lldpd reload
+}
+
 reload_service() {
 	running || return 1
+	
+	local running_hash=""
+	local config_hash=""
+
+	get_config_restart_hash config_hash
+	if [ -f ${LLDPD_RESTART_HASH} ]; then running_hash=`cat $LLDPD_RESTART_HASH`; fi
+
+	if [ "x$running_hash" != "x$config_hash" ]; then
+		# Restart LLDPd
+		# Some parameters can't be configured at runtime
+		restart
+		return 0
+	fi
+
 	$LLDPCLI -u $LLDPSOCKET &> /dev/null <<-EOF
 		pause
 		unconfigure lldp custom-tlv
@@ -116,7 +340,14 @@ reload_service() {
 		unconfigure system description
 		unconfigure system hostname
 		unconfigure system ip management pattern
+		unconfigure system platform
 	EOF
+	if [ "$CONFIG_LLDPD_WITH_LLDPMED" == "y" ]; then
+		$LLDPCLI -u $LLDPSOCKET &> /dev/null <<-EOF
+			unconfigure med fast-start
+		EOF
+
+	fi
 	# Rewrite lldpd.conf
 	# If something changed it should be included by the lldpcli call
 	write_lldpd_conf
@@ -130,5 +361,6 @@ reload_service() {
 }
 
 stop_service() {
-	rm -rf /var/run/lldp $LLDPSOCKET
+	rm -rf ${LLDPD_RUN} $LLDPSOCKET 2>/dev/null
 }
+
diff --git a/package/network/services/uhttpd/Makefile b/package/network/services/uhttpd/Makefile
index 37117bf91192f4..2a6ad535b41420 100644
--- a/package/network/services/uhttpd/Makefile
+++ b/package/network/services/uhttpd/Makefile
@@ -8,7 +8,7 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=uhttpd
-PKG_RELEASE:=2
+PKG_RELEASE:=3
 
 PKG_SOURCE_PROTO:=git
 PKG_SOURCE_URL=$(PROJECT_GIT)/project/uhttpd.git
diff --git a/package/network/services/uhttpd/files/uhttpd.init b/package/network/services/uhttpd/files/uhttpd.init
index bfde231bf62f70..c4d0025d699e69 100755
--- a/package/network/services/uhttpd/files/uhttpd.init
+++ b/package/network/services/uhttpd/files/uhttpd.init
@@ -219,10 +219,76 @@ start_instance()
 	procd_close_instance
 }
 
+uhttpd_interfaces()
+{
+	local cfg="$1"
+	local http https listen ips
+
+	config_get http "$cfg" listen_http
+	config_get https "$cfg" listen_https
+	for listen in $http $https; do
+		case "$listen" in
+		"" |\
+		"0.0.0.0:"* |\
+		"[::]:"* )
+			continue
+			;;
+		*.*.*.*:*)
+			ips="$ips ${listen%%:*}
+"
+			;;
+		\[*\]:* )
+			listen="${listen:1}"
+			ips="$ips ${listen%%]:*}
+"
+			;;
+		esac
+	done
+	ips="$( echo "$ips" | sort -u )"
+	echo "$ips"
+}
+
+resolve_iface()
+{
+	local cfg="$1"
+	local ipaddr ipaddrs testip="$2"
+
+	config_get ipaddrs "$cfg" ipaddr
+	for ipaddr in $ipaddrs; do
+		[ "$ipaddr" = "$testip" ] && echo "$cfg"
+	done
+}
+
+get_interface_by_ip()
+{
+	config_load network
+	config_foreach resolve_iface interface "$@"
+}
+
 service_triggers()
 {
+	local iface ifaces all=0
+
 	procd_add_reload_trigger "uhttpd"
 	procd_add_raw_trigger acme.renew 5000 /etc/init.d/uhttpd reload
+
+	config_load uhttpd
+	ips="$(config_foreach uhttpd_interfaces uhttpd)"
+	[ -z "$ips" ] && return 0
+
+	for ip in $ips; do
+		iface="$(get_interface_by_ip $ip)"
+		[ -z "$iface" ] && all=1
+		ifaces="$ifaces $iface"
+	done
+
+	if [ "$all" = "1" ]; then
+		procd_add_raw_trigger "interface.*.up" 1000 /etc/init.d/uhttpd start
+	else
+		for iface in $ifaces; do
+			procd_add_raw_trigger "interface.$iface.up" 1000 /etc/init.d/uhttpd start
+		done
+	fi
 }
 
 start_service() {
diff --git a/package/network/services/umdns/files/umdns.init b/package/network/services/umdns/files/umdns.init
index 1ae1cccb039ca3..7f25595f2493aa 100644
--- a/package/network/services/umdns/files/umdns.init
+++ b/package/network/services/umdns/files/umdns.init
@@ -8,7 +8,7 @@ PROG=/usr/sbin/umdns
 IFACES=""
 
 load_ifaces() {
-	local network="$(uci get umdns.@umdns[-1].network)"
+	local network="$(uci -q get umdns.@umdns[-1].network)"
 	for n in $network; do
 		local device
 		json_load "$(ifstatus $n)"
@@ -29,7 +29,7 @@ reload_service() {
 }
 
 start_service() {
-	local network="$(uci get umdns.@umdns[-1].network)"
+	local network="$(uci -q get umdns.@umdns[-1].network)"
 
 	procd_open_instance
 	procd_set_param command "$PROG"
@@ -42,7 +42,7 @@ start_service() {
 	done
 	procd_add_raw_trigger "instance.update" 5000 "/bin/ubus" "call" "umdns" "reload"
 	procd_close_trigger
-	[ "$(uci get umdns.@umdns[-1].jail)" = 1 ] && procd_add_jail umdns ubus log
+	[ "$(uci -q get umdns.@umdns[-1].jail)" = 1 ] && procd_add_jail umdns ubus log
 	procd_close_instance
 }
 
diff --git a/package/system/ca-certificates/Makefile b/package/system/ca-certificates/Makefile
index ec588cc65b6c6b..06418cebfa6d27 100644
--- a/package/system/ca-certificates/Makefile
+++ b/package/system/ca-certificates/Makefile
@@ -7,13 +7,13 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=ca-certificates
-PKG_VERSION:=20230311
+PKG_VERSION:=20240203
 PKG_RELEASE:=1
 PKG_MAINTAINER:=
 
 PKG_SOURCE:=$(PKG_NAME)_$(PKG_VERSION).tar.xz
 PKG_SOURCE_URL:=@DEBIAN/pool/main/c/ca-certificates
-PKG_HASH:=83de934afa186e279d1ed08ea0d73f5cf43a6fbfb5f00874b6db3711c64576f3
+PKG_HASH:=3286d3fc42c4d11b7086711a85f865b44065ce05cf1fb5376b2abed07622a9c6
 PKG_INSTALL:=1
 
 include $(INCLUDE_DIR)/package.mk
diff --git a/package/system/procd/Makefile b/package/system/procd/Makefile
index 0af90c7d4ade35..5cbc44f0c060cd 100644
--- a/package/system/procd/Makefile
+++ b/package/system/procd/Makefile
@@ -12,9 +12,9 @@ PKG_RELEASE:=1
 
 PKG_SOURCE_PROTO:=git
 PKG_SOURCE_URL=$(PROJECT_GIT)/project/procd.git
-PKG_MIRROR_HASH:=48e5d555b5beb15cf936e1d2433b8e614de64a4eaf25293f0211eeb9ac79d534
-PKG_SOURCE_DATE:=2023-11-28
-PKG_SOURCE_VERSION:=7e6c6efd6fbcc7955801c5e2ac915a90697e1fd9
+PKG_MIRROR_HASH:=fc7ea415ebb1946661c1204a16b2a2b129014d39521da5883524e5ced8c3c9b4
+PKG_SOURCE_DATE:=2024-02-24
+PKG_SOURCE_VERSION:=1901aba90b6841ec1a99a25224a92d2519c603fd
 CMAKE_INSTALL:=1
 
 PKG_LICENSE:=GPL-2.0
diff --git a/package/system/rpcd/Makefile b/package/system/rpcd/Makefile
index 977932f9d1cf22..ef360a2c12b2c3 100644
--- a/package/system/rpcd/Makefile
+++ b/package/system/rpcd/Makefile
@@ -12,9 +12,9 @@ PKG_RELEASE:=1
 
 PKG_SOURCE_PROTO:=git
 PKG_SOURCE_URL=$(PROJECT_GIT)/project/rpcd.git
-PKG_MIRROR_HASH:=76467ff072b50190f93d071b7792ade7c717674397a2547e995a8f819a48954e
-PKG_SOURCE_DATE:=2023-07-01
-PKG_SOURCE_VERSION:=c07ab2f91061ad64209e9aaa1fb1b77061a1af25
+PKG_MIRROR_HASH:=cf77c8aca75f893315620e2e3abf7fa02d8c8a21f54808b238973e43c66d0059
+PKG_SOURCE_DATE:=2024-02-22
+PKG_SOURCE_VERSION:=8ef4c2587ac0041049c67befed281a70cf240769
 PKG_MAINTAINER:=Jo-Philipp Wich <jo@mein.io>
 
 PKG_LICENSE:=ISC
diff --git a/package/utils/e2fsprogs/Makefile b/package/utils/e2fsprogs/Makefile
index 2657077a16be29..9e2f2fafe55345 100644
--- a/package/utils/e2fsprogs/Makefile
+++ b/package/utils/e2fsprogs/Makefile
@@ -34,7 +34,7 @@ define Package/e2fsprogs
   SUBMENU:=Filesystem
   TITLE:=Ext2/3/4 filesystem utilities
   URL:=http://e2fsprogs.sourceforge.net/
-  DEPENDS:=+libuuid +libext2fs
+  DEPENDS:=+libuuid +libext2fs +libe2p
 endef
 
 define Package/e2fsprogs/description
@@ -55,6 +55,20 @@ define Package/libext2fs/description
  libext2fs is a library which can access ext2, ext3 and ext4 filesystems.
 endef
 
+define Package/libe2p
+  SECTION:=libs
+  CATEGORY:=Libraries
+  TITLE:=ext2fs userspace programs utility library
+  URL:=http://e2fsprogs.sourceforge.net/
+  DEPENDS:=+libuuid
+  ABI_VERSION:=2
+endef
+
+define Package/libe2p/description
+ This package contains libe2p, ext2fs userspace programs utility library
+ bundled with e2fsprogs.
+endef
+
 define Package/libss
   SECTION:=libs
   CATEGORY:=Libraries
@@ -184,13 +198,17 @@ endef
 
 define Build/InstallDev
 	$(INSTALL_DIR) $(1)/usr/lib/pkgconfig
+
 	$(CP) $(PKG_BUILD_DIR)/lib/ext2fs/ext2fs.pc $(1)/usr/lib/pkgconfig
 	$(CP) $(PKG_BUILD_DIR)/lib/et/com_err.pc $(1)/usr/lib/pkgconfig
+	$(CP) $(PKG_BUILD_DIR)/lib/e2p/e2p.pc $(1)/usr/lib/pkgconfig
+	$(CP) $(PKG_BUILD_DIR)/lib/ss/ss.pc $(1)/usr/lib/pkgconfig
 
 	$(INSTALL_DIR) $(1)/usr/lib
 	$(CP) $(PKG_BUILD_DIR)/lib/libext2fs.{so,a}* $(1)/usr/lib
 	$(CP) $(PKG_BUILD_DIR)/lib/libcom_err.{so,a}* $(1)/usr/lib
 	$(CP) $(PKG_BUILD_DIR)/lib/libss.{so,a}* $(1)/usr/lib
+	$(CP) $(PKG_BUILD_DIR)/lib/libe2p.{so,a}* $(1)/usr/lib
 
 	$(INSTALL_DIR) $(1)/usr/include/ext2fs
 	$(CP) $(PKG_BUILD_DIR)/lib/ext2fs/*.h $(1)/usr/include/ext2fs
@@ -203,6 +221,8 @@ define Build/InstallDev
 		$(PKG_BUILD_DIR)/lib/ss/ss.h \
 		$(PKG_BUILD_DIR)/lib/ss/ss_err.h \
 		$(1)/usr/include/ss/
+	$(INSTALL_DIR) $(1)/usr/include/e2p
+	$(CP) $(PKG_BUILD_DIR)/lib/e2p/e2p.h $(1)/usr/include/e2p
 endef
 
 define Host/Compile
@@ -237,13 +257,17 @@ define Package/e2fsprogs/install
 	$(LN) e2fsck $(1)/usr/sbin/fsck.ext3
 	$(LN) e2fsck $(1)/usr/sbin/fsck.ext4
 	$(INSTALL_DIR) $(1)/usr/lib
-	$(CP) $(PKG_INSTALL_DIR)/usr/lib/libe2p.so.* $(1)/usr/lib/
 	$(INSTALL_DIR) $(1)/etc/init.d
 	$(INSTALL_DIR) $(1)/lib/functions/fsck
 	$(INSTALL_DATA) ./files/e2fsck.sh $(1)/lib/functions/fsck/
 	$(INSTALL_DATA) ./files/e2fsck.conf $(1)/etc/e2fsck.conf
 endef
 
+define Package/libe2p/install
+	$(INSTALL_DIR) $(1)/usr/lib
+	$(CP) $(PKG_INSTALL_DIR)/usr/lib/libe2p.so.* $(1)/usr/lib/
+endef
+
 define Package/libcomerr/install
 	$(INSTALL_DIR) $(1)/usr/lib
 	$(CP) $(PKG_INSTALL_DIR)/usr/lib/libcom_err.so.* $(1)/usr/lib/
@@ -318,6 +342,7 @@ endef
 $(eval $(call BuildPackage,libcomerr))
 $(eval $(call BuildPackage,libss))
 $(eval $(call BuildPackage,libext2fs))
+$(eval $(call BuildPackage,libe2p))
 $(eval $(call BuildPackage,e2fsprogs))
 $(eval $(call BuildPackage,tune2fs))
 $(eval $(call BuildPackage,resize2fs))
diff --git a/package/utils/fitblk/Makefile b/package/utils/fitblk/Makefile
new file mode 100644
index 00000000000000..cb9e7ebb400ab6
--- /dev/null
+++ b/package/utils/fitblk/Makefile
@@ -0,0 +1,41 @@
+include $(TOPDIR)/rules.mk
+
+PKG_NAME:=fitblk
+PKG_RELEASE:=1
+PKG_LICENSE:=GPL-2.0-only
+PKG_MAINTAINER:=Daniel Golle <daniel@makrotopia.org>
+
+PKG_BUILD_DIR := $(BUILD_DIR)/$(PKG_NAME)
+
+PKG_FLAGS:=nonshared
+
+include $(INCLUDE_DIR)/package.mk
+
+define Package/fitblk
+  HIDDEN:=1
+  SECTION:=base
+  CATEGORY:=Base system
+  TITLE:=fitblk firmware release tool
+  DEPENDS:=@LINUX_6_1
+endef
+
+define Package/fitblk/description
+Release uImage.FIT block devices using ioctl.
+endef
+
+define Build/Configure
+endef
+
+define Build/Compile
+	$(MAKE) -C $(PKG_BUILD_DIR) \
+		CC="$(TARGET_CC)" \
+		CFLAGS="$(TARGET_CFLAGS) -Wall -Werror" \
+		LDFLAGS="$(TARGET_LDFLAGS)"
+endef
+
+define Package/fitblk/install
+	$(INSTALL_DIR) $(1)/usr/sbin
+	$(INSTALL_BIN) $(PKG_BUILD_DIR)/fitblk $(1)/usr/sbin/
+endef
+
+$(eval $(call BuildPackage,fitblk))
diff --git a/package/utils/fitblk/src/Makefile b/package/utils/fitblk/src/Makefile
new file mode 100644
index 00000000000000..064764c17d28c1
--- /dev/null
+++ b/package/utils/fitblk/src/Makefile
@@ -0,0 +1,7 @@
+all: fitblk
+
+fitblk:
+	$(CC) $(CFLAGS) -o $@ fitblk.c $(LDFLAGS)
+
+clean:
+	rm -f fitblk
diff --git a/package/utils/fitblk/src/fitblk.c b/package/utils/fitblk/src/fitblk.c
new file mode 100644
index 00000000000000..059ba6098cea79
--- /dev/null
+++ b/package/utils/fitblk/src/fitblk.c
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include <stdio.h>
+#include <errno.h>
+#include <fcntl.h>
+#include <string.h>
+#include <unistd.h>
+#include <sys/ioctl.h>
+#include <linux/fitblk.h>
+
+static int fitblk_release(char *device)
+{
+	int fd, ret;
+
+	fd = open(device, O_RDONLY);
+	if (fd == -1)
+		return errno;
+
+	ret = ioctl(fd, FITBLK_RELEASE, NULL);
+	close(fd);
+
+	if (ret == -1)
+		return errno;
+
+	return 0;
+}
+
+int main(int argc, char *argp[])
+{
+	int ret;
+
+	if (argc != 2) {
+		fprintf(stderr, "Release uImage.FIT sub-image block device\n");
+		fprintf(stderr, "Syntax: %s /dev/fitXXX\n", argp[0]);
+		return -EINVAL;
+	}
+
+	ret = fitblk_release(argp[1]);
+	if (ret)
+		fprintf(stderr, "fitblk: error releasing %s: %s\n", argp[1],
+			strerror(ret));
+	else
+		fprintf(stderr, "fitblk: %s released\n", argp[1]);
+
+	return ret;
+}
diff --git a/package/utils/lua/Makefile b/package/utils/lua/Makefile
index 46e7bb0dcdb6c3..36d332f1c762b0 100644
--- a/package/utils/lua/Makefile
+++ b/package/utils/lua/Makefile
@@ -9,7 +9,7 @@ include $(TOPDIR)/rules.mk
 
 PKG_NAME:=lua
 PKG_VERSION:=5.1.5
-PKG_RELEASE:=10
+PKG_RELEASE:=11
 
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
 PKG_SOURCE_URL:=https://www.lua.org/ftp/ \
diff --git a/package/utils/lua/patches-host/001-include-version-number.patch b/package/utils/lua/patches-host/001-include-version-number.patch
index f769e607367fb0..806d37003edc5f 100644
--- a/package/utils/lua/patches-host/001-include-version-number.patch
+++ b/package/utils/lua/patches-host/001-include-version-number.patch
@@ -8,7 +8,6 @@ Including it allows multiple lua versions to coexist.
 Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
 ---
 
-diff --git a/Makefile b/Makefile
 --- a/Makefile
 +++ b/Makefile
 @@ -41,10 +41,10 @@ RANLIB= ranlib
@@ -42,7 +41,7 @@ rename to doc/luac5.1.1
 diff --git a/src/Makefile b/src/Makefile
 --- a/src/Makefile
 +++ b/src/Makefile
-@@ -29,10 +29,10 @@ CORE_O=	lapi.o lcode.o ldebug.o ldo.o ldump.o lfunc.o lgc.o llex.o lmem.o \
+@@ -29,10 +29,10 @@ CORE_O=	lapi.o lcode.o ldebug.o ldo.o ld
  LIB_O=	lauxlib.o lbaselib.o ldblib.o liolib.o lmathlib.o loslib.o ltablib.o \
  	lstrlib.o loadlib.o linit.o
  
diff --git a/package/utils/lua/patches-host/013-lnum-strtoul-parsing-fixes.patch b/package/utils/lua/patches-host/013-lnum-strtoul-parsing-fixes.patch
index 7f00c8c3a2dfe4..8887229589d908 100644
--- a/package/utils/lua/patches-host/013-lnum-strtoul-parsing-fixes.patch
+++ b/package/utils/lua/patches-host/013-lnum-strtoul-parsing-fixes.patch
@@ -1,8 +1,6 @@
-diff --git a/src/lnum.c b/src/lnum.c
-index 1456b6a2ed23..b0632b04c2b7 100644
 --- a/src/lnum.c
 +++ b/src/lnum.c
-@@ -127,6 +127,8 @@ static int luaO_str2i (const char *s, lua_Integer *res, char **endptr_ref) {
+@@ -127,6 +127,8 @@ static int luaO_str2i (const char *s, lu
  #else
        return 0;  /* Reject the number */
  #endif
@@ -11,7 +9,7 @@ index 1456b6a2ed23..b0632b04c2b7 100644
      }
    } else if ((v > LUA_INTEGER_MAX) || (*endptr && (!isspace(*endptr)))) {
      return TK_NUMBER;	/* not in signed range, or has '.', 'e' etc. trailing */
-@@ -310,3 +312,13 @@ int try_unmint( lua_Integer *r, lua_Integer ib ) {
+@@ -310,3 +312,13 @@ int try_unmint( lua_Integer *r, lua_Inte
    return 0;
  }
  
@@ -25,8 +23,6 @@ index 1456b6a2ed23..b0632b04c2b7 100644
 +  return (unsigned LUA_INTEGER)v;
 +}
 +#endif
-diff --git a/src/lnum_config.h b/src/lnum_config.h
-index 19d7a4231a49..1092eead6629 100644
 --- a/src/lnum_config.h
 +++ b/src/lnum_config.h
 @@ -141,7 +141,12 @@
@@ -43,6 +39,3 @@ index 19d7a4231a49..1092eead6629 100644
  #endif
  #ifndef LUA_INTEGER_MIN
  # define LUA_INTEGER_MIN (-LUA_INTEGER_MAX -1)  /* -2^16|32 */
--- 
-1.9.1
-
diff --git a/package/utils/lua/patches-host/100-no_readline.patch b/package/utils/lua/patches-host/100-no_readline.patch
index 209c302bb7231b..700114e43cd113 100644
--- a/package/utils/lua/patches-host/100-no_readline.patch
+++ b/package/utils/lua/patches-host/100-no_readline.patch
@@ -10,7 +10,7 @@
  #if defined(LUA_USE_MACOSX)
 --- a/src/Makefile
 +++ b/src/Makefile
-@@ -17,6 +17,7 @@
+@@ -17,6 +17,7 @@ LIBS= -lm $(MYLIBS)
  MYCFLAGS=
  MYLDFLAGS=
  MYLIBS=
@@ -18,7 +18,7 @@
  
  # == END OF USER SETTINGS. NO NEED TO CHANGE ANYTHING BELOW THIS LINE =========
  
-@@ -75,7 +76,7 @@
+@@ -75,7 +76,7 @@ echo:
  	@echo "MYLIBS = $(MYLIBS)"
  
  # convenience targets for popular platforms
@@ -27,7 +27,7 @@
  none:
  	@echo "Please choose a platform:"
  	@echo "   $(PLATS)"
-@@ -90,16 +91,16 @@
+@@ -90,16 +91,16 @@ bsd:
  	$(MAKE) all MYCFLAGS="-DLUA_USE_POSIX -DLUA_USE_DLOPEN" MYLIBS="-Wl,-E"
  
  freebsd:
diff --git a/package/utils/lua/patches-host/400-CVE-2014-5461.patch b/package/utils/lua/patches-host/400-CVE-2014-5461.patch
new file mode 100644
index 00000000000000..cce73ff96bdc36
--- /dev/null
+++ b/package/utils/lua/patches-host/400-CVE-2014-5461.patch
@@ -0,0 +1,19 @@
+From: Enrico Tassi <gareuselesinge@debian.org>
+Date: Tue, 26 Aug 2014 16:20:55 +0200
+Subject: Fix stack overflow in vararg functions
+
+---
+ src/ldo.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/src/ldo.c
++++ b/src/ldo.c
+@@ -274,7 +274,7 @@ int luaD_precall (lua_State *L, StkId fu
+     CallInfo *ci;
+     StkId st, base;
+     Proto *p = cl->p;
+-    luaD_checkstack(L, p->maxstacksize);
++    luaD_checkstack(L, p->maxstacksize + p->numparams);
+     func = restorestack(L, funcr);
+     if (!p->is_vararg) {  /* no varargs? */
+       base = func + 1;
diff --git a/package/utils/lua/patches/001-include-version-number.patch b/package/utils/lua/patches/001-include-version-number.patch
index f769e607367fb0..806d37003edc5f 100644
--- a/package/utils/lua/patches/001-include-version-number.patch
+++ b/package/utils/lua/patches/001-include-version-number.patch
@@ -8,7 +8,6 @@ Including it allows multiple lua versions to coexist.
 Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
 ---
 
-diff --git a/Makefile b/Makefile
 --- a/Makefile
 +++ b/Makefile
 @@ -41,10 +41,10 @@ RANLIB= ranlib
@@ -42,7 +41,7 @@ rename to doc/luac5.1.1
 diff --git a/src/Makefile b/src/Makefile
 --- a/src/Makefile
 +++ b/src/Makefile
-@@ -29,10 +29,10 @@ CORE_O=	lapi.o lcode.o ldebug.o ldo.o ldump.o lfunc.o lgc.o llex.o lmem.o \
+@@ -29,10 +29,10 @@ CORE_O=	lapi.o lcode.o ldebug.o ldo.o ld
  LIB_O=	lauxlib.o lbaselib.o ldblib.o liolib.o lmathlib.o loslib.o ltablib.o \
  	lstrlib.o loadlib.o linit.o
  
diff --git a/package/utils/lua/patches/013-lnum-strtoul-parsing-fixes.patch b/package/utils/lua/patches/013-lnum-strtoul-parsing-fixes.patch
index 7f00c8c3a2dfe4..8887229589d908 100644
--- a/package/utils/lua/patches/013-lnum-strtoul-parsing-fixes.patch
+++ b/package/utils/lua/patches/013-lnum-strtoul-parsing-fixes.patch
@@ -1,8 +1,6 @@
-diff --git a/src/lnum.c b/src/lnum.c
-index 1456b6a2ed23..b0632b04c2b7 100644
 --- a/src/lnum.c
 +++ b/src/lnum.c
-@@ -127,6 +127,8 @@ static int luaO_str2i (const char *s, lua_Integer *res, char **endptr_ref) {
+@@ -127,6 +127,8 @@ static int luaO_str2i (const char *s, lu
  #else
        return 0;  /* Reject the number */
  #endif
@@ -11,7 +9,7 @@ index 1456b6a2ed23..b0632b04c2b7 100644
      }
    } else if ((v > LUA_INTEGER_MAX) || (*endptr && (!isspace(*endptr)))) {
      return TK_NUMBER;	/* not in signed range, or has '.', 'e' etc. trailing */
-@@ -310,3 +312,13 @@ int try_unmint( lua_Integer *r, lua_Integer ib ) {
+@@ -310,3 +312,13 @@ int try_unmint( lua_Integer *r, lua_Inte
    return 0;
  }
  
@@ -25,8 +23,6 @@ index 1456b6a2ed23..b0632b04c2b7 100644
 +  return (unsigned LUA_INTEGER)v;
 +}
 +#endif
-diff --git a/src/lnum_config.h b/src/lnum_config.h
-index 19d7a4231a49..1092eead6629 100644
 --- a/src/lnum_config.h
 +++ b/src/lnum_config.h
 @@ -141,7 +141,12 @@
@@ -43,6 +39,3 @@ index 19d7a4231a49..1092eead6629 100644
  #endif
  #ifndef LUA_INTEGER_MIN
  # define LUA_INTEGER_MIN (-LUA_INTEGER_MAX -1)  /* -2^16|32 */
--- 
-1.9.1
-
diff --git a/package/utils/lua/patches/400-CVE-2014-5461.patch b/package/utils/lua/patches/400-CVE-2014-5461.patch
new file mode 100644
index 00000000000000..cce73ff96bdc36
--- /dev/null
+++ b/package/utils/lua/patches/400-CVE-2014-5461.patch
@@ -0,0 +1,19 @@
+From: Enrico Tassi <gareuselesinge@debian.org>
+Date: Tue, 26 Aug 2014 16:20:55 +0200
+Subject: Fix stack overflow in vararg functions
+
+---
+ src/ldo.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/src/ldo.c
++++ b/src/ldo.c
+@@ -274,7 +274,7 @@ int luaD_precall (lua_State *L, StkId fu
+     CallInfo *ci;
+     StkId st, base;
+     Proto *p = cl->p;
+-    luaD_checkstack(L, p->maxstacksize);
++    luaD_checkstack(L, p->maxstacksize + p->numparams);
+     func = restorestack(L, funcr);
+     if (!p->is_vararg) {  /* no varargs? */
+       base = func + 1;
diff --git a/package/utils/lua5.3/Makefile b/package/utils/lua5.3/Makefile
index 0a295040f2337a..405fa901455fe6 100644
--- a/package/utils/lua5.3/Makefile
+++ b/package/utils/lua5.3/Makefile
@@ -9,7 +9,7 @@ include $(TOPDIR)/rules.mk
 
 PKG_NAME:=lua
 PKG_VERSION:=5.3.5
-PKG_RELEASE:=5
+PKG_RELEASE:=6
 
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
 PKG_SOURCE_URL:=https://www.lua.org/ftp/ \
diff --git a/package/utils/lua5.3/patches-host/001-include-version-number.patch b/package/utils/lua5.3/patches-host/001-include-version-number.patch
index 78f00549607f98..1c9fdb250b5d90 100644
--- a/package/utils/lua5.3/patches-host/001-include-version-number.patch
+++ b/package/utils/lua5.3/patches-host/001-include-version-number.patch
@@ -8,7 +8,6 @@ Including it allows multiple lua versions to coexist.
 Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
 ---
 
-diff --git a/Makefile b/Makefile
 --- a/Makefile
 +++ b/Makefile
 @@ -12,7 +12,7 @@ PLAT= none
diff --git a/package/utils/lua5.3/patches-host/200-CVE-2019-6706.patch b/package/utils/lua5.3/patches-host/200-CVE-2019-6706.patch
new file mode 100644
index 00000000000000..8024d414cc80af
--- /dev/null
+++ b/package/utils/lua5.3/patches-host/200-CVE-2019-6706.patch
@@ -0,0 +1,51 @@
+From 89aee84cbc9224f638f3b7951b306d2ee8ecb71e Mon Sep 17 00:00:00 2001
+From: Roberto Ierusalimschy <roberto@inf.puc-rio.br>
+Date: Wed, 27 Mar 2019 14:30:12 -0300
+Subject: [PATCH] Fixed bug in 'lua_upvaluejoin'
+
+Bug-fix: joining an upvalue with itself could cause a use-after-free
+crash.
+---
+ src/lapi.c   | 12 +++++------
+ 1 file changed, 41 insertions(+), 39 deletions(-)
+
+--- a/src/lapi.c
++++ b/src/lapi.c
+@@ -1254,13 +1254,12 @@ LUA_API const char *lua_setupvalue (lua_
+ }
+ 
+ 
+-static UpVal **getupvalref (lua_State *L, int fidx, int n, LClosure **pf) {
++static UpVal **getupvalref (lua_State *L, int fidx, int n) {
+   LClosure *f;
+   StkId fi = index2addr(L, fidx);
+   api_check(L, ttisLclosure(fi), "Lua function expected");
+   f = clLvalue(fi);
+   api_check(L, (1 <= n && n <= f->p->sizeupvalues), "invalid upvalue index");
+-  if (pf) *pf = f;
+   return &f->upvals[n - 1];  /* get its upvalue pointer */
+ }
+ 
+@@ -1269,7 +1268,7 @@ LUA_API void *lua_upvalueid (lua_State *
+   StkId fi = index2addr(L, fidx);
+   switch (ttype(fi)) {
+     case LUA_TLCL: {  /* lua closure */
+-      return *getupvalref(L, fidx, n, NULL);
++      return *getupvalref(L, fidx, n);
+     }
+     case LUA_TCCL: {  /* C closure */
+       CClosure *f = clCvalue(fi);
+@@ -1286,9 +1285,10 @@ LUA_API void *lua_upvalueid (lua_State *
+ 
+ LUA_API void lua_upvaluejoin (lua_State *L, int fidx1, int n1,
+                                             int fidx2, int n2) {
+-  LClosure *f1;
+-  UpVal **up1 = getupvalref(L, fidx1, n1, &f1);
+-  UpVal **up2 = getupvalref(L, fidx2, n2, NULL);
++  UpVal **up1 = getupvalref(L, fidx1, n1);
++  UpVal **up2 = getupvalref(L, fidx2, n2);
++  if (*up1 == *up2)
++    return;
+   luaC_upvdeccount(L, *up1);
+   *up1 = *up2;
+   (*up1)->refcount++;
diff --git a/package/utils/lua5.3/patches/001-include-version-number.patch b/package/utils/lua5.3/patches/001-include-version-number.patch
index 78f00549607f98..1c9fdb250b5d90 100644
--- a/package/utils/lua5.3/patches/001-include-version-number.patch
+++ b/package/utils/lua5.3/patches/001-include-version-number.patch
@@ -8,7 +8,6 @@ Including it allows multiple lua versions to coexist.
 Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
 ---
 
-diff --git a/Makefile b/Makefile
 --- a/Makefile
 +++ b/Makefile
 @@ -12,7 +12,7 @@ PLAT= none
diff --git a/package/utils/lua5.3/patches/020-shared_liblua.patch b/package/utils/lua5.3/patches/020-shared_liblua.patch
index 7fa9652290b631..a462fa4f1e3857 100644
--- a/package/utils/lua5.3/patches/020-shared_liblua.patch
+++ b/package/utils/lua5.3/patches/020-shared_liblua.patch
@@ -1,5 +1,5 @@
---- a/Makefile	2019-07-02 09:24:57.554332875 -0600
-+++ b/Makefile	2019-07-02 09:25:42.626694604 -0600
+--- a/Makefile
++++ b/Makefile
 @@ -41,7 +41,7 @@ PLATS= aix bsd c89 freebsd generic linux
  # What to install.
  TO_BIN= lua$V luac$V
@@ -19,8 +19,8 @@
  	cd doc && $(INSTALL_DATA) $(TO_MAN) $(INSTALL_MAN)
  
  uninstall:
---- a/src/ldo.h	2017-04-19 11:20:42.000000000 -0600
-+++ b/src/ldo.h	2019-07-02 09:25:42.626694604 -0600
+--- a/src/ldo.h
++++ b/src/ldo.h
 @@ -47,8 +47,8 @@ LUAI_FUNC int luaD_pcall (lua_State *L,
  LUAI_FUNC int luaD_poscall (lua_State *L, CallInfo *ci, StkId firstResult,
                                            int nres);
@@ -32,8 +32,8 @@
  LUAI_FUNC void luaD_inctop (lua_State *L);
  
  LUAI_FUNC l_noret luaD_throw (lua_State *L, int errcode);
---- a/src/lfunc.h	2017-04-19 11:39:34.000000000 -0600
-+++ b/src/lfunc.h	2019-07-02 09:25:42.630694635 -0600
+--- a/src/lfunc.h
++++ b/src/lfunc.h
 @@ -47,14 +47,14 @@ struct UpVal {
  #define upisopen(up)	((up)->v != &(up)->u.value)
  
@@ -55,8 +55,8 @@
                                           int pc);
  
  
---- a/src/lgc.h	2017-04-19 11:39:34.000000000 -0600
-+++ b/src/lgc.h	2019-07-02 09:25:42.634694666 -0600
+--- a/src/lgc.h
++++ b/src/lgc.h
 @@ -133,11 +133,11 @@
  
  LUAI_FUNC void luaC_fix (lua_State *L, GCObject *o);
@@ -71,8 +71,8 @@
  LUAI_FUNC void luaC_barrierback_ (lua_State *L, Table *o);
  LUAI_FUNC void luaC_upvalbarrier_ (lua_State *L, UpVal *uv);
  LUAI_FUNC void luaC_checkfinalizer (lua_State *L, GCObject *o, Table *mt);
---- a/src/llex.h	2017-04-19 11:20:42.000000000 -0600
-+++ b/src/llex.h	2019-07-02 09:25:42.630694635 -0600
+--- a/src/llex.h
++++ b/src/llex.h
 @@ -73,13 +73,13 @@ typedef struct LexState {
  
  
@@ -92,8 +92,8 @@
  
  
  #endif
---- a/src/lmem.h	2017-04-19 11:20:42.000000000 -0600
-+++ b/src/lmem.h	2019-07-02 09:25:42.630694635 -0600
+--- a/src/lmem.h
++++ b/src/lmem.h
 @@ -56,12 +56,12 @@
  #define luaM_reallocvector(L, v,oldn,n,t) \
     ((v)=cast(t *, luaM_reallocv(L, v, oldn, n, sizeof(t))))
@@ -110,8 +110,8 @@
                                 size_t size_elem, int limit,
                                 const char *what);
  
---- a/src/lobject.h	2017-04-19 11:39:34.000000000 -0600
-+++ b/src/lobject.h	2019-07-02 09:25:42.630694635 -0600
+--- a/src/lobject.h
++++ b/src/lobject.h
 @@ -525,7 +525,7 @@ typedef struct Table {
  #define luaO_nilobject		(&luaO_nilobject_)
  
@@ -141,8 +141,8 @@
  
  
  #endif
---- a/src/lopcodes.h	2017-04-19 11:20:42.000000000 -0600
-+++ b/src/lopcodes.h	2019-07-02 09:25:42.630694635 -0600
+--- a/src/lopcodes.h
++++ b/src/lopcodes.h
 @@ -278,7 +278,7 @@ enum OpArgMask {
    OpArgK   /* argument is a constant or register/constant */
  };
@@ -161,8 +161,8 @@
  
  
  /* number of list items to accumulate before a SETLIST instruction */
---- a/src/lstate.h	2017-04-19 11:39:34.000000000 -0600
-+++ b/src/lstate.h	2019-07-02 09:25:42.630694635 -0600
+--- a/src/lstate.h
++++ b/src/lstate.h
 @@ -244,9 +244,9 @@ union GCUnion {
  
  LUAI_FUNC void luaE_setdebt (global_State *g, l_mem debt);
@@ -176,8 +176,8 @@
  
  
  #endif
---- a/src/lstring.h	2017-04-19 11:20:42.000000000 -0600
-+++ b/src/lstring.h	2019-07-02 09:25:42.630694635 -0600
+--- a/src/lstring.h
++++ b/src/lstring.h
 @@ -35,15 +35,15 @@
  
  LUAI_FUNC unsigned int luaS_hash (const char *str, size_t l, unsigned int seed);
@@ -198,8 +198,8 @@
  
  
  #endif
---- a/src/ltable.h	2018-05-24 13:39:05.000000000 -0600
-+++ b/src/ltable.h	2019-07-02 09:25:42.630694635 -0600
+--- a/src/ltable.h
++++ b/src/ltable.h
 @@ -41,14 +41,14 @@
  
  
@@ -218,8 +218,8 @@
  LUAI_FUNC void luaH_resize (lua_State *L, Table *t, unsigned int nasize,
                                                      unsigned int nhsize);
  LUAI_FUNC void luaH_resizearray (lua_State *L, Table *t, unsigned int nasize);
---- a/src/ltm.h	2017-04-19 11:20:42.000000000 -0600
-+++ b/src/ltm.h	2019-07-02 09:25:42.634694666 -0600
+--- a/src/ltm.h
++++ b/src/ltm.h
 @@ -55,10 +55,10 @@ typedef enum {
  LUAI_DDEC const char *const luaT_typenames_[LUA_TOTALTAGS];
  
@@ -245,8 +245,8 @@
                                  const TValue *p2, TMS event);
  
  
---- a/src/lundump.h	2017-04-19 11:20:42.000000000 -0600
-+++ b/src/lundump.h	2019-07-02 09:25:42.634694666 -0600
+--- a/src/lundump.h
++++ b/src/lundump.h
 @@ -23,10 +23,10 @@
  #define LUAC_FORMAT	0	/* this is the official format */
  
@@ -260,8 +260,8 @@
                           void* data, int strip);
  
  #endif
---- a/src/lzio.h	2017-04-19 11:20:42.000000000 -0600
-+++ b/src/lzio.h	2019-07-02 09:25:42.634694666 -0600
+--- a/src/lzio.h
++++ b/src/lzio.h
 @@ -61,6 +61,6 @@ struct Zio {
  };
  
@@ -270,8 +270,8 @@
 +LUA_API int luaZ_fill (ZIO *z);
  
  #endif
---- a/src/Makefile	2019-07-02 09:24:57.554332875 -0600
-+++ b/src/Makefile	2019-07-02 09:25:42.630694635 -0600
+--- a/src/Makefile
++++ b/src/Makefile
 @@ -29,6 +29,7 @@ MYOBJS=
  PLATS= aix bsd c89 freebsd generic linux macosx mingw posix solaris
  
diff --git a/package/utils/lua5.3/patches/200-CVE-2019-6706.patch b/package/utils/lua5.3/patches/200-CVE-2019-6706.patch
new file mode 100644
index 00000000000000..8024d414cc80af
--- /dev/null
+++ b/package/utils/lua5.3/patches/200-CVE-2019-6706.patch
@@ -0,0 +1,51 @@
+From 89aee84cbc9224f638f3b7951b306d2ee8ecb71e Mon Sep 17 00:00:00 2001
+From: Roberto Ierusalimschy <roberto@inf.puc-rio.br>
+Date: Wed, 27 Mar 2019 14:30:12 -0300
+Subject: [PATCH] Fixed bug in 'lua_upvaluejoin'
+
+Bug-fix: joining an upvalue with itself could cause a use-after-free
+crash.
+---
+ src/lapi.c   | 12 +++++------
+ 1 file changed, 41 insertions(+), 39 deletions(-)
+
+--- a/src/lapi.c
++++ b/src/lapi.c
+@@ -1254,13 +1254,12 @@ LUA_API const char *lua_setupvalue (lua_
+ }
+ 
+ 
+-static UpVal **getupvalref (lua_State *L, int fidx, int n, LClosure **pf) {
++static UpVal **getupvalref (lua_State *L, int fidx, int n) {
+   LClosure *f;
+   StkId fi = index2addr(L, fidx);
+   api_check(L, ttisLclosure(fi), "Lua function expected");
+   f = clLvalue(fi);
+   api_check(L, (1 <= n && n <= f->p->sizeupvalues), "invalid upvalue index");
+-  if (pf) *pf = f;
+   return &f->upvals[n - 1];  /* get its upvalue pointer */
+ }
+ 
+@@ -1269,7 +1268,7 @@ LUA_API void *lua_upvalueid (lua_State *
+   StkId fi = index2addr(L, fidx);
+   switch (ttype(fi)) {
+     case LUA_TLCL: {  /* lua closure */
+-      return *getupvalref(L, fidx, n, NULL);
++      return *getupvalref(L, fidx, n);
+     }
+     case LUA_TCCL: {  /* C closure */
+       CClosure *f = clCvalue(fi);
+@@ -1286,9 +1285,10 @@ LUA_API void *lua_upvalueid (lua_State *
+ 
+ LUA_API void lua_upvaluejoin (lua_State *L, int fidx1, int n1,
+                                             int fidx2, int n2) {
+-  LClosure *f1;
+-  UpVal **up1 = getupvalref(L, fidx1, n1, &f1);
+-  UpVal **up2 = getupvalref(L, fidx2, n2, NULL);
++  UpVal **up1 = getupvalref(L, fidx1, n1);
++  UpVal **up2 = getupvalref(L, fidx2, n2);
++  if (*up1 == *up2)
++    return;
+   luaC_upvdeccount(L, *up1);
+   *up1 = *up2;
+   (*up1)->refcount++;
diff --git a/package/utils/ucode/Makefile b/package/utils/ucode/Makefile
index f706ee5d20b22b..e18f53ea322d63 100644
--- a/package/utils/ucode/Makefile
+++ b/package/utils/ucode/Makefile
@@ -12,13 +12,14 @@ PKG_RELEASE:=1
 
 PKG_SOURCE_PROTO:=git
 PKG_SOURCE_URL=https://github.com/jow-/ucode.git
-PKG_SOURCE_DATE:=2023-11-30
-PKG_SOURCE_VERSION:=6e89b89e95bbb140bbff5ab72b8c9632727bf6a6
-PKG_MIRROR_HASH:=20ba99f8c2591b581cdf0245dd40301e517659193cddaa3a3888125fcc85b2aa
+PKG_SOURCE_DATE:=2024-02-21
+PKG_SOURCE_VERSION:=ba3855ae3775197f3594fc2615cac539075bd2fb
+PKG_MIRROR_HASH:=82b8a73417575b58a234586354eba4d0b10180a80b441cd87a9a554227304d34
 PKG_MAINTAINER:=Jo-Philipp Wich <jo@mein.io>
 PKG_LICENSE:=ISC
 
 PKG_ABI_VERSION:=20230711
+HOST_BUILD_DEPENDS:=libjson-c/host
 
 include $(INCLUDE_DIR)/package.mk
 include $(INCLUDE_DIR)/host-build.mk
diff --git a/package/utils/ugps/Makefile b/package/utils/ugps/Makefile
index 322f0d210d58be..66d42dca89df4e 100644
--- a/package/utils/ugps/Makefile
+++ b/package/utils/ugps/Makefile
@@ -8,13 +8,13 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=ugps
-PKG_RELEASE:=2
+PKG_RELEASE:=1
 
 PKG_SOURCE_URL=$(PROJECT_GIT)/project/ugps.git
 PKG_SOURCE_PROTO:=git
-PKG_SOURCE_DATE:=2023-01-27
-PKG_SOURCE_VERSION:=a8171a07193351a9125024d5c759c0ebd6a6895c
-PKG_MIRROR_HASH:=9116c9698c15744bb2e36a7cfd0a73f1609b6932f32ca07da57238aea8a2d5cf
+PKG_SOURCE_DATE:=2024-02-14
+PKG_SOURCE_VERSION:=69561a074d6f50f63b82608b19041e5eb2c605a9
+PKG_MIRROR_HASH:=6a9ea235665babc22393df53e6945030a2e2264d92afccf2e9cd61fa01aa3b11
 
 PKG_MAINTAINER:=John Crispin <john@phrozen.org>
 PKG_LICENSE:=GPL-2.0+
diff --git a/scripts/config/.gitignore b/scripts/config/.gitignore
index 05c55c3c8e58e2..1cef9de10fbf75 100644
--- a/scripts/config/.gitignore
+++ b/scripts/config/.gitignore
@@ -1,16 +1,14 @@
 # SPDX-License-Identifier: GPL-2.0-only
 /conf
 /[gmnq]conf
-/[gmnq]conf-cfg
+/[gmnq]conf-bin
+/[gmnq]conf-cflags
+/[gmnq]conf-libs
 /qconf-moc.cc
 
-# From linux kconfig parent directories
-.*
-
-# OpenWrt-generated files
+#
+# Added by openwrt
+#
 mconf_check
-
-# Temporary files from older versions.  They should be removed after the
-# end of support for OpenWrt 19.07.
-zconf.???.c
-zconf.hash.c
+# The next line should be removed after 23.05 is EOL
+*conf-cfg
diff --git a/scripts/config/Kbuild.include b/scripts/config/Kbuild.include
new file mode 100644
index 00000000000000..7778cc97a4e042
--- /dev/null
+++ b/scripts/config/Kbuild.include
@@ -0,0 +1,279 @@
+# SPDX-License-Identifier: GPL-2.0
+####
+# kbuild: Generic definitions
+
+# Convenient variables
+comma   := ,
+quote   := "
+squote  := '
+empty   :=
+space   := $(empty) $(empty)
+space_escape := _-_SPACE_-_
+pound := \#
+define newline
+
+
+endef
+
+###
+# Comparison macros.
+# Usage: $(call test-lt, $(CONFIG_LLD_VERSION), 150000)
+#
+# Use $(intcmp ...) if supported. (Make >= 4.4)
+# Otherwise, fall back to the 'test' shell command.
+ifeq ($(intcmp 1,0,,,y),y)
+test-ge = $(intcmp $(strip $1)0, $(strip $2)0,,y,y)
+test-gt = $(intcmp $(strip $1)0, $(strip $2)0,,,y)
+else
+test-ge = $(shell test $(strip $1)0 -ge $(strip $2)0 && echo y)
+test-gt = $(shell test $(strip $1)0 -gt $(strip $2)0 && echo y)
+endif
+test-le = $(call test-ge, $2, $1)
+test-lt = $(call test-gt, $2, $1)
+
+###
+# Name of target with a '.' as filename prefix. foo/bar.o => foo/.bar.o
+dot-target = $(dir $@).$(notdir $@)
+
+###
+# Name of target with a '.tmp_' as filename prefix. foo/bar.o => foo/.tmp_bar.o
+tmp-target = $(dir $@).tmp_$(notdir $@)
+
+###
+# The temporary file to save gcc -MMD generated dependencies must not
+# contain a comma
+depfile = $(subst $(comma),_,$(dot-target).d)
+
+###
+# filename of target with directory and extension stripped
+basetarget = $(basename $(notdir $@))
+
+###
+# real prerequisites without phony targets
+real-prereqs = $(filter-out $(PHONY), $^)
+
+###
+# Escape single quote for use in echo statements
+escsq = $(subst $(squote),'\$(squote)',$1)
+
+###
+# Quote a string to pass it to C files. foo => '"foo"'
+stringify = $(squote)$(quote)$1$(quote)$(squote)
+
+###
+# The path to Kbuild or Makefile. Kbuild has precedence over Makefile.
+kbuild-dir = $(if $(filter /%,$(src)),$(src),$(srctree)/$(src))
+kbuild-file = $(or $(wildcard $(kbuild-dir)/Kbuild),$(kbuild-dir)/Makefile)
+
+###
+# Read a file, replacing newlines with spaces
+#
+# Make 4.2 or later can read a file by using its builtin function.
+ifneq ($(filter-out 3.% 4.0 4.1, $(MAKE_VERSION)),)
+read-file = $(subst $(newline),$(space),$(file < $1))
+else
+read-file = $(shell cat $1 2>/dev/null)
+endif
+
+###
+# Easy method for doing a status message
+       kecho := :
+ quiet_kecho := echo
+silent_kecho := :
+kecho := $($(quiet)kecho)
+
+###
+# filechk is used to check if the content of a generated file is updated.
+# Sample usage:
+#
+# filechk_sample = echo $(KERNELRELEASE)
+# version.h: FORCE
+#	$(call filechk,sample)
+#
+# The rule defined shall write to stdout the content of the new file.
+# The existing file will be compared with the new one.
+# - If no file exist it is created
+# - If the content differ the new file is used
+# - If they are equal no change, and no timestamp update
+define filechk
+	$(check-FORCE)
+	$(Q)set -e;						\
+	mkdir -p $(dir $@);					\
+	trap "rm -f $(tmp-target)" EXIT;			\
+	{ $(filechk_$(1)); } > $(tmp-target);			\
+	if [ ! -r $@ ] || ! cmp -s $@ $(tmp-target); then	\
+		$(kecho) '  UPD     $@';			\
+		mv -f $(tmp-target) $@;				\
+	fi
+endef
+
+###
+# Shorthand for $(Q)$(MAKE) -f scripts/Makefile.build obj=
+# Usage:
+# $(Q)$(MAKE) $(build)=dir
+build := -f $(srctree)/scripts/Makefile.build obj
+
+###
+# Shorthand for $(Q)$(MAKE) -f scripts/Makefile.dtbinst obj=
+# Usage:
+# $(Q)$(MAKE) $(dtbinst)=dir
+dtbinst := -f $(srctree)/scripts/Makefile.dtbinst obj
+
+###
+# Shorthand for $(Q)$(MAKE) -f scripts/Makefile.clean obj=
+# Usage:
+# $(Q)$(MAKE) $(clean)=dir
+clean := -f $(srctree)/scripts/Makefile.clean obj
+
+# pring log
+#
+# If quiet is "silent_", print nothing and sink stdout
+# If quiet is "quiet_", print short log
+# If quiet is empty, print short log and whole command
+silent_log_print = exec >/dev/null;
+ quiet_log_print = $(if $(quiet_cmd_$1), echo '  $(call escsq,$(quiet_cmd_$1)$(why))';)
+       log_print = echo '$(pound) $(call escsq,$(or $(quiet_cmd_$1),cmd_$1 $@)$(why))'; \
+                   echo '  $(call escsq,$(cmd_$1))';
+
+# Delete the target on interruption
+#
+# GNU Make automatically deletes the target if it has already been changed by
+# the interrupted recipe. So, you can safely stop the build by Ctrl-C (Make
+# will delete incomplete targets), and resume it later.
+#
+# However, this does not work when the stderr is piped to another program, like
+#  $ make >&2 | tee log
+# Make dies with SIGPIPE before cleaning the targets.
+#
+# To address it, we clean the target in signal traps.
+#
+# Make deletes the target when it catches SIGHUP, SIGINT, SIGQUIT, SIGTERM.
+# So, we cover them, and also SIGPIPE just in case.
+#
+# Of course, this is unneeded for phony targets.
+delete-on-interrupt = \
+	$(if $(filter-out $(PHONY), $@), \
+		$(foreach sig, HUP INT QUIT TERM PIPE, \
+			trap 'rm -f $@; trap - $(sig); kill -s $(sig) $$$$' $(sig);))
+
+# print and execute commands
+cmd = @$(if $(cmd_$(1)),set -e; $($(quiet)log_print) $(delete-on-interrupt) $(cmd_$(1)),:)
+
+###
+# if_changed      - execute command if any prerequisite is newer than
+#                   target, or command line has changed
+# if_changed_dep  - as if_changed, but uses fixdep to reveal dependencies
+#                   including used config symbols
+# if_changed_rule - as if_changed but execute rule instead
+# See Documentation/kbuild/makefiles.rst for more info
+
+ifneq ($(KBUILD_NOCMDDEP),1)
+# Check if both commands are the same including their order. Result is empty
+# string if equal. User may override this check using make KBUILD_NOCMDDEP=1
+# If the target does not exist, the *.cmd file should not be included so
+# $(savedcmd_$@) gets empty. Then, target will be built even if $(newer-prereqs)
+# happens to become empty.
+cmd-check = $(filter-out $(subst $(space),$(space_escape),$(strip $(savedcmd_$@))), \
+                         $(subst $(space),$(space_escape),$(strip $(cmd_$1))))
+else
+# We still need to detect missing targets.
+cmd-check = $(if $(strip $(savedcmd_$@)),,1)
+endif
+
+# Replace >$< with >$$< to preserve $ when reloading the .cmd file
+# (needed for make)
+# Replace >#< with >$(pound)< to avoid starting a comment in the .cmd file
+# (needed for make)
+# Replace >'< with >'\''< to be able to enclose the whole string in '...'
+# (needed for the shell)
+make-cmd = $(call escsq,$(subst $(pound),$$(pound),$(subst $$,$$$$,$(cmd_$(1)))))
+
+# Find any prerequisites that are newer than target or that do not exist.
+# PHONY targets skipped in both cases.
+# If there is no prerequisite other than phony targets, $(newer-prereqs) becomes
+# empty even if the target does not exist. cmd-check saves this corner case.
+newer-prereqs = $(filter-out $(PHONY),$?)
+
+# It is a typical mistake to forget the FORCE prerequisite. Check it here so
+# no more breakage will slip in.
+check-FORCE = $(if $(filter FORCE, $^),,$(warning FORCE prerequisite is missing))
+
+if-changed-cond = $(newer-prereqs)$(cmd-check)$(check-FORCE)
+
+# Execute command if command has changed or prerequisite(s) are updated.
+if_changed = $(if $(if-changed-cond),$(cmd_and_savecmd),@:)
+
+cmd_and_savecmd =                                                            \
+	$(cmd);                                                              \
+	printf '%s\n' 'savedcmd_$@ := $(make-cmd)' > $(dot-target).cmd
+
+# Execute the command and also postprocess generated .d dependencies file.
+if_changed_dep = $(if $(if-changed-cond),$(cmd_and_fixdep),@:)
+
+cmd_and_fixdep =                                                             \
+	$(cmd);                                                              \
+	scripts/basic/fixdep $(depfile) $@ '$(make-cmd)' > $(dot-target).cmd;\
+	rm -f $(depfile)
+
+# Usage: $(call if_changed_rule,foo)
+# Will check if $(cmd_foo) or any of the prerequisites changed,
+# and if so will execute $(rule_foo).
+if_changed_rule = $(if $(if-changed-cond),$(rule_$(1)),@:)
+
+###
+# why - tell why a target got built
+#       enabled by make V=2
+#       Output (listed in the order they are checked):
+#          (1) - due to target is PHONY
+#          (2) - due to target missing
+#          (3) - due to: file1.h file2.h
+#          (4) - due to command line change
+#          (5) - due to missing .cmd file
+#          (6) - due to target not in $(targets)
+# (1) PHONY targets are always build
+# (2) No target, so we better build it
+# (3) Prerequisite is newer than target
+# (4) The command line stored in the file named dir/.target.cmd
+#     differed from actual command line. This happens when compiler
+#     options changes
+# (5) No dir/.target.cmd file (used to store command line)
+# (6) No dir/.target.cmd file and target not listed in $(targets)
+#     This is a good hint that there is a bug in the kbuild file
+ifneq ($(findstring 2, $(KBUILD_VERBOSE)),)
+_why =                                                                        \
+    $(if $(filter $@, $(PHONY)),- due to target is PHONY,                    \
+        $(if $(wildcard $@),                                                 \
+            $(if $(newer-prereqs),- due to: $(newer-prereqs),                \
+                $(if $(cmd-check),                                           \
+                    $(if $(savedcmd_$@),- due to command line change,        \
+                        $(if $(filter $@, $(targets)),                       \
+                            - due to missing .cmd file,                      \
+                            - due to $(notdir $@) not in $$(targets)         \
+                         )                                                   \
+                     )                                                       \
+                 )                                                           \
+             ),                                                              \
+             - due to target missing                                         \
+         )                                                                   \
+     )
+
+why = $(space)$(strip $(_why))
+endif
+
+###############################################################################
+
+# delete partially updated (i.e. corrupted) files on error
+.DELETE_ON_ERROR:
+
+# do not delete intermediate files automatically
+#
+# .NOTINTERMEDIATE is more correct, but only available on newer Make versions.
+# Make 4.4 introduced .NOTINTERMEDIATE, and it appears in .FEATURES, but the
+# global .NOTINTERMEDIATE does not work. We can use it on Make > 4.4.
+# Use .SECONDARY for older Make versions, but "newer-prereq" cannot detect
+# deleted files.
+ifneq ($(and $(filter notintermediate, $(.FEATURES)),$(filter-out 4.4,$(MAKE_VERSION))),)
+.NOTINTERMEDIATE:
+else
+.SECONDARY:
+endif
diff --git a/scripts/config/Makefile b/scripts/config/Makefile
index 5976a91b9abf8d..5e7dd9578ecfee 100644
--- a/scripts/config/Makefile
+++ b/scripts/config/Makefile
@@ -5,46 +5,21 @@
 .PHONY: clean all
 all: conf mconf
 clean:
-	rm -f *.o lxdialog/*.o *.moc .*.cmd $(clean-files)
+	rm -f $(clean-files) $(hostprogs)
 
-# This clean-files definition is here to ensure that temporary files from the
-# previous version are removed by make config-clean.
-# It should be emptied after the end of support for OpenWrt 19.07.
-clean-files	:= zconf.tab.c zconf.lex.c zconf.hash.c .tmp_qtcheck
+clean-files	:= *.o lxdialog/*.o *.moc qconf-moc.cc \
+		   *conf-cfg # <- This should be removed after 23.05 is EOL
 
 # ===========================================================================
 # Variables needed by the upstream Makefile
 
-# Avoids displaying 'UPD mconf-cfg' in an otherwise quiet make menuconfig
-kecho:=true
-
+export HOSTPKG_CONFIG=pkg-config
 CONFIG_SHELL:=$(SHELL)
-srctree:=.
-src:=.
+src:=$(CURDIR)
 obj:=.
 Q:=$(if $V,,@)
-cmd = $(cmd_$(1))
-
-# some definitions taken from ../Kbuild.include
-dot-target = $(dir $@).$(notdir $@)
-squote  := '
-escsq = $(subst $(squote),'\$(squote)',$1)
-define filechk
-	$(Q)set -e;						\
-	mkdir -p $(dir $@);					\
-	trap "rm -f $(dot-target).tmp" EXIT;			\
-	{ $(filechk_$(1)); } > $(dot-target).tmp;		\
-	if [ ! -r $@ ] || ! cmp -s $@ $(dot-target).tmp; then	\
-		$(kecho) '  UPD     $@';			\
-		mv -f $(dot-target).tmp $@;			\
-	fi
-endef
-cmd-check = $(if $(strip $(cmd_$@)),,1)
-make-cmd = $(call escsq,$(subst $(pound),$$(pound),$(subst $$,$$$$,$(cmd_$(1)))))
-newer-prereqs = $(filter-out $(PHONY),$?)
-if_changed = $(if $(newer-prereqs)$(cmd-check),			\
-	$(cmd);							\
-	printf '%s\n' 'cmd_$@ := $(make-cmd)' > $(dot-target).cmd, @:)
+quiet:=$(if $V,,_silent)
+include Kbuild.include
 
 ### Stripped down upstream Makefile follows:
 # ===========================================================================
@@ -64,11 +39,12 @@ conf-objs	:= conf.o $(common-objs)
 hostprogs	+= nconf
 nconf-objs	:= nconf.o nconf.gui.o $(common-objs)
 
-HOSTLDLIBS_nconf	= $(shell . $(obj)/nconf-cfg && echo $$libs)
-HOSTCFLAGS_nconf.o	= $(shell . $(obj)/nconf-cfg && echo $$cflags)
-HOSTCFLAGS_nconf.gui.o	= $(shell . $(obj)/nconf-cfg && echo $$cflags)
+HOSTLDLIBS_nconf       = $(call read-file, $(obj)/nconf-libs)
+HOSTCFLAGS_nconf.o     = $(call read-file, $(obj)/nconf-cflags)
+HOSTCFLAGS_nconf.gui.o = $(call read-file, $(obj)/nconf-cflags)
 
-$(obj)/nconf.o $(obj)/nconf.gui.o: $(obj)/nconf-cfg
+$(obj)/nconf: | $(obj)/nconf-libs
+$(obj)/nconf.o $(obj)/nconf.gui.o: | $(obj)/nconf-cflags
 
 # mconf: Used for the menuconfig target based on lxdialog
 hostprogs	+= mconf
@@ -76,45 +52,44 @@ lxdialog	:= $(addprefix lxdialog/, \
 		     checklist.o inputbox.o menubox.o textbox.o util.o yesno.o)
 mconf-objs	:= mconf.o $(lxdialog) $(common-objs)
 
-HOSTLDLIBS_mconf = $(shell . $(obj)/mconf-cfg && echo $$libs)
+HOSTLDLIBS_mconf = $(call read-file, $(obj)/mconf-libs)
 $(foreach f, mconf.o $(lxdialog), \
-  $(eval HOSTCFLAGS_$f = $$(shell . $(obj)/mconf-cfg && echo $$$$cflags)))
+  $(eval HOSTCFLAGS_$f = $$(call read-file, $(obj)/mconf-cflags)))
 
-$(addprefix $(obj)/, mconf.o $(lxdialog)): $(obj)/mconf-cfg
+$(obj)/mconf: | $(obj)/mconf-libs
+$(addprefix $(obj)/, mconf.o $(lxdialog)): | $(obj)/mconf-cflags
 
 # qconf: Used for the xconfig target based on Qt
 hostprogs	+= qconf
 qconf-cxxobjs	:= qconf.o qconf-moc.o
 qconf-objs	:= images.o $(common-objs)
 
-HOSTLDLIBS_qconf	= $(shell . $(obj)/qconf-cfg && echo $$libs)
-HOSTCXXFLAGS_qconf.o	= $(shell . $(obj)/qconf-cfg && echo $$cflags)
-HOSTCXXFLAGS_qconf-moc.o = $(shell . $(obj)/qconf-cfg && echo $$cflags)
-
-$(obj)/qconf.o: $(obj)/qconf-cfg
+HOSTLDLIBS_qconf         = $(call read-file, $(obj)/qconf-libs)
+HOSTCXXFLAGS_qconf.o     = -std=c++11 -fPIC $(call read-file, $(obj)/qconf-cflags)
+HOSTCXXFLAGS_qconf-moc.o = -std=c++11 -fPIC $(call read-file, $(obj)/qconf-cflags)
+$(obj)/qconf: | $(obj)/qconf-libs
+$(obj)/qconf.o $(obj)/qconf-moc.o: | $(obj)/qconf-cflags
 
 quiet_cmd_moc = MOC     $@
-      cmd_moc = $(shell . $(obj)/qconf-cfg && echo $$moc) $< -o $@
+      cmd_moc = $(call read-file, $(obj)/qconf-bin)/moc $< -o $@
 
-$(obj)/qconf-moc.cc: $(src)/qconf.h $(obj)/qconf-cfg FORCE
+$(obj)/qconf-moc.cc: $(src)/qconf.h FORCE | $(obj)/qconf-bin
 	$(call if_changed,moc)
 
 targets += qconf-moc.cc
 
 # check if necessary packages are available, and configure build flags
-filechk_conf_cfg = $(CONFIG_SHELL) $<
+cmd_conf_cfg = $< $(addprefix $(obj)/$*conf-, cflags libs bin); touch $(obj)/$*conf-bin
 
-$(obj)/%conf-cfg: $(src)/%conf-cfg.sh FORCE
-	$(call filechk,conf_cfg)
+$(obj)/%conf-cflags $(obj)/%conf-libs $(obj)/%conf-bin: $(src)/%conf-cfg.sh
+	$(call cmd,conf_cfg)
 
-clean-files += *conf-cfg
+clean-files += *conf-cflags *conf-libs *conf-bin
 
 # ===========================================================================
 # OpenWrt rules and final adjustments that need to be made after reading the
 # full upstream Makefile
 
-clean-files += $(targets) $(hostprogs)
-
 FORCE:
 
 ifdef BUILD_SHIPPED_FILES
@@ -130,25 +105,21 @@ clean-files += $(shipped-files)
 	flex -L -o$@ $<
 endif
 
-$(foreach f,$(conf-objs) $(filter-out $(common-objs),$(mconf-objs) \
-						     $(qconf-objs) \
-						     $(nconf-objs)), \
-  $(eval $(obj)/$f: CFLAGS+=$$(HOSTCFLAGS_$f)))
-
-$(foreach f,$(qconf-cxxobjs), \
-  $(eval $(obj)/$f: CXXFLAGS+=$$(HOSTCXXFLAGS_$f)))
+define link_rule
+$(1): LDLIBS+=$$(HOSTLDLIBS_$(1))
+$(1): $($(1)-objs) $$($(1)-cxxobjs)
+$(if $($(1)-cxxobjs),	$(CXX) $$(LDFLAGS) -o $$@ $$^ $$(LDLIBS))
+all-objs += $($(1)-objs)
+all-cxxobjs += $($(1)-cxxobjs)
+endef
 
-$(obj)/conf: $(addprefix $(obj)/,$(conf-objs))
+all-objs:=
+all-cxxobjs:=
+$(foreach f,$(hostprogs),$(eval $(call link_rule,$f)))
 
-# The *conf-cfg file is used (then filtered out) as the first prerequisite to
-# avoid sourcing it before the script is built, when trying to compute CFLAGS
-# for the actual first prerequisite.  This avoids errors like:
-# '/bin/sh: ./mconf-cfg: No such file or directory'
-$(obj)/mconf: mconf-cfg $(addprefix $(obj)/,$(mconf-objs))
-	$(CC) -o $@ $(filter-out mconf-cfg,$^) $(HOSTLDLIBS_mconf)
 
-$(obj)/nconf: nconf-cfg $(addprefix $(obj)/,$(nconf-objs))
-	$(CC) -o $@ $(filter-out nconf-cfg,$^) $(HOSTLDLIBS_nconf)
+$(foreach f,$(sort $(all-objs)), \
+  $(eval $f: CFLAGS+=$$(HOSTCFLAGS_$f)))
 
-$(obj)/qconf: qconf-cfg $(addprefix $(obj)/,$(qconf-cxxobjs) $(qconf-objs))
-	$(CXX) -o $@ $(filter-out qconf-cfg,$^) $(HOSTLDLIBS_qconf)
+$(foreach f,$(sort $(all-cxxobjs)), \
+  $(eval $f: CXXFLAGS+=$$(HOSTCXXFLAGS_$f)))
diff --git a/scripts/config/README b/scripts/config/README
index 99a7d535ab25d2..e1ebf89cbf1dd4 100644
--- a/scripts/config/README
+++ b/scripts/config/README
@@ -1,6 +1,7 @@
-These files were taken from the Linux 5.14 Kernel Configuration System and
-modified for the OpenWrt Buildroot:
- - Removed nconf, gconf, tests and kernel configuration targets.
+These files were taken from the Linux Kernel Configuration System v6.6.16, 
+at commit eb3e299184cc4f40d4bd84fda269b3a20ddcff80 (Feb 5, 2024),  and modified
+for the OpenWrt Buildroot:
+ - Removed gconf, tests and kernel configuration targets.
  - Adjusted the Makefile to compile outside the kernel.
  - Always use default file when running make all{no,mod,yes}config.
  - Added a 'reset' command to reset config when the target changes.
@@ -23,4 +24,4 @@ modified for the OpenWrt Buildroot:
    BUILD_SHIPPED_FILES defined
 
 For a full list of changes, see the repository at:
-https://github.com/cotequeiroz/linux/commits/openwrt-5.14/scripts/kconfig
+https://github.com/cotequeiroz/linux/commits/openwrt-v6.6.16/scripts/kconfig
diff --git a/scripts/config/conf.c b/scripts/config/conf.c
index 978abebe654555..1bd6f4fa8ba612 100644
--- a/scripts/config/conf.c
+++ b/scripts/config/conf.c
@@ -35,6 +35,7 @@ enum input_mode {
 	olddefconfig,
 	yes2modconfig,
 	mod2yesconfig,
+	mod2noconfig,
 	fatalrecursive,
 };
 static enum input_mode input_mode = oldaskconfig;
@@ -164,8 +165,6 @@ enum conf_def_mode {
 	def_default,
 	def_yes,
 	def_mod,
-	def_y2m,
-	def_m2y,
 	def_no,
 	def_random
 };
@@ -303,12 +302,10 @@ static bool conf_set_all_new_symbols(enum conf_def_mode mode)
 	return has_changed;
 }
 
-static void conf_rewrite_mod_or_yes(enum conf_def_mode mode)
+static void conf_rewrite_tristates(tristate old_val, tristate new_val)
 {
 	struct symbol *sym;
 	int i;
-	tristate old_val = (mode == def_y2m) ? yes : mod;
-	tristate new_val = (mode == def_y2m) ? mod : yes;
 
 	for_all_symbols(i, sym) {
 		if (sym_get_type(sym) == S_TRISTATE &&
@@ -555,7 +552,7 @@ static int conf_choice(struct menu *menu)
 			print_help(child);
 			continue;
 		}
-		sym_set_choice_value(sym, child->sym);
+		sym_set_tristate_value(child->sym, yes);
 		for (child = child->list; child; child = child->next) {
 			indent += 2;
 			conf(child);
@@ -647,19 +644,8 @@ static void check_conf(struct menu *menu)
 
 		switch (input_mode) {
 		case listnewconfig:
-			if (sym->name) {
-				const char *str;
-
-				if (sym->type == S_STRING) {
-					str = sym_get_string_value(sym);
-					str = sym_escape_string_value(str);
-					printf("%s%s=%s\n", CONFIG_, sym->name, str);
-					free((void *)str);
-				} else {
-					str = sym_get_string_value(sym);
-					printf("%s%s=%s\n", CONFIG_, sym->name, str);
-				}
-			}
+			if (sym->name)
+				print_symbol_for_listconfig(sym);
 			break;
 		case helpnewconfig:
 			printf("-----\n");
@@ -697,7 +683,8 @@ static const struct option long_opts[] = {
 	{"olddefconfig",  no_argument,       &input_mode_opt, olddefconfig},
 	{"yes2modconfig", no_argument,       &input_mode_opt, yes2modconfig},
 	{"mod2yesconfig", no_argument,       &input_mode_opt, mod2yesconfig},
-	{"fatalrecursive",no_argument,       NULL, fatalrecursive},
+	{"mod2noconfig",  no_argument,       &input_mode_opt, mod2noconfig},
+	{"fatalrecursive",no_argument,       &input_mode_opt, fatalrecursive},
 	{NULL, 0, NULL, 0}
 };
 
@@ -707,8 +694,10 @@ static void conf_usage(const char *progname)
 	printf("\n");
 	printf("Generic options:\n");
 	printf("  -h, --help              Print this message and exit.\n");
+	printf("  -r <file>               Read <file> as input.\n");
 	printf("  -s, --silent            Do not print log.\n");
-	printf("      --fatalrecursive    Treat recursive depenendencies as a fatal error\n");
+	printf("  -w <file>               Write config to <file>.\n");
+	printf("  --fatalrecursive        Treat recursive dependency as error.\n");
 	printf("\n");
 	printf("Mode options:\n");
 	printf("  --listnewconfig         List new options\n");
@@ -727,6 +716,7 @@ static void conf_usage(const char *progname)
 	printf("  --randconfig            New config with random answer to all options\n");
 	printf("  --yes2modconfig         Change answers from yes to mod if possible\n");
 	printf("  --mod2yesconfig         Change answers from mod to yes if possible\n");
+	printf("  --mod2noconfig          Change answers from mod to no if possible\n");
 	printf("  (If none of the above is given, --oldaskconfig is the default)\n");
 }
 
@@ -740,27 +730,23 @@ int main(int ac, char **av)
 
 	tty_stdio = isatty(0) && isatty(1);
 
-	while ((opt = getopt_long(ac, av, "hr:sw:", long_opts, NULL)) != -1) {
+	while ((opt = getopt_long(ac, av, "hr:w:s", long_opts, NULL)) != -1) {
 		switch (opt) {
 		case 'h':
 			conf_usage(progname);
 			exit(1);
 			break;
-		case 's':
-			conf_set_message_callback(NULL);
-			break;
-		case fatalrecursive:
-			recursive_is_error = 1;
-			continue;
 		case 'r':
 			input_file = optarg;
 			break;
+		case 's':
+			conf_set_message_callback(NULL);
+			break;
 		case 'w':
 			output_file = optarg;
 			break;
 		case 0:
-			input_mode = input_mode_opt;
-			switch (input_mode) {
+			switch (input_mode_opt) {
 			case syncconfig:
 				/*
 				 * syncconfig is invoked during the build stage.
@@ -777,9 +763,13 @@ int main(int ac, char **av)
 			case randconfig:
 				set_randconfig_seed();
 				break;
+			case fatalrecursive:
+				recursive_is_error = 1;
+				continue;
 			default:
 				break;
 			}
+			input_mode = input_mode_opt;
 		default:
 			break;
 		}
@@ -812,6 +802,7 @@ int main(int ac, char **av)
 	case olddefconfig:
 	case yes2modconfig:
 	case mod2yesconfig:
+	case mod2noconfig:
 	case allnoconfig:
 	case allyesconfig:
 	case allmodconfig:
@@ -858,10 +849,13 @@ int main(int ac, char **av)
 	case savedefconfig:
 		break;
 	case yes2modconfig:
-		conf_rewrite_mod_or_yes(def_y2m);
+		conf_rewrite_tristates(yes, mod);
 		break;
 	case mod2yesconfig:
-		conf_rewrite_mod_or_yes(def_m2y);
+		conf_rewrite_tristates(mod, yes);
+		break;
+	case mod2noconfig:
+		conf_rewrite_tristates(mod, no);
 		break;
 	case oldaskconfig:
 		rootEntry = &rootmenu;
diff --git a/scripts/config/confdata.c b/scripts/config/confdata.c
index dad0b471c7df31..e3f6fdfeb324e8 100644
--- a/scripts/config/confdata.c
+++ b/scripts/config/confdata.c
@@ -11,6 +11,7 @@
 #include <fcntl.h>
 #include <limits.h>
 #include <stdarg.h>
+#include <stdbool.h>
 #include <stdio.h>
 #include <stdlib.h>
 #include <string.h>
@@ -129,41 +130,22 @@ static size_t depfile_prefix_len;
 /* touch depfile for symbol 'name' */
 static int conf_touch_dep(const char *name)
 {
-	int fd, ret;
-	char *d;
+	int fd;
 
 	/* check overflow: prefix + name + '\0' must fit in buffer. */
 	if (depfile_prefix_len + strlen(name) + 1 > sizeof(depfile_path))
 		return -1;
 
-	d = depfile_path + depfile_prefix_len;
-	strcpy(d, name);
+	strcpy(depfile_path + depfile_prefix_len, name);
 
-	/* Assume directory path already exists. */
 	fd = open(depfile_path, O_WRONLY | O_CREAT | O_TRUNC, 0644);
-	if (fd == -1) {
-		if (errno != ENOENT)
-			return -1;
-
-		ret = make_parent_dir(depfile_path);
-		if (ret)
-			return ret;
-
-		/* Try it again. */
-		fd = open(depfile_path, O_WRONLY | O_CREAT | O_TRUNC, 0644);
-		if (fd == -1)
-			return -1;
-	}
+	if (fd == -1)
+		return -1;
 	close(fd);
 
 	return 0;
 }
 
-struct conf_printer {
-	void (*print_symbol)(FILE *, struct symbol *, const char *, void *);
-	void (*print_comment)(FILE *, const char *, void *);
-};
-
 static void conf_warning(const char *fmt, ...)
 	__attribute__ ((format (printf, 1, 2)));
 
@@ -227,6 +209,20 @@ static const char *conf_get_autoconfig_name(void)
 	return name ? name : "include/config/auto.conf";
 }
 
+static const char *conf_get_autoheader_name(void)
+{
+	char *name = getenv("KCONFIG_AUTOHEADER");
+
+	return name ? name : "include/generated/autoconf.h";
+}
+
+static const char *conf_get_rustccfg_name(void)
+{
+	char *name = getenv("KCONFIG_RUSTCCFG");
+
+	return name ? name : "include/generated/rustc_cfg";
+}
+
 static int conf_set_sym_val(struct symbol *sym, int def, int def_flags, char *p)
 {
 	char *p2;
@@ -255,19 +251,21 @@ static int conf_set_sym_val(struct symbol *sym, int def, int def_flags, char *p)
 				     p, sym->name);
 		return 1;
 	case S_STRING:
-		if (*p++ != '"')
-			break;
-		for (p2 = p; (p2 = strpbrk(p2, "\"\\")); p2++) {
-			if (*p2 == '"') {
-				*p2 = 0;
+		/* No escaping for S_DEF_AUTO (include/config/auto.conf) */
+		if (def != S_DEF_AUTO) {
+			if (*p++ != '"')
 				break;
+			for (p2 = p; (p2 = strpbrk(p2, "\"\\")); p2++) {
+				if (*p2 == '"') {
+					*p2 = 0;
+					break;
+				}
+				memmove(p2, p2 + 1, strlen(p2));
 			}
-			memmove(p2, p2 + 1, strlen(p2));
-		}
-		if (!p2) {
-			if (def != S_DEF_AUTO)
+			if (!p2) {
 				conf_warning("invalid string found");
-			return 1;
+				return 1;
+			}
 		}
 		/* fall through */
 	case S_INT:
@@ -376,7 +374,11 @@ int conf_read_simple(const char *name, int def)
 	char *p, *p2;
 	struct symbol *sym;
 	int def_flags;
+	const char *warn_unknown;
+	const char *werror;
 
+	warn_unknown = getenv("KCONFIG_WARN_UNKNOWN_SYMBOLS");
+	werror = getenv("KCONFIG_WERROR");
 	if (name) {
 		in = zconf_fopen(name);
 	} else {
@@ -448,6 +450,10 @@ int conf_read_simple(const char *name, int def)
 			if (def == S_DEF_USER) {
 				sym = sym_find(line + 2 + strlen(CONFIG_));
 				if (!sym) {
+					if (warn_unknown)
+						conf_warning("unknown symbol: %s",
+							     line + 2 + strlen(CONFIG_));
+
 					conf_set_changed(true);
 					continue;
 				}
@@ -479,7 +485,7 @@ int conf_read_simple(const char *name, int def)
 
 			sym = sym_find(line + strlen(CONFIG_));
 			if (!sym) {
-				if (def == S_DEF_AUTO)
+				if (def == S_DEF_AUTO) {
 					/*
 					 * Reading from include/config/auto.conf
 					 * If CONFIG_FOO previously existed in
@@ -487,8 +493,13 @@ int conf_read_simple(const char *name, int def)
 					 * include/config/FOO must be touched.
 					 */
 					conf_touch_dep(line + strlen(CONFIG_));
-				else
+				} else {
+					if (warn_unknown)
+						conf_warning("unknown symbol: %s",
+							     line + strlen(CONFIG_));
+
 					conf_set_changed(true);
+				}
 				continue;
 			}
 
@@ -524,6 +535,10 @@ int conf_read_simple(const char *name, int def)
 	}
 	free(line);
 	fclose(in);
+
+	if (conf_warnings && werror)
+		exit(1);
+
 	return 0;
 }
 
@@ -597,169 +612,226 @@ int conf_read(const char *name)
 	return 0;
 }
 
-/*
- * Kconfig configuration printer
- *
- * This printer is used when generating the resulting configuration after
- * kconfig invocation and `defconfig' files. Unset symbol might be omitted by
- * passing a non-NULL argument to the printer.
- *
- */
-static void
-kconfig_print_symbol(FILE *fp, struct symbol *sym, const char *value, void *arg)
+struct comment_style {
+	const char *decoration;
+	const char *prefix;
+	const char *postfix;
+};
+
+static const struct comment_style comment_style_pound = {
+	.decoration = "#",
+	.prefix = "#",
+	.postfix = "#",
+};
+
+static const struct comment_style comment_style_c = {
+	.decoration = " *",
+	.prefix = "/*",
+	.postfix = " */",
+};
+
+static void conf_write_heading(FILE *fp, const struct comment_style *cs)
 {
+	if (!cs)
+		return;
 
-	switch (sym->type) {
-	case S_BOOLEAN:
-	case S_TRISTATE:
-		if (*value == 'n') {
-			bool skip_unset = (arg != NULL);
+	fprintf(fp, "%s\n", cs->prefix);
 
-			if (!skip_unset)
-				fprintf(fp, "# %s%s is not set\n",
-				    CONFIG_, sym->name);
-			return;
-		}
-		break;
-	default:
-		break;
-	}
+	fprintf(fp, "%s Automatically generated file; DO NOT EDIT.\n",
+		cs->decoration);
+
+	fprintf(fp, "%s %s\n", cs->decoration, rootmenu.prompt->text);
 
-	fprintf(fp, "%s%s=%s\n", CONFIG_, sym->name, value);
+	fprintf(fp, "%s\n", cs->postfix);
 }
 
-static void
-kconfig_print_comment(FILE *fp, const char *value, void *arg)
+/* The returned pointer must be freed on the caller side */
+static char *escape_string_value(const char *in)
 {
-	const char *p = value;
-	size_t l;
+	const char *p;
+	char *out;
+	size_t len;
 
-	for (;;) {
-		l = strcspn(p, "\n");
-		fprintf(fp, "#");
-		if (l) {
-			fprintf(fp, " ");
-			xfwrite(p, l, 1, fp);
-			p += l;
-		}
-		fprintf(fp, "\n");
-		if (*p++ == '\0')
+	len = strlen(in) + strlen("\"\"") + 1;
+
+	p = in;
+	while (1) {
+		p += strcspn(p, "\"\\");
+
+		if (p[0] == '\0')
 			break;
+
+		len++;
+		p++;
+	}
+
+	out = xmalloc(len);
+	out[0] = '\0';
+
+	strcat(out, "\"");
+
+	p = in;
+	while (1) {
+		len = strcspn(p, "\"\\");
+		strncat(out, p, len);
+		p += len;
+
+		if (p[0] == '\0')
+			break;
+
+		strcat(out, "\\");
+		strncat(out, p++, 1);
 	}
+
+	strcat(out, "\"");
+
+	return out;
 }
 
-static struct conf_printer kconfig_printer_cb =
+enum output_n { OUTPUT_N, OUTPUT_N_AS_UNSET, OUTPUT_N_NONE };
+
+static void __print_symbol(FILE *fp, struct symbol *sym, enum output_n output_n,
+			   bool escape_string)
 {
-	.print_symbol = kconfig_print_symbol,
-	.print_comment = kconfig_print_comment,
-};
+	const char *val;
+	char *escaped = NULL;
 
-/*
- * Header printer
- *
- * This printer is used when generating the `include/generated/autoconf.h' file.
- */
-static void
-header_print_symbol(FILE *fp, struct symbol *sym, const char *value, void *arg)
+	if (sym->type == S_UNKNOWN)
+		return;
+
+	val = sym_get_string_value(sym);
+
+	if ((sym->type == S_BOOLEAN || sym->type == S_TRISTATE) &&
+	    output_n != OUTPUT_N && *val == 'n') {
+		if (output_n == OUTPUT_N_AS_UNSET)
+			fprintf(fp, "# %s%s is not set\n", CONFIG_, sym->name);
+		return;
+	}
+
+	if (sym->type == S_STRING && escape_string) {
+		escaped = escape_string_value(val);
+		val = escaped;
+	}
+
+	fprintf(fp, "%s%s=%s\n", CONFIG_, sym->name, val);
+
+	free(escaped);
+}
+
+static void print_symbol_for_dotconfig(FILE *fp, struct symbol *sym)
 {
+	__print_symbol(fp, sym, OUTPUT_N_AS_UNSET, true);
+}
+
+static void print_symbol_for_autoconf(FILE *fp, struct symbol *sym)
+{
+	__print_symbol(fp, sym, OUTPUT_N_NONE, false);
+}
+
+void print_symbol_for_listconfig(struct symbol *sym)
+{
+	__print_symbol(stdout, sym, OUTPUT_N, true);
+}
+
+static void print_symbol_for_c(FILE *fp, struct symbol *sym)
+{
+	const char *val;
+	const char *sym_suffix = "";
+	const char *val_prefix = "";
+	char *escaped = NULL;
+
+	if (sym->type == S_UNKNOWN)
+		return;
+
+	val = sym_get_string_value(sym);
 
 	switch (sym->type) {
 	case S_BOOLEAN:
-	case S_TRISTATE: {
-		const char *suffix = "";
-
-		switch (*value) {
+	case S_TRISTATE:
+		switch (*val) {
 		case 'n':
-			break;
+			return;
 		case 'm':
-			suffix = "_MODULE";
+			sym_suffix = "_MODULE";
 			/* fall through */
 		default:
-			fprintf(fp, "#define %s%s%s 1\n",
-			    CONFIG_, sym->name, suffix);
+			val = "1";
 		}
 		break;
-	}
-	case S_HEX: {
-		const char *prefix = "";
-
-		if (value[0] != '0' || (value[1] != 'x' && value[1] != 'X'))
-			prefix = "0x";
-		fprintf(fp, "#define %s%s %s%s\n",
-		    CONFIG_, sym->name, prefix, value);
+	case S_HEX:
+		if (val[0] != '0' || (val[1] != 'x' && val[1] != 'X'))
+			val_prefix = "0x";
 		break;
-	}
 	case S_STRING:
-	case S_INT:
-		fprintf(fp, "#define %s%s %s\n",
-		    CONFIG_, sym->name, value);
-		break;
+		escaped = escape_string_value(val);
+		val = escaped;
 	default:
 		break;
 	}
 
-}
-
-static void
-header_print_comment(FILE *fp, const char *value, void *arg)
-{
-	const char *p = value;
-	size_t l;
+	fprintf(fp, "#define %s%s%s %s%s\n", CONFIG_, sym->name, sym_suffix,
+		val_prefix, val);
 
-	fprintf(fp, "/*\n");
-	for (;;) {
-		l = strcspn(p, "\n");
-		fprintf(fp, " *");
-		if (l) {
-			fprintf(fp, " ");
-			xfwrite(p, l, 1, fp);
-			p += l;
-		}
-		fprintf(fp, "\n");
-		if (*p++ == '\0')
-			break;
-	}
-	fprintf(fp, " */\n");
+	free(escaped);
 }
 
-static struct conf_printer header_printer_cb =
+static void print_symbol_for_rustccfg(FILE *fp, struct symbol *sym)
 {
-	.print_symbol = header_print_symbol,
-	.print_comment = header_print_comment,
-};
+	const char *val;
+	const char *val_prefix = "";
+	char *val_prefixed = NULL;
+	size_t val_prefixed_len;
+	char *escaped = NULL;
 
-static void conf_write_symbol(FILE *fp, struct symbol *sym,
-			      struct conf_printer *printer, void *printer_arg)
-{
-	const char *str;
+	if (sym->type == S_UNKNOWN)
+		return;
+
+	val = sym_get_string_value(sym);
 
 	switch (sym->type) {
-	case S_UNKNOWN:
+	case S_BOOLEAN:
+	case S_TRISTATE:
+		/*
+		 * We do not care about disabled ones, i.e. no need for
+		 * what otherwise are "comments" in other printers.
+		 */
+		if (*val == 'n')
+			return;
+
+		/*
+		 * To have similar functionality to the C macro `IS_ENABLED()`
+		 * we provide an empty `--cfg CONFIG_X` here in both `y`
+		 * and `m` cases.
+		 *
+		 * Then, the common `fprintf()` below will also give us
+		 * a `--cfg CONFIG_X="y"` or `--cfg CONFIG_X="m"`, which can
+		 * be used as the equivalent of `IS_BUILTIN()`/`IS_MODULE()`.
+		 */
+		fprintf(fp, "--cfg=%s%s\n", CONFIG_, sym->name);
 		break;
-	case S_STRING:
-		str = sym_get_string_value(sym);
-		str = sym_escape_string_value(str);
-		printer->print_symbol(fp, sym, str, printer_arg);
-		free((void *)str);
+	case S_HEX:
+		if (val[0] != '0' || (val[1] != 'x' && val[1] != 'X'))
+			val_prefix = "0x";
 		break;
 	default:
-		str = sym_get_string_value(sym);
-		printer->print_symbol(fp, sym, str, printer_arg);
+		break;
 	}
-}
 
-static void
-conf_write_heading(FILE *fp, struct conf_printer *printer, void *printer_arg)
-{
-	char buf[256];
+	if (strlen(val_prefix) > 0) {
+		val_prefixed_len = strlen(val) + strlen(val_prefix) + 1;
+		val_prefixed = xmalloc(val_prefixed_len);
+		snprintf(val_prefixed, val_prefixed_len, "%s%s", val_prefix, val);
+		val = val_prefixed;
+	}
+
+	/* All values get escaped: the `--cfg` option only takes strings */
+	escaped = escape_string_value(val);
+	val = escaped;
 
-	snprintf(buf, sizeof(buf),
-	    "\n"
-	    "Automatically generated file; DO NOT EDIT.\n"
-	    "%s\n",
-	    rootmenu.prompt->text);
+	fprintf(fp, "--cfg=%s%s=%s\n", CONFIG_, sym->name, val);
 
-	printer->print_comment(fp, buf, printer_arg);
+	free(escaped);
+	free(val_prefixed);
 }
 
 /*
@@ -818,7 +890,7 @@ int conf_write_defconfig(const char *filename)
 						goto next_menu;
 				}
 			}
-			conf_write_symbol(out, sym, &kconfig_printer_cb, NULL);
+			print_symbol_for_dotconfig(out, sym);
 		}
 next_menu:
 		if (menu->list != NULL) {
@@ -878,7 +950,7 @@ int conf_write(const char *name)
 	if (!out)
 		return 1;
 
-	conf_write_heading(out, &kconfig_printer_cb, NULL);
+	conf_write_heading(out, &comment_style_pound);
 
 	if (!conf_get_changed())
 		sym_clear_all_valid();
@@ -905,7 +977,7 @@ int conf_write(const char *name)
 				need_newline = false;
 			}
 			sym->flags |= SYMBOL_WRITTEN;
-			conf_write_symbol(out, sym, &kconfig_printer_cb, NULL);
+			print_symbol_for_dotconfig(out, sym);
 		}
 
 next:
@@ -913,19 +985,20 @@ int conf_write(const char *name)
 			menu = menu->list;
 			continue;
 		}
-		if (menu->next)
+
+end_check:
+		if (!menu->sym && menu_is_visible(menu) && menu != &rootmenu &&
+		    menu->prompt->type == P_MENU) {
+			fprintf(out, "# end of %s\n", menu_get_prompt(menu));
+			need_newline = true;
+		}
+
+		if (menu->next) {
 			menu = menu->next;
-		else while ((menu = menu->parent)) {
-			if (!menu->sym && menu_is_visible(menu) &&
-			    menu != &rootmenu) {
-				str = menu_get_prompt(menu);
-				fprintf(out, "# end of %s\n", str);
-				need_newline = true;
-			}
-			if (menu->next) {
-				menu = menu->next;
-				break;
-			}
+		} else {
+			menu = menu->parent;
+			if (menu)
+				goto end_check;
 		}
 	}
 	fclose(out);
@@ -955,45 +1028,69 @@ int conf_write(const char *name)
 }
 
 /* write a dependency file as used by kbuild to track dependencies */
-static int conf_write_dep(const char *name)
+static int conf_write_autoconf_cmd(const char *autoconf_name)
 {
+	char name[PATH_MAX], tmp[PATH_MAX];
 	struct file *file;
 	FILE *out;
+	int ret;
 
-	out = fopen("..config.tmp", "w");
-	if (!out)
-		return 1;
-	fprintf(out, "deps_config := \\\n");
-	for (file = file_list; file; file = file->next) {
-		if (file->next)
-			fprintf(out, "\t%s \\\n", file->name);
-		else
-			fprintf(out, "\t%s\n", file->name);
+	ret = snprintf(name, sizeof(name), "%s.cmd", autoconf_name);
+	if (ret >= sizeof(name)) /* check truncation */
+		return -1;
+
+	if (make_parent_dir(name))
+		return -1;
+
+	ret = snprintf(tmp, sizeof(tmp), "%s.cmd.tmp", autoconf_name);
+	if (ret >= sizeof(tmp)) /* check truncation */
+		return -1;
+
+	out = fopen(tmp, "w");
+	if (!out) {
+		perror("fopen");
+		return -1;
 	}
-	fprintf(out, "\n%s: \\\n"
-		     "\t$(deps_config)\n\n", conf_get_autoconfig_name());
 
-	env_write_dep(out, conf_get_autoconfig_name());
+	fprintf(out, "deps_config := \\\n");
+	for (file = file_list; file; file = file->next)
+		fprintf(out, "\t%s \\\n", file->name);
+
+	fprintf(out, "\n%s: $(deps_config)\n\n", autoconf_name);
+
+	env_write_dep(out, autoconf_name);
 
 	fprintf(out, "\n$(deps_config): ;\n");
+
+	fflush(out);
+	ret = ferror(out); /* error check for all fprintf() calls */
 	fclose(out);
+	if (ret)
+		return -1;
+
+	if (rename(tmp, name)) {
+		perror("rename");
+		return -1;
+	}
 
-	if (make_parent_dir(name))
-		return 1;
-	rename("..config.tmp", name);
 	return 0;
 }
 
 static int conf_touch_deps(void)
 {
-	const char *name;
+	const char *name, *tmp;
 	struct symbol *sym;
 	int res, i;
 
-	strcpy(depfile_path, "include/config/");
-	depfile_prefix_len = strlen(depfile_path);
-
 	name = conf_get_autoconfig_name();
+	tmp = strrchr(name, '/');
+	depfile_prefix_len = tmp ? tmp - name + 1 : 0;
+	if (depfile_prefix_len + 1 > sizeof(depfile_path))
+		return -1;
+
+	strncpy(depfile_path, name, depfile_prefix_len);
+	depfile_path[depfile_prefix_len] = 0;
+
 	conf_read_simple(name, S_DEF_AUTO);
 	sym_calc_value(modules_sym);
 
@@ -1056,13 +1153,54 @@ static int conf_touch_deps(void)
 	return 0;
 }
 
+static int __conf_write_autoconf(const char *filename,
+				 void (*print_symbol)(FILE *, struct symbol *),
+				 const struct comment_style *comment_style)
+{
+	char tmp[PATH_MAX];
+	FILE *file;
+	struct symbol *sym;
+	int ret, i;
+
+	if (make_parent_dir(filename))
+		return -1;
+
+	ret = snprintf(tmp, sizeof(tmp), "%s.tmp", filename);
+	if (ret >= sizeof(tmp)) /* check truncation */
+		return -1;
+
+	file = fopen(tmp, "w");
+	if (!file) {
+		perror("fopen");
+		return -1;
+	}
+
+	conf_write_heading(file, comment_style);
+
+	for_all_symbols(i, sym)
+		if ((sym->flags & SYMBOL_WRITE) && sym->name)
+			print_symbol(file, sym);
+
+	fflush(file);
+	/* check possible errors in conf_write_heading() and print_symbol() */
+	ret = ferror(file);
+	fclose(file);
+	if (ret)
+		return -1;
+
+	if (rename(tmp, filename)) {
+		perror("rename");
+		return -1;
+	}
+
+	return 0;
+}
+
 int conf_write_autoconf(int overwrite)
 {
 	struct symbol *sym;
-	const char *name;
 	const char *autoconf_name = conf_get_autoconfig_name();
-	FILE *out, *out_h;
-	int i;
+	int ret, i;
 
 #ifndef OPENWRT_DOES_NOT_WANT_THIS
 	return 0;
@@ -1070,52 +1208,38 @@ int conf_write_autoconf(int overwrite)
 	if (!overwrite && is_present(autoconf_name))
 		return 0;
 
-	conf_write_dep("include/config/auto.conf.cmd");
+	ret = conf_write_autoconf_cmd(autoconf_name);
+	if (ret)
+		return -1;
 
 	if (conf_touch_deps())
 		return 1;
 
-	out = fopen(".tmpconfig", "w");
-	if (!out)
-		return 1;
-
-	out_h = fopen(".tmpconfig.h", "w");
-	if (!out_h) {
-		fclose(out);
-		return 1;
-	}
-
-	conf_write_heading(out, &kconfig_printer_cb, NULL);
-	conf_write_heading(out_h, &header_printer_cb, NULL);
-
-	for_all_symbols(i, sym) {
+	for_all_symbols(i, sym)
 		sym_calc_value(sym);
-		if (!(sym->flags & SYMBOL_WRITE) || !sym->name)
-			continue;
 
-		/* write symbols to auto.conf and autoconf.h */
-		conf_write_symbol(out, sym, &kconfig_printer_cb, (void *)1);
-		conf_write_symbol(out_h, sym, &header_printer_cb, NULL);
-	}
-	fclose(out);
-	fclose(out_h);
+	ret = __conf_write_autoconf(conf_get_autoheader_name(),
+				    print_symbol_for_c,
+				    &comment_style_c);
+	if (ret)
+		return ret;
 
-	name = getenv("KCONFIG_AUTOHEADER");
-	if (!name)
-		name = "include/generated/autoconf.h";
-	if (make_parent_dir(name))
-		return 1;
-	if (rename(".tmpconfig.h", name))
-		return 1;
+	ret = __conf_write_autoconf(conf_get_rustccfg_name(),
+				    print_symbol_for_rustccfg,
+				    NULL);
+	if (ret)
+		return ret;
 
-	if (make_parent_dir(autoconf_name))
-		return 1;
 	/*
-	 * This must be the last step, kbuild has a dependency on auto.conf
-	 * and this marks the successful completion of the previous steps.
+	 * Create include/config/auto.conf. This must be the last step because
+	 * Kbuild has a dependency on auto.conf and this marks the successful
+	 * completion of the previous steps.
 	 */
-	if (rename(".tmpconfig", autoconf_name))
-		return 1;
+	ret = __conf_write_autoconf(conf_get_autoconfig_name(),
+				    print_symbol_for_autoconf,
+				    &comment_style_pound);
+	if (ret)
+		return ret;
 
 	return 0;
 }
@@ -1125,10 +1249,12 @@ static void (*conf_changed_callback)(void);
 
 void conf_set_changed(bool val)
 {
-	if (conf_changed_callback && conf_changed != val)
-		conf_changed_callback();
+	bool changed = conf_changed != val;
 
 	conf_changed = val;
+
+	if (conf_changed_callback && changed)
+		conf_changed_callback();
 }
 
 bool conf_get_changed(void)
diff --git a/scripts/config/expr.h b/scripts/config/expr.h
index c2fa804fe11402..005e27f130e16c 100644
--- a/scripts/config/expr.h
+++ b/scripts/config/expr.h
@@ -276,7 +276,6 @@ struct jump_key {
 	struct list_head entries;
 	size_t offset;
 	struct menu *target;
-	int index;
 };
 
 extern struct file *file_list;
diff --git a/scripts/config/lexer.l b/scripts/config/lexer.l
index 0df51ec468a7ab..e73b262539eb1a 100644
--- a/scripts/config/lexer.l
+++ b/scripts/config/lexer.l
@@ -86,8 +86,7 @@ static void warn_ignored_character(char chr)
 n	[A-Za-z0-9_-]
 
 %%
-	int str = 0;
-	int ts, i;
+	char open_quote = 0;
 
 #.*			/* ignore comment */
 [ \t]*			/* whitespaces */
@@ -137,7 +136,7 @@ n	[A-Za-z0-9_-]
 ":="			return T_COLON_EQUAL;
 "+="			return T_PLUS_EQUAL;
 \"|\'			{
-				str = yytext[0];
+				open_quote = yytext[0];
 				new_string();
 				BEGIN(STRING);
 			}
@@ -174,7 +173,7 @@ n	[A-Za-z0-9_-]
 		append_string(yytext + 1, yyleng - 1);
 	}
 	\'|\"	{
-		if (str == yytext[0]) {
+		if (open_quote == yytext[0]) {
 			BEGIN(INITIAL);
 			yylval.string = text;
 			return T_WORD_QUOTE;
@@ -199,6 +198,8 @@ n	[A-Za-z0-9_-]
 
 <HELP>{
 	[ \t]+	{
+		int ts, i;
+
 		ts = 0;
 		for (i = 0; i < yyleng; i++) {
 			if (yytext[i] == '\t')
diff --git a/scripts/config/lexer.lex.c b/scripts/config/lexer.lex.c
index 826c06e4e7bdd0..c57119fa235caa 100644
--- a/scripts/config/lexer.lex.c
+++ b/scripts/config/lexer.lex.c
@@ -14,6 +14,7 @@
 /* First, we deal with  platform-specific or compiler-specific issues. */
 
 /* begin standard C headers. */
+
 #include <stdio.h>
 #include <string.h>
 #include <errno.h>
@@ -30,8 +31,8 @@
 
 #if defined (__STDC_VERSION__) && __STDC_VERSION__ >= 199901L
 
-/* C99 says to define __STDC_LIMIT_MACROS before including stdint.h,
- * if you want the limit (max/min) macros for int types. 
+/* C++ systems might need __STDC_LIMIT_MACROS defined before including
+ * <stdint.h>, if you want the limit (max/min) macros for int types.
  */
 #ifndef __STDC_LIMIT_MACROS
 #define __STDC_LIMIT_MACROS 1
@@ -2538,8 +2539,7 @@ YY_DECL
 
 	{
 
-	int str = 0;
-	int ts, i;
+	char open_quote = 0;
 
 	while ( /*CONSTCOND*/1 )		/* loops until end-of-file is reached */
 		{
@@ -2772,7 +2772,7 @@ return T_PLUS_EQUAL;
 case 48:
 YY_RULE_SETUP
 {
-				str = yytext[0];
+				open_quote = yytext[0];
 				new_string();
 				BEGIN(STRING);
 			}
@@ -2837,7 +2837,7 @@ YY_RULE_SETUP
 case 58:
 YY_RULE_SETUP
 {
-		if (str == yytext[0]) {
+		if (open_quote == yytext[0]) {
 			BEGIN(INITIAL);
 			yylval.string = text;
 			return T_WORD_QUOTE;
@@ -2869,6 +2869,8 @@ case YY_STATE_EOF(STRING):
 case 60:
 YY_RULE_SETUP
 {
+		int ts, i;
+
 		ts = 0;
 		for (i = 0; i < yyleng; i++) {
 			if (yytext[i] == '\t')
diff --git a/scripts/config/lkc.h b/scripts/config/lkc.h
index a7b18b227635b7..1c8717de78e2c5 100644
--- a/scripts/config/lkc.h
+++ b/scripts/config/lkc.h
@@ -77,7 +77,7 @@ struct gstr str_new(void);
 void str_free(struct gstr *gs);
 void str_append(struct gstr *gs, const char *s);
 void str_printf(struct gstr *gs, const char *fmt, ...);
-const char *str_get(struct gstr *gs);
+char *str_get(struct gstr *gs);
 
 /* menu.c */
 void _menu_init(void);
@@ -100,10 +100,10 @@ bool menu_is_empty(struct menu *menu);
 bool menu_is_visible(struct menu *menu);
 bool menu_has_prompt(struct menu *menu);
 const char *menu_get_prompt(struct menu *menu);
-struct menu *menu_get_root_menu(struct menu *menu);
 struct menu *menu_get_parent_menu(struct menu *menu);
 bool menu_has_help(struct menu *menu);
 const char *menu_get_help(struct menu *menu);
+int get_jump_key_char(void);
 struct gstr get_relations_str(struct symbol **sym_arr, struct list_head *head);
 void menu_get_ext_help(struct menu *menu, struct gstr *help);
 
@@ -126,11 +126,6 @@ static inline struct symbol *sym_get_choice_value(struct symbol *sym)
 	return (struct symbol *)sym->curr.val;
 }
 
-static inline bool sym_set_choice_value(struct symbol *ch, struct symbol *chval)
-{
-	return sym_set_tristate_value(chval, yes);
-}
-
 static inline bool sym_is_choice(struct symbol *sym)
 {
 	return sym->flags & SYMBOL_CHOICE ? true : false;
diff --git a/scripts/config/lkc_proto.h b/scripts/config/lkc_proto.h
index ebedd230b32cc1..4babf6435a1980 100644
--- a/scripts/config/lkc_proto.h
+++ b/scripts/config/lkc_proto.h
@@ -19,7 +19,7 @@ extern struct symbol * symbol_hash[SYMBOL_HASHSIZE];
 
 struct symbol * sym_lookup(const char *name, int flags);
 struct symbol * sym_find(const char *name);
-const char * sym_escape_string_value(const char *in);
+void print_symbol_for_listconfig(struct symbol *sym);
 struct symbol ** sym_re_search(const char *pattern);
 const char * sym_type_name(enum symbol_type type);
 void sym_calc_value(struct symbol *sym);
diff --git a/scripts/config/lxdialog/dialog.h b/scripts/config/lxdialog/dialog.h
index 3930d93a4adf0d..3128bd6d7664d7 100644
--- a/scripts/config/lxdialog/dialog.h
+++ b/scripts/config/lxdialog/dialog.h
@@ -18,22 +18,6 @@
 #endif
 #include <ncurses.h>
 
-/*
- * Colors in ncurses 1.9.9e do not work properly since foreground and
- * background colors are OR'd rather than separately masked.  This version
- * of dialog was hacked to work with ncurses 1.9.9e, making it incompatible
- * with standard curses.  The simplest fix (to make this work with standard
- * curses) uses the wbkgdset() function, not used in the original hack.
- * Turn it off if we're building with 1.9.9e, since it just confuses things.
- */
-#if defined(NCURSES_VERSION) && defined(_NEED_WRAP) && !defined(GCC_PRINTFLIKE)
-#define OLD_NCURSES 1
-#undef  wbkgdset
-#define wbkgdset(w,p)		/*nothing */
-#else
-#define OLD_NCURSES 0
-#endif
-
 #define TR(params) _tracef params
 
 #define KEY_ESC 27
@@ -212,27 +196,12 @@ int first_alpha(const char *string, const char *exempt);
 int dialog_yesno(const char *title, const char *prompt, int height, int width);
 int dialog_msgbox(const char *title, const char *prompt, int height,
 		  int width, int pause);
-
-
-typedef void (*update_text_fn)(char *buf, size_t start, size_t end, void
-			       *_data);
-int dialog_textbox(const char *title, char *tbuf, int initial_height,
-		   int initial_width, int *keys, int *_vscroll, int *_hscroll,
-		   update_text_fn update_text, void *data);
+int dialog_textbox(const char *title, const char *tbuf, int initial_height,
+		   int initial_width, int *_vscroll, int *_hscroll,
+		   int (*extra_key_cb)(int, size_t, size_t, void *), void *data);
 int dialog_menu(const char *title, const char *prompt,
 		const void *selected, int *s_scroll);
 int dialog_checklist(const char *title, const char *prompt, int height,
 		     int width, int list_height);
 int dialog_inputbox(const char *title, const char *prompt, int height,
 		    int width, const char *init);
-
-/*
- * This is the base for fictitious keys, which activate
- * the buttons.
- *
- * Mouse-generated keys are the following:
- *   -- the first 32 are used as numbers, in addition to '0'-'9'
- *   -- the lowercase are used to signal mouse-enter events (M_EVENT + 'o')
- *   -- uppercase chars are used to invoke the button (M_EVENT + 'O')
- */
-#define M_EVENT (KEY_MAX+1)
diff --git a/scripts/config/lxdialog/menubox.c b/scripts/config/lxdialog/menubox.c
index 428774556674e6..bcdf3bbac99a8a 100644
--- a/scripts/config/lxdialog/menubox.c
+++ b/scripts/config/lxdialog/menubox.c
@@ -63,15 +63,7 @@ static void do_print_item(WINDOW * win, const char *item, int line_y,
 	/* Clear 'residue' of last item */
 	wattrset(win, dlg.menubox.atr);
 	wmove(win, line_y, 0);
-#if OLD_NCURSES
-	{
-		int i;
-		for (i = 0; i < menu_width; i++)
-			waddch(win, ' ');
-	}
-#else
 	wclrtoeol(win);
-#endif
 	wattrset(win, selected ? dlg.item_selected.atr : dlg.item.atr);
 	mvwaddstr(win, line_y, item_x, menu_item);
 	if (hotkey) {
diff --git a/scripts/config/lxdialog/textbox.c b/scripts/config/lxdialog/textbox.c
index b5987735b06cd5..e02acb7493100d 100644
--- a/scripts/config/lxdialog/textbox.c
+++ b/scripts/config/lxdialog/textbox.c
@@ -8,41 +8,149 @@
 
 #include "dialog.h"
 
-static void back_lines(int n);
-static void print_page(WINDOW *win, int height, int width, update_text_fn
-		       update_text, void *data);
-static void print_line(WINDOW *win, int row, int width);
-static char *get_line(void);
-static void print_position(WINDOW * win);
-
 static int hscroll;
 static int begin_reached, end_reached, page_length;
-static char *buf;
-static char *page;
+static const char *buf, *page;
+static size_t start, end;
+
+/*
+ * Go back 'n' lines in text. Called by dialog_textbox().
+ * 'page' will be updated to point to the desired line in 'buf'.
+ */
+static void back_lines(int n)
+{
+	int i;
+
+	begin_reached = 0;
+	/* Go back 'n' lines */
+	for (i = 0; i < n; i++) {
+		if (*page == '\0') {
+			if (end_reached) {
+				end_reached = 0;
+				continue;
+			}
+		}
+		if (page == buf) {
+			begin_reached = 1;
+			return;
+		}
+		page--;
+		do {
+			if (page == buf) {
+				begin_reached = 1;
+				return;
+			}
+			page--;
+		} while (*page != '\n');
+		page++;
+	}
+}
+
+/*
+ * Return current line of text. Called by dialog_textbox() and print_line().
+ * 'page' should point to start of current line before calling, and will be
+ * updated to point to start of next line.
+ */
+static char *get_line(void)
+{
+	int i = 0;
+	static char line[MAX_LEN + 1];
+
+	end_reached = 0;
+	while (*page != '\n') {
+		if (*page == '\0') {
+			end_reached = 1;
+			break;
+		} else if (i < MAX_LEN)
+			line[i++] = *(page++);
+		else {
+			/* Truncate lines longer than MAX_LEN characters */
+			if (i == MAX_LEN)
+				line[i++] = '\0';
+			page++;
+		}
+	}
+	if (i <= MAX_LEN)
+		line[i] = '\0';
+	if (!end_reached)
+		page++;		/* move past '\n' */
+
+	return line;
+}
+
+/*
+ * Print a new line of text.
+ */
+static void print_line(WINDOW *win, int row, int width)
+{
+	char *line;
+
+	line = get_line();
+	line += MIN(strlen(line), hscroll);	/* Scroll horizontally */
+	wmove(win, row, 0);	/* move cursor to correct line */
+	waddch(win, ' ');
+	waddnstr(win, line, MIN(strlen(line), width - 2));
+
+	/* Clear 'residue' of previous line */
+	wclrtoeol(win);
+}
+
+/*
+ * Print a new page of text.
+ */
+static void print_page(WINDOW *win, int height, int width)
+{
+	int i, passed_end = 0;
+
+	page_length = 0;
+	for (i = 0; i < height; i++) {
+		print_line(win, i, width);
+		if (!passed_end)
+			page_length++;
+		if (end_reached && !passed_end)
+			passed_end = 1;
+	}
+	wnoutrefresh(win);
+}
+
+/*
+ * Print current position
+ */
+static void print_position(WINDOW *win)
+{
+	int percent;
+
+	wattrset(win, dlg.position_indicator.atr);
+	wbkgdset(win, dlg.position_indicator.atr & A_COLOR);
+	percent = (page - buf) * 100 / strlen(buf);
+	wmove(win, getmaxy(win) - 3, getmaxx(win) - 9);
+	wprintw(win, "(%3d%%)", percent);
+}
 
 /*
  * refresh window content
  */
 static void refresh_text_box(WINDOW *dialog, WINDOW *box, int boxh, int boxw,
-			     int cur_y, int cur_x, update_text_fn update_text,
-			     void *data)
+			     int cur_y, int cur_x)
 {
-	print_page(box, boxh, boxw, update_text, data);
+	start = page - buf;
+
+	print_page(box, boxh, boxw);
 	print_position(dialog);
 	wmove(dialog, cur_y, cur_x);	/* Restore cursor position */
 	wrefresh(dialog);
-}
 
+	end = page - buf;
+}
 
 /*
  * Display text from a file in a dialog box.
  *
  * keys is a null-terminated array
- * update_text() may not add or remove any '\n' or '\0' in tbuf
  */
-int dialog_textbox(const char *title, char *tbuf, int initial_height,
-		   int initial_width, int *keys, int *_vscroll, int *_hscroll,
-		   update_text_fn update_text, void *data)
+int dialog_textbox(const char *title, const char *tbuf, int initial_height,
+		   int initial_width, int *_vscroll, int *_hscroll,
+		   int (*extra_key_cb)(int, size_t, size_t, void *), void *data)
 {
 	int i, x, y, cur_x, cur_y, key = 0;
 	int height, width, boxh, boxw;
@@ -122,8 +230,7 @@ int dialog_textbox(const char *title, char *tbuf, int initial_height,
 
 	/* Print first page of text */
 	attr_clear(box, boxh, boxw, dlg.dialog.atr);
-	refresh_text_box(dialog, box, boxh, boxw, cur_y, cur_x, update_text,
-			 data);
+	refresh_text_box(dialog, box, boxh, boxw, cur_y, cur_x);
 
 	while (!done) {
 		key = wgetch(dialog);
@@ -142,8 +249,7 @@ int dialog_textbox(const char *title, char *tbuf, int initial_height,
 				begin_reached = 1;
 				page = buf;
 				refresh_text_box(dialog, box, boxh, boxw,
-						 cur_y, cur_x, update_text,
-						 data);
+						 cur_y, cur_x);
 			}
 			break;
 		case 'G':	/* Last page */
@@ -153,8 +259,7 @@ int dialog_textbox(const char *title, char *tbuf, int initial_height,
 			/* point to last char in buf */
 			page = buf + strlen(buf);
 			back_lines(boxh);
-			refresh_text_box(dialog, box, boxh, boxw, cur_y,
-					 cur_x, update_text, data);
+			refresh_text_box(dialog, box, boxh, boxw, cur_y, cur_x);
 			break;
 		case 'K':	/* Previous line */
 		case 'k':
@@ -163,8 +268,7 @@ int dialog_textbox(const char *title, char *tbuf, int initial_height,
 				break;
 
 			back_lines(page_length + 1);
-			refresh_text_box(dialog, box, boxh, boxw, cur_y,
-					 cur_x, update_text, data);
+			refresh_text_box(dialog, box, boxh, boxw, cur_y, cur_x);
 			break;
 		case 'B':	/* Previous page */
 		case 'b':
@@ -173,8 +277,7 @@ int dialog_textbox(const char *title, char *tbuf, int initial_height,
 			if (begin_reached)
 				break;
 			back_lines(page_length + boxh);
-			refresh_text_box(dialog, box, boxh, boxw, cur_y,
-					 cur_x, update_text, data);
+			refresh_text_box(dialog, box, boxh, boxw, cur_y, cur_x);
 			break;
 		case 'J':	/* Next line */
 		case 'j':
@@ -183,8 +286,7 @@ int dialog_textbox(const char *title, char *tbuf, int initial_height,
 				break;
 
 			back_lines(page_length - 1);
-			refresh_text_box(dialog, box, boxh, boxw, cur_y,
-					 cur_x, update_text, data);
+			refresh_text_box(dialog, box, boxh, boxw, cur_y, cur_x);
 			break;
 		case KEY_NPAGE:	/* Next page */
 		case ' ':
@@ -193,8 +295,7 @@ int dialog_textbox(const char *title, char *tbuf, int initial_height,
 				break;
 
 			begin_reached = 0;
-			refresh_text_box(dialog, box, boxh, boxw, cur_y,
-					 cur_x, update_text, data);
+			refresh_text_box(dialog, box, boxh, boxw, cur_y, cur_x);
 			break;
 		case '0':	/* Beginning of line */
 		case 'H':	/* Scroll left */
@@ -209,8 +310,7 @@ int dialog_textbox(const char *title, char *tbuf, int initial_height,
 				hscroll--;
 			/* Reprint current page to scroll horizontally */
 			back_lines(page_length);
-			refresh_text_box(dialog, box, boxh, boxw, cur_y,
-					 cur_x, update_text, data);
+			refresh_text_box(dialog, box, boxh, boxw, cur_y, cur_x);
 			break;
 		case 'L':	/* Scroll right */
 		case 'l':
@@ -220,8 +320,7 @@ int dialog_textbox(const char *title, char *tbuf, int initial_height,
 			hscroll++;
 			/* Reprint current page to scroll horizontally */
 			back_lines(page_length);
-			refresh_text_box(dialog, box, boxh, boxw, cur_y,
-					 cur_x, update_text, data);
+			refresh_text_box(dialog, box, boxh, boxw, cur_y, cur_x);
 			break;
 		case KEY_ESC:
 			if (on_key_esc(dialog) == KEY_ESC)
@@ -234,11 +333,9 @@ int dialog_textbox(const char *title, char *tbuf, int initial_height,
 			on_key_resize();
 			goto do_resize;
 		default:
-			for (i = 0; keys[i]; i++) {
-				if (key == keys[i]) {
-					done = true;
-					break;
-				}
+			if (extra_key_cb && extra_key_cb(key, start, end, data)) {
+				done = true;
+				break;
 			}
 		}
 	}
@@ -259,137 +356,3 @@ int dialog_textbox(const char *title, char *tbuf, int initial_height,
 		*_hscroll = hscroll;
 	return key;
 }
-
-/*
- * Go back 'n' lines in text. Called by dialog_textbox().
- * 'page' will be updated to point to the desired line in 'buf'.
- */
-static void back_lines(int n)
-{
-	int i;
-
-	begin_reached = 0;
-	/* Go back 'n' lines */
-	for (i = 0; i < n; i++) {
-		if (*page == '\0') {
-			if (end_reached) {
-				end_reached = 0;
-				continue;
-			}
-		}
-		if (page == buf) {
-			begin_reached = 1;
-			return;
-		}
-		page--;
-		do {
-			if (page == buf) {
-				begin_reached = 1;
-				return;
-			}
-			page--;
-		} while (*page != '\n');
-		page++;
-	}
-}
-
-/*
- * Print a new page of text.
- */
-static void print_page(WINDOW *win, int height, int width, update_text_fn
-		       update_text, void *data)
-{
-	int i, passed_end = 0;
-
-	if (update_text) {
-		char *end;
-
-		for (i = 0; i < height; i++)
-			get_line();
-		end = page;
-		back_lines(height);
-		update_text(buf, page - buf, end - buf, data);
-	}
-
-	page_length = 0;
-	for (i = 0; i < height; i++) {
-		print_line(win, i, width);
-		if (!passed_end)
-			page_length++;
-		if (end_reached && !passed_end)
-			passed_end = 1;
-	}
-	wnoutrefresh(win);
-}
-
-/*
- * Print a new line of text.
- */
-static void print_line(WINDOW * win, int row, int width)
-{
-	char *line;
-
-	line = get_line();
-	line += MIN(strlen(line), hscroll);	/* Scroll horizontally */
-	wmove(win, row, 0);	/* move cursor to correct line */
-	waddch(win, ' ');
-	waddnstr(win, line, MIN(strlen(line), width - 2));
-
-	/* Clear 'residue' of previous line */
-#if OLD_NCURSES
-	{
-		int x = getcurx(win);
-		int i;
-		for (i = 0; i < width - x; i++)
-			waddch(win, ' ');
-	}
-#else
-	wclrtoeol(win);
-#endif
-}
-
-/*
- * Return current line of text. Called by dialog_textbox() and print_line().
- * 'page' should point to start of current line before calling, and will be
- * updated to point to start of next line.
- */
-static char *get_line(void)
-{
-	int i = 0;
-	static char line[MAX_LEN + 1];
-
-	end_reached = 0;
-	while (*page != '\n') {
-		if (*page == '\0') {
-			end_reached = 1;
-			break;
-		} else if (i < MAX_LEN)
-			line[i++] = *(page++);
-		else {
-			/* Truncate lines longer than MAX_LEN characters */
-			if (i == MAX_LEN)
-				line[i++] = '\0';
-			page++;
-		}
-	}
-	if (i <= MAX_LEN)
-		line[i] = '\0';
-	if (!end_reached)
-		page++;		/* move past '\n' */
-
-	return line;
-}
-
-/*
- * Print current position
- */
-static void print_position(WINDOW * win)
-{
-	int percent;
-
-	wattrset(win, dlg.position_indicator.atr);
-	wbkgdset(win, dlg.position_indicator.atr & A_COLOR);
-	percent = (page - buf) * 100 / strlen(buf);
-	wmove(win, getmaxy(win) - 3, getmaxx(win) - 9);
-	wprintw(win, "(%3d%%)", percent);
-}
diff --git a/scripts/config/mconf-cfg.sh b/scripts/config/mconf-cfg.sh
index 35723692880e6b..4e48cc1d57b8d7 100755
--- a/scripts/config/mconf-cfg.sh
+++ b/scripts/config/mconf-cfg.sh
@@ -1,19 +1,22 @@
 #!/bin/sh
 # SPDX-License-Identifier: GPL-2.0-only
 
+cflags=$1
+libs=$2
+
 PKG="ncursesw"
 PKG2="ncurses"
 
-if [ -n "$(command -v pkg-config)" ]; then
-	if pkg-config --exists $PKG; then
-		echo cflags=\"$(pkg-config --cflags $PKG)\"
-		echo libs=\"$(pkg-config --libs $PKG)\"
+if [ -n "$(command -v ${HOSTPKG_CONFIG})" ]; then
+	if ${HOSTPKG_CONFIG} --exists $PKG; then
+		${HOSTPKG_CONFIG} --cflags ${PKG} > ${cflags}
+		${HOSTPKG_CONFIG} --libs ${PKG} > ${libs}
 		exit 0
 	fi
 
-	if pkg-config --exists $PKG2; then
-		echo cflags=\"$(pkg-config --cflags $PKG2)\"
-		echo libs=\"$(pkg-config --libs $PKG2)\"
+	if ${HOSTPKG_CONFIG} --exists ${PKG2}; then
+		${HOSTPKG_CONFIG} --cflags ${PKG2} > ${cflags}
+		${HOSTPKG_CONFIG} --libs ${PKG2} > ${libs}
 		exit 0
 	fi
 fi
@@ -22,22 +25,22 @@ fi
 # (Even if it is installed, some distributions such as openSUSE cannot
 # find ncurses by pkg-config.)
 if [ -f /usr/include/ncursesw/ncurses.h ]; then
-	echo cflags=\"-D_GNU_SOURCE -I/usr/include/ncursesw\"
-	echo libs=\"-lncursesw\"
+	echo -D_GNU_SOURCE -I/usr/include/ncursesw > ${cflags}
+	echo -lncursesw > ${libs}
 	exit 0
 fi
 
 if [ -f /usr/include/ncurses/ncurses.h ]; then
-	echo cflags=\"-D_GNU_SOURCE -I/usr/include/ncurses\"
-	echo libs=\"-lncurses\"
+	echo -D_GNU_SOURCE -I/usr/include/ncurses > ${cflags}
+	echo -lncurses > ${libs}
 	exit 0
 fi
 
 # As a final fallback before giving up, check if $HOSTCC knows of a default
 # ncurses installation (e.g. from a vendor-specific sysroot).
 if echo '#include <ncurses.h>' | ${HOSTCC} -E - >/dev/null 2>&1; then
-	echo cflags=\"-D_GNU_SOURCE\"
-	echo libs=\"-lncurses\"
+	echo -D_GNU_SOURCE > ${cflags}
+	echo -lncurses > ${libs}
 	exit 0
 fi
 
@@ -46,7 +49,7 @@ echo >&2 "* Unable to find the ncurses package."
 echo >&2 "* Install ncurses (ncurses-devel or libncurses-dev"
 echo >&2 "* depending on your distribution)."
 echo >&2 "*"
-echo >&2 "* You may also need to install pkg-config to find the"
+echo >&2 "* You may also need to install ${HOSTPKG_CONFIG} to find the"
 echo >&2 "* ncurses installed in a non-default location."
 echo >&2 "*"
 exit 1
diff --git a/scripts/config/mconf.c b/scripts/config/mconf.c
index 81d232b66562bf..d357cf11003906 100644
--- a/scripts/config/mconf.c
+++ b/scripts/config/mconf.c
@@ -22,8 +22,6 @@
 #include "lkc.h"
 #include "lxdialog/dialog.h"
 
-#define JUMP_NB			9
-
 static const char mconf_readme[] =
 "OpenWrt config is based on Kernel kconfig\n"
 "so ipkg packages are referred here as modules.\n"
@@ -164,6 +162,12 @@ static const char mconf_readme[] =
 "(especially with a larger number of unrolled categories) than the\n"
 "default mode.\n"
 "\n"
+
+"Search\n"
+"-------\n"
+"Pressing the forward-slash (/) anywhere brings up a search dialog box.\n"
+"\n"
+
 "Different color themes available\n"
 "--------------------------------\n"
 "It is possible to select different color themes using the variable\n"
@@ -285,18 +289,9 @@ static int single_menu_mode;
 static int show_all_options;
 static int save_and_exit;
 static int silent;
+static int jump_key_char;
 
 static void conf(struct menu *menu, struct menu *active_menu);
-static void conf_choice(struct menu *menu);
-static void conf_string(struct menu *menu);
-static void conf_load(void);
-static void conf_save(void);
-static int show_textbox_ext(const char *title, char *text, int r, int c,
-			    int *keys, int *vscroll, int *hscroll,
-			    update_text_fn update_text, void *data);
-static void show_textbox(const char *title, const char *text, int r, int c);
-static void show_helptext(const char *title, const char *text);
-static void show_help(struct menu *menu);
 
 static char filename[PATH_MAX+1];
 static void set_config_filename(const char *config_filename)
@@ -355,37 +350,87 @@ static void reset_subtitle(void)
 	set_dialog_subtitles(subtitles);
 }
 
+static int show_textbox_ext(const char *title, const char *text, int r, int c,
+			    int *vscroll, int *hscroll,
+			    int (*extra_key_cb)(int, size_t, size_t, void *),
+			    void *data)
+{
+	dialog_clear();
+	return dialog_textbox(title, text, r, c, vscroll, hscroll,
+			      extra_key_cb, data);
+}
+
+static void show_textbox(const char *title, const char *text, int r, int c)
+{
+	show_textbox_ext(title, text, r, c, NULL, NULL, NULL, NULL);
+}
+
+static void show_helptext(const char *title, const char *text)
+{
+	show_textbox(title, text, 0, 0);
+}
+
+static void show_help(struct menu *menu)
+{
+	struct gstr help = str_new();
+
+	help.max_width = getmaxx(stdscr) - 10;
+	menu_get_ext_help(menu, &help);
+
+	show_helptext(menu_get_prompt(menu), str_get(&help));
+	str_free(&help);
+}
+
 struct search_data {
 	struct list_head *head;
-	struct menu **targets;
-	int *keys;
+	struct menu *target;
 };
 
-static void update_text(char *buf, size_t start, size_t end, void *_data)
+static int next_jump_key(int key)
+{
+	if (key < '1' || key > '9')
+		return '1';
+
+	key++;
+
+	if (key > '9')
+		key = '1';
+
+	return key;
+}
+
+static int handle_search_keys(int key, size_t start, size_t end, void *_data)
 {
 	struct search_data *data = _data;
 	struct jump_key *pos;
-	int k = 0;
+	int index = 0;
+
+	if (key < '1' || key > '9')
+		return 0;
 
 	list_for_each_entry(pos, data->head, entries) {
-		if (pos->offset >= start && pos->offset < end) {
-			char header[4];
+		index = next_jump_key(index);
 
-			if (k < JUMP_NB) {
-				int key = '0' + (pos->index % JUMP_NB) + 1;
+		if (pos->offset < start)
+			continue;
 
-				sprintf(header, "(%c)", key);
-				data->keys[k] = key;
-				data->targets[k] = pos->target;
-				k++;
-			} else {
-				sprintf(header, "   ");
-			}
+		if (pos->offset >= end)
+			break;
 
-			memcpy(buf + pos->offset, header, sizeof(header) - 1);
+		if (key == index) {
+			data->target = pos->target;
+			return 1;
 		}
 	}
-	data->keys[k] = 0;
+
+	return 0;
+}
+
+int get_jump_key_char(void)
+{
+	jump_key_char = next_jump_key(jump_key_char);
+
+	return jump_key_char;
 }
 
 static void search_conf(void)
@@ -432,27 +477,23 @@ static void search_conf(void)
 	sym_arr = sym_re_search(dialog_input);
 	do {
 		LIST_HEAD(head);
-		struct menu *targets[JUMP_NB];
-		int keys[JUMP_NB + 1], i;
 		struct search_data data = {
 			.head = &head,
-			.targets = targets,
-			.keys = keys,
 		};
 		struct jump_key *pos, *tmp;
 
+		jump_key_char = 0;
 		res = get_relations_str(sym_arr, &head);
 		set_subtitle();
-		dres = show_textbox_ext("Search Results", (char *)
-					str_get(&res), 0, 0, keys, &vscroll,
-					&hscroll, &update_text, (void *)
-					&data);
+		dres = show_textbox_ext("Search Results", str_get(&res), 0, 0,
+					&vscroll, &hscroll,
+					handle_search_keys, &data);
 		again = false;
-		for (i = 0; i < JUMP_NB && keys[i]; i++)
-			if (dres == keys[i]) {
-				conf(targets[i]->parent, targets[i]);
-				again = true;
-			}
+		if (dres >= '1' && dres <= '9') {
+			assert(data.target != NULL);
+			conf(data.target->parent, data.target);
+			again = true;
+		}
 		str_free(&res);
 		list_for_each_entry_safe(pos, tmp, &head, entries)
 			free(pos);
@@ -641,158 +682,6 @@ static void build_conf(struct menu *menu)
 	indent -= doint;
 }
 
-static void conf(struct menu *menu, struct menu *active_menu)
-{
-	struct menu *submenu;
-	const char *prompt = menu_get_prompt(menu);
-	struct subtitle_part stpart;
-	struct symbol *sym;
-	int res;
-	int s_scroll = 0;
-
-	if (menu != &rootmenu)
-		stpart.text = menu_get_prompt(menu);
-	else
-		stpart.text = NULL;
-	list_add_tail(&stpart.entries, &trail);
-
-	while (1) {
-		item_reset();
-		current_menu = menu;
-		build_conf(menu);
-		if (!child_count)
-			break;
-		set_subtitle();
-		dialog_clear();
-		res = dialog_menu(prompt ? prompt : "Main Menu",
-				  menu_instructions,
-				  active_menu, &s_scroll);
-		if (res == 1 || res == KEY_ESC || res == -ERRDISPLAYTOOSMALL)
-			break;
-		if (item_count() != 0) {
-			if (!item_activate_selected())
-				continue;
-			if (!item_tag())
-				continue;
-		}
-		submenu = item_data();
-		active_menu = item_data();
-		if (submenu)
-			sym = submenu->sym;
-		else
-			sym = NULL;
-
-		switch (res) {
-		case 0:
-			switch (item_tag()) {
-			case 'm':
-				if (single_menu_mode)
-					submenu->data = (void *) (long) !submenu->data;
-				else
-					conf(submenu, NULL);
-				break;
-			case 't':
-				if (sym_is_choice(sym) && sym_get_tristate_value(sym) == yes)
-					conf_choice(submenu);
-				else if (submenu->prompt->type == P_MENU)
-					conf(submenu, NULL);
-				break;
-			case 's':
-				conf_string(submenu);
-				break;
-			}
-			break;
-		case 2:
-			if (sym)
-				show_help(submenu);
-			else {
-				reset_subtitle();
-				show_helptext("README", mconf_readme);
-			}
-			break;
-		case 3:
-			reset_subtitle();
-			conf_save();
-			break;
-		case 4:
-			reset_subtitle();
-			conf_load();
-			break;
-		case 5:
-			if (item_is_tag('t')) {
-				if (sym_set_tristate_value(sym, yes))
-					break;
-				if (sym_set_tristate_value(sym, mod))
-					show_textbox(NULL, setmod_text, 6, 74);
-			}
-			break;
-		case 6:
-			if (item_is_tag('t'))
-				sym_set_tristate_value(sym, no);
-			break;
-		case 7:
-			if (item_is_tag('t'))
-				sym_set_tristate_value(sym, mod);
-			break;
-		case 8:
-			if (item_is_tag('t'))
-				sym_toggle_tristate_value(sym);
-			else if (item_is_tag('m'))
-				conf(submenu, NULL);
-			break;
-		case 9:
-			search_conf();
-			break;
-		case 10:
-			show_all_options = !show_all_options;
-			break;
-		}
-	}
-
-	list_del(trail.prev);
-}
-
-static int show_textbox_ext(const char *title, char *text, int r, int c, int
-			    *keys, int *vscroll, int *hscroll, update_text_fn
-			    update_text, void *data)
-{
-	dialog_clear();
-	return dialog_textbox(title, text, r, c, keys, vscroll, hscroll,
-			      update_text, data);
-}
-
-static void show_textbox(const char *title, const char *text, int r, int c)
-{
-	show_textbox_ext(title, (char *) text, r, c, (int []) {0}, NULL, NULL,
-			 NULL, NULL);
-}
-
-static void show_helptext(const char *title, const char *text)
-{
-	show_textbox(title, text, 0, 0);
-}
-
-static void conf_message_callback(const char *s)
-{
-	if (save_and_exit) {
-		if (!silent)
-			printf("%s", s);
-	} else {
-		show_textbox(NULL, s, 6, 60);
-	}
-}
-
-static void show_help(struct menu *menu)
-{
-	struct gstr help = str_new();
-
-	help.max_width = getmaxx(stdscr) - 10;
-	menu_get_ext_help(menu, &help);
-
-	show_helptext(menu_get_prompt(menu), str_get(&help));
-	str_free(&help);
-}
-
 static void conf_choice(struct menu *menu)
 {
 	const char *prompt = menu_get_prompt(menu);
@@ -958,6 +847,127 @@ static void conf_save(void)
 	}
 }
 
+static void conf(struct menu *menu, struct menu *active_menu)
+{
+	struct menu *submenu;
+	const char *prompt = menu_get_prompt(menu);
+	struct subtitle_part stpart;
+	struct symbol *sym;
+	int res;
+	int s_scroll = 0;
+
+	if (menu != &rootmenu)
+		stpart.text = menu_get_prompt(menu);
+	else
+		stpart.text = NULL;
+	list_add_tail(&stpart.entries, &trail);
+
+	while (1) {
+		item_reset();
+		current_menu = menu;
+		build_conf(menu);
+		if (!child_count)
+			break;
+		set_subtitle();
+		dialog_clear();
+		res = dialog_menu(prompt ? prompt : "Main Menu",
+				  menu_instructions,
+				  active_menu, &s_scroll);
+		if (res == 1 || res == KEY_ESC || res == -ERRDISPLAYTOOSMALL)
+			break;
+		if (item_count() != 0) {
+			if (!item_activate_selected())
+				continue;
+			if (!item_tag())
+				continue;
+		}
+		submenu = item_data();
+		active_menu = item_data();
+		if (submenu)
+			sym = submenu->sym;
+		else
+			sym = NULL;
+
+		switch (res) {
+		case 0:
+			switch (item_tag()) {
+			case 'm':
+				if (single_menu_mode)
+					submenu->data = (void *) (long) !submenu->data;
+				else
+					conf(submenu, NULL);
+				break;
+			case 't':
+				if (sym_is_choice(sym) && sym_get_tristate_value(sym) == yes)
+					conf_choice(submenu);
+				else if (submenu->prompt->type == P_MENU)
+					conf(submenu, NULL);
+				break;
+			case 's':
+				conf_string(submenu);
+				break;
+			}
+			break;
+		case 2:
+			if (sym)
+				show_help(submenu);
+			else {
+				reset_subtitle();
+				show_helptext("README", mconf_readme);
+			}
+			break;
+		case 3:
+			reset_subtitle();
+			conf_save();
+			break;
+		case 4:
+			reset_subtitle();
+			conf_load();
+			break;
+		case 5:
+			if (item_is_tag('t')) {
+				if (sym_set_tristate_value(sym, yes))
+					break;
+				if (sym_set_tristate_value(sym, mod))
+					show_textbox(NULL, setmod_text, 6, 74);
+			}
+			break;
+		case 6:
+			if (item_is_tag('t'))
+				sym_set_tristate_value(sym, no);
+			break;
+		case 7:
+			if (item_is_tag('t'))
+				sym_set_tristate_value(sym, mod);
+			break;
+		case 8:
+			if (item_is_tag('t'))
+				sym_toggle_tristate_value(sym);
+			else if (item_is_tag('m'))
+				conf(submenu, NULL);
+			break;
+		case 9:
+			search_conf();
+			break;
+		case 10:
+			show_all_options = !show_all_options;
+			break;
+		}
+	}
+
+	list_del(trail.prev);
+}
+
+static void conf_message_callback(const char *s)
+{
+	if (save_and_exit) {
+		if (!silent)
+			printf("%s", s);
+	} else {
+		show_textbox(NULL, s, 6, 60);
+	}
+}
+
 static int handle_exit(void)
 {
 	int res;
diff --git a/scripts/config/menu.c b/scripts/config/menu.c
index 22fd26a9f7147e..d41a61a73a490d 100644
--- a/scripts/config/menu.c
+++ b/scripts/config/menu.c
@@ -661,11 +661,6 @@ const char *menu_get_prompt(struct menu *menu)
 	return NULL;
 }
 
-struct menu *menu_get_root_menu(struct menu *menu)
-{
-	return &rootmenu;
-}
-
 struct menu *menu_get_parent_menu(struct menu *menu)
 {
 	enum prop_type type;
@@ -706,6 +701,11 @@ static void get_dep_str(struct gstr *r, struct expr *expr, const char *prefix)
 	}
 }
 
+int __attribute__((weak)) get_jump_key_char(void)
+{
+	return -1;
+}
+
 static void get_prompt_str(struct gstr *r, struct property *prop,
 			   struct list_head *head)
 {
@@ -727,52 +727,41 @@ static void get_prompt_str(struct gstr *r, struct property *prop,
 	if (!expr_eq(prop->menu->dep, prop->visible.expr))
 		get_dep_str(r, prop->visible.expr, "  Visible if: ");
 
-	menu = prop->menu->parent;
+	menu = prop->menu;
 	for (i = 0; menu != &rootmenu && i < 8; menu = menu->parent) {
-		bool accessible = menu_is_visible(menu);
-
 		submenu[i++] = menu;
-		if (location == NULL && accessible)
+		if (location == NULL && menu_is_visible(menu))
 			location = menu;
 	}
 	if (head && location) {
 		jump = xmalloc(sizeof(struct jump_key));
+		jump->target = location;
+		list_add_tail(&jump->entries, head);
+	}
 
-		if (menu_is_visible(prop->menu)) {
-			/*
-			 * There is not enough room to put the hint at the
-			 * beginning of the "Prompt" line. Put the hint on the
-			 * last "Location" line even when it would belong on
-			 * the former.
-			 */
-			jump->target = prop->menu;
-		} else
-			jump->target = location;
+	str_printf(r, "  Location:\n");
+	for (j = 0; --i >= 0; j++) {
+		int jk = -1;
+		int indent = 2 * j + 4;
 
-		if (list_empty(head))
-			jump->index = 0;
-		else
-			jump->index = list_entry(head->prev, struct jump_key,
-						 entries)->index + 1;
+		menu = submenu[i];
+		if (jump && menu == location) {
+			jump->offset = strlen(r->s);
+			jk = get_jump_key_char();
+		}
 
-		list_add_tail(&jump->entries, head);
-	}
+		if (jk >= 0) {
+			str_printf(r, "(%c)", jk);
+			indent -= 3;
+		}
 
-	if (i > 0) {
-		str_printf(r, "  Location:\n");
-		for (j = 4; --i >= 0; j += 2) {
-			menu = submenu[i];
-			if (jump && menu == location)
-				jump->offset = strlen(r->s);
-			str_printf(r, "%*c-> %s", j, ' ',
-				   menu_get_prompt(menu));
-			if (menu->sym) {
-				str_printf(r, " (%s [=%s])", menu->sym->name ?
-					menu->sym->name : "<choice>",
-					sym_get_string_value(menu->sym));
-			}
-			str_append(r, "\n");
+		str_printf(r, "%*c-> %s", indent, ' ', menu_get_prompt(menu));
+		if (menu->sym) {
+			str_printf(r, " (%s [=%s])", menu->sym->name ?
+				menu->sym->name : "<choice>",
+				sym_get_string_value(menu->sym));
 		}
+		str_append(r, "\n");
 	}
 }
 
diff --git a/scripts/config/nconf-cfg.sh b/scripts/config/nconf-cfg.sh
index a22730928397e3..9d4096074941e6 100755
--- a/scripts/config/nconf-cfg.sh
+++ b/scripts/config/nconf-cfg.sh
@@ -1,19 +1,22 @@
 #!/bin/sh
 # SPDX-License-Identifier: GPL-2.0-only
 
+cflags=$1
+libs=$2
+
 PKG="ncursesw menuw panelw"
 PKG2="ncurses menu panel"
 
-if [ -n "$(command -v pkg-config)" ]; then
-	if pkg-config --exists $PKG; then
-		echo cflags=\"$(pkg-config --cflags $PKG)\"
-		echo libs=\"$(pkg-config --libs $PKG)\"
+if [ -n "$(command -v ${HOSTPKG_CONFIG})" ]; then
+	if ${HOSTPKG_CONFIG} --exists $PKG; then
+		${HOSTPKG_CONFIG} --cflags ${PKG} > ${cflags}
+		${HOSTPKG_CONFIG} --libs ${PKG} > ${libs}
 		exit 0
 	fi
 
-	if pkg-config --exists $PKG2; then
-		echo cflags=\"$(pkg-config --cflags $PKG2)\"
-		echo libs=\"$(pkg-config --libs $PKG2)\"
+	if ${HOSTPKG_CONFIG} --exists $PKG2; then
+		${HOSTPKG_CONFIG} --cflags ${PKG2} > ${cflags}
+		${HOSTPKG_CONFIG} --libs ${PKG2} > ${libs}
 		exit 0
 	fi
 fi
@@ -22,20 +25,20 @@ fi
 # (Even if it is installed, some distributions such as openSUSE cannot
 # find ncurses by pkg-config.)
 if [ -f /usr/include/ncursesw/ncurses.h ]; then
-	echo cflags=\"-D_GNU_SOURCE -I/usr/include/ncursesw\"
-	echo libs=\"-lncursesw -lmenuw -lpanelw\"
+	echo -D_GNU_SOURCE -I/usr/include/ncursesw > ${cflags}
+	echo -lncursesw -lmenuw -lpanelw > ${libs}
 	exit 0
 fi
 
 if [ -f /usr/include/ncurses/ncurses.h ]; then
-	echo cflags=\"-D_GNU_SOURCE -I/usr/include/ncurses\"
-	echo libs=\"-lncurses -lmenu -lpanel\"
+	echo -D_GNU_SOURCE -I/usr/include/ncurses > ${cflags}
+	echo -lncurses -lmenu -lpanel > ${libs}
 	exit 0
 fi
 
 if [ -f /usr/include/ncurses.h ]; then
-	echo cflags=\"-D_GNU_SOURCE\"
-	echo libs=\"-lncurses -lmenu -lpanel\"
+	echo -D_GNU_SOURCE > ${cflags}
+	echo -lncurses -lmenu -lpanel > ${libs}
 	exit 0
 fi
 
@@ -44,7 +47,7 @@ echo >&2 "* Unable to find the ncurses package."
 echo >&2 "* Install ncurses (ncurses-devel or libncurses-dev"
 echo >&2 "* depending on your distribution)."
 echo >&2 "*"
-echo >&2 "* You may also need to install pkg-config to find the"
+echo >&2 "* You may also need to install ${HOSTPKG_CONFIG} to find the"
 echo >&2 "* ncurses installed in a non-default location."
 echo >&2 "*"
 exit 1
diff --git a/scripts/config/nconf.c b/scripts/config/nconf.c
index b75cabe017cabd..ece86726efd6ce 100644
--- a/scripts/config/nconf.c
+++ b/scripts/config/nconf.c
@@ -55,8 +55,8 @@ static const char nconf_global_help[] =
 "\n"
 "Menu navigation keys\n"
 "----------------------------------------------------------------------\n"
-"Linewise up                 <Up>\n"
-"Linewise down               <Down>\n"
+"Linewise up                 <Up>    <k>\n"
+"Linewise down               <Down>  <j>\n"
 "Pagewise up                 <Page Up>\n"
 "Pagewise down               <Page Down>\n"
 "First entry                 <Home>\n"
@@ -223,7 +223,7 @@ search_help[] =
 "Location:\n"
 "  -> Bus options (PCI, PCMCIA, EISA, ISA)\n"
 "    -> PCI support (PCI [ = y])\n"
-"      -> PCI access mode (<choice> [ = y])\n"
+"(1)   -> PCI access mode (<choice> [ = y])\n"
 "Selects: LIBCRC32\n"
 "Selected by: BAR\n"
 "-----------------------------------------------------------------\n"
@@ -234,9 +234,13 @@ search_help[] =
 "o  The 'Depends on:' line lists symbols that need to be defined for\n"
 "   this symbol to be visible and selectable in the menu.\n"
 "o  The 'Location:' lines tell, where in the menu structure this symbol\n"
-"   is located.  A location followed by a [ = y] indicates that this is\n"
-"   a selectable menu item, and the current value is displayed inside\n"
-"   brackets.\n"
+"   is located.\n"
+"     A location followed by a [ = y] indicates that this is\n"
+"     a selectable menu item, and the current value is displayed inside\n"
+"     brackets.\n"
+"     Press the key in the (#) prefix to jump directly to that\n"
+"     location. You will be returned to the current search results\n"
+"     after exiting this new menu.\n"
 "o  The 'Selects:' line tells, what symbol will be automatically selected\n"
 "   if this symbol is selected (y or m).\n"
 "o  The 'Selected by' line tells what symbol has selected this symbol.\n"
@@ -278,7 +282,9 @@ static const char *current_instructions = menu_instructions;
 
 static char *dialog_input_result;
 static int dialog_input_result_len;
+static int jump_key_char;
 
+static void selected_conf(struct menu *menu, struct menu *active_menu);
 static void conf(struct menu *menu);
 static void conf_choice(struct menu *menu);
 static void conf_string(struct menu *menu);
@@ -688,6 +694,57 @@ static int do_exit(void)
 	return 0;
 }
 
+struct search_data {
+	struct list_head *head;
+	struct menu *target;
+};
+
+static int next_jump_key(int key)
+{
+	if (key < '1' || key > '9')
+		return '1';
+
+	key++;
+
+	if (key > '9')
+		key = '1';
+
+	return key;
+}
+
+static int handle_search_keys(int key, size_t start, size_t end, void *_data)
+{
+	struct search_data *data = _data;
+	struct jump_key *pos;
+	int index = 0;
+
+	if (key < '1' || key > '9')
+		return 0;
+
+	list_for_each_entry(pos, data->head, entries) {
+		index = next_jump_key(index);
+
+		if (pos->offset < start)
+			continue;
+
+		if (pos->offset >= end)
+			break;
+
+		if (key == index) {
+			data->target = pos->target;
+			return 1;
+		}
+	}
+
+	return 0;
+}
+
+int get_jump_key_char(void)
+{
+	jump_key_char = next_jump_key(jump_key_char);
+
+	return jump_key_char;
+}
 
 static void search_conf(void)
 {
@@ -695,7 +752,8 @@ static void search_conf(void)
 	struct gstr res;
 	struct gstr title;
 	char *dialog_input;
-	int dres;
+	int dres, vscroll = 0, hscroll = 0;
+	bool again;
 
 	title = str_new();
 	str_printf( &title, "Enter (sub)string or regexp to search for "
@@ -724,11 +782,28 @@ static void search_conf(void)
 		dialog_input += strlen(CONFIG_);
 
 	sym_arr = sym_re_search(dialog_input);
-	res = get_relations_str(sym_arr, NULL);
+
+	do {
+		LIST_HEAD(head);
+		struct search_data data = {
+			.head = &head,
+			.target = NULL,
+		};
+		jump_key_char = 0;
+		res = get_relations_str(sym_arr, &head);
+		dres = show_scroll_win_ext(main_window,
+				"Search Results", str_get(&res),
+				&vscroll, &hscroll,
+				handle_search_keys, &data);
+		again = false;
+		if (dres >= '1' && dres <= '9') {
+			assert(data.target != NULL);
+			selected_conf(data.target->parent, data.target);
+			again = true;
+		}
+		str_free(&res);
+	} while (again);
 	free(sym_arr);
-	show_scroll_win(main_window,
-			"Search Results", str_get(&res));
-	str_free(&res);
 	str_free(&title);
 }
 
@@ -1065,10 +1140,15 @@ static int do_match(int key, struct match_state *state, int *ans)
 }
 
 static void conf(struct menu *menu)
+{
+	selected_conf(menu, NULL);
+}
+
+static void selected_conf(struct menu *menu, struct menu *active_menu)
 {
 	struct menu *submenu = NULL;
 	struct symbol *sym;
-	int res;
+	int i, res;
 	int current_index = 0;
 	int last_top_row = 0;
 	struct match_state match_state = {
@@ -1084,6 +1164,19 @@ static void conf(struct menu *menu)
 		if (!child_count)
 			break;
 
+		if (active_menu != NULL) {
+			for (i = 0; i < items_num; i++) {
+				struct mitem *mcur;
+
+				mcur = (struct mitem *) item_userptr(curses_menu_items[i]);
+				if ((struct menu *) mcur->usrptr == active_menu) {
+					current_index = i;
+					break;
+				}
+			}
+			active_menu = NULL;
+		}
+
 		show_menu(menu_get_prompt(menu), menu_instructions,
 			  current_index, &last_top_row);
 		keypad((menu_win(curses_menu)), TRUE);
@@ -1108,9 +1201,11 @@ static void conf(struct menu *menu)
 				break;
 			switch (res) {
 			case KEY_DOWN:
+			case 'j':
 				menu_driver(curses_menu, REQ_DOWN_ITEM);
 				break;
 			case KEY_UP:
+			case 'k':
 				menu_driver(curses_menu, REQ_UP_ITEM);
 				break;
 			case KEY_NPAGE:
@@ -1291,9 +1386,11 @@ static void conf_choice(struct menu *menu)
 				break;
 			switch (res) {
 			case KEY_DOWN:
+			case 'j':
 				menu_driver(curses_menu, REQ_DOWN_ITEM);
 				break;
 			case KEY_UP:
+			case 'k':
 				menu_driver(curses_menu, REQ_UP_ITEM);
 				break;
 			case KEY_NPAGE:
diff --git a/scripts/config/nconf.gui.c b/scripts/config/nconf.gui.c
index c72d61a7725e5a..48ba1c1a07f5ae 100644
--- a/scripts/config/nconf.gui.c
+++ b/scripts/config/nconf.gui.c
@@ -497,10 +497,17 @@ void refresh_all_windows(WINDOW *main_window)
 	refresh();
 }
 
-/* layman's scrollable window... */
 void show_scroll_win(WINDOW *main_window,
 		const char *title,
 		const char *text)
+{
+	(void)show_scroll_win_ext(main_window, title, (char *)text, NULL, NULL, NULL, NULL);
+}
+
+/* layman's scrollable window... */
+int show_scroll_win_ext(WINDOW *main_window, const char *title, char *text,
+			int *vscroll, int *hscroll,
+			extra_key_cb_fn extra_key_cb, void *data)
 {
 	int res;
 	int total_lines = get_line_no(text);
@@ -514,6 +521,12 @@ void show_scroll_win(WINDOW *main_window,
 	WINDOW *win;
 	WINDOW *pad;
 	PANEL *panel;
+	bool done = false;
+
+	if (hscroll)
+		start_x = *hscroll;
+	if (vscroll)
+		start_y = *vscroll;
 
 	getmaxyx(stdscr, lines, columns);
 
@@ -549,8 +562,7 @@ void show_scroll_win(WINDOW *main_window,
 	panel = new_panel(win);
 
 	/* handle scrolling */
-	do {
-
+	while (!done) {
 		copywin(pad, win, start_y, start_x, 2, 2, text_lines,
 				text_cols, 0);
 		print_in_middle(win,
@@ -593,8 +605,18 @@ void show_scroll_win(WINDOW *main_window,
 		case 'l':
 			start_x++;
 			break;
+		default:
+			if (extra_key_cb) {
+				size_t start = (get_line(text, start_y) - text);
+				size_t end = (get_line(text, start_y + text_lines) - text);
+
+				if (extra_key_cb(res, start, end, data)) {
+					done = true;
+					break;
+				}
+			}
 		}
-		if (res == 10 || res == 27 || res == 'q' ||
+		if (res == 0 || res == 10 || res == 27 || res == 'q' ||
 			res == KEY_F(F_HELP) || res == KEY_F(F_BACK) ||
 			res == KEY_F(F_EXIT))
 			break;
@@ -606,9 +628,14 @@ void show_scroll_win(WINDOW *main_window,
 			start_x = 0;
 		if (start_x >= total_cols-text_cols)
 			start_x = total_cols-text_cols;
-	} while (res);
+	}
 
+	if (hscroll)
+		*hscroll = start_x;
+	if (vscroll)
+		*vscroll = start_y;
 	del_panel(panel);
 	delwin(win);
 	refresh_all_windows(main_window);
+	return res;
 }
diff --git a/scripts/config/nconf.h b/scripts/config/nconf.h
index 6e127c63d5773a..174b035fdef105 100644
--- a/scripts/config/nconf.h
+++ b/scripts/config/nconf.h
@@ -67,6 +67,8 @@ typedef enum {
 
 void set_colors(void);
 
+typedef int (*extra_key_cb_fn)(int, size_t, size_t, void *);
+
 /* this changes the windows attributes !!! */
 void print_in_middle(WINDOW *win, int y, int width, const char *str, int attrs);
 int get_line_length(const char *line);
@@ -78,6 +80,9 @@ int dialog_inputbox(WINDOW *main_window,
 		const char *title, const char *prompt,
 		const char *init, char **resultp, int *result_len);
 void refresh_all_windows(WINDOW *main_window);
+int show_scroll_win_ext(WINDOW *main_window, const char *title, char *text,
+			int *vscroll, int *hscroll,
+			extra_key_cb_fn extra_key_cb, void *data);
 void show_scroll_win(WINDOW *main_window,
 		const char *title,
 		const char *text);
diff --git a/scripts/config/parser.tab.c b/scripts/config/parser.tab.c
index 18137050a9c2a3..93fdc257a603bb 100644
--- a/scripts/config/parser.tab.c
+++ b/scripts/config/parser.tab.c
@@ -1,4 +1,4 @@
-/* A Bison parser, made by GNU Bison 3.7.6.  */
+/* A Bison parser, made by GNU Bison 3.8.2.  */
 
 /* Bison implementation for Yacc-like parsers in C
 
@@ -46,10 +46,10 @@
    USER NAME SPACE" below.  */
 
 /* Identify Bison output, and Bison version.  */
-#define YYBISON 30706
+#define YYBISON 30802
 
 /* Bison version string.  */
-#define YYBISON_VERSION "3.7.6"
+#define YYBISON_VERSION "3.8.2"
 
 /* Skeleton name.  */
 #define YYSKELETON_NAME "yacc.c"
@@ -379,12 +379,18 @@ typedef int yy_state_fast_t;
 # define YY_USE(E) /* empty */
 #endif
 
-#if defined __GNUC__ && ! defined __ICC && 407 <= __GNUC__ * 100 + __GNUC_MINOR__
 /* Suppress an incorrect diagnostic about yylval being uninitialized.  */
-# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN                            \
+#if defined __GNUC__ && ! defined __ICC && 406 <= __GNUC__ * 100 + __GNUC_MINOR__
+# if __GNUC__ * 100 + __GNUC_MINOR__ < 407
+#  define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN                           \
+    _Pragma ("GCC diagnostic push")                                     \
+    _Pragma ("GCC diagnostic ignored \"-Wuninitialized\"")
+# else
+#  define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN                           \
     _Pragma ("GCC diagnostic push")                                     \
     _Pragma ("GCC diagnostic ignored \"-Wuninitialized\"")              \
     _Pragma ("GCC diagnostic ignored \"-Wmaybe-uninitialized\"")
+# endif
 # define YY_IGNORE_MAYBE_UNINITIALIZED_END      \
     _Pragma ("GCC diagnostic pop")
 #else
@@ -603,7 +609,7 @@ static const yytype_int8 yytranslate[] =
 };
 
 #if YYDEBUG
-  /* YYRLINE[YYN] -- Source line where rule number YYN was defined.  */
+/* YYRLINE[YYN] -- Source line where rule number YYN was defined.  */
 static const yytype_int16 yyrline[] =
 {
        0,   110,   110,   110,   114,   119,   121,   122,   123,   124,
@@ -661,20 +667,6 @@ yysymbol_name (yysymbol_kind_t yysymbol)
 }
 #endif
 
-#ifdef YYPRINT
-/* YYTOKNUM[NUM] -- (External) token number corresponding to the
-   (internal) symbol number NUM (which must be that of a token).  */
-static const yytype_int16 yytoknum[] =
-{
-       0,   256,   257,   258,   259,   260,   261,   262,   263,   264,
-     265,   266,   267,   268,   269,   270,   271,   272,   273,   274,
-     275,   276,   277,   278,   279,   280,   281,   282,   283,   284,
-     285,   286,   287,   288,   289,   290,   291,   292,   293,   294,
-     295,   296,   297,   298,   299,   300,   301,   302,   303,   304,
-     305
-};
-#endif
-
 #define YYPACT_NINF (-105)
 
 #define yypact_value_is_default(Yyn) \
@@ -685,8 +677,8 @@ static const yytype_int16 yytoknum[] =
 #define yytable_value_is_error(Yyn) \
   0
 
-  /* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing
-     STATE-NUM.  */
+/* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing
+   STATE-NUM.  */
 static const yytype_int16 yypact[] =
 {
       -5,    17,    37,  -105,    57,     8,  -105,    91,    39,    15,
@@ -710,9 +702,9 @@ static const yytype_int16 yypact[] =
     -105,   136,  -105,  -105,  -105,  -105,  -105
 };
 
-  /* YYDEFACT[STATE-NUM] -- Default reduction number in state STATE-NUM.
-     Performed when YYTABLE does not specify something else to do.  Zero
-     means the default is an error.  */
+/* YYDEFACT[STATE-NUM] -- Default reduction number in state STATE-NUM.
+   Performed when YYTABLE does not specify something else to do.  Zero
+   means the default is an error.  */
 static const yytype_int8 yydefact[] =
 {
        5,     0,     0,     5,     0,     0,     1,     0,     0,     0,
@@ -736,7 +728,7 @@ static const yytype_int8 yydefact[] =
       30,     0,    32,    31,    48,    44,    34
 };
 
-  /* YYPGOTO[NTERM-NUM].  */
+/* YYPGOTO[NTERM-NUM].  */
 static const yytype_int16 yypgoto[] =
 {
     -105,  -105,  -105,     3,    38,  -105,   -55,  -105,  -105,   138,
@@ -746,7 +738,7 @@ static const yytype_int16 yypgoto[] =
      -46,    -8,   -65,  -105,  -105,  -105,  -105
 };
 
-  /* YYDEFGOTO[NTERM-NUM].  */
+/* YYDEFGOTO[NTERM-NUM].  */
 static const yytype_uint8 yydefgoto[] =
 {
        0,     2,     3,     4,    57,    17,    18,    19,    20,    54,
@@ -756,9 +748,9 @@ static const yytype_uint8 yydefgoto[] =
       48,    49,    50,    41,    32,    39,    64
 };
 
-  /* YYTABLE[YYPACT[STATE-NUM]] -- What to do in state STATE-NUM.  If
-     positive, shift that token.  If negative, reduce the rule whose
-     number is the opposite.  If YYTABLE_NINF, syntax error.  */
+/* YYTABLE[YYPACT[STATE-NUM]] -- What to do in state STATE-NUM.  If
+   positive, shift that token.  If negative, reduce the rule whose
+   number is the opposite.  If YYTABLE_NINF, syntax error.  */
 static const yytype_int16 yytable[] =
 {
       68,    69,   116,   118,    44,   120,     7,    52,   134,   135,
@@ -807,8 +799,8 @@ static const yytype_int16 yycheck[] =
       34,    -1,    -1,    -1,    38
 };
 
-  /* YYSTOS[STATE-NUM] -- The (internal number of the) accessing
-     symbol of state STATE-NUM.  */
+/* YYSTOS[STATE-NUM] -- The symbol kind of the accessing symbol of
+   state STATE-NUM.  */
 static const yytype_int8 yystos[] =
 {
        0,    24,    52,    53,    54,     5,     0,    54,     1,     4,
@@ -832,7 +824,7 @@ static const yytype_int8 yystos[] =
       40,    90,    40,    40,    40,    40,    40
 };
 
-  /* YYR1[YYN] -- Symbol number of symbol that rule YYN derives.  */
+/* YYR1[RULE-NUM] -- Symbol kind of the left-hand side of rule RULE-NUM.  */
 static const yytype_int8 yyr1[] =
 {
        0,    51,    52,    52,    53,    54,    54,    54,    54,    54,
@@ -848,7 +840,7 @@ static const yytype_int8 yyr1[] =
       94,    95,    96,    96,    96,    97,    97
 };
 
-  /* YYR2[YYN] -- Number of symbols on the right hand side of rule YYN.  */
+/* YYR2[RULE-NUM] -- Number of symbols on the right-hand side of rule RULE-NUM.  */
 static const yytype_int8 yyr2[] =
 {
        0,     2,     2,     1,     3,     0,     2,     2,     2,     2,
@@ -873,6 +865,7 @@ enum { YYENOMEM = -2 };
 #define YYACCEPT        goto yyacceptlab
 #define YYABORT         goto yyabortlab
 #define YYERROR         goto yyerrorlab
+#define YYNOMEM         goto yyexhaustedlab
 
 
 #define YYRECOVERING()  (!!yyerrstatus)
@@ -913,10 +906,7 @@ do {                                            \
     YYFPRINTF Args;                             \
 } while (0)
 
-/* This macro is provided for backward compatibility. */
-# ifndef YY_LOCATION_PRINT
-#  define YY_LOCATION_PRINT(File, Loc) ((void) 0)
-# endif
+
 
 
 # define YY_SYMBOL_PRINT(Title, Kind, Value, Location)                    \
@@ -943,10 +933,6 @@ yy_symbol_value_print (FILE *yyo,
   YY_USE (yyoutput);
   if (!yyvaluep)
     return;
-# ifdef YYPRINT
-  if (yykind < YYNTOKENS)
-    YYPRINT (yyo, yytoknum[yykind], *yyvaluep);
-# endif
   YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN
   YY_USE (yykind);
   YY_IGNORE_MAYBE_UNINITIALIZED_END
@@ -1162,6 +1148,7 @@ yyparse (void)
   YYDPRINTF ((stderr, "Starting parse\n"));
 
   yychar = YYEMPTY; /* Cause a token to be read.  */
+
   goto yysetstate;
 
 
@@ -1187,7 +1174,7 @@ yyparse (void)
 
   if (yyss + yystacksize - 1 <= yyssp)
 #if !defined yyoverflow && !defined YYSTACK_RELOCATE
-    goto yyexhaustedlab;
+    YYNOMEM;
 #else
     {
       /* Get the current used size of the three stacks, in elements.  */
@@ -1215,7 +1202,7 @@ yyparse (void)
 # else /* defined YYSTACK_RELOCATE */
       /* Extend the stack our own way.  */
       if (YYMAXDEPTH <= yystacksize)
-        goto yyexhaustedlab;
+        YYNOMEM;
       yystacksize *= 2;
       if (YYMAXDEPTH < yystacksize)
         yystacksize = YYMAXDEPTH;
@@ -1226,7 +1213,7 @@ yyparse (void)
           YY_CAST (union yyalloc *,
                    YYSTACK_ALLOC (YY_CAST (YYSIZE_T, YYSTACK_BYTES (yystacksize))));
         if (! yyptr)
-          goto yyexhaustedlab;
+          YYNOMEM;
         YYSTACK_RELOCATE (yyss_alloc, yyss);
         YYSTACK_RELOCATE (yyvs_alloc, yyvs);
 #  undef YYSTACK_RELOCATE
@@ -1248,6 +1235,7 @@ yyparse (void)
     }
 #endif /* !defined yyoverflow && !defined YYSTACK_RELOCATE */
 
+
   if (yystate == YYFINAL)
     YYACCEPT;
 
@@ -1832,6 +1820,7 @@ yyparse (void)
      label yyerrorlab therefore never appears in user code.  */
   if (0)
     YYERROR;
+  ++yynerrs;
 
   /* Do not reclaim the symbols of the rule whose action triggered
      this YYERROR.  */
@@ -1892,7 +1881,7 @@ yyparse (void)
 `-------------------------------------*/
 yyacceptlab:
   yyresult = 0;
-  goto yyreturn;
+  goto yyreturnlab;
 
 
 /*-----------------------------------.
@@ -1900,24 +1889,22 @@ yyparse (void)
 `-----------------------------------*/
 yyabortlab:
   yyresult = 1;
-  goto yyreturn;
+  goto yyreturnlab;
 
 
-#if !defined yyoverflow
-/*-------------------------------------------------.
-| yyexhaustedlab -- memory exhaustion comes here.  |
-`-------------------------------------------------*/
+/*-----------------------------------------------------------.
+| yyexhaustedlab -- YYNOMEM (memory exhaustion) comes here.  |
+`-----------------------------------------------------------*/
 yyexhaustedlab:
   yyerror (YY_("memory exhausted"));
   yyresult = 2;
-  goto yyreturn;
-#endif
+  goto yyreturnlab;
 
 
-/*-------------------------------------------------------.
-| yyreturn -- parsing is finished, clean up and return.  |
-`-------------------------------------------------------*/
-yyreturn:
+/*----------------------------------------------------------.
+| yyreturnlab -- parsing is finished, clean up and return.  |
+`----------------------------------------------------------*/
+yyreturnlab:
   if (yychar != YYEMPTY)
     {
       /* Make sure we have latest lookahead translation.  See comments at
diff --git a/scripts/config/parser.tab.h b/scripts/config/parser.tab.h
index aac457ce39a899..fa3eb3491bd16e 100644
--- a/scripts/config/parser.tab.h
+++ b/scripts/config/parser.tab.h
@@ -1,4 +1,4 @@
-/* A Bison parser, made by GNU Bison 3.7.6.  */
+/* A Bison parser, made by GNU Bison 3.8.2.  */
 
 /* Bison interface for Yacc-like parsers in C
 
@@ -128,6 +128,8 @@ typedef union YYSTYPE YYSTYPE;
 
 extern YYSTYPE yylval;
 
+
 int yyparse (void);
 
+
 #endif /* !YY_YY_PARSER_TAB_H_INCLUDED  */
diff --git a/scripts/config/preprocess.c b/scripts/config/preprocess.c
index 3c7a35a724703a..3c544b775ae0aa 100644
--- a/scripts/config/preprocess.c
+++ b/scripts/config/preprocess.c
@@ -141,7 +141,7 @@ static char *do_lineno(int argc, char *argv[])
 static char *do_shell(int argc, char *argv[])
 {
 	FILE *p;
-	char buf[256];
+	char buf[4096];
 	char *cmd;
 	size_t nread;
 	int i;
@@ -396,6 +396,9 @@ static char *eval_clause(const char *str, size_t len, int argc, char *argv[])
 
 		p++;
 	}
+
+	if (new_argc >= FUNCTION_MAX_ARGS)
+		pperror("too many function arguments");
 	new_argv[new_argc++] = prev;
 
 	/*
diff --git a/scripts/config/qconf-cfg.sh b/scripts/config/qconf-cfg.sh
index 609bb818e8fec2..203ddf4203406a 100755
--- a/scripts/config/qconf-cfg.sh
+++ b/scripts/config/qconf-cfg.sh
@@ -1,24 +1,40 @@
 #!/bin/sh
 # SPDX-License-Identifier: GPL-2.0-only
 
-PKG="Qt5Core Qt5Gui Qt5Widgets"
+cflags=$1
+libs=$2
+bin=$3
 
-if [ -z "$(command -v pkg-config)" ]; then
+PKG5="Qt5Core Qt5Gui Qt5Widgets"
+PKG6="Qt6Core Qt6Gui Qt6Widgets"
+
+if [ -z "$(command -v ${HOSTPKG_CONFIG})" ]; then
 	echo >&2 "*"
-	echo >&2 "* 'make xconfig' requires 'pkg-config'. Please install it."
+	echo >&2 "* 'make xconfig' requires '${HOSTPKG_CONFIG}'. Please install it."
 	echo >&2 "*"
 	exit 1
 fi
 
-if pkg-config --exists $PKG; then
-	echo cflags=\"-std=c++11 -fPIC $(pkg-config --cflags $PKG)\"
-	echo libs=\"$(pkg-config --libs $PKG)\"
-	echo moc=\"$(pkg-config --variable=host_bins Qt5Core)/moc\"
+if ${HOSTPKG_CONFIG} --exists $PKG6; then
+	${HOSTPKG_CONFIG} --cflags ${PKG6} > ${cflags}
+	# Qt6 requires C++17.
+	echo -std=c++17 >> ${cflags}
+	${HOSTPKG_CONFIG} --libs ${PKG6} > ${libs}
+	${HOSTPKG_CONFIG} --variable=libexecdir Qt6Core > ${bin}
+	exit 0
+fi
+
+if ${HOSTPKG_CONFIG} --exists $PKG5; then
+	${HOSTPKG_CONFIG} --cflags ${PKG5} > ${cflags}
+	${HOSTPKG_CONFIG} --libs ${PKG5} > ${libs}
+	${HOSTPKG_CONFIG} --variable=host_bins Qt5Core > ${bin}
 	exit 0
 fi
 
 echo >&2 "*"
-echo >&2 "* Could not find Qt5 via pkg-config."
-echo >&2 "* Please install Qt5 and make sure it's in PKG_CONFIG_PATH"
+echo >&2 "* Could not find Qt6 or Qt5 via ${HOSTPKG_CONFIG}."
+echo >&2 "* Please install Qt6 or Qt5 and make sure it's in PKG_CONFIG_PATH"
+echo >&2 "* You need $PKG6 for Qt6"
+echo >&2 "* You need $PKG5 for Qt5"
 echo >&2 "*"
 exit 1
diff --git a/scripts/config/qconf.cc b/scripts/config/qconf.cc
index ed7b3e3e20e9b5..abf0d0b392b943 100644
--- a/scripts/config/qconf.cc
+++ b/scripts/config/qconf.cc
@@ -5,10 +5,10 @@
  */
 
 #include <QAction>
+#include <QActionGroup>
 #include <QApplication>
 #include <QCloseEvent>
 #include <QDebug>
-#include <QDesktopWidget>
 #include <QFileDialog>
 #include <QLabel>
 #include <QLayout>
@@ -16,6 +16,8 @@
 #include <QMenu>
 #include <QMenuBar>
 #include <QMessageBox>
+#include <QRegularExpression>
+#include <QScreen>
 #include <QToolBar>
 
 #include <stdlib.h>
@@ -1126,7 +1128,7 @@ QString ConfigInfoView::debug_info(struct symbol *sym)
 
 QString ConfigInfoView::print_filter(const QString &str)
 {
-	QRegExp re("[<>&\"\\n]");
+	QRegularExpression re("[<>&\"\\n]");
 	QString res = str;
 	for (int i = 0; (i = res.indexOf(re, i)) >= 0;) {
 		switch (res[i].toLatin1()) {
@@ -1322,15 +1324,15 @@ ConfigMainWindow::ConfigMainWindow(void)
 	int width, height;
 	char title[256];
 
-	QDesktopWidget *d = configApp->desktop();
 	snprintf(title, sizeof(title), "%s%s",
 		rootmenu.prompt->text,
 		""
 		);
 	setWindowTitle(title);
 
-	width = configSettings->value("/window width", d->width() - 64).toInt();
-	height = configSettings->value("/window height", d->height() - 64).toInt();
+	QRect g = configApp->primaryScreen()->geometry();
+	width = configSettings->value("/window width", g.width() - 64).toInt();
+	height = configSettings->value("/window height", g.height() - 64).toInt();
 	resize(width, height);
 	x = configSettings->value("/window x");
 	y = configSettings->value("/window y");
@@ -1379,17 +1381,17 @@ ConfigMainWindow::ConfigMainWindow(void)
 		this, &ConfigMainWindow::goBack);
 
 	QAction *quitAction = new QAction("&Quit", this);
-	quitAction->setShortcut(Qt::CTRL + Qt::Key_Q);
+	quitAction->setShortcut(Qt::CTRL | Qt::Key_Q);
 	connect(quitAction, &QAction::triggered,
 		this, &ConfigMainWindow::close);
 
 	QAction *loadAction = new QAction(QPixmap(xpm_load), "&Load", this);
-	loadAction->setShortcut(Qt::CTRL + Qt::Key_L);
+	loadAction->setShortcut(Qt::CTRL | Qt::Key_L);
 	connect(loadAction, &QAction::triggered,
 		this, &ConfigMainWindow::loadConfig);
 
 	saveAction = new QAction(QPixmap(xpm_save), "&Save", this);
-	saveAction->setShortcut(Qt::CTRL + Qt::Key_S);
+	saveAction->setShortcut(Qt::CTRL | Qt::Key_S);
 	connect(saveAction, &QAction::triggered,
 		this, &ConfigMainWindow::saveConfig);
 
@@ -1403,7 +1405,7 @@ ConfigMainWindow::ConfigMainWindow(void)
 	connect(saveAsAction, &QAction::triggered,
 		this, &ConfigMainWindow::saveConfigAs);
 	QAction *searchAction = new QAction("&Find", this);
-	searchAction->setShortcut(Qt::CTRL + Qt::Key_F);
+	searchAction->setShortcut(Qt::CTRL | Qt::Key_F);
 	connect(searchAction, &QAction::triggered,
 		this, &ConfigMainWindow::searchConfig);
 	singleViewAction = new QAction(QPixmap(xpm_single_view), "Single View", this);
@@ -1750,11 +1752,21 @@ void ConfigMainWindow::closeEvent(QCloseEvent* e)
 		e->accept();
 		return;
 	}
-	QMessageBox mb("qconf", "Save configuration?", QMessageBox::Warning,
-			QMessageBox::Yes | QMessageBox::Default, QMessageBox::No, QMessageBox::Cancel | QMessageBox::Escape);
-	mb.setButtonText(QMessageBox::Yes, "&Save Changes");
-	mb.setButtonText(QMessageBox::No, "&Discard Changes");
-	mb.setButtonText(QMessageBox::Cancel, "Cancel Exit");
+
+	QMessageBox mb(QMessageBox::Icon::Warning, "qconf",
+		       "Save configuration?");
+
+	QPushButton *yb = mb.addButton(QMessageBox::Yes);
+	QPushButton *db = mb.addButton(QMessageBox::No);
+	QPushButton *cb = mb.addButton(QMessageBox::Cancel);
+
+	yb->setText("&Save Changes");
+	db->setText("&Discard Changes");
+	cb->setText("Cancel Exit");
+
+	mb.setDefaultButton(yb);
+	mb.setEscapeButton(cb);
+
 	switch (mb.exec()) {
 	case QMessageBox::Yes:
 		if (saveConfig())
diff --git a/scripts/config/symbol.c b/scripts/config/symbol.c
index d97b56ab0ece7a..6ef44adc057e41 100644
--- a/scripts/config/symbol.c
+++ b/scripts/config/symbol.c
@@ -123,9 +123,9 @@ static long long sym_get_range_val(struct symbol *sym, int base)
 static void sym_validate_range(struct symbol *sym)
 {
 	struct property *prop;
+	struct symbol *range_sym;
 	int base;
 	long long val, val2;
-	char str[64];
 
 	switch (sym->type) {
 	case S_INT:
@@ -141,17 +141,15 @@ static void sym_validate_range(struct symbol *sym)
 	if (!prop)
 		return;
 	val = strtoll(sym->curr.val, NULL, base);
-	val2 = sym_get_range_val(prop->expr->left.sym, base);
+	range_sym = prop->expr->left.sym;
+	val2 = sym_get_range_val(range_sym, base);
 	if (val >= val2) {
-		val2 = sym_get_range_val(prop->expr->right.sym, base);
+		range_sym = prop->expr->right.sym;
+		val2 = sym_get_range_val(range_sym, base);
 		if (val <= val2)
 			return;
 	}
-	if (sym->type == S_INT)
-		sprintf(str, "%lld", val2);
-	else
-		sprintf(str, "0x%llx", val2);
-	sym->curr.val = xstrdup(str);
+	sym->curr.val = range_sym->curr.val;
 }
 
 static void sym_set_changed(struct symbol *sym)
@@ -851,49 +849,6 @@ struct symbol *sym_find(const char *name)
 	return symbol;
 }
 
-const char *sym_escape_string_value(const char *in)
-{
-	const char *p;
-	size_t reslen;
-	char *res;
-	size_t l;
-
-	reslen = strlen(in) + strlen("\"\"") + 1;
-
-	p = in;
-	for (;;) {
-		l = strcspn(p, "\"\\");
-		p += l;
-
-		if (p[0] == '\0')
-			break;
-
-		reslen++;
-		p++;
-	}
-
-	res = xmalloc(reslen);
-	res[0] = '\0';
-
-	strcat(res, "\"");
-
-	p = in;
-	for (;;) {
-		l = strcspn(p, "\"\\");
-		strncat(res, p, l);
-		p += l;
-
-		if (p[0] == '\0')
-			break;
-
-		strcat(res, "\\");
-		strncat(res, p++, 1);
-	}
-
-	strcat(res, "\"");
-	return res;
-}
-
 struct sym_match {
 	struct symbol	*sym;
 	off_t		so, eo;
diff --git a/scripts/config/util.c b/scripts/config/util.c
index 0bc415cd737e54..53e079e2e8af1a 100644
--- a/scripts/config/util.c
+++ b/scripts/config/util.c
@@ -74,7 +74,7 @@ void str_printf(struct gstr *gs, const char *fmt, ...)
 }
 
 /* Retrieve value of growable string */
-const char *str_get(struct gstr *gs)
+char *str_get(struct gstr *gs)
 {
 	return gs->s;
 }
diff --git a/scripts/get_source_date_epoch.sh b/scripts/get_source_date_epoch.sh
index d122acf385326b..727cb0372b0c5f 100755
--- a/scripts/get_source_date_epoch.sh
+++ b/scripts/get_source_date_epoch.sh
@@ -15,8 +15,8 @@ try_version() {
 }
 
 try_git() {
-	SOURCE_DATE_EPOCH=$(git -C "$SOURCE" log -1 --format=format:%ct \
-		"$SOURCE" 2>/dev/null)
+	SOURCE_DATE_EPOCH=$(git -C "$SOURCE" log -1 --no-show-signature \
+		--format=format:%ct "$SOURCE" 2>/dev/null)
 	[ -n "$SOURCE_DATE_EPOCH" ]
 }
 
diff --git a/scripts/package-metadata.pl b/scripts/package-metadata.pl
index 9e0e6dd9e58934..a46f819ab50f0f 100755
--- a/scripts/package-metadata.pl
+++ b/scripts/package-metadata.pl
@@ -677,6 +677,7 @@ ()
 		license => "GPL-2.0",
 		cpe_id  => "cpe:/o:linux:linux_kernel",
 		name    => "kernel",
+		category  => "operating-system",
 	};
 
 	my %abimap;
@@ -705,6 +706,7 @@ ()
 		if ($pkg->{category}) {
 			my $category = $pkg->{category};
 			my %cat_type = (
+				"operating-system"        => "operating-system",
 				"Firmware"        => "firmware",
 				"Libraries"       => "library"
 			);
diff --git a/scripts/patch-kernel.sh b/scripts/patch-kernel.sh
index c2b7e7204952f9..52750dde6edf19 100755
--- a/scripts/patch-kernel.sh
+++ b/scripts/patch-kernel.sh
@@ -1,4 +1,4 @@
-#! /bin/sh
+#!/bin/sh
 # A little script I whipped up to make it easy to
 # patch source trees and have sane error handling
 # -Erik
diff --git a/scripts/ubinize-image.sh b/scripts/ubinize-image.sh
index 323eae547abc1a..06a6310980177a 100755
--- a/scripts/ubinize-image.sh
+++ b/scripts/ubinize-image.sh
@@ -12,15 +12,16 @@ err=""
 ubinize_seq=""
 
 ubivol() {
-	volid=$1
-	name=$2
-	image=$3
-	autoresize=$4
-	size="$5"
+	local volid="$1"
+	local name="$2"
+	local image="$3"
+	local autoresize="$4"
+	local size="$5"
+	local voltype="${6:-dynamic}"
 	echo "[$name]"
 	echo "mode=ubi"
 	echo "vol_id=$volid"
-	echo "vol_type=dynamic"
+	echo "vol_type=$voltype"
 	echo "vol_name=$name"
 	if [ "$image" ]; then
 		echo "image=$image"
@@ -35,35 +36,47 @@ ubivol() {
 
 ubilayout() {
 	local vol_id=0
-	local rootsize=
-	local autoresize=
-	local rootfs_type="$( get_fs_type "$2" )"
+	local rootsize
+	local autoresize
+	local rootfs_type
+	local voltype
 
+	rootfs_type="$( get_fs_type "$2" )"
 	if [ "$1" = "ubootenv" ]; then
 		ubivol $vol_id ubootenv
-		vol_id=$(( $vol_id + 1 ))
+		vol_id=$(( vol_id + 1 ))
 		ubivol $vol_id ubootenv2
-		vol_id=$(( $vol_id + 1 ))
+		vol_id=$(( vol_id + 1 ))
 	fi
 	for part in $parts; do
 		name="${part%%=*}"
 		prev="$part"
 		part="${part#*=}"
+		voltype=dynamic
 		[ "$prev" = "$part" ] && part=
 
 		image="${part%%=*}"
+		if [ "${image#:}" != "$image" ]; then
+			voltype=static
+			image="${image#:}"
+		fi
 		prev="$part"
 		part="${part#*=}"
 		[ "$prev" = "$part" ] && part=
 
 		size="$part"
+		if [ -z "$size" ]; then
+			size="$( round_up "$( stat -c%s "$image" )" 1024 )"
+		else
+			size="${size}MiB"
+		fi
 
-		ubivol $vol_id "$name" "$image" "" "${size}MiB"
-		vol_id=$(( $vol_id + 1 ))
+		ubivol $vol_id "$name" "$image" "" "${size}" "$voltype"
+		vol_id=$(( vol_id + 1 ))
 	done
 	if [ "$3" ]; then
 		ubivol $vol_id kernel "$3"
-		vol_id=$(( $vol_id + 1 ))
+		vol_id=$(( vol_id + 1 ))
 	fi
 
 	if [ "$2" ]; then
@@ -77,10 +90,10 @@ ubilayout() {
 			rootsize="$( round_up "$( stat -c%s "$2" )" 1024 )"
 			;;
 		esac
-		ubivol $vol_id rootfs "$2" "$autoresize" "$rootsize"
+		ubivol $vol_id rootfs "$2" "$autoresize" "$rootsize" dynamic
 
-		vol_id=$(( $vol_id + 1 ))
-		[ "$rootfs_type" = "ubifs" ] || ubivol $vol_id rootfs_data "" 1
+		vol_id=$(( vol_id + 1 ))
+		[ "$rootfs_type" = "ubifs" ] || ubivol $vol_id rootfs_data "" 1 dymamic
 	fi
 }
 
@@ -116,7 +129,7 @@ while [ "$1" ]; do
 		continue
 		;;
 	"-"*)
-		ubinize_param="$@"
+		ubinize_param="$*"
 		break
 		;;
 	*)
@@ -129,7 +142,7 @@ while [ "$1" ]; do
 	esac
 done
 
-if [ ! -r "$rootfs" -a ! -r "$kernel" -a ! "$outfile" ]; then
+if [ ! -r "$rootfs" ] && [ ! -r "$kernel" ] && [ ! "$parts" ] && [ ! "$outfile" ]; then
 	echo "syntax: $0 [--uboot-env] [--part <name>=<file>] [--kernel kernelimage] [--rootfs rootfsimage] out [ubinize opts]"
 	exit 1
 fi
diff --git a/target/linux/Makefile b/target/linux/Makefile
index 8eea40ee18a6dd..eaf31982229677 100644
--- a/target/linux/Makefile
+++ b/target/linux/Makefile
@@ -7,5 +7,5 @@ include $(INCLUDE_DIR)/target.mk
 
 export TARGET_BUILD=1
 
-prereq clean download prepare compile install oldconfig menuconfig nconfig xconfig update refresh: FORCE
+prereq clean download prepare compile install oldconfig menuconfig nconfig xconfig update refresh dtb: FORCE
 	@+$(NO_TRACE_MAKE) -C $(firstword $(wildcard feeds/$(BOARD) $(BOARD))) $@
diff --git a/target/linux/airoha/Makefile b/target/linux/airoha/Makefile
index 723bec8cd434dc..5906a1307e02a9 100644
--- a/target/linux/airoha/Makefile
+++ b/target/linux/airoha/Makefile
@@ -7,6 +7,7 @@ CPU_TYPE:=cortex-a7
 FEATURES:=dt squashfs nand ramdisk gpio source-only
 
 KERNEL_PATCHVER:=5.15
+KERNEL_TESTING_PATCHVER:=6.1
 
 include $(INCLUDE_DIR)/target.mk
 
diff --git a/target/linux/airoha/config-6.1 b/target/linux/airoha/config-6.1
new file mode 100644
index 00000000000000..3402d779b2773d
--- /dev/null
+++ b/target/linux/airoha/config-6.1
@@ -0,0 +1,293 @@
+CONFIG_ALIGNMENT_TRAP=y
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_AIROHA=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MULTIPLATFORM=y
+CONFIG_ARCH_MULTI_V6_V7=y
+CONFIG_ARCH_MULTI_V7=y
+CONFIG_ARCH_NR_GPIO=0
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARM=y
+CONFIG_ARM_AMBA=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+CONFIG_ARM_CPU_SUSPEND=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_GIC_V3=y
+CONFIG_ARM_GIC_V3_ITS=y
+CONFIG_ARM_GIC_V3_ITS_PCI=y
+CONFIG_ARM_HAS_GROUP_RELOCS=y
+CONFIG_ARM_HEAVY_MB=y
+# CONFIG_ARM_HIGHBANK_CPUIDLE is not set
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+CONFIG_ARM_PATCH_IDIV=y
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_ARM_PSCI=y
+CONFIG_ARM_PSCI_FW=y
+# CONFIG_ARM_SMMU is not set
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_UNWIND=y
+CONFIG_ARM_VIRT_EXT=y
+CONFIG_ATAGS=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_PM=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_CACHE_L2X0=y
+CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
+CONFIG_CMDLINE_FROM_BOOTLOADER=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_EN7523=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_SPECTRE=y
+CONFIG_CPU_THUMB_CAPABLE=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_V7=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_ZSTD=y
+CONFIG_CURRENT_POINTER_IN_TPIDRURO=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+CONFIG_DEBUG_MISC=y
+CONFIG_DMA_OPS=y
+CONFIG_DTC=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC11_NO_ARRAY_BOUNDS=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MIGRATION=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_VDSO_32=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_EN7523=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_HARDEN_BRANCH_PREDICTOR=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HAVE_SMP=y
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HW_RANDOM=y
+CONFIG_HZ_FIXED=0
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_IOMMU_DEBUGFS is not set
+# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
+# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
+CONFIG_IOMMU_SUPPORT=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQSTACKS=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_TIME_ACCOUNTING=y
+CONFIG_IRQ_WORK=y
+# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MEMFD_CREATE=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
+CONFIG_MIGRATION=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTD_SPLIT_FIT_FW=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NLS=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NR_CPUS=2
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_NVMEM_SYSFS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_OUTER_CACHE=y
+CONFIG_OUTER_CACHE_SYNC=y
+CONFIG_PADATA=y
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
+CONFIG_PARTITION_PERCPU=y
+CONFIG_PCI=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_MEDIATEK=y
+CONFIG_PCIE_PME=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_MSI_IRQ_DOMAIN=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+CONFIG_PINCTRL=y
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_PWM=y
+CONFIG_PWM_SYSFS=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_SCSI=y
+CONFIG_SCSI_COMMON=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_FSL=y
+# CONFIG_SERIAL_8250_SHARE_IRQ is not set
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SG_POOL=y
+CONFIG_SMP=y
+CONFIG_SMP_ON_UP=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_AIROHA_EN7523=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SRCU=y
+CONFIG_STACKTRACE=y
+# CONFIG_SWAP is not set
+CONFIG_SWPHY=y
+CONFIG_SWP_EMULATE=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UBIFS_FS=y
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_UNWINDER_ARM=y
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_XHCI_HCD=y
+# CONFIG_USB_XHCI_PLATFORM is not set
+CONFIG_USE_OF=y
+# CONFIG_VFP is not set
+CONFIG_WATCHDOG_CORE=y
+# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZSTD_COMMON=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y
diff --git a/target/linux/airoha/dts/en7523.dtsi b/target/linux/airoha/dts/en7523.dtsi
index 72478b225cbb07..024a89752acbe8 100644
--- a/target/linux/airoha/dts/en7523.dtsi
+++ b/target/linux/airoha/dts/en7523.dtsi
@@ -157,7 +157,7 @@
 		clocks = <&scu EN7523_CLK_PCIE>;
 		clock-names = "sys_ck0";
 		bus-range = <0x00 0xff>;
-		ranges = <0x82000000 0 0x20000000  0x20000000  0 0x8000000>;
+		ranges = <0x82000000 0 0x20000000 0x20000000 0 0x2000000>;
 		status = "disabled";
 
 		#interrupt-cells = <1>;
@@ -186,7 +186,7 @@
 		clocks = <&scu EN7523_CLK_PCIE>;
 		clock-names = "sys_ck1";
 		bus-range = <0x00 0xff>;
-		ranges = <0x82000000 0 0x28000000  0x28000000  0 0x8000000>;
+		ranges = <0x82000000 0 0x22000000 0x22000000 0 0x2000000>;
 		status = "disabled";
 
 		#interrupt-cells = <1>;
diff --git a/target/linux/airoha/files/arch/arm/mach-airoha/Makefile b/target/linux/airoha/files-5.15/arch/arm/mach-airoha/Makefile
similarity index 100%
rename from target/linux/airoha/files/arch/arm/mach-airoha/Makefile
rename to target/linux/airoha/files-5.15/arch/arm/mach-airoha/Makefile
diff --git a/target/linux/airoha/files/arch/arm/mach-airoha/airoha.c b/target/linux/airoha/files-5.15/arch/arm/mach-airoha/airoha.c
similarity index 100%
rename from target/linux/airoha/files/arch/arm/mach-airoha/airoha.c
rename to target/linux/airoha/files-5.15/arch/arm/mach-airoha/airoha.c
diff --git a/target/linux/airoha/files/drivers/clk/clk-en7523.c b/target/linux/airoha/files-5.15/drivers/clk/clk-en7523.c
similarity index 100%
rename from target/linux/airoha/files/drivers/clk/clk-en7523.c
rename to target/linux/airoha/files-5.15/drivers/clk/clk-en7523.c
diff --git a/target/linux/airoha/files/drivers/gpio/gpio-en7523.c b/target/linux/airoha/files-5.15/drivers/gpio/gpio-en7523.c
similarity index 100%
rename from target/linux/airoha/files/drivers/gpio/gpio-en7523.c
rename to target/linux/airoha/files-5.15/drivers/gpio/gpio-en7523.c
diff --git a/target/linux/airoha/files/include/dt-bindings/clock/en7523-clk.h b/target/linux/airoha/files-5.15/include/dt-bindings/clock/en7523-clk.h
similarity index 100%
rename from target/linux/airoha/files/include/dt-bindings/clock/en7523-clk.h
rename to target/linux/airoha/files-5.15/include/dt-bindings/clock/en7523-clk.h
diff --git a/target/linux/airoha/patches-6.1/0005-spi-Add-support-for-the-Airoha-EN7523-SoC-SPI-contro.patch b/target/linux/airoha/patches-6.1/0005-spi-Add-support-for-the-Airoha-EN7523-SoC-SPI-contro.patch
new file mode 100644
index 00000000000000..dc28bd1df97a5e
--- /dev/null
+++ b/target/linux/airoha/patches-6.1/0005-spi-Add-support-for-the-Airoha-EN7523-SoC-SPI-contro.patch
@@ -0,0 +1,341 @@
+--- a/drivers/spi/Kconfig
++++ b/drivers/spi/Kconfig
+@@ -330,6 +330,12 @@ config SPI_DLN2
+ 	 This driver can also be built as a module.  If so, the module
+ 	 will be called spi-dln2.
+ 
++config SPI_AIROHA_EN7523
++	bool "Airoha EN7523 SPI controller support"
++	depends on ARCH_AIROHA
++	help
++	  This enables SPI controller support for the Airoha EN7523 SoC.
++
+ config SPI_EP93XX
+ 	tristate "Cirrus Logic EP93xx SPI controller"
+ 	depends on ARCH_EP93XX || COMPILE_TEST
+--- a/drivers/spi/Makefile
++++ b/drivers/spi/Makefile
+@@ -47,6 +47,7 @@ obj-$(CONFIG_SPI_DW_BT1)		+= spi-dw-bt1.
+ obj-$(CONFIG_SPI_DW_MMIO)		+= spi-dw-mmio.o
+ obj-$(CONFIG_SPI_DW_PCI)		+= spi-dw-pci.o
+ obj-$(CONFIG_SPI_EP93XX)		+= spi-ep93xx.o
++obj-$(CONFIG_SPI_AIROHA_EN7523)		+= spi-en7523.o
+ obj-$(CONFIG_SPI_FALCON)		+= spi-falcon.o
+ obj-$(CONFIG_SPI_FSI)			+= spi-fsi.o
+ obj-$(CONFIG_SPI_FSL_CPM)		+= spi-fsl-cpm.o
+--- /dev/null
++++ b/drivers/spi/spi-en7523.c
+@@ -0,0 +1,313 @@
++// SPDX-License-Identifier: GPL-2.0
++
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/mod_devicetable.h>
++#include <linux/spi/spi.h>
++
++
++#define ENSPI_READ_IDLE_EN			0x0004
++#define ENSPI_MTX_MODE_TOG			0x0014
++#define ENSPI_RDCTL_FSM				0x0018
++#define ENSPI_MANUAL_EN				0x0020
++#define ENSPI_MANUAL_OPFIFO_EMPTY		0x0024
++#define ENSPI_MANUAL_OPFIFO_WDATA		0x0028
++#define ENSPI_MANUAL_OPFIFO_FULL		0x002C
++#define ENSPI_MANUAL_OPFIFO_WR			0x0030
++#define ENSPI_MANUAL_DFIFO_FULL			0x0034
++#define ENSPI_MANUAL_DFIFO_WDATA		0x0038
++#define ENSPI_MANUAL_DFIFO_EMPTY		0x003C
++#define ENSPI_MANUAL_DFIFO_RD			0x0040
++#define ENSPI_MANUAL_DFIFO_RDATA		0x0044
++#define ENSPI_IER				0x0090
++#define ENSPI_NFI2SPI_EN			0x0130
++
++// TODO not in spi block
++#define ENSPI_CLOCK_DIVIDER			((void __iomem *)0x1fa201c4)
++
++#define	OP_CSH					0x00
++#define	OP_CSL					0x01
++#define	OP_CK					0x02
++#define	OP_OUTS					0x08
++#define	OP_OUTD					0x09
++#define	OP_OUTQ					0x0A
++#define	OP_INS					0x0C
++#define	OP_INS0					0x0D
++#define	OP_IND					0x0E
++#define	OP_INQ					0x0F
++#define	OP_OS2IS				0x10
++#define	OP_OS2ID				0x11
++#define	OP_OS2IQ				0x12
++#define	OP_OD2IS				0x13
++#define	OP_OD2ID				0x14
++#define	OP_OD2IQ				0x15
++#define	OP_OQ2IS				0x16
++#define	OP_OQ2ID				0x17
++#define	OP_OQ2IQ				0x18
++#define	OP_OSNIS				0x19
++#define	OP_ODNID				0x1A
++
++#define MATRIX_MODE_AUTO		1
++#define   CONF_MTX_MODE_AUTO		0
++#define   MANUALEN_AUTO			0
++#define MATRIX_MODE_MANUAL		0
++#define   CONF_MTX_MODE_MANUAL		9
++#define   MANUALEN_MANUAL		1
++
++#define _ENSPI_MAX_XFER			0x1ff
++
++#define REG(x)			(iobase + x)
++
++
++static void __iomem *iobase;
++
++
++static void opfifo_write(u32 cmd, u32 len)
++{
++	u32 tmp = ((cmd & 0x1f) << 9) | (len & 0x1ff);
++
++	writel(tmp, REG(ENSPI_MANUAL_OPFIFO_WDATA));
++
++	/* Wait for room in OPFIFO */
++	while (readl(REG(ENSPI_MANUAL_OPFIFO_FULL)))
++		;
++
++	/* Shift command into OPFIFO */
++	writel(1, REG(ENSPI_MANUAL_OPFIFO_WR));
++
++	/* Wait for command to finish */
++	while (!readl(REG(ENSPI_MANUAL_OPFIFO_EMPTY)))
++		;
++}
++
++static void set_cs(int state)
++{
++	if (state)
++		opfifo_write(OP_CSH, 1);
++	else
++		opfifo_write(OP_CSL, 1);
++}
++
++static void manual_begin_cmd(void)
++{
++	/* Disable read idle state */
++	writel(0, REG(ENSPI_READ_IDLE_EN));
++
++	/* Wait for FSM to reach idle state */
++	while (readl(REG(ENSPI_RDCTL_FSM)))
++		;
++
++	/* Set SPI core to manual mode */
++	writel(CONF_MTX_MODE_MANUAL, REG(ENSPI_MTX_MODE_TOG));
++	writel(MANUALEN_MANUAL, REG(ENSPI_MANUAL_EN));
++}
++
++static void manual_end_cmd(void)
++{
++	/* Set SPI core to auto mode */
++	writel(CONF_MTX_MODE_AUTO, REG(ENSPI_MTX_MODE_TOG));
++	writel(MANUALEN_AUTO, REG(ENSPI_MANUAL_EN));
++
++	/* Enable read idle state */
++	writel(1, REG(ENSPI_READ_IDLE_EN));
++}
++
++static void dfifo_read(u8 *buf, int len)
++{
++	int i;
++
++	for (i = 0; i < len; i++) {
++		/* Wait for requested data to show up in DFIFO */
++		while (readl(REG(ENSPI_MANUAL_DFIFO_EMPTY)))
++			;
++		buf[i] = readl(REG(ENSPI_MANUAL_DFIFO_RDATA));
++		/* Queue up next byte */
++		writel(1, REG(ENSPI_MANUAL_DFIFO_RD));
++	}
++}
++
++static void dfifo_write(const u8 *buf, int len)
++{
++	int i;
++
++	for (i = 0; i < len; i++) {
++		/* Wait for room in DFIFO */
++		while (readl(REG(ENSPI_MANUAL_DFIFO_FULL)))
++			;
++		writel(buf[i], REG(ENSPI_MANUAL_DFIFO_WDATA));
++	}
++}
++
++#if 0
++static void set_spi_clock_speed(int freq_mhz)
++{
++	u32 tmp, val;
++
++	tmp = readl(ENSPI_CLOCK_DIVIDER);
++	tmp &= 0xffff0000;
++	writel(tmp, ENSPI_CLOCK_DIVIDER);
++
++	val = (400 / (freq_mhz * 2));
++	tmp |= (val << 8) | 1;
++	writel(tmp, ENSPI_CLOCK_DIVIDER);
++}
++#endif
++
++static void init_hw(void)
++{
++	/* Disable manual/auto mode clash interrupt */
++	writel(0, REG(ENSPI_IER));
++
++	// TODO via clk framework
++	// set_spi_clock_speed(50);
++
++	/* Disable DMA */
++	writel(0, REG(ENSPI_NFI2SPI_EN));
++}
++
++static int xfer_read(struct spi_transfer *xfer)
++{
++	int opcode;
++	uint8_t *buf = xfer->rx_buf;
++
++	switch (xfer->rx_nbits) {
++	case SPI_NBITS_SINGLE:
++		opcode = OP_INS;
++		break;
++	case SPI_NBITS_DUAL:
++		opcode = OP_IND;
++		break;
++	case SPI_NBITS_QUAD:
++		opcode = OP_INQ;
++		break;
++	}
++
++	opfifo_write(opcode, xfer->len);
++	dfifo_read(buf, xfer->len);
++
++	return xfer->len;
++}
++
++static int xfer_write(struct spi_transfer *xfer, int next_xfer_is_rx)
++{
++	int opcode;
++	const uint8_t *buf = xfer->tx_buf;
++
++	if (next_xfer_is_rx) {
++		/* need to use Ox2Ix opcode to set the core to input afterwards */
++		switch (xfer->tx_nbits) {
++		case SPI_NBITS_SINGLE:
++			opcode = OP_OS2IS;
++			break;
++		case SPI_NBITS_DUAL:
++			opcode = OP_OS2ID;
++			break;
++		case SPI_NBITS_QUAD:
++			opcode = OP_OS2IQ;
++			break;
++		}
++	} else {
++		switch (xfer->tx_nbits) {
++		case SPI_NBITS_SINGLE:
++			opcode = OP_OUTS;
++			break;
++		case SPI_NBITS_DUAL:
++			opcode = OP_OUTD;
++			break;
++		case SPI_NBITS_QUAD:
++			opcode = OP_OUTQ;
++			break;
++		}
++	}
++
++	opfifo_write(opcode, xfer->len);
++	dfifo_write(buf, xfer->len);
++
++	return xfer->len;
++}
++
++size_t max_transfer_size(struct spi_device *spi)
++{
++	return _ENSPI_MAX_XFER;
++}
++
++int transfer_one_message(struct spi_controller *ctrl, struct spi_message *msg)
++{
++	struct spi_transfer *xfer;
++	int next_xfer_is_rx = 0;
++
++	manual_begin_cmd();
++	set_cs(0);
++	list_for_each_entry(xfer, &msg->transfers, transfer_list) {
++		if (xfer->tx_buf) {
++			if (!list_is_last(&xfer->transfer_list, &msg->transfers)
++			    && list_next_entry(xfer, transfer_list)->rx_buf != NULL)
++				next_xfer_is_rx = 1;
++			else
++				next_xfer_is_rx = 0;
++			msg->actual_length += xfer_write(xfer, next_xfer_is_rx);
++		} else if (xfer->rx_buf) {
++			msg->actual_length += xfer_read(xfer);
++		}
++	}
++	set_cs(1);
++	manual_end_cmd();
++
++	msg->status = 0;
++	spi_finalize_current_message(ctrl);
++
++	return 0;
++}
++
++static int spi_probe(struct platform_device *pdev)
++{
++	struct spi_controller *ctrl;
++	int err;
++
++	ctrl = devm_spi_alloc_master(&pdev->dev, 0);
++	if (!ctrl) {
++		dev_err(&pdev->dev, "Error allocating SPI controller\n");
++		return -ENOMEM;
++	}
++
++	iobase = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
++	if (IS_ERR(iobase)) {
++		dev_err(&pdev->dev, "Could not map SPI register address");
++		return -ENOMEM;
++	}
++
++	init_hw();
++
++	ctrl->dev.of_node = pdev->dev.of_node;
++	ctrl->flags = SPI_CONTROLLER_HALF_DUPLEX;
++	ctrl->mode_bits = SPI_RX_DUAL | SPI_TX_DUAL;
++	ctrl->max_transfer_size = max_transfer_size;
++	ctrl->transfer_one_message = transfer_one_message;
++	err = devm_spi_register_controller(&pdev->dev, ctrl);
++	if (err) {
++		dev_err(&pdev->dev, "Could not register SPI controller\n");
++		return -ENODEV;
++	}
++
++	return 0;
++}
++
++static const struct of_device_id spi_of_ids[] = {
++	{ .compatible = "airoha,en7523-spi" },
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, spi_of_ids);
++
++static struct platform_driver spi_driver = {
++	.probe = spi_probe,
++	.driver = {
++		.name = "airoha-en7523-spi",
++		.of_match_table = spi_of_ids,
++	},
++};
++
++module_platform_driver(spi_driver);
++
++MODULE_LICENSE("GPL v2");
++MODULE_AUTHOR("Bert Vermeulen <bert@biot.com>");
++MODULE_DESCRIPTION("Airoha EN7523 SPI driver");
diff --git a/target/linux/apm821xx/Makefile b/target/linux/apm821xx/Makefile
index e5e2841fd34afc..66bbf3ef474815 100644
--- a/target/linux/apm821xx/Makefile
+++ b/target/linux/apm821xx/Makefile
@@ -9,8 +9,7 @@ CPU_TYPE:=464fp
 FEATURES:=fpu dt gpio ramdisk squashfs usb
 SUBTARGETS:=nand sata
 
-KERNEL_PATCHVER:=5.15
-KERNEL_TESTING_PATCHVER:=6.1
+KERNEL_PATCHVER:=6.1
 
 define Target/Description
 	Build images for AppliedMicro APM821xx based boards.
diff --git a/target/linux/apm821xx/config-5.15 b/target/linux/apm821xx/config-5.15
deleted file mode 100644
index adcccbe567c26b..00000000000000
--- a/target/linux/apm821xx/config-5.15
+++ /dev/null
@@ -1,240 +0,0 @@
-# CONFIG_40x is not set
-CONFIG_44x=y
-CONFIG_4xx=y
-CONFIG_4xx_SOC=y
-# CONFIG_ADVANCED_OPTIONS is not set
-CONFIG_APM821xx=y
-# CONFIG_APOLLO3G is not set
-# CONFIG_ARCHES is not set
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MAY_HAVE_PC_FDC=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
-CONFIG_ARCH_MMAP_RND_BITS=11
-CONFIG_ARCH_MMAP_RND_BITS_MAX=17
-CONFIG_ARCH_MMAP_RND_BITS_MIN=11
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=17
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
-CONFIG_ARCH_STACKWALK=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_WEAK_RELEASE_ACQUIRE=y
-CONFIG_AUDIT_ARCH=y
-# CONFIG_BAMBOO is not set
-# CONFIG_BLK_DEV_INITRD is not set
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BLUESTONE=y
-CONFIG_BOOKE=y
-CONFIG_BOOKE_WDT=y
-# CONFIG_CANYONLANDS is not set
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="rootfstype=squashfs noinitrd"
-CONFIG_CMDLINE_FROM_BOOTLOADER=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CPU_BIG_ENDIAN=y
-CONFIG_CRC16=y
-# CONFIG_CRC32_SARWATE is not set
-CONFIG_CRC32_SLICEBY8=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_JITTERENTROPY=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1
-CONFIG_CRYPTO_LZO=y
-# CONFIG_CRYPTO_MD5_PPC is not set
-# CONFIG_CRYPTO_SHA1_PPC is not set
-CONFIG_DATA_SHIFT=12
-CONFIG_DMADEVICES=y
-CONFIG_DMA_DIRECT_REMAP=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_REMAP=y
-CONFIG_DTC=y
-CONFIG_DW_DMAC=y
-CONFIG_DW_DMAC_CORE=y
-CONFIG_EARLY_PRINTK=y
-# CONFIG_EBONY is not set
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-# CONFIG_EIGER is not set
-CONFIG_EXTRA_TARGETS="uImage"
-CONFIG_FIXED_PHY=y
-CONFIG_FORCE_PCI=y
-# CONFIG_FSL_LBC is not set
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_ISA_DMA=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-# CONFIG_GEN_RTC is not set
-# CONFIG_GLACIER is not set
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_GENERIC=y
-CONFIG_GPIO_GENERIC_PLATFORM=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_IBM_IIC=y
-CONFIG_IBM_EMAC=y
-CONFIG_IBM_EMAC_EMAC4=y
-CONFIG_IBM_EMAC_POLL_WEIGHT=32
-CONFIG_IBM_EMAC_RGMII=y
-CONFIG_IBM_EMAC_RXB=128
-CONFIG_IBM_EMAC_RX_COPY_THRESHOLD=256
-CONFIG_IBM_EMAC_TAH=y
-CONFIG_IBM_EMAC_TXB=128
-# CONFIG_ICON is not set
-CONFIG_ILLEGAL_POINTER_VALUE=0
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_ISA_DMA_API=y
-# CONFIG_JFFS2_FS is not set
-# CONFIG_KATMAI is not set
-CONFIG_KERNEL_START=0xc0000000
-CONFIG_LEDS_TRIGGER_MTD=y
-CONFIG_LEDS_TRIGGER_PATTERN=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOWMEM_SIZE=0x30000000
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-# CONFIG_MATH_EMULATION is not set
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MIGRATION=y
-CONFIG_MMU_GATHER_PAGE_SIZE=y
-CONFIG_MODULES_USE_ELF_RELA=y
-CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-# CONFIG_MTD_CFI_GEOMETRY is not set
-# CONFIG_MTD_SPLIT_SQUASHFS_ROOT is not set
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NOT_COHERENT_CACHE=y
-CONFIG_NO_HZ=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=1
-CONFIG_NR_IRQS=512
-CONFIG_NVMEM=y
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND=y
-CONFIG_PACKING=y
-CONFIG_PAGE_OFFSET=0xc0000000
-CONFIG_PCI=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_ARCH_FALLBACKS=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYSICAL_START=0x00000000
-CONFIG_PHYS_64BIT=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-# CONFIG_PMU_SYSFS is not set
-# CONFIG_POWERPC_CPU is not set
-CONFIG_PPC=y
-CONFIG_PPC32=y
-CONFIG_PPC44x_SIMPLE=y
-CONFIG_PPC4xx_GPIO=y
-CONFIG_PPC4xx_MSI=y
-CONFIG_PPC4xx_PCI_EXPRESS=y
-# CONFIG_PPC64 is not set
-# CONFIG_PPC_47x is not set
-# CONFIG_PPC_85xx is not set
-# CONFIG_PPC_8xx is not set
-CONFIG_PPC_ADV_DEBUG_DACS=2
-CONFIG_PPC_ADV_DEBUG_DAC_RANGE=y
-CONFIG_PPC_ADV_DEBUG_DVCS=2
-CONFIG_PPC_ADV_DEBUG_IACS=4
-CONFIG_PPC_ADV_DEBUG_REGS=y
-# CONFIG_PPC_BOOK3S_32 is not set
-CONFIG_PPC_DCR=y
-CONFIG_PPC_DCR_NATIVE=y
-# CONFIG_PPC_EARLY_DEBUG is not set
-CONFIG_PPC_FPU=y
-CONFIG_PPC_FPU_REGS=y
-CONFIG_PPC_HAVE_KUEP=y
-CONFIG_PPC_INDIRECT_PCI=y
-CONFIG_PPC_KUEP=y
-CONFIG_PPC_MMU_NOHASH=y
-CONFIG_PPC_MSI_BITMAP=y
-CONFIG_PPC_PAGE_SHIFT=12
-CONFIG_PPC_UDBG_16550=y
-CONFIG_PPC_WERROR=y
-CONFIG_PTE_64BIT=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-# CONFIG_RAINIER is not set
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-CONFIG_REGULATOR=y
-CONFIG_RSEQ=y
-# CONFIG_SAM440EP is not set
-# CONFIG_SCOM_DEBUGFS is not set
-# CONFIG_SEQUOIA is not set
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SRCU=y
-CONFIG_SWPHY=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-# CONFIG_TAISHAN is not set
-CONFIG_TASK_SIZE=0xc0000000
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_THREAD_SHIFT=13
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TINY_SRCU=y
-CONFIG_TOOLCHAIN_DEFAULT_CPU=y
-CONFIG_USB_SUPPORT=y
-CONFIG_VDSO32=y
-# CONFIG_VIRTIO_MENU is not set
-# CONFIG_VIRT_CPU_ACCOUNTING_NATIVE is not set
-# CONFIG_WARP is not set
-CONFIG_WATCHDOG_CORE=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_XZ_DEC_POWERPC=y
-# CONFIG_YOSEMITE is not set
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
diff --git a/target/linux/apm821xx/config-6.1 b/target/linux/apm821xx/config-6.1
index 2979312101b602..bde05e2f122b75 100644
--- a/target/linux/apm821xx/config-6.1
+++ b/target/linux/apm821xx/config-6.1
@@ -153,6 +153,7 @@ CONFIG_NR_CPUS=1
 CONFIG_NR_IRQS=512
 CONFIG_NVMEM=y
 CONFIG_NVMEM_SYSFS=y
+CONFIG_NVMEM_U_BOOT_ENV=y
 CONFIG_OF=y
 CONFIG_OF_ADDRESS=y
 CONFIG_OF_EARLY_FLATTREE=y
diff --git a/target/linux/apm821xx/dts/meraki-mr24.dts b/target/linux/apm821xx/dts/meraki-mr24.dts
index 14bedc59843c5b..a49a4de13fa1b3 100644
--- a/target/linux/apm821xx/dts/meraki-mr24.dts
+++ b/target/linux/apm821xx/dts/meraki-mr24.dts
@@ -63,10 +63,11 @@
 				 * blocks (64KiB) in order to have spares
 				 * around for bad block management
 				 */
-					label = "u-boot-env";
-					reg = <0x00150000 0x00010000>;
-					read-only;
-				};
+				label = "u-boot-env";
+				compatible = "u-boot,env";
+				reg = <0x00150000 0x00010000>;
+				read-only;
+			};
 
 			partition@160000 {
 				/*
diff --git a/target/linux/apm821xx/dts/meraki-mx60.dts b/target/linux/apm821xx/dts/meraki-mx60.dts
index 0e343ed7825e2b..d9568d92635b4d 100644
--- a/target/linux/apm821xx/dts/meraki-mx60.dts
+++ b/target/linux/apm821xx/dts/meraki-mx60.dts
@@ -61,6 +61,7 @@
 			partition@100000 {
 				label = "u-boot-env";
 				reg = <0x00100000 0x00100000>;
+				compatible = "u-boot,env";
 				read-only;
 			};
 
diff --git a/target/linux/apm821xx/dts/netgear-wndap6x0.dtsi b/target/linux/apm821xx/dts/netgear-wndap6x0.dtsi
index 144b17950e86a8..2921bfedb91370 100644
--- a/target/linux/apm821xx/dts/netgear-wndap6x0.dtsi
+++ b/target/linux/apm821xx/dts/netgear-wndap6x0.dtsi
@@ -47,11 +47,29 @@
 			};
 
 			partition@100000 {
+				compatible = "u-boot,env";
 				label = "u-boot-env";
-				reg = <0x00100000 0x00010000>;
+				reg = <0x00100000 0x0004000>;
 				read-only;
+
+				ethaddr {
+				};
+
+				bootcmd {
+				};
+
+				serno {
+				};
+
+				ProductID {
+				};
+
+				HardwareVer {
+				};
 			};
 
+			/* 0x104000 - 0x10ffff free */
+
 			partition@110000 {
 				label = "firmware";
 				reg = <0x00110000 0x01ac0000>;
diff --git a/target/linux/apm821xx/dts/wd-mybooklive.dts b/target/linux/apm821xx/dts/wd-mybooklive.dts
index 588f45078cd470..5ed865e286c849 100644
--- a/target/linux/apm821xx/dts/wd-mybooklive.dts
+++ b/target/linux/apm821xx/dts/wd-mybooklive.dts
@@ -21,30 +21,59 @@
 &POB0 {
 	ebc {
 		nor_flash@0,0 {
-			status = "okay";
-			compatible = "microchip,sst39vf040", "jedec-flash";
-			bank-width = <1>;
-			reg = <0x00000000 0x00000000 0x00080000>;
+		        status = "okay";
+		        compatible = "jedec-flash"; /* "microchip,sst39vf040 */
+		        bank-width = <1>;
+		        reg = <0x00000000 0x00000000 0x00080000>;
 			#address-cells = <1>;
 			#size-cells = <1>;
 
-			partition@0 {
-				/* Part of bootrom - Don't use it without a jump */
-				label = "free";
-				reg = <0x00000000 0x0001e000>;
-				read-only;
-			};
+			partitions {
+				compatible = "fixed-partitions";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				partition@0 {
+					/* Part of bootrom - Don't use it without a jump */
+					label = "free";
+					reg = <0x00000000 0x0001e000>;
+					read-only;
+				};
+
+				partition@1e000 {
+					compatible = "fixed-partitions";
+					reg = <0x0001e000 0x00002000>;
+					label = "u-boot-env";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					partition@0 {
+						compatible = "u-boot,env-redundant-bool";
+						reg = <0x00000000 0x00001000>;
+						label = "u-boot-env-1";
+
+						ethaddr {
+						};
+					};
+
+/*
+ * Causes the following warning: * sysfs: cannot create duplicate filename '/bus/nvmem/devices/u-boot-env0'
+ *
+ *					partition@1000 {
+ *						compatible = "u-boot,env-redundant-bool";
+ *						reg = <0x00001000 0x00001000>;
+ *						label = "u-boot-env-2";
+ *
+ *					};
+ */
+				};
 
-			partition@1e000 {
-				label = "env";
-				reg = <0x0001e000 0x00002000>;
-				read-only;
-			};
 
-			partition@20000 {
-				label = "uboot";
-				reg = <0x00020000 0x00050000>;
-				read-only;
+				partition@20000 {
+					label = "uboot";
+					reg = <0x00020000 0x00050000>;
+					read-only;
+				};
 			};
 		};
 	};
diff --git a/target/linux/apm821xx/patches-5.15/010-hwmon-tc654-add-thermal_cooling-device.patch b/target/linux/apm821xx/patches-5.15/010-hwmon-tc654-add-thermal_cooling-device.patch
deleted file mode 100644
index 74f8e38150f60a..00000000000000
--- a/target/linux/apm821xx/patches-5.15/010-hwmon-tc654-add-thermal_cooling-device.patch
+++ /dev/null
@@ -1,166 +0,0 @@
-From 4d49367c5303e3ebd17502a45b74de280f6be539 Mon Sep 17 00:00:00 2001
-From: Christian Lamparter <chunkeey@gmail.com>
-Date: Sun, 13 Feb 2022 01:47:33 +0100
-Subject: hwmon: (tc654) Add thermal_cooling device support
-
-Adds thermal_cooling device support to the tc654/tc655
-driver. This make it possible to integrate it into a
-device-tree supported thermal-zone node as a
-cooling device.
-
-I have been using this patch as part of the Netgear WNDR4700
-Centria NAS Router support within OpenWrt since 2016.
-
-Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
-Link: https://lore.kernel.org/r/20220213004733.2421193-1-chunkeey@gmail.com
-Signed-off-by: Guenter Roeck <linux@roeck-us.net>
----
---- a/drivers/hwmon/tc654.c
-+++ b/drivers/hwmon/tc654.c
-@@ -15,6 +15,7 @@
- #include <linux/module.h>
- #include <linux/mutex.h>
- #include <linux/slab.h>
-+#include <linux/thermal.h>
- #include <linux/util_macros.h>
- 
- enum tc654_regs {
-@@ -379,28 +380,20 @@ static ssize_t pwm_show(struct device *d
- 	return sprintf(buf, "%d\n", pwm);
- }
- 
--static ssize_t pwm_store(struct device *dev, struct device_attribute *da,
--			 const char *buf, size_t count)
-+static int _set_pwm(struct tc654_data *data, unsigned long val)
- {
--	struct tc654_data *data = dev_get_drvdata(dev);
- 	struct i2c_client *client = data->client;
--	unsigned long val;
- 	int ret;
- 
--	if (kstrtoul(buf, 10, &val))
--		return -EINVAL;
--	if (val > 255)
--		return -EINVAL;
--
- 	mutex_lock(&data->update_lock);
- 
--	if (val == 0)
-+	if (val == 0) {
- 		data->config |= TC654_REG_CONFIG_SDM;
--	else
-+		data->duty_cycle = 0;
-+	} else {
- 		data->config &= ~TC654_REG_CONFIG_SDM;
--
--	data->duty_cycle = find_closest(val, tc654_pwm_map,
--					ARRAY_SIZE(tc654_pwm_map));
-+		data->duty_cycle = val - 1;
-+	}
- 
- 	ret = i2c_smbus_write_byte_data(client, TC654_REG_CONFIG, data->config);
- 	if (ret < 0)
-@@ -411,6 +404,24 @@ static ssize_t pwm_store(struct device *
- 
- out:
- 	mutex_unlock(&data->update_lock);
-+	return ret;
-+}
-+
-+static ssize_t pwm_store(struct device *dev, struct device_attribute *da,
-+			 const char *buf, size_t count)
-+{
-+	struct tc654_data *data = dev_get_drvdata(dev);
-+	unsigned long val;
-+	int ret;
-+
-+	if (kstrtoul(buf, 10, &val))
-+		return -EINVAL;
-+	if (val > 255)
-+		return -EINVAL;
-+	if (val > 0)
-+		val = find_closest(val, tc654_pwm_map, ARRAY_SIZE(tc654_pwm_map)) + 1;
-+
-+	ret = _set_pwm(data, val);
- 	return ret < 0 ? ret : count;
- }
- 
-@@ -443,6 +454,58 @@ static struct attribute *tc654_attrs[] =
- ATTRIBUTE_GROUPS(tc654);
- 
- /*
-+ * thermal cooling device functions
-+ *
-+ * Account for the "ShutDown Mode (SDM)" state by offsetting
-+ * the 16 PWM duty cycle states by 1.
-+ *
-+ * State  0 =   0% PWM | Shutdown - Fan(s) are off
-+ * State  1 =  30% PWM | duty_cycle =  0
-+ * State  2 = ~35% PWM | duty_cycle =  1
-+ * [...]
-+ * State 15 = ~95% PWM | duty_cycle = 14
-+ * State 16 = 100% PWM | duty_cycle = 15
-+ */
-+#define TC654_MAX_COOLING_STATE	16
-+
-+static int tc654_get_max_state(struct thermal_cooling_device *cdev, unsigned long *state)
-+{
-+	*state = TC654_MAX_COOLING_STATE;
-+	return 0;
-+}
-+
-+static int tc654_get_cur_state(struct thermal_cooling_device *cdev, unsigned long *state)
-+{
-+	struct tc654_data *data = tc654_update_client(cdev->devdata);
-+
-+	if (IS_ERR(data))
-+		return PTR_ERR(data);
-+
-+	if (data->config & TC654_REG_CONFIG_SDM)
-+		*state = 0;	/* FAN is off */
-+	else
-+		*state = data->duty_cycle + 1;	/* offset PWM States by 1 */
-+
-+	return 0;
-+}
-+
-+static int tc654_set_cur_state(struct thermal_cooling_device *cdev, unsigned long state)
-+{
-+	struct tc654_data *data = tc654_update_client(cdev->devdata);
-+
-+	if (IS_ERR(data))
-+		return PTR_ERR(data);
-+
-+	return _set_pwm(data, clamp_val(state, 0, TC654_MAX_COOLING_STATE));
-+}
-+
-+static const struct thermal_cooling_device_ops tc654_fan_cool_ops = {
-+	.get_max_state = tc654_get_max_state,
-+	.get_cur_state = tc654_get_cur_state,
-+	.set_cur_state = tc654_set_cur_state,
-+};
-+
-+/*
-  * device probe and removal
-  */
- 
-@@ -472,7 +535,18 @@ static int tc654_probe(struct i2c_client
- 	hwmon_dev =
- 	    devm_hwmon_device_register_with_groups(dev, client->name, data,
- 						   tc654_groups);
--	return PTR_ERR_OR_ZERO(hwmon_dev);
-+	if (IS_ERR(hwmon_dev))
-+		return PTR_ERR(hwmon_dev);
-+
-+	if (IS_ENABLED(CONFIG_THERMAL)) {
-+		struct thermal_cooling_device *cdev;
-+
-+		cdev = devm_thermal_of_cooling_device_register(dev, dev->of_node, client->name,
-+							       hwmon_dev, &tc654_fan_cool_ops);
-+		return PTR_ERR_OR_ZERO(cdev);
-+	}
-+
-+	return 0;
- }
- 
- static const struct i2c_device_id tc654_id[] = {
diff --git a/target/linux/apm821xx/patches-5.15/201-add-amcc-apollo3g-support.patch b/target/linux/apm821xx/patches-5.15/201-add-amcc-apollo3g-support.patch
deleted file mode 100644
index e1889540947edc..00000000000000
--- a/target/linux/apm821xx/patches-5.15/201-add-amcc-apollo3g-support.patch
+++ /dev/null
@@ -1,30 +0,0 @@
---- a/arch/powerpc/platforms/44x/Kconfig
-+++ b/arch/powerpc/platforms/44x/Kconfig
-@@ -121,6 +121,17 @@ config CANYONLANDS
- 	help
- 	  This option enables support for the AMCC PPC460EX evaluation board.
- 
-+config APOLLO3G
-+	bool "Apollo3G"
-+	depends on 44x
-+	default n
-+	select PPC44x_SIMPLE
-+	select APM821xx
-+	select IBM_EMAC_RGMII
-+	select 460EX
-+	help
-+	  This option enables support for the AMCC Apollo 3G board.
-+
- config GLACIER
- 	bool "Glacier"
- 	depends on 44x
---- a/arch/powerpc/platforms/44x/ppc44x_simple.c
-+++ b/arch/powerpc/platforms/44x/ppc44x_simple.c
-@@ -47,6 +47,7 @@ machine_device_initcall(ppc44x_simple, p
-  * board.c file for it rather than adding it to this list.
-  */
- static char *board[] __initdata = {
-+	"amcc,apollo3g",
- 	"amcc,arches",
- 	"amcc,bamboo",
- 	"apm,bluestone",
diff --git a/target/linux/apm821xx/patches-5.15/300-fix-atheros-nics-on-apm82181.patch b/target/linux/apm821xx/patches-5.15/300-fix-atheros-nics-on-apm82181.patch
deleted file mode 100644
index 110726d258acb6..00000000000000
--- a/target/linux/apm821xx/patches-5.15/300-fix-atheros-nics-on-apm82181.patch
+++ /dev/null
@@ -1,51 +0,0 @@
---- a/arch/powerpc/platforms/4xx/pci.c
-+++ b/arch/powerpc/platforms/4xx/pci.c
-@@ -1060,15 +1060,24 @@ static int __init apm821xx_pciex_init_po
- 	u32 val;
- 
- 	/*
--	 * Do a software reset on PCIe ports.
--	 * This code is to fix the issue that pci drivers doesn't re-assign
--	 * bus number for PCIE devices after Uboot
--	 * scanned and configured all the buses (eg. PCIE NIC IntelPro/1000
--	 * PT quad port, SAS LSI 1064E)
-+	 * Only reset the PHY when no link is currently established.
-+	 * This is for the Atheros PCIe board which has problems to establish
-+	 * the link (again) after this PHY reset. All other currently tested
-+	 * PCIe boards don't show this problem.
- 	 */
--
--	mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x0);
--	mdelay(10);
-+	val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);
-+	if (!(val & 0x00001000)) {
-+		/*
-+		 * Do a software reset on PCIe ports.
-+		 * This code is to fix the issue that pci drivers doesn't re-assign
-+		 * bus number for PCIE devices after Uboot
-+		 * scanned and configured all the buses (eg. PCIE NIC IntelPro/1000
-+		 * PT quad port, SAS LSI 1064E)
-+		 */
-+
-+		mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x0);
-+		mdelay(10);
-+	}
- 
- 	if (port->endpoint)
- 		val = PTYPE_LEGACY_ENDPOINT << 20;
-@@ -1085,9 +1094,12 @@ static int __init apm821xx_pciex_init_po
- 	mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130);
- 	mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006);
- 
--	mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10000000);
--	mdelay(50);
--	mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30000000);
-+	val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);
-+	if (!(val & 0x00001000)) {
-+		mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10000000);
-+		mdelay(50);
-+		mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30000000);
-+	}
- 
- 	mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
- 		mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |
diff --git a/target/linux/apm821xx/patches-5.15/301-fix-memory-map-wndr4700.patch b/target/linux/apm821xx/patches-5.15/301-fix-memory-map-wndr4700.patch
deleted file mode 100644
index 452d97e85aa0e9..00000000000000
--- a/target/linux/apm821xx/patches-5.15/301-fix-memory-map-wndr4700.patch
+++ /dev/null
@@ -1,14 +0,0 @@
---- a/arch/powerpc/platforms/4xx/pci.c
-+++ b/arch/powerpc/platforms/4xx/pci.c
-@@ -1902,9 +1902,9 @@ static void __init ppc4xx_configure_pcie
- 		 * if it works
- 		 */
- 		out_le32(mbase + PECFG_PIM0LAL, 0x00000000);
--		out_le32(mbase + PECFG_PIM0LAH, 0x00000000);
-+		out_le32(mbase + PECFG_PIM0LAH, 0x00000008);
- 		out_le32(mbase + PECFG_PIM1LAL, 0x00000000);
--		out_le32(mbase + PECFG_PIM1LAH, 0x00000000);
-+		out_le32(mbase + PECFG_PIM1LAH, 0x0000000c);
- 		out_le32(mbase + PECFG_PIM01SAH, 0xffff0000);
- 		out_le32(mbase + PECFG_PIM01SAL, 0x00000000);
- 
diff --git a/target/linux/apm821xx/patches-5.15/900-powerpc-bootwrapper-force-gzip-as-mkimage-s-compress.patch b/target/linux/apm821xx/patches-5.15/900-powerpc-bootwrapper-force-gzip-as-mkimage-s-compress.patch
deleted file mode 100644
index 1ba8a45cb62ad9..00000000000000
--- a/target/linux/apm821xx/patches-5.15/900-powerpc-bootwrapper-force-gzip-as-mkimage-s-compress.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From c9395ad54e2cabb87d408becc37566f3d8248933 Mon Sep 17 00:00:00 2001
-From: Christian Lamparter <chunkeey@gmail.com>
-Date: Sun, 1 Dec 2019 02:08:23 +0100
-Subject: [PATCH] powerpc: bootwrapper: force gzip as mkimage's compression
- method
-
-Due to CONFIG_KERNEL_XZ symbol, the bootwrapper code tries to
-instruct the mkimage to use the xz compression, which isn't
-supported. This patch forces the gzip compression, which is
-supported and doesn't matter because the generated uImage for
-the apm821xx target gets ignored as the OpenWrt toolchain will
-do separate U-Boot kernel images for each device individually.
-
-Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
----
- arch/powerpc/boot/Makefile | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/powerpc/boot/Makefile
-+++ b/arch/powerpc/boot/Makefile
-@@ -258,7 +258,7 @@ compressor-$(CONFIG_KERNEL_LZO) := lzo
- 
- # args (to if_changed): 1 = (this rule), 2 = platform, 3 = dts 4=dtb 5=initrd
- quiet_cmd_wrap	= WRAP    $@
--      cmd_wrap	=$(CONFIG_SHELL) $(wrapper) -Z $(compressor-y) -c -o $@ -p $2 \
-+      cmd_wrap	=$(CONFIG_SHELL) $(wrapper) -Z gzip -c -o $@ -p $2 \
- 		$(CROSSWRAP) $(if $3, -s $3)$(if $4, -d $4)$(if $5, -i $5) \
- 		vmlinux
- 
diff --git a/target/linux/apm821xx/sata/config-default b/target/linux/apm821xx/sata/config-default
index daff2d04bef2bf..7efb914885f3bd 100644
--- a/target/linux/apm821xx/sata/config-default
+++ b/target/linux/apm821xx/sata/config-default
@@ -54,3 +54,9 @@ CONFIG_PPC4xx_CPM=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_SUSPEND=y
 CONFIG_SUSPEND_FREEZER=y
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_DWC2_HOST=y
+CONFIG_USB_ROLE_SWITCH=y
+CONFIG_USB_STORAGE=y
diff --git a/target/linux/ath79/dts/ar1022_sitecom_wlr-7100.dts b/target/linux/ath79/dts/ar1022_sitecom_wlr-7100.dts
index e2ccef105d6fb6..d2161e4a74e1d0 100644
--- a/target/linux/ath79/dts/ar1022_sitecom_wlr-7100.dts
+++ b/target/linux/ath79/dts/ar1022_sitecom_wlr-7100.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Sitecom WLR-7100 (X7 AC1200)";
@@ -41,7 +42,8 @@
 		};
 
 		led_power: power {
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
@@ -93,6 +95,8 @@
 	wifi@0,0 {
 		compatible = "qcom,ath10k";
 		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>;
+		nvmem-cell-names = "calibration";
 	};
 };
 
@@ -147,6 +151,16 @@
 				label = "art";
 				reg = <0x7f0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_5000: calibration@5000 {
+						reg = <0x5000 0x844>;
+					};
+				};
 			};
 		};
 	};
diff --git a/target/linux/ath79/dts/ar7161_adtran_bsap1880.dtsi b/target/linux/ath79/dts/ar7161_adtran_bsap1880.dtsi
index d7b961d8f63087..3075179b10c094 100644
--- a/target/linux/ath79/dts/ar7161_adtran_bsap1880.dtsi
+++ b/target/linux/ath79/dts/ar7161_adtran_bsap1880.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	chosen {
@@ -33,12 +34,14 @@
 		};
 
 		led_status_green: status_green {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status_yellow: status_yellow {
-			label = "yellow:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_YELLOW>;
 			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ath79/dts/ar7161_aruba_ap-105.dts b/target/linux/ath79/dts/ar7161_aruba_ap-105.dts
index dd110fc18591f0..5e727596439d3f 100644
--- a/target/linux/ath79/dts/ar7161_aruba_ap-105.dts
+++ b/target/linux/ath79/dts/ar7161_aruba_ap-105.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "aruba,ap-105", "qca,ar7161";
@@ -25,12 +26,14 @@
 		compatible = "gpio-leds";
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_red: power_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
 			panic-indicator;
 		};
diff --git a/target/linux/ath79/dts/ar7161_aruba_ap-175.dts b/target/linux/ath79/dts/ar7161_aruba_ap-175.dts
index 62a2083d20c4bd..3ec3a4fe6193b3 100644
--- a/target/linux/ath79/dts/ar7161_aruba_ap-175.dts
+++ b/target/linux/ath79/dts/ar7161_aruba_ap-175.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "aruba,ap-175", "qca,ar7161";
@@ -37,7 +38,8 @@
         /* These external LEDs are visible from the bottom panel */
 
 		led_power_amber: power_amber {
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio_ext 5 GPIO_ACTIVE_HIGH>;
 			panic-indicator;
 		};
diff --git a/target/linux/ath79/dts/ar7161_buffalo_wzr-hp-ag300h.dtsi b/target/linux/ath79/dts/ar7161_buffalo_wzr-hp-ag300h.dtsi
index 50c0748a384151..7219b0dacf234b 100644
--- a/target/linux/ath79/dts/ar7161_buffalo_wzr-hp-ag300h.dtsi
+++ b/target/linux/ath79/dts/ar7161_buffalo_wzr-hp-ag300h.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -30,7 +31,8 @@
 		};
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&ath9k0 3 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&usb_ohci_port>, <&usb_ehci_port>;
 			linux,default-trigger = "usbport";
diff --git a/target/linux/ath79/dts/ar7161_dlink_dir-825-b1.dts b/target/linux/ath79/dts/ar7161_dlink_dir-825-b1.dts
index 639736d9c45320..e6d2db57c080b5 100644
--- a/target/linux/ath79/dts/ar7161_dlink_dir-825-b1.dts
+++ b/target/linux/ath79/dts/ar7161_dlink_dir-825-b1.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "dlink,dir-825-b1", "qca,ar7161";
@@ -20,25 +21,29 @@
 		compatible = "gpio-leds";
 
 		usb {
-			label = "blue:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&usb_ohci_port>, <&usb_ehci_port>;
 			linux,default-trigger = "usbport";
 		};
 
 		led_power_orange: power_orange {
-			label = "orange:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		led_power_blue: power_blue {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
 		};
 
 		wps {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ath79/dts/ar7161_fortinet_fap-220-b.dts b/target/linux/ath79/dts/ar7161_fortinet_fap-220-b.dts
index e0aa5704cddc3d..b98239915edbfe 100644
--- a/target/linux/ath79/dts/ar7161_fortinet_fap-220-b.dts
+++ b/target/linux/ath79/dts/ar7161_fortinet_fap-220-b.dts
@@ -5,6 +5,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "fortinet,fap-220-b", "qca,ar7161";
@@ -36,18 +37,21 @@
 		compatible = "gpio-leds";
 
 		led_power: power-green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 4 GPIO_ACTIVE_HIGH>;
 			default-state = "on";
 		};
 
 		status-green {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
 		};
 
 		status-yellow {
-			label = "yellow:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_YELLOW>;
 			gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
 			panic-indicator;
 		};
diff --git a/target/linux/ath79/dts/ar7161_meraki_mr16.dts b/target/linux/ath79/dts/ar7161_meraki_mr16.dts
index b732010446f220..0353a558f98e02 100644
--- a/target/linux/ath79/dts/ar7161_meraki_mr16.dts
+++ b/target/linux/ath79/dts/ar7161_meraki_mr16.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "meraki,mr16", "qca,ar7161";
@@ -40,18 +41,21 @@
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_orange: power_orange {
-			label = "orange:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
 			panic-indicator;
 		};
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ath79/dts/ar7161_netgear_wndap360.dts b/target/linux/ath79/dts/ar7161_netgear_wndap360.dts
index 020b45d9e1d7bc..2acdba1c86de5a 100644
--- a/target/linux/ath79/dts/ar7161_netgear_wndap360.dts
+++ b/target/linux/ath79/dts/ar7161_netgear_wndap360.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "netgear,wndap360", "qca,ar7161";
@@ -20,7 +21,8 @@
 		compatible = "gpio-leds";
 
 		led_power_orange: power_orange {
-			label = "orange:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ath79/dts/ar7161_netgear_wndr.dtsi b/target/linux/ath79/dts/ar7161_netgear_wndr.dtsi
index d30b4dad308057..bc280976cb5ab8 100644
--- a/target/linux/ath79/dts/ar7161_netgear_wndr.dtsi
+++ b/target/linux/ath79/dts/ar7161_netgear_wndr.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/mtd/partitions/uimage.h>
 
 / {
@@ -18,7 +19,8 @@
 		compatible = "reset-leds";
 
 		usb_led {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			resets = <&rst 12>;
 			trigger-sources = <&usb_ohci_port>, <&usb_ehci_port>;
 			linux,default-trigger = "usbport";
@@ -29,28 +31,33 @@
 		compatible = "gpio-leds";
 
 		wps {
-			label = "orange:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_orange: power_orange {
-			label = "orange:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		wps_green {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
 		};
 
 		wan_green {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ath79/dts/ar7161_ruckus_gd11.dtsi b/target/linux/ath79/dts/ar7161_ruckus_gd11.dtsi
index 54a15c49c1bd3c..a80b6045b4ef3e 100644
--- a/target/linux/ath79/dts/ar7161_ruckus_gd11.dtsi
+++ b/target/linux/ath79/dts/ar7161_ruckus_gd11.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "ruckus,gd11", "qca,ar7161";
@@ -40,13 +41,15 @@
 		};
 
 		led_power_green: power-green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
 			default-state = "on";
 		};
 
 		led_power_red: power-red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
 			panic-indicator;
 		};
diff --git a/target/linux/ath79/dts/ar7161_siemens_ws-ap3610.dts b/target/linux/ath79/dts/ar7161_siemens_ws-ap3610.dts
index 56a2cfab67b916..a8ee7df0da3e9e 100644
--- a/target/linux/ath79/dts/ar7161_siemens_ws-ap3610.dts
+++ b/target/linux/ath79/dts/ar7161_siemens_ws-ap3610.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "siemens,ws-ap3610", "qca,ar7161";
@@ -21,12 +22,14 @@
 		compatible = "gpio-leds";
 
 		led_power_green: led_power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_red: led_power_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ath79/dts/ar7161_trendnet_tew-673gru.dts b/target/linux/ath79/dts/ar7161_trendnet_tew-673gru.dts
index 7508be1df1d9ec..d10c75c0d6708e 100644
--- a/target/linux/ath79/dts/ar7161_trendnet_tew-673gru.dts
+++ b/target/linux/ath79/dts/ar7161_trendnet_tew-673gru.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "trendnet,tew-673gru", "qca,ar7161";
@@ -20,7 +21,8 @@
 		compatible = "gpio-leds";
 
 		led_wps: wps {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ath79/dts/ar7240_buffalo_whr-g301n.dts b/target/linux/ath79/dts/ar7240_buffalo_whr-g301n.dts
index ad42e0a05fd210..d5ceb8b44ae20b 100644
--- a/target/linux/ath79/dts/ar7240_buffalo_whr-g301n.dts
+++ b/target/linux/ath79/dts/ar7240_buffalo_whr-g301n.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "buffalo,whr-g301n", "qca,ar7240";
@@ -90,7 +91,8 @@
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -99,7 +101,8 @@
 		compatible = "gpio-leds";
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&ath9k 1 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/ar7240_dlink_dir-615-e4.dts b/target/linux/ath79/dts/ar7240_dlink_dir-615-e4.dts
index abd298449b5a36..4a709395e968a7 100644
--- a/target/linux/ath79/dts/ar7240_dlink_dir-615-e4.dts
+++ b/target/linux/ath79/dts/ar7240_dlink_dir-615-e4.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "D-Link DIR-615 E4";
@@ -40,17 +41,20 @@
 		pinctrl-0 = <&switch_led_pins>;
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 6 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_power_amber: power_amber {
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
 		};
 
 		wps {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
 		};
 
@@ -75,12 +79,14 @@
 		};
 
 		wan_amber {
-			label = "amber:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
 		};
 
 		wan_green {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -89,7 +95,8 @@
 		compatible = "gpio-leds";
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&ath9k 1 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/ar7240_engenius_enh202-v1.dts b/target/linux/ath79/dts/ar7240_engenius_enh202-v1.dts
index ec3a3718506d06..11e9c6853fd4aa 100644
--- a/target/linux/ath79/dts/ar7240_engenius_enh202-v1.dts
+++ b/target/linux/ath79/dts/ar7240_engenius_enh202-v1.dts
@@ -5,6 +5,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "engenius,enh202-v1", "qca,ar7240";
@@ -50,12 +51,14 @@
 		};
 
 		lan {
-			label = "amber:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -64,7 +67,8 @@
 		compatible = "gpio-leds";
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&ath9k 1 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/ar7240_netgear_wnr1000-v2.dts b/target/linux/ath79/dts/ar7240_netgear_wnr1000-v2.dts
index 32903c2e8ff42c..bfee490051a138 100644
--- a/target/linux/ath79/dts/ar7240_netgear_wnr1000-v2.dts
+++ b/target/linux/ath79/dts/ar7240_netgear_wnr1000-v2.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/mtd/partitions/uimage.h>
 
 / {
@@ -55,23 +56,27 @@
 		pinctrl-0 = <&jtag_disable_pins &switch_led_disable_pins &clks_disable_pins>;
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_amber: power_amber {
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
 			default-state = "keep";
 		};
 
 		wan_green {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
 		};
 
 		wan_amber {
-			label = "amber:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
 		};
 
@@ -120,12 +125,14 @@
 		compatible = "gpio-leds";
 
 		wps_green {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&ath9k 5 GPIO_ACTIVE_LOW>;
 		};
 
 		wlan_blue {
-			label = "blue:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&ath9k 1 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/ar7240_netgear_wnr612-v2.dtsi b/target/linux/ath79/dts/ar7240_netgear_wnr612-v2.dtsi
index ac27874c68ab7b..c197a90ec5aaac 100644
--- a/target/linux/ath79/dts/ar7240_netgear_wnr612-v2.dtsi
+++ b/target/linux/ath79/dts/ar7240_netgear_wnr612-v2.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/mtd/partitions/uimage.h>
 
 / {
@@ -34,7 +35,8 @@
 		pinctrl-0 = <&jtag_disable_pins &switch_led_disable_pins &clks_disable_pins>;
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 		};
 
@@ -49,7 +51,8 @@
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -58,7 +61,8 @@
 		compatible = "gpio-leds";
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&ath9k 1 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/ar7240_openmesh_om2p-v1.dts b/target/linux/ath79/dts/ar7240_openmesh_om2p-v1.dts
index 17a57446618712..673e9b740b6f06 100644
--- a/target/linux/ath79/dts/ar7240_openmesh_om2p-v1.dts
+++ b/target/linux/ath79/dts/ar7240_openmesh_om2p-v1.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "openmesh,om2p-v1", "qca,ar7240";
@@ -38,7 +39,8 @@
 		pinctrl-0 = <&switch_led_disable_pins>;
 
 		led_power_blue: power_blue {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
@@ -60,12 +62,14 @@
 		};
 
 		lan_blue {
-			label = "blue:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
 		};
 
 		wan_blue {
-			label = "blue:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ath79/dts/ar7240_ruckus_zf7025.dts b/target/linux/ath79/dts/ar7240_ruckus_zf7025.dts
index f5d0a9e3b07441..887f5f7b29d6c6 100644
--- a/target/linux/ath79/dts/ar7240_ruckus_zf7025.dts
+++ b/target/linux/ath79/dts/ar7240_ruckus_zf7025.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 
 / {
@@ -71,25 +72,29 @@
 		};
 
 		led_power_red: power-red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 			panic-indicator;
 		};
 
 		led_power_green: power-green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		wlan-green {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0assoc";
 		};
 
 		wlan-yellow {
-			label = "yellow:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_YELLOW>;
 			gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/ar7240_tplink.dtsi b/target/linux/ath79/dts/ar7240_tplink.dtsi
index 5bcfb54bfce298..17c826c6c0f17b 100644
--- a/target/linux/ath79/dts/ar7240_tplink.dtsi
+++ b/target/linux/ath79/dts/ar7240_tplink.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -53,7 +54,8 @@
 		compatible = "gpio-leds";
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&ath9k 1 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/ar7240_tplink_tl-wa.dtsi b/target/linux/ath79/dts/ar7240_tplink_tl-wa.dtsi
index 2bded28ea4233f..1f46e77423cd24 100644
--- a/target/linux/ath79/dts/ar7240_tplink_tl-wa.dtsi
+++ b/target/linux/ath79/dts/ar7240_tplink_tl-wa.dtsi
@@ -1,10 +1,13 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "ar7240_tplink.dtsi"
 
 &leds {
 	lan {
-		label = "green:lan";
+		function = LED_FUNCTION_LAN;
+		color = <LED_COLOR_ID_GREEN>;
 		gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 	};
 };
diff --git a/target/linux/ath79/dts/ar7240_tplink_tl-wr.dtsi b/target/linux/ath79/dts/ar7240_tplink_tl-wr.dtsi
index 6c090fb437e824..e0c625e23955af 100644
--- a/target/linux/ath79/dts/ar7240_tplink_tl-wr.dtsi
+++ b/target/linux/ath79/dts/ar7240_tplink_tl-wr.dtsi
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "ar7240_tplink.dtsi"
 
 &leds {
@@ -24,7 +26,8 @@
 	};
 
 	wan {
-		label = "green:wan";
+		function = LED_FUNCTION_WAN;
+		color = <LED_COLOR_ID_GREEN>;
 		gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
 	};
 };
diff --git a/target/linux/ath79/dts/ar7241_netgear_wnr2000-v3.dts b/target/linux/ath79/dts/ar7241_netgear_wnr2000-v3.dts
index 0a6936c5bfd575..d8baa071112369 100644
--- a/target/linux/ath79/dts/ar7241_netgear_wnr2000-v3.dts
+++ b/target/linux/ath79/dts/ar7241_netgear_wnr2000-v3.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/mtd/partitions/uimage.h>
 
 / {
@@ -58,12 +59,14 @@
 		pinctrl-0 = <&jtag_disable_pins &switch_led_disable_pins &clks_disable_pins>;
 
 		wan_green {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
 		};
 
 		wan_amber {
-			label = "amber:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
 		};
 
@@ -108,7 +111,8 @@
 		};
 
 		wps_green {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -117,18 +121,21 @@
 		compatible = "gpio-leds";
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&ath9k 3 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_amber: power_amber {
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&ath9k 2 GPIO_ACTIVE_LOW>;
 			default-state = "keep";
 		};
 
 		wlan_blue {
-			label = "blue:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&ath9k 1 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/ar7241_netgear_wnr2200.dtsi b/target/linux/ath79/dts/ar7241_netgear_wnr2200.dtsi
index e17a485396ff2c..2c1dd064fecf1d 100644
--- a/target/linux/ath79/dts/ar7241_netgear_wnr2200.dtsi
+++ b/target/linux/ath79/dts/ar7241_netgear_wnr2200.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/mtd/partitions/uimage.h>
 
 / {
@@ -51,12 +52,14 @@
 		pinctrl-0 = <&jtag_disable_pins &switch_led_disable_pins &clks_disable_pins>;
 
 		wan_green {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
 		};
 
 		wan_amber {
-			label = "amber:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
 		};
 
@@ -101,12 +104,14 @@
 		};
 
 		wps_green {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
 		};
 
 		usb_green {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&hub_port>;
 			linux,default-trigger = "usbport";
@@ -117,18 +122,21 @@
 		compatible = "gpio-leds";
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&ath9k 2 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_amber: power_amber {
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&ath9k 1 GPIO_ACTIVE_LOW>;
 			default-state = "keep";
 		};
 
 		wlan_blue {
-			label = "blue:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&ath9k 0 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/ar7241_tplink_tl-mr3220-v1.dts b/target/linux/ath79/dts/ar7241_tplink_tl-mr3220-v1.dts
index af8e297b1df842..c9f696234bf8e5 100644
--- a/target/linux/ath79/dts/ar7241_tplink_tl-mr3220-v1.dts
+++ b/target/linux/ath79/dts/ar7241_tplink_tl-mr3220-v1.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "ar7241_tplink_tl-mr3x20.dtsi"
 
 / {
@@ -10,7 +12,8 @@
 		compatible = "gpio-leds";
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&ath9k 1 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/ar7241_tplink_tl-mr3420-v1.dts b/target/linux/ath79/dts/ar7241_tplink_tl-mr3420-v1.dts
index cae2f5477d652c..539a5952b30efe 100644
--- a/target/linux/ath79/dts/ar7241_tplink_tl-mr3420-v1.dts
+++ b/target/linux/ath79/dts/ar7241_tplink_tl-mr3420-v1.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "ar7241_tplink_tl-mr3x20.dtsi"
 
 / {
@@ -10,7 +12,8 @@
 		compatible = "gpio-leds";
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&ath9k 0 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/ar7241_tplink_tl-wr841-v7.dts b/target/linux/ath79/dts/ar7241_tplink_tl-wr841-v7.dts
index 17e06dfac7d6e7..c9543afed397e3 100644
--- a/target/linux/ath79/dts/ar7241_tplink_tl-wr841-v7.dts
+++ b/target/linux/ath79/dts/ar7241_tplink_tl-wr841-v7.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "ar7241_tplink.dtsi"
 
 / {
@@ -10,7 +12,8 @@
 		compatible = "gpio-leds";
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&ath9k 0 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/ar7241_tplink_tl-wr842n-v1.dts b/target/linux/ath79/dts/ar7241_tplink_tl-wr842n-v1.dts
index e7fe31f36d0db2..b0edbf4d06f319 100644
--- a/target/linux/ath79/dts/ar7241_tplink_tl-wr842n-v1.dts
+++ b/target/linux/ath79/dts/ar7241_tplink_tl-wr842n-v1.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "tplink,tl-wr842n-v1", "qca,ar7241";
@@ -60,7 +61,8 @@
 		compatible = "gpio-leds";
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&ath9k 0 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/ar7241_ubnt_airrouter.dts b/target/linux/ath79/dts/ar7241_ubnt_airrouter.dts
index fcc66c018c7eca..4fa0c704a600d0 100644
--- a/target/linux/ath79/dts/ar7241_ubnt_airrouter.dts
+++ b/target/linux/ath79/dts/ar7241_ubnt_airrouter.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "ar7241.dtsi"
 #include "ar724x_ubnt_xm.dtsi"
 
@@ -24,7 +26,8 @@
 		};
 
 		power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 11 GPIO_ACTIVE_HIGH>;
 		};
 	};
diff --git a/target/linux/ath79/dts/ar7242_avm_fritz300e.dts b/target/linux/ath79/dts/ar7242_avm_fritz300e.dts
index 7a0d7dd2689bfe..f8ca3ed5639e57 100644
--- a/target/linux/ath79/dts/ar7242_avm_fritz300e.dts
+++ b/target/linux/ath79/dts/ar7242_avm_fritz300e.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "avm,fritz300e", "qca,ar7242";
@@ -32,18 +33,21 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/ar7242_buffalo_wzr-bhr.dtsi b/target/linux/ath79/dts/ar7242_buffalo_wzr-bhr.dtsi
index 15a808ad2ac966..f14053b0459174 100644
--- a/target/linux/ath79/dts/ar7242_buffalo_wzr-bhr.dtsi
+++ b/target/linux/ath79/dts/ar7242_buffalo_wzr-bhr.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -39,7 +40,8 @@
 		};
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&hub_port>;
 			linux,default-trigger = "usbport";
diff --git a/target/linux/ath79/dts/ar7242_buffalo_wzr-hp-g302h-a1a0.dts b/target/linux/ath79/dts/ar7242_buffalo_wzr-hp-g302h-a1a0.dts
index ac4c096961badf..abb39e119b94f9 100644
--- a/target/linux/ath79/dts/ar7242_buffalo_wzr-hp-g302h-a1a0.dts
+++ b/target/linux/ath79/dts/ar7242_buffalo_wzr-hp-g302h-a1a0.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "buffalo,wzr-hp-g302h-a1a0", "qca,ar7242";
@@ -69,7 +70,8 @@
 		compatible = "gpio-leds";
 
 		usb {
-			label = "blue:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&ath9k 4 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&hub_port>;
 			linux,default-trigger = "usbport";
diff --git a/target/linux/ath79/dts/ar7242_engenius_eap350-v1.dts b/target/linux/ath79/dts/ar7242_engenius_eap350-v1.dts
index 861964fdfcdc7a..4c618956ac7ef8 100644
--- a/target/linux/ath79/dts/ar7242_engenius_eap350-v1.dts
+++ b/target/linux/ath79/dts/ar7242_engenius_eap350-v1.dts
@@ -5,6 +5,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "engenius,eap350-v1", "qca,ar7242";
@@ -33,7 +34,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
 			default-state = "on";
 		};
@@ -43,7 +45,8 @@
 		compatible = "gpio-leds";
 
 		wlan {
-			label = "blue:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&ath9k 1 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/ar7242_engenius_ecb350-v1.dts b/target/linux/ath79/dts/ar7242_engenius_ecb350-v1.dts
index a7def14c738a72..024cce6f0f4e26 100644
--- a/target/linux/ath79/dts/ar7242_engenius_ecb350-v1.dts
+++ b/target/linux/ath79/dts/ar7242_engenius_ecb350-v1.dts
@@ -5,6 +5,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "engenius,ecb350-v1", "qca,ar7242";
@@ -33,7 +34,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
 			default-state = "on";
 		};
@@ -43,7 +45,8 @@
 		compatible = "gpio-leds";
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&ath9k 1 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/ar7242_meraki_mr12.dts b/target/linux/ath79/dts/ar7242_meraki_mr12.dts
index 5218a5ce27649b..2ab6f8aaf34532 100644
--- a/target/linux/ath79/dts/ar7242_meraki_mr12.dts
+++ b/target/linux/ath79/dts/ar7242_meraki_mr12.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "meraki,mr12", "qca,ar7242";
@@ -40,18 +41,21 @@
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_orange: power_orange {
-			label = "orange:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
 			panic-indicator;
 		};
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ath79/dts/ar7242_tplink_tl-wr2543-v1.dts b/target/linux/ath79/dts/ar7242_tplink_tl-wr2543-v1.dts
index 8df1fdb4ddbe08..efedf2a31bb9f3 100644
--- a/target/linux/ath79/dts/ar7242_tplink_tl-wr2543-v1.dts
+++ b/target/linux/ath79/dts/ar7242_tplink_tl-wr2543-v1.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "tplink,tl-wr2543-v1", "qca,ar7242";
@@ -43,12 +44,14 @@
 		compatible = "gpio-leds";
 
 		led_wps: wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
 		};
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&hub_port>;
 			linux,default-trigger = "usbport";
diff --git a/target/linux/ath79/dts/ar9132_buffalo_wzr-hp-g300nh.dtsi b/target/linux/ath79/dts/ar9132_buffalo_wzr-hp-g300nh.dtsi
index 0eb38b5712effa..77e7925715a3fc 100644
--- a/target/linux/ath79/dts/ar9132_buffalo_wzr-hp-g300nh.dtsi
+++ b/target/linux/ath79/dts/ar9132_buffalo_wzr-hp-g300nh.dtsi
@@ -3,6 +3,7 @@
 #include "ar9132.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -155,7 +156,8 @@
 		compatible = "gpio-leds";
 
 		usb {
-			label = "blue:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&hub_port>;
 			linux,default-trigger = "usbport";
diff --git a/target/linux/ath79/dts/ar9132_tplink_tl-wa901nd-v2.dts b/target/linux/ath79/dts/ar9132_tplink_tl-wa901nd-v2.dts
index 476f3e18a3f45f..1857b2b4a6cc86 100644
--- a/target/linux/ath79/dts/ar9132_tplink_tl-wa901nd-v2.dts
+++ b/target/linux/ath79/dts/ar9132_tplink_tl-wa901nd-v2.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "tplink,tl-wa901nd-v2", "qca,ar9132";
@@ -49,7 +50,8 @@
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/ar9132_tplink_tl-wr1043nd-v1.dts b/target/linux/ath79/dts/ar9132_tplink_tl-wr1043nd-v1.dts
index a4d19ce970a1c9..7957c438d6a3a7 100644
--- a/target/linux/ath79/dts/ar9132_tplink_tl-wr1043nd-v1.dts
+++ b/target/linux/ath79/dts/ar9132_tplink_tl-wr1043nd-v1.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "tplink,tl-wr1043nd-v1", "qca,ar9132";
@@ -39,7 +40,8 @@
 		compatible = "gpio-leds";
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&hub_port>;
 			linux,default-trigger = "usbport";
@@ -57,7 +59,8 @@
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/ar9132_tplink_tl-wr941-v2.dts b/target/linux/ath79/dts/ar9132_tplink_tl-wr941-v2.dts
index 41e53e1fc8d921..e786ad2760eeb8 100644
--- a/target/linux/ath79/dts/ar9132_tplink_tl-wr941-v2.dts
+++ b/target/linux/ath79/dts/ar9132_tplink_tl-wr941-v2.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "tplink,tl-wr941-v2", "qca,ar9132";
@@ -54,7 +55,8 @@
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/ar9330_dlink_dir-505.dts b/target/linux/ath79/dts/ar9330_dlink_dir-505.dts
index ad48e07701de93..c5109ff8000e15 100644
--- a/target/linux/ath79/dts/ar9330_dlink_dir-505.dts
+++ b/target/linux/ath79/dts/ar9330_dlink_dir-505.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "D-Link DIR-505";
@@ -38,12 +39,14 @@
 		pinctrl-0 = <&jtag_disable_pins>;
 
 		led_power_green: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 27 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status_red: status {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 26 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ath79/dts/ar9330_glinet_gl-ar150.dts b/target/linux/ath79/dts/ar9330_glinet_gl-ar150.dts
index 7401cd053a70a6..088973048d8189 100644
--- a/target/linux/ath79/dts/ar9330_glinet_gl-ar150.dts
+++ b/target/linux/ath79/dts/ar9330_glinet_gl-ar150.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "GL.iNet GL-AR150";
@@ -21,7 +22,8 @@
 		compatible = "gpio-leds";
 
 		wlan {
-			label = "orange:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "phy0tpt";
 		};
@@ -32,7 +34,8 @@
 		};
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
 			default-state = "on";
 		};
diff --git a/target/linux/ath79/dts/ar9330_openmesh_om2p.dtsi b/target/linux/ath79/dts/ar9330_openmesh_om2p.dtsi
index a7fd10bd732066..38704f91697164 100644
--- a/target/linux/ath79/dts/ar9330_openmesh_om2p.dtsi
+++ b/target/linux/ath79/dts/ar9330_openmesh_om2p.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	chosen {
@@ -40,13 +41,15 @@
 		};
 
 		led_power_blue: power_blue {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		lan_blue {
-			label = "blue:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 		};
 
@@ -62,7 +65,8 @@
 		};
 
 		wan_blue {
-			label = "blue:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ath79/dts/ar9330_pqi_air-pen.dts b/target/linux/ath79/dts/ar9330_pqi_air-pen.dts
index a2665519f46224..98ef9abcc020ed 100644
--- a/target/linux/ath79/dts/ar9330_pqi_air-pen.dts
+++ b/target/linux/ath79/dts/ar9330_pqi_air-pen.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "PQI Air-Pen";
@@ -19,13 +20,15 @@
 		compatible = "gpio-leds";
 
 		led_wlan: wlan {
-			label = "blue:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "phy0tpt";
 		};
 
 		wps {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
 		};
 	};
diff --git a/target/linux/ath79/dts/ar9330_ziking_cpe46b.dts b/target/linux/ath79/dts/ar9330_ziking_cpe46b.dts
index 256fe5f6154cfa..ebd6d5384fc6bc 100644
--- a/target/linux/ath79/dts/ar9330_ziking_cpe46b.dts
+++ b/target/linux/ath79/dts/ar9330_ziking_cpe46b.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "ZiKing CPE46B";
@@ -17,7 +18,8 @@
 		compatible = "gpio-leds";
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/ar9331_8dev_carambola2.dts b/target/linux/ath79/dts/ar9331_8dev_carambola2.dts
index f786f425f05abf..73699d9bfabf16 100644
--- a/target/linux/ath79/dts/ar9331_8dev_carambola2.dts
+++ b/target/linux/ath79/dts/ar9331_8dev_carambola2.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "8devices Carambola2";
@@ -17,7 +18,8 @@
 		compatible = "gpio-leds";
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/ar9331_alfa-network_ap121f.dtsi b/target/linux/ath79/dts/ar9331_alfa-network_ap121f.dtsi
index 98de255332d6f9..ca0b4131acffdf 100644
--- a/target/linux/ath79/dts/ar9331_alfa-network_ap121f.dtsi
+++ b/target/linux/ath79/dts/ar9331_alfa-network_ap121f.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -35,7 +36,8 @@
 		compatible = "gpio-leds";
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
 		};
 
@@ -45,7 +47,8 @@
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/ar9331_arduino_yun.dts b/target/linux/ath79/dts/ar9331_arduino_yun.dts
index bf3a46f96261ca..c866889ce4b6ca 100644
--- a/target/linux/ath79/dts/ar9331_arduino_yun.dts
+++ b/target/linux/ath79/dts/ar9331_arduino_yun.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Arduino Yun";
@@ -49,13 +50,15 @@
 		compatible = "gpio-leds";
 
 		wlan {
-			label = "blue:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "phy0tpt";
 		};
 
 		usb {
-			label = "white:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
 			trigger-sources = <&hub_port>;
 			linux,default-trigger = "usbport";
diff --git a/target/linux/ath79/dts/ar9331_embeddedwireless_dorin.dts b/target/linux/ath79/dts/ar9331_embeddedwireless_dorin.dts
index 6286f203efc2ae..ee906171601749 100644
--- a/target/linux/ath79/dts/ar9331_embeddedwireless_dorin.dts
+++ b/target/linux/ath79/dts/ar9331_embeddedwireless_dorin.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Embedded Wireless Dorin";
@@ -20,7 +21,8 @@
 		compatible = "gpio-leds";
 
 		led_status: status {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ath79/dts/ar9331_etactica_eg200.dts b/target/linux/ath79/dts/ar9331_etactica_eg200.dts
index 5a96d50940283f..ad3b88ab2b9788 100644
--- a/target/linux/ath79/dts/ar9331_etactica_eg200.dts
+++ b/target/linux/ath79/dts/ar9331_etactica_eg200.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "eTactica EG200";
@@ -45,7 +46,8 @@
 		};
 
 		wlan {
-			label = "red:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/ar9331_glinet_64xx.dtsi b/target/linux/ath79/dts/ar9331_glinet_64xx.dtsi
index 8d003ce0903222..be199b5e4fa1a8 100644
--- a/target/linux/ath79/dts/ar9331_glinet_64xx.dtsi
+++ b/target/linux/ath79/dts/ar9331_glinet_64xx.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	keys {
@@ -21,13 +22,15 @@
 		compatible = "gpio-leds";
 
 		wlan {
-			label = "red:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "phy0tpt";
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 13 GPIO_ACTIVE_HIGH>;
 		};
 	};
diff --git a/target/linux/ath79/dts/ar9331_glinet_gl-mifi.dts b/target/linux/ath79/dts/ar9331_glinet_gl-mifi.dts
index e4d2ff1e11d012..37418bfc4ad946 100644
--- a/target/linux/ath79/dts/ar9331_glinet_gl-mifi.dts
+++ b/target/linux/ath79/dts/ar9331_glinet_gl-mifi.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "glinet,gl-mifi", "qca,ar9331";
@@ -17,18 +18,21 @@
 		compatible = "gpio-leds";
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "phy0tpt";
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 27 GPIO_ACTIVE_HIGH>;
 		};
 
diff --git a/target/linux/ath79/dts/ar9331_glinet_gl-usb150.dts b/target/linux/ath79/dts/ar9331_glinet_gl-usb150.dts
index 541b73850a0599..e9b1c189249037 100644
--- a/target/linux/ath79/dts/ar9331_glinet_gl-usb150.dts
+++ b/target/linux/ath79/dts/ar9331_glinet_gl-usb150.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "glinet,gl-usb150", "qca,ar9331";
@@ -21,13 +22,15 @@
 		compatible = "gpio-leds";
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "phy0tpt";
 		};
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 13 GPIO_ACTIVE_HIGH>;
 			default-state = "on";
 		};
diff --git a/target/linux/ath79/dts/ar9331_hiwifi_hc6361.dts b/target/linux/ath79/dts/ar9331_hiwifi_hc6361.dts
index b10f7fc965f24e..5d0c02a64992c3 100644
--- a/target/linux/ath79/dts/ar9331_hiwifi_hc6361.dts
+++ b/target/linux/ath79/dts/ar9331_hiwifi_hc6361.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "HiWiFi HC6361";
@@ -37,11 +38,13 @@
 			default-state = "on";
 		};
 		wlan {
-			label = "blue:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
 		};
 		wan {
-			label = "blue:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 27 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ath79/dts/ar9331_teltonika_rut230-v1.dts b/target/linux/ath79/dts/ar9331_teltonika_rut230-v1.dts
index ad987dbca1db5c..054ccea52276bb 100644
--- a/target/linux/ath79/dts/ar9331_teltonika_rut230-v1.dts
+++ b/target/linux/ath79/dts/ar9331_teltonika_rut230-v1.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Teltonika RUT230 v1";
@@ -82,13 +83,15 @@
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 			/* GPIO 13 - ACTIVE HIGH for hwrev 0 */
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
 			/* GPIO 14 - ACTIVE HIGH for hwrev 0 */
 		};
diff --git a/target/linux/ath79/dts/ar9331_tplink_tl-mr3020-v1.dts b/target/linux/ath79/dts/ar9331_tplink_tl-mr3020-v1.dts
index 7b307cd6d072dc..0a965c2fa92520 100644
--- a/target/linux/ath79/dts/ar9331_tplink_tl-mr3020-v1.dts
+++ b/target/linux/ath79/dts/ar9331_tplink_tl-mr3020-v1.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "TP-Link TL-MR3020 V1";
@@ -21,18 +22,21 @@
 		compatible = "gpio-leds";
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "phy0tpt";
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
 		};
 
 		led_wps: wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 26 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ath79/dts/ar9331_tplink_tl-mr3040-v2.dts b/target/linux/ath79/dts/ar9331_tplink_tl-mr3040-v2.dts
index 91023111a681d3..df39577110e52f 100644
--- a/target/linux/ath79/dts/ar9331_tplink_tl-mr3040-v2.dts
+++ b/target/linux/ath79/dts/ar9331_tplink_tl-mr3040-v2.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "TP-Link TL-MR3040 V2";
@@ -22,13 +23,15 @@
 		pinctrl-0 = <&switch_led_disable_pins>;
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 26 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
 
 		led_lan: lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ath79/dts/ar9331_tplink_tl-wr741nd-v4.dtsi b/target/linux/ath79/dts/ar9331_tplink_tl-wr741nd-v4.dtsi
index 613b357dc872d2..04537fd33aa24a 100644
--- a/target/linux/ath79/dts/ar9331_tplink_tl-wr741nd-v4.dtsi
+++ b/target/linux/ath79/dts/ar9331_tplink_tl-wr741nd-v4.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "tplink,tl-wr741n-v4", "qca,ar9331";
@@ -72,12 +73,14 @@
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 13 GPIO_ACTIVE_HIGH>;
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/ar9341_engenius_eap300-v2.dts b/target/linux/ath79/dts/ar9341_engenius_eap300-v2.dts
index 9ba89324223ba9..30f42862b22218 100644
--- a/target/linux/ath79/dts/ar9341_engenius_eap300-v2.dts
+++ b/target/linux/ath79/dts/ar9341_engenius_eap300-v2.dts
@@ -5,6 +5,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Engenius EAP300 v2";
@@ -32,13 +33,15 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		wlan {
-			label = "blue:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/ar9341_engenius_ens202ext-v1.dts b/target/linux/ath79/dts/ar9341_engenius_ens202ext-v1.dts
index eb304db8a380d8..1b90deace53cf6 100644
--- a/target/linux/ath79/dts/ar9341_engenius_ens202ext-v1.dts
+++ b/target/linux/ath79/dts/ar9341_engenius_ens202ext-v1.dts
@@ -5,6 +5,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Engenius ENS202EXT v1";
@@ -32,13 +33,15 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		wlan {
-			label = "amber:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/ar9341_openmesh_om2p-hs.dtsi b/target/linux/ath79/dts/ar9341_openmesh_om2p-hs.dtsi
index bb6af232fd2e69..d41dcaa3289cee 100644
--- a/target/linux/ath79/dts/ar9341_openmesh_om2p-hs.dtsi
+++ b/target/linux/ath79/dts/ar9341_openmesh_om2p-hs.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	chosen {
@@ -35,7 +36,8 @@
 		compatible = "gpio-leds";
 
 		led_power_blue: power_blue {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
@@ -57,12 +59,14 @@
 		};
 
 		lan_blue {
-			label = "blue:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
 		};
 
 		wan_blue {
-			label = "blue:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ath79/dts/ar9341_pcs_cr3000.dts b/target/linux/ath79/dts/ar9341_pcs_cr3000.dts
index 5ec17034d17b6d..1011ab4980ea22 100644
--- a/target/linux/ath79/dts/ar9341_pcs_cr3000.dts
+++ b/target/linux/ath79/dts/ar9341_pcs_cr3000.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "PowerCloud Systems CR3000";
@@ -41,19 +42,22 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		wlan2g {
-			label = "blue:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
 
 		wan {
-			label = "blue:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ath79/dts/ar9341_tplink.dtsi b/target/linux/ath79/dts/ar9341_tplink.dtsi
index 9c505f2785c5e2..5dff908129a9c5 100644
--- a/target/linux/ath79/dts/ar9341_tplink.dtsi
+++ b/target/linux/ath79/dts/ar9341_tplink.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -17,13 +18,15 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
@@ -34,7 +37,8 @@
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ath79/dts/ar9341_tplink_tl-mr3420-v2.dts b/target/linux/ath79/dts/ar9341_tplink_tl-mr3420-v2.dts
index 3971df17f81fec..5a5e785d9270e8 100644
--- a/target/linux/ath79/dts/ar9341_tplink_tl-mr3420-v2.dts
+++ b/target/linux/ath79/dts/ar9341_tplink_tl-mr3420-v2.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "ar9341_tplink.dtsi"
 
 / {
@@ -31,7 +33,8 @@
 
 &leds {
 	usb {
-		label = "green:usb";
+		function = LED_FUNCTION_USB;
+		color = <LED_COLOR_ID_GREEN>;
 		gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 		trigger-sources = <&hub_port>;
 		linux,default-trigger = "usbport";
diff --git a/target/linux/ath79/dts/ar9341_tplink_tl-wa850re-v1.dts b/target/linux/ath79/dts/ar9341_tplink_tl-wa850re-v1.dts
index 12755aea2fa85d..08f14f5cc1b6fe 100644
--- a/target/linux/ath79/dts/ar9341_tplink_tl-wa850re-v1.dts
+++ b/target/linux/ath79/dts/ar9341_tplink_tl-wa850re-v1.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "ar9341_tplink_tl-wa.dtsi"
 
 / {
@@ -35,12 +37,14 @@
 		compatible = "gpio-leds";
 
 		lan {
-			label = "blue:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 20 GPIO_ACTIVE_LOW>;
 		};
 
 		wlan {
-			label = "blue:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/ar9341_tplink_tl-wa860re-v1.dts b/target/linux/ath79/dts/ar9341_tplink_tl-wa860re-v1.dts
index 9f540f82d95911..e1ed0c29359687 100644
--- a/target/linux/ath79/dts/ar9341_tplink_tl-wa860re-v1.dts
+++ b/target/linux/ath79/dts/ar9341_tplink_tl-wa860re-v1.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "ar9341_tplink_tl-wa.dtsi"
 
 / {
@@ -42,29 +44,34 @@
 		compatible = "gpio-leds";
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 20 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		led_power_orange: power_orange {
-			label = "orange:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
 		};
 
 		wlan_green {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
 
 		wlan_orange {
-			label = "orange:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ath79/dts/ar9341_tplink_tl-wa901nd-v3.dts b/target/linux/ath79/dts/ar9341_tplink_tl-wa901nd-v3.dts
index 4a4e51f4b8accc..696e8f6391ebd2 100644
--- a/target/linux/ath79/dts/ar9341_tplink_tl-wa901nd-v3.dts
+++ b/target/linux/ath79/dts/ar9341_tplink_tl-wa901nd-v3.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "ar9341_tplink_tl-wa.dtsi"
 
 / {
@@ -28,12 +30,14 @@
 		compatible = "gpio-leds";
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/ar9341_tplink_tl-wr842n-v2.dts b/target/linux/ath79/dts/ar9341_tplink_tl-wr842n-v2.dts
index d0f4c2e1f5aab5..3efd8242469b0b 100644
--- a/target/linux/ath79/dts/ar9341_tplink_tl-wr842n-v2.dts
+++ b/target/linux/ath79/dts/ar9341_tplink_tl-wr842n-v2.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "ar9341_tplink.dtsi"
 
 / {
@@ -41,7 +43,8 @@
 
 &leds {
 	usb {
-		label = "green:usb";
+		function = LED_FUNCTION_USB;
+		color = <LED_COLOR_ID_GREEN>;
 		gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 		trigger-sources = <&hub_port>;
 		linux,default-trigger = "usbport";
diff --git a/target/linux/ath79/dts/ar9342_iodata_etg3-r.dts b/target/linux/ath79/dts/ar9342_iodata_etg3-r.dts
index 8b354d6015348e..21c5d6bc17837a 100644
--- a/target/linux/ath79/dts/ar9342_iodata_etg3-r.dts
+++ b/target/linux/ath79/dts/ar9342_iodata_etg3-r.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "iodata,etg3-r", "qca,ar9344";
@@ -20,7 +21,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
diff --git a/target/linux/ath79/dts/ar9342_mikrotik_routerboard-911g.dtsi b/target/linux/ath79/dts/ar9342_mikrotik_routerboard-911g.dtsi
index 86b4bc358b4c88..5f9d8e42fb8015 100644
--- a/target/linux/ath79/dts/ar9342_mikrotik_routerboard-911g.dtsi
+++ b/target/linux/ath79/dts/ar9342_mikrotik_routerboard-911g.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -85,7 +86,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio_latch 1 GPIO_ACTIVE_HIGH>;
 			default-state = "on";
 		};
diff --git a/target/linux/ath79/dts/ar9342_ruckus_zf7321.dts b/target/linux/ath79/dts/ar9342_ruckus_zf7321.dts
index 917dc297fe1237..83d29c90eae0ad 100644
--- a/target/linux/ath79/dts/ar9342_ruckus_zf7321.dts
+++ b/target/linux/ath79/dts/ar9342_ruckus_zf7321.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "ar934x_ruckus_zf73xx.dtsi"
 
 / {
@@ -18,7 +20,8 @@
 		};
 
 		power_red: power-red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 11 GPIO_ACTIVE_HIGH>;
 			panic-indicator;
 		};
diff --git a/target/linux/ath79/dts/ar9342_ubnt_wa.dtsi b/target/linux/ath79/dts/ar9342_ubnt_wa.dtsi
index d85a07a8dcb180..779b3b681f6b3b 100644
--- a/target/linux/ath79/dts/ar9342_ubnt_wa.dtsi
+++ b/target/linux/ath79/dts/ar9342_ubnt_wa.dtsi
@@ -27,6 +27,13 @@
 
 &pcie {
 	status = "okay";
+
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>;
+		nvmem-cell-names = "calibration";
+	};
 };
 
 &spi {
@@ -79,6 +86,10 @@
 					macaddr_art_0: macaddr@0 {
 						reg = <0x0 0x6>;
 					};
+
+					cal_art_5000: calibration@5000 {
+						reg = <0x5000 0x844>;
+					};
 				};
 			};
 		};
diff --git a/target/linux/ath79/dts/ar9342_zyxel_nwa1100-nh.dts b/target/linux/ath79/dts/ar9342_zyxel_nwa1100-nh.dts
index fd438059e555cf..028171abaa5b1e 100644
--- a/target/linux/ath79/dts/ar9342_zyxel_nwa1100-nh.dts
+++ b/target/linux/ath79/dts/ar9342_zyxel_nwa1100-nh.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "ar9342_zyxel_nwa11xx.dtsi"
 
 / {
@@ -17,29 +19,34 @@
 		compatible = "gpio-leds";
 
 		led_status_green: status_green {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 12 GPIO_ACTIVE_HIGH>;
 			default-state = "on";
 		};
 
 		led_status_red: status_red {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 		};
 
 		led_wlan_green: wlan_green {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
 
 		led_lan_green: lan_green {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 		};
 
 		led_lan_amber: lan_amber {
-			label = "amber:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ath79/dts/ar9342_zyxel_nwa1121-ni.dts b/target/linux/ath79/dts/ar9342_zyxel_nwa1121-ni.dts
index 65dc8c0440a14a..b28f8e5cf6f800 100644
--- a/target/linux/ath79/dts/ar9342_zyxel_nwa1121-ni.dts
+++ b/target/linux/ath79/dts/ar9342_zyxel_nwa1121-ni.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "ar9342_zyxel_nwa11xx.dtsi"
 
 / {
@@ -18,13 +20,15 @@
 		compatible = "gpio-leds";
 
 		led_status_green: status_green {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		led_status_amber: status_amber {
-			label = "amber:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ath79/dts/ar9342_zyxel_nwa1123-ac.dts b/target/linux/ath79/dts/ar9342_zyxel_nwa1123-ac.dts
index 68d49308137f6f..e3164259dfe9d8 100644
--- a/target/linux/ath79/dts/ar9342_zyxel_nwa1123-ac.dts
+++ b/target/linux/ath79/dts/ar9342_zyxel_nwa1123-ac.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "ar9342_zyxel_nwa11xx.dtsi"
 
 / {
@@ -18,13 +20,15 @@
 		compatible = "gpio-leds";
 
 		led_status_green: status_green {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		led_status_amber: status_amber {
-			label = "amber:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ath79/dts/ar9342_zyxel_nwa1123-ni.dts b/target/linux/ath79/dts/ar9342_zyxel_nwa1123-ni.dts
index b999c960c4a0bf..cb5588c12231ee 100644
--- a/target/linux/ath79/dts/ar9342_zyxel_nwa1123-ni.dts
+++ b/target/linux/ath79/dts/ar9342_zyxel_nwa1123-ni.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "ar9342_zyxel_nwa11xx.dtsi"
 
 / {
@@ -18,13 +20,15 @@
 		compatible = "gpio-leds";
 
 		led_status_green: status_green {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		led_status_amber: status_amber {
-			label = "amber:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ath79/dts/ar9344_aerohive_hiveap-121.dts b/target/linux/ath79/dts/ar9344_aerohive_hiveap-121.dts
index 2a2036201e6239..300b3b39bfaa6a 100644
--- a/target/linux/ath79/dts/ar9344_aerohive_hiveap-121.dts
+++ b/target/linux/ath79/dts/ar9344_aerohive_hiveap-121.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "aerohive,hiveap-121", "qca,ar9344";
@@ -36,12 +37,14 @@
 		compatible = "gpio-leds";
 
 		led_power_orange: power_orange {
-			label = "orange:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_white: power_white {
-			label = "white:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ath79/dts/ar9344_alfa-network_n5q.dts b/target/linux/ath79/dts/ar9344_alfa-network_n5q.dts
index 789bd6df149083..9f4c95c3d46ef2 100644
--- a/target/linux/ath79/dts/ar9344_alfa-network_n5q.dts
+++ b/target/linux/ath79/dts/ar9344_alfa-network_n5q.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "ALFA Network N5Q";
@@ -72,7 +73,8 @@
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/ar9344_araknis_an-300-ap-i-n.dts b/target/linux/ath79/dts/ar9344_araknis_an-300-ap-i-n.dts
index c2c7cbb960c797..86e990ffc7deb6 100644
--- a/target/linux/ath79/dts/ar9344_araknis_an-300-ap-i-n.dts
+++ b/target/linux/ath79/dts/ar9344_araknis_an-300-ap-i-n.dts
@@ -5,6 +5,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "araknis,an-300-ap-i-n", "qca,ar9344";
@@ -31,7 +32,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 			default-state = "off";
 		};
@@ -43,7 +45,8 @@
 		};
 
 		wps {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ath79/dts/ar9344_atheros_db120.dts b/target/linux/ath79/dts/ar9344_atheros_db120.dts
index 9d5044141245c6..5004f4034148cc 100644
--- a/target/linux/ath79/dts/ar9344_atheros_db120.dts
+++ b/target/linux/ath79/dts/ar9344_atheros_db120.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/mtd/partitions/uimage.h>
 
 / {
@@ -39,7 +40,8 @@
 		};
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&hub_port>;
 			linux,default-trigger = "usbport";
diff --git a/target/linux/ath79/dts/ar9344_comfast_cf-e120a-v3.dts b/target/linux/ath79/dts/ar9344_comfast_cf-e120a-v3.dts
index c53f03235fcbd0..6bfa82356bfce9 100644
--- a/target/linux/ath79/dts/ar9344_comfast_cf-e120a-v3.dts
+++ b/target/linux/ath79/dts/ar9344_comfast_cf-e120a-v3.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "comfast,cf-e120a-v3", "qca,ar9344";
@@ -23,17 +24,20 @@
 		pinctrl-0 = <&led_rssimediumhigh_pin>;
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/ar9344_compex_wpj344-16m.dts b/target/linux/ath79/dts/ar9344_compex_wpj344-16m.dts
index 21329db2584241..8a354dfe374d41 100644
--- a/target/linux/ath79/dts/ar9344_compex_wpj344-16m.dts
+++ b/target/linux/ath79/dts/ar9344_compex_wpj344-16m.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "compex,wpj344-16m", "qca,ar9344";
@@ -21,7 +22,8 @@
 		compatible = "gpio-leds";
 
 		led_status: status {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ath79/dts/ar9344_devolo_dlan_wifi.dtsi b/target/linux/ath79/dts/ar9344_devolo_dlan_wifi.dtsi
index df157f582cf8cf..e503be08ce0f5b 100644
--- a/target/linux/ath79/dts/ar9344_devolo_dlan_wifi.dtsi
+++ b/target/linux/ath79/dts/ar9344_devolo_dlan_wifi.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -17,7 +18,8 @@
 		compatible = "gpio-leds";
 
 		wlan {
-			label = "white:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy1tpt";
 		};
@@ -127,6 +129,10 @@
 						reg = <0x1002 0x6>;
 						#nvmem-cell-cells = <1>;
 					};
+
+					cal_art_5000: calibration@5000 {
+						reg = <0x5000 0x844>;
+					};
 				};
 			};
 		};
@@ -161,6 +167,8 @@
 	wifi@0,0 {
 		compatible = "qcom,ath10k";
 		reg = <0 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>;
+		nvmem-cell-names = "calibration";
 	};
 };
 
diff --git a/target/linux/ath79/dts/ar9344_dlink_dir-825-c1.dts b/target/linux/ath79/dts/ar9344_dlink_dir-825-c1.dts
index 35d0e26d8530d9..f0ca94f2317d77 100644
--- a/target/linux/ath79/dts/ar9344_dlink_dir-825-c1.dts
+++ b/target/linux/ath79/dts/ar9344_dlink_dir-825-c1.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "ar9344_dlink_dir-8x5.dtsi"
 
 / {
@@ -20,19 +22,22 @@
 		pinctrl-0 = <&enable_gpio_11>;
 
 		led_power_blue: power_blue {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
 		};
 
 		usb {
-			label = "blue:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "usbport";
 			trigger-sources = <&hub_port>;
 		};
 
 		wan_blue {
-			label = "blue:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
 		};
 
@@ -43,17 +48,20 @@
 		};
 
 		wps {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_orange: power_orange {
-			label = "orange:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		};
 
 		wan_orange {
-			label = "orange:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ath79/dts/ar9344_dlink_dir-835-a1.dts b/target/linux/ath79/dts/ar9344_dlink_dir-835-a1.dts
index b2fcf71bd8265f..8ecea4d6c070b7 100644
--- a/target/linux/ath79/dts/ar9344_dlink_dir-835-a1.dts
+++ b/target/linux/ath79/dts/ar9344_dlink_dir-835-a1.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "ar9344_dlink_dir-8x5.dtsi"
 
 / {
@@ -17,27 +19,32 @@
 		compatible = "gpio-leds";
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
 		};
 
 		wan_green {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_orange: power_orange {
-			label = "orange:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		};
 
 		wan_orange {
-			label = "orange:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ath79/dts/ar9344_embeddedwireless_balin.dts b/target/linux/ath79/dts/ar9344_embeddedwireless_balin.dts
index de138658180760..a5d684cf99520f 100644
--- a/target/linux/ath79/dts/ar9344_embeddedwireless_balin.dts
+++ b/target/linux/ath79/dts/ar9344_embeddedwireless_balin.dts
@@ -25,7 +25,6 @@
 		compatible = "gpio-leds";
 
 		led_system: led-0 {
-			label = "green:system";
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_POWER;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
diff --git a/target/linux/ath79/dts/ar9344_engenius_eap600.dts b/target/linux/ath79/dts/ar9344_engenius_eap600.dts
index 4d3a149e3ee26f..94543cd25574fd 100644
--- a/target/linux/ath79/dts/ar9344_engenius_eap600.dts
+++ b/target/linux/ath79/dts/ar9344_engenius_eap600.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "ar9344_senao_ap-dual.dtsi"
 
 / {
@@ -10,13 +12,15 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		wps {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ath79/dts/ar9344_engenius_ecb600.dts b/target/linux/ath79/dts/ar9344_engenius_ecb600.dts
index e7b8b9c3ce239a..1b75d887f298ae 100644
--- a/target/linux/ath79/dts/ar9344_engenius_ecb600.dts
+++ b/target/linux/ath79/dts/ar9344_engenius_ecb600.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "ar9344_senao_ap-dual.dtsi"
 
 / {
@@ -10,7 +12,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
diff --git a/target/linux/ath79/dts/ar9344_enterasys_ws-ap3705i.dts b/target/linux/ath79/dts/ar9344_enterasys_ws-ap3705i.dts
index 8f8276255a3037..0605baa58e7f01 100644
--- a/target/linux/ath79/dts/ar9344_enterasys_ws-ap3705i.dts
+++ b/target/linux/ath79/dts/ar9344_enterasys_ws-ap3705i.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "enterasys,ws-ap3705i", "qca,ar9344";
@@ -45,22 +46,26 @@
 		pinctrl-0 = <&enable_gpio_11 &enable_gpio_16>;
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_red: power_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
 		};
 
 		lan_blue {
-			label = "blue:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 19 GPIO_ACTIVE_HIGH>;
 		};
 
 		lan_green {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 20 GPIO_ACTIVE_HIGH>;
 		};
 
diff --git a/target/linux/ath79/dts/ar9344_fortinet_fap-221-b.dts b/target/linux/ath79/dts/ar9344_fortinet_fap-221-b.dts
index 0cad9b76d15e6a..f97ca429558a4f 100644
--- a/target/linux/ath79/dts/ar9344_fortinet_fap-221-b.dts
+++ b/target/linux/ath79/dts/ar9344_fortinet_fap-221-b.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "ar9344_fortinet_ap-dual.dtsi"
 
 / {
@@ -14,13 +16,15 @@
 		compatible = "gpio-leds";
 
 		led_power: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		power_amber {
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ath79/dts/ar9344_mikrotik_routerboard-911-lite.dts b/target/linux/ath79/dts/ar9344_mikrotik_routerboard-911-lite.dts
index 0315f49d07480d..b815291e70cc98 100644
--- a/target/linux/ath79/dts/ar9344_mikrotik_routerboard-911-lite.dts
+++ b/target/linux/ath79/dts/ar9344_mikrotik_routerboard-911-lite.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "ar9344_mikrotik_routerboard.dtsi"
 #include "ar9344_mikrotik_routerboard-16m-nor.dtsi"
 
@@ -13,12 +15,14 @@
 	pinctrl-0 = <&enable_gpio_20>;
 
 	lan {
-		label = "green:lan";
+		function = LED_FUNCTION_LAN;
+		color = <LED_COLOR_ID_GREEN>;
 		gpios = <&gpio 20 GPIO_ACTIVE_LOW>;
 	};
 
 	power {
-		label = "green:power";
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_GREEN>;
 		gpios = <&gpio 11 GPIO_ACTIVE_HIGH>;
 		default-state = "on";
 	};
diff --git a/target/linux/ath79/dts/ar9344_mikrotik_routerboard-lhg-5nd.dts b/target/linux/ath79/dts/ar9344_mikrotik_routerboard-lhg-5nd.dts
index b6de8c4b7b119f..fd07858b6b69d6 100644
--- a/target/linux/ath79/dts/ar9344_mikrotik_routerboard-lhg-5nd.dts
+++ b/target/linux/ath79/dts/ar9344_mikrotik_routerboard-lhg-5nd.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "ar9344_mikrotik_routerboard.dtsi"
 #include "ar9344_mikrotik_routerboard-16m-nor.dtsi"
 
@@ -10,7 +12,8 @@
 
 &leds {
 	power {
-		label = "blue:power";
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_BLUE>;
 		gpios = <&gpio 11 GPIO_ACTIVE_HIGH>;
 		default-state = "on";
 	};
@@ -21,7 +24,8 @@
 	};
 
 	lan {
-		label = "green:lan";
+		function = LED_FUNCTION_LAN;
+		color = <LED_COLOR_ID_GREEN>;
 		gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 	};
 };
diff --git a/target/linux/ath79/dts/ar9344_mikrotik_routerboard-sxt-5nd-r2.dts b/target/linux/ath79/dts/ar9344_mikrotik_routerboard-sxt-5nd-r2.dts
index a4485320345c1a..0f86ad7903e650 100644
--- a/target/linux/ath79/dts/ar9344_mikrotik_routerboard-sxt-5nd-r2.dts
+++ b/target/linux/ath79/dts/ar9344_mikrotik_routerboard-sxt-5nd-r2.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "ar9344_mikrotik_routerboard.dtsi"
 
 / {
@@ -24,7 +26,8 @@
 
 &leds {
 	power {
-		label = "green:power";
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_GREEN>;
 		gpios = <&gpio 11 GPIO_ACTIVE_HIGH>;
 		default-state = "on";
 	};
diff --git a/target/linux/ath79/dts/ar9344_moxa_awk-1137c.dts b/target/linux/ath79/dts/ar9344_moxa_awk-1137c.dts
index d2c51714020ac6..01b1053142c303 100644
--- a/target/linux/ath79/dts/ar9344_moxa_awk-1137c.dts
+++ b/target/linux/ath79/dts/ar9344_moxa_awk-1137c.dts
@@ -34,7 +34,6 @@
 		pinctrl-names = "default";
 
 		led_status_green: led-0 {
-			label = "green:status";
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_STATUS;
 			function-enumerator = <0>;
@@ -42,7 +41,6 @@
 		};
 
 		led_status_red: led-1 {
-			label = "red:status";
 			color = <LED_COLOR_ID_RED>;
 			function = LED_FUNCTION_STATUS;
 			function-enumerator = <1>;
@@ -50,7 +48,6 @@
 		};
 
 		led-2 {
-			label = "green:wifi";
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_WLAN;
 			function-enumerator = <0>;
@@ -59,21 +56,18 @@
 		};
 
 		led-3 {
-			label = "green:lan1";
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_WAN;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		};
 
 		led-4 {
-			label = "green:lan2";
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_LAN;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 		};
 
 		led-5 {
-			label = "yellow:wifi";
 			color = <LED_COLOR_ID_YELLOW>;
 			function = LED_FUNCTION_WLAN;
 			function-enumerator = <1>;
diff --git a/target/linux/ath79/dts/ar9344_netgear_r6100.dts b/target/linux/ath79/dts/ar9344_netgear_r6100.dts
index 5952e0140fa0c5..d0535251bdc2a3 100644
--- a/target/linux/ath79/dts/ar9344_netgear_r6100.dts
+++ b/target/linux/ath79/dts/ar9344_netgear_r6100.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Netgear R6100";
@@ -57,34 +58,40 @@
 		compatible = "gpio-leds";
 
 		led_power_amber: power_amber {
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
 		};
 
 		usb {
-			label = "blue:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&hub_port>;
 			linux,default-trigger = "usbport";
 		};
 
 		wan_amber {
-			label = "amber:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 		};
 
 		wan_green {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 		};
 
 		wlan {
-			label = "blue:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy1tpt";
 		};
diff --git a/target/linux/ath79/dts/ar9344_netgear_wndr.dtsi b/target/linux/ath79/dts/ar9344_netgear_wndr.dtsi
index 49057548f89dc8..64ceb875d07cbd 100644
--- a/target/linux/ath79/dts/ar9344_netgear_wndr.dtsi
+++ b/target/linux/ath79/dts/ar9344_netgear_wndr.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/mtd/partitions/uimage.h>
 
 / {
@@ -48,12 +49,14 @@
 		pinctrl-0 = <&enable_gpio_11>;
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_amber: power_amber {
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
 			default-state = "keep";
 		};
@@ -71,12 +74,14 @@
 		};
 
 		wps_green {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
 		};
 
 		wps_amber {
-			label = "amber:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ath79/dts/ar9344_netgear_wndr_usb.dtsi b/target/linux/ath79/dts/ar9344_netgear_wndr_usb.dtsi
index bd1eb59f4faba3..165c5bdf4d3e45 100644
--- a/target/linux/ath79/dts/ar9344_netgear_wndr_usb.dtsi
+++ b/target/linux/ath79/dts/ar9344_netgear_wndr_usb.dtsi
@@ -1,8 +1,11 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 &leds {
 	usb_green {
-		label = "green:usb";
+		function = LED_FUNCTION_USB;
+		color = <LED_COLOR_ID_GREEN>;
 		gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 		trigger-sources = <&hub_port>;
 		linux,default-trigger = "usbport";
diff --git a/target/linux/ath79/dts/ar9344_netgear_wndr_wan.dtsi b/target/linux/ath79/dts/ar9344_netgear_wndr_wan.dtsi
index da6020769f189b..f11314694ab7e3 100644
--- a/target/linux/ath79/dts/ar9344_netgear_wndr_wan.dtsi
+++ b/target/linux/ath79/dts/ar9344_netgear_wndr_wan.dtsi
@@ -1,13 +1,17 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 &leds {
 	wan_green {
-		label = "green:wan";
+		function = LED_FUNCTION_WAN;
+		color = <LED_COLOR_ID_GREEN>;
 		gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
 	};
 
 	wan_amber {
-		label = "amber:wan";
+		function = LED_FUNCTION_WAN;
+		color = <LED_COLOR_ID_AMBER>;
 		gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
 	};
 };
diff --git a/target/linux/ath79/dts/ar9344_ocedo_raccoon.dts b/target/linux/ath79/dts/ar9344_ocedo_raccoon.dts
index 39ba2ffc3aff4c..d4ab23ed43ca38 100644
--- a/target/linux/ath79/dts/ar9344_ocedo_raccoon.dts
+++ b/target/linux/ath79/dts/ar9344_ocedo_raccoon.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "OCEDO Raccoon";
@@ -24,7 +25,8 @@
 		compatible = "gpio-leds";
 
 		power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
diff --git a/target/linux/ath79/dts/ar9344_openmesh_mr600-v1.dts b/target/linux/ath79/dts/ar9344_openmesh_mr600-v1.dts
index 6c20f2715f0ee1..f7985629bb2585 100644
--- a/target/linux/ath79/dts/ar9344_openmesh_mr600-v1.dts
+++ b/target/linux/ath79/dts/ar9344_openmesh_mr600-v1.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "ar9344_openmesh_mr600.dtsi"
 
 / {
@@ -23,12 +25,14 @@
 		};
 
 		wps_blue {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_orange: power_orange {
-			label = "orange:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
diff --git a/target/linux/ath79/dts/ar9344_openmesh_mr600-v2.dts b/target/linux/ath79/dts/ar9344_openmesh_mr600-v2.dts
index 988066798f5e86..b6bec0a4385f63 100644
--- a/target/linux/ath79/dts/ar9344_openmesh_mr600-v2.dts
+++ b/target/linux/ath79/dts/ar9344_openmesh_mr600-v2.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "ar9344_openmesh_mr600.dtsi"
 
 / {
@@ -22,12 +24,14 @@
 		};
 
 		wps_blue {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_blue: power_blue {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
diff --git a/target/linux/ath79/dts/ar9344_openmesh_om5p-an.dts b/target/linux/ath79/dts/ar9344_openmesh_om5p-an.dts
index 38153d9dc068c8..d15acfc7ca2eb8 100644
--- a/target/linux/ath79/dts/ar9344_openmesh_om5p-an.dts
+++ b/target/linux/ath79/dts/ar9344_openmesh_om5p-an.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "openmesh,om5p-an", "qca,ar9344";
@@ -38,18 +39,21 @@
 		pinctrl-0 = <&led_lan_wan_blue_pin>;
 
 		led_power_blue: power_blue {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		wan_blue {
-			label = "blue:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		};
 
 		lan_blue {
-			label = "blue:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ath79/dts/ar9344_openmesh_om5p.dts b/target/linux/ath79/dts/ar9344_openmesh_om5p.dts
index e3aa19c82de6ff..739ba583a80003 100644
--- a/target/linux/ath79/dts/ar9344_openmesh_om5p.dts
+++ b/target/linux/ath79/dts/ar9344_openmesh_om5p.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "openmesh,om5p", "qca,ar9344";
@@ -38,18 +39,21 @@
 		pinctrl-0 = <&led_lan_wan_blue_pin>;
 
 		led_power_blue: power_blue {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		wan_blue {
-			label = "blue:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		};
 
 		lan_blue {
-			label = "blue:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ath79/dts/ar9344_pcs_cap324.dts b/target/linux/ath79/dts/ar9344_pcs_cap324.dts
index aab04b080a89cb..f7f3ef06c971e7 100644
--- a/target/linux/ath79/dts/ar9344_pcs_cap324.dts
+++ b/target/linux/ath79/dts/ar9344_pcs_cap324.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "PowerCloud Systems CAP324";
@@ -34,35 +35,41 @@
 		compatible = "gpio-leds";
 
 		led_power_amber: power_amber {
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		wlan_amber {
-			label = "amber:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy1tpt";
 		};
 
 		wlan_green {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
 
 		lan_amber {
-			label = "amber:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 		};
 
 		lan_green {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ath79/dts/ar9344_pcs_cr5000.dts b/target/linux/ath79/dts/ar9344_pcs_cr5000.dts
index a5fc1160c2ce88..6f35bd2c1e51c4 100644
--- a/target/linux/ath79/dts/ar9344_pcs_cr5000.dts
+++ b/target/linux/ath79/dts/ar9344_pcs_cr5000.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "PowerCloud Systems CR5000";
@@ -41,20 +42,23 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 2 GPIO_ACTIVE_LOW>,
 				<&gpio 4 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		wlan2g {
-			label = "blue:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
 
 		wps_white {
-			label = "white:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ath79/dts/ar9344_qihoo_c301.dts b/target/linux/ath79/dts/ar9344_qihoo_c301.dts
index d7e2e242394bac..1d9c6ca9a43134 100644
--- a/target/linux/ath79/dts/ar9344_qihoo_c301.dts
+++ b/target/linux/ath79/dts/ar9344_qihoo_c301.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Qihoo 360 C301";
@@ -21,12 +22,14 @@
 		pinctrl-0 = <&jtag_disable_pins>;
 
 		led_wlan_g: wlan_g {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
 		};
 
 		led_wlan_o: wlan_o {
-			label = "orange:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy1tpt";
 		};
@@ -157,6 +160,16 @@
 				label = "radiocfg";
 				reg = <0xff0000 0x10000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_radiocfg_5000: calibration@5000 {
+						reg = <0x5000 0x844>;
+					};
+				};
 			};
 		};
 	};
@@ -200,6 +213,8 @@
 	wifi@0,0 {
 		compatible = "qcom,ath10k";
 		reg = <0 0 0 0 0>;
+		nvmem-cells = <&cal_radiocfg_5000>;
+		nvmem-cell-names = "calibration";
 	};
 };
 
diff --git a/target/linux/ath79/dts/ar9344_qxwlan_e750a-v4-16m.dts b/target/linux/ath79/dts/ar9344_qxwlan_e750a-v4-16m.dts
index 33e2990284e226..6762264d35828e 100644
--- a/target/linux/ath79/dts/ar9344_qxwlan_e750a-v4-16m.dts
+++ b/target/linux/ath79/dts/ar9344_qxwlan_e750a-v4-16m.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "ar9344_qxwlan_e750x.dtsi"
 
 / {
@@ -9,12 +11,14 @@
 
 &leds {
 	lan {
-		label = "green:lan";
+		function = LED_FUNCTION_LAN;
+		color = <LED_COLOR_ID_GREEN>;
 		gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
 	};
 
 	wan {
-		label = "green:wan";
+		function = LED_FUNCTION_WAN;
+		color = <LED_COLOR_ID_GREEN>;
 		gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
 	};
 };
diff --git a/target/linux/ath79/dts/ar9344_qxwlan_e750a-v4-8m.dts b/target/linux/ath79/dts/ar9344_qxwlan_e750a-v4-8m.dts
index b20d187941da86..999030a9cdd77d 100644
--- a/target/linux/ath79/dts/ar9344_qxwlan_e750a-v4-8m.dts
+++ b/target/linux/ath79/dts/ar9344_qxwlan_e750a-v4-8m.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "ar9344_qxwlan_e750x.dtsi"
 
 / {
@@ -9,12 +11,14 @@
 
 &leds {
 	lan {
-		label = "green:lan";
+		function = LED_FUNCTION_LAN;
+		color = <LED_COLOR_ID_GREEN>;
 		gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
 	};
 
 	wan {
-		label = "green:wan";
+		function = LED_FUNCTION_WAN;
+		color = <LED_COLOR_ID_GREEN>;
 		gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
 	};
 };
diff --git a/target/linux/ath79/dts/ar9344_qxwlan_e750x.dtsi b/target/linux/ath79/dts/ar9344_qxwlan_e750x.dtsi
index 238a59cbe8d543..df8f28c7d748b8 100644
--- a/target/linux/ath79/dts/ar9344_qxwlan_e750x.dtsi
+++ b/target/linux/ath79/dts/ar9344_qxwlan_e750x.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -45,7 +46,8 @@
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/ar9344_ruckus_zf7372.dts b/target/linux/ath79/dts/ar9344_ruckus_zf7372.dts
index dbccbef023b7f0..b60dc61c74a791 100644
--- a/target/linux/ath79/dts/ar9344_ruckus_zf7372.dts
+++ b/target/linux/ath79/dts/ar9344_ruckus_zf7372.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "ar934x_ruckus_zf73xx.dtsi"
 
 / {
@@ -28,7 +30,8 @@
 		};
 
 		power_red: power-red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
 			panic-indicator;
 		};
diff --git a/target/linux/ath79/dts/ar9344_samsung_wam250.dts b/target/linux/ath79/dts/ar9344_samsung_wam250.dts
index 0bbd5c92fe9e59..da8c9ac165d7e2 100644
--- a/target/linux/ath79/dts/ar9344_samsung_wam250.dts
+++ b/target/linux/ath79/dts/ar9344_samsung_wam250.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Samsung WAM250";
@@ -38,12 +39,14 @@
 		compatible = "gpio-leds";
 
 		lan {
-			label = "white:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power: power {
-			label = "white:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 			default-state = "keep";
 		};
@@ -54,7 +57,8 @@
 		};
 
 		wlan {
-			label = "white:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/ar9344_tplink_cpe605-v1.dts b/target/linux/ath79/dts/ar9344_tplink_cpe605-v1.dts
index 0c6eee7ba6347e..1b762896a14d79 100644
--- a/target/linux/ath79/dts/ar9344_tplink_cpe605-v1.dts
+++ b/target/linux/ath79/dts/ar9344_tplink_cpe605-v1.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "ar9344_tplink_cpe.dtsi"
 
 / {
@@ -16,7 +18,8 @@
 		compatible = "gpio-leds";
 
 		led_lan: lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ath79/dts/ar9344_tplink_cpe610-v1.dts b/target/linux/ath79/dts/ar9344_tplink_cpe610-v1.dts
index c495eb298c8cfa..c44ad29ccf907a 100644
--- a/target/linux/ath79/dts/ar9344_tplink_cpe610-v1.dts
+++ b/target/linux/ath79/dts/ar9344_tplink_cpe610-v1.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "ar9344_tplink_cpe.dtsi"
 
 / {
@@ -16,7 +18,8 @@
 		compatible = "gpio-leds";
 
 		led_lan: lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ath79/dts/ar9344_tplink_cpe610-v2.dts b/target/linux/ath79/dts/ar9344_tplink_cpe610-v2.dts
index fa533d9f504a9c..7228ca9f49c860 100644
--- a/target/linux/ath79/dts/ar9344_tplink_cpe610-v2.dts
+++ b/target/linux/ath79/dts/ar9344_tplink_cpe610-v2.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "ar9344_tplink_cpe.dtsi"
 
 / {
@@ -16,7 +18,8 @@
 		compatible = "gpio-leds";
 
 		led_lan: lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ath79/dts/ar9344_tplink_cpe_1port.dtsi b/target/linux/ath79/dts/ar9344_tplink_cpe_1port.dtsi
index a1dca810936f17..27f425fa6d0704 100644
--- a/target/linux/ath79/dts/ar9344_tplink_cpe_1port.dtsi
+++ b/target/linux/ath79/dts/ar9344_tplink_cpe_1port.dtsi
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "ar9344_tplink_cpe.dtsi"
 
 / {
@@ -14,7 +16,8 @@
 		compatible = "gpio-leds";
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ath79/dts/ar9344_tplink_tl-wdr3500-v1.dts b/target/linux/ath79/dts/ar9344_tplink_tl-wdr3500-v1.dts
index a66e1fefa25eed..013b44a1239e43 100644
--- a/target/linux/ath79/dts/ar9344_tplink_tl-wdr3500-v1.dts
+++ b/target/linux/ath79/dts/ar9344_tplink_tl-wdr3500-v1.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "ar9344_tplink_tl-wdrxxxx.dtsi"
 
 / {
@@ -13,7 +15,8 @@
 
 &leds {
 	usb {
-		label = "green:usb";
+		function = LED_FUNCTION_USB;
+		color = <LED_COLOR_ID_GREEN>;
 		gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 		linux,default-trigger = "usbport";
 		trigger-sources = <&hub_port>;
diff --git a/target/linux/ath79/dts/ar9344_tplink_tl-wr841hp-v2.dts b/target/linux/ath79/dts/ar9344_tplink_tl-wr841hp-v2.dts
index 6649e2477b25bf..456efc8b75966a 100644
--- a/target/linux/ath79/dts/ar9344_tplink_tl-wr841hp-v2.dts
+++ b/target/linux/ath79/dts/ar9344_tplink_tl-wr841hp-v2.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "TP-Link TL-WR841HP v2";
@@ -31,7 +32,8 @@
 		compatible = "gpio-leds";
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 		};
 
@@ -56,12 +58,14 @@
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/ar9344_watchguard_ap100.dts b/target/linux/ath79/dts/ar9344_watchguard_ap100.dts
index e09d539c5644e4..6f560166965c38 100644
--- a/target/linux/ath79/dts/ar9344_watchguard_ap100.dts
+++ b/target/linux/ath79/dts/ar9344_watchguard_ap100.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "ar9344_senao_ap-dual.dtsi"
 
 / {
@@ -17,12 +19,14 @@
 		compatible = "gpio-leds";
 
 		led_power_amber: power_amber {
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
diff --git a/target/linux/ath79/dts/ar9344_watchguard_ap200.dts b/target/linux/ath79/dts/ar9344_watchguard_ap200.dts
index c3d7c50813ab9a..cb69bd9da96b88 100644
--- a/target/linux/ath79/dts/ar9344_watchguard_ap200.dts
+++ b/target/linux/ath79/dts/ar9344_watchguard_ap200.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "ar9344_senao_ap-dual.dtsi"
 
 / {
@@ -17,12 +19,14 @@
 		compatible = "gpio-leds";
 
 		led_power_amber: power_amber {
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
diff --git a/target/linux/ath79/dts/ar9344_wd_mynet-n600.dts b/target/linux/ath79/dts/ar9344_wd_mynet-n600.dts
index 3c0e9c56a1c81b..c7149953be3e5a 100644
--- a/target/linux/ath79/dts/ar9344_wd_mynet-n600.dts
+++ b/target/linux/ath79/dts/ar9344_wd_mynet-n600.dts
@@ -24,7 +24,6 @@
 		};
 
 		led_power: led-1 {
-			label = "blue:power";
 			color = <LED_COLOR_ID_BLUE>;
 			function = LED_FUNCTION_POWER;
 			gpios = <&gpio 11 GPIO_ACTIVE_HIGH>;
diff --git a/target/linux/ath79/dts/ar9344_wd_mynet-n750.dts b/target/linux/ath79/dts/ar9344_wd_mynet-n750.dts
index d18ffff34d03e1..ecc1d182d15d6d 100644
--- a/target/linux/ath79/dts/ar9344_wd_mynet-n750.dts
+++ b/target/linux/ath79/dts/ar9344_wd_mynet-n750.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "ar9344_wd_mynet-nxxx.dtsi"
 
 / {
@@ -27,12 +29,14 @@
 		};
 
 		wps {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 13 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_power: power {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
 		};
 	};
diff --git a/target/linux/ath79/dts/ar9344_wd_mynet-wifi-rangeextender.dts b/target/linux/ath79/dts/ar9344_wd_mynet-wifi-rangeextender.dts
index 20dad6a675f9aa..1b531aa03598b6 100644
--- a/target/linux/ath79/dts/ar9344_wd_mynet-wifi-rangeextender.dts
+++ b/target/linux/ath79/dts/ar9344_wd_mynet-wifi-rangeextender.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Western Digital My Net Wi-Fi Range Extender";
@@ -24,13 +25,15 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 11 GPIO_ACTIVE_HIGH>;
 			/* LED has no off state. It's either on or it blinks */
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ath79/dts/ar9344_winchannel_wb2000.dts b/target/linux/ath79/dts/ar9344_winchannel_wb2000.dts
index 4b692b6d9bb3ab..145ff0418ed722 100644
--- a/target/linux/ath79/dts/ar9344_winchannel_wb2000.dts
+++ b/target/linux/ath79/dts/ar9344_winchannel_wb2000.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Winchannel WB2000";
@@ -44,7 +45,8 @@
 		};
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 21 GPIO_ACTIVE_HIGH>;
 			trigger-sources = <&hub_port>;
 			linux,default-trigger = "usbport";
diff --git a/target/linux/ath79/dts/ar934x_ruckus_zf73xx.dtsi b/target/linux/ath79/dts/ar934x_ruckus_zf73xx.dtsi
index d494f9b1ed86f6..2164ce95991e94 100644
--- a/target/linux/ath79/dts/ar934x_ruckus_zf73xx.dtsi
+++ b/target/linux/ath79/dts/ar934x_ruckus_zf73xx.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/mtd/partitions/uimage.h>
 
 / {
@@ -51,7 +52,8 @@
 			    <&clks_disable_pins>;
 
 		power_green: power-green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
diff --git a/target/linux/ath79/dts/qca9531_alcatel_hh40v.dts b/target/linux/ath79/dts/qca9531_alcatel_hh40v.dts
index 072a0fa27c2a5f..9c801d8b606286 100644
--- a/target/linux/ath79/dts/qca9531_alcatel_hh40v.dts
+++ b/target/linux/ath79/dts/qca9531_alcatel_hh40v.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "alcatel,hh40v", "qca,qca9531";
@@ -40,22 +41,26 @@
 		pinctrl-0 = <&jtag_disable_pins>;
 
 		lan_active {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 		};
 
 		led_lan_link: lan_link {
-			label = "orange:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
 		};
 
 		wan_active {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 		};
 
 		wan_link {
-			label = "orange:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ath79/dts/qca9531_alfa-network_n2q.dts b/target/linux/ath79/dts/qca9531_alfa-network_n2q.dts
index c9cd7038a5d90d..2175c72692ae0b 100644
--- a/target/linux/ath79/dts/qca9531_alfa-network_n2q.dts
+++ b/target/linux/ath79/dts/qca9531_alfa-network_n2q.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca9531_alfa-network_r36a.dtsi"
 
 / {
@@ -62,7 +64,8 @@
 		};
 
 		led_usb: usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "usbport";
 			trigger-sources = <&hub_port0>;
@@ -74,7 +77,8 @@
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/qca9531_alfa-network_pi-wifi4.dts b/target/linux/ath79/dts/qca9531_alfa-network_pi-wifi4.dts
index 52a6b5431f3c86..fc2aa19324fbf8 100644
--- a/target/linux/ath79/dts/qca9531_alfa-network_pi-wifi4.dts
+++ b/target/linux/ath79/dts/qca9531_alfa-network_pi-wifi4.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca9531_alfa-network_r36a.dtsi"
 
 / {
@@ -29,7 +31,8 @@
 		};
 
 		led_usb: usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "usbport";
 			trigger-sources = <&gl850g_port1>, <&gl850g_port2>,
@@ -37,7 +40,8 @@
 		};
 
 		wlan {
-			label = "blue:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/qca9531_alfa-network_r36a.dts b/target/linux/ath79/dts/qca9531_alfa-network_r36a.dts
index 943731e69eb8d3..698f028df8157b 100644
--- a/target/linux/ath79/dts/qca9531_alfa-network_r36a.dts
+++ b/target/linux/ath79/dts/qca9531_alfa-network_r36a.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca9531_alfa-network_r36a.dtsi"
 
 / {
@@ -20,29 +22,34 @@
 		pinctrl-0 = <&enable_gpio4 &enable_gpio16>;
 
 		lan {
-			label = "blue:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status: status {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		};
 
 		usb {
-			label = "blue:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&hub_port0>;
 			linux,default-trigger = "usbport";
 		};
 
 		wan {
-			label = "blue:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
 		};
 
 		wlan {
-			label = "blue:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/qca9531_alfa-network_tube-2hq.dts b/target/linux/ath79/dts/qca9531_alfa-network_tube-2hq.dts
index 9b35e471e5922f..774d864964c68d 100644
--- a/target/linux/ath79/dts/qca9531_alfa-network_tube-2hq.dts
+++ b/target/linux/ath79/dts/qca9531_alfa-network_tube-2hq.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca9531_alfa-network_r36a.dtsi"
 
 / {
@@ -19,7 +21,8 @@
 		pinctrl-0 = <&enable_gpio4 &enable_gpio16>;
 
 		lan {
-			label = "blue:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ath79/dts/qca9531_asus_rp-ac51.dts b/target/linux/ath79/dts/qca9531_asus_rp-ac51.dts
index b2777f6cc6fb9c..e24ef541126301 100644
--- a/target/linux/ath79/dts/qca9531_asus_rp-ac51.dts
+++ b/target/linux/ath79/dts/qca9531_asus_rp-ac51.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "ASUS RP-AC51";
@@ -37,17 +38,20 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 4 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_wps: wps {
-			label = "red:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
 		};
 
 		lan {
-			label = "blue:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
 		};
 
@@ -65,6 +69,13 @@
 
 &pcie0 {
 	status = "okay";
+
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&precal_art_5000>;
+		nvmem-cell-names = "pre-calibration";
+	};
 };
 
 &spi {
@@ -109,6 +120,10 @@
 					macaddr_art_1002: macaddr@1002 {
 						reg = <0x1002 0x6>;
 					};
+
+					precal_art_5000: pre-calibration@5000 {
+						reg = <0x5000 0x2f20>;
+					};
 				};
 			};
 
diff --git a/target/linux/ath79/dts/qca9531_comfast_cf-e130n-v2.dts b/target/linux/ath79/dts/qca9531_comfast_cf-e130n-v2.dts
index d0d2a07c2b46e7..1c96bd9a6ac31b 100644
--- a/target/linux/ath79/dts/qca9531_comfast_cf-e130n-v2.dts
+++ b/target/linux/ath79/dts/qca9531_comfast_cf-e130n-v2.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "comfast,cf-e130n-v2", "qca,qca9531";
@@ -23,13 +24,15 @@
 		pinctrl-names = "default";
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ath79/dts/qca9531_comfast_cf-e313ac.dts b/target/linux/ath79/dts/qca9531_comfast_cf-e313ac.dts
index d078a9dcce5bec..08a0a99c2b8f54 100644
--- a/target/linux/ath79/dts/qca9531_comfast_cf-e313ac.dts
+++ b/target/linux/ath79/dts/qca9531_comfast_cf-e313ac.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "comfast,cf-e313ac", "qca,qca9531";
@@ -22,18 +23,21 @@
 		pinctrl-names = "default";
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
 		};
 
@@ -103,9 +107,17 @@
 						reg = <0x0 0x6>;
 					};
 
+					macaddr_art_6: macaddr@6 {
+						reg = <0x6 0x6>;
+					};
+
 					macaddr_art_1002: macaddr@1002 {
 						reg = <0x1002 0x6>;
 					};
+
+					precal_art_5000: pre-calibration@5000 {
+						reg = <0x5000 0x2f20>;
+					};
 				};
 			};
 
@@ -155,5 +167,7 @@
 	wifi@0,0 {
 		compatible = "qcom,ath10k";
 		reg = <0 0 0 0 0>;
+		nvmem-cells = <&precal_art_5000>, <&macaddr_art_6>;
+		nvmem-cell-names = "pre-calibration", "mac-address";
 	};
 };
diff --git a/target/linux/ath79/dts/qca9531_comfast_cf-e314n-v2.dts b/target/linux/ath79/dts/qca9531_comfast_cf-e314n-v2.dts
index ff053d628e471e..9a616921e5392f 100644
--- a/target/linux/ath79/dts/qca9531_comfast_cf-e314n-v2.dts
+++ b/target/linux/ath79/dts/qca9531_comfast_cf-e314n-v2.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "comfast,cf-e314n-v2", "qca,qca9531";
@@ -23,12 +24,14 @@
 		pinctrl-0 = <&jtag_disable_pins &led_rssilow_pin &led_rssimediumhigh_pin &led_rssihigh_pin>;
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
 		};
 
@@ -53,7 +56,8 @@
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/qca9531_comfast_cf-e5.dts b/target/linux/ath79/dts/qca9531_comfast_cf-e5.dts
index 73d45f9b7cc0bf..ec99ee0c4f5e2a 100644
--- a/target/linux/ath79/dts/qca9531_comfast_cf-e5.dts
+++ b/target/linux/ath79/dts/qca9531_comfast_cf-e5.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "comfast,cf-e5", "qca,qca9531";
@@ -29,17 +30,20 @@
 		pinctrl-0 = <&jtag_disable_pins &led_wan_pin>;
 
 		wan {
-			label = "blue:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
 		};
 
 		lan {
-			label = "blue:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
 		};
 
 		wlan {
-			label = "blue:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/qca9531_comfast_cf-e560ac.dts b/target/linux/ath79/dts/qca9531_comfast_cf-e560ac.dts
index a316c48c5b4804..535676aab21286 100644
--- a/target/linux/ath79/dts/qca9531_comfast_cf-e560ac.dts
+++ b/target/linux/ath79/dts/qca9531_comfast_cf-e560ac.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "comfast,cf-e560ac", "qca,qca9531";
@@ -60,12 +61,14 @@
 		};
 
 		wan {
-			label = "blue:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
 		};
 
 		wlan {
-			label = "blue:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
@@ -114,6 +117,10 @@
 						reg = <0x0 0x6>;
 						#nvmem-cell-cells = <1>;
 					};
+
+					precal_art_5000: pre-calibration@5000 {
+						reg = <0x5000 0x2f20>;
+					};
 				};
 			};
 
@@ -140,6 +147,13 @@
 
 &pcie0 {
 	status = "okay";
+
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&precal_art_5000>, <&macaddr_art_0 2>;
+		nvmem-cell-names = "pre-calibration", "mac-address";
+	};
 };
 
 &usb_phy {
diff --git a/target/linux/ath79/dts/qca9531_comfast_cf-ew72.dts b/target/linux/ath79/dts/qca9531_comfast_cf-ew72.dts
index f725ab1faa2928..5f9240d6c1fea6 100644
--- a/target/linux/ath79/dts/qca9531_comfast_cf-ew72.dts
+++ b/target/linux/ath79/dts/qca9531_comfast_cf-ew72.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "comfast,cf-ew72", "qca,qca9531";
@@ -23,17 +24,20 @@
 		pinctrl-0 = <&jtag_disable_pins>;
 
 		lan {
-			label = "blue:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
 		};
 
 		led_wan: wan {
-			label = "blue:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 		};
 
 		wlan {
-			label = "blue:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
@@ -62,6 +66,13 @@
 
 &pcie0 {
 	status = "okay";
+
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&precal_art_5000>, <&macaddr_art_0 2>;
+		nvmem-cell-names = "pre-calibration", "mac-address";
+	};
 };
 
 &spi {
@@ -98,6 +109,10 @@
 						reg = <0x0 0x6>;
 						#nvmem-cell-cells = <1>;
 					};
+
+					precal_art_5000: pre-calibration@5000 {
+						reg = <0x5000 0x2f20>;
+					};
 				};
 			};
 
diff --git a/target/linux/ath79/dts/qca9531_comfast_cf-wr752ac-v1.dts b/target/linux/ath79/dts/qca9531_comfast_cf-wr752ac-v1.dts
index ba33ee9a92307e..d13e4966ae4586 100644
--- a/target/linux/ath79/dts/qca9531_comfast_cf-wr752ac-v1.dts
+++ b/target/linux/ath79/dts/qca9531_comfast_cf-wr752ac-v1.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "comfast,cf-wr752ac-v1", "qca,qca9531";
@@ -23,7 +24,8 @@
 		pinctrl-0 = <&jtag_disable_pins &pinmux_led_rssihigh &pinmux_led_rssilow>;
 
 		led_lan: lan {
-			label = "blue:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
 		};
 
@@ -62,6 +64,13 @@
 
 &pcie0 {
 	status = "okay";
+
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&precal_art_5000>, <&macaddr_art_0 2>;
+		nvmem-cell-names = "pre-calibration", "mac-address";
+	};
 };
 
 &spi {
@@ -98,6 +107,10 @@
 						reg = <0x0 0x6>;
 						#nvmem-cell-cells = <1>;
 					};
+
+					precal_art_5000: pre-calibration@5000 {
+						reg = <0x5000 0x2f20>;
+					};
 				};
 			};
 
diff --git a/target/linux/ath79/dts/qca9531_dlink_dch-g020-a1.dts b/target/linux/ath79/dts/qca9531_dlink_dch-g020-a1.dts
index 9a4db6f9fcdc41..8f2027f25020e3 100644
--- a/target/linux/ath79/dts/qca9531_dlink_dch-g020-a1.dts
+++ b/target/linux/ath79/dts/qca9531_dlink_dch-g020-a1.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "dlink,dch-g020-a1", "qca,qca9531";
@@ -76,12 +77,14 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 		};
 
 		status {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ath79/dts/qca9531_engenius_ews511ap.dts b/target/linux/ath79/dts/qca9531_engenius_ews511ap.dts
index 6fd28d5b3637b0..29886a4d3ec8eb 100644
--- a/target/linux/ath79/dts/qca9531_engenius_ews511ap.dts
+++ b/target/linux/ath79/dts/qca9531_engenius_ews511ap.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "engenius,ews511ap", "qca,qca9531";
@@ -33,7 +34,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
@@ -82,6 +84,13 @@
 
 &pcie0 {
 	status = "okay";
+
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>;
+		nvmem-cell-names = "calibration";
+	};
 };
 
 &spi {
@@ -112,6 +121,16 @@
 				label = "art";
 				reg = <0x050000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_5000: calibration@5000 {
+						reg = <0x5000 0x844>;
+					};
+				};
 			};
 
 			partition@60000 {
diff --git a/target/linux/ath79/dts/qca9531_glinet_gl-ar300m-lite.dts b/target/linux/ath79/dts/qca9531_glinet_gl-ar300m-lite.dts
index c712236114cc3d..f83618aface575 100644
--- a/target/linux/ath79/dts/qca9531_glinet_gl-ar300m-lite.dts
+++ b/target/linux/ath79/dts/qca9531_glinet_gl-ar300m-lite.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca9531_glinet_gl-ar300m.dtsi"
 
 / {
@@ -22,10 +24,12 @@
 };
 
 &led_status {
-	label = "red:status";
+	function = LED_FUNCTION_STATUS;
+	color = <LED_COLOR_ID_RED>;
 };
 
 &led_wlan {
-	label = "green:wlan";
+	function = LED_FUNCTION_WLAN;
+	color = <LED_COLOR_ID_GREEN>;
 };
 
diff --git a/target/linux/ath79/dts/qca9531_glinet_gl-ar300m.dtsi b/target/linux/ath79/dts/qca9531_glinet_gl-ar300m.dtsi
index 652ffb9c698b81..461392660f99c6 100644
--- a/target/linux/ath79/dts/qca9531_glinet_gl-ar300m.dtsi
+++ b/target/linux/ath79/dts/qca9531_glinet_gl-ar300m.dtsi
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -53,17 +54,20 @@
 		// Colors for non-Lite versions
 
 		led_status: status {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 		};
 
 		led_wlan: wlan {
-			label = "red:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/qca9531_glinet_gl-ar750.dts b/target/linux/ath79/dts/qca9531_glinet_gl-ar750.dts
index b81485f4653c11..b6a37754fab7f4 100644
--- a/target/linux/ath79/dts/qca9531_glinet_gl-ar750.dts
+++ b/target/linux/ath79/dts/qca9531_glinet_gl-ar750.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "glinet,gl-ar750", "qca,qca9531";
@@ -40,7 +41,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "white:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
@@ -72,6 +74,8 @@
 	wifi@0,0 {
 		compatible = "qcom,ath10k";
 		reg = <0 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>, <&macaddr_art_0 1>;
+		nvmem-cell-names = "calibration", "mac-address";
 	};
 };
 
@@ -123,6 +127,10 @@
 						reg = <0x0 0x6>;
 						#nvmem-cell-cells = <1>;
 					};
+
+					cal_art_5000: calibration@5000 {
+						reg = <0x5000 0x844>;
+					};
 				};
 			};
 
diff --git a/target/linux/ath79/dts/qca9531_glinet_gl-x300b.dts b/target/linux/ath79/dts/qca9531_glinet_gl-x300b.dts
index 104ed3c72df44c..75a8dca7d201fc 100644
--- a/target/linux/ath79/dts/qca9531_glinet_gl-x300b.dts
+++ b/target/linux/ath79/dts/qca9531_glinet_gl-x300b.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "glinet,gl-x300b", "qca,qca9531";
@@ -32,7 +33,8 @@
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ath79/dts/qca9531_glinet_gl-x750.dts b/target/linux/ath79/dts/qca9531_glinet_gl-x750.dts
index 3f1ad22a764a41..106d81ff113e47 100644
--- a/target/linux/ath79/dts/qca9531_glinet_gl-x750.dts
+++ b/target/linux/ath79/dts/qca9531_glinet_gl-x750.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "glinet,gl-x750", "qca,qca9531";
@@ -26,7 +27,8 @@
 		compatible = "gpio-leds";
 
 		power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
@@ -44,7 +46,8 @@
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		};
 
@@ -57,6 +60,13 @@
 
 &pcie0 {
 	status = "okay";
+
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>, <&macaddr_art_0 2>;
+		nvmem-cell-names = "calibration", "mac-address";
+	};
 };
 
 &usb0 {
@@ -106,6 +116,10 @@
 						reg = <0x0 0x6>;
 						#nvmem-cell-cells = <1>;
 					};
+
+					cal_art_5000: calibration@5000 {
+						reg = <0x5000 0x844>;
+					};
 				};
 			};
 
diff --git a/target/linux/ath79/dts/qca9531_glinet_gl-xe300.dts b/target/linux/ath79/dts/qca9531_glinet_gl-xe300.dts
index 37830c4f7d0484..2e7137bc3a9273 100644
--- a/target/linux/ath79/dts/qca9531_glinet_gl-xe300.dts
+++ b/target/linux/ath79/dts/qca9531_glinet_gl-xe300.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "glinet,gl-xe300", "qca,qca9531";
@@ -47,17 +48,20 @@
 
 		lan {
 			gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 		};
 
 		wan {
 			gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 		};
 
 		wlan {
 			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			linux,default-trigger = "phy0tpt";
 		};
 
diff --git a/target/linux/ath79/dts/qca9531_joyit_jt-or750i.dts b/target/linux/ath79/dts/qca9531_joyit_jt-or750i.dts
index 3b01fa9e421b51..d4e35c84b343b7 100644
--- a/target/linux/ath79/dts/qca9531_joyit_jt-or750i.dts
+++ b/target/linux/ath79/dts/qca9531_joyit_jt-or750i.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "joyit,jt-or750i", "qca,qca9531";
@@ -34,13 +35,15 @@
 		pinctrl-0 = <&jtag_disable_pins &pinmux_led_eth_pins>;
 
 		led_status_green: status_green {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		led_status_red: status_red {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -107,6 +110,10 @@
 					macaddr_art_6: macaddr@6 {
 						reg = <0x6 0x6>;
 					};
+
+					cal_art_5000: calibration@5000 {
+						reg = <0x5000 0x844>;
+					};
 				};
 			};
 		};
@@ -129,6 +136,13 @@
 
 &pcie0 {
 	status = "okay";
+
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>;
+		nvmem-cell-names = "calibration";
+	};
 };
 
 &wmac {
diff --git a/target/linux/ath79/dts/qca9531_letv_lba-047-ch.dts b/target/linux/ath79/dts/qca9531_letv_lba-047-ch.dts
index 414db556cade37..64f5eabb522c8e 100644
--- a/target/linux/ath79/dts/qca9531_letv_lba-047-ch.dts
+++ b/target/linux/ath79/dts/qca9531_letv_lba-047-ch.dts
@@ -33,21 +33,18 @@
 		compatible = "gpio-leds";
 
 		led_status_blue: led-0 {
-			label = "blue:status";
 			color = <LED_COLOR_ID_BLUE>;
 			function = LED_FUNCTION_STATUS;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status_green: led-1 {
-			label = "green:status";
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_STATUS;
 			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status_red: led-2 {
-			label = "red:status";
 			color = <LED_COLOR_ID_RED>;
 			function = LED_FUNCTION_STATUS;
 			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
diff --git a/target/linux/ath79/dts/qca9531_qxwlan_e600g-v2-16m.dts b/target/linux/ath79/dts/qca9531_qxwlan_e600g-v2-16m.dts
index 9b4c0a514d60ed..c3c313f3c67eda 100644
--- a/target/linux/ath79/dts/qca9531_qxwlan_e600g-v2-16m.dts
+++ b/target/linux/ath79/dts/qca9531_qxwlan_e600g-v2-16m.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca9531_qxwlan_e600g.dtsi"
 
 / {
@@ -9,7 +11,8 @@
 
 &leds {
 	wlan {
-		label = "blue:wlan";
+		function = LED_FUNCTION_WLAN;
+		color = <LED_COLOR_ID_BLUE>;
 		gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
 		linux,default-trigger = "phy0tpt";
 	};
@@ -23,6 +26,10 @@
 	};
 };
 
+&pcie0 {
+	/delete-node/ wifi@0,0;
+};
+
 &usb_phy {
 	status = "okay";
 };
diff --git a/target/linux/ath79/dts/qca9531_qxwlan_e600g-v2-8m.dts b/target/linux/ath79/dts/qca9531_qxwlan_e600g-v2-8m.dts
index 7822ec664a4c2f..c417a8ff4cbb6a 100644
--- a/target/linux/ath79/dts/qca9531_qxwlan_e600g-v2-8m.dts
+++ b/target/linux/ath79/dts/qca9531_qxwlan_e600g-v2-8m.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca9531_qxwlan_e600g.dtsi"
 
 / {
@@ -9,7 +11,8 @@
 
 &leds {
 	wlan {
-		label = "blue:wlan";
+		function = LED_FUNCTION_WLAN;
+		color = <LED_COLOR_ID_BLUE>;
 		gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
 		linux,default-trigger = "phy0tpt";
 	};
@@ -23,6 +26,10 @@
 	};
 };
 
+&pcie0 {
+	/delete-node/ wifi@0,0;
+};
+
 &usb_phy {
 	status = "okay";
 };
diff --git a/target/linux/ath79/dts/qca9531_qxwlan_e600g.dtsi b/target/linux/ath79/dts/qca9531_qxwlan_e600g.dtsi
index 04becd63c1013c..ddc3e0f3c6e29d 100644
--- a/target/linux/ath79/dts/qca9531_qxwlan_e600g.dtsi
+++ b/target/linux/ath79/dts/qca9531_qxwlan_e600g.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -35,12 +36,14 @@
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -48,6 +51,13 @@
 
 &pcie0 {
 	status = "okay";
+
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>;
+		nvmem-cell-names = "calibration";
+	};
 };
 
 &spi {
@@ -90,6 +100,10 @@
 						reg = <0x400 0x6>;
 						#nvmem-cell-cells = <1>;
 					};
+
+					cal_art_5000: calibration@5000 {
+						reg = <0x5000 0x844>;
+					};
 				};
 			};
 
diff --git a/target/linux/ath79/dts/qca9531_telco_t1.dts b/target/linux/ath79/dts/qca9531_telco_t1.dts
index 1748d9e1c9cf0b..543fad3c4fc466 100644
--- a/target/linux/ath79/dts/qca9531_telco_t1.dts
+++ b/target/linux/ath79/dts/qca9531_telco_t1.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "telco,t1", "qca,qca9531";
@@ -33,17 +34,20 @@
 		pinctrl-0 = <&jtag_disable_pins &pinmux_led_wan_pin>;
 
 		wan {
-			label = "blue:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
 		};
 
 		lan {
-			label = "blue:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
 		};
 
 		wlan {
-			label = "blue:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/qca9531_teltonika_rut300.dts b/target/linux/ath79/dts/qca9531_teltonika_rut300.dts
index f01bcafbad333c..497cb6f43c0053 100644
--- a/target/linux/ath79/dts/qca9531_teltonika_rut300.dts
+++ b/target/linux/ath79/dts/qca9531_teltonika_rut300.dts
@@ -3,6 +3,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include "qca953x.dtsi"
 
 / {
@@ -24,7 +25,8 @@
 		pinctrl-0 = <&pmx_leds_switch>, <&jtag_disable_pins>;
 
 		led_wan: wan {
-			label = "yellow:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_YELLOW>;
 			gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
 		};
 
diff --git a/target/linux/ath79/dts/qca9531_tplink_archer-d50-v1.dts b/target/linux/ath79/dts/qca9531_tplink_archer-d50-v1.dts
index fb594f78c06d71..fa17cd3ce33a33 100644
--- a/target/linux/ath79/dts/qca9531_tplink_archer-d50-v1.dts
+++ b/target/linux/ath79/dts/qca9531_tplink_archer-d50-v1.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "tplink,archer-d50-v1", "qca,qca9531";
@@ -38,17 +39,20 @@
 		};
 
 		wan {
-			label = "white:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
 		};
 
 		lan {
-			label = "white:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
 		};
 
 		usb {
-			label = "white:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&hub_port0>;
 			linux,default-trigger = "usbport";
@@ -148,6 +152,16 @@
 				label = "art";
 				reg = <0x7f0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_5000: calibration@5000 {
+						reg = <0x5000 0x844>;
+					};
+				};
 			};
 		};
 	};
@@ -181,6 +195,8 @@
 	wifi@0,0 {
 		compatible = "pci168c,003c";
 		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>, <&macaddr_romfile_f100 2>;
+		nvmem-cell-names = "calibration", "mac-address";
 	};
 };
 
diff --git a/target/linux/ath79/dts/qca9531_tplink_tl-mr3420-v3.dts b/target/linux/ath79/dts/qca9531_tplink_tl-mr3420-v3.dts
index f288317c2c374f..be1dc66aff6f4e 100644
--- a/target/linux/ath79/dts/qca9531_tplink_tl-mr3420-v3.dts
+++ b/target/linux/ath79/dts/qca9531_tplink_tl-mr3420-v3.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "tplink,tl-mr3420-v3", "qca,qca9531";
@@ -84,23 +85,27 @@
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&led_gpio 4 GPIO_ACTIVE_LOW>;
 		};
 
 		wan_fail {
-			label = "orange:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&led_gpio 5 GPIO_ACTIVE_LOW>;
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&led_gpio 7 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&hub_port0>;
 			linux,default-trigger = "usbport";
diff --git a/target/linux/ath79/dts/qca9531_tplink_tl-mr6400-v1.dts b/target/linux/ath79/dts/qca9531_tplink_tl-mr6400-v1.dts
index 76f12887386c42..fb9fb12b6b78f8 100644
--- a/target/linux/ath79/dts/qca9531_tplink_tl-mr6400-v1.dts
+++ b/target/linux/ath79/dts/qca9531_tplink_tl-mr6400-v1.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "tplink,tl-mr6400-v1", "qca,qca9531";
@@ -22,7 +23,8 @@
 
 		/* D12 */
 		wan {
-			label = "white:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
 		};
 
@@ -34,26 +36,30 @@
 
 		/* D5 */
 		wps {
-			label = "white:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 3 GPIO_ACTIVE_HIGH>;
 		};
 
 		/* D3 */
 		wlan {
-			label = "white:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 11 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "phy0tpt";
 		};
 
 		/* D2 */
 		led_power: power {
-			label = "white:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 13 GPIO_ACTIVE_HIGH>;
 		};
 
 		/* D4 */
 		lan {
-			label = "white:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
 		};
 	};
diff --git a/target/linux/ath79/dts/qca9531_tplink_tl-wr902ac-v1.dts b/target/linux/ath79/dts/qca9531_tplink_tl-wr902ac-v1.dts
index 048099e2604d63..676f8adf1fce8b 100644
--- a/target/linux/ath79/dts/qca9531_tplink_tl-wr902ac-v1.dts
+++ b/target/linux/ath79/dts/qca9531_tplink_tl-wr902ac-v1.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "tplink,tl-wr902ac-v1", "qca,qca9531";
@@ -21,7 +22,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 13 GPIO_ACTIVE_HIGH>;
 			default-state = "on";
 		};
@@ -38,19 +40,22 @@
 		};
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 4 GPIO_ACTIVE_HIGH>;
 			trigger-sources = <&hub_port0>;
 			linux,default-trigger = "usbport";
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
 		};
 	};
@@ -149,6 +154,16 @@
 				label = "art";
 				reg = <0x7f0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_5000: calibration@5000 {
+						reg = <0x5000 0x844>;
+					};
+				};
 			};
 		};
 	};
@@ -181,6 +196,8 @@
 	wifi@0,0 {
 		compatible = "pci168c,0050";
 		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>, <&macaddr_info_8 (-1)>;
+		nvmem-cell-names = "calibration", "mac-address";
 	};
 };
 
diff --git a/target/linux/ath79/dts/qca9531_wallys_dr531.dts b/target/linux/ath79/dts/qca9531_wallys_dr531.dts
index 59f86170c98f19..9e90f99728ff83 100644
--- a/target/linux/ath79/dts/qca9531_wallys_dr531.dts
+++ b/target/linux/ath79/dts/qca9531_wallys_dr531.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Wallys DR531";
@@ -41,7 +42,8 @@
 		compatible = "gpio-leds";
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		};
 
@@ -66,7 +68,8 @@
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ath79/dts/qca9531_yuncore_a770.dts b/target/linux/ath79/dts/qca9531_yuncore_a770.dts
index fa1f7dc5fca3c5..4ad19fe600ebc7 100644
--- a/target/linux/ath79/dts/qca9531_yuncore_a770.dts
+++ b/target/linux/ath79/dts/qca9531_yuncore_a770.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "YunCore A770";
@@ -31,18 +32,21 @@
 		compatible = "gpio-leds";
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status: status {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
 			default-state = "keep";
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
 		};
 
@@ -101,6 +105,10 @@
 					macaddr_art_6: macaddr@6 {
 						reg = <0x6 0x6>;
 					};
+
+					cal_art_5000: calibration@5000 {
+						reg = <0x5000 0x844>;
+					};
 				};
 			};
 		};
@@ -123,6 +131,13 @@
 
 &pcie0 {
 	status = "okay";
+
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>;
+		nvmem-cell-names = "calibration";
+	};
 };
 
 &wmac {
diff --git a/target/linux/ath79/dts/qca9533_comfast_cf-e110n-v2.dts b/target/linux/ath79/dts/qca9533_comfast_cf-e110n-v2.dts
index f4422e2242903d..e4b6f5fc68ad8e 100644
--- a/target/linux/ath79/dts/qca9533_comfast_cf-e110n-v2.dts
+++ b/target/linux/ath79/dts/qca9533_comfast_cf-e110n-v2.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "comfast,cf-e110n-v2", "qca,qca9533";
@@ -23,12 +24,14 @@
 		pinctrl-0 = <&jtag_disable_pins &led_rssilow_pin &led_rssimediumhigh_pin &led_rssihigh_pin>;
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
 		};
 
@@ -57,7 +60,8 @@
 		compatible = "gpio-leds";
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/qca9533_dlink_dap-13xx.dtsi b/target/linux/ath79/dts/qca9533_dlink_dap-13xx.dtsi
index f1eef86a9b58f4..d5609f7af10c40 100644
--- a/target/linux/ath79/dts/qca9533_dlink_dap-13xx.dtsi
+++ b/target/linux/ath79/dts/qca9533_dlink_dap-13xx.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -33,12 +34,14 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status: status {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ath79/dts/qca9533_dlink_dap-2230-a1.dts b/target/linux/ath79/dts/qca9533_dlink_dap-2230-a1.dts
index 90383690b9721b..796451768f2f07 100644
--- a/target/linux/ath79/dts/qca9533_dlink_dap-2230-a1.dts
+++ b/target/linux/ath79/dts/qca9533_dlink_dap-2230-a1.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca953x_dlink_dap-2xxx.dtsi"
 
 / {
@@ -27,7 +29,8 @@
 		compatible = "gpio-leds";
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
diff --git a/target/linux/ath79/dts/qca9533_dlink_dap-3320-a1.dts b/target/linux/ath79/dts/qca9533_dlink_dap-3320-a1.dts
index 5758b0d2a31cfd..20002aaba85988 100644
--- a/target/linux/ath79/dts/qca9533_dlink_dap-3320-a1.dts
+++ b/target/linux/ath79/dts/qca9533_dlink_dap-3320-a1.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca953x_dlink_dap-2xxx.dtsi"
 
 / {
@@ -27,7 +29,8 @@
 		compatible = "gpio-leds";
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
diff --git a/target/linux/ath79/dts/qca9533_kuwfi_c910.dts b/target/linux/ath79/dts/qca9533_kuwfi_c910.dts
index 487bbf9d4c7081..b1d40ddc05b085 100644
--- a/target/linux/ath79/dts/qca9533_kuwfi_c910.dts
+++ b/target/linux/ath79/dts/qca9533_kuwfi_c910.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/mtd/partitions/uimage.h>
 
 / {
@@ -66,7 +67,8 @@
 		};
 
 		wan {
-			label = "white:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ath79/dts/qca9533_mikrotik_routerboard-lhg-hb.dtsi b/target/linux/ath79/dts/qca9533_mikrotik_routerboard-lhg-hb.dtsi
index aa5c57b27891d6..a65c4fd8ed4c20 100644
--- a/target/linux/ath79/dts/qca9533_mikrotik_routerboard-lhg-hb.dtsi
+++ b/target/linux/ath79/dts/qca9533_mikrotik_routerboard-lhg-hb.dtsi
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca9533_mikrotik_routerboard-16m.dtsi"
 
 / {
@@ -19,7 +21,8 @@
 		pinctrl-0 = <&led_wan_pin>;
 
 		power {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
 			default-state = "on";
 		};
@@ -30,12 +33,14 @@
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/qca9533_mikrotik_routerboard-map-2nd.dts b/target/linux/ath79/dts/qca9533_mikrotik_routerboard-map-2nd.dts
index 062c3bd061a617..7b7477c506f1a1 100644
--- a/target/linux/ath79/dts/qca9533_mikrotik_routerboard-map-2nd.dts
+++ b/target/linux/ath79/dts/qca9533_mikrotik_routerboard-map-2nd.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca9533_mikrotik_routerboard-16m.dtsi"
 
 / {
@@ -17,7 +19,8 @@
 		compatible = "gpio-leds";
 
 		power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
@@ -43,7 +46,8 @@
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio_ext 4 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/qca9533_mikrotik_routerboard-mapl-2nd.dts b/target/linux/ath79/dts/qca9533_mikrotik_routerboard-mapl-2nd.dts
index e337bcc70db878..8d18df8abbdcfd 100644
--- a/target/linux/ath79/dts/qca9533_mikrotik_routerboard-mapl-2nd.dts
+++ b/target/linux/ath79/dts/qca9533_mikrotik_routerboard-mapl-2nd.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca9533_mikrotik_routerboard-16m.dtsi"
 
 / {
@@ -19,18 +21,21 @@
 		pinctrl-0 = <&led_power_pin &led_lan_pin>;
 
 		power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
 			default-state = "on";
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 4 GPIO_ACTIVE_HIGH>;
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 11 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/qca9533_mikrotik_routerboard-wap-2nd.dts b/target/linux/ath79/dts/qca9533_mikrotik_routerboard-wap-2nd.dts
index d4d049920c7f3d..10841591b5deea 100644
--- a/target/linux/ath79/dts/qca9533_mikrotik_routerboard-wap-2nd.dts
+++ b/target/linux/ath79/dts/qca9533_mikrotik_routerboard-wap-2nd.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca9533_mikrotik_routerboard-16m.dtsi"
 
 / {
@@ -19,12 +21,14 @@
 		pinctrl-0 = <&led_lan_pin>;
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/qca9533_mikrotik_routerboard-wapr-2nd.dts b/target/linux/ath79/dts/qca9533_mikrotik_routerboard-wapr-2nd.dts
index 19ada708d99083..942030e4c9a6f3 100644
--- a/target/linux/ath79/dts/qca9533_mikrotik_routerboard-wapr-2nd.dts
+++ b/target/linux/ath79/dts/qca9533_mikrotik_routerboard-wapr-2nd.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca9533_mikrotik_routerboard-16m.dtsi"
 
 / {
@@ -33,7 +35,8 @@
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/qca9533_openmesh_om2p-v4.dtsi b/target/linux/ath79/dts/qca9533_openmesh_om2p-v4.dtsi
index 1f3bf68f69c593..c78f52152d53cc 100644
--- a/target/linux/ath79/dts/qca9533_openmesh_om2p-v4.dtsi
+++ b/target/linux/ath79/dts/qca9533_openmesh_om2p-v4.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	chosen {
@@ -35,7 +36,8 @@
 		compatible = "gpio-leds";
 
 		led_power_blue: power_blue {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
@@ -57,12 +59,14 @@
 		};
 
 		wan_blue {
-			label = "blue:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 		};
 
 		lan_blue {
-			label = "blue:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ath79/dts/qca9533_plasmacloud_pa300.dtsi b/target/linux/ath79/dts/qca9533_plasmacloud_pa300.dtsi
index 66ede5554d0839..010b752995b815 100644
--- a/target/linux/ath79/dts/qca9533_plasmacloud_pa300.dtsi
+++ b/target/linux/ath79/dts/qca9533_plasmacloud_pa300.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	chosen {
@@ -34,17 +35,20 @@
 		compatible = "gpio-leds";
 
 		status_red {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_status_green: status_green {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 2 GPIO_ACTIVE_HIGH>;
 		};
 
 		status_blue {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 3 GPIO_ACTIVE_HIGH>;
 		};
 	};
diff --git a/target/linux/ath79/dts/qca9533_qca_ap143.dtsi b/target/linux/ath79/dts/qca9533_qca_ap143.dtsi
index 2836234b4c7ae0..e7cb1f605d7601 100644
--- a/target/linux/ath79/dts/qca9533_qca_ap143.dtsi
+++ b/target/linux/ath79/dts/qca9533_qca_ap143.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/mtd/partitions/uimage.h>
 
 / {
@@ -18,12 +19,14 @@
 		compatible = "gpio-leds";
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
@@ -49,7 +52,8 @@
 		};
 
 		led_wps: wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ath79/dts/qca9533_tplink_cpe210.dtsi b/target/linux/ath79/dts/qca9533_tplink_cpe210.dtsi
index 3295776bf93e48..e976566f4fcad3 100644
--- a/target/linux/ath79/dts/qca9533_tplink_cpe210.dtsi
+++ b/target/linux/ath79/dts/qca9533_tplink_cpe210.dtsi
@@ -1,10 +1,13 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca9533_tplink_cpexxx.dtsi"
 
 &leds {
 	lan {
-		label = "green:lan";
+		function = LED_FUNCTION_LAN;
+		color = <LED_COLOR_ID_GREEN>;
 		gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 	};
 };
diff --git a/target/linux/ath79/dts/qca9533_tplink_tl-wa801nd.dtsi b/target/linux/ath79/dts/qca9533_tplink_tl-wa801nd.dtsi
index 5a05869a1c0367..7bad615a6c4ac7 100644
--- a/target/linux/ath79/dts/qca9533_tplink_tl-wa801nd.dtsi
+++ b/target/linux/ath79/dts/qca9533_tplink_tl-wa801nd.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -18,7 +19,8 @@
 		compatible = "gpio-leds";
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
 		};
 
@@ -28,7 +30,8 @@
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/qca9533_tplink_tl-wa850re-v2.dts b/target/linux/ath79/dts/qca9533_tplink_tl-wa850re-v2.dts
index c3d42a8b35024f..f1cdde13a2d4cb 100644
--- a/target/linux/ath79/dts/qca9533_tplink_tl-wa850re-v2.dts
+++ b/target/linux/ath79/dts/qca9533_tplink_tl-wa850re-v2.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "tplink,tl-wa850re-v2", "qca,qca9533";
@@ -24,7 +25,8 @@
 		pinctrl-0 = <&jtag_disable_pins>;
 
 		lan {
-			label = "blue:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		};
 
@@ -59,7 +61,8 @@
 		};
 
 		wlan {
-			label = "blue:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/qca9533_tplink_tl-wr841-v11.dtsi b/target/linux/ath79/dts/qca9533_tplink_tl-wr841-v11.dtsi
index 027ed82cbe16b6..035d968cb2a095 100644
--- a/target/linux/ath79/dts/qca9533_tplink_tl-wr841-v11.dtsi
+++ b/target/linux/ath79/dts/qca9533_tplink_tl-wr841-v11.dtsi
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca9533_tplink_tl-wr841.dtsi"
 
 / {
@@ -18,7 +20,8 @@
 	};
 
 	wan_orange {
-		label = "orange:wan";
+		function = LED_FUNCTION_WAN;
+		color = <LED_COLOR_ID_ORANGE>;
 		gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
 	};
 };
diff --git a/target/linux/ath79/dts/qca9533_tplink_tl-wr841.dtsi b/target/linux/ath79/dts/qca9533_tplink_tl-wr841.dtsi
index c0e23f6d62e4f1..9487e67e99bb85 100644
--- a/target/linux/ath79/dts/qca9533_tplink_tl-wr841.dtsi
+++ b/target/linux/ath79/dts/qca9533_tplink_tl-wr841.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -14,7 +15,8 @@
 		compatible = "gpio-leds";
 
 		wifi {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
@@ -25,7 +27,8 @@
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ath79/dts/qca9533_tplink_tl-wr841hp-v3.dts b/target/linux/ath79/dts/qca9533_tplink_tl-wr841hp-v3.dts
index c11f11ae185255..d6768e1af2da88 100644
--- a/target/linux/ath79/dts/qca9533_tplink_tl-wr841hp-v3.dts
+++ b/target/linux/ath79/dts/qca9533_tplink_tl-wr841hp-v3.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "tplink,tl-wr841hp-v3", "qca,qca9533";
@@ -27,28 +28,33 @@
 		};
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		wan_green {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
 		};
 
 		wan_amber {
-			label = "amber:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ath79/dts/qca9533_tplink_tl-wr842n-v3.dts b/target/linux/ath79/dts/qca9533_tplink_tl-wr842n-v3.dts
index 33234fcb9f7a79..4d4acd202ce15a 100644
--- a/target/linux/ath79/dts/qca9533_tplink_tl-wr842n-v3.dts
+++ b/target/linux/ath79/dts/qca9533_tplink_tl-wr842n-v3.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "tplink,tl-wr842n-v3", "qca,qca9533";
@@ -21,13 +22,15 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		wifi {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
@@ -38,12 +41,14 @@
 		};
 
 		wan_green {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 		};
 
 		wan_red {
-			label = "red:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
 		};
 
@@ -68,7 +73,8 @@
 		};
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "usbport";
 			trigger-sources = <&hub_port0>;
diff --git a/target/linux/ath79/dts/qca9550_airtight_c-75.dts b/target/linux/ath79/dts/qca9550_airtight_c-75.dts
index d4bf64ab40bba8..6ade40bfe1e607 100644
--- a/target/linux/ath79/dts/qca9550_airtight_c-75.dts
+++ b/target/linux/ath79/dts/qca9550_airtight_c-75.dts
@@ -32,14 +32,12 @@
 		compatible = "gpio-leds";
 
 		led_power_amber: power-amber {
-			label = "amber:power";
 			color = <LED_COLOR_ID_AMBER>;
 			function = LED_FUNCTION_POWER;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_green: power-green {
-			label = "green:power";
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_POWER;
 			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
diff --git a/target/linux/ath79/dts/qca9556_avm_fritz-repeater.dtsi b/target/linux/ath79/dts/qca9556_avm_fritz-repeater.dtsi
index d0c796fadb500e..4d2f3bb814f54e 100644
--- a/target/linux/ath79/dts/qca9556_avm_fritz-repeater.dtsi
+++ b/target/linux/ath79/dts/qca9556_avm_fritz-repeater.dtsi
@@ -34,6 +34,16 @@
 				label = "urlader";
 				reg = <0x0 0x20000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_urlader_198a: calibration@198a {
+						reg = <0x198a 0x844>;
+					};
+				};
 			};
 
 			partition@20000 {
diff --git a/target/linux/ath79/dts/qca9556_avm_fritz1750e.dts b/target/linux/ath79/dts/qca9556_avm_fritz1750e.dts
index bdb983cd7c73ea..9dafaaa9a4fb56 100644
--- a/target/linux/ath79/dts/qca9556_avm_fritz1750e.dts
+++ b/target/linux/ath79/dts/qca9556_avm_fritz1750e.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca9556_avm_fritz-repeater.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
@@ -45,18 +47,21 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&spi_gpio 6 GPIO_ACTIVE_HIGH>;
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&spi_gpio 5 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "phy1tpt";
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 13 GPIO_ACTIVE_HIGH>;
 		};
 
@@ -89,6 +94,13 @@
 
 &pcie0 {
 	status = "okay";
+
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_urlader_198a>;
+		nvmem-cell-names = "calibration";
+	};
 };
 
 &phy0 {
diff --git a/target/linux/ath79/dts/qca9556_avm_fritz450e.dts b/target/linux/ath79/dts/qca9556_avm_fritz450e.dts
index 0d305359765683..9123ae34b2396f 100644
--- a/target/linux/ath79/dts/qca9556_avm_fritz450e.dts
+++ b/target/linux/ath79/dts/qca9556_avm_fritz450e.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca9556_avm_fritz-repeater.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
@@ -19,18 +21,21 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ath79/dts/qca9556_avm_fritzdvbc.dts b/target/linux/ath79/dts/qca9556_avm_fritzdvbc.dts
index bf1c026d173b7a..a746b95922f754 100644
--- a/target/linux/ath79/dts/qca9556_avm_fritzdvbc.dts
+++ b/target/linux/ath79/dts/qca9556_avm_fritzdvbc.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca9556_avm_fritz-repeater.dtsi"
 
 / {
@@ -48,12 +50,14 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&spi_gpio 6 GPIO_ACTIVE_LOW>;
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&spi_gpio 7 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy1tpt";
 		};
@@ -92,6 +96,13 @@
 
 &pcie0 {
 	status = "okay";
+
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_urlader_198a>;
+		nvmem-cell-names = "calibration";
+	};
 };
 
 &gpio {
diff --git a/target/linux/ath79/dts/qca9557_araknis_an-500-ap-i-ac.dts b/target/linux/ath79/dts/qca9557_araknis_an-500-ap-i-ac.dts
index 6d402df13f922b..8cf1f00255edb6 100644
--- a/target/linux/ath79/dts/qca9557_araknis_an-500-ap-i-ac.dts
+++ b/target/linux/ath79/dts/qca9557_araknis_an-500-ap-i-ac.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "araknis,an-500-ap-i-ac", "qca,qca9557";
@@ -30,7 +31,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
 			default-state = "off";
 		};
@@ -48,7 +50,8 @@
 		};
 
 		wps {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -70,6 +73,10 @@
 				reg = <0x0 0x6>;
 				#nvmem-cell-cells = <1>;
 			};
+
+			cal_art_5000: calibration@5000 {
+				reg = <0x5000 0x844>;
+			};
 		};
 	};
 };
@@ -107,4 +114,11 @@
 
 &pcie0 {
 	status = "okay";
+
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>, <&macaddr_art_0 2>;
+		nvmem-cell-names = "calibration", "mac-address";
+	};
 };
diff --git a/target/linux/ath79/dts/qca9557_buffalo_bhr-4grv2.dts b/target/linux/ath79/dts/qca9557_buffalo_bhr-4grv2.dts
index f17af66cdf9df6..62c1124cb6df05 100644
--- a/target/linux/ath79/dts/qca9557_buffalo_bhr-4grv2.dts
+++ b/target/linux/ath79/dts/qca9557_buffalo_bhr-4grv2.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "buffalo,bhr-4grv2", "qca,qca9557";
@@ -20,7 +21,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
diff --git a/target/linux/ath79/dts/qca9557_dlink_dap-2660-a1.dts b/target/linux/ath79/dts/qca9557_dlink_dap-2660-a1.dts
index b380fef5152ce4..2b5294fe965c7b 100644
--- a/target/linux/ath79/dts/qca9557_dlink_dap-2660-a1.dts
+++ b/target/linux/ath79/dts/qca9557_dlink_dap-2660-a1.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca955x_dlink_dap-2xxx.dtsi"
 
 / {
@@ -27,12 +29,14 @@
 		compatible = "gpio-leds";
 
 		led_power_red: power_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
diff --git a/target/linux/ath79/dts/qca9557_dongwon_dw02-412h.dtsi b/target/linux/ath79/dts/qca9557_dongwon_dw02-412h.dtsi
index 31d86b1cf07f93..c7dd3cea99621f 100644
--- a/target/linux/ath79/dts/qca9557_dongwon_dw02-412h.dtsi
+++ b/target/linux/ath79/dts/qca9557_dongwon_dw02-412h.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -32,12 +33,14 @@
 		compatible = "gpio-leds";
 
 		led_wan: wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ath79/dts/qca9557_elecom_wab-s1167-ps.dts b/target/linux/ath79/dts/qca9557_elecom_wab-s1167-ps.dts
new file mode 100644
index 00000000000000..facead974d3e38
--- /dev/null
+++ b/target/linux/ath79/dts/qca9557_elecom_wab-s1167-ps.dts
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "qca955x_elecom_wab.dtsi"
+
+/ {
+	compatible = "elecom,wab-s1167-ps", "qca,qca9557";
+	model = "ELECOM WAB-S1167-PS";
+};
diff --git a/target/linux/ath79/dts/qca9557_elecom_wab-s600-ps.dts b/target/linux/ath79/dts/qca9557_elecom_wab-s600-ps.dts
new file mode 100644
index 00000000000000..8d4b1d3a852ebe
--- /dev/null
+++ b/target/linux/ath79/dts/qca9557_elecom_wab-s600-ps.dts
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "qca955x_elecom_wab.dtsi"
+
+/ {
+	compatible = "elecom,wab-s600-ps", "qca,qca9557";
+	model = "ELECOM WAB-S600-PS";
+};
diff --git a/target/linux/ath79/dts/qca9557_engenius_eap1200h.dts b/target/linux/ath79/dts/qca9557_engenius_eap1200h.dts
index da159caa20cc26..6fe518cbabe2e1 100644
--- a/target/linux/ath79/dts/qca9557_engenius_eap1200h.dts
+++ b/target/linux/ath79/dts/qca9557_engenius_eap1200h.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "engenius,eap1200h", "qca,qca9557";
@@ -32,7 +33,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
@@ -50,7 +52,8 @@
 		};
 
 		wps {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ath79/dts/qca9557_engenius_enstationac-v1.dts b/target/linux/ath79/dts/qca9557_engenius_enstationac-v1.dts
index 154744afd51767..c81d17d20a1e5c 100644
--- a/target/linux/ath79/dts/qca9557_engenius_enstationac-v1.dts
+++ b/target/linux/ath79/dts/qca9557_engenius_enstationac-v1.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "engenius,enstationac-v1", "qca,qca9557";
@@ -32,13 +33,15 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
@@ -76,6 +79,10 @@
 				reg = <0x0 0x6>;
 				#nvmem-cell-cells = <1>;
 			};
+
+			cal_art_5000: calibration@5000 {
+				reg = <0x5000 0x844>;
+			};
 		};
 	};
 };
@@ -124,4 +131,11 @@
 
 &pcie0 {
 	status = "okay";
+
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>, <&macaddr_art_0 2>;
+		nvmem-cell-names = "calibration", "mac-address";
+	};
 };
diff --git a/target/linux/ath79/dts/qca9557_engenius_esr1200.dts b/target/linux/ath79/dts/qca9557_engenius_esr1200.dts
index a70dc4739dfc74..fd805fa13f67da 100644
--- a/target/linux/ath79/dts/qca9557_engenius_esr1200.dts
+++ b/target/linux/ath79/dts/qca9557_engenius_esr1200.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca955x_senao_router-dual.dtsi"
 
 / {
@@ -17,7 +19,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
@@ -35,12 +38,14 @@
 		};
 
 		wps_amber {
-			label = "amber:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
 		};
 
 		wps_blue {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ath79/dts/qca9557_extreme-networks_ws-ap3805i.dts b/target/linux/ath79/dts/qca9557_extreme-networks_ws-ap3805i.dts
index 4a68f530751d8f..9df72df66ec7d5 100644
--- a/target/linux/ath79/dts/qca9557_extreme-networks_ws-ap3805i.dts
+++ b/target/linux/ath79/dts/qca9557_extreme-networks_ws-ap3805i.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "extreme-networks,ws-ap3805i", "qca,qca9557";
@@ -21,12 +22,14 @@
 		compatible = "gpio-leds";
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_amber: power_amber {
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
 		};
 
@@ -78,6 +81,8 @@
 	wifi@0,0 {
 		compatible = "qcom,ath10k";
 		reg = <0x0 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>;
+		nvmem-cell-names = "calibration";
 	};
 };
 
@@ -193,6 +198,16 @@
 				label = "art";
 				reg = <0x3fc0000 0x40000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_5000: calibration@5000 {
+						reg = <0x5000 0x844>;
+					};
+				};
 			};
 		};
 	};
diff --git a/target/linux/ath79/dts/qca9557_iodata_wn-ac-dgr.dtsi b/target/linux/ath79/dts/qca9557_iodata_wn-ac-dgr.dtsi
index 204a63cda8ddcf..097e1a87beb37d 100644
--- a/target/linux/ath79/dts/qca9557_iodata_wn-ac-dgr.dtsi
+++ b/target/linux/ath79/dts/qca9557_iodata_wn-ac-dgr.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -17,7 +18,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
@@ -140,6 +142,16 @@
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_5000: calibration@5000 {
+						reg = <0x5000 0x844>;
+					};
+				};
 			};
 		};
 	};
@@ -171,6 +183,8 @@
 	wifi@0,0 {
 		compatible = "pci168c,003c";
 		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>;
+		nvmem-cell-names = "calibration";
 	};
 };
 
diff --git a/target/linux/ath79/dts/qca9557_iodata_wn-ac1600dgr.dts b/target/linux/ath79/dts/qca9557_iodata_wn-ac1600dgr.dts
index 1e7d92db3fe22c..934422f5714e1e 100644
--- a/target/linux/ath79/dts/qca9557_iodata_wn-ac1600dgr.dts
+++ b/target/linux/ath79/dts/qca9557_iodata_wn-ac1600dgr.dts
@@ -22,3 +22,10 @@
 		debounce-interval = <60>;
 	};
 };
+
+&pcie1 {
+	wifi@0,0 {
+		/delete-property/ nvmem-cells;
+		/delete-property/ nvmem-cell-names;
+	};
+};
diff --git a/target/linux/ath79/dts/qca9557_meraki_mr18.dts b/target/linux/ath79/dts/qca9557_meraki_mr18.dts
index a88e2bcd377a10..1df5d6125cc4c5 100644
--- a/target/linux/ath79/dts/qca9557_meraki_mr18.dts
+++ b/target/linux/ath79/dts/qca9557_meraki_mr18.dts
@@ -22,12 +22,14 @@
 		compatible = "gpio-leds";
 
 		white: white {
-			label = "white:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
 		};
 
 		orange: orange {
-			label = "orange:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 21 GPIO_ACTIVE_HIGH>;
 			panic-indicator;
 		};
@@ -66,17 +68,14 @@
 
 #else
 		red {
-			label = "red:tricolor";
 			color = <LED_COLOR_ID_RED>;
 		};
 
 		green: green {
-			label = "green:tricolor";
 			color = <LED_COLOR_ID_GREEN>;
 		};
 
 		blue {
-			label = "blue:tricolor";
 			color = <LED_COLOR_ID_BLUE>;
 		};
 #endif
diff --git a/target/linux/ath79/dts/qca9557_zyxel_nbg6616.dts b/target/linux/ath79/dts/qca9557_zyxel_nbg6616.dts
index fff23dcf2ba95e..33fc3f1a070f4f 100644
--- a/target/linux/ath79/dts/qca9557_zyxel_nbg6616.dts
+++ b/target/linux/ath79/dts/qca9557_zyxel_nbg6616.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca955x_zyxel_nbg6x16.dtsi"
 
 / {
@@ -17,7 +19,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 		};
 
@@ -48,7 +51,8 @@
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -86,6 +90,16 @@
 				label = "art";
 				reg = <0x040000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_5000: calibration@5000 {
+						reg = <0x5000 0x844>;
+					};
+				};
 			};
 
 			partition@50000 {
@@ -118,6 +132,7 @@
 	wifi@0,0 {
 		compatible = "qcom,ath10k";
 		reg = <0 0 0 0 0>;
-		qca,no-eeprom;
+		nvmem-cells = <&cal_art_5000>;
+		nvmem-cell-names = "calibration";
 	};
 };
diff --git a/target/linux/ath79/dts/qca9558_allnet_all-wap02860ac.dts b/target/linux/ath79/dts/qca9558_allnet_all-wap02860ac.dts
index a6197fd25ae3d4..c6620969d10047 100644
--- a/target/linux/ath79/dts/qca9558_allnet_all-wap02860ac.dts
+++ b/target/linux/ath79/dts/qca9558_allnet_all-wap02860ac.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "allnet,all-wap02860ac", "qca,qca9558";
@@ -32,7 +33,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
@@ -50,7 +52,8 @@
 		};
 
 		wps {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -94,6 +97,10 @@
 				reg = <0x0 0x6>;
 				#nvmem-cell-cells = <1>;
 			};
+
+			cal_art_5000: calibration@5000 {
+				reg = <0x5000 0x844>;
+			};
 		};
 	};
 };
@@ -108,4 +115,11 @@
 
 &pcie0 {
 	status = "okay";
+
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>, <&macaddr_art_0 2>;
+		nvmem-cell-names = "calibration", "mac-address";
+	};
 };
diff --git a/target/linux/ath79/dts/qca9558_araknis_an-700-ap-i-ac.dts b/target/linux/ath79/dts/qca9558_araknis_an-700-ap-i-ac.dts
index 81a9e6ca086357..3906b82776b9c7 100644
--- a/target/linux/ath79/dts/qca9558_araknis_an-700-ap-i-ac.dts
+++ b/target/linux/ath79/dts/qca9558_araknis_an-700-ap-i-ac.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "araknis,an-700-ap-i-ac", "qca,qca9558";
@@ -30,7 +31,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
 			default-state = "off";
 		};
@@ -48,7 +50,8 @@
 		};
 
 		wps {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -59,6 +62,22 @@
 		label = "art";
 		reg = <0xff0000 0x010000>;
 		read-only;
+
+		nvmem-layout {
+			compatible = "fixed-layout";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			macaddr_art_0: macaddr@0 {
+				compatible = "mac-base";
+				reg = <0x0 0x6>;
+				#nvmem-cell-cells = <1>;
+			};
+
+			cal_art_5000: calibration@5000 {
+				reg = <0x5000 0x844>;
+			};
+		};
 	};
 };
 
@@ -94,18 +113,11 @@
 
 &pcie0 {
 	status = "okay";
-};
-
-&art {
-	nvmem-layout {
-		compatible = "fixed-layout";
-		#address-cells = <1>;
-		#size-cells = <1>;
 
-		macaddr_art_0: macaddr@0 {
-			compatible = "mac-base";
-			reg = <0x0 0x6>;
-			#nvmem-cell-cells = <1>;
-		};
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>, <&macaddr_art_0 2>;
+		nvmem-cell-names = "calibration", "mac-address";
 	};
 };
diff --git a/target/linux/ath79/dts/qca9558_aruba_ap-115.dts b/target/linux/ath79/dts/qca9558_aruba_ap-115.dts
index 9d9528245131f5..a5318b6cdd1876 100644
--- a/target/linux/ath79/dts/qca9558_aruba_ap-115.dts
+++ b/target/linux/ath79/dts/qca9558_aruba_ap-115.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "aruba,ap-115", "qca,qca9558";
@@ -36,12 +37,14 @@
 		compatible = "gpio-leds";
 
 		led_power_green: power-green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
 		};
 		
 		led_power_red: power-red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ath79/dts/qca9558_belkin_f9x-v2.dtsi b/target/linux/ath79/dts/qca9558_belkin_f9x-v2.dtsi
index b20a36a031900f..9048fd3e2f0523 100644
--- a/target/linux/ath79/dts/qca9558_belkin_f9x-v2.dtsi
+++ b/target/linux/ath79/dts/qca9558_belkin_f9x-v2.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/mtd/partitions/uimage.h>
 
 / {
@@ -26,17 +27,20 @@
 		};
 
 		status {
-			label = "amber:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 		};
 
 		wps-amber {
-			label = "amber:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		};
 
 		wps-blue {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ath79/dts/qca9558_comfast_cf-e380ac-v2.dts b/target/linux/ath79/dts/qca9558_comfast_cf-e380ac-v2.dts
index 8ce173f70dd0f4..febbccb4cb4ba0 100644
--- a/target/linux/ath79/dts/qca9558_comfast_cf-e380ac-v2.dts
+++ b/target/linux/ath79/dts/qca9558_comfast_cf-e380ac-v2.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "comfast,cf-e380ac-v2", "qca,qca9558";
@@ -35,7 +36,8 @@
 		pinctrl-0 = <&jtag_disable_pins>;
 
 		led_lan: lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
 		};
 
@@ -102,6 +104,10 @@
 						reg = <0x0 0x6>;
 						#nvmem-cell-cells = <1>;
 					};
+
+					cal_art_5000: calibration@5000 {
+						reg = <0x5000 0x844>;
+					};
 				};
 			};
 
@@ -136,6 +142,13 @@
 
 &pcie0 {
 	status = "okay";
+
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>, <&macaddr_art_0 2>;
+		nvmem-cell-names = "calibration", "mac-address";
+	};
 };
 
 &wdt {
diff --git a/target/linux/ath79/dts/qca9558_comfast_cf-wr650ac-v1.dts b/target/linux/ath79/dts/qca9558_comfast_cf-wr650ac-v1.dts
index e0471c534870a7..2e6f86b0b24f4f 100644
--- a/target/linux/ath79/dts/qca9558_comfast_cf-wr650ac-v1.dts
+++ b/target/linux/ath79/dts/qca9558_comfast_cf-wr650ac-v1.dts
@@ -7,6 +7,15 @@
 	model = "Comfast CF-WR650AC v1";
 };
 
+&pcie0 {
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>;
+		nvmem-cell-names = "calibration";
+	};
+};
+
 &spi {
 	status = "okay";
 
@@ -47,6 +56,10 @@
 					macaddr_art_18: macaddr@18 {
 						reg = <0x18 0x6>;
 					};
+
+					cal_art_5000: calibration@5000 {
+						reg = <0x5000 0x844>;
+					};
 				};
 			};
 
diff --git a/target/linux/ath79/dts/qca9558_comfast_cf-wr650ac-v2.dts b/target/linux/ath79/dts/qca9558_comfast_cf-wr650ac-v2.dts
index 9bbbf2a9b40db3..a4aa4118faf29a 100644
--- a/target/linux/ath79/dts/qca9558_comfast_cf-wr650ac-v2.dts
+++ b/target/linux/ath79/dts/qca9558_comfast_cf-wr650ac-v2.dts
@@ -7,6 +7,17 @@
 	model = "Comfast CF-WR650AC v2";
 };
 
+&pcie0 {
+	status = "okay";
+
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>;
+		nvmem-cell-names = "calibration";
+	};
+};
+
 &spi {
 	status = "okay";
 
@@ -47,6 +58,10 @@
 					macaddr_art_18: macaddr@18 {
 						reg = <0x18 0x6>;
 					};
+
+					cal_art_5000: calibration@5000 {
+						reg = <0x5000 0x844>;
+					};
 				};
 			};
 
diff --git a/target/linux/ath79/dts/qca9558_comfast_cf-wr650ac.dtsi b/target/linux/ath79/dts/qca9558_comfast_cf-wr650ac.dtsi
index 4daad4b0b012cb..7bcadb2adaf4cd 100644
--- a/target/linux/ath79/dts/qca9558_comfast_cf-wr650ac.dtsi
+++ b/target/linux/ath79/dts/qca9558_comfast_cf-wr650ac.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	keys {
@@ -21,7 +22,8 @@
 		compatible = "gpio-leds";
 
 		wps {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 20 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ath79/dts/qca9558_devolo_dvl1200e.dts b/target/linux/ath79/dts/qca9558_devolo_dvl1200e.dts
index d98600934ad60d..ec9d5cc6557d23 100644
--- a/target/linux/ath79/dts/qca9558_devolo_dvl1200e.dts
+++ b/target/linux/ath79/dts/qca9558_devolo_dvl1200e.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca9558_devolo_dvl1xxx.dtsi"
 
 / {
@@ -17,13 +19,15 @@
 		compatible = "gpio-leds";
 
 		led_status_blue: status_blue {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		led_status_red: status_red {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ath79/dts/qca9558_devolo_dvl1200i.dts b/target/linux/ath79/dts/qca9558_devolo_dvl1200i.dts
index 97687f1ce3ad13..dfef71e6d7c5cf 100644
--- a/target/linux/ath79/dts/qca9558_devolo_dvl1200i.dts
+++ b/target/linux/ath79/dts/qca9558_devolo_dvl1200i.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca9558_devolo_dvl1xxx.dtsi"
 
 / {
@@ -17,13 +19,15 @@
 		compatible = "gpio-leds";
 
 		led_status_blue: status_blue {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		led_status_red: status_red {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ath79/dts/qca9558_devolo_dvl1750c.dts b/target/linux/ath79/dts/qca9558_devolo_dvl1750c.dts
index ee6d35685eff81..8d4bbe3ef2da20 100644
--- a/target/linux/ath79/dts/qca9558_devolo_dvl1750c.dts
+++ b/target/linux/ath79/dts/qca9558_devolo_dvl1750c.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca9558_devolo_dvl1xxx.dtsi"
 
 / {
@@ -17,13 +19,15 @@
 		compatible = "gpio-leds";
 
 		led_status_blue: status_blue {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		led_status_red: status_red {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ath79/dts/qca9558_devolo_dvl1750e.dts b/target/linux/ath79/dts/qca9558_devolo_dvl1750e.dts
index c5209046173f01..25760c8ccfa569 100644
--- a/target/linux/ath79/dts/qca9558_devolo_dvl1750e.dts
+++ b/target/linux/ath79/dts/qca9558_devolo_dvl1750e.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca9558_devolo_dvl1xxx.dtsi"
 
 / {
@@ -34,13 +36,15 @@
 		compatible = "gpio-leds";
 
 		led_status_blue: status_blue {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		led_status_red: status_red {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ath79/dts/qca9558_devolo_dvl1750i.dts b/target/linux/ath79/dts/qca9558_devolo_dvl1750i.dts
index 2b808ce9213b8e..aac5d4612fdf01 100644
--- a/target/linux/ath79/dts/qca9558_devolo_dvl1750i.dts
+++ b/target/linux/ath79/dts/qca9558_devolo_dvl1750i.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca9558_devolo_dvl1xxx.dtsi"
 
 / {
@@ -17,13 +19,15 @@
 		compatible = "gpio-leds";
 
 		led_status_blue: status_blue {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		led_status_red: status_red {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ath79/dts/qca9558_devolo_dvl1750x.dts b/target/linux/ath79/dts/qca9558_devolo_dvl1750x.dts
index 747a1a46d303c9..4db10ac776ca2f 100644
--- a/target/linux/ath79/dts/qca9558_devolo_dvl1750x.dts
+++ b/target/linux/ath79/dts/qca9558_devolo_dvl1750x.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca9558_devolo_dvl1xxx.dtsi"
 
 / {
@@ -18,12 +20,14 @@
 
 		led_status_red: status_red {
 			/* This LED is not visible on the external casing. */
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/qca9558_devolo_dvl1xxx.dtsi b/target/linux/ath79/dts/qca9558_devolo_dvl1xxx.dtsi
index 9a2579dd941b3a..9fea2589701460 100644
--- a/target/linux/ath79/dts/qca9558_devolo_dvl1xxx.dtsi
+++ b/target/linux/ath79/dts/qca9558_devolo_dvl1xxx.dtsi
@@ -38,6 +38,13 @@
 
 &pcie0 {
 	status = "okay";
+
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>, <&macaddr_art_0 (-1)>;
+		nvmem-cell-names = "calibration", "mac-address";
+	};
 };
 
 &spi {
@@ -80,6 +87,10 @@
 						reg = <0x0 0x6>;
 						#nvmem-cell-cells = <1>;
 					};
+
+					cal_art_5000: calibration@5000 {
+						reg = <0x5000 0x844>;
+					};
 				};
 			};
 
diff --git a/target/linux/ath79/dts/qca9558_dlink_dap-2680-a1.dts b/target/linux/ath79/dts/qca9558_dlink_dap-2680-a1.dts
index d32329b3660dce..4cee284f31fa94 100644
--- a/target/linux/ath79/dts/qca9558_dlink_dap-2680-a1.dts
+++ b/target/linux/ath79/dts/qca9558_dlink_dap-2680-a1.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca955x_dlink_dap-2xxx.dtsi"
 
 / {
@@ -27,12 +29,14 @@
 		compatible = "gpio-leds";
 
 		led_power_red: power_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 20 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
diff --git a/target/linux/ath79/dts/qca9558_dlink_dap-2695-a1.dts b/target/linux/ath79/dts/qca9558_dlink_dap-2695-a1.dts
index 3ca641a550700c..6f23fbec46489c 100644
--- a/target/linux/ath79/dts/qca9558_dlink_dap-2695-a1.dts
+++ b/target/linux/ath79/dts/qca9558_dlink_dap-2695-a1.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca955x_dlink_dap-2xxx.dtsi"
 
 / {
@@ -17,13 +19,15 @@
 		compatible = "gpio-leds";
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		led_power_red: power_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ath79/dts/qca9558_dlink_dap-3662-a1.dts b/target/linux/ath79/dts/qca9558_dlink_dap-3662-a1.dts
index e72af99da24341..2cdfd2cff93f79 100644
--- a/target/linux/ath79/dts/qca9558_dlink_dap-3662-a1.dts
+++ b/target/linux/ath79/dts/qca9558_dlink_dap-3662-a1.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca955x_dlink_dap-2xxx.dtsi"
 
 / {
@@ -27,12 +29,14 @@
 		compatible = "gpio-leds";
 
 		led_power_red: power_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
diff --git a/target/linux/ath79/dts/qca9558_dlink_dir-629-a1.dts b/target/linux/ath79/dts/qca9558_dlink_dir-629-a1.dts
index e5c2cbcb72c75a..137bff732cf8b6 100644
--- a/target/linux/ath79/dts/qca9558_dlink_dir-629-a1.dts
+++ b/target/linux/ath79/dts/qca9558_dlink_dir-629-a1.dts
@@ -46,7 +46,6 @@
 		};
 
 		led_power: led-1 {
-			label = "green:power";
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_POWER;
 			gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
diff --git a/target/linux/ath79/dts/qca9558_domywifi_dw33d.dts b/target/linux/ath79/dts/qca9558_domywifi_dw33d.dts
index 73f4ed0d1e1dd0..765cfafe15ea83 100644
--- a/target/linux/ath79/dts/qca9558_domywifi_dw33d.dts
+++ b/target/linux/ath79/dts/qca9558_domywifi_dw33d.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "domywifi,dw33d", "qca,qca9558";
@@ -32,7 +33,8 @@
 		};
 
 		usb {
-			label = "blue:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&hub_port1>;
 			linux,default-trigger = "usbport";
@@ -68,6 +70,8 @@
 	wifi@0,0 {
 		compatible = "qcom,ath10k";
 		reg = <0 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>, <&macaddr_art_12>;
+		nvmem-cell-names = "calibration", "mac-address";
 	};
 };
 
@@ -137,6 +141,14 @@
 					macaddr_art_c: macaddr@c {
 						reg = <0xc 0x6>;
 					};
+
+					macaddr_art_12: macaddr@12 {
+						reg = <0x12 0x6>;
+					};
+
+					cal_art_5000: calibration@5000 {
+						reg = <0x5000 0x844>;
+					};
 				};
 			};
 		};
diff --git a/target/linux/ath79/dts/qca9558_elecom_wab-i1750-ps.dts b/target/linux/ath79/dts/qca9558_elecom_wab-i1750-ps.dts
new file mode 100644
index 00000000000000..6f157cf9322fd6
--- /dev/null
+++ b/target/linux/ath79/dts/qca9558_elecom_wab-i1750-ps.dts
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "qca955x_elecom_wab.dtsi"
+
+/ {
+	compatible = "elecom,wab-i1750-ps", "qca,qca9558";
+	model = "ELECOM WAB-I1750-PS";
+
+	ahb {
+		apb {
+			/* "SERIAL" port (RJ-45) on the case */
+			uart1: uart@18500000 {
+				compatible = "qca,ar9330-uart";
+				reg = <0x18500000 0x14>;
+
+				pinctrl-names = "default";
+				pinctrl-0 = <&pmx_uart1_in_pins &pmx_uart1_out_pins
+					     &jtag_disable_pins>;
+
+				interrupts = <6>;
+				interrupt-parent = <&miscintc>;
+
+				clocks = <&pll ATH79_CLK_UART1>;
+				clock-names = "uart";
+
+				/* QCA955x HS UART is not supported */
+				status = "disabled";
+			};
+		};
+	};
+};
+
+&gpio {
+	uart1-out {
+		gpio-hog;
+		gpios = <0 GPIO_ACTIVE_HIGH>,	/* UART1_TD */
+			<2 GPIO_ACTIVE_HIGH>;	/* UART1_RTS */
+		output-low;
+	};
+
+	uart1-in {
+		gpio-hog;
+		gpios = <1 GPIO_ACTIVE_HIGH>,	/* UART1_RD */
+			<3 GPIO_ACTIVE_HIGH>;	/* UART1_CTS */
+		input;
+	};
+};
+
+&pinmux {
+	pmx_uart1_out_pins: uart1-out-pins {
+		/*
+		 * mux as uart1 output
+		 *
+		 * GPIO0: UART1_TD (sel:18)
+		 * GPIO2: UART1_RTS (sel:19)
+		 */
+		pinctrl-single,bits = <0x0 0x130012 0xff00ff>;
+	};
+
+	pmx_uart1_in_pins: uart1-in-pins {
+		/*
+		 * mux as uart1 input
+		 *
+		 * GPIO1: UART1_RD
+		 * GPIO3: UART1_CTS
+		 */
+		pinctrl-single,bits = <0x3c 0x3010000 0xffff0000>;
+	};
+};
diff --git a/target/linux/ath79/dts/qca9558_engenius_eap1750h.dts b/target/linux/ath79/dts/qca9558_engenius_eap1750h.dts
index 56c08621a7465b..ea43eb0e6754ae 100644
--- a/target/linux/ath79/dts/qca9558_engenius_eap1750h.dts
+++ b/target/linux/ath79/dts/qca9558_engenius_eap1750h.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "engenius,eap1750h", "qca,qca9558";
@@ -32,7 +33,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
@@ -50,7 +52,8 @@
 		};
 
 		wps {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ath79/dts/qca9558_engenius_epg5000.dts b/target/linux/ath79/dts/qca9558_engenius_epg5000.dts
index 36aba0714e4e13..52708f3c6b2015 100644
--- a/target/linux/ath79/dts/qca9558_engenius_epg5000.dts
+++ b/target/linux/ath79/dts/qca9558_engenius_epg5000.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca955x_senao_router-dual.dtsi"
 
 / {
@@ -17,7 +19,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
@@ -35,12 +38,14 @@
 		};
 
 		wps_amber {
-			label = "amber:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
 		};
 
 		wps_blue {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ath79/dts/qca9558_engenius_esr1750.dts b/target/linux/ath79/dts/qca9558_engenius_esr1750.dts
index 4cfdfc1f280279..0aae9b5187c2e4 100644
--- a/target/linux/ath79/dts/qca9558_engenius_esr1750.dts
+++ b/target/linux/ath79/dts/qca9558_engenius_esr1750.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca955x_senao_router-dual.dtsi"
 
 / {
@@ -17,7 +19,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
@@ -35,12 +38,14 @@
 		};
 
 		wps_amber {
-			label = "amber:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
 		};
 
 		wps_blue {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ath79/dts/qca9558_engenius_esr900.dts b/target/linux/ath79/dts/qca9558_engenius_esr900.dts
index ef0e21a3b59ff1..39a0790f121e15 100644
--- a/target/linux/ath79/dts/qca9558_engenius_esr900.dts
+++ b/target/linux/ath79/dts/qca9558_engenius_esr900.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca955x_senao_router-dual.dtsi"
 
 / {
@@ -17,7 +19,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
@@ -35,12 +38,14 @@
 		};
 
 		wps_amber {
-			label = "amber:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
 		};
 
 		wps_blue {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ath79/dts/qca9558_jjplus_jwap230.dts b/target/linux/ath79/dts/qca9558_jjplus_jwap230.dts
index ee2e82ef10b588..0f3c23d4748fdb 100644
--- a/target/linux/ath79/dts/qca9558_jjplus_jwap230.dts
+++ b/target/linux/ath79/dts/qca9558_jjplus_jwap230.dts
@@ -21,7 +21,6 @@
 		compatible = "gpio-leds";
 
 		led_power: led-0 {
-			label = "green:power";
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_POWER;
 			gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
diff --git a/target/linux/ath79/dts/qca9558_librerouter_librerouter-v1.dts b/target/linux/ath79/dts/qca9558_librerouter_librerouter-v1.dts
index 5ee38b2e884c78..333b52f4d9150e 100644
--- a/target/linux/ath79/dts/qca9558_librerouter_librerouter-v1.dts
+++ b/target/linux/ath79/dts/qca9558_librerouter_librerouter-v1.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "librerouter,librerouter-v1", "qca,qca9558";
@@ -32,7 +33,8 @@
 		};
 
 		status_blue {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 20 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ath79/dts/qca9558_netgear_ex7300.dts b/target/linux/ath79/dts/qca9558_netgear_ex7300.dts
index 81898e972f095f..3c9141fcba6d5e 100644
--- a/target/linux/ath79/dts/qca9558_netgear_ex7300.dts
+++ b/target/linux/ath79/dts/qca9558_netgear_ex7300.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Netgear EX7300";
@@ -47,12 +48,14 @@
 		compatible = "gpio-leds";
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_amber: power_amber {
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 20 GPIO_ACTIVE_LOW>;
 		};
 
@@ -67,7 +70,8 @@
 		};
 
 		wps_green {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&led_gpio 5 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ath79/dts/qca9558_ocedo_koala.dts b/target/linux/ath79/dts/qca9558_ocedo_koala.dts
index 76305b2ecef2f5..891bdd95c43c52 100644
--- a/target/linux/ath79/dts/qca9558_ocedo_koala.dts
+++ b/target/linux/ath79/dts/qca9558_ocedo_koala.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "ocedo,koala", "qca,qca9558";
@@ -21,7 +22,8 @@
 		compatible = "gpio-leds";
 
 		power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
@@ -57,6 +59,13 @@
 
 &pcie0 {
 	status = "okay";
+
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>, <&macaddr_art_c>;
+		nvmem-cell-names = "calibration", "mac-address";
+	};
 };
 
 &spi {
@@ -119,6 +128,14 @@
 					macaddr_art_6: macaddr@6 {
 						reg = <0x6 0x6>;
 					};
+
+					macaddr_art_c: macaddr@c {
+						reg = <0xc 0x6>;
+					};
+
+					cal_art_5000: calibration@5000 {
+						reg = <0x5000 0x844>;
+					};
 				};
 			};
 		};
diff --git a/target/linux/ath79/dts/qca9558_ocedo_ursus.dts b/target/linux/ath79/dts/qca9558_ocedo_ursus.dts
index d2125c38ba302e..8ddeccefb73383 100644
--- a/target/linux/ath79/dts/qca9558_ocedo_ursus.dts
+++ b/target/linux/ath79/dts/qca9558_ocedo_ursus.dts
@@ -28,6 +28,13 @@
 
 &pcie1 {
 	status = "okay";
+
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>, <&macaddr_art_c>;
+		nvmem-cell-names = "calibration", "mac-address";
+	};
 };
 
 &spi {
@@ -91,9 +98,17 @@
 						reg = <0x6 0x6>;
 					};
 
+					macaddr_art_c: macaddr@c {
+						reg = <0xc 0x6>;
+					};
+
 					macaddr_art_12: macaddr@12 {
 						reg = <0x12 0x6>;
 					};
+
+					cal_art_5000: calibration@5000 {
+						reg = <0x5000 0x844>;
+					};
 				};
 			};
 		};
diff --git a/target/linux/ath79/dts/qca9558_openmesh_a60.dtsi b/target/linux/ath79/dts/qca9558_openmesh_a60.dtsi
index 32a176b542e483..11a6e81f9f28f4 100644
--- a/target/linux/ath79/dts/qca9558_openmesh_a60.dtsi
+++ b/target/linux/ath79/dts/qca9558_openmesh_a60.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	chosen {
@@ -33,17 +34,20 @@
 		compatible = "gpio-leds";
 
 		status_blue {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 13 GPIO_ACTIVE_HIGH>;
 		};
 
 		status_red {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_status_green: status_green {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
 		};
 	};
@@ -126,6 +130,10 @@
 					macaddr_art_6: macaddr@6 {
 						reg = <0x6 0x6>;
 					};
+
+					cal_art_5000: calibration@5000 {
+						reg = <0x5000 0x844>;
+					};
 				};
 			};
 		};
@@ -193,4 +201,11 @@
 
 &pcie0 {
 	status = "okay";
+
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>, <&macaddr_art_0 16>;
+		nvmem-cell-names = "calibration", "mac-address";
+	};
 };
diff --git a/target/linux/ath79/dts/qca9558_openmesh_mr.dtsi b/target/linux/ath79/dts/qca9558_openmesh_mr.dtsi
index 218d5eb944d51b..a5d3d3798788cb 100644
--- a/target/linux/ath79/dts/qca9558_openmesh_mr.dtsi
+++ b/target/linux/ath79/dts/qca9558_openmesh_mr.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	chosen {
@@ -33,7 +34,8 @@
 		compatible = "gpio-leds";
 
 		lan_blue {
-			label = "blue:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
 		};
 
@@ -43,17 +45,20 @@
 		};
 
 		status_green {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
 		};
 
 		status_red {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_blue: power_blue {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
@@ -130,6 +135,10 @@
 						reg = <0x0 0x6>;
 						#nvmem-cell-cells = <1>;
 					};
+
+					cal_art_5000: calibration@5000 {
+						reg = <0x5000 0x844>;
+					};
 				};
 			};
 		};
@@ -173,4 +182,11 @@
 
 &pcie0 {
 	status = "okay";
+
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>, <&macaddr_art_0 16>;
+		nvmem-cell-names = "calibration", "mac-address";
+	};
 };
diff --git a/target/linux/ath79/dts/qca9558_openmesh_mr900-v1.dts b/target/linux/ath79/dts/qca9558_openmesh_mr900-v1.dts
index 8ef3241ee0dcc9..e10e364219dcc7 100644
--- a/target/linux/ath79/dts/qca9558_openmesh_mr900-v1.dts
+++ b/target/linux/ath79/dts/qca9558_openmesh_mr900-v1.dts
@@ -16,6 +16,8 @@
 };
 
 &pcie0 {
+	/delete-node/ wifi@0,0;
+
 	wifi@0,0 {
 		compatible = "pci168c,0033";
 		reg = <0x0000 0 0 0 0>;
diff --git a/target/linux/ath79/dts/qca9558_openmesh_mr900-v2.dts b/target/linux/ath79/dts/qca9558_openmesh_mr900-v2.dts
index cd3baacd158404..3198ad2aa90b93 100644
--- a/target/linux/ath79/dts/qca9558_openmesh_mr900-v2.dts
+++ b/target/linux/ath79/dts/qca9558_openmesh_mr900-v2.dts
@@ -16,6 +16,8 @@
 };
 
 &pcie0 {
+	/delete-node/ wifi@0,0;
+
 	wifi@0,0 {
 		compatible = "pci168c,0033";
 		reg = <0x0000 0 0 0 0>;
diff --git a/target/linux/ath79/dts/qca9558_openmesh_om5p-ac-v1.dts b/target/linux/ath79/dts/qca9558_openmesh_om5p-ac-v1.dts
index ee4b82ee8d9de4..f7c51578ba9aa6 100644
--- a/target/linux/ath79/dts/qca9558_openmesh_om5p-ac-v1.dts
+++ b/target/linux/ath79/dts/qca9558_openmesh_om5p-ac-v1.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "openmesh,om5p-ac-v1", "qca,qca9558";
@@ -26,18 +27,21 @@
 		compatible = "gpio-leds";
 
 		led_power_blue: power_blue {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		wan_blue {
-			label = "blue:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
 		};
 
 		lan_blue {
-			label = "blue:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 20 GPIO_ACTIVE_LOW>;
 		};
 
@@ -145,6 +149,10 @@
 					macaddr_art_6: macaddr@6 {
 						reg = <0x6 0x6>;
 					};
+
+					cal_art_5000: calibration@5000 {
+						reg = <0x5000 0x844>;
+					};
 				};
 			};
 		};
@@ -212,4 +220,11 @@
 
 &pcie1 {
 	status = "okay";
+
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>, <&macaddr_art_0 16>;
+		nvmem-cell-names = "calibration", "mac-address";
+	};
 };
diff --git a/target/linux/ath79/dts/qca9558_openmesh_om5p-ac-v2.dts b/target/linux/ath79/dts/qca9558_openmesh_om5p-ac-v2.dts
index d448ca4284500b..b9eb0e91a9b6ad 100644
--- a/target/linux/ath79/dts/qca9558_openmesh_om5p-ac-v2.dts
+++ b/target/linux/ath79/dts/qca9558_openmesh_om5p-ac-v2.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "openmesh,om5p-ac-v2", "qca,qca9558";
@@ -32,7 +33,8 @@
 		};
 
 		led_power_blue: power_blue {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
@@ -113,6 +115,13 @@
 
 &pcie0 {
 	status = "okay";
+
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>, <&macaddr_art_0 16>;
+		nvmem-cell-names = "calibration", "mac-address";
+	};
 };
 
 &spi {
@@ -175,6 +184,10 @@
 					macaddr_art_6: macaddr@6 {
 						reg = <0x6 0x6>;
 					};
+
+					cal_art_5000: calibration@5000 {
+						reg = <0x5000 0x844>;
+					};
 				};
 			};
 		};
diff --git a/target/linux/ath79/dts/qca9558_qxwlan_e558.dtsi b/target/linux/ath79/dts/qca9558_qxwlan_e558.dtsi
index 716bc0d77b60c7..9cbdca234d9bd6 100644
--- a/target/linux/ath79/dts/qca9558_qxwlan_e558.dtsi
+++ b/target/linux/ath79/dts/qca9558_qxwlan_e558.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -29,7 +30,8 @@
 		compatible = "gpio-leds";
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/qca9558_sitecom_wlr-8100.dts b/target/linux/ath79/dts/qca9558_sitecom_wlr-8100.dts
index 01a69fce15de0a..2a57eeec775211 100644
--- a/target/linux/ath79/dts/qca9558_sitecom_wlr-8100.dts
+++ b/target/linux/ath79/dts/qca9558_sitecom_wlr-8100.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Sitecom WLR-8100 (X8 AC1750)";
@@ -36,7 +37,8 @@
 		compatible = "gpio-leds";
 
 		led_status_amber: status_amber {
-			label = "amber:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
@@ -113,6 +115,16 @@
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_5000: calibration@5000 {
+						reg = <0x5000 0x844>;
+					};
+				};
 			};
 		};
 	};
@@ -128,6 +140,8 @@
 	wifi@0,0 {
 		compatible = "qcom,ath10k";
 		reg = <0 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>;
+		nvmem-cell-names = "calibration";
 	};
 };
 
diff --git a/target/linux/ath79/dts/qca9558_sophos_ap.dtsi b/target/linux/ath79/dts/qca9558_sophos_ap.dtsi
index 0cf5eb6e6631f5..92e89ff3aa797e 100644
--- a/target/linux/ath79/dts/qca9558_sophos_ap.dtsi
+++ b/target/linux/ath79/dts/qca9558_sophos_ap.dtsi
@@ -17,6 +17,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -46,13 +47,15 @@
 		compatible = "gpio-leds";
 
 		led_status_green: status_green {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		led_status_red: status_red {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -71,6 +74,13 @@
 
 &pcie0 {
 	status = "okay";
+
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>;
+		nvmem-cell-names = "calibration";
+	};
 };
 
 &spi {
@@ -101,6 +111,16 @@
 				label = "art";
 				reg = <0x050000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_5000: calibration@5000 {
+						reg = <0x5000 0x844>;
+					};
+				};
 			};
 
 			config: partition@60000 {
diff --git a/target/linux/ath79/dts/qca9558_sophos_ap15.dts b/target/linux/ath79/dts/qca9558_sophos_ap15.dts
index 490d3ae2276758..5801303040f9ce 100644
--- a/target/linux/ath79/dts/qca9558_sophos_ap15.dts
+++ b/target/linux/ath79/dts/qca9558_sophos_ap15.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "sophos,ap15", "qca,qca9558";
@@ -25,13 +26,15 @@
 		compatible = "gpio-leds";
 
 		led_status_green: status_green {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		led_status_yellow: status_yellow {
-			label = "yellow:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_YELLOW>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -39,6 +42,13 @@
 
 &pcie0 {
 	status = "okay";
+
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>;
+		nvmem-cell-names = "calibration";
+	};
 };
 
 &spi {
@@ -69,6 +79,16 @@
 				label = "art";
 				reg = <0x050000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_5000: calibration@5000 {
+						reg = <0x5000 0x844>;
+					};
+				};
 			};
 
 			config: partition@60000 {
diff --git a/target/linux/ath79/dts/qca9558_tplink_archer-c5-v1.dts b/target/linux/ath79/dts/qca9558_tplink_archer-c5-v1.dts
index d41b065c27e049..584a66ba524b18 100644
--- a/target/linux/ath79/dts/qca9558_tplink_archer-c5-v1.dts
+++ b/target/linux/ath79/dts/qca9558_tplink_archer-c5-v1.dts
@@ -57,6 +57,16 @@
 		label = "art";
 		reg = <0xff0000 0x010000>;
 		read-only;
+
+		nvmem-layout {
+			compatible = "fixed-layout";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			cal_art_5000: calibration@5000 {
+				reg = <0x5000 0x844>;
+			};
+		};
 	};
 };
 
@@ -70,6 +80,15 @@
 	nvmem-cell-names = "mac-address";
 };
 
+&pcie1 {
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>, <&macaddr_uboot_1fc00 (-1)>;
+		nvmem-cell-names = "calibration", "mac-address";
+	};
+};
+
 &wmac {
 	mtd-cal-data = <&art 0x1000>;
 
diff --git a/target/linux/ath79/dts/qca9558_tplink_archer-d7-v1.dts b/target/linux/ath79/dts/qca9558_tplink_archer-d7-v1.dts
index 5869ee16e39ca2..20cefe0b793c20 100644
--- a/target/linux/ath79/dts/qca9558_tplink_archer-d7-v1.dts
+++ b/target/linux/ath79/dts/qca9558_tplink_archer-d7-v1.dts
@@ -11,6 +11,15 @@
 	};
 };
 
+&pcie1 {
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>, <&macaddr_romfs_f100 2>;
+		nvmem-cell-names = "calibration", "mac-address";
+	};
+};
+
 &spi {
 	status = "okay";
 
@@ -76,6 +85,16 @@
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_5000: calibration@5000 {
+						reg = <0x5000 0x844>;
+					};
+				};
 			};
 		};
 	};
diff --git a/target/linux/ath79/dts/qca9558_tplink_archer-d7.dtsi b/target/linux/ath79/dts/qca9558_tplink_archer-d7.dtsi
index 35532f42c8b630..b4f32b9fc7c9ce 100644
--- a/target/linux/ath79/dts/qca9558_tplink_archer-d7.dtsi
+++ b/target/linux/ath79/dts/qca9558_tplink_archer-d7.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -23,17 +24,20 @@
 		};
 
 		wlan {
-			label = "white:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
 		};
 
 		lan {
-			label = "white:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
 		};
 
 		usb {
-			label = "white:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&hub_port1>, <&hub_port0>;
 			linux,default-trigger = "usbport";
diff --git a/target/linux/ath79/dts/qca9558_tplink_archer-d7b-v1.dts b/target/linux/ath79/dts/qca9558_tplink_archer-d7b-v1.dts
index 7094077bc6f184..3418601c41e126 100644
--- a/target/linux/ath79/dts/qca9558_tplink_archer-d7b-v1.dts
+++ b/target/linux/ath79/dts/qca9558_tplink_archer-d7b-v1.dts
@@ -11,6 +11,15 @@
 	};
 };
 
+&pcie1 {
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>, <&macaddr_romfs_f100 2>;
+		nvmem-cell-names = "calibration", "mac-address";
+	};
+};
+
 &spi {
 	status = "okay";
 
@@ -70,6 +79,16 @@
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_5000: calibration@5000 {
+						reg = <0x5000 0x844>;
+					};
+				};
 			};
 		};
 	};
diff --git a/target/linux/ath79/dts/qca9558_tplink_re350k-v1.dts b/target/linux/ath79/dts/qca9558_tplink_re350k-v1.dts
index 7c48326d576fb9..a3fb9b22d22792 100644
--- a/target/linux/ath79/dts/qca9558_tplink_re350k-v1.dts
+++ b/target/linux/ath79/dts/qca9558_tplink_re350k-v1.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "TP-Link RE350K v1";
@@ -46,7 +47,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
@@ -99,7 +101,7 @@
 	phy-handle = <&phy4>;
 	pll-data = <0x9e000000 0x80000101 0x80001313>;
 
-	nvmem-cells = <&macaddr_info_8>;
+	nvmem-cells = <&macaddr_info_8 0>;
 	nvmem-cell-names = "mac-address";
 
 	gmac-config {
@@ -115,6 +117,13 @@
 
 &pcie0 {
 	status = "okay";
+
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>, <&macaddr_info_8 2>;
+		nvmem-cell-names = "calibration", "mac-address";
+	};
 };
 
 &spi {
@@ -159,7 +168,9 @@
 					#size-cells = <1>;
 
 					macaddr_info_8: macaddr@8 {
+						compatible = "mac-base";
 						reg = <0x8 0x6>;
+						#nvmem-cell-cells = <1>;
 					};
 				};
 			};
@@ -174,6 +185,16 @@
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_5000: calibration@5000 {
+						reg = <0x5000 0x844>;
+					};
+				};
 			};
 		};
 	};
@@ -183,6 +204,6 @@
 	status = "okay";
 
 	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_info_8>;
+	nvmem-cells = <&macaddr_info_8 0>;
 	nvmem-cell-names = "mac-address";
 };
diff --git a/target/linux/ath79/dts/qca9558_tplink_rex5x.dtsi b/target/linux/ath79/dts/qca9558_tplink_rex5x.dtsi
index f90ebfea155738..3061ae07c7cba1 100644
--- a/target/linux/ath79/dts/qca9558_tplink_rex5x.dtsi
+++ b/target/linux/ath79/dts/qca9558_tplink_rex5x.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -19,7 +20,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
 		};
 
@@ -46,12 +48,14 @@
 		};
 
 		wps_blue {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 21 GPIO_ACTIVE_HIGH>;
 		};
 
 		wps_red {
-			label = "red:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
 		};
 	};
@@ -98,6 +102,13 @@
 
 &pcie0 {
 	status = "okay";
+
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>, <&macaddr_info_8 (-2)>;
+		nvmem-cell-names = "calibration", "mac-address";
+	};
 };
 
 &spi {
@@ -159,6 +170,16 @@
 				label = "art";
 				reg = <0x7f0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_5000: calibration@5000 {
+						reg = <0x5000 0x844>;
+					};
+				};
 			};
 		};
 	};
diff --git a/target/linux/ath79/dts/qca9558_tplink_tl-wdr7500-v3.dts b/target/linux/ath79/dts/qca9558_tplink_tl-wdr7500-v3.dts
index 99a4273ad0db4a..33697d3b836e7d 100644
--- a/target/linux/ath79/dts/qca9558_tplink_tl-wdr7500-v3.dts
+++ b/target/linux/ath79/dts/qca9558_tplink_tl-wdr7500-v3.dts
@@ -57,6 +57,16 @@
 		label = "art";
 		reg = <0x7f0000 0x010000>;
 		read-only;
+
+		nvmem-layout {
+			compatible = "fixed-layout";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			cal_art_5000: calibration@5000 {
+				reg = <0x5000 0x844>;
+			};
+		};
 	};
 };
 
@@ -70,6 +80,15 @@
 	nvmem-cell-names = "mac-address";
 };
 
+&pcie1 {
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>, <&macaddr_uboot_1fc00 (-1)>;
+		nvmem-cell-names = "calibration", "mac-address";
+	};
+};
+
 &wmac {
 	mtd-cal-data = <&art 0x1000>;
 
diff --git a/target/linux/ath79/dts/qca9558_tplink_tl-wr1043nd.dtsi b/target/linux/ath79/dts/qca9558_tplink_tl-wr1043nd.dtsi
index f4390f46568102..a72b6e6050d195 100644
--- a/target/linux/ath79/dts/qca9558_tplink_tl-wr1043nd.dtsi
+++ b/target/linux/ath79/dts/qca9558_tplink_tl-wr1043nd.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -24,20 +25,23 @@
 		};
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&hub_port0>;
 			linux,default-trigger = "usbport";
 		};
 
 		wifi_green {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
 
 		wifi_wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ath79/dts/qca9558_tplink_tl-wr941n-v7-cn.dts b/target/linux/ath79/dts/qca9558_tplink_tl-wr941n-v7-cn.dts
index 9d329000c9bd99..f51b89206d6279 100644
--- a/target/linux/ath79/dts/qca9558_tplink_tl-wr941n-v7-cn.dts
+++ b/target/linux/ath79/dts/qca9558_tplink_tl-wr941n-v7-cn.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "tplink,tl-wr941n-v7-cn", "qca,qca9558";
@@ -27,7 +28,8 @@
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/qca9558_trendnet_tew-823dru.dts b/target/linux/ath79/dts/qca9558_trendnet_tew-823dru.dts
index 176fe97cc0a96e..23b484cdf58eb3 100644
--- a/target/linux/ath79/dts/qca9558_trendnet_tew-823dru.dts
+++ b/target/linux/ath79/dts/qca9558_trendnet_tew-823dru.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "trendnet,tew-823dru", "qca,qca9558";
@@ -20,12 +21,14 @@
 		compatible = "gpio-leds";
 
 		power_orange {
-			label = "orange:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ath79/dts/qca9558_ubnt_nanobeam-ac-xc.dts b/target/linux/ath79/dts/qca9558_ubnt_nanobeam-ac-xc.dts
index 09e7e1bf8d9d35..b42ea4dbc272e9 100644
--- a/target/linux/ath79/dts/qca9558_ubnt_nanobeam-ac-xc.dts
+++ b/target/linux/ath79/dts/qca9558_ubnt_nanobeam-ac-xc.dts
@@ -6,6 +6,8 @@
  * based on device tree from qca9558_ubnt_powerbeam-5ac-500.dts
  */
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca955x_ubnt_xc.dtsi"
 
 / {
@@ -71,7 +73,8 @@
 			gpios = <&led_gpio 3 GPIO_ACTIVE_LOW>;
 		};
 		led_power: power {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&led_gpio 4 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
diff --git a/target/linux/ath79/dts/qca9558_watchguard_ap300.dts b/target/linux/ath79/dts/qca9558_watchguard_ap300.dts
index 5f5ef0f968719e..e3431330de0f1f 100644
--- a/target/linux/ath79/dts/qca9558_watchguard_ap300.dts
+++ b/target/linux/ath79/dts/qca9558_watchguard_ap300.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "watchguard,ap300", "qca,qca9558";
@@ -31,7 +32,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
@@ -115,6 +117,10 @@
 				reg = <0x0 0x6>;
 				#nvmem-cell-cells = <1>;
 			};
+
+			cal_art_5000: calibration@5000 {
+				reg = <0x5000 0x844>;
+			};
 		};
 	};
 };
@@ -134,4 +140,11 @@
 
 &pcie0 {
 	status = "okay";
+
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>, <&macaddr_art_0 2>;
+		nvmem-cell-names = "calibration", "mac-address";
+	};
 };
diff --git a/target/linux/ath79/dts/qca9558_zyxel_nbg6716.dts b/target/linux/ath79/dts/qca9558_zyxel_nbg6716.dts
index 20230e684e3a3c..76ae8a99a691b5 100644
--- a/target/linux/ath79/dts/qca9558_zyxel_nbg6716.dts
+++ b/target/linux/ath79/dts/qca9558_zyxel_nbg6716.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca955x_zyxel_nbg6x16.dtsi"
 
 / {
@@ -17,7 +19,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "white:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 		};
 
@@ -53,7 +56,8 @@
 		};
 
 		wps {
-			label = "white:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -107,6 +111,16 @@
 				label = "art";
 				reg = <0x050000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_5000: calibration@5000 {
+						reg = <0x5000 0x844>;
+					};
+				};
 			};
 
 			partition@60000 {
@@ -167,6 +181,8 @@
 	wifi@0,0 {
 		compatible = "qcom,ath10k";
 		reg = <0 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>;
+		nvmem-cell-names = "calibration";
 		qcom,ath10k-calibration-variant = "ZyXEL-NBG6716";
 	};
 };
diff --git a/target/linux/ath79/dts/qca955x_elecom_wab.dtsi b/target/linux/ath79/dts/qca955x_elecom_wab.dtsi
new file mode 100644
index 00000000000000..f94f5824685863
--- /dev/null
+++ b/target/linux/ath79/dts/qca955x_elecom_wab.dtsi
@@ -0,0 +1,261 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "qca955x.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+	aliases {
+		led-boot = &led_status;
+		led-failsafe = &led_status;
+		led-upgrade = &led_status;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led-0 {
+			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_WLAN;
+			function-enumerator = <24>;
+			linux,default-trigger = "phy1tpt";
+		};
+
+		led_status: led-1 {
+			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_RED>;
+			function = LED_FUNCTION_STATUS;
+		};
+
+		led-2 {
+			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_USB;
+			trigger-sources = <&usb_port1>;
+			linux,default-trigger = "usbport";
+		};
+	};
+
+	keys {
+		compatible = "gpio-keys";
+
+		button-wps {
+			label = "wps";
+			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WPS_BUTTON>;
+			debounce-interval = <60>;
+		};
+
+		button-reset {
+			label = "reset";
+			gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+			debounce-interval = <60>;
+		};
+
+		button-eject {
+			label = "eject";
+			gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_EJECTCD>;
+			debounce-interval = <60>;
+		};
+	};
+
+	beeper {
+		compatible = "gpio-beeper";
+		gpios = <&gpio 4 GPIO_ACTIVE_HIGH>;
+	};
+
+	reg_usb_vbus: regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "usb-vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio 11 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		regulator-always-on;
+	};
+
+	watchdog {
+		compatible = "linux,wdt-gpio";
+		gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
+		hw_algo = "toggle";
+		hw_margin_ms = <300>;
+		always-running;
+	};
+};
+
+&mdio0 {
+	status = "okay";
+
+	ethphy4: ethernet-phy@4 {
+		compatible = "ethernet-phy-id004d,d072",
+			     "ethernet-phy-ieee802.3-c22";
+		reg = <0x4>;
+		eee-broken-100tx;
+		eee-broken-1000t;
+	};
+};
+
+&eth0 {
+	status = "okay";
+
+	phy-handle = <&ethphy4>;
+	phy-mode = "rgmii-rxid";
+	pll-data = <0xae000000 0x80000101 0x80001313>;
+
+	gmac-config {
+		device = <&gmac>;
+
+		rxdv-delay = <3>;
+		rxd-delay = <3>;
+		txen-delay = <0>;
+		txd-delay = <0>;
+		rgmii-enabled = <1>;
+	};
+};
+
+&mdio1 {
+	status = "okay";
+
+	ethphy1: ethernet-phy@1 {
+		compatible = "ethernet-phy-id004d,d074",
+			     "ethernet-phy-ieee802.3-c22";
+		reg = <0x1>;
+		at803x-override-sgmii-link-check;
+	};
+};
+
+&eth1 {
+	status = "okay";
+
+	phy-handle = <&ethphy1>;
+	pll-data = <0x03000000 0x00000101 0x00001313>;
+
+	qca955x-sgmii-fixup;
+};
+
+&pcie0 {
+	status = "okay";
+
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>;
+		nvmem-cell-names = "calibration";
+	};
+};
+
+&spi {
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <25000000>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "u-boot";
+				reg = <0x0 0x40000>;
+				read-only;
+			};
+
+			partition@40000 {
+				label = "u-boot-env";
+				reg = <0x40000 0x10000>;
+				read-only;
+			};
+
+			partition@50000 {
+				label = "art";
+				reg = <0x50000 0x10000>;
+				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
+					cal_art_5000: calibration@5000 {
+						reg = <0x5000 0x844>;
+					};
+				};
+			};
+
+			partition@60000 {
+				label = "art2";
+				reg = <0x60000 0x10000>;
+				read-only;
+			};
+
+			partition@70000 {
+				compatible = "denx,uimage";
+				label = "firmware";
+				reg = <0x70000 0xe00000>;
+			};
+
+			partition@e70000 {
+				label = "manufacture";
+				reg = <0xe70000 0x100000>;
+				read-only;
+			};
+
+			partition@f70000 {
+				label = "backup";
+				reg = <0xf70000 0x10000>;
+				read-only;
+			};
+
+			partition@f80000 {
+				label = "storage";
+				reg = <0xf80000 0x80000>;
+				read-only;
+			};
+		};
+	};
+};
+
+&uart {
+	status = "okay";
+};
+
+&usb_phy0 {
+	status = "okay";
+};
+
+&usb0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	dr_mode = "host";
+	vbus-supply = <&reg_usb_vbus>;
+
+	usb_port1: port@1 {
+		reg = <1>;
+		#trigger-source-cells = <0>;
+	};
+};
+
+&wdt {
+	status = "disabled";
+};
+
+&wmac {
+	status = "okay";
+
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
+};
diff --git a/target/linux/ath79/dts/qca955x_engenius_ecb1xxx.dtsi b/target/linux/ath79/dts/qca955x_engenius_ecb1xxx.dtsi
index 66f2e388534bb8..2a00985ba75b3a 100644
--- a/target/linux/ath79/dts/qca955x_engenius_ecb1xxx.dtsi
+++ b/target/linux/ath79/dts/qca955x_engenius_ecb1xxx.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -28,7 +29,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
@@ -87,6 +89,16 @@
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_5000: calibration@5000 {
+						reg = <0x5000 0x844>;
+					};
+				};
 			};
 		};
 	};
@@ -122,7 +134,8 @@
 	wifi@0,0 {
 		compatible = "qcom,ath10k";
 		reg = <0x0 0 0 0 0>;
-		qca,no-eeprom;
+		nvmem-cells = <&cal_art_5000>;
+		nvmem-cell-names = "calibration";
 	};
 };
 
diff --git a/target/linux/ath79/dts/qca955x_ubnt_xc.dtsi b/target/linux/ath79/dts/qca955x_ubnt_xc.dtsi
index 519f831beabfe9..7c1870d714cd96 100644
--- a/target/linux/ath79/dts/qca955x_ubnt_xc.dtsi
+++ b/target/linux/ath79/dts/qca955x_ubnt_xc.dtsi
@@ -7,6 +7,13 @@
 
 &pcie0 {
 	status = "okay";
+
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>;
+		nvmem-cell-names = "calibration";
+	};
 };
 
 &spi {
@@ -59,6 +66,10 @@
 					macaddr_art_0: macaddr@0 {
 						reg = <0x0 0x6>;
 					};
+
+					cal_art_5000: calibration@5000 {
+						reg = <0x5000 0x844>;
+					};
 				};
 			};
 		};
diff --git a/target/linux/ath79/dts/qca9561_avm_fritz4020.dts b/target/linux/ath79/dts/qca9561_avm_fritz4020.dts
index 7c220baddd33d9..b3b8d01986dbe6 100644
--- a/target/linux/ath79/dts/qca9561_avm_fritz4020.dts
+++ b/target/linux/ath79/dts/qca9561_avm_fritz4020.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "avm,fritz4020", "qca,qca9560";
@@ -46,24 +47,28 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&led_gpio 2 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&led_gpio 3 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&led_gpio 0 GPIO_ACTIVE_LOW>;
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&led_gpio 4 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ath79/dts/qca9561_nec_wf1200cr.dts b/target/linux/ath79/dts/qca9561_nec_wf1200cr.dts
index 90aac30d7f4843..c4671bf57f2fb6 100644
--- a/target/linux/ath79/dts/qca9561_nec_wf1200cr.dts
+++ b/target/linux/ath79/dts/qca9561_nec_wf1200cr.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "NEC Aterm WF1200CR";
@@ -21,12 +22,14 @@
 		/* other LEDs are connected to ath10k (QCA9888) gpiochip */
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_red: power_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -105,6 +108,16 @@
 				label = "art";
 				reg = <0x7f0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					precal_art_5000: pre-calibration@5000 {
+						reg = <0x5000 0x2f20>;
+					};
+				};
 			};
 		};
 	};
@@ -156,6 +169,8 @@
 	wifi@0,0 {
 		compatible = "qcom,ath10k";
 		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&precal_art_5000>;
+		nvmem-cell-names = "pre-calibration";
 	};
 };
 
diff --git a/target/linux/ath79/dts/qca9561_tplink_archer-c25-v1.dts b/target/linux/ath79/dts/qca9561_tplink_archer-c25-v1.dts
index 6179e621bf74f2..97e9ebf0b64911 100644
--- a/target/linux/ath79/dts/qca9561_tplink_archer-c25-v1.dts
+++ b/target/linux/ath79/dts/qca9561_tplink_archer-c25-v1.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "tplink,archer-c25-v1", "qca,qca9561";
@@ -57,13 +58,15 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
 		};
 
@@ -80,12 +83,14 @@
 		};
 
 		wan_green {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&led_gpio 5 GPIO_ACTIVE_LOW>;
 		};
 
 		wan_amber {
-			label = "amber:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&led_gpio 4 GPIO_ACTIVE_LOW>;
 		};
 
@@ -170,6 +175,16 @@
 				label = "art";
 				reg = <0x7f0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_5000: calibration@5000 {
+						reg = <0x5000 0x844>;
+					};
+				};
 			};
 		};
 	};
@@ -177,6 +192,13 @@
 
 &pcie {
 	status = "okay";
+
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>, <&macaddr_info_8 (-1)>;
+		nvmem-cell-names = "calibration", "mac-address";
+	};
 };
 
 &eth0 {
diff --git a/target/linux/ath79/dts/qca9561_tplink_archer-c58-v1.dts b/target/linux/ath79/dts/qca9561_tplink_archer-c58-v1.dts
index a09e1fae6f4a2a..95af75178403bc 100644
--- a/target/linux/ath79/dts/qca9561_tplink_archer-c58-v1.dts
+++ b/target/linux/ath79/dts/qca9561_tplink_archer-c58-v1.dts
@@ -11,6 +11,15 @@
 	};
 };
 
+&pcie {
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&precal_art_5000>, <&macaddr_info_8 (-1)>;
+		nvmem-cell-names = "pre-calibration", "mac-address";
+	};
+};
+
 &spi {
 	status = "okay";
 
@@ -64,6 +73,16 @@
 				label = "art";
 				reg = <0x7f0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					precal_art_5000: pre-calibration@5000 {
+						reg = <0x5000 0x2f20>;
+					};
+				};
 			};
 		};
 	};
diff --git a/target/linux/ath79/dts/qca9561_tplink_archer-c59-v1.dts b/target/linux/ath79/dts/qca9561_tplink_archer-c59-v1.dts
index 720a2b01a9c81d..e8b282b9c207a6 100644
--- a/target/linux/ath79/dts/qca9561_tplink_archer-c59-v1.dts
+++ b/target/linux/ath79/dts/qca9561_tplink_archer-c59-v1.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca9561_tplink_archer-c5x.dtsi"
 
 / {
@@ -13,7 +15,8 @@
 
 &leds {
 	usb {
-		label = "green:usb";
+		function = LED_FUNCTION_USB;
+		color = <LED_COLOR_ID_GREEN>;
 		gpios = <&led_gpio 7 GPIO_ACTIVE_LOW>;
 		linux,default-trigger = "usbport";
 		trigger-sources = <&hub_port0>;
@@ -28,6 +31,15 @@
 	status = "okay";
 };
 
+&pcie {
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&precal_art_5000>, <&macaddr_info_8 (-1)>;
+		nvmem-cell-names = "pre-calibration", "mac-address";
+	};
+};
+
 &spi {
 	status = "okay";
 
@@ -81,6 +93,16 @@
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					precal_art_5000: pre-calibration@5000 {
+						reg = <0x5000 0x2f20>;
+					};
+				};
 			};
 		};
 	};
diff --git a/target/linux/ath79/dts/qca9561_tplink_archer-c59-v2.dts b/target/linux/ath79/dts/qca9561_tplink_archer-c59-v2.dts
index be6e6ade1c7e7d..8a93d2b3b14c98 100644
--- a/target/linux/ath79/dts/qca9561_tplink_archer-c59-v2.dts
+++ b/target/linux/ath79/dts/qca9561_tplink_archer-c59-v2.dts
@@ -28,6 +28,15 @@
 	status = "okay";
 };
 
+&pcie {
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&precal_art_5000>, <&macaddr_info_8 (-1)>;
+		nvmem-cell-names = "pre-calibration", "mac-address";
+	};
+};
+
 &spi {
 	status = "okay";
 
@@ -87,6 +96,16 @@
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					precal_art_5000: pre-calibration@5000 {
+						reg = <0x5000 0x2f20>;
+					};
+				};
 			};
 		};
 	};
diff --git a/target/linux/ath79/dts/qca9561_tplink_archer-c5x.dtsi b/target/linux/ath79/dts/qca9561_tplink_archer-c5x.dtsi
index bb942078dc41c9..80e5db55e4ac5d 100644
--- a/target/linux/ath79/dts/qca9561_tplink_archer-c5x.dtsi
+++ b/target/linux/ath79/dts/qca9561_tplink_archer-c5x.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "tplink,archer-c5x", "qca,qca9560";
@@ -39,7 +40,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&led_gpio 0 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
@@ -57,22 +59,26 @@
 		};
 
 		wan_green {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&led_gpio 4 GPIO_ACTIVE_LOW>;
 		};
 
 		wan_amber {
-			label = "amber:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&led_gpio 5 GPIO_ACTIVE_LOW>;
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&led_gpio 3 GPIO_ACTIVE_LOW>;
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ath79/dts/qca9561_tplink_archer-c60-v1.dts b/target/linux/ath79/dts/qca9561_tplink_archer-c60-v1.dts
index eff85d6a586154..eb21394d046fd9 100644
--- a/target/linux/ath79/dts/qca9561_tplink_archer-c60-v1.dts
+++ b/target/linux/ath79/dts/qca9561_tplink_archer-c60-v1.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca9561_tplink_archer-c6x.dtsi"
 
 / {
@@ -13,16 +15,27 @@
 
 &leds {
 	wan_amber {
-		label = "amber:wan";
+		function = LED_FUNCTION_WAN;
+		color = <LED_COLOR_ID_AMBER>;
 		gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
 	};
 
 	wps {
-		label = "green:wps";
+		function = LED_FUNCTION_WPS;
+		color = <LED_COLOR_ID_GREEN>;
 		gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
 	};
 };
 
+&pcie {
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&precal_art_5000>, <&macaddr_info_8 (-1)>;
+		nvmem-cell-names = "pre-calibration", "mac-address";
+	};
+};
+
 &spi {
 	status = "okay";
 
@@ -76,6 +89,16 @@
 				label = "art";
 				reg = <0x7f0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					precal_art_5000: pre-calibration@5000 {
+						reg = <0x5000 0x2f20>;
+					};
+				};
 			};
 		};
 	};
diff --git a/target/linux/ath79/dts/qca9561_tplink_archer-c60-v2.dts b/target/linux/ath79/dts/qca9561_tplink_archer-c60-v2.dts
index 18053d691c8e82..aa4a7da10cf42f 100644
--- a/target/linux/ath79/dts/qca9561_tplink_archer-c60-v2.dts
+++ b/target/linux/ath79/dts/qca9561_tplink_archer-c60-v2.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca9561_tplink_archer-c6x.dtsi"
 
 / {
@@ -13,16 +15,27 @@
 
 &leds {
 	wan_amber {
-		label = "amber:wan";
+		function = LED_FUNCTION_WAN;
+		color = <LED_COLOR_ID_AMBER>;
 		gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
 	};
 
 	wps {
-		label = "green:wps";
+		function = LED_FUNCTION_WPS;
+		color = <LED_COLOR_ID_GREEN>;
 		gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
 	};
 };
 
+&pcie {
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&precal_art_5000>, <&macaddr_info_8 (-1)>;
+		nvmem-cell-names = "pre-calibration", "mac-address";
+	};
+};
+
 &spi {
 	status = "okay";
 
@@ -82,6 +95,16 @@
 				label = "art";
 				reg = <0x7f0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					precal_art_5000: pre-calibration@5000 {
+						reg = <0x5000 0x2f20>;
+					};
+				};
 			};
 		};
 	};
diff --git a/target/linux/ath79/dts/qca9561_tplink_archer-c60-v3.dts b/target/linux/ath79/dts/qca9561_tplink_archer-c60-v3.dts
index 068f9577591874..ede6878d5c1607 100644
--- a/target/linux/ath79/dts/qca9561_tplink_archer-c60-v3.dts
+++ b/target/linux/ath79/dts/qca9561_tplink_archer-c60-v3.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca9561_tplink_archer-c6x.dtsi"
 
 / {
@@ -13,11 +15,21 @@
 
 &leds {
 	wan_amber {
-		label = "amber:wan";
+		function = LED_FUNCTION_WAN;
+		color = <LED_COLOR_ID_AMBER>;
 		gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
 	};
 };
 
+&pcie {
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&precal_art_5000>, <&macaddr_info_8 (-1)>;
+		nvmem-cell-names = "pre-calibration", "mac-address";
+	};
+};
+
 &spi {
 	status = "okay";
 
@@ -77,6 +89,16 @@
 				label = "art";
 				reg = <0x7f0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					precal_art_5000: pre-calibration@5000 {
+						reg = <0x5000 0x2f20>;
+					};
+				};
 			};
 		};
 	};
diff --git a/target/linux/ath79/dts/qca9561_tplink_archer-c6x.dtsi b/target/linux/ath79/dts/qca9561_tplink_archer-c6x.dtsi
index e5f9d0bcc591c1..b3fdc03de47e0e 100644
--- a/target/linux/ath79/dts/qca9561_tplink_archer-c6x.dtsi
+++ b/target/linux/ath79/dts/qca9561_tplink_archer-c6x.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -33,7 +34,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
@@ -51,12 +53,14 @@
 		};
 
 		wan_green {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 20 GPIO_ACTIVE_LOW>;
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ath79/dts/qca9561_tplink_eap225-wall-v2.dts b/target/linux/ath79/dts/qca9561_tplink_eap225-wall-v2.dts
index cf5f3a3a4e045d..0e5c1fdc43c668 100644
--- a/target/linux/ath79/dts/qca9561_tplink_eap225-wall-v2.dts
+++ b/target/linux/ath79/dts/qca9561_tplink_eap225-wall-v2.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "tplink,eap225-wall-v2", "qca,qca9561";
@@ -39,7 +40,8 @@
 		compatible = "gpio-leds";
 
 		led_status: status {
-			label = "white:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
diff --git a/target/linux/ath79/dts/qca9561_tplink_tl-wdr6500-v2.dts b/target/linux/ath79/dts/qca9561_tplink_tl-wdr6500-v2.dts
index 8767693c82e559..f12043540741fa 100644
--- a/target/linux/ath79/dts/qca9561_tplink_tl-wdr6500-v2.dts
+++ b/target/linux/ath79/dts/qca9561_tplink_tl-wdr6500-v2.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "tplink,tl-wdr6500-v2", "qca,qca9561";
@@ -51,7 +52,8 @@
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ath79/dts/qca9563_asus_pl-ac56.dts b/target/linux/ath79/dts/qca9563_asus_pl-ac56.dts
index a31f188142ffad..752ecb27980a2a 100644
--- a/target/linux/ath79/dts/qca9563_asus_pl-ac56.dts
+++ b/target/linux/ath79/dts/qca9563_asus_pl-ac56.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "ASUS PL-AC56";
@@ -36,12 +37,14 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
 		};
 
@@ -59,6 +62,13 @@
 
 &pcie {
 	status = "okay";
+
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>;
+		nvmem-cell-names = "calibration";
+	};
 };
 
 &spi {
@@ -99,6 +109,10 @@
 					macaddr_art_1002: macaddr@1002 {
 						reg = <0x1002 0x6>;
 					};
+
+					cal_art_5000: calibration@5000 {
+						reg = <0x5000 0x844>;
+					};
 				};
 			};
 
diff --git a/target/linux/ath79/dts/qca9563_asus_rp-ac66.dts b/target/linux/ath79/dts/qca9563_asus_rp-ac66.dts
index c4b9f347134815..763ba431ef39ae 100644
--- a/target/linux/ath79/dts/qca9563_asus_rp-ac66.dts
+++ b/target/linux/ath79/dts/qca9563_asus_rp-ac66.dts
@@ -22,12 +22,14 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 6 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_orange: wps {
-			label = "orange:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
 		};
 
@@ -81,6 +83,13 @@
 
 &pcie {
 	status = "okay";
+
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>;
+		nvmem-cell-names = "calibration";
+	};
 };
 
 &spi {
@@ -121,6 +130,10 @@
 					macaddr_art_1002: macaddr@1002 {
 						reg = <0x1002 0x6>;
 					};
+
+					cal_art_5000: calibration@5000 {
+						reg = <0x5000 0x844>;
+					};
 				};
 			};
 
diff --git a/target/linux/ath79/dts/qca9563_comfast_cf-e375ac.dts b/target/linux/ath79/dts/qca9563_comfast_cf-e375ac.dts
index 2f0a0992a9d45f..ebcaeb6ddc96d6 100644
--- a/target/linux/ath79/dts/qca9563_comfast_cf-e375ac.dts
+++ b/target/linux/ath79/dts/qca9563_comfast_cf-e375ac.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "COMFAST CF-E375AC";
@@ -21,12 +22,14 @@
 		compatible = "gpio-leds";
 
 		led_lan: lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
 		};
 
 		wan {
-			label = "red:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
 		};
 
@@ -59,6 +62,13 @@
 
 &pcie {
 	status = "okay";
+
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&precal_art_5000>, <&macaddr_art_0 2>;
+		nvmem-cell-names = "pre-calibration", "mac-address";
+	};
 };
 
 &spi {
@@ -95,6 +105,10 @@
 						reg = <0x0 0x6>;
 						#nvmem-cell-cells = <1>;
 					};
+
+					precal_art_5000: pre-calibration@5000 {
+						reg = <0x5000 0x2f20>;
+					};
 				};
 			};
 
diff --git a/target/linux/ath79/dts/qca9563_dlink_covr-p2500-a1.dts b/target/linux/ath79/dts/qca9563_dlink_covr-p2500-a1.dts
index 3047c6f4794544..3b0c2afb50d08a 100644
--- a/target/linux/ath79/dts/qca9563_dlink_covr-p2500-a1.dts
+++ b/target/linux/ath79/dts/qca9563_dlink_covr-p2500-a1.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/mtd/partitions/uimage.h>
 
 / {
@@ -39,12 +40,14 @@
 		pinctrl-0 = <&jtag_disable_pins>;
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
@@ -56,7 +59,8 @@
 		};
 
 		led_power_red: power_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ath79/dts/qca9563_dlink_dir-842-c.dtsi b/target/linux/ath79/dts/qca9563_dlink_dir-842-c.dtsi
index a42deaddafd37c..34961c94c4adbc 100644
--- a/target/linux/ath79/dts/qca9563_dlink_dir-842-c.dtsi
+++ b/target/linux/ath79/dts/qca9563_dlink_dir-842-c.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -33,17 +34,20 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/qca9563_dlink_dir-859-a1.dts b/target/linux/ath79/dts/qca9563_dlink_dir-859-a1.dts
index 93bd8e363e85e7..320181c2b398de 100644
--- a/target/linux/ath79/dts/qca9563_dlink_dir-859-a1.dts
+++ b/target/linux/ath79/dts/qca9563_dlink_dir-859-a1.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca9563_dlink_dir-8x9-a1.dtsi"
 
 / {
@@ -17,12 +19,14 @@
 		compatible = "gpio-leds";
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 		};
 
@@ -32,7 +36,8 @@
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/qca9563_dlink_dir-859-a3.dts b/target/linux/ath79/dts/qca9563_dlink_dir-859-a3.dts
index 164e0802f9fb6f..f067df0fb72441 100644
--- a/target/linux/ath79/dts/qca9563_dlink_dir-859-a3.dts
+++ b/target/linux/ath79/dts/qca9563_dlink_dir-859-a3.dts
@@ -20,7 +20,6 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_POWER;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
diff --git a/target/linux/ath79/dts/qca9563_dlink_dir-869-a1.dts b/target/linux/ath79/dts/qca9563_dlink_dir-869-a1.dts
index 5afe683613b42c..60777ea9002cb6 100644
--- a/target/linux/ath79/dts/qca9563_dlink_dir-869-a1.dts
+++ b/target/linux/ath79/dts/qca9563_dlink_dir-869-a1.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca9563_dlink_dir-8x9-a1.dtsi"
 
 / {
@@ -17,12 +19,14 @@
 		compatible = "gpio-leds";
 
 		led_power_orange: power_orange {
-			label = "orange:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_white: power_white {
-			label = "white:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ath79/dts/qca9563_elecom_wrc-1750ghbk2-i.dts b/target/linux/ath79/dts/qca9563_elecom_wrc-1750ghbk2-i.dts
index a69b9d54e8b843..e7cdcad9c3a338 100644
--- a/target/linux/ath79/dts/qca9563_elecom_wrc-1750ghbk2-i.dts
+++ b/target/linux/ath79/dts/qca9563_elecom_wrc-1750ghbk2-i.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca9563_elecom_wrc-ghbk2-i.dtsi"
 
 / {
@@ -9,7 +11,8 @@
 
 &leds {
 	led_power: power {
-		label = "blue:power";
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_BLUE>;
 		gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
 		default-state = "on";
 	};
diff --git a/target/linux/ath79/dts/qca9563_elecom_wrc-300ghbk2-i.dts b/target/linux/ath79/dts/qca9563_elecom_wrc-300ghbk2-i.dts
index 51800820542359..8b64d8d2ff37ff 100644
--- a/target/linux/ath79/dts/qca9563_elecom_wrc-300ghbk2-i.dts
+++ b/target/linux/ath79/dts/qca9563_elecom_wrc-300ghbk2-i.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca9563_elecom_wrc-ghbk2-i.dtsi"
 
 / {
@@ -9,7 +11,8 @@
 
 &leds {
 	led_power: power {
-		label = "white:power";
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_WHITE>;
 		gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
 		default-state = "on";
 	};
diff --git a/target/linux/ath79/dts/qca9563_elecom_wrc-ghbk2-i.dtsi b/target/linux/ath79/dts/qca9563_elecom_wrc-ghbk2-i.dtsi
index a6706da1a50007..f63edb09cf9ba1 100644
--- a/target/linux/ath79/dts/qca9563_elecom_wrc-ghbk2-i.dtsi
+++ b/target/linux/ath79/dts/qca9563_elecom_wrc-ghbk2-i.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -17,7 +18,8 @@
 		compatible = "gpio-leds";
 
 		wps {
-			label = "red:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 9 GPIO_ACTIVE_HIGH>;
 		};
 	};
diff --git a/target/linux/ath79/dts/qca9563_glinet_gl-ar750s.dtsi b/target/linux/ath79/dts/qca9563_glinet_gl-ar750s.dtsi
index 09d2f48c2aa7ed..0624d88d8a132c 100644
--- a/target/linux/ath79/dts/qca9563_glinet_gl-ar750s.dtsi
+++ b/target/linux/ath79/dts/qca9563_glinet_gl-ar750s.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "glinet,gl-ar750s", "qca,qca9563";
@@ -41,7 +42,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
 			default-state = "keep";
 		};
@@ -102,7 +104,13 @@
 					#size-cells = <1>;
 
 					macaddr_art_0: macaddr@0 {
+						compatible = "mac-base";
 						reg = <0x0 0x6>;
+						#nvmem-cell-cells = <1>;
+					};
+
+					cal_art_5000: calibration@5000 {
+						reg = <0x5000 0x844>;
 					};
 				};
 			};
@@ -133,7 +141,7 @@
 	status = "okay";
 
 	phy-handle = <&phy0>;
-	nvmem-cells = <&macaddr_art_0>;
+	nvmem-cells = <&macaddr_art_0 0>;
 	nvmem-cell-names = "mac-address";
 };
 
@@ -161,6 +169,13 @@
 
 &pcie {
 	status = "okay";
+
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>, <&macaddr_art_0 1>;
+		nvmem-cell-names = "calibration", "mac-address";
+	};
 };
 
 &usb0 {
diff --git a/target/linux/ath79/dts/qca9563_nec_wg1200cr.dts b/target/linux/ath79/dts/qca9563_nec_wg1200cr.dts
index 26c1932154f24b..7f8866bd36a66e 100644
--- a/target/linux/ath79/dts/qca9563_nec_wg1200cr.dts
+++ b/target/linux/ath79/dts/qca9563_nec_wg1200cr.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "NEC Aterm WG1200CR";
@@ -21,13 +22,15 @@
 		/* other LEDs are connected to ath10k (QCA9888) gpiochip */
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		led_power_red: power_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -120,6 +123,16 @@
 				label = "art";
 				reg = <0x7f0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					precal_art_5000: pre-calibration@5000 {
+						reg = <0x5000 0x2f20>;
+					};
+				};
 			};
 		};
 	};
@@ -157,6 +170,8 @@
 	wifi@0,0 {
 		compatible = "pci168c,0056";
 		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&precal_art_5000>;
+		nvmem-cell-names = "pre-calibration";
 	};
 };
 
diff --git a/target/linux/ath79/dts/qca9563_nec_wg800hp.dts b/target/linux/ath79/dts/qca9563_nec_wg800hp.dts
index 1069a63a5e052b..fdcca64a0c88ed 100644
--- a/target/linux/ath79/dts/qca9563_nec_wg800hp.dts
+++ b/target/linux/ath79/dts/qca9563_nec_wg800hp.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "NEC Aterm WG800HP";
@@ -37,12 +38,14 @@
 		};
 
 		led_power_red: power_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
@@ -133,12 +136,34 @@
 				label = "board_data";
 				reg = <0x7e0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					macaddr_board_data_880: macaddr@880 {
+						compatible = "mac-base";
+						reg = <0x880 0x11>;
+						#nvmem-cell-cells = <1>;
+					};
+				};
 			};
 
 			art: partition@7f0000 {
 				label = "art";
 				reg = <0x7f0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_5000: calibration@5000 {
+						reg = <0x5000 0x844>;
+					};
+				};
 			};
 		};
 	};
@@ -170,6 +195,13 @@
 
 &pcie {
 	status = "okay";
+
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>, <&macaddr_board_data_880 0>;
+		nvmem-cell-names = "calibration", "mac-address";
+	};
 };
 
 &wmac {
diff --git a/target/linux/ath79/dts/qca9563_netgear_wndr.dtsi b/target/linux/ath79/dts/qca9563_netgear_wndr.dtsi
index c4faec8ef140db..757fdfe650ae21 100644
--- a/target/linux/ath79/dts/qca9563_netgear_wndr.dtsi
+++ b/target/linux/ath79/dts/qca9563_netgear_wndr.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -49,23 +50,27 @@
 		pinctrl-0 = <&jtag_disable_pins>;
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_amber: power_amber {
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
 			default-state = "keep";
 		};
 
 		wan_green {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
 		};
 
 		wan_amber {
-			label = "amber:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
 		};
 
@@ -76,7 +81,8 @@
 		};
 
 		wps_green {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ath79/dts/qca9563_netgear_wndr4300-v2.dts b/target/linux/ath79/dts/qca9563_netgear_wndr4300-v2.dts
index 8682413b0b0076..60b65a4fcbfc5b 100644
--- a/target/linux/ath79/dts/qca9563_netgear_wndr4300-v2.dts
+++ b/target/linux/ath79/dts/qca9563_netgear_wndr4300-v2.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca9563_netgear_wndr.dtsi"
 
 / {
@@ -9,7 +11,8 @@
 
 &leds {
 	usb_green {
-		label = "green:usb";
+		function = LED_FUNCTION_USB;
+		color = <LED_COLOR_ID_GREEN>;
 		gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
 		trigger-sources = <&hub_port0>;
 		linux,default-trigger = "usbport";
diff --git a/target/linux/ath79/dts/qca9563_phicomm_k2t.dts b/target/linux/ath79/dts/qca9563_phicomm_k2t.dts
index 9dbb291295fa8b..614d88d3830f48 100644
--- a/target/linux/ath79/dts/qca9563_phicomm_k2t.dts
+++ b/target/linux/ath79/dts/qca9563_phicomm_k2t.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Phicomm K2T";
@@ -20,17 +21,20 @@
 		compatible = "gpio-leds";
 
 		status_blue {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status_red: status_red {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
 		};
 
 		status_yellow {
-			label = "yellow:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_YELLOW>;
 			gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -48,6 +52,13 @@
 
 &pcie {
 	status = "okay";
+
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&precal_art_5000>;
+		nvmem-cell-names = "pre-calibration";
+	};
 };
 
 &spi {
@@ -91,6 +102,16 @@
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					precal_art_5000: pre-calibration@5000 {
+						reg = <0x5000 0x2f20>;
+					};
+				};
 			};
 		};
 	};
diff --git a/target/linux/ath79/dts/qca9563_qxwlan_e1700ac.dtsi b/target/linux/ath79/dts/qca9563_qxwlan_e1700ac.dtsi
index a4f7be3e1cd6ff..a0e64899187965 100644
--- a/target/linux/ath79/dts/qca9563_qxwlan_e1700ac.dtsi
+++ b/target/linux/ath79/dts/qca9563_qxwlan_e1700ac.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -35,7 +36,8 @@
 		};
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&hub_port0>;
 			linux,default-trigger = "usbport";
@@ -51,6 +53,13 @@
 
 &pcie {
 	status = "okay";
+
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>;
+		nvmem-cell-names = "calibration";
+	};
 };
 
 &spi {
@@ -98,6 +107,16 @@
 				label = "art";
 				reg = <0x060000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_5000: calibration@5000 {
+						reg = <0x5000 0x844>;
+					};
+				};
 			};
 		};
 	};
diff --git a/target/linux/ath79/dts/qca9563_tplink_archer-a7-v5.dts b/target/linux/ath79/dts/qca9563_tplink_archer-a7-v5.dts
index 339891f6da07ea..50996e06c7c310 100644
--- a/target/linux/ath79/dts/qca9563_tplink_archer-a7-v5.dts
+++ b/target/linux/ath79/dts/qca9563_tplink_archer-a7-v5.dts
@@ -50,7 +50,9 @@
 			#size-cells = <1>;
 
 			macaddr_info_8: macaddr@8 {
+				compatible = "mac-base";
 				reg = <0x8 0x6>;
+				#nvmem-cell-cells = <1>;
 			};
 		};
 	};
@@ -71,17 +73,36 @@
 		label = "art";
 		reg = <0xff0000 0x010000>;
 		read-only;
+
+		nvmem-layout {
+			compatible = "fixed-layout";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			cal_art_5000: calibration@5000 {
+				reg = <0x5000 0x844>;
+			};
+		};
 	};
 };
 
 &eth0 {
-	nvmem-cells = <&macaddr_info_8>;
+	nvmem-cells = <&macaddr_info_8 0>;
 	nvmem-cell-names = "mac-address";
 };
 
+&pcie {
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>, <&macaddr_info_8 (-1)>;
+		nvmem-cell-names = "calibration", "mac-address";
+	};
+};
+
 &wmac {
 	mtd-cal-data = <&art 0x1000>;
 
-	nvmem-cells = <&macaddr_info_8>;
+	nvmem-cells = <&macaddr_info_8 0>;
 	nvmem-cell-names = "mac-address";
 };
diff --git a/target/linux/ath79/dts/qca9563_tplink_archer-c2-v3.dts b/target/linux/ath79/dts/qca9563_tplink_archer-c2-v3.dts
index 9925666f826911..907eda94007e23 100644
--- a/target/linux/ath79/dts/qca9563_tplink_archer-c2-v3.dts
+++ b/target/linux/ath79/dts/qca9563_tplink_archer-c2-v3.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "tplink,archer-c2-v3", "qca,qca9563";
@@ -38,17 +39,20 @@
 		};
 
 		wifi_wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
 		};
 
 		wan_fail {
-			label = "orange:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 		};
 
@@ -134,7 +138,9 @@
 					#size-cells = <1>;
 
 					macaddr_info_8: macaddr@8 {
+						compatible = "mac-base";
 						reg = <0x8 0x6>;
+						#nvmem-cell-cells = <1>;
 					};
 				};
 			};
@@ -143,6 +149,16 @@
 				label = "art";
 				reg = <0x7f0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_5000: calibration@5000 {
+						reg = <0x5000 0x844>;
+					};
+				};
 			};
 		};
 	};
@@ -165,12 +181,19 @@
 
 &pcie {
 	status = "okay";
+
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>, <&macaddr_info_8 (-1)>;
+		nvmem-cell-names = "calibration", "mac-address";
+	};
 };
 
 &eth0 {
 	status = "okay";
 
-	nvmem-cells = <&macaddr_info_8>;
+	nvmem-cells = <&macaddr_info_8 0>;
 	nvmem-cell-names = "mac-address";
 	phy-mode = "sgmii";
 	phy-handle = <&phy0>;
@@ -180,6 +203,6 @@
 	status = "okay";
 
 	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_info_8>;
+	nvmem-cells = <&macaddr_info_8 0>;
 	nvmem-cell-names = "mac-address";
 };
diff --git a/target/linux/ath79/dts/qca9563_tplink_archer-c6-v2-us.dts b/target/linux/ath79/dts/qca9563_tplink_archer-c6-v2-us.dts
index 6857054f1cbbbd..f78a52a1208ffa 100644
--- a/target/linux/ath79/dts/qca9563_tplink_archer-c6-v2-us.dts
+++ b/target/linux/ath79/dts/qca9563_tplink_archer-c6-v2-us.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca9563_tplink_archer-x6-v2.dtsi"
 
 / {
@@ -19,7 +21,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
@@ -37,22 +40,26 @@
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
 		};
 
 		wan_fail {
-			label = "amber:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -76,6 +83,15 @@
 	};
 };
 
+&pcie {
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&precal_art_5000>, <&macaddr_info_8 (-1)>;
+		nvmem-cell-names = "pre-calibration", "mac-address";
+	};
+};
+
 &spi {
 	status = "okay";
 
@@ -106,7 +122,9 @@
 					#size-cells = <1>;
 
 					macaddr_info_8: macaddr@8 {
+						compatible = "mac-base";
 						reg = <0x8 0x6>;
+						#nvmem-cell-cells = <1>;
 					};
 				};
 			};
@@ -133,19 +151,29 @@
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					precal_art_5000: pre-calibration@5000 {
+						reg = <0x5000 0x2f20>;
+					};
+				};
 			};
 		};
 	};
 };
 
 &eth0 {
-	nvmem-cells = <&macaddr_info_8>;
+	nvmem-cells = <&macaddr_info_8 0>;
 	nvmem-cell-names = "mac-address";
 };
 
 &wmac {
 	mtd-cal-data = <&art 0x1000>;
 
-	nvmem-cells = <&macaddr_info_8>;
+	nvmem-cells = <&macaddr_info_8 0>;
 	nvmem-cell-names = "mac-address";
 };
diff --git a/target/linux/ath79/dts/qca9563_tplink_archer-c6-v2.dts b/target/linux/ath79/dts/qca9563_tplink_archer-c6-v2.dts
index e7d19c9fbd301f..fc7814a97ec5b3 100644
--- a/target/linux/ath79/dts/qca9563_tplink_archer-c6-v2.dts
+++ b/target/linux/ath79/dts/qca9563_tplink_archer-c6-v2.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca9563_tplink_archer-x6-v2.dtsi"
 
 / {
@@ -19,7 +21,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
@@ -37,22 +40,26 @@
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 20 GPIO_ACTIVE_LOW>;
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
 		};
 
 		wan_fail {
-			label = "amber:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -76,6 +83,15 @@
 	};
 };
 
+&pcie {
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&precal_art_5000>, <&macaddr_info_8 (-1)>;
+		nvmem-cell-names = "pre-calibration", "mac-address";
+	};
+};
+
 &spi {
 	status = "okay";
 
@@ -106,7 +122,9 @@
 					#size-cells = <1>;
 
 					macaddr_info_8: macaddr@8 {
+						compatible = "mac-base";
 						reg = <0x8 0x6>;
+						#nvmem-cell-cells = <1>;
 					};
 				};
 			};
@@ -127,19 +145,29 @@
 				label = "art";
 				reg = <0x7f0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					precal_art_5000: pre-calibration@5000 {
+						reg = <0x5000 0x2f20>;
+					};
+				};
 			};
 		};
 	};
 };
 
 &eth0 {
-	nvmem-cells = <&macaddr_info_8>;
+	nvmem-cells = <&macaddr_info_8 0>;
 	nvmem-cell-names = "mac-address";
 };
 
 &wmac {
 	mtd-cal-data = <&art 0x1000>;
 
-	nvmem-cells = <&macaddr_info_8>;
+	nvmem-cells = <&macaddr_info_8 0>;
 	nvmem-cell-names = "mac-address";
 };
diff --git a/target/linux/ath79/dts/qca9563_tplink_archer-c7-v4.dts b/target/linux/ath79/dts/qca9563_tplink_archer-c7-v4.dts
index ae6061c4cef4f7..611cb8953ed589 100644
--- a/target/linux/ath79/dts/qca9563_tplink_archer-c7-v4.dts
+++ b/target/linux/ath79/dts/qca9563_tplink_archer-c7-v4.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "tplink,archer-c7-v4", "qca,qca9563";
@@ -89,12 +90,14 @@
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&led_gpio 5 GPIO_ACTIVE_LOW>;
 		};
 
 		wan_fail {
-			label = "orange:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;
 		};
 
@@ -119,7 +122,8 @@
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&led_gpio 0 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -145,6 +149,13 @@
 
 &pcie {
 	status = "okay";
+
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>, <&macaddr_info_8 (-1)>;
+		nvmem-cell-names = "calibration", "mac-address";
+	};
 };
 
 &usb_phy0 {
@@ -205,7 +216,9 @@
 					#size-cells = <1>;
 
 					macaddr_info_8: macaddr@8 {
+						compatible = "mac-base";
 						reg = <0x8 0x6>;
+						#nvmem-cell-cells = <1>;
 					};
 				};
 			};
@@ -214,6 +227,16 @@
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_5000: calibration@5000 {
+						reg = <0x5000 0x844>;
+					};
+				};
 			};
 		};
 	};
@@ -241,7 +264,7 @@
 	pll-data = <0x03000101 0x00000101 0x00001919>;
 
 	phy-mode = "sgmii";
-	nvmem-cells = <&macaddr_info_8>;
+	nvmem-cells = <&macaddr_info_8 0>;
 	nvmem-cell-names = "mac-address";
 	phy-handle = <&phy0>;
 };
@@ -250,6 +273,6 @@
 	status = "okay";
 
 	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_info_8>;
+	nvmem-cells = <&macaddr_info_8 0>;
 	nvmem-cell-names = "mac-address";
 };
diff --git a/target/linux/ath79/dts/qca9563_tplink_archer-c7-v5.dts b/target/linux/ath79/dts/qca9563_tplink_archer-c7-v5.dts
index 32b75cad7b4a97..d37fc14b11332c 100644
--- a/target/linux/ath79/dts/qca9563_tplink_archer-c7-v5.dts
+++ b/target/linux/ath79/dts/qca9563_tplink_archer-c7-v5.dts
@@ -43,6 +43,16 @@
 		label = "art";
 		reg = <0x050000 0x010000>;
 		read-only;
+
+		nvmem-layout {
+			compatible = "fixed-layout";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			cal_art_5000: calibration@5000 {
+				reg = <0x5000 0x844>;
+			};
+		};
 	};
 
 	info: partition@60000 {
@@ -56,7 +66,9 @@
 			#size-cells = <1>;
 
 			macaddr_info_8: macaddr@8 {
+				compatible = "mac-base";
 				reg = <0x8 0x6>;
+				#nvmem-cell-cells = <1>;
 			};
 		};
 	};
@@ -81,13 +93,24 @@
 };
 
 &eth0 {
-	nvmem-cells = <&macaddr_info_8>;
+	nvmem-cells = <&macaddr_info_8 0>;
 	nvmem-cell-names = "mac-address";
 };
 
+&pcie {
+	status = "okay";
+
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>, <&macaddr_info_8 (-1)>;
+		nvmem-cell-names = "calibration", "mac-address";
+	};
+};
+
 &wmac {
 	mtd-cal-data = <&art 0x1000>;
 
-	nvmem-cells = <&macaddr_info_8>;
+	nvmem-cells = <&macaddr_info_8 0>;
 	nvmem-cell-names = "mac-address";
 };
diff --git a/target/linux/ath79/dts/qca9563_tplink_archer-x7-v5.dtsi b/target/linux/ath79/dts/qca9563_tplink_archer-x7-v5.dtsi
index f6a959903fb916..c1000f52a3bdf2 100644
--- a/target/linux/ath79/dts/qca9563_tplink_archer-x7-v5.dtsi
+++ b/target/linux/ath79/dts/qca9563_tplink_archer-x7-v5.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -23,7 +24,8 @@
 		};
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&hub_port0>;
 			linux,default-trigger = "usbport";
@@ -42,12 +44,14 @@
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
 		};
 
 		wan_fail {
-			label = "orange:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 20 GPIO_ACTIVE_LOW>;
 		};
 
@@ -72,7 +76,8 @@
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ath79/dts/qca9563_tplink_cpe710-v1.dts b/target/linux/ath79/dts/qca9563_tplink_cpe710-v1.dts
index 491ffac1326a00..3a0c16d4a34b30 100644
--- a/target/linux/ath79/dts/qca9563_tplink_cpe710-v1.dts
+++ b/target/linux/ath79/dts/qca9563_tplink_cpe710-v1.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "TP-Link CPE710 v1";
@@ -20,7 +21,8 @@
 		compatible = "gpio-leds";
 
 		led_lan: lan {
-			label = "blue:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
 		};
 
@@ -45,6 +47,13 @@
 
 &pcie {
 	status = "okay";
+
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&precal_art_5000>, <&macaddr_info_8>;
+		nvmem-cell-names = "pre-calibration", "mac-address";
+	};
 };
 
 &spi {
@@ -109,6 +118,16 @@
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					precal_art_5000: pre-calibration@5000 {
+						reg = <0x5000 0x2f20>;
+					};
+				};
 			};
 		};
 	};
diff --git a/target/linux/ath79/dts/qca9563_tplink_deco-m4r-v1.dts b/target/linux/ath79/dts/qca9563_tplink_deco-m4r-v1.dts
index 63f42eba7600b8..7968bdbf6da820 100644
--- a/target/linux/ath79/dts/qca9563_tplink_deco-m4r-v1.dts
+++ b/target/linux/ath79/dts/qca9563_tplink_deco-m4r-v1.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 #include "qca956x.dtsi"
 
@@ -26,7 +27,8 @@
 		};
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
@@ -53,6 +55,13 @@
 
 &pcie {
 	status = "okay";
+
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&precal_art_5000>, <&macaddr_config_8 (-1)>;
+		nvmem-cell-names = "pre-calibration", "mac-address";
+	};
 };
 
 &mdio0 {
@@ -113,7 +122,9 @@
 					#size-cells = <1>;
 
 					macaddr_config_8: macaddr@8 {
+						compatible = "mac-base";
 						reg = <0x8 0x6>;
+						#nvmem-cell-cells = <1>;
 					};
 				};
 			};
@@ -122,6 +133,16 @@
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					precal_art_5000: pre-calibration@5000 {
+						reg = <0x5000 0x2f20>;
+					};
+				};
 			};
 		};
 	};
@@ -133,7 +154,7 @@
 	phy-mode = "sgmii";
 	phy-handle = <&phy0>;
 
-	nvmem-cells = <&macaddr_config_8>;
+	nvmem-cells = <&macaddr_config_8 0>;
 	nvmem-cell-names = "mac-address";
 };
 
@@ -141,6 +162,6 @@
 	status = "okay";
 
 	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_config_8>;
+	nvmem-cells = <&macaddr_config_8 0>;
 	nvmem-cell-names = "mac-address";
 };
diff --git a/target/linux/ath79/dts/qca9563_tplink_deco-s4-v2.dts b/target/linux/ath79/dts/qca9563_tplink_deco-s4-v2.dts
index e4bb88807ebf24..29d0d8868dfcf5 100644
--- a/target/linux/ath79/dts/qca9563_tplink_deco-s4-v2.dts
+++ b/target/linux/ath79/dts/qca9563_tplink_deco-s4-v2.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 #include "qca956x.dtsi"
 
@@ -26,7 +27,8 @@
 		};
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
@@ -53,6 +55,13 @@
 
 &pcie {
 	status = "okay";
+
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&precal_art_5000>;
+		nvmem-cell-names = "pre-calibration";
+	};
 };
 
 &mdio0 {
@@ -106,6 +115,16 @@
 				label = "art";
 				reg = <0x1f0000 0x10000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					precal_art_5000: pre-calibration@5000 {
+						reg = <0x5000 0x2f20>;
+					};
+				};
 			};
 
 			partition@200000 {
diff --git a/target/linux/ath79/dts/qca9563_tplink_eap225-outdoor-v1.dts b/target/linux/ath79/dts/qca9563_tplink_eap225-outdoor-v1.dts
index c3f1a130eb02f5..4d5d75a8e0f5a2 100644
--- a/target/linux/ath79/dts/qca9563_tplink_eap225-outdoor-v1.dts
+++ b/target/linux/ath79/dts/qca9563_tplink_eap225-outdoor-v1.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca9563_tplink_eap2x5-1port.dtsi"
 
 / {
@@ -17,13 +19,15 @@
 		compatible = "gpio-leds";
 
 		led_status_green: status_green {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		led_status_amber: status_amber {
-			label = "amber:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ath79/dts/qca9563_tplink_eap225-outdoor-v3.dts b/target/linux/ath79/dts/qca9563_tplink_eap225-outdoor-v3.dts
index 1fac6082cf241b..916d30d3c62f65 100644
--- a/target/linux/ath79/dts/qca9563_tplink_eap225-outdoor-v3.dts
+++ b/target/linux/ath79/dts/qca9563_tplink_eap225-outdoor-v3.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca9563_tplink_eap2x5-1port.dtsi"
 
 / {
@@ -17,13 +19,15 @@
 		compatible = "gpio-leds";
 
 		led_status_green: status_green {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		led_status_amber: status_amber {
-			label = "amber:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ath79/dts/qca9563_tplink_eap225-v1.dts b/target/linux/ath79/dts/qca9563_tplink_eap225-v1.dts
index 9d06a49626e2e1..a660c1593c4453 100644
--- a/target/linux/ath79/dts/qca9563_tplink_eap225-v1.dts
+++ b/target/linux/ath79/dts/qca9563_tplink_eap225-v1.dts
@@ -18,7 +18,6 @@
 		compatible = "gpio-leds";
 
 		led_status_green: led-0 {
-			label = "green:status";
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_STATUS;
 			gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
@@ -26,14 +25,12 @@
 		};
 
 		led_status_amber: led-1 {
-			label = "amber:status";
 			color = <LED_COLOR_ID_AMBER>;
 			function = LED_FUNCTION_STATUS;
 			gpios = <&gpio 9 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_status_red: led-2 {
-			label = "red:status";
 			color = <LED_COLOR_ID_RED>;
 			function = LED_FUNCTION_STATUS;
 			gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
diff --git a/target/linux/ath79/dts/qca9563_tplink_eap225-v3.dts b/target/linux/ath79/dts/qca9563_tplink_eap225-v3.dts
index 5139bc76702947..75b28f93a5008e 100644
--- a/target/linux/ath79/dts/qca9563_tplink_eap225-v3.dts
+++ b/target/linux/ath79/dts/qca9563_tplink_eap225-v3.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca9563_tplink_eap2x5-1port.dtsi"
 
 / {
@@ -17,13 +19,15 @@
 		compatible = "gpio-leds";
 
 		led_status_green: status_green {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
 			default-state = "on";
 		};
 
 		led_status_amber: status_amber {
-			label = "amber:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 9 GPIO_ACTIVE_HIGH>;
 		};
 	};
diff --git a/target/linux/ath79/dts/qca9563_tplink_eap225-v4.dts b/target/linux/ath79/dts/qca9563_tplink_eap225-v4.dts
index 6e7ba5fede45e1..82da14faad668b 100644
--- a/target/linux/ath79/dts/qca9563_tplink_eap225-v4.dts
+++ b/target/linux/ath79/dts/qca9563_tplink_eap225-v4.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca9563_tplink_eap2x5-1port.dtsi"
 
 / {
@@ -17,13 +19,15 @@
 		compatible = "gpio-leds";
 
 		led_status_green: status_green {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
 			default-state = "on";
 		};
 
 		led_status_amber: status_amber {
-			label = "amber:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 9 GPIO_ACTIVE_HIGH>;
 		};
 	};
diff --git a/target/linux/ath79/dts/qca9563_tplink_eap245-v1.dts b/target/linux/ath79/dts/qca9563_tplink_eap245-v1.dts
index af133813e71e6c..b44facf3f67a38 100644
--- a/target/linux/ath79/dts/qca9563_tplink_eap245-v1.dts
+++ b/target/linux/ath79/dts/qca9563_tplink_eap245-v1.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca9563_tplink_eap2x5-1port.dtsi"
 
 / {
@@ -17,18 +19,21 @@
 		compatible = "gpio-leds";
 
 		led_status_green: status_green {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
 			default-state = "on";
 		};
 
 		led_status_amber: status_amber {
-			label = "amber:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 9 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_status_red: status_red {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
 		};
 	};
diff --git a/target/linux/ath79/dts/qca9563_tplink_eap245-v3.dts b/target/linux/ath79/dts/qca9563_tplink_eap245-v3.dts
index 1e37db82bce497..38edffc529be96 100644
--- a/target/linux/ath79/dts/qca9563_tplink_eap245-v3.dts
+++ b/target/linux/ath79/dts/qca9563_tplink_eap245-v3.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "tplink,eap245-v3", "qca,qca9563";
@@ -21,13 +22,15 @@
 		compatible = "gpio-leds";
 
 		led_status_green: status_green {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
 			default-state = "on";
 		};
 
 		led_status_amber: status_amber {
-			label = "amber:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 9 GPIO_ACTIVE_HIGH>;
 		};
 	};
diff --git a/target/linux/ath79/dts/qca9563_tplink_re450-v2.dts b/target/linux/ath79/dts/qca9563_tplink_re450-v2.dts
index 5eb1eafaf41c4a..25a7b8229b56cf 100644
--- a/target/linux/ath79/dts/qca9563_tplink_re450-v2.dts
+++ b/target/linux/ath79/dts/qca9563_tplink_re450-v2.dts
@@ -41,7 +41,9 @@
 			#size-cells = <1>;
 
 			macaddr_info_8: macaddr@8 {
+				compatible = "mac-base";
 				reg = <0x8 0x6>;
+				#nvmem-cell-cells = <1>;
 			};
 		};
 	};
@@ -56,17 +58,36 @@
 		label = "art";
 		reg = <0x7f0000 0x010000>;
 		read-only;
+
+		nvmem-layout {
+			compatible = "fixed-layout";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			cal_art_5000: calibration@5000 {
+				reg = <0x5000 0x844>;
+			};
+		};
 	};
 };
 
 &eth0 {
-	nvmem-cells = <&macaddr_info_8>;
+	nvmem-cells = <&macaddr_info_8 0>;
 	nvmem-cell-names = "mac-address";
 };
 
+&pcie {
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>, <&macaddr_info_8 1>;
+		nvmem-cell-names = "calibration", "mac-address";
+	};
+};
+
 &wmac {
 	mtd-cal-data = <&art 0x1000>;
 
-	nvmem-cells = <&macaddr_info_8>;
+	nvmem-cells = <&macaddr_info_8 0>;
 	nvmem-cell-names = "mac-address";
 };
diff --git a/target/linux/ath79/dts/qca9563_tplink_re450-v3.dts b/target/linux/ath79/dts/qca9563_tplink_re450-v3.dts
index fdd982ae2e2447..2572901def8bcb 100644
--- a/target/linux/ath79/dts/qca9563_tplink_re450-v3.dts
+++ b/target/linux/ath79/dts/qca9563_tplink_re450-v3.dts
@@ -29,7 +29,9 @@
 			#size-cells = <1>;
 
 			macaddr_info_8: macaddr@8 {
+				compatible = "mac-base";
 				reg = <0x8 0x6>;
+				#nvmem-cell-cells = <1>;
 			};
 		};
 	};
@@ -62,17 +64,36 @@
 		label = "art";
 		reg = <0x7f0000 0x010000>;
 		read-only;
+
+		nvmem-layout {
+			compatible = "fixed-layout";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			cal_art_5000: calibration@5000 {
+				reg = <0x5000 0x844>;
+			};
+		};
 	};
 };
 
 &eth0 {
-	nvmem-cells = <&macaddr_info_8>;
+	nvmem-cells = <&macaddr_info_8 0>;
 	nvmem-cell-names = "mac-address";
 };
 
+&pcie {
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>, <&macaddr_info_8 1>;
+		nvmem-cell-names = "calibration", "mac-address";
+	};
+};
+
 &wmac {
 	mtd-cal-data = <&art 0x1000>;
 
-	nvmem-cells = <&macaddr_info_8>;
+	nvmem-cells = <&macaddr_info_8 0>;
 	nvmem-cell-names = "mac-address";
 };
diff --git a/target/linux/ath79/dts/qca9563_tplink_re450.dtsi b/target/linux/ath79/dts/qca9563_tplink_re450.dtsi
index 3841a4c8fd7c4a..2e9ef99cd0d9f7 100644
--- a/target/linux/ath79/dts/qca9563_tplink_re450.dtsi
+++ b/target/linux/ath79/dts/qca9563_tplink_re450.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -18,7 +19,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
 		};
 
@@ -45,12 +47,14 @@
 		};
 
 		wps_blue {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
 		};
 
 		wps_red {
-			label = "red:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 20 GPIO_ACTIVE_HIGH>;
 		};
 	};
diff --git a/target/linux/ath79/dts/qca9563_tplink_re455-v1.dts b/target/linux/ath79/dts/qca9563_tplink_re455-v1.dts
index a976f4fa5a2bf6..7caa356861008d 100644
--- a/target/linux/ath79/dts/qca9563_tplink_re455-v1.dts
+++ b/target/linux/ath79/dts/qca9563_tplink_re455-v1.dts
@@ -29,7 +29,9 @@
 			#size-cells = <1>;
 
 			macaddr_info_8: macaddr@8 {
+				compatible = "mac-base";
 				reg = <0x8 0x6>;
+				#nvmem-cell-cells = <1>;
 			};
 		};
 	};
@@ -62,17 +64,36 @@
 		label = "art";
 		reg = <0x7f0000 0x010000>;
 		read-only;
+
+		nvmem-layout {
+			compatible = "fixed-layout";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			cal_art_5000: calibration@5000 {
+				reg = <0x5000 0x844>;
+			};
+		};
 	};
 };
 
 &eth0 {
-	nvmem-cells = <&macaddr_info_8>;
+	nvmem-cells = <&macaddr_info_8 0>;
 	nvmem-cell-names = "mac-address";
 };
 
+&pcie {
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>, <&macaddr_info_8 1>;
+		nvmem-cell-names = "calibration", "mac-address";
+	};
+};
+
 &wmac {
 	mtd-cal-data = <&art 0x1000>;
 
-	nvmem-cells = <&macaddr_info_8>;
+	nvmem-cells = <&macaddr_info_8 0>;
 	nvmem-cell-names = "mac-address";
 };
diff --git a/target/linux/ath79/dts/qca9563_tplink_tl-wa1201-v2.dts b/target/linux/ath79/dts/qca9563_tplink_tl-wa1201-v2.dts
index cf13fcd6b7ff5c..b1d564be155692 100644
--- a/target/linux/ath79/dts/qca9563_tplink_tl-wa1201-v2.dts
+++ b/target/linux/ath79/dts/qca9563_tplink_tl-wa1201-v2.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "tplink,tl-wa1201-v2", "qca,qca9563";
@@ -22,7 +23,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
@@ -40,7 +42,8 @@
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 20 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -83,6 +86,13 @@
 
 &pcie {
 	status = "okay";
+
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&precal_art_5000>, <&macaddr_info_8 (-1)>;
+		nvmem-cell-names = "pre-calibration", "mac-address";
+	};
 };
 
 &eth0 {
@@ -91,7 +101,7 @@
 	phy-mode = "sgmii";
 	phy-handle = <&phy4>;
 
-	nvmem-cells = <&macaddr_info_8>;
+	nvmem-cells = <&macaddr_info_8 0>;
 	nvmem-cell-names = "mac-address";
 };
 
@@ -100,7 +110,7 @@
 
 	mtd-cal-data = <&art 0x1000>;
 
-	nvmem-cells = <&macaddr_info_8>;
+	nvmem-cells = <&macaddr_info_8 0>;
 	nvmem-cell-names = "mac-address";
 };
 
@@ -134,7 +144,9 @@
 					#size-cells = <1>;
 
 					macaddr_info_8: macaddr@8 {
+						compatible = "mac-base";
 						reg = <0x8 0x6>;
+						#nvmem-cell-cells = <1>;
 					};
 				};
 			};
@@ -155,6 +167,16 @@
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					precal_art_5000: pre-calibration@5000 {
+						reg = <0x5000 0x2f20>;
+					};
+				};
 			};
 		};
 	};
diff --git a/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630-v1.dts b/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630-v1.dts
index 8c6c91f1070228..a44caa0b6b0189 100644
--- a/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630-v1.dts
+++ b/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630-v1.dts
@@ -23,7 +23,9 @@
 			#size-cells = <1>;
 
 			macaddr_uboot_fc00: macaddr@fc00 {
+				compatible = "mac-base";
 				reg = <0xfc00 0x6>;
+				#nvmem-cell-cells = <1>;
 			};
 		};
 	};
@@ -44,17 +46,36 @@
 		label = "art";
 		reg = <0x7f0000 0x010000>;
 		read-only;
+
+		nvmem-layout {
+			compatible = "fixed-layout";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			cal_art_5000: calibration@5000 {
+				reg = <0x5000 0x844>;
+			};
+		};
 	};
 };
 
 &eth0 {
-	nvmem-cells = <&macaddr_uboot_fc00>;
+	nvmem-cells = <&macaddr_uboot_fc00 0>;
 	nvmem-cell-names = "mac-address";
 };
 
+&pcie {
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>, <&macaddr_uboot_fc00 1>;
+		nvmem-cell-names = "calibration", "mac-address";
+	};
+};
+
 &wmac {
 	mtd-cal-data = <&art 0x1000>;
 
-	nvmem-cells = <&macaddr_uboot_fc00>;
+	nvmem-cells = <&macaddr_uboot_fc00 0>;
 	nvmem-cell-names = "mac-address";
 };
diff --git a/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630.dtsi b/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630.dtsi
index 560aae9694b925..81fb6ce097fd1c 100644
--- a/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630.dtsi
+++ b/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -49,12 +50,14 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630p-v2-int.dts b/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630p-v2-int.dts
index 8786e309659e0e..1e62094c12b605 100644
--- a/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630p-v2-int.dts
+++ b/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630p-v2-int.dts
@@ -53,7 +53,9 @@
 			#size-cells = <1>;
 
 			macaddr_info_8: macaddr@8 {
+				compatible = "mac-base";
 				reg = <0x8 0x6>;
+				#nvmem-cell-cells = <1>;
 			};
 		};
 	};
@@ -62,17 +64,36 @@
 		label = "art";
 		reg = <0x7f0000 0x010000>;
 		read-only;
+
+		nvmem-layout {
+			compatible = "fixed-layout";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			precal_art_5000: pre-calibration@5000 {
+				reg = <0x5000 0x2f20>;
+			};
+		};
 	};
 };
 
 &eth0 {
-	nvmem-cells = <&macaddr_info_8>;
+	nvmem-cells = <&macaddr_info_8 0>;
 	nvmem-cell-names = "mac-address";
 };
 
+&pcie {
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&precal_art_5000>, <&macaddr_info_8 1>;
+		nvmem-cell-names = "pre-calibration", "mac-address";
+	};
+};
+
 &wmac {
 	mtd-cal-data = <&art 0x1000>;
 
-	nvmem-cells = <&macaddr_info_8>;
+	nvmem-cells = <&macaddr_info_8 0>;
 	nvmem-cell-names = "mac-address";
 };
diff --git a/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630p-v2.0-eu.dts b/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630p-v2.0-eu.dts
index 3c688d67d636a4..5f834542f2ff9b 100644
--- a/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630p-v2.0-eu.dts
+++ b/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630p-v2.0-eu.dts
@@ -47,7 +47,9 @@
 			#size-cells = <1>;
 
 			macaddr_info_8: macaddr@8 {
+				compatible = "mac-base";
 				reg = <0x8 0x6>;
+				#nvmem-cell-cells = <1>;
 			};
 		};
 	};
@@ -62,17 +64,36 @@
 		label = "art";
 		reg = <0x7f0000 0x010000>;
 		read-only;
+
+		nvmem-layout {
+			compatible = "fixed-layout";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			precal_art_5000: pre-calibration@5000 {
+				reg = <0x5000 0x2f20>;
+			};
+		};
 	};
 };
 
 &eth0 {
-	nvmem-cells = <&macaddr_info_8>;
+	nvmem-cells = <&macaddr_info_8 0>;
 	nvmem-cell-names = "mac-address";
 };
 
+&pcie {
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&precal_art_5000>, <&macaddr_info_8 1>;
+		nvmem-cell-names = "pre-calibration", "mac-address";
+	};
+};
+
 &wmac {
 	mtd-cal-data = <&art 0x1000>;
 
-	nvmem-cells = <&macaddr_info_8>;
+	nvmem-cells = <&macaddr_info_8 0>;
 	nvmem-cell-names = "mac-address";
 };
diff --git a/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630p-v2.1-eu.dts b/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630p-v2.1-eu.dts
index 786cd3cc039e00..7be23423df51ee 100644
--- a/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630p-v2.1-eu.dts
+++ b/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630p-v2.1-eu.dts
@@ -49,7 +49,9 @@
 			#size-cells = <1>;
 
 			macaddr_info_8: macaddr@8 {
+				compatible = "mac-base";
 				reg = <0x8 0x6>;
+				#nvmem-cell-cells = <1>;
 			};
 		};
 	};
@@ -58,17 +60,36 @@
 		label = "art";
 		reg = <0x7f0000 0x010000>;
 		read-only;
+
+		nvmem-layout {
+			compatible = "fixed-layout";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			precal_art_5000: pre-calibration@5000 {
+				reg = <0x5000 0x2f20>;
+			};
+		};
+	};
+};
+
+&pcie {
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&precal_art_5000>, <&macaddr_info_8 1>;
+		nvmem-cell-names = "pre-calibration", "mac-address";
 	};
 };
 
 &eth0 {
-	nvmem-cells = <&macaddr_info_8>;
+	nvmem-cells = <&macaddr_info_8 0>;
 	nvmem-cell-names = "mac-address";
 };
 
 &wmac {
 	mtd-cal-data = <&art 0x1000>;
 
-	nvmem-cells = <&macaddr_info_8>;
+	nvmem-cells = <&macaddr_info_8 0>;
 	nvmem-cell-names = "mac-address";
 };
diff --git a/target/linux/ath79/dts/qca9563_tplink_tl-wr1043n.dtsi b/target/linux/ath79/dts/qca9563_tplink_tl-wr1043n.dtsi
index 2e3ac952e290a2..e54003cb7a85d9 100644
--- a/target/linux/ath79/dts/qca9563_tplink_tl-wr1043n.dtsi
+++ b/target/linux/ath79/dts/qca9563_tplink_tl-wr1043n.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -23,23 +24,27 @@
 		};
 
 		wifi_green {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
 
 		wifi_wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 		};
 
 		wan_fail {
-			label = "orange:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ath79/dts/qca9563_tplink_tl-wr1043nd-v4.dts b/target/linux/ath79/dts/qca9563_tplink_tl-wr1043nd-v4.dts
index 4aa0ef572f632b..6db4653f69fe6c 100644
--- a/target/linux/ath79/dts/qca9563_tplink_tl-wr1043nd-v4.dts
+++ b/target/linux/ath79/dts/qca9563_tplink_tl-wr1043nd-v4.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qca9563_tplink_tl-wr1043n.dtsi"
 
 / {
@@ -92,7 +94,8 @@
 
 &leds {
 	usb {
-		label = "green:usb";
+		function = LED_FUNCTION_USB;
+		color = <LED_COLOR_ID_GREEN>;
 		gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
 		trigger-sources = <&hub_port0>;
 		linux,default-trigger = "usbport";
diff --git a/target/linux/ath79/dts/qca9563_ubnt_unifiac.dtsi b/target/linux/ath79/dts/qca9563_ubnt_unifiac.dtsi
index 60d6fbc895ac65..48d8d9c83e9963 100644
--- a/target/linux/ath79/dts/qca9563_ubnt_unifiac.dtsi
+++ b/target/linux/ath79/dts/qca9563_ubnt_unifiac.dtsi
@@ -41,6 +41,13 @@
 
 &pcie {
 	status = "okay";
+
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>;
+		nvmem-cell-names = "calibration";
+	};
 };
 
 &spi {
@@ -99,6 +106,10 @@
 					macaddr_art_0: macaddr@0 {
 						reg = <0x0 0x6>;
 					};
+
+					cal_art_5000: calibration@5000 {
+						reg = <0x5000 0x844>;
+					};
 				};
 			};
 		};
diff --git a/target/linux/ath79/dts/qca9563_xiaomi_aiot-ac2350.dts b/target/linux/ath79/dts/qca9563_xiaomi_aiot-ac2350.dts
index 2085644f766289..27e3436f8f215d 100644
--- a/target/linux/ath79/dts/qca9563_xiaomi_aiot-ac2350.dts
+++ b/target/linux/ath79/dts/qca9563_xiaomi_aiot-ac2350.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Xiaomi AIoT AC2350";
@@ -42,12 +43,14 @@
 		};
 
 		wan_blue {
-			label = "blue:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
 		};
 
 		wan_orange {
-			label = "orange:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -118,6 +121,10 @@
 					macaddr_art_0: macaddr@0 {
 						reg = <0x0 0x6>;
 					};
+
+					precal_art_5000: pre-calibration@5000 {
+						reg = <0x5000 0x2f20>;
+					};
 				};
 			};
 
@@ -183,4 +190,11 @@
 
 &pcie {
 	status = "okay";
+
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&precal_art_5000>;
+		nvmem-cell-names = "pre-calibration";
+	};
 };
diff --git a/target/linux/ath79/dts/qca9563_yuncore_xd3200.dts b/target/linux/ath79/dts/qca9563_yuncore_xd3200.dts
index 5c87752585f3c1..fa82a6914b6d5f 100644
--- a/target/linux/ath79/dts/qca9563_yuncore_xd3200.dts
+++ b/target/linux/ath79/dts/qca9563_yuncore_xd3200.dts
@@ -30,3 +30,10 @@
 		};
 	};
 };
+
+&pcie {
+	wifi@0,0 {
+		nvmem-cells = <&cal_art_5000>;
+		nvmem-cell-names = "calibration";
+	};
+};
diff --git a/target/linux/ath79/dts/qca9563_yuncore_xd4200.dtsi b/target/linux/ath79/dts/qca9563_yuncore_xd4200.dtsi
index dff9428295067b..2cc227a2dad674 100644
--- a/target/linux/ath79/dts/qca9563_yuncore_xd4200.dtsi
+++ b/target/linux/ath79/dts/qca9563_yuncore_xd4200.dtsi
@@ -57,6 +57,8 @@
 	wifi@0,0 {
 		compatible = "pci168c,0056";
 		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&precal_art_5000>;
+		nvmem-cell-names = "pre-calibration";
 	};
 };
 
@@ -103,6 +105,14 @@
 					macaddr_art_0: macaddr@0 {
 						reg = <0x0 0x6>;
 					};
+
+					cal_art_5000: calibration@5000 {
+						reg = <0x5000 0x844>;
+					};
+
+					precal_art_5000: pre-calibration@5000 {
+						reg = <0x5000 0x2f20>;
+					};
 				};
 			};
 		};
diff --git a/target/linux/ath79/dts/qca9563_zte_mf281.dts b/target/linux/ath79/dts/qca9563_zte_mf281.dts
index 8fcd093d66f494..d0693658a4dbdd 100644
--- a/target/linux/ath79/dts/qca9563_zte_mf281.dts
+++ b/target/linux/ath79/dts/qca9563_zte_mf281.dts
@@ -16,7 +16,6 @@
 };
 
 &led_debug {
-	label = "green:debug";
 	color = <LED_COLOR_ID_GREEN>;
 };
 
diff --git a/target/linux/ath79/dts/qca9563_zte_mf282.dts b/target/linux/ath79/dts/qca9563_zte_mf282.dts
index 439cc1af4af943..12c8f00d1f3b11 100644
--- a/target/linux/ath79/dts/qca9563_zte_mf282.dts
+++ b/target/linux/ath79/dts/qca9563_zte_mf282.dts
@@ -28,7 +28,6 @@
 };
 
 &led_debug {
-	label = "blue:debug";
 	color = <LED_COLOR_ID_BLUE>;
 };
 
diff --git a/target/linux/ath79/dts/qca9563_zte_mf286.dts b/target/linux/ath79/dts/qca9563_zte_mf286.dts
index e64680e1121541..4b92239666123c 100644
--- a/target/linux/ath79/dts/qca9563_zte_mf286.dts
+++ b/target/linux/ath79/dts/qca9563_zte_mf286.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 // Copyright (c) 2021 Cezary Jackiewicz
+
+#include <dt-bindings/leds/common.h>
 // Copyright (c) 2021, 2022 Lech Perczak
 #include "qca9563_zte_mf286.dtsi"
 
@@ -30,7 +32,8 @@
 	 * and slightly through the case below signal state LEDs
 	 */
 	color = <LED_COLOR_ID_GREEN>;
-	label = "green:debug";
+	function = LED_FUNCTION_DEBUG;
+	color = <LED_COLOR_ID_GREEN>;
 };
 
 &boot_flash {
diff --git a/target/linux/ath79/dts/qca9563_zte_mf286ar.dtsi b/target/linux/ath79/dts/qca9563_zte_mf286ar.dtsi
index 89177ef2d35027..9a42ea668ac6db 100644
--- a/target/linux/ath79/dts/qca9563_zte_mf286ar.dtsi
+++ b/target/linux/ath79/dts/qca9563_zte_mf286ar.dtsi
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 // Copyright (c) 2021 Cezary Jackiewicz
+
+#include <dt-bindings/leds/common.h>
 // Copyright (c) 2021, 2022 Lech Perczak
 #include "qca9563_zte_mf286.dtsi"
 
@@ -27,7 +29,8 @@
 	 * and slightly through the case below signal state LEDs
 	 */
 	color = <LED_COLOR_ID_BLUE>;
-	label = "blue:debug";
+	function = LED_FUNCTION_DEBUG;
+	color = <LED_COLOR_ID_BLUE>;
 };
 
 &boot_flash {
diff --git a/target/linux/ath79/dts/qcn5502_asus_rt-ac59u.dtsi b/target/linux/ath79/dts/qcn5502_asus_rt-ac59u.dtsi
index ffc2b8934516e5..3d3df1adccaa53 100644
--- a/target/linux/ath79/dts/qcn5502_asus_rt-ac59u.dtsi
+++ b/target/linux/ath79/dts/qcn5502_asus_rt-ac59u.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -35,12 +36,14 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
 		};
 
 		usb {
-			label = "blue:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&hub_port0>;
 			linux,default-trigger = "usbport";
diff --git a/target/linux/ath79/dts/qcn5502_netgear_ex7300-v2.dts b/target/linux/ath79/dts/qcn5502_netgear_ex7300-v2.dts
index 32b97a4601371a..24a54834fd36a6 100644
--- a/target/linux/ath79/dts/qcn5502_netgear_ex7300-v2.dts
+++ b/target/linux/ath79/dts/qcn5502_netgear_ex7300-v2.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Netgear EX7300 v2";
@@ -40,17 +41,20 @@
 		compatible = "gpio-leds";
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_amber: power_amber {
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&led_gpio 7 GPIO_ACTIVE_LOW>;
 		};
 
 		wps_green {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ath79/dts/qcn5502_tplink_archer-a9-v6.dts b/target/linux/ath79/dts/qcn5502_tplink_archer-a9-v6.dts
index 6266f5561be39c..76137c73c4e87d 100644
--- a/target/linux/ath79/dts/qcn5502_tplink_archer-a9-v6.dts
+++ b/target/linux/ath79/dts/qcn5502_tplink_archer-a9-v6.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "TP-Link Archer A9 v6";
@@ -39,25 +40,29 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
 			trigger-sources = <&hub_port0>;
 			linux,default-trigger = "usbport";
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
 		};
 
 		wan_orange {
-			label = "orange:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
 		};
 
@@ -74,7 +79,8 @@
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ath79/dts/tp9343_tplink_tl-wa901nd.dtsi b/target/linux/ath79/dts/tp9343_tplink_tl-wa901nd.dtsi
index 6b27468551e22f..1cf74619260ed0 100644
--- a/target/linux/ath79/dts/tp9343_tplink_tl-wa901nd.dtsi
+++ b/target/linux/ath79/dts/tp9343_tplink_tl-wa901nd.dtsi
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "tp9343_tplink_tl-wx.dtsi"
 
 / {
@@ -35,12 +37,14 @@
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ath79/dts/tp9343_tplink_tl-wr940n-v3.dtsi b/target/linux/ath79/dts/tp9343_tplink_tl-wr940n-v3.dtsi
index b38cd418176af3..7780e0172c3370 100644
--- a/target/linux/ath79/dts/tp9343_tplink_tl-wr940n-v3.dtsi
+++ b/target/linux/ath79/dts/tp9343_tplink_tl-wr940n-v3.dtsi
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "tp9343_tplink_tl-wr94x.dtsi"
 
 / {
@@ -25,18 +27,21 @@
 		};
 
 		wlan {
-			label = "blue:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
 
 		wan_blue {
-			label = "blue:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		};
 
 		wan_red {
-			label = "red:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
 		};
 
diff --git a/target/linux/ath79/dts/tp9343_tplink_tl-wr940n-v4.dts b/target/linux/ath79/dts/tp9343_tplink_tl-wr940n-v4.dts
index f837dccff9af14..549bf4fea42030 100644
--- a/target/linux/ath79/dts/tp9343_tplink_tl-wr940n-v4.dts
+++ b/target/linux/ath79/dts/tp9343_tplink_tl-wr940n-v4.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "tp9343_tplink_tl-wr94x.dtsi"
 
 / {
@@ -28,18 +30,21 @@
 		};
 
 		wlan {
-			label = "blue:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
 
 		wan_blue {
-			label = "blue:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		};
 
 		wan_red {
-			label = "red:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
 		};
 
diff --git a/target/linux/ath79/dts/tp9343_tplink_tl-wr940n-v6.dts b/target/linux/ath79/dts/tp9343_tplink_tl-wr940n-v6.dts
index ccb3bb167090b1..04517cffd4927f 100644
--- a/target/linux/ath79/dts/tp9343_tplink_tl-wr940n-v6.dts
+++ b/target/linux/ath79/dts/tp9343_tplink_tl-wr940n-v6.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "tp9343_tplink_tl-wr94x.dtsi"
 
 / {
@@ -17,7 +19,8 @@
 		compatible = "gpio-leds";
 
 		wan_blue {
-			label = "blue:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ath79/dts/tp9343_tplink_tl-wr941hp-v1.dts b/target/linux/ath79/dts/tp9343_tplink_tl-wr941hp-v1.dts
index 61adc08289a985..aaca7fa531b9fd 100644
--- a/target/linux/ath79/dts/tp9343_tplink_tl-wr941hp-v1.dts
+++ b/target/linux/ath79/dts/tp9343_tplink_tl-wr941hp-v1.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "tplink,tl-wr941hp-v1", "qca,tp9343";
@@ -32,28 +33,33 @@
 		};
 
 		led_power: power {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		wan_blue {
-			label = "blue:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		};
 
 		wan_red {
-			label = "red:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 		};
 
 		lan {
-			label = "blue:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
 		};
 
 		wps {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ath79/generic/base-files/etc/board.d/02_network b/target/linux/ath79/generic/base-files/etc/board.d/02_network
index 01747acae00a48..4e08860cfadcaf 100644
--- a/target/linux/ath79/generic/base-files/etc/board.d/02_network
+++ b/target/linux/ath79/generic/base-files/etc/board.d/02_network
@@ -144,6 +144,9 @@ ath79_setup_interfaces()
 	alfa-network,n5q|\
 	devolo,dvl1200e|\
 	devolo,dvl1750e|\
+	elecom,wab-i1750-ps|\
+	elecom,wab-s1167-ps|\
+	elecom,wab-s600-ps|\
 	engenius,enstationac-v1|\
 	engenius,ews511ap|\
 	engenius,ews660ap|\
@@ -496,6 +499,11 @@ ath79_setup_interfaces()
 		ucidef_add_switch "switch0" \
 			"0@eth1" "3:lan:3" "4:lan:2" "5:lan:1" "6@eth0" "2:wan:4" "1:wan:5"
 		;;
+	tplink,deco-m4r-v1|\
+	tplink,deco-s4-v2)
+		ucidef_add_switch "switch0" \
+			"0@eth0" "3:lan:1" "5:lan:2"
+		;;
 	tplink,eap225-wall-v2)
 		ucidef_add_switch "switch0" \
 			"0@eth0" "1:lan" "2:lan" "3:lan" "4:lan"
@@ -572,11 +580,6 @@ ath79_setup_interfaces()
 		ucidef_add_switch "switch0" \
 			"0@eth0" "1:lan" "2:lan"
 		;;
-	tplink,deco-m4r-v1|\
-	tplink,deco-s4-v2)
-		ucidef_add_switch "switch0" \
-			"0@eth0" "3:lan:1" "5:lan:2"
-		;;
 	hiwifi,hc6361|\
 	xiaomi,mi-router-4q|\
 	zbtlink,zbt-wd323)
@@ -702,16 +705,19 @@ ath79_setup_macs()
 		lan_mac=$(mtd_get_mac_ascii devdata "lanmac")
 		wan_mac=$(mtd_get_mac_ascii devdata "wanmac")
 		;;
-	elecom,wrc-1750ghbk2-i|\
-	elecom,wrc-300ghbk2-i)
-		wan_mac=$(mtd_get_mac_ascii hwconfig "HW.WAN.MAC.Address")
-		label_mac=$wan_mac
-		;;
+	elecom,wab-i1750-ps|\
+	elecom,wab-s1167-ps|\
+	elecom,wab-s600-ps|\
 	engenius,ecb1200|\
 	engenius,ecb1750)
 		lan_mac=$(mtd_get_mac_ascii u-boot-env ethaddr)
 		label_mac=$lan_mac
 		;;
+	elecom,wrc-1750ghbk2-i|\
+	elecom,wrc-300ghbk2-i)
+		wan_mac=$(mtd_get_mac_ascii hwconfig "HW.WAN.MAC.Address")
+		label_mac=$wan_mac
+		;;
 	engenius,epg5000|\
 	engenius,esr1200|\
 	engenius,esr1750|\
diff --git a/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata b/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata
index 1acbf35947036e..19b02a5905238a 100644
--- a/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata
+++ b/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata
@@ -3,200 +3,12 @@
 [ -e /lib/firmware/$FIRMWARE ] && exit 0
 
 . /lib/functions/caldata.sh
-. /lib/functions/k2t.sh
 
 board=$(board_name)
 
 case "$FIRMWARE" in
-"ath10k/cal-pci-0000:00:00.0.bin")
-	case $board in
-	allnet,all-wap02860ac|\
-	araknis,an-500-ap-i-ac|\
-	araknis,an-700-ap-i-ac|\
-	comfast,cf-e380ac-v2|\
-	engenius,enstationac-v1|\
-	glinet,gl-x750|\
-	watchguard,ap300)
-		caldata_extract "art" 0x5000 0x844
-		ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary art 0x0) 2)
-		;;
-	asus,pl-ac56|\
-	asus,rp-ac66|\
-	comfast,cf-wr650ac-v1|\
-	comfast,cf-wr650ac-v2|\
-	devolo,dlan-pro-1200plus-ac|\
-	devolo,magic-2-wifi|\
-	joyit,jt-or750i|\
-	qxwlan,e1700ac-v2-8m|\
-	qxwlan,e1700ac-v2-16m|\
-	qxwlan,e600gac-v2-8m|\
-	qxwlan,e600gac-v2-16m|\
-	sophos,ap15|\
-	sophos,ap55|\
-	sophos,ap55c|\
-	sophos,ap100|\
-	sophos,ap100c|\
-	ubnt,bullet-ac|\
-	ubnt,uk-ultra|\
-	ubnt,unifiac-lite|\
-	ubnt,unifiac-lr|\
-	ubnt,unifiac-mesh|\
-	ubnt,unifiac-mesh-pro|\
-	ubnt,lap-120|\
-	ubnt,litebeam-ac-gen2|\
-	ubnt,nanobeam-ac|\
-	ubnt,nanobeam-ac-gen2|\
-	ubnt,nanobeam-ac-xc|\
-	ubnt,nanostation-ac|\
-	ubnt,nanostation-ac-loco|\
-	ubnt,powerbeam-5ac-500|\
-	ubnt,powerbeam-5ac-gen2|\
-	ubnt,rocket-5ac-lite|\
-	ubnt,unifiac-pro|\
-	yuncore,a770|\
-	yuncore,xd3200)
-		caldata_extract "art" 0x5000 0x844
-		;;
-	avm,fritz1750e|\
-	avm,fritzdvbc)
-		caldata_extract "urlader" 0x198a 0x844
-		;;
-	devolo,dvl1200e|\
-	devolo,dvl1200i|\
-	devolo,dvl1750c|\
-	devolo,dvl1750e|\
-	devolo,dvl1750i|\
-	devolo,dvl1750x)
-		caldata_extract "art" 0x5000 0x844
-		ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary art 0x0) -1)
-		;;
-	engenius,ecb1200|\
-	engenius,ecb1750)
-		caldata_extract "art" 0x5000 0x844
-		ath10k_patch_mac $(mtd_get_mac_ascii u-boot-env athaddr)
-		;;
-	engenius,ews511ap)
-		caldata_extract "art" 0x5000 0x844
-		ath10k_patch_mac $(macaddr_add $(cat /sys/class/net/eth0/address) 1)
-		;;
-	extreme-networks,ws-ap3805i)
-		caldata_extract "art" 0x5000 0x844
-		ath10k_patch_mac $(mtd_get_mac_ascii cfg1 RADIOADDR0)
-		;;
-	glinet,gl-ar750)
-		caldata_extract "art" 0x5000 0x844
-		ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary art 0x0) 1)
-		;;
-	iodata,wn-ac1167dgr|\
-	iodata,wn-ac1600dgr2|\
-	sitecom,wlr-7100|\
-	zyxel,nbg6616)
-		caldata_extract "art" 0x5000 0x844
-		ath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii u-boot-env ethaddr) 1)
-		;;
-	nec,wg800hp)
-		caldata_extract "art" 0x5000 0x844
-		ath10k_patch_mac $(mtd_get_mac_text board_data 0x880)
-		;;
-	ocedo,koala|\
-	ocedo,ursus)
-		caldata_extract "art" 0x5000 0x844
-		ath10k_patch_mac $(mtd_get_mac_binary art 0xc)
-		;;
-	openmesh,a40|\
-	openmesh,a60|\
-	openmesh,mr1750-v1|\
-	openmesh,mr1750-v2|\
-	openmesh,om5p-ac-v2)
-		caldata_extract "ART" 0x5000 0x844
-		ath10k_patch_mac $(macaddr_add $(cat /sys/class/net/eth0/address) 16)
-		;;
-	qihoo,c301)
-		caldata_extract "radiocfg" 0x5000 0x844
-		ath10k_patch_mac $(mtd_get_mac_ascii devdata wlan5mac)
-		;;
-	tplink,archer-a7-v5|\
-	tplink,archer-c2-v3|\
-	tplink,archer-c7-v4|\
-	tplink,archer-c7-v5|\
-	tplink,archer-c25-v1|\
-	tplink,tl-wr902ac-v1)
-		caldata_extract "art" 0x5000 0x844
-		ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary info 0x8) -1)
-		;;
-	tplink,archer-c5-v1|\
-	tplink,tl-wdr7500-v3)
-		caldata_extract "art" 0x5000 0x844
-		ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary u-boot 0x1fc00) -1)
-		;;
-	tplink,archer-d50-v1)
-		caldata_extract "art" 0x5000 0x844
-		ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary romfile 0xf100) 2)
-		;;
-	tplink,archer-d7-v1|\
-	tplink,archer-d7b-v1)
-		caldata_extract "art" 0x5000 0x844
-		ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary romfs 0xf100) 2)
-		;;
-	tplink,re350k-v1)
-		caldata_extract "art" 0x5000 0x844
-		ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary info 0x8) 2)
-		;;
-	tplink,re355-v1|\
-	tplink,re450-v1)
-		caldata_extract "art" 0x5000 0x844
-		ath10k_patch_mac $(macaddr_add $(cat /sys/class/net/eth0/address) -2)
-		;;
-	tplink,re450-v2|\
-	tplink,re450-v3|\
-	tplink,re455-v1)
-		caldata_extract "art" 0x5000 0x844
-		ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary info 0x8) 1)
-		;;
-	tplink,tl-wpa8630-v1)
-		caldata_extract "art" 0x5000 0x844
-		ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary u-boot 0x0fc00) 1)
-		;;
-	esac
-	;;
-"ath10k/cal-pci-0000:01:00.0.bin")
-	case $board in
-	openmesh,om5p-ac-v1)
-		caldata_extract "ART" 0x5000 0x844
-		ath10k_patch_mac $(macaddr_add $(cat /sys/class/net/eth0/address) +16)
-		;;
-	sitecom,wlr-8100)
-		caldata_extract "art" 0x5000 0x844
-		ath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii u-boot-env ethaddr) 1)
-		;;
-	esac
-	;;
 "ath10k/pre-cal-pci-0000:00:00.0.bin")
 	case $board in
-	asus,rp-ac51|\
-	yuncore,a782|\
-	yuncore,xd4200)
-		caldata_extract "art" 0x5000 0x2f20
-		ln -sf /lib/firmware/ath10k/pre-cal-pci-0000\:00\:00.0.bin \
-			/lib/firmware/ath10k/QCA9888/hw2.0/board.bin
-		;;
-	comfast,cf-e313ac)
-		caldata_extract "art" 0x5000 0x2f20
-		ath10k_patch_mac $(mtd_get_mac_binary art 0x6)
-		ln -sf /lib/firmware/ath10k/pre-cal-pci-0000\:00\:00.0.bin \
-			/lib/firmware/ath10k/QCA9888/hw2.0/board.bin
-		rm /lib/firmware/ath10k/QCA9888/hw2.0/board-2.bin
-		;;
-	comfast,cf-e375ac|\
-	comfast,cf-e560ac|\
-	comfast,cf-ew72|\
-	comfast,cf-wr752ac-v1)
-		caldata_extract "art" 0x5000 0x2f20
-		ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary art 0x0) 2)
-		ln -sf /lib/firmware/ath10k/pre-cal-pci-0000\:00\:00.0.bin \
-			/lib/firmware/ath10k/QCA9888/hw2.0/board.bin
-		rm /lib/firmware/ath10k/QCA9888/hw2.0/board-2.bin
-		;;
 	dlink,dir-842-c1|\
 	dlink,dir-842-c2|\
 	dlink,dir-842-c3)
@@ -206,57 +18,6 @@ case "$FIRMWARE" in
 		ln -sf /lib/firmware/ath10k/pre-cal-pci-0000\:00\:00.0.bin \
 			/lib/firmware/ath10k/QCA9888/hw2.0/board.bin
 		;;
-	nec,wf1200cr|\
-	nec,wg1200cr)
-		caldata_extract "art" 0x5000 0x2f20
-		ath10k_patch_mac $(mtd_get_mac_ascii devdata wlan5mac)
-		ln -sf /lib/firmware/ath10k/pre-cal-pci-0000\:00\:00.0.bin \
-			/lib/firmware/ath10k/QCA9888/hw2.0/board.bin
-		;;
-	phicomm,k2t)
-		caldata_extract "art" 0x5000 0x2f20
-		ath10k_patch_mac $(k2t_get_mac "5g_mac")
-		ln -sf /lib/firmware/ath10k/pre-cal-pci-0000\:00\:00.0.bin \
-			/lib/firmware/ath10k/QCA9888/hw2.0/board.bin
-		;;
-	tplink,archer-c58-v1|\
-	tplink,archer-c59-v1|\
-	tplink,archer-c59-v2|\
-	tplink,archer-c60-v1|\
-	tplink,archer-c60-v2|\
-	tplink,archer-c60-v3|\
-	tplink,archer-c6-v2|\
-	tplink,archer-c6-v2-us|\
-	tplink,tl-wa1201-v2)
-		caldata_extract "art" 0x5000 0x2f20
-		ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary info 0x8) -1)
-		ln -sf /lib/firmware/ath10k/pre-cal-pci-0000\:00\:00.0.bin \
-			/lib/firmware/ath10k/QCA9888/hw2.0/board.bin
-		;;
-	tplink,cpe710-v1)
-		caldata_extract "art" 0x5000 0x2f20
-		ath10k_patch_mac $(mtd_get_mac_binary info 0x8)
-		ln -sf /lib/firmware/ath10k/pre-cal-pci-0000\:00\:00.0.bin \
-			/lib/firmware/ath10k/QCA9888/hw2.0/board.bin
-		;;
-	xiaomi,aiot-ac2350)
-		caldata_extract "art" 0x5000 0x2f20
-		ln -sf /lib/firmware/ath10k/pre-cal-pci-0000\:00\:00.0.bin \
-			/lib/firmware/ath10k/QCA9984/hw1.0/board.bin
-		;;
-	tplink,deco-m4r-v1)
-		caldata_extract "art" 0x5000 0x2f20
-		ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary config 0x8) -1)
-		ln -sf /lib/firmware/ath10k/pre-cal-pci-0000\:00\:00.0.bin \
-			/lib/firmware/ath10k/QCA9888/hw2.0/board.bin
-		;;
-	tplink,deco-s4-v2)
-		caldata_extract "art" 0x5000 0x2f20
-		base_mac=$(mtd_get_mac_encrypted_deco $(find_mtd_part config))
-		ath10k_patch_mac $(macaddr_add $base_mac 2)
-		ln -sf /lib/firmware/ath10k/pre-cal-pci-0000\:00\:00.0.bin \
-			/lib/firmware/ath10k/QCA9888/hw2.0/board.bin
-		;;
 	esac
 	;;
 *)
diff --git a/target/linux/ath79/generic/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac b/target/linux/ath79/generic/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac
index 42b69d2ca0c4dd..9574d8a17d90b5 100644
--- a/target/linux/ath79/generic/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac
+++ b/target/linux/ath79/generic/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac
@@ -41,13 +41,41 @@ case "$board" in
 		[ "$PHYNBR" -eq 1 ] && \
 			mtd_get_mac_ascii bdcfg "wlanmac" > /sys${DEVPATH}/macaddress
 		;;
+	elecom,wab-i1750-ps|\
+	elecom,wab-s1167-ps|\
+	elecom,wab-s600-ps)
+		# set the 5G MAC address (= ethaddr + 1)
+		[ "$PHYNBR" -eq 0 ] && \
+			macaddr_add "$(mtd_get_mac_ascii u-boot-env ethaddr)" 1 > /sys${DEVPATH}/macaddress
+		# set the 2.4G MAC address (= ethaddr)
+		[ "$PHYNBR" -eq 1 ] && \
+			mtd_get_mac_ascii u-boot-env "ethaddr" > /sys${DEVPATH}/macaddress
+		;;
+	engenius,ecb1200|\
+	engenius,ecb1750)
+		[ "$PHYNBR" -eq 0 ] && \
+		mtd_get_mac_ascii u-boot-env ethaddr > /sys${DEVPATH}/macaddress
+		;;
 	engenius,epg5000|\
 	engenius,esr1200|\
 	engenius,esr1750|\
 	engenius,esr900)
 		macaddr_add "$(mtd_get_mac_ascii u-boot-env ethaddr)" "$PHYNBR" > /sys${DEVPATH}/macaddress
 		;;
-	iodata,wn-ac1600dgr)
+	engenius,ews511ap)
+		[ "$PHYNBR" -eq 0 ] && \
+		macaddr_add $(cat /sys/class/net/eth0/address) 1 > /sys${DEVPATH}/macaddress
+		;;
+	extreme-networks,ws-ap3805i)
+		[ "$PHYNBR" -eq 0 ] && \
+		mtd_get_mac_ascii cfg1 RADIOADDR0 > /sys${DEVPATH}/macaddress
+		;;
+	iodata,wn-ac1167dgr|\
+	iodata,wn-ac1600dgr|\
+	iodata,wn-ac1600dgr2|\
+	sitecom,wlr-7100|\
+	sitecom,wlr-8100|\
+	zyxel,nbg6616)
 		# There is no eeprom data for 5 GHz wlan in "art" partition
 		# which would allow to patch the macaddress
 		[ "$PHYNBR" -eq 0 ] && \
@@ -59,13 +87,27 @@ case "$board" in
 		[ "$PHYNBR" -eq 1 ] && \
 			macaddr_add "$(mtd_get_mac_ascii u-boot-env ethaddr)" 1 > /sys${DEVPATH}/macaddress
 		;;
+	nec,wf1200cr|\
+	nec,wg1200cr|\
+	qihoo,c301)
+		[ "$PHYNBR" -eq 0 ] && \
+			mtd_get_mac_ascii devdata wlan5mac > /sys${DEVPATH}/macaddress
+		;;
 	phicomm,k2t)
+		[ "$PHYNBR" -eq 0 ] && \
+			k2t_get_mac "5g_mac" > /sys${DEVPATH}/macaddress
 		# The K2T factory firmware does use LAN mac address as the 2.4G wifi mac address
 		[ "$PHYNBR" -eq 1 ] && \
 			k2t_get_mac "lan_mac" > /sys${DEVPATH}/macaddress
 		;;
 	siemens,ws-ap3610)
 		mtd_get_mac_ascii cfg1 RADIOADDR${PHYNBR} > /sys${DEVPATH}/macaddress
+		;;
+	tplink,deco-s4-v2)
+		base_mac=$(mtd_get_mac_encrypted_deco $(find_mtd_part config))
+		[ "$PHYNBR" -eq 0 ] && \
+			macaddr_add $base_mac 2 > /sys${DEVPATH}/macaddress
+
 		;;
 	trendnet,tew-823dru)
 		# set the 2.4G interface mac address to LAN MAC
diff --git a/target/linux/ath79/image/common-ubnt.mk b/target/linux/ath79/image/common-ubnt.mk
index f44e06e1109865..6dd5ae146062dd 100644
--- a/target/linux/ath79/image/common-ubnt.mk
+++ b/target/linux/ath79/image/common-ubnt.mk
@@ -74,7 +74,7 @@ define Device/ubnt-2wa
   UBNT_BOARD := WA
   UBNT_CHIP := ar934x
   UBNT_TYPE := 2WA
-  UBNT_VERSION := 8.5.3
+  UBNT_VERSION := 8.7.4
 endef
 
 define Device/ubnt-wa
@@ -84,7 +84,7 @@ define Device/ubnt-wa
   UBNT_BOARD := WA
   UBNT_CHIP := ar934x
   UBNT_TYPE := WA
-  UBNT_VERSION := 8.5.3
+  UBNT_VERSION := 8.7.4
 endef
 
 define Device/ubnt-xc
@@ -93,7 +93,7 @@ define Device/ubnt-xc
   UBNT_BOARD := XC
   UBNT_CHIP := qca955x
   UBNT_TYPE := XC
-  UBNT_VERSION := 8.5.3
+  UBNT_VERSION := 8.7.4
 endef
 
 define Device/ubnt-xm
diff --git a/target/linux/ath79/image/generic.mk b/target/linux/ath79/image/generic.mk
index 68c41055615130..3bdc0437389041 100644
--- a/target/linux/ath79/image/generic.mk
+++ b/target/linux/ath79/image/generic.mk
@@ -9,6 +9,7 @@ DEVICE_VARS += ADDPATTERN_ID ADDPATTERN_VERSION
 DEVICE_VARS += SEAMA_SIGNATURE SEAMA_MTDBLOCK
 DEVICE_VARS += KERNEL_INITRAMFS_PREFIX DAP_SIGNATURE
 DEVICE_VARS += EDIMAX_HEADER_MAGIC EDIMAX_HEADER_MODEL
+DEVICE_VARS += ELECOM_HWID
 DEVICE_VARS += MOXA_MAGIC MOXA_HWID
 DEVICE_VARS += OPENMESH_CE_TYPE ZYXEL_MODEL_STRING
 DEVICE_VARS += SUPPORTED_TELTONIKA_DEVICES
@@ -1316,6 +1317,40 @@ define Device/dlink_dir-869-a1
 endef
 TARGET_DEVICES += dlink_dir-869-a1
 
+define Device/elecom_wab
+  DEVICE_VENDOR := ELECOM
+  IMAGE_SIZE := 14336k
+  IMAGES += factory.bin
+  IMAGE/factory.bin := append-kernel | pad-to $$$$(BLOCKSIZE) | append-rootfs | \
+	pad-rootfs | check-size | elx-header $$$$(ELECOM_HWID) 8844A2D168B45A2D
+  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca988x-ct kmod-gpio-beeper \
+	kmod-usb2 kmod-usb-ledtrig-usbport
+endef
+
+define Device/elecom_wab-i1750-ps
+  $(Device/elecom_wab)
+  SOC := qca9558
+  DEVICE_MODEL := WAB-I1750-PS
+  ELECOM_HWID := 0107000d
+endef
+TARGET_DEVICES += elecom_wab-i1750-ps
+
+define Device/elecom_wab-s1167-ps
+  $(Device/elecom_wab)
+  SOC := qca9557
+  DEVICE_MODEL := WAB-S1167-PS
+  ELECOM_HWID := 0107000c
+endef
+TARGET_DEVICES += elecom_wab-s1167-ps
+
+define Device/elecom_wab-s600-ps
+  $(Device/elecom_wab)
+  SOC := qca9557
+  DEVICE_MODEL := WAB-S600-PS
+  ELECOM_HWID := 01070028
+endef
+TARGET_DEVICES += elecom_wab-s600-ps
+
 define Device/elecom_wrc-1750ghbk2-i
   SOC := qca9563
   DEVICE_VENDOR := ELECOM
diff --git a/target/linux/ath79/image/nand.mk b/target/linux/ath79/image/nand.mk
index bf2b1a1f8ab15e..1a7eebc92a96fa 100644
--- a/target/linux/ath79/image/nand.mk
+++ b/target/linux/ath79/image/nand.mk
@@ -190,7 +190,8 @@ define Device/glinet_gl-e750
   SOC := qca9531
   DEVICE_VENDOR := GL.iNet
   DEVICE_MODEL := GL-E750
-  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca9887-ct kmod-usb2
+  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca9887-ct kmod-usb2 \
+	kmod-usb-net-qmi-wwan kmod-usb-serial-option uqmi
   SUPPORTED_DEVICES += gl-e750
   KERNEL_SIZE := 4096k
   IMAGE_SIZE := 131072k
@@ -311,6 +312,7 @@ define Device/meraki_mr18
 # KERNEL_INITRAMFS := $$(KERNEL)
   KERNEL_INITRAMFS :=
   IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
+  SUPPORTED_DEVICES += mr18
 endef
 TARGET_DEVICES += meraki_mr18
 
diff --git a/target/linux/ath79/nand/base-files/etc/board.d/02_network b/target/linux/ath79/nand/base-files/etc/board.d/02_network
index f5dda414c2ffa9..b60586a15effa2 100644
--- a/target/linux/ath79/nand/base-files/etc/board.d/02_network
+++ b/target/linux/ath79/nand/base-files/etc/board.d/02_network
@@ -8,7 +8,6 @@ ath79_setup_interfaces()
 
 	case "$board" in
 	aerohive,hiveap-121|\
-	glinet,gl-e750|\
 	meraki,mr18)
 		ucidef_set_interface_lan "eth0"
 		;;
@@ -26,6 +25,11 @@ ath79_setup_interfaces()
 		ucidef_add_switch "switch0" \
 			"0@eth0" "2:lan:2" "3:lan:1" "1:wan"
 		;;
+	glinet,gl-e750|\
+	zte,mf282)
+		ucidef_set_interface_lan "eth0"
+		ucidef_set_interface "wan" device "/dev/cdc-wdm0" protocol "qmi"
+		;;
 	glinet,gl-xe300)
 		ucidef_set_interface_wan "eth1"
 		ucidef_add_switch "switch0" \
@@ -40,8 +44,6 @@ ath79_setup_interfaces()
 		ucidef_add_switch "switch0" \
 			"6@eth1" "1:lan" "2:lan" "3:lan" "4:lan" "5:wan" "0@eth0"
 		;;
-	glinet,gl-s200-nor|\
-	glinet,gl-s200-nor-nand|\
 	netgear,pgzng1)
 		ucidef_set_interfaces_lan_wan "eth1" "eth0"
 		;;
@@ -69,10 +71,6 @@ ath79_setup_interfaces()
 		ucidef_add_switch "switch0" \
 			"0@eth0" "5:lan"
 		;;
-	zte,mf282)
-		ucidef_set_interface_lan "eth0"
-		ucidef_set_interface "wan" device "/dev/cdc-wdm0" protocol "qmi"
-		;;
 	zte,mf286|\
 	zte,mf286a|\
 	zte,mf286r)
diff --git a/target/linux/ath79/nand/base-files/etc/hotplug.d/firmware/11-ath10k-caldata b/target/linux/ath79/nand/base-files/etc/hotplug.d/firmware/11-ath10k-caldata
deleted file mode 100644
index d26625981ee3a8..00000000000000
--- a/target/linux/ath79/nand/base-files/etc/hotplug.d/firmware/11-ath10k-caldata
+++ /dev/null
@@ -1,31 +0,0 @@
-#!/bin/sh
-
-[ -e /lib/firmware/$FIRMWARE ] && exit 0
-
-. /lib/functions/caldata.sh
-
-board=$(board_name)
-
-case "$FIRMWARE" in
-"ath10k/cal-pci-0000:00:00.0.bin")
-	case $board in
-	domywifi,dw33d)
-		caldata_extract "art" 0x5000 0x844
-		ath10k_patch_mac $(mtd_get_mac_binary art 0x12)
-		;;
-	glinet,gl-ar750s-nor|\
-	glinet,gl-ar750s-nor-nand)
-		caldata_extract "art" 0x5000 0x844
-		ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary art 0x0) 1)
-		;;
-	zyxel,emg2926-q10a|\
-	zyxel,nbg6716)
-		caldata_extract "art" 0x5000 0x844
-		ath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii u-boot-env ethaddr) 1)
-		;;
-	esac
-	;;
-*)
-	exit 1
-	;;
-esac
diff --git a/target/linux/ath79/nand/base-files/etc/hotplug.d/ieee80211/10-fix-wifi-mac b/target/linux/ath79/nand/base-files/etc/hotplug.d/ieee80211/10-fix-wifi-mac
index 20974248c16743..5a933df501a7ab 100644
--- a/target/linux/ath79/nand/base-files/etc/hotplug.d/ieee80211/10-fix-wifi-mac
+++ b/target/linux/ath79/nand/base-files/etc/hotplug.d/ieee80211/10-fix-wifi-mac
@@ -17,8 +17,10 @@ case $board in
 		;;
 	zyxel,emg2926-q10a|\
 	zyxel,nbg6716)
-		# Set mac address for 2.4g device
+		ethaddr=$(mtd_get_mac_ascii u-boot-env ethaddr)
+		[ "$PHYNBR" -eq 0 ] && \
+			macaddr_add $ethaddr 1 > /sys${DEVPATH}/macaddress
 		[ "$PHYNBR" -eq 1 ] && \
-			mtd_get_mac_ascii u-boot-env ethaddr > /sys${DEVPATH}/macaddress
+			echo -n $ethaddr > /sys${DEVPATH}/macaddress
 		;;
 esac
diff --git a/target/linux/ath79/patches-5.15/800-leds-add-reset-controller-based-driver.patch b/target/linux/ath79/patches-5.15/800-leds-add-reset-controller-based-driver.patch
index 9daea4c95ab4b5..bbf8d7ef8c5105 100644
--- a/target/linux/ath79/patches-5.15/800-leds-add-reset-controller-based-driver.patch
+++ b/target/linux/ath79/patches-5.15/800-leds-add-reset-controller-based-driver.patch
@@ -13,7 +13,7 @@ Signed-off-by: John Crispin <john@phrozen.org>
 
 --- a/drivers/leds/Kconfig
 +++ b/drivers/leds/Kconfig
-@@ -877,6 +877,17 @@ source "drivers/leds/blink/Kconfig"
+@@ -878,6 +878,17 @@ source "drivers/leds/blink/Kconfig"
  comment "Flash and Torch LED drivers"
  source "drivers/leds/flash/Kconfig"
  
diff --git a/target/linux/ath79/patches-6.1/800-leds-add-reset-controller-based-driver.patch b/target/linux/ath79/patches-6.1/800-leds-add-reset-controller-based-driver.patch
index e9349b4f8c7ee3..0002b9b95b002f 100644
--- a/target/linux/ath79/patches-6.1/800-leds-add-reset-controller-based-driver.patch
+++ b/target/linux/ath79/patches-6.1/800-leds-add-reset-controller-based-driver.patch
@@ -13,7 +13,7 @@ Signed-off-by: John Crispin <john@phrozen.org>
 
 --- a/drivers/leds/Kconfig
 +++ b/drivers/leds/Kconfig
-@@ -873,6 +873,17 @@ source "drivers/leds/flash/Kconfig"
+@@ -874,6 +874,17 @@ source "drivers/leds/flash/Kconfig"
  comment "RGB LED drivers"
  source "drivers/leds/rgb/Kconfig"
  
diff --git a/target/linux/ath79/patches-6.1/900-unaligned_access_hacks.patch b/target/linux/ath79/patches-6.1/900-unaligned_access_hacks.patch
index 2235c28fd96adb..945143867ae37d 100644
--- a/target/linux/ath79/patches-6.1/900-unaligned_access_hacks.patch
+++ b/target/linux/ath79/patches-6.1/900-unaligned_access_hacks.patch
@@ -86,7 +86,7 @@ SVN-Revision: 35130
  	} while (word != stop);
  
  	return csum_fold(csum);
-@@ -179,73 +183,6 @@ static inline __sum16 ip_compute_csum(co
+@@ -179,74 +183,6 @@ static inline __sum16 ip_compute_csum(co
  	return csum_fold(csum_partial(buff, len, 0));
  }
  
@@ -152,7 +152,8 @@ SVN-Revision: 35130
 -	"	.set	pop"
 -	: "=&r" (sum), "=&r" (tmp)
 -	: "r" (saddr), "r" (daddr),
--	  "0" (htonl(len)), "r" (htonl(proto)), "r" (sum));
+-	  "0" (htonl(len)), "r" (htonl(proto)), "r" (sum)
+-	: "memory");
 -
 -	return csum_fold(sum);
 -}
@@ -336,7 +337,7 @@ SVN-Revision: 35130
  #endif /* _LINUX_TYPES_H */
 --- a/net/ipv4/af_inet.c
 +++ b/net/ipv4/af_inet.c
-@@ -1512,8 +1512,8 @@ struct sk_buff *inet_gro_receive(struct
+@@ -1515,8 +1515,8 @@ struct sk_buff *inet_gro_receive(struct
  	if (unlikely(ip_fast_csum((u8 *)iph, 5)))
  		goto out;
  
diff --git a/target/linux/ath79/patches-6.1/910-mikrotik-rb4xx.patch b/target/linux/ath79/patches-6.1/910-mikrotik-rb4xx.patch
index b61eef0b8a88ba..9a163e70b393f4 100644
--- a/target/linux/ath79/patches-6.1/910-mikrotik-rb4xx.patch
+++ b/target/linux/ath79/patches-6.1/910-mikrotik-rb4xx.patch
@@ -45,7 +45,7 @@ Submitted-by: Christopher Hill <ch6574@gmail.com>
 
 --- a/drivers/mfd/Kconfig
 +++ b/drivers/mfd/Kconfig
-@@ -2208,6 +2208,14 @@ config RAVE_SP_CORE
+@@ -2209,6 +2209,14 @@ config RAVE_SP_CORE
  	  Select this to get support for the Supervisory Processor
  	  device found on several devices in RAVE line of hardware.
  
diff --git a/target/linux/ath79/tiny/base-files/etc/hotplug.d/firmware/11-ath10k-caldata b/target/linux/ath79/tiny/base-files/etc/hotplug.d/firmware/11-ath10k-caldata
deleted file mode 100644
index 8e3e142ec972b8..00000000000000
--- a/target/linux/ath79/tiny/base-files/etc/hotplug.d/firmware/11-ath10k-caldata
+++ /dev/null
@@ -1,25 +0,0 @@
-#!/bin/sh
-
-[ -e /lib/firmware/$FIRMWARE ] && exit 0
-
-. /lib/functions/caldata.sh
-
-board=$(board_name)
-
-case "$FIRMWARE" in
-"ath10k/pre-cal-pci-0000:00:00.0.bin")
-	case $board in
-	tplink,tl-wpa8630p-v2-int|\
-	tplink,tl-wpa8630p-v2.0-eu|\
-	tplink,tl-wpa8630p-v2.1-eu)
-		caldata_extract "art" 0x5000 0x2f20
-		ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary info 0x8) 1)
-		ln -sf /lib/firmware/ath10k/pre-cal-pci-0000\:00\:00.0.bin \
-			/lib/firmware/ath10k/QCA9888/hw2.0/board.bin
-		;;
-	esac
-	;;
-*)
-	exit 1
-	;;
-esac
diff --git a/target/linux/bcm27xx/base-files/lib/preinit/05_set_preinit_iface_brcm2708 b/target/linux/bcm27xx/base-files/lib/preinit/05_set_preinit_iface_brcm2708
index c52995bd177603..120475b55dcda6 100644
--- a/target/linux/bcm27xx/base-files/lib/preinit/05_set_preinit_iface_brcm2708
+++ b/target/linux/bcm27xx/base-files/lib/preinit/05_set_preinit_iface_brcm2708
@@ -12,6 +12,7 @@ set_preinit_iface() {
 	raspberrypi,400 |\
 	raspberrypi,4-compute-module |\
 	raspberrypi,4-model-b |\
+	raspberrypi,5-model-b |\
 	raspberrypi,model-b |\
 	raspberrypi,model-b-plus |\
 	raspberrypi,model-b-rev2)
diff --git a/target/linux/bcm27xx/base-files/lib/preinit/79_move_config b/target/linux/bcm27xx/base-files/lib/preinit/79_move_config
index c9fb59a64fe62e..db5bf93b626b00 100644
--- a/target/linux/bcm27xx/base-files/lib/preinit/79_move_config
+++ b/target/linux/bcm27xx/base-files/lib/preinit/79_move_config
@@ -2,16 +2,20 @@
 
 . /lib/upgrade/common.sh
 
-BOOTPART=/dev/mmcblk0p1
-
 move_config() {
-	if [ -b $BOOTPART ]; then
+	local partdev
+
+	export_bootdevice && export_partdevice partdev 1 || {
+		partdev=mmcblk0p1
+	}
+
+	if [ -b "/dev/$partdev" ]; then
 		insmod nls_cp437
 		insmod nls_iso8859-1
 		insmod fat
 		insmod vfat
 		mkdir -p /boot
-		mount -t vfat -o rw,noatime $BOOTPART /boot
+		mount -t vfat -o rw,noatime /dev/$partdev /boot
 		[ -f "/boot/$BACKUP_FILE" ] && mv -f "/boot/$BACKUP_FILE" /
 	fi
 }
diff --git a/target/linux/bcm27xx/base-files/lib/upgrade/platform.sh b/target/linux/bcm27xx/base-files/lib/upgrade/platform.sh
index a48b7cc08a3ee5..956bc1c7886ae1 100644
--- a/target/linux/bcm27xx/base-files/lib/upgrade/platform.sh
+++ b/target/linux/bcm27xx/base-files/lib/upgrade/platform.sh
@@ -90,7 +90,7 @@ platform_copy_config() {
 
 	if export_partdevice partdev 1; then
 		mkdir -p /boot
-		[ -f /boot/kernel.img ] || mount -t vfat -o rw,noatime "/dev/$partdev" /boot
+		[ -f "/boot/kernel*.img" ] || mount -t vfat -o rw,noatime "/dev/$partdev" /boot
 		cp -af "$UPGRADE_BACKUP" "/boot/$BACKUP_FILE"
 		tar -C / -zxvf "$UPGRADE_BACKUP" boot/cmdline.txt boot/config.txt
 		sync
diff --git a/target/linux/bcm27xx/bcm2708/config-6.1 b/target/linux/bcm27xx/bcm2708/config-6.1
index cef17940a35ad1..af5d0183ec1ebf 100644
--- a/target/linux/bcm27xx/bcm2708/config-6.1
+++ b/target/linux/bcm27xx/bcm2708/config-6.1
@@ -234,6 +234,12 @@ CONFIG_MAILBOX=y
 CONFIG_MDIO_BUS=y
 CONFIG_MDIO_DEVICE=y
 CONFIG_MDIO_DEVRES=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_CONTROLLER=y
+CONFIG_MEDIA_PLATFORM_DRIVERS=y
+CONFIG_MEDIA_PLATFORM_SUPPORT=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_SUPPORT_FILTER=y
 CONFIG_MEMFD_CREATE=y
 CONFIG_MEMORY_ISOLATION=y
 CONFIG_MFD_CORE=y
@@ -372,6 +378,8 @@ CONFIG_USB_USBNET=y
 CONFIG_USE_OF=y
 CONFIG_VCHIQ_CDEV=y
 CONFIG_VFP=y
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2_I2C=y
 CONFIG_VT=y
 CONFIG_VT_CONSOLE=y
 CONFIG_VT_CONSOLE_SLEEP=y
diff --git a/target/linux/bcm27xx/bcm2709/config-6.1 b/target/linux/bcm27xx/bcm2709/config-6.1
index 15bbaabd74c078..4d307add542e56 100644
--- a/target/linux/bcm27xx/bcm2709/config-6.1
+++ b/target/linux/bcm27xx/bcm2709/config-6.1
@@ -292,6 +292,12 @@ CONFIG_MDIO_BCM_UNIMAC=y
 CONFIG_MDIO_BUS=y
 CONFIG_MDIO_DEVICE=y
 CONFIG_MDIO_DEVRES=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_CONTROLLER=y
+CONFIG_MEDIA_PLATFORM_DRIVERS=y
+CONFIG_MEDIA_PLATFORM_SUPPORT=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_SUPPORT_FILTER=y
 CONFIG_MEMFD_CREATE=y
 CONFIG_MEMORY_ISOLATION=y
 CONFIG_MFD_CORE=y
@@ -472,6 +478,8 @@ CONFIG_USE_OF=y
 CONFIG_VCHIQ_CDEV=y
 CONFIG_VFP=y
 CONFIG_VFPv3=y
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2_I2C=y
 CONFIG_VT=y
 CONFIG_VT_CONSOLE=y
 CONFIG_VT_CONSOLE_SLEEP=y
diff --git a/target/linux/bcm27xx/bcm2710/config-6.1 b/target/linux/bcm27xx/bcm2710/config-6.1
index 50b3f87d7dff68..f29d8483f827b1 100644
--- a/target/linux/bcm27xx/bcm2710/config-6.1
+++ b/target/linux/bcm27xx/bcm2710/config-6.1
@@ -291,6 +291,12 @@ CONFIG_MAILBOX=y
 CONFIG_MDIO_BUS=y
 CONFIG_MDIO_DEVICE=y
 CONFIG_MDIO_DEVRES=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_CONTROLLER=y
+CONFIG_MEDIA_PLATFORM_DRIVERS=y
+CONFIG_MEDIA_PLATFORM_SUPPORT=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_SUPPORT_FILTER=y
 CONFIG_MEMFD_CREATE=y
 CONFIG_MEMORY_ISOLATION=y
 CONFIG_MFD_CORE=y
@@ -458,6 +464,8 @@ CONFIG_USB_SUPPORT=y
 CONFIG_USB_UAS=y
 CONFIG_USB_USBNET=y
 CONFIG_VCHIQ_CDEV=y
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2_I2C=y
 CONFIG_VMAP_STACK=y
 CONFIG_VT=y
 CONFIG_VT_CONSOLE=y
diff --git a/target/linux/bcm27xx/bcm2711/config-6.1 b/target/linux/bcm27xx/bcm2711/config-6.1
index b9022fe958677d..2feb6e9aeaaad9 100644
--- a/target/linux/bcm27xx/bcm2711/config-6.1
+++ b/target/linux/bcm27xx/bcm2711/config-6.1
@@ -293,6 +293,12 @@ CONFIG_MDIO_BCM_UNIMAC=y
 CONFIG_MDIO_BUS=y
 CONFIG_MDIO_DEVICE=y
 CONFIG_MDIO_DEVRES=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_CONTROLLER=y
+CONFIG_MEDIA_PLATFORM_DRIVERS=y
+CONFIG_MEDIA_PLATFORM_SUPPORT=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_SUPPORT_FILTER=y
 CONFIG_MEMFD_CREATE=y
 CONFIG_MEMORY_ISOLATION=y
 CONFIG_MFD_CORE=y
@@ -467,6 +473,8 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_PCI=y
 CONFIG_USB_XHCI_PLATFORM=y
 CONFIG_VCHIQ_CDEV=y
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2_I2C=y
 CONFIG_VMAP_STACK=y
 CONFIG_VT=y
 CONFIG_VT_CONSOLE=y
diff --git a/target/linux/bcm27xx/bcm2712/config-6.1 b/target/linux/bcm27xx/bcm2712/config-6.1
index ed2cc0ebe4fc05..ddd29f78fb4972 100644
--- a/target/linux/bcm27xx/bcm2712/config-6.1
+++ b/target/linux/bcm27xx/bcm2712/config-6.1
@@ -366,6 +366,12 @@ CONFIG_MDIO_BCM_UNIMAC=y
 CONFIG_MDIO_BUS=y
 CONFIG_MDIO_DEVICE=y
 CONFIG_MDIO_DEVRES=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_CONTROLLER=y
+CONFIG_MEDIA_PLATFORM_DRIVERS=y
+CONFIG_MEDIA_PLATFORM_SUPPORT=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_SUPPORT_FILTER=y
 CONFIG_MEMFD_CREATE=y
 CONFIG_MEMORY=y
 CONFIG_MEMORY_ISOLATION=y
@@ -426,7 +432,6 @@ CONFIG_PADATA=y
 CONFIG_PAGE_POOL=y
 CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
 CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
 CONFIG_PARTITION_PERCPU=y
 CONFIG_PCI=y
 CONFIG_PCIEAER=y
@@ -434,8 +439,8 @@ CONFIG_PCIEAER_INJECT=y
 CONFIG_PCIEASPM=y
 # CONFIG_PCIEASPM_DEFAULT is not set
 # CONFIG_PCIEASPM_PERFORMANCE is not set
-# CONFIG_PCIEASPM_POWERSAVE is not set
-CONFIG_PCIEASPM_POWER_SUPERSAVE=y
+CONFIG_PCIEASPM_POWERSAVE=y
+# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
 CONFIG_PCIEPORTBUS=y
 CONFIG_PCIE_BRCMSTB=y
 CONFIG_PCIE_DPC=y
@@ -593,6 +598,8 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_PCI=y
 CONFIG_USB_XHCI_PLATFORM=y
 CONFIG_VCHIQ_CDEV=y
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2_I2C=y
 CONFIG_VMAP_STACK=y
 CONFIG_VT=y
 CONFIG_VT_CONSOLE=y
diff --git a/target/linux/bcm27xx/image/Makefile b/target/linux/bcm27xx/image/Makefile
index e5c2d154994a32..12ac0012a49169 100644
--- a/target/linux/bcm27xx/image/Makefile
+++ b/target/linux/bcm27xx/image/Makefile
@@ -182,8 +182,8 @@ define Device/rpi-5
 	brcmfmac-nvram-43455-sdio \
 	kmod-brcmfmac wpad-basic-mbedtls \
 	kmod-hwmon-pwmfan kmod-thermal
-  IMAGE/sysupgrade.img.gz := boot-common | boot-2711 | sdcard-img | gzip | append-metadata
-  IMAGE/factory.img.gz := boot-common | boot-2711 | sdcard-img | gzip
+  IMAGE/sysupgrade.img.gz := boot-common | sdcard-img | gzip | append-metadata
+  IMAGE/factory.img.gz := boot-common | sdcard-img | gzip
 endef
 ifeq ($(SUBTARGET),bcm2712)
   TARGET_DEVICES += rpi-5
diff --git a/target/linux/bcm27xx/image/gen_rpi_sdcard_img.sh b/target/linux/bcm27xx/image/gen_rpi_sdcard_img.sh
index 5e8fb2769c41ee..488a3517c735ae 100755
--- a/target/linux/bcm27xx/image/gen_rpi_sdcard_img.sh
+++ b/target/linux/bcm27xx/image/gen_rpi_sdcard_img.sh
@@ -1,10 +1,11 @@
 #!/bin/sh
 
-set -x
-[ $# -eq 5 ] || {
+set -e -x
+
+if [ $# -ne 5 ]; then
     echo "SYNTAX: $0 <file> <bootfs image> <rootfs image> <bootfs size> <rootfs size>"
     exit 1
-}
+fi
 
 OUTPUT="$1"
 BOOTFS="$2"
@@ -12,18 +13,16 @@ ROOTFS="$3"
 BOOTFSSIZE="$4"
 ROOTFSSIZE="$5"
 
+align=4096
 head=4
+kernel_type=c
+rootfs_type=83
 sect=63
 
-set $(ptgen -o $OUTPUT -h $head -s $sect -l 4096 -t c -p ${BOOTFSSIZE}M -t 83 -p ${ROOTFSSIZE}M)
+set $(ptgen -o $OUTPUT -h $head -s $sect -l $align -t $kernel_type -p ${BOOTFSSIZE}M -t $rootfs_type -p ${ROOTFSSIZE}M)
 
 BOOTOFFSET="$(($1 / 512))"
-BOOTSIZE="$(($2 / 512))"
 ROOTFSOFFSET="$(($3 / 512))"
-ROOTFSSIZE="$(($4 / 512))"
 
 dd bs=512 if="$BOOTFS" of="$OUTPUT" seek="$BOOTOFFSET" conv=notrunc
 dd bs=512 if="$ROOTFS" of="$OUTPUT" seek="$ROOTFSOFFSET" conv=notrunc
-
-
-
diff --git a/target/linux/bcm27xx/modules/video.mk b/target/linux/bcm27xx/modules/video.mk
index 86fc44c0a4fa9c..c9b9555b04a2cd 100644
--- a/target/linux/bcm27xx/modules/video.mk
+++ b/target/linux/bcm27xx/modules/video.mk
@@ -5,18 +5,10 @@
 define KernelPackage/camera-bcm2835
   TITLE:=BCM2835 Camera
   KCONFIG:= \
-    CONFIG_VIDEO_BCM2835 \
-    CONFIG_VIDEO_BCM2835_MMAL \
-    CONFIG_VIDEO_ARDUCAM_64MP=n \
-    CONFIG_VIDEO_ARDUCAM_PIVARIETY=n \
-    CONFIG_VIDEO_BCM2835_UNICAM=n \
-    CONFIG_VIDEO_IMX296=n \
-    CONFIG_VIDEO_IMX519=n \
-    CONFIG_VIDEO_IMX708=n \
-    CONFIG_VIDEO_ISP_BCM2835=n
+    CONFIG_VIDEO_BCM2835
   FILES:= \
     $(LINUX_DIR)/drivers/staging/vc04_services/bcm2835-camera/bcm2835-v4l2.ko
-  AUTOLOAD:=$(call AutoLoad,65,bcm2835-v4l2)
+  AUTOLOAD:=$(call AutoLoad,66,bcm2835-v4l2)
   $(call AddDepends/video,@TARGET_bcm27xx +kmod-vchiq-mmal-bcm2835 +kmod-video-videobuf2)
 endef
 
@@ -28,6 +20,24 @@ endef
 $(eval $(call KernelPackage,camera-bcm2835))
 
 
+define KernelPackage/codec-bcm2835
+  TITLE:=BCM2835 Video Codec
+  KCONFIG:= \
+    CONFIG_VIDEO_CODEC_BCM2835
+  FILES:= \
+    $(LINUX_DIR)/drivers/staging/vc04_services/bcm2835-codec/bcm2835-codec.ko
+  AUTOLOAD:=$(call AutoLoad,67,bcm2835-codec)
+  $(call AddDepends/video,@TARGET_bcm27xx +kmod-vchiq-mmal-bcm2835 +kmod-video-dma +kmod-video-mem2mem)
+endef
+
+define KernelPackage/codec-bcm2835/description
+  V4L2 video codecs for Broadcom BCM2835 SoC.
+  This operates over the VCHIQ interface to a service running on VideoCore.
+endef
+
+$(eval $(call KernelPackage,codec-bcm2835))
+
+
 define KernelPackage/drm-vc4
   SUBMENU:=$(VIDEO_MENU)
   TITLE:=Broadcom VC4 Graphics
@@ -37,10 +47,7 @@ define KernelPackage/drm-vc4
     +kmod-sound-soc-core
   KCONFIG:= \
     CONFIG_DRM_VC4 \
-    CONFIG_DRM_VC4_HDMI_CEC=y \
-    CONFIG_DRM_GUD=n \
-    CONFIG_DRM_V3D=n \
-    CONFIG_DRM_TVE200=n
+    CONFIG_DRM_VC4_HDMI_CEC=y
   FILES:= \
     $(LINUX_DIR)/drivers/gpu/drm/display/drm_display_helper.ko \
     $(LINUX_DIR)/drivers/gpu/drm/drm_dma_helper.ko \
@@ -58,6 +65,24 @@ endef
 $(eval $(call KernelPackage,drm-vc4))
 
 
+define KernelPackage/isp-bcm2835
+  TITLE:=BCM2835 ISP
+  KCONFIG:= \
+    CONFIG_VIDEO_ISP_BCM2835
+  FILES:= \
+    $(LINUX_DIR)/drivers/staging/vc04_services/bcm2835-isp/bcm2835-isp.ko
+  AUTOLOAD:=$(call AutoLoad,67,bcm2835-isp)
+  $(call AddDepends/video,@TARGET_bcm27xx +kmod-vchiq-mmal-bcm2835 +kmod-video-dma)
+endef
+
+define KernelPackage/isp-bcm2835/description
+  V4L2 driver for the Broadcom BCM2835 ISP hardware.
+  This operates over the VCHIQ interface to a service running on VideoCore.
+endef
+
+$(eval $(call KernelPackage,isp-bcm2835))
+
+
 define KernelPackage/vc-sm-cma
   TITLE:=VideoCore Shared Memory (CMA) driver
   KCONFIG:= \
@@ -78,8 +103,7 @@ $(eval $(call KernelPackage,vc-sm-cma))
 define KernelPackage/vchiq-mmal-bcm2835
   TITLE:=BCM2835 MMAL VCHIQ service
   KCONFIG:= \
-    CONFIG_BCM2835_VCHIQ_MMAL \
-    CONFIG_VIDEO_CODEC_BCM2835=n
+    CONFIG_BCM2835_VCHIQ_MMAL
   FILES:= \
     $(LINUX_DIR)/drivers/staging/vc04_services/vchiq-mmal/bcm2835-mmal-vchiq.ko
   $(call AddDepends/video,@TARGET_bcm27xx +kmod-vc-sm-cma)
diff --git a/target/linux/bcm27xx/patches-6.1/950-0042-drm-Add-chroma-siting-properties.patch b/target/linux/bcm27xx/patches-6.1/950-0042-drm-Add-chroma-siting-properties.patch
index 7ae221e8a905f8..4bfb85449ab1a9 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0042-drm-Add-chroma-siting-properties.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0042-drm-Add-chroma-siting-properties.patch
@@ -106,7 +106,7 @@ Signed-off-by: Dom Cobley <popcornmix@gmail.com>
   * @tests: bitmask of tests to run
 --- a/include/drm/drm_color_mgmt.h
 +++ b/include/drm/drm_color_mgmt.h
-@@ -93,6 +93,9 @@ int drm_plane_create_color_properties(st
+@@ -94,6 +94,9 @@ int drm_plane_create_color_properties(st
  				      enum drm_color_encoding default_encoding,
  				      enum drm_color_range default_range);
  
diff --git a/target/linux/bcm27xx/patches-6.1/950-0092-watchdog-bcm2835-Support-setting-reboot-partition.patch b/target/linux/bcm27xx/patches-6.1/950-0092-watchdog-bcm2835-Support-setting-reboot-partition.patch
index b1ba4ae6b89951..1fa6d6d75a8242 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0092-watchdog-bcm2835-Support-setting-reboot-partition.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0092-watchdog-bcm2835-Support-setting-reboot-partition.patch
@@ -36,7 +36,7 @@ Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
  
  #define SECS_TO_WDOG_TICKS(x) ((x) << 16)
  #define WDOG_TICKS_TO_SECS(x) ((x) >> 16)
-@@ -97,9 +91,24 @@ static unsigned int bcm2835_wdt_get_time
+@@ -98,9 +92,24 @@ static unsigned int bcm2835_wdt_get_time
  	return WDOG_TICKS_TO_SECS(ret & PM_WDOG_TIME_SET);
  }
  
@@ -63,7 +63,7 @@ Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
  
  	/* use a timeout of 10 ticks (~150us) */
  	writel_relaxed(10 | PM_PASSWORD, wdt->base + PM_WDOG);
-@@ -117,7 +126,13 @@ static int bcm2835_restart(struct watchd
+@@ -118,7 +127,13 @@ static int bcm2835_restart(struct watchd
  {
  	struct bcm2835_wdt *wdt = watchdog_get_drvdata(wdog);
  
@@ -78,7 +78,7 @@ Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
  
  	return 0;
  }
-@@ -152,19 +167,9 @@ static struct watchdog_device bcm2835_wd
+@@ -153,19 +168,9 @@ static struct watchdog_device bcm2835_wd
  static void bcm2835_power_off(void)
  {
  	struct bcm2835_wdt *wdt = bcm2835_power_off_wdt;
diff --git a/target/linux/bcm27xx/patches-6.1/950-0106-Add-dwc_otg-driver.patch b/target/linux/bcm27xx/patches-6.1/950-0106-Add-dwc_otg-driver.patch
index 635e864f99b5c6..f8ab3b04a103f4 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0106-Add-dwc_otg-driver.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0106-Add-dwc_otg-driver.patch
@@ -1185,7 +1185,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  }
 --- a/drivers/usb/core/hub.c
 +++ b/drivers/usb/core/hub.c
-@@ -5655,7 +5655,7 @@ static void port_event(struct usb_hub *h
+@@ -5677,7 +5677,7 @@ static void port_event(struct usb_hub *h
  		port_dev->over_current_count++;
  		port_over_current_notify(port_dev);
  
diff --git a/target/linux/bcm27xx/patches-6.1/950-0111-MMC-added-alternative-MMC-driver.patch b/target/linux/bcm27xx/patches-6.1/950-0111-MMC-added-alternative-MMC-driver.patch
index 09402fbc351d41..a89940dacb6f77 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0111-MMC-added-alternative-MMC-driver.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0111-MMC-added-alternative-MMC-driver.patch
@@ -266,7 +266,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com>
  static inline int mmc_blk_part_switch(struct mmc_card *card,
  				      unsigned int part_type);
  static void mmc_blk_rw_rq_prep(struct mmc_queue_req *mqrq,
-@@ -3000,6 +3007,8 @@ static int mmc_blk_probe(struct mmc_card
+@@ -3050,6 +3057,8 @@ static int mmc_blk_probe(struct mmc_card
  {
  	struct mmc_blk_data *md;
  	int ret = 0;
@@ -275,7 +275,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com>
  
  	/*
  	 * Check that the card supports the command class(es) we need.
-@@ -3007,7 +3016,16 @@ static int mmc_blk_probe(struct mmc_card
+@@ -3057,7 +3066,16 @@ static int mmc_blk_probe(struct mmc_card
  	if (!(card->csd.cmdclass & CCC_BLOCK_READ))
  		return -ENODEV;
  
@@ -293,7 +293,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com>
  
  	card->complete_wq = alloc_workqueue("mmc_complete",
  					WQ_MEM_RECLAIM | WQ_HIGHPRI, 0);
-@@ -3022,6 +3040,17 @@ static int mmc_blk_probe(struct mmc_card
+@@ -3072,6 +3090,17 @@ static int mmc_blk_probe(struct mmc_card
  		goto out_free;
  	}
  
diff --git a/target/linux/bcm27xx/patches-6.1/950-0124-Add-support-for-all-the-downstream-rpi-sound-card-dr.patch b/target/linux/bcm27xx/patches-6.1/950-0124-Add-support-for-all-the-downstream-rpi-sound-card-dr.patch
index c5e90fc8601b99..3b5bfaa7e21841 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0124-Add-support-for-all-the-downstream-rpi-sound-card-dr.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0124-Add-support-for-all-the-downstream-rpi-sound-card-dr.patch
@@ -17615,12 +17615,12 @@ Signed-off-by: Ashish Vara <ashishhvara@gmail.com>
  	 * For devices with more than one control interface, we assume the
 --- a/sound/usb/quirks.c
 +++ b/sound/usb/quirks.c
-@@ -2175,6 +2175,8 @@ static const struct usb_audio_quirk_flag
+@@ -2087,6 +2087,8 @@ static const struct usb_audio_quirk_flag
  		   QUIRK_FLAG_FIXED_RATE),
  	DEVICE_FLG(0x0ecb, 0x2069, /* JBL Quantum810 Wireless */
  		   QUIRK_FLAG_FIXED_RATE),
 +	DEVICE_FLG(0x09da, 0x2695, /* A4Tech FHD 1080p webcam */
 +		   QUIRK_FLAG_DISABLE_AUTOSUSPEND | QUIRK_FLAG_GET_SAMPLE_RATE),
- 	DEVICE_FLG(0x1bcf, 0x2283, /* NexiGo N930AF FHD Webcam */
- 		   QUIRK_FLAG_GET_SAMPLE_RATE),
- 
+ 	DEVICE_FLG(0x0fd9, 0x0008, /* Hauppauge HVR-950Q */
+ 		   QUIRK_FLAG_SHARE_MEDIA_DEVICE | QUIRK_FLAG_ALIGN_TRANSFER),
+ 	DEVICE_FLG(0x1224, 0x2a25, /* Jieli Technology USB PHY 2.0 */
diff --git a/target/linux/bcm27xx/patches-6.1/950-0195-media-i2c-imx477-Support-for-the-Sony-IMX477-sensor.patch b/target/linux/bcm27xx/patches-6.1/950-0195-media-i2c-imx477-Support-for-the-Sony-IMX477-sensor.patch
index 89d7b4eea98ac3..102b1e230947f5 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0195-media-i2c-imx477-Support-for-the-Sony-IMX477-sensor.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0195-media-i2c-imx477-Support-for-the-Sony-IMX477-sensor.patch
@@ -343,7 +343,7 @@ Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
 +...
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
-@@ -19281,6 +19281,14 @@ T:	git git://linuxtv.org/media_tree.git
+@@ -19283,6 +19283,14 @@ T:	git git://linuxtv.org/media_tree.git
  F:	Documentation/devicetree/bindings/media/i2c/sony,imx412.yaml
  F:	drivers/media/i2c/imx412.c
  
diff --git a/target/linux/bcm27xx/patches-6.1/950-0196-media-i2c-imx519-Support-for-the-Sony-IMX519-sensor.patch b/target/linux/bcm27xx/patches-6.1/950-0196-media-i2c-imx519-Support-for-the-Sony-IMX519-sensor.patch
index a7cf1bb1f24787..bae8b88490f39f 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0196-media-i2c-imx519-Support-for-the-Sony-IMX519-sensor.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0196-media-i2c-imx519-Support-for-the-Sony-IMX519-sensor.patch
@@ -177,7 +177,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com>
 +...
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
-@@ -19289,6 +19289,14 @@ T:	git git://linuxtv.org/media_tree.git
+@@ -19291,6 +19291,14 @@ T:	git git://linuxtv.org/media_tree.git
  F:	Documentation/devicetree/bindings/media/i2c/imx477.yaml
  F:	drivers/media/i2c/imx477.c
  
diff --git a/target/linux/bcm27xx/patches-6.1/950-0197-Documentation-devicetree-Add-documentation-for-imx37.patch b/target/linux/bcm27xx/patches-6.1/950-0197-Documentation-devicetree-Add-documentation-for-imx37.patch
index 03628b3e9fcf42..2a42b1feac12df 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0197-Documentation-devicetree-Add-documentation-for-imx37.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0197-Documentation-devicetree-Add-documentation-for-imx37.patch
@@ -132,7 +132,7 @@ Signed-off-by: David Plowman <david.plowman@raspberrypi.com>
 +...
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
-@@ -19286,6 +19286,7 @@ M:	Raspberry Pi Kernel Maintenance <kern
+@@ -19288,6 +19288,7 @@ M:	Raspberry Pi Kernel Maintenance <kern
  L:	linux-media@vger.kernel.org
  S:	Maintained
  T:	git git://linuxtv.org/media_tree.git
diff --git a/target/linux/bcm27xx/patches-6.1/950-0227-spi-Force-CS_HIGH-if-GPIO-descriptors-are-used.patch b/target/linux/bcm27xx/patches-6.1/950-0227-spi-Force-CS_HIGH-if-GPIO-descriptors-are-used.patch
index 974a516829b379..ef96ffe86e132d 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0227-spi-Force-CS_HIGH-if-GPIO-descriptors-are-used.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0227-spi-Force-CS_HIGH-if-GPIO-descriptors-are-used.patch
@@ -32,7 +32,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com>
 
 --- a/drivers/spi/spi.c
 +++ b/drivers/spi/spi.c
-@@ -3675,6 +3675,7 @@ static int spi_set_cs_timing(struct spi_
+@@ -3679,6 +3679,7 @@ static int spi_set_cs_timing(struct spi_
   */
  int spi_setup(struct spi_device *spi)
  {
@@ -40,7 +40,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com>
  	unsigned	bad_bits, ugly_bits;
  	int		status = 0;
  
-@@ -3695,6 +3696,14 @@ int spi_setup(struct spi_device *spi)
+@@ -3699,6 +3700,14 @@ int spi_setup(struct spi_device *spi)
  		(SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL |
  		 SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL)))
  		return -EINVAL;
diff --git a/target/linux/bcm27xx/patches-6.1/950-0249-serial-8250-bcm2835aux-defer-if-clock-is-zero.patch b/target/linux/bcm27xx/patches-6.1/950-0249-serial-8250-bcm2835aux-defer-if-clock-is-zero.patch
index 50131095667069..656defb3c7a35f 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0249-serial-8250-bcm2835aux-defer-if-clock-is-zero.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0249-serial-8250-bcm2835aux-defer-if-clock-is-zero.patch
@@ -12,7 +12,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com>
 
 --- a/drivers/tty/serial/8250/8250_bcm2835aux.c
 +++ b/drivers/tty/serial/8250/8250_bcm2835aux.c
-@@ -180,6 +180,13 @@ static int bcm2835aux_serial_probe(struc
+@@ -182,6 +182,13 @@ static int bcm2835aux_serial_probe(struc
  	 */
  	up.port.uartclk = uartclk * 2;
  
diff --git a/target/linux/bcm27xx/patches-6.1/950-0284-watchdog-bcm2835-Ignore-params-after-the-partition-n.patch b/target/linux/bcm27xx/patches-6.1/950-0284-watchdog-bcm2835-Ignore-params-after-the-partition-n.patch
index bf3ba2153e4d78..a7614795dfbe62 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0284-watchdog-bcm2835-Ignore-params-after-the-partition-n.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0284-watchdog-bcm2835-Ignore-params-after-the-partition-n.patch
@@ -12,7 +12,7 @@ which are only relevant to other reboot notifiers.
 
 --- a/drivers/watchdog/bcm2835_wdt.c
 +++ b/drivers/watchdog/bcm2835_wdt.c
-@@ -126,10 +126,12 @@ static int bcm2835_restart(struct watchd
+@@ -127,10 +127,12 @@ static int bcm2835_restart(struct watchd
  {
  	struct bcm2835_wdt *wdt = watchdog_get_drvdata(wdog);
  
diff --git a/target/linux/bcm27xx/patches-6.1/950-0286-phy-broadcom-split-out-the-BCM54213PE-from-the-BCM54.patch b/target/linux/bcm27xx/patches-6.1/950-0286-phy-broadcom-split-out-the-BCM54213PE-from-the-BCM54.patch
index ec4cd0993e311a..55c881286e1c02 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0286-phy-broadcom-split-out-the-BCM54213PE-from-the-BCM54.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0286-phy-broadcom-split-out-the-BCM54213PE-from-the-BCM54.patch
@@ -26,7 +26,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.org>
  		return;
  
  	val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR3);
-@@ -905,7 +906,7 @@ static struct phy_driver broadcom_driver
+@@ -906,7 +907,7 @@ static struct phy_driver broadcom_driver
  	.link_change_notify	= bcm54xx_link_change_notify,
  }, {
  	.phy_id		= PHY_ID_BCM54210E,
@@ -35,7 +35,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.org>
  	.name		= "Broadcom BCM54210E",
  	/* PHY_GBIT_FEATURES */
  	.get_sset_count	= bcm_phy_get_sset_count,
-@@ -919,6 +920,13 @@ static struct phy_driver broadcom_driver
+@@ -920,6 +921,13 @@ static struct phy_driver broadcom_driver
  	.suspend	= bcm54xx_suspend,
  	.resume		= bcm54xx_resume,
  }, {
@@ -49,7 +49,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.org>
  	.phy_id		= PHY_ID_BCM5461,
  	.phy_id_mask	= 0xfffffff0,
  	.name		= "Broadcom BCM5461",
-@@ -1155,7 +1163,8 @@ module_phy_driver(broadcom_drivers);
+@@ -1156,7 +1164,8 @@ module_phy_driver(broadcom_drivers);
  static struct mdio_device_id __maybe_unused broadcom_tbl[] = {
  	{ PHY_ID_BCM5411, 0xfffffff0 },
  	{ PHY_ID_BCM5421, 0xfffffff0 },
diff --git a/target/linux/bcm27xx/patches-6.1/950-0332-drm-panel-simple-Add-a-timing-for-the-Raspberry-Pi-7.patch b/target/linux/bcm27xx/patches-6.1/950-0332-drm-panel-simple-Add-a-timing-for-the-Raspberry-Pi-7.patch
index 3b663351e2f5eb..d0eecb7ee875ac 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0332-drm-panel-simple-Add-a-timing-for-the-Raspberry-Pi-7.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0332-drm-panel-simple-Add-a-timing-for-the-Raspberry-Pi-7.patch
@@ -47,7 +47,7 @@ Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
  static const struct display_timing rocktech_rk070er9427_timing = {
  	.pixelclock = { 26400000, 33300000, 46800000 },
  	.hactive = { 800, 800, 800 },
-@@ -4224,6 +4249,9 @@ static const struct of_device_id platfor
+@@ -4226,6 +4251,9 @@ static const struct of_device_id platfor
  		.compatible = "qishenglong,gopher2b-lcd",
  		.data = &qishenglong_gopher2b_lcd,
  	}, {
diff --git a/target/linux/bcm27xx/patches-6.1/950-0383-drm-panel-simple-add-Geekworm-MZP280-Panel.patch b/target/linux/bcm27xx/patches-6.1/950-0383-drm-panel-simple-add-Geekworm-MZP280-Panel.patch
index aa446c3346d880..fa850a4fd9aee3 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0383-drm-panel-simple-add-Geekworm-MZP280-Panel.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0383-drm-panel-simple-add-Geekworm-MZP280-Panel.patch
@@ -46,7 +46,7 @@ Acked-by: Maxime Ripard <maxime@cerno.tech>
  static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
  	.clock = 9000,
  	.hdisplay = 480,
-@@ -4108,6 +4134,9 @@ static const struct of_device_id platfor
+@@ -4110,6 +4136,9 @@ static const struct of_device_id platfor
  		.compatible = "friendlyarm,hd702e",
  		.data = &friendlyarm_hd702e,
  	}, {
diff --git a/target/linux/bcm27xx/patches-6.1/950-0418-mmc-block-Don-t-do-single-sector-reads-during-recove.patch b/target/linux/bcm27xx/patches-6.1/950-0418-mmc-block-Don-t-do-single-sector-reads-during-recove.patch
index 0335f0019824fa..8fa58f83270317 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0418-mmc-block-Don-t-do-single-sector-reads-during-recove.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0418-mmc-block-Don-t-do-single-sector-reads-during-recove.patch
@@ -23,7 +23,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
 
 --- a/drivers/mmc/core/block.c
 +++ b/drivers/mmc/core/block.c
-@@ -1930,7 +1930,7 @@ static void mmc_blk_mq_rw_recovery(struc
+@@ -1970,7 +1970,7 @@ static void mmc_blk_mq_rw_recovery(struc
  		return;
  	}
  
diff --git a/target/linux/bcm27xx/patches-6.1/950-0427-Populate-phy-driver-block-for-BCM54213PE.patch b/target/linux/bcm27xx/patches-6.1/950-0427-Populate-phy-driver-block-for-BCM54213PE.patch
index 18e654071c32c1..cdfc996abf5fd3 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0427-Populate-phy-driver-block-for-BCM54213PE.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0427-Populate-phy-driver-block-for-BCM54213PE.patch
@@ -16,7 +16,7 @@ Signed-off-by: Jonathan Lemon <jonathan.lemon@gmail.com>
 
 --- a/drivers/net/phy/broadcom.c
 +++ b/drivers/net/phy/broadcom.c
-@@ -932,8 +932,14 @@ static struct phy_driver broadcom_driver
+@@ -933,8 +933,14 @@ static struct phy_driver broadcom_driver
  	.phy_id_mask	= 0xffffffff,
  	.name		= "Broadcom BCM54213PE",
  	/* PHY_GBIT_FEATURES */
diff --git a/target/linux/bcm27xx/patches-6.1/950-0521-drm-panel-simple-Add-Innolux-AT056tN53V1-5.6-VGA.patch b/target/linux/bcm27xx/patches-6.1/950-0521-drm-panel-simple-Add-Innolux-AT056tN53V1-5.6-VGA.patch
index 505121f4cfdb33..93da3ce94d3bcc 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0521-drm-panel-simple-Add-Innolux-AT056tN53V1-5.6-VGA.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0521-drm-panel-simple-Add-Innolux-AT056tN53V1-5.6-VGA.patch
@@ -165,7 +165,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com>
  static const struct drm_display_mode innolux_at070tn92_mode = {
  	.clock = 33333,
  	.hdisplay = 800,
-@@ -4144,6 +4176,9 @@ static const struct of_device_id platfor
+@@ -4146,6 +4178,9 @@ static const struct of_device_id platfor
  		.compatible = "innolux,at043tn24",
  		.data = &innolux_at043tn24,
  	}, {
diff --git a/target/linux/bcm27xx/patches-6.1/950-0528-dtbindings-media-i2c-Add-IMX708-CMOS-sensor-binding.patch b/target/linux/bcm27xx/patches-6.1/950-0528-dtbindings-media-i2c-Add-IMX708-CMOS-sensor-binding.patch
index 6e515001403224..541f19f26152ec 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0528-dtbindings-media-i2c-Add-IMX708-CMOS-sensor-binding.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0528-dtbindings-media-i2c-Add-IMX708-CMOS-sensor-binding.patch
@@ -138,7 +138,7 @@ Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
 +...
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
-@@ -19330,6 +19330,14 @@ T:	git git://linuxtv.org/media_tree.git
+@@ -19332,6 +19332,14 @@ T:	git git://linuxtv.org/media_tree.git
  F:	Documentation/devicetree/bindings/media/i2c/imx519.yaml
  F:	drivers/media/i2c/imx519.c
  
diff --git a/target/linux/bcm27xx/patches-6.1/950-0593-dt-bindings-media-i2c-Add-IMX296-CMOS-sensor-binding.patch b/target/linux/bcm27xx/patches-6.1/950-0593-dt-bindings-media-i2c-Add-IMX296-CMOS-sensor-binding.patch
index 4d6227a3781a47..ece309fc06b501 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0593-dt-bindings-media-i2c-Add-IMX296-CMOS-sensor-binding.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0593-dt-bindings-media-i2c-Add-IMX296-CMOS-sensor-binding.patch
@@ -128,7 +128,7 @@ Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
 +...
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
-@@ -19272,6 +19272,14 @@ T:	git git://linuxtv.org/media_tree.git
+@@ -19274,6 +19274,14 @@ T:	git git://linuxtv.org/media_tree.git
  F:	Documentation/devicetree/bindings/media/i2c/imx290.txt
  F:	drivers/media/i2c/imx290.c
  
diff --git a/target/linux/bcm27xx/patches-6.1/950-0594-media-i2c-IMX296-camera-sensor-driver.patch b/target/linux/bcm27xx/patches-6.1/950-0594-media-i2c-IMX296-camera-sensor-driver.patch
index de983ddb158fa9..9c084cc80f9bfb 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0594-media-i2c-IMX296-camera-sensor-driver.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0594-media-i2c-IMX296-camera-sensor-driver.patch
@@ -23,7 +23,7 @@ Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
 
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
-@@ -19279,6 +19279,7 @@ L:	linux-media@vger.kernel.org
+@@ -19281,6 +19281,7 @@ L:	linux-media@vger.kernel.org
  S:	Maintained
  T:	git git://linuxtv.org/media_tree.git
  F:	Documentation/devicetree/bindings/media/i2c/sony,imx296.yaml
diff --git a/target/linux/bcm27xx/patches-6.1/950-0649-media-dt-bindings-Convert-imx290.txt-to-YAML.patch b/target/linux/bcm27xx/patches-6.1/950-0649-media-dt-bindings-Convert-imx290.txt-to-YAML.patch
index 374069eca56418..db0e89b1666422 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0649-media-dt-bindings-Convert-imx290.txt-to-YAML.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0649-media-dt-bindings-Convert-imx290.txt-to-YAML.patch
@@ -219,7 +219,7 @@ Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
 +...
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
-@@ -19269,7 +19269,7 @@ M:	Manivannan Sadhasivam <manivannan.sad
+@@ -19271,7 +19271,7 @@ M:	Manivannan Sadhasivam <manivannan.sad
  L:	linux-media@vger.kernel.org
  S:	Maintained
  T:	git git://linuxtv.org/media_tree.git
diff --git a/target/linux/bcm27xx/patches-6.1/950-0670-fbdev-Don-t-cancel-deferred-work-if-pagelist-empty.patch b/target/linux/bcm27xx/patches-6.1/950-0670-fbdev-Don-t-cancel-deferred-work-if-pagelist-empty.patch
index 35441799dd536a..31a34fee85f0f8 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0670-fbdev-Don-t-cancel-deferred-work-if-pagelist-empty.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0670-fbdev-Don-t-cancel-deferred-work-if-pagelist-empty.patch
@@ -1,4 +1,4 @@
-From a25b0ea78e73b699e89c6d5589ba43cd0a22f97e Mon Sep 17 00:00:00 2001
+From cf40d2d8c44a659d09d5c20189aab02f20263e81 Mon Sep 17 00:00:00 2001
 From: Phil Elwell <phil@raspberrypi.com>
 Date: Wed, 29 Mar 2023 09:49:36 +0100
 Subject: [PATCH] fbdev: Don't cancel deferred work if pagelist empty
@@ -24,13 +24,13 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com>
 
 --- a/drivers/video/fbdev/core/fb_defio.c
 +++ b/drivers/video/fbdev/core/fb_defio.c
-@@ -321,7 +321,8 @@ static void fb_deferred_io_lastclose(str
+@@ -317,7 +317,8 @@ static void fb_deferred_io_lastclose(str
  	struct page *page;
  	int i;
  
--	cancel_delayed_work_sync(&info->deferred_work);
+-	flush_delayed_work(&info->deferred_work);
 +	if (!list_empty(&info->fbdefio->pagereflist))
-+		cancel_delayed_work_sync(&info->deferred_work);
++		flush_delayed_work(&info->deferred_work);
  
  	/* clear out the mapping that we setup */
  	for (i = 0 ; i < info->fix.smem_len; i += PAGE_SIZE) {
diff --git a/target/linux/bcm27xx/patches-6.1/950-0676-dt-bindings-media-i2c-Replace-IMX708-sensor-binding-.patch b/target/linux/bcm27xx/patches-6.1/950-0676-dt-bindings-media-i2c-Replace-IMX708-sensor-binding-.patch
index 098e6b611d71d4..1e469f6c328a94 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0676-dt-bindings-media-i2c-Replace-IMX708-sensor-binding-.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0676-dt-bindings-media-i2c-Replace-IMX708-sensor-binding-.patch
@@ -271,7 +271,7 @@ Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
 +...
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
-@@ -19344,7 +19344,7 @@ M:	Raspberry Pi Kernel Maintenance <kern
+@@ -19346,7 +19346,7 @@ M:	Raspberry Pi Kernel Maintenance <kern
  L:	linux-media@vger.kernel.org
  S:	Maintained
  T:	git git://linuxtv.org/media_tree.git
diff --git a/target/linux/bcm27xx/patches-6.1/950-0791-serial-sc16is7xx-Read-modem-line-state-at-startup.patch b/target/linux/bcm27xx/patches-6.1/950-0791-serial-sc16is7xx-Read-modem-line-state-at-startup.patch
index c93ebf3e7e6b80..291302306cd445 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0791-serial-sc16is7xx-Read-modem-line-state-at-startup.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0791-serial-sc16is7xx-Read-modem-line-state-at-startup.patch
@@ -16,7 +16,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com>
 
 --- a/drivers/tty/serial/sc16is7xx.c
 +++ b/drivers/tty/serial/sc16is7xx.c
-@@ -1221,6 +1221,9 @@ static int sc16is7xx_startup(struct uart
+@@ -1193,6 +1193,9 @@ static int sc16is7xx_startup(struct uart
  	      SC16IS7XX_IER_MSI_BIT;
  	sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val);
  
@@ -24,5 +24,5 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com>
 +	one->old_mctrl = sc16is7xx_get_hwmctrl(port);
 +
  	/* Enable modem status polling */
- 	spin_lock_irqsave(&port->lock, flags);
+ 	uart_port_lock_irqsave(port, &flags);
  	sc16is7xx_enable_ms(port);
diff --git a/target/linux/bcm27xx/patches-6.1/950-0864-net-macb-Also-set-DMA-coherent-mask.patch b/target/linux/bcm27xx/patches-6.1/950-0864-net-macb-Also-set-DMA-coherent-mask.patch
index 88d92fbb20ad52..7c8c49a3b5dd8c 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0864-net-macb-Also-set-DMA-coherent-mask.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0864-net-macb-Also-set-DMA-coherent-mask.patch
@@ -191,7 +191,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  static void macb_init_buffers(struct macb *bp)
  {
  	struct macb_queue *queue;
-@@ -915,6 +931,7 @@ static int macb_mii_init(struct macb *bp
+@@ -914,6 +930,7 @@ static int macb_mii_init(struct macb *bp
  	bp->mii_bus->name = "MACB_mii_bus";
  	bp->mii_bus->read = &macb_mdio_read;
  	bp->mii_bus->write = &macb_mdio_write;
@@ -199,7 +199,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  	snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
  		 bp->pdev->name, bp->pdev->id);
  	bp->mii_bus->priv = bp;
-@@ -1584,6 +1601,11 @@ static int macb_rx(struct macb_queue *qu
+@@ -1583,6 +1600,11 @@ static int macb_rx(struct macb_queue *qu
  
  		macb_init_rx_ring(queue);
  		queue_writel(queue, RBQP, queue->rx_ring_dma);
@@ -211,7 +211,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  
  		macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
  
-@@ -1884,8 +1906,9 @@ static irqreturn_t macb_interrupt(int ir
+@@ -1883,8 +1905,9 @@ static irqreturn_t macb_interrupt(int ir
  				queue_writel(queue, ISR, MACB_BIT(TCOMP) |
  							 MACB_BIT(TXUBR));
  
@@ -222,7 +222,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  				wmb(); // ensure softirq can see update
  			}
  
-@@ -2332,6 +2355,11 @@ static netdev_tx_t macb_start_xmit(struc
+@@ -2331,6 +2354,11 @@ static netdev_tx_t macb_start_xmit(struc
  	skb_tx_timestamp(skb);
  
  	spin_lock_irq(&bp->lock);
@@ -234,7 +234,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  	macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
  	spin_unlock_irq(&bp->lock);
  
-@@ -2699,6 +2727,37 @@ static void macb_configure_dma(struct ma
+@@ -2698,6 +2726,37 @@ static void macb_configure_dma(struct ma
  	}
  }
  
@@ -272,7 +272,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  static void macb_init_hw(struct macb *bp)
  {
  	u32 config;
-@@ -2727,6 +2786,11 @@ static void macb_init_hw(struct macb *bp
+@@ -2726,6 +2785,11 @@ static void macb_init_hw(struct macb *bp
  	if (bp->caps & MACB_CAPS_JUMBO)
  		bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
  
@@ -284,7 +284,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  	macb_configure_dma(bp);
  }
  
-@@ -3072,6 +3136,52 @@ static void gem_get_ethtool_strings(stru
+@@ -3071,6 +3135,52 @@ static void gem_get_ethtool_strings(stru
  	}
  }
  
@@ -337,7 +337,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  static struct net_device_stats *macb_get_stats(struct net_device *dev)
  {
  	struct macb *bp = netdev_priv(dev);
-@@ -3664,6 +3774,8 @@ static const struct ethtool_ops macb_eth
+@@ -3663,6 +3773,8 @@ static const struct ethtool_ops macb_eth
  };
  
  static const struct ethtool_ops gem_ethtool_ops = {
@@ -346,7 +346,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  	.get_regs_len		= macb_get_regs_len,
  	.get_regs		= macb_get_regs,
  	.get_wol		= macb_get_wol,
-@@ -3673,6 +3785,8 @@ static const struct ethtool_ops gem_etht
+@@ -3672,6 +3784,8 @@ static const struct ethtool_ops gem_etht
  	.get_ethtool_stats	= gem_get_ethtool_stats,
  	.get_strings		= gem_get_ethtool_strings,
  	.get_sset_count		= gem_get_sset_count,
@@ -355,7 +355,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  	.get_link_ksettings     = macb_get_link_ksettings,
  	.set_link_ksettings     = macb_set_link_ksettings,
  	.get_ringparam		= macb_get_ringparam,
-@@ -4940,6 +5054,10 @@ static int macb_probe(struct platform_de
+@@ -4939,6 +5053,10 @@ static int macb_probe(struct platform_de
  
  	bp->usrio = macb_config->usrio;
  
@@ -366,7 +366,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  	spin_lock_init(&bp->lock);
  
  	/* setup capabilities */
-@@ -4995,6 +5113,21 @@ static int macb_probe(struct platform_de
+@@ -4994,6 +5112,21 @@ static int macb_probe(struct platform_de
  	else
  		bp->phy_interface = interface;
  
@@ -388,7 +388,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  	/* IP specific init */
  	err = init(pdev);
  	if (err)
-@@ -5071,6 +5204,19 @@ static int macb_remove(struct platform_d
+@@ -5070,6 +5203,19 @@ static int macb_remove(struct platform_d
  	return 0;
  }
  
@@ -408,7 +408,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  static int __maybe_unused macb_suspend(struct device *dev)
  {
  	struct net_device *netdev = dev_get_drvdata(dev);
-@@ -5285,6 +5431,7 @@ static const struct dev_pm_ops macb_pm_o
+@@ -5284,6 +5430,7 @@ static const struct dev_pm_ops macb_pm_o
  static struct platform_driver macb_driver = {
  	.probe		= macb_probe,
  	.remove		= macb_remove,
diff --git a/target/linux/bcm27xx/patches-6.1/950-0865-usb-dwc3-Set-DMA-and-coherent-masks-early.patch b/target/linux/bcm27xx/patches-6.1/950-0865-usb-dwc3-Set-DMA-and-coherent-masks-early.patch
index f6944e226f0001..e67cb66880eb03 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0865-usb-dwc3-Set-DMA-and-coherent-masks-early.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0865-usb-dwc3-Set-DMA-and-coherent-masks-early.patch
@@ -212,7 +212,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  	},
 --- a/drivers/usb/dwc3/core.c
 +++ b/drivers/usb/dwc3/core.c
-@@ -1216,6 +1216,24 @@ static void dwc3_config_threshold(struct
+@@ -1179,6 +1179,24 @@ static void dwc3_config_threshold(struct
  	}
  }
  
@@ -237,7 +237,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  /**
   * dwc3_core_init - Low-level initialization of DWC3 Core
   * @dwc: Pointer to our controller context structure
-@@ -1308,6 +1326,8 @@ static int dwc3_core_init(struct dwc3 *d
+@@ -1271,6 +1289,8 @@ static int dwc3_core_init(struct dwc3 *d
  
  	dwc3_set_incr_burst_type(dwc);
  
@@ -246,7 +246,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  	usb_phy_set_suspend(dwc->usb2_phy, 0);
  	usb_phy_set_suspend(dwc->usb3_phy, 0);
  	ret = phy_power_on(dwc->usb2_generic_phy);
-@@ -1541,6 +1561,7 @@ static void dwc3_get_properties(struct d
+@@ -1504,6 +1524,7 @@ static void dwc3_get_properties(struct d
  	u8			tx_thr_num_pkt_prd = 0;
  	u8			tx_max_burst_prd = 0;
  	u8			tx_fifo_resize_max_num;
@@ -254,7 +254,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  	const char		*usb_psy_name;
  	int			ret;
  
-@@ -1563,6 +1584,9 @@ static void dwc3_get_properties(struct d
+@@ -1526,6 +1547,9 @@ static void dwc3_get_properties(struct d
  	 */
  	tx_fifo_resize_max_num = 6;
  
@@ -264,7 +264,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  	dwc->maximum_speed = usb_get_maximum_speed(dev);
  	dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev);
  	dwc->dr_mode = usb_get_dr_mode(dev);
-@@ -1678,6 +1702,9 @@ static void dwc3_get_properties(struct d
+@@ -1641,6 +1665,9 @@ static void dwc3_get_properties(struct d
  	dwc->dis_split_quirk = device_property_read_bool(dev,
  				"snps,dis-split-quirk");
  
@@ -274,7 +274,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  	dwc->lpm_nyet_threshold = lpm_nyet_threshold;
  	dwc->tx_de_emphasis = tx_de_emphasis;
  
-@@ -1695,6 +1722,8 @@ static void dwc3_get_properties(struct d
+@@ -1658,6 +1685,8 @@ static void dwc3_get_properties(struct d
  	dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
  	dwc->tx_max_burst_prd = tx_max_burst_prd;
  
@@ -283,7 +283,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  	dwc->imod_interval = 0;
  
  	dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num;
-@@ -1903,6 +1932,12 @@ static int dwc3_probe(struct platform_de
+@@ -1866,6 +1895,12 @@ static int dwc3_probe(struct platform_de
  
  	dwc3_get_properties(dwc);
  
@@ -362,7 +362,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  int dwc3_host_init(struct dwc3 *dwc)
  {
 +	struct platform_device	*pdev = to_platform_device(dwc->dev);
- 	struct property_entry	props[4];
+ 	struct property_entry	props[5];
  	struct platform_device	*xhci;
  	int			ret, irq;
  	int			prop_idx = 0;
diff --git a/target/linux/bcm27xx/patches-6.1/950-0872-mfd-Add-rp1-driver.patch b/target/linux/bcm27xx/patches-6.1/950-0872-mfd-Add-rp1-driver.patch
index dd252cba36a562..c2044753f9e33c 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0872-mfd-Add-rp1-driver.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0872-mfd-Add-rp1-driver.patch
@@ -19,7 +19,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com>
 
 --- a/drivers/mfd/Kconfig
 +++ b/drivers/mfd/Kconfig
-@@ -2252,6 +2252,17 @@ config MFD_INTEL_M10_BMC
+@@ -2253,6 +2253,17 @@ config MFD_INTEL_M10_BMC
  	  additional drivers must be enabled in order to use the functionality
  	  of the device.
  
diff --git a/target/linux/bcm27xx/patches-6.1/950-0918-irqchip-irq-brcmstb-l2-Add-config-for-2711-controlle.patch b/target/linux/bcm27xx/patches-6.1/950-0918-irqchip-irq-brcmstb-l2-Add-config-for-2711-controlle.patch
index 5ea212d4a7b482..039c5fd74f073c 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0918-irqchip-irq-brcmstb-l2-Add-config-for-2711-controlle.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0918-irqchip-irq-brcmstb-l2-Add-config-for-2711-controlle.patch
@@ -52,7 +52,7 @@ Signed-off-by: Dom Cobley <popcornmix@gmail.com>
  /* L2 intc private data structure */
  struct brcmstb_l2_intc_data {
  	struct irq_domain *domain;
-@@ -286,11 +296,18 @@ static int __init brcmstb_l2_lvl_intc_of
+@@ -289,11 +299,18 @@ static int __init brcmstb_l2_lvl_intc_of
  	return brcmstb_l2_intc_of_init(np, parent, &l2_lvl_intc_init);
  }
  
diff --git a/target/linux/bcm27xx/patches-6.1/950-1182-drm-panel-add-panel-dsi.patch b/target/linux/bcm27xx/patches-6.1/950-1182-drm-panel-add-panel-dsi.patch
index d914ab6d040c98..9122d7347607d7 100644
--- a/target/linux/bcm27xx/patches-6.1/950-1182-drm-panel-add-panel-dsi.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-1182-drm-panel-add-panel-dsi.patch
@@ -23,7 +23,7 @@ Signed-off-by: Timon Skerutsch <kernel@diodes-delight.com>
  
  /**
   * struct panel_desc - Describes a simple panel.
-@@ -4660,6 +4661,9 @@ static const struct panel_desc_dsi osd10
+@@ -4662,6 +4663,9 @@ static const struct panel_desc_dsi osd10
  	.lanes = 4,
  };
  
@@ -33,7 +33,7 @@ Signed-off-by: Timon Skerutsch <kernel@diodes-delight.com>
  static const struct of_device_id dsi_of_match[] = {
  	{
  		.compatible = "auo,b080uan01",
-@@ -4683,14 +4687,118 @@ static const struct of_device_id dsi_of_
+@@ -4685,14 +4689,118 @@ static const struct of_device_id dsi_of_
  		.compatible = "osddisplays,osd101t2045-53ts",
  		.data = &osd101t2045_53ts
  	}, {
@@ -152,7 +152,7 @@ Signed-off-by: Timon Skerutsch <kernel@diodes-delight.com>
  	const struct of_device_id *id;
  	int err;
  
-@@ -4698,7 +4806,20 @@ static int panel_simple_dsi_probe(struct
+@@ -4700,7 +4808,20 @@ static int panel_simple_dsi_probe(struct
  	if (!id)
  		return -ENODEV;
  
diff --git a/target/linux/bcm27xx/patches-6.1/950-1194-media-dt-bindings-i2c-Add-Rohm-BU64754-bindings.patch b/target/linux/bcm27xx/patches-6.1/950-1194-media-dt-bindings-i2c-Add-Rohm-BU64754-bindings.patch
index 82eda14173d3b1..5ea162577c8e24 100644
--- a/target/linux/bcm27xx/patches-6.1/950-1194-media-dt-bindings-i2c-Add-Rohm-BU64754-bindings.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-1194-media-dt-bindings-i2c-Add-Rohm-BU64754-bindings.patch
@@ -67,7 +67,7 @@ Signed-off-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com>
 +...
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
-@@ -17895,6 +17895,13 @@ S:	Maintained
+@@ -17897,6 +17897,13 @@ S:	Maintained
  F:	Documentation/devicetree/bindings/iio/light/bh1750.yaml
  F:	drivers/iio/light/bh1750.c
  
diff --git a/target/linux/bcm27xx/patches-6.1/950-1195-media-i2c-Add-driver-for-OmniVision-OV64A40.patch b/target/linux/bcm27xx/patches-6.1/950-1195-media-i2c-Add-driver-for-OmniVision-OV64A40.patch
index 2f3ea4b0725bee..9888ad8ade99a2 100644
--- a/target/linux/bcm27xx/patches-6.1/950-1195-media-i2c-Add-driver-for-OmniVision-OV64A40.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-1195-media-i2c-Add-driver-for-OmniVision-OV64A40.patch
@@ -16,7 +16,7 @@ Signed-off-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com>
 
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
-@@ -15321,6 +15321,14 @@ S:	Maintained
+@@ -15323,6 +15323,14 @@ S:	Maintained
  T:	git git://linuxtv.org/media_tree.git
  F:	drivers/media/i2c/ov5695.c
  
diff --git a/target/linux/bcm53xx/patches-6.1/500-UBI-Detect-EOF-mark-and-erase-all-remaining-blocks.patch b/target/linux/bcm53xx/patches-6.1/500-UBI-Detect-EOF-mark-and-erase-all-remaining-blocks.patch
index 209c57ca0bdbbc..e6140d9a704ba2 100644
--- a/target/linux/bcm53xx/patches-6.1/500-UBI-Detect-EOF-mark-and-erase-all-remaining-blocks.patch
+++ b/target/linux/bcm53xx/patches-6.1/500-UBI-Detect-EOF-mark-and-erase-all-remaining-blocks.patch
@@ -49,7 +49,7 @@ Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
  			return UBI_IO_BAD_HDR_EBADMSG;
 --- a/drivers/mtd/ubi/ubi.h
 +++ b/drivers/mtd/ubi/ubi.h
-@@ -820,6 +820,7 @@ extern struct mutex ubi_devices_mutex;
+@@ -822,6 +822,7 @@ extern struct mutex ubi_devices_mutex;
  extern struct blocking_notifier_head ubi_notifiers;
  
  /* attach.c */
diff --git a/target/linux/bcm63xx/dts/bcm3368-netgear-cvg834g.dts b/target/linux/bcm63xx/dts/bcm3368-netgear-cvg834g.dts
index fb22f769d69a16..998ca6002a8643 100644
--- a/target/linux/bcm63xx/dts/bcm3368-netgear-cvg834g.dts
+++ b/target/linux/bcm63xx/dts/bcm3368-netgear-cvg834g.dts
@@ -1,6 +1,7 @@
 #include "bcm3368.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Netgear CVG834G";
@@ -22,7 +23,8 @@
 		compatible = "gpio-leds";
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio1 5 0>;
 			default-state = "on";
 		};
diff --git a/target/linux/bcm63xx/dts/bcm63167-sercomm-h500-s.dtsi b/target/linux/bcm63xx/dts/bcm63167-sercomm-h500-s.dtsi
index 07665007344673..af633cadebf779 100644
--- a/target/linux/bcm63xx/dts/bcm63167-sercomm-h500-s.dtsi
+++ b/target/linux/bcm63xx/dts/bcm63167-sercomm-h500-s.dtsi
@@ -8,6 +8,7 @@
 #include "bcm63268.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -62,7 +63,8 @@
 
 	led_power_red: power_red {
 		reg = <8>;
-		label = "red:power";
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_RED>;
 	};
 
 	wifi_green {
@@ -97,7 +99,8 @@
 
 	led_power_green: power_green {
 		reg = <17>;
-		label = "green:power";
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_GREEN>;
 		default-state = "on";
 	};
 
diff --git a/target/linux/bcm63xx/dts/bcm63168-comtrend-vr-3032u.dts b/target/linux/bcm63xx/dts/bcm63168-comtrend-vr-3032u.dts
index c2505f86ba7524..6627d67f8c0f68 100644
--- a/target/linux/bcm63xx/dts/bcm63168-comtrend-vr-3032u.dts
+++ b/target/linux/bcm63xx/dts/bcm63168-comtrend-vr-3032u.dts
@@ -3,6 +3,7 @@
 #include "bcm63268.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Comtrend VR-3032u";
@@ -80,13 +81,15 @@
 	led@4 {
 		reg = <4>;
 		active-low;
-		label = "green:usb";
+		function = LED_FUNCTION_USB;
+		color = <LED_COLOR_ID_GREEN>;
 	};
 
 	led@7 {
 		reg = <7>;
 		active-low;
-		label = "green:wps";
+		function = LED_FUNCTION_WPS;
+		color = <LED_COLOR_ID_GREEN>;
 	};
 
 	led@8 {
@@ -140,7 +143,8 @@
 	led_power_green: led@20 {
 		reg = <20>;
 		active-low;
-		label = "green:power";
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_GREEN>;
 		default-state = "on";
 	};
 };
diff --git a/target/linux/bcm63xx/dts/bcm63168-sky-sr102.dts b/target/linux/bcm63xx/dts/bcm63168-sky-sr102.dts
index 47ba15608e61ab..4be787d09316be 100644
--- a/target/linux/bcm63xx/dts/bcm63168-sky-sr102.dts
+++ b/target/linux/bcm63xx/dts/bcm63168-sky-sr102.dts
@@ -1,6 +1,7 @@
 #include "bcm63268.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "SKY SR102";
@@ -40,7 +41,8 @@
 			gpios = <&pinctrl 1 1>;
 		};
 		power_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&pinctrl 2 1>;
 		};
 		wifi_red {
@@ -56,7 +58,8 @@
 			gpios = <&pinctrl 5 0>;
 		};
 		led_power_white: power_white {
-			label = "white:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&pinctrl 6 0>;
 			default-state = "on";
 		};
diff --git a/target/linux/bcm63xx/dts/bcm63169-comtrend-vg-8050.dts b/target/linux/bcm63xx/dts/bcm63169-comtrend-vg-8050.dts
index 5d5ba46e3c777a..373480b0130d1d 100644
--- a/target/linux/bcm63xx/dts/bcm63169-comtrend-vg-8050.dts
+++ b/target/linux/bcm63xx/dts/bcm63169-comtrend-vg-8050.dts
@@ -3,6 +3,7 @@
 #include "bcm63268.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Comtrend VG-8050";
@@ -60,20 +61,23 @@
 	led@3 {
 		reg = <3>;
 		active-low;
-		label = "red:power";
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_RED>;
 	};
 
 	led_power_green: led@6 {
 		reg = <6>;
 		active-low;
-		label = "green:power";
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_GREEN>;
 		default-state = "on";
 	};
 
 	led@7 {
 		reg = <7>;
 		active-low;
-		label = "green:wps";
+		function = LED_FUNCTION_WPS;
+		color = <LED_COLOR_ID_GREEN>;
 	};
 
 	led@8 {
@@ -97,7 +101,8 @@
 	led@14 {
 		reg = <14>;
 		active-low;
-		label = "red:wps";
+		function = LED_FUNCTION_WPS;
+		color = <LED_COLOR_ID_RED>;
 	};
 };
 
diff --git a/target/linux/bcm63xx/dts/bcm6318-comtrend-ar-5315u.dts b/target/linux/bcm63xx/dts/bcm6318-comtrend-ar-5315u.dts
index 8557730c8cd3b5..a3a7d1a3c56d60 100644
--- a/target/linux/bcm63xx/dts/bcm6318-comtrend-ar-5315u.dts
+++ b/target/linux/bcm63xx/dts/bcm6318-comtrend-ar-5315u.dts
@@ -1,6 +1,7 @@
 #include "bcm6318.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Comtrend AR-5315u";
@@ -89,20 +90,23 @@
 	led@0 {
 		reg = <0>;
 		active-low;
-		label = "green:wps";
+		function = LED_FUNCTION_WPS;
+		color = <LED_COLOR_ID_GREEN>;
 	};
 
 	led_power_green: led@1 {
 		reg = <1>;
 		active-low;
-		label = "green:power";
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_GREEN>;
 		default-state = "on";
 	};
 
 	led@2 {
 		reg = <2>;
 		active-low;
-		label = "green:usb";
+		function = LED_FUNCTION_USB;
+		color = <LED_COLOR_ID_GREEN>;
 	};
 
 	led@4 {
@@ -154,7 +158,8 @@
 	led@11 {
 		reg = <11>;
 		active-low;
-		label = "red:power";
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_RED>;
 	};
 };
 
diff --git a/target/linux/bcm63xx/dts/bcm6318-d-link-dsl-275xb-d1.dts b/target/linux/bcm63xx/dts/bcm6318-d-link-dsl-275xb-d1.dts
index acf4332a66ff7d..31d05b96ae6320 100644
--- a/target/linux/bcm63xx/dts/bcm6318-d-link-dsl-275xb-d1.dts
+++ b/target/linux/bcm63xx/dts/bcm6318-d-link-dsl-275xb-d1.dts
@@ -1,6 +1,7 @@
 #include "bcm6318.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "D-Link DSL-2750B/DSL-2751 rev D1";
@@ -50,7 +51,8 @@
 		compatible = "gpio-leds";
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 3 1>;
 			default-state = "on";
 		};
@@ -71,7 +73,8 @@
 		};
 
 		wps_blue {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&pinctrl 16 1>;
 		};
 
@@ -82,7 +85,8 @@
 
 		usb_green {
 			/* not user controllable? */
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 49 1>;
 		};
 	};
diff --git a/target/linux/bcm63xx/dts/bcm6318-sagem-fast-2704n.dts b/target/linux/bcm63xx/dts/bcm6318-sagem-fast-2704n.dts
index 6702ef16564b9c..4d928f21553849 100644
--- a/target/linux/bcm63xx/dts/bcm6318-sagem-fast-2704n.dts
+++ b/target/linux/bcm63xx/dts/bcm6318-sagem-fast-2704n.dts
@@ -1,6 +1,7 @@
 #include "bcm6318.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Sagem F@st 2704N";
@@ -50,7 +51,8 @@
 		compatible = "gpio-leds";
 
 		wps_green {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 2 1>;
 		};
 		lan1_green {
@@ -82,16 +84,19 @@
 			gpios = <&pinctrl 10 1>;
 		};
 		led_power_red: power_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&pinctrl 11 1>;
 		};
 		power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 47 1>;
 			default-state = "on";
 		};
 		usb_green {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 49 1>;
 		};
 	};
diff --git a/target/linux/bcm63xx/dts/bcm6328-adb-a4001n.dts b/target/linux/bcm63xx/dts/bcm6328-adb-a4001n.dts
index 641de68d356d9e..790320a206f055 100644
--- a/target/linux/bcm63xx/dts/bcm6328-adb-a4001n.dts
+++ b/target/linux/bcm63xx/dts/bcm6328-adb-a4001n.dts
@@ -1,6 +1,7 @@
 #include "bcm6328.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "ADB P.DG A4001N";
@@ -47,16 +48,19 @@
 			gpios = <&pinctrl 1 0>;
 		};
 		power_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&pinctrl 4 0>;
 		};
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 8 0>;
 			default-state = "on";
 		};
 		usb_green {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 10 1>;
 		};
 		dsl_green {
diff --git a/target/linux/bcm63xx/dts/bcm6328-adb-a4001n1.dts b/target/linux/bcm63xx/dts/bcm6328-adb-a4001n1.dts
index bd05547bae9966..f23716bd4d7304 100644
--- a/target/linux/bcm63xx/dts/bcm6328-adb-a4001n1.dts
+++ b/target/linux/bcm63xx/dts/bcm6328-adb-a4001n1.dts
@@ -1,6 +1,7 @@
 #include "bcm6328.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "ADB P.DG A4001N1";
@@ -51,7 +52,8 @@
 			gpios = <&pinctrl 3 1>;
 		};
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 4 1>;
 			default-state = "on";
 		};
@@ -68,15 +70,18 @@
 			gpios = <&pinctrl 7 1>;
 		};
 		power_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&pinctrl 8 1>;
 		};
 		wlan_green {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 9 1>;
 		};
 		wlan_red {
-			label = "red:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&pinctrl 10 1>;
 		};
 		inet_green {
diff --git a/target/linux/bcm63xx/dts/bcm6328-adb-pdg-a4001n-a-000-1a1-ax.dts b/target/linux/bcm63xx/dts/bcm6328-adb-pdg-a4001n-a-000-1a1-ax.dts
index f42b970c4670e1..b2f3ddfc401ddf 100644
--- a/target/linux/bcm63xx/dts/bcm6328-adb-pdg-a4001n-a-000-1a1-ax.dts
+++ b/target/linux/bcm63xx/dts/bcm6328-adb-pdg-a4001n-a-000-1a1-ax.dts
@@ -3,6 +3,7 @@
 #include "bcm6328.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "ADB P.DG A4001N A-000-1A1-AX";
@@ -81,7 +82,8 @@
 	led@8 {
 		reg = <8>;
 		active-low;
-		label = "red:power";
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_RED>;
 	};
 
 	led@9 {
@@ -105,7 +107,8 @@
 	led_power_green: led@12 {
 		reg = <12>;
 		active-low;
-		label = "green:power";
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_GREEN>;
 		default-state = "on";
 	};
 };
diff --git a/target/linux/bcm63xx/dts/bcm6328-adb-pdg-a4101n-a-000-1a1-ae.dts b/target/linux/bcm63xx/dts/bcm6328-adb-pdg-a4101n-a-000-1a1-ae.dts
index 7ffff4e223470d..16c9af574716e9 100644
--- a/target/linux/bcm63xx/dts/bcm6328-adb-pdg-a4101n-a-000-1a1-ae.dts
+++ b/target/linux/bcm63xx/dts/bcm6328-adb-pdg-a4101n-a-000-1a1-ae.dts
@@ -3,6 +3,7 @@
 #include "bcm6328.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "ADB P.DG A4101N A-000-1A1-AE";
@@ -72,13 +73,15 @@
 	led@9 {
 		reg = <9>;
 		active-low;
-		label = "green:wps";
+		function = LED_FUNCTION_WPS;
+		color = <LED_COLOR_ID_GREEN>;
 	};
 
 	led@10 {
 		reg = <10>;
 		active-low;
-		label = "green:usb";
+		function = LED_FUNCTION_USB;
+		color = <LED_COLOR_ID_GREEN>;
 	};
 
 	led@11 {
diff --git a/target/linux/bcm63xx/dts/bcm6328-comtrend-ar-5381u.dts b/target/linux/bcm63xx/dts/bcm6328-comtrend-ar-5381u.dts
index 5878e886d2e699..7e196e5e68307f 100644
--- a/target/linux/bcm63xx/dts/bcm6328-comtrend-ar-5381u.dts
+++ b/target/linux/bcm63xx/dts/bcm6328-comtrend-ar-5381u.dts
@@ -1,6 +1,7 @@
 #include "bcm6328.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Comtrend AR-5381u";
@@ -80,7 +81,8 @@
 	led_alarm_red: led@2 {
 		reg = <2>;
 		active-low;
-		label = "red:alarm";
+		function = LED_FUNCTION_ALARM;
+		color = <LED_COLOR_ID_RED>;
 	};
 
 	led@3 {
@@ -92,7 +94,8 @@
 	led_power_green: led@4 {
 		reg = <4>;
 		active-low;
-		label = "green:power";
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_GREEN>;
 		default-state = "on";
 	};
 };
diff --git a/target/linux/bcm63xx/dts/bcm6328-comtrend-ar-5387un.dts b/target/linux/bcm63xx/dts/bcm6328-comtrend-ar-5387un.dts
index a703fd6629853a..a0f5691fb500b7 100644
--- a/target/linux/bcm63xx/dts/bcm6328-comtrend-ar-5387un.dts
+++ b/target/linux/bcm63xx/dts/bcm6328-comtrend-ar-5387un.dts
@@ -1,6 +1,7 @@
 #include "bcm6328.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Comtrend AR-5387un";
@@ -84,7 +85,8 @@
 
 	led@4 {
 		reg = <4>;
-		label = "red:power";
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_RED>;
 	};
 
 	led@7 {
@@ -94,7 +96,8 @@
 
 	led_power_green: led@8 {
 		reg = <8>;
-		label = "green:power";
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_GREEN>;
 		default-state = "on";
 	};
 
diff --git a/target/linux/bcm63xx/dts/bcm6328-d-link-dsl-274xb-f1.dts b/target/linux/bcm63xx/dts/bcm6328-d-link-dsl-274xb-f1.dts
index 660a4d570ce5ba..f320be4aca8060 100644
--- a/target/linux/bcm63xx/dts/bcm6328-d-link-dsl-274xb-f1.dts
+++ b/target/linux/bcm63xx/dts/bcm6328-d-link-dsl-274xb-f1.dts
@@ -1,6 +1,7 @@
 #include "bcm6328.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "D-Link DSL-2740B/DSL-2741B rev F1";
@@ -58,16 +59,19 @@
 			gpios = <&pinctrl 3 1>;
 		};
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 4 1>;
 			default-state = "on";
 		};
 		power_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&pinctrl 8 1>;
 		};
 		wps_blue {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&pinctrl 9 1>;
 		};
 		inet_green {
diff --git a/target/linux/bcm63xx/dts/bcm6328-d-link-dsl-2750u-c1.dts b/target/linux/bcm63xx/dts/bcm6328-d-link-dsl-2750u-c1.dts
index 09152150392a9d..cdbb5c2c5b2a3a 100644
--- a/target/linux/bcm63xx/dts/bcm6328-d-link-dsl-2750u-c1.dts
+++ b/target/linux/bcm63xx/dts/bcm6328-d-link-dsl-2750u-c1.dts
@@ -3,6 +3,7 @@
 #include "bcm6328.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "D-Link DSL-2750U rev C1";
@@ -97,7 +98,8 @@
 	led_power_green: led@4 {
 		reg = <4>;
 		active-low;
-		label = "green:power";
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_GREEN>;
 		default-state = "on";
 	};
 
@@ -110,19 +112,22 @@
 	led@8 {
 		reg = <8>;
 		active-low;
-		label = "red:power";
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_RED>;
 	};
 
 	led@9 {
 		reg = <9>;
 		active-low;
-		label = "green:wps";
+		function = LED_FUNCTION_WPS;
+		color = <LED_COLOR_ID_GREEN>;
 	};
 
 	led@10 {
 		reg = <10>;
 		active-low;
-		label = "green:usb";
+		function = LED_FUNCTION_USB;
+		color = <LED_COLOR_ID_GREEN>;
 	};
 
 	led@11 {
diff --git a/target/linux/bcm63xx/dts/bcm6328-innacomm-w3400v6.dts b/target/linux/bcm63xx/dts/bcm6328-innacomm-w3400v6.dts
index dd8ab129586a7a..afedfe24508b26 100644
--- a/target/linux/bcm63xx/dts/bcm6328-innacomm-w3400v6.dts
+++ b/target/linux/bcm63xx/dts/bcm6328-innacomm-w3400v6.dts
@@ -3,6 +3,7 @@
 #include "bcm6328.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Innacomm W3400V6";
@@ -88,20 +89,23 @@
 	led_power_green: led@4 {
 		reg = <4>;
 		active-low;
-		label = "green:power";
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_GREEN>;
 		default-state = "on";
 	};
 
 	led_power_red: led@5 {
 		reg = <5>;
 		active-low;
-		label = "red:power";
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_RED>;
 	};
 
 	led@11 {
 		reg = <11>;
 		active-low;
-		label = "green:wps";
+		function = LED_FUNCTION_WPS;
+		color = <LED_COLOR_ID_GREEN>;
 	};
 };
 
diff --git a/target/linux/bcm63xx/dts/bcm6328-nucom-r5010un-v2.dts b/target/linux/bcm63xx/dts/bcm6328-nucom-r5010un-v2.dts
index 08f3736a7b5cdc..e71e1436b52d45 100644
--- a/target/linux/bcm63xx/dts/bcm6328-nucom-r5010un-v2.dts
+++ b/target/linux/bcm63xx/dts/bcm6328-nucom-r5010un-v2.dts
@@ -1,6 +1,7 @@
 #include "bcm6328.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "NuCom R5010UN v2";
@@ -55,7 +56,8 @@
 			gpios = <&pinctrl 3 1>;
 		};
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 4 1>;
 			default-state = "on";
 		};
@@ -64,11 +66,13 @@
 			gpios = <&pinctrl 5 1>;
 		};
 		wps_green {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 10 1>;
 		};
 		usb_green {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 11 1>;
 		};
 	};
diff --git a/target/linux/bcm63xx/dts/bcm6328-sagem-fast-2704-v2.dts b/target/linux/bcm63xx/dts/bcm6328-sagem-fast-2704-v2.dts
index ff9b23049bcf4c..06f314ca79da7a 100644
--- a/target/linux/bcm63xx/dts/bcm6328-sagem-fast-2704-v2.dts
+++ b/target/linux/bcm63xx/dts/bcm6328-sagem-fast-2704-v2.dts
@@ -1,6 +1,7 @@
 #include "bcm6328.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Sagem F@st 2704 V2";
@@ -50,7 +51,8 @@
 		compatible = "gpio-leds";
 
 		usb_green {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 1 1>;
 		};
 		inet_red {
@@ -62,16 +64,19 @@
 			gpios = <&pinctrl 3 1>;
 		};
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 4 1>;
 			default-state = "on";
 		};
 		power_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&pinctrl 5 1>;
 		};
 		wps_green {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 10 1>;
 		};
 		inet_green {
diff --git a/target/linux/bcm63xx/dts/bcm6328-sercomm-ad1018-nor.dts b/target/linux/bcm63xx/dts/bcm6328-sercomm-ad1018-nor.dts
index 5a9f52648e295e..1dda9d64f349d2 100644
--- a/target/linux/bcm63xx/dts/bcm6328-sercomm-ad1018-nor.dts
+++ b/target/linux/bcm63xx/dts/bcm6328-sercomm-ad1018-nor.dts
@@ -1,6 +1,7 @@
 #include "bcm6328.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Sercomm AD1018 (SPI flash mod)";
@@ -81,7 +82,8 @@
 	led_power_green: power_green@8 {
 		reg = <8>;
 		active-low;
-		label = "green:power";
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_GREEN>;
 		default-state = "on";
 	};
 
@@ -106,7 +108,8 @@
 	wps_green@13 {
 		reg = <13>;
 		active-low;
-		label = "green:wps";
+		function = LED_FUNCTION_WPS;
+		color = <LED_COLOR_ID_GREEN>;
 	};
 
 	wifi_green@14 {
@@ -118,7 +121,8 @@
 	usb_green@15 {
 		reg = <15>;
 		active-low;
-		label = "green:usb";
+		function = LED_FUNCTION_USB;
+		color = <LED_COLOR_ID_GREEN>;
 	};
 
 	ephy0_spd@17 {
diff --git a/target/linux/bcm63xx/dts/bcm6328-sercomm-ad1018.dts b/target/linux/bcm63xx/dts/bcm6328-sercomm-ad1018.dts
index edb1ce49a68cf2..edd1d8c348a66f 100644
--- a/target/linux/bcm63xx/dts/bcm6328-sercomm-ad1018.dts
+++ b/target/linux/bcm63xx/dts/bcm6328-sercomm-ad1018.dts
@@ -3,6 +3,7 @@
 #include "bcm6328.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Sercomm AD1018";
@@ -76,7 +77,8 @@
 	led_power_green: led@8 {
 		reg = <8>;
 		active-low;
-		label = "green:power";
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_GREEN>;
 		default-state = "on";
 	};
 
@@ -101,7 +103,8 @@
 	led@13 {
 		reg = <13>;
 		active-low;
-		label = "green:wps";
+		function = LED_FUNCTION_WPS;
+		color = <LED_COLOR_ID_GREEN>;
 	};
 
 	led@14 {
@@ -113,7 +116,8 @@
 	led@15 {
 		reg = <15>;
 		active-low;
-		label = "green:usb";
+		function = LED_FUNCTION_USB;
+		color = <LED_COLOR_ID_GREEN>;
 	};
 
 	led@17 {
diff --git a/target/linux/bcm63xx/dts/bcm6328-technicolor-tg582n-telecom-italia.dts b/target/linux/bcm63xx/dts/bcm6328-technicolor-tg582n-telecom-italia.dts
index 0dfa38e474c436..d88855f7a5a48d 100644
--- a/target/linux/bcm63xx/dts/bcm6328-technicolor-tg582n-telecom-italia.dts
+++ b/target/linux/bcm63xx/dts/bcm6328-technicolor-tg582n-telecom-italia.dts
@@ -3,6 +3,7 @@
 #include "bcm6328.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Technicolor TG582n Telecom Italia";
@@ -57,7 +58,8 @@
 	led_power_green: led@4 {
 		reg = <4>;
 		active-low;
-		label = "green:power";
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_GREEN>;
 		default-state = "on";
 	};
 
@@ -76,7 +78,8 @@
 	led@8 {
 		reg = <8>;
 		active-low;
-		label = "red:power";
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_RED>;
 	};
 
 	led@11 {
diff --git a/target/linux/bcm63xx/dts/bcm6328-technicolor-tg582n.dts b/target/linux/bcm63xx/dts/bcm6328-technicolor-tg582n.dts
index 6ec20048cda686..0bd7b72b3c775f 100644
--- a/target/linux/bcm63xx/dts/bcm6328-technicolor-tg582n.dts
+++ b/target/linux/bcm63xx/dts/bcm6328-technicolor-tg582n.dts
@@ -3,6 +3,7 @@
 #include "bcm6328.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Technicolor TG582n";
@@ -76,7 +77,8 @@
 	led_power_green: led@4 {
 		reg = <4>;
 		active-low;
-		label = "green:power";
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_GREEN>;
 		default-state = "on";
 	};
 
@@ -95,19 +97,22 @@
 	led@8 {
 		reg = <8>;
 		active-low;
-		label = "red:power";
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_RED>;
 	};
 
 	led@9 {
 		reg = <9>;
 		active-low;
-		label = "green:wps";
+		function = LED_FUNCTION_WPS;
+		color = <LED_COLOR_ID_GREEN>;
 	};
 
 	led@10 {
 		reg = <10>;
 		active-low;
-		label = "red:wps";
+		function = LED_FUNCTION_WPS;
+		color = <LED_COLOR_ID_RED>;
 	};
 
 	led@11 {
diff --git a/target/linux/bcm63xx/dts/bcm6338-brcm-bcm96338gw.dts b/target/linux/bcm63xx/dts/bcm6338-brcm-bcm96338gw.dts
index 885654ad41d4bf..882e376d5bae49 100644
--- a/target/linux/bcm63xx/dts/bcm6338-brcm-bcm96338gw.dts
+++ b/target/linux/bcm63xx/dts/bcm6338-brcm-bcm96338gw.dts
@@ -1,6 +1,7 @@
 #include "bcm6338.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Broadcom BCM96338GW reference board";
@@ -15,7 +16,8 @@
 		compatible = "gpio-leds";
 
 		power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 0 1>;
 			default-state = "on";
 		};
diff --git a/target/linux/bcm63xx/dts/bcm6338-brcm-bcm96338w.dts b/target/linux/bcm63xx/dts/bcm6338-brcm-bcm96338w.dts
index 3002a9240ba2a8..4165ddc3254718 100644
--- a/target/linux/bcm63xx/dts/bcm6338-brcm-bcm96338w.dts
+++ b/target/linux/bcm63xx/dts/bcm6338-brcm-bcm96338w.dts
@@ -1,6 +1,7 @@
 #include "bcm6338.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Broadcom BCM96338W reference board";
@@ -15,7 +16,8 @@
 		compatible = "gpio-leds";
 
 		power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 0 1>;
 			default-state = "on";
 		};
diff --git a/target/linux/bcm63xx/dts/bcm6338-d-link-dsl-2640u.dts b/target/linux/bcm63xx/dts/bcm6338-d-link-dsl-2640u.dts
index dae5324f0aa98c..c463eaa4fac4fd 100644
--- a/target/linux/bcm63xx/dts/bcm6338-d-link-dsl-2640u.dts
+++ b/target/linux/bcm63xx/dts/bcm6338-d-link-dsl-2640u.dts
@@ -1,6 +1,7 @@
 #include "bcm6338.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "D-Link DSL-2640U/BRU/C";
@@ -15,7 +16,8 @@
 		compatible = "gpio-leds";
 
 		green_power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 0 1>;
 			default-state = "on";
 		};
diff --git a/target/linux/bcm63xx/dts/bcm6338-dynalink-rta1320.dts b/target/linux/bcm63xx/dts/bcm6338-dynalink-rta1320.dts
index 7d3f4a598f64e2..7148727b1deab7 100644
--- a/target/linux/bcm63xx/dts/bcm6338-dynalink-rta1320.dts
+++ b/target/linux/bcm63xx/dts/bcm6338-dynalink-rta1320.dts
@@ -1,6 +1,7 @@
 #include "bcm6338.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Dynalink RTA1320";
@@ -15,7 +16,8 @@
 		compatible = "gpio-leds";
 
 		green_power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 0 1>;
 			default-state = "on";
 		};
diff --git a/target/linux/bcm63xx/dts/bcm6345-dynalink-rta770bw.dts b/target/linux/bcm63xx/dts/bcm6345-dynalink-rta770bw.dts
index e5b67291b18b4a..0e4b91333e8767 100644
--- a/target/linux/bcm63xx/dts/bcm6345-dynalink-rta770bw.dts
+++ b/target/linux/bcm63xx/dts/bcm6345-dynalink-rta770bw.dts
@@ -1,6 +1,7 @@
 #include "bcm6345.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Siemens Gigaset SE515";
@@ -36,7 +37,8 @@
 		compatible = "gpio-leds";
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 7 1>;
 		};
 
@@ -51,7 +53,8 @@
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 11 1>;
 		};
 	};
diff --git a/target/linux/bcm63xx/dts/bcm6345-dynalink-rta770w.dts b/target/linux/bcm63xx/dts/bcm6345-dynalink-rta770w.dts
index 65fb1d7b1ef579..4ca9f51aa758ab 100644
--- a/target/linux/bcm63xx/dts/bcm6345-dynalink-rta770w.dts
+++ b/target/linux/bcm63xx/dts/bcm6345-dynalink-rta770w.dts
@@ -1,6 +1,7 @@
 #include "bcm6345.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Dynalink RTA770W";
@@ -36,7 +37,8 @@
 		compatible = "gpio-leds";
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 7 1>;
 		};
 
@@ -51,7 +53,8 @@
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 11 1>;
 		};
 	};
diff --git a/target/linux/bcm63xx/dts/bcm6348-asmax-ar-1004g.dts b/target/linux/bcm63xx/dts/bcm6348-asmax-ar-1004g.dts
index 6ffa3b457d3139..43cdb2da92c112 100644
--- a/target/linux/bcm63xx/dts/bcm6348-asmax-ar-1004g.dts
+++ b/target/linux/bcm63xx/dts/bcm6348-asmax-ar-1004g.dts
@@ -1,6 +1,7 @@
 #include "bcm6348.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "ASMAX AR 1004g";
@@ -36,7 +37,8 @@
 		compatible = "gpio-leds";
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 0 1>;
 			default-state = "on";
 		};
@@ -45,7 +47,8 @@
 			gpios = <&pinctrl 3 1>;
 		};
 		power_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&pinctrl 6 1>;
 		};
 	};
diff --git a/target/linux/bcm63xx/dts/bcm6348-belkin-f5d7633.dts b/target/linux/bcm63xx/dts/bcm6348-belkin-f5d7633.dts
index 620d6510b6472d..7686c3deb4994d 100644
--- a/target/linux/bcm63xx/dts/bcm6348-belkin-f5d7633.dts
+++ b/target/linux/bcm63xx/dts/bcm6348-belkin-f5d7633.dts
@@ -1,6 +1,7 @@
 #include "bcm6348.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Belkin F5D7633";
@@ -29,7 +30,8 @@
 		compatible = "gpio-leds";
 
 		power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 0 1>;
 			default-state = "on";
 		};
diff --git a/target/linux/bcm63xx/dts/bcm6348-brcm-bcm96348gw-10.dts b/target/linux/bcm63xx/dts/bcm6348-brcm-bcm96348gw-10.dts
index 8e19d7a261b1d8..d683ac1f09d6cf 100644
--- a/target/linux/bcm63xx/dts/bcm6348-brcm-bcm96348gw-10.dts
+++ b/target/linux/bcm63xx/dts/bcm6348-brcm-bcm96348gw-10.dts
@@ -1,6 +1,7 @@
 #include "bcm6348.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Broadcom BCM96348GW-10 reference board";
@@ -29,7 +30,8 @@
 		compatible = "gpio-leds";
 
 		power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 0 1>;
 			default-state = "on";
 		};
diff --git a/target/linux/bcm63xx/dts/bcm6348-brcm-bcm96348gw-11.dts b/target/linux/bcm63xx/dts/bcm6348-brcm-bcm96348gw-11.dts
index cf983b446b7878..09378dd5147f11 100644
--- a/target/linux/bcm63xx/dts/bcm6348-brcm-bcm96348gw-11.dts
+++ b/target/linux/bcm63xx/dts/bcm6348-brcm-bcm96348gw-11.dts
@@ -1,6 +1,7 @@
 #include "bcm6348.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Broadcom BCM96348GW-11 reference board";
@@ -36,7 +37,8 @@
 		compatible = "gpio-leds";
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 0 1>;
 			default-state = "on";
 		};
diff --git a/target/linux/bcm63xx/dts/bcm6348-brcm-bcm96348gw.dts b/target/linux/bcm63xx/dts/bcm6348-brcm-bcm96348gw.dts
index 9eeb50625d3411..ea1eded5688f4f 100644
--- a/target/linux/bcm63xx/dts/bcm6348-brcm-bcm96348gw.dts
+++ b/target/linux/bcm63xx/dts/bcm6348-brcm-bcm96348gw.dts
@@ -1,6 +1,7 @@
 #include "bcm6348.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Broadcom BCM96348GW reference board";
@@ -36,7 +37,8 @@
 		compatible = "gpio-leds";
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 0 1>;
 			default-state = "on";
 		};
diff --git a/target/linux/bcm63xx/dts/bcm6348-brcm-bcm96348r.dts b/target/linux/bcm63xx/dts/bcm6348-brcm-bcm96348r.dts
index 2b5440456017ba..ff678dc0563caf 100644
--- a/target/linux/bcm63xx/dts/bcm6348-brcm-bcm96348r.dts
+++ b/target/linux/bcm63xx/dts/bcm6348-brcm-bcm96348r.dts
@@ -1,6 +1,7 @@
 #include "bcm6348.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Broadcom 96348R reference board";
@@ -15,7 +16,8 @@
 		compatible = "gpio-leds";
 
 		power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 0 1>;
 			default-state = "on";
 		};
diff --git a/target/linux/bcm63xx/dts/bcm6348-bt-voyager-2110.dts b/target/linux/bcm63xx/dts/bcm6348-bt-voyager-2110.dts
index 39aa48971de46e..d80ed9a943be9b 100644
--- a/target/linux/bcm63xx/dts/bcm6348-bt-voyager-2110.dts
+++ b/target/linux/bcm63xx/dts/bcm6348-bt-voyager-2110.dts
@@ -1,6 +1,7 @@
 #include "bcm6348.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "BT Voyager 2110";
@@ -36,11 +37,13 @@
 		compatible = "gpio-leds";
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 0 1>;
 		};
 		power_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&pinctrl 1 1>;
 		};
 		adsl_green {
diff --git a/target/linux/bcm63xx/dts/bcm6348-bt-voyager-2500v-bb.dts b/target/linux/bcm63xx/dts/bcm6348-bt-voyager-2500v-bb.dts
index 5e399a05a57ca0..bc8616ada1c483 100644
--- a/target/linux/bcm63xx/dts/bcm6348-bt-voyager-2500v-bb.dts
+++ b/target/linux/bcm63xx/dts/bcm6348-bt-voyager-2500v-bb.dts
@@ -1,6 +1,7 @@
 #include "bcm6348.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "BT Voyager 2500V";
@@ -29,11 +30,13 @@
 		compatible = "gpio-leds";
 
 		power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 0 1>;
 		};
 		power_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&pinctrl 1 1>;
 		};
 		adsl_green {
diff --git a/target/linux/bcm63xx/dts/bcm6348-comtrend-ct-5365.dts b/target/linux/bcm63xx/dts/bcm6348-comtrend-ct-5365.dts
index 308139b0ce068f..4eef3139b74951 100644
--- a/target/linux/bcm63xx/dts/bcm6348-comtrend-ct-5365.dts
+++ b/target/linux/bcm63xx/dts/bcm6348-comtrend-ct-5365.dts
@@ -1,6 +1,7 @@
 #include "bcm6348.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Comtrend CT-5365";
@@ -43,16 +44,19 @@
 		compatible = "gpio-leds";
 
 		power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 0 1>;
 			default-state = "on";
 		};
 		alarm_red {
-			label = "red:alarm";
+			function = LED_FUNCTION_ALARM;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&pinctrl 2 1>;
 		};
 		wps_green {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 6 1>;
 		};
 	};
diff --git a/target/linux/bcm63xx/dts/bcm6348-comtrend-ct-536plus.dts b/target/linux/bcm63xx/dts/bcm6348-comtrend-ct-536plus.dts
index e95e4e6e4f4396..2460ccb10c34a3 100644
--- a/target/linux/bcm63xx/dts/bcm6348-comtrend-ct-536plus.dts
+++ b/target/linux/bcm63xx/dts/bcm6348-comtrend-ct-536plus.dts
@@ -1,6 +1,7 @@
 #include "bcm6348.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Comtrend CT-536+/CT-5621T";
@@ -36,7 +37,8 @@
 		compatible = "gpio-leds";
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 0 1>;
 			default-state = "on";
 		};
diff --git a/target/linux/bcm63xx/dts/bcm6348-d-link-dsl-2640b-b.dts b/target/linux/bcm63xx/dts/bcm6348-d-link-dsl-2640b-b.dts
index d71bc4e56a61dc..f50992b02b6a7a 100644
--- a/target/linux/bcm63xx/dts/bcm6348-d-link-dsl-2640b-b.dts
+++ b/target/linux/bcm63xx/dts/bcm6348-d-link-dsl-2640b-b.dts
@@ -1,6 +1,7 @@
 #include "bcm6348.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "D-Link DSL-2640B rev B2";
@@ -36,7 +37,8 @@
 		compatible = "gpio-leds";
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 0 1>;
 			default-state = "on";
 		};
diff --git a/target/linux/bcm63xx/dts/bcm6348-netgear-dg834g-v4.dts b/target/linux/bcm63xx/dts/bcm6348-netgear-dg834g-v4.dts
index e91a4105dbe3f5..318f12b66ca2bd 100644
--- a/target/linux/bcm63xx/dts/bcm6348-netgear-dg834g-v4.dts
+++ b/target/linux/bcm63xx/dts/bcm6348-netgear-dg834g-v4.dts
@@ -1,6 +1,7 @@
 #include "bcm6348.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Netgear DG834G v4";
@@ -29,12 +30,14 @@
 		compatible = "gpio-leds";
 
 		power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 0 1>;
 			default-state = "on";
 		};
 		status {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&pinctrl 1 1>;
 		};
 		inet_green {
diff --git a/target/linux/bcm63xx/dts/bcm6348-netgear-dg834gt-pn.dts b/target/linux/bcm63xx/dts/bcm6348-netgear-dg834gt-pn.dts
index 3f17f987dadeef..eb20d4b6c8af6a 100644
--- a/target/linux/bcm63xx/dts/bcm6348-netgear-dg834gt-pn.dts
+++ b/target/linux/bcm63xx/dts/bcm6348-netgear-dg834gt-pn.dts
@@ -1,6 +1,7 @@
 #include "bcm6348.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Netgear DG834GT/PN";
@@ -29,7 +30,8 @@
 		compatible = "gpio-leds";
 
 		power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 0 1>;
 			default-state = "on";
 		};
diff --git a/target/linux/bcm63xx/dts/bcm6348-sagem-fast-2604.dts b/target/linux/bcm63xx/dts/bcm6348-sagem-fast-2604.dts
index 987903d525e934..4a1862b71f0040 100644
--- a/target/linux/bcm63xx/dts/bcm6348-sagem-fast-2604.dts
+++ b/target/linux/bcm63xx/dts/bcm6348-sagem-fast-2604.dts
@@ -1,6 +1,7 @@
 #include "bcm6348.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Sagem F@st 2604";
@@ -29,12 +30,14 @@
 		compatible = "gpio-leds";
 
 		power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 0 1>;
 			default-state = "on";
 		};
 		power_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&pinctrl 1 1>;
 		};
 		inet_red {
@@ -42,7 +45,8 @@
 			gpios = <&pinctrl 4 1>;
 		};
 		wps_green {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 5 1>;
 		};
 	};
diff --git a/target/linux/bcm63xx/dts/bcm6348-t-com-speedport-w-500v.dts b/target/linux/bcm63xx/dts/bcm6348-t-com-speedport-w-500v.dts
index c096b88d8fc5a4..29cc3fa64438e9 100644
--- a/target/linux/bcm63xx/dts/bcm6348-t-com-speedport-w-500v.dts
+++ b/target/linux/bcm63xx/dts/bcm6348-t-com-speedport-w-500v.dts
@@ -1,6 +1,7 @@
 #include "bcm6348.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "T-Com Speedport W 500V";
@@ -36,12 +37,14 @@
 		compatible = "gpio-leds";
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 0 1>;
 			default-state = "on";
 		};
 		power_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&pinctrl 1 1>;
 		};
 		ppp_green {
diff --git a/target/linux/bcm63xx/dts/bcm6348-telsey-magic.dts b/target/linux/bcm63xx/dts/bcm6348-telsey-magic.dts
index 00ce70f17bae41..c9d9989168c4f1 100644
--- a/target/linux/bcm63xx/dts/bcm6348-telsey-magic.dts
+++ b/target/linux/bcm63xx/dts/bcm6348-telsey-magic.dts
@@ -1,6 +1,7 @@
 #include "bcm6348.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Alice W-Gate";
@@ -15,7 +16,8 @@
 		compatible = "gpio-leds";
 
 		power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 0 1>;
 			default-state = "on";
 		};
@@ -46,7 +48,8 @@
 		};
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 35 1>;
 		};
 	};
diff --git a/target/linux/bcm63xx/dts/bcm6348-tp-link-td-w8900gb.dts b/target/linux/bcm63xx/dts/bcm6348-tp-link-td-w8900gb.dts
index 1a49e7ff337185..6e1f7155d95d56 100644
--- a/target/linux/bcm63xx/dts/bcm6348-tp-link-td-w8900gb.dts
+++ b/target/linux/bcm63xx/dts/bcm6348-tp-link-td-w8900gb.dts
@@ -1,6 +1,7 @@
 #include "bcm6348.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "TP-Link TD-W8900GB";
@@ -29,7 +30,8 @@
 		compatible = "gpio-leds";
 
 		power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 0 1>;
 			default-state = "on";
 		};
diff --git a/target/linux/bcm63xx/dts/bcm6358-alcatel-rg100a.dts b/target/linux/bcm63xx/dts/bcm6358-alcatel-rg100a.dts
index fdc1edf9069297..0b5abbd1f69ac7 100644
--- a/target/linux/bcm63xx/dts/bcm6358-alcatel-rg100a.dts
+++ b/target/linux/bcm63xx/dts/bcm6358-alcatel-rg100a.dts
@@ -1,6 +1,7 @@
 #include "bcm6358.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Alcatel RG100A";
@@ -19,7 +20,8 @@
 			gpios = <&pinctrl 4 1>;
 		};
 		power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 5 1>;
 			default-state = "on";
 		};
diff --git a/target/linux/bcm63xx/dts/bcm6358-brcm-bcm96358vw.dts b/target/linux/bcm63xx/dts/bcm6358-brcm-bcm96358vw.dts
index bf997935e86dc8..0a09b2d86c4993 100644
--- a/target/linux/bcm63xx/dts/bcm6358-brcm-bcm96358vw.dts
+++ b/target/linux/bcm63xx/dts/bcm6358-brcm-bcm96358vw.dts
@@ -1,6 +1,7 @@
 #include "bcm6358.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Broadcom BCM96358VW reference board";
@@ -15,7 +16,8 @@
 		compatible = "gpio-leds";
 
 		power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 4 0>;
 			default-state = "on";
 		};
diff --git a/target/linux/bcm63xx/dts/bcm6358-brcm-bcm96358vw2.dts b/target/linux/bcm63xx/dts/bcm6358-brcm-bcm96358vw2.dts
index 316581d2a5a19b..a89fdb1fe4623a 100644
--- a/target/linux/bcm63xx/dts/bcm6358-brcm-bcm96358vw2.dts
+++ b/target/linux/bcm63xx/dts/bcm6358-brcm-bcm96358vw2.dts
@@ -1,6 +1,7 @@
 #include "bcm6358.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Broadcom BCM96358VW2 reference board";
@@ -19,7 +20,8 @@
 			gpios = <&pinctrl 4 1>;
 		};
 		power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 5 1>;
 			default-state = "on";
 		};
diff --git a/target/linux/bcm63xx/dts/bcm6358-bt-home-hub-2-a.dts b/target/linux/bcm63xx/dts/bcm6358-bt-home-hub-2-a.dts
index 10aea48783b317..809f3b39b4ca1e 100644
--- a/target/linux/bcm63xx/dts/bcm6358-bt-home-hub-2-a.dts
+++ b/target/linux/bcm63xx/dts/bcm6358-bt-home-hub-2-a.dts
@@ -1,6 +1,7 @@
 #include "bcm6358.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "BT Home Hub 2.0 Type A";
@@ -56,20 +57,23 @@
 	led@0 {
 		reg = <0>;
 		active-low;
-		label = "red:power";
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_RED>;
 	};
 
 	led_power_green: led@1 {
 		reg = <1>;
 		active-low;
-		label = "green:power";
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_GREEN>;
 		default-state = "on";
 	};
 
 	led@2 {
 		reg = <2>;
 		active-low;
-		label = "blue:power";
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_BLUE>;
 	};
 
 	led@3 {
diff --git a/target/linux/bcm63xx/dts/bcm6358-comtrend-ct-6373.dts b/target/linux/bcm63xx/dts/bcm6358-comtrend-ct-6373.dts
index ab9d5659ba6e3f..2dc85f6776349e 100644
--- a/target/linux/bcm63xx/dts/bcm6358-comtrend-ct-6373.dts
+++ b/target/linux/bcm63xx/dts/bcm6358-comtrend-ct-6373.dts
@@ -1,6 +1,7 @@
 #include "bcm6358.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Comtrend CT-6373";
@@ -29,16 +30,19 @@
 		compatible = "gpio-leds";
 
 		power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 0 0>;
 			default-state = "on";
 		};
 		usb_green {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 3 1>;
 		};
 		wlan_green {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 9 1>;
 		};
 	};
diff --git a/target/linux/bcm63xx/dts/bcm6358-d-link-dsl-2650u.dts b/target/linux/bcm63xx/dts/bcm6358-d-link-dsl-2650u.dts
index 6d26261a34d484..dbc4172f54d16c 100644
--- a/target/linux/bcm63xx/dts/bcm6358-d-link-dsl-2650u.dts
+++ b/target/linux/bcm63xx/dts/bcm6358-d-link-dsl-2650u.dts
@@ -1,6 +1,7 @@
 #include "bcm6358.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "D-Link DSL-2650U";
@@ -19,7 +20,8 @@
 			gpios = <&pinctrl 4 1>;
 		};
 		power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 5 1>;
 			default-state = "on";
 		};
diff --git a/target/linux/bcm63xx/dts/bcm6358-d-link-dsl-274xb-c2.dts b/target/linux/bcm63xx/dts/bcm6358-d-link-dsl-274xb-c2.dts
index ff007ebe4c7732..917fd6dc1dc566 100644
--- a/target/linux/bcm63xx/dts/bcm6358-d-link-dsl-274xb-c2.dts
+++ b/target/linux/bcm63xx/dts/bcm6358-d-link-dsl-274xb-c2.dts
@@ -1,6 +1,7 @@
 #include "bcm6358.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "D-Link DSL-2740B/DSL-2741B rev C2/3";
@@ -40,11 +41,13 @@
 			gpios = <&pinctrl 2 0>;
 		};
 		power_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&pinctrl 4 1>;
 		};
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 5 1>;
 			default-state = "on";
 		};
diff --git a/target/linux/bcm63xx/dts/bcm6358-huawei-echolife-hg553.dts b/target/linux/bcm63xx/dts/bcm6358-huawei-echolife-hg553.dts
index 243e2ca3003fa8..052262dca710c4 100644
--- a/target/linux/bcm63xx/dts/bcm6358-huawei-echolife-hg553.dts
+++ b/target/linux/bcm63xx/dts/bcm6358-huawei-echolife-hg553.dts
@@ -1,6 +1,7 @@
 #include "bcm6358.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Huawei EchoLife HG553";
@@ -43,12 +44,14 @@
 		compatible = "gpio-leds";
 
 		led_power_blue: power_blue {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&pinctrl 4 1>;
 			default-state = "on";
 		};
 		power_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&pinctrl 5 1>;
 		};
 		hspa_red {
@@ -60,11 +63,13 @@
 			gpios = <&pinctrl 13 1>;
 		};
 		lan_red {
-			label = "red:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&pinctrl 22 1>;
 		};
 		lan_blue {
-			label = "blue:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&pinctrl 23 1>;
 		};
 		wifi_red {
diff --git a/target/linux/bcm63xx/dts/bcm6358-huawei-echolife-hg556a.dtsi b/target/linux/bcm63xx/dts/bcm6358-huawei-echolife-hg556a.dtsi
index 09a21f7ad73559..f64e02e1c53c3f 100644
--- a/target/linux/bcm63xx/dts/bcm6358-huawei-echolife-hg556a.dtsi
+++ b/target/linux/bcm63xx/dts/bcm6358-huawei-echolife-hg556a.dtsi
@@ -1,6 +1,7 @@
 #include "bcm6358.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -52,7 +53,8 @@
 		};
 
 		led_power_red: power_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&pinctrl 3 1>;
 			default-state = "on";
 		};
diff --git a/target/linux/bcm63xx/dts/bcm6358-pirelli-a226.dtsi b/target/linux/bcm63xx/dts/bcm6358-pirelli-a226.dtsi
index cc833b0c18d7e6..f6de31ccf91f16 100644
--- a/target/linux/bcm63xx/dts/bcm6358-pirelli-a226.dtsi
+++ b/target/linux/bcm63xx/dts/bcm6358-pirelli-a226.dtsi
@@ -1,6 +1,7 @@
 #include "bcm6358.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	chosen {
@@ -45,16 +46,19 @@
 			gpios = <&pinctrl 2 1>;
 		};
 		usb_green {
-			label = "green:USB";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 3 1>;
 		};
 		power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 4 1>;
 			default-state = "on";
 		};
 		power_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&pinctrl 5 1>;
 		};
 		inet_red {
@@ -78,7 +82,8 @@
 			gpios = <&pinctrl 10 1>;
 		};
 		usb_red {
-			label = "red:USB";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&pinctrl 11 1>;
 		};
 		dsl_red {
diff --git a/target/linux/bcm63xx/dts/bcm6358-pirelli-agpf-s0.dts b/target/linux/bcm63xx/dts/bcm6358-pirelli-agpf-s0.dts
index 12e9a0eba389d3..55cea95b84bce0 100644
--- a/target/linux/bcm63xx/dts/bcm6358-pirelli-agpf-s0.dts
+++ b/target/linux/bcm63xx/dts/bcm6358-pirelli-agpf-s0.dts
@@ -1,6 +1,7 @@
 #include "bcm6358.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Pirelli Alice Gate AGPF-S0";
@@ -36,12 +37,14 @@
 		compatible = "gpio-leds";
 
 		power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 4 1>;
 			default-state = "on";
 		};
 		power_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&pinctrl 5 1>;
 		};
 		service_green {
diff --git a/target/linux/bcm63xx/dts/bcm6358-sfr-neufbox-4.dtsi b/target/linux/bcm63xx/dts/bcm6358-sfr-neufbox-4.dtsi
index 58075c879ad6cd..9be493ebd549f3 100644
--- a/target/linux/bcm63xx/dts/bcm6358-sfr-neufbox-4.dtsi
+++ b/target/linux/bcm63xx/dts/bcm6358-sfr-neufbox-4.dtsi
@@ -1,6 +1,7 @@
 #include "bcm6358.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	chosen {
@@ -53,7 +54,8 @@
 	led@0 {
 		reg = <0>;
 		active-low;
-		label = "white:alarm";
+		function = LED_FUNCTION_ALARM;
+		color = <LED_COLOR_ID_WHITE>;
 	};
 
 	led@2 {
diff --git a/target/linux/bcm63xx/dts/bcm6358-telsey-cpva642.dts b/target/linux/bcm63xx/dts/bcm6358-telsey-cpva642.dts
index f679b40ac9d065..1a6b9658bb1649 100644
--- a/target/linux/bcm63xx/dts/bcm6358-telsey-cpva642.dts
+++ b/target/linux/bcm63xx/dts/bcm6358-telsey-cpva642.dts
@@ -1,6 +1,7 @@
 #include "bcm6358.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Telsey CPVA642-type (CPA-ZNTE60T)";
@@ -51,7 +52,8 @@
 			gpios = <&pinctrl 2 1>;
 		};
 		usb_green {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 3 1>;
 		};
 		phone1_green {
@@ -71,12 +73,14 @@
 			gpios = <&pinctrl 10 1>;
 		};
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 11 1>;
 			default-state = "on";
 		};
 		power_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&pinctrl 14 1>;
 		};
 		wifi_green {
diff --git a/target/linux/bcm63xx/dts/bcm6362-huawei-hg253s-v2.dts b/target/linux/bcm63xx/dts/bcm6362-huawei-hg253s-v2.dts
index 255c1c8f6c9ab1..9217fd30989f6f 100644
--- a/target/linux/bcm63xx/dts/bcm6362-huawei-hg253s-v2.dts
+++ b/target/linux/bcm63xx/dts/bcm6362-huawei-hg253s-v2.dts
@@ -1,6 +1,7 @@
 #include "bcm6362.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Huawei HG253s v2";
@@ -54,7 +55,8 @@
 		};
 
 		led@30 {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 30 1>;
 		};
 	};
diff --git a/target/linux/bcm63xx/dts/bcm6362-netgear-dgnd3700-v2.dts b/target/linux/bcm63xx/dts/bcm6362-netgear-dgnd3700-v2.dts
index 4bef5908e03596..8d457c906e1a97 100644
--- a/target/linux/bcm63xx/dts/bcm6362-netgear-dgnd3700-v2.dts
+++ b/target/linux/bcm63xx/dts/bcm6362-netgear-dgnd3700-v2.dts
@@ -3,6 +3,7 @@
 #include "bcm6362.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Netgear DGND3700v2";
@@ -57,7 +58,8 @@
 		};
 
 		led@34 {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&pinctrl 34 1>;
 		};
 	};
@@ -81,14 +83,16 @@
 
 	led_power_green: led@8 {
 		reg = <8>;
-		label = "green:power";
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_GREEN>;
 		default-state = "on";
 	};
 
 	led@9 {
 		reg = <9>;
 		active-low;
-		label = "green:wps";
+		function = LED_FUNCTION_WPS;
+		color = <LED_COLOR_ID_GREEN>;
 	};
 
 	led@10 {
diff --git a/target/linux/bcm63xx/dts/bcm6362-sagem-fast-2504n.dts b/target/linux/bcm63xx/dts/bcm6362-sagem-fast-2504n.dts
index e5ae573c973856..105e56a59692a0 100644
--- a/target/linux/bcm63xx/dts/bcm6362-sagem-fast-2504n.dts
+++ b/target/linux/bcm63xx/dts/bcm6362-sagem-fast-2504n.dts
@@ -1,6 +1,7 @@
 #include "bcm6362.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Sagem F@st 2504N";
@@ -43,11 +44,13 @@
 		compatible = "gpio-leds";
 
 		power_orange {
-			label = "orange:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&pinctrl 2 1>;
 		};
 		power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 10 1>;
 			default-state = "on";
 		};
@@ -64,7 +67,8 @@
 			gpios = <&pinctrl 29 1>;
 		};
 		wlan_orangee {
-			label = "orange:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&pinctrl 30 1>;
 		};
 	};
diff --git a/target/linux/bcm63xx/dts/bcm6368-actiontec-r1000h.dts b/target/linux/bcm63xx/dts/bcm6368-actiontec-r1000h.dts
index fa038962c2796b..3fe1693331a3e6 100644
--- a/target/linux/bcm63xx/dts/bcm6368-actiontec-r1000h.dts
+++ b/target/linux/bcm63xx/dts/bcm6368-actiontec-r1000h.dts
@@ -1,6 +1,7 @@
 #include "bcm6368.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Actiontec R1000H";
@@ -48,28 +49,33 @@
 		};
 
 		usb_green {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 21 1>;
 		};
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 22 0>;
 			default-state = "on";
 		};
 
 		wps_green {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 23 1>;
 		};
 
 		power_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&pinctrl 24 0>;
 		};
 
 		wps_red {
-			label = "red:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&pinctrl 30 1>;
 		};
 
diff --git a/target/linux/bcm63xx/dts/bcm6368-adb-av4202n.dts b/target/linux/bcm63xx/dts/bcm6368-adb-av4202n.dts
index fb1b4bcf060265..45046f326a96e2 100644
--- a/target/linux/bcm63xx/dts/bcm6368-adb-av4202n.dts
+++ b/target/linux/bcm63xx/dts/bcm6368-adb-av4202n.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "ADB P.DG AV4202N";
@@ -44,20 +45,24 @@
 		compatible = "gpio-leds";
 
 		led_power_white: power_white {
-			label = "white:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&pinctrl 10 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 		power_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&pinctrl 11 GPIO_ACTIVE_LOW>;
 		};
 		wan_white {
-			label = "white:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&pinctrl 26 GPIO_ACTIVE_LOW>;
 		};
 		wan_red {
-			label = "red:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&pinctrl 27 GPIO_ACTIVE_LOW>;
 		};
 		phone_white {
diff --git a/target/linux/bcm63xx/dts/bcm6368-brcm-bcm96368mvngr.dts b/target/linux/bcm63xx/dts/bcm6368-brcm-bcm96368mvngr.dts
index 50c57d527164f6..6160ab636e64e8 100644
--- a/target/linux/bcm63xx/dts/bcm6368-brcm-bcm96368mvngr.dts
+++ b/target/linux/bcm63xx/dts/bcm6368-brcm-bcm96368mvngr.dts
@@ -1,6 +1,7 @@
 #include "bcm6368.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Broadcom BCM96368MVNgr reference board";
@@ -27,12 +28,14 @@
 			gpios = <&pinctrl 5 0>;
 		};
 		power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 22 0>;
 			default-state = "on";
 		};
 		wps_green {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 23 1>;
 		};
 	};
diff --git a/target/linux/bcm63xx/dts/bcm6368-brcm-bcm96368mvwg.dts b/target/linux/bcm63xx/dts/bcm6368-brcm-bcm96368mvwg.dts
index 664e3e02f5749e..10f98511c0cdc2 100644
--- a/target/linux/bcm63xx/dts/bcm6368-brcm-bcm96368mvwg.dts
+++ b/target/linux/bcm63xx/dts/bcm6368-brcm-bcm96368mvwg.dts
@@ -1,6 +1,7 @@
 #include "bcm6368.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Broadcom BCM96368MVWG reference board";
@@ -23,12 +24,14 @@
 			gpios = <&pinctrl 5 0>;
 		};
 		power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 22 0>;
 			default-state = "on";
 		};
 		wps_green {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 23 1>;
 		};
 		ppp_fail_red {
diff --git a/target/linux/bcm63xx/dts/bcm6368-comtrend-vr-3025u.dts b/target/linux/bcm63xx/dts/bcm6368-comtrend-vr-3025u.dts
index a237d18ac71d4d..12195de8013406 100644
--- a/target/linux/bcm63xx/dts/bcm6368-comtrend-vr-3025u.dts
+++ b/target/linux/bcm63xx/dts/bcm6368-comtrend-vr-3025u.dts
@@ -1,6 +1,7 @@
 #include "bcm6368.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Comtrend VR-3025u";
@@ -44,12 +45,14 @@
 			gpios = <&pinctrl 5 0>;
 		};
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 22 0>;
 			default-state = "on";
 		};
 		power_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&pinctrl 24 0>;
 		};
 		inet_red {
diff --git a/target/linux/bcm63xx/dts/bcm6368-comtrend-vr-3025un.dts b/target/linux/bcm63xx/dts/bcm6368-comtrend-vr-3025un.dts
index 2391fb06710058..6a17c49d120b9e 100644
--- a/target/linux/bcm63xx/dts/bcm6368-comtrend-vr-3025un.dts
+++ b/target/linux/bcm63xx/dts/bcm6368-comtrend-vr-3025un.dts
@@ -1,6 +1,7 @@
 #include "bcm6368.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Comtrend VR-3025un";
@@ -44,12 +45,14 @@
 			gpios = <&pinctrl 5 0>;
 		};
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 22 0>;
 			default-state = "on";
 		};
 		power_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&pinctrl 24 0>;
 		};
 		inet_red {
diff --git a/target/linux/bcm63xx/dts/bcm6368-comtrend-vr-3026e.dts b/target/linux/bcm63xx/dts/bcm6368-comtrend-vr-3026e.dts
index b17439ea23b6ee..b56f693243145e 100644
--- a/target/linux/bcm63xx/dts/bcm6368-comtrend-vr-3026e.dts
+++ b/target/linux/bcm63xx/dts/bcm6368-comtrend-vr-3026e.dts
@@ -1,6 +1,7 @@
 #include "bcm6368.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Comtrend VR-3026e";
@@ -44,12 +45,14 @@
 			gpios = <&pinctrl 5 0>;
 		};
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 22 0>;
 			default-state = "on";
 		};
 		power_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&pinctrl 24 0>;
 		};
 		inet_red {
diff --git a/target/linux/bcm63xx/dts/bcm6368-huawei-echolife-hg622.dts b/target/linux/bcm63xx/dts/bcm6368-huawei-echolife-hg622.dts
index 95e482bca36b21..89c9c26032d6ee 100644
--- a/target/linux/bcm63xx/dts/bcm6368-huawei-echolife-hg622.dts
+++ b/target/linux/bcm63xx/dts/bcm6368-huawei-echolife-hg622.dts
@@ -1,6 +1,7 @@
 #include "bcm6368.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Huawei EchoLife HG622";
@@ -38,11 +39,13 @@
 			gpios = <&pinctrl 5 1>;
 		};
 		usb_green {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 11 1>;
 		};
 		power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 22 1>;
 			default-state = "on";
 		};
diff --git a/target/linux/bcm63xx/dts/bcm6368-huawei-echolife-hg655b.dts b/target/linux/bcm63xx/dts/bcm6368-huawei-echolife-hg655b.dts
index 124b5ca1b7d5a3..778753558d4b78 100644
--- a/target/linux/bcm63xx/dts/bcm6368-huawei-echolife-hg655b.dts
+++ b/target/linux/bcm63xx/dts/bcm6368-huawei-echolife-hg655b.dts
@@ -1,6 +1,7 @@
 #include "bcm6368.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Huawei EchoLife HG655b";
@@ -59,11 +60,13 @@
 		};
 
 		usb_green {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 14 1>;
 		};
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 22 1>;
 			default-state = "on";
 		};
@@ -72,7 +75,8 @@
 			gpios = <&pinctrl 25 1>;
 		};
 		wps_green {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 27 1>;
 		};
 	};
diff --git a/target/linux/bcm63xx/dts/bcm6368-netgear-dgnd3700-v1.dts b/target/linux/bcm63xx/dts/bcm6368-netgear-dgnd3700-v1.dts
index 700adea4c19b11..b1053903f2d446 100644
--- a/target/linux/bcm63xx/dts/bcm6368-netgear-dgnd3700-v1.dts
+++ b/target/linux/bcm63xx/dts/bcm6368-netgear-dgnd3700-v1.dts
@@ -1,6 +1,7 @@
 #include "bcm6368.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Netgear DGND3700v1/DGND3800B";
@@ -62,7 +63,8 @@
 			gpios = <&pinctrl 5 1>;
 		};
 		wps_green {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 11 1>;
 		};
 		usbfront_green {
@@ -74,15 +76,18 @@
 			gpios = <&pinctrl 14 1>;
 		};
 		power_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&pinctrl 22 1>;
 		};
 		lan_green {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 23 1>;
 		};
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 24 1>;
 			default-state = "on";
 		};
diff --git a/target/linux/bcm63xx/dts/bcm6368-observa-vh4032n.dts b/target/linux/bcm63xx/dts/bcm6368-observa-vh4032n.dts
index 9ed3cc23d0e773..7e018584a16fef 100644
--- a/target/linux/bcm63xx/dts/bcm6368-observa-vh4032n.dts
+++ b/target/linux/bcm63xx/dts/bcm6368-observa-vh4032n.dts
@@ -1,6 +1,7 @@
 #include "bcm6368.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Observa VH4032N";
@@ -59,12 +60,14 @@
 			gpios = <&pinctrl 12 1>;
 		};
 		led_power_blue: power_blue {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&pinctrl 22 0>;
 			default-state = "on";
 		};
 		power_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&pinctrl 24 0>;
 		};
 		voice_blue {
diff --git a/target/linux/bcm63xx/dts/bcm6368-zyxel-p870hw-51a-v2.dts b/target/linux/bcm63xx/dts/bcm6368-zyxel-p870hw-51a-v2.dts
index 0bc66fb031a9e6..6118cd81117ec2 100644
--- a/target/linux/bcm63xx/dts/bcm6368-zyxel-p870hw-51a-v2.dts
+++ b/target/linux/bcm63xx/dts/bcm6368-zyxel-p870hw-51a-v2.dts
@@ -1,6 +1,7 @@
 #include "bcm6368.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Zyxel P870HW-51a v2";
@@ -43,7 +44,8 @@
 		compatible = "gpio-leds";
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 0 0>;
 			default-state = "on";
 		};
@@ -56,7 +58,8 @@
 			gpios = <&pinctrl 22 1>;
 		};
 		wps_orange {
-			label = "orange:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&pinctrl 24 1>;
 		};
 		inet_red {
diff --git a/target/linux/bcm63xx/dts/bcm6369-comtrend-wap-5813n.dts b/target/linux/bcm63xx/dts/bcm6369-comtrend-wap-5813n.dts
index 2f0ec53e3473d5..a25ce69f00e7a6 100644
--- a/target/linux/bcm63xx/dts/bcm6369-comtrend-wap-5813n.dts
+++ b/target/linux/bcm63xx/dts/bcm6369-comtrend-wap-5813n.dts
@@ -1,6 +1,7 @@
 #include "bcm6368.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Comtrend WAP-5813n";
@@ -54,16 +55,19 @@
 			gpios = <&pinctrl 5 0>;
 		};
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 22 0>;
 			default-state = "on";
 		};
 		wps_green {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 23 1>;
 		};
 		power_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&pinctrl 24 0>;
 		};
 		inet_red {
diff --git a/target/linux/bcm63xx/dts/bcm6369-netgear-evg2000.dts b/target/linux/bcm63xx/dts/bcm6369-netgear-evg2000.dts
index b96ba7eb653ff0..3e9d9e873cab0f 100644
--- a/target/linux/bcm63xx/dts/bcm6369-netgear-evg2000.dts
+++ b/target/linux/bcm63xx/dts/bcm6369-netgear-evg2000.dts
@@ -1,6 +1,7 @@
 #include "bcm6368.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Netgear EVG2000";
@@ -59,20 +60,24 @@
 			gpios = <&pinctrl 5 1>;
 		};
 		usb_green {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 15 1>;
 		};
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 22 1>;
 			default-state = "on";
 		};
 		power_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&pinctrl 23 1>;
 		};
 		lan_green {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 24 1>;
 		};
 		wireless_green {
@@ -80,7 +85,8 @@
 			gpios = <&pinctrl 26 1>;
 		};
 		wan_green {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pinctrl 27 1>;
 		};
 	};
diff --git a/target/linux/bcm63xx/patches-5.15/144-add-removed-syscon_regmap_lookup_by_pdevname.patch b/target/linux/bcm63xx/patches-5.15/144-add-removed-syscon_regmap_lookup_by_pdevname.patch
index 5a3e6b06798b83..71991663770ae8 100644
--- a/target/linux/bcm63xx/patches-5.15/144-add-removed-syscon_regmap_lookup_by_pdevname.patch
+++ b/target/linux/bcm63xx/patches-5.15/144-add-removed-syscon_regmap_lookup_by_pdevname.patch
@@ -16,7 +16,7 @@ Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
 
 --- a/drivers/mfd/syscon.c
 +++ b/drivers/mfd/syscon.c
-@@ -205,6 +205,27 @@ struct regmap *syscon_regmap_lookup_by_c
+@@ -209,6 +209,27 @@ struct regmap *syscon_regmap_lookup_by_c
  }
  EXPORT_SYMBOL_GPL(syscon_regmap_lookup_by_compatible);
  
diff --git a/target/linux/bmips/dts/bcm63167-sercomm-h500-s.dtsi b/target/linux/bmips/dts/bcm63167-sercomm-h500-s.dtsi
index a389187d8ddd69..66c64d990bdef3 100644
--- a/target/linux/bmips/dts/bcm63167-sercomm-h500-s.dtsi
+++ b/target/linux/bmips/dts/bcm63167-sercomm-h500-s.dtsi
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later
 
+#include <dt-bindings/leds/common.h>
+
 #include "bcm63268.dtsi"
 
 / {
@@ -59,7 +61,8 @@
 
 	led_power_red: led@8 {
 		reg = <8>;
-		label = "red:power";
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_RED>;
 		panic-indicator;
 	};
 
@@ -95,7 +98,8 @@
 
 	led_power_green: led@17 {
 		reg = <17>;
-		label = "green:power";
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_GREEN>;
 	};
 
 	led@23 {
diff --git a/target/linux/bmips/dts/bcm63168-comtrend-vr-3032u.dts b/target/linux/bmips/dts/bcm63168-comtrend-vr-3032u.dts
index 3f830f058e6b24..cb42e0c1f1808f 100644
--- a/target/linux/bmips/dts/bcm63168-comtrend-vr-3032u.dts
+++ b/target/linux/bmips/dts/bcm63168-comtrend-vr-3032u.dts
@@ -83,13 +83,15 @@
 	led@4 {
 		reg = <4>;
 		active-low;
-		label = "green:usb";
+		function = LED_FUNCTION_USB;
+		color = <LED_COLOR_ID_GREEN>;
 	};
 
 	led@7 {
 		reg = <7>;
 		active-low;
-		label = "green:wps";
+		function = LED_FUNCTION_WPS;
+		color = <LED_COLOR_ID_GREEN>;
 	};
 
 	led@8 {
@@ -143,7 +145,8 @@
 	led_power_green: led@20 {
 		reg = <20>;
 		active-low;
-		label = "green:power";
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_GREEN>;
 	};
 };
 
diff --git a/target/linux/bmips/dts/bcm63168-sercomm-shg2500.dts b/target/linux/bmips/dts/bcm63168-sercomm-shg2500.dts
index 3c79d38bfbdd09..7ea76bebc31424 100644
--- a/target/linux/bmips/dts/bcm63168-sercomm-shg2500.dts
+++ b/target/linux/bmips/dts/bcm63168-sercomm-shg2500.dts
@@ -109,7 +109,8 @@
 
 		led_power_red: led@8 {
 			reg = <8>;
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 		};
 
 		led@9 {
diff --git a/target/linux/bmips/dts/bcm63169-comtrend-vg-8050.dts b/target/linux/bmips/dts/bcm63169-comtrend-vg-8050.dts
index b0576748d3500c..05004462e7760d 100644
--- a/target/linux/bmips/dts/bcm63169-comtrend-vg-8050.dts
+++ b/target/linux/bmips/dts/bcm63169-comtrend-vg-8050.dts
@@ -121,20 +121,23 @@
 	led_power_red: led@3 {
 		reg = <3>;
 		active-low;
-		label = "red:power";
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_RED>;
 		panic-indicator;
 	};
 
 	led_power_green: led@6 {
 		reg = <6>;
 		active-low;
-		label = "green:power";
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_GREEN>;
 	};
 
 	led@7 {
 		reg = <7>;
 		active-low;
-		label = "green:wps";
+		function = LED_FUNCTION_WPS;
+		color = <LED_COLOR_ID_GREEN>;
 	};
 
 	led@8 {
@@ -158,7 +161,8 @@
 	led@14 {
 		reg = <14>;
 		active-low;
-		label = "red:wps";
+		function = LED_FUNCTION_WPS;
+		color = <LED_COLOR_ID_RED>;
 	};
 };
 
diff --git a/target/linux/bmips/dts/bcm6318-comtrend-ar-5315u.dts b/target/linux/bmips/dts/bcm6318-comtrend-ar-5315u.dts
index 052f61002bdc4e..c5d2182b78fa6b 100644
--- a/target/linux/bmips/dts/bcm6318-comtrend-ar-5315u.dts
+++ b/target/linux/bmips/dts/bcm6318-comtrend-ar-5315u.dts
@@ -128,19 +128,22 @@
 	led@0 {
 		reg = <0>;
 		active-low;
-		label = "green:wps";
+		function = LED_FUNCTION_WPS;
+		color = <LED_COLOR_ID_GREEN>;
 	};
 
 	led_power_green: led@1 {
 		reg = <1>;
 		active-low;
-		label = "green:power";
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_GREEN>;
 	};
 
 	led@2 {
 		reg = <2>;
 		active-low;
-		label = "green:usb";
+		function = LED_FUNCTION_USB;
+		color = <LED_COLOR_ID_GREEN>;
 	};
 
 	led@4 {
@@ -192,7 +195,8 @@
 	led_power_red: led@11 {
 		reg = <11>;
 		active-low;
-		label = "red:power";
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_RED>;
 		panic-indicator;
 	};
 };
diff --git a/target/linux/bmips/dts/bcm6318.dtsi b/target/linux/bmips/dts/bcm6318.dtsi
index 28c656d090e11c..03fb01bc047d18 100644
--- a/target/linux/bmips/dts/bcm6318.dtsi
+++ b/target/linux/bmips/dts/bcm6318.dtsi
@@ -7,6 +7,7 @@
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/bcm6318-interrupt-controller.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/reset/bcm6318-reset.h>
 #include <dt-bindings/soc/bcm6318-pm.h>
 
diff --git a/target/linux/bmips/dts/bcm63268.dtsi b/target/linux/bmips/dts/bcm63268.dtsi
index f9a31d36ef7219..d1aed29018e3a0 100644
--- a/target/linux/bmips/dts/bcm63268.dtsi
+++ b/target/linux/bmips/dts/bcm63268.dtsi
@@ -7,6 +7,7 @@
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/bcm63268-interrupt-controller.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/reset/bcm63268-reset.h>
 #include <dt-bindings/soc/bcm63268-pm.h>
 
diff --git a/target/linux/bmips/dts/bcm6328-arcadyan-ar7516.dts b/target/linux/bmips/dts/bcm6328-arcadyan-ar7516.dts
index 649c5958483b7c..4c5c607f44f10c 100644
--- a/target/linux/bmips/dts/bcm6328-arcadyan-ar7516.dts
+++ b/target/linux/bmips/dts/bcm6328-arcadyan-ar7516.dts
@@ -117,7 +117,8 @@
 	led@6 {
 		reg = <6>;
 		active-low;
-		label = "green:wan";
+		function = LED_FUNCTION_WAN;
+		color = <LED_COLOR_ID_GREEN>;
 	};
 
 	led@7 {
diff --git a/target/linux/bmips/dts/bcm6328-comtrend-ar-5381u.dts b/target/linux/bmips/dts/bcm6328-comtrend-ar-5381u.dts
index 09e6f99389160c..8864a844e4ac9b 100644
--- a/target/linux/bmips/dts/bcm6328-comtrend-ar-5381u.dts
+++ b/target/linux/bmips/dts/bcm6328-comtrend-ar-5381u.dts
@@ -114,7 +114,8 @@
 	led_alarm_red: led@2 {
 		reg = <2>;
 		active-low;
-		label = "red:alarm";
+		function = LED_FUNCTION_ALARM;
+		color = <LED_COLOR_ID_RED>;
 		panic-indicator;
 	};
 
@@ -127,7 +128,8 @@
 	led_power_green: led@4 {
 		reg = <4>;
 		active-low;
-		label = "green:power";
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_GREEN>;
 	};
 };
 
diff --git a/target/linux/bmips/dts/bcm6328-comtrend-ar-5387un.dts b/target/linux/bmips/dts/bcm6328-comtrend-ar-5387un.dts
index 7ee87c636ec4e4..18be03a248744e 100644
--- a/target/linux/bmips/dts/bcm6328-comtrend-ar-5387un.dts
+++ b/target/linux/bmips/dts/bcm6328-comtrend-ar-5387un.dts
@@ -136,7 +136,8 @@
 
 	led_power_red: led@4 {
 		reg = <4>;
-		label = "red:power";
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_RED>;
 		panic-indicator;
 	};
 
@@ -147,7 +148,8 @@
 
 	led_power_green: led@8 {
 		reg = <8>;
-		label = "green:power";
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_GREEN>;
 	};
 
 	led@11 {
diff --git a/target/linux/bmips/dts/bcm6328-innacomm-w3400v6.dts b/target/linux/bmips/dts/bcm6328-innacomm-w3400v6.dts
index f2f70fcb177919..e7564f2436bbd9 100644
--- a/target/linux/bmips/dts/bcm6328-innacomm-w3400v6.dts
+++ b/target/linux/bmips/dts/bcm6328-innacomm-w3400v6.dts
@@ -129,21 +129,24 @@
 	led_power_green: led@4 {
 		reg = <4>;
 		active-low;
-		label = "green:power";
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_GREEN>;
 		default-state = "on";
 	};
 
 	led_power_red: led@5 {
 		reg = <5>;
 		active-low;
-		label = "red:power";
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_RED>;
 		panic-indicator;
 	};
 
 	led@11 {
 		reg = <11>;
 		active-low;
-		label = "green:wps";
+		function = LED_FUNCTION_WPS;
+		color = <LED_COLOR_ID_GREEN>;
 	};
 };
 
diff --git a/target/linux/bmips/dts/bcm6328-nucom-r5010unv2.dts b/target/linux/bmips/dts/bcm6328-nucom-r5010unv2.dts
index d096a1a42cdf40..56842544cfe708 100644
--- a/target/linux/bmips/dts/bcm6328-nucom-r5010unv2.dts
+++ b/target/linux/bmips/dts/bcm6328-nucom-r5010unv2.dts
@@ -132,26 +132,30 @@
 	led_power_green: led@4 {
 		reg = <4>;
 		active-low;
-		label = "green:power";
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_GREEN>;
 	};
 
 	led_power_red: led@5 {
 		reg = <5>;
 		active-low;
-		label = "red:power";
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_RED>;
 		panic-indicator;
 	};
 
 	led@10 {
 		reg = <10>;
 		active-low;
-		label = "green:wps";
+		function = LED_FUNCTION_WPS;
+		color = <LED_COLOR_ID_GREEN>;
 	};
 
 	led@11 {
 		reg = <11>;
 		active-low;
-		label = "green:usb";
+		function = LED_FUNCTION_USB;
+		color = <LED_COLOR_ID_GREEN>;
 	};
 };
 
diff --git a/target/linux/bmips/dts/bcm6328-sercomm-ad1018.dts b/target/linux/bmips/dts/bcm6328-sercomm-ad1018.dts
index 438f1d5fec9292..669b0d481831d8 100644
--- a/target/linux/bmips/dts/bcm6328-sercomm-ad1018.dts
+++ b/target/linux/bmips/dts/bcm6328-sercomm-ad1018.dts
@@ -107,7 +107,8 @@
 	led_power_green: led@8 {
 		reg = <8>;
 		active-low;
-		label = "green:power";
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_GREEN>;
 		default-state = "on";
 	};
 
@@ -132,7 +133,8 @@
 	led@13 {
 		reg = <13>;
 		active-low;
-		label = "green:wps";
+		function = LED_FUNCTION_WPS;
+		color = <LED_COLOR_ID_GREEN>;
 	};
 
 	led@14 {
@@ -144,7 +146,8 @@
 	led@15 {
 		reg = <15>;
 		active-low;
-		label = "green:usb";
+		function = LED_FUNCTION_USB;
+		color = <LED_COLOR_ID_GREEN>;
 	};
 
 	led@17 {
diff --git a/target/linux/bmips/dts/bcm6328.dtsi b/target/linux/bmips/dts/bcm6328.dtsi
index f45f94f5b86222..52f94950a3faf8 100644
--- a/target/linux/bmips/dts/bcm6328.dtsi
+++ b/target/linux/bmips/dts/bcm6328.dtsi
@@ -7,6 +7,7 @@
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/bcm6328-interrupt-controller.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/reset/bcm6328-reset.h>
 #include <dt-bindings/soc/bcm6328-pm.h>
 
diff --git a/target/linux/bmips/dts/bcm6358-huawei-hg556a-b.dts b/target/linux/bmips/dts/bcm6358-huawei-hg556a-b.dts
index c2693fa7160702..6500d54e360889 100644
--- a/target/linux/bmips/dts/bcm6358-huawei-hg556a-b.dts
+++ b/target/linux/bmips/dts/bcm6358-huawei-hg556a-b.dts
@@ -65,7 +65,8 @@
 		};
 
 		led_power_red: led@3 {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
 		};
 
@@ -120,7 +121,8 @@
 		compatible = "gpio-leds";
 
 		wlan {
-			label = "red:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&ath9k 2 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/bmips/dts/bcm6358.dtsi b/target/linux/bmips/dts/bcm6358.dtsi
index b56ec698ba6574..43dc87c71d2e9a 100644
--- a/target/linux/bmips/dts/bcm6358.dtsi
+++ b/target/linux/bmips/dts/bcm6358.dtsi
@@ -7,6 +7,7 @@
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/bcm6358-interrupt-controller.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/reset/bcm6358-reset.h>
 
 / {
diff --git a/target/linux/bmips/dts/bcm6362-huawei-hg253s-v2.dts b/target/linux/bmips/dts/bcm6362-huawei-hg253s-v2.dts
index 32682b2610e93c..a7498815e3dd10 100644
--- a/target/linux/bmips/dts/bcm6362-huawei-hg253s-v2.dts
+++ b/target/linux/bmips/dts/bcm6362-huawei-hg253s-v2.dts
@@ -47,7 +47,8 @@
 		};
 
 		led@30 {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 30 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/bmips/dts/bcm6362-netgear-dgnd3700-v2.dts b/target/linux/bmips/dts/bcm6362-netgear-dgnd3700-v2.dts
index f7182b78dac6d8..0259fdba6c5d55 100644
--- a/target/linux/bmips/dts/bcm6362-netgear-dgnd3700-v2.dts
+++ b/target/linux/bmips/dts/bcm6362-netgear-dgnd3700-v2.dts
@@ -48,7 +48,8 @@
 		};
 
 		led_power_red: led@34 {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 34 GPIO_ACTIVE_LOW>;
 			panic-indicator;
 		};
@@ -85,13 +86,15 @@
 
 	led_power_green: led@8 {
 		reg = <8>;
-		label = "green:power";
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_GREEN>;
 	};
 
 	led@9 {
 		reg = <9>;
 		active-low;
-		label = "green:wps";
+		function = LED_FUNCTION_WPS;
+		color = <LED_COLOR_ID_GREEN>;
 	};
 
 	led@10 {
diff --git a/target/linux/bmips/dts/bcm6362.dtsi b/target/linux/bmips/dts/bcm6362.dtsi
index e615eaf8b3b230..1089d89350baa5 100644
--- a/target/linux/bmips/dts/bcm6362.dtsi
+++ b/target/linux/bmips/dts/bcm6362.dtsi
@@ -7,6 +7,7 @@
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/bcm6362-interrupt-controller.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/reset/bcm6362-reset.h>
 #include <dt-bindings/soc/bcm6362-pm.h>
 
diff --git a/target/linux/bmips/dts/bcm6368-actiontec-r1000h.dts b/target/linux/bmips/dts/bcm6368-actiontec-r1000h.dts
index fec67d0db98eb9..5951ad854c49ae 100644
--- a/target/linux/bmips/dts/bcm6368-actiontec-r1000h.dts
+++ b/target/linux/bmips/dts/bcm6368-actiontec-r1000h.dts
@@ -36,38 +36,45 @@
 		compatible = "gpio-leds";
 
 		led@5 {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
 		};
 
 		led@21 {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_green: led@22 {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
 		};
 
 		led@23 {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_red: led@24 {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
 			panic-indicator;
 		};
 
 		led@30 {
-			label = "red:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 30 GPIO_ACTIVE_LOW>;
 		};
 
 		led@31 {
-			label = "red:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 31 GPIO_ACTIVE_HIGH>;
 		};
 	};
diff --git a/target/linux/bmips/dts/bcm6368-comtrend-vr-3025u.dts b/target/linux/bmips/dts/bcm6368-comtrend-vr-3025u.dts
index 63a07fe70e3a56..647db7afaa7314 100644
--- a/target/linux/bmips/dts/bcm6368-comtrend-vr-3025u.dts
+++ b/target/linux/bmips/dts/bcm6368-comtrend-vr-3025u.dts
@@ -39,12 +39,14 @@
 		};
 
 		led_power_green: led@22 {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_power_red: led@24 {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
 			panic-indicator;
 		};
diff --git a/target/linux/bmips/dts/bcm6368-comtrend-vr-3025un.dts b/target/linux/bmips/dts/bcm6368-comtrend-vr-3025un.dts
index 937fbdd1a1d7ca..ba75cb3e5c623d 100644
--- a/target/linux/bmips/dts/bcm6368-comtrend-vr-3025un.dts
+++ b/target/linux/bmips/dts/bcm6368-comtrend-vr-3025un.dts
@@ -39,12 +39,14 @@
 		};
 
 		led_power_green: led@22 {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_power_red: led@24 {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
 			panic-indicator;
 		};
diff --git a/target/linux/bmips/dts/bcm6368-netgear-dgnd3700.dtsi b/target/linux/bmips/dts/bcm6368-netgear-dgnd3700.dtsi
index c647559d6ce57a..49c546692a60b4 100644
--- a/target/linux/bmips/dts/bcm6368-netgear-dgnd3700.dtsi
+++ b/target/linux/bmips/dts/bcm6368-netgear-dgnd3700.dtsi
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later
 
+#include <dt-bindings/leds/common.h>
+
 #include "bcm6368.dtsi"
 
 / {
@@ -45,17 +47,20 @@
 		};
 
 		led@4 {
-			label = "red:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
 		};
 
 		led@5 {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
 		};
 
 		led@11 {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 		};
 
@@ -72,18 +77,21 @@
 		};
 
 		led_power_red: led@22 {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
 			panic-indicator;
 		};
 
 		led@23 {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_green: led@24 {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 24 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/bmips/dts/bcm6368-observa-vh4032n.dts b/target/linux/bmips/dts/bcm6368-observa-vh4032n.dts
index 0f74c4b902df0c..3268ff146fee28 100644
--- a/target/linux/bmips/dts/bcm6368-observa-vh4032n.dts
+++ b/target/linux/bmips/dts/bcm6368-observa-vh4032n.dts
@@ -56,12 +56,14 @@
 		};
 
 		led_power_blue: led@22 {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_power_red: led@24 {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
 			panic-indicator;
 		};
diff --git a/target/linux/bmips/dts/bcm6368.dtsi b/target/linux/bmips/dts/bcm6368.dtsi
index 0ac1269166bda0..cf2f5b081b9d15 100644
--- a/target/linux/bmips/dts/bcm6368.dtsi
+++ b/target/linux/bmips/dts/bcm6368.dtsi
@@ -7,6 +7,7 @@
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/bcm6368-interrupt-controller.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/reset/bcm6368-reset.h>
 
 / {
diff --git a/target/linux/bmips/dts/bcm6369-comtrend-wap-5813n.dts b/target/linux/bmips/dts/bcm6369-comtrend-wap-5813n.dts
index 70572b49a91a06..263a10bf61506b 100644
--- a/target/linux/bmips/dts/bcm6369-comtrend-wap-5813n.dts
+++ b/target/linux/bmips/dts/bcm6369-comtrend-wap-5813n.dts
@@ -48,22 +48,26 @@
 		};
 
 		led@14 {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_green: led@22 {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
 		};
 
 		led@23 {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_red: led@24 {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
 			panic-indicator;
 		};
diff --git a/target/linux/bmips/dts/bcm6369-netgear-evg2000.dts b/target/linux/bmips/dts/bcm6369-netgear-evg2000.dts
index 00017238c852ae..376f5b6865e230 100644
--- a/target/linux/bmips/dts/bcm6369-netgear-evg2000.dts
+++ b/target/linux/bmips/dts/bcm6369-netgear-evg2000.dts
@@ -56,28 +56,33 @@
 		};
 
 		led@15 {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_green: led@22 {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_red: led@23 {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
 			panic-indicator;
 		};
 
 		led@24 {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 24 GPIO_ACTIVE_LOW>;
 		};
 
 		led@27 {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 27 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/bmips/patches-6.1/700-leds-add-support-for-Sercomm-MSP430-LED-controller.patch b/target/linux/bmips/patches-6.1/700-leds-add-support-for-Sercomm-MSP430-LED-controller.patch
index adcb01ec295f91..763e25ba03c8c8 100644
--- a/target/linux/bmips/patches-6.1/700-leds-add-support-for-Sercomm-MSP430-LED-controller.patch
+++ b/target/linux/bmips/patches-6.1/700-leds-add-support-for-Sercomm-MSP430-LED-controller.patch
@@ -17,7 +17,7 @@ Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
 
 --- a/drivers/leds/Kconfig
 +++ b/drivers/leds/Kconfig
-@@ -282,6 +282,15 @@ config LEDS_COBALT_RAQ
+@@ -283,6 +283,15 @@ config LEDS_COBALT_RAQ
  	help
  	  This option enables support for the Cobalt Raq series LEDs.
  
diff --git a/target/linux/d1/Makefile b/target/linux/d1/Makefile
new file mode 100644
index 00000000000000..436ab948623310
--- /dev/null
+++ b/target/linux/d1/Makefile
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Copyright (C) 2024 Toco Technologies <info@toco.ae>
+#
+include $(TOPDIR)/rules.mk
+
+ARCH:=riscv64
+BOARD:=d1
+BOARDNAME:=AllWinner D1 RISC-V SoC
+FEATURES:=ext4 squashfs
+KERNELNAME:=Image dtbs
+
+KERNEL_PATCHVER:=6.1
+
+include $(INCLUDE_DIR)/target.mk
+
+define Target/Description
+	Build firmware images for Allwinner D1 RISC-V boards
+endef
+
+$(eval $(call BuildTarget))
diff --git a/target/linux/d1/base-files/etc/board.d/02_network b/target/linux/d1/base-files/etc/board.d/02_network
new file mode 100644
index 00000000000000..df48b431af5e2c
--- /dev/null
+++ b/target/linux/d1/base-files/etc/board.d/02_network
@@ -0,0 +1,18 @@
+#!/bin/sh
+#
+# Copyright (C) 2013-2015 OpenWrt.org
+#
+
+. /lib/functions/uci-defaults.sh
+
+board_config_update
+
+case "$(board_name)" in
+*)
+	ucidef_set_interface_lan 'eth0'
+	;;
+esac
+
+board_config_flush
+
+exit 0
diff --git a/target/linux/d1/base-files/etc/inittab b/target/linux/d1/base-files/etc/inittab
new file mode 100644
index 00000000000000..be81ab3e23879f
--- /dev/null
+++ b/target/linux/d1/base-files/etc/inittab
@@ -0,0 +1,5 @@
+::sysinit:/etc/init.d/rcS S boot
+::shutdown:/etc/init.d/rcS K shutdown
+tts/0::askfirst:/usr/libexec/login.sh
+ttyS0::askfirst:/usr/libexec/login.sh
+tty1::askfirst:/usr/libexec/login.sh
diff --git a/target/linux/d1/config-6.1 b/target/linux/d1/config-6.1
new file mode 100644
index 00000000000000..ef2112f706d0cd
--- /dev/null
+++ b/target/linux/d1/config-6.1
@@ -0,0 +1,396 @@
+CONFIG_64BIT=y
+# CONFIG_AHCI_SUNXI is not set
+CONFIG_ARCH_CLOCKSOURCE_INIT=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_ARCH_MMAP_RND_BITS=18
+CONFIG_ARCH_MMAP_RND_BITS_MAX=24
+CONFIG_ARCH_MMAP_RND_BITS_MIN=18
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=17
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
+CONFIG_ARCH_RV64I=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_ARCH_WANTS_THP_SWAP=y
+CONFIG_ASN1=y
+CONFIG_ASSOCIATIVE_ARRAY=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CLZ_TAB=y
+CONFIG_CMODEL_MEDANY=y
+# CONFIG_CMODEL_MEDLOW is not set
+CONFIG_COMMON_CLK=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+# CONFIG_COMPAT_32BIT_TIME is not set
+CONFIG_COMPAT_BRK=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_COREDUMP=y
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+CONFIG_CPU_ISOLATION=y
+CONFIG_CPU_RMAP=y
+CONFIG_CRC16=y
+# CONFIG_CRC32_SARWATE is not set
+CONFIG_CRC32_SLICEBY8=y
+CONFIG_CRC7=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRYPTO_DEV_ALLWINNER=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DMADEVICES=y
+CONFIG_DMA_DIRECT_REMAP=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_SUN6I=y
+CONFIG_DMA_VIRTUAL_CHANNELS=y
+CONFIG_DTC=y
+CONFIG_DWMAC_GENERIC=y
+CONFIG_DWMAC_SUN8I=y
+CONFIG_DWMAC_SUNXI=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EFI=y
+CONFIG_EFIVAR_FS=m
+# CONFIG_EFI_BOOTLOADER_CONTROL is not set
+# CONFIG_EFI_CAPSULE_LOADER is not set
+# CONFIG_EFI_COCO_SECRET is not set
+# CONFIG_EFI_DISABLE_PCI_DMA is not set
+# CONFIG_EFI_DISABLE_RUNTIME is not set
+CONFIG_EFI_EARLYCON=y
+CONFIG_EFI_ESRT=y
+CONFIG_EFI_GENERIC_STUB=y
+CONFIG_EFI_PARAMS_FROM_FDT=y
+CONFIG_EFI_RUNTIME_WRAPPERS=y
+CONFIG_EFI_STUB=y
+# CONFIG_EFI_TEST is not set
+# CONFIG_EFI_ZBOOT is not set
+CONFIG_ELF_CORE=y
+# CONFIG_ERRATA_SIFIVE is not set
+CONFIG_ERRATA_THEAD=y
+CONFIG_ERRATA_THEAD_CMO=y
+CONFIG_ERRATA_THEAD_PBMT=y
+CONFIG_EXT4_FS=y
+CONFIG_EXTCON=y
+CONFIG_FAILOVER=y
+CONFIG_FHANDLE=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FONT_8x16=y
+CONFIG_FONT_AUTOSELECT=y
+CONFIG_FONT_SUPPORT=y
+CONFIG_FPU=y
+CONFIG_FRAME_POINTER=y
+CONFIG_FRAME_WARN=2048
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IOREMAP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GLOB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_PCF857X=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HID=y
+CONFIG_HID_GENERIC=y
+CONFIG_HVC_DRIVER=y
+CONFIG_HVC_RISCV_SBI=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_MV64XXX=y
+CONFIG_I2C_OCORES=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INPUT=y
+CONFIG_IOMMU_API=y
+# CONFIG_IOMMU_DEBUGFS is not set
+# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
+CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
+# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
+CONFIG_IOMMU_SUPPORT=y
+CONFIG_IO_URING=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+CONFIG_JBD2=y
+CONFIG_KALLSYMS=y
+# CONFIG_KEYBOARD_SUN4I_LRADC is not set
+# CONFIG_LEDS_PWM_MULTICOLOR is not set
+# CONFIG_LEDS_SUN50I_A100 is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+CONFIG_LIBFDT=y
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_MAILBOX=y
+# CONFIG_MAILBOX_TEST is not set
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_BUS_MUX=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+# CONFIG_MDIO_SUN4I is not set
+CONFIG_MEMFD_CREATE=y
+CONFIG_MFD_AXP20X=y
+CONFIG_MFD_AXP20X_I2C=y
+CONFIG_MFD_CORE=y
+# CONFIG_MFD_SUN4I_GPADC is not set
+CONFIG_MFD_SUN6I_PRCM=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_SUNXI=y
+CONFIG_MMIOWB=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
+# CONFIG_MUSB_PIO_ONLY is not set
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_VENDOR_ALLWINNER=y
+CONFIG_NLS=y
+# CONFIG_NONPORTABLE is not set
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_NR_CPUS=8
+CONFIG_NVMEM=y
+CONFIG_NVMEM_SUNXI_SID=y
+CONFIG_NVMEM_SYSFS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_DMA_DEFAULT_COHERENT=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IOMMU=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OID_REGISTRY=y
+CONFIG_PADATA=y
+CONFIG_PAGE_OFFSET=0xff60000000000000
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+# CONFIG_PAGE_TABLE_CHECK is not set
+CONFIG_PANIC_TIMEOUT=0
+CONFIG_PCPU_DEV_REFCNT=y
+CONFIG_PGTABLE_LEVELS=5
+CONFIG_PHYLIB=y
+CONFIG_PHYLINK=y
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_PHY_SUN4I_USB=y
+CONFIG_PHY_SUN50I_USB3=y
+# CONFIG_PHY_SUN6I_MIPI_DPHY is not set
+# CONFIG_PHY_SUN9I_USB is not set
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_SUN20I_D1=y
+# CONFIG_PINCTRL_SUN4I_A10 is not set
+# CONFIG_PINCTRL_SUN50I_A100 is not set
+# CONFIG_PINCTRL_SUN50I_A100_R is not set
+# CONFIG_PINCTRL_SUN50I_A64 is not set
+# CONFIG_PINCTRL_SUN50I_A64_R is not set
+# CONFIG_PINCTRL_SUN50I_H5 is not set
+# CONFIG_PINCTRL_SUN50I_H6 is not set
+# CONFIG_PINCTRL_SUN50I_H616 is not set
+# CONFIG_PINCTRL_SUN50I_H616_R is not set
+# CONFIG_PINCTRL_SUN50I_H6_R is not set
+# CONFIG_PINCTRL_SUN5I is not set
+# CONFIG_PINCTRL_SUN6I_A31 is not set
+# CONFIG_PINCTRL_SUN6I_A31_R is not set
+# CONFIG_PINCTRL_SUN8I_A23 is not set
+# CONFIG_PINCTRL_SUN8I_A23_R is not set
+# CONFIG_PINCTRL_SUN8I_A33 is not set
+# CONFIG_PINCTRL_SUN8I_A83T is not set
+# CONFIG_PINCTRL_SUN8I_A83T_R is not set
+# CONFIG_PINCTRL_SUN8I_H3 is not set
+# CONFIG_PINCTRL_SUN8I_H3_R is not set
+# CONFIG_PINCTRL_SUN8I_V3S is not set
+# CONFIG_PINCTRL_SUN9I_A80 is not set
+# CONFIG_PINCTRL_SUN9I_A80_R is not set
+CONFIG_PINCTRL_SUNXI=y
+CONFIG_PORTABLE=y
+CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_POWER_RESET_SYSCON_POWEROFF=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PPS=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PRINTK_TIME=y
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_PWM=y
+# CONFIG_PWM_CLK is not set
+# CONFIG_PWM_SIFIVE is not set
+# CONFIG_PWM_SUN4I is not set
+# CONFIG_PWM_SUN8I_V536 is not set
+CONFIG_PWM_SYSFS=y
+# CONFIG_PWM_XILINX is not set
+CONFIG_RATIONAL=y
+CONFIG_RCU_TRACE=y
+CONFIG_REALTEK_PHY=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_IRQ=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGULATOR=y
+# CONFIG_REGULATOR_AXP20X is not set
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_SUN20I=y
+# CONFIG_RESET_ATTACK_MITIGATION is not set
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RESET_SIMPLE=y
+CONFIG_RESET_SUNXI=y
+CONFIG_RISCV=y
+CONFIG_RISCV_ALTERNATIVE=y
+CONFIG_RISCV_ALTERNATIVE_EARLY=y
+CONFIG_RISCV_BOOT_SPINWAIT=y
+CONFIG_RISCV_DMA_NONCOHERENT=y
+CONFIG_RISCV_INTC=y
+CONFIG_RISCV_ISA_C=y
+CONFIG_RISCV_ISA_SVPBMT=y
+CONFIG_RISCV_ISA_ZICBOM=y
+CONFIG_RISCV_SBI=y
+CONFIG_RISCV_SBI_V01=y
+CONFIG_RISCV_TIMER=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_DRV_EFI is not set
+CONFIG_RTC_DRV_GOLDFISH=y
+CONFIG_RTC_DRV_SUN6I=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_SCHED_DEBUG=y
+CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_8250_DWLIB=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SG_POOL=y
+CONFIG_SIFIVE_PLIC=y
+CONFIG_SLUB_DEBUG=y
+CONFIG_SMP=y
+# CONFIG_SND_SUN20I_CODEC is not set
+# CONFIG_SND_SUN4I_I2S is not set
+# CONFIG_SND_SUN50I_DMIC is not set
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+# CONFIG_SOC_MICROCHIP_POLARFIRE is not set
+# CONFIG_SOC_SIFIVE is not set
+# CONFIG_SOC_STARFIVE is not set
+# CONFIG_SOC_VIRT is not set
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+# CONFIG_SPI_SUN4I is not set
+CONFIG_SPI_SUN6I=y
+CONFIG_SRCU=y
+CONFIG_STACKDEPOT=y
+CONFIG_STACKTRACE=y
+CONFIG_STMMAC_ETH=y
+CONFIG_STMMAC_PLATFORM=y
+CONFIG_SUN20I_D1_CCU=y
+CONFIG_SUN20I_D1_R_CCU=y
+# CONFIG_SUN4I_EMAC is not set
+CONFIG_SUN4I_TIMER=y
+CONFIG_SUN50I_IOMMU=y
+CONFIG_SUN6I_MSGBOX=y
+CONFIG_SUN6I_RTC_CCU=y
+CONFIG_SUN8I_DE2_CCU=y
+# CONFIG_SUN8I_R_CCU is not set
+# CONFIG_SUN8I_THERMAL is not set
+CONFIG_SUNXI_CCU=y
+# CONFIG_SUNXI_RSB is not set
+CONFIG_SUNXI_SRAM=y
+CONFIG_SUNXI_WATCHDOG=y
+CONFIG_SWIOTLB=y
+CONFIG_SWPHY=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+# CONFIG_SYSFB_SIMPLEFB is not set
+CONFIG_SYSFS_SYSCALL=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TOOLCHAIN_HAS_ZICBOM=y
+CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE=y
+CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI=y
+CONFIG_TRACE_CLOCK=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_TUNE_GENERIC=y
+# CONFIG_UACCE is not set
+CONFIG_UCS2_STRING=y
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_HID=y
+CONFIG_USB_MUSB_HDRC=y
+CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_SUNXI=y
+CONFIG_USB_NET_DRIVERS=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_PHY=y
+CONFIG_USB_SUPPORT=y
+# CONFIG_USB_UHCI_HCD is not set
+CONFIG_USB_XHCI_HCD=y
+# CONFIG_USB_XHCI_PLATFORM is not set
+CONFIG_VGA_ARB=y
+CONFIG_VGA_ARB_MAX_GPUS=16
+# CONFIG_VHOST_MENU is not set
+# CONFIG_VIRTIO_MENU is not set
+CONFIG_VMAP_STACK=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_XPS=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZONE_DMA32=y
diff --git a/target/linux/d1/image/Config.in b/target/linux/d1/image/Config.in
new file mode 100644
index 00000000000000..92169c8eb2b9f7
--- /dev/null
+++ b/target/linux/d1/image/Config.in
@@ -0,0 +1,5 @@
+config D1_SD_BOOT_PARTSIZE
+	int "Boot (SD Card) filesystem partition size (in MB)"
+	depends on TARGET_d1
+	default 32
+
diff --git a/target/linux/d1/image/Makefile b/target/linux/d1/image/Makefile
new file mode 100644
index 00000000000000..aadf1807e751af
--- /dev/null
+++ b/target/linux/d1/image/Makefile
@@ -0,0 +1,94 @@
+#
+# Copyright (C) 2023 OpenWrt.org
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+include $(TOPDIR)/rules.mk
+include $(INCLUDE_DIR)/image.mk
+
+FAT32_BLOCK_SIZE=1024
+FAT32_BLOCKS=$(shell echo $$(($(CONFIG_D1_SD_BOOT_PARTSIZE)*1024*1024/$(FAT32_BLOCK_SIZE))))
+
+KERNEL_LOADADDR:=0x40200000
+
+define Build/riscv-sdcard
+	rm -f $@.boot #$(KDIR_TMP)/$(IMG_PREFIX)-$(PROFILE)-boot.img
+	mkfs.fat $@.boot  -C $(FAT32_BLOCKS)
+
+	mcopy -i $@.boot $(STAGING_DIR_IMAGE)/$(DEVICE_NAME)-boot.scr ::boot.scr
+	mcopy -i $@.boot $(DTS_DIR)/$(DEVICE_DTS).dtb ::dtb
+	mcopy -i $@.boot $(IMAGE_KERNEL) ::Image
+
+	./gen_d1_sdcard_img.sh \
+		$@ \
+		$@.boot \
+		$(IMAGE_ROOTFS) \
+		$(CONFIG_D1_SD_BOOT_PARTSIZE) \
+		$(CONFIG_TARGET_ROOTFS_PARTSIZE) \
+		$(STAGING_DIR_IMAGE)/$(DEVICE_NAME)-u-boot-sunxi-with-spl.bin
+endef
+
+define Device/Default
+  PROFILES := Default
+  KERNEL_NAME := Image
+  KERNEL := kernel-bin
+  IMAGES := sdcard.img.gz
+  IMAGE/sdcard.img.gz := riscv-sdcard | append-metadata | gzip
+endef
+
+define Device/FitImageGzip
+	KERNEL_SUFFIX := -fit-uImage.itb
+	KERNEL = kernel-bin | gzip | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb
+	KERNEL_NAME := Image
+endef
+
+define Device/FitImage
+	KERNEL_SUFFIX := -fit-uImage.itb
+	KERNEL = kernel-bin | fit none $$(DTS_DIR)/$$(DEVICE_DTS).dtb
+	KERNEL_NAME := Image
+endef
+
+define Device/dongshan_nezha_stu
+  $(call Device/Default)
+  DEVICE_VENDOR := Dongshan
+  DEVICE_MODEL := Nezha STU devkit
+  DEVICE_DTS := allwinner/sun20i-d1-dongshan-nezha-stu
+  UBOOT := dongshan_nezha_stu
+endef
+TARGET_DEVICES += dongshan_nezha_stu
+
+define Device/lichee_rv_dock
+  $(call Device/Default)
+  DEVICE_VENDOR := Sipeed
+  DEVICE_MODEL := LicheePi RV (dock)
+  DEVICE_DTS := allwinner/sun20i-d1-lichee-rv-dock
+  DEVICE_PACKAGES += kmod-rtl8723bs
+  UBOOT := lichee_rv_dock
+endef
+TARGET_DEVICES += lichee_rv_dock
+
+define Device/mangopi_mq_pro
+  $(call Device/Default)
+  DEVICE_VENDOR := MangoPi
+  DEVICE_MODEL := MQ Pro
+  DEVICE_DTS := allwinner/sun20i-d1-mangopi-mq-pro
+  DEVICE_PACKAGES += kmod-rtl8723bs
+  UBOOT := mangopi_mq_pro
+endef
+TARGET_DEVICES += mangopi_mq_pro
+
+define Device/nezha
+  $(call Device/Default)
+  DEVICE_VENDOR := Nezha
+  DEVICE_MODEL := D1
+  DEVICE_DTS := allwinner/sun20i-d1-nezha
+  UBOOT := nezha
+endef
+TARGET_DEVICES += nezha
+
+define Image/Build
+	$(call Image/Build/$(1),$(1))
+endef
+
+$(eval $(call BuildImage))
diff --git a/target/linux/d1/image/gen_d1_sdcard_img.sh b/target/linux/d1/image/gen_d1_sdcard_img.sh
new file mode 100755
index 00000000000000..197eea7a20d147
--- /dev/null
+++ b/target/linux/d1/image/gen_d1_sdcard_img.sh
@@ -0,0 +1,33 @@
+#!/bin/sh
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Copyright (C) 2013 OpenWrt.org
+
+set -ex
+[ $# -eq 6 ] || {
+    echo "SYNTAX: $0 <file> <bootfs image> <rootfs image> <bootfs size> <rootfs size> <u-boot image>"
+    exit 1
+}
+
+OUTPUT="$1"
+BOOTFS="$2"
+ROOTFS="$3"
+BOOTFSSIZE="$4"
+ROOTFSSIZE="$5"
+UBOOT="$6"
+
+ROOTFSPTOFFSET=$(($BOOTFSSIZE + 20 + 1))
+
+head=4
+sect=63
+
+set $(ptgen -o $OUTPUT -h $head -s $sect -l 1024 -t c -p ${BOOTFSSIZE}M@20M -t 83 -p ${ROOTFSSIZE}M@${ROOTFSPTOFFSET}M)
+
+BOOTOFFSET="$(($1 / 512))"
+BOOTSIZE="$(($2 / 512))"
+ROOTFSOFFSET="$(($3 / 512))"
+ROOTFSSIZE="$(($4 / 512))"
+
+dd bs=512 if="$UBOOT" of="$OUTPUT" seek=256 conv=notrunc
+dd bs=512 if="$BOOTFS" of="$OUTPUT" seek="$BOOTOFFSET" conv=notrunc
+dd bs=512 if="$ROOTFS" of="$OUTPUT" seek="$ROOTFSOFFSET" conv=notrunc
diff --git a/target/linux/d1/patches-6.1/0001-dt-bindings-net-bluetooth-realtek-Add-RTL8723DS.patch b/target/linux/d1/patches-6.1/0001-dt-bindings-net-bluetooth-realtek-Add-RTL8723DS.patch
new file mode 100644
index 00000000000000..6636cddde6beb1
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0001-dt-bindings-net-bluetooth-realtek-Add-RTL8723DS.patch
@@ -0,0 +1,32 @@
+From e663d510ae6a81694a8e9e1ce07bb80dd6b77558 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 24 Jul 2022 17:12:07 -0500
+Subject: [PATCH 001/117] dt-bindings: net: bluetooth: realtek: Add RTL8723DS
+
+RTL8723DS is another version of the RTL8723 WiFi + Bluetooth chip. It is
+already supported by the hci_uart/btrtl driver. Document the compatible.
+
+Series-to: Marcel Holtmann <marcel@holtmann.org>
+Series-to: Johan Hedberg <johan.hedberg@gmail.com>
+Series-to: Luiz Augusto von Dentz <luiz.dentz@gmail.com>
+Series-to: David S. Miller <davem@davemloft.net>
+Series-to: Eric Dumazet <edumazet@google.com>
+Series-to: Jakub Kicinski <kuba@kernel.org>
+Series-to: Paolo Abeni <pabeni@redhat.com>
+Series-cc: linux-bluetooth@vger.kernel.org
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ Documentation/devicetree/bindings/net/realtek-bluetooth.yaml | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/Documentation/devicetree/bindings/net/realtek-bluetooth.yaml
++++ b/Documentation/devicetree/bindings/net/realtek-bluetooth.yaml
+@@ -20,6 +20,7 @@ properties:
+     enum:
+       - realtek,rtl8723bs-bt
+       - realtek,rtl8723cs-bt
++      - realtek,rtl8723ds-bt
+       - realtek,rtl8822cs-bt
+ 
+   device-wake-gpios:
diff --git a/target/linux/d1/patches-6.1/0002-clk-sunxi-ng-mp-Avoid-computing-the-rate-twice.patch b/target/linux/d1/patches-6.1/0002-clk-sunxi-ng-mp-Avoid-computing-the-rate-twice.patch
new file mode 100644
index 00000000000000..22d4885e291f1a
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0002-clk-sunxi-ng-mp-Avoid-computing-the-rate-twice.patch
@@ -0,0 +1,51 @@
+From 74492b9ecd874496578693d9985649665b560308 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 7 Aug 2022 20:08:49 -0500
+Subject: [PATCH 002/117] clk: sunxi-ng: mp: Avoid computing the rate twice
+
+ccu_mp_find_best() already computes a best_rate at the same time as the
+best m and p factors. Return it so the caller does not need to duplicate
+the division.
+
+Series-to: Chen-Yu Tsai <wens@csie.org>
+Series-to: Jernej Skrabec <jernej.skrabec@gmail.com>
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/clk/sunxi-ng/ccu_mp.c | 11 ++++++-----
+ 1 file changed, 6 insertions(+), 5 deletions(-)
+
+--- a/drivers/clk/sunxi-ng/ccu_mp.c
++++ b/drivers/clk/sunxi-ng/ccu_mp.c
+@@ -10,9 +10,9 @@
+ #include "ccu_gate.h"
+ #include "ccu_mp.h"
+ 
+-static void ccu_mp_find_best(unsigned long parent, unsigned long rate,
+-			     unsigned int max_m, unsigned int max_p,
+-			     unsigned int *m, unsigned int *p)
++static unsigned long ccu_mp_find_best(unsigned long parent, unsigned long rate,
++				      unsigned int max_m, unsigned int max_p,
++				      unsigned int *m, unsigned int *p)
+ {
+ 	unsigned long best_rate = 0;
+ 	unsigned int best_m = 0, best_p = 0;
+@@ -35,6 +35,8 @@ static void ccu_mp_find_best(unsigned lo
+ 
+ 	*m = best_m;
+ 	*p = best_p;
++
++	return best_rate;
+ }
+ 
+ static unsigned long ccu_mp_find_best_with_parent_adj(struct clk_hw *hw,
+@@ -109,8 +111,7 @@ static unsigned long ccu_mp_round_rate(s
+ 	max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1);
+ 
+ 	if (!clk_hw_can_set_rate_parent(&cmp->common.hw)) {
+-		ccu_mp_find_best(*parent_rate, rate, max_m, max_p, &m, &p);
+-		rate = *parent_rate / p / m;
++		rate = ccu_mp_find_best(*parent_rate, rate, max_m, max_p, &m, &p);
+ 	} else {
+ 		rate = ccu_mp_find_best_with_parent_adj(hw, parent_rate, rate,
+ 							max_m, max_p);
diff --git a/target/linux/d1/patches-6.1/0003-dt-bindings-net-sun8i-emac-Add-phy-supply-property.patch b/target/linux/d1/patches-6.1/0003-dt-bindings-net-sun8i-emac-Add-phy-supply-property.patch
new file mode 100644
index 00000000000000..ec3f553b51b579
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0003-dt-bindings-net-sun8i-emac-Add-phy-supply-property.patch
@@ -0,0 +1,22 @@
+From 7185f7b424dfd9082bf0859a60b98a2dbd784ed6 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Mon, 5 Sep 2022 16:45:44 -0500
+Subject: [PATCH 003/117] dt-bindings: net: sun8i-emac: Add phy-supply property
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ .../devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml     | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
++++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
+@@ -40,6 +40,9 @@ properties:
+   clock-names:
+     const: stmmaceth
+ 
++  phy-supply:
++    description: PHY regulator
++
+   syscon:
+     $ref: /schemas/types.yaml#/definitions/phandle
+     description:
diff --git a/target/linux/d1/patches-6.1/0004-dt-bindings-net-sun8i-emac-Add-properties-from-dwmac.patch b/target/linux/d1/patches-6.1/0004-dt-bindings-net-sun8i-emac-Add-properties-from-dwmac.patch
new file mode 100644
index 00000000000000..9ac335ae3e0488
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0004-dt-bindings-net-sun8i-emac-Add-properties-from-dwmac.patch
@@ -0,0 +1,32 @@
+From d20bb97fac77e4d88424043627c769427fc0d35e Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Mon, 5 Sep 2022 16:46:34 -0500
+Subject: [PATCH 004/117] dt-bindings: net: sun8i-emac: Add properties from
+ dwmac binding
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ .../devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml   | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
++++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
+@@ -40,6 +40,9 @@ properties:
+   clock-names:
+     const: stmmaceth
+ 
++  resets: true
++  reset-names: true
++
+   phy-supply:
+     description: PHY regulator
+ 
+@@ -49,6 +52,8 @@ properties:
+       Phandle to the device containing the EMAC or GMAC clock
+       register
+ 
++  mdio: true
++
+ required:
+   - compatible
+   - reg
diff --git a/target/linux/d1/patches-6.1/0005-dt-bindings-display-sun8i-a83t-dw-hdmi-Remove-phy-ce.patch b/target/linux/d1/patches-6.1/0005-dt-bindings-display-sun8i-a83t-dw-hdmi-Remove-phy-ce.patch
new file mode 100644
index 00000000000000..402f291674bfff
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0005-dt-bindings-display-sun8i-a83t-dw-hdmi-Remove-phy-ce.patch
@@ -0,0 +1,28 @@
+From c99d1e681dc460892004054a314fa7f929f43490 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 13 Aug 2022 10:45:59 -0500
+Subject: [PATCH 005/117] dt-bindings: display: sun8i-a83t-dw-hdmi: Remove
+ #phy-cells
+
+This device is not a PHY, and none of the nodes using this schema
+contain a #phy-cells property. Likely this was a copy/paste error
+introduced during the YAML conversion.
+
+Fixes: f5a98bfe7b37 ("dt-bindings: display: Convert Allwinner display pipeline to schemas")
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ .../bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml         | 3 ---
+ 1 file changed, 3 deletions(-)
+
+--- a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml
++++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml
+@@ -20,9 +20,6 @@ maintainers:
+   - Maxime Ripard <mripard@kernel.org>
+ 
+ properties:
+-  "#phy-cells":
+-    const: 0
+-
+   compatible:
+     oneOf:
+       - const: allwinner,sun8i-a83t-dw-hdmi
diff --git a/target/linux/d1/patches-6.1/0006-dt-bindings-display-Add-D1-HDMI-compatibles.patch b/target/linux/d1/patches-6.1/0006-dt-bindings-display-Add-D1-HDMI-compatibles.patch
new file mode 100644
index 00000000000000..b62e45c09f8ae1
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0006-dt-bindings-display-Add-D1-HDMI-compatibles.patch
@@ -0,0 +1,34 @@
+From e214b79d45cccdd0cfe839e54da2b3c82b6c6be4 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Thu, 31 Mar 2022 23:43:15 -0500
+Subject: [PATCH 006/117] dt-bindings: display: Add D1 HDMI compatibles
+
+Allwinner D1 contains a DesignWare HDMI controller with some changes in
+platform integration, and a new HDMI PHY. Add their compatibles.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ .../bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml           | 1 +
+ .../bindings/display/allwinner,sun8i-a83t-hdmi-phy.yaml          | 1 +
+ 2 files changed, 2 insertions(+)
+
+--- a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml
++++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml
+@@ -29,6 +29,7 @@ properties:
+           - enum:
+               - allwinner,sun8i-h3-dw-hdmi
+               - allwinner,sun8i-r40-dw-hdmi
++              - allwinner,sun20i-d1-dw-hdmi
+               - allwinner,sun50i-a64-dw-hdmi
+           - const: allwinner,sun8i-a83t-dw-hdmi
+ 
+--- a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-hdmi-phy.yaml
++++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-hdmi-phy.yaml
+@@ -19,6 +19,7 @@ properties:
+       - allwinner,sun8i-a83t-hdmi-phy
+       - allwinner,sun8i-h3-hdmi-phy
+       - allwinner,sun8i-r40-hdmi-phy
++      - allwinner,sun20i-d1-hdmi-phy
+       - allwinner,sun50i-a64-hdmi-phy
+       - allwinner,sun50i-h6-hdmi-phy
+ 
diff --git a/target/linux/d1/patches-6.1/0007-drm-sun4i-Add-support-for-D1-HDMI.patch b/target/linux/d1/patches-6.1/0007-drm-sun4i-Add-support-for-D1-HDMI.patch
new file mode 100644
index 00000000000000..b55c3a3f20d941
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0007-drm-sun4i-Add-support-for-D1-HDMI.patch
@@ -0,0 +1,52 @@
+From 75dc74ecc1bf5e270659c6c78877053b50e6ae19 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Wed, 30 Mar 2022 21:24:21 -0500
+Subject: [PATCH 007/117] drm/sun4i: Add support for D1 HDMI
+
+D1's HDMI controller contains some platform integration changes.
+It now has no external TMDS clock. The controller also supports HDCP
+without an external clock or reset.
+
+While the maximum HDMI frequency is not explicity stated, the BSP PHY
+driver provides PLL configurations only up to 297 MHz, so use that as
+the max frequency.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 11 ++++++++++-
+ 1 file changed, 10 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
++++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
+@@ -133,7 +133,7 @@ static int sun8i_dw_hdmi_bind(struct dev
+ 		return dev_err_probe(dev, PTR_ERR(hdmi->rst_ctrl),
+ 				     "Could not get ctrl reset control\n");
+ 
+-	hdmi->clk_tmds = devm_clk_get(dev, "tmds");
++	hdmi->clk_tmds = devm_clk_get_optional(dev, "tmds");
+ 	if (IS_ERR(hdmi->clk_tmds))
+ 		return dev_err_probe(dev, PTR_ERR(hdmi->clk_tmds),
+ 				     "Couldn't get the tmds clock\n");
+@@ -246,6 +246,11 @@ static const struct sun8i_dw_hdmi_quirks
+ 	.mode_valid = sun8i_dw_hdmi_mode_valid_a83t,
+ };
+ 
++static const struct sun8i_dw_hdmi_quirks sun20i_d1_quirks = {
++	.mode_valid = sun8i_dw_hdmi_mode_valid_a83t,
++	.use_drm_infoframe = true,
++};
++
+ static const struct sun8i_dw_hdmi_quirks sun50i_h6_quirks = {
+ 	.mode_valid = sun8i_dw_hdmi_mode_valid_h6,
+ 	.use_drm_infoframe = true,
+@@ -257,6 +262,10 @@ static const struct of_device_id sun8i_d
+ 		.data = &sun8i_a83t_quirks,
+ 	},
+ 	{
++		.compatible = "allwinner,sun20i-d1-dw-hdmi",
++		.data = &sun20i_d1_quirks,
++	},
++	{
+ 		.compatible = "allwinner,sun50i-h6-dw-hdmi",
+ 		.data = &sun50i_h6_quirks,
+ 	},
diff --git a/target/linux/d1/patches-6.1/0008-drm-sun4i-sun8i-hdmi-phy-Add-support-for-D1-PHY.patch b/target/linux/d1/patches-6.1/0008-drm-sun4i-sun8i-hdmi-phy-Add-support-for-D1-PHY.patch
new file mode 100644
index 00000000000000..e8007cc5c41e61
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0008-drm-sun4i-sun8i-hdmi-phy-Add-support-for-D1-PHY.patch
@@ -0,0 +1,251 @@
+From 11f9765a8e6723bcb7243f6dbc48e6deaf17b097 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 3 Apr 2022 15:15:41 -0500
+Subject: [PATCH 008/117] drm/sun4i: sun8i-hdmi-phy: Add support for D1 PHY
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h  | 169 +++++++++++++++++++++++++
+ drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c |  32 +++++
+ 2 files changed, 201 insertions(+)
+
+--- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
++++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
+@@ -145,6 +145,175 @@
+ 
+ #define SUN8I_HDMI_PHY_CEC_REG		0x003c
+ 
++#define SUN20I_HDMI_PHY_CTL0_REG	0x0040
++#define SUN20I_HDMI_PHY_CTL0_PLL_LOCK_MODE_MAN	BIT(31)
++#define SUN20I_HDMI_PHY_CTL0_PLL_LOCK_MODE	BIT(30)
++#define SUN20I_HDMI_PHY_CTL0_FIFO_WORKC_EN	BIT(29)
++#define SUN20I_HDMI_PHY_CTL0_FIFO_AUTOSYNC_DIS	BIT(28)
++#define SUN20I_HDMI_PHY_CTL0_ENTX		GENMASK(27, 24)
++#define SUN20I_HDMI_PHY_CTL0_ENBI		GENMASK(23, 20)
++#define SUN20I_HDMI_PHY_CTL0_ENLDO		BIT(18)
++#define SUN20I_HDMI_PHY_CTL0_ENLDO_FS		BIT(17)
++#define SUN20I_HDMI_PHY_CTL0_ENCK		BIT(16)
++#define SUN20I_HDMI_PHY_CTL0_REG_PLR		GENMASK(15, 12)
++#define SUN20I_HDMI_PHY_CTL0_REG_DEN		GENMASK(11, 8)
++#define SUN20I_HDMI_PHY_CTL0_REG_CSMPS		GENMASK(7, 6)
++#define SUN20I_HDMI_PHY_CTL0_REG_CK_TEST_SEL	BIT(5)
++#define SUN20I_HDMI_PHY_CTL0_REG_CK_SEL		BIT(4)
++#define SUN20I_HDMI_PHY_CTL0_HPD_EN		BIT(2)
++#define SUN20I_HDMI_PHY_CTL0_SCL_EN		BIT(1)
++#define SUN20I_HDMI_PHY_CTL0_SDA_EN		BIT(0)
++
++#define SUN20I_HDMI_PHY_CTL1_REG	0x0044
++#define SUN20I_HDMI_PHY_CTL1_RXSENSE_MODE_MAN	BIT(31)
++#define SUN20I_HDMI_PHY_CTL1_RXSENSE_MODE	BIT(30)
++#define SUN20I_HDMI_PHY_CTL1_RES_S		GENMASK(29, 28)
++#define SUN20I_HDMI_PHY_CTL1_RES_SCKTMDS	BIT(27)
++#define SUN20I_HDMI_PHY_CTL1_REG_SWI		BIT(26)
++#define SUN20I_HDMI_PHY_CTL1_REG_SVR		GENMASK(25, 24)
++#define SUN20I_HDMI_PHY_CTL1_REG_BST2		GENMASK(21, 20)
++#define SUN20I_HDMI_PHY_CTL1_REG_BST1		GENMASK(19, 18)
++#define SUN20I_HDMI_PHY_CTL1_REG_BST0		GENMASK(17, 16)
++#define SUN20I_HDMI_PHY_CTL1_REG_SP2_3		GENMASK(15, 12)
++#define SUN20I_HDMI_PHY_CTL1_REG_SP2_2		GENMASK(11, 8)
++#define SUN20I_HDMI_PHY_CTL1_REG_SP2_1		GENMASK(7, 4)
++#define SUN20I_HDMI_PHY_CTL1_REG_SP2_0		GENMASK(3, 0)
++
++#define SUN20I_HDMI_PHY_CTL2_REG	0x0048
++#define SUN20I_HDMI_PHY_CTL2_HPDO_MODE_MAN	BIT(31)
++#define SUN20I_HDMI_PHY_CTL2_HPDO_MODE		BIT(30)
++#define SUN20I_HDMI_PHY_CTL2_REG_RESDI		GENMASK(29, 24)
++#define SUN20I_HDMI_PHY_CTL2_REG_SP1_3		GENMASK(23, 19)
++#define SUN20I_HDMI_PHY_CTL2_REG_SP1_2		GENMASK(18, 14)
++#define SUN20I_HDMI_PHY_CTL2_REG_SP1_1		GENMASK(13, 9)
++#define SUN20I_HDMI_PHY_CTL2_REG_SP1_0		GENMASK(8, 4)
++#define SUN20I_HDMI_PHY_CTL2_REG_P2OPT		GENMASK(3, 0)
++
++#define SUN20I_HDMI_PHY_CTL3_REG	0x004c
++#define SUN20I_HDMI_PHY_CTL3_REG_P2_3		GENMASK(31, 28)
++#define SUN20I_HDMI_PHY_CTL3_REG_P2_2		GENMASK(27, 24)
++#define SUN20I_HDMI_PHY_CTL3_REG_P2_1		GENMASK(23, 20)
++#define SUN20I_HDMI_PHY_CTL3_REG_P2_0		GENMASK(19, 16)
++#define SUN20I_HDMI_PHY_CTL3_REG_MC3		GENMASK(15, 12)
++#define SUN20I_HDMI_PHY_CTL3_REG_MC2		GENMASK(11, 8)
++#define SUN20I_HDMI_PHY_CTL3_REG_MC1		GENMASK(7, 4)
++#define SUN20I_HDMI_PHY_CTL3_REG_MC0		GENMASK(3, 0)
++
++#define SUN20I_HDMI_PHY_CTL4_REG	0x0050
++#define SUN20I_HDMI_PHY_CTL4_REG_SLV		GENMASK(31, 29)
++#define SUN20I_HDMI_PHY_CTL4_REG_P1_3		GENMASK(28, 24)
++#define SUN20I_HDMI_PHY_CTL4_REG_P1_2		GENMASK(20, 16)
++#define SUN20I_HDMI_PHY_CTL4_REG_P1_1		GENMASK(12, 8)
++#define SUN20I_HDMI_PHY_CTL4_REG_P1_0		GENMASK(4, 0)
++
++#define SUN20I_HDMI_PHY_CTL5_REG	0x0054
++#define SUN20I_HDMI_PHY_CTL5_REG_P1OPT		GENMASK(19, 16)
++#define SUN20I_HDMI_PHY_CTL5_REG_CKPDLYOPT	BIT(12)
++#define SUN20I_HDMI_PHY_CTL5_REG_CALSW		BIT(11)
++#define SUN20I_HDMI_PHY_CTL5_ENRESCK		BIT(10)
++#define SUN20I_HDMI_PHY_CTL5_ENRES		BIT(9)
++#define SUN20I_HDMI_PHY_CTL5_ENRCAL		BIT(8)
++#define SUN20I_HDMI_PHY_CTL5_ENP2S		GENMASK(7, 4)
++#define SUN20I_HDMI_PHY_CTL5_ENIB		BIT(1)
++#define SUN20I_HDMI_PHY_CTL5_ENCALOG		BIT(0)
++
++#define SUN20I_HDMI_PLL_CTL0_REG	0x0058
++#define SUN20I_HDMI_PLL_CTL0_CKO_SEL		GENMASK(31, 30)
++#define SUN20I_HDMI_PLL_CTL0_BYPASS_PPLL	BIT(29)
++#define SUN20I_HDMI_PLL_CTL0_ENVBS		BIT(28)
++#define SUN20I_HDMI_PLL_CTL0_SLV		GENMASK(26, 24)
++#define SUN20I_HDMI_PLL_CTL0_BCR		BIT(23)
++#define SUN20I_HDMI_PLL_CTL0_BYPASS_CLRDPTH	BIT(22)
++#define SUN20I_HDMI_PLL_CTL0_CLR_DPTH		GENMASK(21, 20)
++#define SUN20I_HDMI_PLL_CTL0_CUTFB		BIT(18)
++#define SUN20I_HDMI_PLL_CTL0_DIV2_CKBIT		BIT(17)
++#define SUN20I_HDMI_PLL_CTL0_DIV2_CKTMDS	BIT(16)
++#define SUN20I_HDMI_PLL_CTL0_DIV_PRE		GENMASK(15, 12)
++#define SUN20I_HDMI_PLL_CTL0_DIVX1		BIT(10)
++#define SUN20I_HDMI_PLL_CTL0_SDRVEN		BIT(9)
++#define SUN20I_HDMI_PLL_CTL0_VCORANGE		BIT(8)
++#define SUN20I_HDMI_PLL_CTL0_N_CNTRL		GENMASK(7, 6)
++#define SUN20I_HDMI_PLL_CTL0_GMP_CNTRL		GENMASK(5, 4)
++#define SUN20I_HDMI_PLL_CTL0_PROP_CNTRL		GENMASK(2, 0)
++
++#define SUN20I_HDMI_PLL_CTL1_REG	0x005c
++#define SUN20I_HDMI_PLL_CTL1_CTRL_MODLE_CLKSRC	BIT(31)
++#define SUN20I_HDMI_PLL_CTL1_PCNT_N		GENMASK(27, 20)
++#define SUN20I_HDMI_PLL_CTL1_PCNT_EN		BIT(19)
++#define SUN20I_HDMI_PLL_CTL1_SDM_EN		BIT(18)
++#define SUN20I_HDMI_PLL_CTL1_PIXEL_REP		GENMASK(17, 16)
++#define SUN20I_HDMI_PLL_CTL1_PWRON		BIT(12)
++#define SUN20I_HDMI_PLL_CTL1_RESET		BIT(11)
++#define SUN20I_HDMI_PLL_CTL1_SCKREF		BIT(10)
++#define SUN20I_HDMI_PLL_CTL1_SCKFB		BIT(9)
++#define SUN20I_HDMI_PLL_CTL1_DRV_ANA		BIT(8)
++#define SUN20I_HDMI_PLL_CTL1_FAST_TECH		BIT(7)
++#define SUN20I_HDMI_PLL_CTL1_GEAR_SHIFT		BIT(6)
++#define SUN20I_HDMI_PLL_CTL1_REF_CNTRL		GENMASK(5, 4)
++#define SUN20I_HDMI_PLL_CTL1_INT_CNTRL		GENMASK(2, 0)
++
++#define SUN20I_HDMI_AFIFO_CFG_REG	0x0060
++#define SUN20I_HDMI_AFIFO_CFG_AFIFO_ERROR	BIT(0)
++#define SUN20I_HDMI_AFIFO_CFG_AFIFO_ERROR_DET	BIT(1)
++
++#define SUN20I_HDMI_MODULATOR_CFG0_REG	0x0064
++#define SUN20I_HDMI_MODULATOR_CFG1_REG	0x0068
++
++#define SUN20I_HDMI_INDEB_CTRL_REG	0x006c
++#define SUN20I_HDMI_INDEB_CTRL_HPDI_DEBUGMODE	BIT(29)
++#define SUN20I_HDMI_INDEB_CTRL_HPDI_DEBUG	BIT(28)
++#define SUN20I_HDMI_INDEB_CTRL_SDAI_DEBUGMODE	BIT(25)
++#define SUN20I_HDMI_INDEB_CTRL_SDAI_DEBUG	BIT(24)
++#define SUN20I_HDMI_INDEB_CTRL_SCLI_DEBUGMODE	BIT(21)
++#define SUN20I_HDMI_INDEB_CTRL_SCLI_DEBUG	BIT(20)
++#define SUN20I_HDMI_INDEB_CTRL_CECI_DEBUGMODE	BIT(17)
++#define SUN20I_HDMI_INDEB_CTRL_CECI_DEBUG	BIT(16)
++#define SUN20I_HDMI_INDEB_CTRL_TXDATA_DEBUGMODE	GENMASK(1, 0)
++
++#define SUN20I_HDMI_INDBG_TXD0_REG	0x0070
++#define SUN20I_HDMI_INDBG_TXD1_REG	0x0074
++#define SUN20I_HDMI_INDBG_TXD2_REG	0x0078
++#define SUN20I_HDMI_INDBG_TXD3_REG	0x007c
++
++#define SUN20I_HDMI_PLL_STS_REG		0x0080
++#define SUN20I_HDMI_PLL_STS_PHY_CDETPCK_STATUS	BIT(31)
++#define SUN20I_HDMI_PLL_STS_PHY_CDETP_STATUS	GENMASK(30, 28)
++#define SUN20I_HDMI_PLL_STS_PHY_CDETNCK_STATUS	BIT(27)
++#define SUN20I_HDMI_PLL_STS_PHY_CDETN_STATUS	GENMASK(26, 24)
++#define SUN20I_HDMI_PLL_STS_PHY_HPDO_STATUS	BIT(23)
++#define SUN20I_HDMI_PLL_STS_PHY_SCLO_STATUS	BIT(22)
++#define SUN20I_HDMI_PLL_STS_PHY_SDAO_STATUS	BIT(21)
++#define SUN20I_HDMI_PLL_STS_PHY_CECO_STATUS	BIT(20)
++#define SUN20I_HDMI_PLL_STS_PHY_COUT2D_STATUS	BIT(17)
++#define SUN20I_HDMI_PLL_STS_PHY_RCALEND2D_STS	BIT(16)
++#define SUN20I_HDMI_PLL_STS_PHY_RESDO2D_STATUS	GENMASK(13, 8)
++#define SUN20I_HDMI_PLL_STS_PLL_LOCK_STATUS	BIT(4)
++#define SUN20I_HDMI_PLL_STS_RXSENSE_DLY_STATUS	BIT(1)
++#define SUN20I_HDMI_PLL_STS_TX_READY_DLY_STATUS	BIT(0)
++
++#define SUN20I_HDMI_PRBS_CTL_REG	0x0084
++#define SUN20I_HDMI_PRBS_SEED_GEN_REG	0x0088
++#define SUN20I_HDMI_PRBS_SEED_CHK_REG	0x008c
++#define SUN20I_HDMI_PRBS_SEED_NUM_REG	0x0090
++#define SUN20I_HDMI_PRBS_CYCLE_NUM_REG	0x0094
++
++#define SUN20I_HDMI_PLL_ODLY_REG	0x0098
++#define SUN20I_HDMI_PLL_ODLY_RXSENSE_DLY_RESET	BIT(31)
++#define SUN20I_HDMI_PLL_ODLY_RXSENSE_DLY_COUNT	GENMASK(30, 16)
++#define SUN20I_HDMI_PLL_ODLY_TX_READY_DLY_RESET	BIT(15)
++#define SUN20I_HDMI_PLL_ODLY_TX_READY_DLY_COUNT	GENMASK(14, 0)
++
++#define SUN20I_HDMI_PHY_CTL6_REG	0x009c
++#define SUN20I_HDMI_PHY_CTL6_SWITCH_CLKCH_DATA	BIT(31)
++#define SUN20I_HDMI_PHY_CTL6_EN_CKDAT		BIT(30)
++#define SUN20I_HDMI_PHY_CTL6_CLK_GREATE2_340M	GENMASK(29, 20)
++#define SUN20I_HDMI_PHY_CTL6_CLK_GREATE1_340M	GENMASK(19, 10)
++#define SUN20I_HDMI_PHY_CTL6_CLK_GREATE0_340M	GENMASK(9, 0)
++
++#define SUN20I_HDMI_PHY_CTL7_REG	0x00a0
++#define SUN20I_HDMI_PHY_CTL7_CLK_LOW_340M	GENMASK(21, 12)
++#define SUN20I_HDMI_PHY_CTL7_CLK_GREATE3_340M	GENMASK(9, 0)
++
+ struct sun8i_hdmi_phy;
+ 
+ struct sun8i_hdmi_phy_variant {
+--- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
++++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
+@@ -398,6 +398,28 @@ static const struct dw_hdmi_phy_ops sun8
+ 	.setup_hpd	= dw_hdmi_phy_setup_hpd,
+ };
+ 
++static int sun20i_d1_hdmi_phy_config(struct dw_hdmi *hdmi, void *data,
++				     const struct drm_display_info *display,
++				     const struct drm_display_mode *mode)
++{
++	struct sun8i_hdmi_phy *phy = data;
++
++	return 0;
++}
++
++static void sun20i_d1_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data)
++{
++	struct sun8i_hdmi_phy *phy = data;
++}
++
++static const struct dw_hdmi_phy_ops sun20i_d1_hdmi_phy_ops = {
++	.init		= sun20i_d1_hdmi_phy_config,
++	.disable	= sun20i_d1_hdmi_phy_disable,
++	.read_hpd	= dw_hdmi_phy_read_hpd,
++	.update_hpd	= dw_hdmi_phy_update_hpd,
++	.setup_hpd	= dw_hdmi_phy_setup_hpd,
++};
++
+ static void sun8i_hdmi_phy_unlock(struct sun8i_hdmi_phy *phy)
+ {
+ 	/* enable read access to HDMI controller */
+@@ -576,6 +598,7 @@ void sun8i_hdmi_phy_set_ops(struct sun8i
+ 	const struct sun8i_hdmi_phy_variant *variant = phy->variant;
+ 
+ 	if (variant->phy_ops) {
++		plat_data->phy_force_vendor = true;
+ 		plat_data->phy_ops = variant->phy_ops;
+ 		plat_data->phy_name = "sun8i_dw_hdmi_phy";
+ 		plat_data->phy_data = phy;
+@@ -612,6 +635,11 @@ static const struct sun8i_hdmi_phy_varia
+ 	.phy_init = &sun8i_hdmi_phy_init_h3,
+ };
+ 
++static const struct sun8i_hdmi_phy_variant sun20i_d1_hdmi_phy = {
++	.phy_ops = &sun20i_d1_hdmi_phy_ops,
++	.phy_init = &sun50i_hdmi_phy_init_h6,
++};
++
+ static const struct sun8i_hdmi_phy_variant sun50i_a64_hdmi_phy = {
+ 	.has_phy_clk = true,
+ 	.phy_ops = &sun8i_h3_hdmi_phy_ops,
+@@ -639,6 +667,10 @@ static const struct of_device_id sun8i_h
+ 		.data = &sun8i_r40_hdmi_phy,
+ 	},
+ 	{
++		.compatible = "allwinner,sun20i-d1-hdmi-phy",
++		.data = &sun20i_d1_hdmi_phy,
++	},
++	{
+ 		.compatible = "allwinner,sun50i-a64-hdmi-phy",
+ 		.data = &sun50i_a64_hdmi_phy,
+ 	},
diff --git a/target/linux/d1/patches-6.1/0009-drm-sun4i-Copy-in-BSP-code-for-D1-HDMI-PHY.patch b/target/linux/d1/patches-6.1/0009-drm-sun4i-Copy-in-BSP-code-for-D1-HDMI-PHY.patch
new file mode 100644
index 00000000000000..85c81d5057140e
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0009-drm-sun4i-Copy-in-BSP-code-for-D1-HDMI-PHY.patch
@@ -0,0 +1,621 @@
+From 7ea7d4abfd537230da58533803a2d0257addace8 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Wed, 30 Mar 2022 00:46:07 -0500
+Subject: [PATCH 009/117] drm/sun4i: Copy in BSP code for D1 HDMI PHY
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/gpu/drm/sun4i/aw_phy.h         | 411 +++++++++++++++++++++++++
+ drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h  |   1 +
+ drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 156 ++++++++++
+ 3 files changed, 568 insertions(+)
+ create mode 100644 drivers/gpu/drm/sun4i/aw_phy.h
+
+--- /dev/null
++++ b/drivers/gpu/drm/sun4i/aw_phy.h
+@@ -0,0 +1,411 @@
++/*
++ * Allwinner SoCs hdmi2.0 driver.
++ *
++ * Copyright (C) 2016 Allwinner.
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2.  This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++
++#ifndef AW_PHY_H_
++#define AW_PHY_H_
++
++#define AW_PHY_TIMEOUT	1000
++#define LOCK_TIMEOUT	100
++
++/* allwinner phy register offset */
++#define HDMI_PHY_CTL0				0x40
++#define HDMI_PHY_CTL1				0x44
++#define HDMI_PHY_CTL2				0x48
++#define HDMI_PHY_CTL3				0x4C
++#define HDMI_PHY_CTL4				0x50
++#define HDMI_PHY_CTL5				0x54
++#define HDMI_PLL_CTL0				0x58
++#define HDMI_PLL_CTL1				0x5C
++#define HDMI_AFIFO_CFG				0x60
++#define HDMI_MODULATOR_CFG0			0x64
++#define HDMI_MODULATOR_CFG1			0x68
++#define HDMI_PHY_INDEB_CTRL			0x6C
++#define HDMI_PHY_INDBG_TXD0			0x70
++#define HDMI_PHY_INDBG_TXD1			0x74
++#define HDMI_PHY_INDBG_TXD2			0x78
++#define HDMI_PHY_INDBG_TXD3			0x7C
++#define HDMI_PHY_PLL_STS			0x80
++#define HDMI_PRBS_CTL				0x84
++#define HDMI_PRBS_SEED_GEN			0x88
++#define HDMI_PRBS_SEED_CHK			0x8C
++#define HDMI_PRBS_SEED_NUM			0x90
++#define HDMI_PRBS_CYCLE_NUM			0x94
++#define HDMI_PHY_PLL_ODLY_CFG			0x98
++#define HDMI_PHY_CTL6				0x9C
++#define HDMI_PHY_CTL7				0xA0
++
++typedef union {
++	u32 dwval;
++	struct {
++		u32 sda_en		:1;    // Default: 0;
++		u32 scl_en		:1;    // Default: 0;
++		u32 hpd_en		:1;    // Default: 0;
++		u32 res0		:1;    // Default: 0;
++		u32 reg_ck_sel		:1;    // Default: 1;
++		u32 reg_ck_test_sel	:1;    // Default: 1;
++		u32 reg_csmps		:2;    // Default: 0;
++		u32 reg_den		:4;    // Default: F;
++		u32 reg_plr		:4;    // Default: 0;
++		u32 enck		:1;    // Default: 1;
++		u32 enldo_fs		:1;    // Default: 1;
++		u32 enldo		:1;    // Default: 1;
++		u32 res1		:1;    // Default: 1;
++		u32 enbi		:4;    // Default: F;
++		u32 entx		:4;    // Default: F;
++		u32 async_fifo_autosync_disable	:1;    // Default: 0;
++		u32 async_fifo_workc_enable	:1;    // Default: 1;
++		u32 phy_pll_lock_mode		:1;    // Default: 1;
++		u32 phy_pll_lock_mode_man	:1;    // Default: 1;
++	} bits;
++} HDMI_PHY_CTL0_t;      //===========================    0x0040
++
++typedef union {
++	u32 dwval;
++	struct {
++		u32 reg_sp2_0				:   4  ;    // Default: 0;
++		u32 reg_sp2_1				:   4  ;    // Default: 0;
++		u32 reg_sp2_2				:   4  ;    // Default: 0;
++		u32 reg_sp2_3				:   4  ;    // Default: 0;
++		u32 reg_bst0				:   2  ;    // Default: 3;
++		u32 reg_bst1				:   2  ;    // Default: 3;
++		u32 reg_bst2				:   2  ;    // Default: 3;
++		u32 res0				:   2  ;    // Default: 0;
++		u32 reg_svr				:   2  ;    // Default: 2;
++		u32 reg_swi				:   1  ;    // Default: 0;
++		u32 res_scktmds				:   1  ;    // Default: 0;
++		u32 res_res_s				:   2  ;    // Default: 3;
++		u32 phy_rxsense_mode			:   1  ;    // Default: 0;
++		u32 res_rxsense_mode_man		:   1  ;    // Default: 0;
++	} bits;
++} HDMI_PHY_CTL1_t;      //=====================================================    0x0044
++
++typedef union {
++	u32 dwval;
++	struct {
++		u32 reg_p2opt				:   4  ;    // Default: 0;
++		u32 reg_sp1_0				:   5  ;    // Default: 0;
++		u32 reg_sp1_1				:   5  ;    // Default: 0;
++		u32 reg_sp1_2				:   5  ;    // Default: 0;
++		u32 reg_sp1_3				:   5  ;    // Default: 0;
++		u32 reg_resdi				:   6  ;    // Default: 18;
++		u32 phy_hpdo_mode			:   1  ;    // Default: 0;
++		u32 phy_hpdo_mode_man			:   1  ;    // Default: 0;
++	} bits;
++} HDMI_PHY_CTL2_t;      //=====================================================    0x0048
++
++
++
++typedef union {
++	u32 dwval;
++	struct {
++		u32 reg_mc0				:   4  ;    // Default: F;
++		u32 reg_mc1				:   4  ;    // Default: F;
++		u32 reg_mc2				:   4  ;    // Default: F;
++		u32 reg_mc3				:   4  ;    // Default: F;
++		u32 reg_p2_0				:   4  ;    // Default: F;
++		u32 reg_p2_1				:   4  ;    // Default: F;
++		u32 reg_p2_2				:   4  ;    // Default: F;
++		u32 reg_p2_3				:   4  ;    // Default: F;
++	} bits;
++} HDMI_PHY_CTL3_t;      //=====================================================    0x004C
++
++
++
++typedef union {
++	u32 dwval;
++	struct {
++		u32 reg_p1_0				:   5  ;    // Default: 0x10;
++		u32 res0				:   3  ;    // Default: 0;
++		u32 reg_p1_1				:   5  ;    // Default: 0x10;
++		u32 res1				:   3  ;    // Default: 0;
++		u32 reg_p1_2				:   5  ;    // Default: 0x10;
++		u32 res2				:   3  ;    // Default: 0;
++		u32 reg_p1_3				:   5  ;    // Default: 0x10;
++		u32 reg_slv				:   3  ;    // Default: 0;
++	} bits;
++} HDMI_PHY_CTL4_t;      //=====================================================    0x0050
++
++typedef union {
++	u32 dwval;
++	struct {
++		u32 encalog				:   1  ;    // Default: 0x1;
++		u32 enib				:   1  ;    // Default: 0x1;
++		u32 res0				:   2  ;    // Default: 0;
++		u32 enp2s				:   4  ;    // Default: 0xF;
++		u32 enrcal				:   1  ;    // Default: 0x1;
++		u32 enres				:   1  ;    // Default: 1;
++		u32 enresck				:   1  ;    // Default: 1;
++		u32 reg_calsw				:   1  ;    // Default: 0;
++		u32 reg_ckpdlyopt			:   1  ;    // Default: 0;
++		u32 res1				:   3  ;    // Default: 0;
++		u32 reg_p1opt				:   4  ;    // Default: 0;
++		u32 res2				:  12  ;    // Default: 0;
++	} bits;
++} HDMI_PHY_CTL5_t;      //=====================================================    0x0054
++
++typedef union {
++	u32 dwval;
++	struct {
++		u32 prop_cntrl				:   3  ;    // Default: 0x7;
++		u32 res0				:   1  ;    // Default: 0;
++		u32 gmp_cntrl				:   2  ;    // Default: 1;
++		u32 n_cntrl				:   2  ;    // Default: 0;
++		u32 vcorange				:   1  ;    // Default: 0;
++		u32 sdrven				:   1  ;    // Default: 0;
++		u32 divx1				:   1  ;    // Default: 0;
++		u32 res1				:   1  ;    // Default: 0;
++		u32 div_pre				:   4  ;    // Default: 0;
++		u32 div2_cktmds				:   1  ;    // Default: 1;
++		u32 div2_ckbit				:   1  ;    // Default: 1;
++		u32 cutfb				:   1  ;    // Default: 0;
++		u32 res2				:   1  ;    // Default: 0;
++		u32 clr_dpth				:   2  ;    // Default: 0;
++		u32 bypass_clrdpth			:   1  ;    // Default: 0;
++		u32 bcr					:   1  ;    // Default: 0;
++		u32 slv					:   3  ;    // Default: 4;
++		u32 res3				:   1  ;    // Default: 0;
++		u32 envbs				:   1  ;    // Default: 0;
++		u32 bypass_ppll				:   1  ;    // Default: 0;
++		u32 cko_sel				:   2  ;    // Default: 0;
++	} bits;
++} HDMI_PLL_CTL0_t;      //=====================================================    0x0058
++
++
++
++typedef union {
++	u32 dwval;
++	struct {
++		u32 int_cntrl				:   3  ;    // Default: 0x0;
++		u32 res0				:   1  ;    // Default: 0;
++		u32 ref_cntrl				:   2  ;    // Default: 3;
++		u32 gear_shift				:   1  ;    // Default: 0;
++		u32 fast_tech				:   1  ;    // Default: 0;
++		u32 drv_ana				:   1  ;    // Default: 1;
++		u32 sckfb				:   1  ;    // Default: 0;
++		u32 sckref				:   1  ;    // Default: 0;
++		u32 reset				:   1  ;    // Default: 0;
++		u32 pwron				:   1  ;    // Default: 0;
++		u32 res1				:   3  ;    // Default: 0;
++		u32 pixel_rep				:   2  ;    // Default: 0;
++		u32 sdm_en				:   1  ;    // Default: 0;
++		u32 pcnt_en				:   1  ;    // Default: 0;
++		u32 pcnt_n				:   8  ;    // Default: 0xE;
++		u32 res2				:   3  ;    // Default: 0;
++		u32 ctrl_modle_clksrc			:   1  ;    // Default: 0;
++	} bits;
++} HDMI_PLL_CTL1_t;      //=====================================================    0x005C
++
++typedef union {
++	u32 dwval;
++	struct {
++		u32 hdmi_afifo_error	:   1  ;    // Default: 0x0;
++		u32 hdmi_afifo_error_det	:   1  ;    // Default: 0x0;
++		u32 res0			:  30  ;    // Default: 0;
++	} bits;
++} HDMI_AFIFO_CFG_t;      //=====================================================    0x0060
++
++typedef union {
++	u32 dwval;
++	struct {
++		u32 fnpll_mash_en		:   1  ;    // Default: 0x0;
++		u32 fnpll_mash_mod		:   2  ;    // Default: 0x0;
++		u32 fnpll_mash_stp		:   9  ;    // Default: 0x0;
++		u32 fnpll_mash_m12		:   1  ;    // Default: 0x0;
++		u32 fnpll_mash_frq		:   2  ;    // Default: 0x0;
++		u32 fnpll_mash_bot		:  17  ;    // Default: 0x0;
++	} bits;
++} HDMI_MODULATOR_CFG0_t;      //=====================================================    0x0064
++
++typedef union {
++	u32 dwval;
++	struct {
++		u32 fnpll_mash_dth		:   1  ;    // Default: 0x0;
++		u32 fnpll_mash_fen		:   1  ;    // Default: 0x0;
++		u32 fnpll_mash_frc		:  17  ;    // Default: 0x0;
++		u32 fnpll_mash_fnv		:   8  ;    // Default: 0x0;
++		u32 res0			:   5  ;    // Default: 0x0;
++	} bits;
++} HDMI_MODULATOR_CFG1_t;      //=====================================================    0x0068
++
++typedef union {
++	u32 dwval;
++	struct {
++		u32 txdata_debugmode		:   2  ;    // Default: 0x0;
++		u32 res0			:  14  ;    // Default: 0x0;
++		u32 ceci_debug			:   1  ;    // Default: 0x0;
++		u32 ceci_debugmode		:   1  ;    // Default: 0x0;
++		u32 res1			:   2  ;    // Default: 0x0;
++		u32 sdai_debug			:   1  ;    // Default: 0x0;
++		u32 sdai_debugmode		:   1  ;    // Default: 0x0;
++		u32 res2			:   2  ;    // Default: 0x0;
++		u32 scli_debug			:   1  ;    // Default: 0x0;
++		u32 scli_debugmode		:   1  ;    // Default: 0x0;
++		u32 res3			:   2  ;    // Default: 0x0;
++		u32 hpdi_debug			:   1  ;    // Default: 0x0;
++		u32 hpdi_debugmode		:   1  ;    // Default: 0x0;
++		u32 res4			:   2  ;    // Default: 0x0;
++	} bits;
++} HDMI_PHY_INDBG_CTRL_t;      //==================================================    0x006C
++
++typedef union {
++	u32 dwval;
++	struct {
++		u32 txdata0_debug_data	    :  32  ;    // Default: 0x0;
++	} bits;
++} HDMI_PHY_INDBG_TXD0_t;      //==================================================    0x0070
++
++typedef union {
++	u32 dwval;
++	struct {
++		u32 txdata1_debug_data	    :  32  ;    // Default: 0x0;
++	} bits;
++} HDMI_PHY_INDBG_TXD1_t;      //==================================================    0x0074
++
++typedef union {
++	u32 dwval;
++	struct {
++		u32 txdata2_debug_data	    :  32  ;    // Default: 0x0;
++	} bits;
++} HDMI_PHY_INDBG_TXD2_t;      //==================================================    0x0078
++
++typedef union {
++	u32 dwval;
++	struct {
++		u32 txdata3_debug_data	    :  32  ;    // Default: 0x0;
++	} bits;
++} HDMI_PHY_INDBG_TXD3_t;      //==================================================    0x007C
++
++typedef union {
++	u32 dwval;
++	struct {
++		u32 tx_ready_dly_status	:   1  ;    // Default: 0x0;
++		u32 rxsense_dly_status		:   1  ;    // Default: 0x0;
++		u32 res0			:   2  ;    // Default: 0x0;
++		u32 pll_lock_status		:   1  ;    // Default: 0x0;
++		u32 res1			:   3  ;    // Default: 0x0;
++		u32 phy_resdo2d_status		:   6  ;    // Default: 0x0;
++		u32 res2			:   2  ;    // Default: 0x0;
++		u32 phy_rcalend2d_status	:   1  ;    // Default: 0x0;
++		u32 phy_cout2d_status		:   1  ;    // Default: 0x0;
++		u32 res3			:   2  ;    // Default: 0x0;
++		u32 phy_ceco_status		:   1  ;    // Default: 0x0;
++		u32 phy_sdao_status		:   1  ;    // Default: 0x0;
++		u32 phy_sclo_status		:   1  ;    // Default: 0x0;
++		u32 phy_hpdo_status		:   1  ;    // Default: 0x0;
++		u32 phy_cdetn_status		:   3  ;    // Default: 0x0;
++		u32 phy_cdetnck_status		:   1  ;    // Default: 0x0;
++		u32 phy_cdetp_status		:   3  ;    // Default: 0x0;
++		u32 phy_cdetpck_status		:   1  ;    // Default: 0x0;
++	} bits;
++} HDMI_PHY_PLL_STS_t;      //=====================================================    0x0080
++
++typedef union {
++	u32 dwval;
++	struct {
++		u32 prbs_en				:   1  ;    // Default: 0x0;
++		u32 prbs_start				:   1  ;    // Default: 0x0;
++		u32 prbs_seq_gen			:   1  ;    // Default: 0x0;
++		u32 prbs_seq_chk			:   1  ;    // Default: 0x0;
++		u32 prbs_mode				:   4  ;    // Default: 0x0;
++		u32 prbs_type				:   2  ;    // Default: 0x0;
++		u32 prbs_clk_pol			:   1  ;    // Default: 0x0;
++		u32 res0				:  21  ;    // Default: 0x0;
++	} bits;
++} HDMI_PRBS_CTL_t;      //=====================================================    0x0084
++
++typedef union {
++	u32 dwval;
++	struct {
++		u32 prbs_seed_gen			:  32  ;    // Default: 0x0;
++	} bits;
++} HDMI_PRBS_SEED_GEN_t;      //=================================================    0x0088
++
++typedef union {
++	u32 dwval;
++	struct {
++		u32 prbs_seed_chk			:  32  ;    // Default: 0x0;
++	} bits;
++} HDMI_PRBS_SEED_CHK_t;      //=================================================    0x008C
++
++typedef union {
++	u32 dwval;
++	struct {
++		u32 prbs_seed_num			:  32  ;    // Default: 0x0;
++	} bits;
++} HDMI_PRBS_SEED_NUM_t;      //=================================================    0x0090
++
++typedef union {
++	u32 dwval;
++	struct {
++		u32 prbs_cycle_num			:  32  ;    // Default: 0x0;
++	} bits;
++} HDMI_PRBS_CYCLE_NUM_t;      //=================================================    0x0094
++
++typedef union {
++	u32 dwval;
++	struct {
++		u32	tx_ready_dly_count		:  15  ;    // Default: 0x0;
++		u32	tx_ready_dly_reset		:   1  ;    // Default: 0x0;
++		u32	rxsense_dly_count		:  15  ;    // Default: 0x0;
++		u32	rxsense_dly_reset		:   1  ;    // Default: 0x0;
++	} bits;
++} HDMI_PHY_PLL_ODLY_CFG_t;      //=================================================    0x0098
++
++typedef union {
++	u32 dwval;
++	struct {
++		u32	clk_greate0_340m		:  10  ;    // Default: 0x3FF;
++		u32	clk_greate1_340m		:  10  ;    // Default: 0x3FF;
++		u32	clk_greate2_340m		:  10  ;    // Default: 0x3FF;
++		u32	en_ckdat				:   1  ;    // Default: 0x3FF;
++		u32	switch_clkch_data_corresponding	:   1  ;    // Default: 0x3FF;
++	} bits;
++} HDMI_PHY_CTL6_t;      //=========================================================    0x009C
++
++typedef union {
++	u32 dwval;
++	struct {
++		u32	clk_greate3_340m		:  10  ;    // Default: 0x0;
++		u32	res0				:   2  ;    // Default: 0x3FF;
++		u32	clk_low_340m			:  10  ;    // Default: 0x3FF;
++		u32	res1				:  10  ;    // Default: 0x3FF;
++	} bits;
++} HDMI_PHY_CTL7_t;      //=========================================================    0x00A0
++
++struct __aw_phy_reg_t {
++	u32 res[16];		/* 0x0 ~ 0x3c */
++	HDMI_PHY_CTL0_t		phy_ctl0; /* 0x0040 */
++	HDMI_PHY_CTL1_t		phy_ctl1; /* 0x0044 */
++	HDMI_PHY_CTL2_t		phy_ctl2; /* 0x0048 */
++	HDMI_PHY_CTL3_t		phy_ctl3; /* 0x004c */
++	HDMI_PHY_CTL4_t		phy_ctl4; /* 0x0050 */
++	HDMI_PHY_CTL5_t		phy_ctl5; /* 0x0054 */
++	HDMI_PLL_CTL0_t		pll_ctl0; /* 0x0058 */
++	HDMI_PLL_CTL1_t		pll_ctl1; /* 0x005c */
++	HDMI_AFIFO_CFG_t	afifo_cfg; /* 0x0060 */
++	HDMI_MODULATOR_CFG0_t	modulator_cfg0; /* 0x0064 */
++	HDMI_MODULATOR_CFG1_t	modulator_cfg1; /* 0x0068 */
++	HDMI_PHY_INDBG_CTRL_t	phy_indbg_ctrl;	/* 0x006c */
++	HDMI_PHY_INDBG_TXD0_t	phy_indbg_txd0; /* 0x0070 */
++	HDMI_PHY_INDBG_TXD1_t	phy_indbg_txd1; /* 0x0074 */
++	HDMI_PHY_INDBG_TXD2_t	phy_indbg_txd2; /* 0x0078 */
++	HDMI_PHY_INDBG_TXD3_t	phy_indbg_txd3; /* 0x007c */
++	HDMI_PHY_PLL_STS_t	phy_pll_sts; /* 0x0080 */
++	HDMI_PRBS_CTL_t		prbs_ctl;	/* 0x0084 */
++	HDMI_PRBS_SEED_GEN_t	prbs_seed_gen;	/* 0x0088 */
++	HDMI_PRBS_SEED_CHK_t	prbs_seed_chk;	/* 0x008c */
++	HDMI_PRBS_SEED_NUM_t	prbs_seed_num;	/* 0x0090 */
++	HDMI_PRBS_CYCLE_NUM_t	prbs_cycle_num;	/* 0x0094 */
++	HDMI_PHY_PLL_ODLY_CFG_t	phy_pll_odly_cfg; /* 0x0098 */
++	HDMI_PHY_CTL6_t		phy_ctl6;	/* 0x009c */
++	HDMI_PHY_CTL7_t		phy_ctl7;	/* 0x00A0 */
++};
++
++#endif	/* AW_PHY_H_ */
+--- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
++++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
+@@ -334,6 +334,7 @@ struct sun8i_hdmi_phy {
+ 	struct clk			*clk_pll1;
+ 	struct device			*dev;
+ 	unsigned int			rcal;
++	void __iomem			*base;
+ 	struct regmap			*regs;
+ 	struct reset_control		*rst_phy;
+ 	const struct sun8i_hdmi_phy_variant *variant;
+--- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
++++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
+@@ -9,6 +9,8 @@
+ 
+ #include "sun8i_dw_hdmi.h"
+ 
++#include "aw_phy.h"
++
+ /*
+  * Address can be actually any value. Here is set to same value as
+  * it is set in BSP driver.
+@@ -398,11 +400,164 @@ static const struct dw_hdmi_phy_ops sun8
+ 	.setup_hpd	= dw_hdmi_phy_setup_hpd,
+ };
+ 
++static int sun20i_d1_hdmi_phy_enable(volatile struct __aw_phy_reg_t __iomem *phy_base)
++{
++	int i = 0, status = 0;
++
++	pr_info("enter %s\n", __func__);
++
++	//enib -> enldo -> enrcal -> encalog -> enbi[3:0] -> enck -> enp2s[3:0] -> enres -> enresck -> entx[3:0]
++	phy_base->phy_ctl4.bits.reg_slv = 4;     //low power voltage 1.08V, default is 3, set 4 as well as pll_ctl0 bit [24:26]
++	phy_base->phy_ctl5.bits.enib = 1;
++	phy_base->phy_ctl0.bits.enldo = 1;
++	phy_base->phy_ctl0.bits.enldo_fs = 1;
++	phy_base->phy_ctl5.bits.enrcal = 1;
++
++	phy_base->phy_ctl5.bits.encalog = 1;
++
++	for (i = 0; i < AW_PHY_TIMEOUT; i++) {
++		udelay(5);
++		status = phy_base->phy_pll_sts.bits.phy_rcalend2d_status;
++		if (status & 0x1) {
++			pr_info("[%s]:phy_rcalend2d_status\n", __func__);
++			break;
++		}
++	}
++	if ((i == AW_PHY_TIMEOUT) && !status) {
++		pr_err("phy_rcalend2d_status Timeout !\n");
++		return -1;
++	}
++
++	phy_base->phy_ctl0.bits.enbi = 0xF;
++	for (i = 0; i < AW_PHY_TIMEOUT; i++) {
++		udelay(5);
++		status = phy_base->phy_pll_sts.bits.pll_lock_status;
++		if (status & 0x1) {
++			pr_info("[%s]:pll_lock_status\n", __func__);
++			break;
++		}
++	}
++	if ((i == AW_PHY_TIMEOUT) && !status) {
++		pr_err("pll_lock_status Timeout! status = 0x%x\n", status);
++		return -1;
++	}
++
++	phy_base->phy_ctl0.bits.enck = 1;
++	phy_base->phy_ctl5.bits.enp2s = 0xF;
++	phy_base->phy_ctl5.bits.enres = 1;
++	phy_base->phy_ctl5.bits.enresck = 1;
++	phy_base->phy_ctl0.bits.entx = 0xF;
++
++	for (i = 0; i < AW_PHY_TIMEOUT; i++) {
++		udelay(5);
++		status = phy_base->phy_pll_sts.bits.tx_ready_dly_status;
++		if (status & 0x1) {
++			pr_info("[%s]:tx_ready_status\n", __func__);
++			break;
++		}
++	}
++	if ((i == AW_PHY_TIMEOUT) && !status) {
++		pr_err("tx_ready_status Timeout ! status = 0x%x\n", status);
++		return -1;
++	}
++
++	return 0;
++}
++
+ static int sun20i_d1_hdmi_phy_config(struct dw_hdmi *hdmi, void *data,
+ 				     const struct drm_display_info *display,
+ 				     const struct drm_display_mode *mode)
+ {
+ 	struct sun8i_hdmi_phy *phy = data;
++	volatile struct __aw_phy_reg_t __iomem *phy_base = phy->base;
++	int ret;
++
++	pr_info("enter %s\n", __func__);
++
++	/* enable all channel */
++	phy_base->phy_ctl5.bits.reg_p1opt = 0xF;
++
++	// phy_reset
++	phy_base->phy_ctl0.bits.entx = 0;
++	phy_base->phy_ctl5.bits.enresck = 0;
++	phy_base->phy_ctl5.bits.enres = 0;
++	phy_base->phy_ctl5.bits.enp2s = 0;
++	phy_base->phy_ctl0.bits.enck = 0;
++	phy_base->phy_ctl0.bits.enbi = 0;
++	phy_base->phy_ctl5.bits.encalog = 0;
++	phy_base->phy_ctl5.bits.enrcal = 0;
++	phy_base->phy_ctl0.bits.enldo_fs = 0;
++	phy_base->phy_ctl0.bits.enldo = 0;
++	phy_base->phy_ctl5.bits.enib = 0;
++	phy_base->pll_ctl1.bits.reset = 1;
++	phy_base->pll_ctl1.bits.pwron = 0;
++	phy_base->pll_ctl0.bits.envbs = 0;
++
++	// phy_set_mpll
++	phy_base->pll_ctl0.bits.cko_sel = 0x3;
++	phy_base->pll_ctl0.bits.bypass_ppll = 0x1;
++	phy_base->pll_ctl1.bits.drv_ana = 1;
++	phy_base->pll_ctl1.bits.ctrl_modle_clksrc = 0x0; //0: PLL_video   1: MPLL
++	phy_base->pll_ctl1.bits.sdm_en = 0x0;            //mpll sdm jitter is very large, not used for the time being
++	phy_base->pll_ctl1.bits.sckref = 0;        //default value is 1
++	phy_base->pll_ctl0.bits.slv = 4;
++	phy_base->pll_ctl0.bits.prop_cntrl = 7;   //default value 7
++	phy_base->pll_ctl0.bits.gmp_cntrl = 3;    //default value 1
++	phy_base->pll_ctl1.bits.ref_cntrl = 0;
++	phy_base->pll_ctl0.bits.vcorange = 1;
++
++	// phy_set_div
++	phy_base->pll_ctl0.bits.div_pre = 0;      //div7 = n+1
++	phy_base->pll_ctl1.bits.pcnt_en = 0;
++	phy_base->pll_ctl1.bits.pcnt_n = 1;       //div6 = 1 (pcnt_en=0)    [div6 = n (pcnt_en = 1) note that some multiples are problematic] 4-256
++	phy_base->pll_ctl1.bits.pixel_rep = 0;    //div5 = n+1
++	phy_base->pll_ctl0.bits.bypass_clrdpth = 0;
++	phy_base->pll_ctl0.bits.clr_dpth = 0;     //div4 = 1 (bypass_clrdpth = 0)
++	//00: 2    01: 2.5  10: 3   11: 4
++	phy_base->pll_ctl0.bits.n_cntrl = 1;      //div
++	phy_base->pll_ctl0.bits.div2_ckbit = 0;   //div1 = n+1
++	phy_base->pll_ctl0.bits.div2_cktmds = 0;  //div2 = n+1
++	phy_base->pll_ctl0.bits.bcr = 0;          //div3    0: [1:10]  1: [1:40]
++	phy_base->pll_ctl1.bits.pwron = 1;
++	phy_base->pll_ctl1.bits.reset = 0;
++
++	// configure phy
++	/* config values taken from table */
++	phy_base->phy_ctl1.dwval = ((phy_base->phy_ctl1.dwval & 0xFFC0FFFF) | /* config->phy_ctl1 */ 0x0);
++	phy_base->phy_ctl2.dwval = ((phy_base->phy_ctl2.dwval & 0xFF000000) | /* config->phy_ctl2 */ 0x0);
++	phy_base->phy_ctl3.dwval = ((phy_base->phy_ctl3.dwval & 0xFFFF0000) | /* config->phy_ctl3 */ 0xFFFF);
++	phy_base->phy_ctl4.dwval = ((phy_base->phy_ctl4.dwval & 0xE0000000) | /* config->phy_ctl4 */ 0xC0D0D0D);
++	//phy_base->pll_ctl0.dwval |= config->pll_ctl0;
++	//phy_base->pll_ctl1.dwval |= config->pll_ctl1;
++
++	// phy_set_clk
++	phy_base->phy_ctl6.bits.switch_clkch_data_corresponding = 0;
++	phy_base->phy_ctl6.bits.clk_greate0_340m = 0x3FF;
++	phy_base->phy_ctl6.bits.clk_greate1_340m = 0x3FF;
++	phy_base->phy_ctl6.bits.clk_greate2_340m = 0x0;
++	phy_base->phy_ctl7.bits.clk_greate3_340m = 0x0;
++	phy_base->phy_ctl7.bits.clk_low_340m = 0x3E0;
++	phy_base->phy_ctl6.bits.en_ckdat = 1;       //default value is 0
++
++	// phy_base->phy_ctl2.bits.reg_resdi = 0x18;
++	// phy_base->phy_ctl4.bits.reg_slv = 3;         //low power voltage 1.08V, default value is 3
++
++	phy_base->phy_ctl1.bits.res_scktmds = 0;  //
++	phy_base->phy_ctl0.bits.reg_csmps = 2;
++	phy_base->phy_ctl0.bits.reg_ck_test_sel = 0;  //?
++	phy_base->phy_ctl0.bits.reg_ck_sel = 1;
++	phy_base->phy_indbg_ctrl.bits.txdata_debugmode = 0;
++
++	// phy_enable
++	ret = sun20i_d1_hdmi_phy_enable(phy_base);
++	if (ret)
++		return ret;
++
++	phy_base->phy_ctl0.bits.sda_en = 1;
++	phy_base->phy_ctl0.bits.scl_en = 1;
++	phy_base->phy_ctl0.bits.hpd_en = 1;
++	phy_base->phy_ctl0.bits.reg_den = 0xF;
++	phy_base->pll_ctl0.bits.envbs = 1;
+ 
+ 	return 0;
+ }
+@@ -720,6 +875,7 @@ static int sun8i_hdmi_phy_probe(struct p
+ 		return dev_err_probe(dev, PTR_ERR(regs),
+ 				     "Couldn't map the HDMI PHY registers\n");
+ 
++	phy->base = regs;
+ 	phy->regs = devm_regmap_init_mmio(dev, regs,
+ 					  &sun8i_hdmi_phy_regmap_config);
+ 	if (IS_ERR(phy->regs))
diff --git a/target/linux/d1/patches-6.1/0010-riscv-mm-Use-IOMMU-for-DMA-when-available.patch b/target/linux/d1/patches-6.1/0010-riscv-mm-Use-IOMMU-for-DMA-when-available.patch
new file mode 100644
index 00000000000000..18dfa573e3a6aa
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0010-riscv-mm-Use-IOMMU-for-DMA-when-available.patch
@@ -0,0 +1,30 @@
+From 02a412de18479449c87ed7a332e3fe33d2eff3a4 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Wed, 27 Apr 2022 18:47:53 -0500
+Subject: [PATCH 010/117] riscv: mm: Use IOMMU for DMA when available
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/riscv/mm/dma-noncoherent.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/arch/riscv/mm/dma-noncoherent.c
++++ b/arch/riscv/mm/dma-noncoherent.c
+@@ -7,6 +7,7 @@
+ 
+ #include <linux/dma-direct.h>
+ #include <linux/dma-map-ops.h>
++#include <linux/iommu.h>
+ #include <linux/mm.h>
+ #include <asm/cacheflush.h>
+ 
+@@ -70,6 +71,9 @@ void arch_setup_dma_ops(struct device *d
+ 		   dev_driver_string(dev), dev_name(dev));
+ 
+ 	dev->dma_coherent = coherent;
++
++	if (iommu)
++		iommu_setup_dma_ops(dev, dma_base, dma_base + size - 1);
+ }
+ 
+ void riscv_noncoherent_supported(void)
diff --git a/target/linux/d1/patches-6.1/0011-genirq-Add-support-for-oneshot-safe-threaded-EOIs.patch b/target/linux/d1/patches-6.1/0011-genirq-Add-support-for-oneshot-safe-threaded-EOIs.patch
new file mode 100644
index 00000000000000..d8dd2878d1e4f9
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0011-genirq-Add-support-for-oneshot-safe-threaded-EOIs.patch
@@ -0,0 +1,124 @@
+From ee6459d60f24d91052f0288155f44e6a7f991050 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 7 May 2022 18:34:25 -0500
+Subject: [PATCH 011/117] genirq: Add support for oneshot-safe threaded EOIs
+
+irqchips can use the combination of flags IRQCHIP_ONESHOT_SAFE |
+IRQCHIP_EOI_THREADED to elide mask operations.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ kernel/irq/chip.c      | 36 +++++++++++++++++-------------------
+ kernel/irq/internals.h |  2 +-
+ kernel/irq/manage.c    | 12 ++++++------
+ 3 files changed, 24 insertions(+), 26 deletions(-)
+
+--- a/kernel/irq/chip.c
++++ b/kernel/irq/chip.c
+@@ -439,16 +439,6 @@ void unmask_irq(struct irq_desc *desc)
+ 	}
+ }
+ 
+-void unmask_threaded_irq(struct irq_desc *desc)
+-{
+-	struct irq_chip *chip = desc->irq_data.chip;
+-
+-	if (chip->flags & IRQCHIP_EOI_THREADED)
+-		chip->irq_eoi(&desc->irq_data);
+-
+-	unmask_irq(desc);
+-}
+-
+ /*
+  *	handle_nested_irq - Handle a nested irq from a irq thread
+  *	@irq:	the interrupt number
+@@ -656,25 +646,33 @@ out_unlock:
+ }
+ EXPORT_SYMBOL_GPL(handle_level_irq);
+ 
+-static void cond_unmask_eoi_irq(struct irq_desc *desc, struct irq_chip *chip)
++void unmask_eoi_threaded_irq(struct irq_desc *desc)
+ {
+-	if (!(desc->istate & IRQS_ONESHOT)) {
++	struct irq_chip *chip = desc->irq_data.chip;
++
++	if (desc->istate & IRQS_ONESHOT)
++		unmask_irq(desc);
++
++	if (chip->flags & IRQCHIP_EOI_THREADED)
+ 		chip->irq_eoi(&desc->irq_data);
++}
++
++static void cond_unmask_eoi_irq(struct irq_desc *desc, struct irq_chip *chip)
++{
++	/* Do not send EOI if the thread will do it for us. */
++	if ((chip->flags & IRQCHIP_EOI_THREADED) && desc->threads_oneshot)
+ 		return;
+-	}
++
+ 	/*
+ 	 * We need to unmask in the following cases:
+ 	 * - Oneshot irq which did not wake the thread (caused by a
+ 	 *   spurious interrupt or a primary handler handling it
+ 	 *   completely).
+ 	 */
+-	if (!irqd_irq_disabled(&desc->irq_data) &&
+-	    irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot) {
+-		chip->irq_eoi(&desc->irq_data);
++	if ((desc->istate & IRQS_ONESHOT) && !desc->threads_oneshot)
+ 		unmask_irq(desc);
+-	} else if (!(chip->flags & IRQCHIP_EOI_THREADED)) {
+-		chip->irq_eoi(&desc->irq_data);
+-	}
++
++	chip->irq_eoi(&desc->irq_data);
+ }
+ 
+ /**
+--- a/kernel/irq/internals.h
++++ b/kernel/irq/internals.h
+@@ -93,7 +93,7 @@ extern void irq_percpu_enable(struct irq
+ extern void irq_percpu_disable(struct irq_desc *desc, unsigned int cpu);
+ extern void mask_irq(struct irq_desc *desc);
+ extern void unmask_irq(struct irq_desc *desc);
+-extern void unmask_threaded_irq(struct irq_desc *desc);
++extern void unmask_eoi_threaded_irq(struct irq_desc *desc);
+ 
+ #ifdef CONFIG_SPARSE_IRQ
+ static inline void irq_mark_irq(unsigned int irq) { }
+--- a/kernel/irq/manage.c
++++ b/kernel/irq/manage.c
+@@ -1074,9 +1074,9 @@ static int irq_wait_for_interrupt(struct
+ static void irq_finalize_oneshot(struct irq_desc *desc,
+ 				 struct irqaction *action)
+ {
+-	if (!(desc->istate & IRQS_ONESHOT) ||
+-	    action->handler == irq_forced_secondary_handler)
++	if (action->handler == irq_forced_secondary_handler)
+ 		return;
++
+ again:
+ 	chip_bus_lock(desc);
+ 	raw_spin_lock_irq(&desc->lock);
+@@ -1112,9 +1112,8 @@ again:
+ 
+ 	desc->threads_oneshot &= ~action->thread_mask;
+ 
+-	if (!desc->threads_oneshot && !irqd_irq_disabled(&desc->irq_data) &&
+-	    irqd_irq_masked(&desc->irq_data))
+-		unmask_threaded_irq(desc);
++	if (!desc->threads_oneshot)
++		unmask_eoi_threaded_irq(desc);
+ 
+ out_unlock:
+ 	raw_spin_unlock_irq(&desc->lock);
+@@ -1662,7 +1661,8 @@ __setup_irq(unsigned int irq, struct irq
+ 	 * !ONESHOT irqs the thread mask is 0 so we can avoid a
+ 	 * conditional in irq_wake_thread().
+ 	 */
+-	if (new->flags & IRQF_ONESHOT) {
++	if ((new->flags & IRQF_ONESHOT) ||
++	    (desc->irq_data.chip->flags & (IRQCHIP_ONESHOT_SAFE | IRQCHIP_EOI_THREADED)) == (IRQCHIP_ONESHOT_SAFE | IRQCHIP_EOI_THREADED)) {
+ 		/*
+ 		 * Unlikely to have 32 resp 64 irqs sharing one line,
+ 		 * but who knows.
diff --git a/target/linux/d1/patches-6.1/0012-irqchip-sifive-plic-Enable-oneshot-safe-threaded-EOI.patch b/target/linux/d1/patches-6.1/0012-irqchip-sifive-plic-Enable-oneshot-safe-threaded-EOI.patch
new file mode 100644
index 00000000000000..429a5d6824839e
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0012-irqchip-sifive-plic-Enable-oneshot-safe-threaded-EOI.patch
@@ -0,0 +1,24 @@
+From 1fbe96ec05c41b313b4e7cc4b39b191b4a3f7540 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 7 May 2022 18:38:34 -0500
+Subject: [PATCH 012/117] irqchip/sifive-plic: Enable oneshot-safe threaded
+ EOIs
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/irqchip/irq-sifive-plic.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+--- a/drivers/irqchip/irq-sifive-plic.c
++++ b/drivers/irqchip/irq-sifive-plic.c
+@@ -201,7 +201,9 @@ static struct irq_chip plic_chip = {
+ 	.irq_set_affinity = plic_set_affinity,
+ #endif
+ 	.irq_set_type	= plic_irq_set_type,
+-	.flags		= IRQCHIP_AFFINITY_PRE_STARTUP,
++	.flags		= IRQCHIP_ONESHOT_SAFE |
++			  IRQCHIP_EOI_THREADED |
++			  IRQCHIP_AFFINITY_PRE_STARTUP,
+ };
+ 
+ static int plic_irq_set_type(struct irq_data *d, unsigned int type)
diff --git a/target/linux/d1/patches-6.1/0013-irqchip-sifive-plic-Support-wake-IRQs.patch b/target/linux/d1/patches-6.1/0013-irqchip-sifive-plic-Support-wake-IRQs.patch
new file mode 100644
index 00000000000000..e9033b7d6600c9
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0013-irqchip-sifive-plic-Support-wake-IRQs.patch
@@ -0,0 +1,32 @@
+From d6cf6473b0aaec455e48bccefe318a98a87b789f Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 28 May 2022 19:04:56 -0500
+Subject: [PATCH 013/117] irqchip/sifive-plic: Support wake IRQs
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/irqchip/irq-sifive-plic.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+--- a/drivers/irqchip/irq-sifive-plic.c
++++ b/drivers/irqchip/irq-sifive-plic.c
+@@ -187,7 +187,8 @@ static struct irq_chip plic_edge_chip =
+ 	.irq_set_affinity = plic_set_affinity,
+ #endif
+ 	.irq_set_type	= plic_irq_set_type,
+-	.flags		= IRQCHIP_AFFINITY_PRE_STARTUP,
++	.flags		= IRQCHIP_SKIP_SET_WAKE |
++			  IRQCHIP_AFFINITY_PRE_STARTUP,
+ };
+ 
+ static struct irq_chip plic_chip = {
+@@ -201,7 +202,8 @@ static struct irq_chip plic_chip = {
+ 	.irq_set_affinity = plic_set_affinity,
+ #endif
+ 	.irq_set_type	= plic_irq_set_type,
+-	.flags		= IRQCHIP_ONESHOT_SAFE |
++	.flags		= IRQCHIP_SKIP_SET_WAKE |
++			  IRQCHIP_ONESHOT_SAFE |
+ 			  IRQCHIP_EOI_THREADED |
+ 			  IRQCHIP_AFFINITY_PRE_STARTUP,
+ };
diff --git a/target/linux/d1/patches-6.1/0014-mmc-sunxi-mmc-Correct-the-maximum-segment-size.patch b/target/linux/d1/patches-6.1/0014-mmc-sunxi-mmc-Correct-the-maximum-segment-size.patch
new file mode 100644
index 00000000000000..7e8098a2cfb03e
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0014-mmc-sunxi-mmc-Correct-the-maximum-segment-size.patch
@@ -0,0 +1,65 @@
+From 0e871e791a2530562851109346affa1c0d9987e0 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 13 Jun 2021 23:15:56 -0500
+Subject: [PATCH 014/117] mmc: sunxi-mmc: Correct the maximum segment size
+
+According to the DMA descriptor documentation, the lowest two bits of
+the size field are ignored, so the size must be rounded up to a multiple
+of 4 bytes. Furthermore, 0 is not a valid buffer size; setting the size
+to 0 will cause that DMA descriptor to be ignored.
+
+Together, these restrictions limit the maximum DMA segment size to 4
+less than the power-of-two width of the size field.
+
+Series-to: Ulf Hansson <ulf.hansson@linaro.org>
+Series-to: linux-mmc@vger.kernel.org
+
+Fixes: 3cbcb16095f9 ("mmc: sunxi: Add driver for SD/MMC hosts found on Allwinner sunxi SoCs")
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/mmc/host/sunxi-mmc.c | 14 ++++++++------
+ 1 file changed, 8 insertions(+), 6 deletions(-)
+
+--- a/drivers/mmc/host/sunxi-mmc.c
++++ b/drivers/mmc/host/sunxi-mmc.c
+@@ -214,6 +214,9 @@
+ #define SDXC_IDMAC_DES0_CES	BIT(30) /* card error summary */
+ #define SDXC_IDMAC_DES0_OWN	BIT(31) /* 1-idma owns it, 0-host owns it */
+ 
++/* Buffer size must be a multiple of 4 bytes. */
++#define SDXC_IDMAC_SIZE_ALIGN	4
++
+ #define SDXC_CLK_400K		0
+ #define SDXC_CLK_25M		1
+ #define SDXC_CLK_50M		2
+@@ -361,17 +364,15 @@ static void sunxi_mmc_init_idma_des(stru
+ {
+ 	struct sunxi_idma_des *pdes = (struct sunxi_idma_des *)host->sg_cpu;
+ 	dma_addr_t next_desc = host->sg_dma;
+-	int i, max_len = (1 << host->cfg->idma_des_size_bits);
++	int i;
+ 
+ 	for (i = 0; i < data->sg_len; i++) {
+ 		pdes[i].config = cpu_to_le32(SDXC_IDMAC_DES0_CH |
+ 					     SDXC_IDMAC_DES0_OWN |
+ 					     SDXC_IDMAC_DES0_DIC);
+ 
+-		if (data->sg[i].length == max_len)
+-			pdes[i].buf_size = 0; /* 0 == max_len */
+-		else
+-			pdes[i].buf_size = cpu_to_le32(data->sg[i].length);
++		pdes[i].buf_size = cpu_to_le32(ALIGN(data->sg[i].length,
++						     SDXC_IDMAC_SIZE_ALIGN));
+ 
+ 		next_desc += sizeof(struct sunxi_idma_des);
+ 		pdes[i].buf_addr_ptr1 =
+@@ -1421,7 +1422,8 @@ static int sunxi_mmc_probe(struct platfo
+ 	mmc->max_blk_count	= 8192;
+ 	mmc->max_blk_size	= 4096;
+ 	mmc->max_segs		= PAGE_SIZE / sizeof(struct sunxi_idma_des);
+-	mmc->max_seg_size	= (1 << host->cfg->idma_des_size_bits);
++	mmc->max_seg_size	= (1 << host->cfg->idma_des_size_bits) -
++				  SDXC_IDMAC_SIZE_ALIGN;
+ 	mmc->max_req_size	= mmc->max_seg_size * mmc->max_segs;
+ 	/* 400kHz ~ 52MHz */
+ 	mmc->f_min		=   400000;
diff --git a/target/linux/d1/patches-6.1/0015-dt-bindings-display-Add-bindings-for-ClockworkPi-CWD.patch b/target/linux/d1/patches-6.1/0015-dt-bindings-display-Add-bindings-for-ClockworkPi-CWD.patch
new file mode 100644
index 00000000000000..665c55058cfa3f
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0015-dt-bindings-display-Add-bindings-for-ClockworkPi-CWD.patch
@@ -0,0 +1,82 @@
+From a8e905fb3fd0d26f724646275b72a7363b2f03d8 Mon Sep 17 00:00:00 2001
+From: Max Fierke <max@maxfierke.com>
+Date: Wed, 1 Jun 2022 00:17:47 -0500
+Subject: [PATCH 015/117] dt-bindings: display: Add bindings for ClockworkPi
+ CWD686
+
+The CWD686 is a 6.86" IPS LCD panel used as the primary
+display in the ClockworkPi DevTerm portable (all cores)
+
+Signed-off-by: Max Fierke <max@maxfierke.com>
+Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ .../display/panel/clockwork,cwd686.yaml       | 62 +++++++++++++++++++
+ 1 file changed, 62 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/display/panel/clockwork,cwd686.yaml
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/display/panel/clockwork,cwd686.yaml
+@@ -0,0 +1,62 @@
++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/display/panel/clockwork,cwd686.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Clockwork CWD686 6.86" IPS LCD panel
++
++maintainers:
++  - Max Fierke <max@maxfierke.com>
++
++description: |
++  The Clockwork CWD686 is a 6.86" ICNL9707-based IPS LCD panel used within the
++  Clockwork DevTerm series of portable devices. The panel has a 480x1280
++  resolution and uses 24 bit RGB per pixel.
++
++allOf:
++  - $ref: panel-common.yaml#
++
++properties:
++  compatible:
++    const: clockwork,cwd686
++
++  reg:
++    description: DSI virtual channel used by that screen
++    maxItems: 1
++
++  reset-gpios: true
++  rotation: true
++  backlight: true
++  iovcc-supply: true
++  vci-supply: true
++
++required:
++  - compatible
++  - reg
++  - backlight
++  - reset-gpios
++
++additionalProperties: false
++
++examples:
++  - |
++    #include <dt-bindings/gpio/gpio.h>
++
++    backlight: backlight {
++        compatible = "gpio-backlight";
++        gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
++    };
++
++    dsi {
++        #address-cells = <1>;
++        #size-cells = <0>;
++
++        panel@0 {
++            compatible = "clockwork,cwd686";
++            reg = <0>;
++            backlight = <&backlight>;
++            reset-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
++            rotation = <90>;
++        };
++    };
diff --git a/target/linux/d1/patches-6.1/0016-dt-bindings-display-Add-Sitronix-ST7701s-panel-bindi.patch b/target/linux/d1/patches-6.1/0016-dt-bindings-display-Add-Sitronix-ST7701s-panel-bindi.patch
new file mode 100644
index 00000000000000..85d8421f62eed0
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0016-dt-bindings-display-Add-Sitronix-ST7701s-panel-bindi.patch
@@ -0,0 +1,47 @@
+From d290546a88694dde6d2f64a973cd62ff2c69e27e Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Fri, 12 Aug 2022 01:59:35 -0500
+Subject: [PATCH 016/117] dt-bindings: display: Add Sitronix ST7701s panel
+ binding
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ .../display/panel/sitronix,st7701s.yaml       | 32 +++++++++++++++++++
+ 1 file changed, 32 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/display/panel/sitronix,st7701s.yaml
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/display/panel/sitronix,st7701s.yaml
+@@ -0,0 +1,32 @@
++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/display/panel/sitronix,st7701s.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Sitronix ST7701 based LCD panels
++
++maintainers:
++  - Samuel Holland <samuel@sholland.org>
++
++description: |
++  Panel used on Lichee RV 86 Panel
++
++allOf:
++  - $ref: panel-common.yaml#
++  - $ref: /schemas/spi/spi-peripheral-props.yaml#
++
++properties:
++  compatible:
++    items:
++      - const: sitronix,st7701s
++
++  backlight: true
++
++  reset-gpios: true
++
++required:
++  - compatible
++  - reset-gpios
++
++unevaluatedProperties: false
diff --git a/target/linux/d1/patches-6.1/0017-drm-panel-Add-driver-for-ST7701s-DPI-LCD-panel.patch b/target/linux/d1/patches-6.1/0017-drm-panel-Add-driver-for-ST7701s-DPI-LCD-panel.patch
new file mode 100644
index 00000000000000..535478cf9ef442
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0017-drm-panel-Add-driver-for-ST7701s-DPI-LCD-panel.patch
@@ -0,0 +1,487 @@
+From 9d9b8bd567c30a821c82c27035243536c5234542 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Tue, 29 Mar 2022 22:47:57 -0500
+Subject: [PATCH 017/117] drm/panel: Add driver for ST7701s DPI LCD panel
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/gpu/drm/panel/Kconfig                 |   8 +
+ drivers/gpu/drm/panel/Makefile                |   1 +
+ .../gpu/drm/panel/panel-sitronix-st7701s.c    | 444 ++++++++++++++++++
+ 3 files changed, 453 insertions(+)
+ create mode 100644 drivers/gpu/drm/panel/panel-sitronix-st7701s.c
+
+--- a/drivers/gpu/drm/panel/Kconfig
++++ b/drivers/gpu/drm/panel/Kconfig
+@@ -608,6 +608,14 @@ config DRM_PANEL_SITRONIX_ST7701
+ 	  ST7701 controller for 480X864 LCD panels with MIPI/RGB/SPI
+ 	  system interfaces.
+ 
++config DRM_PANEL_SITRONIX_ST7701S
++	tristate "Sitronix ST7701s panel driver"
++	depends on OF
++	depends on BACKLIGHT_CLASS_DEVICE
++	help
++	  Say Y here if you want to enable support for the Sitronix
++	  ST7701s controller with a SPI interface.
++
+ config DRM_PANEL_SITRONIX_ST7703
+ 	tristate "Sitronix ST7703 based MIPI touchscreen panels"
+ 	depends on OF
+--- a/drivers/gpu/drm/panel/Makefile
++++ b/drivers/gpu/drm/panel/Makefile
+@@ -61,6 +61,7 @@ obj-$(CONFIG_DRM_PANEL_SHARP_LS037V7DW01
+ obj-$(CONFIG_DRM_PANEL_SHARP_LS043T1LE01) += panel-sharp-ls043t1le01.o
+ obj-$(CONFIG_DRM_PANEL_SHARP_LS060T1SX01) += panel-sharp-ls060t1sx01.o
+ obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7701) += panel-sitronix-st7701.o
++obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7701S) += panel-sitronix-st7701s.o
+ obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7703) += panel-sitronix-st7703.o
+ obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7789V) += panel-sitronix-st7789v.o
+ obj-$(CONFIG_DRM_PANEL_SONY_ACX565AKM) += panel-sony-acx565akm.o
+--- /dev/null
++++ b/drivers/gpu/drm/panel/panel-sitronix-st7701s.c
+@@ -0,0 +1,444 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * Copyright (C) 2017 Free Electrons
++ */
++
++#include <linux/delay.h>
++#include <linux/gpio/consumer.h>
++#include <linux/module.h>
++#include <linux/spi/spi.h>
++
++#include <video/mipi_display.h>
++
++#include <drm/drm_device.h>
++#include <drm/drm_modes.h>
++#include <drm/drm_panel.h>
++
++struct st7701s {
++	struct drm_panel	panel;
++	struct gpio_desc	*reset;
++	struct spi_device	*spi;
++};
++
++enum {
++	ST7789V_COMMAND	= 0 << 8,
++	ST7789V_DATA	= 1 << 8,
++};
++
++#define LCD_WRITE_COMMAND(x)	(ST7789V_COMMAND | (x))
++#define LCD_WRITE_DATA(x)	(ST7789V_DATA | (x))
++
++static const u16 st7701s_init_sequence_1[] = {
++	LCD_WRITE_COMMAND(0xFF),
++	LCD_WRITE_DATA(0x77),
++	LCD_WRITE_DATA(0x01),
++	LCD_WRITE_DATA(0x00),
++	LCD_WRITE_DATA(0x00),
++	LCD_WRITE_DATA(0x10),
++
++	LCD_WRITE_COMMAND(0xC0),
++	LCD_WRITE_DATA(0x3B),
++	LCD_WRITE_DATA(0x00),
++
++	LCD_WRITE_COMMAND(0xC1),
++	LCD_WRITE_DATA(0x0D),
++	LCD_WRITE_DATA(0x02),
++
++	LCD_WRITE_COMMAND(0xC2),
++	LCD_WRITE_DATA(0x21),
++	LCD_WRITE_DATA(0x08),
++
++	// RGB Interface Setting
++	// LCD_WRITE_COMMAND(0xC3),
++	// LCD_WRITE_DATA(0x02),
++
++	LCD_WRITE_COMMAND(0xCD),
++	LCD_WRITE_DATA(0x18),//0F 08-OK  D0-D18
++
++	LCD_WRITE_COMMAND(0xB0),
++	LCD_WRITE_DATA(0x00),
++	LCD_WRITE_DATA(0x11),
++	LCD_WRITE_DATA(0x18),
++	LCD_WRITE_DATA(0x0E),
++	LCD_WRITE_DATA(0x11),
++	LCD_WRITE_DATA(0x06),
++	LCD_WRITE_DATA(0x07),
++	LCD_WRITE_DATA(0x08),
++	LCD_WRITE_DATA(0x07),
++	LCD_WRITE_DATA(0x22),
++	LCD_WRITE_DATA(0x04),
++	LCD_WRITE_DATA(0x12),
++	LCD_WRITE_DATA(0x0F),
++	LCD_WRITE_DATA(0xAA),
++	LCD_WRITE_DATA(0x31),
++	LCD_WRITE_DATA(0x18),
++
++	LCD_WRITE_COMMAND(0xB1),
++	LCD_WRITE_DATA(0x00),
++	LCD_WRITE_DATA(0x11),
++	LCD_WRITE_DATA(0x19),
++	LCD_WRITE_DATA(0x0E),
++	LCD_WRITE_DATA(0x12),
++	LCD_WRITE_DATA(0x07),
++	LCD_WRITE_DATA(0x08),
++	LCD_WRITE_DATA(0x08),
++	LCD_WRITE_DATA(0x08),
++	LCD_WRITE_DATA(0x22),
++	LCD_WRITE_DATA(0x04),
++	LCD_WRITE_DATA(0x11),
++	LCD_WRITE_DATA(0x11),
++	LCD_WRITE_DATA(0xA9),
++	LCD_WRITE_DATA(0x32),
++	LCD_WRITE_DATA(0x18),
++
++	LCD_WRITE_COMMAND(0xFF),
++	LCD_WRITE_DATA(0x77),
++	LCD_WRITE_DATA(0x01),
++	LCD_WRITE_DATA(0x00),
++	LCD_WRITE_DATA(0x00),
++	LCD_WRITE_DATA(0x11),
++
++	LCD_WRITE_COMMAND(0xB0),
++	LCD_WRITE_DATA(0x60),
++
++	LCD_WRITE_COMMAND(0xB1),
++	LCD_WRITE_DATA(0x30),
++
++	LCD_WRITE_COMMAND(0xB2),
++	LCD_WRITE_DATA(0x87),
++
++	LCD_WRITE_COMMAND(0xB3),
++	LCD_WRITE_DATA(0x80),
++
++	LCD_WRITE_COMMAND(0xB5),
++	LCD_WRITE_DATA(0x49),
++
++	LCD_WRITE_COMMAND(0xB7),
++	LCD_WRITE_DATA(0x85),
++
++	LCD_WRITE_COMMAND(0xB8),
++	LCD_WRITE_DATA(0x21),
++
++	LCD_WRITE_COMMAND(0xC1),
++	LCD_WRITE_DATA(0x78),
++
++	LCD_WRITE_COMMAND(0xC2),
++	LCD_WRITE_DATA(0x78),
++};
++
++static const u16 st7701s_init_sequence_2[] = {
++	LCD_WRITE_COMMAND(0xE0),
++	LCD_WRITE_DATA(0x00),
++	LCD_WRITE_DATA(0x1B),
++	LCD_WRITE_DATA(0x02),
++
++	LCD_WRITE_COMMAND(0xE1),
++	LCD_WRITE_DATA(0x08),
++	LCD_WRITE_DATA(0xA0),
++	LCD_WRITE_DATA(0x00),
++	LCD_WRITE_DATA(0x00),
++	LCD_WRITE_DATA(0x07),
++	LCD_WRITE_DATA(0xA0),
++	LCD_WRITE_DATA(0x00),
++	LCD_WRITE_DATA(0x00),
++	LCD_WRITE_DATA(0x00),
++	LCD_WRITE_DATA(0x44),
++	LCD_WRITE_DATA(0x44),
++
++	LCD_WRITE_COMMAND(0xE2),
++	LCD_WRITE_DATA(0x11),
++	LCD_WRITE_DATA(0x11),
++	LCD_WRITE_DATA(0x44),
++	LCD_WRITE_DATA(0x44),
++	LCD_WRITE_DATA(0xED),
++	LCD_WRITE_DATA(0xA0),
++	LCD_WRITE_DATA(0x00),
++	LCD_WRITE_DATA(0x00),
++	LCD_WRITE_DATA(0xEC),
++	LCD_WRITE_DATA(0xA0),
++	LCD_WRITE_DATA(0x00),
++	LCD_WRITE_DATA(0x00),
++
++	LCD_WRITE_COMMAND(0xE3),
++	LCD_WRITE_DATA(0x00),
++	LCD_WRITE_DATA(0x00),
++	LCD_WRITE_DATA(0x11),
++	LCD_WRITE_DATA(0x11),
++
++	LCD_WRITE_COMMAND(0xE4),
++	LCD_WRITE_DATA(0x44),
++	LCD_WRITE_DATA(0x44),
++
++	LCD_WRITE_COMMAND(0xE5),
++	LCD_WRITE_DATA(0x0A),
++	LCD_WRITE_DATA(0xE9),
++	LCD_WRITE_DATA(0xD8),
++	LCD_WRITE_DATA(0xA0),
++	LCD_WRITE_DATA(0x0C),
++	LCD_WRITE_DATA(0xEB),
++	LCD_WRITE_DATA(0xD8),
++	LCD_WRITE_DATA(0xA0),
++	LCD_WRITE_DATA(0x0E),
++	LCD_WRITE_DATA(0xED),
++	LCD_WRITE_DATA(0xD8),
++	LCD_WRITE_DATA(0xA0),
++	LCD_WRITE_DATA(0x10),
++	LCD_WRITE_DATA(0xEF),
++	LCD_WRITE_DATA(0xD8),
++	LCD_WRITE_DATA(0xA0),
++
++	LCD_WRITE_COMMAND(0xE6),
++	LCD_WRITE_DATA(0x00),
++	LCD_WRITE_DATA(0x00),
++	LCD_WRITE_DATA(0x11),
++	LCD_WRITE_DATA(0x11),
++
++	LCD_WRITE_COMMAND(0xE7),
++	LCD_WRITE_DATA(0x44),
++	LCD_WRITE_DATA(0x44),
++
++	LCD_WRITE_COMMAND(0xE8),
++	LCD_WRITE_DATA(0x09),
++	LCD_WRITE_DATA(0xE8),
++	LCD_WRITE_DATA(0xD8),
++	LCD_WRITE_DATA(0xA0),
++	LCD_WRITE_DATA(0x0B),
++	LCD_WRITE_DATA(0xEA),
++	LCD_WRITE_DATA(0xD8),
++	LCD_WRITE_DATA(0xA0),
++	LCD_WRITE_DATA(0x0D),
++	LCD_WRITE_DATA(0xEC),
++	LCD_WRITE_DATA(0xD8),
++	LCD_WRITE_DATA(0xA0),
++	LCD_WRITE_DATA(0x0F),
++	LCD_WRITE_DATA(0xEE),
++	LCD_WRITE_DATA(0xD8),
++	LCD_WRITE_DATA(0xA0),
++
++	LCD_WRITE_COMMAND(0xEB),
++	LCD_WRITE_DATA(0x02),
++	LCD_WRITE_DATA(0x00),
++	LCD_WRITE_DATA(0xE4),
++	LCD_WRITE_DATA(0xE4),
++	LCD_WRITE_DATA(0x88),
++	LCD_WRITE_DATA(0x00),
++	LCD_WRITE_DATA(0x40),
++
++	LCD_WRITE_COMMAND(0xEC),
++	LCD_WRITE_DATA(0x3C),
++	LCD_WRITE_DATA(0x00),
++
++	LCD_WRITE_COMMAND(0xED),
++	LCD_WRITE_DATA(0xAB),
++	LCD_WRITE_DATA(0x89),
++	LCD_WRITE_DATA(0x76),
++	LCD_WRITE_DATA(0x54),
++	LCD_WRITE_DATA(0x02),
++	LCD_WRITE_DATA(0xFF),
++	LCD_WRITE_DATA(0xFF),
++	LCD_WRITE_DATA(0xFF),
++	LCD_WRITE_DATA(0xFF),
++	LCD_WRITE_DATA(0xFF),
++	LCD_WRITE_DATA(0xFF),
++	LCD_WRITE_DATA(0x20),
++	LCD_WRITE_DATA(0x45),
++	LCD_WRITE_DATA(0x67),
++	LCD_WRITE_DATA(0x98),
++	LCD_WRITE_DATA(0xBA),
++
++	LCD_WRITE_COMMAND(0xFF),
++	LCD_WRITE_DATA(0x77),
++	LCD_WRITE_DATA(0x01),
++	LCD_WRITE_DATA(0x00),
++	LCD_WRITE_DATA(0x00),
++	LCD_WRITE_DATA(0x00),
++
++	LCD_WRITE_COMMAND(MIPI_DCS_SET_PIXEL_FORMAT),
++	LCD_WRITE_DATA(0x66),
++
++	LCD_WRITE_COMMAND(MIPI_DCS_SET_ADDRESS_MODE),
++	LCD_WRITE_DATA(0x00),
++
++	LCD_WRITE_COMMAND(MIPI_DCS_ENTER_INVERT_MODE),
++
++	LCD_WRITE_COMMAND(MIPI_DCS_EXIT_SLEEP_MODE),
++};
++
++static const u16 st7701s_enable_sequence[] = {
++	LCD_WRITE_COMMAND(MIPI_DCS_SET_DISPLAY_ON),
++};
++
++static const u16 st7701s_disable_sequence[] = {
++	LCD_WRITE_COMMAND(MIPI_DCS_SET_DISPLAY_OFF),
++};
++
++static inline struct st7701s *panel_to_st7701s(struct drm_panel *panel)
++{
++	return container_of(panel, struct st7701s, panel);
++}
++
++static int st7701s_spi_write(struct st7701s *ctx, const u16 *data, size_t size)
++{
++	struct spi_transfer xfer = { };
++	struct spi_message msg;
++
++	spi_message_init(&msg);
++
++	xfer.tx_buf = data;
++	xfer.bits_per_word = 9;
++	xfer.len = size;
++
++	spi_message_add_tail(&xfer, &msg);
++	return spi_sync(ctx->spi, &msg);
++}
++
++static const struct drm_display_mode default_mode = {
++	.clock		= 19800,
++	.hdisplay	= 480,
++	.hsync_start	= 480 + 60,
++	.hsync_end	= 480 + 60 + 12,
++	.htotal		= 480 + 60 + 12 + 60,
++	.vdisplay	= 480,
++	.vsync_start	= 480 + 18,
++	.vsync_end	= 480 + 18 + 4,
++	.vtotal		= 480 + 18 + 4 + 18,
++};
++
++static int st7701s_get_modes(struct drm_panel *panel,
++			     struct drm_connector *connector)
++{
++	struct drm_display_mode *mode;
++
++	mode = drm_mode_duplicate(connector->dev, &default_mode);
++	if (!mode)
++		return -ENOMEM;
++
++	drm_mode_set_name(mode);
++
++	mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
++	drm_mode_probed_add(connector, mode);
++
++	connector->display_info.width_mm = 70;
++	connector->display_info.height_mm = 72;
++
++	return 1;
++}
++
++static int st7701s_prepare(struct drm_panel *panel)
++{
++	struct st7701s *ctx = panel_to_st7701s(panel);
++
++	gpiod_set_value_cansleep(ctx->reset, 1);
++	msleep(20);
++
++	gpiod_set_value_cansleep(ctx->reset, 0);
++	msleep(20);
++
++	st7701s_spi_write(ctx, st7701s_init_sequence_1,
++			  sizeof(st7701s_init_sequence_1));
++	msleep(20);
++
++	st7701s_spi_write(ctx, st7701s_init_sequence_2,
++			  sizeof(st7701s_init_sequence_2));
++	msleep(120);
++
++	return 0;
++}
++
++static int st7701s_enable(struct drm_panel *panel)
++{
++	struct st7701s *ctx = panel_to_st7701s(panel);
++
++	st7701s_spi_write(ctx, st7701s_enable_sequence,
++			  sizeof(st7701s_enable_sequence));
++	msleep(20);
++
++	return 0;
++}
++
++static int st7701s_disable(struct drm_panel *panel)
++{
++	struct st7701s *ctx = panel_to_st7701s(panel);
++
++	st7701s_spi_write(ctx, st7701s_disable_sequence,
++			  sizeof(st7701s_disable_sequence));
++
++	return 0;
++}
++
++static int st7701s_unprepare(struct drm_panel *panel)
++{
++	return 0;
++}
++
++static const struct drm_panel_funcs st7701s_drm_funcs = {
++	.disable	= st7701s_disable,
++	.enable		= st7701s_enable,
++	.get_modes	= st7701s_get_modes,
++	.prepare	= st7701s_prepare,
++	.unprepare	= st7701s_unprepare,
++};
++
++static int st7701s_probe(struct spi_device *spi)
++{
++	struct device *dev = &spi->dev;
++	struct st7701s *ctx;
++	int ret;
++
++	ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
++	if (!ctx)
++		return -ENOMEM;
++
++	spi_set_drvdata(spi, ctx);
++	ctx->spi = spi;
++
++	ctx->reset = devm_gpiod_get(&spi->dev, "reset", GPIOD_OUT_LOW);
++	if (IS_ERR(ctx->reset)) {
++		dev_err(&spi->dev, "Couldn't get our reset line\n");
++		return PTR_ERR(ctx->reset);
++	}
++
++	drm_panel_init(&ctx->panel, dev, &st7701s_drm_funcs,
++		       DRM_MODE_CONNECTOR_DPI);
++
++	ret = drm_panel_of_backlight(&ctx->panel);
++	if (ret)
++		return ret;
++
++	drm_panel_add(&ctx->panel);
++
++	return 0;
++}
++
++static void st7701s_remove(struct spi_device *spi)
++{
++	struct st7701s *ctx = spi_get_drvdata(spi);
++
++	drm_panel_remove(&ctx->panel);
++}
++
++static const struct of_device_id st7701s_of_match[] = {
++	{ .compatible = "sitronix,st7701s" },
++	{ }
++};
++MODULE_DEVICE_TABLE(of, st7701s_of_match);
++
++static const struct spi_device_id st7701s_ids[] = {
++	{ "st7701s" },
++	{ }
++};
++MODULE_DEVICE_TABLE(spi, st7701s_ids);
++
++static struct spi_driver st7701s_driver = {
++	.probe = st7701s_probe,
++	.remove = st7701s_remove,
++	.driver = {
++		.name = "st7701s",
++		.of_match_table = st7701s_of_match,
++	},
++};
++module_spi_driver(st7701s_driver);
++
++MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
++MODULE_DESCRIPTION("Sitronix ST7701s LCD Driver");
++MODULE_LICENSE("GPL v2");
diff --git a/target/linux/d1/patches-6.1/0018-nvmem-sunxi_sid-Drop-the-workaround-on-A64.patch b/target/linux/d1/patches-6.1/0018-nvmem-sunxi_sid-Drop-the-workaround-on-A64.patch
new file mode 100644
index 00000000000000..1db6899a1994c5
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0018-nvmem-sunxi_sid-Drop-the-workaround-on-A64.patch
@@ -0,0 +1,42 @@
+From db71abf941d25b92b2117780d3771197417d1c81 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 31 Jul 2022 20:34:20 -0500
+Subject: [PATCH 018/117] nvmem: sunxi_sid: Drop the workaround on A64
+
+Now that the SRAM readout code is fixed by using 32-bit accesses, it
+always returns the same values as register readout, so the A64 variant
+no longer needs the workaround. This makes the D1 variant structure
+redundant, so remove it.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/nvmem/sunxi_sid.c | 8 +-------
+ 1 file changed, 1 insertion(+), 7 deletions(-)
+
+--- a/drivers/nvmem/sunxi_sid.c
++++ b/drivers/nvmem/sunxi_sid.c
+@@ -196,15 +196,9 @@ static const struct sunxi_sid_cfg sun8i_
+ 	.need_register_readout = true,
+ };
+ 
+-static const struct sunxi_sid_cfg sun20i_d1_cfg = {
+-	.value_offset = 0x200,
+-	.size = 0x100,
+-};
+-
+ static const struct sunxi_sid_cfg sun50i_a64_cfg = {
+ 	.value_offset = 0x200,
+ 	.size = 0x100,
+-	.need_register_readout = true,
+ };
+ 
+ static const struct sunxi_sid_cfg sun50i_h6_cfg = {
+@@ -217,7 +211,7 @@ static const struct of_device_id sunxi_s
+ 	{ .compatible = "allwinner,sun7i-a20-sid", .data = &sun7i_a20_cfg },
+ 	{ .compatible = "allwinner,sun8i-a83t-sid", .data = &sun50i_a64_cfg },
+ 	{ .compatible = "allwinner,sun8i-h3-sid", .data = &sun8i_h3_cfg },
+-	{ .compatible = "allwinner,sun20i-d1-sid", .data = &sun20i_d1_cfg },
++	{ .compatible = "allwinner,sun20i-d1-sid", .data = &sun50i_a64_cfg },
+ 	{ .compatible = "allwinner,sun50i-a64-sid", .data = &sun50i_a64_cfg },
+ 	{ .compatible = "allwinner,sun50i-h5-sid", .data = &sun50i_a64_cfg },
+ 	{ .compatible = "allwinner,sun50i-h6-sid", .data = &sun50i_h6_cfg },
diff --git a/target/linux/d1/patches-6.1/0019-dt-bindings-nvmem-Allow-bit-offsets-greater-than-a-b.patch b/target/linux/d1/patches-6.1/0019-dt-bindings-nvmem-Allow-bit-offsets-greater-than-a-b.patch
new file mode 100644
index 00000000000000..ee4a7f742bcd58
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0019-dt-bindings-nvmem-Allow-bit-offsets-greater-than-a-b.patch
@@ -0,0 +1,30 @@
+From d03341ef7acb64803ade6b173d24f49ffa6149a3 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Tue, 2 Aug 2022 00:29:32 -0500
+Subject: [PATCH 019/117] dt-bindings: nvmem: Allow bit offsets greater than a
+ byte
+
+Some NVMEM devices contain cells which do not start at a multiple of the
+device's stride. However, the "reg" property of a cell must be aligned
+to its provider device's stride.
+
+These cells can be represented in the DT using the "bits" property if
+that property allows offsets up to the full stride. 63 is chosen
+assuming that NVMEM devices will not have strides larger than 8 bytes.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ Documentation/devicetree/bindings/nvmem/nvmem.yaml | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/Documentation/devicetree/bindings/nvmem/nvmem.yaml
++++ b/Documentation/devicetree/bindings/nvmem/nvmem.yaml
+@@ -53,7 +53,7 @@ patternProperties:
+         $ref: /schemas/types.yaml#/definitions/uint32-array
+         items:
+           - minimum: 0
+-            maximum: 7
++            maximum: 63
+             description:
+               Offset in bit within the address range specified by reg.
+           - minimum: 1
diff --git a/target/linux/d1/patches-6.1/0020-regulator-dt-bindings-Add-Allwinner-D1-LDOs.patch b/target/linux/d1/patches-6.1/0020-regulator-dt-bindings-Add-Allwinner-D1-LDOs.patch
new file mode 100644
index 00000000000000..0e59af2f382e6a
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0020-regulator-dt-bindings-Add-Allwinner-D1-LDOs.patch
@@ -0,0 +1,156 @@
+From f666d95c1443854555044d3d4b52c463cf845ccc Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 17 Jul 2022 20:33:40 -0500
+Subject: [PATCH 020/117] regulator: dt-bindings: Add Allwinner D1 LDOs
+
+The Allwinner D1 SoC contains two pairs of in-package LDOs. One pair is
+for general purpose use. LDOA generally powers the board's 1.8 V rail.
+LDOB generally powers the in-package DRAM, where applicable.
+
+The other pair of LDOs powers the analog power domains inside the SoC,
+including the audio codec, thermal sensor, and ADCs. These LDOs require
+a 0.9 V bandgap voltage reference. The calibration value for the voltage
+reference is stored in an eFuse, accessed via an NVMEM cell.
+
+Neither LDO control register is in its own MMIO range; instead, each
+regulator device relies on a regmap/syscon exported by its parent.
+
+Series-changes: 2
+ - Remove syscon property from bindings
+ - Update binding examples to fix warnings and provide context
+
+Series-changes: 3
+ - Add "reg" property to bindings
+ - Add "unevaluatedProperties: true" to regulator nodes
+ - Minor changes to regulator node name patterns
+ - Remove system-ldos example (now added in patch 3)
+
+Series-changes: 4
+ - Fix the order of the maintainer/description sections
+ - Replace unevaluatedProperties with "additionalProperties: false"
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ .../allwinner,sun20i-d1-analog-ldos.yaml      | 74 +++++++++++++++++++
+ .../allwinner,sun20i-d1-system-ldos.yaml      | 37 ++++++++++
+ 2 files changed, 111 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/regulator/allwinner,sun20i-d1-analog-ldos.yaml
+ create mode 100644 Documentation/devicetree/bindings/regulator/allwinner,sun20i-d1-system-ldos.yaml
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/regulator/allwinner,sun20i-d1-analog-ldos.yaml
+@@ -0,0 +1,74 @@
++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/regulator/allwinner,sun20i-d1-analog-ldos.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Allwinner D1 Analog LDOs
++
++maintainers:
++  - Samuel Holland <samuel@sholland.org>
++
++description:
++  Allwinner D1 contains a set of LDOs which are designed to supply analog power
++  inside and outside the SoC. They are controlled by a register within the audio
++  codec MMIO space, but which is not part of the audio codec clock/reset domain.
++
++properties:
++  compatible:
++    enum:
++      - allwinner,sun20i-d1-analog-ldos
++
++  reg:
++    maxItems: 1
++
++  nvmem-cells:
++    items:
++      - description: NVMEM cell for the calibrated bandgap reference trim value
++
++  nvmem-cell-names:
++    items:
++      - const: bg_trim
++
++patternProperties:
++  "^(a|hp)ldo$":
++    type: object
++    $ref: regulator.yaml#
++    unevaluatedProperties: false
++
++required:
++  - compatible
++  - reg
++  - nvmem-cells
++  - nvmem-cell-names
++
++additionalProperties: false
++
++examples:
++  - |
++    audio-codec@2030000 {
++        compatible = "simple-mfd", "syscon";
++        reg = <0x2030000 0x1000>;
++        ranges;
++        #address-cells = <1>;
++        #size-cells = <1>;
++
++        regulators@2030348 {
++            compatible = "allwinner,sun20i-d1-analog-ldos";
++            reg = <0x2030348 0x4>;
++            nvmem-cells = <&bg_trim>;
++            nvmem-cell-names = "bg_trim";
++
++            reg_aldo: aldo {
++                regulator-min-microvolt = <1800000>;
++                regulator-max-microvolt = <1800000>;
++            };
++
++            reg_hpldo: hpldo {
++                regulator-min-microvolt = <1800000>;
++                regulator-max-microvolt = <1800000>;
++            };
++        };
++    };
++
++...
+--- /dev/null
++++ b/Documentation/devicetree/bindings/regulator/allwinner,sun20i-d1-system-ldos.yaml
+@@ -0,0 +1,37 @@
++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/regulator/allwinner,sun20i-d1-system-ldos.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Allwinner D1 System LDOs
++
++maintainers:
++  - Samuel Holland <samuel@sholland.org>
++
++description:
++  Allwinner D1 contains a pair of general-purpose LDOs which are designed to
++  supply power inside and outside the SoC. They are controlled by a register
++  within the system control MMIO space.
++
++properties:
++  compatible:
++    enum:
++      - allwinner,sun20i-d1-system-ldos
++
++  reg:
++    maxItems: 1
++
++patternProperties:
++  "^ldo[ab]$":
++    type: object
++    $ref: regulator.yaml#
++    unevaluatedProperties: false
++
++required:
++  - compatible
++  - reg
++
++additionalProperties: false
++
++...
diff --git a/target/linux/d1/patches-6.1/0021-regulator-sun20i-Add-support-for-Allwinner-D1-LDOs.patch b/target/linux/d1/patches-6.1/0021-regulator-sun20i-Add-support-for-Allwinner-D1-LDOs.patch
new file mode 100644
index 00000000000000..7a5b2a0e74ee60
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0021-regulator-sun20i-Add-support-for-Allwinner-D1-LDOs.patch
@@ -0,0 +1,294 @@
+From ad842bfb2eb10a75050dd69145ca59de982eb0e9 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 17 Jul 2022 11:46:52 -0500
+Subject: [PATCH 021/117] regulator: sun20i: Add support for Allwinner D1 LDOs
+
+D1 contains two pairs of LDOs. Since they have similar bindings, and
+they always exist together, put them in a single driver.
+
+The analog LDOs are relatively boring, with a single linear range. Their
+one quirk is that a bandgap reference must be calibrated for them to
+produce the correct voltage.
+
+The system LDOs have the complication that their voltage step is not an
+integer, so a custom .list_voltage is needed to get the rounding right.
+
+Series-changes: 2
+ - Use decimal numbers for .n_voltages instead of field widths
+ - Get the regmap from the parent device instead of a property/phandle
+
+Series-changes: 3
+ - Adjust control flow in sun20i_regulator_get_regmap() for clarity
+
+Reviewed-by: Heiko Stuebner <heiko@sntech.de>
+Tested-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/regulator/Kconfig            |   8 +
+ drivers/regulator/Makefile           |   1 +
+ drivers/regulator/sun20i-regulator.c | 232 +++++++++++++++++++++++++++
+ 3 files changed, 241 insertions(+)
+ create mode 100644 drivers/regulator/sun20i-regulator.c
+
+--- a/drivers/regulator/Kconfig
++++ b/drivers/regulator/Kconfig
+@@ -1280,6 +1280,14 @@ config REGULATOR_STW481X_VMMC
+ 	  This driver supports the internal VMMC regulator in the STw481x
+ 	  PMIC chips.
+ 
++config REGULATOR_SUN20I
++	tristate "Allwinner D1 internal LDOs"
++	depends on ARCH_SUNXI || COMPILE_TEST
++	depends on MFD_SYSCON && NVMEM
++	default ARCH_SUNXI
++	help
++	  This driver supports the internal LDOs in the Allwinner D1 SoC.
++
+ config REGULATOR_SY7636A
+ 	tristate "Silergy SY7636A voltage regulator"
+ 	depends on MFD_SY7636A
+--- a/drivers/regulator/Makefile
++++ b/drivers/regulator/Makefile
+@@ -150,6 +150,7 @@ obj-$(CONFIG_REGULATOR_STM32_VREFBUF) +=
+ obj-$(CONFIG_REGULATOR_STM32_PWR) += stm32-pwr.o
+ obj-$(CONFIG_REGULATOR_STPMIC1) += stpmic1_regulator.o
+ obj-$(CONFIG_REGULATOR_STW481X_VMMC) += stw481x-vmmc.o
++obj-$(CONFIG_REGULATOR_SUN20I) += sun20i-regulator.o
+ obj-$(CONFIG_REGULATOR_SY7636A) += sy7636a-regulator.o
+ obj-$(CONFIG_REGULATOR_SY8106A) += sy8106a-regulator.o
+ obj-$(CONFIG_REGULATOR_SY8824X) += sy8824x.o
+--- /dev/null
++++ b/drivers/regulator/sun20i-regulator.c
+@@ -0,0 +1,232 @@
++// SPDX-License-Identifier: GPL-2.0-only
++//
++// Copyright (c) 2021-2022 Samuel Holland <samuel@sholland.org>
++//
++
++#include <linux/mfd/syscon.h>
++#include <linux/module.h>
++#include <linux/nvmem-consumer.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include <linux/regmap.h>
++#include <linux/regulator/driver.h>
++
++#define SUN20I_POWER_REG		0x348
++
++#define SUN20I_SYS_LDO_CTRL_REG		0x150
++
++struct sun20i_regulator_data {
++	int				(*init)(struct device *dev,
++						struct regmap *regmap);
++	const struct regulator_desc	*descs;
++	unsigned int			ndescs;
++};
++
++static int sun20i_d1_analog_ldos_init(struct device *dev, struct regmap *regmap)
++{
++	u8 bg_trim;
++	int ret;
++
++	ret = nvmem_cell_read_u8(dev, "bg_trim", &bg_trim);
++	if (ret)
++		return dev_err_probe(dev, ret, "Failed to get bg_trim value\n");
++
++	/* The default value corresponds to 900 mV. */
++	if (!bg_trim)
++		bg_trim = 0x19;
++
++	return regmap_update_bits(regmap, SUN20I_POWER_REG,
++				  GENMASK(7, 0), bg_trim);
++}
++
++static const struct regulator_ops sun20i_d1_analog_ldo_ops = {
++	.list_voltage		= regulator_list_voltage_linear,
++	.map_voltage		= regulator_map_voltage_linear,
++	.set_voltage_sel	= regulator_set_voltage_sel_regmap,
++	.get_voltage_sel	= regulator_get_voltage_sel_regmap,
++	.enable			= regulator_enable_regmap,
++	.disable		= regulator_disable_regmap,
++	.is_enabled		= regulator_is_enabled_regmap,
++};
++
++static const struct regulator_desc sun20i_d1_analog_ldo_descs[] = {
++	{
++		.name		= "aldo",
++		.supply_name	= "vdd33",
++		.of_match	= "aldo",
++		.ops		= &sun20i_d1_analog_ldo_ops,
++		.type		= REGULATOR_VOLTAGE,
++		.owner		= THIS_MODULE,
++		.n_voltages	= 8,
++		.min_uV		= 1650000,
++		.uV_step	= 50000,
++		.vsel_reg	= SUN20I_POWER_REG,
++		.vsel_mask	= GENMASK(14, 12),
++		.enable_reg	= SUN20I_POWER_REG,
++		.enable_mask	= BIT(31),
++	},
++	{
++		.name		= "hpldo",
++		.supply_name	= "hpldoin",
++		.of_match	= "hpldo",
++		.ops		= &sun20i_d1_analog_ldo_ops,
++		.type		= REGULATOR_VOLTAGE,
++		.owner		= THIS_MODULE,
++		.n_voltages	= 8,
++		.min_uV		= 1650000,
++		.uV_step	= 50000,
++		.vsel_reg	= SUN20I_POWER_REG,
++		.vsel_mask	= GENMASK(10, 8),
++		.enable_reg	= SUN20I_POWER_REG,
++		.enable_mask	= BIT(30),
++	},
++};
++
++static const struct sun20i_regulator_data sun20i_d1_analog_ldos = {
++	.init	= sun20i_d1_analog_ldos_init,
++	.descs	= sun20i_d1_analog_ldo_descs,
++	.ndescs	= ARRAY_SIZE(sun20i_d1_analog_ldo_descs),
++};
++
++/* regulator_list_voltage_linear() modified for the non-integral uV_step. */
++static int sun20i_d1_system_ldo_list_voltage(struct regulator_dev *rdev,
++					     unsigned int selector)
++{
++	const struct regulator_desc *desc = rdev->desc;
++	unsigned int uV;
++
++	if (selector >= desc->n_voltages)
++		return -EINVAL;
++
++	uV = desc->min_uV + (desc->uV_step * selector);
++
++	/* Produce correctly-rounded absolute voltages. */
++	return uV + ((selector + 1 + (desc->min_uV % 4)) / 3);
++}
++
++static const struct regulator_ops sun20i_d1_system_ldo_ops = {
++	.list_voltage		= sun20i_d1_system_ldo_list_voltage,
++	.map_voltage		= regulator_map_voltage_ascend,
++	.set_voltage_sel	= regulator_set_voltage_sel_regmap,
++	.get_voltage_sel	= regulator_get_voltage_sel_regmap,
++};
++
++static const struct regulator_desc sun20i_d1_system_ldo_descs[] = {
++	{
++		.name		= "ldoa",
++		.supply_name	= "ldo-in",
++		.of_match	= "ldoa",
++		.ops		= &sun20i_d1_system_ldo_ops,
++		.type		= REGULATOR_VOLTAGE,
++		.owner		= THIS_MODULE,
++		.n_voltages	= 32,
++		.min_uV		= 1600000,
++		.uV_step	= 13333, /* repeating */
++		.vsel_reg	= SUN20I_SYS_LDO_CTRL_REG,
++		.vsel_mask	= GENMASK(7, 0),
++	},
++	{
++		.name		= "ldob",
++		.supply_name	= "ldo-in",
++		.of_match	= "ldob",
++		.ops		= &sun20i_d1_system_ldo_ops,
++		.type		= REGULATOR_VOLTAGE,
++		.owner		= THIS_MODULE,
++		.n_voltages	= 64,
++		.min_uV		= 1166666,
++		.uV_step	= 13333, /* repeating */
++		.vsel_reg	= SUN20I_SYS_LDO_CTRL_REG,
++		.vsel_mask	= GENMASK(15, 8),
++	},
++};
++
++static const struct sun20i_regulator_data sun20i_d1_system_ldos = {
++	.descs	= sun20i_d1_system_ldo_descs,
++	.ndescs	= ARRAY_SIZE(sun20i_d1_system_ldo_descs),
++};
++
++static const struct of_device_id sun20i_regulator_of_match[] = {
++	{
++		.compatible = "allwinner,sun20i-d1-analog-ldos",
++		.data = &sun20i_d1_analog_ldos,
++	},
++	{
++		.compatible = "allwinner,sun20i-d1-system-ldos",
++		.data = &sun20i_d1_system_ldos,
++	},
++	{ },
++};
++MODULE_DEVICE_TABLE(of, sun20i_regulator_of_match);
++
++static struct regmap *sun20i_regulator_get_regmap(struct device *dev)
++{
++	struct regmap *regmap;
++
++	/*
++	 * First try the syscon interface. The system control device is not
++	 * compatible with "syscon", so fall back to getting the regmap from
++	 * its platform device. This is ugly, but required for devicetree
++	 * backward compatibility.
++	 */
++	regmap = syscon_node_to_regmap(dev->parent->of_node);
++	if (!IS_ERR(regmap))
++		return regmap;
++
++	regmap = dev_get_regmap(dev->parent, NULL);
++	if (regmap)
++		return regmap;
++
++	return ERR_PTR(-EPROBE_DEFER);
++}
++
++static int sun20i_regulator_probe(struct platform_device *pdev)
++{
++	const struct sun20i_regulator_data *data;
++	struct device *dev = &pdev->dev;
++	struct regulator_config config;
++	struct regmap *regmap;
++	int ret;
++
++	data = of_device_get_match_data(dev);
++	if (!data)
++		return -EINVAL;
++
++	regmap = sun20i_regulator_get_regmap(dev);
++	if (IS_ERR(regmap))
++		return dev_err_probe(dev, PTR_ERR(regmap), "Failed to get regmap\n");
++
++	if (data->init) {
++		ret = data->init(dev, regmap);
++		if (ret)
++			return ret;
++	}
++
++	config = (struct regulator_config) {
++		.dev	= dev,
++		.regmap	= regmap,
++	};
++
++	for (unsigned int i = 0; i < data->ndescs; ++i) {
++		const struct regulator_desc *desc = &data->descs[i];
++		struct regulator_dev *rdev;
++
++		rdev = devm_regulator_register(dev, desc, &config);
++		if (IS_ERR(rdev))
++			return PTR_ERR(rdev);
++	}
++
++	return 0;
++}
++
++static struct platform_driver sun20i_regulator_driver = {
++	.probe	= sun20i_regulator_probe,
++	.driver	= {
++		.name		= "sun20i-regulator",
++		.of_match_table	= sun20i_regulator_of_match,
++	},
++};
++module_platform_driver(sun20i_regulator_driver);
++
++MODULE_AUTHOR("Samuel Holland <samuel@sholland.org>");
++MODULE_DESCRIPTION("Allwinner D1 internal LDO driver");
++MODULE_LICENSE("GPL");
diff --git a/target/linux/d1/patches-6.1/0022-dt-bindings-sram-sunxi-sram-Add-optional-regulators-.patch b/target/linux/d1/patches-6.1/0022-dt-bindings-sram-sunxi-sram-Add-optional-regulators-.patch
new file mode 100644
index 00000000000000..9e24a75927074a
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0022-dt-bindings-sram-sunxi-sram-Add-optional-regulators-.patch
@@ -0,0 +1,68 @@
+From 52c6979628d596018e9259767bff4def25e449dc Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Mon, 1 Aug 2022 23:57:19 -0500
+Subject: [PATCH 022/117] dt-bindings: sram: sunxi-sram: Add optional
+ regulators child
+
+Some sunxi SoCs have in-package regulators controlled by a register in
+the system control MMIO block. Allow a child node for these regulators
+in addition to SRAM child nodes.
+
+Commit-changes: 2
+ - New patch for v2
+
+Series-changes: 3
+ - Require the regulators node to have a unit address
+ - Reference the regulator schema from the SRAM controller schema
+ - Move the system LDOs example to the SRAM controller schema
+ - Reorder the patches so the example passes validation
+
+Series-changes: 4
+ - Remove unevaluatedProperties from regulators schema reference
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ .../allwinner,sun4i-a10-system-control.yaml   | 28 +++++++++++++++++++
+ 1 file changed, 28 insertions(+)
+
+--- a/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml
++++ b/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml
+@@ -56,6 +56,9 @@ properties:
+   ranges: true
+ 
+ patternProperties:
++  "^regulators@[0-9a-f]+$":
++    $ref: /schemas/regulator/allwinner,sun20i-d1-system-ldos.yaml#
++
+   "^sram@[a-z0-9]+":
+     type: object
+ 
+@@ -130,3 +133,28 @@ examples:
+         };
+       };
+     };
++
++  - |
++    syscon@3000000 {
++      compatible = "allwinner,sun20i-d1-system-control";
++      reg = <0x3000000 0x1000>;
++      ranges;
++      #address-cells = <1>;
++      #size-cells = <1>;
++
++      regulators@3000150 {
++        compatible = "allwinner,sun20i-d1-system-ldos";
++        reg = <0x3000150 0x4>;
++
++        reg_ldoa: ldoa {
++          regulator-min-microvolt = <1800000>;
++          regulator-max-microvolt = <1800000>;
++        };
++
++        reg_ldob: ldob {
++          regulator-name = "vcc-dram";
++          regulator-min-microvolt = <1500000>;
++          regulator-max-microvolt = <1500000>;
++        };
++      };
++    };
diff --git a/target/linux/d1/patches-6.1/0023-soc-sunxi-sram-Only-iterate-over-SRAM-children.patch b/target/linux/d1/patches-6.1/0023-soc-sunxi-sram-Only-iterate-over-SRAM-children.patch
new file mode 100644
index 00000000000000..4544cb3c38e454
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0023-soc-sunxi-sram-Only-iterate-over-SRAM-children.patch
@@ -0,0 +1,50 @@
+From 1946ff7ee38c994ae3eb9968c5b51695c0df2cf7 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Tue, 2 Aug 2022 00:01:21 -0500
+Subject: [PATCH 023/117] soc: sunxi: sram: Only iterate over SRAM children
+
+Now that a "regulators" child is accepted by the controller binding, the
+debugfs show routine must be explicitly limited to "sram" children.
+
+Series-to: Liam Girdwood <lgirdwood@gmail.com>
+Series-to: Mark Brown <broonie@kernel.org>
+Series-to: Chen-Yu Tsai <wens@csie.org>
+Series-to: Jernej Skrabec <jernej.skrabec@gmail.com>
+Series-to: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
+Series-to: Rob Herring <robh+dt@kernel.org>
+
+Commit-changes: 2
+ - New patch for v2
+
+Series-version: 4
+
+Cover-letter:
+regulator: Add support for Allwinner D1 LDOs
+This series adds bindings and a driver for the two pairs of LDOs
+inside the Allwinner D1 SoC.
+
+A binding and driver change is required for the SRAM controller, to
+accept the regulators device as its child node. The new example in the
+SRAM controller binding uses the compatible string added in this series:
+https://lore.kernel.org/lkml/20220815041248.53268-1-samuel@sholland.org/
+END
+
+Reviewed-by: Heiko Stuebner <heiko@sntech.de>
+Tested-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/soc/sunxi/sunxi_sram.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/drivers/soc/sunxi/sunxi_sram.c
++++ b/drivers/soc/sunxi/sunxi_sram.c
+@@ -120,6 +120,9 @@ static int sunxi_sram_show(struct seq_fi
+ 	seq_puts(s, "--------------------\n\n");
+ 
+ 	for_each_child_of_node(sram_dev->of_node, sram_node) {
++		if (!of_node_name_eq(sram_node, "sram"))
++			continue;
++
+ 		sram_addr_p = of_get_address(sram_node, 0, NULL, NULL);
+ 
+ 		seq_printf(s, "sram@%08x\n",
diff --git a/target/linux/d1/patches-6.1/0024-MAINTAINERS-Match-the-sun20i-family-of-Allwinner-SoC.patch b/target/linux/d1/patches-6.1/0024-MAINTAINERS-Match-the-sun20i-family-of-Allwinner-SoC.patch
new file mode 100644
index 00000000000000..442e9865b69599
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0024-MAINTAINERS-Match-the-sun20i-family-of-Allwinner-SoC.patch
@@ -0,0 +1,26 @@
+From 25727569379b42593b55cfb743b7eff4cfa1cce2 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 14 Aug 2022 23:45:50 -0500
+Subject: [PATCH 024/117] MAINTAINERS: Match the sun20i family of Allwinner
+ SoCs
+
+Allwinner sunxi SoCs with a RISC-V CPU use the sun20i designator. Match
+that pattern in addition to the designators for 32 and 64-bit ARM SoCs.
+
+Reviewed-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ MAINTAINERS | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -1828,7 +1828,7 @@ F:	drivers/pinctrl/sunxi/
+ F:	drivers/soc/sunxi/
+ N:	allwinner
+ N:	sun[x456789]i
+-N:	sun50i
++N:	sun[25]0i
+ 
+ ARM/Amlogic Meson SoC CLOCK FRAMEWORK
+ M:	Neil Armstrong <neil.armstrong@linaro.org>
diff --git a/target/linux/d1/patches-6.1/0025-dt-bindings-riscv-Add-T-HEAD-C906-and-C910-compatibl.patch b/target/linux/d1/patches-6.1/0025-dt-bindings-riscv-Add-T-HEAD-C906-and-C910-compatibl.patch
new file mode 100644
index 00000000000000..357cc1e4194e9b
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0025-dt-bindings-riscv-Add-T-HEAD-C906-and-C910-compatibl.patch
@@ -0,0 +1,27 @@
+From 4ae663dbc373f5690581cee16d3667693eb9d73e Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 16 May 2021 14:05:17 -0500
+Subject: [PATCH 025/117] dt-bindings: riscv: Add T-HEAD C906 and C910
+ compatibles
+
+The C906 and C910 are RISC-V CPU cores from T-HEAD Semiconductor.
+Notably, the C906 core is used in the Allwinner D1 SoC.
+
+Acked-by: Rob Herring <robh@kernel.org>
+Reviewed-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ Documentation/devicetree/bindings/riscv/cpus.yaml | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
++++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
+@@ -39,6 +39,8 @@ properties:
+               - sifive,u5
+               - sifive,u7
+               - canaan,k210
++              - thead,c906
++              - thead,c910
+           - const: riscv
+       - items:
+           - enum:
diff --git a/target/linux/d1/patches-6.1/0026-dt-bindings-vendor-prefixes-Add-Allwinner-D1-board-v.patch b/target/linux/d1/patches-6.1/0026-dt-bindings-vendor-prefixes-Add-Allwinner-D1-board-v.patch
new file mode 100644
index 00000000000000..ca4d7c42954594
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0026-dt-bindings-vendor-prefixes-Add-Allwinner-D1-board-v.patch
@@ -0,0 +1,42 @@
+From d0c24deb787a95515d355eea68e0402bfec77f75 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 17 Jul 2022 14:42:05 -0500
+Subject: [PATCH 026/117] dt-bindings: vendor-prefixes: Add Allwinner D1 board
+ vendors
+
+Some boards using the Allwinner D1 SoC are made by vendors not
+previously documented.
+
+Clockwork Tech LLC (https://www.clockworkpi.com/) manufactures the
+ClockworkPi and DevTerm boards.
+
+Beijing Widora Technology Co., Ltd. (https://mangopi.cc/) manufactures
+the MangoPi family of boards.
+
+Acked-by: Rob Herring <robh@kernel.org>
+Reviewed-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ Documentation/devicetree/bindings/vendor-prefixes.yaml | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
++++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
+@@ -260,6 +260,8 @@ patternProperties:
+     description: Cirrus Logic, Inc.
+   "^cisco,.*":
+     description: Cisco Systems, Inc.
++  "^clockwork,.*":
++    description: Clockwork Tech LLC
+   "^cloudengines,.*":
+     description: Cloud Engines, Inc.
+   "^cnm,.*":
+@@ -1424,6 +1426,8 @@ patternProperties:
+     description: Shenzhen whwave Electronics, Inc.
+   "^wi2wi,.*":
+     description: Wi2Wi, Inc.
++  "^widora,.*":
++    description: Beijing Widora Technology Co., Ltd.
+   "^wiligear,.*":
+     description: Wiligear, Ltd.
+   "^willsemi,.*":
diff --git a/target/linux/d1/patches-6.1/0027-dt-bindings-riscv-Add-Allwinner-D1-board-compatibles.patch b/target/linux/d1/patches-6.1/0027-dt-bindings-riscv-Add-Allwinner-D1-board-compatibles.patch
new file mode 100644
index 00000000000000..6fd802e68b83c1
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0027-dt-bindings-riscv-Add-Allwinner-D1-board-compatibles.patch
@@ -0,0 +1,85 @@
+From 4d7c04f210dd401f3560a7f53c78d6e058d182e2 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Wed, 29 Jun 2022 00:26:39 -0500
+Subject: [PATCH 027/117] dt-bindings: riscv: Add Allwinner D1 board
+ compatibles
+
+Several SoMs and boards are available that feature the Allwinner D1 SoC.
+Document their compatible strings.
+
+Acked-by: Rob Herring <robh@kernel.org>
+Reviewed-by: Heiko Stuebner <heiko@sntech.de>
+Tested-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ .../devicetree/bindings/riscv/sunxi.yaml      | 64 +++++++++++++++++++
+ 1 file changed, 64 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/riscv/sunxi.yaml
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/riscv/sunxi.yaml
+@@ -0,0 +1,64 @@
++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/riscv/sunxi.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Allwinner RISC-V SoC-based boards
++
++maintainers:
++  - Chen-Yu Tsai <wens@csie.org>
++  - Jernej Skrabec <jernej.skrabec@gmail.com>
++  - Samuel Holland <samuel@sholland.org>
++
++description:
++  Allwinner RISC-V SoC-based boards
++
++properties:
++  $nodename:
++    const: '/'
++  compatible:
++    oneOf:
++      - description: Dongshan Nezha STU SoM
++        items:
++          - const: 100ask,dongshan-nezha-stu
++          - const: allwinner,sun20i-d1
++
++      - description: D1 Nezha board
++        items:
++          - const: allwinner,d1-nezha
++          - const: allwinner,sun20i-d1
++
++      - description: ClockworkPi R-01 SoM and v3.14 board
++        items:
++          - const: clockwork,r-01-clockworkpi-v3.14
++          - const: allwinner,sun20i-d1
++
++      - description: ClockworkPi R-01 SoM, v3.14 board, and DevTerm expansion
++        items:
++          - const: clockwork,r-01-devterm-v3.14
++          - const: clockwork,r-01-clockworkpi-v3.14
++          - const: allwinner,sun20i-d1
++
++      - description: Lichee RV SoM
++        items:
++          - const: sipeed,lichee-rv
++          - const: allwinner,sun20i-d1
++
++      - description: Carrier boards for the Lichee RV SoM
++        items:
++          - enum:
++              - sipeed,lichee-rv-86-panel-480p
++              - sipeed,lichee-rv-86-panel-720p
++              - sipeed,lichee-rv-dock
++          - const: sipeed,lichee-rv
++          - const: allwinner,sun20i-d1
++
++      - description: MangoPi MQ Pro board
++        items:
++          - const: widora,mangopi-mq-pro
++          - const: allwinner,sun20i-d1
++
++additionalProperties: true
++
++...
diff --git a/target/linux/d1/patches-6.1/0028-riscv-dts-allwinner-Add-the-D1-SoC-base-devicetree.patch b/target/linux/d1/patches-6.1/0028-riscv-dts-allwinner-Add-the-D1-SoC-base-devicetree.patch
new file mode 100644
index 00000000000000..6f414495945532
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0028-riscv-dts-allwinner-Add-the-D1-SoC-base-devicetree.patch
@@ -0,0 +1,936 @@
+From 20d565fb9324b0d2791d10cb65560eddd2ef526e Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Tue, 28 Jun 2022 23:20:33 -0500
+Subject: [PATCH 028/117] riscv: dts: allwinner: Add the D1 SoC base devicetree
+
+D1 is a SoC containing a single-core T-HEAD Xuantie C906 CPU, as well as
+one HiFi 4 DSP. The SoC is based on a design that additionally contained
+a pair of Cortex A7's. For that reason, some peripherals are duplicated.
+
+This devicetree includes all of the peripherals that already have a
+documented binding.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/riscv/boot/dts/Makefile                 |   1 +
+ arch/riscv/boot/dts/allwinner/Makefile       |   1 +
+ arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 900 +++++++++++++++++++
+ 3 files changed, 902 insertions(+)
+ create mode 100644 arch/riscv/boot/dts/allwinner/Makefile
+ create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
+
+--- a/arch/riscv/boot/dts/Makefile
++++ b/arch/riscv/boot/dts/Makefile
+@@ -1,4 +1,5 @@
+ # SPDX-License-Identifier: GPL-2.0
++subdir-y += allwinner
+ subdir-y += sifive
+ subdir-y += starfive
+ subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
+--- /dev/null
++++ b/arch/riscv/boot/dts/allwinner/Makefile
+@@ -0,0 +1 @@
++# SPDX-License-Identifier: GPL-2.0
+--- /dev/null
++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
+@@ -0,0 +1,900 @@
++// SPDX-License-Identifier: (GPL-2.0+ or MIT)
++// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
++
++#include <dt-bindings/clock/sun6i-rtc.h>
++#include <dt-bindings/clock/sun8i-de2.h>
++#include <dt-bindings/clock/sun8i-tcon-top.h>
++#include <dt-bindings/clock/sun20i-d1-ccu.h>
++#include <dt-bindings/clock/sun20i-d1-r-ccu.h>
++#include <dt-bindings/interrupt-controller/irq.h>
++#include <dt-bindings/reset/sun8i-de2.h>
++#include <dt-bindings/reset/sun20i-d1-ccu.h>
++#include <dt-bindings/reset/sun20i-d1-r-ccu.h>
++#include <dt-bindings/thermal/thermal.h>
++
++/ {
++	#address-cells = <1>;
++	#size-cells = <1>;
++
++	cpus {
++		timebase-frequency = <24000000>;
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		cpu0: cpu@0 {
++			compatible = "thead,c906", "riscv";
++			device_type = "cpu";
++			reg = <0>;
++			clocks = <&ccu CLK_RISCV>;
++			clock-frequency = <24000000>;
++			d-cache-block-size = <64>;
++			d-cache-sets = <256>;
++			d-cache-size = <32768>;
++			i-cache-block-size = <64>;
++			i-cache-sets = <128>;
++			i-cache-size = <32768>;
++			mmu-type = "riscv,sv39";
++			riscv,isa = "rv64imafdc";
++			#cooling-cells = <2>;
++
++			cpu0_intc: interrupt-controller {
++				compatible = "riscv,cpu-intc";
++				interrupt-controller;
++				#address-cells = <0>;
++				#interrupt-cells = <1>;
++			};
++		};
++	};
++
++	de: display-engine {
++		compatible = "allwinner,sun20i-d1-display-engine";
++		allwinner,pipelines = <&mixer0>, <&mixer1>;
++		status = "disabled";
++	};
++
++	osc24M: osc24M-clk {
++		compatible = "fixed-clock";
++		clock-frequency = <24000000>;
++		clock-output-names = "osc24M";
++		#clock-cells = <0>;
++	};
++
++	soc {
++		compatible = "simple-bus";
++		ranges;
++		interrupt-parent = <&plic>;
++		dma-noncoherent;
++		#address-cells = <1>;
++		#size-cells = <1>;
++
++		dsp_wdt: watchdog@1700400 {
++			compatible = "allwinner,sun20i-d1-wdt";
++			reg = <0x1700400 0x20>;
++			interrupts = <138 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&osc24M>, <&rtc CLK_OSC32K>;
++			clock-names = "hosc", "losc";
++			status = "reserved";
++		};
++
++		pio: pinctrl@2000000 {
++			compatible = "allwinner,sun20i-d1-pinctrl";
++			reg = <0x2000000 0x800>;
++			interrupts = <85 IRQ_TYPE_LEVEL_HIGH>,
++				     <87 IRQ_TYPE_LEVEL_HIGH>,
++				     <89 IRQ_TYPE_LEVEL_HIGH>,
++				     <91 IRQ_TYPE_LEVEL_HIGH>,
++				     <93 IRQ_TYPE_LEVEL_HIGH>,
++				     <95 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_APB0>,
++				 <&osc24M>,
++				 <&rtc CLK_OSC32K>;
++			clock-names = "apb", "hosc", "losc";
++			gpio-controller;
++			interrupt-controller;
++			#gpio-cells = <3>;
++			#interrupt-cells = <3>;
++
++			/omit-if-no-ref/
++			i2c0_pb10_pins: i2c0-pb10-pins {
++				pins = "PB10", "PB11";
++				function = "i2c0";
++			};
++
++			/omit-if-no-ref/
++			i2c2_pb0_pins: i2c2-pb0-pins {
++				pins = "PB0", "PB1";
++				function = "i2c2";
++			};
++
++			/omit-if-no-ref/
++			lcd_rgb666_pins: lcd-rgb666-pins {
++				pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
++				       "PD6", "PD7", "PD8", "PD9", "PD10", "PD11",
++				       "PD12", "PD13", "PD14", "PD15", "PD16", "PD17",
++				       "PD18", "PD19", "PD20", "PD21";
++				function = "lcd0";
++			};
++
++			/omit-if-no-ref/
++			mmc0_pins: mmc0-pins {
++				pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
++				function = "mmc0";
++			};
++
++			/omit-if-no-ref/
++			mmc1_pins: mmc1-pins {
++				pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5";
++				function = "mmc1";
++			};
++
++			/omit-if-no-ref/
++			mmc2_pins: mmc2-pins {
++				pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7";
++				function = "mmc2";
++			};
++
++			/omit-if-no-ref/
++			rgmii_pe_pins: rgmii-pe-pins {
++				pins = "PE0", "PE1", "PE2", "PE3", "PE4",
++				       "PE5", "PE6", "PE7", "PE8", "PE9",
++				       "PE11", "PE12", "PE13", "PE14", "PE15";
++				function = "emac";
++			};
++
++			/omit-if-no-ref/
++			rmii_pe_pins: rmii-pe-pins {
++				pins = "PE0", "PE1", "PE2", "PE3", "PE4",
++				       "PE5", "PE6", "PE7", "PE8", "PE9";
++				function = "emac";
++			};
++
++			/omit-if-no-ref/
++			uart0_pb8_pins: uart0-pb8-pins {
++				pins = "PB8", "PB9";
++				function = "uart0";
++			};
++
++			/omit-if-no-ref/
++			uart1_pg6_pins: uart1-pg6-pins {
++				pins = "PG6", "PG7";
++				function = "uart1";
++			};
++
++			/omit-if-no-ref/
++			uart1_pg8_rts_cts_pins: uart1-pg8-rts-cts-pins {
++				pins = "PG8", "PG9";
++				function = "uart1";
++			};
++		};
++
++		ccu: clock-controller@2001000 {
++			compatible = "allwinner,sun20i-d1-ccu";
++			reg = <0x2001000 0x1000>;
++			clocks = <&osc24M>,
++				 <&rtc CLK_OSC32K>,
++				 <&rtc CLK_IOSC>;
++			clock-names = "hosc", "losc", "iosc";
++			#clock-cells = <1>;
++			#reset-cells = <1>;
++		};
++
++		lradc: keys@2009800 {
++			compatible = "allwinner,sun20i-d1-lradc",
++				     "allwinner,sun50i-r329-lradc";
++			reg = <0x2009800 0x400>;
++			interrupts = <77 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_LRADC>;
++			resets = <&ccu RST_BUS_LRADC>;
++			status = "disabled";
++		};
++
++		codec: audio-codec@2030000 {
++			compatible = "simple-mfd", "syscon";
++			reg = <0x2030000 0x1000>;
++			#address-cells = <1>;
++			#size-cells = <1>;
++
++			regulators@2030348 {
++				compatible = "allwinner,sun20i-d1-analog-ldos";
++				reg = <0x2030348 0x4>;
++				nvmem-cells = <&bg_trim>;
++				nvmem-cell-names = "bg_trim";
++
++				reg_aldo: aldo {
++				};
++
++				reg_hpldo: hpldo {
++				};
++			};
++		};
++
++		i2s0: i2s@2032000 {
++			compatible = "allwinner,sun20i-d1-i2s",
++				     "allwinner,sun50i-r329-i2s";
++			reg = <0x2032000 0x1000>;
++			interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_I2S0>,
++				 <&ccu CLK_I2S0>;
++			clock-names = "apb", "mod";
++			resets = <&ccu RST_BUS_I2S0>;
++			dmas = <&dma 3>, <&dma 3>;
++			dma-names = "rx", "tx";
++			status = "disabled";
++			#sound-dai-cells = <0>;
++		};
++
++		i2s1: i2s@2033000 {
++			compatible = "allwinner,sun20i-d1-i2s",
++				     "allwinner,sun50i-r329-i2s";
++			reg = <0x2033000 0x1000>;
++			interrupts = <43 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_I2S1>,
++				 <&ccu CLK_I2S1>;
++			clock-names = "apb", "mod";
++			resets = <&ccu RST_BUS_I2S1>;
++			dmas = <&dma 4>, <&dma 4>;
++			dma-names = "rx", "tx";
++			status = "disabled";
++			#sound-dai-cells = <0>;
++		};
++
++		i2s2: i2s@2034000 {
++			compatible = "allwinner,sun20i-d1-i2s",
++				     "allwinner,sun50i-r329-i2s";
++			reg = <0x2034000 0x1000>;
++			interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_I2S2>,
++				 <&ccu CLK_I2S2>;
++			clock-names = "apb", "mod";
++			resets = <&ccu RST_BUS_I2S2>;
++			dmas = <&dma 5>, <&dma 5>;
++			dma-names = "rx", "tx";
++			status = "disabled";
++			#sound-dai-cells = <0>;
++		};
++
++		timer: timer@2050000 {
++			compatible = "allwinner,sun20i-d1-timer",
++				     "allwinner,sun8i-a23-timer";
++			reg = <0x2050000 0xa0>;
++			interrupts = <75 IRQ_TYPE_LEVEL_HIGH>,
++				     <76 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&osc24M>;
++		};
++
++		wdt: watchdog@20500a0 {
++			compatible = "allwinner,sun20i-d1-wdt-reset",
++				     "allwinner,sun20i-d1-wdt";
++			reg = <0x20500a0 0x20>;
++			interrupts = <79 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&osc24M>, <&rtc CLK_OSC32K>;
++			clock-names = "hosc", "losc";
++			status = "reserved";
++		};
++
++		uart0: serial@2500000 {
++			compatible = "snps,dw-apb-uart";
++			reg = <0x2500000 0x400>;
++			reg-io-width = <4>;
++			reg-shift = <2>;
++			interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_UART0>;
++			resets = <&ccu RST_BUS_UART0>;
++			dmas = <&dma 14>, <&dma 14>;
++			dma-names = "rx", "tx";
++			status = "disabled";
++		};
++
++		uart1: serial@2500400 {
++			compatible = "snps,dw-apb-uart";
++			reg = <0x2500400 0x400>;
++			reg-io-width = <4>;
++			reg-shift = <2>;
++			interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_UART1>;
++			resets = <&ccu RST_BUS_UART1>;
++			dmas = <&dma 15>, <&dma 15>;
++			dma-names = "rx", "tx";
++			status = "disabled";
++		};
++
++		uart2: serial@2500800 {
++			compatible = "snps,dw-apb-uart";
++			reg = <0x2500800 0x400>;
++			reg-io-width = <4>;
++			reg-shift = <2>;
++			interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_UART2>;
++			resets = <&ccu RST_BUS_UART2>;
++			dmas = <&dma 16>, <&dma 16>;
++			dma-names = "rx", "tx";
++			status = "disabled";
++		};
++
++		uart3: serial@2500c00 {
++			compatible = "snps,dw-apb-uart";
++			reg = <0x2500c00 0x400>;
++			reg-io-width = <4>;
++			reg-shift = <2>;
++			interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_UART3>;
++			resets = <&ccu RST_BUS_UART3>;
++			dmas = <&dma 17>, <&dma 17>;
++			dma-names = "rx", "tx";
++			status = "disabled";
++		};
++
++		uart4: serial@2501000 {
++			compatible = "snps,dw-apb-uart";
++			reg = <0x2501000 0x400>;
++			reg-io-width = <4>;
++			reg-shift = <2>;
++			interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_UART4>;
++			resets = <&ccu RST_BUS_UART4>;
++			dmas = <&dma 18>, <&dma 18>;
++			dma-names = "rx", "tx";
++			status = "disabled";
++		};
++
++		uart5: serial@2501400 {
++			compatible = "snps,dw-apb-uart";
++			reg = <0x2501400 0x400>;
++			reg-io-width = <4>;
++			reg-shift = <2>;
++			interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_UART5>;
++			resets = <&ccu RST_BUS_UART5>;
++			dmas = <&dma 19>, <&dma 19>;
++			dma-names = "rx", "tx";
++			status = "disabled";
++		};
++
++		i2c0: i2c@2502000 {
++			compatible = "allwinner,sun20i-d1-i2c",
++				     "allwinner,sun8i-v536-i2c",
++				     "allwinner,sun6i-a31-i2c";
++			reg = <0x2502000 0x400>;
++			interrupts = <25 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_I2C0>;
++			resets = <&ccu RST_BUS_I2C0>;
++			dmas = <&dma 43>, <&dma 43>;
++			dma-names = "rx", "tx";
++			status = "disabled";
++			#address-cells = <1>;
++			#size-cells = <0>;
++		};
++
++		i2c1: i2c@2502400 {
++			compatible = "allwinner,sun20i-d1-i2c",
++				     "allwinner,sun8i-v536-i2c",
++				     "allwinner,sun6i-a31-i2c";
++			reg = <0x2502400 0x400>;
++			interrupts = <26 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_I2C1>;
++			resets = <&ccu RST_BUS_I2C1>;
++			dmas = <&dma 44>, <&dma 44>;
++			dma-names = "rx", "tx";
++			status = "disabled";
++			#address-cells = <1>;
++			#size-cells = <0>;
++		};
++
++		i2c2: i2c@2502800 {
++			compatible = "allwinner,sun20i-d1-i2c",
++				     "allwinner,sun8i-v536-i2c",
++				     "allwinner,sun6i-a31-i2c";
++			reg = <0x2502800 0x400>;
++			interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_I2C2>;
++			resets = <&ccu RST_BUS_I2C2>;
++			dmas = <&dma 45>, <&dma 45>;
++			dma-names = "rx", "tx";
++			status = "disabled";
++			#address-cells = <1>;
++			#size-cells = <0>;
++		};
++
++		i2c3: i2c@2502c00 {
++			compatible = "allwinner,sun20i-d1-i2c",
++				     "allwinner,sun8i-v536-i2c",
++				     "allwinner,sun6i-a31-i2c";
++			reg = <0x2502c00 0x400>;
++			interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_I2C3>;
++			resets = <&ccu RST_BUS_I2C3>;
++			dmas = <&dma 46>, <&dma 46>;
++			dma-names = "rx", "tx";
++			status = "disabled";
++			#address-cells = <1>;
++			#size-cells = <0>;
++		};
++
++		syscon: syscon@3000000 {
++			compatible = "allwinner,sun20i-d1-system-control";
++			reg = <0x3000000 0x1000>;
++			ranges;
++			#address-cells = <1>;
++			#size-cells = <1>;
++
++			regulators@3000150 {
++				compatible = "allwinner,sun20i-d1-system-ldos";
++				reg = <0x3000150 0x4>;
++
++				reg_ldoa: ldoa {
++				};
++
++				reg_ldob: ldob {
++				};
++			};
++		};
++
++		dma: dma-controller@3002000 {
++			compatible = "allwinner,sun20i-d1-dma";
++			reg = <0x3002000 0x1000>;
++			interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
++			clock-names = "bus", "mbus";
++			resets = <&ccu RST_BUS_DMA>;
++			dma-channels = <16>;
++			dma-requests = <48>;
++			#dma-cells = <1>;
++		};
++
++		sid: efuse@3006000 {
++			compatible = "allwinner,sun20i-d1-sid";
++			reg = <0x3006000 0x1000>;
++			#address-cells = <1>;
++			#size-cells = <1>;
++
++			ths_calib: ths-calib@14 {
++				reg = <0x14 0x4>;
++			};
++
++			bg_trim: bg-trim@28 {
++				reg = <0x28 0x4>;
++				bits = <16 8>;
++			};
++		};
++
++		mbus: dram-controller@3102000 {
++			compatible = "allwinner,sun20i-d1-mbus";
++			reg = <0x3102000 0x1000>,
++			      <0x3103000 0x1000>;
++			reg-names = "mbus", "dram";
++			interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_MBUS>,
++				 <&ccu CLK_DRAM>,
++				 <&ccu CLK_BUS_DRAM>;
++			clock-names = "mbus", "dram", "bus";
++			dma-ranges = <0 0x40000000 0x80000000>;
++			#address-cells = <1>;
++			#size-cells = <1>;
++			#interconnect-cells = <1>;
++		};
++
++		mmc0: mmc@4020000 {
++			compatible = "allwinner,sun20i-d1-mmc";
++			reg = <0x4020000 0x1000>;
++			interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
++			clock-names = "ahb", "mmc";
++			resets = <&ccu RST_BUS_MMC0>;
++			reset-names = "ahb";
++			cap-sd-highspeed;
++			max-frequency = <150000000>;
++			no-mmc;
++			status = "disabled";
++			#address-cells = <1>;
++			#size-cells = <0>;
++		};
++
++		mmc1: mmc@4021000 {
++			compatible = "allwinner,sun20i-d1-mmc";
++			reg = <0x4021000 0x1000>;
++			interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
++			clock-names = "ahb", "mmc";
++			resets = <&ccu RST_BUS_MMC1>;
++			reset-names = "ahb";
++			cap-sd-highspeed;
++			max-frequency = <150000000>;
++			no-mmc;
++			status = "disabled";
++			#address-cells = <1>;
++			#size-cells = <0>;
++		};
++
++		mmc2: mmc@4022000 {
++			compatible = "allwinner,sun20i-d1-emmc",
++				     "allwinner,sun50i-a100-emmc";
++			reg = <0x4022000 0x1000>;
++			interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
++			clock-names = "ahb", "mmc";
++			resets = <&ccu RST_BUS_MMC2>;
++			reset-names = "ahb";
++			cap-mmc-highspeed;
++			max-frequency = <150000000>;
++			mmc-ddr-1_8v;
++			mmc-ddr-3_3v;
++			no-sd;
++			no-sdio;
++			status = "disabled";
++			#address-cells = <1>;
++			#size-cells = <0>;
++		};
++
++		usb_otg: usb@4100000 {
++			compatible = "allwinner,sun20i-d1-musb",
++				     "allwinner,sun8i-a33-musb";
++			reg = <0x4100000 0x400>;
++			interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "mc";
++			clocks = <&ccu CLK_BUS_OTG>;
++			resets = <&ccu RST_BUS_OTG>;
++			extcon = <&usbphy 0>;
++			phys = <&usbphy 0>;
++			phy-names = "usb";
++			status = "disabled";
++		};
++
++		usbphy: phy@4100400 {
++			compatible = "allwinner,sun20i-d1-usb-phy";
++			reg = <0x4100400 0x100>,
++			      <0x4101800 0x100>,
++			      <0x4200800 0x100>;
++			reg-names = "phy_ctrl",
++				    "pmu0",
++				    "pmu1";
++			clocks = <&osc24M>,
++				 <&osc24M>;
++			clock-names = "usb0_phy",
++				      "usb1_phy";
++			resets = <&ccu RST_USB_PHY0>,
++				 <&ccu RST_USB_PHY1>;
++			reset-names = "usb0_reset",
++				      "usb1_reset";
++			status = "disabled";
++			#phy-cells = <1>;
++		};
++
++		ehci0: usb@4101000 {
++			compatible = "allwinner,sun20i-d1-ehci",
++				     "generic-ehci";
++			reg = <0x4101000 0x100>;
++			interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_OHCI0>,
++				 <&ccu CLK_BUS_EHCI0>,
++				 <&ccu CLK_USB_OHCI0>;
++			resets = <&ccu RST_BUS_OHCI0>,
++				 <&ccu RST_BUS_EHCI0>;
++			phys = <&usbphy 0>;
++			phy-names = "usb";
++			status = "disabled";
++		};
++
++		ohci0: usb@4101400 {
++			compatible = "allwinner,sun20i-d1-ohci",
++				     "generic-ohci";
++			reg = <0x4101400 0x100>;
++			interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_OHCI0>,
++				 <&ccu CLK_USB_OHCI0>;
++			resets = <&ccu RST_BUS_OHCI0>;
++			phys = <&usbphy 0>;
++			phy-names = "usb";
++			status = "disabled";
++		};
++
++		ehci1: usb@4200000 {
++			compatible = "allwinner,sun20i-d1-ehci",
++				     "generic-ehci";
++			reg = <0x4200000 0x100>;
++			interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_OHCI1>,
++				 <&ccu CLK_BUS_EHCI1>,
++				 <&ccu CLK_USB_OHCI1>;
++			resets = <&ccu RST_BUS_OHCI1>,
++				 <&ccu RST_BUS_EHCI1>;
++			phys = <&usbphy 1>;
++			phy-names = "usb";
++			status = "disabled";
++		};
++
++		ohci1: usb@4200400 {
++			compatible = "allwinner,sun20i-d1-ohci",
++				     "generic-ohci";
++			reg = <0x4200400 0x100>;
++			interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_OHCI1>,
++				 <&ccu CLK_USB_OHCI1>;
++			resets = <&ccu RST_BUS_OHCI1>;
++			phys = <&usbphy 1>;
++			phy-names = "usb";
++			status = "disabled";
++		};
++
++		emac: ethernet@4500000 {
++			compatible = "allwinner,sun20i-d1-emac",
++				     "allwinner,sun50i-a64-emac";
++			reg = <0x4500000 0x10000>;
++			interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "macirq";
++			clocks = <&ccu CLK_BUS_EMAC>;
++			clock-names = "stmmaceth";
++			resets = <&ccu RST_BUS_EMAC>;
++			reset-names = "stmmaceth";
++			syscon = <&syscon>;
++			status = "disabled";
++
++			mdio: mdio {
++				compatible = "snps,dwmac-mdio";
++				#address-cells = <1>;
++				#size-cells = <0>;
++			};
++		};
++
++		display_clocks: clock-controller@5000000 {
++			compatible = "allwinner,sun20i-d1-de2-clk",
++				     "allwinner,sun50i-h5-de2-clk";
++			reg = <0x5000000 0x10000>;
++			clocks = <&ccu CLK_BUS_DE>, <&ccu CLK_DE>;
++			clock-names = "bus", "mod";
++			resets = <&ccu RST_BUS_DE>;
++			#clock-cells = <1>;
++			#reset-cells = <1>;
++		};
++
++		mixer0: mixer@5100000 {
++			compatible = "allwinner,sun20i-d1-de2-mixer-0";
++			reg = <0x5100000 0x100000>;
++			clocks = <&display_clocks CLK_BUS_MIXER0>,
++				 <&display_clocks CLK_MIXER0>;
++			clock-names = "bus", "mod";
++			resets = <&display_clocks RST_MIXER0>;
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				mixer0_out: port@1 {
++					reg = <1>;
++
++					mixer0_out_tcon_top_mixer0: endpoint {
++						remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
++					};
++				};
++			};
++		};
++
++		mixer1: mixer@5200000 {
++			compatible = "allwinner,sun20i-d1-de2-mixer-1";
++			reg = <0x5200000 0x100000>;
++			clocks = <&display_clocks CLK_BUS_MIXER1>,
++				 <&display_clocks CLK_MIXER1>;
++			clock-names = "bus", "mod";
++			resets = <&display_clocks RST_MIXER1>;
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				mixer1_out: port@1 {
++					reg = <1>;
++
++					mixer1_out_tcon_top_mixer1: endpoint {
++						remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
++					};
++				};
++			};
++		};
++
++		tcon_top: tcon-top@5460000 {
++			compatible = "allwinner,sun20i-d1-tcon-top";
++			reg = <0x5460000 0x1000>;
++			clocks = <&ccu CLK_BUS_DPSS_TOP>,
++				 <&ccu CLK_TCON_TV>,
++				 <&ccu CLK_TVE>,
++				 <&ccu CLK_TCON_LCD0>;
++			clock-names = "bus", "tcon-tv0", "tve0", "dsi";
++			clock-output-names = "tcon-top-tv0", "tcon-top-dsi";
++			resets = <&ccu RST_BUS_DPSS_TOP>;
++			#clock-cells = <1>;
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				tcon_top_mixer0_in: port@0 {
++					reg = <0>;
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					tcon_top_mixer0_in_mixer0: endpoint@0 {
++						reg = <0>;
++						remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
++					};
++				};
++
++				tcon_top_mixer0_out: port@1 {
++					reg = <1>;
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
++						reg = <0>;
++						remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer0>;
++					};
++
++					tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
++						reg = <2>;
++						remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
++					};
++				};
++
++				tcon_top_mixer1_in: port@2 {
++					reg = <2>;
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					tcon_top_mixer1_in_mixer1: endpoint@1 {
++						reg = <1>;
++						remote-endpoint = <&mixer1_out_tcon_top_mixer1>;
++					};
++				};
++
++				tcon_top_mixer1_out: port@3 {
++					reg = <3>;
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
++						reg = <0>;
++						remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer1>;
++					};
++
++					tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
++						reg = <2>;
++						remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
++					};
++				};
++
++				tcon_top_hdmi_in: port@4 {
++					reg = <4>;
++
++					tcon_top_hdmi_in_tcon_tv0: endpoint {
++						remote-endpoint = <&tcon_tv0_out_tcon_top_hdmi>;
++					};
++				};
++
++				tcon_top_hdmi_out: port@5 {
++					reg = <5>;
++				};
++			};
++		};
++
++		tcon_lcd0: lcd-controller@5461000 {
++			compatible = "allwinner,sun20i-d1-tcon-lcd";
++			reg = <0x5461000 0x1000>;
++			interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_TCON_LCD0>,
++				 <&ccu CLK_TCON_LCD0>;
++			clock-names = "ahb", "tcon-ch0";
++			clock-output-names = "tcon-pixel-clock";
++			resets = <&ccu RST_BUS_TCON_LCD0>,
++				 <&ccu RST_BUS_LVDS0>;
++			reset-names = "lcd", "lvds";
++			#clock-cells = <0>;
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				tcon_lcd0_in: port@0 {
++					reg = <0>;
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					tcon_lcd0_in_tcon_top_mixer0: endpoint@0 {
++						reg = <0>;
++						remote-endpoint = <&tcon_top_mixer0_out_tcon_lcd0>;
++					};
++
++					tcon_lcd0_in_tcon_top_mixer1: endpoint@1 {
++						reg = <1>;
++						remote-endpoint = <&tcon_top_mixer1_out_tcon_lcd0>;
++					};
++				};
++
++				tcon_lcd0_out: port@1 {
++					reg = <1>;
++				};
++			};
++		};
++
++		tcon_tv0: lcd-controller@5470000 {
++			compatible = "allwinner,sun20i-d1-tcon-tv";
++			reg = <0x5470000 0x1000>;
++			interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_TCON_TV>,
++				 <&tcon_top CLK_TCON_TOP_TV0>;
++			clock-names = "ahb", "tcon-ch1";
++			resets = <&ccu RST_BUS_TCON_TV>;
++			reset-names = "lcd";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				tcon_tv0_in: port@0 {
++					reg = <0>;
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
++						reg = <0>;
++						remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
++					};
++
++					tcon_tv0_in_tcon_top_mixer1: endpoint@1 {
++						reg = <1>;
++						remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
++					};
++				};
++
++				tcon_tv0_out: port@1 {
++					reg = <1>;
++
++					tcon_tv0_out_tcon_top_hdmi: endpoint {
++						remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
++					};
++				};
++			};
++		};
++
++		riscv_wdt: watchdog@6011000 {
++			compatible = "allwinner,sun20i-d1-wdt";
++			reg = <0x6011000 0x20>;
++			interrupts = <147 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&osc24M>, <&rtc CLK_OSC32K>;
++			clock-names = "hosc", "losc";
++		};
++
++		r_ccu: clock-controller@7010000 {
++			compatible = "allwinner,sun20i-d1-r-ccu";
++			reg = <0x7010000 0x400>;
++			clocks = <&osc24M>,
++				 <&rtc CLK_OSC32K>,
++				 <&rtc CLK_IOSC>,
++				 <&ccu CLK_PLL_PERIPH0_DIV3>;
++			clock-names = "hosc", "losc", "iosc", "pll-periph";
++			#clock-cells = <1>;
++			#reset-cells = <1>;
++		};
++
++		rtc: rtc@7090000 {
++			compatible = "allwinner,sun20i-d1-rtc",
++				     "allwinner,sun50i-r329-rtc";
++			reg = <0x7090000 0x400>;
++			interrupts = <160 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&r_ccu CLK_BUS_R_RTC>,
++				 <&osc24M>,
++				 <&r_ccu CLK_R_AHB>;
++			clock-names = "bus", "hosc", "ahb";
++			#clock-cells = <1>;
++		};
++
++		plic: interrupt-controller@10000000 {
++			compatible = "allwinner,sun20i-d1-plic",
++				     "thead,c900-plic";
++			reg = <0x10000000 0x4000000>;
++			interrupts-extended = <&cpu0_intc 11>,
++					      <&cpu0_intc 9>;
++			interrupt-controller;
++			riscv,ndev = <176>;
++			#address-cells = <0>;
++			#interrupt-cells = <2>;
++		};
++	};
++};
diff --git a/target/linux/d1/patches-6.1/0029-riscv-dts-allwinner-Add-Allwinner-D1-Nezha-devicetre.patch b/target/linux/d1/patches-6.1/0029-riscv-dts-allwinner-Add-Allwinner-D1-Nezha-devicetre.patch
new file mode 100644
index 00000000000000..aadc3138d462e9
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0029-riscv-dts-allwinner-Add-Allwinner-D1-Nezha-devicetre.patch
@@ -0,0 +1,263 @@
+From 5da27190c54b7a51062786eb01246f6f4cf2ba98 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Tue, 28 Jun 2022 23:31:16 -0500
+Subject: [PATCH 029/117] riscv: dts: allwinner: Add Allwinner D1 Nezha
+ devicetree
+
+"D1 Nezha" is Allwinner's first-party development board for the D1 SoC.
+It was shipped with 512M, 1G, or 2G of DDR3. It supports onboard audio,
+HDMI, gigabit Ethernet, WiFi and Bluetooth, USB 2.0 host and OTG ports,
+plus low-speed I/O from the SoC and a GPIO expander chip.
+
+Most other D1 boards copied the Nezha's power tree, with the 1.8V rail
+powered by the SoCs internal LDOA, analog domains powered by ALDO, and
+the rest of the board powered by always-on fixed regulators. Some (but
+not all) boards also copied the PWM CPU regulator. To avoid duplication,
+factor out the out the regulator references that are common across all
+known boards.
+
+Reviewed-by: Heiko Stuebner <heiko@sntech.de>
+Tested-by: Conor Dooley <conor.dooley@microchip.com>
+Tested-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/riscv/boot/dts/allwinner/Makefile        |   1 +
+ .../sun20i-d1-common-regulators.dtsi          |  51 ++++++
+ .../boot/dts/allwinner/sun20i-d1-nezha.dts    | 171 ++++++++++++++++++
+ 3 files changed, 223 insertions(+)
+ create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi
+ create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
+
+--- a/arch/riscv/boot/dts/allwinner/Makefile
++++ b/arch/riscv/boot/dts/allwinner/Makefile
+@@ -1 +1,2 @@
+ # SPDX-License-Identifier: GPL-2.0
++dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-nezha.dtb
+--- /dev/null
++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi
+@@ -0,0 +1,51 @@
++// SPDX-License-Identifier: (GPL-2.0+ or MIT)
++// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
++
++/ {
++	reg_vcc: vcc {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++	};
++
++	reg_vcc_3v3: vcc-3v3 {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc-3v3";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		vin-supply = <&reg_vcc>;
++	};
++};
++
++&lradc {
++	vref-supply = <&reg_aldo>;
++};
++
++&pio {
++	vcc-pb-supply = <&reg_vcc_3v3>;
++	vcc-pc-supply = <&reg_vcc_3v3>;
++	vcc-pd-supply = <&reg_vcc_3v3>;
++	vcc-pe-supply = <&reg_vcc_3v3>;
++	vcc-pf-supply = <&reg_vcc_3v3>;
++	vcc-pg-supply = <&reg_vcc_3v3>;
++};
++
++&reg_aldo {
++	regulator-min-microvolt = <1800000>;
++	regulator-max-microvolt = <1800000>;
++	vdd33-supply = <&reg_vcc_3v3>;
++};
++
++&reg_hpldo {
++	regulator-min-microvolt = <1800000>;
++	regulator-max-microvolt = <1800000>;
++	hpldoin-supply = <&reg_vcc_3v3>;
++};
++
++&reg_ldoa {
++	regulator-always-on;
++	regulator-min-microvolt = <1800000>;
++	regulator-max-microvolt = <1800000>;
++	ldo-in-supply = <&reg_vcc_3v3>;
++};
+--- /dev/null
++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
+@@ -0,0 +1,171 @@
++// SPDX-License-Identifier: (GPL-2.0+ or MIT)
++// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
++
++/dts-v1/;
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
++
++#include "sun20i-d1.dtsi"
++#include "sun20i-d1-common-regulators.dtsi"
++
++/ {
++	model = "Allwinner D1 Nezha";
++	compatible = "allwinner,d1-nezha", "allwinner,sun20i-d1";
++
++	aliases {
++		ethernet0 = &emac;
++		ethernet1 = &xr829;
++		mmc0 = &mmc0;
++		serial0 = &uart0;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	reg_usbvbus: usbvbus {
++		compatible = "regulator-fixed";
++		regulator-name = "usbvbus";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		gpio = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */
++		enable-active-high;
++		vin-supply = <&reg_vcc>;
++	};
++
++	/*
++	 * This regulator is PWM-controlled, but the PWM controller is not
++	 * yet supported, so fix the regulator to its default voltage.
++	 */
++	reg_vdd_cpu: vdd-cpu {
++		compatible = "regulator-fixed";
++		regulator-name = "vdd-cpu";
++		regulator-min-microvolt = <1100000>;
++		regulator-max-microvolt = <1100000>;
++		vin-supply = <&reg_vcc>;
++	};
++
++	wifi_pwrseq: wifi-pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
++	};
++};
++
++&cpu0 {
++	cpu-supply = <&reg_vdd_cpu>;
++};
++
++&ehci0 {
++	status = "okay";
++};
++
++&ehci1 {
++	status = "okay";
++};
++
++&emac {
++	pinctrl-0 = <&rgmii_pe_pins>;
++	pinctrl-names = "default";
++	phy-handle = <&ext_rgmii_phy>;
++	phy-mode = "rgmii-id";
++	phy-supply = <&reg_vcc_3v3>;
++	status = "okay";
++};
++
++&i2c2 {
++	pinctrl-0 = <&i2c2_pb0_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++
++	pcf8574a: gpio@38 {
++		compatible = "nxp,pcf8574a";
++		reg = <0x38>;
++		interrupt-parent = <&pio>;
++		interrupts = <1 2 IRQ_TYPE_LEVEL_LOW>; /* PB2 */
++		interrupt-controller;
++		gpio-controller;
++		#gpio-cells = <2>;
++		#interrupt-cells = <2>;
++	};
++};
++
++&lradc {
++	status = "okay";
++
++	button-160 {
++		label = "OK";
++		linux,code = <KEY_OK>;
++		channel = <0>;
++		voltage = <160000>;
++	};
++};
++
++&mdio {
++	ext_rgmii_phy: ethernet-phy@1 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <1>;
++	};
++};
++
++&mmc0 {
++	bus-width = <4>;
++	cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
++	disable-wp;
++	vmmc-supply = <&reg_vcc_3v3>;
++	vqmmc-supply = <&reg_vcc_3v3>;
++	pinctrl-0 = <&mmc0_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
++&mmc1 {
++	bus-width = <4>;
++	mmc-pwrseq = <&wifi_pwrseq>;
++	non-removable;
++	vmmc-supply = <&reg_vcc_3v3>;
++	vqmmc-supply = <&reg_vcc_3v3>;
++	pinctrl-0 = <&mmc1_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++
++	xr829: wifi@1 {
++		reg = <1>;
++	};
++};
++
++&ohci0 {
++	status = "okay";
++};
++
++&ohci1 {
++	status = "okay";
++};
++
++&uart0 {
++	pinctrl-0 = <&uart0_pb8_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
++&uart1 {
++	uart-has-rtscts;
++	pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++
++	/* XR829 bluetooth is connected here */
++};
++
++&usb_otg {
++	dr_mode = "otg";
++	status = "okay";
++};
++
++&usbphy {
++	usb0_id_det-gpios = <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21 */
++	usb0_vbus_det-gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */
++	usb0_vbus-supply = <&reg_usbvbus>;
++	usb1_vbus-supply = <&reg_vcc>;
++	status = "okay";
++};
diff --git a/target/linux/d1/patches-6.1/0030-riscv-dts-allwinner-Add-Sipeed-Lichee-RV-devicetrees.patch b/target/linux/d1/patches-6.1/0030-riscv-dts-allwinner-Add-Sipeed-Lichee-RV-devicetrees.patch
new file mode 100644
index 00000000000000..73c486aed2e3fd
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0030-riscv-dts-allwinner-Add-Sipeed-Lichee-RV-devicetrees.patch
@@ -0,0 +1,344 @@
+From 3bf76e93011425ed64a69c462b9959ed2a8ccf46 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Wed, 29 Jun 2022 00:13:50 -0500
+Subject: [PATCH 030/117] riscv: dts: allwinner: Add Sipeed Lichee RV
+ devicetrees
+
+Sipeed manufactures a "Lichee RV" system-on-module, which provides a
+minimal working system on its own, as well as a few carrier boards. The
+"Dock" board provides audio, USB, and WiFi. The "86 Panel" additionally
+provides 100M Ethernet and a built-in display panel.
+
+The 86 Panel repurposes the USB ID and VBUS detection GPIOs for its RGB
+panel interface, since the USB OTG port is inaccessible inside the case.
+
+Co-developed-by: Jisheng Zhang <jszhang@kernel.org>
+Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/riscv/boot/dts/allwinner/Makefile        |  4 +
+ .../sun20i-d1-lichee-rv-86-panel-480p.dts     | 29 ++++++
+ .../sun20i-d1-lichee-rv-86-panel-720p.dts     | 10 ++
+ .../sun20i-d1-lichee-rv-86-panel.dtsi         | 92 +++++++++++++++++++
+ .../allwinner/sun20i-d1-lichee-rv-dock.dts    | 74 +++++++++++++++
+ .../dts/allwinner/sun20i-d1-lichee-rv.dts     | 84 +++++++++++++++++
+ 6 files changed, 293 insertions(+)
+ create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-480p.dts
+ create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-720p.dts
+ create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel.dtsi
+ create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts
+ create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv.dts
+
+--- a/arch/riscv/boot/dts/allwinner/Makefile
++++ b/arch/riscv/boot/dts/allwinner/Makefile
+@@ -1,2 +1,6 @@
+ # SPDX-License-Identifier: GPL-2.0
++dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-480p.dtb
++dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-720p.dtb
++dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-dock.dtb
++dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-nezha.dtb
+--- /dev/null
++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-480p.dts
+@@ -0,0 +1,29 @@
++// SPDX-License-Identifier: (GPL-2.0+ or MIT)
++// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
++
++#include "sun20i-d1-lichee-rv-86-panel.dtsi"
++
++/ {
++	model = "Sipeed Lichee RV 86 Panel (480p)";
++	compatible = "sipeed,lichee-rv-86-panel-480p", "sipeed,lichee-rv",
++		     "allwinner,sun20i-d1";
++};
++
++&i2c2 {
++	pinctrl-0 = <&i2c2_pb0_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++
++	touchscreen@48 {
++		compatible = "focaltech,ft6236";
++		reg = <0x48>;
++		interrupt-parent = <&pio>;
++		interrupts = <6 14 IRQ_TYPE_LEVEL_LOW>; /* PG14 */
++		iovcc-supply = <&reg_vcc_3v3>;
++		reset-gpios = <&pio 6 15 GPIO_ACTIVE_LOW>; /* PG15 */
++		touchscreen-size-x = <480>;
++		touchscreen-size-y = <480>;
++		vcc-supply = <&reg_vcc_3v3>;
++		wakeup-source;
++	};
++};
+--- /dev/null
++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-720p.dts
+@@ -0,0 +1,10 @@
++// SPDX-License-Identifier: (GPL-2.0+ or MIT)
++// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
++
++#include "sun20i-d1-lichee-rv-86-panel.dtsi"
++
++/ {
++	model = "Sipeed Lichee RV 86 Panel (720p)";
++	compatible = "sipeed,lichee-rv-86-panel-720p", "sipeed,lichee-rv",
++		     "allwinner,sun20i-d1";
++};
+--- /dev/null
++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel.dtsi
+@@ -0,0 +1,92 @@
++// SPDX-License-Identifier: (GPL-2.0+ or MIT)
++// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
++
++#include "sun20i-d1-lichee-rv.dts"
++
++/ {
++	aliases {
++		ethernet0 = &emac;
++		ethernet1 = &xr829;
++	};
++
++	/* PC1 is repurposed as BT_WAKE_AP */
++	/delete-node/ leds;
++
++	wifi_pwrseq: wifi-pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		clocks = <&ccu CLK_FANOUT1>;
++		clock-names = "ext_clock";
++		reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
++		assigned-clocks = <&ccu CLK_FANOUT1>;
++		assigned-clock-rates = <32768>;
++		pinctrl-0 = <&clk_pg11_pin>;
++		pinctrl-names = "default";
++	};
++};
++
++&ehci1 {
++	status = "okay";
++};
++
++&emac {
++	pinctrl-0 = <&rmii_pe_pins>;
++	pinctrl-names = "default";
++	phy-handle = <&ext_rmii_phy>;
++	phy-mode = "rmii";
++	phy-supply = <&reg_vcc_3v3>;
++	status = "okay";
++};
++
++&mdio {
++	ext_rmii_phy: ethernet-phy@1 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <1>;
++		reset-gpios = <&pio 4 16 GPIO_ACTIVE_LOW>; /* PE16 */
++	};
++};
++
++&mmc1 {
++	bus-width = <4>;
++	mmc-pwrseq = <&wifi_pwrseq>;
++	non-removable;
++	vmmc-supply = <&reg_vcc_3v3>;
++	vqmmc-supply = <&reg_vcc_3v3>;
++	pinctrl-0 = <&mmc1_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++
++	xr829: wifi@1 {
++		reg = <1>;
++	};
++};
++
++&ohci1 {
++	status = "okay";
++};
++
++&pio {
++	clk_pg11_pin: clk-pg11-pin {
++		pins = "PG11";
++		function = "clk";
++	};
++};
++
++&uart1 {
++	uart-has-rtscts;
++	pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++
++	/* XR829 bluetooth is connected here */
++};
++
++&usb_otg {
++	status = "disabled";
++};
++
++&usbphy {
++	/* PD20 and PD21 are repurposed for the LCD panel */
++	/delete-property/ usb0_id_det-gpios;
++	/delete-property/ usb0_vbus_det-gpios;
++	usb1_vbus-supply = <&reg_vcc>;
++};
+--- /dev/null
++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts
+@@ -0,0 +1,74 @@
++// SPDX-License-Identifier: (GPL-2.0+ or MIT)
++// Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org>
++// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
++
++#include <dt-bindings/input/input.h>
++
++#include "sun20i-d1-lichee-rv.dts"
++
++/ {
++	model = "Sipeed Lichee RV Dock";
++	compatible = "sipeed,lichee-rv-dock", "sipeed,lichee-rv",
++		     "allwinner,sun20i-d1";
++
++	aliases {
++		ethernet1 = &rtl8723ds;
++	};
++
++	wifi_pwrseq: wifi-pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
++	};
++};
++
++&ehci1 {
++	status = "okay";
++};
++
++&lradc {
++	status = "okay";
++
++	button-220 {
++		label = "OK";
++		linux,code = <KEY_OK>;
++		channel = <0>;
++		voltage = <220000>;
++	};
++};
++
++&mmc1 {
++	bus-width = <4>;
++	mmc-pwrseq = <&wifi_pwrseq>;
++	non-removable;
++	vmmc-supply = <&reg_vcc_3v3>;
++	vqmmc-supply = <&reg_vcc_3v3>;
++	pinctrl-0 = <&mmc1_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++
++	rtl8723ds: wifi@1 {
++		reg = <1>;
++	};
++};
++
++&ohci1 {
++	status = "okay";
++};
++
++&uart1 {
++	uart-has-rtscts;
++	pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++
++	bluetooth {
++		compatible = "realtek,rtl8723ds-bt";
++		device-wake-gpios = <&pio 6 15 GPIO_ACTIVE_HIGH>; /* PG16 */
++		enable-gpios = <&pio 6 18 GPIO_ACTIVE_HIGH>; /* PG18 */
++		host-wake-gpios = <&pio 6 17 GPIO_ACTIVE_HIGH>; /* PG17 */
++	};
++};
++
++&usbphy {
++	usb1_vbus-supply = <&reg_vcc>;
++};
+--- /dev/null
++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv.dts
+@@ -0,0 +1,84 @@
++// SPDX-License-Identifier: (GPL-2.0+ or MIT)
++// Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org>
++// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
++
++/dts-v1/;
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/leds/common.h>
++
++#include "sun20i-d1.dtsi"
++#include "sun20i-d1-common-regulators.dtsi"
++
++/ {
++	model = "Sipeed Lichee RV";
++	compatible = "sipeed,lichee-rv", "allwinner,sun20i-d1";
++
++	aliases {
++		mmc0 = &mmc0;
++		serial0 = &uart0;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		led-0 {
++			color = <LED_COLOR_ID_GREEN>;
++			function = LED_FUNCTION_STATUS;
++			gpios = <&pio 2 1 GPIO_ACTIVE_HIGH>; /* PC1 */
++		};
++	};
++
++	reg_vdd_cpu: vdd-cpu {
++		compatible = "regulator-fixed";
++		regulator-name = "vdd-cpu";
++		regulator-min-microvolt = <900000>;
++		regulator-max-microvolt = <900000>;
++		vin-supply = <&reg_vcc>;
++	};
++};
++
++&cpu0 {
++	cpu-supply = <&reg_vdd_cpu>;
++};
++
++&ehci0 {
++	status = "okay";
++};
++
++&mmc0 {
++	broken-cd;
++	bus-width = <4>;
++	disable-wp;
++	vmmc-supply = <&reg_vcc_3v3>;
++	vqmmc-supply = <&reg_vcc_3v3>;
++	pinctrl-0 = <&mmc0_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
++&ohci0 {
++	status = "okay";
++};
++
++&uart0 {
++	pinctrl-0 = <&uart0_pb8_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
++&usb_otg {
++	dr_mode = "otg";
++	status = "okay";
++};
++
++&usbphy {
++	usb0_id_det-gpios = <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21 */
++	usb0_vbus_det-gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */
++	usb0_vbus-supply = <&reg_vcc>;
++	status = "okay";
++};
diff --git a/target/linux/d1/patches-6.1/0031-riscv-dts-allwinner-Add-MangoPi-MQ-Pro-devicetree.patch b/target/linux/d1/patches-6.1/0031-riscv-dts-allwinner-Add-MangoPi-MQ-Pro-devicetree.patch
new file mode 100644
index 00000000000000..54073136bf9852
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0031-riscv-dts-allwinner-Add-MangoPi-MQ-Pro-devicetree.patch
@@ -0,0 +1,159 @@
+From 3cf55c25453517960d72b56d1ba8f12840b1990e Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 9 Jul 2022 17:43:17 -0500
+Subject: [PATCH 031/117] riscv: dts: allwinner: Add MangoPi MQ Pro devicetree
+
+The MangoPi MQ Pro is a tiny SBC with a layout compatible to the
+Raspberry Pi Zero. It includes the Allwinner D1 SoC, 512M or 1G of DDR3,
+and an RTL8723DS-based WiFi/Bluetooth module.
+
+The board also exposes GPIO Port E via a connector on the end of the
+board, which can support either a camera or an RMII Ethernet PHY. The
+additional regulators supply that connector.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/riscv/boot/dts/allwinner/Makefile        |   1 +
+ .../allwinner/sun20i-d1-mangopi-mq-pro.dts    | 128 ++++++++++++++++++
+ 2 files changed, 129 insertions(+)
+ create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-mangopi-mq-pro.dts
+
+--- a/arch/riscv/boot/dts/allwinner/Makefile
++++ b/arch/riscv/boot/dts/allwinner/Makefile
+@@ -3,4 +3,5 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-li
+ dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-720p.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-dock.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv.dtb
++dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-mangopi-mq-pro.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-nezha.dtb
+--- /dev/null
++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-mangopi-mq-pro.dts
+@@ -0,0 +1,128 @@
++// SPDX-License-Identifier: (GPL-2.0+ or MIT)
++// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
++
++/dts-v1/;
++
++#include <dt-bindings/gpio/gpio.h>
++
++#include "sun20i-d1.dtsi"
++#include "sun20i-d1-common-regulators.dtsi"
++
++/ {
++	model = "MangoPi MQ Pro";
++	compatible = "widora,mangopi-mq-pro", "allwinner,sun20i-d1";
++
++	aliases {
++		ethernet0 = &rtl8723ds;
++		mmc0 = &mmc0;
++		serial0 = &uart0;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	reg_avdd2v8: avdd2v8 {
++		compatible = "regulator-fixed";
++		regulator-name = "avdd2v8";
++		regulator-min-microvolt = <2800000>;
++		regulator-max-microvolt = <2800000>;
++		vin-supply = <&reg_vcc_3v3>;
++	};
++
++	reg_dvdd: dvdd {
++		compatible = "regulator-fixed";
++		regulator-name = "dvdd";
++		regulator-min-microvolt = <1200000>;
++		regulator-max-microvolt = <1200000>;
++		vin-supply = <&reg_vcc_3v3>;
++	};
++
++	reg_vdd_cpu: vdd-cpu {
++		compatible = "regulator-fixed";
++		regulator-name = "vdd-cpu";
++		regulator-min-microvolt = <1100000>;
++		regulator-max-microvolt = <1100000>;
++		vin-supply = <&reg_vcc>;
++	};
++
++	wifi_pwrseq: wifi-pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		reset-gpios = <&pio 6 17 GPIO_ACTIVE_LOW>; /* PG17 */
++	};
++};
++
++&cpu0 {
++	cpu-supply = <&reg_vdd_cpu>;
++};
++
++&ehci1 {
++	status = "okay";
++};
++
++&mmc0 {
++	bus-width = <4>;
++	cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
++	disable-wp;
++	vmmc-supply = <&reg_vcc_3v3>;
++	vqmmc-supply = <&reg_vcc_3v3>;
++	pinctrl-0 = <&mmc0_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
++&mmc1 {
++	bus-width = <4>;
++	mmc-pwrseq = <&wifi_pwrseq>;
++	non-removable;
++	vmmc-supply = <&reg_vcc_3v3>;
++	vqmmc-supply = <&reg_vcc_3v3>;
++	pinctrl-0 = <&mmc1_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++
++	rtl8723ds: wifi@1 {
++		reg = <1>;
++		interrupt-parent = <&pio>;
++		interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 */
++		interrupt-names = "host-wake";
++	};
++};
++
++&ohci1 {
++	status = "okay";
++};
++
++&pio {
++	vcc-pe-supply = <&reg_avdd2v8>;
++};
++
++&uart0 {
++	pinctrl-0 = <&uart0_pb8_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
++&uart1 {
++	uart-has-rtscts;
++	pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++
++	bluetooth {
++		compatible = "realtek,rtl8723ds-bt";
++		device-wake-gpios = <&pio 6 18 GPIO_ACTIVE_HIGH>; /* PG18 */
++		enable-gpios = <&pio 6 15 GPIO_ACTIVE_HIGH>; /* PG15 */
++		host-wake-gpios = <&pio 6 14 GPIO_ACTIVE_HIGH>; /* PG14 */
++	};
++};
++
++&usb_otg {
++	dr_mode = "peripheral";
++	status = "okay";
++};
++
++&usbphy {
++	usb0_vbus-supply = <&reg_vcc>;
++	status = "okay";
++};
diff --git a/target/linux/d1/patches-6.1/0032-riscv-dts-allwinner-Add-Dongshan-Nezha-STU-devicetre.patch b/target/linux/d1/patches-6.1/0032-riscv-dts-allwinner-Add-Dongshan-Nezha-STU-devicetre.patch
new file mode 100644
index 00000000000000..fe64eabd4e9a45
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0032-riscv-dts-allwinner-Add-Dongshan-Nezha-STU-devicetre.patch
@@ -0,0 +1,146 @@
+From 1f26c90ac9cbb60ff315c552368a3bca16562e51 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 10 Jul 2022 11:24:42 -0500
+Subject: [PATCH 032/117] riscv: dts: allwinner: Add Dongshan Nezha STU
+ devicetree
+
+The 100ask Dongshan Nezha STU is a system-on-module that can be used
+standalone or with a carrier board. The SoM provides gigabit Ethernet,
+HDMI, a USB peripheral port, and WiFi/Bluetooth via an RTL8723DS chip.
+
+The "DIY" carrier board exposes almost every pin from the D1 SoC to 0.1"
+headers, but contains no digital circuitry, so it does not have its own
+devicetree.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/riscv/boot/dts/allwinner/Makefile        |   1 +
+ .../sun20i-d1-dongshan-nezha-stu.dts          | 114 ++++++++++++++++++
+ 2 files changed, 115 insertions(+)
+ create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dts
+
+--- a/arch/riscv/boot/dts/allwinner/Makefile
++++ b/arch/riscv/boot/dts/allwinner/Makefile
+@@ -1,4 +1,5 @@
+ # SPDX-License-Identifier: GPL-2.0
++dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-dongshan-nezha-stu.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-480p.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-720p.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-dock.dtb
+--- /dev/null
++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dts
+@@ -0,0 +1,114 @@
++// SPDX-License-Identifier: (GPL-2.0+ or MIT)
++// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
++
++/dts-v1/;
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/leds/common.h>
++
++#include "sun20i-d1.dtsi"
++#include "sun20i-d1-common-regulators.dtsi"
++
++/ {
++	model = "Dongshan Nezha STU";
++	compatible = "100ask,dongshan-nezha-stu", "allwinner,sun20i-d1";
++
++	aliases {
++		ethernet0 = &emac;
++		mmc0 = &mmc0;
++		serial0 = &uart0;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		led-0 {
++			color = <LED_COLOR_ID_GREEN>;
++			function = LED_FUNCTION_STATUS;
++			gpios = <&pio 2 1 GPIO_ACTIVE_HIGH>; /* PC1 */
++		};
++	};
++
++	reg_usbvbus: usbvbus {
++		compatible = "regulator-fixed";
++		regulator-name = "usbvbus";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		gpio = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */
++		enable-active-high;
++		vin-supply = <&reg_vcc>;
++	};
++
++	/*
++	 * This regulator is PWM-controlled, but the PWM controller is not
++	 * yet supported, so fix the regulator to its default voltage.
++	 */
++	reg_vdd_cpu: vdd-cpu {
++		compatible = "regulator-fixed";
++		regulator-name = "vdd-cpu";
++		regulator-min-microvolt = <1100000>;
++		regulator-max-microvolt = <1100000>;
++		vin-supply = <&reg_vcc>;
++	};
++};
++
++&cpu0 {
++	cpu-supply = <&reg_vdd_cpu>;
++};
++
++&ehci0 {
++	status = "okay";
++};
++
++&emac {
++	pinctrl-0 = <&rgmii_pe_pins>;
++	pinctrl-names = "default";
++	phy-handle = <&ext_rgmii_phy>;
++	phy-mode = "rgmii-id";
++	phy-supply = <&reg_vcc_3v3>;
++	status = "okay";
++};
++
++&mdio {
++	ext_rgmii_phy: ethernet-phy@1 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <1>;
++	};
++};
++
++&mmc0 {
++	broken-cd;
++	bus-width = <4>;
++	disable-wp;
++	vmmc-supply = <&reg_vcc_3v3>;
++	vqmmc-supply = <&reg_vcc_3v3>;
++	pinctrl-0 = <&mmc0_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
++&ohci0 {
++	status = "okay";
++};
++
++&uart0 {
++	pinctrl-0 = <&uart0_pb8_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
++&usb_otg {
++	dr_mode = "otg";
++	status = "okay";
++};
++
++&usbphy {
++	usb0_id_det-gpios = <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21 */
++	usb0_vbus_det-gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */
++	usb0_vbus-supply = <&reg_usbvbus>;
++	status = "okay";
++};
diff --git a/target/linux/d1/patches-6.1/0033-riscv-dts-allwinner-Add-ClockworkPi-and-DevTerm-devi.patch b/target/linux/d1/patches-6.1/0033-riscv-dts-allwinner-Add-ClockworkPi-and-DevTerm-devi.patch
new file mode 100644
index 00000000000000..f9fcae026f9040
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0033-riscv-dts-allwinner-Add-ClockworkPi-and-DevTerm-devi.patch
@@ -0,0 +1,322 @@
+From 11f692c6b009f36b9a91d5ceb5998ae15e57f18c Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 10 Jul 2022 23:43:49 -0500
+Subject: [PATCH 033/117] riscv: dts: allwinner: Add ClockworkPi and DevTerm
+ devicetrees
+
+Clockwork Tech manufactures several SoMs for their RasPi CM3-compatible
+"ClockworkPi" mainboard. Their R-01 SoM features the Allwinner D1 SoC.
+The R-01 contains only the CPU, DRAM, and always-on voltage regulation;
+it does not merit a separate devicetree.
+
+The ClockworkPi mainboard features analog audio, a MIPI-DSI panel, USB
+host and peripheral ports, an Ampak AP6256 WiFi/Bluetooth module, and an
+X-Powers AXP228 PMIC for managing a Li-ion battery.
+
+The DevTerm is a complete system which extends the ClockworkPi mainboard
+with a pair of expansion boards. These expansion boards provide a fan, a
+keyboard, speakers, and a thermal printer.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/riscv/boot/dts/allwinner/Makefile        |   2 +
+ .../allwinner/sun20i-d1-clockworkpi-v3.14.dts | 242 ++++++++++++++++++
+ .../dts/allwinner/sun20i-d1-devterm-v3.14.dts |  37 +++
+ 3 files changed, 281 insertions(+)
+ create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts
+ create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-devterm-v3.14.dts
+
+--- a/arch/riscv/boot/dts/allwinner/Makefile
++++ b/arch/riscv/boot/dts/allwinner/Makefile
+@@ -1,4 +1,6 @@
+ # SPDX-License-Identifier: GPL-2.0
++dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-clockworkpi-v3.14.dtb
++dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-devterm-v3.14.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-dongshan-nezha-stu.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-480p.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-720p.dtb
+--- /dev/null
++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts
+@@ -0,0 +1,242 @@
++// SPDX-License-Identifier: (GPL-2.0+ or MIT)
++// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
++
++/dts-v1/;
++
++#include <dt-bindings/gpio/gpio.h>
++
++#include "sun20i-d1.dtsi"
++#include "sun20i-d1-common-regulators.dtsi"
++
++/ {
++	model = "ClockworkPi v3.14 (R-01)";
++	compatible = "clockwork,r-01-clockworkpi-v3.14", "allwinner,sun20i-d1";
++
++	aliases {
++		ethernet0 = &ap6256;
++		mmc0 = &mmc0;
++		serial0 = &uart0;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	/*
++	 * This regulator is PWM-controlled, but the PWM controller is not
++	 * yet supported, so fix the regulator to its default voltage.
++	 */
++	reg_vdd_cpu: vdd-cpu {
++		compatible = "regulator-fixed";
++		regulator-name = "vdd-cpu";
++		regulator-min-microvolt = <1100000>;
++		regulator-max-microvolt = <1100000>;
++		vin-supply = <&reg_vcc>;
++	};
++
++	wifi_pwrseq: wifi-pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		reset-gpios = <&pio 6 11 GPIO_ACTIVE_LOW>; /* PG11/GPIO3 */
++	};
++};
++
++&cpu0 {
++	cpu-supply = <&reg_vdd_cpu>;
++};
++
++&ehci1 {
++	status = "okay";
++};
++
++&i2c0 {
++	pinctrl-0 = <&i2c0_pb10_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++
++	axp221: pmic@34 {
++		compatible = "x-powers,axp228", "x-powers,axp221";
++		reg = <0x34>;
++		interrupt-parent = <&pio>;
++		interrupts = <4 9 IRQ_TYPE_LEVEL_LOW>; /* PE9/GPIO2 */
++		interrupt-controller;
++		#interrupt-cells = <1>;
++
++		ac_power_supply: ac-power {
++			compatible = "x-powers,axp221-ac-power-supply";
++		};
++
++		axp_adc: adc {
++			compatible = "x-powers,axp221-adc";
++			#io-channel-cells = <1>;
++		};
++
++		battery_power_supply: battery-power {
++			compatible = "x-powers,axp221-battery-power-supply";
++		};
++
++		regulators {
++			x-powers,dcdc-freq = <3000>;
++
++			reg_dcdc1: dcdc1 {
++				regulator-name = "sys-3v3";
++				regulator-always-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++			};
++
++			reg_dcdc3: dcdc3 {
++				regulator-name = "sys-1v8";
++				regulator-always-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++			};
++
++			reg_aldo1: aldo1 {
++				regulator-name = "aud-3v3";
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++			};
++
++			reg_aldo2: aldo2 {
++				regulator-name = "disp-3v3";
++				regulator-always-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++			};
++
++			reg_aldo3: aldo3 {
++				regulator-name = "vdd-wifi";
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++			};
++
++			/* DLDO1 and ELDO1-3 are connected in parallel. */
++			reg_dldo1: dldo1 {
++				regulator-name = "vbat-wifi-a";
++				regulator-always-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++			};
++
++			/* DLDO2-DLDO4 are connected in parallel. */
++			reg_dldo2: dldo2 {
++				regulator-name = "vcc-3v3-ext-a";
++				regulator-always-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++			};
++
++			reg_dldo3: dldo3 {
++				regulator-name = "vcc-3v3-ext-b";
++				regulator-always-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++			};
++
++			reg_dldo4: dldo4 {
++				regulator-name = "vcc-3v3-ext-c";
++				regulator-always-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++			};
++
++			reg_eldo1: eldo1 {
++				regulator-name = "vbat-wifi-b";
++				regulator-always-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++			};
++
++			reg_eldo2: eldo2 {
++				regulator-name = "vbat-wifi-c";
++				regulator-always-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++			};
++
++			reg_eldo3: eldo3 {
++				regulator-name = "vbat-wifi-d";
++				regulator-always-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++			};
++		};
++
++		usb_power_supply: usb-power {
++			compatible = "x-powers,axp221-usb-power-supply";
++			status = "disabled";
++		};
++	};
++};
++
++&mmc0 {
++	broken-cd;
++	bus-width = <4>;
++	disable-wp;
++	vmmc-supply = <&reg_dcdc1>;
++	vqmmc-supply = <&reg_vcc_3v3>;
++	pinctrl-0 = <&mmc0_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
++&mmc1 {
++	bus-width = <4>;
++	mmc-pwrseq = <&wifi_pwrseq>;
++	non-removable;
++	vmmc-supply = <&reg_dldo1>;
++	vqmmc-supply = <&reg_aldo3>;
++	pinctrl-0 = <&mmc1_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++
++	ap6256: wifi@1 {
++		compatible = "brcm,bcm43456-fmac", "brcm,bcm4329-fmac";
++		reg = <1>;
++		interrupt-parent = <&pio>;
++		interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10/GPIO4 */
++		interrupt-names = "host-wake";
++	};
++};
++
++&ohci1 {
++	status = "okay";
++};
++
++&pio {
++	vcc-pg-supply = <&reg_ldoa>;
++};
++
++&uart0 {
++	pinctrl-0 = <&uart0_pb8_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
++&uart1 {
++	uart-has-rtscts;
++	pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++
++	bluetooth {
++		compatible = "brcm,bcm4345c5";
++		interrupt-parent = <&pio>;
++		interrupts = <6 17 IRQ_TYPE_LEVEL_HIGH>; /* PG17/GPIO6 */
++		device-wakeup-gpios = <&pio 6 16 GPIO_ACTIVE_HIGH>; /* PG16/GPIO7 */
++		shutdown-gpios = <&pio 6 18 GPIO_ACTIVE_HIGH>; /* PG18/GPIO5 */
++		max-speed = <1500000>;
++		vbat-supply = <&reg_dldo1>;
++		vddio-supply = <&reg_aldo3>;
++	};
++};
++
++&usb_otg {
++	dr_mode = "peripheral";
++	status = "okay";
++};
++
++&usbphy {
++	usb0_vbus_power-supply = <&ac_power_supply>;
++	status = "okay";
++};
+--- /dev/null
++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-devterm-v3.14.dts
+@@ -0,0 +1,37 @@
++// SPDX-License-Identifier: (GPL-2.0+ or MIT)
++// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
++
++/dts-v1/;
++
++#include "sun20i-d1-clockworkpi-v3.14.dts"
++
++/ {
++	model = "Clockwork DevTerm (R-01)";
++	compatible = "clockwork,r-01-devterm-v3.14",
++		     "clockwork,r-01-clockworkpi-v3.14",
++		     "allwinner,sun20i-d1";
++
++	fan {
++		compatible = "gpio-fan";
++		gpios = <&pio 3 10 GPIO_ACTIVE_HIGH>; /* PD10/GPIO41 */
++		gpio-fan,speed-map = <0    0>,
++				     <6000 1>;
++		#cooling-cells = <2>;
++	};
++
++	i2c-gpio-0 {
++		compatible = "i2c-gpio";
++		sda-gpios = <&pio 3 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PD14/GPIO44 */
++		scl-gpios = <&pio 3 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PD15/GPIO45 */
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		adc@54 {
++			compatible = "ti,adc101c";
++			reg = <0x54>;
++			interrupt-parent = <&pio>;
++			interrupts = <4 12 IRQ_TYPE_LEVEL_LOW>; /* PE12/GPIO35 */
++			vref-supply = <&reg_dldo2>;
++		};
++	};
++};
diff --git a/target/linux/d1/patches-6.1/0034-riscv-Add-the-Allwinner-SoC-family-Kconfig-option.patch b/target/linux/d1/patches-6.1/0034-riscv-Add-the-Allwinner-SoC-family-Kconfig-option.patch
new file mode 100644
index 00000000000000..b31537d15029c5
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0034-riscv-Add-the-Allwinner-SoC-family-Kconfig-option.patch
@@ -0,0 +1,44 @@
+From f648ec2a040efde432876ee04240cb71e4c24d6e Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 16 May 2021 14:17:45 -0500
+Subject: [PATCH 034/117] riscv: Add the Allwinner SoC family Kconfig option
+
+Allwinner manufactures the sunxi family of application processors. This
+includes the "sun8i" series of ARMv7 SoCs, the "sun50i" series of ARMv8
+SoCs, and now the "sun20i" series of 64-bit RISC-V SoCs.
+
+The first SoC in the sun20i series is D1, containing a single T-HEAD
+C906 core. D1s is a low-pin-count variant of D1 with co-packaged DRAM.
+
+Most peripherals are shared across the entire chip family. In fact, the
+ARMv7 T113 SoC is pin-compatible and almost entirely register-compatible
+with the D1s.
+
+This means many existing device drivers can be reused. To facilitate
+this reuse, name the symbol ARCH_SUNXI, since that is what the existing
+drivers have as their dependency.
+
+Reviewed-by: Heiko Stuebner <heiko@sntech.de>
+Tested-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/riscv/Kconfig.socs | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+--- a/arch/riscv/Kconfig.socs
++++ b/arch/riscv/Kconfig.socs
+@@ -1,5 +1,14 @@
+ menu "SoC selection"
+ 
++config ARCH_SUNXI
++	bool "Allwinner sun20i SoCs"
++	select ERRATA_THEAD if MMU && !XIP_KERNEL
++	select SIFIVE_PLIC
++	select SUN4I_TIMER
++	help
++	  This enables support for Allwinner sun20i platform hardware,
++	  including boards based on the D1 and D1s SoCs.
++
+ config SOC_MICROCHIP_POLARFIRE
+ 	bool "Microchip PolarFire SoCs"
+ 	select MCHP_CLK_MPFS
diff --git a/target/linux/d1/patches-6.1/0035-riscv-defconfig-Enable-the-Allwinner-D1-platform-and.patch b/target/linux/d1/patches-6.1/0035-riscv-defconfig-Enable-the-Allwinner-D1-platform-and.patch
new file mode 100644
index 00000000000000..2c172c8ad82923
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0035-riscv-defconfig-Enable-the-Allwinner-D1-platform-and.patch
@@ -0,0 +1,127 @@
+From 73f9cc8568b6b821107d5194fa868e922b159091 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Mon, 27 Jun 2022 01:33:05 -0500
+Subject: [PATCH 035/117] riscv: defconfig: Enable the Allwinner D1 platform
+ and drivers
+
+Now that several D1-based boards are supported, enable the platform in
+our defconfig. Build in the drivers which are necessary to boot, such as
+the pinctrl, MMC, RTC (which provides critical clocks), SPI (for flash),
+and watchdog (which may be left enabled by the bootloader). Other common
+onboard peripherals are enabled as modules.
+
+Cover-letter:
+riscv: Allwinner D1 platform support
+This series adds the Kconfig/defconfig plumbing and devicetrees for a
+range of Allwinner D1-based boards. Many features are already enabled,
+including USB, Ethernet, and WiFi.
+
+The SoC devicetree uses bindings from the following series which have
+not yet been merged:
+- SRAM controller:
+  https://lore.kernel.org/lkml/20220815041248.53268-1-samuel@sholland.org/
+- NVMEM cell bits property change:
+  https://lore.kernel.org/lkml/20220814173656.11856-1-samuel@sholland.org/
+- In-package LDO regulators:
+  https://lore.kernel.org/lkml/20220815043436.20170-1-samuel@sholland.org/
+
+All three of these are required to set the correct I/O domain voltages
+in the pin controller, which I would consider important to have in the
+initial version of the devicetree.
+
+The SoC devicetree does contain one small hack to avoid a dependency on
+the audio codec binding, since that is not ready yet: the codec node
+uses a bare "simple-mfd", "syscon" compatible.
+END
+
+Series-to: Chen-Yu Tsai <wens@csie.org>
+Series-to: Jernej Skrabec <jernej.skrabec@gmail.com>
+Series-to: linux-sunxi@lists.linux.dev
+Series-to: Palmer Dabbelt <palmer@dabbelt.com>
+Series-to: Paul Walmsley <paul.walmsley@sifive.com>
+Series-to: Albert Ou <aou@eecs.berkeley.edu>
+Series-to: linux-riscv@lists.infradead.org
+Series-cc: Rob Herring <robh+dt@kernel.org>
+Series-cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
+Series-cc: devicetree@vger.kernel.org
+Series-cc: linux-kernel@vger.kernel.org
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/riscv/configs/defconfig | 23 ++++++++++++++++++++++-
+ 1 file changed, 22 insertions(+), 1 deletion(-)
+
+--- a/arch/riscv/configs/defconfig
++++ b/arch/riscv/configs/defconfig
+@@ -25,6 +25,7 @@ CONFIG_BLK_DEV_INITRD=y
+ CONFIG_EXPERT=y
+ # CONFIG_SYSFS_SYSCALL is not set
+ CONFIG_PROFILING=y
++CONFIG_ARCH_SUNXI=y
+ CONFIG_SOC_MICROCHIP_POLARFIRE=y
+ CONFIG_SOC_SIFIVE=y
+ CONFIG_SOC_STARFIVE=y
+@@ -118,22 +119,31 @@ CONFIG_VIRTIO_NET=y
+ CONFIG_MACB=y
+ CONFIG_E1000E=y
+ CONFIG_R8169=y
++CONFIG_STMMAC_ETH=m
+ CONFIG_MICROSEMI_PHY=y
+ CONFIG_INPUT_MOUSEDEV=y
++CONFIG_KEYBOARD_SUN4I_LRADC=m
+ CONFIG_SERIAL_8250=y
+ CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_DW=y
+ CONFIG_SERIAL_OF_PLATFORM=y
+ CONFIG_VIRTIO_CONSOLE=y
+ CONFIG_HW_RANDOM=y
+ CONFIG_HW_RANDOM_VIRTIO=y
++CONFIG_I2C_MV64XXX=m
+ CONFIG_SPI=y
+ CONFIG_SPI_SIFIVE=y
++CONFIG_SPI_SUN6I=y
+ # CONFIG_PTP_1588_CLOCK is not set
+-CONFIG_GPIOLIB=y
+ CONFIG_GPIO_SIFIVE=y
++CONFIG_WATCHDOG=y
++CONFIG_SUNXI_WATCHDOG=y
++CONFIG_REGULATOR=y
++CONFIG_REGULATOR_FIXED_VOLTAGE=y
+ CONFIG_DRM=m
+ CONFIG_DRM_RADEON=m
+ CONFIG_DRM_NOUVEAU=m
++CONFIG_DRM_SUN4I=m
+ CONFIG_DRM_VIRTIO_GPU=m
+ CONFIG_FB=y
+ CONFIG_FRAMEBUFFER_CONSOLE=y
+@@ -146,19 +156,30 @@ CONFIG_USB_OHCI_HCD=y
+ CONFIG_USB_OHCI_HCD_PLATFORM=y
+ CONFIG_USB_STORAGE=y
+ CONFIG_USB_UAS=y
++CONFIG_USB_MUSB_HDRC=m
++CONFIG_USB_MUSB_SUNXI=m
++CONFIG_NOP_USB_XCEIV=m
+ CONFIG_MMC=y
+ CONFIG_MMC_SDHCI=y
+ CONFIG_MMC_SDHCI_PLTFM=y
+ CONFIG_MMC_SDHCI_CADENCE=y
+ CONFIG_MMC_SPI=y
++CONFIG_MMC_SUNXI=y
+ CONFIG_RTC_CLASS=y
++CONFIG_RTC_DRV_SUN6I=y
++CONFIG_DMADEVICES=y
++CONFIG_DMA_SUN6I=m
+ CONFIG_VIRTIO_PCI=y
+ CONFIG_VIRTIO_BALLOON=y
+ CONFIG_VIRTIO_INPUT=y
+ CONFIG_VIRTIO_MMIO=y
++CONFIG_SUN8I_DE2_CCU=m
++CONFIG_SUN50I_IOMMU=y
+ CONFIG_RPMSG_CHAR=y
+ CONFIG_RPMSG_CTRL=y
+ CONFIG_RPMSG_VIRTIO=y
++CONFIG_PHY_SUN4I_USB=m
++CONFIG_NVMEM_SUNXI_SID=y
+ CONFIG_EXT4_FS=y
+ CONFIG_EXT4_FS_POSIX_ACL=y
+ CONFIG_EXT4_FS_SECURITY=y
diff --git a/target/linux/d1/patches-6.1/0036-riscv-dts-allwinner-Add-Bluetooth-PCM-audio.patch b/target/linux/d1/patches-6.1/0036-riscv-dts-allwinner-Add-Bluetooth-PCM-audio.patch
new file mode 100644
index 00000000000000..0ef4b3c56be206
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0036-riscv-dts-allwinner-Add-Bluetooth-PCM-audio.patch
@@ -0,0 +1,80 @@
+From bf83f1dc034111aac1f23b98d7205d08c7c83208 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Wed, 17 Aug 2022 02:33:25 -0500
+Subject: [PATCH 036/117] riscv: dts: allwinner: Add Bluetooth PCM audio
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ .../allwinner/sun20i-d1-clockworkpi-v3.14.dts | 47 +++++++++++++++++++
+ 1 file changed, 47 insertions(+)
+
+--- a/arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts
++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts
+@@ -22,6 +22,32 @@
+ 		stdout-path = "serial0:115200n8";
+ 	};
+ 
++	bt_sco_codec: bt-sco-codec {
++		#sound-dai-cells = <0>;
++		compatible = "linux,bt-sco";
++	};
++
++	bt-sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,name = "Bluetooth";
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		simple-audio-card,dai-link@0 {
++			format = "dsp_a";
++			frame-master = <&bt_sound_cpu>;
++			bitclock-master = <&bt_sound_cpu>;
++
++			bt_sound_cpu: cpu {
++				sound-dai = <&i2s1>;
++			};
++
++			codec {
++				sound-dai = <&bt_sco_codec>;
++			};
++		};
++	};
++
+ 	/*
+ 	 * This regulator is PWM-controlled, but the PWM controller is not
+ 	 * yet supported, so fix the regulator to its default voltage.
+@@ -169,6 +195,12 @@
+ 	};
+ };
+ 
++&i2s1 {
++	pinctrl-0 = <&i2s1_clk_pins>, <&i2s1_din_pin>, <&i2s1_dout_pin>;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
+ &mmc0 {
+ 	broken-cd;
+ 	bus-width = <4>;
+@@ -205,6 +237,21 @@
+ 
+ &pio {
+ 	vcc-pg-supply = <&reg_ldoa>;
++
++	i2s1_clk_pins: i2s1-clk-pins {
++		pins = "PG12", "PG13";
++		function = "i2s1";
++	};
++
++	i2s1_din_pin: i2s1-din-pin {
++		pins = "PG14";
++		function = "i2s1_din";
++	};
++
++	i2s1_dout_pin: i2s1-dout-pin {
++		pins = "PG15";
++		function = "i2s1_dout";
++	};
+ };
+ 
+ &uart0 {
diff --git a/target/linux/d1/patches-6.1/0037-dt-bindings-crypto-sun8i-ce-Add-compatible-for-D1.patch b/target/linux/d1/patches-6.1/0037-dt-bindings-crypto-sun8i-ce-Add-compatible-for-D1.patch
new file mode 100644
index 00000000000000..1aee036b10bd9e
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0037-dt-bindings-crypto-sun8i-ce-Add-compatible-for-D1.patch
@@ -0,0 +1,87 @@
+From 690b8d708e0193d50522f70359bcab62a2f99742 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 14 Nov 2021 09:04:29 -0600
+Subject: [PATCH 037/117] dt-bindings: crypto: sun8i-ce: Add compatible for D1
+
+D1 has a crypto engine similar to the one in other Allwinner SoCs.
+Like H6, it has a separate MBUS clock gate.
+
+It also requires the internal RC oscillator to be enabled for the TRNG
+to return data. This is likely the case for earlier variants as well,
+but the clock drivers for earlier SoCs did not allow disabling the RC
+oscillator.
+
+Series-changes: 2
+ - Add TRNG clock
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ .../bindings/crypto/allwinner,sun8i-ce.yaml   | 31 ++++++++++++++-----
+ 1 file changed, 23 insertions(+), 8 deletions(-)
+
+--- a/Documentation/devicetree/bindings/crypto/allwinner,sun8i-ce.yaml
++++ b/Documentation/devicetree/bindings/crypto/allwinner,sun8i-ce.yaml
+@@ -14,6 +14,7 @@ properties:
+     enum:
+       - allwinner,sun8i-h3-crypto
+       - allwinner,sun8i-r40-crypto
++      - allwinner,sun20i-d1-crypto
+       - allwinner,sun50i-a64-crypto
+       - allwinner,sun50i-h5-crypto
+       - allwinner,sun50i-h6-crypto
+@@ -29,6 +30,7 @@ properties:
+       - description: Bus clock
+       - description: Module clock
+       - description: MBus clock
++      - description: TRNG clock (RC oscillator)
+     minItems: 2
+ 
+   clock-names:
+@@ -36,6 +38,7 @@ properties:
+       - const: bus
+       - const: mod
+       - const: ram
++      - const: trng
+     minItems: 2
+ 
+   resets:
+@@ -44,19 +47,31 @@ properties:
+ if:
+   properties:
+     compatible:
+-      const: allwinner,sun50i-h6-crypto
++      enum:
++        - allwinner,sun20i-d1-crypto
+ then:
+   properties:
+     clocks:
+-      minItems: 3
++      minItems: 4
+     clock-names:
+-      minItems: 3
++      minItems: 4
+ else:
+-  properties:
+-    clocks:
+-      maxItems: 2
+-    clock-names:
+-      maxItems: 2
++  if:
++    properties:
++      compatible:
++        const: allwinner,sun50i-h6-crypto
++  then:
++    properties:
++      clocks:
++        minItems: 3
++      clock-names:
++        minItems: 3
++  else:
++    properties:
++      clocks:
++        maxItems: 2
++      clock-names:
++        maxItems: 2
+ 
+ required:
+   - compatible
diff --git a/target/linux/d1/patches-6.1/0038-crypto-sun8i-ce-Add-TRNG-clock-to-D1-variant.patch b/target/linux/d1/patches-6.1/0038-crypto-sun8i-ce-Add-TRNG-clock-to-D1-variant.patch
new file mode 100644
index 00000000000000..b8344ce5ce31f3
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0038-crypto-sun8i-ce-Add-TRNG-clock-to-D1-variant.patch
@@ -0,0 +1,47 @@
+From d09357656ae3985095f562cf005fa94fd61ebfe6 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Tue, 1 Feb 2022 21:50:16 -0600
+Subject: [PATCH 038/117] crypto: sun8i-ce - Add TRNG clock to D1 variant
+
+At least the D1 variant requires a separate clock for the TRNG.
+Without this clock enabled, reading from /dev/hwrng reports:
+
+   sun8i-ce 3040000.crypto: DMA timeout for TRNG (tm=96) on flow 3
+
+Experimentation shows that the necessary clock is the SoC's internal
+RC oscillator. This makes sense, as the oscillator's frequency
+variations can be used as a source of randomness.
+
+Since D1 does not yet have a device tree, we can update this variant
+without breaking anything.
+
+Series-changes: 2
+ - New patch
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c | 1 +
+ drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h      | 2 +-
+ 2 files changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
++++ b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
+@@ -118,6 +118,7 @@ static const struct ce_variant ce_d1_var
+ 		{ "bus", 0, 200000000 },
+ 		{ "mod", 300000000, 0 },
+ 		{ "ram", 0, 400000000 },
++		{ "trng", 0, 0 },
+ 		},
+ 	.esr = ESR_D1,
+ 	.prng = CE_ALG_PRNG,
+--- a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h
++++ b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h
+@@ -105,7 +105,7 @@
+ 
+ #define MAX_SG 8
+ 
+-#define CE_MAX_CLOCKS 3
++#define CE_MAX_CLOCKS 4
+ 
+ #define MAXFLOW 4
+ 
diff --git a/target/linux/d1/patches-6.1/0039-riscv-dts-allwinner-d1-Add-crypto-engine-support.patch b/target/linux/d1/patches-6.1/0039-riscv-dts-allwinner-d1-Add-crypto-engine-support.patch
new file mode 100644
index 00000000000000..05289b737c779d
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0039-riscv-dts-allwinner-d1-Add-crypto-engine-support.patch
@@ -0,0 +1,31 @@
+From 5dae72bf0e0fabb3164dbc4b5eee310c63f1975c Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Thu, 11 Aug 2022 22:20:31 -0500
+Subject: [PATCH 039/117] riscv: dts: allwinner: d1: Add crypto engine support
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+--- a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
+@@ -457,6 +457,18 @@
+ 			};
+ 		};
+ 
++		crypto: crypto@3040000 {
++			compatible = "allwinner,sun20i-d1-crypto";
++			reg = <0x3040000 0x800>;
++			interrupts = <68 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_CE>,
++				 <&ccu CLK_CE>,
++				 <&ccu CLK_MBUS_CE>,
++				 <&rtc CLK_IOSC>;
++			clock-names = "bus", "mod", "ram", "trng";
++			resets = <&ccu RST_BUS_CE>;
++		};
++
+ 		mbus: dram-controller@3102000 {
+ 			compatible = "allwinner,sun20i-d1-mbus";
+ 			reg = <0x3102000 0x1000>,
diff --git a/target/linux/d1/patches-6.1/0040-ASoC-sun50i-dmic-dt-bindings-Add-D1-compatible-strin.patch b/target/linux/d1/patches-6.1/0040-ASoC-sun50i-dmic-dt-bindings-Add-D1-compatible-strin.patch
new file mode 100644
index 00000000000000..abc4608e193f4f
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0040-ASoC-sun50i-dmic-dt-bindings-Add-D1-compatible-strin.patch
@@ -0,0 +1,27 @@
+From 7a24e5ee94e0163801c8ab4c131ae1d530a420ea Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Wed, 17 Aug 2022 02:08:36 -0500
+Subject: [PATCH 040/117] ASoC: sun50i-dmic: dt-bindings: Add D1 compatible
+ string
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ .../bindings/sound/allwinner,sun50i-h6-dmic.yaml           | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+--- a/Documentation/devicetree/bindings/sound/allwinner,sun50i-h6-dmic.yaml
++++ b/Documentation/devicetree/bindings/sound/allwinner,sun50i-h6-dmic.yaml
+@@ -11,7 +11,12 @@ maintainers:
+ 
+ properties:
+   compatible:
+-    const: allwinner,sun50i-h6-dmic
++    oneOf:
++      - items:
++          - enum:
++              - allwinner,sun20i-d1-dmic
++          - const: allwinner,sun50i-h6-dmic
++      - const: allwinner,sun50i-h6-dmic
+ 
+   "#sound-dai-cells":
+     const: 0
diff --git a/target/linux/d1/patches-6.1/0041-riscv-dts-allwinner-d1-Add-DMIC-node.patch b/target/linux/d1/patches-6.1/0041-riscv-dts-allwinner-d1-Add-DMIC-node.patch
new file mode 100644
index 00000000000000..1d838c92bf3258
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0041-riscv-dts-allwinner-d1-Add-DMIC-node.patch
@@ -0,0 +1,34 @@
+From d73f2176958e405e55c4e782c6d0f888e20080e5 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Wed, 17 Aug 2022 02:08:58 -0500
+Subject: [PATCH 041/117] riscv: dts: allwinner: d1: Add DMIC node
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+--- a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
+@@ -208,6 +208,21 @@
+ 			};
+ 		};
+ 
++		dmic: dmic@2031000 {
++			compatible = "allwinner,sun20i-d1-dmic",
++				     "allwinner,sun50i-h6-dmic";
++			reg = <0x2031000 0x400>;
++			interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_DMIC>,
++				 <&ccu CLK_DMIC>;
++			clock-names = "bus", "mod";
++			resets = <&ccu RST_BUS_DMIC>;
++			dmas = <&dma 8>;
++			dma-names = "rx";
++			status = "disabled";
++			#sound-dai-cells = <0>;
++		};
++
+ 		i2s0: i2s@2032000 {
+ 			compatible = "allwinner,sun20i-d1-i2s",
+ 				     "allwinner,sun50i-r329-i2s";
diff --git a/target/linux/d1/patches-6.1/0042-riscv-dts-allwinner-Add-DMIC-sound-cards.patch b/target/linux/d1/patches-6.1/0042-riscv-dts-allwinner-Add-DMIC-sound-cards.patch
new file mode 100644
index 00000000000000..1aec73b70f365f
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0042-riscv-dts-allwinner-Add-DMIC-sound-cards.patch
@@ -0,0 +1,144 @@
+From 500a3fc1ce1b216ef4f4df73e4e048170764189e Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Wed, 17 Aug 2022 02:20:49 -0500
+Subject: [PATCH 042/117] riscv: dts: allwinner: Add DMIC sound cards
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ .../sun20i-d1-lichee-rv-86-panel.dtsi         | 43 ++++++++++++++++++
+ .../allwinner/sun20i-d1-lichee-rv-dock.dts    | 45 +++++++++++++++++++
+ 2 files changed, 88 insertions(+)
+
+--- a/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel.dtsi
++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel.dtsi
+@@ -9,6 +9,33 @@
+ 		ethernet1 = &xr829;
+ 	};
+ 
++	dmic_codec: dmic-codec {
++		compatible = "dmic-codec";
++		num-channels = <2>;
++		#sound-dai-cells = <0>;
++	};
++
++	dmic-sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,name = "DMIC";
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		simple-audio-card,dai-link@0 {
++			format = "pdm";
++			frame-master = <&link0_cpu>;
++			bitclock-master = <&link0_cpu>;
++
++			link0_cpu: cpu {
++				sound-dai = <&dmic>;
++			};
++
++			link0_codec: codec {
++				sound-dai = <&dmic_codec>;
++			};
++		};
++	};
++
+ 	/* PC1 is repurposed as BT_WAKE_AP */
+ 	/delete-node/ leds;
+ 
+@@ -24,6 +51,12 @@
+ 	};
+ };
+ 
++&dmic {
++	pinctrl-0 = <&dmic_pb11_d0_pin>, <&dmic_pe17_clk_pin>;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
+ &ehci1 {
+ 	status = "okay";
+ };
+@@ -69,6 +102,16 @@
+ 		pins = "PG11";
+ 		function = "clk";
+ 	};
++
++	dmic_pb11_d0_pin: dmic-pb11-d0-pin {
++		pins = "PB11";
++		function = "dmic";
++	};
++
++	dmic_pe17_clk_pin: dmic-pe17-clk-pin {
++		pins = "PE17";
++		function = "dmic";
++	};
+ };
+ 
+ &uart1 {
+--- a/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts
++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts
+@@ -15,12 +15,45 @@
+ 		ethernet1 = &rtl8723ds;
+ 	};
+ 
++	dmic_codec: dmic-codec {
++		compatible = "dmic-codec";
++		num-channels = <2>;
++		#sound-dai-cells = <0>;
++	};
++
++	dmic-sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,name = "DMIC";
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		simple-audio-card,dai-link@0 {
++			format = "pdm";
++			frame-master = <&link0_cpu>;
++			bitclock-master = <&link0_cpu>;
++
++			link0_cpu: cpu {
++				sound-dai = <&dmic>;
++			};
++
++			link0_codec: codec {
++				sound-dai = <&dmic_codec>;
++			};
++		};
++	};
++
+ 	wifi_pwrseq: wifi-pwrseq {
+ 		compatible = "mmc-pwrseq-simple";
+ 		reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
+ 	};
+ };
+ 
++&dmic {
++	pinctrl-0 = <&dmic_pb11_d0_pin>, <&dmic_pe17_clk_pin>;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
+ &ehci1 {
+ 	status = "okay";
+ };
+@@ -55,6 +88,18 @@
+ 	status = "okay";
+ };
+ 
++&pio {
++	dmic_pb11_d0_pin: dmic-pb11-d0-pin {
++		pins = "PB11";
++		function = "dmic";
++	};
++
++	dmic_pe17_clk_pin: dmic-pe17-clk-pin {
++		pins = "PE17";
++		function = "dmic";
++	};
++};
++
+ &uart1 {
+ 	uart-has-rtscts;
+ 	pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
diff --git a/target/linux/d1/patches-6.1/0043-hwspinlock-sun6i-Clarify-bank-counting-logic.patch b/target/linux/d1/patches-6.1/0043-hwspinlock-sun6i-Clarify-bank-counting-logic.patch
new file mode 100644
index 00000000000000..e7fb8877725801
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0043-hwspinlock-sun6i-Clarify-bank-counting-logic.patch
@@ -0,0 +1,64 @@
+From 7708f7471ab45039e08237b42121d0372f9216a7 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 13 Jun 2021 23:42:19 -0500
+Subject: [PATCH 043/117] hwspinlock: sun6i: Clarify bank counting logic
+
+In some of the most recent datasheets, the register definition was
+updated in a way that resolves the conflict here: the field is only two
+bits wide, and a value of "4" really means a bit pattern of "0". Correct
+the code to reflect this, but leave an updated comment because some
+datasheets still have incorrect information in them.
+
+Fixes: 3c881e05c814 ("hwspinlock: add sun6i hardware spinlock support")
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/hwspinlock/sun6i_hwspinlock.c | 36 +++++++++++----------------
+ 1 file changed, 14 insertions(+), 22 deletions(-)
+
+--- a/drivers/hwspinlock/sun6i_hwspinlock.c
++++ b/drivers/hwspinlock/sun6i_hwspinlock.c
+@@ -129,30 +129,22 @@ static int sun6i_hwspinlock_probe(struct
+ 	}
+ 
+ 	/*
+-	 * bit 28 and 29 represents the hwspinlock setup
++	 * Bits 28 and 29 represent the number of available locks.
+ 	 *
+-	 * every datasheet (A64, A80, A83T, H3, H5, H6 ...) says the default value is 0x1 and 0x1
+-	 * to 0x4 represent 32, 64, 128 and 256 locks
+-	 * but later datasheets (H5, H6) say 00, 01, 10, 11 represent 32, 64, 128 and 256 locks,
+-	 * but that would mean H5 and H6 have 64 locks, while their datasheets talk about 32 locks
+-	 * all the time, not a single mentioning of 64 locks
+-	 * the 0x4 value is also not representable by 2 bits alone, so some datasheets are not
+-	 * correct
+-	 * one thing have all in common, default value of the sysstatus register is 0x10000000,
+-	 * which results in bit 28 being set
+-	 * this is the reason 0x1 is considered being 32 locks and bit 30 is taken into account
+-	 * verified on H2+ (datasheet 0x1 = 32 locks) and H5 (datasheet 01 = 64 locks)
++	 * The datasheets have two conflicting interpretations for these bits:
++	 *   |  00 | 01 |  10 |  11 |
++	 *   +-----+----+-----+-----+
++	 *   | 256 | 32 |  64 | 128 | A80, A83T, H3, A64, A50, D1
++	 *   |  32 | 64 | 128 | 256 | H5, H6, R329
++	 * where some datasheets use "4" instead of "0" for the first column.
++	 *
++	 * Experiments shows that the first interpretation is correct, as all
++	 * known implementations report the value "1" and have 32 spinlocks.
+ 	 */
+-	num_banks = readl(io_base + SPINLOCK_SYSSTATUS_REG) >> 28;
+-	switch (num_banks) {
+-	case 1 ... 4:
+-		priv->nlocks = 1 << (4 + num_banks);
+-		break;
+-	default:
+-		err = -EINVAL;
+-		dev_err(&pdev->dev, "unsupported hwspinlock setup (%d)\n", num_banks);
+-		goto bank_fail;
+-	}
++	num_banks = readl(io_base + SPINLOCK_SYSSTATUS_REG) >> 28 & 0x3;
++	if (!num_banks)
++		num_banks = 4;
++	priv->nlocks = 1 << (4 + num_banks);
+ 
+ 	priv->bank = devm_kzalloc(&pdev->dev, struct_size(priv->bank, lock, priv->nlocks),
+ 				  GFP_KERNEL);
diff --git a/target/linux/d1/patches-6.1/0044-hwspinlock-sun6i-Fix-driver-to-match-binding.patch b/target/linux/d1/patches-6.1/0044-hwspinlock-sun6i-Fix-driver-to-match-binding.patch
new file mode 100644
index 00000000000000..23adcd3af32a95
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0044-hwspinlock-sun6i-Fix-driver-to-match-binding.patch
@@ -0,0 +1,37 @@
+From a19b55088945ce86051ea4eab22df27805a30c71 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 13 Jun 2021 23:41:44 -0500
+Subject: [PATCH 044/117] hwspinlock: sun6i: Fix driver to match binding
+
+The binding for this device does not allow using the clock-names and
+reset-names properties, so the driver should not reference the clock or
+reset by name.
+
+Fixes: 3c881e05c814 ("hwspinlock: add sun6i hardware spinlock support")
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/hwspinlock/sun6i_hwspinlock.c | 12 +++++-------
+ 1 file changed, 5 insertions(+), 7 deletions(-)
+
+--- a/drivers/hwspinlock/sun6i_hwspinlock.c
++++ b/drivers/hwspinlock/sun6i_hwspinlock.c
+@@ -104,14 +104,12 @@ static int sun6i_hwspinlock_probe(struct
+ 	if (!priv)
+ 		return -ENOMEM;
+ 
+-	priv->ahb_clk = devm_clk_get(&pdev->dev, "ahb");
+-	if (IS_ERR(priv->ahb_clk)) {
+-		err = PTR_ERR(priv->ahb_clk);
+-		dev_err(&pdev->dev, "unable to get AHB clock (%d)\n", err);
+-		return err;
+-	}
++	priv->ahb_clk = devm_clk_get(&pdev->dev, NULL);
++	if (IS_ERR(priv->ahb_clk))
++		return dev_err_probe(&pdev->dev, PTR_ERR(priv->ahb_clk),
++				     "unable to get AHB clock\n");
+ 
+-	priv->reset = devm_reset_control_get(&pdev->dev, "ahb");
++	priv->reset = devm_reset_control_get(&pdev->dev, NULL);
+ 	if (IS_ERR(priv->reset))
+ 		return dev_err_probe(&pdev->dev, PTR_ERR(priv->reset),
+ 				     "unable to get reset control\n");
diff --git a/target/linux/d1/patches-6.1/0045-dt-bindings-hwlock-sun6i-Add-interrupts-property.patch b/target/linux/d1/patches-6.1/0045-dt-bindings-hwlock-sun6i-Add-interrupts-property.patch
new file mode 100644
index 00000000000000..d2c61a54ddb12b
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0045-dt-bindings-hwlock-sun6i-Add-interrupts-property.patch
@@ -0,0 +1,51 @@
+From f0c29c5d370507ca2106689e7e17b81e8b58f236 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 14 Nov 2021 11:37:34 -0600
+Subject: [PATCH 045/117] dt-bindings: hwlock: sun6i: Add interrupts property
+
+While it was not officially documented until recently (e.g. A50), the
+hwspinlock block can trigger an interrupt when a lock is unlocked. This
+capability is used by Allwinner's ARISC firmware, it has been verified
+to work on A64, and the IRQ numbers are reserved as far back as A31.
+So most likely this feature has always been available.
+
+Even though the Linux hwspinlock framework cannot make use of the IRQ,
+the capability should still be documented in the device tree.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ .../bindings/hwlock/allwinner,sun6i-a31-hwspinlock.yaml     | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/Documentation/devicetree/bindings/hwlock/allwinner,sun6i-a31-hwspinlock.yaml
++++ b/Documentation/devicetree/bindings/hwlock/allwinner,sun6i-a31-hwspinlock.yaml
+@@ -26,17 +26,22 @@ properties:
+   resets:
+     maxItems: 1
+ 
++  interrupts:
++    maxItems: 1
++
+ required:
+   - compatible
+   - reg
+   - clocks
+   - resets
++  - interrupts
+ 
+ additionalProperties: false
+ 
+ examples:
+   - |
+     #include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
++    #include <dt-bindings/interrupt-controller/arm-gic.h>
+     #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
+ 
+     hwlock@1c18000 {
+@@ -44,5 +49,6 @@ examples:
+         reg = <0x01c18000 0x1000>;
+         clocks = <&ccu CLK_BUS_SPINLOCK>;
+         resets = <&ccu RST_BUS_SPINLOCK>;
++        interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+     };
+ ...
diff --git a/target/linux/d1/patches-6.1/0046-dt-bindings-hwlock-sun6i-Add-per-SoC-compatibles.patch b/target/linux/d1/patches-6.1/0046-dt-bindings-hwlock-sun6i-Add-per-SoC-compatibles.patch
new file mode 100644
index 00000000000000..120232b51abb23
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0046-dt-bindings-hwlock-sun6i-Add-per-SoC-compatibles.patch
@@ -0,0 +1,39 @@
+From e7b8c42c6bf02f4c2e24b015a12cd9edad094644 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 14 Nov 2021 12:36:52 -0600
+Subject: [PATCH 046/117] dt-bindings: hwlock: sun6i: Add per-SoC compatibles
+
+While all implementations of this hardware appear to be indentical, it
+is possible that some difference exists. To be safe, add a compatible
+for each SoC integration, using the A31 compatible only as a fallback.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ .../hwlock/allwinner,sun6i-a31-hwspinlock.yaml   | 16 +++++++++++++++-
+ 1 file changed, 15 insertions(+), 1 deletion(-)
+
+--- a/Documentation/devicetree/bindings/hwlock/allwinner,sun6i-a31-hwspinlock.yaml
++++ b/Documentation/devicetree/bindings/hwlock/allwinner,sun6i-a31-hwspinlock.yaml
+@@ -15,7 +15,21 @@ description:
+ 
+ properties:
+   compatible:
+-    const: allwinner,sun6i-a31-hwspinlock
++    oneOf:
++      - items:
++          - enum:
++              - allwinner,sun8i-a23-hwspinlock
++              - allwinner,sun8i-a33-hwspinlock
++              - allwinner,sun8i-a50-hwspinlock
++              - allwinner,sun8i-a83t-hwspinlock
++              - allwinner,sun8i-h3-hwspinlock
++              - allwinner,sun9i-a80-hwspinlock
++              - allwinner,sun20i-d1-hwspinlock
++              - allwinner,sun50i-a64-hwspinlock
++              - allwinner,sun50i-h6-hwspinlock
++              - allwinner,sun50i-r329-hwspinlock
++          - const: allwinner,sun6i-a31-hwspinlock
++      - const: allwinner,sun6i-a31-hwspinlock
+ 
+   reg:
+     maxItems: 1
diff --git a/target/linux/d1/patches-6.1/0047-ASoC-sun4i-i2s-Also-set-capture-DMA-width.patch b/target/linux/d1/patches-6.1/0047-ASoC-sun4i-i2s-Also-set-capture-DMA-width.patch
new file mode 100644
index 00000000000000..c0350455c9cdea
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0047-ASoC-sun4i-i2s-Also-set-capture-DMA-width.patch
@@ -0,0 +1,20 @@
+From 419b337ac3e60126f9de0bc98892e54a8ffe3b6e Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 13 Jun 2021 23:50:57 -0500
+Subject: [PATCH 047/117] ASoC: sun4i-i2s: Also set capture DMA width
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ sound/soc/sunxi/sun4i-i2s.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/sound/soc/sunxi/sun4i-i2s.c
++++ b/sound/soc/sunxi/sun4i-i2s.c
+@@ -633,6 +633,7 @@ static int sun4i_i2s_hw_params(struct sn
+ 			params_physical_width(params));
+ 		return -EINVAL;
+ 	}
++	i2s->capture_dma_data.addr_width = width;
+ 	i2s->playback_dma_data.addr_width = width;
+ 
+ 	sr = i2s->variant->get_sr(word_size);
diff --git a/target/linux/d1/patches-6.1/0048-todo.patch b/target/linux/d1/patches-6.1/0048-todo.patch
new file mode 100644
index 00000000000000..b06f37ea376fda
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0048-todo.patch
@@ -0,0 +1,19 @@
+From dbad9a1f280b3c3e34cc133407ae057293b8aadf Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Wed, 17 Aug 2022 02:34:08 -0500
+Subject: [PATCH 048/117] todo
+
+---
+ arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
+@@ -253,6 +253,7 @@
+ 			#sound-dai-cells = <0>;
+ 		};
+ 
++		// TODO: how to integrate ASRC? same or separate node?
+ 		i2s2: i2s@2034000 {
+ 			compatible = "allwinner,sun20i-d1-i2s",
+ 				     "allwinner,sun50i-r329-i2s";
diff --git a/target/linux/d1/patches-6.1/0049-dt-bindings-iommu-sun50i-Add-compatible-for-Allwinne.patch b/target/linux/d1/patches-6.1/0049-dt-bindings-iommu-sun50i-Add-compatible-for-Allwinne.patch
new file mode 100644
index 00000000000000..63ff6234c8fd75
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0049-dt-bindings-iommu-sun50i-Add-compatible-for-Allwinne.patch
@@ -0,0 +1,46 @@
+From 031deed1d755fc9f1e4908ef70969e1458203421 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 6 Jun 2021 10:20:38 -0500
+Subject: [PATCH 049/117] dt-bindings: iommu: sun50i: Add compatible for
+ Allwinner D1
+
+D1 contains an IOMMU similar to the one in the H6 SoC, but the D1
+variant has no external reset signal.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ .../iommu/allwinner,sun50i-h6-iommu.yaml         | 16 ++++++++++++++--
+ 1 file changed, 14 insertions(+), 2 deletions(-)
+
+--- a/Documentation/devicetree/bindings/iommu/allwinner,sun50i-h6-iommu.yaml
++++ b/Documentation/devicetree/bindings/iommu/allwinner,sun50i-h6-iommu.yaml
+@@ -17,7 +17,9 @@ properties:
+       The content of the cell is the master ID.
+ 
+   compatible:
+-    const: allwinner,sun50i-h6-iommu
++    enum:
++      - allwinner,sun20i-d1-iommu
++      - allwinner,sun50i-h6-iommu
+ 
+   reg:
+     maxItems: 1
+@@ -37,7 +39,17 @@ required:
+   - reg
+   - interrupts
+   - clocks
+-  - resets
++
++if:
++  properties:
++    compatible:
++      contains:
++        enum:
++          - allwinner,sun50i-h6-iommu
++
++then:
++  required:
++    - resets
+ 
+ additionalProperties: false
+ 
diff --git a/target/linux/d1/patches-6.1/0050-iommu-sun50i-Support-variants-without-an-external-re.patch b/target/linux/d1/patches-6.1/0050-iommu-sun50i-Support-variants-without-an-external-re.patch
new file mode 100644
index 00000000000000..483746a11f5f47
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0050-iommu-sun50i-Support-variants-without-an-external-re.patch
@@ -0,0 +1,69 @@
+From 15a0487680cf506bb4b9bfee2c41b2c3176d4efa Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Wed, 27 Apr 2022 19:01:57 -0500
+Subject: [PATCH 050/117] iommu/sun50i: Support variants without an external
+ reset
+
+The IOMMU in the Allwinner D1 SoC does not have an external reset line.
+
+Only attempt to get the reset on hardware variants which should have one
+according to the binding. And switch from the deprecated function to the
+explicit "exclusive" variant.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/iommu/sun50i-iommu.c | 18 ++++++++++++++++--
+ 1 file changed, 16 insertions(+), 2 deletions(-)
+
+--- a/drivers/iommu/sun50i-iommu.c
++++ b/drivers/iommu/sun50i-iommu.c
+@@ -95,6 +95,10 @@
+ 
+ #define SPAGE_SIZE			4096
+ 
++struct sun50i_iommu_variant {
++	bool has_reset;
++};
++
+ struct sun50i_iommu {
+ 	struct iommu_device iommu;
+ 
+@@ -979,9 +983,14 @@ static irqreturn_t sun50i_iommu_irq(int
+ 
+ static int sun50i_iommu_probe(struct platform_device *pdev)
+ {
++	const struct sun50i_iommu_variant *variant;
+ 	struct sun50i_iommu *iommu;
+ 	int ret, irq;
+ 
++	variant = of_device_get_match_data(&pdev->dev);
++	if (!variant)
++		return -EINVAL;
++
+ 	iommu = devm_kzalloc(&pdev->dev, sizeof(*iommu), GFP_KERNEL);
+ 	if (!iommu)
+ 		return -ENOMEM;
+@@ -1021,7 +1030,8 @@ static int sun50i_iommu_probe(struct pla
+ 		goto err_free_group;
+ 	}
+ 
+-	iommu->reset = devm_reset_control_get(&pdev->dev, NULL);
++	if (variant->has_reset)
++		iommu->reset = devm_reset_control_get_exclusive(&pdev->dev, NULL);
+ 	if (IS_ERR(iommu->reset)) {
+ 		dev_err(&pdev->dev, "Couldn't get our reset line.\n");
+ 		ret = PTR_ERR(iommu->reset);
+@@ -1059,8 +1069,12 @@ err_free_cache:
+ 	return ret;
+ }
+ 
++static const struct sun50i_iommu_variant sun50i_h6_iommu = {
++	.has_reset = true,
++};
++
+ static const struct of_device_id sun50i_iommu_dt[] = {
+-	{ .compatible = "allwinner,sun50i-h6-iommu", },
++	{ .compatible = "allwinner,sun50i-h6-iommu", .data = &sun50i_h6_iommu },
+ 	{ /* sentinel */ },
+ };
+ MODULE_DEVICE_TABLE(of, sun50i_iommu_dt);
diff --git a/target/linux/d1/patches-6.1/0051-iommu-sun50i-Ensure-bypass-is-disabled.patch b/target/linux/d1/patches-6.1/0051-iommu-sun50i-Ensure-bypass-is-disabled.patch
new file mode 100644
index 00000000000000..3f2db0054ecc87
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0051-iommu-sun50i-Ensure-bypass-is-disabled.patch
@@ -0,0 +1,26 @@
+From 384e2ca3c049fe36f4e679fc76fcc8dfdc9297f9 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Wed, 27 Apr 2022 19:06:28 -0500
+Subject: [PATCH 051/117] iommu/sun50i: Ensure bypass is disabled
+
+The H6 variant of the hardware disables bypass by default. The D1
+variant of the hardware enables bypass for all masters by default.
+
+Since the driver expects bypass to be disabled, ensure that is the case.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/iommu/sun50i-iommu.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/iommu/sun50i-iommu.c
++++ b/drivers/iommu/sun50i-iommu.c
+@@ -445,6 +445,8 @@ static int sun50i_iommu_enable(struct su
+ 
+ 	spin_lock_irqsave(&iommu->iommu_lock, flags);
+ 
++	iommu_write(iommu, IOMMU_BYPASS_REG, 0);
++
+ 	iommu_write(iommu, IOMMU_TTB_REG, sun50i_domain->dt_dma);
+ 	iommu_write(iommu, IOMMU_TLB_PREFETCH_REG,
+ 		    IOMMU_TLB_PREFETCH_MASTER_ENABLE(0) |
diff --git a/target/linux/d1/patches-6.1/0052-iommu-sun50i-Add-support-for-the-D1-variant.patch b/target/linux/d1/patches-6.1/0052-iommu-sun50i-Add-support-for-the-D1-variant.patch
new file mode 100644
index 00000000000000..d82542a4a2b2db
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0052-iommu-sun50i-Add-support-for-the-D1-variant.patch
@@ -0,0 +1,32 @@
+From 5fdd5231c56d58f16a6cefa2bed4b8f331da2c92 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Wed, 27 Apr 2022 19:20:58 -0500
+Subject: [PATCH 052/117] iommu/sun50i: Add support for the D1 variant
+
+D1 contains an IOMMU similar to the one in the H6 SoC, but the D1
+variant has no external reset signal. It also has some register
+definition changes, but none that affect the current driver.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/iommu/sun50i-iommu.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/drivers/iommu/sun50i-iommu.c
++++ b/drivers/iommu/sun50i-iommu.c
+@@ -1071,11 +1071,15 @@ err_free_cache:
+ 	return ret;
+ }
+ 
++static const struct sun50i_iommu_variant sun20i_d1_iommu = {
++};
++
+ static const struct sun50i_iommu_variant sun50i_h6_iommu = {
+ 	.has_reset = true,
+ };
+ 
+ static const struct of_device_id sun50i_iommu_dt[] = {
++	{ .compatible = "allwinner,sun20i-d1-iommu", .data = &sun20i_d1_iommu },
+ 	{ .compatible = "allwinner,sun50i-h6-iommu", .data = &sun50i_h6_iommu },
+ 	{ /* sentinel */ },
+ };
diff --git a/target/linux/d1/patches-6.1/0053-riscv-dts-allwinner-d1-Add-IOMMU-node.patch b/target/linux/d1/patches-6.1/0053-riscv-dts-allwinner-d1-Add-IOMMU-node.patch
new file mode 100644
index 00000000000000..b3a2d53c24c0ad
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0053-riscv-dts-allwinner-d1-Add-IOMMU-node.patch
@@ -0,0 +1,43 @@
+From 4c37ac95ee354857c8c662b6b7b4bc50eea23206 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 14 Aug 2022 11:20:37 -0500
+Subject: [PATCH 053/117] riscv: dts: allwinner: d1: Add IOMMU node
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+--- a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
+@@ -188,6 +188,14 @@
+ 			status = "disabled";
+ 		};
+ 
++		iommu: iommu@2010000 {
++			compatible = "allwinner,sun20i-d1-iommu";
++			reg = <0x2010000 0x10000>;
++			interrupts = <80 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_IOMMU>;
++			#iommu-cells = <1>;
++		};
++
+ 		codec: audio-codec@2030000 {
+ 			compatible = "simple-mfd", "syscon";
+ 			reg = <0x2030000 0x1000>;
+@@ -681,6 +689,7 @@
+ 				 <&display_clocks CLK_MIXER0>;
+ 			clock-names = "bus", "mod";
+ 			resets = <&display_clocks RST_MIXER0>;
++			iommus = <&iommu 2>;
+ 
+ 			ports {
+ 				#address-cells = <1>;
+@@ -703,6 +712,7 @@
+ 				 <&display_clocks CLK_MIXER1>;
+ 			clock-names = "bus", "mod";
+ 			resets = <&display_clocks RST_MIXER1>;
++			iommus = <&iommu 2>;
+ 
+ 			ports {
+ 				#address-cells = <1>;
diff --git a/target/linux/d1/patches-6.1/0054-dt-bindings-leds-Add-Allwinner-A100-LED-controller.patch b/target/linux/d1/patches-6.1/0054-dt-bindings-leds-Add-Allwinner-A100-LED-controller.patch
new file mode 100644
index 00000000000000..548a92efb54d3f
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0054-dt-bindings-leds-Add-Allwinner-A100-LED-controller.patch
@@ -0,0 +1,179 @@
+From 31857adcc9db7244a047a3a3550219f7559d8846 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Wed, 4 Aug 2021 21:36:26 -0500
+Subject: [PATCH 054/117] dt-bindings: leds: Add Allwinner A100 LED controller
+
+The Allwinner A100, R329, and D1 SoCs contain an LED controller designed
+to drive a series of RGB LED pixels. It supports PIO and DMA transfers,
+and has configurable timing and pixel format. All three implementations
+appear to be identical, so use the oldest as the fallback compatible.
+
+Series-changes: 2
+ - Fixed typo leading to duplicate t1h-ns property
+ - Removed "items" layer in definition of dmas/dma-names
+ - Replaced uint32 type reference with maxItems in timing properties
+
+Series-changes: 3
+ - Removed quotes from enumeration values
+ - Added vendor prefix to timing/format properties
+ - Renamed "format" property to "pixel-format" for clarity
+ - Dropped "vled-supply" as it is unrelated to the controller hardware
+
+Series-changes: 4
+ - Use "default" instead of "maxItems" for timing properties
+
+Series-changes: 5
+ - A100 contains the original implementation, so use that as the base
+   compatible string, and rename the binding to match
+ - Add "unevaluatedProperties: false" to the child multi-led binding
+
+Acked-by: Maxime Ripard <maxime@cerno.tech>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ .../leds/allwinner,sun50i-a100-ledc.yaml      | 139 ++++++++++++++++++
+ 1 file changed, 139 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/leds/allwinner,sun50i-a100-ledc.yaml
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/leds/allwinner,sun50i-a100-ledc.yaml
+@@ -0,0 +1,139 @@
++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/leds/allwinner,sun50i-a100-ledc.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Allwinner A100 LED Controller Bindings
++
++maintainers:
++  - Samuel Holland <samuel@sholland.org>
++
++description:
++  The LED controller found in Allwinner sunxi SoCs uses a one-wire serial
++  interface to drive up to 1024 RGB LEDs.
++
++properties:
++  compatible:
++    oneOf:
++      - const: allwinner,sun50i-a100-ledc
++      - items:
++          - enum:
++              - allwinner,sun20i-d1-ledc
++              - allwinner,sun50i-r329-ledc
++          - const: allwinner,sun50i-a100-ledc
++
++  reg:
++    maxItems: 1
++
++  "#address-cells":
++    const: 1
++
++  "#size-cells":
++    const: 0
++
++  interrupts:
++    maxItems: 1
++
++  clocks:
++    items:
++      - description: Bus clock
++      - description: Module clock
++
++  clock-names:
++    items:
++      - const: bus
++      - const: mod
++
++  resets:
++    maxItems: 1
++
++  dmas:
++    maxItems: 1
++    description: TX DMA channel
++
++  dma-names:
++    const: tx
++
++  allwinner,pixel-format:
++    description: Pixel format (subpixel transmission order), default is "grb"
++    enum:
++      - bgr
++      - brg
++      - gbr
++      - grb
++      - rbg
++      - rgb
++
++  allwinner,t0h-ns:
++    default: 336
++    description: Length of high pulse when transmitting a "0" bit
++
++  allwinner,t0l-ns:
++    default: 840
++    description: Length of low pulse when transmitting a "0" bit
++
++  allwinner,t1h-ns:
++    default: 882
++    description: Length of high pulse when transmitting a "1" bit
++
++  allwinner,t1l-ns:
++    default: 294
++    description: Length of low pulse when transmitting a "1" bit
++
++  allwinner,treset-ns:
++    default: 300000
++    description: Minimum delay between transmission frames
++
++patternProperties:
++  "^multi-led@[0-9a-f]+$":
++    type: object
++    $ref: leds-class-multicolor.yaml#
++    unevaluatedProperties: false
++    properties:
++      reg:
++        minimum: 0
++        maximum: 1023
++        description: Index of the LED in the series (must be contiguous)
++
++    required:
++      - reg
++
++required:
++  - compatible
++  - reg
++  - interrupts
++  - clocks
++  - clock-names
++  - resets
++  - dmas
++  - dma-names
++
++additionalProperties: false
++
++examples:
++  - |
++    #include <dt-bindings/interrupt-controller/irq.h>
++    #include <dt-bindings/leds/common.h>
++
++    ledc: led-controller@2008000 {
++      compatible = "allwinner,sun20i-d1-ledc",
++                   "allwinner,sun50i-a100-ledc";
++      reg = <0x2008000 0x400>;
++      interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
++      clocks = <&ccu 12>, <&ccu 34>;
++      clock-names = "bus", "mod";
++      resets = <&ccu 12>;
++      dmas = <&dma 42>;
++      dma-names = "tx";
++      #address-cells = <1>;
++      #size-cells = <0>;
++
++      multi-led@0 {
++        reg = <0x0>;
++        color = <LED_COLOR_ID_RGB>;
++        function = LED_FUNCTION_INDICATOR;
++      };
++    };
++
++...
diff --git a/target/linux/d1/patches-6.1/0055-leds-sun50i-a100-New-driver-for-the-A100-LED-control.patch b/target/linux/d1/patches-6.1/0055-leds-sun50i-a100-New-driver-for-the-A100-LED-control.patch
new file mode 100644
index 00000000000000..4c2cab557a6a4c
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0055-leds-sun50i-a100-New-driver-for-the-A100-LED-control.patch
@@ -0,0 +1,620 @@
+From 352b296d30df06b880d2c7620910cd759dc2609d Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 26 Jun 2021 11:02:49 -0500
+Subject: [PATCH 055/117] leds: sun50i-a100: New driver for the A100 LED
+ controller
+
+Some Allwinner sunxi SoCs, starting with the A100, contain an LED
+controller designed to drive RGB LED pixels. Add a driver for it using
+the multicolor LED framework, and with LEDs defined in the device tree.
+
+Series-changes: 2
+ - Renamed from sunxi-ledc to sun50i-r329-ledc
+ - Added missing "static" to functions/globals as reported by 0day bot
+
+Series-changes: 3
+ - Added vendor prefix to timing/format properties
+ - Renamed "format" property to "pixel-format" for clarity
+ - Dropped "vled-supply" as it is unrelated to the controller hardware
+ - Changed "writesl" to "iowrite32_rep" so the driver builds on hppa
+
+Series-changes: 4
+ - Depend on LEDS_CLASS_MULTICOLOR
+
+Series-changes: 5
+ - Rename the driver R329 -> A100, since that is the actual original
+   implementation
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/leds/Kconfig            |   9 +
+ drivers/leds/Makefile           |   1 +
+ drivers/leds/leds-sun50i-a100.c | 554 ++++++++++++++++++++++++++++++++
+ 3 files changed, 564 insertions(+)
+ create mode 100644 drivers/leds/leds-sun50i-a100.c
+
+--- a/drivers/leds/Kconfig
++++ b/drivers/leds/Kconfig
+@@ -283,6 +283,15 @@ config LEDS_COBALT_RAQ
+ 	help
+ 	  This option enables support for the Cobalt Raq series LEDs.
+ 
++config LEDS_SUN50I_A100
++	tristate "LED support for Allwinner A100 RGB LED controller"
++	depends on LEDS_CLASS_MULTICOLOR && OF
++	depends on ARCH_SUNXI || COMPILE_TEST
++	help
++	  This option enables support for the RGB LED controller found
++	  in some Allwinner sunxi SoCs, includeing A100, R329, and D1.
++	  It uses a one-wire interface to control up to 1024 LEDs.
++
+ config LEDS_SUNFIRE
+ 	tristate "LED support for SunFire servers."
+ 	depends on LEDS_CLASS
+--- a/drivers/leds/Makefile
++++ b/drivers/leds/Makefile
+@@ -76,6 +76,7 @@ obj-$(CONFIG_LEDS_PWM)			+= leds-pwm.o
+ obj-$(CONFIG_LEDS_REGULATOR)		+= leds-regulator.o
+ obj-$(CONFIG_LEDS_S3C24XX)		+= leds-s3c24xx.o
+ obj-$(CONFIG_LEDS_SC27XX_BLTC)		+= leds-sc27xx-bltc.o
++obj-$(CONFIG_LEDS_SUN50I_A100)		+= leds-sun50i-a100.o
+ obj-$(CONFIG_LEDS_SUNFIRE)		+= leds-sunfire.o
+ obj-$(CONFIG_LEDS_SYSCON)		+= leds-syscon.o
+ obj-$(CONFIG_LEDS_TCA6507)		+= leds-tca6507.o
+--- /dev/null
++++ b/drivers/leds/leds-sun50i-a100.c
+@@ -0,0 +1,554 @@
++// SPDX-License-Identifier: GPL-2.0
++//
++// Copyright (c) 2021-2022 Samuel Holland <samuel@sholland.org>
++//
++// Partly based on drivers/leds/leds-turris-omnia.c, which is:
++//     Copyright (c) 2020 by Marek Behún <kabel@kernel.org>
++//
++
++#include <linux/clk.h>
++#include <linux/dma-mapping.h>
++#include <linux/dmaengine.h>
++#include <linux/interrupt.h>
++#include <linux/io.h>
++#include <linux/led-class-multicolor.h>
++#include <linux/leds.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/pm.h>
++#include <linux/reset.h>
++#include <linux/spinlock.h>
++
++#define LEDC_CTRL_REG			0x0000
++#define LEDC_CTRL_REG_DATA_LENGTH		(0x1fff << 16)
++#define LEDC_CTRL_REG_RGB_MODE			(0x7 << 6)
++#define LEDC_CTRL_REG_LEDC_EN			BIT(0)
++#define LEDC_T01_TIMING_CTRL_REG	0x0004
++#define LEDC_T01_TIMING_CTRL_REG_T1H		(0x3f << 21)
++#define LEDC_T01_TIMING_CTRL_REG_T1L		(0x1f << 16)
++#define LEDC_T01_TIMING_CTRL_REG_T0H		(0x1f << 6)
++#define LEDC_T01_TIMING_CTRL_REG_T0L		(0x3f << 0)
++#define LEDC_RESET_TIMING_CTRL_REG	0x000c
++#define LEDC_RESET_TIMING_CTRL_REG_LED_NUM	(0x3ff << 0)
++#define LEDC_DATA_REG			0x0014
++#define LEDC_DMA_CTRL_REG		0x0018
++#define LEDC_DMA_CTRL_REG_FIFO_TRIG_LEVEL	(0x1f << 0)
++#define LEDC_INT_CTRL_REG		0x001c
++#define LEDC_INT_CTRL_REG_GLOBAL_INT_EN		BIT(5)
++#define LEDC_INT_CTRL_REG_FIFO_CPUREQ_INT_EN	BIT(1)
++#define LEDC_INT_CTRL_REG_TRANS_FINISH_INT_EN	BIT(0)
++#define LEDC_INT_STS_REG		0x0020
++#define LEDC_INT_STS_REG_FIFO_CPUREQ_INT	BIT(1)
++#define LEDC_INT_STS_REG_TRANS_FINISH_INT	BIT(0)
++
++#define LEDC_FIFO_DEPTH			32
++#define LEDC_MAX_LEDS			1024
++
++#define LEDS_TO_BYTES(n)		((n) * sizeof(u32))
++
++struct sun50i_a100_ledc_led {
++	struct led_classdev_mc mc_cdev;
++	struct mc_subled subled_info[3];
++};
++
++#define to_ledc_led(mc) container_of(mc, struct sun50i_a100_ledc_led, mc_cdev)
++
++struct sun50i_a100_ledc_timing {
++	u32 t0h_ns;
++	u32 t0l_ns;
++	u32 t1h_ns;
++	u32 t1l_ns;
++	u32 treset_ns;
++};
++
++struct sun50i_a100_ledc {
++	struct device *dev;
++	void __iomem *base;
++	struct clk *bus_clk;
++	struct clk *mod_clk;
++	struct reset_control *reset;
++
++	u32 *buffer;
++	struct dma_chan *dma_chan;
++	dma_addr_t dma_handle;
++	int pio_length;
++	int pio_offset;
++
++	spinlock_t lock;
++	int next_length;
++	bool xfer_active;
++
++	u32 format;
++	struct sun50i_a100_ledc_timing timing;
++
++	int num_leds;
++	struct sun50i_a100_ledc_led leds[];
++};
++
++static int sun50i_a100_ledc_dma_xfer(struct sun50i_a100_ledc *priv, int length)
++{
++	struct dma_async_tx_descriptor *desc;
++	dma_cookie_t cookie;
++
++	desc = dmaengine_prep_slave_single(priv->dma_chan, priv->dma_handle,
++					   LEDS_TO_BYTES(length),
++					   DMA_MEM_TO_DEV, 0);
++	if (!desc)
++		return -ENOMEM;
++
++	cookie = dmaengine_submit(desc);
++	if (dma_submit_error(cookie))
++		return -EIO;
++
++	dma_async_issue_pending(priv->dma_chan);
++
++	return 0;
++}
++
++static void sun50i_a100_ledc_pio_xfer(struct sun50i_a100_ledc *priv, int length)
++{
++	u32 burst, offset, val;
++
++	if (length) {
++		/* New transfer (FIFO is empty). */
++		offset = 0;
++		burst  = min(length, LEDC_FIFO_DEPTH);
++	} else {
++		/* Existing transfer (FIFO is half-full). */
++		length = priv->pio_length;
++		offset = priv->pio_offset;
++		burst  = min(length, LEDC_FIFO_DEPTH / 2);
++	}
++
++	iowrite32_rep(priv->base + LEDC_DATA_REG, priv->buffer + offset, burst);
++
++	if (burst < length) {
++		priv->pio_length = length - burst;
++		priv->pio_offset = offset + burst;
++
++		if (!offset) {
++			val = readl(priv->base + LEDC_INT_CTRL_REG);
++			val |= LEDC_INT_CTRL_REG_FIFO_CPUREQ_INT_EN;
++			writel(val, priv->base + LEDC_INT_CTRL_REG);
++		}
++	} else {
++		/* Disable the request IRQ once all data is written. */
++		val = readl(priv->base + LEDC_INT_CTRL_REG);
++		val &= ~LEDC_INT_CTRL_REG_FIFO_CPUREQ_INT_EN;
++		writel(val, priv->base + LEDC_INT_CTRL_REG);
++	}
++}
++
++static void sun50i_a100_ledc_start_xfer(struct sun50i_a100_ledc *priv,
++					int length)
++{
++	u32 val;
++
++	dev_dbg(priv->dev, "Updating %d LEDs\n", length);
++
++	val = readl(priv->base + LEDC_CTRL_REG);
++	val &= ~LEDC_CTRL_REG_DATA_LENGTH;
++	val |= length << 16 | LEDC_CTRL_REG_LEDC_EN;
++	writel(val, priv->base + LEDC_CTRL_REG);
++
++	if (length > LEDC_FIFO_DEPTH) {
++		int ret = sun50i_a100_ledc_dma_xfer(priv, length);
++
++		if (!ret)
++			return;
++
++		dev_warn(priv->dev, "Failed to set up DMA: %d\n", ret);
++	}
++
++	sun50i_a100_ledc_pio_xfer(priv, length);
++}
++
++static irqreturn_t sun50i_a100_ledc_irq(int irq, void *dev_id)
++{
++	struct sun50i_a100_ledc *priv = dev_id;
++	u32 val;
++
++	val = readl(priv->base + LEDC_INT_STS_REG);
++
++	if (val & LEDC_INT_STS_REG_TRANS_FINISH_INT) {
++		int next_length;
++
++		/* Start the next transfer if needed. */
++		spin_lock(&priv->lock);
++		next_length = priv->next_length;
++		if (next_length)
++			priv->next_length = 0;
++		else
++			priv->xfer_active = false;
++		spin_unlock(&priv->lock);
++
++		if (next_length)
++			sun50i_a100_ledc_start_xfer(priv, next_length);
++	} else if (val & LEDC_INT_STS_REG_FIFO_CPUREQ_INT) {
++		/* Continue the current transfer. */
++		sun50i_a100_ledc_pio_xfer(priv, 0);
++	}
++
++	writel(val, priv->base + LEDC_INT_STS_REG);
++
++	return IRQ_HANDLED;
++}
++
++static void sun50i_a100_ledc_brightness_set(struct led_classdev *cdev,
++					    enum led_brightness brightness)
++{
++	struct sun50i_a100_ledc *priv = dev_get_drvdata(cdev->dev->parent);
++	struct led_classdev_mc *mc_cdev = lcdev_to_mccdev(cdev);
++	struct sun50i_a100_ledc_led *led = to_ledc_led(mc_cdev);
++	int addr = led - priv->leds;
++	unsigned long flags;
++	bool xfer_active;
++	int next_length;
++
++	led_mc_calc_color_components(mc_cdev, brightness);
++
++	priv->buffer[addr] = led->subled_info[0].brightness << 16 |
++			     led->subled_info[1].brightness <<  8 |
++			     led->subled_info[2].brightness;
++
++	dev_dbg(priv->dev, "LED %d -> #%06x\n", addr, priv->buffer[addr]);
++
++	spin_lock_irqsave(&priv->lock, flags);
++	next_length = max(priv->next_length, addr + 1);
++	xfer_active = priv->xfer_active;
++	if (xfer_active)
++		priv->next_length = next_length;
++	else
++		priv->xfer_active = true;
++	spin_unlock_irqrestore(&priv->lock, flags);
++
++	if (!xfer_active)
++		sun50i_a100_ledc_start_xfer(priv, next_length);
++}
++
++static const char *const sun50i_a100_ledc_formats[] = {
++	"rgb",
++	"rbg",
++	"grb",
++	"gbr",
++	"brg",
++	"bgr",
++};
++
++static int sun50i_a100_ledc_parse_format(const struct device_node *np,
++					 struct sun50i_a100_ledc *priv)
++{
++	const char *format = "grb";
++	u32 i;
++
++	of_property_read_string(np, "allwinner,pixel-format", &format);
++
++	for (i = 0; i < ARRAY_SIZE(sun50i_a100_ledc_formats); ++i) {
++		if (!strcmp(format, sun50i_a100_ledc_formats[i])) {
++			priv->format = i;
++			return 0;
++		}
++	}
++
++	dev_err(priv->dev, "Bad pixel format '%s'\n", format);
++
++	return -EINVAL;
++}
++
++static void sun50i_a100_ledc_set_format(struct sun50i_a100_ledc *priv)
++{
++	u32 val;
++
++	val = readl(priv->base + LEDC_CTRL_REG);
++	val &= ~LEDC_CTRL_REG_RGB_MODE;
++	val |= priv->format << 6;
++	writel(val, priv->base + LEDC_CTRL_REG);
++}
++
++static const struct sun50i_a100_ledc_timing sun50i_a100_ledc_default_timing = {
++	.t0h_ns = 336,
++	.t0l_ns = 840,
++	.t1h_ns = 882,
++	.t1l_ns = 294,
++	.treset_ns = 300000,
++};
++
++static int sun50i_a100_ledc_parse_timing(const struct device_node *np,
++					 struct sun50i_a100_ledc *priv)
++{
++	struct sun50i_a100_ledc_timing *timing = &priv->timing;
++
++	*timing = sun50i_a100_ledc_default_timing;
++
++	of_property_read_u32(np, "allwinner,t0h-ns", &timing->t0h_ns);
++	of_property_read_u32(np, "allwinner,t0l-ns", &timing->t0l_ns);
++	of_property_read_u32(np, "allwinner,t1h-ns", &timing->t1h_ns);
++	of_property_read_u32(np, "allwinner,t1l-ns", &timing->t1l_ns);
++	of_property_read_u32(np, "allwinner,treset-ns", &timing->treset_ns);
++
++	return 0;
++}
++
++static void sun50i_a100_ledc_set_timing(struct sun50i_a100_ledc *priv)
++{
++	const struct sun50i_a100_ledc_timing *timing = &priv->timing;
++	unsigned long mod_freq = clk_get_rate(priv->mod_clk);
++	u32 cycle_ns = NSEC_PER_SEC / mod_freq;
++	u32 val;
++
++	val = (timing->t1h_ns / cycle_ns) << 21 |
++	      (timing->t1l_ns / cycle_ns) << 16 |
++	      (timing->t0h_ns / cycle_ns) <<  6 |
++	      (timing->t0l_ns / cycle_ns);
++	writel(val, priv->base + LEDC_T01_TIMING_CTRL_REG);
++
++	val = (timing->treset_ns / cycle_ns) << 16 |
++	      (priv->num_leds - 1);
++	writel(val, priv->base + LEDC_RESET_TIMING_CTRL_REG);
++}
++
++static int sun50i_a100_ledc_resume(struct device *dev)
++{
++	struct sun50i_a100_ledc *priv = dev_get_drvdata(dev);
++	u32 val;
++	int ret;
++
++	ret = reset_control_deassert(priv->reset);
++	if (ret)
++		return ret;
++
++	ret = clk_prepare_enable(priv->bus_clk);
++	if (ret)
++		goto err_assert_reset;
++
++	ret = clk_prepare_enable(priv->mod_clk);
++	if (ret)
++		goto err_disable_bus_clk;
++
++	sun50i_a100_ledc_set_format(priv);
++	sun50i_a100_ledc_set_timing(priv);
++
++	/* The trigger level must be at least the burst length. */
++	val = readl(priv->base + LEDC_DMA_CTRL_REG);
++	val &= ~LEDC_DMA_CTRL_REG_FIFO_TRIG_LEVEL;
++	val |= LEDC_FIFO_DEPTH / 2;
++	writel(val, priv->base + LEDC_DMA_CTRL_REG);
++
++	val = LEDC_INT_CTRL_REG_GLOBAL_INT_EN |
++	      LEDC_INT_CTRL_REG_TRANS_FINISH_INT_EN;
++	writel(val, priv->base + LEDC_INT_CTRL_REG);
++
++	return 0;
++
++err_disable_bus_clk:
++	clk_disable_unprepare(priv->bus_clk);
++err_assert_reset:
++	reset_control_assert(priv->reset);
++
++	return ret;
++}
++
++static int sun50i_a100_ledc_suspend(struct device *dev)
++{
++	struct sun50i_a100_ledc *priv = dev_get_drvdata(dev);
++
++	clk_disable_unprepare(priv->mod_clk);
++	clk_disable_unprepare(priv->bus_clk);
++	reset_control_assert(priv->reset);
++
++	return 0;
++}
++
++static void sun50i_a100_ledc_dma_cleanup(void *data)
++{
++	struct sun50i_a100_ledc *priv = data;
++	struct device *dma_dev = dmaengine_get_dma_device(priv->dma_chan);
++
++	if (priv->buffer)
++		dma_free_wc(dma_dev, LEDS_TO_BYTES(priv->num_leds),
++			    priv->buffer, priv->dma_handle);
++	dma_release_channel(priv->dma_chan);
++}
++
++static int sun50i_a100_ledc_probe(struct platform_device *pdev)
++{
++	const struct device_node *np = pdev->dev.of_node;
++	struct dma_slave_config dma_cfg = {};
++	struct led_init_data init_data = {};
++	struct device *dev = &pdev->dev;
++	struct device_node *child;
++	struct sun50i_a100_ledc *priv;
++	struct resource *mem;
++	int count, irq, ret;
++
++	count = of_get_available_child_count(np);
++	if (!count)
++		return -ENODEV;
++	if (count > LEDC_MAX_LEDS) {
++		dev_err(dev, "Too many LEDs! (max is %d)\n", LEDC_MAX_LEDS);
++		return -EINVAL;
++	}
++
++	priv = devm_kzalloc(dev, struct_size(priv, leds, count), GFP_KERNEL);
++	if (!priv)
++		return -ENOMEM;
++
++	priv->dev = dev;
++	priv->num_leds = count;
++	spin_lock_init(&priv->lock);
++	dev_set_drvdata(dev, priv);
++
++	ret = sun50i_a100_ledc_parse_format(np, priv);
++	if (ret)
++		return ret;
++
++	ret = sun50i_a100_ledc_parse_timing(np, priv);
++	if (ret)
++		return ret;
++
++	priv->base = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
++	if (IS_ERR(priv->base))
++		return PTR_ERR(priv->base);
++
++	priv->bus_clk = devm_clk_get(dev, "bus");
++	if (IS_ERR(priv->bus_clk))
++		return PTR_ERR(priv->bus_clk);
++
++	priv->mod_clk = devm_clk_get(dev, "mod");
++	if (IS_ERR(priv->mod_clk))
++		return PTR_ERR(priv->mod_clk);
++
++	priv->reset = devm_reset_control_get_exclusive(dev, NULL);
++	if (IS_ERR(priv->reset))
++		return PTR_ERR(priv->reset);
++
++	priv->dma_chan = dma_request_chan(dev, "tx");
++	if (IS_ERR(priv->dma_chan))
++		return PTR_ERR(priv->dma_chan);
++
++	ret = devm_add_action_or_reset(dev, sun50i_a100_ledc_dma_cleanup, priv);
++	if (ret)
++		return ret;
++
++	dma_cfg.dst_addr	= mem->start + LEDC_DATA_REG;
++	dma_cfg.dst_addr_width	= DMA_SLAVE_BUSWIDTH_4_BYTES;
++	dma_cfg.dst_maxburst	= LEDC_FIFO_DEPTH / 2;
++	ret = dmaengine_slave_config(priv->dma_chan, &dma_cfg);
++	if (ret)
++		return ret;
++
++	priv->buffer = dma_alloc_wc(dmaengine_get_dma_device(priv->dma_chan),
++				    LEDS_TO_BYTES(priv->num_leds),
++				    &priv->dma_handle, GFP_KERNEL);
++	if (!priv->buffer)
++		return -ENOMEM;
++
++	irq = platform_get_irq(pdev, 0);
++	if (irq < 0)
++		return irq;
++
++	ret = devm_request_irq(dev, irq, sun50i_a100_ledc_irq,
++			       0, dev_name(dev), priv);
++	if (ret)
++		return ret;
++
++	ret = sun50i_a100_ledc_resume(dev);
++	if (ret)
++		return ret;
++
++	for_each_available_child_of_node(np, child) {
++		struct sun50i_a100_ledc_led *led;
++		struct led_classdev *cdev;
++		u32 addr, color;
++
++		ret = of_property_read_u32(child, "reg", &addr);
++		if (ret || addr >= count) {
++			dev_err(dev, "LED 'reg' values must be from 0 to %d\n",
++				priv->num_leds - 1);
++			ret = -EINVAL;
++			goto err_put_child;
++		}
++
++		ret = of_property_read_u32(child, "color", &color);
++		if (ret || color != LED_COLOR_ID_RGB) {
++			dev_err(dev, "LED 'color' must be LED_COLOR_ID_RGB\n");
++			ret = -EINVAL;
++			goto err_put_child;
++		}
++
++		led = &priv->leds[addr];
++
++		led->subled_info[0].color_index = LED_COLOR_ID_RED;
++		led->subled_info[0].channel = 0;
++		led->subled_info[1].color_index = LED_COLOR_ID_GREEN;
++		led->subled_info[1].channel = 1;
++		led->subled_info[2].color_index = LED_COLOR_ID_BLUE;
++		led->subled_info[2].channel = 2;
++
++		led->mc_cdev.num_colors = ARRAY_SIZE(led->subled_info);
++		led->mc_cdev.subled_info = led->subled_info;
++
++		cdev = &led->mc_cdev.led_cdev;
++		cdev->max_brightness = U8_MAX;
++		cdev->brightness_set = sun50i_a100_ledc_brightness_set;
++
++		init_data.fwnode = of_fwnode_handle(child);
++
++		ret = devm_led_classdev_multicolor_register_ext(dev,
++								&led->mc_cdev,
++								&init_data);
++		if (ret) {
++			dev_err(dev, "Failed to register LED %u: %d\n",
++				addr, ret);
++			goto err_put_child;
++		}
++	}
++
++	dev_info(dev, "Registered %d LEDs\n", priv->num_leds);
++
++	return 0;
++
++err_put_child:
++	of_node_put(child);
++	sun50i_a100_ledc_suspend(&pdev->dev);
++
++	return ret;
++}
++
++static int sun50i_a100_ledc_remove(struct platform_device *pdev)
++{
++	sun50i_a100_ledc_suspend(&pdev->dev);
++
++	return 0;
++}
++
++static void sun50i_a100_ledc_shutdown(struct platform_device *pdev)
++{
++	sun50i_a100_ledc_suspend(&pdev->dev);
++}
++
++static const struct of_device_id sun50i_a100_ledc_of_match[] = {
++	{ .compatible = "allwinner,sun50i-a100-ledc" },
++	{}
++};
++MODULE_DEVICE_TABLE(of, sun50i_a100_ledc_of_match);
++
++static SIMPLE_DEV_PM_OPS(sun50i_a100_ledc_pm,
++			 sun50i_a100_ledc_suspend, sun50i_a100_ledc_resume);
++
++static struct platform_driver sun50i_a100_ledc_driver = {
++	.probe		= sun50i_a100_ledc_probe,
++	.remove		= sun50i_a100_ledc_remove,
++	.shutdown	= sun50i_a100_ledc_shutdown,
++	.driver		= {
++		.name		= "sun50i-a100-ledc",
++		.of_match_table	= sun50i_a100_ledc_of_match,
++		.pm		= pm_ptr(&sun50i_a100_ledc_pm),
++	},
++};
++module_platform_driver(sun50i_a100_ledc_driver);
++
++MODULE_AUTHOR("Samuel Holland <samuel@sholland.org>");
++MODULE_DESCRIPTION("Allwinner A100 LED controller driver");
++MODULE_LICENSE("GPL");
diff --git a/target/linux/d1/patches-6.1/0056-arm64-dts-allwinner-a100-Add-LED-controller-node.patch b/target/linux/d1/patches-6.1/0056-arm64-dts-allwinner-a100-Add-LED-controller-node.patch
new file mode 100644
index 00000000000000..92fa2a31ee2891
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0056-arm64-dts-allwinner-a100-Add-LED-controller-node.patch
@@ -0,0 +1,38 @@
+From 0040f071ab45d3098b2aad7e28e07593a5740782 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Thu, 25 Aug 2022 23:19:40 -0500
+Subject: [PATCH 056/117] arm64: dts: allwinner: a100: Add LED controller node
+
+Allwinner A100 contains an LED controller. Add it to the devicetree.
+
+Commit-changes: 5
+ - New patch for v5
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
+@@ -273,6 +273,20 @@
+ 			#size-cells = <0>;
+ 		};
+ 
++		ledc: led-controller@5018000 {
++			compatible = "allwinner,sun50i-a100-ledc";
++			reg = <0x5018000 0x400>;
++			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_LEDC>, <&ccu CLK_LEDC>;
++			clock-names = "bus", "mod";
++			resets = <&ccu RST_BUS_LEDC>;
++			dmas = <&dma 42>;
++			dma-names = "tx";
++			status = "disabled";
++			#address-cells = <1>;
++			#size-cells = <0>;
++		};
++
+ 		ths: thermal-sensor@5070400 {
+ 			compatible = "allwinner,sun50i-a100-ths";
+ 			reg = <0x05070400 0x100>;
diff --git a/target/linux/d1/patches-6.1/0057-riscv-dts-allwinner-d1-Add-LED-controller-node.patch b/target/linux/d1/patches-6.1/0057-riscv-dts-allwinner-d1-Add-LED-controller-node.patch
new file mode 100644
index 00000000000000..f6a04113b1ba22
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0057-riscv-dts-allwinner-d1-Add-LED-controller-node.patch
@@ -0,0 +1,53 @@
+From 595f76548e1d51a76b1ab201293ef441233921cf Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Thu, 11 Aug 2022 23:02:43 -0500
+Subject: [PATCH 057/117] riscv: dts: allwinner: d1: Add LED controller node
+
+Allwinner D1 contains an LED controller. Add its devicetree node, as
+well as the pinmux used by the reference board design.
+
+Commit-changes: 5
+ - New patch for v5
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 21 ++++++++++++++++++++
+ 1 file changed, 21 insertions(+)
+
+--- a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
+@@ -116,6 +116,12 @@
+ 			};
+ 
+ 			/omit-if-no-ref/
++			ledc_pc0_pin: ledc-pc0-pin {
++				pins = "PC0";
++				function = "ledc";
++			};
++
++			/omit-if-no-ref/
+ 			mmc0_pins: mmc0-pins {
+ 				pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
+ 				function = "mmc0";
+@@ -178,6 +184,21 @@
+ 			#reset-cells = <1>;
+ 		};
+ 
++		ledc: led-controller@2008000 {
++			compatible = "allwinner,sun20i-d1-ledc",
++				     "allwinner,sun50i-a100-ledc";
++			reg = <0x2008000 0x400>;
++			interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_LEDC>, <&ccu CLK_LEDC>;
++			clock-names = "bus", "mod";
++			resets = <&ccu RST_BUS_LEDC>;
++			dmas = <&dma 42>;
++			dma-names = "tx";
++			status = "disabled";
++			#address-cells = <1>;
++			#size-cells = <0>;
++		};
++
+ 		lradc: keys@2009800 {
+ 			compatible = "allwinner,sun20i-d1-lradc",
+ 				     "allwinner,sun50i-r329-lradc";
diff --git a/target/linux/d1/patches-6.1/0058-riscv-dts-allwinner-d1-Add-RGB-LEDs-to-boards.patch b/target/linux/d1/patches-6.1/0058-riscv-dts-allwinner-d1-Add-RGB-LEDs-to-boards.patch
new file mode 100644
index 00000000000000..901cb0daf8caed
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0058-riscv-dts-allwinner-d1-Add-RGB-LEDs-to-boards.patch
@@ -0,0 +1,98 @@
+From e6eb041b2099ec3d07a4ec391a06e86d7697c9d1 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Thu, 11 Aug 2022 23:03:01 -0500
+Subject: [PATCH 058/117] riscv: dts: allwinner: d1: Add RGB LEDs to boards
+
+Some D1-based boards feature an onboard RGB LED. Enable them.
+
+Commit-changes: 5
+ - New patch for v5
+
+Series-version: 5
+
+Series-to: Pavel Machek <pavel@ucw.cz>
+Series-to: Chen-Yu Tsai <wens@csie.org>
+Series-to: Jernej Skrabec <jernej.skrabec@gmail.com>
+Series-to: linux-leds@vger.kernel.org
+Series-cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
+Series-cc: Rob Herring <robh+dt@kernel.org>
+Series-cc: devicetree@vger.kernel.org
+Series-cc: linux-arm-kernel@lists.infradead.org
+Series-cc: linux-kernel@vger.kernel.org
+Series-cc: linux-riscv@lists.infradead.org
+Series-cc: linux-sunxi@lists.linux.dev
+
+Cover-letter:
+leds: Allwinner A100 LED controller support
+This series adds bindings and a driver for the RGB LED controller found
+in some Allwinner SoCs, starting with A100. The hardware in the R329 and
+D1 SoCs appears to be identical.
+
+Patch 3 is included because the LED controller binding requires the DMA
+properties. That patch was sent previously[1], but never got merged.
+
+Patches 5-6 depend on the D1 devicetree series[2], but the rest of this
+series can be merged without them.
+
+This driver was tested on the D1 Nezha board.
+
+[1]: https://lore.kernel.org/linux-arm-kernel/20201110040553.1381-7-frank@allwinnertech.com/
+[2]: https://lore.kernel.org/linux-riscv/20220815050815.22340-1-samuel@sholland.org/
+END
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ .../boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts | 12 ++++++++++++
+ arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts   | 13 +++++++++++++
+ 2 files changed, 25 insertions(+)
+
+--- a/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts
++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts
+@@ -58,6 +58,18 @@
+ 	status = "okay";
+ };
+ 
++&ledc {
++	pinctrl-0 = <&ledc_pc0_pin>;
++	pinctrl-names = "default";
++	status = "okay";
++
++	multi-led@0 {
++		reg = <0x0>;
++		color = <LED_COLOR_ID_RGB>;
++		function = LED_FUNCTION_STATUS;
++	};
++};
++
+ &lradc {
+ 	status = "okay";
+ 
+--- a/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
+@@ -5,6 +5,7 @@
+ 
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/input/input.h>
++#include <dt-bindings/leds/common.h>
+ 
+ #include "sun20i-d1.dtsi"
+ #include "sun20i-d1-common-regulators.dtsi"
+@@ -90,6 +91,18 @@
+ 	};
+ };
+ 
++&ledc {
++	pinctrl-0 = <&ledc_pc0_pin>;
++	pinctrl-names = "default";
++	status = "okay";
++
++	multi-led@0 {
++		reg = <0x0>;
++		color = <LED_COLOR_ID_RGB>;
++		function = LED_FUNCTION_STATUS;
++	};
++};
++
+ &lradc {
+ 	status = "okay";
+ 
diff --git a/target/linux/d1/patches-6.1/0059-pwm-sun8i-v536-document-device-tree-bindings.patch b/target/linux/d1/patches-6.1/0059-pwm-sun8i-v536-document-device-tree-bindings.patch
new file mode 100644
index 00000000000000..4ec15bce0cc91e
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0059-pwm-sun8i-v536-document-device-tree-bindings.patch
@@ -0,0 +1,40 @@
+From effa2ef8717b0390e8fb0648e16df1b43610af53 Mon Sep 17 00:00:00 2001
+From: Ban Tao <fengzheng923@gmail.com>
+Date: Tue, 2 Mar 2021 20:40:23 +0800
+Subject: [PATCH 059/117] pwm: sun8i-v536: document device tree bindings
+
+This adds binding documentation for sun8i-v536 SoC PWM driver.
+
+Signed-off-by: Ban Tao <fengzheng923@gmail.com>
+---
+ .../bindings/pwm/pwm-sun8i-v536.txt           | 24 +++++++++++++++++++
+ 1 file changed, 24 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/pwm/pwm-sun8i-v536.txt
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/pwm/pwm-sun8i-v536.txt
+@@ -0,0 +1,24 @@
++Allwinner sun8i-v536 SoC PWM controller
++
++Required properties:
++ - compatible: should be "allwinner,<name>-pwm"
++   "allwinner,sun8i-v833-pwm"
++   "allwinner,sun8i-v536-pwm"
++   "allwinner,sun50i-r818-pwm"
++   "allwinner,sun50i-a133-pwm"
++   "allwinner,sun50i-r329-pwm"
++ - reg: physical base address and length of the controller's registers
++ - #pwm-cells: should be 3. See pwm.txt in this directory for a description of
++   the cells format.
++ - clocks: From common clock binding, handle to the parent clock.
++ - resets: From reset clock binding, handle to the parent clock.
++
++Example:
++
++	pwm: pwm@300a0000 {
++		compatible = "allwinner,sun50i-r818-pwm";
++		reg = <0x0300a000 0x3ff>;
++		clocks = <&ccu CLK_BUS_PWM>;
++		resets = <&ccu RST_BUS_PWM>;
++		#pwm-cells = <3>;
++	};
diff --git a/target/linux/d1/patches-6.1/0060-pwm-sunxi-Add-Allwinner-SoC-PWM-controller-driver.patch b/target/linux/d1/patches-6.1/0060-pwm-sunxi-Add-Allwinner-SoC-PWM-controller-driver.patch
new file mode 100644
index 00000000000000..8c5d290c49c23c
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0060-pwm-sunxi-Add-Allwinner-SoC-PWM-controller-driver.patch
@@ -0,0 +1,466 @@
+From 4919e67557eaebb9f155950e7cac547a507b59e5 Mon Sep 17 00:00:00 2001
+From: Ban Tao <fengzheng923@gmail.com>
+Date: Tue, 2 Mar 2021 20:37:37 +0800
+Subject: [PATCH 060/117] pwm: sunxi: Add Allwinner SoC PWM controller driver
+
+The Allwinner R818, A133, R329, V536 and V833 has a new PWM controller
+IP compared to the older Allwinner SoCs.
+
+Signed-off-by: Ban Tao <fengzheng923@gmail.com>
+---
+ MAINTAINERS                  |   6 +
+ drivers/pwm/Kconfig          |  11 +
+ drivers/pwm/Makefile         |   1 +
+ drivers/pwm/pwm-sun8i-v536.c | 401 +++++++++++++++++++++++++++++++++++
+ 4 files changed, 419 insertions(+)
+ create mode 100644 drivers/pwm/pwm-sun8i-v536.c
+
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -802,6 +802,12 @@ S:	Maintained
+ F:	Documentation/devicetree/bindings/hwlock/allwinner,sun6i-a31-hwspinlock.yaml
+ F:	drivers/hwspinlock/sun6i_hwspinlock.c
+ 
++ALLWINNER PWM DRIVER
++M:	Ban Tao <fengzheng923@gmail.com>
++L:	linux-pwm@vger.kernel.org
++S:	Maintained
++F:	drivers/pwm/pwm-sun8i-v536.c
++
+ ALLWINNER THERMAL DRIVER
+ M:	Vasily Khoruzhick <anarsoul@gmail.com>
+ M:	Yangtao Li <tiny.windzz@gmail.com>
+--- a/drivers/pwm/Kconfig
++++ b/drivers/pwm/Kconfig
+@@ -582,6 +582,17 @@ config PWM_SUN4I
+ 	  To compile this driver as a module, choose M here: the module
+ 	  will be called pwm-sun4i.
+ 
++config PWM_SUN8I_V536
++	tristate "Allwinner SUN8I_V536 PWM support"
++	depends on ARCH_SUNXI || COMPILE_TEST
++	depends on HAS_IOMEM && COMMON_CLK
++	help
++	  Enhanced PWM framework driver for Allwinner R818, A133, R329,
++	  V536 and V833 SoCs.
++
++	  To compile this driver as a module, choose M here: the module
++	  will be called pwm-sun8i-v536.
++
+ config PWM_SUNPLUS
+ 	tristate "Sunplus PWM support"
+ 	depends on ARCH_SUNPLUS || COMPILE_TEST
+--- a/drivers/pwm/Makefile
++++ b/drivers/pwm/Makefile
+@@ -54,6 +54,7 @@ obj-$(CONFIG_PWM_STM32)		+= pwm-stm32.o
+ obj-$(CONFIG_PWM_STM32_LP)	+= pwm-stm32-lp.o
+ obj-$(CONFIG_PWM_STMPE)		+= pwm-stmpe.o
+ obj-$(CONFIG_PWM_SUN4I)		+= pwm-sun4i.o
++obj-$(CONFIG_PWM_SUN8I_V536)	+= pwm-sun8i-v536.o
+ obj-$(CONFIG_PWM_SUNPLUS)	+= pwm-sunplus.o
+ obj-$(CONFIG_PWM_TEGRA)		+= pwm-tegra.o
+ obj-$(CONFIG_PWM_TIECAP)	+= pwm-tiecap.o
+--- /dev/null
++++ b/drivers/pwm/pwm-sun8i-v536.c
+@@ -0,0 +1,401 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * Driver for Allwinner sun8i-v536 Pulse Width Modulation Controller
++ *
++ * Copyright (C) 2021 Ban Tao <fengzheng923@gmail.com>
++ *
++ *
++ * Limitations:
++ * - When PWM is disabled, the output is driven to inactive.
++ * - If the register is reconfigured while PWM is running,
++ *   it does not complete the currently running period.
++ * - If the user input duty is beyond acceptible limits,
++ *   -EINVAL is returned.
++ */
++
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/module.h>
++#include <linux/of_device.h>
++#include <linux/pwm.h>
++#include <linux/clk.h>
++#include <linux/reset.h>
++
++#define PWM_GET_CLK_OFFSET(chan)	(0x20 + ((chan >> 1) * 0x4))
++#define PWM_CLK_APB_SCR			BIT(7)
++#define PWM_DIV_M			0
++#define PWM_DIV_M_MASK			GENMASK(3, PWM_DIV_M)
++
++#define PWM_CLK_REG			0x40
++#define PWM_CLK_GATING			BIT(0)
++
++#define PWM_ENABLE_REG			0x80
++#define PWM_EN				BIT(0)
++
++#define PWM_CTL_REG(chan)		(0x100 + 0x20 * chan)
++#define PWM_ACT_STA			BIT(8)
++#define PWM_PRESCAL_K			0
++#define PWM_PRESCAL_K_MASK		GENMASK(7, PWM_PRESCAL_K)
++
++#define PWM_PERIOD_REG(chan)		(0x104 + 0x20 * chan)
++#define PWM_ENTIRE_CYCLE			16
++#define PWM_ENTIRE_CYCLE_MASK		GENMASK(31, PWM_ENTIRE_CYCLE)
++#define PWM_ACT_CYCLE			0
++#define PWM_ACT_CYCLE_MASK		GENMASK(15, PWM_ACT_CYCLE)
++
++#define BIT_CH(bit, chan)		((bit) << (chan))
++#define SET_BITS(shift, mask, reg, val) \
++	    (((reg) & ~mask) | (val << (shift)))
++
++#define PWM_OSC_CLK			24000000
++#define PWM_PRESCALER_MAX		256
++#define PWM_CLK_DIV_M__MAX		9
++#define PWM_ENTIRE_CYCLE_MAX		65536
++
++struct sun8i_pwm_data {
++	unsigned int npwm;
++};
++
++struct sun8i_pwm_chip {
++	struct pwm_chip chip;
++	struct clk *clk;
++	struct reset_control *rst_clk;
++	void __iomem *base;
++	const struct sun8i_pwm_data *data;
++};
++
++static inline struct sun8i_pwm_chip *to_sun8i_pwm_chip(struct pwm_chip *chip)
++{
++	return container_of(chip, struct sun8i_pwm_chip, chip);
++}
++
++static inline u32 sun8i_pwm_readl(struct sun8i_pwm_chip *chip,
++				   unsigned long offset)
++{
++	return readl(chip->base + offset);
++}
++
++static inline void sun8i_pwm_writel(struct sun8i_pwm_chip *chip,
++				     u32 val, unsigned long offset)
++{
++	writel(val, chip->base + offset);
++}
++
++static void sun8i_pwm_get_state(struct pwm_chip *chip,
++				 struct pwm_device *pwm,
++				 struct pwm_state *state)
++{
++	struct sun8i_pwm_chip *pc = to_sun8i_pwm_chip(chip);
++	u64 clk_rate;
++	u32 tmp, entire_cycles, active_cycles;
++	unsigned int prescaler, div_m;
++
++	tmp = sun8i_pwm_readl(pc, PWM_GET_CLK_OFFSET(pwm->hwpwm));
++	if (tmp & PWM_CLK_APB_SCR)
++		clk_rate = clk_get_rate(pc->clk);
++	else
++		clk_rate = PWM_OSC_CLK;
++
++	tmp = sun8i_pwm_readl(pc, PWM_GET_CLK_OFFSET(pwm->hwpwm));
++	div_m = 0x1 << (tmp & PWM_DIV_M_MASK);
++
++	tmp = sun8i_pwm_readl(pc, PWM_CTL_REG(pwm->hwpwm));
++	prescaler = (tmp & PWM_PRESCAL_K_MASK) + 1;
++
++	tmp = sun8i_pwm_readl(pc, PWM_PERIOD_REG(pwm->hwpwm));
++	entire_cycles = (tmp >> PWM_ENTIRE_CYCLE) + 1;
++	active_cycles = (tmp & PWM_ACT_CYCLE_MASK);
++
++	/* (clk / div_m / prescaler) / entire_cycles = NSEC_PER_SEC / period_ns. */
++	state->period = DIV_ROUND_CLOSEST_ULL(entire_cycles * NSEC_PER_SEC,
++					      clk_rate) * div_m * prescaler;
++	/* duty_ns / period_ns = active_cycles / entire_cycles. */
++	state->duty_cycle = DIV_ROUND_CLOSEST_ULL(active_cycles * state->period,
++						  entire_cycles);
++
++	/* parsing polarity */
++	tmp = sun8i_pwm_readl(pc, PWM_CTL_REG(pwm->hwpwm));
++	if (tmp & PWM_ACT_STA)
++		state->polarity = PWM_POLARITY_NORMAL;
++	else
++		state->polarity = PWM_POLARITY_INVERSED;
++
++	/* parsing enabled */
++	tmp = sun8i_pwm_readl(pc, PWM_ENABLE_REG);
++	if (tmp & BIT_CH(PWM_EN, pwm->hwpwm))
++		state->enabled = true;
++	else
++		state->enabled = false;
++
++	dev_dbg(chip->dev, "duty_ns=%lld period_ns=%lld polarity=%s enabled=%s.\n",
++				state->duty_cycle, state->period,
++				state->polarity ? "inversed":"normal",
++				state->enabled ? "true":"false");
++}
++
++static void sun8i_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
++				    enum pwm_polarity polarity)
++{
++	struct sun8i_pwm_chip *pc = to_sun8i_pwm_chip(chip);
++	u32 temp;
++
++	temp = sun8i_pwm_readl(pc, PWM_CTL_REG(pwm->hwpwm));
++
++	if (polarity == PWM_POLARITY_NORMAL)
++		temp |= PWM_ACT_STA;
++	else
++		temp &= ~PWM_ACT_STA;
++
++	sun8i_pwm_writel(pc, temp, PWM_CTL_REG(pwm->hwpwm));
++}
++
++static int sun8i_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
++			      const struct pwm_state *state)
++{
++	struct sun8i_pwm_chip *pc = to_sun8i_pwm_chip(chip);
++	unsigned long long c;
++	unsigned long entire_cycles, active_cycles;
++	unsigned int div_m, prescaler;
++	u64 duty_ns = state->duty_cycle, period_ns = state->period;
++	u32 config;
++	int ret = 0;
++
++	if (period_ns > 334) {
++		/* if freq < 3M, then select 24M clock */
++		c = PWM_OSC_CLK;
++		config = sun8i_pwm_readl(pc, PWM_GET_CLK_OFFSET(pwm->hwpwm));
++		config &= ~PWM_CLK_APB_SCR;
++		sun8i_pwm_writel(pc, config, PWM_GET_CLK_OFFSET(pwm->hwpwm));
++	} else {
++		/* if freq > 3M, then select APB as clock */
++		c = clk_get_rate(pc->clk);
++		config = sun8i_pwm_readl(pc, PWM_GET_CLK_OFFSET(pwm->hwpwm));
++		config |= PWM_CLK_APB_SCR;
++		sun8i_pwm_writel(pc, config, PWM_GET_CLK_OFFSET(pwm->hwpwm));
++	}
++
++	dev_dbg(chip->dev, "duty_ns=%lld period_ns=%lld c =%llu.\n",
++			duty_ns, period_ns, c);
++
++	/*
++	 * (clk / div_m / prescaler) / entire_cycles = NSEC_PER_SEC / period_ns.
++	 * So, entire_cycles = clk * period_ns / NSEC_PER_SEC / div_m / prescaler.
++	 */
++	c = c * period_ns;
++	c = DIV_ROUND_CLOSEST_ULL(c, NSEC_PER_SEC);
++	for (div_m = 0; div_m < PWM_CLK_DIV_M__MAX; div_m++) {
++		for (prescaler = 0; prescaler < PWM_PRESCALER_MAX; prescaler++) {
++			/*
++			 * actual prescaler = prescaler(reg value) + 1.
++			 * actual div_m = 0x1 << div_m(reg value).
++			 */
++			entire_cycles = ((unsigned long)c >> div_m)/(prescaler + 1);
++			if (entire_cycles <= PWM_ENTIRE_CYCLE_MAX)
++				goto calc_end;
++		}
++	}
++	ret = -EINVAL;
++	goto exit;
++
++calc_end:
++	/*
++	 * duty_ns / period_ns = active_cycles / entire_cycles.
++	 * So, active_cycles = entire_cycles * duty_ns / period_ns.
++	 */
++	c = (unsigned long long)entire_cycles * duty_ns;
++	c = DIV_ROUND_CLOSEST_ULL(c, period_ns);
++	active_cycles = c;
++	if (entire_cycles == 0)
++		entire_cycles++;
++
++	/* config  clk div_m*/
++	config = sun8i_pwm_readl(pc, PWM_GET_CLK_OFFSET(pwm->hwpwm));
++	config = SET_BITS(PWM_DIV_M, PWM_DIV_M_MASK, config, div_m);
++	sun8i_pwm_writel(pc, config, PWM_GET_CLK_OFFSET(pwm->hwpwm));
++
++	/* config prescaler */
++	config = sun8i_pwm_readl(pc, PWM_CTL_REG(pwm->hwpwm));
++	config = SET_BITS(PWM_PRESCAL_K, PWM_PRESCAL_K_MASK, config, prescaler);
++	sun8i_pwm_writel(pc, config, PWM_CTL_REG(pwm->hwpwm));
++
++	/* config active and period cycles */
++	config = sun8i_pwm_readl(pc, PWM_PERIOD_REG(pwm->hwpwm));
++	config = SET_BITS(PWM_ACT_CYCLE, PWM_ACT_CYCLE_MASK, config, active_cycles);
++	config = SET_BITS(PWM_ENTIRE_CYCLE, PWM_ENTIRE_CYCLE_MASK,
++			config, (entire_cycles - 1));
++	sun8i_pwm_writel(pc, config, PWM_PERIOD_REG(pwm->hwpwm));
++
++	dev_dbg(chip->dev, "active_cycles=%lu entire_cycles=%lu prescaler=%u div_m=%u\n",
++			   active_cycles, entire_cycles, prescaler, div_m);
++
++exit:
++	return ret;
++}
++
++static void sun8i_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm,
++			     bool enable)
++{
++	struct sun8i_pwm_chip *pc = to_sun8i_pwm_chip(chip);
++	u32 clk, pwm_en;
++
++	clk = sun8i_pwm_readl(pc, PWM_CLK_REG);
++	pwm_en = sun8i_pwm_readl(pc, PWM_ENABLE_REG);
++
++	if (enable) {
++		clk |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
++		sun8i_pwm_writel(pc, clk, PWM_CLK_REG);
++
++		pwm_en |= BIT_CH(PWM_EN, pwm->hwpwm);
++		sun8i_pwm_writel(pc, pwm_en, PWM_ENABLE_REG);
++	} else {
++		pwm_en &= ~BIT_CH(PWM_EN, pwm->hwpwm);
++		sun8i_pwm_writel(pc, pwm_en, PWM_ENABLE_REG);
++
++		clk &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
++		sun8i_pwm_writel(pc, clk, PWM_CLK_REG);
++	}
++}
++
++static int sun8i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
++			      const struct pwm_state *state)
++{
++	struct pwm_state curstate;
++	int ret;
++
++	pwm_get_state(pwm, &curstate);
++
++	ret = sun8i_pwm_config(chip, pwm, state);
++
++	if (state->polarity != curstate.polarity)
++		sun8i_pwm_set_polarity(chip, pwm, state->polarity);
++
++	if (state->enabled != curstate.enabled)
++		sun8i_pwm_enable(chip, pwm, state->enabled);
++
++	return ret;
++}
++
++static const struct pwm_ops sun8i_pwm_ops = {
++	.get_state = sun8i_pwm_get_state,
++	.apply = sun8i_pwm_apply,
++	.owner = THIS_MODULE,
++};
++
++static const struct sun8i_pwm_data sun8i_pwm_data_c9 = {
++	.npwm = 9,
++};
++
++static const struct sun8i_pwm_data sun50i_pwm_data_c16 = {
++	.npwm = 16,
++};
++
++static const struct of_device_id sun8i_pwm_dt_ids[] = {
++	{
++		.compatible = "allwinner,sun8i-v536-pwm",
++		.data = &sun8i_pwm_data_c9,
++	}, {
++		.compatible = "allwinner,sun50i-r818-pwm",
++		.data = &sun50i_pwm_data_c16,
++	}, {
++		/* sentinel */
++	},
++};
++MODULE_DEVICE_TABLE(of, sun8i_pwm_dt_ids);
++
++static int sun8i_pwm_probe(struct platform_device *pdev)
++{
++	struct sun8i_pwm_chip *pc;
++	int ret;
++
++	pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
++	if (!pc)
++		return dev_err_probe(&pdev->dev, -ENOMEM,
++				     "memory allocation failed\n");
++
++	pc->data = of_device_get_match_data(&pdev->dev);
++	if (!pc->data)
++		return dev_err_probe(&pdev->dev, -ENODEV,
++				     "can't get match data\n");
++
++	pc->base = devm_platform_ioremap_resource(pdev, 0);
++	if (IS_ERR(pc->base))
++		return dev_err_probe(&pdev->dev, PTR_ERR(pc->base),
++				     "can't remap pwm resource\n");
++
++	pc->clk = devm_clk_get(&pdev->dev, NULL);
++	if (IS_ERR(pc->clk))
++		return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk),
++				     "get clock failed\n");
++
++	pc->rst_clk = devm_reset_control_get_exclusive(&pdev->dev, NULL);
++	if (IS_ERR(pc->rst_clk))
++		return dev_err_probe(&pdev->dev, PTR_ERR(pc->rst_clk),
++				     "get reset failed\n");
++
++	/* Deassert reset */
++	ret = reset_control_deassert(pc->rst_clk);
++	if (ret < 0)
++		return dev_err_probe(&pdev->dev, ret,
++				     "cannot deassert reset control\n");
++
++	ret = clk_prepare_enable(pc->clk);
++	if (ret) {
++		dev_err(&pdev->dev, "cannot prepare and enable clk %pe\n",
++			ERR_PTR(ret));
++		goto err_clk;
++	}
++
++	pc->chip.dev = &pdev->dev;
++	pc->chip.ops = &sun8i_pwm_ops;
++	pc->chip.npwm = pc->data->npwm;
++	pc->chip.of_xlate = of_pwm_xlate_with_flags;
++	pc->chip.base = -1;
++	pc->chip.of_pwm_n_cells = 3;
++
++	ret = pwmchip_add(&pc->chip);
++	if (ret < 0) {
++		dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
++		goto err_pwm_add;
++	}
++
++	platform_set_drvdata(pdev, pc);
++
++	return 0;
++
++err_pwm_add:
++	clk_disable_unprepare(pc->clk);
++err_clk:
++	reset_control_assert(pc->rst_clk);
++
++	return ret;
++}
++
++static int sun8i_pwm_remove(struct platform_device *pdev)
++{
++	struct sun8i_pwm_chip *pc = platform_get_drvdata(pdev);
++	int ret;
++
++	ret = pwmchip_remove(&pc->chip);
++	if (ret)
++		return ret;
++
++	clk_disable_unprepare(pc->clk);
++	reset_control_assert(pc->rst_clk);
++
++	return 0;
++}
++
++static struct platform_driver sun8i_pwm_driver = {
++	.driver = {
++		.name = "sun8i-pwm-v536",
++		.of_match_table = sun8i_pwm_dt_ids,
++	},
++	.probe = sun8i_pwm_probe,
++	.remove = sun8i_pwm_remove,
++};
++module_platform_driver(sun8i_pwm_driver);
++
++MODULE_ALIAS("platform:sun8i-v536-pwm");
++MODULE_AUTHOR("Ban Tao <fengzheng923@gmail.com>");
++MODULE_DESCRIPTION("Allwinner sun8i-v536 PWM driver");
++MODULE_LICENSE("GPL v2");
diff --git a/target/linux/d1/patches-6.1/0061-squash-pwm-sunxi-Add-Allwinner-SoC-PWM-controller-dr.patch b/target/linux/d1/patches-6.1/0061-squash-pwm-sunxi-Add-Allwinner-SoC-PWM-controller-dr.patch
new file mode 100644
index 00000000000000..0eac89797d298d
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0061-squash-pwm-sunxi-Add-Allwinner-SoC-PWM-controller-dr.patch
@@ -0,0 +1,43 @@
+From 2f452dd6047126c42a0ad32ef0f10145c6047d66 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 6 Jun 2021 11:05:20 -0500
+Subject: [PATCH 061/117] squash? pwm: sunxi: Add Allwinner SoC PWM controller
+ driver
+
+---
+ drivers/pwm/Kconfig          | 4 ++--
+ drivers/pwm/pwm-sun8i-v536.c | 6 +-----
+ 2 files changed, 3 insertions(+), 7 deletions(-)
+
+--- a/drivers/pwm/Kconfig
++++ b/drivers/pwm/Kconfig
+@@ -583,11 +583,11 @@ config PWM_SUN4I
+ 	  will be called pwm-sun4i.
+ 
+ config PWM_SUN8I_V536
+-	tristate "Allwinner SUN8I_V536 PWM support"
++	tristate "Allwinner SUN8I V536 enhanced PWM support"
+ 	depends on ARCH_SUNXI || COMPILE_TEST
+ 	depends on HAS_IOMEM && COMMON_CLK
+ 	help
+-	  Enhanced PWM framework driver for Allwinner R818, A133, R329,
++	  Enhanced PWM framework driver for Allwinner A133, D1, R329, R818,
+ 	  V536 and V833 SoCs.
+ 
+ 	  To compile this driver as a module, choose M here: the module
+--- a/drivers/pwm/pwm-sun8i-v536.c
++++ b/drivers/pwm/pwm-sun8i-v536.c
+@@ -373,12 +373,8 @@ err_clk:
+ static int sun8i_pwm_remove(struct platform_device *pdev)
+ {
+ 	struct sun8i_pwm_chip *pc = platform_get_drvdata(pdev);
+-	int ret;
+-
+-	ret = pwmchip_remove(&pc->chip);
+-	if (ret)
+-		return ret;
+ 
++	pwmchip_remove(&pc->chip);
+ 	clk_disable_unprepare(pc->clk);
+ 	reset_control_assert(pc->rst_clk);
+ 
diff --git a/target/linux/d1/patches-6.1/0062-pwm-sun8i-v536-Add-support-for-the-Allwinner-D1.patch b/target/linux/d1/patches-6.1/0062-pwm-sun8i-v536-Add-support-for-the-Allwinner-D1.patch
new file mode 100644
index 00000000000000..d9df6e668109dc
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0062-pwm-sun8i-v536-Add-support-for-the-Allwinner-D1.patch
@@ -0,0 +1,33 @@
+From 8bb576d8640fdf896650a4d4a1b2e60254d75eb2 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 6 Jun 2021 10:56:25 -0500
+Subject: [PATCH 062/117] pwm: sun8i-v536: Add support for the Allwinner D1
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/pwm/pwm-sun8i-v536.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+--- a/drivers/pwm/pwm-sun8i-v536.c
++++ b/drivers/pwm/pwm-sun8i-v536.c
+@@ -285,6 +285,10 @@ static const struct sun8i_pwm_data sun8i
+ 	.npwm = 9,
+ };
+ 
++static const struct sun8i_pwm_data sun20i_pwm_data_c8 = {
++	.npwm = 8,
++};
++
+ static const struct sun8i_pwm_data sun50i_pwm_data_c16 = {
+ 	.npwm = 16,
+ };
+@@ -294,6 +298,9 @@ static const struct of_device_id sun8i_p
+ 		.compatible = "allwinner,sun8i-v536-pwm",
+ 		.data = &sun8i_pwm_data_c9,
+ 	}, {
++		.compatible = "allwinner,sun20i-d1-pwm",
++		.data = &sun20i_pwm_data_c8,
++	}, {
+ 		.compatible = "allwinner,sun50i-r818-pwm",
+ 		.data = &sun50i_pwm_data_c16,
+ 	}, {
diff --git a/target/linux/d1/patches-6.1/0063-riscv-dts-allwinner-d1-Add-PWM-support.patch b/target/linux/d1/patches-6.1/0063-riscv-dts-allwinner-d1-Add-PWM-support.patch
new file mode 100644
index 00000000000000..f353c6f91b2fd7
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0063-riscv-dts-allwinner-d1-Add-PWM-support.patch
@@ -0,0 +1,61 @@
+From 2ee8994e4db3978261e6c644e897400c4df5edeb Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Thu, 11 Aug 2022 22:24:52 -0500
+Subject: [PATCH 063/117] riscv: dts: allwinner: d1: Add PWM support
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 35 ++++++++++++++++++++
+ 1 file changed, 35 insertions(+)
+
+--- a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
+@@ -155,6 +155,30 @@
+ 			};
+ 
+ 			/omit-if-no-ref/
++			pwm0_pd16_pin: pwm0-pd16-pin {
++				pins = "PD16";
++				function = "pwm0";
++			};
++
++			/omit-if-no-ref/
++			pwm2_pd18_pin: pwm2-pd18-pin {
++				pins = "PD18";
++				function = "pwm2";
++			};
++
++			/omit-if-no-ref/
++			pwm4_pd20_pin: pwm4-pd20-pin {
++				pins = "PD20";
++				function = "pwm4";
++			};
++
++			/omit-if-no-ref/
++			pwm7_pd22_pin: pwm7-pd22-pin {
++				pins = "PD22";
++				function = "pwm7";
++			};
++
++			/omit-if-no-ref/
+ 			uart0_pb8_pins: uart0-pb8-pins {
+ 				pins = "PB8", "PB9";
+ 				function = "uart0";
+@@ -173,6 +197,17 @@
+ 			};
+ 		};
+ 
++		pwm: pwm@2000c00 {
++			compatible = "allwinner,sun20i-d1-pwm";
++			reg = <0x2000c00 0x400>;
++			interrupts = <34 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_PWM>, <&osc24M>;
++			clock-names = "bus", "mod";
++			resets = <&ccu RST_BUS_PWM>;
++			status = "disabled";
++			#pwm-cells = <3>;
++		};
++
+ 		ccu: clock-controller@2001000 {
+ 			compatible = "allwinner,sun20i-d1-ccu";
+ 			reg = <0x2001000 0x1000>;
diff --git a/target/linux/d1/patches-6.1/0064-riscv-dts-allwinner-d1-Hook-up-PWM-controlled-CPU-vo.patch b/target/linux/d1/patches-6.1/0064-riscv-dts-allwinner-d1-Hook-up-PWM-controlled-CPU-vo.patch
new file mode 100644
index 00000000000000..ff61b07d932847
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0064-riscv-dts-allwinner-d1-Hook-up-PWM-controlled-CPU-vo.patch
@@ -0,0 +1,124 @@
+From 5479c8efb6ffbbc8b7fd1068337037faf9c20a36 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Thu, 11 Aug 2022 22:25:40 -0500
+Subject: [PATCH 064/117] riscv: dts: allwinner: d1: Hook up PWM-controlled CPU
+ voltage regulators
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ .../allwinner/sun20i-d1-clockworkpi-v3.14.dts | 19 +++++++++++--------
+ .../sun20i-d1-dongshan-nezha-stu.dts          | 19 +++++++++++--------
+ .../boot/dts/allwinner/sun20i-d1-nezha.dts    | 19 +++++++++++--------
+ 3 files changed, 33 insertions(+), 24 deletions(-)
+
+--- a/arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts
++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts
+@@ -48,16 +48,13 @@
+ 		};
+ 	};
+ 
+-	/*
+-	 * This regulator is PWM-controlled, but the PWM controller is not
+-	 * yet supported, so fix the regulator to its default voltage.
+-	 */
+ 	reg_vdd_cpu: vdd-cpu {
+-		compatible = "regulator-fixed";
++		compatible = "pwm-regulator";
++		pwms = <&pwm 0 50000 0>;
++		pwm-supply = <&reg_vcc>;
+ 		regulator-name = "vdd-cpu";
+-		regulator-min-microvolt = <1100000>;
+-		regulator-max-microvolt = <1100000>;
+-		vin-supply = <&reg_vcc>;
++		regulator-min-microvolt = <810000>;
++		regulator-max-microvolt = <1160000>;
+ 	};
+ 
+ 	wifi_pwrseq: wifi-pwrseq {
+@@ -254,6 +251,12 @@
+ 	};
+ };
+ 
++&pwm {
++	pinctrl-0 = <&pwm0_pd16_pin>;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-0 = <&uart0_pb8_pins>;
+ 	pinctrl-names = "default";
+--- a/arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dts
++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dts
+@@ -43,16 +43,13 @@
+ 		vin-supply = <&reg_vcc>;
+ 	};
+ 
+-	/*
+-	 * This regulator is PWM-controlled, but the PWM controller is not
+-	 * yet supported, so fix the regulator to its default voltage.
+-	 */
+ 	reg_vdd_cpu: vdd-cpu {
+-		compatible = "regulator-fixed";
++		compatible = "pwm-regulator";
++		pwms = <&pwm 0 50000 0>;
++		pwm-supply = <&reg_vcc>;
+ 		regulator-name = "vdd-cpu";
+-		regulator-min-microvolt = <1100000>;
+-		regulator-max-microvolt = <1100000>;
+-		vin-supply = <&reg_vcc>;
++		regulator-min-microvolt = <810000>;
++		regulator-max-microvolt = <1160000>;
+ 	};
+ };
+ 
+@@ -95,6 +92,12 @@
+ 	status = "okay";
+ };
+ 
++&pwm {
++	pinctrl-0 = <&pwm0_pd16_pin>;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-0 = <&uart0_pb8_pins>;
+ 	pinctrl-names = "default";
+--- a/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
+@@ -35,16 +35,13 @@
+ 		vin-supply = <&reg_vcc>;
+ 	};
+ 
+-	/*
+-	 * This regulator is PWM-controlled, but the PWM controller is not
+-	 * yet supported, so fix the regulator to its default voltage.
+-	 */
+ 	reg_vdd_cpu: vdd-cpu {
+-		compatible = "regulator-fixed";
++		compatible = "pwm-regulator";
++		pwms = <&pwm 0 50000 0>;
++		pwm-supply = <&reg_vcc>;
+ 		regulator-name = "vdd-cpu";
+-		regulator-min-microvolt = <1100000>;
+-		regulator-max-microvolt = <1100000>;
+-		vin-supply = <&reg_vcc>;
++		regulator-min-microvolt = <810000>;
++		regulator-max-microvolt = <1160000>;
+ 	};
+ 
+ 	wifi_pwrseq: wifi-pwrseq {
+@@ -155,6 +152,12 @@
+ 	status = "okay";
+ };
+ 
++&pwm {
++	pinctrl-0 = <&pwm0_pd16_pin>;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-0 = <&uart0_pb8_pins>;
+ 	pinctrl-names = "default";
diff --git a/target/linux/d1/patches-6.1/0065-riscv-dts-allwinner-mangopi-mq-pro-Add-PWM-LED.patch b/target/linux/d1/patches-6.1/0065-riscv-dts-allwinner-mangopi-mq-pro-Add-PWM-LED.patch
new file mode 100644
index 00000000000000..f184bd2136c839
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0065-riscv-dts-allwinner-mangopi-mq-pro-Add-PWM-LED.patch
@@ -0,0 +1,38 @@
+From 29360e65c326ea8bbac6e63b42aa91fb8f14d3bf Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Thu, 11 Aug 2022 22:57:13 -0500
+Subject: [PATCH 065/117] riscv: dts: allwinner: mangopi-mq-pro: Add PWM LED
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ .../boot/dts/allwinner/sun20i-d1-mangopi-mq-pro.dts  | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+--- a/arch/riscv/boot/dts/allwinner/sun20i-d1-mangopi-mq-pro.dts
++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-mangopi-mq-pro.dts
+@@ -4,6 +4,7 @@
+ /dts-v1/;
+ 
+ #include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/leds/common.h>
+ 
+ #include "sun20i-d1.dtsi"
+ #include "sun20i-d1-common-regulators.dtsi"
+@@ -22,6 +23,17 @@
+ 		stdout-path = "serial0:115200n8";
+ 	};
+ 
++	leds {
++		compatible = "pwm-leds";
++
++		led {
++			color = <LED_COLOR_ID_BLUE>;
++			function = LED_FUNCTION_STATUS;
++			max-brightness = <255>;
++			pwms = <&pwm 2 50000 0>;
++		};
++	};
++
+ 	reg_avdd2v8: avdd2v8 {
+ 		compatible = "regulator-fixed";
+ 		regulator-name = "avdd2v8";
diff --git a/target/linux/d1/patches-6.1/0066-ASoC-dt-bindings-sun4i-spdif-Require-resets-for-H6.patch b/target/linux/d1/patches-6.1/0066-ASoC-dt-bindings-sun4i-spdif-Require-resets-for-H6.patch
new file mode 100644
index 00000000000000..0d27224ac3efd6
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0066-ASoC-dt-bindings-sun4i-spdif-Require-resets-for-H6.patch
@@ -0,0 +1,24 @@
+From bccb19038038c7377275d74bb815f5f9363ba2e3 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 13 Nov 2021 10:08:41 -0600
+Subject: [PATCH 066/117] ASoC: dt-bindings: sun4i-spdif: Require resets for H6
+
+The H6 variant has a module reset, and it is used by the driver. So the
+resets property should be required in the binding for this variant.
+
+Fixes: b20453031472 ("dt-bindings: sound: sun4i-spdif: Add Allwinner H6 compatible")
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ .../devicetree/bindings/sound/allwinner,sun4i-a10-spdif.yaml     | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-spdif.yaml
++++ b/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-spdif.yaml
+@@ -61,6 +61,7 @@ allOf:
+             enum:
+               - allwinner,sun6i-a31-spdif
+               - allwinner,sun8i-h3-spdif
++              - allwinner,sun50i-h6-spdif
+ 
+     then:
+       required:
diff --git a/target/linux/d1/patches-6.1/0067-ASoC-dt-bindings-sun4i-spdif-Add-compatible-for-D1.patch b/target/linux/d1/patches-6.1/0067-ASoC-dt-bindings-sun4i-spdif-Add-compatible-for-D1.patch
new file mode 100644
index 00000000000000..5c7e21954f274b
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0067-ASoC-dt-bindings-sun4i-spdif-Add-compatible-for-D1.patch
@@ -0,0 +1,94 @@
+From 4e72722bfb7dec028e11278a924bb8bef3e10897 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 13 Nov 2021 10:48:24 -0600
+Subject: [PATCH 067/117] ASoC: dt-bindings: sun4i-spdif: Add compatible for D1
+
+D1 mostly keeps the existing register layout, but it separates the
+module clock into separate clocks for the RX block and the TX block.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ .../sound/allwinner,sun4i-a10-spdif.yaml      | 54 +++++++++++++++----
+ 1 file changed, 44 insertions(+), 10 deletions(-)
+
+--- a/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-spdif.yaml
++++ b/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-spdif.yaml
+@@ -18,10 +18,12 @@ properties:
+ 
+   compatible:
+     oneOf:
+-      - const: allwinner,sun4i-a10-spdif
+-      - const: allwinner,sun6i-a31-spdif
+-      - const: allwinner,sun8i-h3-spdif
+-      - const: allwinner,sun50i-h6-spdif
++      - enum:
++          - allwinner,sun4i-a10-spdif
++          - allwinner,sun6i-a31-spdif
++          - allwinner,sun8i-h3-spdif
++          - allwinner,sun20i-d1-spdif
++          - allwinner,sun50i-h6-spdif
+       - items:
+           - const: allwinner,sun8i-a83t-spdif
+           - const: allwinner,sun8i-h3-spdif
+@@ -36,14 +38,12 @@ properties:
+     maxItems: 1
+ 
+   clocks:
+-    items:
+-      - description: Bus Clock
+-      - description: Module Clock
++    minItems: 2
++    maxItems: 3
+ 
+   clock-names:
+-    items:
+-      - const: apb
+-      - const: spdif
++    minItems: 2
++    maxItems: 3
+ 
+   # Even though it only applies to subschemas under the conditionals,
+   # not listing them here will trigger a warning because of the
+@@ -59,8 +59,42 @@ allOf:
+         compatible:
+           contains:
+             enum:
++              - allwinner,sun20i-d1-spdif
++
++    then:
++      properties:
++        clocks:
++          items:
++            - description: Bus Clock
++            - description: RX Module Clock
++            - description: TX Module Clock
++
++        clock-names:
++          items:
++            - const: apb
++            - const: rx
++            - const: tx
++
++    else:
++      properties:
++        clocks:
++          items:
++            - description: Bus Clock
++            - description: Module Clock
++
++        clock-names:
++          items:
++            - const: apb
++            - const: spdif
++
++  - if:
++      properties:
++        compatible:
++          contains:
++            enum:
+               - allwinner,sun6i-a31-spdif
+               - allwinner,sun8i-h3-spdif
++              - allwinner,sun20i-d1-spdif
+               - allwinner,sun50i-h6-spdif
+ 
+     then:
diff --git a/target/linux/d1/patches-6.1/0068-ASoC-sun4i-spdif-Assert-reset-when-removing-the-devi.patch b/target/linux/d1/patches-6.1/0068-ASoC-sun4i-spdif-Assert-reset-when-removing-the-devi.patch
new file mode 100644
index 00000000000000..794fd8c1dbbfb4
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0068-ASoC-sun4i-spdif-Assert-reset-when-removing-the-devi.patch
@@ -0,0 +1,30 @@
+From 1d85b3609cf4239f7e971b839f1ab985413cd560 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 13 Nov 2021 11:12:14 -0600
+Subject: [PATCH 068/117] ASoC: sun4i-spdif: Assert reset when removing the
+ device
+
+This completes reversing the process done in the probe function.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ sound/soc/sunxi/sun4i-spdif.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/sound/soc/sunxi/sun4i-spdif.c
++++ b/sound/soc/sunxi/sun4i-spdif.c
+@@ -705,10 +705,14 @@ err_unregister:
+ 
+ static int sun4i_spdif_remove(struct platform_device *pdev)
+ {
++	struct sun4i_spdif_dev *host = dev_get_drvdata(&pdev->dev);
++
+ 	pm_runtime_disable(&pdev->dev);
+ 	if (!pm_runtime_status_suspended(&pdev->dev))
+ 		sun4i_spdif_runtime_suspend(&pdev->dev);
+ 
++	reset_control_assert(host->rst);
++
+ 	return 0;
+ }
+ 
diff --git a/target/linux/d1/patches-6.1/0069-ASoC-sun4i-spdif-Simplify-code-around-optional-reset.patch b/target/linux/d1/patches-6.1/0069-ASoC-sun4i-spdif-Simplify-code-around-optional-reset.patch
new file mode 100644
index 00000000000000..0cd39d0b1957e3
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0069-ASoC-sun4i-spdif-Simplify-code-around-optional-reset.patch
@@ -0,0 +1,78 @@
+From 0efd742482dbe4b17a441eab5c57231d65f9a852 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 13 Nov 2021 11:14:30 -0600
+Subject: [PATCH 069/117] ASoC: sun4i-spdif: Simplify code around optional
+ resets
+
+The driver does not need to care about which variants have a reset;
+the devicetree binding already enforces that the necessary resources are
+provided. Simplify the logic by always calling the optional getter,
+which will return NULL if no reset reference is found.
+
+Also clean up the error handling, which should not print a misleading
+error in the EPROBE_DEFER case.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ sound/soc/sunxi/sun4i-spdif.c | 22 ++++++----------------
+ 1 file changed, 6 insertions(+), 16 deletions(-)
+
+--- a/sound/soc/sunxi/sun4i-spdif.c
++++ b/sound/soc/sunxi/sun4i-spdif.c
+@@ -170,12 +170,10 @@
+  * struct sun4i_spdif_quirks - Differences between SoC variants.
+  *
+  * @reg_dac_txdata: TX FIFO offset for DMA config.
+- * @has_reset: SoC needs reset deasserted.
+  * @val_fctl_ftx: TX FIFO flush bitmask.
+  */
+ struct sun4i_spdif_quirks {
+ 	unsigned int reg_dac_txdata;
+-	bool has_reset;
+ 	unsigned int val_fctl_ftx;
+ };
+ 
+@@ -546,19 +544,16 @@ static const struct sun4i_spdif_quirks s
+ static const struct sun4i_spdif_quirks sun6i_a31_spdif_quirks = {
+ 	.reg_dac_txdata	= SUN4I_SPDIF_TXFIFO,
+ 	.val_fctl_ftx   = SUN4I_SPDIF_FCTL_FTX,
+-	.has_reset	= true,
+ };
+ 
+ static const struct sun4i_spdif_quirks sun8i_h3_spdif_quirks = {
+ 	.reg_dac_txdata	= SUN8I_SPDIF_TXFIFO,
+ 	.val_fctl_ftx   = SUN4I_SPDIF_FCTL_FTX,
+-	.has_reset	= true,
+ };
+ 
+ static const struct sun4i_spdif_quirks sun50i_h6_spdif_quirks = {
+ 	.reg_dac_txdata = SUN8I_SPDIF_TXFIFO,
+ 	.val_fctl_ftx   = SUN50I_H6_SPDIF_FCTL_FTX,
+-	.has_reset      = true,
+ };
+ 
+ static const struct of_device_id sun4i_spdif_of_match[] = {
+@@ -667,17 +662,12 @@ static int sun4i_spdif_probe(struct plat
+ 
+ 	platform_set_drvdata(pdev, host);
+ 
+-	if (quirks->has_reset) {
+-		host->rst = devm_reset_control_get_optional_exclusive(&pdev->dev,
+-								      NULL);
+-		if (PTR_ERR(host->rst) == -EPROBE_DEFER) {
+-			ret = -EPROBE_DEFER;
+-			dev_err(&pdev->dev, "Failed to get reset: %d\n", ret);
+-			return ret;
+-		}
+-		if (!IS_ERR(host->rst))
+-			reset_control_deassert(host->rst);
+-	}
++	host->rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
++	if (IS_ERR(host->rst))
++		return dev_err_probe(&pdev->dev, PTR_ERR(host->rst),
++				     "Failed to get reset\n");
++
++	reset_control_deassert(host->rst);
+ 
+ 	ret = devm_snd_soc_register_component(&pdev->dev,
+ 				&sun4i_spdif_component, &sun4i_spdif_dai, 1);
diff --git a/target/linux/d1/patches-6.1/0070-ASoC-sun4i-spdif-Add-support-for-separate-RX-TX-cloc.patch b/target/linux/d1/patches-6.1/0070-ASoC-sun4i-spdif-Add-support-for-separate-RX-TX-cloc.patch
new file mode 100644
index 00000000000000..99a198bd82ee91
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0070-ASoC-sun4i-spdif-Add-support-for-separate-RX-TX-cloc.patch
@@ -0,0 +1,116 @@
+From b42a9e0cf6b0ca78b4ef5310de967d515a3cca03 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 13 Jun 2021 23:53:16 -0500
+Subject: [PATCH 070/117] ASoC: sun4i-spdif: Add support for separate RX/TX
+ clocks
+
+On older variants of the hardware, the RX and TX blocks share a single
+module clock, named "spdif" in the DT binding. The D1 variant has
+separate RX and TX clocks, so the TX module clock is named "tx" in the
+binding. To support this, supply the clock name in the quirks structure.
+
+Since the driver supports only TX, only the TX clock name is needed.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ sound/soc/sunxi/sun4i-spdif.c | 24 +++++++++++++++---------
+ 1 file changed, 15 insertions(+), 9 deletions(-)
+
+--- a/sound/soc/sunxi/sun4i-spdif.c
++++ b/sound/soc/sunxi/sun4i-spdif.c
+@@ -169,18 +169,20 @@
+ /**
+  * struct sun4i_spdif_quirks - Differences between SoC variants.
+  *
++ * @tx_clk_name: firmware name for the TX clock reference.
+  * @reg_dac_txdata: TX FIFO offset for DMA config.
+  * @val_fctl_ftx: TX FIFO flush bitmask.
+  */
+ struct sun4i_spdif_quirks {
++	const char *tx_clk_name;
+ 	unsigned int reg_dac_txdata;
+ 	unsigned int val_fctl_ftx;
+ };
+ 
+ struct sun4i_spdif_dev {
+ 	struct platform_device *pdev;
+-	struct clk *spdif_clk;
+ 	struct clk *apb_clk;
++	struct clk *tx_clk;
+ 	struct reset_control *rst;
+ 	struct snd_soc_dai_driver cpu_dai_drv;
+ 	struct regmap *regmap;
+@@ -313,7 +315,7 @@ static int sun4i_spdif_hw_params(struct
+ 		return -EINVAL;
+ 	}
+ 
+-	ret = clk_set_rate(host->spdif_clk, mclk);
++	ret = clk_set_rate(host->tx_clk, mclk);
+ 	if (ret < 0) {
+ 		dev_err(&pdev->dev,
+ 			"Setting SPDIF clock rate for %d Hz failed!\n", mclk);
+@@ -537,21 +539,25 @@ static struct snd_soc_dai_driver sun4i_s
+ };
+ 
+ static const struct sun4i_spdif_quirks sun4i_a10_spdif_quirks = {
++	.tx_clk_name	= "spdif",
+ 	.reg_dac_txdata	= SUN4I_SPDIF_TXFIFO,
+ 	.val_fctl_ftx   = SUN4I_SPDIF_FCTL_FTX,
+ };
+ 
+ static const struct sun4i_spdif_quirks sun6i_a31_spdif_quirks = {
++	.tx_clk_name	= "spdif",
+ 	.reg_dac_txdata	= SUN4I_SPDIF_TXFIFO,
+ 	.val_fctl_ftx   = SUN4I_SPDIF_FCTL_FTX,
+ };
+ 
+ static const struct sun4i_spdif_quirks sun8i_h3_spdif_quirks = {
++	.tx_clk_name	= "spdif",
+ 	.reg_dac_txdata	= SUN8I_SPDIF_TXFIFO,
+ 	.val_fctl_ftx   = SUN4I_SPDIF_FCTL_FTX,
+ };
+ 
+ static const struct sun4i_spdif_quirks sun50i_h6_spdif_quirks = {
++	.tx_clk_name	= "spdif",
+ 	.reg_dac_txdata = SUN8I_SPDIF_TXFIFO,
+ 	.val_fctl_ftx   = SUN50I_H6_SPDIF_FCTL_FTX,
+ };
+@@ -586,7 +592,7 @@ static int sun4i_spdif_runtime_suspend(s
+ {
+ 	struct sun4i_spdif_dev *host  = dev_get_drvdata(dev);
+ 
+-	clk_disable_unprepare(host->spdif_clk);
++	clk_disable_unprepare(host->tx_clk);
+ 	clk_disable_unprepare(host->apb_clk);
+ 
+ 	return 0;
+@@ -597,12 +603,12 @@ static int sun4i_spdif_runtime_resume(st
+ 	struct sun4i_spdif_dev *host  = dev_get_drvdata(dev);
+ 	int ret;
+ 
+-	ret = clk_prepare_enable(host->spdif_clk);
++	ret = clk_prepare_enable(host->tx_clk);
+ 	if (ret)
+ 		return ret;
+ 	ret = clk_prepare_enable(host->apb_clk);
+ 	if (ret)
+-		clk_disable_unprepare(host->spdif_clk);
++		clk_disable_unprepare(host->tx_clk);
+ 
+ 	return ret;
+ }
+@@ -650,10 +656,10 @@ static int sun4i_spdif_probe(struct plat
+ 		return PTR_ERR(host->apb_clk);
+ 	}
+ 
+-	host->spdif_clk = devm_clk_get(&pdev->dev, "spdif");
+-	if (IS_ERR(host->spdif_clk)) {
+-		dev_err(&pdev->dev, "failed to get a spdif clock.\n");
+-		return PTR_ERR(host->spdif_clk);
++	host->tx_clk = devm_clk_get(&pdev->dev, quirks->tx_clk_name);
++	if (IS_ERR(host->tx_clk)) {
++		dev_err(&pdev->dev, "failed to get TX module clock.\n");
++		return PTR_ERR(host->tx_clk);
+ 	}
+ 
+ 	host->dma_params_tx.addr = res->start + quirks->reg_dac_txdata;
diff --git a/target/linux/d1/patches-6.1/0071-ASoC-sun4i-spdif-Add-support-for-the-D1-variant.patch b/target/linux/d1/patches-6.1/0071-ASoC-sun4i-spdif-Add-support-for-the-D1-variant.patch
new file mode 100644
index 00000000000000..022e319ab0b29a
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0071-ASoC-sun4i-spdif-Add-support-for-the-D1-variant.patch
@@ -0,0 +1,40 @@
+From af01261bf4e334cad158519291e5bc38765c955f Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 13 Jun 2021 23:53:26 -0500
+Subject: [PATCH 071/117] ASoC: sun4i-spdif: Add support for the D1 variant
+
+The D1 variant is similar to the H6 variant, except for its clock setup.
+The clock tree changes impact some register fields on the RX side, but
+those are not yet relevant, because RX is not supported by this driver.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ sound/soc/sunxi/sun4i-spdif.c | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+--- a/sound/soc/sunxi/sun4i-spdif.c
++++ b/sound/soc/sunxi/sun4i-spdif.c
+@@ -556,6 +556,12 @@ static const struct sun4i_spdif_quirks s
+ 	.val_fctl_ftx   = SUN4I_SPDIF_FCTL_FTX,
+ };
+ 
++static const struct sun4i_spdif_quirks sun20i_d1_spdif_quirks = {
++	.tx_clk_name	= "tx",
++	.reg_dac_txdata = SUN8I_SPDIF_TXFIFO,
++	.val_fctl_ftx   = SUN50I_H6_SPDIF_FCTL_FTX,
++};
++
+ static const struct sun4i_spdif_quirks sun50i_h6_spdif_quirks = {
+ 	.tx_clk_name	= "spdif",
+ 	.reg_dac_txdata = SUN8I_SPDIF_TXFIFO,
+@@ -576,6 +582,10 @@ static const struct of_device_id sun4i_s
+ 		.data = &sun8i_h3_spdif_quirks,
+ 	},
+ 	{
++		.compatible = "allwinner,sun20i-d1-spdif",
++		.data = &sun20i_d1_spdif_quirks,
++	},
++	{
+ 		.compatible = "allwinner,sun50i-h6-spdif",
+ 		.data = &sun50i_h6_spdif_quirks,
+ 	},
diff --git a/target/linux/d1/patches-6.1/0072-riscv-dts-allwinner-d1-Add-SPDIF-support.patch b/target/linux/d1/patches-6.1/0072-riscv-dts-allwinner-d1-Add-SPDIF-support.patch
new file mode 100644
index 00000000000000..72335cab404326
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0072-riscv-dts-allwinner-d1-Add-SPDIF-support.patch
@@ -0,0 +1,35 @@
+From 36153e325aa912268a5a5d4574dc7092e67c8008 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Wed, 17 Aug 2022 01:54:46 -0500
+Subject: [PATCH 072/117] riscv: dts: allwinner: d1: Add SPDIF support
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
+
+--- a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
+@@ -333,6 +333,22 @@
+ 			#sound-dai-cells = <0>;
+ 		};
+ 
++		// TODO: add receive functionality
++		spdif: spdif@2036000 {
++			compatible = "allwinner,sun20i-d1-spdif";
++			reg = <0x2036000 0x400>;
++			interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_SPDIF>,
++				 <&ccu CLK_SPDIF_RX>,
++				 <&ccu CLK_SPDIF_TX>;
++			clock-names = "apb", "rx", "tx";
++			resets = <&ccu RST_BUS_SPDIF>;
++			dmas = <&dma 2>, <&dma 2>;
++			dma-names = "rx", "tx";
++			status = "disabled";
++			#sound-dai-cells = <0>;
++		};
++
+ 		timer: timer@2050000 {
+ 			compatible = "allwinner,sun20i-d1-timer",
+ 				     "allwinner,sun8i-a23-timer";
diff --git a/target/linux/d1/patches-6.1/0073-ASoC-sun4i-spdif-Add-support-for-separate-resets.patch b/target/linux/d1/patches-6.1/0073-ASoC-sun4i-spdif-Add-support-for-separate-resets.patch
new file mode 100644
index 00000000000000..37ff3e2a9a07dc
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0073-ASoC-sun4i-spdif-Add-support-for-separate-resets.patch
@@ -0,0 +1,34 @@
+From c2b3f2c723e1b558afe5661bb91669e3b68154f7 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 13 Jun 2021 23:52:47 -0500
+Subject: [PATCH 073/117] ASoC: sun4i-spdif: Add support for separate resets
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ sound/soc/sunxi/sun4i-spdif.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+--- a/sound/soc/sunxi/sun4i-spdif.c
++++ b/sound/soc/sunxi/sun4i-spdif.c
+@@ -28,10 +28,11 @@
+ #include <sound/soc.h>
+ 
+ #define	SUN4I_SPDIF_CTL		(0x00)
++	#define SUN4I_SPDIF_CTL_RST_RX			BIT(12)
+ 	#define SUN4I_SPDIF_CTL_MCLKDIV(v)		((v) << 4) /* v even */
+ 	#define SUN4I_SPDIF_CTL_MCLKOUTEN		BIT(2)
+ 	#define SUN4I_SPDIF_CTL_GEN			BIT(1)
+-	#define SUN4I_SPDIF_CTL_RESET			BIT(0)
++	#define SUN4I_SPDIF_CTL_RST_TX			BIT(0)
+ 
+ #define SUN4I_SPDIF_TXCFG	(0x04)
+ 	#define SUN4I_SPDIF_TXCFG_SINGLEMOD		BIT(31)
+@@ -196,7 +197,7 @@ static void sun4i_spdif_configure(struct
+ 	const struct sun4i_spdif_quirks *quirks = host->quirks;
+ 
+ 	/* soft reset SPDIF */
+-	regmap_write(host->regmap, SUN4I_SPDIF_CTL, SUN4I_SPDIF_CTL_RESET);
++	regmap_write(host->regmap, SUN4I_SPDIF_CTL, SUN4I_SPDIF_CTL_RST_TX);
+ 
+ 	/* flush TX FIFO */
+ 	regmap_update_bits(host->regmap, SUN4I_SPDIF_FCTL,
diff --git a/target/linux/d1/patches-6.1/0074-dt-bindings-spi-sun6i-Add-R329-variant.patch b/target/linux/d1/patches-6.1/0074-dt-bindings-spi-sun6i-Add-R329-variant.patch
new file mode 100644
index 00000000000000..2301fad1cd6402
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0074-dt-bindings-spi-sun6i-Add-R329-variant.patch
@@ -0,0 +1,34 @@
+From e8e8a9490b2d4acc8670256dd3ba7d2a77346c4d Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Thu, 11 Aug 2022 22:23:05 -0500
+Subject: [PATCH 074/117] dt-bindings: spi: sun6i: Add R329 variant
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ .../devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml  | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml
++++ b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml
+@@ -21,6 +21,7 @@ properties:
+     oneOf:
+       - const: allwinner,sun6i-a31-spi
+       - const: allwinner,sun8i-h3-spi
++      - const: allwinner,sun50i-r329-spi
+       - items:
+           - enum:
+               - allwinner,sun8i-r40-spi
+@@ -28,6 +29,13 @@ properties:
+               - allwinner,sun50i-h616-spi
+               - allwinner,suniv-f1c100s-spi
+           - const: allwinner,sun8i-h3-spi
++      - items:
++          - const: allwinner,sun20i-d1-spi
++          - const: allwinner,sun50i-r329-spi
++      - items:
++          - const: allwinner,sun20i-d1-spi-dbi
++          - const: allwinner,sun50i-r329-spi-dbi
++          - const: allwinner,sun50i-r329-spi
+ 
+   reg:
+     maxItems: 1
diff --git a/target/linux/d1/patches-6.1/0075-spi-spi-sun6i-Use-a-struct-for-quirks.patch b/target/linux/d1/patches-6.1/0075-spi-spi-sun6i-Use-a-struct-for-quirks.patch
new file mode 100644
index 00000000000000..b13b7accf74a21
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0075-spi-spi-sun6i-Use-a-struct-for-quirks.patch
@@ -0,0 +1,109 @@
+From dbc9e83cefe51d19877a4a7349ebbeafa31c0e06 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Fri, 16 Jul 2021 21:33:16 -0500
+Subject: [PATCH 075/117] spi: spi-sun6i: Use a struct for quirks
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/spi/spi-sun6i.c | 32 ++++++++++++++++++++++----------
+ 1 file changed, 22 insertions(+), 10 deletions(-)
+
+--- a/drivers/spi/spi-sun6i.c
++++ b/drivers/spi/spi-sun6i.c
+@@ -85,7 +85,12 @@
+ #define SUN6I_TXDATA_REG		0x200
+ #define SUN6I_RXDATA_REG		0x300
+ 
++struct sun6i_spi_quirks {
++	unsigned long		fifo_depth;
++};
++
+ struct sun6i_spi {
++	const struct sun6i_spi_quirks *quirks;
+ 	struct spi_master	*master;
+ 	void __iomem		*base_addr;
+ 	dma_addr_t		dma_addr_rx;
+@@ -100,7 +105,6 @@ struct sun6i_spi {
+ 	const u8		*tx_buf;
+ 	u8			*rx_buf;
+ 	int			len;
+-	unsigned long		fifo_depth;
+ };
+ 
+ static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg)
+@@ -157,7 +161,7 @@ static inline void sun6i_spi_fill_fifo(s
+ 	u8 byte;
+ 
+ 	/* See how much data we can fit */
+-	cnt = sspi->fifo_depth - sun6i_spi_get_tx_fifo_count(sspi);
++	cnt = sspi->quirks->fifo_depth - sun6i_spi_get_tx_fifo_count(sspi);
+ 
+ 	len = min((int)cnt, sspi->len);
+ 
+@@ -300,14 +304,14 @@ static int sun6i_spi_transfer_one(struct
+ 		 * the hardcoded value used in old generation of Allwinner
+ 		 * SPI controller. (See spi-sun4i.c)
+ 		 */
+-		trig_level = sspi->fifo_depth / 4 * 3;
++		trig_level = sspi->quirks->fifo_depth / 4 * 3;
+ 	} else {
+ 		/*
+ 		 * Setup FIFO DMA request trigger level
+ 		 * We choose 1/2 of the full fifo depth, that value will
+ 		 * be used as DMA burst length.
+ 		 */
+-		trig_level = sspi->fifo_depth / 2;
++		trig_level = sspi->quirks->fifo_depth / 2;
+ 
+ 		if (tfr->tx_buf)
+ 			reg |= SUN6I_FIFO_CTL_TF_DRQ_EN;
+@@ -421,9 +425,9 @@ static int sun6i_spi_transfer_one(struct
+ 	reg = SUN6I_INT_CTL_TC;
+ 
+ 	if (!use_dma) {
+-		if (rx_len > sspi->fifo_depth)
++		if (rx_len > sspi->quirks->fifo_depth)
+ 			reg |= SUN6I_INT_CTL_RF_RDY;
+-		if (tx_len > sspi->fifo_depth)
++		if (tx_len > sspi->quirks->fifo_depth)
+ 			reg |= SUN6I_INT_CTL_TF_ERQ;
+ 	}
+ 
+@@ -569,7 +573,7 @@ static bool sun6i_spi_can_dma(struct spi
+ 	 * the fifo length we can just fill the fifo and wait for a single
+ 	 * irq, so don't bother setting up dma
+ 	 */
+-	return xfer->len > sspi->fifo_depth;
++	return xfer->len > sspi->quirks->fifo_depth;
+ }
+ 
+ static int sun6i_spi_probe(struct platform_device *pdev)
+@@ -608,7 +612,7 @@ static int sun6i_spi_probe(struct platfo
+ 	}
+ 
+ 	sspi->master = master;
+-	sspi->fifo_depth = (unsigned long)of_device_get_match_data(&pdev->dev);
++	sspi->quirks = of_device_get_match_data(&pdev->dev);
+ 
+ 	master->max_speed_hz = 100 * 1000 * 1000;
+ 	master->min_speed_hz = 3 * 1000;
+@@ -723,9 +727,17 @@ static int sun6i_spi_remove(struct platf
+ 	return 0;
+ }
+ 
++static const struct sun6i_spi_quirks sun6i_a31_spi_quirks = {
++	.fifo_depth		= SUN6I_FIFO_DEPTH,
++};
++
++static const struct sun6i_spi_quirks sun8i_h3_spi_quirks = {
++	.fifo_depth		= SUN8I_FIFO_DEPTH,
++};
++
+ static const struct of_device_id sun6i_spi_match[] = {
+-	{ .compatible = "allwinner,sun6i-a31-spi", .data = (void *)SUN6I_FIFO_DEPTH },
+-	{ .compatible = "allwinner,sun8i-h3-spi",  .data = (void *)SUN8I_FIFO_DEPTH },
++	{ .compatible = "allwinner,sun6i-a31-spi", .data = &sun6i_a31_spi_quirks },
++	{ .compatible = "allwinner,sun8i-h3-spi", .data = &sun8i_h3_spi_quirks },
+ 	{}
+ };
+ MODULE_DEVICE_TABLE(of, sun6i_spi_match);
diff --git a/target/linux/d1/patches-6.1/0076-spi-spi-sun6i-Add-Allwinner-R329-support.patch b/target/linux/d1/patches-6.1/0076-spi-spi-sun6i-Add-Allwinner-R329-support.patch
new file mode 100644
index 00000000000000..04e1c17f6695b4
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0076-spi-spi-sun6i-Add-Allwinner-R329-support.patch
@@ -0,0 +1,146 @@
+From ec8dfb455da3822451129257ab21e2f0d03a6ae3 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Fri, 16 Jul 2021 21:46:31 -0500
+Subject: [PATCH 076/117] spi: spi-sun6i: Add Allwinner R329 support
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/spi/spi-sun6i.c | 78 ++++++++++++++++++++++++++---------------
+ 1 file changed, 49 insertions(+), 29 deletions(-)
+
+--- a/drivers/spi/spi-sun6i.c
++++ b/drivers/spi/spi-sun6i.c
+@@ -30,6 +30,7 @@
+ #define SUN6I_GBL_CTL_REG		0x04
+ #define SUN6I_GBL_CTL_BUS_ENABLE		BIT(0)
+ #define SUN6I_GBL_CTL_MASTER			BIT(1)
++#define SUN6I_GBL_CTL_SAMPLE_MODE		BIT(2)
+ #define SUN6I_GBL_CTL_TP			BIT(7)
+ #define SUN6I_GBL_CTL_RST			BIT(31)
+ 
+@@ -87,6 +88,8 @@
+ 
+ struct sun6i_spi_quirks {
+ 	unsigned long		fifo_depth;
++	bool			has_divider : 1;
++	bool			has_new_sample_mode : 1;
+ };
+ 
+ struct sun6i_spi {
+@@ -362,38 +365,44 @@ static int sun6i_spi_transfer_one(struct
+ 	sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
+ 
+ 	/* Ensure that we have a parent clock fast enough */
+-	mclk_rate = clk_get_rate(sspi->mclk);
+-	if (mclk_rate < (2 * tfr->speed_hz)) {
+-		clk_set_rate(sspi->mclk, 2 * tfr->speed_hz);
++	if (sspi->quirks->has_divider) {
+ 		mclk_rate = clk_get_rate(sspi->mclk);
+-	}
++		if (mclk_rate < (2 * tfr->speed_hz)) {
++			clk_set_rate(sspi->mclk, 2 * tfr->speed_hz);
++			mclk_rate = clk_get_rate(sspi->mclk);
++		}
+ 
+-	/*
+-	 * Setup clock divider.
+-	 *
+-	 * We have two choices there. Either we can use the clock
+-	 * divide rate 1, which is calculated thanks to this formula:
+-	 * SPI_CLK = MOD_CLK / (2 ^ cdr)
+-	 * Or we can use CDR2, which is calculated with the formula:
+-	 * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
+-	 * Wether we use the former or the latter is set through the
+-	 * DRS bit.
+-	 *
+-	 * First try CDR2, and if we can't reach the expected
+-	 * frequency, fall back to CDR1.
+-	 */
+-	div_cdr1 = DIV_ROUND_UP(mclk_rate, tfr->speed_hz);
+-	div_cdr2 = DIV_ROUND_UP(div_cdr1, 2);
+-	if (div_cdr2 <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) {
+-		reg = SUN6I_CLK_CTL_CDR2(div_cdr2 - 1) | SUN6I_CLK_CTL_DRS;
+-		tfr->effective_speed_hz = mclk_rate / (2 * div_cdr2);
++		/*
++		 * Setup clock divider.
++		 *
++		 * We have two choices there. Either we can use the clock
++		 * divide rate 1, which is calculated thanks to this formula:
++		 * SPI_CLK = MOD_CLK / (2 ^ cdr)
++		 * Or we can use CDR2, which is calculated with the formula:
++		 * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
++		 * Wether we use the former or the latter is set through the
++		 * DRS bit.
++		 *
++		 * First try CDR2, and if we can't reach the expected
++		 * frequency, fall back to CDR1.
++		 */
++		div_cdr1 = DIV_ROUND_UP(mclk_rate, tfr->speed_hz);
++		div_cdr2 = DIV_ROUND_UP(div_cdr1, 2);
++		if (div_cdr2 <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) {
++			reg = SUN6I_CLK_CTL_CDR2(div_cdr2 - 1) | SUN6I_CLK_CTL_DRS;
++			tfr->effective_speed_hz = mclk_rate / (2 * div_cdr2);
++		} else {
++			div = min(SUN6I_CLK_CTL_CDR1_MASK, order_base_2(div_cdr1));
++			reg = SUN6I_CLK_CTL_CDR1(div);
++			tfr->effective_speed_hz = mclk_rate / (1 << div);
++		}
++		sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg);
+ 	} else {
+-		div = min(SUN6I_CLK_CTL_CDR1_MASK, order_base_2(div_cdr1));
+-		reg = SUN6I_CLK_CTL_CDR1(div);
+-		tfr->effective_speed_hz = mclk_rate / (1 << div);
++		clk_set_rate(sspi->mclk, tfr->speed_hz);
++		mclk_rate = clk_get_rate(sspi->mclk);
++		tfr->effective_speed_hz = mclk_rate;
+ 	}
+ 
+-	sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg);
+ 	/* Finally enable the bus - doing so before might raise SCK to HIGH */
+ 	reg = sun6i_spi_read(sspi, SUN6I_GBL_CTL_REG);
+ 	reg |= SUN6I_GBL_CTL_BUS_ENABLE;
+@@ -518,6 +527,7 @@ static int sun6i_spi_runtime_resume(stru
+ 	struct spi_master *master = dev_get_drvdata(dev);
+ 	struct sun6i_spi *sspi = spi_master_get_devdata(master);
+ 	int ret;
++	u32 reg;
+ 
+ 	ret = clk_prepare_enable(sspi->hclk);
+ 	if (ret) {
+@@ -537,8 +547,10 @@ static int sun6i_spi_runtime_resume(stru
+ 		goto err2;
+ 	}
+ 
+-	sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG,
+-			SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP);
++	reg = SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP;
++	if (sspi->quirks->has_new_sample_mode)
++		reg |= SUN6I_GBL_CTL_SAMPLE_MODE;
++	sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG, reg);
+ 
+ 	return 0;
+ 
+@@ -729,15 +741,23 @@ static int sun6i_spi_remove(struct platf
+ 
+ static const struct sun6i_spi_quirks sun6i_a31_spi_quirks = {
+ 	.fifo_depth		= SUN6I_FIFO_DEPTH,
++	.has_divider		= true,
+ };
+ 
+ static const struct sun6i_spi_quirks sun8i_h3_spi_quirks = {
+ 	.fifo_depth		= SUN8I_FIFO_DEPTH,
++	.has_divider		= true,
++};
++
++static const struct sun6i_spi_quirks sun50i_r329_spi_quirks = {
++	.fifo_depth		= SUN8I_FIFO_DEPTH,
++	.has_new_sample_mode	= true,
+ };
+ 
+ static const struct of_device_id sun6i_spi_match[] = {
+ 	{ .compatible = "allwinner,sun6i-a31-spi", .data = &sun6i_a31_spi_quirks },
+ 	{ .compatible = "allwinner,sun8i-h3-spi", .data = &sun8i_h3_spi_quirks },
++	{ .compatible = "allwinner,sun50i-r329-spi", .data = &sun50i_r329_spi_quirks },
+ 	{}
+ };
+ MODULE_DEVICE_TABLE(of, sun6i_spi_match);
diff --git a/target/linux/d1/patches-6.1/0077-spi-spi-sun6i-Dual-Quad-RX-Support.patch b/target/linux/d1/patches-6.1/0077-spi-spi-sun6i-Dual-Quad-RX-Support.patch
new file mode 100644
index 00000000000000..ab7df5fe8726d8
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0077-spi-spi-sun6i-Dual-Quad-RX-Support.patch
@@ -0,0 +1,50 @@
+From b300b013de16109f833782d9f4e7ee8cc204780f Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 17 Jul 2021 11:19:29 -0500
+Subject: [PATCH 077/117] spi: spi-sun6i: Dual/Quad RX Support
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/spi/spi-sun6i.c | 17 +++++++++++++++--
+ 1 file changed, 15 insertions(+), 2 deletions(-)
+
+--- a/drivers/spi/spi-sun6i.c
++++ b/drivers/spi/spi-sun6i.c
+@@ -82,6 +82,8 @@
+ #define SUN6I_XMIT_CNT_REG		0x34
+ 
+ #define SUN6I_BURST_CTL_CNT_REG		0x38
++#define SUN6I_BURST_CTL_CNT_QUAD_EN		BIT(29)
++#define SUN6I_BURST_CTL_CNT_DUAL_EN		BIT(28)
+ 
+ #define SUN6I_TXDATA_REG		0x200
+ #define SUN6I_RXDATA_REG		0x300
+@@ -415,7 +417,17 @@ static int sun6i_spi_transfer_one(struct
+ 	/* Setup the counters */
+ 	sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, tfr->len);
+ 	sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, tx_len);
+-	sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG, tx_len);
++
++	reg = tx_len;
++	switch (tfr->rx_nbits) {
++	case SPI_NBITS_QUAD:
++		reg |= SUN6I_BURST_CTL_CNT_QUAD_EN;
++		break;
++	case SPI_NBITS_DUAL:
++		reg |= SUN6I_BURST_CTL_CNT_DUAL_EN;
++		break;
++	}
++	sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG, reg);
+ 
+ 	if (!use_dma) {
+ 		/* Fill the TX FIFO */
+@@ -632,7 +644,8 @@ static int sun6i_spi_probe(struct platfo
+ 	master->set_cs = sun6i_spi_set_cs;
+ 	master->transfer_one = sun6i_spi_transfer_one;
+ 	master->num_chipselect = 4;
+-	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
++	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST
++			  | SPI_RX_DUAL | SPI_RX_QUAD;
+ 	master->bits_per_word_mask = SPI_BPW_MASK(8);
+ 	master->dev.of_node = pdev->dev.of_node;
+ 	master->auto_runtime_pm = true;
diff --git a/target/linux/d1/patches-6.1/0078-riscv-dts-allwinner-Add-SPI-support.patch b/target/linux/d1/patches-6.1/0078-riscv-dts-allwinner-Add-SPI-support.patch
new file mode 100644
index 00000000000000..67a3dfb32b97a4
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0078-riscv-dts-allwinner-Add-SPI-support.patch
@@ -0,0 +1,154 @@
+From aaabd3cf8c041b5122ca252f51fa616833e18749 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Thu, 11 Aug 2022 00:54:01 -0500
+Subject: [PATCH 078/117] riscv: dts: allwinner: Add SPI support
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ .../dts/allwinner/sun20i-d1-lichee-rv.dts     |  6 +++
+ .../boot/dts/allwinner/sun20i-d1-nezha.dts    | 44 ++++++++++++++++
+ arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi  | 51 +++++++++++++++++++
+ 3 files changed, 101 insertions(+)
+
+--- a/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv.dts
++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv.dts
+@@ -65,6 +65,12 @@
+ 	status = "okay";
+ };
+ 
++&spi0 {
++	pinctrl-0 = <&spi0_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-0 = <&uart0_pb8_pins>;
+ 	pinctrl-names = "default";
+--- a/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
+@@ -19,6 +19,7 @@
+ 		ethernet1 = &xr829;
+ 		mmc0 = &mmc0;
+ 		serial0 = &uart0;
++		spi0 = &spi0;
+ 	};
+ 
+ 	chosen {
+@@ -157,6 +158,49 @@
+ 	pinctrl-names = "default";
+ 	status = "okay";
+ };
++
++&spi0 {
++	pinctrl-0 = <&spi0_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++
++	flash@0 {
++		compatible = "spi-nand";
++		reg = <0>;
++
++		partitions {
++			compatible = "fixed-partitions";
++			#address-cells = <1>;
++			#size-cells = <1>;
++
++			partition@0 {
++				label = "boot0";
++				reg = <0x00000000 0x00100000>;
++			};
++
++			partition@100000 {
++				label = "uboot";
++				reg = <0x00100000 0x00300000>;
++			};
++
++			partition@400000 {
++				label = "secure_storage";
++				reg = <0x00400000 0x00100000>;
++			};
++
++			partition@500000 {
++				label = "sys";
++				reg = <0x00500000 0x0fb00000>;
++			};
++		};
++	};
++};
++
++&spi1 {
++	pinctrl-0 = <&spi1_pd_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++};
+ 
+ &uart0 {
+ 	pinctrl-0 = <&uart0_pb8_pins>;
+--- a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
+@@ -179,6 +179,24 @@
+ 			};
+ 
+ 			/omit-if-no-ref/
++			spi0_pins: spi0-pins {
++				pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7";
++				function = "spi0";
++			};
++
++			/omit-if-no-ref/
++			spi1_pb_pins: spi1-pb-pins {
++				pins = "PB0", "PB8", "PB9", "PB10", "PB11", "PB12";
++				function = "spi1";
++			};
++
++			/omit-if-no-ref/
++			spi1_pd_pins: spi1-pd-pins {
++				pins = "PD10", "PD11", "PD12", "PD13", "PD14", "PD15";
++				function = "spi1";
++			};
++
++			/omit-if-no-ref/
+ 			uart0_pb8_pins: uart0-pb8-pins {
+ 				pins = "PB8", "PB9";
+ 				function = "uart0";
+@@ -631,6 +649,39 @@
+ 			status = "disabled";
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
++		};
++
++		spi0: spi@4025000 {
++			compatible = "allwinner,sun20i-d1-spi",
++				     "allwinner,sun50i-r329-spi";
++			reg = <0x4025000 0x1000>;
++			interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
++			clock-names = "ahb", "mod";
++			resets = <&ccu RST_BUS_SPI0>;
++			dmas = <&dma 22>, <&dma 22>;
++			dma-names = "rx", "tx";
++			num-cs = <1>;
++			status = "disabled";
++			#address-cells = <1>;
++			#size-cells = <0>;
++		};
++
++		spi1: spi@4026000 {
++			compatible = "allwinner,sun20i-d1-spi-dbi",
++				     "allwinner,sun50i-r329-spi-dbi",
++				     "allwinner,sun50i-r329-spi";
++			reg = <0x4026000 0x1000>;
++			interrupts = <32 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
++			clock-names = "ahb", "mod";
++			resets = <&ccu RST_BUS_SPI1>;
++			dmas = <&dma 23>, <&dma 23>;
++			dma-names = "rx", "tx";
++			num-cs = <1>;
++			status = "disabled";
++			#address-cells = <1>;
++			#size-cells = <0>;
+ 		};
+ 
+ 		usb_otg: usb@4100000 {
diff --git a/target/linux/d1/patches-6.1/0079-dt-bindings-thermal-sun8i-Add-compatible-for-D1.patch b/target/linux/d1/patches-6.1/0079-dt-bindings-thermal-sun8i-Add-compatible-for-D1.patch
new file mode 100644
index 00000000000000..6ba5b3ac7541a4
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0079-dt-bindings-thermal-sun8i-Add-compatible-for-D1.patch
@@ -0,0 +1,80 @@
+From 68c6f452bf42d6c5cbaf40537d8a17a7f3f5481e Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 6 Jun 2021 10:03:12 -0500
+Subject: [PATCH 079/117] dt-bindings: thermal: sun8i: Add compatible for D1
+
+D1 contains a thermal sensor similar to other Allwinner SoCs. Like the
+H3 variant, it contains only one channel.
+
+D1's thermal sensor gets a reference voltage from AVCC. This may always
+have been the case; it is explicitly documented in the SoC user manuals
+since at least H616. However, it was not as important on earlier SoCs,
+because those reference designs foreced AVCC always-on by connecting it
+to the PLL power supply.
+
+Now, since D1 only uses AVCC for other optional peripherals, this supply
+could be turned off at runtime, so it must be made explicit in the DTS.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ .../thermal/allwinner,sun8i-a83t-ths.yaml     | 21 ++++++++++++++++++-
+ 1 file changed, 20 insertions(+), 1 deletion(-)
+
+--- a/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml
++++ b/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml
+@@ -16,6 +16,7 @@ properties:
+       - allwinner,sun8i-a83t-ths
+       - allwinner,sun8i-h3-ths
+       - allwinner,sun8i-r40-ths
++      - allwinner,sun20i-d1-ths
+       - allwinner,sun50i-a64-ths
+       - allwinner,sun50i-a100-ths
+       - allwinner,sun50i-h5-ths
+@@ -55,6 +56,10 @@ properties:
+       - 0
+       - 1
+ 
++  vref-supply:
++    description:
++      Regulator for the analog reference voltage
++
+ allOf:
+   - if:
+       properties:
+@@ -84,7 +89,9 @@ allOf:
+       properties:
+         compatible:
+           contains:
+-            const: allwinner,sun8i-h3-ths
++            enum:
++              - allwinner,sun8i-h3-ths
++              - allwinner,sun20i-d1-ths
+ 
+     then:
+       properties:
+@@ -103,6 +110,7 @@ allOf:
+             enum:
+               - allwinner,sun8i-h3-ths
+               - allwinner,sun8i-r40-ths
++              - allwinner,sun20i-d1-ths
+               - allwinner,sun50i-a64-ths
+               - allwinner,sun50i-a100-ths
+               - allwinner,sun50i-h5-ths
+@@ -114,6 +122,17 @@ allOf:
+         - clock-names
+         - resets
+ 
++  - if:
++      properties:
++        compatible:
++          contains:
++            enum:
++              - allwinner,sun20i-d1-ths
++
++    then:
++      required:
++        - vref-supply
++
+ required:
+   - compatible
+   - reg
diff --git a/target/linux/d1/patches-6.1/0080-riscv-dts-allwinner-d1-Add-thermal-sensor-and-zone.patch b/target/linux/d1/patches-6.1/0080-riscv-dts-allwinner-d1-Add-thermal-sensor-and-zone.patch
new file mode 100644
index 00000000000000..9bfb74b895f59d
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0080-riscv-dts-allwinner-d1-Add-thermal-sensor-and-zone.patch
@@ -0,0 +1,79 @@
+From c225b48d2cf5f5a824b5b0a4144511bdc5f65ab5 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 14 Aug 2022 11:18:11 -0500
+Subject: [PATCH 080/117] riscv: dts: allwinner: d1: Add thermal sensor and
+ zone
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ .../sun20i-d1-common-regulators.dtsi          |  4 ++
+ arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi  | 41 +++++++++++++++++++
+ 2 files changed, 45 insertions(+)
+
+--- a/arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi
++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi
+@@ -49,3 +49,7 @@
+ 	regulator-max-microvolt = <1800000>;
+ 	ldo-in-supply = <&reg_vcc_3v3>;
+ };
++
++&ths {
++	vref-supply = <&reg_aldo>;
++};
+--- a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
+@@ -59,6 +59,35 @@
+ 		#clock-cells = <0>;
+ 	};
+ 
++	thermal-zones {
++		cpu-thermal {
++			polling-delay = <0>;
++			polling-delay-passive = <0>;
++			thermal-sensors = <&ths>;
++
++			trips {
++				cpu_target: cpu-target {
++					hysteresis = <3000>;
++					temperature = <85000>;
++					type = "passive";
++				};
++
++				cpu-crit {
++					hysteresis = <0>;
++					temperature = <110000>;
++					type = "critical";
++				};
++			};
++
++			cooling-maps {
++				map0 {
++					trip = <&cpu_target>;
++					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
++				};
++			};
++		};
++	};
++
+ 	soc {
+ 		compatible = "simple-bus";
+ 		ranges;
+@@ -252,6 +281,18 @@
+ 			#size-cells = <0>;
+ 		};
+ 
++		ths: temperature-sensor@2009400 {
++			compatible = "allwinner,sun20i-d1-ths";
++			reg = <0x2009400 0x400>;
++			interrupts = <74 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_THS>, <&osc24M>;
++			clock-names = "bus", "mod";
++			resets = <&ccu RST_BUS_THS>;
++			nvmem-cells = <&ths_calib>;
++			nvmem-cell-names = "calibration";
++			#thermal-sensor-cells = <0>;
++		};
++
+ 		lradc: keys@2009800 {
+ 			compatible = "allwinner,sun20i-d1-lradc",
+ 				     "allwinner,sun50i-r329-lradc";
diff --git a/target/linux/d1/patches-6.1/0081-ASoC-sun20i-codec-New-driver-for-D1-internal-codec.patch b/target/linux/d1/patches-6.1/0081-ASoC-sun20i-codec-New-driver-for-D1-internal-codec.patch
new file mode 100644
index 00000000000000..6460d84f07a176
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0081-ASoC-sun20i-codec-New-driver-for-D1-internal-codec.patch
@@ -0,0 +1,927 @@
+From 9b6a07cacab9300c261b1f7e25857f96cfeae9cf Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 12 Jun 2021 23:42:48 -0500
+Subject: [PATCH 081/117] ASoC: sun20i-codec: New driver for D1 internal codec
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ sound/soc/sunxi/Kconfig        |   6 +
+ sound/soc/sunxi/Makefile       |   1 +
+ sound/soc/sunxi/sun20i-codec.c | 886 +++++++++++++++++++++++++++++++++
+ 3 files changed, 893 insertions(+)
+ create mode 100644 sound/soc/sunxi/sun20i-codec.c
+
+--- a/sound/soc/sunxi/Kconfig
++++ b/sound/soc/sunxi/Kconfig
+@@ -30,6 +30,12 @@ config SND_SUN8I_CODEC_ANALOG
+ 	  Say Y or M if you want to add support for the analog controls for
+ 	  the codec embedded in newer Allwinner SoCs.
+ 
++config SND_SUN20I_CODEC
++	tristate "Allwinner D1 (sun20i) Audio Codec"
++	depends on ARCH_SUNXI || COMPILE_TEST
++	help
++	  Say Y or M to add support for the audio codec in Allwinner D1 SoC.
++
+ config SND_SUN50I_CODEC_ANALOG
+ 	tristate "Allwinner sun50i Codec Analog Controls Support"
+ 	depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
+--- a/sound/soc/sunxi/Makefile
++++ b/sound/soc/sunxi/Makefile
+@@ -3,6 +3,7 @@ obj-$(CONFIG_SND_SUN4I_CODEC) += sun4i-c
+ obj-$(CONFIG_SND_SUN4I_I2S) += sun4i-i2s.o
+ obj-$(CONFIG_SND_SUN4I_SPDIF) += sun4i-spdif.o
+ obj-$(CONFIG_SND_SUN8I_CODEC_ANALOG) += sun8i-codec-analog.o
++obj-$(CONFIG_SND_SUN20I_CODEC) += sun20i-codec.o
+ obj-$(CONFIG_SND_SUN50I_CODEC_ANALOG) += sun50i-codec-analog.o
+ obj-$(CONFIG_SND_SUN8I_CODEC) += sun8i-codec.o
+ obj-$(CONFIG_SND_SUN8I_ADDA_PR_REGMAP) += sun8i-adda-pr-regmap.o
+--- /dev/null
++++ b/sound/soc/sunxi/sun20i-codec.c
+@@ -0,0 +1,886 @@
++// SPDX-License-Identifier: GPL-2.0+
++
++#include <linux/clk.h>
++#include <linux/io.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/regmap.h>
++#include <linux/reset.h>
++
++#include <sound/dmaengine_pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/simple_card_utils.h>
++#include <sound/soc.h>
++#include <sound/soc-dai.h>
++#include <sound/soc-dapm.h>
++#include <sound/tlv.h>
++
++#define SUN20I_CODEC_DAC_DPC		0x0000
++#define SUN20I_CODEC_DAC_DPC_EN_DA		31
++#define SUN20I_CODEC_DAC_DPC_HPF_EN		18
++#define SUN20I_CODEC_DAC_DPC_DVOL		12
++#define SUN20I_CODEC_DAC_VOL_CTRL	0x0004
++#define SUN20I_CODEC_DAC_VOL_CTRL_DAC_VOL_SEL	16
++#define SUN20I_CODEC_DAC_VOL_CTRL_DAC_VOL_L	8
++#define SUN20I_CODEC_DAC_VOL_CTRL_DAC_VOL_R	0
++#define SUN20I_CODEC_DAC_FIFOC		0x0010
++#define SUN20I_CODEC_DAC_FIFOC_FS		29
++#define SUN20I_CODEC_DAC_FIFOC_FIFO_MODE	24
++#define SUN20I_CODEC_DAC_FIFOC_DRQ_CLR_CNT	21
++#define SUN20I_CODEC_DAC_FIFOC_TRIG_LEVEL	8
++#define SUN20I_CODEC_DAC_FIFOC_MONO_EN		6
++#define SUN20I_CODEC_DAC_FIFOC_SAMPLE_BITS	5
++#define SUN20I_CODEC_DAC_FIFOC_DRQ_EN		4
++#define SUN20I_CODEC_DAC_FIFOC_FIFO_FLUSH	0
++#define SUN20I_CODEC_DAC_TXDATA		0x0020
++#define SUN20I_CODEC_DAC_DEBUG		0x0028
++#define SUN20I_CODEC_DAC_DEBUG_DA_SWP		6
++#define SUN20I_CODEC_DAC_ADDA_LOOP_MODE		0
++
++#define SUN20I_CODEC_ADC_FIFOC		0x0030
++#define SUN20I_CODEC_ADC_FIFOC_FS		29
++#define SUN20I_CODEC_ADC_FIFOC_EN_AD		28
++#define SUN20I_CODEC_ADC_FIFOC_FIFO_MODE	24
++#define SUN20I_CODEC_ADC_FIFOC_SAMPLE_BITS	16
++#define SUN20I_CODEC_ADC_FIFOC_TRIG_LEVEL	4
++#define SUN20I_CODEC_ADC_FIFOC_DRQ_EN		3
++#define SUN20I_CODEC_ADC_FIFOC_FIFO_FLUSH	0
++#define SUN20I_CODEC_ADC_VOL_CTRL	0x0034
++#define SUN20I_CODEC_ADC_VOL_CTRL_ADC3_VOL	16
++#define SUN20I_CODEC_ADC_VOL_CTRL_ADC2_VOL	8
++#define SUN20I_CODEC_ADC_VOL_CTRL_ADC1_VOL	0
++#define SUN20I_CODEC_ADC_RXDATA		0x0040
++#define SUN20I_CODEC_ADC_DEBUG		0x004c
++#define SUN20I_CODEC_ADC_DEBUG_AD_SWP1		24
++#define SUN20I_CODEC_ADC_DIG_CTRL	0x0050
++#define SUN20I_CODEC_ADC_DIG_CTRL_ADC_VOL_EN	16
++#define SUN20I_CODEC_ADC_DIG_CTRL_ADC_EN	0
++
++#define SUN20I_CODEC_DAC_DAP_CTRL	0x00f0
++#define SUN20I_CODEC_DAC_DAP_CTRL_DAP_EN	31
++#define SUN20I_CODEC_DAC_DAP_CTRL_DAP_DRC_EN	29
++#define SUN20I_CODEC_DAC_DAP_CTRL_DAP_HPF_EN	28
++
++#define SUN20I_CODEC_ADC_DAP_CTRL	0x00f8
++#define SUN20I_CODEC_ADC_DAP_CTRL_DAP0_EN	31
++#define SUN20I_CODEC_ADC_DAP_CTRL_DAP0_DRC_EN	29
++#define SUN20I_CODEC_ADC_DAP_CTRL_DAP0_HPF_EN	28
++#define SUN20I_CODEC_ADC_DAP_CTRL_DAP1_EN	27
++#define SUN20I_CODEC_ADC_DAP_CTRL_DAP1_DRC_EN	25
++#define SUN20I_CODEC_ADC_DAP_CTRL_DAP1_HPF_EN	24
++
++#define SUN20I_CODEC_ADC1		0x0300
++#define SUN20I_CODEC_ADC1_ADC1_EN		31
++#define SUN20I_CODEC_ADC1_MICIN1_PGA_EN		30
++#define SUN20I_CODEC_ADC1_ADC1_DITHER_EN	29
++#define SUN20I_CODEC_ADC1_MICIN1_SIN_EN		28
++#define SUN20I_CODEC_ADC1_FMINL_EN		27
++#define SUN20I_CODEC_ADC1_FMINL_GAIN		26
++#define SUN20I_CODEC_ADC1_DITHER_LEVEL		24
++#define SUN20I_CODEC_ADC1_LINEINL_EN		23
++#define SUN20I_CODEC_ADC1_LINEINL_GAIN		22
++#define SUN20I_CODEC_ADC1_ADC1_PGA_GAIN		8
++#define SUN20I_CODEC_ADC2		0x0304
++#define SUN20I_CODEC_ADC2_ADC2_EN		31
++#define SUN20I_CODEC_ADC2_MICIN2_PGA_EN		30
++#define SUN20I_CODEC_ADC2_ADC2_DITHER_EN	29
++#define SUN20I_CODEC_ADC2_MICIN2_SIN_EN		28
++#define SUN20I_CODEC_ADC2_FMINR_EN		27
++#define SUN20I_CODEC_ADC2_FMINR_GAIN		26
++#define SUN20I_CODEC_ADC2_DITHER_LEVEL		24
++#define SUN20I_CODEC_ADC2_LINEINR_EN		23
++#define SUN20I_CODEC_ADC2_LINEINR_GAIN		22
++#define SUN20I_CODEC_ADC2_ADC2_PGA_GAIN		8
++#define SUN20I_CODEC_ADC3		0x0308
++#define SUN20I_CODEC_ADC3_ADC3_EN		31
++#define SUN20I_CODEC_ADC3_MICIN3_PGA_EN		30
++#define SUN20I_CODEC_ADC3_ADC3_DITHER_EN	29
++#define SUN20I_CODEC_ADC3_MICIN3_SIN_EN		28
++#define SUN20I_CODEC_ADC3_DITHER_LEVEL		24
++#define SUN20I_CODEC_ADC3_ADC3_PGA_GAIN		8
++
++#define SUN20I_CODEC_DAC		0x0310
++#define SUN20I_CODEC_DAC_DACL_EN		15
++#define SUN20I_CODEC_DAC_DACR_EN		14
++#define SUN20I_CODEC_DAC_LINEOUTL_EN		13
++#define SUN20I_CODEC_DAC_LMUTE			12
++#define SUN20I_CODEC_DAC_LINEOUTR_EN		11
++#define SUN20I_CODEC_DAC_RMUTE			10
++#define SUN20I_CODEC_DAC_LINEOUTL_DIFFEN	6
++#define SUN20I_CODEC_DAC_LINEOUTR_DIFFEN	5
++#define SUN20I_CODEC_DAC_LINEOUT_VOL_CTRL	0
++
++#define SUN20I_CODEC_MICBIAS		0x0318
++#define SUN20I_CODEC_MICBIAS_SELDETADCFS	28
++#define SUN20I_CODEC_MICBIAS_SELDETADCDB	26
++#define SUN20I_CODEC_MICBIAS_SELDETADCBF	24
++#define SUN20I_CODEC_MICBIAS_JACKDETEN		23
++#define SUN20I_CODEC_MICBIAS_SELDETADCDY	21
++#define SUN20I_CODEC_MICBIAS_MICADCEN		20
++#define SUN20I_CODEC_MICBIAS_POPFREE		19
++#define SUN20I_CODEC_MICBIAS_DET_MODE		18
++#define SUN20I_CODEC_MICBIAS_AUTOPLEN		17
++#define SUN20I_CODEC_MICBIAS_MICDETPL		16
++#define SUN20I_CODEC_MICBIAS_HMICBIASEN		15
++#define SUN20I_CODEC_MICBIAS_HMICBIASSEL	13
++#define SUN20I_CODEC_MICBIAS_HMIC_CHOPPER_EN	12
++#define SUN20I_CODEC_MICBIAS_HMIC_CHOPPER_CLK	10
++#define SUN20I_CODEC_MICBIAS_MMICBIASEN		7
++#define SUN20I_CODEC_MICBIAS_MMICBIASSEL	5
++#define SUN20I_CODEC_MICBIAS_MMIC_CHOPPER_EN	4
++#define SUN20I_CODEC_MICBIAS_MMIC_CHOPPER_CLK	2
++
++/* TODO */
++#define SUN20I_CODEC_RAMP		0x031c
++#define SUN20I_CODEC_RAMP_HP_PULL_OUT_EN	15
++
++#define SUN20I_CODEC_HMIC_CTRL		0x0328
++#define SUN20I_CODEC_HMIC_CTRL_SAMPLE_SELECT	21
++#define SUN20I_CODEC_HMIC_CTRL_MDATA_THRESHOLD	16
++#define SUN20I_CODEC_HMIC_CTRL_SF		14
++#define SUN20I_CODEC_HMIC_CTRL_M		10
++#define SUN20I_CODEC_HMIC_CTRL_N		6
++#define SUN20I_CODEC_HMIC_CTRL_THRESH_DEBOUNCE	3
++#define SUN20I_CODEC_HMIC_CTRL_JACK_OUT_IRQ_EN	2
++#define SUN20I_CODEC_HMIC_CTRL_JACK_IN_IRQ_EN	1
++#define SUN20I_CODEC_HMIC_CTRL_MIC_DET_IRQ_EN	0
++#define SUN20I_CODEC_HMIC_STS		0x032c
++#define SUN20I_CODEC_HMIC_STS_MDATA_DISCARD	13
++#define SUN20I_CODEC_HMIC_STS_HMIC_DATA		8
++#define SUN20I_CODEC_HMIC_STS_JACK_OUT_IRQ	4
++#define SUN20I_CODEC_HMIC_STS_JACK_IN_IRQ	3
++#define SUN20I_CODEC_HMIC_STS_MIC_DET_IRQ	0
++
++#define SUN20I_CODEC_HP2		0x0340
++#define SUN20I_CODEC_HP2_HPFB_BUF_EN		31
++#define SUN20I_CODEC_HP2_HEADPHONE_GAIN		28
++#define SUN20I_CODEC_HP2_HPFB_RES		26
++#define SUN20I_CODEC_HP2_HP_DRVEN		21
++#define SUN20I_CODEC_HP2_HP_DRVOUTEN		20
++#define SUN20I_CODEC_HP2_RSWITCH		19
++#define SUN20I_CODEC_HP2_RAMPEN			18
++#define SUN20I_CODEC_HP2_HPFB_IN_EN		17
++#define SUN20I_CODEC_HP2_RAMP_FINAL_CONTROL	16
++#define SUN20I_CODEC_HP2_RAMP_OUT_EN		15
++#define SUN20I_CODEC_HP2_RAMP_FINAL_STATE_RES	13
++
++/* Not affected by codec bus clock/reset */
++#define SUN20I_CODEC_POWER		0x0348
++#define SUN20I_CODEC_POWER_ALDO_EN_MASK		BIT(31)
++#define SUN20I_CODEC_POWER_HPLDO_EN_MASK	BIT(30)
++#define SUN20I_CODEC_POWER_ALDO_VOLTAGE_MASK	GENMASK(14, 12)
++#define SUN20I_CODEC_POWER_HPLDO_VOLTAGE_MASK	GENMASK(10, 8)
++
++#define SUN20I_CODEC_ADC_CUR		0x034c
++
++#define SUN20I_CODEC_PCM_FORMATS	(SNDRV_PCM_FMTBIT_S16_LE|\
++					 SNDRV_PCM_FMTBIT_S20_LE|\
++					 SNDRV_PCM_FMTBIT_S32_LE)
++
++#define DRIVER_NAME			"sun20i-codec"
++
++/* snd_soc_register_card() takes over drvdata, so the card must be first! */
++struct sun20i_codec {
++	struct snd_soc_card			card;
++	struct snd_soc_dai_link			dai_link;
++	struct snd_soc_dai_link_component	dlcs[3];
++	struct snd_dmaengine_dai_dma_data	dma_data[2];
++
++	struct clk		*bus_clk;
++	struct clk		*adc_clk;
++	struct clk		*dac_clk;
++	struct reset_control	*reset;
++};
++
++static int sun20i_codec_dai_probe(struct snd_soc_dai *dai)
++{
++	struct sun20i_codec *codec = snd_soc_dai_get_drvdata(dai);
++
++	snd_soc_dai_init_dma_data(dai,
++				  &codec->dma_data[SNDRV_PCM_STREAM_PLAYBACK],
++				  &codec->dma_data[SNDRV_PCM_STREAM_CAPTURE]);
++
++	return 0;
++}
++
++static struct clk *sun20i_codec_get_clk(struct snd_pcm_substream *substream,
++					struct snd_soc_dai *dai)
++{
++	struct sun20i_codec *codec = snd_soc_dai_get_drvdata(dai);
++
++	return substream->stream == SNDRV_PCM_STREAM_CAPTURE ?
++		codec->adc_clk : codec->dac_clk;
++}
++
++static const unsigned int sun20i_codec_rates[] = {
++	 7350,   8000,  11025,  12000,  14700,  16000,  22050,  24000,
++	29400,  32000,  44100,  48000,  88200,  96000, 176400, 192000,
++};
++
++static const struct snd_pcm_hw_constraint_list sun20i_codec_rate_lists[] = {
++	[SNDRV_PCM_STREAM_PLAYBACK] = {
++		.list	= sun20i_codec_rates,
++		.count	= ARRAY_SIZE(sun20i_codec_rates),
++	},
++	[SNDRV_PCM_STREAM_CAPTURE] = {
++		.list	= sun20i_codec_rates,
++		.count	= ARRAY_SIZE(sun20i_codec_rates) - 4, /* max 48 kHz */
++	},
++};
++
++static int sun20i_codec_startup(struct snd_pcm_substream *substream,
++				struct snd_soc_dai *dai)
++{
++	const struct snd_pcm_hw_constraint_list *list;
++	int ret;
++
++	list = &sun20i_codec_rate_lists[substream->stream];
++	ret = snd_pcm_hw_constraint_list(substream->runtime, 0,
++					 SNDRV_PCM_HW_PARAM_RATE, list);
++	if (ret)
++		return ret;
++
++	ret = clk_prepare_enable(sun20i_codec_get_clk(substream, dai));
++	if (ret)
++		return ret;
++
++	return 0;
++}
++
++static void sun20i_codec_shutdown(struct snd_pcm_substream *substream,
++				  struct snd_soc_dai *dai)
++{
++	clk_disable_unprepare(sun20i_codec_get_clk(substream, dai));
++}
++
++static unsigned int sun20i_codec_get_clk_rate(unsigned int sample_rate)
++{
++	return (sample_rate % 4000) ? 22579200 : 24576000;
++}
++
++static const unsigned short sun20i_codec_divisors[] = {
++	512, 1024, 2048, 128,
++	768, 1536, 3072, 256,
++};
++
++static int sun20i_codec_get_fs(unsigned int clk_rate, unsigned int sample_rate)
++{
++	unsigned int divisor = clk_rate / sample_rate;
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(sun20i_codec_divisors); ++i)
++		if (sun20i_codec_divisors[i] == divisor)
++			return i;
++
++	return -EINVAL;
++}
++
++static int sun20i_codec_hw_params(struct snd_pcm_substream *substream,
++				  struct snd_pcm_hw_params *params,
++				  struct snd_soc_dai *dai)
++{
++	struct sun20i_codec *codec = snd_soc_dai_get_drvdata(dai);
++	struct snd_soc_component *component = dai->component;
++	unsigned int channels = params_channels(params);
++	unsigned int sample_bits = params_width(params);
++	unsigned int sample_rate = params_rate(params);
++	unsigned int clk_rate = sun20i_codec_get_clk_rate(sample_rate);
++	enum dma_slave_buswidth dma_width;
++	unsigned int reg;
++	int ret, val;
++
++	switch (params_physical_width(params)) {
++	case 16:
++		dma_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
++		break;
++	case 32:
++		dma_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
++		break;
++	default:
++		dev_err(dai->dev, "Unsupported physical sample width: %d\n",
++			params_physical_width(params));
++		return -EINVAL;
++	}
++	codec->dma_data[substream->stream].addr_width = dma_width;
++
++	ret = clk_set_rate(sun20i_codec_get_clk(substream, dai),
++			   sun20i_codec_get_clk_rate(sample_rate));
++	if (ret)
++		return ret;
++
++	reg = substream->stream == SNDRV_PCM_STREAM_CAPTURE ?
++		SUN20I_CODEC_ADC_FIFOC : SUN20I_CODEC_DAC_FIFOC;
++
++	val = sun20i_codec_get_fs(clk_rate, sample_rate);
++	if (val < 0)
++		return val;
++	snd_soc_component_update_bits(component, reg,
++				      0x7 << SUN20I_CODEC_DAC_FIFOC_FS,
++				      val << SUN20I_CODEC_DAC_FIFOC_FS);
++
++	/* Data is at MSB for full 4-byte samples, otherwise at LSB. */
++	val = sample_bits != 32;
++	snd_soc_component_update_bits(component, reg,
++				      0x1 << SUN20I_CODEC_DAC_FIFOC_FIFO_MODE,
++				      val << SUN20I_CODEC_DAC_FIFOC_FIFO_MODE);
++
++	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
++		val = sample_bits > 16;
++		snd_soc_component_update_bits(component, reg,
++					      0x1 << SUN20I_CODEC_ADC_FIFOC_SAMPLE_BITS,
++					      val << SUN20I_CODEC_ADC_FIFOC_SAMPLE_BITS);
++
++		val = BIT(channels) - 1;
++		snd_soc_component_update_bits(component, SUN20I_CODEC_ADC_DIG_CTRL,
++					      0xf << SUN20I_CODEC_ADC_DIG_CTRL_ADC_EN,
++					      val << SUN20I_CODEC_ADC_DIG_CTRL_ADC_EN);
++	} else {
++		val = sample_bits > 16;
++		snd_soc_component_update_bits(component, reg,
++					      0x1 << SUN20I_CODEC_DAC_FIFOC_SAMPLE_BITS,
++					      val << SUN20I_CODEC_DAC_FIFOC_SAMPLE_BITS);
++
++		val = channels == 1;
++		snd_soc_component_update_bits(component, reg,
++					      0x1 << SUN20I_CODEC_DAC_FIFOC_MONO_EN,
++					      val << SUN20I_CODEC_DAC_FIFOC_MONO_EN);
++	}
++
++	return 0;
++}
++
++static int sun20i_codec_trigger(struct snd_pcm_substream *substream, int cmd,
++				struct snd_soc_dai *dai)
++{
++	struct snd_soc_component *component = dai->component;
++	unsigned int reg, mask;
++
++	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
++		reg  = SUN20I_CODEC_ADC_FIFOC;
++		mask = BIT(SUN20I_CODEC_ADC_FIFOC_DRQ_EN);
++	} else {
++		reg  = SUN20I_CODEC_DAC_FIFOC;
++		mask = BIT(SUN20I_CODEC_DAC_FIFOC_DRQ_EN);
++	}
++
++	switch (cmd) {
++	case SNDRV_PCM_TRIGGER_START:
++	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++	case SNDRV_PCM_TRIGGER_RESUME:
++		mask |= BIT(SUN20I_CODEC_DAC_FIFOC_FIFO_FLUSH);
++		snd_soc_component_update_bits(component, reg, mask, mask);
++		break;
++	case SNDRV_PCM_TRIGGER_STOP:
++	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++	case SNDRV_PCM_TRIGGER_SUSPEND:
++		snd_soc_component_update_bits(component, reg, mask, 0);
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static const struct snd_soc_dai_ops sun20i_codec_dai_ops = {
++	.startup	= sun20i_codec_startup,
++	.shutdown	= sun20i_codec_shutdown,
++	.hw_params	= sun20i_codec_hw_params,
++	.trigger	= sun20i_codec_trigger,
++};
++
++static struct snd_soc_dai_driver sun20i_codec_dai = {
++	.name = DRIVER_NAME,
++	.probe = sun20i_codec_dai_probe,
++	.ops = &sun20i_codec_dai_ops,
++	.capture = {
++		.stream_name	= "Capture",
++		.channels_min	= 1,
++		.channels_max	= 3, /* ??? */
++		.rates		= SNDRV_PCM_RATE_CONTINUOUS,
++		.formats	= SUN20I_CODEC_PCM_FORMATS,
++		.sig_bits	= 20,
++	},
++	.playback = {
++		.stream_name	= "Playback",
++		.channels_min	= 1,
++		.channels_max	= 2,
++		.rates		= SNDRV_PCM_RATE_CONTINUOUS,
++		.formats	= SUN20I_CODEC_PCM_FORMATS,
++		.sig_bits	= 20,
++	},
++};
++
++static const DECLARE_TLV_DB_SCALE(sun20i_codec_boost_vol_scale, 0, 600, 0);
++static const DECLARE_TLV_DB_SCALE(sun20i_codec_digital_vol_scale, -12000, 75, 1);
++static const DECLARE_TLV_DB_SCALE(sun20i_codec_headphone_vol_scale, -4200, 600, 0);
++/* FIXME */
++static const DECLARE_TLV_DB_SCALE(sun20i_codec_line_out_vol_scale, -4650, 150, 1);
++/* FIXME */
++static const DECLARE_TLV_DB_SCALE(sun20i_codec_pga_vol_scale, 500, 100, 0);
++
++static const char *const sun20i_codec_line_out_mode_enum_text[] = {
++	"Single-Ended", "Differential"
++};
++
++static const SOC_ENUM_DOUBLE_DECL(sun20i_codec_line_out_mode_enum,
++				  SUN20I_CODEC_DAC,
++				  SUN20I_CODEC_DAC_LINEOUTL_DIFFEN,
++				  SUN20I_CODEC_DAC_LINEOUTR_DIFFEN,
++				  sun20i_codec_line_out_mode_enum_text);
++
++static const struct snd_kcontrol_new sun20i_codec_controls[] = {
++	/* Digital Controls */
++	SOC_DOUBLE_TLV("DAC Playback Volume",
++		       SUN20I_CODEC_DAC_VOL_CTRL,
++		       SUN20I_CODEC_DAC_VOL_CTRL_DAC_VOL_L,
++		       SUN20I_CODEC_DAC_VOL_CTRL_DAC_VOL_R,
++		       0xc0, 0, sun20i_codec_digital_vol_scale),
++	SOC_SINGLE_TLV("ADC3 Capture Volume",
++		       SUN20I_CODEC_ADC_VOL_CTRL,
++		       SUN20I_CODEC_ADC_VOL_CTRL_ADC3_VOL,
++		       0xc0, 0, sun20i_codec_digital_vol_scale),
++	SOC_SINGLE_TLV("ADC2 Capture Volume",
++		       SUN20I_CODEC_ADC_VOL_CTRL,
++		       SUN20I_CODEC_ADC_VOL_CTRL_ADC2_VOL,
++		       0xc0, 0, sun20i_codec_digital_vol_scale),
++	SOC_SINGLE_TLV("ADC1 Capture Volume",
++		       SUN20I_CODEC_ADC_VOL_CTRL,
++		       SUN20I_CODEC_ADC_VOL_CTRL_ADC1_VOL,
++		       0xc0, 0, sun20i_codec_digital_vol_scale),
++
++	/* Analog Controls */
++	SOC_DOUBLE_R_TLV("FM Capture Volume",
++			 SUN20I_CODEC_ADC1,
++			 SUN20I_CODEC_ADC2,
++			 SUN20I_CODEC_ADC1_FMINL_GAIN,
++			 0x1, 0, sun20i_codec_boost_vol_scale),
++	SOC_DOUBLE_R_TLV("Line In Capture Volume",
++			 SUN20I_CODEC_ADC1,
++			 SUN20I_CODEC_ADC2,
++			 SUN20I_CODEC_ADC1_LINEINL_GAIN,
++			 0x1, 0, sun20i_codec_boost_vol_scale),
++	SOC_ENUM("Line Out Mode Playback Enum",
++		 sun20i_codec_line_out_mode_enum),
++	SOC_SINGLE_TLV("Line Out Playback Volume",
++		       SUN20I_CODEC_DAC,
++		       SUN20I_CODEC_DAC_LINEOUT_VOL_CTRL,
++		       0x1f, 0, sun20i_codec_line_out_vol_scale),
++	SOC_SINGLE_TLV("Headphone Playback Volume",
++		       SUN20I_CODEC_HP2,
++		       SUN20I_CODEC_HP2_HEADPHONE_GAIN,
++		       0x7, 1, sun20i_codec_headphone_vol_scale),
++};
++
++static const struct snd_kcontrol_new sun20i_codec_line_out_switch =
++	SOC_DAPM_DOUBLE("Line Out Playback Switch",
++			SUN20I_CODEC_DAC,
++			SUN20I_CODEC_DAC_LMUTE,
++			SUN20I_CODEC_DAC_RMUTE, 1, 1);
++
++static const struct snd_kcontrol_new sun20i_codec_hp_switch =
++	SOC_DAPM_SINGLE("Headphone Playback Switch",
++			SUN20I_CODEC_HP2,
++			SUN20I_CODEC_HP2_HP_DRVOUTEN, 1, 0);
++
++static const struct snd_kcontrol_new sun20i_codec_adc12_mixer_controls[] = {
++	/* ADC1 Only */
++	SOC_DAPM_SINGLE("Mic1 Capture Switch",
++			SUN20I_CODEC_ADC1,
++			SUN20I_CODEC_ADC1_MICIN1_SIN_EN, 1, 0),
++	/* Shared */
++	SOC_DAPM_DOUBLE_R("FM Capture Switch",
++			  SUN20I_CODEC_ADC1,
++			  SUN20I_CODEC_ADC2,
++			  SUN20I_CODEC_ADC1_FMINL_EN, 1, 0),
++	/* Shared */
++	SOC_DAPM_DOUBLE_R("Line In Capture Switch",
++			  SUN20I_CODEC_ADC1,
++			  SUN20I_CODEC_ADC2,
++			  SUN20I_CODEC_ADC1_LINEINL_EN, 1, 0),
++	/* ADC2 Only */
++	SOC_DAPM_SINGLE("Mic2 Capture Switch",
++			SUN20I_CODEC_ADC2,
++			SUN20I_CODEC_ADC2_MICIN2_SIN_EN, 1, 0),
++};
++
++static const struct snd_kcontrol_new sun20i_codec_adc3_mixer_controls[] = {
++	SOC_DAPM_SINGLE("Mic3 Capture Switch",
++			SUN20I_CODEC_ADC3,
++			SUN20I_CODEC_ADC3_MICIN3_SIN_EN, 1, 0),
++};
++
++static const struct snd_kcontrol_new sun20i_codec_mic1_volume =
++	SOC_DAPM_SINGLE_TLV("Capture Volume",
++			    SUN20I_CODEC_ADC1,
++			    SUN20I_CODEC_ADC1_ADC1_PGA_GAIN,
++			    0x1f, 0, sun20i_codec_pga_vol_scale);
++
++static const struct snd_kcontrol_new sun20i_codec_mic2_volume =
++	SOC_DAPM_SINGLE_TLV("Capture Volume",
++			    SUN20I_CODEC_ADC2,
++			    SUN20I_CODEC_ADC2_ADC2_PGA_GAIN,
++			    0x1f, 0, sun20i_codec_pga_vol_scale);
++
++static const struct snd_kcontrol_new sun20i_codec_mic3_volume =
++	SOC_DAPM_SINGLE_TLV("Capture Volume",
++			    SUN20I_CODEC_ADC3,
++			    SUN20I_CODEC_ADC3_ADC3_PGA_GAIN,
++			    0x1f, 0, sun20i_codec_pga_vol_scale);
++
++static const struct snd_soc_dapm_widget sun20i_codec_widgets[] = {
++	/* Playback */
++	SND_SOC_DAPM_OUTPUT("LINEOUTL"),
++	SND_SOC_DAPM_OUTPUT("LINEOUTR"),
++
++	SND_SOC_DAPM_SWITCH("LINEOUTL Switch",
++			    SUN20I_CODEC_DAC,
++			    SUN20I_CODEC_DAC_LINEOUTL_EN, 0,
++			    &sun20i_codec_line_out_switch),
++	SND_SOC_DAPM_SWITCH("LINEOUTR Switch",
++			    SUN20I_CODEC_DAC,
++			    SUN20I_CODEC_DAC_LINEOUTR_EN, 0,
++			    &sun20i_codec_line_out_switch),
++
++	SND_SOC_DAPM_OUTPUT("HPOUTL"),
++	SND_SOC_DAPM_OUTPUT("HPOUTR"),
++
++	SND_SOC_DAPM_SWITCH("HPOUTL Switch",
++			    SND_SOC_NOPM, 0, 0, &sun20i_codec_hp_switch),
++	SND_SOC_DAPM_SWITCH("HPOUTR Switch",
++			    SND_SOC_NOPM, 0, 0, &sun20i_codec_hp_switch),
++	SND_SOC_DAPM_SUPPLY("Headphone Driver",
++			    SUN20I_CODEC_HP2,
++			    SUN20I_CODEC_HP2_HP_DRVEN, 0, NULL, 0),
++
++	SND_SOC_DAPM_DAC("DACL", NULL,
++			 SUN20I_CODEC_DAC,
++			 SUN20I_CODEC_DAC_DACL_EN, 0),
++	SND_SOC_DAPM_DAC("DACR", NULL,
++			 SUN20I_CODEC_DAC,
++			 SUN20I_CODEC_DAC_DACR_EN, 0),
++	SND_SOC_DAPM_SUPPLY("DAC",
++			    SUN20I_CODEC_DAC_DPC,
++			    SUN20I_CODEC_DAC_DPC_EN_DA, 0, NULL, 0),
++
++	SND_SOC_DAPM_AIF_IN("DACL FIFO", "Playback", 0,
++			    SND_SOC_NOPM, 0, 0),
++	SND_SOC_DAPM_AIF_IN("DACR FIFO", "Playback", 1,
++			    SND_SOC_NOPM, 0, 0),
++
++	/* Capture */
++	SND_SOC_DAPM_AIF_OUT("ADC1 FIFO", "Capture", 0,
++			     SND_SOC_NOPM, 0, 0),
++	SND_SOC_DAPM_AIF_OUT("ADC2 FIFO", "Capture", 1,
++			     SND_SOC_NOPM, 0, 0),
++	SND_SOC_DAPM_AIF_OUT("ADC3 FIFO", "Capture", 2,
++			     SND_SOC_NOPM, 0, 0),
++
++	SND_SOC_DAPM_ADC("ADC1", NULL,
++			 SUN20I_CODEC_ADC1,
++			 SUN20I_CODEC_ADC1_ADC1_EN, 0),
++	SND_SOC_DAPM_ADC("ADC2", NULL,
++			 SUN20I_CODEC_ADC2,
++			 SUN20I_CODEC_ADC2_ADC2_EN, 0),
++	SND_SOC_DAPM_ADC("ADC3", NULL,
++			 SUN20I_CODEC_ADC3,
++			 SUN20I_CODEC_ADC3_ADC3_EN, 0),
++	SND_SOC_DAPM_SUPPLY("ADC",
++			    SUN20I_CODEC_ADC_FIFOC,
++			    SUN20I_CODEC_ADC_FIFOC_EN_AD, 0, NULL, 0),
++
++	SND_SOC_DAPM_MIXER_NAMED_CTL("ADC1 Mixer", SND_SOC_NOPM, 0, 0,
++				     sun20i_codec_adc12_mixer_controls, 3),
++	SND_SOC_DAPM_MIXER_NAMED_CTL("ADC2 Mixer", SND_SOC_NOPM, 0, 0,
++				     sun20i_codec_adc12_mixer_controls + 1, 3),
++	SND_SOC_DAPM_MIXER_NAMED_CTL("ADC3 Mixer", SND_SOC_NOPM, 0, 0,
++				     sun20i_codec_adc3_mixer_controls,
++				     ARRAY_SIZE(sun20i_codec_adc3_mixer_controls)),
++
++	SND_SOC_DAPM_PGA("Mic1",
++			 SUN20I_CODEC_ADC1,
++			 SUN20I_CODEC_ADC1_MICIN1_PGA_EN, 0,
++			 &sun20i_codec_mic1_volume, 1),
++	SND_SOC_DAPM_PGA("Mic2",
++			 SUN20I_CODEC_ADC2,
++			 SUN20I_CODEC_ADC2_MICIN2_PGA_EN, 0,
++			 &sun20i_codec_mic2_volume, 1),
++	SND_SOC_DAPM_PGA("Mic3",
++			 SUN20I_CODEC_ADC3,
++			 SUN20I_CODEC_ADC3_MICIN3_PGA_EN, 0,
++			 &sun20i_codec_mic3_volume, 1),
++
++	SND_SOC_DAPM_INPUT("MICIN1"),
++	SND_SOC_DAPM_INPUT("MICIN2"),
++	SND_SOC_DAPM_INPUT("MICIN3"),
++
++	SND_SOC_DAPM_INPUT("FMINL"),
++	SND_SOC_DAPM_INPUT("FMINR"),
++
++	SND_SOC_DAPM_INPUT("LINEINL"),
++	SND_SOC_DAPM_INPUT("LINEINR"),
++
++	SND_SOC_DAPM_SUPPLY("HBIAS",
++			    SUN20I_CODEC_MICBIAS,
++			    SUN20I_CODEC_MICBIAS_HMICBIASEN, 0, NULL, 0),
++	SND_SOC_DAPM_SUPPLY("MBIAS",
++			    SUN20I_CODEC_MICBIAS,
++			    SUN20I_CODEC_MICBIAS_MMICBIASEN, 0, NULL, 0),
++
++	SND_SOC_DAPM_REGULATOR_SUPPLY("avcc", 0, 0),
++	SND_SOC_DAPM_REGULATOR_SUPPLY("hpvcc", 0, 0),
++	SND_SOC_DAPM_REGULATOR_SUPPLY("vdd33", 0, 0),
++};
++
++static const struct snd_soc_dapm_route sun20i_codec_routes[] = {
++	/* Playback */
++	{ "LINEOUTL", NULL, "LINEOUTL Switch" },
++	{ "LINEOUTR", NULL, "LINEOUTR Switch" },
++
++	{ "LINEOUTL Switch", "Line Out Playback Switch", "DACL" },
++	{ "LINEOUTR Switch", "Line Out Playback Switch", "DACR" },
++
++	{ "HPOUTL", NULL, "HPOUTL Switch" },
++	{ "HPOUTR", NULL, "HPOUTR Switch" },
++
++	{ "HPOUTL Switch", "Headphone Playback Switch", "DACL" },
++	{ "HPOUTR Switch", "Headphone Playback Switch", "DACR" },
++	{ "HPOUTL Switch", NULL, "Headphone Driver" },
++	{ "HPOUTR Switch", NULL, "Headphone Driver" },
++	{ "Headphone Driver", NULL, "hpvcc" },
++
++	{ "DACL", NULL, "DACL FIFO" },
++	{ "DACR", NULL, "DACR FIFO" },
++	{ "DACL", NULL, "DAC" },
++	{ "DACR", NULL, "DAC" },
++	{ "DACL", NULL, "avcc" },
++	{ "DACR", NULL, "avcc" },
++
++	/* Capture */
++	{ "ADC1 FIFO", NULL, "ADC1" },
++	{ "ADC2 FIFO", NULL, "ADC2" },
++	{ "ADC3 FIFO", NULL, "ADC3" },
++
++	{ "ADC1", NULL, "ADC1 Mixer" },
++	{ "ADC2", NULL, "ADC2 Mixer" },
++	{ "ADC3", NULL, "ADC3 Mixer" },
++	{ "ADC1", NULL, "ADC" },
++	{ "ADC2", NULL, "ADC" },
++	{ "ADC3", NULL, "ADC" },
++	{ "ADC1", NULL, "avcc" },
++	{ "ADC2", NULL, "avcc" },
++	{ "ADC3", NULL, "avcc" },
++
++	{ "ADC1 Mixer", "Mic1 Capture Switch", "Mic1" },
++	{ "ADC2 Mixer", "Mic2 Capture Switch", "Mic2" },
++	{ "ADC3 Mixer", "Mic3 Capture Switch", "Mic3" },
++	{ "ADC1 Mixer", "FM Capture Switch", "FMINL" },
++	{ "ADC2 Mixer", "FM Capture Switch", "FMINR" },
++	{ "ADC1 Mixer", "Line In Capture Switch", "LINEINL" },
++	{ "ADC2 Mixer", "Line In Capture Switch", "LINEINR" },
++
++	{ "Mic1", NULL, "MICIN1" },
++	{ "Mic2", NULL, "MICIN2" },
++	{ "Mic3", NULL, "MICIN3" },
++
++	{ "HBIAS", NULL, "vdd33" },
++	{ "MBIAS", NULL, "vdd33" },
++};
++
++static int sun20i_codec_component_probe(struct snd_soc_component *component)
++{
++	struct sun20i_codec *codec = snd_soc_component_get_drvdata(component);
++	int ret;
++
++	ret = reset_control_deassert(codec->reset);
++	if (ret)
++		return ret;
++
++	ret = clk_prepare_enable(codec->bus_clk);
++	if (ret)
++		goto err_assert_reset;
++
++	/* Enable digital volume control. */
++	snd_soc_component_update_bits(component, SUN20I_CODEC_DAC_VOL_CTRL,
++				      0x1 << SUN20I_CODEC_DAC_VOL_CTRL_DAC_VOL_SEL,
++				      0x1 << SUN20I_CODEC_DAC_VOL_CTRL_DAC_VOL_SEL);
++	snd_soc_component_update_bits(component, SUN20I_CODEC_ADC_DIG_CTRL,
++				      0x3 << SUN20I_CODEC_ADC_DIG_CTRL_ADC_VOL_EN,
++				      0x3 << SUN20I_CODEC_ADC_DIG_CTRL_ADC_VOL_EN);
++
++	return 0;
++
++err_assert_reset:
++	reset_control_assert(codec->reset);
++
++	return ret;
++}
++
++static void sun20i_codec_component_remove(struct snd_soc_component *component)
++{
++	struct sun20i_codec *codec = snd_soc_component_get_drvdata(component);
++
++	clk_disable_unprepare(codec->bus_clk);
++	reset_control_assert(codec->reset);
++}
++
++static const struct snd_soc_component_driver sun20i_codec_component = {
++	.controls		= sun20i_codec_controls,
++	.num_controls		= ARRAY_SIZE(sun20i_codec_controls),
++	.dapm_widgets		= sun20i_codec_widgets,
++	.num_dapm_widgets	= ARRAY_SIZE(sun20i_codec_widgets),
++	.dapm_routes		= sun20i_codec_routes,
++	.num_dapm_routes	= ARRAY_SIZE(sun20i_codec_routes),
++	.probe			= sun20i_codec_component_probe,
++	.remove			= sun20i_codec_component_remove,
++};
++
++static int sun20i_codec_init_card(struct device *dev,
++				  struct sun20i_codec *codec)
++{
++	struct snd_soc_dai_link *dai_link = &codec->dai_link;
++	struct snd_soc_card *card = &codec->card;
++	int ret;
++
++	codec->dlcs[0].of_node	= dev->of_node;
++	codec->dlcs[0].dai_name	= DRIVER_NAME;
++	codec->dlcs[1].name	= "snd-soc-dummy";
++	codec->dlcs[1].dai_name	= "snd-soc-dummy-dai";
++	codec->dlcs[2].of_node	= dev->of_node;
++
++	dai_link->name		= DRIVER_NAME;
++	dai_link->stream_name	= DRIVER_NAME;
++	dai_link->cpus		= &codec->dlcs[0];
++	dai_link->num_cpus	= 1;
++	dai_link->codecs	= &codec->dlcs[1];
++	dai_link->num_codecs	= 1;
++	dai_link->platforms	= &codec->dlcs[2];
++	dai_link->num_platforms	= 1;
++
++	card->name		= DRIVER_NAME;
++	card->dev		= dev;
++	card->owner		= THIS_MODULE;
++	card->dai_link		= dai_link;
++	card->num_links		= 1;
++	card->fully_routed	= true;
++
++	ret = snd_soc_of_parse_aux_devs(card, "aux-devs");
++	if (ret)
++		return ret;
++
++	ret = snd_soc_of_parse_pin_switches(card, "pin-switches");
++	if (ret)
++		return ret;
++
++	ret = snd_soc_of_parse_audio_routing(card, "routing");
++	if (ret)
++		return ret;
++
++	ret = snd_soc_of_parse_audio_simple_widgets(card, "widgets");
++	if (ret)
++		return ret;
++
++	return 0;
++}
++
++static const struct regmap_config sun20i_codec_regmap_config = {
++	.reg_bits		= 32,
++	.reg_stride		= 4,
++	.val_bits		= 32,
++	.max_register		= SUN20I_CODEC_ADC_CUR,
++};
++
++static int sun20i_codec_probe(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct sun20i_codec *codec;
++	struct regmap *regmap;
++	struct resource *res;
++	void __iomem *base;
++	int ret;
++
++	codec = devm_kzalloc(dev, sizeof(*codec), GFP_KERNEL);
++	if (!codec)
++		return -ENOMEM;
++
++	dev_set_drvdata(dev, codec);
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	base = devm_ioremap_resource(dev, res);
++	if (IS_ERR(base))
++		return dev_err_probe(dev, PTR_ERR(base),
++				     "Failed to map registers\n");
++
++	regmap = devm_regmap_init_mmio(dev, base,
++				       &sun20i_codec_regmap_config);
++	if (IS_ERR(regmap))
++		return dev_err_probe(dev, PTR_ERR(regmap),
++				     "Failed to create regmap\n");
++
++	codec->bus_clk = devm_clk_get(dev, "bus");
++	if (IS_ERR(codec->bus_clk))
++		return dev_err_probe(dev, PTR_ERR(codec->bus_clk),
++				     "Failed to get bus clock\n");
++
++	codec->adc_clk = devm_clk_get(dev, "adc");
++	if (IS_ERR(codec->adc_clk))
++		return dev_err_probe(dev, PTR_ERR(codec->adc_clk),
++				     "Failed to get ADC clock\n");
++
++	codec->dac_clk = devm_clk_get(dev, "dac");
++	if (IS_ERR(codec->dac_clk))
++		return dev_err_probe(dev, PTR_ERR(codec->dac_clk),
++				     "Failed to get DAC clock\n");
++
++	codec->reset = devm_reset_control_get_exclusive(dev, NULL);
++	if (IS_ERR(codec->reset))
++		return dev_err_probe(dev, PTR_ERR(codec->reset),
++				     "Failed to get reset\n");
++
++	ret = devm_snd_soc_register_component(dev, &sun20i_codec_component,
++					      &sun20i_codec_dai, 1);
++	if (ret)
++		return dev_err_probe(dev, ret, "Failed to register component\n");
++
++	codec->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr =
++			res->start + SUN20I_CODEC_DAC_TXDATA;
++	codec->dma_data[SNDRV_PCM_STREAM_PLAYBACK].maxburst = 8;
++	codec->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr =
++			res->start + SUN20I_CODEC_ADC_RXDATA;
++	codec->dma_data[SNDRV_PCM_STREAM_CAPTURE].maxburst = 8;
++
++	ret = devm_snd_dmaengine_pcm_register(dev, NULL, 0);
++	if (ret)
++		return dev_err_probe(dev, ret, "Failed to register PCM\n");
++
++	ret = sun20i_codec_init_card(dev, codec);
++	if (ret)
++		return dev_err_probe(dev, ret, "Failed to initialize card\n");
++
++	ret = devm_snd_soc_register_card(dev, &codec->card);
++	if (ret)
++		return dev_err_probe(dev, ret, "Failed to register card\n");
++
++	return 0;
++}
++
++static const struct of_device_id sun20i_codec_of_match[] = {
++	{ .compatible = "allwinner,sun20i-d1-codec" },
++	{}
++};
++MODULE_DEVICE_TABLE(of, sun20i_codec_of_match);
++
++static struct platform_driver sun20i_codec_driver = {
++	.driver	= {
++		.name		= DRIVER_NAME,
++		.of_match_table	= sun20i_codec_of_match,
++	},
++	.probe	= sun20i_codec_probe,
++};
++module_platform_driver(sun20i_codec_driver);
++
++MODULE_DESCRIPTION("Allwinner D1 (sun20i) codec driver");
++MODULE_AUTHOR("Samuel Holland <samuel@sholland.org>");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:sun20i-codec");
diff --git a/target/linux/d1/patches-6.1/0082-ASoC-sun20i-codec-What-is-this-ramp-thing.patch b/target/linux/d1/patches-6.1/0082-ASoC-sun20i-codec-What-is-this-ramp-thing.patch
new file mode 100644
index 00000000000000..d837c6afdca7d2
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0082-ASoC-sun20i-codec-What-is-this-ramp-thing.patch
@@ -0,0 +1,23 @@
+From 87a77f803f5038e3fc64f45d5142ea402512029a Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Wed, 23 Jun 2021 21:18:47 -0500
+Subject: [PATCH 082/117] ASoC: sun20i-codec: What is this ramp thing?
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ sound/soc/sunxi/sun20i-codec.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/sound/soc/sunxi/sun20i-codec.c
++++ b/sound/soc/sunxi/sun20i-codec.c
+@@ -709,6 +709,10 @@ static int sun20i_codec_component_probe(
+ 				      0x3 << SUN20I_CODEC_ADC_DIG_CTRL_ADC_VOL_EN,
+ 				      0x3 << SUN20I_CODEC_ADC_DIG_CTRL_ADC_VOL_EN);
+ 
++	/* Maaagic... */
++	snd_soc_component_update_bits(component, SUN20I_CODEC_RAMP,
++				      BIT(1) | BIT(0), BIT(0));
++
+ 	return 0;
+ 
+ err_assert_reset:
diff --git a/target/linux/d1/patches-6.1/0083-riscv-dts-allwinner-d1-Add-sound-cards-to-boards.patch b/target/linux/d1/patches-6.1/0083-riscv-dts-allwinner-d1-Add-sound-cards-to-boards.patch
new file mode 100644
index 00000000000000..b0f93c3a489ba9
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0083-riscv-dts-allwinner-d1-Add-sound-cards-to-boards.patch
@@ -0,0 +1,132 @@
+From 54b1030c72d74ba6390d62086cbfc6a511f58aa7 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Thu, 11 Aug 2022 00:39:42 -0500
+Subject: [PATCH 083/117] riscv: dts: allwinner: d1: Add sound cards to boards
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ .../sun20i-d1-common-regulators.dtsi          |  5 +++++
+ .../sun20i-d1-lichee-rv-86-panel.dtsi         | 21 +++++++++++++++++++
+ .../allwinner/sun20i-d1-lichee-rv-dock.dts    | 12 +++++++++++
+ .../boot/dts/allwinner/sun20i-d1-nezha.dts    | 12 +++++++++++
+ arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi  | 13 +++++++++++-
+ 5 files changed, 62 insertions(+), 1 deletion(-)
+
+--- a/arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi
++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi
+@@ -18,6 +18,11 @@
+ 	};
+ };
+ 
++&codec {
++	avcc-supply = <&reg_aldo>;
++	hpvcc-supply = <&reg_hpldo>;
++};
++
+ &lradc {
+ 	vref-supply = <&reg_aldo>;
+ };
+--- a/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel.dtsi
++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel.dtsi
+@@ -9,6 +9,12 @@
+ 		ethernet1 = &xr829;
+ 	};
+ 
++	audio_amplifier: audio-amplifier {
++		compatible = "simple-audio-amplifier";
++		enable-gpios = <&pio 1 10 GPIO_ACTIVE_HIGH>; /* PB10 */
++		sound-name-prefix = "Amplifier";
++	};
++
+ 	dmic_codec: dmic-codec {
+ 		compatible = "dmic-codec";
+ 		num-channels = <2>;
+@@ -51,6 +57,21 @@
+ 	};
+ };
+ 
++&codec {
++	aux-devs = <&audio_amplifier>;
++	routing = "Internal Speaker", "Amplifier OUTL",
++		  "Internal Speaker", "Amplifier OUTR",
++		  "Amplifier INL", "HPOUTL",
++		  "Amplifier INR", "HPOUTR",
++		  "LINEINL", "HPOUTL",
++		  "LINEINR", "HPOUTR",
++		  "MICIN3", "Internal Microphone",
++		  "Internal Microphone", "HBIAS";
++	widgets = "Microphone", "Internal Microphone",
++		  "Speaker", "Internal Speaker";
++	status = "okay";
++};
++
+ &dmic {
+ 	pinctrl-0 = <&dmic_pb11_d0_pin>, <&dmic_pe17_clk_pin>;
+ 	pinctrl-names = "default";
+--- a/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts
++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts
+@@ -48,6 +48,18 @@
+ 	};
+ };
+ 
++&codec {
++	routing = "Internal Speaker", "HPOUTL",
++		  "Internal Speaker", "HPOUTR",
++		  "LINEINL", "HPOUTL",
++		  "LINEINR", "HPOUTR",
++		  "MICIN3", "Internal Microphone",
++		  "Internal Microphone", "HBIAS";
++	widgets = "Microphone", "Internal Microphone",
++		  "Speaker", "Internal Speaker";
++	status = "okay";
++};
++
+ &dmic {
+ 	pinctrl-0 = <&dmic_pb11_d0_pin>, <&dmic_pe17_clk_pin>;
+ 	pinctrl-names = "default";
+--- a/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
+@@ -51,6 +51,18 @@
+ 	};
+ };
+ 
++&codec {
++	routing = "Headphone Jack", "HPOUTL",
++		  "Headphone Jack", "HPOUTR",
++		  "LINEINL", "HPOUTL",
++		  "LINEINR", "HPOUTR",
++		  "MICIN3", "Headset Microphone",
++		  "Headset Microphone", "HBIAS";
++	widgets = "Microphone", "Headset Microphone",
++		  "Headphone", "Headphone Jack";
++	status = "okay";
++};
++
+ &cpu0 {
+ 	cpu-supply = <&reg_vdd_cpu>;
+ };
+--- a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
+@@ -312,10 +312,21 @@
+ 		};
+ 
+ 		codec: audio-codec@2030000 {
+-			compatible = "simple-mfd", "syscon";
++			compatible = "allwinner,sun20i-d1-codec", "simple-mfd", "syscon";
+ 			reg = <0x2030000 0x1000>;
++			interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_AUDIO>,
++				 <&ccu CLK_AUDIO_ADC>,
++				 <&ccu CLK_AUDIO_DAC>,
++				 <&osc24M>,
++				 <&rtc CLK_OSC32K>;
++			clock-names = "bus", "adc", "dac", "hosc", "losc";
++			resets = <&ccu RST_BUS_AUDIO>;
++			dmas = <&dma 7>, <&dma 7>;
++			dma-names = "rx", "tx";
+ 			#address-cells = <1>;
+ 			#size-cells = <1>;
++			#sound-dai-cells = <0>;
+ 
+ 			regulators@2030348 {
+ 				compatible = "allwinner,sun20i-d1-analog-ldos";
diff --git a/target/linux/d1/patches-6.1/0084-drm-sun4i-dsi-Allow-panel-attach-before-card-registr.patch b/target/linux/d1/patches-6.1/0084-drm-sun4i-dsi-Allow-panel-attach-before-card-registr.patch
new file mode 100644
index 00000000000000..e74ea35e5a7602
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0084-drm-sun4i-dsi-Allow-panel-attach-before-card-registr.patch
@@ -0,0 +1,39 @@
+From bae2790f627eb30ec3845167341b108e13328f6f Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 7 Aug 2022 10:46:43 -0500
+Subject: [PATCH 084/117] drm/sun4i: dsi: Allow panel attach before card
+ registration
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+--- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
++++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
+@@ -967,13 +967,12 @@ static int sun6i_dsi_attach(struct mipi_
+ 
+ 	if (IS_ERR(panel))
+ 		return PTR_ERR(panel);
+-	if (!dsi->drm || !dsi->drm->registered)
+-		return -EPROBE_DEFER;
+ 
+ 	dsi->panel = panel;
+ 	dsi->device = device;
+ 
+-	drm_kms_helper_hotplug_event(dsi->drm);
++	if (dsi->drm && dsi->drm->registered)
++		drm_kms_helper_hotplug_event(dsi->drm);
+ 
+ 	dev_info(host->dev, "Attached device %s\n", device->name);
+ 
+@@ -988,7 +987,8 @@ static int sun6i_dsi_detach(struct mipi_
+ 	dsi->panel = NULL;
+ 	dsi->device = NULL;
+ 
+-	drm_kms_helper_hotplug_event(dsi->drm);
++	if (dsi->drm && dsi->drm->registered)
++		drm_kms_helper_hotplug_event(dsi->drm);
+ 
+ 	return 0;
+ }
diff --git a/target/linux/d1/patches-6.1/0085-drm-sun4i-mixer-Remove-unused-CMA-headers.patch b/target/linux/d1/patches-6.1/0085-drm-sun4i-mixer-Remove-unused-CMA-headers.patch
new file mode 100644
index 00000000000000..ae47bbed2626cc
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0085-drm-sun4i-mixer-Remove-unused-CMA-headers.patch
@@ -0,0 +1,21 @@
+From 5755bea969adcb00b102271b0cbaa3002acd7a35 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Wed, 27 Apr 2022 18:50:01 -0500
+Subject: [PATCH 085/117] drm/sun4i: mixer: Remove unused CMA headers
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/gpu/drm/sun4i/sun8i_mixer.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+@@ -17,7 +17,7 @@
+ #include <drm/drm_atomic_helper.h>
+ #include <drm/drm_crtc.h>
+ #include <drm/drm_framebuffer.h>
+-#include <drm/drm_gem_dma_helper.h>
++#include <drm/drm_print.h>
+ #include <drm/drm_probe_helper.h>
+ 
+ #include "sun4i_drv.h"
diff --git a/target/linux/d1/patches-6.1/0086-drm-sun4i-decouple-TCON_DCLK_DIV-value-from-pll_mipi.patch b/target/linux/d1/patches-6.1/0086-drm-sun4i-decouple-TCON_DCLK_DIV-value-from-pll_mipi.patch
new file mode 100644
index 00000000000000..8a6015bc56a6cb
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0086-drm-sun4i-decouple-TCON_DCLK_DIV-value-from-pll_mipi.patch
@@ -0,0 +1,110 @@
+From 9a7acb8f03346705d7420a490d95b32309d90e22 Mon Sep 17 00:00:00 2001
+From: Roman Beranek <roman.beranek@prusa3d.com>
+Date: Wed, 25 Nov 2020 13:07:35 +0100
+Subject: [PATCH 086/117] drm/sun4i: decouple TCON_DCLK_DIV value from
+ pll_mipi/dotclock ratio
+
+Observations showed that an actual refresh rate differs from the intended.
+Specifically, in case of 4-lane panels it was reduced by 1/3, and in case of
+2-lane panels by 2/3.
+
+BSP code apparently distinguishes between a `dsi_div` and a 'tcon inner div'.
+While this 'inner' divider is under DSI always 4, the `dsi_div` is defined
+as a number of bits per pixel over a number of DSI lanes. This value is then
+involved in setting the rate of PLL_MIPI.
+
+I couldn't really figure out how to fit this into the dotclock driver,
+so I opted for this hack where the requested rate is adjusted in such a way
+that the sun4i_dotclock driver can remain untouched.
+
+Signed-off-by: Roman Beranek <roman.beranek@prusa3d.com>
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/gpu/drm/sun4i/sun4i_tcon.c | 44 +++++++++++++++++-------------
+ 1 file changed, 25 insertions(+), 19 deletions(-)
+
+--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
++++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
+@@ -291,18 +291,6 @@ static int sun4i_tcon_get_clk_delay(cons
+ 	return delay;
+ }
+ 
+-static void sun4i_tcon0_mode_set_common(struct sun4i_tcon *tcon,
+-					const struct drm_display_mode *mode)
+-{
+-	/* Configure the dot clock */
+-	clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
+-
+-	/* Set the resolution */
+-	regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
+-		     SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) |
+-		     SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay));
+-}
+-
+ static void sun4i_tcon0_mode_set_dithering(struct sun4i_tcon *tcon,
+ 					   const struct drm_connector *connector)
+ {
+@@ -365,12 +353,18 @@ static void sun4i_tcon0_mode_set_cpu(str
+ 	u8 bpp = mipi_dsi_pixel_format_to_bpp(device->format);
+ 	u8 lanes = device->lanes;
+ 	u32 block_space, start_delay;
+-	u32 tcon_div;
+ 
+ 	tcon->dclk_min_div = SUN6I_DSI_TCON_DIV;
+ 	tcon->dclk_max_div = SUN6I_DSI_TCON_DIV;
+ 
+-	sun4i_tcon0_mode_set_common(tcon, mode);
++	/* Configure the dot clock */
++	clk_set_rate(tcon->dclk, mode->crtc_clock * 1000
++				 * bpp / (lanes * SUN6I_DSI_TCON_DIV));
++
++        /* Set the resolution */
++	regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
++		     SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) |
++		     SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay));
+ 
+ 	/* Set dithering if needed */
+ 	sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder));
+@@ -394,9 +388,7 @@ static void sun4i_tcon0_mode_set_cpu(str
+ 	 * The datasheet says that this should be set higher than 20 *
+ 	 * pixel cycle, but it's not clear what a pixel cycle is.
+ 	 */
+-	regmap_read(tcon->regs, SUN4I_TCON0_DCLK_REG, &tcon_div);
+-	tcon_div &= GENMASK(6, 0);
+-	block_space = mode->htotal * bpp / (tcon_div * lanes);
++	block_space = mode->htotal * bpp / (SUN6I_DSI_TCON_DIV * lanes);
+ 	block_space -= mode->hdisplay + 40;
+ 
+ 	regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI0_REG,
+@@ -438,7 +430,14 @@ static void sun4i_tcon0_mode_set_lvds(st
+ 
+ 	tcon->dclk_min_div = 7;
+ 	tcon->dclk_max_div = 7;
+-	sun4i_tcon0_mode_set_common(tcon, mode);
++
++	/* Configure the dot clock */
++	clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
++
++        /* Set the resolution */
++	regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
++		     SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) |
++		     SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay));
+ 
+ 	/* Set dithering if needed */
+ 	sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder));
+@@ -515,7 +514,14 @@ static void sun4i_tcon0_mode_set_rgb(str
+ 
+ 	tcon->dclk_min_div = tcon->quirks->dclk_min_div;
+ 	tcon->dclk_max_div = 127;
+-	sun4i_tcon0_mode_set_common(tcon, mode);
++
++	/* Configure the dot clock */
++	clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
++
++	/* Set the resolution */
++	regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
++		     SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) |
++		     SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay));
+ 
+ 	/* Set dithering if needed */
+ 	sun4i_tcon0_mode_set_dithering(tcon, connector);
diff --git a/target/linux/d1/patches-6.1/0087-drm-sun4i-tcon-Always-protect-the-LCD-dotclock-rate.patch b/target/linux/d1/patches-6.1/0087-drm-sun4i-tcon-Always-protect-the-LCD-dotclock-rate.patch
new file mode 100644
index 00000000000000..7e404eecd1d767
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0087-drm-sun4i-tcon-Always-protect-the-LCD-dotclock-rate.patch
@@ -0,0 +1,57 @@
+From 9ea0c216d4f85a8ea888a38853e9573bbd9e995a Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 7 Aug 2022 21:09:39 -0500
+Subject: [PATCH 087/117] drm/sun4i: tcon: Always protect the LCD dotclock rate
+
+This handles the case where multiple CRTCs get their .mode_set function
+called during the same atomic commit, before rate protection is applied
+by enabling the CRTC.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/gpu/drm/sun4i/sun4i_dotclock.c | 4 ++++
+ drivers/gpu/drm/sun4i/sun4i_tcon.c     | 6 ++++--
+ 2 files changed, 8 insertions(+), 2 deletions(-)
+
+--- a/drivers/gpu/drm/sun4i/sun4i_dotclock.c
++++ b/drivers/gpu/drm/sun4i/sun4i_dotclock.c
+@@ -6,6 +6,7 @@
+  * Maxime Ripard <maxime.ripard@free-electrons.com>
+  */
+ 
++#include <linux/clk.h>
+ #include <linux/clk-provider.h>
+ #include <linux/regmap.h>
+ 
+@@ -194,12 +195,15 @@ int sun4i_dclk_create(struct device *dev
+ 	if (IS_ERR(tcon->dclk))
+ 		return PTR_ERR(tcon->dclk);
+ 
++	clk_rate_exclusive_get(tcon->dclk);
++
+ 	return 0;
+ }
+ EXPORT_SYMBOL(sun4i_dclk_create);
+ 
+ int sun4i_dclk_free(struct sun4i_tcon *tcon)
+ {
++	clk_rate_exclusive_put(tcon->dclk);
+ 	clk_unregister(tcon->dclk);
+ 	return 0;
+ }
+--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
++++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
+@@ -108,9 +108,11 @@ static void sun4i_tcon_channel_set_statu
+ 
+ 	if (enabled) {
+ 		clk_prepare_enable(clk);
+-		clk_rate_exclusive_get(clk);
++		if (clk != tcon->dclk)
++			clk_rate_exclusive_get(clk);
+ 	} else {
+-		clk_rate_exclusive_put(clk);
++		if (clk != tcon->dclk)
++			clk_rate_exclusive_put(clk);
+ 		clk_disable_unprepare(clk);
+ 	}
+ }
diff --git a/target/linux/d1/patches-6.1/0088-drm-sun4i-tcon_top-Register-reset-clock-gates-in-pro.patch b/target/linux/d1/patches-6.1/0088-drm-sun4i-tcon_top-Register-reset-clock-gates-in-pro.patch
new file mode 100644
index 00000000000000..fae19b8087072e
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0088-drm-sun4i-tcon_top-Register-reset-clock-gates-in-pro.patch
@@ -0,0 +1,113 @@
+From f792492db1f42c43eb4b8bb72ce573418afc933d Mon Sep 17 00:00:00 2001
+From: Jagan Teki <jagan@amarulasolutions.com>
+Date: Tue, 31 Dec 2019 18:35:24 +0530
+Subject: [PATCH 088/117] drm/sun4i: tcon_top: Register reset, clock gates in
+ probe
+
+TCON TOP is processing clock gates and reset control for
+TV0, TV1 and DSI channels during bind and release the same
+during unbind component ops.
+
+The usual DSI initialization would setup all controller
+clocks along with DPHY clocking during probe.
+
+Since the actual clock gates (along with DSI clock gate)
+are initialized during ton top bind, the DPHY is failed to
+get the DSI clock during that time.
+
+To solve, this circular dependency move the reset control,
+clock gate registration from bind to probe and release the
+same from unbind to remove.
+
+This eventually give a chance DPHY to initialize the DSI
+clock gate.
+
+Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/gpu/drm/sun4i/sun8i_tcon_top.c | 42 ++++++++++++++------------
+ 1 file changed, 22 insertions(+), 20 deletions(-)
+
+--- a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
++++ b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
+@@ -124,14 +124,29 @@ static struct clk_hw *sun8i_tcon_top_reg
+ static int sun8i_tcon_top_bind(struct device *dev, struct device *master,
+ 			       void *data)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
++	return 0;
++}
++
++static void sun8i_tcon_top_unbind(struct device *dev, struct device *master,
++				  void *data)
++{
++}
++
++static const struct component_ops sun8i_tcon_top_ops = {
++	.bind	= sun8i_tcon_top_bind,
++	.unbind	= sun8i_tcon_top_unbind,
++};
++
++static int sun8i_tcon_top_probe(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
+ 	struct clk_hw_onecell_data *clk_data;
+ 	struct sun8i_tcon_top *tcon_top;
+ 	const struct sun8i_tcon_top_quirks *quirks;
+ 	void __iomem *regs;
+ 	int ret, i;
+ 
+-	quirks = of_device_get_match_data(&pdev->dev);
++	quirks = of_device_get_match_data(dev);
+ 
+ 	tcon_top = devm_kzalloc(dev, sizeof(*tcon_top), GFP_KERNEL);
+ 	if (!tcon_top)
+@@ -222,7 +237,7 @@ static int sun8i_tcon_top_bind(struct de
+ 
+ 	dev_set_drvdata(dev, tcon_top);
+ 
+-	return 0;
++	return component_add(dev, &sun8i_tcon_top_ops);
+ 
+ err_unregister_gates:
+ 	for (i = 0; i < CLK_NUM; i++)
+@@ -235,13 +250,15 @@ err_assert_reset:
+ 	return ret;
+ }
+ 
+-static void sun8i_tcon_top_unbind(struct device *dev, struct device *master,
+-				  void *data)
++static int sun8i_tcon_top_remove(struct platform_device *pdev)
+ {
++	struct device *dev = &pdev->dev;
+ 	struct sun8i_tcon_top *tcon_top = dev_get_drvdata(dev);
+ 	struct clk_hw_onecell_data *clk_data = tcon_top->clk_data;
+ 	int i;
+ 
++	component_del(dev, &sun8i_tcon_top_ops);
++
+ 	of_clk_del_provider(dev->of_node);
+ 	for (i = 0; i < CLK_NUM; i++)
+ 		if (clk_data->hws[i])
+@@ -249,21 +266,6 @@ static void sun8i_tcon_top_unbind(struct
+ 
+ 	clk_disable_unprepare(tcon_top->bus);
+ 	reset_control_assert(tcon_top->rst);
+-}
+-
+-static const struct component_ops sun8i_tcon_top_ops = {
+-	.bind	= sun8i_tcon_top_bind,
+-	.unbind	= sun8i_tcon_top_unbind,
+-};
+-
+-static int sun8i_tcon_top_probe(struct platform_device *pdev)
+-{
+-	return component_add(&pdev->dev, &sun8i_tcon_top_ops);
+-}
+-
+-static int sun8i_tcon_top_remove(struct platform_device *pdev)
+-{
+-	component_del(&pdev->dev, &sun8i_tcon_top_ops);
+ 
+ 	return 0;
+ }
diff --git a/target/linux/d1/patches-6.1/0089-riscv-dts-allwinner-lichee-rv-86-panel-480p-Add-pane.patch b/target/linux/d1/patches-6.1/0089-riscv-dts-allwinner-lichee-rv-86-panel-480p-Add-pane.patch
new file mode 100644
index 00000000000000..ce7510d1564c52
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0089-riscv-dts-allwinner-lichee-rv-86-panel-480p-Add-pane.patch
@@ -0,0 +1,75 @@
+From 03dbb926f6d65f75af902e421c44aeaaf84be66a Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Thu, 11 Aug 2022 22:46:28 -0500
+Subject: [PATCH 089/117] riscv: dts: allwinner: lichee-rv-86-panel-480p: Add
+ panel
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ .../sun20i-d1-lichee-rv-86-panel-480p.dts     | 51 +++++++++++++++++++
+ 1 file changed, 51 insertions(+)
+
+--- a/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-480p.dts
++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-480p.dts
+@@ -7,6 +7,40 @@
+ 	model = "Sipeed Lichee RV 86 Panel (480p)";
+ 	compatible = "sipeed,lichee-rv-86-panel-480p", "sipeed,lichee-rv",
+ 		     "allwinner,sun20i-d1";
++
++	backlight: backlight {
++		compatible = "pwm-backlight";
++		power-supply = <&reg_vcc>;
++		pwms = <&pwm 7 50000 0>;
++	};
++
++	spi {
++		compatible = "spi-gpio";
++		cs-gpios = <&pio 4 14 GPIO_ACTIVE_LOW>; /* PE14 */
++		mosi-gpios = <&pio 4 12 GPIO_ACTIVE_HIGH>; /* PE12 */
++		sck-gpios = <&pio 4 15 GPIO_ACTIVE_HIGH>; /* PE15 */
++		num-chipselects = <1>;
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		panel@0 {
++			compatible = "sitronix,st7701s";
++			reg = <0>;
++			backlight = <&backlight>;
++			reset-gpios = <&pio 6 13 GPIO_ACTIVE_LOW>; /* PG13 */
++			spi-3wire;
++
++			port {
++				panel_in_tcon_lcd0: endpoint {
++					remote-endpoint = <&tcon_lcd0_out_panel>;
++				};
++			};
++		};
++	};
++};
++
++&de {
++	status = "okay";
+ };
+ 
+ &i2c2 {
+@@ -27,3 +61,20 @@
+ 		wakeup-source;
+ 	};
+ };
++
++&pwm {
++	pinctrl-0 = <&pwm7_pd22_pin>;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
++&tcon_lcd0 {
++	pinctrl-0 = <&lcd_rgb666_pins>;
++	pinctrl-names = "default";
++};
++
++&tcon_lcd0_out {
++	tcon_lcd0_out_panel: endpoint {
++		remote-endpoint = <&panel_in_tcon_lcd0>;
++	};
++};
diff --git a/target/linux/d1/patches-6.1/0090-riscv-dts-allwinner-d1-Add-DSI-pipeline.patch b/target/linux/d1/patches-6.1/0090-riscv-dts-allwinner-d1-Add-DSI-pipeline.patch
new file mode 100644
index 00000000000000..e6e992b9e6bcec
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0090-riscv-dts-allwinner-d1-Add-DSI-pipeline.patch
@@ -0,0 +1,82 @@
+From 4c72279c90469971ca5ec627a76e50bf51bf076f Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 7 Aug 2022 10:59:29 -0500
+Subject: [PATCH 090/117] riscv: dts: allwinner: d1: Add DSI pipeline
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 49 ++++++++++++++++++++
+ 1 file changed, 49 insertions(+)
+
+--- a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
+@@ -124,6 +124,14 @@
+ 			#interrupt-cells = <3>;
+ 
+ 			/omit-if-no-ref/
++			dsi_4lane_pins: dsi-4lane-pins {
++				pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
++				       "PD6", "PD7", "PD8", "PD9";
++				drive-strength = <30>;
++				function = "dsi";
++			};
++
++			/omit-if-no-ref/
+ 			i2c0_pb10_pins: i2c0-pb10-pins {
+ 				pins = "PB10", "PB11";
+ 				function = "i2c0";
+@@ -903,6 +911,40 @@
+ 			};
+ 		};
+ 
++		dsi: dsi@5450000 {
++			compatible = "allwinner,sun20i-d1-mipi-dsi",
++				     "allwinner,sun50i-a100-mipi-dsi";
++			reg = <0x5450000 0x1000>;
++			interrupts = <108 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_MIPI_DSI>,
++				 <&tcon_top CLK_TCON_TOP_DSI>;
++			clock-names = "bus", "mod";
++			resets = <&ccu RST_BUS_MIPI_DSI>;
++			phys = <&dphy>;
++			phy-names = "dphy";
++			status = "disabled";
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			port {
++				dsi_in_tcon_lcd0: endpoint {
++					remote-endpoint = <&tcon_lcd0_out_dsi>;
++				};
++			};
++		};
++
++		dphy: phy@5451000 {
++			compatible = "allwinner,sun20i-d1-mipi-dphy",
++				     "allwinner,sun50i-a100-mipi-dphy";
++			reg = <0x5451000 0x1000>;
++			interrupts = <108 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_MIPI_DSI>,
++				 <&ccu CLK_MIPI_DSI>;
++			clock-names = "bus", "mod";
++			resets = <&ccu RST_BUS_MIPI_DSI>;
++			#phy-cells = <0>;
++		};
++
+ 		tcon_top: tcon-top@5460000 {
+ 			compatible = "allwinner,sun20i-d1-tcon-top";
+ 			reg = <0x5460000 0x1000>;
+@@ -1022,6 +1064,13 @@
+ 
+ 				tcon_lcd0_out: port@1 {
+ 					reg = <1>;
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					tcon_lcd0_out_dsi: endpoint@1 {
++						reg = <1>;
++						remote-endpoint = <&dsi_in_tcon_lcd0>;
++					};
+ 				};
+ 			};
+ 		};
diff --git a/target/linux/d1/patches-6.1/0091-riscv-dts-allwinner-devterm-Add-DSI-panel-and-backli.patch b/target/linux/d1/patches-6.1/0091-riscv-dts-allwinner-devterm-Add-DSI-panel-and-backli.patch
new file mode 100644
index 00000000000000..60855f0f1c2e76
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0091-riscv-dts-allwinner-devterm-Add-DSI-panel-and-backli.patch
@@ -0,0 +1,62 @@
+From 7ac17ab7ea644ec27935865d6d0208ecc7fd4ed9 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Thu, 11 Aug 2022 22:29:03 -0500
+Subject: [PATCH 091/117] riscv: dts: allwinner: devterm: Add DSI panel and
+ backlight
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ .../allwinner/sun20i-d1-clockworkpi-v3.14.dts |  8 +++++++-
+ .../dts/allwinner/sun20i-d1-devterm-v3.14.dts | 20 +++++++++++++++++++
+ 2 files changed, 27 insertions(+), 1 deletion(-)
+
+--- a/arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts
++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts
+@@ -48,6 +48,12 @@
+ 		};
+ 	};
+ 
++	backlight: backlight {
++		compatible = "pwm-backlight";
++		power-supply = <&reg_vcc>;
++		pwms = <&pwm 4 50000 0>; /* PD20/GPIO9 */
++	};
++
+ 	reg_vdd_cpu: vdd-cpu {
+ 		compatible = "pwm-regulator";
+ 		pwms = <&pwm 0 50000 0>;
+@@ -252,7 +258,7 @@
+ };
+ 
+ &pwm {
+-	pinctrl-0 = <&pwm0_pd16_pin>;
++	pinctrl-0 = <&pwm0_pd16_pin>, <&pwm4_pd20_pin>;
+ 	pinctrl-names = "default";
+ 	status = "okay";
+ };
+--- a/arch/riscv/boot/dts/allwinner/sun20i-d1-devterm-v3.14.dts
++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-devterm-v3.14.dts
+@@ -35,3 +35,23 @@
+ 		};
+ 	};
+ };
++
++&de {
++	status = "okay";
++};
++
++&dsi {
++	pinctrl-0 = <&dsi_4lane_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++
++	panel@0 {
++		compatible = "clockwork,cwd686";
++		reg = <0>;
++		backlight = <&backlight>;
++		reset-gpios = <&pio 3 19 GPIO_ACTIVE_LOW>; /* PD19/GPIO8 */
++		rotation = <90>;
++		iovcc-supply = <&reg_dcdc3>;
++		vci-supply = <&reg_aldo2>;
++	};
++};
diff --git a/target/linux/d1/patches-6.1/0092-dt-bindings-display-sun4i-tcon-Add-external-LVDS-PHY.patch b/target/linux/d1/patches-6.1/0092-dt-bindings-display-sun4i-tcon-Add-external-LVDS-PHY.patch
new file mode 100644
index 00000000000000..a8c6b685cd6232
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0092-dt-bindings-display-sun4i-tcon-Add-external-LVDS-PHY.patch
@@ -0,0 +1,29 @@
+From 822fdc3556b688103cdaf7b4b34e98fbe1676425 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 7 Aug 2022 10:58:02 -0500
+Subject: [PATCH 092/117] dt-bindings: display: sun4i-tcon: Add external LVDS
+ PHY
+
+A100 and D1 use the same "combo" PHY for LVDS0 and DSI.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ .../bindings/display/allwinner,sun4i-a10-tcon.yaml         | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+--- a/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml
++++ b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml
+@@ -80,6 +80,13 @@ properties:
+   dmas:
+     maxItems: 1
+ 
++  phys:
++    maxItems: 1
++
++  phy-names:
++    items:
++      - const: "lvds0"
++
+   resets:
+     anyOf:
+       - items:
diff --git a/target/linux/d1/patches-6.1/0093-riscv-dts-allwinner-d1-Add-LVDS0-PHY.patch b/target/linux/d1/patches-6.1/0093-riscv-dts-allwinner-d1-Add-LVDS0-PHY.patch
new file mode 100644
index 00000000000000..f80b125c6783f6
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0093-riscv-dts-allwinner-d1-Add-LVDS0-PHY.patch
@@ -0,0 +1,21 @@
+From 7d95f6b52ea5f01c9e2414d4984e5a274328c021 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 7 Aug 2022 10:58:57 -0500
+Subject: [PATCH 093/117] riscv: dts: allwinner: d1: Add LVDS0 PHY
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
+@@ -1040,6 +1040,8 @@
+ 			resets = <&ccu RST_BUS_TCON_LCD0>,
+ 				 <&ccu RST_BUS_LVDS0>;
+ 			reset-names = "lcd", "lvds";
++			phys = <&dphy>;
++			phy-names = "lvds0";
+ 			#clock-cells = <0>;
+ 
+ 			ports {
diff --git a/target/linux/d1/patches-6.1/0094-dt-bindings-display-sun6i-dsi-Fix-clock-conditional.patch b/target/linux/d1/patches-6.1/0094-dt-bindings-display-sun6i-dsi-Fix-clock-conditional.patch
new file mode 100644
index 00000000000000..60063102988636
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0094-dt-bindings-display-sun6i-dsi-Fix-clock-conditional.patch
@@ -0,0 +1,38 @@
+From d0f7ed9dc803e09fb6c1e895efbd1182c9212483 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 7 Aug 2022 10:49:30 -0500
+Subject: [PATCH 094/117] dt-bindings: display: sun6i-dsi: Fix clock
+ conditional
+
+The A64 case should have limited maxItems, instead of duplicating the
+minItems value from the main binding. While here, simplify the binding
+by making this an "else" case of the two-clock conditional block.
+
+Fixes: fe5040f2843a ("dt-bindings: sun6i-dsi: Document A64 MIPI-DSI controller")
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ .../bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml | 10 ++--------
+ 1 file changed, 2 insertions(+), 8 deletions(-)
+
+--- a/Documentation/devicetree/bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml
++++ b/Documentation/devicetree/bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml
+@@ -78,16 +78,10 @@ allOf:
+       required:
+         - clock-names
+ 
+-  - if:
+-      properties:
+-        compatible:
+-          contains:
+-            const: allwinner,sun50i-a64-mipi-dsi
+-
+-    then:
++    else:
+       properties:
+         clocks:
+-          minItems: 1
++          maxItems: 1
+ 
+ unevaluatedProperties: false
+ 
diff --git a/target/linux/d1/patches-6.1/0095-dt-bindings-display-sun6i-dsi-Add-the-A100-variant.patch b/target/linux/d1/patches-6.1/0095-dt-bindings-display-sun6i-dsi-Add-the-A100-variant.patch
new file mode 100644
index 00000000000000..325c2528a50f3f
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0095-dt-bindings-display-sun6i-dsi-Add-the-A100-variant.patch
@@ -0,0 +1,85 @@
+From 30abd0e5f27bc57fba7084ba51aca671316b6d24 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 7 Aug 2022 10:50:21 -0500
+Subject: [PATCH 095/117] dt-bindings: display: sun6i-dsi: Add the A100 variant
+
+The "40nm" MIPI DSI controller found in the A100 and D1 SoCs has the
+same register layout as previous SoC integrations. However, its module
+clock now comes from the TCON, which means it no longer runs at a fixed
+rate, so this needs to be distinguished in the driver.
+
+The controller also now uses pins on Port D instead of dedicated pins,
+so it drops the separate power domain.
+
+Commit-notes:
+Removal of the vcc-dsi-supply is maybe a bit questionable. Since there
+is no "VCC-DSI" pin anymore, it's not obvious which pin actually does
+power the DSI controller/PHY. Possibly power comes from VCC-PD or VCC-IO
+or VCC-LVDS. So far, all boards have all of these as always-on supplies,
+so it is hard to test.
+END
+
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ .../display/allwinner,sun6i-a31-mipi-dsi.yaml | 28 +++++++++++++++----
+ 1 file changed, 23 insertions(+), 5 deletions(-)
+
+--- a/Documentation/devicetree/bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml
++++ b/Documentation/devicetree/bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml
+@@ -12,9 +12,14 @@ maintainers:
+ 
+ properties:
+   compatible:
+-    enum:
+-      - allwinner,sun6i-a31-mipi-dsi
+-      - allwinner,sun50i-a64-mipi-dsi
++    oneOf:
++      - enum:
++          - allwinner,sun6i-a31-mipi-dsi
++          - allwinner,sun50i-a64-mipi-dsi
++          - allwinner,sun50i-a100-mipi-dsi
++      - items:
++          - const: allwinner,sun20i-d1-mipi-dsi
++          - const: allwinner,sun50i-a100-mipi-dsi
+ 
+   reg:
+     maxItems: 1
+@@ -59,7 +64,6 @@ required:
+   - phys
+   - phy-names
+   - resets
+-  - vcc-dsi-supply
+   - port
+ 
+ allOf:
+@@ -68,7 +72,9 @@ allOf:
+       properties:
+         compatible:
+           contains:
+-            const: allwinner,sun6i-a31-mipi-dsi
++            enum:
++              - allwinner,sun6i-a31-mipi-dsi
++              - allwinner,sun50i-a100-mipi-dsi
+ 
+     then:
+       properties:
+@@ -83,6 +89,18 @@ allOf:
+         clocks:
+           maxItems: 1
+ 
++  - if:
++      properties:
++        compatible:
++          contains:
++            enum:
++              - allwinner,sun6i-a31-mipi-dsi
++              - allwinner,sun50i-a64-mipi-dsi
++
++    then:
++      required:
++        - vcc-dsi-supply
++
+ unevaluatedProperties: false
+ 
+ examples:
diff --git a/target/linux/d1/patches-6.1/0096-drm-sun4i-dsi-Add-a-variant-structure.patch b/target/linux/d1/patches-6.1/0096-drm-sun4i-dsi-Add-a-variant-structure.patch
new file mode 100644
index 00000000000000..afe7a1ed428d18
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0096-drm-sun4i-dsi-Add-a-variant-structure.patch
@@ -0,0 +1,158 @@
+From 28e64e830ef487b400b3b943fa3bda83dfb2a937 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Tue, 9 Aug 2022 22:03:42 -0500
+Subject: [PATCH 096/117] drm/sun4i: dsi: Add a variant structure
+
+Replace the ad-hoc calls to of_device_is_compatible() with a structure
+describing the differences between variants. This is in preparation for
+adding more variants to the driver.
+
+Series-changes: 2
+ - Add the variant check to the probe error path
+
+Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 53 +++++++++++++++++---------
+ drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h |  7 ++++
+ 2 files changed, 42 insertions(+), 18 deletions(-)
+
+--- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
++++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
+@@ -1101,12 +1101,16 @@ static const struct component_ops sun6i_
+ 
+ static int sun6i_dsi_probe(struct platform_device *pdev)
+ {
++	const struct sun6i_dsi_variant *variant;
+ 	struct device *dev = &pdev->dev;
+-	const char *bus_clk_name = NULL;
+ 	struct sun6i_dsi *dsi;
+ 	void __iomem *base;
+ 	int ret;
+ 
++	variant = device_get_match_data(dev);
++	if (!variant)
++		return -EINVAL;
++
+ 	dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
+ 	if (!dsi)
+ 		return -ENOMEM;
+@@ -1114,10 +1118,7 @@ static int sun6i_dsi_probe(struct platfo
+ 	dsi->dev = dev;
+ 	dsi->host.ops = &sun6i_dsi_host_ops;
+ 	dsi->host.dev = dev;
+-
+-	if (of_device_is_compatible(dev->of_node,
+-				    "allwinner,sun6i-a31-mipi-dsi"))
+-		bus_clk_name = "bus";
++	dsi->variant = variant;
+ 
+ 	base = devm_platform_ioremap_resource(pdev, 0);
+ 	if (IS_ERR(base)) {
+@@ -1142,7 +1143,7 @@ static int sun6i_dsi_probe(struct platfo
+ 		return PTR_ERR(dsi->regs);
+ 	}
+ 
+-	dsi->bus_clk = devm_clk_get(dev, bus_clk_name);
++	dsi->bus_clk = devm_clk_get(dev, variant->has_mod_clk ? "bus" : NULL);
+ 	if (IS_ERR(dsi->bus_clk))
+ 		return dev_err_probe(dev, PTR_ERR(dsi->bus_clk),
+ 				     "Couldn't get the DSI bus clock\n");
+@@ -1151,21 +1152,21 @@ static int sun6i_dsi_probe(struct platfo
+ 	if (ret)
+ 		return ret;
+ 
+-	if (of_device_is_compatible(dev->of_node,
+-				    "allwinner,sun6i-a31-mipi-dsi")) {
++	if (variant->has_mod_clk) {
+ 		dsi->mod_clk = devm_clk_get(dev, "mod");
+ 		if (IS_ERR(dsi->mod_clk)) {
+ 			dev_err(dev, "Couldn't get the DSI mod clock\n");
+ 			ret = PTR_ERR(dsi->mod_clk);
+ 			goto err_attach_clk;
+ 		}
+-	}
+ 
+-	/*
+-	 * In order to operate properly, that clock seems to be always
+-	 * set to 297MHz.
+-	 */
+-	clk_set_rate_exclusive(dsi->mod_clk, 297000000);
++		/*
++		 * In order to operate properly, the module clock on the
++		 * A31 variant always seems to be set to 297MHz.
++		 */
++		if (variant->set_mod_clk)
++			clk_set_rate_exclusive(dsi->mod_clk, 297000000);
++	}
+ 
+ 	dsi->dphy = devm_phy_get(dev, "dphy");
+ 	if (IS_ERR(dsi->dphy)) {
+@@ -1191,7 +1192,8 @@ static int sun6i_dsi_probe(struct platfo
+ err_remove_dsi_host:
+ 	mipi_dsi_host_unregister(&dsi->host);
+ err_unprotect_clk:
+-	clk_rate_exclusive_put(dsi->mod_clk);
++	if (dsi->variant->has_mod_clk && dsi->variant->set_mod_clk)
++		clk_rate_exclusive_put(dsi->mod_clk);
+ err_attach_clk:
+ 	regmap_mmio_detach_clk(dsi->regs);
+ 
+@@ -1205,16 +1207,31 @@ static int sun6i_dsi_remove(struct platf
+ 
+ 	component_del(&pdev->dev, &sun6i_dsi_ops);
+ 	mipi_dsi_host_unregister(&dsi->host);
+-	clk_rate_exclusive_put(dsi->mod_clk);
++	if (dsi->variant->has_mod_clk && dsi->variant->set_mod_clk)
++		clk_rate_exclusive_put(dsi->mod_clk);
+ 
+ 	regmap_mmio_detach_clk(dsi->regs);
+ 
+ 	return 0;
+ }
+ 
++static const struct sun6i_dsi_variant sun6i_a31_mipi_dsi_variant = {
++	.has_mod_clk	= true,
++	.set_mod_clk	= true,
++};
++
++static const struct sun6i_dsi_variant sun50i_a64_mipi_dsi_variant = {
++};
++
+ static const struct of_device_id sun6i_dsi_of_table[] = {
+-	{ .compatible = "allwinner,sun6i-a31-mipi-dsi" },
+-	{ .compatible = "allwinner,sun50i-a64-mipi-dsi" },
++	{
++		.compatible	= "allwinner,sun6i-a31-mipi-dsi",
++		.data		= &sun6i_a31_mipi_dsi_variant,
++	},
++	{
++		.compatible	= "allwinner,sun50i-a64-mipi-dsi",
++		.data		= &sun50i_a64_mipi_dsi_variant,
++	},
+ 	{ }
+ };
+ MODULE_DEVICE_TABLE(of, sun6i_dsi_of_table);
+--- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
++++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
+@@ -15,6 +15,11 @@
+ 
+ #define SUN6I_DSI_TCON_DIV	4
+ 
++struct sun6i_dsi_variant {
++	bool			has_mod_clk;
++	bool			set_mod_clk;
++};
++
+ struct sun6i_dsi {
+ 	struct drm_connector	connector;
+ 	struct drm_encoder	encoder;
+@@ -31,6 +36,8 @@ struct sun6i_dsi {
+ 	struct mipi_dsi_device	*device;
+ 	struct drm_device	*drm;
+ 	struct drm_panel	*panel;
++
++	const struct sun6i_dsi_variant *variant;
+ };
+ 
+ static inline struct sun6i_dsi *host_to_sun6i_dsi(struct mipi_dsi_host *host)
diff --git a/target/linux/d1/patches-6.1/0097-drm-sun4i-dsi-Add-the-A100-variant.patch b/target/linux/d1/patches-6.1/0097-drm-sun4i-dsi-Add-the-A100-variant.patch
new file mode 100644
index 00000000000000..0077e37ed41e9c
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0097-drm-sun4i-dsi-Add-the-A100-variant.patch
@@ -0,0 +1,66 @@
+From 713029c6a33df9218d11593bc5be79420715633f Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 7 Aug 2022 11:06:22 -0500
+Subject: [PATCH 097/117] drm/sun4i: dsi: Add the A100 variant
+
+The A100 variant of the MIPI DSI controller now gets its module clock
+from the TCON via the TCON TOP, so the clock rate cannot be set to a
+fixed value. Otherwise, it appears to be the same as the A31 variant.
+
+Cover-letter:
+drm/sun4i: dsi: Support the A100/D1 controller variant
+This series adds support for the digital part of the DSI controller
+found in the A100 and D1 SoCs (plus T7, which is not supported by
+mainline Linux). There are two changes to the hardware integration:
+  1) the module clock routes through the TCON TOP, and
+  2) the separate I/O domain is removed.
+
+The actual register interface appears to be the same as before. The
+register definitions in the D1 BSP exactly match the A64 BSP.
+
+The BSP describes this as the "40nm" DSI controller variant. There is
+also a "28nm" variant with a different register interface; that one is
+found in a different subset of SoCs (V5 and A50).
+
+A100/D1 also come with an updated DPHY, described by the BSP as a
+"combo" PHY, which is now also used for LVDS channel 0. (LVDS and DSI
+share the same pins on Port D.) Since that is a different subsystem,
+I am sending that as a separate series.
+END
+
+Series-to: Chen-Yu Tsai <wens@csie.org>
+Series-to: Jernej Skrabec <jernej.skrabec@gmail.com>
+Series-to: Maxime Ripard <mripard@kernel.org>
+
+Series-version: 2
+
+Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
++++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
+@@ -1223,6 +1223,10 @@ static const struct sun6i_dsi_variant su
+ static const struct sun6i_dsi_variant sun50i_a64_mipi_dsi_variant = {
+ };
+ 
++static const struct sun6i_dsi_variant sun50i_a100_mipi_dsi_variant = {
++	.has_mod_clk	= true,
++};
++
+ static const struct of_device_id sun6i_dsi_of_table[] = {
+ 	{
+ 		.compatible	= "allwinner,sun6i-a31-mipi-dsi",
+@@ -1232,6 +1236,10 @@ static const struct of_device_id sun6i_d
+ 		.compatible	= "allwinner,sun50i-a64-mipi-dsi",
+ 		.data		= &sun50i_a64_mipi_dsi_variant,
+ 	},
++	{
++		.compatible	= "allwinner,sun50i-a100-mipi-dsi",
++		.data		= &sun50i_a100_mipi_dsi_variant,
++	},
+ 	{ }
+ };
+ MODULE_DEVICE_TABLE(of, sun6i_dsi_of_table);
diff --git a/target/linux/d1/patches-6.1/0098-riscv-Move-cast-inside-kernel_mapping_-pv-a_to_-vp-a.patch b/target/linux/d1/patches-6.1/0098-riscv-Move-cast-inside-kernel_mapping_-pv-a_to_-vp-a.patch
new file mode 100644
index 00000000000000..c4ac271b204253
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0098-riscv-Move-cast-inside-kernel_mapping_-pv-a_to_-vp-a.patch
@@ -0,0 +1,81 @@
+From b6af4b7f6f75904509747c08e87d91c1bb607bd4 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Thu, 22 Sep 2022 00:39:36 -0500
+Subject: [PATCH 098/117] riscv: Move cast inside kernel_mapping_[pv]a_to_[vp]a
+
+Before commit 44c922572952 ("RISC-V: enable XIP"), these macros cast
+their argument to unsigned long. That commit moved the cast after an
+assignment to an unsigned long variable, rendering it ineffectual.
+Move the cast back, so we can remove the cast at each call site.
+
+Series-to: Palmer Dabbelt <palmer@dabbelt.com>
+Series-to: linux-riscv@lists.infradead.org
+
+Series-version: 2
+
+Reviewed-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
+Reviewed-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/riscv/include/asm/page.h | 18 +++++++++---------
+ arch/riscv/mm/init.c          | 16 ++++++++--------
+ 2 files changed, 17 insertions(+), 17 deletions(-)
+
+--- a/arch/riscv/include/asm/page.h
++++ b/arch/riscv/include/asm/page.h
+@@ -123,20 +123,20 @@ extern phys_addr_t phys_ram_base;
+ 	((x) >= PAGE_OFFSET && (!IS_ENABLED(CONFIG_64BIT) || (x) < PAGE_OFFSET + KERN_VIRT_SIZE))
+ 
+ #define linear_mapping_pa_to_va(x)	((void *)((unsigned long)(x) + kernel_map.va_pa_offset))
+-#define kernel_mapping_pa_to_va(y)	({						\
+-	unsigned long _y = y;								\
+-	(IS_ENABLED(CONFIG_XIP_KERNEL) && _y < phys_ram_base) ?					\
+-		(void *)((unsigned long)(_y) + kernel_map.va_kernel_xip_pa_offset) :		\
+-		(void *)((unsigned long)(_y) + kernel_map.va_kernel_pa_offset + XIP_OFFSET);	\
++#define kernel_mapping_pa_to_va(y)	({					\
++	unsigned long _y = (unsigned long)(y);					\
++	(IS_ENABLED(CONFIG_XIP_KERNEL) && _y < phys_ram_base) ?			\
++		(void *)(_y + kernel_map.va_kernel_xip_pa_offset) :		\
++		(void *)(_y + kernel_map.va_kernel_pa_offset + XIP_OFFSET);	\
+ 	})
+ #define __pa_to_va_nodebug(x)		linear_mapping_pa_to_va(x)
+ 
+ #define linear_mapping_va_to_pa(x)	((unsigned long)(x) - kernel_map.va_pa_offset)
+ #define kernel_mapping_va_to_pa(y) ({						\
+-	unsigned long _y = y;							\
+-	(IS_ENABLED(CONFIG_XIP_KERNEL) && _y < kernel_map.virt_addr + XIP_OFFSET) ?	\
+-		((unsigned long)(_y) - kernel_map.va_kernel_xip_pa_offset) :		\
+-		((unsigned long)(_y) - kernel_map.va_kernel_pa_offset - XIP_OFFSET);	\
++	unsigned long _y = (unsigned long)(y);					\
++	(IS_ENABLED(CONFIG_XIP_KERNEL) && _y < kernel_map.virt_addr + XIP_OFFSET) ? \
++		(_y - kernel_map.va_kernel_xip_pa_offset) :			\
++		(_y - kernel_map.va_kernel_pa_offset - XIP_OFFSET);		\
+ 	})
+ 
+ #define __va_to_pa_nodebug(x)	({						\
+--- a/arch/riscv/mm/init.c
++++ b/arch/riscv/mm/init.c
+@@ -903,15 +903,15 @@ static void __init pt_ops_set_early(void
+  */
+ static void __init pt_ops_set_fixmap(void)
+ {
+-	pt_ops.alloc_pte = kernel_mapping_pa_to_va((uintptr_t)alloc_pte_fixmap);
+-	pt_ops.get_pte_virt = kernel_mapping_pa_to_va((uintptr_t)get_pte_virt_fixmap);
++	pt_ops.alloc_pte = kernel_mapping_pa_to_va(alloc_pte_fixmap);
++	pt_ops.get_pte_virt = kernel_mapping_pa_to_va(get_pte_virt_fixmap);
+ #ifndef __PAGETABLE_PMD_FOLDED
+-	pt_ops.alloc_pmd = kernel_mapping_pa_to_va((uintptr_t)alloc_pmd_fixmap);
+-	pt_ops.get_pmd_virt = kernel_mapping_pa_to_va((uintptr_t)get_pmd_virt_fixmap);
+-	pt_ops.alloc_pud = kernel_mapping_pa_to_va((uintptr_t)alloc_pud_fixmap);
+-	pt_ops.get_pud_virt = kernel_mapping_pa_to_va((uintptr_t)get_pud_virt_fixmap);
+-	pt_ops.alloc_p4d = kernel_mapping_pa_to_va((uintptr_t)alloc_p4d_fixmap);
+-	pt_ops.get_p4d_virt = kernel_mapping_pa_to_va((uintptr_t)get_p4d_virt_fixmap);
++	pt_ops.alloc_pmd = kernel_mapping_pa_to_va(alloc_pmd_fixmap);
++	pt_ops.get_pmd_virt = kernel_mapping_pa_to_va(get_pmd_virt_fixmap);
++	pt_ops.alloc_pud = kernel_mapping_pa_to_va(alloc_pud_fixmap);
++	pt_ops.get_pud_virt = kernel_mapping_pa_to_va(get_pud_virt_fixmap);
++	pt_ops.alloc_p4d = kernel_mapping_pa_to_va(alloc_p4d_fixmap);
++	pt_ops.get_p4d_virt = kernel_mapping_pa_to_va(get_p4d_virt_fixmap);
+ #endif
+ }
+ 
diff --git a/target/linux/d1/patches-6.1/0099-dt-bindings-sun6i-a31-mipi-dphy-Add-the-interrupts-p.patch b/target/linux/d1/patches-6.1/0099-dt-bindings-sun6i-a31-mipi-dphy-Add-the-interrupts-p.patch
new file mode 100644
index 00000000000000..056d92af36a391
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0099-dt-bindings-sun6i-a31-mipi-dphy-Add-the-interrupts-p.patch
@@ -0,0 +1,38 @@
+From 20a204b31291befcd583f97dafc0a827f3bc7f00 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Fri, 12 Aug 2022 01:37:16 -0500
+Subject: [PATCH 099/117] dt-bindings: sun6i-a31-mipi-dphy: Add the interrupts
+ property
+
+The sun6i DPHY can generate several interrupts, mostly for reporting
+error conditions, but also for detecting BTA and UPLS sequences.
+Document this capability in order to accurately describe the hardware.
+
+The DPHY has no interrupt number provided in the vendor documentation
+because its interrupt line is shared with the DSI controller.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ .../bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml           | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
++++ b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
+@@ -24,6 +24,9 @@ properties:
+   reg:
+     maxItems: 1
+ 
++  interrupts:
++    maxItems: 1
++
+   clocks:
+     items:
+       - description: Bus Clock
+@@ -53,6 +56,7 @@ required:
+   - "#phy-cells"
+   - compatible
+   - reg
++  - interrupts
+   - clocks
+   - clock-names
+   - resets
diff --git a/target/linux/d1/patches-6.1/0100-ARM-dts-sun8i-a33-Add-DPHY-interrupt.patch b/target/linux/d1/patches-6.1/0100-ARM-dts-sun8i-a33-Add-DPHY-interrupt.patch
new file mode 100644
index 00000000000000..36a4627e007530
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0100-ARM-dts-sun8i-a33-Add-DPHY-interrupt.patch
@@ -0,0 +1,22 @@
+From 7d47c62b378a4dbbf3e46a80c7b03966f8964da1 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Fri, 12 Aug 2022 02:24:14 -0500
+Subject: [PATCH 100/117] ARM: dts: sun8i: a33: Add DPHY interrupt
+
+The DPHY has an interrupt line which is shared with the DSI controller.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm/boot/dts/sun8i-a33.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/arm/boot/dts/sun8i-a33.dtsi
++++ b/arch/arm/boot/dts/sun8i-a33.dtsi
+@@ -278,6 +278,7 @@
+ 		dphy: d-phy@1ca1000 {
+ 			compatible = "allwinner,sun6i-a31-mipi-dphy";
+ 			reg = <0x01ca1000 0x1000>;
++			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&ccu CLK_BUS_MIPI_DSI>,
+ 				 <&ccu CLK_DSI_DPHY>;
+ 			clock-names = "bus", "mod";
diff --git a/target/linux/d1/patches-6.1/0101-arm64-dts-allwinner-a64-Add-DPHY-interrupt.patch b/target/linux/d1/patches-6.1/0101-arm64-dts-allwinner-a64-Add-DPHY-interrupt.patch
new file mode 100644
index 00000000000000..5734a84a19494f
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0101-arm64-dts-allwinner-a64-Add-DPHY-interrupt.patch
@@ -0,0 +1,22 @@
+From 11d78fce09e80ec246016c19ecc28a724e1e5530 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Fri, 12 Aug 2022 02:25:55 -0500
+Subject: [PATCH 101/117] arm64: dts: allwinner: a64: Add DPHY interrupt
+
+The DPHY has an interrupt line which is shared with the DSI controller.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+@@ -1199,6 +1199,7 @@
+ 			compatible = "allwinner,sun50i-a64-mipi-dphy",
+ 				     "allwinner,sun6i-a31-mipi-dphy";
+ 			reg = <0x01ca1000 0x1000>;
++			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&ccu CLK_BUS_MIPI_DSI>,
+ 				 <&ccu CLK_DSI_DPHY>;
+ 			clock-names = "bus", "mod";
diff --git a/target/linux/d1/patches-6.1/0102-dt-bindings-sun6i-a31-mipi-dphy-Add-the-A100-DPHY-va.patch b/target/linux/d1/patches-6.1/0102-dt-bindings-sun6i-a31-mipi-dphy-Add-the-A100-DPHY-va.patch
new file mode 100644
index 00000000000000..6c93a60296be3e
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0102-dt-bindings-sun6i-a31-mipi-dphy-Add-the-A100-DPHY-va.patch
@@ -0,0 +1,34 @@
+From c7fa1be12bf0ef02f5557dd1d1100d25af4e34f5 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 7 Aug 2022 11:00:12 -0500
+Subject: [PATCH 102/117] dt-bindings: sun6i-a31-mipi-dphy: Add the A100 DPHY
+ variant
+
+A100 features an updated DPHY, which moves PLL control inside the DPHY
+register space. (Previously PLL-MIPI was controlled from the CCU. This
+does not affect the "clocks" property because the link between PLL-MIPI
+and the DPHY was never represented in the devicetree.) It also requires
+a modified analog power-on sequence. Finally, the new DPHY adds support
+for operating as an LVDS PHY. D1 uses this same variant.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ .../bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml           | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
++++ b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
+@@ -17,9 +17,13 @@ properties:
+   compatible:
+     oneOf:
+       - const: allwinner,sun6i-a31-mipi-dphy
++      - const: allwinner,sun50i-a100-mipi-dphy
+       - items:
+           - const: allwinner,sun50i-a64-mipi-dphy
+           - const: allwinner,sun6i-a31-mipi-dphy
++      - items:
++          - const: allwinner,sun20i-d1-mipi-dphy
++          - const: allwinner,sun50i-a100-mipi-dphy
+ 
+   reg:
+     maxItems: 1
diff --git a/target/linux/d1/patches-6.1/0103-phy-allwinner-phy-sun6i-mipi-dphy-Make-RX-support-op.patch b/target/linux/d1/patches-6.1/0103-phy-allwinner-phy-sun6i-mipi-dphy-Make-RX-support-op.patch
new file mode 100644
index 00000000000000..6a1f4f9af9b9b4
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0103-phy-allwinner-phy-sun6i-mipi-dphy-Make-RX-support-op.patch
@@ -0,0 +1,80 @@
+From 27c0c2cbe7b30b907b031016d2cd15fe9505cb1b Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 7 Aug 2022 12:11:53 -0500
+Subject: [PATCH 103/117] phy: allwinner: phy-sun6i-mipi-dphy: Make RX support
+ optional
+
+While all variants of the DPHY likely support RX mode, the new variant
+in the A100 is not used in this direction by the BSP, and it has some
+analog register changes, so its RX power-on sequence is unknown. To be
+safe, limit RX support to variants where the power-on sequence is known.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 25 +++++++++++++++++++--
+ 1 file changed, 23 insertions(+), 2 deletions(-)
+
+--- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
++++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
+@@ -114,6 +114,10 @@ enum sun6i_dphy_direction {
+ 	SUN6I_DPHY_DIRECTION_RX,
+ };
+ 
++struct sun6i_dphy_variant {
++	bool	supports_rx;
++};
++
+ struct sun6i_dphy {
+ 	struct clk				*bus_clk;
+ 	struct clk				*mod_clk;
+@@ -123,6 +127,7 @@ struct sun6i_dphy {
+ 	struct phy				*phy;
+ 	struct phy_configure_opts_mipi_dphy	config;
+ 
++	const struct sun6i_dphy_variant		*variant;
+ 	enum sun6i_dphy_direction		direction;
+ };
+ 
+@@ -409,6 +414,10 @@ static int sun6i_dphy_probe(struct platf
+ 	if (!dphy)
+ 		return -ENOMEM;
+ 
++	dphy->variant = device_get_match_data(&pdev->dev);
++	if (!dphy->variant)
++		return -EINVAL;
++
+ 	regs = devm_platform_ioremap_resource(pdev, 0);
+ 	if (IS_ERR(regs)) {
+ 		dev_err(&pdev->dev, "Couldn't map the DPHY encoder registers\n");
+@@ -445,8 +454,13 @@ static int sun6i_dphy_probe(struct platf
+ 	ret = of_property_read_string(pdev->dev.of_node, "allwinner,direction",
+ 				      &direction);
+ 
+-	if (!ret && !strncmp(direction, "rx", 2))
++	if (!ret && !strncmp(direction, "rx", 2)) {
++		if (!dphy->variant->supports_rx) {
++			dev_err(&pdev->dev, "RX not supported on this variant\n");
++			return -EOPNOTSUPP;
++		}
+ 		dphy->direction = SUN6I_DPHY_DIRECTION_RX;
++	}
+ 
+ 	phy_set_drvdata(dphy->phy, dphy);
+ 	phy_provider = devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate);
+@@ -454,8 +468,15 @@ static int sun6i_dphy_probe(struct platf
+ 	return PTR_ERR_OR_ZERO(phy_provider);
+ }
+ 
++static const struct sun6i_dphy_variant sun6i_a31_mipi_dphy_variant = {
++	.supports_rx	= true,
++};
++
+ static const struct of_device_id sun6i_dphy_of_table[] = {
+-	{ .compatible = "allwinner,sun6i-a31-mipi-dphy" },
++	{
++		.compatible	= "allwinner,sun6i-a31-mipi-dphy",
++		.data		= &sun6i_a31_mipi_dphy_variant,
++	},
+ 	{ }
+ };
+ MODULE_DEVICE_TABLE(of, sun6i_dphy_of_table);
diff --git a/target/linux/d1/patches-6.1/0104-phy-allwinner-phy-sun6i-mipi-dphy-Set-enable-bit-las.patch b/target/linux/d1/patches-6.1/0104-phy-allwinner-phy-sun6i-mipi-dphy-Set-enable-bit-las.patch
new file mode 100644
index 00000000000000..e8c6ef8c5af51c
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0104-phy-allwinner-phy-sun6i-mipi-dphy-Set-enable-bit-las.patch
@@ -0,0 +1,39 @@
+From 16993169c82c2c57e1df1e7f4598a7c2aa565fe2 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 7 Aug 2022 11:12:02 -0500
+Subject: [PATCH 104/117] phy: allwinner: phy-sun6i-mipi-dphy: Set enable bit
+ last
+
+The A100 variant of the DPHY requires configuring the analog registers
+before setting the global enable bit. Since this order also works on the
+other variants, always use it, to minimize the differences between them.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+--- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
++++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
+@@ -183,10 +183,6 @@ static int sun6i_dphy_tx_power_on(struct
+ 		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(3) |
+ 		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(3));
+ 
+-	regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG,
+-		     SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) |
+-		     SUN6I_DPHY_GCTL_EN);
+-
+ 	regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,
+ 		     SUN6I_DPHY_ANA0_REG_PWS |
+ 		     SUN6I_DPHY_ANA0_REG_DMPC |
+@@ -244,6 +240,10 @@ static int sun6i_dphy_tx_power_on(struct
+ 			   SUN6I_DPHY_ANA2_EN_P2S_CPU_MASK,
+ 			   SUN6I_DPHY_ANA2_EN_P2S_CPU(lanes_mask));
+ 
++	regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG,
++		     SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) |
++		     SUN6I_DPHY_GCTL_EN);
++
+ 	return 0;
+ }
+ 
diff --git a/target/linux/d1/patches-6.1/0105-phy-allwinner-phy-sun6i-mipi-dphy-Add-a-variant-powe.patch b/target/linux/d1/patches-6.1/0105-phy-allwinner-phy-sun6i-mipi-dphy-Add-a-variant-powe.patch
new file mode 100644
index 00000000000000..6df659e80da769
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0105-phy-allwinner-phy-sun6i-mipi-dphy-Add-a-variant-powe.patch
@@ -0,0 +1,109 @@
+From b953c09bde508c2edd8acd95abba8542b6cebff6 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 7 Aug 2022 11:44:09 -0500
+Subject: [PATCH 105/117] phy: allwinner: phy-sun6i-mipi-dphy: Add a variant
+ power-on hook
+
+The A100 variant uses the same values for the timing registers, and it
+uses the same final power-on sequence, but it needs a different analog
+register configuration in the middle. Support this by moving the
+variant-specific parts to a hook provided by the variant.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 59 ++++++++++++---------
+ 1 file changed, 35 insertions(+), 24 deletions(-)
+
+--- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
++++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
+@@ -114,7 +114,10 @@ enum sun6i_dphy_direction {
+ 	SUN6I_DPHY_DIRECTION_RX,
+ };
+ 
++struct sun6i_dphy;
++
+ struct sun6i_dphy_variant {
++	void	(*tx_power_on)(struct sun6i_dphy *dphy);
+ 	bool	supports_rx;
+ };
+ 
+@@ -156,33 +159,10 @@ static int sun6i_dphy_configure(struct p
+ 	return 0;
+ }
+ 
+-static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
++static void sun6i_a31_mipi_dphy_tx_power_on(struct sun6i_dphy *dphy)
+ {
+ 	u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0);
+ 
+-	regmap_write(dphy->regs, SUN6I_DPHY_TX_CTL_REG,
+-		     SUN6I_DPHY_TX_CTL_HS_TX_CLK_CONT);
+-
+-	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME0_REG,
+-		     SUN6I_DPHY_TX_TIME0_LP_CLK_DIV(14) |
+-		     SUN6I_DPHY_TX_TIME0_HS_PREPARE(6) |
+-		     SUN6I_DPHY_TX_TIME0_HS_TRAIL(10));
+-
+-	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME1_REG,
+-		     SUN6I_DPHY_TX_TIME1_CLK_PREPARE(7) |
+-		     SUN6I_DPHY_TX_TIME1_CLK_ZERO(50) |
+-		     SUN6I_DPHY_TX_TIME1_CLK_PRE(3) |
+-		     SUN6I_DPHY_TX_TIME1_CLK_POST(10));
+-
+-	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME2_REG,
+-		     SUN6I_DPHY_TX_TIME2_CLK_TRAIL(30));
+-
+-	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME3_REG, 0);
+-
+-	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME4_REG,
+-		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(3) |
+-		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(3));
+-
+ 	regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,
+ 		     SUN6I_DPHY_ANA0_REG_PWS |
+ 		     SUN6I_DPHY_ANA0_REG_DMPC |
+@@ -214,6 +194,36 @@ static int sun6i_dphy_tx_power_on(struct
+ 		     SUN6I_DPHY_ANA3_EN_LDOC |
+ 		     SUN6I_DPHY_ANA3_EN_LDOD);
+ 	udelay(1);
++}
++
++static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
++{
++	u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0);
++
++	regmap_write(dphy->regs, SUN6I_DPHY_TX_CTL_REG,
++		     SUN6I_DPHY_TX_CTL_HS_TX_CLK_CONT);
++
++	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME0_REG,
++		     SUN6I_DPHY_TX_TIME0_LP_CLK_DIV(14) |
++		     SUN6I_DPHY_TX_TIME0_HS_PREPARE(6) |
++		     SUN6I_DPHY_TX_TIME0_HS_TRAIL(10));
++
++	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME1_REG,
++		     SUN6I_DPHY_TX_TIME1_CLK_PREPARE(7) |
++		     SUN6I_DPHY_TX_TIME1_CLK_ZERO(50) |
++		     SUN6I_DPHY_TX_TIME1_CLK_PRE(3) |
++		     SUN6I_DPHY_TX_TIME1_CLK_POST(10));
++
++	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME2_REG,
++		     SUN6I_DPHY_TX_TIME2_CLK_TRAIL(30));
++
++	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME3_REG, 0);
++
++	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME4_REG,
++		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(3) |
++		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(3));
++
++	dphy->variant->tx_power_on(dphy);
+ 
+ 	regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA3_REG,
+ 			   SUN6I_DPHY_ANA3_EN_VTTC |
+@@ -469,6 +479,7 @@ static int sun6i_dphy_probe(struct platf
+ }
+ 
+ static const struct sun6i_dphy_variant sun6i_a31_mipi_dphy_variant = {
++	.tx_power_on	= sun6i_a31_mipi_dphy_tx_power_on,
+ 	.supports_rx	= true,
+ };
+ 
diff --git a/target/linux/d1/patches-6.1/0106-phy-allwinner-phy-sun6i-mipi-dphy-Add-the-A100-DPHY-.patch b/target/linux/d1/patches-6.1/0106-phy-allwinner-phy-sun6i-mipi-dphy-Add-the-A100-DPHY-.patch
new file mode 100644
index 00000000000000..751d3821776fc0
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0106-phy-allwinner-phy-sun6i-mipi-dphy-Add-the-A100-DPHY-.patch
@@ -0,0 +1,229 @@
+From 474b608dee5e6285dd1981b00ab568a2f7f15fd0 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Wed, 10 Aug 2022 23:02:06 -0500
+Subject: [PATCH 106/117] phy: allwinner: phy-sun6i-mipi-dphy: Add the A100
+ DPHY variant
+
+A100 features an updated DPHY, which moves PLL control inside the DPHY
+register space (previously the PLL was controlled from the CCU). It also
+requires a modified analog power-on sequence. This "combo PHY" can also
+be used as an LVDS PHY, but that is not yet supported by the driver.
+
+Cover-letter:
+phy: allwinner: phy-sun6i-mipi-dphy: Add the A100 DPHY
+This series adds support for the updated DPHY found in a couple of
+recent Allwinner SoCs. The first three patches fix an omission in the
+existing binding. The remaining patches add the new hardware variant.
+END
+
+Series-to: Kishon Vijay Abraham I <kishon@ti.com>
+Series-to: Vinod Koul <vkoul@kernel.org>
+Series-to: Chen-Yu Tsai <wens@csie.org>
+Series-to: Jernej Skrabec <jernej.skrabec@gmail.com>
+Series-to: Maxime Ripard <mripard@kernel.org>
+Series-cc: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 143 +++++++++++++++++++-
+ 1 file changed, 142 insertions(+), 1 deletion(-)
+
+--- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
++++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
+@@ -70,11 +70,19 @@
+ 
+ #define SUN6I_DPHY_ANA0_REG		0x4c
+ #define SUN6I_DPHY_ANA0_REG_PWS			BIT(31)
++#define SUN6I_DPHY_ANA0_REG_PWEND		BIT(30)
++#define SUN6I_DPHY_ANA0_REG_PWENC		BIT(29)
+ #define SUN6I_DPHY_ANA0_REG_DMPC		BIT(28)
+ #define SUN6I_DPHY_ANA0_REG_DMPD(n)		(((n) & 0xf) << 24)
++#define SUN6I_DPHY_ANA0_REG_SRXDT(n)		(((n) & 0xf) << 20)
++#define SUN6I_DPHY_ANA0_REG_SRXCK(n)		(((n) & 0xf) << 16)
++#define SUN6I_DPHY_ANA0_REG_SDIV2		BIT(15)
+ #define SUN6I_DPHY_ANA0_REG_SLV(n)		(((n) & 7) << 12)
+ #define SUN6I_DPHY_ANA0_REG_DEN(n)		(((n) & 0xf) << 8)
++#define SUN6I_DPHY_ANA0_REG_PLR(n)		(((n) & 0xf) << 4)
+ #define SUN6I_DPHY_ANA0_REG_SFB(n)		(((n) & 3) << 2)
++#define SUN6I_DPHY_ANA0_REG_RSD			BIT(1)
++#define SUN6I_DPHY_ANA0_REG_SELSCK		BIT(0)
+ 
+ #define SUN6I_DPHY_ANA1_REG		0x50
+ #define SUN6I_DPHY_ANA1_REG_VTTMODE		BIT(31)
+@@ -97,8 +105,13 @@
+ #define SUN6I_DPHY_ANA3_EN_LDOR			BIT(18)
+ 
+ #define SUN6I_DPHY_ANA4_REG		0x5c
++#define SUN6I_DPHY_ANA4_REG_EN_MIPI		BIT(31)
++#define SUN6I_DPHY_ANA4_REG_EN_COMTEST		BIT(30)
++#define SUN6I_DPHY_ANA4_REG_COMTEST(n)		(((n) & 3) << 28)
++#define SUN6I_DPHY_ANA4_REG_IB(n)		(((n) & 3) << 25)
+ #define SUN6I_DPHY_ANA4_REG_DMPLVC		BIT(24)
+ #define SUN6I_DPHY_ANA4_REG_DMPLVD(n)		(((n) & 0xf) << 20)
++#define SUN6I_DPHY_ANA4_REG_VTT_SET(n)		(((n) & 0x7) << 17)
+ #define SUN6I_DPHY_ANA4_REG_CKDV(n)		(((n) & 0x1f) << 12)
+ #define SUN6I_DPHY_ANA4_REG_TMSC(n)		(((n) & 3) << 10)
+ #define SUN6I_DPHY_ANA4_REG_TMSD(n)		(((n) & 3) << 8)
+@@ -109,6 +122,56 @@
+ 
+ #define SUN6I_DPHY_DBG5_REG		0xf4
+ 
++#define SUN50I_DPHY_TX_SLEW_REG0	0xf8
++#define SUN50I_DPHY_TX_SLEW_REG1	0xfc
++#define SUN50I_DPHY_TX_SLEW_REG2	0x100
++
++#define SUN50I_DPHY_PLL_REG0		0x104
++#define SUN50I_DPHY_PLL_REG0_CP36_EN		BIT(23)
++#define SUN50I_DPHY_PLL_REG0_LDO_EN		BIT(22)
++#define SUN50I_DPHY_PLL_REG0_EN_LVS		BIT(21)
++#define SUN50I_DPHY_PLL_REG0_PLL_EN		BIT(20)
++#define SUN50I_DPHY_PLL_REG0_P(n)		(((n) & 0xf) << 16)
++#define SUN50I_DPHY_PLL_REG0_N(n)		(((n) & 0xff) << 8)
++#define SUN50I_DPHY_PLL_REG0_NDET		BIT(7)
++#define SUN50I_DPHY_PLL_REG0_TDIV		BIT(6)
++#define SUN50I_DPHY_PLL_REG0_M0(n)		(((n) & 3) << 4)
++#define SUN50I_DPHY_PLL_REG0_M1(n)		((n) & 0xf)
++
++#define SUN50I_DPHY_PLL_REG1		0x108
++#define SUN50I_DPHY_PLL_REG1_UNLOCK_MDSEL(n)	(((n) & 3) << 14)
++#define SUN50I_DPHY_PLL_REG1_LOCKMDSEL		BIT(13)
++#define SUN50I_DPHY_PLL_REG1_LOCKDET_EN		BIT(12)
++#define SUN50I_DPHY_PLL_REG1_VSETA(n)		(((n) & 0x7) << 9)
++#define SUN50I_DPHY_PLL_REG1_VSETD(n)		(((n) & 0x7) << 6)
++#define SUN50I_DPHY_PLL_REG1_LPF_SW		BIT(5)
++#define SUN50I_DPHY_PLL_REG1_ICP_SEL(n)		(((n) & 3) << 3)
++#define SUN50I_DPHY_PLL_REG1_ATEST_SEL(n)	(((n) & 3) << 1)
++#define SUN50I_DPHY_PLL_REG1_TEST_EN		BIT(0)
++
++#define SUN50I_DPHY_PLL_REG2		0x10c
++#define SUN50I_DPHY_PLL_REG2_SDM_EN		BIT(31)
++#define SUN50I_DPHY_PLL_REG2_FF_EN		BIT(30)
++#define SUN50I_DPHY_PLL_REG2_SS_EN		BIT(29)
++#define SUN50I_DPHY_PLL_REG2_SS_FRAC(n)		(((n) & 0x1ff) << 20)
++#define SUN50I_DPHY_PLL_REG2_SS_INT(n)		(((n) & 0xff) << 12)
++#define SUN50I_DPHY_PLL_REG2_FRAC(n)		((n) & 0xfff)
++
++#define SUN50I_COMBO_PHY_REG0		0x110
++#define SUN50I_COMBO_PHY_REG0_EN_TEST_COMBOLDO	BIT(5)
++#define SUN50I_COMBO_PHY_REG0_EN_TEST_0P8	BIT(4)
++#define SUN50I_COMBO_PHY_REG0_EN_MIPI		BIT(3)
++#define SUN50I_COMBO_PHY_REG0_EN_LVDS		BIT(2)
++#define SUN50I_COMBO_PHY_REG0_EN_COMBOLDO	BIT(1)
++#define SUN50I_COMBO_PHY_REG0_EN_CP		BIT(0)
++
++#define SUN50I_COMBO_PHY_REG1		0x114
++#define SUN50I_COMBO_PHY_REG2_REG_VREF1P6(n)	(((n) & 0x7) << 4)
++#define SUN50I_COMBO_PHY_REG2_REG_VREF0P8(n)	((n) & 0x7)
++
++#define SUN50I_COMBO_PHY_REG2		0x118
++#define SUN50I_COMBO_PHY_REG2_HS_STOP_DLY(n)	((n) & 0xff)
++
+ enum sun6i_dphy_direction {
+ 	SUN6I_DPHY_DIRECTION_TX,
+ 	SUN6I_DPHY_DIRECTION_RX,
+@@ -196,6 +259,76 @@ static void sun6i_a31_mipi_dphy_tx_power
+ 	udelay(1);
+ }
+ 
++static void sun50i_a100_mipi_dphy_tx_power_on(struct sun6i_dphy *dphy)
++{
++	unsigned long mipi_symbol_rate = dphy->config.hs_clk_rate;
++	unsigned int div, n;
++
++	regmap_write(dphy->regs, SUN6I_DPHY_ANA4_REG,
++		     SUN6I_DPHY_ANA4_REG_IB(2) |
++		     SUN6I_DPHY_ANA4_REG_DMPLVD(4) |
++		     SUN6I_DPHY_ANA4_REG_VTT_SET(3) |
++		     SUN6I_DPHY_ANA4_REG_CKDV(3) |
++		     SUN6I_DPHY_ANA4_REG_TMSD(1) |
++		     SUN6I_DPHY_ANA4_REG_TMSC(1) |
++		     SUN6I_DPHY_ANA4_REG_TXPUSD(2) |
++		     SUN6I_DPHY_ANA4_REG_TXPUSC(3) |
++		     SUN6I_DPHY_ANA4_REG_TXDNSD(2) |
++		     SUN6I_DPHY_ANA4_REG_TXDNSC(3));
++
++	regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA2_REG,
++			   SUN6I_DPHY_ANA2_EN_CK_CPU,
++			   SUN6I_DPHY_ANA2_EN_CK_CPU);
++
++	regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA2_REG,
++			   SUN6I_DPHY_ANA2_REG_ENIB,
++			   SUN6I_DPHY_ANA2_REG_ENIB);
++
++	regmap_write(dphy->regs, SUN6I_DPHY_ANA3_REG,
++		     SUN6I_DPHY_ANA3_EN_LDOR |
++		     SUN6I_DPHY_ANA3_EN_LDOC |
++		     SUN6I_DPHY_ANA3_EN_LDOD);
++
++	regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,
++		     SUN6I_DPHY_ANA0_REG_PLR(4) |
++		     SUN6I_DPHY_ANA0_REG_SFB(1));
++
++	regmap_write(dphy->regs, SUN50I_COMBO_PHY_REG0,
++		     SUN50I_COMBO_PHY_REG0_EN_CP);
++
++	/* Choose a divider to limit the VCO frequency to around 2 GHz. */
++	div = 16 >> order_base_2(DIV_ROUND_UP(mipi_symbol_rate, 264000000));
++	n = mipi_symbol_rate * div / 24000000;
++
++	regmap_write(dphy->regs, SUN50I_DPHY_PLL_REG0,
++		     SUN50I_DPHY_PLL_REG0_CP36_EN |
++		     SUN50I_DPHY_PLL_REG0_LDO_EN |
++		     SUN50I_DPHY_PLL_REG0_EN_LVS |
++		     SUN50I_DPHY_PLL_REG0_PLL_EN |
++		     SUN50I_DPHY_PLL_REG0_NDET |
++		     SUN50I_DPHY_PLL_REG0_P((div - 1) % 8) |
++		     SUN50I_DPHY_PLL_REG0_N(n) |
++		     SUN50I_DPHY_PLL_REG0_M0((div - 1) / 8) |
++		     SUN50I_DPHY_PLL_REG0_M1(2));
++
++	/* Disable sigma-delta modulation. */
++	regmap_write(dphy->regs, SUN50I_DPHY_PLL_REG2, 0);
++
++	regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA4_REG,
++			   SUN6I_DPHY_ANA4_REG_EN_MIPI,
++			   SUN6I_DPHY_ANA4_REG_EN_MIPI);
++
++	regmap_update_bits(dphy->regs, SUN50I_COMBO_PHY_REG0,
++			   SUN50I_COMBO_PHY_REG0_EN_MIPI |
++			   SUN50I_COMBO_PHY_REG0_EN_COMBOLDO,
++			   SUN50I_COMBO_PHY_REG0_EN_MIPI |
++			   SUN50I_COMBO_PHY_REG0_EN_COMBOLDO);
++
++	regmap_write(dphy->regs, SUN50I_COMBO_PHY_REG2,
++		     SUN50I_COMBO_PHY_REG2_HS_STOP_DLY(20));
++	udelay(1);
++}
++
+ static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
+ {
+ 	u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0);
+@@ -408,7 +541,7 @@ static const struct regmap_config sun6i_
+ 	.reg_bits	= 32,
+ 	.val_bits	= 32,
+ 	.reg_stride	= 4,
+-	.max_register	= SUN6I_DPHY_DBG5_REG,
++	.max_register	= SUN50I_COMBO_PHY_REG2,
+ 	.name		= "mipi-dphy",
+ };
+ 
+@@ -483,11 +616,19 @@ static const struct sun6i_dphy_variant s
+ 	.supports_rx	= true,
+ };
+ 
++static const struct sun6i_dphy_variant sun50i_a100_mipi_dphy_variant = {
++	.tx_power_on	= sun50i_a100_mipi_dphy_tx_power_on,
++};
++
+ static const struct of_device_id sun6i_dphy_of_table[] = {
+ 	{
+ 		.compatible	= "allwinner,sun6i-a31-mipi-dphy",
+ 		.data		= &sun6i_a31_mipi_dphy_variant,
+ 	},
++	{
++		.compatible	= "allwinner,sun50i-a100-mipi-dphy",
++		.data		= &sun50i_a100_mipi_dphy_variant,
++	},
+ 	{ }
+ };
+ MODULE_DEVICE_TABLE(of, sun6i_dphy_of_table);
diff --git a/target/linux/d1/patches-6.1/0107-drm-panel-Add-driver-for-Clockwork-cwd686-panel.patch b/target/linux/d1/patches-6.1/0107-drm-panel-Add-driver-for-Clockwork-cwd686-panel.patch
new file mode 100644
index 00000000000000..5dd0273b7e408d
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0107-drm-panel-Add-driver-for-Clockwork-cwd686-panel.patch
@@ -0,0 +1,518 @@
+From 5bf84a1a0a282a18bf9dd2d752537525aefc2e05 Mon Sep 17 00:00:00 2001
+From: Max Fierke <max@maxfierke.com>
+Date: Wed, 1 Jun 2022 00:17:48 -0500
+Subject: [PATCH 107/117] drm: panel: Add driver for Clockwork cwd686 panel
+
+The Clockwork DevTerm (all models) uses a 6.86" IPS display
+of unknown provenance, which uses the Chipone ICNL9707 IC driver.
+
+The display panel I have has two model numbers: TXW686001 and WTL068601G,
+but cannot find any manufacturer associated with either, so opting for the
+Clockwork model number.
+
+This driver is based on the GPL-licensed driver released by Clockwork,
+authored by Pinfan Zhu, with some additional cleanup, rotation support,
+and display sleep re-enabling done by me.
+
+Original driver here for reference: https://github.com/clockworkpi/DevTerm/blob/main/Code/patch/armbian_build_a06/patch/kernel-004-panel.patch
+Display IC datasheet provided here: https://github.com/clockworkpi/DevTerm/blob/main/Schematics/ICNL9707_Datasheet.pdf
+
+Signed-off-by: Max Fierke <max@maxfierke.com>
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/gpu/drm/panel/Kconfig                 |  12 +
+ drivers/gpu/drm/panel/Makefile                |   1 +
+ .../gpu/drm/panel/panel-clockwork-cwd686.c    | 456 ++++++++++++++++++
+ 3 files changed, 469 insertions(+)
+ create mode 100644 drivers/gpu/drm/panel/panel-clockwork-cwd686.c
+
+--- a/drivers/gpu/drm/panel/Kconfig
++++ b/drivers/gpu/drm/panel/Kconfig
+@@ -68,6 +68,18 @@ config DRM_PANEL_BOE_TV101WUM_NL6
+ 	  Say Y here if you want to support for BOE TV101WUM and AUO KD101N80
+ 	  45NA WUXGA PANEL DSI Video Mode panel
+ 
++config DRM_PANEL_CLOCKWORK_CWD686
++	tristate "Clockwork CWD686 panel"
++	depends on OF
++	depends on DRM_MIPI_DSI
++	depends on BACKLIGHT_CLASS_DEVICE
++	help
++	  Say Y here if you want to enable support for the Clockwork CWD686
++	  ICNL9707-based panel, e.g. as used within the Clockwork DevTerm.
++	  The panel has a 480x1280 resolution and uses 24 bit RGB per pixel.
++
++	  To compile this driver as a module, choose M here.
++
+ config DRM_PANEL_DSI_CM
+ 	tristate "Generic DSI command mode panels"
+ 	depends on OF
+--- a/drivers/gpu/drm/panel/Makefile
++++ b/drivers/gpu/drm/panel/Makefile
+@@ -5,6 +5,7 @@ obj-$(CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_N
+ obj-$(CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0) += panel-boe-bf060y8m-aj0.o
+ obj-$(CONFIG_DRM_PANEL_BOE_HIMAX8279D) += panel-boe-himax8279d.o
+ obj-$(CONFIG_DRM_PANEL_BOE_TV101WUM_NL6) += panel-boe-tv101wum-nl6.o
++obj-$(CONFIG_DRM_PANEL_CLOCKWORK_CWD686) += panel-clockwork-cwd686.o
+ obj-$(CONFIG_DRM_PANEL_DSI_CM) += panel-dsi-cm.o
+ obj-$(CONFIG_DRM_PANEL_LVDS) += panel-lvds.o
+ obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o
+--- /dev/null
++++ b/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
+@@ -0,0 +1,456 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright (c) 2021 Clockwork Tech LLC
++ * Copyright (c) 2021-2022 Max Fierke <max@maxfierke.com>
++ *
++ * Based on Pinfan Zhu's work on panel-cwd686.c for ClockworkPi's 5.10 BSP
++ */
++
++#include <drm/drm_modes.h>
++#include <drm/drm_mipi_dsi.h>
++#include <drm/drm_panel.h>
++#include <linux/backlight.h>
++#include <linux/gpio/consumer.h>
++#include <linux/regulator/consumer.h>
++#include <linux/delay.h>
++#include <linux/of_device.h>
++#include <linux/module.h>
++#include <video/mipi_display.h>
++
++struct cwd686 {
++	struct device *dev;
++	struct drm_panel panel;
++	struct regulator *supply;
++	struct gpio_desc *enable_gpio;
++	struct gpio_desc *reset_gpio;
++	struct backlight_device *backlight;
++	enum drm_panel_orientation orientation;
++	bool prepared;
++	bool enabled;
++};
++
++static const struct drm_display_mode default_mode = {
++	.clock = 54465,
++	.hdisplay = 480,
++	.hsync_start = 480 + 150,
++	.hsync_end = 480 + 150 + 24,
++	.htotal = 480 + 150 + 24 + 40,
++	.vdisplay = 1280,
++	.vsync_start = 1280 + 12,
++	.vsync_end = 1280 + 12 + 6,
++	.vtotal = 1280 + 12 + 6 + 10,
++};
++
++static inline struct cwd686 *panel_to_cwd686(struct drm_panel *panel)
++{
++	return container_of(panel, struct cwd686, panel);
++}
++
++#define ICNL9707_DCS(seq...)                              \
++({                                                              \
++	static const u8 d[] = { seq };                          \
++	mipi_dsi_dcs_write_buffer(dsi, d, ARRAY_SIZE(d));	 \
++})
++
++#define ICNL9707_CMD_CGOUTL 0xB3
++#define ICNL9707_CMD_CGOUTR 0xB4
++#define ICNL9707_P_CGOUT_VGL 0x00
++#define ICNL9707_P_CGOUT_VGH 0x01
++#define ICNL9707_P_CGOUT_HZ 0x02
++#define ICNL9707_P_CGOUT_GND 0x03
++#define ICNL9707_P_CGOUT_GSP1 0x04
++#define ICNL9707_P_CGOUT_GSP2 0x05
++#define ICNL9707_P_CGOUT_GSP3 0x06
++#define ICNL9707_P_CGOUT_GSP4 0x07
++#define ICNL9707_P_CGOUT_GSP5 0x08
++#define ICNL9707_P_CGOUT_GSP6 0x09
++#define ICNL9707_P_CGOUT_GSP7 0x0A
++#define ICNL9707_P_CGOUT_GSP8 0x0B
++#define ICNL9707_P_CGOUT_GCK1 0x0C
++#define ICNL9707_P_CGOUT_GCK2 0x0D
++#define ICNL9707_P_CGOUT_GCK3 0x0E
++#define ICNL9707_P_CGOUT_GCK4 0x0F
++#define ICNL9707_P_CGOUT_GCK5 0x10
++#define ICNL9707_P_CGOUT_GCK6 0x11
++#define ICNL9707_P_CGOUT_GCK7 0x12
++#define ICNL9707_P_CGOUT_GCK8 0x13
++#define ICNL9707_P_CGOUT_GCK9 0x14
++#define ICNL9707_P_CGOUT_GCK10 0x15
++#define ICNL9707_P_CGOUT_GCK11 0x16
++#define ICNL9707_P_CGOUT_GCK12 0x17
++#define ICNL9707_P_CGOUT_GCK13 0x18
++#define ICNL9707_P_CGOUT_GCK14 0x19
++#define ICNL9707_P_CGOUT_GCK15 0x1A
++#define ICNL9707_P_CGOUT_GCK16 0x1B
++#define ICNL9707_P_CGOUT_DIR 0x1C
++#define ICNL9707_P_CGOUT_DIRB 0x1D
++#define ICNL9707_P_CGOUT_ECLK_AC 0x1E
++#define ICNL9707_P_CGOUT_ECLK_ACB 0x1F
++#define ICNL9707_P_CGOUT_ECLK_AC2 0x20
++#define ICNL9707_P_CGOUT_ECLK_AC2B 0x21
++#define ICNL9707_P_CGOUT_GCH 0x22
++#define ICNL9707_P_CGOUT_GCL 0x23
++#define ICNL9707_P_CGOUT_XDON 0x24
++#define ICNL9707_P_CGOUT_XDONB 0x25
++
++#define ICNL9707_MADCTL_ML  0x10
++#define ICNL9707_MADCTL_RGB 0x00
++#define ICNL9707_MADCTL_BGR 0x08
++#define ICNL9707_MADCTL_MH  0x04
++
++#define ICNL9707_CMD_PWRCON_VCOM 0xB6
++#define ICNL9707_P_PWRCON_VCOM_0495V 0x0D
++
++#define ICNL9707_CMD_PWRCON_SEQ 0xB7
++#define ICNL9707_CMD_PWRCON_CLK 0xB8
++#define ICNL9707_CMD_PWRCON_BTA 0xB9
++#define ICNL9707_CMD_PWRCON_MODE 0xBA
++#define ICNL9707_CMD_PWRCON_REG 0xBD
++
++#define ICNL9707_CMD_TCON 0xC1
++#define ICNL9707_CMD_TCON2 0xC2
++#define ICNL9707_CMD_TCON3 0xC3
++#define ICNL9707_CMD_SRC_TIM 0xC6
++#define ICNL9707_CMD_SRCCON 0xC7
++#define ICNL9707_CMD_SET_GAMMA 0xC8
++
++#define ICNL9707_CMD_ETC 0xD0
++
++#define ICNL9707_CMD_PASSWORD1 0xF0
++#define ICNL9707_P_PASSWORD1_DEFAULT 0xA5
++#define ICNL9707_P_PASSWORD1_ENABLE_LVL2 0x5A
++
++#define ICNL9707_CMD_PASSWORD2 0xF1
++#define ICNL9707_P_PASSWORD2_DEFAULT 0x5A
++#define ICNL9707_P_PASSWORD2_ENABLE_LVL2 0xA5
++
++static int cwd686_init_sequence(struct cwd686 *ctx)
++{
++	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
++	int err;
++
++	/* Enable access to Level 2 registers */
++	ICNL9707_DCS(ICNL9707_CMD_PASSWORD1,
++		     ICNL9707_P_PASSWORD1_ENABLE_LVL2,
++		     ICNL9707_P_PASSWORD1_ENABLE_LVL2);
++	ICNL9707_DCS(ICNL9707_CMD_PASSWORD2,
++		     ICNL9707_P_PASSWORD2_ENABLE_LVL2,
++		     ICNL9707_P_PASSWORD2_ENABLE_LVL2);
++
++	/* Set PWRCON_VCOM (-0.495V, -0.495V) */
++	ICNL9707_DCS(ICNL9707_CMD_PWRCON_VCOM,
++		     ICNL9707_P_PWRCON_VCOM_0495V,
++		     ICNL9707_P_PWRCON_VCOM_0495V);
++
++	/* Map ASG output signals */
++	ICNL9707_DCS(ICNL9707_CMD_CGOUTR,
++		     ICNL9707_P_CGOUT_GSP7, ICNL9707_P_CGOUT_GSP5,
++		     ICNL9707_P_CGOUT_GCK7, ICNL9707_P_CGOUT_GCK5,
++		     ICNL9707_P_CGOUT_GCK3, ICNL9707_P_CGOUT_GCK1,
++		     ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_VGL,
++		     ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_GND,
++		     ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_GND,
++		     ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
++		     ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
++		     ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
++		     ICNL9707_P_CGOUT_GSP1, ICNL9707_P_CGOUT_GSP3);
++	ICNL9707_DCS(ICNL9707_CMD_CGOUTL,
++		     ICNL9707_P_CGOUT_GSP8, ICNL9707_P_CGOUT_GSP6,
++		     ICNL9707_P_CGOUT_GCK8, ICNL9707_P_CGOUT_GCK6,
++		     ICNL9707_P_CGOUT_GCK4, ICNL9707_P_CGOUT_GCK2,
++		     ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_VGL,
++		     ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_GND,
++		     ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_GND,
++		     ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
++		     ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
++		     ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
++		     ICNL9707_P_CGOUT_GSP2, ICNL9707_P_CGOUT_GSP4);
++
++	/* Undocumented commands provided by the vendor */
++	ICNL9707_DCS(0xB0, 0x54, 0x32, 0x23, 0x45, 0x44, 0x44, 0x44, 0x44, 0x90, 0x01, 0x90, 0x01);
++	ICNL9707_DCS(0xB1, 0x32, 0x84, 0x02, 0x83, 0x30, 0x01, 0x6B, 0x01);
++	ICNL9707_DCS(0xB2, 0x73);
++
++	ICNL9707_DCS(ICNL9707_CMD_PWRCON_REG,
++		     0x4E, 0x0E, 0x50, 0x50, 0x26,
++		     0x1D, 0x00, 0x14, 0x42, 0x03);
++	ICNL9707_DCS(ICNL9707_CMD_PWRCON_SEQ,
++		     0x01, 0x01, 0x09, 0x11, 0x0D, 0x55,
++		     0x19, 0x19, 0x21, 0x1D, 0x00, 0x00,
++		     0x00, 0x00, 0x02, 0xFF, 0x3C);
++	ICNL9707_DCS(ICNL9707_CMD_PWRCON_CLK, 0x23, 0x01, 0x30, 0x34, 0x63);
++
++	/* Disable abnormal power-off flag */
++	ICNL9707_DCS(ICNL9707_CMD_PWRCON_BTA, 0xA0, 0x22, 0x00, 0x44);
++
++	ICNL9707_DCS(ICNL9707_CMD_PWRCON_MODE, 0x12, 0x63);
++
++	/* Set VBP, VFP, VSW, HBP, HFP, HSW */
++	ICNL9707_DCS(ICNL9707_CMD_TCON, 0x0C, 0x16, 0x04, 0x0C, 0x10, 0x04);
++
++	/* Set resolution */
++	ICNL9707_DCS(ICNL9707_CMD_TCON2, 0x11, 0x41);
++
++	/* Set frame blanking */
++	ICNL9707_DCS(ICNL9707_CMD_TCON3, 0x22, 0x31, 0x04);
++
++	ICNL9707_DCS(ICNL9707_CMD_SRCCON, 0x05, 0x23, 0x6B, 0x49, 0x00);
++
++	/* Another undocumented command */
++	ICNL9707_DCS(0xC5, 0x00);
++
++	ICNL9707_DCS(ICNL9707_CMD_ETC, 0x37, 0xFF, 0xFF);
++
++	/* Another set of undocumented commands */
++	ICNL9707_DCS(0xD2, 0x63, 0x0B, 0x08, 0x88);
++	ICNL9707_DCS(0xD3, 0x01, 0x00, 0x00, 0x01, 0x01, 0x37, 0x25, 0x38, 0x31, 0x06, 0x07);
++
++	/* Set Gamma to 2.2 */
++	ICNL9707_DCS(ICNL9707_CMD_SET_GAMMA,
++		     0x7C, 0x6A, 0x5D, 0x53, 0x53, 0x45, 0x4B,
++		     0x35, 0x4D, 0x4A, 0x49, 0x66, 0x53, 0x57,
++		     0x4A, 0x48, 0x3B, 0x2A, 0x06, 0x7C, 0x6A,
++		     0x5D, 0x53, 0x53, 0x45, 0x4B, 0x35, 0x4D,
++		     0x4A, 0x49, 0x66, 0x53, 0x57, 0x4A, 0x48,
++		     0x3B, 0x2A, 0x06);
++
++	ICNL9707_DCS(ICNL9707_CMD_SRC_TIM, 0x00, 0x00, 0xFF, 0x00, 0x00, 0xFF, 0x00, 0x00);
++
++	/* Another undocumented command */
++	ICNL9707_DCS(0xF4, 0x08, 0x77);
++
++	ICNL9707_DCS(MIPI_DCS_SET_ADDRESS_MODE,
++		     ICNL9707_MADCTL_RGB | ICNL9707_MADCTL_ML | ICNL9707_MADCTL_MH);
++
++	/* Enable tearing mode at VBLANK */
++	err = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
++	if (err) {
++		dev_err(ctx->dev, "failed to enable vblank TE (%d)\n", err);
++		return err;
++	}
++
++	/* Disable access to Level 2 registers */
++	ICNL9707_DCS(ICNL9707_CMD_PASSWORD2,
++		     ICNL9707_P_PASSWORD2_DEFAULT,
++		     ICNL9707_P_PASSWORD2_DEFAULT);
++	ICNL9707_DCS(ICNL9707_CMD_PASSWORD1,
++		     ICNL9707_P_PASSWORD1_DEFAULT,
++		     ICNL9707_P_PASSWORD1_DEFAULT);
++
++	return 0;
++}
++
++static int cwd686_disable(struct drm_panel *panel)
++{
++	struct cwd686 *ctx = panel_to_cwd686(panel);
++
++	if (!ctx->enabled)
++		return 0;
++
++	backlight_disable(ctx->backlight);
++
++	ctx->enabled = false;
++
++	return 0;
++}
++
++static int cwd686_unprepare(struct drm_panel *panel)
++{
++	struct cwd686 *ctx = panel_to_cwd686(panel);
++	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
++	int err;
++
++	if (!ctx->prepared)
++		return 0;
++
++	err = mipi_dsi_dcs_set_display_off(dsi);
++	if (err) {
++		dev_err(ctx->dev, "failed to turn display off (%d)\n", err);
++		return err;
++	}
++
++	err = mipi_dsi_dcs_enter_sleep_mode(dsi);
++	if (err) {
++		dev_err(ctx->dev, "failed to enter sleep mode (%d)\n", err);
++		return err;
++	}
++
++	msleep(120);
++
++	gpiod_set_value_cansleep(ctx->reset_gpio, 1);
++
++	ctx->prepared = false;
++
++	return 0;
++}
++
++static int cwd686_prepare(struct drm_panel *panel)
++{
++	struct cwd686 *ctx = panel_to_cwd686(panel);
++	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
++	int err;
++
++	if (ctx->prepared)
++		return 0;
++
++	gpiod_set_value_cansleep(ctx->reset_gpio, 1);
++	/* T2 */
++	msleep(10);
++
++	gpiod_set_value_cansleep(ctx->reset_gpio, 0);
++	/* T3 */
++	msleep(20);
++
++	/* Exit sleep mode and power on */
++
++	err = cwd686_init_sequence(ctx);
++	if (err) {
++		dev_err(ctx->dev, "failed to initialize display (%d)\n", err);
++		return err;
++	}
++
++	err = mipi_dsi_dcs_exit_sleep_mode(dsi);
++	if (err) {
++		dev_err(ctx->dev, "failed to exit sleep mode (%d)\n", err);
++		return err;
++	}
++	/* T6 */
++	msleep(120);
++
++	err = mipi_dsi_dcs_set_display_on(dsi);
++	if (err) {
++		dev_err(ctx->dev, "failed to turn display on (%d)\n", err);
++		return err;
++	}
++	msleep(20);
++
++	ctx->prepared = true;
++
++	return 0;
++}
++
++static int cwd686_enable(struct drm_panel *panel)
++{
++	struct cwd686 *ctx = panel_to_cwd686(panel);
++
++	if (ctx->enabled)
++		return 0;
++
++	backlight_enable(ctx->backlight);
++
++	ctx->enabled = true;
++
++	return 0;
++}
++
++static int cwd686_get_modes(struct drm_panel *panel, struct drm_connector *connector)
++{
++	struct cwd686 *ctx = panel_to_cwd686(panel);
++	struct drm_display_mode *mode;
++
++	mode = drm_mode_duplicate(connector->dev, &default_mode);
++	if (!mode) {
++		dev_err(panel->dev, "bad mode or failed to add mode\n");
++		return -EINVAL;
++	}
++	drm_mode_set_name(mode);
++	mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
++
++	connector->display_info.width_mm = mode->width_mm;
++	connector->display_info.height_mm = mode->height_mm;
++
++	/* set up connector's "panel orientation" property */
++	drm_connector_set_panel_orientation(connector, ctx->orientation);
++
++	drm_mode_probed_add(connector, mode);
++
++	return 1; /* Number of modes */
++}
++
++static const struct drm_panel_funcs cwd686_drm_funcs = {
++	.disable = cwd686_disable,
++	.unprepare = cwd686_unprepare,
++	.prepare = cwd686_prepare,
++	.enable = cwd686_enable,
++	.get_modes = cwd686_get_modes,
++};
++
++static int cwd686_probe(struct mipi_dsi_device *dsi)
++{
++	struct device *dev = &dsi->dev;
++	struct cwd686 *ctx;
++	int err;
++
++	ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
++	if (!ctx)
++		return -ENOMEM;
++
++	mipi_dsi_set_drvdata(dsi, ctx);
++	ctx->dev = dev;
++
++	dsi->lanes = 4;
++	dsi->format = MIPI_DSI_FMT_RGB888;
++	dsi->mode_flags = MIPI_DSI_MODE_VIDEO |
++			  MIPI_DSI_MODE_VIDEO_BURST |
++			  MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
++
++	ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
++	if (IS_ERR(ctx->reset_gpio)) {
++		err = PTR_ERR(ctx->reset_gpio);
++		if (err != -EPROBE_DEFER)
++			dev_err(dev, "failed to request GPIO (%d)\n", err);
++		return err;
++	}
++
++	ctx->backlight = devm_of_find_backlight(dev);
++	if (IS_ERR(ctx->backlight))
++		return PTR_ERR(ctx->backlight);
++
++	err = of_drm_get_panel_orientation(dev->of_node, &ctx->orientation);
++	if (err) {
++		dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err);
++		return err;
++	}
++
++	drm_panel_init(&ctx->panel, dev, &cwd686_drm_funcs, DRM_MODE_CONNECTOR_DSI);
++
++	drm_panel_add(&ctx->panel);
++
++	err = mipi_dsi_attach(dsi);
++	if (err < 0) {
++		dev_err(dev, "mipi_dsi_attach() failed: %d\n", err);
++		drm_panel_remove(&ctx->panel);
++		return err;
++	}
++
++	return 0;
++}
++
++static void cwd686_remove(struct mipi_dsi_device *dsi)
++{
++	struct cwd686 *ctx = mipi_dsi_get_drvdata(dsi);
++
++	mipi_dsi_detach(dsi);
++	drm_panel_remove(&ctx->panel);
++}
++
++static const struct of_device_id cwd686_of_match[] = {
++	{ .compatible = "clockwork,cwd686" },
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, cwd686_of_match);
++
++static struct mipi_dsi_driver cwd686_driver = {
++	.probe = cwd686_probe,
++	.remove = cwd686_remove,
++	.driver = {
++		.name = "panel-clockwork-cwd686",
++		.of_match_table = cwd686_of_match,
++	},
++};
++module_mipi_dsi_driver(cwd686_driver);
++
++MODULE_AUTHOR("Pinfan Zhu <zhu@clockworkpi.com>");
++MODULE_AUTHOR("Max Fierke <max@maxfierke.com>");
++MODULE_DESCRIPTION("ClockworkPi CWD686 panel driver");
++MODULE_LICENSE("GPL");
diff --git a/target/linux/d1/patches-6.1/0108-drm-panel-cwd686-Add-regulators.patch b/target/linux/d1/patches-6.1/0108-drm-panel-cwd686-Add-regulators.patch
new file mode 100644
index 00000000000000..60b21168b5de27
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0108-drm-panel-cwd686-Add-regulators.patch
@@ -0,0 +1,66 @@
+From 979271f803c1578087a965a2a4b845c87e7d922f Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 7 Aug 2022 19:14:21 -0500
+Subject: [PATCH 108/117] drm: panel: cwd686: Add regulators
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ .../gpu/drm/panel/panel-clockwork-cwd686.c    | 26 ++++++++++++++++++-
+ 1 file changed, 25 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
++++ b/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
+@@ -20,7 +20,8 @@
+ struct cwd686 {
+ 	struct device *dev;
+ 	struct drm_panel panel;
+-	struct regulator *supply;
++	struct regulator *iovcc;
++	struct regulator *vci;
+ 	struct gpio_desc *enable_gpio;
+ 	struct gpio_desc *reset_gpio;
+ 	struct backlight_device *backlight;
+@@ -279,6 +280,9 @@ static int cwd686_unprepare(struct drm_p
+ 
+ 	gpiod_set_value_cansleep(ctx->reset_gpio, 1);
+ 
++	regulator_disable(ctx->vci);
++	regulator_disable(ctx->iovcc);
++
+ 	ctx->prepared = false;
+ 
+ 	return 0;
+@@ -293,6 +297,18 @@ static int cwd686_prepare(struct drm_pan
+ 	if (ctx->prepared)
+ 		return 0;
+ 
++	err = regulator_enable(ctx->iovcc);
++	if (err) {
++		dev_err(ctx->dev, "failed to enable iovcc (%d)\n", err);
++		return err;
++	}
++
++	err = regulator_enable(ctx->vci);
++	if (err) {
++		dev_err(ctx->dev, "failed to enable vci (%d)\n", err);
++		return err;
++	}
++
+ 	gpiod_set_value_cansleep(ctx->reset_gpio, 1);
+ 	/* T2 */
+ 	msleep(10);
+@@ -402,6 +418,14 @@ static int cwd686_probe(struct mipi_dsi_
+ 		return err;
+ 	}
+ 
++	ctx->iovcc = devm_regulator_get(dev, "iovcc");
++	if (IS_ERR(ctx->iovcc))
++		return PTR_ERR(ctx->iovcc);
++
++	ctx->vci = devm_regulator_get(dev, "vci");
++	if (IS_ERR(ctx->vci))
++		return PTR_ERR(ctx->vci);
++
+ 	ctx->backlight = devm_of_find_backlight(dev);
+ 	if (IS_ERR(ctx->backlight))
+ 		return PTR_ERR(ctx->backlight);
diff --git a/target/linux/d1/patches-6.1/0109-drm-panel-cwd686-Make-reset-gpio-mandatory.patch b/target/linux/d1/patches-6.1/0109-drm-panel-cwd686-Make-reset-gpio-mandatory.patch
new file mode 100644
index 00000000000000..786273bcfd82dc
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0109-drm-panel-cwd686-Make-reset-gpio-mandatory.patch
@@ -0,0 +1,21 @@
+From 6112585994a6bdbd882709e7187c8c9289211b3b Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 7 Aug 2022 19:16:03 -0500
+Subject: [PATCH 109/117] drm: panel: cwd686: Make reset gpio mandatory
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/gpu/drm/panel/panel-clockwork-cwd686.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
++++ b/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
+@@ -410,7 +410,7 @@ static int cwd686_probe(struct mipi_dsi_
+ 			  MIPI_DSI_MODE_VIDEO_BURST |
+ 			  MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
+ 
+-	ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
++	ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
+ 	if (IS_ERR(ctx->reset_gpio)) {
+ 		err = PTR_ERR(ctx->reset_gpio);
+ 		if (err != -EPROBE_DEFER)
diff --git a/target/linux/d1/patches-6.1/0110-drm-panel-cwd686-Increase-post-reset-delay.patch b/target/linux/d1/patches-6.1/0110-drm-panel-cwd686-Increase-post-reset-delay.patch
new file mode 100644
index 00000000000000..6551348a4fc305
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0110-drm-panel-cwd686-Increase-post-reset-delay.patch
@@ -0,0 +1,21 @@
+From 8d70f9f4a66522c2720de986623d1130337ff670 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 7 Aug 2022 19:16:18 -0500
+Subject: [PATCH 110/117] drm: panel: cwd686: Increase post-reset delay
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/gpu/drm/panel/panel-clockwork-cwd686.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
++++ b/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
+@@ -315,7 +315,7 @@ static int cwd686_prepare(struct drm_pan
+ 
+ 	gpiod_set_value_cansleep(ctx->reset_gpio, 0);
+ 	/* T3 */
+-	msleep(20);
++	msleep(120);
+ 
+ 	/* Exit sleep mode and power on */
+ 
diff --git a/target/linux/d1/patches-6.1/0111-drm-panel-cwd686-Use-vendor-panel-init-sequence.patch b/target/linux/d1/patches-6.1/0111-drm-panel-cwd686-Use-vendor-panel-init-sequence.patch
new file mode 100644
index 00000000000000..df68d1855794c7
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0111-drm-panel-cwd686-Use-vendor-panel-init-sequence.patch
@@ -0,0 +1,171 @@
+From 8fc2a02d1d2e98a01a2dad3bf3da8e33366725eb Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 7 Aug 2022 19:17:35 -0500
+Subject: [PATCH 111/117] drm: panel: cwd686: Use vendor panel init sequence
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ .../gpu/drm/panel/panel-clockwork-cwd686.c    | 142 ++++--------------
+ 1 file changed, 32 insertions(+), 110 deletions(-)
+
+--- a/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
++++ b/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
+@@ -47,10 +47,12 @@ static inline struct cwd686 *panel_to_cw
+ 	return container_of(panel, struct cwd686, panel);
+ }
+ 
+-#define ICNL9707_DCS(seq...)                              \
++#define dcs_write_seq(seq...)                              \
+ ({                                                              \
+ 	static const u8 d[] = { seq };                          \
+-	mipi_dsi_dcs_write_buffer(dsi, d, ARRAY_SIZE(d));	 \
++	ssize_t r = mipi_dsi_dcs_write_buffer(dsi, d, ARRAY_SIZE(d));	 \
++	if (r < 0) \
++		return r; \
+ })
+ 
+ #define ICNL9707_CMD_CGOUTL 0xB3
+@@ -128,115 +130,35 @@ static inline struct cwd686 *panel_to_cw
+ static int cwd686_init_sequence(struct cwd686 *ctx)
+ {
+ 	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
+-	int err;
+ 
+-	/* Enable access to Level 2 registers */
+-	ICNL9707_DCS(ICNL9707_CMD_PASSWORD1,
+-		     ICNL9707_P_PASSWORD1_ENABLE_LVL2,
+-		     ICNL9707_P_PASSWORD1_ENABLE_LVL2);
+-	ICNL9707_DCS(ICNL9707_CMD_PASSWORD2,
+-		     ICNL9707_P_PASSWORD2_ENABLE_LVL2,
+-		     ICNL9707_P_PASSWORD2_ENABLE_LVL2);
+-
+-	/* Set PWRCON_VCOM (-0.495V, -0.495V) */
+-	ICNL9707_DCS(ICNL9707_CMD_PWRCON_VCOM,
+-		     ICNL9707_P_PWRCON_VCOM_0495V,
+-		     ICNL9707_P_PWRCON_VCOM_0495V);
+-
+-	/* Map ASG output signals */
+-	ICNL9707_DCS(ICNL9707_CMD_CGOUTR,
+-		     ICNL9707_P_CGOUT_GSP7, ICNL9707_P_CGOUT_GSP5,
+-		     ICNL9707_P_CGOUT_GCK7, ICNL9707_P_CGOUT_GCK5,
+-		     ICNL9707_P_CGOUT_GCK3, ICNL9707_P_CGOUT_GCK1,
+-		     ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_VGL,
+-		     ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_GND,
+-		     ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_GND,
+-		     ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
+-		     ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
+-		     ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
+-		     ICNL9707_P_CGOUT_GSP1, ICNL9707_P_CGOUT_GSP3);
+-	ICNL9707_DCS(ICNL9707_CMD_CGOUTL,
+-		     ICNL9707_P_CGOUT_GSP8, ICNL9707_P_CGOUT_GSP6,
+-		     ICNL9707_P_CGOUT_GCK8, ICNL9707_P_CGOUT_GCK6,
+-		     ICNL9707_P_CGOUT_GCK4, ICNL9707_P_CGOUT_GCK2,
+-		     ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_VGL,
+-		     ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_GND,
+-		     ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_GND,
+-		     ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
+-		     ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
+-		     ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
+-		     ICNL9707_P_CGOUT_GSP2, ICNL9707_P_CGOUT_GSP4);
+-
+-	/* Undocumented commands provided by the vendor */
+-	ICNL9707_DCS(0xB0, 0x54, 0x32, 0x23, 0x45, 0x44, 0x44, 0x44, 0x44, 0x90, 0x01, 0x90, 0x01);
+-	ICNL9707_DCS(0xB1, 0x32, 0x84, 0x02, 0x83, 0x30, 0x01, 0x6B, 0x01);
+-	ICNL9707_DCS(0xB2, 0x73);
+-
+-	ICNL9707_DCS(ICNL9707_CMD_PWRCON_REG,
+-		     0x4E, 0x0E, 0x50, 0x50, 0x26,
+-		     0x1D, 0x00, 0x14, 0x42, 0x03);
+-	ICNL9707_DCS(ICNL9707_CMD_PWRCON_SEQ,
+-		     0x01, 0x01, 0x09, 0x11, 0x0D, 0x55,
+-		     0x19, 0x19, 0x21, 0x1D, 0x00, 0x00,
+-		     0x00, 0x00, 0x02, 0xFF, 0x3C);
+-	ICNL9707_DCS(ICNL9707_CMD_PWRCON_CLK, 0x23, 0x01, 0x30, 0x34, 0x63);
+-
+-	/* Disable abnormal power-off flag */
+-	ICNL9707_DCS(ICNL9707_CMD_PWRCON_BTA, 0xA0, 0x22, 0x00, 0x44);
+-
+-	ICNL9707_DCS(ICNL9707_CMD_PWRCON_MODE, 0x12, 0x63);
+-
+-	/* Set VBP, VFP, VSW, HBP, HFP, HSW */
+-	ICNL9707_DCS(ICNL9707_CMD_TCON, 0x0C, 0x16, 0x04, 0x0C, 0x10, 0x04);
+-
+-	/* Set resolution */
+-	ICNL9707_DCS(ICNL9707_CMD_TCON2, 0x11, 0x41);
+-
+-	/* Set frame blanking */
+-	ICNL9707_DCS(ICNL9707_CMD_TCON3, 0x22, 0x31, 0x04);
+-
+-	ICNL9707_DCS(ICNL9707_CMD_SRCCON, 0x05, 0x23, 0x6B, 0x49, 0x00);
+-
+-	/* Another undocumented command */
+-	ICNL9707_DCS(0xC5, 0x00);
+-
+-	ICNL9707_DCS(ICNL9707_CMD_ETC, 0x37, 0xFF, 0xFF);
+-
+-	/* Another set of undocumented commands */
+-	ICNL9707_DCS(0xD2, 0x63, 0x0B, 0x08, 0x88);
+-	ICNL9707_DCS(0xD3, 0x01, 0x00, 0x00, 0x01, 0x01, 0x37, 0x25, 0x38, 0x31, 0x06, 0x07);
+-
+-	/* Set Gamma to 2.2 */
+-	ICNL9707_DCS(ICNL9707_CMD_SET_GAMMA,
+-		     0x7C, 0x6A, 0x5D, 0x53, 0x53, 0x45, 0x4B,
+-		     0x35, 0x4D, 0x4A, 0x49, 0x66, 0x53, 0x57,
+-		     0x4A, 0x48, 0x3B, 0x2A, 0x06, 0x7C, 0x6A,
+-		     0x5D, 0x53, 0x53, 0x45, 0x4B, 0x35, 0x4D,
+-		     0x4A, 0x49, 0x66, 0x53, 0x57, 0x4A, 0x48,
+-		     0x3B, 0x2A, 0x06);
+-
+-	ICNL9707_DCS(ICNL9707_CMD_SRC_TIM, 0x00, 0x00, 0xFF, 0x00, 0x00, 0xFF, 0x00, 0x00);
+-
+-	/* Another undocumented command */
+-	ICNL9707_DCS(0xF4, 0x08, 0x77);
+-
+-	ICNL9707_DCS(MIPI_DCS_SET_ADDRESS_MODE,
+-		     ICNL9707_MADCTL_RGB | ICNL9707_MADCTL_ML | ICNL9707_MADCTL_MH);
+-
+-	/* Enable tearing mode at VBLANK */
+-	err = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
+-	if (err) {
+-		dev_err(ctx->dev, "failed to enable vblank TE (%d)\n", err);
+-		return err;
+-	}
+-
+-	/* Disable access to Level 2 registers */
+-	ICNL9707_DCS(ICNL9707_CMD_PASSWORD2,
+-		     ICNL9707_P_PASSWORD2_DEFAULT,
+-		     ICNL9707_P_PASSWORD2_DEFAULT);
+-	ICNL9707_DCS(ICNL9707_CMD_PASSWORD1,
+-		     ICNL9707_P_PASSWORD1_DEFAULT,
+-		     ICNL9707_P_PASSWORD1_DEFAULT);
++	dcs_write_seq(0xF0,0x5A,0x5A);
++	dcs_write_seq(0xF1,0xA5,0xA5);
++	dcs_write_seq(0xB6,0x0D,0x0D);
++	dcs_write_seq(0xB4,0x0A,0x08,0x12,0x10,0x0E,0x0C,0x00,0x00,0x00,0x03,0x00,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x04,0x06);
++	dcs_write_seq(0xB3,0x0B,0x09,0x13,0x11,0x0F,0x0D,0x00,0x00,0x00,0x03,0x00,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x05,0x07);
++	dcs_write_seq(0xB0,0x54,0x32,0x23,0x45,0x44,0x44,0x44,0x44,0x90,0x01,0x90,0x01);
++	dcs_write_seq(0xB1,0x32,0x84,0x02,0x83,0x30,0x01,0x6B,0x01);
++	dcs_write_seq(0xB2,0x73);
++	dcs_write_seq(0xBD,0x4E,0x0E,0x50,0x50,0x26,0x1D,0x00,0x14,0x42,0x03);
++	dcs_write_seq(0xB7,0x01,0x01,0x09,0x11,0x0D,0x55,0x19,0x19,0x21,0x1D,0x00,0x00,0x00,0x00,0x02,0xFF,0x3C);
++	dcs_write_seq(0xB8,0x23,0x01,0x30,0x34,0x63);
++	dcs_write_seq(0xB9,0xA0,0x22,0x00,0x44);
++	dcs_write_seq(0xBA,0x12,0x63);
++	dcs_write_seq(0xC1,0x0C,0x16,0x04,0x0C,0x10,0x04);
++	dcs_write_seq(0xC2,0x11,0x41);
++	dcs_write_seq(0xC3,0x22,0x31,0x04);
++	dcs_write_seq(0xC7,0x05,0x23,0x6B,0x49,0x00);
++	dcs_write_seq(0xC5,0x00);
++	dcs_write_seq(0xD0,0x37,0xFF,0xFF);
++	dcs_write_seq(0xD2,0x63,0x0B,0x08,0x88);
++	dcs_write_seq(0xD3,0x01,0x00,0x00,0x01,0x01,0x37,0x25,0x38,0x31,0x06,0x07);
++	dcs_write_seq(0xC8,0x7C,0x6A,0x5D,0x53,0x53,0x45,0x4B,0x35,0x4D,0x4A,0x49,0x66,0x53,0x57,0x4A,0x48,0x3B,0x2A,0x06,0x7C,0x6A,0x5D,0x53,0x53,0x45,0x4B,0x35,0x4D,0x4A,0x49,0x66,0x53,0x57,0x4A,0x48,0x3B,0x2A,0x06);//GAMMA2.2
++	dcs_write_seq(0xC6,0x00,0x00,0xFF,0x00,0x00,0xFF,0x00,0x00);
++	dcs_write_seq(0xF4,0x08,0x77);
++	dcs_write_seq(0x36,0x14);
++	dcs_write_seq(0x35,0x00);
++	dcs_write_seq(0xF1,0x5A,0x5A);
++	dcs_write_seq(0xF0,0xA5,0xA5);
+ 
+ 	return 0;
+ }
diff --git a/target/linux/d1/patches-6.1/0112-drm-panel-cwd686-Fix-timings.patch b/target/linux/d1/patches-6.1/0112-drm-panel-cwd686-Fix-timings.patch
new file mode 100644
index 00000000000000..08c0f59eed30ba
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0112-drm-panel-cwd686-Fix-timings.patch
@@ -0,0 +1,37 @@
+From 6ea428297717faa16056076f7dd5a69e49c58fe6 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 7 Aug 2022 23:34:35 -0500
+Subject: [PATCH 112/117] drm: panel: cwd686: Fix timings
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/gpu/drm/panel/panel-clockwork-cwd686.c | 18 +++++++++---------
+ 1 file changed, 9 insertions(+), 9 deletions(-)
+
+--- a/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
++++ b/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
+@@ -31,15 +31,15 @@ struct cwd686 {
+ };
+ 
+ static const struct drm_display_mode default_mode = {
+-	.clock = 54465,
+-	.hdisplay = 480,
+-	.hsync_start = 480 + 150,
+-	.hsync_end = 480 + 150 + 24,
+-	.htotal = 480 + 150 + 24 + 40,
+-	.vdisplay = 1280,
+-	.vsync_start = 1280 + 12,
+-	.vsync_end = 1280 + 12 + 6,
+-	.vtotal = 1280 + 12 + 6 + 10,
++	.clock		= 54465,
++	.hdisplay	= 480,
++	.hsync_start	= 480 + 64,
++	.hsync_end	= 480 + 64 + 40,
++	.htotal		= 480 + 64 + 40 + 110,
++	.vdisplay	= 1280,
++	.vsync_start	= 1280 + 16,
++	.vsync_end	= 1280 + 16 + 10,
++	.vtotal		= 1280 + 16 + 10 + 2,
+ };
+ 
+ static inline struct cwd686 *panel_to_cwd686(struct drm_panel *panel)
diff --git a/target/linux/d1/patches-6.1/0113-drm-panel-cwd686-Disable-burst.patch b/target/linux/d1/patches-6.1/0113-drm-panel-cwd686-Disable-burst.patch
new file mode 100644
index 00000000000000..5e732945a92d05
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0113-drm-panel-cwd686-Disable-burst.patch
@@ -0,0 +1,20 @@
+From 16359ba0c5f5011e4742672454b35ad91a02fabe Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Mon, 8 Aug 2022 00:30:17 -0500
+Subject: [PATCH 113/117] drm: panel: cwd686: Disable burst
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/gpu/drm/panel/panel-clockwork-cwd686.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+--- a/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
++++ b/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
+@@ -329,7 +329,6 @@ static int cwd686_probe(struct mipi_dsi_
+ 	dsi->lanes = 4;
+ 	dsi->format = MIPI_DSI_FMT_RGB888;
+ 	dsi->mode_flags = MIPI_DSI_MODE_VIDEO |
+-			  MIPI_DSI_MODE_VIDEO_BURST |
+ 			  MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
+ 
+ 	ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
diff --git a/target/linux/d1/patches-6.1/0114-drm-panel-cwd686-Use-the-init-sequence-from-the-R-01.patch b/target/linux/d1/patches-6.1/0114-drm-panel-cwd686-Use-the-init-sequence-from-the-R-01.patch
new file mode 100644
index 00000000000000..334f75c68befb6
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0114-drm-panel-cwd686-Use-the-init-sequence-from-the-R-01.patch
@@ -0,0 +1,67 @@
+From 02da00f2215f3d755ec806636fe499331870e8d6 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Tue, 9 Aug 2022 20:14:59 -0500
+Subject: [PATCH 114/117] drm: panel: cwd686: Use the init sequence from the
+ R-01 BSP
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ .../gpu/drm/panel/panel-clockwork-cwd686.c    | 44 ++++++++-----------
+ 1 file changed, 19 insertions(+), 25 deletions(-)
+
+--- a/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
++++ b/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
+@@ -131,34 +131,28 @@ static int cwd686_init_sequence(struct c
+ {
+ 	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
+ 
+-	dcs_write_seq(0xF0,0x5A,0x5A);
+-	dcs_write_seq(0xF1,0xA5,0xA5);
+-	dcs_write_seq(0xB6,0x0D,0x0D);
+-	dcs_write_seq(0xB4,0x0A,0x08,0x12,0x10,0x0E,0x0C,0x00,0x00,0x00,0x03,0x00,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x04,0x06);
+-	dcs_write_seq(0xB3,0x0B,0x09,0x13,0x11,0x0F,0x0D,0x00,0x00,0x00,0x03,0x00,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x05,0x07);
+-	dcs_write_seq(0xB0,0x54,0x32,0x23,0x45,0x44,0x44,0x44,0x44,0x90,0x01,0x90,0x01);
+-	dcs_write_seq(0xB1,0x32,0x84,0x02,0x83,0x30,0x01,0x6B,0x01);
++	dcs_write_seq(0xF0,0x5A,0x59);
++	dcs_write_seq(0xF1,0xA5,0xA6);
++	dcs_write_seq(0xB0,0x54,0x32,0x23,0x45,0x44,0x44,0x44,0x44,0x9F,0x00,0x01,0x9F,0x00,0x01);
++	dcs_write_seq(0xB1,0x32,0x84,0x02,0x83,0x29,0x06,0x06,0x72,0x06,0x06);
+ 	dcs_write_seq(0xB2,0x73);
+-	dcs_write_seq(0xBD,0x4E,0x0E,0x50,0x50,0x26,0x1D,0x00,0x14,0x42,0x03);
+-	dcs_write_seq(0xB7,0x01,0x01,0x09,0x11,0x0D,0x55,0x19,0x19,0x21,0x1D,0x00,0x00,0x00,0x00,0x02,0xFF,0x3C);
+-	dcs_write_seq(0xB8,0x23,0x01,0x30,0x34,0x63);
+-	dcs_write_seq(0xB9,0xA0,0x22,0x00,0x44);
+-	dcs_write_seq(0xBA,0x12,0x63);
+-	dcs_write_seq(0xC1,0x0C,0x16,0x04,0x0C,0x10,0x04);
+-	dcs_write_seq(0xC2,0x11,0x41);
+-	dcs_write_seq(0xC3,0x22,0x31,0x04);
+-	dcs_write_seq(0xC7,0x05,0x23,0x6B,0x49,0x00);
+-	dcs_write_seq(0xC5,0x00);
+-	dcs_write_seq(0xD0,0x37,0xFF,0xFF);
+-	dcs_write_seq(0xD2,0x63,0x0B,0x08,0x88);
+-	dcs_write_seq(0xD3,0x01,0x00,0x00,0x01,0x01,0x37,0x25,0x38,0x31,0x06,0x07);
+-	dcs_write_seq(0xC8,0x7C,0x6A,0x5D,0x53,0x53,0x45,0x4B,0x35,0x4D,0x4A,0x49,0x66,0x53,0x57,0x4A,0x48,0x3B,0x2A,0x06,0x7C,0x6A,0x5D,0x53,0x53,0x45,0x4B,0x35,0x4D,0x4A,0x49,0x66,0x53,0x57,0x4A,0x48,0x3B,0x2A,0x06);//GAMMA2.2
+-	dcs_write_seq(0xC6,0x00,0x00,0xFF,0x00,0x00,0xFF,0x00,0x00);
+-	dcs_write_seq(0xF4,0x08,0x77);
++	dcs_write_seq(0xB3,0x0B,0x09,0x13,0x11,0x0F,0x0D,0x00,0x00,0x00,0x03,0x00,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x05,0x07);
++	dcs_write_seq(0xB4,0x0A,0x08,0x12,0x10,0x0E,0x0C,0x00,0x00,0x00,0x03,0x00,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x04,0x06);
++	dcs_write_seq(0xB6,0x13,0x13);
++	dcs_write_seq(0xB8,0xB4,0x43,0x02,0xCC);
++	dcs_write_seq(0xB9,0xA5,0x20,0xFF,0xC8);
++	dcs_write_seq(0xBA,0x88,0x23);
++	dcs_write_seq(0xBD,0x43,0x0E,0x0E,0x50,0x50,0x29,0x10,0x03,0x44,0x03);
++	dcs_write_seq(0xC1,0x00,0x0C,0x16,0x04,0x00,0x30,0x10,0x04);
++	dcs_write_seq(0xC2,0x21,0x81);
++	dcs_write_seq(0xC3,0x02,0x30);
++	dcs_write_seq(0xC7,0x25,0x6A);
++	dcs_write_seq(0xC8,0x7C,0x68,0x59,0x4E,0x4B,0x3C,0x41,0x2B,0x44,0x43,0x43,0x60,0x4E,0x55,0x47,0x44,0x38,0x27,0x06,0x7C,0x68,0x59,0x4E,0x4B,0x3C,0x41,0x2B,0x44,0x43,0x43,0x60,0x4E,0x55,0x47,0x44,0x38,0x27,0x06);
++	dcs_write_seq(0xD4,0x00,0x00,0x00,0x32,0x04,0x51);
++	dcs_write_seq(0xF1,0x5A,0x59);
++	dcs_write_seq(0xF0,0xA5,0xA6);
+ 	dcs_write_seq(0x36,0x14);
+ 	dcs_write_seq(0x35,0x00);
+-	dcs_write_seq(0xF1,0x5A,0x5A);
+-	dcs_write_seq(0xF0,0xA5,0xA5);
+ 
+ 	return 0;
+ }
diff --git a/target/linux/d1/patches-6.1/0115-drm-panel-cwd686-Power-up-sequence.patch b/target/linux/d1/patches-6.1/0115-drm-panel-cwd686-Power-up-sequence.patch
new file mode 100644
index 00000000000000..149e42d0cc6044
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0115-drm-panel-cwd686-Power-up-sequence.patch
@@ -0,0 +1,27 @@
+From 6b438292e6b86a5cb5bffee2e517f1335903e39e Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Tue, 9 Aug 2022 20:15:24 -0500
+Subject: [PATCH 115/117] drm: panel: cwd686: Power up sequence
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/gpu/drm/panel/panel-clockwork-cwd686.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
++++ b/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
+@@ -218,12 +218,14 @@ static int cwd686_prepare(struct drm_pan
+ 		dev_err(ctx->dev, "failed to enable iovcc (%d)\n", err);
+ 		return err;
+ 	}
++	msleep(20);
+ 
+ 	err = regulator_enable(ctx->vci);
+ 	if (err) {
+ 		dev_err(ctx->dev, "failed to enable vci (%d)\n", err);
+ 		return err;
+ 	}
++	msleep(120);
+ 
+ 	gpiod_set_value_cansleep(ctx->reset_gpio, 1);
+ 	/* T2 */
diff --git a/target/linux/d1/patches-6.1/0116-drm-panel-cwd686-Why-is-this-not-getting-called.patch b/target/linux/d1/patches-6.1/0116-drm-panel-cwd686-Why-is-this-not-getting-called.patch
new file mode 100644
index 00000000000000..b46a58752ad20e
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0116-drm-panel-cwd686-Why-is-this-not-getting-called.patch
@@ -0,0 +1,21 @@
+From a19565eccfdc0fce7f41cfe70cd67a1a10d2113c Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Tue, 9 Aug 2022 20:15:39 -0500
+Subject: [PATCH 116/117] drm: panel: cwd686: Why is this not getting called?
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/gpu/drm/panel/panel-clockwork-cwd686.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
++++ b/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
+@@ -373,6 +373,8 @@ static void cwd686_remove(struct mipi_ds
+ 
+ 	mipi_dsi_detach(dsi);
+ 	drm_panel_remove(&ctx->panel);
++	if (ctx->prepared)
++		cwd686_unprepare(&ctx->panel);
+ }
+ 
+ static const struct of_device_id cwd686_of_match[] = {
diff --git a/target/linux/d1/patches-6.1/0117-riscv-dts-allwinner-d1-Add-video-engine-node.patch b/target/linux/d1/patches-6.1/0117-riscv-dts-allwinner-d1-Add-video-engine-node.patch
new file mode 100644
index 00000000000000..fd25a0af48c3d1
--- /dev/null
+++ b/target/linux/d1/patches-6.1/0117-riscv-dts-allwinner-d1-Add-video-engine-node.patch
@@ -0,0 +1,56 @@
+From d6036571b774437bb3bdd378821033e118a01fe8 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Wed, 2 Nov 2022 23:42:52 -0500
+Subject: [PATCH 117/117] riscv: dts: allwinner: d1: Add video engine node
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 30 ++++++++++++++++++++
+ 1 file changed, 30 insertions(+)
+
+--- a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
+@@ -105,6 +105,21 @@
+ 			status = "reserved";
+ 		};
+ 
++		ve: video-codec@1c0e000 {
++			compatible = "allwinner,sun20i-d1-video-engine";
++			reg = <0x1c0e000 0x2000>;
++			interrupts = <82 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_VE>,
++				 <&ccu CLK_VE>,
++				 <&ccu CLK_MBUS_VE>;
++			clock-names = "ahb", "mod", "ram";
++			resets = <&ccu RST_BUS_VE>;
++			allwinner,sram = <&ve_sram 1>;
++			interconnects = <&mbus 4>;
++			interconnect-names = "dma-mem";
++			iommus = <&iommu 0>;
++		};
++
+ 		pio: pinctrl@2000000 {
+ 			compatible = "allwinner,sun20i-d1-pinctrl";
+ 			reg = <0x2000000 0x800>;
+@@ -591,6 +606,21 @@
+ 			#address-cells = <1>;
+ 			#size-cells = <1>;
+ 
++			// FIXME: Address is not verified. It is copied from A64/H6.
++			sram@1d00000 {
++				compatible = "mmio-sram";
++				reg = <0x1d00000 0x40000>;
++				ranges = <0 0x1d00000 0x40000>;
++				#address-cells = <1>;
++				#size-cells = <1>;
++
++				ve_sram: sram-section@0 {
++					compatible = "allwinner,sun20i-d1-sram-c1",
++						     "allwinner,sun4i-a10-sram-c1";
++					reg = <0 0x40000>;
++				};
++			};
++
+ 			regulators@3000150 {
+ 				compatible = "allwinner,sun20i-d1-system-ldos";
+ 				reg = <0x3000150 0x4>;
diff --git a/target/linux/generic/backport-5.15/080-v5.17-clk-gate-Add-devm_clk_hw_register_gate.patch b/target/linux/generic/backport-5.15/080-v5.17-clk-gate-Add-devm_clk_hw_register_gate.patch
index 51c23b6e349501..819cc292e860ee 100644
--- a/target/linux/generic/backport-5.15/080-v5.17-clk-gate-Add-devm_clk_hw_register_gate.patch
+++ b/target/linux/generic/backport-5.15/080-v5.17-clk-gate-Add-devm_clk_hw_register_gate.patch
@@ -66,7 +66,7 @@ Link: https://lore.kernel.org/r/20211103085102.1656081-2-horatiu.vultur@microchi
 +EXPORT_SYMBOL_GPL(__devm_clk_hw_register_gate);
 --- a/include/linux/clk-provider.h
 +++ b/include/linux/clk-provider.h
-@@ -490,6 +490,13 @@ struct clk_hw *__clk_hw_register_gate(st
+@@ -517,6 +517,13 @@ struct clk_hw *__clk_hw_register_gate(st
  		unsigned long flags,
  		void __iomem *reg, u8 bit_idx,
  		u8 clk_gate_flags, spinlock_t *lock);
@@ -80,7 +80,7 @@ Link: https://lore.kernel.org/r/20211103085102.1656081-2-horatiu.vultur@microchi
  struct clk *clk_register_gate(struct device *dev, const char *name,
  		const char *parent_name, unsigned long flags,
  		void __iomem *reg, u8 bit_idx,
-@@ -544,6 +551,22 @@ struct clk *clk_register_gate(struct dev
+@@ -571,6 +578,22 @@ struct clk *clk_register_gate(struct dev
  	__clk_hw_register_gate((dev), NULL, (name), NULL, NULL, (parent_data), \
  			       (flags), (reg), (bit_idx),		      \
  			       (clk_gate_flags), (lock))
diff --git a/target/linux/generic/backport-5.15/738-v6.9-net-phy-aquantia-add-AQR111-and-AQR111B0-PHY-ID.patch b/target/linux/generic/backport-5.15/738-v6.9-net-phy-aquantia-add-AQR111-and-AQR111B0-PHY-ID.patch
new file mode 100644
index 00000000000000..d130794c08403e
--- /dev/null
+++ b/target/linux/generic/backport-5.15/738-v6.9-net-phy-aquantia-add-AQR111-and-AQR111B0-PHY-ID.patch
@@ -0,0 +1,100 @@
+From 038ba1dc4e54d51d953f5618d8eb5dd39bd9de25 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Tue, 13 Feb 2024 14:35:51 +0100
+Subject: [PATCH] net: phy: aquantia: add AQR111 and AQR111B0 PHY ID
+
+Add Aquantia AQR111 and AQR111B0 PHY ID. These PHY advertise 10G speed
+but actually supports up to 5G speed, hence some manual fixup is needed.
+
+The Aquantia AQR111B0 PHY is just a variant of the AQR111 with smaller
+chip size.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://lore.kernel.org/r/20240213133558.1836-1-ansuelsmth@gmail.com
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/phy/aquantia/aquantia_main.c | 52 ++++++++++++++++++++++++
+ 1 file changed, 52 insertions(+)
+
+--- a/drivers/net/phy/aquantia/aquantia_main.c
++++ b/drivers/net/phy/aquantia/aquantia_main.c
+@@ -22,6 +22,8 @@
+ #define PHY_ID_AQR107	0x03a1b4e0
+ #define PHY_ID_AQCS109	0x03a1b5c2
+ #define PHY_ID_AQR405	0x03a1b4b0
++#define PHY_ID_AQR111	0x03a1b610
++#define PHY_ID_AQR111B0	0x03a1b612
+ #define PHY_ID_AQR113C	0x31c31c12
+ 
+ #define MDIO_PHYXS_VEND_IF_STATUS		0xe812
+@@ -672,6 +674,16 @@ static int aqr107_probe(struct phy_devic
+ 	return aqr_hwmon_probe(phydev);
+ }
+ 
++static int aqr111_config_init(struct phy_device *phydev)
++{
++	/* AQR111 reports supporting speed up to 10G,
++	 * however only speeds up to 5G are supported.
++	 */
++	phy_set_max_speed(phydev, SPEED_5000);
++
++	return aqr107_config_init(phydev);
++}
++
+ static struct phy_driver aqr_driver[] = {
+ {
+ 	PHY_ID_MATCH_MODEL(PHY_ID_AQ1202),
+@@ -746,6 +758,42 @@ static struct phy_driver aqr_driver[] =
+ 	.link_change_notify = aqr107_link_change_notify,
+ },
+ {
++	PHY_ID_MATCH_MODEL(PHY_ID_AQR111),
++	.name		= "Aquantia AQR111",
++	.probe		= aqr107_probe,
++	.config_init	= aqr111_config_init,
++	.config_aneg    = aqr_config_aneg,
++	.config_intr	= aqr_config_intr,
++	.handle_interrupt = aqr_handle_interrupt,
++	.read_status	= aqr107_read_status,
++	.get_tunable    = aqr107_get_tunable,
++	.set_tunable    = aqr107_set_tunable,
++	.suspend	= aqr107_suspend,
++	.resume		= aqr107_resume,
++	.get_sset_count	= aqr107_get_sset_count,
++	.get_strings	= aqr107_get_strings,
++	.get_stats	= aqr107_get_stats,
++	.link_change_notify = aqr107_link_change_notify,
++},
++{
++	PHY_ID_MATCH_MODEL(PHY_ID_AQR111B0),
++	.name		= "Aquantia AQR111B0",
++	.probe		= aqr107_probe,
++	.config_init	= aqr111_config_init,
++	.config_aneg    = aqr_config_aneg,
++	.config_intr	= aqr_config_intr,
++	.handle_interrupt = aqr_handle_interrupt,
++	.read_status	= aqr107_read_status,
++	.get_tunable    = aqr107_get_tunable,
++	.set_tunable    = aqr107_set_tunable,
++	.suspend	= aqr107_suspend,
++	.resume		= aqr107_resume,
++	.get_sset_count	= aqr107_get_sset_count,
++	.get_strings	= aqr107_get_strings,
++	.get_stats	= aqr107_get_stats,
++	.link_change_notify = aqr107_link_change_notify,
++},
++{
+ 	PHY_ID_MATCH_MODEL(PHY_ID_AQR405),
+ 	.name		= "Aquantia AQR405",
+ 	.config_aneg    = aqr_config_aneg,
+@@ -784,6 +832,8 @@ static struct mdio_device_id __maybe_unu
+ 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR107) },
+ 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },
+ 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
++	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR111) },
++	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR111B0) },
+ 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
+ 	{ }
+ };
diff --git a/target/linux/generic/backport-5.15/739-v6.9-net-phy-aquantia-add-AQR113-PHY-ID.patch b/target/linux/generic/backport-5.15/739-v6.9-net-phy-aquantia-add-AQR113-PHY-ID.patch
new file mode 100644
index 00000000000000..5a46ab39cf061a
--- /dev/null
+++ b/target/linux/generic/backport-5.15/739-v6.9-net-phy-aquantia-add-AQR113-PHY-ID.patch
@@ -0,0 +1,59 @@
+From 71b605d32017e5b8d257db7344bc2f8e8fcc973e Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Thu, 15 Feb 2024 16:30:05 +0100
+Subject: [PATCH] net: phy: aquantia: add AQR113 PHY ID
+
+Add Aquantia AQR113 PHY ID. Aquantia AQR113 is just a chip size variant of
+the already supported AQR133C where the only difference is the PHY ID
+and the hw chip size.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/aquantia/aquantia_main.c | 21 +++++++++++++++++++++
+ 1 file changed, 21 insertions(+)
+
+--- a/drivers/net/phy/aquantia/aquantia_main.c
++++ b/drivers/net/phy/aquantia/aquantia_main.c
+@@ -24,6 +24,7 @@
+ #define PHY_ID_AQR405	0x03a1b4b0
+ #define PHY_ID_AQR111	0x03a1b610
+ #define PHY_ID_AQR111B0	0x03a1b612
++#define PHY_ID_AQR113	0x31c31c40
+ #define PHY_ID_AQR113C	0x31c31c12
+ 
+ #define MDIO_PHYXS_VEND_IF_STATUS		0xe812
+@@ -802,6 +803,24 @@ static struct phy_driver aqr_driver[] =
+ 	.read_status	= aqr_read_status,
+ },
+ {
++	PHY_ID_MATCH_MODEL(PHY_ID_AQR113),
++	.name		= "Aquantia AQR113",
++	.probe          = aqr107_probe,
++	.config_init    = aqr107_config_init,
++	.config_aneg    = aqr_config_aneg,
++	.config_intr    = aqr_config_intr,
++	.handle_interrupt       = aqr_handle_interrupt,
++	.read_status    = aqr107_read_status,
++	.get_tunable    = aqr107_get_tunable,
++	.set_tunable    = aqr107_set_tunable,
++	.suspend        = aqr107_suspend,
++	.resume         = aqr107_resume,
++	.get_sset_count = aqr107_get_sset_count,
++	.get_strings    = aqr107_get_strings,
++	.get_stats      = aqr107_get_stats,
++	.link_change_notify = aqr107_link_change_notify,
++},
++{
+ 	PHY_ID_MATCH_MODEL(PHY_ID_AQR113C),
+ 	.name           = "Aquantia AQR113C",
+ 	.probe          = aqr107_probe,
+@@ -834,6 +853,7 @@ static struct mdio_device_id __maybe_unu
+ 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
+ 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR111) },
+ 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR111B0) },
++	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113) },
+ 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
+ 	{ }
+ };
diff --git a/target/linux/generic/backport-5.15/740-v6.9-net-phy-aquantia-add-AQR813-PHY-ID.patch b/target/linux/generic/backport-5.15/740-v6.9-net-phy-aquantia-add-AQR813-PHY-ID.patch
new file mode 100644
index 00000000000000..49651a5e4f474c
--- /dev/null
+++ b/target/linux/generic/backport-5.15/740-v6.9-net-phy-aquantia-add-AQR813-PHY-ID.patch
@@ -0,0 +1,58 @@
+From 6d47302a3f0ba31445478d518d98bd55918bc8ab Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Thu, 15 Feb 2024 22:43:30 +0100
+Subject: [PATCH] net: phy: aquantia: add AQR813 PHY ID
+
+Aquantia AQR813 is the Octal Port variant of the AQR113. Add PHY ID for
+it to provide support for it.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/aquantia/aquantia_main.c | 21 +++++++++++++++++++++
+ 1 file changed, 21 insertions(+)
+
+--- a/drivers/net/phy/aquantia/aquantia_main.c
++++ b/drivers/net/phy/aquantia/aquantia_main.c
+@@ -26,6 +26,7 @@
+ #define PHY_ID_AQR111B0	0x03a1b612
+ #define PHY_ID_AQR113	0x31c31c40
+ #define PHY_ID_AQR113C	0x31c31c12
++#define PHY_ID_AQR813	0x31c31cb2
+ 
+ #define MDIO_PHYXS_VEND_IF_STATUS		0xe812
+ #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK	GENMASK(7, 3)
+@@ -839,6 +840,24 @@ static struct phy_driver aqr_driver[] =
+ 	.get_stats      = aqr107_get_stats,
+ 	.link_change_notify = aqr107_link_change_notify,
+ },
++{
++	PHY_ID_MATCH_MODEL(PHY_ID_AQR813),
++	.name		= "Aquantia AQR813",
++	.probe		= aqr107_probe,
++	.config_init	= aqr107_config_init,
++	.config_aneg    = aqr_config_aneg,
++	.config_intr	= aqr_config_intr,
++	.handle_interrupt = aqr_handle_interrupt,
++	.read_status	= aqr107_read_status,
++	.get_tunable    = aqr107_get_tunable,
++	.set_tunable    = aqr107_set_tunable,
++	.suspend	= aqr107_suspend,
++	.resume		= aqr107_resume,
++	.get_sset_count	= aqr107_get_sset_count,
++	.get_strings	= aqr107_get_strings,
++	.get_stats	= aqr107_get_stats,
++	.link_change_notify = aqr107_link_change_notify,
++},
+ };
+ 
+ module_phy_driver(aqr_driver);
+@@ -855,6 +874,7 @@ static struct mdio_device_id __maybe_unu
+ 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR111B0) },
+ 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113) },
+ 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
++	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR813) },
+ 	{ }
+ };
+ 
diff --git a/target/linux/generic/backport-5.15/775-v6.0-01-net-ethernet-stmicro-stmmac-move-queue-reset-to-dedi.patch b/target/linux/generic/backport-5.15/775-v6.0-01-net-ethernet-stmicro-stmmac-move-queue-reset-to-dedi.patch
index 3c10819b681375..931c589cfa3908 100644
--- a/target/linux/generic/backport-5.15/775-v6.0-01-net-ethernet-stmicro-stmmac-move-queue-reset-to-dedi.patch
+++ b/target/linux/generic/backport-5.15/775-v6.0-01-net-ethernet-stmicro-stmmac-move-queue-reset-to-dedi.patch
@@ -62,7 +62,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
  			    tx_q->dma_tx_phy, chan);
  	stmmac_start_tx_dma(priv, chan);
-@@ -3782,6 +3773,8 @@ static int stmmac_open(struct net_device
+@@ -3783,6 +3774,8 @@ static int stmmac_open(struct net_device
  		}
  	}
  
@@ -71,7 +71,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	ret = stmmac_hw_setup(dev, true);
  	if (ret < 0) {
  		netdev_err(priv->dev, "%s: Hw setup failed\n", __func__);
-@@ -6429,6 +6422,7 @@ void stmmac_enable_rx_queue(struct stmma
+@@ -6430,6 +6423,7 @@ void stmmac_enable_rx_queue(struct stmma
  		return;
  	}
  
@@ -79,7 +79,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	stmmac_clear_rx_descriptors(priv, queue);
  
  	stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
-@@ -6490,6 +6484,7 @@ void stmmac_enable_tx_queue(struct stmma
+@@ -6491,6 +6485,7 @@ void stmmac_enable_tx_queue(struct stmma
  		return;
  	}
  
@@ -87,7 +87,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	stmmac_clear_tx_descriptors(priv, queue);
  
  	stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
-@@ -7414,6 +7409,25 @@ int stmmac_suspend(struct device *dev)
+@@ -7415,6 +7410,25 @@ int stmmac_suspend(struct device *dev)
  }
  EXPORT_SYMBOL_GPL(stmmac_suspend);
  
@@ -113,7 +113,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  /**
   * stmmac_reset_queues_param - reset queue parameters
   * @priv: device pointer
-@@ -7424,22 +7438,11 @@ static void stmmac_reset_queues_param(st
+@@ -7425,22 +7439,11 @@ static void stmmac_reset_queues_param(st
  	u32 tx_cnt = priv->plat->tx_queues_to_use;
  	u32 queue;
  
diff --git a/target/linux/generic/backport-5.15/775-v6.0-02-net-ethernet-stmicro-stmmac-first-disable-all-queues.patch b/target/linux/generic/backport-5.15/775-v6.0-02-net-ethernet-stmicro-stmmac-first-disable-all-queues.patch
index 6e115834eb8911..8bdeef7a696f71 100644
--- a/target/linux/generic/backport-5.15/775-v6.0-02-net-ethernet-stmicro-stmmac-first-disable-all-queues.patch
+++ b/target/linux/generic/backport-5.15/775-v6.0-02-net-ethernet-stmicro-stmmac-first-disable-all-queues.patch
@@ -17,7 +17,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
 +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-@@ -3834,8 +3834,6 @@ static int stmmac_release(struct net_dev
+@@ -3835,8 +3835,6 @@ static int stmmac_release(struct net_dev
  	struct stmmac_priv *priv = netdev_priv(dev);
  	u32 chan;
  
@@ -26,7 +26,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	if (device_may_wakeup(priv->device))
  		phylink_speed_down(priv->phylink, false);
  	/* Stop and disconnect the PHY */
-@@ -3847,6 +3845,8 @@ static int stmmac_release(struct net_dev
+@@ -3848,6 +3846,8 @@ static int stmmac_release(struct net_dev
  	for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
  		hrtimer_cancel(&priv->tx_queue[chan].txtimer);
  
diff --git a/target/linux/generic/backport-5.15/775-v6.0-03-net-ethernet-stmicro-stmmac-move-dma-conf-to-dedicat.patch b/target/linux/generic/backport-5.15/775-v6.0-03-net-ethernet-stmicro-stmmac-move-dma-conf-to-dedicat.patch
index 99518b11a040ef..c59a5d1fe1782d 100644
--- a/target/linux/generic/backport-5.15/775-v6.0-03-net-ethernet-stmicro-stmmac-move-dma-conf-to-dedicat.patch
+++ b/target/linux/generic/backport-5.15/775-v6.0-03-net-ethernet-stmicro-stmmac-move-dma-conf-to-dedicat.patch
@@ -719,7 +719,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  			}
  		}
  
-@@ -3575,7 +3575,7 @@ static int stmmac_request_irq_multi_msi(
+@@ -3576,7 +3576,7 @@ static int stmmac_request_irq_multi_msi(
  		sprintf(int_name, "%s:%s-%d", dev->name, "rx", i);
  		ret = request_irq(priv->rx_irq[i],
  				  stmmac_msi_intr_rx,
@@ -728,7 +728,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		if (unlikely(ret < 0)) {
  			netdev_err(priv->dev,
  				   "%s: alloc rx-%d  MSI %d (error: %d)\n",
-@@ -3598,7 +3598,7 @@ static int stmmac_request_irq_multi_msi(
+@@ -3599,7 +3599,7 @@ static int stmmac_request_irq_multi_msi(
  		sprintf(int_name, "%s:%s-%d", dev->name, "tx", i);
  		ret = request_irq(priv->tx_irq[i],
  				  stmmac_msi_intr_tx,
@@ -737,7 +737,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		if (unlikely(ret < 0)) {
  			netdev_err(priv->dev,
  				   "%s: alloc tx-%d  MSI %d (error: %d)\n",
-@@ -3729,21 +3729,21 @@ static int stmmac_open(struct net_device
+@@ -3730,21 +3730,21 @@ static int stmmac_open(struct net_device
  		bfsize = 0;
  
  	if (bfsize < BUF_SIZE_16KiB)
@@ -766,7 +766,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		int tbs_en = priv->plat->tx_queues_cfg[chan].tbs_en;
  
  		/* Setup per-TXQ tbs flag before TX descriptor alloc */
-@@ -3801,7 +3801,7 @@ irq_error:
+@@ -3802,7 +3802,7 @@ irq_error:
  	phylink_stop(priv->phylink);
  
  	for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
@@ -775,7 +775,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	stmmac_hw_teardown(dev);
  init_error:
-@@ -3843,7 +3843,7 @@ static int stmmac_release(struct net_dev
+@@ -3844,7 +3844,7 @@ static int stmmac_release(struct net_dev
  	stmmac_disable_all_queues(priv);
  
  	for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
@@ -784,7 +784,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	netif_tx_disable(dev);
  
-@@ -3907,7 +3907,7 @@ static bool stmmac_vlan_insert(struct st
+@@ -3908,7 +3908,7 @@ static bool stmmac_vlan_insert(struct st
  		return false;
  
  	stmmac_set_tx_owner(priv, p);
@@ -793,7 +793,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	return true;
  }
  
-@@ -3925,7 +3925,7 @@ static bool stmmac_vlan_insert(struct st
+@@ -3926,7 +3926,7 @@ static bool stmmac_vlan_insert(struct st
  static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des,
  				 int total_len, bool last_segment, u32 queue)
  {
@@ -802,7 +802,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	struct dma_desc *desc;
  	u32 buff_size;
  	int tmp_len;
-@@ -3936,7 +3936,7 @@ static void stmmac_tso_allocator(struct
+@@ -3937,7 +3937,7 @@ static void stmmac_tso_allocator(struct
  		dma_addr_t curr_addr;
  
  		tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx,
@@ -811,7 +811,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
  
  		if (tx_q->tbs & STMMAC_TBS_AVAIL)
-@@ -3964,7 +3964,7 @@ static void stmmac_tso_allocator(struct
+@@ -3965,7 +3965,7 @@ static void stmmac_tso_allocator(struct
  
  static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue)
  {
@@ -820,7 +820,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	int desc_size;
  
  	if (likely(priv->extend_desc))
-@@ -4026,7 +4026,7 @@ static netdev_tx_t stmmac_tso_xmit(struc
+@@ -4027,7 +4027,7 @@ static netdev_tx_t stmmac_tso_xmit(struc
  	dma_addr_t des;
  	int i;
  
@@ -829,7 +829,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	first_tx = tx_q->cur_tx;
  
  	/* Compute header lengths */
-@@ -4066,7 +4066,7 @@ static netdev_tx_t stmmac_tso_xmit(struc
+@@ -4067,7 +4067,7 @@ static netdev_tx_t stmmac_tso_xmit(struc
  		stmmac_set_mss(priv, mss_desc, mss);
  		tx_q->mss = mss;
  		tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx,
@@ -838,7 +838,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
  	}
  
-@@ -4178,7 +4178,7 @@ static netdev_tx_t stmmac_tso_xmit(struc
+@@ -4179,7 +4179,7 @@ static netdev_tx_t stmmac_tso_xmit(struc
  	 * ndo_start_xmit will fill this descriptor the next time it's
  	 * called and stmmac_tx_clean may clean up to this descriptor.
  	 */
@@ -847,7 +847,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
  		netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
-@@ -4266,7 +4266,7 @@ static netdev_tx_t stmmac_xmit(struct sk
+@@ -4267,7 +4267,7 @@ static netdev_tx_t stmmac_xmit(struct sk
  	int entry, first_tx;
  	dma_addr_t des;
  
@@ -856,7 +856,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	first_tx = tx_q->cur_tx;
  
  	if (priv->tx_path_in_lpi_mode && priv->eee_sw_timer_en)
-@@ -4329,7 +4329,7 @@ static netdev_tx_t stmmac_xmit(struct sk
+@@ -4330,7 +4330,7 @@ static netdev_tx_t stmmac_xmit(struct sk
  		int len = skb_frag_size(frag);
  		bool last_segment = (i == (nfrags - 1));
  
@@ -865,7 +865,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		WARN_ON(tx_q->tx_skbuff[entry]);
  
  		if (likely(priv->extend_desc))
-@@ -4400,7 +4400,7 @@ static netdev_tx_t stmmac_xmit(struct sk
+@@ -4401,7 +4401,7 @@ static netdev_tx_t stmmac_xmit(struct sk
  	 * ndo_start_xmit will fill this descriptor the next time it's
  	 * called and stmmac_tx_clean may clean up to this descriptor.
  	 */
@@ -874,7 +874,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	tx_q->cur_tx = entry;
  
  	if (netif_msg_pktdata(priv)) {
-@@ -4512,7 +4512,7 @@ static void stmmac_rx_vlan(struct net_de
+@@ -4513,7 +4513,7 @@ static void stmmac_rx_vlan(struct net_de
   */
  static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue)
  {
@@ -883,7 +883,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	int dirty = stmmac_rx_dirty(priv, queue);
  	unsigned int entry = rx_q->dirty_rx;
  
-@@ -4562,7 +4562,7 @@ static inline void stmmac_rx_refill(stru
+@@ -4563,7 +4563,7 @@ static inline void stmmac_rx_refill(stru
  		dma_wmb();
  		stmmac_set_rx_owner(priv, p, use_rx_wd);
  
@@ -892,7 +892,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	}
  	rx_q->dirty_rx = entry;
  	rx_q->rx_tail_addr = rx_q->dma_rx_phy +
-@@ -4590,12 +4590,12 @@ static unsigned int stmmac_rx_buf1_len(s
+@@ -4591,12 +4591,12 @@ static unsigned int stmmac_rx_buf1_len(s
  
  	/* First descriptor, not last descriptor and not split header */
  	if (status & rx_not_ls)
@@ -907,7 +907,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  }
  
  static unsigned int stmmac_rx_buf2_len(struct stmmac_priv *priv,
-@@ -4611,7 +4611,7 @@ static unsigned int stmmac_rx_buf2_len(s
+@@ -4612,7 +4612,7 @@ static unsigned int stmmac_rx_buf2_len(s
  
  	/* Not last descriptor */
  	if (status & rx_not_ls)
@@ -916,7 +916,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	plen = stmmac_get_rx_frame_len(priv, p, coe);
  
-@@ -4622,7 +4622,7 @@ static unsigned int stmmac_rx_buf2_len(s
+@@ -4623,7 +4623,7 @@ static unsigned int stmmac_rx_buf2_len(s
  static int stmmac_xdp_xmit_xdpf(struct stmmac_priv *priv, int queue,
  				struct xdp_frame *xdpf, bool dma_map)
  {
@@ -925,7 +925,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	unsigned int entry = tx_q->cur_tx;
  	struct dma_desc *tx_desc;
  	dma_addr_t dma_addr;
-@@ -4685,7 +4685,7 @@ static int stmmac_xdp_xmit_xdpf(struct s
+@@ -4686,7 +4686,7 @@ static int stmmac_xdp_xmit_xdpf(struct s
  
  	stmmac_enable_dma_transmission(priv, priv->ioaddr);
  
@@ -934,7 +934,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	tx_q->cur_tx = entry;
  
  	return STMMAC_XDP_TX;
-@@ -4859,7 +4859,7 @@ static void stmmac_dispatch_skb_zc(struc
+@@ -4860,7 +4860,7 @@ static void stmmac_dispatch_skb_zc(struc
  
  static bool stmmac_rx_refill_zc(struct stmmac_priv *priv, u32 queue, u32 budget)
  {
@@ -943,7 +943,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	unsigned int entry = rx_q->dirty_rx;
  	struct dma_desc *rx_desc = NULL;
  	bool ret = true;
-@@ -4902,7 +4902,7 @@ static bool stmmac_rx_refill_zc(struct s
+@@ -4903,7 +4903,7 @@ static bool stmmac_rx_refill_zc(struct s
  		dma_wmb();
  		stmmac_set_rx_owner(priv, rx_desc, use_rx_wd);
  
@@ -952,7 +952,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	}
  
  	if (rx_desc) {
-@@ -4917,7 +4917,7 @@ static bool stmmac_rx_refill_zc(struct s
+@@ -4918,7 +4918,7 @@ static bool stmmac_rx_refill_zc(struct s
  
  static int stmmac_rx_zc(struct stmmac_priv *priv, int limit, u32 queue)
  {
@@ -961,7 +961,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	unsigned int count = 0, error = 0, len = 0;
  	int dirty = stmmac_rx_dirty(priv, queue);
  	unsigned int next_entry = rx_q->cur_rx;
-@@ -4939,7 +4939,7 @@ static int stmmac_rx_zc(struct stmmac_pr
+@@ -4940,7 +4940,7 @@ static int stmmac_rx_zc(struct stmmac_pr
  			desc_size = sizeof(struct dma_desc);
  		}
  
@@ -970,7 +970,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  				    rx_q->dma_rx_phy, desc_size);
  	}
  	while (count < limit) {
-@@ -4986,7 +4986,7 @@ read_again:
+@@ -4987,7 +4987,7 @@ read_again:
  
  		/* Prefetch the next RX descriptor */
  		rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx,
@@ -979,7 +979,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		next_entry = rx_q->cur_rx;
  
  		if (priv->extend_desc)
-@@ -5107,7 +5107,7 @@ read_again:
+@@ -5108,7 +5108,7 @@ read_again:
   */
  static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue)
  {
@@ -988,7 +988,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	struct stmmac_channel *ch = &priv->channel[queue];
  	unsigned int count = 0, error = 0, len = 0;
  	int status = 0, coe = priv->hw->rx_csum;
-@@ -5120,7 +5120,7 @@ static int stmmac_rx(struct stmmac_priv
+@@ -5121,7 +5121,7 @@ static int stmmac_rx(struct stmmac_priv
  	int buf_sz;
  
  	dma_dir = page_pool_get_dma_dir(rx_q->page_pool);
@@ -997,7 +997,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	if (netif_msg_rx_status(priv)) {
  		void *rx_head;
-@@ -5134,7 +5134,7 @@ static int stmmac_rx(struct stmmac_priv
+@@ -5135,7 +5135,7 @@ static int stmmac_rx(struct stmmac_priv
  			desc_size = sizeof(struct dma_desc);
  		}
  
@@ -1006,7 +1006,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  				    rx_q->dma_rx_phy, desc_size);
  	}
  	while (count < limit) {
-@@ -5178,7 +5178,7 @@ read_again:
+@@ -5179,7 +5179,7 @@ read_again:
  			break;
  
  		rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx,
@@ -1015,7 +1015,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		next_entry = rx_q->cur_rx;
  
  		if (priv->extend_desc)
-@@ -5312,7 +5312,7 @@ read_again:
+@@ -5313,7 +5313,7 @@ read_again:
  						buf1_len, dma_dir);
  			skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
  					buf->page, buf->page_offset, buf1_len,
@@ -1024,7 +1024,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  			/* Data payload appended into SKB */
  			page_pool_release_page(rx_q->page_pool, buf->page);
-@@ -5324,7 +5324,7 @@ read_again:
+@@ -5325,7 +5325,7 @@ read_again:
  						buf2_len, dma_dir);
  			skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
  					buf->sec_page, 0, buf2_len,
@@ -1033,7 +1033,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  			/* Data payload appended into SKB */
  			page_pool_release_page(rx_q->page_pool, buf->sec_page);
-@@ -5767,11 +5767,13 @@ static irqreturn_t stmmac_safety_interru
+@@ -5768,11 +5768,13 @@ static irqreturn_t stmmac_safety_interru
  static irqreturn_t stmmac_msi_intr_tx(int irq, void *data)
  {
  	struct stmmac_tx_queue *tx_q = (struct stmmac_tx_queue *)data;
@@ -1048,7 +1048,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	if (unlikely(!data)) {
  		netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
-@@ -5811,10 +5813,12 @@ static irqreturn_t stmmac_msi_intr_tx(in
+@@ -5812,10 +5814,12 @@ static irqreturn_t stmmac_msi_intr_tx(in
  static irqreturn_t stmmac_msi_intr_rx(int irq, void *data)
  {
  	struct stmmac_rx_queue *rx_q = (struct stmmac_rx_queue *)data;
@@ -1062,7 +1062,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	if (unlikely(!data)) {
  		netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
-@@ -5845,10 +5849,10 @@ static void stmmac_poll_controller(struc
+@@ -5846,10 +5850,10 @@ static void stmmac_poll_controller(struc
  
  	if (priv->plat->multi_msi_en) {
  		for (i = 0; i < priv->plat->rx_queues_to_use; i++)
@@ -1075,7 +1075,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	} else {
  		disable_irq(dev->irq);
  		stmmac_interrupt(dev->irq, dev);
-@@ -6029,34 +6033,34 @@ static int stmmac_rings_status_show(stru
+@@ -6030,34 +6034,34 @@ static int stmmac_rings_status_show(stru
  		return 0;
  
  	for (queue = 0; queue < rx_count; queue++) {
@@ -1116,7 +1116,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		}
  	}
  
-@@ -6403,7 +6407,7 @@ void stmmac_disable_rx_queue(struct stmm
+@@ -6404,7 +6408,7 @@ void stmmac_disable_rx_queue(struct stmm
  
  void stmmac_enable_rx_queue(struct stmmac_priv *priv, u32 queue)
  {
@@ -1125,7 +1125,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	struct stmmac_channel *ch = &priv->channel[queue];
  	unsigned long flags;
  	u32 buf_size;
-@@ -6440,7 +6444,7 @@ void stmmac_enable_rx_queue(struct stmma
+@@ -6441,7 +6445,7 @@ void stmmac_enable_rx_queue(struct stmma
  				      rx_q->queue_index);
  	} else {
  		stmmac_set_dma_bfsize(priv, priv->ioaddr,
@@ -1134,7 +1134,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  				      rx_q->queue_index);
  	}
  
-@@ -6466,7 +6470,7 @@ void stmmac_disable_tx_queue(struct stmm
+@@ -6467,7 +6471,7 @@ void stmmac_disable_tx_queue(struct stmm
  
  void stmmac_enable_tx_queue(struct stmmac_priv *priv, u32 queue)
  {
@@ -1143,7 +1143,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	struct stmmac_channel *ch = &priv->channel[queue];
  	unsigned long flags;
  	int ret;
-@@ -6516,7 +6520,7 @@ void stmmac_xdp_release(struct net_devic
+@@ -6517,7 +6521,7 @@ void stmmac_xdp_release(struct net_devic
  	stmmac_disable_all_queues(priv);
  
  	for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
@@ -1152,7 +1152,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	/* Free the IRQ lines */
  	stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0);
-@@ -6575,7 +6579,7 @@ int stmmac_xdp_open(struct net_device *d
+@@ -6576,7 +6580,7 @@ int stmmac_xdp_open(struct net_device *d
  
  	/* DMA RX Channel Configuration */
  	for (chan = 0; chan < rx_cnt; chan++) {
@@ -1161,7 +1161,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  		stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
  				    rx_q->dma_rx_phy, chan);
-@@ -6593,7 +6597,7 @@ int stmmac_xdp_open(struct net_device *d
+@@ -6594,7 +6598,7 @@ int stmmac_xdp_open(struct net_device *d
  					      rx_q->queue_index);
  		} else {
  			stmmac_set_dma_bfsize(priv, priv->ioaddr,
@@ -1170,7 +1170,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  					      rx_q->queue_index);
  		}
  
-@@ -6602,7 +6606,7 @@ int stmmac_xdp_open(struct net_device *d
+@@ -6603,7 +6607,7 @@ int stmmac_xdp_open(struct net_device *d
  
  	/* DMA TX Channel Configuration */
  	for (chan = 0; chan < tx_cnt; chan++) {
@@ -1179,7 +1179,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  		stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
  				    tx_q->dma_tx_phy, chan);
-@@ -6635,7 +6639,7 @@ int stmmac_xdp_open(struct net_device *d
+@@ -6636,7 +6640,7 @@ int stmmac_xdp_open(struct net_device *d
  
  irq_error:
  	for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
@@ -1188,7 +1188,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	stmmac_hw_teardown(dev);
  init_error:
-@@ -6662,8 +6666,8 @@ int stmmac_xsk_wakeup(struct net_device
+@@ -6663,8 +6667,8 @@ int stmmac_xsk_wakeup(struct net_device
  	    queue >= priv->plat->tx_queues_to_use)
  		return -EINVAL;
  
@@ -1199,7 +1199,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	ch = &priv->channel[queue];
  
  	if (!rx_q->xsk_pool && !tx_q->xsk_pool)
-@@ -6923,8 +6927,8 @@ int stmmac_reinit_ringparam(struct net_d
+@@ -6924,8 +6928,8 @@ int stmmac_reinit_ringparam(struct net_d
  	if (netif_running(dev))
  		stmmac_release(dev);
  
@@ -1210,7 +1210,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	if (netif_running(dev))
  		ret = stmmac_open(dev);
-@@ -7359,7 +7363,7 @@ int stmmac_suspend(struct device *dev)
+@@ -7360,7 +7364,7 @@ int stmmac_suspend(struct device *dev)
  	stmmac_disable_all_queues(priv);
  
  	for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
@@ -1219,7 +1219,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	if (priv->eee_enabled) {
  		priv->tx_path_in_lpi_mode = false;
-@@ -7411,7 +7415,7 @@ EXPORT_SYMBOL_GPL(stmmac_suspend);
+@@ -7412,7 +7416,7 @@ EXPORT_SYMBOL_GPL(stmmac_suspend);
  
  static void stmmac_reset_rx_queue(struct stmmac_priv *priv, u32 queue)
  {
@@ -1228,7 +1228,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	rx_q->cur_rx = 0;
  	rx_q->dirty_rx = 0;
-@@ -7419,7 +7423,7 @@ static void stmmac_reset_rx_queue(struct
+@@ -7420,7 +7424,7 @@ static void stmmac_reset_rx_queue(struct
  
  static void stmmac_reset_tx_queue(struct stmmac_priv *priv, u32 queue)
  {
diff --git a/target/linux/generic/backport-5.15/775-v6.0-04-net-ethernet-stmicro-stmmac-generate-stmmac-dma-conf.patch b/target/linux/generic/backport-5.15/775-v6.0-04-net-ethernet-stmicro-stmmac-generate-stmmac-dma-conf.patch
index 7336456c0c0e9b..bdf8b8585e214e 100644
--- a/target/linux/generic/backport-5.15/775-v6.0-04-net-ethernet-stmicro-stmmac-generate-stmmac-dma-conf.patch
+++ b/target/linux/generic/backport-5.15/775-v6.0-04-net-ethernet-stmicro-stmmac-generate-stmmac-dma-conf.patch
@@ -860,7 +860,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	stmmac_reset_tx_queue(priv, chan);
  	stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
  			    tx_q->dma_tx_phy, chan);
-@@ -3685,19 +3748,93 @@ static int stmmac_request_irq(struct net
+@@ -3686,19 +3749,93 @@ static int stmmac_request_irq(struct net
  }
  
  /**
@@ -957,7 +957,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	u32 chan;
  	int ret;
  
-@@ -3724,45 +3861,10 @@ static int stmmac_open(struct net_device
+@@ -3725,45 +3862,10 @@ static int stmmac_open(struct net_device
  	memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
  	priv->xstats.threshold = tc;
  
@@ -1005,7 +1005,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	if (priv->plat->serdes_powerup) {
  		ret = priv->plat->serdes_powerup(dev, priv->plat->bsp_priv);
-@@ -3805,14 +3907,28 @@ irq_error:
+@@ -3806,14 +3908,28 @@ irq_error:
  
  	stmmac_hw_teardown(dev);
  init_error:
@@ -1036,7 +1036,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  static void stmmac_fpe_stop_wq(struct stmmac_priv *priv)
  {
  	set_bit(__FPE_REMOVING, &priv->fpe_task_state);
-@@ -3859,7 +3975,7 @@ static int stmmac_release(struct net_dev
+@@ -3860,7 +3976,7 @@ static int stmmac_release(struct net_dev
  	stmmac_stop_all_dma(priv);
  
  	/* Release and free the Rx/Tx resources */
@@ -1045,7 +1045,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	/* Disable the MAC Rx/Tx */
  	stmmac_mac_set(priv, priv->ioaddr, false);
-@@ -6402,7 +6518,7 @@ void stmmac_disable_rx_queue(struct stmm
+@@ -6403,7 +6519,7 @@ void stmmac_disable_rx_queue(struct stmm
  	spin_unlock_irqrestore(&ch->lock, flags);
  
  	stmmac_stop_rx_dma(priv, queue);
@@ -1054,7 +1054,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  }
  
  void stmmac_enable_rx_queue(struct stmmac_priv *priv, u32 queue)
-@@ -6413,21 +6529,21 @@ void stmmac_enable_rx_queue(struct stmma
+@@ -6414,21 +6530,21 @@ void stmmac_enable_rx_queue(struct stmma
  	u32 buf_size;
  	int ret;
  
@@ -1080,7 +1080,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
  			    rx_q->dma_rx_phy, rx_q->queue_index);
-@@ -6465,7 +6581,7 @@ void stmmac_disable_tx_queue(struct stmm
+@@ -6466,7 +6582,7 @@ void stmmac_disable_tx_queue(struct stmm
  	spin_unlock_irqrestore(&ch->lock, flags);
  
  	stmmac_stop_tx_dma(priv, queue);
@@ -1089,7 +1089,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  }
  
  void stmmac_enable_tx_queue(struct stmmac_priv *priv, u32 queue)
-@@ -6475,21 +6591,21 @@ void stmmac_enable_tx_queue(struct stmma
+@@ -6476,21 +6592,21 @@ void stmmac_enable_tx_queue(struct stmma
  	unsigned long flags;
  	int ret;
  
@@ -1115,7 +1115,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
  			    tx_q->dma_tx_phy, tx_q->queue_index);
-@@ -6529,7 +6645,7 @@ void stmmac_xdp_release(struct net_devic
+@@ -6530,7 +6646,7 @@ void stmmac_xdp_release(struct net_devic
  	stmmac_stop_all_dma(priv);
  
  	/* Release and free the Rx/Tx resources */
@@ -1124,7 +1124,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	/* Disable the MAC Rx/Tx */
  	stmmac_mac_set(priv, priv->ioaddr, false);
-@@ -6554,14 +6670,14 @@ int stmmac_xdp_open(struct net_device *d
+@@ -6555,14 +6671,14 @@ int stmmac_xdp_open(struct net_device *d
  	u32 chan;
  	int ret;
  
@@ -1141,7 +1141,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	if (ret < 0) {
  		netdev_err(dev, "%s: DMA descriptors initialization failed\n",
  			   __func__);
-@@ -6643,7 +6759,7 @@ irq_error:
+@@ -6644,7 +6760,7 @@ irq_error:
  
  	stmmac_hw_teardown(dev);
  init_error:
@@ -1150,7 +1150,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  dma_desc_error:
  	return ret;
  }
-@@ -7506,7 +7622,7 @@ int stmmac_resume(struct device *dev)
+@@ -7507,7 +7623,7 @@ int stmmac_resume(struct device *dev)
  	stmmac_reset_queues_param(priv);
  
  	stmmac_free_tx_skbufs(priv);
diff --git a/target/linux/generic/backport-5.15/775-v6.0-05-net-ethernet-stmicro-stmmac-permit-MTU-change-with-i.patch b/target/linux/generic/backport-5.15/775-v6.0-05-net-ethernet-stmicro-stmmac-permit-MTU-change-with-i.patch
index 6ebb527726e440..2576df45224db1 100644
--- a/target/linux/generic/backport-5.15/775-v6.0-05-net-ethernet-stmicro-stmmac-permit-MTU-change-with-i.patch
+++ b/target/linux/generic/backport-5.15/775-v6.0-05-net-ethernet-stmicro-stmmac-permit-MTU-change-with-i.patch
@@ -19,7 +19,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
 +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-@@ -5624,18 +5624,15 @@ static int stmmac_change_mtu(struct net_
+@@ -5625,18 +5625,15 @@ static int stmmac_change_mtu(struct net_
  {
  	struct stmmac_priv *priv = netdev_priv(dev);
  	int txfifosz = priv->plat->tx_fifo_size;
@@ -40,7 +40,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	if (stmmac_xdp_is_enabled(priv) && new_mtu > ETH_DATA_LEN) {
  		netdev_dbg(priv->dev, "Jumbo frames not supported for XDP\n");
  		return -EINVAL;
-@@ -5647,8 +5644,29 @@ static int stmmac_change_mtu(struct net_
+@@ -5648,8 +5645,29 @@ static int stmmac_change_mtu(struct net_
  	if ((txfifosz < new_mtu) || (new_mtu > BUF_SIZE_16KiB))
  		return -EINVAL;
  
diff --git a/target/linux/generic/backport-5.15/826-v5.17-of-base-make-small-of_parse_phandle-variants-static-.patch b/target/linux/generic/backport-5.15/826-v5.17-of-base-make-small-of_parse_phandle-variants-static-.patch
index b00cf5741991d0..0ad89de56007bd 100644
--- a/target/linux/generic/backport-5.15/826-v5.17-of-base-make-small-of_parse_phandle-variants-static-.patch
+++ b/target/linux/generic/backport-5.15/826-v5.17-of-base-make-small-of_parse_phandle-variants-static-.patch
@@ -128,7 +128,7 @@ Link: https://lore.kernel.org/r/20220118173504.2867523-2-michael@walle.cc
  
  /**
   * of_parse_phandle_with_args_map() - Find a node pointed by phandle in a list and remap it
-@@ -1684,47 +1612,6 @@ free:
+@@ -1685,47 +1613,6 @@ free:
  EXPORT_SYMBOL(of_parse_phandle_with_args_map);
  
  /**
@@ -200,7 +200,7 @@ Link: https://lore.kernel.org/r/20220118173504.2867523-2-michael@walle.cc
  extern int of_count_phandle_with_args(const struct device_node *np,
  	const char *list_name, const char *cells_name);
  
-@@ -864,18 +858,12 @@ static inline int of_property_read_strin
+@@ -714,18 +708,12 @@ static inline int of_property_read_strin
  	return -ENOSYS;
  }
  
@@ -225,7 +225,7 @@ Link: https://lore.kernel.org/r/20220118173504.2867523-2-michael@walle.cc
  {
  	return -ENOSYS;
  }
-@@ -889,13 +877,6 @@ static inline int of_parse_phandle_with_
+@@ -739,13 +727,6 @@ static inline int of_parse_phandle_with_
  	return -ENOSYS;
  }
  
@@ -239,7 +239,7 @@ Link: https://lore.kernel.org/r/20220118173504.2867523-2-michael@walle.cc
  static inline int of_count_phandle_with_args(const struct device_node *np,
  					     const char *list_name,
  					     const char *cells_name)
-@@ -1077,6 +1058,117 @@ static inline bool of_node_is_type(const
+@@ -927,6 +908,117 @@ static inline bool of_node_is_type(const
  }
  
  /**
diff --git a/target/linux/generic/backport-5.15/827-v6.3-0001-of-base-add-of_parse_phandle_with_optional_args.patch b/target/linux/generic/backport-5.15/827-v6.3-0001-of-base-add-of_parse_phandle_with_optional_args.patch
index 2b2a60e096bef2..97f4c6981e211b 100644
--- a/target/linux/generic/backport-5.15/827-v6.3-0001-of-base-add-of_parse_phandle_with_optional_args.patch
+++ b/target/linux/generic/backport-5.15/827-v6.3-0001-of-base-add-of_parse_phandle_with_optional_args.patch
@@ -24,7 +24,7 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 
 --- a/include/linux/of.h
 +++ b/include/linux/of.h
-@@ -1169,6 +1169,31 @@ static inline int of_parse_phandle_with_
+@@ -1019,6 +1019,31 @@ static inline int of_parse_phandle_with_
  }
  
  /**
diff --git a/target/linux/generic/backport-5.15/828-v6.4-0004-of-Move-of_modalias-to-module.c.patch b/target/linux/generic/backport-5.15/828-v6.4-0004-of-Move-of_modalias-to-module.c.patch
index a70c6f2eec8cd7..b4554b2ecad28c 100644
--- a/target/linux/generic/backport-5.15/828-v6.4-0004-of-Move-of_modalias-to-module.c.patch
+++ b/target/linux/generic/backport-5.15/828-v6.4-0004-of-Move-of_modalias-to-module.c.patch
@@ -145,7 +145,7 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  /* phandle iterator functions */
  extern int of_phandle_iterator_init(struct of_phandle_iterator *it,
  				    const struct device_node *np,
-@@ -885,6 +888,12 @@ static inline int of_count_phandle_with_
+@@ -735,6 +738,12 @@ static inline int of_count_phandle_with_
  	return -ENOSYS;
  }
  
diff --git a/target/linux/generic/backport-5.15/828-v6.4-0005-of-Move-the-request-module-helper-logic-to-module.c.patch b/target/linux/generic/backport-5.15/828-v6.4-0005-of-Move-the-request-module-helper-logic-to-module.c.patch
index 06bc24ca6e3753..ad42039e112aee 100644
--- a/target/linux/generic/backport-5.15/828-v6.4-0005-of-Move-the-request-module-helper-logic-to-module.c.patch
+++ b/target/linux/generic/backport-5.15/828-v6.4-0005-of-Move-the-request-module-helper-logic-to-module.c.patch
@@ -117,7 +117,7 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  
  /* phandle iterator functions */
  extern int of_phandle_iterator_init(struct of_phandle_iterator *it,
-@@ -893,6 +894,11 @@ static inline ssize_t of_modalias(const
+@@ -743,6 +744,11 @@ static inline ssize_t of_modalias(const
  {
  	return -ENODEV;
  }
diff --git a/target/linux/generic/backport-5.15/830-v6.7-3-leds-turris-omnia-Support-HW-controlled-mode-via-pri.patch b/target/linux/generic/backport-5.15/830-v6.7-3-leds-turris-omnia-Support-HW-controlled-mode-via-pri.patch
index dd2b310d66feb0..7f6bac37dd15ec 100644
--- a/target/linux/generic/backport-5.15/830-v6.7-3-leds-turris-omnia-Support-HW-controlled-mode-via-pri.patch
+++ b/target/linux/generic/backport-5.15/830-v6.7-3-leds-turris-omnia-Support-HW-controlled-mode-via-pri.patch
@@ -48,7 +48,7 @@ Signed-off-by: Lee Jones <lee@kernel.org>
 
 --- a/drivers/leds/Kconfig
 +++ b/drivers/leds/Kconfig
-@@ -163,6 +163,7 @@ config LEDS_TURRIS_OMNIA
+@@ -164,6 +164,7 @@ config LEDS_TURRIS_OMNIA
  	depends on I2C
  	depends on MACH_ARMADA_38X || COMPILE_TEST
  	depends on OF
diff --git a/target/linux/generic/backport-6.1/424-v6.3-mtd-ubi-wire-up-parent-MTD-device.patch b/target/linux/generic/backport-6.1/424-v6.3-mtd-ubi-wire-up-parent-MTD-device.patch
new file mode 100644
index 00000000000000..657404196d37d3
--- /dev/null
+++ b/target/linux/generic/backport-6.1/424-v6.3-mtd-ubi-wire-up-parent-MTD-device.patch
@@ -0,0 +1,33 @@
+From 1ecf9e390452e73a362ea7fbde8f3f0db83de856 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Thu, 22 Dec 2022 19:33:04 +0000
+Subject: [PATCH] mtd: ubi: wire-up parent MTD device
+
+Wire up the device parent pointer of UBI devices to their lower MTD
+device, typically an MTD partition or whole-chip device.
+
+The most noticeable change is that in sysfs, previously ubi devices
+would be could in /sys/devices/virtual/ubi while after this change they
+would be correctly attached to their parent MTD device, e.g.
+
+/sys/devices/platform/1100d000.spi/spi_master/spi1/spi1.0/mtd/mtd2/ubi0.
+
+Locating UBI devices using /sys/class/ubi/ of course still works as
+well.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: Richard Weinberger <richard@nod.at>
+---
+ drivers/mtd/ubi/build.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/mtd/ubi/build.c
++++ b/drivers/mtd/ubi/build.c
+@@ -929,6 +929,7 @@ int ubi_attach_mtd_dev(struct mtd_info *
+ 	ubi->dev.release = dev_release;
+ 	ubi->dev.class = &ubi_class;
+ 	ubi->dev.groups = ubi_dev_groups;
++	ubi->dev.parent = &mtd->dev;
+ 
+ 	ubi->mtd = mtd;
+ 	ubi->ubi_num = ubi_num;
diff --git a/target/linux/generic/backport-6.1/425-v6.3-mtd-ubi-block-wire-up-device-parent.patch b/target/linux/generic/backport-6.1/425-v6.3-mtd-ubi-block-wire-up-device-parent.patch
new file mode 100644
index 00000000000000..48bf9861184738
--- /dev/null
+++ b/target/linux/generic/backport-6.1/425-v6.3-mtd-ubi-block-wire-up-device-parent.patch
@@ -0,0 +1,49 @@
+From 05b8773ca33253ea562be145cf3145b05ef19f86 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Thu, 22 Dec 2022 19:33:31 +0000
+Subject: [PATCH] mtd: ubi: block: wire-up device parent
+
+ubiblock devices were previously only identifyable by their name, but
+not connected to their parent UBI volume device e.g. in sysfs.
+Properly parent ubiblock device as descendant of a UBI volume device
+to reflect device model hierachy.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: Richard Weinberger <richard@nod.at>
+---
+ drivers/mtd/ubi/block.c | 2 +-
+ drivers/mtd/ubi/kapi.c  | 1 +
+ include/linux/mtd/ubi.h | 1 +
+ 3 files changed, 3 insertions(+), 1 deletion(-)
+
+--- a/drivers/mtd/ubi/block.c
++++ b/drivers/mtd/ubi/block.c
+@@ -452,7 +452,7 @@ int ubiblock_create(struct ubi_volume_in
+ 	list_add_tail(&dev->list, &ubiblock_devices);
+ 
+ 	/* Must be the last step: anyone can call file ops from now on */
+-	ret = add_disk(dev->gd);
++	ret = device_add_disk(vi->dev, dev->gd, NULL);
+ 	if (ret)
+ 		goto out_destroy_wq;
+ 
+--- a/drivers/mtd/ubi/kapi.c
++++ b/drivers/mtd/ubi/kapi.c
+@@ -79,6 +79,7 @@ void ubi_do_get_volume_info(struct ubi_d
+ 	vi->name_len = vol->name_len;
+ 	vi->name = vol->name;
+ 	vi->cdev = vol->cdev.dev;
++	vi->dev = &vol->dev;
+ }
+ 
+ /**
+--- a/include/linux/mtd/ubi.h
++++ b/include/linux/mtd/ubi.h
+@@ -110,6 +110,7 @@ struct ubi_volume_info {
+ 	int name_len;
+ 	const char *name;
+ 	dev_t cdev;
++	struct device *dev;
+ };
+ 
+ /**
diff --git a/target/linux/generic/backport-6.1/424-v6.4-0004-mtd-core-prepare-mtd_otp_nvmem_add-to-handle-EPROBE_.patch b/target/linux/generic/backport-6.1/426-v6.4-0004-mtd-core-prepare-mtd_otp_nvmem_add-to-handle-EPROBE_.patch
similarity index 100%
rename from target/linux/generic/backport-6.1/424-v6.4-0004-mtd-core-prepare-mtd_otp_nvmem_add-to-handle-EPROBE_.patch
rename to target/linux/generic/backport-6.1/426-v6.4-0004-mtd-core-prepare-mtd_otp_nvmem_add-to-handle-EPROBE_.patch
diff --git a/target/linux/generic/backport-6.1/700-v6.2-net-phylink-add-phylink_get_link_timer_ns-helper.patch b/target/linux/generic/backport-6.1/700-v6.2-net-phylink-add-phylink_get_link_timer_ns-helper.patch
deleted file mode 100644
index 81c14a0557b2aa..00000000000000
--- a/target/linux/generic/backport-6.1/700-v6.2-net-phylink-add-phylink_get_link_timer_ns-helper.patch
+++ /dev/null
@@ -1,48 +0,0 @@
-From 9c5a170677c3c8facc83e931a57f4c99c0511ae0 Mon Sep 17 00:00:00 2001
-From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
-Date: Thu, 27 Oct 2022 14:10:37 +0100
-Subject: [PATCH] net: phylink: add phylink_get_link_timer_ns() helper
-
-Add a helper to convert the PHY interface mode to the required link
-timer setting as stated by the appropriate standard. Inappropriate
-interface modes return an error.
-
-Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
-Signed-off-by: Jakub Kicinski <kuba@kernel.org>
----
- include/linux/phylink.h | 24 ++++++++++++++++++++++++
- 1 file changed, 24 insertions(+)
-
---- a/include/linux/phylink.h
-+++ b/include/linux/phylink.h
-@@ -614,6 +614,30 @@ int phylink_speed_up(struct phylink *pl)
- 
- void phylink_set_port_modes(unsigned long *bits);
- 
-+/**
-+ * phylink_get_link_timer_ns - return the PCS link timer value
-+ * @interface: link &typedef phy_interface_t mode
-+ *
-+ * Return the PCS link timer setting in nanoseconds for the PHY @interface
-+ * mode, or -EINVAL if not appropriate.
-+ */
-+static inline int phylink_get_link_timer_ns(phy_interface_t interface)
-+{
-+	switch (interface) {
-+	case PHY_INTERFACE_MODE_SGMII:
-+	case PHY_INTERFACE_MODE_QSGMII:
-+	case PHY_INTERFACE_MODE_USXGMII:
-+		return 1600000;
-+
-+	case PHY_INTERFACE_MODE_1000BASEX:
-+	case PHY_INTERFACE_MODE_2500BASEX:
-+		return 10000000;
-+
-+	default:
-+		return -EINVAL;
-+	}
-+}
-+
- void phylink_mii_c22_pcs_decode_state(struct phylink_link_state *state,
- 				      u16 bmsr, u16 lpa);
- void phylink_mii_c22_pcs_get_state(struct mdio_device *pcs,
diff --git a/target/linux/generic/backport-6.1/707-v6.8-01-net-phy-at803x-fix-passing-the-wrong-reference-for-c.patch b/target/linux/generic/backport-6.1/707-v6.8-01-net-phy-at803x-fix-passing-the-wrong-reference-for-c.patch
deleted file mode 100644
index b206b180526d63..00000000000000
--- a/target/linux/generic/backport-6.1/707-v6.8-01-net-phy-at803x-fix-passing-the-wrong-reference-for-c.patch
+++ /dev/null
@@ -1,45 +0,0 @@
-From f8fdbf3389f44c7026f16e36cb1f2ff017f7f5b2 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Fri, 8 Dec 2023 15:51:48 +0100
-Subject: [PATCH 01/13] net: phy: at803x: fix passing the wrong reference for
- config_intr
-
-Fix passing the wrong reference for config_initr on passing the function
-pointer, drop the wrong & from at803x_config_intr in the PHY struct.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Reviewed-by: Andrew Lunn <andrew@lunn.ch>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/phy/at803x.c | 6 +++---
- 1 file changed, 3 insertions(+), 3 deletions(-)
-
---- a/drivers/net/phy/at803x.c
-+++ b/drivers/net/phy/at803x.c
-@@ -2104,7 +2104,7 @@ static struct phy_driver at803x_driver[]
- 	.write_page		= at803x_write_page,
- 	.get_features		= at803x_get_features,
- 	.read_status		= at803x_read_status,
--	.config_intr		= &at803x_config_intr,
-+	.config_intr		= at803x_config_intr,
- 	.handle_interrupt	= at803x_handle_interrupt,
- 	.get_tunable		= at803x_get_tunable,
- 	.set_tunable		= at803x_set_tunable,
-@@ -2134,7 +2134,7 @@ static struct phy_driver at803x_driver[]
- 	.resume			= at803x_resume,
- 	.flags			= PHY_POLL_CABLE_TEST,
- 	/* PHY_BASIC_FEATURES */
--	.config_intr		= &at803x_config_intr,
-+	.config_intr		= at803x_config_intr,
- 	.handle_interrupt	= at803x_handle_interrupt,
- 	.cable_test_start	= at803x_cable_test_start,
- 	.cable_test_get_status	= at803x_cable_test_get_status,
-@@ -2150,7 +2150,7 @@ static struct phy_driver at803x_driver[]
- 	.resume			= at803x_resume,
- 	.flags			= PHY_POLL_CABLE_TEST,
- 	/* PHY_BASIC_FEATURES */
--	.config_intr		= &at803x_config_intr,
-+	.config_intr		= at803x_config_intr,
- 	.handle_interrupt	= at803x_handle_interrupt,
- 	.cable_test_start	= at803x_cable_test_start,
- 	.cable_test_get_status	= at803x_cable_test_get_status,
diff --git a/target/linux/generic/backport-6.1/713-v6.9-01-net-phy-move-at803x-PHY-driver-to-dedicated-director.patch b/target/linux/generic/backport-6.1/713-v6.9-01-net-phy-move-at803x-PHY-driver-to-dedicated-director.patch
new file mode 100644
index 00000000000000..8c9babea7b1203
--- /dev/null
+++ b/target/linux/generic/backport-6.1/713-v6.9-01-net-phy-move-at803x-PHY-driver-to-dedicated-director.patch
@@ -0,0 +1,5598 @@
+From 9e56ff53b4115875667760445b028357848b4748 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Mon, 29 Jan 2024 15:15:19 +0100
+Subject: [PATCH 1/5] net: phy: move at803x PHY driver to dedicated directory
+
+In preparation for addition of other Qcom PHY and to tidy things up,
+move the at803x PHY driver to dedicated directory.
+
+The same order in the Kconfig selection is saved.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://lore.kernel.org/r/20240129141600.2592-2-ansuelsmth@gmail.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/Kconfig             | 7 +------
+ drivers/net/phy/Makefile            | 2 +-
+ drivers/net/phy/qcom/Kconfig        | 7 +++++++
+ drivers/net/phy/qcom/Makefile       | 2 ++
+ drivers/net/phy/{ => qcom}/at803x.c | 0
+ 5 files changed, 11 insertions(+), 7 deletions(-)
+ create mode 100644 drivers/net/phy/qcom/Kconfig
+ create mode 100644 drivers/net/phy/qcom/Makefile
+ rename drivers/net/phy/{ => qcom}/at803x.c (100%)
+
+--- a/drivers/net/phy/Kconfig
++++ b/drivers/net/phy/Kconfig
+@@ -277,12 +277,7 @@ config NXP_TJA11XX_PHY
+ 	help
+ 	  Currently supports the NXP TJA1100 and TJA1101 PHY.
+ 
+-config AT803X_PHY
+-	tristate "Qualcomm Atheros AR803X PHYs and QCA833x PHYs"
+-	depends on REGULATOR
+-	help
+-	  Currently supports the AR8030, AR8031, AR8033, AR8035 and internal
+-	  QCA8337(Internal qca8k PHY) model
++source "drivers/net/phy/qcom/Kconfig"
+ 
+ config QSEMI_PHY
+ 	tristate "Quality Semiconductor PHYs"
+--- a/drivers/net/phy/Makefile
++++ b/drivers/net/phy/Makefile
+@@ -34,7 +34,6 @@ obj-$(CONFIG_ADIN_PHY)		+= adin.o
+ obj-$(CONFIG_ADIN1100_PHY)	+= adin1100.o
+ obj-$(CONFIG_AMD_PHY)		+= amd.o
+ obj-$(CONFIG_AQUANTIA_PHY)	+= aquantia/
+-obj-$(CONFIG_AT803X_PHY)	+= at803x.o
+ obj-$(CONFIG_AX88796B_PHY)	+= ax88796b.o
+ obj-$(CONFIG_BCM54140_PHY)	+= bcm54140.o
+ obj-$(CONFIG_BCM63XX_PHY)	+= bcm63xx.o
+@@ -75,6 +74,7 @@ obj-$(CONFIG_MOTORCOMM_PHY)	+= motorcomm
+ obj-$(CONFIG_NATIONAL_PHY)	+= national.o
+ obj-$(CONFIG_NXP_C45_TJA11XX_PHY)	+= nxp-c45-tja11xx.o
+ obj-$(CONFIG_NXP_TJA11XX_PHY)	+= nxp-tja11xx.o
++obj-y				+= qcom/
+ obj-$(CONFIG_QSEMI_PHY)		+= qsemi.o
+ obj-$(CONFIG_REALTEK_PHY)	+= realtek.o
+ obj-$(CONFIG_RENESAS_PHY)	+= uPD60620.o
+--- /dev/null
++++ b/drivers/net/phy/qcom/Kconfig
+@@ -0,0 +1,7 @@
++# SPDX-License-Identifier: GPL-2.0-only
++config AT803X_PHY
++	tristate "Qualcomm Atheros AR803X PHYs and QCA833x PHYs"
++	depends on REGULATOR
++	help
++	  Currently supports the AR8030, AR8031, AR8033, AR8035 and internal
++	  QCA8337(Internal qca8k PHY) model
+--- /dev/null
++++ b/drivers/net/phy/qcom/Makefile
+@@ -0,0 +1,2 @@
++# SPDX-License-Identifier: GPL-2.0
++obj-$(CONFIG_AT803X_PHY)	+= at803x.o
+--- a/drivers/net/phy/at803x.c
++++ /dev/null
+@@ -1,2759 +0,0 @@
+-// SPDX-License-Identifier: GPL-2.0+
+-/*
+- * drivers/net/phy/at803x.c
+- *
+- * Driver for Qualcomm Atheros AR803x PHY
+- *
+- * Author: Matus Ujhelyi <ujhelyi.m@gmail.com>
+- */
+-
+-#include <linux/phy.h>
+-#include <linux/module.h>
+-#include <linux/string.h>
+-#include <linux/netdevice.h>
+-#include <linux/etherdevice.h>
+-#include <linux/ethtool_netlink.h>
+-#include <linux/bitfield.h>
+-#include <linux/regulator/of_regulator.h>
+-#include <linux/regulator/driver.h>
+-#include <linux/regulator/consumer.h>
+-#include <linux/of.h>
+-#include <linux/phylink.h>
+-#include <linux/sfp.h>
+-#include <dt-bindings/net/qca-ar803x.h>
+-
+-#define AT803X_SPECIFIC_FUNCTION_CONTROL	0x10
+-#define AT803X_SFC_ASSERT_CRS			BIT(11)
+-#define AT803X_SFC_FORCE_LINK			BIT(10)
+-#define AT803X_SFC_MDI_CROSSOVER_MODE_M		GENMASK(6, 5)
+-#define AT803X_SFC_AUTOMATIC_CROSSOVER		0x3
+-#define AT803X_SFC_MANUAL_MDIX			0x1
+-#define AT803X_SFC_MANUAL_MDI			0x0
+-#define AT803X_SFC_SQE_TEST			BIT(2)
+-#define AT803X_SFC_POLARITY_REVERSAL		BIT(1)
+-#define AT803X_SFC_DISABLE_JABBER		BIT(0)
+-
+-#define AT803X_SPECIFIC_STATUS			0x11
+-#define AT803X_SS_SPEED_MASK			GENMASK(15, 14)
+-#define AT803X_SS_SPEED_1000			2
+-#define AT803X_SS_SPEED_100			1
+-#define AT803X_SS_SPEED_10			0
+-#define AT803X_SS_DUPLEX			BIT(13)
+-#define AT803X_SS_SPEED_DUPLEX_RESOLVED		BIT(11)
+-#define AT803X_SS_MDIX				BIT(6)
+-
+-#define QCA808X_SS_SPEED_MASK			GENMASK(9, 7)
+-#define QCA808X_SS_SPEED_2500			4
+-
+-#define AT803X_INTR_ENABLE			0x12
+-#define AT803X_INTR_ENABLE_AUTONEG_ERR		BIT(15)
+-#define AT803X_INTR_ENABLE_SPEED_CHANGED	BIT(14)
+-#define AT803X_INTR_ENABLE_DUPLEX_CHANGED	BIT(13)
+-#define AT803X_INTR_ENABLE_PAGE_RECEIVED	BIT(12)
+-#define AT803X_INTR_ENABLE_LINK_FAIL		BIT(11)
+-#define AT803X_INTR_ENABLE_LINK_SUCCESS		BIT(10)
+-#define AT803X_INTR_ENABLE_LINK_FAIL_BX		BIT(8)
+-#define AT803X_INTR_ENABLE_LINK_SUCCESS_BX	BIT(7)
+-#define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE	BIT(5)
+-#define AT803X_INTR_ENABLE_POLARITY_CHANGED	BIT(1)
+-#define AT803X_INTR_ENABLE_WOL			BIT(0)
+-
+-#define AT803X_INTR_STATUS			0x13
+-
+-#define AT803X_SMART_SPEED			0x14
+-#define AT803X_SMART_SPEED_ENABLE		BIT(5)
+-#define AT803X_SMART_SPEED_RETRY_LIMIT_MASK	GENMASK(4, 2)
+-#define AT803X_SMART_SPEED_BYPASS_TIMER		BIT(1)
+-#define AT803X_CDT				0x16
+-#define AT803X_CDT_MDI_PAIR_MASK		GENMASK(9, 8)
+-#define AT803X_CDT_ENABLE_TEST			BIT(0)
+-#define AT803X_CDT_STATUS			0x1c
+-#define AT803X_CDT_STATUS_STAT_NORMAL		0
+-#define AT803X_CDT_STATUS_STAT_SHORT		1
+-#define AT803X_CDT_STATUS_STAT_OPEN		2
+-#define AT803X_CDT_STATUS_STAT_FAIL		3
+-#define AT803X_CDT_STATUS_STAT_MASK		GENMASK(9, 8)
+-#define AT803X_CDT_STATUS_DELTA_TIME_MASK	GENMASK(7, 0)
+-#define AT803X_LED_CONTROL			0x18
+-
+-#define AT803X_PHY_MMD3_WOL_CTRL		0x8012
+-#define AT803X_WOL_EN				BIT(5)
+-#define AT803X_LOC_MAC_ADDR_0_15_OFFSET		0x804C
+-#define AT803X_LOC_MAC_ADDR_16_31_OFFSET	0x804B
+-#define AT803X_LOC_MAC_ADDR_32_47_OFFSET	0x804A
+-#define AT803X_REG_CHIP_CONFIG			0x1f
+-#define AT803X_BT_BX_REG_SEL			0x8000
+-
+-#define AT803X_DEBUG_ADDR			0x1D
+-#define AT803X_DEBUG_DATA			0x1E
+-
+-#define AT803X_MODE_CFG_MASK			0x0F
+-#define AT803X_MODE_CFG_BASET_RGMII		0x00
+-#define AT803X_MODE_CFG_BASET_SGMII		0x01
+-#define AT803X_MODE_CFG_BX1000_RGMII_50OHM	0x02
+-#define AT803X_MODE_CFG_BX1000_RGMII_75OHM	0x03
+-#define AT803X_MODE_CFG_BX1000_CONV_50OHM	0x04
+-#define AT803X_MODE_CFG_BX1000_CONV_75OHM	0x05
+-#define AT803X_MODE_CFG_FX100_RGMII_50OHM	0x06
+-#define AT803X_MODE_CFG_FX100_CONV_50OHM	0x07
+-#define AT803X_MODE_CFG_RGMII_AUTO_MDET		0x0B
+-#define AT803X_MODE_CFG_FX100_RGMII_75OHM	0x0E
+-#define AT803X_MODE_CFG_FX100_CONV_75OHM	0x0F
+-
+-#define AT803X_PSSR				0x11	/*PHY-Specific Status Register*/
+-#define AT803X_PSSR_MR_AN_COMPLETE		0x0200
+-
+-#define AT803X_DEBUG_ANALOG_TEST_CTRL		0x00
+-#define QCA8327_DEBUG_MANU_CTRL_EN		BIT(2)
+-#define QCA8337_DEBUG_MANU_CTRL_EN		GENMASK(3, 2)
+-#define AT803X_DEBUG_RX_CLK_DLY_EN		BIT(15)
+-
+-#define AT803X_DEBUG_SYSTEM_CTRL_MODE		0x05
+-#define AT803X_DEBUG_TX_CLK_DLY_EN		BIT(8)
+-
+-#define AT803X_DEBUG_REG_HIB_CTRL		0x0b
+-#define   AT803X_DEBUG_HIB_CTRL_SEL_RST_80U	BIT(10)
+-#define   AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE	BIT(13)
+-#define   AT803X_DEBUG_HIB_CTRL_PS_HIB_EN	BIT(15)
+-
+-#define AT803X_DEBUG_REG_3C			0x3C
+-
+-#define AT803X_DEBUG_REG_GREEN			0x3D
+-#define   AT803X_DEBUG_GATE_CLK_IN1000		BIT(6)
+-
+-#define AT803X_DEBUG_REG_1F			0x1F
+-#define AT803X_DEBUG_PLL_ON			BIT(2)
+-#define AT803X_DEBUG_RGMII_1V8			BIT(3)
+-
+-#define MDIO_AZ_DEBUG				0x800D
+-
+-/* AT803x supports either the XTAL input pad, an internal PLL or the
+- * DSP as clock reference for the clock output pad. The XTAL reference
+- * is only used for 25 MHz output, all other frequencies need the PLL.
+- * The DSP as a clock reference is used in synchronous ethernet
+- * applications.
+- *
+- * By default the PLL is only enabled if there is a link. Otherwise
+- * the PHY will go into low power state and disabled the PLL. You can
+- * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always
+- * enabled.
+- */
+-#define AT803X_MMD7_CLK25M			0x8016
+-#define AT803X_CLK_OUT_MASK			GENMASK(4, 2)
+-#define AT803X_CLK_OUT_25MHZ_XTAL		0
+-#define AT803X_CLK_OUT_25MHZ_DSP		1
+-#define AT803X_CLK_OUT_50MHZ_PLL		2
+-#define AT803X_CLK_OUT_50MHZ_DSP		3
+-#define AT803X_CLK_OUT_62_5MHZ_PLL		4
+-#define AT803X_CLK_OUT_62_5MHZ_DSP		5
+-#define AT803X_CLK_OUT_125MHZ_PLL		6
+-#define AT803X_CLK_OUT_125MHZ_DSP		7
+-
+-/* The AR8035 has another mask which is compatible with the AR8031/AR8033 mask
+- * but doesn't support choosing between XTAL/PLL and DSP.
+- */
+-#define AT8035_CLK_OUT_MASK			GENMASK(4, 3)
+-
+-#define AT803X_CLK_OUT_STRENGTH_MASK		GENMASK(8, 7)
+-#define AT803X_CLK_OUT_STRENGTH_FULL		0
+-#define AT803X_CLK_OUT_STRENGTH_HALF		1
+-#define AT803X_CLK_OUT_STRENGTH_QUARTER		2
+-
+-#define AT803X_DEFAULT_DOWNSHIFT		5
+-#define AT803X_MIN_DOWNSHIFT			2
+-#define AT803X_MAX_DOWNSHIFT			9
+-
+-#define AT803X_MMD3_SMARTEEE_CTL1		0x805b
+-#define AT803X_MMD3_SMARTEEE_CTL2		0x805c
+-#define AT803X_MMD3_SMARTEEE_CTL3		0x805d
+-#define AT803X_MMD3_SMARTEEE_CTL3_LPI_EN	BIT(8)
+-
+-#define ATH9331_PHY_ID				0x004dd041
+-#define ATH8030_PHY_ID				0x004dd076
+-#define ATH8031_PHY_ID				0x004dd074
+-#define ATH8032_PHY_ID				0x004dd023
+-#define ATH8035_PHY_ID				0x004dd072
+-#define AT8030_PHY_ID_MASK			0xffffffef
+-
+-#define QCA8081_PHY_ID				0x004dd101
+-
+-#define QCA8327_A_PHY_ID			0x004dd033
+-#define QCA8327_B_PHY_ID			0x004dd034
+-#define QCA8337_PHY_ID				0x004dd036
+-#define QCA9561_PHY_ID				0x004dd042
+-#define QCA8K_PHY_ID_MASK			0xffffffff
+-
+-#define QCA8K_DEVFLAGS_REVISION_MASK		GENMASK(2, 0)
+-
+-#define AT803X_PAGE_FIBER			0
+-#define AT803X_PAGE_COPPER			1
+-
+-/* don't turn off internal PLL */
+-#define AT803X_KEEP_PLL_ENABLED			BIT(0)
+-#define AT803X_DISABLE_SMARTEEE			BIT(1)
+-
+-/* disable hibernation mode */
+-#define AT803X_DISABLE_HIBERNATION_MODE		BIT(2)
+-
+-/* ADC threshold */
+-#define QCA808X_PHY_DEBUG_ADC_THRESHOLD		0x2c80
+-#define QCA808X_ADC_THRESHOLD_MASK		GENMASK(7, 0)
+-#define QCA808X_ADC_THRESHOLD_80MV		0
+-#define QCA808X_ADC_THRESHOLD_100MV		0xf0
+-#define QCA808X_ADC_THRESHOLD_200MV		0x0f
+-#define QCA808X_ADC_THRESHOLD_300MV		0xff
+-
+-/* CLD control */
+-#define QCA808X_PHY_MMD3_ADDR_CLD_CTRL7		0x8007
+-#define QCA808X_8023AZ_AFE_CTRL_MASK		GENMASK(8, 4)
+-#define QCA808X_8023AZ_AFE_EN			0x90
+-
+-/* AZ control */
+-#define QCA808X_PHY_MMD3_AZ_TRAINING_CTRL	0x8008
+-#define QCA808X_MMD3_AZ_TRAINING_VAL		0x1c32
+-
+-#define QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB	0x8014
+-#define QCA808X_MSE_THRESHOLD_20DB_VALUE	0x529
+-
+-#define QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB	0x800E
+-#define QCA808X_MSE_THRESHOLD_17DB_VALUE	0x341
+-
+-#define QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB	0x801E
+-#define QCA808X_MSE_THRESHOLD_27DB_VALUE	0x419
+-
+-#define QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB	0x8020
+-#define QCA808X_MSE_THRESHOLD_28DB_VALUE	0x341
+-
+-#define QCA808X_PHY_MMD7_TOP_OPTION1		0x901c
+-#define QCA808X_TOP_OPTION1_DATA		0x0
+-
+-#define QCA808X_PHY_MMD3_DEBUG_1		0xa100
+-#define QCA808X_MMD3_DEBUG_1_VALUE		0x9203
+-#define QCA808X_PHY_MMD3_DEBUG_2		0xa101
+-#define QCA808X_MMD3_DEBUG_2_VALUE		0x48ad
+-#define QCA808X_PHY_MMD3_DEBUG_3		0xa103
+-#define QCA808X_MMD3_DEBUG_3_VALUE		0x1698
+-#define QCA808X_PHY_MMD3_DEBUG_4		0xa105
+-#define QCA808X_MMD3_DEBUG_4_VALUE		0x8001
+-#define QCA808X_PHY_MMD3_DEBUG_5		0xa106
+-#define QCA808X_MMD3_DEBUG_5_VALUE		0x1111
+-#define QCA808X_PHY_MMD3_DEBUG_6		0xa011
+-#define QCA808X_MMD3_DEBUG_6_VALUE		0x5f85
+-
+-/* master/slave seed config */
+-#define QCA808X_PHY_DEBUG_LOCAL_SEED		9
+-#define QCA808X_MASTER_SLAVE_SEED_ENABLE	BIT(1)
+-#define QCA808X_MASTER_SLAVE_SEED_CFG		GENMASK(12, 2)
+-#define QCA808X_MASTER_SLAVE_SEED_RANGE		0x32
+-
+-/* Hibernation yields lower power consumpiton in contrast with normal operation mode.
+- * when the copper cable is unplugged, the PHY enters into hibernation mode in about 10s.
+- */
+-#define QCA808X_DBG_AN_TEST			0xb
+-#define QCA808X_HIBERNATION_EN			BIT(15)
+-
+-#define QCA808X_CDT_ENABLE_TEST			BIT(15)
+-#define QCA808X_CDT_INTER_CHECK_DIS		BIT(13)
+-#define QCA808X_CDT_STATUS			BIT(11)
+-#define QCA808X_CDT_LENGTH_UNIT			BIT(10)
+-
+-#define QCA808X_MMD3_CDT_STATUS			0x8064
+-#define QCA808X_MMD3_CDT_DIAG_PAIR_A		0x8065
+-#define QCA808X_MMD3_CDT_DIAG_PAIR_B		0x8066
+-#define QCA808X_MMD3_CDT_DIAG_PAIR_C		0x8067
+-#define QCA808X_MMD3_CDT_DIAG_PAIR_D		0x8068
+-#define QCA808X_CDT_DIAG_LENGTH_SAME_SHORT	GENMASK(15, 8)
+-#define QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT	GENMASK(7, 0)
+-
+-#define QCA808X_CDT_CODE_PAIR_A			GENMASK(15, 12)
+-#define QCA808X_CDT_CODE_PAIR_B			GENMASK(11, 8)
+-#define QCA808X_CDT_CODE_PAIR_C			GENMASK(7, 4)
+-#define QCA808X_CDT_CODE_PAIR_D			GENMASK(3, 0)
+-
+-#define QCA808X_CDT_STATUS_STAT_TYPE		GENMASK(1, 0)
+-#define QCA808X_CDT_STATUS_STAT_FAIL		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 0)
+-#define QCA808X_CDT_STATUS_STAT_NORMAL		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 1)
+-#define QCA808X_CDT_STATUS_STAT_SAME_OPEN	FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 2)
+-#define QCA808X_CDT_STATUS_STAT_SAME_SHORT	FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 3)
+-
+-#define QCA808X_CDT_STATUS_STAT_MDI		GENMASK(3, 2)
+-#define QCA808X_CDT_STATUS_STAT_MDI1		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 1)
+-#define QCA808X_CDT_STATUS_STAT_MDI2		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 2)
+-#define QCA808X_CDT_STATUS_STAT_MDI3		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 3)
+-
+-/* NORMAL are MDI with type set to 0 */
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL	QCA808X_CDT_STATUS_STAT_MDI1
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN		(QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
+-									 QCA808X_CDT_STATUS_STAT_MDI1)
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT	(QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
+-									 QCA808X_CDT_STATUS_STAT_MDI1)
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL	QCA808X_CDT_STATUS_STAT_MDI2
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN		(QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
+-									 QCA808X_CDT_STATUS_STAT_MDI2)
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT	(QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
+-									 QCA808X_CDT_STATUS_STAT_MDI2)
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL	QCA808X_CDT_STATUS_STAT_MDI3
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN		(QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
+-									 QCA808X_CDT_STATUS_STAT_MDI3)
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT	(QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
+-									 QCA808X_CDT_STATUS_STAT_MDI3)
+-
+-/* Added for reference of existence but should be handled by wait_for_completion already */
+-#define QCA808X_CDT_STATUS_STAT_BUSY		(BIT(1) | BIT(3))
+-
+-#define QCA808X_MMD7_LED_GLOBAL			0x8073
+-#define QCA808X_LED_BLINK_1			GENMASK(11, 6)
+-#define QCA808X_LED_BLINK_2			GENMASK(5, 0)
+-/* Values are the same for both BLINK_1 and BLINK_2 */
+-#define QCA808X_LED_BLINK_FREQ_MASK		GENMASK(5, 3)
+-#define QCA808X_LED_BLINK_FREQ_2HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x0)
+-#define QCA808X_LED_BLINK_FREQ_4HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x1)
+-#define QCA808X_LED_BLINK_FREQ_8HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x2)
+-#define QCA808X_LED_BLINK_FREQ_16HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x3)
+-#define QCA808X_LED_BLINK_FREQ_32HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x4)
+-#define QCA808X_LED_BLINK_FREQ_64HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x5)
+-#define QCA808X_LED_BLINK_FREQ_128HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x6)
+-#define QCA808X_LED_BLINK_FREQ_256HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x7)
+-#define QCA808X_LED_BLINK_DUTY_MASK		GENMASK(2, 0)
+-#define QCA808X_LED_BLINK_DUTY_50_50		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x0)
+-#define QCA808X_LED_BLINK_DUTY_75_25		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x1)
+-#define QCA808X_LED_BLINK_DUTY_25_75		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x2)
+-#define QCA808X_LED_BLINK_DUTY_33_67		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x3)
+-#define QCA808X_LED_BLINK_DUTY_67_33		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x4)
+-#define QCA808X_LED_BLINK_DUTY_17_83		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x5)
+-#define QCA808X_LED_BLINK_DUTY_83_17		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x6)
+-#define QCA808X_LED_BLINK_DUTY_8_92		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x7)
+-
+-#define QCA808X_MMD7_LED2_CTRL			0x8074
+-#define QCA808X_MMD7_LED2_FORCE_CTRL		0x8075
+-#define QCA808X_MMD7_LED1_CTRL			0x8076
+-#define QCA808X_MMD7_LED1_FORCE_CTRL		0x8077
+-#define QCA808X_MMD7_LED0_CTRL			0x8078
+-#define QCA808X_MMD7_LED_CTRL(x)		(0x8078 - ((x) * 2))
+-
+-/* LED hw control pattern is the same for every LED */
+-#define QCA808X_LED_PATTERN_MASK		GENMASK(15, 0)
+-#define QCA808X_LED_SPEED2500_ON		BIT(15)
+-#define QCA808X_LED_SPEED2500_BLINK		BIT(14)
+-/* Follow blink trigger even if duplex or speed condition doesn't match */
+-#define QCA808X_LED_BLINK_CHECK_BYPASS		BIT(13)
+-#define QCA808X_LED_FULL_DUPLEX_ON		BIT(12)
+-#define QCA808X_LED_HALF_DUPLEX_ON		BIT(11)
+-#define QCA808X_LED_TX_BLINK			BIT(10)
+-#define QCA808X_LED_RX_BLINK			BIT(9)
+-#define QCA808X_LED_TX_ON_10MS			BIT(8)
+-#define QCA808X_LED_RX_ON_10MS			BIT(7)
+-#define QCA808X_LED_SPEED1000_ON		BIT(6)
+-#define QCA808X_LED_SPEED100_ON			BIT(5)
+-#define QCA808X_LED_SPEED10_ON			BIT(4)
+-#define QCA808X_LED_COLLISION_BLINK		BIT(3)
+-#define QCA808X_LED_SPEED1000_BLINK		BIT(2)
+-#define QCA808X_LED_SPEED100_BLINK		BIT(1)
+-#define QCA808X_LED_SPEED10_BLINK		BIT(0)
+-
+-#define QCA808X_MMD7_LED0_FORCE_CTRL		0x8079
+-#define QCA808X_MMD7_LED_FORCE_CTRL(x)		(0x8079 - ((x) * 2))
+-
+-/* LED force ctrl is the same for every LED
+- * No documentation exist for this, not even internal one
+- * with NDA as QCOM gives only info about configuring
+- * hw control pattern rules and doesn't indicate any way
+- * to force the LED to specific mode.
+- * These define comes from reverse and testing and maybe
+- * lack of some info or some info are not entirely correct.
+- * For the basic LED control and hw control these finding
+- * are enough to support LED control in all the required APIs.
+- *
+- * On doing some comparison with implementation with qca807x,
+- * it was found that it's 1:1 equal to it and confirms all the
+- * reverse done. It was also found further specification with the
+- * force mode and the blink modes.
+- */
+-#define QCA808X_LED_FORCE_EN			BIT(15)
+-#define QCA808X_LED_FORCE_MODE_MASK		GENMASK(14, 13)
+-#define QCA808X_LED_FORCE_BLINK_1		FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x3)
+-#define QCA808X_LED_FORCE_BLINK_2		FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x2)
+-#define QCA808X_LED_FORCE_ON			FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x1)
+-#define QCA808X_LED_FORCE_OFF			FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x0)
+-
+-#define QCA808X_MMD7_LED_POLARITY_CTRL		0x901a
+-/* QSDK sets by default 0x46 to this reg that sets BIT 6 for
+- * LED to active high. It's not clear what BIT 3 and BIT 4 does.
+- */
+-#define QCA808X_LED_ACTIVE_HIGH			BIT(6)
+-
+-/* QCA808X 1G chip type */
+-#define QCA808X_PHY_MMD7_CHIP_TYPE		0x901d
+-#define QCA808X_PHY_CHIP_TYPE_1G		BIT(0)
+-
+-#define QCA8081_PHY_SERDES_MMD1_FIFO_CTRL	0x9072
+-#define QCA8081_PHY_FIFO_RSTN			BIT(11)
+-
+-MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver");
+-MODULE_AUTHOR("Matus Ujhelyi");
+-MODULE_LICENSE("GPL");
+-
+-enum stat_access_type {
+-	PHY,
+-	MMD
+-};
+-
+-struct at803x_hw_stat {
+-	const char *string;
+-	u8 reg;
+-	u32 mask;
+-	enum stat_access_type access_type;
+-};
+-
+-static struct at803x_hw_stat qca83xx_hw_stats[] = {
+-	{ "phy_idle_errors", 0xa, GENMASK(7, 0), PHY},
+-	{ "phy_receive_errors", 0x15, GENMASK(15, 0), PHY},
+-	{ "eee_wake_errors", 0x16, GENMASK(15, 0), MMD},
+-};
+-
+-struct at803x_ss_mask {
+-	u16 speed_mask;
+-	u8 speed_shift;
+-};
+-
+-struct at803x_priv {
+-	int flags;
+-	u16 clk_25m_reg;
+-	u16 clk_25m_mask;
+-	u8 smarteee_lpi_tw_1g;
+-	u8 smarteee_lpi_tw_100m;
+-	bool is_fiber;
+-	bool is_1000basex;
+-	struct regulator_dev *vddio_rdev;
+-	struct regulator_dev *vddh_rdev;
+-	u64 stats[ARRAY_SIZE(qca83xx_hw_stats)];
+-	int led_polarity_mode;
+-};
+-
+-struct at803x_context {
+-	u16 bmcr;
+-	u16 advertise;
+-	u16 control1000;
+-	u16 int_enable;
+-	u16 smart_speed;
+-	u16 led_control;
+-};
+-
+-static int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data)
+-{
+-	int ret;
+-
+-	ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
+-	if (ret < 0)
+-		return ret;
+-
+-	return phy_write(phydev, AT803X_DEBUG_DATA, data);
+-}
+-
+-static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg)
+-{
+-	int ret;
+-
+-	ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
+-	if (ret < 0)
+-		return ret;
+-
+-	return phy_read(phydev, AT803X_DEBUG_DATA);
+-}
+-
+-static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
+-				 u16 clear, u16 set)
+-{
+-	u16 val;
+-	int ret;
+-
+-	ret = at803x_debug_reg_read(phydev, reg);
+-	if (ret < 0)
+-		return ret;
+-
+-	val = ret & 0xffff;
+-	val &= ~clear;
+-	val |= set;
+-
+-	return phy_write(phydev, AT803X_DEBUG_DATA, val);
+-}
+-
+-static int at803x_write_page(struct phy_device *phydev, int page)
+-{
+-	int mask;
+-	int set;
+-
+-	if (page == AT803X_PAGE_COPPER) {
+-		set = AT803X_BT_BX_REG_SEL;
+-		mask = 0;
+-	} else {
+-		set = 0;
+-		mask = AT803X_BT_BX_REG_SEL;
+-	}
+-
+-	return __phy_modify(phydev, AT803X_REG_CHIP_CONFIG, mask, set);
+-}
+-
+-static int at803x_read_page(struct phy_device *phydev)
+-{
+-	int ccr = __phy_read(phydev, AT803X_REG_CHIP_CONFIG);
+-
+-	if (ccr < 0)
+-		return ccr;
+-
+-	if (ccr & AT803X_BT_BX_REG_SEL)
+-		return AT803X_PAGE_COPPER;
+-
+-	return AT803X_PAGE_FIBER;
+-}
+-
+-static int at803x_enable_rx_delay(struct phy_device *phydev)
+-{
+-	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0,
+-				     AT803X_DEBUG_RX_CLK_DLY_EN);
+-}
+-
+-static int at803x_enable_tx_delay(struct phy_device *phydev)
+-{
+-	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0,
+-				     AT803X_DEBUG_TX_CLK_DLY_EN);
+-}
+-
+-static int at803x_disable_rx_delay(struct phy_device *phydev)
+-{
+-	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
+-				     AT803X_DEBUG_RX_CLK_DLY_EN, 0);
+-}
+-
+-static int at803x_disable_tx_delay(struct phy_device *phydev)
+-{
+-	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE,
+-				     AT803X_DEBUG_TX_CLK_DLY_EN, 0);
+-}
+-
+-/* save relevant PHY registers to private copy */
+-static void at803x_context_save(struct phy_device *phydev,
+-				struct at803x_context *context)
+-{
+-	context->bmcr = phy_read(phydev, MII_BMCR);
+-	context->advertise = phy_read(phydev, MII_ADVERTISE);
+-	context->control1000 = phy_read(phydev, MII_CTRL1000);
+-	context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE);
+-	context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED);
+-	context->led_control = phy_read(phydev, AT803X_LED_CONTROL);
+-}
+-
+-/* restore relevant PHY registers from private copy */
+-static void at803x_context_restore(struct phy_device *phydev,
+-				   const struct at803x_context *context)
+-{
+-	phy_write(phydev, MII_BMCR, context->bmcr);
+-	phy_write(phydev, MII_ADVERTISE, context->advertise);
+-	phy_write(phydev, MII_CTRL1000, context->control1000);
+-	phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable);
+-	phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed);
+-	phy_write(phydev, AT803X_LED_CONTROL, context->led_control);
+-}
+-
+-static int at803x_set_wol(struct phy_device *phydev,
+-			  struct ethtool_wolinfo *wol)
+-{
+-	int ret, irq_enabled;
+-
+-	if (wol->wolopts & WAKE_MAGIC) {
+-		struct net_device *ndev = phydev->attached_dev;
+-		const u8 *mac;
+-		unsigned int i;
+-		static const unsigned int offsets[] = {
+-			AT803X_LOC_MAC_ADDR_32_47_OFFSET,
+-			AT803X_LOC_MAC_ADDR_16_31_OFFSET,
+-			AT803X_LOC_MAC_ADDR_0_15_OFFSET,
+-		};
+-
+-		if (!ndev)
+-			return -ENODEV;
+-
+-		mac = (const u8 *)ndev->dev_addr;
+-
+-		if (!is_valid_ether_addr(mac))
+-			return -EINVAL;
+-
+-		for (i = 0; i < 3; i++)
+-			phy_write_mmd(phydev, MDIO_MMD_PCS, offsets[i],
+-				      mac[(i * 2) + 1] | (mac[(i * 2)] << 8));
+-
+-		/* Enable WOL interrupt */
+-		ret = phy_modify(phydev, AT803X_INTR_ENABLE, 0, AT803X_INTR_ENABLE_WOL);
+-		if (ret)
+-			return ret;
+-	} else {
+-		/* Disable WOL interrupt */
+-		ret = phy_modify(phydev, AT803X_INTR_ENABLE, AT803X_INTR_ENABLE_WOL, 0);
+-		if (ret)
+-			return ret;
+-	}
+-
+-	/* Clear WOL status */
+-	ret = phy_read(phydev, AT803X_INTR_STATUS);
+-	if (ret < 0)
+-		return ret;
+-
+-	/* Check if there are other interrupts except for WOL triggered when PHY is
+-	 * in interrupt mode, only the interrupts enabled by AT803X_INTR_ENABLE can
+-	 * be passed up to the interrupt PIN.
+-	 */
+-	irq_enabled = phy_read(phydev, AT803X_INTR_ENABLE);
+-	if (irq_enabled < 0)
+-		return irq_enabled;
+-
+-	irq_enabled &= ~AT803X_INTR_ENABLE_WOL;
+-	if (ret & irq_enabled && !phy_polling_mode(phydev))
+-		phy_trigger_machine(phydev);
+-
+-	return 0;
+-}
+-
+-static void at803x_get_wol(struct phy_device *phydev,
+-			   struct ethtool_wolinfo *wol)
+-{
+-	int value;
+-
+-	wol->supported = WAKE_MAGIC;
+-	wol->wolopts = 0;
+-
+-	value = phy_read(phydev, AT803X_INTR_ENABLE);
+-	if (value < 0)
+-		return;
+-
+-	if (value & AT803X_INTR_ENABLE_WOL)
+-		wol->wolopts |= WAKE_MAGIC;
+-}
+-
+-static int qca83xx_get_sset_count(struct phy_device *phydev)
+-{
+-	return ARRAY_SIZE(qca83xx_hw_stats);
+-}
+-
+-static void qca83xx_get_strings(struct phy_device *phydev, u8 *data)
+-{
+-	int i;
+-
+-	for (i = 0; i < ARRAY_SIZE(qca83xx_hw_stats); i++) {
+-		strscpy(data + i * ETH_GSTRING_LEN,
+-			qca83xx_hw_stats[i].string, ETH_GSTRING_LEN);
+-	}
+-}
+-
+-static u64 qca83xx_get_stat(struct phy_device *phydev, int i)
+-{
+-	struct at803x_hw_stat stat = qca83xx_hw_stats[i];
+-	struct at803x_priv *priv = phydev->priv;
+-	int val;
+-	u64 ret;
+-
+-	if (stat.access_type == MMD)
+-		val = phy_read_mmd(phydev, MDIO_MMD_PCS, stat.reg);
+-	else
+-		val = phy_read(phydev, stat.reg);
+-
+-	if (val < 0) {
+-		ret = U64_MAX;
+-	} else {
+-		val = val & stat.mask;
+-		priv->stats[i] += val;
+-		ret = priv->stats[i];
+-	}
+-
+-	return ret;
+-}
+-
+-static void qca83xx_get_stats(struct phy_device *phydev,
+-			      struct ethtool_stats *stats, u64 *data)
+-{
+-	int i;
+-
+-	for (i = 0; i < ARRAY_SIZE(qca83xx_hw_stats); i++)
+-		data[i] = qca83xx_get_stat(phydev, i);
+-}
+-
+-static int at803x_suspend(struct phy_device *phydev)
+-{
+-	int value;
+-	int wol_enabled;
+-
+-	value = phy_read(phydev, AT803X_INTR_ENABLE);
+-	wol_enabled = value & AT803X_INTR_ENABLE_WOL;
+-
+-	if (wol_enabled)
+-		value = BMCR_ISOLATE;
+-	else
+-		value = BMCR_PDOWN;
+-
+-	phy_modify(phydev, MII_BMCR, 0, value);
+-
+-	return 0;
+-}
+-
+-static int at803x_resume(struct phy_device *phydev)
+-{
+-	return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0);
+-}
+-
+-static int at803x_parse_dt(struct phy_device *phydev)
+-{
+-	struct device_node *node = phydev->mdio.dev.of_node;
+-	struct at803x_priv *priv = phydev->priv;
+-	u32 freq, strength, tw;
+-	unsigned int sel;
+-	int ret;
+-
+-	if (!IS_ENABLED(CONFIG_OF_MDIO))
+-		return 0;
+-
+-	if (of_property_read_bool(node, "qca,disable-smarteee"))
+-		priv->flags |= AT803X_DISABLE_SMARTEEE;
+-
+-	if (of_property_read_bool(node, "qca,disable-hibernation-mode"))
+-		priv->flags |= AT803X_DISABLE_HIBERNATION_MODE;
+-
+-	if (!of_property_read_u32(node, "qca,smarteee-tw-us-1g", &tw)) {
+-		if (!tw || tw > 255) {
+-			phydev_err(phydev, "invalid qca,smarteee-tw-us-1g\n");
+-			return -EINVAL;
+-		}
+-		priv->smarteee_lpi_tw_1g = tw;
+-	}
+-
+-	if (!of_property_read_u32(node, "qca,smarteee-tw-us-100m", &tw)) {
+-		if (!tw || tw > 255) {
+-			phydev_err(phydev, "invalid qca,smarteee-tw-us-100m\n");
+-			return -EINVAL;
+-		}
+-		priv->smarteee_lpi_tw_100m = tw;
+-	}
+-
+-	ret = of_property_read_u32(node, "qca,clk-out-frequency", &freq);
+-	if (!ret) {
+-		switch (freq) {
+-		case 25000000:
+-			sel = AT803X_CLK_OUT_25MHZ_XTAL;
+-			break;
+-		case 50000000:
+-			sel = AT803X_CLK_OUT_50MHZ_PLL;
+-			break;
+-		case 62500000:
+-			sel = AT803X_CLK_OUT_62_5MHZ_PLL;
+-			break;
+-		case 125000000:
+-			sel = AT803X_CLK_OUT_125MHZ_PLL;
+-			break;
+-		default:
+-			phydev_err(phydev, "invalid qca,clk-out-frequency\n");
+-			return -EINVAL;
+-		}
+-
+-		priv->clk_25m_reg |= FIELD_PREP(AT803X_CLK_OUT_MASK, sel);
+-		priv->clk_25m_mask |= AT803X_CLK_OUT_MASK;
+-	}
+-
+-	ret = of_property_read_u32(node, "qca,clk-out-strength", &strength);
+-	if (!ret) {
+-		priv->clk_25m_mask |= AT803X_CLK_OUT_STRENGTH_MASK;
+-		switch (strength) {
+-		case AR803X_STRENGTH_FULL:
+-			priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_FULL;
+-			break;
+-		case AR803X_STRENGTH_HALF:
+-			priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_HALF;
+-			break;
+-		case AR803X_STRENGTH_QUARTER:
+-			priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_QUARTER;
+-			break;
+-		default:
+-			phydev_err(phydev, "invalid qca,clk-out-strength\n");
+-			return -EINVAL;
+-		}
+-	}
+-
+-	return 0;
+-}
+-
+-static int at803x_probe(struct phy_device *phydev)
+-{
+-	struct device *dev = &phydev->mdio.dev;
+-	struct at803x_priv *priv;
+-	int ret;
+-
+-	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+-	if (!priv)
+-		return -ENOMEM;
+-
+-	/* Init LED polarity mode to -1 */
+-	priv->led_polarity_mode = -1;
+-
+-	phydev->priv = priv;
+-
+-	ret = at803x_parse_dt(phydev);
+-	if (ret)
+-		return ret;
+-
+-	return 0;
+-}
+-
+-static int at803x_get_features(struct phy_device *phydev)
+-{
+-	struct at803x_priv *priv = phydev->priv;
+-	int err;
+-
+-	err = genphy_read_abilities(phydev);
+-	if (err)
+-		return err;
+-
+-	if (phydev->drv->phy_id != ATH8031_PHY_ID)
+-		return 0;
+-
+-	/* AR8031/AR8033 have different status registers
+-	 * for copper and fiber operation. However, the
+-	 * extended status register is the same for both
+-	 * operation modes.
+-	 *
+-	 * As a result of that, ESTATUS_1000_XFULL is set
+-	 * to 1 even when operating in copper TP mode.
+-	 *
+-	 * Remove this mode from the supported link modes
+-	 * when not operating in 1000BaseX mode.
+-	 */
+-	if (!priv->is_1000basex)
+-		linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
+-				   phydev->supported);
+-
+-	return 0;
+-}
+-
+-static int at803x_smarteee_config(struct phy_device *phydev)
+-{
+-	struct at803x_priv *priv = phydev->priv;
+-	u16 mask = 0, val = 0;
+-	int ret;
+-
+-	if (priv->flags & AT803X_DISABLE_SMARTEEE)
+-		return phy_modify_mmd(phydev, MDIO_MMD_PCS,
+-				      AT803X_MMD3_SMARTEEE_CTL3,
+-				      AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 0);
+-
+-	if (priv->smarteee_lpi_tw_1g) {
+-		mask |= 0xff00;
+-		val |= priv->smarteee_lpi_tw_1g << 8;
+-	}
+-	if (priv->smarteee_lpi_tw_100m) {
+-		mask |= 0x00ff;
+-		val |= priv->smarteee_lpi_tw_100m;
+-	}
+-	if (!mask)
+-		return 0;
+-
+-	ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL1,
+-			     mask, val);
+-	if (ret)
+-		return ret;
+-
+-	return phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL3,
+-			      AT803X_MMD3_SMARTEEE_CTL3_LPI_EN,
+-			      AT803X_MMD3_SMARTEEE_CTL3_LPI_EN);
+-}
+-
+-static int at803x_clk_out_config(struct phy_device *phydev)
+-{
+-	struct at803x_priv *priv = phydev->priv;
+-
+-	if (!priv->clk_25m_mask)
+-		return 0;
+-
+-	return phy_modify_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M,
+-			      priv->clk_25m_mask, priv->clk_25m_reg);
+-}
+-
+-static int at8031_pll_config(struct phy_device *phydev)
+-{
+-	struct at803x_priv *priv = phydev->priv;
+-
+-	/* The default after hardware reset is PLL OFF. After a soft reset, the
+-	 * values are retained.
+-	 */
+-	if (priv->flags & AT803X_KEEP_PLL_ENABLED)
+-		return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
+-					     0, AT803X_DEBUG_PLL_ON);
+-	else
+-		return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
+-					     AT803X_DEBUG_PLL_ON, 0);
+-}
+-
+-static int at803x_hibernation_mode_config(struct phy_device *phydev)
+-{
+-	struct at803x_priv *priv = phydev->priv;
+-
+-	/* The default after hardware reset is hibernation mode enabled. After
+-	 * software reset, the value is retained.
+-	 */
+-	if (!(priv->flags & AT803X_DISABLE_HIBERNATION_MODE))
+-		return 0;
+-
+-	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL,
+-					 AT803X_DEBUG_HIB_CTRL_PS_HIB_EN, 0);
+-}
+-
+-static int at803x_config_init(struct phy_device *phydev)
+-{
+-	int ret;
+-
+-	/* The RX and TX delay default is:
+-	 *   after HW reset: RX delay enabled and TX delay disabled
+-	 *   after SW reset: RX delay enabled, while TX delay retains the
+-	 *   value before reset.
+-	 */
+-	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+-	    phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
+-		ret = at803x_enable_rx_delay(phydev);
+-	else
+-		ret = at803x_disable_rx_delay(phydev);
+-	if (ret < 0)
+-		return ret;
+-
+-	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+-	    phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
+-		ret = at803x_enable_tx_delay(phydev);
+-	else
+-		ret = at803x_disable_tx_delay(phydev);
+-	if (ret < 0)
+-		return ret;
+-
+-	ret = at803x_smarteee_config(phydev);
+-	if (ret < 0)
+-		return ret;
+-
+-	ret = at803x_clk_out_config(phydev);
+-	if (ret < 0)
+-		return ret;
+-
+-	ret = at803x_hibernation_mode_config(phydev);
+-	if (ret < 0)
+-		return ret;
+-
+-	/* Ar803x extended next page bit is enabled by default. Cisco
+-	 * multigig switches read this bit and attempt to negotiate 10Gbps
+-	 * rates even if the next page bit is disabled. This is incorrect
+-	 * behaviour but we still need to accommodate it. XNP is only needed
+-	 * for 10Gbps support, so disable XNP.
+-	 */
+-	return phy_modify(phydev, MII_ADVERTISE, MDIO_AN_CTRL1_XNP, 0);
+-}
+-
+-static int at803x_ack_interrupt(struct phy_device *phydev)
+-{
+-	int err;
+-
+-	err = phy_read(phydev, AT803X_INTR_STATUS);
+-
+-	return (err < 0) ? err : 0;
+-}
+-
+-static int at803x_config_intr(struct phy_device *phydev)
+-{
+-	int err;
+-	int value;
+-
+-	value = phy_read(phydev, AT803X_INTR_ENABLE);
+-
+-	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
+-		/* Clear any pending interrupts */
+-		err = at803x_ack_interrupt(phydev);
+-		if (err)
+-			return err;
+-
+-		value |= AT803X_INTR_ENABLE_AUTONEG_ERR;
+-		value |= AT803X_INTR_ENABLE_SPEED_CHANGED;
+-		value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED;
+-		value |= AT803X_INTR_ENABLE_LINK_FAIL;
+-		value |= AT803X_INTR_ENABLE_LINK_SUCCESS;
+-
+-		err = phy_write(phydev, AT803X_INTR_ENABLE, value);
+-	} else {
+-		err = phy_write(phydev, AT803X_INTR_ENABLE, 0);
+-		if (err)
+-			return err;
+-
+-		/* Clear any pending interrupts */
+-		err = at803x_ack_interrupt(phydev);
+-	}
+-
+-	return err;
+-}
+-
+-static irqreturn_t at803x_handle_interrupt(struct phy_device *phydev)
+-{
+-	int irq_status, int_enabled;
+-
+-	irq_status = phy_read(phydev, AT803X_INTR_STATUS);
+-	if (irq_status < 0) {
+-		phy_error(phydev);
+-		return IRQ_NONE;
+-	}
+-
+-	/* Read the current enabled interrupts */
+-	int_enabled = phy_read(phydev, AT803X_INTR_ENABLE);
+-	if (int_enabled < 0) {
+-		phy_error(phydev);
+-		return IRQ_NONE;
+-	}
+-
+-	/* See if this was one of our enabled interrupts */
+-	if (!(irq_status & int_enabled))
+-		return IRQ_NONE;
+-
+-	phy_trigger_machine(phydev);
+-
+-	return IRQ_HANDLED;
+-}
+-
+-static void at803x_link_change_notify(struct phy_device *phydev)
+-{
+-	/*
+-	 * Conduct a hardware reset for AT8030 every time a link loss is
+-	 * signalled. This is necessary to circumvent a hardware bug that
+-	 * occurs when the cable is unplugged while TX packets are pending
+-	 * in the FIFO. In such cases, the FIFO enters an error mode it
+-	 * cannot recover from by software.
+-	 */
+-	if (phydev->state == PHY_NOLINK && phydev->mdio.reset_gpio) {
+-		struct at803x_context context;
+-
+-		at803x_context_save(phydev, &context);
+-
+-		phy_device_reset(phydev, 1);
+-		usleep_range(1000, 2000);
+-		phy_device_reset(phydev, 0);
+-		usleep_range(1000, 2000);
+-
+-		at803x_context_restore(phydev, &context);
+-
+-		phydev_dbg(phydev, "%s(): phy was reset\n", __func__);
+-	}
+-}
+-
+-static int at803x_read_specific_status(struct phy_device *phydev,
+-				       struct at803x_ss_mask ss_mask)
+-{
+-	int ss;
+-
+-	/* Read the AT8035 PHY-Specific Status register, which indicates the
+-	 * speed and duplex that the PHY is actually using, irrespective of
+-	 * whether we are in autoneg mode or not.
+-	 */
+-	ss = phy_read(phydev, AT803X_SPECIFIC_STATUS);
+-	if (ss < 0)
+-		return ss;
+-
+-	if (ss & AT803X_SS_SPEED_DUPLEX_RESOLVED) {
+-		int sfc, speed;
+-
+-		sfc = phy_read(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL);
+-		if (sfc < 0)
+-			return sfc;
+-
+-		speed = ss & ss_mask.speed_mask;
+-		speed >>= ss_mask.speed_shift;
+-
+-		switch (speed) {
+-		case AT803X_SS_SPEED_10:
+-			phydev->speed = SPEED_10;
+-			break;
+-		case AT803X_SS_SPEED_100:
+-			phydev->speed = SPEED_100;
+-			break;
+-		case AT803X_SS_SPEED_1000:
+-			phydev->speed = SPEED_1000;
+-			break;
+-		case QCA808X_SS_SPEED_2500:
+-			phydev->speed = SPEED_2500;
+-			break;
+-		}
+-		if (ss & AT803X_SS_DUPLEX)
+-			phydev->duplex = DUPLEX_FULL;
+-		else
+-			phydev->duplex = DUPLEX_HALF;
+-
+-		if (ss & AT803X_SS_MDIX)
+-			phydev->mdix = ETH_TP_MDI_X;
+-		else
+-			phydev->mdix = ETH_TP_MDI;
+-
+-		switch (FIELD_GET(AT803X_SFC_MDI_CROSSOVER_MODE_M, sfc)) {
+-		case AT803X_SFC_MANUAL_MDI:
+-			phydev->mdix_ctrl = ETH_TP_MDI;
+-			break;
+-		case AT803X_SFC_MANUAL_MDIX:
+-			phydev->mdix_ctrl = ETH_TP_MDI_X;
+-			break;
+-		case AT803X_SFC_AUTOMATIC_CROSSOVER:
+-			phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
+-			break;
+-		}
+-	}
+-
+-	return 0;
+-}
+-
+-static int at803x_read_status(struct phy_device *phydev)
+-{
+-	struct at803x_ss_mask ss_mask = { 0 };
+-	int err, old_link = phydev->link;
+-
+-	/* Update the link, but return if there was an error */
+-	err = genphy_update_link(phydev);
+-	if (err)
+-		return err;
+-
+-	/* why bother the PHY if nothing can have changed */
+-	if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link)
+-		return 0;
+-
+-	phydev->speed = SPEED_UNKNOWN;
+-	phydev->duplex = DUPLEX_UNKNOWN;
+-	phydev->pause = 0;
+-	phydev->asym_pause = 0;
+-
+-	err = genphy_read_lpa(phydev);
+-	if (err < 0)
+-		return err;
+-
+-	ss_mask.speed_mask = AT803X_SS_SPEED_MASK;
+-	ss_mask.speed_shift = __bf_shf(AT803X_SS_SPEED_MASK);
+-	err = at803x_read_specific_status(phydev, ss_mask);
+-	if (err < 0)
+-		return err;
+-
+-	if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete)
+-		phy_resolve_aneg_pause(phydev);
+-
+-	return 0;
+-}
+-
+-static int at803x_config_mdix(struct phy_device *phydev, u8 ctrl)
+-{
+-	u16 val;
+-
+-	switch (ctrl) {
+-	case ETH_TP_MDI:
+-		val = AT803X_SFC_MANUAL_MDI;
+-		break;
+-	case ETH_TP_MDI_X:
+-		val = AT803X_SFC_MANUAL_MDIX;
+-		break;
+-	case ETH_TP_MDI_AUTO:
+-		val = AT803X_SFC_AUTOMATIC_CROSSOVER;
+-		break;
+-	default:
+-		return 0;
+-	}
+-
+-	return phy_modify_changed(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL,
+-			  AT803X_SFC_MDI_CROSSOVER_MODE_M,
+-			  FIELD_PREP(AT803X_SFC_MDI_CROSSOVER_MODE_M, val));
+-}
+-
+-static int at803x_prepare_config_aneg(struct phy_device *phydev)
+-{
+-	int ret;
+-
+-	ret = at803x_config_mdix(phydev, phydev->mdix_ctrl);
+-	if (ret < 0)
+-		return ret;
+-
+-	/* Changes of the midx bits are disruptive to the normal operation;
+-	 * therefore any changes to these registers must be followed by a
+-	 * software reset to take effect.
+-	 */
+-	if (ret == 1) {
+-		ret = genphy_soft_reset(phydev);
+-		if (ret < 0)
+-			return ret;
+-	}
+-
+-	return 0;
+-}
+-
+-static int at803x_config_aneg(struct phy_device *phydev)
+-{
+-	struct at803x_priv *priv = phydev->priv;
+-	int ret;
+-
+-	ret = at803x_prepare_config_aneg(phydev);
+-	if (ret)
+-		return ret;
+-
+-	if (priv->is_1000basex)
+-		return genphy_c37_config_aneg(phydev);
+-
+-	return genphy_config_aneg(phydev);
+-}
+-
+-static int at803x_get_downshift(struct phy_device *phydev, u8 *d)
+-{
+-	int val;
+-
+-	val = phy_read(phydev, AT803X_SMART_SPEED);
+-	if (val < 0)
+-		return val;
+-
+-	if (val & AT803X_SMART_SPEED_ENABLE)
+-		*d = FIELD_GET(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, val) + 2;
+-	else
+-		*d = DOWNSHIFT_DEV_DISABLE;
+-
+-	return 0;
+-}
+-
+-static int at803x_set_downshift(struct phy_device *phydev, u8 cnt)
+-{
+-	u16 mask, set;
+-	int ret;
+-
+-	switch (cnt) {
+-	case DOWNSHIFT_DEV_DEFAULT_COUNT:
+-		cnt = AT803X_DEFAULT_DOWNSHIFT;
+-		fallthrough;
+-	case AT803X_MIN_DOWNSHIFT ... AT803X_MAX_DOWNSHIFT:
+-		set = AT803X_SMART_SPEED_ENABLE |
+-		      AT803X_SMART_SPEED_BYPASS_TIMER |
+-		      FIELD_PREP(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, cnt - 2);
+-		mask = AT803X_SMART_SPEED_RETRY_LIMIT_MASK;
+-		break;
+-	case DOWNSHIFT_DEV_DISABLE:
+-		set = 0;
+-		mask = AT803X_SMART_SPEED_ENABLE |
+-		       AT803X_SMART_SPEED_BYPASS_TIMER;
+-		break;
+-	default:
+-		return -EINVAL;
+-	}
+-
+-	ret = phy_modify_changed(phydev, AT803X_SMART_SPEED, mask, set);
+-
+-	/* After changing the smart speed settings, we need to perform a
+-	 * software reset, use phy_init_hw() to make sure we set the
+-	 * reapply any values which might got lost during software reset.
+-	 */
+-	if (ret == 1)
+-		ret = phy_init_hw(phydev);
+-
+-	return ret;
+-}
+-
+-static int at803x_get_tunable(struct phy_device *phydev,
+-			      struct ethtool_tunable *tuna, void *data)
+-{
+-	switch (tuna->id) {
+-	case ETHTOOL_PHY_DOWNSHIFT:
+-		return at803x_get_downshift(phydev, data);
+-	default:
+-		return -EOPNOTSUPP;
+-	}
+-}
+-
+-static int at803x_set_tunable(struct phy_device *phydev,
+-			      struct ethtool_tunable *tuna, const void *data)
+-{
+-	switch (tuna->id) {
+-	case ETHTOOL_PHY_DOWNSHIFT:
+-		return at803x_set_downshift(phydev, *(const u8 *)data);
+-	default:
+-		return -EOPNOTSUPP;
+-	}
+-}
+-
+-static int at803x_cable_test_result_trans(u16 status)
+-{
+-	switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) {
+-	case AT803X_CDT_STATUS_STAT_NORMAL:
+-		return ETHTOOL_A_CABLE_RESULT_CODE_OK;
+-	case AT803X_CDT_STATUS_STAT_SHORT:
+-		return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
+-	case AT803X_CDT_STATUS_STAT_OPEN:
+-		return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
+-	case AT803X_CDT_STATUS_STAT_FAIL:
+-	default:
+-		return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
+-	}
+-}
+-
+-static bool at803x_cdt_test_failed(u16 status)
+-{
+-	return FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status) ==
+-		AT803X_CDT_STATUS_STAT_FAIL;
+-}
+-
+-static bool at803x_cdt_fault_length_valid(u16 status)
+-{
+-	switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) {
+-	case AT803X_CDT_STATUS_STAT_OPEN:
+-	case AT803X_CDT_STATUS_STAT_SHORT:
+-		return true;
+-	}
+-	return false;
+-}
+-
+-static int at803x_cdt_fault_length(int dt)
+-{
+-	/* According to the datasheet the distance to the fault is
+-	 * DELTA_TIME * 0.824 meters.
+-	 *
+-	 * The author suspect the correct formula is:
+-	 *
+-	 *   fault_distance = DELTA_TIME * (c * VF) / 125MHz / 2
+-	 *
+-	 * where c is the speed of light, VF is the velocity factor of
+-	 * the twisted pair cable, 125MHz the counter frequency and
+-	 * we need to divide by 2 because the hardware will measure the
+-	 * round trip time to the fault and back to the PHY.
+-	 *
+-	 * With a VF of 0.69 we get the factor 0.824 mentioned in the
+-	 * datasheet.
+-	 */
+-	return (dt * 824) / 10;
+-}
+-
+-static int at803x_cdt_start(struct phy_device *phydev,
+-			    u32 cdt_start)
+-{
+-	return phy_write(phydev, AT803X_CDT, cdt_start);
+-}
+-
+-static int at803x_cdt_wait_for_completion(struct phy_device *phydev,
+-					  u32 cdt_en)
+-{
+-	int val, ret;
+-
+-	/* One test run takes about 25ms */
+-	ret = phy_read_poll_timeout(phydev, AT803X_CDT, val,
+-				    !(val & cdt_en),
+-				    30000, 100000, true);
+-
+-	return ret < 0 ? ret : 0;
+-}
+-
+-static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair)
+-{
+-	static const int ethtool_pair[] = {
+-		ETHTOOL_A_CABLE_PAIR_A,
+-		ETHTOOL_A_CABLE_PAIR_B,
+-		ETHTOOL_A_CABLE_PAIR_C,
+-		ETHTOOL_A_CABLE_PAIR_D,
+-	};
+-	int ret, val;
+-
+-	val = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) |
+-	      AT803X_CDT_ENABLE_TEST;
+-	ret = at803x_cdt_start(phydev, val);
+-	if (ret)
+-		return ret;
+-
+-	ret = at803x_cdt_wait_for_completion(phydev, AT803X_CDT_ENABLE_TEST);
+-	if (ret)
+-		return ret;
+-
+-	val = phy_read(phydev, AT803X_CDT_STATUS);
+-	if (val < 0)
+-		return val;
+-
+-	if (at803x_cdt_test_failed(val))
+-		return 0;
+-
+-	ethnl_cable_test_result(phydev, ethtool_pair[pair],
+-				at803x_cable_test_result_trans(val));
+-
+-	if (at803x_cdt_fault_length_valid(val)) {
+-		val = FIELD_GET(AT803X_CDT_STATUS_DELTA_TIME_MASK, val);
+-		ethnl_cable_test_fault_length(phydev, ethtool_pair[pair],
+-					      at803x_cdt_fault_length(val));
+-	}
+-
+-	return 1;
+-}
+-
+-static int at803x_cable_test_get_status(struct phy_device *phydev,
+-					bool *finished, unsigned long pair_mask)
+-{
+-	int retries = 20;
+-	int pair, ret;
+-
+-	*finished = false;
+-
+-	/* According to the datasheet the CDT can be performed when
+-	 * there is no link partner or when the link partner is
+-	 * auto-negotiating. Starting the test will restart the AN
+-	 * automatically. It seems that doing this repeatedly we will
+-	 * get a slot where our link partner won't disturb our
+-	 * measurement.
+-	 */
+-	while (pair_mask && retries--) {
+-		for_each_set_bit(pair, &pair_mask, 4) {
+-			ret = at803x_cable_test_one_pair(phydev, pair);
+-			if (ret < 0)
+-				return ret;
+-			if (ret)
+-				clear_bit(pair, &pair_mask);
+-		}
+-		if (pair_mask)
+-			msleep(250);
+-	}
+-
+-	*finished = true;
+-
+-	return 0;
+-}
+-
+-static void at803x_cable_test_autoneg(struct phy_device *phydev)
+-{
+-	/* Enable auto-negotiation, but advertise no capabilities, no link
+-	 * will be established. A restart of the auto-negotiation is not
+-	 * required, because the cable test will automatically break the link.
+-	 */
+-	phy_write(phydev, MII_BMCR, BMCR_ANENABLE);
+-	phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA);
+-}
+-
+-static int at803x_cable_test_start(struct phy_device *phydev)
+-{
+-	at803x_cable_test_autoneg(phydev);
+-	/* we do all the (time consuming) work later */
+-	return 0;
+-}
+-
+-static int at8031_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev,
+-					    unsigned int selector)
+-{
+-	struct phy_device *phydev = rdev_get_drvdata(rdev);
+-
+-	if (selector)
+-		return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
+-					     0, AT803X_DEBUG_RGMII_1V8);
+-	else
+-		return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
+-					     AT803X_DEBUG_RGMII_1V8, 0);
+-}
+-
+-static int at8031_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev)
+-{
+-	struct phy_device *phydev = rdev_get_drvdata(rdev);
+-	int val;
+-
+-	val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F);
+-	if (val < 0)
+-		return val;
+-
+-	return (val & AT803X_DEBUG_RGMII_1V8) ? 1 : 0;
+-}
+-
+-static const struct regulator_ops vddio_regulator_ops = {
+-	.list_voltage = regulator_list_voltage_table,
+-	.set_voltage_sel = at8031_rgmii_reg_set_voltage_sel,
+-	.get_voltage_sel = at8031_rgmii_reg_get_voltage_sel,
+-};
+-
+-static const unsigned int vddio_voltage_table[] = {
+-	1500000,
+-	1800000,
+-};
+-
+-static const struct regulator_desc vddio_desc = {
+-	.name = "vddio",
+-	.of_match = of_match_ptr("vddio-regulator"),
+-	.n_voltages = ARRAY_SIZE(vddio_voltage_table),
+-	.volt_table = vddio_voltage_table,
+-	.ops = &vddio_regulator_ops,
+-	.type = REGULATOR_VOLTAGE,
+-	.owner = THIS_MODULE,
+-};
+-
+-static const struct regulator_ops vddh_regulator_ops = {
+-};
+-
+-static const struct regulator_desc vddh_desc = {
+-	.name = "vddh",
+-	.of_match = of_match_ptr("vddh-regulator"),
+-	.n_voltages = 1,
+-	.fixed_uV = 2500000,
+-	.ops = &vddh_regulator_ops,
+-	.type = REGULATOR_VOLTAGE,
+-	.owner = THIS_MODULE,
+-};
+-
+-static int at8031_register_regulators(struct phy_device *phydev)
+-{
+-	struct at803x_priv *priv = phydev->priv;
+-	struct device *dev = &phydev->mdio.dev;
+-	struct regulator_config config = { };
+-
+-	config.dev = dev;
+-	config.driver_data = phydev;
+-
+-	priv->vddio_rdev = devm_regulator_register(dev, &vddio_desc, &config);
+-	if (IS_ERR(priv->vddio_rdev)) {
+-		phydev_err(phydev, "failed to register VDDIO regulator\n");
+-		return PTR_ERR(priv->vddio_rdev);
+-	}
+-
+-	priv->vddh_rdev = devm_regulator_register(dev, &vddh_desc, &config);
+-	if (IS_ERR(priv->vddh_rdev)) {
+-		phydev_err(phydev, "failed to register VDDH regulator\n");
+-		return PTR_ERR(priv->vddh_rdev);
+-	}
+-
+-	return 0;
+-}
+-
+-static int at8031_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
+-{
+-	struct phy_device *phydev = upstream;
+-	__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_support);
+-	__ETHTOOL_DECLARE_LINK_MODE_MASK(sfp_support);
+-	DECLARE_PHY_INTERFACE_MASK(interfaces);
+-	phy_interface_t iface;
+-
+-	linkmode_zero(phy_support);
+-	phylink_set(phy_support, 1000baseX_Full);
+-	phylink_set(phy_support, 1000baseT_Full);
+-	phylink_set(phy_support, Autoneg);
+-	phylink_set(phy_support, Pause);
+-	phylink_set(phy_support, Asym_Pause);
+-
+-	linkmode_zero(sfp_support);
+-	sfp_parse_support(phydev->sfp_bus, id, sfp_support, interfaces);
+-	/* Some modules support 10G modes as well as others we support.
+-	 * Mask out non-supported modes so the correct interface is picked.
+-	 */
+-	linkmode_and(sfp_support, phy_support, sfp_support);
+-
+-	if (linkmode_empty(sfp_support)) {
+-		dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n");
+-		return -EINVAL;
+-	}
+-
+-	iface = sfp_select_interface(phydev->sfp_bus, sfp_support);
+-
+-	/* Only 1000Base-X is supported by AR8031/8033 as the downstream SerDes
+-	 * interface for use with SFP modules.
+-	 * However, some copper modules detected as having a preferred SGMII
+-	 * interface do default to and function in 1000Base-X mode, so just
+-	 * print a warning and allow such modules, as they may have some chance
+-	 * of working.
+-	 */
+-	if (iface == PHY_INTERFACE_MODE_SGMII)
+-		dev_warn(&phydev->mdio.dev, "module may not function if 1000Base-X not supported\n");
+-	else if (iface != PHY_INTERFACE_MODE_1000BASEX)
+-		return -EINVAL;
+-
+-	return 0;
+-}
+-
+-static const struct sfp_upstream_ops at8031_sfp_ops = {
+-	.attach = phy_sfp_attach,
+-	.detach = phy_sfp_detach,
+-	.module_insert = at8031_sfp_insert,
+-};
+-
+-static int at8031_parse_dt(struct phy_device *phydev)
+-{
+-	struct device_node *node = phydev->mdio.dev.of_node;
+-	struct at803x_priv *priv = phydev->priv;
+-	int ret;
+-
+-	if (of_property_read_bool(node, "qca,keep-pll-enabled"))
+-		priv->flags |= AT803X_KEEP_PLL_ENABLED;
+-
+-	ret = at8031_register_regulators(phydev);
+-	if (ret < 0)
+-		return ret;
+-
+-	ret = devm_regulator_get_enable_optional(&phydev->mdio.dev,
+-						 "vddio");
+-	if (ret) {
+-		phydev_err(phydev, "failed to get VDDIO regulator\n");
+-		return ret;
+-	}
+-
+-	/* Only AR8031/8033 support 1000Base-X for SFP modules */
+-	return phy_sfp_probe(phydev, &at8031_sfp_ops);
+-}
+-
+-static int at8031_probe(struct phy_device *phydev)
+-{
+-	struct at803x_priv *priv = phydev->priv;
+-	int mode_cfg;
+-	int ccr;
+-	int ret;
+-
+-	ret = at803x_probe(phydev);
+-	if (ret)
+-		return ret;
+-
+-	/* Only supported on AR8031/AR8033, the AR8030/AR8035 use strapping
+-	 * options.
+-	 */
+-	ret = at8031_parse_dt(phydev);
+-	if (ret)
+-		return ret;
+-
+-	ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG);
+-	if (ccr < 0)
+-		return ccr;
+-	mode_cfg = ccr & AT803X_MODE_CFG_MASK;
+-
+-	switch (mode_cfg) {
+-	case AT803X_MODE_CFG_BX1000_RGMII_50OHM:
+-	case AT803X_MODE_CFG_BX1000_RGMII_75OHM:
+-		priv->is_1000basex = true;
+-		fallthrough;
+-	case AT803X_MODE_CFG_FX100_RGMII_50OHM:
+-	case AT803X_MODE_CFG_FX100_RGMII_75OHM:
+-		priv->is_fiber = true;
+-		break;
+-	}
+-
+-	/* Disable WoL in 1588 register which is enabled
+-	 * by default
+-	 */
+-	return phy_modify_mmd(phydev, MDIO_MMD_PCS,
+-			      AT803X_PHY_MMD3_WOL_CTRL,
+-			      AT803X_WOL_EN, 0);
+-}
+-
+-static int at8031_config_init(struct phy_device *phydev)
+-{
+-	struct at803x_priv *priv = phydev->priv;
+-	int ret;
+-
+-	/* Some bootloaders leave the fiber page selected.
+-	 * Switch to the appropriate page (fiber or copper), as otherwise we
+-	 * read the PHY capabilities from the wrong page.
+-	 */
+-	phy_lock_mdio_bus(phydev);
+-	ret = at803x_write_page(phydev,
+-				priv->is_fiber ? AT803X_PAGE_FIBER :
+-						 AT803X_PAGE_COPPER);
+-	phy_unlock_mdio_bus(phydev);
+-	if (ret)
+-		return ret;
+-
+-	ret = at8031_pll_config(phydev);
+-	if (ret < 0)
+-		return ret;
+-
+-	return at803x_config_init(phydev);
+-}
+-
+-static int at8031_set_wol(struct phy_device *phydev,
+-			  struct ethtool_wolinfo *wol)
+-{
+-	int ret;
+-
+-	/* First setup MAC address and enable WOL interrupt */
+-	ret = at803x_set_wol(phydev, wol);
+-	if (ret)
+-		return ret;
+-
+-	if (wol->wolopts & WAKE_MAGIC)
+-		/* Enable WOL function for 1588 */
+-		ret = phy_modify_mmd(phydev, MDIO_MMD_PCS,
+-				     AT803X_PHY_MMD3_WOL_CTRL,
+-				     0, AT803X_WOL_EN);
+-	else
+-		/* Disable WoL function for 1588 */
+-		ret = phy_modify_mmd(phydev, MDIO_MMD_PCS,
+-				     AT803X_PHY_MMD3_WOL_CTRL,
+-				     AT803X_WOL_EN, 0);
+-
+-	return ret;
+-}
+-
+-static int at8031_config_intr(struct phy_device *phydev)
+-{
+-	struct at803x_priv *priv = phydev->priv;
+-	int err, value = 0;
+-
+-	if (phydev->interrupts == PHY_INTERRUPT_ENABLED &&
+-	    priv->is_fiber) {
+-		/* Clear any pending interrupts */
+-		err = at803x_ack_interrupt(phydev);
+-		if (err)
+-			return err;
+-
+-		value |= AT803X_INTR_ENABLE_LINK_FAIL_BX;
+-		value |= AT803X_INTR_ENABLE_LINK_SUCCESS_BX;
+-
+-		err = phy_set_bits(phydev, AT803X_INTR_ENABLE, value);
+-		if (err)
+-			return err;
+-	}
+-
+-	return at803x_config_intr(phydev);
+-}
+-
+-/* AR8031 and AR8033 share the same read status logic */
+-static int at8031_read_status(struct phy_device *phydev)
+-{
+-	struct at803x_priv *priv = phydev->priv;
+-
+-	if (priv->is_1000basex)
+-		return genphy_c37_read_status(phydev);
+-
+-	return at803x_read_status(phydev);
+-}
+-
+-/* AR8031 and AR8035 share the same cable test get status reg */
+-static int at8031_cable_test_get_status(struct phy_device *phydev,
+-					bool *finished)
+-{
+-	return at803x_cable_test_get_status(phydev, finished, 0xf);
+-}
+-
+-/* AR8031 and AR8035 share the same cable test start logic */
+-static int at8031_cable_test_start(struct phy_device *phydev)
+-{
+-	at803x_cable_test_autoneg(phydev);
+-	phy_write(phydev, MII_CTRL1000, 0);
+-	/* we do all the (time consuming) work later */
+-	return 0;
+-}
+-
+-/* AR8032, AR9331 and QCA9561 share the same cable test get status reg */
+-static int at8032_cable_test_get_status(struct phy_device *phydev,
+-					bool *finished)
+-{
+-	return at803x_cable_test_get_status(phydev, finished, 0x3);
+-}
+-
+-static int at8035_parse_dt(struct phy_device *phydev)
+-{
+-	struct at803x_priv *priv = phydev->priv;
+-
+-	/* Mask is set by the generic at803x_parse_dt
+-	 * if property is set. Assume property is set
+-	 * with the mask not zero.
+-	 */
+-	if (priv->clk_25m_mask) {
+-		/* Fixup for the AR8030/AR8035. This chip has another mask and
+-		 * doesn't support the DSP reference. Eg. the lowest bit of the
+-		 * mask. The upper two bits select the same frequencies. Mask
+-		 * the lowest bit here.
+-		 *
+-		 * Warning:
+-		 *   There was no datasheet for the AR8030 available so this is
+-		 *   just a guess. But the AR8035 is listed as pin compatible
+-		 *   to the AR8030 so there might be a good chance it works on
+-		 *   the AR8030 too.
+-		 */
+-		priv->clk_25m_reg &= AT8035_CLK_OUT_MASK;
+-		priv->clk_25m_mask &= AT8035_CLK_OUT_MASK;
+-	}
+-
+-	return 0;
+-}
+-
+-/* AR8030 and AR8035 shared the same special mask for clk_25m */
+-static int at8035_probe(struct phy_device *phydev)
+-{
+-	int ret;
+-
+-	ret = at803x_probe(phydev);
+-	if (ret)
+-		return ret;
+-
+-	return at8035_parse_dt(phydev);
+-}
+-
+-static int qca83xx_config_init(struct phy_device *phydev)
+-{
+-	u8 switch_revision;
+-
+-	switch_revision = phydev->dev_flags & QCA8K_DEVFLAGS_REVISION_MASK;
+-
+-	switch (switch_revision) {
+-	case 1:
+-		/* For 100M waveform */
+-		at803x_debug_reg_write(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0x02ea);
+-		/* Turn on Gigabit clock */
+-		at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x68a0);
+-		break;
+-
+-	case 2:
+-		phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0);
+-		fallthrough;
+-	case 4:
+-		phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f);
+-		at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x6860);
+-		at803x_debug_reg_write(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0x2c46);
+-		at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3C, 0x6000);
+-		break;
+-	}
+-
+-	/* Following original QCA sourcecode set port to prefer master */
+-	phy_set_bits(phydev, MII_CTRL1000, CTL1000_PREFER_MASTER);
+-
+-	return 0;
+-}
+-
+-static int qca8327_config_init(struct phy_device *phydev)
+-{
+-	/* QCA8327 require DAC amplitude adjustment for 100m set to +6%.
+-	 * Disable on init and enable only with 100m speed following
+-	 * qca original source code.
+-	 */
+-	at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
+-			      QCA8327_DEBUG_MANU_CTRL_EN, 0);
+-
+-	return qca83xx_config_init(phydev);
+-}
+-
+-static void qca83xx_link_change_notify(struct phy_device *phydev)
+-{
+-	/* Set DAC Amplitude adjustment to +6% for 100m on link running */
+-	if (phydev->state == PHY_RUNNING) {
+-		if (phydev->speed == SPEED_100)
+-			at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
+-					      QCA8327_DEBUG_MANU_CTRL_EN,
+-					      QCA8327_DEBUG_MANU_CTRL_EN);
+-	} else {
+-		/* Reset DAC Amplitude adjustment */
+-		at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
+-				      QCA8327_DEBUG_MANU_CTRL_EN, 0);
+-	}
+-}
+-
+-static int qca83xx_resume(struct phy_device *phydev)
+-{
+-	int ret, val;
+-
+-	/* Skip reset if not suspended */
+-	if (!phydev->suspended)
+-		return 0;
+-
+-	/* Reinit the port, reset values set by suspend */
+-	qca83xx_config_init(phydev);
+-
+-	/* Reset the port on port resume */
+-	phy_set_bits(phydev, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
+-
+-	/* On resume from suspend the switch execute a reset and
+-	 * restart auto-negotiation. Wait for reset to complete.
+-	 */
+-	ret = phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET),
+-				    50000, 600000, true);
+-	if (ret)
+-		return ret;
+-
+-	usleep_range(1000, 2000);
+-
+-	return 0;
+-}
+-
+-static int qca83xx_suspend(struct phy_device *phydev)
+-{
+-	at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_GREEN,
+-			      AT803X_DEBUG_GATE_CLK_IN1000, 0);
+-
+-	at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL,
+-			      AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE |
+-			      AT803X_DEBUG_HIB_CTRL_SEL_RST_80U, 0);
+-
+-	return 0;
+-}
+-
+-static int qca8337_suspend(struct phy_device *phydev)
+-{
+-	/* Only QCA8337 support actual suspend. */
+-	genphy_suspend(phydev);
+-
+-	return qca83xx_suspend(phydev);
+-}
+-
+-static int qca8327_suspend(struct phy_device *phydev)
+-{
+-	u16 mask = 0;
+-
+-	/* QCA8327 cause port unreliability when phy suspend
+-	 * is set.
+-	 */
+-	mask |= ~(BMCR_SPEED1000 | BMCR_FULLDPLX);
+-	phy_modify(phydev, MII_BMCR, mask, 0);
+-
+-	return qca83xx_suspend(phydev);
+-}
+-
+-static int qca808x_phy_fast_retrain_config(struct phy_device *phydev)
+-{
+-	int ret;
+-
+-	/* Enable fast retrain */
+-	ret = genphy_c45_fast_retrain(phydev, true);
+-	if (ret)
+-		return ret;
+-
+-	phy_write_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_TOP_OPTION1,
+-		      QCA808X_TOP_OPTION1_DATA);
+-	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB,
+-		      QCA808X_MSE_THRESHOLD_20DB_VALUE);
+-	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB,
+-		      QCA808X_MSE_THRESHOLD_17DB_VALUE);
+-	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB,
+-		      QCA808X_MSE_THRESHOLD_27DB_VALUE);
+-	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB,
+-		      QCA808X_MSE_THRESHOLD_28DB_VALUE);
+-	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_1,
+-		      QCA808X_MMD3_DEBUG_1_VALUE);
+-	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_4,
+-		      QCA808X_MMD3_DEBUG_4_VALUE);
+-	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_5,
+-		      QCA808X_MMD3_DEBUG_5_VALUE);
+-	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_3,
+-		      QCA808X_MMD3_DEBUG_3_VALUE);
+-	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_6,
+-		      QCA808X_MMD3_DEBUG_6_VALUE);
+-	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_2,
+-		      QCA808X_MMD3_DEBUG_2_VALUE);
+-
+-	return 0;
+-}
+-
+-static int qca808x_phy_ms_seed_enable(struct phy_device *phydev, bool enable)
+-{
+-	u16 seed_value;
+-
+-	if (!enable)
+-		return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED,
+-				QCA808X_MASTER_SLAVE_SEED_ENABLE, 0);
+-
+-	seed_value = prandom_u32_max(QCA808X_MASTER_SLAVE_SEED_RANGE);
+-	return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED,
+-			QCA808X_MASTER_SLAVE_SEED_CFG | QCA808X_MASTER_SLAVE_SEED_ENABLE,
+-			FIELD_PREP(QCA808X_MASTER_SLAVE_SEED_CFG, seed_value) |
+-			QCA808X_MASTER_SLAVE_SEED_ENABLE);
+-}
+-
+-static bool qca808x_is_prefer_master(struct phy_device *phydev)
+-{
+-	return (phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_FORCE) ||
+-		(phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_PREFERRED);
+-}
+-
+-static bool qca808x_has_fast_retrain_or_slave_seed(struct phy_device *phydev)
+-{
+-	return linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported);
+-}
+-
+-static int qca808x_config_init(struct phy_device *phydev)
+-{
+-	int ret;
+-
+-	/* Active adc&vga on 802.3az for the link 1000M and 100M */
+-	ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_ADDR_CLD_CTRL7,
+-			     QCA808X_8023AZ_AFE_CTRL_MASK, QCA808X_8023AZ_AFE_EN);
+-	if (ret)
+-		return ret;
+-
+-	/* Adjust the threshold on 802.3az for the link 1000M */
+-	ret = phy_write_mmd(phydev, MDIO_MMD_PCS,
+-			    QCA808X_PHY_MMD3_AZ_TRAINING_CTRL,
+-			    QCA808X_MMD3_AZ_TRAINING_VAL);
+-	if (ret)
+-		return ret;
+-
+-	if (qca808x_has_fast_retrain_or_slave_seed(phydev)) {
+-		/* Config the fast retrain for the link 2500M */
+-		ret = qca808x_phy_fast_retrain_config(phydev);
+-		if (ret)
+-			return ret;
+-
+-		ret = genphy_read_master_slave(phydev);
+-		if (ret < 0)
+-			return ret;
+-
+-		if (!qca808x_is_prefer_master(phydev)) {
+-			/* Enable seed and configure lower ramdom seed to make phy
+-			 * linked as slave mode.
+-			 */
+-			ret = qca808x_phy_ms_seed_enable(phydev, true);
+-			if (ret)
+-				return ret;
+-		}
+-	}
+-
+-	/* Configure adc threshold as 100mv for the link 10M */
+-	return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD,
+-				     QCA808X_ADC_THRESHOLD_MASK,
+-				     QCA808X_ADC_THRESHOLD_100MV);
+-}
+-
+-static int qca808x_read_status(struct phy_device *phydev)
+-{
+-	struct at803x_ss_mask ss_mask = { 0 };
+-	int ret;
+-
+-	ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);
+-	if (ret < 0)
+-		return ret;
+-
+-	linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->lp_advertising,
+-			 ret & MDIO_AN_10GBT_STAT_LP2_5G);
+-
+-	ret = genphy_read_status(phydev);
+-	if (ret)
+-		return ret;
+-
+-	/* qca8081 takes the different bits for speed value from at803x */
+-	ss_mask.speed_mask = QCA808X_SS_SPEED_MASK;
+-	ss_mask.speed_shift = __bf_shf(QCA808X_SS_SPEED_MASK);
+-	ret = at803x_read_specific_status(phydev, ss_mask);
+-	if (ret < 0)
+-		return ret;
+-
+-	if (phydev->link) {
+-		if (phydev->speed == SPEED_2500)
+-			phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
+-		else
+-			phydev->interface = PHY_INTERFACE_MODE_SGMII;
+-	} else {
+-		/* generate seed as a lower random value to make PHY linked as SLAVE easily,
+-		 * except for master/slave configuration fault detected or the master mode
+-		 * preferred.
+-		 *
+-		 * the reason for not putting this code into the function link_change_notify is
+-		 * the corner case where the link partner is also the qca8081 PHY and the seed
+-		 * value is configured as the same value, the link can't be up and no link change
+-		 * occurs.
+-		 */
+-		if (qca808x_has_fast_retrain_or_slave_seed(phydev)) {
+-			if (phydev->master_slave_state == MASTER_SLAVE_STATE_ERR ||
+-			    qca808x_is_prefer_master(phydev)) {
+-				qca808x_phy_ms_seed_enable(phydev, false);
+-			} else {
+-				qca808x_phy_ms_seed_enable(phydev, true);
+-			}
+-		}
+-	}
+-
+-	return 0;
+-}
+-
+-static int qca808x_soft_reset(struct phy_device *phydev)
+-{
+-	int ret;
+-
+-	ret = genphy_soft_reset(phydev);
+-	if (ret < 0)
+-		return ret;
+-
+-	if (qca808x_has_fast_retrain_or_slave_seed(phydev))
+-		ret = qca808x_phy_ms_seed_enable(phydev, true);
+-
+-	return ret;
+-}
+-
+-static bool qca808x_cdt_fault_length_valid(int cdt_code)
+-{
+-	switch (cdt_code) {
+-	case QCA808X_CDT_STATUS_STAT_SAME_SHORT:
+-	case QCA808X_CDT_STATUS_STAT_SAME_OPEN:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT:
+-		return true;
+-	default:
+-		return false;
+-	}
+-}
+-
+-static int qca808x_cable_test_result_trans(int cdt_code)
+-{
+-	switch (cdt_code) {
+-	case QCA808X_CDT_STATUS_STAT_NORMAL:
+-		return ETHTOOL_A_CABLE_RESULT_CODE_OK;
+-	case QCA808X_CDT_STATUS_STAT_SAME_SHORT:
+-		return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
+-	case QCA808X_CDT_STATUS_STAT_SAME_OPEN:
+-		return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT:
+-		return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;
+-	case QCA808X_CDT_STATUS_STAT_FAIL:
+-	default:
+-		return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
+-	}
+-}
+-
+-static int qca808x_cdt_fault_length(struct phy_device *phydev, int pair,
+-				    int result)
+-{
+-	int val;
+-	u32 cdt_length_reg = 0;
+-
+-	switch (pair) {
+-	case ETHTOOL_A_CABLE_PAIR_A:
+-		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_A;
+-		break;
+-	case ETHTOOL_A_CABLE_PAIR_B:
+-		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_B;
+-		break;
+-	case ETHTOOL_A_CABLE_PAIR_C:
+-		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_C;
+-		break;
+-	case ETHTOOL_A_CABLE_PAIR_D:
+-		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_D;
+-		break;
+-	default:
+-		return -EINVAL;
+-	}
+-
+-	val = phy_read_mmd(phydev, MDIO_MMD_PCS, cdt_length_reg);
+-	if (val < 0)
+-		return val;
+-
+-	if (result == ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT)
+-		val = FIELD_GET(QCA808X_CDT_DIAG_LENGTH_SAME_SHORT, val);
+-	else
+-		val = FIELD_GET(QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT, val);
+-
+-	return at803x_cdt_fault_length(val);
+-}
+-
+-static int qca808x_cable_test_start(struct phy_device *phydev)
+-{
+-	int ret;
+-
+-	/* perform CDT with the following configs:
+-	 * 1. disable hibernation.
+-	 * 2. force PHY working in MDI mode.
+-	 * 3. for PHY working in 1000BaseT.
+-	 * 4. configure the threshold.
+-	 */
+-
+-	ret = at803x_debug_reg_mask(phydev, QCA808X_DBG_AN_TEST, QCA808X_HIBERNATION_EN, 0);
+-	if (ret < 0)
+-		return ret;
+-
+-	ret = at803x_config_mdix(phydev, ETH_TP_MDI);
+-	if (ret < 0)
+-		return ret;
+-
+-	/* Force 1000base-T needs to configure PMA/PMD and MII_BMCR */
+-	phydev->duplex = DUPLEX_FULL;
+-	phydev->speed = SPEED_1000;
+-	ret = genphy_c45_pma_setup_forced(phydev);
+-	if (ret < 0)
+-		return ret;
+-
+-	ret = genphy_setup_forced(phydev);
+-	if (ret < 0)
+-		return ret;
+-
+-	/* configure the thresholds for open, short, pair ok test */
+-	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8074, 0xc040);
+-	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8076, 0xc040);
+-	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8077, 0xa060);
+-	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8078, 0xc050);
+-	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060);
+-	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807e, 0xb060);
+-
+-	return 0;
+-}
+-
+-static int qca808x_cable_test_get_pair_status(struct phy_device *phydev, u8 pair,
+-					      u16 status)
+-{
+-	int length, result;
+-	u16 pair_code;
+-
+-	switch (pair) {
+-	case ETHTOOL_A_CABLE_PAIR_A:
+-		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_A, status);
+-		break;
+-	case ETHTOOL_A_CABLE_PAIR_B:
+-		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_B, status);
+-		break;
+-	case ETHTOOL_A_CABLE_PAIR_C:
+-		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_C, status);
+-		break;
+-	case ETHTOOL_A_CABLE_PAIR_D:
+-		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_D, status);
+-		break;
+-	default:
+-		return -EINVAL;
+-	}
+-
+-	result = qca808x_cable_test_result_trans(pair_code);
+-	ethnl_cable_test_result(phydev, pair, result);
+-
+-	if (qca808x_cdt_fault_length_valid(pair_code)) {
+-		length = qca808x_cdt_fault_length(phydev, pair, result);
+-		ethnl_cable_test_fault_length(phydev, pair, length);
+-	}
+-
+-	return 0;
+-}
+-
+-static int qca808x_cable_test_get_status(struct phy_device *phydev, bool *finished)
+-{
+-	int ret, val;
+-
+-	*finished = false;
+-
+-	val = QCA808X_CDT_ENABLE_TEST |
+-	      QCA808X_CDT_LENGTH_UNIT;
+-	ret = at803x_cdt_start(phydev, val);
+-	if (ret)
+-		return ret;
+-
+-	ret = at803x_cdt_wait_for_completion(phydev, QCA808X_CDT_ENABLE_TEST);
+-	if (ret)
+-		return ret;
+-
+-	val = phy_read_mmd(phydev, MDIO_MMD_PCS, QCA808X_MMD3_CDT_STATUS);
+-	if (val < 0)
+-		return val;
+-
+-	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_A, val);
+-	if (ret)
+-		return ret;
+-
+-	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_B, val);
+-	if (ret)
+-		return ret;
+-
+-	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_C, val);
+-	if (ret)
+-		return ret;
+-
+-	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_D, val);
+-	if (ret)
+-		return ret;
+-
+-	*finished = true;
+-
+-	return 0;
+-}
+-
+-static int qca808x_get_features(struct phy_device *phydev)
+-{
+-	int ret;
+-
+-	ret = genphy_c45_pma_read_abilities(phydev);
+-	if (ret)
+-		return ret;
+-
+-	/* The autoneg ability is not existed in bit3 of MMD7.1,
+-	 * but it is supported by qca808x PHY, so we add it here
+-	 * manually.
+-	 */
+-	linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
+-
+-	/* As for the qca8081 1G version chip, the 2500baseT ability is also
+-	 * existed in the bit0 of MMD1.21, we need to remove it manually if
+-	 * it is the qca8081 1G chip according to the bit0 of MMD7.0x901d.
+-	 */
+-	ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_CHIP_TYPE);
+-	if (ret < 0)
+-		return ret;
+-
+-	if (QCA808X_PHY_CHIP_TYPE_1G & ret)
+-		linkmode_clear_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported);
+-
+-	return 0;
+-}
+-
+-static int qca808x_config_aneg(struct phy_device *phydev)
+-{
+-	int phy_ctrl = 0;
+-	int ret;
+-
+-	ret = at803x_prepare_config_aneg(phydev);
+-	if (ret)
+-		return ret;
+-
+-	/* The reg MII_BMCR also needs to be configured for force mode, the
+-	 * genphy_config_aneg is also needed.
+-	 */
+-	if (phydev->autoneg == AUTONEG_DISABLE)
+-		genphy_c45_pma_setup_forced(phydev);
+-
+-	if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->advertising))
+-		phy_ctrl = MDIO_AN_10GBT_CTRL_ADV2_5G;
+-
+-	ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
+-				     MDIO_AN_10GBT_CTRL_ADV2_5G, phy_ctrl);
+-	if (ret < 0)
+-		return ret;
+-
+-	return __genphy_config_aneg(phydev, ret);
+-}
+-
+-static void qca808x_link_change_notify(struct phy_device *phydev)
+-{
+-	/* Assert interface sgmii fifo on link down, deassert it on link up,
+-	 * the interface device address is always phy address added by 1.
+-	 */
+-	mdiobus_c45_modify_changed(phydev->mdio.bus, phydev->mdio.addr + 1,
+-				   MDIO_MMD_PMAPMD, QCA8081_PHY_SERDES_MMD1_FIFO_CTRL,
+-				   QCA8081_PHY_FIFO_RSTN,
+-				   phydev->link ? QCA8081_PHY_FIFO_RSTN : 0);
+-}
+-
+-static int qca808x_led_parse_netdev(struct phy_device *phydev, unsigned long rules,
+-				    u16 *offload_trigger)
+-{
+-	/* Parsing specific to netdev trigger */
+-	if (test_bit(TRIGGER_NETDEV_TX, &rules))
+-		*offload_trigger |= QCA808X_LED_TX_BLINK;
+-	if (test_bit(TRIGGER_NETDEV_RX, &rules))
+-		*offload_trigger |= QCA808X_LED_RX_BLINK;
+-	if (test_bit(TRIGGER_NETDEV_LINK_10, &rules))
+-		*offload_trigger |= QCA808X_LED_SPEED10_ON;
+-	if (test_bit(TRIGGER_NETDEV_LINK_100, &rules))
+-		*offload_trigger |= QCA808X_LED_SPEED100_ON;
+-	if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules))
+-		*offload_trigger |= QCA808X_LED_SPEED1000_ON;
+-	if (test_bit(TRIGGER_NETDEV_LINK_2500, &rules))
+-		*offload_trigger |= QCA808X_LED_SPEED2500_ON;
+-	if (test_bit(TRIGGER_NETDEV_HALF_DUPLEX, &rules))
+-		*offload_trigger |= QCA808X_LED_HALF_DUPLEX_ON;
+-	if (test_bit(TRIGGER_NETDEV_FULL_DUPLEX, &rules))
+-		*offload_trigger |= QCA808X_LED_FULL_DUPLEX_ON;
+-
+-	if (rules && !*offload_trigger)
+-		return -EOPNOTSUPP;
+-
+-	/* Enable BLINK_CHECK_BYPASS by default to make the LED
+-	 * blink even with duplex or speed mode not enabled.
+-	 */
+-	*offload_trigger |= QCA808X_LED_BLINK_CHECK_BYPASS;
+-
+-	return 0;
+-}
+-
+-static int qca808x_led_hw_control_enable(struct phy_device *phydev, u8 index)
+-{
+-	u16 reg;
+-
+-	if (index > 2)
+-		return -EINVAL;
+-
+-	reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
+-
+-	return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg,
+-				  QCA808X_LED_FORCE_EN);
+-}
+-
+-static int qca808x_led_hw_is_supported(struct phy_device *phydev, u8 index,
+-				       unsigned long rules)
+-{
+-	u16 offload_trigger = 0;
+-
+-	if (index > 2)
+-		return -EINVAL;
+-
+-	return qca808x_led_parse_netdev(phydev, rules, &offload_trigger);
+-}
+-
+-static int qca808x_led_hw_control_set(struct phy_device *phydev, u8 index,
+-				      unsigned long rules)
+-{
+-	u16 reg, offload_trigger = 0;
+-	int ret;
+-
+-	if (index > 2)
+-		return -EINVAL;
+-
+-	reg = QCA808X_MMD7_LED_CTRL(index);
+-
+-	ret = qca808x_led_parse_netdev(phydev, rules, &offload_trigger);
+-	if (ret)
+-		return ret;
+-
+-	ret = qca808x_led_hw_control_enable(phydev, index);
+-	if (ret)
+-		return ret;
+-
+-	return phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
+-			      QCA808X_LED_PATTERN_MASK,
+-			      offload_trigger);
+-}
+-
+-static bool qca808x_led_hw_control_status(struct phy_device *phydev, u8 index)
+-{
+-	u16 reg;
+-	int val;
+-
+-	if (index > 2)
+-		return false;
+-
+-	reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
+-
+-	val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
+-
+-	return !(val & QCA808X_LED_FORCE_EN);
+-}
+-
+-static int qca808x_led_hw_control_get(struct phy_device *phydev, u8 index,
+-				      unsigned long *rules)
+-{
+-	u16 reg;
+-	int val;
+-
+-	if (index > 2)
+-		return -EINVAL;
+-
+-	/* Check if we have hw control enabled */
+-	if (qca808x_led_hw_control_status(phydev, index))
+-		return -EINVAL;
+-
+-	reg = QCA808X_MMD7_LED_CTRL(index);
+-
+-	val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
+-	if (val & QCA808X_LED_TX_BLINK)
+-		set_bit(TRIGGER_NETDEV_TX, rules);
+-	if (val & QCA808X_LED_RX_BLINK)
+-		set_bit(TRIGGER_NETDEV_RX, rules);
+-	if (val & QCA808X_LED_SPEED10_ON)
+-		set_bit(TRIGGER_NETDEV_LINK_10, rules);
+-	if (val & QCA808X_LED_SPEED100_ON)
+-		set_bit(TRIGGER_NETDEV_LINK_100, rules);
+-	if (val & QCA808X_LED_SPEED1000_ON)
+-		set_bit(TRIGGER_NETDEV_LINK_1000, rules);
+-	if (val & QCA808X_LED_SPEED2500_ON)
+-		set_bit(TRIGGER_NETDEV_LINK_2500, rules);
+-	if (val & QCA808X_LED_HALF_DUPLEX_ON)
+-		set_bit(TRIGGER_NETDEV_HALF_DUPLEX, rules);
+-	if (val & QCA808X_LED_FULL_DUPLEX_ON)
+-		set_bit(TRIGGER_NETDEV_FULL_DUPLEX, rules);
+-
+-	return 0;
+-}
+-
+-static int qca808x_led_hw_control_reset(struct phy_device *phydev, u8 index)
+-{
+-	u16 reg;
+-
+-	if (index > 2)
+-		return -EINVAL;
+-
+-	reg = QCA808X_MMD7_LED_CTRL(index);
+-
+-	return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg,
+-				  QCA808X_LED_PATTERN_MASK);
+-}
+-
+-static int qca808x_led_brightness_set(struct phy_device *phydev,
+-				      u8 index, enum led_brightness value)
+-{
+-	u16 reg;
+-	int ret;
+-
+-	if (index > 2)
+-		return -EINVAL;
+-
+-	if (!value) {
+-		ret = qca808x_led_hw_control_reset(phydev, index);
+-		if (ret)
+-			return ret;
+-	}
+-
+-	reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
+-
+-	return phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
+-			      QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_MODE_MASK,
+-			      QCA808X_LED_FORCE_EN | value ? QCA808X_LED_FORCE_ON :
+-							     QCA808X_LED_FORCE_OFF);
+-}
+-
+-static int qca808x_led_blink_set(struct phy_device *phydev, u8 index,
+-				 unsigned long *delay_on,
+-				 unsigned long *delay_off)
+-{
+-	int ret;
+-	u16 reg;
+-
+-	if (index > 2)
+-		return -EINVAL;
+-
+-	reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
+-
+-	/* Set blink to 50% off, 50% on at 4Hz by default */
+-	ret = phy_modify_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_LED_GLOBAL,
+-			     QCA808X_LED_BLINK_FREQ_MASK | QCA808X_LED_BLINK_DUTY_MASK,
+-			     QCA808X_LED_BLINK_FREQ_4HZ | QCA808X_LED_BLINK_DUTY_50_50);
+-	if (ret)
+-		return ret;
+-
+-	/* We use BLINK_1 for normal blinking */
+-	ret = phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
+-			     QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_MODE_MASK,
+-			     QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_BLINK_1);
+-	if (ret)
+-		return ret;
+-
+-	/* We set blink to 4Hz, aka 250ms */
+-	*delay_on = 250 / 2;
+-	*delay_off = 250 / 2;
+-
+-	return 0;
+-}
+-
+-static int qca808x_led_polarity_set(struct phy_device *phydev, int index,
+-				    unsigned long modes)
+-{
+-	struct at803x_priv *priv = phydev->priv;
+-	bool active_low = false;
+-	u32 mode;
+-
+-	for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) {
+-		switch (mode) {
+-		case PHY_LED_ACTIVE_LOW:
+-			active_low = true;
+-			break;
+-		default:
+-			return -EINVAL;
+-		}
+-	}
+-
+-	/* PHY polarity is global and can't be set per LED.
+-	 * To detect this, check if last requested polarity mode
+-	 * match the new one.
+-	 */
+-	if (priv->led_polarity_mode >= 0 &&
+-	    priv->led_polarity_mode != active_low) {
+-		phydev_err(phydev, "PHY polarity is global. Mismatched polarity on different LED\n");
+-		return -EINVAL;
+-	}
+-
+-	/* Save the last PHY polarity mode */
+-	priv->led_polarity_mode = active_low;
+-
+-	return phy_modify_mmd(phydev, MDIO_MMD_AN,
+-			      QCA808X_MMD7_LED_POLARITY_CTRL,
+-			      QCA808X_LED_ACTIVE_HIGH,
+-			      active_low ? 0 : QCA808X_LED_ACTIVE_HIGH);
+-}
+-
+-static struct phy_driver at803x_driver[] = {
+-{
+-	/* Qualcomm Atheros AR8035 */
+-	PHY_ID_MATCH_EXACT(ATH8035_PHY_ID),
+-	.name			= "Qualcomm Atheros AR8035",
+-	.flags			= PHY_POLL_CABLE_TEST,
+-	.probe			= at8035_probe,
+-	.config_aneg		= at803x_config_aneg,
+-	.config_init		= at803x_config_init,
+-	.soft_reset		= genphy_soft_reset,
+-	.set_wol		= at803x_set_wol,
+-	.get_wol		= at803x_get_wol,
+-	.suspend		= at803x_suspend,
+-	.resume			= at803x_resume,
+-	/* PHY_GBIT_FEATURES */
+-	.read_status		= at803x_read_status,
+-	.config_intr		= at803x_config_intr,
+-	.handle_interrupt	= at803x_handle_interrupt,
+-	.get_tunable		= at803x_get_tunable,
+-	.set_tunable		= at803x_set_tunable,
+-	.cable_test_start	= at8031_cable_test_start,
+-	.cable_test_get_status	= at8031_cable_test_get_status,
+-}, {
+-	/* Qualcomm Atheros AR8030 */
+-	.phy_id			= ATH8030_PHY_ID,
+-	.name			= "Qualcomm Atheros AR8030",
+-	.phy_id_mask		= AT8030_PHY_ID_MASK,
+-	.probe			= at8035_probe,
+-	.config_init		= at803x_config_init,
+-	.link_change_notify	= at803x_link_change_notify,
+-	.set_wol		= at803x_set_wol,
+-	.get_wol		= at803x_get_wol,
+-	.suspend		= at803x_suspend,
+-	.resume			= at803x_resume,
+-	/* PHY_BASIC_FEATURES */
+-	.config_intr		= at803x_config_intr,
+-	.handle_interrupt	= at803x_handle_interrupt,
+-}, {
+-	/* Qualcomm Atheros AR8031/AR8033 */
+-	PHY_ID_MATCH_EXACT(ATH8031_PHY_ID),
+-	.name			= "Qualcomm Atheros AR8031/AR8033",
+-	.flags			= PHY_POLL_CABLE_TEST,
+-	.probe			= at8031_probe,
+-	.config_init		= at8031_config_init,
+-	.config_aneg		= at803x_config_aneg,
+-	.soft_reset		= genphy_soft_reset,
+-	.set_wol		= at8031_set_wol,
+-	.get_wol		= at803x_get_wol,
+-	.suspend		= at803x_suspend,
+-	.resume			= at803x_resume,
+-	.read_page		= at803x_read_page,
+-	.write_page		= at803x_write_page,
+-	.get_features		= at803x_get_features,
+-	.read_status		= at8031_read_status,
+-	.config_intr		= at8031_config_intr,
+-	.handle_interrupt	= at803x_handle_interrupt,
+-	.get_tunable		= at803x_get_tunable,
+-	.set_tunable		= at803x_set_tunable,
+-	.cable_test_start	= at8031_cable_test_start,
+-	.cable_test_get_status	= at8031_cable_test_get_status,
+-}, {
+-	/* Qualcomm Atheros AR8032 */
+-	PHY_ID_MATCH_EXACT(ATH8032_PHY_ID),
+-	.name			= "Qualcomm Atheros AR8032",
+-	.probe			= at803x_probe,
+-	.flags			= PHY_POLL_CABLE_TEST,
+-	.config_init		= at803x_config_init,
+-	.link_change_notify	= at803x_link_change_notify,
+-	.suspend		= at803x_suspend,
+-	.resume			= at803x_resume,
+-	/* PHY_BASIC_FEATURES */
+-	.config_intr		= at803x_config_intr,
+-	.handle_interrupt	= at803x_handle_interrupt,
+-	.cable_test_start	= at803x_cable_test_start,
+-	.cable_test_get_status	= at8032_cable_test_get_status,
+-}, {
+-	/* ATHEROS AR9331 */
+-	PHY_ID_MATCH_EXACT(ATH9331_PHY_ID),
+-	.name			= "Qualcomm Atheros AR9331 built-in PHY",
+-	.probe			= at803x_probe,
+-	.suspend		= at803x_suspend,
+-	.resume			= at803x_resume,
+-	.flags			= PHY_POLL_CABLE_TEST,
+-	/* PHY_BASIC_FEATURES */
+-	.config_intr		= at803x_config_intr,
+-	.handle_interrupt	= at803x_handle_interrupt,
+-	.cable_test_start	= at803x_cable_test_start,
+-	.cable_test_get_status	= at8032_cable_test_get_status,
+-	.read_status		= at803x_read_status,
+-	.soft_reset		= genphy_soft_reset,
+-	.config_aneg		= at803x_config_aneg,
+-}, {
+-	/* Qualcomm Atheros QCA9561 */
+-	PHY_ID_MATCH_EXACT(QCA9561_PHY_ID),
+-	.name			= "Qualcomm Atheros QCA9561 built-in PHY",
+-	.probe			= at803x_probe,
+-	.suspend		= at803x_suspend,
+-	.resume			= at803x_resume,
+-	.flags			= PHY_POLL_CABLE_TEST,
+-	/* PHY_BASIC_FEATURES */
+-	.config_intr		= at803x_config_intr,
+-	.handle_interrupt	= at803x_handle_interrupt,
+-	.cable_test_start	= at803x_cable_test_start,
+-	.cable_test_get_status	= at8032_cable_test_get_status,
+-	.read_status		= at803x_read_status,
+-	.soft_reset		= genphy_soft_reset,
+-	.config_aneg		= at803x_config_aneg,
+-}, {
+-	/* QCA8337 */
+-	.phy_id			= QCA8337_PHY_ID,
+-	.phy_id_mask		= QCA8K_PHY_ID_MASK,
+-	.name			= "Qualcomm Atheros 8337 internal PHY",
+-	/* PHY_GBIT_FEATURES */
+-	.probe			= at803x_probe,
+-	.flags			= PHY_IS_INTERNAL,
+-	.config_init		= qca83xx_config_init,
+-	.soft_reset		= genphy_soft_reset,
+-	.get_sset_count		= qca83xx_get_sset_count,
+-	.get_strings		= qca83xx_get_strings,
+-	.get_stats		= qca83xx_get_stats,
+-	.suspend		= qca8337_suspend,
+-	.resume			= qca83xx_resume,
+-}, {
+-	/* QCA8327-A from switch QCA8327-AL1A */
+-	.phy_id			= QCA8327_A_PHY_ID,
+-	.phy_id_mask		= QCA8K_PHY_ID_MASK,
+-	.name			= "Qualcomm Atheros 8327-A internal PHY",
+-	/* PHY_GBIT_FEATURES */
+-	.link_change_notify	= qca83xx_link_change_notify,
+-	.probe			= at803x_probe,
+-	.flags			= PHY_IS_INTERNAL,
+-	.config_init		= qca8327_config_init,
+-	.soft_reset		= genphy_soft_reset,
+-	.get_sset_count		= qca83xx_get_sset_count,
+-	.get_strings		= qca83xx_get_strings,
+-	.get_stats		= qca83xx_get_stats,
+-	.suspend		= qca8327_suspend,
+-	.resume			= qca83xx_resume,
+-}, {
+-	/* QCA8327-B from switch QCA8327-BL1A */
+-	.phy_id			= QCA8327_B_PHY_ID,
+-	.phy_id_mask		= QCA8K_PHY_ID_MASK,
+-	.name			= "Qualcomm Atheros 8327-B internal PHY",
+-	/* PHY_GBIT_FEATURES */
+-	.link_change_notify	= qca83xx_link_change_notify,
+-	.probe			= at803x_probe,
+-	.flags			= PHY_IS_INTERNAL,
+-	.config_init		= qca8327_config_init,
+-	.soft_reset		= genphy_soft_reset,
+-	.get_sset_count		= qca83xx_get_sset_count,
+-	.get_strings		= qca83xx_get_strings,
+-	.get_stats		= qca83xx_get_stats,
+-	.suspend		= qca8327_suspend,
+-	.resume			= qca83xx_resume,
+-}, {
+-	/* Qualcomm QCA8081 */
+-	PHY_ID_MATCH_EXACT(QCA8081_PHY_ID),
+-	.name			= "Qualcomm QCA8081",
+-	.flags			= PHY_POLL_CABLE_TEST,
+-	.probe			= at803x_probe,
+-	.config_intr		= at803x_config_intr,
+-	.handle_interrupt	= at803x_handle_interrupt,
+-	.get_tunable		= at803x_get_tunable,
+-	.set_tunable		= at803x_set_tunable,
+-	.set_wol		= at803x_set_wol,
+-	.get_wol		= at803x_get_wol,
+-	.get_features		= qca808x_get_features,
+-	.config_aneg		= qca808x_config_aneg,
+-	.suspend		= genphy_suspend,
+-	.resume			= genphy_resume,
+-	.read_status		= qca808x_read_status,
+-	.config_init		= qca808x_config_init,
+-	.soft_reset		= qca808x_soft_reset,
+-	.cable_test_start	= qca808x_cable_test_start,
+-	.cable_test_get_status	= qca808x_cable_test_get_status,
+-	.link_change_notify	= qca808x_link_change_notify,
+-	.led_brightness_set	= qca808x_led_brightness_set,
+-	.led_blink_set		= qca808x_led_blink_set,
+-	.led_hw_is_supported	= qca808x_led_hw_is_supported,
+-	.led_hw_control_set	= qca808x_led_hw_control_set,
+-	.led_hw_control_get	= qca808x_led_hw_control_get,
+-	.led_polarity_set	= qca808x_led_polarity_set,
+-}, };
+-
+-module_phy_driver(at803x_driver);
+-
+-static struct mdio_device_id __maybe_unused atheros_tbl[] = {
+-	{ ATH8030_PHY_ID, AT8030_PHY_ID_MASK },
+-	{ PHY_ID_MATCH_EXACT(ATH8031_PHY_ID) },
+-	{ PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) },
+-	{ PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) },
+-	{ PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) },
+-	{ PHY_ID_MATCH_EXACT(QCA8337_PHY_ID) },
+-	{ PHY_ID_MATCH_EXACT(QCA8327_A_PHY_ID) },
+-	{ PHY_ID_MATCH_EXACT(QCA8327_B_PHY_ID) },
+-	{ PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) },
+-	{ PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) },
+-	{ }
+-};
+-
+-MODULE_DEVICE_TABLE(mdio, atheros_tbl);
+--- /dev/null
++++ b/drivers/net/phy/qcom/at803x.c
+@@ -0,0 +1,2759 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * drivers/net/phy/at803x.c
++ *
++ * Driver for Qualcomm Atheros AR803x PHY
++ *
++ * Author: Matus Ujhelyi <ujhelyi.m@gmail.com>
++ */
++
++#include <linux/phy.h>
++#include <linux/module.h>
++#include <linux/string.h>
++#include <linux/netdevice.h>
++#include <linux/etherdevice.h>
++#include <linux/ethtool_netlink.h>
++#include <linux/bitfield.h>
++#include <linux/regulator/of_regulator.h>
++#include <linux/regulator/driver.h>
++#include <linux/regulator/consumer.h>
++#include <linux/of.h>
++#include <linux/phylink.h>
++#include <linux/sfp.h>
++#include <dt-bindings/net/qca-ar803x.h>
++
++#define AT803X_SPECIFIC_FUNCTION_CONTROL	0x10
++#define AT803X_SFC_ASSERT_CRS			BIT(11)
++#define AT803X_SFC_FORCE_LINK			BIT(10)
++#define AT803X_SFC_MDI_CROSSOVER_MODE_M		GENMASK(6, 5)
++#define AT803X_SFC_AUTOMATIC_CROSSOVER		0x3
++#define AT803X_SFC_MANUAL_MDIX			0x1
++#define AT803X_SFC_MANUAL_MDI			0x0
++#define AT803X_SFC_SQE_TEST			BIT(2)
++#define AT803X_SFC_POLARITY_REVERSAL		BIT(1)
++#define AT803X_SFC_DISABLE_JABBER		BIT(0)
++
++#define AT803X_SPECIFIC_STATUS			0x11
++#define AT803X_SS_SPEED_MASK			GENMASK(15, 14)
++#define AT803X_SS_SPEED_1000			2
++#define AT803X_SS_SPEED_100			1
++#define AT803X_SS_SPEED_10			0
++#define AT803X_SS_DUPLEX			BIT(13)
++#define AT803X_SS_SPEED_DUPLEX_RESOLVED		BIT(11)
++#define AT803X_SS_MDIX				BIT(6)
++
++#define QCA808X_SS_SPEED_MASK			GENMASK(9, 7)
++#define QCA808X_SS_SPEED_2500			4
++
++#define AT803X_INTR_ENABLE			0x12
++#define AT803X_INTR_ENABLE_AUTONEG_ERR		BIT(15)
++#define AT803X_INTR_ENABLE_SPEED_CHANGED	BIT(14)
++#define AT803X_INTR_ENABLE_DUPLEX_CHANGED	BIT(13)
++#define AT803X_INTR_ENABLE_PAGE_RECEIVED	BIT(12)
++#define AT803X_INTR_ENABLE_LINK_FAIL		BIT(11)
++#define AT803X_INTR_ENABLE_LINK_SUCCESS		BIT(10)
++#define AT803X_INTR_ENABLE_LINK_FAIL_BX		BIT(8)
++#define AT803X_INTR_ENABLE_LINK_SUCCESS_BX	BIT(7)
++#define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE	BIT(5)
++#define AT803X_INTR_ENABLE_POLARITY_CHANGED	BIT(1)
++#define AT803X_INTR_ENABLE_WOL			BIT(0)
++
++#define AT803X_INTR_STATUS			0x13
++
++#define AT803X_SMART_SPEED			0x14
++#define AT803X_SMART_SPEED_ENABLE		BIT(5)
++#define AT803X_SMART_SPEED_RETRY_LIMIT_MASK	GENMASK(4, 2)
++#define AT803X_SMART_SPEED_BYPASS_TIMER		BIT(1)
++#define AT803X_CDT				0x16
++#define AT803X_CDT_MDI_PAIR_MASK		GENMASK(9, 8)
++#define AT803X_CDT_ENABLE_TEST			BIT(0)
++#define AT803X_CDT_STATUS			0x1c
++#define AT803X_CDT_STATUS_STAT_NORMAL		0
++#define AT803X_CDT_STATUS_STAT_SHORT		1
++#define AT803X_CDT_STATUS_STAT_OPEN		2
++#define AT803X_CDT_STATUS_STAT_FAIL		3
++#define AT803X_CDT_STATUS_STAT_MASK		GENMASK(9, 8)
++#define AT803X_CDT_STATUS_DELTA_TIME_MASK	GENMASK(7, 0)
++#define AT803X_LED_CONTROL			0x18
++
++#define AT803X_PHY_MMD3_WOL_CTRL		0x8012
++#define AT803X_WOL_EN				BIT(5)
++#define AT803X_LOC_MAC_ADDR_0_15_OFFSET		0x804C
++#define AT803X_LOC_MAC_ADDR_16_31_OFFSET	0x804B
++#define AT803X_LOC_MAC_ADDR_32_47_OFFSET	0x804A
++#define AT803X_REG_CHIP_CONFIG			0x1f
++#define AT803X_BT_BX_REG_SEL			0x8000
++
++#define AT803X_DEBUG_ADDR			0x1D
++#define AT803X_DEBUG_DATA			0x1E
++
++#define AT803X_MODE_CFG_MASK			0x0F
++#define AT803X_MODE_CFG_BASET_RGMII		0x00
++#define AT803X_MODE_CFG_BASET_SGMII		0x01
++#define AT803X_MODE_CFG_BX1000_RGMII_50OHM	0x02
++#define AT803X_MODE_CFG_BX1000_RGMII_75OHM	0x03
++#define AT803X_MODE_CFG_BX1000_CONV_50OHM	0x04
++#define AT803X_MODE_CFG_BX1000_CONV_75OHM	0x05
++#define AT803X_MODE_CFG_FX100_RGMII_50OHM	0x06
++#define AT803X_MODE_CFG_FX100_CONV_50OHM	0x07
++#define AT803X_MODE_CFG_RGMII_AUTO_MDET		0x0B
++#define AT803X_MODE_CFG_FX100_RGMII_75OHM	0x0E
++#define AT803X_MODE_CFG_FX100_CONV_75OHM	0x0F
++
++#define AT803X_PSSR				0x11	/*PHY-Specific Status Register*/
++#define AT803X_PSSR_MR_AN_COMPLETE		0x0200
++
++#define AT803X_DEBUG_ANALOG_TEST_CTRL		0x00
++#define QCA8327_DEBUG_MANU_CTRL_EN		BIT(2)
++#define QCA8337_DEBUG_MANU_CTRL_EN		GENMASK(3, 2)
++#define AT803X_DEBUG_RX_CLK_DLY_EN		BIT(15)
++
++#define AT803X_DEBUG_SYSTEM_CTRL_MODE		0x05
++#define AT803X_DEBUG_TX_CLK_DLY_EN		BIT(8)
++
++#define AT803X_DEBUG_REG_HIB_CTRL		0x0b
++#define   AT803X_DEBUG_HIB_CTRL_SEL_RST_80U	BIT(10)
++#define   AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE	BIT(13)
++#define   AT803X_DEBUG_HIB_CTRL_PS_HIB_EN	BIT(15)
++
++#define AT803X_DEBUG_REG_3C			0x3C
++
++#define AT803X_DEBUG_REG_GREEN			0x3D
++#define   AT803X_DEBUG_GATE_CLK_IN1000		BIT(6)
++
++#define AT803X_DEBUG_REG_1F			0x1F
++#define AT803X_DEBUG_PLL_ON			BIT(2)
++#define AT803X_DEBUG_RGMII_1V8			BIT(3)
++
++#define MDIO_AZ_DEBUG				0x800D
++
++/* AT803x supports either the XTAL input pad, an internal PLL or the
++ * DSP as clock reference for the clock output pad. The XTAL reference
++ * is only used for 25 MHz output, all other frequencies need the PLL.
++ * The DSP as a clock reference is used in synchronous ethernet
++ * applications.
++ *
++ * By default the PLL is only enabled if there is a link. Otherwise
++ * the PHY will go into low power state and disabled the PLL. You can
++ * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always
++ * enabled.
++ */
++#define AT803X_MMD7_CLK25M			0x8016
++#define AT803X_CLK_OUT_MASK			GENMASK(4, 2)
++#define AT803X_CLK_OUT_25MHZ_XTAL		0
++#define AT803X_CLK_OUT_25MHZ_DSP		1
++#define AT803X_CLK_OUT_50MHZ_PLL		2
++#define AT803X_CLK_OUT_50MHZ_DSP		3
++#define AT803X_CLK_OUT_62_5MHZ_PLL		4
++#define AT803X_CLK_OUT_62_5MHZ_DSP		5
++#define AT803X_CLK_OUT_125MHZ_PLL		6
++#define AT803X_CLK_OUT_125MHZ_DSP		7
++
++/* The AR8035 has another mask which is compatible with the AR8031/AR8033 mask
++ * but doesn't support choosing between XTAL/PLL and DSP.
++ */
++#define AT8035_CLK_OUT_MASK			GENMASK(4, 3)
++
++#define AT803X_CLK_OUT_STRENGTH_MASK		GENMASK(8, 7)
++#define AT803X_CLK_OUT_STRENGTH_FULL		0
++#define AT803X_CLK_OUT_STRENGTH_HALF		1
++#define AT803X_CLK_OUT_STRENGTH_QUARTER		2
++
++#define AT803X_DEFAULT_DOWNSHIFT		5
++#define AT803X_MIN_DOWNSHIFT			2
++#define AT803X_MAX_DOWNSHIFT			9
++
++#define AT803X_MMD3_SMARTEEE_CTL1		0x805b
++#define AT803X_MMD3_SMARTEEE_CTL2		0x805c
++#define AT803X_MMD3_SMARTEEE_CTL3		0x805d
++#define AT803X_MMD3_SMARTEEE_CTL3_LPI_EN	BIT(8)
++
++#define ATH9331_PHY_ID				0x004dd041
++#define ATH8030_PHY_ID				0x004dd076
++#define ATH8031_PHY_ID				0x004dd074
++#define ATH8032_PHY_ID				0x004dd023
++#define ATH8035_PHY_ID				0x004dd072
++#define AT8030_PHY_ID_MASK			0xffffffef
++
++#define QCA8081_PHY_ID				0x004dd101
++
++#define QCA8327_A_PHY_ID			0x004dd033
++#define QCA8327_B_PHY_ID			0x004dd034
++#define QCA8337_PHY_ID				0x004dd036
++#define QCA9561_PHY_ID				0x004dd042
++#define QCA8K_PHY_ID_MASK			0xffffffff
++
++#define QCA8K_DEVFLAGS_REVISION_MASK		GENMASK(2, 0)
++
++#define AT803X_PAGE_FIBER			0
++#define AT803X_PAGE_COPPER			1
++
++/* don't turn off internal PLL */
++#define AT803X_KEEP_PLL_ENABLED			BIT(0)
++#define AT803X_DISABLE_SMARTEEE			BIT(1)
++
++/* disable hibernation mode */
++#define AT803X_DISABLE_HIBERNATION_MODE		BIT(2)
++
++/* ADC threshold */
++#define QCA808X_PHY_DEBUG_ADC_THRESHOLD		0x2c80
++#define QCA808X_ADC_THRESHOLD_MASK		GENMASK(7, 0)
++#define QCA808X_ADC_THRESHOLD_80MV		0
++#define QCA808X_ADC_THRESHOLD_100MV		0xf0
++#define QCA808X_ADC_THRESHOLD_200MV		0x0f
++#define QCA808X_ADC_THRESHOLD_300MV		0xff
++
++/* CLD control */
++#define QCA808X_PHY_MMD3_ADDR_CLD_CTRL7		0x8007
++#define QCA808X_8023AZ_AFE_CTRL_MASK		GENMASK(8, 4)
++#define QCA808X_8023AZ_AFE_EN			0x90
++
++/* AZ control */
++#define QCA808X_PHY_MMD3_AZ_TRAINING_CTRL	0x8008
++#define QCA808X_MMD3_AZ_TRAINING_VAL		0x1c32
++
++#define QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB	0x8014
++#define QCA808X_MSE_THRESHOLD_20DB_VALUE	0x529
++
++#define QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB	0x800E
++#define QCA808X_MSE_THRESHOLD_17DB_VALUE	0x341
++
++#define QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB	0x801E
++#define QCA808X_MSE_THRESHOLD_27DB_VALUE	0x419
++
++#define QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB	0x8020
++#define QCA808X_MSE_THRESHOLD_28DB_VALUE	0x341
++
++#define QCA808X_PHY_MMD7_TOP_OPTION1		0x901c
++#define QCA808X_TOP_OPTION1_DATA		0x0
++
++#define QCA808X_PHY_MMD3_DEBUG_1		0xa100
++#define QCA808X_MMD3_DEBUG_1_VALUE		0x9203
++#define QCA808X_PHY_MMD3_DEBUG_2		0xa101
++#define QCA808X_MMD3_DEBUG_2_VALUE		0x48ad
++#define QCA808X_PHY_MMD3_DEBUG_3		0xa103
++#define QCA808X_MMD3_DEBUG_3_VALUE		0x1698
++#define QCA808X_PHY_MMD3_DEBUG_4		0xa105
++#define QCA808X_MMD3_DEBUG_4_VALUE		0x8001
++#define QCA808X_PHY_MMD3_DEBUG_5		0xa106
++#define QCA808X_MMD3_DEBUG_5_VALUE		0x1111
++#define QCA808X_PHY_MMD3_DEBUG_6		0xa011
++#define QCA808X_MMD3_DEBUG_6_VALUE		0x5f85
++
++/* master/slave seed config */
++#define QCA808X_PHY_DEBUG_LOCAL_SEED		9
++#define QCA808X_MASTER_SLAVE_SEED_ENABLE	BIT(1)
++#define QCA808X_MASTER_SLAVE_SEED_CFG		GENMASK(12, 2)
++#define QCA808X_MASTER_SLAVE_SEED_RANGE		0x32
++
++/* Hibernation yields lower power consumpiton in contrast with normal operation mode.
++ * when the copper cable is unplugged, the PHY enters into hibernation mode in about 10s.
++ */
++#define QCA808X_DBG_AN_TEST			0xb
++#define QCA808X_HIBERNATION_EN			BIT(15)
++
++#define QCA808X_CDT_ENABLE_TEST			BIT(15)
++#define QCA808X_CDT_INTER_CHECK_DIS		BIT(13)
++#define QCA808X_CDT_STATUS			BIT(11)
++#define QCA808X_CDT_LENGTH_UNIT			BIT(10)
++
++#define QCA808X_MMD3_CDT_STATUS			0x8064
++#define QCA808X_MMD3_CDT_DIAG_PAIR_A		0x8065
++#define QCA808X_MMD3_CDT_DIAG_PAIR_B		0x8066
++#define QCA808X_MMD3_CDT_DIAG_PAIR_C		0x8067
++#define QCA808X_MMD3_CDT_DIAG_PAIR_D		0x8068
++#define QCA808X_CDT_DIAG_LENGTH_SAME_SHORT	GENMASK(15, 8)
++#define QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT	GENMASK(7, 0)
++
++#define QCA808X_CDT_CODE_PAIR_A			GENMASK(15, 12)
++#define QCA808X_CDT_CODE_PAIR_B			GENMASK(11, 8)
++#define QCA808X_CDT_CODE_PAIR_C			GENMASK(7, 4)
++#define QCA808X_CDT_CODE_PAIR_D			GENMASK(3, 0)
++
++#define QCA808X_CDT_STATUS_STAT_TYPE		GENMASK(1, 0)
++#define QCA808X_CDT_STATUS_STAT_FAIL		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 0)
++#define QCA808X_CDT_STATUS_STAT_NORMAL		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 1)
++#define QCA808X_CDT_STATUS_STAT_SAME_OPEN	FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 2)
++#define QCA808X_CDT_STATUS_STAT_SAME_SHORT	FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 3)
++
++#define QCA808X_CDT_STATUS_STAT_MDI		GENMASK(3, 2)
++#define QCA808X_CDT_STATUS_STAT_MDI1		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 1)
++#define QCA808X_CDT_STATUS_STAT_MDI2		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 2)
++#define QCA808X_CDT_STATUS_STAT_MDI3		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 3)
++
++/* NORMAL are MDI with type set to 0 */
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL	QCA808X_CDT_STATUS_STAT_MDI1
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN		(QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
++									 QCA808X_CDT_STATUS_STAT_MDI1)
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT	(QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
++									 QCA808X_CDT_STATUS_STAT_MDI1)
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL	QCA808X_CDT_STATUS_STAT_MDI2
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN		(QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
++									 QCA808X_CDT_STATUS_STAT_MDI2)
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT	(QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
++									 QCA808X_CDT_STATUS_STAT_MDI2)
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL	QCA808X_CDT_STATUS_STAT_MDI3
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN		(QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
++									 QCA808X_CDT_STATUS_STAT_MDI3)
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT	(QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
++									 QCA808X_CDT_STATUS_STAT_MDI3)
++
++/* Added for reference of existence but should be handled by wait_for_completion already */
++#define QCA808X_CDT_STATUS_STAT_BUSY		(BIT(1) | BIT(3))
++
++#define QCA808X_MMD7_LED_GLOBAL			0x8073
++#define QCA808X_LED_BLINK_1			GENMASK(11, 6)
++#define QCA808X_LED_BLINK_2			GENMASK(5, 0)
++/* Values are the same for both BLINK_1 and BLINK_2 */
++#define QCA808X_LED_BLINK_FREQ_MASK		GENMASK(5, 3)
++#define QCA808X_LED_BLINK_FREQ_2HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x0)
++#define QCA808X_LED_BLINK_FREQ_4HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x1)
++#define QCA808X_LED_BLINK_FREQ_8HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x2)
++#define QCA808X_LED_BLINK_FREQ_16HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x3)
++#define QCA808X_LED_BLINK_FREQ_32HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x4)
++#define QCA808X_LED_BLINK_FREQ_64HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x5)
++#define QCA808X_LED_BLINK_FREQ_128HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x6)
++#define QCA808X_LED_BLINK_FREQ_256HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x7)
++#define QCA808X_LED_BLINK_DUTY_MASK		GENMASK(2, 0)
++#define QCA808X_LED_BLINK_DUTY_50_50		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x0)
++#define QCA808X_LED_BLINK_DUTY_75_25		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x1)
++#define QCA808X_LED_BLINK_DUTY_25_75		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x2)
++#define QCA808X_LED_BLINK_DUTY_33_67		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x3)
++#define QCA808X_LED_BLINK_DUTY_67_33		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x4)
++#define QCA808X_LED_BLINK_DUTY_17_83		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x5)
++#define QCA808X_LED_BLINK_DUTY_83_17		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x6)
++#define QCA808X_LED_BLINK_DUTY_8_92		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x7)
++
++#define QCA808X_MMD7_LED2_CTRL			0x8074
++#define QCA808X_MMD7_LED2_FORCE_CTRL		0x8075
++#define QCA808X_MMD7_LED1_CTRL			0x8076
++#define QCA808X_MMD7_LED1_FORCE_CTRL		0x8077
++#define QCA808X_MMD7_LED0_CTRL			0x8078
++#define QCA808X_MMD7_LED_CTRL(x)		(0x8078 - ((x) * 2))
++
++/* LED hw control pattern is the same for every LED */
++#define QCA808X_LED_PATTERN_MASK		GENMASK(15, 0)
++#define QCA808X_LED_SPEED2500_ON		BIT(15)
++#define QCA808X_LED_SPEED2500_BLINK		BIT(14)
++/* Follow blink trigger even if duplex or speed condition doesn't match */
++#define QCA808X_LED_BLINK_CHECK_BYPASS		BIT(13)
++#define QCA808X_LED_FULL_DUPLEX_ON		BIT(12)
++#define QCA808X_LED_HALF_DUPLEX_ON		BIT(11)
++#define QCA808X_LED_TX_BLINK			BIT(10)
++#define QCA808X_LED_RX_BLINK			BIT(9)
++#define QCA808X_LED_TX_ON_10MS			BIT(8)
++#define QCA808X_LED_RX_ON_10MS			BIT(7)
++#define QCA808X_LED_SPEED1000_ON		BIT(6)
++#define QCA808X_LED_SPEED100_ON			BIT(5)
++#define QCA808X_LED_SPEED10_ON			BIT(4)
++#define QCA808X_LED_COLLISION_BLINK		BIT(3)
++#define QCA808X_LED_SPEED1000_BLINK		BIT(2)
++#define QCA808X_LED_SPEED100_BLINK		BIT(1)
++#define QCA808X_LED_SPEED10_BLINK		BIT(0)
++
++#define QCA808X_MMD7_LED0_FORCE_CTRL		0x8079
++#define QCA808X_MMD7_LED_FORCE_CTRL(x)		(0x8079 - ((x) * 2))
++
++/* LED force ctrl is the same for every LED
++ * No documentation exist for this, not even internal one
++ * with NDA as QCOM gives only info about configuring
++ * hw control pattern rules and doesn't indicate any way
++ * to force the LED to specific mode.
++ * These define comes from reverse and testing and maybe
++ * lack of some info or some info are not entirely correct.
++ * For the basic LED control and hw control these finding
++ * are enough to support LED control in all the required APIs.
++ *
++ * On doing some comparison with implementation with qca807x,
++ * it was found that it's 1:1 equal to it and confirms all the
++ * reverse done. It was also found further specification with the
++ * force mode and the blink modes.
++ */
++#define QCA808X_LED_FORCE_EN			BIT(15)
++#define QCA808X_LED_FORCE_MODE_MASK		GENMASK(14, 13)
++#define QCA808X_LED_FORCE_BLINK_1		FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x3)
++#define QCA808X_LED_FORCE_BLINK_2		FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x2)
++#define QCA808X_LED_FORCE_ON			FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x1)
++#define QCA808X_LED_FORCE_OFF			FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x0)
++
++#define QCA808X_MMD7_LED_POLARITY_CTRL		0x901a
++/* QSDK sets by default 0x46 to this reg that sets BIT 6 for
++ * LED to active high. It's not clear what BIT 3 and BIT 4 does.
++ */
++#define QCA808X_LED_ACTIVE_HIGH			BIT(6)
++
++/* QCA808X 1G chip type */
++#define QCA808X_PHY_MMD7_CHIP_TYPE		0x901d
++#define QCA808X_PHY_CHIP_TYPE_1G		BIT(0)
++
++#define QCA8081_PHY_SERDES_MMD1_FIFO_CTRL	0x9072
++#define QCA8081_PHY_FIFO_RSTN			BIT(11)
++
++MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver");
++MODULE_AUTHOR("Matus Ujhelyi");
++MODULE_LICENSE("GPL");
++
++enum stat_access_type {
++	PHY,
++	MMD
++};
++
++struct at803x_hw_stat {
++	const char *string;
++	u8 reg;
++	u32 mask;
++	enum stat_access_type access_type;
++};
++
++static struct at803x_hw_stat qca83xx_hw_stats[] = {
++	{ "phy_idle_errors", 0xa, GENMASK(7, 0), PHY},
++	{ "phy_receive_errors", 0x15, GENMASK(15, 0), PHY},
++	{ "eee_wake_errors", 0x16, GENMASK(15, 0), MMD},
++};
++
++struct at803x_ss_mask {
++	u16 speed_mask;
++	u8 speed_shift;
++};
++
++struct at803x_priv {
++	int flags;
++	u16 clk_25m_reg;
++	u16 clk_25m_mask;
++	u8 smarteee_lpi_tw_1g;
++	u8 smarteee_lpi_tw_100m;
++	bool is_fiber;
++	bool is_1000basex;
++	struct regulator_dev *vddio_rdev;
++	struct regulator_dev *vddh_rdev;
++	u64 stats[ARRAY_SIZE(qca83xx_hw_stats)];
++	int led_polarity_mode;
++};
++
++struct at803x_context {
++	u16 bmcr;
++	u16 advertise;
++	u16 control1000;
++	u16 int_enable;
++	u16 smart_speed;
++	u16 led_control;
++};
++
++static int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data)
++{
++	int ret;
++
++	ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
++	if (ret < 0)
++		return ret;
++
++	return phy_write(phydev, AT803X_DEBUG_DATA, data);
++}
++
++static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg)
++{
++	int ret;
++
++	ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
++	if (ret < 0)
++		return ret;
++
++	return phy_read(phydev, AT803X_DEBUG_DATA);
++}
++
++static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
++				 u16 clear, u16 set)
++{
++	u16 val;
++	int ret;
++
++	ret = at803x_debug_reg_read(phydev, reg);
++	if (ret < 0)
++		return ret;
++
++	val = ret & 0xffff;
++	val &= ~clear;
++	val |= set;
++
++	return phy_write(phydev, AT803X_DEBUG_DATA, val);
++}
++
++static int at803x_write_page(struct phy_device *phydev, int page)
++{
++	int mask;
++	int set;
++
++	if (page == AT803X_PAGE_COPPER) {
++		set = AT803X_BT_BX_REG_SEL;
++		mask = 0;
++	} else {
++		set = 0;
++		mask = AT803X_BT_BX_REG_SEL;
++	}
++
++	return __phy_modify(phydev, AT803X_REG_CHIP_CONFIG, mask, set);
++}
++
++static int at803x_read_page(struct phy_device *phydev)
++{
++	int ccr = __phy_read(phydev, AT803X_REG_CHIP_CONFIG);
++
++	if (ccr < 0)
++		return ccr;
++
++	if (ccr & AT803X_BT_BX_REG_SEL)
++		return AT803X_PAGE_COPPER;
++
++	return AT803X_PAGE_FIBER;
++}
++
++static int at803x_enable_rx_delay(struct phy_device *phydev)
++{
++	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0,
++				     AT803X_DEBUG_RX_CLK_DLY_EN);
++}
++
++static int at803x_enable_tx_delay(struct phy_device *phydev)
++{
++	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0,
++				     AT803X_DEBUG_TX_CLK_DLY_EN);
++}
++
++static int at803x_disable_rx_delay(struct phy_device *phydev)
++{
++	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
++				     AT803X_DEBUG_RX_CLK_DLY_EN, 0);
++}
++
++static int at803x_disable_tx_delay(struct phy_device *phydev)
++{
++	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE,
++				     AT803X_DEBUG_TX_CLK_DLY_EN, 0);
++}
++
++/* save relevant PHY registers to private copy */
++static void at803x_context_save(struct phy_device *phydev,
++				struct at803x_context *context)
++{
++	context->bmcr = phy_read(phydev, MII_BMCR);
++	context->advertise = phy_read(phydev, MII_ADVERTISE);
++	context->control1000 = phy_read(phydev, MII_CTRL1000);
++	context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE);
++	context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED);
++	context->led_control = phy_read(phydev, AT803X_LED_CONTROL);
++}
++
++/* restore relevant PHY registers from private copy */
++static void at803x_context_restore(struct phy_device *phydev,
++				   const struct at803x_context *context)
++{
++	phy_write(phydev, MII_BMCR, context->bmcr);
++	phy_write(phydev, MII_ADVERTISE, context->advertise);
++	phy_write(phydev, MII_CTRL1000, context->control1000);
++	phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable);
++	phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed);
++	phy_write(phydev, AT803X_LED_CONTROL, context->led_control);
++}
++
++static int at803x_set_wol(struct phy_device *phydev,
++			  struct ethtool_wolinfo *wol)
++{
++	int ret, irq_enabled;
++
++	if (wol->wolopts & WAKE_MAGIC) {
++		struct net_device *ndev = phydev->attached_dev;
++		const u8 *mac;
++		unsigned int i;
++		static const unsigned int offsets[] = {
++			AT803X_LOC_MAC_ADDR_32_47_OFFSET,
++			AT803X_LOC_MAC_ADDR_16_31_OFFSET,
++			AT803X_LOC_MAC_ADDR_0_15_OFFSET,
++		};
++
++		if (!ndev)
++			return -ENODEV;
++
++		mac = (const u8 *)ndev->dev_addr;
++
++		if (!is_valid_ether_addr(mac))
++			return -EINVAL;
++
++		for (i = 0; i < 3; i++)
++			phy_write_mmd(phydev, MDIO_MMD_PCS, offsets[i],
++				      mac[(i * 2) + 1] | (mac[(i * 2)] << 8));
++
++		/* Enable WOL interrupt */
++		ret = phy_modify(phydev, AT803X_INTR_ENABLE, 0, AT803X_INTR_ENABLE_WOL);
++		if (ret)
++			return ret;
++	} else {
++		/* Disable WOL interrupt */
++		ret = phy_modify(phydev, AT803X_INTR_ENABLE, AT803X_INTR_ENABLE_WOL, 0);
++		if (ret)
++			return ret;
++	}
++
++	/* Clear WOL status */
++	ret = phy_read(phydev, AT803X_INTR_STATUS);
++	if (ret < 0)
++		return ret;
++
++	/* Check if there are other interrupts except for WOL triggered when PHY is
++	 * in interrupt mode, only the interrupts enabled by AT803X_INTR_ENABLE can
++	 * be passed up to the interrupt PIN.
++	 */
++	irq_enabled = phy_read(phydev, AT803X_INTR_ENABLE);
++	if (irq_enabled < 0)
++		return irq_enabled;
++
++	irq_enabled &= ~AT803X_INTR_ENABLE_WOL;
++	if (ret & irq_enabled && !phy_polling_mode(phydev))
++		phy_trigger_machine(phydev);
++
++	return 0;
++}
++
++static void at803x_get_wol(struct phy_device *phydev,
++			   struct ethtool_wolinfo *wol)
++{
++	int value;
++
++	wol->supported = WAKE_MAGIC;
++	wol->wolopts = 0;
++
++	value = phy_read(phydev, AT803X_INTR_ENABLE);
++	if (value < 0)
++		return;
++
++	if (value & AT803X_INTR_ENABLE_WOL)
++		wol->wolopts |= WAKE_MAGIC;
++}
++
++static int qca83xx_get_sset_count(struct phy_device *phydev)
++{
++	return ARRAY_SIZE(qca83xx_hw_stats);
++}
++
++static void qca83xx_get_strings(struct phy_device *phydev, u8 *data)
++{
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(qca83xx_hw_stats); i++) {
++		strscpy(data + i * ETH_GSTRING_LEN,
++			qca83xx_hw_stats[i].string, ETH_GSTRING_LEN);
++	}
++}
++
++static u64 qca83xx_get_stat(struct phy_device *phydev, int i)
++{
++	struct at803x_hw_stat stat = qca83xx_hw_stats[i];
++	struct at803x_priv *priv = phydev->priv;
++	int val;
++	u64 ret;
++
++	if (stat.access_type == MMD)
++		val = phy_read_mmd(phydev, MDIO_MMD_PCS, stat.reg);
++	else
++		val = phy_read(phydev, stat.reg);
++
++	if (val < 0) {
++		ret = U64_MAX;
++	} else {
++		val = val & stat.mask;
++		priv->stats[i] += val;
++		ret = priv->stats[i];
++	}
++
++	return ret;
++}
++
++static void qca83xx_get_stats(struct phy_device *phydev,
++			      struct ethtool_stats *stats, u64 *data)
++{
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(qca83xx_hw_stats); i++)
++		data[i] = qca83xx_get_stat(phydev, i);
++}
++
++static int at803x_suspend(struct phy_device *phydev)
++{
++	int value;
++	int wol_enabled;
++
++	value = phy_read(phydev, AT803X_INTR_ENABLE);
++	wol_enabled = value & AT803X_INTR_ENABLE_WOL;
++
++	if (wol_enabled)
++		value = BMCR_ISOLATE;
++	else
++		value = BMCR_PDOWN;
++
++	phy_modify(phydev, MII_BMCR, 0, value);
++
++	return 0;
++}
++
++static int at803x_resume(struct phy_device *phydev)
++{
++	return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0);
++}
++
++static int at803x_parse_dt(struct phy_device *phydev)
++{
++	struct device_node *node = phydev->mdio.dev.of_node;
++	struct at803x_priv *priv = phydev->priv;
++	u32 freq, strength, tw;
++	unsigned int sel;
++	int ret;
++
++	if (!IS_ENABLED(CONFIG_OF_MDIO))
++		return 0;
++
++	if (of_property_read_bool(node, "qca,disable-smarteee"))
++		priv->flags |= AT803X_DISABLE_SMARTEEE;
++
++	if (of_property_read_bool(node, "qca,disable-hibernation-mode"))
++		priv->flags |= AT803X_DISABLE_HIBERNATION_MODE;
++
++	if (!of_property_read_u32(node, "qca,smarteee-tw-us-1g", &tw)) {
++		if (!tw || tw > 255) {
++			phydev_err(phydev, "invalid qca,smarteee-tw-us-1g\n");
++			return -EINVAL;
++		}
++		priv->smarteee_lpi_tw_1g = tw;
++	}
++
++	if (!of_property_read_u32(node, "qca,smarteee-tw-us-100m", &tw)) {
++		if (!tw || tw > 255) {
++			phydev_err(phydev, "invalid qca,smarteee-tw-us-100m\n");
++			return -EINVAL;
++		}
++		priv->smarteee_lpi_tw_100m = tw;
++	}
++
++	ret = of_property_read_u32(node, "qca,clk-out-frequency", &freq);
++	if (!ret) {
++		switch (freq) {
++		case 25000000:
++			sel = AT803X_CLK_OUT_25MHZ_XTAL;
++			break;
++		case 50000000:
++			sel = AT803X_CLK_OUT_50MHZ_PLL;
++			break;
++		case 62500000:
++			sel = AT803X_CLK_OUT_62_5MHZ_PLL;
++			break;
++		case 125000000:
++			sel = AT803X_CLK_OUT_125MHZ_PLL;
++			break;
++		default:
++			phydev_err(phydev, "invalid qca,clk-out-frequency\n");
++			return -EINVAL;
++		}
++
++		priv->clk_25m_reg |= FIELD_PREP(AT803X_CLK_OUT_MASK, sel);
++		priv->clk_25m_mask |= AT803X_CLK_OUT_MASK;
++	}
++
++	ret = of_property_read_u32(node, "qca,clk-out-strength", &strength);
++	if (!ret) {
++		priv->clk_25m_mask |= AT803X_CLK_OUT_STRENGTH_MASK;
++		switch (strength) {
++		case AR803X_STRENGTH_FULL:
++			priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_FULL;
++			break;
++		case AR803X_STRENGTH_HALF:
++			priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_HALF;
++			break;
++		case AR803X_STRENGTH_QUARTER:
++			priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_QUARTER;
++			break;
++		default:
++			phydev_err(phydev, "invalid qca,clk-out-strength\n");
++			return -EINVAL;
++		}
++	}
++
++	return 0;
++}
++
++static int at803x_probe(struct phy_device *phydev)
++{
++	struct device *dev = &phydev->mdio.dev;
++	struct at803x_priv *priv;
++	int ret;
++
++	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
++	if (!priv)
++		return -ENOMEM;
++
++	/* Init LED polarity mode to -1 */
++	priv->led_polarity_mode = -1;
++
++	phydev->priv = priv;
++
++	ret = at803x_parse_dt(phydev);
++	if (ret)
++		return ret;
++
++	return 0;
++}
++
++static int at803x_get_features(struct phy_device *phydev)
++{
++	struct at803x_priv *priv = phydev->priv;
++	int err;
++
++	err = genphy_read_abilities(phydev);
++	if (err)
++		return err;
++
++	if (phydev->drv->phy_id != ATH8031_PHY_ID)
++		return 0;
++
++	/* AR8031/AR8033 have different status registers
++	 * for copper and fiber operation. However, the
++	 * extended status register is the same for both
++	 * operation modes.
++	 *
++	 * As a result of that, ESTATUS_1000_XFULL is set
++	 * to 1 even when operating in copper TP mode.
++	 *
++	 * Remove this mode from the supported link modes
++	 * when not operating in 1000BaseX mode.
++	 */
++	if (!priv->is_1000basex)
++		linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
++				   phydev->supported);
++
++	return 0;
++}
++
++static int at803x_smarteee_config(struct phy_device *phydev)
++{
++	struct at803x_priv *priv = phydev->priv;
++	u16 mask = 0, val = 0;
++	int ret;
++
++	if (priv->flags & AT803X_DISABLE_SMARTEEE)
++		return phy_modify_mmd(phydev, MDIO_MMD_PCS,
++				      AT803X_MMD3_SMARTEEE_CTL3,
++				      AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 0);
++
++	if (priv->smarteee_lpi_tw_1g) {
++		mask |= 0xff00;
++		val |= priv->smarteee_lpi_tw_1g << 8;
++	}
++	if (priv->smarteee_lpi_tw_100m) {
++		mask |= 0x00ff;
++		val |= priv->smarteee_lpi_tw_100m;
++	}
++	if (!mask)
++		return 0;
++
++	ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL1,
++			     mask, val);
++	if (ret)
++		return ret;
++
++	return phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL3,
++			      AT803X_MMD3_SMARTEEE_CTL3_LPI_EN,
++			      AT803X_MMD3_SMARTEEE_CTL3_LPI_EN);
++}
++
++static int at803x_clk_out_config(struct phy_device *phydev)
++{
++	struct at803x_priv *priv = phydev->priv;
++
++	if (!priv->clk_25m_mask)
++		return 0;
++
++	return phy_modify_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M,
++			      priv->clk_25m_mask, priv->clk_25m_reg);
++}
++
++static int at8031_pll_config(struct phy_device *phydev)
++{
++	struct at803x_priv *priv = phydev->priv;
++
++	/* The default after hardware reset is PLL OFF. After a soft reset, the
++	 * values are retained.
++	 */
++	if (priv->flags & AT803X_KEEP_PLL_ENABLED)
++		return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
++					     0, AT803X_DEBUG_PLL_ON);
++	else
++		return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
++					     AT803X_DEBUG_PLL_ON, 0);
++}
++
++static int at803x_hibernation_mode_config(struct phy_device *phydev)
++{
++	struct at803x_priv *priv = phydev->priv;
++
++	/* The default after hardware reset is hibernation mode enabled. After
++	 * software reset, the value is retained.
++	 */
++	if (!(priv->flags & AT803X_DISABLE_HIBERNATION_MODE))
++		return 0;
++
++	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL,
++					 AT803X_DEBUG_HIB_CTRL_PS_HIB_EN, 0);
++}
++
++static int at803x_config_init(struct phy_device *phydev)
++{
++	int ret;
++
++	/* The RX and TX delay default is:
++	 *   after HW reset: RX delay enabled and TX delay disabled
++	 *   after SW reset: RX delay enabled, while TX delay retains the
++	 *   value before reset.
++	 */
++	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
++	    phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
++		ret = at803x_enable_rx_delay(phydev);
++	else
++		ret = at803x_disable_rx_delay(phydev);
++	if (ret < 0)
++		return ret;
++
++	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
++	    phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
++		ret = at803x_enable_tx_delay(phydev);
++	else
++		ret = at803x_disable_tx_delay(phydev);
++	if (ret < 0)
++		return ret;
++
++	ret = at803x_smarteee_config(phydev);
++	if (ret < 0)
++		return ret;
++
++	ret = at803x_clk_out_config(phydev);
++	if (ret < 0)
++		return ret;
++
++	ret = at803x_hibernation_mode_config(phydev);
++	if (ret < 0)
++		return ret;
++
++	/* Ar803x extended next page bit is enabled by default. Cisco
++	 * multigig switches read this bit and attempt to negotiate 10Gbps
++	 * rates even if the next page bit is disabled. This is incorrect
++	 * behaviour but we still need to accommodate it. XNP is only needed
++	 * for 10Gbps support, so disable XNP.
++	 */
++	return phy_modify(phydev, MII_ADVERTISE, MDIO_AN_CTRL1_XNP, 0);
++}
++
++static int at803x_ack_interrupt(struct phy_device *phydev)
++{
++	int err;
++
++	err = phy_read(phydev, AT803X_INTR_STATUS);
++
++	return (err < 0) ? err : 0;
++}
++
++static int at803x_config_intr(struct phy_device *phydev)
++{
++	int err;
++	int value;
++
++	value = phy_read(phydev, AT803X_INTR_ENABLE);
++
++	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
++		/* Clear any pending interrupts */
++		err = at803x_ack_interrupt(phydev);
++		if (err)
++			return err;
++
++		value |= AT803X_INTR_ENABLE_AUTONEG_ERR;
++		value |= AT803X_INTR_ENABLE_SPEED_CHANGED;
++		value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED;
++		value |= AT803X_INTR_ENABLE_LINK_FAIL;
++		value |= AT803X_INTR_ENABLE_LINK_SUCCESS;
++
++		err = phy_write(phydev, AT803X_INTR_ENABLE, value);
++	} else {
++		err = phy_write(phydev, AT803X_INTR_ENABLE, 0);
++		if (err)
++			return err;
++
++		/* Clear any pending interrupts */
++		err = at803x_ack_interrupt(phydev);
++	}
++
++	return err;
++}
++
++static irqreturn_t at803x_handle_interrupt(struct phy_device *phydev)
++{
++	int irq_status, int_enabled;
++
++	irq_status = phy_read(phydev, AT803X_INTR_STATUS);
++	if (irq_status < 0) {
++		phy_error(phydev);
++		return IRQ_NONE;
++	}
++
++	/* Read the current enabled interrupts */
++	int_enabled = phy_read(phydev, AT803X_INTR_ENABLE);
++	if (int_enabled < 0) {
++		phy_error(phydev);
++		return IRQ_NONE;
++	}
++
++	/* See if this was one of our enabled interrupts */
++	if (!(irq_status & int_enabled))
++		return IRQ_NONE;
++
++	phy_trigger_machine(phydev);
++
++	return IRQ_HANDLED;
++}
++
++static void at803x_link_change_notify(struct phy_device *phydev)
++{
++	/*
++	 * Conduct a hardware reset for AT8030 every time a link loss is
++	 * signalled. This is necessary to circumvent a hardware bug that
++	 * occurs when the cable is unplugged while TX packets are pending
++	 * in the FIFO. In such cases, the FIFO enters an error mode it
++	 * cannot recover from by software.
++	 */
++	if (phydev->state == PHY_NOLINK && phydev->mdio.reset_gpio) {
++		struct at803x_context context;
++
++		at803x_context_save(phydev, &context);
++
++		phy_device_reset(phydev, 1);
++		usleep_range(1000, 2000);
++		phy_device_reset(phydev, 0);
++		usleep_range(1000, 2000);
++
++		at803x_context_restore(phydev, &context);
++
++		phydev_dbg(phydev, "%s(): phy was reset\n", __func__);
++	}
++}
++
++static int at803x_read_specific_status(struct phy_device *phydev,
++				       struct at803x_ss_mask ss_mask)
++{
++	int ss;
++
++	/* Read the AT8035 PHY-Specific Status register, which indicates the
++	 * speed and duplex that the PHY is actually using, irrespective of
++	 * whether we are in autoneg mode or not.
++	 */
++	ss = phy_read(phydev, AT803X_SPECIFIC_STATUS);
++	if (ss < 0)
++		return ss;
++
++	if (ss & AT803X_SS_SPEED_DUPLEX_RESOLVED) {
++		int sfc, speed;
++
++		sfc = phy_read(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL);
++		if (sfc < 0)
++			return sfc;
++
++		speed = ss & ss_mask.speed_mask;
++		speed >>= ss_mask.speed_shift;
++
++		switch (speed) {
++		case AT803X_SS_SPEED_10:
++			phydev->speed = SPEED_10;
++			break;
++		case AT803X_SS_SPEED_100:
++			phydev->speed = SPEED_100;
++			break;
++		case AT803X_SS_SPEED_1000:
++			phydev->speed = SPEED_1000;
++			break;
++		case QCA808X_SS_SPEED_2500:
++			phydev->speed = SPEED_2500;
++			break;
++		}
++		if (ss & AT803X_SS_DUPLEX)
++			phydev->duplex = DUPLEX_FULL;
++		else
++			phydev->duplex = DUPLEX_HALF;
++
++		if (ss & AT803X_SS_MDIX)
++			phydev->mdix = ETH_TP_MDI_X;
++		else
++			phydev->mdix = ETH_TP_MDI;
++
++		switch (FIELD_GET(AT803X_SFC_MDI_CROSSOVER_MODE_M, sfc)) {
++		case AT803X_SFC_MANUAL_MDI:
++			phydev->mdix_ctrl = ETH_TP_MDI;
++			break;
++		case AT803X_SFC_MANUAL_MDIX:
++			phydev->mdix_ctrl = ETH_TP_MDI_X;
++			break;
++		case AT803X_SFC_AUTOMATIC_CROSSOVER:
++			phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
++			break;
++		}
++	}
++
++	return 0;
++}
++
++static int at803x_read_status(struct phy_device *phydev)
++{
++	struct at803x_ss_mask ss_mask = { 0 };
++	int err, old_link = phydev->link;
++
++	/* Update the link, but return if there was an error */
++	err = genphy_update_link(phydev);
++	if (err)
++		return err;
++
++	/* why bother the PHY if nothing can have changed */
++	if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link)
++		return 0;
++
++	phydev->speed = SPEED_UNKNOWN;
++	phydev->duplex = DUPLEX_UNKNOWN;
++	phydev->pause = 0;
++	phydev->asym_pause = 0;
++
++	err = genphy_read_lpa(phydev);
++	if (err < 0)
++		return err;
++
++	ss_mask.speed_mask = AT803X_SS_SPEED_MASK;
++	ss_mask.speed_shift = __bf_shf(AT803X_SS_SPEED_MASK);
++	err = at803x_read_specific_status(phydev, ss_mask);
++	if (err < 0)
++		return err;
++
++	if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete)
++		phy_resolve_aneg_pause(phydev);
++
++	return 0;
++}
++
++static int at803x_config_mdix(struct phy_device *phydev, u8 ctrl)
++{
++	u16 val;
++
++	switch (ctrl) {
++	case ETH_TP_MDI:
++		val = AT803X_SFC_MANUAL_MDI;
++		break;
++	case ETH_TP_MDI_X:
++		val = AT803X_SFC_MANUAL_MDIX;
++		break;
++	case ETH_TP_MDI_AUTO:
++		val = AT803X_SFC_AUTOMATIC_CROSSOVER;
++		break;
++	default:
++		return 0;
++	}
++
++	return phy_modify_changed(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL,
++			  AT803X_SFC_MDI_CROSSOVER_MODE_M,
++			  FIELD_PREP(AT803X_SFC_MDI_CROSSOVER_MODE_M, val));
++}
++
++static int at803x_prepare_config_aneg(struct phy_device *phydev)
++{
++	int ret;
++
++	ret = at803x_config_mdix(phydev, phydev->mdix_ctrl);
++	if (ret < 0)
++		return ret;
++
++	/* Changes of the midx bits are disruptive to the normal operation;
++	 * therefore any changes to these registers must be followed by a
++	 * software reset to take effect.
++	 */
++	if (ret == 1) {
++		ret = genphy_soft_reset(phydev);
++		if (ret < 0)
++			return ret;
++	}
++
++	return 0;
++}
++
++static int at803x_config_aneg(struct phy_device *phydev)
++{
++	struct at803x_priv *priv = phydev->priv;
++	int ret;
++
++	ret = at803x_prepare_config_aneg(phydev);
++	if (ret)
++		return ret;
++
++	if (priv->is_1000basex)
++		return genphy_c37_config_aneg(phydev);
++
++	return genphy_config_aneg(phydev);
++}
++
++static int at803x_get_downshift(struct phy_device *phydev, u8 *d)
++{
++	int val;
++
++	val = phy_read(phydev, AT803X_SMART_SPEED);
++	if (val < 0)
++		return val;
++
++	if (val & AT803X_SMART_SPEED_ENABLE)
++		*d = FIELD_GET(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, val) + 2;
++	else
++		*d = DOWNSHIFT_DEV_DISABLE;
++
++	return 0;
++}
++
++static int at803x_set_downshift(struct phy_device *phydev, u8 cnt)
++{
++	u16 mask, set;
++	int ret;
++
++	switch (cnt) {
++	case DOWNSHIFT_DEV_DEFAULT_COUNT:
++		cnt = AT803X_DEFAULT_DOWNSHIFT;
++		fallthrough;
++	case AT803X_MIN_DOWNSHIFT ... AT803X_MAX_DOWNSHIFT:
++		set = AT803X_SMART_SPEED_ENABLE |
++		      AT803X_SMART_SPEED_BYPASS_TIMER |
++		      FIELD_PREP(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, cnt - 2);
++		mask = AT803X_SMART_SPEED_RETRY_LIMIT_MASK;
++		break;
++	case DOWNSHIFT_DEV_DISABLE:
++		set = 0;
++		mask = AT803X_SMART_SPEED_ENABLE |
++		       AT803X_SMART_SPEED_BYPASS_TIMER;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	ret = phy_modify_changed(phydev, AT803X_SMART_SPEED, mask, set);
++
++	/* After changing the smart speed settings, we need to perform a
++	 * software reset, use phy_init_hw() to make sure we set the
++	 * reapply any values which might got lost during software reset.
++	 */
++	if (ret == 1)
++		ret = phy_init_hw(phydev);
++
++	return ret;
++}
++
++static int at803x_get_tunable(struct phy_device *phydev,
++			      struct ethtool_tunable *tuna, void *data)
++{
++	switch (tuna->id) {
++	case ETHTOOL_PHY_DOWNSHIFT:
++		return at803x_get_downshift(phydev, data);
++	default:
++		return -EOPNOTSUPP;
++	}
++}
++
++static int at803x_set_tunable(struct phy_device *phydev,
++			      struct ethtool_tunable *tuna, const void *data)
++{
++	switch (tuna->id) {
++	case ETHTOOL_PHY_DOWNSHIFT:
++		return at803x_set_downshift(phydev, *(const u8 *)data);
++	default:
++		return -EOPNOTSUPP;
++	}
++}
++
++static int at803x_cable_test_result_trans(u16 status)
++{
++	switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) {
++	case AT803X_CDT_STATUS_STAT_NORMAL:
++		return ETHTOOL_A_CABLE_RESULT_CODE_OK;
++	case AT803X_CDT_STATUS_STAT_SHORT:
++		return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
++	case AT803X_CDT_STATUS_STAT_OPEN:
++		return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
++	case AT803X_CDT_STATUS_STAT_FAIL:
++	default:
++		return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
++	}
++}
++
++static bool at803x_cdt_test_failed(u16 status)
++{
++	return FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status) ==
++		AT803X_CDT_STATUS_STAT_FAIL;
++}
++
++static bool at803x_cdt_fault_length_valid(u16 status)
++{
++	switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) {
++	case AT803X_CDT_STATUS_STAT_OPEN:
++	case AT803X_CDT_STATUS_STAT_SHORT:
++		return true;
++	}
++	return false;
++}
++
++static int at803x_cdt_fault_length(int dt)
++{
++	/* According to the datasheet the distance to the fault is
++	 * DELTA_TIME * 0.824 meters.
++	 *
++	 * The author suspect the correct formula is:
++	 *
++	 *   fault_distance = DELTA_TIME * (c * VF) / 125MHz / 2
++	 *
++	 * where c is the speed of light, VF is the velocity factor of
++	 * the twisted pair cable, 125MHz the counter frequency and
++	 * we need to divide by 2 because the hardware will measure the
++	 * round trip time to the fault and back to the PHY.
++	 *
++	 * With a VF of 0.69 we get the factor 0.824 mentioned in the
++	 * datasheet.
++	 */
++	return (dt * 824) / 10;
++}
++
++static int at803x_cdt_start(struct phy_device *phydev,
++			    u32 cdt_start)
++{
++	return phy_write(phydev, AT803X_CDT, cdt_start);
++}
++
++static int at803x_cdt_wait_for_completion(struct phy_device *phydev,
++					  u32 cdt_en)
++{
++	int val, ret;
++
++	/* One test run takes about 25ms */
++	ret = phy_read_poll_timeout(phydev, AT803X_CDT, val,
++				    !(val & cdt_en),
++				    30000, 100000, true);
++
++	return ret < 0 ? ret : 0;
++}
++
++static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair)
++{
++	static const int ethtool_pair[] = {
++		ETHTOOL_A_CABLE_PAIR_A,
++		ETHTOOL_A_CABLE_PAIR_B,
++		ETHTOOL_A_CABLE_PAIR_C,
++		ETHTOOL_A_CABLE_PAIR_D,
++	};
++	int ret, val;
++
++	val = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) |
++	      AT803X_CDT_ENABLE_TEST;
++	ret = at803x_cdt_start(phydev, val);
++	if (ret)
++		return ret;
++
++	ret = at803x_cdt_wait_for_completion(phydev, AT803X_CDT_ENABLE_TEST);
++	if (ret)
++		return ret;
++
++	val = phy_read(phydev, AT803X_CDT_STATUS);
++	if (val < 0)
++		return val;
++
++	if (at803x_cdt_test_failed(val))
++		return 0;
++
++	ethnl_cable_test_result(phydev, ethtool_pair[pair],
++				at803x_cable_test_result_trans(val));
++
++	if (at803x_cdt_fault_length_valid(val)) {
++		val = FIELD_GET(AT803X_CDT_STATUS_DELTA_TIME_MASK, val);
++		ethnl_cable_test_fault_length(phydev, ethtool_pair[pair],
++					      at803x_cdt_fault_length(val));
++	}
++
++	return 1;
++}
++
++static int at803x_cable_test_get_status(struct phy_device *phydev,
++					bool *finished, unsigned long pair_mask)
++{
++	int retries = 20;
++	int pair, ret;
++
++	*finished = false;
++
++	/* According to the datasheet the CDT can be performed when
++	 * there is no link partner or when the link partner is
++	 * auto-negotiating. Starting the test will restart the AN
++	 * automatically. It seems that doing this repeatedly we will
++	 * get a slot where our link partner won't disturb our
++	 * measurement.
++	 */
++	while (pair_mask && retries--) {
++		for_each_set_bit(pair, &pair_mask, 4) {
++			ret = at803x_cable_test_one_pair(phydev, pair);
++			if (ret < 0)
++				return ret;
++			if (ret)
++				clear_bit(pair, &pair_mask);
++		}
++		if (pair_mask)
++			msleep(250);
++	}
++
++	*finished = true;
++
++	return 0;
++}
++
++static void at803x_cable_test_autoneg(struct phy_device *phydev)
++{
++	/* Enable auto-negotiation, but advertise no capabilities, no link
++	 * will be established. A restart of the auto-negotiation is not
++	 * required, because the cable test will automatically break the link.
++	 */
++	phy_write(phydev, MII_BMCR, BMCR_ANENABLE);
++	phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA);
++}
++
++static int at803x_cable_test_start(struct phy_device *phydev)
++{
++	at803x_cable_test_autoneg(phydev);
++	/* we do all the (time consuming) work later */
++	return 0;
++}
++
++static int at8031_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev,
++					    unsigned int selector)
++{
++	struct phy_device *phydev = rdev_get_drvdata(rdev);
++
++	if (selector)
++		return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
++					     0, AT803X_DEBUG_RGMII_1V8);
++	else
++		return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
++					     AT803X_DEBUG_RGMII_1V8, 0);
++}
++
++static int at8031_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev)
++{
++	struct phy_device *phydev = rdev_get_drvdata(rdev);
++	int val;
++
++	val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F);
++	if (val < 0)
++		return val;
++
++	return (val & AT803X_DEBUG_RGMII_1V8) ? 1 : 0;
++}
++
++static const struct regulator_ops vddio_regulator_ops = {
++	.list_voltage = regulator_list_voltage_table,
++	.set_voltage_sel = at8031_rgmii_reg_set_voltage_sel,
++	.get_voltage_sel = at8031_rgmii_reg_get_voltage_sel,
++};
++
++static const unsigned int vddio_voltage_table[] = {
++	1500000,
++	1800000,
++};
++
++static const struct regulator_desc vddio_desc = {
++	.name = "vddio",
++	.of_match = of_match_ptr("vddio-regulator"),
++	.n_voltages = ARRAY_SIZE(vddio_voltage_table),
++	.volt_table = vddio_voltage_table,
++	.ops = &vddio_regulator_ops,
++	.type = REGULATOR_VOLTAGE,
++	.owner = THIS_MODULE,
++};
++
++static const struct regulator_ops vddh_regulator_ops = {
++};
++
++static const struct regulator_desc vddh_desc = {
++	.name = "vddh",
++	.of_match = of_match_ptr("vddh-regulator"),
++	.n_voltages = 1,
++	.fixed_uV = 2500000,
++	.ops = &vddh_regulator_ops,
++	.type = REGULATOR_VOLTAGE,
++	.owner = THIS_MODULE,
++};
++
++static int at8031_register_regulators(struct phy_device *phydev)
++{
++	struct at803x_priv *priv = phydev->priv;
++	struct device *dev = &phydev->mdio.dev;
++	struct regulator_config config = { };
++
++	config.dev = dev;
++	config.driver_data = phydev;
++
++	priv->vddio_rdev = devm_regulator_register(dev, &vddio_desc, &config);
++	if (IS_ERR(priv->vddio_rdev)) {
++		phydev_err(phydev, "failed to register VDDIO regulator\n");
++		return PTR_ERR(priv->vddio_rdev);
++	}
++
++	priv->vddh_rdev = devm_regulator_register(dev, &vddh_desc, &config);
++	if (IS_ERR(priv->vddh_rdev)) {
++		phydev_err(phydev, "failed to register VDDH regulator\n");
++		return PTR_ERR(priv->vddh_rdev);
++	}
++
++	return 0;
++}
++
++static int at8031_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
++{
++	struct phy_device *phydev = upstream;
++	__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_support);
++	__ETHTOOL_DECLARE_LINK_MODE_MASK(sfp_support);
++	DECLARE_PHY_INTERFACE_MASK(interfaces);
++	phy_interface_t iface;
++
++	linkmode_zero(phy_support);
++	phylink_set(phy_support, 1000baseX_Full);
++	phylink_set(phy_support, 1000baseT_Full);
++	phylink_set(phy_support, Autoneg);
++	phylink_set(phy_support, Pause);
++	phylink_set(phy_support, Asym_Pause);
++
++	linkmode_zero(sfp_support);
++	sfp_parse_support(phydev->sfp_bus, id, sfp_support, interfaces);
++	/* Some modules support 10G modes as well as others we support.
++	 * Mask out non-supported modes so the correct interface is picked.
++	 */
++	linkmode_and(sfp_support, phy_support, sfp_support);
++
++	if (linkmode_empty(sfp_support)) {
++		dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n");
++		return -EINVAL;
++	}
++
++	iface = sfp_select_interface(phydev->sfp_bus, sfp_support);
++
++	/* Only 1000Base-X is supported by AR8031/8033 as the downstream SerDes
++	 * interface for use with SFP modules.
++	 * However, some copper modules detected as having a preferred SGMII
++	 * interface do default to and function in 1000Base-X mode, so just
++	 * print a warning and allow such modules, as they may have some chance
++	 * of working.
++	 */
++	if (iface == PHY_INTERFACE_MODE_SGMII)
++		dev_warn(&phydev->mdio.dev, "module may not function if 1000Base-X not supported\n");
++	else if (iface != PHY_INTERFACE_MODE_1000BASEX)
++		return -EINVAL;
++
++	return 0;
++}
++
++static const struct sfp_upstream_ops at8031_sfp_ops = {
++	.attach = phy_sfp_attach,
++	.detach = phy_sfp_detach,
++	.module_insert = at8031_sfp_insert,
++};
++
++static int at8031_parse_dt(struct phy_device *phydev)
++{
++	struct device_node *node = phydev->mdio.dev.of_node;
++	struct at803x_priv *priv = phydev->priv;
++	int ret;
++
++	if (of_property_read_bool(node, "qca,keep-pll-enabled"))
++		priv->flags |= AT803X_KEEP_PLL_ENABLED;
++
++	ret = at8031_register_regulators(phydev);
++	if (ret < 0)
++		return ret;
++
++	ret = devm_regulator_get_enable_optional(&phydev->mdio.dev,
++						 "vddio");
++	if (ret) {
++		phydev_err(phydev, "failed to get VDDIO regulator\n");
++		return ret;
++	}
++
++	/* Only AR8031/8033 support 1000Base-X for SFP modules */
++	return phy_sfp_probe(phydev, &at8031_sfp_ops);
++}
++
++static int at8031_probe(struct phy_device *phydev)
++{
++	struct at803x_priv *priv = phydev->priv;
++	int mode_cfg;
++	int ccr;
++	int ret;
++
++	ret = at803x_probe(phydev);
++	if (ret)
++		return ret;
++
++	/* Only supported on AR8031/AR8033, the AR8030/AR8035 use strapping
++	 * options.
++	 */
++	ret = at8031_parse_dt(phydev);
++	if (ret)
++		return ret;
++
++	ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG);
++	if (ccr < 0)
++		return ccr;
++	mode_cfg = ccr & AT803X_MODE_CFG_MASK;
++
++	switch (mode_cfg) {
++	case AT803X_MODE_CFG_BX1000_RGMII_50OHM:
++	case AT803X_MODE_CFG_BX1000_RGMII_75OHM:
++		priv->is_1000basex = true;
++		fallthrough;
++	case AT803X_MODE_CFG_FX100_RGMII_50OHM:
++	case AT803X_MODE_CFG_FX100_RGMII_75OHM:
++		priv->is_fiber = true;
++		break;
++	}
++
++	/* Disable WoL in 1588 register which is enabled
++	 * by default
++	 */
++	return phy_modify_mmd(phydev, MDIO_MMD_PCS,
++			      AT803X_PHY_MMD3_WOL_CTRL,
++			      AT803X_WOL_EN, 0);
++}
++
++static int at8031_config_init(struct phy_device *phydev)
++{
++	struct at803x_priv *priv = phydev->priv;
++	int ret;
++
++	/* Some bootloaders leave the fiber page selected.
++	 * Switch to the appropriate page (fiber or copper), as otherwise we
++	 * read the PHY capabilities from the wrong page.
++	 */
++	phy_lock_mdio_bus(phydev);
++	ret = at803x_write_page(phydev,
++				priv->is_fiber ? AT803X_PAGE_FIBER :
++						 AT803X_PAGE_COPPER);
++	phy_unlock_mdio_bus(phydev);
++	if (ret)
++		return ret;
++
++	ret = at8031_pll_config(phydev);
++	if (ret < 0)
++		return ret;
++
++	return at803x_config_init(phydev);
++}
++
++static int at8031_set_wol(struct phy_device *phydev,
++			  struct ethtool_wolinfo *wol)
++{
++	int ret;
++
++	/* First setup MAC address and enable WOL interrupt */
++	ret = at803x_set_wol(phydev, wol);
++	if (ret)
++		return ret;
++
++	if (wol->wolopts & WAKE_MAGIC)
++		/* Enable WOL function for 1588 */
++		ret = phy_modify_mmd(phydev, MDIO_MMD_PCS,
++				     AT803X_PHY_MMD3_WOL_CTRL,
++				     0, AT803X_WOL_EN);
++	else
++		/* Disable WoL function for 1588 */
++		ret = phy_modify_mmd(phydev, MDIO_MMD_PCS,
++				     AT803X_PHY_MMD3_WOL_CTRL,
++				     AT803X_WOL_EN, 0);
++
++	return ret;
++}
++
++static int at8031_config_intr(struct phy_device *phydev)
++{
++	struct at803x_priv *priv = phydev->priv;
++	int err, value = 0;
++
++	if (phydev->interrupts == PHY_INTERRUPT_ENABLED &&
++	    priv->is_fiber) {
++		/* Clear any pending interrupts */
++		err = at803x_ack_interrupt(phydev);
++		if (err)
++			return err;
++
++		value |= AT803X_INTR_ENABLE_LINK_FAIL_BX;
++		value |= AT803X_INTR_ENABLE_LINK_SUCCESS_BX;
++
++		err = phy_set_bits(phydev, AT803X_INTR_ENABLE, value);
++		if (err)
++			return err;
++	}
++
++	return at803x_config_intr(phydev);
++}
++
++/* AR8031 and AR8033 share the same read status logic */
++static int at8031_read_status(struct phy_device *phydev)
++{
++	struct at803x_priv *priv = phydev->priv;
++
++	if (priv->is_1000basex)
++		return genphy_c37_read_status(phydev);
++
++	return at803x_read_status(phydev);
++}
++
++/* AR8031 and AR8035 share the same cable test get status reg */
++static int at8031_cable_test_get_status(struct phy_device *phydev,
++					bool *finished)
++{
++	return at803x_cable_test_get_status(phydev, finished, 0xf);
++}
++
++/* AR8031 and AR8035 share the same cable test start logic */
++static int at8031_cable_test_start(struct phy_device *phydev)
++{
++	at803x_cable_test_autoneg(phydev);
++	phy_write(phydev, MII_CTRL1000, 0);
++	/* we do all the (time consuming) work later */
++	return 0;
++}
++
++/* AR8032, AR9331 and QCA9561 share the same cable test get status reg */
++static int at8032_cable_test_get_status(struct phy_device *phydev,
++					bool *finished)
++{
++	return at803x_cable_test_get_status(phydev, finished, 0x3);
++}
++
++static int at8035_parse_dt(struct phy_device *phydev)
++{
++	struct at803x_priv *priv = phydev->priv;
++
++	/* Mask is set by the generic at803x_parse_dt
++	 * if property is set. Assume property is set
++	 * with the mask not zero.
++	 */
++	if (priv->clk_25m_mask) {
++		/* Fixup for the AR8030/AR8035. This chip has another mask and
++		 * doesn't support the DSP reference. Eg. the lowest bit of the
++		 * mask. The upper two bits select the same frequencies. Mask
++		 * the lowest bit here.
++		 *
++		 * Warning:
++		 *   There was no datasheet for the AR8030 available so this is
++		 *   just a guess. But the AR8035 is listed as pin compatible
++		 *   to the AR8030 so there might be a good chance it works on
++		 *   the AR8030 too.
++		 */
++		priv->clk_25m_reg &= AT8035_CLK_OUT_MASK;
++		priv->clk_25m_mask &= AT8035_CLK_OUT_MASK;
++	}
++
++	return 0;
++}
++
++/* AR8030 and AR8035 shared the same special mask for clk_25m */
++static int at8035_probe(struct phy_device *phydev)
++{
++	int ret;
++
++	ret = at803x_probe(phydev);
++	if (ret)
++		return ret;
++
++	return at8035_parse_dt(phydev);
++}
++
++static int qca83xx_config_init(struct phy_device *phydev)
++{
++	u8 switch_revision;
++
++	switch_revision = phydev->dev_flags & QCA8K_DEVFLAGS_REVISION_MASK;
++
++	switch (switch_revision) {
++	case 1:
++		/* For 100M waveform */
++		at803x_debug_reg_write(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0x02ea);
++		/* Turn on Gigabit clock */
++		at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x68a0);
++		break;
++
++	case 2:
++		phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0);
++		fallthrough;
++	case 4:
++		phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f);
++		at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x6860);
++		at803x_debug_reg_write(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0x2c46);
++		at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3C, 0x6000);
++		break;
++	}
++
++	/* Following original QCA sourcecode set port to prefer master */
++	phy_set_bits(phydev, MII_CTRL1000, CTL1000_PREFER_MASTER);
++
++	return 0;
++}
++
++static int qca8327_config_init(struct phy_device *phydev)
++{
++	/* QCA8327 require DAC amplitude adjustment for 100m set to +6%.
++	 * Disable on init and enable only with 100m speed following
++	 * qca original source code.
++	 */
++	at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
++			      QCA8327_DEBUG_MANU_CTRL_EN, 0);
++
++	return qca83xx_config_init(phydev);
++}
++
++static void qca83xx_link_change_notify(struct phy_device *phydev)
++{
++	/* Set DAC Amplitude adjustment to +6% for 100m on link running */
++	if (phydev->state == PHY_RUNNING) {
++		if (phydev->speed == SPEED_100)
++			at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
++					      QCA8327_DEBUG_MANU_CTRL_EN,
++					      QCA8327_DEBUG_MANU_CTRL_EN);
++	} else {
++		/* Reset DAC Amplitude adjustment */
++		at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
++				      QCA8327_DEBUG_MANU_CTRL_EN, 0);
++	}
++}
++
++static int qca83xx_resume(struct phy_device *phydev)
++{
++	int ret, val;
++
++	/* Skip reset if not suspended */
++	if (!phydev->suspended)
++		return 0;
++
++	/* Reinit the port, reset values set by suspend */
++	qca83xx_config_init(phydev);
++
++	/* Reset the port on port resume */
++	phy_set_bits(phydev, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
++
++	/* On resume from suspend the switch execute a reset and
++	 * restart auto-negotiation. Wait for reset to complete.
++	 */
++	ret = phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET),
++				    50000, 600000, true);
++	if (ret)
++		return ret;
++
++	usleep_range(1000, 2000);
++
++	return 0;
++}
++
++static int qca83xx_suspend(struct phy_device *phydev)
++{
++	at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_GREEN,
++			      AT803X_DEBUG_GATE_CLK_IN1000, 0);
++
++	at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL,
++			      AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE |
++			      AT803X_DEBUG_HIB_CTRL_SEL_RST_80U, 0);
++
++	return 0;
++}
++
++static int qca8337_suspend(struct phy_device *phydev)
++{
++	/* Only QCA8337 support actual suspend. */
++	genphy_suspend(phydev);
++
++	return qca83xx_suspend(phydev);
++}
++
++static int qca8327_suspend(struct phy_device *phydev)
++{
++	u16 mask = 0;
++
++	/* QCA8327 cause port unreliability when phy suspend
++	 * is set.
++	 */
++	mask |= ~(BMCR_SPEED1000 | BMCR_FULLDPLX);
++	phy_modify(phydev, MII_BMCR, mask, 0);
++
++	return qca83xx_suspend(phydev);
++}
++
++static int qca808x_phy_fast_retrain_config(struct phy_device *phydev)
++{
++	int ret;
++
++	/* Enable fast retrain */
++	ret = genphy_c45_fast_retrain(phydev, true);
++	if (ret)
++		return ret;
++
++	phy_write_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_TOP_OPTION1,
++		      QCA808X_TOP_OPTION1_DATA);
++	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB,
++		      QCA808X_MSE_THRESHOLD_20DB_VALUE);
++	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB,
++		      QCA808X_MSE_THRESHOLD_17DB_VALUE);
++	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB,
++		      QCA808X_MSE_THRESHOLD_27DB_VALUE);
++	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB,
++		      QCA808X_MSE_THRESHOLD_28DB_VALUE);
++	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_1,
++		      QCA808X_MMD3_DEBUG_1_VALUE);
++	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_4,
++		      QCA808X_MMD3_DEBUG_4_VALUE);
++	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_5,
++		      QCA808X_MMD3_DEBUG_5_VALUE);
++	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_3,
++		      QCA808X_MMD3_DEBUG_3_VALUE);
++	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_6,
++		      QCA808X_MMD3_DEBUG_6_VALUE);
++	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_2,
++		      QCA808X_MMD3_DEBUG_2_VALUE);
++
++	return 0;
++}
++
++static int qca808x_phy_ms_seed_enable(struct phy_device *phydev, bool enable)
++{
++	u16 seed_value;
++
++	if (!enable)
++		return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED,
++				QCA808X_MASTER_SLAVE_SEED_ENABLE, 0);
++
++	seed_value = prandom_u32_max(QCA808X_MASTER_SLAVE_SEED_RANGE);
++	return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED,
++			QCA808X_MASTER_SLAVE_SEED_CFG | QCA808X_MASTER_SLAVE_SEED_ENABLE,
++			FIELD_PREP(QCA808X_MASTER_SLAVE_SEED_CFG, seed_value) |
++			QCA808X_MASTER_SLAVE_SEED_ENABLE);
++}
++
++static bool qca808x_is_prefer_master(struct phy_device *phydev)
++{
++	return (phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_FORCE) ||
++		(phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_PREFERRED);
++}
++
++static bool qca808x_has_fast_retrain_or_slave_seed(struct phy_device *phydev)
++{
++	return linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported);
++}
++
++static int qca808x_config_init(struct phy_device *phydev)
++{
++	int ret;
++
++	/* Active adc&vga on 802.3az for the link 1000M and 100M */
++	ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_ADDR_CLD_CTRL7,
++			     QCA808X_8023AZ_AFE_CTRL_MASK, QCA808X_8023AZ_AFE_EN);
++	if (ret)
++		return ret;
++
++	/* Adjust the threshold on 802.3az for the link 1000M */
++	ret = phy_write_mmd(phydev, MDIO_MMD_PCS,
++			    QCA808X_PHY_MMD3_AZ_TRAINING_CTRL,
++			    QCA808X_MMD3_AZ_TRAINING_VAL);
++	if (ret)
++		return ret;
++
++	if (qca808x_has_fast_retrain_or_slave_seed(phydev)) {
++		/* Config the fast retrain for the link 2500M */
++		ret = qca808x_phy_fast_retrain_config(phydev);
++		if (ret)
++			return ret;
++
++		ret = genphy_read_master_slave(phydev);
++		if (ret < 0)
++			return ret;
++
++		if (!qca808x_is_prefer_master(phydev)) {
++			/* Enable seed and configure lower ramdom seed to make phy
++			 * linked as slave mode.
++			 */
++			ret = qca808x_phy_ms_seed_enable(phydev, true);
++			if (ret)
++				return ret;
++		}
++	}
++
++	/* Configure adc threshold as 100mv for the link 10M */
++	return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD,
++				     QCA808X_ADC_THRESHOLD_MASK,
++				     QCA808X_ADC_THRESHOLD_100MV);
++}
++
++static int qca808x_read_status(struct phy_device *phydev)
++{
++	struct at803x_ss_mask ss_mask = { 0 };
++	int ret;
++
++	ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);
++	if (ret < 0)
++		return ret;
++
++	linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->lp_advertising,
++			 ret & MDIO_AN_10GBT_STAT_LP2_5G);
++
++	ret = genphy_read_status(phydev);
++	if (ret)
++		return ret;
++
++	/* qca8081 takes the different bits for speed value from at803x */
++	ss_mask.speed_mask = QCA808X_SS_SPEED_MASK;
++	ss_mask.speed_shift = __bf_shf(QCA808X_SS_SPEED_MASK);
++	ret = at803x_read_specific_status(phydev, ss_mask);
++	if (ret < 0)
++		return ret;
++
++	if (phydev->link) {
++		if (phydev->speed == SPEED_2500)
++			phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
++		else
++			phydev->interface = PHY_INTERFACE_MODE_SGMII;
++	} else {
++		/* generate seed as a lower random value to make PHY linked as SLAVE easily,
++		 * except for master/slave configuration fault detected or the master mode
++		 * preferred.
++		 *
++		 * the reason for not putting this code into the function link_change_notify is
++		 * the corner case where the link partner is also the qca8081 PHY and the seed
++		 * value is configured as the same value, the link can't be up and no link change
++		 * occurs.
++		 */
++		if (qca808x_has_fast_retrain_or_slave_seed(phydev)) {
++			if (phydev->master_slave_state == MASTER_SLAVE_STATE_ERR ||
++			    qca808x_is_prefer_master(phydev)) {
++				qca808x_phy_ms_seed_enable(phydev, false);
++			} else {
++				qca808x_phy_ms_seed_enable(phydev, true);
++			}
++		}
++	}
++
++	return 0;
++}
++
++static int qca808x_soft_reset(struct phy_device *phydev)
++{
++	int ret;
++
++	ret = genphy_soft_reset(phydev);
++	if (ret < 0)
++		return ret;
++
++	if (qca808x_has_fast_retrain_or_slave_seed(phydev))
++		ret = qca808x_phy_ms_seed_enable(phydev, true);
++
++	return ret;
++}
++
++static bool qca808x_cdt_fault_length_valid(int cdt_code)
++{
++	switch (cdt_code) {
++	case QCA808X_CDT_STATUS_STAT_SAME_SHORT:
++	case QCA808X_CDT_STATUS_STAT_SAME_OPEN:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT:
++		return true;
++	default:
++		return false;
++	}
++}
++
++static int qca808x_cable_test_result_trans(int cdt_code)
++{
++	switch (cdt_code) {
++	case QCA808X_CDT_STATUS_STAT_NORMAL:
++		return ETHTOOL_A_CABLE_RESULT_CODE_OK;
++	case QCA808X_CDT_STATUS_STAT_SAME_SHORT:
++		return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
++	case QCA808X_CDT_STATUS_STAT_SAME_OPEN:
++		return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT:
++		return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;
++	case QCA808X_CDT_STATUS_STAT_FAIL:
++	default:
++		return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
++	}
++}
++
++static int qca808x_cdt_fault_length(struct phy_device *phydev, int pair,
++				    int result)
++{
++	int val;
++	u32 cdt_length_reg = 0;
++
++	switch (pair) {
++	case ETHTOOL_A_CABLE_PAIR_A:
++		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_A;
++		break;
++	case ETHTOOL_A_CABLE_PAIR_B:
++		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_B;
++		break;
++	case ETHTOOL_A_CABLE_PAIR_C:
++		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_C;
++		break;
++	case ETHTOOL_A_CABLE_PAIR_D:
++		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_D;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	val = phy_read_mmd(phydev, MDIO_MMD_PCS, cdt_length_reg);
++	if (val < 0)
++		return val;
++
++	if (result == ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT)
++		val = FIELD_GET(QCA808X_CDT_DIAG_LENGTH_SAME_SHORT, val);
++	else
++		val = FIELD_GET(QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT, val);
++
++	return at803x_cdt_fault_length(val);
++}
++
++static int qca808x_cable_test_start(struct phy_device *phydev)
++{
++	int ret;
++
++	/* perform CDT with the following configs:
++	 * 1. disable hibernation.
++	 * 2. force PHY working in MDI mode.
++	 * 3. for PHY working in 1000BaseT.
++	 * 4. configure the threshold.
++	 */
++
++	ret = at803x_debug_reg_mask(phydev, QCA808X_DBG_AN_TEST, QCA808X_HIBERNATION_EN, 0);
++	if (ret < 0)
++		return ret;
++
++	ret = at803x_config_mdix(phydev, ETH_TP_MDI);
++	if (ret < 0)
++		return ret;
++
++	/* Force 1000base-T needs to configure PMA/PMD and MII_BMCR */
++	phydev->duplex = DUPLEX_FULL;
++	phydev->speed = SPEED_1000;
++	ret = genphy_c45_pma_setup_forced(phydev);
++	if (ret < 0)
++		return ret;
++
++	ret = genphy_setup_forced(phydev);
++	if (ret < 0)
++		return ret;
++
++	/* configure the thresholds for open, short, pair ok test */
++	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8074, 0xc040);
++	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8076, 0xc040);
++	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8077, 0xa060);
++	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8078, 0xc050);
++	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060);
++	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807e, 0xb060);
++
++	return 0;
++}
++
++static int qca808x_cable_test_get_pair_status(struct phy_device *phydev, u8 pair,
++					      u16 status)
++{
++	int length, result;
++	u16 pair_code;
++
++	switch (pair) {
++	case ETHTOOL_A_CABLE_PAIR_A:
++		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_A, status);
++		break;
++	case ETHTOOL_A_CABLE_PAIR_B:
++		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_B, status);
++		break;
++	case ETHTOOL_A_CABLE_PAIR_C:
++		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_C, status);
++		break;
++	case ETHTOOL_A_CABLE_PAIR_D:
++		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_D, status);
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	result = qca808x_cable_test_result_trans(pair_code);
++	ethnl_cable_test_result(phydev, pair, result);
++
++	if (qca808x_cdt_fault_length_valid(pair_code)) {
++		length = qca808x_cdt_fault_length(phydev, pair, result);
++		ethnl_cable_test_fault_length(phydev, pair, length);
++	}
++
++	return 0;
++}
++
++static int qca808x_cable_test_get_status(struct phy_device *phydev, bool *finished)
++{
++	int ret, val;
++
++	*finished = false;
++
++	val = QCA808X_CDT_ENABLE_TEST |
++	      QCA808X_CDT_LENGTH_UNIT;
++	ret = at803x_cdt_start(phydev, val);
++	if (ret)
++		return ret;
++
++	ret = at803x_cdt_wait_for_completion(phydev, QCA808X_CDT_ENABLE_TEST);
++	if (ret)
++		return ret;
++
++	val = phy_read_mmd(phydev, MDIO_MMD_PCS, QCA808X_MMD3_CDT_STATUS);
++	if (val < 0)
++		return val;
++
++	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_A, val);
++	if (ret)
++		return ret;
++
++	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_B, val);
++	if (ret)
++		return ret;
++
++	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_C, val);
++	if (ret)
++		return ret;
++
++	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_D, val);
++	if (ret)
++		return ret;
++
++	*finished = true;
++
++	return 0;
++}
++
++static int qca808x_get_features(struct phy_device *phydev)
++{
++	int ret;
++
++	ret = genphy_c45_pma_read_abilities(phydev);
++	if (ret)
++		return ret;
++
++	/* The autoneg ability is not existed in bit3 of MMD7.1,
++	 * but it is supported by qca808x PHY, so we add it here
++	 * manually.
++	 */
++	linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
++
++	/* As for the qca8081 1G version chip, the 2500baseT ability is also
++	 * existed in the bit0 of MMD1.21, we need to remove it manually if
++	 * it is the qca8081 1G chip according to the bit0 of MMD7.0x901d.
++	 */
++	ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_CHIP_TYPE);
++	if (ret < 0)
++		return ret;
++
++	if (QCA808X_PHY_CHIP_TYPE_1G & ret)
++		linkmode_clear_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported);
++
++	return 0;
++}
++
++static int qca808x_config_aneg(struct phy_device *phydev)
++{
++	int phy_ctrl = 0;
++	int ret;
++
++	ret = at803x_prepare_config_aneg(phydev);
++	if (ret)
++		return ret;
++
++	/* The reg MII_BMCR also needs to be configured for force mode, the
++	 * genphy_config_aneg is also needed.
++	 */
++	if (phydev->autoneg == AUTONEG_DISABLE)
++		genphy_c45_pma_setup_forced(phydev);
++
++	if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->advertising))
++		phy_ctrl = MDIO_AN_10GBT_CTRL_ADV2_5G;
++
++	ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
++				     MDIO_AN_10GBT_CTRL_ADV2_5G, phy_ctrl);
++	if (ret < 0)
++		return ret;
++
++	return __genphy_config_aneg(phydev, ret);
++}
++
++static void qca808x_link_change_notify(struct phy_device *phydev)
++{
++	/* Assert interface sgmii fifo on link down, deassert it on link up,
++	 * the interface device address is always phy address added by 1.
++	 */
++	mdiobus_c45_modify_changed(phydev->mdio.bus, phydev->mdio.addr + 1,
++				   MDIO_MMD_PMAPMD, QCA8081_PHY_SERDES_MMD1_FIFO_CTRL,
++				   QCA8081_PHY_FIFO_RSTN,
++				   phydev->link ? QCA8081_PHY_FIFO_RSTN : 0);
++}
++
++static int qca808x_led_parse_netdev(struct phy_device *phydev, unsigned long rules,
++				    u16 *offload_trigger)
++{
++	/* Parsing specific to netdev trigger */
++	if (test_bit(TRIGGER_NETDEV_TX, &rules))
++		*offload_trigger |= QCA808X_LED_TX_BLINK;
++	if (test_bit(TRIGGER_NETDEV_RX, &rules))
++		*offload_trigger |= QCA808X_LED_RX_BLINK;
++	if (test_bit(TRIGGER_NETDEV_LINK_10, &rules))
++		*offload_trigger |= QCA808X_LED_SPEED10_ON;
++	if (test_bit(TRIGGER_NETDEV_LINK_100, &rules))
++		*offload_trigger |= QCA808X_LED_SPEED100_ON;
++	if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules))
++		*offload_trigger |= QCA808X_LED_SPEED1000_ON;
++	if (test_bit(TRIGGER_NETDEV_LINK_2500, &rules))
++		*offload_trigger |= QCA808X_LED_SPEED2500_ON;
++	if (test_bit(TRIGGER_NETDEV_HALF_DUPLEX, &rules))
++		*offload_trigger |= QCA808X_LED_HALF_DUPLEX_ON;
++	if (test_bit(TRIGGER_NETDEV_FULL_DUPLEX, &rules))
++		*offload_trigger |= QCA808X_LED_FULL_DUPLEX_ON;
++
++	if (rules && !*offload_trigger)
++		return -EOPNOTSUPP;
++
++	/* Enable BLINK_CHECK_BYPASS by default to make the LED
++	 * blink even with duplex or speed mode not enabled.
++	 */
++	*offload_trigger |= QCA808X_LED_BLINK_CHECK_BYPASS;
++
++	return 0;
++}
++
++static int qca808x_led_hw_control_enable(struct phy_device *phydev, u8 index)
++{
++	u16 reg;
++
++	if (index > 2)
++		return -EINVAL;
++
++	reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
++
++	return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg,
++				  QCA808X_LED_FORCE_EN);
++}
++
++static int qca808x_led_hw_is_supported(struct phy_device *phydev, u8 index,
++				       unsigned long rules)
++{
++	u16 offload_trigger = 0;
++
++	if (index > 2)
++		return -EINVAL;
++
++	return qca808x_led_parse_netdev(phydev, rules, &offload_trigger);
++}
++
++static int qca808x_led_hw_control_set(struct phy_device *phydev, u8 index,
++				      unsigned long rules)
++{
++	u16 reg, offload_trigger = 0;
++	int ret;
++
++	if (index > 2)
++		return -EINVAL;
++
++	reg = QCA808X_MMD7_LED_CTRL(index);
++
++	ret = qca808x_led_parse_netdev(phydev, rules, &offload_trigger);
++	if (ret)
++		return ret;
++
++	ret = qca808x_led_hw_control_enable(phydev, index);
++	if (ret)
++		return ret;
++
++	return phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
++			      QCA808X_LED_PATTERN_MASK,
++			      offload_trigger);
++}
++
++static bool qca808x_led_hw_control_status(struct phy_device *phydev, u8 index)
++{
++	u16 reg;
++	int val;
++
++	if (index > 2)
++		return false;
++
++	reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
++
++	val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
++
++	return !(val & QCA808X_LED_FORCE_EN);
++}
++
++static int qca808x_led_hw_control_get(struct phy_device *phydev, u8 index,
++				      unsigned long *rules)
++{
++	u16 reg;
++	int val;
++
++	if (index > 2)
++		return -EINVAL;
++
++	/* Check if we have hw control enabled */
++	if (qca808x_led_hw_control_status(phydev, index))
++		return -EINVAL;
++
++	reg = QCA808X_MMD7_LED_CTRL(index);
++
++	val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
++	if (val & QCA808X_LED_TX_BLINK)
++		set_bit(TRIGGER_NETDEV_TX, rules);
++	if (val & QCA808X_LED_RX_BLINK)
++		set_bit(TRIGGER_NETDEV_RX, rules);
++	if (val & QCA808X_LED_SPEED10_ON)
++		set_bit(TRIGGER_NETDEV_LINK_10, rules);
++	if (val & QCA808X_LED_SPEED100_ON)
++		set_bit(TRIGGER_NETDEV_LINK_100, rules);
++	if (val & QCA808X_LED_SPEED1000_ON)
++		set_bit(TRIGGER_NETDEV_LINK_1000, rules);
++	if (val & QCA808X_LED_SPEED2500_ON)
++		set_bit(TRIGGER_NETDEV_LINK_2500, rules);
++	if (val & QCA808X_LED_HALF_DUPLEX_ON)
++		set_bit(TRIGGER_NETDEV_HALF_DUPLEX, rules);
++	if (val & QCA808X_LED_FULL_DUPLEX_ON)
++		set_bit(TRIGGER_NETDEV_FULL_DUPLEX, rules);
++
++	return 0;
++}
++
++static int qca808x_led_hw_control_reset(struct phy_device *phydev, u8 index)
++{
++	u16 reg;
++
++	if (index > 2)
++		return -EINVAL;
++
++	reg = QCA808X_MMD7_LED_CTRL(index);
++
++	return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg,
++				  QCA808X_LED_PATTERN_MASK);
++}
++
++static int qca808x_led_brightness_set(struct phy_device *phydev,
++				      u8 index, enum led_brightness value)
++{
++	u16 reg;
++	int ret;
++
++	if (index > 2)
++		return -EINVAL;
++
++	if (!value) {
++		ret = qca808x_led_hw_control_reset(phydev, index);
++		if (ret)
++			return ret;
++	}
++
++	reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
++
++	return phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
++			      QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_MODE_MASK,
++			      QCA808X_LED_FORCE_EN | value ? QCA808X_LED_FORCE_ON :
++							     QCA808X_LED_FORCE_OFF);
++}
++
++static int qca808x_led_blink_set(struct phy_device *phydev, u8 index,
++				 unsigned long *delay_on,
++				 unsigned long *delay_off)
++{
++	int ret;
++	u16 reg;
++
++	if (index > 2)
++		return -EINVAL;
++
++	reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
++
++	/* Set blink to 50% off, 50% on at 4Hz by default */
++	ret = phy_modify_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_LED_GLOBAL,
++			     QCA808X_LED_BLINK_FREQ_MASK | QCA808X_LED_BLINK_DUTY_MASK,
++			     QCA808X_LED_BLINK_FREQ_4HZ | QCA808X_LED_BLINK_DUTY_50_50);
++	if (ret)
++		return ret;
++
++	/* We use BLINK_1 for normal blinking */
++	ret = phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
++			     QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_MODE_MASK,
++			     QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_BLINK_1);
++	if (ret)
++		return ret;
++
++	/* We set blink to 4Hz, aka 250ms */
++	*delay_on = 250 / 2;
++	*delay_off = 250 / 2;
++
++	return 0;
++}
++
++static int qca808x_led_polarity_set(struct phy_device *phydev, int index,
++				    unsigned long modes)
++{
++	struct at803x_priv *priv = phydev->priv;
++	bool active_low = false;
++	u32 mode;
++
++	for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) {
++		switch (mode) {
++		case PHY_LED_ACTIVE_LOW:
++			active_low = true;
++			break;
++		default:
++			return -EINVAL;
++		}
++	}
++
++	/* PHY polarity is global and can't be set per LED.
++	 * To detect this, check if last requested polarity mode
++	 * match the new one.
++	 */
++	if (priv->led_polarity_mode >= 0 &&
++	    priv->led_polarity_mode != active_low) {
++		phydev_err(phydev, "PHY polarity is global. Mismatched polarity on different LED\n");
++		return -EINVAL;
++	}
++
++	/* Save the last PHY polarity mode */
++	priv->led_polarity_mode = active_low;
++
++	return phy_modify_mmd(phydev, MDIO_MMD_AN,
++			      QCA808X_MMD7_LED_POLARITY_CTRL,
++			      QCA808X_LED_ACTIVE_HIGH,
++			      active_low ? 0 : QCA808X_LED_ACTIVE_HIGH);
++}
++
++static struct phy_driver at803x_driver[] = {
++{
++	/* Qualcomm Atheros AR8035 */
++	PHY_ID_MATCH_EXACT(ATH8035_PHY_ID),
++	.name			= "Qualcomm Atheros AR8035",
++	.flags			= PHY_POLL_CABLE_TEST,
++	.probe			= at8035_probe,
++	.config_aneg		= at803x_config_aneg,
++	.config_init		= at803x_config_init,
++	.soft_reset		= genphy_soft_reset,
++	.set_wol		= at803x_set_wol,
++	.get_wol		= at803x_get_wol,
++	.suspend		= at803x_suspend,
++	.resume			= at803x_resume,
++	/* PHY_GBIT_FEATURES */
++	.read_status		= at803x_read_status,
++	.config_intr		= at803x_config_intr,
++	.handle_interrupt	= at803x_handle_interrupt,
++	.get_tunable		= at803x_get_tunable,
++	.set_tunable		= at803x_set_tunable,
++	.cable_test_start	= at8031_cable_test_start,
++	.cable_test_get_status	= at8031_cable_test_get_status,
++}, {
++	/* Qualcomm Atheros AR8030 */
++	.phy_id			= ATH8030_PHY_ID,
++	.name			= "Qualcomm Atheros AR8030",
++	.phy_id_mask		= AT8030_PHY_ID_MASK,
++	.probe			= at8035_probe,
++	.config_init		= at803x_config_init,
++	.link_change_notify	= at803x_link_change_notify,
++	.set_wol		= at803x_set_wol,
++	.get_wol		= at803x_get_wol,
++	.suspend		= at803x_suspend,
++	.resume			= at803x_resume,
++	/* PHY_BASIC_FEATURES */
++	.config_intr		= at803x_config_intr,
++	.handle_interrupt	= at803x_handle_interrupt,
++}, {
++	/* Qualcomm Atheros AR8031/AR8033 */
++	PHY_ID_MATCH_EXACT(ATH8031_PHY_ID),
++	.name			= "Qualcomm Atheros AR8031/AR8033",
++	.flags			= PHY_POLL_CABLE_TEST,
++	.probe			= at8031_probe,
++	.config_init		= at8031_config_init,
++	.config_aneg		= at803x_config_aneg,
++	.soft_reset		= genphy_soft_reset,
++	.set_wol		= at8031_set_wol,
++	.get_wol		= at803x_get_wol,
++	.suspend		= at803x_suspend,
++	.resume			= at803x_resume,
++	.read_page		= at803x_read_page,
++	.write_page		= at803x_write_page,
++	.get_features		= at803x_get_features,
++	.read_status		= at8031_read_status,
++	.config_intr		= at8031_config_intr,
++	.handle_interrupt	= at803x_handle_interrupt,
++	.get_tunable		= at803x_get_tunable,
++	.set_tunable		= at803x_set_tunable,
++	.cable_test_start	= at8031_cable_test_start,
++	.cable_test_get_status	= at8031_cable_test_get_status,
++}, {
++	/* Qualcomm Atheros AR8032 */
++	PHY_ID_MATCH_EXACT(ATH8032_PHY_ID),
++	.name			= "Qualcomm Atheros AR8032",
++	.probe			= at803x_probe,
++	.flags			= PHY_POLL_CABLE_TEST,
++	.config_init		= at803x_config_init,
++	.link_change_notify	= at803x_link_change_notify,
++	.suspend		= at803x_suspend,
++	.resume			= at803x_resume,
++	/* PHY_BASIC_FEATURES */
++	.config_intr		= at803x_config_intr,
++	.handle_interrupt	= at803x_handle_interrupt,
++	.cable_test_start	= at803x_cable_test_start,
++	.cable_test_get_status	= at8032_cable_test_get_status,
++}, {
++	/* ATHEROS AR9331 */
++	PHY_ID_MATCH_EXACT(ATH9331_PHY_ID),
++	.name			= "Qualcomm Atheros AR9331 built-in PHY",
++	.probe			= at803x_probe,
++	.suspend		= at803x_suspend,
++	.resume			= at803x_resume,
++	.flags			= PHY_POLL_CABLE_TEST,
++	/* PHY_BASIC_FEATURES */
++	.config_intr		= at803x_config_intr,
++	.handle_interrupt	= at803x_handle_interrupt,
++	.cable_test_start	= at803x_cable_test_start,
++	.cable_test_get_status	= at8032_cable_test_get_status,
++	.read_status		= at803x_read_status,
++	.soft_reset		= genphy_soft_reset,
++	.config_aneg		= at803x_config_aneg,
++}, {
++	/* Qualcomm Atheros QCA9561 */
++	PHY_ID_MATCH_EXACT(QCA9561_PHY_ID),
++	.name			= "Qualcomm Atheros QCA9561 built-in PHY",
++	.probe			= at803x_probe,
++	.suspend		= at803x_suspend,
++	.resume			= at803x_resume,
++	.flags			= PHY_POLL_CABLE_TEST,
++	/* PHY_BASIC_FEATURES */
++	.config_intr		= at803x_config_intr,
++	.handle_interrupt	= at803x_handle_interrupt,
++	.cable_test_start	= at803x_cable_test_start,
++	.cable_test_get_status	= at8032_cable_test_get_status,
++	.read_status		= at803x_read_status,
++	.soft_reset		= genphy_soft_reset,
++	.config_aneg		= at803x_config_aneg,
++}, {
++	/* QCA8337 */
++	.phy_id			= QCA8337_PHY_ID,
++	.phy_id_mask		= QCA8K_PHY_ID_MASK,
++	.name			= "Qualcomm Atheros 8337 internal PHY",
++	/* PHY_GBIT_FEATURES */
++	.probe			= at803x_probe,
++	.flags			= PHY_IS_INTERNAL,
++	.config_init		= qca83xx_config_init,
++	.soft_reset		= genphy_soft_reset,
++	.get_sset_count		= qca83xx_get_sset_count,
++	.get_strings		= qca83xx_get_strings,
++	.get_stats		= qca83xx_get_stats,
++	.suspend		= qca8337_suspend,
++	.resume			= qca83xx_resume,
++}, {
++	/* QCA8327-A from switch QCA8327-AL1A */
++	.phy_id			= QCA8327_A_PHY_ID,
++	.phy_id_mask		= QCA8K_PHY_ID_MASK,
++	.name			= "Qualcomm Atheros 8327-A internal PHY",
++	/* PHY_GBIT_FEATURES */
++	.link_change_notify	= qca83xx_link_change_notify,
++	.probe			= at803x_probe,
++	.flags			= PHY_IS_INTERNAL,
++	.config_init		= qca8327_config_init,
++	.soft_reset		= genphy_soft_reset,
++	.get_sset_count		= qca83xx_get_sset_count,
++	.get_strings		= qca83xx_get_strings,
++	.get_stats		= qca83xx_get_stats,
++	.suspend		= qca8327_suspend,
++	.resume			= qca83xx_resume,
++}, {
++	/* QCA8327-B from switch QCA8327-BL1A */
++	.phy_id			= QCA8327_B_PHY_ID,
++	.phy_id_mask		= QCA8K_PHY_ID_MASK,
++	.name			= "Qualcomm Atheros 8327-B internal PHY",
++	/* PHY_GBIT_FEATURES */
++	.link_change_notify	= qca83xx_link_change_notify,
++	.probe			= at803x_probe,
++	.flags			= PHY_IS_INTERNAL,
++	.config_init		= qca8327_config_init,
++	.soft_reset		= genphy_soft_reset,
++	.get_sset_count		= qca83xx_get_sset_count,
++	.get_strings		= qca83xx_get_strings,
++	.get_stats		= qca83xx_get_stats,
++	.suspend		= qca8327_suspend,
++	.resume			= qca83xx_resume,
++}, {
++	/* Qualcomm QCA8081 */
++	PHY_ID_MATCH_EXACT(QCA8081_PHY_ID),
++	.name			= "Qualcomm QCA8081",
++	.flags			= PHY_POLL_CABLE_TEST,
++	.probe			= at803x_probe,
++	.config_intr		= at803x_config_intr,
++	.handle_interrupt	= at803x_handle_interrupt,
++	.get_tunable		= at803x_get_tunable,
++	.set_tunable		= at803x_set_tunable,
++	.set_wol		= at803x_set_wol,
++	.get_wol		= at803x_get_wol,
++	.get_features		= qca808x_get_features,
++	.config_aneg		= qca808x_config_aneg,
++	.suspend		= genphy_suspend,
++	.resume			= genphy_resume,
++	.read_status		= qca808x_read_status,
++	.config_init		= qca808x_config_init,
++	.soft_reset		= qca808x_soft_reset,
++	.cable_test_start	= qca808x_cable_test_start,
++	.cable_test_get_status	= qca808x_cable_test_get_status,
++	.link_change_notify	= qca808x_link_change_notify,
++	.led_brightness_set	= qca808x_led_brightness_set,
++	.led_blink_set		= qca808x_led_blink_set,
++	.led_hw_is_supported	= qca808x_led_hw_is_supported,
++	.led_hw_control_set	= qca808x_led_hw_control_set,
++	.led_hw_control_get	= qca808x_led_hw_control_get,
++	.led_polarity_set	= qca808x_led_polarity_set,
++}, };
++
++module_phy_driver(at803x_driver);
++
++static struct mdio_device_id __maybe_unused atheros_tbl[] = {
++	{ ATH8030_PHY_ID, AT8030_PHY_ID_MASK },
++	{ PHY_ID_MATCH_EXACT(ATH8031_PHY_ID) },
++	{ PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) },
++	{ PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) },
++	{ PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) },
++	{ PHY_ID_MATCH_EXACT(QCA8337_PHY_ID) },
++	{ PHY_ID_MATCH_EXACT(QCA8327_A_PHY_ID) },
++	{ PHY_ID_MATCH_EXACT(QCA8327_B_PHY_ID) },
++	{ PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) },
++	{ PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) },
++	{ }
++};
++
++MODULE_DEVICE_TABLE(mdio, atheros_tbl);
diff --git a/target/linux/generic/backport-6.1/713-v6.9-02-net-phy-qcom-create-and-move-functions-to-shared-lib.patch b/target/linux/generic/backport-6.1/713-v6.9-02-net-phy-qcom-create-and-move-functions-to-shared-lib.patch
new file mode 100644
index 00000000000000..7d0e1f4a285dea
--- /dev/null
+++ b/target/linux/generic/backport-6.1/713-v6.9-02-net-phy-qcom-create-and-move-functions-to-shared-lib.patch
@@ -0,0 +1,243 @@
+From 6fb760972c49490b03f3db2ad64cf30bdd28c54a Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Mon, 29 Jan 2024 15:15:20 +0100
+Subject: [PATCH 2/5] net: phy: qcom: create and move functions to shared
+ library
+
+Create and move functions to shared library in preparation for qca83xx
+PHY Family to be detached from at803x driver.
+
+Only the shared defines are moved to the shared qcom.h header.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://lore.kernel.org/r/20240129141600.2592-3-ansuelsmth@gmail.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/qcom/Kconfig        |  4 ++
+ drivers/net/phy/qcom/Makefile       |  1 +
+ drivers/net/phy/qcom/at803x.c       | 69 +----------------------------
+ drivers/net/phy/qcom/qcom-phy-lib.c | 53 ++++++++++++++++++++++
+ drivers/net/phy/qcom/qcom.h         | 34 ++++++++++++++
+ 5 files changed, 94 insertions(+), 67 deletions(-)
+ create mode 100644 drivers/net/phy/qcom/qcom-phy-lib.c
+ create mode 100644 drivers/net/phy/qcom/qcom.h
+
+--- a/drivers/net/phy/qcom/Kconfig
++++ b/drivers/net/phy/qcom/Kconfig
+@@ -1,6 +1,10 @@
+ # SPDX-License-Identifier: GPL-2.0-only
++config QCOM_NET_PHYLIB
++	tristate
++
+ config AT803X_PHY
+ 	tristate "Qualcomm Atheros AR803X PHYs and QCA833x PHYs"
++	select QCOM_NET_PHYLIB
+ 	depends on REGULATOR
+ 	help
+ 	  Currently supports the AR8030, AR8031, AR8033, AR8035 and internal
+--- a/drivers/net/phy/qcom/Makefile
++++ b/drivers/net/phy/qcom/Makefile
+@@ -1,2 +1,3 @@
+ # SPDX-License-Identifier: GPL-2.0
++obj-$(CONFIG_QCOM_NET_PHYLIB)	+= qcom-phy-lib.o
+ obj-$(CONFIG_AT803X_PHY)	+= at803x.o
+--- a/drivers/net/phy/qcom/at803x.c
++++ b/drivers/net/phy/qcom/at803x.c
+@@ -22,6 +22,8 @@
+ #include <linux/sfp.h>
+ #include <dt-bindings/net/qca-ar803x.h>
+ 
++#include "qcom.h"
++
+ #define AT803X_SPECIFIC_FUNCTION_CONTROL	0x10
+ #define AT803X_SFC_ASSERT_CRS			BIT(11)
+ #define AT803X_SFC_FORCE_LINK			BIT(10)
+@@ -84,9 +86,6 @@
+ #define AT803X_REG_CHIP_CONFIG			0x1f
+ #define AT803X_BT_BX_REG_SEL			0x8000
+ 
+-#define AT803X_DEBUG_ADDR			0x1D
+-#define AT803X_DEBUG_DATA			0x1E
+-
+ #define AT803X_MODE_CFG_MASK			0x0F
+ #define AT803X_MODE_CFG_BASET_RGMII		0x00
+ #define AT803X_MODE_CFG_BASET_SGMII		0x01
+@@ -103,19 +102,6 @@
+ #define AT803X_PSSR				0x11	/*PHY-Specific Status Register*/
+ #define AT803X_PSSR_MR_AN_COMPLETE		0x0200
+ 
+-#define AT803X_DEBUG_ANALOG_TEST_CTRL		0x00
+-#define QCA8327_DEBUG_MANU_CTRL_EN		BIT(2)
+-#define QCA8337_DEBUG_MANU_CTRL_EN		GENMASK(3, 2)
+-#define AT803X_DEBUG_RX_CLK_DLY_EN		BIT(15)
+-
+-#define AT803X_DEBUG_SYSTEM_CTRL_MODE		0x05
+-#define AT803X_DEBUG_TX_CLK_DLY_EN		BIT(8)
+-
+-#define AT803X_DEBUG_REG_HIB_CTRL		0x0b
+-#define   AT803X_DEBUG_HIB_CTRL_SEL_RST_80U	BIT(10)
+-#define   AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE	BIT(13)
+-#define   AT803X_DEBUG_HIB_CTRL_PS_HIB_EN	BIT(15)
+-
+ #define AT803X_DEBUG_REG_3C			0x3C
+ 
+ #define AT803X_DEBUG_REG_GREEN			0x3D
+@@ -393,18 +379,6 @@ MODULE_DESCRIPTION("Qualcomm Atheros AR8
+ MODULE_AUTHOR("Matus Ujhelyi");
+ MODULE_LICENSE("GPL");
+ 
+-enum stat_access_type {
+-	PHY,
+-	MMD
+-};
+-
+-struct at803x_hw_stat {
+-	const char *string;
+-	u8 reg;
+-	u32 mask;
+-	enum stat_access_type access_type;
+-};
+-
+ static struct at803x_hw_stat qca83xx_hw_stats[] = {
+ 	{ "phy_idle_errors", 0xa, GENMASK(7, 0), PHY},
+ 	{ "phy_receive_errors", 0x15, GENMASK(15, 0), PHY},
+@@ -439,45 +413,6 @@ struct at803x_context {
+ 	u16 led_control;
+ };
+ 
+-static int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data)
+-{
+-	int ret;
+-
+-	ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
+-	if (ret < 0)
+-		return ret;
+-
+-	return phy_write(phydev, AT803X_DEBUG_DATA, data);
+-}
+-
+-static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg)
+-{
+-	int ret;
+-
+-	ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
+-	if (ret < 0)
+-		return ret;
+-
+-	return phy_read(phydev, AT803X_DEBUG_DATA);
+-}
+-
+-static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
+-				 u16 clear, u16 set)
+-{
+-	u16 val;
+-	int ret;
+-
+-	ret = at803x_debug_reg_read(phydev, reg);
+-	if (ret < 0)
+-		return ret;
+-
+-	val = ret & 0xffff;
+-	val &= ~clear;
+-	val |= set;
+-
+-	return phy_write(phydev, AT803X_DEBUG_DATA, val);
+-}
+-
+ static int at803x_write_page(struct phy_device *phydev, int page)
+ {
+ 	int mask;
+--- /dev/null
++++ b/drivers/net/phy/qcom/qcom-phy-lib.c
+@@ -0,0 +1,53 @@
++// SPDX-License-Identifier: GPL-2.0
++
++#include <linux/phy.h>
++#include <linux/module.h>
++
++#include "qcom.h"
++
++MODULE_DESCRIPTION("Qualcomm PHY driver Common Functions");
++MODULE_AUTHOR("Matus Ujhelyi");
++MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
++MODULE_LICENSE("GPL");
++
++int at803x_debug_reg_read(struct phy_device *phydev, u16 reg)
++{
++	int ret;
++
++	ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
++	if (ret < 0)
++		return ret;
++
++	return phy_read(phydev, AT803X_DEBUG_DATA);
++}
++EXPORT_SYMBOL_GPL(at803x_debug_reg_read);
++
++int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
++			  u16 clear, u16 set)
++{
++	u16 val;
++	int ret;
++
++	ret = at803x_debug_reg_read(phydev, reg);
++	if (ret < 0)
++		return ret;
++
++	val = ret & 0xffff;
++	val &= ~clear;
++	val |= set;
++
++	return phy_write(phydev, AT803X_DEBUG_DATA, val);
++}
++EXPORT_SYMBOL_GPL(at803x_debug_reg_mask);
++
++int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data)
++{
++	int ret;
++
++	ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
++	if (ret < 0)
++		return ret;
++
++	return phy_write(phydev, AT803X_DEBUG_DATA, data);
++}
++EXPORT_SYMBOL_GPL(at803x_debug_reg_write);
+--- /dev/null
++++ b/drivers/net/phy/qcom/qcom.h
+@@ -0,0 +1,34 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++
++#define AT803X_DEBUG_ADDR			0x1D
++#define AT803X_DEBUG_DATA			0x1E
++
++#define AT803X_DEBUG_ANALOG_TEST_CTRL		0x00
++#define QCA8327_DEBUG_MANU_CTRL_EN		BIT(2)
++#define QCA8337_DEBUG_MANU_CTRL_EN		GENMASK(3, 2)
++#define AT803X_DEBUG_RX_CLK_DLY_EN		BIT(15)
++
++#define AT803X_DEBUG_SYSTEM_CTRL_MODE		0x05
++#define AT803X_DEBUG_TX_CLK_DLY_EN		BIT(8)
++
++#define AT803X_DEBUG_REG_HIB_CTRL		0x0b
++#define   AT803X_DEBUG_HIB_CTRL_SEL_RST_80U	BIT(10)
++#define   AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE	BIT(13)
++#define   AT803X_DEBUG_HIB_CTRL_PS_HIB_EN	BIT(15)
++
++enum stat_access_type {
++	PHY,
++	MMD
++};
++
++struct at803x_hw_stat {
++	const char *string;
++	u8 reg;
++	u32 mask;
++	enum stat_access_type access_type;
++};
++
++int at803x_debug_reg_read(struct phy_device *phydev, u16 reg);
++int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
++			  u16 clear, u16 set);
++int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data);
diff --git a/target/linux/generic/backport-6.1/713-v6.9-03-net-phy-qcom-deatch-qca83xx-PHY-driver-from-at803x.patch b/target/linux/generic/backport-6.1/713-v6.9-03-net-phy-qcom-deatch-qca83xx-PHY-driver-from-at803x.patch
new file mode 100644
index 00000000000000..6ac09dcb9ab922
--- /dev/null
+++ b/target/linux/generic/backport-6.1/713-v6.9-03-net-phy-qcom-deatch-qca83xx-PHY-driver-from-at803x.patch
@@ -0,0 +1,638 @@
+From 2e45d404d99d43bb7127b74b5dea8818df64996c Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Mon, 29 Jan 2024 15:15:21 +0100
+Subject: [PATCH 3/5] net: phy: qcom: deatch qca83xx PHY driver from at803x
+
+Deatch qca83xx PHY driver from at803x.
+
+The QCA83xx PHYs implement specific function and doesn't use generic
+at803x so it can be detached from the driver and moved to a dedicated
+one.
+
+Probe function and priv struct is reimplemented to allocate and use
+only the qca83xx specific data. Unused data from at803x PHY driver
+are dropped from at803x priv struct.
+
+This is to make slimmer PHY drivers instead of including lots of bloat
+that would never be used in specific SoC.
+
+A new Kconfig flag QCA83XX_PHY is introduced to compile the new
+introduced PHY driver.
+
+As the Kconfig name starts with Qualcomm the same order is kept.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://lore.kernel.org/r/20240129141600.2592-4-ansuelsmth@gmail.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/qcom/Kconfig   |  11 +-
+ drivers/net/phy/qcom/Makefile  |   1 +
+ drivers/net/phy/qcom/at803x.c  | 235 ----------------------------
+ drivers/net/phy/qcom/qca83xx.c | 275 +++++++++++++++++++++++++++++++++
+ 4 files changed, 284 insertions(+), 238 deletions(-)
+ create mode 100644 drivers/net/phy/qcom/qca83xx.c
+
+--- a/drivers/net/phy/qcom/Kconfig
++++ b/drivers/net/phy/qcom/Kconfig
+@@ -3,9 +3,14 @@ config QCOM_NET_PHYLIB
+ 	tristate
+ 
+ config AT803X_PHY
+-	tristate "Qualcomm Atheros AR803X PHYs and QCA833x PHYs"
++	tristate "Qualcomm Atheros AR803X PHYs"
+ 	select QCOM_NET_PHYLIB
+ 	depends on REGULATOR
+ 	help
+-	  Currently supports the AR8030, AR8031, AR8033, AR8035 and internal
+-	  QCA8337(Internal qca8k PHY) model
++	  Currently supports the AR8030, AR8031, AR8033, AR8035 model
++
++config QCA83XX_PHY
++	tristate "Qualcomm Atheros QCA833x PHYs"
++	select QCOM_NET_PHYLIB
++	help
++	  Currently supports the internal QCA8337(Internal qca8k PHY) model
+--- a/drivers/net/phy/qcom/Makefile
++++ b/drivers/net/phy/qcom/Makefile
+@@ -1,3 +1,4 @@
+ # SPDX-License-Identifier: GPL-2.0
+ obj-$(CONFIG_QCOM_NET_PHYLIB)	+= qcom-phy-lib.o
+ obj-$(CONFIG_AT803X_PHY)	+= at803x.o
++obj-$(CONFIG_QCA83XX_PHY)	+= qca83xx.o
+--- a/drivers/net/phy/qcom/at803x.c
++++ b/drivers/net/phy/qcom/at803x.c
+@@ -102,17 +102,10 @@
+ #define AT803X_PSSR				0x11	/*PHY-Specific Status Register*/
+ #define AT803X_PSSR_MR_AN_COMPLETE		0x0200
+ 
+-#define AT803X_DEBUG_REG_3C			0x3C
+-
+-#define AT803X_DEBUG_REG_GREEN			0x3D
+-#define   AT803X_DEBUG_GATE_CLK_IN1000		BIT(6)
+-
+ #define AT803X_DEBUG_REG_1F			0x1F
+ #define AT803X_DEBUG_PLL_ON			BIT(2)
+ #define AT803X_DEBUG_RGMII_1V8			BIT(3)
+ 
+-#define MDIO_AZ_DEBUG				0x800D
+-
+ /* AT803x supports either the XTAL input pad, an internal PLL or the
+  * DSP as clock reference for the clock output pad. The XTAL reference
+  * is only used for 25 MHz output, all other frequencies need the PLL.
+@@ -163,13 +156,7 @@
+ 
+ #define QCA8081_PHY_ID				0x004dd101
+ 
+-#define QCA8327_A_PHY_ID			0x004dd033
+-#define QCA8327_B_PHY_ID			0x004dd034
+-#define QCA8337_PHY_ID				0x004dd036
+ #define QCA9561_PHY_ID				0x004dd042
+-#define QCA8K_PHY_ID_MASK			0xffffffff
+-
+-#define QCA8K_DEVFLAGS_REVISION_MASK		GENMASK(2, 0)
+ 
+ #define AT803X_PAGE_FIBER			0
+ #define AT803X_PAGE_COPPER			1
+@@ -379,12 +366,6 @@ MODULE_DESCRIPTION("Qualcomm Atheros AR8
+ MODULE_AUTHOR("Matus Ujhelyi");
+ MODULE_LICENSE("GPL");
+ 
+-static struct at803x_hw_stat qca83xx_hw_stats[] = {
+-	{ "phy_idle_errors", 0xa, GENMASK(7, 0), PHY},
+-	{ "phy_receive_errors", 0x15, GENMASK(15, 0), PHY},
+-	{ "eee_wake_errors", 0x16, GENMASK(15, 0), MMD},
+-};
+-
+ struct at803x_ss_mask {
+ 	u16 speed_mask;
+ 	u8 speed_shift;
+@@ -400,7 +381,6 @@ struct at803x_priv {
+ 	bool is_1000basex;
+ 	struct regulator_dev *vddio_rdev;
+ 	struct regulator_dev *vddh_rdev;
+-	u64 stats[ARRAY_SIZE(qca83xx_hw_stats)];
+ 	int led_polarity_mode;
+ };
+ 
+@@ -564,53 +544,6 @@ static void at803x_get_wol(struct phy_de
+ 		wol->wolopts |= WAKE_MAGIC;
+ }
+ 
+-static int qca83xx_get_sset_count(struct phy_device *phydev)
+-{
+-	return ARRAY_SIZE(qca83xx_hw_stats);
+-}
+-
+-static void qca83xx_get_strings(struct phy_device *phydev, u8 *data)
+-{
+-	int i;
+-
+-	for (i = 0; i < ARRAY_SIZE(qca83xx_hw_stats); i++) {
+-		strscpy(data + i * ETH_GSTRING_LEN,
+-			qca83xx_hw_stats[i].string, ETH_GSTRING_LEN);
+-	}
+-}
+-
+-static u64 qca83xx_get_stat(struct phy_device *phydev, int i)
+-{
+-	struct at803x_hw_stat stat = qca83xx_hw_stats[i];
+-	struct at803x_priv *priv = phydev->priv;
+-	int val;
+-	u64 ret;
+-
+-	if (stat.access_type == MMD)
+-		val = phy_read_mmd(phydev, MDIO_MMD_PCS, stat.reg);
+-	else
+-		val = phy_read(phydev, stat.reg);
+-
+-	if (val < 0) {
+-		ret = U64_MAX;
+-	} else {
+-		val = val & stat.mask;
+-		priv->stats[i] += val;
+-		ret = priv->stats[i];
+-	}
+-
+-	return ret;
+-}
+-
+-static void qca83xx_get_stats(struct phy_device *phydev,
+-			      struct ethtool_stats *stats, u64 *data)
+-{
+-	int i;
+-
+-	for (i = 0; i < ARRAY_SIZE(qca83xx_hw_stats); i++)
+-		data[i] = qca83xx_get_stat(phydev, i);
+-}
+-
+ static int at803x_suspend(struct phy_device *phydev)
+ {
+ 	int value;
+@@ -1707,124 +1640,6 @@ static int at8035_probe(struct phy_devic
+ 	return at8035_parse_dt(phydev);
+ }
+ 
+-static int qca83xx_config_init(struct phy_device *phydev)
+-{
+-	u8 switch_revision;
+-
+-	switch_revision = phydev->dev_flags & QCA8K_DEVFLAGS_REVISION_MASK;
+-
+-	switch (switch_revision) {
+-	case 1:
+-		/* For 100M waveform */
+-		at803x_debug_reg_write(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0x02ea);
+-		/* Turn on Gigabit clock */
+-		at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x68a0);
+-		break;
+-
+-	case 2:
+-		phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0);
+-		fallthrough;
+-	case 4:
+-		phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f);
+-		at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x6860);
+-		at803x_debug_reg_write(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0x2c46);
+-		at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3C, 0x6000);
+-		break;
+-	}
+-
+-	/* Following original QCA sourcecode set port to prefer master */
+-	phy_set_bits(phydev, MII_CTRL1000, CTL1000_PREFER_MASTER);
+-
+-	return 0;
+-}
+-
+-static int qca8327_config_init(struct phy_device *phydev)
+-{
+-	/* QCA8327 require DAC amplitude adjustment for 100m set to +6%.
+-	 * Disable on init and enable only with 100m speed following
+-	 * qca original source code.
+-	 */
+-	at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
+-			      QCA8327_DEBUG_MANU_CTRL_EN, 0);
+-
+-	return qca83xx_config_init(phydev);
+-}
+-
+-static void qca83xx_link_change_notify(struct phy_device *phydev)
+-{
+-	/* Set DAC Amplitude adjustment to +6% for 100m on link running */
+-	if (phydev->state == PHY_RUNNING) {
+-		if (phydev->speed == SPEED_100)
+-			at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
+-					      QCA8327_DEBUG_MANU_CTRL_EN,
+-					      QCA8327_DEBUG_MANU_CTRL_EN);
+-	} else {
+-		/* Reset DAC Amplitude adjustment */
+-		at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
+-				      QCA8327_DEBUG_MANU_CTRL_EN, 0);
+-	}
+-}
+-
+-static int qca83xx_resume(struct phy_device *phydev)
+-{
+-	int ret, val;
+-
+-	/* Skip reset if not suspended */
+-	if (!phydev->suspended)
+-		return 0;
+-
+-	/* Reinit the port, reset values set by suspend */
+-	qca83xx_config_init(phydev);
+-
+-	/* Reset the port on port resume */
+-	phy_set_bits(phydev, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
+-
+-	/* On resume from suspend the switch execute a reset and
+-	 * restart auto-negotiation. Wait for reset to complete.
+-	 */
+-	ret = phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET),
+-				    50000, 600000, true);
+-	if (ret)
+-		return ret;
+-
+-	usleep_range(1000, 2000);
+-
+-	return 0;
+-}
+-
+-static int qca83xx_suspend(struct phy_device *phydev)
+-{
+-	at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_GREEN,
+-			      AT803X_DEBUG_GATE_CLK_IN1000, 0);
+-
+-	at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL,
+-			      AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE |
+-			      AT803X_DEBUG_HIB_CTRL_SEL_RST_80U, 0);
+-
+-	return 0;
+-}
+-
+-static int qca8337_suspend(struct phy_device *phydev)
+-{
+-	/* Only QCA8337 support actual suspend. */
+-	genphy_suspend(phydev);
+-
+-	return qca83xx_suspend(phydev);
+-}
+-
+-static int qca8327_suspend(struct phy_device *phydev)
+-{
+-	u16 mask = 0;
+-
+-	/* QCA8327 cause port unreliability when phy suspend
+-	 * is set.
+-	 */
+-	mask |= ~(BMCR_SPEED1000 | BMCR_FULLDPLX);
+-	phy_modify(phydev, MII_BMCR, mask, 0);
+-
+-	return qca83xx_suspend(phydev);
+-}
+-
+ static int qca808x_phy_fast_retrain_config(struct phy_device *phydev)
+ {
+ 	int ret;
+@@ -2599,53 +2414,6 @@ static struct phy_driver at803x_driver[]
+ 	.soft_reset		= genphy_soft_reset,
+ 	.config_aneg		= at803x_config_aneg,
+ }, {
+-	/* QCA8337 */
+-	.phy_id			= QCA8337_PHY_ID,
+-	.phy_id_mask		= QCA8K_PHY_ID_MASK,
+-	.name			= "Qualcomm Atheros 8337 internal PHY",
+-	/* PHY_GBIT_FEATURES */
+-	.probe			= at803x_probe,
+-	.flags			= PHY_IS_INTERNAL,
+-	.config_init		= qca83xx_config_init,
+-	.soft_reset		= genphy_soft_reset,
+-	.get_sset_count		= qca83xx_get_sset_count,
+-	.get_strings		= qca83xx_get_strings,
+-	.get_stats		= qca83xx_get_stats,
+-	.suspend		= qca8337_suspend,
+-	.resume			= qca83xx_resume,
+-}, {
+-	/* QCA8327-A from switch QCA8327-AL1A */
+-	.phy_id			= QCA8327_A_PHY_ID,
+-	.phy_id_mask		= QCA8K_PHY_ID_MASK,
+-	.name			= "Qualcomm Atheros 8327-A internal PHY",
+-	/* PHY_GBIT_FEATURES */
+-	.link_change_notify	= qca83xx_link_change_notify,
+-	.probe			= at803x_probe,
+-	.flags			= PHY_IS_INTERNAL,
+-	.config_init		= qca8327_config_init,
+-	.soft_reset		= genphy_soft_reset,
+-	.get_sset_count		= qca83xx_get_sset_count,
+-	.get_strings		= qca83xx_get_strings,
+-	.get_stats		= qca83xx_get_stats,
+-	.suspend		= qca8327_suspend,
+-	.resume			= qca83xx_resume,
+-}, {
+-	/* QCA8327-B from switch QCA8327-BL1A */
+-	.phy_id			= QCA8327_B_PHY_ID,
+-	.phy_id_mask		= QCA8K_PHY_ID_MASK,
+-	.name			= "Qualcomm Atheros 8327-B internal PHY",
+-	/* PHY_GBIT_FEATURES */
+-	.link_change_notify	= qca83xx_link_change_notify,
+-	.probe			= at803x_probe,
+-	.flags			= PHY_IS_INTERNAL,
+-	.config_init		= qca8327_config_init,
+-	.soft_reset		= genphy_soft_reset,
+-	.get_sset_count		= qca83xx_get_sset_count,
+-	.get_strings		= qca83xx_get_strings,
+-	.get_stats		= qca83xx_get_stats,
+-	.suspend		= qca8327_suspend,
+-	.resume			= qca83xx_resume,
+-}, {
+ 	/* Qualcomm QCA8081 */
+ 	PHY_ID_MATCH_EXACT(QCA8081_PHY_ID),
+ 	.name			= "Qualcomm QCA8081",
+@@ -2683,9 +2451,6 @@ static struct mdio_device_id __maybe_unu
+ 	{ PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) },
+ 	{ PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) },
+ 	{ PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) },
+-	{ PHY_ID_MATCH_EXACT(QCA8337_PHY_ID) },
+-	{ PHY_ID_MATCH_EXACT(QCA8327_A_PHY_ID) },
+-	{ PHY_ID_MATCH_EXACT(QCA8327_B_PHY_ID) },
+ 	{ PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) },
+ 	{ PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) },
+ 	{ }
+--- /dev/null
++++ b/drivers/net/phy/qcom/qca83xx.c
+@@ -0,0 +1,275 @@
++// SPDX-License-Identifier: GPL-2.0+
++
++#include <linux/phy.h>
++#include <linux/module.h>
++
++#include "qcom.h"
++
++#define AT803X_DEBUG_REG_3C			0x3C
++
++#define AT803X_DEBUG_REG_GREEN			0x3D
++#define   AT803X_DEBUG_GATE_CLK_IN1000		BIT(6)
++
++#define MDIO_AZ_DEBUG				0x800D
++
++#define QCA8327_A_PHY_ID			0x004dd033
++#define QCA8327_B_PHY_ID			0x004dd034
++#define QCA8337_PHY_ID				0x004dd036
++#define QCA8K_PHY_ID_MASK			0xffffffff
++
++#define QCA8K_DEVFLAGS_REVISION_MASK		GENMASK(2, 0)
++
++static struct at803x_hw_stat qca83xx_hw_stats[] = {
++	{ "phy_idle_errors", 0xa, GENMASK(7, 0), PHY},
++	{ "phy_receive_errors", 0x15, GENMASK(15, 0), PHY},
++	{ "eee_wake_errors", 0x16, GENMASK(15, 0), MMD},
++};
++
++struct qca83xx_priv {
++	u64 stats[ARRAY_SIZE(qca83xx_hw_stats)];
++};
++
++MODULE_DESCRIPTION("Qualcomm Atheros QCA83XX PHY driver");
++MODULE_AUTHOR("Matus Ujhelyi");
++MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
++MODULE_LICENSE("GPL");
++
++static int qca83xx_get_sset_count(struct phy_device *phydev)
++{
++	return ARRAY_SIZE(qca83xx_hw_stats);
++}
++
++static void qca83xx_get_strings(struct phy_device *phydev, u8 *data)
++{
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(qca83xx_hw_stats); i++) {
++		strscpy(data + i * ETH_GSTRING_LEN,
++			qca83xx_hw_stats[i].string, ETH_GSTRING_LEN);
++	}
++}
++
++static u64 qca83xx_get_stat(struct phy_device *phydev, int i)
++{
++	struct at803x_hw_stat stat = qca83xx_hw_stats[i];
++	struct qca83xx_priv *priv = phydev->priv;
++	int val;
++	u64 ret;
++
++	if (stat.access_type == MMD)
++		val = phy_read_mmd(phydev, MDIO_MMD_PCS, stat.reg);
++	else
++		val = phy_read(phydev, stat.reg);
++
++	if (val < 0) {
++		ret = U64_MAX;
++	} else {
++		val = val & stat.mask;
++		priv->stats[i] += val;
++		ret = priv->stats[i];
++	}
++
++	return ret;
++}
++
++static void qca83xx_get_stats(struct phy_device *phydev,
++			      struct ethtool_stats *stats, u64 *data)
++{
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(qca83xx_hw_stats); i++)
++		data[i] = qca83xx_get_stat(phydev, i);
++}
++
++static int qca83xx_probe(struct phy_device *phydev)
++{
++	struct device *dev = &phydev->mdio.dev;
++	struct qca83xx_priv *priv;
++
++	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
++	if (!priv)
++		return -ENOMEM;
++
++	phydev->priv = priv;
++
++	return 0;
++}
++
++static int qca83xx_config_init(struct phy_device *phydev)
++{
++	u8 switch_revision;
++
++	switch_revision = phydev->dev_flags & QCA8K_DEVFLAGS_REVISION_MASK;
++
++	switch (switch_revision) {
++	case 1:
++		/* For 100M waveform */
++		at803x_debug_reg_write(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0x02ea);
++		/* Turn on Gigabit clock */
++		at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x68a0);
++		break;
++
++	case 2:
++		phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0);
++		fallthrough;
++	case 4:
++		phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f);
++		at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x6860);
++		at803x_debug_reg_write(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0x2c46);
++		at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3C, 0x6000);
++		break;
++	}
++
++	/* Following original QCA sourcecode set port to prefer master */
++	phy_set_bits(phydev, MII_CTRL1000, CTL1000_PREFER_MASTER);
++
++	return 0;
++}
++
++static int qca8327_config_init(struct phy_device *phydev)
++{
++	/* QCA8327 require DAC amplitude adjustment for 100m set to +6%.
++	 * Disable on init and enable only with 100m speed following
++	 * qca original source code.
++	 */
++	at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
++			      QCA8327_DEBUG_MANU_CTRL_EN, 0);
++
++	return qca83xx_config_init(phydev);
++}
++
++static void qca83xx_link_change_notify(struct phy_device *phydev)
++{
++	/* Set DAC Amplitude adjustment to +6% for 100m on link running */
++	if (phydev->state == PHY_RUNNING) {
++		if (phydev->speed == SPEED_100)
++			at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
++					      QCA8327_DEBUG_MANU_CTRL_EN,
++					      QCA8327_DEBUG_MANU_CTRL_EN);
++	} else {
++		/* Reset DAC Amplitude adjustment */
++		at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
++				      QCA8327_DEBUG_MANU_CTRL_EN, 0);
++	}
++}
++
++static int qca83xx_resume(struct phy_device *phydev)
++{
++	int ret, val;
++
++	/* Skip reset if not suspended */
++	if (!phydev->suspended)
++		return 0;
++
++	/* Reinit the port, reset values set by suspend */
++	qca83xx_config_init(phydev);
++
++	/* Reset the port on port resume */
++	phy_set_bits(phydev, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
++
++	/* On resume from suspend the switch execute a reset and
++	 * restart auto-negotiation. Wait for reset to complete.
++	 */
++	ret = phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET),
++				    50000, 600000, true);
++	if (ret)
++		return ret;
++
++	usleep_range(1000, 2000);
++
++	return 0;
++}
++
++static int qca83xx_suspend(struct phy_device *phydev)
++{
++	at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_GREEN,
++			      AT803X_DEBUG_GATE_CLK_IN1000, 0);
++
++	at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL,
++			      AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE |
++			      AT803X_DEBUG_HIB_CTRL_SEL_RST_80U, 0);
++
++	return 0;
++}
++
++static int qca8337_suspend(struct phy_device *phydev)
++{
++	/* Only QCA8337 support actual suspend. */
++	genphy_suspend(phydev);
++
++	return qca83xx_suspend(phydev);
++}
++
++static int qca8327_suspend(struct phy_device *phydev)
++{
++	u16 mask = 0;
++
++	/* QCA8327 cause port unreliability when phy suspend
++	 * is set.
++	 */
++	mask |= ~(BMCR_SPEED1000 | BMCR_FULLDPLX);
++	phy_modify(phydev, MII_BMCR, mask, 0);
++
++	return qca83xx_suspend(phydev);
++}
++
++static struct phy_driver qca83xx_driver[] = {
++{
++	/* QCA8337 */
++	.phy_id			= QCA8337_PHY_ID,
++	.phy_id_mask		= QCA8K_PHY_ID_MASK,
++	.name			= "Qualcomm Atheros 8337 internal PHY",
++	/* PHY_GBIT_FEATURES */
++	.probe			= qca83xx_probe,
++	.flags			= PHY_IS_INTERNAL,
++	.config_init		= qca83xx_config_init,
++	.soft_reset		= genphy_soft_reset,
++	.get_sset_count		= qca83xx_get_sset_count,
++	.get_strings		= qca83xx_get_strings,
++	.get_stats		= qca83xx_get_stats,
++	.suspend		= qca8337_suspend,
++	.resume			= qca83xx_resume,
++}, {
++	/* QCA8327-A from switch QCA8327-AL1A */
++	.phy_id			= QCA8327_A_PHY_ID,
++	.phy_id_mask		= QCA8K_PHY_ID_MASK,
++	.name			= "Qualcomm Atheros 8327-A internal PHY",
++	/* PHY_GBIT_FEATURES */
++	.link_change_notify	= qca83xx_link_change_notify,
++	.probe			= qca83xx_probe,
++	.flags			= PHY_IS_INTERNAL,
++	.config_init		= qca8327_config_init,
++	.soft_reset		= genphy_soft_reset,
++	.get_sset_count		= qca83xx_get_sset_count,
++	.get_strings		= qca83xx_get_strings,
++	.get_stats		= qca83xx_get_stats,
++	.suspend		= qca8327_suspend,
++	.resume			= qca83xx_resume,
++}, {
++	/* QCA8327-B from switch QCA8327-BL1A */
++	.phy_id			= QCA8327_B_PHY_ID,
++	.phy_id_mask		= QCA8K_PHY_ID_MASK,
++	.name			= "Qualcomm Atheros 8327-B internal PHY",
++	/* PHY_GBIT_FEATURES */
++	.link_change_notify	= qca83xx_link_change_notify,
++	.probe			= qca83xx_probe,
++	.flags			= PHY_IS_INTERNAL,
++	.config_init		= qca8327_config_init,
++	.soft_reset		= genphy_soft_reset,
++	.get_sset_count		= qca83xx_get_sset_count,
++	.get_strings		= qca83xx_get_strings,
++	.get_stats		= qca83xx_get_stats,
++	.suspend		= qca8327_suspend,
++	.resume			= qca83xx_resume,
++}, };
++
++module_phy_driver(qca83xx_driver);
++
++static struct mdio_device_id __maybe_unused qca83xx_tbl[] = {
++	{ PHY_ID_MATCH_EXACT(QCA8337_PHY_ID) },
++	{ PHY_ID_MATCH_EXACT(QCA8327_A_PHY_ID) },
++	{ PHY_ID_MATCH_EXACT(QCA8327_B_PHY_ID) },
++	{ }
++};
++
++MODULE_DEVICE_TABLE(mdio, qca83xx_tbl);
diff --git a/target/linux/generic/backport-6.1/713-v6.9-04-net-phy-qcom-move-additional-functions-to-shared-lib.patch b/target/linux/generic/backport-6.1/713-v6.9-04-net-phy-qcom-move-additional-functions-to-shared-lib.patch
new file mode 100644
index 00000000000000..9c43ad13b4434f
--- /dev/null
+++ b/target/linux/generic/backport-6.1/713-v6.9-04-net-phy-qcom-move-additional-functions-to-shared-lib.patch
@@ -0,0 +1,1014 @@
+From 249d2b80e4db0e38503ed0ec2af6c7401bc099b9 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Mon, 29 Jan 2024 15:15:22 +0100
+Subject: [PATCH 4/5] net: phy: qcom: move additional functions to shared
+ library
+
+Move additional functions to shared library in preparation for qca808x
+PHY Family to be detached from at803x driver.
+
+Only the shared defines are moved to the shared qcom.h header.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://lore.kernel.org/r/20240129141600.2592-5-ansuelsmth@gmail.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/qcom/at803x.c       | 426 +---------------------------
+ drivers/net/phy/qcom/qcom-phy-lib.c | 376 ++++++++++++++++++++++++
+ drivers/net/phy/qcom/qcom.h         |  86 ++++++
+ 3 files changed, 463 insertions(+), 425 deletions(-)
+
+--- a/drivers/net/phy/qcom/at803x.c
++++ b/drivers/net/phy/qcom/at803x.c
+@@ -24,65 +24,11 @@
+ 
+ #include "qcom.h"
+ 
+-#define AT803X_SPECIFIC_FUNCTION_CONTROL	0x10
+-#define AT803X_SFC_ASSERT_CRS			BIT(11)
+-#define AT803X_SFC_FORCE_LINK			BIT(10)
+-#define AT803X_SFC_MDI_CROSSOVER_MODE_M		GENMASK(6, 5)
+-#define AT803X_SFC_AUTOMATIC_CROSSOVER		0x3
+-#define AT803X_SFC_MANUAL_MDIX			0x1
+-#define AT803X_SFC_MANUAL_MDI			0x0
+-#define AT803X_SFC_SQE_TEST			BIT(2)
+-#define AT803X_SFC_POLARITY_REVERSAL		BIT(1)
+-#define AT803X_SFC_DISABLE_JABBER		BIT(0)
+-
+-#define AT803X_SPECIFIC_STATUS			0x11
+-#define AT803X_SS_SPEED_MASK			GENMASK(15, 14)
+-#define AT803X_SS_SPEED_1000			2
+-#define AT803X_SS_SPEED_100			1
+-#define AT803X_SS_SPEED_10			0
+-#define AT803X_SS_DUPLEX			BIT(13)
+-#define AT803X_SS_SPEED_DUPLEX_RESOLVED		BIT(11)
+-#define AT803X_SS_MDIX				BIT(6)
+-
+-#define QCA808X_SS_SPEED_MASK			GENMASK(9, 7)
+-#define QCA808X_SS_SPEED_2500			4
+-
+-#define AT803X_INTR_ENABLE			0x12
+-#define AT803X_INTR_ENABLE_AUTONEG_ERR		BIT(15)
+-#define AT803X_INTR_ENABLE_SPEED_CHANGED	BIT(14)
+-#define AT803X_INTR_ENABLE_DUPLEX_CHANGED	BIT(13)
+-#define AT803X_INTR_ENABLE_PAGE_RECEIVED	BIT(12)
+-#define AT803X_INTR_ENABLE_LINK_FAIL		BIT(11)
+-#define AT803X_INTR_ENABLE_LINK_SUCCESS		BIT(10)
+-#define AT803X_INTR_ENABLE_LINK_FAIL_BX		BIT(8)
+-#define AT803X_INTR_ENABLE_LINK_SUCCESS_BX	BIT(7)
+-#define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE	BIT(5)
+-#define AT803X_INTR_ENABLE_POLARITY_CHANGED	BIT(1)
+-#define AT803X_INTR_ENABLE_WOL			BIT(0)
+-
+-#define AT803X_INTR_STATUS			0x13
+-
+-#define AT803X_SMART_SPEED			0x14
+-#define AT803X_SMART_SPEED_ENABLE		BIT(5)
+-#define AT803X_SMART_SPEED_RETRY_LIMIT_MASK	GENMASK(4, 2)
+-#define AT803X_SMART_SPEED_BYPASS_TIMER		BIT(1)
+-#define AT803X_CDT				0x16
+-#define AT803X_CDT_MDI_PAIR_MASK		GENMASK(9, 8)
+-#define AT803X_CDT_ENABLE_TEST			BIT(0)
+-#define AT803X_CDT_STATUS			0x1c
+-#define AT803X_CDT_STATUS_STAT_NORMAL		0
+-#define AT803X_CDT_STATUS_STAT_SHORT		1
+-#define AT803X_CDT_STATUS_STAT_OPEN		2
+-#define AT803X_CDT_STATUS_STAT_FAIL		3
+-#define AT803X_CDT_STATUS_STAT_MASK		GENMASK(9, 8)
+-#define AT803X_CDT_STATUS_DELTA_TIME_MASK	GENMASK(7, 0)
+ #define AT803X_LED_CONTROL			0x18
+ 
+ #define AT803X_PHY_MMD3_WOL_CTRL		0x8012
+ #define AT803X_WOL_EN				BIT(5)
+-#define AT803X_LOC_MAC_ADDR_0_15_OFFSET		0x804C
+-#define AT803X_LOC_MAC_ADDR_16_31_OFFSET	0x804B
+-#define AT803X_LOC_MAC_ADDR_32_47_OFFSET	0x804A
++
+ #define AT803X_REG_CHIP_CONFIG			0x1f
+ #define AT803X_BT_BX_REG_SEL			0x8000
+ 
+@@ -138,10 +84,6 @@
+ #define AT803X_CLK_OUT_STRENGTH_HALF		1
+ #define AT803X_CLK_OUT_STRENGTH_QUARTER		2
+ 
+-#define AT803X_DEFAULT_DOWNSHIFT		5
+-#define AT803X_MIN_DOWNSHIFT			2
+-#define AT803X_MAX_DOWNSHIFT			9
+-
+ #define AT803X_MMD3_SMARTEEE_CTL1		0x805b
+ #define AT803X_MMD3_SMARTEEE_CTL2		0x805c
+ #define AT803X_MMD3_SMARTEEE_CTL3		0x805d
+@@ -366,11 +308,6 @@ MODULE_DESCRIPTION("Qualcomm Atheros AR8
+ MODULE_AUTHOR("Matus Ujhelyi");
+ MODULE_LICENSE("GPL");
+ 
+-struct at803x_ss_mask {
+-	u16 speed_mask;
+-	u8 speed_shift;
+-};
+-
+ struct at803x_priv {
+ 	int flags;
+ 	u16 clk_25m_reg;
+@@ -470,80 +407,6 @@ static void at803x_context_restore(struc
+ 	phy_write(phydev, AT803X_LED_CONTROL, context->led_control);
+ }
+ 
+-static int at803x_set_wol(struct phy_device *phydev,
+-			  struct ethtool_wolinfo *wol)
+-{
+-	int ret, irq_enabled;
+-
+-	if (wol->wolopts & WAKE_MAGIC) {
+-		struct net_device *ndev = phydev->attached_dev;
+-		const u8 *mac;
+-		unsigned int i;
+-		static const unsigned int offsets[] = {
+-			AT803X_LOC_MAC_ADDR_32_47_OFFSET,
+-			AT803X_LOC_MAC_ADDR_16_31_OFFSET,
+-			AT803X_LOC_MAC_ADDR_0_15_OFFSET,
+-		};
+-
+-		if (!ndev)
+-			return -ENODEV;
+-
+-		mac = (const u8 *)ndev->dev_addr;
+-
+-		if (!is_valid_ether_addr(mac))
+-			return -EINVAL;
+-
+-		for (i = 0; i < 3; i++)
+-			phy_write_mmd(phydev, MDIO_MMD_PCS, offsets[i],
+-				      mac[(i * 2) + 1] | (mac[(i * 2)] << 8));
+-
+-		/* Enable WOL interrupt */
+-		ret = phy_modify(phydev, AT803X_INTR_ENABLE, 0, AT803X_INTR_ENABLE_WOL);
+-		if (ret)
+-			return ret;
+-	} else {
+-		/* Disable WOL interrupt */
+-		ret = phy_modify(phydev, AT803X_INTR_ENABLE, AT803X_INTR_ENABLE_WOL, 0);
+-		if (ret)
+-			return ret;
+-	}
+-
+-	/* Clear WOL status */
+-	ret = phy_read(phydev, AT803X_INTR_STATUS);
+-	if (ret < 0)
+-		return ret;
+-
+-	/* Check if there are other interrupts except for WOL triggered when PHY is
+-	 * in interrupt mode, only the interrupts enabled by AT803X_INTR_ENABLE can
+-	 * be passed up to the interrupt PIN.
+-	 */
+-	irq_enabled = phy_read(phydev, AT803X_INTR_ENABLE);
+-	if (irq_enabled < 0)
+-		return irq_enabled;
+-
+-	irq_enabled &= ~AT803X_INTR_ENABLE_WOL;
+-	if (ret & irq_enabled && !phy_polling_mode(phydev))
+-		phy_trigger_machine(phydev);
+-
+-	return 0;
+-}
+-
+-static void at803x_get_wol(struct phy_device *phydev,
+-			   struct ethtool_wolinfo *wol)
+-{
+-	int value;
+-
+-	wol->supported = WAKE_MAGIC;
+-	wol->wolopts = 0;
+-
+-	value = phy_read(phydev, AT803X_INTR_ENABLE);
+-	if (value < 0)
+-		return;
+-
+-	if (value & AT803X_INTR_ENABLE_WOL)
+-		wol->wolopts |= WAKE_MAGIC;
+-}
+-
+ static int at803x_suspend(struct phy_device *phydev)
+ {
+ 	int value;
+@@ -816,73 +679,6 @@ static int at803x_config_init(struct phy
+ 	return phy_modify(phydev, MII_ADVERTISE, MDIO_AN_CTRL1_XNP, 0);
+ }
+ 
+-static int at803x_ack_interrupt(struct phy_device *phydev)
+-{
+-	int err;
+-
+-	err = phy_read(phydev, AT803X_INTR_STATUS);
+-
+-	return (err < 0) ? err : 0;
+-}
+-
+-static int at803x_config_intr(struct phy_device *phydev)
+-{
+-	int err;
+-	int value;
+-
+-	value = phy_read(phydev, AT803X_INTR_ENABLE);
+-
+-	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
+-		/* Clear any pending interrupts */
+-		err = at803x_ack_interrupt(phydev);
+-		if (err)
+-			return err;
+-
+-		value |= AT803X_INTR_ENABLE_AUTONEG_ERR;
+-		value |= AT803X_INTR_ENABLE_SPEED_CHANGED;
+-		value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED;
+-		value |= AT803X_INTR_ENABLE_LINK_FAIL;
+-		value |= AT803X_INTR_ENABLE_LINK_SUCCESS;
+-
+-		err = phy_write(phydev, AT803X_INTR_ENABLE, value);
+-	} else {
+-		err = phy_write(phydev, AT803X_INTR_ENABLE, 0);
+-		if (err)
+-			return err;
+-
+-		/* Clear any pending interrupts */
+-		err = at803x_ack_interrupt(phydev);
+-	}
+-
+-	return err;
+-}
+-
+-static irqreturn_t at803x_handle_interrupt(struct phy_device *phydev)
+-{
+-	int irq_status, int_enabled;
+-
+-	irq_status = phy_read(phydev, AT803X_INTR_STATUS);
+-	if (irq_status < 0) {
+-		phy_error(phydev);
+-		return IRQ_NONE;
+-	}
+-
+-	/* Read the current enabled interrupts */
+-	int_enabled = phy_read(phydev, AT803X_INTR_ENABLE);
+-	if (int_enabled < 0) {
+-		phy_error(phydev);
+-		return IRQ_NONE;
+-	}
+-
+-	/* See if this was one of our enabled interrupts */
+-	if (!(irq_status & int_enabled))
+-		return IRQ_NONE;
+-
+-	phy_trigger_machine(phydev);
+-
+-	return IRQ_HANDLED;
+-}
+-
+ static void at803x_link_change_notify(struct phy_device *phydev)
+ {
+ 	/*
+@@ -908,69 +704,6 @@ static void at803x_link_change_notify(st
+ 	}
+ }
+ 
+-static int at803x_read_specific_status(struct phy_device *phydev,
+-				       struct at803x_ss_mask ss_mask)
+-{
+-	int ss;
+-
+-	/* Read the AT8035 PHY-Specific Status register, which indicates the
+-	 * speed and duplex that the PHY is actually using, irrespective of
+-	 * whether we are in autoneg mode or not.
+-	 */
+-	ss = phy_read(phydev, AT803X_SPECIFIC_STATUS);
+-	if (ss < 0)
+-		return ss;
+-
+-	if (ss & AT803X_SS_SPEED_DUPLEX_RESOLVED) {
+-		int sfc, speed;
+-
+-		sfc = phy_read(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL);
+-		if (sfc < 0)
+-			return sfc;
+-
+-		speed = ss & ss_mask.speed_mask;
+-		speed >>= ss_mask.speed_shift;
+-
+-		switch (speed) {
+-		case AT803X_SS_SPEED_10:
+-			phydev->speed = SPEED_10;
+-			break;
+-		case AT803X_SS_SPEED_100:
+-			phydev->speed = SPEED_100;
+-			break;
+-		case AT803X_SS_SPEED_1000:
+-			phydev->speed = SPEED_1000;
+-			break;
+-		case QCA808X_SS_SPEED_2500:
+-			phydev->speed = SPEED_2500;
+-			break;
+-		}
+-		if (ss & AT803X_SS_DUPLEX)
+-			phydev->duplex = DUPLEX_FULL;
+-		else
+-			phydev->duplex = DUPLEX_HALF;
+-
+-		if (ss & AT803X_SS_MDIX)
+-			phydev->mdix = ETH_TP_MDI_X;
+-		else
+-			phydev->mdix = ETH_TP_MDI;
+-
+-		switch (FIELD_GET(AT803X_SFC_MDI_CROSSOVER_MODE_M, sfc)) {
+-		case AT803X_SFC_MANUAL_MDI:
+-			phydev->mdix_ctrl = ETH_TP_MDI;
+-			break;
+-		case AT803X_SFC_MANUAL_MDIX:
+-			phydev->mdix_ctrl = ETH_TP_MDI_X;
+-			break;
+-		case AT803X_SFC_AUTOMATIC_CROSSOVER:
+-			phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
+-			break;
+-		}
+-	}
+-
+-	return 0;
+-}
+-
+ static int at803x_read_status(struct phy_device *phydev)
+ {
+ 	struct at803x_ss_mask ss_mask = { 0 };
+@@ -1006,50 +739,6 @@ static int at803x_read_status(struct phy
+ 	return 0;
+ }
+ 
+-static int at803x_config_mdix(struct phy_device *phydev, u8 ctrl)
+-{
+-	u16 val;
+-
+-	switch (ctrl) {
+-	case ETH_TP_MDI:
+-		val = AT803X_SFC_MANUAL_MDI;
+-		break;
+-	case ETH_TP_MDI_X:
+-		val = AT803X_SFC_MANUAL_MDIX;
+-		break;
+-	case ETH_TP_MDI_AUTO:
+-		val = AT803X_SFC_AUTOMATIC_CROSSOVER;
+-		break;
+-	default:
+-		return 0;
+-	}
+-
+-	return phy_modify_changed(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL,
+-			  AT803X_SFC_MDI_CROSSOVER_MODE_M,
+-			  FIELD_PREP(AT803X_SFC_MDI_CROSSOVER_MODE_M, val));
+-}
+-
+-static int at803x_prepare_config_aneg(struct phy_device *phydev)
+-{
+-	int ret;
+-
+-	ret = at803x_config_mdix(phydev, phydev->mdix_ctrl);
+-	if (ret < 0)
+-		return ret;
+-
+-	/* Changes of the midx bits are disruptive to the normal operation;
+-	 * therefore any changes to these registers must be followed by a
+-	 * software reset to take effect.
+-	 */
+-	if (ret == 1) {
+-		ret = genphy_soft_reset(phydev);
+-		if (ret < 0)
+-			return ret;
+-	}
+-
+-	return 0;
+-}
+-
+ static int at803x_config_aneg(struct phy_device *phydev)
+ {
+ 	struct at803x_priv *priv = phydev->priv;
+@@ -1065,80 +754,6 @@ static int at803x_config_aneg(struct phy
+ 	return genphy_config_aneg(phydev);
+ }
+ 
+-static int at803x_get_downshift(struct phy_device *phydev, u8 *d)
+-{
+-	int val;
+-
+-	val = phy_read(phydev, AT803X_SMART_SPEED);
+-	if (val < 0)
+-		return val;
+-
+-	if (val & AT803X_SMART_SPEED_ENABLE)
+-		*d = FIELD_GET(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, val) + 2;
+-	else
+-		*d = DOWNSHIFT_DEV_DISABLE;
+-
+-	return 0;
+-}
+-
+-static int at803x_set_downshift(struct phy_device *phydev, u8 cnt)
+-{
+-	u16 mask, set;
+-	int ret;
+-
+-	switch (cnt) {
+-	case DOWNSHIFT_DEV_DEFAULT_COUNT:
+-		cnt = AT803X_DEFAULT_DOWNSHIFT;
+-		fallthrough;
+-	case AT803X_MIN_DOWNSHIFT ... AT803X_MAX_DOWNSHIFT:
+-		set = AT803X_SMART_SPEED_ENABLE |
+-		      AT803X_SMART_SPEED_BYPASS_TIMER |
+-		      FIELD_PREP(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, cnt - 2);
+-		mask = AT803X_SMART_SPEED_RETRY_LIMIT_MASK;
+-		break;
+-	case DOWNSHIFT_DEV_DISABLE:
+-		set = 0;
+-		mask = AT803X_SMART_SPEED_ENABLE |
+-		       AT803X_SMART_SPEED_BYPASS_TIMER;
+-		break;
+-	default:
+-		return -EINVAL;
+-	}
+-
+-	ret = phy_modify_changed(phydev, AT803X_SMART_SPEED, mask, set);
+-
+-	/* After changing the smart speed settings, we need to perform a
+-	 * software reset, use phy_init_hw() to make sure we set the
+-	 * reapply any values which might got lost during software reset.
+-	 */
+-	if (ret == 1)
+-		ret = phy_init_hw(phydev);
+-
+-	return ret;
+-}
+-
+-static int at803x_get_tunable(struct phy_device *phydev,
+-			      struct ethtool_tunable *tuna, void *data)
+-{
+-	switch (tuna->id) {
+-	case ETHTOOL_PHY_DOWNSHIFT:
+-		return at803x_get_downshift(phydev, data);
+-	default:
+-		return -EOPNOTSUPP;
+-	}
+-}
+-
+-static int at803x_set_tunable(struct phy_device *phydev,
+-			      struct ethtool_tunable *tuna, const void *data)
+-{
+-	switch (tuna->id) {
+-	case ETHTOOL_PHY_DOWNSHIFT:
+-		return at803x_set_downshift(phydev, *(const u8 *)data);
+-	default:
+-		return -EOPNOTSUPP;
+-	}
+-}
+-
+ static int at803x_cable_test_result_trans(u16 status)
+ {
+ 	switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) {
+@@ -1170,45 +785,6 @@ static bool at803x_cdt_fault_length_vali
+ 	return false;
+ }
+ 
+-static int at803x_cdt_fault_length(int dt)
+-{
+-	/* According to the datasheet the distance to the fault is
+-	 * DELTA_TIME * 0.824 meters.
+-	 *
+-	 * The author suspect the correct formula is:
+-	 *
+-	 *   fault_distance = DELTA_TIME * (c * VF) / 125MHz / 2
+-	 *
+-	 * where c is the speed of light, VF is the velocity factor of
+-	 * the twisted pair cable, 125MHz the counter frequency and
+-	 * we need to divide by 2 because the hardware will measure the
+-	 * round trip time to the fault and back to the PHY.
+-	 *
+-	 * With a VF of 0.69 we get the factor 0.824 mentioned in the
+-	 * datasheet.
+-	 */
+-	return (dt * 824) / 10;
+-}
+-
+-static int at803x_cdt_start(struct phy_device *phydev,
+-			    u32 cdt_start)
+-{
+-	return phy_write(phydev, AT803X_CDT, cdt_start);
+-}
+-
+-static int at803x_cdt_wait_for_completion(struct phy_device *phydev,
+-					  u32 cdt_en)
+-{
+-	int val, ret;
+-
+-	/* One test run takes about 25ms */
+-	ret = phy_read_poll_timeout(phydev, AT803X_CDT, val,
+-				    !(val & cdt_en),
+-				    30000, 100000, true);
+-
+-	return ret < 0 ? ret : 0;
+-}
+-
+ static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair)
+ {
+ 	static const int ethtool_pair[] = {
+--- a/drivers/net/phy/qcom/qcom-phy-lib.c
++++ b/drivers/net/phy/qcom/qcom-phy-lib.c
+@@ -3,6 +3,9 @@
+ #include <linux/phy.h>
+ #include <linux/module.h>
+ 
++#include <linux/netdevice.h>
++#include <linux/etherdevice.h>
++
+ #include "qcom.h"
+ 
+ MODULE_DESCRIPTION("Qualcomm PHY driver Common Functions");
+@@ -51,3 +54,376 @@ int at803x_debug_reg_write(struct phy_de
+ 	return phy_write(phydev, AT803X_DEBUG_DATA, data);
+ }
+ EXPORT_SYMBOL_GPL(at803x_debug_reg_write);
++
++int at803x_set_wol(struct phy_device *phydev,
++		   struct ethtool_wolinfo *wol)
++{
++	int ret, irq_enabled;
++
++	if (wol->wolopts & WAKE_MAGIC) {
++		struct net_device *ndev = phydev->attached_dev;
++		const u8 *mac;
++		unsigned int i;
++		static const unsigned int offsets[] = {
++			AT803X_LOC_MAC_ADDR_32_47_OFFSET,
++			AT803X_LOC_MAC_ADDR_16_31_OFFSET,
++			AT803X_LOC_MAC_ADDR_0_15_OFFSET,
++		};
++
++		if (!ndev)
++			return -ENODEV;
++
++		mac = (const u8 *)ndev->dev_addr;
++
++		if (!is_valid_ether_addr(mac))
++			return -EINVAL;
++
++		for (i = 0; i < 3; i++)
++			phy_write_mmd(phydev, MDIO_MMD_PCS, offsets[i],
++				      mac[(i * 2) + 1] | (mac[(i * 2)] << 8));
++
++		/* Enable WOL interrupt */
++		ret = phy_modify(phydev, AT803X_INTR_ENABLE, 0, AT803X_INTR_ENABLE_WOL);
++		if (ret)
++			return ret;
++	} else {
++		/* Disable WOL interrupt */
++		ret = phy_modify(phydev, AT803X_INTR_ENABLE, AT803X_INTR_ENABLE_WOL, 0);
++		if (ret)
++			return ret;
++	}
++
++	/* Clear WOL status */
++	ret = phy_read(phydev, AT803X_INTR_STATUS);
++	if (ret < 0)
++		return ret;
++
++	/* Check if there are other interrupts except for WOL triggered when PHY is
++	 * in interrupt mode, only the interrupts enabled by AT803X_INTR_ENABLE can
++	 * be passed up to the interrupt PIN.
++	 */
++	irq_enabled = phy_read(phydev, AT803X_INTR_ENABLE);
++	if (irq_enabled < 0)
++		return irq_enabled;
++
++	irq_enabled &= ~AT803X_INTR_ENABLE_WOL;
++	if (ret & irq_enabled && !phy_polling_mode(phydev))
++		phy_trigger_machine(phydev);
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(at803x_set_wol);
++
++void at803x_get_wol(struct phy_device *phydev,
++		    struct ethtool_wolinfo *wol)
++{
++	int value;
++
++	wol->supported = WAKE_MAGIC;
++	wol->wolopts = 0;
++
++	value = phy_read(phydev, AT803X_INTR_ENABLE);
++	if (value < 0)
++		return;
++
++	if (value & AT803X_INTR_ENABLE_WOL)
++		wol->wolopts |= WAKE_MAGIC;
++}
++EXPORT_SYMBOL_GPL(at803x_get_wol);
++
++int at803x_ack_interrupt(struct phy_device *phydev)
++{
++	int err;
++
++	err = phy_read(phydev, AT803X_INTR_STATUS);
++
++	return (err < 0) ? err : 0;
++}
++EXPORT_SYMBOL_GPL(at803x_ack_interrupt);
++
++int at803x_config_intr(struct phy_device *phydev)
++{
++	int err;
++	int value;
++
++	value = phy_read(phydev, AT803X_INTR_ENABLE);
++
++	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
++		/* Clear any pending interrupts */
++		err = at803x_ack_interrupt(phydev);
++		if (err)
++			return err;
++
++		value |= AT803X_INTR_ENABLE_AUTONEG_ERR;
++		value |= AT803X_INTR_ENABLE_SPEED_CHANGED;
++		value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED;
++		value |= AT803X_INTR_ENABLE_LINK_FAIL;
++		value |= AT803X_INTR_ENABLE_LINK_SUCCESS;
++
++		err = phy_write(phydev, AT803X_INTR_ENABLE, value);
++	} else {
++		err = phy_write(phydev, AT803X_INTR_ENABLE, 0);
++		if (err)
++			return err;
++
++		/* Clear any pending interrupts */
++		err = at803x_ack_interrupt(phydev);
++	}
++
++	return err;
++}
++EXPORT_SYMBOL_GPL(at803x_config_intr);
++
++irqreturn_t at803x_handle_interrupt(struct phy_device *phydev)
++{
++	int irq_status, int_enabled;
++
++	irq_status = phy_read(phydev, AT803X_INTR_STATUS);
++	if (irq_status < 0) {
++		phy_error(phydev);
++		return IRQ_NONE;
++	}
++
++	/* Read the current enabled interrupts */
++	int_enabled = phy_read(phydev, AT803X_INTR_ENABLE);
++	if (int_enabled < 0) {
++		phy_error(phydev);
++		return IRQ_NONE;
++	}
++
++	/* See if this was one of our enabled interrupts */
++	if (!(irq_status & int_enabled))
++		return IRQ_NONE;
++
++	phy_trigger_machine(phydev);
++
++	return IRQ_HANDLED;
++}
++EXPORT_SYMBOL_GPL(at803x_handle_interrupt);
++
++int at803x_read_specific_status(struct phy_device *phydev,
++				struct at803x_ss_mask ss_mask)
++{
++	int ss;
++
++	/* Read the AT8035 PHY-Specific Status register, which indicates the
++	 * speed and duplex that the PHY is actually using, irrespective of
++	 * whether we are in autoneg mode or not.
++	 */
++	ss = phy_read(phydev, AT803X_SPECIFIC_STATUS);
++	if (ss < 0)
++		return ss;
++
++	if (ss & AT803X_SS_SPEED_DUPLEX_RESOLVED) {
++		int sfc, speed;
++
++		sfc = phy_read(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL);
++		if (sfc < 0)
++			return sfc;
++
++		speed = ss & ss_mask.speed_mask;
++		speed >>= ss_mask.speed_shift;
++
++		switch (speed) {
++		case AT803X_SS_SPEED_10:
++			phydev->speed = SPEED_10;
++			break;
++		case AT803X_SS_SPEED_100:
++			phydev->speed = SPEED_100;
++			break;
++		case AT803X_SS_SPEED_1000:
++			phydev->speed = SPEED_1000;
++			break;
++		case QCA808X_SS_SPEED_2500:
++			phydev->speed = SPEED_2500;
++			break;
++		}
++		if (ss & AT803X_SS_DUPLEX)
++			phydev->duplex = DUPLEX_FULL;
++		else
++			phydev->duplex = DUPLEX_HALF;
++
++		if (ss & AT803X_SS_MDIX)
++			phydev->mdix = ETH_TP_MDI_X;
++		else
++			phydev->mdix = ETH_TP_MDI;
++
++		switch (FIELD_GET(AT803X_SFC_MDI_CROSSOVER_MODE_M, sfc)) {
++		case AT803X_SFC_MANUAL_MDI:
++			phydev->mdix_ctrl = ETH_TP_MDI;
++			break;
++		case AT803X_SFC_MANUAL_MDIX:
++			phydev->mdix_ctrl = ETH_TP_MDI_X;
++			break;
++		case AT803X_SFC_AUTOMATIC_CROSSOVER:
++			phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
++			break;
++		}
++	}
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(at803x_read_specific_status);
++
++int at803x_config_mdix(struct phy_device *phydev, u8 ctrl)
++{
++	u16 val;
++
++	switch (ctrl) {
++	case ETH_TP_MDI:
++		val = AT803X_SFC_MANUAL_MDI;
++		break;
++	case ETH_TP_MDI_X:
++		val = AT803X_SFC_MANUAL_MDIX;
++		break;
++	case ETH_TP_MDI_AUTO:
++		val = AT803X_SFC_AUTOMATIC_CROSSOVER;
++		break;
++	default:
++		return 0;
++	}
++
++	return phy_modify_changed(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL,
++			  AT803X_SFC_MDI_CROSSOVER_MODE_M,
++			  FIELD_PREP(AT803X_SFC_MDI_CROSSOVER_MODE_M, val));
++}
++EXPORT_SYMBOL_GPL(at803x_config_mdix);
++
++int at803x_prepare_config_aneg(struct phy_device *phydev)
++{
++	int ret;
++
++	ret = at803x_config_mdix(phydev, phydev->mdix_ctrl);
++	if (ret < 0)
++		return ret;
++
++	/* Changes of the midx bits are disruptive to the normal operation;
++	 * therefore any changes to these registers must be followed by a
++	 * software reset to take effect.
++	 */
++	if (ret == 1) {
++		ret = genphy_soft_reset(phydev);
++		if (ret < 0)
++			return ret;
++	}
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(at803x_prepare_config_aneg);
++
++static int at803x_get_downshift(struct phy_device *phydev, u8 *d)
++{
++	int val;
++
++	val = phy_read(phydev, AT803X_SMART_SPEED);
++	if (val < 0)
++		return val;
++
++	if (val & AT803X_SMART_SPEED_ENABLE)
++		*d = FIELD_GET(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, val) + 2;
++	else
++		*d = DOWNSHIFT_DEV_DISABLE;
++
++	return 0;
++}
++
++static int at803x_set_downshift(struct phy_device *phydev, u8 cnt)
++{
++	u16 mask, set;
++	int ret;
++
++	switch (cnt) {
++	case DOWNSHIFT_DEV_DEFAULT_COUNT:
++		cnt = AT803X_DEFAULT_DOWNSHIFT;
++		fallthrough;
++	case AT803X_MIN_DOWNSHIFT ... AT803X_MAX_DOWNSHIFT:
++		set = AT803X_SMART_SPEED_ENABLE |
++		      AT803X_SMART_SPEED_BYPASS_TIMER |
++		      FIELD_PREP(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, cnt - 2);
++		mask = AT803X_SMART_SPEED_RETRY_LIMIT_MASK;
++		break;
++	case DOWNSHIFT_DEV_DISABLE:
++		set = 0;
++		mask = AT803X_SMART_SPEED_ENABLE |
++		       AT803X_SMART_SPEED_BYPASS_TIMER;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	ret = phy_modify_changed(phydev, AT803X_SMART_SPEED, mask, set);
++
++	/* After changing the smart speed settings, we need to perform a
++	 * software reset, use phy_init_hw() to make sure we set the
++	 * reapply any values which might got lost during software reset.
++	 */
++	if (ret == 1)
++		ret = phy_init_hw(phydev);
++
++	return ret;
++}
++
++int at803x_get_tunable(struct phy_device *phydev,
++		       struct ethtool_tunable *tuna, void *data)
++{
++	switch (tuna->id) {
++	case ETHTOOL_PHY_DOWNSHIFT:
++		return at803x_get_downshift(phydev, data);
++	default:
++		return -EOPNOTSUPP;
++	}
++}
++EXPORT_SYMBOL_GPL(at803x_get_tunable);
++
++int at803x_set_tunable(struct phy_device *phydev,
++		       struct ethtool_tunable *tuna, const void *data)
++{
++	switch (tuna->id) {
++	case ETHTOOL_PHY_DOWNSHIFT:
++		return at803x_set_downshift(phydev, *(const u8 *)data);
++	default:
++		return -EOPNOTSUPP;
++	}
++}
++EXPORT_SYMBOL_GPL(at803x_set_tunable);
++
++int at803x_cdt_fault_length(int dt)
++{
++	/* According to the datasheet the distance to the fault is
++	 * DELTA_TIME * 0.824 meters.
++	 *
++	 * The author suspect the correct formula is:
++	 *
++	 *   fault_distance = DELTA_TIME * (c * VF) / 125MHz / 2
++	 *
++	 * where c is the speed of light, VF is the velocity factor of
++	 * the twisted pair cable, 125MHz the counter frequency and
++	 * we need to divide by 2 because the hardware will measure the
++	 * round trip time to the fault and back to the PHY.
++	 *
++	 * With a VF of 0.69 we get the factor 0.824 mentioned in the
++	 * datasheet.
++	 */
++	return (dt * 824) / 10;
++}
++EXPORT_SYMBOL_GPL(at803x_cdt_fault_length);
++
++int at803x_cdt_start(struct phy_device *phydev, u32 cdt_start)
++{
++	return phy_write(phydev, AT803X_CDT, cdt_start);
++}
++EXPORT_SYMBOL_GPL(at803x_cdt_start);
++
++int at803x_cdt_wait_for_completion(struct phy_device *phydev,
++				   u32 cdt_en)
++{
++	int val, ret;
++
++	/* One test run takes about 25ms */
++	ret = phy_read_poll_timeout(phydev, AT803X_CDT, val,
++				    !(val & cdt_en),
++				    30000, 100000, true);
++
++	return ret < 0 ? ret : 0;
++}
++EXPORT_SYMBOL_GPL(at803x_cdt_wait_for_completion);
+--- a/drivers/net/phy/qcom/qcom.h
++++ b/drivers/net/phy/qcom/qcom.h
+@@ -1,5 +1,63 @@
+ /* SPDX-License-Identifier: GPL-2.0 */
+ 
++#define AT803X_SPECIFIC_FUNCTION_CONTROL	0x10
++#define AT803X_SFC_ASSERT_CRS			BIT(11)
++#define AT803X_SFC_FORCE_LINK			BIT(10)
++#define AT803X_SFC_MDI_CROSSOVER_MODE_M		GENMASK(6, 5)
++#define AT803X_SFC_AUTOMATIC_CROSSOVER		0x3
++#define AT803X_SFC_MANUAL_MDIX			0x1
++#define AT803X_SFC_MANUAL_MDI			0x0
++#define AT803X_SFC_SQE_TEST			BIT(2)
++#define AT803X_SFC_POLARITY_REVERSAL		BIT(1)
++#define AT803X_SFC_DISABLE_JABBER		BIT(0)
++
++#define AT803X_SPECIFIC_STATUS			0x11
++#define AT803X_SS_SPEED_MASK			GENMASK(15, 14)
++#define AT803X_SS_SPEED_1000			2
++#define AT803X_SS_SPEED_100			1
++#define AT803X_SS_SPEED_10			0
++#define AT803X_SS_DUPLEX			BIT(13)
++#define AT803X_SS_SPEED_DUPLEX_RESOLVED		BIT(11)
++#define AT803X_SS_MDIX				BIT(6)
++
++#define QCA808X_SS_SPEED_MASK			GENMASK(9, 7)
++#define QCA808X_SS_SPEED_2500			4
++
++#define AT803X_INTR_ENABLE			0x12
++#define AT803X_INTR_ENABLE_AUTONEG_ERR		BIT(15)
++#define AT803X_INTR_ENABLE_SPEED_CHANGED	BIT(14)
++#define AT803X_INTR_ENABLE_DUPLEX_CHANGED	BIT(13)
++#define AT803X_INTR_ENABLE_PAGE_RECEIVED	BIT(12)
++#define AT803X_INTR_ENABLE_LINK_FAIL		BIT(11)
++#define AT803X_INTR_ENABLE_LINK_SUCCESS		BIT(10)
++#define AT803X_INTR_ENABLE_LINK_FAIL_BX		BIT(8)
++#define AT803X_INTR_ENABLE_LINK_SUCCESS_BX	BIT(7)
++#define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE	BIT(5)
++#define AT803X_INTR_ENABLE_POLARITY_CHANGED	BIT(1)
++#define AT803X_INTR_ENABLE_WOL			BIT(0)
++
++#define AT803X_INTR_STATUS			0x13
++
++#define AT803X_SMART_SPEED			0x14
++#define AT803X_SMART_SPEED_ENABLE		BIT(5)
++#define AT803X_SMART_SPEED_RETRY_LIMIT_MASK	GENMASK(4, 2)
++#define AT803X_SMART_SPEED_BYPASS_TIMER		BIT(1)
++
++#define AT803X_CDT				0x16
++#define AT803X_CDT_MDI_PAIR_MASK		GENMASK(9, 8)
++#define AT803X_CDT_ENABLE_TEST			BIT(0)
++#define AT803X_CDT_STATUS			0x1c
++#define AT803X_CDT_STATUS_STAT_NORMAL		0
++#define AT803X_CDT_STATUS_STAT_SHORT		1
++#define AT803X_CDT_STATUS_STAT_OPEN		2
++#define AT803X_CDT_STATUS_STAT_FAIL		3
++#define AT803X_CDT_STATUS_STAT_MASK		GENMASK(9, 8)
++#define AT803X_CDT_STATUS_DELTA_TIME_MASK	GENMASK(7, 0)
++
++#define AT803X_LOC_MAC_ADDR_0_15_OFFSET		0x804C
++#define AT803X_LOC_MAC_ADDR_16_31_OFFSET	0x804B
++#define AT803X_LOC_MAC_ADDR_32_47_OFFSET	0x804A
++
+ #define AT803X_DEBUG_ADDR			0x1D
+ #define AT803X_DEBUG_DATA			0x1E
+ 
+@@ -16,6 +74,10 @@
+ #define   AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE	BIT(13)
+ #define   AT803X_DEBUG_HIB_CTRL_PS_HIB_EN	BIT(15)
+ 
++#define AT803X_DEFAULT_DOWNSHIFT		5
++#define AT803X_MIN_DOWNSHIFT			2
++#define AT803X_MAX_DOWNSHIFT			9
++
+ enum stat_access_type {
+ 	PHY,
+ 	MMD
+@@ -28,7 +90,31 @@ struct at803x_hw_stat {
+ 	enum stat_access_type access_type;
+ };
+ 
++struct at803x_ss_mask {
++	u16 speed_mask;
++	u8 speed_shift;
++};
++
+ int at803x_debug_reg_read(struct phy_device *phydev, u16 reg);
+ int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
+ 			  u16 clear, u16 set);
+ int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data);
++int at803x_set_wol(struct phy_device *phydev,
++		   struct ethtool_wolinfo *wol);
++void at803x_get_wol(struct phy_device *phydev,
++		    struct ethtool_wolinfo *wol);
++int at803x_ack_interrupt(struct phy_device *phydev);
++int at803x_config_intr(struct phy_device *phydev);
++irqreturn_t at803x_handle_interrupt(struct phy_device *phydev);
++int at803x_read_specific_status(struct phy_device *phydev,
++				struct at803x_ss_mask ss_mask);
++int at803x_config_mdix(struct phy_device *phydev, u8 ctrl);
++int at803x_prepare_config_aneg(struct phy_device *phydev);
++int at803x_get_tunable(struct phy_device *phydev,
++		       struct ethtool_tunable *tuna, void *data);
++int at803x_set_tunable(struct phy_device *phydev,
++		       struct ethtool_tunable *tuna, const void *data);
++int at803x_cdt_fault_length(int dt);
++int at803x_cdt_start(struct phy_device *phydev, u32 cdt_start);
++int at803x_cdt_wait_for_completion(struct phy_device *phydev,
++				   u32 cdt_en);
diff --git a/target/linux/generic/backport-6.1/713-v6.9-05-net-phy-qcom-detach-qca808x-PHY-driver-from-at803x.patch b/target/linux/generic/backport-6.1/713-v6.9-05-net-phy-qcom-detach-qca808x-PHY-driver-from-at803x.patch
new file mode 100644
index 00000000000000..597dcea4c06955
--- /dev/null
+++ b/target/linux/generic/backport-6.1/713-v6.9-05-net-phy-qcom-detach-qca808x-PHY-driver-from-at803x.patch
@@ -0,0 +1,1936 @@
+From c89414adf2ec7cd9e7080c419aa5847f1db1009c Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Mon, 29 Jan 2024 15:15:23 +0100
+Subject: [PATCH 5/5] net: phy: qcom: detach qca808x PHY driver from at803x
+
+Almost all the QCA8081 PHY driver OPs are specific and only some of them
+use the generic at803x.
+
+To make the at803x code slimmer, move all the specific qca808x regs and
+functions to a dedicated PHY driver.
+
+Probe function and priv struct is reworked to allocate and use only the
+qca808x specific data. Unused data from at803x PHY driver are dropped
+from at803x priv struct.
+
+Also a new Kconfig is introduced QCA808X_PHY, to compile the newly
+introduced PHY driver for QCA8081 PHY.
+
+As the Kconfig name starts with Qualcomm the same order is kept.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://lore.kernel.org/r/20240129141600.2592-6-ansuelsmth@gmail.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/qcom/Kconfig   |   6 +
+ drivers/net/phy/qcom/Makefile  |   1 +
+ drivers/net/phy/qcom/at803x.c  | 897 +------------------------------
+ drivers/net/phy/qcom/qca808x.c | 934 +++++++++++++++++++++++++++++++++
+ 4 files changed, 942 insertions(+), 896 deletions(-)
+ create mode 100644 drivers/net/phy/qcom/qca808x.c
+
+--- a/drivers/net/phy/qcom/Kconfig
++++ b/drivers/net/phy/qcom/Kconfig
+@@ -14,3 +14,9 @@ config QCA83XX_PHY
+ 	select QCOM_NET_PHYLIB
+ 	help
+ 	  Currently supports the internal QCA8337(Internal qca8k PHY) model
++
++config QCA808X_PHY
++	tristate "Qualcomm QCA808x PHYs"
++	select QCOM_NET_PHYLIB
++	help
++	  Currently supports the QCA8081 model
+--- a/drivers/net/phy/qcom/Makefile
++++ b/drivers/net/phy/qcom/Makefile
+@@ -2,3 +2,4 @@
+ obj-$(CONFIG_QCOM_NET_PHYLIB)	+= qcom-phy-lib.o
+ obj-$(CONFIG_AT803X_PHY)	+= at803x.o
+ obj-$(CONFIG_QCA83XX_PHY)	+= qca83xx.o
++obj-$(CONFIG_QCA808X_PHY)	+= qca808x.o
+--- a/drivers/net/phy/qcom/at803x.c
++++ b/drivers/net/phy/qcom/at803x.c
+@@ -96,8 +96,6 @@
+ #define ATH8035_PHY_ID				0x004dd072
+ #define AT8030_PHY_ID_MASK			0xffffffef
+ 
+-#define QCA8081_PHY_ID				0x004dd101
+-
+ #define QCA9561_PHY_ID				0x004dd042
+ 
+ #define AT803X_PAGE_FIBER			0
+@@ -110,201 +108,7 @@
+ /* disable hibernation mode */
+ #define AT803X_DISABLE_HIBERNATION_MODE		BIT(2)
+ 
+-/* ADC threshold */
+-#define QCA808X_PHY_DEBUG_ADC_THRESHOLD		0x2c80
+-#define QCA808X_ADC_THRESHOLD_MASK		GENMASK(7, 0)
+-#define QCA808X_ADC_THRESHOLD_80MV		0
+-#define QCA808X_ADC_THRESHOLD_100MV		0xf0
+-#define QCA808X_ADC_THRESHOLD_200MV		0x0f
+-#define QCA808X_ADC_THRESHOLD_300MV		0xff
+-
+-/* CLD control */
+-#define QCA808X_PHY_MMD3_ADDR_CLD_CTRL7		0x8007
+-#define QCA808X_8023AZ_AFE_CTRL_MASK		GENMASK(8, 4)
+-#define QCA808X_8023AZ_AFE_EN			0x90
+-
+-/* AZ control */
+-#define QCA808X_PHY_MMD3_AZ_TRAINING_CTRL	0x8008
+-#define QCA808X_MMD3_AZ_TRAINING_VAL		0x1c32
+-
+-#define QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB	0x8014
+-#define QCA808X_MSE_THRESHOLD_20DB_VALUE	0x529
+-
+-#define QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB	0x800E
+-#define QCA808X_MSE_THRESHOLD_17DB_VALUE	0x341
+-
+-#define QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB	0x801E
+-#define QCA808X_MSE_THRESHOLD_27DB_VALUE	0x419
+-
+-#define QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB	0x8020
+-#define QCA808X_MSE_THRESHOLD_28DB_VALUE	0x341
+-
+-#define QCA808X_PHY_MMD7_TOP_OPTION1		0x901c
+-#define QCA808X_TOP_OPTION1_DATA		0x0
+-
+-#define QCA808X_PHY_MMD3_DEBUG_1		0xa100
+-#define QCA808X_MMD3_DEBUG_1_VALUE		0x9203
+-#define QCA808X_PHY_MMD3_DEBUG_2		0xa101
+-#define QCA808X_MMD3_DEBUG_2_VALUE		0x48ad
+-#define QCA808X_PHY_MMD3_DEBUG_3		0xa103
+-#define QCA808X_MMD3_DEBUG_3_VALUE		0x1698
+-#define QCA808X_PHY_MMD3_DEBUG_4		0xa105
+-#define QCA808X_MMD3_DEBUG_4_VALUE		0x8001
+-#define QCA808X_PHY_MMD3_DEBUG_5		0xa106
+-#define QCA808X_MMD3_DEBUG_5_VALUE		0x1111
+-#define QCA808X_PHY_MMD3_DEBUG_6		0xa011
+-#define QCA808X_MMD3_DEBUG_6_VALUE		0x5f85
+-
+-/* master/slave seed config */
+-#define QCA808X_PHY_DEBUG_LOCAL_SEED		9
+-#define QCA808X_MASTER_SLAVE_SEED_ENABLE	BIT(1)
+-#define QCA808X_MASTER_SLAVE_SEED_CFG		GENMASK(12, 2)
+-#define QCA808X_MASTER_SLAVE_SEED_RANGE		0x32
+-
+-/* Hibernation yields lower power consumpiton in contrast with normal operation mode.
+- * when the copper cable is unplugged, the PHY enters into hibernation mode in about 10s.
+- */
+-#define QCA808X_DBG_AN_TEST			0xb
+-#define QCA808X_HIBERNATION_EN			BIT(15)
+-
+-#define QCA808X_CDT_ENABLE_TEST			BIT(15)
+-#define QCA808X_CDT_INTER_CHECK_DIS		BIT(13)
+-#define QCA808X_CDT_STATUS			BIT(11)
+-#define QCA808X_CDT_LENGTH_UNIT			BIT(10)
+-
+-#define QCA808X_MMD3_CDT_STATUS			0x8064
+-#define QCA808X_MMD3_CDT_DIAG_PAIR_A		0x8065
+-#define QCA808X_MMD3_CDT_DIAG_PAIR_B		0x8066
+-#define QCA808X_MMD3_CDT_DIAG_PAIR_C		0x8067
+-#define QCA808X_MMD3_CDT_DIAG_PAIR_D		0x8068
+-#define QCA808X_CDT_DIAG_LENGTH_SAME_SHORT	GENMASK(15, 8)
+-#define QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT	GENMASK(7, 0)
+-
+-#define QCA808X_CDT_CODE_PAIR_A			GENMASK(15, 12)
+-#define QCA808X_CDT_CODE_PAIR_B			GENMASK(11, 8)
+-#define QCA808X_CDT_CODE_PAIR_C			GENMASK(7, 4)
+-#define QCA808X_CDT_CODE_PAIR_D			GENMASK(3, 0)
+-
+-#define QCA808X_CDT_STATUS_STAT_TYPE		GENMASK(1, 0)
+-#define QCA808X_CDT_STATUS_STAT_FAIL		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 0)
+-#define QCA808X_CDT_STATUS_STAT_NORMAL		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 1)
+-#define QCA808X_CDT_STATUS_STAT_SAME_OPEN	FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 2)
+-#define QCA808X_CDT_STATUS_STAT_SAME_SHORT	FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 3)
+-
+-#define QCA808X_CDT_STATUS_STAT_MDI		GENMASK(3, 2)
+-#define QCA808X_CDT_STATUS_STAT_MDI1		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 1)
+-#define QCA808X_CDT_STATUS_STAT_MDI2		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 2)
+-#define QCA808X_CDT_STATUS_STAT_MDI3		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 3)
+-
+-/* NORMAL are MDI with type set to 0 */
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL	QCA808X_CDT_STATUS_STAT_MDI1
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN		(QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
+-									 QCA808X_CDT_STATUS_STAT_MDI1)
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT	(QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
+-									 QCA808X_CDT_STATUS_STAT_MDI1)
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL	QCA808X_CDT_STATUS_STAT_MDI2
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN		(QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
+-									 QCA808X_CDT_STATUS_STAT_MDI2)
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT	(QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
+-									 QCA808X_CDT_STATUS_STAT_MDI2)
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL	QCA808X_CDT_STATUS_STAT_MDI3
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN		(QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
+-									 QCA808X_CDT_STATUS_STAT_MDI3)
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT	(QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
+-									 QCA808X_CDT_STATUS_STAT_MDI3)
+-
+-/* Added for reference of existence but should be handled by wait_for_completion already */
+-#define QCA808X_CDT_STATUS_STAT_BUSY		(BIT(1) | BIT(3))
+-
+-#define QCA808X_MMD7_LED_GLOBAL			0x8073
+-#define QCA808X_LED_BLINK_1			GENMASK(11, 6)
+-#define QCA808X_LED_BLINK_2			GENMASK(5, 0)
+-/* Values are the same for both BLINK_1 and BLINK_2 */
+-#define QCA808X_LED_BLINK_FREQ_MASK		GENMASK(5, 3)
+-#define QCA808X_LED_BLINK_FREQ_2HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x0)
+-#define QCA808X_LED_BLINK_FREQ_4HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x1)
+-#define QCA808X_LED_BLINK_FREQ_8HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x2)
+-#define QCA808X_LED_BLINK_FREQ_16HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x3)
+-#define QCA808X_LED_BLINK_FREQ_32HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x4)
+-#define QCA808X_LED_BLINK_FREQ_64HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x5)
+-#define QCA808X_LED_BLINK_FREQ_128HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x6)
+-#define QCA808X_LED_BLINK_FREQ_256HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x7)
+-#define QCA808X_LED_BLINK_DUTY_MASK		GENMASK(2, 0)
+-#define QCA808X_LED_BLINK_DUTY_50_50		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x0)
+-#define QCA808X_LED_BLINK_DUTY_75_25		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x1)
+-#define QCA808X_LED_BLINK_DUTY_25_75		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x2)
+-#define QCA808X_LED_BLINK_DUTY_33_67		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x3)
+-#define QCA808X_LED_BLINK_DUTY_67_33		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x4)
+-#define QCA808X_LED_BLINK_DUTY_17_83		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x5)
+-#define QCA808X_LED_BLINK_DUTY_83_17		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x6)
+-#define QCA808X_LED_BLINK_DUTY_8_92		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x7)
+-
+-#define QCA808X_MMD7_LED2_CTRL			0x8074
+-#define QCA808X_MMD7_LED2_FORCE_CTRL		0x8075
+-#define QCA808X_MMD7_LED1_CTRL			0x8076
+-#define QCA808X_MMD7_LED1_FORCE_CTRL		0x8077
+-#define QCA808X_MMD7_LED0_CTRL			0x8078
+-#define QCA808X_MMD7_LED_CTRL(x)		(0x8078 - ((x) * 2))
+-
+-/* LED hw control pattern is the same for every LED */
+-#define QCA808X_LED_PATTERN_MASK		GENMASK(15, 0)
+-#define QCA808X_LED_SPEED2500_ON		BIT(15)
+-#define QCA808X_LED_SPEED2500_BLINK		BIT(14)
+-/* Follow blink trigger even if duplex or speed condition doesn't match */
+-#define QCA808X_LED_BLINK_CHECK_BYPASS		BIT(13)
+-#define QCA808X_LED_FULL_DUPLEX_ON		BIT(12)
+-#define QCA808X_LED_HALF_DUPLEX_ON		BIT(11)
+-#define QCA808X_LED_TX_BLINK			BIT(10)
+-#define QCA808X_LED_RX_BLINK			BIT(9)
+-#define QCA808X_LED_TX_ON_10MS			BIT(8)
+-#define QCA808X_LED_RX_ON_10MS			BIT(7)
+-#define QCA808X_LED_SPEED1000_ON		BIT(6)
+-#define QCA808X_LED_SPEED100_ON			BIT(5)
+-#define QCA808X_LED_SPEED10_ON			BIT(4)
+-#define QCA808X_LED_COLLISION_BLINK		BIT(3)
+-#define QCA808X_LED_SPEED1000_BLINK		BIT(2)
+-#define QCA808X_LED_SPEED100_BLINK		BIT(1)
+-#define QCA808X_LED_SPEED10_BLINK		BIT(0)
+-
+-#define QCA808X_MMD7_LED0_FORCE_CTRL		0x8079
+-#define QCA808X_MMD7_LED_FORCE_CTRL(x)		(0x8079 - ((x) * 2))
+-
+-/* LED force ctrl is the same for every LED
+- * No documentation exist for this, not even internal one
+- * with NDA as QCOM gives only info about configuring
+- * hw control pattern rules and doesn't indicate any way
+- * to force the LED to specific mode.
+- * These define comes from reverse and testing and maybe
+- * lack of some info or some info are not entirely correct.
+- * For the basic LED control and hw control these finding
+- * are enough to support LED control in all the required APIs.
+- *
+- * On doing some comparison with implementation with qca807x,
+- * it was found that it's 1:1 equal to it and confirms all the
+- * reverse done. It was also found further specification with the
+- * force mode and the blink modes.
+- */
+-#define QCA808X_LED_FORCE_EN			BIT(15)
+-#define QCA808X_LED_FORCE_MODE_MASK		GENMASK(14, 13)
+-#define QCA808X_LED_FORCE_BLINK_1		FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x3)
+-#define QCA808X_LED_FORCE_BLINK_2		FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x2)
+-#define QCA808X_LED_FORCE_ON			FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x1)
+-#define QCA808X_LED_FORCE_OFF			FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x0)
+-
+-#define QCA808X_MMD7_LED_POLARITY_CTRL		0x901a
+-/* QSDK sets by default 0x46 to this reg that sets BIT 6 for
+- * LED to active high. It's not clear what BIT 3 and BIT 4 does.
+- */
+-#define QCA808X_LED_ACTIVE_HIGH			BIT(6)
+-
+-/* QCA808X 1G chip type */
+-#define QCA808X_PHY_MMD7_CHIP_TYPE		0x901d
+-#define QCA808X_PHY_CHIP_TYPE_1G		BIT(0)
+-
+-#define QCA8081_PHY_SERDES_MMD1_FIFO_CTRL	0x9072
+-#define QCA8081_PHY_FIFO_RSTN			BIT(11)
+-
+-MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver");
++MODULE_DESCRIPTION("Qualcomm Atheros AR803x PHY driver");
+ MODULE_AUTHOR("Matus Ujhelyi");
+ MODULE_LICENSE("GPL");
+ 
+@@ -318,7 +122,6 @@ struct at803x_priv {
+ 	bool is_1000basex;
+ 	struct regulator_dev *vddio_rdev;
+ 	struct regulator_dev *vddh_rdev;
+-	int led_polarity_mode;
+ };
+ 
+ struct at803x_context {
+@@ -519,9 +322,6 @@ static int at803x_probe(struct phy_devic
+ 	if (!priv)
+ 		return -ENOMEM;
+ 
+-	/* Init LED polarity mode to -1 */
+-	priv->led_polarity_mode = -1;
+-
+ 	phydev->priv = priv;
+ 
+ 	ret = at803x_parse_dt(phydev);
+@@ -1216,672 +1016,6 @@ static int at8035_probe(struct phy_devic
+ 	return at8035_parse_dt(phydev);
+ }
+ 
+-static int qca808x_phy_fast_retrain_config(struct phy_device *phydev)
+-{
+-	int ret;
+-
+-	/* Enable fast retrain */
+-	ret = genphy_c45_fast_retrain(phydev, true);
+-	if (ret)
+-		return ret;
+-
+-	phy_write_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_TOP_OPTION1,
+-		      QCA808X_TOP_OPTION1_DATA);
+-	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB,
+-		      QCA808X_MSE_THRESHOLD_20DB_VALUE);
+-	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB,
+-		      QCA808X_MSE_THRESHOLD_17DB_VALUE);
+-	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB,
+-		      QCA808X_MSE_THRESHOLD_27DB_VALUE);
+-	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB,
+-		      QCA808X_MSE_THRESHOLD_28DB_VALUE);
+-	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_1,
+-		      QCA808X_MMD3_DEBUG_1_VALUE);
+-	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_4,
+-		      QCA808X_MMD3_DEBUG_4_VALUE);
+-	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_5,
+-		      QCA808X_MMD3_DEBUG_5_VALUE);
+-	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_3,
+-		      QCA808X_MMD3_DEBUG_3_VALUE);
+-	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_6,
+-		      QCA808X_MMD3_DEBUG_6_VALUE);
+-	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_2,
+-		      QCA808X_MMD3_DEBUG_2_VALUE);
+-
+-	return 0;
+-}
+-
+-static int qca808x_phy_ms_seed_enable(struct phy_device *phydev, bool enable)
+-{
+-	u16 seed_value;
+-
+-	if (!enable)
+-		return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED,
+-				QCA808X_MASTER_SLAVE_SEED_ENABLE, 0);
+-
+-	seed_value = prandom_u32_max(QCA808X_MASTER_SLAVE_SEED_RANGE);
+-	return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED,
+-			QCA808X_MASTER_SLAVE_SEED_CFG | QCA808X_MASTER_SLAVE_SEED_ENABLE,
+-			FIELD_PREP(QCA808X_MASTER_SLAVE_SEED_CFG, seed_value) |
+-			QCA808X_MASTER_SLAVE_SEED_ENABLE);
+-}
+-
+-static bool qca808x_is_prefer_master(struct phy_device *phydev)
+-{
+-	return (phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_FORCE) ||
+-		(phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_PREFERRED);
+-}
+-
+-static bool qca808x_has_fast_retrain_or_slave_seed(struct phy_device *phydev)
+-{
+-	return linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported);
+-}
+-
+-static int qca808x_config_init(struct phy_device *phydev)
+-{
+-	int ret;
+-
+-	/* Active adc&vga on 802.3az for the link 1000M and 100M */
+-	ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_ADDR_CLD_CTRL7,
+-			     QCA808X_8023AZ_AFE_CTRL_MASK, QCA808X_8023AZ_AFE_EN);
+-	if (ret)
+-		return ret;
+-
+-	/* Adjust the threshold on 802.3az for the link 1000M */
+-	ret = phy_write_mmd(phydev, MDIO_MMD_PCS,
+-			    QCA808X_PHY_MMD3_AZ_TRAINING_CTRL,
+-			    QCA808X_MMD3_AZ_TRAINING_VAL);
+-	if (ret)
+-		return ret;
+-
+-	if (qca808x_has_fast_retrain_or_slave_seed(phydev)) {
+-		/* Config the fast retrain for the link 2500M */
+-		ret = qca808x_phy_fast_retrain_config(phydev);
+-		if (ret)
+-			return ret;
+-
+-		ret = genphy_read_master_slave(phydev);
+-		if (ret < 0)
+-			return ret;
+-
+-		if (!qca808x_is_prefer_master(phydev)) {
+-			/* Enable seed and configure lower ramdom seed to make phy
+-			 * linked as slave mode.
+-			 */
+-			ret = qca808x_phy_ms_seed_enable(phydev, true);
+-			if (ret)
+-				return ret;
+-		}
+-	}
+-
+-	/* Configure adc threshold as 100mv for the link 10M */
+-	return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD,
+-				     QCA808X_ADC_THRESHOLD_MASK,
+-				     QCA808X_ADC_THRESHOLD_100MV);
+-}
+-
+-static int qca808x_read_status(struct phy_device *phydev)
+-{
+-	struct at803x_ss_mask ss_mask = { 0 };
+-	int ret;
+-
+-	ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);
+-	if (ret < 0)
+-		return ret;
+-
+-	linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->lp_advertising,
+-			 ret & MDIO_AN_10GBT_STAT_LP2_5G);
+-
+-	ret = genphy_read_status(phydev);
+-	if (ret)
+-		return ret;
+-
+-	/* qca8081 takes the different bits for speed value from at803x */
+-	ss_mask.speed_mask = QCA808X_SS_SPEED_MASK;
+-	ss_mask.speed_shift = __bf_shf(QCA808X_SS_SPEED_MASK);
+-	ret = at803x_read_specific_status(phydev, ss_mask);
+-	if (ret < 0)
+-		return ret;
+-
+-	if (phydev->link) {
+-		if (phydev->speed == SPEED_2500)
+-			phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
+-		else
+-			phydev->interface = PHY_INTERFACE_MODE_SGMII;
+-	} else {
+-		/* generate seed as a lower random value to make PHY linked as SLAVE easily,
+-		 * except for master/slave configuration fault detected or the master mode
+-		 * preferred.
+-		 *
+-		 * the reason for not putting this code into the function link_change_notify is
+-		 * the corner case where the link partner is also the qca8081 PHY and the seed
+-		 * value is configured as the same value, the link can't be up and no link change
+-		 * occurs.
+-		 */
+-		if (qca808x_has_fast_retrain_or_slave_seed(phydev)) {
+-			if (phydev->master_slave_state == MASTER_SLAVE_STATE_ERR ||
+-			    qca808x_is_prefer_master(phydev)) {
+-				qca808x_phy_ms_seed_enable(phydev, false);
+-			} else {
+-				qca808x_phy_ms_seed_enable(phydev, true);
+-			}
+-		}
+-	}
+-
+-	return 0;
+-}
+-
+-static int qca808x_soft_reset(struct phy_device *phydev)
+-{
+-	int ret;
+-
+-	ret = genphy_soft_reset(phydev);
+-	if (ret < 0)
+-		return ret;
+-
+-	if (qca808x_has_fast_retrain_or_slave_seed(phydev))
+-		ret = qca808x_phy_ms_seed_enable(phydev, true);
+-
+-	return ret;
+-}
+-
+-static bool qca808x_cdt_fault_length_valid(int cdt_code)
+-{
+-	switch (cdt_code) {
+-	case QCA808X_CDT_STATUS_STAT_SAME_SHORT:
+-	case QCA808X_CDT_STATUS_STAT_SAME_OPEN:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT:
+-		return true;
+-	default:
+-		return false;
+-	}
+-}
+-
+-static int qca808x_cable_test_result_trans(int cdt_code)
+-{
+-	switch (cdt_code) {
+-	case QCA808X_CDT_STATUS_STAT_NORMAL:
+-		return ETHTOOL_A_CABLE_RESULT_CODE_OK;
+-	case QCA808X_CDT_STATUS_STAT_SAME_SHORT:
+-		return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
+-	case QCA808X_CDT_STATUS_STAT_SAME_OPEN:
+-		return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT:
+-		return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;
+-	case QCA808X_CDT_STATUS_STAT_FAIL:
+-	default:
+-		return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
+-	}
+-}
+-
+-static int qca808x_cdt_fault_length(struct phy_device *phydev, int pair,
+-				    int result)
+-{
+-	int val;
+-	u32 cdt_length_reg = 0;
+-
+-	switch (pair) {
+-	case ETHTOOL_A_CABLE_PAIR_A:
+-		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_A;
+-		break;
+-	case ETHTOOL_A_CABLE_PAIR_B:
+-		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_B;
+-		break;
+-	case ETHTOOL_A_CABLE_PAIR_C:
+-		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_C;
+-		break;
+-	case ETHTOOL_A_CABLE_PAIR_D:
+-		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_D;
+-		break;
+-	default:
+-		return -EINVAL;
+-	}
+-
+-	val = phy_read_mmd(phydev, MDIO_MMD_PCS, cdt_length_reg);
+-	if (val < 0)
+-		return val;
+-
+-	if (result == ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT)
+-		val = FIELD_GET(QCA808X_CDT_DIAG_LENGTH_SAME_SHORT, val);
+-	else
+-		val = FIELD_GET(QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT, val);
+-
+-	return at803x_cdt_fault_length(val);
+-}
+-
+-static int qca808x_cable_test_start(struct phy_device *phydev)
+-{
+-	int ret;
+-
+-	/* perform CDT with the following configs:
+-	 * 1. disable hibernation.
+-	 * 2. force PHY working in MDI mode.
+-	 * 3. for PHY working in 1000BaseT.
+-	 * 4. configure the threshold.
+-	 */
+-
+-	ret = at803x_debug_reg_mask(phydev, QCA808X_DBG_AN_TEST, QCA808X_HIBERNATION_EN, 0);
+-	if (ret < 0)
+-		return ret;
+-
+-	ret = at803x_config_mdix(phydev, ETH_TP_MDI);
+-	if (ret < 0)
+-		return ret;
+-
+-	/* Force 1000base-T needs to configure PMA/PMD and MII_BMCR */
+-	phydev->duplex = DUPLEX_FULL;
+-	phydev->speed = SPEED_1000;
+-	ret = genphy_c45_pma_setup_forced(phydev);
+-	if (ret < 0)
+-		return ret;
+-
+-	ret = genphy_setup_forced(phydev);
+-	if (ret < 0)
+-		return ret;
+-
+-	/* configure the thresholds for open, short, pair ok test */
+-	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8074, 0xc040);
+-	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8076, 0xc040);
+-	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8077, 0xa060);
+-	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8078, 0xc050);
+-	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060);
+-	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807e, 0xb060);
+-
+-	return 0;
+-}
+-
+-static int qca808x_cable_test_get_pair_status(struct phy_device *phydev, u8 pair,
+-					      u16 status)
+-{
+-	int length, result;
+-	u16 pair_code;
+-
+-	switch (pair) {
+-	case ETHTOOL_A_CABLE_PAIR_A:
+-		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_A, status);
+-		break;
+-	case ETHTOOL_A_CABLE_PAIR_B:
+-		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_B, status);
+-		break;
+-	case ETHTOOL_A_CABLE_PAIR_C:
+-		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_C, status);
+-		break;
+-	case ETHTOOL_A_CABLE_PAIR_D:
+-		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_D, status);
+-		break;
+-	default:
+-		return -EINVAL;
+-	}
+-
+-	result = qca808x_cable_test_result_trans(pair_code);
+-	ethnl_cable_test_result(phydev, pair, result);
+-
+-	if (qca808x_cdt_fault_length_valid(pair_code)) {
+-		length = qca808x_cdt_fault_length(phydev, pair, result);
+-		ethnl_cable_test_fault_length(phydev, pair, length);
+-	}
+-
+-	return 0;
+-}
+-
+-static int qca808x_cable_test_get_status(struct phy_device *phydev, bool *finished)
+-{
+-	int ret, val;
+-
+-	*finished = false;
+-
+-	val = QCA808X_CDT_ENABLE_TEST |
+-	      QCA808X_CDT_LENGTH_UNIT;
+-	ret = at803x_cdt_start(phydev, val);
+-	if (ret)
+-		return ret;
+-
+-	ret = at803x_cdt_wait_for_completion(phydev, QCA808X_CDT_ENABLE_TEST);
+-	if (ret)
+-		return ret;
+-
+-	val = phy_read_mmd(phydev, MDIO_MMD_PCS, QCA808X_MMD3_CDT_STATUS);
+-	if (val < 0)
+-		return val;
+-
+-	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_A, val);
+-	if (ret)
+-		return ret;
+-
+-	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_B, val);
+-	if (ret)
+-		return ret;
+-
+-	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_C, val);
+-	if (ret)
+-		return ret;
+-
+-	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_D, val);
+-	if (ret)
+-		return ret;
+-
+-	*finished = true;
+-
+-	return 0;
+-}
+-
+-static int qca808x_get_features(struct phy_device *phydev)
+-{
+-	int ret;
+-
+-	ret = genphy_c45_pma_read_abilities(phydev);
+-	if (ret)
+-		return ret;
+-
+-	/* The autoneg ability is not existed in bit3 of MMD7.1,
+-	 * but it is supported by qca808x PHY, so we add it here
+-	 * manually.
+-	 */
+-	linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
+-
+-	/* As for the qca8081 1G version chip, the 2500baseT ability is also
+-	 * existed in the bit0 of MMD1.21, we need to remove it manually if
+-	 * it is the qca8081 1G chip according to the bit0 of MMD7.0x901d.
+-	 */
+-	ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_CHIP_TYPE);
+-	if (ret < 0)
+-		return ret;
+-
+-	if (QCA808X_PHY_CHIP_TYPE_1G & ret)
+-		linkmode_clear_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported);
+-
+-	return 0;
+-}
+-
+-static int qca808x_config_aneg(struct phy_device *phydev)
+-{
+-	int phy_ctrl = 0;
+-	int ret;
+-
+-	ret = at803x_prepare_config_aneg(phydev);
+-	if (ret)
+-		return ret;
+-
+-	/* The reg MII_BMCR also needs to be configured for force mode, the
+-	 * genphy_config_aneg is also needed.
+-	 */
+-	if (phydev->autoneg == AUTONEG_DISABLE)
+-		genphy_c45_pma_setup_forced(phydev);
+-
+-	if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->advertising))
+-		phy_ctrl = MDIO_AN_10GBT_CTRL_ADV2_5G;
+-
+-	ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
+-				     MDIO_AN_10GBT_CTRL_ADV2_5G, phy_ctrl);
+-	if (ret < 0)
+-		return ret;
+-
+-	return __genphy_config_aneg(phydev, ret);
+-}
+-
+-static void qca808x_link_change_notify(struct phy_device *phydev)
+-{
+-	/* Assert interface sgmii fifo on link down, deassert it on link up,
+-	 * the interface device address is always phy address added by 1.
+-	 */
+-	mdiobus_c45_modify_changed(phydev->mdio.bus, phydev->mdio.addr + 1,
+-				   MDIO_MMD_PMAPMD, QCA8081_PHY_SERDES_MMD1_FIFO_CTRL,
+-				   QCA8081_PHY_FIFO_RSTN,
+-				   phydev->link ? QCA8081_PHY_FIFO_RSTN : 0);
+-}
+-
+-static int qca808x_led_parse_netdev(struct phy_device *phydev, unsigned long rules,
+-				    u16 *offload_trigger)
+-{
+-	/* Parsing specific to netdev trigger */
+-	if (test_bit(TRIGGER_NETDEV_TX, &rules))
+-		*offload_trigger |= QCA808X_LED_TX_BLINK;
+-	if (test_bit(TRIGGER_NETDEV_RX, &rules))
+-		*offload_trigger |= QCA808X_LED_RX_BLINK;
+-	if (test_bit(TRIGGER_NETDEV_LINK_10, &rules))
+-		*offload_trigger |= QCA808X_LED_SPEED10_ON;
+-	if (test_bit(TRIGGER_NETDEV_LINK_100, &rules))
+-		*offload_trigger |= QCA808X_LED_SPEED100_ON;
+-	if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules))
+-		*offload_trigger |= QCA808X_LED_SPEED1000_ON;
+-	if (test_bit(TRIGGER_NETDEV_LINK_2500, &rules))
+-		*offload_trigger |= QCA808X_LED_SPEED2500_ON;
+-	if (test_bit(TRIGGER_NETDEV_HALF_DUPLEX, &rules))
+-		*offload_trigger |= QCA808X_LED_HALF_DUPLEX_ON;
+-	if (test_bit(TRIGGER_NETDEV_FULL_DUPLEX, &rules))
+-		*offload_trigger |= QCA808X_LED_FULL_DUPLEX_ON;
+-
+-	if (rules && !*offload_trigger)
+-		return -EOPNOTSUPP;
+-
+-	/* Enable BLINK_CHECK_BYPASS by default to make the LED
+-	 * blink even with duplex or speed mode not enabled.
+-	 */
+-	*offload_trigger |= QCA808X_LED_BLINK_CHECK_BYPASS;
+-
+-	return 0;
+-}
+-
+-static int qca808x_led_hw_control_enable(struct phy_device *phydev, u8 index)
+-{
+-	u16 reg;
+-
+-	if (index > 2)
+-		return -EINVAL;
+-
+-	reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
+-
+-	return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg,
+-				  QCA808X_LED_FORCE_EN);
+-}
+-
+-static int qca808x_led_hw_is_supported(struct phy_device *phydev, u8 index,
+-				       unsigned long rules)
+-{
+-	u16 offload_trigger = 0;
+-
+-	if (index > 2)
+-		return -EINVAL;
+-
+-	return qca808x_led_parse_netdev(phydev, rules, &offload_trigger);
+-}
+-
+-static int qca808x_led_hw_control_set(struct phy_device *phydev, u8 index,
+-				      unsigned long rules)
+-{
+-	u16 reg, offload_trigger = 0;
+-	int ret;
+-
+-	if (index > 2)
+-		return -EINVAL;
+-
+-	reg = QCA808X_MMD7_LED_CTRL(index);
+-
+-	ret = qca808x_led_parse_netdev(phydev, rules, &offload_trigger);
+-	if (ret)
+-		return ret;
+-
+-	ret = qca808x_led_hw_control_enable(phydev, index);
+-	if (ret)
+-		return ret;
+-
+-	return phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
+-			      QCA808X_LED_PATTERN_MASK,
+-			      offload_trigger);
+-}
+-
+-static bool qca808x_led_hw_control_status(struct phy_device *phydev, u8 index)
+-{
+-	u16 reg;
+-	int val;
+-
+-	if (index > 2)
+-		return false;
+-
+-	reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
+-
+-	val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
+-
+-	return !(val & QCA808X_LED_FORCE_EN);
+-}
+-
+-static int qca808x_led_hw_control_get(struct phy_device *phydev, u8 index,
+-				      unsigned long *rules)
+-{
+-	u16 reg;
+-	int val;
+-
+-	if (index > 2)
+-		return -EINVAL;
+-
+-	/* Check if we have hw control enabled */
+-	if (qca808x_led_hw_control_status(phydev, index))
+-		return -EINVAL;
+-
+-	reg = QCA808X_MMD7_LED_CTRL(index);
+-
+-	val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
+-	if (val & QCA808X_LED_TX_BLINK)
+-		set_bit(TRIGGER_NETDEV_TX, rules);
+-	if (val & QCA808X_LED_RX_BLINK)
+-		set_bit(TRIGGER_NETDEV_RX, rules);
+-	if (val & QCA808X_LED_SPEED10_ON)
+-		set_bit(TRIGGER_NETDEV_LINK_10, rules);
+-	if (val & QCA808X_LED_SPEED100_ON)
+-		set_bit(TRIGGER_NETDEV_LINK_100, rules);
+-	if (val & QCA808X_LED_SPEED1000_ON)
+-		set_bit(TRIGGER_NETDEV_LINK_1000, rules);
+-	if (val & QCA808X_LED_SPEED2500_ON)
+-		set_bit(TRIGGER_NETDEV_LINK_2500, rules);
+-	if (val & QCA808X_LED_HALF_DUPLEX_ON)
+-		set_bit(TRIGGER_NETDEV_HALF_DUPLEX, rules);
+-	if (val & QCA808X_LED_FULL_DUPLEX_ON)
+-		set_bit(TRIGGER_NETDEV_FULL_DUPLEX, rules);
+-
+-	return 0;
+-}
+-
+-static int qca808x_led_hw_control_reset(struct phy_device *phydev, u8 index)
+-{
+-	u16 reg;
+-
+-	if (index > 2)
+-		return -EINVAL;
+-
+-	reg = QCA808X_MMD7_LED_CTRL(index);
+-
+-	return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg,
+-				  QCA808X_LED_PATTERN_MASK);
+-}
+-
+-static int qca808x_led_brightness_set(struct phy_device *phydev,
+-				      u8 index, enum led_brightness value)
+-{
+-	u16 reg;
+-	int ret;
+-
+-	if (index > 2)
+-		return -EINVAL;
+-
+-	if (!value) {
+-		ret = qca808x_led_hw_control_reset(phydev, index);
+-		if (ret)
+-			return ret;
+-	}
+-
+-	reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
+-
+-	return phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
+-			      QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_MODE_MASK,
+-			      QCA808X_LED_FORCE_EN | value ? QCA808X_LED_FORCE_ON :
+-							     QCA808X_LED_FORCE_OFF);
+-}
+-
+-static int qca808x_led_blink_set(struct phy_device *phydev, u8 index,
+-				 unsigned long *delay_on,
+-				 unsigned long *delay_off)
+-{
+-	int ret;
+-	u16 reg;
+-
+-	if (index > 2)
+-		return -EINVAL;
+-
+-	reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
+-
+-	/* Set blink to 50% off, 50% on at 4Hz by default */
+-	ret = phy_modify_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_LED_GLOBAL,
+-			     QCA808X_LED_BLINK_FREQ_MASK | QCA808X_LED_BLINK_DUTY_MASK,
+-			     QCA808X_LED_BLINK_FREQ_4HZ | QCA808X_LED_BLINK_DUTY_50_50);
+-	if (ret)
+-		return ret;
+-
+-	/* We use BLINK_1 for normal blinking */
+-	ret = phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
+-			     QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_MODE_MASK,
+-			     QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_BLINK_1);
+-	if (ret)
+-		return ret;
+-
+-	/* We set blink to 4Hz, aka 250ms */
+-	*delay_on = 250 / 2;
+-	*delay_off = 250 / 2;
+-
+-	return 0;
+-}
+-
+-static int qca808x_led_polarity_set(struct phy_device *phydev, int index,
+-				    unsigned long modes)
+-{
+-	struct at803x_priv *priv = phydev->priv;
+-	bool active_low = false;
+-	u32 mode;
+-
+-	for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) {
+-		switch (mode) {
+-		case PHY_LED_ACTIVE_LOW:
+-			active_low = true;
+-			break;
+-		default:
+-			return -EINVAL;
+-		}
+-	}
+-
+-	/* PHY polarity is global and can't be set per LED.
+-	 * To detect this, check if last requested polarity mode
+-	 * match the new one.
+-	 */
+-	if (priv->led_polarity_mode >= 0 &&
+-	    priv->led_polarity_mode != active_low) {
+-		phydev_err(phydev, "PHY polarity is global. Mismatched polarity on different LED\n");
+-		return -EINVAL;
+-	}
+-
+-	/* Save the last PHY polarity mode */
+-	priv->led_polarity_mode = active_low;
+-
+-	return phy_modify_mmd(phydev, MDIO_MMD_AN,
+-			      QCA808X_MMD7_LED_POLARITY_CTRL,
+-			      QCA808X_LED_ACTIVE_HIGH,
+-			      active_low ? 0 : QCA808X_LED_ACTIVE_HIGH);
+-}
+-
+ static struct phy_driver at803x_driver[] = {
+ {
+ 	/* Qualcomm Atheros AR8035 */
+@@ -1989,34 +1123,6 @@ static struct phy_driver at803x_driver[]
+ 	.read_status		= at803x_read_status,
+ 	.soft_reset		= genphy_soft_reset,
+ 	.config_aneg		= at803x_config_aneg,
+-}, {
+-	/* Qualcomm QCA8081 */
+-	PHY_ID_MATCH_EXACT(QCA8081_PHY_ID),
+-	.name			= "Qualcomm QCA8081",
+-	.flags			= PHY_POLL_CABLE_TEST,
+-	.probe			= at803x_probe,
+-	.config_intr		= at803x_config_intr,
+-	.handle_interrupt	= at803x_handle_interrupt,
+-	.get_tunable		= at803x_get_tunable,
+-	.set_tunable		= at803x_set_tunable,
+-	.set_wol		= at803x_set_wol,
+-	.get_wol		= at803x_get_wol,
+-	.get_features		= qca808x_get_features,
+-	.config_aneg		= qca808x_config_aneg,
+-	.suspend		= genphy_suspend,
+-	.resume			= genphy_resume,
+-	.read_status		= qca808x_read_status,
+-	.config_init		= qca808x_config_init,
+-	.soft_reset		= qca808x_soft_reset,
+-	.cable_test_start	= qca808x_cable_test_start,
+-	.cable_test_get_status	= qca808x_cable_test_get_status,
+-	.link_change_notify	= qca808x_link_change_notify,
+-	.led_brightness_set	= qca808x_led_brightness_set,
+-	.led_blink_set		= qca808x_led_blink_set,
+-	.led_hw_is_supported	= qca808x_led_hw_is_supported,
+-	.led_hw_control_set	= qca808x_led_hw_control_set,
+-	.led_hw_control_get	= qca808x_led_hw_control_get,
+-	.led_polarity_set	= qca808x_led_polarity_set,
+ }, };
+ 
+ module_phy_driver(at803x_driver);
+@@ -2028,7 +1134,6 @@ static struct mdio_device_id __maybe_unu
+ 	{ PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) },
+ 	{ PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) },
+ 	{ PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) },
+-	{ PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) },
+ 	{ }
+ };
+ 
+--- /dev/null
++++ b/drivers/net/phy/qcom/qca808x.c
+@@ -0,0 +1,934 @@
++// SPDX-License-Identifier: GPL-2.0+
++
++#include <linux/phy.h>
++#include <linux/module.h>
++#include <linux/ethtool_netlink.h>
++
++#include "qcom.h"
++
++/* ADC threshold */
++#define QCA808X_PHY_DEBUG_ADC_THRESHOLD		0x2c80
++#define QCA808X_ADC_THRESHOLD_MASK		GENMASK(7, 0)
++#define QCA808X_ADC_THRESHOLD_80MV		0
++#define QCA808X_ADC_THRESHOLD_100MV		0xf0
++#define QCA808X_ADC_THRESHOLD_200MV		0x0f
++#define QCA808X_ADC_THRESHOLD_300MV		0xff
++
++/* CLD control */
++#define QCA808X_PHY_MMD3_ADDR_CLD_CTRL7		0x8007
++#define QCA808X_8023AZ_AFE_CTRL_MASK		GENMASK(8, 4)
++#define QCA808X_8023AZ_AFE_EN			0x90
++
++/* AZ control */
++#define QCA808X_PHY_MMD3_AZ_TRAINING_CTRL	0x8008
++#define QCA808X_MMD3_AZ_TRAINING_VAL		0x1c32
++
++#define QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB	0x8014
++#define QCA808X_MSE_THRESHOLD_20DB_VALUE	0x529
++
++#define QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB	0x800E
++#define QCA808X_MSE_THRESHOLD_17DB_VALUE	0x341
++
++#define QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB	0x801E
++#define QCA808X_MSE_THRESHOLD_27DB_VALUE	0x419
++
++#define QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB	0x8020
++#define QCA808X_MSE_THRESHOLD_28DB_VALUE	0x341
++
++#define QCA808X_PHY_MMD7_TOP_OPTION1		0x901c
++#define QCA808X_TOP_OPTION1_DATA		0x0
++
++#define QCA808X_PHY_MMD3_DEBUG_1		0xa100
++#define QCA808X_MMD3_DEBUG_1_VALUE		0x9203
++#define QCA808X_PHY_MMD3_DEBUG_2		0xa101
++#define QCA808X_MMD3_DEBUG_2_VALUE		0x48ad
++#define QCA808X_PHY_MMD3_DEBUG_3		0xa103
++#define QCA808X_MMD3_DEBUG_3_VALUE		0x1698
++#define QCA808X_PHY_MMD3_DEBUG_4		0xa105
++#define QCA808X_MMD3_DEBUG_4_VALUE		0x8001
++#define QCA808X_PHY_MMD3_DEBUG_5		0xa106
++#define QCA808X_MMD3_DEBUG_5_VALUE		0x1111
++#define QCA808X_PHY_MMD3_DEBUG_6		0xa011
++#define QCA808X_MMD3_DEBUG_6_VALUE		0x5f85
++
++/* master/slave seed config */
++#define QCA808X_PHY_DEBUG_LOCAL_SEED		9
++#define QCA808X_MASTER_SLAVE_SEED_ENABLE	BIT(1)
++#define QCA808X_MASTER_SLAVE_SEED_CFG		GENMASK(12, 2)
++#define QCA808X_MASTER_SLAVE_SEED_RANGE		0x32
++
++/* Hibernation yields lower power consumpiton in contrast with normal operation mode.
++ * when the copper cable is unplugged, the PHY enters into hibernation mode in about 10s.
++ */
++#define QCA808X_DBG_AN_TEST			0xb
++#define QCA808X_HIBERNATION_EN			BIT(15)
++
++#define QCA808X_CDT_ENABLE_TEST			BIT(15)
++#define QCA808X_CDT_INTER_CHECK_DIS		BIT(13)
++#define QCA808X_CDT_STATUS			BIT(11)
++#define QCA808X_CDT_LENGTH_UNIT			BIT(10)
++
++#define QCA808X_MMD3_CDT_STATUS			0x8064
++#define QCA808X_MMD3_CDT_DIAG_PAIR_A		0x8065
++#define QCA808X_MMD3_CDT_DIAG_PAIR_B		0x8066
++#define QCA808X_MMD3_CDT_DIAG_PAIR_C		0x8067
++#define QCA808X_MMD3_CDT_DIAG_PAIR_D		0x8068
++#define QCA808X_CDT_DIAG_LENGTH_SAME_SHORT	GENMASK(15, 8)
++#define QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT	GENMASK(7, 0)
++
++#define QCA808X_CDT_CODE_PAIR_A			GENMASK(15, 12)
++#define QCA808X_CDT_CODE_PAIR_B			GENMASK(11, 8)
++#define QCA808X_CDT_CODE_PAIR_C			GENMASK(7, 4)
++#define QCA808X_CDT_CODE_PAIR_D			GENMASK(3, 0)
++
++#define QCA808X_CDT_STATUS_STAT_TYPE		GENMASK(1, 0)
++#define QCA808X_CDT_STATUS_STAT_FAIL		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 0)
++#define QCA808X_CDT_STATUS_STAT_NORMAL		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 1)
++#define QCA808X_CDT_STATUS_STAT_SAME_OPEN	FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 2)
++#define QCA808X_CDT_STATUS_STAT_SAME_SHORT	FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 3)
++
++#define QCA808X_CDT_STATUS_STAT_MDI		GENMASK(3, 2)
++#define QCA808X_CDT_STATUS_STAT_MDI1		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 1)
++#define QCA808X_CDT_STATUS_STAT_MDI2		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 2)
++#define QCA808X_CDT_STATUS_STAT_MDI3		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 3)
++
++/* NORMAL are MDI with type set to 0 */
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL	QCA808X_CDT_STATUS_STAT_MDI1
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN		(QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
++									 QCA808X_CDT_STATUS_STAT_MDI1)
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT	(QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
++									 QCA808X_CDT_STATUS_STAT_MDI1)
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL	QCA808X_CDT_STATUS_STAT_MDI2
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN		(QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
++									 QCA808X_CDT_STATUS_STAT_MDI2)
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT	(QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
++									 QCA808X_CDT_STATUS_STAT_MDI2)
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL	QCA808X_CDT_STATUS_STAT_MDI3
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN		(QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
++									 QCA808X_CDT_STATUS_STAT_MDI3)
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT	(QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
++									 QCA808X_CDT_STATUS_STAT_MDI3)
++
++/* Added for reference of existence but should be handled by wait_for_completion already */
++#define QCA808X_CDT_STATUS_STAT_BUSY		(BIT(1) | BIT(3))
++
++#define QCA808X_MMD7_LED_GLOBAL			0x8073
++#define QCA808X_LED_BLINK_1			GENMASK(11, 6)
++#define QCA808X_LED_BLINK_2			GENMASK(5, 0)
++/* Values are the same for both BLINK_1 and BLINK_2 */
++#define QCA808X_LED_BLINK_FREQ_MASK		GENMASK(5, 3)
++#define QCA808X_LED_BLINK_FREQ_2HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x0)
++#define QCA808X_LED_BLINK_FREQ_4HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x1)
++#define QCA808X_LED_BLINK_FREQ_8HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x2)
++#define QCA808X_LED_BLINK_FREQ_16HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x3)
++#define QCA808X_LED_BLINK_FREQ_32HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x4)
++#define QCA808X_LED_BLINK_FREQ_64HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x5)
++#define QCA808X_LED_BLINK_FREQ_128HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x6)
++#define QCA808X_LED_BLINK_FREQ_256HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x7)
++#define QCA808X_LED_BLINK_DUTY_MASK		GENMASK(2, 0)
++#define QCA808X_LED_BLINK_DUTY_50_50		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x0)
++#define QCA808X_LED_BLINK_DUTY_75_25		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x1)
++#define QCA808X_LED_BLINK_DUTY_25_75		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x2)
++#define QCA808X_LED_BLINK_DUTY_33_67		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x3)
++#define QCA808X_LED_BLINK_DUTY_67_33		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x4)
++#define QCA808X_LED_BLINK_DUTY_17_83		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x5)
++#define QCA808X_LED_BLINK_DUTY_83_17		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x6)
++#define QCA808X_LED_BLINK_DUTY_8_92		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x7)
++
++#define QCA808X_MMD7_LED2_CTRL			0x8074
++#define QCA808X_MMD7_LED2_FORCE_CTRL		0x8075
++#define QCA808X_MMD7_LED1_CTRL			0x8076
++#define QCA808X_MMD7_LED1_FORCE_CTRL		0x8077
++#define QCA808X_MMD7_LED0_CTRL			0x8078
++#define QCA808X_MMD7_LED_CTRL(x)		(0x8078 - ((x) * 2))
++
++/* LED hw control pattern is the same for every LED */
++#define QCA808X_LED_PATTERN_MASK		GENMASK(15, 0)
++#define QCA808X_LED_SPEED2500_ON		BIT(15)
++#define QCA808X_LED_SPEED2500_BLINK		BIT(14)
++/* Follow blink trigger even if duplex or speed condition doesn't match */
++#define QCA808X_LED_BLINK_CHECK_BYPASS		BIT(13)
++#define QCA808X_LED_FULL_DUPLEX_ON		BIT(12)
++#define QCA808X_LED_HALF_DUPLEX_ON		BIT(11)
++#define QCA808X_LED_TX_BLINK			BIT(10)
++#define QCA808X_LED_RX_BLINK			BIT(9)
++#define QCA808X_LED_TX_ON_10MS			BIT(8)
++#define QCA808X_LED_RX_ON_10MS			BIT(7)
++#define QCA808X_LED_SPEED1000_ON		BIT(6)
++#define QCA808X_LED_SPEED100_ON			BIT(5)
++#define QCA808X_LED_SPEED10_ON			BIT(4)
++#define QCA808X_LED_COLLISION_BLINK		BIT(3)
++#define QCA808X_LED_SPEED1000_BLINK		BIT(2)
++#define QCA808X_LED_SPEED100_BLINK		BIT(1)
++#define QCA808X_LED_SPEED10_BLINK		BIT(0)
++
++#define QCA808X_MMD7_LED0_FORCE_CTRL		0x8079
++#define QCA808X_MMD7_LED_FORCE_CTRL(x)		(0x8079 - ((x) * 2))
++
++/* LED force ctrl is the same for every LED
++ * No documentation exist for this, not even internal one
++ * with NDA as QCOM gives only info about configuring
++ * hw control pattern rules and doesn't indicate any way
++ * to force the LED to specific mode.
++ * These define comes from reverse and testing and maybe
++ * lack of some info or some info are not entirely correct.
++ * For the basic LED control and hw control these finding
++ * are enough to support LED control in all the required APIs.
++ *
++ * On doing some comparison with implementation with qca807x,
++ * it was found that it's 1:1 equal to it and confirms all the
++ * reverse done. It was also found further specification with the
++ * force mode and the blink modes.
++ */
++#define QCA808X_LED_FORCE_EN			BIT(15)
++#define QCA808X_LED_FORCE_MODE_MASK		GENMASK(14, 13)
++#define QCA808X_LED_FORCE_BLINK_1		FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x3)
++#define QCA808X_LED_FORCE_BLINK_2		FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x2)
++#define QCA808X_LED_FORCE_ON			FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x1)
++#define QCA808X_LED_FORCE_OFF			FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x0)
++
++#define QCA808X_MMD7_LED_POLARITY_CTRL		0x901a
++/* QSDK sets by default 0x46 to this reg that sets BIT 6 for
++ * LED to active high. It's not clear what BIT 3 and BIT 4 does.
++ */
++#define QCA808X_LED_ACTIVE_HIGH			BIT(6)
++
++/* QCA808X 1G chip type */
++#define QCA808X_PHY_MMD7_CHIP_TYPE		0x901d
++#define QCA808X_PHY_CHIP_TYPE_1G		BIT(0)
++
++#define QCA8081_PHY_SERDES_MMD1_FIFO_CTRL	0x9072
++#define QCA8081_PHY_FIFO_RSTN			BIT(11)
++
++#define QCA8081_PHY_ID				0x004dd101
++
++MODULE_DESCRIPTION("Qualcomm Atheros QCA808X PHY driver");
++MODULE_AUTHOR("Matus Ujhelyi");
++MODULE_LICENSE("GPL");
++
++struct qca808x_priv {
++	int led_polarity_mode;
++};
++
++static int qca808x_phy_fast_retrain_config(struct phy_device *phydev)
++{
++	int ret;
++
++	/* Enable fast retrain */
++	ret = genphy_c45_fast_retrain(phydev, true);
++	if (ret)
++		return ret;
++
++	phy_write_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_TOP_OPTION1,
++		      QCA808X_TOP_OPTION1_DATA);
++	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB,
++		      QCA808X_MSE_THRESHOLD_20DB_VALUE);
++	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB,
++		      QCA808X_MSE_THRESHOLD_17DB_VALUE);
++	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB,
++		      QCA808X_MSE_THRESHOLD_27DB_VALUE);
++	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB,
++		      QCA808X_MSE_THRESHOLD_28DB_VALUE);
++	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_1,
++		      QCA808X_MMD3_DEBUG_1_VALUE);
++	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_4,
++		      QCA808X_MMD3_DEBUG_4_VALUE);
++	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_5,
++		      QCA808X_MMD3_DEBUG_5_VALUE);
++	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_3,
++		      QCA808X_MMD3_DEBUG_3_VALUE);
++	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_6,
++		      QCA808X_MMD3_DEBUG_6_VALUE);
++	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_2,
++		      QCA808X_MMD3_DEBUG_2_VALUE);
++
++	return 0;
++}
++
++static int qca808x_phy_ms_seed_enable(struct phy_device *phydev, bool enable)
++{
++	u16 seed_value;
++
++	if (!enable)
++		return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED,
++				QCA808X_MASTER_SLAVE_SEED_ENABLE, 0);
++
++	seed_value = prandom_u32_max(QCA808X_MASTER_SLAVE_SEED_RANGE);
++	return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED,
++			QCA808X_MASTER_SLAVE_SEED_CFG | QCA808X_MASTER_SLAVE_SEED_ENABLE,
++			FIELD_PREP(QCA808X_MASTER_SLAVE_SEED_CFG, seed_value) |
++			QCA808X_MASTER_SLAVE_SEED_ENABLE);
++}
++
++static bool qca808x_is_prefer_master(struct phy_device *phydev)
++{
++	return (phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_FORCE) ||
++		(phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_PREFERRED);
++}
++
++static bool qca808x_has_fast_retrain_or_slave_seed(struct phy_device *phydev)
++{
++	return linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported);
++}
++
++static int qca808x_probe(struct phy_device *phydev)
++{
++	struct device *dev = &phydev->mdio.dev;
++	struct qca808x_priv *priv;
++
++	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
++	if (!priv)
++		return -ENOMEM;
++
++	/* Init LED polarity mode to -1 */
++	priv->led_polarity_mode = -1;
++
++	phydev->priv = priv;
++
++	return 0;
++}
++
++static int qca808x_config_init(struct phy_device *phydev)
++{
++	int ret;
++
++	/* Active adc&vga on 802.3az for the link 1000M and 100M */
++	ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_ADDR_CLD_CTRL7,
++			     QCA808X_8023AZ_AFE_CTRL_MASK, QCA808X_8023AZ_AFE_EN);
++	if (ret)
++		return ret;
++
++	/* Adjust the threshold on 802.3az for the link 1000M */
++	ret = phy_write_mmd(phydev, MDIO_MMD_PCS,
++			    QCA808X_PHY_MMD3_AZ_TRAINING_CTRL,
++			    QCA808X_MMD3_AZ_TRAINING_VAL);
++	if (ret)
++		return ret;
++
++	if (qca808x_has_fast_retrain_or_slave_seed(phydev)) {
++		/* Config the fast retrain for the link 2500M */
++		ret = qca808x_phy_fast_retrain_config(phydev);
++		if (ret)
++			return ret;
++
++		ret = genphy_read_master_slave(phydev);
++		if (ret < 0)
++			return ret;
++
++		if (!qca808x_is_prefer_master(phydev)) {
++			/* Enable seed and configure lower ramdom seed to make phy
++			 * linked as slave mode.
++			 */
++			ret = qca808x_phy_ms_seed_enable(phydev, true);
++			if (ret)
++				return ret;
++		}
++	}
++
++	/* Configure adc threshold as 100mv for the link 10M */
++	return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD,
++				     QCA808X_ADC_THRESHOLD_MASK,
++				     QCA808X_ADC_THRESHOLD_100MV);
++}
++
++static int qca808x_read_status(struct phy_device *phydev)
++{
++	struct at803x_ss_mask ss_mask = { 0 };
++	int ret;
++
++	ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);
++	if (ret < 0)
++		return ret;
++
++	linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->lp_advertising,
++			 ret & MDIO_AN_10GBT_STAT_LP2_5G);
++
++	ret = genphy_read_status(phydev);
++	if (ret)
++		return ret;
++
++	/* qca8081 takes the different bits for speed value from at803x */
++	ss_mask.speed_mask = QCA808X_SS_SPEED_MASK;
++	ss_mask.speed_shift = __bf_shf(QCA808X_SS_SPEED_MASK);
++	ret = at803x_read_specific_status(phydev, ss_mask);
++	if (ret < 0)
++		return ret;
++
++	if (phydev->link) {
++		if (phydev->speed == SPEED_2500)
++			phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
++		else
++			phydev->interface = PHY_INTERFACE_MODE_SGMII;
++	} else {
++		/* generate seed as a lower random value to make PHY linked as SLAVE easily,
++		 * except for master/slave configuration fault detected or the master mode
++		 * preferred.
++		 *
++		 * the reason for not putting this code into the function link_change_notify is
++		 * the corner case where the link partner is also the qca8081 PHY and the seed
++		 * value is configured as the same value, the link can't be up and no link change
++		 * occurs.
++		 */
++		if (qca808x_has_fast_retrain_or_slave_seed(phydev)) {
++			if (phydev->master_slave_state == MASTER_SLAVE_STATE_ERR ||
++			    qca808x_is_prefer_master(phydev)) {
++				qca808x_phy_ms_seed_enable(phydev, false);
++			} else {
++				qca808x_phy_ms_seed_enable(phydev, true);
++			}
++		}
++	}
++
++	return 0;
++}
++
++static int qca808x_soft_reset(struct phy_device *phydev)
++{
++	int ret;
++
++	ret = genphy_soft_reset(phydev);
++	if (ret < 0)
++		return ret;
++
++	if (qca808x_has_fast_retrain_or_slave_seed(phydev))
++		ret = qca808x_phy_ms_seed_enable(phydev, true);
++
++	return ret;
++}
++
++static bool qca808x_cdt_fault_length_valid(int cdt_code)
++{
++	switch (cdt_code) {
++	case QCA808X_CDT_STATUS_STAT_SAME_SHORT:
++	case QCA808X_CDT_STATUS_STAT_SAME_OPEN:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT:
++		return true;
++	default:
++		return false;
++	}
++}
++
++static int qca808x_cable_test_result_trans(int cdt_code)
++{
++	switch (cdt_code) {
++	case QCA808X_CDT_STATUS_STAT_NORMAL:
++		return ETHTOOL_A_CABLE_RESULT_CODE_OK;
++	case QCA808X_CDT_STATUS_STAT_SAME_SHORT:
++		return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
++	case QCA808X_CDT_STATUS_STAT_SAME_OPEN:
++		return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT:
++		return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;
++	case QCA808X_CDT_STATUS_STAT_FAIL:
++	default:
++		return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
++	}
++}
++
++static int qca808x_cdt_fault_length(struct phy_device *phydev, int pair,
++				    int result)
++{
++	int val;
++	u32 cdt_length_reg = 0;
++
++	switch (pair) {
++	case ETHTOOL_A_CABLE_PAIR_A:
++		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_A;
++		break;
++	case ETHTOOL_A_CABLE_PAIR_B:
++		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_B;
++		break;
++	case ETHTOOL_A_CABLE_PAIR_C:
++		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_C;
++		break;
++	case ETHTOOL_A_CABLE_PAIR_D:
++		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_D;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	val = phy_read_mmd(phydev, MDIO_MMD_PCS, cdt_length_reg);
++	if (val < 0)
++		return val;
++
++	if (result == ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT)
++		val = FIELD_GET(QCA808X_CDT_DIAG_LENGTH_SAME_SHORT, val);
++	else
++		val = FIELD_GET(QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT, val);
++
++	return at803x_cdt_fault_length(val);
++}
++
++static int qca808x_cable_test_start(struct phy_device *phydev)
++{
++	int ret;
++
++	/* perform CDT with the following configs:
++	 * 1. disable hibernation.
++	 * 2. force PHY working in MDI mode.
++	 * 3. for PHY working in 1000BaseT.
++	 * 4. configure the threshold.
++	 */
++
++	ret = at803x_debug_reg_mask(phydev, QCA808X_DBG_AN_TEST, QCA808X_HIBERNATION_EN, 0);
++	if (ret < 0)
++		return ret;
++
++	ret = at803x_config_mdix(phydev, ETH_TP_MDI);
++	if (ret < 0)
++		return ret;
++
++	/* Force 1000base-T needs to configure PMA/PMD and MII_BMCR */
++	phydev->duplex = DUPLEX_FULL;
++	phydev->speed = SPEED_1000;
++	ret = genphy_c45_pma_setup_forced(phydev);
++	if (ret < 0)
++		return ret;
++
++	ret = genphy_setup_forced(phydev);
++	if (ret < 0)
++		return ret;
++
++	/* configure the thresholds for open, short, pair ok test */
++	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8074, 0xc040);
++	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8076, 0xc040);
++	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8077, 0xa060);
++	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8078, 0xc050);
++	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060);
++	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807e, 0xb060);
++
++	return 0;
++}
++
++static int qca808x_cable_test_get_pair_status(struct phy_device *phydev, u8 pair,
++					      u16 status)
++{
++	int length, result;
++	u16 pair_code;
++
++	switch (pair) {
++	case ETHTOOL_A_CABLE_PAIR_A:
++		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_A, status);
++		break;
++	case ETHTOOL_A_CABLE_PAIR_B:
++		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_B, status);
++		break;
++	case ETHTOOL_A_CABLE_PAIR_C:
++		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_C, status);
++		break;
++	case ETHTOOL_A_CABLE_PAIR_D:
++		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_D, status);
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	result = qca808x_cable_test_result_trans(pair_code);
++	ethnl_cable_test_result(phydev, pair, result);
++
++	if (qca808x_cdt_fault_length_valid(pair_code)) {
++		length = qca808x_cdt_fault_length(phydev, pair, result);
++		ethnl_cable_test_fault_length(phydev, pair, length);
++	}
++
++	return 0;
++}
++
++static int qca808x_cable_test_get_status(struct phy_device *phydev, bool *finished)
++{
++	int ret, val;
++
++	*finished = false;
++
++	val = QCA808X_CDT_ENABLE_TEST |
++	      QCA808X_CDT_LENGTH_UNIT;
++	ret = at803x_cdt_start(phydev, val);
++	if (ret)
++		return ret;
++
++	ret = at803x_cdt_wait_for_completion(phydev, QCA808X_CDT_ENABLE_TEST);
++	if (ret)
++		return ret;
++
++	val = phy_read_mmd(phydev, MDIO_MMD_PCS, QCA808X_MMD3_CDT_STATUS);
++	if (val < 0)
++		return val;
++
++	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_A, val);
++	if (ret)
++		return ret;
++
++	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_B, val);
++	if (ret)
++		return ret;
++
++	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_C, val);
++	if (ret)
++		return ret;
++
++	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_D, val);
++	if (ret)
++		return ret;
++
++	*finished = true;
++
++	return 0;
++}
++
++static int qca808x_get_features(struct phy_device *phydev)
++{
++	int ret;
++
++	ret = genphy_c45_pma_read_abilities(phydev);
++	if (ret)
++		return ret;
++
++	/* The autoneg ability is not existed in bit3 of MMD7.1,
++	 * but it is supported by qca808x PHY, so we add it here
++	 * manually.
++	 */
++	linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
++
++	/* As for the qca8081 1G version chip, the 2500baseT ability is also
++	 * existed in the bit0 of MMD1.21, we need to remove it manually if
++	 * it is the qca8081 1G chip according to the bit0 of MMD7.0x901d.
++	 */
++	ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_CHIP_TYPE);
++	if (ret < 0)
++		return ret;
++
++	if (QCA808X_PHY_CHIP_TYPE_1G & ret)
++		linkmode_clear_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported);
++
++	return 0;
++}
++
++static int qca808x_config_aneg(struct phy_device *phydev)
++{
++	int phy_ctrl = 0;
++	int ret;
++
++	ret = at803x_prepare_config_aneg(phydev);
++	if (ret)
++		return ret;
++
++	/* The reg MII_BMCR also needs to be configured for force mode, the
++	 * genphy_config_aneg is also needed.
++	 */
++	if (phydev->autoneg == AUTONEG_DISABLE)
++		genphy_c45_pma_setup_forced(phydev);
++
++	if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->advertising))
++		phy_ctrl = MDIO_AN_10GBT_CTRL_ADV2_5G;
++
++	ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
++				     MDIO_AN_10GBT_CTRL_ADV2_5G, phy_ctrl);
++	if (ret < 0)
++		return ret;
++
++	return __genphy_config_aneg(phydev, ret);
++}
++
++static void qca808x_link_change_notify(struct phy_device *phydev)
++{
++	/* Assert interface sgmii fifo on link down, deassert it on link up,
++	 * the interface device address is always phy address added by 1.
++	 */
++	mdiobus_c45_modify_changed(phydev->mdio.bus, phydev->mdio.addr + 1,
++				   MDIO_MMD_PMAPMD, QCA8081_PHY_SERDES_MMD1_FIFO_CTRL,
++				   QCA8081_PHY_FIFO_RSTN,
++				   phydev->link ? QCA8081_PHY_FIFO_RSTN : 0);
++}
++
++static int qca808x_led_parse_netdev(struct phy_device *phydev, unsigned long rules,
++				    u16 *offload_trigger)
++{
++	/* Parsing specific to netdev trigger */
++	if (test_bit(TRIGGER_NETDEV_TX, &rules))
++		*offload_trigger |= QCA808X_LED_TX_BLINK;
++	if (test_bit(TRIGGER_NETDEV_RX, &rules))
++		*offload_trigger |= QCA808X_LED_RX_BLINK;
++	if (test_bit(TRIGGER_NETDEV_LINK_10, &rules))
++		*offload_trigger |= QCA808X_LED_SPEED10_ON;
++	if (test_bit(TRIGGER_NETDEV_LINK_100, &rules))
++		*offload_trigger |= QCA808X_LED_SPEED100_ON;
++	if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules))
++		*offload_trigger |= QCA808X_LED_SPEED1000_ON;
++	if (test_bit(TRIGGER_NETDEV_LINK_2500, &rules))
++		*offload_trigger |= QCA808X_LED_SPEED2500_ON;
++	if (test_bit(TRIGGER_NETDEV_HALF_DUPLEX, &rules))
++		*offload_trigger |= QCA808X_LED_HALF_DUPLEX_ON;
++	if (test_bit(TRIGGER_NETDEV_FULL_DUPLEX, &rules))
++		*offload_trigger |= QCA808X_LED_FULL_DUPLEX_ON;
++
++	if (rules && !*offload_trigger)
++		return -EOPNOTSUPP;
++
++	/* Enable BLINK_CHECK_BYPASS by default to make the LED
++	 * blink even with duplex or speed mode not enabled.
++	 */
++	*offload_trigger |= QCA808X_LED_BLINK_CHECK_BYPASS;
++
++	return 0;
++}
++
++static int qca808x_led_hw_control_enable(struct phy_device *phydev, u8 index)
++{
++	u16 reg;
++
++	if (index > 2)
++		return -EINVAL;
++
++	reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
++
++	return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg,
++				  QCA808X_LED_FORCE_EN);
++}
++
++static int qca808x_led_hw_is_supported(struct phy_device *phydev, u8 index,
++				       unsigned long rules)
++{
++	u16 offload_trigger = 0;
++
++	if (index > 2)
++		return -EINVAL;
++
++	return qca808x_led_parse_netdev(phydev, rules, &offload_trigger);
++}
++
++static int qca808x_led_hw_control_set(struct phy_device *phydev, u8 index,
++				      unsigned long rules)
++{
++	u16 reg, offload_trigger = 0;
++	int ret;
++
++	if (index > 2)
++		return -EINVAL;
++
++	reg = QCA808X_MMD7_LED_CTRL(index);
++
++	ret = qca808x_led_parse_netdev(phydev, rules, &offload_trigger);
++	if (ret)
++		return ret;
++
++	ret = qca808x_led_hw_control_enable(phydev, index);
++	if (ret)
++		return ret;
++
++	return phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
++			      QCA808X_LED_PATTERN_MASK,
++			      offload_trigger);
++}
++
++static bool qca808x_led_hw_control_status(struct phy_device *phydev, u8 index)
++{
++	u16 reg;
++	int val;
++
++	if (index > 2)
++		return false;
++
++	reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
++
++	val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
++
++	return !(val & QCA808X_LED_FORCE_EN);
++}
++
++static int qca808x_led_hw_control_get(struct phy_device *phydev, u8 index,
++				      unsigned long *rules)
++{
++	u16 reg;
++	int val;
++
++	if (index > 2)
++		return -EINVAL;
++
++	/* Check if we have hw control enabled */
++	if (qca808x_led_hw_control_status(phydev, index))
++		return -EINVAL;
++
++	reg = QCA808X_MMD7_LED_CTRL(index);
++
++	val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
++	if (val & QCA808X_LED_TX_BLINK)
++		set_bit(TRIGGER_NETDEV_TX, rules);
++	if (val & QCA808X_LED_RX_BLINK)
++		set_bit(TRIGGER_NETDEV_RX, rules);
++	if (val & QCA808X_LED_SPEED10_ON)
++		set_bit(TRIGGER_NETDEV_LINK_10, rules);
++	if (val & QCA808X_LED_SPEED100_ON)
++		set_bit(TRIGGER_NETDEV_LINK_100, rules);
++	if (val & QCA808X_LED_SPEED1000_ON)
++		set_bit(TRIGGER_NETDEV_LINK_1000, rules);
++	if (val & QCA808X_LED_SPEED2500_ON)
++		set_bit(TRIGGER_NETDEV_LINK_2500, rules);
++	if (val & QCA808X_LED_HALF_DUPLEX_ON)
++		set_bit(TRIGGER_NETDEV_HALF_DUPLEX, rules);
++	if (val & QCA808X_LED_FULL_DUPLEX_ON)
++		set_bit(TRIGGER_NETDEV_FULL_DUPLEX, rules);
++
++	return 0;
++}
++
++static int qca808x_led_hw_control_reset(struct phy_device *phydev, u8 index)
++{
++	u16 reg;
++
++	if (index > 2)
++		return -EINVAL;
++
++	reg = QCA808X_MMD7_LED_CTRL(index);
++
++	return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg,
++				  QCA808X_LED_PATTERN_MASK);
++}
++
++static int qca808x_led_brightness_set(struct phy_device *phydev,
++				      u8 index, enum led_brightness value)
++{
++	u16 reg;
++	int ret;
++
++	if (index > 2)
++		return -EINVAL;
++
++	if (!value) {
++		ret = qca808x_led_hw_control_reset(phydev, index);
++		if (ret)
++			return ret;
++	}
++
++	reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
++
++	return phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
++			      QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_MODE_MASK,
++			      QCA808X_LED_FORCE_EN | value ? QCA808X_LED_FORCE_ON :
++							     QCA808X_LED_FORCE_OFF);
++}
++
++static int qca808x_led_blink_set(struct phy_device *phydev, u8 index,
++				 unsigned long *delay_on,
++				 unsigned long *delay_off)
++{
++	int ret;
++	u16 reg;
++
++	if (index > 2)
++		return -EINVAL;
++
++	reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
++
++	/* Set blink to 50% off, 50% on at 4Hz by default */
++	ret = phy_modify_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_LED_GLOBAL,
++			     QCA808X_LED_BLINK_FREQ_MASK | QCA808X_LED_BLINK_DUTY_MASK,
++			     QCA808X_LED_BLINK_FREQ_4HZ | QCA808X_LED_BLINK_DUTY_50_50);
++	if (ret)
++		return ret;
++
++	/* We use BLINK_1 for normal blinking */
++	ret = phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
++			     QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_MODE_MASK,
++			     QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_BLINK_1);
++	if (ret)
++		return ret;
++
++	/* We set blink to 4Hz, aka 250ms */
++	*delay_on = 250 / 2;
++	*delay_off = 250 / 2;
++
++	return 0;
++}
++
++static int qca808x_led_polarity_set(struct phy_device *phydev, int index,
++				    unsigned long modes)
++{
++	struct qca808x_priv *priv = phydev->priv;
++	bool active_low = false;
++	u32 mode;
++
++	for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) {
++		switch (mode) {
++		case PHY_LED_ACTIVE_LOW:
++			active_low = true;
++			break;
++		default:
++			return -EINVAL;
++		}
++	}
++
++	/* PHY polarity is global and can't be set per LED.
++	 * To detect this, check if last requested polarity mode
++	 * match the new one.
++	 */
++	if (priv->led_polarity_mode >= 0 &&
++	    priv->led_polarity_mode != active_low) {
++		phydev_err(phydev, "PHY polarity is global. Mismatched polarity on different LED\n");
++		return -EINVAL;
++	}
++
++	/* Save the last PHY polarity mode */
++	priv->led_polarity_mode = active_low;
++
++	return phy_modify_mmd(phydev, MDIO_MMD_AN,
++			      QCA808X_MMD7_LED_POLARITY_CTRL,
++			      QCA808X_LED_ACTIVE_HIGH,
++			      active_low ? 0 : QCA808X_LED_ACTIVE_HIGH);
++}
++
++static struct phy_driver qca808x_driver[] = {
++{
++	/* Qualcomm QCA8081 */
++	PHY_ID_MATCH_EXACT(QCA8081_PHY_ID),
++	.name			= "Qualcomm QCA8081",
++	.flags			= PHY_POLL_CABLE_TEST,
++	.probe			= qca808x_probe,
++	.config_intr		= at803x_config_intr,
++	.handle_interrupt	= at803x_handle_interrupt,
++	.get_tunable		= at803x_get_tunable,
++	.set_tunable		= at803x_set_tunable,
++	.set_wol		= at803x_set_wol,
++	.get_wol		= at803x_get_wol,
++	.get_features		= qca808x_get_features,
++	.config_aneg		= qca808x_config_aneg,
++	.suspend		= genphy_suspend,
++	.resume			= genphy_resume,
++	.read_status		= qca808x_read_status,
++	.config_init		= qca808x_config_init,
++	.soft_reset		= qca808x_soft_reset,
++	.cable_test_start	= qca808x_cable_test_start,
++	.cable_test_get_status	= qca808x_cable_test_get_status,
++	.link_change_notify	= qca808x_link_change_notify,
++	.led_brightness_set	= qca808x_led_brightness_set,
++	.led_blink_set		= qca808x_led_blink_set,
++	.led_hw_is_supported	= qca808x_led_hw_is_supported,
++	.led_hw_control_set	= qca808x_led_hw_control_set,
++	.led_hw_control_get	= qca808x_led_hw_control_get,
++	.led_polarity_set	= qca808x_led_polarity_set,
++}, };
++
++module_phy_driver(qca808x_driver);
++
++static struct mdio_device_id __maybe_unused qca808x_tbl[] = {
++	{ PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) },
++	{ }
++};
++
++MODULE_DEVICE_TABLE(mdio, qca808x_tbl);
diff --git a/target/linux/generic/backport-6.1/723-v6.3-net-pcs-add-driver-for-MediaTek-SGMII-PCS.patch b/target/linux/generic/backport-6.1/714-net-pcs-add-driver-for-MediaTek-SGMII-PCS.patch
similarity index 100%
rename from target/linux/generic/backport-6.1/723-v6.3-net-pcs-add-driver-for-MediaTek-SGMII-PCS.patch
rename to target/linux/generic/backport-6.1/714-net-pcs-add-driver-for-MediaTek-SGMII-PCS.patch
diff --git a/target/linux/generic/backport-6.1/714-v6.8-01-net-phy-make-addr-type-u8-in-phy_package_shared-stru.patch b/target/linux/generic/backport-6.1/714-v6.8-01-net-phy-make-addr-type-u8-in-phy_package_shared-stru.patch
new file mode 100644
index 00000000000000..6decc3430b0da2
--- /dev/null
+++ b/target/linux/generic/backport-6.1/714-v6.8-01-net-phy-make-addr-type-u8-in-phy_package_shared-stru.patch
@@ -0,0 +1,28 @@
+From ebb30ccbbdbd6fae5177b676da4f4ac92bb4f635 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Fri, 15 Dec 2023 14:15:31 +0100
+Subject: [PATCH 1/4] net: phy: make addr type u8 in phy_package_shared struct
+
+Switch addr type in phy_package_shared struct to u8.
+
+The value is already checked to be non negative and to be less than
+PHY_MAX_ADDR, hence u8 is better suited than using int.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ include/linux/phy.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/include/linux/phy.h
++++ b/include/linux/phy.h
+@@ -330,7 +330,7 @@ struct mdio_bus_stats {
+  * phy_package_leave().
+  */
+ struct phy_package_shared {
+-	int addr;
++	u8 addr;
+ 	refcount_t refcnt;
+ 	unsigned long flags;
+ 	size_t priv_size;
diff --git a/target/linux/generic/backport-6.1/714-v6.8-02-net-phy-extend-PHY-package-API-to-support-multiple-g.patch b/target/linux/generic/backport-6.1/714-v6.8-02-net-phy-extend-PHY-package-API-to-support-multiple-g.patch
new file mode 100644
index 00000000000000..0cf01df3d35dcf
--- /dev/null
+++ b/target/linux/generic/backport-6.1/714-v6.8-02-net-phy-extend-PHY-package-API-to-support-multiple-g.patch
@@ -0,0 +1,341 @@
+From 9eea577eb1155fe4a183bc5e7bf269b0b2e7a6ba Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Fri, 15 Dec 2023 14:15:32 +0100
+Subject: [PATCH 2/4] net: phy: extend PHY package API to support multiple
+ global address
+
+Current API for PHY package are limited to single address to configure
+global settings for the PHY package.
+
+It was found that some PHY package (for example the qca807x, a PHY
+package that is shipped with a bundle of 5 PHY) requires multiple PHY
+address to configure global settings. An example scenario is a PHY that
+have a dedicated PHY for PSGMII/serdes calibrarion and have a specific
+PHY in the package where the global PHY mode is set and affects every
+other PHY in the package.
+
+Change the API in the following way:
+- Change phy_package_join() to take the base addr of the PHY package
+  instead of the global PHY addr.
+- Make __/phy_package_write/read() require an additional arg that
+  select what global PHY address to use by passing the offset from the
+  base addr passed on phy_package_join().
+
+Each user of this API is updated to follow this new implementation
+following a pattern where an enum is defined to declare the offset of the
+addr.
+
+We also drop the check if shared is defined as any user of the
+phy_package_read/write is expected to use phy_package_join first. Misuse
+of this will correctly trigger a kernel panic for NULL pointer
+exception.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/bcm54140.c       | 16 ++++++--
+ drivers/net/phy/mscc/mscc.h      |  5 +++
+ drivers/net/phy/mscc/mscc_main.c |  4 +-
+ drivers/net/phy/phy_device.c     | 35 +++++++++--------
+ include/linux/phy.h              | 64 +++++++++++++++++++++-----------
+ 5 files changed, 80 insertions(+), 44 deletions(-)
+
+--- a/drivers/net/phy/bcm54140.c
++++ b/drivers/net/phy/bcm54140.c
+@@ -128,6 +128,10 @@
+ #define BCM54140_DEFAULT_DOWNSHIFT 5
+ #define BCM54140_MAX_DOWNSHIFT 9
+ 
++enum bcm54140_global_phy {
++	BCM54140_BASE_ADDR = 0,
++};
++
+ struct bcm54140_priv {
+ 	int port;
+ 	int base_addr;
+@@ -429,11 +433,13 @@ static int bcm54140_base_read_rdb(struct
+ 	int ret;
+ 
+ 	phy_lock_mdio_bus(phydev);
+-	ret = __phy_package_write(phydev, MII_BCM54XX_RDB_ADDR, rdb);
++	ret = __phy_package_write(phydev, BCM54140_BASE_ADDR,
++				  MII_BCM54XX_RDB_ADDR, rdb);
+ 	if (ret < 0)
+ 		goto out;
+ 
+-	ret = __phy_package_read(phydev, MII_BCM54XX_RDB_DATA);
++	ret = __phy_package_read(phydev, BCM54140_BASE_ADDR,
++				 MII_BCM54XX_RDB_DATA);
+ 
+ out:
+ 	phy_unlock_mdio_bus(phydev);
+@@ -446,11 +452,13 @@ static int bcm54140_base_write_rdb(struc
+ 	int ret;
+ 
+ 	phy_lock_mdio_bus(phydev);
+-	ret = __phy_package_write(phydev, MII_BCM54XX_RDB_ADDR, rdb);
++	ret = __phy_package_write(phydev, BCM54140_BASE_ADDR,
++				  MII_BCM54XX_RDB_ADDR, rdb);
+ 	if (ret < 0)
+ 		goto out;
+ 
+-	ret = __phy_package_write(phydev, MII_BCM54XX_RDB_DATA, val);
++	ret = __phy_package_write(phydev, BCM54140_BASE_ADDR,
++				  MII_BCM54XX_RDB_DATA, val);
+ 
+ out:
+ 	phy_unlock_mdio_bus(phydev);
+--- a/drivers/net/phy/mscc/mscc.h
++++ b/drivers/net/phy/mscc/mscc.h
+@@ -414,6 +414,11 @@ struct vsc8531_private {
+  * gpio_lock: used for PHC operations. Common for all PHYs as the load/save GPIO
+  * is shared.
+  */
++
++enum vsc85xx_global_phy {
++	VSC88XX_BASE_ADDR = 0,
++};
++
+ struct vsc85xx_shared_private {
+ 	struct mutex gpio_lock;
+ };
+--- a/drivers/net/phy/mscc/mscc_main.c
++++ b/drivers/net/phy/mscc/mscc_main.c
+@@ -700,7 +700,7 @@ int phy_base_write(struct phy_device *ph
+ 		dump_stack();
+ 	}
+ 
+-	return __phy_package_write(phydev, regnum, val);
++	return __phy_package_write(phydev, VSC88XX_BASE_ADDR, regnum, val);
+ }
+ 
+ /* phydev->bus->mdio_lock should be locked when using this function */
+@@ -711,7 +711,7 @@ int phy_base_read(struct phy_device *phy
+ 		dump_stack();
+ 	}
+ 
+-	return __phy_package_read(phydev, regnum);
++	return __phy_package_read(phydev, VSC88XX_BASE_ADDR, regnum);
+ }
+ 
+ u32 vsc85xx_csr_read(struct phy_device *phydev,
+--- a/drivers/net/phy/phy_device.c
++++ b/drivers/net/phy/phy_device.c
+@@ -1602,20 +1602,22 @@ EXPORT_SYMBOL_GPL(phy_driver_is_genphy_1
+ /**
+  * phy_package_join - join a common PHY group
+  * @phydev: target phy_device struct
+- * @addr: cookie and PHY address for global register access
++ * @base_addr: cookie and base PHY address of PHY package for offset
++ *   calculation of global register access
+  * @priv_size: if non-zero allocate this amount of bytes for private data
+  *
+  * This joins a PHY group and provides a shared storage for all phydevs in
+  * this group. This is intended to be used for packages which contain
+  * more than one PHY, for example a quad PHY transceiver.
+  *
+- * The addr parameter serves as a cookie which has to have the same value
+- * for all members of one group and as a PHY address to access generic
+- * registers of a PHY package. Usually, one of the PHY addresses of the
+- * different PHYs in the package provides access to these global registers.
++ * The base_addr parameter serves as cookie which has to have the same values
++ * for all members of one group and as the base PHY address of the PHY package
++ * for offset calculation to access generic registers of a PHY package.
++ * Usually, one of the PHY addresses of the different PHYs in the package
++ * provides access to these global registers.
+  * The address which is given here, will be used in the phy_package_read()
+- * and phy_package_write() convenience functions. If your PHY doesn't have
+- * global registers you can just pick any of the PHY addresses.
++ * and phy_package_write() convenience functions as base and added to the
++ * passed offset in those functions.
+  *
+  * This will set the shared pointer of the phydev to the shared storage.
+  * If this is the first call for a this cookie the shared storage will be
+@@ -1625,17 +1627,17 @@ EXPORT_SYMBOL_GPL(phy_driver_is_genphy_1
+  * Returns < 1 on error, 0 on success. Esp. calling phy_package_join()
+  * with the same cookie but a different priv_size is an error.
+  */
+-int phy_package_join(struct phy_device *phydev, int addr, size_t priv_size)
++int phy_package_join(struct phy_device *phydev, int base_addr, size_t priv_size)
+ {
+ 	struct mii_bus *bus = phydev->mdio.bus;
+ 	struct phy_package_shared *shared;
+ 	int ret;
+ 
+-	if (addr < 0 || addr >= PHY_MAX_ADDR)
++	if (base_addr < 0 || base_addr >= PHY_MAX_ADDR)
+ 		return -EINVAL;
+ 
+ 	mutex_lock(&bus->shared_lock);
+-	shared = bus->shared[addr];
++	shared = bus->shared[base_addr];
+ 	if (!shared) {
+ 		ret = -ENOMEM;
+ 		shared = kzalloc(sizeof(*shared), GFP_KERNEL);
+@@ -1647,9 +1649,9 @@ int phy_package_join(struct phy_device *
+ 				goto err_free;
+ 			shared->priv_size = priv_size;
+ 		}
+-		shared->addr = addr;
++		shared->base_addr = base_addr;
+ 		refcount_set(&shared->refcnt, 1);
+-		bus->shared[addr] = shared;
++		bus->shared[base_addr] = shared;
+ 	} else {
+ 		ret = -EINVAL;
+ 		if (priv_size && priv_size != shared->priv_size)
+@@ -1687,7 +1689,7 @@ void phy_package_leave(struct phy_device
+ 		return;
+ 
+ 	if (refcount_dec_and_mutex_lock(&shared->refcnt, &bus->shared_lock)) {
+-		bus->shared[shared->addr] = NULL;
++		bus->shared[shared->base_addr] = NULL;
+ 		mutex_unlock(&bus->shared_lock);
+ 		kfree(shared->priv);
+ 		kfree(shared);
+@@ -1706,7 +1708,8 @@ static void devm_phy_package_leave(struc
+  * devm_phy_package_join - resource managed phy_package_join()
+  * @dev: device that is registering this PHY package
+  * @phydev: target phy_device struct
+- * @addr: cookie and PHY address for global register access
++ * @base_addr: cookie and base PHY address of PHY package for offset
++ *   calculation of global register access
+  * @priv_size: if non-zero allocate this amount of bytes for private data
+  *
+  * Managed phy_package_join(). Shared storage fetched by this function,
+@@ -1714,7 +1717,7 @@ static void devm_phy_package_leave(struc
+  * phy_package_join() for more information.
+  */
+ int devm_phy_package_join(struct device *dev, struct phy_device *phydev,
+-			  int addr, size_t priv_size)
++			  int base_addr, size_t priv_size)
+ {
+ 	struct phy_device **ptr;
+ 	int ret;
+@@ -1724,7 +1727,7 @@ int devm_phy_package_join(struct device
+ 	if (!ptr)
+ 		return -ENOMEM;
+ 
+-	ret = phy_package_join(phydev, addr, priv_size);
++	ret = phy_package_join(phydev, base_addr, priv_size);
+ 
+ 	if (!ret) {
+ 		*ptr = phydev;
+--- a/include/linux/phy.h
++++ b/include/linux/phy.h
+@@ -319,7 +319,8 @@ struct mdio_bus_stats {
+ 
+ /**
+  * struct phy_package_shared - Shared information in PHY packages
+- * @addr: Common PHY address used to combine PHYs in one package
++ * @base_addr: Base PHY address of PHY package used to combine PHYs
++ *   in one package and for offset calculation of phy_package_read/write
+  * @refcnt: Number of PHYs connected to this shared data
+  * @flags: Initialization of PHY package
+  * @priv_size: Size of the shared private data @priv
+@@ -330,7 +331,7 @@ struct mdio_bus_stats {
+  * phy_package_leave().
+  */
+ struct phy_package_shared {
+-	u8 addr;
++	u8 base_addr;
+ 	refcount_t refcnt;
+ 	unsigned long flags;
+ 	size_t priv_size;
+@@ -1763,10 +1764,10 @@ int phy_ethtool_get_link_ksettings(struc
+ int phy_ethtool_set_link_ksettings(struct net_device *ndev,
+ 				   const struct ethtool_link_ksettings *cmd);
+ int phy_ethtool_nway_reset(struct net_device *ndev);
+-int phy_package_join(struct phy_device *phydev, int addr, size_t priv_size);
++int phy_package_join(struct phy_device *phydev, int base_addr, size_t priv_size);
+ void phy_package_leave(struct phy_device *phydev);
+ int devm_phy_package_join(struct device *dev, struct phy_device *phydev,
+-			  int addr, size_t priv_size);
++			  int base_addr, size_t priv_size);
+ 
+ #if IS_ENABLED(CONFIG_PHYLIB)
+ int __init mdio_bus_init(void);
+@@ -1778,46 +1779,65 @@ int phy_ethtool_get_sset_count(struct ph
+ int phy_ethtool_get_stats(struct phy_device *phydev,
+ 			  struct ethtool_stats *stats, u64 *data);
+ 
+-static inline int phy_package_read(struct phy_device *phydev, u32 regnum)
++static inline int phy_package_address(struct phy_device *phydev,
++				      unsigned int addr_offset)
+ {
+ 	struct phy_package_shared *shared = phydev->shared;
++	u8 base_addr = shared->base_addr;
+ 
+-	if (!shared)
++	if (addr_offset >= PHY_MAX_ADDR - base_addr)
+ 		return -EIO;
+ 
+-	return mdiobus_read(phydev->mdio.bus, shared->addr, regnum);
++	/* we know that addr will be in the range 0..31 and thus the
++	 * implicit cast to a signed int is not a problem.
++	 */
++	return base_addr + addr_offset;
+ }
+ 
+-static inline int __phy_package_read(struct phy_device *phydev, u32 regnum)
++static inline int phy_package_read(struct phy_device *phydev,
++				   unsigned int addr_offset, u32 regnum)
+ {
+-	struct phy_package_shared *shared = phydev->shared;
++	int addr = phy_package_address(phydev, addr_offset);
+ 
+-	if (!shared)
+-		return -EIO;
++	if (addr < 0)
++		return addr;
++
++	return mdiobus_read(phydev->mdio.bus, addr, regnum);
++}
++
++static inline int __phy_package_read(struct phy_device *phydev,
++				     unsigned int addr_offset, u32 regnum)
++{
++	int addr = phy_package_address(phydev, addr_offset);
++
++	if (addr < 0)
++		return addr;
+ 
+-	return __mdiobus_read(phydev->mdio.bus, shared->addr, regnum);
++	return __mdiobus_read(phydev->mdio.bus, addr, regnum);
+ }
+ 
+ static inline int phy_package_write(struct phy_device *phydev,
+-				    u32 regnum, u16 val)
++				    unsigned int addr_offset, u32 regnum,
++				    u16 val)
+ {
+-	struct phy_package_shared *shared = phydev->shared;
++	int addr = phy_package_address(phydev, addr_offset);
+ 
+-	if (!shared)
+-		return -EIO;
++	if (addr < 0)
++		return addr;
+ 
+-	return mdiobus_write(phydev->mdio.bus, shared->addr, regnum, val);
++	return mdiobus_write(phydev->mdio.bus, addr, regnum, val);
+ }
+ 
+ static inline int __phy_package_write(struct phy_device *phydev,
+-				      u32 regnum, u16 val)
++				      unsigned int addr_offset, u32 regnum,
++				      u16 val)
+ {
+-	struct phy_package_shared *shared = phydev->shared;
++	int addr = phy_package_address(phydev, addr_offset);
+ 
+-	if (!shared)
+-		return -EIO;
++	if (addr < 0)
++		return addr;
+ 
+-	return __mdiobus_write(phydev->mdio.bus, shared->addr, regnum, val);
++	return __mdiobus_write(phydev->mdio.bus, addr, regnum, val);
+ }
+ 
+ static inline bool __phy_package_set_once(struct phy_device *phydev,
diff --git a/target/linux/generic/backport-6.1/714-v6.8-03-net-phy-restructure-__phy_write-read_mmd-to-helper-a.patch b/target/linux/generic/backport-6.1/714-v6.8-03-net-phy-restructure-__phy_write-read_mmd-to-helper-a.patch
new file mode 100644
index 00000000000000..4a17d4645344bb
--- /dev/null
+++ b/target/linux/generic/backport-6.1/714-v6.8-03-net-phy-restructure-__phy_write-read_mmd-to-helper-a.patch
@@ -0,0 +1,116 @@
+From 028672bd1d73cf65249a420c1de75e8d2acd2f6a Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Fri, 15 Dec 2023 14:15:33 +0100
+Subject: [PATCH 3/4] net: phy: restructure __phy_write/read_mmd to helper and
+ phydev user
+
+Restructure phy_write_mmd and phy_read_mmd to implement generic helper
+for direct mdiobus access for mmd and use these helper for phydev user.
+
+This is needed in preparation of PHY package API that requires generic
+access to the mdiobus and are deatched from phydev struct but instead
+access them based on PHY package base_addr and offsets.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/phy-core.c | 64 ++++++++++++++++++--------------------
+ 1 file changed, 30 insertions(+), 34 deletions(-)
+
+--- a/drivers/net/phy/phy-core.c
++++ b/drivers/net/phy/phy-core.c
+@@ -528,6 +528,28 @@ static void mmd_phy_indirect(struct mii_
+ 			devad | MII_MMD_CTRL_NOINCR);
+ }
+ 
++static int mmd_phy_read(struct mii_bus *bus, int phy_addr, bool is_c45,
++			int devad, u32 regnum)
++{
++	if (is_c45)
++		return __mdiobus_c45_read(bus, phy_addr, devad, regnum);
++
++	mmd_phy_indirect(bus, phy_addr, devad, regnum);
++	/* Read the content of the MMD's selected register */
++	return __mdiobus_read(bus, phy_addr, MII_MMD_DATA);
++}
++
++static int mmd_phy_write(struct mii_bus *bus, int phy_addr, bool is_c45,
++			 int devad, u32 regnum, u16 val)
++{
++	if (is_c45)
++		return __mdiobus_c45_write(bus, phy_addr, devad, regnum, val);
++
++	mmd_phy_indirect(bus, phy_addr, devad, regnum);
++	/* Write the data into MMD's selected register */
++	return __mdiobus_write(bus, phy_addr, MII_MMD_DATA, val);
++}
++
+ /**
+  * __phy_read_mmd - Convenience function for reading a register
+  * from an MMD on a given PHY.
+@@ -539,26 +561,14 @@ static void mmd_phy_indirect(struct mii_
+  */
+ int __phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum)
+ {
+-	int val;
+-
+ 	if (regnum > (u16)~0 || devad > 32)
+ 		return -EINVAL;
+ 
+-	if (phydev->drv && phydev->drv->read_mmd) {
+-		val = phydev->drv->read_mmd(phydev, devad, regnum);
+-	} else if (phydev->is_c45) {
+-		val = __mdiobus_c45_read(phydev->mdio.bus, phydev->mdio.addr,
+-					 devad, regnum);
+-	} else {
+-		struct mii_bus *bus = phydev->mdio.bus;
+-		int phy_addr = phydev->mdio.addr;
+-
+-		mmd_phy_indirect(bus, phy_addr, devad, regnum);
+-
+-		/* Read the content of the MMD's selected register */
+-		val = __mdiobus_read(bus, phy_addr, MII_MMD_DATA);
+-	}
+-	return val;
++	if (phydev->drv && phydev->drv->read_mmd)
++		return phydev->drv->read_mmd(phydev, devad, regnum);
++
++	return mmd_phy_read(phydev->mdio.bus, phydev->mdio.addr,
++			    phydev->is_c45, devad, regnum);
+ }
+ EXPORT_SYMBOL(__phy_read_mmd);
+ 
+@@ -595,28 +605,14 @@ EXPORT_SYMBOL(phy_read_mmd);
+  */
+ int __phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val)
+ {
+-	int ret;
+-
+ 	if (regnum > (u16)~0 || devad > 32)
+ 		return -EINVAL;
+ 
+-	if (phydev->drv && phydev->drv->write_mmd) {
+-		ret = phydev->drv->write_mmd(phydev, devad, regnum, val);
+-	} else if (phydev->is_c45) {
+-		ret = __mdiobus_c45_write(phydev->mdio.bus, phydev->mdio.addr,
+-					  devad, regnum, val);
+-	} else {
+-		struct mii_bus *bus = phydev->mdio.bus;
+-		int phy_addr = phydev->mdio.addr;
++	if (phydev->drv && phydev->drv->write_mmd)
++		return phydev->drv->write_mmd(phydev, devad, regnum, val);
+ 
+-		mmd_phy_indirect(bus, phy_addr, devad, regnum);
+-
+-		/* Write the data into MMD's selected register */
+-		__mdiobus_write(bus, phy_addr, MII_MMD_DATA, val);
+-
+-		ret = 0;
+-	}
+-	return ret;
++	return mmd_phy_write(phydev->mdio.bus, phydev->mdio.addr,
++			     phydev->is_c45, devad, regnum, val);
+ }
+ EXPORT_SYMBOL(__phy_write_mmd);
+ 
diff --git a/target/linux/generic/backport-6.1/714-v6.8-04-net-phy-add-support-for-PHY-package-MMD-read-write.patch b/target/linux/generic/backport-6.1/714-v6.8-04-net-phy-add-support-for-PHY-package-MMD-read-write.patch
new file mode 100644
index 00000000000000..a628a37929190f
--- /dev/null
+++ b/target/linux/generic/backport-6.1/714-v6.8-04-net-phy-add-support-for-PHY-package-MMD-read-write.patch
@@ -0,0 +1,196 @@
+From d63710fc0f1a501fd75a7025e3070a96ffa1645f Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Fri, 15 Dec 2023 14:15:34 +0100
+Subject: [PATCH 4/4] net: phy: add support for PHY package MMD read/write
+
+Some PHY in PHY package may require to read/write MMD regs to correctly
+configure the PHY package.
+
+Add support for these additional required function in both lock and no
+lock variant.
+
+It's assumed that the entire PHY package is either C22 or C45. We use
+C22 or C45 way of writing/reading to mmd regs based on the passed phydev
+whether it's C22 or C45.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/phy-core.c | 140 +++++++++++++++++++++++++++++++++++++
+ include/linux/phy.h        |  16 +++++
+ 2 files changed, 156 insertions(+)
+
+--- a/drivers/net/phy/phy-core.c
++++ b/drivers/net/phy/phy-core.c
+@@ -639,6 +639,146 @@ int phy_write_mmd(struct phy_device *phy
+ EXPORT_SYMBOL(phy_write_mmd);
+ 
+ /**
++ * __phy_package_read_mmd - read MMD reg relative to PHY package base addr
++ * @phydev: The phy_device struct
++ * @addr_offset: The offset to be added to PHY package base_addr
++ * @devad: The MMD to read from
++ * @regnum: The register on the MMD to read
++ *
++ * Convenience helper for reading a register of an MMD on a given PHY
++ * using the PHY package base address. The base address is added to
++ * the addr_offset value.
++ *
++ * Same calling rules as for __phy_read();
++ *
++ * NOTE: It's assumed that the entire PHY package is either C22 or C45.
++ */
++int __phy_package_read_mmd(struct phy_device *phydev,
++			   unsigned int addr_offset, int devad,
++			   u32 regnum)
++{
++	int addr = phy_package_address(phydev, addr_offset);
++
++	if (addr < 0)
++		return addr;
++
++	if (regnum > (u16)~0 || devad > 32)
++		return -EINVAL;
++
++	return mmd_phy_read(phydev->mdio.bus, addr, phydev->is_c45, devad,
++			    regnum);
++}
++EXPORT_SYMBOL(__phy_package_read_mmd);
++
++/**
++ * phy_package_read_mmd - read MMD reg relative to PHY package base addr
++ * @phydev: The phy_device struct
++ * @addr_offset: The offset to be added to PHY package base_addr
++ * @devad: The MMD to read from
++ * @regnum: The register on the MMD to read
++ *
++ * Convenience helper for reading a register of an MMD on a given PHY
++ * using the PHY package base address. The base address is added to
++ * the addr_offset value.
++ *
++ * Same calling rules as for phy_read();
++ *
++ * NOTE: It's assumed that the entire PHY package is either C22 or C45.
++ */
++int phy_package_read_mmd(struct phy_device *phydev,
++			 unsigned int addr_offset, int devad,
++			 u32 regnum)
++{
++	int addr = phy_package_address(phydev, addr_offset);
++	int val;
++
++	if (addr < 0)
++		return addr;
++
++	if (regnum > (u16)~0 || devad > 32)
++		return -EINVAL;
++
++	phy_lock_mdio_bus(phydev);
++	val = mmd_phy_read(phydev->mdio.bus, addr, phydev->is_c45, devad,
++			   regnum);
++	phy_unlock_mdio_bus(phydev);
++
++	return val;
++}
++EXPORT_SYMBOL(phy_package_read_mmd);
++
++/**
++ * __phy_package_write_mmd - write MMD reg relative to PHY package base addr
++ * @phydev: The phy_device struct
++ * @addr_offset: The offset to be added to PHY package base_addr
++ * @devad: The MMD to write to
++ * @regnum: The register on the MMD to write
++ * @val: value to write to @regnum
++ *
++ * Convenience helper for writing a register of an MMD on a given PHY
++ * using the PHY package base address. The base address is added to
++ * the addr_offset value.
++ *
++ * Same calling rules as for __phy_write();
++ *
++ * NOTE: It's assumed that the entire PHY package is either C22 or C45.
++ */
++int __phy_package_write_mmd(struct phy_device *phydev,
++			    unsigned int addr_offset, int devad,
++			    u32 regnum, u16 val)
++{
++	int addr = phy_package_address(phydev, addr_offset);
++
++	if (addr < 0)
++		return addr;
++
++	if (regnum > (u16)~0 || devad > 32)
++		return -EINVAL;
++
++	return mmd_phy_write(phydev->mdio.bus, addr, phydev->is_c45, devad,
++			     regnum, val);
++}
++EXPORT_SYMBOL(__phy_package_write_mmd);
++
++/**
++ * phy_package_write_mmd - write MMD reg relative to PHY package base addr
++ * @phydev: The phy_device struct
++ * @addr_offset: The offset to be added to PHY package base_addr
++ * @devad: The MMD to write to
++ * @regnum: The register on the MMD to write
++ * @val: value to write to @regnum
++ *
++ * Convenience helper for writing a register of an MMD on a given PHY
++ * using the PHY package base address. The base address is added to
++ * the addr_offset value.
++ *
++ * Same calling rules as for phy_write();
++ *
++ * NOTE: It's assumed that the entire PHY package is either C22 or C45.
++ */
++int phy_package_write_mmd(struct phy_device *phydev,
++			  unsigned int addr_offset, int devad,
++			  u32 regnum, u16 val)
++{
++	int addr = phy_package_address(phydev, addr_offset);
++	int ret;
++
++	if (addr < 0)
++		return addr;
++
++	if (regnum > (u16)~0 || devad > 32)
++		return -EINVAL;
++
++	phy_lock_mdio_bus(phydev);
++	ret = mmd_phy_write(phydev->mdio.bus, addr, phydev->is_c45, devad,
++			    regnum, val);
++	phy_unlock_mdio_bus(phydev);
++
++	return ret;
++}
++EXPORT_SYMBOL(phy_package_write_mmd);
++
++/**
+  * phy_modify_changed - Function for modifying a PHY register
+  * @phydev: the phy_device struct
+  * @regnum: register number to modify
+--- a/include/linux/phy.h
++++ b/include/linux/phy.h
+@@ -1840,6 +1840,22 @@ static inline int __phy_package_write(st
+ 	return __mdiobus_write(phydev->mdio.bus, addr, regnum, val);
+ }
+ 
++int __phy_package_read_mmd(struct phy_device *phydev,
++			   unsigned int addr_offset, int devad,
++			   u32 regnum);
++
++int phy_package_read_mmd(struct phy_device *phydev,
++			 unsigned int addr_offset, int devad,
++			 u32 regnum);
++
++int __phy_package_write_mmd(struct phy_device *phydev,
++			    unsigned int addr_offset, int devad,
++			    u32 regnum, u16 val);
++
++int phy_package_write_mmd(struct phy_device *phydev,
++			  unsigned int addr_offset, int devad,
++			  u32 regnum, u16 val);
++
+ static inline bool __phy_package_set_once(struct phy_device *phydev,
+ 					  unsigned int b)
+ {
diff --git a/target/linux/generic/backport-6.1/715-01-v6.2-net-fman-memac-Add-serdes-support.patch b/target/linux/generic/backport-6.1/715-01-v6.2-net-fman-memac-Add-serdes-support.patch
new file mode 100644
index 00000000000000..2886123f2d8f08
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-01-v6.2-net-fman-memac-Add-serdes-support.patch
@@ -0,0 +1,103 @@
+From affa013f494486079c3c5ad2d00cebc41a3d7445 Mon Sep 17 00:00:00 2001
+From: Sean Anderson <sean.anderson@seco.com>
+Date: Mon, 17 Oct 2022 16:22:36 -0400
+Subject: [PATCH 01/21] net: fman: memac: Add serdes support
+
+This adds support for using a serdes which has to be configured. This is
+primarly in preparation for phylink conversion, which will then change the
+serdes mode dynamically.
+
+Signed-off-by: Sean Anderson <sean.anderson@seco.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ .../net/ethernet/freescale/fman/fman_memac.c  | 49 ++++++++++++++++++-
+ 1 file changed, 47 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/ethernet/freescale/fman/fman_memac.c
++++ b/drivers/net/ethernet/freescale/fman/fman_memac.c
+@@ -13,6 +13,7 @@
+ #include <linux/io.h>
+ #include <linux/phy.h>
+ #include <linux/phy_fixed.h>
++#include <linux/phy/phy.h>
+ #include <linux/of_mdio.h>
+ 
+ /* PCS registers */
+@@ -324,6 +325,7 @@ struct fman_mac {
+ 	void *fm;
+ 	struct fman_rev_info fm_rev_info;
+ 	bool basex_if;
++	struct phy *serdes;
+ 	struct phy_device *pcsphy;
+ 	bool allmulti_enabled;
+ };
+@@ -1203,17 +1205,56 @@ int memac_initialization(struct mac_devi
+ 		}
+ 	}
+ 
++	memac->serdes = devm_of_phy_get(mac_dev->dev, mac_node, "serdes");
++	err = PTR_ERR(memac->serdes);
++	if (err == -ENODEV || err == -ENOSYS) {
++		dev_dbg(mac_dev->dev, "could not get (optional) serdes\n");
++		memac->serdes = NULL;
++	} else if (IS_ERR(memac->serdes)) {
++		dev_err_probe(mac_dev->dev, err, "could not get serdes\n");
++		goto _return_fm_mac_free;
++	} else {
++		err = phy_init(memac->serdes);
++		if (err) {
++			dev_err_probe(mac_dev->dev, err,
++				      "could not initialize serdes\n");
++			goto _return_fm_mac_free;
++		}
++
++		err = phy_power_on(memac->serdes);
++		if (err) {
++			dev_err_probe(mac_dev->dev, err,
++				      "could not power on serdes\n");
++			goto _return_phy_exit;
++		}
++
++		if (memac->phy_if == PHY_INTERFACE_MODE_SGMII ||
++		    memac->phy_if == PHY_INTERFACE_MODE_1000BASEX ||
++		    memac->phy_if == PHY_INTERFACE_MODE_2500BASEX ||
++		    memac->phy_if == PHY_INTERFACE_MODE_QSGMII ||
++		    memac->phy_if == PHY_INTERFACE_MODE_XGMII) {
++			err = phy_set_mode_ext(memac->serdes, PHY_MODE_ETHERNET,
++					       memac->phy_if);
++			if (err) {
++				dev_err_probe(mac_dev->dev, err,
++					      "could not set serdes mode to %s\n",
++					      phy_modes(memac->phy_if));
++				goto _return_phy_power_off;
++			}
++		}
++	}
++
+ 	if (!mac_dev->phy_node && of_phy_is_fixed_link(mac_node)) {
+ 		struct phy_device *phy;
+ 
+ 		err = of_phy_register_fixed_link(mac_node);
+ 		if (err)
+-			goto _return_fm_mac_free;
++			goto _return_phy_power_off;
+ 
+ 		fixed_link = kzalloc(sizeof(*fixed_link), GFP_KERNEL);
+ 		if (!fixed_link) {
+ 			err = -ENOMEM;
+-			goto _return_fm_mac_free;
++			goto _return_phy_power_off;
+ 		}
+ 
+ 		mac_dev->phy_node = of_node_get(mac_node);
+@@ -1242,6 +1283,10 @@ int memac_initialization(struct mac_devi
+ 
+ 	goto _return;
+ 
++_return_phy_power_off:
++	phy_power_off(memac->serdes);
++_return_phy_exit:
++	phy_exit(memac->serdes);
+ _return_fixed_link_free:
+ 	kfree(fixed_link);
+ _return_fm_mac_free:
diff --git a/target/linux/generic/backport-6.1/715-02-v6.2-net-fman-memac-Use-lynx-pcs-driver.patch b/target/linux/generic/backport-6.1/715-02-v6.2-net-fman-memac-Use-lynx-pcs-driver.patch
new file mode 100644
index 00000000000000..873debc0807e99
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-02-v6.2-net-fman-memac-Use-lynx-pcs-driver.patch
@@ -0,0 +1,384 @@
+From fe60e7154d3a35af975c5e6570d6ec31aab9a731 Mon Sep 17 00:00:00 2001
+From: Sean Anderson <sean.anderson@seco.com>
+Date: Mon, 17 Oct 2022 16:22:37 -0400
+Subject: [PATCH 02/21] net: fman: memac: Use lynx pcs driver
+
+Although not stated in the datasheet, as far as I can tell PCS for mEMACs
+is a "Lynx." By reusing the existing driver, we can remove the PCS
+management code from the memac driver. This requires calling some PCS
+functions manually which phylink would usually do for us, but we will let
+it do that soon.
+
+One problem is that we don't actually have a PCS for QSGMII. We pretend
+that each mEMAC's MDIO bus has four QSGMII PCSs, but this is not the case.
+Only the "base" mEMAC's MDIO bus has the four QSGMII PCSs. This is not an
+issue yet, because we never get the PCS state. However, it will be once the
+conversion to phylink is complete, since the links will appear to never
+come up. To get around this, we allow specifying multiple PCSs in pcsphy.
+This breaks backwards compatibility with old device trees, but only for
+QSGMII. IMO this is the only reasonable way to figure out what the actual
+QSGMII PCS is.
+
+Additionally, we now also support a separate XFI PCS. This can allow the
+SerDes driver to set different addresses for the SGMII and XFI PCSs so they
+can be accessed at the same time.
+
+Signed-off-by: Sean Anderson <sean.anderson@seco.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/ethernet/freescale/fman/Kconfig   |   3 +
+ .../net/ethernet/freescale/fman/fman_memac.c  | 258 +++++++-----------
+ 2 files changed, 105 insertions(+), 156 deletions(-)
+
+--- a/drivers/net/ethernet/freescale/fman/Kconfig
++++ b/drivers/net/ethernet/freescale/fman/Kconfig
+@@ -4,6 +4,9 @@ config FSL_FMAN
+ 	depends on FSL_SOC || ARCH_LAYERSCAPE || COMPILE_TEST
+ 	select GENERIC_ALLOCATOR
+ 	select PHYLIB
++	select PHYLINK
++	select PCS
++	select PCS_LYNX
+ 	select CRC32
+ 	default n
+ 	help
+--- a/drivers/net/ethernet/freescale/fman/fman_memac.c
++++ b/drivers/net/ethernet/freescale/fman/fman_memac.c
+@@ -11,43 +11,12 @@
+ 
+ #include <linux/slab.h>
+ #include <linux/io.h>
++#include <linux/pcs-lynx.h>
+ #include <linux/phy.h>
+ #include <linux/phy_fixed.h>
+ #include <linux/phy/phy.h>
+ #include <linux/of_mdio.h>
+ 
+-/* PCS registers */
+-#define MDIO_SGMII_CR			0x00
+-#define MDIO_SGMII_DEV_ABIL_SGMII	0x04
+-#define MDIO_SGMII_LINK_TMR_L		0x12
+-#define MDIO_SGMII_LINK_TMR_H		0x13
+-#define MDIO_SGMII_IF_MODE		0x14
+-
+-/* SGMII Control defines */
+-#define SGMII_CR_AN_EN			0x1000
+-#define SGMII_CR_RESTART_AN		0x0200
+-#define SGMII_CR_FD			0x0100
+-#define SGMII_CR_SPEED_SEL1_1G		0x0040
+-#define SGMII_CR_DEF_VAL		(SGMII_CR_AN_EN | SGMII_CR_FD | \
+-					 SGMII_CR_SPEED_SEL1_1G)
+-
+-/* SGMII Device Ability for SGMII defines */
+-#define MDIO_SGMII_DEV_ABIL_SGMII_MODE	0x4001
+-#define MDIO_SGMII_DEV_ABIL_BASEX_MODE	0x01A0
+-
+-/* Link timer define */
+-#define LINK_TMR_L			0xa120
+-#define LINK_TMR_H			0x0007
+-#define LINK_TMR_L_BASEX		0xaf08
+-#define LINK_TMR_H_BASEX		0x002f
+-
+-/* SGMII IF Mode defines */
+-#define IF_MODE_USE_SGMII_AN		0x0002
+-#define IF_MODE_SGMII_EN		0x0001
+-#define IF_MODE_SGMII_SPEED_100M	0x0004
+-#define IF_MODE_SGMII_SPEED_1G		0x0008
+-#define IF_MODE_SGMII_DUPLEX_HALF	0x0010
+-
+ /* Num of additional exact match MAC adr regs */
+ #define MEMAC_NUM_OF_PADDRS 7
+ 
+@@ -326,7 +295,9 @@ struct fman_mac {
+ 	struct fman_rev_info fm_rev_info;
+ 	bool basex_if;
+ 	struct phy *serdes;
+-	struct phy_device *pcsphy;
++	struct phylink_pcs *sgmii_pcs;
++	struct phylink_pcs *qsgmii_pcs;
++	struct phylink_pcs *xfi_pcs;
+ 	bool allmulti_enabled;
+ };
+ 
+@@ -487,91 +458,22 @@ static u32 get_mac_addr_hash_code(u64 et
+ 	return xor_val;
+ }
+ 
+-static void setup_sgmii_internal_phy(struct fman_mac *memac,
+-				     struct fixed_phy_status *fixed_link)
+-{
+-	u16 tmp_reg16;
+-
+-	if (WARN_ON(!memac->pcsphy))
+-		return;
+-
+-	/* SGMII mode */
+-	tmp_reg16 = IF_MODE_SGMII_EN;
+-	if (!fixed_link)
+-		/* AN enable */
+-		tmp_reg16 |= IF_MODE_USE_SGMII_AN;
+-	else {
+-		switch (fixed_link->speed) {
+-		case 10:
+-			/* For 10M: IF_MODE[SPEED_10M] = 0 */
+-		break;
+-		case 100:
+-			tmp_reg16 |= IF_MODE_SGMII_SPEED_100M;
+-		break;
+-		case 1000:
+-		default:
+-			tmp_reg16 |= IF_MODE_SGMII_SPEED_1G;
+-		break;
+-		}
+-		if (!fixed_link->duplex)
+-			tmp_reg16 |= IF_MODE_SGMII_DUPLEX_HALF;
+-	}
+-	phy_write(memac->pcsphy, MDIO_SGMII_IF_MODE, tmp_reg16);
+-
+-	/* Device ability according to SGMII specification */
+-	tmp_reg16 = MDIO_SGMII_DEV_ABIL_SGMII_MODE;
+-	phy_write(memac->pcsphy, MDIO_SGMII_DEV_ABIL_SGMII, tmp_reg16);
+-
+-	/* Adjust link timer for SGMII  -
+-	 * According to Cisco SGMII specification the timer should be 1.6 ms.
+-	 * The link_timer register is configured in units of the clock.
+-	 * - When running as 1G SGMII, Serdes clock is 125 MHz, so
+-	 * unit = 1 / (125*10^6 Hz) = 8 ns.
+-	 * 1.6 ms in units of 8 ns = 1.6ms / 8ns = 2*10^5 = 0x30d40
+-	 * - When running as 2.5G SGMII, Serdes clock is 312.5 MHz, so
+-	 * unit = 1 / (312.5*10^6 Hz) = 3.2 ns.
+-	 * 1.6 ms in units of 3.2 ns = 1.6ms / 3.2ns = 5*10^5 = 0x7a120.
+-	 * Since link_timer value of 1G SGMII will be too short for 2.5 SGMII,
+-	 * we always set up here a value of 2.5 SGMII.
+-	 */
+-	phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_H, LINK_TMR_H);
+-	phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_L, LINK_TMR_L);
+-
+-	if (!fixed_link)
+-		/* Restart AN */
+-		tmp_reg16 = SGMII_CR_DEF_VAL | SGMII_CR_RESTART_AN;
++static void setup_sgmii_internal(struct fman_mac *memac,
++				 struct phylink_pcs *pcs,
++				 struct fixed_phy_status *fixed_link)
++{
++	__ETHTOOL_DECLARE_LINK_MODE_MASK(advertising);
++	phy_interface_t iface = memac->basex_if ? PHY_INTERFACE_MODE_1000BASEX :
++				PHY_INTERFACE_MODE_SGMII;
++	unsigned int mode = fixed_link ? MLO_AN_FIXED : MLO_AN_INBAND;
++
++	linkmode_set_pause(advertising, true, true);
++	pcs->ops->pcs_config(pcs, mode, iface, advertising, true);
++	if (fixed_link)
++		pcs->ops->pcs_link_up(pcs, mode, iface, fixed_link->speed,
++				      fixed_link->duplex);
+ 	else
+-		/* AN disabled */
+-		tmp_reg16 = SGMII_CR_DEF_VAL & ~SGMII_CR_AN_EN;
+-	phy_write(memac->pcsphy, 0x0, tmp_reg16);
+-}
+-
+-static void setup_sgmii_internal_phy_base_x(struct fman_mac *memac)
+-{
+-	u16 tmp_reg16;
+-
+-	/* AN Device capability  */
+-	tmp_reg16 = MDIO_SGMII_DEV_ABIL_BASEX_MODE;
+-	phy_write(memac->pcsphy, MDIO_SGMII_DEV_ABIL_SGMII, tmp_reg16);
+-
+-	/* Adjust link timer for SGMII  -
+-	 * For Serdes 1000BaseX auto-negotiation the timer should be 10 ms.
+-	 * The link_timer register is configured in units of the clock.
+-	 * - When running as 1G SGMII, Serdes clock is 125 MHz, so
+-	 * unit = 1 / (125*10^6 Hz) = 8 ns.
+-	 * 10 ms in units of 8 ns = 10ms / 8ns = 1250000 = 0x1312d0
+-	 * - When running as 2.5G SGMII, Serdes clock is 312.5 MHz, so
+-	 * unit = 1 / (312.5*10^6 Hz) = 3.2 ns.
+-	 * 10 ms in units of 3.2 ns = 10ms / 3.2ns = 3125000 = 0x2faf08.
+-	 * Since link_timer value of 1G SGMII will be too short for 2.5 SGMII,
+-	 * we always set up here a value of 2.5 SGMII.
+-	 */
+-	phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_H, LINK_TMR_H_BASEX);
+-	phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_L, LINK_TMR_L_BASEX);
+-
+-	/* Restart AN */
+-	tmp_reg16 = SGMII_CR_DEF_VAL | SGMII_CR_RESTART_AN;
+-	phy_write(memac->pcsphy, 0x0, tmp_reg16);
++		pcs->ops->pcs_an_restart(pcs);
+ }
+ 
+ static int check_init_parameters(struct fman_mac *memac)
+@@ -983,7 +885,6 @@ static int memac_set_exception(struct fm
+ static int memac_init(struct fman_mac *memac)
+ {
+ 	struct memac_cfg *memac_drv_param;
+-	u8 i;
+ 	enet_addr_t eth_addr;
+ 	bool slow_10g_if = false;
+ 	struct fixed_phy_status *fixed_link = NULL;
+@@ -1036,32 +937,10 @@ static int memac_init(struct fman_mac *m
+ 		iowrite32be(reg32, &memac->regs->command_config);
+ 	}
+ 
+-	if (memac->phy_if == PHY_INTERFACE_MODE_SGMII) {
+-		/* Configure internal SGMII PHY */
+-		if (memac->basex_if)
+-			setup_sgmii_internal_phy_base_x(memac);
+-		else
+-			setup_sgmii_internal_phy(memac, fixed_link);
+-	} else if (memac->phy_if == PHY_INTERFACE_MODE_QSGMII) {
+-		/* Configure 4 internal SGMII PHYs */
+-		for (i = 0; i < 4; i++) {
+-			u8 qsmgii_phy_addr, phy_addr;
+-			/* QSGMII PHY address occupies 3 upper bits of 5-bit
+-			 * phy_address; the lower 2 bits are used to extend
+-			 * register address space and access each one of 4
+-			 * ports inside QSGMII.
+-			 */
+-			phy_addr = memac->pcsphy->mdio.addr;
+-			qsmgii_phy_addr = (u8)((phy_addr << 2) | i);
+-			memac->pcsphy->mdio.addr = qsmgii_phy_addr;
+-			if (memac->basex_if)
+-				setup_sgmii_internal_phy_base_x(memac);
+-			else
+-				setup_sgmii_internal_phy(memac, fixed_link);
+-
+-			memac->pcsphy->mdio.addr = phy_addr;
+-		}
+-	}
++	if (memac->phy_if == PHY_INTERFACE_MODE_SGMII)
++		setup_sgmii_internal(memac, memac->sgmii_pcs, fixed_link);
++	else if (memac->phy_if == PHY_INTERFACE_MODE_QSGMII)
++		setup_sgmii_internal(memac, memac->qsgmii_pcs, fixed_link);
+ 
+ 	/* Max Frame Length */
+ 	err = fman_set_mac_max_frame(memac->fm, memac->mac_id,
+@@ -1097,12 +976,25 @@ static int memac_init(struct fman_mac *m
+ 	return 0;
+ }
+ 
++static void pcs_put(struct phylink_pcs *pcs)
++{
++	struct mdio_device *mdiodev;
++
++	if (IS_ERR_OR_NULL(pcs))
++		return;
++
++	mdiodev = lynx_get_mdio_device(pcs);
++	lynx_pcs_destroy(pcs);
++	mdio_device_free(mdiodev);
++}
++
+ static int memac_free(struct fman_mac *memac)
+ {
+ 	free_init_resources(memac);
+ 
+-	if (memac->pcsphy)
+-		put_device(&memac->pcsphy->mdio.dev);
++	pcs_put(memac->sgmii_pcs);
++	pcs_put(memac->qsgmii_pcs);
++	pcs_put(memac->xfi_pcs);
+ 
+ 	kfree(memac->memac_drv_param);
+ 	kfree(memac);
+@@ -1153,12 +1045,31 @@ static struct fman_mac *memac_config(str
+ 	return memac;
+ }
+ 
++static struct phylink_pcs *memac_pcs_create(struct device_node *mac_node,
++					    int index)
++{
++	struct device_node *node;
++	struct mdio_device *mdiodev = NULL;
++	struct phylink_pcs *pcs;
++
++	node = of_parse_phandle(mac_node, "pcsphy-handle", index);
++	if (node && of_device_is_available(node))
++		mdiodev = of_mdio_find_device(node);
++	of_node_put(node);
++
++	if (!mdiodev)
++		return ERR_PTR(-EPROBE_DEFER);
++
++	pcs = lynx_pcs_create(mdiodev);
++	return pcs;
++}
++
+ int memac_initialization(struct mac_device *mac_dev,
+ 			 struct device_node *mac_node,
+ 			 struct fman_mac_params *params)
+ {
+ 	int			 err;
+-	struct device_node	*phy_node;
++	struct phylink_pcs	*pcs;
+ 	struct fixed_phy_status *fixed_link;
+ 	struct fman_mac		*memac;
+ 
+@@ -1188,23 +1099,58 @@ int memac_initialization(struct mac_devi
+ 	memac = mac_dev->fman_mac;
+ 	memac->memac_drv_param->max_frame_length = fman_get_max_frm();
+ 	memac->memac_drv_param->reset_on_init = true;
+-	if (memac->phy_if == PHY_INTERFACE_MODE_SGMII ||
+-	    memac->phy_if == PHY_INTERFACE_MODE_QSGMII) {
+-		phy_node = of_parse_phandle(mac_node, "pcsphy-handle", 0);
+-		if (!phy_node) {
+-			pr_err("PCS PHY node is not available\n");
+-			err = -EINVAL;
++
++	err = of_property_match_string(mac_node, "pcs-handle-names", "xfi");
++	if (err >= 0) {
++		memac->xfi_pcs = memac_pcs_create(mac_node, err);
++		if (IS_ERR(memac->xfi_pcs)) {
++			err = PTR_ERR(memac->xfi_pcs);
++			dev_err_probe(mac_dev->dev, err, "missing xfi pcs\n");
+ 			goto _return_fm_mac_free;
+ 		}
++	} else if (err != -EINVAL && err != -ENODATA) {
++		goto _return_fm_mac_free;
++	}
+ 
+-		memac->pcsphy = of_phy_find_device(phy_node);
+-		if (!memac->pcsphy) {
+-			pr_err("of_phy_find_device (PCS PHY) failed\n");
+-			err = -EINVAL;
++	err = of_property_match_string(mac_node, "pcs-handle-names", "qsgmii");
++	if (err >= 0) {
++		memac->qsgmii_pcs = memac_pcs_create(mac_node, err);
++		if (IS_ERR(memac->qsgmii_pcs)) {
++			err = PTR_ERR(memac->qsgmii_pcs);
++			dev_err_probe(mac_dev->dev, err,
++				      "missing qsgmii pcs\n");
+ 			goto _return_fm_mac_free;
+ 		}
++	} else if (err != -EINVAL && err != -ENODATA) {
++		goto _return_fm_mac_free;
++	}
++
++	/* For compatibility, if pcs-handle-names is missing, we assume this
++	 * phy is the first one in pcsphy-handle
++	 */
++	err = of_property_match_string(mac_node, "pcs-handle-names", "sgmii");
++	if (err == -EINVAL || err == -ENODATA)
++		pcs = memac_pcs_create(mac_node, 0);
++	else if (err < 0)
++		goto _return_fm_mac_free;
++	else
++		pcs = memac_pcs_create(mac_node, err);
++
++	if (!pcs) {
++		dev_err(mac_dev->dev, "missing pcs\n");
++		err = -ENOENT;
++		goto _return_fm_mac_free;
+ 	}
+ 
++	/* If err is set here, it means that pcs-handle-names was missing above
++	 * (and therefore that xfi_pcs cannot be set). If we are defaulting to
++	 * XGMII, assume this is for XFI. Otherwise, assume it is for SGMII.
++	 */
++	if (err && mac_dev->phy_if == PHY_INTERFACE_MODE_XGMII)
++		memac->xfi_pcs = pcs;
++	else
++		memac->sgmii_pcs = pcs;
++
+ 	memac->serdes = devm_of_phy_get(mac_dev->dev, mac_node, "serdes");
+ 	err = PTR_ERR(memac->serdes);
+ 	if (err == -ENODEV || err == -ENOSYS) {
diff --git a/target/linux/generic/backport-6.1/715-03-v6.2-net-dpaa-Convert-to-phylink.patch b/target/linux/generic/backport-6.1/715-03-v6.2-net-dpaa-Convert-to-phylink.patch
new file mode 100644
index 00000000000000..63b651bb2dd309
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-03-v6.2-net-dpaa-Convert-to-phylink.patch
@@ -0,0 +1,2451 @@
+From 38e50fc3d43882a43115b4f1ca3eb88255163c5b Mon Sep 17 00:00:00 2001
+From: Sean Anderson <sean.anderson@seco.com>
+Date: Mon, 17 Oct 2022 16:22:38 -0400
+Subject: [PATCH 03/21] net: dpaa: Convert to phylink
+
+This converts DPAA to phylink. All macs are converted. This should work
+with no device tree modifications (including those made in this series),
+except for QSGMII (as noted previously).
+
+The mEMAC configuration is one of the tricker areas. I have tried to
+capture all the restrictions across the various models. Most of the time,
+we assume that if the serdes supports a mode or the phy-interface-mode
+specifies it, then we support it. The only place we can't do this is
+(RG)MII, since there's no serdes. In that case, we rely on a (new)
+devicetree property. There are also several cases where half-duplex is
+broken. Unfortunately, only a single compatible is used for the MAC, so we
+have to use the board compatible instead.
+
+The 10GEC conversion is very straightforward, since it only supports XAUI.
+There is generally nothing to configure.
+
+The dTSEC conversion is broadly similar to mEMAC, but is simpler because we
+don't support configuring the SerDes (though this can be easily added) and
+we don't have multiple PCSs. From what I can tell, there's nothing
+different in the driver or documentation between SGMII and 1000BASE-X
+except for the advertising. Similarly, I couldn't find anything about
+2500BASE-X. In both cases, I treat them like SGMII. These modes aren't used
+by any in-tree boards. Similarly, despite being mentioned in the driver, I
+couldn't find any documented SoCs which supported QSGMII.  I have left it
+unimplemented for now.
+
+Signed-off-by: Sean Anderson <sean.anderson@seco.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/ethernet/freescale/dpaa/Kconfig   |   4 +-
+ .../net/ethernet/freescale/dpaa/dpaa_eth.c    |  89 +--
+ .../ethernet/freescale/dpaa/dpaa_ethtool.c    |  90 +--
+ drivers/net/ethernet/freescale/fman/Kconfig   |   1 -
+ .../net/ethernet/freescale/fman/fman_dtsec.c  | 458 +++++++--------
+ .../net/ethernet/freescale/fman/fman_mac.h    |  10 -
+ .../net/ethernet/freescale/fman/fman_memac.c  | 547 +++++++++---------
+ .../net/ethernet/freescale/fman/fman_tgec.c   | 131 ++---
+ drivers/net/ethernet/freescale/fman/mac.c     | 168 +-----
+ drivers/net/ethernet/freescale/fman/mac.h     |  23 +-
+ 10 files changed, 612 insertions(+), 909 deletions(-)
+
+--- a/drivers/net/ethernet/freescale/dpaa/Kconfig
++++ b/drivers/net/ethernet/freescale/dpaa/Kconfig
+@@ -2,8 +2,8 @@
+ menuconfig FSL_DPAA_ETH
+ 	tristate "DPAA Ethernet"
+ 	depends on FSL_DPAA && FSL_FMAN
+-	select PHYLIB
+-	select FIXED_PHY
++	select PHYLINK
++	select PCS_LYNX
+ 	help
+ 	  Data Path Acceleration Architecture Ethernet driver,
+ 	  supporting the Freescale QorIQ chips.
+--- a/drivers/net/ethernet/freescale/dpaa/dpaa_eth.c
++++ b/drivers/net/ethernet/freescale/dpaa/dpaa_eth.c
+@@ -264,8 +264,19 @@ static int dpaa_netdev_init(struct net_d
+ 	net_dev->needed_headroom = priv->tx_headroom;
+ 	net_dev->watchdog_timeo = msecs_to_jiffies(tx_timeout);
+ 
+-	mac_dev->net_dev = net_dev;
++	/* The rest of the config is filled in by the mac device already */
++	mac_dev->phylink_config.dev = &net_dev->dev;
++	mac_dev->phylink_config.type = PHYLINK_NETDEV;
+ 	mac_dev->update_speed = dpaa_eth_cgr_set_speed;
++	mac_dev->phylink = phylink_create(&mac_dev->phylink_config,
++					  dev_fwnode(mac_dev->dev),
++					  mac_dev->phy_if,
++					  mac_dev->phylink_ops);
++	if (IS_ERR(mac_dev->phylink)) {
++		err = PTR_ERR(mac_dev->phylink);
++		dev_err_probe(dev, err, "Could not create phylink\n");
++		return err;
++	}
+ 
+ 	/* start without the RUNNING flag, phylib controls it later */
+ 	netif_carrier_off(net_dev);
+@@ -273,6 +284,7 @@ static int dpaa_netdev_init(struct net_d
+ 	err = register_netdev(net_dev);
+ 	if (err < 0) {
+ 		dev_err(dev, "register_netdev() = %d\n", err);
++		phylink_destroy(mac_dev->phylink);
+ 		return err;
+ 	}
+ 
+@@ -295,8 +307,7 @@ static int dpaa_stop(struct net_device *
+ 	 */
+ 	msleep(200);
+ 
+-	if (mac_dev->phy_dev)
+-		phy_stop(mac_dev->phy_dev);
++	phylink_stop(mac_dev->phylink);
+ 	mac_dev->disable(mac_dev->fman_mac);
+ 
+ 	for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++) {
+@@ -305,8 +316,7 @@ static int dpaa_stop(struct net_device *
+ 			err = error;
+ 	}
+ 
+-	if (net_dev->phydev)
+-		phy_disconnect(net_dev->phydev);
++	phylink_disconnect_phy(mac_dev->phylink);
+ 	net_dev->phydev = NULL;
+ 
+ 	msleep(200);
+@@ -834,10 +844,10 @@ static int dpaa_eth_cgr_init(struct dpaa
+ 
+ 	/* Set different thresholds based on the configured MAC speed.
+ 	 * This may turn suboptimal if the MAC is reconfigured at another
+-	 * speed, so MACs must call dpaa_eth_cgr_set_speed in their adjust_link
++	 * speed, so MACs must call dpaa_eth_cgr_set_speed in their link_up
+ 	 * callback.
+ 	 */
+-	if (priv->mac_dev->if_support & SUPPORTED_10000baseT_Full)
++	if (priv->mac_dev->phylink_config.mac_capabilities & MAC_10000FD)
+ 		cs_th = DPAA_CS_THRESHOLD_10G;
+ 	else
+ 		cs_th = DPAA_CS_THRESHOLD_1G;
+@@ -866,7 +876,7 @@ out_error:
+ 
+ static void dpaa_eth_cgr_set_speed(struct mac_device *mac_dev, int speed)
+ {
+-	struct net_device *net_dev = mac_dev->net_dev;
++	struct net_device *net_dev = to_net_dev(mac_dev->phylink_config.dev);
+ 	struct dpaa_priv *priv = netdev_priv(net_dev);
+ 	struct qm_mcc_initcgr opts = { };
+ 	u32 cs_th;
+@@ -2905,58 +2915,6 @@ static void dpaa_eth_napi_disable(struct
+ 	}
+ }
+ 
+-static void dpaa_adjust_link(struct net_device *net_dev)
+-{
+-	struct mac_device *mac_dev;
+-	struct dpaa_priv *priv;
+-
+-	priv = netdev_priv(net_dev);
+-	mac_dev = priv->mac_dev;
+-	mac_dev->adjust_link(mac_dev);
+-}
+-
+-/* The Aquantia PHYs are capable of performing rate adaptation */
+-#define PHY_VEND_AQUANTIA	0x03a1b400
+-#define PHY_VEND_AQUANTIA2	0x31c31c00
+-
+-static int dpaa_phy_init(struct net_device *net_dev)
+-{
+-	__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
+-	struct mac_device *mac_dev;
+-	struct phy_device *phy_dev;
+-	struct dpaa_priv *priv;
+-	u32 phy_vendor;
+-
+-	priv = netdev_priv(net_dev);
+-	mac_dev = priv->mac_dev;
+-
+-	phy_dev = of_phy_connect(net_dev, mac_dev->phy_node,
+-				 &dpaa_adjust_link, 0,
+-				 mac_dev->phy_if);
+-	if (!phy_dev) {
+-		netif_err(priv, ifup, net_dev, "init_phy() failed\n");
+-		return -ENODEV;
+-	}
+-
+-	phy_vendor = phy_dev->drv->phy_id & GENMASK(31, 10);
+-	/* Unless the PHY is capable of rate adaptation */
+-	if (mac_dev->phy_if != PHY_INTERFACE_MODE_XGMII ||
+-	    (phy_vendor != PHY_VEND_AQUANTIA &&
+-	     phy_vendor != PHY_VEND_AQUANTIA2)) {
+-		/* remove any features not supported by the controller */
+-		ethtool_convert_legacy_u32_to_link_mode(mask,
+-							mac_dev->if_support);
+-		linkmode_and(phy_dev->supported, phy_dev->supported, mask);
+-	}
+-
+-	phy_support_asym_pause(phy_dev);
+-
+-	mac_dev->phy_dev = phy_dev;
+-	net_dev->phydev = phy_dev;
+-
+-	return 0;
+-}
+-
+ static int dpaa_open(struct net_device *net_dev)
+ {
+ 	struct mac_device *mac_dev;
+@@ -2967,7 +2925,8 @@ static int dpaa_open(struct net_device *
+ 	mac_dev = priv->mac_dev;
+ 	dpaa_eth_napi_enable(priv);
+ 
+-	err = dpaa_phy_init(net_dev);
++	err = phylink_of_phy_connect(mac_dev->phylink,
++				     mac_dev->dev->of_node, 0);
+ 	if (err)
+ 		goto phy_init_failed;
+ 
+@@ -2982,7 +2941,7 @@ static int dpaa_open(struct net_device *
+ 		netif_err(priv, ifup, net_dev, "mac_dev->enable() = %d\n", err);
+ 		goto mac_start_failed;
+ 	}
+-	phy_start(priv->mac_dev->phy_dev);
++	phylink_start(mac_dev->phylink);
+ 
+ 	netif_tx_start_all_queues(net_dev);
+ 
+@@ -2991,6 +2950,7 @@ static int dpaa_open(struct net_device *
+ mac_start_failed:
+ 	for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++)
+ 		fman_port_disable(mac_dev->port[i]);
++	phylink_disconnect_phy(mac_dev->phylink);
+ 
+ phy_init_failed:
+ 	dpaa_eth_napi_disable(priv);
+@@ -3146,10 +3106,12 @@ static int dpaa_ts_ioctl(struct net_devi
+ static int dpaa_ioctl(struct net_device *net_dev, struct ifreq *rq, int cmd)
+ {
+ 	int ret = -EINVAL;
++	struct dpaa_priv *priv = netdev_priv(net_dev);
+ 
+ 	if (cmd == SIOCGMIIREG) {
+ 		if (net_dev->phydev)
+-			return phy_mii_ioctl(net_dev->phydev, rq, cmd);
++			return phylink_mii_ioctl(priv->mac_dev->phylink, rq,
++						 cmd);
+ 	}
+ 
+ 	if (cmd == SIOCSHWTSTAMP)
+@@ -3552,6 +3514,7 @@ static int dpaa_remove(struct platform_d
+ 
+ 	dev_set_drvdata(dev, NULL);
+ 	unregister_netdev(net_dev);
++	phylink_destroy(priv->mac_dev->phylink);
+ 
+ 	err = dpaa_fq_free(dev, &priv->dpaa_fq_list);
+ 
+--- a/drivers/net/ethernet/freescale/dpaa/dpaa_ethtool.c
++++ b/drivers/net/ethernet/freescale/dpaa/dpaa_ethtool.c
+@@ -54,27 +54,19 @@ static char dpaa_stats_global[][ETH_GSTR
+ static int dpaa_get_link_ksettings(struct net_device *net_dev,
+ 				   struct ethtool_link_ksettings *cmd)
+ {
+-	if (!net_dev->phydev)
+-		return 0;
++	struct dpaa_priv *priv = netdev_priv(net_dev);
++	struct mac_device *mac_dev = priv->mac_dev;
+ 
+-	phy_ethtool_ksettings_get(net_dev->phydev, cmd);
+-
+-	return 0;
++	return phylink_ethtool_ksettings_get(mac_dev->phylink, cmd);
+ }
+ 
+ static int dpaa_set_link_ksettings(struct net_device *net_dev,
+ 				   const struct ethtool_link_ksettings *cmd)
+ {
+-	int err;
+-
+-	if (!net_dev->phydev)
+-		return -ENODEV;
++	struct dpaa_priv *priv = netdev_priv(net_dev);
++	struct mac_device *mac_dev = priv->mac_dev;
+ 
+-	err = phy_ethtool_ksettings_set(net_dev->phydev, cmd);
+-	if (err < 0)
+-		netdev_err(net_dev, "phy_ethtool_ksettings_set() = %d\n", err);
+-
+-	return err;
++	return phylink_ethtool_ksettings_set(mac_dev->phylink, cmd);
+ }
+ 
+ static void dpaa_get_drvinfo(struct net_device *net_dev,
+@@ -99,80 +91,28 @@ static void dpaa_set_msglevel(struct net
+ 
+ static int dpaa_nway_reset(struct net_device *net_dev)
+ {
+-	int err;
+-
+-	if (!net_dev->phydev)
+-		return -ENODEV;
++	struct dpaa_priv *priv = netdev_priv(net_dev);
++	struct mac_device *mac_dev = priv->mac_dev;
+ 
+-	err = 0;
+-	if (net_dev->phydev->autoneg) {
+-		err = phy_start_aneg(net_dev->phydev);
+-		if (err < 0)
+-			netdev_err(net_dev, "phy_start_aneg() = %d\n",
+-				   err);
+-	}
+-
+-	return err;
++	return phylink_ethtool_nway_reset(mac_dev->phylink);
+ }
+ 
+ static void dpaa_get_pauseparam(struct net_device *net_dev,
+ 				struct ethtool_pauseparam *epause)
+ {
+-	struct mac_device *mac_dev;
+-	struct dpaa_priv *priv;
+-
+-	priv = netdev_priv(net_dev);
+-	mac_dev = priv->mac_dev;
+-
+-	if (!net_dev->phydev)
+-		return;
++	struct dpaa_priv *priv = netdev_priv(net_dev);
++	struct mac_device *mac_dev = priv->mac_dev;
+ 
+-	epause->autoneg = mac_dev->autoneg_pause;
+-	epause->rx_pause = mac_dev->rx_pause_active;
+-	epause->tx_pause = mac_dev->tx_pause_active;
++	phylink_ethtool_get_pauseparam(mac_dev->phylink, epause);
+ }
+ 
+ static int dpaa_set_pauseparam(struct net_device *net_dev,
+ 			       struct ethtool_pauseparam *epause)
+ {
+-	struct mac_device *mac_dev;
+-	struct phy_device *phydev;
+-	bool rx_pause, tx_pause;
+-	struct dpaa_priv *priv;
+-	int err;
+-
+-	priv = netdev_priv(net_dev);
+-	mac_dev = priv->mac_dev;
+-
+-	phydev = net_dev->phydev;
+-	if (!phydev) {
+-		netdev_err(net_dev, "phy device not initialized\n");
+-		return -ENODEV;
+-	}
+-
+-	if (!phy_validate_pause(phydev, epause))
+-		return -EINVAL;
+-
+-	/* The MAC should know how to handle PAUSE frame autonegotiation before
+-	 * adjust_link is triggered by a forced renegotiation of sym/asym PAUSE
+-	 * settings.
+-	 */
+-	mac_dev->autoneg_pause = !!epause->autoneg;
+-	mac_dev->rx_pause_req = !!epause->rx_pause;
+-	mac_dev->tx_pause_req = !!epause->tx_pause;
+-
+-	/* Determine the sym/asym advertised PAUSE capabilities from the desired
+-	 * rx/tx pause settings.
+-	 */
+-
+-	phy_set_asym_pause(phydev, epause->rx_pause, epause->tx_pause);
+-
+-	fman_get_pause_cfg(mac_dev, &rx_pause, &tx_pause);
+-	err = fman_set_mac_active_pause(mac_dev, rx_pause, tx_pause);
+-	if (err < 0)
+-		netdev_err(net_dev, "set_mac_active_pause() = %d\n", err);
++	struct dpaa_priv *priv = netdev_priv(net_dev);
++	struct mac_device *mac_dev = priv->mac_dev;
+ 
+-	return err;
++	return phylink_ethtool_set_pauseparam(mac_dev->phylink, epause);
+ }
+ 
+ static int dpaa_get_sset_count(struct net_device *net_dev, int type)
+--- a/drivers/net/ethernet/freescale/fman/Kconfig
++++ b/drivers/net/ethernet/freescale/fman/Kconfig
+@@ -3,7 +3,6 @@ config FSL_FMAN
+ 	tristate "FMan support"
+ 	depends on FSL_SOC || ARCH_LAYERSCAPE || COMPILE_TEST
+ 	select GENERIC_ALLOCATOR
+-	select PHYLIB
+ 	select PHYLINK
+ 	select PCS
+ 	select PCS_LYNX
+--- a/drivers/net/ethernet/freescale/fman/fman_dtsec.c
++++ b/drivers/net/ethernet/freescale/fman/fman_dtsec.c
+@@ -17,6 +17,7 @@
+ #include <linux/crc32.h>
+ #include <linux/of_mdio.h>
+ #include <linux/mii.h>
++#include <linux/netdevice.h>
+ 
+ /* TBI register addresses */
+ #define MII_TBICON		0x11
+@@ -29,9 +30,6 @@
+ #define TBICON_CLK_SELECT	0x0020	/* Clock select */
+ #define TBICON_MI_MODE		0x0010	/* GMII mode (TBI if not set) */
+ 
+-#define TBIANA_SGMII		0x4001
+-#define TBIANA_1000X		0x01a0
+-
+ /* Interrupt Mask Register (IMASK) */
+ #define DTSEC_IMASK_BREN	0x80000000
+ #define DTSEC_IMASK_RXCEN	0x40000000
+@@ -92,9 +90,10 @@
+ 
+ #define DTSEC_ECNTRL_GMIIM		0x00000040
+ #define DTSEC_ECNTRL_TBIM		0x00000020
+-#define DTSEC_ECNTRL_SGMIIM		0x00000002
+ #define DTSEC_ECNTRL_RPM		0x00000010
+ #define DTSEC_ECNTRL_R100M		0x00000008
++#define DTSEC_ECNTRL_RMM		0x00000004
++#define DTSEC_ECNTRL_SGMIIM		0x00000002
+ #define DTSEC_ECNTRL_QSGMIIM		0x00000001
+ 
+ #define TCTRL_TTSE			0x00000040
+@@ -318,7 +317,8 @@ struct fman_mac {
+ 	void *fm;
+ 	struct fman_rev_info fm_rev_info;
+ 	bool basex_if;
+-	struct phy_device *tbiphy;
++	struct mdio_device *tbidev;
++	struct phylink_pcs pcs;
+ };
+ 
+ static void set_dflts(struct dtsec_cfg *cfg)
+@@ -356,56 +356,14 @@ static int init(struct dtsec_regs __iome
+ 		phy_interface_t iface, u16 iface_speed, u64 addr,
+ 		u32 exception_mask, u8 tbi_addr)
+ {
+-	bool is_rgmii, is_sgmii, is_qsgmii;
+ 	enet_addr_t eth_addr;
+-	u32 tmp;
++	u32 tmp = 0;
+ 	int i;
+ 
+ 	/* Soft reset */
+ 	iowrite32be(MACCFG1_SOFT_RESET, &regs->maccfg1);
+ 	iowrite32be(0, &regs->maccfg1);
+ 
+-	/* dtsec_id2 */
+-	tmp = ioread32be(&regs->tsec_id2);
+-
+-	/* check RGMII support */
+-	if (iface == PHY_INTERFACE_MODE_RGMII ||
+-	    iface == PHY_INTERFACE_MODE_RGMII_ID ||
+-	    iface == PHY_INTERFACE_MODE_RGMII_RXID ||
+-	    iface == PHY_INTERFACE_MODE_RGMII_TXID ||
+-	    iface == PHY_INTERFACE_MODE_RMII)
+-		if (tmp & DTSEC_ID2_INT_REDUCED_OFF)
+-			return -EINVAL;
+-
+-	if (iface == PHY_INTERFACE_MODE_SGMII ||
+-	    iface == PHY_INTERFACE_MODE_MII)
+-		if (tmp & DTSEC_ID2_INT_REDUCED_OFF)
+-			return -EINVAL;
+-
+-	is_rgmii = iface == PHY_INTERFACE_MODE_RGMII ||
+-		   iface == PHY_INTERFACE_MODE_RGMII_ID ||
+-		   iface == PHY_INTERFACE_MODE_RGMII_RXID ||
+-		   iface == PHY_INTERFACE_MODE_RGMII_TXID;
+-	is_sgmii = iface == PHY_INTERFACE_MODE_SGMII;
+-	is_qsgmii = iface == PHY_INTERFACE_MODE_QSGMII;
+-
+-	tmp = 0;
+-	if (is_rgmii || iface == PHY_INTERFACE_MODE_GMII)
+-		tmp |= DTSEC_ECNTRL_GMIIM;
+-	if (is_sgmii)
+-		tmp |= (DTSEC_ECNTRL_SGMIIM | DTSEC_ECNTRL_TBIM);
+-	if (is_qsgmii)
+-		tmp |= (DTSEC_ECNTRL_SGMIIM | DTSEC_ECNTRL_TBIM |
+-			DTSEC_ECNTRL_QSGMIIM);
+-	if (is_rgmii)
+-		tmp |= DTSEC_ECNTRL_RPM;
+-	if (iface_speed == SPEED_100)
+-		tmp |= DTSEC_ECNTRL_R100M;
+-
+-	iowrite32be(tmp, &regs->ecntrl);
+-
+-	tmp = 0;
+-
+ 	if (cfg->tx_pause_time)
+ 		tmp |= cfg->tx_pause_time;
+ 	if (cfg->tx_pause_time_extd)
+@@ -446,17 +404,10 @@ static int init(struct dtsec_regs __iome
+ 
+ 	tmp = 0;
+ 
+-	if (iface_speed < SPEED_1000)
+-		tmp |= MACCFG2_NIBBLE_MODE;
+-	else if (iface_speed == SPEED_1000)
+-		tmp |= MACCFG2_BYTE_MODE;
+-
+ 	tmp |= (cfg->preamble_len << MACCFG2_PREAMBLE_LENGTH_SHIFT) &
+ 		MACCFG2_PREAMBLE_LENGTH_MASK;
+ 	if (cfg->tx_pad_crc)
+ 		tmp |= MACCFG2_PAD_CRC_EN;
+-	/* Full Duplex */
+-	tmp |= MACCFG2_FULL_DUPLEX;
+ 	iowrite32be(tmp, &regs->maccfg2);
+ 
+ 	tmp = (((cfg->non_back_to_back_ipg1 <<
+@@ -525,10 +476,6 @@ static void set_bucket(struct dtsec_regs
+ 
+ static int check_init_parameters(struct fman_mac *dtsec)
+ {
+-	if (dtsec->max_speed >= SPEED_10000) {
+-		pr_err("1G MAC driver supports 1G or lower speeds\n");
+-		return -EINVAL;
+-	}
+ 	if ((dtsec->dtsec_drv_param)->rx_prepend >
+ 	    MAX_PACKET_ALIGNMENT) {
+ 		pr_err("packetAlignmentPadding can't be > than %d\n",
+@@ -630,22 +577,10 @@ static int get_exception_flag(enum fman_
+ 	return bit_mask;
+ }
+ 
+-static bool is_init_done(struct dtsec_cfg *dtsec_drv_params)
+-{
+-	/* Checks if dTSEC driver parameters were initialized */
+-	if (!dtsec_drv_params)
+-		return true;
+-
+-	return false;
+-}
+-
+ static u16 dtsec_get_max_frame_length(struct fman_mac *dtsec)
+ {
+ 	struct dtsec_regs __iomem *regs = dtsec->regs;
+ 
+-	if (is_init_done(dtsec->dtsec_drv_param))
+-		return 0;
+-
+ 	return (u16)ioread32be(&regs->maxfrm);
+ }
+ 
+@@ -682,6 +617,7 @@ static void dtsec_isr(void *handle)
+ 		dtsec->exception_cb(dtsec->dev_id, FM_MAC_EX_1G_COL_RET_LMT);
+ 	if (event & DTSEC_IMASK_XFUNEN) {
+ 		/* FM_TX_LOCKUP_ERRATA_DTSEC6 Errata workaround */
++		/* FIXME: This races with the rest of the driver! */
+ 		if (dtsec->fm_rev_info.major == 2) {
+ 			u32 tpkt1, tmp_reg1, tpkt2, tmp_reg2, i;
+ 			/* a. Write 0x00E0_0C00 to DTSEC_ID
+@@ -814,6 +750,43 @@ static void free_init_resources(struct f
+ 	dtsec->unicast_addr_hash = NULL;
+ }
+ 
++static struct fman_mac *pcs_to_dtsec(struct phylink_pcs *pcs)
++{
++	return container_of(pcs, struct fman_mac, pcs);
++}
++
++static void dtsec_pcs_get_state(struct phylink_pcs *pcs,
++				struct phylink_link_state *state)
++{
++	struct fman_mac *dtsec = pcs_to_dtsec(pcs);
++
++	phylink_mii_c22_pcs_get_state(dtsec->tbidev, state);
++}
++
++static int dtsec_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
++			    phy_interface_t interface,
++			    const unsigned long *advertising,
++			    bool permit_pause_to_mac)
++{
++	struct fman_mac *dtsec = pcs_to_dtsec(pcs);
++
++	return phylink_mii_c22_pcs_config(dtsec->tbidev, mode, interface,
++					  advertising);
++}
++
++static void dtsec_pcs_an_restart(struct phylink_pcs *pcs)
++{
++	struct fman_mac *dtsec = pcs_to_dtsec(pcs);
++
++	phylink_mii_c22_pcs_an_restart(dtsec->tbidev);
++}
++
++static const struct phylink_pcs_ops dtsec_pcs_ops = {
++	.pcs_get_state = dtsec_pcs_get_state,
++	.pcs_config = dtsec_pcs_config,
++	.pcs_an_restart = dtsec_pcs_an_restart,
++};
++
+ static void graceful_start(struct fman_mac *dtsec)
+ {
+ 	struct dtsec_regs __iomem *regs = dtsec->regs;
+@@ -854,36 +827,11 @@ static void graceful_stop(struct fman_ma
+ 
+ static int dtsec_enable(struct fman_mac *dtsec)
+ {
+-	struct dtsec_regs __iomem *regs = dtsec->regs;
+-	u32 tmp;
+-
+-	if (!is_init_done(dtsec->dtsec_drv_param))
+-		return -EINVAL;
+-
+-	/* Enable */
+-	tmp = ioread32be(&regs->maccfg1);
+-	tmp |= MACCFG1_RX_EN | MACCFG1_TX_EN;
+-	iowrite32be(tmp, &regs->maccfg1);
+-
+-	/* Graceful start - clear the graceful Rx/Tx stop bit */
+-	graceful_start(dtsec);
+-
+ 	return 0;
+ }
+ 
+ static void dtsec_disable(struct fman_mac *dtsec)
+ {
+-	struct dtsec_regs __iomem *regs = dtsec->regs;
+-	u32 tmp;
+-
+-	WARN_ON_ONCE(!is_init_done(dtsec->dtsec_drv_param));
+-
+-	/* Graceful stop - Assert the graceful Rx/Tx stop bit */
+-	graceful_stop(dtsec);
+-
+-	tmp = ioread32be(&regs->maccfg1);
+-	tmp &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
+-	iowrite32be(tmp, &regs->maccfg1);
+ }
+ 
+ static int dtsec_set_tx_pause_frames(struct fman_mac *dtsec,
+@@ -894,11 +842,6 @@ static int dtsec_set_tx_pause_frames(str
+ 	struct dtsec_regs __iomem *regs = dtsec->regs;
+ 	u32 ptv = 0;
+ 
+-	if (!is_init_done(dtsec->dtsec_drv_param))
+-		return -EINVAL;
+-
+-	graceful_stop(dtsec);
+-
+ 	if (pause_time) {
+ 		/* FM_BAD_TX_TS_IN_B_2_B_ERRATA_DTSEC_A003 Errata workaround */
+ 		if (dtsec->fm_rev_info.major == 2 && pause_time <= 320) {
+@@ -919,8 +862,6 @@ static int dtsec_set_tx_pause_frames(str
+ 		iowrite32be(ioread32be(&regs->maccfg1) & ~MACCFG1_TX_FLOW,
+ 			    &regs->maccfg1);
+ 
+-	graceful_start(dtsec);
+-
+ 	return 0;
+ }
+ 
+@@ -929,11 +870,6 @@ static int dtsec_accept_rx_pause_frames(
+ 	struct dtsec_regs __iomem *regs = dtsec->regs;
+ 	u32 tmp;
+ 
+-	if (!is_init_done(dtsec->dtsec_drv_param))
+-		return -EINVAL;
+-
+-	graceful_stop(dtsec);
+-
+ 	tmp = ioread32be(&regs->maccfg1);
+ 	if (en)
+ 		tmp |= MACCFG1_RX_FLOW;
+@@ -941,17 +877,125 @@ static int dtsec_accept_rx_pause_frames(
+ 		tmp &= ~MACCFG1_RX_FLOW;
+ 	iowrite32be(tmp, &regs->maccfg1);
+ 
++	return 0;
++}
++
++static struct phylink_pcs *dtsec_select_pcs(struct phylink_config *config,
++					    phy_interface_t iface)
++{
++	struct fman_mac *dtsec = fman_config_to_mac(config)->fman_mac;
++
++	switch (iface) {
++	case PHY_INTERFACE_MODE_SGMII:
++	case PHY_INTERFACE_MODE_1000BASEX:
++	case PHY_INTERFACE_MODE_2500BASEX:
++		return &dtsec->pcs;
++	default:
++		return NULL;
++	}
++}
++
++static void dtsec_mac_config(struct phylink_config *config, unsigned int mode,
++			     const struct phylink_link_state *state)
++{
++	struct mac_device *mac_dev = fman_config_to_mac(config);
++	struct dtsec_regs __iomem *regs = mac_dev->fman_mac->regs;
++	u32 tmp;
++
++	switch (state->interface) {
++	case PHY_INTERFACE_MODE_RMII:
++		tmp = DTSEC_ECNTRL_RMM;
++		break;
++	case PHY_INTERFACE_MODE_RGMII:
++	case PHY_INTERFACE_MODE_RGMII_ID:
++	case PHY_INTERFACE_MODE_RGMII_RXID:
++	case PHY_INTERFACE_MODE_RGMII_TXID:
++		tmp = DTSEC_ECNTRL_GMIIM | DTSEC_ECNTRL_RPM;
++		break;
++	case PHY_INTERFACE_MODE_SGMII:
++	case PHY_INTERFACE_MODE_1000BASEX:
++	case PHY_INTERFACE_MODE_2500BASEX:
++		tmp = DTSEC_ECNTRL_TBIM | DTSEC_ECNTRL_SGMIIM;
++		break;
++	default:
++		dev_warn(mac_dev->dev, "cannot configure dTSEC for %s\n",
++			 phy_modes(state->interface));
++		return;
++	}
++
++	iowrite32be(tmp, &regs->ecntrl);
++}
++
++static void dtsec_link_up(struct phylink_config *config, struct phy_device *phy,
++			  unsigned int mode, phy_interface_t interface,
++			  int speed, int duplex, bool tx_pause, bool rx_pause)
++{
++	struct mac_device *mac_dev = fman_config_to_mac(config);
++	struct fman_mac *dtsec = mac_dev->fman_mac;
++	struct dtsec_regs __iomem *regs = dtsec->regs;
++	u16 pause_time = tx_pause ? FSL_FM_PAUSE_TIME_ENABLE :
++			 FSL_FM_PAUSE_TIME_DISABLE;
++	u32 tmp;
++
++	dtsec_set_tx_pause_frames(dtsec, 0, pause_time, 0);
++	dtsec_accept_rx_pause_frames(dtsec, rx_pause);
++
++	tmp = ioread32be(&regs->ecntrl);
++	if (speed == SPEED_100)
++		tmp |= DTSEC_ECNTRL_R100M;
++	else
++		tmp &= ~DTSEC_ECNTRL_R100M;
++	iowrite32be(tmp, &regs->ecntrl);
++
++	tmp = ioread32be(&regs->maccfg2);
++	tmp &= ~(MACCFG2_NIBBLE_MODE | MACCFG2_BYTE_MODE | MACCFG2_FULL_DUPLEX);
++	if (speed >= SPEED_1000)
++		tmp |= MACCFG2_BYTE_MODE;
++	else
++		tmp |= MACCFG2_NIBBLE_MODE;
++
++	if (duplex == DUPLEX_FULL)
++		tmp |= MACCFG2_FULL_DUPLEX;
++
++	iowrite32be(tmp, &regs->maccfg2);
++
++	mac_dev->update_speed(mac_dev, speed);
++
++	/* Enable */
++	tmp = ioread32be(&regs->maccfg1);
++	tmp |= MACCFG1_RX_EN | MACCFG1_TX_EN;
++	iowrite32be(tmp, &regs->maccfg1);
++
++	/* Graceful start - clear the graceful Rx/Tx stop bit */
+ 	graceful_start(dtsec);
++}
+ 
+-	return 0;
++static void dtsec_link_down(struct phylink_config *config, unsigned int mode,
++			    phy_interface_t interface)
++{
++	struct fman_mac *dtsec = fman_config_to_mac(config)->fman_mac;
++	struct dtsec_regs __iomem *regs = dtsec->regs;
++	u32 tmp;
++
++	/* Graceful stop - Assert the graceful Rx/Tx stop bit */
++	graceful_stop(dtsec);
++
++	tmp = ioread32be(&regs->maccfg1);
++	tmp &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
++	iowrite32be(tmp, &regs->maccfg1);
+ }
+ 
++static const struct phylink_mac_ops dtsec_mac_ops = {
++	.validate = phylink_generic_validate,
++	.mac_select_pcs = dtsec_select_pcs,
++	.mac_config = dtsec_mac_config,
++	.mac_link_up = dtsec_link_up,
++	.mac_link_down = dtsec_link_down,
++};
++
+ static int dtsec_modify_mac_address(struct fman_mac *dtsec,
+ 				    const enet_addr_t *enet_addr)
+ {
+-	if (!is_init_done(dtsec->dtsec_drv_param))
+-		return -EINVAL;
+-
+ 	graceful_stop(dtsec);
+ 
+ 	/* Initialize MAC Station Address registers (1 & 2)
+@@ -975,9 +1019,6 @@ static int dtsec_add_hash_mac_address(st
+ 	u32 crc = 0xFFFFFFFF;
+ 	bool mcast, ghtx;
+ 
+-	if (!is_init_done(dtsec->dtsec_drv_param))
+-		return -EINVAL;
+-
+ 	addr = ENET_ADDR_TO_UINT64(*eth_addr);
+ 
+ 	ghtx = (bool)((ioread32be(&regs->rctrl) & RCTRL_GHTX) ? true : false);
+@@ -1037,9 +1078,6 @@ static int dtsec_set_allmulti(struct fma
+ 	u32 tmp;
+ 	struct dtsec_regs __iomem *regs = dtsec->regs;
+ 
+-	if (!is_init_done(dtsec->dtsec_drv_param))
+-		return -EINVAL;
+-
+ 	tmp = ioread32be(&regs->rctrl);
+ 	if (enable)
+ 		tmp |= RCTRL_MPROM;
+@@ -1056,9 +1094,6 @@ static int dtsec_set_tstamp(struct fman_
+ 	struct dtsec_regs __iomem *regs = dtsec->regs;
+ 	u32 rctrl, tctrl;
+ 
+-	if (!is_init_done(dtsec->dtsec_drv_param))
+-		return -EINVAL;
+-
+ 	rctrl = ioread32be(&regs->rctrl);
+ 	tctrl = ioread32be(&regs->tctrl);
+ 
+@@ -1087,9 +1122,6 @@ static int dtsec_del_hash_mac_address(st
+ 	u32 crc = 0xFFFFFFFF;
+ 	bool mcast, ghtx;
+ 
+-	if (!is_init_done(dtsec->dtsec_drv_param))
+-		return -EINVAL;
+-
+ 	addr = ENET_ADDR_TO_UINT64(*eth_addr);
+ 
+ 	ghtx = (bool)((ioread32be(&regs->rctrl) & RCTRL_GHTX) ? true : false);
+@@ -1153,9 +1185,6 @@ static int dtsec_set_promiscuous(struct
+ 	struct dtsec_regs __iomem *regs = dtsec->regs;
+ 	u32 tmp;
+ 
+-	if (!is_init_done(dtsec->dtsec_drv_param))
+-		return -EINVAL;
+-
+ 	/* Set unicast promiscuous */
+ 	tmp = ioread32be(&regs->rctrl);
+ 	if (new_val)
+@@ -1177,90 +1206,12 @@ static int dtsec_set_promiscuous(struct
+ 	return 0;
+ }
+ 
+-static int dtsec_adjust_link(struct fman_mac *dtsec, u16 speed)
+-{
+-	struct dtsec_regs __iomem *regs = dtsec->regs;
+-	u32 tmp;
+-
+-	if (!is_init_done(dtsec->dtsec_drv_param))
+-		return -EINVAL;
+-
+-	graceful_stop(dtsec);
+-
+-	tmp = ioread32be(&regs->maccfg2);
+-
+-	/* Full Duplex */
+-	tmp |= MACCFG2_FULL_DUPLEX;
+-
+-	tmp &= ~(MACCFG2_NIBBLE_MODE | MACCFG2_BYTE_MODE);
+-	if (speed < SPEED_1000)
+-		tmp |= MACCFG2_NIBBLE_MODE;
+-	else if (speed == SPEED_1000)
+-		tmp |= MACCFG2_BYTE_MODE;
+-	iowrite32be(tmp, &regs->maccfg2);
+-
+-	tmp = ioread32be(&regs->ecntrl);
+-	if (speed == SPEED_100)
+-		tmp |= DTSEC_ECNTRL_R100M;
+-	else
+-		tmp &= ~DTSEC_ECNTRL_R100M;
+-	iowrite32be(tmp, &regs->ecntrl);
+-
+-	graceful_start(dtsec);
+-
+-	return 0;
+-}
+-
+-static int dtsec_restart_autoneg(struct fman_mac *dtsec)
+-{
+-	u16 tmp_reg16;
+-
+-	if (!is_init_done(dtsec->dtsec_drv_param))
+-		return -EINVAL;
+-
+-	tmp_reg16 = phy_read(dtsec->tbiphy, MII_BMCR);
+-
+-	tmp_reg16 &= ~(BMCR_SPEED100 | BMCR_SPEED1000);
+-	tmp_reg16 |= (BMCR_ANENABLE | BMCR_ANRESTART |
+-		      BMCR_FULLDPLX | BMCR_SPEED1000);
+-
+-	phy_write(dtsec->tbiphy, MII_BMCR, tmp_reg16);
+-
+-	return 0;
+-}
+-
+-static void adjust_link_dtsec(struct mac_device *mac_dev)
+-{
+-	struct phy_device *phy_dev = mac_dev->phy_dev;
+-	struct fman_mac *fman_mac;
+-	bool rx_pause, tx_pause;
+-	int err;
+-
+-	fman_mac = mac_dev->fman_mac;
+-	if (!phy_dev->link) {
+-		dtsec_restart_autoneg(fman_mac);
+-
+-		return;
+-	}
+-
+-	dtsec_adjust_link(fman_mac, phy_dev->speed);
+-	mac_dev->update_speed(mac_dev, phy_dev->speed);
+-	fman_get_pause_cfg(mac_dev, &rx_pause, &tx_pause);
+-	err = fman_set_mac_active_pause(mac_dev, rx_pause, tx_pause);
+-	if (err < 0)
+-		dev_err(mac_dev->dev, "fman_set_mac_active_pause() = %d\n",
+-			err);
+-}
+-
+ static int dtsec_set_exception(struct fman_mac *dtsec,
+ 			       enum fman_mac_exceptions exception, bool enable)
+ {
+ 	struct dtsec_regs __iomem *regs = dtsec->regs;
+ 	u32 bit_mask = 0;
+ 
+-	if (!is_init_done(dtsec->dtsec_drv_param))
+-		return -EINVAL;
+-
+ 	if (exception != FM_MAC_EX_1G_1588_TS_RX_ERR) {
+ 		bit_mask = get_exception_flag(exception);
+ 		if (bit_mask) {
+@@ -1310,12 +1261,9 @@ static int dtsec_init(struct fman_mac *d
+ {
+ 	struct dtsec_regs __iomem *regs = dtsec->regs;
+ 	struct dtsec_cfg *dtsec_drv_param;
+-	u16 max_frm_ln;
++	u16 max_frm_ln, tbicon;
+ 	int err;
+ 
+-	if (is_init_done(dtsec->dtsec_drv_param))
+-		return -EINVAL;
+-
+ 	if (DEFAULT_RESET_ON_INIT &&
+ 	    (fman_reset_mac(dtsec->fm, dtsec->mac_id) != 0)) {
+ 		pr_err("Can't reset MAC!\n");
+@@ -1330,38 +1278,19 @@ static int dtsec_init(struct fman_mac *d
+ 
+ 	err = init(dtsec->regs, dtsec_drv_param, dtsec->phy_if,
+ 		   dtsec->max_speed, dtsec->addr, dtsec->exceptions,
+-		   dtsec->tbiphy->mdio.addr);
++		   dtsec->tbidev->addr);
+ 	if (err) {
+ 		free_init_resources(dtsec);
+ 		pr_err("DTSEC version doesn't support this i/f mode\n");
+ 		return err;
+ 	}
+ 
+-	if (dtsec->phy_if == PHY_INTERFACE_MODE_SGMII) {
+-		u16 tmp_reg16;
+-
+-		/* Configure the TBI PHY Control Register */
+-		tmp_reg16 = TBICON_CLK_SELECT | TBICON_SOFT_RESET;
+-		phy_write(dtsec->tbiphy, MII_TBICON, tmp_reg16);
+-
+-		tmp_reg16 = TBICON_CLK_SELECT;
+-		phy_write(dtsec->tbiphy, MII_TBICON, tmp_reg16);
+-
+-		tmp_reg16 = (BMCR_RESET | BMCR_ANENABLE |
+-			     BMCR_FULLDPLX | BMCR_SPEED1000);
+-		phy_write(dtsec->tbiphy, MII_BMCR, tmp_reg16);
+-
+-		if (dtsec->basex_if)
+-			tmp_reg16 = TBIANA_1000X;
+-		else
+-			tmp_reg16 = TBIANA_SGMII;
+-		phy_write(dtsec->tbiphy, MII_ADVERTISE, tmp_reg16);
++	/* Configure the TBI PHY Control Register */
++	tbicon = TBICON_CLK_SELECT | TBICON_SOFT_RESET;
++	mdiodev_write(dtsec->tbidev, MII_TBICON, tbicon);
+ 
+-		tmp_reg16 = (BMCR_ANENABLE | BMCR_ANRESTART |
+-			     BMCR_FULLDPLX | BMCR_SPEED1000);
+-
+-		phy_write(dtsec->tbiphy, MII_BMCR, tmp_reg16);
+-	}
++	tbicon = TBICON_CLK_SELECT;
++	mdiodev_write(dtsec->tbidev, MII_TBICON, tbicon);
+ 
+ 	/* Max Frame Length */
+ 	max_frm_ln = (u16)ioread32be(&regs->maxfrm);
+@@ -1406,6 +1335,8 @@ static int dtsec_free(struct fman_mac *d
+ 
+ 	kfree(dtsec->dtsec_drv_param);
+ 	dtsec->dtsec_drv_param = NULL;
++	if (!IS_ERR_OR_NULL(dtsec->tbidev))
++		put_device(&dtsec->tbidev->dev);
+ 	kfree(dtsec);
+ 
+ 	return 0;
+@@ -1434,7 +1365,6 @@ static struct fman_mac *dtsec_config(str
+ 
+ 	dtsec->regs = mac_dev->vaddr;
+ 	dtsec->addr = ENET_ADDR_TO_UINT64(mac_dev->addr);
+-	dtsec->max_speed = params->max_speed;
+ 	dtsec->phy_if = mac_dev->phy_if;
+ 	dtsec->mac_id = params->mac_id;
+ 	dtsec->exceptions = (DTSEC_IMASK_BREN	|
+@@ -1457,7 +1387,6 @@ static struct fman_mac *dtsec_config(str
+ 	dtsec->en_tsu_err_exception = dtsec->dtsec_drv_param->ptp_exception_en;
+ 
+ 	dtsec->fm = params->fm;
+-	dtsec->basex_if = params->basex_if;
+ 
+ 	/* Save FMan revision */
+ 	fman_get_revision(dtsec->fm, &dtsec->fm_rev_info);
+@@ -1476,18 +1405,18 @@ int dtsec_initialization(struct mac_devi
+ 	int			err;
+ 	struct fman_mac		*dtsec;
+ 	struct device_node	*phy_node;
++	unsigned long		 capabilities;
++	unsigned long		*supported;
+ 
++	mac_dev->phylink_ops		= &dtsec_mac_ops;
+ 	mac_dev->set_promisc		= dtsec_set_promiscuous;
+ 	mac_dev->change_addr		= dtsec_modify_mac_address;
+ 	mac_dev->add_hash_mac_addr	= dtsec_add_hash_mac_address;
+ 	mac_dev->remove_hash_mac_addr	= dtsec_del_hash_mac_address;
+-	mac_dev->set_tx_pause		= dtsec_set_tx_pause_frames;
+-	mac_dev->set_rx_pause		= dtsec_accept_rx_pause_frames;
+ 	mac_dev->set_exception		= dtsec_set_exception;
+ 	mac_dev->set_allmulti		= dtsec_set_allmulti;
+ 	mac_dev->set_tstamp		= dtsec_set_tstamp;
+ 	mac_dev->set_multi		= fman_set_multi;
+-	mac_dev->adjust_link            = adjust_link_dtsec;
+ 	mac_dev->enable			= dtsec_enable;
+ 	mac_dev->disable		= dtsec_disable;
+ 
+@@ -1502,19 +1431,56 @@ int dtsec_initialization(struct mac_devi
+ 	dtsec->dtsec_drv_param->tx_pad_crc = true;
+ 
+ 	phy_node = of_parse_phandle(mac_node, "tbi-handle", 0);
+-	if (!phy_node) {
+-		pr_err("TBI PHY node is not available\n");
++	if (!phy_node || of_device_is_available(phy_node)) {
++		of_node_put(phy_node);
+ 		err = -EINVAL;
++		dev_err_probe(mac_dev->dev, err,
++			      "TBI PCS node is not available\n");
+ 		goto _return_fm_mac_free;
+ 	}
+ 
+-	dtsec->tbiphy = of_phy_find_device(phy_node);
+-	if (!dtsec->tbiphy) {
+-		pr_err("of_phy_find_device (TBI PHY) failed\n");
+-		err = -EINVAL;
++	dtsec->tbidev = of_mdio_find_device(phy_node);
++	of_node_put(phy_node);
++	if (!dtsec->tbidev) {
++		err = -EPROBE_DEFER;
++		dev_err_probe(mac_dev->dev, err,
++			      "could not find mdiodev for PCS\n");
+ 		goto _return_fm_mac_free;
+ 	}
+-	put_device(&dtsec->tbiphy->mdio.dev);
++	dtsec->pcs.ops = &dtsec_pcs_ops;
++	dtsec->pcs.poll = true;
++
++	supported = mac_dev->phylink_config.supported_interfaces;
++
++	/* FIXME: Can we use DTSEC_ID2_INT_FULL_OFF to determine if these are
++	 * supported? If not, we can determine support via the phy if SerDes
++	 * support is added.
++	 */
++	if (mac_dev->phy_if == PHY_INTERFACE_MODE_SGMII ||
++	    mac_dev->phy_if == PHY_INTERFACE_MODE_1000BASEX) {
++		__set_bit(PHY_INTERFACE_MODE_SGMII, supported);
++		__set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
++	} else if (mac_dev->phy_if == PHY_INTERFACE_MODE_2500BASEX) {
++		__set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
++	}
++
++	if (!(ioread32be(&dtsec->regs->tsec_id2) & DTSEC_ID2_INT_REDUCED_OFF)) {
++		phy_interface_set_rgmii(supported);
++
++		/* DTSEC_ID2_INT_REDUCED_OFF indicates that the dTSEC supports
++		 * RMII and RGMII. However, the only SoCs which support RMII
++		 * are the P1017 and P1023. Avoid advertising this mode on
++		 * other SoCs. This is a bit of a moot point, since there's no
++		 * in-tree support for ethernet on these platforms...
++		 */
++		if (of_machine_is_compatible("fsl,P1023") ||
++		    of_machine_is_compatible("fsl,P1023RDB"))
++			__set_bit(PHY_INTERFACE_MODE_RMII, supported);
++	}
++
++	capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE;
++	capabilities |= MAC_10 | MAC_100 | MAC_1000FD | MAC_2500FD;
++	mac_dev->phylink_config.mac_capabilities = capabilities;
+ 
+ 	err = dtsec_init(dtsec);
+ 	if (err < 0)
+--- a/drivers/net/ethernet/freescale/fman/fman_mac.h
++++ b/drivers/net/ethernet/freescale/fman/fman_mac.h
+@@ -170,20 +170,10 @@ struct fman_mac_params {
+ 	 * 0 - FM_MAX_NUM_OF_10G_MACS
+ 	 */
+ 	u8 mac_id;
+-	/* Note that the speed should indicate the maximum rate that
+-	 * this MAC should support rather than the actual speed;
+-	 */
+-	u16 max_speed;
+ 	/* A handle to the FM object this port related to */
+ 	void *fm;
+ 	fman_mac_exception_cb *event_cb;    /* MDIO Events Callback Routine */
+ 	fman_mac_exception_cb *exception_cb;/* Exception Callback Routine */
+-	/* SGMII/QSGII interface with 1000BaseX auto-negotiation between MAC
+-	 * and phy or backplane; Note: 1000BaseX auto-negotiation relates only
+-	 * to interface between MAC and phy/backplane, SGMII phy can still
+-	 * synchronize with far-end phy at 10Mbps, 100Mbps or 1000Mbps
+-	*/
+-	bool basex_if;
+ };
+ 
+ struct eth_hash_t {
+--- a/drivers/net/ethernet/freescale/fman/fman_memac.c
++++ b/drivers/net/ethernet/freescale/fman/fman_memac.c
+@@ -278,9 +278,6 @@ struct fman_mac {
+ 	struct memac_regs __iomem *regs;
+ 	/* MAC address of device */
+ 	u64 addr;
+-	/* Ethernet physical interface */
+-	phy_interface_t phy_if;
+-	u16 max_speed;
+ 	struct mac_device *dev_id; /* device cookie used by the exception cbs */
+ 	fman_mac_exception_cb *exception_cb;
+ 	fman_mac_exception_cb *event_cb;
+@@ -293,12 +290,12 @@ struct fman_mac {
+ 	struct memac_cfg *memac_drv_param;
+ 	void *fm;
+ 	struct fman_rev_info fm_rev_info;
+-	bool basex_if;
+ 	struct phy *serdes;
+ 	struct phylink_pcs *sgmii_pcs;
+ 	struct phylink_pcs *qsgmii_pcs;
+ 	struct phylink_pcs *xfi_pcs;
+ 	bool allmulti_enabled;
++	bool rgmii_no_half_duplex;
+ };
+ 
+ static void add_addr_in_paddr(struct memac_regs __iomem *regs, const u8 *adr,
+@@ -356,7 +353,6 @@ static void set_exception(struct memac_r
+ }
+ 
+ static int init(struct memac_regs __iomem *regs, struct memac_cfg *cfg,
+-		phy_interface_t phy_if, u16 speed, bool slow_10g_if,
+ 		u32 exceptions)
+ {
+ 	u32 tmp;
+@@ -384,41 +380,6 @@ static int init(struct memac_regs __iome
+ 	iowrite32be((u32)cfg->pause_quanta, &regs->pause_quanta[0]);
+ 	iowrite32be((u32)0, &regs->pause_thresh[0]);
+ 
+-	/* IF_MODE */
+-	tmp = 0;
+-	switch (phy_if) {
+-	case PHY_INTERFACE_MODE_XGMII:
+-		tmp |= IF_MODE_10G;
+-		break;
+-	case PHY_INTERFACE_MODE_MII:
+-		tmp |= IF_MODE_MII;
+-		break;
+-	default:
+-		tmp |= IF_MODE_GMII;
+-		if (phy_if == PHY_INTERFACE_MODE_RGMII ||
+-		    phy_if == PHY_INTERFACE_MODE_RGMII_ID ||
+-		    phy_if == PHY_INTERFACE_MODE_RGMII_RXID ||
+-		    phy_if == PHY_INTERFACE_MODE_RGMII_TXID)
+-			tmp |= IF_MODE_RGMII | IF_MODE_RGMII_AUTO;
+-	}
+-	iowrite32be(tmp, &regs->if_mode);
+-
+-	/* TX_FIFO_SECTIONS */
+-	tmp = 0;
+-	if (phy_if == PHY_INTERFACE_MODE_XGMII) {
+-		if (slow_10g_if) {
+-			tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_SLOW_10G |
+-				TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G);
+-		} else {
+-			tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_10G |
+-				TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G);
+-		}
+-	} else {
+-		tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_1G |
+-			TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G);
+-	}
+-	iowrite32be(tmp, &regs->tx_fifo_sections);
+-
+ 	/* clear all pending events and set-up interrupts */
+ 	iowrite32be(0xffffffff, &regs->ievent);
+ 	set_exception(regs, exceptions, true);
+@@ -458,24 +419,6 @@ static u32 get_mac_addr_hash_code(u64 et
+ 	return xor_val;
+ }
+ 
+-static void setup_sgmii_internal(struct fman_mac *memac,
+-				 struct phylink_pcs *pcs,
+-				 struct fixed_phy_status *fixed_link)
+-{
+-	__ETHTOOL_DECLARE_LINK_MODE_MASK(advertising);
+-	phy_interface_t iface = memac->basex_if ? PHY_INTERFACE_MODE_1000BASEX :
+-				PHY_INTERFACE_MODE_SGMII;
+-	unsigned int mode = fixed_link ? MLO_AN_FIXED : MLO_AN_INBAND;
+-
+-	linkmode_set_pause(advertising, true, true);
+-	pcs->ops->pcs_config(pcs, mode, iface, advertising, true);
+-	if (fixed_link)
+-		pcs->ops->pcs_link_up(pcs, mode, iface, fixed_link->speed,
+-				      fixed_link->duplex);
+-	else
+-		pcs->ops->pcs_an_restart(pcs);
+-}
+-
+ static int check_init_parameters(struct fman_mac *memac)
+ {
+ 	if (!memac->exception_cb) {
+@@ -581,41 +524,31 @@ static void free_init_resources(struct f
+ 	memac->unicast_addr_hash = NULL;
+ }
+ 
+-static bool is_init_done(struct memac_cfg *memac_drv_params)
+-{
+-	/* Checks if mEMAC driver parameters were initialized */
+-	if (!memac_drv_params)
+-		return true;
+-
+-	return false;
+-}
+-
+ static int memac_enable(struct fman_mac *memac)
+ {
+-	struct memac_regs __iomem *regs = memac->regs;
+-	u32 tmp;
++	int ret;
+ 
+-	if (!is_init_done(memac->memac_drv_param))
+-		return -EINVAL;
++	ret = phy_init(memac->serdes);
++	if (ret) {
++		dev_err(memac->dev_id->dev,
++			"could not initialize serdes: %pe\n", ERR_PTR(ret));
++		return ret;
++	}
+ 
+-	tmp = ioread32be(&regs->command_config);
+-	tmp |= CMD_CFG_RX_EN | CMD_CFG_TX_EN;
+-	iowrite32be(tmp, &regs->command_config);
++	ret = phy_power_on(memac->serdes);
++	if (ret) {
++		dev_err(memac->dev_id->dev,
++			"could not power on serdes: %pe\n", ERR_PTR(ret));
++		phy_exit(memac->serdes);
++	}
+ 
+-	return 0;
++	return ret;
+ }
+ 
+ static void memac_disable(struct fman_mac *memac)
+-
+ {
+-	struct memac_regs __iomem *regs = memac->regs;
+-	u32 tmp;
+-
+-	WARN_ON_ONCE(!is_init_done(memac->memac_drv_param));
+-
+-	tmp = ioread32be(&regs->command_config);
+-	tmp &= ~(CMD_CFG_RX_EN | CMD_CFG_TX_EN);
+-	iowrite32be(tmp, &regs->command_config);
++	phy_power_off(memac->serdes);
++	phy_exit(memac->serdes);
+ }
+ 
+ static int memac_set_promiscuous(struct fman_mac *memac, bool new_val)
+@@ -623,9 +556,6 @@ static int memac_set_promiscuous(struct
+ 	struct memac_regs __iomem *regs = memac->regs;
+ 	u32 tmp;
+ 
+-	if (!is_init_done(memac->memac_drv_param))
+-		return -EINVAL;
+-
+ 	tmp = ioread32be(&regs->command_config);
+ 	if (new_val)
+ 		tmp |= CMD_CFG_PROMIS_EN;
+@@ -637,73 +567,12 @@ static int memac_set_promiscuous(struct
+ 	return 0;
+ }
+ 
+-static int memac_adjust_link(struct fman_mac *memac, u16 speed)
+-{
+-	struct memac_regs __iomem *regs = memac->regs;
+-	u32 tmp;
+-
+-	if (!is_init_done(memac->memac_drv_param))
+-		return -EINVAL;
+-
+-	tmp = ioread32be(&regs->if_mode);
+-
+-	/* Set full duplex */
+-	tmp &= ~IF_MODE_HD;
+-
+-	if (phy_interface_mode_is_rgmii(memac->phy_if)) {
+-		/* Configure RGMII in manual mode */
+-		tmp &= ~IF_MODE_RGMII_AUTO;
+-		tmp &= ~IF_MODE_RGMII_SP_MASK;
+-		/* Full duplex */
+-		tmp |= IF_MODE_RGMII_FD;
+-
+-		switch (speed) {
+-		case SPEED_1000:
+-			tmp |= IF_MODE_RGMII_1000;
+-			break;
+-		case SPEED_100:
+-			tmp |= IF_MODE_RGMII_100;
+-			break;
+-		case SPEED_10:
+-			tmp |= IF_MODE_RGMII_10;
+-			break;
+-		default:
+-			break;
+-		}
+-	}
+-
+-	iowrite32be(tmp, &regs->if_mode);
+-
+-	return 0;
+-}
+-
+-static void adjust_link_memac(struct mac_device *mac_dev)
+-{
+-	struct phy_device *phy_dev = mac_dev->phy_dev;
+-	struct fman_mac *fman_mac;
+-	bool rx_pause, tx_pause;
+-	int err;
+-
+-	fman_mac = mac_dev->fman_mac;
+-	memac_adjust_link(fman_mac, phy_dev->speed);
+-	mac_dev->update_speed(mac_dev, phy_dev->speed);
+-
+-	fman_get_pause_cfg(mac_dev, &rx_pause, &tx_pause);
+-	err = fman_set_mac_active_pause(mac_dev, rx_pause, tx_pause);
+-	if (err < 0)
+-		dev_err(mac_dev->dev, "fman_set_mac_active_pause() = %d\n",
+-			err);
+-}
+-
+ static int memac_set_tx_pause_frames(struct fman_mac *memac, u8 priority,
+ 				     u16 pause_time, u16 thresh_time)
+ {
+ 	struct memac_regs __iomem *regs = memac->regs;
+ 	u32 tmp;
+ 
+-	if (!is_init_done(memac->memac_drv_param))
+-		return -EINVAL;
+-
+ 	tmp = ioread32be(&regs->tx_fifo_sections);
+ 
+ 	GET_TX_EMPTY_DEFAULT_VALUE(tmp);
+@@ -738,9 +607,6 @@ static int memac_accept_rx_pause_frames(
+ 	struct memac_regs __iomem *regs = memac->regs;
+ 	u32 tmp;
+ 
+-	if (!is_init_done(memac->memac_drv_param))
+-		return -EINVAL;
+-
+ 	tmp = ioread32be(&regs->command_config);
+ 	if (en)
+ 		tmp &= ~CMD_CFG_PAUSE_IGNORE;
+@@ -752,12 +618,175 @@ static int memac_accept_rx_pause_frames(
+ 	return 0;
+ }
+ 
++static void memac_validate(struct phylink_config *config,
++			   unsigned long *supported,
++			   struct phylink_link_state *state)
++{
++	struct fman_mac *memac = fman_config_to_mac(config)->fman_mac;
++	unsigned long caps = config->mac_capabilities;
++
++	if (phy_interface_mode_is_rgmii(state->interface) &&
++	    memac->rgmii_no_half_duplex)
++		caps &= ~(MAC_10HD | MAC_100HD);
++
++	phylink_validate_mask_caps(supported, state, caps);
++}
++
++/**
++ * memac_if_mode() - Convert an interface mode into an IF_MODE config
++ * @interface: A phy interface mode
++ *
++ * Return: A configuration word, suitable for programming into the lower bits
++ *         of %IF_MODE.
++ */
++static u32 memac_if_mode(phy_interface_t interface)
++{
++	switch (interface) {
++	case PHY_INTERFACE_MODE_MII:
++		return IF_MODE_MII;
++	case PHY_INTERFACE_MODE_RGMII:
++	case PHY_INTERFACE_MODE_RGMII_ID:
++	case PHY_INTERFACE_MODE_RGMII_RXID:
++	case PHY_INTERFACE_MODE_RGMII_TXID:
++		return IF_MODE_GMII | IF_MODE_RGMII;
++	case PHY_INTERFACE_MODE_SGMII:
++	case PHY_INTERFACE_MODE_1000BASEX:
++	case PHY_INTERFACE_MODE_QSGMII:
++		return IF_MODE_GMII;
++	case PHY_INTERFACE_MODE_10GBASER:
++		return IF_MODE_10G;
++	default:
++		WARN_ON_ONCE(1);
++		return 0;
++	}
++}
++
++static struct phylink_pcs *memac_select_pcs(struct phylink_config *config,
++					    phy_interface_t iface)
++{
++	struct fman_mac *memac = fman_config_to_mac(config)->fman_mac;
++
++	switch (iface) {
++	case PHY_INTERFACE_MODE_SGMII:
++	case PHY_INTERFACE_MODE_1000BASEX:
++		return memac->sgmii_pcs;
++	case PHY_INTERFACE_MODE_QSGMII:
++		return memac->qsgmii_pcs;
++	case PHY_INTERFACE_MODE_10GBASER:
++		return memac->xfi_pcs;
++	default:
++		return NULL;
++	}
++}
++
++static int memac_prepare(struct phylink_config *config, unsigned int mode,
++			 phy_interface_t iface)
++{
++	struct fman_mac *memac = fman_config_to_mac(config)->fman_mac;
++
++	switch (iface) {
++	case PHY_INTERFACE_MODE_SGMII:
++	case PHY_INTERFACE_MODE_1000BASEX:
++	case PHY_INTERFACE_MODE_QSGMII:
++	case PHY_INTERFACE_MODE_10GBASER:
++		return phy_set_mode_ext(memac->serdes, PHY_MODE_ETHERNET,
++					iface);
++	default:
++		return 0;
++	}
++}
++
++static void memac_mac_config(struct phylink_config *config, unsigned int mode,
++			     const struct phylink_link_state *state)
++{
++	struct mac_device *mac_dev = fman_config_to_mac(config);
++	struct memac_regs __iomem *regs = mac_dev->fman_mac->regs;
++	u32 tmp = ioread32be(&regs->if_mode);
++
++	tmp &= ~(IF_MODE_MASK | IF_MODE_RGMII);
++	tmp |= memac_if_mode(state->interface);
++	if (phylink_autoneg_inband(mode))
++		tmp |= IF_MODE_RGMII_AUTO;
++	iowrite32be(tmp, &regs->if_mode);
++}
++
++static void memac_link_up(struct phylink_config *config, struct phy_device *phy,
++			  unsigned int mode, phy_interface_t interface,
++			  int speed, int duplex, bool tx_pause, bool rx_pause)
++{
++	struct mac_device *mac_dev = fman_config_to_mac(config);
++	struct fman_mac *memac = mac_dev->fman_mac;
++	struct memac_regs __iomem *regs = memac->regs;
++	u32 tmp = memac_if_mode(interface);
++	u16 pause_time = tx_pause ? FSL_FM_PAUSE_TIME_ENABLE :
++			 FSL_FM_PAUSE_TIME_DISABLE;
++
++	memac_set_tx_pause_frames(memac, 0, pause_time, 0);
++	memac_accept_rx_pause_frames(memac, rx_pause);
++
++	if (duplex == DUPLEX_HALF)
++		tmp |= IF_MODE_HD;
++
++	switch (speed) {
++	case SPEED_1000:
++		tmp |= IF_MODE_RGMII_1000;
++		break;
++	case SPEED_100:
++		tmp |= IF_MODE_RGMII_100;
++		break;
++	case SPEED_10:
++		tmp |= IF_MODE_RGMII_10;
++		break;
++	}
++	iowrite32be(tmp, &regs->if_mode);
++
++	/* TODO: EEE? */
++
++	if (speed == SPEED_10000) {
++		if (memac->fm_rev_info.major == 6 &&
++		    memac->fm_rev_info.minor == 4)
++			tmp = TX_FIFO_SECTIONS_TX_AVAIL_SLOW_10G;
++		else
++			tmp = TX_FIFO_SECTIONS_TX_AVAIL_10G;
++		tmp |= TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G;
++	} else {
++		tmp = TX_FIFO_SECTIONS_TX_AVAIL_1G |
++		      TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G;
++	}
++	iowrite32be(tmp, &regs->tx_fifo_sections);
++
++	mac_dev->update_speed(mac_dev, speed);
++
++	tmp = ioread32be(&regs->command_config);
++	tmp |= CMD_CFG_RX_EN | CMD_CFG_TX_EN;
++	iowrite32be(tmp, &regs->command_config);
++}
++
++static void memac_link_down(struct phylink_config *config, unsigned int mode,
++			    phy_interface_t interface)
++{
++	struct fman_mac *memac = fman_config_to_mac(config)->fman_mac;
++	struct memac_regs __iomem *regs = memac->regs;
++	u32 tmp;
++
++	/* TODO: graceful */
++	tmp = ioread32be(&regs->command_config);
++	tmp &= ~(CMD_CFG_RX_EN | CMD_CFG_TX_EN);
++	iowrite32be(tmp, &regs->command_config);
++}
++
++static const struct phylink_mac_ops memac_mac_ops = {
++	.validate = memac_validate,
++	.mac_select_pcs = memac_select_pcs,
++	.mac_prepare = memac_prepare,
++	.mac_config = memac_mac_config,
++	.mac_link_up = memac_link_up,
++	.mac_link_down = memac_link_down,
++};
++
+ static int memac_modify_mac_address(struct fman_mac *memac,
+ 				    const enet_addr_t *enet_addr)
+ {
+-	if (!is_init_done(memac->memac_drv_param))
+-		return -EINVAL;
+-
+ 	add_addr_in_paddr(memac->regs, (const u8 *)(*enet_addr), 0);
+ 
+ 	return 0;
+@@ -771,9 +800,6 @@ static int memac_add_hash_mac_address(st
+ 	u32 hash;
+ 	u64 addr;
+ 
+-	if (!is_init_done(memac->memac_drv_param))
+-		return -EINVAL;
+-
+ 	addr = ENET_ADDR_TO_UINT64(*eth_addr);
+ 
+ 	if (!(addr & GROUP_ADDRESS)) {
+@@ -802,9 +828,6 @@ static int memac_set_allmulti(struct fma
+ 	u32 entry;
+ 	struct memac_regs __iomem *regs = memac->regs;
+ 
+-	if (!is_init_done(memac->memac_drv_param))
+-		return -EINVAL;
+-
+ 	if (enable) {
+ 		for (entry = 0; entry < HASH_TABLE_SIZE; entry++)
+ 			iowrite32be(entry | HASH_CTRL_MCAST_EN,
+@@ -834,9 +857,6 @@ static int memac_del_hash_mac_address(st
+ 	u32 hash;
+ 	u64 addr;
+ 
+-	if (!is_init_done(memac->memac_drv_param))
+-		return -EINVAL;
+-
+ 	addr = ENET_ADDR_TO_UINT64(*eth_addr);
+ 
+ 	hash = get_mac_addr_hash_code(addr) & HASH_CTRL_ADDR_MASK;
+@@ -864,9 +884,6 @@ static int memac_set_exception(struct fm
+ {
+ 	u32 bit_mask = 0;
+ 
+-	if (!is_init_done(memac->memac_drv_param))
+-		return -EINVAL;
+-
+ 	bit_mask = get_exception_flag(exception);
+ 	if (bit_mask) {
+ 		if (enable)
+@@ -886,23 +903,15 @@ static int memac_init(struct fman_mac *m
+ {
+ 	struct memac_cfg *memac_drv_param;
+ 	enet_addr_t eth_addr;
+-	bool slow_10g_if = false;
+-	struct fixed_phy_status *fixed_link = NULL;
+ 	int err;
+ 	u32 reg32 = 0;
+ 
+-	if (is_init_done(memac->memac_drv_param))
+-		return -EINVAL;
+-
+ 	err = check_init_parameters(memac);
+ 	if (err)
+ 		return err;
+ 
+ 	memac_drv_param = memac->memac_drv_param;
+ 
+-	if (memac->fm_rev_info.major == 6 && memac->fm_rev_info.minor == 4)
+-		slow_10g_if = true;
+-
+ 	/* First, reset the MAC if desired. */
+ 	if (memac_drv_param->reset_on_init) {
+ 		err = reset(memac->regs);
+@@ -918,10 +927,7 @@ static int memac_init(struct fman_mac *m
+ 		add_addr_in_paddr(memac->regs, (const u8 *)eth_addr, 0);
+ 	}
+ 
+-	fixed_link = memac_drv_param->fixed_link;
+-
+-	init(memac->regs, memac->memac_drv_param, memac->phy_if,
+-	     memac->max_speed, slow_10g_if, memac->exceptions);
++	init(memac->regs, memac->memac_drv_param, memac->exceptions);
+ 
+ 	/* FM_RX_FIFO_CORRUPT_ERRATA_10GMAC_A006320 errata workaround
+ 	 * Exists only in FMan 6.0 and 6.3.
+@@ -937,11 +943,6 @@ static int memac_init(struct fman_mac *m
+ 		iowrite32be(reg32, &memac->regs->command_config);
+ 	}
+ 
+-	if (memac->phy_if == PHY_INTERFACE_MODE_SGMII)
+-		setup_sgmii_internal(memac, memac->sgmii_pcs, fixed_link);
+-	else if (memac->phy_if == PHY_INTERFACE_MODE_QSGMII)
+-		setup_sgmii_internal(memac, memac->qsgmii_pcs, fixed_link);
+-
+ 	/* Max Frame Length */
+ 	err = fman_set_mac_max_frame(memac->fm, memac->mac_id,
+ 				     memac_drv_param->max_frame_length);
+@@ -970,9 +971,6 @@ static int memac_init(struct fman_mac *m
+ 	fman_register_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id,
+ 			   FMAN_INTR_TYPE_NORMAL, memac_exception, memac);
+ 
+-	kfree(memac_drv_param);
+-	memac->memac_drv_param = NULL;
+-
+ 	return 0;
+ }
+ 
+@@ -995,7 +993,6 @@ static int memac_free(struct fman_mac *m
+ 	pcs_put(memac->sgmii_pcs);
+ 	pcs_put(memac->qsgmii_pcs);
+ 	pcs_put(memac->xfi_pcs);
+-
+ 	kfree(memac->memac_drv_param);
+ 	kfree(memac);
+ 
+@@ -1028,8 +1025,6 @@ static struct fman_mac *memac_config(str
+ 	memac->addr = ENET_ADDR_TO_UINT64(mac_dev->addr);
+ 
+ 	memac->regs = mac_dev->vaddr;
+-	memac->max_speed = params->max_speed;
+-	memac->phy_if = mac_dev->phy_if;
+ 	memac->mac_id = params->mac_id;
+ 	memac->exceptions = (MEMAC_IMASK_TSECC_ER | MEMAC_IMASK_TECC_ER |
+ 			     MEMAC_IMASK_RECC_ER | MEMAC_IMASK_MGI);
+@@ -1037,7 +1032,6 @@ static struct fman_mac *memac_config(str
+ 	memac->event_cb = params->event_cb;
+ 	memac->dev_id = mac_dev;
+ 	memac->fm = params->fm;
+-	memac->basex_if = params->basex_if;
+ 
+ 	/* Save FMan revision */
+ 	fman_get_revision(memac->fm, &memac->fm_rev_info);
+@@ -1064,37 +1058,44 @@ static struct phylink_pcs *memac_pcs_cre
+ 	return pcs;
+ }
+ 
++static bool memac_supports(struct mac_device *mac_dev, phy_interface_t iface)
++{
++	/* If there's no serdes device, assume that it's been configured for
++	 * whatever the default interface mode is.
++	 */
++	if (!mac_dev->fman_mac->serdes)
++		return mac_dev->phy_if == iface;
++	/* Otherwise, ask the serdes */
++	return !phy_validate(mac_dev->fman_mac->serdes, PHY_MODE_ETHERNET,
++			     iface, NULL);
++}
++
+ int memac_initialization(struct mac_device *mac_dev,
+ 			 struct device_node *mac_node,
+ 			 struct fman_mac_params *params)
+ {
+ 	int			 err;
++	struct device_node      *fixed;
+ 	struct phylink_pcs	*pcs;
+-	struct fixed_phy_status *fixed_link;
+ 	struct fman_mac		*memac;
++	unsigned long		 capabilities;
++	unsigned long		*supported;
+ 
++	mac_dev->phylink_ops		= &memac_mac_ops;
+ 	mac_dev->set_promisc		= memac_set_promiscuous;
+ 	mac_dev->change_addr		= memac_modify_mac_address;
+ 	mac_dev->add_hash_mac_addr	= memac_add_hash_mac_address;
+ 	mac_dev->remove_hash_mac_addr	= memac_del_hash_mac_address;
+-	mac_dev->set_tx_pause		= memac_set_tx_pause_frames;
+-	mac_dev->set_rx_pause		= memac_accept_rx_pause_frames;
+ 	mac_dev->set_exception		= memac_set_exception;
+ 	mac_dev->set_allmulti		= memac_set_allmulti;
+ 	mac_dev->set_tstamp		= memac_set_tstamp;
+ 	mac_dev->set_multi		= fman_set_multi;
+-	mac_dev->adjust_link            = adjust_link_memac;
+ 	mac_dev->enable			= memac_enable;
+ 	mac_dev->disable		= memac_disable;
+ 
+-	if (params->max_speed == SPEED_10000)
+-		mac_dev->phy_if = PHY_INTERFACE_MODE_XGMII;
+-
+ 	mac_dev->fman_mac = memac_config(mac_dev, params);
+-	if (!mac_dev->fman_mac) {
+-		err = -EINVAL;
+-		goto _return;
+-	}
++	if (!mac_dev->fman_mac)
++		return -EINVAL;
+ 
+ 	memac = mac_dev->fman_mac;
+ 	memac->memac_drv_param->max_frame_length = fman_get_max_frm();
+@@ -1136,9 +1137,9 @@ int memac_initialization(struct mac_devi
+ 	else
+ 		pcs = memac_pcs_create(mac_node, err);
+ 
+-	if (!pcs) {
+-		dev_err(mac_dev->dev, "missing pcs\n");
+-		err = -ENOENT;
++	if (IS_ERR(pcs)) {
++		err = PTR_ERR(pcs);
++		dev_err_probe(mac_dev->dev, err, "missing pcs\n");
+ 		goto _return_fm_mac_free;
+ 	}
+ 
+@@ -1159,84 +1160,100 @@ int memac_initialization(struct mac_devi
+ 	} else if (IS_ERR(memac->serdes)) {
+ 		dev_err_probe(mac_dev->dev, err, "could not get serdes\n");
+ 		goto _return_fm_mac_free;
+-	} else {
+-		err = phy_init(memac->serdes);
+-		if (err) {
+-			dev_err_probe(mac_dev->dev, err,
+-				      "could not initialize serdes\n");
+-			goto _return_fm_mac_free;
+-		}
+-
+-		err = phy_power_on(memac->serdes);
+-		if (err) {
+-			dev_err_probe(mac_dev->dev, err,
+-				      "could not power on serdes\n");
+-			goto _return_phy_exit;
+-		}
+-
+-		if (memac->phy_if == PHY_INTERFACE_MODE_SGMII ||
+-		    memac->phy_if == PHY_INTERFACE_MODE_1000BASEX ||
+-		    memac->phy_if == PHY_INTERFACE_MODE_2500BASEX ||
+-		    memac->phy_if == PHY_INTERFACE_MODE_QSGMII ||
+-		    memac->phy_if == PHY_INTERFACE_MODE_XGMII) {
+-			err = phy_set_mode_ext(memac->serdes, PHY_MODE_ETHERNET,
+-					       memac->phy_if);
+-			if (err) {
+-				dev_err_probe(mac_dev->dev, err,
+-					      "could not set serdes mode to %s\n",
+-					      phy_modes(memac->phy_if));
+-				goto _return_phy_power_off;
+-			}
+-		}
+ 	}
+ 
+-	if (!mac_dev->phy_node && of_phy_is_fixed_link(mac_node)) {
+-		struct phy_device *phy;
+-
+-		err = of_phy_register_fixed_link(mac_node);
+-		if (err)
+-			goto _return_phy_power_off;
+-
+-		fixed_link = kzalloc(sizeof(*fixed_link), GFP_KERNEL);
+-		if (!fixed_link) {
+-			err = -ENOMEM;
+-			goto _return_phy_power_off;
+-		}
++	/* The internal connection to the serdes is XGMII, but this isn't
++	 * really correct for the phy mode (which is the external connection).
++	 * However, this is how all older device trees say that they want
++	 * 10GBASE-R (aka XFI), so just convert it for them.
++	 */
++	if (mac_dev->phy_if == PHY_INTERFACE_MODE_XGMII)
++		mac_dev->phy_if = PHY_INTERFACE_MODE_10GBASER;
+ 
+-		mac_dev->phy_node = of_node_get(mac_node);
+-		phy = of_phy_find_device(mac_dev->phy_node);
+-		if (!phy) {
+-			err = -EINVAL;
+-			of_node_put(mac_dev->phy_node);
+-			goto _return_fixed_link_free;
+-		}
++	/* TODO: The following interface modes are supported by (some) hardware
++	 * but not by this driver:
++	 * - 1000BASE-KX
++	 * - 10GBASE-KR
++	 * - XAUI/HiGig
++	 */
++	supported = mac_dev->phylink_config.supported_interfaces;
+ 
+-		fixed_link->link = phy->link;
+-		fixed_link->speed = phy->speed;
+-		fixed_link->duplex = phy->duplex;
+-		fixed_link->pause = phy->pause;
+-		fixed_link->asym_pause = phy->asym_pause;
++	/* Note that half duplex is only supported on 10/100M interfaces. */
+ 
+-		put_device(&phy->mdio.dev);
+-		memac->memac_drv_param->fixed_link = fixed_link;
++	if (memac->sgmii_pcs &&
++	    (memac_supports(mac_dev, PHY_INTERFACE_MODE_SGMII) ||
++	     memac_supports(mac_dev, PHY_INTERFACE_MODE_1000BASEX))) {
++		__set_bit(PHY_INTERFACE_MODE_SGMII, supported);
++		__set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
++	}
++
++	if (memac->sgmii_pcs &&
++	    memac_supports(mac_dev, PHY_INTERFACE_MODE_2500BASEX))
++		__set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
++
++	if (memac->qsgmii_pcs &&
++	    memac_supports(mac_dev, PHY_INTERFACE_MODE_QSGMII))
++		__set_bit(PHY_INTERFACE_MODE_QSGMII, supported);
++	else if (mac_dev->phy_if == PHY_INTERFACE_MODE_QSGMII)
++		dev_warn(mac_dev->dev, "no QSGMII pcs specified\n");
++
++	if (memac->xfi_pcs &&
++	    memac_supports(mac_dev, PHY_INTERFACE_MODE_10GBASER)) {
++		__set_bit(PHY_INTERFACE_MODE_10GBASER, supported);
++	} else {
++		/* From what I can tell, no 10g macs support RGMII. */
++		phy_interface_set_rgmii(supported);
++		__set_bit(PHY_INTERFACE_MODE_MII, supported);
+ 	}
+ 
++	capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE | MAC_10 | MAC_100;
++	capabilities |= MAC_1000FD | MAC_2500FD | MAC_10000FD;
++
++	/* These SoCs don't support half duplex at all; there's no different
++	 * FMan version or compatible, so we just have to check the machine
++	 * compatible instead
++	 */
++	if (of_machine_is_compatible("fsl,ls1043a") ||
++	    of_machine_is_compatible("fsl,ls1046a") ||
++	    of_machine_is_compatible("fsl,B4QDS"))
++		capabilities &= ~(MAC_10HD | MAC_100HD);
++
++	mac_dev->phylink_config.mac_capabilities = capabilities;
++
++	/* The T2080 and T4240 don't support half duplex RGMII. There is no
++	 * other way to identify these SoCs, so just use the machine
++	 * compatible.
++	 */
++	if (of_machine_is_compatible("fsl,T2080QDS") ||
++	    of_machine_is_compatible("fsl,T2080RDB") ||
++	    of_machine_is_compatible("fsl,T2081QDS") ||
++	    of_machine_is_compatible("fsl,T4240QDS") ||
++	    of_machine_is_compatible("fsl,T4240RDB"))
++		memac->rgmii_no_half_duplex = true;
++
++	/* Most boards should use MLO_AN_INBAND, but existing boards don't have
++	 * a managed property. Default to MLO_AN_INBAND if nothing else is
++	 * specified. We need to be careful and not enable this if we have a
++	 * fixed link or if we are using MII or RGMII, since those
++	 * configurations modes don't use in-band autonegotiation.
++	 */
++	fixed = of_get_child_by_name(mac_node, "fixed-link");
++	if (!fixed && !of_property_read_bool(mac_node, "fixed-link") &&
++	    !of_property_read_bool(mac_node, "managed") &&
++	    mac_dev->phy_if != PHY_INTERFACE_MODE_MII &&
++	    !phy_interface_mode_is_rgmii(mac_dev->phy_if))
++		mac_dev->phylink_config.ovr_an_inband = true;
++	of_node_put(fixed);
++
+ 	err = memac_init(mac_dev->fman_mac);
+ 	if (err < 0)
+-		goto _return_fixed_link_free;
++		goto _return_fm_mac_free;
+ 
+ 	dev_info(mac_dev->dev, "FMan MEMAC\n");
+ 
+-	goto _return;
++	return 0;
+ 
+-_return_phy_power_off:
+-	phy_power_off(memac->serdes);
+-_return_phy_exit:
+-	phy_exit(memac->serdes);
+-_return_fixed_link_free:
+-	kfree(fixed_link);
+ _return_fm_mac_free:
+ 	memac_free(mac_dev->fman_mac);
+-_return:
+ 	return err;
+ }
+--- a/drivers/net/ethernet/freescale/fman/fman_tgec.c
++++ b/drivers/net/ethernet/freescale/fman/fman_tgec.c
+@@ -13,6 +13,7 @@
+ #include <linux/bitrev.h>
+ #include <linux/io.h>
+ #include <linux/crc32.h>
++#include <linux/netdevice.h>
+ 
+ /* Transmit Inter-Packet Gap Length Register (TX_IPG_LENGTH) */
+ #define TGEC_TX_IPG_LENGTH_MASK	0x000003ff
+@@ -243,10 +244,6 @@ static int init(struct tgec_regs __iomem
+ 
+ static int check_init_parameters(struct fman_mac *tgec)
+ {
+-	if (tgec->max_speed < SPEED_10000) {
+-		pr_err("10G MAC driver only support 10G speed\n");
+-		return -EINVAL;
+-	}
+ 	if (!tgec->exception_cb) {
+ 		pr_err("uninitialized exception_cb\n");
+ 		return -EINVAL;
+@@ -384,40 +381,13 @@ static void free_init_resources(struct f
+ 	tgec->unicast_addr_hash = NULL;
+ }
+ 
+-static bool is_init_done(struct tgec_cfg *cfg)
+-{
+-	/* Checks if tGEC driver parameters were initialized */
+-	if (!cfg)
+-		return true;
+-
+-	return false;
+-}
+-
+ static int tgec_enable(struct fman_mac *tgec)
+ {
+-	struct tgec_regs __iomem *regs = tgec->regs;
+-	u32 tmp;
+-
+-	if (!is_init_done(tgec->cfg))
+-		return -EINVAL;
+-
+-	tmp = ioread32be(&regs->command_config);
+-	tmp |= CMD_CFG_RX_EN | CMD_CFG_TX_EN;
+-	iowrite32be(tmp, &regs->command_config);
+-
+ 	return 0;
+ }
+ 
+ static void tgec_disable(struct fman_mac *tgec)
+ {
+-	struct tgec_regs __iomem *regs = tgec->regs;
+-	u32 tmp;
+-
+-	WARN_ON_ONCE(!is_init_done(tgec->cfg));
+-
+-	tmp = ioread32be(&regs->command_config);
+-	tmp &= ~(CMD_CFG_RX_EN | CMD_CFG_TX_EN);
+-	iowrite32be(tmp, &regs->command_config);
+ }
+ 
+ static int tgec_set_promiscuous(struct fman_mac *tgec, bool new_val)
+@@ -425,9 +395,6 @@ static int tgec_set_promiscuous(struct f
+ 	struct tgec_regs __iomem *regs = tgec->regs;
+ 	u32 tmp;
+ 
+-	if (!is_init_done(tgec->cfg))
+-		return -EINVAL;
+-
+ 	tmp = ioread32be(&regs->command_config);
+ 	if (new_val)
+ 		tmp |= CMD_CFG_PROMIS_EN;
+@@ -444,9 +411,6 @@ static int tgec_set_tx_pause_frames(stru
+ {
+ 	struct tgec_regs __iomem *regs = tgec->regs;
+ 
+-	if (!is_init_done(tgec->cfg))
+-		return -EINVAL;
+-
+ 	iowrite32be((u32)pause_time, &regs->pause_quant);
+ 
+ 	return 0;
+@@ -457,9 +421,6 @@ static int tgec_accept_rx_pause_frames(s
+ 	struct tgec_regs __iomem *regs = tgec->regs;
+ 	u32 tmp;
+ 
+-	if (!is_init_done(tgec->cfg))
+-		return -EINVAL;
+-
+ 	tmp = ioread32be(&regs->command_config);
+ 	if (!en)
+ 		tmp |= CMD_CFG_PAUSE_IGNORE;
+@@ -470,12 +431,53 @@ static int tgec_accept_rx_pause_frames(s
+ 	return 0;
+ }
+ 
++static void tgec_mac_config(struct phylink_config *config, unsigned int mode,
++			    const struct phylink_link_state *state)
++{
++}
++
++static void tgec_link_up(struct phylink_config *config, struct phy_device *phy,
++			 unsigned int mode, phy_interface_t interface,
++			 int speed, int duplex, bool tx_pause, bool rx_pause)
++{
++	struct mac_device *mac_dev = fman_config_to_mac(config);
++	struct fman_mac *tgec = mac_dev->fman_mac;
++	struct tgec_regs __iomem *regs = tgec->regs;
++	u16 pause_time = tx_pause ? FSL_FM_PAUSE_TIME_ENABLE :
++			 FSL_FM_PAUSE_TIME_DISABLE;
++	u32 tmp;
++
++	tgec_set_tx_pause_frames(tgec, 0, pause_time, 0);
++	tgec_accept_rx_pause_frames(tgec, rx_pause);
++	mac_dev->update_speed(mac_dev, speed);
++
++	tmp = ioread32be(&regs->command_config);
++	tmp |= CMD_CFG_RX_EN | CMD_CFG_TX_EN;
++	iowrite32be(tmp, &regs->command_config);
++}
++
++static void tgec_link_down(struct phylink_config *config, unsigned int mode,
++			   phy_interface_t interface)
++{
++	struct fman_mac *tgec = fman_config_to_mac(config)->fman_mac;
++	struct tgec_regs __iomem *regs = tgec->regs;
++	u32 tmp;
++
++	tmp = ioread32be(&regs->command_config);
++	tmp &= ~(CMD_CFG_RX_EN | CMD_CFG_TX_EN);
++	iowrite32be(tmp, &regs->command_config);
++}
++
++static const struct phylink_mac_ops tgec_mac_ops = {
++	.validate = phylink_generic_validate,
++	.mac_config = tgec_mac_config,
++	.mac_link_up = tgec_link_up,
++	.mac_link_down = tgec_link_down,
++};
++
+ static int tgec_modify_mac_address(struct fman_mac *tgec,
+ 				   const enet_addr_t *p_enet_addr)
+ {
+-	if (!is_init_done(tgec->cfg))
+-		return -EINVAL;
+-
+ 	tgec->addr = ENET_ADDR_TO_UINT64(*p_enet_addr);
+ 	set_mac_address(tgec->regs, (const u8 *)(*p_enet_addr));
+ 
+@@ -490,9 +492,6 @@ static int tgec_add_hash_mac_address(str
+ 	u32 crc = 0xFFFFFFFF, hash;
+ 	u64 addr;
+ 
+-	if (!is_init_done(tgec->cfg))
+-		return -EINVAL;
+-
+ 	addr = ENET_ADDR_TO_UINT64(*eth_addr);
+ 
+ 	if (!(addr & GROUP_ADDRESS)) {
+@@ -525,9 +524,6 @@ static int tgec_set_allmulti(struct fman
+ 	u32 entry;
+ 	struct tgec_regs __iomem *regs = tgec->regs;
+ 
+-	if (!is_init_done(tgec->cfg))
+-		return -EINVAL;
+-
+ 	if (enable) {
+ 		for (entry = 0; entry < TGEC_HASH_TABLE_SIZE; entry++)
+ 			iowrite32be(entry | TGEC_HASH_MCAST_EN,
+@@ -548,9 +544,6 @@ static int tgec_set_tstamp(struct fman_m
+ 	struct tgec_regs __iomem *regs = tgec->regs;
+ 	u32 tmp;
+ 
+-	if (!is_init_done(tgec->cfg))
+-		return -EINVAL;
+-
+ 	tmp = ioread32be(&regs->command_config);
+ 
+ 	if (enable)
+@@ -572,9 +565,6 @@ static int tgec_del_hash_mac_address(str
+ 	u32 crc = 0xFFFFFFFF, hash;
+ 	u64 addr;
+ 
+-	if (!is_init_done(tgec->cfg))
+-		return -EINVAL;
+-
+ 	addr = ((*(u64 *)eth_addr) >> 16);
+ 
+ 	/* CRC calculation */
+@@ -601,22 +591,12 @@ static int tgec_del_hash_mac_address(str
+ 	return 0;
+ }
+ 
+-static void tgec_adjust_link(struct mac_device *mac_dev)
+-{
+-	struct phy_device *phy_dev = mac_dev->phy_dev;
+-
+-	mac_dev->update_speed(mac_dev, phy_dev->speed);
+-}
+-
+ static int tgec_set_exception(struct fman_mac *tgec,
+ 			      enum fman_mac_exceptions exception, bool enable)
+ {
+ 	struct tgec_regs __iomem *regs = tgec->regs;
+ 	u32 bit_mask = 0;
+ 
+-	if (!is_init_done(tgec->cfg))
+-		return -EINVAL;
+-
+ 	bit_mask = get_exception_flag(exception);
+ 	if (bit_mask) {
+ 		if (enable)
+@@ -641,9 +621,6 @@ static int tgec_init(struct fman_mac *tg
+ 	enet_addr_t eth_addr;
+ 	int err;
+ 
+-	if (is_init_done(tgec->cfg))
+-		return -EINVAL;
+-
+ 	if (DEFAULT_RESET_ON_INIT &&
+ 	    (fman_reset_mac(tgec->fm, tgec->mac_id) != 0)) {
+ 		pr_err("Can't reset MAC!\n");
+@@ -753,7 +730,6 @@ static struct fman_mac *tgec_config(stru
+ 
+ 	tgec->regs = mac_dev->vaddr;
+ 	tgec->addr = ENET_ADDR_TO_UINT64(mac_dev->addr);
+-	tgec->max_speed = params->max_speed;
+ 	tgec->mac_id = params->mac_id;
+ 	tgec->exceptions = (TGEC_IMASK_MDIO_SCAN_EVENT	|
+ 			    TGEC_IMASK_REM_FAULT	|
+@@ -788,17 +764,15 @@ int tgec_initialization(struct mac_devic
+ 	int err;
+ 	struct fman_mac		*tgec;
+ 
++	mac_dev->phylink_ops		= &tgec_mac_ops;
+ 	mac_dev->set_promisc		= tgec_set_promiscuous;
+ 	mac_dev->change_addr		= tgec_modify_mac_address;
+ 	mac_dev->add_hash_mac_addr	= tgec_add_hash_mac_address;
+ 	mac_dev->remove_hash_mac_addr	= tgec_del_hash_mac_address;
+-	mac_dev->set_tx_pause		= tgec_set_tx_pause_frames;
+-	mac_dev->set_rx_pause		= tgec_accept_rx_pause_frames;
+ 	mac_dev->set_exception		= tgec_set_exception;
+ 	mac_dev->set_allmulti		= tgec_set_allmulti;
+ 	mac_dev->set_tstamp		= tgec_set_tstamp;
+ 	mac_dev->set_multi		= fman_set_multi;
+-	mac_dev->adjust_link            = tgec_adjust_link;
+ 	mac_dev->enable			= tgec_enable;
+ 	mac_dev->disable		= tgec_disable;
+ 
+@@ -808,6 +782,19 @@ int tgec_initialization(struct mac_devic
+ 		goto _return;
+ 	}
+ 
++	/* The internal connection to the serdes is XGMII, but this isn't
++	 * really correct for the phy mode (which is the external connection).
++	 * However, this is how all older device trees say that they want
++	 * XAUI, so just convert it for them.
++	 */
++	if (mac_dev->phy_if == PHY_INTERFACE_MODE_XGMII)
++		mac_dev->phy_if = PHY_INTERFACE_MODE_XAUI;
++
++	__set_bit(PHY_INTERFACE_MODE_XAUI,
++		  mac_dev->phylink_config.supported_interfaces);
++	mac_dev->phylink_config.mac_capabilities =
++		MAC_SYM_PAUSE | MAC_ASYM_PAUSE | MAC_10000FD;
++
+ 	tgec = mac_dev->fman_mac;
+ 	tgec->cfg->max_frame_length = fman_get_max_frm();
+ 	err = tgec_init(tgec);
+--- a/drivers/net/ethernet/freescale/fman/mac.c
++++ b/drivers/net/ethernet/freescale/fman/mac.c
+@@ -15,6 +15,7 @@
+ #include <linux/phy.h>
+ #include <linux/netdevice.h>
+ #include <linux/phy_fixed.h>
++#include <linux/phylink.h>
+ #include <linux/etherdevice.h>
+ #include <linux/libfdt_env.h>
+ 
+@@ -93,130 +94,8 @@ int fman_set_multi(struct net_device *ne
+ 	return 0;
+ }
+ 
+-/**
+- * fman_set_mac_active_pause
+- * @mac_dev:	A pointer to the MAC device
+- * @rx:		Pause frame setting for RX
+- * @tx:		Pause frame setting for TX
+- *
+- * Set the MAC RX/TX PAUSE frames settings
+- *
+- * Avoid redundant calls to FMD, if the MAC driver already contains the desired
+- * active PAUSE settings. Otherwise, the new active settings should be reflected
+- * in FMan.
+- *
+- * Return: 0 on success; Error code otherwise.
+- */
+-int fman_set_mac_active_pause(struct mac_device *mac_dev, bool rx, bool tx)
+-{
+-	struct fman_mac *fman_mac = mac_dev->fman_mac;
+-	int err = 0;
+-
+-	if (rx != mac_dev->rx_pause_active) {
+-		err = mac_dev->set_rx_pause(fman_mac, rx);
+-		if (likely(err == 0))
+-			mac_dev->rx_pause_active = rx;
+-	}
+-
+-	if (tx != mac_dev->tx_pause_active) {
+-		u16 pause_time = (tx ? FSL_FM_PAUSE_TIME_ENABLE :
+-					 FSL_FM_PAUSE_TIME_DISABLE);
+-
+-		err = mac_dev->set_tx_pause(fman_mac, 0, pause_time, 0);
+-
+-		if (likely(err == 0))
+-			mac_dev->tx_pause_active = tx;
+-	}
+-
+-	return err;
+-}
+-EXPORT_SYMBOL(fman_set_mac_active_pause);
+-
+-/**
+- * fman_get_pause_cfg
+- * @mac_dev:	A pointer to the MAC device
+- * @rx_pause:	Return value for RX setting
+- * @tx_pause:	Return value for TX setting
+- *
+- * Determine the MAC RX/TX PAUSE frames settings based on PHY
+- * autonegotiation or values set by eththool.
+- *
+- * Return: Pointer to FMan device.
+- */
+-void fman_get_pause_cfg(struct mac_device *mac_dev, bool *rx_pause,
+-			bool *tx_pause)
+-{
+-	struct phy_device *phy_dev = mac_dev->phy_dev;
+-	u16 lcl_adv, rmt_adv;
+-	u8 flowctrl;
+-
+-	*rx_pause = *tx_pause = false;
+-
+-	if (!phy_dev->duplex)
+-		return;
+-
+-	/* If PAUSE autonegotiation is disabled, the TX/RX PAUSE settings
+-	 * are those set by ethtool.
+-	 */
+-	if (!mac_dev->autoneg_pause) {
+-		*rx_pause = mac_dev->rx_pause_req;
+-		*tx_pause = mac_dev->tx_pause_req;
+-		return;
+-	}
+-
+-	/* Else if PAUSE autonegotiation is enabled, the TX/RX PAUSE
+-	 * settings depend on the result of the link negotiation.
+-	 */
+-
+-	/* get local capabilities */
+-	lcl_adv = linkmode_adv_to_lcl_adv_t(phy_dev->advertising);
+-
+-	/* get link partner capabilities */
+-	rmt_adv = 0;
+-	if (phy_dev->pause)
+-		rmt_adv |= LPA_PAUSE_CAP;
+-	if (phy_dev->asym_pause)
+-		rmt_adv |= LPA_PAUSE_ASYM;
+-
+-	/* Calculate TX/RX settings based on local and peer advertised
+-	 * symmetric/asymmetric PAUSE capabilities.
+-	 */
+-	flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
+-	if (flowctrl & FLOW_CTRL_RX)
+-		*rx_pause = true;
+-	if (flowctrl & FLOW_CTRL_TX)
+-		*tx_pause = true;
+-}
+-EXPORT_SYMBOL(fman_get_pause_cfg);
+-
+-#define DTSEC_SUPPORTED \
+-	(SUPPORTED_10baseT_Half \
+-	| SUPPORTED_10baseT_Full \
+-	| SUPPORTED_100baseT_Half \
+-	| SUPPORTED_100baseT_Full \
+-	| SUPPORTED_Autoneg \
+-	| SUPPORTED_Pause \
+-	| SUPPORTED_Asym_Pause \
+-	| SUPPORTED_FIBRE \
+-	| SUPPORTED_MII)
+-
+ static DEFINE_MUTEX(eth_lock);
+ 
+-static const u16 phy2speed[] = {
+-	[PHY_INTERFACE_MODE_MII]		= SPEED_100,
+-	[PHY_INTERFACE_MODE_GMII]		= SPEED_1000,
+-	[PHY_INTERFACE_MODE_SGMII]		= SPEED_1000,
+-	[PHY_INTERFACE_MODE_TBI]		= SPEED_1000,
+-	[PHY_INTERFACE_MODE_RMII]		= SPEED_100,
+-	[PHY_INTERFACE_MODE_RGMII]		= SPEED_1000,
+-	[PHY_INTERFACE_MODE_RGMII_ID]		= SPEED_1000,
+-	[PHY_INTERFACE_MODE_RGMII_RXID]	= SPEED_1000,
+-	[PHY_INTERFACE_MODE_RGMII_TXID]	= SPEED_1000,
+-	[PHY_INTERFACE_MODE_RTBI]		= SPEED_1000,
+-	[PHY_INTERFACE_MODE_QSGMII]		= SPEED_1000,
+-	[PHY_INTERFACE_MODE_XGMII]		= SPEED_10000
+-};
+-
+ static struct platform_device *dpaa_eth_add_device(int fman_id,
+ 						   struct mac_device *mac_dev)
+ {
+@@ -263,8 +142,8 @@ no_mem:
+ }
+ 
+ static const struct of_device_id mac_match[] = {
+-	{ .compatible	= "fsl,fman-dtsec", .data = dtsec_initialization },
+-	{ .compatible	= "fsl,fman-xgec", .data = tgec_initialization },
++	{ .compatible   = "fsl,fman-dtsec", .data = dtsec_initialization },
++	{ .compatible   = "fsl,fman-xgec", .data = tgec_initialization },
+ 	{ .compatible	= "fsl,fman-memac", .data = memac_initialization },
+ 	{}
+ };
+@@ -295,6 +174,7 @@ static int mac_probe(struct platform_dev
+ 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ 	if (!priv)
+ 		return -ENOMEM;
++	platform_set_drvdata(_of_dev, mac_dev);
+ 
+ 	/* Save private information */
+ 	mac_dev->priv = priv;
+@@ -424,57 +304,21 @@ static int mac_probe(struct platform_dev
+ 	}
+ 	mac_dev->phy_if = phy_if;
+ 
+-	priv->speed		= phy2speed[mac_dev->phy_if];
+-	params.max_speed	= priv->speed;
+-	mac_dev->if_support	= DTSEC_SUPPORTED;
+-	/* We don't support half-duplex in SGMII mode */
+-	if (mac_dev->phy_if == PHY_INTERFACE_MODE_SGMII)
+-		mac_dev->if_support &= ~(SUPPORTED_10baseT_Half |
+-					SUPPORTED_100baseT_Half);
+-
+-	/* Gigabit support (no half-duplex) */
+-	if (params.max_speed == 1000)
+-		mac_dev->if_support |= SUPPORTED_1000baseT_Full;
+-
+-	/* The 10G interface only supports one mode */
+-	if (mac_dev->phy_if == PHY_INTERFACE_MODE_XGMII)
+-		mac_dev->if_support = SUPPORTED_10000baseT_Full;
+-
+-	/* Get the rest of the PHY information */
+-	mac_dev->phy_node = of_parse_phandle(mac_node, "phy-handle", 0);
+-
+-	params.basex_if		= false;
+ 	params.mac_id		= priv->cell_index;
+ 	params.fm		= (void *)priv->fman;
+ 	params.exception_cb	= mac_exception;
+ 	params.event_cb		= mac_exception;
+ 
+ 	err = init(mac_dev, mac_node, &params);
+-	if (err < 0) {
+-		dev_err(dev, "mac_dev->init() = %d\n", err);
+-		of_node_put(mac_dev->phy_node);
+-		return err;
+-	}
+-
+-	/* pause frame autonegotiation enabled */
+-	mac_dev->autoneg_pause = true;
+-
+-	/* By intializing the values to false, force FMD to enable PAUSE frames
+-	 * on RX and TX
+-	 */
+-	mac_dev->rx_pause_req = true;
+-	mac_dev->tx_pause_req = true;
+-	mac_dev->rx_pause_active = false;
+-	mac_dev->tx_pause_active = false;
+-	err = fman_set_mac_active_pause(mac_dev, true, true);
+ 	if (err < 0)
+-		dev_err(dev, "fman_set_mac_active_pause() = %d\n", err);
++		return err;
+ 
+ 	if (!is_zero_ether_addr(mac_dev->addr))
+ 		dev_info(dev, "FMan MAC address: %pM\n", mac_dev->addr);
+ 
+ 	priv->eth_dev = dpaa_eth_add_device(fman_id, mac_dev);
+ 	if (IS_ERR(priv->eth_dev)) {
++		err = PTR_ERR(priv->eth_dev);
+ 		dev_err(dev, "failed to add Ethernet platform device for MAC %d\n",
+ 			priv->cell_index);
+ 		priv->eth_dev = NULL;
+--- a/drivers/net/ethernet/freescale/fman/mac.h
++++ b/drivers/net/ethernet/freescale/fman/mac.h
+@@ -9,6 +9,7 @@
+ #include <linux/device.h>
+ #include <linux/if_ether.h>
+ #include <linux/phy.h>
++#include <linux/phylink.h>
+ #include <linux/list.h>
+ 
+ #include "fman_port.h"
+@@ -24,32 +25,22 @@ struct mac_device {
+ 	struct resource		*res;
+ 	u8			 addr[ETH_ALEN];
+ 	struct fman_port	*port[2];
+-	u32			 if_support;
+-	struct phy_device	*phy_dev;
++	struct phylink		*phylink;
++	struct phylink_config	phylink_config;
+ 	phy_interface_t		phy_if;
+-	struct device_node	*phy_node;
+-	struct net_device	*net_dev;
+ 
+-	bool autoneg_pause;
+-	bool rx_pause_req;
+-	bool tx_pause_req;
+-	bool rx_pause_active;
+-	bool tx_pause_active;
+ 	bool promisc;
+ 	bool allmulti;
+ 
++	const struct phylink_mac_ops *phylink_ops;
+ 	int (*enable)(struct fman_mac *mac_dev);
+ 	void (*disable)(struct fman_mac *mac_dev);
+-	void (*adjust_link)(struct mac_device *mac_dev);
+ 	int (*set_promisc)(struct fman_mac *mac_dev, bool enable);
+ 	int (*change_addr)(struct fman_mac *mac_dev, const enet_addr_t *enet_addr);
+ 	int (*set_allmulti)(struct fman_mac *mac_dev, bool enable);
+ 	int (*set_tstamp)(struct fman_mac *mac_dev, bool enable);
+ 	int (*set_multi)(struct net_device *net_dev,
+ 			 struct mac_device *mac_dev);
+-	int (*set_rx_pause)(struct fman_mac *mac_dev, bool en);
+-	int (*set_tx_pause)(struct fman_mac *mac_dev, u8 priority,
+-			    u16 pause_time, u16 thresh_time);
+ 	int (*set_exception)(struct fman_mac *mac_dev,
+ 			     enum fman_mac_exceptions exception, bool enable);
+ 	int (*add_hash_mac_addr)(struct fman_mac *mac_dev,
+@@ -63,6 +54,12 @@ struct mac_device {
+ 	struct mac_priv_s	*priv;
+ };
+ 
++static inline struct mac_device
++*fman_config_to_mac(struct phylink_config *config)
++{
++	return container_of(config, struct mac_device, phylink_config);
++}
++
+ struct dpaa_eth_data {
+ 	struct mac_device *mac_dev;
+ 	int mac_hw_id;
diff --git a/target/linux/generic/backport-6.1/715-04-v6.2-net-phylink-provide-phylink_validate_mask_caps-helpe.patch b/target/linux/generic/backport-6.1/715-04-v6.2-net-phylink-provide-phylink_validate_mask_caps-helpe.patch
new file mode 100644
index 00000000000000..06c348b1cdfa78
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-04-v6.2-net-phylink-provide-phylink_validate_mask_caps-helpe.patch
@@ -0,0 +1,93 @@
+From bf4de031052fe7c5309e8956c342d4e5ce79038e Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Mon, 17 Oct 2022 16:22:35 -0400
+Subject: [PATCH 04/21] net: phylink: provide phylink_validate_mask_caps()
+ helper
+
+Provide a helper that restricts the link modes according to the
+phylink capabilities.
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+[rebased on net-next/master and added documentation]
+Signed-off-by: Sean Anderson <sean.anderson@seco.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/phylink.c | 41 +++++++++++++++++++++++++++------------
+ include/linux/phylink.h   |  3 +++
+ 2 files changed, 32 insertions(+), 12 deletions(-)
+
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -564,31 +564,48 @@ unsigned long phylink_get_capabilities(p
+ EXPORT_SYMBOL_GPL(phylink_get_capabilities);
+ 
+ /**
+- * phylink_generic_validate() - generic validate() callback implementation
+- * @config: a pointer to a &struct phylink_config.
++ * phylink_validate_mask_caps() - Restrict link modes based on caps
+  * @supported: ethtool bitmask for supported link modes.
+- * @state: a pointer to a &struct phylink_link_state.
++ * @state: an (optional) pointer to a &struct phylink_link_state.
++ * @mac_capabilities: bitmask of MAC capabilities
+  *
+- * Generic implementation of the validate() callback that MAC drivers can
+- * use when they pass the range of supported interfaces and MAC capabilities.
+- * This makes use of phylink_get_linkmodes().
++ * Calculate the supported link modes based on @mac_capabilities, and restrict
++ * @supported and @state based on that. Use this function if your capabiliies
++ * aren't constant, such as if they vary depending on the interface.
+  */
+-void phylink_generic_validate(struct phylink_config *config,
+-			      unsigned long *supported,
+-			      struct phylink_link_state *state)
++void phylink_validate_mask_caps(unsigned long *supported,
++				struct phylink_link_state *state,
++				unsigned long mac_capabilities)
+ {
+ 	__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
+ 	unsigned long caps;
+ 
+ 	phylink_set_port_modes(mask);
+ 	phylink_set(mask, Autoneg);
+-	caps = phylink_get_capabilities(state->interface,
+-					config->mac_capabilities,
++	caps = phylink_get_capabilities(state->interface, mac_capabilities,
+ 					state->rate_matching);
+ 	phylink_caps_to_linkmodes(mask, caps);
+ 
+ 	linkmode_and(supported, supported, mask);
+-	linkmode_and(state->advertising, state->advertising, mask);
++	if (state)
++		linkmode_and(state->advertising, state->advertising, mask);
++}
++EXPORT_SYMBOL_GPL(phylink_validate_mask_caps);
++
++/**
++ * phylink_generic_validate() - generic validate() callback implementation
++ * @config: a pointer to a &struct phylink_config.
++ * @supported: ethtool bitmask for supported link modes.
++ * @state: a pointer to a &struct phylink_link_state.
++ *
++ * Generic implementation of the validate() callback that MAC drivers can
++ * use when they pass the range of supported interfaces and MAC capabilities.
++ */
++void phylink_generic_validate(struct phylink_config *config,
++			      unsigned long *supported,
++			      struct phylink_link_state *state)
++{
++	phylink_validate_mask_caps(supported, state, config->mac_capabilities);
+ }
+ EXPORT_SYMBOL_GPL(phylink_generic_validate);
+ 
+--- a/include/linux/phylink.h
++++ b/include/linux/phylink.h
+@@ -558,6 +558,9 @@ void phylink_caps_to_linkmodes(unsigned
+ unsigned long phylink_get_capabilities(phy_interface_t interface,
+ 				       unsigned long mac_capabilities,
+ 				       int rate_matching);
++void phylink_validate_mask_caps(unsigned long *supported,
++				struct phylink_link_state *state,
++				unsigned long caps);
+ void phylink_generic_validate(struct phylink_config *config,
+ 			      unsigned long *supported,
+ 			      struct phylink_link_state *state);
diff --git a/target/linux/generic/backport-6.1/715-05-v6.2-phylink-require-valid-state-argument-to-phylink_vali.patch b/target/linux/generic/backport-6.1/715-05-v6.2-phylink-require-valid-state-argument-to-phylink_vali.patch
new file mode 100644
index 00000000000000..e3a1dda688ab5f
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-05-v6.2-phylink-require-valid-state-argument-to-phylink_vali.patch
@@ -0,0 +1,39 @@
+From 2bf7e4a68c42eed909f3c29582e1fb85cb157e35 Mon Sep 17 00:00:00 2001
+From: Jakub Kicinski <kuba@kernel.org>
+Date: Tue, 25 Oct 2022 11:51:26 -0700
+Subject: [PATCH 05/21] phylink: require valid state argument to
+ phylink_validate_mask_caps()
+
+state is deferenced earlier in the function, the NULL check
+is pointless. Since we don't have any crash reports presumably
+it's safe to assume state is not NULL.
+
+Fixes: f392a1846489 ("net: phylink: provide phylink_validate_mask_caps() helper")
+Reviewed-by: Sean Anderson <sean.anderson@seco.com>
+Link: https://lore.kernel.org/r/20221025185126.1720553-1-kuba@kernel.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/phylink.c | 5 ++---
+ 1 file changed, 2 insertions(+), 3 deletions(-)
+
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -566,7 +566,7 @@ EXPORT_SYMBOL_GPL(phylink_get_capabiliti
+ /**
+  * phylink_validate_mask_caps() - Restrict link modes based on caps
+  * @supported: ethtool bitmask for supported link modes.
+- * @state: an (optional) pointer to a &struct phylink_link_state.
++ * @state: pointer to a &struct phylink_link_state.
+  * @mac_capabilities: bitmask of MAC capabilities
+  *
+  * Calculate the supported link modes based on @mac_capabilities, and restrict
+@@ -587,8 +587,7 @@ void phylink_validate_mask_caps(unsigned
+ 	phylink_caps_to_linkmodes(mask, caps);
+ 
+ 	linkmode_and(supported, supported, mask);
+-	if (state)
+-		linkmode_and(state->advertising, state->advertising, mask);
++	linkmode_and(state->advertising, state->advertising, mask);
+ }
+ EXPORT_SYMBOL_GPL(phylink_validate_mask_caps);
+ 
diff --git a/target/linux/generic/backport-6.1/715-06-v6.2-net-phylink-add-phylink_get_link_timer_ns-helper.patch b/target/linux/generic/backport-6.1/715-06-v6.2-net-phylink-add-phylink_get_link_timer_ns-helper.patch
new file mode 100644
index 00000000000000..c217ed87b51d6f
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-06-v6.2-net-phylink-add-phylink_get_link_timer_ns-helper.patch
@@ -0,0 +1,48 @@
+From f8fc363bf0c023e4736a0328174b4a24b44ab23a Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Thu, 27 Oct 2022 14:10:37 +0100
+Subject: [PATCH 06/21] net: phylink: add phylink_get_link_timer_ns() helper
+
+Add a helper to convert the PHY interface mode to the required link
+timer setting as stated by the appropriate standard. Inappropriate
+interface modes return an error.
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ include/linux/phylink.h | 24 ++++++++++++++++++++++++
+ 1 file changed, 24 insertions(+)
+
+--- a/include/linux/phylink.h
++++ b/include/linux/phylink.h
+@@ -617,6 +617,30 @@ int phylink_speed_up(struct phylink *pl)
+ 
+ void phylink_set_port_modes(unsigned long *bits);
+ 
++/**
++ * phylink_get_link_timer_ns - return the PCS link timer value
++ * @interface: link &typedef phy_interface_t mode
++ *
++ * Return the PCS link timer setting in nanoseconds for the PHY @interface
++ * mode, or -EINVAL if not appropriate.
++ */
++static inline int phylink_get_link_timer_ns(phy_interface_t interface)
++{
++	switch (interface) {
++	case PHY_INTERFACE_MODE_SGMII:
++	case PHY_INTERFACE_MODE_QSGMII:
++	case PHY_INTERFACE_MODE_USXGMII:
++		return 1600000;
++
++	case PHY_INTERFACE_MODE_1000BASEX:
++	case PHY_INTERFACE_MODE_2500BASEX:
++		return 10000000;
++
++	default:
++		return -EINVAL;
++	}
++}
++
+ void phylink_mii_c22_pcs_decode_state(struct phylink_link_state *state,
+ 				      u16 bmsr, u16 lpa);
+ void phylink_mii_c22_pcs_get_state(struct mdio_device *pcs,
diff --git a/target/linux/generic/backport-6.1/715-07-v6.2-net-remove-explicit-phylink_generic_validate-referen.patch b/target/linux/generic/backport-6.1/715-07-v6.2-net-remove-explicit-phylink_generic_validate-referen.patch
new file mode 100644
index 00000000000000..28154af920c5a7
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-07-v6.2-net-remove-explicit-phylink_generic_validate-referen.patch
@@ -0,0 +1,250 @@
+From b45b773a96b0e9e8d51e5d005485f4e376d6ce9a Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Fri, 4 Nov 2022 17:13:01 +0000
+Subject: [PATCH 07/21] net: remove explicit phylink_generic_validate()
+ references
+
+Virtually all conventional network drivers are now converted to use
+phylink_generic_validate() - only DSA drivers and fman_memac remain,
+so lets remove the necessity for network drivers to explicitly set
+this member, and default to phylink_generic_validate() when unset.
+This is possible as .validate must currently be set.
+
+Any remaining instances that have not been addressed by this patch can
+be fixed up later.
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
+Link: https://lore.kernel.org/r/E1or0FZ-001tRa-DI@rmk-PC.armlinux.org.uk
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/ethernet/altera/altera_tse_main.c            | 1 -
+ drivers/net/ethernet/atheros/ag71xx.c                    | 1 -
+ drivers/net/ethernet/cadence/macb_main.c                 | 1 -
+ drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c         | 1 -
+ drivers/net/ethernet/freescale/enetc/enetc_pf.c          | 1 -
+ drivers/net/ethernet/freescale/fman/fman_dtsec.c         | 1 -
+ drivers/net/ethernet/freescale/fman/fman_tgec.c          | 1 -
+ drivers/net/ethernet/marvell/mvneta.c                    | 1 -
+ drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c          | 1 -
+ drivers/net/ethernet/marvell/prestera/prestera_main.c    | 1 -
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c              | 1 -
+ drivers/net/ethernet/microchip/lan966x/lan966x_phylink.c | 1 -
+ drivers/net/ethernet/microchip/sparx5/sparx5_phylink.c   | 1 -
+ drivers/net/ethernet/mscc/ocelot_net.c                   | 1 -
+ drivers/net/ethernet/stmicro/stmmac/stmmac_main.c        | 1 -
+ drivers/net/ethernet/ti/am65-cpsw-nuss.c                 | 1 -
+ drivers/net/ethernet/xilinx/xilinx_axienet_main.c        | 1 -
+ drivers/net/phy/phylink.c                                | 5 ++++-
+ drivers/net/usb/asix_devices.c                           | 1 -
+ include/linux/phylink.h                                  | 5 +++++
+ 20 files changed, 9 insertions(+), 19 deletions(-)
+
+--- a/drivers/net/ethernet/altera/altera_tse_main.c
++++ b/drivers/net/ethernet/altera/altera_tse_main.c
+@@ -1096,7 +1096,6 @@ static struct phylink_pcs *alt_tse_selec
+ }
+ 
+ static const struct phylink_mac_ops alt_tse_phylink_ops = {
+-	.validate = phylink_generic_validate,
+ 	.mac_an_restart = alt_tse_mac_an_restart,
+ 	.mac_config = alt_tse_mac_config,
+ 	.mac_link_down = alt_tse_mac_link_down,
+--- a/drivers/net/ethernet/atheros/ag71xx.c
++++ b/drivers/net/ethernet/atheros/ag71xx.c
+@@ -1086,7 +1086,6 @@ static void ag71xx_mac_link_up(struct ph
+ }
+ 
+ static const struct phylink_mac_ops ag71xx_phylink_mac_ops = {
+-	.validate = phylink_generic_validate,
+ 	.mac_config = ag71xx_mac_config,
+ 	.mac_link_down = ag71xx_mac_link_down,
+ 	.mac_link_up = ag71xx_mac_link_up,
+--- a/drivers/net/ethernet/cadence/macb_main.c
++++ b/drivers/net/ethernet/cadence/macb_main.c
+@@ -752,7 +752,6 @@ static struct phylink_pcs *macb_mac_sele
+ }
+ 
+ static const struct phylink_mac_ops macb_phylink_ops = {
+-	.validate = phylink_generic_validate,
+ 	.mac_select_pcs = macb_mac_select_pcs,
+ 	.mac_config = macb_mac_config,
+ 	.mac_link_down = macb_mac_link_down,
+--- a/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c
++++ b/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c
+@@ -235,7 +235,6 @@ static void dpaa2_mac_link_down(struct p
+ }
+ 
+ static const struct phylink_mac_ops dpaa2_mac_phylink_ops = {
+-	.validate = phylink_generic_validate,
+ 	.mac_select_pcs = dpaa2_mac_select_pcs,
+ 	.mac_config = dpaa2_mac_config,
+ 	.mac_link_up = dpaa2_mac_link_up,
+--- a/drivers/net/ethernet/freescale/enetc/enetc_pf.c
++++ b/drivers/net/ethernet/freescale/enetc/enetc_pf.c
+@@ -1111,7 +1111,6 @@ static void enetc_pl_mac_link_down(struc
+ }
+ 
+ static const struct phylink_mac_ops enetc_mac_phylink_ops = {
+-	.validate = phylink_generic_validate,
+ 	.mac_select_pcs = enetc_pl_mac_select_pcs,
+ 	.mac_config = enetc_pl_mac_config,
+ 	.mac_link_up = enetc_pl_mac_link_up,
+--- a/drivers/net/ethernet/freescale/fman/fman_dtsec.c
++++ b/drivers/net/ethernet/freescale/fman/fman_dtsec.c
+@@ -986,7 +986,6 @@ static void dtsec_link_down(struct phyli
+ }
+ 
+ static const struct phylink_mac_ops dtsec_mac_ops = {
+-	.validate = phylink_generic_validate,
+ 	.mac_select_pcs = dtsec_select_pcs,
+ 	.mac_config = dtsec_mac_config,
+ 	.mac_link_up = dtsec_link_up,
+--- a/drivers/net/ethernet/freescale/fman/fman_tgec.c
++++ b/drivers/net/ethernet/freescale/fman/fman_tgec.c
+@@ -469,7 +469,6 @@ static void tgec_link_down(struct phylin
+ }
+ 
+ static const struct phylink_mac_ops tgec_mac_ops = {
+-	.validate = phylink_generic_validate,
+ 	.mac_config = tgec_mac_config,
+ 	.mac_link_up = tgec_link_up,
+ 	.mac_link_down = tgec_link_down,
+--- a/drivers/net/ethernet/marvell/mvneta.c
++++ b/drivers/net/ethernet/marvell/mvneta.c
+@@ -4228,7 +4228,6 @@ static void mvneta_mac_link_up(struct ph
+ }
+ 
+ static const struct phylink_mac_ops mvneta_phylink_ops = {
+-	.validate = phylink_generic_validate,
+ 	.mac_select_pcs = mvneta_mac_select_pcs,
+ 	.mac_prepare = mvneta_mac_prepare,
+ 	.mac_config = mvneta_mac_config,
+--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
++++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+@@ -6633,7 +6633,6 @@ static void mvpp2_mac_link_down(struct p
+ }
+ 
+ static const struct phylink_mac_ops mvpp2_phylink_ops = {
+-	.validate = phylink_generic_validate,
+ 	.mac_select_pcs = mvpp2_select_pcs,
+ 	.mac_prepare = mvpp2_mac_prepare,
+ 	.mac_config = mvpp2_mac_config,
+--- a/drivers/net/ethernet/marvell/prestera/prestera_main.c
++++ b/drivers/net/ethernet/marvell/prestera/prestera_main.c
+@@ -360,7 +360,6 @@ static void prestera_pcs_an_restart(stru
+ }
+ 
+ static const struct phylink_mac_ops prestera_mac_ops = {
+-	.validate = phylink_generic_validate,
+ 	.mac_select_pcs = prestera_mac_select_pcs,
+ 	.mac_config = prestera_mac_config,
+ 	.mac_link_down = prestera_mac_link_down,
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -654,7 +654,6 @@ static void mtk_mac_link_up(struct phyli
+ }
+ 
+ static const struct phylink_mac_ops mtk_phylink_ops = {
+-	.validate = phylink_generic_validate,
+ 	.mac_select_pcs = mtk_mac_select_pcs,
+ 	.mac_pcs_get_state = mtk_mac_pcs_get_state,
+ 	.mac_config = mtk_mac_config,
+--- a/drivers/net/ethernet/microchip/lan966x/lan966x_phylink.c
++++ b/drivers/net/ethernet/microchip/lan966x/lan966x_phylink.c
+@@ -125,7 +125,6 @@ static void lan966x_pcs_aneg_restart(str
+ }
+ 
+ const struct phylink_mac_ops lan966x_phylink_mac_ops = {
+-	.validate = phylink_generic_validate,
+ 	.mac_select_pcs = lan966x_phylink_mac_select,
+ 	.mac_config = lan966x_phylink_mac_config,
+ 	.mac_prepare = lan966x_phylink_mac_prepare,
+--- a/drivers/net/ethernet/microchip/sparx5/sparx5_phylink.c
++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_phylink.c
+@@ -138,7 +138,6 @@ const struct phylink_pcs_ops sparx5_phyl
+ };
+ 
+ const struct phylink_mac_ops sparx5_phylink_mac_ops = {
+-	.validate = phylink_generic_validate,
+ 	.mac_select_pcs = sparx5_phylink_mac_select_pcs,
+ 	.mac_config = sparx5_phylink_mac_config,
+ 	.mac_link_down = sparx5_phylink_mac_link_down,
+--- a/drivers/net/ethernet/mscc/ocelot_net.c
++++ b/drivers/net/ethernet/mscc/ocelot_net.c
+@@ -1737,7 +1737,6 @@ static void vsc7514_phylink_mac_link_up(
+ }
+ 
+ static const struct phylink_mac_ops ocelot_phylink_ops = {
+-	.validate		= phylink_generic_validate,
+ 	.mac_config		= vsc7514_phylink_mac_config,
+ 	.mac_link_down		= vsc7514_phylink_mac_link_down,
+ 	.mac_link_up		= vsc7514_phylink_mac_link_up,
+--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
++++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+@@ -1090,7 +1090,6 @@ static void stmmac_mac_link_up(struct ph
+ }
+ 
+ static const struct phylink_mac_ops stmmac_phylink_mac_ops = {
+-	.validate = phylink_generic_validate,
+ 	.mac_select_pcs = stmmac_mac_select_pcs,
+ 	.mac_config = stmmac_mac_config,
+ 	.mac_link_down = stmmac_mac_link_down,
+--- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c
++++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c
+@@ -1493,7 +1493,6 @@ static void am65_cpsw_nuss_mac_link_up(s
+ }
+ 
+ static const struct phylink_mac_ops am65_cpsw_phylink_mac_ops = {
+-	.validate = phylink_generic_validate,
+ 	.mac_config = am65_cpsw_nuss_mac_config,
+ 	.mac_link_down = am65_cpsw_nuss_mac_link_down,
+ 	.mac_link_up = am65_cpsw_nuss_mac_link_up,
+--- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
++++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
+@@ -1736,7 +1736,6 @@ static void axienet_mac_link_up(struct p
+ }
+ 
+ static const struct phylink_mac_ops axienet_phylink_ops = {
+-	.validate = phylink_generic_validate,
+ 	.mac_select_pcs = axienet_mac_select_pcs,
+ 	.mac_config = axienet_mac_config,
+ 	.mac_link_down = axienet_mac_link_down,
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -651,7 +651,10 @@ static int phylink_validate_mac_and_pcs(
+ 	}
+ 
+ 	/* Then validate the link parameters with the MAC */
+-	pl->mac_ops->validate(pl->config, supported, state);
++	if (pl->mac_ops->validate)
++		pl->mac_ops->validate(pl->config, supported, state);
++	else
++		phylink_generic_validate(pl->config, supported, state);
+ 
+ 	return phylink_is_empty_linkmode(supported) ? -EINVAL : 0;
+ }
+--- a/drivers/net/usb/asix_devices.c
++++ b/drivers/net/usb/asix_devices.c
+@@ -787,7 +787,6 @@ static void ax88772_mac_link_up(struct p
+ }
+ 
+ static const struct phylink_mac_ops ax88772_phylink_mac_ops = {
+-	.validate = phylink_generic_validate,
+ 	.mac_config = ax88772_mac_config,
+ 	.mac_link_down = ax88772_mac_link_down,
+ 	.mac_link_up = ax88772_mac_link_up,
+--- a/include/linux/phylink.h
++++ b/include/linux/phylink.h
+@@ -207,6 +207,11 @@ struct phylink_mac_ops {
+  *
+  * If the @state->interface mode is not supported, then the @supported
+  * mask must be cleared.
++ *
++ * This member is optional; if not set, the generic validator will be
++ * used making use of @config->mac_capabilities and
++ * @config->supported_interfaces to determine which link modes are
++ * supported.
+  */
+ void validate(struct phylink_config *config, unsigned long *supported,
+ 	      struct phylink_link_state *state);
diff --git a/target/linux/generic/backport-6.1/715-08-net-sfp-make-sfp_bus_find_fwnode-take-a-const-fwnode.patch b/target/linux/generic/backport-6.1/715-08-net-sfp-make-sfp_bus_find_fwnode-take-a-const-fwnode.patch
new file mode 100644
index 00000000000000..37d82b2cd7db93
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-08-net-sfp-make-sfp_bus_find_fwnode-take-a-const-fwnode.patch
@@ -0,0 +1,48 @@
+From a90ac762d345890b40d88a1385a34a2449c2d75e Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Fri, 24 Mar 2023 09:23:42 +0000
+Subject: [PATCH] net: sfp: make sfp_bus_find_fwnode() take a const fwnode
+
+sfp_bus_find_fwnode() does not write to the fwnode, so let's make it
+const.
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Simon Horman <simon.horman@corigine.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/sfp-bus.c | 2 +-
+ include/linux/sfp.h       | 5 +++--
+ 2 files changed, 4 insertions(+), 3 deletions(-)
+
+--- a/drivers/net/phy/sfp-bus.c
++++ b/drivers/net/phy/sfp-bus.c
+@@ -603,7 +603,7 @@ static void sfp_upstream_clear(struct sf
+  *	- %-ENOMEM if we failed to allocate the bus.
+  *	- an error from the upstream's connect_phy() method.
+  */
+-struct sfp_bus *sfp_bus_find_fwnode(struct fwnode_handle *fwnode)
++struct sfp_bus *sfp_bus_find_fwnode(const struct fwnode_handle *fwnode)
+ {
+ 	struct fwnode_reference_args ref;
+ 	struct sfp_bus *bus;
+--- a/include/linux/sfp.h
++++ b/include/linux/sfp.h
+@@ -548,7 +548,7 @@ int sfp_get_module_eeprom_by_page(struct
+ void sfp_upstream_start(struct sfp_bus *bus);
+ void sfp_upstream_stop(struct sfp_bus *bus);
+ void sfp_bus_put(struct sfp_bus *bus);
+-struct sfp_bus *sfp_bus_find_fwnode(struct fwnode_handle *fwnode);
++struct sfp_bus *sfp_bus_find_fwnode(const struct fwnode_handle *fwnode);
+ int sfp_bus_add_upstream(struct sfp_bus *bus, void *upstream,
+ 			 const struct sfp_upstream_ops *ops);
+ void sfp_bus_del_upstream(struct sfp_bus *bus);
+@@ -610,7 +610,8 @@ static inline void sfp_bus_put(struct sf
+ {
+ }
+ 
+-static inline struct sfp_bus *sfp_bus_find_fwnode(struct fwnode_handle *fwnode)
++static inline struct sfp_bus *
++sfp_bus_find_fwnode(const struct fwnode_handle *fwnode)
+ {
+ 	return NULL;
+ }
diff --git a/target/linux/generic/backport-6.1/715-09-v6.4-net-pcs-lynx-don-t-print-an_enabled-in-pcs_get_state.patch b/target/linux/generic/backport-6.1/715-09-v6.4-net-pcs-lynx-don-t-print-an_enabled-in-pcs_get_state.patch
new file mode 100644
index 00000000000000..290cb8d161d632
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-09-v6.4-net-pcs-lynx-don-t-print-an_enabled-in-pcs_get_state.patch
@@ -0,0 +1,31 @@
+From ecec0ebbc6381a5a375f1cf10c4858f24e91e2ef Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Wed, 15 Mar 2023 14:46:49 +0000
+Subject: [PATCH] net: pcs: lynx: don't print an_enabled in pcs_get_state()
+
+an_enabled will be going away, and in any case, pcs_get_state() should
+not be updating this member. Remove the print.
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/pcs/pcs-lynx.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/pcs/pcs-lynx.c
++++ b/drivers/net/pcs/pcs-lynx.c
+@@ -115,11 +115,11 @@ static void lynx_pcs_get_state(struct ph
+ 	}
+ 
+ 	dev_dbg(&lynx->mdio->dev,
+-		"mode=%s/%s/%s link=%u an_enabled=%u an_complete=%u\n",
++		"mode=%s/%s/%s link=%u an_complete=%u\n",
+ 		phy_modes(state->interface),
+ 		phy_speed_to_str(state->speed),
+ 		phy_duplex_to_str(state->duplex),
+-		state->link, state->an_enabled, state->an_complete);
++		state->link, state->an_complete);
+ }
+ 
+ static int lynx_pcs_config_giga(struct mdio_device *pcs, unsigned int mode,
diff --git a/target/linux/generic/backport-6.1/715-10-v6.4-net-dpaa2-mac-use-Autoneg-bit-rather-than-an_enabled.patch b/target/linux/generic/backport-6.1/715-10-v6.4-net-dpaa2-mac-use-Autoneg-bit-rather-than-an_enabled.patch
new file mode 100644
index 00000000000000..38ea2654760798
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-10-v6.4-net-dpaa2-mac-use-Autoneg-bit-rather-than-an_enabled.patch
@@ -0,0 +1,32 @@
+From 99d0f3a1095f4c938b1665025c29411edafe8a01 Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Tue, 21 Mar 2023 15:58:44 +0000
+Subject: [PATCH] net: dpaa2-mac: use Autoneg bit rather than an_enabled
+
+The Autoneg bit in the advertising bitmap and state->an_enabled are
+always identical. Thus, we will be removing state->an_enabled.
+
+Use the Autoneg bit in the advertising bitmap to indicate whether
+autonegotiation should be used, rather than using the an_enabled
+member which will be going away. This means we use the same condition
+as phylink_mii_c22_pcs_config().
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Simon Horman <simon.horman@corigine.com>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c
++++ b/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c
+@@ -158,7 +158,8 @@ static void dpaa2_mac_config(struct phyl
+ 	struct dpmac_link_state *dpmac_state = &mac->state;
+ 	int err;
+ 
+-	if (state->an_enabled)
++	if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
++			      state->advertising))
+ 		dpmac_state->options |= DPMAC_LINK_OPT_AUTONEG;
+ 	else
+ 		dpmac_state->options &= ~DPMAC_LINK_OPT_AUTONEG;
diff --git a/target/linux/generic/backport-6.1/715-11-v6.4-net-phylink-support-validated-pause-and-autoneg-in-f.patch b/target/linux/generic/backport-6.1/715-11-v6.4-net-phylink-support-validated-pause-and-autoneg-in-f.patch
new file mode 100644
index 00000000000000..cb9c411cfb0d35
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-11-v6.4-net-phylink-support-validated-pause-and-autoneg-in-f.patch
@@ -0,0 +1,64 @@
+From 471c40bde606ec0b1ce8c616f7998739c7a783a6 Mon Sep 17 00:00:00 2001
+From: Ivan Bornyakov <i.bornyakov@metrotek.ru>
+Date: Fri, 10 Feb 2023 18:46:27 +0300
+Subject: [PATCH 10/21] net: phylink: support validated pause and autoneg in
+ fixed-link
+
+In fixed-link setup phylink_parse_fixedlink() unconditionally sets
+Pause, Asym_Pause and Autoneg bits to "supported" bitmap, while MAC may
+not support these.
+
+This leads to ethtool reporting:
+
+ > Supported pause frame use: Symmetric Receive-only
+ > Supports auto-negotiation: Yes
+
+regardless of what is actually supported.
+
+Instead of unconditionally set Pause, Asym_Pause and Autoneg it is
+sensible to set them according to validated "supported" bitmap, i.e. the
+result of phylink_validate().
+
+Signed-off-by: Ivan Bornyakov <i.bornyakov@metrotek.ru>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/phylink.c | 17 ++++++++++++++---
+ 1 file changed, 14 insertions(+), 3 deletions(-)
+
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -709,6 +709,7 @@ static int phylink_parse_fixedlink(struc
+ 				   struct fwnode_handle *fwnode)
+ {
+ 	struct fwnode_handle *fixed_node;
++	bool pause, asym_pause, autoneg;
+ 	const struct phy_setting *s;
+ 	struct gpio_desc *desc;
+ 	u32 speed;
+@@ -781,13 +782,23 @@ static int phylink_parse_fixedlink(struc
+ 	linkmode_copy(pl->link_config.advertising, pl->supported);
+ 	phylink_validate(pl, pl->supported, &pl->link_config);
+ 
++	pause = phylink_test(pl->supported, Pause);
++	asym_pause = phylink_test(pl->supported, Asym_Pause);
++	autoneg = phylink_test(pl->supported, Autoneg);
+ 	s = phy_lookup_setting(pl->link_config.speed, pl->link_config.duplex,
+ 			       pl->supported, true);
+ 	linkmode_zero(pl->supported);
+ 	phylink_set(pl->supported, MII);
+-	phylink_set(pl->supported, Pause);
+-	phylink_set(pl->supported, Asym_Pause);
+-	phylink_set(pl->supported, Autoneg);
++
++	if (pause)
++		phylink_set(pl->supported, Pause);
++
++	if (asym_pause)
++		phylink_set(pl->supported, Asym_Pause);
++
++	if (autoneg)
++		phylink_set(pl->supported, Autoneg);
++
+ 	if (s) {
+ 		__set_bit(s->bit, pl->supported);
+ 		__set_bit(s->bit, pl->link_config.lp_advertising);
diff --git a/target/linux/generic/backport-6.1/715-12-v6.4-net-phylink-remove-an_enabled.patch b/target/linux/generic/backport-6.1/715-12-v6.4-net-phylink-remove-an_enabled.patch
new file mode 100644
index 00000000000000..03b4f9d0c4cc2a
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-12-v6.4-net-phylink-remove-an_enabled.patch
@@ -0,0 +1,177 @@
+From 7211ffd70941933a7825a56cf480f07ee81c321c Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Tue, 21 Mar 2023 15:58:54 +0000
+Subject: [PATCH 11/21] net: phylink: remove an_enabled
+
+The Autoneg bit in the advertising bitmap and state->an_enabled are
+always identical. state->an_enabled is now no longer used by any
+drivers, so lets kill this duplication.
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Simon Horman <simon.horman@corigine.com>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/phylink.c | 37 +++++++++++++++++--------------------
+ include/linux/phylink.h   |  2 --
+ 2 files changed, 17 insertions(+), 22 deletions(-)
+
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -841,7 +841,6 @@ static int phylink_parse_mode(struct phy
+ 		phylink_set(pl->supported, Autoneg);
+ 		phylink_set(pl->supported, Asym_Pause);
+ 		phylink_set(pl->supported, Pause);
+-		pl->link_config.an_enabled = true;
+ 		pl->cfg_link_an_mode = MLO_AN_INBAND;
+ 
+ 		switch (pl->link_config.interface) {
+@@ -944,9 +943,6 @@ static int phylink_parse_mode(struct phy
+ 				    "failed to validate link configuration for in-band status\n");
+ 			return -EINVAL;
+ 		}
+-
+-		/* Check if MAC/PCS also supports Autoneg. */
+-		pl->link_config.an_enabled = phylink_test(pl->supported, Autoneg);
+ 	}
+ 
+ 	return 0;
+@@ -956,7 +952,8 @@ static void phylink_apply_manual_flow(st
+ 				      struct phylink_link_state *state)
+ {
+ 	/* If autoneg is disabled, pause AN is also disabled */
+-	if (!state->an_enabled)
++	if (!linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
++			       state->advertising))
+ 		state->pause &= ~MLO_PAUSE_AN;
+ 
+ 	/* Manual configuration of pause modes */
+@@ -996,21 +993,22 @@ static void phylink_mac_config(struct ph
+ 			       const struct phylink_link_state *state)
+ {
+ 	phylink_dbg(pl,
+-		    "%s: mode=%s/%s/%s/%s/%s adv=%*pb pause=%02x link=%u an=%u\n",
++		    "%s: mode=%s/%s/%s/%s/%s adv=%*pb pause=%02x link=%u\n",
+ 		    __func__, phylink_an_mode_str(pl->cur_link_an_mode),
+ 		    phy_modes(state->interface),
+ 		    phy_speed_to_str(state->speed),
+ 		    phy_duplex_to_str(state->duplex),
+ 		    phy_rate_matching_to_str(state->rate_matching),
+ 		    __ETHTOOL_LINK_MODE_MASK_NBITS, state->advertising,
+-		    state->pause, state->link, state->an_enabled);
++		    state->pause, state->link);
+ 
+ 	pl->mac_ops->mac_config(pl->config, pl->cur_link_an_mode, state);
+ }
+ 
+ static void phylink_mac_pcs_an_restart(struct phylink *pl)
+ {
+-	if (pl->link_config.an_enabled &&
++	if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
++			      pl->link_config.advertising) &&
+ 	    phy_interface_mode_is_8023z(pl->link_config.interface) &&
+ 	    phylink_autoneg_inband(pl->cur_link_an_mode)) {
+ 		if (pl->pcs)
+@@ -1137,9 +1135,9 @@ static void phylink_mac_pcs_get_state(st
+ 	linkmode_copy(state->advertising, pl->link_config.advertising);
+ 	linkmode_zero(state->lp_advertising);
+ 	state->interface = pl->link_config.interface;
+-	state->an_enabled = pl->link_config.an_enabled;
+ 	state->rate_matching = pl->link_config.rate_matching;
+-	if (state->an_enabled) {
++	if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
++			      state->advertising)) {
+ 		state->speed = SPEED_UNKNOWN;
+ 		state->duplex = DUPLEX_UNKNOWN;
+ 		state->pause = MLO_PAUSE_NONE;
+@@ -1531,7 +1529,6 @@ struct phylink *phylink_create(struct ph
+ 	pl->link_config.pause = MLO_PAUSE_AN;
+ 	pl->link_config.speed = SPEED_UNKNOWN;
+ 	pl->link_config.duplex = DUPLEX_UNKNOWN;
+-	pl->link_config.an_enabled = true;
+ 	pl->mac_ops = mac_ops;
+ 	__set_bit(PHYLINK_DISABLE_STOPPED, &pl->phylink_disable_state);
+ 	timer_setup(&pl->link_poll, phylink_fixed_poll, 0);
+@@ -2155,8 +2152,9 @@ static void phylink_get_ksettings(const
+ 		kset->base.speed = state->speed;
+ 		kset->base.duplex = state->duplex;
+ 	}
+-	kset->base.autoneg = state->an_enabled ? AUTONEG_ENABLE :
+-				AUTONEG_DISABLE;
++	kset->base.autoneg = linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
++					       state->advertising) ?
++				AUTONEG_ENABLE : AUTONEG_DISABLE;
+ }
+ 
+ /**
+@@ -2303,9 +2301,8 @@ int phylink_ethtool_ksettings_set(struct
+ 	/* We have ruled out the case with a PHY attached, and the
+ 	 * fixed-link cases.  All that is left are in-band links.
+ 	 */
+-	config.an_enabled = kset->base.autoneg == AUTONEG_ENABLE;
+ 	linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, config.advertising,
+-			 config.an_enabled);
++			 kset->base.autoneg == AUTONEG_ENABLE);
+ 
+ 	/* If this link is with an SFP, ensure that changes to advertised modes
+ 	 * also cause the associated interface to be selected such that the
+@@ -2339,13 +2336,14 @@ int phylink_ethtool_ksettings_set(struct
+ 	}
+ 
+ 	/* If autonegotiation is enabled, we must have an advertisement */
+-	if (config.an_enabled && phylink_is_empty_linkmode(config.advertising))
++	if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
++			      config.advertising) &&
++	    phylink_is_empty_linkmode(config.advertising))
+ 		return -EINVAL;
+ 
+ 	mutex_lock(&pl->state_mutex);
+ 	pl->link_config.speed = config.speed;
+ 	pl->link_config.duplex = config.duplex;
+-	pl->link_config.an_enabled = config.an_enabled;
+ 
+ 	if (pl->link_config.interface != config.interface) {
+ 		/* The interface changed, e.g. 1000base-X <-> 2500base-X */
+@@ -2951,7 +2949,6 @@ static int phylink_sfp_config_phy(struct
+ 	config.speed = SPEED_UNKNOWN;
+ 	config.duplex = DUPLEX_UNKNOWN;
+ 	config.pause = MLO_PAUSE_AN;
+-	config.an_enabled = pl->link_config.an_enabled;
+ 
+ 	/* Ignore errors if we're expecting a PHY to attach later */
+ 	ret = phylink_validate(pl, support, &config);
+@@ -3020,7 +3017,6 @@ static int phylink_sfp_config_optical(st
+ 	config.speed = SPEED_UNKNOWN;
+ 	config.duplex = DUPLEX_UNKNOWN;
+ 	config.pause = MLO_PAUSE_AN;
+-	config.an_enabled = true;
+ 
+ 	/* For all the interfaces that are supported, reduce the sfp_support
+ 	 * mask to only those link modes that can be supported.
+@@ -3354,7 +3350,8 @@ void phylink_mii_c22_pcs_decode_state(st
+ 	/* If there is no link or autonegotiation is disabled, the LP advertisement
+ 	 * data is not meaningful, so don't go any further.
+ 	 */
+-	if (!state->link || !state->an_enabled)
++	if (!state->link || !linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
++					       state->advertising))
+ 		return;
+ 
+ 	switch (state->interface) {
+--- a/include/linux/phylink.h
++++ b/include/linux/phylink.h
+@@ -93,7 +93,6 @@ static inline bool phylink_autoneg_inban
+  *   the medium link mode (@speed and @duplex) and the speed/duplex of the phy
+  *   interface mode (@interface) are different.
+  * @link: true if the link is up.
+- * @an_enabled: true if autonegotiation is enabled/desired.
+  * @an_complete: true if autonegotiation has completed.
+  */
+ struct phylink_link_state {
+@@ -105,7 +104,6 @@ struct phylink_link_state {
+ 	int pause;
+ 	int rate_matching;
+ 	unsigned int link:1;
+-	unsigned int an_enabled:1;
+ 	unsigned int an_complete:1;
+ };
+ 
diff --git a/target/linux/generic/backport-6.1/715-13-v6.5-net-phylink-constify-fwnode-arguments.patch b/target/linux/generic/backport-6.1/715-13-v6.5-net-phylink-constify-fwnode-arguments.patch
new file mode 100644
index 00000000000000..c06a367b8be370
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-13-v6.5-net-phylink-constify-fwnode-arguments.patch
@@ -0,0 +1,88 @@
+From a3555d1f5c208f0a63eafee77381f68d304a0512 Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Fri, 12 May 2023 17:58:37 +0100
+Subject: [PATCH 12/21] net: phylink: constify fwnode arguments
+
+Both phylink_create() and phylink_fwnode_phy_connect() do not modify
+the fwnode argument that they are passed, so lets constify these.
+
+Reviewed-by: Simon Horman <simon.horman@corigine.com>
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/phylink.c | 11 ++++++-----
+ include/linux/phylink.h   |  9 +++++----
+ 2 files changed, 11 insertions(+), 9 deletions(-)
+
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -706,7 +706,7 @@ static int phylink_validate(struct phyli
+ }
+ 
+ static int phylink_parse_fixedlink(struct phylink *pl,
+-				   struct fwnode_handle *fwnode)
++				   const struct fwnode_handle *fwnode)
+ {
+ 	struct fwnode_handle *fixed_node;
+ 	bool pause, asym_pause, autoneg;
+@@ -817,7 +817,8 @@ static int phylink_parse_fixedlink(struc
+ 	return 0;
+ }
+ 
+-static int phylink_parse_mode(struct phylink *pl, struct fwnode_handle *fwnode)
++static int phylink_parse_mode(struct phylink *pl,
++			      const struct fwnode_handle *fwnode)
+ {
+ 	struct fwnode_handle *dn;
+ 	const char *managed;
+@@ -1440,7 +1441,7 @@ static void phylink_fixed_poll(struct ti
+ static const struct sfp_upstream_ops sfp_phylink_ops;
+ 
+ static int phylink_register_sfp(struct phylink *pl,
+-				struct fwnode_handle *fwnode)
++				const struct fwnode_handle *fwnode)
+ {
+ 	struct sfp_bus *bus;
+ 	int ret;
+@@ -1479,7 +1480,7 @@ static int phylink_register_sfp(struct p
+  * must use IS_ERR() to check for errors from this function.
+  */
+ struct phylink *phylink_create(struct phylink_config *config,
+-			       struct fwnode_handle *fwnode,
++			       const struct fwnode_handle *fwnode,
+ 			       phy_interface_t iface,
+ 			       const struct phylink_mac_ops *mac_ops)
+ {
+@@ -1809,7 +1810,7 @@ EXPORT_SYMBOL_GPL(phylink_of_phy_connect
+  * Returns 0 on success or a negative errno.
+  */
+ int phylink_fwnode_phy_connect(struct phylink *pl,
+-			       struct fwnode_handle *fwnode,
++			       const struct fwnode_handle *fwnode,
+ 			       u32 flags)
+ {
+ 	struct fwnode_handle *phy_fwnode;
+--- a/include/linux/phylink.h
++++ b/include/linux/phylink.h
+@@ -568,16 +568,17 @@ void phylink_generic_validate(struct phy
+ 			      unsigned long *supported,
+ 			      struct phylink_link_state *state);
+ 
+-struct phylink *phylink_create(struct phylink_config *, struct fwnode_handle *,
+-			       phy_interface_t iface,
+-			       const struct phylink_mac_ops *mac_ops);
++struct phylink *phylink_create(struct phylink_config *,
++			       const struct fwnode_handle *,
++			       phy_interface_t,
++			       const struct phylink_mac_ops *);
+ void phylink_destroy(struct phylink *);
+ bool phylink_expects_phy(struct phylink *pl);
+ 
+ int phylink_connect_phy(struct phylink *, struct phy_device *);
+ int phylink_of_phy_connect(struct phylink *, struct device_node *, u32 flags);
+ int phylink_fwnode_phy_connect(struct phylink *pl,
+-			       struct fwnode_handle *fwnode,
++			       const struct fwnode_handle *fwnode,
+ 			       u32 flags);
+ void phylink_disconnect_phy(struct phylink *);
+ 
diff --git a/target/linux/generic/backport-6.1/715-14-v6.3-net-phy-constify-fwnode_get_phy_node-fwnode-argument.patch b/target/linux/generic/backport-6.1/715-14-v6.3-net-phy-constify-fwnode_get_phy_node-fwnode-argument.patch
new file mode 100644
index 00000000000000..2649634dc7ba0b
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-14-v6.3-net-phy-constify-fwnode_get_phy_node-fwnode-argument.patch
@@ -0,0 +1,38 @@
+From 4a0faa02d419a6728abef0f1d8a32d8c35ef95e6 Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Fri, 24 Mar 2023 09:23:53 +0000
+Subject: [PATCH] net: phy: constify fwnode_get_phy_node() fwnode argument
+
+fwnode_get_phy_node() does not motify the fwnode structure, so make
+the argument const,
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Simon Horman <simon.horman@corigine.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/phy_device.c | 2 +-
+ include/linux/phy.h          | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/phy/phy_device.c
++++ b/drivers/net/phy/phy_device.c
+@@ -3003,7 +3003,7 @@ EXPORT_SYMBOL_GPL(device_phy_find_device
+  * and "phy-device" are not supported in ACPI. DT supports all the three
+  * named references to the phy node.
+  */
+-struct fwnode_handle *fwnode_get_phy_node(struct fwnode_handle *fwnode)
++struct fwnode_handle *fwnode_get_phy_node(const struct fwnode_handle *fwnode)
+ {
+ 	struct fwnode_handle *phy_node;
+ 
+--- a/include/linux/phy.h
++++ b/include/linux/phy.h
+@@ -1473,7 +1473,7 @@ int fwnode_get_phy_id(struct fwnode_hand
+ struct mdio_device *fwnode_mdio_find_device(struct fwnode_handle *fwnode);
+ struct phy_device *fwnode_phy_find_device(struct fwnode_handle *phy_fwnode);
+ struct phy_device *device_phy_find_device(struct device *dev);
+-struct fwnode_handle *fwnode_get_phy_node(struct fwnode_handle *fwnode);
++struct fwnode_handle *fwnode_get_phy_node(const struct fwnode_handle *fwnode);
+ struct phy_device *get_phy_device(struct mii_bus *bus, int addr, bool is_c45);
+ int phy_device_register(struct phy_device *phy);
+ void phy_device_free(struct phy_device *phydev);
diff --git a/target/linux/generic/backport-6.1/715-15-v6.4-net-phylink-fix-ksettings_set-ethtool-call.patch b/target/linux/generic/backport-6.1/715-15-v6.4-net-phylink-fix-ksettings_set-ethtool-call.patch
new file mode 100644
index 00000000000000..5eba18b0260544
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-15-v6.4-net-phylink-fix-ksettings_set-ethtool-call.patch
@@ -0,0 +1,44 @@
+From cc73de0411f7d3cdd157564a78f7a39058420ff8 Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Sat, 13 May 2023 22:03:45 +0100
+Subject: [PATCH 13/21] net: phylink: fix ksettings_set() ethtool call
+
+While testing a Fiberstore SFP-10G-T module (which uses 10GBASE-R with
+rate adaption) in a Clearfog platform (which can't do that) it was
+found that the PHYs advertisement was not limited according to the
+hosts capabilities when using ethtool to change it.
+
+Fix this by ensuring that we mask the advertisement with the computed
+support mask as the very first thing we do.
+
+Fixes: cbc1bb1e4689 ("net: phylink: simplify phy case for ksettings_set method")
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/phylink.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -2226,6 +2226,10 @@ int phylink_ethtool_ksettings_set(struct
+ 
+ 	ASSERT_RTNL();
+ 
++	/* Mask out unsupported advertisements */
++	linkmode_and(config.advertising, kset->link_modes.advertising,
++		     pl->supported);
++
+ 	if (pl->phydev) {
+ 		/* We can rely on phylib for this update; we also do not need
+ 		 * to update the pl->link_config settings:
+@@ -2250,10 +2254,6 @@ int phylink_ethtool_ksettings_set(struct
+ 
+ 	config = pl->link_config;
+ 
+-	/* Mask out unsupported advertisements */
+-	linkmode_and(config.advertising, kset->link_modes.advertising,
+-		     pl->supported);
+-
+ 	/* FIXME: should we reject autoneg if phy/mac does not support it? */
+ 	switch (kset->base.autoneg) {
+ 	case AUTONEG_DISABLE:
diff --git a/target/linux/generic/backport-6.1/715-16-v6.5-net-sfp-add-support-for-setting-signalling-rate.patch b/target/linux/generic/backport-6.1/715-16-v6.5-net-sfp-add-support-for-setting-signalling-rate.patch
new file mode 100644
index 00000000000000..79de6122b75096
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-16-v6.5-net-sfp-add-support-for-setting-signalling-rate.patch
@@ -0,0 +1,149 @@
+From 0100d1c5789018ba77bf2f4fab3bd91ecece7b3b Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Wed, 17 May 2023 11:38:12 +0100
+Subject: [PATCH 14/21] net: sfp: add support for setting signalling rate
+
+Add support to the SFP layer to allow phylink to set the signalling
+rate for a SFP module. The rate given will be in units of kilo-baud
+(1000 baud).
+
+Reviewed-by: Simon Horman <simon.horman@corigine.com>
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/phylink.c | 24 ++++++++++++++++++++++++
+ drivers/net/phy/sfp-bus.c | 20 ++++++++++++++++++++
+ drivers/net/phy/sfp.c     |  5 +++++
+ drivers/net/phy/sfp.h     |  1 +
+ include/linux/sfp.h       |  6 ++++++
+ 5 files changed, 56 insertions(+)
+
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -156,6 +156,23 @@ static const char *phylink_an_mode_str(u
+ 	return mode < ARRAY_SIZE(modestr) ? modestr[mode] : "unknown";
+ }
+ 
++static unsigned int phylink_interface_signal_rate(phy_interface_t interface)
++{
++	switch (interface) {
++	case PHY_INTERFACE_MODE_SGMII:
++	case PHY_INTERFACE_MODE_1000BASEX: /* 1.25Mbd */
++		return 1250;
++	case PHY_INTERFACE_MODE_2500BASEX: /* 3.125Mbd */
++		return 3125;
++	case PHY_INTERFACE_MODE_5GBASER: /* 5.15625Mbd */
++		return 5156;
++	case PHY_INTERFACE_MODE_10GBASER: /* 10.3125Mbd */
++		return 10313;
++	default:
++		return 0;
++	}
++}
++
+ /**
+  * phylink_interface_max_speed() - get the maximum speed of a phy interface
+  * @interface: phy interface mode defined by &typedef phy_interface_t
+@@ -1024,6 +1041,7 @@ static void phylink_major_config(struct
+ {
+ 	struct phylink_pcs *pcs = NULL;
+ 	bool pcs_changed = false;
++	unsigned int rate_kbd;
+ 	int err;
+ 
+ 	phylink_dbg(pl, "major config %s\n", phy_modes(state->interface));
+@@ -1083,6 +1101,12 @@ static void phylink_major_config(struct
+ 				    ERR_PTR(err));
+ 	}
+ 
++	if (pl->sfp_bus) {
++		rate_kbd = phylink_interface_signal_rate(state->interface);
++		if (rate_kbd)
++			sfp_upstream_set_signal_rate(pl->sfp_bus, rate_kbd);
++	}
++
+ 	phylink_pcs_poll_start(pl);
+ }
+ 
+--- a/drivers/net/phy/sfp-bus.c
++++ b/drivers/net/phy/sfp-bus.c
+@@ -586,6 +586,26 @@ static void sfp_upstream_clear(struct sf
+ }
+ 
+ /**
++ * sfp_upstream_set_signal_rate() - set data signalling rate
++ * @bus: a pointer to the &struct sfp_bus structure for the sfp module
++ * @rate_kbd: signalling rate in units of 1000 baud
++ *
++ * Configure the rate select settings on the SFP module for the signalling
++ * rate (not the same as the data rate).
++ *
++ * Locks that may be held:
++ *  Phylink's state_mutex
++ *  rtnl lock
++ *  SFP's sm_mutex
++ */
++void sfp_upstream_set_signal_rate(struct sfp_bus *bus, unsigned int rate_kbd)
++{
++	if (bus->registered)
++		bus->socket_ops->set_signal_rate(bus->sfp, rate_kbd);
++}
++EXPORT_SYMBOL_GPL(sfp_upstream_set_signal_rate);
++
++/**
+  * sfp_bus_find_fwnode() - parse and locate the SFP bus from fwnode
+  * @fwnode: firmware node for the parent device (MAC or PHY)
+  *
+--- a/drivers/net/phy/sfp.c
++++ b/drivers/net/phy/sfp.c
+@@ -2474,6 +2474,10 @@ static void sfp_stop(struct sfp *sfp)
+ 	sfp_sm_event(sfp, SFP_E_DEV_DOWN);
+ }
+ 
++static void sfp_set_signal_rate(struct sfp *sfp, unsigned int rate_kbd)
++{
++}
++
+ static int sfp_module_info(struct sfp *sfp, struct ethtool_modinfo *modinfo)
+ {
+ 	/* locking... and check module is present */
+@@ -2552,6 +2556,7 @@ static const struct sfp_socket_ops sfp_m
+ 	.detach = sfp_detach,
+ 	.start = sfp_start,
+ 	.stop = sfp_stop,
++	.set_signal_rate = sfp_set_signal_rate,
+ 	.module_info = sfp_module_info,
+ 	.module_eeprom = sfp_module_eeprom,
+ 	.module_eeprom_by_page = sfp_module_eeprom_by_page,
+--- a/drivers/net/phy/sfp.h
++++ b/drivers/net/phy/sfp.h
+@@ -19,6 +19,7 @@ struct sfp_socket_ops {
+ 	void (*detach)(struct sfp *sfp);
+ 	void (*start)(struct sfp *sfp);
+ 	void (*stop)(struct sfp *sfp);
++	void (*set_signal_rate)(struct sfp *sfp, unsigned int rate_kbd);
+ 	int (*module_info)(struct sfp *sfp, struct ethtool_modinfo *modinfo);
+ 	int (*module_eeprom)(struct sfp *sfp, struct ethtool_eeprom *ee,
+ 			     u8 *data);
+--- a/include/linux/sfp.h
++++ b/include/linux/sfp.h
+@@ -547,6 +547,7 @@ int sfp_get_module_eeprom_by_page(struct
+ 				  struct netlink_ext_ack *extack);
+ void sfp_upstream_start(struct sfp_bus *bus);
+ void sfp_upstream_stop(struct sfp_bus *bus);
++void sfp_upstream_set_signal_rate(struct sfp_bus *bus, unsigned int rate_kbd);
+ void sfp_bus_put(struct sfp_bus *bus);
+ struct sfp_bus *sfp_bus_find_fwnode(const struct fwnode_handle *fwnode);
+ int sfp_bus_add_upstream(struct sfp_bus *bus, void *upstream,
+@@ -606,6 +607,11 @@ static inline void sfp_upstream_stop(str
+ {
+ }
+ 
++static inline void sfp_upstream_set_signal_rate(struct sfp_bus *bus,
++						unsigned int rate_kbd)
++{
++}
++
+ static inline void sfp_bus_put(struct sfp_bus *bus)
+ {
+ }
diff --git a/target/linux/generic/backport-6.1/715-17-v6.5-net-phy-add-helpers-for-comparing-phy-IDs.patch b/target/linux/generic/backport-6.1/715-17-v6.5-net-phy-add-helpers-for-comparing-phy-IDs.patch
new file mode 100644
index 00000000000000..8a694c86dafc1a
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-17-v6.5-net-phy-add-helpers-for-comparing-phy-IDs.patch
@@ -0,0 +1,147 @@
+From b84acdb07222a701bfc6403b374249c86f97d18d Mon Sep 17 00:00:00 2001
+From: Russell King <rmk+kernel@armlinux.org.uk>
+Date: Fri, 19 May 2023 14:03:59 +0100
+Subject: [PATCH 15/21] net: phy: add helpers for comparing phy IDs
+
+There are several places which open code comparing PHY IDs. Provide a
+couple of helpers to assist with this, using a slightly simpler test
+than the original:
+
+- phy_id_compare() compares two arbitary PHY IDs and a mask of the
+  significant bits in the ID.
+- phydev_id_compare() compares the bound phydev with the specified
+  PHY ID, using the bound driver's mask.
+
+Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Simon Horman <simon.horman@corigine.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/micrel.c     |  6 +++---
+ drivers/net/phy/phy_device.c | 16 +++++++---------
+ drivers/net/phy/phylink.c    |  4 ++--
+ include/linux/phy.h          | 28 ++++++++++++++++++++++++++++
+ 4 files changed, 40 insertions(+), 14 deletions(-)
+
+--- a/drivers/net/phy/micrel.c
++++ b/drivers/net/phy/micrel.c
+@@ -620,7 +620,7 @@ static int ksz8051_ksz8795_match_phy_dev
+ {
+ 	int ret;
+ 
+-	if ((phydev->phy_id & MICREL_PHY_ID_MASK) != PHY_ID_KSZ8051)
++	if (!phy_id_compare(phydev->phy_id, PHY_ID_KSZ8051, MICREL_PHY_ID_MASK))
+ 		return 0;
+ 
+ 	ret = phy_read(phydev, MII_BMSR);
+@@ -1455,7 +1455,7 @@ static int ksz9x31_cable_test_fault_leng
+ 	 *
+ 	 * distance to fault = (VCT_DATA - 22) * 4 / cable propagation velocity
+ 	 */
+-	if ((phydev->phy_id & MICREL_PHY_ID_MASK) == PHY_ID_KSZ9131)
++	if (phydev_id_compare(phydev, PHY_ID_KSZ9131))
+ 		dt = clamp(dt - 22, 0, 255);
+ 
+ 	return (dt * 400) / 10;
+@@ -1887,7 +1887,7 @@ static __always_inline int ksz886x_cable
+ 	 */
+ 	dt = FIELD_GET(data_mask, status);
+ 
+-	if ((phydev->phy_id & MICREL_PHY_ID_MASK) == PHY_ID_LAN8814)
++	if (phydev_id_compare(phydev, PHY_ID_LAN8814))
+ 		return ((dt - 22) * 800) / 10;
+ 	else
+ 		return (dt * 400) / 10;
+--- a/drivers/net/phy/phy_device.c
++++ b/drivers/net/phy/phy_device.c
+@@ -422,8 +422,7 @@ int phy_unregister_fixup(const char *bus
+ 		fixup = list_entry(pos, struct phy_fixup, list);
+ 
+ 		if ((!strcmp(fixup->bus_id, bus_id)) &&
+-		    ((fixup->phy_uid & phy_uid_mask) ==
+-		     (phy_uid & phy_uid_mask))) {
++		    phy_id_compare(fixup->phy_uid, phy_uid, phy_uid_mask)) {
+ 			list_del(&fixup->list);
+ 			kfree(fixup);
+ 			ret = 0;
+@@ -459,8 +458,8 @@ static int phy_needs_fixup(struct phy_de
+ 		if (strcmp(fixup->bus_id, PHY_ANY_ID) != 0)
+ 			return 0;
+ 
+-	if ((fixup->phy_uid & fixup->phy_uid_mask) !=
+-	    (phydev->phy_id & fixup->phy_uid_mask))
++	if (!phy_id_compare(phydev->phy_id, fixup->phy_uid,
++			    fixup->phy_uid_mask))
+ 		if (fixup->phy_uid != PHY_ANY_UID)
+ 			return 0;
+ 
+@@ -507,15 +506,14 @@ static int phy_bus_match(struct device *
+ 			if (phydev->c45_ids.device_ids[i] == 0xffffffff)
+ 				continue;
+ 
+-			if ((phydrv->phy_id & phydrv->phy_id_mask) ==
+-			    (phydev->c45_ids.device_ids[i] &
+-			     phydrv->phy_id_mask))
++			if (phy_id_compare(phydev->c45_ids.device_ids[i],
++					   phydrv->phy_id, phydrv->phy_id_mask))
+ 				return 1;
+ 		}
+ 		return 0;
+ 	} else {
+-		return (phydrv->phy_id & phydrv->phy_id_mask) ==
+-			(phydev->phy_id & phydrv->phy_id_mask);
++		return phy_id_compare(phydev->phy_id, phydrv->phy_id,
++				      phydrv->phy_id_mask);
+ 	}
+ }
+ 
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -3151,8 +3151,8 @@ static void phylink_sfp_link_up(void *up
+  */
+ static bool phylink_phy_no_inband(struct phy_device *phy)
+ {
+-	return phy->is_c45 &&
+-		(phy->c45_ids.device_ids[1] & 0xfffffff0) == 0xae025150;
++	return phy->is_c45 && phy_id_compare(phy->c45_ids.device_ids[1],
++					     0xae025150, 0xfffffff0);
+ }
+ 
+ static int phylink_sfp_connect_phy(void *upstream, struct phy_device *phy)
+--- a/include/linux/phy.h
++++ b/include/linux/phy.h
+@@ -993,6 +993,34 @@ struct phy_driver {
+ #define PHY_ID_MATCH_MODEL(id) .phy_id = (id), .phy_id_mask = GENMASK(31, 4)
+ #define PHY_ID_MATCH_VENDOR(id) .phy_id = (id), .phy_id_mask = GENMASK(31, 10)
+ 
++/**
++ * phy_id_compare - compare @id1 with @id2 taking account of @mask
++ * @id1: first PHY ID
++ * @id2: second PHY ID
++ * @mask: the PHY ID mask, set bits are significant in matching
++ *
++ * Return true if the bits from @id1 and @id2 specified by @mask match.
++ * This uses an equivalent test to (@id & @mask) == (@phy_id & @mask).
++ */
++static inline bool phy_id_compare(u32 id1, u32 id2, u32 mask)
++{
++	return !((id1 ^ id2) & mask);
++}
++
++/**
++ * phydev_id_compare - compare @id with the PHY's Clause 22 ID
++ * @phydev: the PHY device
++ * @id: the PHY ID to be matched
++ *
++ * Compare the @phydev clause 22 ID with the provided @id and return true or
++ * false depending whether it matches, using the bound driver mask. The
++ * @phydev must be bound to a driver.
++ */
++static inline bool phydev_id_compare(struct phy_device *phydev, u32 id)
++{
++	return phy_id_compare(id, phydev->phy_id, phydev->drv->phy_id_mask);
++}
++
+ /* A Structure for boards to register fixups with the PHY Lib */
+ struct phy_fixup {
+ 	struct list_head list;
diff --git a/target/linux/generic/backport-6.1/715-18-v6.5-net-phylink-require-supported_interfaces-to-be-fille.patch b/target/linux/generic/backport-6.1/715-18-v6.5-net-phylink-require-supported_interfaces-to-be-fille.patch
new file mode 100644
index 00000000000000..5970355a6c21d1
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-18-v6.5-net-phylink-require-supported_interfaces-to-be-fille.patch
@@ -0,0 +1,71 @@
+From 441e1e44301fc5762a06737f8ec04bf1ce3fb039 Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Sat, 20 May 2023 11:41:42 +0100
+Subject: [PATCH 16/21] net: phylink: require supported_interfaces to be filled
+
+We have been requiring the supported_interfaces bitmap to be filled in
+by MAC drivers that have a mac_select_pcs() method. Now that all MAC
+drivers fill in the supported_interfaces bitmap, it is time to enforce
+this. We have already required supported_interfaces to be set in order
+for optical SFPs to be configured in commit f81fa96d8a6c ("net: phylink:
+use phy_interface_t bitmaps for optical modules").
+
+Refuse phylink creation if supported_interfaces is empty, and remove
+code to deal with cases where this mask is empty.
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://lore.kernel.org/r/E1q0K1u-006EIP-ET@rmk-PC.armlinux.org.uk
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/phylink.c | 26 +++++++++++---------------
+ 1 file changed, 11 insertions(+), 15 deletions(-)
+
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -710,14 +710,11 @@ static int phylink_validate(struct phyli
+ {
+ 	const unsigned long *interfaces = pl->config->supported_interfaces;
+ 
+-	if (!phy_interface_empty(interfaces)) {
+-		if (state->interface == PHY_INTERFACE_MODE_NA)
+-			return phylink_validate_mask(pl, supported, state,
+-						     interfaces);
++	if (state->interface == PHY_INTERFACE_MODE_NA)
++		return phylink_validate_mask(pl, supported, state, interfaces);
+ 
+-		if (!test_bit(state->interface, interfaces))
+-			return -EINVAL;
+-	}
++	if (!test_bit(state->interface, interfaces))
++		return -EINVAL;
+ 
+ 	return phylink_validate_mac_and_pcs(pl, supported, state);
+ }
+@@ -1512,19 +1509,18 @@ struct phylink *phylink_create(struct ph
+ 	struct phylink *pl;
+ 	int ret;
+ 
+-	if (mac_ops->mac_select_pcs &&
+-	    mac_ops->mac_select_pcs(config, PHY_INTERFACE_MODE_NA) !=
+-	      ERR_PTR(-EOPNOTSUPP))
+-		using_mac_select_pcs = true;
+-
+ 	/* Validate the supplied configuration */
+-	if (using_mac_select_pcs &&
+-	    phy_interface_empty(config->supported_interfaces)) {
++	if (phy_interface_empty(config->supported_interfaces)) {
+ 		dev_err(config->dev,
+-			"phylink: error: empty supported_interfaces but mac_select_pcs() method present\n");
++			"phylink: error: empty supported_interfaces\n");
+ 		return ERR_PTR(-EINVAL);
+ 	}
+ 
++	if (mac_ops->mac_select_pcs &&
++	    mac_ops->mac_select_pcs(config, PHY_INTERFACE_MODE_NA) !=
++	      ERR_PTR(-EOPNOTSUPP))
++		using_mac_select_pcs = true;
++
+ 	pl = kzalloc(sizeof(*pl), GFP_KERNEL);
+ 	if (!pl)
+ 		return ERR_PTR(-ENOMEM);
diff --git a/target/linux/generic/backport-6.1/715-19-v6.5-net-phylink-remove-duplicated-linkmode-pause-resolut.patch b/target/linux/generic/backport-6.1/715-19-v6.5-net-phylink-remove-duplicated-linkmode-pause-resolut.patch
new file mode 100644
index 00000000000000..3a26b4b6006ffb
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-19-v6.5-net-phylink-remove-duplicated-linkmode-pause-resolut.patch
@@ -0,0 +1,64 @@
+From 4b624a39f2ab523ca6a6ad9448fab1deb7b101e2 Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Tue, 23 May 2023 11:15:53 +0100
+Subject: [PATCH 17/21] net: phylink: remove duplicated linkmode pause
+ resolution
+
+Phylink had two chunks of code virtually the same for resolving the
+negotiated pause modes. Factor this down to one function.
+
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/phylink.c | 15 ++++-----------
+ 1 file changed, 4 insertions(+), 11 deletions(-)
+
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -976,11 +976,10 @@ static void phylink_apply_manual_flow(st
+ 		state->pause = pl->link_config.pause;
+ }
+ 
+-static void phylink_resolve_flow(struct phylink_link_state *state)
++static void phylink_resolve_an_pause(struct phylink_link_state *state)
+ {
+ 	bool tx_pause, rx_pause;
+ 
+-	state->pause = MLO_PAUSE_NONE;
+ 	if (state->duplex == DUPLEX_FULL) {
+ 		linkmode_resolve_pause(state->advertising,
+ 				       state->lp_advertising,
+@@ -1192,7 +1191,8 @@ static void phylink_get_fixed_state(stru
+ 	else if (pl->link_gpio)
+ 		state->link = !!gpiod_get_value_cansleep(pl->link_gpio);
+ 
+-	phylink_resolve_flow(state);
++	state->pause = MLO_PAUSE_NONE;
++	phylink_resolve_an_pause(state);
+ }
+ 
+ static void phylink_mac_initial_config(struct phylink *pl, bool force_restart)
+@@ -3215,7 +3215,6 @@ static const struct sfp_upstream_ops sfp
+ static void phylink_decode_c37_word(struct phylink_link_state *state,
+ 				    uint16_t config_reg, int speed)
+ {
+-	bool tx_pause, rx_pause;
+ 	int fd_bit;
+ 
+ 	if (speed == SPEED_2500)
+@@ -3234,13 +3233,7 @@ static void phylink_decode_c37_word(stru
+ 		state->link = false;
+ 	}
+ 
+-	linkmode_resolve_pause(state->advertising, state->lp_advertising,
+-			       &tx_pause, &rx_pause);
+-
+-	if (tx_pause)
+-		state->pause |= MLO_PAUSE_TX;
+-	if (rx_pause)
+-		state->pause |= MLO_PAUSE_RX;
++	phylink_resolve_an_pause(state);
+ }
+ 
+ static void phylink_decode_sgmii_word(struct phylink_link_state *state,
diff --git a/target/linux/generic/backport-6.1/715-20-v6.5-net-phylink-add-function-to-resolve-clause-73-negoti.patch b/target/linux/generic/backport-6.1/715-20-v6.5-net-phylink-add-function-to-resolve-clause-73-negoti.patch
new file mode 100644
index 00000000000000..2b2634f80c006c
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-20-v6.5-net-phylink-add-function-to-resolve-clause-73-negoti.patch
@@ -0,0 +1,76 @@
+From aa8b6bd2b1f235b262bd27f317a0516f196c2c6a Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Tue, 23 May 2023 11:15:58 +0100
+Subject: [PATCH 18/21] net: phylink: add function to resolve clause 73
+ negotiation
+
+Add a function to resolve clause 73 negotiation according to the
+priority resolution function described in clause 73.3.6.
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/phylink.c | 39 +++++++++++++++++++++++++++++++++++++++
+ include/linux/phylink.h   |  2 ++
+ 2 files changed, 41 insertions(+)
+
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -3212,6 +3212,45 @@ static const struct sfp_upstream_ops sfp
+ 
+ /* Helpers for MAC drivers */
+ 
++static struct {
++	int bit;
++	int speed;
++} phylink_c73_priority_resolution[] = {
++	{ ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, SPEED_100000 },
++	{ ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, SPEED_100000 },
++	/* 100GBASE-KP4 and 100GBASE-CR10 not supported */
++	{ ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, SPEED_40000 },
++	{ ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, SPEED_40000 },
++	{ ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, SPEED_10000 },
++	{ ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, SPEED_10000 },
++	/* 5GBASE-KR not supported */
++	{ ETHTOOL_LINK_MODE_2500baseX_Full_BIT, SPEED_2500 },
++	{ ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, SPEED_1000 },
++};
++
++void phylink_resolve_c73(struct phylink_link_state *state)
++{
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(phylink_c73_priority_resolution); i++) {
++		int bit = phylink_c73_priority_resolution[i].bit;
++		if (linkmode_test_bit(bit, state->advertising) &&
++		    linkmode_test_bit(bit, state->lp_advertising))
++			break;
++	}
++
++	if (i < ARRAY_SIZE(phylink_c73_priority_resolution)) {
++		state->speed = phylink_c73_priority_resolution[i].speed;
++		state->duplex = DUPLEX_FULL;
++	} else {
++		/* negotiation failure */
++		state->link = false;
++	}
++
++	phylink_resolve_an_pause(state);
++}
++EXPORT_SYMBOL_GPL(phylink_resolve_c73);
++
+ static void phylink_decode_c37_word(struct phylink_link_state *state,
+ 				    uint16_t config_reg, int speed)
+ {
+--- a/include/linux/phylink.h
++++ b/include/linux/phylink.h
+@@ -656,6 +656,8 @@ int phylink_mii_c22_pcs_config(struct md
+ 			       const unsigned long *advertising);
+ void phylink_mii_c22_pcs_an_restart(struct mdio_device *pcs);
+ 
++void phylink_resolve_c73(struct phylink_link_state *state);
++
+ void phylink_mii_c45_pcs_get_state(struct mdio_device *pcs,
+ 				   struct phylink_link_state *state);
+ 
diff --git a/target/linux/generic/backport-6.1/715-21-v6.5-net-phylink-provide-phylink_pcs_config-and-phylink_p.patch b/target/linux/generic/backport-6.1/715-21-v6.5-net-phylink-provide-phylink_pcs_config-and-phylink_p.patch
new file mode 100644
index 00000000000000..eea99a5d782e83
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-21-v6.5-net-phylink-provide-phylink_pcs_config-and-phylink_p.patch
@@ -0,0 +1,100 @@
+From 796d709363135a6bd6a8ccc07b509c939e5b855f Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Tue, 23 May 2023 16:31:50 +0100
+Subject: [PATCH 19/21] net: phylink: provide phylink_pcs_config() and
+ phylink_pcs_link_up()
+
+Add two helper functions for calling PCS methods. phylink_pcs_config()
+allows us to handle PCS configuration specifics in one location, rather
+than the two call sites. phylink_pcs_link_up() gives us consistency.
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Link: https://lore.kernel.org/r/E1q1TzK-007Exd-Rs@rmk-PC.armlinux.org.uk
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/phylink.c | 53 ++++++++++++++++++++++++---------------
+ 1 file changed, 33 insertions(+), 20 deletions(-)
+
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -991,6 +991,25 @@ static void phylink_resolve_an_pause(str
+ 	}
+ }
+ 
++static int phylink_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
++			      const struct phylink_link_state *state,
++			      bool permit_pause_to_mac)
++{
++	if (!pcs)
++		return 0;
++
++	return pcs->ops->pcs_config(pcs, mode, state->interface,
++				    state->advertising, permit_pause_to_mac);
++}
++
++static void phylink_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
++				phy_interface_t interface, int speed,
++				int duplex)
++{
++	if (pcs && pcs->ops->pcs_link_up)
++		pcs->ops->pcs_link_up(pcs, mode, interface, speed, duplex);
++}
++
+ static void phylink_pcs_poll_stop(struct phylink *pl)
+ {
+ 	if (pl->cfg_link_an_mode == MLO_AN_INBAND)
+@@ -1074,18 +1093,15 @@ static void phylink_major_config(struct
+ 
+ 	phylink_mac_config(pl, state);
+ 
+-	if (pl->pcs) {
+-		err = pl->pcs->ops->pcs_config(pl->pcs, pl->cur_link_an_mode,
+-					       state->interface,
+-					       state->advertising,
+-					       !!(pl->link_config.pause &
+-						  MLO_PAUSE_AN));
+-		if (err < 0)
+-			phylink_err(pl, "pcs_config failed: %pe\n",
+-				    ERR_PTR(err));
+-		if (err > 0)
+-			restart = true;
+-	}
++	err = phylink_pcs_config(pl->pcs, pl->cur_link_an_mode, state,
++				 !!(pl->link_config.pause &
++				    MLO_PAUSE_AN));
++	if (err < 0)
++		phylink_err(pl, "pcs_config failed: %pe\n",
++			    ERR_PTR(err));
++	else if (err > 0)
++		restart = true;
++
+ 	if (restart)
+ 		phylink_mac_pcs_an_restart(pl);
+ 
+@@ -1136,11 +1152,9 @@ static int phylink_change_inband_advert(
+ 	 * restart negotiation if the pcs_config() helper indicates that
+ 	 * the programmed advertisement has changed.
+ 	 */
+-	ret = pl->pcs->ops->pcs_config(pl->pcs, pl->cur_link_an_mode,
+-				       pl->link_config.interface,
+-				       pl->link_config.advertising,
+-				       !!(pl->link_config.pause &
+-					  MLO_PAUSE_AN));
++	ret = phylink_pcs_config(pl->pcs, pl->cur_link_an_mode,
++				 &pl->link_config,
++				 !!(pl->link_config.pause & MLO_PAUSE_AN));
+ 	if (ret < 0)
+ 		return ret;
+ 
+@@ -1272,9 +1286,8 @@ static void phylink_link_up(struct phyli
+ 
+ 	pl->cur_interface = link_state.interface;
+ 
+-	if (pl->pcs && pl->pcs->ops->pcs_link_up)
+-		pl->pcs->ops->pcs_link_up(pl->pcs, pl->cur_link_an_mode,
+-					  pl->cur_interface, speed, duplex);
++	phylink_pcs_link_up(pl->pcs, pl->cur_link_an_mode, pl->cur_interface,
++			    speed, duplex);
+ 
+ 	pl->mac_ops->mac_link_up(pl->config, pl->phydev, pl->cur_link_an_mode,
+ 				 pl->cur_interface, speed, duplex,
diff --git a/target/linux/generic/backport-6.1/715-23-v6.4-net-phylink-actually-fix-ksettings_set-ethtool-call.patch b/target/linux/generic/backport-6.1/715-23-v6.4-net-phylink-actually-fix-ksettings_set-ethtool-call.patch
new file mode 100644
index 00000000000000..2f7f7a5737fcab
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-23-v6.4-net-phylink-actually-fix-ksettings_set-ethtool-call.patch
@@ -0,0 +1,55 @@
+From 11933aa76865621d8e82553c8f3bc07796a5aaa2 Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Thu, 1 Jun 2023 10:12:06 +0100
+Subject: [PATCH 20/21] net: phylink: actually fix ksettings_set() ethtool call
+
+Raju Lakkaraju reported that the below commit caused a regression
+with Lan743x drivers and a 2.5G SFP. Sadly, this is because the commit
+was utterly wrong. Let's fix this properly by not moving the
+linkmode_and(), but instead copying the link ksettings and then
+modifying the advertising mask before passing the modified link
+ksettings to phylib.
+
+Fixes: df0acdc59b09 ("net: phylink: fix ksettings_set() ethtool call")
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Link: https://lore.kernel.org/r/E1q4eLm-00Ayxk-GZ@rmk-PC.armlinux.org.uk
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/phylink.c | 15 ++++++++++-----
+ 1 file changed, 10 insertions(+), 5 deletions(-)
+
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -2259,11 +2259,13 @@ int phylink_ethtool_ksettings_set(struct
+ 
+ 	ASSERT_RTNL();
+ 
+-	/* Mask out unsupported advertisements */
+-	linkmode_and(config.advertising, kset->link_modes.advertising,
+-		     pl->supported);
+-
+ 	if (pl->phydev) {
++		struct ethtool_link_ksettings phy_kset = *kset;
++
++		linkmode_and(phy_kset.link_modes.advertising,
++			     phy_kset.link_modes.advertising,
++			     pl->supported);
++
+ 		/* We can rely on phylib for this update; we also do not need
+ 		 * to update the pl->link_config settings:
+ 		 * - the configuration returned via ksettings_get() will come
+@@ -2282,10 +2284,13 @@ int phylink_ethtool_ksettings_set(struct
+ 		 *   the presence of a PHY, this should not be changed as that
+ 		 *   should be determined from the media side advertisement.
+ 		 */
+-		return phy_ethtool_ksettings_set(pl->phydev, kset);
++		return phy_ethtool_ksettings_set(pl->phydev, &phy_kset);
+ 	}
+ 
+ 	config = pl->link_config;
++	/* Mask out unsupported advertisements */
++	linkmode_and(config.advertising, kset->link_modes.advertising,
++		     pl->supported);
+ 
+ 	/* FIXME: should we reject autoneg if phy/mac does not support it? */
+ 	switch (kset->base.autoneg) {
diff --git a/target/linux/generic/backport-6.1/715-24-v6.5-net-phylink-add-PCS-negotiation-mode.patch b/target/linux/generic/backport-6.1/715-24-v6.5-net-phylink-add-PCS-negotiation-mode.patch
new file mode 100644
index 00000000000000..e1a8539aae425e
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-24-v6.5-net-phylink-add-PCS-negotiation-mode.patch
@@ -0,0 +1,324 @@
+From 79b07c3e9c4a2272927be8848c26b372516e1958 Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Fri, 16 Jun 2023 13:06:22 +0100
+Subject: [PATCH 21/21] net: phylink: add PCS negotiation mode
+
+PCS have to work out whether they should enable PCS negotiation by
+looking at the "mode" and "interface" arguments, and the Autoneg bit
+in the advertising mask.
+
+This leads to some complex logic, so lets pull that out into phylink
+and instead pass a "neg_mode" argument to the PCS configuration and
+link up methods, instead of the "mode" argument.
+
+In order to transition drivers, add a "neg_mode" flag to the phylink
+PCS structure to PCS can indicate whether they want to be passed the
+neg_mode or the old mode argument.
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Link: https://lore.kernel.org/r/E1qA8De-00EaFA-Ht@rmk-PC.armlinux.org.uk
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/phylink.c |  45 +++++++++++++----
+ include/linux/phylink.h   | 104 +++++++++++++++++++++++++++++++++++---
+ 2 files changed, 132 insertions(+), 17 deletions(-)
+
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -71,6 +71,7 @@ struct phylink {
+ 	struct mutex state_mutex;
+ 	struct phylink_link_state phy_state;
+ 	struct work_struct resolve;
++	unsigned int pcs_neg_mode;
+ 
+ 	bool mac_link_dropped;
+ 	bool using_mac_select_pcs;
+@@ -991,23 +992,23 @@ static void phylink_resolve_an_pause(str
+ 	}
+ }
+ 
+-static int phylink_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
++static int phylink_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
+ 			      const struct phylink_link_state *state,
+ 			      bool permit_pause_to_mac)
+ {
+ 	if (!pcs)
+ 		return 0;
+ 
+-	return pcs->ops->pcs_config(pcs, mode, state->interface,
++	return pcs->ops->pcs_config(pcs, neg_mode, state->interface,
+ 				    state->advertising, permit_pause_to_mac);
+ }
+ 
+-static void phylink_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
++static void phylink_pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,
+ 				phy_interface_t interface, int speed,
+ 				int duplex)
+ {
+ 	if (pcs && pcs->ops->pcs_link_up)
+-		pcs->ops->pcs_link_up(pcs, mode, interface, speed, duplex);
++		pcs->ops->pcs_link_up(pcs, neg_mode, interface, speed, duplex);
+ }
+ 
+ static void phylink_pcs_poll_stop(struct phylink *pl)
+@@ -1057,10 +1058,15 @@ static void phylink_major_config(struct
+ 	struct phylink_pcs *pcs = NULL;
+ 	bool pcs_changed = false;
+ 	unsigned int rate_kbd;
++	unsigned int neg_mode;
+ 	int err;
+ 
+ 	phylink_dbg(pl, "major config %s\n", phy_modes(state->interface));
+ 
++	pl->pcs_neg_mode = phylink_pcs_neg_mode(pl->cur_link_an_mode,
++						state->interface,
++						state->advertising);
++
+ 	if (pl->using_mac_select_pcs) {
+ 		pcs = pl->mac_ops->mac_select_pcs(pl->config, state->interface);
+ 		if (IS_ERR(pcs)) {
+@@ -1093,9 +1099,12 @@ static void phylink_major_config(struct
+ 
+ 	phylink_mac_config(pl, state);
+ 
+-	err = phylink_pcs_config(pl->pcs, pl->cur_link_an_mode, state,
+-				 !!(pl->link_config.pause &
+-				    MLO_PAUSE_AN));
++	neg_mode = pl->cur_link_an_mode;
++	if (pl->pcs && pl->pcs->neg_mode)
++		neg_mode = pl->pcs_neg_mode;
++
++	err = phylink_pcs_config(pl->pcs, neg_mode, state,
++				 !!(pl->link_config.pause & MLO_PAUSE_AN));
+ 	if (err < 0)
+ 		phylink_err(pl, "pcs_config failed: %pe\n",
+ 			    ERR_PTR(err));
+@@ -1130,6 +1139,7 @@ static void phylink_major_config(struct
+  */
+ static int phylink_change_inband_advert(struct phylink *pl)
+ {
++	unsigned int neg_mode;
+ 	int ret;
+ 
+ 	if (test_bit(PHYLINK_DISABLE_STOPPED, &pl->phylink_disable_state))
+@@ -1148,12 +1158,20 @@ static int phylink_change_inband_advert(
+ 		    __ETHTOOL_LINK_MODE_MASK_NBITS, pl->link_config.advertising,
+ 		    pl->link_config.pause);
+ 
++	/* Recompute the PCS neg mode */
++	pl->pcs_neg_mode = phylink_pcs_neg_mode(pl->cur_link_an_mode,
++					pl->link_config.interface,
++					pl->link_config.advertising);
++
++	neg_mode = pl->cur_link_an_mode;
++	if (pl->pcs->neg_mode)
++		neg_mode = pl->pcs_neg_mode;
++
+ 	/* Modern PCS-based method; update the advert at the PCS, and
+ 	 * restart negotiation if the pcs_config() helper indicates that
+ 	 * the programmed advertisement has changed.
+ 	 */
+-	ret = phylink_pcs_config(pl->pcs, pl->cur_link_an_mode,
+-				 &pl->link_config,
++	ret = phylink_pcs_config(pl->pcs, neg_mode, &pl->link_config,
+ 				 !!(pl->link_config.pause & MLO_PAUSE_AN));
+ 	if (ret < 0)
+ 		return ret;
+@@ -1256,6 +1274,7 @@ static void phylink_link_up(struct phyli
+ 			    struct phylink_link_state link_state)
+ {
+ 	struct net_device *ndev = pl->netdev;
++	unsigned int neg_mode;
+ 	int speed, duplex;
+ 	bool rx_pause;
+ 
+@@ -1286,8 +1305,12 @@ static void phylink_link_up(struct phyli
+ 
+ 	pl->cur_interface = link_state.interface;
+ 
+-	phylink_pcs_link_up(pl->pcs, pl->cur_link_an_mode, pl->cur_interface,
+-			    speed, duplex);
++	neg_mode = pl->cur_link_an_mode;
++	if (pl->pcs && pl->pcs->neg_mode)
++		neg_mode = pl->pcs_neg_mode;
++
++	phylink_pcs_link_up(pl->pcs, neg_mode, pl->cur_interface, speed,
++			    duplex);
+ 
+ 	pl->mac_ops->mac_link_up(pl->config, pl->phydev, pl->cur_link_an_mode,
+ 				 pl->cur_interface, speed, duplex,
+--- a/include/linux/phylink.h
++++ b/include/linux/phylink.h
+@@ -21,6 +21,24 @@ enum {
+ 	MLO_AN_FIXED,	/* Fixed-link mode */
+ 	MLO_AN_INBAND,	/* In-band protocol */
+ 
++	/* PCS "negotiation" mode.
++	 *  PHYLINK_PCS_NEG_NONE - protocol has no inband capability
++	 *  PHYLINK_PCS_NEG_OUTBAND - some out of band or fixed link setting
++	 *  PHYLINK_PCS_NEG_INBAND_DISABLED - inband mode disabled, e.g.
++	 *				      1000base-X with autoneg off
++	 *  PHYLINK_PCS_NEG_INBAND_ENABLED - inband mode enabled
++	 * Additionally, this can be tested using bitmasks:
++	 *  PHYLINK_PCS_NEG_INBAND - inband mode selected
++	 *  PHYLINK_PCS_NEG_ENABLED - negotiation mode enabled
++	 */
++	PHYLINK_PCS_NEG_NONE = 0,
++	PHYLINK_PCS_NEG_ENABLED = BIT(4),
++	PHYLINK_PCS_NEG_OUTBAND = BIT(5),
++	PHYLINK_PCS_NEG_INBAND = BIT(6),
++	PHYLINK_PCS_NEG_INBAND_DISABLED = PHYLINK_PCS_NEG_INBAND,
++	PHYLINK_PCS_NEG_INBAND_ENABLED = PHYLINK_PCS_NEG_INBAND |
++					 PHYLINK_PCS_NEG_ENABLED,
++
+ 	/* MAC_SYM_PAUSE and MAC_ASYM_PAUSE are used when configuring our
+ 	 * autonegotiation advertisement. They correspond to the PAUSE and
+ 	 * ASM_DIR bits defined by 802.3, respectively.
+@@ -80,6 +98,70 @@ static inline bool phylink_autoneg_inban
+ }
+ 
+ /**
++ * phylink_pcs_neg_mode() - helper to determine PCS inband mode
++ * @mode: one of %MLO_AN_FIXED, %MLO_AN_PHY, %MLO_AN_INBAND.
++ * @interface: interface mode to be used
++ * @advertising: adertisement ethtool link mode mask
++ *
++ * Determines the negotiation mode to be used by the PCS, and returns
++ * one of:
++ * %PHYLINK_PCS_NEG_NONE: interface mode does not support inband
++ * %PHYLINK_PCS_NEG_OUTBAND: an out of band mode (e.g. reading the PHY)
++ *   will be used.
++ * %PHYLINK_PCS_NEG_INBAND_DISABLED: inband mode selected but autoneg disabled
++ * %PHYLINK_PCS_NEG_INBAND_ENABLED: inband mode selected and autoneg enabled
++ *
++ * Note: this is for cases where the PCS itself is involved in negotiation
++ * (e.g. Clause 37, SGMII and similar) not Clause 73.
++ */
++static inline unsigned int phylink_pcs_neg_mode(unsigned int mode,
++						phy_interface_t interface,
++						const unsigned long *advertising)
++{
++	unsigned int neg_mode;
++
++	switch (interface) {
++	case PHY_INTERFACE_MODE_SGMII:
++	case PHY_INTERFACE_MODE_QSGMII:
++	case PHY_INTERFACE_MODE_QUSGMII:
++	case PHY_INTERFACE_MODE_USXGMII:
++		/* These protocols are designed for use with a PHY which
++		 * communicates its negotiation result back to the MAC via
++		 * inband communication. Note: there exist PHYs that run
++		 * with SGMII but do not send the inband data.
++		 */
++		if (!phylink_autoneg_inband(mode))
++			neg_mode = PHYLINK_PCS_NEG_OUTBAND;
++		else
++			neg_mode = PHYLINK_PCS_NEG_INBAND_ENABLED;
++		break;
++
++	case PHY_INTERFACE_MODE_1000BASEX:
++	case PHY_INTERFACE_MODE_2500BASEX:
++		/* 1000base-X is designed for use media-side for Fibre
++		 * connections, and thus the Autoneg bit needs to be
++		 * taken into account. We also do this for 2500base-X
++		 * as well, but drivers may not support this, so may
++		 * need to override this.
++		 */
++		if (!phylink_autoneg_inband(mode))
++			neg_mode = PHYLINK_PCS_NEG_OUTBAND;
++		else if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
++					   advertising))
++			neg_mode = PHYLINK_PCS_NEG_INBAND_ENABLED;
++		else
++			neg_mode = PHYLINK_PCS_NEG_INBAND_DISABLED;
++		break;
++
++	default:
++		neg_mode = PHYLINK_PCS_NEG_NONE;
++		break;
++	}
++
++	return neg_mode;
++}
++
++/**
+  * struct phylink_link_state - link state structure
+  * @advertising: ethtool bitmask containing advertised link modes
+  * @lp_advertising: ethtool bitmask containing link partner advertised link
+@@ -436,6 +518,7 @@ struct phylink_pcs_ops;
+ /**
+  * struct phylink_pcs - PHYLINK PCS instance
+  * @ops: a pointer to the &struct phylink_pcs_ops structure
++ * @neg_mode: provide PCS neg mode via "mode" argument
+  * @poll: poll the PCS for link changes
+  *
+  * This structure is designed to be embedded within the PCS private data,
+@@ -443,6 +526,7 @@ struct phylink_pcs_ops;
+  */
+ struct phylink_pcs {
+ 	const struct phylink_pcs_ops *ops;
++	bool neg_mode;
+ 	bool poll;
+ };
+ 
+@@ -460,12 +544,12 @@ struct phylink_pcs_ops {
+ 			    const struct phylink_link_state *state);
+ 	void (*pcs_get_state)(struct phylink_pcs *pcs,
+ 			      struct phylink_link_state *state);
+-	int (*pcs_config)(struct phylink_pcs *pcs, unsigned int mode,
++	int (*pcs_config)(struct phylink_pcs *pcs, unsigned int neg_mode,
+ 			  phy_interface_t interface,
+ 			  const unsigned long *advertising,
+ 			  bool permit_pause_to_mac);
+ 	void (*pcs_an_restart)(struct phylink_pcs *pcs);
+-	void (*pcs_link_up)(struct phylink_pcs *pcs, unsigned int mode,
++	void (*pcs_link_up)(struct phylink_pcs *pcs, unsigned int neg_mode,
+ 			    phy_interface_t interface, int speed, int duplex);
+ };
+ 
+@@ -508,7 +592,7 @@ void pcs_get_state(struct phylink_pcs *p
+ /**
+  * pcs_config() - Configure the PCS mode and advertisement
+  * @pcs: a pointer to a &struct phylink_pcs.
+- * @mode: one of %MLO_AN_FIXED, %MLO_AN_PHY, %MLO_AN_INBAND.
++ * @neg_mode: link negotiation mode (see below)
+  * @interface: interface mode to be used
+  * @advertising: adertisement ethtool link mode mask
+  * @permit_pause_to_mac: permit forwarding pause resolution to MAC
+@@ -526,8 +610,12 @@ void pcs_get_state(struct phylink_pcs *p
+  * For 1000BASE-X, the advertisement should be programmed into the PCS.
+  *
+  * For most 10GBASE-R, there is no advertisement.
++ *
++ * The %neg_mode argument should be tested via the phylink_mode_*() family of
++ * functions, or for PCS that set pcs->neg_mode true, should be tested
++ * against the %PHYLINK_PCS_NEG_* definitions.
+  */
+-int pcs_config(struct phylink_pcs *pcs, unsigned int mode,
++int pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
+ 	       phy_interface_t interface, const unsigned long *advertising,
+ 	       bool permit_pause_to_mac);
+ 
+@@ -543,7 +631,7 @@ void pcs_an_restart(struct phylink_pcs *
+ /**
+  * pcs_link_up() - program the PCS for the resolved link configuration
+  * @pcs: a pointer to a &struct phylink_pcs.
+- * @mode: link autonegotiation mode
++ * @neg_mode: link negotiation mode (see below)
+  * @interface: link &typedef phy_interface_t mode
+  * @speed: link speed
+  * @duplex: link duplex
+@@ -552,8 +640,12 @@ void pcs_an_restart(struct phylink_pcs *
+  * the resolved link parameters. For example, a PCS operating in SGMII
+  * mode without in-band AN needs to be manually configured for the link
+  * and duplex setting. Otherwise, this should be a no-op.
++ *
++ * The %mode argument should be tested via the phylink_mode_*() family of
++ * functions, or for PCS that set pcs->neg_mode true, should be tested
++ * against the %PHYLINK_PCS_NEG_* definitions.
+  */
+-void pcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
++void pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,
+ 		 phy_interface_t interface, int speed, int duplex);
+ #endif
+ 
diff --git a/target/linux/generic/backport-6.1/715-25-v6.5-net-phylink-convert-phylink_mii_c22_pcs_config-to-ne.patch b/target/linux/generic/backport-6.1/715-25-v6.5-net-phylink-convert-phylink_mii_c22_pcs_config-to-ne.patch
new file mode 100644
index 00000000000000..473e9d5836d1c2
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-25-v6.5-net-phylink-convert-phylink_mii_c22_pcs_config-to-ne.patch
@@ -0,0 +1,45 @@
+From cdb08aa0473730315dbc088d5394e59622314034 Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Fri, 16 Jun 2023 13:06:27 +0100
+Subject: [PATCH 1/2] net: phylink: convert phylink_mii_c22_pcs_config() to
+ neg_mode
+
+Use phylink_pcs_neg_mode() for phylink_mii_c22_pcs_config(). This
+results in no functional change.
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Link: https://lore.kernel.org/r/E1qA8Dj-00EaFG-Mt@rmk-PC.armlinux.org.uk
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/phylink.c | 9 ++++-----
+ 1 file changed, 4 insertions(+), 5 deletions(-)
+
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -3558,6 +3558,7 @@ int phylink_mii_c22_pcs_config(struct md
+ 			       phy_interface_t interface,
+ 			       const unsigned long *advertising)
+ {
++	unsigned int neg_mode;
+ 	bool changed = 0;
+ 	u16 bmcr;
+ 	int ret, adv;
+@@ -3571,15 +3572,13 @@ int phylink_mii_c22_pcs_config(struct md
+ 		changed = ret;
+ 	}
+ 
+-	/* Ensure ISOLATE bit is disabled */
+-	if (mode == MLO_AN_INBAND &&
+-	    (interface == PHY_INTERFACE_MODE_SGMII ||
+-	     interface == PHY_INTERFACE_MODE_QSGMII ||
+-	     linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, advertising)))
++	neg_mode = phylink_pcs_neg_mode(mode, interface, advertising);
++	if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
+ 		bmcr = BMCR_ANENABLE;
+ 	else
+ 		bmcr = 0;
+ 
++	/* Configure the inband state. Ensure ISOLATE bit is disabled */
+ 	ret = mdiodev_modify(pcs, MII_BMCR, BMCR_ANENABLE | BMCR_ISOLATE, bmcr);
+ 	if (ret < 0)
+ 		return ret;
diff --git a/target/linux/generic/backport-6.1/715-26-v6.5-net-phylink-pass-neg_mode-into-phylink_mii_c22_pcs_c.patch b/target/linux/generic/backport-6.1/715-26-v6.5-net-phylink-pass-neg_mode-into-phylink_mii_c22_pcs_c.patch
new file mode 100644
index 00000000000000..5572850e95a8fe
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-26-v6.5-net-phylink-pass-neg_mode-into-phylink_mii_c22_pcs_c.patch
@@ -0,0 +1,187 @@
+From febf2aaf05641f3258cc30e072aff65cffc7c82c Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Fri, 16 Jun 2023 13:06:32 +0100
+Subject: [PATCH 2/2] net: phylink: pass neg_mode into
+ phylink_mii_c22_pcs_config()
+
+Convert fman_dtsec, xilinx_axienet and pcs-lynx to pass the neg_mode
+into phylink_mii_c22_pcs_config(). Where appropriate, drivers are
+updated to have neg_mode passed into their pcs_config() and
+pcs_link_up() functions. For other drivers, we just hoist the call
+to phylink_pcs_neg_mode() to their pcs_config() method out of
+phylink_mii_c22_pcs_config().
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Link: https://lore.kernel.org/r/E1qA8Do-00EaFM-Ra@rmk-PC.armlinux.org.uk
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ .../net/ethernet/freescale/fman/fman_dtsec.c   |  7 ++++---
+ .../net/ethernet/xilinx/xilinx_axienet_main.c  |  6 ++++--
+ drivers/net/pcs/pcs-lynx.c                     | 18 ++++++++++++------
+ drivers/net/phy/phylink.c                      |  9 ++++-----
+ include/linux/phylink.h                        |  5 +++--
+ 5 files changed, 27 insertions(+), 18 deletions(-)
+
+--- a/drivers/net/ethernet/freescale/fman/fman_dtsec.c
++++ b/drivers/net/ethernet/freescale/fman/fman_dtsec.c
+@@ -763,15 +763,15 @@ static void dtsec_pcs_get_state(struct p
+ 	phylink_mii_c22_pcs_get_state(dtsec->tbidev, state);
+ }
+ 
+-static int dtsec_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
++static int dtsec_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
+ 			    phy_interface_t interface,
+ 			    const unsigned long *advertising,
+ 			    bool permit_pause_to_mac)
+ {
+ 	struct fman_mac *dtsec = pcs_to_dtsec(pcs);
+ 
+-	return phylink_mii_c22_pcs_config(dtsec->tbidev, mode, interface,
+-					  advertising);
++	return phylink_mii_c22_pcs_config(dtsec->tbidev, interface,
++					  advertising, neg_mode);
+ }
+ 
+ static void dtsec_pcs_an_restart(struct phylink_pcs *pcs)
+@@ -1447,6 +1447,7 @@ int dtsec_initialization(struct mac_devi
+ 		goto _return_fm_mac_free;
+ 	}
+ 	dtsec->pcs.ops = &dtsec_pcs_ops;
++	dtsec->pcs.neg_mode = true;
+ 	dtsec->pcs.poll = true;
+ 
+ 	supported = mac_dev->phylink_config.supported_interfaces;
+--- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
++++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
+@@ -1631,7 +1631,7 @@ static void axienet_pcs_an_restart(struc
+ 	phylink_mii_c22_pcs_an_restart(pcs_phy);
+ }
+ 
+-static int axienet_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
++static int axienet_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
+ 			      phy_interface_t interface,
+ 			      const unsigned long *advertising,
+ 			      bool permit_pause_to_mac)
+@@ -1653,7 +1653,8 @@ static int axienet_pcs_config(struct phy
+ 		}
+ 	}
+ 
+-	ret = phylink_mii_c22_pcs_config(pcs_phy, mode, interface, advertising);
++	ret = phylink_mii_c22_pcs_config(pcs_phy, interface, advertising,
++					 neg_mode);
+ 	if (ret < 0)
+ 		netdev_warn(ndev, "Failed to configure PCS: %d\n", ret);
+ 
+@@ -2129,6 +2130,7 @@ static int axienet_probe(struct platform
+ 		}
+ 		of_node_put(np);
+ 		lp->pcs.ops = &axienet_pcs_ops;
++		lp->pcs.neg_mode = true;
+ 		lp->pcs.poll = true;
+ 	}
+ 
+--- a/drivers/net/pcs/pcs-lynx.c
++++ b/drivers/net/pcs/pcs-lynx.c
+@@ -122,9 +122,10 @@ static void lynx_pcs_get_state(struct ph
+ 		state->link, state->an_complete);
+ }
+ 
+-static int lynx_pcs_config_giga(struct mdio_device *pcs, unsigned int mode,
++static int lynx_pcs_config_giga(struct mdio_device *pcs,
+ 				phy_interface_t interface,
+-				const unsigned long *advertising)
++				const unsigned long *advertising,
++				unsigned int neg_mode)
+ {
+ 	u32 link_timer;
+ 	u16 if_mode;
+@@ -137,8 +138,9 @@ static int lynx_pcs_config_giga(struct m
+ 
+ 		if_mode = 0;
+ 	} else {
++		/* SGMII and QSGMII */
+ 		if_mode = IF_MODE_SGMII_EN;
+-		if (mode == MLO_AN_INBAND) {
++		if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
+ 			if_mode |= IF_MODE_USE_SGMII_AN;
+ 
+ 			/* Adjust link timer for SGMII */
+@@ -154,7 +156,8 @@ static int lynx_pcs_config_giga(struct m
+ 	if (err)
+ 		return err;
+ 
+-	return phylink_mii_c22_pcs_config(pcs, mode, interface, advertising);
++	return phylink_mii_c22_pcs_config(pcs, interface, advertising,
++					  neg_mode);
+ }
+ 
+ static int lynx_pcs_config_usxgmii(struct mdio_device *pcs, unsigned int mode,
+@@ -181,13 +184,16 @@ static int lynx_pcs_config(struct phylin
+ 			   bool permit)
+ {
+ 	struct lynx_pcs *lynx = phylink_pcs_to_lynx(pcs);
++	unsigned int neg_mode;
++
++	neg_mode = phylink_pcs_neg_mode(mode, ifmode, advertising);
+ 
+ 	switch (ifmode) {
+ 	case PHY_INTERFACE_MODE_1000BASEX:
+ 	case PHY_INTERFACE_MODE_SGMII:
+ 	case PHY_INTERFACE_MODE_QSGMII:
+-		return lynx_pcs_config_giga(lynx->mdio, mode, ifmode,
+-					    advertising);
++		return lynx_pcs_config_giga(lynx->mdio, ifmode, advertising,
++					    neg_mode);
+ 	case PHY_INTERFACE_MODE_2500BASEX:
+ 		if (phylink_autoneg_inband(mode)) {
+ 			dev_err(&lynx->mdio->dev,
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -3545,20 +3545,20 @@ EXPORT_SYMBOL_GPL(phylink_mii_c22_pcs_en
+ /**
+  * phylink_mii_c22_pcs_config() - configure clause 22 PCS
+  * @pcs: a pointer to a &struct mdio_device.
+- * @mode: link autonegotiation mode
+  * @interface: the PHY interface mode being configured
+  * @advertising: the ethtool advertisement mask
++ * @neg_mode: PCS negotiation mode
+  *
+  * Configure a Clause 22 PCS PHY with the appropriate negotiation
+  * parameters for the @mode, @interface and @advertising parameters.
+  * Returns negative error number on failure, zero if the advertisement
+  * has not changed, or positive if there is a change.
+  */
+-int phylink_mii_c22_pcs_config(struct mdio_device *pcs, unsigned int mode,
++int phylink_mii_c22_pcs_config(struct mdio_device *pcs,
+ 			       phy_interface_t interface,
+-			       const unsigned long *advertising)
++			       const unsigned long *advertising,
++			       unsigned int neg_mode)
+ {
+-	unsigned int neg_mode;
+ 	bool changed = 0;
+ 	u16 bmcr;
+ 	int ret, adv;
+@@ -3572,7 +3572,6 @@ int phylink_mii_c22_pcs_config(struct md
+ 		changed = ret;
+ 	}
+ 
+-	neg_mode = phylink_pcs_neg_mode(mode, interface, advertising);
+ 	if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
+ 		bmcr = BMCR_ANENABLE;
+ 	else
+--- a/include/linux/phylink.h
++++ b/include/linux/phylink.h
+@@ -743,9 +743,10 @@ void phylink_mii_c22_pcs_get_state(struc
+ 				   struct phylink_link_state *state);
+ int phylink_mii_c22_pcs_encode_advertisement(phy_interface_t interface,
+ 					     const unsigned long *advertising);
+-int phylink_mii_c22_pcs_config(struct mdio_device *pcs, unsigned int mode,
++int phylink_mii_c22_pcs_config(struct mdio_device *pcs,
+ 			       phy_interface_t interface,
+-			       const unsigned long *advertising);
++			       const unsigned long *advertising,
++			       unsigned int neg_mode);
+ void phylink_mii_c22_pcs_an_restart(struct mdio_device *pcs);
+ 
+ void phylink_resolve_c73(struct phylink_link_state *state);
diff --git a/target/linux/generic/backport-6.1/715-27-v6.5-net-pcs-lynxi-update-PCS-driver-to-use-neg_mode.patch b/target/linux/generic/backport-6.1/715-27-v6.5-net-pcs-lynxi-update-PCS-driver-to-use-neg_mode.patch
new file mode 100644
index 00000000000000..5e0128766ca8de
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-27-v6.5-net-pcs-lynxi-update-PCS-driver-to-use-neg_mode.patch
@@ -0,0 +1,101 @@
+From 3b2de56a146f34e3f70a84cc3a1897064e445d16 Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Fri, 16 Jun 2023 13:06:43 +0100
+Subject: [PATCH] net: pcs: lynxi: update PCS driver to use neg_mode
+
+Update the Lynxi PCS driver to use neg_mode rather than the mode
+argument. This ensures that the link_up() method will always program
+the speed and duplex when negotiation is disabled.
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Link: https://lore.kernel.org/r/E1qA8Dz-00EaFY-5A@rmk-PC.armlinux.org.uk
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/pcs/pcs-mtk-lynxi.c | 39 ++++++++++++++-------------------
+ 1 file changed, 16 insertions(+), 23 deletions(-)
+
+--- a/drivers/net/pcs/pcs-mtk-lynxi.c
++++ b/drivers/net/pcs/pcs-mtk-lynxi.c
+@@ -102,13 +102,13 @@ static void mtk_pcs_lynxi_get_state(stru
+ 					 FIELD_GET(SGMII_LPA, adv));
+ }
+ 
+-static int mtk_pcs_lynxi_config(struct phylink_pcs *pcs, unsigned int mode,
++static int mtk_pcs_lynxi_config(struct phylink_pcs *pcs, unsigned int neg_mode,
+ 				phy_interface_t interface,
+ 				const unsigned long *advertising,
+ 				bool permit_pause_to_mac)
+ {
+ 	struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs);
+-	bool mode_changed = false, changed, use_an;
++	bool mode_changed = false, changed;
+ 	unsigned int rgc3, sgm_mode, bmcr;
+ 	int advertise, link_timer;
+ 
+@@ -121,30 +121,22 @@ static int mtk_pcs_lynxi_config(struct p
+ 	 * we assume that fixes it's speed at bitrate = line rate (in
+ 	 * other words, 1000Mbps or 2500Mbps).
+ 	 */
+-	if (interface == PHY_INTERFACE_MODE_SGMII) {
++	if (interface == PHY_INTERFACE_MODE_SGMII)
+ 		sgm_mode = SGMII_IF_MODE_SGMII;
+-		if (phylink_autoneg_inband(mode)) {
+-			sgm_mode |= SGMII_REMOTE_FAULT_DIS |
+-				    SGMII_SPEED_DUPLEX_AN;
+-			use_an = true;
+-		} else {
+-			use_an = false;
+-		}
+-	} else if (phylink_autoneg_inband(mode)) {
+-		/* 1000base-X or 2500base-X autoneg */
+-		sgm_mode = SGMII_REMOTE_FAULT_DIS;
+-		use_an = linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
+-					   advertising);
+-	} else {
++	else
+ 		/* 1000base-X or 2500base-X without autoneg */
+ 		sgm_mode = 0;
+-		use_an = false;
+-	}
+ 
+-	if (use_an)
++	if (neg_mode & PHYLINK_PCS_NEG_INBAND)
++		sgm_mode |= SGMII_REMOTE_FAULT_DIS;
++
++	if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
++		if (interface == PHY_INTERFACE_MODE_SGMII)
++			sgm_mode |= SGMII_SPEED_DUPLEX_AN;
+ 		bmcr = BMCR_ANENABLE;
+-	else
++	} else {
+ 		bmcr = 0;
++	}
+ 
+ 	if (mpcs->interface != interface) {
+ 		link_timer = phylink_get_link_timer_ns(interface);
+@@ -216,14 +208,15 @@ static void mtk_pcs_lynxi_restart_an(str
+ 	regmap_set_bits(mpcs->regmap, SGMSYS_PCS_CONTROL_1, BMCR_ANRESTART);
+ }
+ 
+-static void mtk_pcs_lynxi_link_up(struct phylink_pcs *pcs, unsigned int mode,
++static void mtk_pcs_lynxi_link_up(struct phylink_pcs *pcs,
++				  unsigned int neg_mode,
+ 				  phy_interface_t interface, int speed,
+ 				  int duplex)
+ {
+ 	struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs);
+ 	unsigned int sgm_mode;
+ 
+-	if (!phylink_autoneg_inband(mode)) {
++	if (neg_mode != PHYLINK_PCS_NEG_INBAND_ENABLED) {
+ 		/* Force the speed and duplex setting */
+ 		if (speed == SPEED_10)
+ 			sgm_mode = SGMII_SPEED_10;
+@@ -286,6 +279,7 @@ struct phylink_pcs *mtk_pcs_lynxi_create
+ 	mpcs->regmap = regmap;
+ 	mpcs->flags = flags;
+ 	mpcs->pcs.ops = &mtk_pcs_lynxi_ops;
++	mpcs->pcs.neg_mode = true;
+ 	mpcs->pcs.poll = true;
+ 	mpcs->interface = PHY_INTERFACE_MODE_NA;
+ 
diff --git a/target/linux/generic/backport-6.1/715-28-v6.4-net-pcs-xpcs-use-Autoneg-bit-rather-than-an_enabled.patch b/target/linux/generic/backport-6.1/715-28-v6.4-net-pcs-xpcs-use-Autoneg-bit-rather-than-an_enabled.patch
new file mode 100644
index 00000000000000..3dd22d29160fed
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-28-v6.4-net-pcs-xpcs-use-Autoneg-bit-rather-than-an_enabled.patch
@@ -0,0 +1,55 @@
+From 459fd2f11204c962e3153020f4f56748e0e10afb Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Tue, 21 Mar 2023 15:58:49 +0000
+Subject: [PATCH] net: pcs: xpcs: use Autoneg bit rather than an_enabled
+
+The Autoneg bit in the advertising bitmap and state->an_enabled are
+always identical. Thus, we will be removing state->an_enabled.
+
+Use the Autoneg bit in the advertising bitmap to indicate whether
+autonegotiation should be used, rather than using the an_enabled
+member which will be going away.
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Simon Horman <simon.horman@corigine.com>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/pcs/pcs-xpcs.c | 10 +++++++---
+ 1 file changed, 7 insertions(+), 3 deletions(-)
+
+--- a/drivers/net/pcs/pcs-xpcs.c
++++ b/drivers/net/pcs/pcs-xpcs.c
+@@ -931,6 +931,7 @@ static int xpcs_get_state_c73(struct dw_
+ 			      struct phylink_link_state *state,
+ 			      const struct xpcs_compat *compat)
+ {
++	bool an_enabled;
+ 	int ret;
+ 
+ 	/* Link needs to be read first ... */
+@@ -948,11 +949,13 @@ static int xpcs_get_state_c73(struct dw_
+ 		return xpcs_do_config(xpcs, state->interface, MLO_AN_INBAND, NULL);
+ 	}
+ 
+-	if (state->an_enabled && xpcs_aneg_done_c73(xpcs, state, compat)) {
++	an_enabled = linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
++				       state->advertising);
++	if (an_enabled && xpcs_aneg_done_c73(xpcs, state, compat)) {
+ 		state->an_complete = true;
+ 		xpcs_read_lpa_c73(xpcs, state);
+ 		xpcs_resolve_lpa_c73(xpcs, state);
+-	} else if (state->an_enabled) {
++	} else if (an_enabled) {
+ 		state->link = 0;
+ 	} else if (state->link) {
+ 		xpcs_resolve_pma(xpcs, state);
+@@ -1007,7 +1010,8 @@ static int xpcs_get_state_c37_1000basex(
+ {
+ 	int lpa, bmsr;
+ 
+-	if (state->an_enabled) {
++	if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
++			      state->advertising)) {
+ 		/* Reset link state */
+ 		state->link = false;
+ 
diff --git a/target/linux/generic/backport-6.1/715-29-v6.4-net-pcs-xpcs-fix-incorrect-number-of-interfaces.patch b/target/linux/generic/backport-6.1/715-29-v6.4-net-pcs-xpcs-fix-incorrect-number-of-interfaces.patch
new file mode 100644
index 00000000000000..7cae8515fa1e8d
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-29-v6.4-net-pcs-xpcs-fix-incorrect-number-of-interfaces.patch
@@ -0,0 +1,30 @@
+From 43fb622d91a9f408322735d2f736495c1009f575 Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Tue, 9 May 2023 12:50:04 +0100
+Subject: [PATCH] net: pcs: xpcs: fix incorrect number of interfaces
+
+In synopsys_xpcs_compat[], the DW_XPCS_2500BASEX entry was setting
+the number of interfaces using the xpcs_2500basex_features array
+rather than xpcs_2500basex_interfaces. This causes us to overflow
+the array of interfaces. Fix this.
+
+Fixes: f27abde3042a ("net: pcs: add 2500BASEX support for Intel mGbE controller")
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Reviewed-by: Leon Romanovsky <leonro@nvidia.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/pcs/pcs-xpcs.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/net/pcs/pcs-xpcs.c
++++ b/drivers/net/pcs/pcs-xpcs.c
+@@ -1211,7 +1211,7 @@ static const struct xpcs_compat synopsys
+ 	[DW_XPCS_2500BASEX] = {
+ 		.supported = xpcs_2500basex_features,
+ 		.interface = xpcs_2500basex_interfaces,
+-		.num_interfaces = ARRAY_SIZE(xpcs_2500basex_features),
++		.num_interfaces = ARRAY_SIZE(xpcs_2500basex_interfaces),
+ 		.an_mode = DW_2500BASEX,
+ 	},
+ };
diff --git a/target/linux/generic/backport-6.1/715-v6.9-01-net-phy-qcom-qca808x-fix-logic-error-in-LED-brightne.patch b/target/linux/generic/backport-6.1/715-v6.9-01-net-phy-qcom-qca808x-fix-logic-error-in-LED-brightne.patch
new file mode 100644
index 00000000000000..0a7b5358f13607
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-v6.9-01-net-phy-qcom-qca808x-fix-logic-error-in-LED-brightne.patch
@@ -0,0 +1,36 @@
+From f2ec98566775dd4341ec1dcf93aa5859c60de826 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Thu, 1 Feb 2024 14:46:00 +0100
+Subject: [PATCH 1/2] net: phy: qcom: qca808x: fix logic error in LED
+ brightness set
+
+In switching to using phy_modify_mmd and a more short version of the
+LED ON/OFF condition in later revision, it was made a logic error where
+
+value ? QCA808X_LED_FORCE_ON : QCA808X_LED_FORCE_OFF is always true as
+value is always OR with QCA808X_LED_FORCE_EN due to missing ()
+resulting in the testing condition being QCA808X_LED_FORCE_EN | value.
+
+Add the () to apply the correct condition and restore correct
+functionality of the brightness ON/OFF.
+
+Fixes: 7196062b64ee ("net: phy: at803x: add LED support for qca808x")
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/qcom/qca808x.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/phy/qcom/qca808x.c
++++ b/drivers/net/phy/qcom/qca808x.c
+@@ -820,8 +820,8 @@ static int qca808x_led_brightness_set(st
+ 
+ 	return phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
+ 			      QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_MODE_MASK,
+-			      QCA808X_LED_FORCE_EN | value ? QCA808X_LED_FORCE_ON :
+-							     QCA808X_LED_FORCE_OFF);
++			      QCA808X_LED_FORCE_EN | (value ? QCA808X_LED_FORCE_ON :
++							     QCA808X_LED_FORCE_OFF));
+ }
+ 
+ static int qca808x_led_blink_set(struct phy_device *phydev, u8 index,
diff --git a/target/linux/generic/backport-6.1/715-v6.9-02-net-phy-qcom-qca808x-default-to-LED-active-High-if-n.patch b/target/linux/generic/backport-6.1/715-v6.9-02-net-phy-qcom-qca808x-default-to-LED-active-High-if-n.patch
new file mode 100644
index 00000000000000..e32ed7f7772415
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-v6.9-02-net-phy-qcom-qca808x-default-to-LED-active-High-if-n.patch
@@ -0,0 +1,41 @@
+From f203c8c77c7616c099647636f4c67d59a45fe8a2 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Thu, 1 Feb 2024 14:46:01 +0100
+Subject: [PATCH 2/2] net: phy: qcom: qca808x: default to LED active High if
+ not set
+
+qca808x PHY provide support for the led_polarity_set OP to configure
+and apply the active-low property but on PHY reset, the Active High bit
+is not set resulting in the LED driven as active-low.
+
+To fix this, check if active-low is not set in DT and enable Active High
+polarity by default to restore correct funcionality of the LED.
+
+Fixes: 7196062b64ee ("net: phy: at803x: add LED support for qca808x")
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/qcom/qca808x.c | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+--- a/drivers/net/phy/qcom/qca808x.c
++++ b/drivers/net/phy/qcom/qca808x.c
+@@ -290,8 +290,18 @@ static int qca808x_probe(struct phy_devi
+ 
+ static int qca808x_config_init(struct phy_device *phydev)
+ {
++	struct qca808x_priv *priv = phydev->priv;
+ 	int ret;
+ 
++	/* Default to LED Active High if active-low not in DT */
++	if (priv->led_polarity_mode == -1) {
++		ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN,
++				       QCA808X_MMD7_LED_POLARITY_CTRL,
++				       QCA808X_LED_ACTIVE_HIGH);
++		if (ret)
++			return ret;
++	}
++
+ 	/* Active adc&vga on 802.3az for the link 1000M and 100M */
+ 	ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_ADDR_CLD_CTRL7,
+ 			     QCA808X_8023AZ_AFE_CTRL_MASK, QCA808X_8023AZ_AFE_EN);
diff --git a/target/linux/generic/backport-6.1/716-v6.9-02-net-phy-add-support-for-scanning-PHY-in-PHY-packages.patch b/target/linux/generic/backport-6.1/716-v6.9-02-net-phy-add-support-for-scanning-PHY-in-PHY-packages.patch
new file mode 100644
index 00000000000000..b355031aa5ebcc
--- /dev/null
+++ b/target/linux/generic/backport-6.1/716-v6.9-02-net-phy-add-support-for-scanning-PHY-in-PHY-packages.patch
@@ -0,0 +1,211 @@
+From 385ef48f468696d6d172eb367656a3466fa0408d Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Tue, 6 Feb 2024 18:31:05 +0100
+Subject: [PATCH 02/10] net: phy: add support for scanning PHY in PHY packages
+ nodes
+
+Add support for scanning PHY in PHY package nodes. PHY packages nodes
+are just container for actual PHY on the MDIO bus.
+
+Their PHY address defined in the PHY package node are absolute and
+reflect the address on the MDIO bus.
+
+mdio_bus.c and of_mdio.c is updated to now support and parse also
+PHY package subnode by checking if the node name match
+"ethernet-phy-package".
+
+As PHY package reg is mandatory and each PHY in the PHY package must
+have a reg, every invalid PHY Package node is ignored and will be
+skipped by the autoscan fallback.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/mdio/of_mdio.c | 79 +++++++++++++++++++++++++++-----------
+ drivers/net/phy/mdio_bus.c | 44 +++++++++++++++++----
+ 2 files changed, 92 insertions(+), 31 deletions(-)
+
+--- a/drivers/net/mdio/of_mdio.c
++++ b/drivers/net/mdio/of_mdio.c
+@@ -138,6 +138,53 @@ bool of_mdiobus_child_is_phy(struct devi
+ }
+ EXPORT_SYMBOL(of_mdiobus_child_is_phy);
+ 
++static int __of_mdiobus_parse_phys(struct mii_bus *mdio, struct device_node *np,
++				   bool *scanphys)
++{
++	struct device_node *child;
++	int addr, rc = 0;
++
++	/* Loop over the child nodes and register a phy_device for each phy */
++	for_each_available_child_of_node(np, child) {
++		if (of_node_name_eq(child, "ethernet-phy-package")) {
++			/* Ignore invalid ethernet-phy-package node */
++			if (!of_find_property(child, "reg", NULL))
++				continue;
++
++			rc = __of_mdiobus_parse_phys(mdio, child, NULL);
++			if (rc && rc != -ENODEV)
++				goto exit;
++
++			continue;
++		}
++
++		addr = of_mdio_parse_addr(&mdio->dev, child);
++		if (addr < 0) {
++			/* Skip scanning for invalid ethernet-phy-package node */
++			if (scanphys)
++				*scanphys = true;
++			continue;
++		}
++
++		if (of_mdiobus_child_is_phy(child))
++			rc = of_mdiobus_register_phy(mdio, child, addr);
++		else
++			rc = of_mdiobus_register_device(mdio, child, addr);
++
++		if (rc == -ENODEV)
++			dev_err(&mdio->dev,
++				"MDIO device at address %d is missing.\n",
++				addr);
++		else if (rc)
++			goto exit;
++	}
++
++	return 0;
++exit:
++	of_node_put(child);
++	return rc;
++}
++
+ /**
+  * __of_mdiobus_register - Register mii_bus and create PHYs from the device tree
+  * @mdio: pointer to mii_bus structure
+@@ -179,33 +226,18 @@ int __of_mdiobus_register(struct mii_bus
+ 		return rc;
+ 
+ 	/* Loop over the child nodes and register a phy_device for each phy */
+-	for_each_available_child_of_node(np, child) {
+-		addr = of_mdio_parse_addr(&mdio->dev, child);
+-		if (addr < 0) {
+-			scanphys = true;
+-			continue;
+-		}
+-
+-		if (of_mdiobus_child_is_phy(child))
+-			rc = of_mdiobus_register_phy(mdio, child, addr);
+-		else
+-			rc = of_mdiobus_register_device(mdio, child, addr);
+-
+-		if (rc == -ENODEV)
+-			dev_err(&mdio->dev,
+-				"MDIO device at address %d is missing.\n",
+-				addr);
+-		else if (rc)
+-			goto unregister;
+-	}
++	rc = __of_mdiobus_parse_phys(mdio, np, &scanphys);
++	if (rc)
++		goto unregister;
+ 
+ 	if (!scanphys)
+ 		return 0;
+ 
+ 	/* auto scan for PHYs with empty reg property */
+ 	for_each_available_child_of_node(np, child) {
+-		/* Skip PHYs with reg property set */
+-		if (of_find_property(child, "reg", NULL))
++		/* Skip PHYs with reg property set or ethernet-phy-package node */
++		if (of_find_property(child, "reg", NULL) ||
++		    of_node_name_eq(child, "ethernet-phy-package"))
+ 			continue;
+ 
+ 		for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
+@@ -226,15 +258,16 @@ int __of_mdiobus_register(struct mii_bus
+ 				if (!rc)
+ 					break;
+ 				if (rc != -ENODEV)
+-					goto unregister;
++					goto put_unregister;
+ 			}
+ 		}
+ 	}
+ 
+ 	return 0;
+ 
+-unregister:
++put_unregister:
+ 	of_node_put(child);
++unregister:
+ 	mdiobus_unregister(mdio);
+ 	return rc;
+ }
+--- a/drivers/net/phy/mdio_bus.c
++++ b/drivers/net/phy/mdio_bus.c
+@@ -448,19 +448,34 @@ EXPORT_SYMBOL(of_mdio_find_bus);
+  * found, set the of_node pointer for the mdio device. This allows
+  * auto-probed phy devices to be supplied with information passed in
+  * via DT.
++ * If a PHY package is found, PHY is searched also there.
+  */
+-static void of_mdiobus_link_mdiodev(struct mii_bus *bus,
+-				    struct mdio_device *mdiodev)
++static int of_mdiobus_find_phy(struct device *dev, struct mdio_device *mdiodev,
++			       struct device_node *np)
+ {
+-	struct device *dev = &mdiodev->dev;
+ 	struct device_node *child;
+ 
+-	if (dev->of_node || !bus->dev.of_node)
+-		return;
+-
+-	for_each_available_child_of_node(bus->dev.of_node, child) {
++	for_each_available_child_of_node(np, child) {
+ 		int addr;
+ 
++		if (of_node_name_eq(child, "ethernet-phy-package")) {
++			/* Validate PHY package reg presence */
++			if (!of_find_property(child, "reg", NULL)) {
++				of_node_put(child);
++				return -EINVAL;
++			}
++
++			if (!of_mdiobus_find_phy(dev, mdiodev, child)) {
++				/* The refcount for the PHY package will be
++				 * incremented later when PHY join the Package.
++				 */
++				of_node_put(child);
++				return 0;
++			}
++
++			continue;
++		}
++
+ 		addr = of_mdio_parse_addr(dev, child);
+ 		if (addr < 0)
+ 			continue;
+@@ -470,9 +485,22 @@ static void of_mdiobus_link_mdiodev(stru
+ 			/* The refcount on "child" is passed to the mdio
+ 			 * device. Do _not_ use of_node_put(child) here.
+ 			 */
+-			return;
++			return 0;
+ 		}
+ 	}
++
++	return -ENODEV;
++}
++
++static void of_mdiobus_link_mdiodev(struct mii_bus *bus,
++				    struct mdio_device *mdiodev)
++{
++	struct device *dev = &mdiodev->dev;
++
++	if (dev->of_node || !bus->dev.of_node)
++		return;
++
++	of_mdiobus_find_phy(dev, mdiodev, bus->dev.of_node);
+ }
+ #else /* !IS_ENABLED(CONFIG_OF_MDIO) */
+ static inline void of_mdiobus_link_mdiodev(struct mii_bus *mdio,
diff --git a/target/linux/generic/backport-6.1/716-v6.9-03-net-phy-add-devm-of_phy_package_join-helper.patch b/target/linux/generic/backport-6.1/716-v6.9-03-net-phy-add-devm-of_phy_package_join-helper.patch
new file mode 100644
index 00000000000000..3c7bf6c132ff57
--- /dev/null
+++ b/target/linux/generic/backport-6.1/716-v6.9-03-net-phy-add-devm-of_phy_package_join-helper.patch
@@ -0,0 +1,185 @@
+From 471e8fd3afcef5a9f9089f0bd21965ad9ba35c91 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Tue, 6 Feb 2024 18:31:06 +0100
+Subject: [PATCH 03/10] net: phy: add devm/of_phy_package_join helper
+
+Add devm/of_phy_package_join helper to join PHYs in a PHY package. These
+are variant of the manual phy_package_join with the difference that
+these will use DT nodes to derive the base_addr instead of manually
+passing an hardcoded value.
+
+An additional value is added in phy_package_shared, "np" to reference
+the PHY package node pointer in specific PHY driver probe_once and
+config_init_once functions to make use of additional specific properties
+defined in the PHY package node in DT.
+
+The np value is filled only with of_phy_package_join if a valid PHY
+package node is found. A valid PHY package node must have the node name
+set to "ethernet-phy-package".
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/phy_device.c | 96 ++++++++++++++++++++++++++++++++++++
+ include/linux/phy.h          |  6 +++
+ 2 files changed, 102 insertions(+)
+
+--- a/drivers/net/phy/phy_device.c
++++ b/drivers/net/phy/phy_device.c
+@@ -1648,6 +1648,7 @@ int phy_package_join(struct phy_device *
+ 			shared->priv_size = priv_size;
+ 		}
+ 		shared->base_addr = base_addr;
++		shared->np = NULL;
+ 		refcount_set(&shared->refcnt, 1);
+ 		bus->shared[base_addr] = shared;
+ 	} else {
+@@ -1671,6 +1672,63 @@ err_unlock:
+ EXPORT_SYMBOL_GPL(phy_package_join);
+ 
+ /**
++ * of_phy_package_join - join a common PHY group in PHY package
++ * @phydev: target phy_device struct
++ * @priv_size: if non-zero allocate this amount of bytes for private data
++ *
++ * This is a variant of phy_package_join for PHY package defined in DT.
++ *
++ * The parent node of the @phydev is checked as a valid PHY package node
++ * structure (by matching the node name "ethernet-phy-package") and the
++ * base_addr for the PHY package is passed to phy_package_join.
++ *
++ * With this configuration the shared struct will also have the np value
++ * filled to use additional DT defined properties in PHY specific
++ * probe_once and config_init_once PHY package OPs.
++ *
++ * Returns < 0 on error, 0 on success. Esp. calling phy_package_join()
++ * with the same cookie but a different priv_size is an error. Or a parent
++ * node is not detected or is not valid or doesn't match the expected node
++ * name for PHY package.
++ */
++int of_phy_package_join(struct phy_device *phydev, size_t priv_size)
++{
++	struct device_node *node = phydev->mdio.dev.of_node;
++	struct device_node *package_node;
++	u32 base_addr;
++	int ret;
++
++	if (!node)
++		return -EINVAL;
++
++	package_node = of_get_parent(node);
++	if (!package_node)
++		return -EINVAL;
++
++	if (!of_node_name_eq(package_node, "ethernet-phy-package")) {
++		ret = -EINVAL;
++		goto exit;
++	}
++
++	if (of_property_read_u32(package_node, "reg", &base_addr)) {
++		ret = -EINVAL;
++		goto exit;
++	}
++
++	ret = phy_package_join(phydev, base_addr, priv_size);
++	if (ret)
++		goto exit;
++
++	phydev->shared->np = package_node;
++
++	return 0;
++exit:
++	of_node_put(package_node);
++	return ret;
++}
++EXPORT_SYMBOL_GPL(of_phy_package_join);
++
++/**
+  * phy_package_leave - leave a common PHY group
+  * @phydev: target phy_device struct
+  *
+@@ -1686,6 +1744,10 @@ void phy_package_leave(struct phy_device
+ 	if (!shared)
+ 		return;
+ 
++	/* Decrease the node refcount on leave if present */
++	if (shared->np)
++		of_node_put(shared->np);
++
+ 	if (refcount_dec_and_mutex_lock(&shared->refcnt, &bus->shared_lock)) {
+ 		bus->shared[shared->base_addr] = NULL;
+ 		mutex_unlock(&bus->shared_lock);
+@@ -1739,6 +1801,40 @@ int devm_phy_package_join(struct device
+ EXPORT_SYMBOL_GPL(devm_phy_package_join);
+ 
+ /**
++ * devm_of_phy_package_join - resource managed of_phy_package_join()
++ * @dev: device that is registering this PHY package
++ * @phydev: target phy_device struct
++ * @priv_size: if non-zero allocate this amount of bytes for private data
++ *
++ * Managed of_phy_package_join(). Shared storage fetched by this function,
++ * phy_package_leave() is automatically called on driver detach. See
++ * of_phy_package_join() for more information.
++ */
++int devm_of_phy_package_join(struct device *dev, struct phy_device *phydev,
++			     size_t priv_size)
++{
++	struct phy_device **ptr;
++	int ret;
++
++	ptr = devres_alloc(devm_phy_package_leave, sizeof(*ptr),
++			   GFP_KERNEL);
++	if (!ptr)
++		return -ENOMEM;
++
++	ret = of_phy_package_join(phydev, priv_size);
++
++	if (!ret) {
++		*ptr = phydev;
++		devres_add(dev, ptr);
++	} else {
++		devres_free(ptr);
++	}
++
++	return ret;
++}
++EXPORT_SYMBOL_GPL(devm_of_phy_package_join);
++
++/**
+  * phy_detach - detach a PHY device from its network device
+  * @phydev: target phy_device struct
+  *
+--- a/include/linux/phy.h
++++ b/include/linux/phy.h
+@@ -321,6 +321,7 @@ struct mdio_bus_stats {
+  * struct phy_package_shared - Shared information in PHY packages
+  * @base_addr: Base PHY address of PHY package used to combine PHYs
+  *   in one package and for offset calculation of phy_package_read/write
++ * @np: Pointer to the Device Node if PHY package defined in DT
+  * @refcnt: Number of PHYs connected to this shared data
+  * @flags: Initialization of PHY package
+  * @priv_size: Size of the shared private data @priv
+@@ -332,6 +333,8 @@ struct mdio_bus_stats {
+  */
+ struct phy_package_shared {
+ 	u8 base_addr;
++	/* With PHY package defined in DT this points to the PHY package node */
++	struct device_node *np;
+ 	refcount_t refcnt;
+ 	unsigned long flags;
+ 	size_t priv_size;
+@@ -1793,9 +1796,12 @@ int phy_ethtool_set_link_ksettings(struc
+ 				   const struct ethtool_link_ksettings *cmd);
+ int phy_ethtool_nway_reset(struct net_device *ndev);
+ int phy_package_join(struct phy_device *phydev, int base_addr, size_t priv_size);
++int of_phy_package_join(struct phy_device *phydev, size_t priv_size);
+ void phy_package_leave(struct phy_device *phydev);
+ int devm_phy_package_join(struct device *dev, struct phy_device *phydev,
+ 			  int base_addr, size_t priv_size);
++int devm_of_phy_package_join(struct device *dev, struct phy_device *phydev,
++			     size_t priv_size);
+ 
+ #if IS_ENABLED(CONFIG_PHYLIB)
+ int __init mdio_bus_init(void);
diff --git a/target/linux/generic/backport-6.1/716-v6.9-04-net-phy-qcom-move-more-function-to-shared-library.patch b/target/linux/generic/backport-6.1/716-v6.9-04-net-phy-qcom-move-more-function-to-shared-library.patch
new file mode 100644
index 00000000000000..e935725630c445
--- /dev/null
+++ b/target/linux/generic/backport-6.1/716-v6.9-04-net-phy-qcom-move-more-function-to-shared-library.patch
@@ -0,0 +1,583 @@
+From 737eb75a815f9c08dcbb6631db57f4f4b0540a5b Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Tue, 6 Feb 2024 18:31:07 +0100
+Subject: [PATCH 04/10] net: phy: qcom: move more function to shared library
+
+Move more function to shared library in preparation for introduction of
+new PHY Family qca807x that will make use of both functions from at803x
+and qca808x as it's a transition PHY with some implementation of at803x
+and some from the new qca808x.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/qcom/at803x.c       |  35 -----
+ drivers/net/phy/qcom/qca808x.c      | 205 ----------------------------
+ drivers/net/phy/qcom/qcom-phy-lib.c | 193 ++++++++++++++++++++++++++
+ drivers/net/phy/qcom/qcom.h         |  51 +++++++
+ 4 files changed, 244 insertions(+), 240 deletions(-)
+
+--- a/drivers/net/phy/qcom/at803x.c
++++ b/drivers/net/phy/qcom/at803x.c
+@@ -504,41 +504,6 @@ static void at803x_link_change_notify(st
+ 	}
+ }
+ 
+-static int at803x_read_status(struct phy_device *phydev)
+-{
+-	struct at803x_ss_mask ss_mask = { 0 };
+-	int err, old_link = phydev->link;
+-
+-	/* Update the link, but return if there was an error */
+-	err = genphy_update_link(phydev);
+-	if (err)
+-		return err;
+-
+-	/* why bother the PHY if nothing can have changed */
+-	if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link)
+-		return 0;
+-
+-	phydev->speed = SPEED_UNKNOWN;
+-	phydev->duplex = DUPLEX_UNKNOWN;
+-	phydev->pause = 0;
+-	phydev->asym_pause = 0;
+-
+-	err = genphy_read_lpa(phydev);
+-	if (err < 0)
+-		return err;
+-
+-	ss_mask.speed_mask = AT803X_SS_SPEED_MASK;
+-	ss_mask.speed_shift = __bf_shf(AT803X_SS_SPEED_MASK);
+-	err = at803x_read_specific_status(phydev, ss_mask);
+-	if (err < 0)
+-		return err;
+-
+-	if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete)
+-		phy_resolve_aneg_pause(phydev);
+-
+-	return 0;
+-}
+-
+ static int at803x_config_aneg(struct phy_device *phydev)
+ {
+ 	struct at803x_priv *priv = phydev->priv;
+--- a/drivers/net/phy/qcom/qca808x.c
++++ b/drivers/net/phy/qcom/qca808x.c
+@@ -2,7 +2,6 @@
+ 
+ #include <linux/phy.h>
+ #include <linux/module.h>
+-#include <linux/ethtool_netlink.h>
+ 
+ #include "qcom.h"
+ 
+@@ -63,55 +62,6 @@
+ #define QCA808X_DBG_AN_TEST			0xb
+ #define QCA808X_HIBERNATION_EN			BIT(15)
+ 
+-#define QCA808X_CDT_ENABLE_TEST			BIT(15)
+-#define QCA808X_CDT_INTER_CHECK_DIS		BIT(13)
+-#define QCA808X_CDT_STATUS			BIT(11)
+-#define QCA808X_CDT_LENGTH_UNIT			BIT(10)
+-
+-#define QCA808X_MMD3_CDT_STATUS			0x8064
+-#define QCA808X_MMD3_CDT_DIAG_PAIR_A		0x8065
+-#define QCA808X_MMD3_CDT_DIAG_PAIR_B		0x8066
+-#define QCA808X_MMD3_CDT_DIAG_PAIR_C		0x8067
+-#define QCA808X_MMD3_CDT_DIAG_PAIR_D		0x8068
+-#define QCA808X_CDT_DIAG_LENGTH_SAME_SHORT	GENMASK(15, 8)
+-#define QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT	GENMASK(7, 0)
+-
+-#define QCA808X_CDT_CODE_PAIR_A			GENMASK(15, 12)
+-#define QCA808X_CDT_CODE_PAIR_B			GENMASK(11, 8)
+-#define QCA808X_CDT_CODE_PAIR_C			GENMASK(7, 4)
+-#define QCA808X_CDT_CODE_PAIR_D			GENMASK(3, 0)
+-
+-#define QCA808X_CDT_STATUS_STAT_TYPE		GENMASK(1, 0)
+-#define QCA808X_CDT_STATUS_STAT_FAIL		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 0)
+-#define QCA808X_CDT_STATUS_STAT_NORMAL		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 1)
+-#define QCA808X_CDT_STATUS_STAT_SAME_OPEN	FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 2)
+-#define QCA808X_CDT_STATUS_STAT_SAME_SHORT	FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 3)
+-
+-#define QCA808X_CDT_STATUS_STAT_MDI		GENMASK(3, 2)
+-#define QCA808X_CDT_STATUS_STAT_MDI1		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 1)
+-#define QCA808X_CDT_STATUS_STAT_MDI2		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 2)
+-#define QCA808X_CDT_STATUS_STAT_MDI3		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 3)
+-
+-/* NORMAL are MDI with type set to 0 */
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL	QCA808X_CDT_STATUS_STAT_MDI1
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN		(QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
+-									 QCA808X_CDT_STATUS_STAT_MDI1)
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT	(QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
+-									 QCA808X_CDT_STATUS_STAT_MDI1)
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL	QCA808X_CDT_STATUS_STAT_MDI2
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN		(QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
+-									 QCA808X_CDT_STATUS_STAT_MDI2)
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT	(QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
+-									 QCA808X_CDT_STATUS_STAT_MDI2)
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL	QCA808X_CDT_STATUS_STAT_MDI3
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN		(QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
+-									 QCA808X_CDT_STATUS_STAT_MDI3)
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT	(QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
+-									 QCA808X_CDT_STATUS_STAT_MDI3)
+-
+-/* Added for reference of existence but should be handled by wait_for_completion already */
+-#define QCA808X_CDT_STATUS_STAT_BUSY		(BIT(1) | BIT(3))
+-
+ #define QCA808X_MMD7_LED_GLOBAL			0x8073
+ #define QCA808X_LED_BLINK_1			GENMASK(11, 6)
+ #define QCA808X_LED_BLINK_2			GENMASK(5, 0)
+@@ -406,86 +356,6 @@ static int qca808x_soft_reset(struct phy
+ 	return ret;
+ }
+ 
+-static bool qca808x_cdt_fault_length_valid(int cdt_code)
+-{
+-	switch (cdt_code) {
+-	case QCA808X_CDT_STATUS_STAT_SAME_SHORT:
+-	case QCA808X_CDT_STATUS_STAT_SAME_OPEN:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT:
+-		return true;
+-	default:
+-		return false;
+-	}
+-}
+-
+-static int qca808x_cable_test_result_trans(int cdt_code)
+-{
+-	switch (cdt_code) {
+-	case QCA808X_CDT_STATUS_STAT_NORMAL:
+-		return ETHTOOL_A_CABLE_RESULT_CODE_OK;
+-	case QCA808X_CDT_STATUS_STAT_SAME_SHORT:
+-		return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
+-	case QCA808X_CDT_STATUS_STAT_SAME_OPEN:
+-		return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT:
+-		return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;
+-	case QCA808X_CDT_STATUS_STAT_FAIL:
+-	default:
+-		return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
+-	}
+-}
+-
+-static int qca808x_cdt_fault_length(struct phy_device *phydev, int pair,
+-				    int result)
+-{
+-	int val;
+-	u32 cdt_length_reg = 0;
+-
+-	switch (pair) {
+-	case ETHTOOL_A_CABLE_PAIR_A:
+-		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_A;
+-		break;
+-	case ETHTOOL_A_CABLE_PAIR_B:
+-		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_B;
+-		break;
+-	case ETHTOOL_A_CABLE_PAIR_C:
+-		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_C;
+-		break;
+-	case ETHTOOL_A_CABLE_PAIR_D:
+-		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_D;
+-		break;
+-	default:
+-		return -EINVAL;
+-	}
+-
+-	val = phy_read_mmd(phydev, MDIO_MMD_PCS, cdt_length_reg);
+-	if (val < 0)
+-		return val;
+-
+-	if (result == ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT)
+-		val = FIELD_GET(QCA808X_CDT_DIAG_LENGTH_SAME_SHORT, val);
+-	else
+-		val = FIELD_GET(QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT, val);
+-
+-	return at803x_cdt_fault_length(val);
+-}
+-
+ static int qca808x_cable_test_start(struct phy_device *phydev)
+ {
+ 	int ret;
+@@ -526,81 +396,6 @@ static int qca808x_cable_test_start(stru
+ 
+ 	return 0;
+ }
+-
+-static int qca808x_cable_test_get_pair_status(struct phy_device *phydev, u8 pair,
+-					      u16 status)
+-{
+-	int length, result;
+-	u16 pair_code;
+-
+-	switch (pair) {
+-	case ETHTOOL_A_CABLE_PAIR_A:
+-		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_A, status);
+-		break;
+-	case ETHTOOL_A_CABLE_PAIR_B:
+-		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_B, status);
+-		break;
+-	case ETHTOOL_A_CABLE_PAIR_C:
+-		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_C, status);
+-		break;
+-	case ETHTOOL_A_CABLE_PAIR_D:
+-		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_D, status);
+-		break;
+-	default:
+-		return -EINVAL;
+-	}
+-
+-	result = qca808x_cable_test_result_trans(pair_code);
+-	ethnl_cable_test_result(phydev, pair, result);
+-
+-	if (qca808x_cdt_fault_length_valid(pair_code)) {
+-		length = qca808x_cdt_fault_length(phydev, pair, result);
+-		ethnl_cable_test_fault_length(phydev, pair, length);
+-	}
+-
+-	return 0;
+-}
+-
+-static int qca808x_cable_test_get_status(struct phy_device *phydev, bool *finished)
+-{
+-	int ret, val;
+-
+-	*finished = false;
+-
+-	val = QCA808X_CDT_ENABLE_TEST |
+-	      QCA808X_CDT_LENGTH_UNIT;
+-	ret = at803x_cdt_start(phydev, val);
+-	if (ret)
+-		return ret;
+-
+-	ret = at803x_cdt_wait_for_completion(phydev, QCA808X_CDT_ENABLE_TEST);
+-	if (ret)
+-		return ret;
+-
+-	val = phy_read_mmd(phydev, MDIO_MMD_PCS, QCA808X_MMD3_CDT_STATUS);
+-	if (val < 0)
+-		return val;
+-
+-	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_A, val);
+-	if (ret)
+-		return ret;
+-
+-	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_B, val);
+-	if (ret)
+-		return ret;
+-
+-	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_C, val);
+-	if (ret)
+-		return ret;
+-
+-	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_D, val);
+-	if (ret)
+-		return ret;
+-
+-	*finished = true;
+-
+-	return 0;
+-}
+ 
+ static int qca808x_get_features(struct phy_device *phydev)
+ {
+--- a/drivers/net/phy/qcom/qcom-phy-lib.c
++++ b/drivers/net/phy/qcom/qcom-phy-lib.c
+@@ -5,6 +5,7 @@
+ 
+ #include <linux/netdevice.h>
+ #include <linux/etherdevice.h>
++#include <linux/ethtool_netlink.h>
+ 
+ #include "qcom.h"
+ 
+@@ -311,6 +312,42 @@ int at803x_prepare_config_aneg(struct ph
+ }
+ EXPORT_SYMBOL_GPL(at803x_prepare_config_aneg);
+ 
++int at803x_read_status(struct phy_device *phydev)
++{
++	struct at803x_ss_mask ss_mask = { 0 };
++	int err, old_link = phydev->link;
++
++	/* Update the link, but return if there was an error */
++	err = genphy_update_link(phydev);
++	if (err)
++		return err;
++
++	/* why bother the PHY if nothing can have changed */
++	if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link)
++		return 0;
++
++	phydev->speed = SPEED_UNKNOWN;
++	phydev->duplex = DUPLEX_UNKNOWN;
++	phydev->pause = 0;
++	phydev->asym_pause = 0;
++
++	err = genphy_read_lpa(phydev);
++	if (err < 0)
++		return err;
++
++	ss_mask.speed_mask = AT803X_SS_SPEED_MASK;
++	ss_mask.speed_shift = __bf_shf(AT803X_SS_SPEED_MASK);
++	err = at803x_read_specific_status(phydev, ss_mask);
++	if (err < 0)
++		return err;
++
++	if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete)
++		phy_resolve_aneg_pause(phydev);
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(at803x_read_status);
++
+ static int at803x_get_downshift(struct phy_device *phydev, u8 *d)
+ {
+ 	int val;
+@@ -427,3 +464,159 @@ int at803x_cdt_wait_for_completion(struc
+ 	return ret < 0 ? ret : 0;
+ }
+ EXPORT_SYMBOL_GPL(at803x_cdt_wait_for_completion);
++
++static bool qca808x_cdt_fault_length_valid(int cdt_code)
++{
++	switch (cdt_code) {
++	case QCA808X_CDT_STATUS_STAT_SAME_SHORT:
++	case QCA808X_CDT_STATUS_STAT_SAME_OPEN:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT:
++		return true;
++	default:
++		return false;
++	}
++}
++
++static int qca808x_cable_test_result_trans(int cdt_code)
++{
++	switch (cdt_code) {
++	case QCA808X_CDT_STATUS_STAT_NORMAL:
++		return ETHTOOL_A_CABLE_RESULT_CODE_OK;
++	case QCA808X_CDT_STATUS_STAT_SAME_SHORT:
++		return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
++	case QCA808X_CDT_STATUS_STAT_SAME_OPEN:
++		return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT:
++		return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;
++	case QCA808X_CDT_STATUS_STAT_FAIL:
++	default:
++		return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
++	}
++}
++
++static int qca808x_cdt_fault_length(struct phy_device *phydev, int pair,
++				    int result)
++{
++	int val;
++	u32 cdt_length_reg = 0;
++
++	switch (pair) {
++	case ETHTOOL_A_CABLE_PAIR_A:
++		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_A;
++		break;
++	case ETHTOOL_A_CABLE_PAIR_B:
++		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_B;
++		break;
++	case ETHTOOL_A_CABLE_PAIR_C:
++		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_C;
++		break;
++	case ETHTOOL_A_CABLE_PAIR_D:
++		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_D;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	val = phy_read_mmd(phydev, MDIO_MMD_PCS, cdt_length_reg);
++	if (val < 0)
++		return val;
++
++	if (result == ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT)
++		val = FIELD_GET(QCA808X_CDT_DIAG_LENGTH_SAME_SHORT, val);
++	else
++		val = FIELD_GET(QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT, val);
++
++	return at803x_cdt_fault_length(val);
++}
++
++static int qca808x_cable_test_get_pair_status(struct phy_device *phydev, u8 pair,
++					      u16 status)
++{
++	int length, result;
++	u16 pair_code;
++
++	switch (pair) {
++	case ETHTOOL_A_CABLE_PAIR_A:
++		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_A, status);
++		break;
++	case ETHTOOL_A_CABLE_PAIR_B:
++		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_B, status);
++		break;
++	case ETHTOOL_A_CABLE_PAIR_C:
++		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_C, status);
++		break;
++	case ETHTOOL_A_CABLE_PAIR_D:
++		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_D, status);
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	result = qca808x_cable_test_result_trans(pair_code);
++	ethnl_cable_test_result(phydev, pair, result);
++
++	if (qca808x_cdt_fault_length_valid(pair_code)) {
++		length = qca808x_cdt_fault_length(phydev, pair, result);
++		ethnl_cable_test_fault_length(phydev, pair, length);
++	}
++
++	return 0;
++}
++
++int qca808x_cable_test_get_status(struct phy_device *phydev, bool *finished)
++{
++	int ret, val;
++
++	*finished = false;
++
++	val = QCA808X_CDT_ENABLE_TEST |
++	      QCA808X_CDT_LENGTH_UNIT;
++	ret = at803x_cdt_start(phydev, val);
++	if (ret)
++		return ret;
++
++	ret = at803x_cdt_wait_for_completion(phydev, QCA808X_CDT_ENABLE_TEST);
++	if (ret)
++		return ret;
++
++	val = phy_read_mmd(phydev, MDIO_MMD_PCS, QCA808X_MMD3_CDT_STATUS);
++	if (val < 0)
++		return val;
++
++	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_A, val);
++	if (ret)
++		return ret;
++
++	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_B, val);
++	if (ret)
++		return ret;
++
++	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_C, val);
++	if (ret)
++		return ret;
++
++	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_D, val);
++	if (ret)
++		return ret;
++
++	*finished = true;
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(qca808x_cable_test_get_status);
+--- a/drivers/net/phy/qcom/qcom.h
++++ b/drivers/net/phy/qcom/qcom.h
+@@ -54,6 +54,55 @@
+ #define AT803X_CDT_STATUS_STAT_MASK		GENMASK(9, 8)
+ #define AT803X_CDT_STATUS_DELTA_TIME_MASK	GENMASK(7, 0)
+ 
++#define QCA808X_CDT_ENABLE_TEST			BIT(15)
++#define QCA808X_CDT_INTER_CHECK_DIS		BIT(13)
++#define QCA808X_CDT_STATUS			BIT(11)
++#define QCA808X_CDT_LENGTH_UNIT			BIT(10)
++
++#define QCA808X_MMD3_CDT_STATUS			0x8064
++#define QCA808X_MMD3_CDT_DIAG_PAIR_A		0x8065
++#define QCA808X_MMD3_CDT_DIAG_PAIR_B		0x8066
++#define QCA808X_MMD3_CDT_DIAG_PAIR_C		0x8067
++#define QCA808X_MMD3_CDT_DIAG_PAIR_D		0x8068
++#define QCA808X_CDT_DIAG_LENGTH_SAME_SHORT	GENMASK(15, 8)
++#define QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT	GENMASK(7, 0)
++
++#define QCA808X_CDT_CODE_PAIR_A			GENMASK(15, 12)
++#define QCA808X_CDT_CODE_PAIR_B			GENMASK(11, 8)
++#define QCA808X_CDT_CODE_PAIR_C			GENMASK(7, 4)
++#define QCA808X_CDT_CODE_PAIR_D			GENMASK(3, 0)
++
++#define QCA808X_CDT_STATUS_STAT_TYPE		GENMASK(1, 0)
++#define QCA808X_CDT_STATUS_STAT_FAIL		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 0)
++#define QCA808X_CDT_STATUS_STAT_NORMAL		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 1)
++#define QCA808X_CDT_STATUS_STAT_SAME_OPEN	FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 2)
++#define QCA808X_CDT_STATUS_STAT_SAME_SHORT	FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 3)
++
++#define QCA808X_CDT_STATUS_STAT_MDI		GENMASK(3, 2)
++#define QCA808X_CDT_STATUS_STAT_MDI1		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 1)
++#define QCA808X_CDT_STATUS_STAT_MDI2		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 2)
++#define QCA808X_CDT_STATUS_STAT_MDI3		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 3)
++
++/* NORMAL are MDI with type set to 0 */
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL	QCA808X_CDT_STATUS_STAT_MDI1
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN		(QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
++									 QCA808X_CDT_STATUS_STAT_MDI1)
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT	(QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
++									 QCA808X_CDT_STATUS_STAT_MDI1)
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL	QCA808X_CDT_STATUS_STAT_MDI2
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN		(QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
++									 QCA808X_CDT_STATUS_STAT_MDI2)
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT	(QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
++									 QCA808X_CDT_STATUS_STAT_MDI2)
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL	QCA808X_CDT_STATUS_STAT_MDI3
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN		(QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
++									 QCA808X_CDT_STATUS_STAT_MDI3)
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT	(QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
++									 QCA808X_CDT_STATUS_STAT_MDI3)
++
++/* Added for reference of existence but should be handled by wait_for_completion already */
++#define QCA808X_CDT_STATUS_STAT_BUSY		(BIT(1) | BIT(3))
++
+ #define AT803X_LOC_MAC_ADDR_0_15_OFFSET		0x804C
+ #define AT803X_LOC_MAC_ADDR_16_31_OFFSET	0x804B
+ #define AT803X_LOC_MAC_ADDR_32_47_OFFSET	0x804A
+@@ -110,6 +159,7 @@ int at803x_read_specific_status(struct p
+ 				struct at803x_ss_mask ss_mask);
+ int at803x_config_mdix(struct phy_device *phydev, u8 ctrl);
+ int at803x_prepare_config_aneg(struct phy_device *phydev);
++int at803x_read_status(struct phy_device *phydev);
+ int at803x_get_tunable(struct phy_device *phydev,
+ 		       struct ethtool_tunable *tuna, void *data);
+ int at803x_set_tunable(struct phy_device *phydev,
+@@ -118,3 +168,4 @@ int at803x_cdt_fault_length(int dt);
+ int at803x_cdt_start(struct phy_device *phydev, u32 cdt_start);
+ int at803x_cdt_wait_for_completion(struct phy_device *phydev,
+ 				   u32 cdt_en);
++int qca808x_cable_test_get_status(struct phy_device *phydev, bool *finished);
diff --git a/target/linux/generic/backport-6.1/716-v6.9-06-net-phy-provide-whether-link-has-changed-in-c37_read.patch b/target/linux/generic/backport-6.1/716-v6.9-06-net-phy-provide-whether-link-has-changed-in-c37_read.patch
new file mode 100644
index 00000000000000..acaa4a644ee419
--- /dev/null
+++ b/target/linux/generic/backport-6.1/716-v6.9-06-net-phy-provide-whether-link-has-changed-in-c37_read.patch
@@ -0,0 +1,100 @@
+From 9b1d5e055508393561e26bd1720f4c2639b03b1a Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Tue, 6 Feb 2024 18:31:09 +0100
+Subject: [PATCH 06/10] net: phy: provide whether link has changed in
+ c37_read_status
+
+Some PHY driver might require additional regs call after
+genphy_c37_read_status() is called.
+
+Expand genphy_c37_read_status to provide a bool wheather the link has
+changed or not to permit PHY driver to skip additional regs call if
+nothing has changed.
+
+Every user of genphy_c37_read_status() is updated with the new
+additional bool.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/broadcom.c    |  3 ++-
+ drivers/net/phy/phy_device.c  | 11 +++++++++--
+ drivers/net/phy/qcom/at803x.c |  3 ++-
+ include/linux/phy.h           |  2 +-
+ 4 files changed, 14 insertions(+), 5 deletions(-)
+
+--- a/drivers/net/phy/broadcom.c
++++ b/drivers/net/phy/broadcom.c
+@@ -609,10 +609,11 @@ static int bcm54616s_config_aneg(struct
+ static int bcm54616s_read_status(struct phy_device *phydev)
+ {
+ 	struct bcm54616s_phy_priv *priv = phydev->priv;
++	bool changed;
+ 	int err;
+ 
+ 	if (priv->mode_1000bx_en)
+-		err = genphy_c37_read_status(phydev);
++		err = genphy_c37_read_status(phydev, &changed);
+ 	else
+ 		err = genphy_read_status(phydev);
+ 
+--- a/drivers/net/phy/phy_device.c
++++ b/drivers/net/phy/phy_device.c
+@@ -2549,12 +2549,15 @@ EXPORT_SYMBOL(genphy_read_status);
+ /**
+  * genphy_c37_read_status - check the link status and update current link state
+  * @phydev: target phy_device struct
++ * @changed: pointer where to store if link changed
+  *
+  * Description: Check the link, then figure out the current state
+  *   by comparing what we advertise with what the link partner
+  *   advertises. This function is for Clause 37 1000Base-X mode.
++ *
++ *   If link has changed, @changed is set to true, false otherwise.
+  */
+-int genphy_c37_read_status(struct phy_device *phydev)
++int genphy_c37_read_status(struct phy_device *phydev, bool *changed)
+ {
+ 	int lpa, err, old_link = phydev->link;
+ 
+@@ -2564,9 +2567,13 @@ int genphy_c37_read_status(struct phy_de
+ 		return err;
+ 
+ 	/* why bother the PHY if nothing can have changed */
+-	if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link)
++	if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link) {
++		*changed = false;
+ 		return 0;
++	}
+ 
++	/* Signal link has changed */
++	*changed = true;
+ 	phydev->duplex = DUPLEX_UNKNOWN;
+ 	phydev->pause = 0;
+ 	phydev->asym_pause = 0;
+--- a/drivers/net/phy/qcom/at803x.c
++++ b/drivers/net/phy/qcom/at803x.c
+@@ -912,9 +912,10 @@ static int at8031_config_intr(struct phy
+ static int at8031_read_status(struct phy_device *phydev)
+ {
+ 	struct at803x_priv *priv = phydev->priv;
++	bool changed;
+ 
+ 	if (priv->is_1000basex)
+-		return genphy_c37_read_status(phydev);
++		return genphy_c37_read_status(phydev, &changed);
+ 
+ 	return at803x_read_status(phydev);
+ }
+--- a/include/linux/phy.h
++++ b/include/linux/phy.h
+@@ -1688,7 +1688,7 @@ int genphy_write_mmd_unsupported(struct
+ 
+ /* Clause 37 */
+ int genphy_c37_config_aneg(struct phy_device *phydev);
+-int genphy_c37_read_status(struct phy_device *phydev);
++int genphy_c37_read_status(struct phy_device *phydev, bool *changed);
+ 
+ /* Clause 45 PHY */
+ int genphy_c45_restart_aneg(struct phy_device *phydev);
diff --git a/target/linux/generic/backport-6.1/716-v6.9-07-net-phy-qcom-add-support-for-QCA807x-PHY-Family.patch b/target/linux/generic/backport-6.1/716-v6.9-07-net-phy-qcom-add-support-for-QCA807x-PHY-Family.patch
new file mode 100644
index 00000000000000..bbf0f76d68cc87
--- /dev/null
+++ b/target/linux/generic/backport-6.1/716-v6.9-07-net-phy-qcom-add-support-for-QCA807x-PHY-Family.patch
@@ -0,0 +1,668 @@
+From d1cb613efbd3cd7d0c000167816beb3f248f5eb8 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robert.marko@sartura.hr>
+Date: Tue, 6 Feb 2024 18:31:10 +0100
+Subject: [PATCH 07/10] net: phy: qcom: add support for QCA807x PHY Family
+
+This adds driver for the Qualcomm QCA8072 and QCA8075 PHY-s.
+
+They are 2 or 5 port IEEE 802.3 clause 22 compliant 10BASE-Te,
+100BASE-TX and 1000BASE-T PHY-s.
+
+They feature 2 SerDes, one for PSGMII or QSGMII connection with
+MAC, while second one is SGMII for connection to MAC or fiber.
+
+Both models have a combo port that supports 1000BASE-X and
+100BASE-FX fiber.
+
+PHY package can be configured in 3 mode following this table:
+
+              First Serdes mode       Second Serdes mode
+Option 1      PSGMII for copper       Disabled
+              ports 0-4
+Option 2      PSGMII for copper       1000BASE-X / 100BASE-FX
+              ports 0-4
+Option 3      QSGMII for copper       SGMII for
+              ports 0-3               copper port 4
+
+Each PHY inside of QCA807x series has 4 digitally controlled
+output only pins that natively drive LED-s.
+But some vendors used these to driver generic LED-s controlled
+by userspace, so lets enable registering each PHY as GPIO
+controller and add driver for it.
+
+These are commonly used in Qualcomm IPQ40xx, IPQ60xx and IPQ807x
+boards.
+
+Co-developed-by: Christian Marangi <ansuelsmth@gmail.com>
+Signed-off-by: Robert Marko <robert.marko@sartura.hr>
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/qcom/Kconfig   |   8 +
+ drivers/net/phy/qcom/Makefile  |   1 +
+ drivers/net/phy/qcom/qca807x.c | 597 +++++++++++++++++++++++++++++++++
+ 3 files changed, 606 insertions(+)
+ create mode 100644 drivers/net/phy/qcom/qca807x.c
+
+--- a/drivers/net/phy/qcom/Kconfig
++++ b/drivers/net/phy/qcom/Kconfig
+@@ -20,3 +20,11 @@ config QCA808X_PHY
+ 	select QCOM_NET_PHYLIB
+ 	help
+ 	  Currently supports the QCA8081 model
++
++config QCA807X_PHY
++	tristate "Qualcomm QCA807x PHYs"
++	select QCOM_NET_PHYLIB
++	depends on OF_MDIO
++	help
++	  Currently supports the Qualcomm QCA8072, QCA8075 and the PSGMII
++	  control PHY.
+--- a/drivers/net/phy/qcom/Makefile
++++ b/drivers/net/phy/qcom/Makefile
+@@ -3,3 +3,4 @@ obj-$(CONFIG_QCOM_NET_PHYLIB)	+= qcom-ph
+ obj-$(CONFIG_AT803X_PHY)	+= at803x.o
+ obj-$(CONFIG_QCA83XX_PHY)	+= qca83xx.o
+ obj-$(CONFIG_QCA808X_PHY)	+= qca808x.o
++obj-$(CONFIG_QCA807X_PHY)	+= qca807x.o
+--- /dev/null
++++ b/drivers/net/phy/qcom/qca807x.c
+@@ -0,0 +1,597 @@
++// SPDX-License-Identifier: GPL-2.0-or-later
++/*
++ * Copyright (c) 2023 Sartura Ltd.
++ *
++ * Author: Robert Marko <robert.marko@sartura.hr>
++ *         Christian Marangi <ansuelsmth@gmail.com>
++ *
++ * Qualcomm QCA8072 and QCA8075 PHY driver
++ */
++
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/phy.h>
++#include <linux/bitfield.h>
++#include <linux/gpio/driver.h>
++#include <linux/sfp.h>
++
++#include "qcom.h"
++
++#define QCA807X_CHIP_CONFIGURATION				0x1f
++#define QCA807X_BT_BX_REG_SEL					BIT(15)
++#define QCA807X_BT_BX_REG_SEL_FIBER				0
++#define QCA807X_BT_BX_REG_SEL_COPPER				1
++#define QCA807X_CHIP_CONFIGURATION_MODE_CFG_MASK		GENMASK(3, 0)
++#define QCA807X_CHIP_CONFIGURATION_MODE_QSGMII_SGMII		4
++#define QCA807X_CHIP_CONFIGURATION_MODE_PSGMII_FIBER		3
++#define QCA807X_CHIP_CONFIGURATION_MODE_PSGMII_ALL_COPPER	0
++
++#define QCA807X_MEDIA_SELECT_STATUS				0x1a
++#define QCA807X_MEDIA_DETECTED_COPPER				BIT(5)
++#define QCA807X_MEDIA_DETECTED_1000_BASE_X			BIT(4)
++#define QCA807X_MEDIA_DETECTED_100_BASE_FX			BIT(3)
++
++#define QCA807X_MMD7_FIBER_MODE_AUTO_DETECTION			0x807e
++#define QCA807X_MMD7_FIBER_MODE_AUTO_DETECTION_EN		BIT(0)
++
++#define QCA807X_MMD7_1000BASE_T_POWER_SAVE_PER_CABLE_LENGTH	0x801a
++#define QCA807X_CONTROL_DAC_MASK				GENMASK(2, 0)
++/* List of tweaks enabled by this bit:
++ * - With both FULL amplitude and FULL bias current: bias current
++ *   is set to half.
++ * - With only DSP amplitude: bias current is set to half and
++ *   is set to 1/4 with cable < 10m.
++ * - With DSP bias current (included both DSP amplitude and
++ *   DSP bias current): bias current is half the detected current
++ *   with cable < 10m.
++ */
++#define QCA807X_CONTROL_DAC_BIAS_CURRENT_TWEAK			BIT(2)
++#define QCA807X_CONTROL_DAC_DSP_BIAS_CURRENT			BIT(1)
++#define QCA807X_CONTROL_DAC_DSP_AMPLITUDE			BIT(0)
++
++#define QCA807X_MMD7_LED_100N_1				0x8074
++#define QCA807X_MMD7_LED_100N_2				0x8075
++#define QCA807X_MMD7_LED_1000N_1			0x8076
++#define QCA807X_MMD7_LED_1000N_2			0x8077
++
++#define QCA807X_MMD7_LED_CTRL(x)			(0x8074 + ((x) * 2))
++#define QCA807X_MMD7_LED_FORCE_CTRL(x)			(0x8075 + ((x) * 2))
++
++#define QCA807X_GPIO_FORCE_EN				BIT(15)
++#define QCA807X_GPIO_FORCE_MODE_MASK			GENMASK(14, 13)
++
++#define QCA807X_FUNCTION_CONTROL			0x10
++#define QCA807X_FC_MDI_CROSSOVER_MODE_MASK		GENMASK(6, 5)
++#define QCA807X_FC_MDI_CROSSOVER_AUTO			3
++#define QCA807X_FC_MDI_CROSSOVER_MANUAL_MDIX		1
++#define QCA807X_FC_MDI_CROSSOVER_MANUAL_MDI		0
++
++/* PQSGMII Analog PHY specific */
++#define PQSGMII_CTRL_REG				0x0
++#define PQSGMII_ANALOG_SW_RESET				BIT(6)
++#define PQSGMII_DRIVE_CONTROL_1				0xb
++#define PQSGMII_TX_DRIVER_MASK				GENMASK(7, 4)
++#define PQSGMII_TX_DRIVER_140MV				0x0
++#define PQSGMII_TX_DRIVER_160MV				0x1
++#define PQSGMII_TX_DRIVER_180MV				0x2
++#define PQSGMII_TX_DRIVER_200MV				0x3
++#define PQSGMII_TX_DRIVER_220MV				0x4
++#define PQSGMII_TX_DRIVER_240MV				0x5
++#define PQSGMII_TX_DRIVER_260MV				0x6
++#define PQSGMII_TX_DRIVER_280MV				0x7
++#define PQSGMII_TX_DRIVER_300MV				0x8
++#define PQSGMII_TX_DRIVER_320MV				0x9
++#define PQSGMII_TX_DRIVER_400MV				0xa
++#define PQSGMII_TX_DRIVER_500MV				0xb
++#define PQSGMII_TX_DRIVER_600MV				0xc
++#define PQSGMII_MODE_CTRL				0x6d
++#define PQSGMII_MODE_CTRL_AZ_WORKAROUND_MASK		BIT(0)
++#define PQSGMII_MMD3_SERDES_CONTROL			0x805a
++
++#define PHY_ID_QCA8072		0x004dd0b2
++#define PHY_ID_QCA8075		0x004dd0b1
++
++#define QCA807X_COMBO_ADDR_OFFSET			4
++#define QCA807X_PQSGMII_ADDR_OFFSET			5
++#define SERDES_RESET_SLEEP				100
++
++enum qca807x_global_phy {
++	QCA807X_COMBO_ADDR = 4,
++	QCA807X_PQSGMII_ADDR = 5,
++};
++
++struct qca807x_shared_priv {
++	unsigned int package_mode;
++	u32 tx_drive_strength;
++};
++
++struct qca807x_gpio_priv {
++	struct phy_device *phy;
++};
++
++struct qca807x_priv {
++	bool dac_full_amplitude;
++	bool dac_full_bias_current;
++	bool dac_disable_bias_current_tweak;
++};
++
++static int qca807x_cable_test_start(struct phy_device *phydev)
++{
++	/* we do all the (time consuming) work later */
++	return 0;
++}
++
++#ifdef CONFIG_GPIOLIB
++static int qca807x_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
++{
++	return GPIO_LINE_DIRECTION_OUT;
++}
++
++static int qca807x_gpio_get(struct gpio_chip *gc, unsigned int offset)
++{
++	struct qca807x_gpio_priv *priv = gpiochip_get_data(gc);
++	u16 reg;
++	int val;
++
++	reg = QCA807X_MMD7_LED_FORCE_CTRL(offset);
++	val = phy_read_mmd(priv->phy, MDIO_MMD_AN, reg);
++
++	return FIELD_GET(QCA807X_GPIO_FORCE_MODE_MASK, val);
++}
++
++static void qca807x_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
++{
++	struct qca807x_gpio_priv *priv = gpiochip_get_data(gc);
++	u16 reg;
++	int val;
++
++	reg = QCA807X_MMD7_LED_FORCE_CTRL(offset);
++
++	val = phy_read_mmd(priv->phy, MDIO_MMD_AN, reg);
++	val &= ~QCA807X_GPIO_FORCE_MODE_MASK;
++	val |= QCA807X_GPIO_FORCE_EN;
++	val |= FIELD_PREP(QCA807X_GPIO_FORCE_MODE_MASK, value);
++
++	phy_write_mmd(priv->phy, MDIO_MMD_AN, reg, val);
++}
++
++static int qca807x_gpio_dir_out(struct gpio_chip *gc, unsigned int offset, int value)
++{
++	qca807x_gpio_set(gc, offset, value);
++
++	return 0;
++}
++
++static int qca807x_gpio(struct phy_device *phydev)
++{
++	struct device *dev = &phydev->mdio.dev;
++	struct qca807x_gpio_priv *priv;
++	struct gpio_chip *gc;
++
++	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
++	if (!priv)
++		return -ENOMEM;
++
++	priv->phy = phydev;
++
++	gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL);
++	if (!gc)
++		return -ENOMEM;
++
++	gc->label = dev_name(dev);
++	gc->base = -1;
++	gc->ngpio = 2;
++	gc->parent = dev;
++	gc->owner = THIS_MODULE;
++	gc->can_sleep = true;
++	gc->get_direction = qca807x_gpio_get_direction;
++	gc->direction_output = qca807x_gpio_dir_out;
++	gc->get = qca807x_gpio_get;
++	gc->set = qca807x_gpio_set;
++
++	return devm_gpiochip_add_data(dev, gc, priv);
++}
++#endif
++
++static int qca807x_read_fiber_status(struct phy_device *phydev)
++{
++	bool changed;
++	int ss, err;
++
++	err = genphy_c37_read_status(phydev, &changed);
++	if (err || !changed)
++		return err;
++
++	/* Read the QCA807x PHY-Specific Status register fiber page,
++	 * which indicates the speed and duplex that the PHY is actually
++	 * using, irrespective of whether we are in autoneg mode or not.
++	 */
++	ss = phy_read(phydev, AT803X_SPECIFIC_STATUS);
++	if (ss < 0)
++		return ss;
++
++	phydev->speed = SPEED_UNKNOWN;
++	phydev->duplex = DUPLEX_UNKNOWN;
++	if (ss & AT803X_SS_SPEED_DUPLEX_RESOLVED) {
++		switch (FIELD_GET(AT803X_SS_SPEED_MASK, ss)) {
++		case AT803X_SS_SPEED_100:
++			phydev->speed = SPEED_100;
++			break;
++		case AT803X_SS_SPEED_1000:
++			phydev->speed = SPEED_1000;
++			break;
++		}
++
++		if (ss & AT803X_SS_DUPLEX)
++			phydev->duplex = DUPLEX_FULL;
++		else
++			phydev->duplex = DUPLEX_HALF;
++	}
++
++	return 0;
++}
++
++static int qca807x_read_status(struct phy_device *phydev)
++{
++	if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported)) {
++		switch (phydev->port) {
++		case PORT_FIBRE:
++			return qca807x_read_fiber_status(phydev);
++		case PORT_TP:
++			return at803x_read_status(phydev);
++		default:
++			return -EINVAL;
++		}
++	}
++
++	return at803x_read_status(phydev);
++}
++
++static int qca807x_phy_package_probe_once(struct phy_device *phydev)
++{
++	struct phy_package_shared *shared = phydev->shared;
++	struct qca807x_shared_priv *priv = shared->priv;
++	unsigned int tx_drive_strength;
++	const char *package_mode_name;
++
++	/* Default to 600mw if not defined */
++	if (of_property_read_u32(shared->np, "qcom,tx-drive-strength-milliwatt",
++				 &tx_drive_strength))
++		tx_drive_strength = 600;
++
++	switch (tx_drive_strength) {
++	case 140:
++		priv->tx_drive_strength = PQSGMII_TX_DRIVER_140MV;
++		break;
++	case 160:
++		priv->tx_drive_strength = PQSGMII_TX_DRIVER_160MV;
++		break;
++	case 180:
++		priv->tx_drive_strength = PQSGMII_TX_DRIVER_180MV;
++		break;
++	case 200:
++		priv->tx_drive_strength = PQSGMII_TX_DRIVER_200MV;
++		break;
++	case 220:
++		priv->tx_drive_strength = PQSGMII_TX_DRIVER_220MV;
++		break;
++	case 240:
++		priv->tx_drive_strength = PQSGMII_TX_DRIVER_240MV;
++		break;
++	case 260:
++		priv->tx_drive_strength = PQSGMII_TX_DRIVER_260MV;
++		break;
++	case 280:
++		priv->tx_drive_strength = PQSGMII_TX_DRIVER_280MV;
++		break;
++	case 300:
++		priv->tx_drive_strength = PQSGMII_TX_DRIVER_300MV;
++		break;
++	case 320:
++		priv->tx_drive_strength = PQSGMII_TX_DRIVER_320MV;
++		break;
++	case 400:
++		priv->tx_drive_strength = PQSGMII_TX_DRIVER_400MV;
++		break;
++	case 500:
++		priv->tx_drive_strength = PQSGMII_TX_DRIVER_500MV;
++		break;
++	case 600:
++		priv->tx_drive_strength = PQSGMII_TX_DRIVER_600MV;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	priv->package_mode = PHY_INTERFACE_MODE_NA;
++	if (!of_property_read_string(shared->np, "qcom,package-mode",
++				     &package_mode_name)) {
++		if (!strcasecmp(package_mode_name,
++				phy_modes(PHY_INTERFACE_MODE_PSGMII)))
++			priv->package_mode = PHY_INTERFACE_MODE_PSGMII;
++		else if (!strcasecmp(package_mode_name,
++				     phy_modes(PHY_INTERFACE_MODE_QSGMII)))
++			priv->package_mode = PHY_INTERFACE_MODE_QSGMII;
++		else
++			return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int qca807x_phy_package_config_init_once(struct phy_device *phydev)
++{
++	struct phy_package_shared *shared = phydev->shared;
++	struct qca807x_shared_priv *priv = shared->priv;
++	int val, ret;
++
++	phy_lock_mdio_bus(phydev);
++
++	/* Set correct PHY package mode */
++	val = __phy_package_read(phydev, QCA807X_COMBO_ADDR,
++				 QCA807X_CHIP_CONFIGURATION);
++	val &= ~QCA807X_CHIP_CONFIGURATION_MODE_CFG_MASK;
++	/* package_mode can be QSGMII or PSGMII and we validate
++	 * this in probe_once.
++	 * With package_mode to NA, we default to PSGMII.
++	 */
++	switch (priv->package_mode) {
++	case PHY_INTERFACE_MODE_QSGMII:
++		val |= QCA807X_CHIP_CONFIGURATION_MODE_QSGMII_SGMII;
++		break;
++	case PHY_INTERFACE_MODE_PSGMII:
++	default:
++		val |= QCA807X_CHIP_CONFIGURATION_MODE_PSGMII_ALL_COPPER;
++	}
++	ret = __phy_package_write(phydev, QCA807X_COMBO_ADDR,
++				  QCA807X_CHIP_CONFIGURATION, val);
++	if (ret)
++		goto exit;
++
++	/* After mode change Serdes reset is required */
++	val = __phy_package_read(phydev, QCA807X_PQSGMII_ADDR,
++				 PQSGMII_CTRL_REG);
++	val &= ~PQSGMII_ANALOG_SW_RESET;
++	ret = __phy_package_write(phydev, QCA807X_PQSGMII_ADDR,
++				  PQSGMII_CTRL_REG, val);
++	if (ret)
++		goto exit;
++
++	msleep(SERDES_RESET_SLEEP);
++
++	val = __phy_package_read(phydev, QCA807X_PQSGMII_ADDR,
++				 PQSGMII_CTRL_REG);
++	val |= PQSGMII_ANALOG_SW_RESET;
++	ret = __phy_package_write(phydev, QCA807X_PQSGMII_ADDR,
++				  PQSGMII_CTRL_REG, val);
++	if (ret)
++		goto exit;
++
++	/* Workaround to enable AZ transmitting ability */
++	val = __phy_package_read_mmd(phydev, QCA807X_PQSGMII_ADDR,
++				     MDIO_MMD_PMAPMD, PQSGMII_MODE_CTRL);
++	val &= ~PQSGMII_MODE_CTRL_AZ_WORKAROUND_MASK;
++	ret = __phy_package_write_mmd(phydev, QCA807X_PQSGMII_ADDR,
++				      MDIO_MMD_PMAPMD, PQSGMII_MODE_CTRL, val);
++	if (ret)
++		goto exit;
++
++	/* Set PQSGMII TX AMP strength */
++	val = __phy_package_read(phydev, QCA807X_PQSGMII_ADDR,
++				 PQSGMII_DRIVE_CONTROL_1);
++	val &= ~PQSGMII_TX_DRIVER_MASK;
++	val |= FIELD_PREP(PQSGMII_TX_DRIVER_MASK, priv->tx_drive_strength);
++	ret = __phy_package_write(phydev, QCA807X_PQSGMII_ADDR,
++				  PQSGMII_DRIVE_CONTROL_1, val);
++	if (ret)
++		goto exit;
++
++	/* Prevent PSGMII going into hibernation via PSGMII self test */
++	val = __phy_package_read_mmd(phydev, QCA807X_COMBO_ADDR,
++				     MDIO_MMD_PCS, PQSGMII_MMD3_SERDES_CONTROL);
++	val &= ~BIT(1);
++	ret = __phy_package_write_mmd(phydev, QCA807X_COMBO_ADDR,
++				      MDIO_MMD_PCS, PQSGMII_MMD3_SERDES_CONTROL, val);
++
++exit:
++	phy_unlock_mdio_bus(phydev);
++
++	return ret;
++}
++
++static int qca807x_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
++{
++	struct phy_device *phydev = upstream;
++	__ETHTOOL_DECLARE_LINK_MODE_MASK(support) = { 0, };
++	phy_interface_t iface;
++	int ret;
++	DECLARE_PHY_INTERFACE_MASK(interfaces);
++
++	sfp_parse_support(phydev->sfp_bus, id, support, interfaces);
++	iface = sfp_select_interface(phydev->sfp_bus, support);
++
++	dev_info(&phydev->mdio.dev, "%s SFP module inserted\n", phy_modes(iface));
++
++	switch (iface) {
++	case PHY_INTERFACE_MODE_1000BASEX:
++	case PHY_INTERFACE_MODE_100BASEX:
++		/* Set PHY mode to PSGMII combo (1/4 copper + combo ports) mode */
++		ret = phy_modify(phydev,
++				 QCA807X_CHIP_CONFIGURATION,
++				 QCA807X_CHIP_CONFIGURATION_MODE_CFG_MASK,
++				 QCA807X_CHIP_CONFIGURATION_MODE_PSGMII_FIBER);
++		/* Enable fiber mode autodection (1000Base-X or 100Base-FX) */
++		ret = phy_set_bits_mmd(phydev,
++				       MDIO_MMD_AN,
++				       QCA807X_MMD7_FIBER_MODE_AUTO_DETECTION,
++				       QCA807X_MMD7_FIBER_MODE_AUTO_DETECTION_EN);
++		/* Select fiber page */
++		ret = phy_clear_bits(phydev,
++				     QCA807X_CHIP_CONFIGURATION,
++				     QCA807X_BT_BX_REG_SEL);
++
++		phydev->port = PORT_FIBRE;
++		break;
++	default:
++		dev_err(&phydev->mdio.dev, "Incompatible SFP module inserted\n");
++		return -EINVAL;
++	}
++
++	return ret;
++}
++
++static void qca807x_sfp_remove(void *upstream)
++{
++	struct phy_device *phydev = upstream;
++
++	/* Select copper page */
++	phy_set_bits(phydev,
++		     QCA807X_CHIP_CONFIGURATION,
++		     QCA807X_BT_BX_REG_SEL);
++
++	phydev->port = PORT_TP;
++}
++
++static const struct sfp_upstream_ops qca807x_sfp_ops = {
++	.attach = phy_sfp_attach,
++	.detach = phy_sfp_detach,
++	.module_insert = qca807x_sfp_insert,
++	.module_remove = qca807x_sfp_remove,
++};
++
++static int qca807x_probe(struct phy_device *phydev)
++{
++	struct device_node *node = phydev->mdio.dev.of_node;
++	struct qca807x_shared_priv *shared_priv;
++	struct device *dev = &phydev->mdio.dev;
++	struct phy_package_shared *shared;
++	struct qca807x_priv *priv;
++	int ret;
++
++	ret = devm_of_phy_package_join(dev, phydev, sizeof(*shared_priv));
++	if (ret)
++		return ret;
++
++	if (phy_package_probe_once(phydev)) {
++		ret = qca807x_phy_package_probe_once(phydev);
++		if (ret)
++			return ret;
++	}
++
++	shared = phydev->shared;
++	shared_priv = shared->priv;
++
++	/* Make sure PHY follow PHY package mode if enforced */
++	if (shared_priv->package_mode != PHY_INTERFACE_MODE_NA &&
++	    phydev->interface != shared_priv->package_mode)
++		return -EINVAL;
++
++	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
++	if (!priv)
++		return -ENOMEM;
++
++	priv->dac_full_amplitude = of_property_read_bool(node, "qcom,dac-full-amplitude");
++	priv->dac_full_bias_current = of_property_read_bool(node, "qcom,dac-full-bias-current");
++	priv->dac_disable_bias_current_tweak = of_property_read_bool(node,
++								     "qcom,dac-disable-bias-current-tweak");
++
++	if (IS_ENABLED(CONFIG_GPIOLIB)) {
++		/* Do not register a GPIO controller unless flagged for it */
++		if (of_property_read_bool(node, "gpio-controller")) {
++			ret = qca807x_gpio(phydev);
++			if (ret)
++				return ret;
++		}
++	}
++
++	/* Attach SFP bus on combo port*/
++	if (phy_read(phydev, QCA807X_CHIP_CONFIGURATION)) {
++		ret = phy_sfp_probe(phydev, &qca807x_sfp_ops);
++		if (ret)
++			return ret;
++		linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported);
++		linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->advertising);
++	}
++
++	phydev->priv = priv;
++
++	return 0;
++}
++
++static int qca807x_config_init(struct phy_device *phydev)
++{
++	struct qca807x_priv *priv = phydev->priv;
++	u16 control_dac;
++	int ret;
++
++	if (phy_package_init_once(phydev)) {
++		ret = qca807x_phy_package_config_init_once(phydev);
++		if (ret)
++			return ret;
++	}
++
++	control_dac = phy_read_mmd(phydev, MDIO_MMD_AN,
++				   QCA807X_MMD7_1000BASE_T_POWER_SAVE_PER_CABLE_LENGTH);
++	control_dac &= ~QCA807X_CONTROL_DAC_MASK;
++	if (!priv->dac_full_amplitude)
++		control_dac |= QCA807X_CONTROL_DAC_DSP_AMPLITUDE;
++	if (!priv->dac_full_amplitude)
++		control_dac |= QCA807X_CONTROL_DAC_DSP_BIAS_CURRENT;
++	if (!priv->dac_disable_bias_current_tweak)
++		control_dac |= QCA807X_CONTROL_DAC_BIAS_CURRENT_TWEAK;
++	return phy_write_mmd(phydev, MDIO_MMD_AN,
++			     QCA807X_MMD7_1000BASE_T_POWER_SAVE_PER_CABLE_LENGTH,
++			     control_dac);
++}
++
++static struct phy_driver qca807x_drivers[] = {
++	{
++		PHY_ID_MATCH_EXACT(PHY_ID_QCA8072),
++		.name           = "Qualcomm QCA8072",
++		.flags		= PHY_POLL_CABLE_TEST,
++		/* PHY_GBIT_FEATURES */
++		.probe		= qca807x_probe,
++		.config_init	= qca807x_config_init,
++		.read_status	= qca807x_read_status,
++		.config_intr	= at803x_config_intr,
++		.handle_interrupt = at803x_handle_interrupt,
++		.soft_reset	= genphy_soft_reset,
++		.get_tunable	= at803x_get_tunable,
++		.set_tunable	= at803x_set_tunable,
++		.resume		= genphy_resume,
++		.suspend	= genphy_suspend,
++		.cable_test_start	= qca807x_cable_test_start,
++		.cable_test_get_status	= qca808x_cable_test_get_status,
++	},
++	{
++		PHY_ID_MATCH_EXACT(PHY_ID_QCA8075),
++		.name           = "Qualcomm QCA8075",
++		.flags		= PHY_POLL_CABLE_TEST,
++		/* PHY_GBIT_FEATURES */
++		.probe		= qca807x_probe,
++		.config_init	= qca807x_config_init,
++		.read_status	= qca807x_read_status,
++		.config_intr	= at803x_config_intr,
++		.handle_interrupt = at803x_handle_interrupt,
++		.soft_reset	= genphy_soft_reset,
++		.get_tunable	= at803x_get_tunable,
++		.set_tunable	= at803x_set_tunable,
++		.resume		= genphy_resume,
++		.suspend	= genphy_suspend,
++		.cable_test_start	= qca807x_cable_test_start,
++		.cable_test_get_status	= qca808x_cable_test_get_status,
++	},
++};
++module_phy_driver(qca807x_drivers);
++
++static struct mdio_device_id __maybe_unused qca807x_tbl[] = {
++	{ PHY_ID_MATCH_EXACT(PHY_ID_QCA8072) },
++	{ PHY_ID_MATCH_EXACT(PHY_ID_QCA8075) },
++	{ }
++};
++
++MODULE_AUTHOR("Robert Marko <robert.marko@sartura.hr>");
++MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
++MODULE_DESCRIPTION("Qualcomm QCA807x PHY driver");
++MODULE_DEVICE_TABLE(mdio, qca807x_tbl);
++MODULE_LICENSE("GPL");
diff --git a/target/linux/generic/backport-6.1/716-v6.9-08-net-phy-qcom-move-common-qca808x-LED-define-to-share.patch b/target/linux/generic/backport-6.1/716-v6.9-08-net-phy-qcom-move-common-qca808x-LED-define-to-share.patch
new file mode 100644
index 00000000000000..cf4d74e8c523c2
--- /dev/null
+++ b/target/linux/generic/backport-6.1/716-v6.9-08-net-phy-qcom-move-common-qca808x-LED-define-to-share.patch
@@ -0,0 +1,179 @@
+From ee9d9807bee0e6af8ca2a4db6f0d1dc0e5b41f44 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Tue, 6 Feb 2024 18:31:11 +0100
+Subject: [PATCH 08/10] net: phy: qcom: move common qca808x LED define to
+ shared header
+
+The LED implementation of qca808x and qca807x is the same but qca807x
+supports also Fiber port and have different hw control bits for Fiber
+port.
+
+In preparation for qca807x introduction, move all the common define to
+shared header.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/qcom/qca808x.c | 65 ----------------------------------
+ drivers/net/phy/qcom/qcom.h    | 65 ++++++++++++++++++++++++++++++++++
+ 2 files changed, 65 insertions(+), 65 deletions(-)
+
+--- a/drivers/net/phy/qcom/qca808x.c
++++ b/drivers/net/phy/qcom/qca808x.c
+@@ -62,29 +62,6 @@
+ #define QCA808X_DBG_AN_TEST			0xb
+ #define QCA808X_HIBERNATION_EN			BIT(15)
+ 
+-#define QCA808X_MMD7_LED_GLOBAL			0x8073
+-#define QCA808X_LED_BLINK_1			GENMASK(11, 6)
+-#define QCA808X_LED_BLINK_2			GENMASK(5, 0)
+-/* Values are the same for both BLINK_1 and BLINK_2 */
+-#define QCA808X_LED_BLINK_FREQ_MASK		GENMASK(5, 3)
+-#define QCA808X_LED_BLINK_FREQ_2HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x0)
+-#define QCA808X_LED_BLINK_FREQ_4HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x1)
+-#define QCA808X_LED_BLINK_FREQ_8HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x2)
+-#define QCA808X_LED_BLINK_FREQ_16HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x3)
+-#define QCA808X_LED_BLINK_FREQ_32HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x4)
+-#define QCA808X_LED_BLINK_FREQ_64HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x5)
+-#define QCA808X_LED_BLINK_FREQ_128HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x6)
+-#define QCA808X_LED_BLINK_FREQ_256HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x7)
+-#define QCA808X_LED_BLINK_DUTY_MASK		GENMASK(2, 0)
+-#define QCA808X_LED_BLINK_DUTY_50_50		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x0)
+-#define QCA808X_LED_BLINK_DUTY_75_25		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x1)
+-#define QCA808X_LED_BLINK_DUTY_25_75		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x2)
+-#define QCA808X_LED_BLINK_DUTY_33_67		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x3)
+-#define QCA808X_LED_BLINK_DUTY_67_33		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x4)
+-#define QCA808X_LED_BLINK_DUTY_17_83		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x5)
+-#define QCA808X_LED_BLINK_DUTY_83_17		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x6)
+-#define QCA808X_LED_BLINK_DUTY_8_92		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x7)
+-
+ #define QCA808X_MMD7_LED2_CTRL			0x8074
+ #define QCA808X_MMD7_LED2_FORCE_CTRL		0x8075
+ #define QCA808X_MMD7_LED1_CTRL			0x8076
+@@ -92,51 +69,9 @@
+ #define QCA808X_MMD7_LED0_CTRL			0x8078
+ #define QCA808X_MMD7_LED_CTRL(x)		(0x8078 - ((x) * 2))
+ 
+-/* LED hw control pattern is the same for every LED */
+-#define QCA808X_LED_PATTERN_MASK		GENMASK(15, 0)
+-#define QCA808X_LED_SPEED2500_ON		BIT(15)
+-#define QCA808X_LED_SPEED2500_BLINK		BIT(14)
+-/* Follow blink trigger even if duplex or speed condition doesn't match */
+-#define QCA808X_LED_BLINK_CHECK_BYPASS		BIT(13)
+-#define QCA808X_LED_FULL_DUPLEX_ON		BIT(12)
+-#define QCA808X_LED_HALF_DUPLEX_ON		BIT(11)
+-#define QCA808X_LED_TX_BLINK			BIT(10)
+-#define QCA808X_LED_RX_BLINK			BIT(9)
+-#define QCA808X_LED_TX_ON_10MS			BIT(8)
+-#define QCA808X_LED_RX_ON_10MS			BIT(7)
+-#define QCA808X_LED_SPEED1000_ON		BIT(6)
+-#define QCA808X_LED_SPEED100_ON			BIT(5)
+-#define QCA808X_LED_SPEED10_ON			BIT(4)
+-#define QCA808X_LED_COLLISION_BLINK		BIT(3)
+-#define QCA808X_LED_SPEED1000_BLINK		BIT(2)
+-#define QCA808X_LED_SPEED100_BLINK		BIT(1)
+-#define QCA808X_LED_SPEED10_BLINK		BIT(0)
+-
+ #define QCA808X_MMD7_LED0_FORCE_CTRL		0x8079
+ #define QCA808X_MMD7_LED_FORCE_CTRL(x)		(0x8079 - ((x) * 2))
+ 
+-/* LED force ctrl is the same for every LED
+- * No documentation exist for this, not even internal one
+- * with NDA as QCOM gives only info about configuring
+- * hw control pattern rules and doesn't indicate any way
+- * to force the LED to specific mode.
+- * These define comes from reverse and testing and maybe
+- * lack of some info or some info are not entirely correct.
+- * For the basic LED control and hw control these finding
+- * are enough to support LED control in all the required APIs.
+- *
+- * On doing some comparison with implementation with qca807x,
+- * it was found that it's 1:1 equal to it and confirms all the
+- * reverse done. It was also found further specification with the
+- * force mode and the blink modes.
+- */
+-#define QCA808X_LED_FORCE_EN			BIT(15)
+-#define QCA808X_LED_FORCE_MODE_MASK		GENMASK(14, 13)
+-#define QCA808X_LED_FORCE_BLINK_1		FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x3)
+-#define QCA808X_LED_FORCE_BLINK_2		FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x2)
+-#define QCA808X_LED_FORCE_ON			FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x1)
+-#define QCA808X_LED_FORCE_OFF			FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x0)
+-
+ #define QCA808X_MMD7_LED_POLARITY_CTRL		0x901a
+ /* QSDK sets by default 0x46 to this reg that sets BIT 6 for
+  * LED to active high. It's not clear what BIT 3 and BIT 4 does.
+--- a/drivers/net/phy/qcom/qcom.h
++++ b/drivers/net/phy/qcom/qcom.h
+@@ -103,6 +103,71 @@
+ /* Added for reference of existence but should be handled by wait_for_completion already */
+ #define QCA808X_CDT_STATUS_STAT_BUSY		(BIT(1) | BIT(3))
+ 
++#define QCA808X_MMD7_LED_GLOBAL			0x8073
++#define QCA808X_LED_BLINK_1			GENMASK(11, 6)
++#define QCA808X_LED_BLINK_2			GENMASK(5, 0)
++/* Values are the same for both BLINK_1 and BLINK_2 */
++#define QCA808X_LED_BLINK_FREQ_MASK		GENMASK(5, 3)
++#define QCA808X_LED_BLINK_FREQ_2HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x0)
++#define QCA808X_LED_BLINK_FREQ_4HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x1)
++#define QCA808X_LED_BLINK_FREQ_8HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x2)
++#define QCA808X_LED_BLINK_FREQ_16HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x3)
++#define QCA808X_LED_BLINK_FREQ_32HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x4)
++#define QCA808X_LED_BLINK_FREQ_64HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x5)
++#define QCA808X_LED_BLINK_FREQ_128HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x6)
++#define QCA808X_LED_BLINK_FREQ_256HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x7)
++#define QCA808X_LED_BLINK_DUTY_MASK		GENMASK(2, 0)
++#define QCA808X_LED_BLINK_DUTY_50_50		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x0)
++#define QCA808X_LED_BLINK_DUTY_75_25		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x1)
++#define QCA808X_LED_BLINK_DUTY_25_75		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x2)
++#define QCA808X_LED_BLINK_DUTY_33_67		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x3)
++#define QCA808X_LED_BLINK_DUTY_67_33		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x4)
++#define QCA808X_LED_BLINK_DUTY_17_83		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x5)
++#define QCA808X_LED_BLINK_DUTY_83_17		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x6)
++#define QCA808X_LED_BLINK_DUTY_8_92		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x7)
++
++/* LED hw control pattern is the same for every LED */
++#define QCA808X_LED_PATTERN_MASK		GENMASK(15, 0)
++#define QCA808X_LED_SPEED2500_ON		BIT(15)
++#define QCA808X_LED_SPEED2500_BLINK		BIT(14)
++/* Follow blink trigger even if duplex or speed condition doesn't match */
++#define QCA808X_LED_BLINK_CHECK_BYPASS		BIT(13)
++#define QCA808X_LED_FULL_DUPLEX_ON		BIT(12)
++#define QCA808X_LED_HALF_DUPLEX_ON		BIT(11)
++#define QCA808X_LED_TX_BLINK			BIT(10)
++#define QCA808X_LED_RX_BLINK			BIT(9)
++#define QCA808X_LED_TX_ON_10MS			BIT(8)
++#define QCA808X_LED_RX_ON_10MS			BIT(7)
++#define QCA808X_LED_SPEED1000_ON		BIT(6)
++#define QCA808X_LED_SPEED100_ON			BIT(5)
++#define QCA808X_LED_SPEED10_ON			BIT(4)
++#define QCA808X_LED_COLLISION_BLINK		BIT(3)
++#define QCA808X_LED_SPEED1000_BLINK		BIT(2)
++#define QCA808X_LED_SPEED100_BLINK		BIT(1)
++#define QCA808X_LED_SPEED10_BLINK		BIT(0)
++
++/* LED force ctrl is the same for every LED
++ * No documentation exist for this, not even internal one
++ * with NDA as QCOM gives only info about configuring
++ * hw control pattern rules and doesn't indicate any way
++ * to force the LED to specific mode.
++ * These define comes from reverse and testing and maybe
++ * lack of some info or some info are not entirely correct.
++ * For the basic LED control and hw control these finding
++ * are enough to support LED control in all the required APIs.
++ *
++ * On doing some comparison with implementation with qca807x,
++ * it was found that it's 1:1 equal to it and confirms all the
++ * reverse done. It was also found further specification with the
++ * force mode and the blink modes.
++ */
++#define QCA808X_LED_FORCE_EN			BIT(15)
++#define QCA808X_LED_FORCE_MODE_MASK		GENMASK(14, 13)
++#define QCA808X_LED_FORCE_BLINK_1		FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x3)
++#define QCA808X_LED_FORCE_BLINK_2		FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x2)
++#define QCA808X_LED_FORCE_ON			FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x1)
++#define QCA808X_LED_FORCE_OFF			FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x0)
++
+ #define AT803X_LOC_MAC_ADDR_0_15_OFFSET		0x804C
+ #define AT803X_LOC_MAC_ADDR_16_31_OFFSET	0x804B
+ #define AT803X_LOC_MAC_ADDR_32_47_OFFSET	0x804A
diff --git a/target/linux/generic/backport-6.1/716-v6.9-09-net-phy-qcom-generalize-some-qca808x-LED-functions.patch b/target/linux/generic/backport-6.1/716-v6.9-09-net-phy-qcom-generalize-some-qca808x-LED-functions.patch
new file mode 100644
index 00000000000000..da73c1d3b8981b
--- /dev/null
+++ b/target/linux/generic/backport-6.1/716-v6.9-09-net-phy-qcom-generalize-some-qca808x-LED-functions.patch
@@ -0,0 +1,172 @@
+From 47b930d0dd437af927145dba50a2e2ea1ba97c67 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Tue, 6 Feb 2024 18:31:12 +0100
+Subject: [PATCH 09/10] net: phy: qcom: generalize some qca808x LED functions
+
+Generalize some qca808x LED functions in preparation for qca807x LED
+support.
+
+The LED implementation of qca808x and qca807x is the same but qca807x
+supports also Fiber port and have different hw control bits for Fiber
+port. To limit code duplication introduce micro functions that takes reg
+instead of LED index to tweak all the supported LED modes.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/qcom/qca808x.c      | 38 +++-----------------
+ drivers/net/phy/qcom/qcom-phy-lib.c | 54 +++++++++++++++++++++++++++++
+ drivers/net/phy/qcom/qcom.h         |  7 ++++
+ 3 files changed, 65 insertions(+), 34 deletions(-)
+
+--- a/drivers/net/phy/qcom/qca808x.c
++++ b/drivers/net/phy/qcom/qca808x.c
+@@ -437,9 +437,7 @@ static int qca808x_led_hw_control_enable
+ 		return -EINVAL;
+ 
+ 	reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
+-
+-	return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg,
+-				  QCA808X_LED_FORCE_EN);
++	return qca808x_led_reg_hw_control_enable(phydev, reg);
+ }
+ 
+ static int qca808x_led_hw_is_supported(struct phy_device *phydev, u8 index,
+@@ -480,16 +478,12 @@ static int qca808x_led_hw_control_set(st
+ static bool qca808x_led_hw_control_status(struct phy_device *phydev, u8 index)
+ {
+ 	u16 reg;
+-	int val;
+ 
+ 	if (index > 2)
+ 		return false;
+ 
+ 	reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
+-
+-	val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
+-
+-	return !(val & QCA808X_LED_FORCE_EN);
++	return qca808x_led_reg_hw_control_status(phydev, reg);
+ }
+ 
+ static int qca808x_led_hw_control_get(struct phy_device *phydev, u8 index,
+@@ -557,44 +551,20 @@ static int qca808x_led_brightness_set(st
+ 	}
+ 
+ 	reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
+-
+-	return phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
+-			      QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_MODE_MASK,
+-			      QCA808X_LED_FORCE_EN | (value ? QCA808X_LED_FORCE_ON :
+-							     QCA808X_LED_FORCE_OFF));
++	return qca808x_led_reg_brightness_set(phydev, reg, value);
+ }
+ 
+ static int qca808x_led_blink_set(struct phy_device *phydev, u8 index,
+ 				 unsigned long *delay_on,
+ 				 unsigned long *delay_off)
+ {
+-	int ret;
+ 	u16 reg;
+ 
+ 	if (index > 2)
+ 		return -EINVAL;
+ 
+ 	reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
+-
+-	/* Set blink to 50% off, 50% on at 4Hz by default */
+-	ret = phy_modify_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_LED_GLOBAL,
+-			     QCA808X_LED_BLINK_FREQ_MASK | QCA808X_LED_BLINK_DUTY_MASK,
+-			     QCA808X_LED_BLINK_FREQ_4HZ | QCA808X_LED_BLINK_DUTY_50_50);
+-	if (ret)
+-		return ret;
+-
+-	/* We use BLINK_1 for normal blinking */
+-	ret = phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
+-			     QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_MODE_MASK,
+-			     QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_BLINK_1);
+-	if (ret)
+-		return ret;
+-
+-	/* We set blink to 4Hz, aka 250ms */
+-	*delay_on = 250 / 2;
+-	*delay_off = 250 / 2;
+-
+-	return 0;
++	return qca808x_led_reg_blink_set(phydev, reg, delay_on, delay_off);
+ }
+ 
+ static int qca808x_led_polarity_set(struct phy_device *phydev, int index,
+--- a/drivers/net/phy/qcom/qcom-phy-lib.c
++++ b/drivers/net/phy/qcom/qcom-phy-lib.c
+@@ -620,3 +620,57 @@ int qca808x_cable_test_get_status(struct
+ 	return 0;
+ }
+ EXPORT_SYMBOL_GPL(qca808x_cable_test_get_status);
++
++int qca808x_led_reg_hw_control_enable(struct phy_device *phydev, u16 reg)
++{
++	return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg,
++				  QCA808X_LED_FORCE_EN);
++}
++EXPORT_SYMBOL_GPL(qca808x_led_reg_hw_control_enable);
++
++bool qca808x_led_reg_hw_control_status(struct phy_device *phydev, u16 reg)
++{
++	int val;
++
++	val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
++	return !(val & QCA808X_LED_FORCE_EN);
++}
++EXPORT_SYMBOL_GPL(qca808x_led_reg_hw_control_status);
++
++int qca808x_led_reg_brightness_set(struct phy_device *phydev,
++				   u16 reg, enum led_brightness value)
++{
++	return phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
++			      QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_MODE_MASK,
++			      QCA808X_LED_FORCE_EN | (value ? QCA808X_LED_FORCE_ON :
++							      QCA808X_LED_FORCE_OFF));
++}
++EXPORT_SYMBOL_GPL(qca808x_led_reg_brightness_set);
++
++int qca808x_led_reg_blink_set(struct phy_device *phydev, u16 reg,
++			      unsigned long *delay_on,
++			      unsigned long *delay_off)
++{
++	int ret;
++
++	/* Set blink to 50% off, 50% on at 4Hz by default */
++	ret = phy_modify_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_LED_GLOBAL,
++			     QCA808X_LED_BLINK_FREQ_MASK | QCA808X_LED_BLINK_DUTY_MASK,
++			     QCA808X_LED_BLINK_FREQ_4HZ | QCA808X_LED_BLINK_DUTY_50_50);
++	if (ret)
++		return ret;
++
++	/* We use BLINK_1 for normal blinking */
++	ret = phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
++			     QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_MODE_MASK,
++			     QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_BLINK_1);
++	if (ret)
++		return ret;
++
++	/* We set blink to 4Hz, aka 250ms */
++	*delay_on = 250 / 2;
++	*delay_off = 250 / 2;
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(qca808x_led_reg_blink_set);
+--- a/drivers/net/phy/qcom/qcom.h
++++ b/drivers/net/phy/qcom/qcom.h
+@@ -234,3 +234,10 @@ int at803x_cdt_start(struct phy_device *
+ int at803x_cdt_wait_for_completion(struct phy_device *phydev,
+ 				   u32 cdt_en);
+ int qca808x_cable_test_get_status(struct phy_device *phydev, bool *finished);
++int qca808x_led_reg_hw_control_enable(struct phy_device *phydev, u16 reg);
++bool qca808x_led_reg_hw_control_status(struct phy_device *phydev, u16 reg);
++int qca808x_led_reg_brightness_set(struct phy_device *phydev,
++				   u16 reg, enum led_brightness value);
++int qca808x_led_reg_blink_set(struct phy_device *phydev, u16 reg,
++			      unsigned long *delay_on,
++			      unsigned long *delay_off);
diff --git a/target/linux/generic/backport-6.1/716-v6.9-10-net-phy-qca807x-add-support-for-configurable-LED.patch b/target/linux/generic/backport-6.1/716-v6.9-10-net-phy-qca807x-add-support-for-configurable-LED.patch
new file mode 100644
index 00000000000000..3bd36f6ffe2f7a
--- /dev/null
+++ b/target/linux/generic/backport-6.1/716-v6.9-10-net-phy-qca807x-add-support-for-configurable-LED.patch
@@ -0,0 +1,326 @@
+From f508a226b517a6a8afd78a317de46bc83e3e3d51 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Tue, 6 Feb 2024 18:31:13 +0100
+Subject: [PATCH 10/10] net: phy: qca807x: add support for configurable LED
+
+QCA8072/5 have up to 2 LEDs attached for PHY.
+
+LEDs can be configured to be ON/hw blink or be set to HW control.
+
+Hw blink mode is set to blink at 4Hz or 250ms.
+
+PHY can support both copper (TP) or fiber (FIBRE) kind and supports
+different HW control modes based on the port type.
+
+HW control modes supported for netdev trigger for copper ports are:
+- LINK_10
+- LINK_100
+- LINK_1000
+- TX
+- RX
+- FULL_DUPLEX
+- HALF_DUPLEX
+
+HW control modes supported for netdev trigger for fiber ports are:
+- LINK_100
+- LINK_1000
+- TX
+- RX
+- FULL_DUPLEX
+- HALF_DUPLEX
+
+LED support conflicts with GPIO controller feature and must be disabled
+if gpio-controller is used for the PHY.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/qcom/qca807x.c | 256 ++++++++++++++++++++++++++++++++-
+ 1 file changed, 254 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/phy/qcom/qca807x.c
++++ b/drivers/net/phy/qcom/qca807x.c
+@@ -57,8 +57,18 @@
+ #define QCA807X_MMD7_LED_CTRL(x)			(0x8074 + ((x) * 2))
+ #define QCA807X_MMD7_LED_FORCE_CTRL(x)			(0x8075 + ((x) * 2))
+ 
+-#define QCA807X_GPIO_FORCE_EN				BIT(15)
+-#define QCA807X_GPIO_FORCE_MODE_MASK			GENMASK(14, 13)
++/* LED hw control pattern for fiber port */
++#define QCA807X_LED_FIBER_PATTERN_MASK			GENMASK(11, 1)
++#define QCA807X_LED_FIBER_TXACT_BLK_EN			BIT(10)
++#define QCA807X_LED_FIBER_RXACT_BLK_EN			BIT(9)
++#define QCA807X_LED_FIBER_FDX_ON_EN			BIT(6)
++#define QCA807X_LED_FIBER_HDX_ON_EN			BIT(5)
++#define QCA807X_LED_FIBER_1000BX_ON_EN			BIT(2)
++#define QCA807X_LED_FIBER_100FX_ON_EN			BIT(1)
++
++/* Some device repurpose the LED as GPIO out */
++#define QCA807X_GPIO_FORCE_EN				QCA808X_LED_FORCE_EN
++#define QCA807X_GPIO_FORCE_MODE_MASK			QCA808X_LED_FORCE_MODE_MASK
+ 
+ #define QCA807X_FUNCTION_CONTROL			0x10
+ #define QCA807X_FC_MDI_CROSSOVER_MODE_MASK		GENMASK(6, 5)
+@@ -121,6 +131,233 @@ static int qca807x_cable_test_start(stru
+ 	return 0;
+ }
+ 
++static int qca807x_led_parse_netdev(struct phy_device *phydev, unsigned long rules,
++				    u16 *offload_trigger)
++{
++	/* Parsing specific to netdev trigger */
++	switch (phydev->port) {
++	case PORT_TP:
++		if (test_bit(TRIGGER_NETDEV_TX, &rules))
++			*offload_trigger |= QCA808X_LED_TX_BLINK;
++		if (test_bit(TRIGGER_NETDEV_RX, &rules))
++			*offload_trigger |= QCA808X_LED_RX_BLINK;
++		if (test_bit(TRIGGER_NETDEV_LINK_10, &rules))
++			*offload_trigger |= QCA808X_LED_SPEED10_ON;
++		if (test_bit(TRIGGER_NETDEV_LINK_100, &rules))
++			*offload_trigger |= QCA808X_LED_SPEED100_ON;
++		if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules))
++			*offload_trigger |= QCA808X_LED_SPEED1000_ON;
++		if (test_bit(TRIGGER_NETDEV_HALF_DUPLEX, &rules))
++			*offload_trigger |= QCA808X_LED_HALF_DUPLEX_ON;
++		if (test_bit(TRIGGER_NETDEV_FULL_DUPLEX, &rules))
++			*offload_trigger |= QCA808X_LED_FULL_DUPLEX_ON;
++		break;
++	case PORT_FIBRE:
++		if (test_bit(TRIGGER_NETDEV_TX, &rules))
++			*offload_trigger |= QCA807X_LED_FIBER_TXACT_BLK_EN;
++		if (test_bit(TRIGGER_NETDEV_RX, &rules))
++			*offload_trigger |= QCA807X_LED_FIBER_RXACT_BLK_EN;
++		if (test_bit(TRIGGER_NETDEV_LINK_100, &rules))
++			*offload_trigger |= QCA807X_LED_FIBER_100FX_ON_EN;
++		if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules))
++			*offload_trigger |= QCA807X_LED_FIBER_1000BX_ON_EN;
++		if (test_bit(TRIGGER_NETDEV_HALF_DUPLEX, &rules))
++			*offload_trigger |= QCA807X_LED_FIBER_HDX_ON_EN;
++		if (test_bit(TRIGGER_NETDEV_FULL_DUPLEX, &rules))
++			*offload_trigger |= QCA807X_LED_FIBER_FDX_ON_EN;
++		break;
++	default:
++		return -EOPNOTSUPP;
++	}
++
++	if (rules && !*offload_trigger)
++		return -EOPNOTSUPP;
++
++	return 0;
++}
++
++static int qca807x_led_hw_control_enable(struct phy_device *phydev, u8 index)
++{
++	u16 reg;
++
++	if (index > 1)
++		return -EINVAL;
++
++	reg = QCA807X_MMD7_LED_FORCE_CTRL(index);
++	return qca808x_led_reg_hw_control_enable(phydev, reg);
++}
++
++static int qca807x_led_hw_is_supported(struct phy_device *phydev, u8 index,
++				       unsigned long rules)
++{
++	u16 offload_trigger = 0;
++
++	if (index > 1)
++		return -EINVAL;
++
++	return qca807x_led_parse_netdev(phydev, rules, &offload_trigger);
++}
++
++static int qca807x_led_hw_control_set(struct phy_device *phydev, u8 index,
++				      unsigned long rules)
++{
++	u16 reg, mask, offload_trigger = 0;
++	int ret;
++
++	if (index > 1)
++		return -EINVAL;
++
++	ret = qca807x_led_parse_netdev(phydev, rules, &offload_trigger);
++	if (ret)
++		return ret;
++
++	ret = qca807x_led_hw_control_enable(phydev, index);
++	if (ret)
++		return ret;
++
++	switch (phydev->port) {
++	case PORT_TP:
++		reg = QCA807X_MMD7_LED_CTRL(index);
++		mask = QCA808X_LED_PATTERN_MASK;
++		break;
++	case PORT_FIBRE:
++		/* HW control pattern bits are in LED FORCE reg */
++		reg = QCA807X_MMD7_LED_FORCE_CTRL(index);
++		mask = QCA807X_LED_FIBER_PATTERN_MASK;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	return phy_modify_mmd(phydev, MDIO_MMD_AN, reg, mask,
++			      offload_trigger);
++}
++
++static bool qca807x_led_hw_control_status(struct phy_device *phydev, u8 index)
++{
++	u16 reg;
++
++	if (index > 1)
++		return false;
++
++	reg = QCA807X_MMD7_LED_FORCE_CTRL(index);
++	return qca808x_led_reg_hw_control_status(phydev, reg);
++}
++
++static int qca807x_led_hw_control_get(struct phy_device *phydev, u8 index,
++				      unsigned long *rules)
++{
++	u16 reg;
++	int val;
++
++	if (index > 1)
++		return -EINVAL;
++
++	/* Check if we have hw control enabled */
++	if (qca807x_led_hw_control_status(phydev, index))
++		return -EINVAL;
++
++	/* Parsing specific to netdev trigger */
++	switch (phydev->port) {
++	case PORT_TP:
++		reg = QCA807X_MMD7_LED_CTRL(index);
++		val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
++		if (val & QCA808X_LED_TX_BLINK)
++			set_bit(TRIGGER_NETDEV_TX, rules);
++		if (val & QCA808X_LED_RX_BLINK)
++			set_bit(TRIGGER_NETDEV_RX, rules);
++		if (val & QCA808X_LED_SPEED10_ON)
++			set_bit(TRIGGER_NETDEV_LINK_10, rules);
++		if (val & QCA808X_LED_SPEED100_ON)
++			set_bit(TRIGGER_NETDEV_LINK_100, rules);
++		if (val & QCA808X_LED_SPEED1000_ON)
++			set_bit(TRIGGER_NETDEV_LINK_1000, rules);
++		if (val & QCA808X_LED_HALF_DUPLEX_ON)
++			set_bit(TRIGGER_NETDEV_HALF_DUPLEX, rules);
++		if (val & QCA808X_LED_FULL_DUPLEX_ON)
++			set_bit(TRIGGER_NETDEV_FULL_DUPLEX, rules);
++		break;
++	case PORT_FIBRE:
++		/* HW control pattern bits are in LED FORCE reg */
++		reg = QCA807X_MMD7_LED_FORCE_CTRL(index);
++		val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
++		if (val & QCA807X_LED_FIBER_TXACT_BLK_EN)
++			set_bit(TRIGGER_NETDEV_TX, rules);
++		if (val & QCA807X_LED_FIBER_RXACT_BLK_EN)
++			set_bit(TRIGGER_NETDEV_RX, rules);
++		if (val & QCA807X_LED_FIBER_100FX_ON_EN)
++			set_bit(TRIGGER_NETDEV_LINK_100, rules);
++		if (val & QCA807X_LED_FIBER_1000BX_ON_EN)
++			set_bit(TRIGGER_NETDEV_LINK_1000, rules);
++		if (val & QCA807X_LED_FIBER_HDX_ON_EN)
++			set_bit(TRIGGER_NETDEV_HALF_DUPLEX, rules);
++		if (val & QCA807X_LED_FIBER_FDX_ON_EN)
++			set_bit(TRIGGER_NETDEV_FULL_DUPLEX, rules);
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int qca807x_led_hw_control_reset(struct phy_device *phydev, u8 index)
++{
++	u16 reg, mask;
++
++	if (index > 1)
++		return -EINVAL;
++
++	switch (phydev->port) {
++	case PORT_TP:
++		reg = QCA807X_MMD7_LED_CTRL(index);
++		mask = QCA808X_LED_PATTERN_MASK;
++		break;
++	case PORT_FIBRE:
++		/* HW control pattern bits are in LED FORCE reg */
++		reg = QCA807X_MMD7_LED_FORCE_CTRL(index);
++		mask = QCA807X_LED_FIBER_PATTERN_MASK;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg, mask);
++}
++
++static int qca807x_led_brightness_set(struct phy_device *phydev,
++				      u8 index, enum led_brightness value)
++{
++	u16 reg;
++	int ret;
++
++	if (index > 1)
++		return -EINVAL;
++
++	/* If we are setting off the LED reset any hw control rule */
++	if (!value) {
++		ret = qca807x_led_hw_control_reset(phydev, index);
++		if (ret)
++			return ret;
++	}
++
++	reg = QCA807X_MMD7_LED_FORCE_CTRL(index);
++	return qca808x_led_reg_brightness_set(phydev, reg, value);
++}
++
++static int qca807x_led_blink_set(struct phy_device *phydev, u8 index,
++				 unsigned long *delay_on,
++				 unsigned long *delay_off)
++{
++	u16 reg;
++
++	if (index > 1)
++		return -EINVAL;
++
++	reg = QCA807X_MMD7_LED_FORCE_CTRL(index);
++	return qca808x_led_reg_blink_set(phydev, reg, delay_on, delay_off);
++}
++
+ #ifdef CONFIG_GPIOLIB
+ static int qca807x_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
+ {
+@@ -496,6 +733,16 @@ static int qca807x_probe(struct phy_devi
+ 								     "qcom,dac-disable-bias-current-tweak");
+ 
+ 	if (IS_ENABLED(CONFIG_GPIOLIB)) {
++		/* Make sure we don't have mixed leds node and gpio-controller
++		 * to prevent registering leds and having gpio-controller usage
++		 * conflicting with them.
++		 */
++		if (of_find_property(node, "leds", NULL) &&
++		    of_find_property(node, "gpio-controller", NULL)) {
++			phydev_err(phydev, "Invalid property detected. LEDs and gpio-controller are mutually exclusive.");
++			return -EINVAL;
++		}
++
+ 		/* Do not register a GPIO controller unless flagged for it */
+ 		if (of_property_read_bool(node, "gpio-controller")) {
+ 			ret = qca807x_gpio(phydev);
+@@ -580,6 +827,11 @@ static struct phy_driver qca807x_drivers
+ 		.suspend	= genphy_suspend,
+ 		.cable_test_start	= qca807x_cable_test_start,
+ 		.cable_test_get_status	= qca808x_cable_test_get_status,
++		.led_brightness_set = qca807x_led_brightness_set,
++		.led_blink_set = qca807x_led_blink_set,
++		.led_hw_is_supported = qca807x_led_hw_is_supported,
++		.led_hw_control_set = qca807x_led_hw_control_set,
++		.led_hw_control_get = qca807x_led_hw_control_get,
+ 	},
+ };
+ module_phy_driver(qca807x_drivers);
diff --git a/target/linux/generic/backport-6.1/717-v6.9-net-phy-qca807x-move-interface-mode-check-to-.config.patch b/target/linux/generic/backport-6.1/717-v6.9-net-phy-qca807x-move-interface-mode-check-to-.config.patch
new file mode 100644
index 00000000000000..53652c38fc0561
--- /dev/null
+++ b/target/linux/generic/backport-6.1/717-v6.9-net-phy-qca807x-move-interface-mode-check-to-.config.patch
@@ -0,0 +1,51 @@
+From 3be0d950b62852a693182cb678948f481de02825 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Mon, 12 Feb 2024 12:49:34 +0100
+Subject: [PATCH] net: phy: qca807x: move interface mode check to
+ .config_init_once
+
+Currently, we are checking whether the PHY package mode matches the
+individual PHY interface modes at PHY package probe time, but at that time
+we only know the PHY package mode and not the individual PHY interface
+modes as of_get_phy_mode() that populates it will only get called once the
+netdev to which PHY-s are attached to is being probed and thus this check
+will always fail and return -EINVAL.
+
+So, lets move this check to .config_init_once as at that point individual
+PHY interface modes should be populated.
+
+Fixes: d1cb613efbd3 ("net: phy: qcom: add support for QCA807x PHY Family")
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://lore.kernel.org/r/20240212115043.1725918-1-robimarko@gmail.com
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/phy/qcom/qca807x.c | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+--- a/drivers/net/phy/qcom/qca807x.c
++++ b/drivers/net/phy/qcom/qca807x.c
+@@ -562,6 +562,11 @@ static int qca807x_phy_package_config_in
+ 	struct qca807x_shared_priv *priv = shared->priv;
+ 	int val, ret;
+ 
++	/* Make sure PHY follow PHY package mode if enforced */
++	if (priv->package_mode != PHY_INTERFACE_MODE_NA &&
++	    phydev->interface != priv->package_mode)
++		return -EINVAL;
++
+ 	phy_lock_mdio_bus(phydev);
+ 
+ 	/* Set correct PHY package mode */
+@@ -718,11 +723,6 @@ static int qca807x_probe(struct phy_devi
+ 	shared = phydev->shared;
+ 	shared_priv = shared->priv;
+ 
+-	/* Make sure PHY follow PHY package mode if enforced */
+-	if (shared_priv->package_mode != PHY_INTERFACE_MODE_NA &&
+-	    phydev->interface != shared_priv->package_mode)
+-		return -EINVAL;
+-
+ 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ 	if (!priv)
+ 		return -ENOMEM;
diff --git a/target/linux/generic/backport-6.1/720-v6.9-net-mdio-ipq4019-add-support-for-clock-frequency-pro.patch b/target/linux/generic/backport-6.1/720-v6.9-net-mdio-ipq4019-add-support-for-clock-frequency-pro.patch
new file mode 100644
index 00000000000000..e6a240dbdae9ea
--- /dev/null
+++ b/target/linux/generic/backport-6.1/720-v6.9-net-mdio-ipq4019-add-support-for-clock-frequency-pro.patch
@@ -0,0 +1,205 @@
+From bdce82e960d1205d118662f575cec39379984e34 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Wed, 31 Jan 2024 03:26:04 +0100
+Subject: [PATCH] net: mdio: ipq4019: add support for clock-frequency property
+
+The IPQ4019 MDIO internally divide the clock feed by AHB based on the
+MDIO_MODE reg. On reset or power up, the default value for the
+divider is 0xff that reflect the divider set to /256.
+
+This makes the MDC run at a very low rate, that is, considering AHB is
+always fixed to 100Mhz, a value of 390KHz.
+
+This hasn't have been a problem as MDIO wasn't used for time sensitive
+operation, it is now that on IPQ807x is usually mounted with PHY that
+requires MDIO to load their firmware (example Aquantia PHY).
+
+To handle this problem and permit to set the correct designed MDC
+frequency for the SoC add support for the standard "clock-frequency"
+property for the MDIO node.
+
+The divider supports value from /1 to /256 and the common value are to
+set it to /16 to reflect 6.25Mhz or to /8 on newer platform to reflect
+12.5Mhz.
+
+To scan if the requested rate is supported by the divider, loop with
+each supported divider and stop when the requested rate match the final
+rate with the current divider. An error is returned if the rate doesn't
+match any value.
+
+On MDIO reset, the divider is restored to the requested value to prevent
+any kind of downclocking caused by the divider reverting to a default
+value.
+
+To follow 802.3 spec of 2.5MHz of default value, if divider is set at
+/256 and "clock-frequency" is not set in DT, assume nobody set the
+divider and try to find the closest MDC rate to 2.5MHz. (in the case of
+AHB set to 100MHz, it's 1.5625MHz)
+
+While at is also document other bits of the MDIO_MODE reg to have a
+clear idea of what is actually applied there.
+
+Documentation of some BITs is skipped as they are marked as reserved and
+their usage is not clear (RES 11:9 GENPHY 16:13 RES1 19:17)
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/mdio/mdio-ipq4019.c | 109 ++++++++++++++++++++++++++++++--
+ 1 file changed, 103 insertions(+), 6 deletions(-)
+
+--- a/drivers/net/mdio/mdio-ipq4019.c
++++ b/drivers/net/mdio/mdio-ipq4019.c
+@@ -14,6 +14,20 @@
+ #include <linux/clk.h>
+ 
+ #define MDIO_MODE_REG				0x40
++#define   MDIO_MODE_MDC_MODE			BIT(12)
++/* 0 = Clause 22, 1 = Clause 45 */
++#define   MDIO_MODE_C45				BIT(8)
++#define   MDIO_MODE_DIV_MASK			GENMASK(7, 0)
++#define     MDIO_MODE_DIV(x)			FIELD_PREP(MDIO_MODE_DIV_MASK, (x) - 1)
++#define     MDIO_MODE_DIV_1			0x0
++#define     MDIO_MODE_DIV_2			0x1
++#define     MDIO_MODE_DIV_4			0x3
++#define     MDIO_MODE_DIV_8			0x7
++#define     MDIO_MODE_DIV_16			0xf
++#define     MDIO_MODE_DIV_32			0x1f
++#define     MDIO_MODE_DIV_64			0x3f
++#define     MDIO_MODE_DIV_128			0x7f
++#define     MDIO_MODE_DIV_256			0xff
+ #define MDIO_ADDR_REG				0x44
+ #define MDIO_DATA_WRITE_REG			0x48
+ #define MDIO_DATA_READ_REG			0x4c
+@@ -26,9 +40,6 @@
+ #define MDIO_CMD_ACCESS_CODE_C45_WRITE	1
+ #define MDIO_CMD_ACCESS_CODE_C45_READ	2
+ 
+-/* 0 = Clause 22, 1 = Clause 45 */
+-#define MDIO_MODE_C45				BIT(8)
+-
+ #define IPQ4019_MDIO_TIMEOUT	10000
+ #define IPQ4019_MDIO_SLEEP		10
+ 
+@@ -41,6 +52,7 @@ struct ipq4019_mdio_data {
+ 	void __iomem	*membase;
+ 	void __iomem *eth_ldo_rdy;
+ 	struct clk *mdio_clk;
++	unsigned int mdc_rate;
+ };
+ 
+ static int ipq4019_mdio_wait_busy(struct mii_bus *bus)
+@@ -179,6 +191,38 @@ static int ipq4019_mdio_write(struct mii
+ 	return 0;
+ }
+ 
++static int ipq4019_mdio_set_div(struct ipq4019_mdio_data *priv)
++{
++	unsigned long ahb_rate;
++	int div;
++	u32 val;
++
++	/* If we don't have a clock for AHB use the fixed value */
++	ahb_rate = IPQ_MDIO_CLK_RATE;
++	if (priv->mdio_clk)
++		ahb_rate = clk_get_rate(priv->mdio_clk);
++
++	/* MDC rate is ahb_rate/(MDIO_MODE_DIV + 1)
++	 * While supported, internal documentation doesn't
++	 * assure correct functionality of the MDIO bus
++	 * with divider of 1, 2 or 4.
++	 */
++	for (div = 8; div <= 256; div *= 2) {
++		/* The requested rate is supported by the div */
++		if (priv->mdc_rate == DIV_ROUND_UP(ahb_rate, div)) {
++			val = readl(priv->membase + MDIO_MODE_REG);
++			val &= ~MDIO_MODE_DIV_MASK;
++			val |= MDIO_MODE_DIV(div);
++			writel(val, priv->membase + MDIO_MODE_REG);
++
++			return 0;
++		}
++	}
++
++	/* The requested rate is not supported */
++	return -EINVAL;
++}
++
+ static int ipq_mdio_reset(struct mii_bus *bus)
+ {
+ 	struct ipq4019_mdio_data *priv = bus->priv;
+@@ -201,10 +245,58 @@ static int ipq_mdio_reset(struct mii_bus
+ 		return ret;
+ 
+ 	ret = clk_prepare_enable(priv->mdio_clk);
+-	if (ret == 0)
+-		mdelay(10);
++	if (ret)
++		return ret;
++
++	mdelay(10);
+ 
+-	return ret;
++	/* Restore MDC rate */
++	return ipq4019_mdio_set_div(priv);
++}
++
++static void ipq4019_mdio_select_mdc_rate(struct platform_device *pdev,
++					 struct ipq4019_mdio_data *priv)
++{
++	unsigned long ahb_rate;
++	int div;
++	u32 val;
++
++	/* MDC rate defined in DT, we don't have to decide a default value */
++	if (!of_property_read_u32(pdev->dev.of_node, "clock-frequency",
++				  &priv->mdc_rate))
++		return;
++
++	/* If we don't have a clock for AHB use the fixed value */
++	ahb_rate = IPQ_MDIO_CLK_RATE;
++	if (priv->mdio_clk)
++		ahb_rate = clk_get_rate(priv->mdio_clk);
++
++	/* Check what is the current div set */
++	val = readl(priv->membase + MDIO_MODE_REG);
++	div = FIELD_GET(MDIO_MODE_DIV_MASK, val);
++
++	/* div is not set to the default value of /256
++	 * Probably someone changed that (bootloader, other drivers)
++	 * Keep this and don't overwrite it.
++	 */
++	if (div != MDIO_MODE_DIV_256) {
++		priv->mdc_rate = DIV_ROUND_UP(ahb_rate, div + 1);
++		return;
++	}
++
++	/* If div is /256 assume nobody have set this value and
++	 * try to find one MDC rate that is close the 802.3 spec of
++	 * 2.5MHz
++	 */
++	for (div = 256; div >= 8; div /= 2) {
++		/* Stop as soon as we found a divider that
++		 * reached the closest value to 2.5MHz
++		 */
++		if (DIV_ROUND_UP(ahb_rate, div) > 2500000)
++			break;
++
++		priv->mdc_rate = DIV_ROUND_UP(ahb_rate, div);
++	}
+ }
+ 
+ static int ipq4019_mdio_probe(struct platform_device *pdev)
+@@ -228,6 +320,11 @@ static int ipq4019_mdio_probe(struct pla
+ 	if (IS_ERR(priv->mdio_clk))
+ 		return PTR_ERR(priv->mdio_clk);
+ 
++	ipq4019_mdio_select_mdc_rate(pdev, priv);
++	ret = ipq4019_mdio_set_div(priv);
++	if (ret)
++		return ret;
++
+ 	/* The platform resource is provided on the chipset IPQ5018 */
+ 	/* This resource is optional */
+ 	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
diff --git a/target/linux/generic/backport-6.1/721-v6.7-net-phy-aquantia-drop-wrong-endianness-conversion-fo.patch b/target/linux/generic/backport-6.1/721-v6.7-net-phy-aquantia-drop-wrong-endianness-conversion-fo.patch
new file mode 100644
index 00000000000000..d32a7edf93cdcb
--- /dev/null
+++ b/target/linux/generic/backport-6.1/721-v6.7-net-phy-aquantia-drop-wrong-endianness-conversion-fo.patch
@@ -0,0 +1,92 @@
+From 7edce370d87a23e8ed46af5b76a9fef1e341b67b Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Tue, 28 Nov 2023 14:59:28 +0100
+Subject: [PATCH] net: phy: aquantia: drop wrong endianness conversion for addr
+ and CRC
+
+On further testing on BE target with kernel test robot, it was notice
+that the endianness conversion for addr and CRC in fw_load_memory was
+wrong.
+
+Drop the cpu_to_le32 conversion for addr load as it's not needed.
+
+Use get_unaligned_le32 instead of get_unaligned for FW data word load to
+correctly convert data in the correct order to follow system endian.
+
+Also drop the cpu_to_be32 for CRC calculation as it's wrong and would
+cause different CRC on BE system.
+The loaded word is swapped internally and MAILBOX calculates the CRC on
+the swapped word. To correctly calculate the CRC to be later matched
+with the one from MAILBOX, use an u8 struct and swap the word there to
+keep the same order on both LE and BE for crc_ccitt_false function.
+Also add additional comments on how the CRC verification for the loaded
+section works.
+
+CRC is calculated as we load the section and verified with the MAILBOX
+only after the entire section is loaded to skip additional slowdown by
+loop the section data again.
+
+Reported-by: kernel test robot <lkp@intel.com>
+Closes: https://lore.kernel.org/oe-kbuild-all/202311210414.sEJZjlcD-lkp@intel.com/
+Fixes: e93984ebc1c8 ("net: phy: aquantia: add firmware load support")
+Tested-by: Robert Marko <robimarko@gmail.com> # ipq8072 LE device
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Link: https://lore.kernel.org/r/20231128135928.9841-1-ansuelsmth@gmail.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/aquantia/aquantia_firmware.c | 24 ++++++++++++--------
+ 1 file changed, 14 insertions(+), 10 deletions(-)
+
+--- a/drivers/net/phy/aquantia/aquantia_firmware.c
++++ b/drivers/net/phy/aquantia/aquantia_firmware.c
+@@ -93,9 +93,6 @@ static int aqr_fw_load_memory(struct phy
+ 	u16 crc = 0, up_crc;
+ 	size_t pos;
+ 
+-	/* PHY expect addr in LE */
+-	addr = (__force u32)cpu_to_le32(addr);
+-
+ 	phy_write_mmd(phydev, MDIO_MMD_VEND1,
+ 		      VEND1_GLOBAL_MAILBOX_INTERFACE1,
+ 		      VEND1_GLOBAL_MAILBOX_INTERFACE1_CRC_RESET);
+@@ -110,10 +107,11 @@ static int aqr_fw_load_memory(struct phy
+ 	 * If a firmware that is not word aligned is found, please report upstream.
+ 	 */
+ 	for (pos = 0; pos < len; pos += sizeof(u32)) {
++		u8 crc_data[4];
+ 		u32 word;
+ 
+ 		/* FW data is always stored in little-endian */
+-		word = get_unaligned((const u32 *)(data + pos));
++		word = get_unaligned_le32((const u32 *)(data + pos));
+ 
+ 		phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_MAILBOX_INTERFACE5,
+ 			      VEND1_GLOBAL_MAILBOX_INTERFACE5_MSW_DATA(word));
+@@ -124,15 +122,21 @@ static int aqr_fw_load_memory(struct phy
+ 			      VEND1_GLOBAL_MAILBOX_INTERFACE1_EXECUTE |
+ 			      VEND1_GLOBAL_MAILBOX_INTERFACE1_WRITE);
+ 
+-		/* calculate CRC as we load data to the mailbox.
+-		 * We convert word to big-endian as PHY is BE and mailbox will
+-		 * return a BE CRC.
++		/* Word is swapped internally and MAILBOX CRC is calculated
++		 * using big-endian order. Mimic what the PHY does to have a
++		 * matching CRC...
+ 		 */
+-		word = (__force u32)cpu_to_be32(word);
+-		crc = crc_ccitt_false(crc, (u8 *)&word, sizeof(word));
+-	}
++		crc_data[0] = word >> 24;
++		crc_data[1] = word >> 16;
++		crc_data[2] = word >> 8;
++		crc_data[3] = word;
+ 
++		/* ...calculate CRC as we load data... */
++		crc = crc_ccitt_false(crc, crc_data, sizeof(crc_data));
++	}
++	/* ...gets CRC from MAILBOX after we have loaded the entire section... */
+ 	up_crc = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_MAILBOX_INTERFACE2);
++	/* ...and make sure it does match our calculated CRC */
+ 	if (crc != up_crc) {
+ 		phydev_err(phydev, "CRC mismatch: calculated 0x%04x PHY 0x%04x\n",
+ 			   crc, up_crc);
diff --git a/target/linux/generic/backport-6.1/724-v6.2-net-ethernet-mtk_eth_soc-enable-flow-offloading-supp.patch b/target/linux/generic/backport-6.1/724-v6.2-net-ethernet-mtk_eth_soc-enable-flow-offloading-supp.patch
index 55267916242a99..816aa67787d5f8 100644
--- a/target/linux/generic/backport-6.1/724-v6.2-net-ethernet-mtk_eth_soc-enable-flow-offloading-supp.patch
+++ b/target/linux/generic/backport-6.1/724-v6.2-net-ethernet-mtk_eth_soc-enable-flow-offloading-supp.patch
@@ -16,7 +16,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -4334,6 +4334,7 @@ static const struct mtk_soc_data mt7986_
+@@ -4333,6 +4333,7 @@ static const struct mtk_soc_data mt7986_
  	.hw_features = MTK_HW_FEATURES,
  	.required_clks = MT7986_CLKS_BITMAP,
  	.required_pctl = false,
diff --git a/target/linux/generic/backport-6.1/729-07-v6.1-net-ethernet-mtk_eth_soc-remove-cpu_relax-in-mtk_pen.patch b/target/linux/generic/backport-6.1/729-07-v6.1-net-ethernet-mtk_eth_soc-remove-cpu_relax-in-mtk_pen.patch
index 95a21e1c9a39d7..cefe1eefff2ca7 100644
--- a/target/linux/generic/backport-6.1/729-07-v6.1-net-ethernet-mtk_eth_soc-remove-cpu_relax-in-mtk_pen.patch
+++ b/target/linux/generic/backport-6.1/729-07-v6.1-net-ethernet-mtk_eth_soc-remove-cpu_relax-in-mtk_pen.patch
@@ -12,7 +12,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -3481,11 +3481,8 @@ static void mtk_pending_work(struct work
+@@ -3480,11 +3480,8 @@ static void mtk_pending_work(struct work
  	rtnl_lock();
  
  	dev_dbg(eth->dev, "[%s][%d] reset\n", __func__, __LINE__);
@@ -25,7 +25,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	/* stop all devices to make sure that dma is properly shut down */
  	for (i = 0; i < MTK_MAC_COUNT; i++) {
  		if (!eth->netdev[i])
-@@ -3519,7 +3516,7 @@ static void mtk_pending_work(struct work
+@@ -3518,7 +3515,7 @@ static void mtk_pending_work(struct work
  
  	dev_dbg(eth->dev, "[%s][%d] reset done\n", __func__, __LINE__);
  
diff --git a/target/linux/generic/backport-6.1/729-18-v6.3-net-ethernet-mtk_eth_soc-introduce-mtk_hw_reset-util.patch b/target/linux/generic/backport-6.1/729-18-v6.3-net-ethernet-mtk_eth_soc-introduce-mtk_hw_reset-util.patch
index 8bdbfc29279982..c91861a8f11a3e 100644
--- a/target/linux/generic/backport-6.1/729-18-v6.3-net-ethernet-mtk_eth_soc-introduce-mtk_hw_reset-util.patch
+++ b/target/linux/generic/backport-6.1/729-18-v6.3-net-ethernet-mtk_eth_soc-introduce-mtk_hw_reset-util.patch
@@ -16,7 +16,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -3257,6 +3257,27 @@ static void mtk_set_mcr_max_rx(struct mt
+@@ -3256,6 +3256,27 @@ static void mtk_set_mcr_max_rx(struct mt
  		mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id));
  }
  
@@ -44,7 +44,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  static int mtk_hw_init(struct mtk_eth *eth)
  {
  	u32 dma_mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA |
-@@ -3296,22 +3317,9 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -3295,22 +3316,9 @@ static int mtk_hw_init(struct mtk_eth *e
  		return 0;
  	}
  
diff --git a/target/linux/generic/backport-6.1/729-19-v6.3-net-ethernet-mtk_eth_soc-introduce-mtk_hw_warm_reset.patch b/target/linux/generic/backport-6.1/729-19-v6.3-net-ethernet-mtk_eth_soc-introduce-mtk_hw_warm_reset.patch
index 712b6a2d3afeee..6597eb5b7468c2 100644
--- a/target/linux/generic/backport-6.1/729-19-v6.3-net-ethernet-mtk_eth_soc-introduce-mtk_hw_warm_reset.patch
+++ b/target/linux/generic/backport-6.1/729-19-v6.3-net-ethernet-mtk_eth_soc-introduce-mtk_hw_warm_reset.patch
@@ -17,7 +17,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -3278,7 +3278,54 @@ static void mtk_hw_reset(struct mtk_eth
+@@ -3277,7 +3277,54 @@ static void mtk_hw_reset(struct mtk_eth
  			     0x3ffffff);
  }
  
@@ -73,7 +73,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  {
  	u32 dma_mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA |
  		       ETHSYS_DMA_AG_MAP_PPE;
-@@ -3317,7 +3364,12 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -3316,7 +3363,12 @@ static int mtk_hw_init(struct mtk_eth *e
  		return 0;
  	}
  
@@ -87,7 +87,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
  		/* Set FE to PDMAv2 if necessary */
-@@ -3508,7 +3560,7 @@ static void mtk_pending_work(struct work
+@@ -3507,7 +3559,7 @@ static void mtk_pending_work(struct work
  	if (eth->dev->pins)
  		pinctrl_select_state(eth->dev->pins->p,
  				     eth->dev->pins->default_state);
@@ -96,7 +96,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  	/* restart DMA and enable IRQs */
  	for (i = 0; i < MTK_MAC_COUNT; i++) {
-@@ -4110,7 +4162,7 @@ static int mtk_probe(struct platform_dev
+@@ -4109,7 +4161,7 @@ static int mtk_probe(struct platform_dev
  	eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
  	INIT_WORK(&eth->pending_work, mtk_pending_work);
  
diff --git a/target/linux/generic/backport-6.1/729-20-v6.3-net-ethernet-mtk_eth_soc-align-reset-procedure-to-ve.patch b/target/linux/generic/backport-6.1/729-20-v6.3-net-ethernet-mtk_eth_soc-align-reset-procedure-to-ve.patch
index 9da16ec56ccd8f..55ab19f4c8df69 100644
--- a/target/linux/generic/backport-6.1/729-20-v6.3-net-ethernet-mtk_eth_soc-align-reset-procedure-to-ve.patch
+++ b/target/linux/generic/backport-6.1/729-20-v6.3-net-ethernet-mtk_eth_soc-align-reset-procedure-to-ve.patch
@@ -16,7 +16,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -2845,14 +2845,29 @@ static void mtk_dma_free(struct mtk_eth
+@@ -2844,14 +2844,29 @@ static void mtk_dma_free(struct mtk_eth
  	kfree(eth->scratch_head);
  }
  
@@ -48,7 +48,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	schedule_work(&eth->pending_work);
  }
  
-@@ -3332,15 +3347,17 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -3331,15 +3346,17 @@ static int mtk_hw_init(struct mtk_eth *e
  	const struct mtk_reg_map *reg_map = eth->soc->reg_map;
  	int i, val, ret;
  
@@ -72,7 +72,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  	if (eth->ethsys)
  		regmap_update_bits(eth->ethsys, ETHSYS_DMA_AG_MAP, dma_mask,
-@@ -3469,8 +3486,10 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -3468,8 +3485,10 @@ static int mtk_hw_init(struct mtk_eth *e
  	return 0;
  
  err_disable_pm:
@@ -85,7 +85,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  	return ret;
  }
-@@ -3532,30 +3551,53 @@ static int mtk_do_ioctl(struct net_devic
+@@ -3531,30 +3550,53 @@ static int mtk_do_ioctl(struct net_devic
  	return -EOPNOTSUPP;
  }
  
@@ -148,7 +148,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  	if (eth->dev->pins)
  		pinctrl_select_state(eth->dev->pins->p,
-@@ -3566,15 +3608,19 @@ static void mtk_pending_work(struct work
+@@ -3565,15 +3607,19 @@ static void mtk_pending_work(struct work
  	for (i = 0; i < MTK_MAC_COUNT; i++) {
  		if (!test_bit(i, &restart))
  			continue;
diff --git a/target/linux/generic/backport-6.1/729-21-v6.3-net-ethernet-mtk_eth_soc-add-dma-checks-to-mtk_hw_re.patch b/target/linux/generic/backport-6.1/729-21-v6.3-net-ethernet-mtk_eth_soc-add-dma-checks-to-mtk_hw_re.patch
index 96ebc874814fb8..d5a7c0eba2a0e4 100644
--- a/target/linux/generic/backport-6.1/729-21-v6.3-net-ethernet-mtk_eth_soc-add-dma-checks-to-mtk_hw_re.patch
+++ b/target/linux/generic/backport-6.1/729-21-v6.3-net-ethernet-mtk_eth_soc-add-dma-checks-to-mtk_hw_re.patch
@@ -49,7 +49,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  };
  
  /* strings used by ethtool */
-@@ -3340,6 +3346,102 @@ static void mtk_hw_warm_reset(struct mtk
+@@ -3339,6 +3345,102 @@ static void mtk_hw_warm_reset(struct mtk
  			val, rst_mask);
  }
  
@@ -152,7 +152,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  static int mtk_hw_init(struct mtk_eth *eth, bool reset)
  {
  	u32 dma_mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA |
-@@ -3658,6 +3760,7 @@ static int mtk_cleanup(struct mtk_eth *e
+@@ -3657,6 +3759,7 @@ static int mtk_cleanup(struct mtk_eth *e
  	mtk_unreg_dev(eth);
  	mtk_free_dev(eth);
  	cancel_work_sync(&eth->pending_work);
@@ -160,7 +160,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  	return 0;
  }
-@@ -4095,6 +4198,7 @@ static int mtk_probe(struct platform_dev
+@@ -4094,6 +4197,7 @@ static int mtk_probe(struct platform_dev
  
  	eth->rx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
  	INIT_WORK(&eth->rx_dim.work, mtk_dim_rx);
@@ -168,7 +168,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  	eth->tx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
  	INIT_WORK(&eth->tx_dim.work, mtk_dim_tx);
-@@ -4297,6 +4401,8 @@ static int mtk_probe(struct platform_dev
+@@ -4296,6 +4400,8 @@ static int mtk_probe(struct platform_dev
  	netif_napi_add(&eth->dummy_dev, &eth->rx_napi, mtk_napi_rx);
  
  	platform_set_drvdata(pdev, eth);
diff --git a/target/linux/generic/backport-6.1/729-22-v6.3-net-ethernet-mtk_wed-add-reset-reset_complete-callba.patch b/target/linux/generic/backport-6.1/729-22-v6.3-net-ethernet-mtk_wed-add-reset-reset_complete-callba.patch
index da1ce24b8ffe4b..c21d094ae849ba 100644
--- a/target/linux/generic/backport-6.1/729-22-v6.3-net-ethernet-mtk_wed-add-reset-reset_complete-callba.patch
+++ b/target/linux/generic/backport-6.1/729-22-v6.3-net-ethernet-mtk_wed-add-reset-reset_complete-callba.patch
@@ -14,7 +14,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -3689,6 +3689,11 @@ static void mtk_pending_work(struct work
+@@ -3688,6 +3688,11 @@ static void mtk_pending_work(struct work
  	set_bit(MTK_RESETTING, &eth->state);
  
  	mtk_prepare_for_reset(eth);
@@ -26,7 +26,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  	/* stop all devices to make sure that dma is properly shut down */
  	for (i = 0; i < MTK_MAC_COUNT; i++) {
-@@ -3726,6 +3731,8 @@ static void mtk_pending_work(struct work
+@@ -3725,6 +3730,8 @@ static void mtk_pending_work(struct work
  
  	clear_bit(MTK_RESETTING, &eth->state);
  
diff --git a/target/linux/generic/backport-6.1/730-02-v6.3-net-ethernet-mtk_eth_soc-increase-tx-ring-side-for-Q.patch b/target/linux/generic/backport-6.1/730-02-v6.3-net-ethernet-mtk_eth_soc-increase-tx-ring-side-for-Q.patch
index c3b8af0b2b7fe9..046a5812247a99 100644
--- a/target/linux/generic/backport-6.1/730-02-v6.3-net-ethernet-mtk_eth_soc-increase-tx-ring-side-for-Q.patch
+++ b/target/linux/generic/backport-6.1/730-02-v6.3-net-ethernet-mtk_eth_soc-increase-tx-ring-side-for-Q.patch
@@ -12,7 +12,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -945,7 +945,7 @@ static int mtk_init_fq_dma(struct mtk_et
+@@ -944,7 +944,7 @@ static int mtk_init_fq_dma(struct mtk_et
  {
  	const struct mtk_soc_data *soc = eth->soc;
  	dma_addr_t phy_ring_tail;
@@ -21,7 +21,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	dma_addr_t dma_addr;
  	int i;
  
-@@ -2209,19 +2209,25 @@ static int mtk_tx_alloc(struct mtk_eth *
+@@ -2208,19 +2208,25 @@ static int mtk_tx_alloc(struct mtk_eth *
  	struct mtk_tx_ring *ring = &eth->tx_ring;
  	int i, sz = soc->txrx.txd_size;
  	struct mtk_tx_dma_v2 *txd;
@@ -51,7 +51,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  		u32 next_ptr = ring->phys + next * sz;
  
  		txd = ring->dma + i * sz;
-@@ -2241,22 +2247,22 @@ static int mtk_tx_alloc(struct mtk_eth *
+@@ -2240,22 +2246,22 @@ static int mtk_tx_alloc(struct mtk_eth *
  	 * descriptors in ring->dma_pdma.
  	 */
  	if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
@@ -79,7 +79,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	ring->thresh = MAX_SKB_FRAGS;
  
  	/* make sure that all changes to the dma ring are flushed before we
-@@ -2268,14 +2274,14 @@ static int mtk_tx_alloc(struct mtk_eth *
+@@ -2267,14 +2273,14 @@ static int mtk_tx_alloc(struct mtk_eth *
  		mtk_w32(eth, ring->phys, soc->reg_map->qdma.ctx_ptr);
  		mtk_w32(eth, ring->phys, soc->reg_map->qdma.dtx_ptr);
  		mtk_w32(eth,
@@ -96,7 +96,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  		mtk_w32(eth, 0, MT7628_TX_CTX_IDX0);
  		mtk_w32(eth, MT7628_PST_DTX_IDX0, soc->reg_map->pdma.rst_idx);
  	}
-@@ -2293,7 +2299,7 @@ static void mtk_tx_clean(struct mtk_eth
+@@ -2292,7 +2298,7 @@ static void mtk_tx_clean(struct mtk_eth
  	int i;
  
  	if (ring->buf) {
@@ -105,7 +105,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  			mtk_tx_unmap(eth, &ring->buf[i], NULL, false);
  		kfree(ring->buf);
  		ring->buf = NULL;
-@@ -2301,14 +2307,14 @@ static void mtk_tx_clean(struct mtk_eth
+@@ -2300,14 +2306,14 @@ static void mtk_tx_clean(struct mtk_eth
  
  	if (ring->dma) {
  		dma_free_coherent(eth->dma_dev,
@@ -122,7 +122,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  				  ring->dma_pdma, ring->phys_pdma);
  		ring->dma_pdma = NULL;
  	}
-@@ -2833,7 +2839,7 @@ static void mtk_dma_free(struct mtk_eth
+@@ -2832,7 +2838,7 @@ static void mtk_dma_free(struct mtk_eth
  			netdev_reset_queue(eth->netdev[i]);
  	if (eth->scratch_ring) {
  		dma_free_coherent(eth->dma_dev,
diff --git a/target/linux/generic/backport-6.1/730-03-v6.3-net-ethernet-mtk_eth_soc-avoid-port_mg-assignment-on.patch b/target/linux/generic/backport-6.1/730-03-v6.3-net-ethernet-mtk_eth_soc-avoid-port_mg-assignment-on.patch
index bc794a5c8a0f9b..7e879ca1d5aad8 100644
--- a/target/linux/generic/backport-6.1/730-03-v6.3-net-ethernet-mtk_eth_soc-avoid-port_mg-assignment-on.patch
+++ b/target/linux/generic/backport-6.1/730-03-v6.3-net-ethernet-mtk_eth_soc-avoid-port_mg-assignment-on.patch
@@ -12,7 +12,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -4480,7 +4480,7 @@ static const struct mtk_soc_data mt7621_
+@@ -4479,7 +4479,7 @@ static const struct mtk_soc_data mt7621_
  	.hw_features = MTK_HW_FEATURES,
  	.required_clks = MT7621_CLKS_BITMAP,
  	.required_pctl = false,
@@ -21,7 +21,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	.hash_offset = 2,
  	.foe_entry_size = sizeof(struct mtk_foe_entry) - 16,
  	.txrx = {
-@@ -4519,7 +4519,7 @@ static const struct mtk_soc_data mt7623_
+@@ -4518,7 +4518,7 @@ static const struct mtk_soc_data mt7623_
  	.hw_features = MTK_HW_FEATURES,
  	.required_clks = MT7623_CLKS_BITMAP,
  	.required_pctl = true,
diff --git a/target/linux/generic/backport-6.1/730-04-v6.3-net-ethernet-mtk_eth_soc-implement-multi-queue-suppo.patch b/target/linux/generic/backport-6.1/730-04-v6.3-net-ethernet-mtk_eth_soc-implement-multi-queue-suppo.patch
index 48d9b31fef4300..8ceba7831e02ce 100644
--- a/target/linux/generic/backport-6.1/730-04-v6.3-net-ethernet-mtk_eth_soc-implement-multi-queue-suppo.patch
+++ b/target/linux/generic/backport-6.1/730-04-v6.3-net-ethernet-mtk_eth_soc-implement-multi-queue-suppo.patch
@@ -139,7 +139,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	/* Configure duplex */
  	if (duplex == DUPLEX_FULL)
  		mcr |= MAC_MCR_FORCE_DPX;
-@@ -1106,7 +1181,8 @@ static void mtk_tx_set_dma_desc_v1(struc
+@@ -1105,7 +1180,8 @@ static void mtk_tx_set_dma_desc_v1(struc
  
  	WRITE_ONCE(desc->txd1, info->addr);
  
@@ -149,7 +149,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	if (info->last)
  		data |= TX_DMA_LS0;
  	WRITE_ONCE(desc->txd3, data);
-@@ -1140,9 +1216,6 @@ static void mtk_tx_set_dma_desc_v2(struc
+@@ -1139,9 +1215,6 @@ static void mtk_tx_set_dma_desc_v2(struc
  		data |= TX_DMA_LS0;
  	WRITE_ONCE(desc->txd3, data);
  
@@ -159,7 +159,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	data = (mac->id + 1) << TX_DMA_FPORT_SHIFT_V2; /* forward port */
  	data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid);
  	WRITE_ONCE(desc->txd4, data);
-@@ -1186,11 +1259,12 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -1185,11 +1258,12 @@ static int mtk_tx_map(struct sk_buff *sk
  		.gso = gso,
  		.csum = skb->ip_summed == CHECKSUM_PARTIAL,
  		.vlan = skb_vlan_tag_present(skb),
@@ -173,7 +173,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	struct mtk_mac *mac = netdev_priv(dev);
  	struct mtk_eth *eth = mac->hw;
  	const struct mtk_soc_data *soc = eth->soc;
-@@ -1198,8 +1272,10 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -1197,8 +1271,10 @@ static int mtk_tx_map(struct sk_buff *sk
  	struct mtk_tx_dma *itxd_pdma, *txd_pdma;
  	struct mtk_tx_buf *itx_buf, *tx_buf;
  	int i, n_desc = 1;
@@ -184,7 +184,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	itxd = ring->next_free;
  	itxd_pdma = qdma_to_pdma(ring, itxd);
  	if (itxd == ring->last_free)
-@@ -1248,7 +1324,7 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -1247,7 +1323,7 @@ static int mtk_tx_map(struct sk_buff *sk
  			memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info));
  			txd_info.size = min_t(unsigned int, frag_size,
  					      soc->txrx.dma_max_len);
@@ -193,7 +193,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  			txd_info.last = i == skb_shinfo(skb)->nr_frags - 1 &&
  					!(frag_size - txd_info.size);
  			txd_info.addr = skb_frag_dma_map(eth->dma_dev, frag,
-@@ -1287,7 +1363,7 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -1286,7 +1362,7 @@ static int mtk_tx_map(struct sk_buff *sk
  			txd_pdma->txd2 |= TX_DMA_LS1;
  	}
  
@@ -202,7 +202,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	skb_tx_timestamp(skb);
  
  	ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
-@@ -1299,8 +1375,7 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -1298,8 +1374,7 @@ static int mtk_tx_map(struct sk_buff *sk
  	wmb();
  
  	if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
@@ -212,7 +212,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  			mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr);
  	} else {
  		int next_idx;
-@@ -1369,7 +1444,7 @@ static void mtk_wake_queue(struct mtk_et
+@@ -1368,7 +1443,7 @@ static void mtk_wake_queue(struct mtk_et
  	for (i = 0; i < MTK_MAC_COUNT; i++) {
  		if (!eth->netdev[i])
  			continue;
@@ -221,7 +221,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	}
  }
  
-@@ -1393,7 +1468,7 @@ static netdev_tx_t mtk_start_xmit(struct
+@@ -1392,7 +1467,7 @@ static netdev_tx_t mtk_start_xmit(struct
  
  	tx_num = mtk_cal_txd_req(eth, skb);
  	if (unlikely(atomic_read(&ring->free_count) <= tx_num)) {
@@ -230,7 +230,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  		netif_err(eth, tx_queued, dev,
  			  "Tx Ring full when queue awake!\n");
  		spin_unlock(&eth->page_lock);
-@@ -1419,7 +1494,7 @@ static netdev_tx_t mtk_start_xmit(struct
+@@ -1418,7 +1493,7 @@ static netdev_tx_t mtk_start_xmit(struct
  		goto drop;
  
  	if (unlikely(atomic_read(&ring->free_count) <= ring->thresh))
@@ -239,7 +239,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  	spin_unlock(&eth->page_lock);
  
-@@ -1586,10 +1661,12 @@ static int mtk_xdp_submit_frame(struct m
+@@ -1585,10 +1660,12 @@ static int mtk_xdp_submit_frame(struct m
  	struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf);
  	const struct mtk_soc_data *soc = eth->soc;
  	struct mtk_tx_ring *ring = &eth->tx_ring;
@@ -252,7 +252,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	};
  	int err, index = 0, n_desc = 1, nr_frags;
  	struct mtk_tx_buf *htx_buf, *tx_buf;
-@@ -1639,6 +1716,7 @@ static int mtk_xdp_submit_frame(struct m
+@@ -1638,6 +1715,7 @@ static int mtk_xdp_submit_frame(struct m
  		memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info));
  		txd_info.size = skb_frag_size(&sinfo->frags[index]);
  		txd_info.last = index + 1 == nr_frags;
@@ -260,7 +260,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  		data = skb_frag_address(&sinfo->frags[index]);
  
  		index++;
-@@ -1993,8 +2071,46 @@ rx_done:
+@@ -1992,8 +2070,46 @@ rx_done:
  	return done;
  }
  
@@ -308,7 +308,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  {
  	const struct mtk_reg_map *reg_map = eth->soc->reg_map;
  	struct mtk_tx_ring *ring = &eth->tx_ring;
-@@ -2026,12 +2142,9 @@ static int mtk_poll_tx_qdma(struct mtk_e
+@@ -2025,12 +2141,9 @@ static int mtk_poll_tx_qdma(struct mtk_e
  			break;
  
  		if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) {
@@ -323,7 +323,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  			budget--;
  		}
  		mtk_tx_unmap(eth, tx_buf, &bq, true);
-@@ -2050,7 +2163,7 @@ static int mtk_poll_tx_qdma(struct mtk_e
+@@ -2049,7 +2162,7 @@ static int mtk_poll_tx_qdma(struct mtk_e
  }
  
  static int mtk_poll_tx_pdma(struct mtk_eth *eth, int budget,
@@ -332,7 +332,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  {
  	struct mtk_tx_ring *ring = &eth->tx_ring;
  	struct mtk_tx_buf *tx_buf;
-@@ -2068,12 +2181,8 @@ static int mtk_poll_tx_pdma(struct mtk_e
+@@ -2067,12 +2180,8 @@ static int mtk_poll_tx_pdma(struct mtk_e
  			break;
  
  		if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) {
@@ -347,7 +347,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  			budget--;
  		}
  		mtk_tx_unmap(eth, tx_buf, &bq, true);
-@@ -2095,26 +2204,15 @@ static int mtk_poll_tx(struct mtk_eth *e
+@@ -2094,26 +2203,15 @@ static int mtk_poll_tx(struct mtk_eth *e
  {
  	struct mtk_tx_ring *ring = &eth->tx_ring;
  	struct dim_sample dim_sample = {};
@@ -379,7 +379,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  	dim_update_sample(eth->tx_events, eth->tx_packets, eth->tx_bytes,
  			  &dim_sample);
-@@ -2124,7 +2222,7 @@ static int mtk_poll_tx(struct mtk_eth *e
+@@ -2123,7 +2221,7 @@ static int mtk_poll_tx(struct mtk_eth *e
  	    (atomic_read(&ring->free_count) > ring->thresh))
  		mtk_wake_queue(eth);
  
@@ -388,7 +388,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  }
  
  static void mtk_handle_status_irq(struct mtk_eth *eth)
-@@ -2210,6 +2308,7 @@ static int mtk_tx_alloc(struct mtk_eth *
+@@ -2209,6 +2307,7 @@ static int mtk_tx_alloc(struct mtk_eth *
  	int i, sz = soc->txrx.txd_size;
  	struct mtk_tx_dma_v2 *txd;
  	int ring_size;
@@ -396,7 +396,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  	if (MTK_HAS_CAPS(soc->caps, MTK_QDMA))
  		ring_size = MTK_QDMA_RING_SIZE;
-@@ -2277,8 +2376,25 @@ static int mtk_tx_alloc(struct mtk_eth *
+@@ -2276,8 +2375,25 @@ static int mtk_tx_alloc(struct mtk_eth *
  			ring->phys + ((ring_size - 1) * sz),
  			soc->reg_map->qdma.crx_ptr);
  		mtk_w32(eth, ring->last_free_ptr, soc->reg_map->qdma.drx_ptr);
@@ -424,7 +424,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	} else {
  		mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0);
  		mtk_w32(eth, ring_size, MT7628_TX_MAX_CNT0);
-@@ -2963,7 +3079,7 @@ static int mtk_start_dma(struct mtk_eth
+@@ -2962,7 +3078,7 @@ static int mtk_start_dma(struct mtk_eth
  		if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
  			val |= MTK_MUTLI_CNT | MTK_RESV_BUF |
  			       MTK_WCOMP_EN | MTK_DMAD_WR_WDONE |
@@ -433,7 +433,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  		else
  			val |= MTK_RX_BT_32DWORDS;
  		mtk_w32(eth, val, reg_map->qdma.glo_cfg);
-@@ -3009,6 +3125,45 @@ static void mtk_gdm_config(struct mtk_et
+@@ -3008,6 +3124,45 @@ static void mtk_gdm_config(struct mtk_et
  	mtk_w32(eth, 0, MTK_RST_GL);
  }
  
@@ -479,7 +479,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  static int mtk_open(struct net_device *dev)
  {
  	struct mtk_mac *mac = netdev_priv(dev);
-@@ -3051,7 +3206,8 @@ static int mtk_open(struct net_device *d
+@@ -3050,7 +3205,8 @@ static int mtk_open(struct net_device *d
  		refcount_inc(&eth->dma_refcnt);
  
  	phylink_start(mac->phylink);
@@ -489,7 +489,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	return 0;
  }
  
-@@ -3760,8 +3916,12 @@ static int mtk_unreg_dev(struct mtk_eth
+@@ -3759,8 +3915,12 @@ static int mtk_unreg_dev(struct mtk_eth
  	int i;
  
  	for (i = 0; i < MTK_MAC_COUNT; i++) {
@@ -502,7 +502,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  		unregister_netdev(eth->netdev[i]);
  	}
  
-@@ -3978,6 +4138,23 @@ static int mtk_set_rxnfc(struct net_devi
+@@ -3977,6 +4137,23 @@ static int mtk_set_rxnfc(struct net_devi
  	return ret;
  }
  
@@ -526,7 +526,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  static const struct ethtool_ops mtk_ethtool_ops = {
  	.get_link_ksettings	= mtk_get_link_ksettings,
  	.set_link_ksettings	= mtk_set_link_ksettings,
-@@ -4012,6 +4189,7 @@ static const struct net_device_ops mtk_n
+@@ -4011,6 +4188,7 @@ static const struct net_device_ops mtk_n
  	.ndo_setup_tc		= mtk_eth_setup_tc,
  	.ndo_bpf		= mtk_xdp,
  	.ndo_xdp_xmit		= mtk_xdp_xmit,
@@ -534,7 +534,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  };
  
  static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
-@@ -4021,6 +4199,7 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4020,6 +4198,7 @@ static int mtk_add_mac(struct mtk_eth *e
  	struct phylink *phylink;
  	struct mtk_mac *mac;
  	int id, err;
@@ -542,7 +542,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  	if (!_id) {
  		dev_err(eth->dev, "missing mac id\n");
-@@ -4038,7 +4217,10 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4037,7 +4216,10 @@ static int mtk_add_mac(struct mtk_eth *e
  		return -EINVAL;
  	}
  
@@ -554,7 +554,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	if (!eth->netdev[id]) {
  		dev_err(eth->dev, "alloc_etherdev failed\n");
  		return -ENOMEM;
-@@ -4146,6 +4328,11 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4145,6 +4327,11 @@ static int mtk_add_mac(struct mtk_eth *e
  	else
  		eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN;
  
diff --git a/target/linux/generic/backport-6.1/730-09-v6.3-net-ethernet-mtk_eth_soc-fix-VLAN-rx-hardware-accele.patch b/target/linux/generic/backport-6.1/730-09-v6.3-net-ethernet-mtk_eth_soc-fix-VLAN-rx-hardware-accele.patch
index b45a33c4cb5388..b8e3452f300b0d 100644
--- a/target/linux/generic/backport-6.1/730-09-v6.3-net-ethernet-mtk_eth_soc-fix-VLAN-rx-hardware-accele.patch
+++ b/target/linux/generic/backport-6.1/730-09-v6.3-net-ethernet-mtk_eth_soc-fix-VLAN-rx-hardware-accele.patch
@@ -22,7 +22,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  #include "mtk_eth_soc.h"
  #include "mtk_wed.h"
-@@ -2022,16 +2023,22 @@ static int mtk_poll_rx(struct napi_struc
+@@ -2021,16 +2022,22 @@ static int mtk_poll_rx(struct napi_struc
  						htons(RX_DMA_VPID(trxd.rxd4)),
  						RX_DMA_VID(trxd.rxd4));
  			} else if (trxd.rxd2 & RX_DMA_VTAG) {
@@ -52,7 +52,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  		}
  
  		skb_record_rx_queue(skb, 0);
-@@ -2859,15 +2866,30 @@ static netdev_features_t mtk_fix_feature
+@@ -2858,15 +2865,30 @@ static netdev_features_t mtk_fix_feature
  
  static int mtk_set_features(struct net_device *dev, netdev_features_t features)
  {
@@ -88,7 +88,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  }
  
  /* wait for DMA to finish whatever it is doing before we start using it again */
-@@ -3164,11 +3186,45 @@ found:
+@@ -3163,11 +3185,45 @@ found:
  	return NOTIFY_DONE;
  }
  
@@ -135,7 +135,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  	err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0);
  	if (err) {
-@@ -3689,6 +3745,10 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -3688,6 +3744,10 @@ static int mtk_hw_init(struct mtk_eth *e
  	 */
  	val = mtk_r32(eth, MTK_CDMQ_IG_CTRL);
  	mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL);
@@ -146,7 +146,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  	/* Enable RX VLan Offloading */
  	mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
-@@ -3908,6 +3968,12 @@ static int mtk_free_dev(struct mtk_eth *
+@@ -3907,6 +3967,12 @@ static int mtk_free_dev(struct mtk_eth *
  		free_netdev(eth->netdev[i]);
  	}
  
diff --git a/target/linux/generic/backport-6.1/730-12-v6.3-net-ethernet-mtk_eth_soc-disable-hardware-DSA-untagg.patch b/target/linux/generic/backport-6.1/730-12-v6.3-net-ethernet-mtk_eth_soc-disable-hardware-DSA-untagg.patch
index 42c745d02fa9a0..a88df2b8e3a227 100644
--- a/target/linux/generic/backport-6.1/730-12-v6.3-net-ethernet-mtk_eth_soc-disable-hardware-DSA-untagg.patch
+++ b/target/linux/generic/backport-6.1/730-12-v6.3-net-ethernet-mtk_eth_soc-disable-hardware-DSA-untagg.patch
@@ -20,7 +20,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -3202,7 +3202,8 @@ static int mtk_open(struct net_device *d
+@@ -3201,7 +3201,8 @@ static int mtk_open(struct net_device *d
  	struct mtk_eth *eth = mac->hw;
  	int i, err;
  
@@ -30,7 +30,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) {
  			struct metadata_dst *md_dst = eth->dsa_meta[i];
  
-@@ -3219,7 +3220,8 @@ static int mtk_open(struct net_device *d
+@@ -3218,7 +3219,8 @@ static int mtk_open(struct net_device *d
  		}
  	} else {
  		/* Hardware special tag parsing needs to be disabled if at least
diff --git a/target/linux/generic/backport-6.1/730-13-v6.3-net-ethernet-mtk_eth_soc-enable-special-tag-when-any.patch b/target/linux/generic/backport-6.1/730-13-v6.3-net-ethernet-mtk_eth_soc-enable-special-tag-when-any.patch
index 39874c9d1c0959..8da728b9e9d479 100644
--- a/target/linux/generic/backport-6.1/730-13-v6.3-net-ethernet-mtk_eth_soc-enable-special-tag-when-any.patch
+++ b/target/linux/generic/backport-6.1/730-13-v6.3-net-ethernet-mtk_eth_soc-enable-special-tag-when-any.patch
@@ -23,7 +23,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -3137,7 +3137,7 @@ static void mtk_gdm_config(struct mtk_et
+@@ -3136,7 +3136,7 @@ static void mtk_gdm_config(struct mtk_et
  
  		val |= config;
  
@@ -32,7 +32,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  			val |= MTK_GDMA_SPECIAL_TAG;
  
  		mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
-@@ -3202,8 +3202,7 @@ static int mtk_open(struct net_device *d
+@@ -3201,8 +3201,7 @@ static int mtk_open(struct net_device *d
  	struct mtk_eth *eth = mac->hw;
  	int i, err;
  
@@ -42,7 +42,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  		for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) {
  			struct metadata_dst *md_dst = eth->dsa_meta[i];
  
-@@ -3220,8 +3219,7 @@ static int mtk_open(struct net_device *d
+@@ -3219,8 +3218,7 @@ static int mtk_open(struct net_device *d
  		}
  	} else {
  		/* Hardware special tag parsing needs to be disabled if at least
diff --git a/target/linux/generic/backport-6.1/730-14-v6.3-net-ethernet-mtk_eth_soc-fix-DSA-TX-tag-hwaccel-for-.patch b/target/linux/generic/backport-6.1/730-14-v6.3-net-ethernet-mtk_eth_soc-fix-DSA-TX-tag-hwaccel-for-.patch
index a9879ebfa9d21b..51cd572ab245af 100644
--- a/target/linux/generic/backport-6.1/730-14-v6.3-net-ethernet-mtk_eth_soc-fix-DSA-TX-tag-hwaccel-for-.patch
+++ b/target/linux/generic/backport-6.1/730-14-v6.3-net-ethernet-mtk_eth_soc-fix-DSA-TX-tag-hwaccel-for-.patch
@@ -77,7 +77,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1878,7 +1878,9 @@ static int mtk_poll_rx(struct napi_struc
+@@ -1877,7 +1877,9 @@ static int mtk_poll_rx(struct napi_struc
  
  	while (done < budget) {
  		unsigned int pktlen, *rxdcsum;
@@ -87,7 +87,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  		dma_addr_t dma_addr;
  		u32 hash, reason;
  		int mac = 0;
-@@ -2018,27 +2020,29 @@ static int mtk_poll_rx(struct napi_struc
+@@ -2017,27 +2019,29 @@ static int mtk_poll_rx(struct napi_struc
  
  		if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
  			if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
diff --git a/target/linux/generic/backport-6.1/733-v6.3-18-net-ethernet-mtk_eth_soc-add-support-for-MT7981.patch b/target/linux/generic/backport-6.1/733-v6.3-18-net-ethernet-mtk_eth_soc-add-support-for-MT7981.patch
index 089f25545d60f4..a1247218b0928b 100644
--- a/target/linux/generic/backport-6.1/733-v6.3-18-net-ethernet-mtk_eth_soc-add-support-for-MT7981.patch
+++ b/target/linux/generic/backport-6.1/733-v6.3-18-net-ethernet-mtk_eth_soc-add-support-for-MT7981.patch
@@ -57,7 +57,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		mtk_eth_path_name(path), __func__, updated);
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -4804,6 +4804,26 @@ static const struct mtk_soc_data mt7629_
+@@ -4803,6 +4803,26 @@ static const struct mtk_soc_data mt7629_
  	},
  };
  
@@ -84,7 +84,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  static const struct mtk_soc_data mt7986_data = {
  	.reg_map = &mt7986_reg_map,
  	.ana_rgc3 = 0x128,
-@@ -4846,6 +4866,7 @@ const struct of_device_id of_mtk_match[]
+@@ -4845,6 +4865,7 @@ const struct of_device_id of_mtk_match[]
  	{ .compatible = "mediatek,mt7622-eth", .data = &mt7622_data},
  	{ .compatible = "mediatek,mt7623-eth", .data = &mt7623_data},
  	{ .compatible = "mediatek,mt7629-eth", .data = &mt7629_data},
diff --git a/target/linux/generic/backport-6.1/733-v6.3-19-net-ethernet-mtk_eth_soc-set-MDIO-bus-clock-frequenc.patch b/target/linux/generic/backport-6.1/733-v6.3-19-net-ethernet-mtk_eth_soc-set-MDIO-bus-clock-frequenc.patch
index ea20bd87f73417..1cb1f405385c3c 100644
--- a/target/linux/generic/backport-6.1/733-v6.3-19-net-ethernet-mtk_eth_soc-set-MDIO-bus-clock-frequenc.patch
+++ b/target/linux/generic/backport-6.1/733-v6.3-19-net-ethernet-mtk_eth_soc-set-MDIO-bus-clock-frequenc.patch
@@ -21,7 +21,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -745,8 +745,10 @@ static const struct phylink_mac_ops mtk_
+@@ -744,8 +744,10 @@ static const struct phylink_mac_ops mtk_
  
  static int mtk_mdio_init(struct mtk_eth *eth)
  {
@@ -32,7 +32,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus");
  	if (!mii_np) {
-@@ -773,6 +775,25 @@ static int mtk_mdio_init(struct mtk_eth
+@@ -772,6 +774,25 @@ static int mtk_mdio_init(struct mtk_eth
  	eth->mii_bus->parent = eth->dev;
  
  	snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np);
diff --git a/target/linux/generic/backport-6.1/733-v6.3-20-net-ethernet-mtk_eth_soc-switch-to-external-PCS-driv.patch b/target/linux/generic/backport-6.1/733-v6.3-20-net-ethernet-mtk_eth_soc-switch-to-external-PCS-driv.patch
index 15295959c11ad9..110944658dee80 100644
--- a/target/linux/generic/backport-6.1/733-v6.3-20-net-ethernet-mtk_eth_soc-switch-to-external-PCS-driv.patch
+++ b/target/linux/generic/backport-6.1/733-v6.3-20-net-ethernet-mtk_eth_soc-switch-to-external-PCS-driv.patch
@@ -60,7 +60,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	}
  
  	return NULL;
-@@ -4017,8 +4018,17 @@ static int mtk_unreg_dev(struct mtk_eth
+@@ -4016,8 +4017,17 @@ static int mtk_unreg_dev(struct mtk_eth
  	return 0;
  }
  
@@ -78,7 +78,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	mtk_unreg_dev(eth);
  	mtk_free_dev(eth);
  	cancel_work_sync(&eth->pending_work);
-@@ -4458,6 +4468,36 @@ void mtk_eth_set_dma_device(struct mtk_e
+@@ -4457,6 +4467,36 @@ void mtk_eth_set_dma_device(struct mtk_e
  	rtnl_unlock();
  }
  
@@ -115,7 +115,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  static int mtk_probe(struct platform_device *pdev)
  {
  	struct resource *res = NULL;
-@@ -4521,13 +4561,7 @@ static int mtk_probe(struct platform_dev
+@@ -4520,13 +4560,7 @@ static int mtk_probe(struct platform_dev
  	}
  
  	if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
@@ -130,7 +130,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  		if (err)
  			return err;
-@@ -4538,14 +4572,17 @@ static int mtk_probe(struct platform_dev
+@@ -4537,14 +4571,17 @@ static int mtk_probe(struct platform_dev
  							    "mediatek,pctl");
  		if (IS_ERR(eth->pctl)) {
  			dev_err(&pdev->dev, "no pctl regmap found\n");
@@ -151,7 +151,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	}
  
  	if (eth->soc->offload_version) {
-@@ -4704,6 +4741,8 @@ err_deinit_hw:
+@@ -4703,6 +4740,8 @@ err_deinit_hw:
  	mtk_hw_deinit(eth);
  err_wed_exit:
  	mtk_wed_exit();
diff --git a/target/linux/generic/backport-6.1/733-v6.4-23-net-ethernet-mtk_eth_soc-ppe-add-support-for-flow-ac.patch b/target/linux/generic/backport-6.1/733-v6.4-23-net-ethernet-mtk_eth_soc-ppe-add-support-for-flow-ac.patch
index df8d6427943c9d..93eaffa19e7745 100644
--- a/target/linux/generic/backport-6.1/733-v6.4-23-net-ethernet-mtk_eth_soc-ppe-add-support-for-flow-ac.patch
+++ b/target/linux/generic/backport-6.1/733-v6.4-23-net-ethernet-mtk_eth_soc-ppe-add-support-for-flow-ac.patch
@@ -27,7 +27,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -4692,8 +4692,8 @@ static int mtk_probe(struct platform_dev
+@@ -4691,8 +4691,8 @@ static int mtk_probe(struct platform_dev
  		for (i = 0; i < num_ppe; i++) {
  			u32 ppe_addr = eth->soc->reg_map->ppe_base + i * 0x400;
  
@@ -38,7 +38,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  			if (!eth->ppe[i]) {
  				err = -ENOMEM;
  				goto err_deinit_ppe;
-@@ -4817,6 +4817,7 @@ static const struct mtk_soc_data mt7622_
+@@ -4816,6 +4816,7 @@ static const struct mtk_soc_data mt7622_
  	.required_pctl = false,
  	.offload_version = 2,
  	.hash_offset = 2,
@@ -46,7 +46,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	.foe_entry_size = sizeof(struct mtk_foe_entry) - 16,
  	.txrx = {
  		.txd_size = sizeof(struct mtk_tx_dma),
-@@ -4854,6 +4855,7 @@ static const struct mtk_soc_data mt7629_
+@@ -4853,6 +4854,7 @@ static const struct mtk_soc_data mt7629_
  	.hw_features = MTK_HW_FEATURES,
  	.required_clks = MT7629_CLKS_BITMAP,
  	.required_pctl = false,
@@ -54,7 +54,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	.txrx = {
  		.txd_size = sizeof(struct mtk_tx_dma),
  		.rxd_size = sizeof(struct mtk_rx_dma),
-@@ -4874,6 +4876,7 @@ static const struct mtk_soc_data mt7981_
+@@ -4873,6 +4875,7 @@ static const struct mtk_soc_data mt7981_
  	.offload_version = 2,
  	.hash_offset = 4,
  	.foe_entry_size = sizeof(struct mtk_foe_entry),
@@ -62,7 +62,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	.txrx = {
  		.txd_size = sizeof(struct mtk_tx_dma_v2),
  		.rxd_size = sizeof(struct mtk_rx_dma_v2),
-@@ -4894,6 +4897,7 @@ static const struct mtk_soc_data mt7986_
+@@ -4893,6 +4896,7 @@ static const struct mtk_soc_data mt7986_
  	.offload_version = 2,
  	.hash_offset = 4,
  	.foe_entry_size = sizeof(struct mtk_foe_entry),
diff --git a/target/linux/generic/backport-6.1/733-v6.4-25-net-ethernet-mtk_eth_soc-drop-generic-vlan-rx-offloa.patch b/target/linux/generic/backport-6.1/733-v6.4-25-net-ethernet-mtk_eth_soc-drop-generic-vlan-rx-offloa.patch
index d6309964c384bd..217e517c3af4c6 100644
--- a/target/linux/generic/backport-6.1/733-v6.4-25-net-ethernet-mtk_eth_soc-drop-generic-vlan-rx-offloa.patch
+++ b/target/linux/generic/backport-6.1/733-v6.4-25-net-ethernet-mtk_eth_soc-drop-generic-vlan-rx-offloa.patch
@@ -17,7 +17,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1898,9 +1898,7 @@ static int mtk_poll_rx(struct napi_struc
+@@ -1897,9 +1897,7 @@ static int mtk_poll_rx(struct napi_struc
  
  	while (done < budget) {
  		unsigned int pktlen, *rxdcsum;
@@ -27,7 +27,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  		dma_addr_t dma_addr;
  		u32 hash, reason;
  		int mac = 0;
-@@ -2035,36 +2033,21 @@ static int mtk_poll_rx(struct napi_struc
+@@ -2034,36 +2032,21 @@ static int mtk_poll_rx(struct napi_struc
  			skb_checksum_none_assert(skb);
  		skb->protocol = eth_type_trans(skb, netdev);
  
@@ -70,7 +70,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  		skb_record_rx_queue(skb, 0);
  		napi_gro_receive(napi, skb);
  
-@@ -2890,29 +2873,11 @@ static netdev_features_t mtk_fix_feature
+@@ -2889,29 +2872,11 @@ static netdev_features_t mtk_fix_feature
  
  static int mtk_set_features(struct net_device *dev, netdev_features_t features)
  {
@@ -100,7 +100,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	return 0;
  }
  
-@@ -3226,30 +3191,6 @@ static int mtk_open(struct net_device *d
+@@ -3225,30 +3190,6 @@ static int mtk_open(struct net_device *d
  	struct mtk_eth *eth = mac->hw;
  	int i, err;
  
@@ -131,7 +131,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0);
  	if (err) {
  		netdev_err(dev, "%s: could not attach PHY: %d\n", __func__,
-@@ -3288,6 +3229,35 @@ static int mtk_open(struct net_device *d
+@@ -3287,6 +3228,35 @@ static int mtk_open(struct net_device *d
  	phylink_start(mac->phylink);
  	netif_tx_start_all_queues(dev);
  
@@ -167,7 +167,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	return 0;
  }
  
-@@ -3772,10 +3742,9 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -3771,10 +3741,9 @@ static int mtk_hw_init(struct mtk_eth *e
  	if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
  		val = mtk_r32(eth, MTK_CDMP_IG_CTRL);
  		mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL);
@@ -180,7 +180,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  	/* set interrupt delays based on current Net DIM sample */
  	mtk_dim_rx(&eth->rx_dim.work);
-@@ -4415,7 +4384,7 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4414,7 +4383,7 @@ static int mtk_add_mac(struct mtk_eth *e
  		eth->netdev[id]->hw_features |= NETIF_F_LRO;
  
  	eth->netdev[id]->vlan_features = eth->soc->hw_features &
diff --git a/target/linux/generic/backport-6.1/750-v6.5-01-net-ethernet-mtk_ppe-add-MTK_FOE_ENTRY_V-1-2-_SIZE-m.patch b/target/linux/generic/backport-6.1/750-v6.5-01-net-ethernet-mtk_ppe-add-MTK_FOE_ENTRY_V-1-2-_SIZE-m.patch
index a0b9b6a299bc21..d7d1c08fce0dc8 100644
--- a/target/linux/generic/backport-6.1/750-v6.5-01-net-ethernet-mtk_ppe-add-MTK_FOE_ENTRY_V-1-2-_SIZE-m.patch
+++ b/target/linux/generic/backport-6.1/750-v6.5-01-net-ethernet-mtk_ppe-add-MTK_FOE_ENTRY_V-1-2-_SIZE-m.patch
@@ -17,7 +17,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -4766,7 +4766,7 @@ static const struct mtk_soc_data mt7621_
+@@ -4765,7 +4765,7 @@ static const struct mtk_soc_data mt7621_
  	.required_pctl = false,
  	.offload_version = 1,
  	.hash_offset = 2,
@@ -26,7 +26,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	.txrx = {
  		.txd_size = sizeof(struct mtk_tx_dma),
  		.rxd_size = sizeof(struct mtk_rx_dma),
-@@ -4787,7 +4787,7 @@ static const struct mtk_soc_data mt7622_
+@@ -4786,7 +4786,7 @@ static const struct mtk_soc_data mt7622_
  	.offload_version = 2,
  	.hash_offset = 2,
  	.has_accounting = true,
@@ -35,7 +35,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	.txrx = {
  		.txd_size = sizeof(struct mtk_tx_dma),
  		.rxd_size = sizeof(struct mtk_rx_dma),
-@@ -4806,7 +4806,7 @@ static const struct mtk_soc_data mt7623_
+@@ -4805,7 +4805,7 @@ static const struct mtk_soc_data mt7623_
  	.required_pctl = true,
  	.offload_version = 1,
  	.hash_offset = 2,
@@ -44,7 +44,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	.txrx = {
  		.txd_size = sizeof(struct mtk_tx_dma),
  		.rxd_size = sizeof(struct mtk_rx_dma),
-@@ -4844,8 +4844,8 @@ static const struct mtk_soc_data mt7981_
+@@ -4843,8 +4843,8 @@ static const struct mtk_soc_data mt7981_
  	.required_pctl = false,
  	.offload_version = 2,
  	.hash_offset = 4,
@@ -54,7 +54,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	.txrx = {
  		.txd_size = sizeof(struct mtk_tx_dma_v2),
  		.rxd_size = sizeof(struct mtk_rx_dma_v2),
-@@ -4865,8 +4865,8 @@ static const struct mtk_soc_data mt7986_
+@@ -4864,8 +4864,8 @@ static const struct mtk_soc_data mt7986_
  	.required_pctl = false,
  	.offload_version = 2,
  	.hash_offset = 4,
diff --git a/target/linux/generic/backport-6.1/750-v6.5-02-net-ethernet-mtk_eth_soc-remove-incorrect-PLL-config.patch b/target/linux/generic/backport-6.1/750-v6.5-02-net-ethernet-mtk_eth_soc-remove-incorrect-PLL-config.patch
index 8914e8da96d87c..fb54f404b21a9a 100644
--- a/target/linux/generic/backport-6.1/750-v6.5-02-net-ethernet-mtk_eth_soc-remove-incorrect-PLL-config.patch
+++ b/target/linux/generic/backport-6.1/750-v6.5-02-net-ethernet-mtk_eth_soc-remove-incorrect-PLL-config.patch
@@ -95,7 +95,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  				/* mt7623_pad_clk_setup */
  				for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
-@@ -4343,13 +4315,19 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4342,13 +4314,19 @@ static int mtk_add_mac(struct mtk_eth *e
  	mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
  		MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD;
  
@@ -121,7 +121,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  	if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) && !mac->id)
  		__set_bit(PHY_INTERFACE_MODE_TRGMII,
-@@ -4807,6 +4785,7 @@ static const struct mtk_soc_data mt7623_
+@@ -4806,6 +4784,7 @@ static const struct mtk_soc_data mt7623_
  	.offload_version = 1,
  	.hash_offset = 2,
  	.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
diff --git a/target/linux/generic/backport-6.1/750-v6.5-03-net-ethernet-mtk_eth_soc-remove-mac_pcs_get_state-an.patch b/target/linux/generic/backport-6.1/750-v6.5-03-net-ethernet-mtk_eth_soc-remove-mac_pcs_get_state-an.patch
index 351568f187ca9c..293066fa9a05ee 100644
--- a/target/linux/generic/backport-6.1/750-v6.5-03-net-ethernet-mtk_eth_soc-remove-mac_pcs_get_state-an.patch
+++ b/target/linux/generic/backport-6.1/750-v6.5-03-net-ethernet-mtk_eth_soc-remove-mac_pcs_get_state-an.patch
@@ -62,15 +62,15 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode,
  			      phy_interface_t interface)
  {
-@@ -709,7 +677,6 @@ static void mtk_mac_link_up(struct phyli
+@@ -708,7 +676,6 @@ static void mtk_mac_link_up(struct phyli
+ 
  static const struct phylink_mac_ops mtk_phylink_ops = {
- 	.validate = phylink_generic_validate,
  	.mac_select_pcs = mtk_mac_select_pcs,
 -	.mac_pcs_get_state = mtk_mac_pcs_get_state,
  	.mac_config = mtk_mac_config,
  	.mac_finish = mtk_mac_finish,
  	.mac_link_down = mtk_mac_link_down,
-@@ -4310,8 +4277,6 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4309,8 +4276,6 @@ static int mtk_add_mac(struct mtk_eth *e
  
  	mac->phylink_config.dev = &eth->netdev[id]->dev;
  	mac->phylink_config.type = PHYLINK_NETDEV;
diff --git a/target/linux/generic/backport-6.1/750-v6.5-05-net-ethernet-mtk_eth_soc-add-version-in-mtk_soc_data.patch b/target/linux/generic/backport-6.1/750-v6.5-05-net-ethernet-mtk_eth_soc-add-version-in-mtk_soc_data.patch
index f4795223394283..25c87b0415e0ab 100644
--- a/target/linux/generic/backport-6.1/750-v6.5-05-net-ethernet-mtk_eth_soc-add-version-in-mtk_soc_data.patch
+++ b/target/linux/generic/backport-6.1/750-v6.5-05-net-ethernet-mtk_eth_soc-add-version-in-mtk_soc_data.patch
@@ -32,7 +32,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		val |= MTK_QTX_SCH_LEAKY_BUCKET_EN;
  
  	if (IS_ENABLED(CONFIG_SOC_MT7621)) {
-@@ -956,7 +956,7 @@ static bool mtk_rx_get_desc(struct mtk_e
+@@ -955,7 +955,7 @@ static bool mtk_rx_get_desc(struct mtk_e
  	rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
  	rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
  	rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
@@ -41,7 +41,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		rxd->rxd5 = READ_ONCE(dma_rxd->rxd5);
  		rxd->rxd6 = READ_ONCE(dma_rxd->rxd6);
  	}
-@@ -1014,7 +1014,7 @@ static int mtk_init_fq_dma(struct mtk_et
+@@ -1013,7 +1013,7 @@ static int mtk_init_fq_dma(struct mtk_et
  
  		txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE);
  		txd->txd4 = 0;
@@ -50,7 +50,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  			txd->txd5 = 0;
  			txd->txd6 = 0;
  			txd->txd7 = 0;
-@@ -1205,7 +1205,7 @@ static void mtk_tx_set_dma_desc(struct n
+@@ -1204,7 +1204,7 @@ static void mtk_tx_set_dma_desc(struct n
  	struct mtk_mac *mac = netdev_priv(dev);
  	struct mtk_eth *eth = mac->hw;
  
@@ -59,7 +59,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		mtk_tx_set_dma_desc_v2(dev, txd, info);
  	else
  		mtk_tx_set_dma_desc_v1(dev, txd, info);
-@@ -1512,7 +1512,7 @@ static void mtk_update_rx_cpu_idx(struct
+@@ -1511,7 +1511,7 @@ static void mtk_update_rx_cpu_idx(struct
  
  static bool mtk_page_pool_enabled(struct mtk_eth *eth)
  {
@@ -68,7 +68,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  }
  
  static struct page_pool *mtk_create_page_pool(struct mtk_eth *eth,
-@@ -1854,7 +1854,7 @@ static int mtk_poll_rx(struct napi_struc
+@@ -1853,7 +1853,7 @@ static int mtk_poll_rx(struct napi_struc
  			break;
  
  		/* find out which mac the packet come from. values start at 1 */
@@ -77,7 +77,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  			mac = RX_DMA_GET_SPORT_V2(trxd.rxd5) - 1;
  		else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) &&
  			 !(trxd.rxd4 & RX_DMA_SPECIAL_TAG))
-@@ -1950,7 +1950,7 @@ static int mtk_poll_rx(struct napi_struc
+@@ -1949,7 +1949,7 @@ static int mtk_poll_rx(struct napi_struc
  		skb->dev = netdev;
  		bytes += skb->len;
  
@@ -86,7 +86,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  			reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5);
  			hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY;
  			if (hash != MTK_RXD5_FOE_ENTRY)
-@@ -1975,8 +1975,8 @@ static int mtk_poll_rx(struct napi_struc
+@@ -1974,8 +1974,8 @@ static int mtk_poll_rx(struct napi_struc
  		/* When using VLAN untagging in combination with DSA, the
  		 * hardware treats the MTK special tag as a VLAN and untags it.
  		 */
@@ -97,7 +97,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  			unsigned int port = RX_DMA_VPID(trxd.rxd3) & GENMASK(2, 0);
  
  			if (port < ARRAY_SIZE(eth->dsa_meta) &&
-@@ -2286,7 +2286,7 @@ static int mtk_tx_alloc(struct mtk_eth *
+@@ -2285,7 +2285,7 @@ static int mtk_tx_alloc(struct mtk_eth *
  		txd->txd2 = next_ptr;
  		txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
  		txd->txd4 = 0;
@@ -106,7 +106,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  			txd->txd5 = 0;
  			txd->txd6 = 0;
  			txd->txd7 = 0;
-@@ -2339,14 +2339,14 @@ static int mtk_tx_alloc(struct mtk_eth *
+@@ -2338,14 +2338,14 @@ static int mtk_tx_alloc(struct mtk_eth *
  			      FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) |
  			      FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) |
  			      MTK_QTX_SCH_LEAKY_BUCKET_SIZE;
@@ -123,7 +123,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  			mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate + 4);
  	} else {
  		mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0);
-@@ -2475,7 +2475,7 @@ static int mtk_rx_alloc(struct mtk_eth *
+@@ -2474,7 +2474,7 @@ static int mtk_rx_alloc(struct mtk_eth *
  
  		rxd->rxd3 = 0;
  		rxd->rxd4 = 0;
@@ -132,7 +132,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  			rxd->rxd5 = 0;
  			rxd->rxd6 = 0;
  			rxd->rxd7 = 0;
-@@ -3026,7 +3026,7 @@ static int mtk_start_dma(struct mtk_eth
+@@ -3025,7 +3025,7 @@ static int mtk_start_dma(struct mtk_eth
  		       MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO |
  		       MTK_RX_2B_OFFSET | MTK_TX_WB_DDONE;
  
@@ -141,7 +141,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  			val |= MTK_MUTLI_CNT | MTK_RESV_BUF |
  			       MTK_WCOMP_EN | MTK_DMAD_WR_WDONE |
  			       MTK_CHK_DDONE_EN | MTK_LEAKY_BUCKET_EN;
-@@ -3168,7 +3168,7 @@ static int mtk_open(struct net_device *d
+@@ -3167,7 +3167,7 @@ static int mtk_open(struct net_device *d
  	phylink_start(mac->phylink);
  	netif_tx_start_all_queues(dev);
  
@@ -150,7 +150,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		return 0;
  
  	if (mtk_uses_dsa(dev) && !eth->prog) {
-@@ -3433,7 +3433,7 @@ static void mtk_hw_reset(struct mtk_eth
+@@ -3432,7 +3432,7 @@ static void mtk_hw_reset(struct mtk_eth
  {
  	u32 val;
  
@@ -159,7 +159,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0);
  		val = RSTCTRL_PPE0_V2;
  	} else {
-@@ -3445,7 +3445,7 @@ static void mtk_hw_reset(struct mtk_eth
+@@ -3444,7 +3444,7 @@ static void mtk_hw_reset(struct mtk_eth
  
  	ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val);
  
@@ -168,7 +168,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN,
  			     0x3ffffff);
  }
-@@ -3471,7 +3471,7 @@ static void mtk_hw_warm_reset(struct mtk
+@@ -3470,7 +3470,7 @@ static void mtk_hw_warm_reset(struct mtk
  		return;
  	}
  
@@ -177,7 +177,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V2;
  	else
  		rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0;
-@@ -3641,7 +3641,7 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -3640,7 +3640,7 @@ static int mtk_hw_init(struct mtk_eth *e
  	else
  		mtk_hw_reset(eth);
  
@@ -186,7 +186,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		/* Set FE to PDMAv2 if necessary */
  		val = mtk_r32(eth, MTK_FE_GLO_MISC);
  		mtk_w32(eth,  val | BIT(4), MTK_FE_GLO_MISC);
-@@ -3678,7 +3678,7 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -3677,7 +3677,7 @@ static int mtk_hw_init(struct mtk_eth *e
  	 */
  	val = mtk_r32(eth, MTK_CDMQ_IG_CTRL);
  	mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL);
@@ -195,7 +195,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		val = mtk_r32(eth, MTK_CDMP_IG_CTRL);
  		mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL);
  
-@@ -3700,7 +3700,7 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -3699,7 +3699,7 @@ static int mtk_hw_init(struct mtk_eth *e
  	mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4);
  	mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
  
@@ -204,7 +204,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		/* PSE should not drop port8 and port9 packets from WDMA Tx */
  		mtk_w32(eth, 0x00000300, PSE_DROP_CFG);
  
-@@ -4489,7 +4489,7 @@ static int mtk_probe(struct platform_dev
+@@ -4488,7 +4488,7 @@ static int mtk_probe(struct platform_dev
  		}
  	}
  
@@ -213,7 +213,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  		if (!res) {
  			err = -EINVAL;
-@@ -4597,9 +4597,8 @@ static int mtk_probe(struct platform_dev
+@@ -4596,9 +4596,8 @@ static int mtk_probe(struct platform_dev
  	}
  
  	if (eth->soc->offload_version) {
@@ -224,7 +224,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		num_ppe = min_t(u32, ARRAY_SIZE(eth->ppe), num_ppe);
  		for (i = 0; i < num_ppe; i++) {
  			u32 ppe_addr = eth->soc->reg_map->ppe_base + i * 0x400;
-@@ -4691,6 +4690,7 @@ static const struct mtk_soc_data mt2701_
+@@ -4690,6 +4689,7 @@ static const struct mtk_soc_data mt2701_
  	.hw_features = MTK_HW_FEATURES,
  	.required_clks = MT7623_CLKS_BITMAP,
  	.required_pctl = true,
@@ -232,7 +232,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	.txrx = {
  		.txd_size = sizeof(struct mtk_tx_dma),
  		.rxd_size = sizeof(struct mtk_rx_dma),
-@@ -4707,6 +4707,7 @@ static const struct mtk_soc_data mt7621_
+@@ -4706,6 +4706,7 @@ static const struct mtk_soc_data mt7621_
  	.hw_features = MTK_HW_FEATURES,
  	.required_clks = MT7621_CLKS_BITMAP,
  	.required_pctl = false,
@@ -240,7 +240,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	.offload_version = 1,
  	.hash_offset = 2,
  	.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
-@@ -4727,6 +4728,7 @@ static const struct mtk_soc_data mt7622_
+@@ -4726,6 +4727,7 @@ static const struct mtk_soc_data mt7622_
  	.hw_features = MTK_HW_FEATURES,
  	.required_clks = MT7622_CLKS_BITMAP,
  	.required_pctl = false,
@@ -248,7 +248,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	.offload_version = 2,
  	.hash_offset = 2,
  	.has_accounting = true,
-@@ -4747,6 +4749,7 @@ static const struct mtk_soc_data mt7623_
+@@ -4746,6 +4748,7 @@ static const struct mtk_soc_data mt7623_
  	.hw_features = MTK_HW_FEATURES,
  	.required_clks = MT7623_CLKS_BITMAP,
  	.required_pctl = true,
@@ -256,7 +256,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	.offload_version = 1,
  	.hash_offset = 2,
  	.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
-@@ -4769,6 +4772,7 @@ static const struct mtk_soc_data mt7629_
+@@ -4768,6 +4771,7 @@ static const struct mtk_soc_data mt7629_
  	.required_clks = MT7629_CLKS_BITMAP,
  	.required_pctl = false,
  	.has_accounting = true,
@@ -264,7 +264,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	.txrx = {
  		.txd_size = sizeof(struct mtk_tx_dma),
  		.rxd_size = sizeof(struct mtk_rx_dma),
-@@ -4786,6 +4790,7 @@ static const struct mtk_soc_data mt7981_
+@@ -4785,6 +4789,7 @@ static const struct mtk_soc_data mt7981_
  	.hw_features = MTK_HW_FEATURES,
  	.required_clks = MT7981_CLKS_BITMAP,
  	.required_pctl = false,
@@ -272,7 +272,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	.offload_version = 2,
  	.hash_offset = 4,
  	.has_accounting = true,
-@@ -4807,6 +4812,7 @@ static const struct mtk_soc_data mt7986_
+@@ -4806,6 +4811,7 @@ static const struct mtk_soc_data mt7986_
  	.hw_features = MTK_HW_FEATURES,
  	.required_clks = MT7986_CLKS_BITMAP,
  	.required_pctl = false,
@@ -280,7 +280,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	.offload_version = 2,
  	.hash_offset = 4,
  	.has_accounting = true,
-@@ -4827,6 +4833,7 @@ static const struct mtk_soc_data rt5350_
+@@ -4826,6 +4832,7 @@ static const struct mtk_soc_data rt5350_
  	.hw_features = MTK_HW_FEATURES_MT7628,
  	.required_clks = MT7628_CLKS_BITMAP,
  	.required_pctl = false,
diff --git a/target/linux/generic/backport-6.1/750-v6.5-07-net-ethernet-mtk_eth_soc-rely-on-MTK_MAX_DEVS-and-re.patch b/target/linux/generic/backport-6.1/750-v6.5-07-net-ethernet-mtk_eth_soc-rely-on-MTK_MAX_DEVS-and-re.patch
index 5ac9d61ab424a7..80716583134404 100644
--- a/target/linux/generic/backport-6.1/750-v6.5-07-net-ethernet-mtk_eth_soc-rely-on-MTK_MAX_DEVS-and-re.patch
+++ b/target/linux/generic/backport-6.1/750-v6.5-07-net-ethernet-mtk_eth_soc-rely-on-MTK_MAX_DEVS-and-re.patch
@@ -17,7 +17,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -882,7 +882,7 @@ static void mtk_stats_update(struct mtk_
+@@ -881,7 +881,7 @@ static void mtk_stats_update(struct mtk_
  {
  	int i;
  
@@ -26,7 +26,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		if (!eth->mac[i] || !eth->mac[i]->hw_stats)
  			continue;
  		if (spin_trylock(&eth->mac[i]->hw_stats->stats_lock)) {
-@@ -1387,7 +1387,7 @@ static int mtk_queue_stopped(struct mtk_
+@@ -1386,7 +1386,7 @@ static int mtk_queue_stopped(struct mtk_
  {
  	int i;
  
@@ -35,7 +35,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		if (!eth->netdev[i])
  			continue;
  		if (netif_queue_stopped(eth->netdev[i]))
-@@ -1401,7 +1401,7 @@ static void mtk_wake_queue(struct mtk_et
+@@ -1400,7 +1400,7 @@ static void mtk_wake_queue(struct mtk_et
  {
  	int i;
  
@@ -44,7 +44,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		if (!eth->netdev[i])
  			continue;
  		netif_tx_wake_all_queues(eth->netdev[i]);
-@@ -1860,7 +1860,7 @@ static int mtk_poll_rx(struct napi_struc
+@@ -1859,7 +1859,7 @@ static int mtk_poll_rx(struct napi_struc
  			 !(trxd.rxd4 & RX_DMA_SPECIAL_TAG))
  			mac = RX_DMA_GET_SPORT(trxd.rxd4) - 1;
  
@@ -53,7 +53,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  			     !eth->netdev[mac]))
  			goto release_desc;
  
-@@ -2900,7 +2900,7 @@ static void mtk_dma_free(struct mtk_eth
+@@ -2899,7 +2899,7 @@ static void mtk_dma_free(struct mtk_eth
  	const struct mtk_soc_data *soc = eth->soc;
  	int i;
  
@@ -62,7 +62,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		if (eth->netdev[i])
  			netdev_reset_queue(eth->netdev[i]);
  	if (eth->scratch_ring) {
-@@ -3054,8 +3054,13 @@ static void mtk_gdm_config(struct mtk_et
+@@ -3053,8 +3053,13 @@ static void mtk_gdm_config(struct mtk_et
  	if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
  		return;
  
@@ -78,7 +78,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  		/* default setup the forward port to send frame to PDMA */
  		val &= ~0xffff;
-@@ -3065,7 +3070,7 @@ static void mtk_gdm_config(struct mtk_et
+@@ -3064,7 +3069,7 @@ static void mtk_gdm_config(struct mtk_et
  
  		val |= config;
  
@@ -87,7 +87,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  			val |= MTK_GDMA_SPECIAL_TAG;
  
  		mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
-@@ -3662,15 +3667,15 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -3661,15 +3666,15 @@ static int mtk_hw_init(struct mtk_eth *e
  	 * up with the more appropriate value when mtk_mac_config call is being
  	 * invoked.
  	 */
@@ -109,7 +109,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	}
  
  	/* Indicates CDM to parse the MTK special tag from CPU
-@@ -3850,7 +3855,7 @@ static void mtk_pending_work(struct work
+@@ -3849,7 +3854,7 @@ static void mtk_pending_work(struct work
  	mtk_prepare_for_reset(eth);
  
  	/* stop all devices to make sure that dma is properly shut down */
@@ -118,7 +118,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		if (!eth->netdev[i] || !netif_running(eth->netdev[i]))
  			continue;
  
-@@ -3866,8 +3871,8 @@ static void mtk_pending_work(struct work
+@@ -3865,8 +3870,8 @@ static void mtk_pending_work(struct work
  	mtk_hw_init(eth, true);
  
  	/* restart DMA and enable IRQs */
@@ -129,7 +129,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  			continue;
  
  		if (mtk_open(eth->netdev[i])) {
-@@ -3894,7 +3899,7 @@ static int mtk_free_dev(struct mtk_eth *
+@@ -3893,7 +3898,7 @@ static int mtk_free_dev(struct mtk_eth *
  {
  	int i;
  
@@ -138,7 +138,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		if (!eth->netdev[i])
  			continue;
  		free_netdev(eth->netdev[i]);
-@@ -3913,7 +3918,7 @@ static int mtk_unreg_dev(struct mtk_eth
+@@ -3912,7 +3917,7 @@ static int mtk_unreg_dev(struct mtk_eth
  {
  	int i;
  
@@ -147,7 +147,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		struct mtk_mac *mac;
  		if (!eth->netdev[i])
  			continue;
-@@ -4214,7 +4219,7 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4213,7 +4218,7 @@ static int mtk_add_mac(struct mtk_eth *e
  	}
  
  	id = be32_to_cpup(_id);
@@ -156,7 +156,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		dev_err(eth->dev, "%d is not a valid mac id\n", id);
  		return -EINVAL;
  	}
-@@ -4359,7 +4364,7 @@ void mtk_eth_set_dma_device(struct mtk_e
+@@ -4358,7 +4363,7 @@ void mtk_eth_set_dma_device(struct mtk_e
  
  	rtnl_lock();
  
@@ -165,7 +165,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		dev = eth->netdev[i];
  
  		if (!dev || !(dev->flags & IFF_UP))
-@@ -4665,7 +4670,7 @@ static int mtk_remove(struct platform_de
+@@ -4664,7 +4669,7 @@ static int mtk_remove(struct platform_de
  	int i;
  
  	/* stop all devices to make sure that dma is properly shut down */
diff --git a/target/linux/generic/backport-6.1/750-v6.5-08-net-ethernet-mtk_eth_soc-add-NETSYS_V3-version-suppo.patch b/target/linux/generic/backport-6.1/750-v6.5-08-net-ethernet-mtk_eth_soc-add-NETSYS_V3-version-suppo.patch
index bf6ef4c1370676..1a9b31f526b469 100644
--- a/target/linux/generic/backport-6.1/750-v6.5-08-net-ethernet-mtk_eth_soc-add-NETSYS_V3-version-suppo.patch
+++ b/target/linux/generic/backport-6.1/750-v6.5-08-net-ethernet-mtk_eth_soc-add-NETSYS_V3-version-suppo.patch
@@ -18,7 +18,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -862,17 +862,32 @@ void mtk_stats_update_mac(struct mtk_mac
+@@ -861,17 +861,32 @@ void mtk_stats_update_mac(struct mtk_mac
  			mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x20 + offs);
  		hw_stats->rx_flow_control_packets +=
  			mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x24 + offs);
@@ -62,7 +62,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	}
  
  	u64_stats_update_end(&hw_stats->syncp);
-@@ -1176,7 +1191,10 @@ static void mtk_tx_set_dma_desc_v2(struc
+@@ -1175,7 +1190,10 @@ static void mtk_tx_set_dma_desc_v2(struc
  		data |= TX_DMA_LS0;
  	WRITE_ONCE(desc->txd3, data);
  
@@ -74,7 +74,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid);
  	WRITE_ONCE(desc->txd4, data);
  
-@@ -1187,6 +1205,8 @@ static void mtk_tx_set_dma_desc_v2(struc
+@@ -1186,6 +1204,8 @@ static void mtk_tx_set_dma_desc_v2(struc
  		/* tx checksum offload */
  		if (info->csum)
  			data |= TX_DMA_CHKSUM_V2;
@@ -83,7 +83,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	}
  	WRITE_ONCE(desc->txd5, data);
  
-@@ -1252,8 +1272,7 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -1251,8 +1271,7 @@ static int mtk_tx_map(struct sk_buff *sk
  	mtk_tx_set_dma_desc(dev, itxd, &txd_info);
  
  	itx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
@@ -93,7 +93,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	setup_tx_buf(eth, itx_buf, itxd_pdma, txd_info.addr, txd_info.size,
  		     k++);
  
-@@ -1301,8 +1320,7 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -1300,8 +1319,7 @@ static int mtk_tx_map(struct sk_buff *sk
  				memset(tx_buf, 0, sizeof(*tx_buf));
  			tx_buf->data = (void *)MTK_DMA_DUMMY_DESC;
  			tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
@@ -103,7 +103,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  			setup_tx_buf(eth, tx_buf, txd_pdma, txd_info.addr,
  				     txd_info.size, k++);
-@@ -1604,7 +1622,7 @@ static int mtk_xdp_frame_map(struct mtk_
+@@ -1603,7 +1621,7 @@ static int mtk_xdp_frame_map(struct mtk_
  	}
  	mtk_tx_set_dma_desc(dev, txd, txd_info);
  
@@ -112,7 +112,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	tx_buf->type = dma_map ? MTK_TYPE_XDP_NDO : MTK_TYPE_XDP_TX;
  	tx_buf->data = (void *)MTK_DMA_DUMMY_DESC;
  
-@@ -1854,11 +1872,24 @@ static int mtk_poll_rx(struct napi_struc
+@@ -1853,11 +1871,24 @@ static int mtk_poll_rx(struct napi_struc
  			break;
  
  		/* find out which mac the packet come from. values start at 1 */
@@ -141,7 +141,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  		if (unlikely(mac < 0 || mac >= MTK_MAX_DEVS ||
  			     !eth->netdev[mac]))
-@@ -2080,7 +2111,6 @@ static int mtk_poll_tx_qdma(struct mtk_e
+@@ -2079,7 +2110,6 @@ static int mtk_poll_tx_qdma(struct mtk_e
  
  	while ((cpu != dma) && budget) {
  		u32 next_cpu = desc->txd2;
@@ -149,7 +149,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  		desc = mtk_qdma_phys_to_virt(ring, desc->txd2);
  		if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0)
-@@ -2088,15 +2118,13 @@ static int mtk_poll_tx_qdma(struct mtk_e
+@@ -2087,15 +2117,13 @@ static int mtk_poll_tx_qdma(struct mtk_e
  
  		tx_buf = mtk_desc_to_tx_buf(ring, desc,
  					    eth->soc->txrx.txd_size);
@@ -167,7 +167,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  			budget--;
  		}
-@@ -3705,7 +3733,24 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -3704,7 +3732,24 @@ static int mtk_hw_init(struct mtk_eth *e
  	mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4);
  	mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
  
@@ -193,7 +193,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		/* PSE should not drop port8 and port9 packets from WDMA Tx */
  		mtk_w32(eth, 0x00000300, PSE_DROP_CFG);
  
-@@ -4267,7 +4312,11 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4266,7 +4311,11 @@ static int mtk_add_mac(struct mtk_eth *e
  	}
  	spin_lock_init(&mac->hw_stats->stats_lock);
  	u64_stats_init(&mac->hw_stats->syncp);
diff --git a/target/linux/generic/backport-6.1/750-v6.5-11-net-ethernet-mtk_eth_soc-add-basic-support-for-MT798.patch b/target/linux/generic/backport-6.1/750-v6.5-11-net-ethernet-mtk_eth_soc-add-basic-support-for-MT798.patch
index 97a2992cfedc7c..8c24321dd4356f 100644
--- a/target/linux/generic/backport-6.1/750-v6.5-11-net-ethernet-mtk_eth_soc-add-basic-support-for-MT798.patch
+++ b/target/linux/generic/backport-6.1/750-v6.5-11-net-ethernet-mtk_eth_soc-add-basic-support-for-MT798.patch
@@ -219,7 +219,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	return;
  
  err_phy:
-@@ -726,11 +842,15 @@ static int mtk_mdio_init(struct mtk_eth
+@@ -725,11 +841,15 @@ static int mtk_mdio_init(struct mtk_eth
  	}
  	divider = min_t(unsigned int, DIV_ROUND_UP(MDC_MAX_FREQ, max_clk), 63);
  
@@ -239,7 +239,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	dev_dbg(eth->dev, "MDC is running on %d Hz\n", MDC_MAX_FREQ / divider);
  
-@@ -1191,10 +1311,19 @@ static void mtk_tx_set_dma_desc_v2(struc
+@@ -1190,10 +1310,19 @@ static void mtk_tx_set_dma_desc_v2(struc
  		data |= TX_DMA_LS0;
  	WRITE_ONCE(desc->txd3, data);
  
@@ -263,7 +263,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid);
  	WRITE_ONCE(desc->txd4, data);
  
-@@ -4361,6 +4490,17 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4360,6 +4489,17 @@ static int mtk_add_mac(struct mtk_eth *e
  			  mac->phylink_config.supported_interfaces);
  	}
  
@@ -281,7 +281,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	phylink = phylink_create(&mac->phylink_config,
  				 of_fwnode_handle(mac->of_node),
  				 phy_mode, &mtk_phylink_ops);
-@@ -4881,6 +5021,24 @@ static const struct mtk_soc_data mt7986_
+@@ -4880,6 +5020,24 @@ static const struct mtk_soc_data mt7986_
  	},
  };
  
@@ -306,7 +306,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  static const struct mtk_soc_data rt5350_data = {
  	.reg_map = &mt7628_reg_map,
  	.caps = MT7628_CAPS,
-@@ -4899,14 +5057,15 @@ static const struct mtk_soc_data rt5350_
+@@ -4898,14 +5056,15 @@ static const struct mtk_soc_data rt5350_
  };
  
  const struct of_device_id of_mtk_match[] = {
diff --git a/target/linux/generic/backport-6.1/750-v6.5-12-net-ethernet-mtk_eth_soc-enable-page_pool-support-fo.patch b/target/linux/generic/backport-6.1/750-v6.5-12-net-ethernet-mtk_eth_soc-enable-page_pool-support-fo.patch
index 62c38c7137f725..3dc4662d1a5479 100644
--- a/target/linux/generic/backport-6.1/750-v6.5-12-net-ethernet-mtk_eth_soc-enable-page_pool-support-fo.patch
+++ b/target/linux/generic/backport-6.1/750-v6.5-12-net-ethernet-mtk_eth_soc-enable-page_pool-support-fo.patch
@@ -16,7 +16,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1659,7 +1659,7 @@ static void mtk_update_rx_cpu_idx(struct
+@@ -1658,7 +1658,7 @@ static void mtk_update_rx_cpu_idx(struct
  
  static bool mtk_page_pool_enabled(struct mtk_eth *eth)
  {
diff --git a/target/linux/generic/backport-6.1/750-v6.5-13-net-ethernet-mtk_eth_soc-enable-nft-hw-flowtable_off.patch b/target/linux/generic/backport-6.1/750-v6.5-13-net-ethernet-mtk_eth_soc-enable-nft-hw-flowtable_off.patch
index b175aedf0c43e2..32f26d7d27d0a6 100644
--- a/target/linux/generic/backport-6.1/750-v6.5-13-net-ethernet-mtk_eth_soc-enable-nft-hw-flowtable_off.patch
+++ b/target/linux/generic/backport-6.1/750-v6.5-13-net-ethernet-mtk_eth_soc-enable-nft-hw-flowtable_off.patch
@@ -18,7 +18,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -5029,6 +5029,9 @@ static const struct mtk_soc_data mt7988_
+@@ -5028,6 +5028,9 @@ static const struct mtk_soc_data mt7988_
  	.required_clks = MT7988_CLKS_BITMAP,
  	.required_pctl = false,
  	.version = 3,
diff --git a/target/linux/generic/backport-6.1/750-v6.5-14-net-ethernet-mtk_eth_soc-support-per-flow-accounting.patch b/target/linux/generic/backport-6.1/750-v6.5-14-net-ethernet-mtk_eth_soc-support-per-flow-accounting.patch
index bf0a39b9d3fda8..876bdd5dd31e65 100644
--- a/target/linux/generic/backport-6.1/750-v6.5-14-net-ethernet-mtk_eth_soc-support-per-flow-accounting.patch
+++ b/target/linux/generic/backport-6.1/750-v6.5-14-net-ethernet-mtk_eth_soc-support-per-flow-accounting.patch
@@ -20,7 +20,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -5031,6 +5031,7 @@ static const struct mtk_soc_data mt7988_
+@@ -5030,6 +5030,7 @@ static const struct mtk_soc_data mt7988_
  	.version = 3,
  	.offload_version = 2,
  	.hash_offset = 4,
diff --git a/target/linux/generic/backport-6.1/750-v6.5-17-net-ethernet-mtk_eth_soc-add-reset-bits-for-MT7988.patch b/target/linux/generic/backport-6.1/750-v6.5-17-net-ethernet-mtk_eth_soc-add-reset-bits-for-MT7988.patch
index a4ff5a292e7d8e..05a18364d67968 100644
--- a/target/linux/generic/backport-6.1/750-v6.5-17-net-ethernet-mtk_eth_soc-add-reset-bits-for-MT7988.patch
+++ b/target/linux/generic/backport-6.1/750-v6.5-17-net-ethernet-mtk_eth_soc-add-reset-bits-for-MT7988.patch
@@ -16,7 +16,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -3595,19 +3595,34 @@ static void mtk_hw_reset(struct mtk_eth
+@@ -3594,19 +3594,34 @@ static void mtk_hw_reset(struct mtk_eth
  {
  	u32 val;
  
@@ -56,7 +56,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN,
  			     0x3ffffff);
  }
-@@ -3633,13 +3648,21 @@ static void mtk_hw_warm_reset(struct mtk
+@@ -3632,13 +3647,21 @@ static void mtk_hw_warm_reset(struct mtk
  		return;
  	}
  
@@ -83,7 +83,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, rst_mask);
  
-@@ -3991,11 +4014,17 @@ static void mtk_prepare_for_reset(struct
+@@ -3990,11 +4013,17 @@ static void mtk_prepare_for_reset(struct
  	u32 val;
  	int i;
  
@@ -106,7 +106,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	/* adjust PPE configurations to prepare for reset */
  	for (i = 0; i < ARRAY_SIZE(eth->ppe); i++)
-@@ -4056,11 +4085,18 @@ static void mtk_pending_work(struct work
+@@ -4055,11 +4084,18 @@ static void mtk_pending_work(struct work
  		}
  	}
  
diff --git a/target/linux/generic/backport-6.1/750-v6.5-18-net-ethernet-mtk_eth_soc-add-support-for-in-SoC-SRAM.patch b/target/linux/generic/backport-6.1/750-v6.5-18-net-ethernet-mtk_eth_soc-add-support-for-in-SoC-SRAM.patch
index 872262b0f82a80..74ac8dc89813a4 100644
--- a/target/linux/generic/backport-6.1/750-v6.5-18-net-ethernet-mtk_eth_soc-add-support-for-in-SoC-SRAM.patch
+++ b/target/linux/generic/backport-6.1/750-v6.5-18-net-ethernet-mtk_eth_soc-add-support-for-in-SoC-SRAM.patch
@@ -20,7 +20,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1119,10 +1119,13 @@ static int mtk_init_fq_dma(struct mtk_et
+@@ -1118,10 +1118,13 @@ static int mtk_init_fq_dma(struct mtk_et
  	dma_addr_t dma_addr;
  	int i;
  
@@ -38,7 +38,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	if (unlikely(!eth->scratch_ring))
  		return -ENOMEM;
  
-@@ -2430,8 +2433,14 @@ static int mtk_tx_alloc(struct mtk_eth *
+@@ -2429,8 +2432,14 @@ static int mtk_tx_alloc(struct mtk_eth *
  	if (!ring->buf)
  		goto no_tx_mem;
  
@@ -55,7 +55,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	if (!ring->dma)
  		goto no_tx_mem;
  
-@@ -2530,8 +2539,7 @@ static void mtk_tx_clean(struct mtk_eth
+@@ -2529,8 +2538,7 @@ static void mtk_tx_clean(struct mtk_eth
  		kfree(ring->buf);
  		ring->buf = NULL;
  	}
@@ -65,7 +65,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		dma_free_coherent(eth->dma_dev,
  				  ring->dma_size * soc->txrx.txd_size,
  				  ring->dma, ring->phys);
-@@ -2550,9 +2558,14 @@ static int mtk_rx_alloc(struct mtk_eth *
+@@ -2549,9 +2557,14 @@ static int mtk_rx_alloc(struct mtk_eth *
  {
  	const struct mtk_reg_map *reg_map = eth->soc->reg_map;
  	struct mtk_rx_ring *ring;
@@ -81,7 +81,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	if (rx_flag == MTK_RX_FLAGS_QDMA) {
  		if (ring_no)
  			return -EINVAL;
-@@ -2587,9 +2600,20 @@ static int mtk_rx_alloc(struct mtk_eth *
+@@ -2586,9 +2599,20 @@ static int mtk_rx_alloc(struct mtk_eth *
  		ring->page_pool = pp;
  	}
  
@@ -105,7 +105,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	if (!ring->dma)
  		return -ENOMEM;
  
-@@ -2674,7 +2698,7 @@ static int mtk_rx_alloc(struct mtk_eth *
+@@ -2673,7 +2697,7 @@ static int mtk_rx_alloc(struct mtk_eth *
  	return 0;
  }
  
@@ -114,7 +114,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  {
  	int i;
  
-@@ -2697,7 +2721,7 @@ static void mtk_rx_clean(struct mtk_eth
+@@ -2696,7 +2720,7 @@ static void mtk_rx_clean(struct mtk_eth
  		ring->data = NULL;
  	}
  
@@ -123,7 +123,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		dma_free_coherent(eth->dma_dev,
  				  ring->dma_size * eth->soc->txrx.rxd_size,
  				  ring->dma, ring->phys);
-@@ -3060,7 +3084,7 @@ static void mtk_dma_free(struct mtk_eth
+@@ -3059,7 +3083,7 @@ static void mtk_dma_free(struct mtk_eth
  	for (i = 0; i < MTK_MAX_DEVS; i++)
  		if (eth->netdev[i])
  			netdev_reset_queue(eth->netdev[i]);
@@ -132,7 +132,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		dma_free_coherent(eth->dma_dev,
  				  MTK_QDMA_RING_SIZE * soc->txrx.txd_size,
  				  eth->scratch_ring, eth->phy_scratch_ring);
-@@ -3068,13 +3092,13 @@ static void mtk_dma_free(struct mtk_eth
+@@ -3067,13 +3091,13 @@ static void mtk_dma_free(struct mtk_eth
  		eth->phy_scratch_ring = 0;
  	}
  	mtk_tx_clean(eth);
@@ -149,7 +149,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	}
  
  	kfree(eth->scratch_head);
-@@ -4642,7 +4666,7 @@ static int mtk_sgmii_init(struct mtk_eth
+@@ -4641,7 +4665,7 @@ static int mtk_sgmii_init(struct mtk_eth
  
  static int mtk_probe(struct platform_device *pdev)
  {
@@ -158,7 +158,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	struct device_node *mac_np;
  	struct mtk_eth *eth;
  	int err, i;
-@@ -4662,6 +4686,20 @@ static int mtk_probe(struct platform_dev
+@@ -4661,6 +4685,20 @@ static int mtk_probe(struct platform_dev
  	if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
  		eth->ip_align = NET_IP_ALIGN;
  
@@ -179,7 +179,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	spin_lock_init(&eth->page_lock);
  	spin_lock_init(&eth->tx_irq_lock);
  	spin_lock_init(&eth->rx_irq_lock);
-@@ -4725,6 +4763,18 @@ static int mtk_probe(struct platform_dev
+@@ -4724,6 +4762,18 @@ static int mtk_probe(struct platform_dev
  			err = -EINVAL;
  			goto err_destroy_sgmii;
  		}
diff --git a/target/linux/generic/backport-6.1/750-v6.5-19-net-ethernet-mtk_eth_soc-support-36-bit-DMA-addressi.patch b/target/linux/generic/backport-6.1/750-v6.5-19-net-ethernet-mtk_eth_soc-support-36-bit-DMA-addressi.patch
index 9266c33f825545..1584dfd07c63fe 100644
--- a/target/linux/generic/backport-6.1/750-v6.5-19-net-ethernet-mtk_eth_soc-support-36-bit-DMA-addressi.patch
+++ b/target/linux/generic/backport-6.1/750-v6.5-19-net-ethernet-mtk_eth_soc-support-36-bit-DMA-addressi.patch
@@ -19,7 +19,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1312,6 +1312,10 @@ static void mtk_tx_set_dma_desc_v2(struc
+@@ -1311,6 +1311,10 @@ static void mtk_tx_set_dma_desc_v2(struc
  	data = TX_DMA_PLEN0(info->size);
  	if (info->last)
  		data |= TX_DMA_LS0;
@@ -30,7 +30,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	WRITE_ONCE(desc->txd3, data);
  
  	 /* set forward port */
-@@ -1981,6 +1985,7 @@ static int mtk_poll_rx(struct napi_struc
+@@ -1980,6 +1984,7 @@ static int mtk_poll_rx(struct napi_struc
  	bool xdp_flush = false;
  	int idx;
  	struct sk_buff *skb;
@@ -38,7 +38,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	u8 *data, *new_data;
  	struct mtk_rx_dma_v2 *rxd, trxd;
  	int done = 0, bytes = 0;
-@@ -2096,7 +2101,10 @@ static int mtk_poll_rx(struct napi_struc
+@@ -2095,7 +2100,10 @@ static int mtk_poll_rx(struct napi_struc
  				goto release_desc;
  			}
  
@@ -50,7 +50,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  					 ring->buf_size, DMA_FROM_DEVICE);
  
  			skb = build_skb(data, ring->frag_size);
-@@ -2162,6 +2170,9 @@ release_desc:
+@@ -2161,6 +2169,9 @@ release_desc:
  		else
  			rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size);
  
@@ -60,7 +60,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		ring->calc_idx = idx;
  		done++;
  	}
-@@ -2654,6 +2665,9 @@ static int mtk_rx_alloc(struct mtk_eth *
+@@ -2653,6 +2664,9 @@ static int mtk_rx_alloc(struct mtk_eth *
  		else
  			rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size);
  
@@ -70,7 +70,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		rxd->rxd3 = 0;
  		rxd->rxd4 = 0;
  		if (mtk_is_netsys_v2_or_greater(eth)) {
-@@ -2700,6 +2714,7 @@ static int mtk_rx_alloc(struct mtk_eth *
+@@ -2699,6 +2713,7 @@ static int mtk_rx_alloc(struct mtk_eth *
  
  static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring, bool in_sram)
  {
@@ -78,7 +78,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	int i;
  
  	if (ring->data && ring->dma) {
-@@ -2713,7 +2728,10 @@ static void mtk_rx_clean(struct mtk_eth
+@@ -2712,7 +2727,10 @@ static void mtk_rx_clean(struct mtk_eth
  			if (!rxd->rxd1)
  				continue;
  
@@ -90,7 +90,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  					 ring->buf_size, DMA_FROM_DEVICE);
  			mtk_rx_put_buff(ring, ring->data[i], false);
  		}
-@@ -4700,6 +4718,14 @@ static int mtk_probe(struct platform_dev
+@@ -4699,6 +4717,14 @@ static int mtk_probe(struct platform_dev
  		}
  	}
  
diff --git a/target/linux/generic/backport-6.1/750-v6.5-20-net-ethernet-mtk_eth_soc-fix-uninitialized-variable.patch b/target/linux/generic/backport-6.1/750-v6.5-20-net-ethernet-mtk_eth_soc-fix-uninitialized-variable.patch
index 697c2db1451907..5b27458eb8e186 100644
--- a/target/linux/generic/backport-6.1/750-v6.5-20-net-ethernet-mtk_eth_soc-fix-uninitialized-variable.patch
+++ b/target/linux/generic/backport-6.1/750-v6.5-20-net-ethernet-mtk_eth_soc-fix-uninitialized-variable.patch
@@ -19,7 +19,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1989,11 +1989,11 @@ static int mtk_poll_rx(struct napi_struc
+@@ -1988,11 +1988,11 @@ static int mtk_poll_rx(struct napi_struc
  	u8 *data, *new_data;
  	struct mtk_rx_dma_v2 *rxd, trxd;
  	int done = 0, bytes = 0;
@@ -32,7 +32,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  		u32 hash, reason;
  		int mac = 0;
  
-@@ -2170,7 +2170,8 @@ release_desc:
+@@ -2169,7 +2169,8 @@ release_desc:
  		else
  			rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size);
  
diff --git a/target/linux/generic/backport-6.1/760-v6.9-net-phy-aquantia-add-AQR111-and-AQR111B0-PHY-ID.patch b/target/linux/generic/backport-6.1/760-v6.9-net-phy-aquantia-add-AQR111-and-AQR111B0-PHY-ID.patch
new file mode 100644
index 00000000000000..32ac37e8d02ede
--- /dev/null
+++ b/target/linux/generic/backport-6.1/760-v6.9-net-phy-aquantia-add-AQR111-and-AQR111B0-PHY-ID.patch
@@ -0,0 +1,102 @@
+From 038ba1dc4e54d51d953f5618d8eb5dd39bd9de25 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Tue, 13 Feb 2024 14:35:51 +0100
+Subject: [PATCH] net: phy: aquantia: add AQR111 and AQR111B0 PHY ID
+
+Add Aquantia AQR111 and AQR111B0 PHY ID. These PHY advertise 10G speed
+but actually supports up to 5G speed, hence some manual fixup is needed.
+
+The Aquantia AQR111B0 PHY is just a variant of the AQR111 with smaller
+chip size.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://lore.kernel.org/r/20240213133558.1836-1-ansuelsmth@gmail.com
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/phy/aquantia/aquantia_main.c | 52 ++++++++++++++++++++++++
+ 1 file changed, 52 insertions(+)
+
+--- a/drivers/net/phy/aquantia/aquantia_main.c
++++ b/drivers/net/phy/aquantia/aquantia_main.c
+@@ -22,6 +22,8 @@
+ #define PHY_ID_AQR107	0x03a1b4e0
+ #define PHY_ID_AQCS109	0x03a1b5c2
+ #define PHY_ID_AQR405	0x03a1b4b0
++#define PHY_ID_AQR111	0x03a1b610
++#define PHY_ID_AQR111B0	0x03a1b612
+ #define PHY_ID_AQR113C	0x31c31c12
+ 
+ #define MDIO_PHYXS_VEND_IF_STATUS		0xe812
+@@ -670,6 +672,16 @@ static int aqr107_probe(struct phy_devic
+ 	return aqr_hwmon_probe(phydev);
+ }
+ 
++static int aqr111_config_init(struct phy_device *phydev)
++{
++	/* AQR111 reports supporting speed up to 10G,
++	 * however only speeds up to 5G are supported.
++	 */
++	phy_set_max_speed(phydev, SPEED_5000);
++
++	return aqr107_config_init(phydev);
++}
++
+ static struct phy_driver aqr_driver[] = {
+ {
+ 	PHY_ID_MATCH_MODEL(PHY_ID_AQ1202),
+@@ -744,6 +756,44 @@ static struct phy_driver aqr_driver[] =
+ 	.link_change_notify = aqr107_link_change_notify,
+ },
+ {
++	PHY_ID_MATCH_MODEL(PHY_ID_AQR111),
++	.name		= "Aquantia AQR111",
++	.probe		= aqr107_probe,
++	.get_rate_matching = aqr107_get_rate_matching,
++	.config_init	= aqr111_config_init,
++	.config_aneg    = aqr_config_aneg,
++	.config_intr	= aqr_config_intr,
++	.handle_interrupt = aqr_handle_interrupt,
++	.read_status	= aqr107_read_status,
++	.get_tunable    = aqr107_get_tunable,
++	.set_tunable    = aqr107_set_tunable,
++	.suspend	= aqr107_suspend,
++	.resume		= aqr107_resume,
++	.get_sset_count	= aqr107_get_sset_count,
++	.get_strings	= aqr107_get_strings,
++	.get_stats	= aqr107_get_stats,
++	.link_change_notify = aqr107_link_change_notify,
++},
++{
++	PHY_ID_MATCH_MODEL(PHY_ID_AQR111B0),
++	.name		= "Aquantia AQR111B0",
++	.probe		= aqr107_probe,
++	.get_rate_matching = aqr107_get_rate_matching,
++	.config_init	= aqr111_config_init,
++	.config_aneg    = aqr_config_aneg,
++	.config_intr	= aqr_config_intr,
++	.handle_interrupt = aqr_handle_interrupt,
++	.read_status	= aqr107_read_status,
++	.get_tunable    = aqr107_get_tunable,
++	.set_tunable    = aqr107_set_tunable,
++	.suspend	= aqr107_suspend,
++	.resume		= aqr107_resume,
++	.get_sset_count	= aqr107_get_sset_count,
++	.get_strings	= aqr107_get_strings,
++	.get_stats	= aqr107_get_stats,
++	.link_change_notify = aqr107_link_change_notify,
++},
++{
+ 	PHY_ID_MATCH_MODEL(PHY_ID_AQR405),
+ 	.name		= "Aquantia AQR405",
+ 	.config_aneg    = aqr_config_aneg,
+@@ -782,6 +832,8 @@ static struct mdio_device_id __maybe_unu
+ 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR107) },
+ 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },
+ 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
++	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR111) },
++	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR111B0) },
+ 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
+ 	{ }
+ };
diff --git a/target/linux/generic/backport-6.1/761-v6.9-net-phy-aquantia-add-AQR113-PHY-ID.patch b/target/linux/generic/backport-6.1/761-v6.9-net-phy-aquantia-add-AQR113-PHY-ID.patch
new file mode 100644
index 00000000000000..073bbbd49d03c9
--- /dev/null
+++ b/target/linux/generic/backport-6.1/761-v6.9-net-phy-aquantia-add-AQR113-PHY-ID.patch
@@ -0,0 +1,60 @@
+From 71b605d32017e5b8d257db7344bc2f8e8fcc973e Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Thu, 15 Feb 2024 16:30:05 +0100
+Subject: [PATCH] net: phy: aquantia: add AQR113 PHY ID
+
+Add Aquantia AQR113 PHY ID. Aquantia AQR113 is just a chip size variant of
+the already supported AQR133C where the only difference is the PHY ID
+and the hw chip size.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/aquantia/aquantia_main.c | 21 +++++++++++++++++++++
+ 1 file changed, 21 insertions(+)
+
+--- a/drivers/net/phy/aquantia/aquantia_main.c
++++ b/drivers/net/phy/aquantia/aquantia_main.c
+@@ -24,6 +24,7 @@
+ #define PHY_ID_AQR405	0x03a1b4b0
+ #define PHY_ID_AQR111	0x03a1b610
+ #define PHY_ID_AQR111B0	0x03a1b612
++#define PHY_ID_AQR113	0x31c31c40
+ #define PHY_ID_AQR113C	0x31c31c12
+ 
+ #define MDIO_PHYXS_VEND_IF_STATUS		0xe812
+@@ -802,6 +803,25 @@ static struct phy_driver aqr_driver[] =
+ 	.read_status	= aqr_read_status,
+ },
+ {
++	PHY_ID_MATCH_MODEL(PHY_ID_AQR113),
++	.name		= "Aquantia AQR113",
++	.probe          = aqr107_probe,
++	.get_rate_matching = aqr107_get_rate_matching,
++	.config_init    = aqr107_config_init,
++	.config_aneg    = aqr_config_aneg,
++	.config_intr    = aqr_config_intr,
++	.handle_interrupt       = aqr_handle_interrupt,
++	.read_status    = aqr107_read_status,
++	.get_tunable    = aqr107_get_tunable,
++	.set_tunable    = aqr107_set_tunable,
++	.suspend        = aqr107_suspend,
++	.resume         = aqr107_resume,
++	.get_sset_count = aqr107_get_sset_count,
++	.get_strings    = aqr107_get_strings,
++	.get_stats      = aqr107_get_stats,
++	.link_change_notify = aqr107_link_change_notify,
++},
++{
+ 	PHY_ID_MATCH_MODEL(PHY_ID_AQR113C),
+ 	.name           = "Aquantia AQR113C",
+ 	.probe          = aqr107_probe,
+@@ -834,6 +854,7 @@ static struct mdio_device_id __maybe_unu
+ 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
+ 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR111) },
+ 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR111B0) },
++	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113) },
+ 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
+ 	{ }
+ };
diff --git a/target/linux/generic/backport-6.1/762-v6.9-net-phy-aquantia-add-AQR813-PHY-ID.patch b/target/linux/generic/backport-6.1/762-v6.9-net-phy-aquantia-add-AQR813-PHY-ID.patch
new file mode 100644
index 00000000000000..965b8c91b28248
--- /dev/null
+++ b/target/linux/generic/backport-6.1/762-v6.9-net-phy-aquantia-add-AQR813-PHY-ID.patch
@@ -0,0 +1,59 @@
+From 6d47302a3f0ba31445478d518d98bd55918bc8ab Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Thu, 15 Feb 2024 22:43:30 +0100
+Subject: [PATCH] net: phy: aquantia: add AQR813 PHY ID
+
+Aquantia AQR813 is the Octal Port variant of the AQR113. Add PHY ID for
+it to provide support for it.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/aquantia/aquantia_main.c | 21 +++++++++++++++++++++
+ 1 file changed, 21 insertions(+)
+
+--- a/drivers/net/phy/aquantia/aquantia_main.c
++++ b/drivers/net/phy/aquantia/aquantia_main.c
+@@ -26,6 +26,7 @@
+ #define PHY_ID_AQR111B0	0x03a1b612
+ #define PHY_ID_AQR113	0x31c31c40
+ #define PHY_ID_AQR113C	0x31c31c12
++#define PHY_ID_AQR813	0x31c31cb2
+ 
+ #define MDIO_PHYXS_VEND_IF_STATUS		0xe812
+ #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK	GENMASK(7, 3)
+@@ -840,6 +841,25 @@ static struct phy_driver aqr_driver[] =
+ 	.get_stats      = aqr107_get_stats,
+ 	.link_change_notify = aqr107_link_change_notify,
+ },
++{
++	PHY_ID_MATCH_MODEL(PHY_ID_AQR813),
++	.name		= "Aquantia AQR813",
++	.probe		= aqr107_probe,
++	.get_rate_matching = aqr107_get_rate_matching,
++	.config_init	= aqr107_config_init,
++	.config_aneg    = aqr_config_aneg,
++	.config_intr	= aqr_config_intr,
++	.handle_interrupt = aqr_handle_interrupt,
++	.read_status	= aqr107_read_status,
++	.get_tunable    = aqr107_get_tunable,
++	.set_tunable    = aqr107_set_tunable,
++	.suspend	= aqr107_suspend,
++	.resume		= aqr107_resume,
++	.get_sset_count	= aqr107_get_sset_count,
++	.get_strings	= aqr107_get_strings,
++	.get_stats	= aqr107_get_stats,
++	.link_change_notify = aqr107_link_change_notify,
++},
+ };
+ 
+ module_phy_driver(aqr_driver);
+@@ -856,6 +876,7 @@ static struct mdio_device_id __maybe_unu
+ 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR111B0) },
+ 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113) },
+ 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
++	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR813) },
+ 	{ }
+ };
+ 
diff --git a/target/linux/generic/backport-6.1/771-v6.7-01-net-stmmac-improve-TX-timer-arm-logic.patch b/target/linux/generic/backport-6.1/771-v6.7-01-net-stmmac-improve-TX-timer-arm-logic.patch
index 07c087260c257d..aa0d730bc8a0fa 100644
--- a/target/linux/generic/backport-6.1/771-v6.7-01-net-stmmac-improve-TX-timer-arm-logic.patch
+++ b/target/linux/generic/backport-6.1/771-v6.7-01-net-stmmac-improve-TX-timer-arm-logic.patch
@@ -46,7 +46,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
 +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-@@ -2975,13 +2975,25 @@ static void stmmac_tx_timer_arm(struct s
+@@ -2974,13 +2974,25 @@ static void stmmac_tx_timer_arm(struct s
  {
  	struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue];
  	u32 tx_coal_timer = priv->tx_coal_timer[queue];
diff --git a/target/linux/generic/backport-6.1/771-v6.7-02-net-stmmac-move-TX-timer-arm-after-DMA-enable.patch b/target/linux/generic/backport-6.1/771-v6.7-02-net-stmmac-move-TX-timer-arm-after-DMA-enable.patch
index d1e04e9069f3fc..95dd24881b6652 100644
--- a/target/linux/generic/backport-6.1/771-v6.7-02-net-stmmac-move-TX-timer-arm-after-DMA-enable.patch
+++ b/target/linux/generic/backport-6.1/771-v6.7-02-net-stmmac-move-TX-timer-arm-after-DMA-enable.patch
@@ -18,7 +18,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
 +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-@@ -2528,9 +2528,13 @@ static void stmmac_bump_dma_threshold(st
+@@ -2527,9 +2527,13 @@ static void stmmac_bump_dma_threshold(st
   * @priv: driver private structure
   * @budget: napi budget limiting this functions packet handling
   * @queue: TX queue index
@@ -33,7 +33,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  {
  	struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue];
  	unsigned int bytes_compl = 0, pkts_compl = 0;
-@@ -2693,7 +2697,7 @@ static int stmmac_tx_clean(struct stmmac
+@@ -2692,7 +2696,7 @@ static int stmmac_tx_clean(struct stmmac
  
  	/* We still have pending packets, let's call for a new scheduling */
  	if (tx_q->dirty_tx != tx_q->cur_tx)
@@ -42,7 +42,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  	__netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue));
  
-@@ -5485,12 +5489,13 @@ static int stmmac_napi_poll_tx(struct na
+@@ -5488,12 +5492,13 @@ static int stmmac_napi_poll_tx(struct na
  	struct stmmac_channel *ch =
  		container_of(napi, struct stmmac_channel, tx_napi);
  	struct stmmac_priv *priv = ch->priv_data;
@@ -57,7 +57,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	work_done = min(work_done, budget);
  
  	if (work_done < budget && napi_complete_done(napi, work_done)) {
-@@ -5501,6 +5506,10 @@ static int stmmac_napi_poll_tx(struct na
+@@ -5504,6 +5509,10 @@ static int stmmac_napi_poll_tx(struct na
  		spin_unlock_irqrestore(&ch->lock, flags);
  	}
  
@@ -68,7 +68,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	return work_done;
  }
  
-@@ -5509,12 +5518,13 @@ static int stmmac_napi_poll_rxtx(struct
+@@ -5512,12 +5521,13 @@ static int stmmac_napi_poll_rxtx(struct
  	struct stmmac_channel *ch =
  		container_of(napi, struct stmmac_channel, rxtx_napi);
  	struct stmmac_priv *priv = ch->priv_data;
@@ -83,7 +83,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	tx_done = min(tx_done, budget);
  
  	rx_done = stmmac_rx_zc(priv, budget, chan);
-@@ -5539,6 +5549,10 @@ static int stmmac_napi_poll_rxtx(struct
+@@ -5542,6 +5552,10 @@ static int stmmac_napi_poll_rxtx(struct
  		spin_unlock_irqrestore(&ch->lock, flags);
  	}
  
diff --git a/target/linux/generic/backport-6.1/771-v6.7-03-net-stmmac-increase-TX-coalesce-timer-to-5ms.patch b/target/linux/generic/backport-6.1/771-v6.7-03-net-stmmac-increase-TX-coalesce-timer-to-5ms.patch
index cc8cbf5a1639ff..bce54eba4f0679 100644
--- a/target/linux/generic/backport-6.1/771-v6.7-03-net-stmmac-increase-TX-coalesce-timer-to-5ms.patch
+++ b/target/linux/generic/backport-6.1/771-v6.7-03-net-stmmac-increase-TX-coalesce-timer-to-5ms.patch
@@ -27,7 +27,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/ethernet/stmicro/stmmac/common.h
 +++ b/drivers/net/ethernet/stmicro/stmmac/common.h
-@@ -286,7 +286,7 @@ struct stmmac_safety_stats {
+@@ -287,7 +287,7 @@ struct stmmac_safety_stats {
  #define MIN_DMA_RIWT		0x10
  #define DEF_DMA_RIWT		0xa0
  /* Tx coalesce parameters */
diff --git a/target/linux/generic/backport-6.1/778-v6.3-02-net-dsa-qca8k-convert-to-regmap-read-write-API.patch b/target/linux/generic/backport-6.1/778-v6.3-02-net-dsa-qca8k-convert-to-regmap-read-write-API.patch
index 0a631a09c1daa5..b8f8071b0a14f3 100644
--- a/target/linux/generic/backport-6.1/778-v6.3-02-net-dsa-qca8k-convert-to-regmap-read-write-API.patch
+++ b/target/linux/generic/backport-6.1/778-v6.3-02-net-dsa-qca8k-convert-to-regmap-read-write-API.patch
@@ -168,7 +168,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  };
  
  static int
-@@ -2102,8 +2158,6 @@ static SIMPLE_DEV_PM_OPS(qca8k_pm_ops,
+@@ -2112,8 +2168,6 @@ static SIMPLE_DEV_PM_OPS(qca8k_pm_ops,
  
  static const struct qca8k_info_ops qca8xxx_ops = {
  	.autocast_mib = qca8k_get_ethtool_stats_eth,
diff --git a/target/linux/generic/backport-6.1/780-v6.6-01-net-dsa-qca8k-make-learning-configurable-and-keep-of.patch b/target/linux/generic/backport-6.1/780-v6.6-01-net-dsa-qca8k-make-learning-configurable-and-keep-of.patch
index 6e93491a1278d4..d31789370e8c6b 100644
--- a/target/linux/generic/backport-6.1/780-v6.6-01-net-dsa-qca8k-make-learning-configurable-and-keep-of.patch
+++ b/target/linux/generic/backport-6.1/780-v6.6-01-net-dsa-qca8k-make-learning-configurable-and-keep-of.patch
@@ -32,7 +32,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/dsa/qca/qca8k-8xxx.c
 +++ b/drivers/net/dsa/qca/qca8k-8xxx.c
-@@ -1894,9 +1894,8 @@ qca8k_setup(struct dsa_switch *ds)
+@@ -1905,9 +1905,8 @@ qca8k_setup(struct dsa_switch *ds)
  			if (ret)
  				return ret;
  
@@ -44,7 +44,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  			if (ret)
  				return ret;
  
-@@ -2002,6 +2001,8 @@ static const struct dsa_switch_ops qca8k
+@@ -2013,6 +2012,8 @@ static const struct dsa_switch_ops qca8k
  	.port_change_mtu	= qca8k_port_change_mtu,
  	.port_max_mtu		= qca8k_port_max_mtu,
  	.port_stp_state_set	= qca8k_port_stp_state_set,
diff --git a/target/linux/generic/backport-6.1/780-v6.6-02-net-dsa-qca8k-limit-user-ports-access-to-the-first-C.patch b/target/linux/generic/backport-6.1/780-v6.6-02-net-dsa-qca8k-limit-user-ports-access-to-the-first-C.patch
index fdb3a8cdb9486b..4b457f67de8a6c 100644
--- a/target/linux/generic/backport-6.1/780-v6.6-02-net-dsa-qca8k-limit-user-ports-access-to-the-first-C.patch
+++ b/target/linux/generic/backport-6.1/780-v6.6-02-net-dsa-qca8k-limit-user-ports-access-to-the-first-C.patch
@@ -26,7 +26,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/dsa/qca/qca8k-8xxx.c
 +++ b/drivers/net/dsa/qca/qca8k-8xxx.c
-@@ -1874,18 +1874,16 @@ qca8k_setup(struct dsa_switch *ds)
+@@ -1885,18 +1885,16 @@ qca8k_setup(struct dsa_switch *ds)
  	if (ret)
  		return ret;
  
diff --git a/target/linux/generic/backport-6.1/780-v6.6-03-net-dsa-qca8k-move-qca8xxx-hol-fixup-to-separate-fun.patch b/target/linux/generic/backport-6.1/780-v6.6-03-net-dsa-qca8k-move-qca8xxx-hol-fixup-to-separate-fun.patch
index c789fdf05ee7cc..f556628b5b5dea 100644
--- a/target/linux/generic/backport-6.1/780-v6.6-03-net-dsa-qca8k-move-qca8xxx-hol-fixup-to-separate-fun.patch
+++ b/target/linux/generic/backport-6.1/780-v6.6-03-net-dsa-qca8k-move-qca8xxx-hol-fixup-to-separate-fun.patch
@@ -17,7 +17,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/dsa/qca/qca8k-8xxx.c
 +++ b/drivers/net/dsa/qca/qca8k-8xxx.c
-@@ -1784,6 +1784,46 @@ static int qca8k_connect_tag_protocol(st
+@@ -1795,6 +1795,46 @@ static int qca8k_connect_tag_protocol(st
  	return 0;
  }
  
@@ -64,7 +64,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  static int
  qca8k_setup(struct dsa_switch *ds)
  {
-@@ -1919,42 +1959,8 @@ qca8k_setup(struct dsa_switch *ds)
+@@ -1930,42 +1970,8 @@ qca8k_setup(struct dsa_switch *ds)
  		 * missing settings to improve switch stability under load condition.
  		 * This problem is limited to qca8337 and other qca8k switch are not affected.
  		 */
diff --git a/target/linux/generic/backport-6.1/780-v6.6-04-net-dsa-qca8k-use-dsa_for_each-macro-instead-of-for-.patch b/target/linux/generic/backport-6.1/780-v6.6-04-net-dsa-qca8k-use-dsa_for_each-macro-instead-of-for-.patch
index 4f9581235db18c..faa0142ca997ba 100644
--- a/target/linux/generic/backport-6.1/780-v6.6-04-net-dsa-qca8k-use-dsa_for_each-macro-instead-of-for-.patch
+++ b/target/linux/generic/backport-6.1/780-v6.6-04-net-dsa-qca8k-use-dsa_for_each-macro-instead-of-for-.patch
@@ -17,7 +17,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/dsa/qca/qca8k-8xxx.c
 +++ b/drivers/net/dsa/qca/qca8k-8xxx.c
-@@ -1828,7 +1828,8 @@ static int
+@@ -1839,7 +1839,8 @@ static int
  qca8k_setup(struct dsa_switch *ds)
  {
  	struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
@@ -27,7 +27,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	u32 mask;
  
  	cpu_port = qca8k_find_cpu_port(ds);
-@@ -1879,27 +1880,27 @@ qca8k_setup(struct dsa_switch *ds)
+@@ -1890,27 +1891,27 @@ qca8k_setup(struct dsa_switch *ds)
  		dev_warn(priv->dev, "mib init failed");
  
  	/* Initial setup of all ports */
@@ -70,7 +70,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	}
  
  	/* Forward all unknown frames to CPU port for Linux processing
-@@ -1921,48 +1922,48 @@ qca8k_setup(struct dsa_switch *ds)
+@@ -1932,48 +1933,48 @@ qca8k_setup(struct dsa_switch *ds)
  		return ret;
  
  	/* Setup connection between CPU port & user ports
diff --git a/target/linux/generic/backport-6.1/792-v6.6-net-phylink-add-pcs_enable-pcs_disable-methods.patch b/target/linux/generic/backport-6.1/792-v6.6-net-phylink-add-pcs_enable-pcs_disable-methods.patch
index 893a81246d8811..f82c8fc622b99d 100644
--- a/target/linux/generic/backport-6.1/792-v6.6-net-phylink-add-pcs_enable-pcs_disable-methods.patch
+++ b/target/linux/generic/backport-6.1/792-v6.6-net-phylink-add-pcs_enable-pcs_disable-methods.patch
@@ -27,15 +27,15 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  };
  
  /**
-@@ -71,6 +75,7 @@ struct phylink {
- 	struct mutex state_mutex;
+@@ -72,6 +76,7 @@ struct phylink {
  	struct phylink_link_state phy_state;
  	struct work_struct resolve;
+ 	unsigned int pcs_neg_mode;
 +	unsigned int pcs_state;
  
  	bool mac_link_dropped;
  	bool using_mac_select_pcs;
-@@ -990,6 +995,22 @@ static void phylink_mac_pcs_an_restart(s
+@@ -992,6 +997,22 @@ static void phylink_resolve_an_pause(str
  	}
  }
  
@@ -55,16 +55,17 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 +	return err;
 +}
 +
- static void phylink_major_config(struct phylink *pl, bool restart,
- 				  const struct phylink_link_state *state)
- {
-@@ -1026,11 +1047,16 @@ static void phylink_major_config(struct
+ static int phylink_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
+ 			      const struct phylink_link_state *state,
+ 			      bool permit_pause_to_mac)
+@@ -1094,11 +1115,17 @@ static void phylink_major_config(struct
  	/* If we have a new PCS, switch to the new PCS after preparing the MAC
  	 * for the change.
  	 */
 -	if (pcs_changed)
 +	if (pcs_changed) {
 +		phylink_pcs_disable(pl->pcs);
++
  		pl->pcs = pcs;
 +	}
  
@@ -73,18 +74,18 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 +	if (pl->pcs_state == PCS_STATE_STARTING || pcs_changed)
 +		phylink_pcs_enable(pl->pcs);
 +
- 	if (pl->pcs) {
- 		err = pl->pcs->ops->pcs_config(pl->pcs, pl->cur_link_an_mode,
- 					       state->interface,
-@@ -1502,6 +1528,7 @@ struct phylink *phylink_create(struct ph
+ 	neg_mode = pl->cur_link_an_mode;
+ 	if (pl->pcs && pl->pcs->neg_mode)
+ 		neg_mode = pl->pcs_neg_mode;
+@@ -1586,6 +1613,7 @@ struct phylink *phylink_create(struct ph
+ 	pl->link_config.pause = MLO_PAUSE_AN;
  	pl->link_config.speed = SPEED_UNKNOWN;
  	pl->link_config.duplex = DUPLEX_UNKNOWN;
- 	pl->link_config.an_enabled = true;
 +	pl->pcs_state = PCS_STATE_DOWN;
  	pl->mac_ops = mac_ops;
  	__set_bit(PHYLINK_DISABLE_STOPPED, &pl->phylink_disable_state);
  	timer_setup(&pl->link_poll, phylink_fixed_poll, 0);
-@@ -1903,6 +1930,8 @@ void phylink_start(struct phylink *pl)
+@@ -1987,6 +2015,8 @@ void phylink_start(struct phylink *pl)
  	if (pl->netdev)
  		netif_carrier_off(pl->netdev);
  
@@ -93,7 +94,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	/* Apply the link configuration to the MAC when starting. This allows
  	 * a fixed-link to start with the correct parameters, and also
  	 * ensures that we set the appropriate advertisement for Serdes links.
-@@ -1913,6 +1942,8 @@ void phylink_start(struct phylink *pl)
+@@ -1997,6 +2027,8 @@ void phylink_start(struct phylink *pl)
  	 */
  	phylink_mac_initial_config(pl, true);
  
@@ -102,7 +103,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	phylink_enable_and_run_resolve(pl, PHYLINK_DISABLE_STOPPED);
  
  	if (pl->cfg_link_an_mode == MLO_AN_FIXED && pl->link_gpio) {
-@@ -1931,15 +1962,9 @@ void phylink_start(struct phylink *pl)
+@@ -2015,15 +2047,9 @@ void phylink_start(struct phylink *pl)
  			poll = true;
  	}
  
@@ -120,7 +121,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	if (poll)
  		mod_timer(&pl->link_poll, jiffies + HZ);
  	if (pl->phydev)
-@@ -1976,6 +2001,10 @@ void phylink_stop(struct phylink *pl)
+@@ -2060,6 +2086,10 @@ void phylink_stop(struct phylink *pl)
  	}
  
  	phylink_run_resolve_and_disable(pl, PHYLINK_DISABLE_STOPPED);
@@ -133,7 +134,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
 --- a/include/linux/phylink.h
 +++ b/include/linux/phylink.h
-@@ -446,6 +446,8 @@ struct phylink_pcs {
+@@ -533,6 +533,8 @@ struct phylink_pcs {
  /**
   * struct phylink_pcs_ops - MAC PCS operations structure.
   * @pcs_validate: validate the link configuration.
@@ -142,7 +143,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
   * @pcs_get_state: read the current MAC PCS link state from the hardware.
   * @pcs_config: configure the MAC PCS for the selected mode and state.
   * @pcs_an_restart: restart 802.3z BaseX autonegotiation.
-@@ -455,6 +457,8 @@ struct phylink_pcs {
+@@ -542,6 +544,8 @@ struct phylink_pcs {
  struct phylink_pcs_ops {
  	int (*pcs_validate)(struct phylink_pcs *pcs, unsigned long *supported,
  			    const struct phylink_link_state *state);
@@ -150,8 +151,8 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 +	void (*pcs_disable)(struct phylink_pcs *pcs);
  	void (*pcs_get_state)(struct phylink_pcs *pcs,
  			      struct phylink_link_state *state);
- 	int (*pcs_config)(struct phylink_pcs *pcs, unsigned int mode,
-@@ -485,6 +489,18 @@ int pcs_validate(struct phylink_pcs *pcs
+ 	int (*pcs_config)(struct phylink_pcs *pcs, unsigned int neg_mode,
+@@ -572,6 +576,18 @@ int pcs_validate(struct phylink_pcs *pcs
  		 const struct phylink_link_state *state);
  
  /**
diff --git a/target/linux/generic/backport-6.1/793-v6.6-net-pcs-lynxi-implement-pcs_disable-op.patch b/target/linux/generic/backport-6.1/793-v6.6-net-pcs-lynxi-implement-pcs_disable-op.patch
index eb9b4b7c09ee0d..6b6369761a185e 100644
--- a/target/linux/generic/backport-6.1/793-v6.6-net-pcs-lynxi-implement-pcs_disable-op.patch
+++ b/target/linux/generic/backport-6.1/793-v6.6-net-pcs-lynxi-implement-pcs_disable-op.patch
@@ -22,7 +22,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/pcs/pcs-mtk-lynxi.c
 +++ b/drivers/net/pcs/pcs-mtk-lynxi.c
-@@ -241,11 +241,19 @@ static void mtk_pcs_lynxi_link_up(struct
+@@ -234,11 +234,19 @@ static void mtk_pcs_lynxi_link_up(struct
  	}
  }
  
diff --git a/target/linux/generic/backport-6.1/801-v6.4-02-net-dsa-qca8k-add-LEDs-basic-support.patch b/target/linux/generic/backport-6.1/801-v6.4-02-net-dsa-qca8k-add-LEDs-basic-support.patch
index 4bd84223ef33f1..409fe9c7a19c79 100644
--- a/target/linux/generic/backport-6.1/801-v6.4-02-net-dsa-qca8k-add-LEDs-basic-support.patch
+++ b/target/linux/generic/backport-6.1/801-v6.4-02-net-dsa-qca8k-add-LEDs-basic-support.patch
@@ -71,7 +71,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  static void
  qca8k_split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
-@@ -1840,6 +1841,10 @@ qca8k_setup(struct dsa_switch *ds)
+@@ -1851,6 +1852,10 @@ qca8k_setup(struct dsa_switch *ds)
  	if (ret)
  		return ret;
  
diff --git a/target/linux/generic/backport-6.1/801-v6.4-05-net-phy-Add-a-binding-for-PHY-LEDs.patch b/target/linux/generic/backport-6.1/801-v6.4-05-net-phy-Add-a-binding-for-PHY-LEDs.patch
index d33fc72dd1ea9a..0d2c0bcd83f26f 100644
--- a/target/linux/generic/backport-6.1/801-v6.4-05-net-phy-Add-a-binding-for-PHY-LEDs.patch
+++ b/target/linux/generic/backport-6.1/801-v6.4-05-net-phy-Add-a-binding-for-PHY-LEDs.patch
@@ -48,7 +48,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  #include <linux/netdevice.h>
  #include <linux/phy.h>
  #include <linux/phy_led_triggers.h>
-@@ -644,6 +646,7 @@ struct phy_device *phy_device_create(str
+@@ -642,6 +644,7 @@ struct phy_device *phy_device_create(str
  	device_initialize(&mdiodev->dev);
  
  	dev->state = PHY_DOWN;
@@ -56,7 +56,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	mutex_init(&dev->lock);
  	INIT_DELAYED_WORK(&dev->state_queue, phy_state_machine);
-@@ -2931,6 +2934,74 @@ static bool phy_drv_supports_irq(struct
+@@ -3035,6 +3038,74 @@ static bool phy_drv_supports_irq(struct
  	return phydrv->config_intr && phydrv->handle_interrupt;
  }
  
@@ -131,7 +131,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  /**
   * fwnode_mdio_find_device - Given a fwnode, find the mdio_device
   * @fwnode: pointer to the mdio_device's fwnode
-@@ -3109,6 +3180,11 @@ static int phy_probe(struct device *dev)
+@@ -3213,6 +3284,11 @@ static int phy_probe(struct device *dev)
  	/* Set the state to READY by default */
  	phydev->state = PHY_READY;
  
@@ -153,7 +153,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  #include <linux/linkmode.h>
  #include <linux/netlink.h>
  #include <linux/mdio.h>
-@@ -602,6 +603,7 @@ struct macsec_ops;
+@@ -606,6 +607,7 @@ struct macsec_ops;
   * @phy_num_led_triggers: Number of triggers in @phy_led_triggers
   * @led_link_trigger: LED trigger for link up/down
   * @last_triggered: last LED trigger for link speed
@@ -161,7 +161,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
   * @master_slave_set: User requested master/slave configuration
   * @master_slave_get: Current master/slave advertisement
   * @master_slave_state: Current master/slave configuration
-@@ -694,6 +696,7 @@ struct phy_device {
+@@ -698,6 +700,7 @@ struct phy_device {
  
  	struct phy_led_trigger *led_link_trigger;
  #endif
@@ -169,7 +169,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	/*
  	 * Interrupt number for this PHY
-@@ -768,6 +771,19 @@ struct phy_tdr_config {
+@@ -772,6 +775,19 @@ struct phy_tdr_config {
  #define PHY_PAIR_ALL -1
  
  /**
diff --git a/target/linux/generic/backport-6.1/801-v6.4-06-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch b/target/linux/generic/backport-6.1/801-v6.4-06-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch
index c1678ce2ea3a24..4873c40a7766b3 100644
--- a/target/linux/generic/backport-6.1/801-v6.4-06-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch
+++ b/target/linux/generic/backport-6.1/801-v6.4-06-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch
@@ -20,7 +20,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/drivers/net/phy/phy_device.c
 +++ b/drivers/net/phy/phy_device.c
-@@ -2934,11 +2934,18 @@ static bool phy_drv_supports_irq(struct
+@@ -3038,11 +3038,18 @@ static bool phy_drv_supports_irq(struct
  	return phydrv->config_intr && phydrv->handle_interrupt;
  }
  
@@ -41,7 +41,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  }
  
  static int of_phy_led(struct phy_device *phydev,
-@@ -2955,12 +2962,14 @@ static int of_phy_led(struct phy_device
+@@ -3059,12 +3066,14 @@ static int of_phy_led(struct phy_device
  		return -ENOMEM;
  
  	cdev = &phyled->led_cdev;
@@ -59,7 +59,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	init_data.fwnode = of_fwnode_handle(led);
 --- a/include/linux/phy.h
 +++ b/include/linux/phy.h
-@@ -774,15 +774,19 @@ struct phy_tdr_config {
+@@ -778,15 +778,19 @@ struct phy_tdr_config {
   * struct phy_led: An LED driven by the PHY
   *
   * @list: List of LEDs
@@ -79,7 +79,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  /**
   * struct phy_driver - Driver structure for a particular PHY type
   *
-@@ -997,6 +1001,15 @@ struct phy_driver {
+@@ -1001,6 +1005,15 @@ struct phy_driver {
  	int (*get_sqi)(struct phy_device *dev);
  	/** @get_sqi_max: Get the maximum signal quality indication */
  	int (*get_sqi_max)(struct phy_device *dev);
diff --git a/target/linux/generic/backport-6.1/801-v6.4-08-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch b/target/linux/generic/backport-6.1/801-v6.4-08-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch
index f234b2bff13018..00bdcc54689ce6 100644
--- a/target/linux/generic/backport-6.1/801-v6.4-08-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch
+++ b/target/linux/generic/backport-6.1/801-v6.4-08-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch
@@ -18,7 +18,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/drivers/net/phy/phy_device.c
 +++ b/drivers/net/phy/phy_device.c
-@@ -2948,6 +2948,22 @@ static int phy_led_set_brightness(struct
+@@ -3052,6 +3052,22 @@ static int phy_led_set_brightness(struct
  	return err;
  }
  
@@ -41,7 +41,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  static int of_phy_led(struct phy_device *phydev,
  		      struct device_node *led)
  {
-@@ -2970,6 +2986,8 @@ static int of_phy_led(struct phy_device
+@@ -3074,6 +3090,8 @@ static int of_phy_led(struct phy_device
  
  	if (phydev->drv->led_brightness_set)
  		cdev->brightness_set_blocking = phy_led_set_brightness;
@@ -52,7 +52,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	init_data.fwnode = of_fwnode_handle(led);
 --- a/include/linux/phy.h
 +++ b/include/linux/phy.h
-@@ -1010,6 +1010,18 @@ struct phy_driver {
+@@ -1014,6 +1014,18 @@ struct phy_driver {
  	 */
  	int (*led_brightness_set)(struct phy_device *dev,
  				  u8 index, enum led_brightness value);
diff --git a/target/linux/generic/backport-6.1/815-v6.7-3-leds-turris-omnia-Support-HW-controlled-mode-via-pri.patch b/target/linux/generic/backport-6.1/815-v6.7-3-leds-turris-omnia-Support-HW-controlled-mode-via-pri.patch
index f64bbc7782772b..00773ab0f63293 100644
--- a/target/linux/generic/backport-6.1/815-v6.7-3-leds-turris-omnia-Support-HW-controlled-mode-via-pri.patch
+++ b/target/linux/generic/backport-6.1/815-v6.7-3-leds-turris-omnia-Support-HW-controlled-mode-via-pri.patch
@@ -49,7 +49,7 @@ Signed-off-by: Lee Jones <lee@kernel.org>
 
 --- a/drivers/leds/Kconfig
 +++ b/drivers/leds/Kconfig
-@@ -163,6 +163,7 @@ config LEDS_TURRIS_OMNIA
+@@ -164,6 +164,7 @@ config LEDS_TURRIS_OMNIA
  	depends on I2C
  	depends on MACH_ARMADA_38X || COMPILE_TEST
  	depends on OF
diff --git a/target/linux/generic/backport-6.1/820-v6.4-net-phy-fix-circular-LEDS_CLASS-dependencies.patch b/target/linux/generic/backport-6.1/820-v6.4-net-phy-fix-circular-LEDS_CLASS-dependencies.patch
index 1de086417b6112..3b68403690c679 100644
--- a/target/linux/generic/backport-6.1/820-v6.4-net-phy-fix-circular-LEDS_CLASS-dependencies.patch
+++ b/target/linux/generic/backport-6.1/820-v6.4-net-phy-fix-circular-LEDS_CLASS-dependencies.patch
@@ -53,7 +53,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	tristate "MDIO Bus/PHY emulation with fixed speed/link PHYs"
 --- a/drivers/net/phy/phy_device.c
 +++ b/drivers/net/phy/phy_device.c
-@@ -3210,7 +3210,8 @@ static int phy_probe(struct device *dev)
+@@ -3314,7 +3314,8 @@ static int phy_probe(struct device *dev)
  	/* Get the LEDs from the device tree, and instantiate standard
  	 * LEDs for them.
  	 */
diff --git a/target/linux/generic/backport-6.1/821-v6.4-net-phy-Fix-reading-LED-reg-property.patch b/target/linux/generic/backport-6.1/821-v6.4-net-phy-Fix-reading-LED-reg-property.patch
index d6081d0e637c3a..622bb9e94a9e31 100644
--- a/target/linux/generic/backport-6.1/821-v6.4-net-phy-Fix-reading-LED-reg-property.patch
+++ b/target/linux/generic/backport-6.1/821-v6.4-net-phy-Fix-reading-LED-reg-property.patch
@@ -18,7 +18,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/phy/phy_device.c
 +++ b/drivers/net/phy/phy_device.c
-@@ -2971,6 +2971,7 @@ static int of_phy_led(struct phy_device
+@@ -3075,6 +3075,7 @@ static int of_phy_led(struct phy_device
  	struct led_init_data init_data = {};
  	struct led_classdev *cdev;
  	struct phy_led *phyled;
@@ -26,7 +26,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	int err;
  
  	phyled = devm_kzalloc(dev, sizeof(*phyled), GFP_KERNEL);
-@@ -2980,10 +2981,13 @@ static int of_phy_led(struct phy_device
+@@ -3084,10 +3085,13 @@ static int of_phy_led(struct phy_device
  	cdev = &phyled->led_cdev;
  	phyled->phydev = phydev;
  
diff --git a/target/linux/generic/backport-6.1/822-v6.4-net-phy-Manual-remove-LEDs-to-ensure-correct-orderin.patch b/target/linux/generic/backport-6.1/822-v6.4-net-phy-Manual-remove-LEDs-to-ensure-correct-orderin.patch
index 8f076be640c9c4..80197e963b8483 100644
--- a/target/linux/generic/backport-6.1/822-v6.4-net-phy-Manual-remove-LEDs-to-ensure-correct-orderin.patch
+++ b/target/linux/generic/backport-6.1/822-v6.4-net-phy-Manual-remove-LEDs-to-ensure-correct-orderin.patch
@@ -22,7 +22,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/drivers/net/phy/phy_device.c
 +++ b/drivers/net/phy/phy_device.c
-@@ -2964,6 +2964,15 @@ static int phy_led_blink_set(struct led_
+@@ -3068,6 +3068,15 @@ static int phy_led_blink_set(struct led_
  	return err;
  }
  
@@ -38,7 +38,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  static int of_phy_led(struct phy_device *phydev,
  		      struct device_node *led)
  {
-@@ -2997,7 +3006,7 @@ static int of_phy_led(struct phy_device
+@@ -3101,7 +3110,7 @@ static int of_phy_led(struct phy_device
  	init_data.fwnode = of_fwnode_handle(led);
  	init_data.devname_mandatory = true;
  
@@ -47,7 +47,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	if (err)
  		return err;
  
-@@ -3026,6 +3035,7 @@ static int of_phy_leds(struct phy_device
+@@ -3130,6 +3139,7 @@ static int of_phy_leds(struct phy_device
  		err = of_phy_led(phydev, led);
  		if (err) {
  			of_node_put(led);
@@ -55,7 +55,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  			return err;
  		}
  	}
-@@ -3231,6 +3241,9 @@ static int phy_remove(struct device *dev
+@@ -3335,6 +3345,9 @@ static int phy_remove(struct device *dev
  
  	cancel_delayed_work_sync(&phydev->state_queue);
  
diff --git a/target/linux/generic/backport-6.1/826-v6.6-02-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch b/target/linux/generic/backport-6.1/826-v6.6-02-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch
index daa970884e62b7..505513a53fe31f 100644
--- a/target/linux/generic/backport-6.1/826-v6.6-02-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch
+++ b/target/linux/generic/backport-6.1/826-v6.6-02-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch
@@ -23,7 +23,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/phy/phy_device.c
 +++ b/drivers/net/phy/phy_device.c
-@@ -2964,6 +2964,61 @@ static int phy_led_blink_set(struct led_
+@@ -3068,6 +3068,61 @@ static int phy_led_blink_set(struct led_
  	return err;
  }
  
@@ -85,7 +85,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  static void phy_leds_unregister(struct phy_device *phydev)
  {
  	struct phy_led *phyled;
-@@ -3001,6 +3056,19 @@ static int of_phy_led(struct phy_device
+@@ -3105,6 +3160,19 @@ static int of_phy_led(struct phy_device
  		cdev->brightness_set_blocking = phy_led_set_brightness;
  	if (phydev->drv->led_blink_set)
  		cdev->blink_set = phy_led_blink_set;
@@ -107,7 +107,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	init_data.fwnode = of_fwnode_handle(led);
 --- a/include/linux/phy.h
 +++ b/include/linux/phy.h
-@@ -1022,6 +1022,39 @@ struct phy_driver {
+@@ -1026,6 +1026,39 @@ struct phy_driver {
  	int (*led_blink_set)(struct phy_device *dev, u8 index,
  			     unsigned long *delay_on,
  			     unsigned long *delay_off);
diff --git a/target/linux/generic/backport-6.1/827-v6.3-0002-of-property-make-.-cells-optional-for-simple-props.patch b/target/linux/generic/backport-6.1/827-v6.3-0002-of-property-make-.-cells-optional-for-simple-props.patch
index 3af514c42dfd5b..66c29126b6be8e 100644
--- a/target/linux/generic/backport-6.1/827-v6.3-0002-of-property-make-.-cells-optional-for-simple-props.patch
+++ b/target/linux/generic/backport-6.1/827-v6.3-0002-of-property-make-.-cells-optional-for-simple-props.patch
@@ -21,7 +21,7 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 
 --- a/drivers/of/property.c
 +++ b/drivers/of/property.c
-@@ -1144,8 +1144,8 @@ static struct device_node *parse_prop_ce
+@@ -1146,8 +1146,8 @@ static struct device_node *parse_prop_ce
  	if (strcmp(prop_name, list_name))
  		return NULL;
  
diff --git a/target/linux/generic/backport-6.1/827-v6.3-0003-of-property-add-nvmem-cell-cells-property.patch b/target/linux/generic/backport-6.1/827-v6.3-0003-of-property-add-nvmem-cell-cells-property.patch
index 025f094987a680..07354d7da7c003 100644
--- a/target/linux/generic/backport-6.1/827-v6.3-0003-of-property-add-nvmem-cell-cells-property.patch
+++ b/target/linux/generic/backport-6.1/827-v6.3-0003-of-property-add-nvmem-cell-cells-property.patch
@@ -19,7 +19,7 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 
 --- a/drivers/of/property.c
 +++ b/drivers/of/property.c
-@@ -1249,7 +1249,7 @@ DEFINE_SIMPLE_PROP(dmas, "dmas", "#dma-c
+@@ -1251,7 +1251,7 @@ DEFINE_SIMPLE_PROP(dmas, "dmas", "#dma-c
  DEFINE_SIMPLE_PROP(power_domains, "power-domains", "#power-domain-cells")
  DEFINE_SIMPLE_PROP(hwlocks, "hwlocks", "#hwlock-cells")
  DEFINE_SIMPLE_PROP(extcon, "extcon", NULL)
diff --git a/target/linux/generic/backport-6.1/828-v6.4-0003-of-Rename-of_modalias_node.patch b/target/linux/generic/backport-6.1/828-v6.4-0003-of-Rename-of_modalias_node.patch
index 15af039a16f01d..671556fbaa8228 100644
--- a/target/linux/generic/backport-6.1/828-v6.4-0003-of-Rename-of_modalias_node.patch
+++ b/target/linux/generic/backport-6.1/828-v6.4-0003-of-Rename-of_modalias_node.patch
@@ -148,7 +148,7 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
   * of_find_node_by_phandle - Find a node given a phandle
 --- a/drivers/spi/spi.c
 +++ b/drivers/spi/spi.c
-@@ -2326,8 +2326,8 @@ of_register_spi_device(struct spi_contro
+@@ -2330,8 +2330,8 @@ of_register_spi_device(struct spi_contro
  	}
  
  	/* Select device driver */
diff --git a/target/linux/generic/backport-6.1/835-v6.9-net-phy-add-support-for-PHY-LEDs-polarity-modes.patch b/target/linux/generic/backport-6.1/835-v6.9-net-phy-add-support-for-PHY-LEDs-polarity-modes.patch
index 604b3db270214a..0182e6d1a203b0 100644
--- a/target/linux/generic/backport-6.1/835-v6.9-net-phy-add-support-for-PHY-LEDs-polarity-modes.patch
+++ b/target/linux/generic/backport-6.1/835-v6.9-net-phy-add-support-for-PHY-LEDs-polarity-modes.patch
@@ -28,7 +28,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/phy/phy_device.c
 +++ b/drivers/net/phy/phy_device.c
-@@ -3034,6 +3034,7 @@ static int of_phy_led(struct phy_device
+@@ -3138,6 +3138,7 @@ static int of_phy_led(struct phy_device
  	struct device *dev = &phydev->mdio.dev;
  	struct led_init_data init_data = {};
  	struct led_classdev *cdev;
@@ -36,7 +36,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	struct phy_led *phyled;
  	u32 index;
  	int err;
-@@ -3051,6 +3052,21 @@ static int of_phy_led(struct phy_device
+@@ -3155,6 +3156,21 @@ static int of_phy_led(struct phy_device
  	if (index > U8_MAX)
  		return -EINVAL;
  
@@ -60,7 +60,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		cdev->brightness_set_blocking = phy_led_set_brightness;
 --- a/include/linux/phy.h
 +++ b/include/linux/phy.h
-@@ -787,6 +787,15 @@ struct phy_led {
+@@ -791,6 +791,15 @@ struct phy_led {
  
  #define to_phy_led(d) container_of(d, struct phy_led, led_cdev)
  
@@ -76,7 +76,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  /**
   * struct phy_driver - Driver structure for a particular PHY type
   *
-@@ -1055,6 +1064,19 @@ struct phy_driver {
+@@ -1059,6 +1068,19 @@ struct phy_driver {
  	int (*led_hw_control_get)(struct phy_device *dev, u8 index,
  				  unsigned long *rules);
  
diff --git a/target/linux/generic/backport-6.1/836-v6.7-leds-trigger-netdev-fix-RTNL-handling-to-prevent-pot.patch b/target/linux/generic/backport-6.1/836-v6.7-leds-trigger-netdev-fix-RTNL-handling-to-prevent-pot.patch
new file mode 100644
index 00000000000000..cbb9172032326c
--- /dev/null
+++ b/target/linux/generic/backport-6.1/836-v6.7-leds-trigger-netdev-fix-RTNL-handling-to-prevent-pot.patch
@@ -0,0 +1,170 @@
+From fe2b1226656afae56702d1d84c6900f6b67df297 Mon Sep 17 00:00:00 2001
+From: Heiner Kallweit <hkallweit1@gmail.com>
+Date: Fri, 1 Dec 2023 11:23:22 +0100
+Subject: [PATCH] leds: trigger: netdev: fix RTNL handling to prevent potential
+ deadlock
+
+When working on LED support for r8169 I got the following lockdep
+warning. Easiest way to prevent this scenario seems to be to take
+the RTNL lock before the trigger_data lock in set_device_name().
+
+======================================================
+WARNING: possible circular locking dependency detected
+6.7.0-rc2-next-20231124+ #2 Not tainted
+------------------------------------------------------
+bash/383 is trying to acquire lock:
+ffff888103aa1c68 (&trigger_data->lock){+.+.}-{3:3}, at: netdev_trig_notify+0xec/0x190 [ledtrig_netdev]
+
+but task is already holding lock:
+ffffffff8cddf808 (rtnl_mutex){+.+.}-{3:3}, at: rtnl_lock+0x12/0x20
+
+which lock already depends on the new lock.
+
+the existing dependency chain (in reverse order) is:
+
+-> #1 (rtnl_mutex){+.+.}-{3:3}:
+       __mutex_lock+0x9b/0xb50
+       mutex_lock_nested+0x16/0x20
+       rtnl_lock+0x12/0x20
+       set_device_name+0xa9/0x120 [ledtrig_netdev]
+       netdev_trig_activate+0x1a1/0x230 [ledtrig_netdev]
+       led_trigger_set+0x172/0x2c0
+       led_trigger_write+0xf1/0x140
+       sysfs_kf_bin_write+0x5d/0x80
+       kernfs_fop_write_iter+0x15d/0x210
+       vfs_write+0x1f0/0x510
+       ksys_write+0x6c/0xf0
+       __x64_sys_write+0x14/0x20
+       do_syscall_64+0x3f/0xf0
+       entry_SYSCALL_64_after_hwframe+0x6c/0x74
+
+-> #0 (&trigger_data->lock){+.+.}-{3:3}:
+       __lock_acquire+0x1459/0x25a0
+       lock_acquire+0xc8/0x2d0
+       __mutex_lock+0x9b/0xb50
+       mutex_lock_nested+0x16/0x20
+       netdev_trig_notify+0xec/0x190 [ledtrig_netdev]
+       call_netdevice_register_net_notifiers+0x5a/0x100
+       register_netdevice_notifier+0x85/0x120
+       netdev_trig_activate+0x1d4/0x230 [ledtrig_netdev]
+       led_trigger_set+0x172/0x2c0
+       led_trigger_write+0xf1/0x140
+       sysfs_kf_bin_write+0x5d/0x80
+       kernfs_fop_write_iter+0x15d/0x210
+       vfs_write+0x1f0/0x510
+       ksys_write+0x6c/0xf0
+       __x64_sys_write+0x14/0x20
+       do_syscall_64+0x3f/0xf0
+       entry_SYSCALL_64_after_hwframe+0x6c/0x74
+
+other info that might help us debug this:
+
+ Possible unsafe locking scenario:
+
+       CPU0                    CPU1
+       ----                    ----
+  lock(rtnl_mutex);
+                               lock(&trigger_data->lock);
+                               lock(rtnl_mutex);
+  lock(&trigger_data->lock);
+
+ *** DEADLOCK ***
+
+8 locks held by bash/383:
+ #0: ffff888103ff33f0 (sb_writers#3){.+.+}-{0:0}, at: ksys_write+0x6c/0xf0
+ #1: ffff888103aa1e88 (&of->mutex){+.+.}-{3:3}, at: kernfs_fop_write_iter+0x114/0x210
+ #2: ffff8881036f1890 (kn->active#82){.+.+}-{0:0}, at: kernfs_fop_write_iter+0x11d/0x210
+ #3: ffff888108e2c358 (&led_cdev->led_access){+.+.}-{3:3}, at: led_trigger_write+0x30/0x140
+ #4: ffffffff8cdd9e10 (triggers_list_lock){++++}-{3:3}, at: led_trigger_write+0x75/0x140
+ #5: ffff888108e2c270 (&led_cdev->trigger_lock){++++}-{3:3}, at: led_trigger_write+0xe3/0x140
+ #6: ffffffff8cdde3d0 (pernet_ops_rwsem){++++}-{3:3}, at: register_netdevice_notifier+0x1c/0x120
+ #7: ffffffff8cddf808 (rtnl_mutex){+.+.}-{3:3}, at: rtnl_lock+0x12/0x20
+
+stack backtrace:
+CPU: 0 PID: 383 Comm: bash Not tainted 6.7.0-rc2-next-20231124+ #2
+Hardware name: Default string Default string/Default string, BIOS ADLN.M6.SODIMM.ZB.CY.015 08/08/2023
+Call Trace:
+ <TASK>
+ dump_stack_lvl+0x5c/0xd0
+ dump_stack+0x10/0x20
+ print_circular_bug+0x2dd/0x410
+ check_noncircular+0x131/0x150
+ __lock_acquire+0x1459/0x25a0
+ lock_acquire+0xc8/0x2d0
+ ? netdev_trig_notify+0xec/0x190 [ledtrig_netdev]
+ __mutex_lock+0x9b/0xb50
+ ? netdev_trig_notify+0xec/0x190 [ledtrig_netdev]
+ ? __this_cpu_preempt_check+0x13/0x20
+ ? netdev_trig_notify+0xec/0x190 [ledtrig_netdev]
+ ? __cancel_work_timer+0x11c/0x1b0
+ ? __mutex_lock+0x123/0xb50
+ mutex_lock_nested+0x16/0x20
+ ? mutex_lock_nested+0x16/0x20
+ netdev_trig_notify+0xec/0x190 [ledtrig_netdev]
+ call_netdevice_register_net_notifiers+0x5a/0x100
+ register_netdevice_notifier+0x85/0x120
+ netdev_trig_activate+0x1d4/0x230 [ledtrig_netdev]
+ led_trigger_set+0x172/0x2c0
+ ? preempt_count_add+0x49/0xc0
+ led_trigger_write+0xf1/0x140
+ sysfs_kf_bin_write+0x5d/0x80
+ kernfs_fop_write_iter+0x15d/0x210
+ vfs_write+0x1f0/0x510
+ ksys_write+0x6c/0xf0
+ __x64_sys_write+0x14/0x20
+ do_syscall_64+0x3f/0xf0
+ entry_SYSCALL_64_after_hwframe+0x6c/0x74
+RIP: 0033:0x7f269055d034
+Code: c7 00 16 00 00 00 b8 ff ff ff ff c3 66 2e 0f 1f 84 00 00 00 00 00 f3 0f 1e fa 80 3d 35 c3 0d 00 00 74 13 b8 01 00 00 00 0f 05 <48> 3d 00 f0 ff ff 77 54 c3 0f 1f 00 48 83 ec 28 48 89 54 24 18 48
+RSP: 002b:00007ffddb7ef748 EFLAGS: 00000202 ORIG_RAX: 0000000000000001
+RAX: ffffffffffffffda RBX: 0000000000000007 RCX: 00007f269055d034
+RDX: 0000000000000007 RSI: 000055bf5f4af3c0 RDI: 0000000000000001
+RBP: 000055bf5f4af3c0 R08: 0000000000000073 R09: 0000000000000001
+R10: 0000000000000000 R11: 0000000000000202 R12: 0000000000000007
+R13: 00007f26906325c0 R14: 00007f269062ff20 R15: 0000000000000000
+ </TASK>
+
+Fixes: d5e01266e7f5 ("leds: trigger: netdev: add additional specific link speed mode")
+Cc: stable@vger.kernel.org
+Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Acked-by: Lee Jones <lee@kernel.org>
+Link: https://lore.kernel.org/r/fb5c8294-2a10-4bf5-8f10-3d2b77d2757e@gmail.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/leds/trigger/ledtrig-netdev.c | 11 +++++++----
+ 1 file changed, 7 insertions(+), 4 deletions(-)
+
+--- a/drivers/leds/trigger/ledtrig-netdev.c
++++ b/drivers/leds/trigger/ledtrig-netdev.c
+@@ -235,6 +235,11 @@ static int set_device_name(struct led_ne
+ {
+ 	cancel_delayed_work_sync(&trigger_data->work);
+ 
++	/*
++	 * Take RTNL lock before trigger_data lock to prevent potential
++	 * deadlock with netdev notifier registration.
++	 */
++	rtnl_lock();
+ 	mutex_lock(&trigger_data->lock);
+ 
+ 	if (trigger_data->net_dev) {
+@@ -254,16 +259,14 @@ static int set_device_name(struct led_ne
+ 	trigger_data->carrier_link_up = false;
+ 	trigger_data->link_speed = SPEED_UNKNOWN;
+ 	trigger_data->duplex = DUPLEX_UNKNOWN;
+-	if (trigger_data->net_dev != NULL) {
+-		rtnl_lock();
++	if (trigger_data->net_dev)
+ 		get_device_state(trigger_data);
+-		rtnl_unlock();
+-	}
+ 
+ 	trigger_data->last_activity = 0;
+ 
+ 	set_baseline_state(trigger_data);
+ 	mutex_unlock(&trigger_data->lock);
++	rtnl_unlock();
+ 
+ 	return 0;
+ }
diff --git a/target/linux/generic/backport-6.1/837-v6.4-net-phy-hide-the-PHYLIB_LEDS-knob.patch b/target/linux/generic/backport-6.1/837-v6.4-net-phy-hide-the-PHYLIB_LEDS-knob.patch
new file mode 100644
index 00000000000000..51b4bbbfcb1402
--- /dev/null
+++ b/target/linux/generic/backport-6.1/837-v6.4-net-phy-hide-the-PHYLIB_LEDS-knob.patch
@@ -0,0 +1,43 @@
+From 9b78d919632b7149d311aaad5a977e4b48b10321 Mon Sep 17 00:00:00 2001
+From: Paolo Abeni <pabeni@redhat.com>
+Date: Wed, 26 Apr 2023 10:15:31 +0200
+Subject: [PATCH] net: phy: hide the PHYLIB_LEDS knob
+
+commit 4bb7aac70b5d ("net: phy: fix circular LEDS_CLASS dependencies")
+solved a build failure, but introduces a new config knob with a default
+'y' value: PHYLIB_LEDS.
+
+The latter is against the current new config policy. The exception
+was raised to allow the user to catch bad configurations without led
+support.
+
+Anyway the current definition of PHYLIB_LEDS does not fit the above
+goal: if LEDS_CLASS is disabled, the new config will be available
+only with PHYLIB disabled, too.
+
+Hide the mentioned config, to preserve the randconfig testing done so
+far, while respecting the mentioned policy.
+
+Suggested-by: Andrew Lunn <andrew@lunn.ch>
+Suggested-by: Arnd Bergmann <arnd@arndb.de>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+Link: https://lore.kernel.org/r/d82489be8ed911c383c3447e9abf469995ccf39a.1682496488.git.pabeni@redhat.com
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/phy/Kconfig | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+--- a/drivers/net/phy/Kconfig
++++ b/drivers/net/phy/Kconfig
+@@ -45,10 +45,8 @@ config LED_TRIGGER_PHY
+ 		for any speed known to the PHY.
+ 
+ config PHYLIB_LEDS
+-	bool "Support probing LEDs from device tree"
++	def_bool OF
+ 	depends on LEDS_CLASS=y || LEDS_CLASS=PHYLIB
+-	depends on OF
+-	default y
+ 	help
+ 	  When LED class support is enabled, phylib can automatically
+ 	  probe LED setting from device tree.
diff --git a/target/linux/generic/backport-6.1/838-v6.9-leds-trigger-netdev-Fix-kernel-panic-on-interface-re.patch b/target/linux/generic/backport-6.1/838-v6.9-leds-trigger-netdev-Fix-kernel-panic-on-interface-re.patch
new file mode 100644
index 00000000000000..8d391678ffb7c8
--- /dev/null
+++ b/target/linux/generic/backport-6.1/838-v6.9-leds-trigger-netdev-Fix-kernel-panic-on-interface-re.patch
@@ -0,0 +1,55 @@
+From 12ce20e02e532f101b725d71c52a36c5cc8ad1e6 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Sun, 4 Feb 2024 00:54:01 +0100
+Subject: [PATCH] leds: trigger: netdev: Fix kernel panic on interface rename
+ trig notify
+
+Commit d5e01266e7f5 ("leds: trigger: netdev: add additional specific link
+speed mode") in the various changes, reworked the way to set the LINKUP
+mode in commit cee4bd16c319 ("leds: trigger: netdev: Recheck
+NETDEV_LED_MODE_LINKUP on dev rename") and moved it to a generic function.
+
+This changed the logic where, in the previous implementation the dev
+from the trigger event was used to check if the carrier was ok, but in
+the new implementation with the generic function, the dev in
+trigger_data is used instead.
+
+This is problematic and cause a possible kernel panic due to the fact
+that the dev in the trigger_data still reference the old one as the
+new one (passed from the trigger event) still has to be hold and saved
+in the trigger_data struct (done in the NETDEV_REGISTER case).
+
+On calling of get_device_state(), an invalid net_dev is used and this
+cause a kernel panic.
+
+To handle this correctly, move the call to get_device_state() after the
+new net_dev is correctly set in trigger_data (in the NETDEV_REGISTER
+case) and correctly parse the new dev.
+
+Fixes: d5e01266e7f5 ("leds: trigger: netdev: add additional specific link speed mode")
+Cc: stable@vger.kernel.org
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://lore.kernel.org/r/20240203235413.1146-1-ansuelsmth@gmail.com
+Signed-off-by: Lee Jones <lee@kernel.org>
+---
+ drivers/leds/trigger/ledtrig-netdev.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/leds/trigger/ledtrig-netdev.c
++++ b/drivers/leds/trigger/ledtrig-netdev.c
+@@ -489,12 +489,12 @@ static int netdev_trig_notify(struct not
+ 	trigger_data->duplex = DUPLEX_UNKNOWN;
+ 	switch (evt) {
+ 	case NETDEV_CHANGENAME:
+-		get_device_state(trigger_data);
+-		fallthrough;
+ 	case NETDEV_REGISTER:
+ 		dev_put(trigger_data->net_dev);
+ 		dev_hold(dev);
+ 		trigger_data->net_dev = dev;
++		if (evt == NETDEV_CHANGENAME)
++			get_device_state(trigger_data);
+ 		break;
+ 	case NETDEV_UNREGISTER:
+ 		dev_put(trigger_data->net_dev);
diff --git a/target/linux/generic/config-5.15 b/target/linux/generic/config-5.15
index bc2509ff47865a..5f82f0937d48e7 100644
--- a/target/linux/generic/config-5.15
+++ b/target/linux/generic/config-5.15
@@ -2071,7 +2071,6 @@ CONFIG_FILE_LOCKING=y
 # CONFIG_FIRMWARE_EDID is not set
 # CONFIG_FIRMWARE_IN_KERNEL is not set
 # CONFIG_FIRMWARE_MEMMAP is not set
-# CONFIG_FIT_PARTITION is not set
 # CONFIG_FIXED_PHY is not set
 CONFIG_FLATMEM=y
 CONFIG_FLATMEM_MANUAL=y
diff --git a/target/linux/generic/config-6.1 b/target/linux/generic/config-6.1
index c6301662f70be9..b4aeeb9a7089c5 100644
--- a/target/linux/generic/config-6.1
+++ b/target/linux/generic/config-6.1
@@ -155,6 +155,7 @@ CONFIG_AF_UNIX_OOB=y
 # CONFIG_AHCI_QORIQ is not set
 # CONFIG_AHCI_XGENE is not set
 CONFIG_AIO=y
+# CONFIG_AIR_EN8811H_PHY is not set
 # CONFIG_AIRO is not set
 # CONFIG_AIRO_CS is not set
 # CONFIG_AIX_PARTITION is not set
@@ -730,6 +731,7 @@ CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
 # CONFIG_BLK_DEV_VIA82CXXX is not set
 # CONFIG_BLK_DEV_ZONED is not set
 # CONFIG_BLK_INLINE_ENCRYPTION is not set
+# CONFIG_BLK_NVMEM is not set
 # CONFIG_BLK_SED_OPAL is not set
 # CONFIG_BLK_WBT is not set
 CONFIG_BLOCK=y
@@ -1756,6 +1758,7 @@ CONFIG_DQL=y
 # CONFIG_DRM_TOSHIBA_TC358775 is not set
 # CONFIG_DRM_TVE200 is not set
 # CONFIG_DRM_UDL is not set
+# CONFIG_DRM_V3D is not set
 # CONFIG_DRM_VBOXVIDEO is not set
 # CONFIG_DRM_VC4_HDMI_CEC is not set
 # CONFIG_DRM_VGEM is not set
@@ -2166,7 +2169,6 @@ CONFIG_FILE_LOCKING=y
 # CONFIG_FIRMWARE_EDID is not set
 # CONFIG_FIRMWARE_IN_KERNEL is not set
 # CONFIG_FIRMWARE_MEMMAP is not set
-# CONFIG_FIT_PARTITION is not set
 # CONFIG_FIXED_PHY is not set
 CONFIG_FLATMEM=y
 CONFIG_FLATMEM_MANUAL=y
@@ -4037,6 +4039,7 @@ CONFIG_MTD_SPLIT_SUPPORT=y
 # CONFIG_MTD_UBI is not set
 # CONFIG_MTD_UBI_FASTMAP is not set
 # CONFIG_MTD_UBI_GLUEBI is not set
+# CONFIG_MTD_UBI_NVMEM is not set
 # CONFIG_MTD_UIMAGE_SPLIT is not set
 # CONFIG_MTD_VIRT_CONCAT is not set
 # CONFIG_MTK_DEVAPC is not set
@@ -4836,6 +4839,7 @@ CONFIG_PCI_SYSCALL=y
 # CONFIG_PCNET32 is not set
 # CONFIG_PCPU_DEV_REFCNT is not set
 # CONFIG_PCSPKR_PLATFORM is not set
+# CONFIG_PCS_MTK_USXGMII is not set
 # CONFIG_PCS_XPCS is not set
 # CONFIG_PD6729 is not set
 # CONFIG_PDA_POWER is not set
@@ -4870,6 +4874,7 @@ CONFIG_PCI_SYSCALL=y
 # CONFIG_PHY_MIXEL_MIPI_DPHY is not set
 # CONFIG_PHY_MTK_HDMI is not set
 # CONFIG_PHY_MTK_MIPI_DSI is not set
+# CONFIG_PHY_MTK_XFI_TPHY is not set
 # CONFIG_PHY_MVEBU_CP110_UTMI is not set
 # CONFIG_PHY_OCELOT_SERDES is not set
 # CONFIG_PHY_PISTACHIO_USB is not set
@@ -5076,6 +5081,9 @@ CONFIG_PWRSEQ_SIMPLE=y
 # CONFIG_QCA7000 is not set
 # CONFIG_QCA7000_SPI is not set
 # CONFIG_QCA7000_UART is not set
+# CONFIG_QCA83XX_PHY is not set
+# CONFIG_QCA807X_PHY is not set
+# CONFIG_QCA808X_PHY is not set
 # CONFIG_QCOM_A7PLL is not set
 # CONFIG_QCOM_BAM_DMUX is not set
 # CONFIG_QCOM_EMAC is not set
@@ -6039,6 +6047,7 @@ CONFIG_SLUB_CPU_PARTIAL=y
 # CONFIG_SND_AZT2320 is not set
 # CONFIG_SND_AZT3328 is not set
 # CONFIG_SND_BCD2000 is not set
+# CONFIG_SND_BCM2835 is not set
 # CONFIG_SND_BCM63XX_I2S_WHISTLER is not set
 # CONFIG_SND_BT87X is not set
 # CONFIG_SND_CA0106 is not set
@@ -7067,6 +7076,7 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 # CONFIG_UHID is not set
 CONFIG_UID16=y
 # CONFIG_UIO is not set
+# CONFIG_UIMAGE_FIT_BLK is not set
 # CONFIG_ULTRA is not set
 # CONFIG_ULTRIX_PARTITION is not set
 # CONFIG_UNICODE is not set
@@ -7522,10 +7532,14 @@ CONFIG_VHOST_MENU=y
 # CONFIG_VIDEO_AK881X is not set
 # CONFIG_VIDEO_AM437X_VPFE is not set
 # CONFIG_VIDEO_AR0521 is not set
+# CONFIG_VIDEO_ARDUCAM_64MP is not set
+# CONFIG_VIDEO_ARDUCAM_PIVARIETY is not set
 # CONFIG_VIDEO_ASPEED is not set
 # CONFIG_VIDEO_ATMEL_ISC is not set
 # CONFIG_VIDEO_ATMEL_ISI is not set
 # CONFIG_VIDEO_AU0828 is not set
+# CONFIG_VIDEO_BCM2835 is not set
+# CONFIG_VIDEO_BCM2835_UNICAM is not set
 # CONFIG_VIDEO_BT819 is not set
 # CONFIG_VIDEO_BT848 is not set
 # CONFIG_VIDEO_BT856 is not set
@@ -7539,6 +7553,7 @@ CONFIG_VHOST_MENU=y
 # CONFIG_VIDEO_CCS is not set
 # CONFIG_VIDEO_COBALT is not set
 # CONFIG_VIDEO_CODA is not set
+# CONFIG_VIDEO_CODEC_BCM2835 is not set
 # CONFIG_VIDEO_CS3308 is not set
 # CONFIG_VIDEO_CS5345 is not set
 # CONFIG_VIDEO_CS53L32A is not set
@@ -7571,17 +7586,22 @@ CONFIG_VHOST_MENU=y
 # CONFIG_VIDEO_IMX258 is not set
 # CONFIG_VIDEO_IMX274 is not set
 # CONFIG_VIDEO_IMX290 is not set
+# CONFIG_VIDEO_IMX296 is not set
 # CONFIG_VIDEO_IMX319 is not set
 # CONFIG_VIDEO_IMX334 is not set
 # CONFIG_VIDEO_IMX335 is not set
 # CONFIG_VIDEO_IMX355 is not set
 # CONFIG_VIDEO_IMX412 is not set
 # CONFIG_VIDEO_IMX477 is not set
+# CONFIG_VIDEO_IMX519 is not set
+# CONFIG_VIDEO_IMX708 is not set
 # CONFIG_VIDEO_IMX8_JPEG is not set
+# CONFIG_VIDEO_IMX_MIPI_CSIS is not set
 # CONFIG_VIDEO_IMX_PXP is not set
 # CONFIG_VIDEO_IRS1125 is not set
 # CONFIG_VIDEO_IR_I2C is not set
 # CONFIG_VIDEO_ISL7998X is not set
+# CONFIG_VIDEO_ISP_BCM2835 is not set
 # CONFIG_VIDEO_IVTV is not set
 # CONFIG_VIDEO_KS0127 is not set
 # CONFIG_VIDEO_LM3560 is not set
@@ -7639,9 +7659,15 @@ CONFIG_VHOST_MENU=y
 # CONFIG_VIDEO_OV9650 is not set
 # CONFIG_VIDEO_OV9734 is not set
 # CONFIG_VIDEO_PVRUSB2 is not set
+# CONFIG_VIDEO_RASPBERRYPI_PISP_BE is not set
+# CONFIG_VIDEO_RCAR_CSI2 is not set
+# CONFIG_VIDEO_RCAR_ISP is not set
+# CONFIG_VIDEO_RCAR_VIN is not set
 # CONFIG_VIDEO_RDACM20 is not set
 # CONFIG_VIDEO_RDACM21 is not set
 # CONFIG_VIDEO_RJ54N1 is not set
+# CONFIG_VIDEO_ROCKCHIP_ISP1 is not set
+# CONFIG_VIDEO_RP1_CFE is not set
 # CONFIG_VIDEO_S5C73M3 is not set
 # CONFIG_VIDEO_S5K4ECGX is not set
 # CONFIG_VIDEO_S5K5BAF is not set
@@ -7660,6 +7686,9 @@ CONFIG_VHOST_MENU=y
 # CONFIG_VIDEO_SMIAPP is not set
 # CONFIG_VIDEO_SOLO6X10 is not set
 # CONFIG_VIDEO_SONY_BTF_MPX is not set
+# CONFIG_VIDEO_SUN4I_CSI is not set
+# CONFIG_VIDEO_SUN6I_CSI is not set
+# CONFIG_VIDEO_SUN8I_A83T_MIPI_CSI2 is not set
 # CONFIG_VIDEO_SR030PC30 is not set
 # CONFIG_VIDEO_STK1160_COMMON is not set
 # CONFIG_VIDEO_ST_MIPID02 is not set
diff --git a/target/linux/generic/files/drivers/net/phy/rtl8366_smi.c b/target/linux/generic/files/drivers/net/phy/rtl8366_smi.c
index 028b9916e78eb8..a26fd204cb25db 100644
--- a/target/linux/generic/files/drivers/net/phy/rtl8366_smi.c
+++ b/target/linux/generic/files/drivers/net/phy/rtl8366_smi.c
@@ -256,7 +256,7 @@ static int __rtl8366_smi_read_reg(struct rtl8366_smi *smi, u32 addr, u32 *data)
 
 int __rtl8366_mdio_read_reg(struct rtl8366_smi *smi, u32 addr, u32 *data)
 {
-	u32 phy_id = MDC_REALTEK_PHY_ADDR;
+	u32 phy_id = smi->phy_id;
 	struct mii_bus *mbus = smi->ext_mbus;
 
 	BUG_ON(in_interrupt());
@@ -293,7 +293,7 @@ int __rtl8366_mdio_read_reg(struct rtl8366_smi *smi, u32 addr, u32 *data)
 
 static int __rtl8366_mdio_write_reg(struct rtl8366_smi *smi, u32 addr, u32 data)
 {
-	u32 phy_id = MDC_REALTEK_PHY_ADDR;
+	u32 phy_id = smi->phy_id;
 	struct mii_bus *mbus = smi->ext_mbus;
 
 	BUG_ON(in_interrupt());
@@ -1547,6 +1547,9 @@ int rtl8366_smi_probe_of(struct platform_device *pdev, struct rtl8366_smi *smi)
 		goto try_gpio;
 	}
 
+	if (of_property_read_u32(np, "phy-id", &smi->phy_id))
+		smi->phy_id = MDC_REALTEK_PHY_ADDR;
+
 	return 0;
 
 try_gpio:
@@ -1586,6 +1589,7 @@ int rtl8366_smi_probe_plat(struct platform_device *pdev, struct rtl8366_smi *smi
 	smi->gpio_sda = pdata->gpio_sda;
 	smi->gpio_sck = pdata->gpio_sck;
 	smi->hw_reset = pdata->hw_reset;
+	smi->phy_id = MDC_REALTEK_PHY_ADDR;
 
 	return 0;
 }
diff --git a/target/linux/generic/files/drivers/net/phy/rtl8366_smi.h b/target/linux/generic/files/drivers/net/phy/rtl8366_smi.h
index fabc9402780d60..3fcae81fa45d61 100644
--- a/target/linux/generic/files/drivers/net/phy/rtl8366_smi.h
+++ b/target/linux/generic/files/drivers/net/phy/rtl8366_smi.h
@@ -63,6 +63,7 @@ struct rtl8366_smi {
 	u16			dbg_reg;
 	u8			dbg_vlan_4k_page;
 #endif
+	u32			phy_id;
 	struct mii_bus		*ext_mbus;
 };
 
diff --git a/target/linux/generic/files/drivers/net/phy/rtl8367b.c b/target/linux/generic/files/drivers/net/phy/rtl8367b.c
index 3599791a517bbf..cd0d58cbfa33c7 100644
--- a/target/linux/generic/files/drivers/net/phy/rtl8367b.c
+++ b/target/linux/generic/files/drivers/net/phy/rtl8367b.c
@@ -605,6 +605,20 @@ static const struct rtl8367b_initval rtl8367r_vb_initvals_1[] = {
 	{0x133E, 0x000E}, {0x133F, 0x0010},
 };
 
+static const struct rtl8367b_initval rtl8367c_initvals[] = {
+	{0x13c2, 0x0000}, {0x0018, 0x0f00}, {0x0038, 0x0f00}, {0x0058, 0x0f00},
+	{0x0078, 0x0f00}, {0x0098, 0x0f00}, {0x1d15, 0x0a69}, {0x2000, 0x1340},
+	{0x2020, 0x1340}, {0x2040, 0x1340}, {0x2060, 0x1340}, {0x2080, 0x1340},
+	{0x13eb, 0x15bb}, {0x1303, 0x06d6}, {0x1304, 0x0700}, {0x13E2, 0x003F},
+	{0x13F9, 0x0090}, {0x121e, 0x03CA}, {0x1233, 0x0352}, {0x1237, 0x00a0},
+	{0x123a, 0x0030}, {0x1239, 0x0084}, {0x0301, 0x1000}, {0x1349, 0x001F},
+	{0x18e0, 0x4004}, {0x122b, 0x641c}, {0x1305, 0xc000}, {0x1200, 0x7fcb},
+	{0x0884, 0x0003}, {0x06eb, 0x0001}, {0x00cf, 0xffff}, {0x00d0, 0x0007},
+	{0x00ce, 0x48b0}, {0x00ce, 0x48b0}, {0x0398, 0xffff}, {0x0399, 0x0007},
+	{0x0300, 0x0001}, {0x03fa, 0x0007}, {0x08c8, 0x00c0}, {0x0a30, 0x020e},
+	{0x0800, 0x0000}, {0x0802, 0x0000}, {0x09da, 0x0017}, {0x1d32, 0x0002},
+};
+
 static int rtl8367b_write_initvals(struct rtl8366_smi *smi,
 				  const struct rtl8367b_initval *initvals,
 				  int count)
@@ -716,31 +730,35 @@ static int rtl8367b_write_phy_reg(struct rtl8366_smi *smi,
 static int rtl8367b_init_regs(struct rtl8366_smi *smi)
 {
 	const struct rtl8367b_initval *initvals;
+	u32 chip_num;
 	u32 chip_ver;
 	u32 rlvid;
 	int count;
 	int err;
 
 	REG_WR(smi, RTL8367B_RTL_MAGIC_ID_REG, RTL8367B_RTL_MAGIC_ID_VAL);
+	REG_RD(smi, RTL8367B_CHIP_NUMBER_REG, &chip_num);
 	REG_RD(smi, RTL8367B_CHIP_VER_REG, &chip_ver);
 
-	rlvid = (chip_ver >> RTL8367B_CHIP_VER_RLVID_SHIFT) &
-		RTL8367B_CHIP_VER_RLVID_MASK;
-
-	switch (rlvid) {
-	case 0:
-		initvals = rtl8367r_vb_initvals_0;
-		count = ARRAY_SIZE(rtl8367r_vb_initvals_0);
-		break;
-
-	case 1:
-		initvals = rtl8367r_vb_initvals_1;
-		count = ARRAY_SIZE(rtl8367r_vb_initvals_1);
-		break;
-
-	default:
-		dev_err(smi->parent, "unknow rlvid %u\n", rlvid);
-		return -ENODEV;
+	if ((chip_ver ==  0x0020 || chip_ver == 0x00A0) && chip_num == 0x6367)  {
+		initvals = rtl8367c_initvals;
+		count = ARRAY_SIZE(rtl8367c_initvals);
+	} else {
+		rlvid = (chip_ver >> RTL8367B_CHIP_VER_RLVID_SHIFT) &
+			RTL8367B_CHIP_VER_RLVID_MASK;
+		switch (rlvid) {
+		case 0:
+			initvals = rtl8367r_vb_initvals_0;
+			count = ARRAY_SIZE(rtl8367r_vb_initvals_0);
+			break;
+		case 1:
+			initvals = rtl8367r_vb_initvals_1;
+			count = ARRAY_SIZE(rtl8367r_vb_initvals_1);
+			break;
+		default:
+			dev_err(smi->parent, "unknow rlvid %u\n", rlvid);
+			return -ENODEV;
+		}
 	}
 
 	/* TODO: disable RLTP */
@@ -1509,7 +1527,7 @@ static int rtl8367b_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
 
 static int rtl8367b_detect(struct rtl8366_smi *smi)
 {
-	const char *chip_name;
+	const char *chip_name = NULL;
 	u32 chip_num;
 	u32 chip_ver;
 	u32 chip_mode;
@@ -1541,13 +1559,22 @@ static int rtl8367b_detect(struct rtl8366_smi *smi)
 	}
 
 	switch (chip_ver) {
+	case 0x0020:
+		if (chip_num == 0x6367)
+			chip_name = "8367RB-VB";
+		break;
+	case 0x00A0:
+		if (chip_num == 0x6367)
+			chip_name = "8367S";
+		break;
 	case 0x1000:
 		chip_name = "8367RB";
 		break;
 	case 0x1010:
 		chip_name = "8367R-VB";
-		break;
-	default:
+	}
+
+	if (!chip_name) {
 		dev_err(smi->parent,
 			"unknown chip num:%04x ver:%04x, mode:%04x\n",
 			chip_num, chip_ver, chip_mode);
diff --git a/target/linux/generic/hack-5.15/251-kconfig.patch b/target/linux/generic/hack-5.15/251-kconfig.patch
index 9350e366d8668c..00c23db955e83c 100644
--- a/target/linux/generic/hack-5.15/251-kconfig.patch
+++ b/target/linux/generic/hack-5.15/251-kconfig.patch
@@ -124,59 +124,6 @@ Signed-off-by: John Crispin <john@phrozen.org>
  
  config NETFILTER_FAMILY_BRIDGE
  	bool
---- a/net/wireless/Kconfig
-+++ b/net/wireless/Kconfig
-@@ -1,6 +1,6 @@
- # SPDX-License-Identifier: GPL-2.0-only
- config WIRELESS_EXT
--	bool
-+	bool "Wireless extensions"
- 
- config WEXT_CORE
- 	def_bool y
-@@ -12,10 +12,10 @@ config WEXT_PROC
- 	depends on WEXT_CORE
- 
- config WEXT_SPY
--	bool
-+	bool "WEXT_SPY"
- 
- config WEXT_PRIV
--	bool
-+	bool "WEXT_PRIV"
- 
- config CFG80211
- 	tristate "cfg80211 - wireless configuration API"
-@@ -204,7 +204,7 @@ config CFG80211_WEXT_EXPORT
- endif # CFG80211
- 
- config LIB80211
--	tristate
-+	tristate "LIB80211"
- 	default n
- 	help
- 	  This options enables a library of common routines used
-@@ -213,17 +213,17 @@ config LIB80211
- 	  Drivers should select this themselves if needed.
- 
- config LIB80211_CRYPT_WEP
--	tristate
-+	tristate "LIB80211_CRYPT_WEP"
- 	select CRYPTO_LIB_ARC4
- 
- config LIB80211_CRYPT_CCMP
--	tristate
-+	tristate "LIB80211_CRYPT_CCMP"
- 	select CRYPTO
- 	select CRYPTO_AES
- 	select CRYPTO_CCM
- 
- config LIB80211_CRYPT_TKIP
--	tristate
-+	tristate "LIB80211_CRYPT_TKIP"
- 	select CRYPTO_LIB_ARC4
- 
- config LIB80211_DEBUG
 --- a/sound/core/Kconfig
 +++ b/sound/core/Kconfig
 @@ -17,7 +17,7 @@ config SND_DMAENGINE_PCM
diff --git a/target/linux/generic/hack-5.15/321-powerpc_crtsavres_prereq.patch b/target/linux/generic/hack-5.15/321-powerpc_crtsavres_prereq.patch
deleted file mode 100644
index f1942e2037598d..00000000000000
--- a/target/linux/generic/hack-5.15/321-powerpc_crtsavres_prereq.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From 107c0964cb8db7ca28ac5199426414fdab3c274d Mon Sep 17 00:00:00 2001
-From: "Alexandros C. Couloumbis" <alex@ozo.com>
-Date: Fri, 7 Jul 2017 17:14:51 +0200
-Subject: hack: arch: powerpc: drop register save/restore library from modules
-
-Upstream GCC uses a libgcc function for saving/restoring registers. This
-makes the code bigger, and upstream kernels need to carry that function
-for every single kernel module. Our GCC is patched to avoid those
-references, so we can drop the extra bloat for modules.
-
-lede-commit: e8e1084654f50904e6bf77b70b2de3f137d7b3ec
-Signed-off-by: Alexandros C. Couloumbis <alex@ozo.com>
----
- arch/powerpc/Makefile | 1 -
- 1 file changed, 1 deletion(-)
-
---- a/arch/powerpc/Makefile
-+++ b/arch/powerpc/Makefile
-@@ -44,19 +44,6 @@ machine-$(CONFIG_PPC64) += 64
- machine-$(CONFIG_CPU_LITTLE_ENDIAN) += le
- UTS_MACHINE := $(subst $(space),,$(machine-y))
- 
--# XXX This needs to be before we override LD below
--ifdef CONFIG_PPC32
--KBUILD_LDFLAGS_MODULE += arch/powerpc/lib/crtsavres.o
--else
--ifeq ($(call ld-ifversion, -ge, 22500, y),y)
--# Have the linker provide sfpr if possible.
--# There is a corresponding test in arch/powerpc/lib/Makefile
--KBUILD_LDFLAGS_MODULE += --save-restore-funcs
--else
--KBUILD_LDFLAGS_MODULE += arch/powerpc/lib/crtsavres.o
--endif
--endif
--
- ifdef CONFIG_CPU_LITTLE_ENDIAN
- KBUILD_CFLAGS	+= -mlittle-endian
- KBUILD_LDFLAGS	+= -EL
diff --git a/target/linux/generic/hack-5.15/410-block-fit-partition-parser.patch b/target/linux/generic/hack-5.15/410-block-fit-partition-parser.patch
deleted file mode 100644
index 13a16b6fa08240..00000000000000
--- a/target/linux/generic/hack-5.15/410-block-fit-partition-parser.patch
+++ /dev/null
@@ -1,214 +0,0 @@
-From 69357074558daf6ff24c9f58714935e9e095a865 Mon Sep 17 00:00:00 2001
-From: OpenWrt community <openwrt-devel@lists.openwrt.org>
-Date: Wed, 13 Jul 2022 13:37:33 +0200
-Subject: [PATCH] kernel: add block fit partition parser
-
----
- block/blk.h                     |  2 ++
- block/partitions/Kconfig        |  7 +++++++
- block/partitions/Makefile       |  1 +
- block/partitions/check.h        |  3 +++
- block/partitions/core.c         | 17 +++++++++++++++++
- block/partitions/efi.c          |  8 ++++++++
- block/partitions/efi.h          |  3 +++
- block/partitions/msdos.c        | 10 ++++++++++
- drivers/mtd/mtd_blkdevs.c       |  2 ++
- drivers/mtd/ubi/block.c         |  3 +++
- include/linux/msdos_partition.h |  1 +
- 11 files changed, 57 insertions(+)
-
---- a/block/blk.h
-+++ b/block/blk.h
-@@ -354,6 +354,8 @@ void blk_free_ext_minor(unsigned int min
- #define ADDPART_FLAG_NONE	0
- #define ADDPART_FLAG_RAID	1
- #define ADDPART_FLAG_WHOLEDISK	2
-+#define ADDPART_FLAG_READONLY	4
-+#define ADDPART_FLAG_ROOTDEV	8
- int bdev_add_partition(struct gendisk *disk, int partno, sector_t start,
- 		sector_t length);
- int bdev_del_partition(struct gendisk *disk, int partno);
---- a/block/partitions/Kconfig
-+++ b/block/partitions/Kconfig
-@@ -101,6 +101,13 @@ config ATARI_PARTITION
- 	  Say Y here if you would like to use hard disks under Linux which
- 	  were partitioned under the Atari OS.
- 
-+config FIT_PARTITION
-+	bool "Flattened-Image-Tree (FIT) partition support" if PARTITION_ADVANCED
-+	default n
-+	help
-+	  Say Y here if your system needs to mount the filesystem part of
-+	  a Flattened-Image-Tree (FIT) image commonly used with Das U-Boot.
-+
- config IBM_PARTITION
- 	bool "IBM disk label and partition support"
- 	depends on PARTITION_ADVANCED && S390
---- a/block/partitions/Makefile
-+++ b/block/partitions/Makefile
-@@ -8,6 +8,7 @@ obj-$(CONFIG_ACORN_PARTITION) += acorn.o
- obj-$(CONFIG_AMIGA_PARTITION) += amiga.o
- obj-$(CONFIG_ATARI_PARTITION) += atari.o
- obj-$(CONFIG_AIX_PARTITION) += aix.o
-+obj-$(CONFIG_FIT_PARTITION) += fit.o
- obj-$(CONFIG_CMDLINE_PARTITION) += cmdline.o
- obj-$(CONFIG_MAC_PARTITION) += mac.o
- obj-$(CONFIG_LDM_PARTITION) += ldm.o
---- a/block/partitions/check.h
-+++ b/block/partitions/check.h
-@@ -58,6 +58,7 @@ int amiga_partition(struct parsed_partit
- int atari_partition(struct parsed_partitions *state);
- int cmdline_partition(struct parsed_partitions *state);
- int efi_partition(struct parsed_partitions *state);
-+int fit_partition(struct parsed_partitions *state);
- int ibm_partition(struct parsed_partitions *);
- int karma_partition(struct parsed_partitions *state);
- int ldm_partition(struct parsed_partitions *state);
-@@ -68,3 +69,5 @@ int sgi_partition(struct parsed_partitio
- int sun_partition(struct parsed_partitions *state);
- int sysv68_partition(struct parsed_partitions *state);
- int ultrix_partition(struct parsed_partitions *state);
-+
-+int parse_fit_partitions(struct parsed_partitions *state, u64 start_sector, u64 nr_sectors, int *slot, int add_remain);
---- a/block/partitions/core.c
-+++ b/block/partitions/core.c
-@@ -12,6 +12,10 @@
- #include <linux/vmalloc.h>
- #include <linux/blktrace_api.h>
- #include <linux/raid/detect.h>
-+#ifdef CONFIG_FIT_PARTITION
-+#include <linux/root_dev.h>
-+#endif
-+
- #include "check.h"
- 
- static int (*check_part[])(struct parsed_partitions *) = {
-@@ -48,6 +52,9 @@ static int (*check_part[])(struct parsed
- #ifdef CONFIG_EFI_PARTITION
- 	efi_partition,		/* this must come before msdos */
- #endif
-+#ifdef CONFIG_FIT_PARTITION
-+	fit_partition,
-+#endif
- #ifdef CONFIG_SGI_PARTITION
- 	sgi_partition,
- #endif
-@@ -408,6 +415,11 @@ static struct block_device *add_partitio
- 			goto out_del;
- 	}
- 
-+#ifdef CONFIG_FIT_PARTITION
-+	if (flags & ADDPART_FLAG_READONLY)
-+		bdev->bd_read_only = true;
-+#endif
-+
- 	/* everything is up and running, commence */
- 	err = xa_insert(&disk->part_tbl, partno, bdev, GFP_KERNEL);
- 	if (err)
-@@ -595,6 +607,11 @@ static bool blk_add_partition(struct gen
- 	    (state->parts[p].flags & ADDPART_FLAG_RAID))
- 		md_autodetect_dev(part->bd_dev);
- 
-+#ifdef CONFIG_FIT_PARTITION
-+	if ((state->parts[p].flags & ADDPART_FLAG_ROOTDEV) && ROOT_DEV == 0)
-+		ROOT_DEV = part->bd_dev;
-+#endif
-+
- 	return true;
- }
- 
---- a/block/partitions/efi.c
-+++ b/block/partitions/efi.c
-@@ -716,6 +716,9 @@ int efi_partition(struct parsed_partitio
- 	gpt_entry *ptes = NULL;
- 	u32 i;
- 	unsigned ssz = queue_logical_block_size(state->disk->queue) / 512;
-+#ifdef CONFIG_FIT_PARTITION
-+	u32 extra_slot = 64;
-+#endif
- 
- 	if (!find_valid_gpt(state, &gpt, &ptes) || !gpt || !ptes) {
- 		kfree(gpt);
-@@ -749,6 +752,11 @@ int efi_partition(struct parsed_partitio
- 				ARRAY_SIZE(ptes[i].partition_name));
- 		utf16_le_to_7bit(ptes[i].partition_name, label_max, info->volname);
- 		state->parts[i + 1].has_info = true;
-+#ifdef CONFIG_FIT_PARTITION
-+		/* If this is a U-Boot FIT volume it may have subpartitions */
-+		if (!efi_guidcmp(ptes[i].partition_type_guid, PARTITION_LINUX_FIT_GUID))
-+			(void) parse_fit_partitions(state, start * ssz, size * ssz, &extra_slot, 1);
-+#endif
- 	}
- 	kfree(ptes);
- 	kfree(gpt);
---- a/block/partitions/efi.h
-+++ b/block/partitions/efi.h
-@@ -52,6 +52,9 @@
- #define PARTITION_LINUX_LVM_GUID \
-     EFI_GUID( 0xe6d6d379, 0xf507, 0x44c2, \
-               0xa2, 0x3c, 0x23, 0x8f, 0x2a, 0x3d, 0xf9, 0x28)
-+#define PARTITION_LINUX_FIT_GUID \
-+    EFI_GUID( 0xcae9be83, 0xb15f, 0x49cc, \
-+              0x86, 0x3f, 0x08, 0x1b, 0x74, 0x4a, 0x2d, 0x93)
- 
- typedef struct _gpt_header {
- 	__le64 signature;
---- a/block/partitions/msdos.c
-+++ b/block/partitions/msdos.c
-@@ -564,6 +564,15 @@ static void parse_minix(struct parsed_pa
- #endif /* CONFIG_MINIX_SUBPARTITION */
- }
- 
-+static void parse_fit_mbr(struct parsed_partitions *state,
-+			  sector_t offset, sector_t size, int origin)
-+{
-+#ifdef CONFIG_FIT_PARTITION
-+	u32 extra_slot = 64;
-+	(void) parse_fit_partitions(state, offset, size, &extra_slot, 1);
-+#endif /* CONFIG_FIT_PARTITION */
-+}
-+
- static struct {
- 	unsigned char id;
- 	void (*parse)(struct parsed_partitions *, sector_t, sector_t, int);
-@@ -575,6 +584,7 @@ static struct {
- 	{UNIXWARE_PARTITION, parse_unixware},
- 	{SOLARIS_X86_PARTITION, parse_solaris_x86},
- 	{NEW_SOLARIS_X86_PARTITION, parse_solaris_x86},
-+	{FIT_PARTITION, parse_fit_mbr},
- 	{0, NULL},
- };
- 
---- a/drivers/mtd/mtd_blkdevs.c
-+++ b/drivers/mtd/mtd_blkdevs.c
-@@ -345,6 +345,8 @@ int add_mtd_blktrans_dev(struct mtd_blkt
- 	gd->first_minor = (new->devnum) << tr->part_bits;
- 	gd->minors = 1 << tr->part_bits;
- 	gd->fops = &mtd_block_ops;
-+	if (IS_ENABLED(CONFIG_FIT_PARTITION) && !mtd_type_is_nand(new->mtd))
-+		gd->flags |= GENHD_FL_EXT_DEVT;
- 
- 	if (tr->part_bits)
- 		if (new->devnum < 26)
---- a/drivers/mtd/ubi/block.c
-+++ b/drivers/mtd/ubi/block.c
-@@ -428,6 +428,9 @@ int ubiblock_create(struct ubi_volume_in
- 		goto out_cleanup_disk;
- 	}
- 	gd->private_data = dev;
-+#ifdef CONFIG_FIT_PARTITION
-+	gd->flags |= GENHD_FL_EXT_DEVT;
-+#endif
- 	sprintf(gd->disk_name, "ubiblock%d_%d", dev->ubi_num, dev->vol_id);
- 	set_capacity(gd, disk_capacity);
- 	dev->gd = gd;
---- a/include/linux/msdos_partition.h
-+++ b/include/linux/msdos_partition.h
-@@ -31,6 +31,7 @@ enum msdos_sys_ind {
- 	LINUX_LVM_PARTITION = 0x8e,
- 	LINUX_RAID_PARTITION = 0xfd,	/* autodetect RAID partition */
- 
-+	FIT_PARTITION = 0x2e,		/* U-Boot uImage.FIT */
- 	SOLARIS_X86_PARTITION =	0x82,	/* also Linux swap partitions */
- 	NEW_SOLARIS_X86_PARTITION = 0xbf,
- 
diff --git a/target/linux/generic/hack-5.15/720-net-phy-add-aqr-phys.patch b/target/linux/generic/hack-5.15/720-net-phy-add-aqr-phys.patch
deleted file mode 100644
index c4a915956e9c9d..00000000000000
--- a/target/linux/generic/hack-5.15/720-net-phy-add-aqr-phys.patch
+++ /dev/null
@@ -1,120 +0,0 @@
-From: Birger Koblitz <git@birger-koblitz.de>
-Date: Sun, 5 Sep 2021 15:13:10 +0200
-Subject: [PATCH] kernel: Add AQR113C and AQR813 support
-
-This hack adds support for the Aquantia 4th generation, 10GBit
-PHYs AQR113C and AQR813.
-
-Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
-
---- a/drivers/net/phy/aquantia/aquantia_main.c
-+++ b/drivers/net/phy/aquantia/aquantia_main.c
-@@ -23,6 +23,7 @@
- #define PHY_ID_AQCS109	0x03a1b5c2
- #define PHY_ID_AQR405	0x03a1b4b0
- #define PHY_ID_AQR113C	0x31c31c12
-+#define PHY_ID_AQR813	0x31c31cb2
- 
- #define MDIO_PHYXS_VEND_IF_STATUS		0xe812
- #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK	GENMASK(7, 3)
-@@ -360,6 +361,49 @@ static int aqr107_read_rate(struct phy_d
- 	return 0;
- }
- 
-+static int aqr113c_read_status(struct phy_device *phydev)
-+{
-+	int val, ret;
-+
-+	ret = aqr_read_status(phydev);
-+	if (ret)
-+		return ret;
-+
-+	if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE)
-+		return 0;
-+
-+	// On AQR113C, the speed returned by aqr_read_status is wrong
-+	aqr107_read_rate(phydev);
-+
-+	val = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_VEND_IF_STATUS);
-+	if (val < 0)
-+		return val;
-+
-+	switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) {
-+	case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR:
-+		phydev->interface = PHY_INTERFACE_MODE_10GKR;
-+		break;
-+	case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI:
-+		phydev->interface = PHY_INTERFACE_MODE_10GBASER;
-+		break;
-+	case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII:
-+		phydev->interface = PHY_INTERFACE_MODE_USXGMII;
-+		break;
-+	case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII:
-+		phydev->interface = PHY_INTERFACE_MODE_SGMII;
-+		break;
-+	case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII:
-+		phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
-+		break;
-+	default:
-+		phydev->interface = PHY_INTERFACE_MODE_NA;
-+		break;
-+	}
-+
-+	/* Read downshifted rate from vendor register */
-+	return aqr107_read_rate(phydev);
-+}
-+
- static int aqr107_read_status(struct phy_device *phydev)
- {
- 	int val, ret;
-@@ -499,7 +543,7 @@ static void aqr107_chip_info(struct phy_
- 	build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val);
- 	prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val);
- 
--	phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u\n",
-+	phydev_info(phydev, "FW %u.%u, Build %u, Provisioning %u\n",
- 		   fw_major, fw_minor, build_id, prov_id);
- }
- 
-@@ -762,7 +806,7 @@ static struct phy_driver aqr_driver[] =
- 	.config_aneg    = aqr_config_aneg,
- 	.config_intr    = aqr_config_intr,
- 	.handle_interrupt       = aqr_handle_interrupt,
--	.read_status    = aqr107_read_status,
-+	.read_status    = aqr113c_read_status,
- 	.get_tunable    = aqr107_get_tunable,
- 	.set_tunable    = aqr107_set_tunable,
- 	.suspend        = aqr107_suspend,
-@@ -772,6 +816,24 @@ static struct phy_driver aqr_driver[] =
- 	.get_stats      = aqr107_get_stats,
- 	.link_change_notify = aqr107_link_change_notify,
- },
-+{
-+	PHY_ID_MATCH_MODEL(PHY_ID_AQR813),
-+	.name		= "Aquantia AQR813",
-+	.probe		= aqr107_probe,
-+	.config_init	= aqr107_config_init,
-+	.config_aneg    = aqr_config_aneg,
-+	.config_intr	= aqr_config_intr,
-+	.handle_interrupt = aqr_handle_interrupt,
-+	.read_status	= aqr113c_read_status,
-+	.get_tunable    = aqr107_get_tunable,
-+	.set_tunable    = aqr107_set_tunable,
-+	.suspend	= aqr107_suspend,
-+	.resume		= aqr107_resume,
-+	.get_sset_count	= aqr107_get_sset_count,
-+	.get_strings	= aqr107_get_strings,
-+	.get_stats	= aqr107_get_stats,
-+	.link_change_notify = aqr107_link_change_notify,
-+},
- };
- 
- module_phy_driver(aqr_driver);
-@@ -785,6 +847,7 @@ static struct mdio_device_id __maybe_unu
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
-+	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR813) },
- 	{ }
- };
- 
diff --git a/target/linux/generic/hack-5.15/722-net-phy-aquantia-enable-AQR112-and-AQR412.patch b/target/linux/generic/hack-5.15/722-net-phy-aquantia-enable-AQR112-and-AQR412.patch
index 6ec0db2526d625..d003291f755aea 100644
--- a/target/linux/generic/hack-5.15/722-net-phy-aquantia-enable-AQR112-and-AQR412.patch
+++ b/target/linux/generic/hack-5.15/722-net-phy-aquantia-enable-AQR112-and-AQR412.patch
@@ -15,8 +15,8 @@ Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
 
 --- a/drivers/net/phy/aquantia/aquantia_main.c
 +++ b/drivers/net/phy/aquantia/aquantia_main.c
-@@ -24,6 +24,8 @@
- #define PHY_ID_AQR405	0x03a1b4b0
+@@ -27,6 +27,8 @@
+ #define PHY_ID_AQR113	0x31c31c40
  #define PHY_ID_AQR113C	0x31c31c12
  #define PHY_ID_AQR813	0x31c31cb2
 +#define PHY_ID_AQR112	0x03a1b662
@@ -24,7 +24,7 @@ Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
  
  #define MDIO_PHYXS_VEND_IF_STATUS		0xe812
  #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK	GENMASK(7, 3)
-@@ -96,6 +98,29 @@
+@@ -99,6 +101,29 @@
  #define AQR107_OP_IN_PROG_SLEEP		1000
  #define AQR107_OP_IN_PROG_TIMEOUT	100000
  
@@ -54,7 +54,7 @@ Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
  struct aqr107_hw_stat {
  	const char *name;
  	int reg;
-@@ -227,6 +252,51 @@ static int aqr_config_aneg(struct phy_de
+@@ -230,6 +255,51 @@ static int aqr_config_aneg(struct phy_de
  	return genphy_c45_check_and_restart_aneg(phydev, changed);
  }
  
@@ -106,7 +106,7 @@ Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
  static int aqr_config_intr(struct phy_device *phydev)
  {
  	bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED;
-@@ -834,6 +904,30 @@ static struct phy_driver aqr_driver[] =
+@@ -858,6 +928,30 @@ static struct phy_driver aqr_driver[] =
  	.get_stats	= aqr107_get_stats,
  	.link_change_notify = aqr107_link_change_notify,
  },
@@ -137,8 +137,8 @@ Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
  };
  
  module_phy_driver(aqr_driver);
-@@ -848,6 +942,8 @@ static struct mdio_device_id __maybe_unu
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
+@@ -875,6 +969,8 @@ static struct mdio_device_id __maybe_unu
+ 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113) },
  	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
  	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR813) },
 +	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR112) },
diff --git a/target/linux/generic/hack-5.15/723-net-phy-aquantia-fix-system-side-protocol-mi.patch b/target/linux/generic/hack-5.15/723-net-phy-aquantia-fix-system-side-protocol-mi.patch
index 33b182eab92557..72a70ebc140a94 100644
--- a/target/linux/generic/hack-5.15/723-net-phy-aquantia-fix-system-side-protocol-mi.patch
+++ b/target/linux/generic/hack-5.15/723-net-phy-aquantia-fix-system-side-protocol-mi.patch
@@ -14,7 +14,7 @@ Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
 
 --- a/drivers/net/phy/aquantia/aquantia_main.c
 +++ b/drivers/net/phy/aquantia/aquantia_main.c
-@@ -285,10 +285,16 @@ static int aqr_config_aneg_set_prot(stru
+@@ -288,10 +288,16 @@ static int aqr_config_aneg_set_prot(stru
  	phy_write_mmd(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GSTART_RATE,
  		      aquantia_syscfg[if_type].start_rate);
  
diff --git a/target/linux/generic/hack-5.15/724-net-phy-aquantia-Add-AQR113-driver-support.patch b/target/linux/generic/hack-5.15/724-net-phy-aquantia-Add-AQR113-driver-support.patch
deleted file mode 100644
index a31b327f9e96ed..00000000000000
--- a/target/linux/generic/hack-5.15/724-net-phy-aquantia-Add-AQR113-driver-support.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From 2e677e4ae8f8330f68013163b060d0fda3a43095 Mon Sep 17 00:00:00 2001
-From: "Langer, Thomas" <tlanger@maxlinear.com>
-Date: Fri, 9 Jul 2021 17:36:46 +0200
-Subject: [PATCH] PONRTSYS-8842: aquantia: Add AQR113 driver support
-
-Add a new entry for AQR113 PHY_ID
----
- drivers/net/phy/aquantia/aquantia_main.c | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
---- a/drivers/net/phy/aquantia/aquantia_main.c
-+++ b/drivers/net/phy/aquantia/aquantia_main.c
-@@ -26,6 +26,7 @@
- #define PHY_ID_AQR813	0x31c31cb2
- #define PHY_ID_AQR112	0x03a1b662
- #define PHY_ID_AQR412	0x03a1b712
-+#define PHY_ID_AQR113	0x31c31c40
- 
- #define MDIO_PHYXS_VEND_IF_STATUS		0xe812
- #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK	GENMASK(7, 3)
-@@ -923,6 +924,14 @@ static struct phy_driver aqr_driver[] =
- 	.get_stats	= aqr107_get_stats,
- },
- {
-+	PHY_ID_MATCH_MODEL(PHY_ID_AQR113),
-+	.name		= "Aquantia AQR113",
-+	.config_aneg	= aqr_config_aneg,
-+	.config_intr	= aqr_config_intr,
-+	.handle_interrupt = aqr_handle_interrupt,
-+	.read_status	= aqr107_read_status,
-+},
-+{
- 	PHY_ID_MATCH_MODEL(PHY_ID_AQR412),
- 	.name		= "Aquantia AQR412",
- 	.probe		= aqr107_probe,
-@@ -950,6 +959,7 @@ static struct mdio_device_id __maybe_unu
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR813) },
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR112) },
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR412) },
-+	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113) },
- 	{ }
- };
- 
diff --git a/target/linux/generic/hack-5.15/725-net-phy-aquantia-add-PHY_IDs-for-AQR112-variants.patch b/target/linux/generic/hack-5.15/725-net-phy-aquantia-add-PHY_IDs-for-AQR112-variants.patch
index b2f79f4d5862c7..2193844e64a784 100644
--- a/target/linux/generic/hack-5.15/725-net-phy-aquantia-add-PHY_IDs-for-AQR112-variants.patch
+++ b/target/linux/generic/hack-5.15/725-net-phy-aquantia-add-PHY_IDs-for-AQR112-variants.patch
@@ -12,17 +12,17 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 
 --- a/drivers/net/phy/aquantia/aquantia_main.c
 +++ b/drivers/net/phy/aquantia/aquantia_main.c
-@@ -27,6 +27,8 @@
+@@ -29,6 +29,8 @@
+ #define PHY_ID_AQR813	0x31c31cb2
  #define PHY_ID_AQR112	0x03a1b662
  #define PHY_ID_AQR412	0x03a1b712
- #define PHY_ID_AQR113	0x31c31c40
 +#define PHY_ID_AQR112C	0x03a1b790
 +#define PHY_ID_AQR112R	0x31c31d12
  
  #define MDIO_PHYXS_VEND_IF_STATUS		0xe812
  #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK	GENMASK(7, 3)
-@@ -924,6 +926,30 @@ static struct phy_driver aqr_driver[] =
- 	.get_stats	= aqr107_get_stats,
+@@ -880,6 +882,30 @@ static struct phy_driver aqr_driver[] =
+ 	.read_status	= aqr_read_status,
  },
  {
 +	PHY_ID_MATCH_MODEL(PHY_ID_AQR112C),
@@ -51,11 +51,11 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 +{
  	PHY_ID_MATCH_MODEL(PHY_ID_AQR113),
  	.name		= "Aquantia AQR113",
- 	.config_aneg	= aqr_config_aneg,
-@@ -960,6 +986,8 @@ static struct mdio_device_id __maybe_unu
+ 	.probe          = aqr107_probe,
+@@ -977,6 +1003,8 @@ static struct mdio_device_id __maybe_unu
+ 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR813) },
  	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR112) },
  	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR412) },
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113) },
 +	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR112C) },
 +	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR112R) },
  	{ }
diff --git a/target/linux/generic/hack-5.15/726-net-phy-aquantia-enable-AQR111-and-AQR111B0.patch b/target/linux/generic/hack-5.15/726-net-phy-aquantia-enable-AQR111-and-AQR111B0.patch
deleted file mode 100644
index 3d2c86169b660c..00000000000000
--- a/target/linux/generic/hack-5.15/726-net-phy-aquantia-enable-AQR111-and-AQR111B0.patch
+++ /dev/null
@@ -1,109 +0,0 @@
-Author: Thomas Kupper <thomas.kupper@gmail.com>
-Date:   Wed May 24 21:14:17 2023 +0200
-
-kernel: phy: add Aquantia PHY AQR111 & AQR111B0
-
-Add the IDs for Aquantia PHY AQR111 and AQR111B0 as found in the GPL sources
-of the Netgear RAX120v2 firmware v1.2.8.40.
-
-This is a 5GbE chip but it reports support for 10G. Implement config_init()
-to set max speed to 5G.
-
-Signed-off-by: Thomas Kupper <thomas.kupper@gmail.com>
---- a/drivers/net/phy/aquantia/aquantia_main.c
-+++ b/drivers/net/phy/aquantia/aquantia_main.c
-@@ -24,6 +24,8 @@
- #define PHY_ID_AQR405	0x03a1b4b0
- #define PHY_ID_AQR113C	0x31c31c12
- #define PHY_ID_AQR813	0x31c31cb2
-+#define PHY_ID_AQR111	0x03a1b610
-+#define PHY_ID_AQR111B0	0x03a1b612
- #define PHY_ID_AQR112	0x03a1b662
- #define PHY_ID_AQR412	0x03a1b712
- #define PHY_ID_AQR113	0x31c31c40
-@@ -676,6 +678,33 @@ static int aqcs109_config_init(struct ph
- 	return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
- }
- 
-+static int aqr111_config_init(struct phy_device *phydev)
-+{
-+	int ret;
-+
-+	/* Check that the PHY interface type is compatible */
-+	if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
-+	    phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&
-+	    phydev->interface != PHY_INTERFACE_MODE_XGMII &&
-+	    phydev->interface != PHY_INTERFACE_MODE_USXGMII &&
-+	    phydev->interface != PHY_INTERFACE_MODE_10GKR &&
-+	    phydev->interface != PHY_INTERFACE_MODE_10GBASER)
-+		return -ENODEV;
-+
-+	WARN(phydev->interface == PHY_INTERFACE_MODE_XGMII,
-+	     "Your devicetree is out of date, please update it. The AQR107 family doesn't support XGMII, maybe you mean USXGMII.\n");
-+
-+	ret = aqr107_wait_reset_complete(phydev);
-+	if (!ret)
-+		aqr107_chip_info(phydev);
-+
-+	/* AQR111 reports supporting speed up to 10G, however only speeds up to 5G are supported. */
-+	ret = phy_set_max_speed(phydev, SPEED_5000);
-+	if (ret)
-+		return ret;
-+
-+	return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
-+}
- static void aqr107_link_change_notify(struct phy_device *phydev)
- {
- 	u8 fw_major, fw_minor;
-@@ -914,6 +943,42 @@ static struct phy_driver aqr_driver[] =
- 	.link_change_notify = aqr107_link_change_notify,
- },
- {
-+	PHY_ID_MATCH_MODEL(PHY_ID_AQR111),
-+	.name		= "Aquantia AQR111",
-+	.probe		= aqr107_probe,
-+	.config_init	= aqr111_config_init,
-+	.config_aneg    = aqr_config_aneg,
-+	.config_intr	= aqr_config_intr,
-+	.handle_interrupt = aqr_handle_interrupt,
-+	.read_status	= aqr107_read_status,
-+	.get_tunable    = aqr107_get_tunable,
-+	.set_tunable    = aqr107_set_tunable,
-+	.suspend	= aqr107_suspend,
-+	.resume		= aqr107_resume,
-+	.get_sset_count	= aqr107_get_sset_count,
-+	.get_strings	= aqr107_get_strings,
-+	.get_stats	= aqr107_get_stats,
-+	.link_change_notify = aqr107_link_change_notify,
-+},
-+{
-+	PHY_ID_MATCH_MODEL(PHY_ID_AQR111B0),
-+	.name		= "Aquantia AQR111B0",
-+	.probe		= aqr107_probe,
-+	.config_init	= aqr111_config_init,
-+	.config_aneg    = aqr_config_aneg,
-+	.config_intr	= aqr_config_intr,
-+	.handle_interrupt = aqr_handle_interrupt,
-+	.read_status	= aqr107_read_status,
-+	.get_tunable    = aqr107_get_tunable,
-+	.set_tunable    = aqr107_set_tunable,
-+	.suspend	= aqr107_suspend,
-+	.resume		= aqr107_resume,
-+	.get_sset_count	= aqr107_get_sset_count,
-+	.get_strings	= aqr107_get_strings,
-+	.get_stats	= aqr107_get_stats,
-+	.link_change_notify = aqr107_link_change_notify,
-+},
-+{
- 	PHY_ID_MATCH_MODEL(PHY_ID_AQR112),
- 	.name		= "Aquantia AQR112",
- 	.probe		= aqr107_probe,
-@@ -983,6 +1048,8 @@ static struct mdio_device_id __maybe_unu
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR813) },
-+	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR111) },
-+	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR111B0) },
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR112) },
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR412) },
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113) },
diff --git a/target/linux/generic/hack-6.1/204-module_strip.patch b/target/linux/generic/hack-6.1/204-module_strip.patch
index bd168649f2ea20..9fefd0bd6eff2a 100644
--- a/target/linux/generic/hack-6.1/204-module_strip.patch
+++ b/target/linux/generic/hack-6.1/204-module_strip.patch
@@ -141,7 +141,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
 --- a/scripts/mod/modpost.c
 +++ b/scripts/mod/modpost.c
-@@ -1781,7 +1781,9 @@ static void read_symbols(const char *mod
+@@ -1785,7 +1785,9 @@ static void read_symbols(const char *mod
  		symname = remove_dot(info.strtab + sym->st_name);
  
  		handle_symbol(mod, &info, sym, symname);
@@ -151,7 +151,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	}
  
  	for (sym = info.symtab_start; sym < info.symtab_stop; sym++) {
-@@ -1944,8 +1946,10 @@ static void add_header(struct buffer *b,
+@@ -1948,8 +1950,10 @@ static void add_header(struct buffer *b,
  	buf_printf(b, "BUILD_SALT;\n");
  	buf_printf(b, "BUILD_LTO_INFO;\n");
  	buf_printf(b, "\n");
@@ -162,7 +162,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	buf_printf(b, "\n");
  	buf_printf(b, "__visible struct module __this_module\n");
  	buf_printf(b, "__section(\".gnu.linkonce.this_module\") = {\n");
-@@ -1959,8 +1963,10 @@ static void add_header(struct buffer *b,
+@@ -1963,8 +1967,10 @@ static void add_header(struct buffer *b,
  	buf_printf(b, "\t.arch = MODULE_ARCH_INIT,\n");
  	buf_printf(b, "};\n");
  
@@ -173,7 +173,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  	buf_printf(b,
  		   "\n"
-@@ -1968,8 +1974,10 @@ static void add_header(struct buffer *b,
+@@ -1972,8 +1978,10 @@ static void add_header(struct buffer *b,
  		   "MODULE_INFO(retpoline, \"Y\");\n"
  		   "#endif\n");
  
@@ -184,7 +184,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  	if (strstarts(mod->name, "tools/testing"))
  		buf_printf(b, "\nMODULE_INFO(test, \"Y\");\n");
-@@ -2065,11 +2073,13 @@ static void add_depends(struct buffer *b
+@@ -2069,11 +2077,13 @@ static void add_depends(struct buffer *b
  
  static void add_srcversion(struct buffer *b, struct module *mod)
  {
@@ -198,7 +198,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  }
  
  static void write_buf(struct buffer *b, const char *fname)
-@@ -2155,7 +2165,9 @@ static void write_mod_c_file(struct modu
+@@ -2159,7 +2169,9 @@ static void write_mod_c_file(struct modu
  	add_exported_symbols(&buf, mod);
  	add_versions(&buf, mod);
  	add_depends(&buf, mod);
diff --git a/target/linux/generic/hack-6.1/221-module_exports.patch b/target/linux/generic/hack-6.1/221-module_exports.patch
index d1ff81613a87fb..967510bcb6d92f 100644
--- a/target/linux/generic/hack-6.1/221-module_exports.patch
+++ b/target/linux/generic/hack-6.1/221-module_exports.patch
@@ -30,7 +30,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  /* Align . to a 8 byte boundary equals to maximum function alignment. */
  #define ALIGN_FUNCTION()  . = ALIGN(8)
  
-@@ -512,14 +522,14 @@
+@@ -511,14 +521,14 @@
  	/* Kernel symbol table: Normal symbols */			\
  	__ksymtab         : AT(ADDR(__ksymtab) - LOAD_OFFSET) {		\
  		__start___ksymtab = .;					\
@@ -47,7 +47,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  		__stop___ksymtab_gpl = .;				\
  	}								\
  									\
-@@ -539,7 +549,7 @@
+@@ -538,7 +548,7 @@
  									\
  	/* Kernel symbol table: strings */				\
          __ksymtab_strings : AT(ADDR(__ksymtab_strings) - LOAD_OFFSET) {	\
@@ -56,7 +56,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	}								\
  									\
  	/* __*init sections */						\
-@@ -1048,6 +1058,8 @@
+@@ -1042,6 +1052,8 @@
  #define COMMON_DISCARDS							\
  	SANITIZER_DISCARDS						\
  	PATCHABLE_DISCARDS						\
diff --git a/target/linux/generic/hack-6.1/251-kconfig.patch b/target/linux/generic/hack-6.1/251-kconfig.patch
index e1ecbca6fe36a3..fcf4eaf6e8d398 100644
--- a/target/linux/generic/hack-6.1/251-kconfig.patch
+++ b/target/linux/generic/hack-6.1/251-kconfig.patch
@@ -124,59 +124,6 @@ Signed-off-by: John Crispin <john@phrozen.org>
  
  config NETFILTER_FAMILY_BRIDGE
  	bool
---- a/net/wireless/Kconfig
-+++ b/net/wireless/Kconfig
-@@ -1,6 +1,6 @@
- # SPDX-License-Identifier: GPL-2.0-only
- config WIRELESS_EXT
--	bool
-+	bool "Wireless extensions"
- 
- config WEXT_CORE
- 	def_bool y
-@@ -12,10 +12,10 @@ config WEXT_PROC
- 	depends on WEXT_CORE
- 
- config WEXT_SPY
--	bool
-+	bool "WEXT_SPY"
- 
- config WEXT_PRIV
--	bool
-+	bool "WEXT_PRIV"
- 
- config CFG80211
- 	tristate "cfg80211 - wireless configuration API"
-@@ -208,7 +208,7 @@ config CFG80211_WEXT_EXPORT
- endif # CFG80211
- 
- config LIB80211
--	tristate
-+	tristate "LIB80211"
- 	default n
- 	help
- 	  This options enables a library of common routines used
-@@ -217,17 +217,17 @@ config LIB80211
- 	  Drivers should select this themselves if needed.
- 
- config LIB80211_CRYPT_WEP
--	tristate
-+	tristate "LIB80211_CRYPT_WEP"
- 	select CRYPTO_LIB_ARC4
- 
- config LIB80211_CRYPT_CCMP
--	tristate
-+	tristate "LIB80211_CRYPT_CCMP"
- 	select CRYPTO
- 	select CRYPTO_AES
- 	select CRYPTO_CCM
- 
- config LIB80211_CRYPT_TKIP
--	tristate
-+	tristate "LIB80211_CRYPT_TKIP"
- 	select CRYPTO_LIB_ARC4
- 
- config LIB80211_DEBUG
 --- a/sound/core/Kconfig
 +++ b/sound/core/Kconfig
 @@ -17,7 +17,7 @@ config SND_DMAENGINE_PCM
diff --git a/target/linux/generic/hack-6.1/253-ksmbd-config.patch b/target/linux/generic/hack-6.1/253-ksmbd-config.patch
index 4bb5eb9a6c5b74..a57c914180b84e 100644
--- a/target/linux/generic/hack-6.1/253-ksmbd-config.patch
+++ b/target/linux/generic/hack-6.1/253-ksmbd-config.patch
@@ -10,7 +10,7 @@ Subject: [PATCH] Kconfig: add tristate for OID and ASNI string
 
 --- a/init/Kconfig
 +++ b/init/Kconfig
-@@ -2004,7 +2004,7 @@ config PADATA
+@@ -2013,7 +2013,7 @@ config PADATA
  	bool
  
  config ASN1
diff --git a/target/linux/generic/hack-6.1/321-powerpc_crtsavres_prereq.patch b/target/linux/generic/hack-6.1/321-powerpc_crtsavres_prereq.patch
deleted file mode 100644
index 17eba0b354eb80..00000000000000
--- a/target/linux/generic/hack-6.1/321-powerpc_crtsavres_prereq.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From 107c0964cb8db7ca28ac5199426414fdab3c274d Mon Sep 17 00:00:00 2001
-From: "Alexandros C. Couloumbis" <alex@ozo.com>
-Date: Fri, 7 Jul 2017 17:14:51 +0200
-Subject: hack: arch: powerpc: drop register save/restore library from modules
-
-Upstream GCC uses a libgcc function for saving/restoring registers. This
-makes the code bigger, and upstream kernels need to carry that function
-for every single kernel module. Our GCC is patched to avoid those
-references, so we can drop the extra bloat for modules.
-
-lede-commit: e8e1084654f50904e6bf77b70b2de3f137d7b3ec
-Signed-off-by: Alexandros C. Couloumbis <alex@ozo.com>
----
- arch/powerpc/Makefile | 1 -
- 1 file changed, 1 deletion(-)
-
---- a/arch/powerpc/Makefile
-+++ b/arch/powerpc/Makefile
-@@ -42,19 +42,6 @@ machine-$(CONFIG_PPC64) += 64
- machine-$(CONFIG_CPU_LITTLE_ENDIAN) += le
- UTS_MACHINE := $(subst $(space),,$(machine-y))
- 
--# XXX This needs to be before we override LD below
--ifdef CONFIG_PPC32
--KBUILD_LDFLAGS_MODULE += arch/powerpc/lib/crtsavres.o
--else
--ifeq ($(call ld-ifversion, -ge, 22500, y),y)
--# Have the linker provide sfpr if possible.
--# There is a corresponding test in arch/powerpc/lib/Makefile
--KBUILD_LDFLAGS_MODULE += --save-restore-funcs
--else
--KBUILD_LDFLAGS_MODULE += arch/powerpc/lib/crtsavres.o
--endif
--endif
--
- ifdef CONFIG_CPU_LITTLE_ENDIAN
- KBUILD_CFLAGS	+= -mlittle-endian
- KBUILD_LDFLAGS	+= -EL
diff --git a/target/linux/generic/hack-6.1/410-block-fit-partition-parser.patch b/target/linux/generic/hack-6.1/410-block-fit-partition-parser.patch
deleted file mode 100644
index 1258f64722a526..00000000000000
--- a/target/linux/generic/hack-6.1/410-block-fit-partition-parser.patch
+++ /dev/null
@@ -1,217 +0,0 @@
-From 69357074558daf6ff24c9f58714935e9e095a865 Mon Sep 17 00:00:00 2001
-From: OpenWrt community <openwrt-devel@lists.openwrt.org>
-Date: Wed, 13 Jul 2022 13:37:33 +0200
-Subject: [PATCH] kernel: add block fit partition parser
-
----
- block/blk.h                     |  2 ++
- block/partitions/Kconfig        |  7 +++++++
- block/partitions/Makefile       |  1 +
- block/partitions/check.h        |  3 +++
- block/partitions/core.c         | 17 +++++++++++++++++
- block/partitions/efi.c          |  8 ++++++++
- block/partitions/efi.h          |  3 +++
- block/partitions/msdos.c        | 10 ++++++++++
- drivers/mtd/mtd_blkdevs.c       |  2 ++
- drivers/mtd/ubi/block.c         |  3 +++
- include/linux/msdos_partition.h |  1 +
- 11 files changed, 57 insertions(+)
-
---- a/block/blk.h
-+++ b/block/blk.h
-@@ -414,6 +414,8 @@ void blk_free_ext_minor(unsigned int min
- #define ADDPART_FLAG_NONE	0
- #define ADDPART_FLAG_RAID	1
- #define ADDPART_FLAG_WHOLEDISK	2
-+#define ADDPART_FLAG_READONLY	4
-+#define ADDPART_FLAG_ROOTDEV	8
- int bdev_add_partition(struct gendisk *disk, int partno, sector_t start,
- 		sector_t length);
- int bdev_del_partition(struct gendisk *disk, int partno);
---- a/block/partitions/Kconfig
-+++ b/block/partitions/Kconfig
-@@ -103,6 +103,13 @@ config ATARI_PARTITION
- 	  Say Y here if you would like to use hard disks under Linux which
- 	  were partitioned under the Atari OS.
- 
-+config FIT_PARTITION
-+	bool "Flattened-Image-Tree (FIT) partition support" if PARTITION_ADVANCED
-+	default n
-+	help
-+	  Say Y here if your system needs to mount the filesystem part of
-+	  a Flattened-Image-Tree (FIT) image commonly used with Das U-Boot.
-+
- config IBM_PARTITION
- 	bool "IBM disk label and partition support"
- 	depends on PARTITION_ADVANCED && S390
---- a/block/partitions/Makefile
-+++ b/block/partitions/Makefile
-@@ -8,6 +8,7 @@ obj-$(CONFIG_ACORN_PARTITION) += acorn.o
- obj-$(CONFIG_AMIGA_PARTITION) += amiga.o
- obj-$(CONFIG_ATARI_PARTITION) += atari.o
- obj-$(CONFIG_AIX_PARTITION) += aix.o
-+obj-$(CONFIG_FIT_PARTITION) += fit.o
- obj-$(CONFIG_CMDLINE_PARTITION) += cmdline.o
- obj-$(CONFIG_MAC_PARTITION) += mac.o
- obj-$(CONFIG_LDM_PARTITION) += ldm.o
---- a/block/partitions/check.h
-+++ b/block/partitions/check.h
-@@ -57,6 +57,7 @@ int amiga_partition(struct parsed_partit
- int atari_partition(struct parsed_partitions *state);
- int cmdline_partition(struct parsed_partitions *state);
- int efi_partition(struct parsed_partitions *state);
-+int fit_partition(struct parsed_partitions *state);
- int ibm_partition(struct parsed_partitions *);
- int karma_partition(struct parsed_partitions *state);
- int ldm_partition(struct parsed_partitions *state);
-@@ -67,3 +68,5 @@ int sgi_partition(struct parsed_partitio
- int sun_partition(struct parsed_partitions *state);
- int sysv68_partition(struct parsed_partitions *state);
- int ultrix_partition(struct parsed_partitions *state);
-+
-+int parse_fit_partitions(struct parsed_partitions *state, u64 start_sector, u64 nr_sectors, int *slot, int add_remain);
---- a/block/partitions/core.c
-+++ b/block/partitions/core.c
-@@ -10,6 +10,10 @@
- #include <linux/ctype.h>
- #include <linux/vmalloc.h>
- #include <linux/raid/detect.h>
-+#ifdef CONFIG_FIT_PARTITION
-+#include <linux/root_dev.h>
-+#endif
-+
- #include "check.h"
- 
- static int (*check_part[])(struct parsed_partitions *) = {
-@@ -46,6 +50,9 @@ static int (*check_part[])(struct parsed
- #ifdef CONFIG_EFI_PARTITION
- 	efi_partition,		/* this must come before msdos */
- #endif
-+#ifdef CONFIG_FIT_PARTITION
-+	fit_partition,
-+#endif
- #ifdef CONFIG_SGI_PARTITION
- 	sgi_partition,
- #endif
-@@ -398,6 +405,11 @@ static struct block_device *add_partitio
- 			goto out_del;
- 	}
- 
-+#ifdef CONFIG_FIT_PARTITION
-+	if (flags & ADDPART_FLAG_READONLY)
-+		bdev->bd_read_only = true;
-+#endif
-+
- 	/* everything is up and running, commence */
- 	err = xa_insert(&disk->part_tbl, partno, bdev, GFP_KERNEL);
- 	if (err)
-@@ -585,6 +597,11 @@ static bool blk_add_partition(struct gen
- 	    (state->parts[p].flags & ADDPART_FLAG_RAID))
- 		md_autodetect_dev(part->bd_dev);
- 
-+#ifdef CONFIG_FIT_PARTITION
-+	if ((state->parts[p].flags & ADDPART_FLAG_ROOTDEV) && ROOT_DEV == 0)
-+		ROOT_DEV = part->bd_dev;
-+#endif
-+
- 	return true;
- }
- 
---- a/block/partitions/efi.c
-+++ b/block/partitions/efi.c
-@@ -716,6 +716,9 @@ int efi_partition(struct parsed_partitio
- 	gpt_entry *ptes = NULL;
- 	u32 i;
- 	unsigned ssz = queue_logical_block_size(state->disk->queue) / 512;
-+#ifdef CONFIG_FIT_PARTITION
-+	u32 extra_slot = 64;
-+#endif
- 
- 	if (!find_valid_gpt(state, &gpt, &ptes) || !gpt || !ptes) {
- 		kfree(gpt);
-@@ -749,6 +752,11 @@ int efi_partition(struct parsed_partitio
- 				ARRAY_SIZE(ptes[i].partition_name));
- 		utf16_le_to_7bit(ptes[i].partition_name, label_max, info->volname);
- 		state->parts[i + 1].has_info = true;
-+#ifdef CONFIG_FIT_PARTITION
-+		/* If this is a U-Boot FIT volume it may have subpartitions */
-+		if (!efi_guidcmp(ptes[i].partition_type_guid, PARTITION_LINUX_FIT_GUID))
-+			(void) parse_fit_partitions(state, start * ssz, size * ssz, &extra_slot, 1);
-+#endif
- 	}
- 	kfree(ptes);
- 	kfree(gpt);
---- a/block/partitions/efi.h
-+++ b/block/partitions/efi.h
-@@ -51,6 +51,9 @@
- #define PARTITION_LINUX_LVM_GUID \
-     EFI_GUID( 0xe6d6d379, 0xf507, 0x44c2, \
-               0xa2, 0x3c, 0x23, 0x8f, 0x2a, 0x3d, 0xf9, 0x28)
-+#define PARTITION_LINUX_FIT_GUID \
-+    EFI_GUID( 0xcae9be83, 0xb15f, 0x49cc, \
-+              0x86, 0x3f, 0x08, 0x1b, 0x74, 0x4a, 0x2d, 0x93)
- 
- typedef struct _gpt_header {
- 	__le64 signature;
---- a/block/partitions/msdos.c
-+++ b/block/partitions/msdos.c
-@@ -564,6 +564,15 @@ static void parse_minix(struct parsed_pa
- #endif /* CONFIG_MINIX_SUBPARTITION */
- }
- 
-+static void parse_fit_mbr(struct parsed_partitions *state,
-+			  sector_t offset, sector_t size, int origin)
-+{
-+#ifdef CONFIG_FIT_PARTITION
-+	u32 extra_slot = 64;
-+	(void) parse_fit_partitions(state, offset, size, &extra_slot, 1);
-+#endif /* CONFIG_FIT_PARTITION */
-+}
-+
- static struct {
- 	unsigned char id;
- 	void (*parse)(struct parsed_partitions *, sector_t, sector_t, int);
-@@ -575,6 +584,7 @@ static struct {
- 	{UNIXWARE_PARTITION, parse_unixware},
- 	{SOLARIS_X86_PARTITION, parse_solaris_x86},
- 	{NEW_SOLARIS_X86_PARTITION, parse_solaris_x86},
-+	{FIT_PARTITION, parse_fit_mbr},
- 	{0, NULL},
- };
- 
---- a/drivers/mtd/mtd_blkdevs.c
-+++ b/drivers/mtd/mtd_blkdevs.c
-@@ -359,7 +359,9 @@ int add_mtd_blktrans_dev(struct mtd_blkt
- 	} else {
- 		snprintf(gd->disk_name, sizeof(gd->disk_name),
- 			 "%s%d", tr->name, new->devnum);
--		gd->flags |= GENHD_FL_NO_PART;
-+
-+		if (!IS_ENABLED(CONFIG_FIT_PARTITION) || mtd_type_is_nand(new->mtd))
-+			gd->flags |= GENHD_FL_NO_PART;
- 	}
- 
- 	set_capacity(gd, ((u64)new->size * tr->blksize) >> 9);
---- a/drivers/mtd/ubi/block.c
-+++ b/drivers/mtd/ubi/block.c
-@@ -431,7 +431,9 @@ int ubiblock_create(struct ubi_volume_in
- 		ret = -ENODEV;
- 		goto out_cleanup_disk;
- 	}
--	gd->flags |= GENHD_FL_NO_PART;
-+	if (!IS_ENABLED(CONFIG_FIT_PARTITION))
-+		gd->flags |= GENHD_FL_NO_PART;
-+
- 	gd->private_data = dev;
- 	sprintf(gd->disk_name, "ubiblock%d_%d", dev->ubi_num, dev->vol_id);
- 	set_capacity(gd, disk_capacity);
---- a/include/linux/msdos_partition.h
-+++ b/include/linux/msdos_partition.h
-@@ -31,6 +31,7 @@ enum msdos_sys_ind {
- 	LINUX_LVM_PARTITION = 0x8e,
- 	LINUX_RAID_PARTITION = 0xfd,	/* autodetect RAID partition */
- 
-+	FIT_PARTITION = 0x2e,		/* U-Boot uImage.FIT */
- 	SOLARIS_X86_PARTITION =	0x82,	/* also Linux swap partitions */
- 	NEW_SOLARIS_X86_PARTITION = 0xbf,
- 
diff --git a/target/linux/generic/hack-6.1/650-netfilter-add-xt_FLOWOFFLOAD-target.patch b/target/linux/generic/hack-6.1/650-netfilter-add-xt_FLOWOFFLOAD-target.patch
index 9ff45a414ee0b8..f753b590e70b9c 100644
--- a/target/linux/generic/hack-6.1/650-netfilter-add-xt_FLOWOFFLOAD-target.patch
+++ b/target/linux/generic/hack-6.1/650-netfilter-add-xt_FLOWOFFLOAD-target.patch
@@ -36,7 +36,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  obj-$(CONFIG_NETFILTER_XT_TARGET_LED) += xt_LED.o
 --- /dev/null
 +++ b/net/netfilter/xt_FLOWOFFLOAD.c
-@@ -0,0 +1,698 @@
+@@ -0,0 +1,699 @@
 +/*
 + * Copyright (C) 2018-2021 Felix Fietkau <nbd@nbd.name>
 + *
@@ -574,6 +574,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 +	if (!net)
 +		write_pnet(&table->ft.net, xt_net(par));
 +
++	__set_bit(NF_FLOW_HW_BIDIRECTIONAL, &flow->flags);
 +	if (flow_offload_add(&table->ft, flow) < 0)
 +		goto err_flow_add;
 +
diff --git a/target/linux/generic/hack-6.1/700-swconfig_switch_drivers.patch b/target/linux/generic/hack-6.1/700-swconfig_switch_drivers.patch
index 5f49678a34b979..673082d8408e02 100644
--- a/target/linux/generic/hack-6.1/700-swconfig_switch_drivers.patch
+++ b/target/linux/generic/hack-6.1/700-swconfig_switch_drivers.patch
@@ -12,7 +12,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/drivers/net/phy/Kconfig
 +++ b/drivers/net/phy/Kconfig
-@@ -69,6 +69,80 @@ config SFP
+@@ -67,6 +67,80 @@ config SFP
  	depends on HWMON || HWMON=n
  	select MDIO_I2C
  
@@ -92,7 +92,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 +
  comment "MII PHY device drivers"
  
- config AMD_PHY
+ config AIR_EN8811H_PHY
 --- a/drivers/net/phy/Makefile
 +++ b/drivers/net/phy/Makefile
 @@ -24,6 +24,21 @@ libphy-$(CONFIG_LED_TRIGGER_PHY)	+= phy_
diff --git a/target/linux/generic/hack-6.1/720-net-phy-add-aqr-phys.patch b/target/linux/generic/hack-6.1/720-net-phy-add-aqr-phys.patch
deleted file mode 100644
index df04511c81b034..00000000000000
--- a/target/linux/generic/hack-6.1/720-net-phy-add-aqr-phys.patch
+++ /dev/null
@@ -1,120 +0,0 @@
-From: Birger Koblitz <git@birger-koblitz.de>
-Date: Sun, 5 Sep 2021 15:13:10 +0200
-Subject: [PATCH] kernel: Add AQR113C and AQR813 support
-
-This hack adds support for the Aquantia 4th generation, 10GBit
-PHYs AQR113C and AQR813.
-
-Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
-
---- a/drivers/net/phy/aquantia/aquantia_main.c
-+++ b/drivers/net/phy/aquantia/aquantia_main.c
-@@ -23,6 +23,7 @@
- #define PHY_ID_AQCS109	0x03a1b5c2
- #define PHY_ID_AQR405	0x03a1b4b0
- #define PHY_ID_AQR113C	0x31c31c12
-+#define PHY_ID_AQR813	0x31c31cb2
- 
- #define MDIO_PHYXS_VEND_IF_STATUS		0xe812
- #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK	GENMASK(7, 3)
-@@ -360,6 +361,49 @@ static int aqr107_read_rate(struct phy_d
- 	return 0;
- }
- 
-+static int aqr113c_read_status(struct phy_device *phydev)
-+{
-+	int val, ret;
-+
-+	ret = aqr_read_status(phydev);
-+	if (ret)
-+		return ret;
-+
-+	if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE)
-+		return 0;
-+
-+	// On AQR113C, the speed returned by aqr_read_status is wrong
-+	aqr107_read_rate(phydev);
-+
-+	val = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_VEND_IF_STATUS);
-+	if (val < 0)
-+		return val;
-+
-+	switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) {
-+	case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR:
-+		phydev->interface = PHY_INTERFACE_MODE_10GKR;
-+		break;
-+	case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI:
-+		phydev->interface = PHY_INTERFACE_MODE_10GBASER;
-+		break;
-+	case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII:
-+		phydev->interface = PHY_INTERFACE_MODE_USXGMII;
-+		break;
-+	case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII:
-+		phydev->interface = PHY_INTERFACE_MODE_SGMII;
-+		break;
-+	case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII:
-+		phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
-+		break;
-+	default:
-+		phydev->interface = PHY_INTERFACE_MODE_NA;
-+		break;
-+	}
-+
-+	/* Read downshifted rate from vendor register */
-+	return aqr107_read_rate(phydev);
-+}
-+
- static int aqr107_read_status(struct phy_device *phydev)
- {
- 	int val, ret;
-@@ -499,7 +543,7 @@ static void aqr107_chip_info(struct phy_
- 	build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val);
- 	prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val);
- 
--	phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u\n",
-+	phydev_info(phydev, "FW %u.%u, Build %u, Provisioning %u\n",
- 		   fw_major, fw_minor, build_id, prov_id);
- }
- 
-@@ -760,7 +804,7 @@ static struct phy_driver aqr_driver[] =
- 	.config_aneg    = aqr_config_aneg,
- 	.config_intr    = aqr_config_intr,
- 	.handle_interrupt       = aqr_handle_interrupt,
--	.read_status    = aqr107_read_status,
-+	.read_status    = aqr113c_read_status,
- 	.get_tunable    = aqr107_get_tunable,
- 	.set_tunable    = aqr107_set_tunable,
- 	.suspend        = aqr107_suspend,
-@@ -770,6 +814,24 @@ static struct phy_driver aqr_driver[] =
- 	.get_stats      = aqr107_get_stats,
- 	.link_change_notify = aqr107_link_change_notify,
- },
-+{
-+	PHY_ID_MATCH_MODEL(PHY_ID_AQR813),
-+	.name		= "Aquantia AQR813",
-+	.probe		= aqr107_probe,
-+	.config_init	= aqr107_config_init,
-+	.config_aneg    = aqr_config_aneg,
-+	.config_intr	= aqr_config_intr,
-+	.handle_interrupt = aqr_handle_interrupt,
-+	.read_status	= aqr113c_read_status,
-+	.get_tunable    = aqr107_get_tunable,
-+	.set_tunable    = aqr107_set_tunable,
-+	.suspend	= aqr107_suspend,
-+	.resume		= aqr107_resume,
-+	.get_sset_count	= aqr107_get_sset_count,
-+	.get_strings	= aqr107_get_strings,
-+	.get_stats	= aqr107_get_stats,
-+	.link_change_notify = aqr107_link_change_notify,
-+},
- };
- 
- module_phy_driver(aqr_driver);
-@@ -783,6 +845,7 @@ static struct mdio_device_id __maybe_unu
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
-+	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR813) },
- 	{ }
- };
- 
diff --git a/target/linux/generic/hack-6.1/722-net-phy-aquantia-enable-AQR112-and-AQR412.patch b/target/linux/generic/hack-6.1/722-net-phy-aquantia-enable-AQR112-and-AQR412.patch
index 3823050e341d7a..faaa40f9bda7c7 100644
--- a/target/linux/generic/hack-6.1/722-net-phy-aquantia-enable-AQR112-and-AQR412.patch
+++ b/target/linux/generic/hack-6.1/722-net-phy-aquantia-enable-AQR112-and-AQR412.patch
@@ -15,8 +15,8 @@ Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
 
 --- a/drivers/net/phy/aquantia/aquantia_main.c
 +++ b/drivers/net/phy/aquantia/aquantia_main.c
-@@ -24,6 +24,8 @@
- #define PHY_ID_AQR405	0x03a1b4b0
+@@ -27,6 +27,8 @@
+ #define PHY_ID_AQR113	0x31c31c40
  #define PHY_ID_AQR113C	0x31c31c12
  #define PHY_ID_AQR813	0x31c31cb2
 +#define PHY_ID_AQR112	0x03a1b662
@@ -24,7 +24,7 @@ Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
  
  #define MDIO_PHYXS_VEND_IF_STATUS		0xe812
  #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK	GENMASK(7, 3)
-@@ -96,6 +98,29 @@
+@@ -99,6 +101,29 @@
  #define AQR107_OP_IN_PROG_SLEEP		1000
  #define AQR107_OP_IN_PROG_TIMEOUT	100000
  
@@ -54,7 +54,7 @@ Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
  struct aqr107_hw_stat {
  	const char *name;
  	int reg;
-@@ -227,6 +252,51 @@ static int aqr_config_aneg(struct phy_de
+@@ -230,6 +255,51 @@ static int aqr_config_aneg(struct phy_de
  	return genphy_c45_check_and_restart_aneg(phydev, changed);
  }
  
@@ -106,7 +106,7 @@ Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
  static int aqr_config_intr(struct phy_device *phydev)
  {
  	bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED;
-@@ -832,6 +902,30 @@ static struct phy_driver aqr_driver[] =
+@@ -860,6 +930,30 @@ static struct phy_driver aqr_driver[] =
  	.get_stats	= aqr107_get_stats,
  	.link_change_notify = aqr107_link_change_notify,
  },
@@ -137,8 +137,8 @@ Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
  };
  
  module_phy_driver(aqr_driver);
-@@ -846,6 +940,8 @@ static struct mdio_device_id __maybe_unu
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
+@@ -877,6 +971,8 @@ static struct mdio_device_id __maybe_unu
+ 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113) },
  	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
  	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR813) },
 +	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR112) },
diff --git a/target/linux/generic/hack-6.1/723-net-phy-aquantia-fix-system-side-protocol-mi.patch b/target/linux/generic/hack-6.1/723-net-phy-aquantia-fix-system-side-protocol-mi.patch
index 33b182eab92557..72a70ebc140a94 100644
--- a/target/linux/generic/hack-6.1/723-net-phy-aquantia-fix-system-side-protocol-mi.patch
+++ b/target/linux/generic/hack-6.1/723-net-phy-aquantia-fix-system-side-protocol-mi.patch
@@ -14,7 +14,7 @@ Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
 
 --- a/drivers/net/phy/aquantia/aquantia_main.c
 +++ b/drivers/net/phy/aquantia/aquantia_main.c
-@@ -285,10 +285,16 @@ static int aqr_config_aneg_set_prot(stru
+@@ -288,10 +288,16 @@ static int aqr_config_aneg_set_prot(stru
  	phy_write_mmd(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GSTART_RATE,
  		      aquantia_syscfg[if_type].start_rate);
  
diff --git a/target/linux/generic/hack-6.1/724-net-phy-aquantia-Add-AQR113-driver-support.patch b/target/linux/generic/hack-6.1/724-net-phy-aquantia-Add-AQR113-driver-support.patch
deleted file mode 100644
index f59a88a14705db..00000000000000
--- a/target/linux/generic/hack-6.1/724-net-phy-aquantia-Add-AQR113-driver-support.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From 2e677e4ae8f8330f68013163b060d0fda3a43095 Mon Sep 17 00:00:00 2001
-From: "Langer, Thomas" <tlanger@maxlinear.com>
-Date: Fri, 9 Jul 2021 17:36:46 +0200
-Subject: [PATCH] PONRTSYS-8842: aquantia: Add AQR113 driver support
-
-Add a new entry for AQR113 PHY_ID
----
- drivers/net/phy/aquantia/aquantia_main.c | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
---- a/drivers/net/phy/aquantia/aquantia_main.c
-+++ b/drivers/net/phy/aquantia/aquantia_main.c
-@@ -26,6 +26,7 @@
- #define PHY_ID_AQR813	0x31c31cb2
- #define PHY_ID_AQR112	0x03a1b662
- #define PHY_ID_AQR412	0x03a1b712
-+#define PHY_ID_AQR113	0x31c31c40
- 
- #define MDIO_PHYXS_VEND_IF_STATUS		0xe812
- #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK	GENMASK(7, 3)
-@@ -932,6 +933,14 @@ static struct phy_driver aqr_driver[] =
- 	.get_strings	= aqr107_get_strings,
- 	.get_stats	= aqr107_get_stats,
- },
-+{
-+	PHY_ID_MATCH_MODEL(PHY_ID_AQR113),
-+	.name		= "Aquantia AQR113",
-+	.config_aneg	= aqr_config_aneg,
-+	.config_intr	= aqr_config_intr,
-+	.handle_interrupt = aqr_handle_interrupt,
-+	.read_status	= aqr107_read_status,
-+},
- };
- 
- module_phy_driver(aqr_driver);
-@@ -948,6 +957,7 @@ static struct mdio_device_id __maybe_unu
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR813) },
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR112) },
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR412) },
-+	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113) },
- 	{ }
- };
- 
diff --git a/target/linux/generic/hack-6.1/725-net-phy-aquantia-add-PHY_IDs-for-AQR112-variants.patch b/target/linux/generic/hack-6.1/725-net-phy-aquantia-add-PHY_IDs-for-AQR112-variants.patch
index c29c36aa22aad8..d83cc48a33ae57 100644
--- a/target/linux/generic/hack-6.1/725-net-phy-aquantia-add-PHY_IDs-for-AQR112-variants.patch
+++ b/target/linux/generic/hack-6.1/725-net-phy-aquantia-add-PHY_IDs-for-AQR112-variants.patch
@@ -12,18 +12,18 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 
 --- a/drivers/net/phy/aquantia/aquantia_main.c
 +++ b/drivers/net/phy/aquantia/aquantia_main.c
-@@ -27,6 +27,8 @@
+@@ -29,6 +29,8 @@
+ #define PHY_ID_AQR813	0x31c31cb2
  #define PHY_ID_AQR112	0x03a1b662
  #define PHY_ID_AQR412	0x03a1b712
- #define PHY_ID_AQR113	0x31c31c40
 +#define PHY_ID_AQR112C	0x03a1b790
 +#define PHY_ID_AQR112R	0x31c31d12
  
  #define MDIO_PHYXS_VEND_IF_STATUS		0xe812
  #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK	GENMASK(7, 3)
-@@ -941,6 +943,30 @@ static struct phy_driver aqr_driver[] =
- 	.handle_interrupt = aqr_handle_interrupt,
- 	.read_status	= aqr107_read_status,
+@@ -960,6 +962,30 @@ static struct phy_driver aqr_driver[] =
+ 	.get_strings	= aqr107_get_strings,
+ 	.get_stats	= aqr107_get_stats,
  },
 +{
 +	PHY_ID_MATCH_MODEL(PHY_ID_AQR112C),
@@ -52,10 +52,10 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  };
  
  module_phy_driver(aqr_driver);
-@@ -958,6 +984,8 @@ static struct mdio_device_id __maybe_unu
+@@ -979,6 +1005,8 @@ static struct mdio_device_id __maybe_unu
+ 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR813) },
  	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR112) },
  	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR412) },
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113) },
 +	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR112C) },
 +	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR112R) },
  	{ }
diff --git a/target/linux/generic/hack-6.1/726-net-phy-aquantia-enable-AQR111-and-AQR111B0.patch b/target/linux/generic/hack-6.1/726-net-phy-aquantia-enable-AQR111-and-AQR111B0.patch
deleted file mode 100644
index dbae8f52f4796d..00000000000000
--- a/target/linux/generic/hack-6.1/726-net-phy-aquantia-enable-AQR111-and-AQR111B0.patch
+++ /dev/null
@@ -1,110 +0,0 @@
-Author: Thomas Kupper <thomas.kupper@gmail.com>
-Date:   Wed May 24 21:14:17 2023 +0200
-
-kernel: phy: add Aquantia PHY AQR111 & AQR111B0
-
-Add the IDs for Aquantia PHY AQR111 and AQR111B0 as found in the GPL sources
-of the Netgear RAX120v2 firmware v1.2.8.40.
-
-This is a 5GbE chip but it reports support for 10G. Implement config_init()
-to set max speed to 5G.
-
-Signed-off-by: Thomas Kupper <thomas.kupper@gmail.com>
---- a/drivers/net/phy/aquantia/aquantia_main.c
-+++ b/drivers/net/phy/aquantia/aquantia_main.c
-@@ -24,6 +24,8 @@
- #define PHY_ID_AQR405	0x03a1b4b0
- #define PHY_ID_AQR113C	0x31c31c12
- #define PHY_ID_AQR813	0x31c31cb2
-+#define PHY_ID_AQR111	0x03a1b610
-+#define PHY_ID_AQR111B0	0x03a1b612
- #define PHY_ID_AQR112	0x03a1b662
- #define PHY_ID_AQR412	0x03a1b712
- #define PHY_ID_AQR113	0x31c31c40
-@@ -674,6 +676,34 @@ static int aqcs109_config_init(struct ph
- 	return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
- }
- 
-+static int aqr111_config_init(struct phy_device *phydev)
-+{
-+	int ret;
-+
-+	/* Check that the PHY interface type is compatible */
-+	if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
-+	    phydev->interface != PHY_INTERFACE_MODE_1000BASEKX &&
-+	    phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&
-+	    phydev->interface != PHY_INTERFACE_MODE_XGMII &&
-+	    phydev->interface != PHY_INTERFACE_MODE_USXGMII &&
-+	    phydev->interface != PHY_INTERFACE_MODE_10GKR &&
-+	    phydev->interface != PHY_INTERFACE_MODE_10GBASER &&
-+	    phydev->interface != PHY_INTERFACE_MODE_XAUI &&
-+	    phydev->interface != PHY_INTERFACE_MODE_RXAUI)
-+		return -ENODEV;
-+
-+	WARN(phydev->interface == PHY_INTERFACE_MODE_XGMII,
-+	     "Your devicetree is out of date, please update it. The AQR107 family doesn't support XGMII, maybe you mean USXGMII.\n");
-+
-+	ret = aqr107_wait_reset_complete(phydev);
-+	if (!ret)
-+		aqr107_chip_info(phydev);
-+
-+	/* AQR111 reports supporting speed up to 10G, however only speeds up to 5G are supported. */
-+	phy_set_max_speed(phydev, SPEED_5000);
-+
-+	return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
-+}
- static void aqr107_link_change_notify(struct phy_device *phydev)
- {
- 	u8 fw_major, fw_minor;
-@@ -912,6 +942,42 @@ static struct phy_driver aqr_driver[] =
- 	.link_change_notify = aqr107_link_change_notify,
- },
- {
-+	PHY_ID_MATCH_MODEL(PHY_ID_AQR111),
-+	.name		= "Aquantia AQR111",
-+	.probe		= aqr107_probe,
-+	.config_init	= aqr111_config_init,
-+	.config_aneg    = aqr_config_aneg,
-+	.config_intr	= aqr_config_intr,
-+	.handle_interrupt = aqr_handle_interrupt,
-+	.read_status	= aqr107_read_status,
-+	.get_tunable    = aqr107_get_tunable,
-+	.set_tunable    = aqr107_set_tunable,
-+	.suspend	= aqr107_suspend,
-+	.resume		= aqr107_resume,
-+	.get_sset_count	= aqr107_get_sset_count,
-+	.get_strings	= aqr107_get_strings,
-+	.get_stats	= aqr107_get_stats,
-+	.link_change_notify = aqr107_link_change_notify,
-+},
-+{
-+	PHY_ID_MATCH_MODEL(PHY_ID_AQR111B0),
-+	.name		= "Aquantia AQR111B0",
-+	.probe		= aqr107_probe,
-+	.config_init	= aqr111_config_init,
-+	.config_aneg    = aqr_config_aneg,
-+	.config_intr	= aqr_config_intr,
-+	.handle_interrupt = aqr_handle_interrupt,
-+	.read_status	= aqr107_read_status,
-+	.get_tunable    = aqr107_get_tunable,
-+	.set_tunable    = aqr107_set_tunable,
-+	.suspend	= aqr107_suspend,
-+	.resume		= aqr107_resume,
-+	.get_sset_count	= aqr107_get_sset_count,
-+	.get_strings	= aqr107_get_strings,
-+	.get_stats	= aqr107_get_stats,
-+	.link_change_notify = aqr107_link_change_notify,
-+},
-+{
- 	PHY_ID_MATCH_MODEL(PHY_ID_AQR112),
- 	.name		= "Aquantia AQR112",
- 	.probe		= aqr107_probe,
-@@ -981,6 +1047,8 @@ static struct mdio_device_id __maybe_unu
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR813) },
-+	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR111) },
-+	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR111B0) },
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR112) },
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR412) },
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113) },
diff --git a/target/linux/generic/hack-6.1/750-net-pcs-mtk-lynxi-workaround-2500BaseX-no-an.patch b/target/linux/generic/hack-6.1/750-net-pcs-mtk-lynxi-workaround-2500BaseX-no-an.patch
index 8b7f2f095577fd..a2bd3a3dbbc26b 100644
--- a/target/linux/generic/hack-6.1/750-net-pcs-mtk-lynxi-workaround-2500BaseX-no-an.patch
+++ b/target/linux/generic/hack-6.1/750-net-pcs-mtk-lynxi-workaround-2500BaseX-no-an.patch
@@ -13,7 +13,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 
 --- a/drivers/net/pcs/pcs-mtk-lynxi.c
 +++ b/drivers/net/pcs/pcs-mtk-lynxi.c
-@@ -92,14 +92,23 @@ static void mtk_pcs_lynxi_get_state(stru
+@@ -114,14 +114,23 @@ static void mtk_pcs_lynxi_get_state(stru
  				    struct phylink_link_state *state)
  {
  	struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs);
@@ -40,14 +40,14 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 +	phylink_mii_c22_pcs_decode_state(state, bmsr, FIELD_GET(SGMII_LPA, adv));
  }
  
- static int mtk_pcs_lynxi_config(struct phylink_pcs *pcs, unsigned int mode,
-@@ -134,7 +143,8 @@ static int mtk_pcs_lynxi_config(struct p
- 		/* 1000base-X or 2500base-X autoneg */
- 		sgm_mode = SGMII_REMOTE_FAULT_DIS;
- 		use_an = linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
--					   advertising);
-+					   advertising) &&
-+			 !(interface == PHY_INTERFACE_MODE_2500BASEX);
- 	} else {
- 		/* 1000base-X or 2500base-X without autoneg */
- 		sgm_mode = 0;
+ static void mtk_sgmii_reset(struct mtk_pcs_lynxi *mpcs)
+@@ -163,7 +172,8 @@ static int mtk_pcs_lynxi_config(struct p
+ 	if (neg_mode & PHYLINK_PCS_NEG_INBAND)
+ 		sgm_mode |= SGMII_REMOTE_FAULT_DIS;
+ 
+-	if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
++	if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED &&
++	    interface != PHY_INTERFACE_MODE_2500BASEX) {
+ 		if (interface == PHY_INTERFACE_MODE_SGMII)
+ 			sgm_mode |= SGMII_SPEED_DUPLEX_AN;
+ 		bmcr = BMCR_ANENABLE;
diff --git a/target/linux/generic/hack-6.1/790-SFP-GE-T-ignore-TX_FAULT.patch b/target/linux/generic/hack-6.1/790-SFP-GE-T-ignore-TX_FAULT.patch
index 27c87d5b656016..bb21bb39d39866 100644
--- a/target/linux/generic/hack-6.1/790-SFP-GE-T-ignore-TX_FAULT.patch
+++ b/target/linux/generic/hack-6.1/790-SFP-GE-T-ignore-TX_FAULT.patch
@@ -46,7 +46,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  		} else if (event == SFP_E_TIMEOUT || event == SFP_E_TX_CLEAR) {
  	init_done:
  			/* Create mdiobus and start trying for PHY */
-@@ -2573,10 +2577,12 @@ static void sfp_check_state(struct sfp *
+@@ -2578,10 +2582,12 @@ static void sfp_check_state(struct sfp *
  	mutex_lock(&sfp->st_mutex);
  	state = sfp_get_state(sfp);
  	changed = state ^ sfp->state;
diff --git a/target/linux/generic/hack-6.1/901-debloat_sock_diag.patch b/target/linux/generic/hack-6.1/901-debloat_sock_diag.patch
index ffa6e8ac60dbe9..ec71f9af4be03e 100644
--- a/target/linux/generic/hack-6.1/901-debloat_sock_diag.patch
+++ b/target/linux/generic/hack-6.1/901-debloat_sock_diag.patch
@@ -44,7 +44,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  obj-$(CONFIG_PROC_FS) += net-procfs.o
 --- a/net/core/sock.c
 +++ b/net/core/sock.c
-@@ -114,6 +114,7 @@
+@@ -115,6 +115,7 @@
  #include <linux/memcontrol.h>
  #include <linux/prefetch.h>
  #include <linux/compat.h>
@@ -52,7 +52,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  #include <linux/uaccess.h>
  
-@@ -145,6 +146,7 @@
+@@ -146,6 +147,7 @@
  
  static DEFINE_MUTEX(proto_list_mutex);
  static LIST_HEAD(proto_list);
@@ -60,7 +60,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  static void sock_def_write_space_wfree(struct sock *sk);
  static void sock_def_write_space(struct sock *sk);
-@@ -584,6 +586,18 @@ discard_and_relse:
+@@ -585,6 +587,18 @@ discard_and_relse:
  }
  EXPORT_SYMBOL(__sk_receive_skb);
  
@@ -79,7 +79,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  INDIRECT_CALLABLE_DECLARE(struct dst_entry *ip6_dst_check(struct dst_entry *,
  							  u32));
  INDIRECT_CALLABLE_DECLARE(struct dst_entry *ipv4_dst_check(struct dst_entry *,
-@@ -2187,9 +2201,11 @@ static void __sk_free(struct sock *sk)
+@@ -2188,9 +2202,11 @@ static void __sk_free(struct sock *sk)
  	if (likely(sk->sk_net_refcnt))
  		sock_inuse_add(sock_net(sk), -1);
  
diff --git a/target/linux/generic/hack-6.1/902-debloat_proc.patch b/target/linux/generic/hack-6.1/902-debloat_proc.patch
index 0d844994aaed8e..a90169efc9c202 100644
--- a/target/linux/generic/hack-6.1/902-debloat_proc.patch
+++ b/target/linux/generic/hack-6.1/902-debloat_proc.patch
@@ -330,7 +330,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
 --- a/net/core/sock.c
 +++ b/net/core/sock.c
-@@ -4113,6 +4113,8 @@ static __net_initdata struct pernet_oper
+@@ -4114,6 +4114,8 @@ static __net_initdata struct pernet_oper
  
  static int __init proto_init(void)
  {
diff --git a/target/linux/generic/hack-6.1/930-Revert-Revert-Revert-driver-core-Set-fw_devlink-on-b.patch b/target/linux/generic/hack-6.1/930-Revert-Revert-Revert-driver-core-Set-fw_devlink-on-b.patch
index 98081c4b64b14c..04aaab7adf162f 100644
--- a/target/linux/generic/hack-6.1/930-Revert-Revert-Revert-driver-core-Set-fw_devlink-on-b.patch
+++ b/target/linux/generic/hack-6.1/930-Revert-Revert-Revert-driver-core-Set-fw_devlink-on-b.patch
@@ -19,7 +19,7 @@ Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
 
 --- a/drivers/base/core.c
 +++ b/drivers/base/core.c
-@@ -1700,7 +1700,7 @@ static void device_links_purge(struct de
+@@ -1702,7 +1702,7 @@ static void device_links_purge(struct de
  #define FW_DEVLINK_FLAGS_RPM		(FW_DEVLINK_FLAGS_ON | \
  					 DL_FLAG_PM_RUNTIME)
  
diff --git a/target/linux/generic/pending-5.15/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch b/target/linux/generic/pending-5.15/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch
index d2ca7c7b537008..892887c423663f 100644
--- a/target/linux/generic/pending-5.15/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch
+++ b/target/linux/generic/pending-5.15/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch
@@ -18,7 +18,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/net/netfilter/nf_tables_api.c
 +++ b/net/netfilter/nf_tables_api.c
-@@ -7736,7 +7736,7 @@ static int nft_register_flowtable_net_ho
+@@ -7752,7 +7752,7 @@ static int nft_register_flowtable_net_ho
  		err = flowtable->data.type->setup(&flowtable->data,
  						  hook->ops.dev,
  						  FLOW_BLOCK_BIND);
diff --git a/target/linux/generic/pending-5.15/738-net-ethernet-mtk_eth_soc-set-coherent-mask-to-get-PP.patch b/target/linux/generic/pending-5.15/738-net-ethernet-mtk_eth_soc-set-coherent-mask-to-get-PP.patch
new file mode 100644
index 00000000000000..dda864ab4df022
--- /dev/null
+++ b/target/linux/generic/pending-5.15/738-net-ethernet-mtk_eth_soc-set-coherent-mask-to-get-PP.patch
@@ -0,0 +1,46 @@
+From dee3f591103910c8d8b2a6d57879ccd2a4be4b10 Mon Sep 17 00:00:00 2001
+Message-ID: <dee3f591103910c8d8b2a6d57879ccd2a4be4b10.1706067287.git.daniel@makrotopia.org>
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Wed, 24 Jan 2024 03:19:49 +0000
+Subject: [PATCH net] net: ethernet: mtk_eth_soc: set coherent mask to get PPE
+ working
+To: Felix Fietkau <nbd@nbd.name>,
+    Sean Wang <sean.wang@mediatek.com>,
+    Mark Lee <Mark-MC.Lee@mediatek.com>,
+    Lorenzo Bianconi <lorenzo@kernel.org>,
+    David S. Miller <davem@davemloft.net>,
+    Eric Dumazet <edumazet@google.com>,
+    Jakub Kicinski <kuba@kernel.org>,
+    Paolo Abeni <pabeni@redhat.com>,
+    Matthias Brugger <matthias.bgg@gmail.com>,
+    AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
+    Daniel Golle <daniel@makrotopia.org>,
+    netdev@vger.kernel.org,
+    linux-kernel@vger.kernel.org,
+    linux-arm-kernel@lists.infradead.org,
+    linux-mediatek@lists.infradead.org
+
+Set DMA coherent mask to 32-bit which makes PPE offloading engine start
+working on BPi-R4 which got 4 GiB of RAM.
+
+Fixes: 2d75891ebc09 ("net: ethernet: mtk_eth_soc: support 36-bit DMA addressing on MT7988")
+Suggested-by: Elad Yifee <eladwf@users.github.com>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -4832,7 +4832,10 @@ static int mtk_probe(struct platform_dev
+ 	}
+ 
+ 	if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) {
+-		err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(36));
++		err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(36));
++		if (!err)
++			err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
++
+ 		if (err) {
+ 			dev_err(&pdev->dev, "Wrong DMA config\n");
+ 			return -EINVAL;
diff --git a/target/linux/generic/pending-5.15/778-net-l2tp-drop-flow-hash-on-forward.patch b/target/linux/generic/pending-5.15/778-net-l2tp-drop-flow-hash-on-forward.patch
new file mode 100644
index 00000000000000..a2c0edcbbf5808
--- /dev/null
+++ b/target/linux/generic/pending-5.15/778-net-l2tp-drop-flow-hash-on-forward.patch
@@ -0,0 +1,31 @@
+From 4a44a52f16ccd3d03e0cb5fb437a5eb31a5f9f05 Mon Sep 17 00:00:00 2001
+From: David Bauer <mail@david-bauer.net>
+Date: Mon, 26 Feb 2024 21:39:34 +0100
+Subject: [PATCH] net l2tp: drop flow hash on forward
+
+Drop the flow-hash of the skb when forwarding to the L2TP netdev.
+
+This avoids the L2TP qdisc from using the flow-hash from the outer
+packet, which is identical for every flow within the tunnel.
+
+This does not affect every platform but is specific for the ethernet
+driver. It depends on the platform including L4 information in the
+flow-hash.
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+---
+ net/l2tp/l2tp_eth.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/net/l2tp/l2tp_eth.c
++++ b/net/l2tp/l2tp_eth.c
+@@ -136,6 +136,9 @@ static void l2tp_eth_dev_recv(struct l2t
+ 	/* checksums verified by L2TP */
+ 	skb->ip_summed = CHECKSUM_NONE;
+ 
++	/* drop outer flow-hash */
++	skb_clear_hash(skb);
++
+ 	skb_dst_drop(skb);
+ 	nf_reset_ct(skb);
+ 
diff --git a/target/linux/generic/pending-5.15/779-net-vxlan-don-t-learn-non-unicast-L2-destinations.patch b/target/linux/generic/pending-5.15/779-net-vxlan-don-t-learn-non-unicast-L2-destinations.patch
new file mode 100644
index 00000000000000..6c1f5967590078
--- /dev/null
+++ b/target/linux/generic/pending-5.15/779-net-vxlan-don-t-learn-non-unicast-L2-destinations.patch
@@ -0,0 +1,30 @@
+From 3f1a227cb071f65f6ecc4db9f399649869735a7c Mon Sep 17 00:00:00 2001
+From: David Bauer <mail@david-bauer.net>
+Date: Sat, 17 Feb 2024 22:34:59 +0100
+Subject: [PATCH] net vxlan: don't learn non-unicast L2 destinations
+
+This patch avoids learning non-unicast targets in the vxlan FDB.
+They are non-unicast and thus should be sent to the broadcast-IPv6
+instead of a unicast address.
+
+Link: https://lore.kernel.org/netdev/15ee0cc7-9252-466b-8ce7-5225d605dde8@david-bauer.net/
+Link: https://github.com/freifunk-gluon/gluon/issues/3191
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+---
+ drivers/net/vxlan.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/drivers/net/vxlan/vxlan_core.c
++++ b/drivers/net/vxlan/vxlan_core.c
+@@ -1493,6 +1493,10 @@ static bool vxlan_snoop(struct net_devic
+ 	struct vxlan_fdb *f;
+ 	u32 ifindex = 0;
+ 
++	/* Don't learn broadcast packets */
++	if (is_multicast_ether_addr(src_mac) || is_zero_ether_addr(src_mac))
++		return false;
++
+ #if IS_ENABLED(CONFIG_IPV6)
+ 	if (src_ip->sa.sa_family == AF_INET6 &&
+ 	    (ipv6_addr_type(&src_ip->sin6.sin6_addr) & IPV6_ADDR_LINKLOCAL))
diff --git a/target/linux/generic/pending-5.15/796-net-dsa-mt7530-fix-10M-100M-speed-on-MT7988-switch.patch b/target/linux/generic/pending-5.15/796-net-dsa-mt7530-fix-10M-100M-speed-on-MT7988-switch.patch
new file mode 100644
index 00000000000000..f2e91d3fe5fe23
--- /dev/null
+++ b/target/linux/generic/pending-5.15/796-net-dsa-mt7530-fix-10M-100M-speed-on-MT7988-switch.patch
@@ -0,0 +1,45 @@
+From a444877c10a665cd8a869e6d37facdb89fd95f79 Mon Sep 17 00:00:00 2001
+Message-ID: <a444877c10a665cd8a869e6d37facdb89fd95f79.1706070008.git.daniel@makrotopia.org>
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Wed, 24 Jan 2024 04:17:11 +0000
+Subject: [PATCH net] net: dsa: mt7530: fix 10M/100M speed on MT7988 switch
+To: Arınç ÜNAL <arinc.unal@arinc9.com>,
+    Daniel Golle <daniel@makrotopia.org>,
+    DENG Qingfang <dqfext@gmail.com>,
+    Sean Wang <sean.wang@mediatek.com>,
+    Andrew Lunn <andrew@lunn.ch>,
+    Florian Fainelli <f.fainelli@gmail.com>,
+    Vladimir Oltean <olteanv@gmail.com>,
+    David S. Miller <davem@davemloft.net>,
+    Eric Dumazet <edumazet@google.com>,
+    Jakub Kicinski <kuba@kernel.org>,
+    Paolo Abeni <pabeni@redhat.com>,
+    Matthias Brugger <matthias.bgg@gmail.com>,
+    AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
+    netdev@vger.kernel.org,
+    linux-kernel@vger.kernel.org,
+    linux-arm-kernel@lists.infradead.org,
+    linux-mediatek@lists.infradead.org
+
+Setup PMCR port register for actual speed and duplex on internally
+connected PHYs of the MT7988 built-in switch. This fixes links with
+speeds other than 1000M.
+
+Fixes: ("110c18bfed414 net: dsa: mt7530: introduce driver for MT7988 built-in switch")
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/net/dsa/mt7530.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2832,8 +2832,7 @@ static void mt753x_phylink_mac_link_up(s
+ 	/* MT753x MAC works in 1G full duplex mode for all up-clocked
+ 	 * variants.
+ 	 */
+-	if (interface == PHY_INTERFACE_MODE_INTERNAL ||
+-	    interface == PHY_INTERFACE_MODE_TRGMII ||
++	if (interface == PHY_INTERFACE_MODE_TRGMII ||
+ 	    (phy_interface_mode_is_8023z(interface))) {
+ 		speed = SPEED_1000;
+ 		duplex = DUPLEX_FULL;
diff --git a/target/linux/generic/pending-6.1/103-kbuild-export-SUBARCH.patch b/target/linux/generic/pending-6.1/103-kbuild-export-SUBARCH.patch
index e6480ac03e331b..c8c0efaecfa1bb 100644
--- a/target/linux/generic/pending-6.1/103-kbuild-export-SUBARCH.patch
+++ b/target/linux/generic/pending-6.1/103-kbuild-export-SUBARCH.patch
@@ -10,7 +10,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/Makefile
 +++ b/Makefile
-@@ -606,7 +606,7 @@ endif
+@@ -605,7 +605,7 @@ endif
  # Allows the usage of unstable features in stable compilers.
  export RUSTC_BOOTSTRAP := 1
  
diff --git a/target/linux/generic/pending-6.1/203-kallsyms_uncompressed.patch b/target/linux/generic/pending-6.1/203-kallsyms_uncompressed.patch
index ce93b73af64e09..78ed262b786c6a 100644
--- a/target/linux/generic/pending-6.1/203-kallsyms_uncompressed.patch
+++ b/target/linux/generic/pending-6.1/203-kallsyms_uncompressed.patch
@@ -13,7 +13,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/init/Kconfig
 +++ b/init/Kconfig
-@@ -1482,6 +1482,17 @@ config SYSCTL_ARCH_UNALIGN_ALLOW
+@@ -1491,6 +1491,17 @@ config SYSCTL_ARCH_UNALIGN_ALLOW
  	  the unaligned access emulation.
  	  see arch/parisc/kernel/unaligned.c for reference
  
@@ -105,7 +105,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
 --- a/scripts/link-vmlinux.sh
 +++ b/scripts/link-vmlinux.sh
-@@ -160,6 +160,10 @@ kallsyms()
+@@ -165,6 +165,10 @@ kallsyms()
  		kallsymopt="${kallsymopt} --lto-clang"
  	fi
  
diff --git a/target/linux/generic/pending-6.1/450-01-dt-bindings-mtd-add-basic-bindings-for-UBI.patch b/target/linux/generic/pending-6.1/450-01-dt-bindings-mtd-add-basic-bindings-for-UBI.patch
new file mode 100644
index 00000000000000..063d3fa79c99cf
--- /dev/null
+++ b/target/linux/generic/pending-6.1/450-01-dt-bindings-mtd-add-basic-bindings-for-UBI.patch
@@ -0,0 +1,121 @@
+From ffbbe7d66872ff8957dad2136133e28a1fd5d437 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 7 Aug 2023 22:51:05 +0100
+Subject: [PATCH 01/15] dt-bindings: mtd: add basic bindings for UBI
+
+Add basic bindings for UBI devices and volumes.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ .../bindings/mtd/partitions/linux,ubi.yaml    | 65 +++++++++++++++++++
+ .../bindings/mtd/partitions/ubi-volume.yaml   | 35 ++++++++++
+ 2 files changed, 100 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/mtd/partitions/linux,ubi.yaml
+ create mode 100644 Documentation/devicetree/bindings/mtd/partitions/ubi-volume.yaml
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/mtd/partitions/linux,ubi.yaml
+@@ -0,0 +1,65 @@
++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/mtd/partitions/linux,ubi.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Unsorted Block Images
++
++description: |
++  UBI ("Unsorted Block Images") is a volume management system for raw
++  flash devices which manages multiple logical volumes on a single
++  physical flash device and spreads the I/O load (i.e wear-leveling)
++  across the whole flash chip.
++
++maintainers:
++  - Daniel Golle <daniel@makrotopia.org>
++
++allOf:
++  - $ref: partition.yaml#
++
++properties:
++  compatible:
++    const: linux,ubi
++
++  volumes:
++    type: object
++    description: UBI Volumes
++
++    patternProperties:
++      "^ubi-volume-.*$":
++        $ref: /schemas/mtd/partitions/ubi-volume.yaml#
++
++    unevaluatedProperties: false
++
++required:
++  - compatible
++
++unevaluatedProperties: false
++
++examples:
++  - |
++    partitions {
++        compatible = "fixed-partitions";
++        #address-cells = <1>;
++        #size-cells = <1>;
++
++        partition@0 {
++            reg = <0x0 0x100000>;
++            label = "bootloader";
++            read-only;
++        };
++
++        partition@100000 {
++            reg = <0x100000 0x1ff00000>;
++            label = "ubi";
++            compatible = "linux,ubi";
++
++            volumes {
++                ubi-volume-caldata {
++                    volid = <2>;
++                    volname = "rf";
++                };
++            };
++        };
++    };
+--- /dev/null
++++ b/Documentation/devicetree/bindings/mtd/partitions/ubi-volume.yaml
+@@ -0,0 +1,35 @@
++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/mtd/partitions/ubi-volume.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: UBI volume
++
++description: |
++  This binding describes a single UBI volume. Volumes can be matches either
++  by their ID or their name, or both.
++
++maintainers:
++  - Daniel Golle <daniel@makrotopia.org>
++
++properties:
++  volid:
++    $ref: "/schemas/types.yaml#/definitions/uint32"
++    description:
++      Match UBI volume ID
++
++  volname:
++    $ref: "/schemas/types.yaml#/definitions/string"
++    description:
++      Match UBI volume ID
++
++anyOf:
++  - required:
++    - volid
++
++  - required:
++    - volname
++
++# This is a generic file other binding inherit from and extend
++additionalProperties: true
diff --git a/target/linux/generic/pending-6.1/450-02-dt-bindings-mtd-ubi-volume-allow-UBI-volumes-to-prov.patch b/target/linux/generic/pending-6.1/450-02-dt-bindings-mtd-ubi-volume-allow-UBI-volumes-to-prov.patch
new file mode 100644
index 00000000000000..823c8e83b715ba
--- /dev/null
+++ b/target/linux/generic/pending-6.1/450-02-dt-bindings-mtd-ubi-volume-allow-UBI-volumes-to-prov.patch
@@ -0,0 +1,48 @@
+From e4dad3aa5c3ab9c553555dd23c0b85f725f2eb51 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 7 Aug 2023 22:53:01 +0100
+Subject: [PATCH 02/15] dt-bindings: mtd: ubi-volume: allow UBI volumes to
+ provide NVMEM
+
+UBI volumes may be used to contain NVMEM bits, typically device MAC
+addresses or wireless radio calibration data.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ .../devicetree/bindings/mtd/partitions/linux,ubi.yaml  | 10 ++++++++++
+ .../devicetree/bindings/mtd/partitions/ubi-volume.yaml |  5 +++++
+ 2 files changed, 15 insertions(+)
+
+--- a/Documentation/devicetree/bindings/mtd/partitions/linux,ubi.yaml
++++ b/Documentation/devicetree/bindings/mtd/partitions/linux,ubi.yaml
+@@ -59,6 +59,16 @@ examples:
+                 ubi-volume-caldata {
+                     volid = <2>;
+                     volname = "rf";
++
++                    nvmem-layout {
++                        compatible = "fixed-layout";
++                        #address-cells = <1>;
++                        #size-cells = <1>;
++
++                        eeprom@0 {
++                            reg = <0x0 0x1000>;
++                        };
++                    };
+                 };
+             };
+         };
+--- a/Documentation/devicetree/bindings/mtd/partitions/ubi-volume.yaml
++++ b/Documentation/devicetree/bindings/mtd/partitions/ubi-volume.yaml
+@@ -24,6 +24,11 @@ properties:
+     description:
+       Match UBI volume ID
+ 
++  nvmem-layout:
++    $ref: /schemas/nvmem/layouts/nvmem-layout.yaml#
++    description:
++      This container may reference an NVMEM layout parser.
++
+ anyOf:
+   - required:
+     - volid
diff --git a/target/linux/generic/pending-6.1/450-03-mtd-ubi-block-use-notifier-to-create-ubiblock-from-p.patch b/target/linux/generic/pending-6.1/450-03-mtd-ubi-block-use-notifier-to-create-ubiblock-from-p.patch
new file mode 100644
index 00000000000000..eda3b108da3d9a
--- /dev/null
+++ b/target/linux/generic/pending-6.1/450-03-mtd-ubi-block-use-notifier-to-create-ubiblock-from-p.patch
@@ -0,0 +1,225 @@
+From e5cf19bd8204925f3bd2067df9e867313eac388b Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 1 May 2023 11:57:51 +0100
+Subject: [PATCH 03/15] mtd: ubi: block: use notifier to create ubiblock from
+ parameter
+
+Use UBI_VOLUME_ADDED notification to create ubiblock device specified
+on kernel cmdline or module parameter.
+This makes thing more simple and has the advantage that ubiblock devices
+on volumes which are not present at the time the ubi module is probed
+will still be created.
+
+Suggested-by: Zhihao Cheng <chengzhihao1@huawei.com>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/mtd/ubi/block.c | 154 ++++++++++++++++++++++------------------
+ 1 file changed, 85 insertions(+), 69 deletions(-)
+
+--- a/drivers/mtd/ubi/block.c
++++ b/drivers/mtd/ubi/block.c
+@@ -33,6 +33,7 @@
+ #include <linux/kernel.h>
+ #include <linux/list.h>
+ #include <linux/mutex.h>
++#include <linux/namei.h>
+ #include <linux/slab.h>
+ #include <linux/mtd/ubi.h>
+ #include <linux/workqueue.h>
+@@ -67,10 +68,10 @@ struct ubiblock_pdu {
+ };
+ 
+ /* Numbers of elements set in the @ubiblock_param array */
+-static int ubiblock_devs __initdata;
++static int ubiblock_devs;
+ 
+ /* MTD devices specification parameters */
+-static struct ubiblock_param ubiblock_param[UBIBLOCK_MAX_DEVICES] __initdata;
++static struct ubiblock_param ubiblock_param[UBIBLOCK_MAX_DEVICES];
+ 
+ struct ubiblock {
+ 	struct ubi_volume_desc *desc;
+@@ -504,7 +505,7 @@ int ubiblock_remove(struct ubi_volume_in
+ 	}
+ 
+ 	/* Found a device, let's lock it so we can check if it's busy */
+-	mutex_lock(&dev->dev_mutex);
++	mutex_lock_nested(&dev->dev_mutex, SINGLE_DEPTH_NESTING);
+ 	if (dev->refcnt > 0) {
+ 		ret = -EBUSY;
+ 		goto out_unlock_dev;
+@@ -567,6 +568,85 @@ static int ubiblock_resize(struct ubi_vo
+ 	return 0;
+ }
+ 
++static bool
++match_volume_desc(struct ubi_volume_info *vi, const char *name, int ubi_num, int vol_id)
++{
++	int err, len;
++	struct path path;
++	struct kstat stat;
++
++	if (ubi_num == -1) {
++		/* No ubi num, name must be a vol device path */
++		err = kern_path(name, LOOKUP_FOLLOW, &path);
++		if (err)
++			return false;
++
++		err = vfs_getattr(&path, &stat, STATX_TYPE, AT_STATX_SYNC_AS_STAT);
++		path_put(&path);
++		if (err)
++			return false;
++
++		if (!S_ISCHR(stat.mode))
++			return false;
++
++		if (vi->ubi_num != ubi_major2num(MAJOR(stat.rdev)))
++			return false;
++
++		if (vi->vol_id != MINOR(stat.rdev) - 1)
++			return false;
++
++		return true;
++	}
++
++	if (vol_id == -1) {
++		if (vi->ubi_num != ubi_num)
++			return false;
++
++		len = strnlen(name, UBI_VOL_NAME_MAX + 1);
++		if (len < 1 || vi->name_len != len)
++			return false;
++
++		if (strcmp(name, vi->name))
++			return false;
++
++		return true;
++	}
++
++	if (vi->ubi_num != ubi_num)
++		return false;
++
++	if (vi->vol_id != vol_id)
++		return false;
++
++	return true;
++}
++
++static void
++ubiblock_create_from_param(struct ubi_volume_info *vi)
++{
++	int i, ret = 0;
++	struct ubiblock_param *p;
++
++	/*
++	 * Iterate over ubiblock cmdline parameters. If a parameter matches the
++	 * newly added volume create the ubiblock device for it.
++	 */
++	for (i = 0; i < ubiblock_devs; i++) {
++		p = &ubiblock_param[i];
++
++		if (!match_volume_desc(vi, p->name, p->ubi_num, p->vol_id))
++			continue;
++
++		ret = ubiblock_create(vi);
++		if (ret) {
++			pr_err(
++			       "UBI: block: can't add '%s' volume on ubi%d_%d, err=%d\n",
++			       vi->name, p->ubi_num, p->vol_id, ret);
++		}
++		break;
++	}
++}
++
+ static int ubiblock_notify(struct notifier_block *nb,
+ 			 unsigned long notification_type, void *ns_ptr)
+ {
+@@ -574,10 +654,7 @@ static int ubiblock_notify(struct notifi
+ 
+ 	switch (notification_type) {
+ 	case UBI_VOLUME_ADDED:
+-		/*
+-		 * We want to enforce explicit block device creation for
+-		 * volumes, so when a volume is added we do nothing.
+-		 */
++		ubiblock_create_from_param(&nt->vi);
+ 		break;
+ 	case UBI_VOLUME_REMOVED:
+ 		ubiblock_remove(&nt->vi);
+@@ -603,56 +680,6 @@ static struct notifier_block ubiblock_no
+ 	.notifier_call = ubiblock_notify,
+ };
+ 
+-static struct ubi_volume_desc * __init
+-open_volume_desc(const char *name, int ubi_num, int vol_id)
+-{
+-	if (ubi_num == -1)
+-		/* No ubi num, name must be a vol device path */
+-		return ubi_open_volume_path(name, UBI_READONLY);
+-	else if (vol_id == -1)
+-		/* No vol_id, must be vol_name */
+-		return ubi_open_volume_nm(ubi_num, name, UBI_READONLY);
+-	else
+-		return ubi_open_volume(ubi_num, vol_id, UBI_READONLY);
+-}
+-
+-static void __init ubiblock_create_from_param(void)
+-{
+-	int i, ret = 0;
+-	struct ubiblock_param *p;
+-	struct ubi_volume_desc *desc;
+-	struct ubi_volume_info vi;
+-
+-	/*
+-	 * If there is an error creating one of the ubiblocks, continue on to
+-	 * create the following ubiblocks. This helps in a circumstance where
+-	 * the kernel command-line specifies multiple block devices and some
+-	 * may be broken, but we still want the working ones to come up.
+-	 */
+-	for (i = 0; i < ubiblock_devs; i++) {
+-		p = &ubiblock_param[i];
+-
+-		desc = open_volume_desc(p->name, p->ubi_num, p->vol_id);
+-		if (IS_ERR(desc)) {
+-			pr_err(
+-			       "UBI: block: can't open volume on ubi%d_%d, err=%ld\n",
+-			       p->ubi_num, p->vol_id, PTR_ERR(desc));
+-			continue;
+-		}
+-
+-		ubi_get_volume_info(desc, &vi);
+-		ubi_close_volume(desc);
+-
+-		ret = ubiblock_create(&vi);
+-		if (ret) {
+-			pr_err(
+-			       "UBI: block: can't add '%s' volume on ubi%d_%d, err=%d\n",
+-			       vi.name, p->ubi_num, p->vol_id, ret);
+-			continue;
+-		}
+-	}
+-}
+-
+ static void ubiblock_remove_all(void)
+ {
+ 	struct ubiblock *next;
+@@ -678,18 +705,7 @@ int __init ubiblock_init(void)
+ 	if (ubiblock_major < 0)
+ 		return ubiblock_major;
+ 
+-	/*
+-	 * Attach block devices from 'block=' module param.
+-	 * Even if one block device in the param list fails to come up,
+-	 * still allow the module to load and leave any others up.
+-	 */
+-	ubiblock_create_from_param();
+-
+-	/*
+-	 * Block devices are only created upon user requests, so we ignore
+-	 * existing volumes.
+-	 */
+-	ret = ubi_register_volume_notifier(&ubiblock_notifier, 1);
++	ret = ubi_register_volume_notifier(&ubiblock_notifier, 0);
+ 	if (ret)
+ 		goto err_unreg;
+ 	return 0;
diff --git a/target/linux/generic/pending-6.1/450-04-mtd-ubi-attach-from-device-tree.patch b/target/linux/generic/pending-6.1/450-04-mtd-ubi-attach-from-device-tree.patch
new file mode 100644
index 00000000000000..6e10e5ebed401e
--- /dev/null
+++ b/target/linux/generic/pending-6.1/450-04-mtd-ubi-attach-from-device-tree.patch
@@ -0,0 +1,264 @@
+From 471a17d8d1b838092d1a76e48cdce8b5b67ff809 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 27 Nov 2023 01:54:28 +0000
+Subject: [PATCH 04/15] mtd: ubi: attach from device tree
+
+Introduce device tree compatible 'linux,ubi' and attach compatible MTD
+devices using the MTD add notifier. This is needed for a UBI device to
+be available early at boot (and not only after late_initcall), so
+volumes on them can be used eg. as NVMEM providers for other drivers.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/mtd/ubi/build.c | 146 ++++++++++++++++++++++++++++------------
+ drivers/mtd/ubi/cdev.c  |   2 +-
+ drivers/mtd/ubi/ubi.h   |   2 +-
+ 3 files changed, 106 insertions(+), 44 deletions(-)
+
+--- a/drivers/mtd/ubi/build.c
++++ b/drivers/mtd/ubi/build.c
+@@ -27,6 +27,7 @@
+ #include <linux/log2.h>
+ #include <linux/kthread.h>
+ #include <linux/kernel.h>
++#include <linux/of.h>
+ #include <linux/slab.h>
+ #include <linux/major.h>
+ #include "ubi.h"
+@@ -1071,6 +1072,7 @@ out_free:
+  * ubi_detach_mtd_dev - detach an MTD device.
+  * @ubi_num: UBI device number to detach from
+  * @anyway: detach MTD even if device reference count is not zero
++ * @have_lock: called by MTD notifier holding mtd_table_mutex
+  *
+  * This function destroys an UBI device number @ubi_num and detaches the
+  * underlying MTD device. Returns zero in case of success and %-EBUSY if the
+@@ -1080,7 +1082,7 @@ out_free:
+  * Note, the invocations of this function has to be serialized by the
+  * @ubi_devices_mutex.
+  */
+-int ubi_detach_mtd_dev(int ubi_num, int anyway)
++int ubi_detach_mtd_dev(int ubi_num, int anyway, bool have_lock)
+ {
+ 	struct ubi_device *ubi;
+ 
+@@ -1136,7 +1138,11 @@ int ubi_detach_mtd_dev(int ubi_num, int
+ 	vfree(ubi->peb_buf);
+ 	vfree(ubi->fm_buf);
+ 	ubi_msg(ubi, "mtd%d is detached", ubi->mtd->index);
+-	put_mtd_device(ubi->mtd);
++	if (have_lock)
++		__put_mtd_device(ubi->mtd);
++	else
++		put_mtd_device(ubi->mtd);
++
+ 	put_device(&ubi->dev);
+ 	return 0;
+ }
+@@ -1213,43 +1219,43 @@ static struct mtd_info * __init open_mtd
+ 	return mtd;
+ }
+ 
+-static int __init ubi_init(void)
++static void ubi_notify_add(struct mtd_info *mtd)
+ {
+-	int err, i, k;
++	struct device_node *np = mtd_get_of_node(mtd);
++	int err;
+ 
+-	/* Ensure that EC and VID headers have correct size */
+-	BUILD_BUG_ON(sizeof(struct ubi_ec_hdr) != 64);
+-	BUILD_BUG_ON(sizeof(struct ubi_vid_hdr) != 64);
++	if (!of_device_is_compatible(np, "linux,ubi"))
++		return;
+ 
+-	if (mtd_devs > UBI_MAX_DEVICES) {
+-		pr_err("UBI error: too many MTD devices, maximum is %d\n",
+-		       UBI_MAX_DEVICES);
+-		return -EINVAL;
+-	}
++	/*
++	 * we are already holding &mtd_table_mutex, but still need
++	 * to bump refcount
++	 */
++	err = __get_mtd_device(mtd);
++	if (err)
++		return;
+ 
+-	/* Create base sysfs directory and sysfs files */
+-	err = class_register(&ubi_class);
++	/* called while holding mtd_table_mutex */
++	mutex_lock_nested(&ubi_devices_mutex, SINGLE_DEPTH_NESTING);
++	err = ubi_attach_mtd_dev(mtd, UBI_DEV_NUM_AUTO, 0, 0, false);
++	mutex_unlock(&ubi_devices_mutex);
+ 	if (err < 0)
+-		return err;
+-
+-	err = misc_register(&ubi_ctrl_cdev);
+-	if (err) {
+-		pr_err("UBI error: cannot register device\n");
+-		goto out;
+-	}
++		__put_mtd_device(mtd);
++}
+ 
+-	ubi_wl_entry_slab = kmem_cache_create("ubi_wl_entry_slab",
+-					      sizeof(struct ubi_wl_entry),
+-					      0, 0, NULL);
+-	if (!ubi_wl_entry_slab) {
+-		err = -ENOMEM;
+-		goto out_dev_unreg;
+-	}
++static void ubi_notify_remove(struct mtd_info *mtd)
++{
++	WARN(1, "mtd%d removed despite UBI still being attached", mtd->index);
++}
+ 
+-	err = ubi_debugfs_init();
+-	if (err)
+-		goto out_slab;
++static struct mtd_notifier ubi_mtd_notifier = {
++	.add = ubi_notify_add,
++	.remove = ubi_notify_remove,
++};
+ 
++static int __init ubi_init_attach(void)
++{
++	int err, i, k;
+ 
+ 	/* Attach MTD devices */
+ 	for (i = 0; i < mtd_devs; i++) {
+@@ -1297,25 +1303,79 @@ static int __init ubi_init(void)
+ 		}
+ 	}
+ 
++	return 0;
++
++out_detach:
++	for (k = 0; k < i; k++)
++		if (ubi_devices[k]) {
++			mutex_lock(&ubi_devices_mutex);
++			ubi_detach_mtd_dev(ubi_devices[k]->ubi_num, 1, false);
++			mutex_unlock(&ubi_devices_mutex);
++		}
++	return err;
++}
++#ifndef CONFIG_MTD_UBI_MODULE
++late_initcall(ubi_init_attach);
++#endif
++
++static int __init ubi_init(void)
++{
++	int err;
++
++	/* Ensure that EC and VID headers have correct size */
++	BUILD_BUG_ON(sizeof(struct ubi_ec_hdr) != 64);
++	BUILD_BUG_ON(sizeof(struct ubi_vid_hdr) != 64);
++
++	if (mtd_devs > UBI_MAX_DEVICES) {
++		pr_err("UBI error: too many MTD devices, maximum is %d\n",
++		       UBI_MAX_DEVICES);
++		return -EINVAL;
++	}
++
++	/* Create base sysfs directory and sysfs files */
++	err = class_register(&ubi_class);
++	if (err < 0)
++		return err;
++
++	err = misc_register(&ubi_ctrl_cdev);
++	if (err) {
++		pr_err("UBI error: cannot register device\n");
++		goto out;
++	}
++
++	ubi_wl_entry_slab = kmem_cache_create("ubi_wl_entry_slab",
++					      sizeof(struct ubi_wl_entry),
++					      0, 0, NULL);
++	if (!ubi_wl_entry_slab) {
++		err = -ENOMEM;
++		goto out_dev_unreg;
++	}
++
++	err = ubi_debugfs_init();
++	if (err)
++		goto out_slab;
++
+ 	err = ubiblock_init();
+ 	if (err) {
+ 		pr_err("UBI error: block: cannot initialize, error %d\n", err);
+ 
+ 		/* See comment above re-ubi_is_module(). */
+ 		if (ubi_is_module())
+-			goto out_detach;
++			goto out_slab;
++	}
++
++	register_mtd_user(&ubi_mtd_notifier);
++
++	if (ubi_is_module()) {
++		err = ubi_init_attach();
++		if (err)
++			goto out_mtd_notifier;
+ 	}
+ 
+ 	return 0;
+ 
+-out_detach:
+-	for (k = 0; k < i; k++)
+-		if (ubi_devices[k]) {
+-			mutex_lock(&ubi_devices_mutex);
+-			ubi_detach_mtd_dev(ubi_devices[k]->ubi_num, 1);
+-			mutex_unlock(&ubi_devices_mutex);
+-		}
+-	ubi_debugfs_exit();
++out_mtd_notifier:
++	unregister_mtd_user(&ubi_mtd_notifier);
+ out_slab:
+ 	kmem_cache_destroy(ubi_wl_entry_slab);
+ out_dev_unreg:
+@@ -1325,18 +1385,20 @@ out:
+ 	pr_err("UBI error: cannot initialize UBI, error %d\n", err);
+ 	return err;
+ }
+-late_initcall(ubi_init);
++device_initcall(ubi_init);
++
+ 
+ static void __exit ubi_exit(void)
+ {
+ 	int i;
+ 
+ 	ubiblock_exit();
++	unregister_mtd_user(&ubi_mtd_notifier);
+ 
+ 	for (i = 0; i < UBI_MAX_DEVICES; i++)
+ 		if (ubi_devices[i]) {
+ 			mutex_lock(&ubi_devices_mutex);
+-			ubi_detach_mtd_dev(ubi_devices[i]->ubi_num, 1);
++			ubi_detach_mtd_dev(ubi_devices[i]->ubi_num, 1, false);
+ 			mutex_unlock(&ubi_devices_mutex);
+ 		}
+ 	ubi_debugfs_exit();
+--- a/drivers/mtd/ubi/cdev.c
++++ b/drivers/mtd/ubi/cdev.c
+@@ -1065,7 +1065,7 @@ static long ctrl_cdev_ioctl(struct file
+ 		}
+ 
+ 		mutex_lock(&ubi_devices_mutex);
+-		err = ubi_detach_mtd_dev(ubi_num, 0);
++		err = ubi_detach_mtd_dev(ubi_num, 0, false);
+ 		mutex_unlock(&ubi_devices_mutex);
+ 		break;
+ 	}
+--- a/drivers/mtd/ubi/ubi.h
++++ b/drivers/mtd/ubi/ubi.h
+@@ -939,7 +939,7 @@ int ubi_io_write_vid_hdr(struct ubi_devi
+ int ubi_attach_mtd_dev(struct mtd_info *mtd, int ubi_num,
+ 		       int vid_hdr_offset, int max_beb_per1024,
+ 		       bool disable_fm);
+-int ubi_detach_mtd_dev(int ubi_num, int anyway);
++int ubi_detach_mtd_dev(int ubi_num, int anyway, bool have_lock);
+ struct ubi_device *ubi_get_device(int ubi_num);
+ void ubi_put_device(struct ubi_device *ubi);
+ struct ubi_device *ubi_get_by_major(int major);
diff --git a/target/linux/generic/pending-6.1/450-05-mtd-ubi-introduce-pre-removal-notification-for-UBI-v.patch b/target/linux/generic/pending-6.1/450-05-mtd-ubi-introduce-pre-removal-notification-for-UBI-v.patch
new file mode 100644
index 00000000000000..d5da37b8562eda
--- /dev/null
+++ b/target/linux/generic/pending-6.1/450-05-mtd-ubi-introduce-pre-removal-notification-for-UBI-v.patch
@@ -0,0 +1,226 @@
+From 2d664266cfdd114cc7a1fa28dd64275e99222455 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Thu, 8 Jun 2023 17:18:09 +0100
+Subject: [PATCH 05/15] mtd: ubi: introduce pre-removal notification for UBI
+ volumes
+
+Introduce a new notification type UBI_VOLUME_SHUTDOWN to inform users
+that a volume is just about to be removed.
+This is needed because users (such as the NVMEM subsystem) expect that
+at the time their removal function is called, the parenting device is
+still available (for removal of sysfs nodes, for example, in case of
+NVMEM which otherwise WARNs on volume removal).
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/mtd/ubi/block.c | 26 ++++++++++++++++++++++++++
+ drivers/mtd/ubi/build.c | 20 +++++++++++++++-----
+ drivers/mtd/ubi/kapi.c  |  2 +-
+ drivers/mtd/ubi/ubi.h   |  2 ++
+ drivers/mtd/ubi/vmt.c   | 17 +++++++++++++++--
+ include/linux/mtd/ubi.h |  2 ++
+ 6 files changed, 61 insertions(+), 8 deletions(-)
+
+--- a/drivers/mtd/ubi/block.c
++++ b/drivers/mtd/ubi/block.c
+@@ -568,6 +568,29 @@ static int ubiblock_resize(struct ubi_vo
+ 	return 0;
+ }
+ 
++static int ubiblock_shutdown(struct ubi_volume_info *vi)
++{
++	struct ubiblock *dev;
++	struct gendisk *disk;
++	int ret = 0;
++
++	mutex_lock(&devices_mutex);
++	dev = find_dev_nolock(vi->ubi_num, vi->vol_id);
++	if (!dev) {
++		ret = -ENODEV;
++		goto out_unlock;
++	}
++	disk = dev->gd;
++
++out_unlock:
++	mutex_unlock(&devices_mutex);
++
++	if (!ret)
++		blk_mark_disk_dead(disk);
++
++	return ret;
++};
++
+ static bool
+ match_volume_desc(struct ubi_volume_info *vi, const char *name, int ubi_num, int vol_id)
+ {
+@@ -659,6 +682,9 @@ static int ubiblock_notify(struct notifi
+ 	case UBI_VOLUME_REMOVED:
+ 		ubiblock_remove(&nt->vi);
+ 		break;
++	case UBI_VOLUME_SHUTDOWN:
++		ubiblock_shutdown(&nt->vi);
++		break;
+ 	case UBI_VOLUME_RESIZED:
+ 		ubiblock_resize(&nt->vi);
+ 		break;
+--- a/drivers/mtd/ubi/build.c
++++ b/drivers/mtd/ubi/build.c
+@@ -89,7 +89,7 @@ static struct ubi_device *ubi_devices[UB
+ /* Serializes UBI devices creations and removals */
+ DEFINE_MUTEX(ubi_devices_mutex);
+ 
+-/* Protects @ubi_devices and @ubi->ref_count */
++/* Protects @ubi_devices, @ubi->ref_count and @ubi->is_dead */
+ static DEFINE_SPINLOCK(ubi_devices_lock);
+ 
+ /* "Show" method for files in '/<sysfs>/class/ubi/' */
+@@ -258,6 +258,9 @@ struct ubi_device *ubi_get_device(int ub
+ 
+ 	spin_lock(&ubi_devices_lock);
+ 	ubi = ubi_devices[ubi_num];
++	if (ubi && ubi->is_dead)
++		ubi = NULL;
++
+ 	if (ubi) {
+ 		ubi_assert(ubi->ref_count >= 0);
+ 		ubi->ref_count += 1;
+@@ -295,7 +298,7 @@ struct ubi_device *ubi_get_by_major(int
+ 	spin_lock(&ubi_devices_lock);
+ 	for (i = 0; i < UBI_MAX_DEVICES; i++) {
+ 		ubi = ubi_devices[i];
+-		if (ubi && MAJOR(ubi->cdev.dev) == major) {
++		if (ubi && !ubi->is_dead && MAJOR(ubi->cdev.dev) == major) {
+ 			ubi_assert(ubi->ref_count >= 0);
+ 			ubi->ref_count += 1;
+ 			get_device(&ubi->dev);
+@@ -324,7 +327,7 @@ int ubi_major2num(int major)
+ 	for (i = 0; i < UBI_MAX_DEVICES; i++) {
+ 		struct ubi_device *ubi = ubi_devices[i];
+ 
+-		if (ubi && MAJOR(ubi->cdev.dev) == major) {
++		if (ubi && !ubi->is_dead && MAJOR(ubi->cdev.dev) == major) {
+ 			ubi_num = ubi->ubi_num;
+ 			break;
+ 		}
+@@ -511,7 +514,7 @@ static void ubi_free_volumes_from(struct
+ 	int i;
+ 
+ 	for (i = from; i < ubi->vtbl_slots + UBI_INT_VOL_COUNT; i++) {
+-		if (!ubi->volumes[i])
++		if (!ubi->volumes[i] || ubi->volumes[i]->is_dead)
+ 			continue;
+ 		ubi_eba_replace_table(ubi->volumes[i], NULL);
+ 		ubi_fastmap_destroy_checkmap(ubi->volumes[i]);
+@@ -1094,10 +1097,10 @@ int ubi_detach_mtd_dev(int ubi_num, int
+ 		return -EINVAL;
+ 
+ 	spin_lock(&ubi_devices_lock);
+-	put_device(&ubi->dev);
+ 	ubi->ref_count -= 1;
+ 	if (ubi->ref_count) {
+ 		if (!anyway) {
++			ubi->ref_count += 1;
+ 			spin_unlock(&ubi_devices_lock);
+ 			return -EBUSY;
+ 		}
+@@ -1105,6 +1108,13 @@ int ubi_detach_mtd_dev(int ubi_num, int
+ 		ubi_err(ubi, "%s reference count %d, destroy anyway",
+ 			ubi->ubi_name, ubi->ref_count);
+ 	}
++	ubi->is_dead = true;
++	spin_unlock(&ubi_devices_lock);
++
++	ubi_notify_all(ubi, UBI_VOLUME_SHUTDOWN, NULL);
++
++	spin_lock(&ubi_devices_lock);
++	put_device(&ubi->dev);
+ 	ubi_devices[ubi_num] = NULL;
+ 	spin_unlock(&ubi_devices_lock);
+ 
+--- a/drivers/mtd/ubi/kapi.c
++++ b/drivers/mtd/ubi/kapi.c
+@@ -152,7 +152,7 @@ struct ubi_volume_desc *ubi_open_volume(
+ 
+ 	spin_lock(&ubi->volumes_lock);
+ 	vol = ubi->volumes[vol_id];
+-	if (!vol)
++	if (!vol || vol->is_dead)
+ 		goto out_unlock;
+ 
+ 	err = -EBUSY;
+--- a/drivers/mtd/ubi/ubi.h
++++ b/drivers/mtd/ubi/ubi.h
+@@ -345,6 +345,7 @@ struct ubi_volume {
+ 	int writers;
+ 	int exclusive;
+ 	int metaonly;
++	bool is_dead;
+ 
+ 	int reserved_pebs;
+ 	int vol_type;
+@@ -564,6 +565,7 @@ struct ubi_device {
+ 	spinlock_t volumes_lock;
+ 	int ref_count;
+ 	int image_seq;
++	bool is_dead;
+ 
+ 	int rsvd_pebs;
+ 	int avail_pebs;
+--- a/drivers/mtd/ubi/vmt.c
++++ b/drivers/mtd/ubi/vmt.c
+@@ -59,7 +59,7 @@ static ssize_t vol_attribute_show(struct
+ 	struct ubi_device *ubi = vol->ubi;
+ 
+ 	spin_lock(&ubi->volumes_lock);
+-	if (!ubi->volumes[vol->vol_id]) {
++	if (!ubi->volumes[vol->vol_id] || ubi->volumes[vol->vol_id]->is_dead) {
+ 		spin_unlock(&ubi->volumes_lock);
+ 		return -ENODEV;
+ 	}
+@@ -189,7 +189,7 @@ int ubi_create_volume(struct ubi_device
+ 
+ 	/* Ensure that the name is unique */
+ 	for (i = 0; i < ubi->vtbl_slots; i++)
+-		if (ubi->volumes[i] &&
++		if (ubi->volumes[i] && !ubi->volumes[i]->is_dead &&
+ 		    ubi->volumes[i]->name_len == req->name_len &&
+ 		    !strcmp(ubi->volumes[i]->name, req->name)) {
+ 			ubi_err(ubi, "volume \"%s\" exists (ID %d)",
+@@ -352,6 +352,19 @@ int ubi_remove_volume(struct ubi_volume_
+ 		err = -EBUSY;
+ 		goto out_unlock;
+ 	}
++
++	/*
++	 * Mark volume as dead at this point to prevent that anyone
++	 * can take a reference to the volume from now on.
++	 * This is necessary as we have to release the spinlock before
++	 * calling ubi_volume_notify.
++	 */
++	vol->is_dead = true;
++	spin_unlock(&ubi->volumes_lock);
++
++	ubi_volume_notify(ubi, vol, UBI_VOLUME_SHUTDOWN);
++
++	spin_lock(&ubi->volumes_lock);
+ 	ubi->volumes[vol_id] = NULL;
+ 	spin_unlock(&ubi->volumes_lock);
+ 
+--- a/include/linux/mtd/ubi.h
++++ b/include/linux/mtd/ubi.h
+@@ -192,6 +192,7 @@ struct ubi_device_info {
+  *			or a volume was removed)
+  * @UBI_VOLUME_RESIZED: a volume has been re-sized
+  * @UBI_VOLUME_RENAMED: a volume has been re-named
++ * @UBI_VOLUME_SHUTDOWN: a volume is going to removed, shutdown users
+  * @UBI_VOLUME_UPDATED: data has been written to a volume
+  *
+  * These constants define which type of event has happened when a volume
+@@ -202,6 +203,7 @@ enum {
+ 	UBI_VOLUME_REMOVED,
+ 	UBI_VOLUME_RESIZED,
+ 	UBI_VOLUME_RENAMED,
++	UBI_VOLUME_SHUTDOWN,
+ 	UBI_VOLUME_UPDATED,
+ };
+ 
diff --git a/target/linux/generic/pending-6.1/450-06-mtd-ubi-populate-ubi-volume-fwnode.patch b/target/linux/generic/pending-6.1/450-06-mtd-ubi-populate-ubi-volume-fwnode.patch
new file mode 100644
index 00000000000000..132276696547c3
--- /dev/null
+++ b/target/linux/generic/pending-6.1/450-06-mtd-ubi-populate-ubi-volume-fwnode.patch
@@ -0,0 +1,65 @@
+From 3a041ee543cdf2e707a1dd72946cd6a583509b28 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Fri, 21 Jul 2023 19:26:37 +0100
+Subject: [PATCH 06/15] mtd: ubi: populate ubi volume fwnode
+
+Look for the 'volumes' subnode of an MTD partition attached to a UBI
+device and attach matching child nodes to UBI volumes.
+This allows UBI volumes to be referenced in device tree, e.g. for use
+as NVMEM providers.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/mtd/ubi/vmt.c | 27 +++++++++++++++++++++++++++
+ 1 file changed, 27 insertions(+)
+
+--- a/drivers/mtd/ubi/vmt.c
++++ b/drivers/mtd/ubi/vmt.c
+@@ -124,6 +124,31 @@ static void vol_release(struct device *d
+ 	kfree(vol);
+ }
+ 
++static struct fwnode_handle *find_volume_fwnode(struct ubi_volume *vol)
++{
++	struct fwnode_handle *fw_vols, *fw_vol;
++	const char *volname;
++	u32 volid;
++
++	fw_vols = device_get_named_child_node(vol->dev.parent->parent, "volumes");
++	if (!fw_vols)
++		return NULL;
++
++	fwnode_for_each_child_node(fw_vols, fw_vol) {
++		if (!fwnode_property_read_string(fw_vol, "volname", &volname) &&
++		    strncmp(volname, vol->name, vol->name_len))
++			continue;
++
++		if (!fwnode_property_read_u32(fw_vol, "volid", &volid) &&
++		    vol->vol_id != volid)
++			continue;
++
++		return fw_vol;
++	}
++
++	return NULL;
++}
++
+ /**
+  * ubi_create_volume - create volume.
+  * @ubi: UBI device description object
+@@ -223,6 +248,7 @@ int ubi_create_volume(struct ubi_device
+ 	vol->name_len  = req->name_len;
+ 	memcpy(vol->name, req->name, vol->name_len);
+ 	vol->ubi = ubi;
++	device_set_node(&vol->dev, find_volume_fwnode(vol));
+ 
+ 	/*
+ 	 * Finish all pending erases because there may be some LEBs belonging
+@@ -605,6 +631,7 @@ int ubi_add_volume(struct ubi_device *ub
+ 	vol->dev.class = &ubi_class;
+ 	vol->dev.groups = volume_dev_groups;
+ 	dev_set_name(&vol->dev, "%s_%d", ubi->ubi_name, vol->vol_id);
++	device_set_node(&vol->dev, find_volume_fwnode(vol));
+ 	err = device_register(&vol->dev);
+ 	if (err) {
+ 		cdev_del(&vol->cdev);
diff --git a/target/linux/generic/pending-6.1/450-07-mtd-ubi-provide-NVMEM-layer-over-UBI-volumes.patch b/target/linux/generic/pending-6.1/450-07-mtd-ubi-provide-NVMEM-layer-over-UBI-volumes.patch
new file mode 100644
index 00000000000000..59a1eb9374ea62
--- /dev/null
+++ b/target/linux/generic/pending-6.1/450-07-mtd-ubi-provide-NVMEM-layer-over-UBI-volumes.patch
@@ -0,0 +1,246 @@
+From 7eb6666348f3f2d1f7308c712fa5903cbe189401 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Thu, 8 Jun 2023 17:22:04 +0100
+Subject: [PATCH 07/15] mtd: ubi: provide NVMEM layer over UBI volumes
+
+In an ideal world we would like UBI to be used where ever possible on a
+NAND chip. And with UBI support in ARM Trusted Firmware and U-Boot it
+is possible to achieve an (almost-)all-UBI flash layout. Hence the need
+for a way to also use UBI volumes to store board-level constants, such
+as MAC addresses and calibration data of wireless interfaces.
+
+Add UBI volume NVMEM driver module exposing UBI volumes as NVMEM
+providers. Allow UBI devices to have a "volumes" firmware subnode with
+volumes which may be compatible with "nvmem-cells".
+Access to UBI volumes via the NVMEM interface at this point is
+read-only, and it is slow, opening and closing the UBI volume for each
+access due to limitations of the NVMEM provider API.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/mtd/ubi/Kconfig  |  12 +++
+ drivers/mtd/ubi/Makefile |   1 +
+ drivers/mtd/ubi/nvmem.c  | 188 +++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 201 insertions(+)
+ create mode 100644 drivers/mtd/ubi/nvmem.c
+
+--- a/drivers/mtd/ubi/Kconfig
++++ b/drivers/mtd/ubi/Kconfig
+@@ -104,4 +104,16 @@ config MTD_UBI_BLOCK
+ 
+ 	   If in doubt, say "N".
+ 
++config MTD_UBI_NVMEM
++	tristate "UBI virtual NVMEM"
++	default n
++	depends on NVMEM
++	help
++	   This option enabled an additional driver exposing UBI volumes as NVMEM
++	   providers, intended for platforms where UBI is part of the firmware
++	   specification and used to store also e.g. MAC addresses or board-
++	   specific Wi-Fi calibration data.
++
++	   If in doubt, say "N".
++
+ endif # MTD_UBI
+--- a/drivers/mtd/ubi/Makefile
++++ b/drivers/mtd/ubi/Makefile
+@@ -7,3 +7,4 @@ ubi-$(CONFIG_MTD_UBI_FASTMAP) += fastmap
+ ubi-$(CONFIG_MTD_UBI_BLOCK) += block.o
+ 
+ obj-$(CONFIG_MTD_UBI_GLUEBI) += gluebi.o
++obj-$(CONFIG_MTD_UBI_NVMEM) += nvmem.o
+--- /dev/null
++++ b/drivers/mtd/ubi/nvmem.c
+@@ -0,0 +1,191 @@
++// SPDX-License-Identifier: GPL-2.0-or-later
++/*
++ * Copyright (c) 2023 Daniel Golle <daniel@makrotopia.org>
++ */
++
++/* UBI NVMEM provider */
++#include "ubi.h"
++#include <linux/nvmem-provider.h>
++#include <asm/div64.h>
++
++/* List of all NVMEM devices */
++static LIST_HEAD(nvmem_devices);
++static DEFINE_MUTEX(devices_mutex);
++
++struct ubi_nvmem {
++	struct nvmem_device *nvmem;
++	int ubi_num;
++	int vol_id;
++	int usable_leb_size;
++	struct list_head list;
++};
++
++static int ubi_nvmem_reg_read(void *priv, unsigned int from,
++			      void *val, size_t bytes)
++{
++	uint32_t offs, to_read, bytes_left;
++	struct ubi_nvmem *unv = priv;
++	struct ubi_volume_desc *desc;
++	uint64_t lnum = from;
++	int err = 0;
++
++	desc = ubi_open_volume(unv->ubi_num, unv->vol_id, UBI_READONLY);
++	if (IS_ERR(desc))
++		return PTR_ERR(desc);
++
++	bytes_left = bytes;
++	offs = do_div(lnum, unv->usable_leb_size);
++	while (bytes_left) {
++		to_read = unv->usable_leb_size - offs;
++
++		if (to_read > bytes_left)
++			to_read = bytes_left;
++
++		err = ubi_read(desc, lnum, val, offs, to_read);
++		if (err)
++			break;
++
++		lnum += 1;
++		offs = 0;
++		bytes_left -= to_read;
++		val += to_read;
++	}
++	ubi_close_volume(desc);
++
++	if (err)
++		return err;
++
++	return bytes_left == 0 ? 0 : -EIO;
++}
++
++static int ubi_nvmem_add(struct ubi_volume_info *vi)
++{
++	struct device_node *np = dev_of_node(vi->dev);
++	struct nvmem_config config = {};
++	struct ubi_nvmem *unv;
++	int ret;
++
++	if (!np)
++		return 0;
++
++	if (!of_get_child_by_name(np, "nvmem-layout"))
++		return 0;
++
++	if (WARN_ON_ONCE(vi->usable_leb_size <= 0) ||
++	    WARN_ON_ONCE(vi->size <= 0))
++		return -EINVAL;
++
++	unv = kzalloc(sizeof(struct ubi_nvmem), GFP_KERNEL);
++	if (!unv)
++		return -ENOMEM;
++
++	config.id = NVMEM_DEVID_NONE;
++	config.dev = vi->dev;
++	config.name = dev_name(vi->dev);
++	config.owner = THIS_MODULE;
++	config.priv = unv;
++	config.reg_read = ubi_nvmem_reg_read;
++	config.size = vi->usable_leb_size * vi->size;
++	config.word_size = 1;
++	config.stride = 1;
++	config.read_only = true;
++	config.root_only = true;
++	config.ignore_wp = true;
++	config.of_node = np;
++
++	unv->ubi_num = vi->ubi_num;
++	unv->vol_id = vi->vol_id;
++	unv->usable_leb_size = vi->usable_leb_size;
++	unv->nvmem = nvmem_register(&config);
++	if (IS_ERR(unv->nvmem)) {
++		ret = dev_err_probe(vi->dev, PTR_ERR(unv->nvmem),
++				    "Failed to register NVMEM device\n");
++		kfree(unv);
++		return ret;
++	}
++
++	mutex_lock(&devices_mutex);
++	list_add_tail(&unv->list, &nvmem_devices);
++	mutex_unlock(&devices_mutex);
++
++	return 0;
++}
++
++static void ubi_nvmem_remove(struct ubi_volume_info *vi)
++{
++	struct ubi_nvmem *unv_c, *unv = NULL;
++
++	mutex_lock(&devices_mutex);
++	list_for_each_entry(unv_c, &nvmem_devices, list)
++		if (unv_c->ubi_num == vi->ubi_num && unv_c->vol_id == vi->vol_id) {
++			unv = unv_c;
++			break;
++		}
++
++	if (!unv) {
++		mutex_unlock(&devices_mutex);
++		return;
++	}
++
++	list_del(&unv->list);
++	mutex_unlock(&devices_mutex);
++	nvmem_unregister(unv->nvmem);
++	kfree(unv);
++}
++
++/**
++ * nvmem_notify - UBI notification handler.
++ * @nb: registered notifier block
++ * @l: notification type
++ * @ns_ptr: pointer to the &struct ubi_notification object
++ */
++static int nvmem_notify(struct notifier_block *nb, unsigned long l,
++			 void *ns_ptr)
++{
++	struct ubi_notification *nt = ns_ptr;
++
++	switch (l) {
++	case UBI_VOLUME_RESIZED:
++		ubi_nvmem_remove(&nt->vi);
++		fallthrough;
++	case UBI_VOLUME_ADDED:
++		ubi_nvmem_add(&nt->vi);
++		break;
++	case UBI_VOLUME_SHUTDOWN:
++		ubi_nvmem_remove(&nt->vi);
++		break;
++	default:
++		break;
++	}
++	return NOTIFY_OK;
++}
++
++static struct notifier_block nvmem_notifier = {
++	.notifier_call = nvmem_notify,
++};
++
++static int __init ubi_nvmem_init(void)
++{
++	return ubi_register_volume_notifier(&nvmem_notifier, 0);
++}
++
++static void __exit ubi_nvmem_exit(void)
++{
++	struct ubi_nvmem *unv, *tmp;
++
++	mutex_lock(&devices_mutex);
++	list_for_each_entry_safe(unv, tmp, &nvmem_devices, list) {
++		nvmem_unregister(unv->nvmem);
++		list_del(&unv->list);
++		kfree(unv);
++	}
++	mutex_unlock(&devices_mutex);
++
++	ubi_unregister_volume_notifier(&nvmem_notifier);
++}
++
++module_init(ubi_nvmem_init);
++module_exit(ubi_nvmem_exit);
++MODULE_DESCRIPTION("NVMEM layer over UBI volumes");
++MODULE_AUTHOR("Daniel Golle");
++MODULE_LICENSE("GPL");
diff --git a/target/linux/generic/pending-6.1/450-08-dt-bindings-block-add-basic-bindings-for-block-devic.patch b/target/linux/generic/pending-6.1/450-08-dt-bindings-block-add-basic-bindings-for-block-devic.patch
new file mode 100644
index 00000000000000..d0727faf3dc195
--- /dev/null
+++ b/target/linux/generic/pending-6.1/450-08-dt-bindings-block-add-basic-bindings-for-block-devic.patch
@@ -0,0 +1,120 @@
+From 9ffc1d7d73609a89eb264d6066340f8b7b3b0ebe Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 7 Aug 2023 21:19:45 +0100
+Subject: [PATCH 08/15] dt-bindings: block: add basic bindings for block
+ devices
+
+Add bindings for block devices which are used to allow referencing
+nvmem bits on them.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ .../bindings/block/block-device.yaml          | 22 ++++++++
+ .../devicetree/bindings/block/partition.yaml  | 50 +++++++++++++++++++
+ .../devicetree/bindings/block/partitions.yaml | 20 ++++++++
+ 3 files changed, 92 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/block/block-device.yaml
+ create mode 100644 Documentation/devicetree/bindings/block/partition.yaml
+ create mode 100644 Documentation/devicetree/bindings/block/partitions.yaml
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/block/block-device.yaml
+@@ -0,0 +1,22 @@
++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/block/block-device.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: block storage device
++
++description: |
++  This binding is generic and describes a block-oriented storage device.
++
++maintainers:
++  - Daniel Golle <daniel@makrotopia.org>
++
++properties:
++  partitions:
++    $ref: /schemas/block/partitions.yaml
++
++  nvmem-layout:
++    $ref: /schemas/nvmem/layouts/nvmem-layout.yaml#
++
++unevaluatedProperties: false
+--- /dev/null
++++ b/Documentation/devicetree/bindings/block/partition.yaml
+@@ -0,0 +1,50 @@
++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/block/partition.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Partition on a block device
++
++description: |
++  This binding describes a partition on a block device.
++  Partitions may be matched by a combination of partition number, name,
++  and UUID.
++
++maintainers:
++  - Daniel Golle <daniel@makrotopia.org>
++
++properties:
++  $nodename:
++    pattern: '^block-partition-.+$'
++
++  partnum:
++    description:
++      Matches partition by number if present.
++
++  partname:
++    "$ref": "/schemas/types.yaml#/definitions/string"
++    description:
++      Matches partition by PARTNAME if present.
++
++  uuid:
++    "$ref": "/schemas/types.yaml#/definitions/string"
++    description:
++      Matches partition by PARTUUID if present.
++
++  nvmem-layout:
++    $ref: /schemas/nvmem/layouts/nvmem-layout.yaml#
++    description:
++      This container may reference an NVMEM layout parser.
++
++anyOf:
++  - required:
++    - partnum
++
++  - required:
++    - partname
++
++  - required:
++    - uuid
++
++unevaluatedProperties: false
+--- /dev/null
++++ b/Documentation/devicetree/bindings/block/partitions.yaml
+@@ -0,0 +1,20 @@
++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/block/partitions.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Partitions on block devices
++
++description: |
++  This binding is generic and describes the content of the partitions container
++  node.
++
++maintainers:
++  - Daniel Golle <daniel@makrotopia.org>
++
++patternProperties:
++  "^block-partition-.+$":
++    $ref: partition.yaml
++
++unevaluatedProperties: false
diff --git a/target/linux/generic/pending-6.1/450-09-block-partitions-populate-fwnode.patch b/target/linux/generic/pending-6.1/450-09-block-partitions-populate-fwnode.patch
new file mode 100644
index 00000000000000..8aa5cba678897a
--- /dev/null
+++ b/target/linux/generic/pending-6.1/450-09-block-partitions-populate-fwnode.patch
@@ -0,0 +1,77 @@
+From 614f4f6fdda09e30ecf7ef6c8091579db15018cb Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Fri, 21 Jul 2023 17:51:03 +0100
+Subject: [PATCH 09/15] block: partitions: populate fwnode
+
+Let block partitions to be represented by a firmware node and hence
+allow them to being referenced e.g. for use with blk-nvmem.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ block/partitions/core.c | 41 +++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 41 insertions(+)
+
+--- a/block/partitions/core.c
++++ b/block/partitions/core.c
+@@ -10,6 +10,8 @@
+ #include <linux/ctype.h>
+ #include <linux/vmalloc.h>
+ #include <linux/raid/detect.h>
++#include <linux/property.h>
++
+ #include "check.h"
+ 
+ static int (*check_part[])(struct parsed_partitions *) = {
+@@ -298,6 +300,43 @@ static ssize_t whole_disk_show(struct de
+ }
+ static DEVICE_ATTR(whole_disk, 0444, whole_disk_show, NULL);
+ 
++static struct fwnode_handle *find_partition_fwnode(struct block_device *bdev)
++{
++	struct fwnode_handle *fw_parts, *fw_part;
++	struct device *ddev = disk_to_dev(bdev->bd_disk);
++	const char *partname, *uuid;
++	u32 partno;
++
++	fw_parts = device_get_named_child_node(ddev, "partitions");
++	if (!fw_parts)
++		fw_parts = device_get_named_child_node(ddev->parent, "partitions");
++
++	if (!fw_parts)
++		return NULL;
++
++	fwnode_for_each_child_node(fw_parts, fw_part) {
++		if (!fwnode_property_read_string(fw_part, "uuid", &uuid) &&
++		    (!bdev->bd_meta_info || strncmp(uuid,
++						    bdev->bd_meta_info->uuid,
++						    PARTITION_META_INFO_UUIDLTH)))
++			continue;
++
++		if (!fwnode_property_read_string(fw_part, "partname", &partname) &&
++		    (!bdev->bd_meta_info || strncmp(partname,
++						    bdev->bd_meta_info->volname,
++						    PARTITION_META_INFO_VOLNAMELTH)))
++			continue;
++
++		if (!fwnode_property_read_u32(fw_part, "partno", &partno) &&
++		    bdev->bd_partno != partno)
++			continue;
++
++		return fw_part;
++	}
++
++	return NULL;
++}
++
+ /*
+  * Must be called either with open_mutex held, before a disk can be opened or
+  * after all disk users are gone.
+@@ -380,6 +419,8 @@ static struct block_device *add_partitio
+ 			goto out_put;
+ 	}
+ 
++	device_set_node(pdev, find_partition_fwnode(bdev));
++
+ 	/* delay uevent until 'holders' subdir is created */
+ 	dev_set_uevent_suppress(pdev, 1);
+ 	err = device_add(pdev);
diff --git a/target/linux/generic/pending-6.1/450-10-block-add-new-genhd-flag-GENHD_FL_NVMEM.patch b/target/linux/generic/pending-6.1/450-10-block-add-new-genhd-flag-GENHD_FL_NVMEM.patch
new file mode 100644
index 00000000000000..4cbec14f5c97f6
--- /dev/null
+++ b/target/linux/generic/pending-6.1/450-10-block-add-new-genhd-flag-GENHD_FL_NVMEM.patch
@@ -0,0 +1,29 @@
+From 65f3ff9672ccd5ee78937047e7a2fc696eee1c8f Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Thu, 13 Jul 2023 04:07:16 +0100
+Subject: [PATCH 10/15] block: add new genhd flag GENHD_FL_NVMEM
+
+Add new flag to destinguish block devices which may act as an NVMEM
+provider.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ include/linux/blkdev.h | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/include/linux/blkdev.h
++++ b/include/linux/blkdev.h
+@@ -87,11 +87,13 @@ struct partition_meta_info {
+  * ``GENHD_FL_NO_PART``: partition support is disabled.  The kernel will not
+  * scan for partitions from add_disk, and users can't add partitions manually.
+  *
++ * ``GENHD_FL_NVMEM``: the block device should be considered as NVMEM provider.
+  */
+ enum {
+ 	GENHD_FL_REMOVABLE			= 1 << 0,
+ 	GENHD_FL_HIDDEN				= 1 << 1,
+ 	GENHD_FL_NO_PART			= 1 << 2,
++	GENHD_FL_NVMEM				= 1 << 3,
+ };
+ 
+ enum {
diff --git a/target/linux/generic/pending-6.1/450-11-block-implement-NVMEM-provider.patch b/target/linux/generic/pending-6.1/450-11-block-implement-NVMEM-provider.patch
new file mode 100644
index 00000000000000..e18b0c3a5c7887
--- /dev/null
+++ b/target/linux/generic/pending-6.1/450-11-block-implement-NVMEM-provider.patch
@@ -0,0 +1,235 @@
+From b9936aa8a3775c2027f655d91a206d0e6e1c7ec0 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Tue, 11 Jul 2023 00:17:31 +0100
+Subject: [PATCH 11/15] block: implement NVMEM provider
+
+On embedded devices using an eMMC it is common that one or more partitions
+on the eMMC are used to store MAC addresses and Wi-Fi calibration EEPROM
+data. Allow referencing the partition in device tree for the kernel and
+Wi-Fi drivers accessing it via the NVMEM layer.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ block/Kconfig     |   9 +++
+ block/Makefile    |   1 +
+ block/blk-nvmem.c | 186 ++++++++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 196 insertions(+)
+ create mode 100644 block/blk-nvmem.c
+
+--- a/block/Kconfig
++++ b/block/Kconfig
+@@ -203,6 +203,15 @@ config BLK_INLINE_ENCRYPTION_FALLBACK
+ 	  by falling back to the kernel crypto API when inline
+ 	  encryption hardware is not present.
+ 
++config BLK_NVMEM
++	bool "Block device NVMEM provider"
++	depends on OF
++	depends on NVMEM
++	help
++	  Allow block devices (or partitions) to act as NVMEM prodivers,
++	  typically used with eMMC to store MAC addresses or Wi-Fi
++	  calibration data on embedded devices.
++
+ source "block/partitions/Kconfig"
+ 
+ config BLOCK_COMPAT
+--- a/block/Makefile
++++ b/block/Makefile
+@@ -35,6 +35,7 @@ obj-$(CONFIG_BLK_DEV_ZONED)	+= blk-zoned
+ obj-$(CONFIG_BLK_WBT)		+= blk-wbt.o
+ obj-$(CONFIG_BLK_DEBUG_FS)	+= blk-mq-debugfs.o
+ obj-$(CONFIG_BLK_DEBUG_FS_ZONED)+= blk-mq-debugfs-zoned.o
++obj-$(CONFIG_BLK_NVMEM)		+= blk-nvmem.o
+ obj-$(CONFIG_BLK_SED_OPAL)	+= sed-opal.o
+ obj-$(CONFIG_BLK_PM)		+= blk-pm.o
+ obj-$(CONFIG_BLK_INLINE_ENCRYPTION)	+= blk-crypto.o blk-crypto-profile.o \
+--- /dev/null
++++ b/block/blk-nvmem.c
+@@ -0,0 +1,186 @@
++// SPDX-License-Identifier: GPL-2.0-or-later
++/*
++ * block device NVMEM provider
++ *
++ * Copyright (c) 2023 Daniel Golle <daniel@makrotopia.org>
++ *
++ * Useful on devices using a partition on an eMMC for MAC addresses or
++ * Wi-Fi calibration EEPROM data.
++ */
++
++#include "blk.h"
++#include <linux/nvmem-provider.h>
++#include <linux/of.h>
++#include <linux/pagemap.h>
++#include <linux/property.h>
++
++/* List of all NVMEM devices */
++static LIST_HEAD(nvmem_devices);
++static DEFINE_MUTEX(devices_mutex);
++
++struct blk_nvmem {
++	struct nvmem_device *nvmem;
++	struct block_device *bdev;
++	struct list_head list;
++};
++
++static int blk_nvmem_reg_read(void *priv, unsigned int from,
++			      void *val, size_t bytes)
++{
++	unsigned long offs = from & ~PAGE_MASK, to_read;
++	pgoff_t f_index = from >> PAGE_SHIFT;
++	struct address_space *mapping;
++	struct blk_nvmem *bnv = priv;
++	size_t bytes_left = bytes;
++	struct folio *folio;
++	void *p;
++	int ret;
++
++	if (!bnv->bdev)
++		return -ENODEV;
++
++	if (!bnv->bdev->bd_disk)
++		return -EINVAL;
++
++	if (!bnv->bdev->bd_disk->fops)
++		return -EIO;
++
++	if (!bnv->bdev->bd_disk->fops->open)
++		return -EIO;
++
++	ret = bnv->bdev->bd_disk->fops->open(bnv->bdev, FMODE_READ);
++	if (ret)
++		return ret;
++
++	mapping = bnv->bdev->bd_inode->i_mapping;
++
++	while (bytes_left) {
++		folio = read_mapping_folio(mapping, f_index++, NULL);
++		if (IS_ERR(folio)) {
++			ret = PTR_ERR(folio);
++			goto err_release_bdev;
++		}
++		to_read = min_t(unsigned long, bytes_left, PAGE_SIZE - offs);
++		p = folio_address(folio) + offset_in_folio(folio, offs);
++		memcpy(val, p, to_read);
++		offs = 0;
++		bytes_left -= to_read;
++		val += to_read;
++		folio_put(folio);
++	}
++
++err_release_bdev:
++	bnv->bdev->bd_disk->fops->release(bnv->bdev->bd_disk, FMODE_READ);
++
++	return ret;
++}
++
++static int blk_nvmem_register(struct device *dev, struct class_interface *iface)
++{
++	struct device_node *np = dev_of_node(dev);
++	struct block_device *bdev = dev_to_bdev(dev);
++	struct nvmem_config config = {};
++	struct blk_nvmem *bnv;
++
++	/* skip devices which do not have a device tree node */
++	if (!np)
++		return 0;
++
++	/* skip devices without an nvmem layout defined */
++	if (!of_get_child_by_name(np, "nvmem-layout"))
++		return 0;
++
++	/*
++	 * skip devices which don't have GENHD_FL_NVMEM set
++	 *
++	 * This flag is used for mtdblock and ubiblock devices because
++	 * both, MTD and UBI already implement their own NVMEM provider.
++	 * To avoid registering multiple NVMEM providers for the same
++	 * device node, don't register the block NVMEM provider for them.
++	 */
++	if (!(bdev->bd_disk->flags & GENHD_FL_NVMEM))
++		return 0;
++
++	/*
++	 * skip block device too large to be represented as NVMEM devices
++	 * which are using an 'int' as address
++	 */
++	if (bdev_nr_bytes(bdev) > INT_MAX)
++		return -EFBIG;
++
++	bnv = kzalloc(sizeof(struct blk_nvmem), GFP_KERNEL);
++	if (!bnv)
++		return -ENOMEM;
++
++	config.id = NVMEM_DEVID_NONE;
++	config.dev = &bdev->bd_device;
++	config.name = dev_name(&bdev->bd_device);
++	config.owner = THIS_MODULE;
++	config.priv = bnv;
++	config.reg_read = blk_nvmem_reg_read;
++	config.size = bdev_nr_bytes(bdev);
++	config.word_size = 1;
++	config.stride = 1;
++	config.read_only = true;
++	config.root_only = true;
++	config.ignore_wp = true;
++	config.of_node = to_of_node(dev->fwnode);
++
++	bnv->bdev = bdev;
++	bnv->nvmem = nvmem_register(&config);
++	if (IS_ERR(bnv->nvmem)) {
++		dev_err_probe(&bdev->bd_device, PTR_ERR(bnv->nvmem),
++			      "Failed to register NVMEM device\n");
++
++		kfree(bnv);
++		return PTR_ERR(bnv->nvmem);
++	}
++
++	mutex_lock(&devices_mutex);
++	list_add_tail(&bnv->list, &nvmem_devices);
++	mutex_unlock(&devices_mutex);
++
++	return 0;
++}
++
++static void blk_nvmem_unregister(struct device *dev, struct class_interface *iface)
++{
++	struct block_device *bdev = dev_to_bdev(dev);
++	struct blk_nvmem *bnv_c, *bnv = NULL;
++
++	mutex_lock(&devices_mutex);
++	list_for_each_entry(bnv_c, &nvmem_devices, list) {
++		if (bnv_c->bdev == bdev) {
++			bnv = bnv_c;
++			break;
++		}
++	}
++
++	if (!bnv) {
++		mutex_unlock(&devices_mutex);
++		return;
++	}
++
++	list_del(&bnv->list);
++	mutex_unlock(&devices_mutex);
++	nvmem_unregister(bnv->nvmem);
++	kfree(bnv);
++}
++
++static struct class_interface blk_nvmem_bus_interface __refdata = {
++	.class = &block_class,
++	.add_dev = &blk_nvmem_register,
++	.remove_dev = &blk_nvmem_unregister,
++};
++
++static int __init blk_nvmem_init(void)
++{
++	int ret;
++
++	ret = class_interface_register(&blk_nvmem_bus_interface);
++	if (ret)
++		return ret;
++
++	return 0;
++}
++device_initcall(blk_nvmem_init);
diff --git a/target/linux/generic/pending-6.1/450-12-dt-bindings-mmc-mmc-card-add-block-device-nodes.patch b/target/linux/generic/pending-6.1/450-12-dt-bindings-mmc-mmc-card-add-block-device-nodes.patch
new file mode 100644
index 00000000000000..77c9bf91a54d9e
--- /dev/null
+++ b/target/linux/generic/pending-6.1/450-12-dt-bindings-mmc-mmc-card-add-block-device-nodes.patch
@@ -0,0 +1,74 @@
+From 86864bf8f40e84dc881c197ef470a88668329dbf Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 7 Aug 2023 21:21:45 +0100
+Subject: [PATCH 12/15] dt-bindings: mmc: mmc-card: add block device nodes
+
+Add nodes representing the block devices exposed by an MMC device
+including an example involving nvmem-cells.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ .../devicetree/bindings/mmc/mmc-card.yaml     | 45 +++++++++++++++++++
+ 1 file changed, 45 insertions(+)
+
+--- a/Documentation/devicetree/bindings/mmc/mmc-card.yaml
++++ b/Documentation/devicetree/bindings/mmc/mmc-card.yaml
+@@ -26,6 +26,18 @@ properties:
+       Use this to indicate that the mmc-card has a broken hpi
+       implementation, and that hpi should not be used.
+ 
++  block:
++    $ref: /schemas/block/block-device.yaml#
++    description:
++      Represents the block storage provided by an SD card or the
++      main hardware partition of an eMMC.
++
++patternProperties:
++  '^boot[0-9]+':
++    $ref: /schemas/block/block-device.yaml#
++    description:
++      Represents a boot hardware partition on an eMMC.
++
+ required:
+   - compatible
+   - reg
+@@ -42,6 +54,39 @@ examples:
+             compatible = "mmc-card";
+             reg = <0>;
+             broken-hpi;
++
++            block {
++                partitions {
++                    cal_data: block-partition-rf {
++                        partnum = <3>;
++                        partname = "rf";
++
++                        nvmem-layout {
++                            compatible = "fixed-layout";
++                            #address-cells = <1>;
++                            #size-cells = <1>;
++
++                            eeprom@0 {
++                                reg = <0x0 0x1000>;
++                            };
++                        };
++                    };
++                };
++            };
++
++            boot1 {
++                nvmem-layout {
++                    compatible = "fixed-layout";
++                    #address-cells = <1>;
++                    #size-cells = <1>;
++
++                    macaddr: macaddr@a {
++                        compatible = "mac-base";
++                        reg = <0xa 0x6>;
++                        #nvmem-cell-cells = <1>;
++                    };
++                };
++            };
+         };
+     };
+ 
diff --git a/target/linux/generic/pending-6.1/450-13-mmc-core-set-card-fwnode_handle.patch b/target/linux/generic/pending-6.1/450-13-mmc-core-set-card-fwnode_handle.patch
new file mode 100644
index 00000000000000..fada280437971f
--- /dev/null
+++ b/target/linux/generic/pending-6.1/450-13-mmc-core-set-card-fwnode_handle.patch
@@ -0,0 +1,23 @@
+From 644942a31719de674e2aa68f83d66bd8ae7e4fb7 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Thu, 13 Jul 2023 04:12:21 +0100
+Subject: [PATCH 13/15] mmc: core: set card fwnode_handle
+
+Set fwnode in case it isn't set yet and of_node is present.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/mmc/core/bus.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/mmc/core/bus.c
++++ b/drivers/mmc/core/bus.c
+@@ -363,6 +363,8 @@ int mmc_add_card(struct mmc_card *card)
+ 	mmc_add_card_debugfs(card);
+ #endif
+ 	card->dev.of_node = mmc_of_find_child_device(card->host, 0);
++	if (card->dev.of_node && !card->dev.fwnode)
++		card->dev.fwnode = &card->dev.of_node->fwnode;
+ 
+ 	device_enable_async_suspend(&card->dev);
+ 
diff --git a/target/linux/generic/pending-6.1/450-14-mmc-block-set-fwnode-of-disk-devices.patch b/target/linux/generic/pending-6.1/450-14-mmc-block-set-fwnode-of-disk-devices.patch
new file mode 100644
index 00000000000000..a9e53f115530e5
--- /dev/null
+++ b/target/linux/generic/pending-6.1/450-14-mmc-block-set-fwnode-of-disk-devices.patch
@@ -0,0 +1,39 @@
+From d9143f86330dd038fc48878558dd287ceee5d3d4 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Thu, 13 Jul 2023 04:13:04 +0100
+Subject: [PATCH 14/15] mmc: block: set fwnode of disk devices
+
+Set fwnode of disk devices to 'block', 'boot0' and 'boot1' subnodes of
+the mmc-card. This is done in preparation for having the eMMC act as
+NVMEM provider.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/mmc/core/block.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/drivers/mmc/core/block.c
++++ b/drivers/mmc/core/block.c
+@@ -2484,6 +2484,8 @@ static struct mmc_blk_data *mmc_blk_allo
+ 					      int area_type,
+ 					      unsigned int part_type)
+ {
++	struct fwnode_handle *fwnode;
++	struct device *ddev;
+ 	struct mmc_blk_data *md;
+ 	int devidx, ret;
+ 	char cap_str[10];
+@@ -2580,6 +2582,13 @@ static struct mmc_blk_data *mmc_blk_allo
+ 
+ 	blk_queue_write_cache(md->queue.queue, cache_enabled, fua_enabled);
+ 
++	ddev = disk_to_dev(md->disk);
++	fwnode = device_get_named_child_node(subname ? md->parent->parent :
++						       md->parent,
++					     subname ? subname : "block");
++	if (fwnode)
++		device_set_node(ddev, fwnode);
++
+ 	string_get_size((u64)size, 512, STRING_UNITS_2,
+ 			cap_str, sizeof(cap_str));
+ 	pr_info("%s: %s %s %s %s\n",
diff --git a/target/linux/generic/pending-6.1/450-15-mmc-block-set-GENHD_FL_NVMEM.patch b/target/linux/generic/pending-6.1/450-15-mmc-block-set-GENHD_FL_NVMEM.patch
new file mode 100644
index 00000000000000..d76e7b2fe59ad0
--- /dev/null
+++ b/target/linux/generic/pending-6.1/450-15-mmc-block-set-GENHD_FL_NVMEM.patch
@@ -0,0 +1,22 @@
+From 322035ab2b0113d98b6c0ea788d971e0df2952a4 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Thu, 20 Jul 2023 17:36:44 +0100
+Subject: [PATCH 15/15] mmc: block: set GENHD_FL_NVMEM
+
+Set flag to consider MMC block devices as NVMEM providers.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/mmc/core/block.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/mmc/core/block.c
++++ b/drivers/mmc/core/block.c
+@@ -2538,6 +2538,7 @@ static struct mmc_blk_data *mmc_blk_allo
+ 	md->disk->major	= MMC_BLOCK_MAJOR;
+ 	md->disk->minors = perdev_minors;
+ 	md->disk->first_minor = devidx * perdev_minors;
++	md->disk->flags = GENHD_FL_NVMEM;
+ 	md->disk->fops = &mmc_bdops;
+ 	md->disk->private_data = md;
+ 	md->parent = parent;
diff --git a/target/linux/generic/pending-6.1/490-ubi-auto-attach-mtd-device-named-ubi-or-data-on-boot.patch b/target/linux/generic/pending-6.1/490-ubi-auto-attach-mtd-device-named-ubi-or-data-on-boot.patch
index 765eecd9d713ff..2eccb9d3bbb513 100644
--- a/target/linux/generic/pending-6.1/490-ubi-auto-attach-mtd-device-named-ubi-or-data-on-boot.patch
+++ b/target/linux/generic/pending-6.1/490-ubi-auto-attach-mtd-device-named-ubi-or-data-on-boot.patch
@@ -8,10 +8,11 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 
 --- a/drivers/mtd/ubi/build.c
 +++ b/drivers/mtd/ubi/build.c
-@@ -1212,6 +1212,73 @@ static struct mtd_info * __init open_mtd
- 	return mtd;
- }
+@@ -1263,6 +1263,74 @@ static struct mtd_notifier ubi_mtd_notif
+ 	.remove = ubi_notify_remove,
+ };
  
++
 +/*
 + * This function tries attaching mtd partitions named either "ubi" or "data"
 + * during boot.
@@ -79,10 +80,10 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 +	put_mtd_device(mtd);
 +}
 +
- static int __init ubi_init(void)
+ static int __init ubi_init_attach(void)
  {
  	int err, i, k;
-@@ -1296,6 +1363,12 @@ static int __init ubi_init(void)
+@@ -1313,6 +1381,12 @@ static int __init ubi_init_attach(void)
  		}
  	}
  
@@ -92,6 +93,6 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 +	    !ubi_is_module() && !mtd_devs)
 +		ubi_auto_attach();
 +
- 	err = ubiblock_init();
- 	if (err) {
- 		pr_err("UBI error: block: cannot initialize, error %d\n", err);
+ 	return 0;
+ 
+ out_detach:
diff --git a/target/linux/generic/pending-6.1/491-ubi-auto-create-ubiblock-device-for-rootfs.patch b/target/linux/generic/pending-6.1/491-ubi-auto-create-ubiblock-device-for-rootfs.patch
index 17e8d8bedb6c16..a43da2a57259a9 100644
--- a/target/linux/generic/pending-6.1/491-ubi-auto-create-ubiblock-device-for-rootfs.patch
+++ b/target/linux/generic/pending-6.1/491-ubi-auto-create-ubiblock-device-for-rootfs.patch
@@ -8,8 +8,8 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 
 --- a/drivers/mtd/ubi/block.c
 +++ b/drivers/mtd/ubi/block.c
-@@ -653,6 +653,47 @@ static void __init ubiblock_create_from_
- 	}
+@@ -644,10 +644,47 @@ match_volume_desc(struct ubi_volume_info
+ 	return true;
  }
  
 +#define UBIFS_NODE_MAGIC  0x06101831
@@ -24,46 +24,54 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 +	return magic == UBIFS_NODE_MAGIC;
 +}
 +
-+static void __init ubiblock_create_auto_rootfs(void)
++static void __init ubiblock_create_auto_rootfs(struct ubi_volume_info *vi)
 +{
-+	int ubi_num, ret, is_ubifs;
++	int ret, is_ubifs;
 +	struct ubi_volume_desc *desc;
-+	struct ubi_volume_info vi;
 +
-+	for (ubi_num = 0; ubi_num < UBI_MAX_DEVICES; ubi_num++) {
-+		desc = ubi_open_volume_nm(ubi_num, "rootfs", UBI_READONLY);
-+		if (IS_ERR(desc))
-+			desc = ubi_open_volume_nm(ubi_num, "fit", UBI_READONLY);;
++	if (strcmp(vi->name, "rootfs") &&
++	    strcmp(vi->name, "fit"))
++		return;
 +
-+		if (IS_ERR(desc))
-+			continue;
++	desc = ubi_open_volume(vi->ubi_num, vi->vol_id, UBI_READONLY);
++	if (IS_ERR(desc))
++		return;
 +
-+		ubi_get_volume_info(desc, &vi);
-+		is_ubifs = ubi_vol_is_ubifs(desc);
-+		ubi_close_volume(desc);
-+		if (is_ubifs)
-+			break;
++	is_ubifs = ubi_vol_is_ubifs(desc);
++	ubi_close_volume(desc);
++	if (is_ubifs)
++		return;
 +
-+		ret = ubiblock_create(&vi);
-+		if (ret)
-+			pr_err("UBI error: block: can't add '%s' volume, err=%d\n",
-+				vi.name, ret);
-+		/* always break if we get here */
-+		break;
-+	}
++	ret = ubiblock_create(vi);
++	if (ret)
++		pr_err("UBI error: block: can't add '%s' volume, err=%d\n",
++			vi->name, ret);
 +}
 +
- static void ubiblock_remove_all(void)
+ static void
+ ubiblock_create_from_param(struct ubi_volume_info *vi)
  {
- 	struct ubiblock *next;
-@@ -685,6 +726,10 @@ int __init ubiblock_init(void)
- 	 */
- 	ubiblock_create_from_param();
+ 	int i, ret = 0;
++	bool got_param = false;
+ 	struct ubiblock_param *p;
  
-+	/* auto-attach "rootfs" volume if existing and non-ubifs */
-+	if (IS_ENABLED(CONFIG_MTD_ROOTFS_ROOT_DEV))
-+		ubiblock_create_auto_rootfs();
-+
  	/*
- 	 * Block devices are only created upon user requests, so we ignore
- 	 * existing volumes.
+@@ -660,6 +697,7 @@ ubiblock_create_from_param(struct ubi_vo
+ 		if (!match_volume_desc(vi, p->name, p->ubi_num, p->vol_id))
+ 			continue;
+ 
++		got_param = true;
+ 		ret = ubiblock_create(vi);
+ 		if (ret) {
+ 			pr_err(
+@@ -668,6 +706,10 @@ ubiblock_create_from_param(struct ubi_vo
+ 		}
+ 		break;
+ 	}
++
++	/* auto-attach "rootfs" volume if existing and non-ubifs */
++	if (!got_param && IS_ENABLED(CONFIG_MTD_ROOTFS_ROOT_DEV))
++		ubiblock_create_auto_rootfs(vi);
+ }
+ 
+ static int ubiblock_notify(struct notifier_block *nb,
diff --git a/target/linux/generic/pending-6.1/493-ubi-set-ROOT_DEV-to-ubiblock-rootfs-if-unset.patch b/target/linux/generic/pending-6.1/493-ubi-set-ROOT_DEV-to-ubiblock-rootfs-if-unset.patch
index e3493ef19ef8ca..5357c7e15d7b18 100644
--- a/target/linux/generic/pending-6.1/493-ubi-set-ROOT_DEV-to-ubiblock-rootfs-if-unset.patch
+++ b/target/linux/generic/pending-6.1/493-ubi-set-ROOT_DEV-to-ubiblock-rootfs-if-unset.patch
@@ -8,7 +8,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 
 --- a/drivers/mtd/ubi/block.c
 +++ b/drivers/mtd/ubi/block.c
-@@ -42,6 +42,7 @@
+@@ -43,6 +43,7 @@
  #include <linux/scatterlist.h>
  #include <linux/idr.h>
  #include <asm/div64.h>
@@ -16,7 +16,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  
  #include "ubi-media.h"
  #include "ubi.h"
-@@ -459,6 +460,15 @@ int ubiblock_create(struct ubi_volume_in
+@@ -460,6 +461,15 @@ int ubiblock_create(struct ubi_volume_in
  	dev_info(disk_to_dev(dev->gd), "created from ubi%d:%d(%s)",
  		 dev->ubi_num, dev->vol_id, vi->name);
  	mutex_unlock(&devices_mutex);
diff --git a/target/linux/generic/pending-6.1/494-mtd-ubi-add-EOF-marker-support.patch b/target/linux/generic/pending-6.1/494-mtd-ubi-add-EOF-marker-support.patch
index 413431755f1d2c..fc481462212cea 100644
--- a/target/linux/generic/pending-6.1/494-mtd-ubi-add-EOF-marker-support.patch
+++ b/target/linux/generic/pending-6.1/494-mtd-ubi-add-EOF-marker-support.patch
@@ -50,7 +50,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
  		break;
 --- a/drivers/mtd/ubi/ubi.h
 +++ b/drivers/mtd/ubi/ubi.h
-@@ -778,6 +778,7 @@ struct ubi_attach_info {
+@@ -780,6 +780,7 @@ struct ubi_attach_info {
  	int mean_ec;
  	uint64_t ec_sum;
  	int ec_count;
diff --git a/target/linux/generic/pending-6.1/510-block-add-uImage.FIT-subimage-block-driver.patch b/target/linux/generic/pending-6.1/510-block-add-uImage.FIT-subimage-block-driver.patch
new file mode 100644
index 00000000000000..54234caf949651
--- /dev/null
+++ b/target/linux/generic/pending-6.1/510-block-add-uImage.FIT-subimage-block-driver.patch
@@ -0,0 +1,733 @@
+From 6173a065cb395d4a9528c4e49810af127db68141 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Wed, 16 Nov 2022 12:49:52 +0000
+Subject: [PATCH 1/2] block: add uImage.FIT subimage block driver
+
+Add a small block driver which exposes filesystem sub-images contained
+in U-Boot uImage.FIT images as block devices.
+
+The uImage.FIT image has to be stored directly on a block device or
+partition, MTD device or partition, or UBI volume.
+
+The driver is intended for systems using the U-Boot bootloader and
+uses the root device hint left by the bootloader (or the user) in
+the 'chosen' section of the device-tree.
+
+Example:
+/dts-v1/;
+/ {
+        chosen {
+                rootdisk = <&mmc0_part3>;
+        };
+};
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ MAINTAINERS                 |   6 +
+ drivers/block/Kconfig       |  12 +
+ drivers/block/Makefile      |   2 +
+ drivers/block/fitblk.c      | 658 ++++++++++++++++++++++++++++++++++++
+ drivers/block/open          |   4 +
+ include/uapi/linux/fitblk.h |  10 +
+ 6 files changed, 692 insertions(+)
+ create mode 100644 drivers/block/fitblk.c
+ create mode 100644 drivers/block/open
+ create mode 100644 include/uapi/linux/fitblk.h
+
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -21052,6 +21052,12 @@ F:	Documentation/filesystems/ubifs-authe
+ F:	Documentation/filesystems/ubifs.rst
+ F:	fs/ubifs/
+ 
++U-BOOT UIMAGE.FIT PARSER
++M:	Daniel Golle <daniel@makrotopia.org>
++L:	linux-block@vger.kernel.org
++S:	Maintained
++F:	drivers/block/fitblk.c
++
+ UBLK USERSPACE BLOCK DRIVER
+ M:	Ming Lei <ming.lei@redhat.com>
+ L:	linux-block@vger.kernel.org
+--- a/drivers/block/Kconfig
++++ b/drivers/block/Kconfig
+@@ -383,6 +383,18 @@ config VIRTIO_BLK
+ 	  This is the virtual block driver for virtio.  It can be used with
+           QEMU based VMMs (like KVM or Xen).  Say Y or M.
+ 
++config UIMAGE_FIT_BLK
++	bool "uImage.FIT block driver"
++	help
++	  This driver allows using filesystems contained in uImage.FIT images
++	  by mapping them as block devices.
++
++	  It can currently not be built as a module due to libfdt symbols not
++	  being exported.
++
++	  Say Y if you want to mount filesystems sub-images of a uImage.FIT
++	  stored in a block device partition, mtdblock or ubiblock device.
++
+ config BLK_DEV_RBD
+ 	tristate "Rados block device (RBD)"
+ 	depends on INET && BLOCK
+--- a/drivers/block/Makefile
++++ b/drivers/block/Makefile
+@@ -39,4 +39,6 @@ obj-$(CONFIG_BLK_DEV_NULL_BLK)	+= null_b
+ 
+ obj-$(CONFIG_BLK_DEV_UBLK)			+= ublk_drv.o
+ 
++obj-$(CONFIG_UIMAGE_FIT_BLK)	+= fitblk.o
++
+ swim_mod-y	:= swim.o swim_asm.o
+--- /dev/null
++++ b/drivers/block/fitblk.c
+@@ -0,0 +1,636 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * uImage.FIT virtual block device driver.
++ *
++ * Copyright (C) 2023 Daniel Golle
++ * Copyright (C) 2007 Nick Piggin
++ * Copyright (C) 2007 Novell Inc.
++ *
++ * Initially derived from drivers/block/brd.c which is in parts derived from
++ * drivers/block/rd.c, and drivers/block/loop.c, copyright of their respective
++ * owners.
++ *
++ * uImage.FIT headers extracted from Das U-Boot
++ *  (C) Copyright 2008 Semihalf
++ *  (C) Copyright 2000-2005
++ *  Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++ */
++
++#include <linux/init.h>
++#include <linux/initrd.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/major.h>
++#include <linux/blkdev.h>
++#include <linux/blkpg.h>
++#include <linux/blk-mq.h>
++#include <linux/ctype.h>
++#include <linux/hdreg.h>
++#include <linux/list.h>
++#include <linux/mutex.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/of_fdt.h>
++#include <linux/pagemap.h>
++#include <linux/platform_device.h>
++#include <linux/property.h>
++#include <linux/refcount.h>
++#include <linux/task_work.h>
++#include <linux/types.h>
++#include <linux/libfdt.h>
++#include <linux/mtd/mtd.h>
++#include <linux/root_dev.h>
++#include <uapi/linux/fitblk.h>
++
++#define FIT_DEVICE_PREFIX	"fit"
++
++/* maximum number of pages used for the uImage.FIT index structure */
++#define FIT_MAX_PAGES		1024
++
++/* minimum free sectors to map as read-write "remainder" volume */
++#define MIN_FREE_SECT		16
++
++/* maximum number of mapped loadables */
++#define MAX_FIT_LOADABLES	16
++
++/* constants for uImage.FIT structrure traversal */
++#define FIT_IMAGES_PATH		"/images"
++#define FIT_CONFS_PATH		"/configurations"
++
++/* hash/signature/key node */
++#define FIT_HASH_NODENAME	"hash"
++#define FIT_ALGO_PROP		"algo"
++#define FIT_VALUE_PROP		"value"
++#define FIT_IGNORE_PROP		"uboot-ignore"
++#define FIT_SIG_NODENAME	"signature"
++#define FIT_KEY_REQUIRED	"required"
++#define FIT_KEY_HINT		"key-name-hint"
++
++/* cipher node */
++#define FIT_CIPHER_NODENAME	"cipher"
++#define FIT_ALGO_PROP		"algo"
++
++/* image node */
++#define FIT_DATA_PROP		"data"
++#define FIT_DATA_POSITION_PROP	"data-position"
++#define FIT_DATA_OFFSET_PROP	"data-offset"
++#define FIT_DATA_SIZE_PROP	"data-size"
++#define FIT_TIMESTAMP_PROP	"timestamp"
++#define FIT_DESC_PROP		"description"
++#define FIT_ARCH_PROP		"arch"
++#define FIT_TYPE_PROP		"type"
++#define FIT_OS_PROP		"os"
++#define FIT_COMP_PROP		"compression"
++#define FIT_ENTRY_PROP		"entry"
++#define FIT_LOAD_PROP		"load"
++
++/* configuration node */
++#define FIT_KERNEL_PROP		"kernel"
++#define FIT_FILESYSTEM_PROP	"filesystem"
++#define FIT_RAMDISK_PROP	"ramdisk"
++#define FIT_FDT_PROP		"fdt"
++#define FIT_LOADABLE_PROP	"loadables"
++#define FIT_DEFAULT_PROP	"default"
++#define FIT_SETUP_PROP		"setup"
++#define FIT_FPGA_PROP		"fpga"
++#define FIT_FIRMWARE_PROP	"firmware"
++#define FIT_STANDALONE_PROP	"standalone"
++
++/* fitblk driver data */
++static const char *_fitblk_claim_ptr = "I belong to fitblk";
++static const char *ubootver;
++struct device_node *rootdisk;
++static struct platform_device *pdev;
++static LIST_HEAD(fitblk_devices);
++static DEFINE_MUTEX(devices_mutex);
++refcount_t num_devs;
++
++struct fitblk {
++	struct platform_device	*pdev;
++	struct block_device	*lower_bdev;
++	sector_t		start_sect;
++	struct gendisk		*disk;
++	struct work_struct	remove_work;
++	struct list_head	list;
++	bool			dead;
++};
++
++static int fitblk_open(struct block_device *bdev, fmode_t mode)
++{
++	struct fitblk *fitblk = bdev->bd_disk->private_data;
++
++	if (fitblk->dead)
++		return -ENOENT;
++
++	return 0;
++}
++
++static void fitblk_release(struct gendisk *disk, fmode_t mode)
++{
++	return;
++}
++
++static void fitblk_submit_bio(struct bio *orig_bio)
++{
++	struct bio *bio = orig_bio;
++	struct fitblk *fitblk = bio->bi_bdev->bd_disk->private_data;
++
++	if (fitblk->dead)
++		return;
++
++	/* mangle bio and re-submit */
++	while (bio) {
++		bio->bi_iter.bi_sector += fitblk->start_sect;
++		bio->bi_bdev = fitblk->lower_bdev;
++		bio = bio->bi_next;
++	}
++	submit_bio(orig_bio);
++}
++
++static void fitblk_remove(struct fitblk *fitblk)
++{
++	blk_mark_disk_dead(fitblk->disk);
++	mutex_lock(&devices_mutex);
++	fitblk->dead = true;
++	list_del(&fitblk->list);
++	mutex_unlock(&devices_mutex);
++
++	schedule_work(&fitblk->remove_work);
++}
++
++static int fitblk_ioctl(struct block_device *bdev, fmode_t mode,
++			unsigned int cmd, unsigned long arg)
++{
++	struct fitblk *fitblk = bdev->bd_disk->private_data;
++
++	if (!capable(CAP_SYS_ADMIN))
++		return -EACCES;
++
++	if (fitblk->dead)
++		return -ENOENT;
++
++	switch (cmd) {
++	case FITBLK_RELEASE:
++		fitblk_remove(fitblk);
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static const struct block_device_operations fitblk_fops = {
++	.owner		= THIS_MODULE,
++	.ioctl		= fitblk_ioctl,
++	.open		= fitblk_open,
++	.release	= fitblk_release,
++	.submit_bio	= fitblk_submit_bio,
++};
++
++static void fitblk_purge(struct work_struct *work)
++{
++	struct fitblk *fitblk = container_of(work, struct fitblk, remove_work);
++
++	//del_gendisk(fitblk->disk); // causes crash, not doing it doesn't matter
++	refcount_dec(&num_devs);
++	platform_device_del(fitblk->pdev);
++	platform_device_put(fitblk->pdev);
++
++	if (refcount_dec_if_one(&num_devs)) {
++		sysfs_remove_link(&pdev->dev.kobj, "lower_dev");
++		blkdev_put(fitblk->lower_bdev, FMODE_READ | FMODE_EXCL);
++	}
++
++	kfree(fitblk);
++}
++
++static int add_fit_subimage_device(struct block_device *lower_bdev,
++				   unsigned int slot, sector_t start_sect,
++				   sector_t nr_sect, bool readonly)
++{
++	struct fitblk *fitblk;
++	struct gendisk *disk;
++	int err;
++
++	mutex_lock(&devices_mutex);
++	if (!refcount_inc_not_zero(&num_devs))
++		return -EBADF;
++
++	fitblk = kzalloc(sizeof(struct fitblk), GFP_KERNEL);
++	if (!fitblk) {
++		err = -ENOMEM;
++		goto out_unlock;
++	}
++
++	fitblk->lower_bdev = lower_bdev;
++	fitblk->start_sect = start_sect;
++	INIT_WORK(&fitblk->remove_work, fitblk_purge);
++
++	disk = blk_alloc_disk(NUMA_NO_NODE);
++	if (!disk) {
++		err = -ENOMEM;
++		goto out_free_fitblk;
++	}
++
++	disk->first_minor = 0;
++	disk->flags = lower_bdev->bd_disk->flags | GENHD_FL_NO_PART;
++	disk->fops = &fitblk_fops;
++	disk->private_data = fitblk;
++	if (readonly) {
++		set_disk_ro(disk, 1);
++		snprintf(disk->disk_name, sizeof(disk->disk_name), FIT_DEVICE_PREFIX "%u", slot);
++	} else {
++		strcpy(disk->disk_name, FIT_DEVICE_PREFIX "rw");
++	}
++
++	set_capacity(disk, nr_sect);
++
++	disk->queue->queue_flags = lower_bdev->bd_disk->queue->queue_flags;
++	memcpy(&disk->queue->limits, &lower_bdev->bd_disk->queue->limits,
++	       sizeof(struct queue_limits));
++
++	fitblk->disk = disk;
++	fitblk->pdev = platform_device_alloc(disk->disk_name, PLATFORM_DEVID_NONE);
++	if (!fitblk->pdev) {
++		err = -ENOMEM;
++		goto out_cleanup_disk;
++	}
++
++	fitblk->pdev->dev.parent = &pdev->dev;
++	err = platform_device_add(fitblk->pdev);
++	if (err)
++		goto out_put_pdev;
++
++	err = device_add_disk(&fitblk->pdev->dev, disk, NULL);
++	if (err)
++		goto out_del_pdev;
++
++	if (!ROOT_DEV)
++		ROOT_DEV = disk->part0->bd_dev;
++
++	list_add_tail(&fitblk->list, &fitblk_devices);
++
++	mutex_unlock(&devices_mutex);
++
++	return 0;
++
++out_del_pdev:
++	platform_device_del(fitblk->pdev);
++out_put_pdev:
++	platform_device_put(fitblk->pdev);
++out_cleanup_disk:
++	put_disk(disk);
++out_free_fitblk:
++	kfree(fitblk);
++out_unlock:
++	refcount_dec(&num_devs);
++	mutex_unlock(&devices_mutex);
++	return err;
++}
++
++static int parse_fit_on_dev(struct device *dev)
++{
++	struct block_device *bdev;
++	struct address_space *mapping;
++	struct folio *folio;
++	pgoff_t f_index = 0;
++	size_t bytes_left, bytes_to_copy;
++	void *pre_fit, *fit, *fit_c;
++	u64 dsize, dsectors, imgmaxsect = 0;
++	u32 size, image_pos, image_len;
++	const __be32 *image_offset_be, *image_len_be, *image_pos_be;
++	int ret = 0, node, images, config;
++	const char *image_name, *image_type, *image_description,
++		*config_default, *config_description, *config_loadables;
++	u32 image_name_len, image_type_len, image_description_len,
++		bootconf_len, config_default_len, config_description_len,
++		config_loadables_len;
++	sector_t start_sect, nr_sects;
++	struct device_node *np = NULL;
++	const char *bootconf_c;
++	const char *loadable;
++	char *bootconf = NULL, *bootconf_term;
++	bool found;
++	int loadables_rem_len, loadable_len;
++	u16 loadcnt;
++	unsigned int slot = 0;
++
++	/* Exclusive open the block device to receive holder notifications */
++	bdev = blkdev_get_by_dev(dev->devt, FMODE_READ | FMODE_EXCL, &_fitblk_claim_ptr);
++	if (!bdev)
++		return -ENODEV;
++
++	if (IS_ERR(bdev))
++		return PTR_ERR(bdev);
++
++	mapping = bdev->bd_inode->i_mapping;
++
++	/* map first page */
++	folio = read_mapping_folio(mapping, f_index++, NULL);
++	if (IS_ERR(folio)) {
++		ret = PTR_ERR(folio);
++		goto out_blkdev;
++	}
++	pre_fit = folio_address(folio) + offset_in_folio(folio, 0);
++
++	/* uImage.FIT is based on flattened device tree structure */
++	if (fdt_check_header(pre_fit)) {
++		ret = -EINVAL;
++		folio_put(folio);
++		goto out_blkdev;
++	}
++
++	size = fdt_totalsize(pre_fit);
++
++	if (size > PAGE_SIZE * FIT_MAX_PAGES) {
++		ret = -EOPNOTSUPP;
++		folio_put(folio);
++		goto out_blkdev;
++	}
++
++	/* acquire disk size */
++	dsectors = bdev_nr_sectors(bdev);
++	dsize = dsectors << SECTOR_SHIFT;
++
++	/* abort if FIT structure is larger than disk or partition size */
++	if (size >= dsize) {
++		ret = -EFBIG;
++		folio_put(folio);
++		goto out_blkdev;
++	}
++
++	fit = kmalloc(size, GFP_KERNEL);
++	if (!fit) {
++		ret = -ENOMEM;
++		folio_put(folio);
++		goto out_blkdev;
++	}
++
++	bytes_left = size;
++	fit_c = fit;
++	while (bytes_left > 0) {
++		bytes_to_copy = min_t(size_t, bytes_left,
++				     folio_size(folio) - offset_in_folio(folio, 0));
++		memcpy(fit_c, pre_fit, bytes_to_copy);
++		fit_c += bytes_to_copy;
++		bytes_left -= bytes_to_copy;
++		if (bytes_left) {
++			folio_put(folio);
++			folio = read_mapping_folio(mapping, f_index++, NULL);
++			if (IS_ERR(folio)) {
++				ret = PTR_ERR(folio);
++				goto out_blkdev;
++			};
++			pre_fit = folio_address(folio) + offset_in_folio(folio, 0);
++		}
++	}
++	folio_put(folio);
++
++	/* set boot config node name U-Boot may have added to the device tree */
++	np = of_find_node_by_path("/chosen");
++	if (np) {
++		bootconf_c = of_get_property(np, "u-boot,bootconf", &bootconf_len);
++		if (bootconf_c && bootconf_len)
++			bootconf = kmemdup_nul(bootconf_c, bootconf_len, GFP_KERNEL);
++	}
++
++	if (bootconf) {
++		bootconf_term = strchr(bootconf, '#');
++		if (bootconf_term)
++			*bootconf_term = '\0';
++	}
++
++	/* find configuration path in uImage.FIT */
++	config = fdt_path_offset(fit, FIT_CONFS_PATH);
++	if (config < 0) {
++		pr_err("FIT: Cannot find %s node: %d\n",
++			FIT_CONFS_PATH, config);
++		ret = -ENOENT;
++		goto out_bootconf;
++	}
++
++	/* get default configuration node name */
++	config_default =
++		fdt_getprop(fit, config, FIT_DEFAULT_PROP, &config_default_len);
++
++	/* make sure we got either default or selected boot config node name */
++	if (!config_default && !bootconf) {
++		pr_err("FIT: Cannot find default configuration\n");
++		ret = -ENOENT;
++		goto out_bootconf;
++	}
++
++	/* find selected boot config node, fallback on default config node */
++	node = fdt_subnode_offset(fit, config, bootconf ?: config_default);
++	if (node < 0) {
++		pr_err("FIT: Cannot find %s node: %d\n",
++			bootconf ?: config_default, node);
++		ret = -ENOENT;
++		goto out_bootconf;
++	}
++
++	pr_info("FIT: Detected U-Boot %s\n", ubootver);
++
++	/* get selected configuration data */
++	config_description =
++		fdt_getprop(fit, node, FIT_DESC_PROP, &config_description_len);
++	config_loadables = fdt_getprop(fit, node, FIT_LOADABLE_PROP,
++				       &config_loadables_len);
++
++	pr_info("FIT: %s configuration: \"%.*s\"%s%.*s%s\n",
++		bootconf ? "Selected" : "Default",
++		bootconf ? bootconf_len : config_default_len,
++		bootconf ?: config_default,
++		config_description ? " (" : "",
++		config_description ? config_description_len : 0,
++		config_description ?: "",
++		config_description ? ")" : "");
++
++	if (!config_loadables || !config_loadables_len) {
++		pr_err("FIT: No loadables configured in \"%s\"\n",
++			bootconf ?: config_default);
++		ret = -ENOENT;
++		goto out_bootconf;
++	}
++
++	/* get images path in uImage.FIT */
++	images = fdt_path_offset(fit, FIT_IMAGES_PATH);
++	if (images < 0) {
++		pr_err("FIT: Cannot find %s node: %d\n", FIT_IMAGES_PATH, images);
++		ret = -EINVAL;
++		goto out_bootconf;
++	}
++
++	/* iterate over images in uImage.FIT */
++	fdt_for_each_subnode(node, fit, images) {
++		image_name = fdt_get_name(fit, node, &image_name_len);
++		image_type = fdt_getprop(fit, node, FIT_TYPE_PROP, &image_type_len);
++		image_offset_be = fdt_getprop(fit, node, FIT_DATA_OFFSET_PROP, NULL);
++		image_pos_be = fdt_getprop(fit, node, FIT_DATA_POSITION_PROP, NULL);
++		image_len_be = fdt_getprop(fit, node, FIT_DATA_SIZE_PROP, NULL);
++
++		if (!image_name || !image_type || !image_len_be ||
++		    !image_name_len || !image_type_len)
++			continue;
++
++		image_len = be32_to_cpu(*image_len_be);
++		if (!image_len)
++			continue;
++
++		if (image_offset_be)
++			image_pos = be32_to_cpu(*image_offset_be) + size;
++		else if (image_pos_be)
++			image_pos = be32_to_cpu(*image_pos_be);
++		else
++			continue;
++
++		image_description = fdt_getprop(fit, node, FIT_DESC_PROP,
++						&image_description_len);
++
++		pr_info("FIT: %16s sub-image 0x%08x..0x%08x \"%.*s\"%s%.*s%s\n",
++			image_type, image_pos, image_pos + image_len - 1,
++			image_name_len, image_name, image_description ? " (" : "",
++			image_description ? image_description_len : 0,
++			image_description ?: "", image_description ? ") " : "");
++
++		/* only 'filesystem' images should be mapped as partitions */
++		if (strncmp(image_type, FIT_FILESYSTEM_PROP, image_type_len))
++			continue;
++
++		/* check if sub-image is part of configured loadables */
++		found = false;
++		loadable = config_loadables;
++		loadables_rem_len = config_loadables_len;
++		for (loadcnt = 0; loadables_rem_len > 1 &&
++				  loadcnt < MAX_FIT_LOADABLES; ++loadcnt) {
++			loadable_len =
++				strnlen(loadable, loadables_rem_len - 1) + 1;
++			loadables_rem_len -= loadable_len;
++			if (!strncmp(image_name, loadable, loadable_len)) {
++				found = true;
++				break;
++			}
++			loadable += loadable_len;
++		}
++		if (!found)
++			continue;
++
++		if (image_pos % (1 << PAGE_SHIFT)) {
++			dev_err(dev, "FIT: image %.*s start not aligned to page boundaries, skipping\n",
++				image_name_len, image_name);
++			continue;
++		}
++
++		if (image_len % (1 << PAGE_SHIFT)) {
++			dev_err(dev, "FIT: sub-image %.*s end not aligned to page boundaries, skipping\n",
++				image_name_len, image_name);
++			continue;
++		}
++
++		start_sect = image_pos >> SECTOR_SHIFT;
++		nr_sects = image_len >> SECTOR_SHIFT;
++		imgmaxsect = max_t(sector_t, imgmaxsect, start_sect + nr_sects);
++
++		if (start_sect + nr_sects > dsectors) {
++			dev_err(dev, "FIT: sub-image %.*s disk access beyond EOD\n",
++				image_name_len, image_name);
++			continue;
++		}
++
++		if (!slot) {
++			ret = sysfs_create_link_nowarn(&pdev->dev.kobj, bdev_kobj(bdev), "lower_dev");
++			if (ret && ret != -EEXIST)
++				goto out_bootconf;
++
++			ret = 0;
++		}
++
++		add_fit_subimage_device(bdev, slot++, start_sect, nr_sects, true);
++	}
++
++	if (!found || !slot)
++		goto out_bootconf;
++
++	dev_info(dev, "mapped %u uImage.FIT filesystem sub-image%s as /dev/fit%s%u%s\n",
++		 slot, (slot > 1)?"s":"", (slot > 1)?"[0...":"", slot - 1,
++		 (slot > 1)?"]":"");
++
++	/* in case uImage.FIT is stored in a partition, map the remaining space */
++	if (!bdev->bd_read_only && bdev_is_partition(bdev) &&
++	    (imgmaxsect + MIN_FREE_SECT) < dsectors) {
++		add_fit_subimage_device(bdev, slot++, imgmaxsect,
++					dsectors - imgmaxsect, false);
++		dev_info(dev, "mapped remaing space as /dev/fitrw\n");
++	}
++
++out_bootconf:
++	kfree(bootconf);
++	kfree(fit);
++out_blkdev:
++	if (!found || ret)
++		blkdev_put(bdev, FMODE_READ | FMODE_EXCL);
++
++	return ret;
++}
++
++static int fitblk_match_of_node(struct device *dev, const void *np)
++{
++	int ret;
++
++	ret = device_match_of_node(dev, np);
++	if (ret)
++		return ret;
++
++	/*
++	 * To match ubiblock and mtdblock devices by their parent ubi
++	 * or mtd device, also consider block device parent
++	 */
++	if (!dev->parent)
++		return 0;
++
++	return device_match_of_node(dev->parent, np);
++}
++
++static int fitblk_probe(struct platform_device *pdev)
++{
++	struct device *dev;
++
++	dev = class_find_device(&block_class, NULL, rootdisk, fitblk_match_of_node);
++	if (!dev)
++		return -EPROBE_DEFER;
++
++	return parse_fit_on_dev(dev);
++}
++
++static struct platform_driver fitblk_driver = {
++	.probe		= fitblk_probe,
++	.driver		= {
++		.name   = "fitblk",
++		.owner   = THIS_MODULE,
++	},
++};
++
++static int __init fitblk_init(void)
++{
++	/* detect U-Boot firmware */
++	ubootver = of_get_property(of_chosen, "u-boot,version", NULL);
++	if (!ubootver)
++		return 0;
++
++	/* parse 'rootdisk' property phandle */
++	rootdisk = of_parse_phandle(of_chosen, "rootdisk", 0);
++	if (!rootdisk)
++		return 0;
++
++	if (platform_driver_register(&fitblk_driver))
++		return -ENODEV;
++
++	refcount_set(&num_devs, 1);
++	pdev = platform_device_register_simple("fitblk", -1, NULL, 0);
++	if (IS_ERR(pdev))
++		return PTR_ERR(pdev);
++
++	return 0;
++}
++device_initcall(fitblk_init);
+--- /dev/null
++++ b/include/uapi/linux/fitblk.h
+@@ -0,0 +1,10 @@
++/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
++#ifndef _UAPI_LINUX_FITBLK_H
++#define _UAPI_LINUX_FITBLK_H
++
++/*
++ * IOCTL commands --- we will commandeer 0x46 ('F')
++ */
++#define FITBLK_RELEASE             0x4600
++
++#endif /* _UAPI_LINUX_FITBLK_H */
diff --git a/target/linux/generic/pending-6.1/511-init-bypass-device-lookup-for-dev-fit-rootfs.patch b/target/linux/generic/pending-6.1/511-init-bypass-device-lookup-for-dev-fit-rootfs.patch
new file mode 100644
index 00000000000000..685a5f9da510ba
--- /dev/null
+++ b/target/linux/generic/pending-6.1/511-init-bypass-device-lookup-for-dev-fit-rootfs.patch
@@ -0,0 +1,25 @@
+From 5ede3f8aed9a1a579bf7304142600d1f3500add9 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 12 Jun 2023 03:58:42 +0100
+Subject: [PATCH 2/2] init: bypass device lookup for /dev/fit* rootfs
+
+Allow 'rootwait' as /dev/fit* can show up late if the underlaying
+device is probed late.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ init/do_mounts.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/init/do_mounts.c
++++ b/init/do_mounts.c
+@@ -645,7 +645,8 @@ void __init prepare_namespace(void)
+ 
+ 	if (saved_root_name[0]) {
+ 		root_device_name = saved_root_name;
+-		if (!strncmp(root_device_name, "mtd", 3) ||
++		if (!strncmp(root_device_name, "fit", 3) ||
++		    !strncmp(root_device_name, "mtd", 3) ||
+ 		    !strncmp(root_device_name, "ubi", 3)) {
+ 			mount_block_root(root_device_name, root_mountflags);
+ 			goto out;
diff --git a/target/linux/generic/pending-6.1/540-ksmbd-only-v2-leases-handle-the-directory.patch b/target/linux/generic/pending-6.1/540-ksmbd-only-v2-leases-handle-the-directory.patch
deleted file mode 100644
index b565fbd5b97215..00000000000000
--- a/target/linux/generic/pending-6.1/540-ksmbd-only-v2-leases-handle-the-directory.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From 86b7307af26834415e1ba8597319a8b64846346f Mon Sep 17 00:00:00 2001
-From: Namjae Jeon <linkinjeon@kernel.org>
-Date: Mon, 15 Jan 2024 10:24:54 +0900
-Subject: [PATCH] ksmbd: only v2 leases handle the directory
-
-When smb2 leases is disable, ksmbd can send oplock break notification
-and cause wait oplock break ack timeout. It may appear like hang when
-accessing a directory. This patch make only v2 leases handle the
-directory.
-
-Cc: stable@vger.kernel.org
-Signed-off-by: Namjae Jeon <linkinjeon@kernel.org>
-Signed-off-by: Steve French <stfrench@microsoft.com>
----
- fs/smb/server/oplock.c | 6 ++++++
- 1 file changed, 6 insertions(+)
-
---- a/fs/smb/server/oplock.c
-+++ b/fs/smb/server/oplock.c
-@@ -1191,6 +1191,12 @@ int smb_grant_oplock(struct ksmbd_work *
- 	bool prev_op_has_lease;
- 	__le32 prev_op_state = 0;
- 
-+	/* Only v2 leases handle the directory */
-+	if (S_ISDIR(file_inode(fp->filp)->i_mode)) {
-+		if (!lctx || lctx->version != 2)
-+			return 0;
-+	}
-+
- 	opinfo = alloc_opinfo(work, pid, tid);
- 	if (!opinfo)
- 		return -ENOMEM;
diff --git a/target/linux/generic/pending-6.1/666-Add-support-for-MAP-E-FMRs-mesh-mode.patch b/target/linux/generic/pending-6.1/666-Add-support-for-MAP-E-FMRs-mesh-mode.patch
index 2bc25eb4fa6684..b799c6fc9cb6a6 100644
--- a/target/linux/generic/pending-6.1/666-Add-support-for-MAP-E-FMRs-mesh-mode.patch
+++ b/target/linux/generic/pending-6.1/666-Add-support-for-MAP-E-FMRs-mesh-mode.patch
@@ -275,8 +275,8 @@ Signed-off-by: Steven Barth <cyrus@openwrt.org>
  static int __ip6_tnl_rcv(struct ip6_tnl *tunnel, struct sk_buff *skb,
  			 const struct tnl_ptk_info *tpi,
  			 struct metadata_dst *tun_dst,
-@@ -840,6 +966,27 @@ static int __ip6_tnl_rcv(struct ip6_tnl
- 	skb_reset_network_header(skb);
+@@ -855,6 +981,27 @@ static int __ip6_tnl_rcv(struct ip6_tnl
+ 
  	memset(skb->cb, 0, sizeof(struct inet6_skb_parm));
  
 +	if (tpi->proto == htons(ETH_P_IP) && tunnel->parms.fmrs &&
@@ -303,7 +303,7 @@ Signed-off-by: Steven Barth <cyrus@openwrt.org>
  	__skb_tunnel_rx(skb, tunnel->dev, tunnel->net);
  
  	err = dscp_ecn_decapsulate(tunnel, ipv6h, skb);
-@@ -987,6 +1134,7 @@ static void init_tel_txopt(struct ipv6_t
+@@ -1002,6 +1149,7 @@ static void init_tel_txopt(struct ipv6_t
  	opt->ops.opt_nflen = 8;
  }
  
@@ -311,7 +311,7 @@ Signed-off-by: Steven Barth <cyrus@openwrt.org>
  /**
   * ip6_tnl_addr_conflict - compare packet addresses to tunnel's own
   *   @t: the outgoing tunnel device
-@@ -1278,6 +1426,7 @@ ipxip6_tnl_xmit(struct sk_buff *skb, str
+@@ -1293,6 +1441,7 @@ ipxip6_tnl_xmit(struct sk_buff *skb, str
  		u8 protocol)
  {
  	struct ip6_tnl *t = netdev_priv(dev);
@@ -319,7 +319,7 @@ Signed-off-by: Steven Barth <cyrus@openwrt.org>
  	struct ipv6hdr *ipv6h;
  	const struct iphdr  *iph;
  	int encap_limit = -1;
-@@ -1377,6 +1526,18 @@ ipxip6_tnl_xmit(struct sk_buff *skb, str
+@@ -1392,6 +1541,18 @@ ipxip6_tnl_xmit(struct sk_buff *skb, str
  	fl6.flowi6_uid = sock_net_uid(dev_net(dev), NULL);
  	dsfield = INET_ECN_encapsulate(dsfield, orig_dsfield);
  
@@ -338,7 +338,7 @@ Signed-off-by: Steven Barth <cyrus@openwrt.org>
  	if (iptunnel_handle_offloads(skb, SKB_GSO_IPXIP6))
  		return -1;
  
-@@ -1530,6 +1691,14 @@ ip6_tnl_change(struct ip6_tnl *t, const
+@@ -1545,6 +1706,14 @@ ip6_tnl_change(struct ip6_tnl *t, const
  	t->parms.link = p->link;
  	t->parms.proto = p->proto;
  	t->parms.fwmark = p->fwmark;
@@ -353,7 +353,7 @@ Signed-off-by: Steven Barth <cyrus@openwrt.org>
  	dst_cache_reset(&t->dst_cache);
  	ip6_tnl_link_config(t);
  }
-@@ -1564,6 +1733,7 @@ ip6_tnl_parm_from_user(struct __ip6_tnl_
+@@ -1579,6 +1748,7 @@ ip6_tnl_parm_from_user(struct __ip6_tnl_
  	p->flowinfo = u->flowinfo;
  	p->link = u->link;
  	p->proto = u->proto;
@@ -361,7 +361,7 @@ Signed-off-by: Steven Barth <cyrus@openwrt.org>
  	memcpy(p->name, u->name, sizeof(u->name));
  }
  
-@@ -1950,6 +2120,15 @@ static int ip6_tnl_validate(struct nlatt
+@@ -1965,6 +2135,15 @@ static int ip6_tnl_validate(struct nlatt
  	return 0;
  }
  
@@ -377,7 +377,7 @@ Signed-off-by: Steven Barth <cyrus@openwrt.org>
  static void ip6_tnl_netlink_parms(struct nlattr *data[],
  				  struct __ip6_tnl_parm *parms)
  {
-@@ -1987,6 +2166,46 @@ static void ip6_tnl_netlink_parms(struct
+@@ -2002,6 +2181,46 @@ static void ip6_tnl_netlink_parms(struct
  
  	if (data[IFLA_IPTUN_FWMARK])
  		parms->fwmark = nla_get_u32(data[IFLA_IPTUN_FWMARK]);
@@ -424,7 +424,7 @@ Signed-off-by: Steven Barth <cyrus@openwrt.org>
  }
  
  static int ip6_tnl_newlink(struct net *src_net, struct net_device *dev,
-@@ -2070,6 +2289,12 @@ static void ip6_tnl_dellink(struct net_d
+@@ -2085,6 +2304,12 @@ static void ip6_tnl_dellink(struct net_d
  
  static size_t ip6_tnl_get_size(const struct net_device *dev)
  {
@@ -437,7 +437,7 @@ Signed-off-by: Steven Barth <cyrus@openwrt.org>
  	return
  		/* IFLA_IPTUN_LINK */
  		nla_total_size(4) +
-@@ -2099,6 +2324,24 @@ static size_t ip6_tnl_get_size(const str
+@@ -2114,6 +2339,24 @@ static size_t ip6_tnl_get_size(const str
  		nla_total_size(0) +
  		/* IFLA_IPTUN_FWMARK */
  		nla_total_size(4) +
@@ -462,7 +462,7 @@ Signed-off-by: Steven Barth <cyrus@openwrt.org>
  		0;
  }
  
-@@ -2106,6 +2349,9 @@ static int ip6_tnl_fill_info(struct sk_b
+@@ -2121,6 +2364,9 @@ static int ip6_tnl_fill_info(struct sk_b
  {
  	struct ip6_tnl *tunnel = netdev_priv(dev);
  	struct __ip6_tnl_parm *parm = &tunnel->parms;
@@ -472,7 +472,7 @@ Signed-off-by: Steven Barth <cyrus@openwrt.org>
  
  	if (nla_put_u32(skb, IFLA_IPTUN_LINK, parm->link) ||
  	    nla_put_in6_addr(skb, IFLA_IPTUN_LOCAL, &parm->laddr) ||
-@@ -2115,9 +2361,27 @@ static int ip6_tnl_fill_info(struct sk_b
+@@ -2130,9 +2376,27 @@ static int ip6_tnl_fill_info(struct sk_b
  	    nla_put_be32(skb, IFLA_IPTUN_FLOWINFO, parm->flowinfo) ||
  	    nla_put_u32(skb, IFLA_IPTUN_FLAGS, parm->flags) ||
  	    nla_put_u8(skb, IFLA_IPTUN_PROTO, parm->proto) ||
@@ -501,7 +501,7 @@ Signed-off-by: Steven Barth <cyrus@openwrt.org>
  	if (nla_put_u16(skb, IFLA_IPTUN_ENCAP_TYPE, tunnel->encap.type) ||
  	    nla_put_be16(skb, IFLA_IPTUN_ENCAP_SPORT, tunnel->encap.sport) ||
  	    nla_put_be16(skb, IFLA_IPTUN_ENCAP_DPORT, tunnel->encap.dport) ||
-@@ -2157,6 +2421,7 @@ static const struct nla_policy ip6_tnl_p
+@@ -2172,6 +2436,7 @@ static const struct nla_policy ip6_tnl_p
  	[IFLA_IPTUN_ENCAP_DPORT]	= { .type = NLA_U16 },
  	[IFLA_IPTUN_COLLECT_METADATA]	= { .type = NLA_FLAG },
  	[IFLA_IPTUN_FWMARK]		= { .type = NLA_U32 },
diff --git a/target/linux/generic/pending-6.1/700-netfilter-nft_flow_offload-handle-netdevice-events-f.patch b/target/linux/generic/pending-6.1/700-netfilter-nft_flow_offload-handle-netdevice-events-f.patch
index 47c742cff0689b..a3897a9fd1096e 100644
--- a/target/linux/generic/pending-6.1/700-netfilter-nft_flow_offload-handle-netdevice-events-f.patch
+++ b/target/linux/generic/pending-6.1/700-netfilter-nft_flow_offload-handle-netdevice-events-f.patch
@@ -59,7 +59,7 @@ Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
  }
 --- a/net/netfilter/nft_flow_offload.c
 +++ b/net/netfilter/nft_flow_offload.c
-@@ -470,47 +470,14 @@ static struct nft_expr_type nft_flow_off
+@@ -475,47 +475,14 @@ static struct nft_expr_type nft_flow_off
  	.owner		= THIS_MODULE,
  };
  
diff --git a/target/linux/generic/pending-6.1/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch b/target/linux/generic/pending-6.1/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch
index 307ddce761fc1b..db95e28af3b15f 100644
--- a/target/linux/generic/pending-6.1/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch
+++ b/target/linux/generic/pending-6.1/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch
@@ -18,7 +18,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/net/netfilter/nf_tables_api.c
 +++ b/net/netfilter/nf_tables_api.c
-@@ -7884,7 +7884,7 @@ static int nft_register_flowtable_net_ho
+@@ -7908,7 +7908,7 @@ static int nft_register_flowtable_net_ho
  		err = flowtable->data.type->setup(&flowtable->data,
  						  hook->ops.dev,
  						  FLOW_BLOCK_BIND);
diff --git a/target/linux/generic/pending-6.1/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch b/target/linux/generic/pending-6.1/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch
index be28fdc8036183..842fef3a9c5b3f 100644
--- a/target/linux/generic/pending-6.1/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch
+++ b/target/linux/generic/pending-6.1/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch
@@ -10,7 +10,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -4942,6 +4942,8 @@ static int mtk_probe(struct platform_dev
+@@ -4941,6 +4941,8 @@ static int mtk_probe(struct platform_dev
  	 * for NAPI to work
  	 */
  	init_dummy_netdev(&eth->dummy_dev);
diff --git a/target/linux/generic/pending-6.1/703-phy-add-detach-callback-to-struct-phy_driver.patch b/target/linux/generic/pending-6.1/703-phy-add-detach-callback-to-struct-phy_driver.patch
index aa852e7fec936f..e4937a1df1be8c 100644
--- a/target/linux/generic/pending-6.1/703-phy-add-detach-callback-to-struct-phy_driver.patch
+++ b/target/linux/generic/pending-6.1/703-phy-add-detach-callback-to-struct-phy_driver.patch
@@ -11,7 +11,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
 
 --- a/drivers/net/phy/phy_device.c
 +++ b/drivers/net/phy/phy_device.c
-@@ -1753,6 +1753,9 @@ void phy_detach(struct phy_device *phyde
+@@ -1850,6 +1850,9 @@ void phy_detach(struct phy_device *phyde
  	struct module *ndev_owner = NULL;
  	struct mii_bus *bus;
  
@@ -23,7 +23,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
  			sysfs_remove_link(&dev->dev.kobj, "phydev");
 --- a/include/linux/phy.h
 +++ b/include/linux/phy.h
-@@ -896,6 +896,12 @@ struct phy_driver {
+@@ -900,6 +900,12 @@ struct phy_driver {
  	/** @handle_interrupt: Override default interrupt handling */
  	irqreturn_t (*handle_interrupt)(struct phy_device *phydev);
  
diff --git a/target/linux/generic/pending-6.1/704-netfilter-nf_tables-fix-bidirectional-offload-regres.patch b/target/linux/generic/pending-6.1/704-netfilter-nf_tables-fix-bidirectional-offload-regres.patch
new file mode 100644
index 00000000000000..70724cb3a2d9e6
--- /dev/null
+++ b/target/linux/generic/pending-6.1/704-netfilter-nf_tables-fix-bidirectional-offload-regres.patch
@@ -0,0 +1,24 @@
+From: Felix Fietkau <nbd@nbd.name>
+Date: Wed, 14 Feb 2024 15:24:41 +0100
+Subject: [PATCH] netfilter: nf_tables: fix bidirectional offload regression
+
+Commit 8f84780b84d6 ("netfilter: flowtable: allow unidirectional rules")
+made unidirectional flow offload possible, while completely ignoring (and
+breaking) bidirectional flow offload for nftables.
+Add the missing flag that was left out as an exercise for the reader :)
+
+Cc: Vlad Buslov <vladbu@nvidia.com>
+Fixes: 8f84780b84d6 ("netfilter: flowtable: allow unidirectional rules")
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/net/netfilter/nft_flow_offload.c
++++ b/net/netfilter/nft_flow_offload.c
+@@ -357,6 +357,7 @@ static void nft_flow_offload_eval(const
+ 		ct->proto.tcp.seen[1].flags |= IP_CT_TCP_FLAG_BE_LIBERAL;
+ 	}
+ 
++	__set_bit(NF_FLOW_HW_BIDIRECTIONAL, &flow->flags);
+ 	ret = flow_offload_add(flowtable, flow);
+ 	if (ret < 0)
+ 		goto err_flow_add;
diff --git a/target/linux/generic/pending-6.1/711-01-net-dsa-qca8k-implement-lag_fdb_add-del-ops.patch b/target/linux/generic/pending-6.1/711-01-net-dsa-qca8k-implement-lag_fdb_add-del-ops.patch
index b03bb622d326fa..629b141572dbc7 100644
--- a/target/linux/generic/pending-6.1/711-01-net-dsa-qca8k-implement-lag_fdb_add-del-ops.patch
+++ b/target/linux/generic/pending-6.1/711-01-net-dsa-qca8k-implement-lag_fdb_add-del-ops.patch
@@ -16,7 +16,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
 
 --- a/drivers/net/dsa/qca/qca8k-8xxx.c
 +++ b/drivers/net/dsa/qca/qca8k-8xxx.c
-@@ -2004,6 +2004,8 @@ static const struct dsa_switch_ops qca8k
+@@ -2015,6 +2015,8 @@ static const struct dsa_switch_ops qca8k
  	.port_fdb_add		= qca8k_port_fdb_add,
  	.port_fdb_del		= qca8k_port_fdb_del,
  	.port_fdb_dump		= qca8k_port_fdb_dump,
diff --git a/target/linux/generic/pending-6.1/711-02-net-dsa-qca8k-enable-flooding-to-both-CPU-port.patch b/target/linux/generic/pending-6.1/711-02-net-dsa-qca8k-enable-flooding-to-both-CPU-port.patch
index 8ba89ccfa59389..24243468a8fa83 100644
--- a/target/linux/generic/pending-6.1/711-02-net-dsa-qca8k-enable-flooding-to-both-CPU-port.patch
+++ b/target/linux/generic/pending-6.1/711-02-net-dsa-qca8k-enable-flooding-to-both-CPU-port.patch
@@ -14,7 +14,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
 
 --- a/drivers/net/dsa/qca/qca8k-8xxx.c
 +++ b/drivers/net/dsa/qca/qca8k-8xxx.c
-@@ -1893,15 +1893,12 @@ qca8k_setup(struct dsa_switch *ds)
+@@ -1904,15 +1904,12 @@ qca8k_setup(struct dsa_switch *ds)
  		}
  	}
  
diff --git a/target/linux/generic/pending-6.1/711-03-net-dsa-qca8k-add-support-for-port_change_master.patch b/target/linux/generic/pending-6.1/711-03-net-dsa-qca8k-add-support-for-port_change_master.patch
index bf1415b939fcb8..8a58e0f76e0e61 100644
--- a/target/linux/generic/pending-6.1/711-03-net-dsa-qca8k-add-support-for-port_change_master.patch
+++ b/target/linux/generic/pending-6.1/711-03-net-dsa-qca8k-add-support-for-port_change_master.patch
@@ -26,7 +26,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
 
 --- a/drivers/net/dsa/qca/qca8k-8xxx.c
 +++ b/drivers/net/dsa/qca/qca8k-8xxx.c
-@@ -1730,6 +1730,117 @@ qca8k_get_tag_protocol(struct dsa_switch
+@@ -1741,6 +1741,117 @@ qca8k_get_tag_protocol(struct dsa_switch
  	return DSA_TAG_PROTO_QCA;
  }
  
@@ -144,7 +144,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
  static void
  qca8k_master_change(struct dsa_switch *ds, const struct net_device *master,
  		    bool operational)
-@@ -2016,8 +2127,9 @@ static const struct dsa_switch_ops qca8k
+@@ -2027,8 +2138,9 @@ static const struct dsa_switch_ops qca8k
  	.phylink_mac_link_down	= qca8k_phylink_mac_link_down,
  	.phylink_mac_link_up	= qca8k_phylink_mac_link_up,
  	.get_phy_flags		= qca8k_get_phy_flags,
diff --git a/target/linux/generic/pending-6.1/712-net-dsa-qca8k-enable-assisted-learning-on-CPU-port.patch b/target/linux/generic/pending-6.1/712-net-dsa-qca8k-enable-assisted-learning-on-CPU-port.patch
index 4d0b363c379472..23816fe3660cde 100644
--- a/target/linux/generic/pending-6.1/712-net-dsa-qca8k-enable-assisted-learning-on-CPU-port.patch
+++ b/target/linux/generic/pending-6.1/712-net-dsa-qca8k-enable-assisted-learning-on-CPU-port.patch
@@ -20,7 +20,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
 
 --- a/drivers/net/dsa/qca/qca8k-8xxx.c
 +++ b/drivers/net/dsa/qca/qca8k-8xxx.c
-@@ -2002,6 +2002,12 @@ qca8k_setup(struct dsa_switch *ds)
+@@ -2013,6 +2013,12 @@ qca8k_setup(struct dsa_switch *ds)
  			dev_err(priv->dev, "failed enabling QCA header mode on port %d", dp->index);
  			return ret;
  		}
@@ -33,7 +33,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
  	}
  
  	/* Forward all unknown frames to CPU port for Linux processing */
-@@ -2031,11 +2037,6 @@ qca8k_setup(struct dsa_switch *ds)
+@@ -2042,11 +2048,6 @@ qca8k_setup(struct dsa_switch *ds)
  		if (ret)
  			return ret;
  
@@ -45,7 +45,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
  		/* For port based vlans to work we need to set the
  		 * default egress vid
  		 */
-@@ -2087,6 +2088,9 @@ qca8k_setup(struct dsa_switch *ds)
+@@ -2098,6 +2099,9 @@ qca8k_setup(struct dsa_switch *ds)
  	/* Set max number of LAGs supported */
  	ds->num_lag_ids = QCA8K_NUM_LAGS;
  
diff --git a/target/linux/generic/pending-6.1/713-01-dt-bindings-net-ipq4019-mdio-document-now-supported-.patch b/target/linux/generic/pending-6.1/713-01-dt-bindings-net-ipq4019-mdio-document-now-supported-.patch
deleted file mode 100644
index 35258d85418d11..00000000000000
--- a/target/linux/generic/pending-6.1/713-01-dt-bindings-net-ipq4019-mdio-document-now-supported-.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From 85e2038891989e41bc62f6a4625fd5865da8a1a2 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Wed, 24 Jan 2024 19:17:02 +0100
-Subject: [PATCH 1/3] dt-bindings: net: ipq4019-mdio: document now supported
- clock-frequency
-
-Document support for clock-frequency and add details on why this
-property is needed and what values are supported.
-
-From internal documentation, while other values are supported, the
-correct function of the MDIO bus is not assured hence add only the
-suggested supported values to the property enum.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- .../bindings/net/qcom,ipq4019-mdio.yaml           | 15 +++++++++++++++
- 1 file changed, 15 insertions(+)
-
---- a/Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml
-+++ b/Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml
-@@ -38,6 +38,21 @@ properties:
-       MDIO clock source frequency fixed to 100MHZ, this clock should be specified
-       by the platform IPQ807x, IPQ60xx and IPQ50xx.
- 
-+  clock-frequency:
-+    description:
-+      The MDIO bus clock that must be output by the MDIO bus hardware, if
-+      absent, the default hardware values are used.
-+
-+      MDC rate is feed by an external clock (fixed 100MHz) and is divider
-+      internally. The default divider is /256 resulting in the default rate
-+      applied of 390KHz.
-+
-+      To follow 802.3 standard that instruct up to 2.5MHz by default, if
-+      this property is not declared and the divider is set to /256, by
-+      default 1.5625Mhz is select.
-+    enum: [ 390625, 781250, 1562500, 3125000, 6250000, 12500000 ]
-+    default: 1562500
-+
- required:
-   - compatible
-   - reg
diff --git a/target/linux/generic/pending-6.1/713-02-net-mdio-ipq4019-add-support-for-clock-frequency-pro.patch b/target/linux/generic/pending-6.1/713-02-net-mdio-ipq4019-add-support-for-clock-frequency-pro.patch
deleted file mode 100644
index 809d7a04419a62..00000000000000
--- a/target/linux/generic/pending-6.1/713-02-net-mdio-ipq4019-add-support-for-clock-frequency-pro.patch
+++ /dev/null
@@ -1,204 +0,0 @@
-From eacf1d2505dfecd3599d558cdade1a2da47fe06d Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Wed, 24 Jan 2024 18:52:33 +0100
-Subject: [PATCH 2/3] net: mdio: ipq4019: add support for clock-frequency
- property
-
-The IPQ4019 MDIO internally divide the clock feed by AHB based on the
-MDIO_MODE reg. On reset or power up, the default value for the
-divider is 0xff that reflect the divider set to /256.
-
-This makes the MDC run at a very low rate, that is, considering AHB is
-always fixed to 100Mhz, a value of 390KHz.
-
-This hasn't have been a problem as MDIO wasn't used for time sensitive
-operation, it is now that on IPQ807x is usually mounted with PHY that
-requires MDIO to load their firmware (example Aquantia PHY).
-
-To handle this problem and permit to set the correct designed MDC
-frequency for the SoC add support for the standard "clock-frequency"
-property for the MDIO node.
-
-The divider supports value from /1 to /256 and the common value are to
-set it to /16 to reflect 6.25Mhz or to /8 on newer platform to reflect
-12.5Mhz.
-
-To scan if the requested rate is supported by the divider, loop with
-each supported divider and stop when the requested rate match the final
-rate with the current divider. An error is returned if the rate doesn't
-match any value.
-
-On MDIO reset, the divider is restored to the requested value to prevent
-any kind of downclocking caused by the divider reverting to a default
-value.
-
-To follow 802.3 spec of 2.5MHz of default value, if divider is set at
-/256 and "clock-frequency" is not set in DT, assume nobody set the
-divider and try to find the closest MDC rate to 2.5MHz. (in the case of
-AHB set to 100MHz, it's 1.5625MHz)
-
-While at is also document other bits of the MDIO_MODE reg to have a
-clear idea of what is actually applied there.
-
-Documentation of some BITs is skipped as they are marked as reserved and
-their usage is not clear (RES 11:9 GENPHY 16:13 RES1 19:17)
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- drivers/net/mdio/mdio-ipq4019.c | 109 ++++++++++++++++++++++++++++++--
- 1 file changed, 103 insertions(+), 6 deletions(-)
-
---- a/drivers/net/mdio/mdio-ipq4019.c
-+++ b/drivers/net/mdio/mdio-ipq4019.c
-@@ -14,6 +14,20 @@
- #include <linux/clk.h>
- 
- #define MDIO_MODE_REG				0x40
-+#define   MDIO_MODE_MDC_MODE			BIT(12)
-+/* 0 = Clause 22, 1 = Clause 45 */
-+#define   MDIO_MODE_C45				BIT(8)
-+#define   MDIO_MODE_DIV_MASK			GENMASK(7, 0)
-+#define     MDIO_MODE_DIV(x)			FIELD_PREP(MDIO_MODE_DIV_MASK, (x) - 1)
-+#define     MDIO_MODE_DIV_1			0x0
-+#define     MDIO_MODE_DIV_2			0x1
-+#define     MDIO_MODE_DIV_4			0x3
-+#define     MDIO_MODE_DIV_8			0x7
-+#define     MDIO_MODE_DIV_16			0xf
-+#define     MDIO_MODE_DIV_32			0x1f
-+#define     MDIO_MODE_DIV_64			0x3f
-+#define     MDIO_MODE_DIV_128			0x7f
-+#define     MDIO_MODE_DIV_256			0xff
- #define MDIO_ADDR_REG				0x44
- #define MDIO_DATA_WRITE_REG			0x48
- #define MDIO_DATA_READ_REG			0x4c
-@@ -26,9 +40,6 @@
- #define MDIO_CMD_ACCESS_CODE_C45_WRITE	1
- #define MDIO_CMD_ACCESS_CODE_C45_READ	2
- 
--/* 0 = Clause 22, 1 = Clause 45 */
--#define MDIO_MODE_C45				BIT(8)
--
- #define IPQ4019_MDIO_TIMEOUT	10000
- #define IPQ4019_MDIO_SLEEP		10
- 
-@@ -41,6 +52,7 @@ struct ipq4019_mdio_data {
- 	void __iomem	*membase;
- 	void __iomem *eth_ldo_rdy;
- 	struct clk *mdio_clk;
-+	unsigned int mdc_rate;
- };
- 
- static int ipq4019_mdio_wait_busy(struct mii_bus *bus)
-@@ -179,6 +191,38 @@ static int ipq4019_mdio_write(struct mii
- 	return 0;
- }
- 
-+static int ipq4019_mdio_set_div(struct ipq4019_mdio_data *priv)
-+{
-+	unsigned long ahb_rate;
-+	int div;
-+	u32 val;
-+
-+	/* If we don't have a clock for AHB use the fixed value */
-+	ahb_rate = IPQ_MDIO_CLK_RATE;
-+	if (priv->mdio_clk)
-+		ahb_rate = clk_get_rate(priv->mdio_clk);
-+
-+	/* MDC rate is ahb_rate/(MDIO_MODE_DIV + 1)
-+	 * While supported, internal documentation doesn't
-+	 * assure correct functionality of the MDIO bus
-+	 * with divider of 1, 2 or 4.
-+	 */
-+	for (div = 8; div <= 256; div *= 2) {
-+		/* The requested rate is supported by the div */
-+		if (priv->mdc_rate == DIV_ROUND_UP(ahb_rate, div)) {
-+			val = readl(priv->membase + MDIO_MODE_REG);
-+			val &= ~MDIO_MODE_DIV_MASK;
-+			val |= MDIO_MODE_DIV(div);
-+			writel(val, priv->membase + MDIO_MODE_REG);
-+
-+			return 0;
-+		}
-+	}
-+
-+	/* The requested rate is not supported */
-+	return -EINVAL;
-+}
-+
- static int ipq_mdio_reset(struct mii_bus *bus)
- {
- 	struct ipq4019_mdio_data *priv = bus->priv;
-@@ -201,10 +245,58 @@ static int ipq_mdio_reset(struct mii_bus
- 		return ret;
- 
- 	ret = clk_prepare_enable(priv->mdio_clk);
--	if (ret == 0)
--		mdelay(10);
-+	if (ret)
-+		return ret;
-+
-+	mdelay(10);
- 
--	return ret;
-+	/* Restore MDC rate */
-+	return ipq4019_mdio_set_div(priv);
-+}
-+
-+static void ipq4019_mdio_select_mdc_rate(struct platform_device *pdev,
-+					 struct ipq4019_mdio_data *priv)
-+{
-+	unsigned long ahb_rate;
-+	int div;
-+	u32 val;
-+
-+	/* MDC rate defined in DT, we don't have to decide a default value */
-+	if (!of_property_read_u32(pdev->dev.of_node, "clock-frequency",
-+				  &priv->mdc_rate))
-+		return;
-+
-+	/* If we don't have a clock for AHB use the fixed value */
-+	ahb_rate = IPQ_MDIO_CLK_RATE;
-+	if (priv->mdio_clk)
-+		ahb_rate = clk_get_rate(priv->mdio_clk);
-+
-+	/* Check what is the current div set */
-+	val = readl(priv->membase + MDIO_MODE_REG);
-+	div = FIELD_GET(MDIO_MODE_DIV_MASK, val);
-+
-+	/* div is not set to the default value of /256
-+	 * Probably someone changed that (bootloader, other drivers)
-+	 * Keep this and doesn't overwrite it.
-+	 */
-+	if (div != MDIO_MODE_DIV_256) {
-+		priv->mdc_rate = DIV_ROUND_UP(ahb_rate, div + 1);
-+		return;
-+	}
-+
-+	/* If div is /256 assume nobody have set this value and
-+	 * try to find one MDC rate that is close the 802.3 spec of
-+	 * 2.5MHz
-+	 */
-+	for (div = 256; div >= 8; div /= 2) {
-+		/* Stop as soon as we found a divider that
-+		 * reached the closest value to 2.5MHz
-+		 */
-+		if (DIV_ROUND_UP(ahb_rate, div) > 2500000)
-+			break;
-+
-+		priv->mdc_rate = DIV_ROUND_UP(ahb_rate, div);
-+	}
- }
- 
- static int ipq4019_mdio_probe(struct platform_device *pdev)
-@@ -228,6 +320,11 @@ static int ipq4019_mdio_probe(struct pla
- 	if (IS_ERR(priv->mdio_clk))
- 		return PTR_ERR(priv->mdio_clk);
- 
-+	ipq4019_mdio_select_mdc_rate(pdev, priv);
-+	ret = ipq4019_mdio_set_div(priv);
-+	if (ret)
-+		return ret;
-+
- 	/* The platform resource is provided on the chipset IPQ5018 */
- 	/* This resource is optional */
- 	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
diff --git a/target/linux/generic/pending-6.1/732-01-net-ethernet-mtk_eth_soc-work-around-issue-with-send.patch b/target/linux/generic/pending-6.1/732-01-net-ethernet-mtk_eth_soc-work-around-issue-with-send.patch
index fe8841dd3e6c9f..a1cc109050e1df 100644
--- a/target/linux/generic/pending-6.1/732-01-net-ethernet-mtk_eth_soc-work-around-issue-with-send.patch
+++ b/target/linux/generic/pending-6.1/732-01-net-ethernet-mtk_eth_soc-work-around-issue-with-send.patch
@@ -16,7 +16,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1563,12 +1563,28 @@ static void mtk_wake_queue(struct mtk_et
+@@ -1562,12 +1562,28 @@ static void mtk_wake_queue(struct mtk_et
  	}
  }
  
@@ -45,7 +45,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	bool gso = false;
  	int tx_num;
  
-@@ -1590,6 +1606,18 @@ static netdev_tx_t mtk_start_xmit(struct
+@@ -1589,6 +1605,18 @@ static netdev_tx_t mtk_start_xmit(struct
  		return NETDEV_TX_BUSY;
  	}
  
@@ -64,7 +64,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	/* TSO: fill MSS info in tcp checksum field */
  	if (skb_is_gso(skb)) {
  		if (skb_cow_head(skb, 0)) {
-@@ -1605,8 +1633,14 @@ static netdev_tx_t mtk_start_xmit(struct
+@@ -1604,8 +1632,14 @@ static netdev_tx_t mtk_start_xmit(struct
  		}
  	}
  
diff --git a/target/linux/generic/pending-6.1/732-03-net-ethernet-mtk_eth_soc-fix-remaining-throughput-re.patch b/target/linux/generic/pending-6.1/732-03-net-ethernet-mtk_eth_soc-fix-remaining-throughput-re.patch
index 757d2edb2c5307..0a49c75b00d8c1 100644
--- a/target/linux/generic/pending-6.1/732-03-net-ethernet-mtk_eth_soc-fix-remaining-throughput-re.patch
+++ b/target/linux/generic/pending-6.1/732-03-net-ethernet-mtk_eth_soc-fix-remaining-throughput-re.patch
@@ -30,7 +30,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	switch (speed) {
  	case SPEED_2500:
  	case SPEED_1000:
-@@ -3349,6 +3350,9 @@ found:
+@@ -3348,6 +3349,9 @@ found:
  	if (dp->index >= MTK_QDMA_NUM_QUEUES)
  		return NOTIFY_DONE;
  
diff --git a/target/linux/generic/pending-6.1/737-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch b/target/linux/generic/pending-6.1/737-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch
index 23daa2999895fc..afe561ab31f5cf 100644
--- a/target/linux/generic/pending-6.1/737-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch
+++ b/target/linux/generic/pending-6.1/737-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch
@@ -1,8 +1,8 @@
-From 1e25ca1147579bda8b941be1b9851f5911d44eb0 Mon Sep 17 00:00:00 2001
+From 91bda2f441f9e37273922028ffc48ce8e91bf5bd Mon Sep 17 00:00:00 2001
 From: Daniel Golle <daniel@makrotopia.org>
-Date: Tue, 22 Aug 2023 19:04:42 +0100
-Subject: [PATCH 098/125] net: ethernet: mtk_eth_soc: add paths and SerDes
- modes for MT7988
+Date: Tue, 12 Dec 2023 03:51:14 +0000
+Subject: [PATCH] net: ethernet: mtk_eth_soc: add paths and SerDes modes for
+ MT7988
 
 MT7988 comes with a built-in 2.5G PHY as well as SerDes lanes to
 connect external PHYs or transceivers in USXGMII, 10GBase-R, 5GBase-R,
@@ -18,50 +18,11 @@ modes.
 
 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 ---
- drivers/net/ethernet/mediatek/Kconfig        |  16 +
- drivers/net/ethernet/mediatek/Makefile       |   1 +
- drivers/net/ethernet/mediatek/mtk_eth_path.c | 123 +++-
- drivers/net/ethernet/mediatek/mtk_eth_soc.c  | 182 ++++-
- drivers/net/ethernet/mediatek/mtk_eth_soc.h  | 232 ++++++-
- drivers/net/ethernet/mediatek/mtk_usxgmii.c  | 692 +++++++++++++++++++
- 6 files changed, 1215 insertions(+), 31 deletions(-)
- create mode 100644 drivers/net/ethernet/mediatek/mtk_usxgmii.c
+ drivers/net/ethernet/mediatek/mtk_eth_path.c | 122 +++++++-
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c  | 291 +++++++++++++++++--
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h  | 107 ++++++-
+ 3 files changed, 469 insertions(+), 51 deletions(-)
 
---- a/drivers/net/ethernet/mediatek/Kconfig
-+++ b/drivers/net/ethernet/mediatek/Kconfig
-@@ -25,6 +25,22 @@ config NET_MEDIATEK_SOC
- 	  This driver supports the gigabit ethernet MACs in the
- 	  MediaTek SoC family.
- 
-+config NET_MEDIATEK_SOC_USXGMII
-+	bool "Support USXGMII SerDes on MT7988"
-+	depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
-+	def_bool NET_MEDIATEK_SOC != n
-+	help
-+	  Include support for 10GE SerDes which can be found on MT7988.
-+	  If this kernel should run on SoCs with 10 GBit/s Ethernet you
-+	  will need to select this option to use GMAC2 and GMAC3 with
-+	  external PHYs, SFP(+) cages in 10GBase-R, 5GBase-R or USXGMII
-+	  interface modes.
-+
-+	  Note that as the 2500Base-X/1000Base-X/Cisco SGMII SerDes PCS
-+	  unit (MediaTek LynxI) in MT7988 is connected via the new 10GE
-+	  SerDes, you will also need to select this option in case you
-+	  want to use any of those SerDes modes.
-+
- config NET_MEDIATEK_STAR_EMAC
- 	tristate "MediaTek STAR Ethernet MAC support"
- 	select PHYLIB
---- a/drivers/net/ethernet/mediatek/Makefile
-+++ b/drivers/net/ethernet/mediatek/Makefile
-@@ -5,6 +5,7 @@
- 
- obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o
- mtk_eth-y := mtk_eth_soc.o mtk_eth_path.o mtk_ppe.o mtk_ppe_debugfs.o mtk_ppe_offload.o
-+mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_USXGMII) += mtk_usxgmii.o
- mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed.o mtk_wed_mcu.o mtk_wed_wo.o
- ifdef CONFIG_DEBUG_FS
- mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed_debugfs.o
 --- a/drivers/net/ethernet/mediatek/mtk_eth_path.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_path.c
 @@ -31,10 +31,20 @@ static const char *mtk_eth_path_name(u64
@@ -242,14 +203,31 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  
  	/* Setup proper MUXes along the path */
  	return mtk_eth_mux_setup(eth, path);
-@@ -284,4 +398,3 @@ int mtk_gmac_rgmii_path_setup(struct mtk
- 	/* Setup proper MUXes along the path */
- 	return mtk_eth_mux_setup(eth, path);
- }
--
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -475,6 +475,30 @@ static void mtk_setup_bridge_switch(stru
+@@ -21,6 +21,8 @@
+ #include <linux/pinctrl/devinfo.h>
+ #include <linux/phylink.h>
+ #include <linux/pcs/pcs-mtk-lynxi.h>
++#include <linux/pcs/pcs-mtk-usxgmii.h>
++#include <linux/phy/phy.h>
+ #include <linux/jhash.h>
+ #include <linux/bitfield.h>
+ #include <net/dsa.h>
+@@ -258,12 +260,8 @@ static const char * const mtk_clks_sourc
+ 	"ethwarp_wocpu2",
+ 	"ethwarp_wocpu1",
+ 	"ethwarp_wocpu0",
+-	"top_usxgmii0_sel",
+-	"top_usxgmii1_sel",
+ 	"top_sgm0_sel",
+ 	"top_sgm1_sel",
+-	"top_xfi_phy0_xtal_sel",
+-	"top_xfi_phy1_xtal_sel",
+ 	"top_eth_gmii_sel",
+ 	"top_eth_refck_50m_sel",
+ 	"top_eth_sys_200m_sel",
+@@ -475,6 +473,30 @@ static void mtk_setup_bridge_switch(stru
  		MTK_GSW_CFG);
  }
  
@@ -280,34 +258,29 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config,
  					      phy_interface_t interface)
  {
-@@ -483,12 +507,20 @@ static struct phylink_pcs *mtk_mac_selec
+@@ -483,6 +505,21 @@ static struct phylink_pcs *mtk_mac_selec
  	struct mtk_eth *eth = mac->hw;
  	unsigned int sid;
  
--	if (interface == PHY_INTERFACE_MODE_SGMII ||
--	    phy_interface_mode_is_8023z(interface)) {
--		sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ?
--		       0 : mac->id;
--
--		return eth->sgmii_pcs[sid];
-+	if ((interface == PHY_INTERFACE_MODE_SGMII ||
-+	     phy_interface_mode_is_8023z(interface)) &&
-+	    MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
-+		sid = mtk_mac2xgmii_id(eth, mac->id);
-+		if (MTK_HAS_CAPS(eth->soc->caps, MTK_USXGMII))
-+			return mtk_sgmii_wrapper_select_pcs(eth, mac->id);
-+		else
-+			return eth->sgmii_pcs[sid];
-+	} else if ((interface == PHY_INTERFACE_MODE_USXGMII ||
-+		    interface == PHY_INTERFACE_MODE_10GBASER ||
-+		    interface == PHY_INTERFACE_MODE_5GBASER) &&
-+		   MTK_HAS_CAPS(eth->soc->caps, MTK_USXGMII) &&
-+		   mac->id != MTK_GMAC1_ID) {
-+		return mtk_usxgmii_select_pcs(eth, mac->id);
- 	}
- 
- 	return NULL;
-@@ -544,7 +576,22 @@ static void mtk_mac_config(struct phylin
++	if (mtk_is_netsys_v3_or_greater(eth)) {
++		switch (interface) {
++		case PHY_INTERFACE_MODE_1000BASEX:
++		case PHY_INTERFACE_MODE_2500BASEX:
++		case PHY_INTERFACE_MODE_SGMII:
++			return mac->sgmii_pcs;
++		case PHY_INTERFACE_MODE_5GBASER:
++		case PHY_INTERFACE_MODE_10GBASER:
++		case PHY_INTERFACE_MODE_USXGMII:
++			return mac->usxgmii_pcs;
++		default:
++			return NULL;
++		}
++	}
++
+ 	if (interface == PHY_INTERFACE_MODE_SGMII ||
+ 	    phy_interface_mode_is_8023z(interface)) {
+ 		sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ?
+@@ -544,7 +581,22 @@ static void mtk_mac_config(struct phylin
  					goto init_err;
  			}
  			break;
@@ -330,7 +303,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  			break;
  		default:
  			goto err_phy;
-@@ -599,8 +646,6 @@ static void mtk_mac_config(struct phylin
+@@ -599,8 +651,6 @@ static void mtk_mac_config(struct phylin
  		val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
  		val |= SYSCFG0_GE_MODE(ge_mode, mac->id);
  		regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
@@ -339,7 +312,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  	}
  
  	/* SGMII */
-@@ -617,21 +662,40 @@ static void mtk_mac_config(struct phylin
+@@ -617,21 +667,40 @@ static void mtk_mac_config(struct phylin
  
  		/* Save the syscfg0 value for mac_finish */
  		mac->syscfg0 = val;
@@ -387,7 +360,37 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  	return;
  
  err_phy:
-@@ -677,10 +741,13 @@ static void mtk_mac_link_down(struct phy
+@@ -644,6 +713,18 @@ init_err:
+ 		mac->id, phy_modes(state->interface), err);
+ }
+ 
++static int mtk_mac_prepare(struct phylink_config *config, unsigned int mode,
++			   phy_interface_t interface)
++{
++	struct mtk_mac *mac = container_of(config, struct mtk_mac,
++					   phylink_config);
++
++	if (mac->pextp && mac->interface != interface)
++		phy_reset(mac->pextp);
++
++	return 0;
++}
++
+ static int mtk_mac_finish(struct phylink_config *config, unsigned int mode,
+ 			  phy_interface_t interface)
+ {
+@@ -652,6 +733,10 @@ static int mtk_mac_finish(struct phylink
+ 	struct mtk_eth *eth = mac->hw;
+ 	u32 mcr_cur, mcr_new;
+ 
++	/* Setup PMA/PMD */
++	if (mac->pextp)
++		phy_set_mode_ext(mac->pextp, PHY_MODE_ETHERNET, interface);
++
+ 	/* Enable SGMII */
+ 	if (interface == PHY_INTERFACE_MODE_SGMII ||
+ 	    phy_interface_mode_is_8023z(interface))
+@@ -677,10 +762,13 @@ static void mtk_mac_link_down(struct phy
  {
  	struct mtk_mac *mac = container_of(config, struct mtk_mac,
  					   phylink_config);
@@ -404,7 +407,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  }
  
  static void mtk_set_queue_speed(struct mtk_eth *eth, unsigned int idx,
-@@ -752,13 +819,11 @@ static void mtk_set_queue_speed(struct m
+@@ -752,13 +840,11 @@ static void mtk_set_queue_speed(struct m
  	mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs);
  }
  
@@ -422,7 +425,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  	u32 mcr;
  
  	mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
-@@ -792,6 +857,55 @@ static void mtk_mac_link_up(struct phyli
+@@ -792,9 +878,63 @@ static void mtk_mac_link_up(struct phyli
  	mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
  }
  
@@ -473,12 +476,98 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 +	else
 +		mtk_gdm_mac_link_up(mac, phy, mode, interface, speed, duplex,
 +				    tx_pause, rx_pause);
++
++	/* Repeat pextp setup to tune link */
++	if (mac->pextp)
++		phy_set_mode_ext(mac->pextp, PHY_MODE_ETHERNET, interface);
 +}
 +
  static const struct phylink_mac_ops mtk_phylink_ops = {
- 	.validate = phylink_generic_validate,
  	.mac_select_pcs = mtk_mac_select_pcs,
-@@ -4617,8 +4731,21 @@ static int mtk_add_mac(struct mtk_eth *e
+ 	.mac_config = mtk_mac_config,
++	.mac_prepare = mtk_mac_prepare,
+ 	.mac_finish = mtk_mac_finish,
+ 	.mac_link_down = mtk_mac_link_down,
+ 	.mac_link_up = mtk_mac_link_up,
+@@ -3373,6 +3513,9 @@ static int mtk_open(struct net_device *d
+ 	struct mtk_eth *eth = mac->hw;
+ 	int i, err;
+ 
++	if (mac->pextp)
++		phy_power_on(mac->pextp);
++
+ 	err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0);
+ 	if (err) {
+ 		netdev_err(dev, "%s: could not attach PHY: %d\n", __func__,
+@@ -3501,6 +3644,9 @@ static int mtk_stop(struct net_device *d
+ 	for (i = 0; i < ARRAY_SIZE(eth->ppe); i++)
+ 		mtk_ppe_stop(eth->ppe[i]);
+ 
++	if (mac->pextp)
++		phy_power_off(mac->pextp);
++
+ 	return 0;
+ }
+ 
+@@ -4498,6 +4644,7 @@ static const struct net_device_ops mtk_n
+ static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
+ {
+ 	const __be32 *_id = of_get_property(np, "reg", NULL);
++	struct device_node *pcs_np;
+ 	phy_interface_t phy_mode;
+ 	struct phylink *phylink;
+ 	struct mtk_mac *mac;
+@@ -4533,16 +4680,41 @@ static int mtk_add_mac(struct mtk_eth *e
+ 	mac->id = id;
+ 	mac->hw = eth;
+ 	mac->of_node = np;
++	pcs_np = of_parse_phandle(mac->of_node, "pcs-handle", 0);
++	if (pcs_np) {
++		mac->sgmii_pcs = mtk_pcs_lynxi_get(eth->dev, pcs_np);
++		if (IS_ERR(mac->sgmii_pcs)) {
++			if (PTR_ERR(mac->sgmii_pcs) == -EPROBE_DEFER)
++				return -EPROBE_DEFER;
+ 
+-	err = of_get_ethdev_address(mac->of_node, eth->netdev[id]);
+-	if (err == -EPROBE_DEFER)
+-		return err;
++			dev_err(eth->dev, "cannot select SGMII PCS, error %ld\n",
++				PTR_ERR(mac->sgmii_pcs));
++			return PTR_ERR(mac->sgmii_pcs);
++		}
++	}
+ 
+-	if (err) {
+-		/* If the mac address is invalid, use random mac address */
+-		eth_hw_addr_random(eth->netdev[id]);
+-		dev_err(eth->dev, "generated random MAC address %pM\n",
+-			eth->netdev[id]->dev_addr);
++	pcs_np = of_parse_phandle(mac->of_node, "pcs-handle", 1);
++	if (pcs_np) {
++		mac->usxgmii_pcs = mtk_usxgmii_pcs_get(eth->dev, pcs_np);
++		if (IS_ERR(mac->usxgmii_pcs)) {
++			if (PTR_ERR(mac->usxgmii_pcs) == -EPROBE_DEFER)
++				return -EPROBE_DEFER;
++
++			dev_err(eth->dev, "cannot select USXGMII PCS, error %ld\n",
++				PTR_ERR(mac->usxgmii_pcs));
++			return PTR_ERR(mac->usxgmii_pcs);
++		}
++	}
++
++	if (mtk_is_netsys_v3_or_greater(eth) && (mac->sgmii_pcs || mac->usxgmii_pcs)) {
++		mac->pextp = devm_of_phy_get(eth->dev, mac->of_node, NULL);
++		if (IS_ERR(mac->pextp)) {
++			if (PTR_ERR(mac->pextp) != -EPROBE_DEFER)
++				dev_err(eth->dev, "cannot get PHY, error %ld\n",
++					PTR_ERR(mac->pextp));
++
++			return PTR_ERR(mac->pextp);
++		}
+ 	}
+ 
+ 	memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip));
+@@ -4616,8 +4788,21 @@ static int mtk_add_mac(struct mtk_eth *e
  		phy_interface_zero(mac->phylink_config.supported_interfaces);
  		__set_bit(PHY_INTERFACE_MODE_INTERNAL,
  			  mac->phylink_config.supported_interfaces);
@@ -500,23 +589,91 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  	phylink = phylink_create(&mac->phylink_config,
  				 of_fwnode_handle(mac->of_node),
  				 phy_mode, &mtk_phylink_ops);
-@@ -4811,6 +4938,13 @@ static int mtk_probe(struct platform_dev
+@@ -4662,6 +4847,26 @@ free_netdev:
+ 	return err;
+ }
+ 
++static int mtk_mac_assign_address(struct mtk_eth *eth, int i, bool test_defer_only)
++{
++	int err = of_get_ethdev_address(eth->mac[i]->of_node, eth->netdev[i]);
++
++	if (err == -EPROBE_DEFER)
++		return err;
++
++	if (test_defer_only)
++		return 0;
++
++	if (err) {
++		/* If the mac address is invalid, use random mac address */
++		eth_hw_addr_random(eth->netdev[i]);
++		dev_err(eth->dev, "generated random MAC address %pM\n",
++			eth->netdev[i]);
++	}
++
++	return 0;
++}
++
+ void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev)
+ {
+ 	struct net_device *dev, *tmp;
+@@ -4805,7 +5010,8 @@ static int mtk_probe(struct platform_dev
+ 			regmap_write(cci, 0, 3);
+ 	}
+ 
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
++	if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII) &&
++	    !mtk_is_netsys_v3_or_greater(eth)) {
+ 		err = mtk_sgmii_init(eth);
  
  		if (err)
- 			return err;
+@@ -4916,6 +5122,24 @@ static int mtk_probe(struct platform_dev
+ 		}
+ 	}
+ 
++	for (i = 0; i < MTK_MAX_DEVS; i++) {
++		if (!eth->netdev[i])
++			continue;
++
++		err = mtk_mac_assign_address(eth, i, true);
++		if (err)
++			goto err_deinit_hw;
 +	}
 +
-+	if (MTK_HAS_CAPS(eth->soc->caps, MTK_USXGMII)) {
-+		err = mtk_usxgmii_init(eth);
++	for (i = 0; i < MTK_MAX_DEVS; i++) {
++		if (!eth->netdev[i])
++			continue;
 +
++		err = mtk_mac_assign_address(eth, i, false);
 +		if (err)
-+			return err;
++			goto err_deinit_hw;
++	}
++
+ 	if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) {
+ 		err = devm_request_irq(eth->dev, eth->irq[0],
+ 				       mtk_handle_irq, 0,
+@@ -5018,6 +5242,11 @@ static int mtk_remove(struct platform_de
+ 		mtk_stop(eth->netdev[i]);
+ 		mac = netdev_priv(eth->netdev[i]);
+ 		phylink_disconnect_phy(mac->phylink);
++		if (mac->sgmii_pcs)
++			mtk_pcs_lynxi_put(mac->sgmii_pcs);
++
++		if (mac->usxgmii_pcs)
++			mtk_usxgmii_pcs_put(mac->usxgmii_pcs);
  	}
  
- 	if (eth->soc->required_pctl) {
+ 	mtk_wed_exit();
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -502,6 +502,21 @@
+@@ -15,6 +15,7 @@
+ #include <linux/u64_stats_sync.h>
+ #include <linux/refcount.h>
+ #include <linux/phylink.h>
++#include <linux/reset.h>
+ #include <linux/rhashtable.h>
+ #include <linux/dim.h>
+ #include <linux/bitfield.h>
+@@ -502,6 +503,21 @@
  #define INTF_MODE_RGMII_1000    (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED)
  #define INTF_MODE_RGMII_10_100  0
  
@@ -538,7 +695,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  /* GPIO port control registers for GMAC 2*/
  #define GPIO_OD33_CTRL8		0x4c0
  #define GPIO_BIAS_CTRL		0xed0
-@@ -527,6 +542,7 @@
+@@ -527,6 +543,7 @@
  #define SYSCFG0_SGMII_GMAC2    ((3 << 8) & SYSCFG0_SGMII_MASK)
  #define SYSCFG0_SGMII_GMAC1_V2 BIT(9)
  #define SYSCFG0_SGMII_GMAC2_V2 BIT(8)
@@ -546,72 +703,9 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  
  
  /* ethernet subsystem clock register */
-@@ -559,12 +575,74 @@
- #define ETHSYS_DMA_AG_MAP_QDMA	BIT(1)
- #define ETHSYS_DMA_AG_MAP_PPE	BIT(2)
- 
-+/* USXGMII subsystem config registers */
-+/* Register to control speed */
-+#define RG_PHY_TOP_SPEED_CTRL1	0x80C
-+#define USXGMII_RATE_UPDATE_MODE	BIT(31)
-+#define USXGMII_MAC_CK_GATED	BIT(29)
-+#define USXGMII_IF_FORCE_EN	BIT(28)
-+#define USXGMII_RATE_ADAPT_MODE	GENMASK(10, 8)
-+#define USXGMII_RATE_ADAPT_MODE_X1	0
-+#define USXGMII_RATE_ADAPT_MODE_X2	1
-+#define USXGMII_RATE_ADAPT_MODE_X4	2
-+#define USXGMII_RATE_ADAPT_MODE_X10	3
-+#define USXGMII_RATE_ADAPT_MODE_X100	4
-+#define USXGMII_RATE_ADAPT_MODE_X5	5
-+#define USXGMII_RATE_ADAPT_MODE_X50	6
-+#define USXGMII_XFI_RX_MODE	GENMASK(6, 4)
-+#define USXGMII_XFI_RX_MODE_10G	0
-+#define USXGMII_XFI_RX_MODE_5G	1
-+#define USXGMII_XFI_TX_MODE	GENMASK(2, 0)
-+#define USXGMII_XFI_TX_MODE_10G	0
-+#define USXGMII_XFI_TX_MODE_5G	1
-+
-+/* Register to control PCS AN */
-+#define RG_PCS_AN_CTRL0		0x810
-+#define USXGMII_AN_RESTART	BIT(31)
-+#define USXGMII_AN_SYNC_CNT	GENMASK(30, 11)
-+#define USXGMII_AN_ENABLE	BIT(0)
-+
-+#define RG_PCS_AN_CTRL2		0x818
-+#define USXGMII_LINK_TIMER_IDLE_DETECT	GENMASK(29, 20)
-+#define USXGMII_LINK_TIMER_COMP_ACK_DETECT	GENMASK(19, 10)
-+#define USXGMII_LINK_TIMER_AN_RESTART	GENMASK(9, 0)
-+
-+/* Register to read PCS AN status */
-+#define RG_PCS_AN_STS0		0x81c
-+#define USXGMII_PCS_AN_WORD	GENMASK(15, 0)
-+#define USXGMII_LPA_LATCH	BIT(31)
-+
-+/* Register to control USXGMII XFI PLL digital */
-+#define XFI_PLL_DIG_GLB8	0x08
-+#define RG_XFI_PLL_EN		BIT(31)
-+
-+/* Register to control USXGMII XFI PLL analog */
-+#define XFI_PLL_ANA_GLB8	0x108
-+#define RG_XFI_PLL_ANA_SWWA	0x02283248
-+
- /* Infrasys subsystem config registers */
- #define INFRA_MISC2            0x70c
- #define CO_QPHY_SEL            BIT(0)
+@@ -565,6 +582,11 @@
  #define GEPHY_MAC_SEL          BIT(1)
  
-+/* Toprgu subsystem config registers */
-+#define TOPRGU_SWSYSRST		0x18
-+#define SWSYSRST_UNLOCK_KEY	GENMASK(31, 24)
-+#define SWSYSRST_XFI_PLL_GRST	BIT(16)
-+#define SWSYSRST_XFI_PEXPT1_GRST	BIT(15)
-+#define SWSYSRST_XFI_PEXPT0_GRST	BIT(14)
-+#define SWSYSRST_XFI1_GRST	BIT(13)
-+#define SWSYSRST_XFI0_GRST	BIT(12)
-+#define SWSYSRST_SGMII1_GRST	BIT(2)
-+#define SWSYSRST_SGMII0_GRST	BIT(1)
-+#define TOPRGU_SWSYSRST_EN		0xFC
-+
  /* Top misc registers */
 +#define TOP_MISC_NETSYS_PCS_MUX	0x84
 +#define NETSYS_PCS_MUX_MASK	GENMASK(1, 0)
@@ -621,7 +715,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  #define USB_PHY_SWITCH_REG	0x218
  #define QPHY_SEL_MASK		GENMASK(1, 0)
  #define SGMII_QPHY_SEL		0x2
-@@ -589,6 +667,8 @@
+@@ -589,6 +611,8 @@
  #define MT7628_SDM_RBCNT	(MT7628_SDM_OFFSET + 0x10c)
  #define MT7628_SDM_CS_ERR	(MT7628_SDM_OFFSET + 0x110)
  
@@ -630,7 +724,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  #define MTK_FE_CDM1_FSM		0x220
  #define MTK_FE_CDM2_FSM		0x224
  #define MTK_FE_CDM3_FSM		0x238
-@@ -597,6 +677,11 @@
+@@ -597,6 +621,11 @@
  #define MTK_FE_CDM6_FSM		0x328
  #define MTK_FE_GDM1_FSM		0x228
  #define MTK_FE_GDM2_FSM		0x22C
@@ -642,7 +736,40 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  
  #define MTK_MAC_FSM(x)		(0x1010C + ((x) * 0x100))
  
-@@ -943,6 +1028,8 @@ enum mkt_eth_capabilities {
+@@ -721,12 +750,8 @@ enum mtk_clks_map {
+ 	MTK_CLK_ETHWARP_WOCPU2,
+ 	MTK_CLK_ETHWARP_WOCPU1,
+ 	MTK_CLK_ETHWARP_WOCPU0,
+-	MTK_CLK_TOP_USXGMII_SBUS_0_SEL,
+-	MTK_CLK_TOP_USXGMII_SBUS_1_SEL,
+ 	MTK_CLK_TOP_SGM_0_SEL,
+ 	MTK_CLK_TOP_SGM_1_SEL,
+-	MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL,
+-	MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL,
+ 	MTK_CLK_TOP_ETH_GMII_SEL,
+ 	MTK_CLK_TOP_ETH_REFCK_50M_SEL,
+ 	MTK_CLK_TOP_ETH_SYS_200M_SEL,
+@@ -797,19 +822,9 @@ enum mtk_clks_map {
+ 				 BIT_ULL(MTK_CLK_GP3) | BIT_ULL(MTK_CLK_XGP1) | \
+ 				 BIT_ULL(MTK_CLK_XGP2) | BIT_ULL(MTK_CLK_XGP3) | \
+ 				 BIT_ULL(MTK_CLK_CRYPTO) | \
+-				 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
+-				 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
+-				 BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
+-				 BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
+ 				 BIT_ULL(MTK_CLK_ETHWARP_WOCPU2) | \
+ 				 BIT_ULL(MTK_CLK_ETHWARP_WOCPU1) | \
+ 				 BIT_ULL(MTK_CLK_ETHWARP_WOCPU0) | \
+-				 BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_0_SEL) | \
+-				 BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_1_SEL) | \
+-				 BIT_ULL(MTK_CLK_TOP_SGM_0_SEL) | \
+-				 BIT_ULL(MTK_CLK_TOP_SGM_1_SEL) | \
+-				 BIT_ULL(MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL) | \
+-				 BIT_ULL(MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL) | \
+ 				 BIT_ULL(MTK_CLK_TOP_ETH_GMII_SEL) | \
+ 				 BIT_ULL(MTK_CLK_TOP_ETH_REFCK_50M_SEL) | \
+ 				 BIT_ULL(MTK_CLK_TOP_ETH_SYS_200M_SEL) | \
+@@ -943,6 +958,8 @@ enum mkt_eth_capabilities {
  	MTK_RGMII_BIT = 0,
  	MTK_TRGMII_BIT,
  	MTK_SGMII_BIT,
@@ -651,7 +778,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  	MTK_ESW_BIT,
  	MTK_GEPHY_BIT,
  	MTK_MUX_BIT,
-@@ -963,8 +1050,11 @@ enum mkt_eth_capabilities {
+@@ -963,8 +980,11 @@ enum mkt_eth_capabilities {
  	MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT,
  	MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT,
  	MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT,
@@ -663,7 +790,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  
  	/* PATH BITS */
  	MTK_ETH_PATH_GMAC1_RGMII_BIT,
-@@ -972,14 +1062,21 @@ enum mkt_eth_capabilities {
+@@ -972,14 +992,21 @@ enum mkt_eth_capabilities {
  	MTK_ETH_PATH_GMAC1_SGMII_BIT,
  	MTK_ETH_PATH_GMAC2_RGMII_BIT,
  	MTK_ETH_PATH_GMAC2_SGMII_BIT,
@@ -685,7 +812,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  #define MTK_ESW			BIT_ULL(MTK_ESW_BIT)
  #define MTK_GEPHY		BIT_ULL(MTK_GEPHY_BIT)
  #define MTK_MUX			BIT_ULL(MTK_MUX_BIT)
-@@ -1002,10 +1099,16 @@ enum mkt_eth_capabilities {
+@@ -1002,10 +1029,16 @@ enum mkt_eth_capabilities {
  	BIT_ULL(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT)
  #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY		\
  	BIT_ULL(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT)
@@ -702,7 +829,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  
  /* Supported path present on SoCs */
  #define MTK_ETH_PATH_GMAC1_RGMII	BIT_ULL(MTK_ETH_PATH_GMAC1_RGMII_BIT)
-@@ -1013,8 +1116,13 @@ enum mkt_eth_capabilities {
+@@ -1013,8 +1046,13 @@ enum mkt_eth_capabilities {
  #define MTK_ETH_PATH_GMAC1_SGMII	BIT_ULL(MTK_ETH_PATH_GMAC1_SGMII_BIT)
  #define MTK_ETH_PATH_GMAC2_RGMII	BIT_ULL(MTK_ETH_PATH_GMAC2_RGMII_BIT)
  #define MTK_ETH_PATH_GMAC2_SGMII	BIT_ULL(MTK_ETH_PATH_GMAC2_SGMII_BIT)
@@ -716,7 +843,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  
  #define MTK_GMAC1_RGMII		(MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII)
  #define MTK_GMAC1_TRGMII	(MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
-@@ -1022,7 +1130,12 @@ enum mkt_eth_capabilities {
+@@ -1022,7 +1060,12 @@ enum mkt_eth_capabilities {
  #define MTK_GMAC2_RGMII		(MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII)
  #define MTK_GMAC2_SGMII		(MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII)
  #define MTK_GMAC2_GEPHY		(MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY)
@@ -729,7 +856,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  
  /* MUXes present on SoCs */
  /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */
-@@ -1041,10 +1154,20 @@ enum mkt_eth_capabilities {
+@@ -1041,10 +1084,20 @@ enum mkt_eth_capabilities {
  	(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \
  	MTK_SHARED_SGMII)
  
@@ -750,7 +877,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  #define MTK_HAS_CAPS(caps, _x)		(((caps) & (_x)) == (_x))
  
  #define MT7621_CAPS  (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \
-@@ -1076,8 +1199,12 @@ enum mkt_eth_capabilities {
+@@ -1076,8 +1129,12 @@ enum mkt_eth_capabilities {
  		      MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
  		      MTK_RSTCTRL_PPE1 | MTK_SRAM)
  
@@ -765,56 +892,17 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  
  struct mtk_tx_dma_desc_info {
  	dma_addr_t	addr;
-@@ -1187,6 +1314,24 @@ struct mtk_soc_data {
- /* currently no SoC has more than 3 macs */
- #define MTK_MAX_DEVS	3
- 
-+/* struct mtk_usxgmii_pcs - This structure holds each usxgmii regmap and
-+ *			associated data
-+ * @regmap:		The register map pointing at the range used to setup
-+ *			USXGMII modes
-+ * @interface:		Currently selected interface mode
-+ * @id:			The element is used to record the index of PCS
-+ * @pcs:		Phylink PCS structure
-+ */
-+struct mtk_usxgmii_pcs {
-+	struct mtk_eth		*eth;
-+	struct regmap		*regmap;
-+	struct phylink_pcs	*wrapped_sgmii_pcs;
-+	phy_interface_t		interface;
-+	u8			id;
-+	unsigned int		mode;
-+	struct phylink_pcs	pcs;
-+};
-+
- /* struct mtk_eth -	This is the main datasructure for holding the state
-  *			of the driver
-  * @dev:		The device pointer
-@@ -1207,6 +1352,12 @@ struct mtk_soc_data {
-  * @infra:              The register map pointing at the range used to setup
-  *                      SGMII and GePHY path
-  * @sgmii_pcs:		Pointers to mtk-pcs-lynxi phylink_pcs instances
-+ * @sgmii_wrapped_pcs:	Pointers to NETSYSv3 wrapper PCS instances
-+ * @usxgmii_pll:	The register map pointing at the range used to control
-+ *			the USXGMII SerDes PLL
-+ * @regmap_pextp:	The register map pointing at the range used to setup
-+ *			PHYA
-+ * @usxgmii_pcs:	Pointer to array of pointers to struct for USXGMII PCS
-  * @pctl:		The register map pointing at the range used to setup
-  *			GMAC port drive/slew values
-  * @dma_refcnt:		track how many netdevs are using the DMA engine
-@@ -1250,6 +1401,10 @@ struct mtk_eth {
- 	struct regmap			*ethsys;
- 	struct regmap			*infra;
- 	struct phylink_pcs		*sgmii_pcs[MTK_MAX_DEVS];
-+	struct regmap			*toprgu;
-+	struct regmap			*usxgmii_pll;
-+	struct regmap			*regmap_pextp[MTK_MAX_DEVS];
-+	struct mtk_usxgmii_pcs		*usxgmii_pcs[MTK_MAX_DEVS];
- 	struct regmap			*pctl;
- 	bool				hwlro;
- 	refcount_t			dma_refcnt;
-@@ -1437,6 +1592,19 @@ static inline u32 mtk_get_ib2_multicast_
+@@ -1314,6 +1371,9 @@ struct mtk_mac {
+ 	struct device_node		*of_node;
+ 	struct phylink			*phylink;
+ 	struct phylink_config		phylink_config;
++	struct phylink_pcs		*sgmii_pcs;
++	struct phylink_pcs		*usxgmii_pcs;
++	struct phy			*pextp;
+ 	struct mtk_eth			*hw;
+ 	struct mtk_hw_stats		*hw_stats;
+ 	__be32				hwlro_ip[MTK_MAX_LRO_IP_CNT];
+@@ -1437,6 +1497,19 @@ static inline u32 mtk_get_ib2_multicast_
  	return MTK_FOE_IB2_MULTICAST;
  }
  
@@ -834,7 +922,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  /* read the hardware status register */
  void mtk_stats_update_mac(struct mtk_mac *mac);
  
-@@ -1445,8 +1613,10 @@ u32 mtk_r32(struct mtk_eth *eth, unsigne
+@@ -1445,8 +1518,10 @@ u32 mtk_r32(struct mtk_eth *eth, unsigne
  u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg);
  
  int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id);
@@ -845,760 +933,3 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  
  int mtk_eth_offload_init(struct mtk_eth *eth);
  int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type,
-@@ -1456,5 +1626,63 @@ int mtk_flow_offload_cmd(struct mtk_eth
- void mtk_flow_offload_cleanup(struct mtk_eth *eth, struct list_head *list);
- void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev);
- 
-+static inline int mtk_mac2xgmii_id(struct mtk_eth *eth, int mac_id)
-+{
-+	int xgmii_id = mac_id;
-+
-+	if (mtk_is_netsys_v3_or_greater(eth)) {
-+		switch (mac_id) {
-+		case MTK_GMAC1_ID:
-+		case MTK_GMAC2_ID:
-+			xgmii_id = 1;
-+			break;
-+		case MTK_GMAC3_ID:
-+			xgmii_id = 0;
-+			break;
-+		default:
-+			xgmii_id = -1;
-+		}
-+	}
-+
-+	return MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII) ? 0 : xgmii_id;
-+}
-+
-+static inline int mtk_xgmii2mac_id(struct mtk_eth *eth, int xgmii_id)
-+{
-+	int mac_id = xgmii_id;
-+
-+	if (mtk_is_netsys_v3_or_greater(eth)) {
-+		switch (xgmii_id) {
-+		case 0:
-+			mac_id = 2;
-+			break;
-+		case 1:
-+			mac_id = 1;
-+			break;
-+		default:
-+			mac_id = -1;
-+		}
-+	}
-+
-+	return mac_id;
-+}
-+
-+#ifdef CONFIG_NET_MEDIATEK_SOC_USXGMII
-+struct phylink_pcs *mtk_sgmii_wrapper_select_pcs(struct mtk_eth *eth, int id);
-+struct phylink_pcs *mtk_usxgmii_select_pcs(struct mtk_eth *eth, int id);
-+int mtk_usxgmii_init(struct mtk_eth *eth);
-+#else
-+static inline struct phylink_pcs *mtk_sgmii_wrapper_select_pcs(struct mtk_eth *eth, int id)
-+{
-+	return NULL;
-+}
-+
-+static inline struct phylink_pcs *mtk_usxgmii_select_pcs(struct mtk_eth *eth, int id)
-+{
-+	return NULL;
-+}
-+
-+static inline int mtk_usxgmii_init(struct mtk_eth *eth) { return 0; }
-+#endif /* NET_MEDIATEK_SOC_USXGMII */
- 
- #endif /* MTK_ETH_H */
---- /dev/null
-+++ b/drivers/net/ethernet/mediatek/mtk_usxgmii.c
-@@ -0,0 +1,690 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2023 MediaTek Inc.
-+ * Author: Henry Yen <henry.yen@mediatek.com>
-+ *         Daniel Golle <daniel@makrotopia.org>
-+ */
-+
-+#include <linux/mfd/syscon.h>
-+#include <linux/of.h>
-+#include <linux/regmap.h>
-+#include "mtk_eth_soc.h"
-+
-+static struct mtk_usxgmii_pcs *pcs_to_mtk_usxgmii_pcs(struct phylink_pcs *pcs)
-+{
-+	return container_of(pcs, struct mtk_usxgmii_pcs, pcs);
-+}
-+
-+static int mtk_xfi_pextp_init(struct mtk_eth *eth)
-+{
-+	struct device *dev = eth->dev;
-+	struct device_node *r = dev->of_node;
-+	struct device_node *np;
-+	int i;
-+
-+	for (i = 0; i < MTK_MAX_DEVS; i++) {
-+		np = of_parse_phandle(r, "mediatek,xfi-pextp", i);
-+		if (!np)
-+			break;
-+
-+		eth->regmap_pextp[i] = syscon_node_to_regmap(np);
-+		if (IS_ERR(eth->regmap_pextp[i]))
-+			return PTR_ERR(eth->regmap_pextp[i]);
-+	}
-+
-+	return 0;
-+}
-+
-+static int mtk_xfi_pll_init(struct mtk_eth *eth)
-+{
-+	struct device_node *r = eth->dev->of_node;
-+	struct device_node *np;
-+
-+	np = of_parse_phandle(r, "mediatek,xfi-pll", 0);
-+	if (!np)
-+		return -1;
-+
-+	eth->usxgmii_pll = syscon_node_to_regmap(np);
-+	if (IS_ERR(eth->usxgmii_pll))
-+		return PTR_ERR(eth->usxgmii_pll);
-+
-+	return 0;
-+}
-+
-+static int mtk_toprgu_init(struct mtk_eth *eth)
-+{
-+	struct device_node *r = eth->dev->of_node;
-+	struct device_node *np;
-+
-+	np = of_parse_phandle(r, "mediatek,toprgu", 0);
-+	if (!np)
-+		return -1;
-+
-+	eth->toprgu = syscon_node_to_regmap(np);
-+	if (IS_ERR(eth->toprgu))
-+		return PTR_ERR(eth->toprgu);
-+
-+	return 0;
-+}
-+
-+static int mtk_xfi_pll_enable(struct mtk_eth *eth)
-+{
-+	u32 val = 0;
-+
-+	if (!eth->usxgmii_pll)
-+		return -EINVAL;
-+
-+	/* Add software workaround for USXGMII PLL TCL issue */
-+	regmap_write(eth->usxgmii_pll, XFI_PLL_ANA_GLB8, RG_XFI_PLL_ANA_SWWA);
-+
-+	regmap_read(eth->usxgmii_pll, XFI_PLL_DIG_GLB8, &val);
-+	val |= RG_XFI_PLL_EN;
-+	regmap_write(eth->usxgmii_pll, XFI_PLL_DIG_GLB8, val);
-+
-+	return 0;
-+}
-+
-+static void mtk_usxgmii_setup_phya(struct regmap *pextp, phy_interface_t interface, int id)
-+{
-+	bool is_10g = (interface == PHY_INTERFACE_MODE_10GBASER ||
-+		       interface == PHY_INTERFACE_MODE_USXGMII);
-+	bool is_2p5g = (interface == PHY_INTERFACE_MODE_2500BASEX);
-+	bool is_5g = (interface == PHY_INTERFACE_MODE_5GBASER);
-+
-+	/* Setup operation mode */
-+	if (is_10g)
-+		regmap_write(pextp, 0x9024, 0x00C9071C);
-+	else
-+		regmap_write(pextp, 0x9024, 0x00D9071C);
-+
-+	if (is_5g)
-+		regmap_write(pextp, 0x2020, 0xAAA5A5AA);
-+	else
-+		regmap_write(pextp, 0x2020, 0xAA8585AA);
-+
-+	if (is_2p5g || is_5g || is_10g) {
-+		regmap_write(pextp, 0x2030, 0x0C020707);
-+		regmap_write(pextp, 0x2034, 0x0E050F0F);
-+		regmap_write(pextp, 0x2040, 0x00140032);
-+	} else {
-+		regmap_write(pextp, 0x2030, 0x0C020207);
-+		regmap_write(pextp, 0x2034, 0x0E05050F);
-+		regmap_write(pextp, 0x2040, 0x00200032);
-+	}
-+
-+	if (is_2p5g || is_10g)
-+		regmap_write(pextp, 0x50F0, 0x00C014AA);
-+	else if (is_5g)
-+		regmap_write(pextp, 0x50F0, 0x00C018AA);
-+	else
-+		regmap_write(pextp, 0x50F0, 0x00C014BA);
-+
-+	if (is_5g) {
-+		regmap_write(pextp, 0x50E0, 0x3777812B);
-+		regmap_write(pextp, 0x506C, 0x005C9CFF);
-+		regmap_write(pextp, 0x5070, 0x9DFAFAFA);
-+		regmap_write(pextp, 0x5074, 0x273F3F3F);
-+		regmap_write(pextp, 0x5078, 0xA8883868);
-+		regmap_write(pextp, 0x507C, 0x14661466);
-+	} else {
-+		regmap_write(pextp, 0x50E0, 0x3777C12B);
-+		regmap_write(pextp, 0x506C, 0x005F9CFF);
-+		regmap_write(pextp, 0x5070, 0x9D9DFAFA);
-+		regmap_write(pextp, 0x5074, 0x27273F3F);
-+		regmap_write(pextp, 0x5078, 0xA7883C68);
-+		regmap_write(pextp, 0x507C, 0x11661166);
-+	}
-+
-+	if (is_2p5g || is_10g) {
-+		regmap_write(pextp, 0x5080, 0x0E000AAF);
-+		regmap_write(pextp, 0x5084, 0x08080D0D);
-+		regmap_write(pextp, 0x5088, 0x02030909);
-+	} else if (is_5g) {
-+		regmap_write(pextp, 0x5080, 0x0E001ABF);
-+		regmap_write(pextp, 0x5084, 0x080B0D0D);
-+		regmap_write(pextp, 0x5088, 0x02050909);
-+	} else {
-+		regmap_write(pextp, 0x5080, 0x0E000EAF);
-+		regmap_write(pextp, 0x5084, 0x08080E0D);
-+		regmap_write(pextp, 0x5088, 0x02030B09);
-+	}
-+
-+	if (is_5g) {
-+		regmap_write(pextp, 0x50E4, 0x0C000000);
-+		regmap_write(pextp, 0x50E8, 0x04000000);
-+	} else {
-+		regmap_write(pextp, 0x50E4, 0x0C0C0000);
-+		regmap_write(pextp, 0x50E8, 0x04040000);
-+	}
-+
-+	if (is_2p5g || mtk_interface_mode_is_xgmii(interface))
-+		regmap_write(pextp, 0x50EC, 0x0F0F0C06);
-+	else
-+		regmap_write(pextp, 0x50EC, 0x0F0F0606);
-+
-+	if (is_5g) {
-+		regmap_write(pextp, 0x50A8, 0x50808C8C);
-+		regmap_write(pextp, 0x6004, 0x18000000);
-+	} else {
-+		regmap_write(pextp, 0x50A8, 0x506E8C8C);
-+		regmap_write(pextp, 0x6004, 0x18190000);
-+	}
-+
-+	if (is_10g)
-+		regmap_write(pextp, 0x00F8, 0x01423342);
-+	else if (is_5g)
-+		regmap_write(pextp, 0x00F8, 0x00A132A1);
-+	else if (is_2p5g)
-+		regmap_write(pextp, 0x00F8, 0x009C329C);
-+	else
-+		regmap_write(pextp, 0x00F8, 0x00FA32FA);
-+
-+	/* Force SGDT_OUT off and select PCS */
-+	if (mtk_interface_mode_is_xgmii(interface))
-+		regmap_write(pextp, 0x00F4, 0x80201F20);
-+	else
-+		regmap_write(pextp, 0x00F4, 0x80201F21);
-+
-+	/* Force GLB_CKDET_OUT */
-+	regmap_write(pextp, 0x0030, 0x00050C00);
-+
-+	/* Force AEQ on */
-+	regmap_write(pextp, 0x0070, 0x02002800);
-+	ndelay(1020);
-+
-+	/* Setup DA default value */
-+	regmap_write(pextp, 0x30B0, 0x00000020);
-+	regmap_write(pextp, 0x3028, 0x00008A01);
-+	regmap_write(pextp, 0x302C, 0x0000A884);
-+	regmap_write(pextp, 0x3024, 0x00083002);
-+	if (mtk_interface_mode_is_xgmii(interface)) {
-+		regmap_write(pextp, 0x3010, 0x00022220);
-+		regmap_write(pextp, 0x5064, 0x0F020A01);
-+		regmap_write(pextp, 0x50B4, 0x06100600);
-+		if (interface == PHY_INTERFACE_MODE_USXGMII)
-+			regmap_write(pextp, 0x3048, 0x40704000);
-+		else
-+			regmap_write(pextp, 0x3048, 0x47684100);
-+	} else {
-+		regmap_write(pextp, 0x3010, 0x00011110);
-+		regmap_write(pextp, 0x3048, 0x40704000);
-+	}
-+
-+	if (!mtk_interface_mode_is_xgmii(interface) && !is_2p5g)
-+		regmap_write(pextp, 0x3064, 0x0000C000);
-+
-+	if (interface == PHY_INTERFACE_MODE_USXGMII) {
-+		regmap_write(pextp, 0x3050, 0xA8000000);
-+		regmap_write(pextp, 0x3054, 0x000000AA);
-+	} else if (mtk_interface_mode_is_xgmii(interface)) {
-+		regmap_write(pextp, 0x3050, 0x00000000);
-+		regmap_write(pextp, 0x3054, 0x00000000);
-+	} else {
-+		regmap_write(pextp, 0x3050, 0xA8000000);
-+		regmap_write(pextp, 0x3054, 0x000000AA);
-+	}
-+
-+	if (mtk_interface_mode_is_xgmii(interface))
-+		regmap_write(pextp, 0x306C, 0x00000F00);
-+	else if (is_2p5g)
-+		regmap_write(pextp, 0x306C, 0x22000F00);
-+	else
-+		regmap_write(pextp, 0x306C, 0x20200F00);
-+
-+	if (interface == PHY_INTERFACE_MODE_10GBASER && id == 0)
-+		regmap_write(pextp, 0xA008, 0x0007B400);
-+
-+	if (mtk_interface_mode_is_xgmii(interface))
-+		regmap_write(pextp, 0xA060, 0x00040000);
-+	else
-+		regmap_write(pextp, 0xA060, 0x00050000);
-+
-+	if (is_10g)
-+		regmap_write(pextp, 0x90D0, 0x00000001);
-+	else if (is_5g)
-+		regmap_write(pextp, 0x90D0, 0x00000003);
-+	else if (is_2p5g)
-+		regmap_write(pextp, 0x90D0, 0x00000005);
-+	else
-+		regmap_write(pextp, 0x90D0, 0x00000007);
-+
-+	/* Release reset */
-+	regmap_write(pextp, 0x0070, 0x0200E800);
-+	usleep_range(150, 500);
-+
-+	/* Switch to P0 */
-+	regmap_write(pextp, 0x0070, 0x0200C111);
-+	ndelay(1020);
-+	regmap_write(pextp, 0x0070, 0x0200C101);
-+	usleep_range(15, 50);
-+
-+	if (mtk_interface_mode_is_xgmii(interface)) {
-+		/* Switch to Gen3 */
-+		regmap_write(pextp, 0x0070, 0x0202C111);
-+	} else {
-+		/* Switch to Gen2 */
-+		regmap_write(pextp, 0x0070, 0x0201C111);
-+	}
-+	ndelay(1020);
-+	if (mtk_interface_mode_is_xgmii(interface))
-+		regmap_write(pextp, 0x0070, 0x0202C101);
-+	else
-+		regmap_write(pextp, 0x0070, 0x0201C101);
-+	usleep_range(100, 500);
-+	regmap_write(pextp, 0x30B0, 0x00000030);
-+	if (mtk_interface_mode_is_xgmii(interface))
-+		regmap_write(pextp, 0x00F4, 0x80201F00);
-+	else
-+		regmap_write(pextp, 0x00F4, 0x80201F01);
-+
-+	regmap_write(pextp, 0x3040, 0x30000000);
-+	usleep_range(400, 1000);
-+}
-+
-+static void mtk_usxgmii_reset(struct mtk_eth *eth, int id)
-+{
-+	u32 toggle, val;
-+
-+	if (id >= MTK_MAX_DEVS || !eth->toprgu)
-+		return;
-+
-+	switch (id) {
-+	case 0:
-+		toggle = SWSYSRST_XFI_PEXPT0_GRST | SWSYSRST_XFI0_GRST |
-+			 SWSYSRST_SGMII0_GRST;
-+		break;
-+	case 1:
-+		toggle = SWSYSRST_XFI_PEXPT1_GRST | SWSYSRST_XFI1_GRST |
-+			 SWSYSRST_SGMII1_GRST;
-+		break;
-+	default:
-+		return;
-+	}
-+
-+	/* Enable software reset */
-+	regmap_set_bits(eth->toprgu, TOPRGU_SWSYSRST_EN, toggle);
-+
-+	/* Assert USXGMII reset */
-+	regmap_set_bits(eth->toprgu, TOPRGU_SWSYSRST,
-+			FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88) | toggle);
-+
-+	usleep_range(100, 500);
-+
-+	/* De-assert USXGMII reset */
-+	regmap_read(eth->toprgu, TOPRGU_SWSYSRST, &val);
-+	val |= FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88);
-+	val &= ~toggle;
-+	regmap_write(eth->toprgu, TOPRGU_SWSYSRST, val);
-+
-+	/* Disable software reset */
-+	regmap_clear_bits(eth->toprgu, TOPRGU_SWSYSRST_EN, toggle);
-+
-+	mdelay(10);
-+}
-+
-+/* As the USXGMII PHYA is shared with the 1000Base-X/2500Base-X/Cisco SGMII unit
-+ * the psc-mtk-lynxi instance needs to be wrapped, so that calls to .pcs_config
-+ * also trigger an initial reset and subsequent configuration of the PHYA.
-+ */
-+struct mtk_sgmii_wrapper_pcs {
-+	struct mtk_eth		*eth;
-+	struct phylink_pcs	*wrapped_pcs;
-+	u8			id;
-+	struct phylink_pcs	pcs;
-+};
-+
-+static int mtk_sgmii_wrapped_pcs_config(struct phylink_pcs *pcs,
-+					unsigned int mode,
-+					phy_interface_t interface,
-+					const unsigned long *advertising,
-+					bool permit_pause_to_mac)
-+{
-+	struct mtk_sgmii_wrapper_pcs *wp = container_of(pcs, struct mtk_sgmii_wrapper_pcs, pcs);
-+	bool full_reconf;
-+	int ret;
-+
-+	full_reconf = interface != wp->eth->usxgmii_pcs[wp->id]->interface;
-+	if (full_reconf) {
-+		mtk_xfi_pll_enable(wp->eth);
-+		mtk_usxgmii_reset(wp->eth, wp->id);
-+	}
-+
-+	ret = wp->wrapped_pcs->ops->pcs_config(wp->wrapped_pcs, mode, interface,
-+					       advertising, permit_pause_to_mac);
-+
-+	if (full_reconf)
-+		mtk_usxgmii_setup_phya(wp->eth->regmap_pextp[wp->id], interface, wp->id);
-+
-+	wp->eth->usxgmii_pcs[wp->id]->interface = interface;
-+
-+	return ret;
-+}
-+
-+static void mtk_sgmii_wrapped_pcs_get_state(struct phylink_pcs *pcs,
-+					    struct phylink_link_state *state)
-+{
-+	struct mtk_sgmii_wrapper_pcs *wp = container_of(pcs, struct mtk_sgmii_wrapper_pcs, pcs);
-+
-+	return wp->wrapped_pcs->ops->pcs_get_state(wp->wrapped_pcs, state);
-+}
-+
-+static void mtk_sgmii_wrapped_pcs_an_restart(struct phylink_pcs *pcs)
-+{
-+	struct mtk_sgmii_wrapper_pcs *wp = container_of(pcs, struct mtk_sgmii_wrapper_pcs, pcs);
-+
-+	wp->wrapped_pcs->ops->pcs_an_restart(wp->wrapped_pcs);
-+}
-+
-+static void mtk_sgmii_wrapped_pcs_link_up(struct phylink_pcs *pcs,
-+					  unsigned int mode,
-+					  phy_interface_t interface, int speed,
-+					  int duplex)
-+{
-+	struct mtk_sgmii_wrapper_pcs *wp = container_of(pcs, struct mtk_sgmii_wrapper_pcs, pcs);
-+
-+	wp->wrapped_pcs->ops->pcs_link_up(wp->wrapped_pcs, mode, interface, speed, duplex);
-+}
-+
-+static void mtk_sgmii_wrapped_pcs_disable(struct phylink_pcs *pcs)
-+{
-+	struct mtk_sgmii_wrapper_pcs *wp = container_of(pcs, struct mtk_sgmii_wrapper_pcs, pcs);
-+
-+	wp->wrapped_pcs->ops->pcs_disable(wp->wrapped_pcs);
-+
-+	wp->eth->usxgmii_pcs[wp->id]->interface = PHY_INTERFACE_MODE_NA;
-+}
-+
-+static const struct phylink_pcs_ops mtk_sgmii_wrapped_pcs_ops = {
-+	.pcs_get_state = mtk_sgmii_wrapped_pcs_get_state,
-+	.pcs_config = mtk_sgmii_wrapped_pcs_config,
-+	.pcs_an_restart = mtk_sgmii_wrapped_pcs_an_restart,
-+	.pcs_link_up = mtk_sgmii_wrapped_pcs_link_up,
-+	.pcs_disable = mtk_sgmii_wrapped_pcs_disable,
-+};
-+
-+static int mtk_sgmii_wrapper_init(struct mtk_eth *eth)
-+{
-+	struct mtk_sgmii_wrapper_pcs *wp;
-+	int i;
-+
-+	for (i = 0; i < MTK_MAX_DEVS; i++) {
-+		if (!eth->sgmii_pcs[i])
-+			continue;
-+
-+		if (!eth->usxgmii_pcs[i])
-+			continue;
-+
-+		/* Make sure all PCS ops are supported by wrapped PCS */
-+		if (!eth->sgmii_pcs[i]->ops->pcs_get_state ||
-+		    !eth->sgmii_pcs[i]->ops->pcs_config ||
-+		    !eth->sgmii_pcs[i]->ops->pcs_an_restart ||
-+		    !eth->sgmii_pcs[i]->ops->pcs_link_up ||
-+		    !eth->sgmii_pcs[i]->ops->pcs_disable)
-+			return -EOPNOTSUPP;
-+
-+		wp = devm_kzalloc(eth->dev, sizeof(*wp), GFP_KERNEL);
-+		if (!wp)
-+			return -ENOMEM;
-+
-+		wp->wrapped_pcs = eth->sgmii_pcs[i];
-+		wp->id = i;
-+		wp->pcs.poll = true;
-+		wp->pcs.ops = &mtk_sgmii_wrapped_pcs_ops;
-+		wp->eth = eth;
-+
-+		eth->usxgmii_pcs[i]->wrapped_sgmii_pcs = &wp->pcs;
-+	}
-+
-+	return 0;
-+}
-+
-+struct phylink_pcs *mtk_sgmii_wrapper_select_pcs(struct mtk_eth *eth, int mac_id)
-+{
-+	u32 xgmii_id = mtk_mac2xgmii_id(eth, mac_id);
-+
-+	if (!eth->usxgmii_pcs[xgmii_id])
-+		return NULL;
-+
-+	return eth->usxgmii_pcs[xgmii_id]->wrapped_sgmii_pcs;
-+}
-+
-+static int mtk_usxgmii_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
-+				  phy_interface_t interface,
-+				  const unsigned long *advertising,
-+				  bool permit_pause_to_mac)
-+{
-+	struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
-+	struct mtk_eth *eth = mpcs->eth;
-+	struct regmap *pextp = eth->regmap_pextp[mpcs->id];
-+	unsigned int an_ctrl = 0, link_timer = 0, xfi_mode = 0, adapt_mode = 0;
-+	bool mode_changed = false;
-+
-+	if (!pextp)
-+		return -ENODEV;
-+
-+	if (interface == PHY_INTERFACE_MODE_USXGMII) {
-+		an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0x1FF) | USXGMII_AN_ENABLE;
-+		link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x7B) |
-+			     FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x7B) |
-+			     FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x7B);
-+		xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_RX_MODE_10G) |
-+			   FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_TX_MODE_10G);
-+	} else if (interface == PHY_INTERFACE_MODE_10GBASER) {
-+		an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0x1FF);
-+		link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x7B) |
-+			     FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x7B) |
-+			     FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x7B);
-+		xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_RX_MODE_10G) |
-+			   FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_TX_MODE_10G);
-+		adapt_mode = USXGMII_RATE_UPDATE_MODE;
-+	} else if (interface == PHY_INTERFACE_MODE_5GBASER) {
-+		an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0xFF);
-+		link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x3D) |
-+			     FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x3D) |
-+			     FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x3D);
-+		xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_RX_MODE_5G) |
-+			   FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_TX_MODE_5G);
-+		adapt_mode = USXGMII_RATE_UPDATE_MODE;
-+	} else {
-+		return -EINVAL;
-+	}
-+
-+	adapt_mode |= FIELD_PREP(USXGMII_RATE_ADAPT_MODE, USXGMII_RATE_ADAPT_MODE_X1);
-+
-+	if (mpcs->interface != interface) {
-+		mpcs->interface = interface;
-+		mode_changed = true;
-+	}
-+
-+	mtk_xfi_pll_enable(eth);
-+	mtk_usxgmii_reset(eth, mpcs->id);
-+
-+	/* Setup USXGMII AN ctrl */
-+	regmap_update_bits(mpcs->regmap, RG_PCS_AN_CTRL0,
-+			   USXGMII_AN_SYNC_CNT | USXGMII_AN_ENABLE,
-+			   an_ctrl);
-+
-+	regmap_update_bits(mpcs->regmap, RG_PCS_AN_CTRL2,
-+			   USXGMII_LINK_TIMER_IDLE_DETECT |
-+			   USXGMII_LINK_TIMER_COMP_ACK_DETECT |
-+			   USXGMII_LINK_TIMER_AN_RESTART,
-+			   link_timer);
-+
-+	mpcs->mode = mode;
-+
-+	/* Gated MAC CK */
-+	regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1,
-+			   USXGMII_MAC_CK_GATED, USXGMII_MAC_CK_GATED);
-+
-+	/* Enable interface force mode */
-+	regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1,
-+			   USXGMII_IF_FORCE_EN, USXGMII_IF_FORCE_EN);
-+
-+	/* Setup USXGMII adapt mode */
-+	regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1,
-+			   USXGMII_RATE_UPDATE_MODE | USXGMII_RATE_ADAPT_MODE,
-+			   adapt_mode);
-+
-+	/* Setup USXGMII speed */
-+	regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1,
-+			   USXGMII_XFI_RX_MODE | USXGMII_XFI_TX_MODE,
-+			   xfi_mode);
-+
-+	usleep_range(1, 10);
-+
-+	/* Un-gated MAC CK */
-+	regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1,
-+			   USXGMII_MAC_CK_GATED, 0);
-+
-+	usleep_range(1, 10);
-+
-+	/* Disable interface force mode for the AN mode */
-+	if (an_ctrl & USXGMII_AN_ENABLE)
-+		regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1,
-+				   USXGMII_IF_FORCE_EN, 0);
-+
-+	/* Setup USXGMIISYS with the determined property */
-+	mtk_usxgmii_setup_phya(pextp, interface, mpcs->id);
-+
-+	return mode_changed;
-+}
-+
-+static void mtk_usxgmii_pcs_get_state(struct phylink_pcs *pcs,
-+				      struct phylink_link_state *state)
-+{
-+	struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
-+	struct mtk_eth *eth = mpcs->eth;
-+	struct mtk_mac *mac = eth->mac[mtk_xgmii2mac_id(eth, mpcs->id)];
-+	u32 val = 0;
-+
-+	regmap_read(mpcs->regmap, RG_PCS_AN_CTRL0, &val);
-+	if (FIELD_GET(USXGMII_AN_ENABLE, val)) {
-+		/* Refresh LPA by inverting LPA_LATCH */
-+		regmap_read(mpcs->regmap, RG_PCS_AN_STS0, &val);
-+		regmap_update_bits(mpcs->regmap, RG_PCS_AN_STS0,
-+				   USXGMII_LPA_LATCH,
-+				   !(val & USXGMII_LPA_LATCH));
-+
-+		regmap_read(mpcs->regmap, RG_PCS_AN_STS0, &val);
-+
-+		phylink_decode_usxgmii_word(state, FIELD_GET(USXGMII_PCS_AN_WORD,
-+							     val));
-+
-+		state->interface = mpcs->interface;
-+	} else {
-+		val = mtk_r32(mac->hw, MTK_XGMAC_STS(mac->id));
-+
-+		if (mac->id == MTK_GMAC2_ID)
-+			val >>= 16;
-+
-+		switch (FIELD_GET(MTK_USXGMII_PCS_MODE, val)) {
-+		case 0:
-+			state->speed = SPEED_10000;
-+			break;
-+		case 1:
-+			state->speed = SPEED_5000;
-+			break;
-+		case 2:
-+			state->speed = SPEED_2500;
-+			break;
-+		case 3:
-+			state->speed = SPEED_1000;
-+			break;
-+		}
-+
-+		state->interface = mpcs->interface;
-+		state->link = FIELD_GET(MTK_USXGMII_PCS_LINK, val);
-+		state->duplex = DUPLEX_FULL;
-+	}
-+
-+	/* Continuously repeat re-configuration sequence until link comes up */
-+	if (state->link == 0)
-+		mtk_usxgmii_pcs_config(pcs, mpcs->mode,
-+				       state->interface, NULL, false);
-+}
-+
-+static void mtk_usxgmii_pcs_restart_an(struct phylink_pcs *pcs)
-+{
-+	struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
-+	unsigned int val = 0;
-+
-+	if (!mpcs->regmap)
-+		return;
-+
-+	regmap_read(mpcs->regmap, RG_PCS_AN_CTRL0, &val);
-+	val |= USXGMII_AN_RESTART;
-+	regmap_write(mpcs->regmap, RG_PCS_AN_CTRL0, val);
-+}
-+
-+static void mtk_usxgmii_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
-+				    phy_interface_t interface,
-+				    int speed, int duplex)
-+{
-+	/* Reconfiguring USXGMII to ensure the quality of the RX signal
-+	 * after the line side link up.
-+	 */
-+	mtk_usxgmii_pcs_config(pcs, mode,
-+			       interface, NULL, false);
-+}
-+
-+static const struct phylink_pcs_ops mtk_usxgmii_pcs_ops = {
-+	.pcs_config = mtk_usxgmii_pcs_config,
-+	.pcs_get_state = mtk_usxgmii_pcs_get_state,
-+	.pcs_an_restart = mtk_usxgmii_pcs_restart_an,
-+	.pcs_link_up = mtk_usxgmii_pcs_link_up,
-+};
-+
-+int mtk_usxgmii_init(struct mtk_eth *eth)
-+{
-+	struct device_node *r = eth->dev->of_node;
-+	struct device *dev = eth->dev;
-+	struct device_node *np;
-+	int i, ret;
-+
-+	for (i = 0; i < MTK_MAX_DEVS; i++) {
-+		np = of_parse_phandle(r, "mediatek,usxgmiisys", i);
-+		if (!np)
-+			break;
-+
-+		eth->usxgmii_pcs[i] = devm_kzalloc(dev, sizeof(*eth->usxgmii_pcs[i]), GFP_KERNEL);
-+		if (!eth->usxgmii_pcs[i])
-+			return -ENOMEM;
-+
-+		eth->usxgmii_pcs[i]->id = i;
-+		eth->usxgmii_pcs[i]->eth = eth;
-+		eth->usxgmii_pcs[i]->regmap = syscon_node_to_regmap(np);
-+		if (IS_ERR(eth->usxgmii_pcs[i]->regmap))
-+			return PTR_ERR(eth->usxgmii_pcs[i]->regmap);
-+
-+		eth->usxgmii_pcs[i]->pcs.ops = &mtk_usxgmii_pcs_ops;
-+		eth->usxgmii_pcs[i]->pcs.poll = true;
-+		eth->usxgmii_pcs[i]->interface = PHY_INTERFACE_MODE_NA;
-+		eth->usxgmii_pcs[i]->mode = -1;
-+
-+		of_node_put(np);
-+	}
-+
-+	ret = mtk_xfi_pextp_init(eth);
-+	if (ret)
-+		return ret;
-+
-+	ret = mtk_xfi_pll_init(eth);
-+	if (ret)
-+		return ret;
-+
-+	ret = mtk_toprgu_init(eth);
-+	if (ret)
-+		return ret;
-+
-+	return mtk_sgmii_wrapper_init(eth);
-+}
-+
-+struct phylink_pcs *mtk_usxgmii_select_pcs(struct mtk_eth *eth, int mac_id)
-+{
-+	u32 xgmii_id = mtk_mac2xgmii_id(eth, mac_id);
-+
-+	if (!eth->usxgmii_pcs[xgmii_id]->regmap)
-+		return NULL;
-+
-+	return &eth->usxgmii_pcs[xgmii_id]->pcs;
-+}
diff --git a/target/linux/generic/pending-6.1/738-net-ethernet-mtk_eth_soc-set-coherent-mask-to-get-PP.patch b/target/linux/generic/pending-6.1/738-net-ethernet-mtk_eth_soc-set-coherent-mask-to-get-PP.patch
new file mode 100644
index 00000000000000..b598d15866efa4
--- /dev/null
+++ b/target/linux/generic/pending-6.1/738-net-ethernet-mtk_eth_soc-set-coherent-mask-to-get-PP.patch
@@ -0,0 +1,46 @@
+From dee3f591103910c8d8b2a6d57879ccd2a4be4b10 Mon Sep 17 00:00:00 2001
+Message-ID: <dee3f591103910c8d8b2a6d57879ccd2a4be4b10.1706067287.git.daniel@makrotopia.org>
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Wed, 24 Jan 2024 03:19:49 +0000
+Subject: [PATCH net] net: ethernet: mtk_eth_soc: set coherent mask to get PPE
+ working
+To: Felix Fietkau <nbd@nbd.name>,
+    Sean Wang <sean.wang@mediatek.com>,
+    Mark Lee <Mark-MC.Lee@mediatek.com>,
+    Lorenzo Bianconi <lorenzo@kernel.org>,
+    David S. Miller <davem@davemloft.net>,
+    Eric Dumazet <edumazet@google.com>,
+    Jakub Kicinski <kuba@kernel.org>,
+    Paolo Abeni <pabeni@redhat.com>,
+    Matthias Brugger <matthias.bgg@gmail.com>,
+    AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
+    Daniel Golle <daniel@makrotopia.org>,
+    netdev@vger.kernel.org,
+    linux-kernel@vger.kernel.org,
+    linux-arm-kernel@lists.infradead.org,
+    linux-mediatek@lists.infradead.org
+
+Set DMA coherent mask to 32-bit which makes PPE offloading engine start
+working on BPi-R4 which got 4 GiB of RAM.
+
+Fixes: 2d75891ebc09 ("net: ethernet: mtk_eth_soc: support 36-bit DMA addressing on MT7988")
+Suggested-by: Elad Yifee <eladwf@users.github.com>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -4963,7 +4963,10 @@ static int mtk_probe(struct platform_dev
+ 	}
+ 
+ 	if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) {
+-		err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(36));
++		err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(36));
++		if (!err)
++			err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
++
+ 		if (err) {
+ 			dev_err(&pdev->dev, "Wrong DMA config\n");
+ 			return -EINVAL;
diff --git a/target/linux/generic/pending-6.1/739-01-dt-bindings-phy-mediatek-xfi-tphy-add-new-bindings.patch b/target/linux/generic/pending-6.1/739-01-dt-bindings-phy-mediatek-xfi-tphy-add-new-bindings.patch
new file mode 100644
index 00000000000000..1f1c40b1d91589
--- /dev/null
+++ b/target/linux/generic/pending-6.1/739-01-dt-bindings-phy-mediatek-xfi-tphy-add-new-bindings.patch
@@ -0,0 +1,136 @@
+From patchwork Thu Feb  1 21:52:20 2024
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
+X-Patchwork-Id: 13541842
+Date: Thu, 1 Feb 2024 21:52:20 +0000
+From: Daniel Golle <daniel@makrotopia.org>
+To: Bc-bocun Chen <bc-bocun.chen@mediatek.com>,
+	Steven Liu <steven.liu@mediatek.com>,
+	John Crispin <john@phrozen.org>,
+	Chunfeng Yun <chunfeng.yun@mediatek.com>,
+	Vinod Koul <vkoul@kernel.org>,
+	Kishon Vijay Abraham I <kishon@kernel.org>,
+	Rob Herring <robh@kernel.org>,
+	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
+	Conor Dooley <conor+dt@kernel.org>,
+	Daniel Golle <daniel@makrotopia.org>,
+	Qingfang Deng <dqfext@gmail.com>,
+	SkyLake Huang <SkyLake.Huang@mediatek.com>,
+	Matthias Brugger <matthias.bgg@gmail.com>,
+	AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
+	Philipp Zabel <p.zabel@pengutronix.de>,
+	linux-arm-kernel@lists.infradead.org,
+	linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org,
+	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
+	netdev@vger.kernel.org
+Subject: [PATCH 1/2] dt-bindings: phy: mediatek,xfi-tphy: add new bindings
+Message-ID: 
+ <702afb0c1246d95c90b22e57105304028bdd3083.1706823233.git.daniel@makrotopia.org>
+MIME-Version: 1.0
+Content-Disposition: inline
+List-Id: Linux Phy Mailing list <linux-phy.lists.infradead.org>
+
+Add bindings for the MediaTek XFI T-PHY Ethernet SerDes PHY found in the
+MediaTek MT7988 SoC which can operate at various interfaces modes:
+
+via USXGMII PCS:
+ * USXGMII
+ * 10GBase-R
+ * 5GBase-R
+
+via LynxI SGMII PCS:
+ * 2500Base-X
+ * 1000Base-X
+ * Cisco SGMII (MAC side)
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ .../bindings/phy/mediatek,xfi-tphy.yaml       | 80 +++++++++++++++++++
+ 1 file changed, 80 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/phy/mediatek,xfi-tphy.yaml
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/phy/mediatek,xfi-tphy.yaml
+@@ -0,0 +1,80 @@
++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/phy/mediatek,xfi-tphy.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: MediaTek XFI T-PHY
++
++maintainers:
++  - Daniel Golle <daniel@makrotopia.org>
++
++description:
++  The MediaTek XFI SerDes T-PHY provides the physical SerDes lanes
++  used by the (10G/5G) USXGMII PCS and (1G/2.5G) LynxI PCS found in
++  MediaTek's 10G-capabale SoCs.
++
++properties:
++  $nodename:
++    pattern: "^phy@[0-9a-f]+$"
++
++  compatible:
++    const: mediatek,mt7988-xfi-tphy
++
++  reg:
++    maxItems: 1
++
++  clocks:
++    items:
++      - description: XFI PHY clock
++      - description: XFI register clock
++
++  clock-names:
++    items:
++      - const: xfipll
++      - const: topxtal
++
++  resets:
++    items:
++      - description: PEXTP reset
++
++  mediatek,usxgmii-performance-errata:
++    $ref: /schemas/types.yaml#/definitions/flag
++    description:
++      One instance of the T-PHY on MT7988 suffers from a performance
++      problem in 10GBase-R mode which needs a work-around in the driver.
++      The work-around is enabled using this flag.
++
++  "#phy-cells":
++    const: 0
++
++required:
++  - compatible
++  - reg
++  - clocks
++  - clock-names
++  - resets
++  - "#phy-cells"
++
++additionalProperties: false
++
++examples:
++  - |
++    #include <dt-bindings/clock/mediatek,mt7988-clk.h>
++    soc {
++      #address-cells = <2>;
++      #size-cells = <2>;
++
++      phy@11f20000 {
++        compatible = "mediatek,mt7988-xfi-tphy";
++        reg = <0 0x11f20000 0 0x10000>;
++        clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>,
++                 <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>;
++        clock-names = "xfipll", "topxtal";
++        resets = <&watchdog 14>;
++        mediatek,usxgmii-performance-errata;
++        #phy-cells = <0>;
++      };
++    };
++
++...
diff --git a/target/linux/generic/pending-6.1/739-02-phy-add-driver-for-MediaTek-XFI-T-PHY.patch b/target/linux/generic/pending-6.1/739-02-phy-add-driver-for-MediaTek-XFI-T-PHY.patch
new file mode 100644
index 00000000000000..d7424020a78327
--- /dev/null
+++ b/target/linux/generic/pending-6.1/739-02-phy-add-driver-for-MediaTek-XFI-T-PHY.patch
@@ -0,0 +1,497 @@
+From patchwork Thu Feb  1 21:53:06 2024
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
+X-Patchwork-Id: 13541843
+Date: Thu, 1 Feb 2024 21:53:06 +0000
+From: Daniel Golle <daniel@makrotopia.org>
+To: Bc-bocun Chen <bc-bocun.chen@mediatek.com>,
+	Chunfeng Yun <chunfeng.yun@mediatek.com>,
+	Vinod Koul <vkoul@kernel.org>,
+	Kishon Vijay Abraham I <kishon@kernel.org>,
+	Rob Herring <robh@kernel.org>,
+	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
+	Conor Dooley <conor+dt@kernel.org>,
+	Daniel Golle <daniel@makrotopia.org>,
+	Qingfang Deng <dqfext@gmail.com>,
+	SkyLake Huang <SkyLake.Huang@mediatek.com>,
+	Matthias Brugger <matthias.bgg@gmail.com>,
+	AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
+	Philipp Zabel <p.zabel@pengutronix.de>,
+	linux-arm-kernel@lists.infradead.org,
+	linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org,
+	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
+	netdev@vger.kernel.org
+Subject: [PATCH 2/2] phy: add driver for MediaTek XFI T-PHY
+Message-ID: 
+ <dd6b40ea1f7f8459a9a2cfe7fa60c1108332ade6.1706823233.git.daniel@makrotopia.org>
+References: 
+ <702afb0c1246d95c90b22e57105304028bdd3083.1706823233.git.daniel@makrotopia.org>
+MIME-Version: 1.0
+Content-Disposition: inline
+In-Reply-To: 
+ <702afb0c1246d95c90b22e57105304028bdd3083.1706823233.git.daniel@makrotopia.org>
+List-Id: Linux Phy Mailing list <linux-phy.lists.infradead.org>
+
+Add driver for MediaTek's XFI T-PHY, 10 Gigabit/s Ethernet SerDes PHY
+which can be found in the MT7988 SoC.
+
+The PHY can operates only in PHY_MODE_ETHERNET, the submode is one of
+PHY_INTERFACE_MODE_* corresponding to the supported modes:
+
+ * USXGMII                 \
+ * 10GBase-R                }- USXGMII PCS - XGDM  \
+ * 5GBase-R                /                        \
+                                                     }- Ethernet MAC
+ * 2500Base-X              \                        /
+ * 1000Base-X               }- LynxI PCS - GDM     /
+ * Cisco SGMII (MAC side)  /
+
+In order to work-around a performance issue present on the first of
+two XFI T-PHYs present in MT7988, special tuning is applied which can be
+selected by adding the 'mediatek,usxgmii-performance-errata' property to
+the device tree node.
+
+There is no documentation for most registers used for the
+analog/tuning part, however, most of the registers have been partially
+reverse-engineered from MediaTek's SDK implementation (an opaque
+sequence of 32-bit register writes) and descriptions for all relevant
+digital registers and bits such as resets and muxes have been supplied
+by MediaTek.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ MAINTAINERS                             |   1 +
+ drivers/phy/mediatek/Kconfig            |  12 +
+ drivers/phy/mediatek/Makefile           |   1 +
+ drivers/phy/mediatek/phy-mtk-xfi-tphy.c | 392 ++++++++++++++++++++++++
+ 4 files changed, 406 insertions(+)
+ create mode 100644 drivers/phy/mediatek/phy-mtk-xfi-tphy.c
+
+--- a/drivers/phy/mediatek/Kconfig
++++ b/drivers/phy/mediatek/Kconfig
+@@ -13,6 +13,18 @@ config PHY_MTK_PCIE
+ 	  callback for PCIe GEN3 port, it supports software efuse
+ 	  initialization.
+ 
++config PHY_MTK_XFI_TPHY
++	tristate "MediaTek XFI T-PHY Driver"
++	depends on ARCH_MEDIATEK || COMPILE_TEST
++	depends on OF && OF_ADDRESS
++	depends on HAS_IOMEM
++	select GENERIC_PHY
++	help
++	  Say 'Y' here to add support for MediaTek XFI T-PHY driver.
++	  The driver provides access to the Ethernet SerDes T-PHY supporting
++	  1GE and 2.5GE modes via the LynxI PCS, and 5GE and 10GE modes
++	  via the USXGMII PCS found in MediaTek SoCs with 10G Ethernet.
++
+ config PHY_MTK_TPHY
+ 	tristate "MediaTek T-PHY Driver"
+ 	depends on ARCH_MEDIATEK || COMPILE_TEST
+--- a/drivers/phy/mediatek/Makefile
++++ b/drivers/phy/mediatek/Makefile
+@@ -8,6 +8,7 @@ obj-$(CONFIG_PHY_MTK_PCIE)		+= phy-mtk-p
+ obj-$(CONFIG_PHY_MTK_TPHY)		+= phy-mtk-tphy.o
+ obj-$(CONFIG_PHY_MTK_UFS)		+= phy-mtk-ufs.o
+ obj-$(CONFIG_PHY_MTK_XSPHY)		+= phy-mtk-xsphy.o
++obj-$(CONFIG_PHY_MTK_XFI_TPHY)		+= phy-mtk-xfi-tphy.o
+ 
+ phy-mtk-hdmi-drv-y			:= phy-mtk-hdmi.o
+ phy-mtk-hdmi-drv-y			+= phy-mtk-hdmi-mt2701.o
+--- /dev/null
++++ b/drivers/phy/mediatek/phy-mtk-xfi-tphy.c
+@@ -0,0 +1,392 @@
++// SPDX-License-Identifier: GPL-2.0-or-later
++/* MediaTek 10GE SerDes PHY driver
++ *
++ * Copyright (c) 2024 Daniel Golle <daniel@makrotopia.org>
++ *                    Bc-bocun Chen <bc-bocun.chen@mediatek.com>
++ * based on mtk_usxgmii.c found in MediaTek's SDK released under GPL-2.0
++ * Copyright (c) 2022 MediaTek Inc.
++ * Author: Henry Yen <henry.yen@mediatek.com>
++ */
++
++#include <linux/module.h>
++#include <linux/device.h>
++#include <linux/platform_device.h>
++#include <linux/of.h>
++#include <linux/io.h>
++#include <linux/clk.h>
++#include <linux/reset.h>
++#include <linux/phy.h>
++#include <linux/phy/phy.h>
++
++#define MTK_XFI_TPHY_NUM_CLOCKS		2
++
++#define REG_DIG_GLB_70			0x0070
++#define  XTP_PCS_RX_EQ_IN_PROGRESS(x)	FIELD_PREP(GENMASK(25, 24), (x))
++#define  XTP_PCS_MODE_MASK		GENMASK(17, 16)
++#define  XTP_PCS_MODE(x)		FIELD_PREP(GENMASK(17, 16), (x))
++#define  XTP_PCS_RST_B			BIT(15)
++#define  XTP_FRC_PCS_RST_B		BIT(14)
++#define  XTP_PCS_PWD_SYNC_MASK		GENMASK(13, 12)
++#define  XTP_PCS_PWD_SYNC(x)		FIELD_PREP(XTP_PCS_PWD_SYNC_MASK, (x))
++#define  XTP_PCS_PWD_ASYNC_MASK		GENMASK(11, 10)
++#define  XTP_PCS_PWD_ASYNC(x)		FIELD_PREP(XTP_PCS_PWD_ASYNC_MASK, (x))
++#define  XTP_FRC_PCS_PWD_ASYNC		BIT(8)
++#define  XTP_PCS_UPDT			BIT(4)
++#define  XTP_PCS_IN_FR_RG		BIT(0)
++
++#define REG_DIG_GLB_F4			0x00f4
++#define  XFI_DPHY_PCS_SEL		BIT(0)
++#define   XFI_DPHY_PCS_SEL_SGMII	FIELD_PREP(XFI_DPHY_PCS_SEL, 1)
++#define   XFI_DPHY_PCS_SEL_USXGMII	FIELD_PREP(XFI_DPHY_PCS_SEL, 0)
++#define  XFI_DPHY_AD_SGDT_FRC_EN	BIT(5)
++
++#define REG_DIG_LN_TRX_40		0x3040
++#define  XTP_LN_FRC_TX_DATA_EN		BIT(29)
++#define  XTP_LN_TX_DATA_EN		BIT(28)
++
++#define REG_DIG_LN_TRX_B0		0x30b0
++#define  XTP_LN_FRC_TX_MACCK_EN		BIT(5)
++#define  XTP_LN_TX_MACCK_EN		BIT(4)
++
++#define REG_ANA_GLB_D0			0x90d0
++#define  XTP_GLB_USXGMII_SEL_MASK	GENMASK(3, 1)
++#define  XTP_GLB_USXGMII_SEL(x)		FIELD_PREP(GENMASK(3, 1), (x))
++#define  XTP_GLB_USXGMII_EN		BIT(0)
++
++struct mtk_xfi_tphy {
++	void __iomem		*base;
++	struct device		*dev;
++	struct reset_control	*reset;
++	struct clk_bulk_data	clocks[MTK_XFI_TPHY_NUM_CLOCKS];
++	bool			da_war;
++};
++
++static void mtk_xfi_tphy_write(struct mtk_xfi_tphy *xfi_tphy, u16 reg,
++			       u32 value)
++{
++	iowrite32(value, xfi_tphy->base + reg);
++}
++
++static void mtk_xfi_tphy_rmw(struct mtk_xfi_tphy *xfi_tphy, u16 reg,
++			     u32 clr, u32 set)
++{
++	u32 val;
++
++	val = ioread32(xfi_tphy->base + reg);
++	val &= ~clr;
++	val |= set;
++	iowrite32(val, xfi_tphy->base + reg);
++}
++
++static void mtk_xfi_tphy_set(struct mtk_xfi_tphy *xfi_tphy, u16 reg,
++			     u32 set)
++{
++	mtk_xfi_tphy_rmw(xfi_tphy, reg, 0, set);
++}
++
++static void mtk_xfi_tphy_clear(struct mtk_xfi_tphy *xfi_tphy, u16 reg,
++			       u32 clr)
++{
++	mtk_xfi_tphy_rmw(xfi_tphy, reg, clr, 0);
++}
++
++static void mtk_xfi_tphy_setup(struct mtk_xfi_tphy *xfi_tphy,
++			       phy_interface_t interface)
++{
++	bool is_2p5g = (interface == PHY_INTERFACE_MODE_2500BASEX);
++	bool is_1g = (interface == PHY_INTERFACE_MODE_1000BASEX ||
++		      interface == PHY_INTERFACE_MODE_SGMII);
++	bool is_10g = (interface == PHY_INTERFACE_MODE_10GBASER ||
++		       interface == PHY_INTERFACE_MODE_USXGMII);
++	bool is_5g = (interface == PHY_INTERFACE_MODE_5GBASER);
++	bool is_xgmii = (is_10g || is_5g);
++
++	dev_dbg(xfi_tphy->dev, "setting up for mode %s\n", phy_modes(interface));
++
++	/* Setup PLL setting */
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x9024, 0x100000, is_10g ? 0x0 : 0x100000);
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x2020, 0x202000, is_5g ? 0x202000 : 0x0);
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x2030, 0x500, is_1g ? 0x0 : 0x500);
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x2034, 0xa00, is_1g ? 0x0 : 0xa00);
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x2040, 0x340000, is_1g ? 0x200000 :
++							     0x140000);
++
++	/* Setup RXFE BW setting */
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x50f0, 0xc10, is_1g ? 0x410 :
++							  is_5g ? 0x800 : 0x400);
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x50e0, 0x4000, is_5g ? 0x0 : 0x4000);
++
++	/* Setup RX CDR setting */
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x506c, 0x30000, is_5g ? 0x0 : 0x30000);
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x5070, 0x670000, is_5g ? 0x620000 : 0x50000);
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x5074, 0x180000, is_5g ? 0x180000 : 0x0);
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x5078, 0xf000400, is_5g ? 0x8000000 :
++							      0x7000400);
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x507c, 0x5000500, is_5g ? 0x4000400 :
++							      0x1000100);
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x5080, 0x1410, is_1g ? 0x400 :
++							   is_5g ? 0x1010 : 0x0);
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x5084, 0x30300, is_1g ? 0x30300 :
++							    is_5g ? 0x30100 :
++								    0x100);
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x5088, 0x60200, is_1g ? 0x20200 :
++							 is_5g ? 0x40000 :
++								 0x20000);
++
++	/* Setting RXFE adaptation range setting */
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x50e4, 0xc0000, is_5g ? 0x0 : 0xc0000);
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x50e8, 0x40000, is_5g ? 0x0 : 0x40000);
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x50ec, 0xa00, is_1g ? 0x200 : 0x800);
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x50a8, 0xee0000, is_5g ? 0x800000 :
++							     0x6e0000);
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x6004, 0x190000, is_5g ? 0x0 : 0x190000);
++	if (is_10g)
++		mtk_xfi_tphy_write(xfi_tphy, 0x00f8, 0x01423342);
++	else if (is_5g)
++		mtk_xfi_tphy_write(xfi_tphy, 0x00f8, 0x00a132a1);
++	else if (is_2p5g)
++		mtk_xfi_tphy_write(xfi_tphy, 0x00f8, 0x009c329c);
++	else
++		mtk_xfi_tphy_write(xfi_tphy, 0x00f8, 0x00fa32fa);
++
++	/* Force SGDT_OUT off and select PCS */
++	mtk_xfi_tphy_rmw(xfi_tphy, REG_DIG_GLB_F4,
++			 XFI_DPHY_AD_SGDT_FRC_EN | XFI_DPHY_PCS_SEL,
++			 XFI_DPHY_AD_SGDT_FRC_EN |
++			 (is_xgmii ? XFI_DPHY_PCS_SEL_USXGMII :
++				     XFI_DPHY_PCS_SEL_SGMII));
++
++
++	/* Force GLB_CKDET_OUT */
++	mtk_xfi_tphy_set(xfi_tphy, 0x0030, 0xc00);
++
++	/* Force AEQ on */
++	mtk_xfi_tphy_write(xfi_tphy, REG_DIG_GLB_70,
++			   XTP_PCS_RX_EQ_IN_PROGRESS(2) |
++			   XTP_PCS_PWD_SYNC(2) |
++			   XTP_PCS_PWD_ASYNC(2));
++
++	usleep_range(1, 5);
++
++	/* Setup TX DA default value */
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x30b0, 0x30, 0x20);
++	mtk_xfi_tphy_write(xfi_tphy, 0x3028, 0x00008a01);
++	mtk_xfi_tphy_write(xfi_tphy, 0x302c, 0x0000a884);
++	mtk_xfi_tphy_write(xfi_tphy, 0x3024, 0x00083002);
++
++	/* Setup RG default value */
++	if (is_xgmii) {
++		mtk_xfi_tphy_write(xfi_tphy, 0x3010, 0x00022220);
++		mtk_xfi_tphy_write(xfi_tphy, 0x5064, 0x0f020a01);
++		mtk_xfi_tphy_write(xfi_tphy, 0x50b4, 0x06100600);
++		if (interface == PHY_INTERFACE_MODE_USXGMII)
++			mtk_xfi_tphy_write(xfi_tphy, 0x3048, 0x40704000);
++		else
++			mtk_xfi_tphy_write(xfi_tphy, 0x3048, 0x47684100);
++	} else {
++		mtk_xfi_tphy_write(xfi_tphy, 0x3010, 0x00011110);
++		mtk_xfi_tphy_write(xfi_tphy, 0x3048, 0x40704000);
++	}
++
++	if (is_1g)
++		mtk_xfi_tphy_write(xfi_tphy, 0x3064, 0x0000c000);
++
++	/* Setup RX EQ initial value */
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x3050, 0xa8000000,
++			 (interface != PHY_INTERFACE_MODE_10GBASER) ?
++			  0xa8000000 : 0x0);
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x3054, 0xaa,
++			 (interface != PHY_INTERFACE_MODE_10GBASER) ?
++			  0xaa : 0x0);
++
++	if (is_xgmii)
++		mtk_xfi_tphy_write(xfi_tphy, 0x306c, 0x00000f00);
++	else if (is_2p5g)
++		mtk_xfi_tphy_write(xfi_tphy, 0x306c, 0x22000f00);
++	else
++		mtk_xfi_tphy_write(xfi_tphy, 0x306c, 0x20200f00);
++
++	if (interface == PHY_INTERFACE_MODE_10GBASER && xfi_tphy->da_war)
++		mtk_xfi_tphy_rmw(xfi_tphy, 0xa008, 0x10000, 0x10000);
++
++	mtk_xfi_tphy_rmw(xfi_tphy, 0xa060, 0x50000, is_xgmii ? 0x40000 :
++							       0x50000);
++
++	/* Setup PHYA speed */
++	mtk_xfi_tphy_rmw(xfi_tphy, REG_ANA_GLB_D0,
++			 XTP_GLB_USXGMII_SEL_MASK | XTP_GLB_USXGMII_EN,
++			 is_10g ?  XTP_GLB_USXGMII_SEL(0) :
++			 is_5g ?   XTP_GLB_USXGMII_SEL(1) :
++			 is_2p5g ? XTP_GLB_USXGMII_SEL(2) :
++				   XTP_GLB_USXGMII_SEL(3));
++	mtk_xfi_tphy_set(xfi_tphy, REG_ANA_GLB_D0, XTP_GLB_USXGMII_EN);
++
++	/* Release reset */
++	mtk_xfi_tphy_set(xfi_tphy, REG_DIG_GLB_70,
++			 XTP_PCS_RST_B | XTP_FRC_PCS_RST_B);
++	usleep_range(150, 500);
++
++	/* Switch to P0 */
++	mtk_xfi_tphy_rmw(xfi_tphy, REG_DIG_GLB_70,
++			 XTP_PCS_PWD_SYNC_MASK |
++			 XTP_PCS_PWD_ASYNC_MASK,
++			 XTP_FRC_PCS_PWD_ASYNC |
++			 XTP_PCS_UPDT | XTP_PCS_IN_FR_RG);
++	usleep_range(1, 5);
++
++	mtk_xfi_tphy_clear(xfi_tphy, REG_DIG_GLB_70, XTP_PCS_UPDT);
++	usleep_range(15, 50);
++
++	if (is_xgmii) {
++		/* Switch to Gen3 */
++		mtk_xfi_tphy_rmw(xfi_tphy, REG_DIG_GLB_70,
++				 XTP_PCS_MODE_MASK | XTP_PCS_UPDT,
++				 XTP_PCS_MODE(2) | XTP_PCS_UPDT);
++	} else {
++		/* Switch to Gen2 */
++		mtk_xfi_tphy_rmw(xfi_tphy, REG_DIG_GLB_70,
++				 XTP_PCS_MODE_MASK | XTP_PCS_UPDT,
++				 XTP_PCS_MODE(1) | XTP_PCS_UPDT);
++	}
++	usleep_range(1, 5);
++
++	mtk_xfi_tphy_clear(xfi_tphy, REG_DIG_GLB_70, XTP_PCS_UPDT);
++
++	usleep_range(100, 500);
++
++	/* Enable MAC CK */
++	mtk_xfi_tphy_set(xfi_tphy, REG_DIG_LN_TRX_B0, XTP_LN_TX_MACCK_EN);
++	mtk_xfi_tphy_clear(xfi_tphy, REG_DIG_GLB_F4, XFI_DPHY_AD_SGDT_FRC_EN);
++
++	/* Enable TX data */
++	mtk_xfi_tphy_set(xfi_tphy, REG_DIG_LN_TRX_40,
++			 XTP_LN_FRC_TX_DATA_EN | XTP_LN_TX_DATA_EN);
++	usleep_range(400, 1000);
++}
++
++static int mtk_xfi_tphy_set_mode(struct phy *phy, enum phy_mode mode, int
++				 submode)
++{
++	struct mtk_xfi_tphy *xfi_tphy = phy_get_drvdata(phy);
++
++	if (mode != PHY_MODE_ETHERNET)
++		return -EINVAL;
++
++	switch (submode) {
++	case PHY_INTERFACE_MODE_1000BASEX:
++	case PHY_INTERFACE_MODE_2500BASEX:
++	case PHY_INTERFACE_MODE_SGMII:
++	case PHY_INTERFACE_MODE_5GBASER:
++	case PHY_INTERFACE_MODE_10GBASER:
++	case PHY_INTERFACE_MODE_USXGMII:
++		mtk_xfi_tphy_setup(xfi_tphy, submode);
++		return 0;
++	default:
++		return -EINVAL;
++	}
++}
++
++static int mtk_xfi_tphy_reset(struct phy *phy)
++{
++	struct mtk_xfi_tphy *xfi_tphy = phy_get_drvdata(phy);
++
++	reset_control_assert(xfi_tphy->reset);
++	usleep_range(100, 500);
++	reset_control_deassert(xfi_tphy->reset);
++	usleep_range(1, 10);
++
++	return 0;
++}
++
++static int mtk_xfi_tphy_power_on(struct phy *phy)
++{
++	struct mtk_xfi_tphy *xfi_tphy = phy_get_drvdata(phy);
++
++	return clk_bulk_prepare_enable(MTK_XFI_TPHY_NUM_CLOCKS, xfi_tphy->clocks);
++}
++
++static int mtk_xfi_tphy_power_off(struct phy *phy)
++{
++	struct mtk_xfi_tphy *xfi_tphy = phy_get_drvdata(phy);
++
++	clk_bulk_disable_unprepare(MTK_XFI_TPHY_NUM_CLOCKS, xfi_tphy->clocks);
++
++	return 0;
++}
++
++static const struct phy_ops mtk_xfi_tphy_ops = {
++	.power_on	= mtk_xfi_tphy_power_on,
++	.power_off	= mtk_xfi_tphy_power_off,
++	.set_mode	= mtk_xfi_tphy_set_mode,
++	.reset		= mtk_xfi_tphy_reset,
++	.owner		= THIS_MODULE,
++};
++
++static int mtk_xfi_tphy_probe(struct platform_device *pdev)
++{
++	struct device_node *np = pdev->dev.of_node;
++	struct phy_provider *phy_provider;
++	struct mtk_xfi_tphy *xfi_tphy;
++	struct phy *phy;
++
++	if (!np)
++		return -ENODEV;
++
++	xfi_tphy = devm_kzalloc(&pdev->dev, sizeof(*xfi_tphy), GFP_KERNEL);
++	if (!xfi_tphy)
++		return -ENOMEM;
++
++	xfi_tphy->base = devm_of_iomap(&pdev->dev, np, 0, NULL);
++	if (!xfi_tphy->base)
++		return -EIO;
++
++	xfi_tphy->dev = &pdev->dev;
++
++	xfi_tphy->clocks[0].id = "topxtal";
++	xfi_tphy->clocks[0].clk = devm_clk_get(&pdev->dev, xfi_tphy->clocks[0].id);
++	if (IS_ERR(xfi_tphy->clocks[0].clk))
++		return PTR_ERR(xfi_tphy->clocks[0].clk);
++
++	xfi_tphy->clocks[1].id = "xfipll";
++	xfi_tphy->clocks[1].clk = devm_clk_get(&pdev->dev, xfi_tphy->clocks[1].id);
++	if (IS_ERR(xfi_tphy->clocks[1].clk))
++		return PTR_ERR(xfi_tphy->clocks[1].clk);
++
++	xfi_tphy->reset = devm_reset_control_get_exclusive(&pdev->dev, NULL);
++	if (IS_ERR(xfi_tphy->reset))
++		return PTR_ERR(xfi_tphy->reset);
++
++	xfi_tphy->da_war = of_property_read_bool(np,
++						 "mediatek,usxgmii-performance-errata");
++
++	phy = devm_phy_create(&pdev->dev, NULL, &mtk_xfi_tphy_ops);
++	if (IS_ERR(phy))
++		return PTR_ERR(phy);
++
++	phy_set_drvdata(phy, xfi_tphy);
++
++	phy_provider = devm_of_phy_provider_register(&pdev->dev,
++						     of_phy_simple_xlate);
++
++	return PTR_ERR_OR_ZERO(phy_provider);
++}
++
++static const struct of_device_id mtk_xfi_tphy_match[] = {
++	{ .compatible = "mediatek,mt7988-xfi-tphy", },
++	{ }
++};
++MODULE_DEVICE_TABLE(of, mtk_xfi_tphy_match);
++
++static struct platform_driver mtk_xfi_tphy_driver = {
++	.probe = mtk_xfi_tphy_probe,
++	.driver = {
++		.name = "mtk-xfi-tphy",
++		.of_match_table = mtk_xfi_tphy_match,
++	},
++};
++module_platform_driver(mtk_xfi_tphy_driver);
++
++MODULE_DESCRIPTION("MediaTek XFI T-PHY driver");
++MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
++MODULE_AUTHOR("Bc-bocun Chen <bc-bocun.chen@mediatek.com>");
++MODULE_LICENSE("GPL");
diff --git a/target/linux/generic/pending-6.1/739-03-net-pcs-pcs-mtk-lynxi-add-platform-driver-for-MT7988.patch b/target/linux/generic/pending-6.1/739-03-net-pcs-pcs-mtk-lynxi-add-platform-driver-for-MT7988.patch
new file mode 100644
index 00000000000000..adb95e9587f1f3
--- /dev/null
+++ b/target/linux/generic/pending-6.1/739-03-net-pcs-pcs-mtk-lynxi-add-platform-driver-for-MT7988.patch
@@ -0,0 +1,371 @@
+From 4b1a2716299c0e96a698044aebf3f80513509ae7 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Tue, 12 Dec 2023 03:47:18 +0000
+Subject: [PATCH 3/5] net: pcs: pcs-mtk-lynxi: add platform driver for MT7988
+
+Introduce a proper platform MFD driver for the LynxI (H)SGMII PCS which
+is going to initially be used for the MT7988 SoC.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/net/pcs/pcs-mtk-lynxi.c   | 227 ++++++++++++++++++++++++++++--
+ include/linux/pcs/pcs-mtk-lynxi.h |  11 ++
+ 2 files changed, 227 insertions(+), 11 deletions(-)
+
+--- a/drivers/net/pcs/pcs-mtk-lynxi.c
++++ b/drivers/net/pcs/pcs-mtk-lynxi.c
+@@ -1,6 +1,6 @@
+ // SPDX-License-Identifier: GPL-2.0
+ // Copyright (c) 2018-2019 MediaTek Inc.
+-/* A library for MediaTek SGMII circuit
++/* A library and platform driver for the MediaTek LynxI SGMII circuit
+  *
+  * Author: Sean Wang <sean.wang@mediatek.com>
+  * Author: Alexander Couzens <lynxis@fe80.eu>
+@@ -8,11 +8,17 @@
+  *
+  */
+ 
++#include <linux/clk.h>
+ #include <linux/mdio.h>
++#include <linux/mfd/syscon.h>
++#include <linux/mutex.h>
+ #include <linux/of.h>
++#include <linux/of_platform.h>
+ #include <linux/pcs/pcs-mtk-lynxi.h>
+ #include <linux/phylink.h>
++#include <linux/platform_device.h>
+ #include <linux/regmap.h>
++#include <linux/reset.h>
+ 
+ /* SGMII subsystem config registers */
+ /* BMCR (low 16) BMSR (high 16) */
+@@ -65,6 +71,8 @@
+ #define SGMII_PN_SWAP_MASK		GENMASK(1, 0)
+ #define SGMII_PN_SWAP_TX_RX		(BIT(0) | BIT(1))
+ 
++#define MTK_NETSYS_V3_AMA_RGC3		0x128
++
+ /* struct mtk_pcs_lynxi -  This structure holds each sgmii regmap andassociated
+  *                         data
+  * @regmap:                The register map pointing at the range used to setup
+@@ -74,15 +82,29 @@
+  * @interface:             Currently configured interface mode
+  * @pcs:                   Phylink PCS structure
+  * @flags:                 Flags indicating hardware properties
++ * @rstc:                  Reset controller
++ * @sgmii_sel:             SGMII Register Clock
++ * @sgmii_rx:              SGMII RX Clock
++ * @sgmii_tx:              SGMII TX Clock
++ * @node:                  List node
+  */
+ struct mtk_pcs_lynxi {
+ 	struct regmap		*regmap;
++	struct device		*dev;
+ 	u32			ana_rgc3;
+ 	phy_interface_t		interface;
+ 	struct			phylink_pcs pcs;
+ 	u32			flags;
++	struct reset_control	*rstc;
++	struct clk		*sgmii_sel;
++	struct clk		*sgmii_rx;
++	struct clk		*sgmii_tx;
++	struct list_head	node;
+ };
+ 
++static LIST_HEAD(mtk_pcs_lynxi_instances);
++static DEFINE_MUTEX(instance_mutex);
++
+ static struct mtk_pcs_lynxi *pcs_to_mtk_pcs_lynxi(struct phylink_pcs *pcs)
+ {
+ 	return container_of(pcs, struct mtk_pcs_lynxi, pcs);
+@@ -102,6 +124,17 @@ static void mtk_pcs_lynxi_get_state(stru
+ 					 FIELD_GET(SGMII_LPA, adv));
+ }
+ 
++static void mtk_sgmii_reset(struct mtk_pcs_lynxi *mpcs)
++{
++	if (!mpcs->rstc)
++		return;
++
++	reset_control_assert(mpcs->rstc);
++	udelay(100);
++	reset_control_deassert(mpcs->rstc);
++	mdelay(1);
++}
++
+ static int mtk_pcs_lynxi_config(struct phylink_pcs *pcs, unsigned int neg_mode,
+ 				phy_interface_t interface,
+ 				const unsigned long *advertising,
+@@ -148,6 +181,7 @@ static int mtk_pcs_lynxi_config(struct p
+ 				SGMII_PHYA_PWD);
+ 
+ 		/* Reset SGMII PCS state */
++		mtk_sgmii_reset(mpcs);
+ 		regmap_set_bits(mpcs->regmap, SGMSYS_RESERVED_0,
+ 				SGMII_SW_RESET);
+ 
+@@ -234,10 +268,29 @@ static void mtk_pcs_lynxi_link_up(struct
+ 	}
+ }
+ 
++static int mtk_pcs_lynxi_enable(struct phylink_pcs *pcs)
++{
++	struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs);
++
++	if (mpcs->sgmii_tx && mpcs->sgmii_rx) {
++		clk_prepare_enable(mpcs->sgmii_rx);
++		clk_prepare_enable(mpcs->sgmii_tx);
++	}
++
++	return 0;
++}
++
+ static void mtk_pcs_lynxi_disable(struct phylink_pcs *pcs)
+ {
+ 	struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs);
+ 
++	regmap_set_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, SGMII_PHYA_PWD);
++
++	if (mpcs->sgmii_tx && mpcs->sgmii_rx) {
++		clk_disable_unprepare(mpcs->sgmii_tx);
++		clk_disable_unprepare(mpcs->sgmii_rx);
++	}
++
+ 	mpcs->interface = PHY_INTERFACE_MODE_NA;
+ }
+ 
+@@ -247,11 +300,12 @@ static const struct phylink_pcs_ops mtk_
+ 	.pcs_an_restart = mtk_pcs_lynxi_restart_an,
+ 	.pcs_link_up = mtk_pcs_lynxi_link_up,
+ 	.pcs_disable = mtk_pcs_lynxi_disable,
++	.pcs_enable = mtk_pcs_lynxi_enable,
+ };
+ 
+-struct phylink_pcs *mtk_pcs_lynxi_create(struct device *dev,
+-					 struct regmap *regmap, u32 ana_rgc3,
+-					 u32 flags)
++static struct phylink_pcs *mtk_pcs_lynxi_init(struct device *dev, struct regmap *regmap,
++					      u32 ana_rgc3, u32 flags,
++					      struct mtk_pcs_lynxi *prealloc)
+ {
+ 	struct mtk_pcs_lynxi *mpcs;
+ 	u32 id, ver;
+@@ -259,29 +313,33 @@ struct phylink_pcs *mtk_pcs_lynxi_create
+ 
+ 	ret = regmap_read(regmap, SGMSYS_PCS_DEVICE_ID, &id);
+ 	if (ret < 0)
+-		return NULL;
++		return ERR_PTR(ret);
+ 
+ 	if (id != SGMII_LYNXI_DEV_ID) {
+ 		dev_err(dev, "unknown PCS device id %08x\n", id);
+-		return NULL;
++		return ERR_PTR(-ENODEV);
+ 	}
+ 
+ 	ret = regmap_read(regmap, SGMSYS_PCS_SCRATCH, &ver);
+ 	if (ret < 0)
+-		return NULL;
++		return ERR_PTR(ret);
+ 
+ 	ver = FIELD_GET(SGMII_DEV_VERSION, ver);
+ 	if (ver != 0x1) {
+ 		dev_err(dev, "unknown PCS device version %04x\n", ver);
+-		return NULL;
++		return ERR_PTR(-ENODEV);
+ 	}
+ 
+ 	dev_dbg(dev, "MediaTek LynxI SGMII PCS (id 0x%08x, ver 0x%04x)\n", id,
+ 		ver);
+ 
+-	mpcs = kzalloc(sizeof(*mpcs), GFP_KERNEL);
+-	if (!mpcs)
+-		return NULL;
++	if (prealloc) {
++		mpcs = prealloc;
++	} else {
++		mpcs = kzalloc(sizeof(*mpcs), GFP_KERNEL);
++		if (!mpcs)
++			return ERR_PTR(-ENOMEM);
++	};
+ 
+ 	mpcs->ana_rgc3 = ana_rgc3;
+ 	mpcs->regmap = regmap;
+@@ -292,6 +350,13 @@ struct phylink_pcs *mtk_pcs_lynxi_create
+ 	mpcs->interface = PHY_INTERFACE_MODE_NA;
+ 
+ 	return &mpcs->pcs;
++};
++
++struct phylink_pcs *mtk_pcs_lynxi_create(struct device *dev,
++					 struct regmap *regmap, u32 ana_rgc3,
++					 u32 flags)
++{
++	return mtk_pcs_lynxi_init(dev, regmap, ana_rgc3, flags, NULL);
+ }
+ EXPORT_SYMBOL(mtk_pcs_lynxi_create);
+ 
+@@ -304,4 +369,144 @@ void mtk_pcs_lynxi_destroy(struct phylin
+ }
+ EXPORT_SYMBOL(mtk_pcs_lynxi_destroy);
+ 
++static int mtk_pcs_lynxi_probe(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct device_node *np = dev->of_node;
++	struct mtk_pcs_lynxi *mpcs;
++	struct phylink_pcs *pcs;
++	struct regmap *regmap;
++	u32 flags = 0;
++
++	mpcs = devm_kzalloc(dev, sizeof(*mpcs), GFP_KERNEL);
++	if (!mpcs)
++		return -ENOMEM;
++
++	mpcs->dev = dev;
++	regmap = syscon_node_to_regmap(np->parent);
++	if (IS_ERR(regmap))
++		return PTR_ERR(regmap);
++
++	if (of_property_read_bool(np->parent, "mediatek,pnswap"))
++		flags |= MTK_SGMII_FLAG_PN_SWAP;
++
++	mpcs->rstc = of_reset_control_get_shared(np->parent, NULL);
++	if (IS_ERR(mpcs->rstc))
++		return PTR_ERR(mpcs->rstc);
++
++	reset_control_deassert(mpcs->rstc);
++	mpcs->sgmii_sel = devm_clk_get_enabled(dev, "sgmii_sel");
++	if (IS_ERR(mpcs->sgmii_sel))
++		return PTR_ERR(mpcs->sgmii_sel);
++
++	mpcs->sgmii_rx = devm_clk_get(dev, "sgmii_rx");
++	if (IS_ERR(mpcs->sgmii_rx))
++		return PTR_ERR(mpcs->sgmii_rx);
++
++	mpcs->sgmii_tx = devm_clk_get(dev, "sgmii_tx");
++	if (IS_ERR(mpcs->sgmii_tx))
++		return PTR_ERR(mpcs->sgmii_tx);
++
++	pcs = mtk_pcs_lynxi_init(dev, regmap, (uintptr_t)of_device_get_match_data(dev),
++				 flags, mpcs);
++	if (IS_ERR(pcs))
++		return PTR_ERR(pcs);
++
++	regmap_set_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, SGMII_PHYA_PWD);
++
++	platform_set_drvdata(pdev, mpcs);
++
++	mutex_lock(&instance_mutex);
++	list_add_tail(&mpcs->node, &mtk_pcs_lynxi_instances);
++	mutex_unlock(&instance_mutex);
++
++	return 0;
++}
++
++static int mtk_pcs_lynxi_remove(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct mtk_pcs_lynxi *cur, *tmp;
++
++	mutex_lock(&instance_mutex);
++	list_for_each_entry_safe(cur, tmp, &mtk_pcs_lynxi_instances, node)
++		if (cur->dev == dev) {
++			list_del(&cur->node);
++			kfree(cur);
++			break;
++		}
++	mutex_unlock(&instance_mutex);
++
++	return 0;
++}
++
++static const struct of_device_id mtk_pcs_lynxi_of_match[] = {
++	{ .compatible = "mediatek,mt7988-sgmii", .data = (void *)MTK_NETSYS_V3_AMA_RGC3 },
++	{ /* sentinel */ },
++};
++MODULE_DEVICE_TABLE(of, mtk_pcs_lynxi_of_match);
++
++struct phylink_pcs *mtk_pcs_lynxi_get(struct device *dev, struct device_node *np)
++{
++	struct platform_device *pdev;
++	struct mtk_pcs_lynxi *mpcs;
++
++	if (!np)
++		return NULL;
++
++	if (!of_device_is_available(np))
++		return ERR_PTR(-ENODEV);
++
++	if (!of_match_node(mtk_pcs_lynxi_of_match, np))
++		return ERR_PTR(-EINVAL);
++
++	pdev = of_find_device_by_node(np);
++	if (!pdev || !platform_get_drvdata(pdev)) {
++		if (pdev)
++			put_device(&pdev->dev);
++		return ERR_PTR(-EPROBE_DEFER);
++	}
++
++	mpcs = platform_get_drvdata(pdev);
++	device_link_add(dev, mpcs->dev, DL_FLAG_AUTOREMOVE_CONSUMER);
++
++	return &mpcs->pcs;
++}
++EXPORT_SYMBOL(mtk_pcs_lynxi_get);
++
++void mtk_pcs_lynxi_put(struct phylink_pcs *pcs)
++{
++	struct mtk_pcs_lynxi *cur, *mpcs = NULL;
++
++	if (!pcs)
++		return;
++
++	mutex_lock(&instance_mutex);
++	list_for_each_entry(cur, &mtk_pcs_lynxi_instances, node)
++		if (pcs == &cur->pcs) {
++			mpcs = cur;
++			break;
++		}
++	mutex_unlock(&instance_mutex);
++
++	if (WARN_ON(!mpcs))
++		return;
++
++	put_device(mpcs->dev);
++}
++EXPORT_SYMBOL(mtk_pcs_lynxi_put);
++
++static struct platform_driver mtk_pcs_lynxi_driver = {
++	.driver = {
++		.name			= "mtk-pcs-lynxi",
++		.suppress_bind_attrs	= true,
++		.of_match_table		= mtk_pcs_lynxi_of_match,
++	},
++	.probe = mtk_pcs_lynxi_probe,
++	.remove = mtk_pcs_lynxi_remove,
++};
++module_platform_driver(mtk_pcs_lynxi_driver);
++
++MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
++MODULE_DESCRIPTION("MediaTek LynxI HSGMII PCS");
+ MODULE_LICENSE("GPL");
+--- a/include/linux/pcs/pcs-mtk-lynxi.h
++++ b/include/linux/pcs/pcs-mtk-lynxi.h
+@@ -10,4 +10,15 @@ struct phylink_pcs *mtk_pcs_lynxi_create
+ 					 struct regmap *regmap,
+ 					 u32 ana_rgc3, u32 flags);
+ void mtk_pcs_lynxi_destroy(struct phylink_pcs *pcs);
++
++#if IS_ENABLED(CONFIG_PCS_MTK_LYNXI)
++struct phylink_pcs *mtk_pcs_lynxi_get(struct device *dev, struct device_node *np);
++void mtk_pcs_lynxi_put(struct phylink_pcs *pcs);
++#else
++static inline struct phylink_pcs *mtk_pcs_lynxi_get(struct device *dev, struct device_node *np)
++{
++	return NULL;
++}
++static inline void mtk_pcs_lynxi_put(struct phylink_pcs *pcs) { }
++#endif /* IS_ENABLED(CONFIG_PCS_MTK_LYNXI) */
+ #endif
diff --git a/target/linux/generic/pending-6.1/739-04-dt-bindings-net-pcs-add-bindings-for-MediaTek-USXGMI.patch b/target/linux/generic/pending-6.1/739-04-dt-bindings-net-pcs-add-bindings-for-MediaTek-USXGMI.patch
new file mode 100644
index 00000000000000..215bd2ca2ef415
--- /dev/null
+++ b/target/linux/generic/pending-6.1/739-04-dt-bindings-net-pcs-add-bindings-for-MediaTek-USXGMI.patch
@@ -0,0 +1,81 @@
+From 7d88d79c0f65b27a92754d7547f7af098b3de67b Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Tue, 12 Dec 2023 03:47:31 +0000
+Subject: [PATCH 4/5] dt-bindings: net: pcs: add bindings for MediaTek USXGMII
+ PCS
+
+MediaTek's USXGMII can be found in the MT7988 SoC. We need to access
+it in order to configure and monitor the Ethernet SerDes link in
+USXGMII, 10GBase-R and 5GBase-R mode. By including a wrapped
+legacy 1000Base-X/2500Base-X/Cisco SGMII LynxI PCS as well, those
+interface modes are also available.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ .../bindings/net/pcs/mediatek,usxgmii.yaml    | 60 +++++++++++++++++++
+ 1 file changed, 60 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml
+@@ -0,0 +1,60 @@
++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/net/pcs/mediatek,usxgmii.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: MediaTek USXGMII PCS
++
++maintainers:
++  - Daniel Golle <daniel@makrotopia.org>
++
++description:
++  The MediaTek USXGMII PCS provides physical link control and status
++  for USXGMII, 10GBase-R and 5GBase-R links on the SerDes interfaces
++  provided by the PEXTP PHY.
++  In order to also support legacy 2500Base-X, 1000Base-X and Cisco
++  SGMII an existing mediatek,*-sgmiisys LynxI PCS is wrapped to
++  provide those interfaces modes on the same SerDes interfaces shared
++  with the USXGMII PCS.
++
++properties:
++  $nodename:
++    pattern: "^pcs@[0-9a-f]+$"
++
++  compatible:
++    const: mediatek,mt7988-usxgmiisys
++
++  reg:
++    maxItems: 1
++
++  clocks:
++    items:
++      - description: USXGMII top-level clock
++
++  resets:
++    items:
++      - description: XFI reset
++
++required:
++  - compatible
++  - reg
++  - clocks
++  - resets
++
++additionalProperties: false
++
++examples:
++  - |
++    #include <dt-bindings/clock/mediatek,mt7988-clk.h>
++    #define MT7988_TOPRGU_XFI0_GRST 12
++    soc {
++      #address-cells = <2>;
++      #size-cells = <2>;
++        usxgmiisys0: pcs@10080000 {
++          compatible = "mediatek,mt7988-usxgmiisys";
++          reg = <0 0x10080000 0 0x1000>;
++          clocks = <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>;
++          resets = <&watchdog MT7988_TOPRGU_XFI0_GRST>;
++        };
++    };
diff --git a/target/linux/generic/pending-6.1/739-05-net-pcs-add-driver-for-MediaTek-USXGMII-PCS.patch b/target/linux/generic/pending-6.1/739-05-net-pcs-add-driver-for-MediaTek-USXGMII-PCS.patch
new file mode 100644
index 00000000000000..5bd2850fec2397
--- /dev/null
+++ b/target/linux/generic/pending-6.1/739-05-net-pcs-add-driver-for-MediaTek-USXGMII-PCS.patch
@@ -0,0 +1,547 @@
+From dde0e95fff92e9f5009f3bea75278e0e34a48822 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Tue, 12 Dec 2023 03:47:47 +0000
+Subject: [PATCH 5/5] net: pcs: add driver for MediaTek USXGMII PCS
+
+Add driver for USXGMII PCS found in the MediaTek MT7988 SoC and supporting
+USXGMII, 10GBase-R and 5GBase-R interface modes.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ MAINTAINERS                         |   2 +
+ drivers/net/pcs/Kconfig             |  11 +
+ drivers/net/pcs/Makefile            |   1 +
+ drivers/net/pcs/pcs-mtk-usxgmii.c   | 456 ++++++++++++++++++++++++++++
+ include/linux/pcs/pcs-mtk-usxgmii.h |  27 ++
+ 5 files changed, 497 insertions(+)
+ create mode 100644 drivers/net/pcs/pcs-mtk-usxgmii.c
+ create mode 100644 include/linux/pcs/pcs-mtk-usxgmii.h
+
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -12934,7 +12934,9 @@ M:	Daniel Golle <daniel@makrotopia.org>
+ L:	netdev@vger.kernel.org
+ S:	Maintained
+ F:	drivers/net/pcs/pcs-mtk-lynxi.c
++F:	drivers/net/pcs/pcs-mtk-usxgmii.c
+ F:	include/linux/pcs/pcs-mtk-lynxi.h
++F:	include/linux/pcs/pcs-mtk-usxgmii.h
+ 
+ MEDIATEK I2C CONTROLLER DRIVER
+ M:	Qii Wang <qii.wang@mediatek.com>
+--- a/drivers/net/pcs/Kconfig
++++ b/drivers/net/pcs/Kconfig
+@@ -18,6 +18,17 @@ config PCS_LYNX
+ 	  This module provides helpers to phylink for managing the Lynx PCS
+ 	  which is part of the Layerscape and QorIQ Ethernet SERDES.
+ 
++config PCS_MTK_USXGMII
++	tristate "MediaTek USXGMII PCS"
++	select PCS_MTK_LYNXI
++	select PHY_MTK_PEXTP
++	select PHYLINK
++	help
++	  This module provides a driver for MediaTek's USXGMII PCS supporting
++	  10GBase-R, 5GBase-R and USXGMII interface modes.
++	  1000Base-X, 2500Base-X and Cisco SGMII are supported on the same
++	  differential pairs via an embedded LynxI PHY.
++
+ config PCS_RZN1_MIIC
+ 	tristate "Renesas RZ/N1 MII converter"
+ 	depends on OF && (ARCH_RZN1 || COMPILE_TEST)
+--- a/drivers/net/pcs/Makefile
++++ b/drivers/net/pcs/Makefile
+@@ -8,3 +8,4 @@ obj-$(CONFIG_PCS_LYNX)		+= pcs-lynx.o
+ obj-$(CONFIG_PCS_RZN1_MIIC)	+= pcs-rzn1-miic.o
+ obj-$(CONFIG_PCS_ALTERA_TSE)	+= pcs-altera-tse.o
+ obj-$(CONFIG_PCS_MTK_LYNXI)	+= pcs-mtk-lynxi.o
++obj-$(CONFIG_PCS_MTK_USXGMII)	+= pcs-mtk-usxgmii.o
+--- /dev/null
++++ b/drivers/net/pcs/pcs-mtk-usxgmii.c
+@@ -0,0 +1,456 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2023 MediaTek Inc.
++ * Author: Henry Yen <henry.yen@mediatek.com>
++ *         Daniel Golle <daniel@makrotopia.org>
++ */
++
++#include <linux/clk.h>
++#include <linux/io.h>
++#include <linux/mfd/syscon.h>
++#include <linux/mdio.h>
++#include <linux/mutex.h>
++#include <linux/of.h>
++#include <linux/of_platform.h>
++#include <linux/reset.h>
++#include <linux/pcs/pcs-mtk-usxgmii.h>
++#include <linux/platform_device.h>
++
++/* USXGMII subsystem config registers */
++/* Register to control speed */
++#define RG_PHY_TOP_SPEED_CTRL1			0x80c
++#define USXGMII_RATE_UPDATE_MODE		BIT(31)
++#define USXGMII_MAC_CK_GATED			BIT(29)
++#define USXGMII_IF_FORCE_EN			BIT(28)
++#define USXGMII_RATE_ADAPT_MODE			GENMASK(10, 8)
++#define USXGMII_RATE_ADAPT_MODE_X1		0
++#define USXGMII_RATE_ADAPT_MODE_X2		1
++#define USXGMII_RATE_ADAPT_MODE_X4		2
++#define USXGMII_RATE_ADAPT_MODE_X10		3
++#define USXGMII_RATE_ADAPT_MODE_X100		4
++#define USXGMII_RATE_ADAPT_MODE_X5		5
++#define USXGMII_RATE_ADAPT_MODE_X50		6
++#define USXGMII_XFI_RX_MODE			GENMASK(6, 4)
++#define USXGMII_XFI_TX_MODE			GENMASK(2, 0)
++#define USXGMII_XFI_MODE_10G			0
++#define USXGMII_XFI_MODE_5G			1
++#define USXGMII_XFI_MODE_2P5G			3
++
++/* Register to control PCS AN */
++#define RG_PCS_AN_CTRL0				0x810
++#define USXGMII_AN_RESTART			BIT(31)
++#define USXGMII_AN_SYNC_CNT			GENMASK(30, 11)
++#define USXGMII_AN_ENABLE			BIT(0)
++
++#define RG_PCS_AN_CTRL2				0x818
++#define USXGMII_LINK_TIMER_IDLE_DETECT		GENMASK(29, 20)
++#define USXGMII_LINK_TIMER_COMP_ACK_DETECT	GENMASK(19, 10)
++#define USXGMII_LINK_TIMER_AN_RESTART		GENMASK(9, 0)
++
++/* Register to read PCS AN status */
++#define RG_PCS_AN_STS0				0x81c
++#define USXGMII_LPA				GENMASK(15, 0)
++#define USXGMII_LPA_LATCH			BIT(31)
++
++/* Register to read PCS link status */
++#define RG_PCS_RX_STATUS0			0x904
++#define RG_PCS_RX_STATUS_UPDATE			BIT(16)
++#define RG_PCS_RX_LINK_STATUS			BIT(2)
++
++/* struct mtk_usxgmii_pcs - This structure holds each usxgmii PCS
++ * @pcs:		Phylink PCS structure
++ * @dev:		Pointer to device structure
++ * @base:		IO memory to access PCS hardware
++ * @clk:		Pointer to USXGMII clk
++ * @reset:		Pointer to USXGMII reset control
++ * @interface:		Currently selected interface mode
++ * @neg_mode:		Currently used phylink neg_mode
++ * @node:		List node
++ */
++struct mtk_usxgmii_pcs {
++	struct phylink_pcs		pcs;
++	struct device			*dev;
++	void __iomem			*base;
++	struct clk			*clk;
++	struct reset_control		*reset;
++	phy_interface_t			interface;
++	unsigned int			neg_mode;
++	struct list_head		node;
++};
++
++static LIST_HEAD(mtk_usxgmii_pcs_instances);
++static DEFINE_MUTEX(instance_mutex);
++
++static u32 mtk_r32(struct mtk_usxgmii_pcs *mpcs, unsigned int reg)
++{
++	return ioread32(mpcs->base + reg);
++}
++
++static void mtk_m32(struct mtk_usxgmii_pcs *mpcs, unsigned int reg, u32 mask, u32 set)
++{
++	u32 val;
++
++	val = ioread32(mpcs->base + reg);
++	val &= ~mask;
++	val |= set;
++	iowrite32(val, mpcs->base + reg);
++}
++
++static struct mtk_usxgmii_pcs *pcs_to_mtk_usxgmii_pcs(struct phylink_pcs *pcs)
++{
++	return container_of(pcs, struct mtk_usxgmii_pcs, pcs);
++}
++
++static void mtk_usxgmii_reset(struct mtk_usxgmii_pcs *mpcs)
++{
++	reset_control_assert(mpcs->reset);
++	udelay(100);
++	reset_control_deassert(mpcs->reset);
++
++	mdelay(10);
++}
++
++static int mtk_usxgmii_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
++				  phy_interface_t interface,
++				  const unsigned long *advertising,
++				  bool permit_pause_to_mac)
++{
++	struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
++	unsigned int an_ctrl = 0, link_timer = 0, xfi_mode = 0, adapt_mode = 0;
++	bool mode_changed = false;
++
++	if (interface == PHY_INTERFACE_MODE_USXGMII) {
++		an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0x1FF) | USXGMII_AN_ENABLE;
++		link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x7B) |
++			     FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x7B) |
++			     FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x7B);
++		xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_MODE_10G) |
++			   FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_MODE_10G);
++	} else if (interface == PHY_INTERFACE_MODE_10GBASER) {
++		an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0x1FF);
++		link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x7B) |
++			     FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x7B) |
++			     FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x7B);
++		xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_MODE_10G) |
++			   FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_MODE_10G);
++		adapt_mode = USXGMII_RATE_UPDATE_MODE;
++	} else if (interface == PHY_INTERFACE_MODE_5GBASER) {
++		an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0xFF);
++		link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x3D) |
++			     FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x3D) |
++			     FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x3D);
++		xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_MODE_5G) |
++			   FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_MODE_5G);
++		adapt_mode = USXGMII_RATE_UPDATE_MODE;
++	} else {
++		return -EINVAL;
++	}
++
++	adapt_mode |= FIELD_PREP(USXGMII_RATE_ADAPT_MODE, USXGMII_RATE_ADAPT_MODE_X1);
++
++	if (mpcs->interface != interface) {
++		mpcs->interface = interface;
++		mode_changed = true;
++	}
++
++	mtk_usxgmii_reset(mpcs);
++
++	/* Setup USXGMII AN ctrl */
++	mtk_m32(mpcs, RG_PCS_AN_CTRL0,
++		USXGMII_AN_SYNC_CNT | USXGMII_AN_ENABLE,
++		an_ctrl);
++
++	mtk_m32(mpcs, RG_PCS_AN_CTRL2,
++		USXGMII_LINK_TIMER_IDLE_DETECT |
++		USXGMII_LINK_TIMER_COMP_ACK_DETECT |
++		USXGMII_LINK_TIMER_AN_RESTART,
++		link_timer);
++
++	mpcs->neg_mode = neg_mode;
++
++	/* Gated MAC CK */
++	mtk_m32(mpcs, RG_PHY_TOP_SPEED_CTRL1,
++		USXGMII_MAC_CK_GATED, USXGMII_MAC_CK_GATED);
++
++	/* Enable interface force mode */
++	mtk_m32(mpcs, RG_PHY_TOP_SPEED_CTRL1,
++		USXGMII_IF_FORCE_EN, USXGMII_IF_FORCE_EN);
++
++	/* Setup USXGMII adapt mode */
++	mtk_m32(mpcs, RG_PHY_TOP_SPEED_CTRL1,
++		USXGMII_RATE_UPDATE_MODE | USXGMII_RATE_ADAPT_MODE,
++		adapt_mode);
++
++	/* Setup USXGMII speed */
++	mtk_m32(mpcs, RG_PHY_TOP_SPEED_CTRL1,
++		USXGMII_XFI_RX_MODE | USXGMII_XFI_TX_MODE,
++		xfi_mode);
++
++	usleep_range(1, 10);
++
++	/* Un-gated MAC CK */
++	mtk_m32(mpcs, RG_PHY_TOP_SPEED_CTRL1, USXGMII_MAC_CK_GATED, 0);
++
++	usleep_range(1, 10);
++
++	/* Disable interface force mode for the AN mode */
++	if (an_ctrl & USXGMII_AN_ENABLE)
++		mtk_m32(mpcs, RG_PHY_TOP_SPEED_CTRL1, USXGMII_IF_FORCE_EN, 0);
++
++	return mode_changed;
++}
++
++static void mtk_usxgmii_pcs_get_fixed_speed(struct mtk_usxgmii_pcs *mpcs,
++					    struct phylink_link_state *state)
++{
++	u32 val = mtk_r32(mpcs, RG_PHY_TOP_SPEED_CTRL1);
++	int speed;
++
++	/* Calculate speed from interface speed and rate adapt mode */
++	switch (FIELD_GET(USXGMII_XFI_RX_MODE, val)) {
++	case USXGMII_XFI_MODE_10G:
++		speed = 10000;
++		break;
++	case USXGMII_XFI_MODE_5G:
++		speed = 5000;
++		break;
++	case USXGMII_XFI_MODE_2P5G:
++		speed = 2500;
++		break;
++	default:
++		state->speed = SPEED_UNKNOWN;
++		return;
++	}
++
++	switch (FIELD_GET(USXGMII_RATE_ADAPT_MODE, val)) {
++	case USXGMII_RATE_ADAPT_MODE_X100:
++		speed /= 100;
++		break;
++	case USXGMII_RATE_ADAPT_MODE_X50:
++		speed /= 50;
++		break;
++	case USXGMII_RATE_ADAPT_MODE_X10:
++		speed /= 10;
++		break;
++	case USXGMII_RATE_ADAPT_MODE_X5:
++		speed /= 5;
++		break;
++	case USXGMII_RATE_ADAPT_MODE_X4:
++		speed /= 4;
++		break;
++	case USXGMII_RATE_ADAPT_MODE_X2:
++		speed /= 2;
++		break;
++	case USXGMII_RATE_ADAPT_MODE_X1:
++		break;
++	default:
++		state->speed = SPEED_UNKNOWN;
++		return;
++	}
++
++	state->speed = speed;
++	state->duplex = DUPLEX_FULL;
++}
++
++static void mtk_usxgmii_pcs_get_an_state(struct mtk_usxgmii_pcs *mpcs,
++					 struct phylink_link_state *state)
++{
++	u16 lpa;
++
++	/* Refresh LPA by toggling LPA_LATCH */
++	mtk_m32(mpcs, RG_PCS_AN_STS0, USXGMII_LPA_LATCH, USXGMII_LPA_LATCH);
++	ndelay(1020);
++	mtk_m32(mpcs, RG_PCS_AN_STS0, USXGMII_LPA_LATCH, 0);
++	ndelay(1020);
++	lpa = FIELD_GET(USXGMII_LPA, mtk_r32(mpcs, RG_PCS_AN_STS0));
++
++	phylink_decode_usxgmii_word(state, lpa);
++}
++
++static void mtk_usxgmii_pcs_get_state(struct phylink_pcs *pcs,
++				      struct phylink_link_state *state)
++{
++	struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
++
++	/* Refresh USXGMII link status by toggling RG_PCS_AN_STATUS_UPDATE */
++	mtk_m32(mpcs, RG_PCS_RX_STATUS0, RG_PCS_RX_STATUS_UPDATE,
++		RG_PCS_RX_STATUS_UPDATE);
++	ndelay(1020);
++	mtk_m32(mpcs, RG_PCS_RX_STATUS0, RG_PCS_RX_STATUS_UPDATE, 0);
++	ndelay(1020);
++
++	/* Read USXGMII link status */
++	state->link = FIELD_GET(RG_PCS_RX_LINK_STATUS,
++				mtk_r32(mpcs, RG_PCS_RX_STATUS0));
++
++	/* Continuously repeat re-configuration sequence until link comes up */
++	if (!state->link) {
++		mtk_usxgmii_pcs_config(pcs, mpcs->neg_mode,
++				       state->interface, NULL, false);
++		return;
++	}
++
++	if (FIELD_GET(USXGMII_AN_ENABLE, mtk_r32(mpcs, RG_PCS_AN_CTRL0)))
++		mtk_usxgmii_pcs_get_an_state(mpcs, state);
++	else
++		mtk_usxgmii_pcs_get_fixed_speed(mpcs, state);
++}
++
++static void mtk_usxgmii_pcs_restart_an(struct phylink_pcs *pcs)
++{
++	struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
++
++	mtk_m32(mpcs, RG_PCS_AN_CTRL0, USXGMII_AN_RESTART, USXGMII_AN_RESTART);
++}
++
++static void mtk_usxgmii_pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,
++				    phy_interface_t interface,
++				    int speed, int duplex)
++{
++	/* Reconfiguring USXGMII to ensure the quality of the RX signal
++	 * after the line side link up.
++	 */
++	mtk_usxgmii_pcs_config(pcs, neg_mode, interface, NULL, false);
++}
++
++static void mtk_usxgmii_pcs_disable(struct phylink_pcs *pcs)
++{
++	struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
++
++	mpcs->interface = PHY_INTERFACE_MODE_NA;
++	mpcs->neg_mode = -1;
++}
++
++static const struct phylink_pcs_ops mtk_usxgmii_pcs_ops = {
++	.pcs_config = mtk_usxgmii_pcs_config,
++	.pcs_get_state = mtk_usxgmii_pcs_get_state,
++	.pcs_an_restart = mtk_usxgmii_pcs_restart_an,
++	.pcs_link_up = mtk_usxgmii_pcs_link_up,
++	.pcs_disable = mtk_usxgmii_pcs_disable,
++};
++
++static int mtk_usxgmii_probe(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct mtk_usxgmii_pcs *mpcs;
++
++	mpcs = devm_kzalloc(dev, sizeof(*mpcs), GFP_KERNEL);
++	if (!mpcs)
++		return -ENOMEM;
++
++	mpcs->base = devm_platform_ioremap_resource(pdev, 0);
++	if (IS_ERR(mpcs->base))
++		return PTR_ERR(mpcs->base);
++
++	mpcs->dev = dev;
++	mpcs->pcs.ops = &mtk_usxgmii_pcs_ops;
++	mpcs->pcs.poll = true;
++	mpcs->pcs.neg_mode = true;
++	mpcs->interface = PHY_INTERFACE_MODE_NA;
++	mpcs->neg_mode = -1;
++
++	mpcs->clk = devm_clk_get_enabled(mpcs->dev, NULL);
++	if (IS_ERR(mpcs->clk))
++		return PTR_ERR(mpcs->clk);
++
++	mpcs->reset = devm_reset_control_get_shared(dev, NULL);
++	if (IS_ERR(mpcs->reset))
++		return PTR_ERR(mpcs->reset);
++
++	reset_control_deassert(mpcs->reset);
++
++	platform_set_drvdata(pdev, mpcs);
++
++	mutex_lock(&instance_mutex);
++	list_add_tail(&mpcs->node, &mtk_usxgmii_pcs_instances);
++	mutex_unlock(&instance_mutex);
++
++	return 0;
++}
++
++static int mtk_usxgmii_remove(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct mtk_usxgmii_pcs *cur, *tmp;
++
++	mutex_lock(&instance_mutex);
++	list_for_each_entry_safe(cur, tmp, &mtk_usxgmii_pcs_instances, node)
++		if (cur->dev == dev) {
++			list_del(&cur->node);
++			break;
++		}
++	mutex_unlock(&instance_mutex);
++
++	return 0;
++}
++
++static const struct of_device_id mtk_usxgmii_of_mtable[] = {
++	{ .compatible = "mediatek,mt7988-usxgmiisys" },
++	{ /* sentinel */ },
++};
++MODULE_DEVICE_TABLE(of, mtk_usxgmii_of_mtable);
++
++struct phylink_pcs *mtk_usxgmii_pcs_get(struct device *dev, struct device_node *np)
++{
++	struct platform_device *pdev;
++	struct mtk_usxgmii_pcs *mpcs;
++
++	if (!np)
++		return NULL;
++
++	if (!of_device_is_available(np))
++		return ERR_PTR(-ENODEV);
++
++	if (!of_match_node(mtk_usxgmii_of_mtable, np))
++		return ERR_PTR(-EINVAL);
++
++	pdev = of_find_device_by_node(np);
++	if (!pdev || !platform_get_drvdata(pdev)) {
++		if (pdev)
++			put_device(&pdev->dev);
++		return ERR_PTR(-EPROBE_DEFER);
++	}
++
++	mpcs = platform_get_drvdata(pdev);
++	device_link_add(dev, mpcs->dev, DL_FLAG_AUTOREMOVE_CONSUMER);
++
++	return &mpcs->pcs;
++}
++EXPORT_SYMBOL(mtk_usxgmii_pcs_get);
++
++void mtk_usxgmii_pcs_put(struct phylink_pcs *pcs)
++{
++	struct mtk_usxgmii_pcs *cur, *mpcs = NULL;
++
++	if (!pcs)
++		return;
++
++	mutex_lock(&instance_mutex);
++	list_for_each_entry(cur, &mtk_usxgmii_pcs_instances, node)
++		if (pcs == &cur->pcs) {
++			mpcs = cur;
++			break;
++		}
++	mutex_unlock(&instance_mutex);
++
++	if (WARN_ON(!mpcs))
++		return;
++
++	put_device(mpcs->dev);
++}
++EXPORT_SYMBOL(mtk_usxgmii_pcs_put);
++
++static struct platform_driver mtk_usxgmii_driver = {
++	.driver = {
++		.name			= "mtk_usxgmii",
++		.suppress_bind_attrs	= true,
++		.of_match_table		= mtk_usxgmii_of_mtable,
++	},
++	.probe = mtk_usxgmii_probe,
++	.remove = mtk_usxgmii_remove,
++};
++module_platform_driver(mtk_usxgmii_driver);
++
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("MediaTek USXGMII PCS driver");
++MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
+--- /dev/null
++++ b/include/linux/pcs/pcs-mtk-usxgmii.h
+@@ -0,0 +1,27 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++#ifndef __LINUX_PCS_MTK_USXGMII_H
++#define __LINUX_PCS_MTK_USXGMII_H
++
++#include <linux/phylink.h>
++
++/**
++ * mtk_usxgmii_select_pcs() - Get MediaTek PCS instance
++ * @np:		Pointer to device node indentifying a MediaTek USXGMII PCS
++ * @mode:	Ethernet PHY interface mode
++ *
++ * Return PCS identified by a device node and the PHY interface mode in use
++ *
++ * Return:	Pointer to phylink PCS instance of NULL
++ */
++#if IS_ENABLED(CONFIG_PCS_MTK_USXGMII)
++struct phylink_pcs *mtk_usxgmii_pcs_get(struct device *dev, struct device_node *np);
++void mtk_usxgmii_pcs_put(struct phylink_pcs *pcs);
++#else
++static inline struct phylink_pcs *mtk_usxgmii_pcs_get(struct device *dev, struct device_node *np)
++{
++	return NULL;
++}
++static inline void mtk_usxgmii_pcs_put(struct phylink_pcs *pcs) { }
++#endif /* IS_ENABLED(CONFIG_PCS_MTK_USXGMII) */
++
++#endif /* __LINUX_PCS_MTK_USXGMII_H */
diff --git a/target/linux/generic/pending-6.1/750-net-phy-airoha-Add-the-Airoha-EN8811H-PHY-driver.patch b/target/linux/generic/pending-6.1/750-net-phy-airoha-Add-the-Airoha-EN8811H-PHY-driver.patch
new file mode 100644
index 00000000000000..1dfa1366ebf248
--- /dev/null
+++ b/target/linux/generic/pending-6.1/750-net-phy-airoha-Add-the-Airoha-EN8811H-PHY-driver.patch
@@ -0,0 +1,1115 @@
+From patchwork Tue Feb  6 19:47:51 2024
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+X-Patchwork-Submitter: Eric Woudstra <ericwouds@gmail.com>
+X-Patchwork-Id: 13547762
+X-Patchwork-Delegate: kuba@kernel.org
+From: Eric Woudstra <ericwouds@gmail.com>
+To: "David S. Miller" <davem@davemloft.net>,
+	Eric Dumazet <edumazet@google.com>,
+	Jakub Kicinski <kuba@kernel.org>,
+	Paolo Abeni <pabeni@redhat.com>,
+	Rob Herring <robh+dt@kernel.org>,
+	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
+	Conor Dooley <conor+dt@kernel.org>,
+	Andrew Lunn <andrew@lunn.ch>,
+	Heiner Kallweit <hkallweit1@gmail.com>,
+	Russell King <linux@armlinux.org.uk>,
+	Matthias Brugger <matthias.bgg@gmail.com>,
+	AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
+	"Frank Wunderlich" <frank-w@public-files.de>,
+	Daniel Golle <daniel@makrotopia.org>,
+	Lucien Jheng  <lucien.jheng@airoha.com>,
+	Zhi-Jun You <hujy652@protonmail.com>
+Cc: netdev@vger.kernel.org,
+	devicetree@vger.kernel.org,
+	Eric Woudstra <ericwouds@gmail.com>
+Subject: [PATCH net-next 2/2] net: phy: air_en8811h: Add the Airoha EN8811H
+ PHY driver
+Date: Tue,  6 Feb 2024 20:47:51 +0100
+Message-ID: <20240206194751.1901802-3-ericwouds@gmail.com>
+X-Mailer: git-send-email 2.42.1
+In-Reply-To: <20240206194751.1901802-1-ericwouds@gmail.com>
+References: <20240206194751.1901802-1-ericwouds@gmail.com>
+Precedence: bulk
+X-Mailing-List: netdev@vger.kernel.org
+List-Id: <netdev.vger.kernel.org>
+List-Subscribe: <mailto:netdev+subscribe@vger.kernel.org>
+List-Unsubscribe: <mailto:netdev+unsubscribe@vger.kernel.org>
+MIME-Version: 1.0
+X-Patchwork-Delegate: kuba@kernel.org
+
+* Source originated from airoha's en8811h v1.2.1 driver
+ * Moved air_en8811h.h to air_en8811h.c
+ * Removed air_pbus_reg_write() as it writes to another device on mdio-bus
+ * Load firmware from /lib/firmware/airoha/ instead of /lib/firmware/
+ * Added .get_rate_matching()
+ * Use generic phy_read/write() and phy_read/write_mmd()
+ * Edited .get_features() to use generic C45 functions
+ * Edited .config_aneg() and .read_status() to use a mix of generic C22/C45
+ * Use led handling functions from mediatek-ge-soc.c
+ * Simplified led handling by storing led rules
+ * Cleanup macro definitions
+ * Cleanup code to pass checkpatch.pl
+ * General code cleanup
+
+Changes from original RFC patch:
+
+ * Use the correct order in Kconfig and Makefile
+ * Change some register naming to correspond with datasheet
+ * Use phy_driver .read_page() and .write_page()
+ * Use module_phy_driver()
+ * Use get_unaligned_le16() instead of macro
+ * In .config_aneg() and .read_status() use genphy_xxx() C22
+ * Use another vendor register to read real speed
+ * Load firmware only once and store firmware version
+ * Apply 2.5G LPA work-around (firmware before 24011202)
+ * Read 2.5G LPA from vendor register (firmware 24011202 and later)
+
+Changes to be committed:
+	modified:   drivers/net/phy/Kconfig
+	modified:   drivers/net/phy/Makefile
+	new file:   drivers/net/phy/air_en8811h.c
+
+Signed-off-by: Eric Woudstra <ericwouds@gmail.com>
+---
+ drivers/net/phy/Kconfig       |    5 +
+ drivers/net/phy/Makefile      |    1 +
+ drivers/net/phy/air_en8811h.c | 1006 +++++++++++++++++++++++++++++++++
+ 3 files changed, 1012 insertions(+)
+ create mode 100644 drivers/net/phy/air_en8811h.c
+
+--- a/drivers/net/phy/Kconfig
++++ b/drivers/net/phy/Kconfig
+@@ -69,6 +69,11 @@ config SFP
+ 
+ comment "MII PHY device drivers"
+ 
++config AIR_EN8811H_PHY
++	tristate "Airoha EN8811H 2.5 Gigabit PHY"
++	help
++	  Currently supports the Airoha EN8811H PHY.
++
+ config AMD_PHY
+ 	tristate "AMD and Altima PHYs"
+ 	help
+--- a/drivers/net/phy/Makefile
++++ b/drivers/net/phy/Makefile
+@@ -32,6 +32,7 @@ obj-y				+= $(sfp-obj-y) $(sfp-obj-m)
+ 
+ obj-$(CONFIG_ADIN_PHY)		+= adin.o
+ obj-$(CONFIG_ADIN1100_PHY)	+= adin1100.o
++obj-$(CONFIG_AIR_EN8811H_PHY)   += air_en8811h.o
+ obj-$(CONFIG_AMD_PHY)		+= amd.o
+ obj-$(CONFIG_AQUANTIA_PHY)	+= aquantia/
+ obj-$(CONFIG_AX88796B_PHY)	+= ax88796b.o
+--- /dev/null
++++ b/drivers/net/phy/air_en8811h.c
+@@ -0,0 +1,1006 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Driver for Airoha Ethernet PHYs
++ *
++ * Currently supporting the EN8811H.
++ *
++ * Limitations of the EN8811H:
++ * - Only full duplex supported
++ * - Forced speed (AN off) is not supported by hardware (100Mbps)
++ *
++ * Source originated from airoha's en8811h.c and en8811h.h v1.2.1
++ *
++ * Copyright (C) 2023 Airoha Technology Corp.
++ */
++
++#include <linux/phy.h>
++#include <linux/firmware.h>
++#include <linux/property.h>
++#include <asm/unaligned.h>
++
++#define EN8811H_PHY_ID		0x03a2a411
++
++#define EN8811H_MD32_DM		"airoha/EthMD32.dm.bin"
++#define EN8811H_MD32_DSP	"airoha/EthMD32.DSP.bin"
++
++#define AIR_FW_ADDR_DM	0x00000000
++#define AIR_FW_ADDR_DSP	0x00100000
++
++/* u32 (DWORD) component macros */
++#define LOWORD(d) ((u16)(u32)(d))
++#define HIWORD(d) ((u16)(((u32)(d)) >> 16))
++
++/* MII Registers */
++#define AIR_AUX_CTRL_STATUS	0x1d
++#define   AIR_AUX_CTRL_STATUS_SPEED_MASK	GENMASK(4, 2)
++#define   AIR_AUX_CTRL_STATUS_SPEED_100		0x4
++#define   AIR_AUX_CTRL_STATUS_SPEED_1000	0x8
++#define   AIR_AUX_CTRL_STATUS_SPEED_2500	0xc
++
++#define AIR_EXT_PAGE_ACCESS		0x1f
++#define   AIR_PHY_PAGE_STANDARD			0x0000
++#define   AIR_PHY_PAGE_EXTENDED_4		0x0004
++
++/* MII Registers Page 4*/
++#define AIR_PBUS_MODE			0x10
++#define   AIR_PBUS_MODE_ADDR_FIXED		0x0000
++#define   AIR_PBUS_MODE_ADDR_INCR		BIT(15)
++#define AIR_PBUS_WR_ADDR_HIGH		0x11
++#define AIR_PBUS_WR_ADDR_LOW		0x12
++#define AIR_PBUS_WR_DATA_HIGH		0x13
++#define AIR_PBUS_WR_DATA_LOW		0x14
++#define AIR_PBUS_RD_ADDR_HIGH		0x15
++#define AIR_PBUS_RD_ADDR_LOW		0x16
++#define AIR_PBUS_RD_DATA_HIGH		0x17
++#define AIR_PBUS_RD_DATA_LOW		0x18
++
++/* Registers on MDIO_MMD_VEND1 */
++#define EN8811H_PHY_FW_STATUS		0x8009
++#define   EN8811H_PHY_READY			0x02
++
++#define AIR_PHY_HOST_CMD_1		0x800c
++#define AIR_PHY_HOST_CMD_1_MODE1		0x0
++#define AIR_PHY_HOST_CMD_2		0x800d
++#define AIR_PHY_HOST_CMD_2_MODE1		0x0
++#define AIR_PHY_HOST_CMD_3		0x800e
++#define AIR_PHY_HOST_CMD_3_MODE1		0x1101
++#define AIR_PHY_HOST_CMD_3_DOCMD		0x1100
++#define AIR_PHY_HOST_CMD_4		0x800f
++#define AIR_PHY_HOST_CMD_4_MODE1		0x0002
++#define AIR_PHY_HOST_CMD_4_INTCLR		0x00e4
++
++/* Registers on MDIO_MMD_VEND2 */
++#define AIR_PHY_LED_BCR			0x021
++#define   AIR_PHY_LED_BCR_MODE_MASK		GENMASK(1, 0)
++#define   AIR_PHY_LED_BCR_TIME_TEST		BIT(2)
++#define   AIR_PHY_LED_BCR_CLK_EN		BIT(3)
++#define   AIR_PHY_LED_BCR_EXT_CTRL		BIT(15)
++
++#define AIR_PHY_LED_DUR_ON		0x022
++
++#define AIR_PHY_LED_DUR_BLINK		0x023
++
++#define AIR_PHY_LED_ON(i)	       (0x024 + ((i) * 2))
++#define   AIR_PHY_LED_ON_MASK			(GENMASK(6, 0) | BIT(8))
++#define   AIR_PHY_LED_ON_LINK1000		BIT(0)
++#define   AIR_PHY_LED_ON_LINK100		BIT(1)
++#define   AIR_PHY_LED_ON_LINK10			BIT(2)
++#define   AIR_PHY_LED_ON_LINKDOWN		BIT(3)
++#define   AIR_PHY_LED_ON_FDX			BIT(4) /* Full duplex */
++#define   AIR_PHY_LED_ON_HDX			BIT(5) /* Half duplex */
++#define   AIR_PHY_LED_ON_FORCE_ON		BIT(6)
++#define   AIR_PHY_LED_ON_LINK2500		BIT(8)
++#define   AIR_PHY_LED_ON_POLARITY		BIT(14)
++#define   AIR_PHY_LED_ON_ENABLE			BIT(15)
++
++#define AIR_PHY_LED_BLINK(i)	       (0x025 + ((i) * 2))
++#define   AIR_PHY_LED_BLINK_1000TX		BIT(0)
++#define   AIR_PHY_LED_BLINK_1000RX		BIT(1)
++#define   AIR_PHY_LED_BLINK_100TX		BIT(2)
++#define   AIR_PHY_LED_BLINK_100RX		BIT(3)
++#define   AIR_PHY_LED_BLINK_10TX		BIT(4)
++#define   AIR_PHY_LED_BLINK_10RX		BIT(5)
++#define   AIR_PHY_LED_BLINK_COLLISION		BIT(6)
++#define   AIR_PHY_LED_BLINK_RX_CRC_ERR		BIT(7)
++#define   AIR_PHY_LED_BLINK_RX_IDLE_ERR		BIT(8)
++#define   AIR_PHY_LED_BLINK_FORCE_BLINK		BIT(9)
++#define   AIR_PHY_LED_BLINK_2500TX		BIT(10)
++#define   AIR_PHY_LED_BLINK_2500RX		BIT(11)
++
++/* Registers on BUCKPBUS */
++#define EN8811H_2P5G_LPA		0x3b30
++#define   EN8811H_2P5G_LPA_2P5G			BIT(0)
++
++#define EN8811H_FW_VERSION		0x3b3c
++
++#define EN8811H_POLARITY		0xca0f8
++#define   EN8811H_POLARITY_TX_NORMAL		BIT(0)
++#define   EN8811H_POLARITY_RX_REVERSE		BIT(1)
++
++#define EN8811H_GPIO_OUTPUT		0xcf8b8
++#define   EN8811H_GPIO_OUTPUT_345		(BIT(3) | BIT(4) | BIT(5))
++
++#define EN8811H_FW_CTRL_1		0x0f0018
++#define   EN8811H_FW_CTRL_1_START		0x0
++#define   EN8811H_FW_CTRL_1_FINISH		0x1
++#define EN8811H_FW_CTRL_2		0x800000
++#define EN8811H_FW_CTRL_2_LOADING		BIT(11)
++
++#define EN8811H_LED_COUNT	3
++
++/* GPIO5  <-> BASE_T_LED0
++ * GPIO4  <-> BASE_T_LED1
++ * GPIO3  <-> BASE_T_LED2
++ *
++ * Default setup suitable for 2 leds connected:
++ *    100M link up triggers led0, only led0 blinking on traffic
++ *   1000M link up triggers led1, only led1 blinking on traffic
++ *   2500M link up triggers led0 and led1, both blinking on traffic
++ * Also suitable for 1 led connected:
++ *     any link up triggers led2
++ */
++#define AIR_DEFAULT_TRIGGER_LED0 (BIT(TRIGGER_NETDEV_LINK_2500) | \
++				  BIT(TRIGGER_NETDEV_LINK_100)  | \
++				  BIT(TRIGGER_NETDEV_RX)        | \
++				  BIT(TRIGGER_NETDEV_TX))
++#define AIR_DEFAULT_TRIGGER_LED1 (BIT(TRIGGER_NETDEV_LINK_2500) | \
++				  BIT(TRIGGER_NETDEV_LINK_1000) | \
++				  BIT(TRIGGER_NETDEV_RX)        | \
++				  BIT(TRIGGER_NETDEV_TX))
++#define AIR_DEFAULT_TRIGGER_LED2  BIT(TRIGGER_NETDEV_LINK)
++
++struct led {
++	unsigned long rules;
++	unsigned long state;
++};
++
++struct en8811h_priv {
++	u32		firmware_version;
++	struct led	led[EN8811H_LED_COUNT];
++};
++
++enum {
++	AIR_PHY_LED_STATE_FORCE_ON,
++	AIR_PHY_LED_STATE_FORCE_BLINK,
++};
++
++enum {
++	AIR_PHY_LED_DUR_BLINK_32M,
++	AIR_PHY_LED_DUR_BLINK_64M,
++	AIR_PHY_LED_DUR_BLINK_128M,
++	AIR_PHY_LED_DUR_BLINK_256M,
++	AIR_PHY_LED_DUR_BLINK_512M,
++	AIR_PHY_LED_DUR_BLINK_1024M,
++};
++
++enum {
++	AIR_LED_DISABLE,
++	AIR_LED_ENABLE,
++};
++
++enum {
++	AIR_ACTIVE_LOW,
++	AIR_ACTIVE_HIGH,
++};
++
++enum {
++	AIR_LED_MODE_DISABLE,
++	AIR_LED_MODE_USER_DEFINE,
++};
++
++#define AIR_PHY_LED_DUR_UNIT	1024
++#define AIR_PHY_LED_DUR (AIR_PHY_LED_DUR_UNIT << AIR_PHY_LED_DUR_BLINK_64M)
++
++static const unsigned long en8811h_led_trig = (BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
++					       BIT(TRIGGER_NETDEV_LINK)        |
++					       BIT(TRIGGER_NETDEV_LINK_10)     |
++					       BIT(TRIGGER_NETDEV_LINK_100)    |
++					       BIT(TRIGGER_NETDEV_LINK_1000)   |
++					       BIT(TRIGGER_NETDEV_LINK_2500)   |
++					       BIT(TRIGGER_NETDEV_RX)          |
++					       BIT(TRIGGER_NETDEV_TX));
++
++static int air_phy_read_page(struct phy_device *phydev)
++{
++	return __phy_read(phydev, AIR_EXT_PAGE_ACCESS);
++}
++
++static int air_phy_write_page(struct phy_device *phydev, int page)
++{
++	return __phy_write(phydev, AIR_EXT_PAGE_ACCESS, page);
++}
++
++static int __air_buckpbus_reg_write(struct phy_device *phydev,
++				    u32 pbus_address, u32 pbus_data)
++{
++	int ret;
++
++	ret = __phy_write(phydev, AIR_PBUS_MODE, AIR_PBUS_MODE_ADDR_FIXED);
++	if (ret < 0)
++		return ret;
++
++	ret = __phy_write(phydev, AIR_PBUS_WR_ADDR_HIGH, HIWORD(pbus_address));
++	if (ret < 0)
++		return ret;
++
++	ret = __phy_write(phydev, AIR_PBUS_WR_ADDR_LOW,  LOWORD(pbus_address));
++	if (ret < 0)
++		return ret;
++
++	ret = __phy_write(phydev, AIR_PBUS_WR_DATA_HIGH, HIWORD(pbus_data));
++	if (ret < 0)
++		return ret;
++
++	ret = __phy_write(phydev, AIR_PBUS_WR_DATA_LOW,  LOWORD(pbus_data));
++	if (ret < 0)
++		return ret;
++
++	return 0;
++}
++
++static int air_buckpbus_reg_write(struct phy_device *phydev,
++				  u32 pbus_address, u32 pbus_data)
++{
++	int ret, saved_page;
++
++	saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
++
++	ret = __air_buckpbus_reg_write(phydev, pbus_address, pbus_data);
++	if (ret < 0)
++		phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
++			   pbus_address, ret);
++
++	return phy_restore_page(phydev, saved_page, ret);
++;
++}
++
++static int __air_buckpbus_reg_read(struct phy_device *phydev,
++				   u32 pbus_address, u32 *pbus_data)
++{
++	int pbus_data_low, pbus_data_high;
++	int ret;
++
++	ret = __phy_write(phydev, AIR_PBUS_MODE, AIR_PBUS_MODE_ADDR_FIXED);
++	if (ret < 0)
++		return ret;
++
++	ret = __phy_write(phydev, AIR_PBUS_RD_ADDR_HIGH, HIWORD(pbus_address));
++	if (ret < 0)
++		return ret;
++
++	ret = __phy_write(phydev, AIR_PBUS_RD_ADDR_LOW,  LOWORD(pbus_address));
++	if (ret < 0)
++		return ret;
++
++	pbus_data_high = __phy_read(phydev, AIR_PBUS_RD_DATA_HIGH);
++	if (pbus_data_high < 0)
++		return ret;
++
++	pbus_data_low = __phy_read(phydev, AIR_PBUS_RD_DATA_LOW);
++	if (pbus_data_low < 0)
++		return ret;
++
++	*pbus_data = (u16)pbus_data_low | ((u32)(u16)pbus_data_high << 16);
++	return 0;
++}
++
++static int air_buckpbus_reg_read(struct phy_device *phydev,
++				 u32 pbus_address, u32 *pbus_data)
++{
++	int ret, saved_page;
++
++	saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
++
++	ret = __air_buckpbus_reg_read(phydev, pbus_address, pbus_data);
++	if (ret < 0)
++		phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
++			   pbus_address, ret);
++
++	return phy_restore_page(phydev, saved_page, ret);
++}
++
++static int __air_write_buf(struct phy_device *phydev, u32 address,
++			   const struct firmware *fw)
++{
++	unsigned int offset;
++	int ret;
++	u16 val;
++
++	ret = __phy_write(phydev, AIR_PBUS_MODE, AIR_PBUS_MODE_ADDR_INCR);
++	if (ret < 0)
++		return ret;
++
++	ret = __phy_write(phydev, AIR_PBUS_WR_ADDR_HIGH, HIWORD(address));
++	if (ret < 0)
++		return ret;
++
++	ret = __phy_write(phydev, AIR_PBUS_WR_ADDR_LOW,  LOWORD(address));
++	if (ret < 0)
++		return ret;
++
++	for (offset = 0; offset < fw->size; offset += 4) {
++		val = get_unaligned_le16(&fw->data[offset + 2]);
++		ret = __phy_write(phydev, AIR_PBUS_WR_DATA_HIGH, val);
++		if (ret < 0)
++			return ret;
++
++		val = get_unaligned_le16(&fw->data[offset]);
++		ret = __phy_write(phydev, AIR_PBUS_WR_DATA_LOW, val);
++		if (ret < 0)
++			return ret;
++	}
++
++	return 0;
++}
++
++static int air_write_buf(struct phy_device *phydev, u32 address,
++			 const struct firmware *fw)
++{
++	int ret, saved_page;
++
++	saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
++
++	ret = __air_write_buf(phydev, address, fw);
++	if (ret < 0)
++		phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
++			   address, ret);
++
++	return phy_restore_page(phydev, saved_page, ret);
++}
++
++static int en8811h_load_firmware(struct phy_device *phydev)
++{
++	struct device *dev = &phydev->mdio.dev;
++	const struct firmware *fw1, *fw2;
++	u32 pbus_value;
++	int ret;
++
++	ret = request_firmware_direct(&fw1, EN8811H_MD32_DM, dev);
++	if (ret < 0)
++		return ret;
++
++	ret = request_firmware_direct(&fw2, EN8811H_MD32_DSP, dev);
++	if (ret < 0)
++		goto en8811h_load_firmware_rel1;
++
++	ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
++				     EN8811H_FW_CTRL_1_START);
++	if (ret < 0)
++		goto en8811h_load_firmware_out;
++
++	ret = air_buckpbus_reg_read(phydev, EN8811H_FW_CTRL_2, &pbus_value);
++	if (ret < 0)
++		goto en8811h_load_firmware_out;
++	pbus_value |= EN8811H_FW_CTRL_2_LOADING;
++	ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_2, pbus_value);
++	if (ret < 0)
++		goto en8811h_load_firmware_out;
++
++	ret = air_write_buf(phydev, AIR_FW_ADDR_DM,  fw1);
++	if (ret < 0)
++		goto en8811h_load_firmware_out;
++
++	ret = air_write_buf(phydev, AIR_FW_ADDR_DSP, fw2);
++	if (ret < 0)
++		goto en8811h_load_firmware_out;
++
++	ret = air_buckpbus_reg_read(phydev, EN8811H_FW_CTRL_2, &pbus_value);
++	if (ret < 0)
++		goto en8811h_load_firmware_out;
++	pbus_value &= ~EN8811H_FW_CTRL_2_LOADING;
++	ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_2, pbus_value);
++	if (ret < 0)
++		goto en8811h_load_firmware_out;
++
++	ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
++				     EN8811H_FW_CTRL_1_FINISH);
++	if (ret < 0)
++		goto en8811h_load_firmware_out;
++
++	ret = 0;
++
++en8811h_load_firmware_out:
++	release_firmware(fw2);
++
++en8811h_load_firmware_rel1:
++	release_firmware(fw1);
++
++	if (ret < 0)
++		phydev_err(phydev, "Load firmware failed: %d\n", ret);
++
++	return ret;
++}
++
++static int en8811h_restart_host(struct phy_device *phydev)
++{
++	int ret;
++
++	ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
++				     EN8811H_FW_CTRL_1_START);
++	if (ret < 0)
++		return ret;
++
++	return air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
++				     EN8811H_FW_CTRL_1_FINISH);
++}
++
++static int air_hw_led_on_set(struct phy_device *phydev, u8 index, bool on)
++{
++	struct en8811h_priv *priv = phydev->priv;
++	bool changed;
++
++	if (index >= EN8811H_LED_COUNT)
++		return -EINVAL;
++
++	if (on)
++		changed = !test_and_set_bit(AIR_PHY_LED_STATE_FORCE_ON,
++					    &priv->led[index].state);
++	else
++		changed = !!test_and_clear_bit(AIR_PHY_LED_STATE_FORCE_ON,
++					       &priv->led[index].state);
++
++	changed |= (priv->led[index].rules != 0);
++
++	if (changed)
++		return phy_modify_mmd(phydev, MDIO_MMD_VEND2,
++				      AIR_PHY_LED_ON(index),
++				      AIR_PHY_LED_ON_MASK,
++				      on ? AIR_PHY_LED_ON_FORCE_ON : 0);
++
++	return 0;
++}
++
++static int air_hw_led_blink_set(struct phy_device *phydev, u8 index,
++				bool blinking)
++{
++	struct en8811h_priv *priv = phydev->priv;
++	bool changed;
++
++	if (index >= EN8811H_LED_COUNT)
++		return -EINVAL;
++
++	if (blinking)
++		changed = !test_and_set_bit(AIR_PHY_LED_STATE_FORCE_BLINK,
++					    &priv->led[index].state);
++	else
++		changed = !!test_and_clear_bit(AIR_PHY_LED_STATE_FORCE_BLINK,
++					       &priv->led[index].state);
++
++	changed |= (priv->led[index].rules != 0);
++
++	if (changed)
++		return phy_write_mmd(phydev, MDIO_MMD_VEND2,
++				     AIR_PHY_LED_BLINK(index),
++				     blinking ?
++				     AIR_PHY_LED_BLINK_FORCE_BLINK : 0);
++	else
++		return 0;
++}
++
++static int air_led_blink_set(struct phy_device *phydev, u8 index,
++			     unsigned long *delay_on,
++			     unsigned long *delay_off)
++{
++	struct en8811h_priv *priv = phydev->priv;
++	bool blinking = false;
++	int err;
++
++	if (index >= EN8811H_LED_COUNT)
++		return -EINVAL;
++
++	if (delay_on && delay_off && (*delay_on > 0) && (*delay_off > 0)) {
++		blinking = true;
++		*delay_on = 50;
++		*delay_off = 50;
++	}
++
++	err = air_hw_led_blink_set(phydev, index, blinking);
++	if (err)
++		return err;
++
++	/* led-blink set, so switch led-on off */
++	err = air_hw_led_on_set(phydev, index, false);
++	if (err)
++		return err;
++
++	/* hw-control is off*/
++	if (!!test_bit(AIR_PHY_LED_STATE_FORCE_BLINK, &priv->led[index].state))
++		priv->led[index].rules = 0;
++
++	return 0;
++}
++
++static int air_led_brightness_set(struct phy_device *phydev, u8 index,
++				  enum led_brightness value)
++{
++	struct en8811h_priv *priv = phydev->priv;
++	int err;
++
++	if (index >= EN8811H_LED_COUNT)
++		return -EINVAL;
++
++	/* led-on set, so switch led-blink off */
++	err = air_hw_led_blink_set(phydev, index, false);
++	if (err)
++		return err;
++
++	err = air_hw_led_on_set(phydev, index, (value != LED_OFF));
++	if (err)
++		return err;
++
++	/* hw-control is off */
++	if (!!test_bit(AIR_PHY_LED_STATE_FORCE_ON, &priv->led[index].state))
++		priv->led[index].rules = 0;
++
++	return 0;
++}
++
++static int air_led_hw_control_get(struct phy_device *phydev, u8 index,
++				  unsigned long *rules)
++{
++	struct en8811h_priv *priv = phydev->priv;
++
++	if (index >= EN8811H_LED_COUNT)
++		return -EINVAL;
++
++	*rules = priv->led[index].rules;
++
++	return 0;
++};
++
++static int air_led_hw_control_set(struct phy_device *phydev, u8 index,
++				  unsigned long rules)
++{
++	struct en8811h_priv *priv = phydev->priv;
++	u16 on = 0, blink = 0;
++	int ret;
++
++	priv->led[index].rules = rules;
++
++	if (index >= EN8811H_LED_COUNT)
++		return -EINVAL;
++
++	if (rules & (BIT(TRIGGER_NETDEV_LINK_10)   | BIT(TRIGGER_NETDEV_LINK))) {
++		on |= AIR_PHY_LED_ON_LINK10;
++		if (rules & BIT(TRIGGER_NETDEV_RX))
++			blink |= AIR_PHY_LED_BLINK_10RX;
++		if (rules & BIT(TRIGGER_NETDEV_TX))
++			blink |= AIR_PHY_LED_BLINK_10TX;
++	}
++
++	if (rules & (BIT(TRIGGER_NETDEV_LINK_100)  | BIT(TRIGGER_NETDEV_LINK))) {
++		on |= AIR_PHY_LED_ON_LINK100;
++		if (rules & BIT(TRIGGER_NETDEV_RX))
++			blink |= AIR_PHY_LED_BLINK_100RX;
++		if (rules & BIT(TRIGGER_NETDEV_TX))
++			blink |= AIR_PHY_LED_BLINK_100TX;
++	}
++
++	if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK))) {
++		on |= AIR_PHY_LED_ON_LINK1000;
++		if (rules & BIT(TRIGGER_NETDEV_RX))
++			blink |= AIR_PHY_LED_BLINK_1000RX;
++		if (rules & BIT(TRIGGER_NETDEV_TX))
++			blink |= AIR_PHY_LED_BLINK_1000TX;
++	}
++
++	if (rules & (BIT(TRIGGER_NETDEV_LINK_2500) | BIT(TRIGGER_NETDEV_LINK))) {
++		on |= AIR_PHY_LED_ON_LINK2500;
++		if (rules & BIT(TRIGGER_NETDEV_RX))
++			blink |= AIR_PHY_LED_BLINK_2500RX;
++		if (rules & BIT(TRIGGER_NETDEV_TX))
++			blink |= AIR_PHY_LED_BLINK_2500TX;
++	}
++
++	if (on == 0) {
++		if (rules & BIT(TRIGGER_NETDEV_RX)) {
++			blink |= AIR_PHY_LED_BLINK_10RX   |
++				 AIR_PHY_LED_BLINK_100RX  |
++				 AIR_PHY_LED_BLINK_1000RX |
++				 AIR_PHY_LED_BLINK_2500RX;
++		}
++		if (rules & BIT(TRIGGER_NETDEV_TX)) {
++			blink |= AIR_PHY_LED_BLINK_10TX   |
++				 AIR_PHY_LED_BLINK_100TX  |
++				 AIR_PHY_LED_BLINK_1000TX |
++				 AIR_PHY_LED_BLINK_2500TX;
++		}
++	}
++
++	if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX))
++		on |= AIR_PHY_LED_ON_FDX;
++
++	if (rules & BIT(TRIGGER_NETDEV_HALF_DUPLEX))
++		on |= AIR_PHY_LED_ON_HDX;
++
++	if (blink || on) {
++		/* switch hw-control on, so led-on and led-blink are off */
++		clear_bit(AIR_PHY_LED_STATE_FORCE_ON, &priv->led[index].state);
++		clear_bit(AIR_PHY_LED_STATE_FORCE_BLINK, &priv->led[index].state);
++	} else {
++		priv->led[index].rules = 0;
++	}
++
++	ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index),
++			     AIR_PHY_LED_ON_MASK, on);
++
++	if (ret < 0)
++		return ret;
++
++	return phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BLINK(index),
++			     blink);
++};
++
++static int air_led_init(struct phy_device *phydev, u8 index, u8 state, u8 pol)
++{
++	int cl45_data;
++	int err;
++
++	if (index >= EN8811H_LED_COUNT)
++		return -EINVAL;
++
++	cl45_data = phy_read_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index));
++	if (cl45_data < 0)
++		return cl45_data;
++
++	if (state == AIR_LED_ENABLE)
++		cl45_data |= AIR_PHY_LED_ON_ENABLE;
++	else
++		cl45_data &= ~AIR_PHY_LED_ON_ENABLE;
++
++	if (pol == AIR_ACTIVE_HIGH)
++		cl45_data |= AIR_PHY_LED_ON_POLARITY;
++	else
++		cl45_data &= ~AIR_PHY_LED_ON_POLARITY;
++
++	err = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index),
++			    cl45_data);
++	if (err < 0)
++		return err;
++
++	return 0;
++}
++
++static int air_leds_init(struct phy_device *phydev, int num, int dur, int mode)
++{
++	struct en8811h_priv *priv = phydev->priv;
++	int cl45_data = dur;
++	int ret, i;
++
++	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_BLINK,
++			    cl45_data);
++	if (ret < 0)
++		return ret;
++
++	cl45_data >>= 1;
++	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_ON,
++			    cl45_data);
++	if (ret < 0)
++		return ret;
++
++	cl45_data = phy_read_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BCR);
++	if (cl45_data < 0)
++		return cl45_data;
++
++	switch (mode) {
++	case AIR_LED_MODE_DISABLE:
++		cl45_data &= ~AIR_PHY_LED_BCR_EXT_CTRL;
++		cl45_data &= ~AIR_PHY_LED_BCR_MODE_MASK;
++		break;
++	case AIR_LED_MODE_USER_DEFINE:
++		cl45_data |= AIR_PHY_LED_BCR_EXT_CTRL;
++		cl45_data |= AIR_PHY_LED_BCR_CLK_EN;
++		break;
++	default:
++		phydev_err(phydev, "LED mode %d is not supported\n", mode);
++		return -EINVAL;
++	}
++
++	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BCR, cl45_data);
++	if (ret < 0)
++		return ret;
++
++	for (i = 0; i < num; ++i) {
++		ret = air_led_init(phydev, i, AIR_LED_ENABLE, AIR_ACTIVE_HIGH);
++		if (ret < 0) {
++			phydev_err(phydev, "LED%d init failed: %d\n", i, ret);
++			return ret;
++		}
++		air_led_hw_control_set(phydev, i, priv->led[i].rules);
++	}
++
++	return 0;
++}
++
++static int en8811h_led_hw_is_supported(struct phy_device *phydev, u8 index,
++				       unsigned long rules)
++{
++	if (index >= EN8811H_LED_COUNT)
++		return -EINVAL;
++
++	/* All combinations of the supported triggers are allowed */
++	if (rules & ~en8811h_led_trig)
++		return -EOPNOTSUPP;
++
++	return 0;
++};
++
++static int en8811h_probe(struct phy_device *phydev)
++{
++	struct en8811h_priv *priv;
++
++	priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct en8811h_priv),
++			    GFP_KERNEL);
++	if (!priv)
++		return -ENOMEM;
++
++	priv->led[0].rules = AIR_DEFAULT_TRIGGER_LED0;
++	priv->led[1].rules = AIR_DEFAULT_TRIGGER_LED1;
++	priv->led[2].rules = AIR_DEFAULT_TRIGGER_LED2;
++
++	phydev->priv = priv;
++
++	/* MDIO_DEVS1/2 empty, so set mmds_present bits here */
++	phydev->c45_ids.mmds_present |= MDIO_DEVS_PMAPMD | MDIO_DEVS_AN;
++
++	return 0;
++}
++
++static int en8811h_config_init(struct phy_device *phydev)
++{
++	struct en8811h_priv *priv = phydev->priv;
++	struct device *dev = &phydev->mdio.dev;
++	int ret, pollret, reg_value;
++	u32 pbus_value;
++
++	if (!priv->firmware_version)
++		ret = en8811h_load_firmware(phydev);
++	else
++		ret = en8811h_restart_host(phydev);
++	if (ret < 0)
++		return ret;
++
++	/* Because of mdio-lock, may have to wait for multiple loads */
++	pollret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
++					    EN8811H_PHY_FW_STATUS, reg_value,
++					    reg_value == EN8811H_PHY_READY,
++					    20000, 7500000, true);
++
++	ret = air_buckpbus_reg_read(phydev, EN8811H_FW_VERSION, &pbus_value);
++	if (ret < 0)
++		return ret;
++
++	if (pollret || !pbus_value) {
++		phydev_err(phydev, "Firmware not ready: 0x%x\n", reg_value);
++		return -ENODEV;
++	}
++
++	if (!priv->firmware_version) {
++		phydev_info(phydev, "MD32 firmware version: %08x\n", pbus_value);
++		priv->firmware_version = pbus_value;
++	}
++
++	/* Select mode 1, the only mode supported */
++	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_1,
++			    AIR_PHY_HOST_CMD_1_MODE1);
++	if (ret < 0)
++		return ret;
++	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_2,
++			    AIR_PHY_HOST_CMD_2_MODE1);
++	if (ret < 0)
++		return ret;
++	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_3,
++			    AIR_PHY_HOST_CMD_3_MODE1);
++	if (ret < 0)
++		return ret;
++	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_4,
++			    AIR_PHY_HOST_CMD_4_MODE1);
++	if (ret < 0)
++		return ret;
++
++	/* Serdes polarity */
++	ret = air_buckpbus_reg_read(phydev, EN8811H_POLARITY, &pbus_value);
++	if (ret < 0)
++		return ret;
++	if (device_property_read_bool(dev, "airoha,pnswap-rx"))
++		pbus_value |=  EN8811H_POLARITY_RX_REVERSE;
++	else
++		pbus_value &= ~EN8811H_POLARITY_RX_REVERSE;
++	if (device_property_read_bool(dev, "airoha,pnswap-tx"))
++		pbus_value &= ~EN8811H_POLARITY_TX_NORMAL;
++	else
++		pbus_value |=  EN8811H_POLARITY_TX_NORMAL;
++	ret = air_buckpbus_reg_write(phydev, EN8811H_POLARITY, pbus_value);
++	if (ret < 0)
++		return ret;
++
++	ret = air_leds_init(phydev, EN8811H_LED_COUNT, AIR_PHY_LED_DUR,
++			    AIR_LED_MODE_USER_DEFINE);
++	if (ret < 0) {
++		phydev_err(phydev, "Failed to initialize leds: %d\n", ret);
++		return ret;
++	}
++
++	ret = air_buckpbus_reg_read(phydev, EN8811H_GPIO_OUTPUT, &pbus_value);
++	if (ret < 0)
++		return ret;
++	pbus_value |= EN8811H_GPIO_OUTPUT_345;
++	ret = air_buckpbus_reg_write(phydev, EN8811H_GPIO_OUTPUT, pbus_value);
++	if (ret < 0)
++		return ret;
++
++	return 0;
++}
++
++static int en8811h_get_features(struct phy_device *phydev)
++{
++	linkmode_set_bit_array(phy_basic_ports_array,
++			       ARRAY_SIZE(phy_basic_ports_array),
++			       phydev->supported);
++
++	return genphy_c45_pma_read_abilities(phydev);
++}
++
++static int en8811h_get_rate_matching(struct phy_device *phydev,
++				     phy_interface_t iface)
++{
++	return RATE_MATCH_PAUSE;
++}
++
++static int en8811h_config_aneg(struct phy_device *phydev)
++{
++	bool changed = false;
++	int err, val;
++
++	val = 0;
++	if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
++			      phydev->advertising))
++		val |= MDIO_AN_10GBT_CTRL_ADV2_5G;
++	err =  phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
++				      MDIO_AN_10GBT_CTRL_ADV2_5G, val);
++	if (err < 0)
++		return err;
++	if (err > 0)
++		changed = true;
++
++	return __genphy_config_aneg(phydev, changed);
++}
++
++static int en8811h_read_status(struct phy_device *phydev)
++{
++	struct en8811h_priv *priv = phydev->priv;
++	u32 pbus_value;
++	int ret, val;
++
++	ret = genphy_update_link(phydev);
++	if (ret)
++		return ret;
++
++	phydev->master_slave_get = MASTER_SLAVE_CFG_UNSUPPORTED;
++	phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED;
++	phydev->speed = SPEED_UNKNOWN;
++	phydev->duplex = DUPLEX_UNKNOWN;
++	phydev->pause = 0;
++	phydev->asym_pause = 0;
++
++	ret = genphy_read_master_slave(phydev);
++	if (ret < 0)
++		return ret;
++
++	ret = genphy_read_lpa(phydev);
++	if (ret < 0)
++		return ret;
++
++	/* Get link partner 2.5GBASE-T ability from vendor register */
++	ret = air_buckpbus_reg_read(phydev, EN8811H_2P5G_LPA, &pbus_value);
++	if (ret < 0)
++		return ret;
++	linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
++			 phydev->lp_advertising,
++			 pbus_value & EN8811H_2P5G_LPA_2P5G);
++
++	if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete)
++		phy_resolve_aneg_pause(phydev);
++
++	if (!phydev->link)
++		return 0;
++
++	/* Get real speed from vendor register */
++	val = phy_read(phydev, AIR_AUX_CTRL_STATUS);
++	if (val < 0)
++		return val;
++	switch (val & AIR_AUX_CTRL_STATUS_SPEED_MASK) {
++	case AIR_AUX_CTRL_STATUS_SPEED_2500:
++		phydev->speed = SPEED_2500;
++		break;
++	case AIR_AUX_CTRL_STATUS_SPEED_1000:
++		phydev->speed = SPEED_1000;
++		break;
++	case AIR_AUX_CTRL_STATUS_SPEED_100:
++		phydev->speed = SPEED_100;
++		break;
++	}
++
++	/* BUG in PHY firmware: MDIO_AN_10GBT_STAT_LP2_5G does not get set.
++	 * Firmware before version 24011202 has no vendor register 2P5G_LPA.
++	 * Assume link partner advertised it if connected at 2500Mbps.
++	 */
++	if (priv->firmware_version < 0x24011202) {
++		linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
++				 phydev->lp_advertising,
++				 phydev->speed == SPEED_2500);
++	}
++
++	/* Only supports full duplex */
++	phydev->duplex = DUPLEX_FULL;
++
++	return 0;
++}
++
++static int en8811h_clear_intr(struct phy_device *phydev)
++{
++	int ret;
++
++	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_3,
++			    AIR_PHY_HOST_CMD_3_DOCMD);
++	if (ret < 0)
++		return ret;
++
++	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_4,
++			    AIR_PHY_HOST_CMD_4_INTCLR);
++	if (ret < 0)
++		return ret;
++
++	return 0;
++}
++
++static irqreturn_t en8811h_handle_interrupt(struct phy_device *phydev)
++{
++	int ret;
++
++	ret = en8811h_clear_intr(phydev);
++	if (ret < 0) {
++		phy_error(phydev);
++		return IRQ_NONE;
++	}
++
++	phy_trigger_machine(phydev);
++
++	return IRQ_HANDLED;
++}
++
++static struct phy_driver en8811h_driver[] = {
++{
++	PHY_ID_MATCH_MODEL(EN8811H_PHY_ID),
++	.name			= "Airoha EN8811H",
++	.probe			= en8811h_probe,
++	.get_features		= en8811h_get_features,
++	.config_init		= en8811h_config_init,
++	.get_rate_matching	= en8811h_get_rate_matching,
++	.config_aneg		= en8811h_config_aneg,
++	.read_status		= en8811h_read_status,
++	.config_intr		= en8811h_clear_intr,
++	.handle_interrupt	= en8811h_handle_interrupt,
++	.led_hw_is_supported	= en8811h_led_hw_is_supported,
++	.read_page		= air_phy_read_page,
++	.write_page		= air_phy_write_page,
++	.led_blink_set		= air_led_blink_set,
++	.led_brightness_set	= air_led_brightness_set,
++	.led_hw_control_set	= air_led_hw_control_set,
++	.led_hw_control_get	= air_led_hw_control_get,
++} };
++
++module_phy_driver(en8811h_driver);
++
++static struct mdio_device_id __maybe_unused en8811h_tbl[] = {
++	{ PHY_ID_MATCH_MODEL(EN8811H_PHY_ID) },
++	{ }
++};
++MODULE_DEVICE_TABLE(mdio, en8811h_tbl);
++MODULE_FIRMWARE(EN8811H_MD32_DM);
++MODULE_FIRMWARE(EN8811H_MD32_DSP);
++
++MODULE_DESCRIPTION("Airoha EN8811H PHY drivers");
++MODULE_AUTHOR("Airoha");
++MODULE_AUTHOR("Eric Woudstra <ericwouds@gmail.com>");
++MODULE_LICENSE("GPL");
diff --git a/target/linux/generic/pending-6.1/760-net-core-add-optional-threading-for-backlog-processi.patch b/target/linux/generic/pending-6.1/760-net-core-add-optional-threading-for-backlog-processi.patch
index 944e4d18697892..42c8519c9055d1 100644
--- a/target/linux/generic/pending-6.1/760-net-core-add-optional-threading-for-backlog-processi.patch
+++ b/target/linux/generic/pending-6.1/760-net-core-add-optional-threading-for-backlog-processi.patch
@@ -167,7 +167,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  #ifdef CONFIG_RPS
  	remsd = oldsd->rps_ipi_list;
  	oldsd->rps_ipi_list = NULL;
-@@ -11471,6 +11545,7 @@ static int __init net_dev_init(void)
+@@ -11480,6 +11554,7 @@ static int __init net_dev_init(void)
  		INIT_CSD(&sd->defer_csd, trigger_rx_softirq, sd);
  		spin_lock_init(&sd->defer_lock);
  
diff --git a/target/linux/generic/pending-6.1/778-net-l2tp-drop-flow-hash-on-forward.patch b/target/linux/generic/pending-6.1/778-net-l2tp-drop-flow-hash-on-forward.patch
new file mode 100644
index 00000000000000..a2c0edcbbf5808
--- /dev/null
+++ b/target/linux/generic/pending-6.1/778-net-l2tp-drop-flow-hash-on-forward.patch
@@ -0,0 +1,31 @@
+From 4a44a52f16ccd3d03e0cb5fb437a5eb31a5f9f05 Mon Sep 17 00:00:00 2001
+From: David Bauer <mail@david-bauer.net>
+Date: Mon, 26 Feb 2024 21:39:34 +0100
+Subject: [PATCH] net l2tp: drop flow hash on forward
+
+Drop the flow-hash of the skb when forwarding to the L2TP netdev.
+
+This avoids the L2TP qdisc from using the flow-hash from the outer
+packet, which is identical for every flow within the tunnel.
+
+This does not affect every platform but is specific for the ethernet
+driver. It depends on the platform including L4 information in the
+flow-hash.
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+---
+ net/l2tp/l2tp_eth.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/net/l2tp/l2tp_eth.c
++++ b/net/l2tp/l2tp_eth.c
+@@ -136,6 +136,9 @@ static void l2tp_eth_dev_recv(struct l2t
+ 	/* checksums verified by L2TP */
+ 	skb->ip_summed = CHECKSUM_NONE;
+ 
++	/* drop outer flow-hash */
++	skb_clear_hash(skb);
++
+ 	skb_dst_drop(skb);
+ 	nf_reset_ct(skb);
+ 
diff --git a/target/linux/generic/pending-6.1/779-net-vxlan-don-t-learn-non-unicast-L2-destinations.patch b/target/linux/generic/pending-6.1/779-net-vxlan-don-t-learn-non-unicast-L2-destinations.patch
new file mode 100644
index 00000000000000..6c1f5967590078
--- /dev/null
+++ b/target/linux/generic/pending-6.1/779-net-vxlan-don-t-learn-non-unicast-L2-destinations.patch
@@ -0,0 +1,30 @@
+From 3f1a227cb071f65f6ecc4db9f399649869735a7c Mon Sep 17 00:00:00 2001
+From: David Bauer <mail@david-bauer.net>
+Date: Sat, 17 Feb 2024 22:34:59 +0100
+Subject: [PATCH] net vxlan: don't learn non-unicast L2 destinations
+
+This patch avoids learning non-unicast targets in the vxlan FDB.
+They are non-unicast and thus should be sent to the broadcast-IPv6
+instead of a unicast address.
+
+Link: https://lore.kernel.org/netdev/15ee0cc7-9252-466b-8ce7-5225d605dde8@david-bauer.net/
+Link: https://github.com/freifunk-gluon/gluon/issues/3191
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+---
+ drivers/net/vxlan.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/drivers/net/vxlan/vxlan_core.c
++++ b/drivers/net/vxlan/vxlan_core.c
+@@ -1493,6 +1493,10 @@ static bool vxlan_snoop(struct net_devic
+ 	struct vxlan_fdb *f;
+ 	u32 ifindex = 0;
+ 
++	/* Don't learn broadcast packets */
++	if (is_multicast_ether_addr(src_mac) || is_zero_ether_addr(src_mac))
++		return false;
++
+ #if IS_ENABLED(CONFIG_IPV6)
+ 	if (src_ip->sa.sa_family == AF_INET6 &&
+ 	    (ipv6_addr_type(&src_ip->sin6.sin6_addr) & IPV6_ADDR_LINKLOCAL))
diff --git a/target/linux/generic/pending-6.1/790-bus-mhi-core-add-SBL-state-callback.patch b/target/linux/generic/pending-6.1/790-bus-mhi-core-add-SBL-state-callback.patch
index 874df43e7ce6fc..f239355594ad53 100644
--- a/target/linux/generic/pending-6.1/790-bus-mhi-core-add-SBL-state-callback.patch
+++ b/target/linux/generic/pending-6.1/790-bus-mhi-core-add-SBL-state-callback.patch
@@ -20,7 +20,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
 
 --- a/drivers/bus/mhi/host/main.c
 +++ b/drivers/bus/mhi/host/main.c
-@@ -900,6 +900,7 @@ int mhi_process_ctrl_ev_ring(struct mhi_
+@@ -905,6 +905,7 @@ int mhi_process_ctrl_ev_ring(struct mhi_
  			switch (event) {
  			case MHI_EE_SBL:
  				st = DEV_ST_TRANSITION_SBL;
diff --git a/target/linux/generic/pending-6.1/796-net-dsa-mt7530-fix-10M-100M-speed-on-MT7988-switch.patch b/target/linux/generic/pending-6.1/796-net-dsa-mt7530-fix-10M-100M-speed-on-MT7988-switch.patch
new file mode 100644
index 00000000000000..47e3b140c81e1c
--- /dev/null
+++ b/target/linux/generic/pending-6.1/796-net-dsa-mt7530-fix-10M-100M-speed-on-MT7988-switch.patch
@@ -0,0 +1,45 @@
+From a444877c10a665cd8a869e6d37facdb89fd95f79 Mon Sep 17 00:00:00 2001
+Message-ID: <a444877c10a665cd8a869e6d37facdb89fd95f79.1706070008.git.daniel@makrotopia.org>
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Wed, 24 Jan 2024 04:17:11 +0000
+Subject: [PATCH net] net: dsa: mt7530: fix 10M/100M speed on MT7988 switch
+To: Arınç ÜNAL <arinc.unal@arinc9.com>,
+    Daniel Golle <daniel@makrotopia.org>,
+    DENG Qingfang <dqfext@gmail.com>,
+    Sean Wang <sean.wang@mediatek.com>,
+    Andrew Lunn <andrew@lunn.ch>,
+    Florian Fainelli <f.fainelli@gmail.com>,
+    Vladimir Oltean <olteanv@gmail.com>,
+    David S. Miller <davem@davemloft.net>,
+    Eric Dumazet <edumazet@google.com>,
+    Jakub Kicinski <kuba@kernel.org>,
+    Paolo Abeni <pabeni@redhat.com>,
+    Matthias Brugger <matthias.bgg@gmail.com>,
+    AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
+    netdev@vger.kernel.org,
+    linux-kernel@vger.kernel.org,
+    linux-arm-kernel@lists.infradead.org,
+    linux-mediatek@lists.infradead.org
+
+Setup PMCR port register for actual speed and duplex on internally
+connected PHYs of the MT7988 built-in switch. This fixes links with
+speeds other than 1000M.
+
+Fixes: ("110c18bfed414 net: dsa: mt7530: introduce driver for MT7988 built-in switch")
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/net/dsa/mt7530.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2849,8 +2849,7 @@ static void mt753x_phylink_mac_link_up(s
+ 	/* MT753x MAC works in 1G full duplex mode for all up-clocked
+ 	 * variants.
+ 	 */
+-	if (interface == PHY_INTERFACE_MODE_INTERNAL ||
+-	    interface == PHY_INTERFACE_MODE_TRGMII ||
++	if (interface == PHY_INTERFACE_MODE_TRGMII ||
+ 	    (phy_interface_mode_is_8023z(interface))) {
+ 		speed = SPEED_1000;
+ 		duplex = DUPLEX_FULL;
diff --git a/target/linux/generic/pending-6.1/810-pci_disable_common_quirks.patch b/target/linux/generic/pending-6.1/810-pci_disable_common_quirks.patch
index 68ac12f996d11d..ba06196f7cbbff 100644
--- a/target/linux/generic/pending-6.1/810-pci_disable_common_quirks.patch
+++ b/target/linux/generic/pending-6.1/810-pci_disable_common_quirks.patch
@@ -33,7 +33,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
  /*
   * The Mellanox Tavor device gives false positive parity errors.  Disable
   * parity error reporting.
-@@ -3390,6 +3391,8 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_I
+@@ -3393,6 +3394,8 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_I
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
  
@@ -42,7 +42,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
  /*
   * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum.
   * To work around this, query the size it should be configured to by the
-@@ -3415,6 +3418,8 @@ static void quirk_intel_ntb(struct pci_d
+@@ -3418,6 +3421,8 @@ static void quirk_intel_ntb(struct pci_d
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
  
@@ -51,7 +51,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
  /*
   * Some BIOS implementations leave the Intel GPU interrupts enabled, even
   * though no one is handling them (e.g., if the i915 driver is never
-@@ -3453,6 +3458,8 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_IN
+@@ -3456,6 +3461,8 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_IN
  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
  
diff --git a/target/linux/generic/pending-6.1/920-mangle_bootargs.patch b/target/linux/generic/pending-6.1/920-mangle_bootargs.patch
index db7274e7aadb94..4552b4cd66c124 100644
--- a/target/linux/generic/pending-6.1/920-mangle_bootargs.patch
+++ b/target/linux/generic/pending-6.1/920-mangle_bootargs.patch
@@ -13,7 +13,7 @@ Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
 
 --- a/init/Kconfig
 +++ b/init/Kconfig
-@@ -1827,6 +1827,15 @@ config EMBEDDED
+@@ -1836,6 +1836,15 @@ config EMBEDDED
  	  an embedded system so certain expert options are available
  	  for configuration.
  
diff --git a/target/linux/imx/Makefile b/target/linux/imx/Makefile
index 5fb7a4d339ef54..8fd6f239509215 100644
--- a/target/linux/imx/Makefile
+++ b/target/linux/imx/Makefile
@@ -10,7 +10,7 @@ BOARDNAME:=NXP i.MX
 FEATURES:=audio display fpu gpio pcie rtc usb usbgadget squashfs targz nand ubifs boot-part rootfs-part
 SUBTARGETS:=cortexa7 cortexa9
 
-KERNEL_PATCHVER:=5.15
+KERNEL_PATCHVER:=6.1
 
 include $(INCLUDE_DIR)/target.mk
 
diff --git a/target/linux/imx/config-5.15 b/target/linux/imx/config-5.15
deleted file mode 100644
index d3291a59973962..00000000000000
--- a/target/linux/imx/config-5.15
+++ /dev/null
@@ -1,447 +0,0 @@
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MMAP_RND_BITS_MAX=15
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_MXC=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-CONFIG_ARM_CRYPTO=y
-CONFIG_ARM_ERRATA_754322=y
-CONFIG_ARM_ERRATA_764369=y
-CONFIG_ARM_ERRATA_775420=y
-CONFIG_ARM_ERRATA_814220=y
-CONFIG_ARM_HAS_SG_CHAIN=y
-CONFIG_ARM_HEAVY_MB=y
-# CONFIG_ARM_IMX6Q_CPUFREQ is not set
-# CONFIG_ARM_IMX_CPUFREQ_DT is not set
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-CONFIG_ARM_PATCH_IDIV=y
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_ASN1=y
-CONFIG_ASSOCIATIVE_ARRAY=y
-CONFIG_ATA=y
-CONFIG_ATAGS=y
-# CONFIG_ATA_SFF is not set
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_PM=y
-CONFIG_CACHE_L2X0=y
-CONFIG_CLKSRC_IMX_GPT=y
-CONFIG_CLKSRC_MMIO=y
-# CONFIG_CLK_IMX8MM is not set
-# CONFIG_CLK_IMX8MN is not set
-# CONFIG_CLK_IMX8MP is not set
-# CONFIG_CLK_IMX8MQ is not set
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CLZ_TAB=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CPUFREQ_DT=y
-CONFIG_CPUFREQ_DT_PLATDEV=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_THERMAL=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_SPECTRE=y
-CONFIG_CPU_THERMAL=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRC16=y
-CONFIG_CRYPTO_AES_ARM=y
-CONFIG_CRYPTO_AES_ARM_BS=y
-CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=y
-CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
-CONFIG_CRYPTO_AUTHENC=y
-CONFIG_CRYPTO_BLAKE2S_ARM=y
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_CHACHA20=y
-CONFIG_CRYPTO_CHACHA20_NEON=y
-CONFIG_CRYPTO_CRC32=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_CRC32_ARM_CE=y
-CONFIG_CRYPTO_CRYPTD=y
-CONFIG_CRYPTO_CTS=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_DEV_FSL_CAAM=y
-CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API=y
-CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API_DESC=y
-CONFIG_CRYPTO_DEV_FSL_CAAM_COMMON=y
-CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API=y
-CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC=y
-# CONFIG_CRYPTO_DEV_FSL_CAAM_DEBUG is not set
-# CONFIG_CRYPTO_DEV_FSL_CAAM_INTC is not set
-CONFIG_CRYPTO_DEV_FSL_CAAM_JR=y
-CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API=y
-CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE=9
-CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API=y
-CONFIG_CRYPTO_DRBG=y
-CONFIG_CRYPTO_DRBG_HMAC=y
-CONFIG_CRYPTO_DRBG_MENU=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_ENGINE=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_JITTERENTROPY=y
-CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y
-CONFIG_CRYPTO_LIB_DES=y
-CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_RNG_DEFAULT=y
-CONFIG_CRYPTO_RSA=y
-CONFIG_CRYPTO_SEQIV=y
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_SHA1_ARM=y
-CONFIG_CRYPTO_SHA1_ARM_NEON=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA256_ARM=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_SHA512_ARM=y
-CONFIG_CRYPTO_SIMD=y
-CONFIG_CRYPTO_XTS=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-CONFIG_DEBUG_MISC=y
-CONFIG_DECOMPRESS_BZIP2=y
-CONFIG_DECOMPRESS_GZIP=y
-CONFIG_DECOMPRESS_LZO=y
-CONFIG_DECOMPRESS_XZ=y
-CONFIG_DMADEVICES=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_OPS=y
-CONFIG_DMA_REMAP=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DTC=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_ENCRYPTED_KEYS=y
-CONFIG_EXT4_FS=y
-CONFIG_EXT4_FS_POSIX_ACL=y
-CONFIG_EXT4_FS_SECURITY=y
-CONFIG_EXTCON=y
-CONFIG_F2FS_FS=y
-CONFIG_FEC=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-# CONFIG_FSL_DPAA2_SWITCH is not set
-CONFIG_FSL_GUTS=y
-CONFIG_FS_ENCRYPTION=y
-CONFIG_FS_ENCRYPTION_ALGS=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FS_POSIX_ACL=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GENERIC_VDSO_32=y
-# CONFIG_GIANFAR is not set
-CONFIG_GLOB=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_GENERIC=y
-CONFIG_GPIO_MXC=y
-CONFIG_GRO_CELLS=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDEN_BRANCH_PREDICTOR=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HAVE_ARM_ARCH_TIMER=y
-CONFIG_HAVE_SMP=y
-CONFIG_HWMON=y
-CONFIG_HW_RANDOM=y
-CONFIG_HZ_FIXED=0
-CONFIG_HZ_PERIODIC=y
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_IMX=y
-# CONFIG_I2C_IMX_LPI2C is not set
-CONFIG_I2C_SLAVE=y
-# CONFIG_I2C_SLAVE_TESTUNIT is not set
-CONFIG_IMX2_WDT=y
-# CONFIG_IMX7ULP_WDT is not set
-# CONFIG_IMX8MM_THERMAL is not set
-CONFIG_IMX_DMA=y
-# CONFIG_IMX_GPCV2_PM_DOMAINS is not set
-CONFIG_IMX_INTMUX=y
-CONFIG_IMX_IRQSTEER=y
-CONFIG_IMX_SDMA=y
-CONFIG_IMX_THERMAL=y
-# CONFIG_IMX_WEIM is not set
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_JBD2=y
-# CONFIG_JFFS2_FS is not set
-CONFIG_KEYS=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_CQHCI=y
-# CONFIG_MMC_MXC is not set
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_ESDHC_IMX=y
-CONFIG_MMC_SDHCI_IO_ACCESSORS=y
-CONFIG_MMC_SDHCI_OF_ESDHC=y
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MPILIB=y
-CONFIG_MTD_NAND_CORE=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_ECC_SW_HAMMING=y
-CONFIG_MTD_NAND_GPMI_NAND=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-# CONFIG_MX3_IPU is not set
-CONFIG_MXC_CLK=y
-CONFIG_MXS_DMA=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEON=y
-CONFIG_NET_DEVLINK=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_TAG_DSA=y
-CONFIG_NET_DSA_TAG_DSA_COMMON=y
-CONFIG_NET_DSA_TAG_EDSA=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NLS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NR_CPUS=4
-CONFIG_NVMEM=y
-# CONFIG_NVMEM_IMX_IIM is not set
-CONFIG_NVMEM_IMX_OCOTP=y
-# CONFIG_NVMEM_IMX_OCOTP_ELE is not set
-# CONFIG_NVMEM_SNVS_LPGPR is not set
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_OUTER_CACHE=y
-CONFIG_OUTER_CACHE_SYNC=y
-CONFIG_PADATA=y
-CONFIG_PAGE_OFFSET=0x80000000
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_IMX8MM is not set
-# CONFIG_PINCTRL_IMX8MN is not set
-# CONFIG_PINCTRL_IMX8MP is not set
-# CONFIG_PINCTRL_IMX8MQ is not set
-# CONFIG_PINCTRL_IMX8ULP is not set
-CONFIG_PL310_ERRATA_769419=y
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_PM_OPP=y
-CONFIG_PPS=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PWM=y
-# CONFIG_PWM_IMX1 is not set
-CONFIG_PWM_IMX27=y
-# CONFIG_PWM_IMX_TPM is not set
-CONFIG_PWM_SYSFS=y
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-CONFIG_RD_BZIP2=y
-CONFIG_RD_GZIP=y
-CONFIG_RD_LZO=y
-CONFIG_RD_XZ=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_ANATOP=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_PFUZE100=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-# CONFIG_RTC_DRV_CMOS is not set
-# CONFIG_RTC_DRV_IMXDI is not set
-# CONFIG_RTC_DRV_MXC is not set
-# CONFIG_RTC_DRV_MXC_V2 is not set
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_IMX=y
-CONFIG_SERIAL_IMX_CONSOLE=y
-CONFIG_SERIAL_IMX_EARLYCON=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SG_POOL=y
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SOC_BUS=y
-# CONFIG_SOC_IMX50 is not set
-# CONFIG_SOC_IMX51 is not set
-# CONFIG_SOC_IMX53 is not set
-# CONFIG_SOC_IMX6Q is not set
-# CONFIG_SOC_IMX6SL is not set
-# CONFIG_SOC_IMX6SLL is not set
-# CONFIG_SOC_IMX6SX is not set
-# CONFIG_SOC_IMX6UL is not set
-# CONFIG_SOC_IMX7D is not set
-# CONFIG_SOC_IMX7ULP is not set
-# CONFIG_SOC_IMX8M is not set
-# CONFIG_SOC_LS1021A is not set
-# CONFIG_SOC_VF610 is not set
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_BITBANG=y
-# CONFIG_SPI_FSL_LPSPI is not set
-# CONFIG_SPI_FSL_QUADSPI is not set
-CONFIG_SPI_IMX=y
-CONFIG_SPI_MASTER=y
-CONFIG_SRAM=y
-CONFIG_SRAM_EXEC=y
-CONFIG_SRCU=y
-CONFIG_STMP_DEVICE=y
-CONFIG_SWPHY=y
-CONFIG_SWP_EMULATE=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_OF=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UBIFS_FS=y
-# CONFIG_UCLAMP_TASK is not set
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNWINDER_ARM=y
-CONFIG_USB=y
-CONFIG_USB_CHIPIDEA=y
-CONFIG_USB_CHIPIDEA_HOST=y
-CONFIG_USB_CHIPIDEA_IMX=y
-CONFIG_USB_CHIPIDEA_UDC=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_EHCI_HCD=y
-# CONFIG_USB_EHCI_HCD_PLATFORM is not set
-CONFIG_USB_GADGET=y
-CONFIG_USB_MXS_PHY=y
-CONFIG_USB_OTG=y
-CONFIG_USB_PHY=y
-CONFIG_USB_ROLE_SWITCH=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_ULPI_BUS=y
-CONFIG_USE_OF=y
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_VMSPLIT_2G=y
-# CONFIG_VMSPLIT_3G is not set
-CONFIG_WATCHDOG_CORE=y
-CONFIG_XOR_BLOCKS=y
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_ARMTHUMB=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
diff --git a/target/linux/imx/config-6.1 b/target/linux/imx/config-6.1
new file mode 100644
index 00000000000000..837bab909a5eb8
--- /dev/null
+++ b/target/linux/imx/config-6.1
@@ -0,0 +1,486 @@
+CONFIG_ALIGNMENT_TRAP=y
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MMAP_RND_BITS_MAX=15
+CONFIG_ARCH_MULTIPLATFORM=y
+CONFIG_ARCH_MULTI_V6_V7=y
+CONFIG_ARCH_MULTI_V7=y
+CONFIG_ARCH_MXC=y
+CONFIG_ARCH_NR_GPIO=0
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARM=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+CONFIG_ARM_ERRATA_754322=y
+CONFIG_ARM_ERRATA_764369=y
+CONFIG_ARM_ERRATA_775420=y
+CONFIG_ARM_ERRATA_814220=y
+CONFIG_ARM_HAS_GROUP_RELOCS=y
+CONFIG_ARM_HEAVY_MB=y
+# CONFIG_ARM_IMX6Q_CPUFREQ is not set
+# CONFIG_ARM_IMX_CPUFREQ_DT is not set
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+CONFIG_ARM_PATCH_IDIV=y
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_UNWIND=y
+CONFIG_ARM_VIRT_EXT=y
+CONFIG_ASN1=y
+CONFIG_ASSOCIATIVE_ARRAY=y
+CONFIG_ATA=y
+CONFIG_ATAGS=y
+# CONFIG_ATA_SFF is not set
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_PM=y
+CONFIG_CACHE_L2X0=y
+CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CLKSRC_IMX_GPT=y
+CONFIG_CLKSRC_MMIO=y
+# CONFIG_CLK_IMX8MM is not set
+# CONFIG_CLK_IMX8MN is not set
+# CONFIG_CLK_IMX8MP is not set
+# CONFIG_CLK_IMX8MQ is not set
+# CONFIG_CLK_IMX8ULP is not set
+# CONFIG_CLK_IMX93 is not set
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CLZ_TAB=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_CPUFREQ_DT_PLATDEV=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ_THERMAL=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_SPECTRE=y
+CONFIG_CPU_THERMAL=y
+CONFIG_CPU_THUMB_CAPABLE=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_V7=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_AES_ARM=y
+CONFIG_CRYPTO_AES_ARM_BS=y
+CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=y
+CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
+CONFIG_CRYPTO_AUTHENC=y
+CONFIG_CRYPTO_BLAKE2S_ARM=y
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CHACHA20=y
+CONFIG_CRYPTO_CHACHA20_NEON=y
+CONFIG_CRYPTO_CRC32=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_CRC32_ARM_CE=y
+CONFIG_CRYPTO_CRYPTD=y
+CONFIG_CRYPTO_CTS=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_DEV_FSL_CAAM=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API_DESC=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_COMMON=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC=y
+# CONFIG_CRYPTO_DEV_FSL_CAAM_DEBUG is not set
+# CONFIG_CRYPTO_DEV_FSL_CAAM_INTC is not set
+CONFIG_CRYPTO_DEV_FSL_CAAM_JR=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_PRNG_API=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE=9
+CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API=y
+CONFIG_CRYPTO_DRBG=y
+CONFIG_CRYPTO_DRBG_HMAC=y
+CONFIG_CRYPTO_DRBG_MENU=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_ENGINE=y
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y
+CONFIG_CRYPTO_LIB_DES=y
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_SHA256=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RNG_DEFAULT=y
+CONFIG_CRYPTO_RSA=y
+CONFIG_CRYPTO_SEQIV=y
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA1_ARM=y
+CONFIG_CRYPTO_SHA1_ARM_NEON=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA256_ARM=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_SHA512_ARM=y
+CONFIG_CRYPTO_SIMD=y
+CONFIG_CRYPTO_XTS=y
+CONFIG_CRYPTO_ZSTD=y
+CONFIG_CURRENT_POINTER_IN_TPIDRURO=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+CONFIG_DEBUG_MISC=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_LZO=y
+CONFIG_DECOMPRESS_XZ=y
+CONFIG_DMADEVICES=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_OPS=y
+CONFIG_DMA_VIRTUAL_CHANNELS=y
+# CONFIG_DRM_FSL_LDB is not set
+# CONFIG_DRM_IMX8QM_LDB is not set
+# CONFIG_DRM_IMX8QXP_LDB is not set
+# CONFIG_DRM_IMX8QXP_PIXEL_COMBINER is not set
+# CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI is not set
+# CONFIG_DRM_DW_HDMI_GP_AUDIO is not set
+# CONFIG_VIDEO_IMX_MIPI_CSIS is not set
+# CONFIG_VIDEO_DW100 is not set
+# CONFIG_VIDEO_ROCKCHIP_ISP1 is not set
+# CONFIG_VIDEO_HANTRO is not set
+CONFIG_DTC=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_ENCRYPTED_KEYS=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_EXTCON=y
+CONFIG_F2FS_FS=y
+CONFIG_FEC=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+# CONFIG_FSL_DPAA2_SWITCH is not set
+CONFIG_FSL_GUTS=y
+CONFIG_FS_ENCRYPTION=y
+CONFIG_FS_ENCRYPTION_ALGS=y
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC11_NO_ARRAY_BOUNDS=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_VDSO_32=y
+# CONFIG_GIANFAR is not set
+CONFIG_GLOB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_MXC=y
+CONFIG_GPIO_VF610=y
+CONFIG_GRO_CELLS=y
+CONFIG_HARDEN_BRANCH_PREDICTOR=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HAVE_SMP=y
+CONFIG_HWMON=y
+CONFIG_HW_RANDOM=y
+CONFIG_HZ_FIXED=0
+CONFIG_HZ_PERIODIC=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_IMX=y
+# CONFIG_I2C_IMX_LPI2C is not set
+CONFIG_I2C_SLAVE=y
+# CONFIG_I2C_SLAVE_TESTUNIT is not set
+CONFIG_IMX2_WDT=y
+# CONFIG_IMX7ULP_WDT is not set
+# CONFIG_IMX8MM_THERMAL is not set
+CONFIG_IMX_DMA=y
+# CONFIG_IMX_GPCV2_PM_DOMAINS is not set
+CONFIG_IMX_INTMUX=y
+CONFIG_IMX_IRQSTEER=y
+CONFIG_IMX_MU_MSI=m
+CONFIG_IMX_SDMA=y
+CONFIG_IMX_THERMAL=y
+# CONFIG_IMX_WEIM is not set
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IRQCHIP=y
+CONFIG_IRQSTACKS=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+CONFIG_JBD2=y
+# CONFIG_JFFS2_FS is not set
+CONFIG_KEYS=y
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MEMFD_CREATE=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
+CONFIG_MIGRATION=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_CQHCI=y
+# CONFIG_MMC_MXC is not set
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ESDHC_IMX=y
+CONFIG_MMC_SDHCI_IO_ACCESSORS=y
+CONFIG_MMC_SDHCI_OF_ESDHC=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MPILIB=y
+CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+CONFIG_MTD_NAND_GPMI_NAND=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+# CONFIG_MX3_IPU is not set
+CONFIG_MXC_CLK=y
+CONFIG_MXS_DMA=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEON=y
+CONFIG_NET_DEVLINK=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_TAG_DSA=y
+CONFIG_NET_DSA_TAG_DSA_COMMON=y
+CONFIG_NET_DSA_TAG_EDSA=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_SWITCHDEV=y
+CONFIG_NLS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NR_CPUS=4
+CONFIG_NVMEM=y
+# CONFIG_NVMEM_IMX_IIM is not set
+CONFIG_NVMEM_IMX_OCOTP=y
+# CONFIG_NVMEM_IMX_OCOTP_ELE is not set
+CONFIG_NVMEM_LAYOUTS=y
+# CONFIG_NVMEM_SNVS_LPGPR is not set
+CONFIG_NVMEM_SYSFS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_OUTER_CACHE=y
+CONFIG_OUTER_CACHE_SYNC=y
+CONFIG_PADATA=y
+CONFIG_PAGE_OFFSET=0x80000000
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLINK=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_IMX8ULP is not set
+# CONFIG_PINCTRL_IMX93 is not set
+# CONFIG_PINCTRL_IMXRT1050 is not set
+# CONFIG_PINCTRL_IMXRT1170 is not set
+CONFIG_PL310_ERRATA_769419=y
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+CONFIG_PM_OPP=y
+CONFIG_PPS=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_PWM=y
+# CONFIG_PWM_IMX1 is not set
+CONFIG_PWM_IMX27=y
+# CONFIG_PWM_IMX_TPM is not set
+CONFIG_PWM_SYSFS=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_GZIP=y
+CONFIG_RD_LZO=y
+CONFIG_RD_XZ=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_ANATOP=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_PFUZE100=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_IMXDI is not set
+# CONFIG_RTC_DRV_MXC is not set
+# CONFIG_RTC_DRV_MXC_V2 is not set
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_SCHED_THERMAL_PRESSURE=y
+CONFIG_SCSI=y
+CONFIG_SCSI_COMMON=y
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_IMX=y
+CONFIG_SERIAL_IMX_CONSOLE=y
+CONFIG_SERIAL_IMX_EARLYCON=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SG_POOL=y
+CONFIG_SMP=y
+CONFIG_SMP_ON_UP=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SOC_BUS=y
+# CONFIG_SOC_IMX50 is not set
+# CONFIG_SOC_IMX51 is not set
+# CONFIG_SOC_IMX53 is not set
+# CONFIG_SOC_IMX6Q is not set
+# CONFIG_SOC_IMX6SL is not set
+# CONFIG_SOC_IMX6SLL is not set
+# CONFIG_SOC_IMX6SX is not set
+# CONFIG_SOC_IMX6UL is not set
+# CONFIG_SOC_IMX7D is not set
+# CONFIG_SOC_IMX7ULP is not set
+# CONFIG_SOC_IMX8M is not set
+# CONFIG_SOC_IMX9 is not set
+# CONFIG_SOC_LS1021A is not set
+# CONFIG_SOC_VF610 is not set
+CONFIG_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=y
+# CONFIG_SPI_FSL_LPSPI is not set
+# CONFIG_SPI_FSL_QUADSPI is not set
+CONFIG_SPI_IMX=y
+CONFIG_SPI_MASTER=y
+CONFIG_SRAM=y
+CONFIG_SRAM_EXEC=y
+CONFIG_SRCU=y
+CONFIG_STMP_DEVICE=y
+CONFIG_SWPHY=y
+CONFIG_SWP_EMULATE=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_OF=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UBIFS_FS=y
+# CONFIG_UCLAMP_TASK is not set
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_UNWINDER_ARM=y
+CONFIG_USB=y
+CONFIG_USB_CHIPIDEA=y
+CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_USB_CHIPIDEA_IMX=y
+CONFIG_USB_CHIPIDEA_UDC=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_EHCI_HCD=y
+# CONFIG_USB_EHCI_HCD_PLATFORM is not set
+CONFIG_USB_GADGET=y
+CONFIG_USB_MXS_PHY=y
+CONFIG_USB_OTG=y
+CONFIG_USB_PHY=y
+CONFIG_USB_ROLE_SWITCH=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ULPI_BUS=y
+CONFIG_USE_OF=y
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_VMSPLIT_2G=y
+# CONFIG_VMSPLIT_3G is not set
+CONFIG_WATCHDOG_CORE=y
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZSTD_COMMON=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y
diff --git a/target/linux/imx/cortexa9/base-files/etc/board.d/02_network b/target/linux/imx/cortexa9/base-files/etc/board.d/02_network
index 1ef2fcdc65cd2d..3aad761a1568e0 100644
--- a/target/linux/imx/cortexa9/base-files/etc/board.d/02_network
+++ b/target/linux/imx/cortexa9/base-files/etc/board.d/02_network
@@ -34,7 +34,7 @@ gw,imx6q-gw53xx|\
 gw,imx6q-gw5400-a|\
 gw,imx6q-gw54xx|\
 gw,imx6q-gw552x)
-	ucidef_set_interfaces_lan_wan 'eth0' 'eth1'
+	ucidef_set_interfaces_lan_wan 'eth1' 'eth0'
 	;;
 wand,imx6dl-wandboard)
 	ucidef_set_interface_wan 'eth0'
diff --git a/target/linux/imx/image/cortexa9.mk b/target/linux/imx/image/cortexa9.mk
index 2edbbaac4765cf..2321469cc861e8 100644
--- a/target/linux/imx/image/cortexa9.mk
+++ b/target/linux/imx/image/cortexa9.mk
@@ -120,7 +120,8 @@ define Device/gateworks_ventana
 	imx6q-gw5913
   DEVICE_PACKAGES := kmod-sky2 kmod-sound-core kmod-sound-soc-imx \
 	kmod-sound-soc-imx-sgtl5000 kmod-can kmod-can-flexcan kmod-can-raw \
-	kmod-hwmon-gsc kmod-leds-gpio kmod-pps-gpio kobs-ng
+	kmod-hwmon-gsc kmod-leds-gpio kmod-pps-gpio kobs-ng \
+	kmod-gpio-button-hotplug
   KERNEL += | boot-overlay
   IMAGES := img.gz nand.ubi bootfs.tar.gz dtb
   IMAGE/nand.ubi := append-ubi
diff --git a/target/linux/imx/patches-5.15/301-ARM-dts-imx6q-apalis-ixora-make-switch3-reset-button.patch b/target/linux/imx/patches-5.15/301-ARM-dts-imx6q-apalis-ixora-make-switch3-reset-button.patch
deleted file mode 100644
index 8f07f0b1a5111e..00000000000000
--- a/target/linux/imx/patches-5.15/301-ARM-dts-imx6q-apalis-ixora-make-switch3-reset-button.patch
+++ /dev/null
@@ -1,86 +0,0 @@
-From b6764bb27c819cdcf854371db485a43d71f579f3 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Petr=20=C5=A0tetiar?= <ynezz@true.cz>
-Date: Tue, 3 Mar 2020 15:15:57 +0100
-Subject: [PATCH] ARM: dts: imx6q-apalis: ixora: make switch3 reset button
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Petr Štetiar <ynezz@true.cz>
----
- arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts | 15 ++++++++++++++-
- arch/arm/boot/dts/imx6q-apalis-ixora.dts      | 15 ++++++++++++++-
- 2 files changed, 28 insertions(+), 2 deletions(-)
-
---- a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts
-+++ b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts
-@@ -38,7 +38,7 @@
- 	gpio-keys {
- 		compatible = "gpio-keys";
- 		pinctrl-names = "default";
--		pinctrl-0 = <&pinctrl_gpio_keys>;
-+		pinctrl-0 = <&pinctrl_gpio_keys &pinctrl_switch3_ixora>;
- 
- 		wakeup {
- 			label = "Wake-Up";
-@@ -47,6 +47,13 @@
- 			debounce-interval = <10>;
- 			wakeup-source;
- 		};
-+
-+		reset {
-+			label = "reset";
-+			gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
-+			linux,code = <KEY_RESTART>;
-+			debounce-interval = <10>;
-+		};
- 	};
- 
- 	lcd_display: disp0 {
-@@ -275,4 +282,10 @@
- 			MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
- 		>;
- 	};
-+
-+	pinctrl_switch3_ixora: switch3ixora {
-+		fsl,pins = <
-+			MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0
-+		>;
-+	};
- };
---- a/arch/arm/boot/dts/imx6q-apalis-ixora.dts
-+++ b/arch/arm/boot/dts/imx6q-apalis-ixora.dts
-@@ -37,7 +37,7 @@
- 	gpio-keys {
- 		compatible = "gpio-keys";
- 		pinctrl-names = "default";
--		pinctrl-0 = <&pinctrl_gpio_keys>;
-+		pinctrl-0 = <&pinctrl_gpio_keys &pinctrl_switch3_ixora>;
- 
- 		wakeup {
- 			label = "Wake-Up";
-@@ -46,6 +46,13 @@
- 			debounce-interval = <10>;
- 			wakeup-source;
- 		};
-+
-+		reset {
-+			label = "reset";
-+			gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
-+			linux,code = <KEY_RESTART>;
-+			debounce-interval = <10>;
-+		};
- 	};
- 
- 	lcd_display: disp0 {
-@@ -276,4 +283,10 @@
- 			MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
- 		>;
- 	};
-+
-+	pinctrl_switch3_ixora: switch3ixora {
-+		fsl,pins = <
-+			MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0
-+		>;
-+	};
- };
diff --git a/target/linux/imx/patches-5.15/100-bootargs.patch b/target/linux/imx/patches-6.1/100-bootargs.patch
similarity index 100%
rename from target/linux/imx/patches-5.15/100-bootargs.patch
rename to target/linux/imx/patches-6.1/100-bootargs.patch
diff --git a/target/linux/imx/patches-5.15/300-ARM-dts-imx6q-apalis-ixora-add-status-LEDs-aliases.patch b/target/linux/imx/patches-6.1/300-ARM-dts-imx6q-apalis-ixora-add-status-LEDs-aliases.patch
similarity index 93%
rename from target/linux/imx/patches-5.15/300-ARM-dts-imx6q-apalis-ixora-add-status-LEDs-aliases.patch
rename to target/linux/imx/patches-6.1/300-ARM-dts-imx6q-apalis-ixora-add-status-LEDs-aliases.patch
index e14dc484b08a74..9db7098aaf94e4 100644
--- a/target/linux/imx/patches-5.15/300-ARM-dts-imx6q-apalis-ixora-add-status-LEDs-aliases.patch
+++ b/target/linux/imx/patches-6.1/300-ARM-dts-imx6q-apalis-ixora-add-status-LEDs-aliases.patch
@@ -12,9 +12,9 @@ Signed-off-by: Petr Štetiar <ynezz@true.cz>
  arch/arm/boot/dts/imx6q-apalis-ixora.dts      | 12 ++++++++----
  2 files changed, 18 insertions(+), 10 deletions(-)
 
---- a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts
-+++ b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts
-@@ -25,6 +25,10 @@
+--- a/arch/arm/boot/dts/imx6q-apalis-ixora.dts
++++ b/arch/arm/boot/dts/imx6q-apalis-ixora.dts
+@@ -24,6 +24,10 @@
  		i2c2 = &i2c2;
  		rtc0 = &rtc_i2c;
  		rtc1 = &snvs_rtc;
@@ -25,37 +25,35 @@ Signed-off-by: Petr Štetiar <ynezz@true.cz>
  	};
  
  	chosen {
-@@ -92,22 +96,22 @@
+@@ -35,22 +39,22 @@
  		pinctrl-names = "default";
  		pinctrl-0 = <&pinctrl_leds_ixora>;
  
 -		led4-green {
 +		led_running: led4-green {
+ 			gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
  			label = "LED_4_GREEN";
--			gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
-+			gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
  		};
  
 -		led4-red {
 +		led_upgrade: led4-red {
+ 			gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
  			label = "LED_4_RED";
--			gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
-+			gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
  		};
  
 -		led5-green {
 +		led_boot: led5-green {
- 			label = "LED_5_GREEN";
  			gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
+ 			label = "LED_5_GREEN";
  		};
  
 -		led5-red {
 +		led_failsafe: led5-red {
- 			label = "LED_5_RED";
  			gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+ 			label = "LED_5_RED";
  		};
---- a/arch/arm/boot/dts/imx6q-apalis-ixora.dts
-+++ b/arch/arm/boot/dts/imx6q-apalis-ixora.dts
+--- a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.2.dts
++++ b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.2.dts
 @@ -24,6 +24,10 @@
  		i2c2 = &i2c2;
  		rtc0 = &rtc_i2c;
@@ -67,30 +65,32 @@ Signed-off-by: Petr Štetiar <ynezz@true.cz>
  	};
  
  	chosen {
-@@ -91,22 +95,22 @@
+@@ -36,22 +40,22 @@
  		pinctrl-names = "default";
  		pinctrl-0 = <&pinctrl_leds_ixora>;
  
 -		led4-green {
+-			gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
 +		led_running: led4-green {
++			gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
  			label = "LED_4_GREEN";
- 			gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
  		};
  
 -		led4-red {
+-			gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
 +		led_upgrade: led4-red {
++			gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
  			label = "LED_4_RED";
- 			gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
  		};
  
 -		led5-green {
 +		led_boot: led5-green {
- 			label = "LED_5_GREEN";
  			gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
+ 			label = "LED_5_GREEN";
  		};
  
 -		led5-red {
 +		led_failsafe: led5-red {
- 			label = "LED_5_RED";
  			gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+ 			label = "LED_5_RED";
  		};
diff --git a/target/linux/imx/patches-6.1/301-ARM-dts-imx6q-apalis-ixora-make-switch3-reset-button.patch b/target/linux/imx/patches-6.1/301-ARM-dts-imx6q-apalis-ixora-make-switch3-reset-button.patch
new file mode 100644
index 00000000000000..95f572f35e62b1
--- /dev/null
+++ b/target/linux/imx/patches-6.1/301-ARM-dts-imx6q-apalis-ixora-make-switch3-reset-button.patch
@@ -0,0 +1,78 @@
+From b6764bb27c819cdcf854371db485a43d71f579f3 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Petr=20=C5=A0tetiar?= <ynezz@true.cz>
+Date: Tue, 3 Mar 2020 15:15:57 +0100
+Subject: [PATCH] ARM: dts: imx6q-apalis: ixora: make switch3 reset button
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Petr Štetiar <ynezz@true.cz>
+---
+ arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts | 15 ++++++++++++++-
+ arch/arm/boot/dts/imx6q-apalis-ixora.dts      | 15 ++++++++++++++-
+ 2 files changed, 28 insertions(+), 2 deletions(-)
+
+--- a/arch/arm/boot/dts/imx6q-apalis-ixora.dts
++++ b/arch/arm/boot/dts/imx6q-apalis-ixora.dts
+@@ -59,6 +59,17 @@
+ 			label = "LED_5_RED";
+ 		};
+ 	};
++
++	gpio-keys {
++		pinctrl-0 = <&pinctrl_gpio_keys &pinctrl_switch3_ixora>;
++
++		reset {
++			label = "reset";
++			gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
++			linux,code = <KEY_RESTART>;
++			debounce-interval = <10>;
++		};
++	};
+ };
+ 
+ &can1 {
+@@ -181,4 +192,10 @@
+ 			MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
+ 		>;
+ 	};
++
++	pinctrl_switch3_ixora: switch3ixora {
++		fsl,pins = <
++			MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0
++		>;
++	};
+ };
+--- a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.2.dts
++++ b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.2.dts
+@@ -61,6 +61,17 @@
+ 		};
+ 	};
+ 
++	gpio-keys {
++		pinctrl-0 = <&pinctrl_gpio_keys &pinctrl_switch3_ixora>;
++
++		reset {
++			label = "reset";
++			gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
++			linux,code = <KEY_RESTART>;
++			debounce-interval = <10>;
++		};
++	};
++
+ 	reg_3v3_vmmc: regulator-3v3-vmmc {
+ 		compatible = "regulator-fixed";
+ 		enable-active-high;
+@@ -262,6 +273,12 @@
+ 		>;
+ 	};
+ 
++	pinctrl_switch3_ixora: switch3ixora {
++		fsl,pins = <
++			MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0
++		>;
++	};
++
+ 	pinctrl_mmc_cd_sleep: mmccdslpgrp {
+ 		fsl,pins = <
+ 			 /* MMC1 CD */
diff --git a/target/linux/imx/patches-5.15/310-ARM-dts-imx7d-pico-pi-set-aliases.patch b/target/linux/imx/patches-6.1/310-ARM-dts-imx7d-pico-pi-set-aliases.patch
similarity index 100%
rename from target/linux/imx/patches-5.15/310-ARM-dts-imx7d-pico-pi-set-aliases.patch
rename to target/linux/imx/patches-6.1/310-ARM-dts-imx7d-pico-pi-set-aliases.patch
diff --git a/target/linux/imx/patches-5.15/311-ARM-imx7d-pico-pi.dts-add-default-stdout-path.patch b/target/linux/imx/patches-6.1/311-ARM-imx7d-pico-pi.dts-add-default-stdout-path.patch
similarity index 100%
rename from target/linux/imx/patches-5.15/311-ARM-imx7d-pico-pi.dts-add-default-stdout-path.patch
rename to target/linux/imx/patches-6.1/311-ARM-imx7d-pico-pi.dts-add-default-stdout-path.patch
diff --git a/target/linux/ipq40xx/base-files/etc/board.d/02_network b/target/linux/ipq40xx/base-files/etc/board.d/02_network
index babde1b8e220b2..02059580a16476 100644
--- a/target/linux/ipq40xx/base-files/etc/board.d/02_network
+++ b/target/linux/ipq40xx/base-files/etc/board.d/02_network
@@ -124,6 +124,10 @@ ipq40xx_setup_interfaces()
 		ucidef_set_interface_lan "lan1 lan2 lan3 lan4"
 		ucidef_set_interface "wan" device "/dev/cdc-wdm0" protocol "qmi"
 		;;
+	netgear,lbr20)
+		ucidef_set_interface_lan "lan1 lan2"
+		ucidef_set_interface "wan" device "/dev/cdc-wdm0" protocol "qmi"
+		;;
 	*)
 		echo "Unsupported hardware. Network interfaces not initialized"
 		;;
diff --git a/target/linux/ipq40xx/base-files/etc/init.d/modem_switch b/target/linux/ipq40xx/base-files/etc/init.d/modem_switch
new file mode 100755
index 00000000000000..9aeeec8dad014f
--- /dev/null
+++ b/target/linux/ipq40xx/base-files/etc/init.d/modem_switch
@@ -0,0 +1,34 @@
+#!/bin/sh /etc/rc.common
+
+START=15
+STOP=10
+
+boot() {
+	case $(board_name) in
+		netgear,lbr20)
+			echo "0" > /sys/class/gpio/lte_rst/value
+			echo "0" > /sys/class/gpio/lte_pwrkey/value
+			echo "0" > /sys/class/gpio/lte_usb_boot/value
+			echo "0" > /sys/class/gpio/lte_pwm/value
+			sleep 1
+			echo "1" > /sys/class/gpio/lte_pwm/value
+			echo "1" > /sys/class/gpio/lte_pwrkey/value
+			echo "1" > /sys/class/gpio/lte_rst/value
+			sleep 1
+			echo "0" > /sys/class/gpio/lte_pwrkey/value
+			sleep 1
+			echo "1" > /sys/class/gpio/lte_pwrkey/value
+		;;
+	esac
+}
+
+shutdown() {
+	case $(board_name) in
+		netgear,lbr20)
+			echo "0" > /sys/class/gpio/lte_pwrkey/value
+			sleep 1
+			echo "1" > /sys/class/gpio/lte_pwrkey/value
+			sleep 10
+		;;
+	esac
+}
diff --git a/target/linux/ipq40xx/base-files/lib/upgrade/platform.sh b/target/linux/ipq40xx/base-files/lib/upgrade/platform.sh
index 22f2ee9ccc8238..e93432684956ef 100644
--- a/target/linux/ipq40xx/base-files/lib/upgrade/platform.sh
+++ b/target/linux/ipq40xx/base-files/lib/upgrade/platform.sh
@@ -120,6 +120,7 @@ platform_do_upgrade() {
 	glinet,gl-ap1300 |\
 	luma,wrtq-329acn |\
 	mobipromo,cm520-79f |\
+	netgear,lbr20 |\
 	netgear,wac510 |\
 	p2w,r619ac-64m |\
 	p2w,r619ac-128m |\
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-a42.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-a42.dts
index 4cf5d45ff92a60..f43c4b800008a4 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-a42.dts
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-a42.dts
@@ -6,6 +6,7 @@
 #include "qcom-ipq4019.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/soc/qcom,tcsr.h>
 
 / {
@@ -78,17 +79,20 @@
 		compatible = "gpio-leds";
 
 		status_red {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_status_green: status_green {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
 		};
 
 		status_blue {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
 		};
 	};
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dts
index 17b67c23788771..ceaa1edd45972b 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dts
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dts
@@ -3,6 +3,7 @@
 #include "qcom-ipq4019.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/soc/qcom,tcsr.h>
 
 / {
@@ -31,13 +32,15 @@
 		compatible = "gpio-leds";
 
 		status: status {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
 			default-state = "keep";
 		};
 
 		wan {
-			label = "amber:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&ethphy4 1 GPIO_ACTIVE_HIGH>;
 		};
 
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-cap-ac.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-cap-ac.dts
index 0609324310888d..388b2dd5908416 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-cap-ac.dts
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-cap-ac.dts
@@ -4,6 +4,7 @@
 #include "qcom-ipq4019.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/soc/qcom,tcsr.h>
 
 / {
@@ -83,7 +84,8 @@
 		compatible = "gpio-leds";
 
 		power {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
 			default-state = "keep";
 		};
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-cs-w3-wd1200g-eup.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-cs-w3-wd1200g-eup.dts
index ea00dd83f51b07..c388ceca27b900 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-cs-w3-wd1200g-eup.dts
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-cs-w3-wd1200g-eup.dts
@@ -3,6 +3,7 @@
 #include "qcom-ipq4019.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/soc/qcom,tcsr.h>
 
 / {
@@ -66,17 +67,20 @@
 		compatible = "gpio-leds";
 
 		led_status_red: status_red {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status_green: status_green {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status_blue: status_blue {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-dap-2610.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-dap-2610.dts
index 493905d56d8f0a..fef549035d636d 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-dap-2610.dts
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-dap-2610.dts
@@ -3,6 +3,7 @@
 #include "qcom-ipq4019.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/soc/qcom,tcsr.h>
 
 / {
@@ -52,12 +53,14 @@
 		compatible = "gpio-leds";
 
 		led_red: red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
 		};
 
 		led_green: green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-ea6350v3.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-ea6350v3.dts
index d890e83c8991cc..50e7f3d4e0c8b6 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-ea6350v3.dts
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-ea6350v3.dts
@@ -3,6 +3,7 @@
 #include "qcom-ipq4019.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/soc/qcom,tcsr.h>
 
 / {
@@ -86,7 +87,8 @@
 		compatible = "gpio-leds";
 
 		power: status {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
 		};
 	};
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-eap1300.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-eap1300.dts
index 778394a96562d0..e9d4775fd87ad4 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-eap1300.dts
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-eap1300.dts
@@ -3,6 +3,7 @@
 #include "qcom-ipq4019.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/soc/qcom,tcsr.h>
 
 / {
@@ -66,12 +67,14 @@
 		compatible = "gpio-leds";
 
 		power: orange {
-			label = "orange:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
 		};
 
 		lan {
-			label = "blue:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
 		};
 
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-ecw5211.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-ecw5211.dts
index c5804b4896ef80..e74d110b3df38e 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-ecw5211.dts
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-ecw5211.dts
@@ -3,6 +3,7 @@
 #include "qcom-ipq4019.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/soc/qcom,tcsr.h>
 
 / {
@@ -36,7 +37,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "yellow:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_YELLOW>;
 			gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-emd1.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-emd1.dts
index 396595ba5185c5..bca85cf4ab77ee 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-emd1.dts
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-emd1.dts
@@ -3,6 +3,7 @@
 #include "qcom-ipq4019.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/soc/qcom,tcsr.h>
 
 / {
@@ -66,7 +67,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "white:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-emr3500.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-emr3500.dts
index 3616149451456d..701dc936f14b20 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-emr3500.dts
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-emr3500.dts
@@ -3,6 +3,7 @@
 #include "qcom-ipq4019.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/soc/qcom,tcsr.h>
 
 / {
@@ -70,7 +71,8 @@
 		compatible = "gpio-leds";
 
 		power: white {
-			label = "white:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
 		};
 
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-ens620ext.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-ens620ext.dts
index 69275e24b8cd31..17bac82bfeef61 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-ens620ext.dts
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-ens620ext.dts
@@ -3,6 +3,7 @@
 #include "qcom-ipq4019.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/soc/qcom,tcsr.h>
 
 / {
@@ -76,7 +77,8 @@
 		compatible = "gpio-leds";
 
 		power: power {
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-ex61x0v2.dtsi b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-ex61x0v2.dtsi
index 0e1527ad4f6d92..918224607ac73d 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-ex61x0v2.dtsi
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-ex61x0v2.dtsi
@@ -18,6 +18,7 @@
 #include "qcom-ipq4019.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/soc/qcom,tcsr.h>
 
 / {
@@ -107,12 +108,14 @@
 		compatible = "gpio-leds";
 
 		power_amber: power_amber {
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&led_gpio 7 GPIO_ACTIVE_LOW>;
 		};
 
 		power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;
 		};
 
@@ -147,7 +150,8 @@
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&tlmm 1 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-fritzbox-4040.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-fritzbox-4040.dts
index ec1112ee2bc58e..524bcbcb2b2a26 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-fritzbox-4040.dts
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-fritzbox-4040.dts
@@ -3,6 +3,7 @@
 #include "qcom-ipq4019.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/soc/qcom,tcsr.h>
 
 / {
@@ -87,7 +88,8 @@
 		compatible = "gpio-leds";
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&ethphy0 0 GPIO_ACTIVE_HIGH>;
 		};
 
@@ -98,17 +100,20 @@
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&ethphy1 0 GPIO_ACTIVE_HIGH>;
 		};
 
 		power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&ethphy2 1 GPIO_ACTIVE_HIGH>;
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&ethphy3 0 GPIO_ACTIVE_HIGH>;
 		};
 
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-gl-a1300.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-gl-a1300.dts
index a646ec3358f2b2..cdb00932175a65 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-gl-a1300.dts
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-gl-a1300.dts
@@ -3,6 +3,7 @@
 #include "qcom-ipq4019.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/soc/qcom,tcsr.h>
 
 / {
@@ -69,12 +70,14 @@
 		compatible = "gpio-leds";
 
 		led_run: blue {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
 		};
 
 		white {
-			label = "white:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
 		};
 	};
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-gl-ap1300.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-gl-ap1300.dts
index 3f3e7cf6833d06..5fc97d7bb2b6e9 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-gl-ap1300.dts
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-gl-ap1300.dts
@@ -3,6 +3,7 @@
 #include "qcom-ipq4019.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/soc/qcom,tcsr.h>
 
 / {
@@ -91,13 +92,15 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "white:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
 			default-state = "on";
 		};
 
 		wan {
-			label = "white:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
 		};
 	};
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-hap-ac2.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-hap-ac2.dts
index c8868d8b301c97..fa3ed8b054455a 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-hap-ac2.dts
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-hap-ac2.dts
@@ -4,6 +4,7 @@
 #include "qcom-ipq4019.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/soc/qcom,tcsr.h>
 
 / {
@@ -100,7 +101,8 @@
 		compatible = "gpio-leds";
 
 		power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
 			default-state = "keep";
 			panic-indicator;
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-magic-2-wifi-next.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-magic-2-wifi-next.dts
index 1fbc02d62b28d3..501aed54679df8 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-magic-2-wifi-next.dts
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-magic-2-wifi-next.dts
@@ -3,6 +3,7 @@
 #include "qcom-ipq4019.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "devolo Magic 2 WiFi next";
@@ -73,7 +74,8 @@
 		};
 
 		status_wlan {
-			label = "white:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
 			default-state = "keep";
 		};
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-meshpoint-one.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-meshpoint-one.dts
index 62ba76802de5ed..cab34b5a6cd0d6 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-meshpoint-one.dts
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-meshpoint-one.dts
@@ -3,6 +3,8 @@
  * Author: Robert Marko <robert@meshpoint.me>
  */
 
+#include <dt-bindings/leds/common.h>
+
 #include "qcom-ipq4018-jalapeno.dtsi"
 
 / {
@@ -74,7 +76,8 @@
 		compatible = "gpio-leds";
 
 		led_status: status {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&tlmm 63 GPIO_ACTIVE_HIGH>;
 		};
 	};
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-mf287_common.dtsi b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-mf287_common.dtsi
index a688a8aa58664e..3784e62d0b10ed 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-mf287_common.dtsi
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-mf287_common.dtsi
@@ -29,7 +29,6 @@
 		compatible = "gpio-leds";
 
 		led_status: led-0 {
-			label = "blue:power";
 			function = LED_FUNCTION_POWER;
 			color = <LED_COLOR_ID_BLUE>;
 		};
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-nbg6617.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-nbg6617.dts
index ff7252d696ecfe..a9e96835920757 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-nbg6617.dts
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-nbg6617.dts
@@ -3,6 +3,7 @@
 #include "qcom-ipq4019.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/input/linux-event-codes.h>
 #include <dt-bindings/soc/qcom,tcsr.h>
 
@@ -130,12 +131,14 @@
 		pinctrl-names = "default";
 
 		power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
 		};
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
 			trigger-sources = <&usb2_port1>, <&usb3_port1>, <&usb3_port2>;
 			linux,default-trigger = "usbport";
@@ -152,7 +155,8 @@
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
 		};
 	};
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-pa1200.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-pa1200.dts
index 30511e3886052f..f23b58a3f44d9d 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-pa1200.dts
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-pa1200.dts
@@ -6,6 +6,7 @@
 #include "qcom-ipq4019.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/soc/qcom,tcsr.h>
 
 / {
@@ -78,17 +79,20 @@
 		compatible = "gpio-leds";
 
 		led_status_cyan: status_cyan {
-			label = "cyan:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_CYAN>;
 			gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_status_purple: status_purple {
-			label = "purple:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_PURPLE>;
 			gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_status_yellow: status_yellow {
-			label = "yellow:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_YELLOW>;
 			gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
 		};
 	};
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-sxtsq-5-ac.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-sxtsq-5-ac.dts
index de3fa96922e7c2..252f9ad71ae760 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-sxtsq-5-ac.dts
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-sxtsq-5-ac.dts
@@ -4,6 +4,7 @@
 #include "qcom-ipq4019.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/soc/qcom,tcsr.h>
 
 / {
@@ -81,7 +82,8 @@
 		compatible = "gpio-leds";
 
 		power {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
 			default-state = "keep";
 			panic-indicator;
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-wac510.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-wac510.dts
index ae0d8524e5216f..9bcfab44873148 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-wac510.dts
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-wac510.dts
@@ -93,7 +93,6 @@
 		compatible = "gpio-leds";
 
 		led_power_amber: led-0 {
-			label = "amber:power";
 			color = <LED_COLOR_ID_AMBER>;
 			function = LED_FUNCTION_POWER;
 			gpios = <&ssr 6 GPIO_ACTIVE_LOW>;
@@ -101,7 +100,6 @@
 		};
 
 		led_power_green: led-1 {
-			label = "green:power";
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_POWER;
 			gpios = <&ssr 5 GPIO_ACTIVE_LOW>;
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-wap-ac.dtsi b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-wap-ac.dtsi
index 777f46e3af25dc..2b357a1f03335f 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-wap-ac.dtsi
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-wap-ac.dtsi
@@ -4,6 +4,7 @@
 #include "qcom-ipq4019.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/soc/qcom,tcsr.h>
 
 / {
@@ -62,7 +63,8 @@
 		compatible = "gpio-leds";
 
 		power {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
 			default-state = "keep";
 		};
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-wr-1.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-wr-1.dts
index 16951da47fc013..dd56cb215e8e0e 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-wr-1.dts
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-wr-1.dts
@@ -36,14 +36,12 @@
 		pinctrl-names = "default";
 
 		led_power: power {
-			label = "blue:power";
 			gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_BLUE>;
 			function = LED_FUNCTION_POWER;
 		};
 
 		wlan2g {
-			label = "blue:wlan2g";
 			gpios = <&tlmm 1 GPIO_ACTIVE_LOW>;
 			color = <LED_COLOR_ID_BLUE>;
 			function = LED_FUNCTION_WLAN;
@@ -51,7 +49,6 @@
 		};
 
 		wlan5g {
-			label = "blue:wlan5g";
 			gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
 			color = <LED_COLOR_ID_BLUE>;
 			function = LED_FUNCTION_WLAN;
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-wre6606.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-wre6606.dts
index efb267ae369225..7ce0b9e3594d32 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-wre6606.dts
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-wre6606.dts
@@ -18,6 +18,7 @@
 #include "qcom-ipq4019.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/soc/qcom,tcsr.h>
 
 / {
@@ -75,7 +76,8 @@
 		compatible = "gpio-leds";
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
 		};
 
@@ -85,7 +87,8 @@
 		};
 
 		power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
 		};
 
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-a62.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-a62.dts
index 369b5475d0537d..39a52a7c489796 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-a62.dts
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-a62.dts
@@ -6,6 +6,7 @@
 #include "qcom-ipq4019.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/soc/qcom,tcsr.h>
 
 / {
@@ -78,17 +79,20 @@
 		compatible = "gpio-leds";
 
 		status_red {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&tlmm 43 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_status_green: status_green {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
 		};
 
 		status_blue {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
 		};
 	};
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-cm520-79f.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-cm520-79f.dts
index 523fe4e501f4ee..d1c8d798f9f425 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-cm520-79f.dts
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-cm520-79f.dts
@@ -3,6 +3,7 @@
 #include "qcom-ipq4019.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/soc/qcom,tcsr.h>
 
 / {
@@ -118,7 +119,8 @@
 		compatible = "gpio-leds";
 
 		usb {
-			label = "blue:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&tlmm 10 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "usbport";
 			trigger-sources = <&usb3_port1>, <&usb3_port2>, <&usb2_port1>;
@@ -130,7 +132,8 @@
 		};
 
 		wan {
-			label = "blue:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&led_gpio 0 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-e2600ac.dtsi b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-e2600ac.dtsi
index 9689bc566fde22..d22661131130c1 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-e2600ac.dtsi
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-e2600ac.dtsi
@@ -7,6 +7,7 @@
 #include "qcom-ipq4019.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/soc/qcom,tcsr.h>
 
 / {
@@ -130,7 +131,8 @@
 			};
 
 			led3 {
-				label = "green:usb";
+				function = LED_FUNCTION_USB;
+				color = <LED_COLOR_ID_GREEN>;
 				gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
 				trigger-sources = <&usb2_port1>, <&usb3_port1>, <&usb3_port2>;
 				linux,default-trigger = "usbport";
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-ea8300.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-ea8300.dts
index 5a738da33d3a69..1b9276ede2f8d6 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-ea8300.dts
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-ea8300.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qcom-ipq4019-xx8300.dtsi"
 
 / {
@@ -34,12 +36,14 @@
 		};
 
 		led_wps: wps {
-			label = "white:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_wps_amber: wps_amber {
-			label = "amber:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
 			panic-indicator;
 		};
@@ -52,7 +56,8 @@
 		// On back panel, above USB socket
 
 		led_usb: usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&usb3_port1>, <&usb3_port2>,
 					  <&usb2_port1>;
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-eap2200.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-eap2200.dts
index 63fd66901d8cbc..000acd196cfd94 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-eap2200.dts
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-eap2200.dts
@@ -3,6 +3,7 @@
 #include "qcom-ipq4019.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "EnGenius EAP2200";
@@ -29,7 +30,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-fritzbox-7530.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-fritzbox-7530.dts
index 336da52f27248c..a118bdf26bd6ca 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-fritzbox-7530.dts
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-fritzbox-7530.dts
@@ -3,6 +3,7 @@
 #include "qcom-ipq4019.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/soc/qcom,tcsr.h>
 
 / {
@@ -102,7 +103,8 @@
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&tlmm 34 GPIO_ACTIVE_LOW>;
 		};
 
@@ -112,12 +114,14 @@
 		};
 
 		power_green: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&tlmm 45 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-fritzrepeater-1200.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-fritzrepeater-1200.dts
index 723f2161c61472..7d683cdf652dbd 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-fritzrepeater-1200.dts
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-fritzrepeater-1200.dts
@@ -3,6 +3,7 @@
 #include "qcom-ipq4019.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/soc/qcom,tcsr.h>
 
 / {
@@ -73,17 +74,20 @@
 		compatible = "gpio-leds";
 
 		power_red: power_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
 		};
 
 		power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
 		};
 
 		power_yellow {
-			label = "yellow:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_YELLOW>;
 			gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-fritzrepeater-3000.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-fritzrepeater-3000.dts
index 41dec72542421d..25559843845547 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-fritzrepeater-3000.dts
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-fritzrepeater-3000.dts
@@ -3,6 +3,7 @@
 #include "qcom-ipq4019.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/soc/qcom,tcsr.h>
 
 / {
@@ -81,7 +82,8 @@
 		};
 
 		power_led: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&tlmm 33 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-gl-b2200.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-gl-b2200.dts
index 5cb5f7ca082fa3..9f645dd65739a9 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-gl-b2200.dts
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-gl-b2200.dts
@@ -3,6 +3,7 @@
 #include "qcom-ipq4019.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/soc/qcom,tcsr.h>
 
 / {
@@ -84,7 +85,8 @@
 		compatible = "gpio-leds";
 
 		power_blue {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&tlmm 57 GPIO_ACTIVE_HIGH>;
 			default-state = "on";
 		};
@@ -93,7 +95,8 @@
 			gpios = <&tlmm 60 GPIO_ACTIVE_HIGH>;
 		};
 		power_white {
-			label = "white:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
 		};
 		internet_white {
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-habanero-dvk.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-habanero-dvk.dts
index d5d00b2eefe8d1..26e9941a9fdc8d 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-habanero-dvk.dts
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-habanero-dvk.dts
@@ -4,6 +4,7 @@
 #include "qcom-ipq4019.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/soc/qcom,tcsr.h>
 
 / {
@@ -92,7 +93,8 @@
 		compatible = "gpio-leds";
 
 		led_status: status {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
 			panic-indicator;
 		};
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-hap-ac3-lte6-kit.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-hap-ac3-lte6-kit.dts
index 6459fc3b927ec9..52af1f125e26d8 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-hap-ac3-lte6-kit.dts
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-hap-ac3-lte6-kit.dts
@@ -4,6 +4,7 @@
 #include "qcom-ipq4019.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/soc/qcom,tcsr.h>
 
 / {
@@ -73,23 +74,27 @@
 		compatible = "gpio-leds";
 
 		led_status_blue: status-blue {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_status_red: status-red {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
 			panic-indicator;
 		};
 
 		led_status_green: status-green {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&tlmm 23 GPIO_ACTIVE_HIGH>;
 		};
 
@@ -99,7 +104,8 @@
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&tlmm 28 GPIO_ACTIVE_HIGH>;
 		};
 
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-hap-ac3.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-hap-ac3.dts
index 35c4c26a2cb4bb..4e2b4574d386d2 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-hap-ac3.dts
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-hap-ac3.dts
@@ -4,6 +4,7 @@
 #include "qcom-ipq4019.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/soc/qcom,tcsr.h>
 
 / {
@@ -101,23 +102,27 @@
 		compatible = "gpio-leds";
 
 		led_status_blue: status-blue {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_status_red: status-red {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
 			panic-indicator;
 		};
 
 		led_status_green: status-green {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&tlmm 23 GPIO_ACTIVE_HIGH>;
 		};
 
@@ -127,7 +132,8 @@
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&tlmm 28 GPIO_ACTIVE_HIGH>;
 		};
 
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-lbr20.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-lbr20.dts
new file mode 100644
index 00000000000000..4e5497cbc30c20
--- /dev/null
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-lbr20.dts
@@ -0,0 +1,516 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/qcom,tcsr.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+	model = "Netgear LBR20";
+	compatible = "netgear,lbr20";
+
+	chosen {
+		bootargs-append = "ubi.mtd=ubi root=/dev/ubiblock0_0";
+	};
+
+	aliases {
+		led-boot = &led_backlight_white;
+		led-failsafe = &led_status_green;
+		led-running = &led_status_green;
+		led-upgrade = &led_status_red;
+		label-mac-device = &gmac;
+	};
+
+	keys {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "reset";
+			gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+
+		wps {
+			label = "wps";
+			gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WPS_BUTTON>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_status_green: led-status-green {
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
+			default-state = "keep";
+		};
+
+		led_status_red: led-status-red {
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
+			gpios = <&tlmm 23 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	gpio_export {
+		compatible = "gpio-export";
+		#size-cells = <0>;
+
+		lte_rst {
+			gpio-export,name = "lte_rst";
+			gpio-export,output = <1>;
+			gpios = <&tlmm 28 GPIO_ACTIVE_HIGH>;
+		};
+
+		lte_pwrkey {
+			gpio-export,name = "lte_pwrkey";
+			gpio-export,output = <1>;
+			gpios = <&tlmm 29 GPIO_ACTIVE_HIGH>;
+		};
+
+		lte_usb_boot {
+			gpio-export,name = "lte_usb_boot";
+			gpio-export,output = <0>;
+			gpios = <&tlmm 30 GPIO_ACTIVE_HIGH>;
+		};
+
+		lte_pwm {
+			gpio-export,name = "lte_pwm";
+			gpio-export,output = <1>;
+			gpios = <&tlmm 31 GPIO_ACTIVE_HIGH>;
+		};
+
+	};
+
+	soc {
+
+		tcsr@1949000 {
+			compatible = "qcom,tcsr";
+			reg = <0x1949000 0x100>;
+			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+		};
+
+		tcsr@194b000 {
+			status = "okay";
+
+			compatible = "qcom,tcsr";
+			reg = <0x194b000 0x100>;
+			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
+		};
+
+		ess_tcsr@1953000 {
+			compatible = "qcom,tcsr";
+			reg = <0x1953000 0x1000>;
+			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
+		};
+
+		tcsr@1957000 {
+			compatible = "qcom,tcsr";
+			reg = <0x1957000 0x100>;
+			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+		};
+		
+	};
+};
+
+&prng {
+	status = "okay";
+};
+
+&mdio {
+	status = "okay";
+	pinctrl-0 = <&mdio_pins>;
+	pinctrl-names = "default";
+};
+
+&crypto {
+	status = "okay";
+};
+
+&watchdog {
+	status = "okay";
+};
+
+&usb2_hs_phy {
+	status = "okay";
+};
+
+&usb2 {
+	status = "okay";
+};
+
+&usb3_ss_phy {
+	status = "okay";
+};
+
+&usb3_hs_phy {
+	status = "okay";
+};
+
+&usb3 {
+	status = "okay";
+};
+
+&blsp_dma {
+	status = "okay";
+};
+
+&qpic_bam {
+	status = "okay";
+};
+
+&tlmm {
+	mdio_pins: mdio-pinmux {
+		mux_mdio {
+			pins = "gpio6";
+			function = "mdio";
+			bias-pull-up;
+		};
+
+		mux_mdc {
+			pins = "gpio7";
+			function = "mdc";
+			bias-pull-up;
+		};
+	};
+
+	serial_pins: serial-pinmux {
+		function = "blsp_uart0";
+		pins = "gpio16", "gpio17";
+		bias-disable;
+	};
+
+	nand_pins: nand-pins {
+		pullups {
+			pins =	"gpio52", "gpio53", "gpio58", "gpio59";
+			function = "qpic";
+			bias-pull-up;
+		};
+
+		pulldowns {
+			pins =	"gpio54", "gpio55", "gpio56",
+				"gpio57", "gpio60", "gpio61",
+				"gpio62", "gpio63", "gpio64",
+				"gpio65", "gpio66", "gpio67",
+				"gpio68", "gpio69";
+			function = "qpic";
+			bias-pull-down;
+		};
+	};
+};
+
+&nand {
+	pinctrl-0 = <&nand_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	nand@0 {
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "0:SBL1";
+				reg = <0x00000000 0x00100000>;
+				read-only;
+			};
+
+			partition@100000 {
+				label = "0:MIBIB";
+				reg = <0x00100000 0x00100000>;
+				read-only;
+			};
+
+			partition@200000 {
+				label = "0:BOOTCONFIG";
+				reg = <0x00200000 0x00100000>;
+				read-only;
+			};
+
+			partition@300000 {
+				label = "0:QSEE";
+				reg = <0x00300000 0x00100000>;
+				read-only;
+			};
+
+			partition@400000 {
+				label = "0:QSEE_1";
+				reg = <0x00400000 0x00100000>;
+				read-only;
+			};
+
+			partition@500000 {
+				label = "0:CDT";
+				reg = <0x00500000 0x00080000>;
+				read-only;
+			};
+
+			partition@580000 {
+				label = "0:CDT_1";
+				reg = <0x00580000 0x00080000>;
+				read-only;
+			};
+
+			partition@600000 {
+				label = "0:BOOTCONFIG1";
+				reg = <0x00600000 0x00080000>;
+				read-only;
+			};
+
+			partition@680000 {
+				label = "0:APPSBLENV";
+				reg = <0x00680000 0x00080000>;
+			};
+
+			partition@700000 {
+				label = "0:APPSBL";
+				reg = <0x00700000 0x00200000>;
+				read-only;
+			};
+
+			partition@900000 {
+				label = "0:APPSBL_1";
+				reg = <0x00900000 0x00200000>;
+				read-only;
+			};
+
+			partition@b00000 {
+				label = "0:ART";
+				reg = <0x00b00000 0x00080000>;
+				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					precal_art_1000: precal@1000 {
+						reg = <0x1000 0x2f20>;
+					};
+
+					precal_art_5000: precal@5000 {
+						reg = <0x5000 0x2f20>;
+					};
+
+					precal_art_9000: precal@9000 {
+						reg = <0x9000 0x2f20>;
+					};
+
+				};
+			};
+
+			partition@b80000 {
+				label = "0:ART.bak";
+				reg = <0x00b80000 0x00080000>;
+				read-only;
+			};
+
+			partition@c00000 {
+				label = "config";
+				reg = <0x00c00000 0x00100000>;
+				read-only;
+			};
+
+			partition@d00000 {
+				label = "boarddata1";
+				reg = <0x00d00000 0x00080000>;
+				read-only;
+				
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					mac_address_lan: macaddr@0 {
+						compatible = "mac-base";
+						reg = <0x0 0x6>;
+						#nvmem-cell-cells = <1>;
+					};
+
+					mac_address_wan: macaddr@6 {
+						compatible = "mac-base";
+						reg = <0x6 0x6>;
+						#nvmem-cell-cells = <1>;
+					};
+
+					mac_address_wlan_5g: macaddr@c {
+						compatible = "mac-base";
+						reg = <0xc 0x6>;
+						#nvmem-cell-cells = <1>;
+					};
+
+					mac_address_wlan_2nd5g: macaddr@12 {
+						compatible = "mac-base";
+						reg = <0x12 0x6>;
+						#nvmem-cell-cells = <1>;
+					};
+
+				};
+			};
+
+			partition@d80000 {
+				label = "boarddata2";
+				reg = <0x00d80000 0x00040000>;
+				read-only;
+			};
+
+			partition@dc0000 {
+				label = "pot";
+				reg = <0x00dc0000 0x00100000>;
+				read-only;
+			};
+
+			partition@ec0000 {
+				label = "boarddata1.bak";
+				reg = <0x00ec0000 0x00080000>;
+				read-only;
+			};
+
+			partition@f40000 {
+				label = "boarddata2.bak";
+				reg = <0x00f40000 0x00040000>;
+				read-only;
+			};
+
+			partition@f80000 {
+				label = "language";
+				reg = <0x00f80000 0x00300000>;
+				read-only;
+			};
+
+			partition@1280000 {
+				label = "cert";
+				reg = <0x01280000 0x00080000>;
+				read-only;
+			};
+
+			partition@1300000 {
+				label = "ntgrdata";
+				reg = <0x01300000 0x09300000>;
+			};
+
+			partition@a600000 {
+				label = "kernel";
+				reg = <0x0a600000 0x00700000>;
+			};
+
+			partition@a9c0000 {
+				label = "ubi";
+				reg = <0x0ad00000 0x05300000>;
+			};
+
+		};
+	};
+};
+
+&blsp1_i2c3 {
+	status = "okay";
+
+	led-controller {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "ti,tlc59108"; /* really is tlc59208f */
+		reg = <0x27>;
+
+		led_backlight_green: led-backlight-green {
+			function = LED_FUNCTION_BACKLIGHT;
+			color = <LED_COLOR_ID_GREEN>;
+			reg = <0x0>;
+			linux,default-trigger = "default-off";
+		};
+
+		led_backlight_red: led-backlight-red {
+			function = LED_FUNCTION_BACKLIGHT;
+			color = <LED_COLOR_ID_RED>;
+			reg = <0x1>;
+			linux,default-trigger = "default-off";
+		};
+
+		led_backlight_blue: led-backlight-blue {
+			function = LED_FUNCTION_BACKLIGHT;
+			color = <LED_COLOR_ID_BLUE>;
+			reg = <0x2>;
+			linux,default-trigger = "default-off";
+		};
+
+		led_backlight_white: led-backlight-white {
+			function = LED_FUNCTION_BACKLIGHT;
+			color = <LED_COLOR_ID_WHITE>;
+			reg = <0x3>;
+			linux,default-trigger = "default-off";
+		};
+
+	};
+};
+
+&blsp1_uart1 {
+	status = "okay";
+	pinctrl-0 = <&serial_pins>;
+	pinctrl-names = "default";
+};
+
+&cryptobam {
+	status = "okay";
+};
+
+&gmac {
+	status = "okay";
+	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&mac_address_lan 0>;
+};
+
+&switch {
+	status = "okay";
+};
+
+&swport4 {
+	status = "okay";
+	label = "lan1";
+};
+
+&swport5 {
+	status = "okay";
+	label = "lan2";
+};
+
+&pcie0 {
+	status = "okay";
+	perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
+	wake-gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
+
+	bridge@0,0 {
+		reg = <0x00000000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+
+		wifi@1,0 {
+			compatible = "qcom,ath10k";
+			status = "okay";
+			reg = <0x00010000 0 0 0 0>;
+			ieee80211-freq-limit = <5170000 5350000>;
+			nvmem-cell-names = "pre-calibration", "mac-address";
+			nvmem-cells = <&precal_art_9000>, <&mac_address_wlan_2nd5g 0>;
+			qcom,ath10k-calibration-variant = "Netgear-LBR20";
+		};
+	};
+};
+
+&wifi0 {
+	status = "okay";
+	nvmem-cell-names = "pre-calibration", "mac-address";
+	nvmem-cells = <&precal_art_1000>, <&mac_address_lan 0>;
+	qcom,ath10k-calibration-variant = "Netgear-LBR20";
+};
+
+&wifi1 {
+	status = "okay";
+	ieee80211-freq-limit = <5470000 5815000>;
+	nvmem-cell-names = "pre-calibration", "mac-address";
+	nvmem-cells = <&precal_art_5000>, <&mac_address_wlan_5g 0>;
+	qcom,ath10k-calibration-variant = "Netgear-LBR20";
+};
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-le1.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-le1.dts
index 677b4baa0fabed..c4e7d0b2075a81 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-le1.dts
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-le1.dts
@@ -3,6 +3,7 @@
 #include "qcom-ipq4019.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/soc/qcom,tcsr.h>
 
 / {
@@ -33,7 +34,8 @@
 		compatible = "gpio-leds";
 
 		led_usb: usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&tlmm 36 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "usbport";
 			trigger-sources = <&usb3_port1>, <&usb3_port2>, <&usb2_port1>;
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-lhgg-60ad.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-lhgg-60ad.dts
index 38bacfa2bafb6a..4f0eaa625bc526 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-lhgg-60ad.dts
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-lhgg-60ad.dts
@@ -18,6 +18,7 @@
 #include "qcom-ipq4019.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/soc/qcom,tcsr.h>
 
 / {
@@ -95,7 +96,8 @@
 		compatible = "gpio-leds";
 
 		power: power {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
 			default-state = "keep";
 			panic-indicator;
@@ -107,7 +109,8 @@
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;
 		};
 
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-mf18a.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-mf18a.dts
index 1b1a697f13b029..6987515720408f 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-mf18a.dts
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-mf18a.dts
@@ -43,20 +43,22 @@
 		};
 
 		led_power: led-1 {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>;
 			default-state = "keep";
 		};
 
 		led-2 {
 			function = LED_FUNCTION_WLAN;
-			label = "blue:wlan";
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&tlmm 23 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "phy0tpt";
 		};
 
 		led-3 {
-			label = "red:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&tlmm 26 GPIO_ACTIVE_HIGH>;
 		};
 
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-mf289f.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-mf289f.dts
index bbb2cb902a2e5c..7c0194ccc0243c 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-mf289f.dts
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-mf289f.dts
@@ -40,7 +40,6 @@
 		compatible = "gpio-leds";
 
 		led_status: led-0 {
-			label = "blue:power";
 			function = LED_FUNCTION_POWER;
 			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-mr8300.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-mr8300.dts
index 057aa880285b9c..ab9a05c7887d9b 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-mr8300.dts
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-mr8300.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qcom-ipq4019-xx8300.dtsi"
 
 / {
@@ -19,25 +21,29 @@
 		compatible = "gpio-leds";
 
 		led_red: red {
-			label = "red:alarm";
+			function = LED_FUNCTION_ALARM;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&tlmm 47 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_amber: amber {
-			label = "amber:programming";
+			function = LED_FUNCTION_PROGRAMMING;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
 			panic-indicator;
 		};
 
 		led_blue: blue {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
 		};
 
 		// On back panel, above USB socket
 
 		led_usb: usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&usb3_port1>, <&usb3_port2>,
 					  <&usb2_port1>;
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-orbi.dtsi b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-orbi.dtsi
index 44dbfef529d9af..849df642016ea4 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-orbi.dtsi
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-orbi.dtsi
@@ -3,6 +3,7 @@
 #include "qcom-ipq4019.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/soc/qcom,tcsr.h>
 
 / {
@@ -86,34 +87,40 @@
 		compatible = "gpio-leds";
 
 		led-0 {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&tlmm 63 GPIO_ACTIVE_HIGH>;
 			default-state = "on";
 		};
 
 		led-1 {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>;
 			panic-indicator;
 		};
 
 		led_status_green: led-2 {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&tlmm 53 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_status_red: led-3 {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_status_blue: led-4 {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&tlmm 57 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_status_white: led-5 {
-			label = "white:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&tlmm 60 GPIO_ACTIVE_HIGH>;
 		};
 	};
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-pa2200.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-pa2200.dts
index 49d399ed1f45d3..ed333c499004f2 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-pa2200.dts
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-pa2200.dts
@@ -6,6 +6,7 @@
 #include "qcom-ipq4019.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/soc/qcom,tcsr.h>
 
 / {
@@ -66,7 +67,8 @@
 		compatible = "gpio-leds";
 
 		led_power_orange: power_orange {
-			label = "orange:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
 		};
 
@@ -89,7 +91,8 @@
 		};
 
 		led_status_blue: status_blue {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-r619ac.dtsi b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-r619ac.dtsi
index 1566dc39a9dfc2..90e5455b25a969 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-r619ac.dtsi
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-r619ac.dtsi
@@ -74,14 +74,12 @@
 		compatible = "gpio-leds";
 
 		led_sys: led-0 {
-			label = "blue:sys";
 			gpios = <&tlmm 39 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_BLUE>;
 			function = LED_FUNCTION_POWER;
 		};
 
 		led-1 {
-			label = "blue:wlan2g";
 			gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "phy0tpt";
 			color = <LED_COLOR_ID_BLUE>;
@@ -90,7 +88,6 @@
 		};
 
 		led-2 {
-			label = "blue:wlan5g";
 			gpios = <&tlmm 50 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "phy1tpt";
 			color = <LED_COLOR_ID_BLUE>;
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-rt-ac42u.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-rt-ac42u.dts
index f746acfbb950db..70849d71d67fab 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-rt-ac42u.dts
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-rt-ac42u.dts
@@ -106,7 +106,6 @@
 			color = <LED_COLOR_ID_BLUE>;
 			function = LED_FUNCTION_STATUS;
 			gpios = <&tlmm 40 GPIO_ACTIVE_LOW>;
-			label = "blue:status";
 		};
 
 		led-1 {
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-rtl30vw.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-rtl30vw.dts
index 6fce4ae87b5162..e2df1d1997609d 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-rtl30vw.dts
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-rtl30vw.dts
@@ -7,6 +7,7 @@
 #include <dt-bindings/soc/qcom,tcsr.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Cell C RTL30VW";
@@ -48,13 +49,15 @@
 
 		led_power_blue: power_blue {
 			gpios = <&led_gpio 0 GPIO_ACTIVE_HIGH>;
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			default-state = "on";
 		};
 
 		led_power_red: power_red {
 			gpios = <&led_gpio 1 GPIO_ACTIVE_HIGH>;
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 		};
 
 		tp28 {
@@ -83,7 +86,8 @@
 
 		wps {
 			gpios = <&led_gpio 10 GPIO_ACTIVE_HIGH>;
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 		};
 
 		voip {
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-whw03v2.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-whw03v2.dts
index 963c0915bb3712..7b3f1c8bb73627 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-whw03v2.dts
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-whw03v2.dts
@@ -275,7 +275,6 @@
 		#size-cells = <0>;
 
 		led_red: red@0 {
-			label = "red";
 			color = <LED_COLOR_ID_RED>;
 			function = LED_FUNCTION_INDICATOR;
 			linux,default-trigger = "none";
@@ -283,7 +282,6 @@
 		};
 
 		led_green: green@1 {
-			label = "green";
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_INDICATOR;
 			linux,default-trigger = "none";
@@ -291,7 +289,6 @@
 		};
 
 		led_blue: blue@2 {
-			label = "blue";
 			color = <LED_COLOR_ID_BLUE>;
 			function = LED_FUNCTION_INDICATOR;
 			linux,default-trigger = "default-on";
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-wtr-m2133hp.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-wtr-m2133hp.dts
index 7d030c489d2fe6..00b5897b7dbac1 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-wtr-m2133hp.dts
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-wtr-m2133hp.dts
@@ -6,6 +6,7 @@
 
 #include "qcom-ipq4019.dtsi"
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/soc/qcom,tcsr.h>
 
@@ -81,17 +82,20 @@
 		compatible = "gpio-leds";
 
 		led_power_white: power_white {
-			label = "white:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&tlmm 40 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_power_orange: power_orange {
-			label = "orange:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&tlmm 25 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_power_blue: power_blue {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&tlmm 43 GPIO_ACTIVE_HIGH>;
 		};
 
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-x1pro.dtsi b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-x1pro.dtsi
index 3de6a10433714b..fe3650ca580771 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-x1pro.dtsi
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-x1pro.dtsi
@@ -3,6 +3,7 @@
 #include "qcom-ipq4019.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/soc/qcom,tcsr.h>
 
 / {
@@ -98,7 +99,8 @@
 			pinctrl-names = "default";
 
 			led_status: status {
-				label = "green:status";
+				function = LED_FUNCTION_STATUS;
+				color = <LED_COLOR_ID_GREEN>;
 				gpios = <&tlmm 68 GPIO_ACTIVE_LOW>;
 			};
 		};
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4029-gl-b1300.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4029-gl-b1300.dts
index 9694973132f5ea..13ed26d5d6082e 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4029-gl-b1300.dts
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4029-gl-b1300.dts
@@ -17,6 +17,7 @@
 #include "qcom-ipq4019.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/soc/qcom,tcsr.h>
 
 / {
@@ -108,7 +109,8 @@
 		compatible = "gpio-leds";
 
 		power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
 			default-state = "on";
 		};
@@ -119,7 +121,8 @@
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
 		};
 	};
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4029-gl-s1300.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4029-gl-s1300.dts
index 1a61b8161de71b..e7236824aa0fee 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4029-gl-s1300.dts
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4029-gl-s1300.dts
@@ -3,6 +3,7 @@
 #include "qcom-ipq4019.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/soc/qcom,tcsr.h>
 
 / {
@@ -93,7 +94,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&tlmm 57 GPIO_ACTIVE_HIGH>;
 			default-state = "on";
 		};
@@ -104,7 +106,8 @@
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&tlmm 60 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4029-insect-common.dtsi b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4029-insect-common.dtsi
index dbf6c14b7246d5..2b9f73eb24442d 100644
--- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4029-insect-common.dtsi
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4029-insect-common.dtsi
@@ -102,7 +102,8 @@
 		compatible = "gpio-leds";
 
 		power_orange: power {
-			label = "orange:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
 			panic-indicator;
 		};
diff --git a/target/linux/ipq40xx/files/drivers/net/phy/qca807x.c b/target/linux/ipq40xx/files/drivers/net/phy/qca807x.c
deleted file mode 100644
index abfc11e121c1bf..00000000000000
--- a/target/linux/ipq40xx/files/drivers/net/phy/qca807x.c
+++ /dev/null
@@ -1,844 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright (c) 2020 Sartura Ltd.
- *
- * Author: Robert Marko <robert.marko@sartura.hr>
- *
- * Qualcomm QCA8072 and QCA8075 PHY driver
- */
-
-#include <linux/version.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/phy.h>
-#include <linux/bitfield.h>
-#include <linux/ethtool_netlink.h>
-#include <linux/gpio.h>
-#include <linux/sfp.h>
-
-#include <dt-bindings/net/qcom-qca807x.h>
-
-#define PHY_ID_QCA8072		0x004dd0b2
-#define PHY_ID_QCA8075		0x004dd0b1
-#define PHY_ID_QCA807X_PSGMII	0x06820805
-
-/* Downshift */
-#define QCA807X_SMARTSPEED_EN			BIT(5)
-#define QCA807X_SMARTSPEED_RETRY_LIMIT_MASK	GENMASK(4, 2)
-#define QCA807X_SMARTSPEED_RETRY_LIMIT_DEFAULT	5
-#define QCA807X_SMARTSPEED_RETRY_LIMIT_MIN	2
-#define QCA807X_SMARTSPEED_RETRY_LIMIT_MAX	9
-
-/* Cable diagnostic test (CDT) */
-#define QCA807X_CDT						0x16
-#define QCA807X_CDT_ENABLE					BIT(15)
-#define QCA807X_CDT_ENABLE_INTER_PAIR_SHORT			BIT(13)
-#define QCA807X_CDT_STATUS					BIT(11)
-#define QCA807X_CDT_MMD3_STATUS					0x8064
-#define QCA807X_CDT_MDI0_STATUS_MASK				GENMASK(15, 12)
-#define QCA807X_CDT_MDI1_STATUS_MASK				GENMASK(11, 8)
-#define QCA807X_CDT_MDI2_STATUS_MASK				GENMASK(7, 4)
-#define QCA807X_CDT_MDI3_STATUS_MASK				GENMASK(3, 0)
-#define QCA807X_CDT_RESULTS_INVALID				0x0
-#define QCA807X_CDT_RESULTS_OK					0x1
-#define QCA807X_CDT_RESULTS_OPEN				0x2
-#define QCA807X_CDT_RESULTS_SAME_SHORT				0x3
-#define QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI1_SAME_OK	0x4
-#define QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI2_SAME_OK	0x8
-#define QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI3_SAME_OK	0xc
-#define QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI1_SAME_OPEN	0x6
-#define QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI2_SAME_OPEN	0xa
-#define QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI3_SAME_OPEN	0xe
-#define QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI1_SAME_SHORT	0x7
-#define QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI2_SAME_SHORT	0xb
-#define QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI3_SAME_SHORT	0xf
-#define QCA807X_CDT_RESULTS_BUSY				0x9
-#define QCA807X_CDT_MMD3_MDI0_LENGTH				0x8065
-#define QCA807X_CDT_MMD3_MDI1_LENGTH				0x8066
-#define QCA807X_CDT_MMD3_MDI2_LENGTH				0x8067
-#define QCA807X_CDT_MMD3_MDI3_LENGTH				0x8068
-#define QCA807X_CDT_SAME_SHORT_LENGTH_MASK			GENMASK(15, 8)
-#define QCA807X_CDT_CROSS_SHORT_LENGTH_MASK			GENMASK(7, 0)
-
-#define QCA807X_CHIP_CONFIGURATION				0x1f
-#define QCA807X_BT_BX_REG_SEL					BIT(15)
-#define QCA807X_BT_BX_REG_SEL_FIBER				0
-#define QCA807X_BT_BX_REG_SEL_COPPER				1
-#define QCA807X_CHIP_CONFIGURATION_MODE_CFG_MASK		GENMASK(3, 0)
-#define QCA807X_CHIP_CONFIGURATION_MODE_QSGMII_SGMII		4
-#define QCA807X_CHIP_CONFIGURATION_MODE_PSGMII_FIBER		3
-#define QCA807X_CHIP_CONFIGURATION_MODE_PSGMII_ALL_COPPER	0
-
-#define QCA807X_MEDIA_SELECT_STATUS				0x1a
-#define QCA807X_MEDIA_DETECTED_COPPER				BIT(5)
-#define QCA807X_MEDIA_DETECTED_1000_BASE_X			BIT(4)
-#define QCA807X_MEDIA_DETECTED_100_BASE_FX			BIT(3)
-
-#define QCA807X_MMD7_FIBER_MODE_AUTO_DETECTION			0x807e
-#define QCA807X_MMD7_FIBER_MODE_AUTO_DETECTION_EN		BIT(0)
-
-#define QCA807X_MMD7_1000BASE_T_POWER_SAVE_PER_CABLE_LENGTH	0x801a
-#define QCA807X_CONTROL_DAC_MASK				GENMASK(2, 0)
-
-#define QCA807X_MMD7_LED_100N_1				0x8074
-#define QCA807X_MMD7_LED_100N_2				0x8075
-#define QCA807X_MMD7_LED_1000N_1			0x8076
-#define QCA807X_MMD7_LED_1000N_2			0x8077
-#define QCA807X_LED_TXACT_BLK_EN_2			BIT(10)
-#define QCA807X_LED_RXACT_BLK_EN_2			BIT(9)
-#define QCA807X_LED_GT_ON_EN_2				BIT(6)
-#define QCA807X_LED_HT_ON_EN_2				BIT(5)
-#define QCA807X_LED_BT_ON_EN_2				BIT(4)
-#define QCA807X_GPIO_FORCE_EN				BIT(15)
-#define QCA807X_GPIO_FORCE_MODE_MASK			GENMASK(14, 13)
-
-#define QCA807X_INTR_ENABLE				0x12
-#define QCA807X_INTR_STATUS				0x13
-#define QCA807X_INTR_ENABLE_AUTONEG_ERR			BIT(15)
-#define QCA807X_INTR_ENABLE_SPEED_CHANGED		BIT(14)
-#define QCA807X_INTR_ENABLE_DUPLEX_CHANGED		BIT(13)
-#define QCA807X_INTR_ENABLE_LINK_FAIL			BIT(11)
-#define QCA807X_INTR_ENABLE_LINK_SUCCESS		BIT(10)
-
-#define QCA807X_FUNCTION_CONTROL			0x10
-#define QCA807X_FC_MDI_CROSSOVER_MODE_MASK		GENMASK(6, 5)
-#define QCA807X_FC_MDI_CROSSOVER_AUTO			3
-#define QCA807X_FC_MDI_CROSSOVER_MANUAL_MDIX		1
-#define QCA807X_FC_MDI_CROSSOVER_MANUAL_MDI		0
-
-#define QCA807X_PHY_SPECIFIC_STATUS			0x11
-#define QCA807X_SS_SPEED_AND_DUPLEX_RESOLVED		BIT(11)
-#define QCA807X_SS_SPEED_MASK				GENMASK(15, 14)
-#define QCA807X_SS_SPEED_1000				2
-#define QCA807X_SS_SPEED_100				1
-#define QCA807X_SS_SPEED_10				0
-#define QCA807X_SS_DUPLEX				BIT(13)
-#define QCA807X_SS_MDIX					BIT(6)
-
-/* PSGMII PHY specific */
-#define PSGMII_QSGMII_DRIVE_CONTROL_1			0xb
-#define PSGMII_QSGMII_TX_DRIVER_MASK			GENMASK(7, 4)
-#define PSGMII_MODE_CTRL				0x6d
-#define PSGMII_MODE_CTRL_AZ_WORKAROUND_MASK		BIT(0)
-#define PSGMII_MMD3_SERDES_CONTROL			0x805a
-
-struct qca807x_gpio_priv {
-	struct phy_device *phy;
-};
-
-static int qca807x_get_downshift(struct phy_device *phydev, u8 *data)
-{
-	int val, cnt, enable;
-
-	val = phy_read(phydev, MII_NWAYTEST);
-	if (val < 0)
-		return val;
-
-	enable = FIELD_GET(QCA807X_SMARTSPEED_EN, val);
-	cnt = FIELD_GET(QCA807X_SMARTSPEED_RETRY_LIMIT_MASK, val) + 2;
-
-	*data = enable ? cnt : DOWNSHIFT_DEV_DISABLE;
-
-	return 0;
-}
-
-static int qca807x_set_downshift(struct phy_device *phydev, u8 cnt)
-{
-	int ret, val;
-
-	if (cnt > QCA807X_SMARTSPEED_RETRY_LIMIT_MAX ||
-	    (cnt < QCA807X_SMARTSPEED_RETRY_LIMIT_MIN && cnt != DOWNSHIFT_DEV_DISABLE))
-		return -EINVAL;
-
-	if (!cnt) {
-		ret = phy_clear_bits(phydev, MII_NWAYTEST, QCA807X_SMARTSPEED_EN);
-	} else {
-		val = QCA807X_SMARTSPEED_EN;
-		val |= FIELD_PREP(QCA807X_SMARTSPEED_RETRY_LIMIT_MASK, cnt - 2);
-
-		phy_modify(phydev, MII_NWAYTEST,
-			   QCA807X_SMARTSPEED_EN |
-			   QCA807X_SMARTSPEED_RETRY_LIMIT_MASK,
-			   val);
-	}
-
-	ret = genphy_soft_reset(phydev);
-
-	return ret;
-}
-
-static int qca807x_get_tunable(struct phy_device *phydev,
-			       struct ethtool_tunable *tuna, void *data)
-{
-	switch (tuna->id) {
-	case ETHTOOL_PHY_DOWNSHIFT:
-		return qca807x_get_downshift(phydev, data);
-	default:
-		return -EOPNOTSUPP;
-	}
-}
-
-static int qca807x_set_tunable(struct phy_device *phydev,
-			       struct ethtool_tunable *tuna, const void *data)
-{
-	switch (tuna->id) {
-	case ETHTOOL_PHY_DOWNSHIFT:
-		return qca807x_set_downshift(phydev, *(const u8 *)data);
-	default:
-		return -EOPNOTSUPP;
-	}
-}
-
-static bool qca807x_distance_valid(int result)
-{
-	switch (result) {
-	case QCA807X_CDT_RESULTS_OPEN:
-	case QCA807X_CDT_RESULTS_SAME_SHORT:
-	case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI1_SAME_OK:
-	case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI2_SAME_OK:
-	case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI3_SAME_OK:
-	case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI1_SAME_OPEN:
-	case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI2_SAME_OPEN:
-	case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI3_SAME_OPEN:
-	case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI1_SAME_SHORT:
-	case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI2_SAME_SHORT:
-	case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI3_SAME_SHORT:
-		return true;
-	}
-	return false;
-}
-
-static int qca807x_report_length(struct phy_device *phydev,
-				 int pair, int result)
-{
-	int length;
-	int ret;
-
-	ret = phy_read_mmd(phydev, MDIO_MMD_PCS, QCA807X_CDT_MMD3_MDI0_LENGTH + pair);
-	if (ret < 0)
-		return ret;
-
-	switch (result) {
-	case ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT:
-		length = (FIELD_GET(QCA807X_CDT_SAME_SHORT_LENGTH_MASK, ret) * 800) / 10;
-		break;
-	case ETHTOOL_A_CABLE_RESULT_CODE_OPEN:
-	case ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT:
-		length = (FIELD_GET(QCA807X_CDT_CROSS_SHORT_LENGTH_MASK, ret) * 800) / 10;
-		break;
-	}
-
-	ethnl_cable_test_fault_length(phydev, pair, length);
-
-	return 0;
-}
-
-static int qca807x_cable_test_report_trans(int result)
-{
-	switch (result) {
-	case QCA807X_CDT_RESULTS_OK:
-		return ETHTOOL_A_CABLE_RESULT_CODE_OK;
-	case QCA807X_CDT_RESULTS_OPEN:
-		return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
-	case QCA807X_CDT_RESULTS_SAME_SHORT:
-		return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
-	case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI1_SAME_OK:
-	case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI2_SAME_OK:
-	case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI3_SAME_OK:
-	case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI1_SAME_OPEN:
-	case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI2_SAME_OPEN:
-	case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI3_SAME_OPEN:
-	case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI1_SAME_SHORT:
-	case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI2_SAME_SHORT:
-	case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI3_SAME_SHORT:
-		return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;
-	default:
-		return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
-	}
-}
-
-static int qca807x_cable_test_report(struct phy_device *phydev)
-{
-	int pair0, pair1, pair2, pair3;
-	int ret;
-
-	ret = phy_read_mmd(phydev, MDIO_MMD_PCS, QCA807X_CDT_MMD3_STATUS);
-	if (ret < 0)
-		return ret;
-
-	pair0 = FIELD_GET(QCA807X_CDT_MDI0_STATUS_MASK, ret);
-	pair1 = FIELD_GET(QCA807X_CDT_MDI1_STATUS_MASK, ret);
-	pair2 = FIELD_GET(QCA807X_CDT_MDI2_STATUS_MASK, ret);
-	pair3 = FIELD_GET(QCA807X_CDT_MDI3_STATUS_MASK, ret);
-
-	ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
-				qca807x_cable_test_report_trans(pair0));
-	ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_B,
-				qca807x_cable_test_report_trans(pair1));
-	ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_C,
-				qca807x_cable_test_report_trans(pair2));
-	ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_D,
-				qca807x_cable_test_report_trans(pair3));
-
-	if (qca807x_distance_valid(pair0))
-		qca807x_report_length(phydev, 0, qca807x_cable_test_report_trans(pair0));
-	if (qca807x_distance_valid(pair1))
-		qca807x_report_length(phydev, 1, qca807x_cable_test_report_trans(pair1));
-	if (qca807x_distance_valid(pair2))
-		qca807x_report_length(phydev, 2, qca807x_cable_test_report_trans(pair2));
-	if (qca807x_distance_valid(pair3))
-		qca807x_report_length(phydev, 3, qca807x_cable_test_report_trans(pair3));
-
-	return 0;
-}
-
-static int qca807x_cable_test_get_status(struct phy_device *phydev,
-					 bool *finished)
-{
-	int val;
-
-	*finished = false;
-
-	val = phy_read(phydev, QCA807X_CDT);
-	if (!((val & QCA807X_CDT_ENABLE) && (val & QCA807X_CDT_STATUS))) {
-		*finished = true;
-
-		return qca807x_cable_test_report(phydev);
-	}
-
-	return 0;
-}
-
-static int qca807x_cable_test_start(struct phy_device *phydev)
-{
-	int val, ret;
-
-	val = phy_read(phydev, QCA807X_CDT);
-	/* Enable inter-pair short check as well */
-	val &= ~QCA807X_CDT_ENABLE_INTER_PAIR_SHORT;
-	val |= QCA807X_CDT_ENABLE;
-	ret = phy_write(phydev, QCA807X_CDT, val);
-
-	return ret;
-}
-
-#ifdef CONFIG_GPIOLIB
-static int qca807x_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
-{
-	return GPIO_LINE_DIRECTION_OUT;
-}
-
-static int qca807x_gpio_get_reg(unsigned int offset)
-{
-	return QCA807X_MMD7_LED_100N_2 + (offset % 2) * 2;
-}
-
-static int qca807x_gpio_get(struct gpio_chip *gc, unsigned int offset)
-{
-	struct qca807x_gpio_priv *priv = gpiochip_get_data(gc);
-	int val;
-
-	val = phy_read_mmd(priv->phy, MDIO_MMD_AN, qca807x_gpio_get_reg(offset));
-
-	return FIELD_GET(QCA807X_GPIO_FORCE_MODE_MASK, val);
-}
-
-static void qca807x_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
-{
-	struct qca807x_gpio_priv *priv = gpiochip_get_data(gc);
-	int val;
-
-	val = phy_read_mmd(priv->phy, MDIO_MMD_AN, qca807x_gpio_get_reg(offset));
-	val &= ~QCA807X_GPIO_FORCE_MODE_MASK;
-	val |= QCA807X_GPIO_FORCE_EN;
-	val |= FIELD_PREP(QCA807X_GPIO_FORCE_MODE_MASK, value);
-
-	phy_write_mmd(priv->phy, MDIO_MMD_AN, qca807x_gpio_get_reg(offset), val);
-}
-
-static int qca807x_gpio_dir_out(struct gpio_chip *gc, unsigned int offset, int value)
-{
-	qca807x_gpio_set(gc, offset, value);
-
-	return 0;
-}
-
-static int qca807x_gpio(struct phy_device *phydev)
-{
-	struct device *dev = &phydev->mdio.dev;
-	struct qca807x_gpio_priv *priv;
-	struct gpio_chip *gc;
-
-	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
-	if (!priv)
-		return -ENOMEM;
-
-	priv->phy = phydev;
-
-	gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL);
-	if (!gc)
-		return -ENOMEM;
-
-	gc->label = dev_name(dev);
-	gc->base = -1;
-	gc->ngpio = 2;
-	gc->parent = dev;
-	gc->owner = THIS_MODULE;
-	gc->can_sleep = true;
-	gc->get_direction = qca807x_gpio_get_direction;
-	gc->direction_output = qca807x_gpio_dir_out;
-	gc->get = qca807x_gpio_get;
-	gc->set = qca807x_gpio_set;
-
-	return devm_gpiochip_add_data(dev, gc, priv);
-}
-#endif
-
-static int qca807x_read_copper_status(struct phy_device *phydev)
-{
-	int ss, err, old_link = phydev->link;
-
-	/* Update the link, but return if there was an error */
-	err = genphy_update_link(phydev);
-	if (err)
-		return err;
-
-	/* why bother the PHY if nothing can have changed */
-	if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link)
-		return 0;
-
-	phydev->speed = SPEED_UNKNOWN;
-	phydev->duplex = DUPLEX_UNKNOWN;
-	phydev->pause = 0;
-	phydev->asym_pause = 0;
-
-	err = genphy_read_lpa(phydev);
-	if (err < 0)
-		return err;
-
-	/* Read the QCA807x PHY-Specific Status register copper page,
-	 * which indicates the speed and duplex that the PHY is actually
-	 * using, irrespective of whether we are in autoneg mode or not.
-	 */
-	ss = phy_read(phydev, QCA807X_PHY_SPECIFIC_STATUS);
-	if (ss < 0)
-		return ss;
-
-	if (ss & QCA807X_SS_SPEED_AND_DUPLEX_RESOLVED) {
-		int sfc;
-
-		sfc = phy_read(phydev, QCA807X_FUNCTION_CONTROL);
-		if (sfc < 0)
-			return sfc;
-
-		switch (FIELD_GET(QCA807X_SS_SPEED_MASK, ss)) {
-		case QCA807X_SS_SPEED_10:
-			phydev->speed = SPEED_10;
-			break;
-		case QCA807X_SS_SPEED_100:
-			phydev->speed = SPEED_100;
-			break;
-		case QCA807X_SS_SPEED_1000:
-			phydev->speed = SPEED_1000;
-			break;
-		}
-		if (ss & QCA807X_SS_DUPLEX)
-			phydev->duplex = DUPLEX_FULL;
-		else
-			phydev->duplex = DUPLEX_HALF;
-
-		if (ss & QCA807X_SS_MDIX)
-			phydev->mdix = ETH_TP_MDI_X;
-		else
-			phydev->mdix = ETH_TP_MDI;
-
-		switch (FIELD_GET(QCA807X_FC_MDI_CROSSOVER_MODE_MASK, sfc)) {
-		case QCA807X_FC_MDI_CROSSOVER_MANUAL_MDI:
-			phydev->mdix_ctrl = ETH_TP_MDI;
-			break;
-		case QCA807X_FC_MDI_CROSSOVER_MANUAL_MDIX:
-			phydev->mdix_ctrl = ETH_TP_MDI_X;
-			break;
-		case QCA807X_FC_MDI_CROSSOVER_AUTO:
-			phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
-			break;
-		}
-	}
-
-	if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete)
-		phy_resolve_aneg_pause(phydev);
-
-	return 0;
-}
-
-static int qca807x_read_fiber_status(struct phy_device *phydev)
-{
-	int ss, err, lpa, old_link = phydev->link;
-
-	/* Update the link, but return if there was an error */
-	err = genphy_update_link(phydev);
-	if (err)
-		return err;
-
-	/* why bother the PHY if nothing can have changed */
-	if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link)
-		return 0;
-
-	phydev->speed = SPEED_UNKNOWN;
-	phydev->duplex = DUPLEX_UNKNOWN;
-	phydev->pause = 0;
-	phydev->asym_pause = 0;
-
-	if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) {
-		lpa = phy_read(phydev, MII_LPA);
-		if (lpa < 0)
-			return lpa;
-
-		linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
-				 phydev->lp_advertising, lpa & LPA_LPACK);
-		linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
-				 phydev->lp_advertising, lpa & LPA_1000XFULL);
-		linkmode_mod_bit(ETHTOOL_LINK_MODE_Pause_BIT,
-				 phydev->lp_advertising, lpa & LPA_1000XPAUSE);
-		linkmode_mod_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
-				 phydev->lp_advertising,
-				 lpa & LPA_1000XPAUSE_ASYM);
-
-		phy_resolve_aneg_linkmode(phydev);
-	}
-
-	/* Read the QCA807x PHY-Specific Status register fiber page,
-	 * which indicates the speed and duplex that the PHY is actually
-	 * using, irrespective of whether we are in autoneg mode or not.
-	 */
-	ss = phy_read(phydev, QCA807X_PHY_SPECIFIC_STATUS);
-	if (ss < 0)
-		return ss;
-
-	if (ss & QCA807X_SS_SPEED_AND_DUPLEX_RESOLVED) {
-		switch (FIELD_GET(QCA807X_SS_SPEED_MASK, ss)) {
-		case QCA807X_SS_SPEED_100:
-			phydev->speed = SPEED_100;
-			break;
-		case QCA807X_SS_SPEED_1000:
-			phydev->speed = SPEED_1000;
-			break;
-		}
-
-		if (ss & QCA807X_SS_DUPLEX)
-			phydev->duplex = DUPLEX_FULL;
-		else
-			phydev->duplex = DUPLEX_HALF;
-	}
-
-	return 0;
-}
-
-static int qca807x_read_status(struct phy_device *phydev)
-{
-	if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported)) {
-		switch (phydev->port) {
-		case PORT_FIBRE:
-			return qca807x_read_fiber_status(phydev);
-		case PORT_TP:
-			return qca807x_read_copper_status(phydev);
-		default:
-			return -EINVAL;
-		}
-	} else
-		return qca807x_read_copper_status(phydev);
-}
-
-static int qca807x_config_intr(struct phy_device *phydev)
-{
-	int ret, val;
-
-	val = phy_read(phydev, QCA807X_INTR_ENABLE);
-
-	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
-		/* Check for combo port as it has fewer interrupts */
-		if (phy_read(phydev, QCA807X_CHIP_CONFIGURATION)) {
-			val |= QCA807X_INTR_ENABLE_SPEED_CHANGED;
-			val |= QCA807X_INTR_ENABLE_LINK_FAIL;
-			val |= QCA807X_INTR_ENABLE_LINK_SUCCESS;
-		} else {
-			val |= QCA807X_INTR_ENABLE_AUTONEG_ERR;
-			val |= QCA807X_INTR_ENABLE_SPEED_CHANGED;
-			val |= QCA807X_INTR_ENABLE_DUPLEX_CHANGED;
-			val |= QCA807X_INTR_ENABLE_LINK_FAIL;
-			val |= QCA807X_INTR_ENABLE_LINK_SUCCESS;
-		}
-		ret = phy_write(phydev, QCA807X_INTR_ENABLE, val);
-	} else {
-		ret = phy_write(phydev, QCA807X_INTR_ENABLE, 0);
-	}
-
-	return ret;
-}
-
-static irqreturn_t qca807x_handle_interrupt(struct phy_device *phydev)
-{
-	int irq_status, int_enabled;
-
-	irq_status = phy_read(phydev, QCA807X_INTR_STATUS);
-	if (irq_status < 0) {
-		phy_error(phydev);
-		return IRQ_NONE;
-	}
-
-	/* Read the current enabled interrupts */
-	int_enabled = phy_read(phydev, QCA807X_INTR_ENABLE);
-	if (int_enabled < 0) {
-		phy_error(phydev);
-		return IRQ_NONE;
-	}
-
-	/* See if this was one of our enabled interrupts */
-	if (!(irq_status & int_enabled))
-		return IRQ_NONE;
-
-	phy_trigger_machine(phydev);
-
-	return IRQ_HANDLED;
-}
-
-static int qca807x_led_config(struct phy_device *phydev)
-{
-	struct device_node *node = phydev->mdio.dev.of_node;
-	bool led_config = false;
-	int val;
-
-	val = phy_read_mmd(phydev, MDIO_MMD_AN, QCA807X_MMD7_LED_1000N_1);
-	if (val < 0)
-		return val;
-
-	if (of_property_read_bool(node, "qcom,single-led-1000")) {
-		val |= QCA807X_LED_TXACT_BLK_EN_2;
-		val |= QCA807X_LED_RXACT_BLK_EN_2;
-		val |= QCA807X_LED_GT_ON_EN_2;
-
-		led_config = true;
-	}
-
-	if (of_property_read_bool(node, "qcom,single-led-100")) {
-		val |= QCA807X_LED_HT_ON_EN_2;
-
-		led_config = true;
-	}
-
-	if (of_property_read_bool(node, "qcom,single-led-10")) {
-		val |= QCA807X_LED_BT_ON_EN_2;
-
-		led_config = true;
-	}
-
-	if (led_config)
-		return phy_write_mmd(phydev, MDIO_MMD_AN, QCA807X_MMD7_LED_1000N_1, val);
-	else
-		return 0;
-}
-
-static int qca807x_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
-{
-	struct phy_device *phydev = upstream;
-	__ETHTOOL_DECLARE_LINK_MODE_MASK(support) = { 0, };
-	phy_interface_t iface;
-	int ret;
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(6,1,0)
-	DECLARE_PHY_INTERFACE_MASK(interfaces);
-
-	sfp_parse_support(phydev->sfp_bus, id, support, interfaces);
-#else
-	sfp_parse_support(phydev->sfp_bus, id, support);
-#endif
-	iface = sfp_select_interface(phydev->sfp_bus, support);
-
-	dev_info(&phydev->mdio.dev, "%s SFP module inserted\n", phy_modes(iface));
-
-	switch (iface) {
-	case PHY_INTERFACE_MODE_1000BASEX:
-	case PHY_INTERFACE_MODE_100BASEX:
-		/* Set PHY mode to PSGMII combo (1/4 copper + combo ports) mode */
-		ret = phy_modify(phydev,
-				 QCA807X_CHIP_CONFIGURATION,
-				 QCA807X_CHIP_CONFIGURATION_MODE_CFG_MASK,
-				 QCA807X_CHIP_CONFIGURATION_MODE_PSGMII_FIBER);
-		/* Enable fiber mode autodection (1000Base-X or 100Base-FX) */
-		ret = phy_set_bits_mmd(phydev,
-				       MDIO_MMD_AN,
-				       QCA807X_MMD7_FIBER_MODE_AUTO_DETECTION,
-				       QCA807X_MMD7_FIBER_MODE_AUTO_DETECTION_EN);
-		/* Select fiber page */
-		ret = phy_clear_bits(phydev,
-				     QCA807X_CHIP_CONFIGURATION,
-				     QCA807X_BT_BX_REG_SEL);
-
-		phydev->port = PORT_FIBRE;
-		break;
-	default:
-		dev_err(&phydev->mdio.dev, "Incompatible SFP module inserted\n");
-		return -EINVAL;
-	}
-
-	return ret;
-}
-
-static void qca807x_sfp_remove(void *upstream)
-{
-	struct phy_device *phydev = upstream;
-
-	/* Select copper page */
-	phy_set_bits(phydev,
-		     QCA807X_CHIP_CONFIGURATION,
-		     QCA807X_BT_BX_REG_SEL);
-
-	phydev->port = PORT_TP;
-}
-
-static const struct sfp_upstream_ops qca807x_sfp_ops = {
-	.attach = phy_sfp_attach,
-	.detach = phy_sfp_detach,
-	.module_insert = qca807x_sfp_insert,
-	.module_remove = qca807x_sfp_remove,
-};
-
-static int qca807x_config(struct phy_device *phydev)
-{
-	struct device_node *node = phydev->mdio.dev.of_node;
-	int control_dac, ret = 0;
-	u32 of_control_dac;
-
-	/* Check for Combo port */
-	if (phy_read(phydev, QCA807X_CHIP_CONFIGURATION)) {
-		int psgmii_serdes;
-
-		/* Prevent PSGMII going into hibernation via PSGMII self test */
-		psgmii_serdes = phy_read_mmd(phydev, MDIO_MMD_PCS, PSGMII_MMD3_SERDES_CONTROL);
-		psgmii_serdes &= ~BIT(1);
-		ret = phy_write_mmd(phydev, MDIO_MMD_PCS,
-				    PSGMII_MMD3_SERDES_CONTROL,
-				    psgmii_serdes);
-	}
-
-	if (!of_property_read_u32(node, "qcom,control-dac", &of_control_dac)) {
-		control_dac = phy_read_mmd(phydev, MDIO_MMD_AN,
-					   QCA807X_MMD7_1000BASE_T_POWER_SAVE_PER_CABLE_LENGTH);
-		control_dac &= ~QCA807X_CONTROL_DAC_MASK;
-		control_dac |= FIELD_PREP(QCA807X_CONTROL_DAC_MASK, of_control_dac);
-		ret = phy_write_mmd(phydev, MDIO_MMD_AN,
-				    QCA807X_MMD7_1000BASE_T_POWER_SAVE_PER_CABLE_LENGTH,
-				    control_dac);
-	}
-
-	/* Optionally configure LED-s */
-	if (IS_ENABLED(CONFIG_GPIOLIB)) {
-		/* Check whether PHY-s pins are used as GPIO-s */
-		if (!of_property_read_bool(node, "gpio-controller"))
-			ret = qca807x_led_config(phydev);
-	} else {
-		ret = qca807x_led_config(phydev);
-	}
-
-	return ret;
-}
-
-static int qca807x_probe(struct phy_device *phydev)
-{
-	struct device_node *node = phydev->mdio.dev.of_node;
-	int ret = 0;
-
-	if (IS_ENABLED(CONFIG_GPIOLIB)) {
-		/* Do not register a GPIO controller unless flagged for it */
-		if (of_property_read_bool(node, "gpio-controller"))
-			ret = qca807x_gpio(phydev);
-	}
-
-	/* Attach SFP bus on combo port*/
-	if (phy_read(phydev, QCA807X_CHIP_CONFIGURATION)) {
-		ret = phy_sfp_probe(phydev, &qca807x_sfp_ops);
-		linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported);
-		linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->advertising);
-	}
-
-	return ret;
-}
-
-static int qca807x_psgmii_config(struct phy_device *phydev)
-{
-	struct device_node *node = phydev->mdio.dev.of_node;
-	int tx_amp, ret = 0;
-	u32 tx_driver_strength;
-
-	/* Workaround to enable AZ transmitting ability */
-	ret = phy_clear_bits_mmd(phydev,
-				 MDIO_MMD_PMAPMD,
-				 PSGMII_MODE_CTRL,
-				 PSGMII_MODE_CTRL_AZ_WORKAROUND_MASK);
-
-	/* PSGMII/QSGMII TX amp set to DT defined value instead of default 600mV */
-	if (!of_property_read_u32(node, "qcom,tx-driver-strength", &tx_driver_strength)) {
-		tx_amp = phy_read(phydev, PSGMII_QSGMII_DRIVE_CONTROL_1);
-		tx_amp &= ~PSGMII_QSGMII_TX_DRIVER_MASK;
-		tx_amp |= FIELD_PREP(PSGMII_QSGMII_TX_DRIVER_MASK, tx_driver_strength);
-		ret = phy_write(phydev, PSGMII_QSGMII_DRIVE_CONTROL_1, tx_amp);
-	}
-
-	return ret;
-}
-
-static struct phy_driver qca807x_drivers[] = {
-	{
-		PHY_ID_MATCH_EXACT(PHY_ID_QCA8072),
-		.name           = "Qualcomm QCA8072",
-		.flags		= PHY_POLL_CABLE_TEST,
-		/* PHY_GBIT_FEATURES */
-		.probe		= qca807x_probe,
-		.config_init	= qca807x_config,
-		.read_status	= qca807x_read_status,
-		.config_intr	= qca807x_config_intr,
-		.handle_interrupt = qca807x_handle_interrupt,
-		.soft_reset	= genphy_soft_reset,
-		.get_tunable	= qca807x_get_tunable,
-		.set_tunable	= qca807x_set_tunable,
-		.resume		= genphy_resume,
-		.suspend	= genphy_suspend,
-		.cable_test_start	= qca807x_cable_test_start,
-		.cable_test_get_status	= qca807x_cable_test_get_status,
-	},
-	{
-		PHY_ID_MATCH_EXACT(PHY_ID_QCA8075),
-		.name           = "Qualcomm QCA8075",
-		.flags		= PHY_POLL_CABLE_TEST,
-		/* PHY_GBIT_FEATURES */
-		.probe		= qca807x_probe,
-		.config_init	= qca807x_config,
-		.read_status	= qca807x_read_status,
-		.config_intr	= qca807x_config_intr,
-		.handle_interrupt = qca807x_handle_interrupt,
-		.soft_reset	= genphy_soft_reset,
-		.get_tunable	= qca807x_get_tunable,
-		.set_tunable	= qca807x_set_tunable,
-		.resume		= genphy_resume,
-		.suspend	= genphy_suspend,
-		.cable_test_start	= qca807x_cable_test_start,
-		.cable_test_get_status	= qca807x_cable_test_get_status,
-	},
-	{
-		PHY_ID_MATCH_EXACT(PHY_ID_QCA807X_PSGMII),
-		.name           = "Qualcomm QCA807x PSGMII",
-		.probe		= qca807x_psgmii_config,
-	},
-};
-module_phy_driver(qca807x_drivers);
-
-static struct mdio_device_id __maybe_unused qca807x_tbl[] = {
-	{ PHY_ID_MATCH_EXACT(PHY_ID_QCA8072) },
-	{ PHY_ID_MATCH_EXACT(PHY_ID_QCA8075) },
-	{ PHY_ID_MATCH_MODEL(PHY_ID_QCA807X_PSGMII) },
-	{ }
-};
-
-MODULE_AUTHOR("Robert Marko");
-MODULE_DESCRIPTION("Qualcomm QCA807x PHY driver");
-MODULE_DEVICE_TABLE(mdio, qca807x_tbl);
-MODULE_LICENSE("GPL");
diff --git a/target/linux/ipq40xx/image/generic.mk b/target/linux/ipq40xx/image/generic.mk
index f5132cb91fd350..8a83e27f543c64 100644
--- a/target/linux/ipq40xx/image/generic.mk
+++ b/target/linux/ipq40xx/image/generic.mk
@@ -841,6 +841,25 @@ define Device/netgear_orbi
 	DEVICE_PACKAGES := ath10k-firmware-qca9984-ct e2fsprogs kmod-fs-ext4 losetup
 endef
 
+define Device/netgear_lbr20
+	$(call Device/netgear_orbi)
+	DEVICE_MODEL := LBR20
+	NETGEAR_BOARD_ID := LBR20
+	NETGEAR_HW_ID := 29766182+0+256+512+2x2+2x2+2x2+1
+	KERNEL_SIZE := 7340032
+	BLOCKSIZE := 128k
+	PAGESIZE := 2048
+	UBINIZE_OPTS := -E 5
+	IMAGE/factory.img := append-kernel | pad-offset $$$$(BLOCKSIZE) 64 | \
+		append-uImage-fakehdr filesystem | pad-to $$$$(KERNEL_SIZE) | \
+		append-ubi | netgear-dni
+	IMAGE/sysupgrade.bin := append-kernel | pad-offset $$$$(BLOCKSIZE) 64 | \
+		append-uImage-fakehdr filesystem | sysupgrade-tar kernel=$$$$@ | \
+		append-metadata
+	DEVICE_PACKAGES := ipq-wifi-netgear_lbr20 ath10k-firmware-qca9888-ct kmod-usb-net-qmi-wwan kmod-usb-serial-option uqmi
+endef
+TARGET_DEVICES += netgear_lbr20
+
 define Device/netgear_rbx40
 	$(call Device/netgear_orbi)
 	NETGEAR_HW_ID := 29765515+0+4096+512+2x2+2x2+2x2
diff --git a/target/linux/ipq40xx/patches-6.1/700-net-ipqess-introduce-the-Qualcomm-IPQESS-driver.patch b/target/linux/ipq40xx/patches-6.1/700-net-ipqess-introduce-the-Qualcomm-IPQESS-driver.patch
index a3d8bf0488699b..4b1a43259feb7a 100644
--- a/target/linux/ipq40xx/patches-6.1/700-net-ipqess-introduce-the-Qualcomm-IPQESS-driver.patch
+++ b/target/linux/ipq40xx/patches-6.1/700-net-ipqess-introduce-the-Qualcomm-IPQESS-driver.patch
@@ -32,7 +32,7 @@ Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
 
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
-@@ -17066,6 +17066,13 @@ L:	netdev@vger.kernel.org
+@@ -17068,6 +17068,13 @@ L:	netdev@vger.kernel.org
  S:	Maintained
  F:	drivers/net/ethernet/qualcomm/emac/
  
diff --git a/target/linux/ipq40xx/patches-6.1/701-net-dsa-add-out-of-band-tagging-protocol.patch b/target/linux/ipq40xx/patches-6.1/701-net-dsa-add-out-of-band-tagging-protocol.patch
index 7961c9978b466d..ab01e6704a0001 100644
--- a/target/linux/ipq40xx/patches-6.1/701-net-dsa-add-out-of-band-tagging-protocol.patch
+++ b/target/linux/ipq40xx/patches-6.1/701-net-dsa-add-out-of-band-tagging-protocol.patch
@@ -64,7 +64,7 @@ Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
  
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
-@@ -17072,6 +17072,7 @@ L:	netdev@vger.kernel.org
+@@ -17074,6 +17074,7 @@ L:	netdev@vger.kernel.org
  S:	Maintained
  F:	Documentation/devicetree/bindings/net/qcom,ipq4019-ess-edma.yaml
  F:	drivers/net/ethernet/qualcomm/ipqess/
@@ -136,7 +136,7 @@ Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
  #include <net/dst.h>
  #include <net/sock.h>
  #include <net/checksum.h>
-@@ -4516,6 +4520,9 @@ static const u8 skb_ext_type_len[] = {
+@@ -4517,6 +4521,9 @@ static const u8 skb_ext_type_len[] = {
  #if IS_ENABLED(CONFIG_MCTP_FLOWS)
  	[SKB_EXT_MCTP] = SKB_EXT_CHUNKSIZEOF(struct mctp_flow),
  #endif
@@ -146,7 +146,7 @@ Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
  };
  
  static __always_inline unsigned int skb_ext_total_length(void)
-@@ -4536,6 +4543,9 @@ static __always_inline unsigned int skb_
+@@ -4537,6 +4544,9 @@ static __always_inline unsigned int skb_
  #if IS_ENABLED(CONFIG_MCTP_FLOWS)
  		skb_ext_type_len[SKB_EXT_MCTP] +
  #endif
diff --git a/target/linux/ipq40xx/patches-6.1/708-dt-bindings-net-add-QCA807x-PHY.patch b/target/linux/ipq40xx/patches-6.1/708-dt-bindings-net-add-QCA807x-PHY.patch
deleted file mode 100644
index b325d9e535d379..00000000000000
--- a/target/linux/ipq40xx/patches-6.1/708-dt-bindings-net-add-QCA807x-PHY.patch
+++ /dev/null
@@ -1,61 +0,0 @@
-From 96eb388c082bd0086b128d82def9daaab1617951 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robert.marko@sartura.hr>
-Date: Thu, 1 Oct 2020 15:05:35 +0200
-Subject: [PATCH] dt-bindings: net: add QCA807x PHY
-
-Add DT bindings for Qualcomm QCA807x PHY series.
-
-Signed-off-by: Robert Marko <robert.marko@sartura.hr>
----
- include/dt-bindings/net/qcom-qca807x.h | 45 ++++++++++++++++++++++++++
- 1 file changed, 45 insertions(+)
- create mode 100644 include/dt-bindings/net/qcom-qca807x.h
-
---- /dev/null
-+++ b/include/dt-bindings/net/qcom-qca807x.h
-@@ -0,0 +1,45 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+/*
-+ * Device Tree constants for the Qualcomm QCA807X PHYs
-+ */
-+
-+#ifndef _DT_BINDINGS_QCOM_QCA807X_H
-+#define _DT_BINDINGS_QCOM_QCA807X_H
-+
-+#define PSGMII_QSGMII_TX_DRIVER_140MV	0
-+#define PSGMII_QSGMII_TX_DRIVER_160MV	1
-+#define PSGMII_QSGMII_TX_DRIVER_180MV	2
-+#define PSGMII_QSGMII_TX_DRIVER_200MV	3
-+#define PSGMII_QSGMII_TX_DRIVER_220MV	4
-+#define PSGMII_QSGMII_TX_DRIVER_240MV	5
-+#define PSGMII_QSGMII_TX_DRIVER_260MV	6
-+#define PSGMII_QSGMII_TX_DRIVER_280MV	7
-+#define PSGMII_QSGMII_TX_DRIVER_300MV	8
-+#define PSGMII_QSGMII_TX_DRIVER_320MV	9
-+#define PSGMII_QSGMII_TX_DRIVER_400MV	10
-+#define PSGMII_QSGMII_TX_DRIVER_500MV	11
-+/* Default value */
-+#define PSGMII_QSGMII_TX_DRIVER_600MV	12
-+
-+/* Full amplitude, full bias current */
-+#define QCA807X_CONTROL_DAC_FULL_VOLT_BIAS		0
-+/* Amplitude follow DSP (amplitude is adjusted based on cable length), half bias current */
-+#define QCA807X_CONTROL_DAC_DSP_VOLT_HALF_BIAS		1
-+/* Full amplitude, bias current follow DSP (bias current is adjusted based on cable length) */
-+#define QCA807X_CONTROL_DAC_FULL_VOLT_DSP_BIAS		2
-+/* Both amplitude and bias current follow DSP */
-+#define QCA807X_CONTROL_DAC_DSP_VOLT_BIAS		3
-+/* Full amplitude, half bias current */
-+#define QCA807X_CONTROL_DAC_FULL_VOLT_HALF_BIAS		4
-+/* Amplitude follow DSP setting; 1/4 bias current when cable<10m,
-+ * otherwise half bias current
-+ */
-+#define QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS	5
-+/* Full amplitude; same bias current setting with “010” and “011”,
-+ * but half more bias is reduced when cable <10m
-+ */
-+#define QCA807X_CONTROL_DAC_FULL_VOLT_HALF_BIAS_SHORT	6
-+/* Amplitude follow DSP; same bias current setting with “110”, default value */
-+#define QCA807X_CONTROL_DAC_DSP_VOLT_HALF_BIAS_SHORT	7
-+
-+#endif
diff --git a/target/linux/ipq40xx/patches-6.1/709-ARM-dts-qcom-ipq4019-add-QCA8075-PHY-Package-nodes.patch b/target/linux/ipq40xx/patches-6.1/709-ARM-dts-qcom-ipq4019-add-QCA8075-PHY-Package-nodes.patch
new file mode 100644
index 00000000000000..e8b89647cebccc
--- /dev/null
+++ b/target/linux/ipq40xx/patches-6.1/709-ARM-dts-qcom-ipq4019-add-QCA8075-PHY-Package-nodes.patch
@@ -0,0 +1,67 @@
+From 5ac078c8fe18f3e8318547b8ed0ed782730c5039 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Sat, 10 Feb 2024 22:28:27 +0100
+Subject: [PATCH] ARM: dts: qcom: ipq4019: add QCA8075 PHY Package nodes
+
+Add QCA8075 PHY Package nodes. The PHY nodes that were previously
+defined never worked and actually never had a driver to correctly setup
+these PHY. Now that we have a correct driver, correctly add the PHY
+Package node and set the default value of 300mw for tx driver strength
+following specification of ipq4019 SoC.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ arch/arm/boot/dts//qcom-ipq4019.dtsi | 35 +++++++++++++++---------
+ 1 file changed, 22 insertions(+), 13 deletions(-)
+
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -725,24 +725,33 @@
+ 			reg = <0x90000 0x64>;
+ 			status = "disabled";
+ 
+-			ethphy0: ethernet-phy@0 {
++			ethernet-phy-package@0 {
++				#address-cells = <1>;
++				#size-cells = <0>;
++				compatible = "qcom,qca8075-package";
+ 				reg = <0>;
+-			};
+-
+-			ethphy1: ethernet-phy@1 {
+-				reg = <1>;
+-			};
+ 
+-			ethphy2: ethernet-phy@2 {
+-				reg = <2>;
+-			};
+-
+-			ethphy3: ethernet-phy@3 {
+-				reg = <3>;
+-			};
++				qcom,tx-drive-strength-milliwatt = <300>;
+ 
+-			ethphy4: ethernet-phy@4 {
+-				reg = <4>;
++				ethphy0: ethernet-phy@0 {
++					reg = <0>;
++				};
++
++				ethphy1: ethernet-phy@1 {
++					reg = <1>;
++				};
++
++				ethphy2: ethernet-phy@2 {
++					reg = <2>;
++				};
++
++				ethphy3: ethernet-phy@3 {
++					reg = <3>;
++				};
++
++				ethphy4: ethernet-phy@4 {
++					reg = <4>;
++				};
+ 			};
+ 		};
+ 
diff --git a/target/linux/ipq40xx/patches-6.1/709-net-phy-Add-Qualcom-QCA807x-driver.patch b/target/linux/ipq40xx/patches-6.1/709-net-phy-Add-Qualcom-QCA807x-driver.patch
deleted file mode 100644
index dbf87d4ddebcd7..00000000000000
--- a/target/linux/ipq40xx/patches-6.1/709-net-phy-Add-Qualcom-QCA807x-driver.patch
+++ /dev/null
@@ -1,51 +0,0 @@
-From 876bb5b69c1e083be526c0ea261982d5eb78556f Mon Sep 17 00:00:00 2001
-From: Robert Marko <robert.marko@sartura.hr>
-Date: Fri, 9 Sep 2022 23:44:42 +0200
-Subject: [PATCH] net: phy: Add Qualcom QCA807x driver
-
-This adds driver for the Qualcomm QCA8072 and QCA8075 PHY-s.
-
-They are 2 or 5 port IEEE 802.3 clause 22 compliant 10BASE-Te, 100BASE-TX and 1000BASE-T PHY-s.
-
-They feature 2 SerDes, one for PSGMII or QSGMII connection with MAC, while second one is SGMII for connection to MAC or fiber.
-
-Both models have a combo port that supports 1000BASE-X and 100BASE-FX fiber.
-
-Each PHY inside of QCA807x series has 4 digitally controlled output only pins that natively drive LED-s.
-But some vendors used these to driver generic LED-s controlled by userspace,
-so lets enable registering each PHY as GPIO controller and add driver for it.
-
-These are commonly used in Qualcomm IPQ40xx, IPQ60xx and IPQ807x boards.
-
-Signed-off-by: Robert Marko <robert.marko@sartura.hr>
----
- drivers/net/phy/Kconfig  | 7 +++++++
- drivers/net/phy/Makefile | 1 +
- 2 files changed, 8 insertions(+)
-
---- a/drivers/net/phy/Kconfig
-+++ b/drivers/net/phy/Kconfig
-@@ -366,6 +366,13 @@ config AT803X_PHY
- 	  Currently supports the AR8030, AR8031, AR8033, AR8035 and internal
- 	  QCA8337(Internal qca8k PHY) model
- 
-+config QCA807X_PHY
-+	tristate "Qualcomm QCA807x PHYs"
-+	depends on OF_MDIO
-+	help
-+	  Currently supports the Qualcomm QCA8072, QCA8075 and the PSGMII
-+	  control PHY.
-+
- config QSEMI_PHY
- 	tristate "Quality Semiconductor PHYs"
- 	help
---- a/drivers/net/phy/Makefile
-+++ b/drivers/net/phy/Makefile
-@@ -90,6 +90,7 @@ obj-$(CONFIG_MOTORCOMM_PHY)	+= motorcomm
- obj-$(CONFIG_NATIONAL_PHY)	+= national.o
- obj-$(CONFIG_NXP_C45_TJA11XX_PHY)	+= nxp-c45-tja11xx.o
- obj-$(CONFIG_NXP_TJA11XX_PHY)	+= nxp-tja11xx.o
-+obj-$(CONFIG_QCA807X_PHY)		+= qca807x.o
- obj-$(CONFIG_QSEMI_PHY)		+= qsemi.o
- obj-$(CONFIG_REALTEK_PHY)	+= realtek.o
- obj-$(CONFIG_RENESAS_PHY)	+= uPD60620.o
diff --git a/target/linux/ipq40xx/patches-6.1/710-arm-dts-ipq4019-QCA807x-properties.patch b/target/linux/ipq40xx/patches-6.1/710-arm-dts-ipq4019-QCA807x-properties.patch
index 92fb8a6a02271b..a9ba70ff2f71fb 100644
--- a/target/linux/ipq40xx/patches-6.1/710-arm-dts-ipq4019-QCA807x-properties.patch
+++ b/target/linux/ipq40xx/patches-6.1/710-arm-dts-ipq4019-QCA807x-properties.patch
@@ -12,50 +12,14 @@ Signed-off-by: Robert Marko <robert.marko@sartura.hr>
 
 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
 +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -8,6 +8,7 @@
- #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/interrupt-controller/irq.h>
-+#include <dt-bindings/net/qcom-qca807x.h>
- 
- / {
- 	#address-cells = <1>;
-@@ -727,22 +728,38 @@
- 
- 			ethphy0: ethernet-phy@0 {
- 				reg = <0>;
-+
-+				qcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;
- 			};
- 
- 			ethphy1: ethernet-phy@1 {
- 				reg = <1>;
-+
-+				qcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;
- 			};
- 
- 			ethphy2: ethernet-phy@2 {
- 				reg = <2>;
-+
-+				qcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;
- 			};
- 
- 			ethphy3: ethernet-phy@3 {
- 				reg = <3>;
-+
-+				qcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;
- 			};
- 
- 			ethphy4: ethernet-phy@4 {
- 				reg = <4>;
-+
-+				qcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;
-+			};
-+
-+			psgmiiphy: psgmii-phy@5 {
-+				reg = <5>;
+@@ -752,6 +752,10 @@
+ 				ethphy4: ethernet-phy@4 {
+ 					reg = <4>;
+ 				};
 +
-+				qcom,tx-driver-strength = <PSGMII_QSGMII_TX_DRIVER_300MV>;
++				psgmiiphy: psgmii-phy@5 {
++					reg = <5>;
++				};
  			};
  		};
  
diff --git a/target/linux/ipq806x/config-6.1 b/target/linux/ipq806x/config-6.1
index e31e8223800d11..18325c03466eae 100644
--- a/target/linux/ipq806x/config-6.1
+++ b/target/linux/ipq806x/config-6.1
@@ -4,7 +4,6 @@ CONFIG_ALIGNMENT_TRAP=y
 CONFIG_ARCH_32BIT_OFF_T=y
 CONFIG_ARCH_HIBERNATION_POSSIBLE=y
 # CONFIG_ARCH_IPQ40XX is not set
-CONFIG_ARCH_IPQ806X=y
 CONFIG_ARCH_KEEP_MEMBLOCK=y
 # CONFIG_ARCH_MDM9615 is not set
 CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
@@ -31,6 +30,7 @@ CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
 CONFIG_ARM_ATAG_DTB_COMPAT=y
 # CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set
 CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE=y
+CONFIG_ARM_ATAG_DTB_COMPAT_IGNORE_MEM=y
 CONFIG_ARM_CPUIDLE=y
 CONFIG_ARM_CPU_SUSPEND=y
 # CONFIG_ARM_CPU_TOPOLOGY is not set
@@ -49,7 +49,7 @@ CONFIG_ARM_QCOM_SPM_CPUIDLE=y
 CONFIG_ARM_THUMB=y
 CONFIG_ARM_UNWIND=y
 CONFIG_ARM_VIRT_EXT=y
-CONFIG_AT803X_PHY=y
+CONFIG_AUTO_ZRELADDR=y
 CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_MQ_PCI=y
@@ -148,7 +148,6 @@ CONFIG_DWMAC_IPQ806X=y
 # CONFIG_DWMAC_QCOM_ETHQOS is not set
 CONFIG_EDAC_ATOMIC_SCRUB=y
 CONFIG_EDAC_SUPPORT=y
-CONFIG_ETHERNET_PACKET_MANGLE=y
 CONFIG_EXCLUSIVE_SYSTEM_RAM=y
 CONFIG_FIXED_PHY=y
 CONFIG_FIX_EARLYCON_MEM=y
@@ -314,6 +313,7 @@ CONFIG_NO_HZ_COMMON=y
 CONFIG_NO_HZ_IDLE=y
 CONFIG_NR_CPUS=2
 CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
 CONFIG_NVMEM_QCOM_QFPROM=y
 # CONFIG_NVMEM_QCOM_SEC_QFPROM is not set
 # CONFIG_NVMEM_SPMI_SDAM is not set
@@ -334,6 +334,7 @@ CONFIG_PAGE_OFFSET=0xC0000000
 CONFIG_PAGE_POOL=y
 CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
 CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
 CONFIG_PCI=y
 CONFIG_PCIEAER=y
 CONFIG_PCIEPORTBUS=y
@@ -350,8 +351,8 @@ CONFIG_PCS_XPCS=y
 CONFIG_PERF_USE_VMALLOC=y
 CONFIG_PGTABLE_LEVELS=2
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
 CONFIG_PHYLINK=y
-CONFIG_PHYS_OFFSET=0x42000000
 # CONFIG_PHY_QCOM_APQ8064_SATA is not set
 # CONFIG_PHY_QCOM_EDP is not set
 # CONFIG_PHY_QCOM_IPQ4019_USB is not set
@@ -389,6 +390,7 @@ CONFIG_PREEMPT_NONE_BUILD=y
 CONFIG_PRINTK_TIME=y
 CONFIG_PTP_1588_CLOCK=y
 CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_QCA83XX_PHY=y
 # CONFIG_QCM_DISPCC_2290 is not set
 # CONFIG_QCM_GCC_2290 is not set
 # CONFIG_QCOM_A53PLL is not set
@@ -404,6 +406,7 @@ CONFIG_QCOM_HFPLL=y
 # CONFIG_QCOM_ICC_BWMON is not set
 # CONFIG_QCOM_IOMMU is not set
 # CONFIG_QCOM_LLCC is not set
+CONFIG_QCOM_NET_PHYLIB=y
 # CONFIG_QCOM_OCMEM is not set
 # CONFIG_QCOM_PDC is not set
 # CONFIG_QCOM_RMTFS_MEM is not set
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8062-wg2600hp3.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8062-wg2600hp3.dts
index 0c669dcbfe62c7..76751910e01c4d 100644
--- a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8062-wg2600hp3.dts
+++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8062-wg2600hp3.dts
@@ -70,12 +70,14 @@
 		pinctrl-names = "default";
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&qcom_pinmux 14 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_power_red: power_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&qcom_pinmux 35 GPIO_ACTIVE_HIGH>;
 		};
 
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ad7200.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ad7200.dts
index f76e098d9e6188..6e4c9bc773c85f 100644
--- a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ad7200.dts
+++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ad7200.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qcom-ipq8064-ad7200-c2600.dtsi"
 
 / {
@@ -57,7 +59,8 @@
 		pinctrl-names = "default";
 
 		lan {
-			label = "blue:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&qcom_pinmux 2 GPIO_ACTIVE_HIGH>;
 		};
 
@@ -82,17 +85,20 @@
 		};
 
 		wan_orange {
-			label = "orange:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>;
 		};
 
 		wan_blue {
-			label = "blue:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&qcom_pinmux 33 GPIO_ACTIVE_LOW>;
 		};
 
 		wps {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>;
 		};
 
@@ -102,7 +108,8 @@
 		};
 
 		led_status: status {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&qcom_pinmux 66 GPIO_ACTIVE_HIGH>;
 		};
 	};
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-c2600.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-c2600.dts
index cef1aba34445d3..b8cb25ede0c6ff 100644
--- a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-c2600.dts
+++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-c2600.dts
@@ -1,3 +1,5 @@
+#include <dt-bindings/leds/common.h>
+
 #include "qcom-ipq8064-ad7200-c2600.dtsi"
 
 / {
@@ -55,7 +57,8 @@
 		pinctrl-names = "default";
 
 		lan {
-			label = "white:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&qcom_pinmux 6 GPIO_ACTIVE_HIGH>;
 		};
 
@@ -70,22 +73,26 @@
 		};
 
 		wps {
-			label = "white:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
 		};
 
 		wan_amber {
-			label = "amber:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>;
 		};
 
 		wan_white {
-			label = "white:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&qcom_pinmux 33 GPIO_ACTIVE_LOW>;
 		};
 
 		power: power {
-			label = "white:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
 			default-state = "keep";
 		};
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-d7800.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-d7800.dts
index 3cd1bd20452904..8077c3a0901242 100644
--- a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-d7800.dts
+++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-d7800.dts
@@ -1,6 +1,7 @@
 #include "qcom-ipq8064-v2.0-smb208.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Netgear Nighthawk X4 D7800";
@@ -77,22 +78,26 @@
 		};
 
 		power_amber: power_amber {
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
 		};
 
 		wan_white {
-			label = "white:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
 		};
 
 		wan_amber {
-			label = "amber:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
 		};
 
 		wps {
-			label = "white:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
 		};
 
@@ -102,7 +107,8 @@
 		};
 
 		power_white: power_white {
-			label = "white:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
 			default-state = "keep";
 		};
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ea7500-v1.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ea7500-v1.dts
index aab44ea9e3188c..2a565cc2db25a6 100644
--- a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ea7500-v1.dts
+++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ea7500-v1.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "qcom-ipq8064-eax500.dtsi"
 
 / {
@@ -51,7 +53,8 @@
 		pinctrl-names = "default";
 
 		led_power: power {
-			label = "white:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
 			default-state = "keep";
 		};
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts
index bc3a2c304964d6..d9155081a583d9 100644
--- a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts
+++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts
@@ -1,3 +1,5 @@
+#include <dt-bindings/leds/common.h>
+
 #include "qcom-ipq8064-eax500.dtsi"
 
 / {
@@ -54,12 +56,14 @@
 		pinctrl-names = "default";
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_power: power {
-			label = "white:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
 			default-state = "keep";
 		};
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-fap-421e.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-fap-421e.dts
index 1902a2f996e45f..bb66c6c8083166 100644
--- a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-fap-421e.dts
+++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-fap-421e.dts
@@ -80,7 +80,8 @@
 		};
 
 		led_power_yellow: power-yellow {
-			label = "yellow:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_YELLOW>;
 			gpios = <&qcom_pinmux 58 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-g10.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-g10.dts
index efcb6ec2411093..24273291cb1e49 100644
--- a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-g10.dts
+++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-g10.dts
@@ -2,6 +2,7 @@
 #include "qcom-ipq8064-v2.0-smb208.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/soc/qcom,tcsr.h>
 
 / {
@@ -34,17 +35,20 @@
 		 */
 
 		status_yellow {
-			label = "yellow:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_YELLOW>;
 			gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_status_amber: status_amber {
-			label = "amber:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_status_blue: status_blue {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
 		};
 
@@ -54,7 +58,8 @@
 		 * about the LED being white.
 
 		status_white {
-			label = "white:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
 		};
 		*/
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-r7500.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-r7500.dts
index 41360b4a55b596..c2703b05d7860b 100644
--- a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-r7500.dts
+++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-r7500.dts
@@ -1,6 +1,7 @@
 #include "qcom-ipq8064-v1.0.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/soc/qcom,tcsr.h>
 
 / {
@@ -81,22 +82,26 @@
 		};
 
 		power_amber: power_amber {
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
 		};
 
 		wan_white {
-			label = "white:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
 		};
 
 		wan_amber {
-			label = "amber:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
 		};
 
 		wps {
-			label = "white:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
 		};
 
@@ -106,7 +111,8 @@
 		};
 
 		power_white: power_white {
-			label = "white:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
 			default-state = "keep";
 		};
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts
index 88c0daab40491a..6c52d51ebc17e9 100644
--- a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts
+++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts
@@ -1,6 +1,7 @@
 #include "qcom-ipq8064-v2.0-smb208.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Netgear Nighthawk X4 R7500v2";
@@ -77,7 +78,8 @@
 		};
 
 		status {
-			label = "amber:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
 		};
 
@@ -87,12 +89,14 @@
 		};
 
 		wan {
-			label = "white:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
 		};
 
 		wps {
-			label = "white:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
 		};
 
@@ -102,7 +106,8 @@
 		};
 
 		power: power {
-			label = "white:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
 			default-state = "keep";
 		};
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts
index ac62470df48241..62530efeb1f2b0 100644
--- a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts
+++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts
@@ -1,6 +1,7 @@
 #include "qcom-ipq8064-v2.0-smb208.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "TP-Link Archer VR2600v";
@@ -77,12 +78,14 @@
 		};
 
 		usb {
-			label = "white:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
 		};
 
 		lan {
-			label = "white:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
 		};
 
@@ -97,7 +100,8 @@
 		};
 
 		power: power {
-			label = "white:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
 			default-state = "keep";
 		};
@@ -108,7 +112,8 @@
 		};
 
 		wan {
-			label = "white:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>;
 		};
 
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts
index a376eb0e2fe925..0afc9219c9cf24 100644
--- a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts
+++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts
@@ -1,6 +1,7 @@
 #include "qcom-ipq8064-v2.0-smb208.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "NEC Aterm WG2600HP";
@@ -71,7 +72,8 @@
 		};
 
 		power_red: power_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
 		};
 
@@ -86,7 +88,8 @@
 		};
 
 		power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&qcom_pinmux 14 GPIO_ACTIVE_HIGH>;
 		};
 
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-wpq864.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-wpq864.dts
index f8b20b0635f2c1..0fb7e0531d5230 100644
--- a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-wpq864.dts
+++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-wpq864.dts
@@ -8,6 +8,7 @@
 #include "qcom-ipq8064-v1.0.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/soc/qcom,tcsr.h>
 
 / {
@@ -63,7 +64,8 @@
 		};
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
 		};
 
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts
index d484ba9c6036d0..58074258306f3f 100644
--- a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts
+++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts
@@ -2,6 +2,7 @@
 #include "qcom-ipq8064-v2.0-smb208.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Buffalo WXR-2533DHP";
@@ -30,7 +31,8 @@
 		pinctrl-names = "default";
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "usbport";
 			trigger-sources = <&hub_port0 &hub_port1>;
@@ -77,7 +79,8 @@
 		};
 
 		power: power {
-			label = "white:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
 		};
 	};
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts
index db5acd47d7499b..7d22b4f5415554 100644
--- a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts
+++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts
@@ -1,6 +1,7 @@
 #include "qcom-ipq8065-smb208.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "ZyXEL NBG6817";
@@ -68,7 +69,8 @@
 		};
 
 		power: power {
-			label = "white:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
 			default-state = "keep";
 		};
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-nighthawk.dtsi b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-nighthawk.dtsi
index 902df23501e72c..a7f0b1dbf03423 100644
--- a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-nighthawk.dtsi
+++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-nighthawk.dtsi
@@ -1,6 +1,7 @@
 #include "qcom-ipq8065-smb208.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	memory@0 {
@@ -71,23 +72,27 @@
 		pinctrl-names = "default";
 
 		power_white: power_white {
-			label = "white:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
 			default-state = "keep";
 		};
 
 		power_amber: power_amber {
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
 		};
 
 		wan_white {
-			label = "white:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
 		};
 
 		wan_amber {
-			label = "amber:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
 		};
 
@@ -97,7 +102,8 @@
 		};
 
 		wps {
-			label = "white:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
 		};
 	};
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts
index 0e63ddaa7aae7e..8818e95e8d1b3b 100644
--- a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts
+++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts
@@ -2,6 +2,7 @@
 
 #include "qcom-ipq8065-smb208.dtsi"
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Arris TR4400 v2";
@@ -51,12 +52,14 @@
 		pinctrl-names = "default";
 
 		led_status_red: status_red {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_status_blue: status_blue {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
 		};
 	};
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-ap3935.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-ap3935.dts
index 6d473d43ab12aa..0c865ef7c7cf1f 100644
--- a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-ap3935.dts
+++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-ap3935.dts
@@ -3,6 +3,7 @@
 #include "qcom-ipq8064-v2.0.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/soc/qcom,tcsr.h>
 
 / {
@@ -52,12 +53,14 @@
 		pinctrl-names = "default";
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&qcom_pinmux 22 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_orange: power_orange { 
-			label = "orange:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&qcom_pinmux 23 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-ecw5410.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-ecw5410.dts
index 50c1d37c29287e..9f6c5fb6969784 100644
--- a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-ecw5410.dts
+++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-ecw5410.dts
@@ -1,6 +1,7 @@
 #include "qcom-ipq8064-v2.0-smb208.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/soc/qcom,tcsr.h>
 
 / {
@@ -67,7 +68,8 @@
 		pinctrl-names = "default";
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>;
 		};
 
@@ -87,7 +89,8 @@
 		};
 
 		led_power_red: power_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&qcom_pinmux 28 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-mr42.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-mr42.dts
index d9d284fcfaf913..7ec11de56b637c 100644
--- a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-mr42.dts
+++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-mr42.dts
@@ -3,6 +3,7 @@
 #include "qcom-ipq8068-cryptid-common.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Meraki MR42";
@@ -38,7 +39,8 @@
 		pinctrl-names = "default";
 
 		led_power: power {
-			label = "orange:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&qcom_pinmux 31 GPIO_ACTIVE_HIGH>;
 		};
 
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-mr52.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-mr52.dts
index 522fa12fd977aa..7512bfb74f1c2d 100644
--- a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-mr52.dts
+++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-mr52.dts
@@ -3,6 +3,7 @@
 #include "qcom-ipq8068-cryptid-common.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Meraki MR52";
@@ -40,7 +41,8 @@
 		pinctrl-names = "default";
 
 		led_power: power {
-			label = "orange:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&qcom_pinmux 19 GPIO_ACTIVE_HIGH>;
 		};
 
diff --git a/target/linux/ipq806x/patches-6.1/0060-ARM-mach-qcom-fix-support-for-ipq806x.patch b/target/linux/ipq806x/patches-6.1/0060-ARM-mach-qcom-fix-support-for-ipq806x.patch
deleted file mode 100644
index 47053260bb5d39..00000000000000
--- a/target/linux/ipq806x/patches-6.1/0060-ARM-mach-qcom-fix-support-for-ipq806x.patch
+++ /dev/null
@@ -1,60 +0,0 @@
-From 9c896e9fc2ef1209e4a56d8c9fdd183847c2c814 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Tue, 18 Oct 2022 22:02:46 +0200
-Subject: [PATCH] ARM: mach-qcom: fix support for ipq806x
-
-Add a specific config flag for Qcom IPQ806x as this SoC can't use
-AUTO_ZRELADDR and require the PHYS_OFFSET set to 0x42000000.
-
-This is needed as some legacy board (or some wrongly configured
-bootloader) pass the wrong memory map and doesn't exclude the first
-~20MB of RAM reserved for the hardware network accellerators.
-
-With this change we can correctly support each board and prevent any
-kind of misconfiguration done by the OEM.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- arch/arm/Kconfig           |  3 ++-
- arch/arm/mach-qcom/Kconfig | 13 +++++++++++++
- 2 files changed, 15 insertions(+), 1 deletion(-)
-
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -285,6 +285,7 @@ config PHYS_OFFSET
- 	default 0x30000000 if ARCH_S3C24XX
- 	default 0xa0000000 if ARCH_IOP32X || ARCH_PXA
- 	default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100
-+	default 0x42000000 if ARCH_IPQ806X
- 	default 0
- 	help
- 	  Please provide the physical address corresponding to the
-@@ -1704,7 +1705,7 @@ config CRASH_DUMP
- 
- config AUTO_ZRELADDR
- 	bool "Auto calculation of the decompressed kernel image address" if !ARCH_MULTIPLATFORM
--	default !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100)
-+	default !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100 || ARCH_IPQ806X)
- 	help
- 	  ZRELADDR is the physical address where the decompressed kernel
- 	  image will be placed. If AUTO_ZRELADDR is selected, the address
---- a/arch/arm/mach-qcom/Kconfig
-+++ b/arch/arm/mach-qcom/Kconfig
-@@ -46,4 +46,17 @@ config ARCH_MDM9615
- 	bool "Enable support for MDM9615"
- 	select CLKSRC_QCOM
- 
-+config ARCH_IPQ806X
-+	bool "Enable support for IPQ806x"
-+	help
-+	  Enable support for the Qualcomm IPQ806x.
-+
-+	  IPQ806x require special PHYS_OFFSET and can't use AUTO_ZRELADDR.
-+	  The first ~20MB of RAM is reserved for the hardware network accelerators,
-+	  and the bootloader removes this section from the layout passed from the
-+	  ATAGS (when used by some bootloader doesn't even do that).
-+
-+	  To support every system and handle legacy systems, hardcode PHYS_OFFSET and
-+	  disable AUTO_ZRELADDR.
-+
- endif
diff --git a/target/linux/ipq806x/patches-6.1/0067-generic-Mangle-bootloader-s-kernel-arguments.patch b/target/linux/ipq806x/patches-6.1/0067-generic-Mangle-bootloader-s-kernel-arguments.patch
deleted file mode 100644
index 4e47c390a2393b..00000000000000
--- a/target/linux/ipq806x/patches-6.1/0067-generic-Mangle-bootloader-s-kernel-arguments.patch
+++ /dev/null
@@ -1,280 +0,0 @@
-From 71270226b14733a4b1f2cde58ea9265caa50b38d Mon Sep 17 00:00:00 2001
-From: Adrian Panella <ianchi74@outlook.com>
-Date: Thu, 9 Mar 2017 09:37:17 +0100
-Subject: [PATCH 67/69] generic: Mangle bootloader's kernel arguments
-
-The command-line arguments provided by the boot loader will be
-appended to a new device tree property: bootloader-args.
-If there is a property "append-rootblock" in DT under /chosen
-and a root= option in bootloaders command line it will be parsed
-and added to DT bootargs with the form: <append-rootblock>XX.
-Only command line ATAG will be processed, the rest of the ATAGs
-sent by bootloader will be ignored.
-This is usefull in dual boot systems, to get the current root partition
-without afecting the rest of the system.
-
-Signed-off-by: Adrian Panella <ianchi74@outlook.com>
----
- arch/arm/Kconfig                        | 11 +++++
- arch/arm/boot/compressed/atags_to_fdt.c | 72 ++++++++++++++++++++++++++++++++-
- init/main.c                             | 16 ++++++++
- 3 files changed, 98 insertions(+), 1 deletion(-)
-
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -1588,6 +1588,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
- 	  The command-line arguments provided by the boot loader will be
- 	  appended to the the device tree bootargs property.
- 
-+config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
-+	bool "Append rootblock parsing bootloader's kernel arguments"
-+	help
-+	  The command-line arguments provided by the boot loader will be
-+	  appended to a new device tree property: bootloader-args.
-+	  If there is a property "append-rootblock" in DT under /chosen
-+	  and a root= option in bootloaders command line it will be parsed
-+	  and added to DT bootargs with the form: <append-rootblock>XX.
-+	  Only command line ATAG will be processed, the rest of the ATAGs
-+	  sent by bootloader will be ignored.
-+
- endchoice
- 
- config CMDLINE
---- a/arch/arm/boot/compressed/atags_to_fdt.c
-+++ b/arch/arm/boot/compressed/atags_to_fdt.c
-@@ -5,6 +5,8 @@
- 
- #if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND)
- #define do_extend_cmdline 1
-+#elif defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
-+#define do_extend_cmdline 1
- #else
- #define do_extend_cmdline 0
- #endif
-@@ -20,6 +22,7 @@ static int node_offset(void *fdt, const
- 	return offset;
- }
- 
-+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
- static int setprop(void *fdt, const char *node_path, const char *property,
- 		   void *val_array, int size)
- {
-@@ -28,6 +31,7 @@ static int setprop(void *fdt, const char
- 		return offset;
- 	return fdt_setprop(fdt, offset, property, val_array, size);
- }
-+#endif
- 
- static int setprop_string(void *fdt, const char *node_path,
- 			  const char *property, const char *string)
-@@ -38,6 +42,7 @@ static int setprop_string(void *fdt, con
- 	return fdt_setprop_string(fdt, offset, property, string);
- }
- 
-+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
- static int setprop_cell(void *fdt, const char *node_path,
- 			const char *property, uint32_t val)
- {
-@@ -46,6 +51,7 @@ static int setprop_cell(void *fdt, const
- 		return offset;
- 	return fdt_setprop_cell(fdt, offset, property, val);
- }
-+#endif
- 
- static const void *getprop(const void *fdt, const char *node_path,
- 			   const char *property, int *len)
-@@ -58,6 +64,7 @@ static const void *getprop(const void *f
- 	return fdt_getprop(fdt, offset, property, len);
- }
- 
-+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
- static uint32_t get_cell_size(const void *fdt)
- {
- 	int len;
-@@ -68,6 +75,81 @@ static uint32_t get_cell_size(const void
- 		cell_size = fdt32_to_cpu(*size_len);
- 	return cell_size;
- }
-+#endif
-+
-+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
-+/**
-+ * taken from arch/x86/boot/string.c
-+ * local_strstr - Find the first substring in a %NUL terminated string
-+ * @s1: The string to be searched
-+ * @s2: The string to search for
-+ */
-+static char *local_strstr(const char *s1, const char *s2)
-+{
-+	size_t l1, l2;
-+
-+	l2 = strlen(s2);
-+	if (!l2)
-+		return (char *)s1;
-+	l1 = strlen(s1);
-+	while (l1 >= l2) {
-+		l1--;
-+		if (!memcmp(s1, s2, l2))
-+			return (char *)s1;
-+		s1++;
-+	}
-+	return NULL;
-+}
-+
-+static char *append_rootblock(char *dest, const char *str, int len, void *fdt)
-+{
-+	char *ptr, *end, *tmp;
-+	const char *root="root=";
-+	const char *find_rootblock;
-+	int i, l;
-+	const char *rootblock;
-+
-+	find_rootblock = getprop(fdt, "/chosen", "find-rootblock", &l);
-+	if (!find_rootblock)
-+		find_rootblock = root;
-+
-+	//ARM doesn't have __HAVE_ARCH_STRSTR, so it was copied from x86
-+	ptr = local_strstr(str, find_rootblock);
-+
-+	if(!ptr)
-+		return dest;
-+
-+	end = strchr(ptr, ' ');
-+	end = end ? (end - 1) : (strchr(ptr, 0) - 1);
-+
-+	// Some boards ubi.mtd=XX,ZZZZ, so let's check for '," too.
-+	tmp = strchr(ptr, ',');
-+
-+	if(tmp)
-+		end = end < tmp ? end : tmp - 1;
-+
-+	//find partition number (assumes format root=/dev/mtdXX | /dev/mtdblockXX | yy:XX | ubi.mtd=XX,ZZZZ )
-+	for( i = 0; end >= ptr && *end >= '0' && *end <= '9'; end--, i++);
-+	ptr = end + 1;
-+
-+	/* if append-rootblock property is set use it to append to command line */
-+	rootblock = getprop(fdt, "/chosen", "append-rootblock", &l);
-+	if(rootblock != NULL) {
-+		if(*dest != ' ') {
-+			*dest = ' ';
-+			dest++;
-+			len++;
-+		}
-+		if (len + l + i <= COMMAND_LINE_SIZE) {
-+			memcpy(dest, rootblock, l);
-+			dest += l - 1;
-+			memcpy(dest, ptr, i);
-+			dest += i;
-+		}
-+	}
-+	return dest;
-+}
-+#endif
- 
- static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline)
- {
-@@ -88,18 +170,28 @@ static void merge_fdt_bootargs(void *fdt
- 
- 	/* and append the ATAG_CMDLINE */
- 	if (fdt_cmdline) {
-+
-+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
-+		//save original bootloader args
-+		//and append ubi.mtd with root partition number to current cmdline
-+		setprop_string(fdt, "/chosen", "bootloader-args", fdt_cmdline);
-+		ptr = append_rootblock(ptr, fdt_cmdline, len, fdt);
-+
-+#else
- 		len = strlen(fdt_cmdline);
- 		if (ptr - cmdline + len + 2 < COMMAND_LINE_SIZE) {
- 			*ptr++ = ' ';
- 			memcpy(ptr, fdt_cmdline, len);
- 			ptr += len;
- 		}
-+#endif
- 	}
- 	*ptr = '\0';
- 
- 	setprop_string(fdt, "/chosen", "bootargs", cmdline);
- }
- 
-+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
- static void hex_str(char *out, uint32_t value)
- {
- 	uint32_t digit;
-@@ -117,6 +209,7 @@ static void hex_str(char *out, uint32_t
- 	}
- 	*out = '\0';
- }
-+#endif
- 
- /*
-  * Convert and fold provided ATAGs into the provided FDT.
-@@ -131,9 +224,11 @@ int atags_to_fdt(void *atag_list, void *
- 	struct tag *atag = atag_list;
- 	/* In the case of 64 bits memory size, need to reserve 2 cells for
- 	 * address and size for each bank */
-+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
- 	__be32 mem_reg_property[2 * 2 * NR_BANKS];
--	int memcount = 0;
--	int ret, memsize;
-+	int memsize, memcount = 0;
-+#endif
-+	int ret;
- 
- 	/* make sure we've got an aligned pointer */
- 	if ((u32)atag_list & 0x3)
-@@ -168,7 +263,9 @@ int atags_to_fdt(void *atag_list, void *
- 			else
- 				setprop_string(fdt, "/chosen", "bootargs",
- 					       atag->u.cmdline.cmdline);
--		} else if (atag->hdr.tag == ATAG_MEM) {
-+		}
-+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
-+		else if (atag->hdr.tag == ATAG_MEM) {
- 			if (memcount >= sizeof(mem_reg_property)/4)
- 				continue;
- 			if (!atag->u.mem.size)
-@@ -212,6 +309,10 @@ int atags_to_fdt(void *atag_list, void *
- 		setprop(fdt, "/memory", "reg", mem_reg_property,
- 			4 * memcount * memsize);
- 	}
-+#else
-+
-+	}
-+#endif
- 
- 	return fdt_pack(fdt);
- }
---- a/init/main.c
-+++ b/init/main.c
-@@ -112,6 +112,10 @@
- 
- #include <kunit/test.h>
- 
-+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
-+#include <linux/of.h>
-+#endif
-+
- static int kernel_init(void *);
- 
- extern void init_IRQ(void);
-@@ -995,6 +999,18 @@ asmlinkage __visible void __init __no_sa
- 	pr_notice("Kernel command line: %s\n", saved_command_line);
- 	/* parameters may set static keys */
- 	jump_label_init();
-+
-+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
-+	//Show bootloader's original command line for reference
-+	if(of_chosen) {
-+		const char *prop = of_get_property(of_chosen, "bootloader-args", NULL);
-+		if(prop)
-+			pr_notice("Bootloader command line (ignored): %s\n", prop);
-+		else
-+			pr_notice("Bootloader command line not present\n");
-+	}
-+#endif
-+
- 	parse_early_param();
- 	after_dashes = parse_args("Booting kernel",
- 				  static_command_line, __start___param,
diff --git a/target/linux/ipq806x/patches-6.1/900-arm-add-cmdline-override.patch b/target/linux/ipq806x/patches-6.1/900-arm-add-cmdline-override.patch
index 20046325136071..c9583549d0c39b 100644
--- a/target/linux/ipq806x/patches-6.1/900-arm-add-cmdline-override.patch
+++ b/target/linux/ipq806x/patches-6.1/900-arm-add-cmdline-override.patch
@@ -1,6 +1,6 @@
 --- a/arch/arm/Kconfig
 +++ b/arch/arm/Kconfig
-@@ -1601,6 +1601,14 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGL
+@@ -1589,6 +1589,14 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
  
  endchoice
  
diff --git a/target/linux/ipq806x/patches-6.1/901-01-ARM-decompressor-support-memory-start-validation-.patch b/target/linux/ipq806x/patches-6.1/901-01-ARM-decompressor-support-memory-start-validation-.patch
new file mode 100644
index 00000000000000..04e2a0c57e64f7
--- /dev/null
+++ b/target/linux/ipq806x/patches-6.1/901-01-ARM-decompressor-support-memory-start-validation-.patch
@@ -0,0 +1,75 @@
+From 2f86b9b71a11f86e3d850214ab781ebb17d7260e Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Fri, 19 Jan 2024 19:48:30 +0100
+Subject: [PATCH v2 1/2] ARM: decompressor: support memory start validation for
+ appended DTB
+
+There is currently a problem with a very specific sets of kernel config
+and AUTO_ZRELADDR.
+
+For the most common case AUTO_ZRELADDR check the PC register and
+calculate the start of the physical memory. Then fdt_check_mem_start is
+called to make sure the detected value makes sense by comparing it with
+what is present in DTB in the memory nodes and if additional fixup are
+required with the use of linux,usable-memory-range in the chosen node to
+hardcode usable memory range in case some reserved space needs to be
+addressed. With the help of this function the right address is
+calculated and the kernel correctly decompress and loads.
+
+Things starts to become problematic when in the mix,
+CONFIG_ARM_APPENDED_DTB is used. This is a particular kernel config is
+used when legacy systems doesn't support passing a DTB directly and a
+DTB is appended at the end of the image.
+
+In such case, fdt_check_mem_start is skipped in AUTO_ZRELADDR iteration
+as the appended DTB can be augumented later with ATAGS passed from the
+bootloader (if CONFIG_ARM_ATAG_DTB_COMPAT is enabled).
+
+The main problem and what this patch address is the fact that
+fdt_check_mem_start is never called later when the appended DTB is
+augumented, hence any fixup and validation is not done making AUTO_ZRELADDR
+detection inconsistent and most of the time wrong.
+
+Add support in head.S for this by checking if AUTO_ZRELADDR is enabled
+and calling fdt_check_mem_start with the appended DTB and the augumented
+values permitting legacy device to provide info in DTB instead of
+disabling AUTO_ZRELADDR and hardcoding the physical address offsets.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ arch/arm/boot/compressed/head.S | 22 ++++++++++++++++++++++
+ 1 file changed, 22 insertions(+)
+
+--- a/arch/arm/boot/compressed/head.S
++++ b/arch/arm/boot/compressed/head.S
+@@ -443,6 +443,28 @@ restart:	adr	r0, LC1
+ 		add	r6, r6, r5
+ 		add	r10, r10, r5
+ 		add	sp, sp, r5
++
++#ifdef CONFIG_AUTO_ZRELADDR
++		/*
++		 * Validate calculated start of physical memory with appended DTB.
++		 * In the first iteration for physical memory start calculation,
++		 * we skipped validating it as it could have been augumented by
++		 * ATAGS stored at an offset from the same start of physical memory.
++		 *
++		 * We now have parsed them and augumented the appended DTB if asked
++		 * so we can finally validate the start of physical memory.
++		 *
++		 * This is needed to apply additional fixup with
++		 * linux,usable-memory-range or to make sure AUTO_ZRELADDR detected
++		 * the correct value.
++		 */
++		sub	r0, r4, #TEXT_OFFSET	@ revert to base address
++		mov	r1, r8			@ use appended DTB
++		bl	fdt_check_mem_start
++
++		/* Determine final kernel image address. */
++		add	r4, r0, #TEXT_OFFSET
++#endif
+ dtb_check_done:
+ #endif
+ 
diff --git a/target/linux/ipq806x/patches-6.1/901-02-ARM-decompressor-add-option-to-ignore-MEM-ATAGs.patch b/target/linux/ipq806x/patches-6.1/901-02-ARM-decompressor-add-option-to-ignore-MEM-ATAGs.patch
new file mode 100644
index 00000000000000..2e4c4de545c54e
--- /dev/null
+++ b/target/linux/ipq806x/patches-6.1/901-02-ARM-decompressor-add-option-to-ignore-MEM-ATAGs.patch
@@ -0,0 +1,54 @@
+From 781d7cd4c3364e9d38fa12a342c5ad4c7e33a5ba Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Fri, 19 Jan 2024 20:33:10 +0100
+Subject: [PATCH v2 2/2] ARM: decompressor: add option to ignore MEM ATAGs
+
+Some bootloaders can pass broken MEM ATAGs that provide hardcoded
+information about mounted RAM size and physical location.
+Example booloader provide RAM of size 1.7Gb but actual mounted RAM
+size is 512Mb causing kernel panic.
+
+Add option CONFIG_ARM_ATAG_DTB_COMPAT_IGNORE_MEM to ignore these ATAG
+and not augument appended DTB memory node.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Acked-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ arch/arm/Kconfig                        | 12 ++++++++++++
+ arch/arm/boot/compressed/atags_to_fdt.c |  4 ++++
+ 2 files changed, 16 insertions(+)
+
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -1570,6 +1570,18 @@ config ARM_ATAG_DTB_COMPAT
+ 	  bootloaders, this option allows zImage to extract the information
+ 	  from the ATAG list and store it at run time into the appended DTB.
+ 
++config ARM_ATAG_DTB_COMPAT_IGNORE_MEM
++	bool "Ignore MEM ATAG information from bootloader"
++	depends on ARM_ATAG_DTB_COMPAT
++	help
++	  Some bootloaders can pass broken MEM ATAGs that provide hardcoded
++	  information about mounted RAM size and physical location.
++	  Example booloader provide RAM of size 1.7Gb but actual mounted RAM
++	  size is 512Mb causing kernel panic.
++
++	  Enable this option if MEM ATAGs should be ignored and the memory
++	  node in the appended DTB should NOT be augumented.
++
+ choice
+ 	prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
+ 	default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
+--- a/arch/arm/boot/compressed/atags_to_fdt.c
++++ b/arch/arm/boot/compressed/atags_to_fdt.c
+@@ -169,6 +169,10 @@ int atags_to_fdt(void *atag_list, void *
+ 				setprop_string(fdt, "/chosen", "bootargs",
+ 					       atag->u.cmdline.cmdline);
+ 		} else if (atag->hdr.tag == ATAG_MEM) {
++			/* Bootloader MEM ATAG are broken and should be ignored */
++			if (IS_ENABLED(CONFIG_ARM_ATAG_DTB_COMPAT_IGNORE_MEM))
++				continue;
++
+ 			if (memcount >= sizeof(mem_reg_property)/4)
+ 				continue;
+ 			if (!atag->u.mem.size)
diff --git a/target/linux/ipq806x/patches-6.1/902-ARM-decompressor-support-for-ATAGs-rootblock-parsing.patch b/target/linux/ipq806x/patches-6.1/902-ARM-decompressor-support-for-ATAGs-rootblock-parsing.patch
new file mode 100644
index 00000000000000..60b80fefe17571
--- /dev/null
+++ b/target/linux/ipq806x/patches-6.1/902-ARM-decompressor-support-for-ATAGs-rootblock-parsing.patch
@@ -0,0 +1,197 @@
+From 13bb6d8dd9138927950a520a288401db82871dc9 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Sun, 21 Jan 2024 23:36:57 +0100
+Subject: [PATCH] ARM: decompressor: support for ATAGs rootblock parsing
+
+The command-line arguments provided by the boot loader will be
+appended to a new device tree property: bootloader-args.
+
+If there is a property "append-rootblock" in DT under /chosen
+and a root= option in bootloaders command line it will be parsed
+and added to DT bootargs with the form: <append-rootblock>XX.
+
+This is usefull in dual boot systems, to get the current root partition
+without afecting the rest of the system.
+
+Signed-off-by: Adrian Panella <ianchi74@outlook.com>
+[ reworked to a cleaner patch ]
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ arch/arm/Kconfig                        |  10 +++
+ arch/arm/boot/compressed/atags_to_fdt.c | 102 ++++++++++++++++++++++--
+ init/main.c                             |  12 +++
+ 3 files changed, 117 insertions(+), 7 deletions(-)
+
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -1599,6 +1599,16 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
+ 	  The command-line arguments provided by the boot loader will be
+ 	  appended to the the device tree bootargs property.
+ 
++config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
++	bool "Append rootblock parsing bootloader's kernel arguments"
++	help
++	  The command-line arguments provided by the boot loader will be
++	  appended to a new device tree property: bootloader-args.
++
++	  If there is a property "append-rootblock" in DT under /chosen
++	  and a root= option in bootloaders command line it will be parsed
++	  and added to DT bootargs with the form: <append-rootblock>XX.
++
+ endchoice
+ 
+ config CMDLINE_OVERRIDE
+--- a/arch/arm/boot/compressed/atags_to_fdt.c
++++ b/arch/arm/boot/compressed/atags_to_fdt.c
+@@ -3,7 +3,8 @@
+ #include <asm/setup.h>
+ #include <libfdt.h>
+ 
+-#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND)
++#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND) || \
++	defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
+ #define do_extend_cmdline 1
+ #else
+ #define do_extend_cmdline 0
+@@ -69,6 +70,83 @@ static uint32_t get_cell_size(const void
+ 	return cell_size;
+ }
+ 
++/**
++ * taken from arch/x86/boot/string.c
++ * local_strstr - Find the first substring in a %NUL terminated string
++ * @s1: The string to be searched
++ * @s2: The string to search for
++ */
++static char *local_strstr(const char *s1, const char *s2)
++{
++	size_t l1, l2;
++
++	l2 = strlen(s2);
++	if (!l2)
++		return (char *)s1;
++	l1 = strlen(s1);
++	while (l1 >= l2) {
++		l1--;
++		if (!memcmp(s1, s2, l2))
++			return (char *)s1;
++		s1++;
++	}
++	return NULL;
++}
++
++static char *append_rootblock(char *dest, const char *str, int len, void *fdt)
++{
++	char *ptr, *end, *tmp;
++	const char *root="root=";
++	const char *find_rootblock;
++	int i, l;
++	const char *rootblock;
++
++	find_rootblock = getprop(fdt, "/chosen", "find-rootblock", &l);
++	if (!find_rootblock)
++		find_rootblock = root;
++
++	/* ARM doesn't have __HAVE_ARCH_STRSTR, so it was copied from x86 */
++	ptr = local_strstr(str, find_rootblock);
++	if (!ptr)
++		return dest;
++
++	end = strchr(ptr, ' ');
++	end = end ? (end - 1) : (strchr(ptr, 0) - 1);
++
++	/* Some boards ubi.mtd=XX,ZZZZ, so let's check for '," too. */
++	tmp = strchr(ptr, ',');
++	if (tmp)
++		end = end < tmp ? end : tmp - 1;
++
++	/*
++	 * find partition number
++	 * (assumes format root=/dev/mtdXX | /dev/mtdblockXX | yy:XX | ubi.mtd=XX,ZZZZ )
++	 */
++	for (i = 0; end >= ptr && *end >= '0' && *end <= '9'; end--, i++);
++
++	ptr = end + 1;
++
++	/* if append-rootblock property is set use it to append to command line */
++	rootblock = getprop(fdt, "/chosen", "append-rootblock", &l);
++	if (rootblock != NULL) {
++		if (*dest != ' ') {
++			*dest = ' ';
++			dest++;
++			len++;
++		}
++
++		if (len + l + i <= COMMAND_LINE_SIZE) {
++			memcpy(dest, rootblock, l);
++			dest += l - 1;
++
++			memcpy(dest, ptr, i);
++			dest += i;
++		}
++	}
++
++	return dest;
++}
++
+ static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline)
+ {
+ 	char cmdline[COMMAND_LINE_SIZE];
+@@ -86,13 +164,23 @@ static void merge_fdt_bootargs(void *fdt
+ 			ptr += len - 1;
+ 		}
+ 
+-	/* and append the ATAG_CMDLINE */
+ 	if (fdt_cmdline) {
+-		len = strlen(fdt_cmdline);
+-		if (ptr - cmdline + len + 2 < COMMAND_LINE_SIZE) {
+-			*ptr++ = ' ';
+-			memcpy(ptr, fdt_cmdline, len);
+-			ptr += len;
++		if (IS_ENABLED(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)) {
++			/*
++			* save original bootloader args
++			* and append ubi.mtd with root partition number
++			* to current cmdline
++			*/
++			setprop_string(fdt, "/chosen", "bootloader-args", fdt_cmdline);
++			ptr = append_rootblock(ptr, fdt_cmdline, len, fdt);
++		} else {
++			/* and append the ATAG_CMDLINE */
++			len = strlen(fdt_cmdline);
++			if (ptr - cmdline + len + 2 < COMMAND_LINE_SIZE) {
++				*ptr++ = ' ';
++				memcpy(ptr, fdt_cmdline, len);
++				ptr += len;
++			}
+ 		}
+ 	}
+ 	*ptr = '\0';
+--- a/init/main.c
++++ b/init/main.c
+@@ -28,6 +28,7 @@
+ #include <linux/initrd.h>
+ #include <linux/memblock.h>
+ #include <linux/acpi.h>
++#include <linux/of.h>
+ #include <linux/bootconfig.h>
+ #include <linux/console.h>
+ #include <linux/nmi.h>
+@@ -995,6 +996,17 @@ asmlinkage __visible void __init __no_sa
+ 	pr_notice("Kernel command line: %s\n", saved_command_line);
+ 	/* parameters may set static keys */
+ 	jump_label_init();
++
++	/* Show bootloader's original command line for reference */
++	if (IS_ENABLED(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) && of_chosen) {
++		const char *prop = of_get_property(of_chosen, "bootloader-args", NULL);
++
++		if(prop)
++			pr_notice("Bootloader command line (ignored): %s\n", prop);
++		else
++			pr_notice("Bootloader command line not present\n");
++	}
++
+ 	parse_early_param();
+ 	after_dashes = parse_args("Booting kernel",
+ 				  static_command_line, __start___param,
diff --git a/target/linux/kirkwood/Makefile b/target/linux/kirkwood/Makefile
index 54f26281a497bd..424e699157bfe3 100644
--- a/target/linux/kirkwood/Makefile
+++ b/target/linux/kirkwood/Makefile
@@ -7,7 +7,7 @@ include $(TOPDIR)/rules.mk
 ARCH:=arm
 BOARD:=kirkwood
 BOARDNAME:=Marvell Kirkwood
-FEATURES:=usb nand squashfs ramdisk
+FEATURES:=rtc usb nand squashfs ramdisk
 CPU_TYPE:=xscale
 SUBTARGETS:=generic
 
diff --git a/target/linux/kirkwood/files/arch/arm/boot/dts/kirkwood-ix4-200d.dts b/target/linux/kirkwood/files/arch/arm/boot/dts/kirkwood-ix4-200d.dts
index c63742a1a8814e..d57e1f5d5a155e 100644
--- a/target/linux/kirkwood/files/arch/arm/boot/dts/kirkwood-ix4-200d.dts
+++ b/target/linux/kirkwood/files/arch/arm/boot/dts/kirkwood-ix4-200d.dts
@@ -112,21 +112,18 @@
 			compatible = "gpio-leds";
 
 			led_status_white: led-0 {
-				label = "status:white";
 				function = LED_FUNCTION_STATUS;
 				color = <LED_COLOR_ID_WHITE>;
 				gpios = <&gpio_spi 4 GPIO_ACTIVE_LOW>;
 			};
 
 			led_status_red: led-1 {
-				label = "status:red";
 				function = LED_FUNCTION_STATUS;
 				color = <LED_COLOR_ID_RED>;
 				gpios = <&gpio_spi 5 GPIO_ACTIVE_LOW>;
 			};
 
 			led_power_white: led-2 {
-				label = "power:white";
 				function = LED_FUNCTION_POWER;
 				color = <LED_COLOR_ID_WHITE>;
 				gpios = <&gpio_spi 7 GPIO_ACTIVE_HIGH>;
diff --git a/target/linux/kirkwood/files/arch/arm/boot/dts/kirkwood-nas1.dts b/target/linux/kirkwood/files/arch/arm/boot/dts/kirkwood-nas1.dts
index a8d86406b53343..379db8acd8a81e 100644
--- a/target/linux/kirkwood/files/arch/arm/boot/dts/kirkwood-nas1.dts
+++ b/target/linux/kirkwood/files/arch/arm/boot/dts/kirkwood-nas1.dts
@@ -1,6 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /dts-v1/;
 
+#include <dt-bindings/leds/common.h>
+
 #include "kirkwood.dtsi"
 #include "kirkwood-6281.dtsi"
 
@@ -43,7 +45,8 @@
 		};
 
 		usb {
-			label = "blue:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&ehci_port1>;
 			linux,default-trigger = "usbport";
diff --git a/target/linux/kirkwood/image/Makefile b/target/linux/kirkwood/image/Makefile
index 0fa14b89f32cf1..49d0124f43a062 100644
--- a/target/linux/kirkwood/image/Makefile
+++ b/target/linux/kirkwood/image/Makefile
@@ -105,7 +105,7 @@ define Device/cisco_on100
   KERNEL_IN_UBI :=
   UBINIZE_OPTS := -E 5
   IMAGE/factory.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi
-  DEVICE_PACKAGES := kmod-mvsdio
+  DEVICE_PACKAGES := kmod-mvsdio kmod-rtc-mv
   SUPPORTED_DEVICES += on100
 endef
 TARGET_DEVICES += cisco_on100
@@ -114,6 +114,7 @@ define Device/cloudengines_pogoe02
   DEVICE_VENDOR := Cloud Engines
   DEVICE_MODEL := Pogoplug E02
   DEVICE_DTS := kirkwood-pogo_e02
+  DEVICE_PACKAGES := kmod-rtc-mv
   SUPPORTED_DEVICES += pogo_e02
 endef
 TARGET_DEVICES += cloudengines_pogoe02
@@ -123,7 +124,7 @@ define Device/cloudengines_pogoplugv4
   DEVICE_MODEL := Pogoplug V4
   DEVICE_DTS := kirkwood-pogoplug-series-4
   DEVICE_PACKAGES := kmod-ata-marvell-sata kmod-fs-ext4 kmod-mvsdio kmod-usb3 \
-	kmod-gpio-button-hotplug
+	kmod-gpio-button-hotplug kmod-rtc-mv
 endef
 TARGET_DEVICES += cloudengines_pogoplugv4
 
@@ -145,7 +146,7 @@ define Device/endian_4i-edge-200
   DEVICE_MODEL := 4i Edge 200
   DEVICE_ALT0_VENDOR := Endian
   DEVICE_ALT0_MODEL := UTM Mini Firewall
-  DEVICE_PACKAGES := kmod-ath9k kmod-mvsdio wpad-basic-mbedtls
+  DEVICE_PACKAGES := kmod-ath9k kmod-mvsdio wpad-basic-mbedtls kmod-rtc-mv
   KERNEL_SIZE := 4096k
   IMAGES := sysupgrade.bin
 endef
@@ -154,13 +155,14 @@ TARGET_DEVICES += endian_4i-edge-200
 define Device/globalscale_sheevaplug
   DEVICE_VENDOR := Globalscale
   DEVICE_MODEL := Sheevaplug
-  DEVICE_PACKAGES := kmod-mvsdio
+  DEVICE_PACKAGES := kmod-mvsdio kmod-rtc-mv
 endef
 TARGET_DEVICES += globalscale_sheevaplug
 
 define Device/iom_iconnect-1.1
   DEVICE_VENDOR := Iomega
   DEVICE_MODEL := Iconnect
+  DEVICE_PACKAGES := kmod-rtc-mv
   DEVICE_DTS := kirkwood-iconnect
   SUPPORTED_DEVICES += iconnect
 endef
@@ -171,7 +173,7 @@ define Device/iom_ix2-200
   DEVICE_MODEL := StorCenter ix2-200
   DEVICE_DTS := kirkwood-iomega_ix2_200
   DEVICE_PACKAGES := kmod-ata-marvell-sata kmod-fs-ext4 \
-	kmod-gpio-button-hotplug kmod-hwmon-lm63
+	kmod-gpio-button-hotplug kmod-hwmon-lm63 kmod-rtc-mv
   PAGESIZE := 512
   SUBPAGESIZE := 256
   BLOCKSIZE := 16k
@@ -189,7 +191,7 @@ define Device/iom_ix4-200d
   DEVICE_MODEL := StorCenter ix4-200d
   DEVICE_PACKAGES := kmod-ata-marvell-sata kmod-fs-ext4 \
 	kmod-gpio-button-hotplug kmod-gpio-nxp-74hc164 \
-	kmod-hwmon-adt7475 kmod-mvsdio kmod-spi-gpio
+	kmod-hwmon-adt7475 kmod-mvsdio kmod-spi-gpio kmod-rtc-mv
   PAGESIZE := 512
   SUBPAGESIZE := 256
   BLOCKSIZE := 16k
@@ -207,7 +209,7 @@ define Device/iptime_nas1
   DEVICE_MODEL := NAS1
   DEVICE_PACKAGES := kmod-ata-marvell-sata kmod-fs-ext4 \
 	kmod-gpio-button-hotplug kmod-gpio-pca953x kmod-hwmon-drivetemp \
-	kmod-hwmon-gpiofan kmod-usb-ledtrig-usbport -uboot-envtools
+	kmod-hwmon-gpiofan kmod-usb-ledtrig-usbport kmod-rtc-mv -uboot-envtools
   KERNEL := $$(KERNEL) | iptime-naspkg nas1
   BLOCKSIZE := 256k
   IMAGE_SIZE := 15872k
@@ -219,7 +221,8 @@ TARGET_DEVICES += iptime_nas1
 
 define Device/linksys
   DEVICE_VENDOR := Linksys
-  DEVICE_PACKAGES := kmod-mwl8k wpad-basic-mbedtls kmod-gpio-button-hotplug
+  DEVICE_PACKAGES := kmod-mwl8k wpad-basic-mbedtls kmod-gpio-button-hotplug \
+	kmod-rtc-mv
   KERNEL_IN_UBI :=
   UBINIZE_OPTS := -E 5
   IMAGE/factory.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi
@@ -272,7 +275,7 @@ define Device/raidsonic_ib-nas62x0
   DEVICE_VENDOR := RaidSonic
   DEVICE_MODEL := ICY BOX IB-NAS62x0
   DEVICE_DTS := kirkwood-ib62x0
-  DEVICE_PACKAGES := kmod-ata-marvell-sata kmod-fs-ext4
+  DEVICE_PACKAGES := kmod-ata-marvell-sata kmod-fs-ext4 kmod-rtc-mv
   SUPPORTED_DEVICES += ib62x0
 endef
 TARGET_DEVICES += raidsonic_ib-nas62x0
@@ -281,7 +284,7 @@ define Device/seagate_blackarmor-nas220
   DEVICE_VENDOR := Seagate
   DEVICE_MODEL := Blackarmor NAS220
   DEVICE_PACKAGES := kmod-hwmon-adt7475 kmod-fs-ext4 kmod-ata-marvell-sata \
-	mdadm kmod-gpio-button-hotplug
+	mdadm kmod-gpio-button-hotplug kmod-rtc-mv
   PAGESIZE := 512
   SUBPAGESIZE := 256
   BLOCKSIZE := 16k
@@ -292,6 +295,7 @@ TARGET_DEVICES += seagate_blackarmor-nas220
 define Device/seagate_dockstar
   DEVICE_VENDOR := Seagate
   DEVICE_MODEL := FreeAgent Dockstar
+  DEVICE_PACKAGES := kmod-rtc-mv
   SUPPORTED_DEVICES += dockstar
 endef
 TARGET_DEVICES += seagate_dockstar
@@ -299,7 +303,7 @@ TARGET_DEVICES += seagate_dockstar
 define Device/seagate_goflexnet
   DEVICE_VENDOR := Seagate
   DEVICE_MODEL := GoFlexNet
-  DEVICE_PACKAGES := kmod-ata-marvell-sata kmod-fs-ext4
+  DEVICE_PACKAGES := kmod-ata-marvell-sata kmod-fs-ext4 kmod-rtc-mv
   SUPPORTED_DEVICES += goflexnet
 endef
 TARGET_DEVICES += seagate_goflexnet
@@ -307,7 +311,7 @@ TARGET_DEVICES += seagate_goflexnet
 define Device/seagate_goflexhome
   DEVICE_VENDOR := Seagate
   DEVICE_MODEL := GoFlexHome
-  DEVICE_PACKAGES := kmod-ata-marvell-sata kmod-fs-ext4
+  DEVICE_PACKAGES := kmod-ata-marvell-sata kmod-fs-ext4 kmod-rtc-mv
   SUPPORTED_DEVICES += goflexhome
 endef
 TARGET_DEVICES += seagate_goflexhome
@@ -316,7 +320,7 @@ define Device/zyxel_nsa310b
   DEVICE_VENDOR := ZyXEL
   DEVICE_MODEL := NSA310b
   DEVICE_PACKAGES := kmod-ata-marvell-sata kmod-r8169 kmod-fs-ext4 \
-	kmod-gpio-button-hotplug kmod-hwmon-lm85
+	kmod-gpio-button-hotplug kmod-hwmon-lm85 kmod-rtc-mv
   SUPPORTED_DEVICES += nsa310b
 endef
 TARGET_DEVICES += zyxel_nsa310b
diff --git a/target/linux/kirkwood/patches-6.1/202-linksys-find-active-root.patch b/target/linux/kirkwood/patches-6.1/202-linksys-find-active-root.patch
index 515bb21707e3c8..5029b1791c1035 100644
--- a/target/linux/kirkwood/patches-6.1/202-linksys-find-active-root.patch
+++ b/target/linux/kirkwood/patches-6.1/202-linksys-find-active-root.patch
@@ -22,7 +22,7 @@ Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
  	const char *partname;
  	struct device_node *pp;
  	int nr_parts, i, ret = 0;
-@@ -133,9 +136,15 @@ static int parse_fixed_partitions(struct
+@@ -152,9 +155,15 @@ static int parse_fixed_partitions(struct
  		parts[i].size = of_read_number(reg + a_cells, s_cells);
  		parts[i].of_node = pp;
  
@@ -41,7 +41,7 @@ Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
  		parts[i].name = partname;
  
  		if (of_get_property(pp, "read-only", &len))
-@@ -252,6 +261,18 @@ static int __init ofpart_parser_init(voi
+@@ -271,6 +280,18 @@ static int __init ofpart_parser_init(voi
  	return 0;
  }
  
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/amazonse_allnet_all0333cj.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/amazonse_allnet_all0333cj.dts
index 67c6e87bcd1182..e543ab29aa51e0 100644
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/amazonse_allnet_all0333cj.dts
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/amazonse_allnet_all0333cj.dts
@@ -1,3 +1,5 @@
+#include <dt-bindings/leds/common.h>
+
 #include "amazonse.dtsi"
 
 / {
@@ -28,13 +30,15 @@
 
 		/* power led: red=off, green=on */
 		power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 			default-state = "keep";
 		};
 
 		lan: lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/amazonse_netgear_dgn1000b.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/amazonse_netgear_dgn1000b.dts
index 144667ffb645b3..524d97e03c0225 100644
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/amazonse_netgear_dgn1000b.dts
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/amazonse_netgear_dgn1000b.dts
@@ -1,6 +1,7 @@
 #include "amazonse.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "netgear,dgn1000b", "lantiq,xway", "lantiq,ase";
@@ -64,12 +65,14 @@
 			default-state = "on";
 		};
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 		power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 			default-state = "keep";
 		};
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_avm_fritz7312.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_avm_fritz7312.dts
index ba2b82dd670ae6..c6f0454d10fdf3 100644
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_avm_fritz7312.dts
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_avm_fritz7312.dts
@@ -1,6 +1,7 @@
 #include "ar9.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/mtd/partitions/uimage.h>
 
 / {
@@ -46,7 +47,8 @@
 		compatible = "gpio-leds";
 
 		power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
 			default-state = "keep";
 		};
@@ -59,7 +61,8 @@
 			gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
 		};
 		wlan: wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
 		};
 		info_green: info_green {
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_avm_fritz7320.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_avm_fritz7320.dts
index b04efd8a846cc4..3023d4925db589 100644
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_avm_fritz7320.dts
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_avm_fritz7320.dts
@@ -1,6 +1,7 @@
 #include "ar9.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/mtd/partitions/uimage.h>
 
 / {
@@ -45,7 +46,8 @@
 	leds {
 		compatible = "gpio-leds";
 		power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
 			default-state = "keep";
 		};
@@ -58,7 +60,8 @@
 			gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
 		};
 		wlan: wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
 		};
 		info_green: info_green {
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_bt_homehub-v3a.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_bt_homehub-v3a.dts
index 71b32b62f5ab1c..e8024d6463a1de 100644
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_bt_homehub-v3a.dts
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_bt_homehub-v3a.dts
@@ -1,6 +1,7 @@
 #include "ar9.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "bt,homehub-v3a", "lantiq,xway", "lantiq,ar9";
@@ -75,16 +76,19 @@
 		};
 
 		power_red: power-red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		};
 		power_orange: power-orange {
-			label = "orange:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
 			default-state = "keep";
 		};
 		power_blue: power-blue {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_buffalo_wbmr-hp-g300h.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_buffalo_wbmr-hp-g300h.dts
index 7e0f157bf323fe..5a50f27c08b059 100644
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_buffalo_wbmr-hp-g300h.dts
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_buffalo_wbmr-hp-g300h.dts
@@ -1,6 +1,7 @@
 #include "ar9.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "buffalo,wbmr-hp-g300h", "lantiq,xway", "lantiq,ar9";
@@ -57,12 +58,14 @@
 		compatible = "gpio-leds";
 
 		power_green: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
 			default-state = "keep";
 		};
 		power_red: power2 {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
 		};
 		security {
@@ -90,7 +93,8 @@
 			gpios = <&gpio 20 GPIO_ACTIVE_LOW>;
 		};
 		led_usb: usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 28 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500.dtsi
index 18168230b6ab4a..8409e079431b0f 100644
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500.dtsi
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500.dtsi
@@ -1,6 +1,7 @@
 #include "ar9.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	chosen {
@@ -79,16 +80,19 @@
 			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
 		};
 		led_usb: usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
 		};
 		power_green: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 34 GPIO_ACTIVE_LOW>;
 			default-state = "keep";
 		};
 		power_red: power2 {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 39 GPIO_ACTIVE_LOW>;
 		};
 		wifi_green: wifi {
@@ -100,7 +104,8 @@
 			gpios = <&gpio 51 GPIO_ACTIVE_LOW>;
 		};
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 52 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_zte_h201l.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_zte_h201l.dts
index 486261d742213b..b17efe740aa31a 100644
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_zte_h201l.dts
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_zte_h201l.dts
@@ -1,6 +1,7 @@
 #include "ar9.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "zte,h201l", "lantiq,xway", "lantiq,ar9";
@@ -52,7 +53,8 @@
 		compatible = "gpio-leds";
 
 		power_green: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
 			default-state = "keep";
 		};
@@ -69,15 +71,18 @@
 			gpios = <&gpio 39 GPIO_ACTIVE_LOW>;
 		};
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
 		};
 		wifi: wifi {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
 		};
 		led_usb: usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_zyxel_p-2601hn.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_zyxel_p-2601hn.dts
index 2177726d817458..8baf91861c4805 100644
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_zyxel_p-2601hn.dts
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_zyxel_p-2601hn.dts
@@ -1,6 +1,7 @@
 #include "ar9.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "zyxel,p-2601hn", "lantiq,xway", "lantiq,ar9";
@@ -46,12 +47,14 @@
 		compatible = "gpio-leds";
 
 		power_green: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&stp 11 GPIO_ACTIVE_LOW>;
 			default-state = "keep";
 		};
 		power_red: power2 {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 29 GPIO_ACTIVE_LOW>;
 		};
 		online: online {
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4519pw.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4519pw.dts
index 72f8c3bc6615cd..3eff5cd6da57ea 100644
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4519pw.dts
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4519pw.dts
@@ -1,6 +1,7 @@
 #include "danube.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "arcadyan,arv4519pw", "lantiq,xway", "lantiq,danube";
@@ -47,16 +48,19 @@
 		compatible = "gpio-leds";
 
 		power_green: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
 			default-state = "keep";
 		};
 		power_red: power2 {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
 		};
 		wifi: wifi {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
 		};
 		dsl: dsl {
@@ -72,7 +76,8 @@
 			gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
 		};
 		led_usb: usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
 		};
 		voip {
@@ -92,15 +97,18 @@
 			gpios = <&gpiomm 3 GPIO_ACTIVE_LOW>;
 		};
 		wps2 {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpiomm 4 GPIO_ACTIVE_LOW>;
 		};
 		wps {
-			label = "orange:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpiomm 5 GPIO_ACTIVE_LOW>;
 		};
 		wps3 {
-			label = "red:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpiomm 6 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4520pw.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4520pw.dts
index 775aab4ba96b60..c2b44ebb66e388 100644
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4520pw.dts
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4520pw.dts
@@ -1,6 +1,7 @@
 #include "danube.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "arcadyan,arv4520pw", "lantiq,xway", "lantiq,danube";
@@ -47,7 +48,8 @@
 		compatible = "gpio-leds";
 
 		power_blue: power {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
 			default-state = "keep";
 		};
@@ -60,15 +62,18 @@
 			gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
 		};
 		power_red: power2 {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
 		};
 		wps {
-			label = "yellow:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_YELLOW>;
 			gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
 		};
 		wps2 {
-			label = "red:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
 		};
 		/*
@@ -95,7 +100,8 @@
 			gpios = <&gpiomm 4 GPIO_ACTIVE_LOW>;
 		};
 		led_usb: usb {
-			label = "blue:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpiomm 5 GPIO_ACTIVE_LOW>;
 		};
 		wifi: wifi {
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4525pw.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4525pw.dts
index 182b0c0bb183bf..e781be33910fd0 100644
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4525pw.dts
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4525pw.dts
@@ -1,6 +1,7 @@
 #include "danube.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "arcadyan,arv4525pw", "lantiq,xway", "lantiq,danube";
@@ -63,7 +64,8 @@
 			gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
 		};
 		wifi: wifi {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
 		};
 		online: online {
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv452cqw.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv452cqw.dts
index 4825eb2952eae9..34bb167b6a1dc7 100644
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv452cqw.dts
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv452cqw.dts
@@ -1,6 +1,7 @@
 #include "danube.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "arcadyan,arv452cqw", "lantiq,xway", "lantiq,danube";
@@ -57,7 +58,8 @@
 	leds {
 		compatible = "gpio-leds";
 		power_blue: power0 {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
 			default-state = "keep";
 		};
@@ -70,15 +72,18 @@
 			gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
 		};
 		power_red: power1 {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
 		};
 		wps {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
 		};
 		wps1 {
-			label = "yellow:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_YELLOW>;
 			gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
 		};
 		fxs1 {
@@ -90,7 +95,8 @@
 			gpios = <&gpiomm 1 GPIO_ACTIVE_LOW>;
 		};
 		wps2 {
-			label = "red:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpiomm 2 GPIO_ACTIVE_LOW>;
 		};
 		fxo {
@@ -102,11 +108,13 @@
 			gpios = <&gpiomm 4 1>;
 		};
 		led_usb: usb {
-			label = "blue:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpiomm 5 GPIO_ACTIVE_LOW>;
 		};
 		wifi: wifi {
-			label = "blue:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpiomm 6 GPIO_ACTIVE_LOW>;
 		};
 		/*
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7506pw11.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7506pw11.dts
index 3f957c63a60408..1c1fa2f77dd833 100644
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7506pw11.dts
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7506pw11.dts
@@ -1,6 +1,7 @@
 #include "danube.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "arcadyan,arv7506pw11", "lantiq,xway", "lantiq,danube";
@@ -45,11 +46,13 @@
 	leds {
 		compatible = "gpio-leds";
 		wlan: wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
 		};
 		power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
 			default-state = "keep";
 		};
@@ -62,7 +65,8 @@
 			gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
 		};
 		power_red: power_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
 		};
 		internet_red {
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7518pw.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7518pw.dts
index fb3363b2e2aab8..34b88084429328 100644
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7518pw.dts
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7518pw.dts
@@ -1,6 +1,7 @@
 #include "danube.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "arcadyan,arv7518pw", "lantiq,xway", "lantiq,danube";
@@ -46,7 +47,8 @@
 	leds {
 		compatible = "gpio-leds";
 		power_green: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
 			default-state = "keep";
 		};
@@ -59,11 +61,13 @@
 			gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
 		};
 		wifi: wifi {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
 		};
 		power_red: power2 {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
 		};
 		online2 {
@@ -71,7 +75,8 @@
 			gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
 		};
 		led_usb: usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
 		};
 		voice {
@@ -91,15 +96,18 @@
 			gpios = <&gpiomm 3 GPIO_ACTIVE_LOW>;
 		};
 		wps {
-			label = "amber:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpiomm 4 GPIO_ACTIVE_LOW>;
 		};
 		wps2 {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpiomm 5 GPIO_ACTIVE_LOW>;
 		};
 		wps3 {
-			label = "red:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpiomm 6 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7525pw.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7525pw.dts
index d67efb4fca5f2f..890eac972dd22c 100644
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7525pw.dts
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7525pw.dts
@@ -1,6 +1,7 @@
 #include "danube.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "arcadyan,arv7525pw", "lantiq,xway", "lantiq,danube";
@@ -45,12 +46,14 @@
 	leds {
 		compatible = "gpio-leds";
 		power_green: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
 			default-state = "keep";
 		};
 		power_red: power1 {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
 		};
 		online: online {
@@ -66,7 +69,8 @@
 			gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
 		};
 		wifi: wifi {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv752dpw.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv752dpw.dts
index 41a0e1b74a963b..f56ee53e390215 100644
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv752dpw.dts
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv752dpw.dts
@@ -1,6 +1,7 @@
 #include "danube.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "arcadyan,arv752dpw", "lantiq,xway", "lantiq,danube";
@@ -57,7 +58,8 @@
 	leds {
 		compatible = "gpio-leds";
 		power_blue: power1 {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
 		};
 		internet_red: internet {
@@ -69,7 +71,8 @@
 			gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
 		};
 		power_red: power {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
 			default-state = "keep";
 		};
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv752dpw22.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv752dpw22.dts
index 4fb135763d5ba5..910cf65b76a330 100644
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv752dpw22.dts
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv752dpw22.dts
@@ -1,6 +1,7 @@
 #include "danube.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "arcadyan,arv752dpw22", "lantiq,xway", "lantiq,danube";
@@ -54,7 +55,8 @@
 	leds {
 		compatible = "gpio-leds";
 		power_blue: power1 {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
 		};
 		internet_red: internet {
@@ -66,7 +68,8 @@
 			gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
 		};
 		power_red: power {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
 			default-state = "keep";
 		};
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv8539pw22.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv8539pw22.dts
index d6a917057d71e5..1a8b29a4773d71 100644
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv8539pw22.dts
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv8539pw22.dts
@@ -1,6 +1,7 @@
 #include "danube.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "arcadyan,arv8539pw22", "lantiq,xway", "lantiq,danube";
@@ -47,12 +48,14 @@
 		compatible = "gpio-leds";
 
 		power_green: power-green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 24 GPIO_ACTIVE_LOW>;
 			default-state = "keep";
 		};
 		power_red: power-red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
 		};
 
@@ -67,7 +70,8 @@
 		};
 
 		wireless_green: wireless-green {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
 		};
 		/*
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_bt_homehub-v2b.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_bt_homehub-v2b.dts
index 85536b0082a579..4a422c6f4af6a7 100644
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_bt_homehub-v2b.dts
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_bt_homehub-v2b.dts
@@ -1,6 +1,7 @@
 #include "danube.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "bt,homehub-v2b", "lantiq,xway", "lantiq,danube";
@@ -86,16 +87,19 @@
 		};
 
 		power_red: power-red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpios 13 GPIO_ACTIVE_HIGH>;
 		};
 		power_orange: power-orange {
-			label = "orange:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpios 14 GPIO_ACTIVE_HIGH>;
 			default-state = "keep";
 		};
 		power_blue: power-blue {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpios 15 GPIO_ACTIVE_HIGH>;
 		};
 	};
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy88388.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy88388.dts
index fa46dc30fd5821..947fa962ccd27d 100644
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy88388.dts
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy88388.dts
@@ -1,3 +1,5 @@
+#include <dt-bindings/leds/common.h>
+
 #include "falcon.dtsi"
 #include "falcon_sflash-16m.dtsi"
 
@@ -47,7 +49,8 @@
 			gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
 		};
 		STATUS {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
 		};
 		ERROR {
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy88444.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy88444.dts
index d6591aa10e9a31..65e2f9b5eab6ab 100644
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy88444.dts
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy88444.dts
@@ -1,3 +1,5 @@
+#include <dt-bindings/leds/common.h>
+
 #include "falcon.dtsi"
 #include "falcon_sflash-16m.dtsi"
 
@@ -46,7 +48,8 @@
 			gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
 		};
 		STATUS {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
 		};
 
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000.dtsi
index e25145d86937f8..eb2c42c7c6781e 100644
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000.dtsi
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000.dtsi
@@ -1,3 +1,5 @@
+#include <dt-bindings/leds/common.h>
+
 #include "falcon.dtsi"
 
 #include <dt-bindings/interrupt-controller/irq.h>
@@ -42,7 +44,8 @@
 			default-state = "keep";
 		};
 		LED_5 {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
 			default-state = "keep";
 		};
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98020-v18.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98020-v18.dts
index bad808e9bf4786..b5d6d020938b5b 100644
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98020-v18.dts
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98020-v18.dts
@@ -1,3 +1,5 @@
+#include <dt-bindings/leds/common.h>
+
 #include "falcon.dtsi"
 #include "falcon_sflash-16m.dtsi"
 
@@ -48,7 +50,8 @@
 			default-state = "keep";
 		};
 		ETH {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
 			default-state = "keep";
 		};
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98020.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98020.dts
index 2c0a51aa7be5ef..05d6e9eae89706 100644
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98020.dts
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98020.dts
@@ -1,3 +1,5 @@
+#include <dt-bindings/leds/common.h>
+
 #include "falcon.dtsi"
 #include "falcon_sflash-16m.dtsi"
 
@@ -48,7 +50,8 @@
 			default-state = "keep";
 		};
 		ETH {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
 			default-state = "keep";
 		};
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98021.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98021.dts
index 2cc70e6e40e96c..11b86cd7e13b4e 100644
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98021.dts
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98021.dts
@@ -1,3 +1,5 @@
+#include <dt-bindings/leds/common.h>
+
 #include "falcon.dtsi"
 #include "falcon_sflash-16m.dtsi"
 
@@ -60,7 +62,8 @@
 			default-state = "keep";
 		};
 		ETH {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
 			default-state = "keep";
 		};
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_falcon-mdu.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_falcon-mdu.dts
index 611b02f8b3ef70..c6972365972ef1 100644
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_falcon-mdu.dts
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_falcon-mdu.dts
@@ -1,3 +1,5 @@
+#include <dt-bindings/leds/common.h>
+
 #include "falcon.dtsi"
 #include "falcon_sflash-16m.dtsi"
 
@@ -27,7 +29,8 @@
 			default-state = "keep";
 		};
 		LED_1 {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>;
 			default-state = "keep";
 		};
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_alphanetworks_asl56026.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_alphanetworks_asl56026.dts
index 77fcff33920eea..eac6b0792dce19 100644
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_alphanetworks_asl56026.dts
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_alphanetworks_asl56026.dts
@@ -1,6 +1,7 @@
 #include "vr9.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/mips/lantiq_rcu_gphy.h>
 
 / {
@@ -46,13 +47,15 @@
 
 		/* power-* is a bicolour led */
 		power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
 			default-state = "keep";
 		};
 
 		power_red: power_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 18 GPIO_ACTIVE_HIGH>;
 		};
 	};
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_arv7519rw22.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_arv7519rw22.dts
index 935aa08cb90605..9107624eb17cf3 100644
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_arv7519rw22.dts
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_arv7519rw22.dts
@@ -1,6 +1,7 @@
 #include "vr9.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/mips/lantiq_rcu_gphy.h>
 
 / {
@@ -50,7 +51,8 @@
 		compatible = "gpio-leds";
 
 		lan_green {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
 		};
 		internet_red {
@@ -58,12 +60,14 @@
 			gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
 		};
 		power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 			default-state = "keep";
 		};
 		alarm_blue {
-			label = "blue:alarm";
+			function = LED_FUNCTION_ALARM;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 		};
 		internet_orange {
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vg3503j.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vg3503j.dts
index fb771edcb7e65d..9238fba5d63967 100644
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vg3503j.dts
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vg3503j.dts
@@ -1,6 +1,7 @@
 #include "vr9.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/mips/lantiq_rcu_gphy.h>
 
 / {
@@ -39,7 +40,8 @@
 		compatible = "gpio-leds";
 
 		power_red: power2 {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		};
 		dsl: dsl {
@@ -47,7 +49,8 @@
 			gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
 		};
 		power_green: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 28 GPIO_ACTIVE_LOW>;
 			default-state = "keep";
 		};
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22.dtsi
index 69685d801b8218..90d11c991dc430 100644
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22.dtsi
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22.dtsi
@@ -1,6 +1,7 @@
 #include "vr9.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/mips/lantiq_rcu_gphy.h>
 
 / {
@@ -62,7 +63,8 @@
 		};
 
 		power_green: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 			default-state = "keep";
 		};
@@ -78,13 +80,15 @@
 		};
 
 		wifi: wifi {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 20 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
 
 		power_red: power2 {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 28 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519.dtsi
index 71046cfd58c68a..e0bcaa951b31e7 100644
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519.dtsi
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519.dtsi
@@ -1,6 +1,7 @@
 #include "vr9.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/mips/lantiq_rcu_gphy.h>
 
 / {
@@ -59,11 +60,13 @@
 			gpios = <&stp 2 GPIO_ACTIVE_LOW>;
 		};
 		wps_red {
-			label = "red:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&stp 3 GPIO_ACTIVE_LOW>;
 		};
 		wps_green {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&stp 4 GPIO_ACTIVE_LOW>;
 		};
 		upgrade {
@@ -103,12 +106,14 @@
 			gpios = <&stp 13 GPIO_ACTIVE_LOW>;
 		};
 		power_green: power2 {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&stp 14 GPIO_ACTIVE_LOW>;
 			default-state = "keep";
 		};
 		power_red: power {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&stp 15 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vrv9510kwac23.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vrv9510kwac23.dts
new file mode 100644
index 00000000000000..4837223813ff08
--- /dev/null
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vrv9510kwac23.dts
@@ -0,0 +1,361 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "vr9.dtsi"
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/mips/lantiq_rcu_gphy.h>
+
+/ {
+	compatible = "arcadyan,vrv9510kwac23", "lantiq,xway", "lantiq,vr9";
+	model = "Arcadyan VRV9510KWAC23";
+	chosen {
+		bootargs = "console=ttyLTQ0,115200 mem=254M vpe1_load_addr=0x8fe00000 vpe1_mem=2M maxvpes=1 maxtcs=1 nosmp";
+	};
+
+	aliases {
+		led-boot = &power_green;
+		led-failsafe = &upgrade;
+		led-running = &power_green;
+		led-upgrade = &power_green;
+		led-internet = &internet_green;
+		led-wifi = &wireless_green;
+	};
+
+	bcm43222-sprom {
+		compatible = "brcm,ssb-sprom";
+
+		pci-bus = <0>;
+		pci-dev = <14>;
+
+		nvmem-cells = <&macaddr_boardconfig_16 1>;
+		nvmem-cell-names = "mac-address";
+
+		brcm,sprom = "brcm/bcm43222-sprom.bin";
+		brcm,sprom-fixups = <2   0x04d2>, 
+				    <65  0x1308>, <68  0x0402>,
+				    <70  0x1cc6>, <71  0x3c49>,
+				    <72  0x1132>, <87  0x0315>,
+				    <88  0x0315>, <96  0x2048>,
+				    <97  0xfeed>, <98  0x153e>,
+				    <99  0xfb1f>, <100 0x3e54>,
+				    <101 0x3848>, <102 0xfea0>, 
+				    <103 0x145c>, <104 0xfaf0>,
+				    <105 0xfe6e>, <106 0x110c>,
+				    <107 0xfb7e>, <108 0xff00>,
+				    <109 0x13c4>, <110 0xfb30>, 
+				    <111 0x0000>, <112 0x204c>, 
+				    <113 0xfeb8>, <114 0x1508>, 
+				    <115 0xfacb>, <116 0x3e48>,
+				    <117 0x3848>, <118 0xfeb2>, 
+				    <119 0x156e>, <120 0xfabf>, 
+				    <121 0xfe57>, <122 0x1139>,
+				    <123 0xfb6d>, <124 0xff38>,
+				    <125 0x13ee>, <126 0xfb6d>,
+				    <127 0x0000>, <161 0x0000>,
+				    <162 0x0000>, <169 0x0000>,
+				    <170 0x0000>, <171 0x0000>,
+				    <172 0x0000>, <173 0x0000>,
+				    <174 0x0000>, <175 0x0000>,
+				    <176 0x0000>, <219 0x1108>,
+				    <127 0x0000>, <161 0x0000>,
+				    <162 0x0000>, <169 0x0000>,
+				    <170 0x0000>, <171 0x0000>,
+				    <172 0x0000>, <173 0x0000>,
+				    <174 0x0000>, <175 0x0000>,
+				    <176 0x0000>, <219 0x1108>;
+	};
+
+	bcm4360-sprom {
+		compatible = "brcm,bcma-sprom";
+
+		pci-bus = <2>;
+		pci-dev = <0>;
+
+		nvmem-cells = <&macaddr_boardconfig_16 1>;
+		nvmem-cell-names = "mac-address";
+
+		brcm,sprom = "brcm/bcm4360-sprom.bin";
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x10000000>;
+	};
+
+	keys {
+		compatible = "gpio-keys-polled";
+		poll-interval = <100>;
+
+		reset {
+			label = "reset";
+			gpios = <&gpio 20 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+		wps {
+			label = "wps";
+			gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WPS_BUTTON>;
+		};
+		rfkill {
+			label = "rfkill";
+			gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RFKILL>;
+		};
+		service {
+			label = "service";
+			gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
+			linux,code = <BTN_0>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		// from top to bottom
+		power_green: power {
+			gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_POWER;
+		};
+		internet_green: internet_green {
+			gpios = <&gpio 26 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_WAN;
+		};
+		internet_red {
+			gpios = <&gpio 33 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_RED>;
+			function = LED_FUNCTION_FAULT;
+		};
+		phone {
+			gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_GREEN>;
+		};
+		lan {
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio 45 GPIO_ACTIVE_LOW>;
+			function = LED_FUNCTION_LAN;
+		};
+		wireless_blue {
+			gpios = <&gpio 40 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_BLUE>;
+		};
+		wireless_green: wireless_green {
+			gpios = <&gpio 47 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_WLAN;
+		};
+		upgrade: upgrade {
+			gpios = <&gpio 41 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_BLUE>;
+		};
+	};
+
+	usb_vbus: regulator-usb-vbus {
+		compatible = "regulator-fixed";
+
+		regulator-name = "USB_VBUS";
+
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+
+		gpio = <&gpio 32 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+};
+
+&localbus {
+	flash@0 {
+		compatible = "lantiq,nand-xway";
+		lantiq,cs = <1>;
+		bank-width = <2>;
+		reg = <0 0x0 0x2000000>;
+
+		pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>;
+		pinctrl-names = "default";
+
+		nand-use-soft-ecc-engine;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "uboot";
+				reg = <0x00000 0x80000>;
+				read-only;
+			};
+			partition@80000 {
+				label = "u-boot-env";
+				reg = <0x80000 0x20000>;
+			};
+			partition@a0000 {
+				label = "kernel";
+				reg = <0xa0000 0x400000>;
+			};
+			partition@540000 {
+				label = "ubi";
+				reg = <0x4a0000 0x7a00000>;
+			};
+			boardconfig: partition@7ea0000 {
+				label = "board_config";
+				reg = <0x7ea0000 0x1000>;
+				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					macaddr_boardconfig_16: macaddr@16 {
+						compatible = "mac-base";
+						reg = <0x16 0x6>;
+						#nvmem-cell-cells = <1>;
+					};
+				};
+			};
+		};
+	};
+};
+
+&eth0 {
+	nvmem-cells = <&macaddr_boardconfig_16 0>;
+	nvmem-cell-names = "mac-address";
+};
+
+&gphy0 {
+	lantiq,gphy-mode = <GPHY_MODE_GE>;
+};
+
+&gphy1 {
+	lantiq,gphy-mode = <GPHY_MODE_GE>;
+};
+
+&gpio {
+	pinctrl-names = "default";
+	pinctrl-0 = <&state_default>;
+
+	state_default: pinmux {
+		pci_rst {
+			lantiq,pins = "io21";
+			lantiq,output = <1>;
+			lantiq,open-drain = <0>;
+			lantiq,pull = <2>;
+		};
+		pcie_rst {
+			lantiq,pins = "io25";
+			lantiq,output = <1>;
+			lantiq,open-drain = <0>;
+			lantiq,pull = <2>;
+		};
+		usb_vbus {
+			lantiq,pins = "io32";
+			lantiq,output = <1>;
+			lantiq,open-drain = <0>;
+			lantiq,pull = <2>;
+		};
+	};
+};
+
+&gswip {
+	pinctrl-0 = <&mdio_pins>;
+	pinctrl-names = "default";
+};
+
+&gswip_mdio {
+	phy0: ethernet-phy@0 {
+		reg = <0x0>;
+	};
+	phy1: ethernet-phy@1 {
+		reg = <0x1>;
+	};
+	phy5: ethernet-phy@5 {
+		reg = <0x5>;
+	};
+	phy11: ethernet-phy@11 {
+		reg = <0x11>;
+	};
+	phy13: ethernet-phy@13 {
+		reg = <0x13>;
+	};
+};
+
+&gswip_ports {
+	port@0 {
+		reg = <0>;
+		label = "lan3";
+		phy-mode = "rgmii-id";
+		tx-internal-delay-ps = <1500>;
+		rx-internal-delay-ps = <1500>;
+		phy-handle = <&phy0>;
+	};
+	port@1 {
+		reg = <1>;
+		label = "lan2";
+		phy-mode = "rgmii-id";
+		tx-internal-delay-ps = <1500>;
+		rx-internal-delay-ps = <1500>;
+		phy-handle = <&phy1>;
+	};
+	port@2 {
+		reg = <2>;
+		label = "lan1";
+		phy-mode = "internal";
+		phy-handle = <&phy11>;
+	};
+	port@4 {
+		reg = <4>;
+		label = "wan";
+		phy-mode = "internal";
+		phy-handle = <&phy13>;
+	};
+	port@5 {
+		reg = <5>;
+		label = "lan4";
+		phy-mode = "rgmii-id";
+		tx-internal-delay-ps = <1500>;
+		rx-internal-delay-ps = <1500>;
+		phy-handle = <&phy5>;
+	};
+};
+
+&pci0 {
+	status = "okay";
+
+	pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>;
+	pinctrl-names = "default";
+
+	gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;
+};
+
+&pcie0 {
+	status = "okay";
+
+	gpio-reset = <&gpio 25 GPIO_ACTIVE_HIGH>;
+};
+
+&usb_phy0 {
+	status = "okay";
+};
+
+&usb_phy1 {
+	status = "okay";
+};
+
+&usb0 {
+	status = "okay";
+	vbus-supply = <&usb_vbus>;
+};
+
+&usb1 {
+	status = "okay";
+	vbus-supply = <&usb_vbus>;
+};
+
+&vmmc {
+	status = "okay";
+	gpios = <&gpio 30 GPIO_ACTIVE_HIGH  //fxs relay
+		 &gpio 31 GPIO_ACTIVE_HIGH  //still unknown
+		 &gpio 3  GPIO_ACTIVE_HIGH>; //reset_slic?
+};
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2.dtsi
index 664327a861204c..4c9b073b70de77 100644
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2.dtsi
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2.dtsi
@@ -1,6 +1,7 @@
 #include "vr9.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/mips/lantiq_rcu_gphy.h>
 
 / {
@@ -53,13 +54,15 @@
 		compatible = "gpio-leds";
 
 		power_green: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 32 GPIO_ACTIVE_LOW>;
 			default-state = "keep";
 		};
 
 		power_red: power2 {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 33 GPIO_ACTIVE_LOW>;
 		};
 
@@ -69,7 +72,8 @@
 		};
 
 		wifi: wifi {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 35 GPIO_ACTIVE_LOW>;
 		};
 
@@ -79,7 +83,8 @@
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz3390.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz3390.dts
index ba88a812706d35..aef33f2f091cbb 100644
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz3390.dts
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz3390.dts
@@ -3,6 +3,7 @@
 #include "vr9.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/mips/lantiq_rcu_gphy.h>
 
 / {
@@ -50,13 +51,15 @@
 		compatible = "gpio-leds";
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 45 GPIO_ACTIVE_LOW>;
 			default-state = "keep";
 		};
 
 		led_power_red: power_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
 		};
 
@@ -71,7 +74,8 @@
 		};
 
 		led_lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 47 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz3490-micron.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz3490-micron.dts
new file mode 100644
index 00000000000000..b122c04bc057b7
--- /dev/null
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz3490-micron.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "vr9_avm_fritz3490.dtsi"
+
+/ {
+	compatible = "avm,fritz3490-micron", "lantiq,xway", "lantiq,vr9";
+	model = "AVM FRITZ!Box 3490 (Micron NAND)";
+};
+
+&nand1 {
+	nand-ecc-engine = <&nand1>;
+};
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz3490.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz3490.dts
new file mode 100644
index 00000000000000..d795a0b6eb1ac3
--- /dev/null
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz3490.dts
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "vr9_avm_fritz3490.dtsi"
+
+/ {
+	compatible = "avm,fritz3490", "lantiq,xway", "lantiq,vr9";
+	model = "AVM FRITZ!Box 3490";
+};
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz3490.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz3490.dtsi
new file mode 100644
index 00000000000000..fabc56a5aca4c1
--- /dev/null
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz3490.dtsi
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include <dt-bindings/leds/common.h>
+
+#include "vr9_avm_fritzxx90.dtsi"
+
+/ {
+	compatible = "avm,fritz3490", "lantiq,xway", "lantiq,vr9";
+	model = "AVM FRITZ!Box 3490";
+};
+
+&aliases {
+	led-dsl = &led_info_green;
+	led-internet = &led_internet;
+	led-wifi = &led_wifi;
+};
+
+&leds {
+	led_lan: lan {
+		function = LED_FUNCTION_LAN;
+		color = <LED_COLOR_ID_GREEN>;
+		gpios = <&gpio 47 GPIO_ACTIVE_LOW>;
+	};
+
+	led_wifi: wifi {
+		function = LED_FUNCTION_WLAN;
+		color = <LED_COLOR_ID_GREEN>;
+		gpios = <&gpio 36 GPIO_ACTIVE_LOW>;
+	};
+
+	led_internet: internet {
+		label = "green:internet";
+		gpios = <&gpio 35 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&gswip_mdio {
+	phy0: ethernet-phy@0 {
+		reg = <0x00>;
+		reset-gpios = <&gpio 32 GPIO_ACTIVE_LOW>;
+	};
+
+	phy1: ethernet-phy@1 {
+		reg = <0x01>;
+		reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
+	};
+
+	phy11: ethernet-phy@11 {
+		reg = <0x11>;
+	};
+
+	phy13: ethernet-phy@13 {
+		reg = <0x13>;
+	};
+};
+
+&gswip_ports {
+	port@0 {
+		reg = <0>;
+		label = "lan3";
+		phy-mode = "rgmii-rxid";
+		phy-handle = <&phy0>;
+	};
+
+	port@1 {
+		reg = <1>;
+		label = "lan4";
+		phy-mode = "rgmii-rxid";
+		phy-handle = <&phy1>;
+	};
+
+	port@2 {
+		reg = <2>;
+		label = "lan2";
+		phy-mode = "internal";
+		phy-handle = <&phy11>;
+	};
+
+	port@4 {
+		reg = <4>;
+		label = "lan1";
+		phy-mode = "internal";
+		phy-handle = <&phy13>;
+	};
+};
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz5490-micron.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz5490-micron.dts
new file mode 100644
index 00000000000000..18bb81d0b2591f
--- /dev/null
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz5490-micron.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "vr9_avm_fritz5490.dtsi"
+
+/ {
+	compatible = "avm,fritz5490-micron", "lantiq,xway", "lantiq,vr9";
+	model = "AVM FRITZ!Box 5490/5491 (Micron NAND)";
+};
+
+&nand1 {
+	nand-ecc-engine = <&nand1>;
+};
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz5490.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz5490.dts
new file mode 100644
index 00000000000000..631e8390f60912
--- /dev/null
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz5490.dts
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "vr9_avm_fritz5490.dtsi"
+
+/ {
+	compatible = "avm,fritz5490", "lantiq,xway", "lantiq,vr9";
+	model = "AVM FRITZ!Box 5490/5491";
+};
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz5490.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz5490.dtsi
new file mode 100644
index 00000000000000..b38ac9f8b84a7d
--- /dev/null
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz5490.dtsi
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include <dt-bindings/leds/common.h>
+
+#include "vr9_avm_fritzxx90.dtsi"
+
+/ {
+	compatible = "avm,fritz5490", "lantiq,xway", "lantiq,vr9";
+	model = "AVM FRITZ!Box 5490/5491";
+};
+
+&aliases {
+	led-dsl = &led_info_green;
+	led-internet = &led_internet;
+	led-wifi = &led_wifi;
+};
+
+&leds {
+	led_fiber: fiber {
+		label = "green:fiber";
+		gpios = <&gpio 47 GPIO_ACTIVE_LOW>;
+	};
+
+	led_wifi: wifi {
+		function = LED_FUNCTION_WLAN;
+		color = <LED_COLOR_ID_GREEN>;
+		gpios = <&gpio 36 GPIO_ACTIVE_LOW>;
+	};
+
+	led_internet: internet {
+		label = "green:internet";
+		gpios = <&gpio 35 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&gswip_mdio {
+	phy5: ethernet-phy@5 {
+		reg = <0x05>;
+	};
+
+	phy6: ethernet-phy@6 {
+		reg = <0x06>;
+		reset-gpios = <&gpio 32 GPIO_ACTIVE_LOW>;
+	};
+
+	phy9: ethernet-phy@9 {
+		reg = <0x09>;
+	};
+};
+
+&gswip_ports {
+	port@0 {
+		reg = <0>;
+		label = "wan";
+		phy-mode = "rgmii";
+		phy-handle = <&phy6>;
+	};
+
+	port@2 {
+		reg = <2>;
+		label = "lan2";
+		phy-mode = "internal";
+		phy-handle = <&phy5>;
+	};
+
+	port@4 {
+		reg = <4>;
+		label = "lan1";
+		phy-mode = "internal";
+		phy-handle = <&phy9>;
+	};
+};
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz736x.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz736x.dtsi
index 7324127d2a8ece..e7fc9a4f55b7b4 100644
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz736x.dtsi
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz736x.dtsi
@@ -3,6 +3,7 @@
 #include "vr9.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/mips/lantiq_rcu_gphy.h>
 
 / {
@@ -48,13 +49,15 @@
 		compatible = "gpio-leds";
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 32 GPIO_ACTIVE_LOW>;
 			default-state = "keep";
 		};
 
 		led_power_red: power_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 33 GPIO_ACTIVE_LOW>;
 		};
 
@@ -64,7 +67,8 @@
 		};
 
 		led_wifi: wifi {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 36 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz7412.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz7412.dts
index 11f318db5de710..e831af186defc5 100644
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz7412.dts
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz7412.dts
@@ -3,6 +3,7 @@
 #include "vr9.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/mips/lantiq_rcu_gphy.h>
 
 / {
@@ -49,13 +50,15 @@
 		compatible = "gpio-leds";
 
 		power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
 			default-state = "keep";
 		};
 
 		power_red: power_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz7430.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz7430.dts
index 7bc64b76e7c860..cbfa7ebe48f6de 100644
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz7430.dts
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz7430.dts
@@ -3,6 +3,7 @@
 #include "vr9.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/mips/lantiq_rcu_gphy.h>
 
 / {
@@ -49,7 +50,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 31 GPIO_ACTIVE_LOW>;
 			default-state = "keep";
 		};
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz7490-micron.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz7490-micron.dts
new file mode 100644
index 00000000000000..8d763788a0498f
--- /dev/null
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz7490-micron.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "vr9_avm_fritz7490.dtsi"
+
+/ {
+	compatible = "avm,fritz7490-micron", "lantiq,xway", "lantiq,vr9";
+	model = "AVM FRITZ!Box 7490 (Micron NAND)";
+};
+
+&nand1 {
+	nand-ecc-engine = <&nand1>;
+};
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz7490.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz7490.dts
new file mode 100644
index 00000000000000..cccefeaf41ea74
--- /dev/null
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz7490.dts
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "vr9_avm_fritz7490.dtsi"
+
+/ {
+	compatible = "avm,fritz7490", "lantiq,xway", "lantiq,vr9";
+	model = "AVM FRITZ!Box 7490";
+};
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz7490.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz7490.dtsi
new file mode 100644
index 00000000000000..0c682dba3a4475
--- /dev/null
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz7490.dtsi
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include <dt-bindings/leds/common.h>
+
+#include "vr9_avm_fritzxx90.dtsi"
+
+/ {
+	compatible = "avm,fritz7490", "lantiq,xway", "lantiq,vr9";
+	model = "AVM FRITZ!Box 7490";
+};
+
+&aliases {
+	led-dsl = &led_info_green;
+	led-internet = &led_internet;
+	led-wifi = &led_wifi;
+};
+
+&leds {
+	led_internet: internet {
+		label = "green:internet";
+		gpios = <&gpio 47 GPIO_ACTIVE_LOW>;
+	};
+
+	led_fon: fon {
+		label = "green:fon";
+		gpios = <&gpio 36 GPIO_ACTIVE_LOW>;
+	};
+
+	led_wifi: wifi {
+		function = LED_FUNCTION_WLAN;
+		color = <LED_COLOR_ID_GREEN>;
+		gpios = <&gpio 35 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&gswip_mdio {
+	phy0: ethernet-phy@0 {
+		reg = <0x00>;
+		reset-gpios = <&gpio 32 GPIO_ACTIVE_LOW>;
+	};
+
+	phy1: ethernet-phy@1 {
+		reg = <0x01>;
+		reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
+	};
+
+	phy11: ethernet-phy@11 {
+		reg = <0x11>;
+	};
+
+	phy13: ethernet-phy@13 {
+		reg = <0x13>;
+	};
+};
+
+&gswip_ports {
+	port@0 {
+		reg = <0>;
+		label = "lan3";
+		phy-mode = "rgmii-rxid";
+		phy-handle = <&phy0>;
+	};
+
+	port@1 {
+		reg = <1>;
+		label = "lan4";
+		phy-mode = "rgmii-rxid";
+		phy-handle = <&phy1>;
+	};
+
+	port@2 {
+		reg = <2>;
+		label = "lan2";
+		phy-mode = "internal";
+		phy-handle = <&phy11>;
+	};
+
+	port@4 {
+		reg = <4>;
+		label = "lan1";
+		phy-mode = "internal";
+		phy-handle = <&phy13>;
+	};
+};
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritzxx90.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritzxx90.dtsi
new file mode 100644
index 00000000000000..0a2027fb74f526
--- /dev/null
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritzxx90.dtsi
@@ -0,0 +1,176 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "vr9.dtsi"
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/mips/lantiq_rcu_gphy.h>
+
+/ {
+	chosen {
+		bootargs = "console=ttyLTQ0,115200";
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x10000000>;
+	};
+
+	aliases: aliases {
+		led-boot = &led_power_green;
+		led-failsafe = &led_info_red;
+		led-running = &led_power_green;
+		led-upgrade = &led_info_red;
+	};
+
+	keys {
+		compatible = "gpio-keys-polled";
+		poll-interval = <100>;
+
+		power {
+			label = "power";
+			gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_POWER>;
+		};
+
+		wifi {
+			label = "wifi";
+			gpios = <&gpio 29 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RFKILL>;
+		};
+	};
+
+	leds: leds {
+		compatible = "gpio-leds";
+
+		led_power_green: power_green {
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio 45 GPIO_ACTIVE_LOW>;
+			default-state = "keep";
+		};
+
+		led_info_green: info_green {
+			label = "green:info";
+			gpios = <&gpio 33 GPIO_ACTIVE_LOW>;
+		};
+
+		led_info_red: info_red {
+			label = "red:info";
+			gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&gphy0 {
+	lantiq,gphy-mode = <GPHY_MODE_GE>;
+};
+
+&gphy1 {
+	lantiq,gphy-mode = <GPHY_MODE_GE>;
+};
+
+&gpio {
+	pinctrl-names = "default";
+	pinctrl-0 = <&state_default>;
+	gpio-ranges = <&gpio 0 0 56>;
+
+	state_default: pinmux {
+		phy-rst {
+			lantiq,pins = "io32", "io44";
+			lantiq,pull = <0>;
+			lantiq,open-drain;
+			lantiq,output = <1>;
+		};
+
+		pcie-rst {
+			lantiq,pins = "io21";
+			lantiq,open-drain;
+			lantiq,output = <1>;
+		};
+	};
+
+	usb-vbus {
+		gpio-hog;
+		line-name = "usb-vbus";
+		gpios = <14 GPIO_ACTIVE_HIGH>;
+		output-high;
+	};
+
+	pcie-enable-dev {
+		gpio-hog;
+		line-name = "pcie-enable-dev";
+		gpios = <22 GPIO_ACTIVE_LOW>;
+		output-low;
+	};
+};
+
+&gswip {
+	pinctrl-0 = <&mdio_pins>;
+	pinctrl-names = "default";
+};
+
+&spi {
+	status = "okay";
+
+	flash@4 {
+		compatible = "jedec,spi-nor";
+		reg = <4>;
+		spi-max-frequency = <10000000>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			urlader: partition@0 {
+				reg = <0x0 0x40000>;
+				label = "urlader";
+				read-only;
+			};
+
+			partition@40000 {
+				reg = <0x40000 0x60000>;
+				label = "tffs (1)";
+				read-only;
+			};
+
+			partition@a0000 {
+				reg = <0xa0000 0x60000>;
+				label = "tffs (2)";
+				read-only;
+			};
+		};
+	};
+};
+
+&localbus {
+	nand1: nand@1 {
+		compatible = "lantiq,nand-xway";
+		bank-width = <2>;
+		reg = <0x1 0x0 0x2000000>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "kernel";
+				reg = <0x0 0x400000>;
+			};
+
+			partition@400000 {
+				label = "ubi";
+				reg = <0x400000 0x1fc00000>;
+			};
+		};
+	};
+};
+
+&pcie0 {
+	status = "okay";
+
+	gpio-reset = <&gpio 21 GPIO_ACTIVE_LOW>;
+	lantiq,switch-pcie-endianess;
+};
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_bt_homehub-v5a.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_bt_homehub-v5a.dts
index be44cb716197e2..dc43b3a99416d9 100644
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_bt_homehub-v5a.dts
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_bt_homehub-v5a.dts
@@ -1,6 +1,7 @@
 #include "vr9.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/mips/lantiq_rcu_gphy.h>
 
 / {
@@ -82,16 +83,19 @@
 
 		/* power-* is a single RGB led */
 		power_red: power-red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
 		};
 		power_green: power-green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 			default-state = "keep";
 		};
 		power_blue: power-blue {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_buffalo_wbmr-300hpd.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_buffalo_wbmr-300hpd.dts
index eea27a2a1f31ea..31bbfc67cc9825 100644
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_buffalo_wbmr-300hpd.dts
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_buffalo_wbmr-300hpd.dts
@@ -1,6 +1,7 @@
 #include "vr9.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/mips/lantiq_rcu_gphy.h>
 
 / {
@@ -104,7 +105,8 @@
 		};
 
 		wan: wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 12 GPIO_ACTIVE_HIGH>;
 		};
 
@@ -134,7 +136,8 @@
 		};
 
 		power_g: power_g {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 49 GPIO_ACTIVE_HIGH>;
 		};
 	};
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_lantiq_easy80920.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_lantiq_easy80920.dtsi
index 8df81111fa2db4..a8b5f25810f1ad 100644
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_lantiq_easy80920.dtsi
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_lantiq_easy80920.dtsi
@@ -1,6 +1,7 @@
 #include "vr9.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/mips/lantiq_rcu_gphy.h>
 
 / {
@@ -41,7 +42,8 @@
 		compatible = "gpio-leds";
 
 		power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&stp 9 GPIO_ACTIVE_HIGH>;
 			default-state = "keep";
 		};
@@ -75,11 +77,13 @@
 			linux,default-trigger = "usbport";
 		};
 		sd {
-			label = "green:sd";
+			function = LED_FUNCTION_SD;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&stp 14 GPIO_ACTIVE_HIGH>;
 		};
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&stp 12 GPIO_ACTIVE_HIGH>;
 		};
 	};
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_netgear_dm200.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_netgear_dm200.dts
index b817ff3224e98b..e9ba3ad5ee40f1 100644
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_netgear_dm200.dts
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_netgear_dm200.dts
@@ -1,6 +1,7 @@
 #include "vr9.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/mips/lantiq_rcu_gphy.h>
 
 / {
@@ -55,20 +56,24 @@
 		compatible = "gpio-leds";
 
 		power_amber: power_amber {
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
 		};
 		power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
 		};
 
 		lan_amber {
-			label = "amber:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 33 GPIO_ACTIVE_HIGH>;
 		};
 		lan_green {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 11 GPIO_ACTIVE_HIGH>;
 		};
 
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_tdw89x0.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_tdw89x0.dtsi
index 39d7b4908cd46e..d133b5b6d31c8d 100644
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_tdw89x0.dtsi
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_tdw89x0.dtsi
@@ -1,6 +1,7 @@
 #include "vr9.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/mips/lantiq_rcu_gphy.h>
 
 / {
@@ -66,7 +67,8 @@
 		};
 
 		usb0 {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 19 GPIO_ACTIVE_HIGH>;
 			trigger-sources = <&ehci_port1>;
 			linux,default-trigger = "usbport";
@@ -80,7 +82,8 @@
 		};
 
 		led_wps: wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;
 		};
 	};
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dts
index 4ad7a484e6af86..f323b6aa68359a 100644
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dts
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dts
@@ -1,3 +1,5 @@
+#include <dt-bindings/leds/common.h>
+
 #include "vr9_tplink_vr200.dtsi"
 
 / {
@@ -19,7 +21,8 @@
 
 &leds {
 	wps {
-		label = "blue:wps";
+		function = LED_FUNCTION_WPS;
+		color = <LED_COLOR_ID_BLUE>;
 		gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
 	};
 };
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dtsi
index acb54ee80b3172..2160adf7933eca 100644
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dtsi
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dtsi
@@ -1,6 +1,7 @@
 #include "vr9.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/mips/lantiq_rcu_gphy.h>
 
 / {
@@ -48,7 +49,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
 			default-state = "keep";
 		};
@@ -64,19 +66,22 @@
 		};
 
 		usb {
-			label = "blue:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 25 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&ehci_port1>, <&ehci_port2>;
 			linux,default-trigger = "usbport";
 		};
 
 		eth {
-			label = "blue:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 40 GPIO_ACTIVE_LOW>;
 		};
 
 		wlan {
-			label = "blue:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 24 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-fx.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-fx.dtsi
index ff7dce3477abd5..89b7e3e98fbf81 100644
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-fx.dtsi
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-fx.dtsi
@@ -1,6 +1,7 @@
 #include "vr9.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/mips/lantiq_rcu_gphy.h>
 
 / {
@@ -63,19 +64,23 @@
 			gpios = <&stp 19 GPIO_ACTIVE_LOW>;
 		};
 		wireless_orange {
-			label = "orange:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&stp 20 GPIO_ACTIVE_LOW>;
 		};
 		wireless_green: wireless_green {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&stp 21 GPIO_ACTIVE_LOW>;
 		};
 		power_red: power {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&stp 22 GPIO_ACTIVE_LOW>;
 		};
 		power_green: power2 {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&stp 23 GPIO_ACTIVE_LOW>;
 			default-state = "keep";
 		};
diff --git a/target/linux/lantiq/image/vr9.mk b/target/linux/lantiq/image/vr9.mk
index 3c05636f563d0c..a9df6598d79a81 100644
--- a/target/linux/lantiq/image/vr9.mk
+++ b/target/linux/lantiq/image/vr9.mk
@@ -107,6 +107,21 @@ define Device/arcadyan_vgv7519-nor
 endef
 TARGET_DEVICES += arcadyan_vgv7519-nor
 
+define Device/arcadyan_vrv9510kwac23
+  $(Device/dsa-migration)
+  $(Device/NAND)
+  DEVICE_VENDOR := Arcadyan
+  DEVICE_MODEL := VRV9510KWAC23
+  DEVICE_ALT0_VENDOR := Livebox
+  DEVICE_ALT0_MODEL := Next
+  BOARD_NAME := VRV9510KWAC23
+  DEVICE_PACKAGES :=  kmod-b43 wpad-basic-mbedtls broadcom-43222-sprom \
+    broadcom-4360-sprom kmod-usb-dwc2 kmod-ltq-tapi kmod-ltq-vmmc
+  KERNEL_SIZE := 4096k
+  SUPPORTED_DEVICES += arcadyan_vrv9510kwac23
+endef
+TARGET_DEVICES += arcadyan_vrv9510kwac23
+
 define Device/avm_fritz3370
   $(Device/dsa-migration)
   $(Device/AVM)
@@ -149,6 +164,66 @@ define Device/avm_fritz3390
 endef
 TARGET_DEVICES += avm_fritz3390
 
+define Device/avm_fritz3490
+  $(Device/dsa-migration)
+  $(Device/AVM)
+  $(Device/NAND)
+  DEVICE_MODEL := FRITZ!Box 3490
+  DEVICE_VARIANT := Other NAND
+  KERNEL_SIZE := 4096k
+  IMAGE_SIZE := 49152k
+  DEVICE_PACKAGES := kmod-usb3 fritz-tffs -kmod-owl-loader
+endef
+TARGET_DEVICES += avm_fritz3490
+
+define Device/avm_fritz3490-micron
+  $(Device/dsa-migration)
+  $(Device/AVM)
+  $(Device/NAND)
+  DEVICE_MODEL := FRITZ!Box 3490
+  DEVICE_VARIANT := Micron NAND
+  KERNEL_SIZE := 4096k
+  IMAGE_SIZE := 49152k
+  DEVICE_PACKAGES := kmod-usb3 fritz-tffs -kmod-owl-loader
+endef
+TARGET_DEVICES += avm_fritz3490-micron
+
+define Device/avm_fritz5490
+  $(Device/dsa-migration)
+  $(Device/AVM)
+  $(Device/NAND)
+  DEVICE_MODEL := FRITZ!Box 5490
+  DEVICE_ALT0_VENDOR := AVM
+  DEVICE_ALT0_MODEL := FRITZ!Box 5491
+  DEVICE_VARIANT := Other NAND
+  KERNEL_SIZE := 4096k
+  IMAGE_SIZE := 49152k
+  DEVICE_PACKAGES := kmod-usb3 fritz-tffs \
+	-ltq-vdsl-vr9-vectoring-fw-installer -kmod-ltq-vdsl-vr9-mei \
+	-kmod-ltq-vdsl-vr9 -kmod-ltq-atm-vr9 -kmod-ltq-ptm-vr9 \
+	-ltq-vdsl-vr9-app -kmod-owl-loader \
+	-dsl-vrx200-firmware-xdsl-a -dsl-vrx200-firmware-xdsl-b-patch
+endef
+TARGET_DEVICES += avm_fritz5490
+
+define Device/avm_fritz5490-micron
+  $(Device/dsa-migration)
+  $(Device/AVM)
+  $(Device/NAND)
+  DEVICE_MODEL := FRITZ!Box 5490
+  DEVICE_ALT0_VENDOR := AVM
+  DEVICE_ALT0_MODEL := FRITZ!Box 5491
+  DEVICE_VARIANT := Micron NAND
+  KERNEL_SIZE := 4096k
+  IMAGE_SIZE := 49152k
+  DEVICE_PACKAGES := kmod-usb3 fritz-tffs \
+	-ltq-vdsl-vr9-vectoring-fw-installer -kmod-ltq-vdsl-vr9-mei \
+	-kmod-ltq-vdsl-vr9 -kmod-ltq-atm-vr9 -kmod-ltq-ptm-vr9 \
+	-ltq-vdsl-vr9-app -kmod-owl-loader \
+	-dsl-vrx200-firmware-xdsl-a -dsl-vrx200-firmware-xdsl-b-patch
+endef
+TARGET_DEVICES += avm_fritz5490-micron
+
 define Device/avm_fritz7360sl
   $(Device/dsa-migration)
   $(Device/AVM)
@@ -208,6 +283,30 @@ define Device/avm_fritz7430
 endef
 TARGET_DEVICES += avm_fritz7430
 
+define Device/avm_fritz7490
+  $(Device/dsa-migration)
+  $(Device/AVM)
+  $(Device/NAND)
+  DEVICE_MODEL := FRITZ!Box 7490
+  DEVICE_VARIANT := Other NAND
+  KERNEL_SIZE := 4096k
+  IMAGE_SIZE := 49152k
+  DEVICE_PACKAGES := kmod-usb3 fritz-tffs -kmod-owl-loader
+endef
+TARGET_DEVICES += avm_fritz7490
+
+define Device/avm_fritz7490-micron
+  $(Device/dsa-migration)
+  $(Device/AVM)
+  $(Device/NAND)
+  DEVICE_MODEL := FRITZ!Box 7490
+  DEVICE_VARIANT := Micron NAND
+  KERNEL_SIZE := 4096k
+  IMAGE_SIZE := 49152k
+  DEVICE_PACKAGES := kmod-usb3 fritz-tffs -kmod-owl-loader
+endef
+TARGET_DEVICES += avm_fritz7490-micron
+
 define Device/bt_homehub-v5a
   $(Device/dsa-migration)
   $(Device/NAND)
diff --git a/target/linux/lantiq/patches-5.15/0001-MIPS-lantiq-add-pcie-driver.patch b/target/linux/lantiq/patches-5.15/0001-MIPS-lantiq-add-pcie-driver.patch
index bf3d848f41d97f..1c5f69131e438c 100644
--- a/target/linux/lantiq/patches-5.15/0001-MIPS-lantiq-add-pcie-driver.patch
+++ b/target/linux/lantiq/patches-5.15/0001-MIPS-lantiq-add-pcie-driver.patch
@@ -3913,6 +3913,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +#define IFX_RCU_AHB_BE_PCIE_M                    0x00000001  /* Configure AHB master port that connects to PCIe RC in big endian */
 +#define IFX_RCU_AHB_BE_PCIE_S                    0x00000010  /* Configure AHB slave port that connects to PCIe RC in little endian */
 +#define IFX_RCU_AHB_BE_XBAR_M                    0x00000002  /* Configure AHB master port that connects to XBAR in big endian */
++#define IFX_RCU_AHB_BE_XBAR_S                    0x00000008  /* Configure AHB slave port that connects to XBAR in big endian */
 +#define CONFIG_IFX_PCIE_PHY_36MHZ_MODE
 +
 +#define IFX_PMU1_MODULE_PCIE_PHY   (0)
@@ -4159,7 +4160,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +}
 +
 +#endif /* IFXMIPS_PCIE_VR9_H */
-+
 --- a/arch/mips/pci/pci-legacy.c
 +++ b/arch/mips/pci/pci-legacy.c
 @@ -305,3 +305,30 @@ char *__init pcibios_setup(char *str)
diff --git a/target/linux/lantiq/patches-5.15/0151-lantiq-ifxmips_pcie-use-of.patch b/target/linux/lantiq/patches-5.15/0151-lantiq-ifxmips_pcie-use-of.patch
index 0b99b91bd9156a..a11ec3ec98412f 100644
--- a/target/linux/lantiq/patches-5.15/0151-lantiq-ifxmips_pcie-use-of.patch
+++ b/target/linux/lantiq/patches-5.15/0151-lantiq-ifxmips_pcie-use-of.patch
@@ -39,7 +39,7 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
  #include "ifxmips_pcie.h"
  #include "ifxmips_pcie_reg.h"
  
-@@ -40,6 +47,10 @@
+@@ -40,6 +47,11 @@
  static DEFINE_SPINLOCK(ifx_pcie_lock);
  
  u32 g_pcie_debug_flag = PCIE_MSG_ANY & (~PCIE_MSG_CFG);
@@ -47,10 +47,11 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
 +static struct phy *ltq_pcie_phy;
 +static struct reset_control *ltq_pcie_reset;
 +static struct regmap *ltq_rcu_regmap;
++static bool switch_pcie_endianess;
  
  static ifx_pcie_irq_t pcie_irqs[IFX_PCIE_CORE_NR] = {
      {
-@@ -82,6 +93,22 @@ void ifx_pcie_debug(const char *fmt, ...
+@@ -82,6 +94,22 @@ void ifx_pcie_debug(const char *fmt, ...
  	printk("%s", buf);
  }
  
@@ -73,7 +74,7 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
  
  static inline int pcie_ltssm_enable(int pcie_port)
  {
-@@ -988,10 +1015,22 @@ int  ifx_pcie_bios_plat_dev_init(struct
+@@ -988,10 +1016,26 @@ int  ifx_pcie_bios_plat_dev_init(struct
  static int
  pcie_rc_initialize(int pcie_port)
  {
@@ -88,6 +89,10 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
 +#ifdef CONFIG_IFX_PCIE_HW_SWAP
 +	regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_PCIE_S,
 +			   IFX_RCU_AHB_BE_PCIE_S);
++       if (switch_pcie_endianess) {
++	        regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_XBAR_S,
++			           IFX_RCU_AHB_BE_XBAR_S);
++       }
 +#else
 +	regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_PCIE_S,
 +			   0x0);
@@ -98,7 +103,7 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
  
  	pcie_ep_gpio_rst_init(pcie_port);
  
-@@ -1000,26 +1039,21 @@ pcie_rc_initialize(int pcie_port)
+@@ -1000,26 +1044,21 @@ pcie_rc_initialize(int pcie_port)
  	* reset PCIe PHY will solve this issue 
  	*/
  	for (i = 0; i < IFX_PCIE_PHY_LOOP_CNT; i++) {
@@ -135,7 +140,7 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
  
  		/* Enable PCIe PHY and Clock */
  		pcie_core_pmu_setup(pcie_port);
-@@ -1035,6 +1069,10 @@ pcie_rc_initialize(int pcie_port)
+@@ -1035,6 +1074,10 @@ pcie_rc_initialize(int pcie_port)
  		/* Once link is up, break out */
  		if (pcie_app_loigc_setup(pcie_port) == 0)
  			break;
@@ -146,7 +151,7 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
  	}
  	if (i >= IFX_PCIE_PHY_LOOP_CNT) {
  		printk(KERN_ERR "%s link up failed!!!!!\n", __func__);
-@@ -1045,17 +1083,67 @@ pcie_rc_initialize(int pcie_port)
+@@ -1045,17 +1088,74 @@ pcie_rc_initialize(int pcie_port)
  	return 0;
  }
  
@@ -199,6 +204,13 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
 +        return PTR_ERR(ltq_pcie_reset);
 +    }
 +
++    if (of_property_read_bool(node, "lantiq,switch-pcie-endianess")) {
++        switch_pcie_endianess = true;
++        dev_info(&pdev->dev, "switch pcie endianess requested\n");
++    } else {
++        switch_pcie_endianess = false;
++    }
++
 +    ltq_rcu_regmap = syscon_regmap_lookup_by_phandle(node, "lantiq,rcu");
 +    if (IS_ERR(ltq_rcu_regmap))
 +        return PTR_ERR(ltq_rcu_regmap);
@@ -216,7 +228,7 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
      for (pcie_port = startup_port; pcie_port < IFX_PCIE_CORE_NR; pcie_port++){
  	if (pcie_rc_initialize(pcie_port) == 0) {
  	    IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: ifx_pcie_cfg_base 0x%p\n", 
-@@ -1067,6 +1155,7 @@ static int __init ifx_pcie_bios_init(voi
+@@ -1067,6 +1167,7 @@ static int __init ifx_pcie_bios_init(voi
                  return -ENOMEM;
              }
              ifx_pcie_controller[pcie_port].pcic.io_map_base = (unsigned long)io_map_base;
@@ -224,7 +236,7 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
  
              register_pci_controller(&ifx_pcie_controller[pcie_port].pcic);
              /* XXX, clear error status */
-@@ -1083,6 +1172,30 @@ static int __init ifx_pcie_bios_init(voi
+@@ -1083,6 +1184,30 @@ static int __init ifx_pcie_bios_init(voi
  
      return 0;
  }
@@ -266,7 +278,7 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
  #define IFX_REG_R32    ltq_r32
  #define IFX_REG_W32    ltq_w32
  #define CONFIG_IFX_PCIE_HW_SWAP
-@@ -53,21 +51,6 @@
+@@ -54,21 +52,6 @@
  #define OUT			((volatile u32*)(IFX_GPIO + 0x0070))
  
  
@@ -288,7 +300,7 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
  static inline void pcie_ahb_pmu_setup(void) 
  {
  	/* Enable AHB bus master/slave */
-@@ -79,24 +62,6 @@ static inline void pcie_ahb_pmu_setup(vo
+@@ -80,24 +63,6 @@ static inline void pcie_ahb_pmu_setup(vo
      //AHBS_PMU_SETUP(IFX_PMU_ENABLE);
  }
  
@@ -313,7 +325,7 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
  static inline void pcie_phy_pmu_enable(int pcie_port)
  {
  	struct clk *clk;
-@@ -115,17 +80,6 @@ static inline void pcie_phy_pmu_disable(
+@@ -116,17 +81,6 @@ static inline void pcie_phy_pmu_disable(
  //    PCIE_PHY_PMU_SETUP(IFX_PMU_DISABLE);
  }
  
@@ -331,7 +343,7 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
  static inline void pcie_pdi_pmu_enable(int pcie_port)
  {
      /* Enable PDI to access PCIe PHY register */
-@@ -135,65 +89,6 @@ static inline void pcie_pdi_pmu_enable(i
+@@ -136,65 +90,6 @@ static inline void pcie_pdi_pmu_enable(i
      //PDI_PMU_SETUP(IFX_PMU_ENABLE);
  }
  
diff --git a/target/linux/lantiq/xrx200/base-files/etc/board.d/01_leds b/target/linux/lantiq/xrx200/base-files/etc/board.d/01_leds
index 0c80aaa3b8461a..dfc647a43e4b67 100644
--- a/target/linux/lantiq/xrx200/base-files/etc/board.d/01_leds
+++ b/target/linux/lantiq/xrx200/base-files/etc/board.d/01_leds
@@ -31,6 +31,10 @@ arcadyan,vgv7510kw22-nor|\
 arcadyan,vgv7510kw22-brn)
 	ucidef_set_led_netdev "internet" "internet" "$led_internet" "wan"
 	;;
+arcadyan,vrv9510kwac23)
+	ucidef_set_led_netdev "lan" "lan" "green:lan" "eth0"
+	ucidef_set_led_wlan "wifi" "wifi" "green:wlan" "phy1radio"
+	;;
 zyxel,p-2812hnu-f1|\
 zyxel,p-2812hnu-f3)
 	ucidef_set_led_wlan "wifi" "wifi" "green:wlan" "phy0radio"
@@ -41,7 +45,13 @@ arcadyan,vgv7519-brn)
 	;;
 avm,fritz3370-rev2-hynix|\
 avm,fritz3370-rev2-micron|\
-avm,fritz3390)
+avm,fritz3390|\
+avm,fritz3490|\
+avm,fritz3490-micron|\
+avm,fritz5490|\
+avm,fritz5490-micron|\
+avm,fritz7490|\
+avm,fritz7490-micron)
 	ucidef_set_led_switch "lan" "LAN" "green:lan" "switch0" "0x17"
 	;;
 bt,homehub-v5a)
diff --git a/target/linux/lantiq/xrx200/base-files/etc/board.d/02_network b/target/linux/lantiq/xrx200/base-files/etc/board.d/02_network
index 3122d40c92c869..2208752c1423c5 100644
--- a/target/linux/lantiq/xrx200/base-files/etc/board.d/02_network
+++ b/target/linux/lantiq/xrx200/base-files/etc/board.d/02_network
@@ -18,10 +18,15 @@ lantiq_setup_interfaces()
 	arcadyan,arv7519rw22)
 		ucidef_set_interface_lan "lan1 lan2 lan3 lan4 lan5"
 		;;
+	avm,fritz5490|\
+	avm,fritz5490-micron)
+		ucidef_set_interfaces_lan_wan "lan1 lan2" "wan"
+		;;
 	arcadyan,vgv7510kw22-brn|\
 	arcadyan,vgv7510kw22-nor|\
 	arcadyan,vgv7519-brn|\
 	arcadyan,vgv7519-nor|\
+	arcadyan,vrv9510kwac23|\
 	bt,homehub-v5a|\
 	lantiq,easy80920-nand|\
 	lantiq,easy80920-nor|\
@@ -32,10 +37,14 @@ lantiq_setup_interfaces()
 	avm,fritz3370-rev2-hynix|\
 	avm,fritz3370-rev2-micron|\
 	avm,fritz3390|\
+	avm,fritz3490|\
+	avm,fritz3490-micron|\
 	avm,fritz7360sl|\
 	avm,fritz7360-v2|\
 	avm,fritz7362sl|\
 	avm,fritz7430|\
+	avm,fritz7490|\
+	avm,fritz7490-micron|\
 	buffalo,wbmr-300hpd|\
 	tplink,tdw8970|\
 	tplink,tdw8980|\
@@ -64,10 +73,14 @@ lantiq_setup_dsl()
 	avm,fritz3370-rev2-hynix|\
 	avm,fritz3370-rev2-micron|\
 	avm,fritz3390|\
+	avm,fritz3490|\
+	avm,fritz3490-micron|\
 	avm,fritz7360sl|\
 	avm,fritz7362sl|\
 	avm,fritz7412|\
-	avm,fritz7430)
+	avm,fritz7430|\
+	avm,fritz7490|\
+	avm,fritz7490-micron)
 		annex="b"
 		;;
 	esac
@@ -102,7 +115,8 @@ lantiq_setup_macs()
 		wan_mac=$(macaddr_add "$(mtd_get_mac_binary board_config 0x16)" 2)
 		;;
 	arcadyan,vgv7519-brn|\
-	arcadyan,vgv7519-nor)
+	arcadyan,vgv7519-nor|\
+	arcadyan,vrv9510kwac23)
 		wan_mac=$(mtd_get_mac_binary board_config 0x16)
 		;;
 	avm,fritz3370-rev2-hynix|\
@@ -114,7 +128,13 @@ lantiq_setup_macs()
 		wan_mac=$(macaddr_add "$(mtd_get_mac_binary urlader 0xa91)" 1)
 		;;
 	avm,fritz3390|\
-	avm,fritz7362sl)
+	avm,fritz3490|\
+	avm,fritz3490-micron|\
+	avm,fritz5490|\
+	avm,fritz5490-micron|\
+	avm,fritz7362sl|\
+	avm,fritz7490|\
+	avm,fritz7490-micron)
 		lan_mac=$(fritz_tffs -n maca -i $(find_mtd_part "tffs (1)"))
 		wan_mac=$(fritz_tffs -n macdsl -i $(find_mtd_part "tffs (1)"))
 		;;
diff --git a/target/linux/lantiq/xrx200/base-files/lib/upgrade/platform.sh b/target/linux/lantiq/xrx200/base-files/lib/upgrade/platform.sh
index ab01d3bbf723ac..f10030974b1bee 100755
--- a/target/linux/lantiq/xrx200/base-files/lib/upgrade/platform.sh
+++ b/target/linux/lantiq/xrx200/base-files/lib/upgrade/platform.sh
@@ -9,12 +9,19 @@ platform_do_upgrade() {
 	local board=$(board_name)
 
 	case "$board" in
+	arcadyan,vrv9510kwac23|\
 	avm,fritz3370-rev2-hynix|\
 	avm,fritz3370-rev2-micron|\
 	avm,fritz3390|\
+	avm,fritz3490|\
+	avm,fritz3490-micron|\
+	avm,fritz5490|\
+	avm,fritz5490-micron|\
 	avm,fritz7362sl|\
 	avm,fritz7412|\
 	avm,fritz7430|\
+	avm,fritz7490|\
+	avm,fritz7490-micron|\
 	bt,homehub-v5a|\
 	zyxel,p-2812hnu-f1|\
 	zyxel,p-2812hnu-f3)
diff --git a/target/linux/layerscape/Makefile b/target/linux/layerscape/Makefile
index 4ddd348d135ca5..79aa8f14740ee9 100644
--- a/target/linux/layerscape/Makefile
+++ b/target/linux/layerscape/Makefile
@@ -7,8 +7,7 @@ include $(TOPDIR)/rules.mk
 BOARD:=layerscape
 BOARDNAME:=NXP Layerscape
 
-KERNEL_PATCHVER:=5.15
-KERNEL_TESTING_PATCHVER:=6.1
+KERNEL_PATCHVER:=6.1
 
 FEATURES:=squashfs nand usb pcie gpio fpu ubifs ext4 rootfs-part boot-part
 SUBTARGETS:=armv8_64b armv7
diff --git a/target/linux/layerscape/armv7/config-5.15 b/target/linux/layerscape/armv7/config-5.15
deleted file mode 100644
index 121151f58ffbf4..00000000000000
--- a/target/linux/layerscape/armv7/config-5.15
+++ /dev/null
@@ -1,675 +0,0 @@
-CONFIG_AD525X_DPOT=y
-CONFIG_AD525X_DPOT_I2C=y
-# CONFIG_AD525X_DPOT_SPI is not set
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_APDS9802ALS=y
-CONFIG_AQUANTIA_PHY=y
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_MXC=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM=y
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-CONFIG_ARM_ATAG_DTB_COMPAT=y
-CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
-CONFIG_ARM_CPUIDLE=y
-CONFIG_ARM_CPU_SUSPEND=y
-CONFIG_ARM_CRYPTO=y
-CONFIG_ARM_ERRATA_430973=y
-CONFIG_ARM_ERRATA_643719=y
-CONFIG_ARM_ERRATA_720789=y
-CONFIG_ARM_ERRATA_754322=y
-CONFIG_ARM_ERRATA_754327=y
-CONFIG_ARM_ERRATA_764369=y
-CONFIG_ARM_ERRATA_775420=y
-CONFIG_ARM_ERRATA_798181=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_HAS_SG_CHAIN=y
-CONFIG_ARM_HEAVY_MB=y
-# CONFIG_ARM_HIGHBANK_CPUIDLE is not set
-# CONFIG_ARM_IMX8M_DDRC_DEVFREQ is not set
-# CONFIG_ARM_IMX_BUS_DEVFREQ is not set
-# CONFIG_ARM_IMX_CPUFREQ_DT is not set
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-CONFIG_ARM_LPAE=y
-CONFIG_ARM_PATCH_IDIV=y
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_PSCI=y
-CONFIG_ARM_PSCI_FW=y
-# CONFIG_ARM_SMMU is not set
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_THUMBEE=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_ATAGS=y
-CONFIG_AUTOFS4_FS=y
-CONFIG_AUTOFS_FS=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BATTERY_SBS=y
-CONFIG_BCM_NET_PHYLIB=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_DEV_BSG=y
-CONFIG_BLK_DEV_BSG_COMMON=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=262144
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_DEV_SR=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BLK_MQ_VIRTIO=y
-CONFIG_BLK_PM=y
-CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
-CONFIG_BOUNCE=y
-CONFIG_BRCMSTB_GISB_ARB=y
-CONFIG_BROADCOM_PHY=y
-CONFIG_CACHE_L2X0=y
-CONFIG_CDROM=y
-CONFIG_CHECKPOINT_RESTORE=y
-CONFIG_CHR_DEV_SG=y
-CONFIG_CLKSRC_IMX_GPT=y
-CONFIG_CLKSRC_MMIO=y
-# CONFIG_CLK_IMX8MM is not set
-# CONFIG_CLK_IMX8MN is not set
-# CONFIG_CLK_IMX8MP is not set
-# CONFIG_CLK_IMX8MQ is not set
-CONFIG_CLK_QORIQ=y
-# CONFIG_CLK_VEXPRESS_OSC is not set
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMA=y
-CONFIG_CMA_ALIGNMENT=8
-CONFIG_CMA_AREAS=7
-# CONFIG_CMA_DEBUG is not set
-# CONFIG_CMA_DEBUGFS is not set
-CONFIG_CMA_SIZE_MBYTES=64
-# CONFIG_CMA_SIZE_SEL_MAX is not set
-CONFIG_CMA_SIZE_SEL_MBYTES=y
-# CONFIG_CMA_SIZE_SEL_MIN is not set
-# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
-# CONFIG_CMA_SYSFS is not set
-CONFIG_CMDLINE_PARTITION=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_CONTIG_ALLOC=y
-CONFIG_COREDUMP=y
-CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
-CONFIG_CPUFREQ_DT=y
-CONFIG_CPUFREQ_DT_PLATDEV=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
-CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
-# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_SPECTRE=y
-CONFIG_CPU_THERMAL=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRASH_CORE=y
-CONFIG_CRC16=y
-# CONFIG_CRC32_SARWATE is not set
-CONFIG_CRC32_SLICEBY8=y
-CONFIG_CROSS_MEMORY_ATTACH=y
-CONFIG_CRYPTO_CRC32=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_ALIGN_RODATA=y
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-CONFIG_DECOMPRESS_BZIP2=y
-CONFIG_DECOMPRESS_GZIP=y
-CONFIG_DECOMPRESS_LZMA=y
-CONFIG_DECOMPRESS_LZO=y
-CONFIG_DECOMPRESS_XZ=y
-CONFIG_DETECT_HUNG_TASK=y
-# CONFIG_DEVFREQ_GOV_PASSIVE is not set
-# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set
-# CONFIG_DEVFREQ_GOV_POWERSAVE is not set
-# CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND is not set
-# CONFIG_DEVFREQ_GOV_USERSPACE is not set
-# CONFIG_DEVFREQ_THERMAL is not set
-CONFIG_DMADEVICES=y
-CONFIG_DMA_CMA=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_OPS=y
-CONFIG_DMA_REMAP=y
-CONFIG_DMA_SHARED_BUFFER=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DNOTIFY=y
-CONFIG_DTC=y
-CONFIG_DT_IDLE_STATES=y
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_DW_DMAC=y
-CONFIG_DW_DMAC_CORE=y
-CONFIG_DW_WATCHDOG=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EEPROM_93CX6=y
-CONFIG_EEPROM_AT24=y
-CONFIG_ELF_CORE=y
-# CONFIG_ENABLE_DEFAULT_TRACERS is not set
-CONFIG_EXT4_FS=y
-CONFIG_EXT4_FS_POSIX_ACL=y
-CONFIG_EXT4_FS_SECURITY=y
-CONFIG_F2FS_FS=y
-CONFIG_FAILOVER=y
-CONFIG_FAT_FS=y
-# CONFIG_FEC is not set
-CONFIG_FHANDLE=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FORCE_MAX_ZONEORDER=12
-CONFIG_FREEZER=y
-# CONFIG_FSL_DPAA2_SWITCH is not set
-CONFIG_FSL_EDMA=y
-CONFIG_FSL_GUTS=y
-CONFIG_FSL_IFC=y
-# CONFIG_FSL_PPFE is not set
-CONFIG_FSL_PQ_MDIO=y
-CONFIG_FSL_RCPM=y
-CONFIG_FSL_XGMAC_MDIO=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FS_POSIX_ACL=y
-CONFIG_FTRACE=y
-# CONFIG_FTRACE_SYSCALLS is not set
-CONFIG_FUSE_FS=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_CACHE=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MIGRATION=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GENERIC_VDSO_32=y
-CONFIG_GIANFAR=y
-CONFIG_GLOB=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_GENERIC=y
-CONFIG_GPIO_GENERIC_PLATFORM=y
-CONFIG_GPIO_MPC8XXX=y
-CONFIG_GPIO_MXC=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDEN_BRANCH_PREDICTOR=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HAVE_SMP=y
-CONFIG_HID=y
-CONFIG_HID_GENERIC=y
-CONFIG_HIGHMEM=y
-CONFIG_HIGHPTE=y
-# CONFIG_HIST_TRIGGERS is not set
-CONFIG_HOTPLUG_CPU=y
-CONFIG_HVC_DRIVER=y
-CONFIG_HW_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_HZ_FIXED=0
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_COMPAT=y
-CONFIG_I2C_DEMUX_PINCTRL=y
-CONFIG_I2C_DESIGNWARE_CORE=y
-CONFIG_I2C_DESIGNWARE_PLATFORM=y
-CONFIG_I2C_HELPER_AUTO=y
-CONFIG_I2C_IMX=y
-# CONFIG_I2C_IMX_LPI2C is not set
-CONFIG_I2C_MUX=y
-CONFIG_I2C_MUX_PCA954x=y
-CONFIG_I2C_MUX_PINCTRL=y
-CONFIG_I2C_RK3X=y
-CONFIG_I2C_SLAVE=y
-CONFIG_I2C_SLAVE_EEPROM=y
-# CONFIG_I2C_SLAVE_TESTUNIT is not set
-CONFIG_I2C_XILINX=y
-CONFIG_ICPLUS_PHY=y
-CONFIG_ICS932S401=y
-CONFIG_IMX2_WDT=y
-# CONFIG_IMX7ULP_WDT is not set
-# CONFIG_IMX8MM_THERMAL is not set
-CONFIG_IMX_DMA=y
-# CONFIG_IMX_GPCV2_PM_DOMAINS is not set
-CONFIG_IMX_INTMUX=y
-# CONFIG_IMX_IRQSTEER is not set
-CONFIG_IMX_SDMA=y
-# CONFIG_IMX_WEIM is not set
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-# CONFIG_IOMMU_DEBUGFS is not set
-# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
-# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
-CONFIG_IOMMU_SUPPORT=y
-CONFIG_IPC_NS=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-# CONFIG_ISDN is not set
-CONFIG_ISL29003=y
-CONFIG_JBD2=y
-CONFIG_KALLSYMS=y
-CONFIG_KCMP=y
-CONFIG_KERNEL_GZIP=y
-# CONFIG_KERNEL_XZ is not set
-CONFIG_KEXEC=y
-CONFIG_KEXEC_CORE=y
-CONFIG_KMAP_LOCAL=y
-CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
-CONFIG_LIBFDT=y
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LS_EXTIRQ=y
-CONFIG_LS_SCFG_MSI=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MARVELL_PHY=y
-CONFIG_MCPM=y
-CONFIG_MDIO_BITBANG=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-# CONFIG_MDIO_GPIO is not set
-CONFIG_MEMFD_CREATE=y
-CONFIG_MEMORY=y
-CONFIG_MEMORY_ISOLATION=y
-# CONFIG_MFD_HI6421_SPMI is not set
-CONFIG_MFD_SYSCON=y
-# CONFIG_MFD_VEXPRESS_SYSREG is not set
-CONFIG_MICREL_PHY=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_BLOCK_MINORS=16
-# CONFIG_MMC_MXC is not set
-CONFIG_MMC_SDHCI=y
-# CONFIG_MMC_SDHCI_ESDHC_IMX is not set
-CONFIG_MMC_SDHCI_IO_ACCESSORS=y
-CONFIG_MMC_SDHCI_OF_ESDHC=y
-# CONFIG_MMC_SDHCI_PCI is not set
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MSDOS_FS=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_GEOMETRY=y
-CONFIG_MTD_CFI_STAA=y
-CONFIG_MTD_CMDLINE_PARTS=y
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-CONFIG_MTD_DATAFLASH=y
-# CONFIG_MTD_DATAFLASH_OTP is not set
-# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set
-CONFIG_MTD_NAND_CORE=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_ECC_SW_HAMMING=y
-CONFIG_MTD_NAND_FSL_IFC=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
-CONFIG_MTD_SST25L=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-# CONFIG_MTD_UBI_BLOCK is not set
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_MX3_IPU=y
-CONFIG_MX3_IPU_IRQS=4
-CONFIG_MXC_CLK=y
-# CONFIG_MXS_DMA is not set
-CONFIG_NAMESPACES=y
-CONFIG_NATIONAL_PHY=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEON=y
-CONFIG_NET_FAILOVER=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_NS=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NLS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_UTF8=y
-CONFIG_NO_HZ=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=16
-CONFIG_NTFS_FS=y
-CONFIG_NVMEM=y
-# CONFIG_NVMEM_IMX_IIM is not set
-# CONFIG_NVMEM_IMX_OCOTP_ELE is not set
-# CONFIG_NVMEM_SNVS_LPGPR is not set
-# CONFIG_NVMEM_SPMI_SDAM is not set
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_DYNAMIC=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_OUTER_CACHE=y
-CONFIG_OUTER_CACHE_SYNC=y
-CONFIG_PACKET_DIAG=y
-CONFIG_PADATA=y
-CONFIG_PAGE_OFFSET=0xC0000000
-# CONFIG_PANIC_ON_OOPS is not set
-CONFIG_PANIC_ON_OOPS_VALUE=0
-CONFIG_PANIC_TIMEOUT=0
-CONFIG_PCI=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEASPM=y
-CONFIG_PCIEASPM_DEFAULT=y
-# CONFIG_PCIEASPM_PERFORMANCE is not set
-# CONFIG_PCIEASPM_POWERSAVE is not set
-# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_DW=y
-CONFIG_PCIE_DW_HOST=y
-CONFIG_PCIE_PME=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_ECAM=y
-CONFIG_PCI_HOST_COMMON=y
-CONFIG_PCI_HOST_GENERIC=y
-# CONFIG_PCI_IMX6 is not set
-CONFIG_PCI_LAYERSCAPE=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=3
-CONFIG_PHYLIB=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_PID_NS=y
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_IMX8MM is not set
-# CONFIG_PINCTRL_IMX8MN is not set
-# CONFIG_PINCTRL_IMX8MP is not set
-# CONFIG_PINCTRL_IMX8MQ is not set
-# CONFIG_PINCTRL_IMX8ULP is not set
-CONFIG_PL310_ERRATA_588369=y
-CONFIG_PL310_ERRATA_727915=y
-CONFIG_PL310_ERRATA_753970=y
-CONFIG_PL310_ERRATA_769419=y
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_PM_DEVFREQ=y
-# CONFIG_PM_DEVFREQ_EVENT is not set
-CONFIG_PM_OPP=y
-CONFIG_PM_SLEEP=y
-CONFIG_PM_SLEEP_SMP=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_BRCMKONA=y
-CONFIG_POWER_RESET_BRCMSTB=y
-CONFIG_POWER_RESET_GPIO=y
-CONFIG_POWER_RESET_GPIO_RESTART=y
-CONFIG_POWER_RESET_SYSCON=y
-CONFIG_POWER_RESET_SYSCON_POWEROFF=y
-CONFIG_POWER_RESET_VEXPRESS=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PPS=y
-CONFIG_PRINTK_TIME=y
-CONFIG_PROC_CHILDREN=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_PSTORE=y
-CONFIG_PSTORE_COMPRESS=y
-CONFIG_PSTORE_COMPRESS_DEFAULT="deflate"
-CONFIG_PSTORE_CONSOLE=y
-CONFIG_PSTORE_DEFLATE_COMPRESS=y
-CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y
-CONFIG_PSTORE_PMSG=y
-CONFIG_PSTORE_RAM=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PTP_1588_CLOCK_QORIQ=y
-CONFIG_QORIQ_CPUFREQ=y
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-CONFIG_RD_BZIP2=y
-CONFIG_RD_GZIP=y
-CONFIG_RD_LZMA=y
-CONFIG_RD_LZO=y
-CONFIG_RD_XZ=y
-CONFIG_REALTEK_PHY=y
-CONFIG_REED_SOLOMON=y
-CONFIG_REED_SOLOMON_DEC8=y
-CONFIG_REED_SOLOMON_ENC8=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGMAP_SPI=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-# CONFIG_RTC_DRV_CMOS is not set
-CONFIG_RTC_DRV_DS1307=y
-CONFIG_RTC_DRV_DS3232=y
-CONFIG_RTC_DRV_EM3027=y
-CONFIG_RTC_DRV_FSL_FTM_ALARM=y
-# CONFIG_RTC_DRV_IMXDI is not set
-# CONFIG_RTC_DRV_MXC is not set
-# CONFIG_RTC_DRV_MXC_V2 is not set
-CONFIG_RTC_DRV_PCF2127=y
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_SCHED_DEBUG=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-CONFIG_SECCOMP=y
-CONFIG_SECCOMP_FILTER=y
-# CONFIG_SECURITY_DMESG_RESTRICT is not set
-CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
-CONFIG_SERIAL_8250_DW=y
-CONFIG_SERIAL_8250_DWLIB=y
-CONFIG_SERIAL_8250_EM=y
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_PCI=y
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIAL_CONEXANT_DIGICOLOR=y
-CONFIG_SERIAL_CONEXANT_DIGICOLOR_CONSOLE=y
-CONFIG_SERIAL_FSL_LPUART=y
-CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
-CONFIG_SERIAL_IMX=y
-CONFIG_SERIAL_IMX_CONSOLE=y
-CONFIG_SERIAL_IMX_EARLYCON=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SERIAL_ST_ASC=y
-CONFIG_SERIAL_ST_ASC_CONSOLE=y
-CONFIG_SERIAL_XILINX_PS_UART=y
-CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SG_POOL=y
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-CONFIG_SMSC_PHY=y
-CONFIG_SOCK_DIAG=y
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SOC_BRCMSTB=y
-CONFIG_SOC_BUS=y
-# CONFIG_SOC_IMX50 is not set
-# CONFIG_SOC_IMX51 is not set
-# CONFIG_SOC_IMX53 is not set
-# CONFIG_SOC_IMX6Q is not set
-# CONFIG_SOC_IMX6SL is not set
-# CONFIG_SOC_IMX6SLL is not set
-# CONFIG_SOC_IMX6SX is not set
-# CONFIG_SOC_IMX6UL is not set
-# CONFIG_SOC_IMX7D is not set
-# CONFIG_SOC_IMX7ULP is not set
-# CONFIG_SOC_IMX8M is not set
-CONFIG_SOC_LS1021A=y
-# CONFIG_SOC_VF610 is not set
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_BITBANG=y
-CONFIG_SPI_CADENCE=y
-CONFIG_SPI_DYNAMIC=y
-# CONFIG_SPI_FSL_LPSPI is not set
-# CONFIG_SPI_FSL_QUADSPI is not set
-# CONFIG_SPI_IMX is not set
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_SPIDEV=y
-CONFIG_SPI_XILINX=y
-CONFIG_SPMI=y
-# CONFIG_SPMI_HISI3670 is not set
-# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
-CONFIG_SQUASHFS_DECOMP_SINGLE=y
-CONFIG_SQUASHFS_FILE_CACHE=y
-# CONFIG_SQUASHFS_FILE_DIRECT is not set
-CONFIG_SQUASHFS_LZO=y
-CONFIG_SQUASHFS_ZLIB=y
-CONFIG_SRAM=y
-CONFIG_SRAM_EXEC=y
-CONFIG_SRCU=y
-CONFIG_STACKTRACE=y
-CONFIG_STAGING_BOARD=y
-# CONFIG_STRIP_ASM_SYMS is not set
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-CONFIG_SWIOTLB=y
-CONFIG_SWPHY=y
-CONFIG_SWP_EMULATE=y
-CONFIG_SYNC_FILE=y
-CONFIG_SYSFS_SYSCALL=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_OF=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UBIFS_FS=y
-# CONFIG_UCLAMP_TASK is not set
-CONFIG_UEVENT_HELPER_PATH=""
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNIX_DIAG=y
-CONFIG_UNWINDER_ARM=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USER_NS=y
-CONFIG_USE_OF=y
-CONFIG_UTS_NS=y
-CONFIG_VEXPRESS_CONFIG=y
-CONFIG_VFAT_FS=y
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_VIRTIO=y
-CONFIG_VIRTIO_BLK=y
-CONFIG_VIRTIO_CONSOLE=y
-CONFIG_VIRTIO_MMIO=y
-CONFIG_VIRTIO_NET=y
-CONFIG_VIRTIO_PCI=y
-CONFIG_VIRTIO_PCI_LEGACY=y
-CONFIG_VIRTIO_PCI_LIB=y
-CONFIG_VITESSE_PHY=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_VT_CONSOLE_SLEEP=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-CONFIG_WATCHDOG_CORE=y
-# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
-CONFIG_XILINX_WATCHDOG=y
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_ARMTHUMB=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_XZ_DEC_IA64=y
-CONFIG_XZ_DEC_POWERPC=y
-CONFIG_XZ_DEC_SPARC=y
-CONFIG_XZ_DEC_X86=y
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
diff --git a/target/linux/layerscape/armv8_64b/config-5.15 b/target/linux/layerscape/armv8_64b/config-5.15
deleted file mode 100644
index 610da9b18e8f7f..00000000000000
--- a/target/linux/layerscape/armv8_64b/config-5.15
+++ /dev/null
@@ -1,864 +0,0 @@
-CONFIG_64BIT=y
-CONFIG_AQUANTIA_PHY=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_HIBERNATION_HEADER=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_LAYERSCAPE=y
-CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
-CONFIG_ARCH_MMAP_RND_BITS=18
-CONFIG_ARCH_MMAP_RND_BITS_MAX=33
-CONFIG_ARCH_MMAP_RND_BITS_MIN=18
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
-CONFIG_ARCH_PROC_KCORE_TEXT=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_STACKWALK=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_WANTS_NO_INSTR=y
-CONFIG_ARM64=y
-CONFIG_ARM64_4K_PAGES=y
-CONFIG_ARM64_CNP=y
-CONFIG_ARM64_CRYPTO=y
-CONFIG_ARM64_EPAN=y
-CONFIG_ARM64_ERRATUM_1165522=y
-CONFIG_ARM64_ERRATUM_1286807=y
-CONFIG_ARM64_ERRATUM_819472=y
-CONFIG_ARM64_ERRATUM_824069=y
-CONFIG_ARM64_ERRATUM_826319=y
-CONFIG_ARM64_ERRATUM_827319=y
-CONFIG_ARM64_ERRATUM_832075=y
-CONFIG_ARM64_ERRATUM_843419=y
-CONFIG_ARM64_HW_AFDBM=y
-CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
-CONFIG_ARM64_PAGE_SHIFT=12
-CONFIG_ARM64_PAN=y
-CONFIG_ARM64_PA_BITS=48
-CONFIG_ARM64_PA_BITS_48=y
-CONFIG_ARM64_PTR_AUTH=y
-CONFIG_ARM64_PTR_AUTH_KERNEL=y
-CONFIG_ARM64_SVE=y
-CONFIG_ARM64_TAGGED_ADDR_ABI=y
-CONFIG_ARM64_VA_BITS=48
-# CONFIG_ARM64_VA_BITS_39 is not set
-CONFIG_ARM64_VA_BITS_48=y
-CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
-CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
-CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
-CONFIG_ARM_CPUIDLE=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_GIC_V2M=y
-CONFIG_ARM_GIC_V3=y
-CONFIG_ARM_GIC_V3_ITS=y
-CONFIG_ARM_GIC_V3_ITS_FSL_MC=y
-CONFIG_ARM_GIC_V3_ITS_PCI=y
-# CONFIG_ARM_PL172_MPMC is not set
-CONFIG_ARM_PSCI_CPUIDLE=y
-CONFIG_ARM_PSCI_FW=y
-CONFIG_ARM_SMMU=y
-# CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT is not set
-# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
-CONFIG_ARM_SMMU_V3=y
-# CONFIG_ARM_SMMU_V3_SVA is not set
-CONFIG_ARM_SP805_WATCHDOG=y
-CONFIG_ASM_MODVERSIONS=y
-CONFIG_ASN1=y
-CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y
-CONFIG_ATA=y
-CONFIG_AUDIT=y
-CONFIG_AUDITSYSCALL=y
-CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
-CONFIG_AUDIT_GENERIC=y
-CONFIG_AUTOFS4_FS=y
-CONFIG_AUTOFS_FS=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BALLOON_COMPACTION=y
-CONFIG_BATTERY_BQ27XXX=y
-# CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM is not set
-CONFIG_BATTERY_BQ27XXX_I2C=y
-CONFIG_BLK_DEV_BSG=y
-CONFIG_BLK_DEV_BSGLIB=y
-CONFIG_BLK_DEV_BSG_COMMON=y
-CONFIG_BLK_DEV_INTEGRITY=y
-CONFIG_BLK_DEV_INTEGRITY_T10=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=262144
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BLK_MQ_VIRTIO=y
-CONFIG_BLK_PM=y
-CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_BSD_PROCESS_ACCT_V3=y
-CONFIG_BTRFS_FS=y
-# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set
-CONFIG_BTRFS_FS_POSIX_ACL=y
-CONFIG_CAVIUM_ERRATUM_22375=y
-CONFIG_CAVIUM_ERRATUM_23144=y
-CONFIG_CAVIUM_ERRATUM_23154=y
-CONFIG_CAVIUM_ERRATUM_27456=y
-CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
-CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
-CONFIG_CHECKPOINT_RESTORE=y
-CONFIG_CHROME_PLATFORMS=y
-CONFIG_CLK_LS1028A_PLLDIG=y
-CONFIG_CLK_QORIQ=y
-# CONFIG_CLK_VEXPRESS_OSC is not set
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CLZ_TAB=y
-CONFIG_CMA=y
-CONFIG_CMA_ALIGNMENT=8
-CONFIG_CMA_AREAS=7
-# CONFIG_CMA_DEBUG is not set
-# CONFIG_CMA_DEBUGFS is not set
-CONFIG_CMA_SIZE_MBYTES=16
-# CONFIG_CMA_SIZE_SEL_MAX is not set
-CONFIG_CMA_SIZE_SEL_MBYTES=y
-# CONFIG_CMA_SIZE_SEL_MIN is not set
-# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
-# CONFIG_CMA_SYSFS is not set
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_CS2000_CP=y
-CONFIG_COMMON_CLK_FSL_FLEXSPI=y
-# CONFIG_COMMON_CLK_FSL_SAI is not set
-CONFIG_COMMON_CLK_XGENE=y
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_CONTIG_ALLOC=y
-CONFIG_COREDUMP=y
-CONFIG_CPUFREQ_DT=y
-CONFIG_CPUFREQ_DT_PLATDEV=y
-CONFIG_CPU_FREQ=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_FREQ_THERMAL=y
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_THERMAL=y
-CONFIG_CRASH_CORE=y
-CONFIG_CRC16=y
-# CONFIG_CRC32_SARWATE is not set
-CONFIG_CRC32_SLICEBY8=y
-CONFIG_CRC7=y
-CONFIG_CRC_ITU_T=y
-CONFIG_CRC_T10DIF=y
-CONFIG_CROSS_MEMORY_ATTACH=y
-# CONFIG_CROS_EC is not set
-CONFIG_CRYPTO_AES_ARM64=y
-CONFIG_CRYPTO_AES_ARM64_CE=y
-CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
-CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
-CONFIG_CRYPTO_AUTHENC=y
-CONFIG_CRYPTO_BLAKE2B=y
-CONFIG_CRYPTO_CRC32=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_CRCT10DIF=y
-CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
-CONFIG_CRYPTO_CRYPTD=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_DES=y
-CONFIG_CRYPTO_DEV_FSL_CAAM=y
-CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API=y
-CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API_DESC=y
-CONFIG_CRYPTO_DEV_FSL_CAAM_COMMON=y
-CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API=y
-CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC=y
-CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI=y
-# CONFIG_CRYPTO_DEV_FSL_CAAM_DEBUG is not set
-# CONFIG_CRYPTO_DEV_FSL_CAAM_INTC is not set
-CONFIG_CRYPTO_DEV_FSL_CAAM_JR=y
-CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API=y
-CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE=9
-CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API=y
-CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_ENGINE=y
-CONFIG_CRYPTO_GHASH_ARM64_CE=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_DES=y
-CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_RSA=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA256_ARM64=y
-CONFIG_CRYPTO_SHA2_ARM64_CE=y
-CONFIG_CRYPTO_SIMD=y
-CONFIG_CRYPTO_XTS=y
-CONFIG_CRYPTO_XXHASH=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_MEMORY_INIT=y
-CONFIG_DECOMPRESS_BZIP2=y
-CONFIG_DECOMPRESS_GZIP=y
-CONFIG_DECOMPRESS_LZMA=y
-CONFIG_DECOMPRESS_LZO=y
-CONFIG_DECOMPRESS_XZ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DIMLIB=y
-CONFIG_DMADEVICES=y
-CONFIG_DMATEST=y
-CONFIG_DMA_CMA=y
-CONFIG_DMA_DIRECT_REMAP=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_ENGINE_RAID=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_OPS=y
-CONFIG_DMA_REMAP=y
-CONFIG_DMA_SHARED_BUFFER=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DNOTIFY=y
-CONFIG_DPAA2_CONSOLE=y
-CONFIG_DPAA_ERRATUM_A050385=y
-CONFIG_DTC=y
-CONFIG_DT_IDLE_STATES=y
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EEPROM_AT24=y
-CONFIG_ELF_CORE=y
-# CONFIG_EMBEDDED is not set
-CONFIG_EXT4_FS=y
-CONFIG_EXT4_FS_POSIX_ACL=y
-CONFIG_EXT4_FS_SECURITY=y
-CONFIG_EXTCON=y
-CONFIG_EXTCON_USB_GPIO=y
-CONFIG_F2FS_FS=y
-CONFIG_FAILOVER=y
-CONFIG_FANOTIFY=y
-CONFIG_FAT_FS=y
-CONFIG_FB=y
-CONFIG_FB_ARMCLCD=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-CONFIG_FB_CMDLINE=y
-CONFIG_FB_DEFERRED_IO=y
-CONFIG_FB_MODE_HELPERS=y
-CONFIG_FB_SYS_COPYAREA=y
-CONFIG_FB_SYS_FILLRECT=y
-CONFIG_FB_SYS_FOPS=y
-CONFIG_FB_SYS_IMAGEBLIT=y
-CONFIG_FHANDLE=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FONT_8x16=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_SUPPORT=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
-CONFIG_FRAME_POINTER=y
-CONFIG_FREEZER=y
-# CONFIG_FSL_BMAN_TEST is not set
-CONFIG_FSL_DPAA=y
-CONFIG_FSL_DPAA2_ETH=y
-CONFIG_FSL_DPAA2_PTP_CLOCK=y
-# CONFIG_FSL_DPAA2_QDMA is not set
-# CONFIG_FSL_DPAA2_SWITCH is not set
-# CONFIG_FSL_DPAA_CHECKING is not set
-CONFIG_FSL_DPAA_ETH=y
-CONFIG_FSL_EDMA=y
-CONFIG_FSL_ENETC=y
-CONFIG_FSL_ENETC_IERB=y
-CONFIG_FSL_ENETC_MDIO=y
-CONFIG_FSL_ENETC_PTP_CLOCK=y
-CONFIG_FSL_ENETC_VF=y
-CONFIG_FSL_ERRATUM_A008585=y
-CONFIG_FSL_FMAN=y
-CONFIG_FSL_GUTS=y
-CONFIG_FSL_IFC=y
-CONFIG_FSL_MC_BUS=y
-CONFIG_FSL_MC_DPIO=y
-CONFIG_FSL_MC_UAPI_SUPPORT=y
-# CONFIG_FSL_PPFE is not set
-# CONFIG_FSL_QMAN_TEST is not set
-CONFIG_FSL_RCPM=y
-CONFIG_FSL_XGMAC_MDIO=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FS_POSIX_ACL=y
-CONFIG_FUSE_FS=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_CACHE=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
-CONFIG_GARP=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_NUMA=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_CSUM=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_FIND_FIRST_BIT=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MIGRATION=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-# CONFIG_GIANFAR is not set
-CONFIG_GLOB=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_GENERIC=y
-CONFIG_GPIO_GENERIC_PLATFORM=y
-CONFIG_GPIO_MPC8XXX=y
-CONFIG_GPIO_PCA953X=y
-CONFIG_GPIO_PCA953X_IRQ=y
-CONFIG_GRO_CELLS=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HIBERNATE_CALLBACKS=y
-CONFIG_HIBERNATION=y
-CONFIG_HIBERNATION_SNAPSHOT_DEV=y
-CONFIG_HID=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_GENERIC=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HOTPLUG_CPU=y
-CONFIG_HUGETLBFS=y
-CONFIG_HUGETLB_PAGE=y
-CONFIG_HVC_DRIVER=y
-CONFIG_HVC_IRQ=y
-CONFIG_HVC_XEN=y
-CONFIG_HVC_XEN_FRONTEND=y
-CONFIG_HW_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_COMPAT=y
-CONFIG_I2C_DESIGNWARE_CORE=y
-CONFIG_I2C_DESIGNWARE_PLATFORM=y
-CONFIG_I2C_HELPER_AUTO=y
-CONFIG_I2C_IMX=y
-CONFIG_I2C_MUX=y
-CONFIG_I2C_MUX_PCA954x=y
-CONFIG_I2C_RK3X=y
-CONFIG_I2C_SLAVE=y
-# CONFIG_I2C_SLAVE_TESTUNIT is not set
-CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
-CONFIG_IMX2_WDT=y
-CONFIG_INET_DIAG=y
-# CONFIG_INET_DIAG_DESTROY is not set
-# CONFIG_INET_RAW_DIAG is not set
-CONFIG_INET_TCP_DIAG=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_FF_MEMLESS=y
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_INPUT_MOUSE=y
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-CONFIG_INPUT_XEN_KBDDEV_FRONTEND=y
-CONFIG_INTERVAL_TREE=y
-CONFIG_IOMMU_API=y
-# CONFIG_IOMMU_DEBUGFS is not set
-CONFIG_IOMMU_DEFAULT_PASSTHROUGH=y
-CONFIG_IOMMU_DMA=y
-CONFIG_IOMMU_IOVA=y
-CONFIG_IOMMU_IO_PGTABLE=y
-# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
-CONFIG_IOMMU_IO_PGTABLE_LPAE=y
-# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
-CONFIG_IOMMU_SUPPORT=y
-CONFIG_IPC_NS=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_BYPASS_MANAGER=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_MSI_IOMMU=y
-CONFIG_IRQ_WORK=y
-# CONFIG_ISDN is not set
-CONFIG_JBD2=y
-CONFIG_JUMP_LABEL=y
-CONFIG_KALLSYMS=y
-CONFIG_KALLSYMS_ALL=y
-CONFIG_KCMP=y
-CONFIG_KEXEC=y
-CONFIG_KEXEC_CORE=y
-CONFIG_KEYBOARD_ATKBD=y
-CONFIG_KEYBOARD_GPIO=y
-CONFIG_KSM=y
-CONFIG_LIBCRC32C=y
-CONFIG_LIBFDT=y
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LOGO=y
-CONFIG_LOGO_LINUX_CLUT224=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_LS_EXTIRQ=y
-CONFIG_LS_SCFG_MSI=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MDIO_BITBANG=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_BUS_MUX=y
-CONFIG_MDIO_BUS_MUX_MMIOREG=y
-CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-# CONFIG_MDIO_GPIO is not set
-CONFIG_MEMFD_CREATE=y
-CONFIG_MEMORY=y
-CONFIG_MEMORY_BALLOON=y
-CONFIG_MEMORY_ISOLATION=y
-CONFIG_MEMTEST=y
-# CONFIG_MFD_HI6421_SPMI is not set
-CONFIG_MFD_SYSCON=y
-# CONFIG_MFD_VEXPRESS_SYSREG is not set
-CONFIG_MICREL_PHY=y
-CONFIG_MICROSEMI_PHY=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_BLOCK_MINORS=32
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_IO_ACCESSORS=y
-CONFIG_MMC_SDHCI_OF_ESDHC=y
-# CONFIG_MMC_SDHCI_PCI is not set
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MMU_NOTIFIER=y
-CONFIG_MODULES_USE_ELF_RELA=y
-CONFIG_MODULE_FORCE_LOAD=y
-CONFIG_MODVERSIONS=y
-# CONFIG_MOUSE_BCM5974 is not set
-# CONFIG_MOUSE_CYAPA is not set
-CONFIG_MOUSE_PS2=y
-CONFIG_MOUSE_PS2_ALPS=y
-CONFIG_MOUSE_PS2_BYD=y
-CONFIG_MOUSE_PS2_CYPRESS=y
-# CONFIG_MOUSE_PS2_ELANTECH is not set
-CONFIG_MOUSE_PS2_FOCALTECH=y
-CONFIG_MOUSE_PS2_LOGIPS2PP=y
-CONFIG_MOUSE_PS2_SMBUS=y
-CONFIG_MOUSE_PS2_SYNAPTICS=y
-CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
-# CONFIG_MOUSE_PS2_TOUCHKIT is not set
-CONFIG_MOUSE_PS2_TRACKPOINT=y
-# CONFIG_MOUSE_SERIAL is not set
-# CONFIG_MOUSE_VSXXXAA is not set
-CONFIG_MPILIB=y
-CONFIG_MRP=y
-CONFIG_MSCC_OCELOT_SWITCH_LIB=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-# CONFIG_MTD_CFI_GEOMETRY is not set
-CONFIG_MTD_CFI_STAA=y
-CONFIG_MTD_CMDLINE_PARTS=y
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-CONFIG_MTD_DATAFLASH=y
-# CONFIG_MTD_DATAFLASH_OTP is not set
-# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set
-CONFIG_MTD_NAND_CORE=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_ECC_SW_HAMMING=y
-CONFIG_MTD_NAND_FSL_IFC=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_SPI_NAND=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_SPLIT_FIT_FW=y
-CONFIG_MTD_SST25L=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MULTIPLEXER=y
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_MUX_MMIO=y
-CONFIG_MV_XOR_V2=y
-CONFIG_NAMESPACES=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-CONFIG_NET_DEVLINK=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_MSCC_FELIX=y
-CONFIG_NET_DSA_TAG_OCELOT=y
-CONFIG_NET_DSA_TAG_OCELOT_8021Q=y
-CONFIG_NET_FAILOVER=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_NS=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NLS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NODES_SHIFT=2
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=64
-CONFIG_NUMA=y
-CONFIG_NUMA_BALANCING=y
-CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y
-CONFIG_NVMEM=y
-# CONFIG_NVMEM_LAYERSCAPE_SFP is not set
-# CONFIG_NVMEM_SPMI_SDAM is not set
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IOMMU=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_NUMA=y
-CONFIG_PACKET_DIAG=y
-CONFIG_PACKING=y
-CONFIG_PADATA=y
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_REPORTING=y
-# CONFIG_PANIC_ON_OOPS is not set
-CONFIG_PANIC_ON_OOPS_VALUE=0
-CONFIG_PANIC_TIMEOUT=0
-CONFIG_PARAVIRT=y
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_PARTITION_PERCPU=y
-CONFIG_PCI=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEASPM=y
-CONFIG_PCIEASPM_DEFAULT=y
-# CONFIG_PCIEASPM_PERFORMANCE is not set
-# CONFIG_PCIEASPM_POWERSAVE is not set
-# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_DW=y
-CONFIG_PCIE_DW_HOST=y
-CONFIG_PCIE_LAYERSCAPE_GEN4=y
-CONFIG_PCIE_MOBIVEIL=y
-CONFIG_PCIE_MOBIVEIL_HOST=y
-CONFIG_PCIE_PME=y
-CONFIG_PCI_ATS=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_ECAM=y
-CONFIG_PCI_HISI=y
-CONFIG_PCI_HOST_COMMON=y
-CONFIG_PCI_HOST_GENERIC=y
-CONFIG_PCI_IOV=y
-CONFIG_PCI_LAYERSCAPE=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PCS_LYNX=y
-CONFIG_PGTABLE_LEVELS=4
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_PHY_XGENE=y
-CONFIG_PID_IN_CONTEXTIDR=y
-CONFIG_PID_NS=y
-CONFIG_PL330_DMA=y
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_PM_OPP=y
-CONFIG_PM_SLEEP=y
-CONFIG_PM_SLEEP_SMP=y
-CONFIG_PM_STD_PARTITION=""
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_SYSCON=y
-CONFIG_POWER_RESET_VEXPRESS=y
-CONFIG_POWER_RESET_XGENE=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PPS=y
-CONFIG_PREEMPT=y
-CONFIG_PREEMPTION=y
-CONFIG_PREEMPT_COUNT=y
-# CONFIG_PREEMPT_NONE is not set
-CONFIG_PREEMPT_RCU=y
-CONFIG_PRINTK_TIME=y
-CONFIG_PRINT_QUOTA_WARNING=y
-CONFIG_PROC_CHILDREN=y
-CONFIG_PROFILING=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PTP_1588_CLOCK_QORIQ=y
-CONFIG_QCOM_HIDMA=y
-CONFIG_QCOM_HIDMA_MGMT=y
-CONFIG_QCOM_QDF2400_ERRATUM_0065=y
-# CONFIG_QFMT_V2 is not set
-CONFIG_QORIQ_CPUFREQ=y
-CONFIG_QORIQ_THERMAL=y
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_QUEUED_SPINLOCKS=y
-CONFIG_QUOTA=y
-CONFIG_QUOTACTL=y
-CONFIG_RAID6_PQ=y
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-CONFIG_RD_BZIP2=y
-CONFIG_RD_GZIP=y
-CONFIG_RD_LZMA=y
-CONFIG_RD_LZO=y
-CONFIG_RD_XZ=y
-CONFIG_REALTEK_PHY=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGMAP_SPI=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_DS1307=y
-CONFIG_RTC_DRV_DS3232=y
-CONFIG_RTC_DRV_FSL_FTM_ALARM=y
-CONFIG_RTC_DRV_PCF2127=y
-CONFIG_RTC_DRV_PL031=y
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_SCHED_INFO=y
-CONFIG_SCHED_MC=y
-CONFIG_SCHED_THERMAL_PRESSURE=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-# CONFIG_SCSI_PROC_FS is not set
-# CONFIG_SCSI_SAS_ATA is not set
-CONFIG_SCSI_SAS_ATTRS=y
-CONFIG_SCSI_SAS_HOST_SMP=y
-CONFIG_SCSI_SAS_LIBSAS=y
-CONFIG_SECCOMP=y
-CONFIG_SECCOMP_FILTER=y
-CONFIG_SECRETMEM=y
-CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
-CONFIG_SERIAL_8250_DW=y
-CONFIG_SERIAL_8250_DWLIB=y
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_PCI=y
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_AMBA_PL011=y
-CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-CONFIG_SERIAL_FSL_LPUART=y
-CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SERIAL_SC16IS7XX=y
-CONFIG_SERIAL_SC16IS7XX_CORE=y
-# CONFIG_SERIAL_SC16IS7XX_I2C is not set
-CONFIG_SERIAL_SC16IS7XX_SPI=y
-CONFIG_SERIAL_XILINX_PS_UART=y
-CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
-CONFIG_SERIO=y
-CONFIG_SERIO_AMBAKMI=y
-CONFIG_SERIO_LIBPS2=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SG_POOL=y
-CONFIG_SLAB=y
-# CONFIG_SLUB is not set
-CONFIG_SMP=y
-CONFIG_SOCK_DIAG=y
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SOC_BUS=y
-CONFIG_SPARSEMEM=y
-CONFIG_SPARSEMEM_EXTREME=y
-CONFIG_SPARSEMEM_VMEMMAP=y
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_FSL_DSPI=y
-CONFIG_SPI_FSL_QUADSPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_NXP_FLEXSPI=y
-CONFIG_SPI_PL022=y
-CONFIG_SPMI=y
-# CONFIG_SPMI_HISI3670 is not set
-# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
-CONFIG_SQUASHFS_DECOMP_SINGLE=y
-CONFIG_SQUASHFS_FILE_CACHE=y
-# CONFIG_SQUASHFS_FILE_DIRECT is not set
-# CONFIG_SQUASHFS_XZ is not set
-CONFIG_SQUASHFS_ZLIB=y
-CONFIG_SRAM=y
-CONFIG_SRCU=y
-# CONFIG_STRIP_ASM_SYMS is not set
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-CONFIG_SWIOTLB=y
-CONFIG_SWIOTLB_XEN=y
-CONFIG_SWPHY=y
-CONFIG_SYNC_FILE=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_SYSFS_SYSCALL=y
-CONFIG_SYS_HYPERVISOR=y
-CONFIG_TASKSTATS=y
-CONFIG_TASK_DELAY_ACCT=y
-CONFIG_TASK_IO_ACCOUNTING=y
-CONFIG_TASK_XACCT=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_EMULATION=y
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_OF=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
-CONFIG_TRANSPARENT_HUGEPAGE=y
-CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
-# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
-CONFIG_TRANS_TABLE=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-# CONFIG_UACCE is not set
-CONFIG_UBIFS_FS=y
-# CONFIG_UCLAMP_TASK is not set
-CONFIG_UIO=y
-CONFIG_UIO_AEC=y
-CONFIG_UIO_CIF=y
-CONFIG_UIO_DMEM_GENIRQ=y
-CONFIG_UIO_MF624=y
-CONFIG_UIO_NETX=y
-CONFIG_UIO_PCI_GENERIC=y
-CONFIG_UIO_PDRV_GENIRQ=y
-# CONFIG_UIO_PRUSS is not set
-CONFIG_UIO_SERCOS3=y
-CONFIG_UNINLINE_SPIN_UNLOCK=y
-CONFIG_UNIX_DIAG=y
-CONFIG_UNMAP_KERNEL_AT_EL0=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USER_NS=y
-CONFIG_USE_PERCPU_NUMA_NODE_ID=y
-CONFIG_UTS_NS=y
-CONFIG_VEXPRESS_CONFIG=y
-CONFIG_VFAT_FS=y
-CONFIG_VFIO=y
-CONFIG_VFIO_FSL_MC=y
-CONFIG_VFIO_IOMMU_TYPE1=y
-# CONFIG_VFIO_MDEV is not set
-# CONFIG_VFIO_NOIOMMU is not set
-CONFIG_VFIO_PCI=y
-CONFIG_VFIO_PCI_CORE=y
-CONFIG_VFIO_PCI_INTX=y
-CONFIG_VFIO_PCI_MMAP=y
-# CONFIG_VFIO_PLATFORM is not set
-CONFIG_VFIO_VIRQFD=y
-CONFIG_VGA_ARB=y
-CONFIG_VGA_ARB_MAX_GPUS=16
-CONFIG_VIDEOMODE_HELPERS=y
-CONFIG_VIRTIO=y
-CONFIG_VIRTIO_BALLOON=y
-CONFIG_VIRTIO_BLK=y
-CONFIG_VIRTIO_CONSOLE=y
-CONFIG_VIRTIO_MMIO=y
-CONFIG_VIRTIO_NET=y
-CONFIG_VIRTIO_PCI=y
-CONFIG_VIRTIO_PCI_LEGACY=y
-CONFIG_VIRTIO_PCI_LIB=y
-CONFIG_VITESSE_PHY=y
-CONFIG_VLAN_8021Q_GVRP=y
-CONFIG_VLAN_8021Q_MVRP=y
-CONFIG_VMAP_STACK=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_VT_CONSOLE_SLEEP=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-CONFIG_WATCHDOG_CORE=y
-# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
-CONFIG_XARRAY_MULTI=y
-CONFIG_XEN=y
-CONFIG_XENFS=y
-CONFIG_XEN_AUTO_XLATE=y
-CONFIG_XEN_BACKEND=y
-CONFIG_XEN_BALLOON=y
-# CONFIG_XEN_BLKDEV_BACKEND is not set
-CONFIG_XEN_BLKDEV_FRONTEND=y
-CONFIG_XEN_COMPAT_XENFS=y
-CONFIG_XEN_DEV_EVTCHN=y
-CONFIG_XEN_DOM0=y
-CONFIG_XEN_FBDEV_FRONTEND=y
-CONFIG_XEN_GNTDEV=y
-CONFIG_XEN_GRANT_DEV_ALLOC=y
-# CONFIG_XEN_NETDEV_BACKEND is not set
-CONFIG_XEN_NETDEV_FRONTEND=y
-CONFIG_XEN_PRIVCMD=y
-# CONFIG_XEN_PVCALLS_BACKEND is not set
-# CONFIG_XEN_SCSI_FRONTEND is not set
-CONFIG_XEN_SYS_HYPERVISOR=y
-# CONFIG_XEN_WDT is not set
-CONFIG_XEN_XENBUS_FRONTEND=y
-CONFIG_XFS_FS=y
-CONFIG_XFS_POSIX_ACL=y
-CONFIG_XFS_RT=y
-CONFIG_XOR_BLOCKS=y
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_ARMTHUMB=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_XZ_DEC_IA64=y
-CONFIG_XZ_DEC_POWERPC=y
-CONFIG_XZ_DEC_SPARC=y
-CONFIG_XZ_DEC_X86=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZONE_DMA32=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
diff --git a/target/linux/layerscape/patches-5.15/301-arm-dts-ls1021a-Add-LS1021A-IOT-board-support.patch b/target/linux/layerscape/patches-5.15/301-arm-dts-ls1021a-Add-LS1021A-IOT-board-support.patch
deleted file mode 100644
index fa8ded735ccf7b..00000000000000
--- a/target/linux/layerscape/patches-5.15/301-arm-dts-ls1021a-Add-LS1021A-IOT-board-support.patch
+++ /dev/null
@@ -1,291 +0,0 @@
-From 55e00e402d6143aeb153761f8144d9fee5f1f009 Mon Sep 17 00:00:00 2001
-From: Biwen Li <biwen.li@nxp.com>
-Date: Fri, 26 Oct 2018 16:00:37 +0800
-Subject: [PATCH] arm: dts: ls1021a: Add LS1021A-IOT board support
-
-Signed-off-by: Biwen Li <biwen.li@nxp.com>
-[rebase]
-Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
----
- arch/arm/boot/dts/Makefile        |   3 +-
- arch/arm/boot/dts/ls1021a-iot.dts | 262 ++++++++++++++++++++++++++++++++++++++
- 2 files changed, 264 insertions(+), 1 deletion(-)
- create mode 100644 arch/arm/boot/dts/ls1021a-iot.dts
-
---- a/arch/arm/boot/dts/Makefile
-+++ b/arch/arm/boot/dts/Makefile
-@@ -713,7 +713,8 @@ dtb-$(CONFIG_SOC_LS1021A) += \
- 	ls1021a-moxa-uc-8410a.dtb \
- 	ls1021a-qds.dtb \
- 	ls1021a-tsn.dtb \
--	ls1021a-twr.dtb
-+	ls1021a-twr.dtb \
-+	ls1021a-iot.dtb
- dtb-$(CONFIG_SOC_VF610) += \
- 	vf500-colibri-eval-v3.dtb \
- 	vf610-bk4.dtb \
---- /dev/null
-+++ b/arch/arm/boot/dts/ls1021a-iot.dts
-@@ -0,0 +1,262 @@
-+/*
-+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ */
-+
-+/dts-v1/;
-+#include "ls1021a.dtsi"
-+
-+/ {
-+	model = "LS1021A IOT Board";
-+
-+	sys_mclk: clock-mclk {
-+		compatible = "fixed-clock";
-+		#clock-cells = <0>;
-+		clock-frequency = <24576000>;
-+	};
-+
-+	regulators {
-+		compatible = "simple-bus";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+
-+		reg_3p3v: regulator@0 {
-+			compatible = "regulator-fixed";
-+			reg = <0>;
-+			regulator-name = "3P3V";
-+			regulator-min-microvolt = <3300000>;
-+			regulator-max-microvolt = <3300000>;
-+			regulator-always-on;
-+		};
-+
-+		reg_2p5v: regulator@1 {
-+			compatible = "regulator-fixed";
-+			reg = <1>;
-+			regulator-name = "2P5V";
-+			regulator-min-microvolt = <2500000>;
-+			regulator-max-microvolt = <2500000>;
-+			regulator-always-on;
-+		};
-+	};
-+
-+	sound {
-+		compatible = "simple-audio-card";
-+		simple-audio-card,format = "i2s";
-+		simple-audio-card,widgets =
-+			"Microphone", "Microphone Jack",
-+			"Headphone", "Headphone Jack",
-+			"Speaker", "Speaker Ext",
-+			"Line", "Line In Jack";
-+		simple-audio-card,routing =
-+			"MIC_IN", "Microphone Jack",
-+			"Microphone Jack", "Mic Bias",
-+			"LINE_IN", "Line In Jack",
-+			"Headphone Jack", "HP_OUT",
-+			"Speaker Ext", "LINE_OUT";
-+
-+		simple-audio-card,cpu {
-+			sound-dai = <&sai2>;
-+			frame-master;
-+			bitclock-master;
-+		};
-+
-+		simple-audio-card,codec {
-+			sound-dai = <&codec>;
-+			frame-master;
-+			bitclock-master;
-+		};
-+	};
-+
-+	firmware {
-+		optee {
-+			compatible = "linaro,optee-tz";
-+			method = "smc";
-+			};
-+		};
-+};
-+
-+&enet0 {
-+	tbi-handle = <&tbi1>;
-+	phy-handle = <&phy1>;
-+	phy-connection-type = "sgmii";
-+	status = "okay";
-+};
-+
-+&enet1 {
-+	tbi-handle = <&tbi1>;
-+	phy-handle = <&phy3>;
-+	phy-connection-type = "sgmii";
-+	status = "okay";
-+};
-+
-+&enet2 {
-+	fixed-link = <0 1 1000 0 0>;
-+	phy-connection-type = "rgmii-id";
-+	status = "okay";
-+};
-+
-+&can0{
-+	status = "disabled";
-+};
-+
-+&can1{
-+	status = "disabled";
-+};
-+
-+&can2{
-+	status = "disabled";
-+};
-+
-+&can3{
-+	status = "okay";
-+};
-+
-+&esdhc{
-+	status = "okay";
-+};
-+
-+&i2c0 {
-+	status = "okay";
-+
-+	max1239@35 {
-+		compatible = "maxim,max1239";
-+		reg = <0x35>;
-+		#io-channel-cells = <1>;
-+	};
-+
-+	codec: sgtl5000@2a {
-+               #sound-dai-cells=<0x0>;
-+		compatible = "fsl,sgtl5000";
-+		reg = <0x2a>;
-+		VDDA-supply = <&reg_3p3v>;
-+		VDDIO-supply = <&reg_2p5v>;
-+		clocks = <&sys_mclk 1>;
-+	};
-+
-+	pca9555: pca9555@23 {
-+		compatible = "nxp,pca9555";
-+		/*pinctrl-names = "default";*/
-+		/*interrupt-parent = <&gpio2>;
-+		interrupts = <19 0x2>;*/
-+		gpio-controller;
-+		#gpio-cells = <2>;
-+		interrupt-controller;
-+		#interrupt-cells = <2>;
-+		reg = <0x23>;
-+	};
-+
-+	ina220@44 {
-+		compatible = "ti,ina220";
-+		reg = <0x44>;
-+		shunt-resistor = <1000>;
-+	};
-+
-+	ina220@45 {
-+		compatible = "ti,ina220";
-+		reg = <0x45>;
-+		shunt-resistor = <1000>;
-+	};
-+
-+	lm75b@48 {
-+                compatible = "nxp,lm75a";
-+                reg = <0x48>;
-+        };
-+
-+	adt7461a@4c {
-+		compatible = "adt7461a";
-+		reg = <0x4c>;
-+	};
-+
-+	hdmi: sii9022a@39 {
-+		compatible = "fsl,sii902x";
-+		reg = <0x39>;
-+		interrupts = <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>;
-+	};
-+};
-+
-+&i2c1 {
-+	status = "disabled";
-+};
-+
-+&ifc {
-+	status = "disabled";
-+};
-+
-+&lpuart0 {
-+	status = "okay";
-+};
-+
-+&mdio0 {
-+	phy0: ethernet-phy@0 {
-+		reg = <0x0>;
-+	};
-+	phy1: ethernet-phy@1 {
-+		reg = <0x1>;
-+	};
-+	phy2: ethernet-phy@2 {
-+		reg = <0x2>;
-+	};
-+	phy3: ethernet-phy@3 {
-+		reg = <0x3>;
-+	};
-+	tbi1: tbi-phy@1f {
-+		reg = <0x1f>;
-+		device_type = "tbi-phy";
-+	};
-+};
-+
-+&qspi {
-+	num-cs = <2>;
-+	status = "okay";
-+
-+	qflash0: s25fl128s@0 {
-+		compatible = "spansion,s25fl129p1";
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+		spi-max-frequency = <20000000>;
-+		reg = <0>;
-+	};
-+};
-+
-+&sai2 {
-+	status = "okay";
-+};
-+
-+&uart0 {
-+	status = "okay";
-+};
-+
-+&uart1 {
-+	status = "okay";
-+};
-+
-+&dcu {
-+	display = <&display>;
-+	status = "okay";
-+
-+	display: display@0 {
-+		bits-per-pixel = <24>;
-+
-+		display-timings {
-+			native-mode = <&timing0>;
-+
-+			timing0: mode0 {
-+				clock-frequency = <25000000>;
-+				hactive = <640>;
-+				vactive = <480>;
-+				hback-porch = <80>;
-+				hfront-porch = <80>;
-+				vback-porch = <16>;
-+				vfront-porch = <16>;
-+				hsync-len = <12>;
-+				vsync-len = <2>;
-+				hsync-active = <1>;
-+				vsync-active = <1>;
-+			};
-+		};
-+	};
-+};
diff --git a/target/linux/layerscape/patches-5.15/302-arm64-dts-ls1012a-update-with-ppfe-support.patch b/target/linux/layerscape/patches-5.15/302-arm64-dts-ls1012a-update-with-ppfe-support.patch
deleted file mode 100644
index 27f4330bf1f587..00000000000000
--- a/target/linux/layerscape/patches-5.15/302-arm64-dts-ls1012a-update-with-ppfe-support.patch
+++ /dev/null
@@ -1,288 +0,0 @@
-From 1bb35ff4ce33e65601c8d9c736be52e4aabd6252 Mon Sep 17 00:00:00 2001
-From: Calvin Johnson <calvin.johnson@nxp.com>
-Date: Sat, 16 Sep 2017 14:20:23 +0530
-Subject: [PATCH] arm64: dts: freescale: ls1012a: update with ppfe support
-
-Update ls1012a dtsi and platform dts files with support for ppfe.
-
-Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
-Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
----
- .../boot/dts/freescale/fsl-ls1012a-frdm.dts   | 43 +++++++++++++++++
- .../boot/dts/freescale/fsl-ls1012a-frwy.dts   | 43 +++++++++++++++++
- .../boot/dts/freescale/fsl-ls1012a-qds.dts    | 43 +++++++++++++++++
- .../boot/dts/freescale/fsl-ls1012a-rdb.dts    | 47 +++++++++++++++++++
- .../arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 29 ++++++++++++
- 5 files changed, 205 insertions(+)
-
---- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
-@@ -14,6 +14,11 @@
- 	model = "LS1012A Freedom Board";
- 	compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
- 
-+	aliases {
-+		ethernet0 = &pfe_mac0;
-+		ethernet1 = &pfe_mac1;
-+	};
-+
- 	sys_mclk: clock-mclk {
- 		compatible = "fixed-clock";
- 		#clock-cells = <0>;
-@@ -95,6 +100,44 @@
- 	};
- };
- 
-+&pfe {
-+	status = "okay";
-+	#address-cells = <1>;
-+	#size-cells = <0>;
-+
-+	pfe_mac0: ethernet@0 {
-+		compatible = "fsl,pfe-gemac-port";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		reg = <0x0>;	/* GEM_ID */
-+		fsl,gemac-bus-id = <0x0>;	/* BUS_ID */
-+		fsl,gemac-phy-id = <0x2>;	/* PHY_ID */
-+		fsl,mdio-mux-val = <0x0>;
-+		phy-mode = "sgmii";
-+		fsl,pfe-phy-if-flags = <0x0>;
-+
-+		mdio@0 {
-+			reg = <0x1>; /* enabled/disabled */
-+		};
-+	};
-+
-+	pfe_mac1: ethernet@1 {
-+		compatible = "fsl,pfe-gemac-port";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		reg = <0x1>;	/* GEM_ID */
-+		fsl,gemac-bus-id = <0x1>;	/* BUS_ID */
-+		fsl,gemac-phy-id = <0x1>;	/* PHY_ID */
-+		fsl,mdio-mux-val = <0x0>;
-+		phy-mode = "sgmii";
-+		fsl,pfe-phy-if-flags = <0x0>;
-+
-+		mdio@0 {
-+			reg = <0x0>; /* enabled/disabled */
-+		};
-+	};
-+};
-+
- &qspi {
- 	status = "okay";
- 
---- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts
-@@ -14,6 +14,11 @@
- / {
- 	model = "LS1012A FRWY Board";
- 	compatible = "fsl,ls1012a-frwy", "fsl,ls1012a";
-+
-+	aliases {
-+		ethernet0 = &pfe_mac0;
-+		ethernet1 = &pfe_mac1;
-+	};
- };
- 
- &duart0 {
-@@ -28,6 +33,44 @@
- 	status = "okay";
- };
- 
-+&pfe {
-+	status = "okay";
-+	#address-cells = <1>;
-+	#size-cells = <0>;
-+
-+	pfe_mac0: ethernet@0 {
-+		compatible = "fsl,pfe-gemac-port";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		reg = <0x0>;	/* GEM_ID */
-+		fsl,gemac-bus-id = <0x0>;	/* BUS_ID */
-+		fsl,gemac-phy-id = <0x2>;	/* PHY_ID */
-+		fsl,mdio-mux-val = <0x0>;
-+		phy-mode = "sgmii";
-+		fsl,pfe-phy-if-flags = <0x0>;
-+
-+		mdio@0 {
-+			reg = <0x1>; /* enabled/disabled */
-+		};
-+	};
-+
-+	pfe_mac1: ethernet@1 {
-+		compatible = "fsl,pfe-gemac-port";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		reg = <0x1>;	/* GEM_ID */
-+		fsl,gemac-bus-id = <0x1>;	/* BUS_ID */
-+		fsl,gemac-phy-id = <0x1>;	/* PHY_ID */
-+		fsl,mdio-mux-val = <0x0>;
-+		phy-mode = "sgmii";
-+		fsl,pfe-phy-if-flags = <0x0>;
-+
-+		mdio@0 {
-+			reg = <0x0>; /* enabled/disabled */
-+		};
-+	};
-+};
-+
- &qspi {
- 	status = "okay";
- 
---- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
-@@ -18,6 +18,11 @@
- 		mmc1 = &esdhc1;
- 	};
- 
-+	aliases {
-+		ethernet0 = &pfe_mac0;
-+		ethernet1 = &pfe_mac1;
-+	};
-+
- 	sys_mclk: clock-mclk {
- 		compatible = "fixed-clock";
- 		#clock-cells = <0>;
-@@ -132,6 +137,44 @@
- 		};
- 	};
- };
-+
-+&pfe {
-+	status = "okay";
-+	#address-cells = <1>;
-+	#size-cells = <0>;
-+
-+	pfe_mac0: ethernet@0 {
-+		compatible = "fsl,pfe-gemac-port";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		reg = <0x0>;	/* GEM_ID */
-+		fsl,gemac-bus-id = <0x0>;	/* BUS_ID */
-+		fsl,gemac-phy-id = <0x1>;	/* PHY_ID */
-+		fsl,mdio-mux-val = <0x2>;
-+		phy-mode = "sgmii-2500";
-+		fsl,pfe-phy-if-flags = <0x0>;
-+
-+		mdio@0 {
-+			reg = <0x1>; /* enabled/disabled */
-+		};
-+	};
-+
-+	pfe_mac1: ethernet@1 {
-+		compatible = "fsl,pfe-gemac-port";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		reg = <0x1>;	/* GEM_ID */
-+		fsl,gemac-bus-id = <0x1>;	/* BUS_ID */
-+		fsl,gemac-phy-id = <0x2>;	/* PHY_ID */
-+		fsl,mdio-mux-val = <0x3>;
-+		phy-mode = "sgmii-2500";
-+		fsl,pfe-phy-if-flags = <0x0>;
-+
-+		mdio@0 {
-+			reg = <0x0>; /* enabled/disabled */
-+		};
-+	};
-+};
- 
- &qspi {
- 	status = "okay";
---- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
-@@ -16,6 +16,8 @@
- 
- 	aliases {
- 		serial0 = &duart0;
-+		ethernet0 = &pfe_mac0;
-+		ethernet1 = &pfe_mac1;
- 		mmc0 = &esdhc0;
- 		mmc1 = &esdhc1;
- 	};
-@@ -86,6 +88,44 @@
- 	};
- };
- 
-+&pfe {
-+	status = "okay";
-+	#address-cells = <1>;
-+	#size-cells = <0>;
-+
-+	pfe_mac0: ethernet@0 {
-+		compatible = "fsl,pfe-gemac-port";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		reg = <0x0>;	/* GEM_ID */
-+		fsl,gemac-bus-id = <0x0>;	/* BUS_ID */
-+		fsl,gemac-phy-id = <0x2>;	/* PHY_ID */
-+		fsl,mdio-mux-val = <0x0>;
-+		phy-mode = "sgmii";
-+		fsl,pfe-phy-if-flags = <0x0>;
-+
-+		mdio@0 {
-+			reg = <0x1>; /* enabled/disabled */
-+		};
-+	};
-+
-+	pfe_mac1: ethernet@1 {
-+		compatible = "fsl,pfe-gemac-port";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		reg = <0x1>;	/* GEM_ID */
-+		fsl,gemac-bus-id = < 0x1 >;	/* BUS_ID */
-+		fsl,gemac-phy-id = < 0x1 >;	/* PHY_ID */
-+		fsl,mdio-mux-val = <0x0>;
-+		phy-mode = "rgmii-txid";
-+		fsl,pfe-phy-if-flags = <0x0>;
-+
-+		mdio@0 {
-+			reg = <0x0>; /* enabled/disabled */
-+		};
-+	};
-+};
-+
- &qspi {
- 	status = "okay";
- 
---- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
-@@ -560,6 +560,35 @@
- 		};
- 	};
- 
-+	reserved-memory {
-+		#address-cells = <2>;
-+		#size-cells = <2>;
-+		ranges;
-+
-+		pfe_reserved: packetbuffer@83400000 {
-+			reg = <0 0x83400000 0 0xc00000>;
-+		};
-+	};
-+
-+	pfe: pfe@04000000 {
-+		compatible = "fsl,pfe";
-+		reg =   <0x0 0x04000000 0x0 0xc00000>,	/* AXI 16M */
-+			<0x0 0x83400000 0x0 0xc00000>;  /* PFE DDR 12M */
-+		reg-names = "pfe", "pfe-ddr";
-+		fsl,pfe-num-interfaces = <0x2>;
-+		interrupts = <0 172 0x4>,    /* HIF interrupt */
-+			     <0 173 0x4>,    /*HIF_NOCPY interrupt */
-+			     <0 174 0x4>;    /* WoL interrupt */
-+		interrupt-names = "pfe_hif", "pfe_hif_nocpy", "pfe_wol";
-+		memory-region = <&pfe_reserved>;
-+		fsl,pfe-scfg = <&scfg 0>;
-+		fsl,rcpm-wakeup = <&rcpm 0xf0000020>;
-+		clocks = <&clockgen 4 0>;
-+		clock-names = "pfe";
-+
-+		status = "okay";
-+	};
-+
- 	firmware {
- 		optee {
- 			compatible = "linaro,optee-tz";
diff --git a/target/linux/layerscape/patches-5.15/303-arm64-dts-ls1012a-frdm-workaround-by-updating-qspi-f.patch b/target/linux/layerscape/patches-5.15/303-arm64-dts-ls1012a-frdm-workaround-by-updating-qspi-f.patch
deleted file mode 100644
index 5d19cb92dc0d53..00000000000000
--- a/target/linux/layerscape/patches-5.15/303-arm64-dts-ls1012a-frdm-workaround-by-updating-qspi-f.patch
+++ /dev/null
@@ -1,41 +0,0 @@
-From 9c5c18dbf8e1845d349ef7020f8af5bc9b56ed1f Mon Sep 17 00:00:00 2001
-From: Pawel Dembicki <paweldembicki@gmail.com>
-Date: Fri, 28 Sep 2022 17:14:32 +0200
-Subject: [PATCH] arm64: dts: ls1012a-frdm/qds: workaround by updating qspi flash to
- single mode
-
-Update rx and tx bus-width to 1 to use single mode to workaround ubifs
-issue found with double mode. (The same method as RDB board)
-
-Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
----
- arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts | 4 ++--
- arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts  | 4 ++--
- 2 file changed, 4 insertions(+), 4 deletions(-)
-
---- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
-@@ -148,8 +148,8 @@
- 		spi-max-frequency = <50000000>;
- 		m25p,fast-read;
- 		reg = <0>;
--		spi-rx-bus-width = <2>;
--		spi-tx-bus-width = <2>;
-+		spi-rx-bus-width = <1>;
-+		spi-tx-bus-width = <1>;
- 	};
- };
- 
---- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
-@@ -186,8 +186,8 @@
- 		spi-max-frequency = <50000000>;
- 		m25p,fast-read;
- 		reg = <0>;
--		spi-rx-bus-width = <2>;
--		spi-tx-bus-width = <2>;
-+		spi-rx-bus-width = <1>;
-+		spi-tx-bus-width = <1>;
- 	};
- };
- 
diff --git a/target/linux/layerscape/patches-5.15/304-arm64-dts-ls1012a-rdb-workaround-by-updating-qspi-fl.patch b/target/linux/layerscape/patches-5.15/304-arm64-dts-ls1012a-rdb-workaround-by-updating-qspi-fl.patch
deleted file mode 100644
index 53cfd193b78672..00000000000000
--- a/target/linux/layerscape/patches-5.15/304-arm64-dts-ls1012a-rdb-workaround-by-updating-qspi-fl.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From 9c5c18dbf8e1845d349ef7020f8af5bc9b56ed1f Mon Sep 17 00:00:00 2001
-From: Kuldeep Singh <kuldeep.singh@nxp.com>
-Date: Tue, 7 Jan 2020 17:14:32 +0530
-Subject: [PATCH] arm64: dts: ls1012a-rdb: workaround by updating qspi flash to
- single mode
-
-Update rx and tx bus-width to 1 to use single mode to workaround ubifs
-issue found with double mode.
-
-[ Leo: Local workaround ]
-
-Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
----
- arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
-@@ -136,8 +136,8 @@
- 		spi-max-frequency = <50000000>;
- 		m25p,fast-read;
- 		reg = <0>;
--		spi-rx-bus-width = <2>;
--		spi-tx-bus-width = <2>;
-+		spi-rx-bus-width = <1>;
-+		spi-tx-bus-width = <1>;
- 	};
- };
- 
diff --git a/target/linux/layerscape/patches-5.15/305-arm64-dts-ls1046a-rdb-Update-qspi-spi-rx-bus-width-t.patch b/target/linux/layerscape/patches-5.15/305-arm64-dts-ls1046a-rdb-Update-qspi-spi-rx-bus-width-t.patch
deleted file mode 100644
index 9bc4e2b520afb7..00000000000000
--- a/target/linux/layerscape/patches-5.15/305-arm64-dts-ls1046a-rdb-Update-qspi-spi-rx-bus-width-t.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From 38093ebbf25eb60a1aa863f46118a68a0300c56e Mon Sep 17 00:00:00 2001
-From: Kuldeep Singh <kuldeep.singh@nxp.com>
-Date: Fri, 3 Jan 2020 14:49:07 +0530
-Subject: [PATCH] arm64: dts: ls1046a-rdb: Update qspi spi-rx-bus-width to 1
-
-Update rx width from quad mode to single mode as a workaround.
-
-[Leo: Local workaround ]
-
-Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
----
- arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
-@@ -104,7 +104,7 @@
- 		#address-cells = <1>;
- 		#size-cells = <1>;
- 		spi-max-frequency = <50000000>;
--		spi-rx-bus-width = <4>;
-+		spi-rx-bus-width = <1>;
- 		spi-tx-bus-width = <1>;
- 		reg = <0>;
- 	};
-@@ -114,7 +114,7 @@
- 		#address-cells = <1>;
- 		#size-cells = <1>;
- 		spi-max-frequency = <50000000>;
--		spi-rx-bus-width = <4>;
-+		spi-rx-bus-width = <1>;
- 		spi-tx-bus-width = <1>;
- 		reg = <1>;
- 	};
diff --git a/target/linux/layerscape/patches-5.15/400-LF-20-3-mtd-spi-nor-Use-1-bit-mode-of-spansion-s25fs.patch b/target/linux/layerscape/patches-5.15/400-LF-20-3-mtd-spi-nor-Use-1-bit-mode-of-spansion-s25fs.patch
deleted file mode 100644
index 8ba7971e8a83a8..00000000000000
--- a/target/linux/layerscape/patches-5.15/400-LF-20-3-mtd-spi-nor-Use-1-bit-mode-of-spansion-s25fs.patch
+++ /dev/null
@@ -1,26 +0,0 @@
-From 2b84e88d36de482da0370290ad4af09a71993f08 Mon Sep 17 00:00:00 2001
-From: Han Xu <han.xu@nxp.com>
-Date: Tue, 14 Apr 2020 11:58:44 -0500
-Subject: [PATCH] LF-20-3 mtd: spi-nor: Use 1 bit mode of spansion(s25fs512s)
- flash
-
-This is a workaround patch which uses only single bit mode of s25fs512s
-flash
-
-Signed-off-by: Han Xu <han.xu@nxp.com>
-Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
----
- drivers/mtd/spi-nor/spansion.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/mtd/spi-nor/spansion.c
-+++ b/drivers/mtd/spi-nor/spansion.c
-@@ -232,7 +232,7 @@ static const struct flash_info spansion_
- 			      SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
- 			      USE_CLSR) },
- 	{ "s25fs512s",  INFO6(0x010220, 0x4d0081, 256 * 1024, 256,
--			      SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR)
-+			      SPI_NOR_4B_OPCODES | USE_CLSR)
- 	  .fixups = &s25fs_s_fixups, },
- 	{ "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024,  64, 0) },
- 	{ "s25sl12801", INFO(0x012018, 0x0301,  64 * 1024, 256, 0) },
diff --git a/target/linux/layerscape/patches-5.15/701-staging-add-fsl_ppfe-driver.patch b/target/linux/layerscape/patches-5.15/701-staging-add-fsl_ppfe-driver.patch
deleted file mode 100644
index 445d050a7842d1..00000000000000
--- a/target/linux/layerscape/patches-5.15/701-staging-add-fsl_ppfe-driver.patch
+++ /dev/null
@@ -1,11803 +0,0 @@
-From 15eff6c8760a76619654464103314bba9fdda0af Mon Sep 17 00:00:00 2001
-From: Pawel Dembicki <paweldembicki@gmail.com>
-Date: Sat, 19 Oct 2022 07:05:49 +0200
-Subject: [PATCH] staging: add fsl_ppfe driver
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This is squash of all commits with ppfe driver taken from NXP 5.15 tree:
-https://github.com/nxp-qoriq/linux/commits/lf-5.15.y/drivers/staging/fsl_ppfe
-
-List of original commits:
-
-net: fsl_ppfe: dts binding for ppfe
-
-Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
-Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
-
-staging: fsl_ppfe/eth: header files for pfe driver
-
-This patch has all pfe header files.
-
-Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
-Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
-
-staging: fsl_ppfe/eth: introduce pfe driver
-
-	This patch introduces Linux support for NXP's LS1012A Packet
-Forwarding Engine (pfe_eth). LS1012A uses hardware packet forwarding
-engine to provide high performance Ethernet interfaces. The device
-includes two Ethernet ports.
-
-Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
-Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
-
-staging: fsl_ppfe/eth: fix RGMII tx delay issue
-
-Recently logic to enable RGMII tx delay was changed by
-below patch.
-
-https://patchwork.kernel.org/patch/9447581/
-
-Based on the patch, appropriate change is made in PFE driver.
-
-Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
-Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
-
-staging: fsl_ppfe/eth: remove unused functions
-
-Remove unused functions hif_xmit_pkt & hif_lib_xmit_pkt.
-
-Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
-
-staging: fsl_ppfe/eth: fix read/write/ack idx issue
-
-While fixing checkpatch errors some of the index increments
-were commented out. They are enabled.
-
-Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
-
-staging: fsl_ppfe/eth: Make phy_ethtool_ksettings_get return void
-
-Make return value void since function never return meaningful value
-
-Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
-
-staging: fsl_ppfe/eth: add function to update tmu credits
-
-__hif_lib_update_credit function is used to update the tmu credits.
-If tx_qos is set, tmu credit is updated based on the number of packets
-transmitted by tmu.
-
-Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
-Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
-
-staging: fsl_ppfe/eth: Avoid packet drop at TMU queues
-
-Added flow control between TMU queues and PFE Linux driver,
-based on TMU credits availability.
-Added tx_qos module parameter to control this behavior.
-Use queue-0 as default queue to transmit packets.
-
-Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
-Signed-off-by: Akhila Kavi <akhila.kavi@nxp.com>
-Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
-
-staging: fsl_ppfe/eth: Enable PFE in clause 45 mode
-
-when we opearate in clause 45 mode, we need to call
-the function get_phy_device() with its 3rd argument as
-"true" and then the resultant phy device needs to be
-register with phy layer via phy_device_register()
-
-Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
-
-staging: fsl_ppfe/eth: Disable autonegotiation for 2.5G SGMII
-
-PCS initialization sequence for 2.5G SGMII interface governs
-auto negotiation to be in disabled mode
-
-Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
-
-staging: fsl_ppfe/eth: calculate PFE_PKT_SIZE with SKB_DATA_ALIGN
-
-pfe packet size was calculated without considering skb data alignment
-and this resulted in jumbo frames crashing kernel when the
-cacheline size increased from 64 to 128 bytes with
-commit 97303480753e ("arm64: Increase the max granular size").
-
-Modify pfe packet size caclulation to include skb data alignment of
-sizeof(struct skb_shared_info).
-
-Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
-
-staging: fsl_ppfe/eth: support for userspace networking
-
-This patch adds the userspace mode support to fsl_ppfe network driver.
-In the new mode, basic hardware initialization is performed in kernel, while
-the datapath and HIF handling is the responsibility of the userspace.
-
-The new command line parameter is added to initialize the ppfe module
-in userspace mode. By default the module remains in kernelspace networking
-mode.
-To enable userspace mode, use "insmod pfe.ko us=1"
-
-Signed-off-by: Akhil Goyal <akhil.goyal@nxp.com>
-Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
-
-staging: fsl_ppfe/eth: unregister netdev after pfe_phy_exit
-
-rmmod pfe.ko throws below warning:
-
-kernfs: can not remove 'phydev', no directory
-------------[ cut here ]------------
-WARNING: CPU: 0 PID: 2230 at fs/kernfs/dir.c:1481
-kernfs_remove_by_name_ns+0x90/0xa0
-
-This is caused when the unregistered netdev structure is accessed to
-disconnect phy.
-
-Resolve the issue by unregistering netdev after disconnecting phy.
-
-Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
-
-staging: fsl_ppfe/eth: HW parse results for DPDK
-
-HW Parse results are included in the packet headroom.
-Length and Offset calculation now accommodates parse info size.
-
-Signed-off-by: Archana Madhavan <archana.madhavan@nxp.com>
-
-staging: fsl_ppfe/eth: reorganize pfe_netdev_ops
-
-Reorganize members of struct pfe_netdev_ops to match with the order
-of members in struct net_device_ops defined in include/linux/netdevice.h
-
-Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
-
-staging: fsl_ppfe/eth: use mask for rx max frame len
-
-Define and use PFE_RCR_MAX_FL_MASK to properly set Rx max frame
-length of MAC Receive Control Register.
-
-Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
-
-staging: fsl_ppfe/eth: define pfe ndo_change_mtu function
-
-Define ndo_change_mtu function for pfe. This sets the max Rx frame
-length to the new mtu.
-
-Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
-
-staging: fsl_ppfe/eth: remove jumbo frame enable from gemac init
-
-MAC Receive Control Register was configured to allow jumbo frames.
-This is removed as jumbo frames can be supported anytime by changing
-mtu which will in turn modify MAX_FL field of MAC RCR.
-Jumbo frames caused pfe to hang on LS1012A rev 1.0 Silicon due to
-erratum A-010897.
-
-Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
-
-staging: fsl_ppfe/eth: disable CRC removal
-
-Disable CRC removal from the packet, so that packets are forwarded
-as is to Linux.
-CRC configuration in MAC will be reflected in the packet received
-to Linux.
-
-Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
-
-staging: fsl_ppfe/eth: handle ls1012a errata_a010897
-
-On LS1012A rev 1.0, Jumbo frames are not supported as it causes
-the PFE controller to hang. A reset of the entire chip is required
-to resume normal operation.
-
-To handle this errata, frames with length > 1900 are truncated for
-rev 1.0 of LS1012A.
-
-Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
-
-staging: fsl_ppfe/eth: replace magic numbers
-
-Replace magic numbers and some cosmetic changes.
-
-Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
-
-staging: fsl_ppfe/eth: resolve indentation warning
-
-Resolve the following indentation warning:
-
-drivers/staging/fsl_ppfe/pfe_ls1012a_platform.c:
-In function ‘pfe_get_gemac_if_proprties’:
-drivers/staging/fsl_ppfe/pfe_ls1012a_platform.c:96:2:
-warning: this ‘else’ clause does not guard...
-[-Wmisleading-indentation]
-  else
-  ^~~~
-drivers/staging/fsl_ppfe/pfe_ls1012a_platform.c:98:3:
-note: ...this statement, but the latter is misleadingly indented as
-if it were guarded by the ‘else’
-   pdata->ls1012a_eth_pdata[port].mdio_muxval = phy_id;
-   ^~~~~
-
-Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
-
-staging: fsl_ppfe/eth: add fixed-link support
-
-In cases where MAC is not connected to a normal MDIO-managed PHY
-device, and instead to a switch, it is configured as a "fixed-link".
-Code to handle this scenario is added here.
-
-phy_node in the dtb is checked to identify a fixed-link.
-On identification of a fixed-link, it is registered and connected.
-
-Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
-
-staging: fsl_ppfe: add support for a char dev for link status
-
-Read and IOCTL support is added. Application would need to open,
-read/ioctl the /dev/pfe_us_cdev device.
-select is pending as it requires a wait_queue.
-
-Signed-off-by: Shreyansh Jain <shreyansh.jain@nxp.com>
-Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
-
-staging: fsl_ppfe: enable hif event from userspace
-
-HIF interrupts are enabled using ioctl from user space,
-and epoll wait from user space wakes up when there is an HIF
-interrupt.
-
-Signed-off-by: Akhil Goyal <akhil.goyal@nxp.com>
-
-staging: fsl_ppfe: performance tuning for user space
-
-interrupt coalescing of 100 usec is added.
-
-Signed-off-by: Akhil Goyal <akhil.goyal@nxp.com>
-Signed-off-by: Sachin Saxena <sachin.saxena@nxp.com>
-
-staging: fsl_ppfe/eth: Update to use SPDX identifiers
-
-Replace license text with corresponding SPDX identifiers and update the
-format of existing SPDX identifiers to follow the new guideline
-Documentation/process/license-rules.rst.
-
-Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
-
-staging: fsl_ppfe/eth: misc clean up
-
-- remove redundant hwfeature init
-- remove unused vars from ls1012a_eth_platform_data
-- To handle ls1012a errata_a010897, PPFE driver requires GUTS driver
-to be compiled in. Select FSL_GUTS when PPFE driver is compiled.
-
-Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
-
-staging: fsl_ppfe/eth: reorganize platform phy parameters
-
-- Use "phy-handle" and of_* functions to get phy node and fixed-link
-parameters
-
-- Reorganize phy parameters and initialize them only if phy-handle
-or fixed-link is defined in the dtb.
-
-- correct typo pfe_get_gemac_if_proprties to pfe_get_gemac_if_properties
-
-Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
-
-staging: fsl_ppfe/eth: support single interface initialization
-
-- arrange members of struct mii_bus in sequence matching phy.h
-- if mdio node is defined, use of_mdiobus_register to register
-  child nodes (phy devices) available on the mdio bus.
-- remove of_phy_register_fixed_link from pfe_phy_init as it is being
-  handled in pfe_get_gemac_if_properties
-- remove mdio enabled check
-- skip phy init, if no PHY or fixed-link
-
-Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
-
-net: fsl_ppfe: update dts properties for phy
-
-Use commonly used phy-handle property and mdio subnode to handle
-phy properties.
-
-Deprecate bindings fsl,gemac-phy-id & fsl,pfe-phy-if-flags.
-
-Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
-
-staging: fsl_ppfe/eth: remove unused code
-
-- remove gemac-bus-id related code that is unused.
-- remove unused prototype gemac_set_mdc_div.
-
-Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
-
-staging: fsl_ppfe/eth: separate mdio init from mac init
-
-- separate mdio initialization from mac initialization
-- Define pfe_mdio_priv_s structure to hold mii_bus structure and other
-  related data.
-- Modify functions to work with the separted mdio init model.
-
-Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
-
-staging: fsl_ppfe/eth: adapt to link mode based phydev changes
-
-Setting link mode bits have changed with the integration of
-commit (3c1bcc8 net: ethernet: Convert phydev advertize and
-supported from u32 to link mode). Adapt to the new method of
-setting and clearing the link mode bits.
-
-Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
-
-staging: fsl_ppfe/eth: use generic soc_device infra instead of fsl_guts_get_svr()
-
-Commit ("soc: fsl: guts: make fsl_guts_get_svr() static") has
-made fsl_guts_get_svr() static and hence use generic soc_device
-infrastructure to check SoC revision.
-
-Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
-
-staging: fsl_ppfe/eth: use memremap() to map RAM area used by PFE
-
-RAM area used by PFE should be mapped using memremap() instead of
-directly traslating physical addr to virtual. This will ensure proper
-checks are done before the area is used.
-
-Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
-
-staging: fsl_ppfe/eth: remove 'fallback' argument from dev->ndo_select_queue()
-
-To be consistent with upstream API change.
-
-Signed-off-by: Li Yang <leoyang.li@nxp.com>
-
-staging: fsl_ppfe/eth: prefix header search paths with $(srctree)/
-
-Currently, the rules for configuring search paths in Kbuild have
-changed: https://lkml.org/lkml/2019/5/13/37
-
-This will lead the below error:
-
-fatal error: pfe/pfe.h: No such file or directory
-
-Fix it by adding $(srctree)/ prefix to the search paths.
-
-Signed-off-by: Ting Liu <ting.liu@nxp.com>
-
-staging: fsl_ppfe/eth: add pfe support to Kconfig and Makefile
-
-Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
-[ Aisheng: fix minor conflict due to removed VBOXSF_FS ]
-Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
-
-staging: fsl_ppfe/eth: Disable termination of CRC fwd.
-
-LS1012A MAC PCS block has an erratum that is seen with specific PHY AR803x.
-The issue is triggered by the (spec-compliant) operation of the AR803x PHY
-on the LS1012A-FRWY board.Due to this, good FCS packet is reported as error
-packet by MAC, so for these error packets FCS should be validated and
-discard only real error packets in PFE Rx packet path.
-
-Signed-off-by: Nagesh Koneti <koneti.nagesh@nxp.com>
-Signed-off-by: Nagesh Koneti <“koneti.nagesh@nxp.com”>
-
-net: ppfe: Cope with of_get_phy_mode() API change
-
-Signed-off-by: Li Yang <leoyang.li@nxp.com>
-
-staging: fsl_ppfe/eth: Enhance error checking in platform probe
-
-Fix the kernel crash when MAC addr is not passed in dtb.
-
-Signed-off-by: Anji Jagarlmudi <anji.jagarlmudi@nxp.com>
-
-staging: fsl_ppfe/eth: reject unsupported coalescing params
-
-Set ethtool_ops->supported_coalesce_params to let
-the core reject unsupported coalescing parameters.
-
-Signed-off-by: Anji Jagarlmudi <anji.jagarlmudi@nxp.com>
-
-staging: fsl_ppfe/eth:check "reg" property before pfe_get_gemac_if_properties()
-
-It has been observed that the function pfe_get_gemac_if_properties() is
-been called blindly for the next two child nodes. There might be some
-cases where it may go wrong and that lead to missing interfaces.
-with these changes it is ensured thats not the case.
-
-Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
-Signed-off-by: Anji J <anji.jagarlmudi@nxp.com>
-
-staging: fsl_ppfe/eth: "struct firmware" dereference is reduced in many functions
-
-firmware structure's data variable is the actual elf data. It has been
-dereferenced in multiple functions and this has been reduced.
-
-Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
-Signed-off-by: Anji J <anji.jagarlmudi@nxp.com>
-
-staging: fsl_ppfe/eth: LF-27 load pfe binaries from FDT
-
-FDT prepared in uboot now has pfe firmware part of it.
-These changes will read the firmware by default from it and tries to load
-the elf into the PFE PEs. This help build the pfe driver pasrt of kernel.
-
-Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
-Signed-off-by: Anji J <anji.jagarlmudi@nxp.com>
-
-staging: fsl_ppfe/eth: proper handling for RGMII delay mode
-
-The correct setting for the RGMII ports on LS1012ARDB is to
-enable delay on both Tx and Rx. So the phy mode to be matched
-is PHY_INTERFACE_MODE_RGMII_ID.
-
-Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
-Signed-off-by: Anji Jagarlmudi <anji.jagarlmudi@nxp.com>
-
-LF-1762-2 staging: fsl_ppfe: replace '---help---' in Kconfig files with 'help'
-
-Update Kconfig to cope with upstream change
-commit 84af7a6194e4 ("checkpatch: kconfig: prefer 'help' over
-'---help---'").
-
-Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
-
-staging: fsl_ppfe/eth: Nesting level does not match indentation
-
-corrected nesting level
-LF-1661 and Coverity CID: 8879316
-
-Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
-
-staging: fsl_ppfe/eth: Initialized scalar variable
-
-Proper initialization of scalar variable
-LF-1657 and Coverity CID: 3335133
-
-Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
-
-staging: fsl_ppfe/eth: misspelt variable name
-
-variable name corrected
-LF-1656 and Coverity CID: 3335119
-
-Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
-
-staging: fsl_ppfe/eth: Avoiding out-of-bound writes
-
-avoid out-of-bound writes with proper error handling
-LF-1654, LF-1652 and Coverity CID: 3335106, 3335090
-
-Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
-
-staging: fsl_ppfe/eth: Initializing scalar variable
-
-proper initialization of scalar variable.
-LF-1653 and Coverity CID: 3335101
-
-Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
-
-staging: fsl_ppfe/eth: checking return value
-
-proper checks added and handled for return value.
-LF-1644 and Coverity CID: 241888
-
-Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
-
-staging: fsl_ppfe/eth: Avoid out-of-bound access
-
-proper handling to avoid out-of-bound access
-LF-1642, LF-1641 and Coverity CID: 240910, 240891
-
-Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
-
-staging: fsl_ppfe/eth: Avoiding out-of-bound writes
-
-avoid out-of-bound writes with proper error handling
-LF-1654, LF-1652 and Coverity CID: 3335106, 3335090
-
-Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
-
-staging: fsl_ppfe/eth: return value init in error case
-
-proper err return in error case.
-LF-1806 and Coverity CID: 10468592
-
-Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
-
-staging: fsl_ppfe/eth: Avoid recursion in header inclusion
-
-Avoiding header inclusions that are not necessary and also that are
-causing header inclusion recursion.
-
-LF-2102 and Coverity CID: 240838
-
-Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
-
-staging: fsl_ppfe/eth: Avoiding return value overwrite
-
-avoid return value overwrite at the end of function.
-LF-2136, LF-2137 and Coverity CID: 8879341, 8879364
-
-Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
-
-staging: fsl_ppfe/eth: LF-27 enabling PFE firmware load from FDT
-
-The macro, "LOAD_PFEFIRMWARE_FROM_FILESYSTEM" is been disabled to load
-the firmware from FDT by default. Enabling the macro will load the
-firmware from filesystem.
-
-Also, the Makefile is now tuned to build pfe as per the config option
-
-Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
-
-staging: fsl_ppfe/eth: Ethtool stats correction for IEEE_rx_drop counter
-
-Due to carrier extended bug the phy counter IEEE_rx_drop counter is
-incremented some times and phy reports the packet has crc error.
-Because of this PFE revalidates all the packets that are marked crc
-error by phy. Now, the counter phy reports is till bogus and this
-patch decrements the counter by pfe revalidated (and are crc ok)
-counter amount.
-
-Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
-
-staging: fsl_ppfe/eth: PFE firmware load enhancements
-
-PFE driver enhancements to load the PE firmware from filesystem
-when the firmware is not found in FDT.
-
-Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
-
-staging: fsl_ppfe: deal with upstream API change of of_get_mac_address()
-
-Uptream commit 83216e398 changed the of_get_mac_address() API, update
-the user accordingly.
-
-Signed-off-by: Li Yang <leoyang.li@nxp.com>
-
-staging: fsl_ppfe: update coalesce setting uAPI usage
-
-API changed since:
-f3ccfda19319 ("ethtool: extend coalesce setting uAPI with CQE mode")
-
-Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
-
-Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
----
- .../devicetree/bindings/net/fsl_ppfe/pfe.txt  |  199 ++
- MAINTAINERS                                   |    8 +
- drivers/staging/Kconfig                       |    2 +
- drivers/staging/Makefile                      |    1 +
- drivers/staging/fsl_ppfe/Kconfig              |   21 +
- drivers/staging/fsl_ppfe/Makefile             |   20 +
- drivers/staging/fsl_ppfe/TODO                 |    2 +
- drivers/staging/fsl_ppfe/include/pfe/cbus.h   |   78 +
- .../staging/fsl_ppfe/include/pfe/cbus/bmu.h   |   55 +
- .../fsl_ppfe/include/pfe/cbus/class_csr.h     |  289 ++
- .../fsl_ppfe/include/pfe/cbus/emac_mtip.h     |  242 ++
- .../staging/fsl_ppfe/include/pfe/cbus/gpi.h   |   86 +
- .../staging/fsl_ppfe/include/pfe/cbus/hif.h   |  100 +
- .../fsl_ppfe/include/pfe/cbus/hif_nocpy.h     |   50 +
- .../fsl_ppfe/include/pfe/cbus/tmu_csr.h       |  168 ++
- .../fsl_ppfe/include/pfe/cbus/util_csr.h      |   61 +
- drivers/staging/fsl_ppfe/include/pfe/pfe.h    |  372 +++
- drivers/staging/fsl_ppfe/pfe_cdev.c           |  258 ++
- drivers/staging/fsl_ppfe/pfe_cdev.h           |   41 +
- drivers/staging/fsl_ppfe/pfe_ctrl.c           |  226 ++
- drivers/staging/fsl_ppfe/pfe_ctrl.h           |  100 +
- drivers/staging/fsl_ppfe/pfe_debugfs.c        |   99 +
- drivers/staging/fsl_ppfe/pfe_debugfs.h        |   13 +
- drivers/staging/fsl_ppfe/pfe_eth.c            | 2591 +++++++++++++++++
- drivers/staging/fsl_ppfe/pfe_eth.h            |  175 ++
- drivers/staging/fsl_ppfe/pfe_firmware.c       |  398 +++
- drivers/staging/fsl_ppfe/pfe_firmware.h       |   21 +
- drivers/staging/fsl_ppfe/pfe_hal.c            | 1517 ++++++++++
- drivers/staging/fsl_ppfe/pfe_hif.c            | 1064 +++++++
- drivers/staging/fsl_ppfe/pfe_hif.h            |  199 ++
- drivers/staging/fsl_ppfe/pfe_hif_lib.c        |  628 ++++
- drivers/staging/fsl_ppfe/pfe_hif_lib.h        |  229 ++
- drivers/staging/fsl_ppfe/pfe_hw.c             |  164 ++
- drivers/staging/fsl_ppfe/pfe_hw.h             |   15 +
- .../staging/fsl_ppfe/pfe_ls1012a_platform.c   |  383 +++
- drivers/staging/fsl_ppfe/pfe_mod.c            |  158 +
- drivers/staging/fsl_ppfe/pfe_mod.h            |  103 +
- drivers/staging/fsl_ppfe/pfe_perfmon.h        |   26 +
- drivers/staging/fsl_ppfe/pfe_sysfs.c          |  840 ++++++
- drivers/staging/fsl_ppfe/pfe_sysfs.h          |   17 +
- 40 files changed, 11019 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/net/fsl_ppfe/pfe.txt
- create mode 100644 drivers/staging/fsl_ppfe/Kconfig
- create mode 100644 drivers/staging/fsl_ppfe/Makefile
- create mode 100644 drivers/staging/fsl_ppfe/TODO
- create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus.h
- create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/bmu.h
- create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/class_csr.h
- create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/emac_mtip.h
- create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/gpi.h
- create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/hif.h
- create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/hif_nocpy.h
- create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/tmu_csr.h
- create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/util_csr.h
- create mode 100644 drivers/staging/fsl_ppfe/include/pfe/pfe.h
- create mode 100644 drivers/staging/fsl_ppfe/pfe_cdev.c
- create mode 100644 drivers/staging/fsl_ppfe/pfe_cdev.h
- create mode 100644 drivers/staging/fsl_ppfe/pfe_ctrl.c
- create mode 100644 drivers/staging/fsl_ppfe/pfe_ctrl.h
- create mode 100644 drivers/staging/fsl_ppfe/pfe_debugfs.c
- create mode 100644 drivers/staging/fsl_ppfe/pfe_debugfs.h
- create mode 100644 drivers/staging/fsl_ppfe/pfe_eth.c
- create mode 100644 drivers/staging/fsl_ppfe/pfe_eth.h
- create mode 100644 drivers/staging/fsl_ppfe/pfe_firmware.c
- create mode 100644 drivers/staging/fsl_ppfe/pfe_firmware.h
- create mode 100644 drivers/staging/fsl_ppfe/pfe_hal.c
- create mode 100644 drivers/staging/fsl_ppfe/pfe_hif.c
- create mode 100644 drivers/staging/fsl_ppfe/pfe_hif.h
- create mode 100644 drivers/staging/fsl_ppfe/pfe_hif_lib.c
- create mode 100644 drivers/staging/fsl_ppfe/pfe_hif_lib.h
- create mode 100644 drivers/staging/fsl_ppfe/pfe_hw.c
- create mode 100644 drivers/staging/fsl_ppfe/pfe_hw.h
- create mode 100644 drivers/staging/fsl_ppfe/pfe_ls1012a_platform.c
- create mode 100644 drivers/staging/fsl_ppfe/pfe_mod.c
- create mode 100644 drivers/staging/fsl_ppfe/pfe_mod.h
- create mode 100644 drivers/staging/fsl_ppfe/pfe_perfmon.h
- create mode 100644 drivers/staging/fsl_ppfe/pfe_sysfs.c
- create mode 100644 drivers/staging/fsl_ppfe/pfe_sysfs.h
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/net/fsl_ppfe/pfe.txt
-@@ -0,0 +1,199 @@
-+=============================================================================
-+NXP Programmable Packet Forwarding Engine Device Bindings
-+
-+CONTENTS
-+  - PFE Node
-+  - Ethernet Node
-+
-+=============================================================================
-+PFE Node
-+
-+DESCRIPTION
-+
-+PFE Node has all the properties associated with Packet Forwarding Engine block.
-+
-+PROPERTIES
-+
-+- compatible
-+		Usage: required
-+		Value type: <stringlist>
-+		Definition: Must include "fsl,pfe"
-+
-+- reg
-+		Usage: required
-+		Value type: <prop-encoded-array>
-+		Definition: A standard property.
-+		Specifies the offset of the following registers:
-+		- PFE configuration registers
-+		- DDR memory used by PFE
-+
-+- fsl,pfe-num-interfaces
-+		Usage: required
-+		Value type: <u32>
-+		Definition: Must be present. Value can be either one or two.
-+
-+- interrupts
-+		Usage: required
-+		Value type: <prop-encoded-array>
-+		Definition: Three interrupts are specified in this property.
-+		- HIF interrupt
-+		- HIF NO COPY interrupt
-+		- Wake On LAN interrupt
-+
-+- interrupt-names
-+		Usage: required
-+		Value type: <stringlist>
-+		Definition: Following strings are defined for the 3 interrupts.
-+		"pfe_hif" - HIF interrupt
-+		"pfe_hif_nocpy" - HIF NO COPY interrupt
-+		"pfe_wol" - Wake On LAN interrupt
-+
-+- memory-region
-+		Usage: required
-+		Value type: <phandle>
-+		Definition: phandle to a node describing reserved memory used by pfe.
-+		Refer:- Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
-+
-+- fsl,pfe-scfg
-+		Usage: required
-+		Value type: <phandle>
-+		Definition: phandle for scfg.
-+
-+- fsl,rcpm-wakeup
-+		Usage: required
-+		Value type: <phandle>
-+		Definition: phandle for rcpm.
-+
-+- clocks
-+		Usage: required
-+		Value type: <phandle>
-+		Definition: phandle for clockgen.
-+
-+- clock-names
-+		Usage: required
-+		Value type: <string>
-+		Definition: phandle for clock name.
-+
-+EXAMPLE
-+
-+pfe: pfe@04000000 {
-+	compatible = "fsl,pfe";
-+	reg =   <0x0 0x04000000 0x0 0xc00000>,	/* AXI 16M */
-+		<0x0 0x83400000 0x0 0xc00000>;  /* PFE DDR 12M */
-+	reg-names = "pfe", "pfe-ddr";
-+	fsl,pfe-num-interfaces = <0x2>;
-+	interrupts = <0 172 0x4>,    /* HIF interrupt */
-+		     <0 173 0x4>,    /*HIF_NOCPY interrupt */
-+		     <0 174 0x4>;    /* WoL interrupt */
-+	interrupt-names = "pfe_hif", "pfe_hif_nocpy", "pfe_wol";
-+	memory-region = <&pfe_reserved>;
-+	fsl,pfe-scfg = <&scfg 0>;
-+	fsl,rcpm-wakeup = <&rcpm 0xf0000020>;
-+	clocks = <&clockgen 4 0>;
-+	clock-names = "pfe";
-+
-+	status = "okay";
-+	pfe_mac0: ethernet@0 {
-+	};
-+
-+	pfe_mac1: ethernet@1 {
-+	};
-+};
-+
-+=============================================================================
-+Ethernet Node
-+
-+DESCRIPTION
-+
-+Ethernet Node has all the properties associated with PFE used by platforms to
-+connect to PHY:
-+
-+PROPERTIES
-+
-+- compatible
-+		Usage: required
-+		Value type: <stringlist>
-+		Definition: Must include "fsl,pfe-gemac-port"
-+
-+- reg
-+		Usage: required
-+		Value type: <prop-encoded-array>
-+		Definition: A standard property.
-+		Specifies the gemacid of the interface.
-+
-+- fsl,gemac-bus-id
-+		Usage: required
-+		Value type: <u32>
-+		Definition: Must be present. Value should be the id of the bus
-+		connected to gemac.
-+
-+- fsl,gemac-phy-id (deprecated binding)
-+               Usage: required
-+               Value type: <u32>
-+               Definition: This binding shouldn't be used with new platforms.
-+	       Must be present. Value should be the id of the phy
-+               connected to gemac.
-+
-+- fsl,mdio-mux-val
-+		Usage: required
-+		Value type: <u32>
-+		Definition: Must be present. Value can be either 0 or 2 or 3.
-+		This value is used to configure the mux to enable mdio.
-+
-+- phy-mode
-+		Usage: required
-+		Value type: <string>
-+		Definition: Must include "sgmii"
-+
-+- fsl,pfe-phy-if-flags (deprecated binding)
-+               Usage: required
-+               Value type: <u32>
-+               Definition: This binding shouldn't be used with new platforms.
-+               Must be present. Value should be 0 by default.
-+               If there is not phy connected, this need to be 1.
-+
-+- phy-handle
-+		Usage: optional
-+		Value type: <phandle>
-+		Definition: phandle to the PHY device connected to this device.
-+
-+- mdio : A required subnode which specifies the mdio bus in the PFE and used as
-+a container for phy nodes according to ../phy.txt.
-+
-+EXAMPLE
-+
-+ethernet@0 {
-+	compatible = "fsl,pfe-gemac-port";
-+	#address-cells = <1>;
-+	#size-cells = <0>;
-+	reg = <0x0>;	/* GEM_ID */
-+	fsl,gemac-bus-id = <0x0>;	/* BUS_ID */
-+	fsl,mdio-mux-val = <0x0>;
-+	phy-mode = "sgmii";
-+	phy-handle = <&sgmii_phy1>;
-+};
-+
-+
-+ethernet@1 {
-+	compatible = "fsl,pfe-gemac-port";
-+	#address-cells = <1>;
-+	#size-cells = <0>;
-+	reg = <0x1>;	/* GEM_ID */
-+	fsl,gemac-bus-id = <0x1>;	/* BUS_ID */
-+	fsl,mdio-mux-val = <0x0>;
-+	phy-mode = "sgmii";
-+	phy-handle = <&sgmii_phy2>;
-+};
-+
-+mdio@0 {
-+	#address-cells = <1>;
-+	#size-cells = <0>;
-+
-+	sgmii_phy1: ethernet-phy@2 {
-+		reg = <0x2>;
-+	};
-+
-+	sgmii_phy2: ethernet-phy@1 {
-+		reg = <0x1>;
-+	};
-+};
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -7520,6 +7520,14 @@ F:	drivers/ptp/ptp_qoriq.c
- F:	drivers/ptp/ptp_qoriq_debugfs.c
- F:	include/linux/fsl/ptp_qoriq.h
- 
-+FREESCALE QORIQ PPFE ETHERNET DRIVER
-+M:	Anji Jagarlmudi <anji.jagarlmudi@nxp.com>
-+M:	Calvin Johnson <calvin.johnson@nxp.com>
-+L:	netdev@vger.kernel.org
-+S:	Maintained
-+F:	drivers/staging/fsl_ppfe
-+F:	Documentation/devicetree/bindings/net/fsl_ppfe/pfe.txt
-+
- FREESCALE QUAD SPI DRIVER
- M:	Han Xu <han.xu@nxp.com>
- L:	linux-spi@vger.kernel.org
---- a/drivers/staging/Kconfig
-+++ b/drivers/staging/Kconfig
-@@ -102,4 +102,6 @@ source "drivers/staging/qlge/Kconfig"
- 
- source "drivers/staging/wfx/Kconfig"
- 
-+source "drivers/staging/fsl_ppfe/Kconfig"
-+
- endif # STAGING
---- a/drivers/staging/Makefile
-+++ b/drivers/staging/Makefile
-@@ -41,3 +41,4 @@ obj-$(CONFIG_XIL_AXIS_FIFO)	+= axis-fifo
- obj-$(CONFIG_FIELDBUS_DEV)     += fieldbus/
- obj-$(CONFIG_QLGE)		+= qlge/
- obj-$(CONFIG_WFX)		+= wfx/
-+obj-$(CONFIG_FSL_PPFE)		+= fsl_ppfe/
---- /dev/null
-+++ b/drivers/staging/fsl_ppfe/Kconfig
-@@ -0,0 +1,21 @@
-+#
-+# Freescale Programmable Packet Forwarding Engine driver
-+#
-+config FSL_PPFE
-+	tristate "Freescale PPFE Driver"
-+	select FSL_GUTS
-+	default n
-+	help
-+	Freescale LS1012A SoC has a Programmable Packet Forwarding Engine.
-+	It provides two high performance ethernet interfaces.
-+	This driver initializes, programs and controls the PPFE.
-+	Use this driver to enable network connectivity on LS1012A platforms.
-+
-+if FSL_PPFE
-+
-+config FSL_PPFE_UTIL_DISABLED
-+	bool "Disable PPFE UTIL Processor Engine"
-+	help
-+	UTIL PE has to be enabled only if required.
-+
-+endif # FSL_PPFE
---- /dev/null
-+++ b/drivers/staging/fsl_ppfe/Makefile
-@@ -0,0 +1,20 @@
-+#
-+# Makefile for Freesecale PPFE driver
-+#
-+
-+ccflags-y +=  -I $(srctree)/$(src)/include  -I $(srctree)/$(src)
-+
-+obj-$(CONFIG_FSL_PPFE) += pfe.o
-+
-+pfe-y += pfe_mod.o \
-+	pfe_hw.o \
-+	pfe_firmware.o \
-+	pfe_ctrl.o \
-+	pfe_hif.o \
-+	pfe_hif_lib.o\
-+	pfe_eth.o \
-+	pfe_sysfs.o \
-+	pfe_debugfs.o \
-+	pfe_ls1012a_platform.o \
-+	pfe_hal.o \
-+	pfe_cdev.o
---- /dev/null
-+++ b/drivers/staging/fsl_ppfe/TODO
-@@ -0,0 +1,2 @@
-+TODO:
-+	- provide pfe pe monitoring support
---- /dev/null
-+++ b/drivers/staging/fsl_ppfe/include/pfe/cbus.h
-@@ -0,0 +1,78 @@
-+/*
-+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
-+ * Copyright 2017 NXP
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#ifndef _CBUS_H_
-+#define _CBUS_H_
-+
-+#define EMAC1_BASE_ADDR	(CBUS_BASE_ADDR + 0x200000)
-+#define EGPI1_BASE_ADDR	(CBUS_BASE_ADDR + 0x210000)
-+#define EMAC2_BASE_ADDR	(CBUS_BASE_ADDR + 0x220000)
-+#define EGPI2_BASE_ADDR	(CBUS_BASE_ADDR + 0x230000)
-+#define BMU1_BASE_ADDR	(CBUS_BASE_ADDR + 0x240000)
-+#define BMU2_BASE_ADDR	(CBUS_BASE_ADDR + 0x250000)
-+#define ARB_BASE_ADDR	(CBUS_BASE_ADDR + 0x260000)
-+#define DDR_CONFIG_BASE_ADDR	(CBUS_BASE_ADDR + 0x270000)
-+#define HIF_BASE_ADDR	(CBUS_BASE_ADDR + 0x280000)
-+#define HGPI_BASE_ADDR	(CBUS_BASE_ADDR + 0x290000)
-+#define LMEM_BASE_ADDR	(CBUS_BASE_ADDR + 0x300000)
-+#define LMEM_SIZE	0x10000
-+#define LMEM_END	(LMEM_BASE_ADDR + LMEM_SIZE)
-+#define TMU_CSR_BASE_ADDR	(CBUS_BASE_ADDR + 0x310000)
-+#define CLASS_CSR_BASE_ADDR	(CBUS_BASE_ADDR + 0x320000)
-+#define HIF_NOCPY_BASE_ADDR	(CBUS_BASE_ADDR + 0x350000)
-+#define UTIL_CSR_BASE_ADDR	(CBUS_BASE_ADDR + 0x360000)
-+#define CBUS_GPT_BASE_ADDR	(CBUS_BASE_ADDR + 0x370000)
-+
-+/*
-+ * defgroup XXX_MEM_ACCESS_ADDR PE memory access through CSR
-+ * XXX_MEM_ACCESS_ADDR register bit definitions.
-+ */
-+#define PE_MEM_ACCESS_WRITE	BIT(31)	/* Internal Memory Write. */
-+#define PE_MEM_ACCESS_IMEM	BIT(15)
-+#define PE_MEM_ACCESS_DMEM	BIT(16)
-+
-+/* Byte Enables of the Internal memory access. These are interpred in BE */
-+#define PE_MEM_ACCESS_BYTE_ENABLE(offset, size)	\
-+	({ typeof(size) size_ = (size);		\
-+	(((BIT(size_) - 1) << (4 - (offset) - (size_))) & 0xf) << 24; })
-+
-+#include "cbus/emac_mtip.h"
-+#include "cbus/gpi.h"
-+#include "cbus/bmu.h"
-+#include "cbus/hif.h"
-+#include "cbus/tmu_csr.h"
-+#include "cbus/class_csr.h"
-+#include "cbus/hif_nocpy.h"
-+#include "cbus/util_csr.h"
-+
-+/* PFE cores states */
-+#define CORE_DISABLE	0x00000000
-+#define CORE_ENABLE	0x00000001
-+#define CORE_SW_RESET	0x00000002
-+
-+/* LMEM defines */
-+#define LMEM_HDR_SIZE	0x0010
-+#define LMEM_BUF_SIZE_LN2	0x7
-+#define LMEM_BUF_SIZE	BIT(LMEM_BUF_SIZE_LN2)
-+
-+/* DDR defines */
-+#define DDR_HDR_SIZE	0x0100
-+#define DDR_BUF_SIZE_LN2	0xb
-+#define DDR_BUF_SIZE	BIT(DDR_BUF_SIZE_LN2)
-+
-+#endif /* _CBUS_H_ */
---- /dev/null
-+++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/bmu.h
-@@ -0,0 +1,55 @@
-+/*
-+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
-+ * Copyright 2017 NXP
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#ifndef _BMU_H_
-+#define _BMU_H_
-+
-+#define BMU_VERSION	0x000
-+#define BMU_CTRL	0x004
-+#define BMU_UCAST_CONFIG	0x008
-+#define BMU_UCAST_BASE_ADDR	0x00c
-+#define BMU_BUF_SIZE	0x010
-+#define BMU_BUF_CNT	0x014
-+#define BMU_THRES	0x018
-+#define BMU_INT_SRC	0x020
-+#define BMU_INT_ENABLE	0x024
-+#define BMU_ALLOC_CTRL	0x030
-+#define BMU_FREE_CTRL	0x034
-+#define BMU_FREE_ERR_ADDR	0x038
-+#define BMU_CURR_BUF_CNT	0x03c
-+#define BMU_MCAST_CNT	0x040
-+#define BMU_MCAST_ALLOC_CTRL	0x044
-+#define BMU_REM_BUF_CNT	0x048
-+#define BMU_LOW_WATERMARK	0x050
-+#define BMU_HIGH_WATERMARK	0x054
-+#define BMU_INT_MEM_ACCESS	0x100
-+
-+struct BMU_CFG {
-+	unsigned long baseaddr;
-+	u32 count;
-+	u32 size;
-+	u32 low_watermark;
-+	u32 high_watermark;
-+};
-+
-+#define BMU1_BUF_SIZE	LMEM_BUF_SIZE_LN2
-+#define BMU2_BUF_SIZE	DDR_BUF_SIZE_LN2
-+
-+#define BMU2_MCAST_ALLOC_CTRL	(BMU2_BASE_ADDR + BMU_MCAST_ALLOC_CTRL)
-+
-+#endif /* _BMU_H_ */
---- /dev/null
-+++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/class_csr.h
-@@ -0,0 +1,289 @@
-+/*
-+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
-+ * Copyright 2017 NXP
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#ifndef _CLASS_CSR_H_
-+#define _CLASS_CSR_H_
-+
-+/* @file class_csr.h.
-+ * class_csr - block containing all the classifier control and status register.
-+ * Mapped on CBUS and accessible from all PE's and ARM.
-+ */
-+#define CLASS_VERSION	(CLASS_CSR_BASE_ADDR + 0x000)
-+#define CLASS_TX_CTRL	(CLASS_CSR_BASE_ADDR + 0x004)
-+#define CLASS_INQ_PKTPTR	(CLASS_CSR_BASE_ADDR + 0x010)
-+
-+/* (ddr_hdr_size[24:16], lmem_hdr_size[5:0]) */
-+#define CLASS_HDR_SIZE	(CLASS_CSR_BASE_ADDR + 0x014)
-+
-+/* LMEM header size for the Classifier block.\ Data in the LMEM
-+ * is written from this offset.
-+ */
-+#define CLASS_HDR_SIZE_LMEM(off)	((off) & 0x3f)
-+
-+/* DDR header size for the Classifier block.\ Data in the DDR
-+ * is written from this offset.
-+ */
-+#define CLASS_HDR_SIZE_DDR(off)	(((off) & 0x1ff) << 16)
-+
-+#define CLASS_PE0_QB_DM_ADDR0	(CLASS_CSR_BASE_ADDR + 0x020)
-+
-+/* DMEM address of first [15:0] and second [31:16] buffers on QB side. */
-+#define CLASS_PE0_QB_DM_ADDR1	(CLASS_CSR_BASE_ADDR + 0x024)
-+
-+/* DMEM address of third [15:0] and fourth [31:16] buffers on QB side. */
-+#define CLASS_PE0_RO_DM_ADDR0	(CLASS_CSR_BASE_ADDR + 0x060)
-+
-+/* DMEM address of first [15:0] and second [31:16] buffers on RO side. */
-+#define CLASS_PE0_RO_DM_ADDR1	(CLASS_CSR_BASE_ADDR + 0x064)
-+
-+/* DMEM address of third [15:0] and fourth [31:16] buffers on RO side. */
-+
-+/* @name Class PE memory access. Allows external PE's and HOST to
-+ * read/write PMEM/DMEM memory ranges for each classifier PE.
-+ */
-+/* {sr_pe_mem_cmd[31], csr_pe_mem_wren[27:24], csr_pe_mem_addr[23:0]},
-+ * See \ref XXX_MEM_ACCESS_ADDR for details.
-+ */
-+#define CLASS_MEM_ACCESS_ADDR	(CLASS_CSR_BASE_ADDR + 0x100)
-+
-+/* Internal Memory Access Write Data [31:0] */
-+#define CLASS_MEM_ACCESS_WDATA	(CLASS_CSR_BASE_ADDR + 0x104)
-+
-+/* Internal Memory Access Read Data [31:0] */
-+#define CLASS_MEM_ACCESS_RDATA	(CLASS_CSR_BASE_ADDR + 0x108)
-+#define CLASS_TM_INQ_ADDR	(CLASS_CSR_BASE_ADDR + 0x114)
-+#define CLASS_PE_STATUS	(CLASS_CSR_BASE_ADDR + 0x118)
-+
-+#define CLASS_PHY1_RX_PKTS	(CLASS_CSR_BASE_ADDR + 0x11c)
-+#define CLASS_PHY1_TX_PKTS	(CLASS_CSR_BASE_ADDR + 0x120)
-+#define CLASS_PHY1_LP_FAIL_PKTS	(CLASS_CSR_BASE_ADDR + 0x124)
-+#define CLASS_PHY1_INTF_FAIL_PKTS	(CLASS_CSR_BASE_ADDR + 0x128)
-+#define CLASS_PHY1_INTF_MATCH_PKTS	(CLASS_CSR_BASE_ADDR + 0x12c)
-+#define CLASS_PHY1_L3_FAIL_PKTS	(CLASS_CSR_BASE_ADDR + 0x130)
-+#define CLASS_PHY1_V4_PKTS	(CLASS_CSR_BASE_ADDR + 0x134)
-+#define CLASS_PHY1_V6_PKTS	(CLASS_CSR_BASE_ADDR + 0x138)
-+#define CLASS_PHY1_CHKSUM_ERR_PKTS	(CLASS_CSR_BASE_ADDR + 0x13c)
-+#define CLASS_PHY1_TTL_ERR_PKTS	(CLASS_CSR_BASE_ADDR + 0x140)
-+#define CLASS_PHY2_RX_PKTS	(CLASS_CSR_BASE_ADDR + 0x144)
-+#define CLASS_PHY2_TX_PKTS	(CLASS_CSR_BASE_ADDR + 0x148)
-+#define CLASS_PHY2_LP_FAIL_PKTS	(CLASS_CSR_BASE_ADDR + 0x14c)
-+#define CLASS_PHY2_INTF_FAIL_PKTS	(CLASS_CSR_BASE_ADDR + 0x150)
-+#define CLASS_PHY2_INTF_MATCH_PKTS	(CLASS_CSR_BASE_ADDR + 0x154)
-+#define CLASS_PHY2_L3_FAIL_PKTS	(CLASS_CSR_BASE_ADDR + 0x158)
-+#define CLASS_PHY2_V4_PKTS	(CLASS_CSR_BASE_ADDR + 0x15c)
-+#define CLASS_PHY2_V6_PKTS	(CLASS_CSR_BASE_ADDR + 0x160)
-+#define CLASS_PHY2_CHKSUM_ERR_PKTS	(CLASS_CSR_BASE_ADDR + 0x164)
-+#define CLASS_PHY2_TTL_ERR_PKTS	(CLASS_CSR_BASE_ADDR + 0x168)
-+#define CLASS_PHY3_RX_PKTS	(CLASS_CSR_BASE_ADDR + 0x16c)
-+#define CLASS_PHY3_TX_PKTS	(CLASS_CSR_BASE_ADDR + 0x170)
-+#define CLASS_PHY3_LP_FAIL_PKTS	(CLASS_CSR_BASE_ADDR + 0x174)
-+#define CLASS_PHY3_INTF_FAIL_PKTS	(CLASS_CSR_BASE_ADDR + 0x178)
-+#define CLASS_PHY3_INTF_MATCH_PKTS	(CLASS_CSR_BASE_ADDR + 0x17c)
-+#define CLASS_PHY3_L3_FAIL_PKTS	(CLASS_CSR_BASE_ADDR + 0x180)
-+#define CLASS_PHY3_V4_PKTS	(CLASS_CSR_BASE_ADDR + 0x184)
-+#define CLASS_PHY3_V6_PKTS	(CLASS_CSR_BASE_ADDR + 0x188)
-+#define CLASS_PHY3_CHKSUM_ERR_PKTS	(CLASS_CSR_BASE_ADDR + 0x18c)
-+#define CLASS_PHY3_TTL_ERR_PKTS	(CLASS_CSR_BASE_ADDR + 0x190)
-+#define CLASS_PHY1_ICMP_PKTS	(CLASS_CSR_BASE_ADDR + 0x194)
-+#define CLASS_PHY1_IGMP_PKTS	(CLASS_CSR_BASE_ADDR + 0x198)
-+#define CLASS_PHY1_TCP_PKTS	(CLASS_CSR_BASE_ADDR + 0x19c)
-+#define CLASS_PHY1_UDP_PKTS	(CLASS_CSR_BASE_ADDR + 0x1a0)
-+#define CLASS_PHY2_ICMP_PKTS	(CLASS_CSR_BASE_ADDR + 0x1a4)
-+#define CLASS_PHY2_IGMP_PKTS	(CLASS_CSR_BASE_ADDR + 0x1a8)
-+#define CLASS_PHY2_TCP_PKTS	(CLASS_CSR_BASE_ADDR + 0x1ac)
-+#define CLASS_PHY2_UDP_PKTS	(CLASS_CSR_BASE_ADDR + 0x1b0)
-+#define CLASS_PHY3_ICMP_PKTS	(CLASS_CSR_BASE_ADDR + 0x1b4)
-+#define CLASS_PHY3_IGMP_PKTS	(CLASS_CSR_BASE_ADDR + 0x1b8)
-+#define CLASS_PHY3_TCP_PKTS	(CLASS_CSR_BASE_ADDR + 0x1bc)
-+#define CLASS_PHY3_UDP_PKTS	(CLASS_CSR_BASE_ADDR + 0x1c0)
-+#define CLASS_PHY4_ICMP_PKTS	(CLASS_CSR_BASE_ADDR + 0x1c4)
-+#define CLASS_PHY4_IGMP_PKTS	(CLASS_CSR_BASE_ADDR + 0x1c8)
-+#define CLASS_PHY4_TCP_PKTS	(CLASS_CSR_BASE_ADDR + 0x1cc)
-+#define CLASS_PHY4_UDP_PKTS	(CLASS_CSR_BASE_ADDR + 0x1d0)
-+#define CLASS_PHY4_RX_PKTS	(CLASS_CSR_BASE_ADDR + 0x1d4)
-+#define CLASS_PHY4_TX_PKTS	(CLASS_CSR_BASE_ADDR + 0x1d8)
-+#define CLASS_PHY4_LP_FAIL_PKTS	(CLASS_CSR_BASE_ADDR + 0x1dc)
-+#define CLASS_PHY4_INTF_FAIL_PKTS	(CLASS_CSR_BASE_ADDR + 0x1e0)
-+#define CLASS_PHY4_INTF_MATCH_PKTS	(CLASS_CSR_BASE_ADDR + 0x1e4)
-+#define CLASS_PHY4_L3_FAIL_PKTS	(CLASS_CSR_BASE_ADDR + 0x1e8)
-+#define CLASS_PHY4_V4_PKTS	(CLASS_CSR_BASE_ADDR + 0x1ec)
-+#define CLASS_PHY4_V6_PKTS	(CLASS_CSR_BASE_ADDR + 0x1f0)
-+#define CLASS_PHY4_CHKSUM_ERR_PKTS	(CLASS_CSR_BASE_ADDR + 0x1f4)
-+#define CLASS_PHY4_TTL_ERR_PKTS	(CLASS_CSR_BASE_ADDR + 0x1f8)
-+
-+#define CLASS_PE_SYS_CLK_RATIO	(CLASS_CSR_BASE_ADDR + 0x200)
-+#define CLASS_AFULL_THRES	(CLASS_CSR_BASE_ADDR + 0x204)
-+#define CLASS_GAP_BETWEEN_READS	(CLASS_CSR_BASE_ADDR + 0x208)
-+#define CLASS_MAX_BUF_CNT	(CLASS_CSR_BASE_ADDR + 0x20c)
-+#define CLASS_TSQ_FIFO_THRES	(CLASS_CSR_BASE_ADDR + 0x210)
-+#define CLASS_TSQ_MAX_CNT	(CLASS_CSR_BASE_ADDR + 0x214)
-+#define CLASS_IRAM_DATA_0	(CLASS_CSR_BASE_ADDR + 0x218)
-+#define CLASS_IRAM_DATA_1	(CLASS_CSR_BASE_ADDR + 0x21c)
-+#define CLASS_IRAM_DATA_2	(CLASS_CSR_BASE_ADDR + 0x220)
-+#define CLASS_IRAM_DATA_3	(CLASS_CSR_BASE_ADDR + 0x224)
-+
-+#define CLASS_BUS_ACCESS_ADDR	(CLASS_CSR_BASE_ADDR + 0x228)
-+
-+#define CLASS_BUS_ACCESS_WDATA	(CLASS_CSR_BASE_ADDR + 0x22c)
-+#define CLASS_BUS_ACCESS_RDATA	(CLASS_CSR_BASE_ADDR + 0x230)
-+
-+/* (route_entry_size[9:0], route_hash_size[23:16]
-+ * (this is actually ln2(size)))
-+ */
-+#define CLASS_ROUTE_HASH_ENTRY_SIZE	(CLASS_CSR_BASE_ADDR + 0x234)
-+
-+#define CLASS_ROUTE_ENTRY_SIZE(size)	 ((size) & 0x1ff)
-+#define CLASS_ROUTE_HASH_SIZE(hash_bits) (((hash_bits) & 0xff) << 16)
-+
-+#define CLASS_ROUTE_TABLE_BASE	(CLASS_CSR_BASE_ADDR + 0x238)
-+
-+#define CLASS_ROUTE_MULTI	(CLASS_CSR_BASE_ADDR + 0x23c)
-+#define CLASS_SMEM_OFFSET	(CLASS_CSR_BASE_ADDR + 0x240)
-+#define CLASS_LMEM_BUF_SIZE	(CLASS_CSR_BASE_ADDR + 0x244)
-+#define CLASS_VLAN_ID	(CLASS_CSR_BASE_ADDR + 0x248)
-+#define CLASS_BMU1_BUF_FREE	(CLASS_CSR_BASE_ADDR + 0x24c)
-+#define CLASS_USE_TMU_INQ	(CLASS_CSR_BASE_ADDR + 0x250)
-+#define CLASS_VLAN_ID1	(CLASS_CSR_BASE_ADDR + 0x254)
-+
-+#define CLASS_BUS_ACCESS_BASE	(CLASS_CSR_BASE_ADDR + 0x258)
-+#define CLASS_BUS_ACCESS_BASE_MASK	(0xFF000000)
-+/* bit 31:24 of PE peripheral address are stored in CLASS_BUS_ACCESS_BASE */
-+
-+#define CLASS_HIF_PARSE	(CLASS_CSR_BASE_ADDR + 0x25c)
-+
-+#define CLASS_HOST_PE0_GP	(CLASS_CSR_BASE_ADDR + 0x260)
-+#define CLASS_PE0_GP	(CLASS_CSR_BASE_ADDR + 0x264)
-+#define CLASS_HOST_PE1_GP	(CLASS_CSR_BASE_ADDR + 0x268)
-+#define CLASS_PE1_GP	(CLASS_CSR_BASE_ADDR + 0x26c)
-+#define CLASS_HOST_PE2_GP	(CLASS_CSR_BASE_ADDR + 0x270)
-+#define CLASS_PE2_GP	(CLASS_CSR_BASE_ADDR + 0x274)
-+#define CLASS_HOST_PE3_GP	(CLASS_CSR_BASE_ADDR + 0x278)
-+#define CLASS_PE3_GP	(CLASS_CSR_BASE_ADDR + 0x27c)
-+#define CLASS_HOST_PE4_GP	(CLASS_CSR_BASE_ADDR + 0x280)
-+#define CLASS_PE4_GP	(CLASS_CSR_BASE_ADDR + 0x284)
-+#define CLASS_HOST_PE5_GP	(CLASS_CSR_BASE_ADDR + 0x288)
-+#define CLASS_PE5_GP	(CLASS_CSR_BASE_ADDR + 0x28c)
-+
-+#define CLASS_PE_INT_SRC	(CLASS_CSR_BASE_ADDR + 0x290)
-+#define CLASS_PE_INT_ENABLE	(CLASS_CSR_BASE_ADDR + 0x294)
-+
-+#define CLASS_TPID0_TPID1	(CLASS_CSR_BASE_ADDR + 0x298)
-+#define CLASS_TPID2	(CLASS_CSR_BASE_ADDR + 0x29c)
-+
-+#define CLASS_L4_CHKSUM_ADDR	(CLASS_CSR_BASE_ADDR + 0x2a0)
-+
-+#define CLASS_PE0_DEBUG	(CLASS_CSR_BASE_ADDR + 0x2a4)
-+#define CLASS_PE1_DEBUG	(CLASS_CSR_BASE_ADDR + 0x2a8)
-+#define CLASS_PE2_DEBUG	(CLASS_CSR_BASE_ADDR + 0x2ac)
-+#define CLASS_PE3_DEBUG	(CLASS_CSR_BASE_ADDR + 0x2b0)
-+#define CLASS_PE4_DEBUG	(CLASS_CSR_BASE_ADDR + 0x2b4)
-+#define CLASS_PE5_DEBUG	(CLASS_CSR_BASE_ADDR + 0x2b8)
-+
-+#define CLASS_STATE	(CLASS_CSR_BASE_ADDR + 0x2bc)
-+
-+/* CLASS defines */
-+#define CLASS_PBUF_SIZE	0x100	/* Fixed by hardware */
-+#define CLASS_PBUF_HEADER_OFFSET	0x80	/* Can be configured */
-+
-+/* Can be configured */
-+#define CLASS_PBUF0_BASE_ADDR	0x000
-+/* Can be configured */
-+#define CLASS_PBUF1_BASE_ADDR	(CLASS_PBUF0_BASE_ADDR + CLASS_PBUF_SIZE)
-+/* Can be configured */
-+#define CLASS_PBUF2_BASE_ADDR	(CLASS_PBUF1_BASE_ADDR + CLASS_PBUF_SIZE)
-+/* Can be configured */
-+#define CLASS_PBUF3_BASE_ADDR	(CLASS_PBUF2_BASE_ADDR + CLASS_PBUF_SIZE)
-+
-+#define CLASS_PBUF0_HEADER_BASE_ADDR	(CLASS_PBUF0_BASE_ADDR + \
-+						CLASS_PBUF_HEADER_OFFSET)
-+#define CLASS_PBUF1_HEADER_BASE_ADDR	(CLASS_PBUF1_BASE_ADDR + \
-+						CLASS_PBUF_HEADER_OFFSET)
-+#define CLASS_PBUF2_HEADER_BASE_ADDR	(CLASS_PBUF2_BASE_ADDR + \
-+						CLASS_PBUF_HEADER_OFFSET)
-+#define CLASS_PBUF3_HEADER_BASE_ADDR	(CLASS_PBUF3_BASE_ADDR + \
-+						CLASS_PBUF_HEADER_OFFSET)
-+
-+#define CLASS_PE0_RO_DM_ADDR0_VAL	((CLASS_PBUF1_BASE_ADDR << 16) | \
-+						CLASS_PBUF0_BASE_ADDR)
-+#define CLASS_PE0_RO_DM_ADDR1_VAL	((CLASS_PBUF3_BASE_ADDR << 16) | \
-+						CLASS_PBUF2_BASE_ADDR)
-+
-+#define CLASS_PE0_QB_DM_ADDR0_VAL	((CLASS_PBUF1_HEADER_BASE_ADDR << 16) |\
-+						CLASS_PBUF0_HEADER_BASE_ADDR)
-+#define CLASS_PE0_QB_DM_ADDR1_VAL	((CLASS_PBUF3_HEADER_BASE_ADDR << 16) |\
-+						CLASS_PBUF2_HEADER_BASE_ADDR)
-+
-+#define CLASS_ROUTE_SIZE	128
-+#define CLASS_MAX_ROUTE_SIZE	256
-+#define CLASS_ROUTE_HASH_BITS	20
-+#define CLASS_ROUTE_HASH_MASK	(BIT(CLASS_ROUTE_HASH_BITS) - 1)
-+
-+/* Can be configured */
-+#define	CLASS_ROUTE0_BASE_ADDR	0x400
-+/* Can be configured */
-+#define CLASS_ROUTE1_BASE_ADDR	(CLASS_ROUTE0_BASE_ADDR + CLASS_ROUTE_SIZE)
-+/* Can be configured */
-+#define CLASS_ROUTE2_BASE_ADDR	(CLASS_ROUTE1_BASE_ADDR + CLASS_ROUTE_SIZE)
-+/* Can be configured */
-+#define CLASS_ROUTE3_BASE_ADDR	(CLASS_ROUTE2_BASE_ADDR + CLASS_ROUTE_SIZE)
-+
-+#define CLASS_SA_SIZE	128
-+#define CLASS_IPSEC_SA0_BASE_ADDR	0x600
-+/* not used */
-+#define CLASS_IPSEC_SA1_BASE_ADDR  (CLASS_IPSEC_SA0_BASE_ADDR + CLASS_SA_SIZE)
-+/* not used */
-+#define CLASS_IPSEC_SA2_BASE_ADDR  (CLASS_IPSEC_SA1_BASE_ADDR + CLASS_SA_SIZE)
-+/* not used */
-+#define CLASS_IPSEC_SA3_BASE_ADDR  (CLASS_IPSEC_SA2_BASE_ADDR + CLASS_SA_SIZE)
-+
-+/* generic purpose free dmem buffer, last portion of 2K dmem pbuf */
-+#define CLASS_GP_DMEM_BUF_SIZE	(2048 - (CLASS_PBUF_SIZE * 4) - \
-+				(CLASS_ROUTE_SIZE * 4) - (CLASS_SA_SIZE))
-+#define CLASS_GP_DMEM_BUF	((void *)(CLASS_IPSEC_SA0_BASE_ADDR + \
-+					CLASS_SA_SIZE))
-+
-+#define TWO_LEVEL_ROUTE		BIT(0)
-+#define PHYNO_IN_HASH		BIT(1)
-+#define HW_ROUTE_FETCH		BIT(3)
-+#define HW_BRIDGE_FETCH		BIT(5)
-+#define IP_ALIGNED		BIT(6)
-+#define ARC_HIT_CHECK_EN	BIT(7)
-+#define CLASS_TOE		BIT(11)
-+#define HASH_NORMAL		(0 << 12)
-+#define HASH_CRC_PORT		BIT(12)
-+#define HASH_CRC_IP		(2 << 12)
-+#define HASH_CRC_PORT_IP	(3 << 12)
-+#define QB2BUS_LE		BIT(15)
-+
-+#define TCP_CHKSUM_DROP		BIT(0)
-+#define UDP_CHKSUM_DROP		BIT(1)
-+#define IPV4_CHKSUM_DROP	BIT(9)
-+
-+/*CLASS_HIF_PARSE bits*/
-+#define HIF_PKT_CLASS_EN	BIT(0)
-+#define HIF_PKT_OFFSET(ofst)	(((ofst) & 0xF) << 1)
-+
-+struct class_cfg {
-+	u32 toe_mode;
-+	unsigned long route_table_baseaddr;
-+	u32 route_table_hash_bits;
-+	u32 pe_sys_clk_ratio;
-+	u32 resume;
-+};
-+
-+#endif /* _CLASS_CSR_H_ */
---- /dev/null
-+++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/emac_mtip.h
-@@ -0,0 +1,242 @@
-+/*
-+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
-+ * Copyright 2017 NXP
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#ifndef _EMAC_H_
-+#define _EMAC_H_
-+
-+#include <linux/ethtool.h>
-+
-+#define EMAC_IEVENT_REG		0x004
-+#define EMAC_IMASK_REG		0x008
-+#define EMAC_R_DES_ACTIVE_REG	0x010
-+#define EMAC_X_DES_ACTIVE_REG	0x014
-+#define EMAC_ECNTRL_REG		0x024
-+#define EMAC_MII_DATA_REG	0x040
-+#define EMAC_MII_CTRL_REG	0x044
-+#define EMAC_MIB_CTRL_STS_REG	0x064
-+#define EMAC_RCNTRL_REG		0x084
-+#define EMAC_TCNTRL_REG		0x0C4
-+#define EMAC_PHY_ADDR_LOW	0x0E4
-+#define EMAC_PHY_ADDR_HIGH	0x0E8
-+#define EMAC_GAUR		0x120
-+#define EMAC_GALR		0x124
-+#define EMAC_TFWR_STR_FWD	0x144
-+#define EMAC_RX_SECTION_FULL	0x190
-+#define EMAC_RX_SECTION_EMPTY	0x194
-+#define EMAC_TX_SECTION_EMPTY	0x1A0
-+#define EMAC_TRUNC_FL		0x1B0
-+
-+#define RMON_T_DROP	0x200 /* Count of frames not cntd correctly */
-+#define RMON_T_PACKETS	0x204 /* RMON TX packet count */
-+#define RMON_T_BC_PKT	0x208 /* RMON TX broadcast pkts */
-+#define RMON_T_MC_PKT	0x20c /* RMON TX multicast pkts */
-+#define RMON_T_CRC_ALIGN	0x210 /* RMON TX pkts with CRC align err */
-+#define RMON_T_UNDERSIZE	0x214 /* RMON TX pkts < 64 bytes, good CRC */
-+#define RMON_T_OVERSIZE	0x218 /* RMON TX pkts > MAX_FL bytes good CRC */
-+#define RMON_T_FRAG	0x21c /* RMON TX pkts < 64 bytes, bad CRC */
-+#define RMON_T_JAB	0x220 /* RMON TX pkts > MAX_FL bytes, bad CRC */
-+#define RMON_T_COL	0x224 /* RMON TX collision count */
-+#define RMON_T_P64	0x228 /* RMON TX 64 byte pkts */
-+#define RMON_T_P65TO127	0x22c /* RMON TX 65 to 127 byte pkts */
-+#define RMON_T_P128TO255	0x230 /* RMON TX 128 to 255 byte pkts */
-+#define RMON_T_P256TO511	0x234 /* RMON TX 256 to 511 byte pkts */
-+#define RMON_T_P512TO1023	0x238 /* RMON TX 512 to 1023 byte pkts */
-+#define RMON_T_P1024TO2047	0x23c /* RMON TX 1024 to 2047 byte pkts */
-+#define RMON_T_P_GTE2048	0x240 /* RMON TX pkts > 2048 bytes */
-+#define RMON_T_OCTETS	0x244 /* RMON TX octets */
-+#define IEEE_T_DROP	0x248 /* Count of frames not counted crtly */
-+#define IEEE_T_FRAME_OK	0x24c /* Frames tx'd OK */
-+#define IEEE_T_1COL	0x250 /* Frames tx'd with single collision */
-+#define IEEE_T_MCOL	0x254 /* Frames tx'd with multiple collision */
-+#define IEEE_T_DEF	0x258 /* Frames tx'd after deferral delay */
-+#define IEEE_T_LCOL	0x25c /* Frames tx'd with late collision */
-+#define IEEE_T_EXCOL	0x260 /* Frames tx'd with excesv collisions */
-+#define IEEE_T_MACERR	0x264 /* Frames tx'd with TX FIFO underrun */
-+#define IEEE_T_CSERR	0x268 /* Frames tx'd with carrier sense err */
-+#define IEEE_T_SQE	0x26c /* Frames tx'd with SQE err */
-+#define IEEE_T_FDXFC	0x270 /* Flow control pause frames tx'd */
-+#define IEEE_T_OCTETS_OK	0x274 /* Octet count for frames tx'd w/o err */
-+#define RMON_R_PACKETS	0x284 /* RMON RX packet count */
-+#define RMON_R_BC_PKT	0x288 /* RMON RX broadcast pkts */
-+#define RMON_R_MC_PKT	0x28c /* RMON RX multicast pkts */
-+#define RMON_R_CRC_ALIGN	0x290 /* RMON RX pkts with CRC alignment err */
-+#define RMON_R_UNDERSIZE	0x294 /* RMON RX pkts < 64 bytes, good CRC */
-+#define RMON_R_OVERSIZE	0x298 /* RMON RX pkts > MAX_FL bytes good CRC */
-+#define RMON_R_FRAG	0x29c /* RMON RX pkts < 64 bytes, bad CRC */
-+#define RMON_R_JAB	0x2a0 /* RMON RX pkts > MAX_FL bytes, bad CRC */
-+#define RMON_R_RESVD_O	0x2a4 /* Reserved */
-+#define RMON_R_P64	0x2a8 /* RMON RX 64 byte pkts */
-+#define RMON_R_P65TO127	0x2ac /* RMON RX 65 to 127 byte pkts */
-+#define RMON_R_P128TO255	0x2b0 /* RMON RX 128 to 255 byte pkts */
-+#define RMON_R_P256TO511	0x2b4 /* RMON RX 256 to 511 byte pkts */
-+#define RMON_R_P512TO1023	0x2b8 /* RMON RX 512 to 1023 byte pkts */
-+#define RMON_R_P1024TO2047	0x2bc /* RMON RX 1024 to 2047 byte pkts */
-+#define RMON_R_P_GTE2048	0x2c0 /* RMON RX pkts > 2048 bytes */
-+#define RMON_R_OCTETS	0x2c4 /* RMON RX octets */
-+#define IEEE_R_DROP	0x2c8 /* Count frames not counted correctly */
-+#define IEEE_R_FRAME_OK	0x2cc /* Frames rx'd OK */
-+#define IEEE_R_CRC	0x2d0 /* Frames rx'd with CRC err */
-+#define IEEE_R_ALIGN	0x2d4 /* Frames rx'd with alignment err */
-+#define IEEE_R_MACERR	0x2d8 /* Receive FIFO overflow count */
-+#define IEEE_R_FDXFC	0x2dc /* Flow control pause frames rx'd */
-+#define IEEE_R_OCTETS_OK	0x2e0 /* Octet cnt for frames rx'd w/o err */
-+
-+#define EMAC_SMAC_0_0	0x500 /*Supplemental MAC Address 0 (RW).*/
-+#define EMAC_SMAC_0_1	0x504 /*Supplemental MAC Address 0 (RW).*/
-+
-+/* GEMAC definitions and settings */
-+
-+#define EMAC_PORT_0	0
-+#define EMAC_PORT_1	1
-+
-+/* GEMAC Bit definitions */
-+#define EMAC_IEVENT_HBERR		 0x80000000
-+#define EMAC_IEVENT_BABR		 0x40000000
-+#define EMAC_IEVENT_BABT		 0x20000000
-+#define EMAC_IEVENT_GRA			 0x10000000
-+#define EMAC_IEVENT_TXF			 0x08000000
-+#define EMAC_IEVENT_TXB			 0x04000000
-+#define EMAC_IEVENT_RXF			 0x02000000
-+#define EMAC_IEVENT_RXB			 0x01000000
-+#define EMAC_IEVENT_MII			 0x00800000
-+#define EMAC_IEVENT_EBERR		 0x00400000
-+#define EMAC_IEVENT_LC			 0x00200000
-+#define EMAC_IEVENT_RL			 0x00100000
-+#define EMAC_IEVENT_UN			 0x00080000
-+
-+#define EMAC_IMASK_HBERR                 0x80000000
-+#define EMAC_IMASK_BABR                  0x40000000
-+#define EMAC_IMASKT_BABT                 0x20000000
-+#define EMAC_IMASK_GRA                   0x10000000
-+#define EMAC_IMASKT_TXF                  0x08000000
-+#define EMAC_IMASK_TXB                   0x04000000
-+#define EMAC_IMASKT_RXF                  0x02000000
-+#define EMAC_IMASK_RXB                   0x01000000
-+#define EMAC_IMASK_MII                   0x00800000
-+#define EMAC_IMASK_EBERR                 0x00400000
-+#define EMAC_IMASK_LC                    0x00200000
-+#define EMAC_IMASKT_RL                   0x00100000
-+#define EMAC_IMASK_UN                    0x00080000
-+
-+#define EMAC_RCNTRL_MAX_FL_SHIFT         16
-+#define EMAC_RCNTRL_LOOP                 0x00000001
-+#define EMAC_RCNTRL_DRT                  0x00000002
-+#define EMAC_RCNTRL_MII_MODE             0x00000004
-+#define EMAC_RCNTRL_PROM                 0x00000008
-+#define EMAC_RCNTRL_BC_REJ               0x00000010
-+#define EMAC_RCNTRL_FCE                  0x00000020
-+#define EMAC_RCNTRL_RGMII                0x00000040
-+#define EMAC_RCNTRL_SGMII                0x00000080
-+#define EMAC_RCNTRL_RMII                 0x00000100
-+#define EMAC_RCNTRL_RMII_10T             0x00000200
-+#define EMAC_RCNTRL_CRC_FWD		 0x00004000
-+
-+#define EMAC_TCNTRL_GTS                  0x00000001
-+#define EMAC_TCNTRL_HBC                  0x00000002
-+#define EMAC_TCNTRL_FDEN                 0x00000004
-+#define EMAC_TCNTRL_TFC_PAUSE            0x00000008
-+#define EMAC_TCNTRL_RFC_PAUSE            0x00000010
-+
-+#define EMAC_ECNTRL_RESET                0x00000001      /* reset the EMAC */
-+#define EMAC_ECNTRL_ETHER_EN             0x00000002      /* enable the EMAC */
-+#define EMAC_ECNTRL_MAGIC_ENA		 0x00000004
-+#define EMAC_ECNTRL_SLEEP		 0x00000008
-+#define EMAC_ECNTRL_SPEED                0x00000020
-+#define EMAC_ECNTRL_DBSWAP               0x00000100
-+
-+#define EMAC_X_WMRK_STRFWD               0x00000100
-+
-+#define EMAC_X_DES_ACTIVE_TDAR           0x01000000
-+#define EMAC_R_DES_ACTIVE_RDAR           0x01000000
-+
-+#define EMAC_RX_SECTION_EMPTY_V		0x00010006
-+/*
-+ * The possible operating speeds of the MAC, currently supporting 10, 100 and
-+ * 1000Mb modes.
-+ */
-+enum mac_speed {SPEED_10M, SPEED_100M, SPEED_1000M, SPEED_1000M_PCS};
-+
-+/* MII-related definitios */
-+#define EMAC_MII_DATA_ST         0x40000000      /* Start of frame delimiter */
-+#define EMAC_MII_DATA_OP_RD      0x20000000      /* Perform a read operation */
-+#define EMAC_MII_DATA_OP_CL45_RD 0x30000000      /* Perform a read operation */
-+#define EMAC_MII_DATA_OP_WR      0x10000000      /* Perform a write operation */
-+#define EMAC_MII_DATA_OP_CL45_WR 0x10000000      /* Perform a write operation */
-+#define EMAC_MII_DATA_PA_MSK     0x0f800000      /* PHY Address field mask */
-+#define EMAC_MII_DATA_RA_MSK     0x007c0000      /* PHY Register field mask */
-+#define EMAC_MII_DATA_TA         0x00020000      /* Turnaround */
-+#define EMAC_MII_DATA_DATAMSK    0x0000ffff      /* PHY data field */
-+
-+#define EMAC_MII_DATA_RA_SHIFT   18      /* MII Register address bits */
-+#define EMAC_MII_DATA_RA_MASK	 0x1F      /* MII Register address mask */
-+#define EMAC_MII_DATA_PA_SHIFT   23      /* MII PHY address bits */
-+#define EMAC_MII_DATA_PA_MASK    0x1F      /* MII PHY address mask */
-+
-+#define EMAC_MII_DATA_RA(v) (((v) & EMAC_MII_DATA_RA_MASK) << \
-+				EMAC_MII_DATA_RA_SHIFT)
-+#define EMAC_MII_DATA_PA(v) (((v) & EMAC_MII_DATA_RA_MASK) << \
-+				EMAC_MII_DATA_PA_SHIFT)
-+#define EMAC_MII_DATA(v)    ((v) & 0xffff)
-+
-+#define EMAC_MII_SPEED_SHIFT	1
-+#define EMAC_HOLDTIME_SHIFT	8
-+#define EMAC_HOLDTIME_MASK	0x7
-+#define EMAC_HOLDTIME(v)	(((v) & EMAC_HOLDTIME_MASK) << \
-+					EMAC_HOLDTIME_SHIFT)
-+
-+/*
-+ * The Address organisation for the MAC device.  All addresses are split into
-+ * two 32-bit register fields.  The first one (bottom) is the lower 32-bits of
-+ * the address and the other field are the high order bits - this may be 16-bits
-+ * in the case of MAC addresses, or 32-bits for the hash address.
-+ * In terms of memory storage, the first item (bottom) is assumed to be at a
-+ * lower address location than 'top'. i.e. top should be at address location of
-+ * 'bottom' + 4 bytes.
-+ */
-+struct pfe_mac_addr {
-+	u32 bottom;     /* Lower 32-bits of address. */
-+	u32 top;        /* Upper 32-bits of address. */
-+};
-+
-+/*
-+ * The following is the organisation of the address filters section of the MAC
-+ * registers.  The Cadence MAC contains four possible specific address match
-+ * addresses, if an incoming frame corresponds to any one of these four
-+ * addresses then the frame will be copied to memory.
-+ * It is not necessary for all four of the address match registers to be
-+ * programmed, this is application dependent.
-+ */
-+struct spec_addr {
-+	struct pfe_mac_addr one;        /* Specific address register 1. */
-+	struct pfe_mac_addr two;        /* Specific address register 2. */
-+	struct pfe_mac_addr three;      /* Specific address register 3. */
-+	struct pfe_mac_addr four;       /* Specific address register 4. */
-+};
-+
-+struct gemac_cfg {
-+	u32 mode;
-+	u32 speed;
-+	u32 duplex;
-+};
-+
-+/* EMAC Hash size */
-+#define EMAC_HASH_REG_BITS       64
-+
-+#define EMAC_SPEC_ADDR_MAX	4
-+
-+#endif /* _EMAC_H_ */
---- /dev/null
-+++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/gpi.h
-@@ -0,0 +1,86 @@
-+/*
-+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
-+ * Copyright 2017 NXP
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#ifndef _GPI_H_
-+#define _GPI_H_
-+
-+#define GPI_VERSION	0x00
-+#define GPI_CTRL	0x04
-+#define GPI_RX_CONFIG	0x08
-+#define GPI_HDR_SIZE	0x0c
-+#define GPI_BUF_SIZE	0x10
-+#define GPI_LMEM_ALLOC_ADDR	0x14
-+#define GPI_LMEM_FREE_ADDR	0x18
-+#define GPI_DDR_ALLOC_ADDR	0x1c
-+#define GPI_DDR_FREE_ADDR	0x20
-+#define GPI_CLASS_ADDR	0x24
-+#define GPI_DRX_FIFO	0x28
-+#define GPI_TRX_FIFO	0x2c
-+#define GPI_INQ_PKTPTR	0x30
-+#define GPI_DDR_DATA_OFFSET	0x34
-+#define GPI_LMEM_DATA_OFFSET	0x38
-+#define GPI_TMLF_TX	0x4c
-+#define GPI_DTX_ASEQ	0x50
-+#define GPI_FIFO_STATUS	0x54
-+#define GPI_FIFO_DEBUG	0x58
-+#define GPI_TX_PAUSE_TIME	0x5c
-+#define GPI_LMEM_SEC_BUF_DATA_OFFSET	0x60
-+#define GPI_DDR_SEC_BUF_DATA_OFFSET	0x64
-+#define GPI_TOE_CHKSUM_EN	0x68
-+#define GPI_OVERRUN_DROPCNT	0x6c
-+#define GPI_CSR_MTIP_PAUSE_REG		0x74
-+#define GPI_CSR_MTIP_PAUSE_QUANTUM	0x78
-+#define GPI_CSR_RX_CNT			0x7c
-+#define GPI_CSR_TX_CNT			0x80
-+#define GPI_CSR_DEBUG1			0x84
-+#define GPI_CSR_DEBUG2			0x88
-+
-+struct gpi_cfg {
-+	u32 lmem_rtry_cnt;
-+	u32 tmlf_txthres;
-+	u32 aseq_len;
-+	u32 mtip_pause_reg;
-+};
-+
-+/* GPI commons defines */
-+#define GPI_LMEM_BUF_EN	0x1
-+#define GPI_DDR_BUF_EN	0x1
-+
-+/* EGPI 1 defines */
-+#define EGPI1_LMEM_RTRY_CNT	0x40
-+#define EGPI1_TMLF_TXTHRES	0xBC
-+#define EGPI1_ASEQ_LEN	0x50
-+
-+/* EGPI 2 defines */
-+#define EGPI2_LMEM_RTRY_CNT	0x40
-+#define EGPI2_TMLF_TXTHRES	0xBC
-+#define EGPI2_ASEQ_LEN	0x40
-+
-+/* EGPI 3 defines */
-+#define EGPI3_LMEM_RTRY_CNT	0x40
-+#define EGPI3_TMLF_TXTHRES	0xBC
-+#define EGPI3_ASEQ_LEN	0x40
-+
-+/* HGPI defines */
-+#define HGPI_LMEM_RTRY_CNT	0x40
-+#define HGPI_TMLF_TXTHRES	0xBC
-+#define HGPI_ASEQ_LEN	0x40
-+
-+#define EGPI_PAUSE_TIME		0x000007D0
-+#define EGPI_PAUSE_ENABLE	0x40000000
-+#endif /* _GPI_H_ */
---- /dev/null
-+++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/hif.h
-@@ -0,0 +1,100 @@
-+/*
-+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
-+ * Copyright 2017 NXP
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#ifndef _HIF_H_
-+#define _HIF_H_
-+
-+/* @file hif.h.
-+ * hif - PFE hif block control and status register.
-+ * Mapped on CBUS and accessible from all PE's and ARM.
-+ */
-+#define HIF_VERSION	(HIF_BASE_ADDR + 0x00)
-+#define HIF_TX_CTRL	(HIF_BASE_ADDR + 0x04)
-+#define HIF_TX_CURR_BD_ADDR	(HIF_BASE_ADDR + 0x08)
-+#define HIF_TX_ALLOC	(HIF_BASE_ADDR + 0x0c)
-+#define HIF_TX_BDP_ADDR	(HIF_BASE_ADDR + 0x10)
-+#define HIF_TX_STATUS	(HIF_BASE_ADDR + 0x14)
-+#define HIF_RX_CTRL	(HIF_BASE_ADDR + 0x20)
-+#define HIF_RX_BDP_ADDR	(HIF_BASE_ADDR + 0x24)
-+#define HIF_RX_STATUS	(HIF_BASE_ADDR + 0x30)
-+#define HIF_INT_SRC	(HIF_BASE_ADDR + 0x34)
-+#define HIF_INT_ENABLE	(HIF_BASE_ADDR + 0x38)
-+#define HIF_POLL_CTRL	(HIF_BASE_ADDR + 0x3c)
-+#define HIF_RX_CURR_BD_ADDR	(HIF_BASE_ADDR + 0x40)
-+#define HIF_RX_ALLOC	(HIF_BASE_ADDR + 0x44)
-+#define HIF_TX_DMA_STATUS	(HIF_BASE_ADDR + 0x48)
-+#define HIF_RX_DMA_STATUS	(HIF_BASE_ADDR + 0x4c)
-+#define HIF_INT_COAL	(HIF_BASE_ADDR + 0x50)
-+
-+/* HIF_INT_SRC/ HIF_INT_ENABLE control bits */
-+#define HIF_INT		BIT(0)
-+#define HIF_RXBD_INT	BIT(1)
-+#define HIF_RXPKT_INT	BIT(2)
-+#define HIF_TXBD_INT	BIT(3)
-+#define HIF_TXPKT_INT	BIT(4)
-+
-+/* HIF_TX_CTRL bits */
-+#define HIF_CTRL_DMA_EN			BIT(0)
-+#define HIF_CTRL_BDP_POLL_CTRL_EN	BIT(1)
-+#define HIF_CTRL_BDP_CH_START_WSTB	BIT(2)
-+
-+/* HIF_RX_STATUS bits */
-+#define BDP_CSR_RX_DMA_ACTV     BIT(16)
-+
-+/* HIF_INT_ENABLE bits */
-+#define HIF_INT_EN		BIT(0)
-+#define HIF_RXBD_INT_EN		BIT(1)
-+#define HIF_RXPKT_INT_EN	BIT(2)
-+#define HIF_TXBD_INT_EN		BIT(3)
-+#define HIF_TXPKT_INT_EN	BIT(4)
-+
-+/* HIF_POLL_CTRL bits*/
-+#define HIF_RX_POLL_CTRL_CYCLE	0x0400
-+#define HIF_TX_POLL_CTRL_CYCLE	0x0400
-+
-+/* HIF_INT_COAL bits*/
-+#define HIF_INT_COAL_ENABLE	BIT(31)
-+
-+/* Buffer descriptor control bits */
-+#define BD_CTRL_BUFLEN_MASK	0x3fff
-+#define BD_BUF_LEN(x)	((x) & BD_CTRL_BUFLEN_MASK)
-+#define BD_CTRL_CBD_INT_EN	BIT(16)
-+#define BD_CTRL_PKT_INT_EN	BIT(17)
-+#define BD_CTRL_LIFM		BIT(18)
-+#define BD_CTRL_LAST_BD		BIT(19)
-+#define BD_CTRL_DIR		BIT(20)
-+#define BD_CTRL_LMEM_CPY	BIT(21) /* Valid only for HIF_NOCPY */
-+#define BD_CTRL_PKT_XFER	BIT(24)
-+#define BD_CTRL_DESC_EN		BIT(31)
-+#define BD_CTRL_PARSE_DISABLE	BIT(25)
-+#define BD_CTRL_BRFETCH_DISABLE	BIT(26)
-+#define BD_CTRL_RTFETCH_DISABLE	BIT(27)
-+
-+/* Buffer descriptor status bits*/
-+#define BD_STATUS_CONN_ID(x)	((x) & 0xffff)
-+#define BD_STATUS_DIR_PROC_ID	BIT(16)
-+#define BD_STATUS_CONN_ID_EN	BIT(17)
-+#define BD_STATUS_PE2PROC_ID(x)	(((x) & 7) << 18)
-+#define BD_STATUS_LE_DATA	BIT(21)
-+#define BD_STATUS_CHKSUM_EN	BIT(22)
-+
-+/* HIF Buffer descriptor status bits */
-+#define DIR_PROC_ID	BIT(16)
-+#define PROC_ID(id)	((id) << 18)
-+
-+#endif /* _HIF_H_ */
---- /dev/null
-+++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/hif_nocpy.h
-@@ -0,0 +1,50 @@
-+/*
-+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
-+ * Copyright 2017 NXP
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#ifndef _HIF_NOCPY_H_
-+#define _HIF_NOCPY_H_
-+
-+#define HIF_NOCPY_VERSION	(HIF_NOCPY_BASE_ADDR + 0x00)
-+#define HIF_NOCPY_TX_CTRL	(HIF_NOCPY_BASE_ADDR + 0x04)
-+#define HIF_NOCPY_TX_CURR_BD_ADDR	(HIF_NOCPY_BASE_ADDR + 0x08)
-+#define HIF_NOCPY_TX_ALLOC	(HIF_NOCPY_BASE_ADDR + 0x0c)
-+#define HIF_NOCPY_TX_BDP_ADDR	(HIF_NOCPY_BASE_ADDR + 0x10)
-+#define HIF_NOCPY_TX_STATUS	(HIF_NOCPY_BASE_ADDR + 0x14)
-+#define HIF_NOCPY_RX_CTRL	(HIF_NOCPY_BASE_ADDR + 0x20)
-+#define HIF_NOCPY_RX_BDP_ADDR	(HIF_NOCPY_BASE_ADDR + 0x24)
-+#define HIF_NOCPY_RX_STATUS	(HIF_NOCPY_BASE_ADDR + 0x30)
-+#define HIF_NOCPY_INT_SRC	(HIF_NOCPY_BASE_ADDR + 0x34)
-+#define HIF_NOCPY_INT_ENABLE	(HIF_NOCPY_BASE_ADDR + 0x38)
-+#define HIF_NOCPY_POLL_CTRL	(HIF_NOCPY_BASE_ADDR + 0x3c)
-+#define HIF_NOCPY_RX_CURR_BD_ADDR	(HIF_NOCPY_BASE_ADDR + 0x40)
-+#define HIF_NOCPY_RX_ALLOC	(HIF_NOCPY_BASE_ADDR + 0x44)
-+#define HIF_NOCPY_TX_DMA_STATUS	(HIF_NOCPY_BASE_ADDR + 0x48)
-+#define HIF_NOCPY_RX_DMA_STATUS	(HIF_NOCPY_BASE_ADDR + 0x4c)
-+#define HIF_NOCPY_RX_INQ0_PKTPTR	(HIF_NOCPY_BASE_ADDR + 0x50)
-+#define HIF_NOCPY_RX_INQ1_PKTPTR	(HIF_NOCPY_BASE_ADDR + 0x54)
-+#define HIF_NOCPY_TX_PORT_NO	(HIF_NOCPY_BASE_ADDR + 0x60)
-+#define HIF_NOCPY_LMEM_ALLOC_ADDR	(HIF_NOCPY_BASE_ADDR + 0x64)
-+#define HIF_NOCPY_CLASS_ADDR	(HIF_NOCPY_BASE_ADDR + 0x68)
-+#define HIF_NOCPY_TMU_PORT0_ADDR	(HIF_NOCPY_BASE_ADDR + 0x70)
-+#define HIF_NOCPY_TMU_PORT1_ADDR	(HIF_NOCPY_BASE_ADDR + 0x74)
-+#define HIF_NOCPY_TMU_PORT2_ADDR	(HIF_NOCPY_BASE_ADDR + 0x7c)
-+#define HIF_NOCPY_TMU_PORT3_ADDR	(HIF_NOCPY_BASE_ADDR + 0x80)
-+#define HIF_NOCPY_TMU_PORT4_ADDR	(HIF_NOCPY_BASE_ADDR + 0x84)
-+#define HIF_NOCPY_INT_COAL	(HIF_NOCPY_BASE_ADDR + 0x90)
-+
-+#endif /* _HIF_NOCPY_H_ */
---- /dev/null
-+++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/tmu_csr.h
-@@ -0,0 +1,168 @@
-+/*
-+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
-+ * Copyright 2017 NXP
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#ifndef _TMU_CSR_H_
-+#define _TMU_CSR_H_
-+
-+#define TMU_VERSION	(TMU_CSR_BASE_ADDR + 0x000)
-+#define TMU_INQ_WATERMARK	(TMU_CSR_BASE_ADDR + 0x004)
-+#define TMU_PHY_INQ_PKTPTR	(TMU_CSR_BASE_ADDR + 0x008)
-+#define TMU_PHY_INQ_PKTINFO	(TMU_CSR_BASE_ADDR + 0x00c)
-+#define TMU_PHY_INQ_FIFO_CNT	(TMU_CSR_BASE_ADDR + 0x010)
-+#define TMU_SYS_GENERIC_CONTROL	(TMU_CSR_BASE_ADDR + 0x014)
-+#define TMU_SYS_GENERIC_STATUS	(TMU_CSR_BASE_ADDR + 0x018)
-+#define TMU_SYS_GEN_CON0	(TMU_CSR_BASE_ADDR + 0x01c)
-+#define TMU_SYS_GEN_CON1	(TMU_CSR_BASE_ADDR + 0x020)
-+#define TMU_SYS_GEN_CON2	(TMU_CSR_BASE_ADDR + 0x024)
-+#define TMU_SYS_GEN_CON3	(TMU_CSR_BASE_ADDR + 0x028)
-+#define TMU_SYS_GEN_CON4	(TMU_CSR_BASE_ADDR + 0x02c)
-+#define TMU_TEQ_DISABLE_DROPCHK	(TMU_CSR_BASE_ADDR + 0x030)
-+#define TMU_TEQ_CTRL	(TMU_CSR_BASE_ADDR + 0x034)
-+#define TMU_TEQ_QCFG	(TMU_CSR_BASE_ADDR + 0x038)
-+#define TMU_TEQ_DROP_STAT	(TMU_CSR_BASE_ADDR + 0x03c)
-+#define TMU_TEQ_QAVG	(TMU_CSR_BASE_ADDR + 0x040)
-+#define TMU_TEQ_WREG_PROB	(TMU_CSR_BASE_ADDR + 0x044)
-+#define TMU_TEQ_TRANS_STAT	(TMU_CSR_BASE_ADDR + 0x048)
-+#define TMU_TEQ_HW_PROB_CFG0	(TMU_CSR_BASE_ADDR + 0x04c)
-+#define TMU_TEQ_HW_PROB_CFG1	(TMU_CSR_BASE_ADDR + 0x050)
-+#define TMU_TEQ_HW_PROB_CFG2	(TMU_CSR_BASE_ADDR + 0x054)
-+#define TMU_TEQ_HW_PROB_CFG3	(TMU_CSR_BASE_ADDR + 0x058)
-+#define TMU_TEQ_HW_PROB_CFG4	(TMU_CSR_BASE_ADDR + 0x05c)
-+#define TMU_TEQ_HW_PROB_CFG5	(TMU_CSR_BASE_ADDR + 0x060)
-+#define TMU_TEQ_HW_PROB_CFG6	(TMU_CSR_BASE_ADDR + 0x064)
-+#define TMU_TEQ_HW_PROB_CFG7	(TMU_CSR_BASE_ADDR + 0x068)
-+#define TMU_TEQ_HW_PROB_CFG8	(TMU_CSR_BASE_ADDR + 0x06c)
-+#define TMU_TEQ_HW_PROB_CFG9	(TMU_CSR_BASE_ADDR + 0x070)
-+#define TMU_TEQ_HW_PROB_CFG10	(TMU_CSR_BASE_ADDR + 0x074)
-+#define TMU_TEQ_HW_PROB_CFG11	(TMU_CSR_BASE_ADDR + 0x078)
-+#define TMU_TEQ_HW_PROB_CFG12	(TMU_CSR_BASE_ADDR + 0x07c)
-+#define TMU_TEQ_HW_PROB_CFG13	(TMU_CSR_BASE_ADDR + 0x080)
-+#define TMU_TEQ_HW_PROB_CFG14	(TMU_CSR_BASE_ADDR + 0x084)
-+#define TMU_TEQ_HW_PROB_CFG15	(TMU_CSR_BASE_ADDR + 0x088)
-+#define TMU_TEQ_HW_PROB_CFG16	(TMU_CSR_BASE_ADDR + 0x08c)
-+#define TMU_TEQ_HW_PROB_CFG17	(TMU_CSR_BASE_ADDR + 0x090)
-+#define TMU_TEQ_HW_PROB_CFG18	(TMU_CSR_BASE_ADDR + 0x094)
-+#define TMU_TEQ_HW_PROB_CFG19	(TMU_CSR_BASE_ADDR + 0x098)
-+#define TMU_TEQ_HW_PROB_CFG20	(TMU_CSR_BASE_ADDR + 0x09c)
-+#define TMU_TEQ_HW_PROB_CFG21	(TMU_CSR_BASE_ADDR + 0x0a0)
-+#define TMU_TEQ_HW_PROB_CFG22	(TMU_CSR_BASE_ADDR + 0x0a4)
-+#define TMU_TEQ_HW_PROB_CFG23	(TMU_CSR_BASE_ADDR + 0x0a8)
-+#define TMU_TEQ_HW_PROB_CFG24	(TMU_CSR_BASE_ADDR + 0x0ac)
-+#define TMU_TEQ_HW_PROB_CFG25	(TMU_CSR_BASE_ADDR + 0x0b0)
-+#define TMU_TDQ_IIFG_CFG	(TMU_CSR_BASE_ADDR + 0x0b4)
-+/* [9:0] Scheduler Enable for each of the scheduler in the TDQ.
-+ * This is a global Enable for all schedulers in PHY0
-+ */
-+#define TMU_TDQ0_SCH_CTRL	(TMU_CSR_BASE_ADDR + 0x0b8)
-+
-+#define TMU_LLM_CTRL	(TMU_CSR_BASE_ADDR + 0x0bc)
-+#define TMU_LLM_BASE_ADDR	(TMU_CSR_BASE_ADDR + 0x0c0)
-+#define TMU_LLM_QUE_LEN	(TMU_CSR_BASE_ADDR + 0x0c4)
-+#define TMU_LLM_QUE_HEADPTR	(TMU_CSR_BASE_ADDR + 0x0c8)
-+#define TMU_LLM_QUE_TAILPTR	(TMU_CSR_BASE_ADDR + 0x0cc)
-+#define TMU_LLM_QUE_DROPCNT	(TMU_CSR_BASE_ADDR + 0x0d0)
-+#define TMU_INT_EN	(TMU_CSR_BASE_ADDR + 0x0d4)
-+#define TMU_INT_SRC	(TMU_CSR_BASE_ADDR + 0x0d8)
-+#define TMU_INQ_STAT	(TMU_CSR_BASE_ADDR + 0x0dc)
-+#define TMU_CTRL	(TMU_CSR_BASE_ADDR + 0x0e0)
-+
-+/* [31] Mem Access Command. 0 = Internal Memory Read, 1 = Internal memory
-+ * Write [27:24] Byte Enables of the Internal memory access [23:0] Address of
-+ * the internal memory. This address is used to access both the PM and DM of
-+ * all the PE's
-+ */
-+#define TMU_MEM_ACCESS_ADDR	(TMU_CSR_BASE_ADDR + 0x0e4)
-+
-+/* Internal Memory Access Write Data */
-+#define TMU_MEM_ACCESS_WDATA	(TMU_CSR_BASE_ADDR + 0x0e8)
-+/* Internal Memory Access Read Data. The commands are blocked
-+ * at the mem_access only
-+ */
-+#define TMU_MEM_ACCESS_RDATA	(TMU_CSR_BASE_ADDR + 0x0ec)
-+
-+/* [31:0] PHY0 in queue address (must be initialized with one of the
-+ * xxx_INQ_PKTPTR cbus addresses)
-+ */
-+#define TMU_PHY0_INQ_ADDR	(TMU_CSR_BASE_ADDR + 0x0f0)
-+/* [31:0] PHY1 in queue address (must be initialized with one of the
-+ * xxx_INQ_PKTPTR cbus addresses)
-+ */
-+#define TMU_PHY1_INQ_ADDR	(TMU_CSR_BASE_ADDR + 0x0f4)
-+/* [31:0] PHY2 in queue address (must be initialized with one of the
-+ * xxx_INQ_PKTPTR cbus addresses)
-+ */
-+#define TMU_PHY2_INQ_ADDR	(TMU_CSR_BASE_ADDR + 0x0f8)
-+/* [31:0] PHY3 in queue address (must be initialized with one of the
-+ * xxx_INQ_PKTPTR cbus addresses)
-+ */
-+#define TMU_PHY3_INQ_ADDR	(TMU_CSR_BASE_ADDR + 0x0fc)
-+#define TMU_BMU_INQ_ADDR	(TMU_CSR_BASE_ADDR + 0x100)
-+#define TMU_TX_CTRL	(TMU_CSR_BASE_ADDR + 0x104)
-+
-+#define TMU_BUS_ACCESS_WDATA	(TMU_CSR_BASE_ADDR + 0x108)
-+#define TMU_BUS_ACCESS	(TMU_CSR_BASE_ADDR + 0x10c)
-+#define TMU_BUS_ACCESS_RDATA	(TMU_CSR_BASE_ADDR + 0x110)
-+
-+#define TMU_PE_SYS_CLK_RATIO	(TMU_CSR_BASE_ADDR + 0x114)
-+#define TMU_PE_STATUS	(TMU_CSR_BASE_ADDR + 0x118)
-+#define TMU_TEQ_MAX_THRESHOLD	(TMU_CSR_BASE_ADDR + 0x11c)
-+/* [31:0] PHY4 in queue address (must be initialized with one of the
-+ * xxx_INQ_PKTPTR cbus addresses)
-+ */
-+#define TMU_PHY4_INQ_ADDR	(TMU_CSR_BASE_ADDR + 0x134)
-+/* [9:0] Scheduler Enable for each of the scheduler in the TDQ.
-+ * This is a global Enable for all schedulers in PHY1
-+ */
-+#define TMU_TDQ1_SCH_CTRL	(TMU_CSR_BASE_ADDR + 0x138)
-+/* [9:0] Scheduler Enable for each of the scheduler in the TDQ.
-+ * This is a global Enable for all schedulers in PHY2
-+ */
-+#define TMU_TDQ2_SCH_CTRL	(TMU_CSR_BASE_ADDR + 0x13c)
-+/* [9:0] Scheduler Enable for each of the scheduler in the TDQ.
-+ * This is a global Enable for all schedulers in PHY3
-+ */
-+#define TMU_TDQ3_SCH_CTRL	(TMU_CSR_BASE_ADDR + 0x140)
-+#define TMU_BMU_BUF_SIZE	(TMU_CSR_BASE_ADDR + 0x144)
-+/* [31:0] PHY5 in queue address (must be initialized with one of the
-+ * xxx_INQ_PKTPTR cbus addresses)
-+ */
-+#define TMU_PHY5_INQ_ADDR	(TMU_CSR_BASE_ADDR + 0x148)
-+
-+#define SW_RESET		BIT(0)	/* Global software reset */
-+#define INQ_RESET		BIT(2)
-+#define TEQ_RESET		BIT(3)
-+#define TDQ_RESET		BIT(4)
-+#define PE_RESET		BIT(5)
-+#define MEM_INIT		BIT(6)
-+#define MEM_INIT_DONE		BIT(7)
-+#define LLM_INIT		BIT(8)
-+#define LLM_INIT_DONE		BIT(9)
-+#define ECC_MEM_INIT_DONE	BIT(10)
-+
-+struct tmu_cfg {
-+	u32 pe_sys_clk_ratio;
-+	unsigned long llm_base_addr;
-+	u32 llm_queue_len;
-+};
-+
-+/* Not HW related for pfe_ctrl / pfe common defines */
-+#define DEFAULT_MAX_QDEPTH	80
-+#define DEFAULT_Q0_QDEPTH	511 /*We keep one large queue for host tx qos */
-+#define DEFAULT_TMU3_QDEPTH	127
-+
-+#endif /* _TMU_CSR_H_ */
---- /dev/null
-+++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/util_csr.h
-@@ -0,0 +1,61 @@
-+/*
-+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
-+ * Copyright 2017 NXP
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#ifndef _UTIL_CSR_H_
-+#define _UTIL_CSR_H_
-+
-+#define UTIL_VERSION	(UTIL_CSR_BASE_ADDR + 0x000)
-+#define UTIL_TX_CTRL	(UTIL_CSR_BASE_ADDR + 0x004)
-+#define UTIL_INQ_PKTPTR	(UTIL_CSR_BASE_ADDR + 0x010)
-+
-+#define UTIL_HDR_SIZE	(UTIL_CSR_BASE_ADDR + 0x014)
-+
-+#define UTIL_PE0_QB_DM_ADDR0	(UTIL_CSR_BASE_ADDR + 0x020)
-+#define UTIL_PE0_QB_DM_ADDR1	(UTIL_CSR_BASE_ADDR + 0x024)
-+#define UTIL_PE0_RO_DM_ADDR0	(UTIL_CSR_BASE_ADDR + 0x060)
-+#define UTIL_PE0_RO_DM_ADDR1	(UTIL_CSR_BASE_ADDR + 0x064)
-+
-+#define UTIL_MEM_ACCESS_ADDR	(UTIL_CSR_BASE_ADDR + 0x100)
-+#define UTIL_MEM_ACCESS_WDATA	(UTIL_CSR_BASE_ADDR + 0x104)
-+#define UTIL_MEM_ACCESS_RDATA	(UTIL_CSR_BASE_ADDR + 0x108)
-+
-+#define UTIL_TM_INQ_ADDR	(UTIL_CSR_BASE_ADDR + 0x114)
-+#define UTIL_PE_STATUS	(UTIL_CSR_BASE_ADDR + 0x118)
-+
-+#define UTIL_PE_SYS_CLK_RATIO	(UTIL_CSR_BASE_ADDR + 0x200)
-+#define UTIL_AFULL_THRES	(UTIL_CSR_BASE_ADDR + 0x204)
-+#define UTIL_GAP_BETWEEN_READS	(UTIL_CSR_BASE_ADDR + 0x208)
-+#define UTIL_MAX_BUF_CNT	(UTIL_CSR_BASE_ADDR + 0x20c)
-+#define UTIL_TSQ_FIFO_THRES	(UTIL_CSR_BASE_ADDR + 0x210)
-+#define UTIL_TSQ_MAX_CNT	(UTIL_CSR_BASE_ADDR + 0x214)
-+#define UTIL_IRAM_DATA_0	(UTIL_CSR_BASE_ADDR + 0x218)
-+#define UTIL_IRAM_DATA_1	(UTIL_CSR_BASE_ADDR + 0x21c)
-+#define UTIL_IRAM_DATA_2	(UTIL_CSR_BASE_ADDR + 0x220)
-+#define UTIL_IRAM_DATA_3	(UTIL_CSR_BASE_ADDR + 0x224)
-+
-+#define UTIL_BUS_ACCESS_ADDR	(UTIL_CSR_BASE_ADDR + 0x228)
-+#define UTIL_BUS_ACCESS_WDATA	(UTIL_CSR_BASE_ADDR + 0x22c)
-+#define UTIL_BUS_ACCESS_RDATA	(UTIL_CSR_BASE_ADDR + 0x230)
-+
-+#define UTIL_INQ_AFULL_THRES	(UTIL_CSR_BASE_ADDR + 0x234)
-+
-+struct util_cfg {
-+	u32 pe_sys_clk_ratio;
-+};
-+
-+#endif /* _UTIL_CSR_H_ */
---- /dev/null
-+++ b/drivers/staging/fsl_ppfe/include/pfe/pfe.h
-@@ -0,0 +1,372 @@
-+/*
-+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
-+ * Copyright 2017 NXP
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#ifndef _PFE_H_
-+#define _PFE_H_
-+
-+#include "cbus.h"
-+
-+#define CLASS_DMEM_BASE_ADDR(i)	(0x00000000 | ((i) << 20))
-+/*
-+ * Only valid for mem access register interface
-+ */
-+#define CLASS_IMEM_BASE_ADDR(i)	(0x00000000 | ((i) << 20))
-+#define CLASS_DMEM_SIZE	0x00002000
-+#define CLASS_IMEM_SIZE	0x00008000
-+
-+#define TMU_DMEM_BASE_ADDR(i)	(0x00000000 + ((i) << 20))
-+/*
-+ * Only valid for mem access register interface
-+ */
-+#define TMU_IMEM_BASE_ADDR(i)	(0x00000000 + ((i) << 20))
-+#define TMU_DMEM_SIZE	0x00000800
-+#define TMU_IMEM_SIZE	0x00002000
-+
-+#define UTIL_DMEM_BASE_ADDR	0x00000000
-+#define UTIL_DMEM_SIZE	0x00002000
-+
-+#define PE_LMEM_BASE_ADDR	0xc3010000
-+#define PE_LMEM_SIZE	0x8000
-+#define PE_LMEM_END	(PE_LMEM_BASE_ADDR + PE_LMEM_SIZE)
-+
-+#define DMEM_BASE_ADDR	0x00000000
-+#define DMEM_SIZE	0x2000	/* TMU has less... */
-+#define DMEM_END	(DMEM_BASE_ADDR + DMEM_SIZE)
-+
-+#define PMEM_BASE_ADDR	0x00010000
-+#define PMEM_SIZE	0x8000	/* TMU has less... */
-+#define PMEM_END	(PMEM_BASE_ADDR + PMEM_SIZE)
-+
-+/* These check memory ranges from PE point of view/memory map */
-+#define IS_DMEM(addr, len)				\
-+	({ typeof(addr) addr_ = (addr);			\
-+	((unsigned long)(addr_) >= DMEM_BASE_ADDR) &&	\
-+	(((unsigned long)(addr_) + (len)) <= DMEM_END); })
-+
-+#define IS_PMEM(addr, len)				\
-+	({ typeof(addr) addr_ = (addr);			\
-+	((unsigned long)(addr_) >= PMEM_BASE_ADDR) &&	\
-+	(((unsigned long)(addr_) + (len)) <= PMEM_END); })
-+
-+#define IS_PE_LMEM(addr, len)				\
-+	({ typeof(addr) addr_ = (addr);			\
-+	((unsigned long)(addr_) >=			\
-+	PE_LMEM_BASE_ADDR) &&				\
-+	(((unsigned long)(addr_) +			\
-+	(len)) <= PE_LMEM_END); })
-+
-+#define IS_PFE_LMEM(addr, len)				\
-+	({ typeof(addr) addr_ = (addr);			\
-+	((unsigned long)(addr_) >=			\
-+	CBUS_VIRT_TO_PFE(LMEM_BASE_ADDR)) &&		\
-+	(((unsigned long)(addr_) + (len)) <=		\
-+	CBUS_VIRT_TO_PFE(LMEM_END)); })
-+
-+#define __IS_PHYS_DDR(addr, len)			\
-+	({ typeof(addr) addr_ = (addr);			\
-+	((unsigned long)(addr_) >=			\
-+	DDR_PHYS_BASE_ADDR) &&				\
-+	(((unsigned long)(addr_) + (len)) <=		\
-+	DDR_PHYS_END); })
-+
-+#define IS_PHYS_DDR(addr, len)	__IS_PHYS_DDR(DDR_PFE_TO_PHYS(addr), len)
-+
-+/*
-+ * If using a run-time virtual address for the cbus base address use this code
-+ */
-+extern void *cbus_base_addr;
-+extern void *ddr_base_addr;
-+extern unsigned long ddr_phys_base_addr;
-+extern unsigned int ddr_size;
-+
-+#define CBUS_BASE_ADDR	cbus_base_addr
-+#define DDR_PHYS_BASE_ADDR	ddr_phys_base_addr
-+#define DDR_BASE_ADDR	ddr_base_addr
-+#define DDR_SIZE	ddr_size
-+
-+#define DDR_PHYS_END	(DDR_PHYS_BASE_ADDR + DDR_SIZE)
-+
-+#define LS1012A_PFE_RESET_WA	/*
-+				 * PFE doesn't have global reset and re-init
-+				 * should takecare few things to make PFE
-+				 * functional after reset
-+				 */
-+#define PFE_CBUS_PHYS_BASE_ADDR	0xc0000000	/* CBUS physical base address
-+						 * as seen by PE's.
-+						 */
-+/* CBUS physical base address as seen by PE's. */
-+#define PFE_CBUS_PHYS_BASE_ADDR_FROM_PFE	0xc0000000
-+
-+#define DDR_PHYS_TO_PFE(p)	(((unsigned long int)(p)) & 0x7FFFFFFF)
-+#define DDR_PFE_TO_PHYS(p)	(((unsigned long int)(p)) | 0x80000000)
-+#define CBUS_PHYS_TO_PFE(p)	(((p) - PFE_CBUS_PHYS_BASE_ADDR) + \
-+				PFE_CBUS_PHYS_BASE_ADDR_FROM_PFE)
-+/* Translates to PFE address map */
-+
-+#define DDR_PHYS_TO_VIRT(p)	(((p) - DDR_PHYS_BASE_ADDR) + DDR_BASE_ADDR)
-+#define DDR_VIRT_TO_PHYS(v)	(((v) - DDR_BASE_ADDR) + DDR_PHYS_BASE_ADDR)
-+#define DDR_VIRT_TO_PFE(p)	(DDR_PHYS_TO_PFE(DDR_VIRT_TO_PHYS(p)))
-+
-+#define CBUS_VIRT_TO_PFE(v)	(((v) - CBUS_BASE_ADDR) + \
-+				PFE_CBUS_PHYS_BASE_ADDR)
-+#define CBUS_PFE_TO_VIRT(p)	(((unsigned long int)(p) - \
-+				PFE_CBUS_PHYS_BASE_ADDR) + CBUS_BASE_ADDR)
-+
-+/* The below part of the code is used in QOS control driver from host */
-+#define TMU_APB_BASE_ADDR       0xc1000000      /* TMU base address seen by
-+						 * pe's
-+						 */
-+
-+enum {
-+	CLASS0_ID = 0,
-+	CLASS1_ID,
-+	CLASS2_ID,
-+	CLASS3_ID,
-+	CLASS4_ID,
-+	CLASS5_ID,
-+	TMU0_ID,
-+	TMU1_ID,
-+	TMU2_ID,
-+	TMU3_ID,
-+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
-+	UTIL_ID,
-+#endif
-+	MAX_PE
-+};
-+
-+#define CLASS_MASK	(BIT(CLASS0_ID) | BIT(CLASS1_ID) |\
-+			BIT(CLASS2_ID) | BIT(CLASS3_ID) |\
-+			BIT(CLASS4_ID) | BIT(CLASS5_ID))
-+#define CLASS_MAX_ID	CLASS5_ID
-+
-+#define TMU_MASK	(BIT(TMU0_ID) | BIT(TMU1_ID) |\
-+			BIT(TMU3_ID))
-+
-+#define TMU_MAX_ID	TMU3_ID
-+
-+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
-+#define UTIL_MASK	BIT(UTIL_ID)
-+#endif
-+
-+struct pe_status {
-+	u32	cpu_state;
-+	u32	activity_counter;
-+	u32	rx;
-+	union {
-+	u32	tx;
-+	u32	tmu_qstatus;
-+	};
-+	u32	drop;
-+#if defined(CFG_PE_DEBUG)
-+	u32	debug_indicator;
-+	u32	debug[16];
-+#endif
-+} __aligned(16);
-+
-+struct pe_sync_mailbox {
-+	u32 stop;
-+	u32 stopped;
-+};
-+
-+/* Drop counter definitions */
-+
-+#define	CLASS_NUM_DROP_COUNTERS	13
-+#define	UTIL_NUM_DROP_COUNTERS	8
-+
-+/* PE information.
-+ * Structure containing PE's specific information. It is used to create
-+ * generic C functions common to all PE's.
-+ * Before using the library functions this structure needs to be initialized
-+ * with the different registers virtual addresses
-+ * (according to the ARM MMU mmaping). The default initialization supports a
-+ * virtual == physical mapping.
-+ */
-+struct pe_info {
-+	u32 dmem_base_addr;	/* PE's dmem base address */
-+	u32 pmem_base_addr;	/* PE's pmem base address */
-+	u32 pmem_size;	/* PE's pmem size */
-+
-+	void *mem_access_wdata;	/* PE's _MEM_ACCESS_WDATA register
-+				 * address
-+				 */
-+	void *mem_access_addr;	/* PE's _MEM_ACCESS_ADDR register
-+				 * address
-+				 */
-+	void *mem_access_rdata;	/* PE's _MEM_ACCESS_RDATA register
-+				 * address
-+				 */
-+};
-+
-+void pe_lmem_read(u32 *dst, u32 len, u32 offset);
-+void pe_lmem_write(u32 *src, u32 len, u32 offset);
-+
-+void pe_dmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len);
-+void pe_pmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len);
-+
-+u32 pe_pmem_read(int id, u32 addr, u8 size);
-+
-+void pe_dmem_write(int id, u32 val, u32 addr, u8 size);
-+u32 pe_dmem_read(int id, u32 addr, u8 size);
-+void class_pe_lmem_memcpy_to32(u32 dst, const void *src, unsigned int len);
-+void class_pe_lmem_memset(u32 dst, int val, unsigned int len);
-+void class_bus_write(u32 val, u32 addr, u8 size);
-+u32 class_bus_read(u32 addr, u8 size);
-+
-+#define class_bus_readl(addr)	class_bus_read(addr, 4)
-+#define class_bus_readw(addr)	class_bus_read(addr, 2)
-+#define class_bus_readb(addr)	class_bus_read(addr, 1)
-+
-+#define class_bus_writel(val, addr)	class_bus_write(val, addr, 4)
-+#define class_bus_writew(val, addr)	class_bus_write(val, addr, 2)
-+#define class_bus_writeb(val, addr)	class_bus_write(val, addr, 1)
-+
-+#define pe_dmem_readl(id, addr)	pe_dmem_read(id, addr, 4)
-+#define pe_dmem_readw(id, addr)	pe_dmem_read(id, addr, 2)
-+#define pe_dmem_readb(id, addr)	pe_dmem_read(id, addr, 1)
-+
-+#define pe_dmem_writel(id, val, addr)	pe_dmem_write(id, val, addr, 4)
-+#define pe_dmem_writew(id, val, addr)	pe_dmem_write(id, val, addr, 2)
-+#define pe_dmem_writeb(id, val, addr)	pe_dmem_write(id, val, addr, 1)
-+
-+/*int pe_load_elf_section(int id, const void *data, elf32_shdr *shdr); */
-+int pe_load_elf_section(int id, const void *data, struct elf32_shdr *shdr,
-+			struct device *dev);
-+
-+void pfe_lib_init(void *cbus_base, void *ddr_base, unsigned long ddr_phys_base,
-+		  unsigned int ddr_size);
-+void bmu_init(void *base, struct BMU_CFG *cfg);
-+void bmu_reset(void *base);
-+void bmu_enable(void *base);
-+void bmu_disable(void *base);
-+void bmu_set_config(void *base, struct BMU_CFG *cfg);
-+
-+/*
-+ * An enumerated type for loopback values.  This can be one of three values, no
-+ * loopback -normal operation, local loopback with internal loopback module of
-+ * MAC or PHY loopback which is through the external PHY.
-+ */
-+#ifndef __MAC_LOOP_ENUM__
-+#define __MAC_LOOP_ENUM__
-+enum mac_loop {LB_NONE, LB_EXT, LB_LOCAL};
-+#endif
-+
-+void gemac_init(void *base, void *config);
-+void gemac_disable_rx_checksum_offload(void *base);
-+void gemac_enable_rx_checksum_offload(void *base);
-+void gemac_set_speed(void *base, enum mac_speed gem_speed);
-+void gemac_set_duplex(void *base, int duplex);
-+void gemac_set_mode(void *base, int mode);
-+void gemac_enable(void *base);
-+void gemac_tx_disable(void *base);
-+void gemac_tx_enable(void *base);
-+void gemac_disable(void *base);
-+void gemac_reset(void *base);
-+void gemac_set_address(void *base, struct spec_addr *addr);
-+struct spec_addr gemac_get_address(void *base);
-+void gemac_set_loop(void *base, enum mac_loop gem_loop);
-+void gemac_set_laddr1(void *base, struct pfe_mac_addr *address);
-+void gemac_set_laddr2(void *base, struct pfe_mac_addr *address);
-+void gemac_set_laddr3(void *base, struct pfe_mac_addr *address);
-+void gemac_set_laddr4(void *base, struct pfe_mac_addr *address);
-+void gemac_set_laddrN(void *base, struct pfe_mac_addr *address,
-+		      unsigned int entry_index);
-+void gemac_clear_laddr1(void *base);
-+void gemac_clear_laddr2(void *base);
-+void gemac_clear_laddr3(void *base);
-+void gemac_clear_laddr4(void *base);
-+void gemac_clear_laddrN(void *base, unsigned int entry_index);
-+struct pfe_mac_addr gemac_get_hash(void *base);
-+void gemac_set_hash(void *base, struct pfe_mac_addr *hash);
-+struct pfe_mac_addr gem_get_laddr1(void *base);
-+struct pfe_mac_addr gem_get_laddr2(void *base);
-+struct pfe_mac_addr gem_get_laddr3(void *base);
-+struct pfe_mac_addr gem_get_laddr4(void *base);
-+struct pfe_mac_addr gem_get_laddrN(void *base, unsigned int entry_index);
-+void gemac_set_config(void *base, struct gemac_cfg *cfg);
-+void gemac_allow_broadcast(void *base);
-+void gemac_no_broadcast(void *base);
-+void gemac_enable_1536_rx(void *base);
-+void gemac_disable_1536_rx(void *base);
-+void gemac_set_rx_max_fl(void *base, int mtu);
-+void gemac_enable_rx_jmb(void *base);
-+void gemac_disable_rx_jmb(void *base);
-+void gemac_enable_stacked_vlan(void *base);
-+void gemac_disable_stacked_vlan(void *base);
-+void gemac_enable_pause_rx(void *base);
-+void gemac_disable_pause_rx(void *base);
-+void gemac_enable_copy_all(void *base);
-+void gemac_disable_copy_all(void *base);
-+void gemac_set_bus_width(void *base, int width);
-+void gemac_set_wol(void *base, u32 wol_conf);
-+
-+void gpi_init(void *base, struct gpi_cfg *cfg);
-+void gpi_reset(void *base);
-+void gpi_enable(void *base);
-+void gpi_disable(void *base);
-+void gpi_set_config(void *base, struct gpi_cfg *cfg);
-+
-+void class_init(struct class_cfg *cfg);
-+void class_reset(void);
-+void class_enable(void);
-+void class_disable(void);
-+void class_set_config(struct class_cfg *cfg);
-+
-+void tmu_reset(void);
-+void tmu_init(struct tmu_cfg *cfg);
-+void tmu_enable(u32 pe_mask);
-+void tmu_disable(u32 pe_mask);
-+u32  tmu_qstatus(u32 if_id);
-+u32  tmu_pkts_processed(u32 if_id);
-+
-+void util_init(struct util_cfg *cfg);
-+void util_reset(void);
-+void util_enable(void);
-+void util_disable(void);
-+
-+void hif_init(void);
-+void hif_tx_enable(void);
-+void hif_tx_disable(void);
-+void hif_rx_enable(void);
-+void hif_rx_disable(void);
-+
-+/* Get Chip Revision level
-+ *
-+ */
-+static inline unsigned int CHIP_REVISION(void)
-+{
-+	/*For LS1012A return always 1 */
-+	return 1;
-+}
-+
-+/* Start HIF rx DMA
-+ *
-+ */
-+static inline void hif_rx_dma_start(void)
-+{
-+	writel(HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB, HIF_RX_CTRL);
-+}
-+
-+/* Start HIF tx DMA
-+ *
-+ */
-+static inline void hif_tx_dma_start(void)
-+{
-+	writel(HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB, HIF_TX_CTRL);
-+}
-+
-+#endif /* _PFE_H_ */
---- /dev/null
-+++ b/drivers/staging/fsl_ppfe/pfe_cdev.c
-@@ -0,0 +1,258 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+/*
-+ * Copyright 2018 NXP
-+ */
-+
-+/* @pfe_cdev.c.
-+ *  Dummy device representing the PFE US in userspace.
-+ *  - used for interacting with the kernel layer for link status
-+ */
-+
-+#include <linux/eventfd.h>
-+#include <linux/irqreturn.h>
-+#include <linux/io.h>
-+#include <asm/irq.h>
-+
-+#include "pfe_cdev.h"
-+#include "pfe_mod.h"
-+
-+static int pfe_majno;
-+static struct class *pfe_char_class;
-+static struct device *pfe_char_dev;
-+struct eventfd_ctx *g_trigger;
-+
-+struct pfe_shared_info link_states[PFE_CDEV_ETH_COUNT];
-+
-+static int pfe_cdev_open(struct inode *inp, struct file *fp)
-+{
-+	pr_debug("PFE CDEV device opened.\n");
-+	return 0;
-+}
-+
-+static ssize_t pfe_cdev_read(struct file *fp, char *buf,
-+			     size_t len, loff_t *off)
-+{
-+	int ret = 0;
-+
-+	pr_info("PFE CDEV attempt copying (%zu) size of user.\n",
-+		sizeof(link_states));
-+
-+	pr_debug("Dump link_state on screen before copy_to_user\n");
-+	for (; ret < PFE_CDEV_ETH_COUNT; ret++) {
-+		pr_debug("%u  %u", link_states[ret].phy_id,
-+			 link_states[ret].state);
-+		pr_debug("\n");
-+	}
-+
-+	/* Copy to user the value in buffer sized len */
-+	ret = copy_to_user(buf, &link_states, sizeof(link_states));
-+	if (ret != 0) {
-+		pr_err("Failed to send (%d)bytes of (%zu) requested.\n",
-+		       ret, len);
-+		return -EFAULT;
-+	}
-+
-+	/* offset set back to 0 as there is contextual reading offset */
-+	*off = 0;
-+	pr_debug("Read of (%zu) bytes performed.\n", sizeof(link_states));
-+
-+	return sizeof(link_states);
-+}
-+
-+/**
-+ * This function is for getting some commands from user through non-IOCTL
-+ * channel. It can used to configure the device.
-+ * TODO: To be filled in future, if require duplex communication with user
-+ * space.
-+ */
-+static ssize_t pfe_cdev_write(struct file *fp, const char *buf,
-+			      size_t len, loff_t *off)
-+{
-+	pr_info("PFE CDEV Write operation not supported!\n");
-+
-+	return -EFAULT;
-+}
-+
-+static int pfe_cdev_release(struct inode *inp, struct file *fp)
-+{
-+	if (g_trigger) {
-+		free_irq(pfe->hif_irq, g_trigger);
-+		eventfd_ctx_put(g_trigger);
-+		g_trigger = NULL;
-+	}
-+
-+	pr_info("PFE_CDEV: Device successfully closed\n");
-+	return 0;
-+}
-+
-+/*
-+ * hif_us_isr-
-+ * This ISR routine processes Rx/Tx done interrupts from the HIF hardware block
-+ */
-+static irqreturn_t hif_us_isr(int irq, void *arg)
-+{
-+	struct eventfd_ctx *trigger = (struct eventfd_ctx *)arg;
-+	int int_status;
-+	int int_enable_mask;
-+
-+	/*Read hif interrupt source register */
-+	int_status = readl_relaxed(HIF_INT_SRC);
-+	int_enable_mask = readl_relaxed(HIF_INT_ENABLE);
-+
-+	if ((int_status & HIF_INT) == 0)
-+		return IRQ_NONE;
-+
-+	if (int_status & HIF_RXPKT_INT) {
-+		int_enable_mask &= ~(HIF_RXPKT_INT);
-+		/* Disable interrupts, they will be enabled after
-+		 * they are serviced
-+		 */
-+		writel_relaxed(int_enable_mask, HIF_INT_ENABLE);
-+
-+		eventfd_signal(trigger, 1);
-+	}
-+
-+	return IRQ_HANDLED;
-+}
-+
-+#define PFE_INTR_COAL_USECS	100
-+static long pfe_cdev_ioctl(struct file *fp, unsigned int cmd,
-+			   unsigned long arg)
-+{
-+	int ret = -EFAULT;
-+	int __user *argp = (int __user *)arg;
-+
-+	pr_debug("PFE CDEV IOCTL Called with cmd=(%u)\n", cmd);
-+
-+	switch (cmd) {
-+	case PFE_CDEV_ETH0_STATE_GET:
-+		/* Return an unsigned int (link state) for ETH0 */
-+		*argp = link_states[0].state;
-+		pr_debug("Returning state=%d for ETH0\n", *argp);
-+		ret = 0;
-+		break;
-+	case PFE_CDEV_ETH1_STATE_GET:
-+		/* Return an unsigned int (link state) for ETH0 */
-+		*argp = link_states[1].state;
-+		pr_debug("Returning state=%d for ETH1\n", *argp);
-+		ret = 0;
-+		break;
-+	case PFE_CDEV_HIF_INTR_EN:
-+		/* Return success/failure */
-+		g_trigger = eventfd_ctx_fdget(*argp);
-+		if (IS_ERR(g_trigger))
-+			return PTR_ERR(g_trigger);
-+		ret = request_irq(pfe->hif_irq, hif_us_isr, 0, "pfe_hif",
-+				  g_trigger);
-+		if (ret) {
-+			pr_err("%s: failed to get the hif IRQ = %d\n",
-+			       __func__, pfe->hif_irq);
-+			eventfd_ctx_put(g_trigger);
-+			g_trigger = NULL;
-+		}
-+		writel((PFE_INTR_COAL_USECS * (pfe->ctrl.sys_clk / 1000)) |
-+			HIF_INT_COAL_ENABLE, HIF_INT_COAL);
-+
-+		pr_debug("request_irq for hif interrupt: %d\n", pfe->hif_irq);
-+		ret = 0;
-+		break;
-+	default:
-+		pr_info("Unsupport cmd (%d) for PFE CDEV.\n", cmd);
-+		break;
-+	};
-+
-+	return ret;
-+}
-+
-+static unsigned int pfe_cdev_poll(struct file *fp,
-+				  struct poll_table_struct *wait)
-+{
-+	pr_info("PFE CDEV poll method not supported\n");
-+	return 0;
-+}
-+
-+static const struct file_operations pfe_cdev_fops = {
-+	.open = pfe_cdev_open,
-+	.read = pfe_cdev_read,
-+	.write = pfe_cdev_write,
-+	.release = pfe_cdev_release,
-+	.unlocked_ioctl = pfe_cdev_ioctl,
-+	.poll = pfe_cdev_poll,
-+};
-+
-+int pfe_cdev_init(void)
-+{
-+	int ret;
-+
-+	pr_debug("PFE CDEV initialization begin\n");
-+
-+	/* Register the major number for the device */
-+	pfe_majno = register_chrdev(0, PFE_CDEV_NAME, &pfe_cdev_fops);
-+	if (pfe_majno < 0) {
-+		pr_err("Unable to register PFE CDEV. PFE CDEV not available\n");
-+		ret = pfe_majno;
-+		goto cleanup;
-+	}
-+
-+	pr_debug("PFE CDEV assigned major number: %d\n", pfe_majno);
-+
-+	/* Register the class for the device */
-+	pfe_char_class = class_create(THIS_MODULE, PFE_CLASS_NAME);
-+	if (IS_ERR(pfe_char_class)) {
-+		pr_err(
-+		"Failed to init class for PFE CDEV. PFE CDEV not available.\n");
-+		ret = PTR_ERR(pfe_char_class);
-+		goto cleanup;
-+	}
-+
-+	pr_debug("PFE CDEV Class created successfully.\n");
-+
-+	/* Create the device without any parent and without any callback data */
-+	    pfe_char_dev = device_create(pfe_char_class, NULL,
-+					 MKDEV(pfe_majno, 0), NULL,
-+					 PFE_CDEV_NAME);
-+	if (IS_ERR(pfe_char_dev)) {
-+		pr_err("Unable to PFE CDEV device. PFE CDEV not available.\n");
-+		ret = PTR_ERR(pfe_char_dev);
-+		goto cleanup;
-+	}
-+
-+	/* Information structure being shared with the userspace */
-+	memset(link_states, 0, sizeof(struct pfe_shared_info) *
-+			PFE_CDEV_ETH_COUNT);
-+
-+	pr_info("PFE CDEV created: %s\n", PFE_CDEV_NAME);
-+
-+	ret = 0;
-+	return ret;
-+
-+cleanup:
-+	if (!IS_ERR(pfe_char_class))
-+		class_destroy(pfe_char_class);
-+
-+	if (pfe_majno > 0)
-+		unregister_chrdev(pfe_majno, PFE_CDEV_NAME);
-+
-+	return ret;
-+}
-+
-+void pfe_cdev_exit(void)
-+{
-+	if (!IS_ERR(pfe_char_dev))
-+		device_destroy(pfe_char_class, MKDEV(pfe_majno, 0));
-+
-+	if (!IS_ERR(pfe_char_class)) {
-+		class_unregister(pfe_char_class);
-+		class_destroy(pfe_char_class);
-+	}
-+
-+	if (pfe_majno > 0)
-+		unregister_chrdev(pfe_majno, PFE_CDEV_NAME);
-+
-+	/* reset the variables */
-+	pfe_majno = 0;
-+	pfe_char_class = NULL;
-+	pfe_char_dev = NULL;
-+
-+	pr_info("PFE CDEV Removed.\n");
-+}
---- /dev/null
-+++ b/drivers/staging/fsl_ppfe/pfe_cdev.h
-@@ -0,0 +1,41 @@
-+/* SPDX-License-Identifier: GPL-2.0+ */
-+/*
-+ * Copyright 2018 NXP
-+ */
-+
-+#ifndef _PFE_CDEV_H_
-+#define _PFE_CDEV_H_
-+
-+#include <linux/init.h>
-+#include <linux/device.h>
-+#include <linux/err.h>
-+#include <linux/kernel.h>
-+#include <linux/fs.h>
-+#include <linux/uaccess.h>
-+#include <linux/poll.h>
-+
-+#define  PFE_CDEV_NAME "pfe_us_cdev"
-+#define  PFE_CLASS_NAME  "ppfe_us"
-+
-+/* Extracted from ls1012a_pfe_platform_data, there are 3 interfaces which are
-+ * supported by PFE driver. Should be updated if number of eth devices are
-+ * changed.
-+ */
-+#define PFE_CDEV_ETH_COUNT 3
-+
-+struct pfe_shared_info {
-+	uint32_t phy_id; /* Link phy ID */
-+	uint8_t state;  /* Has either 0 or 1 */
-+};
-+
-+extern struct pfe_shared_info link_states[PFE_CDEV_ETH_COUNT];
-+
-+/* IOCTL Commands */
-+#define PFE_CDEV_ETH0_STATE_GET		_IOR('R', 0, int)
-+#define PFE_CDEV_ETH1_STATE_GET		_IOR('R', 1, int)
-+#define PFE_CDEV_HIF_INTR_EN		_IOWR('R', 2, int)
-+
-+int pfe_cdev_init(void);
-+void pfe_cdev_exit(void);
-+
-+#endif /* _PFE_CDEV_H_ */
---- /dev/null
-+++ b/drivers/staging/fsl_ppfe/pfe_ctrl.c
-@@ -0,0 +1,226 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+/*
-+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
-+ * Copyright 2017 NXP
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/sched.h>
-+#include <linux/module.h>
-+#include <linux/list.h>
-+#include <linux/kthread.h>
-+
-+#include "pfe_mod.h"
-+#include "pfe_ctrl.h"
-+
-+#define TIMEOUT_MS	1000
-+
-+int relax(unsigned long end)
-+{
-+	if (time_after(jiffies, end)) {
-+		if (time_after(jiffies, end + (TIMEOUT_MS * HZ) / 1000))
-+			return -1;
-+
-+		if (need_resched())
-+			schedule();
-+	}
-+
-+	return 0;
-+}
-+
-+void pfe_ctrl_suspend(struct pfe_ctrl *ctrl)
-+{
-+	int id;
-+
-+	mutex_lock(&ctrl->mutex);
-+
-+	for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++)
-+		pe_dmem_write(id, cpu_to_be32(0x1), CLASS_DM_RESUME, 4);
-+
-+	for (id = TMU0_ID; id <= TMU_MAX_ID; id++) {
-+		if (id == TMU2_ID)
-+			continue;
-+		pe_dmem_write(id, cpu_to_be32(0x1), TMU_DM_RESUME, 4);
-+	}
-+
-+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
-+	pe_dmem_write(UTIL_ID, cpu_to_be32(0x1), UTIL_DM_RESUME, 4);
-+#endif
-+	mutex_unlock(&ctrl->mutex);
-+}
-+
-+void pfe_ctrl_resume(struct pfe_ctrl *ctrl)
-+{
-+	int pe_mask = CLASS_MASK | TMU_MASK;
-+
-+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
-+	pe_mask |= UTIL_MASK;
-+#endif
-+	mutex_lock(&ctrl->mutex);
-+	pe_start(&pfe->ctrl, pe_mask);
-+	mutex_unlock(&ctrl->mutex);
-+}
-+
-+/* PE sync stop.
-+ * Stops packet processing for a list of PE's (specified using a bitmask).
-+ * The caller must hold ctrl->mutex.
-+ *
-+ * @param ctrl		Control context
-+ * @param pe_mask	Mask of PE id's to stop
-+ *
-+ */
-+int pe_sync_stop(struct pfe_ctrl *ctrl, int pe_mask)
-+{
-+	struct pe_sync_mailbox *mbox;
-+	int pe_stopped = 0;
-+	unsigned long end = jiffies + 2;
-+	int i;
-+
-+	pe_mask &= 0x2FF;  /*Exclude Util + TMU2 */
-+
-+	for (i = 0; i < MAX_PE; i++)
-+		if (pe_mask & (1 << i)) {
-+			mbox = (void *)ctrl->sync_mailbox_baseaddr[i];
-+
-+			pe_dmem_write(i, cpu_to_be32(0x1), (unsigned
-+					long)&mbox->stop, 4);
-+		}
-+
-+	while (pe_stopped != pe_mask) {
-+		for (i = 0; i < MAX_PE; i++)
-+			if ((pe_mask & (1 << i)) && !(pe_stopped & (1 << i))) {
-+				mbox = (void *)ctrl->sync_mailbox_baseaddr[i];
-+
-+				if (pe_dmem_read(i, (unsigned
-+					long)&mbox->stopped, 4) &
-+					cpu_to_be32(0x1))
-+					pe_stopped |= (1 << i);
-+			}
-+
-+		if (relax(end) < 0)
-+			goto err;
-+	}
-+
-+	return 0;
-+
-+err:
-+	pr_err("%s: timeout, %x %x\n", __func__, pe_mask, pe_stopped);
-+
-+	for (i = 0; i < MAX_PE; i++)
-+		if (pe_mask & (1 << i)) {
-+			mbox = (void *)ctrl->sync_mailbox_baseaddr[i];
-+
-+			pe_dmem_write(i, cpu_to_be32(0x0), (unsigned
-+					long)&mbox->stop, 4);
-+	}
-+
-+	return -EIO;
-+}
-+
-+/* PE start.
-+ * Starts packet processing for a list of PE's (specified using a bitmask).
-+ * The caller must hold ctrl->mutex.
-+ *
-+ * @param ctrl		Control context
-+ * @param pe_mask	Mask of PE id's to start
-+ *
-+ */
-+void pe_start(struct pfe_ctrl *ctrl, int pe_mask)
-+{
-+	struct pe_sync_mailbox *mbox;
-+	int i;
-+
-+	for (i = 0; i < MAX_PE; i++)
-+		if (pe_mask & (1 << i)) {
-+			mbox = (void *)ctrl->sync_mailbox_baseaddr[i];
-+
-+			pe_dmem_write(i, cpu_to_be32(0x0), (unsigned
-+					long)&mbox->stop, 4);
-+		}
-+}
-+
-+/* This function will ensure all PEs are put in to idle state */
-+int pe_reset_all(struct pfe_ctrl *ctrl)
-+{
-+	struct pe_sync_mailbox *mbox;
-+	int pe_stopped = 0;
-+	unsigned long end = jiffies + 2;
-+	int i;
-+	int pe_mask  = CLASS_MASK | TMU_MASK;
-+
-+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
-+	pe_mask |= UTIL_MASK;
-+#endif
-+
-+	for (i = 0; i < MAX_PE; i++)
-+		if (pe_mask & (1 << i)) {
-+			mbox = (void *)ctrl->sync_mailbox_baseaddr[i];
-+
-+			pe_dmem_write(i, cpu_to_be32(0x2), (unsigned
-+					long)&mbox->stop, 4);
-+		}
-+
-+	while (pe_stopped != pe_mask) {
-+		for (i = 0; i < MAX_PE; i++)
-+			if ((pe_mask & (1 << i)) && !(pe_stopped & (1 << i))) {
-+				mbox = (void *)ctrl->sync_mailbox_baseaddr[i];
-+
-+				if (pe_dmem_read(i, (unsigned long)
-+							&mbox->stopped, 4) &
-+						cpu_to_be32(0x1))
-+					pe_stopped |= (1 << i);
-+			}
-+
-+		if (relax(end) < 0)
-+			goto err;
-+	}
-+
-+	return 0;
-+
-+err:
-+	pr_err("%s: timeout, %x %x\n", __func__, pe_mask, pe_stopped);
-+	return -EIO;
-+}
-+
-+int pfe_ctrl_init(struct pfe *pfe)
-+{
-+	struct pfe_ctrl *ctrl = &pfe->ctrl;
-+	int id;
-+
-+	pr_info("%s\n", __func__);
-+
-+	mutex_init(&ctrl->mutex);
-+	spin_lock_init(&ctrl->lock);
-+
-+	for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++) {
-+		ctrl->sync_mailbox_baseaddr[id] = CLASS_DM_SYNC_MBOX;
-+		ctrl->msg_mailbox_baseaddr[id] = CLASS_DM_MSG_MBOX;
-+	}
-+
-+	for (id = TMU0_ID; id <= TMU_MAX_ID; id++) {
-+		if (id == TMU2_ID)
-+			continue;
-+		ctrl->sync_mailbox_baseaddr[id] = TMU_DM_SYNC_MBOX;
-+		ctrl->msg_mailbox_baseaddr[id] = TMU_DM_MSG_MBOX;
-+	}
-+
-+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
-+	ctrl->sync_mailbox_baseaddr[UTIL_ID] = UTIL_DM_SYNC_MBOX;
-+	ctrl->msg_mailbox_baseaddr[UTIL_ID] = UTIL_DM_MSG_MBOX;
-+#endif
-+
-+	ctrl->hash_array_baseaddr = pfe->ddr_baseaddr + ROUTE_TABLE_BASEADDR;
-+	ctrl->hash_array_phys_baseaddr = pfe->ddr_phys_baseaddr +
-+						ROUTE_TABLE_BASEADDR;
-+
-+	ctrl->dev = pfe->dev;
-+
-+	pr_info("%s finished\n", __func__);
-+
-+	return 0;
-+}
-+
-+void pfe_ctrl_exit(struct pfe *pfe)
-+{
-+	pr_info("%s\n", __func__);
-+}
---- /dev/null
-+++ b/drivers/staging/fsl_ppfe/pfe_ctrl.h
-@@ -0,0 +1,100 @@
-+/* SPDX-License-Identifier: GPL-2.0+ */
-+/*
-+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
-+ * Copyright 2017 NXP
-+ */
-+
-+#ifndef _PFE_CTRL_H_
-+#define _PFE_CTRL_H_
-+
-+#include <linux/dmapool.h>
-+
-+#include "pfe/pfe.h"
-+
-+#define DMA_BUF_SIZE_128	0x80	/* enough for 1 conntracks */
-+#define DMA_BUF_SIZE_256	0x100
-+/* enough for 2 conntracks, 1 bridge entry or 1 multicast entry */
-+#define DMA_BUF_SIZE_512	0x200
-+/* 512bytes dma allocated buffers used by rtp relay feature */
-+#define DMA_BUF_MIN_ALIGNMENT	8
-+#define DMA_BUF_BOUNDARY	(4 * 1024)
-+/* bursts can not cross 4k boundary */
-+
-+#define CMD_TX_ENABLE	0x0501
-+#define CMD_TX_DISABLE	0x0502
-+
-+#define CMD_RX_LRO		0x0011
-+#define CMD_PKTCAP_ENABLE       0x0d01
-+#define CMD_QM_EXPT_RATE	0x020c
-+
-+#define CLASS_DM_SH_STATIC		(0x800)
-+#define CLASS_DM_CPU_TICKS		(CLASS_DM_SH_STATIC)
-+#define CLASS_DM_SYNC_MBOX		(0x808)
-+#define CLASS_DM_MSG_MBOX		(0x810)
-+#define CLASS_DM_DROP_CNTR		(0x820)
-+#define CLASS_DM_RESUME			(0x854)
-+#define CLASS_DM_PESTATUS		(0x860)
-+#define CLASS_DM_CRC_VALIDATED		(0x14b0)
-+
-+#define TMU_DM_SH_STATIC		(0x80)
-+#define TMU_DM_CPU_TICKS		(TMU_DM_SH_STATIC)
-+#define TMU_DM_SYNC_MBOX		(0x88)
-+#define TMU_DM_MSG_MBOX			(0x90)
-+#define TMU_DM_RESUME			(0xA0)
-+#define TMU_DM_PESTATUS			(0xB0)
-+#define TMU_DM_CONTEXT			(0x300)
-+#define TMU_DM_TX_TRANS			(0x480)
-+
-+#define UTIL_DM_SH_STATIC		(0x0)
-+#define UTIL_DM_CPU_TICKS		(UTIL_DM_SH_STATIC)
-+#define UTIL_DM_SYNC_MBOX		(0x8)
-+#define UTIL_DM_MSG_MBOX		(0x10)
-+#define UTIL_DM_DROP_CNTR		(0x20)
-+#define UTIL_DM_RESUME			(0x40)
-+#define UTIL_DM_PESTATUS		(0x50)
-+
-+struct pfe_ctrl {
-+	struct mutex mutex; /* to serialize pfe control access */
-+	spinlock_t lock;
-+
-+	void *dma_pool;
-+	void *dma_pool_512;
-+	void *dma_pool_128;
-+
-+	struct device *dev;
-+
-+	void *hash_array_baseaddr;		/*
-+						 * Virtual base address of
-+						 * the conntrack hash array
-+						 */
-+	unsigned long hash_array_phys_baseaddr; /*
-+						 * Physical base address of
-+						 * the conntrack hash array
-+						 */
-+
-+	int (*event_cb)(u16, u16, u16*);
-+
-+	unsigned long sync_mailbox_baseaddr[MAX_PE]; /*
-+						      * Sync mailbox PFE
-+						      * internal address,
-+						      * initialized
-+						      * when parsing elf images
-+						      */
-+	unsigned long msg_mailbox_baseaddr[MAX_PE]; /*
-+						     * Msg mailbox PFE internal
-+						     * address, initialized
-+						     * when parsing elf images
-+						     */
-+	unsigned int sys_clk;			/* AXI clock value, in KHz */
-+};
-+
-+int pfe_ctrl_init(struct pfe *pfe);
-+void pfe_ctrl_exit(struct pfe *pfe);
-+int pe_sync_stop(struct pfe_ctrl *ctrl, int pe_mask);
-+void pe_start(struct pfe_ctrl *ctrl, int pe_mask);
-+int pe_reset_all(struct pfe_ctrl *ctrl);
-+void pfe_ctrl_suspend(struct pfe_ctrl *ctrl);
-+void pfe_ctrl_resume(struct pfe_ctrl *ctrl);
-+int relax(unsigned long end);
-+
-+#endif /* _PFE_CTRL_H_ */
---- /dev/null
-+++ b/drivers/staging/fsl_ppfe/pfe_debugfs.c
-@@ -0,0 +1,99 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+/*
-+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
-+ * Copyright 2017 NXP
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/debugfs.h>
-+#include <linux/platform_device.h>
-+
-+#include "pfe_mod.h"
-+
-+static int dmem_show(struct seq_file *s, void *unused)
-+{
-+	u32 dmem_addr, val;
-+	int id = (long int)s->private;
-+	int i;
-+
-+	for (dmem_addr = 0; dmem_addr < CLASS_DMEM_SIZE; dmem_addr += 8 * 4) {
-+		seq_printf(s, "%04x:", dmem_addr);
-+
-+		for (i = 0; i < 8; i++) {
-+			val = pe_dmem_read(id, dmem_addr + i * 4, 4);
-+			seq_printf(s, " %02x %02x %02x %02x", val & 0xff,
-+				   (val >> 8) & 0xff, (val >> 16) & 0xff,
-+				   (val >> 24) & 0xff);
-+		}
-+
-+		seq_puts(s, "\n");
-+	}
-+
-+	return 0;
-+}
-+
-+static int dmem_open(struct inode *inode, struct file *file)
-+{
-+	return single_open(file, dmem_show, inode->i_private);
-+}
-+
-+static const struct file_operations dmem_fops = {
-+	.open		= dmem_open,
-+	.read		= seq_read,
-+	.llseek		= seq_lseek,
-+	.release	= single_release,
-+};
-+
-+int pfe_debugfs_init(struct pfe *pfe)
-+{
-+	struct dentry *d;
-+
-+	pr_info("%s\n", __func__);
-+
-+	pfe->dentry = debugfs_create_dir("pfe", NULL);
-+	if (IS_ERR_OR_NULL(pfe->dentry))
-+		goto err_dir;
-+
-+	d = debugfs_create_file("pe0_dmem", 0444, pfe->dentry, (void *)0,
-+				&dmem_fops);
-+	if (IS_ERR_OR_NULL(d))
-+		goto err_pe;
-+
-+	d = debugfs_create_file("pe1_dmem", 0444, pfe->dentry, (void *)1,
-+				&dmem_fops);
-+	if (IS_ERR_OR_NULL(d))
-+		goto err_pe;
-+
-+	d = debugfs_create_file("pe2_dmem", 0444, pfe->dentry, (void *)2,
-+				&dmem_fops);
-+	if (IS_ERR_OR_NULL(d))
-+		goto err_pe;
-+
-+	d = debugfs_create_file("pe3_dmem", 0444, pfe->dentry, (void *)3,
-+				&dmem_fops);
-+	if (IS_ERR_OR_NULL(d))
-+		goto err_pe;
-+
-+	d = debugfs_create_file("pe4_dmem", 0444, pfe->dentry, (void *)4,
-+				&dmem_fops);
-+	if (IS_ERR_OR_NULL(d))
-+		goto err_pe;
-+
-+	d = debugfs_create_file("pe5_dmem", 0444, pfe->dentry, (void *)5,
-+				&dmem_fops);
-+	if (IS_ERR_OR_NULL(d))
-+		goto err_pe;
-+
-+	return 0;
-+
-+err_pe:
-+	debugfs_remove_recursive(pfe->dentry);
-+
-+err_dir:
-+	return -1;
-+}
-+
-+void pfe_debugfs_exit(struct pfe *pfe)
-+{
-+	debugfs_remove_recursive(pfe->dentry);
-+}
---- /dev/null
-+++ b/drivers/staging/fsl_ppfe/pfe_debugfs.h
-@@ -0,0 +1,13 @@
-+/* SPDX-License-Identifier: GPL-2.0+ */
-+/*
-+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
-+ * Copyright 2017 NXP
-+ */
-+
-+#ifndef _PFE_DEBUGFS_H_
-+#define _PFE_DEBUGFS_H_
-+
-+int pfe_debugfs_init(struct pfe *pfe);
-+void pfe_debugfs_exit(struct pfe *pfe);
-+
-+#endif /* _PFE_DEBUGFS_H_ */
---- /dev/null
-+++ b/drivers/staging/fsl_ppfe/pfe_eth.c
-@@ -0,0 +1,2591 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+/*
-+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
-+ * Copyright 2017 NXP
-+ */
-+
-+/* @pfe_eth.c.
-+ *  Ethernet driver for to handle exception path for PFE.
-+ *  - uses HIF functions to send/receive packets.
-+ *  - uses ctrl function to start/stop interfaces.
-+ *  - uses direct register accesses to control phy operation.
-+ */
-+#include <linux/version.h>
-+#include <linux/kernel.h>
-+#include <linux/interrupt.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/dmapool.h>
-+#include <linux/netdevice.h>
-+#include <linux/etherdevice.h>
-+#include <linux/ethtool.h>
-+#include <linux/mii.h>
-+#include <linux/phy.h>
-+#include <linux/timer.h>
-+#include <linux/hrtimer.h>
-+#include <linux/platform_device.h>
-+
-+#include <net/ip.h>
-+#include <net/sock.h>
-+
-+#include <linux/of.h>
-+#include <linux/of_mdio.h>
-+
-+#include <linux/io.h>
-+#include <asm/irq.h>
-+#include <linux/delay.h>
-+#include <linux/regmap.h>
-+#include <linux/i2c.h>
-+#include <linux/sys_soc.h>
-+
-+#if defined(CONFIG_NF_CONNTRACK_MARK)
-+#include <net/netfilter/nf_conntrack.h>
-+#endif
-+
-+#include "pfe_mod.h"
-+#include "pfe_eth.h"
-+#include "pfe_cdev.h"
-+
-+#define LS1012A_REV_1_0		0x87040010
-+
-+bool pfe_use_old_dts_phy;
-+bool pfe_errata_a010897;
-+
-+static void *cbus_emac_base[3];
-+static void *cbus_gpi_base[3];
-+
-+/* Forward Declaration */
-+static void pfe_eth_exit_one(struct pfe_eth_priv_s *priv);
-+static void pfe_eth_flush_tx(struct pfe_eth_priv_s *priv);
-+static void pfe_eth_flush_txQ(struct pfe_eth_priv_s *priv, int tx_q_num, int
-+				from_tx, int n_desc);
-+
-+/* MDIO registers */
-+#define MDIO_SGMII_CR			0x00
-+#define MDIO_SGMII_SR			0x01
-+#define MDIO_SGMII_DEV_ABIL_SGMII	0x04
-+#define MDIO_SGMII_LINK_TMR_L		0x12
-+#define MDIO_SGMII_LINK_TMR_H		0x13
-+#define MDIO_SGMII_IF_MODE		0x14
-+
-+/* SGMII Control defines */
-+#define SGMII_CR_RST			0x8000
-+#define SGMII_CR_AN_EN			0x1000
-+#define SGMII_CR_RESTART_AN		0x0200
-+#define SGMII_CR_FD			0x0100
-+#define SGMII_CR_SPEED_SEL1_1G		0x0040
-+#define SGMII_CR_DEF_VAL		(SGMII_CR_AN_EN | SGMII_CR_FD | \
-+					 SGMII_CR_SPEED_SEL1_1G)
-+
-+/* SGMII IF Mode */
-+#define SGMII_DUPLEX_HALF		0x10
-+#define SGMII_SPEED_10MBPS		0x00
-+#define SGMII_SPEED_100MBPS		0x04
-+#define SGMII_SPEED_1GBPS		0x08
-+#define SGMII_USE_SGMII_AN		0x02
-+#define SGMII_EN			0x01
-+
-+/* SGMII Device Ability for SGMII */
-+#define SGMII_DEV_ABIL_ACK		0x4000
-+#define SGMII_DEV_ABIL_EEE_CLK_STP_EN	0x0100
-+#define SGMII_DEV_ABIL_SGMII		0x0001
-+
-+unsigned int gemac_regs[] = {
-+	0x0004, /* Interrupt event */
-+	0x0008, /* Interrupt mask */
-+	0x0024, /* Ethernet control */
-+	0x0064, /* MIB Control/Status */
-+	0x0084, /* Receive control/status */
-+	0x00C4, /* Transmit control */
-+	0x00E4, /* Physical address low */
-+	0x00E8, /* Physical address high */
-+	0x0144, /* Transmit FIFO Watermark and Store and Forward Control*/
-+	0x0190, /* Receive FIFO Section Full Threshold */
-+	0x01A0, /* Transmit FIFO Section Empty Threshold */
-+	0x01B0, /* Frame Truncation Length */
-+};
-+
-+const struct soc_device_attribute ls1012a_rev1_soc_attr[] = {
-+	{ .family = "QorIQ LS1012A",
-+	  .soc_id = "svr:0x87040010",
-+	  .revision = "1.0",
-+	  .data = NULL },
-+	{ },
-+};
-+
-+/********************************************************************/
-+/*                   SYSFS INTERFACE				    */
-+/********************************************************************/
-+
-+#ifdef PFE_ETH_NAPI_STATS
-+/*
-+ * pfe_eth_show_napi_stats
-+ */
-+static ssize_t pfe_eth_show_napi_stats(struct device *dev,
-+				       struct device_attribute *attr,
-+				       char *buf)
-+{
-+	struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev));
-+	ssize_t len = 0;
-+
-+	len += sprintf(buf + len, "sched:  %u\n",
-+			priv->napi_counters[NAPI_SCHED_COUNT]);
-+	len += sprintf(buf + len, "poll:   %u\n",
-+			priv->napi_counters[NAPI_POLL_COUNT]);
-+	len += sprintf(buf + len, "packet: %u\n",
-+			priv->napi_counters[NAPI_PACKET_COUNT]);
-+	len += sprintf(buf + len, "budget: %u\n",
-+			priv->napi_counters[NAPI_FULL_BUDGET_COUNT]);
-+	len += sprintf(buf + len, "desc:   %u\n",
-+			priv->napi_counters[NAPI_DESC_COUNT]);
-+
-+	return len;
-+}
-+
-+/*
-+ * pfe_eth_set_napi_stats
-+ */
-+static ssize_t pfe_eth_set_napi_stats(struct device *dev,
-+				      struct device_attribute *attr,
-+				      const char *buf, size_t count)
-+{
-+	struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev));
-+
-+	memset(priv->napi_counters, 0, sizeof(priv->napi_counters));
-+
-+	return count;
-+}
-+#endif
-+#ifdef PFE_ETH_TX_STATS
-+/* pfe_eth_show_tx_stats
-+ *
-+ */
-+static ssize_t pfe_eth_show_tx_stats(struct device *dev,
-+				     struct device_attribute *attr,
-+				     char *buf)
-+{
-+	struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev));
-+	ssize_t len = 0;
-+	int i;
-+
-+	len += sprintf(buf + len, "TX queues stats:\n");
-+
-+	for (i = 0; i < emac_txq_cnt; i++) {
-+		struct netdev_queue *tx_queue = netdev_get_tx_queue(priv->ndev,
-+									i);
-+
-+		len += sprintf(buf + len, "\n");
-+		__netif_tx_lock_bh(tx_queue);
-+
-+		hif_tx_lock(&pfe->hif);
-+		len += sprintf(buf + len,
-+				"Queue %2d :  credits               = %10d\n"
-+				, i, hif_lib_tx_credit_avail(pfe, priv->id, i));
-+		len += sprintf(buf + len,
-+				 "            tx packets            = %10d\n"
-+				,  pfe->tmu_credit.tx_packets[priv->id][i]);
-+		hif_tx_unlock(&pfe->hif);
-+
-+		/* Don't output additionnal stats if queue never used */
-+		if (!pfe->tmu_credit.tx_packets[priv->id][i])
-+			goto skip;
-+
-+		len += sprintf(buf + len,
-+				 "            clean_fail            = %10d\n"
-+				, priv->clean_fail[i]);
-+		len += sprintf(buf + len,
-+				 "            stop_queue            = %10d\n"
-+				, priv->stop_queue_total[i]);
-+		len += sprintf(buf + len,
-+				 "            stop_queue_hif        = %10d\n"
-+				, priv->stop_queue_hif[i]);
-+		len += sprintf(buf + len,
-+				"            stop_queue_hif_client = %10d\n"
-+				, priv->stop_queue_hif_client[i]);
-+		len += sprintf(buf + len,
-+				 "            stop_queue_credit     = %10d\n"
-+				, priv->stop_queue_credit[i]);
-+skip:
-+		__netif_tx_unlock_bh(tx_queue);
-+	}
-+	return len;
-+}
-+
-+/* pfe_eth_set_tx_stats
-+ *
-+ */
-+static ssize_t pfe_eth_set_tx_stats(struct device *dev,
-+				    struct device_attribute *attr,
-+				    const char *buf, size_t count)
-+{
-+	struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev));
-+	int i;
-+
-+	for (i = 0; i < emac_txq_cnt; i++) {
-+		struct netdev_queue *tx_queue = netdev_get_tx_queue(priv->ndev,
-+									i);
-+
-+		__netif_tx_lock_bh(tx_queue);
-+		priv->clean_fail[i] = 0;
-+		priv->stop_queue_total[i] = 0;
-+		priv->stop_queue_hif[i] = 0;
-+		priv->stop_queue_hif_client[i] = 0;
-+		priv->stop_queue_credit[i] = 0;
-+		__netif_tx_unlock_bh(tx_queue);
-+	}
-+
-+	return count;
-+}
-+#endif
-+/* pfe_eth_show_txavail
-+ *
-+ */
-+static ssize_t pfe_eth_show_txavail(struct device *dev,
-+				    struct device_attribute *attr,
-+				    char *buf)
-+{
-+	struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev));
-+	ssize_t len = 0;
-+	int i;
-+
-+	for (i = 0; i < emac_txq_cnt; i++) {
-+		struct netdev_queue *tx_queue = netdev_get_tx_queue(priv->ndev,
-+									i);
-+
-+		__netif_tx_lock_bh(tx_queue);
-+
-+		len += sprintf(buf + len, "%d",
-+				hif_lib_tx_avail(&priv->client, i));
-+
-+		__netif_tx_unlock_bh(tx_queue);
-+
-+		if (i == (emac_txq_cnt - 1))
-+			len += sprintf(buf + len, "\n");
-+		else
-+			len += sprintf(buf + len, " ");
-+	}
-+
-+	return len;
-+}
-+
-+/* pfe_eth_show_default_priority
-+ *
-+ */
-+static ssize_t pfe_eth_show_default_priority(struct device *dev,
-+					     struct device_attribute *attr,
-+						char *buf)
-+{
-+	struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev));
-+	unsigned long flags;
-+	int rc;
-+
-+	spin_lock_irqsave(&priv->lock, flags);
-+	rc = sprintf(buf, "%d\n", priv->default_priority);
-+	spin_unlock_irqrestore(&priv->lock, flags);
-+
-+	return rc;
-+}
-+
-+/* pfe_eth_set_default_priority
-+ *
-+ */
-+
-+static ssize_t pfe_eth_set_default_priority(struct device *dev,
-+					    struct device_attribute *attr,
-+					    const char *buf, size_t count)
-+{
-+	struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev));
-+	unsigned long flags;
-+
-+	spin_lock_irqsave(&priv->lock, flags);
-+	priv->default_priority = kstrtoul(buf, 0, 0);
-+	spin_unlock_irqrestore(&priv->lock, flags);
-+
-+	return count;
-+}
-+
-+static DEVICE_ATTR(txavail, 0444, pfe_eth_show_txavail, NULL);
-+static DEVICE_ATTR(default_priority, 0644, pfe_eth_show_default_priority,
-+			pfe_eth_set_default_priority);
-+
-+#ifdef PFE_ETH_NAPI_STATS
-+static DEVICE_ATTR(napi_stats, 0644, pfe_eth_show_napi_stats,
-+			pfe_eth_set_napi_stats);
-+#endif
-+
-+#ifdef PFE_ETH_TX_STATS
-+static DEVICE_ATTR(tx_stats, 0644, pfe_eth_show_tx_stats,
-+			pfe_eth_set_tx_stats);
-+#endif
-+
-+/*
-+ * pfe_eth_sysfs_init
-+ *
-+ */
-+static int pfe_eth_sysfs_init(struct net_device *ndev)
-+{
-+	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
-+	int err;
-+
-+	/* Initialize the default values */
-+
-+	/*
-+	 * By default, packets without conntrack will use this default low
-+	 * priority queue
-+	 */
-+	priv->default_priority = 0;
-+
-+	/* Create our sysfs files */
-+	err = device_create_file(&ndev->dev, &dev_attr_default_priority);
-+	if (err) {
-+		netdev_err(ndev,
-+			   "failed to create default_priority sysfs files\n");
-+		goto err_priority;
-+	}
-+
-+	err = device_create_file(&ndev->dev, &dev_attr_txavail);
-+	if (err) {
-+		netdev_err(ndev,
-+			   "failed to create default_priority sysfs files\n");
-+		goto err_txavail;
-+	}
-+
-+#ifdef PFE_ETH_NAPI_STATS
-+	err = device_create_file(&ndev->dev, &dev_attr_napi_stats);
-+	if (err) {
-+		netdev_err(ndev, "failed to create napi stats sysfs files\n");
-+		goto err_napi;
-+	}
-+#endif
-+
-+#ifdef PFE_ETH_TX_STATS
-+	err = device_create_file(&ndev->dev, &dev_attr_tx_stats);
-+	if (err) {
-+		netdev_err(ndev, "failed to create tx stats sysfs files\n");
-+		goto err_tx;
-+	}
-+#endif
-+
-+	return 0;
-+
-+#ifdef PFE_ETH_TX_STATS
-+err_tx:
-+#endif
-+#ifdef PFE_ETH_NAPI_STATS
-+	device_remove_file(&ndev->dev, &dev_attr_napi_stats);
-+
-+err_napi:
-+#endif
-+	device_remove_file(&ndev->dev, &dev_attr_txavail);
-+
-+err_txavail:
-+	device_remove_file(&ndev->dev, &dev_attr_default_priority);
-+
-+err_priority:
-+	return -1;
-+}
-+
-+/* pfe_eth_sysfs_exit
-+ *
-+ */
-+void pfe_eth_sysfs_exit(struct net_device *ndev)
-+{
-+#ifdef PFE_ETH_TX_STATS
-+	device_remove_file(&ndev->dev, &dev_attr_tx_stats);
-+#endif
-+
-+#ifdef PFE_ETH_NAPI_STATS
-+	device_remove_file(&ndev->dev, &dev_attr_napi_stats);
-+#endif
-+	device_remove_file(&ndev->dev, &dev_attr_txavail);
-+	device_remove_file(&ndev->dev, &dev_attr_default_priority);
-+}
-+
-+/*************************************************************************/
-+/*		ETHTOOL INTERCAE					 */
-+/*************************************************************************/
-+
-+/*MTIP GEMAC */
-+static const struct fec_stat {
-+	char name[ETH_GSTRING_LEN];
-+	u16 offset;
-+} fec_stats[] = {
-+	/* RMON TX */
-+	{ "tx_dropped", RMON_T_DROP },
-+	{ "tx_packets", RMON_T_PACKETS },
-+	{ "tx_broadcast", RMON_T_BC_PKT },
-+	{ "tx_multicast", RMON_T_MC_PKT },
-+	{ "tx_crc_errors", RMON_T_CRC_ALIGN },
-+	{ "tx_undersize", RMON_T_UNDERSIZE },
-+	{ "tx_oversize", RMON_T_OVERSIZE },
-+	{ "tx_fragment", RMON_T_FRAG },
-+	{ "tx_jabber", RMON_T_JAB },
-+	{ "tx_collision", RMON_T_COL },
-+	{ "tx_64byte", RMON_T_P64 },
-+	{ "tx_65to127byte", RMON_T_P65TO127 },
-+	{ "tx_128to255byte", RMON_T_P128TO255 },
-+	{ "tx_256to511byte", RMON_T_P256TO511 },
-+	{ "tx_512to1023byte", RMON_T_P512TO1023 },
-+	{ "tx_1024to2047byte", RMON_T_P1024TO2047 },
-+	{ "tx_GTE2048byte", RMON_T_P_GTE2048 },
-+	{ "tx_octets", RMON_T_OCTETS },
-+
-+	/* IEEE TX */
-+	{ "IEEE_tx_drop", IEEE_T_DROP },
-+	{ "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
-+	{ "IEEE_tx_1col", IEEE_T_1COL },
-+	{ "IEEE_tx_mcol", IEEE_T_MCOL },
-+	{ "IEEE_tx_def", IEEE_T_DEF },
-+	{ "IEEE_tx_lcol", IEEE_T_LCOL },
-+	{ "IEEE_tx_excol", IEEE_T_EXCOL },
-+	{ "IEEE_tx_macerr", IEEE_T_MACERR },
-+	{ "IEEE_tx_cserr", IEEE_T_CSERR },
-+	{ "IEEE_tx_sqe", IEEE_T_SQE },
-+	{ "IEEE_tx_fdxfc", IEEE_T_FDXFC },
-+	{ "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
-+
-+	/* RMON RX */
-+	{ "rx_packets", RMON_R_PACKETS },
-+	{ "rx_broadcast", RMON_R_BC_PKT },
-+	{ "rx_multicast", RMON_R_MC_PKT },
-+	{ "rx_crc_errors", RMON_R_CRC_ALIGN },
-+	{ "rx_undersize", RMON_R_UNDERSIZE },
-+	{ "rx_oversize", RMON_R_OVERSIZE },
-+	{ "rx_fragment", RMON_R_FRAG },
-+	{ "rx_jabber", RMON_R_JAB },
-+	{ "rx_64byte", RMON_R_P64 },
-+	{ "rx_65to127byte", RMON_R_P65TO127 },
-+	{ "rx_128to255byte", RMON_R_P128TO255 },
-+	{ "rx_256to511byte", RMON_R_P256TO511 },
-+	{ "rx_512to1023byte", RMON_R_P512TO1023 },
-+	{ "rx_1024to2047byte", RMON_R_P1024TO2047 },
-+	{ "rx_GTE2048byte", RMON_R_P_GTE2048 },
-+	{ "rx_octets", RMON_R_OCTETS },
-+
-+	/* IEEE RX */
-+	{ "IEEE_rx_drop", IEEE_R_DROP },
-+	{ "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
-+	{ "IEEE_rx_crc", IEEE_R_CRC },
-+	{ "IEEE_rx_align", IEEE_R_ALIGN },
-+	{ "IEEE_rx_macerr", IEEE_R_MACERR },
-+	{ "IEEE_rx_fdxfc", IEEE_R_FDXFC },
-+	{ "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
-+};
-+
-+static void pfe_eth_fill_stats(struct net_device *ndev, struct ethtool_stats
-+				*stats, u64 *data)
-+{
-+	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
-+	int i;
-+	u64 pfe_crc_validated = 0;
-+	int id;
-+
-+	for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++) {
-+		pfe_crc_validated += be32_to_cpu(pe_dmem_read(id,
-+			CLASS_DM_CRC_VALIDATED + (priv->id * 4), 4));
-+	}
-+
-+	for (i = 0; i < ARRAY_SIZE(fec_stats); i++) {
-+		data[i] = readl(priv->EMAC_baseaddr + fec_stats[i].offset);
-+
-+		if (fec_stats[i].offset == IEEE_R_DROP)
-+			data[i] -= pfe_crc_validated;
-+	}
-+}
-+
-+static void pfe_eth_gstrings(struct net_device *netdev,
-+			     u32 stringset, u8 *data)
-+{
-+	int i;
-+
-+	switch (stringset) {
-+	case ETH_SS_STATS:
-+		for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
-+			memcpy(data + i * ETH_GSTRING_LEN,
-+			       fec_stats[i].name, ETH_GSTRING_LEN);
-+		break;
-+	}
-+}
-+
-+static int pfe_eth_stats_count(struct net_device *ndev, int sset)
-+{
-+	switch (sset) {
-+	case ETH_SS_STATS:
-+		return ARRAY_SIZE(fec_stats);
-+	default:
-+		return -EOPNOTSUPP;
-+	}
-+}
-+
-+/*
-+ * pfe_eth_gemac_reglen - Return the length of the register structure.
-+ *
-+ */
-+static int pfe_eth_gemac_reglen(struct net_device *ndev)
-+{
-+	pr_info("%s()\n", __func__);
-+	return (sizeof(gemac_regs) / sizeof(u32));
-+}
-+
-+/*
-+ * pfe_eth_gemac_get_regs - Return the gemac register structure.
-+ *
-+ */
-+static void  pfe_eth_gemac_get_regs(struct net_device *ndev, struct ethtool_regs
-+					*regs, void *regbuf)
-+{
-+	int i;
-+
-+	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
-+	u32 *buf = (u32 *)regbuf;
-+
-+	pr_info("%s()\n", __func__);
-+	for (i = 0; i < sizeof(gemac_regs) / sizeof(u32); i++)
-+		buf[i] = readl(priv->EMAC_baseaddr + gemac_regs[i]);
-+}
-+
-+/*
-+ * pfe_eth_set_wol - Set the magic packet option, in WoL register.
-+ *
-+ */
-+static int pfe_eth_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
-+{
-+	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
-+
-+	if (wol->wolopts & ~WAKE_MAGIC)
-+		return -EOPNOTSUPP;
-+
-+	/* for MTIP we store wol->wolopts */
-+	priv->wol = wol->wolopts;
-+
-+	device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC);
-+
-+	return 0;
-+}
-+
-+/*
-+ *
-+ * pfe_eth_get_wol - Get the WoL options.
-+ *
-+ */
-+static void pfe_eth_get_wol(struct net_device *ndev, struct ethtool_wolinfo
-+				*wol)
-+{
-+	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
-+
-+	wol->supported = WAKE_MAGIC;
-+	wol->wolopts = 0;
-+
-+	if (priv->wol & WAKE_MAGIC)
-+		wol->wolopts = WAKE_MAGIC;
-+
-+	memset(&wol->sopass, 0, sizeof(wol->sopass));
-+}
-+
-+/*
-+ * pfe_eth_get_drvinfo -  Fills in the drvinfo structure with some basic info
-+ *
-+ */
-+static void pfe_eth_get_drvinfo(struct net_device *ndev, struct ethtool_drvinfo
-+				*drvinfo)
-+{
-+	strlcpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver));
-+	strlcpy(drvinfo->version, DRV_VERSION, sizeof(drvinfo->version));
-+	strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
-+	strlcpy(drvinfo->bus_info, "N/A", sizeof(drvinfo->bus_info));
-+}
-+
-+/*
-+ * pfe_eth_set_settings - Used to send commands to PHY.
-+ *
-+ */
-+static int pfe_eth_set_settings(struct net_device *ndev,
-+				const struct ethtool_link_ksettings *cmd)
-+{
-+	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
-+	struct phy_device *phydev = priv->phydev;
-+
-+	if (!phydev)
-+		return -ENODEV;
-+
-+	return phy_ethtool_ksettings_set(phydev, cmd);
-+}
-+
-+/*
-+ * pfe_eth_getsettings - Return the current settings in the ethtool_cmd
-+ * structure.
-+ *
-+ */
-+static int pfe_eth_get_settings(struct net_device *ndev,
-+				struct ethtool_link_ksettings *cmd)
-+{
-+	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
-+	struct phy_device *phydev = priv->phydev;
-+
-+	if (!phydev)
-+		return -ENODEV;
-+
-+	phy_ethtool_ksettings_get(phydev, cmd);
-+
-+	return 0;
-+}
-+
-+/*
-+ * pfe_eth_get_msglevel - Gets the debug message mask.
-+ *
-+ */
-+static uint32_t pfe_eth_get_msglevel(struct net_device *ndev)
-+{
-+	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
-+
-+	return priv->msg_enable;
-+}
-+
-+/*
-+ * pfe_eth_set_msglevel - Sets the debug message mask.
-+ *
-+ */
-+static void pfe_eth_set_msglevel(struct net_device *ndev, uint32_t data)
-+{
-+	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
-+
-+	priv->msg_enable = data;
-+}
-+
-+#define HIF_RX_COAL_MAX_CLKS		(~(1 << 31))
-+#define HIF_RX_COAL_CLKS_PER_USEC	(pfe->ctrl.sys_clk / 1000)
-+#define HIF_RX_COAL_MAX_USECS		(HIF_RX_COAL_MAX_CLKS	/ \
-+						HIF_RX_COAL_CLKS_PER_USEC)
-+
-+/*
-+ * pfe_eth_set_coalesce - Sets rx interrupt coalescing timer.
-+ *
-+ */
-+static int pfe_eth_set_coalesce(struct net_device *ndev,
-+				struct ethtool_coalesce *ec,
-+				struct kernel_ethtool_coalesce *kernel_coal,
-+				struct netlink_ext_ack *extack)
-+{
-+	if (ec->rx_coalesce_usecs > HIF_RX_COAL_MAX_USECS)
-+		return -EINVAL;
-+
-+	if (!ec->rx_coalesce_usecs) {
-+		writel(0, HIF_INT_COAL);
-+		return 0;
-+	}
-+
-+	writel((ec->rx_coalesce_usecs * HIF_RX_COAL_CLKS_PER_USEC) |
-+			HIF_INT_COAL_ENABLE, HIF_INT_COAL);
-+
-+	return 0;
-+}
-+
-+/*
-+ * pfe_eth_get_coalesce - Gets rx interrupt coalescing timer value.
-+ *
-+ */
-+static int pfe_eth_get_coalesce(struct net_device *ndev,
-+				struct ethtool_coalesce *ec,
-+				struct kernel_ethtool_coalesce *kernel_coal,
-+				struct netlink_ext_ack *extack)
-+{
-+	int reg_val = readl(HIF_INT_COAL);
-+
-+	if (reg_val & HIF_INT_COAL_ENABLE)
-+		ec->rx_coalesce_usecs = (reg_val & HIF_RX_COAL_MAX_CLKS) /
-+						HIF_RX_COAL_CLKS_PER_USEC;
-+	else
-+		ec->rx_coalesce_usecs = 0;
-+
-+	return 0;
-+}
-+
-+/*
-+ * pfe_eth_set_pauseparam - Sets pause parameters
-+ *
-+ */
-+static int pfe_eth_set_pauseparam(struct net_device *ndev,
-+				  struct ethtool_pauseparam *epause)
-+{
-+	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
-+
-+	if (epause->tx_pause != epause->rx_pause) {
-+		netdev_info(ndev,
-+			    "hardware only support enable/disable both tx and rx\n");
-+		return -EINVAL;
-+	}
-+
-+	priv->pause_flag = 0;
-+	priv->pause_flag |= epause->rx_pause ? PFE_PAUSE_FLAG_ENABLE : 0;
-+	priv->pause_flag |= epause->autoneg ? PFE_PAUSE_FLAG_AUTONEG : 0;
-+
-+	if (epause->rx_pause || epause->autoneg) {
-+		gemac_enable_pause_rx(priv->EMAC_baseaddr);
-+		writel((readl(priv->GPI_baseaddr + GPI_TX_PAUSE_TIME) |
-+					EGPI_PAUSE_ENABLE),
-+				priv->GPI_baseaddr + GPI_TX_PAUSE_TIME);
-+		if (priv->phydev) {
-+			linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT,
-+					 priv->phydev->supported);
-+			linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
-+					 priv->phydev->supported);
-+			linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT,
-+					 priv->phydev->advertising);
-+			linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
-+					 priv->phydev->advertising);
-+		}
-+	} else {
-+		gemac_disable_pause_rx(priv->EMAC_baseaddr);
-+		writel((readl(priv->GPI_baseaddr + GPI_TX_PAUSE_TIME) &
-+					~EGPI_PAUSE_ENABLE),
-+				priv->GPI_baseaddr + GPI_TX_PAUSE_TIME);
-+		if (priv->phydev) {
-+			linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT,
-+					   priv->phydev->supported);
-+			linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
-+					   priv->phydev->supported);
-+			linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT,
-+					   priv->phydev->advertising);
-+			linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
-+					   priv->phydev->advertising);
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+/*
-+ * pfe_eth_get_pauseparam - Gets pause parameters
-+ *
-+ */
-+static void pfe_eth_get_pauseparam(struct net_device *ndev,
-+				   struct ethtool_pauseparam *epause)
-+{
-+	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
-+
-+	epause->autoneg = (priv->pause_flag & PFE_PAUSE_FLAG_AUTONEG) != 0;
-+	epause->tx_pause = (priv->pause_flag & PFE_PAUSE_FLAG_ENABLE) != 0;
-+	epause->rx_pause = epause->tx_pause;
-+}
-+
-+/*
-+ * pfe_eth_get_hash
-+ */
-+#define PFE_HASH_BITS	6		/* #bits in hash */
-+#define CRC32_POLY	0xEDB88320
-+
-+static int pfe_eth_get_hash(u8 *addr)
-+{
-+	unsigned int i, bit, data, crc, hash;
-+
-+	/* calculate crc32 value of mac address */
-+	crc = 0xffffffff;
-+
-+	for (i = 0; i < 6; i++) {
-+		data = addr[i];
-+		for (bit = 0; bit < 8; bit++, data >>= 1) {
-+			crc = (crc >> 1) ^
-+				(((crc ^ data) & 1) ? CRC32_POLY : 0);
-+		}
-+	}
-+
-+	/*
-+	 * only upper 6 bits (PFE_HASH_BITS) are used
-+	 * which point to specific bit in the hash registers
-+	 */
-+	hash = (crc >> (32 - PFE_HASH_BITS)) & 0x3f;
-+
-+	return hash;
-+}
-+
-+const struct ethtool_ops pfe_ethtool_ops = {
-+	.supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS,
-+	.get_drvinfo = pfe_eth_get_drvinfo,
-+	.get_regs_len = pfe_eth_gemac_reglen,
-+	.get_regs = pfe_eth_gemac_get_regs,
-+	.get_link = ethtool_op_get_link,
-+	.get_wol  = pfe_eth_get_wol,
-+	.set_wol  = pfe_eth_set_wol,
-+	.set_pauseparam = pfe_eth_set_pauseparam,
-+	.get_pauseparam = pfe_eth_get_pauseparam,
-+	.get_strings = pfe_eth_gstrings,
-+	.get_sset_count = pfe_eth_stats_count,
-+	.get_ethtool_stats = pfe_eth_fill_stats,
-+	.get_msglevel = pfe_eth_get_msglevel,
-+	.set_msglevel = pfe_eth_set_msglevel,
-+	.set_coalesce = pfe_eth_set_coalesce,
-+	.get_coalesce = pfe_eth_get_coalesce,
-+	.get_link_ksettings = pfe_eth_get_settings,
-+	.set_link_ksettings = pfe_eth_set_settings,
-+};
-+
-+/* pfe_eth_mdio_reset
-+ */
-+int pfe_eth_mdio_reset(struct mii_bus *bus)
-+{
-+	struct pfe_mdio_priv_s *priv = (struct pfe_mdio_priv_s *)bus->priv;
-+	u32 phy_speed;
-+
-+
-+	mutex_lock(&bus->mdio_lock);
-+
-+	/*
-+	 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
-+	 *
-+	 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
-+	 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'.
-+	 */
-+	phy_speed = (DIV_ROUND_UP((pfe->ctrl.sys_clk * 1000), 4000000)
-+		     << EMAC_MII_SPEED_SHIFT);
-+	phy_speed |= EMAC_HOLDTIME(0x5);
-+	__raw_writel(phy_speed, priv->mdio_base + EMAC_MII_CTRL_REG);
-+
-+	mutex_unlock(&bus->mdio_lock);
-+
-+	return 0;
-+}
-+
-+/* pfe_eth_mdio_timeout
-+ *
-+ */
-+static int pfe_eth_mdio_timeout(struct pfe_mdio_priv_s *priv, int timeout)
-+{
-+	while (!(__raw_readl(priv->mdio_base + EMAC_IEVENT_REG) &
-+			EMAC_IEVENT_MII)) {
-+		if (timeout-- <= 0)
-+			return -1;
-+		usleep_range(10, 20);
-+	}
-+	__raw_writel(EMAC_IEVENT_MII, priv->mdio_base + EMAC_IEVENT_REG);
-+	return 0;
-+}
-+
-+static int pfe_eth_mdio_mux(u8 muxval)
-+{
-+	struct i2c_adapter *a;
-+	struct i2c_msg msg;
-+	unsigned char buf[2];
-+	int ret;
-+
-+	a = i2c_get_adapter(0);
-+	if (!a)
-+		return -ENODEV;
-+
-+	/* set bit 1 (the second bit) of chip at 0x09, register 0x13 */
-+	buf[0] = 0x54; /* reg number */
-+	buf[1] = (muxval << 6) | 0x3; /* data */
-+	msg.addr = 0x66;
-+	msg.buf = buf;
-+	msg.len = 2;
-+	msg.flags = 0;
-+	ret = i2c_transfer(a, &msg, 1);
-+	i2c_put_adapter(a);
-+	if (ret != 1)
-+		return -ENODEV;
-+	return 0;
-+}
-+
-+static int pfe_eth_mdio_write_addr(struct mii_bus *bus, int mii_id,
-+				   int dev_addr, int regnum)
-+{
-+	struct pfe_mdio_priv_s *priv = (struct pfe_mdio_priv_s *)bus->priv;
-+
-+	__raw_writel(EMAC_MII_DATA_PA(mii_id) |
-+		     EMAC_MII_DATA_RA(dev_addr) |
-+		     EMAC_MII_DATA_TA | EMAC_MII_DATA(regnum),
-+		     priv->mdio_base + EMAC_MII_DATA_REG);
-+
-+	if (pfe_eth_mdio_timeout(priv, EMAC_MDIO_TIMEOUT)) {
-+		dev_err(&bus->dev, "phy MDIO address write timeout\n");
-+		return -1;
-+	}
-+
-+	return 0;
-+}
-+
-+static int pfe_eth_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
-+			      u16 value)
-+{
-+	struct pfe_mdio_priv_s *priv = (struct pfe_mdio_priv_s *)bus->priv;
-+
-+	/*To access external PHYs on QDS board mux needs to be configured*/
-+	if ((mii_id) && (pfe->mdio_muxval[mii_id]))
-+		pfe_eth_mdio_mux(pfe->mdio_muxval[mii_id]);
-+
-+	if (regnum & MII_ADDR_C45) {
-+		pfe_eth_mdio_write_addr(bus, mii_id, (regnum >> 16) & 0x1f,
-+					regnum & 0xffff);
-+		__raw_writel(EMAC_MII_DATA_OP_CL45_WR |
-+			     EMAC_MII_DATA_PA(mii_id) |
-+			     EMAC_MII_DATA_RA((regnum >> 16) & 0x1f) |
-+			     EMAC_MII_DATA_TA | EMAC_MII_DATA(value),
-+			     priv->mdio_base + EMAC_MII_DATA_REG);
-+	} else {
-+		/* start a write op */
-+		__raw_writel(EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_WR |
-+			     EMAC_MII_DATA_PA(mii_id) |
-+			     EMAC_MII_DATA_RA(regnum) |
-+			     EMAC_MII_DATA_TA | EMAC_MII_DATA(value),
-+			     priv->mdio_base + EMAC_MII_DATA_REG);
-+	}
-+
-+	if (pfe_eth_mdio_timeout(priv, EMAC_MDIO_TIMEOUT)) {
-+		dev_err(&bus->dev, "%s: phy MDIO write timeout\n", __func__);
-+		return -1;
-+	}
-+	return 0;
-+}
-+
-+static int pfe_eth_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
-+{
-+	struct pfe_mdio_priv_s *priv = (struct pfe_mdio_priv_s *)bus->priv;
-+	u16 value = 0;
-+
-+	/*To access external PHYs on QDS board mux needs to be configured*/
-+	if ((mii_id) && (pfe->mdio_muxval[mii_id]))
-+		pfe_eth_mdio_mux(pfe->mdio_muxval[mii_id]);
-+
-+	if (regnum & MII_ADDR_C45) {
-+		pfe_eth_mdio_write_addr(bus, mii_id, (regnum >> 16) & 0x1f,
-+					regnum & 0xffff);
-+		__raw_writel(EMAC_MII_DATA_OP_CL45_RD |
-+			     EMAC_MII_DATA_PA(mii_id) |
-+			     EMAC_MII_DATA_RA((regnum >> 16) & 0x1f) |
-+			     EMAC_MII_DATA_TA,
-+			     priv->mdio_base + EMAC_MII_DATA_REG);
-+	} else {
-+		/* start a read op */
-+		__raw_writel(EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_RD |
-+			     EMAC_MII_DATA_PA(mii_id) |
-+			     EMAC_MII_DATA_RA(regnum) |
-+			     EMAC_MII_DATA_TA, priv->mdio_base +
-+			     EMAC_MII_DATA_REG);
-+	}
-+
-+	if (pfe_eth_mdio_timeout(priv, EMAC_MDIO_TIMEOUT)) {
-+		dev_err(&bus->dev, "%s: phy MDIO read timeout\n", __func__);
-+		return -1;
-+	}
-+
-+	value = EMAC_MII_DATA(__raw_readl(priv->mdio_base +
-+						EMAC_MII_DATA_REG));
-+	return value;
-+}
-+
-+static int pfe_eth_mdio_init(struct pfe *pfe,
-+			     struct ls1012a_pfe_platform_data *pfe_info,
-+			     int ii)
-+{
-+	struct pfe_mdio_priv_s *priv = NULL;
-+	struct ls1012a_mdio_platform_data *mdio_info;
-+	struct mii_bus *bus;
-+	struct device_node *mdio_node;
-+	int rc = 0;
-+
-+	mdio_info = (struct ls1012a_mdio_platform_data *)
-+					pfe_info->ls1012a_mdio_pdata;
-+	mdio_info->id = ii;
-+
-+	bus = mdiobus_alloc_size(sizeof(struct pfe_mdio_priv_s));
-+	if (!bus) {
-+		pr_err("mdiobus_alloc() failed\n");
-+		rc = -ENOMEM;
-+		goto err_mdioalloc;
-+	}
-+
-+	bus->name = "ls1012a MDIO Bus";
-+	snprintf(bus->id, MII_BUS_ID_SIZE, "ls1012a-%x", mdio_info->id);
-+
-+	bus->read = &pfe_eth_mdio_read;
-+	bus->write = &pfe_eth_mdio_write;
-+	bus->reset = &pfe_eth_mdio_reset;
-+	bus->parent = pfe->dev;
-+	bus->phy_mask = mdio_info->phy_mask;
-+	bus->irq[0] = mdio_info->irq[0];
-+	priv = bus->priv;
-+	priv->mdio_base = cbus_emac_base[ii];
-+
-+	priv->mdc_div = mdio_info->mdc_div;
-+	if (!priv->mdc_div)
-+		priv->mdc_div = 64;
-+
-+	dev_info(bus->parent, "%s: mdc_div: %d, phy_mask: %x\n",
-+		 __func__, priv->mdc_div, bus->phy_mask);
-+	mdio_node = of_get_child_by_name(pfe->dev->of_node, "mdio");
-+	if ((mdio_info->id == 0) && mdio_node) {
-+		rc = of_mdiobus_register(bus, mdio_node);
-+		of_node_put(mdio_node);
-+	} else {
-+		rc = mdiobus_register(bus);
-+	}
-+
-+	if (rc) {
-+		dev_err(bus->parent, "mdiobus_register(%s) failed\n",
-+			bus->name);
-+		goto err_mdioregister;
-+	}
-+
-+	priv->mii_bus = bus;
-+	pfe->mdio.mdio_priv[ii] = priv;
-+
-+	pfe_eth_mdio_reset(bus);
-+
-+	return 0;
-+
-+err_mdioregister:
-+	mdiobus_free(bus);
-+err_mdioalloc:
-+	return rc;
-+}
-+
-+/* pfe_eth_mdio_exit
-+ */
-+static void pfe_eth_mdio_exit(struct pfe *pfe,
-+			      int ii)
-+{
-+	struct pfe_mdio_priv_s *mdio_priv = pfe->mdio.mdio_priv[ii];
-+	struct mii_bus *bus = mdio_priv->mii_bus;
-+
-+	if (!bus)
-+		return;
-+	mdiobus_unregister(bus);
-+	mdiobus_free(bus);
-+}
-+
-+/* pfe_get_phydev_speed
-+ */
-+static int pfe_get_phydev_speed(struct phy_device *phydev)
-+{
-+	switch (phydev->speed) {
-+	case 10:
-+			return SPEED_10M;
-+	case 100:
-+			return SPEED_100M;
-+	case 1000:
-+	default:
-+			return SPEED_1000M;
-+	}
-+}
-+
-+/* pfe_set_rgmii_speed
-+ */
-+#define RGMIIPCR	0x434
-+/* RGMIIPCR bit definitions*/
-+#define SCFG_RGMIIPCR_EN_AUTO           (0x00000008)
-+#define SCFG_RGMIIPCR_SETSP_1000M       (0x00000004)
-+#define SCFG_RGMIIPCR_SETSP_100M        (0x00000000)
-+#define SCFG_RGMIIPCR_SETSP_10M         (0x00000002)
-+#define SCFG_RGMIIPCR_SETFD             (0x00000001)
-+
-+#define MDIOSELCR	0x484
-+#define MDIOSEL_SERDES	0x0
-+#define MDIOSEL_EXTPHY  0x80000000
-+
-+static void pfe_set_rgmii_speed(struct phy_device *phydev)
-+{
-+	u32 rgmii_pcr;
-+
-+	regmap_read(pfe->scfg, RGMIIPCR, &rgmii_pcr);
-+	rgmii_pcr  &= ~(SCFG_RGMIIPCR_SETSP_1000M | SCFG_RGMIIPCR_SETSP_10M);
-+
-+	switch (phydev->speed) {
-+	case 10:
-+			rgmii_pcr |= SCFG_RGMIIPCR_SETSP_10M;
-+			break;
-+	case 1000:
-+			rgmii_pcr |= SCFG_RGMIIPCR_SETSP_1000M;
-+			break;
-+	case 100:
-+	default:
-+			/* Default is 100M */
-+			break;
-+	}
-+	regmap_write(pfe->scfg, RGMIIPCR, rgmii_pcr);
-+}
-+
-+/* pfe_get_phydev_duplex
-+ */
-+static int pfe_get_phydev_duplex(struct phy_device *phydev)
-+{
-+	/*return (phydev->duplex == DUPLEX_HALF) ? DUP_HALF:DUP_FULL ; */
-+	return DUPLEX_FULL;
-+}
-+
-+/* pfe_eth_adjust_link
-+ */
-+static void pfe_eth_adjust_link(struct net_device *ndev)
-+{
-+	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
-+	unsigned long flags;
-+	struct phy_device *phydev = priv->phydev;
-+	int new_state = 0;
-+
-+	netif_info(priv, drv, ndev, "%s\n", __func__);
-+
-+	spin_lock_irqsave(&priv->lock, flags);
-+
-+	if (phydev->link) {
-+		/*
-+		 * Now we make sure that we can be in full duplex mode.
-+		 * If not, we operate in half-duplex mode.
-+		 */
-+		if (phydev->duplex != priv->oldduplex) {
-+			new_state = 1;
-+			gemac_set_duplex(priv->EMAC_baseaddr,
-+					 pfe_get_phydev_duplex(phydev));
-+			priv->oldduplex = phydev->duplex;
-+		}
-+
-+		if (phydev->speed != priv->oldspeed) {
-+			new_state = 1;
-+			gemac_set_speed(priv->EMAC_baseaddr,
-+					pfe_get_phydev_speed(phydev));
-+			if (priv->einfo->mii_config ==
-+					PHY_INTERFACE_MODE_RGMII_ID)
-+				pfe_set_rgmii_speed(phydev);
-+			priv->oldspeed = phydev->speed;
-+		}
-+
-+		if (!priv->oldlink) {
-+			new_state = 1;
-+			priv->oldlink = 1;
-+		}
-+
-+	} else if (priv->oldlink) {
-+		new_state = 1;
-+		priv->oldlink = 0;
-+		priv->oldspeed = 0;
-+		priv->oldduplex = -1;
-+	}
-+
-+	if (new_state && netif_msg_link(priv))
-+		phy_print_status(phydev);
-+
-+	spin_unlock_irqrestore(&priv->lock, flags);
-+
-+	/* Now, dump the details to the cdev.
-+	 * XXX: Locking would be required? (uniprocess arch)
-+	 *      Or, maybe move it in spinlock above
-+	 */
-+	if (us && priv->einfo->gem_id < PFE_CDEV_ETH_COUNT) {
-+		pr_debug("Changing link state from (%u) to (%u) for ID=(%u)\n",
-+			 link_states[priv->einfo->gem_id].state,
-+			 phydev->link,
-+			 priv->einfo->gem_id);
-+		link_states[priv->einfo->gem_id].phy_id = priv->einfo->gem_id;
-+		link_states[priv->einfo->gem_id].state = phydev->link;
-+	}
-+}
-+
-+/* pfe_phy_exit
-+ */
-+static void pfe_phy_exit(struct net_device *ndev)
-+{
-+	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
-+
-+	netif_info(priv, drv, ndev, "%s\n", __func__);
-+
-+	phy_disconnect(priv->phydev);
-+	priv->phydev = NULL;
-+}
-+
-+/* pfe_eth_stop
-+ */
-+static void pfe_eth_stop(struct net_device *ndev, int wake)
-+{
-+	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
-+
-+	netif_info(priv, drv, ndev, "%s\n", __func__);
-+
-+	if (wake) {
-+		gemac_tx_disable(priv->EMAC_baseaddr);
-+	} else {
-+		gemac_disable(priv->EMAC_baseaddr);
-+		gpi_disable(priv->GPI_baseaddr);
-+
-+		if (priv->phydev)
-+			phy_stop(priv->phydev);
-+	}
-+}
-+
-+/* pfe_eth_start
-+ */
-+static int pfe_eth_start(struct pfe_eth_priv_s *priv)
-+{
-+	netif_info(priv, drv, priv->ndev, "%s\n", __func__);
-+
-+	if (priv->phydev)
-+		phy_start(priv->phydev);
-+
-+	gpi_enable(priv->GPI_baseaddr);
-+	gemac_enable(priv->EMAC_baseaddr);
-+
-+	return 0;
-+}
-+
-+/*
-+ * Configure on chip serdes through mdio
-+ */
-+static void ls1012a_configure_serdes(struct net_device *ndev)
-+{
-+	struct pfe_eth_priv_s *eth_priv = netdev_priv(ndev);
-+	struct pfe_mdio_priv_s *mdio_priv = pfe->mdio.mdio_priv[eth_priv->id];
-+	int sgmii_2500 = 0;
-+	struct mii_bus *bus = mdio_priv->mii_bus;
-+	u16 value = 0;
-+
-+	if (eth_priv->einfo->mii_config == PHY_INTERFACE_MODE_2500SGMII)
-+		sgmii_2500 = 1;
-+
-+	netif_info(eth_priv, drv, ndev, "%s\n", __func__);
-+	/* PCS configuration done with corresponding GEMAC */
-+
-+	pfe_eth_mdio_read(bus, 0, MDIO_SGMII_CR);
-+	pfe_eth_mdio_read(bus, 0, MDIO_SGMII_SR);
-+
-+	pfe_eth_mdio_write(bus, 0, MDIO_SGMII_CR, SGMII_CR_RST);
-+
-+	if (sgmii_2500) {
-+		pfe_eth_mdio_write(bus, 0, MDIO_SGMII_IF_MODE, SGMII_SPEED_1GBPS
-+							       | SGMII_EN);
-+		pfe_eth_mdio_write(bus, 0, MDIO_SGMII_DEV_ABIL_SGMII,
-+				   SGMII_DEV_ABIL_ACK | SGMII_DEV_ABIL_SGMII);
-+		pfe_eth_mdio_write(bus, 0, MDIO_SGMII_LINK_TMR_L, 0xa120);
-+		pfe_eth_mdio_write(bus, 0, MDIO_SGMII_LINK_TMR_H, 0x7);
-+		/* Autonegotiation need to be disabled for 2.5G SGMII mode*/
-+		value = SGMII_CR_FD | SGMII_CR_SPEED_SEL1_1G;
-+		pfe_eth_mdio_write(bus, 0, MDIO_SGMII_CR, value);
-+	} else {
-+		pfe_eth_mdio_write(bus, 0, MDIO_SGMII_IF_MODE,
-+				   SGMII_SPEED_1GBPS
-+				   | SGMII_USE_SGMII_AN
-+				   | SGMII_EN);
-+		pfe_eth_mdio_write(bus, 0, MDIO_SGMII_DEV_ABIL_SGMII,
-+				   SGMII_DEV_ABIL_EEE_CLK_STP_EN
-+				   | 0xa0
-+				   | SGMII_DEV_ABIL_SGMII);
-+		pfe_eth_mdio_write(bus, 0, MDIO_SGMII_LINK_TMR_L, 0x400);
-+		pfe_eth_mdio_write(bus, 0, MDIO_SGMII_LINK_TMR_H, 0x0);
-+		value = SGMII_CR_AN_EN | SGMII_CR_FD | SGMII_CR_SPEED_SEL1_1G;
-+		pfe_eth_mdio_write(bus, 0, MDIO_SGMII_CR, value);
-+	}
-+}
-+
-+/*
-+ * pfe_phy_init
-+ *
-+ */
-+static int pfe_phy_init(struct net_device *ndev)
-+{
-+	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
-+	struct phy_device *phydev;
-+	char phy_id[MII_BUS_ID_SIZE + 3];
-+	char bus_id[MII_BUS_ID_SIZE];
-+	phy_interface_t interface;
-+
-+	priv->oldlink = 0;
-+	priv->oldspeed = 0;
-+	priv->oldduplex = -1;
-+
-+	snprintf(bus_id, MII_BUS_ID_SIZE, "ls1012a-%d", 0);
-+	snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
-+		 priv->einfo->phy_id);
-+	netif_info(priv, drv, ndev, "%s: %s\n", __func__, phy_id);
-+	interface = priv->einfo->mii_config;
-+	if ((interface == PHY_INTERFACE_MODE_SGMII) ||
-+	    (interface == PHY_INTERFACE_MODE_2500SGMII)) {
-+		/*Configure SGMII PCS */
-+		if (pfe->scfg) {
-+			/* Config MDIO from serdes */
-+			regmap_write(pfe->scfg, MDIOSELCR, MDIOSEL_SERDES);
-+		}
-+		ls1012a_configure_serdes(ndev);
-+	}
-+
-+	if (pfe->scfg) {
-+		/*Config MDIO from PAD */
-+		regmap_write(pfe->scfg, MDIOSELCR, MDIOSEL_EXTPHY);
-+	}
-+
-+	priv->oldlink = 0;
-+	priv->oldspeed = 0;
-+	priv->oldduplex = -1;
-+	pr_info("%s interface %x\n", __func__, interface);
-+
-+	if (priv->phy_node) {
-+		phydev = of_phy_connect(ndev, priv->phy_node,
-+					pfe_eth_adjust_link, 0,
-+					priv->einfo->mii_config);
-+		if (!(phydev)) {
-+			netdev_err(ndev, "Unable to connect to phy\n");
-+			return -ENODEV;
-+		}
-+
-+	} else {
-+		phydev = phy_connect(ndev, phy_id,
-+				     &pfe_eth_adjust_link, interface);
-+		if (IS_ERR(phydev)) {
-+			netdev_err(ndev, "Unable to connect to phy\n");
-+			return PTR_ERR(phydev);
-+		}
-+	}
-+
-+	priv->phydev = phydev;
-+	phydev->irq = PHY_POLL;
-+
-+	return 0;
-+}
-+
-+/* pfe_gemac_init
-+ */
-+static int pfe_gemac_init(struct pfe_eth_priv_s *priv)
-+{
-+	struct gemac_cfg cfg;
-+
-+	netif_info(priv, ifup, priv->ndev, "%s\n", __func__);
-+
-+	cfg.mode = 0;
-+	cfg.speed = SPEED_1000M;
-+	cfg.duplex = DUPLEX_FULL;
-+
-+	gemac_set_config(priv->EMAC_baseaddr, &cfg);
-+	gemac_allow_broadcast(priv->EMAC_baseaddr);
-+	gemac_enable_1536_rx(priv->EMAC_baseaddr);
-+	gemac_enable_stacked_vlan(priv->EMAC_baseaddr);
-+	gemac_enable_pause_rx(priv->EMAC_baseaddr);
-+	gemac_set_bus_width(priv->EMAC_baseaddr, 64);
-+
-+	/*GEM will perform checksum verifications*/
-+	if (priv->ndev->features & NETIF_F_RXCSUM)
-+		gemac_enable_rx_checksum_offload(priv->EMAC_baseaddr);
-+	else
-+		gemac_disable_rx_checksum_offload(priv->EMAC_baseaddr);
-+
-+	return 0;
-+}
-+
-+/* pfe_eth_event_handler
-+ */
-+static int pfe_eth_event_handler(void *data, int event, int qno)
-+{
-+	struct pfe_eth_priv_s *priv = data;
-+
-+	switch (event) {
-+	case EVENT_RX_PKT_IND:
-+
-+		if (qno == 0) {
-+			if (napi_schedule_prep(&priv->high_napi)) {
-+				netif_info(priv, intr, priv->ndev,
-+					   "%s: schedule high prio poll\n"
-+					   , __func__);
-+
-+#ifdef PFE_ETH_NAPI_STATS
-+				priv->napi_counters[NAPI_SCHED_COUNT]++;
-+#endif
-+
-+				__napi_schedule(&priv->high_napi);
-+			}
-+		} else if (qno == 1) {
-+			if (napi_schedule_prep(&priv->low_napi)) {
-+				netif_info(priv, intr, priv->ndev,
-+					   "%s: schedule low prio poll\n"
-+					   , __func__);
-+
-+#ifdef PFE_ETH_NAPI_STATS
-+				priv->napi_counters[NAPI_SCHED_COUNT]++;
-+#endif
-+				__napi_schedule(&priv->low_napi);
-+			}
-+		} else if (qno == 2) {
-+			if (napi_schedule_prep(&priv->lro_napi)) {
-+				netif_info(priv, intr, priv->ndev,
-+					   "%s: schedule lro prio poll\n"
-+					   , __func__);
-+
-+#ifdef PFE_ETH_NAPI_STATS
-+				priv->napi_counters[NAPI_SCHED_COUNT]++;
-+#endif
-+				__napi_schedule(&priv->lro_napi);
-+			}
-+		}
-+
-+		break;
-+
-+	case EVENT_TXDONE_IND:
-+		pfe_eth_flush_tx(priv);
-+		hif_lib_event_handler_start(&priv->client, EVENT_TXDONE_IND, 0);
-+		break;
-+	case EVENT_HIGH_RX_WM:
-+	default:
-+		break;
-+	}
-+
-+	return 0;
-+}
-+
-+static int pfe_eth_change_mtu(struct net_device *ndev, int new_mtu)
-+{
-+	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
-+
-+	ndev->mtu = new_mtu;
-+	new_mtu += ETH_HLEN + ETH_FCS_LEN;
-+	gemac_set_rx_max_fl(priv->EMAC_baseaddr, new_mtu);
-+
-+	return 0;
-+}
-+
-+/* pfe_eth_open
-+ */
-+static int pfe_eth_open(struct net_device *ndev)
-+{
-+	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
-+	struct hif_client_s *client;
-+	int rc;
-+
-+	netif_info(priv, ifup, ndev, "%s\n", __func__);
-+
-+	/* Register client driver with HIF */
-+	client = &priv->client;
-+	memset(client, 0, sizeof(*client));
-+	client->id = PFE_CL_GEM0 + priv->id;
-+	client->tx_qn = emac_txq_cnt;
-+	client->rx_qn = EMAC_RXQ_CNT;
-+	client->priv = priv;
-+	client->pfe = priv->pfe;
-+	client->event_handler = pfe_eth_event_handler;
-+
-+	client->tx_qsize = EMAC_TXQ_DEPTH;
-+	client->rx_qsize = EMAC_RXQ_DEPTH;
-+
-+	rc = hif_lib_client_register(client);
-+	if (rc) {
-+		netdev_err(ndev, "%s: hif_lib_client_register(%d) failed\n",
-+			   __func__, client->id);
-+		goto err0;
-+	}
-+
-+	netif_info(priv, drv, ndev, "%s: registered client: %p\n", __func__,
-+		   client);
-+
-+	pfe_gemac_init(priv);
-+
-+	if (!is_valid_ether_addr(ndev->dev_addr)) {
-+		netdev_err(ndev, "%s: invalid MAC address\n", __func__);
-+		rc = -EADDRNOTAVAIL;
-+		goto err1;
-+	}
-+
-+	gemac_set_laddrN(priv->EMAC_baseaddr,
-+			 (struct pfe_mac_addr *)ndev->dev_addr, 1);
-+
-+	napi_enable(&priv->high_napi);
-+	napi_enable(&priv->low_napi);
-+	napi_enable(&priv->lro_napi);
-+
-+	rc = pfe_eth_start(priv);
-+
-+	netif_tx_wake_all_queues(ndev);
-+
-+	return rc;
-+
-+err1:
-+	hif_lib_client_unregister(&priv->client);
-+
-+err0:
-+	return rc;
-+}
-+
-+/*
-+ *  pfe_eth_shutdown
-+ */
-+int pfe_eth_shutdown(struct net_device *ndev, int wake)
-+{
-+	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
-+	int i, qstatus, id;
-+	unsigned long next_poll = jiffies + 1, end = jiffies +
-+				(TX_POLL_TIMEOUT_MS * HZ) / 1000;
-+	int tx_pkts, prv_tx_pkts;
-+
-+	netif_info(priv, ifdown, ndev, "%s\n", __func__);
-+
-+	for (i = 0; i < emac_txq_cnt; i++)
-+		hrtimer_cancel(&priv->fast_tx_timeout[i].timer);
-+
-+	netif_tx_stop_all_queues(ndev);
-+
-+	do {
-+		tx_pkts = 0;
-+		pfe_eth_flush_tx(priv);
-+
-+		for (i = 0; i < emac_txq_cnt; i++)
-+			tx_pkts += hif_lib_tx_pending(&priv->client, i);
-+
-+		if (tx_pkts) {
-+			/*Don't wait forever, break if we cross max timeout */
-+			if (time_after(jiffies, end)) {
-+				pr_err(
-+					"(%s)Tx is not complete after %dmsec\n",
-+					ndev->name, TX_POLL_TIMEOUT_MS);
-+				break;
-+			}
-+
-+			pr_info("%s : (%s) Waiting for tx packets to free. Pending tx pkts = %d.\n"
-+				, __func__, ndev->name, tx_pkts);
-+			if (need_resched())
-+				schedule();
-+		}
-+
-+	} while (tx_pkts);
-+
-+	end = jiffies + (TX_POLL_TIMEOUT_MS * HZ) / 1000;
-+
-+	prv_tx_pkts = tmu_pkts_processed(priv->id);
-+	/*
-+	 * Wait till TMU transmits all pending packets
-+	 * poll tmu_qstatus and pkts processed by TMU for every 10ms
-+	 * Consider TMU is busy, If we see TMU qeueu pending or any packets
-+	 * processed by TMU
-+	 */
-+	while (1) {
-+		if (time_after(jiffies, next_poll)) {
-+			tx_pkts = tmu_pkts_processed(priv->id);
-+			qstatus = tmu_qstatus(priv->id) & 0x7ffff;
-+
-+			if (!qstatus && (tx_pkts == prv_tx_pkts))
-+				break;
-+			/* Don't wait forever, break if we cross max
-+			 * timeout(TX_POLL_TIMEOUT_MS)
-+			 */
-+			if (time_after(jiffies, end)) {
-+				pr_err("TMU%d is busy after %dmsec\n",
-+				       priv->id, TX_POLL_TIMEOUT_MS);
-+				break;
-+			}
-+			prv_tx_pkts = tx_pkts;
-+			next_poll++;
-+		}
-+		if (need_resched())
-+			schedule();
-+	}
-+	/* Wait for some more time to complete transmitting packet if any */
-+	next_poll = jiffies + 1;
-+	while (1) {
-+		if (time_after(jiffies, next_poll))
-+			break;
-+		if (need_resched())
-+			schedule();
-+	}
-+
-+	pfe_eth_stop(ndev, wake);
-+
-+	napi_disable(&priv->lro_napi);
-+	napi_disable(&priv->low_napi);
-+	napi_disable(&priv->high_napi);
-+
-+	for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++) {
-+		pe_dmem_write(id, 0, CLASS_DM_CRC_VALIDATED
-+			      + (priv->id * 4), 4);
-+	}
-+
-+	hif_lib_client_unregister(&priv->client);
-+
-+	return 0;
-+}
-+
-+/* pfe_eth_close
-+ *
-+ */
-+static int pfe_eth_close(struct net_device *ndev)
-+{
-+	pfe_eth_shutdown(ndev, 0);
-+
-+	return 0;
-+}
-+
-+/* pfe_eth_suspend
-+ *
-+ * return value : 1 if netdevice is configured to wakeup system
-+ *                0 otherwise
-+ */
-+int pfe_eth_suspend(struct net_device *ndev)
-+{
-+	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
-+	int retval = 0;
-+
-+	if (priv->wol) {
-+		gemac_set_wol(priv->EMAC_baseaddr, priv->wol);
-+		retval = 1;
-+	}
-+	pfe_eth_shutdown(ndev, priv->wol);
-+
-+	return retval;
-+}
-+
-+/* pfe_eth_resume
-+ *
-+ */
-+int pfe_eth_resume(struct net_device *ndev)
-+{
-+	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
-+
-+	if (priv->wol)
-+		gemac_set_wol(priv->EMAC_baseaddr, 0);
-+	gemac_tx_enable(priv->EMAC_baseaddr);
-+
-+	return pfe_eth_open(ndev);
-+}
-+
-+/* pfe_eth_get_queuenum
-+ */
-+static int pfe_eth_get_queuenum(struct pfe_eth_priv_s *priv, struct sk_buff
-+					*skb)
-+{
-+	int queuenum = 0;
-+	unsigned long flags;
-+
-+	/* Get the Fast Path queue number */
-+	/*
-+	 * Use conntrack mark (if conntrack exists), then packet mark (if any),
-+	 * then fallback to default
-+	 */
-+#if defined(CONFIG_IP_NF_CONNTRACK_MARK) || defined(CONFIG_NF_CONNTRACK_MARK)
-+	if (skb->_nfct) {
-+		enum ip_conntrack_info cinfo;
-+		struct nf_conn *ct;
-+
-+		ct = nf_ct_get(skb, &cinfo);
-+
-+		if (ct) {
-+			u32 connmark;
-+
-+			connmark = ct->mark;
-+
-+			if ((connmark & 0x80000000) && priv->id != 0)
-+				connmark >>= 16;
-+
-+			queuenum = connmark & EMAC_QUEUENUM_MASK;
-+		}
-+	} else  {/* continued after #endif ... */
-+#endif
-+		if (skb->mark) {
-+			queuenum = skb->mark & EMAC_QUEUENUM_MASK;
-+		} else {
-+			spin_lock_irqsave(&priv->lock, flags);
-+			queuenum = priv->default_priority & EMAC_QUEUENUM_MASK;
-+			spin_unlock_irqrestore(&priv->lock, flags);
-+		}
-+#if defined(CONFIG_IP_NF_CONNTRACK_MARK) || defined(CONFIG_NF_CONNTRACK_MARK)
-+	}
-+#endif
-+	return queuenum;
-+}
-+
-+/* pfe_eth_might_stop_tx
-+ *
-+ */
-+static int pfe_eth_might_stop_tx(struct pfe_eth_priv_s *priv, int queuenum,
-+				 struct netdev_queue *tx_queue,
-+				 unsigned int n_desc,
-+				 unsigned int n_segs)
-+{
-+	ktime_t kt;
-+	int tried = 0;
-+
-+try_again:
-+	if (unlikely((__hif_tx_avail(&pfe->hif) < n_desc) ||
-+	(hif_lib_tx_avail(&priv->client, queuenum) < n_desc) ||
-+	(hif_lib_tx_credit_avail(pfe, priv->id, queuenum) < n_segs))) {
-+		if (!tried) {
-+			__hif_lib_update_credit(&priv->client, queuenum);
-+			tried = 1;
-+			goto try_again;
-+		}
-+#ifdef PFE_ETH_TX_STATS
-+		if (__hif_tx_avail(&pfe->hif) < n_desc) {
-+			priv->stop_queue_hif[queuenum]++;
-+		} else if (hif_lib_tx_avail(&priv->client, queuenum) < n_desc) {
-+			priv->stop_queue_hif_client[queuenum]++;
-+		} else if (hif_lib_tx_credit_avail(pfe, priv->id, queuenum) <
-+			n_segs) {
-+			priv->stop_queue_credit[queuenum]++;
-+		}
-+		priv->stop_queue_total[queuenum]++;
-+#endif
-+		netif_tx_stop_queue(tx_queue);
-+
-+		kt = ktime_set(0, LS1012A_TX_FAST_RECOVERY_TIMEOUT_MS *
-+				NSEC_PER_MSEC);
-+		hrtimer_start(&priv->fast_tx_timeout[queuenum].timer, kt,
-+			      HRTIMER_MODE_REL);
-+		return -1;
-+	} else {
-+		return 0;
-+	}
-+}
-+
-+#define SA_MAX_OP 2
-+/* pfe_hif_send_packet
-+ *
-+ * At this level if TX fails we drop the packet
-+ */
-+static void pfe_hif_send_packet(struct sk_buff *skb, struct  pfe_eth_priv_s
-+					*priv, int queuenum)
-+{
-+	struct skb_shared_info *sh = skb_shinfo(skb);
-+	unsigned int nr_frags;
-+	u32 ctrl = 0;
-+
-+	netif_info(priv, tx_queued, priv->ndev, "%s\n", __func__);
-+
-+	if (skb_is_gso(skb)) {
-+		priv->stats.tx_dropped++;
-+		return;
-+	}
-+
-+	if (skb->ip_summed == CHECKSUM_PARTIAL)
-+		ctrl = HIF_CTRL_TX_CHECKSUM;
-+
-+	nr_frags = sh->nr_frags;
-+
-+	if (nr_frags) {
-+		skb_frag_t *f;
-+		int i;
-+
-+		__hif_lib_xmit_pkt(&priv->client, queuenum, skb->data,
-+				   skb_headlen(skb), ctrl, HIF_FIRST_BUFFER,
-+				   skb);
-+
-+		for (i = 0; i < nr_frags - 1; i++) {
-+			f = &sh->frags[i];
-+			__hif_lib_xmit_pkt(&priv->client, queuenum,
-+					   skb_frag_address(f),
-+					   skb_frag_size(f),
-+					   0x0, 0x0, skb);
-+		}
-+
-+		f = &sh->frags[i];
-+
-+		__hif_lib_xmit_pkt(&priv->client, queuenum,
-+				   skb_frag_address(f), skb_frag_size(f),
-+				   0x0, HIF_LAST_BUFFER | HIF_DATA_VALID,
-+				   skb);
-+
-+		netif_info(priv, tx_queued, priv->ndev,
-+			   "%s: pkt sent successfully skb:%p nr_frags:%d len:%d\n",
-+			   __func__, skb, nr_frags, skb->len);
-+	} else {
-+		__hif_lib_xmit_pkt(&priv->client, queuenum, skb->data,
-+				   skb->len, ctrl, HIF_FIRST_BUFFER |
-+				   HIF_LAST_BUFFER | HIF_DATA_VALID,
-+				   skb);
-+		netif_info(priv, tx_queued, priv->ndev,
-+			   "%s: pkt sent successfully skb:%p len:%d\n",
-+			   __func__, skb, skb->len);
-+	}
-+	hif_tx_dma_start();
-+	priv->stats.tx_packets++;
-+	priv->stats.tx_bytes += skb->len;
-+	hif_lib_tx_credit_use(pfe, priv->id, queuenum, 1);
-+}
-+
-+/* pfe_eth_flush_txQ
-+ */
-+static void pfe_eth_flush_txQ(struct pfe_eth_priv_s *priv, int tx_q_num, int
-+				from_tx, int n_desc)
-+{
-+	struct sk_buff *skb;
-+	struct netdev_queue *tx_queue = netdev_get_tx_queue(priv->ndev,
-+								tx_q_num);
-+	unsigned int flags;
-+
-+	netif_info(priv, tx_done, priv->ndev, "%s\n", __func__);
-+
-+	if (!from_tx)
-+		__netif_tx_lock_bh(tx_queue);
-+
-+	/* Clean HIF and client queue */
-+	while ((skb = hif_lib_tx_get_next_complete(&priv->client,
-+						   tx_q_num, &flags,
-+						   HIF_TX_DESC_NT))) {
-+		if (flags & HIF_DATA_VALID)
-+			dev_kfree_skb_any(skb);
-+	}
-+	if (!from_tx)
-+		__netif_tx_unlock_bh(tx_queue);
-+}
-+
-+/* pfe_eth_flush_tx
-+ */
-+static void pfe_eth_flush_tx(struct pfe_eth_priv_s *priv)
-+{
-+	int ii;
-+
-+	netif_info(priv, tx_done, priv->ndev, "%s\n", __func__);
-+
-+	for (ii = 0; ii < emac_txq_cnt; ii++) {
-+		pfe_eth_flush_txQ(priv, ii, 0, 0);
-+		__hif_lib_update_credit(&priv->client, ii);
-+	}
-+}
-+
-+void pfe_tx_get_req_desc(struct sk_buff *skb, unsigned int *n_desc, unsigned int
-+				*n_segs)
-+{
-+	struct skb_shared_info *sh = skb_shinfo(skb);
-+
-+	/* Scattered data */
-+	if (sh->nr_frags) {
-+		*n_desc = sh->nr_frags + 1;
-+		*n_segs = 1;
-+	/* Regular case */
-+	} else {
-+		*n_desc = 1;
-+		*n_segs = 1;
-+	}
-+}
-+
-+/* pfe_eth_send_packet
-+ */
-+static int pfe_eth_send_packet(struct sk_buff *skb, struct net_device *ndev)
-+{
-+	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
-+	int tx_q_num = skb_get_queue_mapping(skb);
-+	int n_desc, n_segs;
-+	struct netdev_queue *tx_queue = netdev_get_tx_queue(priv->ndev,
-+								tx_q_num);
-+
-+	netif_info(priv, tx_queued, ndev, "%s\n", __func__);
-+
-+	if ((!skb_is_gso(skb)) && (skb_headroom(skb) < (PFE_PKT_HEADER_SZ +
-+			sizeof(unsigned long)))) {
-+		netif_warn(priv, tx_err, priv->ndev, "%s: copying skb\n",
-+			   __func__);
-+
-+		if (pskb_expand_head(skb, (PFE_PKT_HEADER_SZ + sizeof(unsigned
-+					long)), 0, GFP_ATOMIC)) {
-+			/* No need to re-transmit, no way to recover*/
-+			kfree_skb(skb);
-+			priv->stats.tx_dropped++;
-+			return NETDEV_TX_OK;
-+		}
-+	}
-+
-+	pfe_tx_get_req_desc(skb, &n_desc, &n_segs);
-+
-+	hif_tx_lock(&pfe->hif);
-+	if (unlikely(pfe_eth_might_stop_tx(priv, tx_q_num, tx_queue, n_desc,
-+					   n_segs))) {
-+#ifdef PFE_ETH_TX_STATS
-+		if (priv->was_stopped[tx_q_num]) {
-+			priv->clean_fail[tx_q_num]++;
-+			priv->was_stopped[tx_q_num] = 0;
-+		}
-+#endif
-+		hif_tx_unlock(&pfe->hif);
-+		return NETDEV_TX_BUSY;
-+	}
-+
-+	pfe_hif_send_packet(skb, priv, tx_q_num);
-+
-+	hif_tx_unlock(&pfe->hif);
-+
-+	tx_queue->trans_start = jiffies;
-+
-+#ifdef PFE_ETH_TX_STATS
-+	priv->was_stopped[tx_q_num] = 0;
-+#endif
-+
-+	return NETDEV_TX_OK;
-+}
-+
-+/* pfe_eth_select_queue
-+ *
-+ */
-+static u16 pfe_eth_select_queue(struct net_device *ndev, struct sk_buff *skb,
-+				struct net_device *sb_dev)
-+{
-+	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
-+
-+	return pfe_eth_get_queuenum(priv, skb);
-+}
-+
-+/* pfe_eth_get_stats
-+ */
-+static struct net_device_stats *pfe_eth_get_stats(struct net_device *ndev)
-+{
-+	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
-+
-+	netif_info(priv, drv, ndev, "%s\n", __func__);
-+
-+	return &priv->stats;
-+}
-+
-+/* pfe_eth_set_mac_address
-+ */
-+static int pfe_eth_set_mac_address(struct net_device *ndev, void *addr)
-+{
-+	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
-+	struct sockaddr *sa = addr;
-+
-+	netif_info(priv, drv, ndev, "%s\n", __func__);
-+
-+	if (!is_valid_ether_addr(sa->sa_data))
-+		return -EADDRNOTAVAIL;
-+
-+	memcpy(ndev->dev_addr, sa->sa_data, ETH_ALEN);
-+
-+	gemac_set_laddrN(priv->EMAC_baseaddr,
-+			 (struct pfe_mac_addr *)ndev->dev_addr, 1);
-+
-+	return 0;
-+}
-+
-+/* pfe_eth_enet_addr_byte_mac
-+ */
-+int pfe_eth_enet_addr_byte_mac(u8 *enet_byte_addr,
-+			       struct pfe_mac_addr *enet_addr)
-+{
-+	if (!enet_byte_addr || !enet_addr) {
-+		return -1;
-+
-+	} else {
-+		enet_addr->bottom = enet_byte_addr[0] |
-+			(enet_byte_addr[1] << 8) |
-+			(enet_byte_addr[2] << 16) |
-+			(enet_byte_addr[3] << 24);
-+		enet_addr->top = enet_byte_addr[4] |
-+			(enet_byte_addr[5] << 8);
-+		return 0;
-+	}
-+}
-+
-+/* pfe_eth_set_multi
-+ */
-+static void pfe_eth_set_multi(struct net_device *ndev)
-+{
-+	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
-+	struct pfe_mac_addr    hash_addr; /* hash register structure */
-+	/* specific mac address	register structure */
-+	struct pfe_mac_addr    spec_addr;
-+	int		result; /* index into hash register to set.. */
-+	int		uc_count = 0;
-+	struct netdev_hw_addr *ha;
-+
-+	if (ndev->flags & IFF_PROMISC) {
-+		netif_info(priv, drv, ndev, "entering promiscuous mode\n");
-+
-+		priv->promisc = 1;
-+		gemac_enable_copy_all(priv->EMAC_baseaddr);
-+	} else {
-+		priv->promisc = 0;
-+		gemac_disable_copy_all(priv->EMAC_baseaddr);
-+	}
-+
-+	/* Enable broadcast frame reception if required. */
-+	if (ndev->flags & IFF_BROADCAST) {
-+		gemac_allow_broadcast(priv->EMAC_baseaddr);
-+	} else {
-+		netif_info(priv, drv, ndev,
-+			   "disabling broadcast frame reception\n");
-+
-+		gemac_no_broadcast(priv->EMAC_baseaddr);
-+	}
-+
-+	if (ndev->flags & IFF_ALLMULTI) {
-+		/* Set the hash to rx all multicast frames */
-+		hash_addr.bottom = 0xFFFFFFFF;
-+		hash_addr.top = 0xFFFFFFFF;
-+		gemac_set_hash(priv->EMAC_baseaddr, &hash_addr);
-+		netdev_for_each_uc_addr(ha, ndev) {
-+			if (uc_count >= MAX_UC_SPEC_ADDR_REG)
-+				break;
-+			pfe_eth_enet_addr_byte_mac(ha->addr, &spec_addr);
-+			gemac_set_laddrN(priv->EMAC_baseaddr, &spec_addr,
-+					 uc_count + 2);
-+			uc_count++;
-+		}
-+	} else if ((netdev_mc_count(ndev) > 0)  || (netdev_uc_count(ndev))) {
-+		u8 *addr;
-+
-+		hash_addr.bottom = 0;
-+		hash_addr.top = 0;
-+
-+		netdev_for_each_mc_addr(ha, ndev) {
-+			addr = ha->addr;
-+
-+			netif_info(priv, drv, ndev,
-+				   "adding multicast address %X:%X:%X:%X:%X:%X to gem filter\n",
-+				addr[0], addr[1], addr[2],
-+				addr[3], addr[4], addr[5]);
-+
-+			result = pfe_eth_get_hash(addr);
-+
-+			if (result < EMAC_HASH_REG_BITS) {
-+				if (result < 32)
-+					hash_addr.bottom |= (1 << result);
-+				else
-+					hash_addr.top |= (1 << (result - 32));
-+			} else {
-+				break;
-+			}
-+		}
-+
-+		uc_count = -1;
-+		netdev_for_each_uc_addr(ha, ndev) {
-+			addr = ha->addr;
-+
-+			if (++uc_count < MAX_UC_SPEC_ADDR_REG)   {
-+				netdev_info(ndev,
-+					    "adding unicast address %02x:%02x:%02x:%02x:%02x:%02x to gem filter\n",
-+					    addr[0], addr[1], addr[2],
-+					    addr[3], addr[4], addr[5]);
-+				pfe_eth_enet_addr_byte_mac(addr, &spec_addr);
-+				gemac_set_laddrN(priv->EMAC_baseaddr,
-+						 &spec_addr, uc_count + 2);
-+			} else {
-+				netif_info(priv, drv, ndev,
-+					   "adding unicast address %02x:%02x:%02x:%02x:%02x:%02x to gem hash\n",
-+					   addr[0], addr[1], addr[2],
-+					   addr[3], addr[4], addr[5]);
-+
-+				result = pfe_eth_get_hash(addr);
-+				if (result >= EMAC_HASH_REG_BITS) {
-+					break;
-+
-+				} else {
-+					if (result < 32)
-+						hash_addr.bottom |= (1 <<
-+								result);
-+					else
-+						hash_addr.top |= (1 <<
-+								(result - 32));
-+				}
-+			}
-+		}
-+
-+		gemac_set_hash(priv->EMAC_baseaddr, &hash_addr);
-+	}
-+
-+	if (!(netdev_uc_count(ndev) >= MAX_UC_SPEC_ADDR_REG)) {
-+		/*
-+		 *  Check if there are any specific address HW registers that
-+		 * need to be flushed
-+		 */
-+		for (uc_count = netdev_uc_count(ndev); uc_count <
-+			MAX_UC_SPEC_ADDR_REG; uc_count++)
-+			gemac_clear_laddrN(priv->EMAC_baseaddr, uc_count + 2);
-+	}
-+
-+	if (ndev->flags & IFF_LOOPBACK)
-+		gemac_set_loop(priv->EMAC_baseaddr, LB_LOCAL);
-+}
-+
-+/* pfe_eth_set_features
-+ */
-+static int pfe_eth_set_features(struct net_device *ndev, netdev_features_t
-+					features)
-+{
-+	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
-+	int rc = 0;
-+
-+	if (features & NETIF_F_RXCSUM)
-+		gemac_enable_rx_checksum_offload(priv->EMAC_baseaddr);
-+	else
-+		gemac_disable_rx_checksum_offload(priv->EMAC_baseaddr);
-+	return rc;
-+}
-+
-+/* pfe_eth_fast_tx_timeout
-+ */
-+static enum hrtimer_restart pfe_eth_fast_tx_timeout(struct hrtimer *timer)
-+{
-+	struct pfe_eth_fast_timer *fast_tx_timeout = container_of(timer, struct
-+							pfe_eth_fast_timer,
-+							timer);
-+	struct pfe_eth_priv_s *priv =  container_of(fast_tx_timeout->base,
-+							struct pfe_eth_priv_s,
-+							fast_tx_timeout);
-+	struct netdev_queue *tx_queue = netdev_get_tx_queue(priv->ndev,
-+						fast_tx_timeout->queuenum);
-+
-+	if (netif_tx_queue_stopped(tx_queue)) {
-+#ifdef PFE_ETH_TX_STATS
-+		priv->was_stopped[fast_tx_timeout->queuenum] = 1;
-+#endif
-+		netif_tx_wake_queue(tx_queue);
-+	}
-+
-+	return HRTIMER_NORESTART;
-+}
-+
-+/* pfe_eth_fast_tx_timeout_init
-+ */
-+static void pfe_eth_fast_tx_timeout_init(struct pfe_eth_priv_s *priv)
-+{
-+	int i;
-+
-+	for (i = 0; i < emac_txq_cnt; i++) {
-+		priv->fast_tx_timeout[i].queuenum = i;
-+		hrtimer_init(&priv->fast_tx_timeout[i].timer, CLOCK_MONOTONIC,
-+			     HRTIMER_MODE_REL);
-+		priv->fast_tx_timeout[i].timer.function =
-+				pfe_eth_fast_tx_timeout;
-+		priv->fast_tx_timeout[i].base = priv->fast_tx_timeout;
-+	}
-+}
-+
-+static struct sk_buff *pfe_eth_rx_skb(struct net_device *ndev,
-+				      struct	pfe_eth_priv_s *priv,
-+				      unsigned int qno)
-+{
-+	void *buf_addr;
-+	unsigned int rx_ctrl;
-+	unsigned int desc_ctrl = 0;
-+	struct hif_ipsec_hdr *ipsec_hdr = NULL;
-+	struct sk_buff *skb;
-+	struct sk_buff *skb_frag, *skb_frag_last = NULL;
-+	int length = 0, offset;
-+
-+	skb = priv->skb_inflight[qno];
-+
-+	if (skb) {
-+		skb_frag_last = skb_shinfo(skb)->frag_list;
-+		if (skb_frag_last) {
-+			while (skb_frag_last->next)
-+				skb_frag_last = skb_frag_last->next;
-+		}
-+	}
-+
-+	while (!(desc_ctrl & CL_DESC_LAST)) {
-+		buf_addr = hif_lib_receive_pkt(&priv->client, qno, &length,
-+					       &offset, &rx_ctrl, &desc_ctrl,
-+					       (void **)&ipsec_hdr);
-+		if (!buf_addr)
-+			goto incomplete;
-+
-+#ifdef PFE_ETH_NAPI_STATS
-+		priv->napi_counters[NAPI_DESC_COUNT]++;
-+#endif
-+
-+		/* First frag */
-+		if (desc_ctrl & CL_DESC_FIRST) {
-+			skb = build_skb(buf_addr, 0);
-+			if (unlikely(!skb))
-+				goto pkt_drop;
-+
-+			skb_reserve(skb, offset);
-+			skb_put(skb, length);
-+			skb->dev = ndev;
-+
-+			if ((ndev->features & NETIF_F_RXCSUM) && (rx_ctrl &
-+					HIF_CTRL_RX_CHECKSUMMED))
-+				skb->ip_summed = CHECKSUM_UNNECESSARY;
-+			else
-+				skb_checksum_none_assert(skb);
-+
-+		} else {
-+			/* Next frags */
-+			if (unlikely(!skb)) {
-+				pr_err("%s: NULL skb_inflight\n",
-+				       __func__);
-+				goto pkt_drop;
-+			}
-+
-+			skb_frag = build_skb(buf_addr, 0);
-+
-+			if (unlikely(!skb_frag)) {
-+				kfree(buf_addr);
-+				goto pkt_drop;
-+			}
-+
-+			skb_reserve(skb_frag, offset);
-+			skb_put(skb_frag, length);
-+
-+			skb_frag->dev = ndev;
-+
-+			if (skb_shinfo(skb)->frag_list)
-+				skb_frag_last->next = skb_frag;
-+			else
-+				skb_shinfo(skb)->frag_list = skb_frag;
-+
-+			skb->truesize += skb_frag->truesize;
-+			skb->data_len += length;
-+			skb->len += length;
-+			skb_frag_last = skb_frag;
-+		}
-+	}
-+
-+	priv->skb_inflight[qno] = NULL;
-+	return skb;
-+
-+incomplete:
-+	priv->skb_inflight[qno] = skb;
-+	return NULL;
-+
-+pkt_drop:
-+	priv->skb_inflight[qno] = NULL;
-+
-+	if (skb)
-+		kfree_skb(skb);
-+	else
-+		kfree(buf_addr);
-+
-+	priv->stats.rx_errors++;
-+
-+	return NULL;
-+}
-+
-+/* pfe_eth_poll
-+ */
-+static int pfe_eth_poll(struct pfe_eth_priv_s *priv, struct napi_struct *napi,
-+			unsigned int qno, int budget)
-+{
-+	struct net_device *ndev = priv->ndev;
-+	struct sk_buff *skb;
-+	int work_done = 0;
-+	unsigned int len;
-+
-+	netif_info(priv, intr, priv->ndev, "%s\n", __func__);
-+
-+#ifdef PFE_ETH_NAPI_STATS
-+	priv->napi_counters[NAPI_POLL_COUNT]++;
-+#endif
-+
-+	do {
-+		skb = pfe_eth_rx_skb(ndev, priv, qno);
-+
-+		if (!skb)
-+			break;
-+
-+		len = skb->len;
-+
-+		/* Packet will be processed */
-+		skb->protocol = eth_type_trans(skb, ndev);
-+
-+		netif_receive_skb(skb);
-+
-+		priv->stats.rx_packets++;
-+		priv->stats.rx_bytes += len;
-+
-+		work_done++;
-+
-+#ifdef PFE_ETH_NAPI_STATS
-+		priv->napi_counters[NAPI_PACKET_COUNT]++;
-+#endif
-+
-+	} while (work_done < budget);
-+
-+	/*
-+	 * If no Rx receive nor cleanup work was done, exit polling mode.
-+	 * No more netif_running(dev) check is required here , as this is
-+	 * checked in net/core/dev.c (2.6.33.5 kernel specific).
-+	 */
-+	if (work_done < budget) {
-+		napi_complete(napi);
-+
-+		hif_lib_event_handler_start(&priv->client, EVENT_RX_PKT_IND,
-+					    qno);
-+	}
-+#ifdef PFE_ETH_NAPI_STATS
-+	else
-+		priv->napi_counters[NAPI_FULL_BUDGET_COUNT]++;
-+#endif
-+
-+	return work_done;
-+}
-+
-+/*
-+ * pfe_eth_lro_poll
-+ */
-+static int pfe_eth_lro_poll(struct napi_struct *napi, int budget)
-+{
-+	struct pfe_eth_priv_s *priv = container_of(napi, struct pfe_eth_priv_s,
-+							lro_napi);
-+
-+	netif_info(priv, intr, priv->ndev, "%s\n", __func__);
-+
-+	return pfe_eth_poll(priv, napi, 2, budget);
-+}
-+
-+/* pfe_eth_low_poll
-+ */
-+static int pfe_eth_low_poll(struct napi_struct *napi, int budget)
-+{
-+	struct pfe_eth_priv_s *priv = container_of(napi, struct pfe_eth_priv_s,
-+							low_napi);
-+
-+	netif_info(priv, intr, priv->ndev, "%s\n", __func__);
-+
-+	return pfe_eth_poll(priv, napi, 1, budget);
-+}
-+
-+/* pfe_eth_high_poll
-+ */
-+static int pfe_eth_high_poll(struct napi_struct *napi, int budget)
-+{
-+	struct pfe_eth_priv_s *priv = container_of(napi, struct pfe_eth_priv_s,
-+							high_napi);
-+
-+	netif_info(priv, intr, priv->ndev, "%s\n", __func__);
-+
-+	return pfe_eth_poll(priv, napi, 0, budget);
-+}
-+
-+static const struct net_device_ops pfe_netdev_ops = {
-+	.ndo_open = pfe_eth_open,
-+	.ndo_stop = pfe_eth_close,
-+	.ndo_start_xmit = pfe_eth_send_packet,
-+	.ndo_select_queue = pfe_eth_select_queue,
-+	.ndo_set_rx_mode = pfe_eth_set_multi,
-+	.ndo_set_mac_address = pfe_eth_set_mac_address,
-+	.ndo_validate_addr = eth_validate_addr,
-+	.ndo_change_mtu = pfe_eth_change_mtu,
-+	.ndo_get_stats = pfe_eth_get_stats,
-+	.ndo_set_features = pfe_eth_set_features,
-+};
-+
-+/* pfe_eth_init_one
-+ */
-+static int pfe_eth_init_one(struct pfe *pfe,
-+			    struct ls1012a_pfe_platform_data *pfe_info,
-+			    int id)
-+{
-+	struct net_device *ndev = NULL;
-+	struct pfe_eth_priv_s *priv = NULL;
-+	struct ls1012a_eth_platform_data *einfo;
-+	int err;
-+
-+	einfo = (struct ls1012a_eth_platform_data *)
-+				pfe_info->ls1012a_eth_pdata;
-+
-+	/* einfo never be NULL, but no harm in having this check */
-+	if (!einfo) {
-+		pr_err(
-+			"%s: pfe missing additional gemacs platform data\n"
-+			, __func__);
-+		err = -ENODEV;
-+		goto err0;
-+	}
-+
-+	if (us)
-+		emac_txq_cnt = EMAC_TXQ_CNT;
-+	/* Create an ethernet device instance */
-+	ndev = alloc_etherdev_mq(sizeof(*priv), emac_txq_cnt);
-+
-+	if (!ndev) {
-+		pr_err("%s: gemac %d device allocation failed\n",
-+		       __func__, einfo[id].gem_id);
-+		err = -ENOMEM;
-+		goto err0;
-+	}
-+
-+	priv = netdev_priv(ndev);
-+	priv->ndev = ndev;
-+	priv->id = einfo[id].gem_id;
-+	priv->pfe = pfe;
-+	priv->phy_node = einfo[id].phy_node;
-+
-+	SET_NETDEV_DEV(priv->ndev, priv->pfe->dev);
-+
-+	pfe->eth.eth_priv[id] = priv;
-+
-+	/* Set the info in the priv to the current info */
-+	priv->einfo = &einfo[id];
-+	priv->EMAC_baseaddr = cbus_emac_base[id];
-+	priv->GPI_baseaddr = cbus_gpi_base[id];
-+
-+	spin_lock_init(&priv->lock);
-+
-+	pfe_eth_fast_tx_timeout_init(priv);
-+
-+	/* Copy the station address into the dev structure, */
-+	memcpy(ndev->dev_addr, einfo[id].mac_addr, ETH_ALEN);
-+
-+	if (us)
-+		goto phy_init;
-+
-+	ndev->mtu = 1500;
-+
-+	/* Set MTU limits */
-+	ndev->min_mtu = ETH_MIN_MTU;
-+
-+/*
-+ * Jumbo frames are not supported on LS1012A rev-1.0.
-+ * So max mtu should be restricted to supported frame length.
-+ */
-+	if (pfe_errata_a010897)
-+		ndev->max_mtu = JUMBO_FRAME_SIZE_V1 - ETH_HLEN - ETH_FCS_LEN;
-+	else
-+		ndev->max_mtu = JUMBO_FRAME_SIZE_V2 - ETH_HLEN - ETH_FCS_LEN;
-+
-+	/*Enable after checksum offload is validated */
-+	ndev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM |
-+		NETIF_F_IPV6_CSUM | NETIF_F_SG;
-+
-+	/* enabled by default */
-+	ndev->features = ndev->hw_features;
-+
-+	priv->usr_features = ndev->features;
-+
-+	ndev->netdev_ops = &pfe_netdev_ops;
-+
-+	ndev->ethtool_ops = &pfe_ethtool_ops;
-+
-+	/* Enable basic messages by default */
-+	priv->msg_enable = NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_LINK |
-+				NETIF_MSG_PROBE;
-+
-+	netif_napi_add(ndev, &priv->low_napi, pfe_eth_low_poll,
-+		       HIF_RX_POLL_WEIGHT - 16);
-+	netif_napi_add(ndev, &priv->high_napi, pfe_eth_high_poll,
-+		       HIF_RX_POLL_WEIGHT - 16);
-+	netif_napi_add(ndev, &priv->lro_napi, pfe_eth_lro_poll,
-+		       HIF_RX_POLL_WEIGHT - 16);
-+
-+	err = register_netdev(ndev);
-+	if (err) {
-+		netdev_err(ndev, "register_netdev() failed\n");
-+		goto err1;
-+	}
-+
-+	if ((!(pfe_use_old_dts_phy) && !(priv->phy_node)) ||
-+	    ((pfe_use_old_dts_phy) &&
-+	      (priv->einfo->phy_flags & GEMAC_NO_PHY))) {
-+		pr_info("%s: No PHY or fixed-link\n", __func__);
-+		goto skip_phy_init;
-+	}
-+
-+phy_init:
-+	device_init_wakeup(&ndev->dev, WAKE_MAGIC);
-+
-+	err = pfe_phy_init(ndev);
-+	if (err) {
-+		netdev_err(ndev, "%s: pfe_phy_init() failed\n",
-+			   __func__);
-+		goto err2;
-+	}
-+
-+	if (us) {
-+		if (priv->phydev)
-+			phy_start(priv->phydev);
-+		return 0;
-+	}
-+
-+	netif_carrier_on(ndev);
-+
-+skip_phy_init:
-+	/* Create all the sysfs files */
-+	if (pfe_eth_sysfs_init(ndev))
-+		goto err3;
-+
-+	netif_info(priv, probe, ndev, "%s: created interface, baseaddr: %p\n",
-+		   __func__, priv->EMAC_baseaddr);
-+
-+	return 0;
-+
-+err3:
-+	pfe_phy_exit(priv->ndev);
-+err2:
-+	if (us)
-+		goto err1;
-+	unregister_netdev(ndev);
-+err1:
-+	free_netdev(priv->ndev);
-+err0:
-+	return err;
-+}
-+
-+/* pfe_eth_init
-+ */
-+int pfe_eth_init(struct pfe *pfe)
-+{
-+	int ii = 0;
-+	int err;
-+	struct ls1012a_pfe_platform_data *pfe_info;
-+
-+	pr_info("%s\n", __func__);
-+
-+	cbus_emac_base[0] = EMAC1_BASE_ADDR;
-+	cbus_emac_base[1] = EMAC2_BASE_ADDR;
-+
-+	cbus_gpi_base[0] = EGPI1_BASE_ADDR;
-+	cbus_gpi_base[1] = EGPI2_BASE_ADDR;
-+
-+	pfe_info = (struct ls1012a_pfe_platform_data *)
-+					pfe->dev->platform_data;
-+	if (!pfe_info) {
-+		pr_err("%s: pfe missing additional platform data\n", __func__);
-+		err = -ENODEV;
-+		goto err_pdata;
-+	}
-+
-+	for (ii = 0; ii < NUM_GEMAC_SUPPORT; ii++) {
-+		err = pfe_eth_mdio_init(pfe, pfe_info, ii);
-+		if (err) {
-+			pr_err("%s: pfe_eth_mdio_init() failed\n", __func__);
-+			goto err_mdio_init;
-+		}
-+	}
-+
-+	if (soc_device_match(ls1012a_rev1_soc_attr))
-+		pfe_errata_a010897 = true;
-+	else
-+		pfe_errata_a010897 = false;
-+
-+	for (ii = 0; ii < NUM_GEMAC_SUPPORT; ii++) {
-+		err = pfe_eth_init_one(pfe, pfe_info, ii);
-+		if (err)
-+			goto err_eth_init;
-+	}
-+
-+	return 0;
-+
-+err_eth_init:
-+	while (ii--) {
-+		pfe_eth_exit_one(pfe->eth.eth_priv[ii]);
-+		pfe_eth_mdio_exit(pfe, ii);
-+	}
-+
-+err_mdio_init:
-+err_pdata:
-+	return err;
-+}
-+
-+/* pfe_eth_exit_one
-+ */
-+static void pfe_eth_exit_one(struct pfe_eth_priv_s *priv)
-+{
-+	netif_info(priv, probe, priv->ndev, "%s\n", __func__);
-+
-+	if (!us)
-+		pfe_eth_sysfs_exit(priv->ndev);
-+
-+	if ((!(pfe_use_old_dts_phy) && !(priv->phy_node)) ||
-+	    ((pfe_use_old_dts_phy) &&
-+	      (priv->einfo->phy_flags & GEMAC_NO_PHY))) {
-+		pr_info("%s: No PHY or fixed-link\n", __func__);
-+		goto skip_phy_exit;
-+	}
-+
-+	pfe_phy_exit(priv->ndev);
-+
-+skip_phy_exit:
-+	if (!us)
-+		unregister_netdev(priv->ndev);
-+
-+	free_netdev(priv->ndev);
-+}
-+
-+/* pfe_eth_exit
-+ */
-+void pfe_eth_exit(struct pfe *pfe)
-+{
-+	int ii;
-+
-+	pr_info("%s\n", __func__);
-+
-+	for (ii = NUM_GEMAC_SUPPORT - 1; ii >= 0; ii--)
-+		pfe_eth_exit_one(pfe->eth.eth_priv[ii]);
-+
-+	for (ii = NUM_GEMAC_SUPPORT - 1; ii >= 0; ii--)
-+		pfe_eth_mdio_exit(pfe, ii);
-+}
---- /dev/null
-+++ b/drivers/staging/fsl_ppfe/pfe_eth.h
-@@ -0,0 +1,175 @@
-+/* SPDX-License-Identifier: GPL-2.0+ */
-+/*
-+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
-+ * Copyright 2017 NXP
-+ */
-+
-+#ifndef _PFE_ETH_H_
-+#define _PFE_ETH_H_
-+#include <linux/kernel.h>
-+#include <linux/netdevice.h>
-+#include <linux/etherdevice.h>
-+#include <linux/ethtool.h>
-+#include <linux/mii.h>
-+#include <linux/phy.h>
-+#include <linux/clk.h>
-+#include <linux/interrupt.h>
-+#include <linux/time.h>
-+
-+#define PFE_ETH_NAPI_STATS
-+#define PFE_ETH_TX_STATS
-+
-+#define PFE_ETH_FRAGS_MAX (65536 / HIF_RX_PKT_MIN_SIZE)
-+#define LRO_LEN_COUNT_MAX	32
-+#define LRO_NB_COUNT_MAX	32
-+
-+#define PFE_PAUSE_FLAG_ENABLE		1
-+#define PFE_PAUSE_FLAG_AUTONEG		2
-+
-+/* GEMAC configured by SW */
-+/* GEMAC configured by phy lines (not for MII/GMII) */
-+
-+#define GEMAC_SW_FULL_DUPLEX    BIT(9)
-+#define GEMAC_SW_SPEED_10M      (0 << 12)
-+#define GEMAC_SW_SPEED_100M     BIT(12)
-+#define GEMAC_SW_SPEED_1G       (2 << 12)
-+
-+#define GEMAC_NO_PHY            BIT(0)
-+
-+struct ls1012a_eth_platform_data {
-+	/* board specific information */
-+	phy_interface_t mii_config;
-+	u32 phy_flags;
-+	u32 gem_id;
-+	u32 phy_id;
-+	u32 mdio_muxval;
-+	u8 mac_addr[ETH_ALEN];
-+	struct device_node	*phy_node;
-+};
-+
-+struct ls1012a_mdio_platform_data {
-+	int id;
-+	int irq[32];
-+	u32 phy_mask;
-+	int mdc_div;
-+};
-+
-+struct ls1012a_pfe_platform_data {
-+	struct ls1012a_eth_platform_data ls1012a_eth_pdata[3];
-+	struct ls1012a_mdio_platform_data ls1012a_mdio_pdata[3];
-+};
-+
-+#define NUM_GEMAC_SUPPORT	2
-+#define DRV_NAME		"pfe-eth"
-+#define DRV_VERSION		"1.0"
-+
-+#define LS1012A_TX_FAST_RECOVERY_TIMEOUT_MS	3
-+#define TX_POLL_TIMEOUT_MS	1000
-+
-+#define EMAC_TXQ_CNT	16
-+#define EMAC_TXQ_DEPTH	(HIF_TX_DESC_NT)
-+
-+#define JUMBO_FRAME_SIZE_V1	1900
-+#define JUMBO_FRAME_SIZE_V2	10258
-+/*
-+ * Client Tx queue threshold, for txQ flush condition.
-+ * It must be smaller than the queue size (in case we ever change it in the
-+ * future).
-+ */
-+#define HIF_CL_TX_FLUSH_MARK	32
-+
-+/*
-+ * Max number of TX resources (HIF descriptors or skbs) that will be released
-+ * in a single go during batch recycling.
-+ * Should be lower than the flush mark so the SW can provide the HW with a
-+ * continuous stream of packets instead of bursts.
-+ */
-+#define TX_FREE_MAX_COUNT 16
-+#define EMAC_RXQ_CNT	3
-+#define EMAC_RXQ_DEPTH	HIF_RX_DESC_NT
-+/* make sure clients can receive a full burst of packets */
-+#define EMAC_RMON_TXBYTES_POS	0x00
-+#define EMAC_RMON_RXBYTES_POS	0x14
-+
-+#define EMAC_QUEUENUM_MASK      (emac_txq_cnt - 1)
-+#define EMAC_MDIO_TIMEOUT	1000
-+#define MAX_UC_SPEC_ADDR_REG 31
-+
-+struct pfe_eth_fast_timer {
-+	int queuenum;
-+	struct hrtimer timer;
-+	void *base;
-+};
-+
-+struct  pfe_eth_priv_s {
-+	struct pfe		*pfe;
-+	struct hif_client_s	client;
-+	struct napi_struct	lro_napi;
-+	struct napi_struct	low_napi;
-+	struct napi_struct	high_napi;
-+	int			low_tmu_q;
-+	int			high_tmu_q;
-+	struct net_device_stats stats;
-+	struct net_device	*ndev;
-+	int			id;
-+	int			promisc;
-+	unsigned int		msg_enable;
-+	unsigned int		usr_features;
-+
-+	spinlock_t		lock; /* protect member variables */
-+	unsigned int		event_status;
-+	int			irq;
-+	void			*EMAC_baseaddr;
-+	void			*GPI_baseaddr;
-+	/* PHY stuff */
-+	struct phy_device	*phydev;
-+	int			oldspeed;
-+	int			oldduplex;
-+	int			oldlink;
-+	struct device_node	*phy_node;
-+	struct clk		*gemtx_clk;
-+	int			wol;
-+	int			pause_flag;
-+
-+	int			default_priority;
-+	struct pfe_eth_fast_timer fast_tx_timeout[EMAC_TXQ_CNT];
-+
-+	struct ls1012a_eth_platform_data *einfo;
-+	struct sk_buff *skb_inflight[EMAC_RXQ_CNT + 6];
-+
-+#ifdef PFE_ETH_TX_STATS
-+	unsigned int stop_queue_total[EMAC_TXQ_CNT];
-+	unsigned int stop_queue_hif[EMAC_TXQ_CNT];
-+	unsigned int stop_queue_hif_client[EMAC_TXQ_CNT];
-+	unsigned int stop_queue_credit[EMAC_TXQ_CNT];
-+	unsigned int clean_fail[EMAC_TXQ_CNT];
-+	unsigned int was_stopped[EMAC_TXQ_CNT];
-+#endif
-+
-+#ifdef PFE_ETH_NAPI_STATS
-+	unsigned int napi_counters[NAPI_MAX_COUNT];
-+#endif
-+	unsigned int frags_inflight[EMAC_RXQ_CNT + 6];
-+};
-+
-+struct pfe_eth {
-+	struct pfe_eth_priv_s *eth_priv[3];
-+};
-+
-+struct pfe_mdio_priv_s {
-+	void __iomem *mdio_base;
-+	int			mdc_div;
-+	struct mii_bus		*mii_bus;
-+};
-+
-+struct pfe_mdio {
-+	struct pfe_mdio_priv_s *mdio_priv[3];
-+};
-+
-+int pfe_eth_init(struct pfe *pfe);
-+void pfe_eth_exit(struct pfe *pfe);
-+int pfe_eth_suspend(struct net_device *dev);
-+int pfe_eth_resume(struct net_device *dev);
-+int pfe_eth_mdio_reset(struct mii_bus *bus);
-+
-+#endif /* _PFE_ETH_H_ */
---- /dev/null
-+++ b/drivers/staging/fsl_ppfe/pfe_firmware.c
-@@ -0,0 +1,398 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+/*
-+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
-+ * Copyright 2017 NXP
-+ */
-+
-+/*
-+ * @file
-+ * Contains all the functions to handle parsing and loading of PE firmware
-+ * files.
-+ */
-+#include <linux/firmware.h>
-+
-+#include "pfe_mod.h"
-+#include "pfe_firmware.h"
-+#include "pfe/pfe.h"
-+#include <linux/of_platform.h>
-+#include <linux/of_address.h>
-+
-+static struct elf32_shdr *get_elf_section_header(const u8 *fw,
-+						 const char *section)
-+{
-+	struct elf32_hdr *elf_hdr = (struct elf32_hdr *)fw;
-+	struct elf32_shdr *shdr;
-+	struct elf32_shdr *shdr_shstr;
-+	Elf32_Off e_shoff = be32_to_cpu(elf_hdr->e_shoff);
-+	Elf32_Half e_shentsize = be16_to_cpu(elf_hdr->e_shentsize);
-+	Elf32_Half e_shnum = be16_to_cpu(elf_hdr->e_shnum);
-+	Elf32_Half e_shstrndx = be16_to_cpu(elf_hdr->e_shstrndx);
-+	Elf32_Off shstr_offset;
-+	Elf32_Word sh_name;
-+	const char *name;
-+	int i;
-+
-+	/* Section header strings */
-+	shdr_shstr = (struct elf32_shdr *)((u8 *)elf_hdr + e_shoff + e_shstrndx
-+					* e_shentsize);
-+	shstr_offset = be32_to_cpu(shdr_shstr->sh_offset);
-+
-+	for (i = 0; i < e_shnum; i++) {
-+		shdr = (struct elf32_shdr *)((u8 *)elf_hdr + e_shoff
-+					     + i * e_shentsize);
-+
-+		sh_name = be32_to_cpu(shdr->sh_name);
-+
-+		name = (const char *)((u8 *)elf_hdr + shstr_offset + sh_name);
-+
-+		if (!strcmp(name, section))
-+			return shdr;
-+	}
-+
-+	pr_err("%s: didn't find section %s\n", __func__, section);
-+
-+	return NULL;
-+}
-+
-+#if defined(CFG_DIAGS)
-+static int pfe_get_diags_info(const u8 *fw, struct pfe_diags_info
-+				*diags_info)
-+{
-+	struct elf32_shdr *shdr;
-+	unsigned long offset, size;
-+
-+	shdr = get_elf_section_header(fw, ".pfe_diags_str");
-+	if (shdr) {
-+		offset = be32_to_cpu(shdr->sh_offset);
-+		size = be32_to_cpu(shdr->sh_size);
-+		diags_info->diags_str_base = be32_to_cpu(shdr->sh_addr);
-+		diags_info->diags_str_size = size;
-+		diags_info->diags_str_array = kmalloc(size, GFP_KERNEL);
-+		memcpy(diags_info->diags_str_array, fw + offset, size);
-+
-+		return 0;
-+	} else {
-+		return -1;
-+	}
-+}
-+#endif
-+
-+static void pfe_check_version_info(const u8 *fw)
-+{
-+	/*static char *version = NULL;*/
-+	const u8 *elf_data = fw;
-+	static char *version;
-+
-+	struct elf32_shdr *shdr = get_elf_section_header(fw, ".version");
-+
-+	if (shdr) {
-+		if (!version) {
-+			/*
-+			 * this is the first fw we load, use its version
-+			 * string as reference (whatever it is)
-+			 */
-+			version = (char *)(elf_data +
-+					be32_to_cpu(shdr->sh_offset));
-+
-+			pr_info("PFE binary version: %s\n", version);
-+		} else {
-+			/*
-+			 * already have loaded at least one firmware, check
-+			 * sequence can start now
-+			 */
-+			if (strcmp(version, (char *)(elf_data +
-+				be32_to_cpu(shdr->sh_offset)))) {
-+				pr_info(
-+				"WARNING: PFE firmware binaries from incompatible version\n");
-+			}
-+		}
-+	} else {
-+		/*
-+		 * version cannot be verified, a potential issue that should
-+		 * be reported
-+		 */
-+		pr_info(
-+			 "WARNING: PFE firmware binaries from incompatible version\n");
-+	}
-+}
-+
-+/* PFE elf firmware loader.
-+ * Loads an elf firmware image into a list of PE's (specified using a bitmask)
-+ *
-+ * @param pe_mask	Mask of PE id's to load firmware to
-+ * @param fw		Pointer to the firmware image
-+ *
-+ * @return		0 on success, a negative value on error
-+ *
-+ */
-+int pfe_load_elf(int pe_mask, const u8 *fw, struct pfe *pfe)
-+{
-+	struct elf32_hdr *elf_hdr = (struct elf32_hdr *)fw;
-+	Elf32_Half sections = be16_to_cpu(elf_hdr->e_shnum);
-+	struct elf32_shdr *shdr = (struct elf32_shdr *)(fw +
-+					be32_to_cpu(elf_hdr->e_shoff));
-+	int id, section;
-+	int rc;
-+
-+	pr_info("%s\n", __func__);
-+
-+	/* Some sanity checks */
-+	if (strncmp(&elf_hdr->e_ident[EI_MAG0], ELFMAG, SELFMAG)) {
-+		pr_err("%s: incorrect elf magic number\n", __func__);
-+		return -EINVAL;
-+	}
-+
-+	if (elf_hdr->e_ident[EI_CLASS] != ELFCLASS32) {
-+		pr_err("%s: incorrect elf class(%x)\n", __func__,
-+		       elf_hdr->e_ident[EI_CLASS]);
-+		return -EINVAL;
-+	}
-+
-+	if (elf_hdr->e_ident[EI_DATA] != ELFDATA2MSB) {
-+		pr_err("%s: incorrect elf data(%x)\n", __func__,
-+		       elf_hdr->e_ident[EI_DATA]);
-+		return -EINVAL;
-+	}
-+
-+	if (be16_to_cpu(elf_hdr->e_type) != ET_EXEC) {
-+		pr_err("%s: incorrect elf file type(%x)\n", __func__,
-+		       be16_to_cpu(elf_hdr->e_type));
-+		return -EINVAL;
-+	}
-+
-+	for (section = 0; section < sections; section++, shdr++) {
-+		if (!(be32_to_cpu(shdr->sh_flags) & (SHF_WRITE | SHF_ALLOC |
-+			SHF_EXECINSTR)))
-+			continue;
-+
-+		for (id = 0; id < MAX_PE; id++)
-+			if (pe_mask & (1 << id)) {
-+				rc = pe_load_elf_section(id, elf_hdr, shdr,
-+							 pfe->dev);
-+				if (rc < 0)
-+					goto err;
-+			}
-+	}
-+
-+	pfe_check_version_info(fw);
-+
-+	return 0;
-+
-+err:
-+	return rc;
-+}
-+
-+int get_firmware_in_fdt(const u8 **pe_fw, const char *name)
-+{
-+	struct device_node *np;
-+	const unsigned int *len;
-+	const void *data;
-+
-+	if (!strcmp(name, CLASS_FIRMWARE_FILENAME)) {
-+		/* The firmware should be inside the device tree. */
-+		np = of_find_compatible_node(NULL, NULL,
-+					     "fsl,pfe-class-firmware");
-+		if (!np) {
-+			pr_info("Failed to find the node\n");
-+			return -ENOENT;
-+		}
-+
-+		data = of_get_property(np, "fsl,class-firmware", NULL);
-+		if (data) {
-+			len = of_get_property(np, "length", NULL);
-+			pr_info("CLASS fw of length %d bytes loaded from FDT.\n",
-+				be32_to_cpu(*len));
-+		} else {
-+			pr_info("fsl,class-firmware not found!!!!\n");
-+			return -ENOENT;
-+		}
-+		of_node_put(np);
-+		*pe_fw = data;
-+	} else if (!strcmp(name, TMU_FIRMWARE_FILENAME)) {
-+		np = of_find_compatible_node(NULL, NULL,
-+					     "fsl,pfe-tmu-firmware");
-+		if (!np) {
-+			pr_info("Failed to find the node\n");
-+			return -ENOENT;
-+		}
-+
-+		data = of_get_property(np, "fsl,tmu-firmware", NULL);
-+		if (data) {
-+			len = of_get_property(np, "length", NULL);
-+			pr_info("TMU fw of length %d bytes loaded from FDT.\n",
-+				be32_to_cpu(*len));
-+		} else {
-+			pr_info("fsl,tmu-firmware not found!!!!\n");
-+			return -ENOENT;
-+		}
-+		of_node_put(np);
-+		*pe_fw = data;
-+	} else if (!strcmp(name, UTIL_FIRMWARE_FILENAME)) {
-+		np = of_find_compatible_node(NULL, NULL,
-+					     "fsl,pfe-util-firmware");
-+		if (!np) {
-+			pr_info("Failed to find the node\n");
-+			return -ENOENT;
-+		}
-+
-+		data = of_get_property(np, "fsl,util-firmware", NULL);
-+		if (data) {
-+			len = of_get_property(np, "length", NULL);
-+			pr_info("UTIL fw of length %d bytes loaded from FDT.\n",
-+				be32_to_cpu(*len));
-+		} else {
-+			pr_info("fsl,util-firmware not found!!!!\n");
-+			return -ENOENT;
-+		}
-+		of_node_put(np);
-+		*pe_fw = data;
-+	} else {
-+		pr_err("firmware:%s not known\n", name);
-+		return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+
-+/* PFE firmware initialization.
-+ * Loads different firmware files from filesystem.
-+ * Initializes PE IMEM/DMEM and UTIL-PE DDR
-+ * Initializes control path symbol addresses (by looking them up in the elf
-+ * firmware files
-+ * Takes PE's out of reset
-+ *
-+ * @return	0 on success, a negative value on error
-+ *
-+ */
-+int pfe_firmware_init(struct pfe *pfe)
-+{
-+	const struct firmware *class_fw, *tmu_fw;
-+	const u8 *class_elf_fw, *tmu_elf_fw;
-+	int rc = 0, fs_load = 0;
-+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
-+	const struct firmware *util_fw;
-+	const u8 *util_elf_fw;
-+
-+#endif
-+
-+	pr_info("%s\n", __func__);
-+
-+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
-+	if (get_firmware_in_fdt(&class_elf_fw, CLASS_FIRMWARE_FILENAME) ||
-+	    get_firmware_in_fdt(&tmu_elf_fw, TMU_FIRMWARE_FILENAME) ||
-+	    get_firmware_in_fdt(&util_elf_fw, UTIL_FIRMWARE_FILENAME))
-+#else
-+	if (get_firmware_in_fdt(&class_elf_fw, CLASS_FIRMWARE_FILENAME) ||
-+	    get_firmware_in_fdt(&tmu_elf_fw, TMU_FIRMWARE_FILENAME))
-+#endif
-+	{
-+		pr_info("%s:PFE firmware not found in FDT.\n", __func__);
-+		pr_info("%s:Trying to load firmware from filesystem...!\n", __func__);
-+
-+		/* look for firmware in filesystem...!*/
-+		fs_load = 1;
-+		if (request_firmware(&class_fw, CLASS_FIRMWARE_FILENAME, pfe->dev)) {
-+			pr_err("%s: request firmware %s failed\n", __func__,
-+			       CLASS_FIRMWARE_FILENAME);
-+			rc = -ETIMEDOUT;
-+			goto err0;
-+		}
-+		class_elf_fw = class_fw->data;
-+
-+		if (request_firmware(&tmu_fw, TMU_FIRMWARE_FILENAME, pfe->dev)) {
-+			pr_err("%s: request firmware %s failed\n", __func__,
-+			       TMU_FIRMWARE_FILENAME);
-+			rc = -ETIMEDOUT;
-+			goto err1;
-+		}
-+		tmu_elf_fw = tmu_fw->data;
-+
-+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
-+		if (request_firmware(&util_fw, UTIL_FIRMWARE_FILENAME, pfe->dev)) {
-+			pr_err("%s: request firmware %s failed\n", __func__,
-+			       UTIL_FIRMWARE_FILENAME);
-+			rc = -ETIMEDOUT;
-+			goto err2;
-+		}
-+		util_elf_fw = util_fw->data;
-+#endif
-+	}
-+
-+	rc = pfe_load_elf(CLASS_MASK, class_elf_fw, pfe);
-+	if (rc < 0) {
-+		pr_err("%s: class firmware load failed\n", __func__);
-+		goto err3;
-+	}
-+
-+#if defined(CFG_DIAGS)
-+	rc = pfe_get_diags_info(class_elf_fw, &pfe->diags.class_diags_info);
-+	if (rc < 0) {
-+		pr_warn(
-+			"PFE diags won't be available for class PEs\n");
-+		rc = 0;
-+	}
-+#endif
-+
-+	rc = pfe_load_elf(TMU_MASK, tmu_elf_fw, pfe);
-+	if (rc < 0) {
-+		pr_err("%s: tmu firmware load failed\n", __func__);
-+		goto err3;
-+	}
-+
-+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
-+	rc = pfe_load_elf(UTIL_MASK, util_elf_fw, pfe);
-+	if (rc < 0) {
-+		pr_err("%s: util firmware load failed\n", __func__);
-+		goto err3;
-+	}
-+
-+#if defined(CFG_DIAGS)
-+	rc = pfe_get_diags_info(util_elf_fw, &pfe->diags.util_diags_info);
-+	if (rc < 0) {
-+		pr_warn(
-+			"PFE diags won't be available for util PE\n");
-+		rc = 0;
-+	}
-+#endif
-+
-+	util_enable();
-+#endif
-+
-+	tmu_enable(0xf);
-+	class_enable();
-+
-+err3:
-+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
-+	if (fs_load)
-+		release_firmware(util_fw);
-+err2:
-+#endif
-+	if (fs_load)
-+		release_firmware(tmu_fw);
-+
-+err1:
-+	if (fs_load)
-+		release_firmware(class_fw);
-+
-+err0:
-+	return rc;
-+}
-+
-+/* PFE firmware cleanup
-+ * Puts PE's in reset
-+ *
-+ *
-+ */
-+void pfe_firmware_exit(struct pfe *pfe)
-+{
-+	pr_info("%s\n", __func__);
-+
-+	if (pe_reset_all(&pfe->ctrl) != 0)
-+		pr_err("Error: Failed to stop PEs, PFE reload may not work correctly\n");
-+
-+	class_disable();
-+	tmu_disable(0xf);
-+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
-+	util_disable();
-+#endif
-+}
---- /dev/null
-+++ b/drivers/staging/fsl_ppfe/pfe_firmware.h
-@@ -0,0 +1,21 @@
-+/* SPDX-License-Identifier: GPL-2.0+ */
-+/*
-+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
-+ * Copyright 2017 NXP
-+ */
-+
-+#ifndef _PFE_FIRMWARE_H_
-+#define _PFE_FIRMWARE_H_
-+
-+#define CLASS_FIRMWARE_FILENAME		"ppfe_class_ls1012a.elf"
-+#define TMU_FIRMWARE_FILENAME		"ppfe_tmu_ls1012a.elf"
-+#define UTIL_FIRMWARE_FILENAME		"ppfe_util_ls1012a.elf"
-+
-+#define PFE_FW_CHECK_PASS		0
-+#define PFE_FW_CHECK_FAIL		1
-+#define NUM_PFE_FW				3
-+
-+int pfe_firmware_init(struct pfe *pfe);
-+void pfe_firmware_exit(struct pfe *pfe);
-+
-+#endif /* _PFE_FIRMWARE_H_ */
---- /dev/null
-+++ b/drivers/staging/fsl_ppfe/pfe_hal.c
-@@ -0,0 +1,1516 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+/*
-+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
-+ * Copyright 2017 NXP
-+ */
-+
-+#include "pfe_mod.h"
-+#include "pfe/pfe.h"
-+
-+/* A-010897: Jumbo frame is not supported */
-+extern bool pfe_errata_a010897;
-+
-+#define PFE_RCR_MAX_FL_MASK	0xC000FFFF
-+
-+void *cbus_base_addr;
-+void *ddr_base_addr;
-+unsigned long ddr_phys_base_addr;
-+unsigned int ddr_size;
-+
-+static struct pe_info pe[MAX_PE];
-+
-+/* Initializes the PFE library.
-+ * Must be called before using any of the library functions.
-+ *
-+ * @param[in] cbus_base		CBUS virtual base address (as mapped in
-+ * the host CPU address space)
-+ * @param[in] ddr_base		PFE DDR range virtual base address (as
-+ * mapped in the host CPU address space)
-+ * @param[in] ddr_phys_base	PFE DDR range physical base address (as
-+ * mapped in platform)
-+ * @param[in] size		PFE DDR range size (as defined by the host
-+ * software)
-+ */
-+void pfe_lib_init(void *cbus_base, void *ddr_base, unsigned long ddr_phys_base,
-+		  unsigned int size)
-+{
-+	cbus_base_addr = cbus_base;
-+	ddr_base_addr = ddr_base;
-+	ddr_phys_base_addr = ddr_phys_base;
-+	ddr_size = size;
-+
-+	pe[CLASS0_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(0);
-+	pe[CLASS0_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(0);
-+	pe[CLASS0_ID].pmem_size = CLASS_IMEM_SIZE;
-+	pe[CLASS0_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA;
-+	pe[CLASS0_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR;
-+	pe[CLASS0_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA;
-+
-+	pe[CLASS1_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(1);
-+	pe[CLASS1_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(1);
-+	pe[CLASS1_ID].pmem_size = CLASS_IMEM_SIZE;
-+	pe[CLASS1_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA;
-+	pe[CLASS1_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR;
-+	pe[CLASS1_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA;
-+
-+	pe[CLASS2_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(2);
-+	pe[CLASS2_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(2);
-+	pe[CLASS2_ID].pmem_size = CLASS_IMEM_SIZE;
-+	pe[CLASS2_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA;
-+	pe[CLASS2_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR;
-+	pe[CLASS2_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA;
-+
-+	pe[CLASS3_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(3);
-+	pe[CLASS3_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(3);
-+	pe[CLASS3_ID].pmem_size = CLASS_IMEM_SIZE;
-+	pe[CLASS3_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA;
-+	pe[CLASS3_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR;
-+	pe[CLASS3_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA;
-+
-+	pe[CLASS4_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(4);
-+	pe[CLASS4_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(4);
-+	pe[CLASS4_ID].pmem_size = CLASS_IMEM_SIZE;
-+	pe[CLASS4_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA;
-+	pe[CLASS4_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR;
-+	pe[CLASS4_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA;
-+
-+	pe[CLASS5_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(5);
-+	pe[CLASS5_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(5);
-+	pe[CLASS5_ID].pmem_size = CLASS_IMEM_SIZE;
-+	pe[CLASS5_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA;
-+	pe[CLASS5_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR;
-+	pe[CLASS5_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA;
-+
-+	pe[TMU0_ID].dmem_base_addr = TMU_DMEM_BASE_ADDR(0);
-+	pe[TMU0_ID].pmem_base_addr = TMU_IMEM_BASE_ADDR(0);
-+	pe[TMU0_ID].pmem_size = TMU_IMEM_SIZE;
-+	pe[TMU0_ID].mem_access_wdata = TMU_MEM_ACCESS_WDATA;
-+	pe[TMU0_ID].mem_access_addr = TMU_MEM_ACCESS_ADDR;
-+	pe[TMU0_ID].mem_access_rdata = TMU_MEM_ACCESS_RDATA;
-+
-+	pe[TMU1_ID].dmem_base_addr = TMU_DMEM_BASE_ADDR(1);
-+	pe[TMU1_ID].pmem_base_addr = TMU_IMEM_BASE_ADDR(1);
-+	pe[TMU1_ID].pmem_size = TMU_IMEM_SIZE;
-+	pe[TMU1_ID].mem_access_wdata = TMU_MEM_ACCESS_WDATA;
-+	pe[TMU1_ID].mem_access_addr = TMU_MEM_ACCESS_ADDR;
-+	pe[TMU1_ID].mem_access_rdata = TMU_MEM_ACCESS_RDATA;
-+
-+	pe[TMU3_ID].dmem_base_addr = TMU_DMEM_BASE_ADDR(3);
-+	pe[TMU3_ID].pmem_base_addr = TMU_IMEM_BASE_ADDR(3);
-+	pe[TMU3_ID].pmem_size = TMU_IMEM_SIZE;
-+	pe[TMU3_ID].mem_access_wdata = TMU_MEM_ACCESS_WDATA;
-+	pe[TMU3_ID].mem_access_addr = TMU_MEM_ACCESS_ADDR;
-+	pe[TMU3_ID].mem_access_rdata = TMU_MEM_ACCESS_RDATA;
-+
-+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
-+	pe[UTIL_ID].dmem_base_addr = UTIL_DMEM_BASE_ADDR;
-+	pe[UTIL_ID].mem_access_wdata = UTIL_MEM_ACCESS_WDATA;
-+	pe[UTIL_ID].mem_access_addr = UTIL_MEM_ACCESS_ADDR;
-+	pe[UTIL_ID].mem_access_rdata = UTIL_MEM_ACCESS_RDATA;
-+#endif
-+}
-+
-+/* Writes a buffer to PE internal memory from the host
-+ * through indirect access registers.
-+ *
-+ * @param[in] id		PE identification (CLASS0_ID, ..., TMU0_ID,
-+ * ..., UTIL_ID)
-+ * @param[in] src		Buffer source address
-+ * @param[in] mem_access_addr	DMEM destination address (must be 32bit
-+ * aligned)
-+ * @param[in] len		Number of bytes to copy
-+ */
-+void pe_mem_memcpy_to32(int id, u32 mem_access_addr, const void *src, unsigned
-+int len)
-+{
-+	u32 offset = 0, val, addr;
-+	unsigned int len32 = len >> 2;
-+	int i;
-+
-+	addr = mem_access_addr | PE_MEM_ACCESS_WRITE |
-+		PE_MEM_ACCESS_BYTE_ENABLE(0, 4);
-+
-+	for (i = 0; i < len32; i++, offset += 4, src += 4) {
-+		val = *(u32 *)src;
-+		writel(cpu_to_be32(val), pe[id].mem_access_wdata);
-+		writel(addr + offset, pe[id].mem_access_addr);
-+	}
-+
-+	len = (len & 0x3);
-+	if (len) {
-+		val = 0;
-+
-+		addr = (mem_access_addr | PE_MEM_ACCESS_WRITE |
-+			PE_MEM_ACCESS_BYTE_ENABLE(0, len)) + offset;
-+
-+		for (i = 0; i < len; i++, src++)
-+			val |= (*(u8 *)src) << (8 * i);
-+
-+		writel(cpu_to_be32(val), pe[id].mem_access_wdata);
-+		writel(addr, pe[id].mem_access_addr);
-+	}
-+}
-+
-+/* Writes a buffer to PE internal data memory (DMEM) from the host
-+ * through indirect access registers.
-+ * @param[in] id		PE identification (CLASS0_ID, ..., TMU0_ID,
-+ * ..., UTIL_ID)
-+ * @param[in] src		Buffer source address
-+ * @param[in] dst		DMEM destination address (must be 32bit
-+ * aligned)
-+ * @param[in] len		Number of bytes to copy
-+ */
-+void pe_dmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len)
-+{
-+	pe_mem_memcpy_to32(id, pe[id].dmem_base_addr | dst |
-+				PE_MEM_ACCESS_DMEM, src, len);
-+}
-+
-+/* Writes a buffer to PE internal program memory (PMEM) from the host
-+ * through indirect access registers.
-+ * @param[in] id		PE identification (CLASS0_ID, ..., TMU0_ID,
-+ * ..., TMU3_ID)
-+ * @param[in] src		Buffer source address
-+ * @param[in] dst		PMEM destination address (must be 32bit
-+ * aligned)
-+ * @param[in] len		Number of bytes to copy
-+ */
-+void pe_pmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len)
-+{
-+	pe_mem_memcpy_to32(id, pe[id].pmem_base_addr | (dst & (pe[id].pmem_size
-+				- 1)) | PE_MEM_ACCESS_IMEM, src, len);
-+}
-+
-+/* Reads PE internal program memory (IMEM) from the host
-+ * through indirect access registers.
-+ * @param[in] id		PE identification (CLASS0_ID, ..., TMU0_ID,
-+ * ..., TMU3_ID)
-+ * @param[in] addr		PMEM read address (must be aligned on size)
-+ * @param[in] size		Number of bytes to read (maximum 4, must not
-+ * cross 32bit boundaries)
-+ * @return			the data read (in PE endianness, i.e BE).
-+ */
-+u32 pe_pmem_read(int id, u32 addr, u8 size)
-+{
-+	u32 offset = addr & 0x3;
-+	u32 mask = 0xffffffff >> ((4 - size) << 3);
-+	u32 val;
-+
-+	addr = pe[id].pmem_base_addr | ((addr & ~0x3) & (pe[id].pmem_size - 1))
-+		| PE_MEM_ACCESS_IMEM | PE_MEM_ACCESS_BYTE_ENABLE(offset, size);
-+
-+	writel(addr, pe[id].mem_access_addr);
-+	val = be32_to_cpu(readl(pe[id].mem_access_rdata));
-+
-+	return (val >> (offset << 3)) & mask;
-+}
-+
-+/* Writes PE internal data memory (DMEM) from the host
-+ * through indirect access registers.
-+ * @param[in] id		PE identification (CLASS0_ID, ..., TMU0_ID,
-+ * ..., UTIL_ID)
-+ * @param[in] addr		DMEM write address (must be aligned on size)
-+ * @param[in] val		Value to write (in PE endianness, i.e BE)
-+ * @param[in] size		Number of bytes to write (maximum 4, must not
-+ * cross 32bit boundaries)
-+ */
-+void pe_dmem_write(int id, u32 val, u32 addr, u8 size)
-+{
-+	u32 offset = addr & 0x3;
-+
-+	addr = pe[id].dmem_base_addr | (addr & ~0x3) | PE_MEM_ACCESS_WRITE |
-+		PE_MEM_ACCESS_DMEM | PE_MEM_ACCESS_BYTE_ENABLE(offset, size);
-+
-+	/* Indirect access interface is byte swapping data being written */
-+	writel(cpu_to_be32(val << (offset << 3)), pe[id].mem_access_wdata);
-+	writel(addr, pe[id].mem_access_addr);
-+}
-+
-+/* Reads PE internal data memory (DMEM) from the host
-+ * through indirect access registers.
-+ * @param[in] id		PE identification (CLASS0_ID, ..., TMU0_ID,
-+ * ..., UTIL_ID)
-+ * @param[in] addr		DMEM read address (must be aligned on size)
-+ * @param[in] size		Number of bytes to read (maximum 4, must not
-+ * cross 32bit boundaries)
-+ * @return			the data read (in PE endianness, i.e BE).
-+ */
-+u32 pe_dmem_read(int id, u32 addr, u8 size)
-+{
-+	u32 offset = addr & 0x3;
-+	u32 mask = 0xffffffff >> ((4 - size) << 3);
-+	u32 val;
-+
-+	addr = pe[id].dmem_base_addr | (addr & ~0x3) | PE_MEM_ACCESS_DMEM |
-+			PE_MEM_ACCESS_BYTE_ENABLE(offset, size);
-+
-+	writel(addr, pe[id].mem_access_addr);
-+
-+	/* Indirect access interface is byte swapping data being read */
-+	val = be32_to_cpu(readl(pe[id].mem_access_rdata));
-+
-+	return (val >> (offset << 3)) & mask;
-+}
-+
-+/* This function is used to write to CLASS internal bus peripherals (ccu,
-+ * pe-lem) from the host
-+ * through indirect access registers.
-+ * @param[in]	val	value to write
-+ * @param[in]	addr	Address to write to (must be aligned on size)
-+ * @param[in]	size	Number of bytes to write (1, 2 or 4)
-+ *
-+ */
-+void class_bus_write(u32 val, u32 addr, u8 size)
-+{
-+	u32 offset = addr & 0x3;
-+
-+	writel((addr & CLASS_BUS_ACCESS_BASE_MASK), CLASS_BUS_ACCESS_BASE);
-+
-+	addr = (addr & ~CLASS_BUS_ACCESS_BASE_MASK) | PE_MEM_ACCESS_WRITE |
-+			(size << 24);
-+
-+	writel(cpu_to_be32(val << (offset << 3)), CLASS_BUS_ACCESS_WDATA);
-+	writel(addr, CLASS_BUS_ACCESS_ADDR);
-+}
-+
-+/* Reads from CLASS internal bus peripherals (ccu, pe-lem) from the host
-+ * through indirect access registers.
-+ * @param[in] addr	Address to read from (must be aligned on size)
-+ * @param[in] size	Number of bytes to read (1, 2 or 4)
-+ * @return		the read data
-+ *
-+ */
-+u32 class_bus_read(u32 addr, u8 size)
-+{
-+	u32 offset = addr & 0x3;
-+	u32 mask = 0xffffffff >> ((4 - size) << 3);
-+	u32 val;
-+
-+	writel((addr & CLASS_BUS_ACCESS_BASE_MASK), CLASS_BUS_ACCESS_BASE);
-+
-+	addr = (addr & ~CLASS_BUS_ACCESS_BASE_MASK) | (size << 24);
-+
-+	writel(addr, CLASS_BUS_ACCESS_ADDR);
-+	val = be32_to_cpu(readl(CLASS_BUS_ACCESS_RDATA));
-+
-+	return (val >> (offset << 3)) & mask;
-+}
-+
-+/* Writes data to the cluster memory (PE_LMEM)
-+ * @param[in] dst	PE LMEM destination address (must be 32bit aligned)
-+ * @param[in] src	Buffer source address
-+ * @param[in] len	Number of bytes to copy
-+ */
-+void class_pe_lmem_memcpy_to32(u32 dst, const void *src, unsigned int len)
-+{
-+	u32 len32 = len >> 2;
-+	int i;
-+
-+	for (i = 0; i < len32; i++, src += 4, dst += 4)
-+		class_bus_write(*(u32 *)src, dst, 4);
-+
-+	if (len & 0x2) {
-+		class_bus_write(*(u16 *)src, dst, 2);
-+		src += 2;
-+		dst += 2;
-+	}
-+
-+	if (len & 0x1) {
-+		class_bus_write(*(u8 *)src, dst, 1);
-+		src++;
-+		dst++;
-+	}
-+}
-+
-+/* Writes value to the cluster memory (PE_LMEM)
-+ * @param[in] dst	PE LMEM destination address (must be 32bit aligned)
-+ * @param[in] val	Value to write
-+ * @param[in] len	Number of bytes to write
-+ */
-+void class_pe_lmem_memset(u32 dst, int val, unsigned int len)
-+{
-+	u32 len32 = len >> 2;
-+	int i;
-+
-+	val = val | (val << 8) | (val << 16) | (val << 24);
-+
-+	for (i = 0; i < len32; i++, dst += 4)
-+		class_bus_write(val, dst, 4);
-+
-+	if (len & 0x2) {
-+		class_bus_write(val, dst, 2);
-+		dst += 2;
-+	}
-+
-+	if (len & 0x1) {
-+		class_bus_write(val, dst, 1);
-+		dst++;
-+	}
-+}
-+
-+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
-+
-+/* Writes UTIL program memory (DDR) from the host.
-+ *
-+ * @param[in] addr	Address to write (virtual, must be aligned on size)
-+ * @param[in] val		Value to write (in PE endianness, i.e BE)
-+ * @param[in] size		Number of bytes to write (2 or 4)
-+ */
-+static void util_pmem_write(u32 val, void *addr, u8 size)
-+{
-+	void *addr64 = (void *)((unsigned long)addr & ~0x7);
-+	unsigned long off = 8 - ((unsigned long)addr & 0x7) - size;
-+
-+	/*
-+	 * IMEM should  be loaded as a 64bit swapped value in a 64bit aligned
-+	 * location
-+	 */
-+	if (size == 4)
-+		writel(be32_to_cpu(val), addr64 + off);
-+	else
-+		writew(be16_to_cpu((u16)val), addr64 + off);
-+}
-+
-+/* Writes a buffer to UTIL program memory (DDR) from the host.
-+ *
-+ * @param[in] dst	Address to write (virtual, must be at least 16bit
-+ * aligned)
-+ * @param[in] src	Buffer to write (in PE endianness, i.e BE, must have
-+ * same alignment as dst)
-+ * @param[in] len	Number of bytes to write (must be at least 16bit
-+ * aligned)
-+ */
-+static void util_pmem_memcpy(void *dst, const void *src, unsigned int len)
-+{
-+	unsigned int len32;
-+	int i;
-+
-+	if ((unsigned long)src & 0x2) {
-+		util_pmem_write(*(u16 *)src, dst, 2);
-+		src += 2;
-+		dst += 2;
-+		len -= 2;
-+	}
-+
-+	len32 = len >> 2;
-+
-+	for (i = 0; i < len32; i++, dst += 4, src += 4)
-+		util_pmem_write(*(u32 *)src, dst, 4);
-+
-+	if (len & 0x2)
-+		util_pmem_write(*(u16 *)src, dst, len & 0x2);
-+}
-+#endif
-+
-+/* Loads an elf section into pmem
-+ * Code needs to be at least 16bit aligned and only PROGBITS sections are
-+ * supported
-+ *
-+ * @param[in] id	PE identification (CLASS0_ID, ..., TMU0_ID, ...,
-+ * TMU3_ID)
-+ * @param[in] data	pointer to the elf firmware
-+ * @param[in] shdr	pointer to the elf section header
-+ *
-+ */
-+static int pe_load_pmem_section(int id, const void *data,
-+				struct elf32_shdr *shdr)
-+{
-+	u32 offset = be32_to_cpu(shdr->sh_offset);
-+	u32 addr = be32_to_cpu(shdr->sh_addr);
-+	u32 size = be32_to_cpu(shdr->sh_size);
-+	u32 type = be32_to_cpu(shdr->sh_type);
-+
-+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
-+	if (id == UTIL_ID) {
-+		pr_err("%s: unsupported pmem section for UTIL\n",
-+		       __func__);
-+		return -EINVAL;
-+	}
-+#endif
-+
-+	if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3)) {
-+		pr_err(
-+			"%s: load address(%x) and elf file address(%lx) don't have the same alignment\n"
-+			, __func__, addr, (unsigned long)data + offset);
-+
-+		return -EINVAL;
-+	}
-+
-+	if (addr & 0x1) {
-+		pr_err("%s: load address(%x) is not 16bit aligned\n",
-+		       __func__, addr);
-+		return -EINVAL;
-+	}
-+
-+	if (size & 0x1) {
-+		pr_err("%s: load size(%x) is not 16bit aligned\n",
-+		       __func__, size);
-+		return -EINVAL;
-+	}
-+
-+	switch (type) {
-+	case SHT_PROGBITS:
-+		pe_pmem_memcpy_to32(id, addr, data + offset, size);
-+
-+		break;
-+
-+	default:
-+		pr_err("%s: unsupported section type(%x)\n", __func__,
-+		       type);
-+		return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+
-+/* Loads an elf section into dmem
-+ * Data needs to be at least 32bit aligned, NOBITS sections are correctly
-+ * initialized to 0
-+ *
-+ * @param[in] id		PE identification (CLASS0_ID, ..., TMU0_ID,
-+ * ..., UTIL_ID)
-+ * @param[in] data		pointer to the elf firmware
-+ * @param[in] shdr		pointer to the elf section header
-+ *
-+ */
-+static int pe_load_dmem_section(int id, const void *data,
-+				struct elf32_shdr *shdr)
-+{
-+	u32 offset = be32_to_cpu(shdr->sh_offset);
-+	u32 addr = be32_to_cpu(shdr->sh_addr);
-+	u32 size = be32_to_cpu(shdr->sh_size);
-+	u32 type = be32_to_cpu(shdr->sh_type);
-+	u32 size32 = size >> 2;
-+	int i;
-+
-+	if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3)) {
-+		pr_err(
-+			"%s: load address(%x) and elf file address(%lx) don't have the same alignment\n",
-+			__func__, addr, (unsigned long)data + offset);
-+
-+		return -EINVAL;
-+	}
-+
-+	if (addr & 0x3) {
-+		pr_err("%s: load address(%x) is not 32bit aligned\n",
-+		       __func__, addr);
-+		return -EINVAL;
-+	}
-+
-+	switch (type) {
-+	case SHT_PROGBITS:
-+		pe_dmem_memcpy_to32(id, addr, data + offset, size);
-+		break;
-+
-+	case SHT_NOBITS:
-+		for (i = 0; i < size32; i++, addr += 4)
-+			pe_dmem_write(id, 0, addr, 4);
-+
-+		if (size & 0x3)
-+			pe_dmem_write(id, 0, addr, size & 0x3);
-+
-+		break;
-+
-+	default:
-+		pr_err("%s: unsupported section type(%x)\n", __func__,
-+		       type);
-+		return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+
-+/* Loads an elf section into DDR
-+ * Data needs to be at least 32bit aligned, NOBITS sections are correctly
-+ * initialized to 0
-+ *
-+ * @param[in] id		PE identification (CLASS0_ID, ..., TMU0_ID,
-+ * ..., UTIL_ID)
-+ * @param[in] data		pointer to the elf firmware
-+ * @param[in] shdr		pointer to the elf section header
-+ *
-+ */
-+static int pe_load_ddr_section(int id, const void *data,
-+			       struct elf32_shdr *shdr,
-+			       struct device *dev) {
-+	u32 offset = be32_to_cpu(shdr->sh_offset);
-+	u32 addr = be32_to_cpu(shdr->sh_addr);
-+	u32 size = be32_to_cpu(shdr->sh_size);
-+	u32 type = be32_to_cpu(shdr->sh_type);
-+	u32 flags = be32_to_cpu(shdr->sh_flags);
-+
-+	switch (type) {
-+	case SHT_PROGBITS:
-+		if (flags & SHF_EXECINSTR) {
-+			if (id <= CLASS_MAX_ID) {
-+				/* DO the loading only once in DDR */
-+				if (id == CLASS0_ID) {
-+					pr_err(
-+						"%s: load address(%x) and elf file address(%lx) rcvd\n",
-+						__func__, addr,
-+						(unsigned long)data + offset);
-+					if (((unsigned long)(data + offset)
-+						& 0x3) != (addr & 0x3)) {
-+						pr_err(
-+							"%s: load address(%x) and elf file address(%lx) don't have the same alignment\n"
-+							, __func__, addr,
-+						(unsigned long)data + offset);
-+
-+						return -EINVAL;
-+					}
-+
-+					if (addr & 0x1) {
-+						pr_err(
-+							"%s: load address(%x) is not 16bit aligned\n"
-+							, __func__, addr);
-+						return -EINVAL;
-+					}
-+
-+					if (size & 0x1) {
-+						pr_err(
-+							"%s: load length(%x) is not 16bit aligned\n"
-+							, __func__, size);
-+						return -EINVAL;
-+					}
-+					memcpy(DDR_PHYS_TO_VIRT(
-+						DDR_PFE_TO_PHYS(addr)),
-+						data + offset, size);
-+				}
-+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
-+			} else if (id == UTIL_ID) {
-+				if (((unsigned long)(data + offset) & 0x3)
-+					!= (addr & 0x3)) {
-+					pr_err(
-+						"%s: load address(%x) and elf file address(%lx) don't have the same alignment\n"
-+						, __func__, addr,
-+						(unsigned long)data + offset);
-+
-+					return -EINVAL;
-+				}
-+
-+				if (addr & 0x1) {
-+					pr_err(
-+						"%s: load address(%x) is not 16bit aligned\n"
-+						, __func__, addr);
-+					return -EINVAL;
-+				}
-+
-+				if (size & 0x1) {
-+					pr_err(
-+						"%s: load length(%x) is not 16bit aligned\n"
-+						, __func__, size);
-+					return -EINVAL;
-+				}
-+
-+				util_pmem_memcpy(DDR_PHYS_TO_VIRT(
-+							DDR_PFE_TO_PHYS(addr)),
-+							data + offset, size);
-+#endif
-+			} else {
-+				pr_err(
-+					"%s: unsupported ddr section type(%x) for PE(%d)\n"
-+						, __func__, type, id);
-+				return -EINVAL;
-+			}
-+
-+		} else {
-+			memcpy(DDR_PHYS_TO_VIRT(DDR_PFE_TO_PHYS(addr)), data
-+				+ offset, size);
-+		}
-+
-+		break;
-+
-+	case SHT_NOBITS:
-+		memset(DDR_PHYS_TO_VIRT(DDR_PFE_TO_PHYS(addr)), 0, size);
-+
-+		break;
-+
-+	default:
-+		pr_err("%s: unsupported section type(%x)\n", __func__,
-+		       type);
-+		return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+
-+/* Loads an elf section into pe lmem
-+ * Data needs to be at least 32bit aligned, NOBITS sections are correctly
-+ * initialized to 0
-+ *
-+ * @param[in] id		PE identification (CLASS0_ID,..., CLASS5_ID)
-+ * @param[in] data		pointer to the elf firmware
-+ * @param[in] shdr		pointer to the elf section header
-+ *
-+ */
-+static int pe_load_pe_lmem_section(int id, const void *data,
-+				   struct elf32_shdr *shdr)
-+{
-+	u32 offset = be32_to_cpu(shdr->sh_offset);
-+	u32 addr = be32_to_cpu(shdr->sh_addr);
-+	u32 size = be32_to_cpu(shdr->sh_size);
-+	u32 type = be32_to_cpu(shdr->sh_type);
-+
-+	if (id > CLASS_MAX_ID) {
-+		pr_err(
-+			"%s: unsupported pe-lmem section type(%x) for PE(%d)\n",
-+			 __func__, type, id);
-+		return -EINVAL;
-+	}
-+
-+	if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3)) {
-+		pr_err(
-+			"%s: load address(%x) and elf file address(%lx) don't have the same alignment\n",
-+			__func__, addr, (unsigned long)data + offset);
-+
-+		return -EINVAL;
-+	}
-+
-+	if (addr & 0x3) {
-+		pr_err("%s: load address(%x) is not 32bit aligned\n",
-+		       __func__, addr);
-+		return -EINVAL;
-+	}
-+
-+	switch (type) {
-+	case SHT_PROGBITS:
-+		class_pe_lmem_memcpy_to32(addr, data + offset, size);
-+		break;
-+
-+	case SHT_NOBITS:
-+		class_pe_lmem_memset(addr, 0, size);
-+		break;
-+
-+	default:
-+		pr_err("%s: unsupported section type(%x)\n", __func__,
-+		       type);
-+		return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+
-+/* Loads an elf section into a PE
-+ * For now only supports loading a section to dmem (all PE's), pmem (class and
-+ * tmu PE's),
-+ * DDDR (util PE code)
-+ *
-+ * @param[in] id		PE identification (CLASS0_ID, ..., TMU0_ID,
-+ * ..., UTIL_ID)
-+ * @param[in] data		pointer to the elf firmware
-+ * @param[in] shdr		pointer to the elf section header
-+ *
-+ */
-+int pe_load_elf_section(int id, const void *data, struct elf32_shdr *shdr,
-+			struct device *dev) {
-+	u32 addr = be32_to_cpu(shdr->sh_addr);
-+	u32 size = be32_to_cpu(shdr->sh_size);
-+
-+	if (IS_DMEM(addr, size))
-+		return pe_load_dmem_section(id, data, shdr);
-+	else if (IS_PMEM(addr, size))
-+		return pe_load_pmem_section(id, data, shdr);
-+	else if (IS_PFE_LMEM(addr, size))
-+		return 0;
-+	else if (IS_PHYS_DDR(addr, size))
-+		return pe_load_ddr_section(id, data, shdr, dev);
-+	else if (IS_PE_LMEM(addr, size))
-+		return pe_load_pe_lmem_section(id, data, shdr);
-+
-+	pr_err("%s: unsupported memory range(%x)\n", __func__,
-+	       addr);
-+	return 0;
-+}
-+
-+/**************************** BMU ***************************/
-+
-+/* Initializes a BMU block.
-+ * @param[in] base	BMU block base address
-+ * @param[in] cfg	BMU configuration
-+ */
-+void bmu_init(void *base, struct BMU_CFG *cfg)
-+{
-+	bmu_disable(base);
-+
-+	bmu_set_config(base, cfg);
-+
-+	bmu_reset(base);
-+}
-+
-+/* Resets a BMU block.
-+ * @param[in] base	BMU block base address
-+ */
-+void bmu_reset(void *base)
-+{
-+	writel(CORE_SW_RESET, base + BMU_CTRL);
-+
-+	/* Wait for self clear */
-+	while (readl(base + BMU_CTRL) & CORE_SW_RESET)
-+		;
-+}
-+
-+/* Enabled a BMU block.
-+ * @param[in] base	BMU block base address
-+ */
-+void bmu_enable(void *base)
-+{
-+	writel(CORE_ENABLE, base + BMU_CTRL);
-+}
-+
-+/* Disables a BMU block.
-+ * @param[in] base	BMU block base address
-+ */
-+void bmu_disable(void *base)
-+{
-+	writel(CORE_DISABLE, base + BMU_CTRL);
-+}
-+
-+/* Sets the configuration of a BMU block.
-+ * @param[in] base	BMU block base address
-+ * @param[in] cfg	BMU configuration
-+ */
-+void bmu_set_config(void *base, struct BMU_CFG *cfg)
-+{
-+	writel(cfg->baseaddr, base + BMU_UCAST_BASE_ADDR);
-+	writel(cfg->count & 0xffff, base + BMU_UCAST_CONFIG);
-+	writel(cfg->size & 0xffff, base + BMU_BUF_SIZE);
-+
-+	/* Interrupts are never used */
-+	writel(cfg->low_watermark, base + BMU_LOW_WATERMARK);
-+	writel(cfg->high_watermark, base + BMU_HIGH_WATERMARK);
-+	writel(0x0, base + BMU_INT_ENABLE);
-+}
-+
-+/**************************** MTIP GEMAC ***************************/
-+
-+/* Enable Rx Checksum Engine. With this enabled, Frame with bad IP,
-+ *   TCP or UDP checksums are discarded
-+ *
-+ * @param[in] base	GEMAC base address.
-+ */
-+void gemac_enable_rx_checksum_offload(void *base)
-+{
-+	/*Do not find configuration to do this */
-+}
-+
-+/* Disable Rx Checksum Engine.
-+ *
-+ * @param[in] base	GEMAC base address.
-+ */
-+void gemac_disable_rx_checksum_offload(void *base)
-+{
-+	/*Do not find configuration to do this */
-+}
-+
-+/* GEMAC set speed.
-+ * @param[in] base	GEMAC base address
-+ * @param[in] speed	GEMAC speed (10, 100 or 1000 Mbps)
-+ */
-+void gemac_set_speed(void *base, enum mac_speed gem_speed)
-+{
-+	u32 ecr = readl(base + EMAC_ECNTRL_REG) & ~EMAC_ECNTRL_SPEED;
-+	u32 rcr = readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_RMII_10T;
-+
-+	switch (gem_speed) {
-+	case SPEED_10M:
-+			rcr |= EMAC_RCNTRL_RMII_10T;
-+			break;
-+
-+	case SPEED_1000M:
-+			ecr |= EMAC_ECNTRL_SPEED;
-+			break;
-+
-+	case SPEED_100M:
-+	default:
-+			/*It is in 100M mode */
-+			break;
-+	}
-+	writel(ecr, (base + EMAC_ECNTRL_REG));
-+	writel(rcr, (base + EMAC_RCNTRL_REG));
-+}
-+
-+/* GEMAC set duplex.
-+ * @param[in] base	GEMAC base address
-+ * @param[in] duplex	GEMAC duplex mode (Full, Half)
-+ */
-+void gemac_set_duplex(void *base, int duplex)
-+{
-+	if (duplex == DUPLEX_HALF) {
-+		writel(readl(base + EMAC_TCNTRL_REG) & ~EMAC_TCNTRL_FDEN, base
-+			+ EMAC_TCNTRL_REG);
-+		writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_DRT, (base
-+			+ EMAC_RCNTRL_REG));
-+	} else{
-+		writel(readl(base + EMAC_TCNTRL_REG) | EMAC_TCNTRL_FDEN, base
-+			+ EMAC_TCNTRL_REG);
-+		writel(readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_DRT, (base
-+			+ EMAC_RCNTRL_REG));
-+	}
-+}
-+
-+/* GEMAC set mode.
-+ * @param[in] base	GEMAC base address
-+ * @param[in] mode	GEMAC operation mode (MII, RMII, RGMII, SGMII)
-+ */
-+void gemac_set_mode(void *base, int mode)
-+{
-+	u32 val = readl(base + EMAC_RCNTRL_REG);
-+
-+	/*Remove loopbank*/
-+	val &= ~EMAC_RCNTRL_LOOP;
-+
-+	/* Enable flow control and MII mode.PFE firmware always expects
-+       CRC should be forwarded by MAC to validate CRC in software.*/
-+	val |= (EMAC_RCNTRL_FCE | EMAC_RCNTRL_MII_MODE);
-+
-+	writel(val, base + EMAC_RCNTRL_REG);
-+}
-+
-+/* GEMAC enable function.
-+ * @param[in] base	GEMAC base address
-+ */
-+void gemac_enable(void *base)
-+{
-+	writel(readl(base + EMAC_ECNTRL_REG) | EMAC_ECNTRL_ETHER_EN, base +
-+		EMAC_ECNTRL_REG);
-+}
-+
-+/* GEMAC disable function.
-+ * @param[in] base	GEMAC base address
-+ */
-+void gemac_disable(void *base)
-+{
-+	writel(readl(base + EMAC_ECNTRL_REG) & ~EMAC_ECNTRL_ETHER_EN, base +
-+		EMAC_ECNTRL_REG);
-+}
-+
-+/* GEMAC TX disable function.
-+ * @param[in] base	GEMAC base address
-+ */
-+void gemac_tx_disable(void *base)
-+{
-+	writel(readl(base + EMAC_TCNTRL_REG) | EMAC_TCNTRL_GTS, base +
-+		EMAC_TCNTRL_REG);
-+}
-+
-+void gemac_tx_enable(void *base)
-+{
-+	writel(readl(base + EMAC_TCNTRL_REG) & ~EMAC_TCNTRL_GTS, base +
-+			EMAC_TCNTRL_REG);
-+}
-+
-+/* Sets the hash register of the MAC.
-+ * This register is used for matching unicast and multicast frames.
-+ *
-+ * @param[in] base	GEMAC base address.
-+ * @param[in] hash	64-bit hash to be configured.
-+ */
-+void gemac_set_hash(void *base, struct pfe_mac_addr *hash)
-+{
-+	writel(hash->bottom,  base + EMAC_GALR);
-+	writel(hash->top, base + EMAC_GAUR);
-+}
-+
-+void gemac_set_laddrN(void *base, struct pfe_mac_addr *address,
-+		      unsigned int entry_index)
-+{
-+	if ((entry_index < 1) || (entry_index > EMAC_SPEC_ADDR_MAX))
-+		return;
-+
-+	entry_index = entry_index - 1;
-+	if (entry_index < 1) {
-+		writel(htonl(address->bottom),  base + EMAC_PHY_ADDR_LOW);
-+		writel((htonl(address->top) | 0x8808), base +
-+			EMAC_PHY_ADDR_HIGH);
-+	} else {
-+		writel(htonl(address->bottom),  base + ((entry_index - 1) * 8)
-+			+ EMAC_SMAC_0_0);
-+		writel((htonl(address->top) | 0x8808), base + ((entry_index -
-+			1) * 8) + EMAC_SMAC_0_1);
-+	}
-+}
-+
-+void gemac_clear_laddrN(void *base, unsigned int entry_index)
-+{
-+	if ((entry_index < 1) || (entry_index > EMAC_SPEC_ADDR_MAX))
-+		return;
-+
-+	entry_index = entry_index - 1;
-+	if (entry_index < 1) {
-+		writel(0, base + EMAC_PHY_ADDR_LOW);
-+		writel(0, base + EMAC_PHY_ADDR_HIGH);
-+	} else {
-+		writel(0,  base + ((entry_index - 1) * 8) + EMAC_SMAC_0_0);
-+		writel(0, base + ((entry_index - 1) * 8) + EMAC_SMAC_0_1);
-+	}
-+}
-+
-+/* Set the loopback mode of the MAC.  This can be either no loopback for
-+ * normal operation, local loopback through MAC internal loopback module or PHY
-+ *   loopback for external loopback through a PHY.  This asserts the external
-+ * loop pin.
-+ *
-+ * @param[in] base	GEMAC base address.
-+ * @param[in] gem_loop	Loopback mode to be enabled. LB_LOCAL - MAC
-+ * Loopback,
-+ *			LB_EXT - PHY Loopback.
-+ */
-+void gemac_set_loop(void *base, enum mac_loop gem_loop)
-+{
-+	pr_info("%s()\n", __func__);
-+	writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_LOOP, (base +
-+		EMAC_RCNTRL_REG));
-+}
-+
-+/* GEMAC allow frames
-+ * @param[in] base	GEMAC base address
-+ */
-+void gemac_enable_copy_all(void *base)
-+{
-+	writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_PROM, (base +
-+		EMAC_RCNTRL_REG));
-+}
-+
-+/* GEMAC do not allow frames
-+ * @param[in] base	GEMAC base address
-+ */
-+void gemac_disable_copy_all(void *base)
-+{
-+	writel(readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_PROM, (base +
-+		EMAC_RCNTRL_REG));
-+}
-+
-+/* GEMAC allow broadcast function.
-+ * @param[in] base	GEMAC base address
-+ */
-+void gemac_allow_broadcast(void *base)
-+{
-+	writel(readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_BC_REJ, base +
-+		EMAC_RCNTRL_REG);
-+}
-+
-+/* GEMAC no broadcast function.
-+ * @param[in] base	GEMAC base address
-+ */
-+void gemac_no_broadcast(void *base)
-+{
-+	writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_BC_REJ, base +
-+		EMAC_RCNTRL_REG);
-+}
-+
-+/* GEMAC enable 1536 rx function.
-+ * @param[in]	base	GEMAC base address
-+ */
-+void gemac_enable_1536_rx(void *base)
-+{
-+	/* Set 1536 as Maximum frame length */
-+	writel((readl(base + EMAC_RCNTRL_REG) & PFE_RCR_MAX_FL_MASK)
-+		| (1536 << 16), base +	EMAC_RCNTRL_REG);
-+}
-+
-+/* GEMAC set rx Max frame length.
-+ * @param[in]	base	GEMAC base address
-+ * @param[in]	mtu	new mtu
-+ */
-+void gemac_set_rx_max_fl(void *base, int mtu)
-+{
-+	/* Set mtu as Maximum frame length */
-+	writel((readl(base + EMAC_RCNTRL_REG) & PFE_RCR_MAX_FL_MASK)
-+		| (mtu << 16), base + EMAC_RCNTRL_REG);
-+}
-+
-+/* GEMAC enable stacked vlan function.
-+ * @param[in]	base	GEMAC base address
-+ */
-+void gemac_enable_stacked_vlan(void *base)
-+{
-+	/* MTIP doesn't support stacked vlan */
-+}
-+
-+/* GEMAC enable pause rx function.
-+ * @param[in] base	GEMAC base address
-+ */
-+void gemac_enable_pause_rx(void *base)
-+{
-+	writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_FCE,
-+	       base + EMAC_RCNTRL_REG);
-+}
-+
-+/* GEMAC disable pause rx function.
-+ * @param[in] base	GEMAC base address
-+ */
-+void gemac_disable_pause_rx(void *base)
-+{
-+	writel(readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_FCE,
-+	       base + EMAC_RCNTRL_REG);
-+}
-+
-+/* GEMAC enable pause tx function.
-+ * @param[in] base GEMAC base address
-+ */
-+void gemac_enable_pause_tx(void *base)
-+{
-+	writel(EMAC_RX_SECTION_EMPTY_V, base + EMAC_RX_SECTION_EMPTY);
-+}
-+
-+/* GEMAC disable pause tx function.
-+ * @param[in] base GEMAC base address
-+ */
-+void gemac_disable_pause_tx(void *base)
-+{
-+	writel(0x0, base + EMAC_RX_SECTION_EMPTY);
-+}
-+
-+/* GEMAC wol configuration
-+ * @param[in] base	GEMAC base address
-+ * @param[in] wol_conf	WoL register configuration
-+ */
-+void gemac_set_wol(void *base, u32 wol_conf)
-+{
-+	u32  val = readl(base + EMAC_ECNTRL_REG);
-+
-+	if (wol_conf)
-+		val |= (EMAC_ECNTRL_MAGIC_ENA | EMAC_ECNTRL_SLEEP);
-+	else
-+		val &= ~(EMAC_ECNTRL_MAGIC_ENA | EMAC_ECNTRL_SLEEP);
-+	writel(val, base + EMAC_ECNTRL_REG);
-+}
-+
-+/* Sets Gemac bus width to 64bit
-+ * @param[in] base       GEMAC base address
-+ * @param[in] width     gemac bus width to be set possible values are 32/64/128
-+ */
-+void gemac_set_bus_width(void *base, int width)
-+{
-+}
-+
-+/* Sets Gemac configuration.
-+ * @param[in] base	GEMAC base address
-+ * @param[in] cfg	GEMAC configuration
-+ */
-+void gemac_set_config(void *base, struct gemac_cfg *cfg)
-+{
-+	/*GEMAC config taken from VLSI */
-+	writel(0x00000004, base + EMAC_TFWR_STR_FWD);
-+	writel(0x00000005, base + EMAC_RX_SECTION_FULL);
-+
-+	if (pfe_errata_a010897)
-+		writel(0x0000076c, base + EMAC_TRUNC_FL);
-+	else
-+		writel(0x00003fff, base + EMAC_TRUNC_FL);
-+
-+	writel(0x00000030, base + EMAC_TX_SECTION_EMPTY);
-+	writel(0x00000000, base + EMAC_MIB_CTRL_STS_REG);
-+
-+	gemac_set_mode(base, cfg->mode);
-+
-+	gemac_set_speed(base, cfg->speed);
-+
-+	gemac_set_duplex(base, cfg->duplex);
-+}
-+
-+/**************************** GPI ***************************/
-+
-+/* Initializes a GPI block.
-+ * @param[in] base	GPI base address
-+ * @param[in] cfg	GPI configuration
-+ */
-+void gpi_init(void *base, struct gpi_cfg *cfg)
-+{
-+	gpi_reset(base);
-+
-+	gpi_disable(base);
-+
-+	gpi_set_config(base, cfg);
-+}
-+
-+/* Resets a GPI block.
-+ * @param[in] base	GPI base address
-+ */
-+void gpi_reset(void *base)
-+{
-+	writel(CORE_SW_RESET, base + GPI_CTRL);
-+}
-+
-+/* Enables a GPI block.
-+ * @param[in] base	GPI base address
-+ */
-+void gpi_enable(void *base)
-+{
-+	writel(CORE_ENABLE, base + GPI_CTRL);
-+}
-+
-+/* Disables a GPI block.
-+ * @param[in] base	GPI base address
-+ */
-+void gpi_disable(void *base)
-+{
-+	writel(CORE_DISABLE, base + GPI_CTRL);
-+}
-+
-+/* Sets the configuration of a GPI block.
-+ * @param[in] base	GPI base address
-+ * @param[in] cfg	GPI configuration
-+ */
-+void gpi_set_config(void *base, struct gpi_cfg *cfg)
-+{
-+	writel(CBUS_VIRT_TO_PFE(BMU1_BASE_ADDR + BMU_ALLOC_CTRL),	base
-+		+ GPI_LMEM_ALLOC_ADDR);
-+	writel(CBUS_VIRT_TO_PFE(BMU1_BASE_ADDR + BMU_FREE_CTRL),	base
-+		+ GPI_LMEM_FREE_ADDR);
-+	writel(CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_ALLOC_CTRL),	base
-+		+ GPI_DDR_ALLOC_ADDR);
-+	writel(CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_FREE_CTRL),	base
-+		+ GPI_DDR_FREE_ADDR);
-+	writel(CBUS_VIRT_TO_PFE(CLASS_INQ_PKTPTR), base + GPI_CLASS_ADDR);
-+	writel(DDR_HDR_SIZE, base + GPI_DDR_DATA_OFFSET);
-+	writel(LMEM_HDR_SIZE, base + GPI_LMEM_DATA_OFFSET);
-+	writel(0, base + GPI_LMEM_SEC_BUF_DATA_OFFSET);
-+	writel(0, base + GPI_DDR_SEC_BUF_DATA_OFFSET);
-+	writel((DDR_HDR_SIZE << 16) |	LMEM_HDR_SIZE,	base + GPI_HDR_SIZE);
-+	writel((DDR_BUF_SIZE << 16) |	LMEM_BUF_SIZE,	base + GPI_BUF_SIZE);
-+
-+	writel(((cfg->lmem_rtry_cnt << 16) | (GPI_DDR_BUF_EN << 1) |
-+		GPI_LMEM_BUF_EN), base + GPI_RX_CONFIG);
-+	writel(cfg->tmlf_txthres, base + GPI_TMLF_TX);
-+	writel(cfg->aseq_len,	base + GPI_DTX_ASEQ);
-+	writel(1, base + GPI_TOE_CHKSUM_EN);
-+
-+	if (cfg->mtip_pause_reg) {
-+		writel(cfg->mtip_pause_reg, base + GPI_CSR_MTIP_PAUSE_REG);
-+		writel(EGPI_PAUSE_TIME, base + GPI_TX_PAUSE_TIME);
-+	}
-+}
-+
-+/**************************** CLASSIFIER ***************************/
-+
-+/* Initializes CLASSIFIER block.
-+ * @param[in] cfg	CLASSIFIER configuration
-+ */
-+void class_init(struct class_cfg *cfg)
-+{
-+	class_reset();
-+
-+	class_disable();
-+
-+	class_set_config(cfg);
-+}
-+
-+/* Resets CLASSIFIER block.
-+ *
-+ */
-+void class_reset(void)
-+{
-+	writel(CORE_SW_RESET, CLASS_TX_CTRL);
-+}
-+
-+/* Enables all CLASS-PE's cores.
-+ *
-+ */
-+void class_enable(void)
-+{
-+	writel(CORE_ENABLE, CLASS_TX_CTRL);
-+}
-+
-+/* Disables all CLASS-PE's cores.
-+ *
-+ */
-+void class_disable(void)
-+{
-+	writel(CORE_DISABLE, CLASS_TX_CTRL);
-+}
-+
-+/*
-+ * Sets the configuration of the CLASSIFIER block.
-+ * @param[in] cfg	CLASSIFIER configuration
-+ */
-+void class_set_config(struct class_cfg *cfg)
-+{
-+	u32 val;
-+
-+	/* Initialize route table */
-+	if (!cfg->resume)
-+		memset(DDR_PHYS_TO_VIRT(cfg->route_table_baseaddr), 0, (1 <<
-+		cfg->route_table_hash_bits) * CLASS_ROUTE_SIZE);
-+
-+#if !defined(LS1012A_PFE_RESET_WA)
-+	writel(cfg->pe_sys_clk_ratio,	CLASS_PE_SYS_CLK_RATIO);
-+#endif
-+
-+	writel((DDR_HDR_SIZE << 16) | LMEM_HDR_SIZE,	CLASS_HDR_SIZE);
-+	writel(LMEM_BUF_SIZE,				CLASS_LMEM_BUF_SIZE);
-+	writel(CLASS_ROUTE_ENTRY_SIZE(CLASS_ROUTE_SIZE) |
-+		CLASS_ROUTE_HASH_SIZE(cfg->route_table_hash_bits),
-+		CLASS_ROUTE_HASH_ENTRY_SIZE);
-+	writel(HIF_PKT_CLASS_EN | HIF_PKT_OFFSET(sizeof(struct hif_hdr)),
-+	       CLASS_HIF_PARSE);
-+
-+	val = HASH_CRC_PORT_IP | QB2BUS_LE;
-+
-+#if defined(CONFIG_IP_ALIGNED)
-+	val |= IP_ALIGNED;
-+#endif
-+
-+	/*
-+	 *  Class PE packet steering will only work if TOE mode, bridge fetch or
-+	 * route fetch are enabled (see class/qb_fet.v). Route fetch would
-+	 * trigger additional memory copies (likely from DDR because of hash
-+	 * table size, which cannot be reduced because PE software still
-+	 * relies on hash value computed in HW), so when not in TOE mode we
-+	 * simply enable HW bridge fetch even though we don't use it.
-+	 */
-+	if (cfg->toe_mode)
-+		val |= CLASS_TOE;
-+	else
-+		val |= HW_BRIDGE_FETCH;
-+
-+	writel(val, CLASS_ROUTE_MULTI);
-+
-+	writel(DDR_PHYS_TO_PFE(cfg->route_table_baseaddr),
-+	       CLASS_ROUTE_TABLE_BASE);
-+	writel(CLASS_PE0_RO_DM_ADDR0_VAL,		CLASS_PE0_RO_DM_ADDR0);
-+	writel(CLASS_PE0_RO_DM_ADDR1_VAL,		CLASS_PE0_RO_DM_ADDR1);
-+	writel(CLASS_PE0_QB_DM_ADDR0_VAL,		CLASS_PE0_QB_DM_ADDR0);
-+	writel(CLASS_PE0_QB_DM_ADDR1_VAL,		CLASS_PE0_QB_DM_ADDR1);
-+	writel(CBUS_VIRT_TO_PFE(TMU_PHY_INQ_PKTPTR),	CLASS_TM_INQ_ADDR);
-+
-+	writel(23, CLASS_AFULL_THRES);
-+	writel(23, CLASS_TSQ_FIFO_THRES);
-+
-+	writel(24, CLASS_MAX_BUF_CNT);
-+	writel(24, CLASS_TSQ_MAX_CNT);
-+}
-+
-+/**************************** TMU ***************************/
-+
-+void tmu_reset(void)
-+{
-+	writel(SW_RESET, TMU_CTRL);
-+}
-+
-+/* Initializes TMU block.
-+ * @param[in] cfg	TMU configuration
-+ */
-+void tmu_init(struct tmu_cfg *cfg)
-+{
-+	int q, phyno;
-+
-+	tmu_disable(0xF);
-+	mdelay(10);
-+
-+#if !defined(LS1012A_PFE_RESET_WA)
-+	/* keep in soft reset */
-+	writel(SW_RESET, TMU_CTRL);
-+#endif
-+	writel(0x3, TMU_SYS_GENERIC_CONTROL);
-+	writel(750, TMU_INQ_WATERMARK);
-+	writel(CBUS_VIRT_TO_PFE(EGPI1_BASE_ADDR +
-+		GPI_INQ_PKTPTR),	TMU_PHY0_INQ_ADDR);
-+	writel(CBUS_VIRT_TO_PFE(EGPI2_BASE_ADDR +
-+		GPI_INQ_PKTPTR),	TMU_PHY1_INQ_ADDR);
-+	writel(CBUS_VIRT_TO_PFE(HGPI_BASE_ADDR +
-+		GPI_INQ_PKTPTR),	TMU_PHY3_INQ_ADDR);
-+	writel(CBUS_VIRT_TO_PFE(HIF_NOCPY_RX_INQ0_PKTPTR), TMU_PHY4_INQ_ADDR);
-+	writel(CBUS_VIRT_TO_PFE(UTIL_INQ_PKTPTR), TMU_PHY5_INQ_ADDR);
-+	writel(CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_FREE_CTRL),
-+	       TMU_BMU_INQ_ADDR);
-+
-+	writel(0x3FF,	TMU_TDQ0_SCH_CTRL);	/*
-+						 * enabling all 10
-+						 * schedulers [9:0] of each TDQ
-+						 */
-+	writel(0x3FF,	TMU_TDQ1_SCH_CTRL);
-+	writel(0x3FF,	TMU_TDQ3_SCH_CTRL);
-+
-+#if !defined(LS1012A_PFE_RESET_WA)
-+	writel(cfg->pe_sys_clk_ratio,	TMU_PE_SYS_CLK_RATIO);
-+#endif
-+
-+#if !defined(LS1012A_PFE_RESET_WA)
-+	writel(DDR_PHYS_TO_PFE(cfg->llm_base_addr),	TMU_LLM_BASE_ADDR);
-+	/* Extra packet pointers will be stored from this address onwards */
-+
-+	writel(cfg->llm_queue_len,	TMU_LLM_QUE_LEN);
-+	writel(5,			TMU_TDQ_IIFG_CFG);
-+	writel(DDR_BUF_SIZE,		TMU_BMU_BUF_SIZE);
-+
-+	writel(0x0,			TMU_CTRL);
-+
-+	/* MEM init */
-+	pr_info("%s: mem init\n", __func__);
-+	writel(MEM_INIT,	TMU_CTRL);
-+
-+	while (!(readl(TMU_CTRL) & MEM_INIT_DONE))
-+		;
-+
-+	/* LLM init */
-+	pr_info("%s: lmem init\n", __func__);
-+	writel(LLM_INIT,	TMU_CTRL);
-+
-+	while (!(readl(TMU_CTRL) & LLM_INIT_DONE))
-+		;
-+#endif
-+	/* set up each queue for tail drop */
-+	for (phyno = 0; phyno < 4; phyno++) {
-+		if (phyno == 2)
-+			continue;
-+		for (q = 0; q < 16; q++) {
-+			u32 qdepth;
-+
-+			writel((phyno << 8) | q, TMU_TEQ_CTRL);
-+			writel(1 << 22, TMU_TEQ_QCFG); /*Enable tail drop */
-+
-+			if (phyno == 3)
-+				qdepth = DEFAULT_TMU3_QDEPTH;
-+			else
-+				qdepth = (q == 0) ? DEFAULT_Q0_QDEPTH :
-+						DEFAULT_MAX_QDEPTH;
-+
-+			/* LOG: 68855 */
-+			/*
-+			 * The following is a workaround for the reordered
-+			 * packet and BMU2 buffer leakage issue.
-+			 */
-+			if (CHIP_REVISION() == 0)
-+				qdepth = 31;
-+
-+			writel(qdepth << 18, TMU_TEQ_HW_PROB_CFG2);
-+			writel(qdepth >> 14, TMU_TEQ_HW_PROB_CFG3);
-+		}
-+	}
-+
-+#ifdef CFG_LRO
-+	/* Set TMU-3 queue 5 (LRO) in no-drop mode */
-+	writel((3 << 8) | TMU_QUEUE_LRO, TMU_TEQ_CTRL);
-+	writel(0, TMU_TEQ_QCFG);
-+#endif
-+
-+	writel(0x05, TMU_TEQ_DISABLE_DROPCHK);
-+
-+	writel(0x0, TMU_CTRL);
-+}
-+
-+/* Enables TMU-PE cores.
-+ * @param[in] pe_mask	TMU PE mask
-+ */
-+void tmu_enable(u32 pe_mask)
-+{
-+	writel(readl(TMU_TX_CTRL) | (pe_mask & 0xF), TMU_TX_CTRL);
-+}
-+
-+/* Disables TMU cores.
-+ * @param[in] pe_mask	TMU PE mask
-+ */
-+void tmu_disable(u32 pe_mask)
-+{
-+	writel(readl(TMU_TX_CTRL) & ~(pe_mask & 0xF), TMU_TX_CTRL);
-+}
-+
-+/* This will return the tmu queue status
-+ * @param[in] if_id	gem interface id or TMU index
-+ * @return		returns the bit mask of busy queues, zero means all
-+ * queues are empty
-+ */
-+u32 tmu_qstatus(u32 if_id)
-+{
-+	return cpu_to_be32(pe_dmem_read(TMU0_ID + if_id, TMU_DM_PESTATUS +
-+		offsetof(struct pe_status, tmu_qstatus), 4));
-+}
-+
-+u32 tmu_pkts_processed(u32 if_id)
-+{
-+	return cpu_to_be32(pe_dmem_read(TMU0_ID + if_id, TMU_DM_PESTATUS +
-+		offsetof(struct pe_status, rx), 4));
-+}
-+
-+/**************************** UTIL ***************************/
-+
-+/* Resets UTIL block.
-+ */
-+void util_reset(void)
-+{
-+	writel(CORE_SW_RESET, UTIL_TX_CTRL);
-+}
-+
-+/* Initializes UTIL block.
-+ * @param[in] cfg	UTIL configuration
-+ */
-+void util_init(struct util_cfg *cfg)
-+{
-+	writel(cfg->pe_sys_clk_ratio,   UTIL_PE_SYS_CLK_RATIO);
-+}
-+
-+/* Enables UTIL-PE core.
-+ *
-+ */
-+void util_enable(void)
-+{
-+	writel(CORE_ENABLE, UTIL_TX_CTRL);
-+}
-+
-+/* Disables UTIL-PE core.
-+ *
-+ */
-+void util_disable(void)
-+{
-+	writel(CORE_DISABLE, UTIL_TX_CTRL);
-+}
-+
-+/**************************** HIF ***************************/
-+/* Initializes HIF copy block.
-+ *
-+ */
-+void hif_init(void)
-+{
-+	/*Initialize HIF registers*/
-+	writel((HIF_RX_POLL_CTRL_CYCLE << 16) | HIF_TX_POLL_CTRL_CYCLE,
-+	       HIF_POLL_CTRL);
-+}
-+
-+/* Enable hif tx DMA and interrupt
-+ *
-+ */
-+void hif_tx_enable(void)
-+{
-+	writel(HIF_CTRL_DMA_EN, HIF_TX_CTRL);
-+	writel((readl(HIF_INT_ENABLE) | HIF_INT_EN | HIF_TXPKT_INT_EN),
-+	       HIF_INT_ENABLE);
-+}
-+
-+/* Disable hif tx DMA and interrupt
-+ *
-+ */
-+void hif_tx_disable(void)
-+{
-+	u32	hif_int;
-+
-+	writel(0, HIF_TX_CTRL);
-+
-+	hif_int = readl(HIF_INT_ENABLE);
-+	hif_int &= HIF_TXPKT_INT_EN;
-+	writel(hif_int, HIF_INT_ENABLE);
-+}
-+
-+/* Enable hif rx DMA and interrupt
-+ *
-+ */
-+void hif_rx_enable(void)
-+{
-+	hif_rx_dma_start();
-+	writel((readl(HIF_INT_ENABLE) | HIF_INT_EN | HIF_RXPKT_INT_EN),
-+	       HIF_INT_ENABLE);
-+}
-+
-+/* Disable hif rx DMA and interrupt
-+ *
-+ */
-+void hif_rx_disable(void)
-+{
-+	u32	hif_int;
-+
-+	writel(0, HIF_RX_CTRL);
-+
-+	hif_int = readl(HIF_INT_ENABLE);
-+	hif_int &= HIF_RXPKT_INT_EN;
-+	writel(hif_int, HIF_INT_ENABLE);
-+}
---- /dev/null
-+++ b/drivers/staging/fsl_ppfe/pfe_hif.c
-@@ -0,0 +1,1064 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+/*
-+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
-+ * Copyright 2017 NXP
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/interrupt.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/dmapool.h>
-+#include <linux/sched.h>
-+#include <linux/module.h>
-+#include <linux/list.h>
-+#include <linux/kthread.h>
-+#include <linux/slab.h>
-+
-+#include <linux/io.h>
-+#include <asm/irq.h>
-+
-+#include "pfe_mod.h"
-+
-+#define HIF_INT_MASK	(HIF_INT | HIF_RXPKT_INT | HIF_TXPKT_INT)
-+
-+unsigned char napi_first_batch;
-+
-+static void pfe_tx_do_cleanup(unsigned long data);
-+
-+static int pfe_hif_alloc_descr(struct pfe_hif *hif)
-+{
-+	void *addr;
-+	dma_addr_t dma_addr;
-+	int err = 0;
-+
-+	pr_info("%s\n", __func__);
-+	addr = dma_alloc_coherent(pfe->dev,
-+				  HIF_RX_DESC_NT * sizeof(struct hif_desc) +
-+				  HIF_TX_DESC_NT * sizeof(struct hif_desc),
-+				  &dma_addr, GFP_KERNEL);
-+
-+	if (!addr) {
-+		pr_err("%s: Could not allocate buffer descriptors!\n"
-+			, __func__);
-+		err = -ENOMEM;
-+		goto err0;
-+	}
-+
-+	hif->descr_baseaddr_p = dma_addr;
-+	hif->descr_baseaddr_v = addr;
-+	hif->rx_ring_size = HIF_RX_DESC_NT;
-+	hif->tx_ring_size = HIF_TX_DESC_NT;
-+
-+	return 0;
-+
-+err0:
-+	return err;
-+}
-+
-+#if defined(LS1012A_PFE_RESET_WA)
-+static void pfe_hif_disable_rx_desc(struct pfe_hif *hif)
-+{
-+	int ii;
-+	struct hif_desc	*desc = hif->rx_base;
-+
-+	/*Mark all descriptors as LAST_BD */
-+	for (ii = 0; ii < hif->rx_ring_size; ii++) {
-+		desc->ctrl |= BD_CTRL_LAST_BD;
-+		desc++;
-+	}
-+}
-+
-+struct class_rx_hdr_t {
-+	u32     next_ptr;       /* ptr to the start of the first DDR buffer */
-+	u16     length;         /* total packet length */
-+	u16     phyno;          /* input physical port number */
-+	u32     status;         /* gemac status bits */
-+	u32     status2;            /* reserved for software usage */
-+};
-+
-+/* STATUS_BAD_FRAME_ERR is set for all errors (including checksums if enabled)
-+ * except overflow
-+ */
-+#define STATUS_BAD_FRAME_ERR            BIT(16)
-+#define STATUS_LENGTH_ERR               BIT(17)
-+#define STATUS_CRC_ERR                  BIT(18)
-+#define STATUS_TOO_SHORT_ERR            BIT(19)
-+#define STATUS_TOO_LONG_ERR             BIT(20)
-+#define STATUS_CODE_ERR                 BIT(21)
-+#define STATUS_MC_HASH_MATCH            BIT(22)
-+#define STATUS_CUMULATIVE_ARC_HIT       BIT(23)
-+#define STATUS_UNICAST_HASH_MATCH       BIT(24)
-+#define STATUS_IP_CHECKSUM_CORRECT      BIT(25)
-+#define STATUS_TCP_CHECKSUM_CORRECT     BIT(26)
-+#define STATUS_UDP_CHECKSUM_CORRECT     BIT(27)
-+#define STATUS_OVERFLOW_ERR             BIT(28) /* GPI error */
-+#define MIN_PKT_SIZE			64
-+
-+static inline void copy_to_lmem(u32 *dst, u32 *src, int len)
-+{
-+	int i;
-+
-+	for (i = 0; i < len; i += sizeof(u32))	{
-+		*dst = htonl(*src);
-+		dst++; src++;
-+	}
-+}
-+
-+static void send_dummy_pkt_to_hif(void)
-+{
-+	void *lmem_ptr, *ddr_ptr, *lmem_virt_addr;
-+	u32 physaddr;
-+	struct class_rx_hdr_t local_hdr;
-+	static u32 dummy_pkt[] =  {
-+		0x33221100, 0x2b785544, 0xd73093cb, 0x01000608,
-+		0x04060008, 0x2b780200, 0xd73093cb, 0x0a01a8c0,
-+		0x33221100, 0xa8c05544, 0x00000301, 0x00000000,
-+		0x00000000, 0x00000000, 0x00000000, 0xbe86c51f };
-+
-+	ddr_ptr = (void *)((uintptr_t)readl(BMU2_BASE_ADDR + BMU_ALLOC_CTRL));
-+	if (!ddr_ptr)
-+		return;
-+
-+	lmem_ptr = (void *)((uintptr_t)readl(BMU1_BASE_ADDR + BMU_ALLOC_CTRL));
-+	if (!lmem_ptr)
-+		return;
-+
-+	pr_info("Sending a dummy pkt to HIF %p %p\n", ddr_ptr, lmem_ptr);
-+	physaddr = (u32)DDR_VIRT_TO_PFE(ddr_ptr);
-+
-+	lmem_virt_addr = (void *)CBUS_PFE_TO_VIRT((unsigned long int)lmem_ptr);
-+
-+	local_hdr.phyno = htons(0); /* RX_PHY_0 */
-+	local_hdr.length = htons(MIN_PKT_SIZE);
-+
-+	local_hdr.next_ptr = htonl((u32)physaddr);
-+	/*Mark checksum is correct */
-+	local_hdr.status = htonl((STATUS_IP_CHECKSUM_CORRECT |
-+				STATUS_UDP_CHECKSUM_CORRECT |
-+				STATUS_TCP_CHECKSUM_CORRECT |
-+				STATUS_UNICAST_HASH_MATCH |
-+				STATUS_CUMULATIVE_ARC_HIT));
-+	local_hdr.status2 = 0;
-+
-+	copy_to_lmem((u32 *)lmem_virt_addr, (u32 *)&local_hdr,
-+		     sizeof(local_hdr));
-+
-+	copy_to_lmem((u32 *)(lmem_virt_addr + LMEM_HDR_SIZE), (u32 *)dummy_pkt,
-+		     0x40);
-+
-+	writel((unsigned long int)lmem_ptr, CLASS_INQ_PKTPTR);
-+}
-+
-+void pfe_hif_rx_idle(struct pfe_hif *hif)
-+{
-+	int hif_stop_loop = 10;
-+	u32 rx_status;
-+
-+	pfe_hif_disable_rx_desc(hif);
-+	pr_info("Bringing hif to idle state...");
-+	writel(0, HIF_INT_ENABLE);
-+	/*If HIF Rx BDP is busy send a dummy packet */
-+	do {
-+		rx_status = readl(HIF_RX_STATUS);
-+		if (rx_status & BDP_CSR_RX_DMA_ACTV)
-+			send_dummy_pkt_to_hif();
-+
-+		usleep_range(100, 150);
-+	} while (--hif_stop_loop);
-+
-+	if (readl(HIF_RX_STATUS) & BDP_CSR_RX_DMA_ACTV)
-+		pr_info("Failed\n");
-+	else
-+		pr_info("Done\n");
-+}
-+#endif
-+
-+static void pfe_hif_free_descr(struct pfe_hif *hif)
-+{
-+	pr_info("%s\n", __func__);
-+
-+	dma_free_coherent(pfe->dev,
-+			  hif->rx_ring_size * sizeof(struct hif_desc) +
-+			  hif->tx_ring_size * sizeof(struct hif_desc),
-+			  hif->descr_baseaddr_v, hif->descr_baseaddr_p);
-+}
-+
-+void pfe_hif_desc_dump(struct pfe_hif *hif)
-+{
-+	struct hif_desc	*desc;
-+	u64 desc_p;
-+	int ii = 0;
-+
-+	pr_info("%s\n", __func__);
-+
-+	desc = hif->rx_base;
-+	desc_p = ((void *)desc - hif->descr_baseaddr_v +
-+			hif->descr_baseaddr_p);
-+
-+	pr_info("HIF Rx desc base %p physical %llx\n", desc, desc_p);
-+	for (ii = 0; ii < hif->rx_ring_size; ii++) {
-+		pr_info("status: %08x, ctrl: %08x, data: %08x, next: %x\n",
-+			readl(&desc->status), readl(&desc->ctrl),
-+			readl(&desc->data), readl(&desc->next));
-+			desc++;
-+	}
-+
-+	desc = hif->tx_base;
-+	desc_p = ((void *)desc - hif->descr_baseaddr_v +
-+			hif->descr_baseaddr_p);
-+
-+	pr_info("HIF Tx desc base %p physical %llx\n", desc, desc_p);
-+	for (ii = 0; ii < hif->tx_ring_size; ii++) {
-+		pr_info("status: %08x, ctrl: %08x, data: %08x, next: %x\n",
-+			readl(&desc->status), readl(&desc->ctrl),
-+			readl(&desc->data), readl(&desc->next));
-+		desc++;
-+	}
-+}
-+
-+/* pfe_hif_release_buffers */
-+static void pfe_hif_release_buffers(struct pfe_hif *hif)
-+{
-+	struct hif_desc	*desc;
-+	int i = 0;
-+
-+	hif->rx_base = hif->descr_baseaddr_v;
-+
-+	pr_info("%s\n", __func__);
-+
-+	/*Free Rx buffers */
-+	desc = hif->rx_base;
-+	for (i = 0; i < hif->rx_ring_size; i++) {
-+		if (readl(&desc->data)) {
-+			if ((i < hif->shm->rx_buf_pool_cnt) &&
-+			    (!hif->shm->rx_buf_pool[i])) {
-+				/*
-+				 * dma_unmap_single(hif->dev, desc->data,
-+				 * hif->rx_buf_len[i], DMA_FROM_DEVICE);
-+				 */
-+				dma_unmap_single(hif->dev,
-+						 DDR_PFE_TO_PHYS(
-+						 readl(&desc->data)),
-+						 hif->rx_buf_len[i],
-+						 DMA_FROM_DEVICE);
-+				hif->shm->rx_buf_pool[i] = hif->rx_buf_addr[i];
-+			} else {
-+				pr_err("%s: buffer pool already full\n"
-+					, __func__);
-+			}
-+		}
-+
-+		writel(0, &desc->data);
-+		writel(0, &desc->status);
-+		writel(0, &desc->ctrl);
-+		desc++;
-+	}
-+}
-+
-+/*
-+ * pfe_hif_init_buffers
-+ * This function initializes the HIF Rx/Tx ring descriptors and
-+ * initialize Rx queue with buffers.
-+ */
-+static int pfe_hif_init_buffers(struct pfe_hif *hif)
-+{
-+	struct hif_desc	*desc, *first_desc_p;
-+	u32 data;
-+	int i = 0;
-+
-+	pr_info("%s\n", __func__);
-+
-+	/* Check enough Rx buffers available in the shared memory */
-+	if (hif->shm->rx_buf_pool_cnt < hif->rx_ring_size)
-+		return -ENOMEM;
-+
-+	hif->rx_base = hif->descr_baseaddr_v;
-+	memset(hif->rx_base, 0, hif->rx_ring_size * sizeof(struct hif_desc));
-+
-+	/*Initialize Rx descriptors */
-+	desc = hif->rx_base;
-+	first_desc_p = (struct hif_desc *)hif->descr_baseaddr_p;
-+
-+	for (i = 0; i < hif->rx_ring_size; i++) {
-+		/* Initialize Rx buffers from the shared memory */
-+
-+		data = (u32)dma_map_single(hif->dev, hif->shm->rx_buf_pool[i],
-+				pfe_pkt_size, DMA_FROM_DEVICE);
-+		hif->rx_buf_addr[i] = hif->shm->rx_buf_pool[i];
-+		hif->rx_buf_len[i] = pfe_pkt_size;
-+		hif->shm->rx_buf_pool[i] = NULL;
-+
-+		if (likely(dma_mapping_error(hif->dev, data) == 0)) {
-+			writel(DDR_PHYS_TO_PFE(data), &desc->data);
-+		} else {
-+			pr_err("%s : low on mem\n",  __func__);
-+
-+			goto err;
-+		}
-+
-+		writel(0, &desc->status);
-+
-+		/*
-+		 * Ensure everything else is written to DDR before
-+		 * writing bd->ctrl
-+		 */
-+		wmb();
-+
-+		writel((BD_CTRL_PKT_INT_EN | BD_CTRL_LIFM
-+			| BD_CTRL_DIR | BD_CTRL_DESC_EN
-+			| BD_BUF_LEN(pfe_pkt_size)), &desc->ctrl);
-+
-+		/* Chain descriptors */
-+		writel((u32)DDR_PHYS_TO_PFE(first_desc_p + i + 1), &desc->next);
-+		desc++;
-+	}
-+
-+	/* Overwrite last descriptor to chain it to first one*/
-+	desc--;
-+	writel((u32)DDR_PHYS_TO_PFE(first_desc_p), &desc->next);
-+
-+	hif->rxtoclean_index = 0;
-+
-+	/*Initialize Rx buffer descriptor ring base address */
-+	writel(DDR_PHYS_TO_PFE(hif->descr_baseaddr_p), HIF_RX_BDP_ADDR);
-+
-+	hif->tx_base = hif->rx_base + hif->rx_ring_size;
-+	first_desc_p = (struct hif_desc *)hif->descr_baseaddr_p +
-+				hif->rx_ring_size;
-+	memset(hif->tx_base, 0, hif->tx_ring_size * sizeof(struct hif_desc));
-+
-+	/*Initialize tx descriptors */
-+	desc = hif->tx_base;
-+
-+	for (i = 0; i < hif->tx_ring_size; i++) {
-+		/* Chain descriptors */
-+		writel((u32)DDR_PHYS_TO_PFE(first_desc_p + i + 1), &desc->next);
-+		writel(0, &desc->ctrl);
-+		desc++;
-+	}
-+
-+	/* Overwrite last descriptor to chain it to first one */
-+	desc--;
-+	writel((u32)DDR_PHYS_TO_PFE(first_desc_p), &desc->next);
-+	hif->txavail = hif->tx_ring_size;
-+	hif->txtosend = 0;
-+	hif->txtoclean = 0;
-+	hif->txtoflush = 0;
-+
-+	/*Initialize Tx buffer descriptor ring base address */
-+	writel((u32)DDR_PHYS_TO_PFE(first_desc_p), HIF_TX_BDP_ADDR);
-+
-+	return 0;
-+
-+err:
-+	pfe_hif_release_buffers(hif);
-+	return -ENOMEM;
-+}
-+
-+/*
-+ * pfe_hif_client_register
-+ *
-+ * This function used to register a client driver with the HIF driver.
-+ *
-+ * Return value:
-+ * 0 - on Successful registration
-+ */
-+static int pfe_hif_client_register(struct pfe_hif *hif, u32 client_id,
-+				   struct hif_client_shm *client_shm)
-+{
-+	struct hif_client *client = &hif->client[client_id];
-+	u32 i, cnt;
-+	struct rx_queue_desc *rx_qbase;
-+	struct tx_queue_desc *tx_qbase;
-+	struct hif_rx_queue *rx_queue;
-+	struct hif_tx_queue *tx_queue;
-+	int err = 0;
-+
-+	pr_info("%s\n", __func__);
-+
-+	spin_lock_bh(&hif->tx_lock);
-+
-+	if (test_bit(client_id, &hif->shm->g_client_status[0])) {
-+		pr_err("%s: client %d already registered\n",
-+		       __func__, client_id);
-+		err = -1;
-+		goto unlock;
-+	}
-+
-+	memset(client, 0, sizeof(struct hif_client));
-+
-+	/* Initialize client Rx queues baseaddr, size */
-+
-+	cnt = CLIENT_CTRL_RX_Q_CNT(client_shm->ctrl);
-+	/* Check if client is requesting for more queues than supported */
-+	if (cnt > HIF_CLIENT_QUEUES_MAX)
-+		cnt = HIF_CLIENT_QUEUES_MAX;
-+
-+	client->rx_qn = cnt;
-+	rx_qbase = (struct rx_queue_desc *)client_shm->rx_qbase;
-+	for (i = 0; i < cnt; i++) {
-+		rx_queue = &client->rx_q[i];
-+		rx_queue->base = rx_qbase + i * client_shm->rx_qsize;
-+		rx_queue->size = client_shm->rx_qsize;
-+		rx_queue->write_idx = 0;
-+	}
-+
-+	/* Initialize client Tx queues baseaddr, size */
-+	cnt = CLIENT_CTRL_TX_Q_CNT(client_shm->ctrl);
-+
-+	/* Check if client is requesting for more queues than supported */
-+	if (cnt > HIF_CLIENT_QUEUES_MAX)
-+		cnt = HIF_CLIENT_QUEUES_MAX;
-+
-+	client->tx_qn = cnt;
-+	tx_qbase = (struct tx_queue_desc *)client_shm->tx_qbase;
-+	for (i = 0; i < cnt; i++) {
-+		tx_queue = &client->tx_q[i];
-+		tx_queue->base = tx_qbase + i * client_shm->tx_qsize;
-+		tx_queue->size = client_shm->tx_qsize;
-+		tx_queue->ack_idx = 0;
-+	}
-+
-+	set_bit(client_id, &hif->shm->g_client_status[0]);
-+
-+unlock:
-+	spin_unlock_bh(&hif->tx_lock);
-+
-+	return err;
-+}
-+
-+/*
-+ * pfe_hif_client_unregister
-+ *
-+ * This function used to unregister a client  from the HIF driver.
-+ *
-+ */
-+static void pfe_hif_client_unregister(struct pfe_hif *hif, u32 client_id)
-+{
-+	pr_info("%s\n", __func__);
-+
-+	/*
-+	 * Mark client as no longer available (which prevents further packet
-+	 * receive for this client)
-+	 */
-+	spin_lock_bh(&hif->tx_lock);
-+
-+	if (!test_bit(client_id, &hif->shm->g_client_status[0])) {
-+		pr_err("%s: client %d not registered\n", __func__,
-+		       client_id);
-+
-+		spin_unlock_bh(&hif->tx_lock);
-+		return;
-+	}
-+
-+	clear_bit(client_id, &hif->shm->g_client_status[0]);
-+
-+	spin_unlock_bh(&hif->tx_lock);
-+}
-+
-+/*
-+ * client_put_rxpacket-
-+ * This functions puts the Rx pkt  in the given client Rx queue.
-+ * It actually swap the Rx pkt in the client Rx descriptor buffer
-+ * and returns the free buffer from it.
-+ *
-+ * If the function returns NULL means client Rx queue is full and
-+ * packet couldn't send to client queue.
-+ */
-+static void *client_put_rxpacket(struct hif_rx_queue *queue, void *pkt, u32 len,
-+				 u32 flags, u32 client_ctrl, u32 *rem_len)
-+{
-+	void *free_pkt = NULL;
-+	struct rx_queue_desc *desc = queue->base + queue->write_idx;
-+
-+	if (readl(&desc->ctrl) & CL_DESC_OWN) {
-+		if (page_mode) {
-+			int rem_page_size = PAGE_SIZE -
-+					PRESENT_OFST_IN_PAGE(pkt);
-+			int cur_pkt_size = ROUND_MIN_RX_SIZE(len +
-+					pfe_pkt_headroom);
-+			*rem_len = (rem_page_size - cur_pkt_size);
-+			if (*rem_len) {
-+				free_pkt = pkt + cur_pkt_size;
-+				get_page(virt_to_page(free_pkt));
-+			} else {
-+				free_pkt = (void
-+				*)__get_free_page(GFP_ATOMIC | GFP_DMA_PFE);
-+				*rem_len = pfe_pkt_size;
-+			}
-+		} else {
-+			free_pkt = kmalloc(PFE_BUF_SIZE, GFP_ATOMIC |
-+					GFP_DMA_PFE);
-+			*rem_len = PFE_BUF_SIZE - pfe_pkt_headroom;
-+		}
-+
-+		if (free_pkt) {
-+			desc->data = pkt;
-+			desc->client_ctrl = client_ctrl;
-+			/*
-+			 * Ensure everything else is written to DDR before
-+			 * writing bd->ctrl
-+			 */
-+			smp_wmb();
-+			writel(CL_DESC_BUF_LEN(len) | flags, &desc->ctrl);
-+			queue->write_idx = (queue->write_idx + 1)
-+					    & (queue->size - 1);
-+
-+			free_pkt += pfe_pkt_headroom;
-+		}
-+	}
-+
-+	return free_pkt;
-+}
-+
-+/*
-+ * pfe_hif_rx_process-
-+ * This function does pfe hif rx queue processing.
-+ * Dequeue packet from Rx queue and send it to corresponding client queue
-+ */
-+static int pfe_hif_rx_process(struct pfe_hif *hif, int budget)
-+{
-+	struct hif_desc	*desc;
-+	struct hif_hdr *pkt_hdr;
-+	struct __hif_hdr hif_hdr;
-+	void *free_buf;
-+	int rtc, len, rx_processed = 0;
-+	struct __hif_desc local_desc;
-+	int flags;
-+	unsigned int desc_p;
-+	unsigned int buf_size = 0;
-+
-+	spin_lock_bh(&hif->lock);
-+
-+	rtc = hif->rxtoclean_index;
-+
-+	while (rx_processed < budget) {
-+		desc = hif->rx_base + rtc;
-+
-+		__memcpy12(&local_desc, desc);
-+
-+		/* ACK pending Rx interrupt */
-+		if (local_desc.ctrl & BD_CTRL_DESC_EN) {
-+			writel(HIF_INT | HIF_RXPKT_INT, HIF_INT_SRC);
-+
-+			if (rx_processed == 0) {
-+				if (napi_first_batch == 1) {
-+					desc_p = hif->descr_baseaddr_p +
-+					((unsigned long int)(desc) -
-+					(unsigned long
-+					int)hif->descr_baseaddr_v);
-+					napi_first_batch = 0;
-+				}
-+			}
-+
-+			__memcpy12(&local_desc, desc);
-+
-+			if (local_desc.ctrl & BD_CTRL_DESC_EN)
-+				break;
-+		}
-+
-+		napi_first_batch = 0;
-+
-+#ifdef HIF_NAPI_STATS
-+		hif->napi_counters[NAPI_DESC_COUNT]++;
-+#endif
-+		len = BD_BUF_LEN(local_desc.ctrl);
-+		/*
-+		 * dma_unmap_single(hif->dev, DDR_PFE_TO_PHYS(local_desc.data),
-+		 * hif->rx_buf_len[rtc], DMA_FROM_DEVICE);
-+		 */
-+		dma_unmap_single(hif->dev, DDR_PFE_TO_PHYS(local_desc.data),
-+				 hif->rx_buf_len[rtc], DMA_FROM_DEVICE);
-+
-+		pkt_hdr = (struct hif_hdr *)hif->rx_buf_addr[rtc];
-+
-+		/* Track last HIF header received */
-+		if (!hif->started) {
-+			hif->started = 1;
-+
-+			__memcpy8(&hif_hdr, pkt_hdr);
-+
-+			hif->qno = hif_hdr.hdr.q_num;
-+			hif->client_id = hif_hdr.hdr.client_id;
-+			hif->client_ctrl = (hif_hdr.hdr.client_ctrl1 << 16) |
-+						hif_hdr.hdr.client_ctrl;
-+			flags = CL_DESC_FIRST;
-+
-+		} else {
-+			flags = 0;
-+		}
-+
-+		if (local_desc.ctrl & BD_CTRL_LIFM)
-+			flags |= CL_DESC_LAST;
-+
-+		/* Check for valid client id and still registered */
-+		if ((hif->client_id >= HIF_CLIENTS_MAX) ||
-+		    !(test_bit(hif->client_id,
-+			&hif->shm->g_client_status[0]))) {
-+			printk_ratelimited("%s: packet with invalid client id %d q_num %d\n",
-+					   __func__,
-+					   hif->client_id,
-+					   hif->qno);
-+
-+			free_buf = pkt_hdr;
-+
-+			goto pkt_drop;
-+		}
-+
-+		/* Check to valid queue number */
-+		if (hif->client[hif->client_id].rx_qn <= hif->qno) {
-+			pr_info("%s: packet with invalid queue: %d\n"
-+				, __func__, hif->qno);
-+			hif->qno = 0;
-+		}
-+
-+		free_buf =
-+		client_put_rxpacket(&hif->client[hif->client_id].rx_q[hif->qno],
-+				    (void *)pkt_hdr, len, flags,
-+			hif->client_ctrl, &buf_size);
-+
-+		hif_lib_indicate_client(hif->client_id, EVENT_RX_PKT_IND,
-+					hif->qno);
-+
-+		if (unlikely(!free_buf)) {
-+#ifdef HIF_NAPI_STATS
-+			hif->napi_counters[NAPI_CLIENT_FULL_COUNT]++;
-+#endif
-+			/*
-+			 * If we want to keep in polling mode to retry later,
-+			 * we need to tell napi that we consumed
-+			 * the full budget or we will hit a livelock scenario.
-+			 * The core code keeps this napi instance
-+			 * at the head of the list and none of the other
-+			 * instances get to run
-+			 */
-+			rx_processed = budget;
-+
-+			if (flags & CL_DESC_FIRST)
-+				hif->started = 0;
-+
-+			break;
-+		}
-+
-+pkt_drop:
-+		/*Fill free buffer in the descriptor */
-+		hif->rx_buf_addr[rtc] = free_buf;
-+		hif->rx_buf_len[rtc] = min(pfe_pkt_size, buf_size);
-+		writel((DDR_PHYS_TO_PFE
-+			((u32)dma_map_single(hif->dev,
-+			free_buf, hif->rx_buf_len[rtc], DMA_FROM_DEVICE))),
-+			&desc->data);
-+		/*
-+		 * Ensure everything else is written to DDR before
-+		 * writing bd->ctrl
-+		 */
-+		wmb();
-+		writel((BD_CTRL_PKT_INT_EN | BD_CTRL_LIFM | BD_CTRL_DIR |
-+			BD_CTRL_DESC_EN | BD_BUF_LEN(hif->rx_buf_len[rtc])),
-+			&desc->ctrl);
-+
-+		rtc = (rtc + 1) & (hif->rx_ring_size - 1);
-+
-+		if (local_desc.ctrl & BD_CTRL_LIFM) {
-+			if (!(hif->client_ctrl & HIF_CTRL_RX_CONTINUED)) {
-+				rx_processed++;
-+
-+#ifdef HIF_NAPI_STATS
-+				hif->napi_counters[NAPI_PACKET_COUNT]++;
-+#endif
-+			}
-+			hif->started = 0;
-+		}
-+	}
-+
-+	hif->rxtoclean_index = rtc;
-+	spin_unlock_bh(&hif->lock);
-+
-+	/* we made some progress, re-start rx dma in case it stopped */
-+	hif_rx_dma_start();
-+
-+	return rx_processed;
-+}
-+
-+/*
-+ * client_ack_txpacket-
-+ * This function ack the Tx packet in the give client Tx queue by resetting
-+ * ownership bit in the descriptor.
-+ */
-+static int client_ack_txpacket(struct pfe_hif *hif, unsigned int client_id,
-+			       unsigned int q_no)
-+{
-+	struct hif_tx_queue *queue = &hif->client[client_id].tx_q[q_no];
-+	struct tx_queue_desc *desc = queue->base + queue->ack_idx;
-+
-+	if (readl(&desc->ctrl) & CL_DESC_OWN) {
-+		writel((readl(&desc->ctrl) & ~CL_DESC_OWN), &desc->ctrl);
-+		queue->ack_idx = (queue->ack_idx + 1) & (queue->size - 1);
-+
-+		return 0;
-+
-+	} else {
-+		/*This should not happen */
-+		pr_err("%s: %d %d %d %d %d %p %d\n", __func__,
-+		       hif->txtosend, hif->txtoclean, hif->txavail,
-+			client_id, q_no, queue, queue->ack_idx);
-+		WARN(1, "%s: doesn't own this descriptor", __func__);
-+		return 1;
-+	}
-+}
-+
-+void __hif_tx_done_process(struct pfe_hif *hif, int count)
-+{
-+	struct hif_desc *desc;
-+	struct hif_desc_sw *desc_sw;
-+	int ttc, tx_avl;
-+	int pkts_done[HIF_CLIENTS_MAX] = {0, 0};
-+
-+	ttc = hif->txtoclean;
-+	tx_avl = hif->txavail;
-+
-+	while ((tx_avl < hif->tx_ring_size) && count--) {
-+		desc = hif->tx_base + ttc;
-+
-+		if (readl(&desc->ctrl) & BD_CTRL_DESC_EN)
-+			break;
-+
-+		desc_sw = &hif->tx_sw_queue[ttc];
-+
-+		if (desc_sw->data) {
-+			/*
-+			 * dmap_unmap_single(hif->dev, desc_sw->data,
-+			 * desc_sw->len, DMA_TO_DEVICE);
-+			 */
-+			dma_unmap_single(hif->dev, desc_sw->data,
-+					 desc_sw->len, DMA_TO_DEVICE);
-+		}
-+
-+		if (desc_sw->client_id >= HIF_CLIENTS_MAX) {
-+			pr_err("Invalid cl id %d\n", desc_sw->client_id);
-+			break;
-+		}
-+
-+		pkts_done[desc_sw->client_id]++;
-+
-+		client_ack_txpacket(hif, desc_sw->client_id, desc_sw->q_no);
-+
-+		ttc = (ttc + 1) & (hif->tx_ring_size - 1);
-+		tx_avl++;
-+	}
-+
-+	if (pkts_done[0])
-+		hif_lib_indicate_client(0, EVENT_TXDONE_IND, 0);
-+	if (pkts_done[1])
-+		hif_lib_indicate_client(1, EVENT_TXDONE_IND, 0);
-+
-+	hif->txtoclean = ttc;
-+	hif->txavail = tx_avl;
-+
-+	if (!count) {
-+		tasklet_schedule(&hif->tx_cleanup_tasklet);
-+	} else {
-+		/*Enable Tx done interrupt */
-+		writel(readl_relaxed(HIF_INT_ENABLE) | HIF_TXPKT_INT,
-+		       HIF_INT_ENABLE);
-+	}
-+}
-+
-+static void pfe_tx_do_cleanup(unsigned long data)
-+{
-+	struct pfe_hif *hif = (struct pfe_hif *)data;
-+
-+	writel(HIF_INT | HIF_TXPKT_INT, HIF_INT_SRC);
-+
-+	hif_tx_done_process(hif, 64);
-+}
-+
-+/*
-+ * __hif_xmit_pkt -
-+ * This function puts one packet in the HIF Tx queue
-+ */
-+void __hif_xmit_pkt(struct pfe_hif *hif, unsigned int client_id, unsigned int
-+			q_no, void *data, u32 len, unsigned int flags)
-+{
-+	struct hif_desc	*desc;
-+	struct hif_desc_sw *desc_sw;
-+
-+	desc = hif->tx_base + hif->txtosend;
-+	desc_sw = &hif->tx_sw_queue[hif->txtosend];
-+
-+	desc_sw->len = len;
-+	desc_sw->client_id = client_id;
-+	desc_sw->q_no = q_no;
-+	desc_sw->flags = flags;
-+
-+	if (flags & HIF_DONT_DMA_MAP) {
-+		desc_sw->data = 0;
-+		writel((u32)DDR_PHYS_TO_PFE(data), &desc->data);
-+	} else {
-+		desc_sw->data = dma_map_single(hif->dev, data, len,
-+						DMA_TO_DEVICE);
-+		writel((u32)DDR_PHYS_TO_PFE(desc_sw->data), &desc->data);
-+	}
-+
-+	hif->txtosend = (hif->txtosend + 1) & (hif->tx_ring_size - 1);
-+	hif->txavail--;
-+
-+	if ((!((flags & HIF_DATA_VALID) && (flags &
-+				HIF_LAST_BUFFER))))
-+		goto skip_tx;
-+
-+	/*
-+	 * Ensure everything else is written to DDR before
-+	 * writing bd->ctrl
-+	 */
-+	wmb();
-+
-+	do {
-+		desc_sw = &hif->tx_sw_queue[hif->txtoflush];
-+		desc = hif->tx_base + hif->txtoflush;
-+
-+		if (desc_sw->flags & HIF_LAST_BUFFER) {
-+			writel((BD_CTRL_LIFM |
-+			       BD_CTRL_BRFETCH_DISABLE | BD_CTRL_RTFETCH_DISABLE
-+			       | BD_CTRL_PARSE_DISABLE | BD_CTRL_DESC_EN |
-+				BD_CTRL_PKT_INT_EN | BD_BUF_LEN(desc_sw->len)),
-+				&desc->ctrl);
-+		} else {
-+			writel((BD_CTRL_DESC_EN |
-+				BD_BUF_LEN(desc_sw->len)), &desc->ctrl);
-+		}
-+		hif->txtoflush = (hif->txtoflush + 1) & (hif->tx_ring_size - 1);
-+	}
-+	while (hif->txtoflush != hif->txtosend)
-+		;
-+
-+skip_tx:
-+	return;
-+}
-+
-+static irqreturn_t wol_isr(int irq, void *dev_id)
-+{
-+	pr_info("WoL\n");
-+	gemac_set_wol(EMAC1_BASE_ADDR, 0);
-+	gemac_set_wol(EMAC2_BASE_ADDR, 0);
-+	return IRQ_HANDLED;
-+}
-+
-+/*
-+ * hif_isr-
-+ * This ISR routine processes Rx/Tx done interrupts from the HIF hardware block
-+ */
-+static irqreturn_t hif_isr(int irq, void *dev_id)
-+{
-+	struct pfe_hif *hif = (struct pfe_hif *)dev_id;
-+	int int_status;
-+	int int_enable_mask;
-+
-+	/*Read hif interrupt source register */
-+	int_status = readl_relaxed(HIF_INT_SRC);
-+	int_enable_mask = readl_relaxed(HIF_INT_ENABLE);
-+
-+	if ((int_status & HIF_INT) == 0)
-+		return IRQ_NONE;
-+
-+	int_status &= ~(HIF_INT);
-+
-+	if (int_status & HIF_RXPKT_INT) {
-+		int_status &= ~(HIF_RXPKT_INT);
-+		int_enable_mask &= ~(HIF_RXPKT_INT);
-+
-+		napi_first_batch = 1;
-+
-+		if (napi_schedule_prep(&hif->napi)) {
-+#ifdef HIF_NAPI_STATS
-+			hif->napi_counters[NAPI_SCHED_COUNT]++;
-+#endif
-+			__napi_schedule(&hif->napi);
-+		}
-+	}
-+
-+	if (int_status & HIF_TXPKT_INT) {
-+		int_status &= ~(HIF_TXPKT_INT);
-+		int_enable_mask &= ~(HIF_TXPKT_INT);
-+		/*Schedule tx cleanup tassklet */
-+		tasklet_schedule(&hif->tx_cleanup_tasklet);
-+	}
-+
-+	/*Disable interrupts, they will be enabled after they are serviced */
-+	writel_relaxed(int_enable_mask, HIF_INT_ENABLE);
-+
-+	if (int_status) {
-+		pr_info("%s : Invalid interrupt : %d\n", __func__,
-+			int_status);
-+		writel(int_status, HIF_INT_SRC);
-+	}
-+
-+	return IRQ_HANDLED;
-+}
-+
-+void hif_process_client_req(struct pfe_hif *hif, int req, int data1, int data2)
-+{
-+	unsigned int client_id = data1;
-+
-+	if (client_id >= HIF_CLIENTS_MAX) {
-+		pr_err("%s: client id %d out of bounds\n", __func__,
-+		       client_id);
-+		return;
-+	}
-+
-+	switch (req) {
-+	case REQUEST_CL_REGISTER:
-+			/* Request for register a client */
-+			pr_info("%s: register client_id %d\n",
-+				__func__, client_id);
-+			pfe_hif_client_register(hif, client_id, (struct
-+				hif_client_shm *)&hif->shm->client[client_id]);
-+			break;
-+
-+	case REQUEST_CL_UNREGISTER:
-+			pr_info("%s: unregister client_id %d\n",
-+				__func__, client_id);
-+
-+			/* Request for unregister a client */
-+			pfe_hif_client_unregister(hif, client_id);
-+
-+			break;
-+
-+	default:
-+			pr_err("%s: unsupported request %d\n",
-+			       __func__, req);
-+			break;
-+	}
-+
-+	/*
-+	 * Process client Tx queues
-+	 * Currently we don't have checking for tx pending
-+	 */
-+}
-+
-+/*
-+ * pfe_hif_rx_poll
-+ *  This function is NAPI poll function to process HIF Rx queue.
-+ */
-+static int pfe_hif_rx_poll(struct napi_struct *napi, int budget)
-+{
-+	struct pfe_hif *hif = container_of(napi, struct pfe_hif, napi);
-+	int work_done;
-+
-+#ifdef HIF_NAPI_STATS
-+	hif->napi_counters[NAPI_POLL_COUNT]++;
-+#endif
-+
-+	work_done = pfe_hif_rx_process(hif, budget);
-+
-+	if (work_done < budget) {
-+		napi_complete(napi);
-+		writel(readl_relaxed(HIF_INT_ENABLE) | HIF_RXPKT_INT,
-+		       HIF_INT_ENABLE);
-+	}
-+#ifdef HIF_NAPI_STATS
-+	else
-+		hif->napi_counters[NAPI_FULL_BUDGET_COUNT]++;
-+#endif
-+
-+	return work_done;
-+}
-+
-+/*
-+ * pfe_hif_init
-+ * This function initializes the baseaddresses and irq, etc.
-+ */
-+int pfe_hif_init(struct pfe *pfe)
-+{
-+	struct pfe_hif *hif = &pfe->hif;
-+	int err;
-+
-+	pr_info("%s\n", __func__);
-+
-+	hif->dev = pfe->dev;
-+	hif->irq = pfe->hif_irq;
-+
-+	err = pfe_hif_alloc_descr(hif);
-+	if (err)
-+		goto err0;
-+
-+	if (pfe_hif_init_buffers(hif)) {
-+		pr_err("%s: Could not initialize buffer descriptors\n"
-+			, __func__);
-+		err = -ENOMEM;
-+		goto err1;
-+	}
-+
-+	/* Initialize NAPI for Rx processing */
-+	init_dummy_netdev(&hif->dummy_dev);
-+	netif_napi_add(&hif->dummy_dev, &hif->napi, pfe_hif_rx_poll,
-+		       HIF_RX_POLL_WEIGHT);
-+	napi_enable(&hif->napi);
-+
-+	spin_lock_init(&hif->tx_lock);
-+	spin_lock_init(&hif->lock);
-+
-+	hif_init();
-+	hif_rx_enable();
-+	hif_tx_enable();
-+
-+	/* Disable tx done interrupt */
-+	writel(HIF_INT_MASK, HIF_INT_ENABLE);
-+
-+	gpi_enable(HGPI_BASE_ADDR);
-+
-+	err = request_irq(hif->irq, hif_isr, 0, "pfe_hif", hif);
-+	if (err) {
-+		pr_err("%s: failed to get the hif IRQ = %d\n",
-+		       __func__, hif->irq);
-+		goto err1;
-+	}
-+
-+	err = request_irq(pfe->wol_irq, wol_isr, 0, "pfe_wol", pfe);
-+	if (err) {
-+		pr_err("%s: failed to get the wol IRQ = %d\n",
-+		       __func__, pfe->wol_irq);
-+		goto err1;
-+	}
-+
-+	tasklet_init(&hif->tx_cleanup_tasklet,
-+		     (void(*)(unsigned long))pfe_tx_do_cleanup,
-+		     (unsigned long)hif);
-+
-+	return 0;
-+err1:
-+	pfe_hif_free_descr(hif);
-+err0:
-+	return err;
-+}
-+
-+/* pfe_hif_exit- */
-+void pfe_hif_exit(struct pfe *pfe)
-+{
-+	struct pfe_hif *hif = &pfe->hif;
-+
-+	pr_info("%s\n", __func__);
-+
-+	tasklet_kill(&hif->tx_cleanup_tasklet);
-+
-+	spin_lock_bh(&hif->lock);
-+	hif->shm->g_client_status[0] = 0;
-+	/* Make sure all clients are disabled*/
-+	hif->shm->g_client_status[1] = 0;
-+
-+	spin_unlock_bh(&hif->lock);
-+
-+	/*Disable Rx/Tx */
-+	gpi_disable(HGPI_BASE_ADDR);
-+	hif_rx_disable();
-+	hif_tx_disable();
-+
-+	napi_disable(&hif->napi);
-+	netif_napi_del(&hif->napi);
-+
-+	free_irq(pfe->wol_irq, pfe);
-+	free_irq(hif->irq, hif);
-+
-+	pfe_hif_release_buffers(hif);
-+	pfe_hif_free_descr(hif);
-+}
---- /dev/null
-+++ b/drivers/staging/fsl_ppfe/pfe_hif.h
-@@ -0,0 +1,199 @@
-+/* SPDX-License-Identifier: GPL-2.0+ */
-+/*
-+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
-+ * Copyright 2017 NXP
-+ */
-+
-+#ifndef _PFE_HIF_H_
-+#define _PFE_HIF_H_
-+
-+#include <linux/netdevice.h>
-+
-+#define HIF_NAPI_STATS
-+
-+#define HIF_CLIENT_QUEUES_MAX	16
-+#define HIF_RX_POLL_WEIGHT	64
-+
-+#define HIF_RX_PKT_MIN_SIZE 0x800 /* 2KB */
-+#define HIF_RX_PKT_MIN_SIZE_MASK ~(HIF_RX_PKT_MIN_SIZE - 1)
-+#define ROUND_MIN_RX_SIZE(_sz) (((_sz) + (HIF_RX_PKT_MIN_SIZE - 1)) \
-+					& HIF_RX_PKT_MIN_SIZE_MASK)
-+#define PRESENT_OFST_IN_PAGE(_buf) (((unsigned long int)(_buf) & (PAGE_SIZE \
-+					- 1)) & HIF_RX_PKT_MIN_SIZE_MASK)
-+
-+enum {
-+	NAPI_SCHED_COUNT = 0,
-+	NAPI_POLL_COUNT,
-+	NAPI_PACKET_COUNT,
-+	NAPI_DESC_COUNT,
-+	NAPI_FULL_BUDGET_COUNT,
-+	NAPI_CLIENT_FULL_COUNT,
-+	NAPI_MAX_COUNT
-+};
-+
-+/*
-+ * HIF_TX_DESC_NT value should be always greter than 4,
-+ * Otherwise HIF_TX_POLL_MARK will become zero.
-+ */
-+#define HIF_RX_DESC_NT		256
-+#define HIF_TX_DESC_NT		2048
-+
-+#define HIF_FIRST_BUFFER	BIT(0)
-+#define HIF_LAST_BUFFER		BIT(1)
-+#define HIF_DONT_DMA_MAP	BIT(2)
-+#define HIF_DATA_VALID		BIT(3)
-+#define HIF_TSO			BIT(4)
-+
-+enum {
-+	PFE_CL_GEM0 = 0,
-+	PFE_CL_GEM1,
-+	HIF_CLIENTS_MAX
-+};
-+
-+/*structure to store client queue info */
-+struct hif_rx_queue {
-+	struct rx_queue_desc *base;
-+	u32	size;
-+	u32	write_idx;
-+};
-+
-+struct hif_tx_queue {
-+	struct tx_queue_desc *base;
-+	u32	size;
-+	u32	ack_idx;
-+};
-+
-+/*Structure to store the client info */
-+struct hif_client {
-+	int	rx_qn;
-+	struct hif_rx_queue	rx_q[HIF_CLIENT_QUEUES_MAX];
-+	int	tx_qn;
-+	struct hif_tx_queue	tx_q[HIF_CLIENT_QUEUES_MAX];
-+};
-+
-+/*HIF hardware buffer descriptor */
-+struct hif_desc {
-+	u32 ctrl;
-+	u32 status;
-+	u32 data;
-+	u32 next;
-+};
-+
-+struct __hif_desc {
-+	u32 ctrl;
-+	u32 status;
-+	u32 data;
-+};
-+
-+struct hif_desc_sw {
-+	dma_addr_t data;
-+	u16 len;
-+	u8 client_id;
-+	u8 q_no;
-+	u16 flags;
-+};
-+
-+struct hif_hdr {
-+	u8 client_id;
-+	u8 q_num;
-+	u16 client_ctrl;
-+	u16 client_ctrl1;
-+};
-+
-+struct __hif_hdr {
-+	union {
-+		struct hif_hdr hdr;
-+		u32 word[2];
-+	};
-+};
-+
-+struct hif_ipsec_hdr {
-+	u16	sa_handle[2];
-+} __packed;
-+
-+/*  HIF_CTRL_TX... defines */
-+#define HIF_CTRL_TX_CHECKSUM		BIT(2)
-+
-+/*  HIF_CTRL_RX... defines */
-+#define HIF_CTRL_RX_OFFSET_OFST         (24)
-+#define HIF_CTRL_RX_CHECKSUMMED		BIT(2)
-+#define HIF_CTRL_RX_CONTINUED		BIT(1)
-+
-+struct pfe_hif {
-+	/* To store registered clients in hif layer */
-+	struct hif_client client[HIF_CLIENTS_MAX];
-+	struct hif_shm *shm;
-+	int	irq;
-+
-+	void	*descr_baseaddr_v;
-+	unsigned long	descr_baseaddr_p;
-+
-+	struct hif_desc *rx_base;
-+	u32	rx_ring_size;
-+	u32	rxtoclean_index;
-+	void	*rx_buf_addr[HIF_RX_DESC_NT];
-+	int	rx_buf_len[HIF_RX_DESC_NT];
-+	unsigned int qno;
-+	unsigned int client_id;
-+	unsigned int client_ctrl;
-+	unsigned int started;
-+
-+	struct hif_desc *tx_base;
-+	u32	tx_ring_size;
-+	u32	txtosend;
-+	u32	txtoclean;
-+	u32	txavail;
-+	u32	txtoflush;
-+	struct hif_desc_sw tx_sw_queue[HIF_TX_DESC_NT];
-+
-+/* tx_lock synchronizes hif packet tx as well as pfe_hif structure access */
-+	spinlock_t tx_lock;
-+/* lock synchronizes hif rx queue processing */
-+	spinlock_t lock;
-+	struct net_device	dummy_dev;
-+	struct napi_struct	napi;
-+	struct device *dev;
-+
-+#ifdef HIF_NAPI_STATS
-+	unsigned int napi_counters[NAPI_MAX_COUNT];
-+#endif
-+	struct tasklet_struct	tx_cleanup_tasklet;
-+};
-+
-+void __hif_xmit_pkt(struct pfe_hif *hif, unsigned int client_id, unsigned int
-+			q_no, void *data, u32 len, unsigned int flags);
-+int hif_xmit_pkt(struct pfe_hif *hif, unsigned int client_id, unsigned int q_no,
-+		 void *data, unsigned int len);
-+void __hif_tx_done_process(struct pfe_hif *hif, int count);
-+void hif_process_client_req(struct pfe_hif *hif, int req, int data1, int
-+				data2);
-+int pfe_hif_init(struct pfe *pfe);
-+void pfe_hif_exit(struct pfe *pfe);
-+void pfe_hif_rx_idle(struct pfe_hif *hif);
-+static inline void hif_tx_done_process(struct pfe_hif *hif, int count)
-+{
-+	spin_lock_bh(&hif->tx_lock);
-+	__hif_tx_done_process(hif, count);
-+	spin_unlock_bh(&hif->tx_lock);
-+}
-+
-+static inline void hif_tx_lock(struct pfe_hif *hif)
-+{
-+	spin_lock_bh(&hif->tx_lock);
-+}
-+
-+static inline void hif_tx_unlock(struct pfe_hif *hif)
-+{
-+	spin_unlock_bh(&hif->tx_lock);
-+}
-+
-+static inline int __hif_tx_avail(struct pfe_hif *hif)
-+{
-+	return hif->txavail;
-+}
-+
-+#define __memcpy8(dst, src)		memcpy(dst, src, 8)
-+#define __memcpy12(dst, src)		memcpy(dst, src, 12)
-+#define __memcpy(dst, src, len)		memcpy(dst, src, len)
-+
-+#endif /* _PFE_HIF_H_ */
---- /dev/null
-+++ b/drivers/staging/fsl_ppfe/pfe_hif_lib.c
-@@ -0,0 +1,628 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+/*
-+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
-+ * Copyright 2017 NXP
-+ */
-+
-+#include <linux/version.h>
-+#include <linux/kernel.h>
-+#include <linux/slab.h>
-+#include <linux/interrupt.h>
-+#include <linux/workqueue.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/dmapool.h>
-+#include <linux/sched.h>
-+#include <linux/skbuff.h>
-+#include <linux/moduleparam.h>
-+#include <linux/cpu.h>
-+
-+#include "pfe_mod.h"
-+#include "pfe_hif.h"
-+#include "pfe_hif_lib.h"
-+
-+unsigned int lro_mode;
-+unsigned int page_mode;
-+unsigned int tx_qos = 1;
-+module_param(tx_qos, uint, 0444);
-+MODULE_PARM_DESC(tx_qos, "0: disable ,\n"
-+			 "1: enable (default), guarantee no packet drop at TMU level\n");
-+unsigned int pfe_pkt_size;
-+unsigned int pfe_pkt_headroom;
-+unsigned int emac_txq_cnt;
-+
-+/*
-+ * @pfe_hal_lib.c.
-+ * Common functions used by HIF client drivers
-+ */
-+
-+/*HIF shared memory Global variable */
-+struct hif_shm ghif_shm;
-+
-+/* Cleanup the HIF shared memory, release HIF rx_buffer_pool.
-+ * This function should be called after pfe_hif_exit
-+ *
-+ * @param[in] hif_shm		Shared memory address location in DDR
-+ */
-+static void pfe_hif_shm_clean(struct hif_shm *hif_shm)
-+{
-+	int i;
-+	void *pkt;
-+
-+	for (i = 0; i < hif_shm->rx_buf_pool_cnt; i++) {
-+		pkt = hif_shm->rx_buf_pool[i];
-+		if (pkt) {
-+			hif_shm->rx_buf_pool[i] = NULL;
-+			pkt -= pfe_pkt_headroom;
-+
-+			if (page_mode)
-+				put_page(virt_to_page(pkt));
-+			else
-+				kfree(pkt);
-+		}
-+	}
-+}
-+
-+/* Initialize shared memory used between HIF driver and clients,
-+ * allocate rx_buffer_pool required for HIF Rx descriptors.
-+ * This function should be called before initializing HIF driver.
-+ *
-+ * @param[in] hif_shm		Shared memory address location in DDR
-+ * @rerurn			0 - on succes, <0 on fail to initialize
-+ */
-+static int pfe_hif_shm_init(struct hif_shm *hif_shm)
-+{
-+	int i;
-+	void *pkt;
-+
-+	memset(hif_shm, 0, sizeof(struct hif_shm));
-+	hif_shm->rx_buf_pool_cnt = HIF_RX_DESC_NT;
-+
-+	for (i = 0; i < hif_shm->rx_buf_pool_cnt; i++) {
-+		if (page_mode) {
-+			pkt = (void *)__get_free_page(GFP_KERNEL |
-+				GFP_DMA_PFE);
-+		} else {
-+			pkt = kmalloc(PFE_BUF_SIZE, GFP_KERNEL | GFP_DMA_PFE);
-+		}
-+
-+		if (pkt)
-+			hif_shm->rx_buf_pool[i] = pkt + pfe_pkt_headroom;
-+		else
-+			goto err0;
-+	}
-+
-+	return 0;
-+
-+err0:
-+	pr_err("%s Low memory\n", __func__);
-+	pfe_hif_shm_clean(hif_shm);
-+	return -ENOMEM;
-+}
-+
-+/*This function sends indication to HIF driver
-+ *
-+ * @param[in] hif	hif context
-+ */
-+static void hif_lib_indicate_hif(struct pfe_hif *hif, int req, int data1, int
-+					data2)
-+{
-+	hif_process_client_req(hif, req, data1, data2);
-+}
-+
-+void hif_lib_indicate_client(int client_id, int event_type, int qno)
-+{
-+	struct hif_client_s *client = pfe->hif_client[client_id];
-+
-+	if (!client || (event_type >= HIF_EVENT_MAX) || (qno >=
-+		HIF_CLIENT_QUEUES_MAX))
-+		return;
-+
-+	if (!test_and_set_bit(qno, &client->queue_mask[event_type]))
-+		client->event_handler(client->priv, event_type, qno);
-+}
-+
-+/*This function releases Rx queue descriptors memory and pre-filled buffers
-+ *
-+ * @param[in] client	hif_client context
-+ */
-+static void hif_lib_client_release_rx_buffers(struct hif_client_s *client)
-+{
-+	struct rx_queue_desc *desc;
-+	int qno, ii;
-+	void *buf;
-+
-+	for (qno = 0; qno < client->rx_qn; qno++) {
-+		desc = client->rx_q[qno].base;
-+
-+		for (ii = 0; ii < client->rx_q[qno].size; ii++) {
-+			buf = (void *)desc->data;
-+			if (buf) {
-+				buf -= pfe_pkt_headroom;
-+
-+				if (page_mode)
-+					free_page((unsigned long)buf);
-+				else
-+					kfree(buf);
-+
-+				desc->ctrl = 0;
-+			}
-+
-+			desc++;
-+		}
-+	}
-+
-+	kfree(client->rx_qbase);
-+}
-+
-+/*This function allocates memory for the rxq descriptors and pre-fill rx queues
-+ * with buffers.
-+ * @param[in] client	client context
-+ * @param[in] q_size	size of the rxQ, all queues are of same size
-+ */
-+static int hif_lib_client_init_rx_buffers(struct hif_client_s *client, int
-+						q_size)
-+{
-+	struct rx_queue_desc *desc;
-+	struct hif_client_rx_queue *queue;
-+	int ii, qno;
-+
-+	/*Allocate memory for the client queues */
-+	client->rx_qbase = kzalloc(client->rx_qn * q_size * sizeof(struct
-+				rx_queue_desc), GFP_KERNEL);
-+	if (!client->rx_qbase)
-+		goto err;
-+
-+	for (qno = 0; qno < client->rx_qn; qno++) {
-+		queue = &client->rx_q[qno];
-+
-+		queue->base = client->rx_qbase + qno * q_size * sizeof(struct
-+				rx_queue_desc);
-+		queue->size = q_size;
-+		queue->read_idx = 0;
-+		queue->write_idx = 0;
-+
-+		pr_debug("rx queue: %d, base: %p, size: %d\n", qno,
-+			 queue->base, queue->size);
-+	}
-+
-+	for (qno = 0; qno < client->rx_qn; qno++) {
-+		queue = &client->rx_q[qno];
-+		desc = queue->base;
-+
-+		for (ii = 0; ii < queue->size; ii++) {
-+			desc->ctrl = CL_DESC_BUF_LEN(pfe_pkt_size) |
-+					CL_DESC_OWN;
-+			desc++;
-+		}
-+	}
-+
-+	return 0;
-+
-+err:
-+	return 1;
-+}
-+
-+
-+static void hif_lib_client_cleanup_tx_queue(struct hif_client_tx_queue *queue)
-+{
-+	pr_debug("%s\n", __func__);
-+
-+	/*
-+	 * Check if there are any pending packets. Client must flush the tx
-+	 * queues before unregistering, by calling by calling
-+	 * hif_lib_tx_get_next_complete()
-+	 *
-+	 * Hif no longer calls since we are no longer registered
-+	 */
-+	if (queue->tx_pending)
-+		pr_err("%s: pending transmit packets\n", __func__);
-+}
-+
-+static void hif_lib_client_release_tx_buffers(struct hif_client_s *client)
-+{
-+	int qno;
-+
-+	pr_debug("%s\n", __func__);
-+
-+	for (qno = 0; qno < client->tx_qn; qno++)
-+		hif_lib_client_cleanup_tx_queue(&client->tx_q[qno]);
-+
-+	kfree(client->tx_qbase);
-+}
-+
-+static int hif_lib_client_init_tx_buffers(struct hif_client_s *client, int
-+						q_size)
-+{
-+	struct hif_client_tx_queue *queue;
-+	int qno;
-+
-+	client->tx_qbase = kzalloc(client->tx_qn * q_size * sizeof(struct
-+					tx_queue_desc), GFP_KERNEL);
-+	if (!client->tx_qbase)
-+		return 1;
-+
-+	for (qno = 0; qno < client->tx_qn; qno++) {
-+		queue = &client->tx_q[qno];
-+
-+		queue->base = client->tx_qbase + qno * q_size * sizeof(struct
-+				tx_queue_desc);
-+		queue->size = q_size;
-+		queue->read_idx = 0;
-+		queue->write_idx = 0;
-+		queue->tx_pending = 0;
-+		queue->nocpy_flag = 0;
-+		queue->prev_tmu_tx_pkts = 0;
-+		queue->done_tmu_tx_pkts = 0;
-+
-+		pr_debug("tx queue: %d, base: %p, size: %d\n", qno,
-+			 queue->base, queue->size);
-+	}
-+
-+	return 0;
-+}
-+
-+static int hif_lib_event_dummy(void *priv, int event_type, int qno)
-+{
-+	return 0;
-+}
-+
-+int hif_lib_client_register(struct hif_client_s *client)
-+{
-+	struct hif_shm *hif_shm;
-+	struct hif_client_shm *client_shm;
-+	int err, i;
-+	/* int loop_cnt = 0; */
-+
-+	pr_debug("%s\n", __func__);
-+
-+	/*Allocate memory before spin_lock*/
-+	if (hif_lib_client_init_rx_buffers(client, client->rx_qsize)) {
-+		err = -ENOMEM;
-+		goto err_rx;
-+	}
-+
-+	if (hif_lib_client_init_tx_buffers(client, client->tx_qsize)) {
-+		err = -ENOMEM;
-+		goto err_tx;
-+	}
-+
-+	spin_lock_bh(&pfe->hif.lock);
-+	if (!(client->pfe) || (client->id >= HIF_CLIENTS_MAX) ||
-+	    (pfe->hif_client[client->id])) {
-+		err = -EINVAL;
-+		goto err;
-+	}
-+
-+	hif_shm = client->pfe->hif.shm;
-+
-+	if (!client->event_handler)
-+		client->event_handler = hif_lib_event_dummy;
-+
-+	/*Initialize client specific shared memory */
-+	client_shm = (struct hif_client_shm *)&hif_shm->client[client->id];
-+	client_shm->rx_qbase = (unsigned long int)client->rx_qbase;
-+	client_shm->rx_qsize = client->rx_qsize;
-+	client_shm->tx_qbase = (unsigned long int)client->tx_qbase;
-+	client_shm->tx_qsize = client->tx_qsize;
-+	client_shm->ctrl = (client->tx_qn << CLIENT_CTRL_TX_Q_CNT_OFST) |
-+				(client->rx_qn << CLIENT_CTRL_RX_Q_CNT_OFST);
-+	/* spin_lock_init(&client->rx_lock); */
-+
-+	for (i = 0; i < HIF_EVENT_MAX; i++) {
-+		client->queue_mask[i] = 0;  /*
-+					     * By default all events are
-+					     * unmasked
-+					     */
-+	}
-+
-+	/*Indicate to HIF driver*/
-+	hif_lib_indicate_hif(&pfe->hif, REQUEST_CL_REGISTER, client->id, 0);
-+
-+	pr_debug("%s: client: %p, client_id: %d, tx_qsize: %d, rx_qsize: %d\n",
-+		 __func__, client, client->id, client->tx_qsize,
-+		 client->rx_qsize);
-+
-+	client->cpu_id = -1;
-+
-+	pfe->hif_client[client->id] = client;
-+	spin_unlock_bh(&pfe->hif.lock);
-+
-+	return 0;
-+
-+err:
-+	spin_unlock_bh(&pfe->hif.lock);
-+	hif_lib_client_release_tx_buffers(client);
-+
-+err_tx:
-+	hif_lib_client_release_rx_buffers(client);
-+
-+err_rx:
-+	return err;
-+}
-+
-+int hif_lib_client_unregister(struct hif_client_s *client)
-+{
-+	struct pfe *pfe = client->pfe;
-+	u32 client_id = client->id;
-+
-+	pr_info(
-+		"%s : client: %p, client_id: %d, txQ_depth: %d, rxQ_depth: %d\n"
-+		, __func__, client, client->id, client->tx_qsize,
-+		client->rx_qsize);
-+
-+	spin_lock_bh(&pfe->hif.lock);
-+	hif_lib_indicate_hif(&pfe->hif, REQUEST_CL_UNREGISTER, client->id, 0);
-+
-+	hif_lib_client_release_tx_buffers(client);
-+	hif_lib_client_release_rx_buffers(client);
-+	pfe->hif_client[client_id] = NULL;
-+	spin_unlock_bh(&pfe->hif.lock);
-+
-+	return 0;
-+}
-+
-+int hif_lib_event_handler_start(struct hif_client_s *client, int event,
-+				int qno)
-+{
-+	struct hif_client_rx_queue *queue = &client->rx_q[qno];
-+	struct rx_queue_desc *desc = queue->base + queue->read_idx;
-+
-+	if ((event >= HIF_EVENT_MAX) || (qno >= HIF_CLIENT_QUEUES_MAX)) {
-+		pr_debug("%s: Unsupported event : %d  queue number : %d\n",
-+			 __func__, event, qno);
-+		return -1;
-+	}
-+
-+	test_and_clear_bit(qno, &client->queue_mask[event]);
-+
-+	switch (event) {
-+	case EVENT_RX_PKT_IND:
-+		if (!(desc->ctrl & CL_DESC_OWN))
-+			hif_lib_indicate_client(client->id,
-+						EVENT_RX_PKT_IND, qno);
-+		break;
-+
-+	case EVENT_HIGH_RX_WM:
-+	case EVENT_TXDONE_IND:
-+	default:
-+		break;
-+	}
-+
-+	return 0;
-+}
-+
-+/*
-+ * This function gets one packet from the specified client queue
-+ * It also refill the rx buffer
-+ */
-+void *hif_lib_receive_pkt(struct hif_client_s *client, int qno, int *len, int
-+				*ofst, unsigned int *rx_ctrl,
-+				unsigned int *desc_ctrl, void **priv_data)
-+{
-+	struct hif_client_rx_queue *queue = &client->rx_q[qno];
-+	struct rx_queue_desc *desc;
-+	void *pkt = NULL;
-+
-+	/*
-+	 * Following lock is to protect rx queue access from,
-+	 * hif_lib_event_handler_start.
-+	 * In general below lock is not required, because hif_lib_xmit_pkt and
-+	 * hif_lib_event_handler_start are called from napi poll and which is
-+	 * not re-entrant. But if some client use in different way this lock is
-+	 * required.
-+	 */
-+	/*spin_lock_irqsave(&client->rx_lock, flags); */
-+	desc = queue->base + queue->read_idx;
-+	if (!(desc->ctrl & CL_DESC_OWN)) {
-+		pkt = desc->data - pfe_pkt_headroom;
-+
-+		*rx_ctrl = desc->client_ctrl;
-+		*desc_ctrl = desc->ctrl;
-+
-+		if (desc->ctrl & CL_DESC_FIRST) {
-+			u16 size = *rx_ctrl >> HIF_CTRL_RX_OFFSET_OFST;
-+
-+			if (size) {
-+				size += PFE_PARSE_INFO_SIZE;
-+				*len = CL_DESC_BUF_LEN(desc->ctrl) -
-+						PFE_PKT_HEADER_SZ - size;
-+				*ofst = pfe_pkt_headroom + PFE_PKT_HEADER_SZ
-+								+ size;
-+				*priv_data = desc->data + PFE_PKT_HEADER_SZ;
-+			} else {
-+				*len = CL_DESC_BUF_LEN(desc->ctrl) -
-+				       PFE_PKT_HEADER_SZ - PFE_PARSE_INFO_SIZE;
-+				*ofst = pfe_pkt_headroom
-+					+ PFE_PKT_HEADER_SZ
-+					+ PFE_PARSE_INFO_SIZE;
-+				*priv_data = NULL;
-+			}
-+
-+		} else {
-+			*len = CL_DESC_BUF_LEN(desc->ctrl);
-+			*ofst = pfe_pkt_headroom;
-+		}
-+
-+		/*
-+		 * Needed so we don't free a buffer/page
-+		 * twice on module_exit
-+		 */
-+		desc->data = NULL;
-+
-+		/*
-+		 * Ensure everything else is written to DDR before
-+		 * writing bd->ctrl
-+		 */
-+		smp_wmb();
-+
-+		desc->ctrl = CL_DESC_BUF_LEN(pfe_pkt_size) | CL_DESC_OWN;
-+		queue->read_idx = (queue->read_idx + 1) & (queue->size - 1);
-+	}
-+
-+	/*spin_unlock_irqrestore(&client->rx_lock, flags); */
-+	return pkt;
-+}
-+
-+static inline void hif_hdr_write(struct hif_hdr *pkt_hdr, unsigned int
-+					client_id, unsigned int qno,
-+					u32 client_ctrl)
-+{
-+	/* Optimize the write since the destinaton may be non-cacheable */
-+	if (!((unsigned long)pkt_hdr & 0x3)) {
-+		((u32 *)pkt_hdr)[0] = (client_ctrl << 16) | (qno << 8) |
-+					client_id;
-+	} else {
-+		((u16 *)pkt_hdr)[0] = (qno << 8) | (client_id & 0xFF);
-+		((u16 *)pkt_hdr)[1] = (client_ctrl & 0xFFFF);
-+	}
-+}
-+
-+/*This function puts the given packet in the specific client queue */
-+void __hif_lib_xmit_pkt(struct hif_client_s *client, unsigned int qno, void
-+				*data, unsigned int len, u32 client_ctrl,
-+				unsigned int flags, void *client_data)
-+{
-+	struct hif_client_tx_queue *queue = &client->tx_q[qno];
-+	struct tx_queue_desc *desc = queue->base + queue->write_idx;
-+
-+	/* First buffer */
-+	if (flags & HIF_FIRST_BUFFER) {
-+		data -= sizeof(struct hif_hdr);
-+		len += sizeof(struct hif_hdr);
-+
-+		hif_hdr_write(data, client->id, qno, client_ctrl);
-+	}
-+
-+	desc->data = client_data;
-+	desc->ctrl = CL_DESC_OWN | CL_DESC_FLAGS(flags);
-+
-+	__hif_xmit_pkt(&pfe->hif, client->id, qno, data, len, flags);
-+
-+	queue->write_idx = (queue->write_idx + 1) & (queue->size - 1);
-+	queue->tx_pending++;
-+	queue->jiffies_last_packet = jiffies;
-+}
-+
-+void *hif_lib_tx_get_next_complete(struct hif_client_s *client, int qno,
-+				   unsigned int *flags, int count)
-+{
-+	struct hif_client_tx_queue *queue = &client->tx_q[qno];
-+	struct tx_queue_desc *desc = queue->base + queue->read_idx;
-+
-+	pr_debug("%s: qno : %d rd_indx: %d pending:%d\n", __func__, qno,
-+		 queue->read_idx, queue->tx_pending);
-+
-+	if (!queue->tx_pending)
-+		return NULL;
-+
-+	if (queue->nocpy_flag && !queue->done_tmu_tx_pkts) {
-+		u32 tmu_tx_pkts = be32_to_cpu(pe_dmem_read(TMU0_ID +
-+			client->id, TMU_DM_TX_TRANS, 4));
-+
-+		if (queue->prev_tmu_tx_pkts > tmu_tx_pkts)
-+			queue->done_tmu_tx_pkts = UINT_MAX -
-+				queue->prev_tmu_tx_pkts + tmu_tx_pkts;
-+		else
-+			queue->done_tmu_tx_pkts = tmu_tx_pkts -
-+						queue->prev_tmu_tx_pkts;
-+
-+		queue->prev_tmu_tx_pkts  = tmu_tx_pkts;
-+
-+		if (!queue->done_tmu_tx_pkts)
-+			return NULL;
-+	}
-+
-+	if (desc->ctrl & CL_DESC_OWN)
-+		return NULL;
-+
-+	queue->read_idx = (queue->read_idx + 1) & (queue->size - 1);
-+	queue->tx_pending--;
-+
-+	*flags = CL_DESC_GET_FLAGS(desc->ctrl);
-+
-+	if (queue->done_tmu_tx_pkts && (*flags & HIF_LAST_BUFFER))
-+		queue->done_tmu_tx_pkts--;
-+
-+	return desc->data;
-+}
-+
-+static void hif_lib_tmu_credit_init(struct pfe *pfe)
-+{
-+	int i, q;
-+
-+	for (i = 0; i < NUM_GEMAC_SUPPORT; i++)
-+		for (q = 0; q < emac_txq_cnt; q++) {
-+			pfe->tmu_credit.tx_credit_max[i][q] = (q == 0) ?
-+					DEFAULT_Q0_QDEPTH : DEFAULT_MAX_QDEPTH;
-+			pfe->tmu_credit.tx_credit[i][q] =
-+					pfe->tmu_credit.tx_credit_max[i][q];
-+		}
-+}
-+
-+/* __hif_lib_update_credit
-+ *
-+ * @param[in] client	hif client context
-+ * @param[in] queue	queue number in match with TMU
-+ */
-+void __hif_lib_update_credit(struct hif_client_s *client, unsigned int queue)
-+{
-+	unsigned int tmu_tx_packets, tmp;
-+
-+	if (tx_qos) {
-+		tmu_tx_packets = be32_to_cpu(pe_dmem_read(TMU0_ID +
-+			client->id, (TMU_DM_TX_TRANS + (queue * 4)), 4));
-+
-+		/* tx_packets counter overflowed */
-+		if (tmu_tx_packets >
-+		    pfe->tmu_credit.tx_packets[client->id][queue]) {
-+			tmp = UINT_MAX - tmu_tx_packets +
-+			pfe->tmu_credit.tx_packets[client->id][queue];
-+
-+			pfe->tmu_credit.tx_credit[client->id][queue] =
-+			pfe->tmu_credit.tx_credit_max[client->id][queue] - tmp;
-+		} else {
-+		/* TMU tx <= pfe_eth tx, normal case or both OF since
-+		 * last time
-+		 */
-+			pfe->tmu_credit.tx_credit[client->id][queue] =
-+			pfe->tmu_credit.tx_credit_max[client->id][queue] -
-+			(pfe->tmu_credit.tx_packets[client->id][queue] -
-+			tmu_tx_packets);
-+		}
-+	}
-+}
-+
-+int pfe_hif_lib_init(struct pfe *pfe)
-+{
-+	int rc;
-+
-+	pr_info("%s\n", __func__);
-+
-+	if (lro_mode) {
-+		page_mode = 1;
-+		pfe_pkt_size = min(PAGE_SIZE, MAX_PFE_PKT_SIZE);
-+		pfe_pkt_headroom = 0;
-+	} else {
-+		page_mode = 0;
-+		pfe_pkt_size = PFE_PKT_SIZE;
-+		pfe_pkt_headroom = PFE_PKT_HEADROOM;
-+	}
-+
-+	if (tx_qos)
-+		emac_txq_cnt = EMAC_TXQ_CNT / 2;
-+	else
-+		emac_txq_cnt = EMAC_TXQ_CNT;
-+
-+	hif_lib_tmu_credit_init(pfe);
-+	pfe->hif.shm = &ghif_shm;
-+	rc = pfe_hif_shm_init(pfe->hif.shm);
-+
-+	return rc;
-+}
-+
-+void pfe_hif_lib_exit(struct pfe *pfe)
-+{
-+	pr_info("%s\n", __func__);
-+
-+	pfe_hif_shm_clean(pfe->hif.shm);
-+}
---- /dev/null
-+++ b/drivers/staging/fsl_ppfe/pfe_hif_lib.h
-@@ -0,0 +1,229 @@
-+/* SPDX-License-Identifier: GPL-2.0+ */
-+/*
-+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
-+ * Copyright 2017 NXP
-+ */
-+
-+#ifndef _PFE_HIF_LIB_H_
-+#define _PFE_HIF_LIB_H_
-+
-+#include "pfe_hif.h"
-+
-+#define HIF_CL_REQ_TIMEOUT	10
-+#define GFP_DMA_PFE 0
-+#define PFE_PARSE_INFO_SIZE	16
-+
-+enum {
-+	REQUEST_CL_REGISTER = 0,
-+	REQUEST_CL_UNREGISTER,
-+	HIF_REQUEST_MAX
-+};
-+
-+enum {
-+	/* Event to indicate that client rx queue is reached water mark level */
-+	EVENT_HIGH_RX_WM = 0,
-+	/* Event to indicate that, packet received for client */
-+	EVENT_RX_PKT_IND,
-+	/* Event to indicate that, packet tx done for client */
-+	EVENT_TXDONE_IND,
-+	HIF_EVENT_MAX
-+};
-+
-+/*structure to store client queue info */
-+
-+/*structure to store client queue info */
-+struct hif_client_rx_queue {
-+	struct rx_queue_desc *base;
-+	u32	size;
-+	u32	read_idx;
-+	u32	write_idx;
-+};
-+
-+struct hif_client_tx_queue {
-+	struct tx_queue_desc *base;
-+	u32	size;
-+	u32	read_idx;
-+	u32	write_idx;
-+	u32	tx_pending;
-+	unsigned long jiffies_last_packet;
-+	u32	nocpy_flag;
-+	u32	prev_tmu_tx_pkts;
-+	u32	done_tmu_tx_pkts;
-+};
-+
-+struct hif_client_s {
-+	int	id;
-+	int	tx_qn;
-+	int	rx_qn;
-+	void	*rx_qbase;
-+	void	*tx_qbase;
-+	int	tx_qsize;
-+	int	rx_qsize;
-+	int	cpu_id;
-+	struct hif_client_tx_queue tx_q[HIF_CLIENT_QUEUES_MAX];
-+	struct hif_client_rx_queue rx_q[HIF_CLIENT_QUEUES_MAX];
-+	int (*event_handler)(void *priv, int event, int data);
-+	unsigned long queue_mask[HIF_EVENT_MAX];
-+	struct pfe *pfe;
-+	void *priv;
-+};
-+
-+/*
-+ * Client specific shared memory
-+ * It contains number of Rx/Tx queues, base addresses and queue sizes
-+ */
-+struct hif_client_shm {
-+	u32 ctrl; /*0-7: number of Rx queues, 8-15: number of tx queues */
-+	unsigned long rx_qbase; /*Rx queue base address */
-+	u32 rx_qsize; /*each Rx queue size, all Rx queues are of same size */
-+	unsigned long tx_qbase; /* Tx queue base address */
-+	u32 tx_qsize; /*each Tx queue size, all Tx queues are of same size */
-+};
-+
-+/*Client shared memory ctrl bit description */
-+#define CLIENT_CTRL_RX_Q_CNT_OFST	0
-+#define CLIENT_CTRL_TX_Q_CNT_OFST	8
-+#define CLIENT_CTRL_RX_Q_CNT(ctrl)	(((ctrl) >> CLIENT_CTRL_RX_Q_CNT_OFST) \
-+						& 0xFF)
-+#define CLIENT_CTRL_TX_Q_CNT(ctrl)	(((ctrl) >> CLIENT_CTRL_TX_Q_CNT_OFST) \
-+						& 0xFF)
-+
-+/*
-+ * Shared memory used to communicate between HIF driver and host/client drivers
-+ * Before starting the hif driver rx_buf_pool ans rx_buf_pool_cnt should be
-+ * initialized with host buffers and buffers count in the pool.
-+ * rx_buf_pool_cnt should be >= HIF_RX_DESC_NT.
-+ *
-+ */
-+struct hif_shm {
-+	u32 rx_buf_pool_cnt; /*Number of rx buffers available*/
-+	/*Rx buffers required to initialize HIF rx descriptors */
-+	void *rx_buf_pool[HIF_RX_DESC_NT];
-+	unsigned long g_client_status[2]; /*Global client status bit mask */
-+	/* Client specific shared memory */
-+	struct hif_client_shm client[HIF_CLIENTS_MAX];
-+};
-+
-+#define CL_DESC_OWN	BIT(31)
-+/* This sets owner ship to HIF driver */
-+#define CL_DESC_LAST	BIT(30)
-+/* This indicates last packet for multi buffers handling */
-+#define CL_DESC_FIRST	BIT(29)
-+/* This indicates first packet for multi buffers handling */
-+
-+#define CL_DESC_BUF_LEN(x)		((x) & 0xFFFF)
-+#define CL_DESC_FLAGS(x)		(((x) & 0xF) << 16)
-+#define CL_DESC_GET_FLAGS(x)		(((x) >> 16) & 0xF)
-+
-+struct rx_queue_desc {
-+	void *data;
-+	u32	ctrl; /*0-15bit len, 16-20bit flags, 31bit owner*/
-+	u32	client_ctrl;
-+};
-+
-+struct tx_queue_desc {
-+	void *data;
-+	u32	ctrl; /*0-15bit len, 16-20bit flags, 31bit owner*/
-+};
-+
-+/* HIF Rx is not working properly for 2-byte aligned buffers and
-+ * ip_header should be 4byte aligned for better iperformance.
-+ * "ip_header = 64 + 6(hif_header) + 14 (MAC Header)" will be 4byte aligned.
-+ */
-+#define PFE_PKT_HEADER_SZ	sizeof(struct hif_hdr)
-+/* must be big enough for headroom, pkt size and skb shared info */
-+#define PFE_BUF_SIZE		2048
-+#define PFE_PKT_HEADROOM	128
-+
-+#define SKB_SHARED_INFO_SIZE   SKB_DATA_ALIGN(sizeof(struct skb_shared_info))
-+#define PFE_PKT_SIZE		(PFE_BUF_SIZE - PFE_PKT_HEADROOM \
-+				 - SKB_SHARED_INFO_SIZE)
-+#define MAX_L2_HDR_SIZE		14	/* Not correct for VLAN/PPPoE */
-+#define MAX_L3_HDR_SIZE		20	/* Not correct for IPv6 */
-+#define MAX_L4_HDR_SIZE		60	/* TCP with maximum options */
-+#define MAX_HDR_SIZE		(MAX_L2_HDR_SIZE + MAX_L3_HDR_SIZE \
-+				 + MAX_L4_HDR_SIZE)
-+/* Used in page mode to clamp packet size to the maximum supported by the hif
-+ *hw interface (<16KiB)
-+ */
-+#define MAX_PFE_PKT_SIZE	16380UL
-+
-+extern unsigned int pfe_pkt_size;
-+extern unsigned int pfe_pkt_headroom;
-+extern unsigned int page_mode;
-+extern unsigned int lro_mode;
-+extern unsigned int tx_qos;
-+extern unsigned int emac_txq_cnt;
-+
-+int pfe_hif_lib_init(struct pfe *pfe);
-+void pfe_hif_lib_exit(struct pfe *pfe);
-+int hif_lib_client_register(struct hif_client_s *client);
-+int hif_lib_client_unregister(struct  hif_client_s *client);
-+void __hif_lib_xmit_pkt(struct hif_client_s *client, unsigned int qno, void
-+				*data, unsigned int len, u32 client_ctrl,
-+				unsigned int flags, void *client_data);
-+int hif_lib_xmit_pkt(struct hif_client_s *client, unsigned int qno, void *data,
-+		     unsigned int len, u32 client_ctrl, void *client_data);
-+void hif_lib_indicate_client(int cl_id, int event, int data);
-+int hif_lib_event_handler_start(struct hif_client_s *client, int event, int
-+					data);
-+int hif_lib_tmu_queue_start(struct hif_client_s *client, int qno);
-+int hif_lib_tmu_queue_stop(struct hif_client_s *client, int qno);
-+void *hif_lib_tx_get_next_complete(struct hif_client_s *client, int qno,
-+				   unsigned int *flags, int count);
-+void *hif_lib_receive_pkt(struct hif_client_s *client, int qno, int *len, int
-+				*ofst, unsigned int *rx_ctrl,
-+				unsigned int *desc_ctrl, void **priv_data);
-+void __hif_lib_update_credit(struct hif_client_s *client, unsigned int queue);
-+void hif_lib_set_rx_cpu_affinity(struct hif_client_s *client, int cpu_id);
-+void hif_lib_set_tx_queue_nocpy(struct hif_client_s *client, int qno, int
-+					enable);
-+static inline int hif_lib_tx_avail(struct hif_client_s *client, unsigned int
-+					qno)
-+{
-+	struct hif_client_tx_queue *queue = &client->tx_q[qno];
-+
-+	return (queue->size - queue->tx_pending);
-+}
-+
-+static inline int hif_lib_get_tx_wr_index(struct hif_client_s *client, unsigned
-+						int qno)
-+{
-+	struct hif_client_tx_queue *queue = &client->tx_q[qno];
-+
-+	return queue->write_idx;
-+}
-+
-+static inline int hif_lib_tx_pending(struct hif_client_s *client, unsigned int
-+					qno)
-+{
-+	struct hif_client_tx_queue *queue = &client->tx_q[qno];
-+
-+	return queue->tx_pending;
-+}
-+
-+#define hif_lib_tx_credit_avail(pfe, id, qno) \
-+				((pfe)->tmu_credit.tx_credit[id][qno])
-+
-+#define hif_lib_tx_credit_max(pfe, id, qno) \
-+				((pfe)->tmu_credit.tx_credit_max[id][qno])
-+
-+/*
-+ * Test comment
-+ */
-+#define hif_lib_tx_credit_use(pfe, id, qno, credit)			\
-+	({ typeof(pfe) pfe_ = pfe;					\
-+		typeof(id) id_ = id;					\
-+		typeof(qno) qno_ = qno;					\
-+		typeof(credit) credit_ = credit;			\
-+		do {							\
-+			if (tx_qos) {					\
-+				(pfe_)->tmu_credit.tx_credit[id_][qno_]\
-+					 -= credit_;			\
-+				(pfe_)->tmu_credit.tx_packets[id_][qno_]\
-+					+= credit_;			\
-+			}						\
-+		} while (0);						\
-+	})
-+
-+#endif /* _PFE_HIF_LIB_H_ */
---- /dev/null
-+++ b/drivers/staging/fsl_ppfe/pfe_hw.c
-@@ -0,0 +1,164 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+/*
-+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
-+ * Copyright 2017 NXP
-+ */
-+
-+#include "pfe_mod.h"
-+#include "pfe_hw.h"
-+
-+/* Functions to handle most of pfe hw register initialization */
-+int pfe_hw_init(struct pfe *pfe, int resume)
-+{
-+	struct class_cfg class_cfg = {
-+		.pe_sys_clk_ratio = PE_SYS_CLK_RATIO,
-+		.route_table_baseaddr = pfe->ddr_phys_baseaddr +
-+					ROUTE_TABLE_BASEADDR,
-+		.route_table_hash_bits = ROUTE_TABLE_HASH_BITS,
-+	};
-+
-+	struct tmu_cfg tmu_cfg = {
-+		.pe_sys_clk_ratio = PE_SYS_CLK_RATIO,
-+		.llm_base_addr = pfe->ddr_phys_baseaddr + TMU_LLM_BASEADDR,
-+		.llm_queue_len = TMU_LLM_QUEUE_LEN,
-+	};
-+
-+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
-+	struct util_cfg util_cfg = {
-+		.pe_sys_clk_ratio = PE_SYS_CLK_RATIO,
-+	};
-+#endif
-+
-+	struct BMU_CFG bmu1_cfg = {
-+		.baseaddr = CBUS_VIRT_TO_PFE(LMEM_BASE_ADDR +
-+						BMU1_LMEM_BASEADDR),
-+		.count = BMU1_BUF_COUNT,
-+		.size = BMU1_BUF_SIZE,
-+		.low_watermark = 10,
-+		.high_watermark = 15,
-+	};
-+
-+	struct BMU_CFG bmu2_cfg = {
-+		.baseaddr = DDR_PHYS_TO_PFE(pfe->ddr_phys_baseaddr +
-+						BMU2_DDR_BASEADDR),
-+		.count = BMU2_BUF_COUNT,
-+		.size = BMU2_BUF_SIZE,
-+		.low_watermark = 250,
-+		.high_watermark = 253,
-+	};
-+
-+	struct gpi_cfg egpi1_cfg = {
-+		.lmem_rtry_cnt = EGPI1_LMEM_RTRY_CNT,
-+		.tmlf_txthres = EGPI1_TMLF_TXTHRES,
-+		.aseq_len = EGPI1_ASEQ_LEN,
-+		.mtip_pause_reg = CBUS_VIRT_TO_PFE(EMAC1_BASE_ADDR +
-+						EMAC_TCNTRL_REG),
-+	};
-+
-+	struct gpi_cfg egpi2_cfg = {
-+		.lmem_rtry_cnt = EGPI2_LMEM_RTRY_CNT,
-+		.tmlf_txthres = EGPI2_TMLF_TXTHRES,
-+		.aseq_len = EGPI2_ASEQ_LEN,
-+		.mtip_pause_reg = CBUS_VIRT_TO_PFE(EMAC2_BASE_ADDR +
-+						EMAC_TCNTRL_REG),
-+	};
-+
-+	struct gpi_cfg hgpi_cfg = {
-+		.lmem_rtry_cnt = HGPI_LMEM_RTRY_CNT,
-+		.tmlf_txthres = HGPI_TMLF_TXTHRES,
-+		.aseq_len = HGPI_ASEQ_LEN,
-+		.mtip_pause_reg = 0,
-+	};
-+
-+	pr_info("%s\n", __func__);
-+
-+#if !defined(LS1012A_PFE_RESET_WA)
-+	/* LS1012A needs this to make PE work correctly */
-+	writel(0x3,     CLASS_PE_SYS_CLK_RATIO);
-+	writel(0x3,     TMU_PE_SYS_CLK_RATIO);
-+	writel(0x3,     UTIL_PE_SYS_CLK_RATIO);
-+	usleep_range(10, 20);
-+#endif
-+
-+	pr_info("CLASS version: %x\n", readl(CLASS_VERSION));
-+	pr_info("TMU version: %x\n", readl(TMU_VERSION));
-+
-+	pr_info("BMU1 version: %x\n", readl(BMU1_BASE_ADDR +
-+		BMU_VERSION));
-+	pr_info("BMU2 version: %x\n", readl(BMU2_BASE_ADDR +
-+		BMU_VERSION));
-+
-+	pr_info("EGPI1 version: %x\n", readl(EGPI1_BASE_ADDR +
-+		GPI_VERSION));
-+	pr_info("EGPI2 version: %x\n", readl(EGPI2_BASE_ADDR +
-+		GPI_VERSION));
-+	pr_info("HGPI version: %x\n", readl(HGPI_BASE_ADDR +
-+		GPI_VERSION));
-+
-+	pr_info("HIF version: %x\n", readl(HIF_VERSION));
-+	pr_info("HIF NOPCY version: %x\n", readl(HIF_NOCPY_VERSION));
-+
-+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
-+	pr_info("UTIL version: %x\n", readl(UTIL_VERSION));
-+#endif
-+	while (!(readl(TMU_CTRL) & ECC_MEM_INIT_DONE))
-+		;
-+
-+	hif_rx_disable();
-+	hif_tx_disable();
-+
-+	bmu_init(BMU1_BASE_ADDR, &bmu1_cfg);
-+
-+	pr_info("bmu_init(1) done\n");
-+
-+	bmu_init(BMU2_BASE_ADDR, &bmu2_cfg);
-+
-+	pr_info("bmu_init(2) done\n");
-+
-+	class_cfg.resume = resume ? 1 : 0;
-+
-+	class_init(&class_cfg);
-+
-+	pr_info("class_init() done\n");
-+
-+	tmu_init(&tmu_cfg);
-+
-+	pr_info("tmu_init() done\n");
-+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
-+	util_init(&util_cfg);
-+
-+	pr_info("util_init() done\n");
-+#endif
-+	gpi_init(EGPI1_BASE_ADDR, &egpi1_cfg);
-+
-+	pr_info("gpi_init(1) done\n");
-+
-+	gpi_init(EGPI2_BASE_ADDR, &egpi2_cfg);
-+
-+	pr_info("gpi_init(2) done\n");
-+
-+	gpi_init(HGPI_BASE_ADDR, &hgpi_cfg);
-+
-+	pr_info("gpi_init(hif) done\n");
-+
-+	bmu_enable(BMU1_BASE_ADDR);
-+
-+	pr_info("bmu_enable(1) done\n");
-+
-+	bmu_enable(BMU2_BASE_ADDR);
-+
-+	pr_info("bmu_enable(2) done\n");
-+
-+	return 0;
-+}
-+
-+void pfe_hw_exit(struct pfe *pfe)
-+{
-+	pr_info("%s\n", __func__);
-+
-+	bmu_disable(BMU1_BASE_ADDR);
-+	bmu_reset(BMU1_BASE_ADDR);
-+
-+	bmu_disable(BMU2_BASE_ADDR);
-+	bmu_reset(BMU2_BASE_ADDR);
-+}
---- /dev/null
-+++ b/drivers/staging/fsl_ppfe/pfe_hw.h
-@@ -0,0 +1,15 @@
-+/* SPDX-License-Identifier: GPL-2.0+ */
-+/*
-+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
-+ * Copyright 2017 NXP
-+ */
-+
-+#ifndef _PFE_HW_H_
-+#define _PFE_HW_H_
-+
-+#define PE_SYS_CLK_RATIO	1	/* SYS/AXI = 250MHz, HFE = 500MHz */
-+
-+int pfe_hw_init(struct pfe *pfe, int resume);
-+void pfe_hw_exit(struct pfe *pfe);
-+
-+#endif /* _PFE_HW_H_ */
---- /dev/null
-+++ b/drivers/staging/fsl_ppfe/pfe_ls1012a_platform.c
-@@ -0,0 +1,383 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+/*
-+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
-+ * Copyright 2017 NXP
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/device.h>
-+#include <linux/of.h>
-+#include <linux/of_net.h>
-+#include <linux/of_address.h>
-+#include <linux/of_mdio.h>
-+#include <linux/platform_device.h>
-+#include <linux/slab.h>
-+#include <linux/clk.h>
-+#include <linux/mfd/syscon.h>
-+#include <linux/regmap.h>
-+
-+#include "pfe_mod.h"
-+
-+extern bool pfe_use_old_dts_phy;
-+struct ls1012a_pfe_platform_data pfe_platform_data;
-+
-+static int pfe_get_gemac_if_properties(struct device_node *gem,
-+				       int port,
-+				       struct ls1012a_pfe_platform_data	*pdata)
-+{
-+	struct device_node *phy_node = NULL;
-+	int size;
-+	int phy_id = 0;
-+	const u32 *addr;
-+	int err;
-+
-+	addr = of_get_property(gem, "reg", &size);
-+	if (addr)
-+		port = be32_to_cpup(addr);
-+	else
-+		goto err;
-+
-+	pdata->ls1012a_eth_pdata[port].gem_id = port;
-+
-+	err = of_get_mac_address(gem, pdata->ls1012a_eth_pdata[port].mac_addr);
-+
-+	phy_node = of_parse_phandle(gem, "phy-handle", 0);
-+	pdata->ls1012a_eth_pdata[port].phy_node = phy_node;
-+	if (phy_node) {
-+		pfe_use_old_dts_phy = false;
-+		goto process_phynode;
-+	} else if (of_phy_is_fixed_link(gem)) {
-+		pfe_use_old_dts_phy = false;
-+		if (of_phy_register_fixed_link(gem) < 0) {
-+			pr_err("broken fixed-link specification\n");
-+			goto err;
-+		}
-+		phy_node = of_node_get(gem);
-+		pdata->ls1012a_eth_pdata[port].phy_node = phy_node;
-+	} else if (of_get_property(gem, "fsl,pfe-phy-if-flags", &size)) {
-+		pfe_use_old_dts_phy = true;
-+		/* Use old dts properties for phy handling */
-+		addr = of_get_property(gem, "fsl,pfe-phy-if-flags", &size);
-+		pdata->ls1012a_eth_pdata[port].phy_flags = be32_to_cpup(addr);
-+
-+		addr = of_get_property(gem, "fsl,gemac-phy-id", &size);
-+		if (!addr) {
-+			pr_err("%s:%d Invalid gemac-phy-id....\n", __func__,
-+			       __LINE__);
-+		} else {
-+			phy_id = be32_to_cpup(addr);
-+			pdata->ls1012a_eth_pdata[port].phy_id = phy_id;
-+			pdata->ls1012a_mdio_pdata[0].phy_mask &= ~(1 << phy_id);
-+		}
-+
-+		/* If PHY is enabled, read mdio properties */
-+		if (pdata->ls1012a_eth_pdata[port].phy_flags & GEMAC_NO_PHY)
-+			goto done;
-+
-+	} else {
-+		pr_info("%s: No PHY or fixed-link\n", __func__);
-+		return 0;
-+	}
-+
-+process_phynode:
-+	err = of_get_phy_mode(gem, &pdata->ls1012a_eth_pdata[port].mii_config);
-+	if (err)
-+		pr_err("%s:%d Incorrect Phy mode....\n", __func__,
-+		       __LINE__);
-+
-+	addr = of_get_property(gem, "fsl,mdio-mux-val", &size);
-+	if (!addr) {
-+		pr_err("%s: Invalid mdio-mux-val....\n", __func__);
-+	} else {
-+		phy_id = be32_to_cpup(addr);
-+		pdata->ls1012a_eth_pdata[port].mdio_muxval = phy_id;
-+	}
-+
-+	if (pdata->ls1012a_eth_pdata[port].phy_id < 32)
-+		pfe->mdio_muxval[pdata->ls1012a_eth_pdata[port].phy_id] =
-+			 pdata->ls1012a_eth_pdata[port].mdio_muxval;
-+
-+
-+	pdata->ls1012a_mdio_pdata[port].irq[0] = PHY_POLL;
-+
-+done:
-+	return 0;
-+
-+err:
-+	return -1;
-+}
-+
-+/*
-+ *
-+ * pfe_platform_probe -
-+ *
-+ *
-+ */
-+static int pfe_platform_probe(struct platform_device *pdev)
-+{
-+	struct resource res;
-+	int ii = 0, rc, interface_count = 0, size = 0;
-+	const u32 *prop;
-+	struct device_node *np, *gem = NULL;
-+	struct clk *pfe_clk;
-+
-+	np = pdev->dev.of_node;
-+
-+	if (!np) {
-+		pr_err("Invalid device node\n");
-+		return -EINVAL;
-+	}
-+
-+	pfe = kzalloc(sizeof(*pfe), GFP_KERNEL);
-+	if (!pfe) {
-+		rc = -ENOMEM;
-+		goto err_alloc;
-+	}
-+
-+	platform_set_drvdata(pdev, pfe);
-+
-+	if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32))) {
-+		rc = -ENOMEM;
-+		pr_err("unable to configure DMA mask.\n");
-+		goto err_ddr;
-+	}
-+
-+	if (of_address_to_resource(np, 1, &res)) {
-+		rc = -ENOMEM;
-+		pr_err("failed to get ddr resource\n");
-+		goto err_ddr;
-+	}
-+
-+	pfe->ddr_phys_baseaddr = res.start;
-+	pfe->ddr_size = resource_size(&res);
-+
-+	pfe->ddr_baseaddr = memremap(res.start, resource_size(&res),
-+				     MEMREMAP_WB);
-+	if (!pfe->ddr_baseaddr) {
-+		pr_err("memremap() ddr failed\n");
-+		rc = -ENOMEM;
-+		goto err_ddr;
-+	}
-+
-+	pfe->scfg =
-+		syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
-+						"fsl,pfe-scfg");
-+	if (IS_ERR(pfe->scfg)) {
-+		dev_err(&pdev->dev, "No syscfg phandle specified\n");
-+		return PTR_ERR(pfe->scfg);
-+	}
-+
-+	pfe->cbus_baseaddr = of_iomap(np, 0);
-+	if (!pfe->cbus_baseaddr) {
-+		rc = -ENOMEM;
-+		pr_err("failed to get axi resource\n");
-+		goto err_axi;
-+	}
-+
-+	pfe->hif_irq = platform_get_irq(pdev, 0);
-+	if (pfe->hif_irq < 0) {
-+		pr_err("platform_get_irq for hif failed\n");
-+		rc = pfe->hif_irq;
-+		goto err_hif_irq;
-+	}
-+
-+	pfe->wol_irq = platform_get_irq(pdev, 2);
-+	if (pfe->wol_irq < 0) {
-+		pr_err("platform_get_irq for WoL failed\n");
-+		rc = pfe->wol_irq;
-+		goto err_hif_irq;
-+	}
-+
-+	/* Read interface count */
-+	prop = of_get_property(np, "fsl,pfe-num-interfaces", &size);
-+	if (!prop) {
-+		pr_err("Failed to read number of interfaces\n");
-+		rc = -ENXIO;
-+		goto err_prop;
-+	}
-+
-+	interface_count = be32_to_cpup(prop);
-+	if (interface_count <= 0) {
-+		pr_err("No ethernet interface count : %d\n",
-+		       interface_count);
-+		rc = -ENXIO;
-+		goto err_prop;
-+	}
-+
-+	pfe_platform_data.ls1012a_mdio_pdata[0].phy_mask = 0xffffffff;
-+
-+	while ((gem = of_get_next_child(np, gem))) {
-+		if (of_find_property(gem, "reg", &size)) {
-+			pfe_get_gemac_if_properties(gem, ii,
-+						&pfe_platform_data);
-+			ii++;
-+		}
-+	}
-+
-+	if (interface_count != ii)
-+		pr_info("missing some of gemac interface properties.\n");
-+
-+	pfe->dev = &pdev->dev;
-+
-+	pfe->dev->platform_data = &pfe_platform_data;
-+
-+	/* declare WoL capabilities */
-+	device_init_wakeup(&pdev->dev, true);
-+
-+	/* find the clocks */
-+	pfe_clk = devm_clk_get(pfe->dev, "pfe");
-+	if (IS_ERR(pfe_clk))
-+		return PTR_ERR(pfe_clk);
-+
-+	/* PFE clock is (platform clock / 2) */
-+	/* save sys_clk value as KHz */
-+	pfe->ctrl.sys_clk = clk_get_rate(pfe_clk) / (2 * 1000);
-+
-+	rc = pfe_probe(pfe);
-+	if (rc < 0)
-+		goto err_probe;
-+
-+	return 0;
-+
-+err_probe:
-+err_prop:
-+err_hif_irq:
-+	iounmap(pfe->cbus_baseaddr);
-+
-+err_axi:
-+	memunmap(pfe->ddr_baseaddr);
-+
-+err_ddr:
-+	platform_set_drvdata(pdev, NULL);
-+
-+	kfree(pfe);
-+
-+err_alloc:
-+	return rc;
-+}
-+
-+/*
-+ * pfe_platform_remove -
-+ */
-+static int pfe_platform_remove(struct platform_device *pdev)
-+{
-+	struct pfe *pfe = platform_get_drvdata(pdev);
-+	int rc;
-+
-+	pr_info("%s\n", __func__);
-+
-+	rc = pfe_remove(pfe);
-+
-+	iounmap(pfe->cbus_baseaddr);
-+
-+	memunmap(pfe->ddr_baseaddr);
-+
-+	platform_set_drvdata(pdev, NULL);
-+
-+	kfree(pfe);
-+
-+	return rc;
-+}
-+
-+#ifdef CONFIG_PM
-+#ifdef CONFIG_PM_SLEEP
-+int pfe_platform_suspend(struct device *dev)
-+{
-+	struct pfe *pfe = platform_get_drvdata(to_platform_device(dev));
-+	struct net_device *netdev;
-+	int i;
-+
-+	pfe->wake = 0;
-+
-+	for (i = 0; i < (NUM_GEMAC_SUPPORT); i++) {
-+		netdev = pfe->eth.eth_priv[i]->ndev;
-+
-+		netif_device_detach(netdev);
-+
-+		if (netif_running(netdev))
-+			if (pfe_eth_suspend(netdev))
-+				pfe->wake = 1;
-+	}
-+
-+	/* Shutdown PFE only if we're not waking up the system */
-+	if (!pfe->wake) {
-+#if defined(LS1012A_PFE_RESET_WA)
-+		pfe_hif_rx_idle(&pfe->hif);
-+#endif
-+		pfe_ctrl_suspend(&pfe->ctrl);
-+		pfe_firmware_exit(pfe);
-+
-+		pfe_hif_exit(pfe);
-+		pfe_hif_lib_exit(pfe);
-+
-+		pfe_hw_exit(pfe);
-+	}
-+
-+	return 0;
-+}
-+
-+static int pfe_platform_resume(struct device *dev)
-+{
-+	struct pfe *pfe = platform_get_drvdata(to_platform_device(dev));
-+	struct net_device *netdev;
-+	int i;
-+
-+	if (!pfe->wake) {
-+		pfe_hw_init(pfe, 1);
-+		pfe_hif_lib_init(pfe);
-+		pfe_hif_init(pfe);
-+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
-+		util_enable();
-+#endif
-+		tmu_enable(0xf);
-+		class_enable();
-+		pfe_ctrl_resume(&pfe->ctrl);
-+	}
-+
-+	for (i = 0; i < (NUM_GEMAC_SUPPORT); i++) {
-+		netdev = pfe->eth.eth_priv[i]->ndev;
-+
-+		if (pfe->mdio.mdio_priv[i]->mii_bus)
-+			pfe_eth_mdio_reset(pfe->mdio.mdio_priv[i]->mii_bus);
-+
-+		if (netif_running(netdev))
-+			pfe_eth_resume(netdev);
-+
-+		netif_device_attach(netdev);
-+	}
-+	return 0;
-+}
-+#else
-+#define pfe_platform_suspend NULL
-+#define pfe_platform_resume NULL
-+#endif
-+
-+static const struct dev_pm_ops pfe_platform_pm_ops = {
-+	SET_SYSTEM_SLEEP_PM_OPS(pfe_platform_suspend, pfe_platform_resume)
-+};
-+#endif
-+
-+static const struct of_device_id pfe_match[] = {
-+	{
-+		.compatible = "fsl,pfe",
-+	},
-+	{},
-+};
-+MODULE_DEVICE_TABLE(of, pfe_match);
-+
-+static struct platform_driver pfe_platform_driver = {
-+	.probe = pfe_platform_probe,
-+	.remove = pfe_platform_remove,
-+	.driver = {
-+		.name = "pfe",
-+		.of_match_table = pfe_match,
-+#ifdef CONFIG_PM
-+		.pm = &pfe_platform_pm_ops,
-+#endif
-+	},
-+};
-+
-+module_platform_driver(pfe_platform_driver);
-+MODULE_LICENSE("GPL");
-+MODULE_DESCRIPTION("PFE Ethernet driver");
-+MODULE_AUTHOR("NXP DNCPE");
---- /dev/null
-+++ b/drivers/staging/fsl_ppfe/pfe_mod.c
-@@ -0,0 +1,158 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+/*
-+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
-+ * Copyright 2017 NXP
-+ */
-+
-+#include <linux/dma-mapping.h>
-+#include "pfe_mod.h"
-+#include "pfe_cdev.h"
-+
-+unsigned int us;
-+module_param(us, uint, 0444);
-+MODULE_PARM_DESC(us, "0: module enabled for kernel networking (DEFAULT)\n"
-+			"1: module enabled for userspace networking\n");
-+struct pfe *pfe;
-+
-+/*
-+ * pfe_probe -
-+ */
-+int pfe_probe(struct pfe *pfe)
-+{
-+	int rc;
-+
-+	if (pfe->ddr_size < DDR_MAX_SIZE) {
-+		pr_err("%s: required DDR memory (%x) above platform ddr memory (%x)\n",
-+		       __func__, (unsigned int)DDR_MAX_SIZE, pfe->ddr_size);
-+		rc = -ENOMEM;
-+		goto err_hw;
-+	}
-+
-+	if (((int)(pfe->ddr_phys_baseaddr + BMU2_DDR_BASEADDR) &
-+			(8 * SZ_1M - 1)) != 0) {
-+		pr_err("%s: BMU2 base address (0x%x) must be aligned on 8MB boundary\n",
-+		       __func__, (int)pfe->ddr_phys_baseaddr +
-+			BMU2_DDR_BASEADDR);
-+		rc = -ENOMEM;
-+		goto err_hw;
-+	}
-+
-+	pr_info("cbus_baseaddr: %lx, ddr_baseaddr: %lx, ddr_phys_baseaddr: %lx, ddr_size: %x\n",
-+		(unsigned long)pfe->cbus_baseaddr,
-+		(unsigned long)pfe->ddr_baseaddr,
-+		pfe->ddr_phys_baseaddr, pfe->ddr_size);
-+
-+	pfe_lib_init(pfe->cbus_baseaddr, pfe->ddr_baseaddr,
-+		     pfe->ddr_phys_baseaddr, pfe->ddr_size);
-+
-+	rc = pfe_hw_init(pfe, 0);
-+	if (rc < 0)
-+		goto err_hw;
-+
-+	if (us)
-+		goto firmware_init;
-+
-+	rc = pfe_hif_lib_init(pfe);
-+	if (rc < 0)
-+		goto err_hif_lib;
-+
-+	rc = pfe_hif_init(pfe);
-+	if (rc < 0)
-+		goto err_hif;
-+
-+firmware_init:
-+	rc = pfe_firmware_init(pfe);
-+	if (rc < 0)
-+		goto err_firmware;
-+
-+	rc = pfe_ctrl_init(pfe);
-+	if (rc < 0)
-+		goto err_ctrl;
-+
-+	rc = pfe_eth_init(pfe);
-+	if (rc < 0)
-+		goto err_eth;
-+
-+	rc = pfe_sysfs_init(pfe);
-+	if (rc < 0)
-+		goto err_sysfs;
-+
-+	rc = pfe_debugfs_init(pfe);
-+	if (rc < 0)
-+		goto err_debugfs;
-+
-+	if (us) {
-+		/* Creating a character device */
-+		rc = pfe_cdev_init();
-+		if (rc < 0)
-+			goto err_cdev;
-+	}
-+
-+	return 0;
-+
-+err_cdev:
-+	pfe_debugfs_exit(pfe);
-+
-+err_debugfs:
-+	pfe_sysfs_exit(pfe);
-+
-+err_sysfs:
-+	pfe_eth_exit(pfe);
-+
-+err_eth:
-+	pfe_ctrl_exit(pfe);
-+
-+err_ctrl:
-+	pfe_firmware_exit(pfe);
-+
-+err_firmware:
-+	if (us)
-+		goto err_hif_lib;
-+
-+	pfe_hif_exit(pfe);
-+
-+err_hif:
-+	pfe_hif_lib_exit(pfe);
-+
-+err_hif_lib:
-+	pfe_hw_exit(pfe);
-+
-+err_hw:
-+	return rc;
-+}
-+
-+/*
-+ * pfe_remove -
-+ */
-+int pfe_remove(struct pfe *pfe)
-+{
-+	pr_info("%s\n", __func__);
-+
-+	if (us)
-+		pfe_cdev_exit();
-+
-+	pfe_debugfs_exit(pfe);
-+
-+	pfe_sysfs_exit(pfe);
-+
-+	pfe_eth_exit(pfe);
-+
-+	pfe_ctrl_exit(pfe);
-+
-+#if defined(LS1012A_PFE_RESET_WA)
-+	pfe_hif_rx_idle(&pfe->hif);
-+#endif
-+	pfe_firmware_exit(pfe);
-+
-+	if (us)
-+		goto hw_exit;
-+
-+	pfe_hif_exit(pfe);
-+
-+	pfe_hif_lib_exit(pfe);
-+
-+hw_exit:
-+	pfe_hw_exit(pfe);
-+
-+	return 0;
-+}
---- /dev/null
-+++ b/drivers/staging/fsl_ppfe/pfe_mod.h
-@@ -0,0 +1,103 @@
-+/* SPDX-License-Identifier: GPL-2.0+ */
-+/*
-+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
-+ * Copyright 2017 NXP
-+ */
-+
-+#ifndef _PFE_MOD_H_
-+#define _PFE_MOD_H_
-+
-+#include <linux/device.h>
-+#include <linux/elf.h>
-+
-+extern unsigned int us;
-+
-+struct pfe;
-+
-+#include "pfe_hw.h"
-+#include "pfe_firmware.h"
-+#include "pfe_ctrl.h"
-+#include "pfe_hif.h"
-+#include "pfe_hif_lib.h"
-+#include "pfe_eth.h"
-+#include "pfe_sysfs.h"
-+#include "pfe_perfmon.h"
-+#include "pfe_debugfs.h"
-+
-+#define PHYID_MAX_VAL 32
-+
-+struct pfe_tmu_credit {
-+	/* Number of allowed TX packet in-flight, matches TMU queue size */
-+	unsigned int tx_credit[NUM_GEMAC_SUPPORT][EMAC_TXQ_CNT];
-+	unsigned int tx_credit_max[NUM_GEMAC_SUPPORT][EMAC_TXQ_CNT];
-+	unsigned int tx_packets[NUM_GEMAC_SUPPORT][EMAC_TXQ_CNT];
-+};
-+
-+struct pfe {
-+	struct regmap	*scfg;
-+	unsigned long ddr_phys_baseaddr;
-+	void *ddr_baseaddr;
-+	unsigned int ddr_size;
-+	void *cbus_baseaddr;
-+	void *apb_baseaddr;
-+	unsigned long iram_phys_baseaddr;
-+	void *iram_baseaddr;
-+	unsigned long ipsec_phys_baseaddr;
-+	void *ipsec_baseaddr;
-+	int hif_irq;
-+	int wol_irq;
-+	int hif_client_irq;
-+	struct device *dev;
-+	struct dentry *dentry;
-+	struct pfe_ctrl ctrl;
-+	struct pfe_hif hif;
-+	struct pfe_eth eth;
-+	struct pfe_mdio mdio;
-+	struct hif_client_s *hif_client[HIF_CLIENTS_MAX];
-+#if defined(CFG_DIAGS)
-+	struct pfe_diags diags;
-+#endif
-+	struct pfe_tmu_credit tmu_credit;
-+	struct pfe_cpumon cpumon;
-+	struct pfe_memmon memmon;
-+	int wake;
-+	int mdio_muxval[PHYID_MAX_VAL];
-+	struct clk *hfe_clock;
-+};
-+
-+extern struct pfe *pfe;
-+
-+int pfe_probe(struct pfe *pfe);
-+int pfe_remove(struct pfe *pfe);
-+
-+/* DDR Mapping in reserved memory*/
-+#define ROUTE_TABLE_BASEADDR	0
-+#define ROUTE_TABLE_HASH_BITS	15	/* 32K entries */
-+#define ROUTE_TABLE_SIZE	((1 << ROUTE_TABLE_HASH_BITS) \
-+				  * CLASS_ROUTE_SIZE)
-+#define BMU2_DDR_BASEADDR	(ROUTE_TABLE_BASEADDR + ROUTE_TABLE_SIZE)
-+#define BMU2_BUF_COUNT		(4096 - 256)
-+/* This is to get a total DDR size of 12MiB */
-+#define BMU2_DDR_SIZE		(DDR_BUF_SIZE * BMU2_BUF_COUNT)
-+#define UTIL_CODE_BASEADDR	(BMU2_DDR_BASEADDR + BMU2_DDR_SIZE)
-+#define UTIL_CODE_SIZE		(128 * SZ_1K)
-+#define UTIL_DDR_DATA_BASEADDR	(UTIL_CODE_BASEADDR + UTIL_CODE_SIZE)
-+#define UTIL_DDR_DATA_SIZE	(64 * SZ_1K)
-+#define CLASS_DDR_DATA_BASEADDR	(UTIL_DDR_DATA_BASEADDR + UTIL_DDR_DATA_SIZE)
-+#define CLASS_DDR_DATA_SIZE	(32 * SZ_1K)
-+#define TMU_DDR_DATA_BASEADDR	(CLASS_DDR_DATA_BASEADDR + CLASS_DDR_DATA_SIZE)
-+#define TMU_DDR_DATA_SIZE	(32 * SZ_1K)
-+#define TMU_LLM_BASEADDR	(TMU_DDR_DATA_BASEADDR + TMU_DDR_DATA_SIZE)
-+#define TMU_LLM_QUEUE_LEN	(8 * 512)
-+/* Must be power of two and at least 16 * 8 = 128 bytes */
-+#define TMU_LLM_SIZE		(4 * 16 * TMU_LLM_QUEUE_LEN)
-+/* (4 TMU's x 16 queues x queue_len) */
-+
-+#define DDR_MAX_SIZE		(TMU_LLM_BASEADDR + TMU_LLM_SIZE)
-+
-+/* LMEM Mapping */
-+#define BMU1_LMEM_BASEADDR	0
-+#define BMU1_BUF_COUNT		256
-+#define BMU1_LMEM_SIZE		(LMEM_BUF_SIZE * BMU1_BUF_COUNT)
-+
-+#endif /* _PFE_MOD_H */
---- /dev/null
-+++ b/drivers/staging/fsl_ppfe/pfe_perfmon.h
-@@ -0,0 +1,26 @@
-+/* SPDX-License-Identifier: GPL-2.0+ */
-+/*
-+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
-+ * Copyright 2017 NXP
-+ */
-+
-+#ifndef _PFE_PERFMON_H_
-+#define _PFE_PERFMON_H_
-+
-+#include "pfe/pfe.h"
-+
-+#define	CT_CPUMON_INTERVAL	(1 * TIMER_TICKS_PER_SEC)
-+
-+struct pfe_cpumon {
-+	u32 cpu_usage_pct[MAX_PE];
-+	u32 class_usage_pct;
-+};
-+
-+struct pfe_memmon {
-+	u32 kernel_memory_allocated;
-+};
-+
-+int pfe_perfmon_init(struct pfe *pfe);
-+void pfe_perfmon_exit(struct pfe *pfe);
-+
-+#endif /* _PFE_PERFMON_H_ */
---- /dev/null
-+++ b/drivers/staging/fsl_ppfe/pfe_sysfs.c
-@@ -0,0 +1,840 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+/*
-+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
-+ * Copyright 2017 NXP
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+
-+#include "pfe_mod.h"
-+
-+#define PE_EXCEPTION_DUMP_ADDRESS 0x1fa8
-+#define NUM_QUEUES		16
-+
-+static char register_name[20][5] = {
-+	"EPC", "ECAS", "EID", "ED",
-+	"r0", "r1", "r2", "r3",
-+	"r4", "r5", "r6", "r7",
-+	"r8", "r9", "r10", "r11",
-+	"r12", "r13", "r14", "r15",
-+};
-+
-+static char exception_name[14][20] = {
-+	"Reset",
-+	"HardwareFailure",
-+	"NMI",
-+	"InstBreakpoint",
-+	"DataBreakpoint",
-+	"Unsupported",
-+	"PrivilegeViolation",
-+	"InstBusError",
-+	"DataBusError",
-+	"AlignmentError",
-+	"ArithmeticError",
-+	"SystemCall",
-+	"MemoryManagement",
-+	"Interrupt",
-+};
-+
-+static unsigned long class_do_clear;
-+static unsigned long tmu_do_clear;
-+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
-+static unsigned long util_do_clear;
-+#endif
-+
-+static ssize_t display_pe_status(char *buf, int id, u32 dmem_addr, unsigned long
-+					do_clear)
-+{
-+	ssize_t len = 0;
-+	u32 val;
-+	char statebuf[5];
-+	struct pfe_cpumon *cpumon = &pfe->cpumon;
-+	u32 debug_indicator;
-+	u32 debug[20];
-+
-+	if (id < CLASS0_ID || id >= MAX_PE)
-+		return len;
-+
-+	*(u32 *)statebuf = pe_dmem_read(id, dmem_addr, 4);
-+	dmem_addr += 4;
-+
-+	statebuf[4] = '\0';
-+	len += sprintf(buf + len, "state=%4s ", statebuf);
-+
-+	val = pe_dmem_read(id, dmem_addr, 4);
-+	dmem_addr += 4;
-+	len += sprintf(buf + len, "ctr=%08x ", cpu_to_be32(val));
-+
-+	val = pe_dmem_read(id, dmem_addr, 4);
-+	if (do_clear && val)
-+		pe_dmem_write(id, 0, dmem_addr, 4);
-+	dmem_addr += 4;
-+	len += sprintf(buf + len, "rx=%u ", cpu_to_be32(val));
-+
-+	val = pe_dmem_read(id, dmem_addr, 4);
-+	if (do_clear && val)
-+		pe_dmem_write(id, 0, dmem_addr, 4);
-+	dmem_addr += 4;
-+	if (id >= TMU0_ID && id <= TMU_MAX_ID)
-+		len += sprintf(buf + len, "qstatus=%x", cpu_to_be32(val));
-+	else
-+		len += sprintf(buf + len, "tx=%u", cpu_to_be32(val));
-+
-+	val = pe_dmem_read(id, dmem_addr, 4);
-+	if (do_clear && val)
-+		pe_dmem_write(id, 0, dmem_addr, 4);
-+	dmem_addr += 4;
-+	if (val)
-+		len += sprintf(buf + len, " drop=%u", cpu_to_be32(val));
-+
-+	len += sprintf(buf + len, " load=%d%%", cpumon->cpu_usage_pct[id]);
-+
-+	len += sprintf(buf + len, "\n");
-+
-+	debug_indicator = pe_dmem_read(id, dmem_addr, 4);
-+	dmem_addr += 4;
-+	if (!strncmp((char *)&debug_indicator, "DBUG", 4)) {
-+		int j, last = 0;
-+
-+		for (j = 0; j < 16; j++) {
-+			debug[j] = pe_dmem_read(id, dmem_addr, 4);
-+			if (debug[j]) {
-+				if (do_clear)
-+					pe_dmem_write(id, 0, dmem_addr, 4);
-+				last = j + 1;
-+			}
-+			dmem_addr += 4;
-+		}
-+		for (j = 0; j < last; j++) {
-+			len += sprintf(buf + len, "%08x%s",
-+			cpu_to_be32(debug[j]),
-+			(j & 0x7) == 0x7 || j == last - 1 ? "\n" : " ");
-+		}
-+	}
-+
-+	if (!strncmp(statebuf, "DEAD", 4)) {
-+		u32 i, dump = PE_EXCEPTION_DUMP_ADDRESS;
-+
-+		len += sprintf(buf + len, "Exception details:\n");
-+		for (i = 0; i < 20; i++) {
-+			debug[i] = pe_dmem_read(id, dump, 4);
-+			dump += 4;
-+			if (i == 2)
-+				len += sprintf(buf + len, "%4s = %08x (=%s) ",
-+				register_name[i], cpu_to_be32(debug[i]),
-+				exception_name[min((u32)
-+				cpu_to_be32(debug[i]), (u32)13)]);
-+			else
-+				len += sprintf(buf + len, "%4s = %08x%s",
-+				register_name[i], cpu_to_be32(debug[i]),
-+				(i & 0x3) == 0x3 || i == 19 ? "\n" : " ");
-+		}
-+	}
-+
-+	return len;
-+}
-+
-+static ssize_t class_phy_stats(char *buf, int phy)
-+{
-+	ssize_t len = 0;
-+	int off1 = phy * 0x28;
-+	int off2 = phy * 0x10;
-+
-+	if (phy == 3)
-+		off1 = CLASS_PHY4_RX_PKTS - CLASS_PHY1_RX_PKTS;
-+
-+	len += sprintf(buf + len, "phy: %d\n", phy);
-+	len += sprintf(buf + len,
-+			"  rx:   %10u, tx:   %10u, intf:  %10u, ipv4:    %10u, ipv6: %10u\n",
-+			readl(CLASS_PHY1_RX_PKTS + off1),
-+			readl(CLASS_PHY1_TX_PKTS + off1),
-+			readl(CLASS_PHY1_INTF_MATCH_PKTS + off1),
-+			readl(CLASS_PHY1_V4_PKTS + off1),
-+			readl(CLASS_PHY1_V6_PKTS + off1));
-+
-+	len += sprintf(buf + len,
-+			"  icmp: %10u, igmp: %10u, tcp:   %10u, udp:     %10u\n",
-+			readl(CLASS_PHY1_ICMP_PKTS + off2),
-+			readl(CLASS_PHY1_IGMP_PKTS + off2),
-+			readl(CLASS_PHY1_TCP_PKTS + off2),
-+			readl(CLASS_PHY1_UDP_PKTS + off2));
-+
-+	len += sprintf(buf + len, "  err\n");
-+	len += sprintf(buf + len,
-+			"  lp:   %10u, intf: %10u, l3:    %10u, chcksum: %10u, ttl:  %10u\n",
-+			readl(CLASS_PHY1_LP_FAIL_PKTS + off1),
-+			readl(CLASS_PHY1_INTF_FAIL_PKTS + off1),
-+			readl(CLASS_PHY1_L3_FAIL_PKTS + off1),
-+			readl(CLASS_PHY1_CHKSUM_ERR_PKTS + off1),
-+			readl(CLASS_PHY1_TTL_ERR_PKTS + off1));
-+
-+	return len;
-+}
-+
-+/* qm_read_drop_stat
-+ * This function is used to read the drop statistics from the TMU
-+ * hw drop counter.  Since the hw counter is always cleared afer
-+ * reading, this function maintains the previous drop count, and
-+ * adds the new value to it.  That value can be retrieved by
-+ * passing a pointer to it with the total_drops arg.
-+ *
-+ * @param tmu		TMU number (0 - 3)
-+ * @param queue		queue number (0 - 15)
-+ * @param total_drops	pointer to location to store total drops (or NULL)
-+ * @param do_reset	if TRUE, clear total drops after updating
-+ */
-+u32 qm_read_drop_stat(u32 tmu, u32 queue, u32 *total_drops, int do_reset)
-+{
-+	static u32 qtotal[TMU_MAX_ID + 1][NUM_QUEUES];
-+	u32 val;
-+
-+	writel((tmu << 8) | queue, TMU_TEQ_CTRL);
-+	writel((tmu << 8) | queue, TMU_LLM_CTRL);
-+	val = readl(TMU_TEQ_DROP_STAT);
-+	qtotal[tmu][queue] += val;
-+	if (total_drops)
-+		*total_drops = qtotal[tmu][queue];
-+	if (do_reset)
-+		qtotal[tmu][queue] = 0;
-+	return val;
-+}
-+
-+static ssize_t tmu_queue_stats(char *buf, int tmu, int queue)
-+{
-+	ssize_t len = 0;
-+	u32 drops;
-+
-+	len += sprintf(buf + len, "%d-%02d, ", tmu, queue);
-+
-+	drops = qm_read_drop_stat(tmu, queue, NULL, 0);
-+
-+	/* Select queue */
-+	writel((tmu << 8) | queue, TMU_TEQ_CTRL);
-+	writel((tmu << 8) | queue, TMU_LLM_CTRL);
-+
-+	len += sprintf(buf + len,
-+			"(teq) drop: %10u, tx: %10u (llm) head: %08x, tail: %08x, drop: %10u\n",
-+		drops, readl(TMU_TEQ_TRANS_STAT),
-+		readl(TMU_LLM_QUE_HEADPTR), readl(TMU_LLM_QUE_TAILPTR),
-+		readl(TMU_LLM_QUE_DROPCNT));
-+
-+	return len;
-+}
-+
-+static ssize_t tmu_queues(char *buf, int tmu)
-+{
-+	ssize_t len = 0;
-+	int queue;
-+
-+	for (queue = 0; queue < 16; queue++)
-+		len += tmu_queue_stats(buf + len, tmu, queue);
-+
-+	return len;
-+}
-+
-+static ssize_t block_version(char *buf, void *addr)
-+{
-+	ssize_t len = 0;
-+	u32 val;
-+
-+	val = readl(addr);
-+	len += sprintf(buf + len, "revision: %x, version: %x, id: %x\n",
-+		(val >> 24) & 0xff, (val >> 16) & 0xff, val & 0xffff);
-+
-+	return len;
-+}
-+
-+static ssize_t bmu(char *buf, int id, void *base)
-+{
-+	ssize_t len = 0;
-+
-+	len += sprintf(buf + len, "%s: %d\n  ", __func__, id);
-+
-+	len += block_version(buf + len, base + BMU_VERSION);
-+
-+	len += sprintf(buf + len, "  buf size:  %x\n", (1 << readl(base +
-+			BMU_BUF_SIZE)));
-+	len += sprintf(buf + len, "  buf count: %x\n", readl(base +
-+			BMU_BUF_CNT));
-+	len += sprintf(buf + len, "  buf rem:   %x\n", readl(base +
-+			BMU_REM_BUF_CNT));
-+	len += sprintf(buf + len, "  buf curr:  %x\n", readl(base +
-+			BMU_CURR_BUF_CNT));
-+	len += sprintf(buf + len, "  free err:  %x\n", readl(base +
-+			BMU_FREE_ERR_ADDR));
-+
-+	return len;
-+}
-+
-+static ssize_t gpi(char *buf, int id, void *base)
-+{
-+	ssize_t len = 0;
-+	u32 val;
-+
-+	len += sprintf(buf + len, "%s%d:\n  ", __func__, id);
-+	len += block_version(buf + len, base + GPI_VERSION);
-+
-+	len += sprintf(buf + len, "  tx under stick: %x\n", readl(base +
-+			GPI_FIFO_STATUS));
-+	val = readl(base + GPI_FIFO_DEBUG);
-+	len += sprintf(buf + len, "  tx pkts:        %x\n", (val >> 23) &
-+			0x3f);
-+	len += sprintf(buf + len, "  rx pkts:        %x\n", (val >> 18) &
-+			0x3f);
-+	len += sprintf(buf + len, "  tx bytes:       %x\n", (val >> 9) &
-+			0x1ff);
-+	len += sprintf(buf + len, "  rx bytes:       %x\n", (val >> 0) &
-+			0x1ff);
-+	len += sprintf(buf + len, "  overrun:        %x\n", readl(base +
-+			GPI_OVERRUN_DROPCNT));
-+
-+	return len;
-+}
-+
-+static ssize_t pfe_set_class(struct device *dev, struct device_attribute *attr,
-+			     const char *buf, size_t count)
-+{
-+	class_do_clear = kstrtoul(buf, 0, 0);
-+	return count;
-+}
-+
-+static ssize_t pfe_show_class(struct device *dev, struct device_attribute *attr,
-+			      char *buf)
-+{
-+	ssize_t len = 0;
-+	int id;
-+	u32 val;
-+	struct pfe_cpumon *cpumon = &pfe->cpumon;
-+
-+	len += block_version(buf + len, CLASS_VERSION);
-+
-+	for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++) {
-+		len += sprintf(buf + len, "%d: ", id - CLASS0_ID);
-+
-+		val = readl(CLASS_PE0_DEBUG + id * 4);
-+		len += sprintf(buf + len, "pc=1%04x ", val & 0xffff);
-+
-+		len += display_pe_status(buf + len, id, CLASS_DM_PESTATUS,
-+						class_do_clear);
-+	}
-+	len += sprintf(buf + len, "aggregate load=%d%%\n\n",
-+			cpumon->class_usage_pct);
-+
-+	len += sprintf(buf + len, "pe status:   0x%x\n",
-+			readl(CLASS_PE_STATUS));
-+	len += sprintf(buf + len, "max buf cnt: 0x%x   afull thres: 0x%x\n",
-+			readl(CLASS_MAX_BUF_CNT), readl(CLASS_AFULL_THRES));
-+	len += sprintf(buf + len, "tsq max cnt: 0x%x   tsq fifo thres: 0x%x\n",
-+			readl(CLASS_TSQ_MAX_CNT), readl(CLASS_TSQ_FIFO_THRES));
-+	len += sprintf(buf + len, "state:       0x%x\n", readl(CLASS_STATE));
-+
-+	len += class_phy_stats(buf + len, 0);
-+	len += class_phy_stats(buf + len, 1);
-+	len += class_phy_stats(buf + len, 2);
-+	len += class_phy_stats(buf + len, 3);
-+
-+	return len;
-+}
-+
-+static ssize_t pfe_set_tmu(struct device *dev, struct device_attribute *attr,
-+			   const char *buf, size_t count)
-+{
-+	tmu_do_clear = kstrtoul(buf, 0, 0);
-+	return count;
-+}
-+
-+static ssize_t pfe_show_tmu(struct device *dev, struct device_attribute *attr,
-+			    char *buf)
-+{
-+	ssize_t len = 0;
-+	int id;
-+	u32 val;
-+
-+	len += block_version(buf + len, TMU_VERSION);
-+
-+	for (id = TMU0_ID; id <= TMU_MAX_ID; id++) {
-+		if (id == TMU2_ID)
-+			continue;
-+		len += sprintf(buf + len, "%d: ", id - TMU0_ID);
-+
-+		len += display_pe_status(buf + len, id, TMU_DM_PESTATUS,
-+						tmu_do_clear);
-+	}
-+
-+	len += sprintf(buf + len, "pe status:    %x\n", readl(TMU_PE_STATUS));
-+	len += sprintf(buf + len, "inq fifo cnt: %x\n",
-+			readl(TMU_PHY_INQ_FIFO_CNT));
-+	val = readl(TMU_INQ_STAT);
-+	len += sprintf(buf + len, "inq wr ptr:     %x\n", val & 0x3ff);
-+	len += sprintf(buf + len, "inq rd ptr:     %x\n", val >> 10);
-+
-+	return len;
-+}
-+
-+static unsigned long drops_do_clear;
-+static u32 class_drop_counter[CLASS_NUM_DROP_COUNTERS];
-+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
-+static u32 util_drop_counter[UTIL_NUM_DROP_COUNTERS];
-+#endif
-+
-+char *class_drop_description[CLASS_NUM_DROP_COUNTERS] = {
-+	"ICC",
-+	"Host Pkt Error",
-+	"Rx Error",
-+	"IPsec Outbound",
-+	"IPsec Inbound",
-+	"EXPT IPsec Error",
-+	"Reassembly",
-+	"Fragmenter",
-+	"NAT-T",
-+	"Socket",
-+	"Multicast",
-+	"NAT-PT",
-+	"Tx Disabled",
-+};
-+
-+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
-+char *util_drop_description[UTIL_NUM_DROP_COUNTERS] = {
-+	"IPsec Outbound",
-+	"IPsec Inbound",
-+	"IPsec Rate Limiter",
-+	"Fragmenter",
-+	"Socket",
-+	"Tx Disabled",
-+	"Rx Error",
-+};
-+#endif
-+
-+static ssize_t pfe_set_drops(struct device *dev, struct device_attribute *attr,
-+			     const char *buf, size_t count)
-+{
-+	drops_do_clear = kstrtoul(buf, 0, 0);
-+	return count;
-+}
-+
-+static u32 tmu_drops[4][16];
-+static ssize_t pfe_show_drops(struct device *dev, struct device_attribute *attr,
-+			      char *buf)
-+{
-+	ssize_t len = 0;
-+	int id, dropnum;
-+	int tmu, queue;
-+	u32 val;
-+	u32 dmem_addr;
-+	int num_class_drops = 0, num_tmu_drops = 0, num_util_drops = 0;
-+	struct pfe_ctrl *ctrl = &pfe->ctrl;
-+
-+	memset(class_drop_counter, 0, sizeof(class_drop_counter));
-+	for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++) {
-+		if (drops_do_clear)
-+			pe_sync_stop(ctrl, (1 << id));
-+		for (dropnum = 0; dropnum < CLASS_NUM_DROP_COUNTERS;
-+			dropnum++) {
-+			dmem_addr = CLASS_DM_DROP_CNTR;
-+			val = be32_to_cpu(pe_dmem_read(id, dmem_addr, 4));
-+			class_drop_counter[dropnum] += val;
-+			num_class_drops += val;
-+			if (drops_do_clear)
-+				pe_dmem_write(id, 0, dmem_addr, 4);
-+		}
-+		if (drops_do_clear)
-+			pe_start(ctrl, (1 << id));
-+	}
-+
-+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
-+	if (drops_do_clear)
-+		pe_sync_stop(ctrl, (1 << UTIL_ID));
-+	for (dropnum = 0; dropnum < UTIL_NUM_DROP_COUNTERS; dropnum++) {
-+		dmem_addr = UTIL_DM_DROP_CNTR;
-+		val = be32_to_cpu(pe_dmem_read(UTIL_ID, dmem_addr, 4));
-+		util_drop_counter[dropnum] = val;
-+		num_util_drops += val;
-+		if (drops_do_clear)
-+			pe_dmem_write(UTIL_ID, 0, dmem_addr, 4);
-+	}
-+	if (drops_do_clear)
-+		pe_start(ctrl, (1 << UTIL_ID));
-+#endif
-+	for (tmu = 0; tmu < 4; tmu++) {
-+		for (queue = 0; queue < 16; queue++) {
-+			qm_read_drop_stat(tmu, queue, &tmu_drops[tmu][queue],
-+					  drops_do_clear);
-+			num_tmu_drops += tmu_drops[tmu][queue];
-+		}
-+	}
-+
-+	if (num_class_drops == 0 && num_util_drops == 0 && num_tmu_drops == 0)
-+		len += sprintf(buf + len, "No PE drops\n\n");
-+
-+	if (num_class_drops > 0) {
-+		len += sprintf(buf + len, "Class PE drops --\n");
-+		for (dropnum = 0; dropnum < CLASS_NUM_DROP_COUNTERS;
-+			dropnum++) {
-+			if (class_drop_counter[dropnum] > 0)
-+				len += sprintf(buf + len, "  %s: %d\n",
-+					class_drop_description[dropnum],
-+					class_drop_counter[dropnum]);
-+		}
-+		len += sprintf(buf + len, "\n");
-+	}
-+
-+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
-+	if (num_util_drops > 0) {
-+		len += sprintf(buf + len, "Util PE drops --\n");
-+		for (dropnum = 0; dropnum < UTIL_NUM_DROP_COUNTERS; dropnum++) {
-+			if (util_drop_counter[dropnum] > 0)
-+				len += sprintf(buf + len, "  %s: %d\n",
-+					util_drop_description[dropnum],
-+					util_drop_counter[dropnum]);
-+		}
-+		len += sprintf(buf + len, "\n");
-+	}
-+#endif
-+	if (num_tmu_drops > 0) {
-+		len += sprintf(buf + len, "TMU drops --\n");
-+		for (tmu = 0; tmu < 4; tmu++) {
-+			for (queue = 0; queue < 16; queue++) {
-+				if (tmu_drops[tmu][queue] > 0)
-+					len += sprintf(buf + len,
-+						"  TMU%d-Q%d: %d\n"
-+					, tmu, queue, tmu_drops[tmu][queue]);
-+			}
-+		}
-+		len += sprintf(buf + len, "\n");
-+	}
-+
-+	return len;
-+}
-+
-+static ssize_t pfe_show_tmu0_queues(struct device *dev, struct device_attribute
-+					*attr, char *buf)
-+{
-+	return tmu_queues(buf, 0);
-+}
-+
-+static ssize_t pfe_show_tmu1_queues(struct device *dev, struct device_attribute
-+					*attr, char *buf)
-+{
-+	return tmu_queues(buf, 1);
-+}
-+
-+static ssize_t pfe_show_tmu2_queues(struct device *dev, struct device_attribute
-+					*attr, char *buf)
-+{
-+	return tmu_queues(buf, 2);
-+}
-+
-+static ssize_t pfe_show_tmu3_queues(struct device *dev, struct device_attribute
-+					*attr, char *buf)
-+{
-+	return tmu_queues(buf, 3);
-+}
-+
-+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
-+static ssize_t pfe_set_util(struct device *dev, struct device_attribute *attr,
-+			    const char *buf, size_t count)
-+{
-+	util_do_clear = kstrtoul(buf, 0, 0);
-+	return count;
-+}
-+
-+static ssize_t pfe_show_util(struct device *dev, struct device_attribute *attr,
-+			     char *buf)
-+{
-+	ssize_t len = 0;
-+	struct pfe_ctrl *ctrl = &pfe->ctrl;
-+
-+	len += block_version(buf + len, UTIL_VERSION);
-+
-+	pe_sync_stop(ctrl, (1 << UTIL_ID));
-+	len += display_pe_status(buf + len, UTIL_ID, UTIL_DM_PESTATUS,
-+					util_do_clear);
-+	pe_start(ctrl, (1 << UTIL_ID));
-+
-+	len += sprintf(buf + len, "pe status:   %x\n", readl(UTIL_PE_STATUS));
-+	len += sprintf(buf + len, "max buf cnt: %x\n",
-+			readl(UTIL_MAX_BUF_CNT));
-+	len += sprintf(buf + len, "tsq max cnt: %x\n",
-+			readl(UTIL_TSQ_MAX_CNT));
-+
-+	return len;
-+}
-+#endif
-+
-+static ssize_t pfe_show_bmu(struct device *dev, struct device_attribute *attr,
-+			    char *buf)
-+{
-+	ssize_t len = 0;
-+
-+	len += bmu(buf + len, 1, BMU1_BASE_ADDR);
-+	len += bmu(buf + len, 2, BMU2_BASE_ADDR);
-+
-+	return len;
-+}
-+
-+static ssize_t pfe_show_hif(struct device *dev, struct device_attribute *attr,
-+			    char *buf)
-+{
-+	ssize_t len = 0;
-+
-+	len += sprintf(buf + len, "hif:\n  ");
-+	len += block_version(buf + len, HIF_VERSION);
-+
-+	len += sprintf(buf + len, "  tx curr bd:    %x\n",
-+			readl(HIF_TX_CURR_BD_ADDR));
-+	len += sprintf(buf + len, "  tx status:     %x\n",
-+			readl(HIF_TX_STATUS));
-+	len += sprintf(buf + len, "  tx dma status: %x\n",
-+			readl(HIF_TX_DMA_STATUS));
-+
-+	len += sprintf(buf + len, "  rx curr bd:    %x\n",
-+			readl(HIF_RX_CURR_BD_ADDR));
-+	len += sprintf(buf + len, "  rx status:     %x\n",
-+			readl(HIF_RX_STATUS));
-+	len += sprintf(buf + len, "  rx dma status: %x\n",
-+			readl(HIF_RX_DMA_STATUS));
-+
-+	len += sprintf(buf + len, "hif nocopy:\n  ");
-+	len += block_version(buf + len, HIF_NOCPY_VERSION);
-+
-+	len += sprintf(buf + len, "  tx curr bd:    %x\n",
-+			readl(HIF_NOCPY_TX_CURR_BD_ADDR));
-+	len += sprintf(buf + len, "  tx status:     %x\n",
-+			readl(HIF_NOCPY_TX_STATUS));
-+	len += sprintf(buf + len, "  tx dma status: %x\n",
-+			readl(HIF_NOCPY_TX_DMA_STATUS));
-+
-+	len += sprintf(buf + len, "  rx curr bd:    %x\n",
-+			readl(HIF_NOCPY_RX_CURR_BD_ADDR));
-+	len += sprintf(buf + len, "  rx status:     %x\n",
-+			readl(HIF_NOCPY_RX_STATUS));
-+	len += sprintf(buf + len, "  rx dma status: %x\n",
-+			readl(HIF_NOCPY_RX_DMA_STATUS));
-+
-+	return len;
-+}
-+
-+static ssize_t pfe_show_gpi(struct device *dev, struct device_attribute *attr,
-+			    char *buf)
-+{
-+	ssize_t len = 0;
-+
-+	len += gpi(buf + len, 0, EGPI1_BASE_ADDR);
-+	len += gpi(buf + len, 1, EGPI2_BASE_ADDR);
-+	len += gpi(buf + len, 3, HGPI_BASE_ADDR);
-+
-+	return len;
-+}
-+
-+static ssize_t pfe_show_pfemem(struct device *dev, struct device_attribute
-+				*attr, char *buf)
-+{
-+	ssize_t len = 0;
-+	struct pfe_memmon *memmon = &pfe->memmon;
-+
-+	len += sprintf(buf + len, "Kernel Memory: %d Bytes (%d KB)\n",
-+		memmon->kernel_memory_allocated,
-+		(memmon->kernel_memory_allocated + 1023) / 1024);
-+
-+	return len;
-+}
-+
-+static ssize_t pfe_show_crc_revalidated(struct device *dev,
-+					struct device_attribute *attr,
-+					char *buf)
-+{
-+	u64 crc_validated = 0;
-+	ssize_t len = 0;
-+	int id, phyid;
-+
-+	len += sprintf(buf + len, "FCS re-validated by PFE:\n");
-+
-+	for (phyid = 0; phyid < 2; phyid++) {
-+		crc_validated = 0;
-+		for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++) {
-+			crc_validated += be32_to_cpu(pe_dmem_read(id,
-+				CLASS_DM_CRC_VALIDATED + (phyid * 4), 4));
-+		}
-+		len += sprintf(buf + len, "MAC %d:\n    count:%10llu\n",
-+			       phyid, crc_validated);
-+	}
-+
-+	return len;
-+}
-+
-+#ifdef HIF_NAPI_STATS
-+static ssize_t pfe_show_hif_napi_stats(struct device *dev,
-+				       struct device_attribute *attr,
-+				       char *buf)
-+{
-+	struct platform_device *pdev = to_platform_device(dev);
-+	struct pfe *pfe = platform_get_drvdata(pdev);
-+	ssize_t len = 0;
-+
-+	len += sprintf(buf + len, "sched:  %u\n",
-+			pfe->hif.napi_counters[NAPI_SCHED_COUNT]);
-+	len += sprintf(buf + len, "poll:   %u\n",
-+			pfe->hif.napi_counters[NAPI_POLL_COUNT]);
-+	len += sprintf(buf + len, "packet: %u\n",
-+			pfe->hif.napi_counters[NAPI_PACKET_COUNT]);
-+	len += sprintf(buf + len, "budget: %u\n",
-+			pfe->hif.napi_counters[NAPI_FULL_BUDGET_COUNT]);
-+	len += sprintf(buf + len, "desc:   %u\n",
-+			pfe->hif.napi_counters[NAPI_DESC_COUNT]);
-+	len += sprintf(buf + len, "full:   %u\n",
-+			pfe->hif.napi_counters[NAPI_CLIENT_FULL_COUNT]);
-+
-+	return len;
-+}
-+
-+static ssize_t pfe_set_hif_napi_stats(struct device *dev,
-+				      struct device_attribute *attr,
-+					const char *buf, size_t count)
-+{
-+	struct platform_device *pdev = to_platform_device(dev);
-+	struct pfe *pfe = platform_get_drvdata(pdev);
-+
-+	memset(pfe->hif.napi_counters, 0, sizeof(pfe->hif.napi_counters));
-+
-+	return count;
-+}
-+
-+static DEVICE_ATTR(hif_napi_stats, 0644, pfe_show_hif_napi_stats,
-+			pfe_set_hif_napi_stats);
-+#endif
-+
-+static DEVICE_ATTR(class, 0644, pfe_show_class, pfe_set_class);
-+static DEVICE_ATTR(tmu, 0644, pfe_show_tmu, pfe_set_tmu);
-+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
-+static DEVICE_ATTR(util, 0644, pfe_show_util, pfe_set_util);
-+#endif
-+static DEVICE_ATTR(bmu, 0444, pfe_show_bmu, NULL);
-+static DEVICE_ATTR(hif, 0444, pfe_show_hif, NULL);
-+static DEVICE_ATTR(gpi, 0444, pfe_show_gpi, NULL);
-+static DEVICE_ATTR(drops, 0644, pfe_show_drops, pfe_set_drops);
-+static DEVICE_ATTR(tmu0_queues, 0444, pfe_show_tmu0_queues, NULL);
-+static DEVICE_ATTR(tmu1_queues, 0444, pfe_show_tmu1_queues, NULL);
-+static DEVICE_ATTR(tmu2_queues, 0444, pfe_show_tmu2_queues, NULL);
-+static DEVICE_ATTR(tmu3_queues, 0444, pfe_show_tmu3_queues, NULL);
-+static DEVICE_ATTR(pfemem, 0444, pfe_show_pfemem, NULL);
-+static DEVICE_ATTR(fcs_revalidated, 0444, pfe_show_crc_revalidated, NULL);
-+
-+int pfe_sysfs_init(struct pfe *pfe)
-+{
-+	if (device_create_file(pfe->dev, &dev_attr_class))
-+		goto err_class;
-+
-+	if (device_create_file(pfe->dev, &dev_attr_tmu))
-+		goto err_tmu;
-+
-+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
-+	if (device_create_file(pfe->dev, &dev_attr_util))
-+		goto err_util;
-+#endif
-+
-+	if (device_create_file(pfe->dev, &dev_attr_bmu))
-+		goto err_bmu;
-+
-+	if (device_create_file(pfe->dev, &dev_attr_hif))
-+		goto err_hif;
-+
-+	if (device_create_file(pfe->dev, &dev_attr_gpi))
-+		goto err_gpi;
-+
-+	if (device_create_file(pfe->dev, &dev_attr_drops))
-+		goto err_drops;
-+
-+	if (device_create_file(pfe->dev, &dev_attr_tmu0_queues))
-+		goto err_tmu0_queues;
-+
-+	if (device_create_file(pfe->dev, &dev_attr_tmu1_queues))
-+		goto err_tmu1_queues;
-+
-+	if (device_create_file(pfe->dev, &dev_attr_tmu2_queues))
-+		goto err_tmu2_queues;
-+
-+	if (device_create_file(pfe->dev, &dev_attr_tmu3_queues))
-+		goto err_tmu3_queues;
-+
-+	if (device_create_file(pfe->dev, &dev_attr_pfemem))
-+		goto err_pfemem;
-+
-+	if (device_create_file(pfe->dev, &dev_attr_fcs_revalidated))
-+		goto err_crc_revalidated;
-+
-+#ifdef HIF_NAPI_STATS
-+	if (device_create_file(pfe->dev, &dev_attr_hif_napi_stats))
-+		goto err_hif_napi_stats;
-+#endif
-+
-+	return 0;
-+
-+#ifdef HIF_NAPI_STATS
-+err_hif_napi_stats:
-+	device_remove_file(pfe->dev, &dev_attr_fcs_revalidated);
-+#endif
-+
-+err_crc_revalidated:
-+	device_remove_file(pfe->dev, &dev_attr_pfemem);
-+
-+err_pfemem:
-+	device_remove_file(pfe->dev, &dev_attr_tmu3_queues);
-+
-+err_tmu3_queues:
-+	device_remove_file(pfe->dev, &dev_attr_tmu2_queues);
-+
-+err_tmu2_queues:
-+	device_remove_file(pfe->dev, &dev_attr_tmu1_queues);
-+
-+err_tmu1_queues:
-+	device_remove_file(pfe->dev, &dev_attr_tmu0_queues);
-+
-+err_tmu0_queues:
-+	device_remove_file(pfe->dev, &dev_attr_drops);
-+
-+err_drops:
-+	device_remove_file(pfe->dev, &dev_attr_gpi);
-+
-+err_gpi:
-+	device_remove_file(pfe->dev, &dev_attr_hif);
-+
-+err_hif:
-+	device_remove_file(pfe->dev, &dev_attr_bmu);
-+
-+err_bmu:
-+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
-+	device_remove_file(pfe->dev, &dev_attr_util);
-+
-+err_util:
-+#endif
-+	device_remove_file(pfe->dev, &dev_attr_tmu);
-+
-+err_tmu:
-+	device_remove_file(pfe->dev, &dev_attr_class);
-+
-+err_class:
-+	return -1;
-+}
-+
-+void pfe_sysfs_exit(struct pfe *pfe)
-+{
-+#ifdef HIF_NAPI_STATS
-+	device_remove_file(pfe->dev, &dev_attr_hif_napi_stats);
-+#endif
-+	device_remove_file(pfe->dev, &dev_attr_fcs_revalidated);
-+	device_remove_file(pfe->dev, &dev_attr_pfemem);
-+	device_remove_file(pfe->dev, &dev_attr_tmu3_queues);
-+	device_remove_file(pfe->dev, &dev_attr_tmu2_queues);
-+	device_remove_file(pfe->dev, &dev_attr_tmu1_queues);
-+	device_remove_file(pfe->dev, &dev_attr_tmu0_queues);
-+	device_remove_file(pfe->dev, &dev_attr_drops);
-+	device_remove_file(pfe->dev, &dev_attr_gpi);
-+	device_remove_file(pfe->dev, &dev_attr_hif);
-+	device_remove_file(pfe->dev, &dev_attr_bmu);
-+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
-+	device_remove_file(pfe->dev, &dev_attr_util);
-+#endif
-+	device_remove_file(pfe->dev, &dev_attr_tmu);
-+	device_remove_file(pfe->dev, &dev_attr_class);
-+}
---- /dev/null
-+++ b/drivers/staging/fsl_ppfe/pfe_sysfs.h
-@@ -0,0 +1,17 @@
-+/* SPDX-License-Identifier: GPL-2.0+ */
-+/*
-+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
-+ * Copyright 2017 NXP
-+ */
-+
-+#ifndef _PFE_SYSFS_H_
-+#define _PFE_SYSFS_H_
-+
-+#include <linux/proc_fs.h>
-+
-+u32 qm_read_drop_stat(u32 tmu, u32 queue, u32 *total_drops, int do_reset);
-+
-+int pfe_sysfs_init(struct pfe *pfe);
-+void pfe_sysfs_exit(struct pfe *pfe);
-+
-+#endif /* _PFE_SYSFS_H_ */
diff --git a/target/linux/layerscape/patches-5.15/702-phy-Add-2.5G-SGMII-interface-mode.patch b/target/linux/layerscape/patches-5.15/702-phy-Add-2.5G-SGMII-interface-mode.patch
deleted file mode 100644
index f1ce7cc0ad0fcc..00000000000000
--- a/target/linux/layerscape/patches-5.15/702-phy-Add-2.5G-SGMII-interface-mode.patch
+++ /dev/null
@@ -1,63 +0,0 @@
-From c918c472546afa83a619ae3cb1a9d7d346c6e288 Mon Sep 17 00:00:00 2001
-From: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
-Date: Wed, 29 Nov 2017 15:27:57 +0530
-Subject: [PATCH 154/173] phy: Add 2.5G SGMII interface mode
-
-Add 2.5G SGMII interface mode(PHY_INTERFACE_MODE_2500SGMII)
-in existing phy_interface list
-
-Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
----
- include/linux/phy.h | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/drivers/net/phy/phy-core.c
-+++ b/drivers/net/phy/phy-core.c
-@@ -136,6 +136,7 @@ int phy_interface_num_ports(phy_interfac
- 	case PHY_INTERFACE_MODE_RXAUI:
- 	case PHY_INTERFACE_MODE_XAUI:
- 	case PHY_INTERFACE_MODE_1000BASEKX:
-+	case PHY_INTERFACE_MODE_2500SGMII:
- 		return 1;
- 	case PHY_INTERFACE_MODE_QSGMII:
- 	case PHY_INTERFACE_MODE_QUSGMII:
---- a/drivers/net/phy/phylink.c
-+++ b/drivers/net/phy/phylink.c
-@@ -400,6 +400,7 @@ void phylink_get_linkmodes(unsigned long
- 		caps |= MAC_1000FD;
- 		break;
- 
-+	case PHY_INTERFACE_MODE_2500SGMII:
- 	case PHY_INTERFACE_MODE_2500BASEX:
- 		caps |= MAC_2500FD;
- 		break;
-@@ -654,6 +655,10 @@ static int phylink_parse_mode(struct phy
- 			phylink_set(pl->supported, 2500baseX_Full);
- 			break;
- 
-+		case PHY_INTERFACE_MODE_2500SGMII:
-+			phylink_set(pl->supported, 2500baseT_Full);
-+			break;
-+
- 		case PHY_INTERFACE_MODE_5GBASER:
- 			phylink_set(pl->supported, 5000baseT_Full);
- 			break;
---- a/include/linux/phy.h
-+++ b/include/linux/phy.h
-@@ -157,6 +157,7 @@ typedef enum {
- 	PHY_INTERFACE_MODE_10GKR,
- 	PHY_INTERFACE_MODE_QUSGMII,
- 	PHY_INTERFACE_MODE_1000BASEKX,
-+	PHY_INTERFACE_MODE_2500SGMII,
- 	PHY_INTERFACE_MODE_MAX,
- } phy_interface_t;
- 
-@@ -276,6 +277,8 @@ static inline const char *phy_modes(phy_
- 		return "100base-x";
- 	case PHY_INTERFACE_MODE_QUSGMII:
- 		return "qusgmii";
-+	case PHY_INTERFACE_MODE_2500SGMII:
-+		return "sgmii-2500";
- 	default:
- 		return "unknown";
- 	}
diff --git a/target/linux/layerscape/patches-5.15/703-net-dpaa2-mac-add-support-for-more-10G-modes.patch b/target/linux/layerscape/patches-5.15/703-net-dpaa2-mac-add-support-for-more-10G-modes.patch
deleted file mode 100644
index 0bd96f1f4f71dd..00000000000000
--- a/target/linux/layerscape/patches-5.15/703-net-dpaa2-mac-add-support-for-more-10G-modes.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From c314138bd045e050432158ab021160de3ba51c5e Mon Sep 17 00:00:00 2001
-From: Russell King <rmk+kernel@armlinux.org.uk>
-Date: Thu, 30 Jan 2020 22:42:38 +0000
-Subject: [PATCH 2/4] net: dpaa2-mac: add support for more 10G modes
-
-Phylink documentation says:
- * Note that the PHY may be able to transform from one connection
- * technology to another, so, eg, don't clear 1000BaseX just
- * because the MAC is unable to BaseX mode. This is more about
- * clearing unsupported speeds and duplex settings. The port modes
- * should not be cleared; phylink_set_port_modes() will help with this.
-
-So add the missing 10G modes.
-
-Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
----
- drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c | 6 ++++++
- 1 file changed, 6 insertions(+)
-
---- a/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c
-+++ b/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c
-@@ -140,6 +140,12 @@ static void dpaa2_mac_validate(struct ph
- 	case PHY_INTERFACE_MODE_10GBASER:
- 	case PHY_INTERFACE_MODE_USXGMII:
- 		phylink_set(mask, 10000baseT_Full);
-+		phylink_set(mask, 10000baseKR_Full);
-+		phylink_set(mask, 10000baseCR_Full);
-+		phylink_set(mask, 10000baseSR_Full);
-+		phylink_set(mask, 10000baseLR_Full);
-+		phylink_set(mask, 10000baseLRM_Full);
-+		phylink_set(mask, 10000baseER_Full);
- 		if (state->interface == PHY_INTERFACE_MODE_10GBASER)
- 			break;
- 		phylink_set(mask, 5000baseT_Full);
diff --git a/target/linux/layerscape/patches-5.15/704-dpaa2-eth-do-not-hold-rtnl_lock.patch b/target/linux/layerscape/patches-5.15/704-dpaa2-eth-do-not-hold-rtnl_lock.patch
deleted file mode 100644
index bff41aa2a478e6..00000000000000
--- a/target/linux/layerscape/patches-5.15/704-dpaa2-eth-do-not-hold-rtnl_lock.patch
+++ /dev/null
@@ -1,74 +0,0 @@
-From d5af37ae22f0364be9ded773d737dd6e5b207b10 Mon Sep 17 00:00:00 2001
-From: Ioana Ciornei <ioana.ciornei@nxp.com>
-Date: Thu, 21 Nov 2019 21:15:25 +0200
-Subject: [PATCH 3/4] dpaa2-eth: do not hold rtnl_lock on phylink_create() or
- _destroy()
-
-The rtnl_lock should not be held when calling phylink_create() or
-phylink_destroy() since it leads to the deadlock listed below:
-
-[   18.656576]  rtnl_lock+0x18/0x20
-[   18.659798]  sfp_bus_add_upstream+0x28/0x90
-[   18.663974]  phylink_create+0x2cc/0x828
-[   18.667803]  dpaa2_mac_connect+0x14c/0x2a8
-[   18.671890]  dpaa2_eth_connect_mac+0x94/0xd8
-
-Fix this by moving the _lock() and _unlock() calls just outside of
-phylink_of_phy_connect() and phylink_disconnect_phy().
-
-Fixes: 719479230893 ("dpaa2-eth: add MAC/PHY support through phylink")
-Reported-by: Russell King <linux@armlinux.org.uk>
-Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
-Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
----
- drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c | 4 ----
- drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c | 4 ++++
- 2 files changed, 4 insertions(+), 4 deletions(-)
-
---- a/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c
-+++ b/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c
-@@ -4215,12 +4215,10 @@ static irqreturn_t dpni_irq0_handler_thr
- 		dpaa2_eth_set_mac_addr(netdev_priv(net_dev));
- 		dpaa2_eth_update_tx_fqids(priv);
- 
--		rtnl_lock();
- 		if (dpaa2_eth_has_mac(priv))
- 			dpaa2_eth_disconnect_mac(priv);
- 		else
- 			dpaa2_eth_connect_mac(priv);
--		rtnl_unlock();
- 	}
- 
- 	return IRQ_HANDLED;
-@@ -4516,9 +4514,7 @@ static int dpaa2_eth_remove(struct fsl_m
- #endif
- 
- 	unregister_netdev(net_dev);
--	rtnl_lock();
- 	dpaa2_eth_disconnect_mac(priv);
--	rtnl_unlock();
- 
- 	dpaa2_eth_dl_port_del(priv);
- 	dpaa2_eth_dl_traps_unregister(priv);
---- a/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c
-+++ b/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c
-@@ -357,7 +357,9 @@ int dpaa2_mac_connect(struct dpaa2_mac *
- 	if (mac->pcs)
- 		phylink_set_pcs(mac->phylink, &mac->pcs->pcs);
- 
-+	rtnl_lock();
- 	err = phylink_fwnode_phy_connect(mac->phylink, dpmac_node, 0);
-+	rtnl_unlock();
- 	if (err) {
- 		netdev_err(net_dev, "phylink_fwnode_phy_connect() = %d\n", err);
- 		goto err_phylink_destroy;
-@@ -378,7 +380,9 @@ void dpaa2_mac_disconnect(struct dpaa2_m
- 	if (!mac->phylink)
- 		return;
- 
-+	rtnl_lock();
- 	phylink_disconnect_phy(mac->phylink);
-+	rtnl_unlock();
- 	phylink_destroy(mac->phylink);
- 	dpaa2_pcs_destroy(mac);
- }
diff --git a/target/linux/layerscape/patches-6.1/702-phy-Add-2.5G-SGMII-interface-mode.patch b/target/linux/layerscape/patches-6.1/702-phy-Add-2.5G-SGMII-interface-mode.patch
index 6af915da906538..8beee8f2dc1af7 100644
--- a/target/linux/layerscape/patches-6.1/702-phy-Add-2.5G-SGMII-interface-mode.patch
+++ b/target/linux/layerscape/patches-6.1/702-phy-Add-2.5G-SGMII-interface-mode.patch
@@ -25,7 +25,7 @@ Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
  	case PHY_INTERFACE_MODE_QUSGMII:
 --- a/drivers/net/phy/phylink.c
 +++ b/drivers/net/phy/phylink.c
-@@ -200,6 +200,7 @@ static int phylink_interface_max_speed(p
+@@ -218,6 +218,7 @@ static int phylink_interface_max_speed(p
  		return SPEED_1000;
  
  	case PHY_INTERFACE_MODE_2500BASEX:
diff --git a/target/linux/layerscape/patches-6.1/704-net-phylink-treat-PHY_INTERFACE_MODE_2500SGMII-in-ph.patch b/target/linux/layerscape/patches-6.1/704-net-phylink-treat-PHY_INTERFACE_MODE_2500SGMII-in-ph.patch
index 265756ea703263..1a1d7a0ac789de 100644
--- a/target/linux/layerscape/patches-6.1/704-net-phylink-treat-PHY_INTERFACE_MODE_2500SGMII-in-ph.patch
+++ b/target/linux/layerscape/patches-6.1/704-net-phylink-treat-PHY_INTERFACE_MODE_2500SGMII-in-ph.patch
@@ -32,7 +32,7 @@ Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
 
 --- a/drivers/net/phy/phylink.c
 +++ b/drivers/net/phy/phylink.c
-@@ -487,6 +487,7 @@ unsigned long phylink_get_capabilities(p
+@@ -505,6 +505,7 @@ unsigned long phylink_get_capabilities(p
  		break;
  
  	case PHY_INTERFACE_MODE_2500BASEX:
diff --git a/target/linux/malta/Makefile b/target/linux/malta/Makefile
index bff63a1dd4bd2c..f98aedf577f3f2 100644
--- a/target/linux/malta/Makefile
+++ b/target/linux/malta/Makefile
@@ -10,8 +10,7 @@ SUBTARGETS:=le be le64 be64
 INITRAMFS_EXTRA_FILES:=
 FEATURES:=cpiogz ext4 ramdisk squashfs targz
 
-KERNEL_PATCHVER:=5.15
-KERNEL_TESTING_PATCHVER:=6.1
+KERNEL_PATCHVER:=6.1
 
 include $(INCLUDE_DIR)/target.mk
 
diff --git a/target/linux/malta/config-5.15 b/target/linux/malta/config-5.15
deleted file mode 100644
index bbedaf56336d37..00000000000000
--- a/target/linux/malta/config-5.15
+++ /dev/null
@@ -1,263 +0,0 @@
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MAY_HAVE_PC_FDC=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
-CONFIG_ARCH_MMAP_RND_BITS_MAX=15
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
-CONFIG_ATA=y
-CONFIG_ATA_PIIX=y
-CONFIG_BLK_DEV_BSG=y
-CONFIG_BLK_DEV_BSGLIB=y
-CONFIG_BLK_DEV_BSG_COMMON=y
-# CONFIG_BLK_DEV_INITRD is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BOARD_SCACHE=y
-CONFIG_BOOT_ELF32=y
-CONFIG_BUILTIN_DTB=y
-CONFIG_CEVT_R4K=y
-CONFIG_CLKBLD_I8253=y
-CONFIG_CLKEVT_I8253=y
-CONFIG_CLKSRC_I8253=y
-CONFIG_CLKSRC_MIPS_GIC=y
-CONFIG_CLOCKSOURCE_WATCHDOG=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_CPU_GENERIC_DUMP_TLB=y
-CONFIG_CPU_HAS_PREFETCH=y
-# CONFIG_CPU_HAS_SMARTMIPS is not set
-CONFIG_CPU_HAS_SYNC=y
-# CONFIG_CPU_MICROMIPS is not set
-# CONFIG_CPU_MIPS32 is not set
-# CONFIG_CPU_MIPS32_3_5_FEATURES is not set
-# CONFIG_CPU_MIPS32_R1 is not set
-# CONFIG_CPU_MIPS32_R2 is not set
-# CONFIG_CPU_MIPS32_R5 is not set
-# CONFIG_CPU_MIPS32_R5_FEATURES is not set
-# CONFIG_CPU_MIPS32_R6 is not set
-# CONFIG_CPU_MIPS64_R1 is not set
-# CONFIG_CPU_MIPS64_R2 is not set
-# CONFIG_CPU_MIPS64_R6 is not set
-# CONFIG_CPU_MIPSR1 is not set
-# CONFIG_CPU_MIPSR2 is not set
-# CONFIG_CPU_MIPSR2_IRQ_EI is not set
-# CONFIG_CPU_MIPSR2_IRQ_VI is not set
-CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
-# CONFIG_CPU_NEVADA is not set
-CONFIG_CPU_R4K_CACHE_TLB=y
-# CONFIG_CPU_RM7000 is not set
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_CRC16=y
-CONFIG_CRYPTO_CRC32=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CSRC_R4K=y
-CONFIG_DMA_NONCOHERENT=y
-CONFIG_DNOTIFY=y
-CONFIG_DTC=y
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_EXT4_FS=y
-CONFIG_F2FS_FS=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FS_POSIX_ACL=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_FIND_FIRST_BIT=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IOMAP=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_ISA_DMA=y
-CONFIG_GENERIC_LIB_ASHLDI3=y
-CONFIG_GENERIC_LIB_ASHRDI3=y
-CONFIG_GENERIC_LIB_CMPDI2=y
-CONFIG_GENERIC_LIB_LSHRDI3=y
-CONFIG_GENERIC_LIB_UCMPDI2=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GLOB=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDWARE_WATCHPOINTS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HW_CONSOLE=y
-CONFIG_I8253=y
-CONFIG_I8253_LOCK=y
-CONFIG_I8259=y
-CONFIG_INPUT=y
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_MIPS_CPU=y
-CONFIG_IRQ_WORK=y
-CONFIG_ISA_DMA_API=y
-CONFIG_JBD2=y
-CONFIG_JFFS2_FS_POSIX_ACL=y
-CONFIG_JFFS2_FS_SECURITY=y
-CONFIG_KALLSYMS=y
-CONFIG_KERNEL_GZIP=y
-# CONFIG_KERNEL_XZ is not set
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_MD=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGRATION=y
-CONFIG_MIPS=y
-CONFIG_MIPS_ASID_BITS=8
-CONFIG_MIPS_ASID_SHIFT=0
-CONFIG_MIPS_BONITO64=y
-CONFIG_MIPS_CLOCK_VSYSCALL=y
-CONFIG_MIPS_CM=y
-CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y
-CONFIG_MIPS_CPC=y
-CONFIG_MIPS_CPU_SCACHE=y
-CONFIG_MIPS_EBPF_JIT=y
-CONFIG_MIPS_EXTERNAL_TIMER=y
-CONFIG_MIPS_GIC=y
-CONFIG_MIPS_L1_CACHE_SHIFT=6
-CONFIG_MIPS_L1_CACHE_SHIFT_6=y
-CONFIG_MIPS_LD_CAN_LINK_VDSO=y
-CONFIG_MIPS_MALTA=y
-CONFIG_MIPS_MSC=y
-CONFIG_MIPS_MT=y
-CONFIG_MIPS_MT_FPAFF=y
-CONFIG_MIPS_MT_SMP=y
-CONFIG_MIPS_NO_APPENDED_DTB=y
-CONFIG_MIPS_NR_CPU_NR_MAP=2
-CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MTD_CFI_STAA=y
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NLS=y
-CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
-CONFIG_NO_HZ=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=2
-CONFIG_NVMEM=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_PADATA=y
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_PATA_LEGACY=y
-CONFIG_PATA_TIMINGS=y
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DRIVERS_LEGACY=y
-CONFIG_PCI_GT64XXX_PCI0=y
-CONFIG_PCSPKR_PLATFORM=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_PIIX4_POWEROFF=y
-CONFIG_POWER_RESET_SYSCON=y
-CONFIG_PRINT_QUOTA_WARNING=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_QFMT_V2=y
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_QUEUED_SPINLOCKS=y
-CONFIG_QUOTA=y
-CONFIG_QUOTACTL=y
-CONFIG_QUOTA_TREE=y
-CONFIG_RATIONAL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_RELAY=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_MC146818_LIB=y
-CONFIG_SATA_HOST=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-CONFIG_SECCOMP=y
-CONFIG_SECCOMP_FILTER=y
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIO=y
-CONFIG_SERIO_SERPORT=y
-CONFIG_SG_POOL=y
-CONFIG_SMP=y
-CONFIG_SMP_UP=y
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SRCU=y
-CONFIG_SWAP_IO_SPACE=y
-CONFIG_SYNC_R4K=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_SYSFS_DEPRECATED_V2=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_CPU_MIPS32_R2=y
-CONFIG_SYS_HAS_CPU_MIPS32_R3_5=y
-CONFIG_SYS_HAS_CPU_MIPS32_R5=y
-CONFIG_SYS_HAS_CPU_MIPS32_R6=y
-CONFIG_SYS_HAS_CPU_MIPS64_R1=y
-CONFIG_SYS_HAS_CPU_MIPS64_R2=y
-CONFIG_SYS_HAS_CPU_MIPS64_R6=y
-CONFIG_SYS_HAS_CPU_NEVADA=y
-CONFIG_SYS_HAS_CPU_RM7000=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
-CONFIG_SYS_SUPPORTS_HIGHMEM=y
-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_SYS_SUPPORTS_MICROMIPS=y
-CONFIG_SYS_SUPPORTS_MIPS16=y
-CONFIG_SYS_SUPPORTS_MIPS_CMP=y
-CONFIG_SYS_SUPPORTS_MIPS_CPS=y
-CONFIG_SYS_SUPPORTS_MULTITHREADING=y
-CONFIG_SYS_SUPPORTS_RELOCATABLE=y
-CONFIG_SYS_SUPPORTS_SCHED_SMT=y
-CONFIG_SYS_SUPPORTS_SMARTMIPS=y
-CONFIG_SYS_SUPPORTS_SMP=y
-CONFIG_SYS_SUPPORTS_VPE_LOADER=y
-CONFIG_SYS_SUPPORTS_ZBOOT=y
-CONFIG_TARGET_ISA_REV=1
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_OF=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-CONFIG_VXFS_FS=y
-CONFIG_WAR_ICACHE_REFILLS=y
-CONFIG_XPS=y
diff --git a/target/linux/mediatek/Makefile b/target/linux/mediatek/Makefile
index f73f2daef615d9..279c167b832593 100644
--- a/target/linux/mediatek/Makefile
+++ b/target/linux/mediatek/Makefile
@@ -8,8 +8,7 @@ BOARDNAME:=MediaTek Ralink ARM
 SUBTARGETS:=mt7622 mt7623 mt7629 filogic
 FEATURES:=dt-overlay emmc fpu gpio nand pci pcie rootfs-part separate_ramdisk squashfs usb
 
-KERNEL_PATCHVER:=5.15
-KERNEL_TESTING_PATCHVER:=6.1
+KERNEL_PATCHVER:=6.1
 
 include $(INCLUDE_DIR)/target.mk
 DEFAULT_PACKAGES += \
diff --git a/target/linux/mediatek/base-files/etc/uci-defaults/99_fwenv-store-ethaddr.sh b/target/linux/mediatek/base-files/etc/uci-defaults/99_fwenv-store-ethaddr.sh
index 5dec158a93f41c..f58f709e1c42bf 100644
--- a/target/linux/mediatek/base-files/etc/uci-defaults/99_fwenv-store-ethaddr.sh
+++ b/target/linux/mediatek/base-files/etc/uci-defaults/99_fwenv-store-ethaddr.sh
@@ -9,7 +9,8 @@ unielec,u7623-02)
 	[ -z "$(fw_printenv -n ethaddr 2>/dev/null)" ] &&
 		fw_setenv ethaddr "$(cat /sys/class/net/eth0/address)"
 	;;
-bananapi,bpi-r3)
+bananapi,bpi-r3|\
+bananapi,bpi-r3-mini)
 	[ -z "$(fw_printenv -n ethaddr 2>/dev/null)" ] &&
 		fw_setenv ethaddr "$(cat /sys/class/net/eth0/address)"
 	[ -z "$(fw_printenv -n eth1addr 2>/dev/null)" ] &&
diff --git a/target/linux/mediatek/base-files/lib/preinit/05_set_preinit_iface b/target/linux/mediatek/base-files/lib/preinit/05_set_preinit_iface
index 9daf1ef26b8d95..2bff09b2b2bc32 100644
--- a/target/linux/mediatek/base-files/lib/preinit/05_set_preinit_iface
+++ b/target/linux/mediatek/base-files/lib/preinit/05_set_preinit_iface
@@ -9,10 +9,21 @@ set_preinit_iface() {
 		ip link set eth1 up
 		ifname=eth1
 		;;
-	ubnt,unifi-6-lr)
+	cudy,re3000-v1|\
+	ubnt,unifi-6-lr|\
+	zyxel,nwa50ax-pro)
 		ip link set eth0 up
 		ifname=eth0
 		;;
+	xiaomi,mi-router-ax3000t|\
+	xiaomi,mi-router-ax3000t-ubootmod|\
+	xiaomi,mi-router-wr30u-stock|\
+	xiaomi,mi-router-wr30u-ubootmod|\
+	xiaomi,redmi-router-ax6000-stock|\
+	xiaomi,redmi-router-ax6000-ubootmod)
+		ip link set eth0 up
+		ifname=lan4
+		;;
 	*)
 		ip link set eth0 up
 		ifname=lan1
diff --git a/target/linux/mediatek/dts/mt7622-buffalo-wsr.dtsi b/target/linux/mediatek/dts/mt7622-buffalo-wsr.dtsi
index e77f83d354bb0c..2f0540f4118a09 100644
--- a/target/linux/mediatek/dts/mt7622-buffalo-wsr.dtsi
+++ b/target/linux/mediatek/dts/mt7622-buffalo-wsr.dtsi
@@ -25,42 +25,36 @@
 		compatible = "gpio-leds";
 
 		led-0 {
-			label = "amber:wireless";
 			gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_AMBER>;
 			function = LED_FUNCTION_WLAN;
 		};
 
 		power_amber: led-1 {
-			label = "amber:power";
 			gpios = <&pio 3 GPIO_ACTIVE_LOW>;
 			color = <LED_COLOR_ID_AMBER>;
 			function = LED_FUNCTION_POWER;
 		};
 
 		power_green: led-2 {
-			label = "green:power";
 			gpios = <&pio 4 GPIO_ACTIVE_LOW>;
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_POWER;
 		};
 
 		led-3 {
-			label = "green:wireless";
 			gpios = <&pio 15 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_WLAN;
 		};
 
 		led-4 {
-			label = "green:internet";
 			gpios = <&pio 19 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_WAN;
 		};
 
 		led-5 {
-			label = "green:router";
 			gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_INDICATOR;
diff --git a/target/linux/mediatek/dts/mt7622-elecom-wrc-x3200gst3.dts b/target/linux/mediatek/dts/mt7622-elecom-wrc-x3200gst3.dts
index c775d998181e28..f3a688b2d684b4 100644
--- a/target/linux/mediatek/dts/mt7622-elecom-wrc-x3200gst3.dts
+++ b/target/linux/mediatek/dts/mt7622-elecom-wrc-x3200gst3.dts
@@ -33,14 +33,12 @@
 		compatible = "gpio-leds";
 
 		led-0 {
-			label = "red:wps";
 			gpios = <&pio 47 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_RED>;
 			function = LED_FUNCTION_WPS;
 		};
 
 		led_power_red: led-1 {
-			label = "red:power";
 			gpios = <&pio 48 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_RED>;
 			function = LED_FUNCTION_POWER;
@@ -48,7 +46,6 @@
 		};
 
 		led_power_green: led-2 {
-			label = "green:power";
 			gpios = <&pio 49 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_POWER;
@@ -56,7 +53,6 @@
 		};
 
 		led-3 {
-			label = "blue:power";
 			gpios = <&pio 50 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_BLUE>;
 			function = LED_FUNCTION_POWER;
@@ -64,7 +60,6 @@
 		};
 
 		led-4 {
-			label = "white:wlan2g";
 			gpios = <&pio 85 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_WHITE>;
 			function = LED_FUNCTION_WLAN;
@@ -73,7 +68,6 @@
 		};
 
 		led-5 {
-			label = "white:wlan5g";
 			gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_WHITE>;
 			function = LED_FUNCTION_WLAN;
diff --git a/target/linux/mediatek/dts/mt7622-linksys-e8450-ubi.dts b/target/linux/mediatek/dts/mt7622-linksys-e8450-ubi.dts
index e78db1de6cf41e..e2b7268e857145 100644
--- a/target/linux/mediatek/dts/mt7622-linksys-e8450-ubi.dts
+++ b/target/linux/mediatek/dts/mt7622-linksys-e8450-ubi.dts
@@ -10,6 +10,11 @@
 	aliases {
 		label-mac-device = &wan;
 	};
+
+	chosen {
+		rootdisk = <&ubi_rootfs>;
+		bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512 ubi.block=0,fit root=/dev/fit0";
+	};
 };
 
 &snand {
@@ -25,45 +30,70 @@
 		};
 
 		partition@80000 {
-			label = "fip";
-			reg = <0x80000 0x140000>;
-			read-only;
-		};
+			label = "ubi";
+			reg = <0x80000 0x7f80000>;
+			compatible = "linux,ubi";
 
-		factory: partition@1c0000 {
-			label = "factory";
-			reg = <0x1c0000 0x100000>;
-			read-only;
+			volumes {
+				ubi-volume-ubootenv {
+					volname = "ubootenv";
+					nvmem-layout {
+						compatible = "u-boot,env-redundant-bool-layout";
+					};
+				};
 
-			nvmem-layout {
-				compatible = "fixed-layout";
-				#address-cells = <1>;
-				#size-cells = <1>;
+				ubi-volume-ubootenv2 {
+					volname = "ubootenv2";
+					nvmem-layout {
+						compatible = "u-boot,env-redundant-bool-layout";
+					};
+				};
 
-				macaddr_factory_7fff4: macaddr@7fff4 {
-					reg = <0x7fff4 0x6>;
+				ubi_rootfs: ubi-volume-fit {
+					volname = "fit";
 				};
 
-				macaddr_factory_7fffa: macaddr@7fffa {
-					reg = <0x7fffa 0x6>;
+				ubi_factory: ubi-volume-factory {
+					volname = "factory";
 				};
 			};
 		};
+	};
+};
+
+&ubi_factory {
+	nvmem-layout {
+		compatible = "fixed-layout";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		eeprom_factory_0: eeprom@0 {
+			reg = <0x0 0x4da8>; /* actual length 0x400 */
+		};
 
-		partition@300000 {
-			label = "ubi";
-			reg = <0x300000 0x7d00000>;
+		eeprom_factory_5000: eeprom@5000 {
+			reg = <0x5000 0xe00>;
+		};
+
+		macaddr_factory_7fff4: macaddr@7fff4 {
+			reg = <0x7fff4 0x6>;
+		};
+
+		macaddr_factory_7fffa: macaddr@7fffa {
+			reg = <0x7fffa 0x6>;
 		};
 	};
 };
 
 &wmac {
-	mediatek,mtd-eeprom = <&factory 0x0>;
+	nvmem-cells = <&eeprom_factory_0>;
+	nvmem-cell-names = "eeprom";
 	status = "okay";
 };
 
 &wmac1 {
-	mediatek,mtd-eeprom = <&factory 0x5000>;
+	nvmem-cells = <&eeprom_factory_5000>;
+	nvmem-cell-names = "eeprom";
 };
 
 &gmac0 {
diff --git a/target/linux/mediatek/dts/mt7622-rfb1-ubi.dts b/target/linux/mediatek/dts/mt7622-rfb1-ubi.dts
index 0f6d9bbc50f8b4..721695227ab9b0 100644
--- a/target/linux/mediatek/dts/mt7622-rfb1-ubi.dts
+++ b/target/linux/mediatek/dts/mt7622-rfb1-ubi.dts
@@ -44,12 +44,12 @@
 
 			partition@200000 {
 				label = "kernel";
-				reg = <0x2c0000 0x400000>;
+				reg = <0x2c0000 0x600000>;
 			};
 
 			partition@6c0000 {
 				label = "ubi";
-				reg = <0x6c0000 0x6f00000>;
+				reg = <0x8c0000 0x6f00000>;
 			};
 
 			/delete-node/ partition@2200000;
diff --git a/target/linux/mediatek/dts/mt7622-totolink-a8000ru.dts b/target/linux/mediatek/dts/mt7622-totolink-a8000ru.dts
index 776d38d1e31dcb..5ec07128baaa76 100644
--- a/target/linux/mediatek/dts/mt7622-totolink-a8000ru.dts
+++ b/target/linux/mediatek/dts/mt7622-totolink-a8000ru.dts
@@ -2,6 +2,7 @@
 
 /dts-v1/;
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/gpio/gpio.h>
 
 #include "mt7622.dtsi"
@@ -57,7 +58,8 @@
 		compatible = "gpio-leds";
 
 		led_status: status_red {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&pio 81 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
diff --git a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v1-ubootmod.dts b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v1-ubootmod.dts
index 7a7a8a815911ea..5f62ed1a455029 100644
--- a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v1-ubootmod.dts
+++ b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v1-ubootmod.dts
@@ -5,6 +5,11 @@
 / {
 	model = "Ubiquiti UniFi 6 LR v1 (U-Boot mod)";
 	compatible = "ubnt,unifi-6-lr-v1-ubootmod", "mediatek,mt7622";
+
+	chosen {
+		rootdisk = <&rootdisk>;
+		bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512 console=ttyS0,115200n8 root=/dev/fit0";
+	};
 };
 
 &nor_partitions {
@@ -54,7 +59,7 @@
 		reg = <0x120000 0xee0000>;
 	};
 
-	partition@1000000 {
+	rootdisk: partition@1000000 {
 		compatible = "denx,fit";
 		label = "firmware";
 		reg = <0x1000000 0x3000000>;
diff --git a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v2-ubootmod.dts b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v2-ubootmod.dts
index 3a37d1d5004f0f..96effb8aab4117 100644
--- a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v2-ubootmod.dts
+++ b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v2-ubootmod.dts
@@ -5,6 +5,11 @@
 / {
 	model = "Ubiquiti UniFi 6 LR v2 (U-Boot mod)";
 	compatible = "ubnt,unifi-6-lr-v2-ubootmod", "mediatek,mt7622";
+
+	chosen {
+		rootdisk = <&rootdisk>;
+		bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512 console=ttyS0,115200n8 root=/dev/fit0";
+	};
 };
 
 &nor_partitions {
@@ -54,7 +59,7 @@
 		reg = <0x120000 0xee0000>;
 	};
 
-	partition@1000000 {
+	rootdisk: partition@1000000 {
 		compatible = "denx,fit";
 		label = "firmware";
 		reg = <0x1000000 0x3000000>;
diff --git a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v3-ubootmod.dts b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v3-ubootmod.dts
index e91aaa63f58bdf..ec98dd262cfb36 100644
--- a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v3-ubootmod.dts
+++ b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v3-ubootmod.dts
@@ -5,6 +5,11 @@
 / {
 	model = "Ubiquiti UniFi 6 LR v3 (U-Boot mod)";
 	compatible = "ubnt,unifi-6-lr-v3-ubootmod", "mediatek,mt7622";
+
+	chosen {
+		rootdisk = <&rootdisk>;
+		bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512 console=ttyS0,115200n8 root=/dev/fit0";
+	};
 };
 
 &nor_partitions {
@@ -54,7 +59,7 @@
 		reg = <0x120000 0xee0000>;
 	};
 
-	partition@1000000 {
+	rootdisk: partition@1000000 {
 		compatible = "denx,fit";
 		label = "firmware";
 		reg = <0x1000000 0x3000000>;
diff --git a/target/linux/mediatek/dts/mt7622-xiaomi-redmi-router-ax6s.dts b/target/linux/mediatek/dts/mt7622-xiaomi-redmi-router-ax6s.dts
index dcf851b2740a38..01365a278da6d1 100644
--- a/target/linux/mediatek/dts/mt7622-xiaomi-redmi-router-ax6s.dts
+++ b/target/linux/mediatek/dts/mt7622-xiaomi-redmi-router-ax6s.dts
@@ -2,6 +2,7 @@
 /dts-v1/;
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/gpio/gpio.h>
 
 #include "mt7622.dtsi"
@@ -32,12 +33,14 @@
 		compatible = "gpio-leds";
 
 		led_power_blue: power_blue {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&pio 18 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_amber: power_amber {
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&pio 17 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/mediatek/dts/mt7623a-unielec-u7623-02.dts b/target/linux/mediatek/dts/mt7623a-unielec-u7623-02.dts
index bcd81ba6da75cc..75ee0723ece6ca 100644
--- a/target/linux/mediatek/dts/mt7623a-unielec-u7623-02.dts
+++ b/target/linux/mediatek/dts/mt7623a-unielec-u7623-02.dts
@@ -9,4 +9,26 @@
 / {
 	model = "UniElec U7623-02 eMMC";
 	compatible = "unielec,u7623-02", "mediatek,mt7623";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+		bootargs = "earlycon=uart8250,mmio32,0x11004000 root=/dev/fit0";
+		rootdisk = <&emmc_rootdisk>;
+	};
+};
+
+&mmc0 {
+	card@0 {
+		compatible = "mmc-card";
+		reg = <0>;
+
+		block {
+			compatible = "block-device";
+			partitions {
+				emmc_rootdisk: block-partition-env {
+					partno = <3>;
+				};
+			};
+		};
+	};
 };
diff --git a/target/linux/mediatek/dts/mt7629-iptime-a6004mx.dts b/target/linux/mediatek/dts/mt7629-iptime-a6004mx.dts
index 5b1b3083a06658..78286714eafa6f 100644
--- a/target/linux/mediatek/dts/mt7629-iptime-a6004mx.dts
+++ b/target/linux/mediatek/dts/mt7629-iptime-a6004mx.dts
@@ -2,6 +2,7 @@
 
 /dts-v1/;
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include "mt7629.dtsi"
 
 / {
@@ -25,7 +26,8 @@
 		compatible = "gpio-leds";
 
 		led_cpu: cpu {
-			label = "orange:cpu";
+			function = LED_FUNCTION_CPU;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&pio 57 GPIO_ACTIVE_LOW>;
 		};
 
@@ -42,7 +44,8 @@
 		};
 
 		wan {
-			label = "orange:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&pio 12 GPIO_ACTIVE_HIGH>;
 		};
 	};
diff --git a/target/linux/mediatek/dts/mt7629-netgear-ex6250-v2.dts b/target/linux/mediatek/dts/mt7629-netgear-ex6250-v2.dts
index 5645ad799e9247..99d3a7cefbbaf8 100644
--- a/target/linux/mediatek/dts/mt7629-netgear-ex6250-v2.dts
+++ b/target/linux/mediatek/dts/mt7629-netgear-ex6250-v2.dts
@@ -2,6 +2,7 @@
 
 /dts-v1/;
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include "mt7629.dtsi"
 
 / {
@@ -53,12 +54,14 @@
 		compatible = "gpio-leds";
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pio 21 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_red: power_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&pio 61 GPIO_ACTIVE_LOW>;
 		};
 
@@ -83,7 +86,8 @@
 		};
 
 		wps_green {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pio 57 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/mediatek/dts/mt7629-tplink_eap225-v5.dts b/target/linux/mediatek/dts/mt7629-tplink_eap225-v5.dts
index 5eab714fdac3c1..bab3ad5737383b 100644
--- a/target/linux/mediatek/dts/mt7629-tplink_eap225-v5.dts
+++ b/target/linux/mediatek/dts/mt7629-tplink_eap225-v5.dts
@@ -2,6 +2,7 @@
 
 /dts-v1/;
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include "mt7629.dtsi"
 
 / {
@@ -35,13 +36,15 @@
 		compatible = "gpio-leds";
 
 		led_status_green: status_green {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pio 55 GPIO_ACTIVE_HIGH>;
 			default-state = "on";
 		};
 
 		led_status_amber: status_amber {
-			label = "amber:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&pio 56 GPIO_ACTIVE_HIGH>;
 		};
 	};
diff --git a/target/linux/mediatek/dts/mt7981a-comfast-cf-e393ax.dts b/target/linux/mediatek/dts/mt7981a-comfast-cf-e393ax.dts
new file mode 100644
index 00000000000000..6ff061b1e9cc89
--- /dev/null
+++ b/target/linux/mediatek/dts/mt7981a-comfast-cf-e393ax.dts
@@ -0,0 +1,247 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+/dts-v1/;
+#include "mt7981.dtsi"
+
+/ {
+	model = "COMFAST CF-E393AX";
+	compatible = "comfast,cf-e393ax", "mediatek,mt7981";
+
+	aliases {
+		serial0 = &uart0;
+		led-boot = &led_red;
+		led-failsafe = &led_red;
+		led-running = &led_blue;
+		led-upgrade = &led_green;
+	};
+
+	chosen {
+		bootargs-override = "console=ttyS0,115200n8";
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory {
+		reg = <0 0x40000000 0 0x10000000>; // 256mb
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "reset";
+			linux,code = <KEY_RESTART>;
+			gpios = <&pio 1 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_blue: blue {
+			gpios = <&pio 8 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_BLUE>;
+			function = LED_FUNCTION_STATUS;
+		};
+
+		led_red: red {
+			gpios = <&pio 34 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_RED>;
+			function = LED_FUNCTION_STATUS;
+		};
+
+		led_green: green {
+			gpios = <&pio 35 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_STATUS;
+		};
+	};
+};
+
+&eth {
+	status = "okay";
+
+	gmac0: mac@0 {
+		/* LAN */
+		compatible = "mediatek,eth-mac";
+		reg = <0>;
+		phy-mode = "2500base-x";
+		nvmem-cells = <&macaddr_factory_e000 0>;
+		nvmem-cell-names = "mac-address";
+
+		fixed-link {
+			speed = <2500>;
+			full-duplex;
+			pause;
+		};
+	};
+
+	gmac1: mac@1 {
+		/* WAN */
+		compatible = "mediatek,eth-mac";
+		reg = <1>;
+		phy-mode = "gmii";
+		phy-handle = <&int_gbe_phy>;
+		nvmem-cells = <&macaddr_factory_e000 1>;
+		nvmem-cell-names = "mac-address";
+	};
+};
+
+&mdio_bus {
+	switch: switch@1f {
+		compatible = "mediatek,mt7531";
+		reg = <31>;
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		interrupt-parent = <&pio>;
+		interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
+		reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&crypto {
+	status = "okay";
+};
+
+&pio {
+	spi0_flash_pins: spi0-pins {
+		mux {
+			function = "spi";
+			groups = "spi0", "spi0_wp_hold";
+		};
+		conf-pu {
+			pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
+			drive-strength = <MTK_DRIVE_8mA>;
+			bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
+		};
+		conf-pd {
+			pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
+			drive-strength = <MTK_DRIVE_8mA>;
+			bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
+		};
+	};
+
+};
+
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0_flash_pins>;
+	cs-gpios = <0>, <0>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	spi_nand: spi_nand@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-nand";
+		reg = <1>;
+		spi-max-frequency = <52000000>;
+
+		spi-cal-enable;
+		spi-cal-mode = "read-data";
+		spi-cal-datalen = <7>;
+		spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>;
+		spi-cal-addrlen = <5>;
+		spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>;
+
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+		mediatek,nmbm;
+		mediatek,bmt-max-ratio = <1>;
+		mediatek,bmt-max-reserved-blocks = <64>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "BL2";
+				reg = <0x00000 0x0100000>;
+				read-only;
+			};
+
+			partition@100000 {
+				label = "u-boot-env";
+				reg = <0x0100000 0x0080000>;
+				read-only;
+			};
+
+			factory: partition@180000 {
+				label = "Factory";
+				reg = <0x180000 0x0200000>;
+				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					eeprom_factory_0: eeprom@0 {
+						reg = <0x0 0x1000>;
+					};
+
+					macaddr_factory_e000: macaddr@e000 {
+						compatible = "mac-base";
+						reg = <0xe000 0x6>;
+						#nvmem-cell-cells = <1>;
+					};
+				};
+			};
+
+			partition@380000 {
+				label = "FIP";
+				reg = <0x380000 0x0200000>;
+				read-only;
+			};
+
+			partition@580000 {
+				label = "ubi";
+				reg = <0x580000 0x4000000>;
+				compatible = "linux,ubi";
+			};
+		};
+	};
+};
+
+&switch {
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+			label = "lan1";
+		};
+
+		port@6 {
+			reg = <6>;
+			label = "cpu";
+			ethernet = <&gmac0>;
+			phy-mode = "2500base-x";
+
+			fixed-link {
+				speed = <2500>;
+				full-duplex;
+				pause;
+			};
+		};
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&watchdog {
+	status = "okay";
+};
+
+&wifi {
+	status = "okay";
+	nvmem-cells = <&eeprom_factory_0>;
+	nvmem-cell-names = "eeprom";
+};
+
diff --git a/target/linux/mediatek/dts/mt7981b-cetron-ct3003.dts b/target/linux/mediatek/dts/mt7981b-cetron-ct3003.dts
index 281c96e275ef5b..919c208918e0d1 100644
--- a/target/linux/mediatek/dts/mt7981b-cetron-ct3003.dts
+++ b/target/linux/mediatek/dts/mt7981b-cetron-ct3003.dts
@@ -3,6 +3,7 @@
 /dts-v1/;
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 #include "mt7981.dtsi"
 
@@ -47,12 +48,14 @@
 		compatible = "gpio-leds";
 
 		led_status_red: led_status_red {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&pio 3 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status_green: led_status_green {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pio 7 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/mediatek/dts/mt7981b-cmcc-rax3000m.dts b/target/linux/mediatek/dts/mt7981b-cmcc-rax3000m.dts
index 3f330f40fae43e..c8db5b58f54329 100644
--- a/target/linux/mediatek/dts/mt7981b-cmcc-rax3000m.dts
+++ b/target/linux/mediatek/dts/mt7981b-cmcc-rax3000m.dts
@@ -6,6 +6,7 @@
 /dts-v1/;
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 #include "mt7981.dtsi"
 
@@ -50,17 +51,20 @@
 		compatible = "gpio-leds";
 
 		green_led: led-0 {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pio 9 GPIO_ACTIVE_LOW>;
 		};
 
 		led-1 {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&pio 12 GPIO_ACTIVE_LOW>;
 		};
 
 		red_led: led-2 {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&pio 35 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/mediatek/dts/mt7981b-confiabits-mt7981.dts b/target/linux/mediatek/dts/mt7981b-confiabits-mt7981.dts
index 8f4dc23fb4b594..8b9c7a75477d65 100644
--- a/target/linux/mediatek/dts/mt7981b-confiabits-mt7981.dts
+++ b/target/linux/mediatek/dts/mt7981b-confiabits-mt7981.dts
@@ -58,7 +58,6 @@
 		};
 
 		led_power: led-power {
-			label = "blue:power"; // can be removed once #13837 is merged
 			color = <LED_COLOR_ID_BLUE>;
 			function = LED_FUNCTION_POWER;
 			gpios = <&pio 7 GPIO_ACTIVE_LOW>;
diff --git a/target/linux/mediatek/dts/mt7981b-cudy-re3000-v1.dts b/target/linux/mediatek/dts/mt7981b-cudy-re3000-v1.dts
new file mode 100644
index 00000000000000..4025e5aaa3908b
--- /dev/null
+++ b/target/linux/mediatek/dts/mt7981b-cudy-re3000-v1.dts
@@ -0,0 +1,221 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+#include "mt7981.dtsi"
+
+/ {
+	model = "Cudy RE3000 v1";
+	compatible = "cudy,re3000-v1", "mediatek,mt7981";
+
+	aliases {
+		serial0 = &uart0;
+		label-mac-device = &gmac1;
+		led-boot = &led_status;
+		led-failsafe = &led_status;
+		led-running = &led_status;
+		led-upgrade = &led_status;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "reset";
+			linux,code = <KEY_RESTART>;
+			gpios = <&pio 1 GPIO_ACTIVE_LOW>;
+		};
+
+		wps {
+			label = "wps";
+			linux,code = <KEY_WPS_BUTTON>;
+			gpios = <&pio 0 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_status: led@0 {
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_WHITE>;
+			gpios = <&pio 10 GPIO_ACTIVE_LOW>;
+		};
+
+		led@1 {
+			label = "red:wifi5";
+			gpios = <&pio 7 GPIO_ACTIVE_LOW>;
+			linux,default-trigger = "phy1tpt";
+		};
+
+		led@2 {
+			label = "white:wifi2";
+			gpios = <&pio 6 GPIO_ACTIVE_LOW>;
+			linux,default-trigger = "phy0tpt";
+		};
+
+		led@3 {
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&pio 9 GPIO_ACTIVE_LOW>;
+		};
+
+		led@4 {
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_WHITE>;
+			gpios = <&pio 11 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&watchdog {
+	status = "okay";
+};
+
+&eth {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mdio_pins>;
+	status = "okay";
+
+	gmac1: mac@1 {
+		compatible = "mediatek,eth-mac";
+		reg = <1>;
+		phy-mode = "gmii";
+		phy-handle = <&int_gbe_phy>;
+		nvmem-cell-names = "mac-address";
+		nvmem-cells = <&macaddr_bdinfo_de00 0>;
+	};
+};
+
+&mdio_bus {
+	switch: switch@1f {
+		compatible = "mediatek,mt7531";
+		reg = <31>;
+		reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&spi0 {
+	status = "disabled";
+};
+
+&spi2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi2_flash_pins>;
+	status = "okay";
+
+	flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+
+		spi-max-frequency = <25000000>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@00000 {
+				label = "BL2";
+				reg = <0x00000 0x40000>;
+				read-only;
+			};
+
+			partition@40000 {
+				label = "u-boot-env";
+				reg = <0x40000 0x10000>;
+				read-only;
+			};
+
+			factory: partition@50000 {
+				label = "Factory";
+				reg = <0x50000 0x10000>;
+				read-only;
+				
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					eeprom_factory_0: eeprom@0 {
+						reg = <0x0 0x1000>;
+					};
+				};
+			};
+
+			bdinfo: partition@60000 {
+				label = "bdinfo";
+				reg = <0x60000 0x10000>;
+				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					macaddr_bdinfo_de00: macaddr@de00 {
+						compatible = "mac-base";
+						reg = <0xde00 0x6>;
+						#nvmem-cell-cells = <1>;
+					};
+				};
+			};
+
+			partition@70000 {
+				label = "FIP";
+				reg = <0x70000 0x80000>;
+				read-only;
+			};
+
+			partition@f0000 {
+				compatible = "denx,fit";
+				label = "firmware";
+				reg = <0xf0000 0xf10000>;
+			};
+		};
+	};
+};
+
+&pio {
+	spi2_flash_pins: spi2-pins {
+		mux {
+			function = "spi";
+			groups = "spi2", "spi2_wp_hold";
+		};
+
+		conf-pu {
+			pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
+			drive-strength = <8>;
+			bias-pull-up = <103>;
+		};
+
+		conf-pd {
+			pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
+			drive-strength = <8>;
+			bias-pull-down = <103>;
+		};
+	};
+};
+
+&wifi {
+	status = "okay";
+	nvmem-cells = <&eeprom_factory_0>;
+	nvmem-cell-names = "eeprom";
+};
diff --git a/target/linux/mediatek/dts/mt7981b-cudy-wr3000-v1.dts b/target/linux/mediatek/dts/mt7981b-cudy-wr3000-v1.dts
index f4ba629525155a..1ded8b5a687d83 100644
--- a/target/linux/mediatek/dts/mt7981b-cudy-wr3000-v1.dts
+++ b/target/linux/mediatek/dts/mt7981b-cudy-wr3000-v1.dts
@@ -2,6 +2,8 @@
 
 /dts-v1/;
 
+#include <dt-bindings/leds/common.h>
+
 #include "mt7981.dtsi"
 
 / {
@@ -34,7 +36,7 @@
 		wps {
 			label = "wps";
 			linux,code = <KEY_WPS_BUTTON>;
-			gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
+			gpios = <&pio 0 GPIO_ACTIVE_LOW>;
 		};
 	};
 
@@ -42,7 +44,8 @@
 		compatible = "gpio-leds";
 
 		led_status: led@0 {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&pio 10 GPIO_ACTIVE_LOW>;
 		};
 
@@ -52,12 +55,14 @@
 		};
 
 		led@2 {
-			label = "blue:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&pio 5 GPIO_ACTIVE_LOW>;
 		};
 
 		led@3 {
-			label = "blue:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&pio 9 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/mediatek/dts/mt7981b-glinet-gl-mt2500.dts b/target/linux/mediatek/dts/mt7981b-glinet-gl-mt2500.dts
index 068dd0f236e28a..9b7c85e51973ee 100644
--- a/target/linux/mediatek/dts/mt7981b-glinet-gl-mt2500.dts
+++ b/target/linux/mediatek/dts/mt7981b-glinet-gl-mt2500.dts
@@ -103,6 +103,8 @@
 
 	gmac0: mac@0 {
 		compatible = "mediatek,eth-mac";
+		nvmem-cells = <&macaddr_boot1_a 0>;
+		nvmem-cell-names = "mac-address";
 		reg = <0>;
 
 		phy-mode = "2500base-x";
@@ -111,6 +113,8 @@
 
 	gmac1: mac@1 {
 		compatible = "mediatek,eth-mac";
+		nvmem-cells = <&macaddr_boot1_a 1>;
+		nvmem-cell-names = "mac-address";
 		reg = <1>;
 		phy-mode = "gmii";
 		phy-handle = <&int_gbe_phy>;
@@ -148,4 +152,54 @@
 	vmmc-supply = <&reg_3p3v>;
 	cap-mmc-highspeed;
 	non-removable;
+
+	card@0 {
+		compatible = "mmc-card";
+		reg = <0>;
+
+		block {
+			compatible = "block-device";
+
+			partitions {
+				block-partition-u-boot-env {
+					partname = "u-boot-env";
+					nvmem-layout {
+						compatible = "u-boot,env-layout";
+					};
+				};
+			};
+		};
+
+		boot1 {
+			compatible = "block-device";
+
+			nvmem-layout {
+				compatible = "fixed-layout";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				macaddr_boot1_a: macaddr@a {
+					compatible = "mac-base";
+					reg = <0xa 0x6>;
+					#nvmem-cell-cells = <1>;
+				};
+
+				ddns@10 {
+					reg = <0x10 0x10>;
+				};
+
+				sn-bak@20 {
+					reg = <0x20 0x10>;
+				};
+
+				sn@30 {
+					reg = <0x30 0x10>;
+				};
+
+				country-code@88 {
+					reg = <0x88 0x10>;
+				};
+			};
+		};
+	};
 };
diff --git a/target/linux/mediatek/dts/mt7981b-h3c-magic-nx30-pro.dts b/target/linux/mediatek/dts/mt7981b-h3c-magic-nx30-pro.dts
index de702d4a534c6f..030cc250416853 100644
--- a/target/linux/mediatek/dts/mt7981b-h3c-magic-nx30-pro.dts
+++ b/target/linux/mediatek/dts/mt7981b-h3c-magic-nx30-pro.dts
@@ -3,6 +3,7 @@
 /dts-v1/;
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 #include "mt7981.dtsi"
 
@@ -46,12 +47,14 @@
 		compatible = "gpio-leds";
 
 		led_status_green: green {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pio 4 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status_red: red {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&pio 5 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/mediatek/dts/mt7981b-jcg-q30-pro.dts b/target/linux/mediatek/dts/mt7981b-jcg-q30-pro.dts
index bb6b474080ac12..c8b9aeba42fe28 100644
--- a/target/linux/mediatek/dts/mt7981b-jcg-q30-pro.dts
+++ b/target/linux/mediatek/dts/mt7981b-jcg-q30-pro.dts
@@ -3,6 +3,7 @@
 /dts-v1/;
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 #include "mt7981.dtsi"
 
@@ -41,12 +42,14 @@
 		compatible = "gpio-leds";
 
 		led_status_red: red {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&pio 8 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_status_blue: blue {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&pio 13 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/mediatek/dts/mt7981b-qihoo-360t7.dts b/target/linux/mediatek/dts/mt7981b-qihoo-360t7.dts
index cd6f6b30c3efed..3925f80ba35ace 100644
--- a/target/linux/mediatek/dts/mt7981b-qihoo-360t7.dts
+++ b/target/linux/mediatek/dts/mt7981b-qihoo-360t7.dts
@@ -3,6 +3,7 @@
 /dts-v1/;
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 #include "mt7981.dtsi"
 
@@ -46,12 +47,14 @@
 		compatible = "gpio-leds";
 
 		led_status_red: red {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&pio 3 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status_green: green {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pio 7 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/mediatek/dts/mt7981b-zbtlink-zbt-z8102ax.dts b/target/linux/mediatek/dts/mt7981b-zbtlink-zbt-z8102ax.dts
index 112fd777f05b51..de35d150980ef3 100644
--- a/target/linux/mediatek/dts/mt7981b-zbtlink-zbt-z8102ax.dts
+++ b/target/linux/mediatek/dts/mt7981b-zbtlink-zbt-z8102ax.dts
@@ -52,28 +52,24 @@
 		compatible = "gpio-leds";
 
 		led_status_red: red {
-			label = "red:status";
 			gpios = <&pio 9 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_RED>;
 			function = LED_FUNCTION_STATUS;
 		};
 
 		led_status_green: green {
-			label = "green:status";
 			gpios = <&pio 10 GPIO_ACTIVE_LOW>;
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_STATUS;
 		};
 
 		blue {
-			label = "blue:status";
 			gpios = <&pio 11 GPIO_ACTIVE_LOW>;
 			color = <LED_COLOR_ID_BLUE>;
 			function = LED_FUNCTION_STATUS;
 		};
 
 		4g {
-			label = "blue:4g";
 			gpios = <&pio 8 GPIO_ACTIVE_LOW>;
 			color = <LED_COLOR_ID_BLUE>;
 			function = LED_FUNCTION_USB;
@@ -81,7 +77,6 @@
 		};
 
 		4g2 {
-			label = "blue:4g2";
 			gpios = <&pio 14 GPIO_ACTIVE_LOW>;
 			color = <LED_COLOR_ID_BLUE>;
 			function = LED_FUNCTION_USB;
diff --git a/target/linux/mediatek/dts/mt7986a-asus-rt-ax59u.dts b/target/linux/mediatek/dts/mt7986a-asus-rt-ax59u.dts
index e2acb637714d66..0034ad8284b1bd 100644
--- a/target/linux/mediatek/dts/mt7986a-asus-rt-ax59u.dts
+++ b/target/linux/mediatek/dts/mt7986a-asus-rt-ax59u.dts
@@ -14,6 +14,7 @@
 
 	aliases {
 		serial0 = &uart0;
+		label-mac-device = &gmac0;
 		led-boot = &led_status_green;
 		led-failsafe = &led_status_red;
 		led-running = &led_status_green;
@@ -22,7 +23,7 @@
 
 	chosen {
 		stdout-path = "serial0:115200n8";
-		bootargs-override = "ubi.mtd=UBI_DEV";
+		bootargs-override = "";
 	};
 
 	memory {
@@ -89,6 +90,8 @@
 		/* LAN */
 		compatible = "mediatek,eth-mac";
 		reg = <0>;
+		nvmem-cells = <&macaddr_factory_4>;
+		nvmem-cell-names = "mac-address";
 		phy-mode = "2500base-x";
 
 		fixed-link {
@@ -206,44 +209,87 @@
 	pinctrl-0 = <&spi_flash_pins>;
 	status = "okay";
 
-	spi_nand: spi_nand@0 {
+	spi_nand: flash@0 {
 		compatible = "spi-nand";
+		reg = <0>;
 		#address-cells = <1>;
 		#size-cells = <1>;
-		reg = <0>;
 
 		spi-max-frequency = <20000000>;
 		spi-tx-bus-width = <4>;
 		spi-rx-bus-width = <4>;
 
-		partitions: partitions {
+		/*
+		 * ASUS bootloader tries to replace the partitions defined in
+		 * Device Tree and by that also deletes all additional properties
+		 * needed for UBI and NVMEM-on-UBI.
+		 * Prevent this from happening by tricking the loader to delete and
+		 * replace a bait node instead.
+		 */
+		partitions: dummy {
+			compatible = "u-boot-dummy-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				reg = <0x0 0x0>;
+				label = "remove_me";
+			};
+		};
+
+		partitions {
 			compatible = "fixed-partitions";
 			#address-cells = <1>;
 			#size-cells = <1>;
 
 			partition@0 {
-				label = "u-boot";
 				reg = <0x0 0x400000>;
+				label = "u-boot";
 				read-only;
 			};
 
 			partition@400000 {
+				compatible = "linux,ubi";
+				reg = <0x400000 0xfc00000>;
 				label = "UBI_DEV";
-				reg = <0x400000 0x7c00000>;
+
+				volumes {
+					ubi_factory: ubi-volume-factory {
+						volname = "Factory";
+					};
+				};
 			};
 		};
 	};
 };
 
+&ubi_factory {
+	nvmem-layout {
+		compatible = "fixed-layout";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		eeprom_factory_0: eeprom@0 {
+			reg = <0x0 0x1000>;
+		};
+
+		macaddr_factory_4: macaddr@4 {
+			reg = <0x4 0x6>;
+		};
+	};
+};
+
 &watchdog {
 	status = "okay";
 };
 
 &wifi {
-	status = "okay";
-	pinctrl-names = "default", "dbdc";
+	nvmem-cells = <&eeprom_factory_0>;
+	nvmem-cell-names = "eeprom";
 	pinctrl-0 = <&wf_2g_5g_pins>;
 	pinctrl-1 = <&wf_dbdc_pins>;
+	pinctrl-names = "default", "dbdc";
+	status = "okay";
 };
 
 &trng {
diff --git a/target/linux/mediatek/dts/mt7986a-asus-tuf-ax4200.dts b/target/linux/mediatek/dts/mt7986a-asus-tuf-ax4200.dts
index 2af18958bc517f..22530df9bb9d05 100644
--- a/target/linux/mediatek/dts/mt7986a-asus-tuf-ax4200.dts
+++ b/target/linux/mediatek/dts/mt7986a-asus-tuf-ax4200.dts
@@ -13,6 +13,7 @@
 
 	aliases {
 		serial0 = &uart0;
+		label-mac-device = &gmac0;
 		led-boot = &led_system;
 		led-failsafe = &led_system;
 		led-running = &led_system;
@@ -21,7 +22,7 @@
 
 	chosen {
 		stdout-path = "serial0:115200n8";
-		bootargs-override = "ubi.mtd=UBI_DEV";
+		bootargs-override = "";
 	};
 
 	memory {
@@ -65,7 +66,8 @@
 		};
 
 		wan-red {
-			label = "red:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&pio 12 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -100,6 +102,8 @@
 		/* LAN */
 		compatible = "mediatek,eth-mac";
 		reg = <0>;
+		nvmem-cells = <&macaddr_factory_4>;
+		nvmem-cell-names = "mac-address";
 		phy-mode = "2500base-x";
 
 		fixed-link {
@@ -214,25 +218,66 @@
 		spi-tx-bus-width = <4>;
 		spi-rx-bus-width = <4>;
 
-		partitions: partitions {
+		/*
+		 * ASUS bootloader tries to replace the partitions defined in
+		 * Device Tree and by that also deletes all additional properties
+		 * needed for UBI and NVMEM-on-UBI.
+		 * Prevent this from happening by tricking the loader to delete and
+		 * replace a bait node instead.
+		 */
+		partitions: dummy {
+			compatible = "u-boot-dummy-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				reg = <0x0 0x0>;
+				label = "remove_me";
+			};
+		};
+
+		partitions {
 			compatible = "fixed-partitions";
 			#address-cells = <1>;
 			#size-cells = <1>;
 
 			partition@0 {
-				label = "bootloader";
 				reg = <0x0 0x400000>;
+				label = "bootloader";
 				read-only;
 			};
 
 			partition@400000 {
-				label = "UBI_DEV";
+				compatible = "linux,ubi";
 				reg = <0x400000 0xfc00000>;
+				label = "UBI_DEV";
+
+				volumes {
+					ubi_factory: ubi-volume-factory {
+						volname = "Factory";
+					};
+				};
 			};
 		};
 	};
 };
 
+&ubi_factory {
+	nvmem-layout {
+		compatible = "fixed-layout";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		eeprom_factory_0: eeprom@0 {
+			reg = <0x0 0x1000>;
+		};
+
+		macaddr_factory_4: macaddr@4 {
+			reg = <0x4 0x6>;
+		};
+	};
+};
+
 &switch {
 	ports {
 		#address-cells = <1>;
@@ -339,10 +384,12 @@
 };
 
 &wifi {
-	status = "okay";
-	pinctrl-names = "default", "dbdc";
+	nvmem-cells = <&eeprom_factory_0>;
+	nvmem-cell-names = "eeprom";
 	pinctrl-0 = <&wf_2g_5g_pins>;
 	pinctrl-1 = <&wf_dbdc_pins>;
+	pinctrl-names = "default", "dbdc";
+	status = "okay";
 };
 
 &trng {
diff --git a/target/linux/mediatek/dts/mt7986a-asus-tuf-ax6000.dts b/target/linux/mediatek/dts/mt7986a-asus-tuf-ax6000.dts
index b05dec93b49a9f..bde2525cd7557e 100644
--- a/target/linux/mediatek/dts/mt7986a-asus-tuf-ax6000.dts
+++ b/target/linux/mediatek/dts/mt7986a-asus-tuf-ax6000.dts
@@ -13,6 +13,7 @@
 
 	aliases {
 		serial0 = &uart0;
+		label-mac-device = &gmac0;
 		led-boot = &led_system;
 		led-failsafe = &led_system;
 		led-running = &led_system;
@@ -21,7 +22,7 @@
 
 	chosen {
 		stdout-path = "serial0:115200n8";
-		bootargs-override = "ubi.mtd=UBI_DEV";
+		bootargs-override = "";
 	};
 
 	memory {
@@ -48,7 +49,8 @@
 		compatible = "gpio-leds";
 
 		wlan {
-			label = "white:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "phy1tpt";
 		};
@@ -59,7 +61,8 @@
 		};
 
 		wan-red {
-			label = "red:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&pio 12 GPIO_ACTIVE_LOW>;
 		};
 
@@ -99,6 +102,8 @@
 		/* LAN */
 		compatible = "mediatek,eth-mac";
 		reg = <0>;
+		nvmem-cells = <&macaddr_factory_4>;
+		nvmem-cell-names = "mac-address";
 		phy-mode = "2500base-x";
 
 		fixed-link {
@@ -217,33 +222,74 @@
 
 	spi_nand_flash: flash@0 {
 		compatible = "spi-nand";
+		reg = <0>;
 		#address-cells = <1>;
 		#size-cells = <1>;
-		reg = <0>;
 
 		spi-max-frequency = <20000000>;
 		spi-tx-bus-width = <4>;
 		spi-rx-bus-width = <4>;
 
-		partitions: partitions {
+		/*
+		 * ASUS bootloader tries to replace the partitions defined in
+		 * Device Tree and by that also deletes all additional properties
+		 * needed for UBI and NVMEM-on-UBI.
+		 * Prevent this from happening by tricking the loader to delete and
+		 * replace a bait node instead.
+		 */
+		partitions: dummy {
+			compatible = "u-boot-dummy-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				reg = <0x0 0x0>;
+				label = "remove_me";
+			};
+		};
+
+		partitions {
 			compatible = "fixed-partitions";
 			#address-cells = <1>;
 			#size-cells = <1>;
 
 			partition@0 {
-				label = "bootloader";
 				reg = <0x0 0x400000>;
+				label = "bootloader";
 				read-only;
 			};
 
 			partition@400000 {
-				label = "UBI_DEV";
+				compatible = "linux,ubi";
 				reg = <0x400000 0xfc00000>;
+				label = "UBI_DEV";
+
+				volumes {
+					ubi_factory: ubi-volume-factory {
+						volname = "Factory";
+					};
+				};
 			};
 		};
 	};
 };
 
+&ubi_factory {
+	nvmem-layout {
+		compatible = "fixed-layout";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		eeprom_factory_0: eeprom@0 {
+			reg = <0x0 0x1000>;
+		};
+
+		macaddr_factory_4: macaddr@4 {
+			reg = <0x4 0x6>;
+		};
+	};
+};
+
 &switch {
 	ports {
 		#address-cells = <1>;
@@ -358,10 +404,12 @@
 };
 
 &wifi {
-	status = "okay";
+	nvmem-cells = <&eeprom_factory_0>;
+	nvmem-cell-names = "eeprom";
 	pinctrl-names = "default", "dbdc";
 	pinctrl-0 = <&wf_2g_5g_pins>;
 	pinctrl-1 = <&wf_dbdc_pins>;
+	status = "okay";
 };
 
 &trng {
diff --git a/target/linux/mediatek/dts/mt7986a-bananapi-bpi-r3-mini.dts b/target/linux/mediatek/dts/mt7986a-bananapi-bpi-r3-mini.dts
new file mode 100644
index 00000000000000..09a557c0cb8122
--- /dev/null
+++ b/target/linux/mediatek/dts/mt7986a-bananapi-bpi-r3-mini.dts
@@ -0,0 +1,715 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (C) 2023 Tianling Shen <cnsztl@immortalwrt.org>
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+#include "mt7986a.dtsi"
+
+/ {
+	model = "Bananapi BPi-R3 Mini";
+	chassis-type = "embedded";
+	compatible = "bananapi,bpi-r3-mini", "mediatek,mt7986a";
+
+	aliases {
+		ethernet0 = &gmac0;
+		ethernet1 = &gmac1;
+		serial0 = &uart0;
+
+		led-boot = &status_led;
+		led-failsafe = &status_led;
+		led-running = &status_led;
+		led-upgrade = &status_led;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+		rootdisk-emmc = <&emmc_rootdisk>;
+		rootdisk-spim-nand = <&nand_rootdisk>;
+	};
+
+	memory {
+		reg = <0 0x40000000 0 0x80000000>;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		button-reset {
+			label = "reset";
+			linux,code = <KEY_RESTART>;
+			gpios = <&pio 7 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		status_led: led-0 {
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&pio 19 GPIO_ACTIVE_HIGH>;
+		};
+
+		led-1 {
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_BLUE>;
+			function-enumerator = <1>;
+			gpios = <&pio 1 GPIO_ACTIVE_HIGH>;
+		};
+
+		led-2 {
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_BLUE>;
+			function-enumerator = <2>;
+			gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	fan: pwm-fan {
+		compatible = "pwm-fan";
+		#cooling-cells = <2>;
+		cooling-levels = <255 128 80 0>;
+		pwms = <&pwm 0 10000 0>;
+		status = "okay";
+	};
+
+	reg_1p8v: regulator-1p8v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-1.8V";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	reg_3p3v: regulator-3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	reg_5v: regulator-5v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-5V";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	usb_vbus: regulator-usb-vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "usb_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpios = <&pio 20 GPIO_ACTIVE_LOW>;
+		regulator-boot-on;
+	};
+};
+
+&auxadc {
+	status = "okay";
+};
+
+&cpu_thermal {
+	cooling-maps {
+		cpu-active-low {
+			cooling-device = <&fan 1 1>;
+			trip = <&cpu_trip_active_low>;
+		};
+
+		cpu-active-med {
+			cooling-device = <&fan 2 2>;
+			trip = <&cpu_trip_active_med>;
+		};
+
+		cpu-active-high {
+			cooling-device = <&fan 3 3>;
+			trip = <&cpu_trip_active_high>;
+		};
+	};
+};
+
+&crypto {
+	status = "okay";
+};
+
+&eth {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&eth_pins>;
+
+	gmac0: mac@0 {
+		compatible = "mediatek,eth-mac";
+		reg = <0>;
+		phy-handle = <&phy14>;
+		phy-mode = "2500base-x";
+	};
+
+	gmac1: mac@1 {
+		compatible = "mediatek,eth-mac";
+		reg = <1>;
+		phy-handle = <&phy15>;
+		phy-mode = "2500base-x";
+	};
+
+	mdio: mdio-bus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		phy14: phy@e {
+			compatible = "ethernet-phy-id03a2.a411";
+			reg = <14>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&en8811_pwr_a>;
+
+			airoha,pnswap-rx;
+
+			interrupt-parent = <&pio>;
+			interrupts = <48 IRQ_TYPE_EDGE_FALLING>;
+			reset-gpios = <&pio 49 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <10000>;
+			reset-deassert-us = <20000>;
+
+			phy-mode = "2500base-x";
+			full-duplex;
+			pause;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					function = LED_FUNCTION_LAN;
+					color = <LED_COLOR_ID_YELLOW>;
+				};
+
+				led@1 {
+					reg = <1>;
+					function = LED_FUNCTION_LAN;
+					color = <LED_COLOR_ID_GREEN>;
+				};
+			};
+		};
+
+		phy15: phy@f {
+			compatible = "ethernet-phy-id03a2.a411";
+			reg = <15>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&en8811_pwr_b>;
+
+			airoha,pnswap-rx;
+
+			interrupt-parent = <&pio>;
+			interrupts = <46 IRQ_TYPE_EDGE_FALLING>;
+			reset-gpios = <&pio 47 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <10000>;
+			reset-deassert-us = <20000>;
+
+			phy-mode = "2500base-x";
+			full-duplex;
+			pause;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					function = LED_FUNCTION_WAN;
+					color = <LED_COLOR_ID_YELLOW>;
+				};
+
+				led@1 {
+					reg = <1>;
+					function = LED_FUNCTION_WAN;
+					color = <LED_COLOR_ID_GREEN>;
+				};
+			};
+		};
+	};
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c_pins>;
+	status = "okay";
+
+	eeprom@50 {
+		compatible = "atmel,24c02";
+		reg = <0x50>;
+		pagesize = <8>;
+		size = <256>;
+	};
+};
+
+&mmc0 {
+	pinctrl-names = "default", "state_uhs";
+	pinctrl-0 = <&mmc0_pins_default>;
+	pinctrl-1 = <&mmc0_pins_uhs>;
+	bus-width = <8>;
+	max-frequency = <200000000>;
+	cap-mmc-highspeed;
+	mmc-hs200-1_8v;
+	mmc-hs400-1_8v;
+	hs400-ds-delay = <0x14014>;
+	vmmc-supply = <&reg_3p3v>;
+	vqmmc-supply = <&reg_1p8v>;
+	non-removable;
+	no-sd;
+	no-sdio;
+	status = "okay";
+
+	card@0 {
+		compatible = "mmc-card";
+		reg = <0>;
+
+		block {
+			compatible = "block-device";
+			partitions {
+				emmc_rootdisk: block-partition-production {
+					partname = "production";
+				};
+			};
+		};
+	};
+};
+
+&pcie {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie_pins>;
+	status = "okay";
+};
+
+&pcie_phy {
+	status = "okay";
+};
+
+&pio {
+	en8811_pwr_a: en8811-pwr-a {
+		pins = "GPIO_11";
+		drive-strength = <8>;
+		mediatek,pull-down-adv = <1>;
+		output-low;
+	};
+
+	en8811_pwr_b: en8811-pwr-b {
+		pins = "GPIO_12";
+		drive-strength = <8>;
+		mediatek,pull-down-adv = <1>;
+		output-low;
+	};
+
+	eth_pins: eth-pins {
+		mux {
+			function = "eth";
+			groups = "mdc_mdio";
+		};
+	};
+
+	i2c_pins: i2c-pins {
+		mux {
+			function = "i2c";
+			groups = "i2c";
+		};
+	};
+
+	mmc0_pins_default: mmc0-pins-default {
+		mux {
+			function = "emmc";
+			groups = "emmc_51";
+		};
+		conf-cmd-dat {
+			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
+			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
+			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
+			input-enable;
+			drive-strength = <4>;
+			mediatek,pull-up-adv = <1>;
+		};
+		conf-clk {
+			pins = "EMMC_CK";
+			drive-strength = <6>;
+			mediatek,pull-down-adv = <2>;
+		};
+		conf-ds {
+			pins = "EMMC_DSL";
+			mediatek,pull-down-adv = <2>;
+		};
+		conf-rst {
+			pins = "EMMC_RSTB";
+			drive-strength = <4>;
+			mediatek,pull-up-adv = <1>;
+		};
+	};
+
+	mmc0_pins_uhs: mmc0-uhs-pins {
+		mux {
+			function = "emmc";
+			groups = "emmc_51";
+		};
+		conf-cmd-dat {
+			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
+			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
+			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
+			input-enable;
+			drive-strength = <4>;
+			mediatek,pull-up-adv = <1>;
+		};
+		conf-clk {
+			pins = "EMMC_CK";
+			drive-strength = <6>;
+			mediatek,pull-down-adv = <2>;
+		};
+		conf-ds {
+			pins = "EMMC_DSL";
+			mediatek,pull-down-adv = <2>;
+		};
+		conf-rst {
+			pins = "EMMC_RSTB";
+			drive-strength = <4>;
+			mediatek,pull-up-adv = <1>;
+		};
+	};
+
+	pcie_pins: pcie-pins {
+		mux {
+			function = "pcie";
+			groups = "pcie_clk", "pcie_wake", "pcie_pereset";
+		};
+	};
+
+	pwm_pins: pwm-pins {
+		mux {
+			function = "pwm";
+			groups = "pwm0", "pwm1_0";
+		};
+	};
+
+	spi_flash_pins: spi-flash-pins {
+		mux {
+			function = "spi";
+			groups = "spi0", "spi0_wp_hold";
+		};
+		conf-pu {
+			pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
+			drive-strength = <8>;
+			mediatek,pull-up-adv = <0>;
+		};
+		conf-pd {
+			pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
+			drive-strength = <8>;
+			mediatek,pull-down-adv = <0>;
+		};
+	};
+
+	spic_pins: spic-pins {
+		mux {
+			function = "spi";
+			groups = "spi1_2";
+		};
+	};
+
+	uart1_pins: uart1-pins {
+		mux {
+			function = "uart";
+			groups = "uart1";
+		};
+	};
+
+	usb_ngff_pins: usb-ngff-pins {
+		ngff-gnss-off {
+			pins = "GPIO_6";
+			drive-strength = <8>;
+			mediatek,pull-up-adv = <1>;
+		};
+		ngff-pe-rst {
+			pins = "GPIO_7";
+			drive-strength = <8>;
+			mediatek,pull-up-adv = <1>;
+		};
+		ngff-wwan-off {
+			pins = "GPIO_8";
+			drive-strength = <8>;
+			mediatek,pull-up-adv = <1>;
+		};
+		ngff-pwr-off {
+			pins = "GPIO_9";
+			drive-strength = <8>;
+			mediatek,pull-up-adv = <1>;
+		};
+		ngff-rst {
+			pins = "GPIO_10";
+			drive-strength = <8>;
+			mediatek,pull-up-adv = <1>;
+		};
+		ngff-coex {
+			pins = "SPI1_CS";
+			drive-strength = <8>;
+			mediatek,pull-up-adv = <1>;
+		};
+	};
+
+	wf_2g_5g_pins: wf-2g-5g-pins {
+		mux {
+			function = "wifi";
+			groups = "wf_2g", "wf_5g";
+		};
+		conf {
+			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
+			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
+			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
+			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
+			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
+			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
+			       "WF1_TOP_CLK", "WF1_TOP_DATA";
+			drive-strength = <4>;
+		};
+	};
+
+	wf_dbdc_pins: wf-dbdc-pins {
+		mux {
+			function = "wifi";
+			groups = "wf_dbdc";
+		};
+		conf {
+			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
+			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
+			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
+			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
+			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
+			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
+			       "WF1_TOP_CLK", "WF1_TOP_DATA";
+			drive-strength = <4>;
+		};
+	};
+};
+
+&pwm {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm_pins>;
+	status = "okay";
+};
+
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi_flash_pins>;
+	status = "okay";
+
+	flash@0 {
+		compatible = "spi-nand";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+
+		spi-max-frequency = <20000000>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "bl2";
+				reg = <0x0 0x200000>;
+				read-only;
+			};
+
+			partition@200000 {
+				label = "ubi";
+				reg = <0x200000 0x7e00000>;
+				compatible = "linux,ubi";
+
+				volumes {
+					nand_rootdisk: ubi-volume-fit {
+						volname = "fit";
+					};
+				};
+			};
+		};
+	};
+};
+
+&spi1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spic_pins>;
+	/* conflicts with M.2 pin */
+	status = "disabled";
+};
+
+&ssusb {
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb_ngff_pins>;
+	vusb33-supply = <&reg_3p3v>;
+	vbus-supply = <&usb_vbus>;
+	status = "okay";
+};
+
+&trng {
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1_pins>;
+	status = "okay";
+};
+
+&usb_phy {
+	status = "okay";
+};
+
+&watchdog {
+	status = "okay";
+};
+
+&wifi {
+	pinctrl-names = "default", "dbdc";
+	pinctrl-0 = <&wf_2g_5g_pins>;
+	pinctrl-1 = <&wf_dbdc_pins>;
+	status = "okay";
+
+	mediatek,eeprom-data = <0x86790200 0x000c4326 0x60000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x125b486c 0x00280000 0x05d00000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x0c000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000012 0x12120000 0x00000000 0x00000000 0x00002222 0x22223333 0x33333333
+				0x33333333 0x33333333 0x33333333 0x33333333 0x33333333 0x33330000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00292929 0x29282828 0x28282828 0x28282828 0x28282828 0x28282828 0x28000000 0x00000000
+				0x00000000 0x00242424 0x24222222 0x22242424 0x24222222 0x22242424 0x24222222 0x22242424
+				0x24222222 0x22000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x007f7f7f 0xd1d1dddd 0xe9e9f5f5 0x01010909 0x1515d1d1 0xdddde9e9 0xf5f5fdfd
+				0x09091515 0xd1d1dddd 0xe9e9f5f5 0xfdfd0909 0x1515d1d1 0xdddde9e9 0xf5f5fdfd 0x09091515
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x0efefc00 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x021e021e 0x02000200 0x02370237 0x02370237
+				0x02370237 0x02370237 0x02370237 0x02370237 0x02370237 0x02370237 0x02370237 0x02370237
+				0x02370237 0x02370237 0x02370237 0x02370237 0x002200c6 0xc6c4c4c3 0x0000c1c2 0xc1838383
+				0x838686c1 0xc1838383 0x838686c2 0xc1c18181 0x82838585 0x8686c1c1 0x81818283 0x85858686
+				0xc1c18181 0x82838585 0x8686c1c1 0x81818283 0x85858686 0xc1c18181 0x82838585 0x8686c5c5
+				0xc3c100c2 0xc3c2c200 0x81828383 0xc2c2c200 0x81828383 0xc3c1c1c1 0x81828384 0x84c2c2c2
+				0xc2008182 0x83838585 0xc2c2c200 0x81828383 0x8585c1c1 0xc1818283 0x84848686 0x82828484
+				0x85868787 0x8989c2c2 0xc2008182 0x83838585 0xc2c2c200 0x81828383 0x8585c2c2 0xc2008182
+				0x83838585 0xc4c4c2c1 0x00c3c3c3 0xc1008183 0x838686c3 0xc3c3c100 0x81838386 0x86c2c2c2
+				0x00818284 0x84868682 0x82828485 0x8688888b 0x8bc3c3c3 0xc1008183 0x838686c3 0xc3c3c100
+				0x81838386 0x86c3c3c3 0xc1008183 0x83868600 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00bd0000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00c50000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00495256 0x55555555 0x004a5251 0x51515151 0x004a5355 0x56565656 0x0049504e 0x51515151
+				0x00495150 0x54545454 0x00495051 0x51515151 0x00495251 0x50505050 0x00495251 0x51515151
+				0x00495251 0x54545454 0x00495150 0x54545454 0x00495352 0x51515151 0x00495353 0x52525252
+				0x00495150 0x50505050 0x00495152 0x54545454 0x00495251 0x53535353 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0xd1d1dddd 0xe9e9f5f5 0xfdfd1414 0x1d1d0000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x85840000 0xc3c4c382 0x828281c1 0xc4c5c400 0x0000c1c3 0xc4c4c481 0x8181c1c2 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0xc0bbc0bb 0xc0bbc0bb 0x40c5c0c4 0xc0c3c0c3 0x40c340c5 0x40c4c0c3 0x40c3c0c2 0xc0c5c0c4
+				0x40c440c4 0xc0c3c0c5 0xc0c440c4 0x40c4c0c3 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x40c640c6 0x40c640c6 0x40c640c6 0x40c640c6 0x40c640c6 0x40c640c6
+				0x40c640c6 0x40c640c6 0x40c640c6 0x40c640c6 0x40c640c6 0x40c640c6 0x40c640c6 0x40c640c6
+				0x40c640c6 0x40c640c6 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>;
+};
diff --git a/target/linux/mediatek/dts/mt7986a-glinet-gl-mt6000.dts b/target/linux/mediatek/dts/mt7986a-glinet-gl-mt6000.dts
index 26996e7b4a5ab2..fd0e1a69157ed0 100644
--- a/target/linux/mediatek/dts/mt7986a-glinet-gl-mt6000.dts
+++ b/target/linux/mediatek/dts/mt7986a-glinet-gl-mt6000.dts
@@ -13,6 +13,7 @@
 
 	aliases {
 		serial0 = &uart0;
+		label-mac-device = &gmac1;
 		led-boot = &led_blue;
 		led-failsafe = &led_blue;
 		led-running = &led_white;
@@ -84,6 +85,8 @@
 		compatible = "mediatek,eth-mac";
 		reg = <0>;
 		phy-mode = "2500base-x";
+		nvmem-cells = <&macaddr_factory_a 2>;
+		nvmem-cell-names = "mac-address";
 
 		fixed-link {
 			speed = <2500>;
@@ -95,6 +98,8 @@
 	gmac1: mac@1 {
 		compatible = "mediatek,eth-mac";
 		reg = <1>;
+		nvmem-cells = <&macaddr_factory_a 0>;
+		nvmem-cell-names = "mac-address";
 		phy-mode = "2500base-x";
 		phy-handle = <&phy1>;
 	};
@@ -285,6 +290,8 @@
 };
 
 &wifi {
+	nvmem-cells = <&eeprom_factory_0>;
+	nvmem-cell-names = "eeprom";
 	pinctrl-names = "default";
 	pinctrl-0 = <&wf_2g_5g_pins>;
 	status = "okay";
@@ -306,4 +313,42 @@
 	no-sd;
 	no-sdio;
 	status = "okay";
+
+	card@0 {
+		compatible = "mmc-card";
+		reg = <0>;
+
+		block {
+			compatible = "block-device";
+			partitions {
+				block-partition-env {
+					partname = "u-boot-env";
+
+					nvmem-layout {
+						compatible = "u-boot,env-layout";
+					};
+				};
+
+				block-partition-factory {
+					partname = "factory";
+
+					nvmem-layout {
+						compatible = "fixed-layout";
+						#address-cells = <1>;
+						#size-cells = <1>;
+
+						eeprom_factory_0: eeprom@0 {
+							reg = <0x0 0x1000>;
+						};
+
+						macaddr_factory_a: macaddr@a {
+							compatible = "mac-base";
+							reg = <0xa 0x6>;
+							#nvmem-cell-cells = <1>;
+						};
+					};
+				};
+			};
+		};
+	};
 };
diff --git a/target/linux/mediatek/dts/mt7986a-tplink-tl-xdr-common.dtsi b/target/linux/mediatek/dts/mt7986a-tplink-tl-xdr-common.dtsi
index da08bdc723b1b2..c851853286a01d 100644
--- a/target/linux/mediatek/dts/mt7986a-tplink-tl-xdr-common.dtsi
+++ b/target/linux/mediatek/dts/mt7986a-tplink-tl-xdr-common.dtsi
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 #include "mt7986a.dtsi"
 
@@ -67,12 +68,14 @@
 		compatible = "gpio-leds";
 
 		led_status_red: status_red {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_status_green: status_green {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pio 8 GPIO_ACTIVE_HIGH>;
 		};
 
diff --git a/target/linux/mediatek/dts/mt7986a-xiaomi-redmi-router-ax6000.dtsi b/target/linux/mediatek/dts/mt7986a-xiaomi-redmi-router-ax6000.dtsi
index ffa5acb5d3694e..30571965bc9e51 100644
--- a/target/linux/mediatek/dts/mt7986a-xiaomi-redmi-router-ax6000.dtsi
+++ b/target/linux/mediatek/dts/mt7986a-xiaomi-redmi-router-ax6000.dtsi
@@ -202,13 +202,11 @@
 
 		led_status_rgb: led@0 {
 			reg = <0>;
-			label = "rgb:status";
 			color-index = <LED_COLOR_ID_RED LED_COLOR_ID_GREEN LED_COLOR_ID_BLUE>;
 		};
 
 		led_network_rgb: led@1 {
 			reg = <1>;
-			label = "rgb:network";
 			color-index = <LED_COLOR_ID_RED LED_COLOR_ID_GREEN LED_COLOR_ID_BLUE>;
 		};
 	};
diff --git a/target/linux/mediatek/dts/mt7986a-zyxel-ex5601-t0-common.dtsi b/target/linux/mediatek/dts/mt7986a-zyxel-ex5601-t0-common.dtsi
index 04e86a737d1d01..335ee93989f38f 100644
--- a/target/linux/mediatek/dts/mt7986a-zyxel-ex5601-t0-common.dtsi
+++ b/target/linux/mediatek/dts/mt7986a-zyxel-ex5601-t0-common.dtsi
@@ -7,6 +7,7 @@
 #include "mt7986a.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -140,7 +141,8 @@
 		};
 
 		led_green_lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
 			default-state = "off";
 		};
diff --git a/target/linux/mediatek/dts/mt7986a-zyxel-ex5700-telenor.dts b/target/linux/mediatek/dts/mt7986a-zyxel-ex5700-telenor.dts
index f5bb73c97d7ee7..29961e528cc741 100644
--- a/target/linux/mediatek/dts/mt7986a-zyxel-ex5700-telenor.dts
+++ b/target/linux/mediatek/dts/mt7986a-zyxel-ex5700-telenor.dts
@@ -2,6 +2,7 @@
 
 /dts-v1/;
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/gpio/gpio.h>
 
 #include "mt7986a.dtsi"
@@ -88,25 +89,29 @@
 		};
 
 		white2 {
-			label = "white:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&pio 16 GPIO_ACTIVE_HIGH>;
 			default-state = "off";
 		};
 
 		red2 {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&pio 17 GPIO_ACTIVE_HIGH>;
 			default-state = "off";
 		};
 
 		led_status_green: green2 {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pio 31 GPIO_ACTIVE_HIGH>;
 			default-state = "off";
 		};
 
 		led_status_amber: amber2 {
-			label = "amber:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&pio 18 GPIO_ACTIVE_HIGH>;
 			default-state = "off";
 		};
diff --git a/target/linux/mediatek/dts/mt7986b-netgear-wax220.dts b/target/linux/mediatek/dts/mt7986b-netgear-wax220.dts
index 19419f593fb273..6e51d884702358 100644
--- a/target/linux/mediatek/dts/mt7986b-netgear-wax220.dts
+++ b/target/linux/mediatek/dts/mt7986b-netgear-wax220.dts
@@ -43,7 +43,8 @@
 
 		led_power_amber: power_amber {
 			gpios = <&pio 15 GPIO_ACTIVE_LOW>;
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 		};
 
 		wlan2g_green {
@@ -53,12 +54,14 @@
 
 		led_power_blue: power_blue {
 			gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 		};
 
 		led_power_green: power_green {
 			gpios = <&pio 10 GPIO_ACTIVE_LOW>;
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 		};
 
 		wlan2g_blue {
@@ -68,12 +71,14 @@
 
 		lan_green {
 			gpios = <&pio 22 GPIO_ACTIVE_HIGH>;
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 		};
 
 		lan_amber {
 			gpios = <&pio 13 GPIO_ACTIVE_LOW>;
-			label = "amber:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_AMBER>;
 		};
 
 		wlan5g_blue {
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-eth1.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-eth1.dtso
deleted file mode 100644
index 4d0e5c04067b39..00000000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-eth1.dtso
+++ /dev/null
@@ -1,32 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
-
-	fragment@0 {
-		target = <&gmac1>;
-		__overlay__ {
-			phy-mode = "2500base-x";
-			phy-handle = <&phy5>;
-		};
-	};
-
-	fragment@1 {
-		target = <&mdio_bus>;
-		__overlay__ {
-			reset-gpios = <&pio 14 GPIO_ACTIVE_LOW>;
-			reset-delay-us = <600>;
-			reset-post-delay-us = <20000>;
-
-			phy5: ethernet-phy@5 {
-				reg = <5>;
-				compatible = "ethernet-phy-ieee802.3-c45";
-				phy-mode = "2500base-x";
-			};
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-swp5.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-swp5.dtso
deleted file mode 100644
index 710e6c0bcfbee2..00000000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-swp5.dtso
+++ /dev/null
@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
-
-	fragment@0 {
-		target = <&sw_p5>;
-		__overlay__ {
-			phy-mode = "2500base-x";
-			phy-handle = <&phy5>;
-			status = "okay";
-		};
-	};
-
-	fragment@1 {
-		target = <&mdio_bus>;
-		__overlay__ {
-			reset-gpios = <&pio 14 GPIO_ACTIVE_LOW>;
-			reset-delay-us = <600>;
-			reset-post-delay-us = <20000>;
-
-			phy5: ethernet-phy@5 {
-				reg = <5>;
-				compatible = "ethernet-phy-ieee802.3-c45";
-				phy-mode = "2500base-x";
-			};
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981-rfb-spim-nand.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981-rfb-spim-nand.dtso
deleted file mode 100644
index 5b51dfd671c228..00000000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981-rfb-spim-nand.dtso
+++ /dev/null
@@ -1,66 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-/dts-v1/;
-/plugin/;
-
-/ {
-	compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
-
-	fragment@0 {
-		target = <&spi0>;
-		__overlay__ {
-			status = "okay";
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			spi_nand: spi_nand@0 {
-				#address-cells = <1>;
-				#size-cells = <1>;
-				compatible = "spi-nand";
-				reg = <1>;
-				spi-max-frequency = <10000000>;
-				spi-tx-bus-width = <4>;
-				spi-rx-bus-width = <4>;
-
-				partitions {
-					compatible = "fixed-partitions";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					partition@0 {
-						label = "BL2";
-						reg = <0x00000 0x0100000>;
-						read-only;
-					};
-
-					partition@100000 {
-						label = "u-boot-env";
-						reg = <0x0100000 0x0080000>;
-					};
-
-					factory: partition@180000 {
-						label = "Factory";
-						reg = <0x180000 0x0200000>;
-					};
-
-					partition@380000 {
-						label = "FIP";
-						reg = <0x380000 0x0200000>;
-					};
-
-					partition@580000 {
-						label = "ubi";
-						reg = <0x580000 0x4000000>;
-					};
-				};
-			};
-		};
-	};
-
-	fragment@1 {
-		target = <&wifi>;
-		__overlay__ {
-			mediatek,mtd-eeprom = <&factory 0x0>;
-			status = "okay";
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981-rfb.dts b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981-rfb.dts
deleted file mode 100644
index b2bb6929562ebd..00000000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981-rfb.dts
+++ /dev/null
@@ -1,188 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-#include "mt7981.dtsi"
-
-/ {
-	model = "MediaTek MT7981 RFB";
-	compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
-
-	aliases {
-		serial0 = &uart0;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	memory {
-		reg = <0 0x40000000 0 0x20000000>;
-	};
-
-	reg_3p3v: regulator-3p3v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-3.3V";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	reg_5v: regulator-5v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-5V";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	gpio-keys {
-		compatible = "gpio-keys";
-		reset {
-			label = "reset";
-			linux,code = <KEY_RESTART>;
-			gpios = <&pio 1 GPIO_ACTIVE_LOW>;
-		};
-		wps {
-			label = "wps";
-			linux,code = <KEY_WPS_BUTTON>;
-			gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&eth {
-	status = "okay";
-
-	gmac0: mac@0 {
-		compatible = "mediatek,eth-mac";
-		reg = <0>;
-		phy-mode = "2500base-x";
-
-		fixed-link {
-			speed = <2500>;
-			full-duplex;
-			pause;
-		};
-	};
-
-	gmac1: mac@1 {
-		compatible = "mediatek,eth-mac";
-		reg = <1>;
-		phy-mode = "gmii";
-		phy-handle = <&int_gbe_phy>;
-	};
-};
-
-&mdio_bus {
-	switch: switch@1f {
-		compatible = "mediatek,mt7531";
-		reg = <31>;
-		interrupt-controller;
-		#interrupt-cells = <1>;
-		interrupt-parent = <&pio>;
-		interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
-		reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
-	};
-};
-
-&crypto {
-	status = "okay";
-};
-
-&pio {
-	spi0_flash_pins: spi0-pins {
-		mux {
-			function = "spi";
-			groups = "spi0", "spi0_wp_hold";
-		};
-		conf-pu {
-			pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
-			drive-strength = <MTK_DRIVE_8mA>;
-			bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
-		};
-		conf-pd {
-			pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
-			drive-strength = <MTK_DRIVE_8mA>;
-			bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
-		};
-	};
-
-};
-
-&spi0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&spi0_flash_pins>;
-	cs-gpios = <0>, <0>;
-	#address-cells = <1>;
-	#size-cells = <0>;
-	status = "disabled";
-};
-
-&switch {
-	ports {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		port@0 {
-			reg = <0>;
-			label = "lan1";
-		};
-
-		port@1 {
-			reg = <1>;
-			label = "lan2";
-		};
-
-		port@2 {
-			reg = <2>;
-			label = "lan3";
-		};
-
-		port@3 {
-			reg = <3>;
-			label = "lan4";
-		};
-
-		sw_p5: port@5 {
-			reg = <5>;
-			label = "lan5";
-			status = "disabled";
-		};
-
-		port@6 {
-			reg = <6>;
-			ethernet = <&gmac0>;
-			phy-mode = "2500base-x";
-
-			fixed-link {
-				speed = <2500>;
-				full-duplex;
-				pause;
-			};
-		};
-	};
-};
-
-&xhci {
-	vusb33-supply = <&reg_3p3v>;
-	vbus-supply = <&reg_5v>;
-	status = "okay";
-};
-
-&uart0 {
-	status = "okay";
-};
-
-&usb_phy {
-	status = "okay";
-};
-
-&watchdog {
-	status = "okay";
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981.dtsi b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981.dtsi
deleted file mode 100644
index cb161df81e9d57..00000000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981.dtsi
+++ /dev/null
@@ -1,820 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (c) 2020 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- * Author: Jianhui Zhao <zhaojh329@gmail.com>
- */
-
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/phy/phy.h>
-#include <dt-bindings/clock/mediatek,mt7981-clk.h>
-#include <dt-bindings/reset/mt7986-resets.h>
-#include <dt-bindings/pinctrl/mt65xx.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/input/linux-event-codes.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/mux/mux.h>
-
-/ {
-	compatible = "mediatek,mt7981";
-	interrupt-parent = <&gic>;
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		cpu@0 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a53";
-			enable-method = "psci";
-			reg = <0x0>;
-		};
-
-		cpu@1 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a53";
-			enable-method = "psci";
-			reg = <0x1>;
-		};
-	};
-
-	pwm: pwm@10048000 {
-		compatible = "mediatek,mt7981-pwm";
-		reg = <0 0x10048000 0 0x1000>;
-		#pwm-cells = <2>;
-		clocks = <&infracfg CLK_INFRA_PWM_STA>,
-			 <&infracfg CLK_INFRA_PWM_HCK>,
-			 <&infracfg CLK_INFRA_PWM1_CK>,
-			 <&infracfg CLK_INFRA_PWM2_CK>,
-			 <&infracfg CLK_INFRA_PWM3_CK>;
-		clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
-	};
-
-	fan: pwm-fan {
-		compatible = "pwm-fan";
-		/* cooling level (0, 1, 2, 3, 4, 5, 6, 7) : (0%/25%/37.5%/50%/62.5%/75%/87.5%/100% duty) */
-		cooling-levels = <0 63 95 127 159 191 223 255>;
-		#cooling-cells = <2>;
-		status = "disabled";
-	};
-
-	thermal-zones {
-		cpu_thermal: cpu-thermal {
-			polling-delay-passive = <1000>;
-			polling-delay = <1000>;
-			thermal-sensors = <&thermal 0>;
-			trips {
-				cpu_trip_active_highest: active-highest {
-					temperature = <70000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-
-				cpu_trip_active_high: active-high {
-					temperature = <60000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-
-				cpu_trip_active_med: active-med {
-					temperature = <50000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-
-				cpu_trip_active_low: active-low {
-					temperature = <45000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-
-				cpu_trip_active_lowest: active-lowest {
-					temperature = <40000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-			};
-
-			cooling-maps {
-				cpu-active-highest {
-					/* active: set fan to cooling level 7 */
-					cooling-device = <&fan 7 7>;
-					trip = <&cpu_trip_active_highest>;
-				};
-
-				cpu-active-high {
-					/* active: set fan to cooling level 5 */
-					cooling-device = <&fan 5 5>;
-					trip = <&cpu_trip_active_high>;
-				};
-
-				cpu-active-med {
-					/* active: set fan to cooling level 3 */
-					cooling-device = <&fan 3 3>;
-					trip = <&cpu_trip_active_med>;
-				};
-
-				cpu-active-low {
-					/* active: set fan to cooling level 2 */
-					cooling-device = <&fan 2 2>;
-					trip = <&cpu_trip_active_low>;
-				};
-
-				cpu-active-lowest {
-					/* active: set fan to cooling level 1 */
-					cooling-device = <&fan 1 1>;
-					trip = <&cpu_trip_active_lowest>;
-				};
-			};
-		};
-	};
-
-	thermal: thermal@1100c800 {
-		#thermal-sensor-cells = <1>;
-		compatible = "mediatek,mt7981-thermal", "mediatek,mt7986-thermal";
-		reg = <0 0x1100c800 0 0x800>;
-		interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&infracfg CLK_INFRA_THERM_CK>,
-			 <&infracfg CLK_INFRA_ADC_26M_CK>;
-		clock-names = "therm", "auxadc";
-		mediatek,auxadc = <&auxadc>;
-		mediatek,apmixedsys = <&apmixedsys>;
-		nvmem-cells = <&thermal_calibration>;
-		nvmem-cell-names = "calibration-data";
-	};
-
-	auxadc: adc@1100d000 {
-		compatible = "mediatek,mt7981-auxadc",
-			     "mediatek,mt7986-auxadc",
-			     "mediatek,mt7622-auxadc";
-		reg = <0 0x1100d000 0 0x1000>;
-		clocks = <&infracfg CLK_INFRA_ADC_26M_CK>,
-			 <&infracfg CLK_INFRA_ADC_FRC_CK>;
-		clock-names = "main", "32k";
-		#io-channel-cells = <1>;
-	};
-
-	wdma: wdma@15104800 {
-		compatible = "mediatek,wed-wdma";
-		reg = <0 0x15104800 0 0x400>,
-		      <0 0x15104c00 0 0x400>;
-	};
-
-	ap2woccif: ap2woccif@151a5000 {
-		compatible = "mediatek,ap2woccif";
-		reg = <0 0x151a5000 0 0x1000>,
-		      <0 0x151ad000 0 0x1000>;
-		interrupt-parent = <&gic>;
-		interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	reserved-memory {
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
-
-		/* 64 KiB reserved for ramoops/pstore */
-		ramoops@42ff0000 {
-			compatible = "ramoops";
-			reg = <0 0x42ff0000 0 0x10000>;
-			record-size = <0x1000>;
-		};
-
-		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
-		secmon_reserved: secmon@43000000 {
-			reg = <0 0x43000000 0 0x30000>;
-			no-map;
-		};
-
-		wmcpu_emi: wmcpu-reserved@47c80000 {
-			reg = <0 0x47c80000 0 0x100000>;
-			no-map;
-		};
-
-		wo_emi0: wo-emi@47d80000 {
-			reg = <0 0x47d80000 0 0x40000>;
-			no-map;
-		};
-
-		wo_data: wo-data@47dc0000 {
-			reg = <0 0x47dc0000 0 0x240000>;
-			no-map;
-		};
-	};
-
-	psci {
-		compatible  = "arm,psci-0.2";
-		method      = "smc";
-	};
-
-	trng {
-		compatible = "mediatek,mt7981-rng";
-	};
-
-	clk40m: oscillator@0 {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <40000000>;
-		clock-output-names = "clkxtal";
-	};
-
-	infracfg: infracfg@10001000 {
-		compatible = "mediatek,mt7981-infracfg", "syscon";
-		reg = <0 0x10001000 0 0x1000>;
-		#clock-cells = <1>;
-	};
-
-	topckgen: topckgen@1001B000 {
-		compatible = "mediatek,mt7981-topckgen", "syscon";
-		reg = <0 0x1001B000 0 0x1000>;
-		#clock-cells = <1>;
-	};
-
-	apmixedsys: apmixedsys@1001E000 {
-		compatible = "mediatek,mt7981-apmixedsys", "mediatek,mt7986-apmixedsys", "syscon";
-		reg = <0 0x1001E000 0 0x1000>;
-		#clock-cells = <1>;
-	};
-
-	timer {
-		compatible = "arm,armv8-timer";
-		interrupt-parent = <&gic>;
-		clock-frequency = <13000000>;
-		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
-
-	};
-
-	watchdog: watchdog@1001c000 {
-		compatible = "mediatek,mt7986-wdt",
-			     "mediatek,mt6589-wdt";
-		reg = <0 0x1001c000 0 0x1000>;
-		interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
-		#reset-cells = <1>;
-		status = "disabled";
-	};
-
-	gic: interrupt-controller@c000000 {
-		compatible = "arm,gic-v3";
-		#interrupt-cells = <3>;
-		interrupt-parent = <&gic>;
-		interrupt-controller;
-		reg = <0 0x0c000000 0 0x40000>,  /* GICD */
-		      <0 0x0c080000 0 0x200000>; /* GICR */
-
-		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	uart0: serial@11002000 {
-		compatible = "mediatek,mt6577-uart";
-		reg = <0 0x11002000 0 0x400>;
-		interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&infracfg CLK_INFRA_UART0_SEL>,
-			<&infracfg CLK_INFRA_UART0_CK>;
-		clock-names = "baud", "bus";
-		assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
-				  <&infracfg CLK_INFRA_UART0_SEL>;
-		assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
-					 <&topckgen CLK_TOP_UART_SEL>;
-		pinctrl-0 = <&uart0_pins>;
-		pinctrl-names = "default";
-		status = "disabled";
-	};
-
-	uart1: serial@11003000 {
-		compatible = "mediatek,mt6577-uart";
-		reg = <0 0x11003000 0 0x400>;
-		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&infracfg CLK_INFRA_UART1_SEL>,
-			<&infracfg CLK_INFRA_UART1_CK>;
-		clock-names = "baud", "bus";
-		assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
-				  <&infracfg CLK_INFRA_UART1_SEL>;
-		assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
-					 <&topckgen CLK_TOP_UART_SEL>;
-		status = "disabled";
-	};
-
-	uart2: serial@11004000 {
-		compatible = "mediatek,mt6577-uart";
-		reg = <0 0x11004000 0 0x400>;
-		interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&infracfg CLK_INFRA_UART2_SEL>,
-			<&infracfg CLK_INFRA_UART2_CK>;
-		clock-names = "baud", "bus";
-		assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
-				  <&infracfg CLK_INFRA_UART2_SEL>;
-		assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
-					 <&topckgen CLK_TOP_UART_SEL>;
-		status = "disabled";
-	};
-
-	i2c0: i2c@11007000 {
-		compatible = "mediatek,mt7981-i2c";
-		reg = <0 0x11007000 0 0x1000>,
-		      <0 0x10217080 0 0x80>;
-		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
-		clock-div = <1>;
-		clocks = <&infracfg CLK_INFRA_I2C0_CK>,
-			 <&infracfg CLK_INFRA_AP_DMA_CK>,
-			 <&infracfg CLK_INFRA_I2C_MCK_CK>,
-			 <&infracfg CLK_INFRA_I2C_PCK_CK>;
-		clock-names = "main", "dma", "arb", "pmic";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-	};
-
-	pcie: pcie@11280000 {
-		compatible = "mediatek,mt7981-pcie",
-			     "mediatek,mt7986-pcie";
-		device_type = "pci";
-		reg = <0 0x11280000 0 0x4000>;
-		reg-names = "pcie-mac";
-		#address-cells = <3>;
-		#size-cells = <2>;
-		interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
-		bus-range = <0x00 0xff>;
-		ranges = <0x82000000 0 0x20000000
-			  0x0 0x20000000 0 0x10000000>;
-		status = "disabled";
-
-		clocks = <&infracfg CLK_INFRA_IPCIE_CK>,
-			 <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
-			 <&infracfg CLK_INFRA_IPCIER_CK>,
-			 <&infracfg CLK_INFRA_IPCIEB_CK>;
-
-		phys = <&u3port0 PHY_TYPE_PCIE>;
-		phy-names = "pcie-phy";
-
-		#interrupt-cells = <1>;
-		interrupt-map-mask = <0 0 0 7>;
-		interrupt-map = <0 0 0 1 &pcie_intc 0>,
-				<0 0 0 2 &pcie_intc 1>,
-				<0 0 0 3 &pcie_intc 2>,
-				<0 0 0 4 &pcie_intc 3>;
-		pcie_intc: interrupt-controller {
-			interrupt-controller;
-			#address-cells = <0>;
-			#interrupt-cells = <1>;
-		};
-	};
-
-	crypto: crypto@10320000 {
-		compatible = "inside-secure,safexcel-eip97";
-		reg = <0 0x10320000 0 0x40000>;
-		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "ring0", "ring1", "ring2", "ring3";
-		clocks = <&topckgen CLK_TOP_EIP97B>;
-		clock-names = "top_eip97_ck";
-		assigned-clocks = <&topckgen CLK_TOP_EIP97B_SEL>;
-		assigned-clock-parents = <&topckgen CLK_TOP_CB_NET1_D5>;
-	};
-
-	pio: pinctrl@11d00000 {
-		compatible = "mediatek,mt7981-pinctrl";
-		reg = <0 0x11d00000 0 0x1000>,
-		      <0 0x11c00000 0 0x1000>,
-		      <0 0x11c10000 0 0x1000>,
-		      <0 0x11d20000 0 0x1000>,
-		      <0 0x11e00000 0 0x1000>,
-		      <0 0x11e20000 0 0x1000>,
-		      <0 0x11f00000 0 0x1000>,
-		      <0 0x11f10000 0 0x1000>,
-		      <0 0x1000b000 0 0x1000>;
-		reg-names = "gpio", "iocfg_rt", "iocfg_rm",
-			    "iocfg_rb", "iocfg_lb", "iocfg_bl",
-			    "iocfg_tm", "iocfg_tl", "eint";
-		gpio-controller;
-		#gpio-cells = <2>;
-		gpio-ranges = <&pio 0 0 56>;
-		interrupt-controller;
-		interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&gic>;
-		#interrupt-cells = <2>;
-
-		mdio_pins: mdc-mdio-pins {
-			mux {
-				function = "eth";
-				groups = "smi_mdc_mdio";
-			};
-		};
-
-		uart0_pins: uart0-pins {
-			mux {
-				function = "uart";
-				groups = "uart0";
-			};
-		};
-
-		wifi_dbdc_pins: wifi-dbdc-pins {
-			mux {
-				function = "eth";
-				groups = "wf0_mode1";
-			};
-			conf {
-				pins = "WF_HB1", "WF_HB2", "WF_HB3", "WF_HB4",
-				       "WF_HB0", "WF_HB0_B", "WF_HB5", "WF_HB6",
-				       "WF_HB7", "WF_HB8", "WF_HB9", "WF_HB10",
-				       "WF_TOP_CLK", "WF_TOP_DATA", "WF_XO_REQ",
-				       "WF_CBA_RESETB", "WF_DIG_RESETB";
-				drive-strength = <4>;
-			};
-		};
-
-		gbe_led0_pins: gbe-led0-pins {
-			mux {
-				function = "led";
-				groups = "gbe_led0";
-			};
-		};
-
-		gbe_led1_pins: gbe-led1-pins {
-			mux {
-				function = "led";
-				groups = "gbe_led1";
-			};
-		};
-	};
-
-	ethsys: syscon@15000000 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "mediatek,mt7981-ethsys",
-			     "mediatek,mt7986-ethsys",
-			     "syscon";
-		reg = <0 0x15000000 0 0x1000>;
-		#clock-cells = <1>;
-		#reset-cells = <1>;
-	};
-
-	wed: wed@15010000 {
-		compatible = "mediatek,mt7981-wed",
-			     "mediatek,mt7986-wed",
-			     "syscon";
-		reg = <0 0x15010000 0 0x1000>;
-		interrupt-parent = <&gic>;
-		interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
-		memory-region = <&wo_emi0>, <&wo_data>;
-		memory-region-names = "wo-emi", "wo-data";
-		mediatek,wo-ccif = <&wo_ccif0>;
-		mediatek,wo-ilm = <&wo_ilm0>;
-		mediatek,wo-dlm = <&wo_dlm0>;
-		mediatek,wo-cpuboot = <&wo_cpuboot>;
-	};
-
-	eth: ethernet@15100000 {
-		compatible = "mediatek,mt7981-eth";
-		reg = <0 0x15100000 0 0x80000>;
-		interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&ethsys CLK_ETH_FE_EN>,
-			<&ethsys CLK_ETH_GP2_EN>,
-			<&ethsys CLK_ETH_GP1_EN>,
-			<&ethsys CLK_ETH_WOCPU0_EN>,
-			<&sgmiisys0 CLK_SGM0_TX_EN>,
-			<&sgmiisys0 CLK_SGM0_RX_EN>,
-			<&sgmiisys0 CLK_SGM0_CK0_EN>,
-			<&sgmiisys0 CLK_SGM0_CDR_CK0_EN>,
-			<&sgmiisys1 CLK_SGM1_TX_EN>,
-			<&sgmiisys1 CLK_SGM1_RX_EN>,
-			<&sgmiisys1 CLK_SGM1_CK1_EN>,
-			<&sgmiisys1 CLK_SGM1_CDR_CK1_EN>,
-			<&topckgen CLK_TOP_SGM_REG>,
-			<&topckgen CLK_TOP_NETSYS_SEL>,
-			<&topckgen CLK_TOP_NETSYS_500M_SEL>;
-		clock-names = "fe", "gp2", "gp1", "wocpu0",
-					"sgmii_tx250m", "sgmii_rx250m",
-					"sgmii_cdr_ref", "sgmii_cdr_fb",
-					"sgmii2_tx250m", "sgmii2_rx250m",
-					"sgmii2_cdr_ref", "sgmii2_cdr_fb",
-					"sgmii_ck", "netsys0", "netsys1";
-		assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
-				  <&topckgen CLK_TOP_SGM_325M_SEL>;
-		assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_800M>,
-					 <&topckgen CLK_TOP_CB_SGM_325M>;
-		mediatek,ethsys = <&ethsys>;
-		mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
-		mediatek,infracfg = <&topmisc>;
-		mediatek,wed = <&wed>;
-		#reset-cells = <1>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-
-		mdio_bus: mdio-bus {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			int_gbe_phy: ethernet-phy@0 {
-				reg = <0>;
-				compatible = "ethernet-phy-ieee802.3-c22";
-				phy-mode = "gmii";
-				phy-is-integrated;
-				nvmem-cells = <&phy_calibration>;
-				nvmem-cell-names = "phy-cal-data";
-
-				leds {
-					#address-cells = <1>;
-					#size-cells = <0>;
-
-					int_gbe_phy_led0: int-gbe-phy-led0@0 {
-						reg = <0>;
-						function = LED_FUNCTION_LAN;
-						status = "disabled";
-					};
-
-					int_gbe_phy_led1: int-gbe-phy-led1@1 {
-						reg = <1>;
-						function = LED_FUNCTION_LAN;
-						status = "disabled";
-					};
-				};
-			};
-		};
-	};
-
-	wo_dlm0: syscon@151e8000 {
-		compatible = "mediatek,mt7986-wo-dlm", "syscon";
-		reg = <0 0x151e8000 0 0x2000>;
-	};
-
-	wo_ilm0: syscon@151e0000 {
-		compatible = "mediatek,mt7986-wo-ilm", "syscon";
-		reg = <0 0x151e0000 0 0x8000>;
-	};
-
-	wo_cpuboot: syscon@15194000 {
-		compatible = "mediatek,mt7986-wo-cpuboot", "syscon";
-		reg = <0 0x15194000 0 0x1000>;
-	};
-
-	wo_ccif0: syscon@151a5000 {
-		compatible = "mediatek,mt7986-wo-ccif", "syscon";
-		reg = <0 0x151a5000 0 0x1000>;
-		interrupt-parent = <&gic>;
-		interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	sgmiisys0: syscon@10060000 {
-		compatible = "mediatek,mt7981-sgmiisys_0", "mediatek,mt7986-sgmiisys_0", "syscon";
-		reg = <0 0x10060000 0 0x1000>;
-		mediatek,pnswap;
-		#clock-cells = <1>;
-	};
-
-	sgmiisys1: syscon@10070000 {
-		compatible = "mediatek,mt7981-sgmiisys_1", "mediatek,mt7986-sgmiisys_1", "syscon";
-		reg = <0 0x10070000 0 0x1000>;
-		#clock-cells = <1>;
-	};
-
-	topmisc: topmisc@11d10000 {
-		compatible = "mediatek,mt7981-topmisc", "syscon";
-		reg = <0 0x11d10000 0 0x10000>;
-		#clock-cells = <1>;
-	};
-
-	snand: snfi@11005000 {
-		compatible = "mediatek,mt7986-snand";
-		reg = <0 0x11005000 0 0x1000>, <0 0x11006000 0 0x1000>;
-		reg-names = "nfi", "ecc";
-		interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&infracfg CLK_INFRA_SPINFI1_CK>,
-			 <&infracfg CLK_INFRA_NFI1_CK>,
-			 <&infracfg CLK_INFRA_NFI_HCK_CK>;
-		clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
-		assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
-				  <&topckgen CLK_TOP_NFI1X_SEL>;
-		assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D8>,
-					 <&topckgen CLK_TOP_CB_M_D8>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-	};
-
-	mmc0: mmc@11230000 {
-		compatible = "mediatek,mt7986-mmc",
-					"mediatek,mt7981-mmc";
-		reg = <0 0x11230000 0 0x1000>, <0 0x11c20000 0 0x1000>;
-		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&infracfg CLK_INFRA_MSDC_CK>,
-			 <&infracfg CLK_INFRA_MSDC_HCK_CK>,
-			 <&infracfg CLK_INFRA_MSDC_66M_CK>,
-			 <&infracfg CLK_INFRA_MSDC_133M_CK>;
-		assigned-clocks = <&topckgen CLK_TOP_EMMC_208M_SEL>,
-				  <&topckgen CLK_TOP_EMMC_400M_SEL>;
-		assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
-					 <&topckgen CLK_TOP_CB_NET2_D2>;
-		clock-names = "source", "hclk", "axi_cg", "ahb_cg";
-		status = "disabled";
-	};
-
-	wed_pcie: wed_pcie@10003000 {
-		compatible = "mediatek,wed_pcie";
-		reg = <0 0x10003000 0 0x10>;
-	};
-
-	spi0: spi@1100a000 {
-		compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0 0x1100a000 0 0x100>;
-		interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&topckgen CLK_TOP_CB_M_D2>,
-			 <&topckgen CLK_TOP_SPI_SEL>,
-			 <&infracfg CLK_INFRA_SPI0_CK>,
-			 <&infracfg CLK_INFRA_SPI0_HCK_CK>;
-
-		clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
-		status = "disabled";
-	};
-
-	spi1: spi@1100b000 {
-		compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0 0x1100b000 0 0x100>;
-		interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&topckgen CLK_TOP_CB_M_D2>,
-			 <&topckgen CLK_TOP_SPIM_MST_SEL>,
-			 <&infracfg CLK_INFRA_SPI1_CK>,
-			 <&infracfg CLK_INFRA_SPI1_HCK_CK>;
-		clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
-		status = "disabled";
-	};
-
-	spi2: spi@11009000 {
-		compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0 0x11009000 0 0x100>;
-		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&topckgen CLK_TOP_CB_M_D2>,
-			 <&topckgen CLK_TOP_SPI_SEL>,
-			 <&infracfg CLK_INFRA_SPI2_CK>,
-			 <&infracfg CLK_INFRA_SPI2_HCK_CK>;
-		clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
-		status = "disabled";
-	};
-
-	consys: consys@10000000 {
-		compatible = "mediatek,mt7981-consys";
-		reg = <0 0x10000000 0 0x8600000>;
-		memory-region = <&wmcpu_emi>;
-	};
-
-	xhci: usb@11200000 {
-		compatible = "mediatek,mt7986-xhci",
-			     "mediatek,mtk-xhci";
-		reg = <0 0x11200000 0 0x2e00>,
-		      <0 0x11203e00 0 0x0100>;
-		reg-names = "mac", "ippc";
-		interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
-			 <&infracfg CLK_INFRA_IUSB_CK>,
-			 <&infracfg CLK_INFRA_IUSB_133_CK>,
-			 <&infracfg CLK_INFRA_IUSB_66M_CK>,
-			 <&topckgen CLK_TOP_U2U3_XHCI_SEL>;
-		clock-names = "sys_ck",
-			      "ref_ck",
-			      "mcu_ck",
-			      "dma_ck",
-			      "xhci_ck";
-		phys = <&u2port0 PHY_TYPE_USB2>,
-		       <&u3port0 PHY_TYPE_USB3>;
-		vusb33-supply = <&reg_3p3v>;
-		status = "disabled";
-	};
-
-	usb_phy: usb-phy@11e10000 {
-		compatible = "mediatek,mt7981",
-			     "mediatek,generic-tphy-v2";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0 0 0x11e10000 0x1700>;
-		status = "disabled";
-
-		u2port0: usb-phy@0 {
-			reg = <0x0 0x700>;
-			clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>;
-			clock-names = "ref";
-			#phy-cells = <1>;
-		};
-
-		u3port0: usb-phy@700 {
-			reg = <0x700 0x900>;
-			clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
-			clock-names = "ref";
-			#phy-cells = <1>;
-			mediatek,syscon-type = <&topmisc 0x218 0>;
-			status = "okay";
-		};
-	};
-
-	reg_3p3v: regulator-3p3v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-3.3V";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	efuse: efuse@11f20000 {
-		compatible = "mediatek,mt7981-efuse",
-			     "mediatek,efuse";
-		reg = <0 0x11f20000 0 0x1000>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		status = "okay";
-
-		thermal_calibration: thermal-calib@274 {
-			reg = <0x274 0xc>;
-		};
-
-		phy_calibration: phy-calib@8dc {
-			reg = <0x8dc 0x10>;
-		};
-
-		comb_rx_imp_p0: usb3-rx-imp@8c8 {
-			reg = <0x8c8 1>;
-			bits = <0 5>;
-		};
-
-		comb_tx_imp_p0: usb3-tx-imp@8c8 {
-			reg = <0x8c8 2>;
-			bits = <5 5>;
-		};
-
-		comb_intr_p0: usb3-intr@8c9 {
-			reg = <0x8c9 1>;
-			bits = <2 6>;
-		};
-	};
-
-	afe: audio-controller@11210000 {
-		compatible = "mediatek,mt79xx-audio";
-		reg = <0 0x11210000 0 0x9000>;
-		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&infracfg CLK_INFRA_AUD_BUS_CK>,
-			 <&infracfg CLK_INFRA_AUD_26M_CK>,
-			 <&infracfg CLK_INFRA_AUD_L_CK>,
-			 <&infracfg CLK_INFRA_AUD_AUD_CK>,
-			 <&infracfg CLK_INFRA_AUD_EG2_CK>,
-			 <&topckgen CLK_TOP_AUD_SEL>;
-		clock-names = "aud_bus_ck",
-			      "aud_26m_ck",
-			      "aud_l_ck",
-			      "aud_aud_ck",
-			      "aud_eg2_ck",
-			      "aud_sel";
-		assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
-				  <&topckgen CLK_TOP_A1SYS_SEL>,
-				  <&topckgen CLK_TOP_AUD_L_SEL>,
-				  <&topckgen CLK_TOP_A_TUNER_SEL>;
-		assigned-clock-parents = <&topckgen CLK_TOP_CB_APLL2_196M>,
-					 <&topckgen CLK_TOP_APLL2_D4>,
-					 <&topckgen CLK_TOP_CB_APLL2_196M>,
-					 <&topckgen CLK_TOP_APLL2_D4>;
-		status = "disabled";
-	};
-
-	ice: ice_debug {
-		compatible = "mediatek,mt7981-ice_debug",
-			   "mediatek,mt2701-ice_debug";
-		clocks = <&infracfg CLK_INFRA_DBG_CK>;
-		clock-names = "ice_dbg";
-	};
-
-	wifi: wifi@18000000 {
-		compatible = "mediatek,mt7981-wmac";
-		resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
-		reset-names = "consys";
-		pinctrl-0 = <&wifi_dbdc_pins>;
-		pinctrl-names = "dbdc";
-		clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>,
-			 <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
-		clock-names = "mcu", "ap2conn";
-		reg = <0 0x18000000 0 0x1000000>,
-		      <0 0x10003000 0 0x1000>,
-		      <0 0x11d10000 0 0x1000>;
-		interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
-		memory-region = <&wmcpu_emi>;
-		status = "disabled";
-	};
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso
deleted file mode 100644
index 779dc6782bb198..00000000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso
+++ /dev/null
@@ -1,29 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2021 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
-	compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
-
-	fragment@0 {
-		target-path = "/soc/mmc@11230000";
-		__overlay__ {
-			bus-width = <8>;
-			max-frequency = <200000000>;
-			cap-mmc-highspeed;
-			mmc-hs200-1_8v;
-			mmc-hs400-1_8v;
-			hs400-ds-delay = <0x14014>;
-			non-removable;
-			no-sd;
-			no-sdio;
-			status = "okay";
-		};
-	};
-};
-
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
deleted file mode 100644
index 0846d88f625aa5..00000000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
+++ /dev/null
@@ -1,55 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-/*
- * Authors: Daniel Golle <daniel@makrotopia.org>
- *          Frank Wunderlich <frank-w@public-files.de>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
-	compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
-
-	fragment@0 {
-		target-path = "/soc/spi@1100a000";
-		__overlay__ {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			spi_nand: spi_nand@0 {
-				compatible = "spi-nand";
-				reg = <0>;
-				spi-max-frequency = <10000000>;
-				spi-tx-bus-width = <4>;
-				spi-rx-bus-width = <4>;
-
-				partitions {
-					compatible = "fixed-partitions";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					partition@0 {
-						label = "bl2";
-						reg = <0x0 0x80000>;
-						read-only;
-					};
-
-					partition@80000 {
-						label = "reserved";
-						reg = <0x80000 0x300000>;
-					};
-
-					partition@380000 {
-						label = "fip";
-						reg = <0x380000 0x200000>;
-						read-only;
-					};
-
-					partition@580000 {
-						label = "ubi";
-						reg = <0x580000 0x7a80000>;
-					};
-				};
-			};
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
deleted file mode 100644
index e48881be4ed60c..00000000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
+++ /dev/null
@@ -1,63 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-/*
- * Authors: Daniel Golle <daniel@makrotopia.org>
- *          Frank Wunderlich <frank-w@public-files.de>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
-	compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
-
-	fragment@0 {
-		target-path = "/soc/spi@1100a000";
-		__overlay__ {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			flash@0 {
-				compatible = "jedec,spi-nor";
-				reg = <0>;
-				spi-max-frequency = <10000000>;
-
-				partitions {
-					compatible = "fixed-partitions";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					partition@0 {
-						label = "bl2";
-						reg = <0x0 0x40000>;
-						read-only;
-					};
-
-					partition@40000 {
-						label = "u-boot-env";
-						reg = <0x40000 0x40000>;
-					};
-
-					partition@80000 {
-						label = "reserved2";
-						reg = <0x80000 0x80000>;
-					};
-
-					partition@100000 {
-						label = "fip";
-						reg = <0x100000 0x80000>;
-						read-only;
-					};
-
-					partition@180000 {
-						label = "recovery";
-						reg = <0x180000 0xa80000>;
-					};
-
-					partition@c00000 {
-						label = "fit";
-						reg = <0xc00000 0x1400000>;
-					};
-				};
-			};
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso
deleted file mode 100644
index f623bce075ce6e..00000000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso
+++ /dev/null
@@ -1,23 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2021 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
-	compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
-
-	fragment@0 {
-		target-path = "/soc/mmc@11230000";
-		__overlay__ {
-			bus-width = <4>;
-			max-frequency = <52000000>;
-			cap-sd-highspeed;
-			status = "okay";
-		};
-	};
-};
-
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
deleted file mode 100644
index d326c416a9d3ae..00000000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
+++ /dev/null
@@ -1,501 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2021 MediaTek Inc.
- * Authors: Sam.Shih <sam.shih@mediatek.com>
- *          Frank Wunderlich <frank-w@public-files.de>
- *          Daniel Golle <daniel@makrotopia.org>
- */
-
-/dts-v1/;
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/pinctrl/mt65xx.h>
-
-#include "mt7986a.dtsi"
-
-/ {
-	model = "Bananapi BPI-R3";
-	chassis-type = "embedded";
-	compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
-
-	aliases {
-		serial0 = &uart0;
-		ethernet0 = &gmac0;
-		ethernet1 = &gmac1;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	dcin: regulator-12vd {
-		compatible = "regulator-fixed";
-		regulator-name = "12vd";
-		regulator-min-microvolt = <12000000>;
-		regulator-max-microvolt = <12000000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	fan: pwm-fan {
-		compatible = "pwm-fan";
-		#cooling-cells = <2>;
-		/* cooling level (0, 1, 2) - pwm inverted */
-		cooling-levels = <255 96 0>;
-		pwms = <&pwm 0 10000 0>;
-		status = "okay";
-	};
-
-	gpio-keys {
-		compatible = "gpio-keys";
-
-		reset-key {
-			label = "reset";
-			linux,code = <KEY_RESTART>;
-			gpios = <&pio 9 GPIO_ACTIVE_LOW>;
-		};
-
-		wps-key {
-			label = "wps";
-			linux,code = <KEY_WPS_BUTTON>;
-			gpios = <&pio 10 GPIO_ACTIVE_LOW>;
-		};
-	};
-
-	/* i2c of the left SFP cage (wan) */
-	i2c_sfp1: i2c-gpio-0 {
-		compatible = "i2c-gpio";
-		sda-gpios = <&pio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-		scl-gpios = <&pio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-		i2c-gpio,delay-us = <2>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-	};
-
-	/* i2c of the right SFP cage (lan) */
-	i2c_sfp2: i2c-gpio-1 {
-		compatible = "i2c-gpio";
-		sda-gpios = <&pio 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-		scl-gpios = <&pio 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-		i2c-gpio,delay-us = <2>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		green_led: led-0 {
-			color = <LED_COLOR_ID_GREEN>;
-			function = LED_FUNCTION_POWER;
-			gpios = <&pio 69 GPIO_ACTIVE_HIGH>;
-			default-state = "on";
-		};
-
-		blue_led: led-1 {
-			color = <LED_COLOR_ID_BLUE>;
-			function = LED_FUNCTION_STATUS;
-			gpios = <&pio 86 GPIO_ACTIVE_HIGH>;
-			default-state = "off";
-		};
-	};
-
-	reg_1p8v: regulator-1p8v {
-		compatible = "regulator-fixed";
-		regulator-name = "1.8vd";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		regulator-boot-on;
-		regulator-always-on;
-		vin-supply = <&dcin>;
-	};
-
-	reg_3p3v: regulator-3p3v {
-		compatible = "regulator-fixed";
-		regulator-name = "3.3vd";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		regulator-always-on;
-		vin-supply = <&dcin>;
-	};
-
-	/* left SFP cage (wan) */
-	sfp1: sfp-1 {
-		compatible = "sff,sfp";
-		i2c-bus = <&i2c_sfp1>;
-		los-gpios = <&pio 46 GPIO_ACTIVE_HIGH>;
-		mod-def0-gpios = <&pio 49 GPIO_ACTIVE_LOW>;
-		tx-disable-gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
-		tx-fault-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
-		maximum-power-milliwatt = <3000>;
-	};
-
-	/* right SFP cage (lan) */
-	sfp2: sfp-2 {
-		compatible = "sff,sfp";
-		i2c-bus = <&i2c_sfp2>;
-		los-gpios = <&pio 31 GPIO_ACTIVE_HIGH>;
-		mod-def0-gpios = <&pio 47 GPIO_ACTIVE_LOW>;
-		tx-disable-gpios = <&pio 15 GPIO_ACTIVE_HIGH>;
-		tx-fault-gpios = <&pio 48 GPIO_ACTIVE_HIGH>;
-		maximum-power-milliwatt = <3000>;
-	};
-};
-
-&cpu_thermal {
-	cooling-maps {
-		cpu-active-high {
-			/* active: set fan to cooling level 2 */
-			cooling-device = <&fan 2 2>;
-			trip = <&cpu_trip_active_high>;
-		};
-
-		cpu-active-med {
-			/* active: set fan to cooling level 1 */
-			cooling-device = <&fan 1 1>;
-			trip = <&cpu_trip_active_med>;
-		};
-
-		cpu-active-low {
-			/* active: set fan to cooling level 0 */
-			cooling-device = <&fan 0 0>;
-			trip = <&cpu_trip_active_low>;
-		};
-	};
-};
-
-&crypto {
-	status = "okay";
-};
-
-&eth {
-	status = "okay";
-
-	gmac0: mac@0 {
-		compatible = "mediatek,eth-mac";
-		reg = <0>;
-		phy-mode = "2500base-x";
-
-		fixed-link {
-			speed = <2500>;
-			full-duplex;
-			pause;
-		};
-	};
-
-	gmac1: mac@1 {
-		compatible = "mediatek,eth-mac";
-		reg = <1>;
-		phy-mode = "2500base-x";
-		sfp = <&sfp1>;
-		managed = "in-band-status";
-	};
-
-	mdio: mdio-bus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-	};
-};
-
-&mdio {
-	switch: switch@1f {
-		compatible = "mediatek,mt7531";
-		reg = <31>;
-		interrupt-controller;
-		#interrupt-cells = <1>;
-		interrupt-parent = <&pio>;
-		interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
-		reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
-	};
-};
-
-&mmc0 {
-	pinctrl-names = "default", "state_uhs";
-	pinctrl-0 = <&mmc0_pins_default>;
-	pinctrl-1 = <&mmc0_pins_uhs>;
-	vmmc-supply = <&reg_3p3v>;
-	vqmmc-supply = <&reg_1p8v>;
-};
-
-&i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c_pins>;
-	status = "okay";
-};
-
-&pcie {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pcie_pins>;
-	status = "okay";
-};
-
-&pcie_phy {
-	status = "okay";
-};
-
-&pio {
-	i2c_pins: i2c-pins {
-		mux {
-			function = "i2c";
-			groups = "i2c";
-		};
-	};
-
-	mmc0_pins_default: mmc0-pins {
-		mux {
-			function = "emmc";
-			groups = "emmc_51";
-		};
-		conf-cmd-dat {
-			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
-			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
-			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
-			input-enable;
-			drive-strength = <4>;
-			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
-		};
-		conf-clk {
-			pins = "EMMC_CK";
-			drive-strength = <6>;
-			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
-		};
-		conf-ds {
-			pins = "EMMC_DSL";
-			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
-		};
-		conf-rst {
-			pins = "EMMC_RSTB";
-			drive-strength = <4>;
-			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
-		};
-	};
-
-	mmc0_pins_uhs: mmc0-uhs-pins {
-		mux {
-			function = "emmc";
-			groups = "emmc_51";
-		};
-		conf-cmd-dat {
-			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
-			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
-			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
-			input-enable;
-			drive-strength = <4>;
-			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
-		};
-		conf-clk {
-			pins = "EMMC_CK";
-			drive-strength = <6>;
-			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
-		};
-		conf-ds {
-			pins = "EMMC_DSL";
-			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
-		};
-		conf-rst {
-			pins = "EMMC_RSTB";
-			drive-strength = <4>;
-			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
-		};
-	};
-
-	pcie_pins: pcie-pins {
-		mux {
-			function = "pcie";
-			groups = "pcie_clk", "pcie_pereset";
-		};
-	};
-
-	pwm_pins: pwm-pins {
-		mux {
-			function = "pwm";
-			groups = "pwm0", "pwm1_0";
-		};
-	};
-
-	spi_flash_pins: spi-flash-pins {
-		mux {
-			function = "spi";
-			groups = "spi0", "spi0_wp_hold";
-		};
-	};
-
-	spic_pins: spic-pins {
-		mux {
-			function = "spi";
-			groups = "spi1_0";
-		};
-	};
-
-	uart1_pins: uart1-pins {
-		mux {
-			function = "uart";
-			groups = "uart1_rx_tx";
-		};
-	};
-
-	uart2_pins: uart2-pins {
-		mux {
-			function = "uart";
-			groups = "uart2_0_rx_tx";
-		};
-	};
-
-	wf_2g_5g_pins: wf-2g-5g-pins {
-		mux {
-			function = "wifi";
-			groups = "wf_2g", "wf_5g";
-		};
-		conf {
-			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
-			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
-			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
-			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
-			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
-			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
-			       "WF1_TOP_CLK", "WF1_TOP_DATA";
-			drive-strength = <4>;
-		};
-	};
-
-	wf_dbdc_pins: wf-dbdc-pins {
-		mux {
-			function = "wifi";
-			groups = "wf_dbdc";
-		};
-		conf {
-			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
-			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
-			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
-			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
-			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
-			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
-			       "WF1_TOP_CLK", "WF1_TOP_DATA";
-			drive-strength = <4>;
-		};
-	};
-
-	wf_led_pins: wf-led-pins {
-		mux {
-			function = "led";
-			groups = "wifi_led";
-		};
-	};
-};
-
-&pwm {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pwm_pins>;
-	status = "okay";
-};
-
-&spi0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&spi_flash_pins>;
-	status = "okay";
-};
-
-&spi1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&spic_pins>;
-	status = "okay";
-};
-
-&ssusb {
-	status = "okay";
-};
-
-&switch {
-	ports {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		port@0 {
-			reg = <0>;
-			label = "wan";
-		};
-
-		port@1 {
-			reg = <1>;
-			label = "lan0";
-		};
-
-		port@2 {
-			reg = <2>;
-			label = "lan1";
-		};
-
-		port@3 {
-			reg = <3>;
-			label = "lan2";
-		};
-
-		port@4 {
-			reg = <4>;
-			label = "lan3";
-		};
-
-		port5: port@5 {
-			reg = <5>;
-			label = "lan4";
-			phy-mode = "2500base-x";
-			sfp = <&sfp2>;
-			managed = "in-band-status";
-		};
-
-		port@6 {
-			reg = <6>;
-			label = "cpu";
-			ethernet = <&gmac0>;
-			phy-mode = "2500base-x";
-
-			fixed-link {
-				speed = <2500>;
-				full-duplex;
-				pause;
-			};
-		};
-	};
-};
-
-&trng {
-	status = "okay";
-};
-
-&uart0 {
-	status = "okay";
-};
-
-&uart1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart1_pins>;
-	status = "okay";
-};
-
-&uart2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart2_pins>;
-	status = "okay";
-};
-
-&usb_phy {
-	status = "okay";
-};
-
-&watchdog {
-	status = "okay";
-};
-
-&wifi {
-	status = "okay";
-	pinctrl-names = "default", "dbdc";
-	pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>;
-	pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>;
-
-	led {
-		led-active-low;
-	};
-};
-
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts
deleted file mode 100644
index ce007099d2ba32..00000000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts
+++ /dev/null
@@ -1,52 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-
-#include "mt7986a-rfb.dtsi"
-
-/ {
-	compatible = "mediatek,mt7986a-rfb-snand";
-};
-
-&spi0 {
-	status = "okay";
-
-	spi_nand: spi_nand@0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "spi-nand";
-		reg = <1>;
-		spi-max-frequency = <10000000>;
-		spi-tx-bus-width = <4>;
-		spi-rx-bus-width = <4>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			partition@0 {
-				label = "BL2";
-				reg = <0x00000 0x0100000>;
-				read-only;
-			};
-			partition@100000 {
-				label = "u-boot-env";
-				reg = <0x0100000 0x0080000>;
-			};
-			factory: partition@180000 {
-				label = "Factory";
-				reg = <0x180000 0x0200000>;
-			};
-			partition@380000 {
-				label = "FIP";
-				reg = <0x380000 0x0200000>;
-			};
-			partition@580000 {
-				label = "ubi";
-				reg = <0x580000 0x4000000>;
-			};
-		};
-	};
-};
-
-&wifi {
-	mediatek,mtd-eeprom = <&factory 0>;
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nor.dts b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nor.dts
deleted file mode 100644
index ea148315f05534..00000000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nor.dts
+++ /dev/null
@@ -1,51 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-
-#include "mt7986a-rfb.dtsi"
-
-/ {
-	compatible = "mediatek,mt7986a-rfb-snor";
-};
-
-&spi0 {
-	status = "okay";
-
-	spi_nor: spi_nor@0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <52000000>;
-		spi-tx-bus-width = <4>;
-		spi-rx-bus-width = <4>;
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@00000 {
-				label = "BL2";
-				reg = <0x00000 0x0040000>;
-			};
-			partition@40000 {
-				label = "u-boot-env";
-				reg = <0x40000 0x0010000>;
-			};
-			factory: partition@50000 {
-				label = "Factory";
-				reg = <0x50000 0x00B0000>;
-			};
-			partition@100000 {
-				label = "FIP";
-				reg = <0x100000 0x0080000>;
-			};
-			partition@180000 {
-				label = "firmware";
-				reg = <0x180000 0xE00000>;
-			};
-		};
-	};
-};
-
-&wifi {
-	mediatek,mtd-eeprom = <&factory 0>;
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi
deleted file mode 100644
index 26d560bd4bcb11..00000000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi
+++ /dev/null
@@ -1,389 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2021 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-#include "mt7986a.dtsi"
-
-/ {
-	model = "MediaTek MT7986a RFB";
-	compatible = "mediatek,mt7986a-rfb";
-
-	aliases {
-		serial0 = &uart0;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	memory {
-		reg = <0 0x40000000 0 0x40000000>;
-	};
-
-	reg_1p8v: regulator-1p8v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-1.8V";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	reg_3p3v: regulator-3p3v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-3.3V";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	reg_5v: regulator-5v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-5V";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-};
-
-&eth {
-	status = "okay";
-
-	gmac0: mac@0 {
-		compatible = "mediatek,eth-mac";
-		reg = <0>;
-		phy-mode = "2500base-x";
-
-		fixed-link {
-			speed = <2500>;
-			full-duplex;
-			pause;
-		};
-	};
-
-	gmac1: mac@1 {
-		compatible = "mediatek,eth-mac";
-		reg = <1>;
-		phy-mode = "2500base-x";
-	};
-
-	mdio: mdio-bus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-	};
-};
-
-&wifi {
-	status = "okay";
-	pinctrl-names = "default", "dbdc";
-	pinctrl-0 = <&wf_2g_5g_pins>;
-	pinctrl-1 = <&wf_dbdc_pins>;
-};
-
-&mdio {
-	phy5: phy@5 {
-		compatible = "ethernet-phy-id67c9.de0a";
-		reg = <5>;
-
-		reset-gpios = <&pio 6 1>;
-		reset-deassert-us = <20000>;
-	};
-
-	phy6: phy@6 {
-		compatible = "ethernet-phy-id67c9.de0a";
-		reg = <6>;
-	};
-
-	switch: switch@1f {
-		compatible = "mediatek,mt7531";
-		reg = <31>;
-		reset-gpios = <&pio 5 0>;
-	};
-};
-
-&crypto {
-	status = "okay";
-};
-
-&mmc0 {
-	pinctrl-names = "default", "state_uhs";
-	pinctrl-0 = <&mmc0_pins_default>;
-	pinctrl-1 = <&mmc0_pins_uhs>;
-	bus-width = <8>;
-	max-frequency = <200000000>;
-	cap-mmc-highspeed;
-	mmc-hs200-1_8v;
-	mmc-hs400-1_8v;
-	hs400-ds-delay = <0x14014>;
-	vmmc-supply = <&reg_3p3v>;
-	vqmmc-supply = <&reg_1p8v>;
-	non-removable;
-	no-sd;
-	no-sdio;
-	status = "okay";
-};
-
-&pcie {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pcie_pins>;
-	status = "okay";
-};
-
-&pcie_phy {
-	status = "okay";
-};
-
-&pio {
-	mmc0_pins_default: mmc0-pins {
-		mux {
-			function = "emmc";
-			groups = "emmc_51";
-		};
-		conf-cmd-dat {
-			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
-			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
-			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
-			input-enable;
-			drive-strength = <4>;
-			mediatek,pull-up-adv = <1>;	/* pull-up 10K */
-		};
-		conf-clk {
-			pins = "EMMC_CK";
-			drive-strength = <6>;
-			mediatek,pull-down-adv = <2>;	/* pull-down 50K */
-		};
-		conf-ds {
-			pins = "EMMC_DSL";
-			mediatek,pull-down-adv = <2>;	/* pull-down 50K */
-		};
-		conf-rst {
-			pins = "EMMC_RSTB";
-			drive-strength = <4>;
-			mediatek,pull-up-adv = <1>;	/* pull-up 10K */
-		};
-	};
-
-	mmc0_pins_uhs: mmc0-uhs-pins {
-		mux {
-			function = "emmc";
-			groups = "emmc_51";
-		};
-		conf-cmd-dat {
-			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
-			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
-			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
-			input-enable;
-			drive-strength = <4>;
-			mediatek,pull-up-adv = <1>;	/* pull-up 10K */
-		};
-		conf-clk {
-			pins = "EMMC_CK";
-			drive-strength = <6>;
-			mediatek,pull-down-adv = <2>;	/* pull-down 50K */
-		};
-		conf-ds {
-			pins = "EMMC_DSL";
-			mediatek,pull-down-adv = <2>;	/* pull-down 50K */
-		};
-		conf-rst {
-			pins = "EMMC_RSTB";
-			drive-strength = <4>;
-			mediatek,pull-up-adv = <1>;	/* pull-up 10K */
-		};
-	};
-
-	pcie_pins: pcie-pins {
-		mux {
-			function = "pcie";
-			groups = "pcie_clk", "pcie_wake", "pcie_pereset";
-		};
-	};
-
-	spic_pins_g2: spic-pins-29-to-32 {
-		mux {
-			function = "spi";
-			groups = "spi1_2";
-		};
-	};
-
-	spi_flash_pins: spi-flash-pins-33-to-38 {
-		mux {
-			function = "spi";
-			groups = "spi0", "spi0_wp_hold";
-		};
-		conf-pu {
-			pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
-			drive-strength = <8>;
-			mediatek,pull-up-adv = <0>;	/* bias-disable */
-		};
-		conf-pd {
-			pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
-			drive-strength = <8>;
-			mediatek,pull-down-adv = <0>;	/* bias-disable */
-		};
-	};
-
-	uart1_pins: uart1-pins {
-		mux {
-			function = "uart";
-			groups = "uart1";
-		};
-	};
-
-	uart2_pins: uart2-pins {
-		mux {
-			function = "uart";
-			groups = "uart2";
-		};
-	};
-
-	wf_2g_5g_pins: wf_2g_5g-pins {
-		mux {
-			function = "wifi";
-			groups = "wf_2g", "wf_5g";
-		};
-		conf {
-			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
-			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
-			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
-			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
-			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
-			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
-			       "WF1_TOP_CLK", "WF1_TOP_DATA";
-			drive-strength = <4>;
-		};
-	};
-
-	wf_dbdc_pins: wf_dbdc-pins {
-		mux {
-			function = "wifi";
-			groups = "wf_dbdc";
-		};
-		conf {
-			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
-			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
-			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
-			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
-			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
-			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
-			       "WF1_TOP_CLK", "WF1_TOP_DATA";
-			drive-strength = <4>;
-		};
-	};
-};
-
-&spi0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&spi_flash_pins>;
-	cs-gpios = <0>, <0>;
-	#address-cells = <1>;
-	#size-cells = <0>;
-	status = "disabled";
-};
-
-&spi1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&spic_pins_g2>;
-	status = "okay";
-
-	proslic_spi: proslic_spi@0 {
-		compatible = "silabs,proslic_spi";
-		reg = <0>;
-		spi-max-frequency = <10000000>;
-		spi-cpha = <1>;
-		spi-cpol = <1>;
-		channel_count = <1>;
-		debug_level = <4>;       /* 1 = TRC, 2 = DBG, 4 = ERR */
-		reset_gpio = <&pio 7 0>;
-		ig,enable-spi = <1>;     /* 1: Enable, 0: Disable */
-	};
-};
-
-&gmac1 {
-	phy-mode = "2500base-x";
-	phy-connection-type = "2500base-x";
-	phy-handle = <&phy6>;
-};
-
-&switch {
-	ports {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		port@0 {
-			reg = <0>;
-			label = "lan1";
-		};
-
-		port@1 {
-			reg = <1>;
-			label = "lan2";
-		};
-
-		port@2 {
-			reg = <2>;
-			label = "lan3";
-		};
-
-		port@3 {
-			reg = <3>;
-			label = "lan4";
-		};
-
-		port@4 {
-			reg = <4>;
-			label = "wan";
-		};
-
-		port@5 {
-			reg = <5>;
-			label = "lan6";
-
-			phy-mode = "2500base-x";
-			phy-handle = <&phy5>;
-		};
-
-		port@6 {
-			reg = <6>;
-			ethernet = <&gmac0>;
-			phy-mode = "2500base-x";
-
-			fixed-link {
-				speed = <2500>;
-				full-duplex;
-				pause;
-			};
-		};
-	};
-};
-
-&ssusb {
-	vusb33-supply = <&reg_3p3v>;
-	vbus-supply = <&reg_5v>;
-	status = "okay";
-};
-
-&uart0 {
-	status = "okay";
-};
-
-&uart1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart1_pins>;
-	status = "okay";
-};
-
-&uart2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart2_pins>;
-	status = "okay";
-};
-
-&usb_phy {
-	status = "okay";
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
deleted file mode 100644
index 64f2cf3756a8b8..00000000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+++ /dev/null
@@ -1,645 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2021 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/clock/mt7986-clk.h>
-#include <dt-bindings/reset/mt7986-resets.h>
-#include <dt-bindings/phy/phy.h>
-
-/ {
-	compatible = "mediatek,mt7986a";
-	interrupt-parent = <&gic>;
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	clk40m: oscillator-40m {
-		compatible = "fixed-clock";
-		clock-frequency = <40000000>;
-		#clock-cells = <0>;
-		clock-output-names = "clkxtal";
-	};
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		cpu0: cpu@0 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a53";
-			enable-method = "psci";
-			reg = <0x0>;
-			#cooling-cells = <2>;
-		};
-
-		cpu1: cpu@1 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a53";
-			enable-method = "psci";
-			reg = <0x1>;
-			#cooling-cells = <2>;
-		};
-
-		cpu2: cpu@2 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a53";
-			enable-method = "psci";
-			reg = <0x2>;
-			#cooling-cells = <2>;
-		};
-
-		cpu3: cpu@3 {
-			device_type = "cpu";
-			enable-method = "psci";
-			compatible = "arm,cortex-a53";
-			reg = <0x3>;
-			#cooling-cells = <2>;
-		};
-	};
-
-	psci {
-		compatible = "arm,psci-0.2";
-		method = "smc";
-	};
-
-	reserved-memory {
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
-		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
-		secmon_reserved: secmon@43000000 {
-			reg = <0 0x43000000 0 0x30000>;
-			no-map;
-		};
-
-		wmcpu_emi: wmcpu-reserved@4fc00000 {
-			no-map;
-			reg = <0 0x4fc00000 0 0x00100000>;
-		};
-
-		wo_emi0: wo-emi@4fd00000 {
-			reg = <0 0x4fd00000 0 0x40000>;
-			no-map;
-		};
-
-		wo_emi1: wo-emi@4fd40000 {
-			reg = <0 0x4fd40000 0 0x40000>;
-			no-map;
-		};
-
-		wo_ilm0: wo-ilm@151e0000 {
-			reg = <0 0x151e0000 0 0x8000>;
-			no-map;
-		};
-
-		wo_ilm1: wo-ilm@151f0000 {
-			reg = <0 0x151f0000 0 0x8000>;
-			no-map;
-		};
-
-		wo_data: wo-data@4fd80000 {
-			reg = <0 0x4fd80000 0 0x240000>;
-			no-map;
-		};
-
-		wo_dlm0: wo-dlm@151e8000 {
-			reg = <0 0x151e8000 0 0x2000>;
-			no-map;
-		};
-
-		wo_dlm1: wo-dlm@151f8000 {
-			reg = <0 0x151f8000 0 0x2000>;
-			no-map;
-		};
-
-		wo_boot: wo-boot@15194000 {
-			reg = <0 0x15194000 0 0x1000>;
-			no-map;
-		};
-
-	};
-
-	timer {
-		compatible = "arm,armv8-timer";
-		interrupt-parent = <&gic>;
-		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
-	};
-
-	soc {
-		#address-cells = <2>;
-		#size-cells = <2>;
-		compatible = "simple-bus";
-		ranges;
-
-		gic: interrupt-controller@c000000 {
-			compatible = "arm,gic-v3";
-			#interrupt-cells = <3>;
-			interrupt-parent = <&gic>;
-			interrupt-controller;
-			reg = <0 0x0c000000 0 0x10000>,  /* GICD */
-			      <0 0x0c080000 0 0x80000>,  /* GICR */
-			      <0 0x0c400000 0 0x2000>,   /* GICC */
-			      <0 0x0c410000 0 0x1000>,   /* GICH */
-			      <0 0x0c420000 0 0x2000>;   /* GICV */
-			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
-		};
-
-		infracfg: infracfg@10001000 {
-			compatible = "mediatek,mt7986-infracfg", "syscon";
-			reg = <0 0x10001000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		wed_pcie: wed-pcie@10003000 {
-			compatible = "mediatek,mt7986-wed-pcie",
-				     "syscon";
-			reg = <0 0x10003000 0 0x10>;
-		};
-
-		topckgen: topckgen@1001b000 {
-			compatible = "mediatek,mt7986-topckgen", "syscon";
-			reg = <0 0x1001B000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		watchdog: watchdog@1001c000 {
-			compatible = "mediatek,mt7986-wdt";
-			reg = <0 0x1001c000 0 0x1000>;
-			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
-			#reset-cells = <1>;
-			status = "disabled";
-		};
-
-		apmixedsys: apmixedsys@1001e000 {
-			compatible = "mediatek,mt7986-apmixedsys";
-			reg = <0 0x1001E000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		pio: pinctrl@1001f000 {
-			compatible = "mediatek,mt7986a-pinctrl";
-			reg = <0 0x1001f000 0 0x1000>,
-			      <0 0x11c30000 0 0x1000>,
-			      <0 0x11c40000 0 0x1000>,
-			      <0 0x11e20000 0 0x1000>,
-			      <0 0x11e30000 0 0x1000>,
-			      <0 0x11f00000 0 0x1000>,
-			      <0 0x11f10000 0 0x1000>,
-			      <0 0x1000b000 0 0x1000>;
-			reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt",
-				    "iocfg_lb", "iocfg_tr", "iocfg_tl", "eint";
-			gpio-controller;
-			#gpio-cells = <2>;
-			gpio-ranges = <&pio 0 0 100>;
-			interrupt-controller;
-			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-parent = <&gic>;
-			#interrupt-cells = <2>;
-		};
-
-		sgmiisys0: syscon@10060000 {
-			compatible = "mediatek,mt7986-sgmiisys_0",
-				     "syscon";
-			reg = <0 0x10060000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		sgmiisys1: syscon@10070000 {
-			compatible = "mediatek,mt7986-sgmiisys_1",
-				     "syscon";
-			reg = <0 0x10070000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		trng: rng@1020f000 {
-			compatible = "mediatek,mt7986-rng",
-				     "mediatek,mt7623-rng";
-			reg = <0 0x1020f000 0 0x100>;
-			clocks = <&infracfg CLK_INFRA_TRNG_CK>;
-			clock-names = "rng";
-			status = "disabled";
-		};
-
-		crypto: crypto@10320000 {
-			compatible = "inside-secure,safexcel-eip97";
-			reg = <0 0x10320000 0 0x40000>;
-			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "ring0", "ring1", "ring2", "ring3";
-			clocks = <&infracfg CLK_INFRA_EIP97_CK>;
-			clock-names = "infra_eip97_ck";
-			assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>;
-			assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>;
-			status = "disabled";
-		};
-
-		pwm: pwm@10048000 {
-			compatible = "mediatek,mt7986-pwm";
-			reg = <0 0x10048000 0 0x1000>;
-			#clock-cells = <1>;
-			#pwm-cells = <2>;
-			interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&topckgen CLK_TOP_PWM_SEL>,
-				 <&infracfg CLK_INFRA_PWM_STA>,
-				 <&infracfg CLK_INFRA_PWM1_CK>,
-				 <&infracfg CLK_INFRA_PWM2_CK>;
-			clock-names = "top", "main", "pwm1", "pwm2";
-			status = "disabled";
-		};
-
-		uart0: serial@11002000 {
-			compatible = "mediatek,mt7986-uart",
-				     "mediatek,mt6577-uart";
-			reg = <0 0x11002000 0 0x400>;
-			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&infracfg CLK_INFRA_UART0_SEL>,
-				 <&infracfg CLK_INFRA_UART0_CK>;
-			clock-names = "baud", "bus";
-			assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
-					  <&infracfg CLK_INFRA_UART0_SEL>;
-			assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
-						 <&topckgen CLK_TOP_UART_SEL>;
-			status = "disabled";
-		};
-
-		uart1: serial@11003000 {
-			compatible = "mediatek,mt7986-uart",
-				     "mediatek,mt6577-uart";
-			reg = <0 0x11003000 0 0x400>;
-			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&infracfg CLK_INFRA_UART1_SEL>,
-				 <&infracfg CLK_INFRA_UART1_CK>;
-			clock-names = "baud", "bus";
-			assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>;
-			assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
-			status = "disabled";
-		};
-
-		uart2: serial@11004000 {
-			compatible = "mediatek,mt7986-uart",
-				     "mediatek,mt6577-uart";
-			reg = <0 0x11004000 0 0x400>;
-			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&infracfg CLK_INFRA_UART2_SEL>,
-				 <&infracfg CLK_INFRA_UART2_CK>;
-			clock-names = "baud", "bus";
-			assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>;
-			assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
-			status = "disabled";
-		};
-
-		i2c0: i2c@11008000 {
-			compatible = "mediatek,mt7986-i2c";
-			reg = <0 0x11008000 0 0x90>,
-			      <0 0x10217080 0 0x80>;
-			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
-			clock-div = <5>;
-			clocks = <&infracfg CLK_INFRA_I2C0_CK>,
-				 <&infracfg CLK_INFRA_AP_DMA_CK>;
-			clock-names = "main", "dma";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-		};
-
-		spi0: spi@1100a000 {
-			compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0 0x1100a000 0 0x100>;
-			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&topckgen CLK_TOP_MPLL_D2>,
-				 <&topckgen CLK_TOP_SPI_SEL>,
-				 <&infracfg CLK_INFRA_SPI0_CK>,
-				 <&infracfg CLK_INFRA_SPI0_HCK_CK>;
-			clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
-			status = "disabled";
-		};
-
-		spi1: spi@1100b000 {
-			compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0 0x1100b000 0 0x100>;
-			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&topckgen CLK_TOP_MPLL_D2>,
-				 <&topckgen CLK_TOP_SPIM_MST_SEL>,
-				 <&infracfg CLK_INFRA_SPI1_CK>,
-				 <&infracfg CLK_INFRA_SPI1_HCK_CK>;
-			clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
-			status = "disabled";
-		};
-
-		auxadc: adc@1100d000 {
-			compatible = "mediatek,mt7986-auxadc";
-			reg = <0 0x1100d000 0 0x1000>;
-			clocks = <&infracfg CLK_INFRA_ADC_26M_CK>;
-			clock-names = "main";
-			#io-channel-cells = <1>;
-			status = "disabled";
-		};
-
-		ssusb: usb@11200000 {
-			compatible = "mediatek,mt7986-xhci",
-				     "mediatek,mtk-xhci";
-			reg = <0 0x11200000 0 0x2e00>,
-			      <0 0x11203e00 0 0x0100>;
-			reg-names = "mac", "ippc";
-			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
-				 <&infracfg CLK_INFRA_IUSB_CK>,
-				 <&infracfg CLK_INFRA_IUSB_133_CK>,
-				 <&infracfg CLK_INFRA_IUSB_66M_CK>,
-				 <&topckgen CLK_TOP_U2U3_XHCI_SEL>;
-			clock-names = "sys_ck",
-				      "ref_ck",
-				      "mcu_ck",
-				      "dma_ck",
-				      "xhci_ck";
-			phys = <&u2port0 PHY_TYPE_USB2>,
-			       <&u3port0 PHY_TYPE_USB3>,
-			       <&u2port1 PHY_TYPE_USB2>;
-			status = "disabled";
-		};
-
-		mmc0: mmc@11230000 {
-			compatible = "mediatek,mt7986-mmc";
-			reg = <0 0x11230000 0 0x1000>,
-			      <0 0x11c20000 0 0x1000>;
-			interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
-				 <&infracfg CLK_INFRA_MSDC_HCK_CK>,
-				 <&infracfg CLK_INFRA_MSDC_CK>,
-				 <&infracfg CLK_INFRA_MSDC_133M_CK>,
-				 <&infracfg CLK_INFRA_MSDC_66M_CK>;
-			clock-names = "source", "hclk", "source_cg", "bus_clk",
-				      "sys_cg";
-			status = "disabled";
-		};
-
-		thermal: thermal@1100c800 {
-			#thermal-sensor-cells = <1>;
-			compatible = "mediatek,mt7986-thermal";
-			reg = <0 0x1100c800 0 0x800>;
-			interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&infracfg CLK_INFRA_THERM_CK>,
-				 <&infracfg CLK_INFRA_ADC_26M_CK>,
-				 <&infracfg CLK_INFRA_ADC_FRC_CK>;
-			clock-names = "therm", "auxadc", "adc_32k";
-			mediatek,auxadc = <&auxadc>;
-			mediatek,apmixedsys = <&apmixedsys>;
-			nvmem-cells = <&thermal_calibration>;
-			nvmem-cell-names = "calibration-data";
-		};
-
-		pcie: pcie@11280000 {
-			compatible = "mediatek,mt7986-pcie",
-				     "mediatek,mt8192-pcie";
-			device_type = "pci";
-			#address-cells = <3>;
-			#size-cells = <2>;
-			reg = <0x00 0x11280000 0x00 0x4000>;
-			reg-names = "pcie-mac";
-			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
-			bus-range = <0x00 0xff>;
-			ranges = <0x82000000 0x00 0x20000000 0x00
-				  0x20000000 0x00 0x10000000>;
-			clocks = <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
-				 <&infracfg CLK_INFRA_IPCIE_CK>,
-				 <&infracfg CLK_INFRA_IPCIER_CK>,
-				 <&infracfg CLK_INFRA_IPCIEB_CK>;
-			clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m";
-			status = "disabled";
-
-			phys = <&pcie_port PHY_TYPE_PCIE>;
-			phy-names = "pcie-phy";
-
-			#interrupt-cells = <1>;
-			interrupt-map-mask = <0 0 0 0x7>;
-			interrupt-map = <0 0 0 1 &pcie_intc 0>,
-					<0 0 0 2 &pcie_intc 1>,
-					<0 0 0 3 &pcie_intc 2>,
-					<0 0 0 4 &pcie_intc 3>;
-			pcie_intc: interrupt-controller {
-				#address-cells = <0>;
-				#interrupt-cells = <1>;
-				interrupt-controller;
-			};
-		};
-
-		pcie_phy: t-phy@11c00000 {
-			compatible = "mediatek,mt7986-tphy",
-				     "mediatek,generic-tphy-v2";
-			#address-cells = <2>;
-			#size-cells = <2>;
-			ranges;
-			status = "disabled";
-
-			pcie_port: pcie-phy@11c00000 {
-				reg = <0 0x11c00000 0 0x20000>;
-				clocks = <&clk40m>;
-				clock-names = "ref";
-				#phy-cells = <1>;
-			};
-		};
-
-		efuse: efuse@11d00000 {
-			compatible = "mediatek,mt7986-efuse", "mediatek,efuse";
-			reg = <0 0x11d00000 0 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			thermal_calibration: calib@274 {
-				reg = <0x274 0xc>;
-			};
-		};
-
-		usb_phy: t-phy@11e10000 {
-			compatible = "mediatek,mt7986-tphy",
-				     "mediatek,generic-tphy-v2";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0 0 0x11e10000 0x1700>;
-			status = "disabled";
-
-			u2port0: usb-phy@0 {
-				reg = <0x0 0x700>;
-				clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
-					 <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
-				clock-names = "ref", "da_ref";
-				#phy-cells = <1>;
-			};
-
-			u3port0: usb-phy@700 {
-				reg = <0x700 0x900>;
-				clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
-				clock-names = "ref";
-				#phy-cells = <1>;
-			};
-
-			u2port1: usb-phy@1000 {
-				reg = <0x1000 0x700>;
-				clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
-					 <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
-				clock-names = "ref", "da_ref";
-				#phy-cells = <1>;
-			};
-		};
-
-		ethsys: syscon@15000000 {
-			 #address-cells = <1>;
-			 #size-cells = <1>;
-			 compatible = "mediatek,mt7986-ethsys",
-				      "syscon";
-			 reg = <0 0x15000000 0 0x1000>;
-			 #clock-cells = <1>;
-			 #reset-cells = <1>;
-		};
-
-		wed0: wed@15010000 {
-			compatible = "mediatek,mt7986-wed",
-				     "syscon";
-			reg = <0 0x15010000 0 0x1000>;
-			interrupt-parent = <&gic>;
-			interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
-			memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>,
-					<&wo_data>, <&wo_boot>;
-			memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
-					      "wo-data", "wo-boot";
-			mediatek,wo-ccif = <&wo_ccif0>;
-		};
-
-		wed1: wed@15011000 {
-			compatible = "mediatek,mt7986-wed",
-				     "syscon";
-			reg = <0 0x15011000 0 0x1000>;
-			interrupt-parent = <&gic>;
-			interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
-			memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>,
-					<&wo_data>, <&wo_boot>;
-			memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
-					      "wo-data", "wo-boot";
-			mediatek,wo-ccif = <&wo_ccif1>;
-		};
-
-		wo_ccif0: syscon@151a5000 {
-			compatible = "mediatek,mt7986-wo-ccif", "syscon";
-			reg = <0 0x151a5000 0 0x1000>;
-			interrupt-parent = <&gic>;
-			interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
-		};
-
-		wo_ccif1: syscon@151ad000 {
-			compatible = "mediatek,mt7986-wo-ccif", "syscon";
-			reg = <0 0x151ad000 0 0x1000>;
-			interrupt-parent = <&gic>;
-			interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
-		};
-
-		eth: ethernet@15100000 {
-			compatible = "mediatek,mt7986-eth";
-			reg = <0 0x15100000 0 0x80000>;
-			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ethsys CLK_ETH_FE_EN>,
-				 <&ethsys CLK_ETH_GP2_EN>,
-				 <&ethsys CLK_ETH_GP1_EN>,
-				 <&ethsys CLK_ETH_WOCPU1_EN>,
-				 <&ethsys CLK_ETH_WOCPU0_EN>,
-				 <&sgmiisys0 CLK_SGMII0_TX250M_EN>,
-				 <&sgmiisys0 CLK_SGMII0_RX250M_EN>,
-				 <&sgmiisys0 CLK_SGMII0_CDR_REF>,
-				 <&sgmiisys0 CLK_SGMII0_CDR_FB>,
-				 <&sgmiisys1 CLK_SGMII1_TX250M_EN>,
-				 <&sgmiisys1 CLK_SGMII1_RX250M_EN>,
-				 <&sgmiisys1 CLK_SGMII1_CDR_REF>,
-				 <&sgmiisys1 CLK_SGMII1_CDR_FB>,
-				 <&topckgen CLK_TOP_NETSYS_SEL>,
-				 <&topckgen CLK_TOP_NETSYS_500M_SEL>;
-			clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
-				      "sgmii_tx250m", "sgmii_rx250m",
-				      "sgmii_cdr_ref", "sgmii_cdr_fb",
-				      "sgmii2_tx250m", "sgmii2_rx250m",
-				      "sgmii2_cdr_ref", "sgmii2_cdr_fb",
-				      "netsys0", "netsys1";
-			assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
-					  <&topckgen CLK_TOP_SGM_325M_SEL>;
-			assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
-						 <&apmixedsys CLK_APMIXED_SGMPLL>;
-			mediatek,ethsys = <&ethsys>;
-			mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
-			mediatek,wed-pcie = <&wed_pcie>;
-			mediatek,wed = <&wed0>, <&wed1>;
-			#reset-cells = <1>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-		};
-
-		wifi: wifi@18000000 {
-			compatible = "mediatek,mt7986-wmac";
-			resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
-			reset-names = "consys";
-			clocks = <&topckgen CLK_TOP_CONN_MCUSYS_SEL>,
-				 <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
-			clock-names = "mcu", "ap2conn";
-			reg = <0 0x18000000 0 0x1000000>,
-			      <0 0x10003000 0 0x1000>,
-			      <0 0x11d10000 0 0x1000>;
-			interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
-			memory-region = <&wmcpu_emi>;
-		};
-	};
-
-	thermal-zones {
-		cpu_thermal: cpu-thermal {
-			polling-delay-passive = <1000>;
-			polling-delay = <1000>;
-			thermal-sensors = <&thermal 0>;
-
-			trips {
-				cpu_trip_crit: crit {
-					temperature = <125000>;
-					hysteresis = <2000>;
-					type = "critical";
-				};
-
-				cpu_trip_hot: hot {
-					temperature = <120000>;
-					hysteresis = <2000>;
-					type = "hot";
-				};
-
-				cpu_trip_active_high: active-high {
-					temperature = <115000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-
-				cpu_trip_active_med: active-med {
-					temperature = <85000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-
-				cpu_trip_active_low: active-low {
-					temperature = <60000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-			};
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
deleted file mode 100644
index 8cd094f7c3eeb1..00000000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
+++ /dev/null
@@ -1,194 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2021 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-#include "mt7986b.dtsi"
-
-/ {
-	model = "MediaTek MT7986b RFB";
-	compatible = "mediatek,mt7986b-rfb";
-
-	aliases {
-		serial0 = &uart0;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	memory {
-		reg = <0 0x40000000 0 0x40000000>;
-	};
-
-	reg_3p3v: regulator-3p3v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-3.3V";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	reg_5v: regulator-5v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-5V";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-};
-
-&ssusb {
-	vusb33-supply = <&reg_3p3v>;
-	vbus-supply = <&reg_5v>;
-	status = "okay";
-};
-
-&uart0 {
-	status = "okay";
-};
-
-&usb_phy {
-	status = "okay";
-};
-
-&wifi {
-	status = "okay";
-	pinctrl-names = "default", "dbdc";
-	pinctrl-0 = <&wf_2g_5g_pins>;
-	pinctrl-1 = <&wf_dbdc_pins>;
-};
-
-&eth {
-	status = "okay";
-
-	gmac0: mac@0 {
-		compatible = "mediatek,eth-mac";
-		reg = <0>;
-		phy-mode = "2500base-x";
-
-		fixed-link {
-			speed = <2500>;
-			full-duplex;
-			pause;
-		};
-	};
-
-	gmac1: mac@1 {
-		compatible = "mediatek,eth-mac";
-		reg = <1>;
-		phy-mode = "2500base-x";
-
-		fixed-link {
-			speed = <2500>;
-			full-duplex;
-			pause;
-		};
-	};
-
-	mdio: mdio-bus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		phy5: phy@5 {
-			compatible = "ethernet-phy-id67c9.de0a";
-			reg = <5>;
-			reset-gpios = <&pio 6 1>;
-			reset-deassert-us = <20000>;
-			phy-mode = "2500base-x";
-		};
-
-		phy6: phy@6 {
-			compatible = "ethernet-phy-id67c9.de0a";
-			reg = <6>;
-			phy-mode = "2500base-x";
-		};
-
-		switch@1f {
-			compatible = "mediatek,mt7531";
-			reg = <31>;
-			reset-gpios = <&pio 5 0>;
-
-			ports {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				port@0 {
-					reg = <0>;
-					label = "lan0";
-				};
-
-				port@1 {
-					reg = <1>;
-					label = "lan1";
-				};
-
-				port@2 {
-					reg = <2>;
-					label = "lan2";
-				};
-
-				port@3 {
-					reg = <3>;
-					label = "lan3";
-				};
-
-				port@6 {
-					reg = <6>;
-					ethernet = <&gmac0>;
-					phy-mode = "2500base-x";
-
-					fixed-link {
-						speed = <2500>;
-						full-duplex;
-						pause;
-					};
-				};
-			};
-		};
-	};
-};
-
-&crypto {
-	status = "okay";
-};
-
-&pio {
-	wf_2g_5g_pins: wf_2g_5g-pins {
-		mux {
-			function = "wifi";
-			groups = "wf_2g", "wf_5g";
-		};
-		conf {
-			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
-			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
-			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
-			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
-			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
-			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
-			       "WF1_TOP_CLK", "WF1_TOP_DATA";
-			drive-strength = <4>;
-		};
-	};
-
-	wf_dbdc_pins: wf_dbdc-pins {
-		mux {
-			function = "wifi";
-			groups = "wf_dbdc";
-		};
-		conf {
-			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
-			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
-			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
-			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
-			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
-			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
-			       "WF1_TOP_CLK", "WF1_TOP_DATA";
-			drive-strength = <4>;
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986b.dtsi b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986b.dtsi
deleted file mode 100644
index db5189664c29ba..00000000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986b.dtsi
+++ /dev/null
@@ -1,15 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2021 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-#include "mt7986a.dtsi"
-/ {
-	compatible = "mediatek,mt7986b";
-};
-
-&pio {
-	compatible = "mediatek,mt7986b-pinctrl";
-	gpio-ranges = <&pio 0 0 41>, <&pio 66 66 35>;
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-emmc.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-emmc.dtso
deleted file mode 100644
index 3f8ac2ae382ba0..00000000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-emmc.dtso
+++ /dev/null
@@ -1,33 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2021 MediaTek Inc.
- * Author: Frank Wunderlich <frank-w@public-files.de>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&mmc0>;
-		__overlay__ {
-			pinctrl-names = "default", "state_uhs";
-			pinctrl-0 = <&mmc0_pins_emmc_51>;
-			pinctrl-1 = <&mmc0_pins_emmc_51>;
-			bus-width = <8>;
-			max-frequency = <200000000>;
-			cap-mmc-highspeed;
-			mmc-hs200-1_8v;
-			mmc-hs400-1_8v;
-			hs400-ds-delay = <0x12814>;
-			vqmmc-supply = <&reg_1p8v>;
-			vmmc-supply = <&reg_3p3v>;
-			non-removable;
-			no-sd;
-			no-sdio;
-			status = "okay";
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-aqr.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-aqr.dtso
deleted file mode 100644
index d21a61ad19fef3..00000000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-aqr.dtso
+++ /dev/null
@@ -1,41 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&mdio_bus>;
-		__overlay__ {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			/* external Aquantia AQR113C */
-			phy0: ethernet-phy@0 {
-				reg = <0>;
-				compatible = "ethernet-phy-ieee802.3-c45";
-				reset-gpios = <&pio 72 GPIO_ACTIVE_LOW>;
-				reset-assert-us = <100000>;
-				reset-deassert-us = <221000>;
-			};
-		};
-	};
-
-	fragment@1 {
-		target = <&gmac1>;
-		__overlay__ {
-			phy-mode = "usxgmii";
-			phy-connection-type = "usxgmii";
-			phy = <&phy0>;
-			status = "okay";
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-i2p5g-phy.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-i2p5g-phy.dtso
deleted file mode 100644
index 86ab7566dc298e..00000000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-i2p5g-phy.dtso
+++ /dev/null
@@ -1,30 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&gmac1>;
-		__overlay__ {
-			phy-mode = "internal";
-			phy-connection-type = "internal";
-			phy = <&int_2p5g_phy>;
-			status = "okay";
-		};
-	};
-
-	fragment@1 {
-		target = <&int_2p5g_phy>;
-		__overlay__ {
-			pinctrl-names = "i2p5gbe-led";
-			pinctrl-0 = <&i2p5gbe_led0_pins>;
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-mxl.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-mxl.dtso
deleted file mode 100644
index 34a23bbd7eb09e..00000000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-mxl.dtso
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&mdio_bus>;
-		__overlay__ {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			/* external Maxlinear GPY211C */
-			phy13: ethernet-phy@13 {
-				reg = <13>;
-				compatible = "ethernet-phy-ieee802.3-c45";
-				phy-mode = "2500base-x";
-			};
-		};
-	};
-
-	fragment@1 {
-		target = <&gmac1>;
-		__overlay__ {
-			phy-mode = "2500base-x";
-			phy-connection-type = "2500base-x";
-			phy = <&phy13>;
-			status = "okay";
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-sfp.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-sfp.dtso
deleted file mode 100644
index ba40a119cbdfdc..00000000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-sfp.dtso
+++ /dev/null
@@ -1,47 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&i2c2>;
-		__overlay__ {
-			pinctrl-names = "default";
-			pinctrl-0 = <&i2c2_0_pins>;
-			status = "okay";
-		};
-	};
-
-	fragment@1 {
-		target-path = "/";
-		__overlay__ {
-			sfp_esp1: sfp@1 {
-				compatible = "sff,sfp";
-				i2c-bus = <&i2c2>;
-				mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>;
-				los-gpios = <&pio 81 GPIO_ACTIVE_HIGH>;
-				tx-disable-gpios = <&pio 36 GPIO_ACTIVE_HIGH>;
-				maximum-power-milliwatt = <3000>;
-			};
-		};
-	};
-
-	fragment@2 {
-		target = <&gmac1>;
-		__overlay__ {
-			phy-mode = "10gbase-r";
-			managed = "in-band-status";
-			sfp = <&sfp_esp1>;
-			status = "okay";
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-aqr.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-aqr.dtso
deleted file mode 100644
index 140391fc45a8f4..00000000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-aqr.dtso
+++ /dev/null
@@ -1,41 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&mdio_bus>;
-		__overlay__ {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			/* external Aquantia AQR113C */
-			phy8: ethernet-phy@8 {
-				reg = <8>;
-				compatible = "ethernet-phy-ieee802.3-c45";
-				reset-gpios = <&pio 71 GPIO_ACTIVE_LOW>;
-				reset-assert-us = <100000>;
-				reset-deassert-us = <221000>;
-			};
-		};
-	};
-
-	fragment@1 {
-		target = <&gmac2>;
-		__overlay__ {
-			phy-mode = "usxgmii";
-			phy-connection-type = "usxgmii";
-			phy = <&phy8>;
-			status = "okay";
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-mxl.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-mxl.dtso
deleted file mode 100644
index 19e0b2799fc848..00000000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-mxl.dtso
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&mdio_bus>;
-		__overlay__ {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			/* external Maxlinear GPY211C */
-			phy5: ethernet-phy@5 {
-				reg = <5>;
-				compatible = "ethernet-phy-ieee802.3-c45";
-				phy-mode = "2500base-x";
-			};
-		};
-	};
-
-	fragment@1 {
-		target = <&gmac2>;
-		__overlay__ {
-			phy-mode = "2500base-x";
-			phy-connection-type = "2500base-x";
-			phy = <&phy5>;
-			status = "okay";
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-sfp.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-sfp.dtso
deleted file mode 100644
index b9aabd2726e2a2..00000000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-sfp.dtso
+++ /dev/null
@@ -1,47 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&i2c1>;
-		__overlay__ {
-			pinctrl-names = "default";
-			pinctrl-0 = <&i2c1_sfp_pins>;
-			status = "okay";
-		};
-	};
-
-	fragment@1 {
-		target-path = "/";
-		__overlay__ {
-			sfp_esp0: sfp@0 {
-				compatible = "sff,sfp";
-				i2c-bus = <&i2c1>;
-				mod-def0-gpios = <&pio 35 GPIO_ACTIVE_LOW>;
-				los-gpios = <&pio 33 GPIO_ACTIVE_HIGH>;
-				tx-disable-gpios = <&pio 29 GPIO_ACTIVE_HIGH>;
-				maximum-power-milliwatt = <3000>;
-			};
-		};
-	};
-
-	fragment@2 {
-		target = <&gmac2>;
-		__overlay__ {
-			phy-mode = "10gbase-r";
-			managed = "in-band-status";
-			sfp = <&sfp_esp0>;
-			status = "okay";
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-sd.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-sd.dtso
deleted file mode 100644
index 04472cc12dc816..00000000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-sd.dtso
+++ /dev/null
@@ -1,31 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2023 MediaTek Inc.
- * Author: Frank Wunderlich <frank-w@public-files.de>
- */
-
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@1 {
-		target-path = <&mmc0>;
-		__overlay__ {
-			pinctrl-names = "default", "state_uhs";
-			pinctrl-0 = <&mmc0_pins_sdcard>;
-			pinctrl-1 = <&mmc0_pins_sdcard>;
-			cd-gpios = <&pio 69 GPIO_ACTIVE_LOW>;
-			bus-width = <4>;
-			max-frequency = <52000000>;
-			cap-sd-highspeed;
-			vmmc-supply = <&reg_3p3v>;
-			vqmmc-supply = <&reg_3p3v>;
-			no-mmc;
-			status = "okay";
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-snfi-nand.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-snfi-nand.dtso
deleted file mode 100644
index 86b0042f647768..00000000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-snfi-nand.dtso
+++ /dev/null
@@ -1,69 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&snand>;
-		__overlay__ {
-			status = "okay";
-
-			flash@0 {
-				compatible = "spi-nand";
-				reg = <0>;
-				spi-max-frequency = <52000000>;
-				spi-tx-bus-width = <4>;
-				spi-rx-bus-width = <4>;
-				mediatek,nmbm;
-				mediatek,bmt-max-ratio = <1>;
-				mediatek,bmt-max-reserved-blocks = <64>;
-
-				partitions {
-					compatible = "fixed-partitions";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					partition@0 {
-						label = "BL2";
-						reg = <0x00000 0x0100000>;
-						read-only;
-					};
-
-					partition@100000 {
-						label = "u-boot-env";
-						reg = <0x0100000 0x0080000>;
-					};
-
-					partition@180000 {
-						label = "Factory";
-						reg = <0x180000 0x0400000>;
-					};
-
-					partition@580000 {
-						label = "FIP";
-						reg = <0x580000 0x0200000>;
-					};
-
-					partition@780000 {
-						label = "ubi";
-						reg = <0x780000 0x7080000>;
-					};
-				};
-			};
-		};
-	};
-
-	fragment@1 {
-		target = <&bch>;
-		__overlay__ {
-			status = "okay";
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtso
deleted file mode 100644
index a9eca00d4416cb..00000000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtso
+++ /dev/null
@@ -1,64 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&spi0>;
-		__overlay__ {
-			pinctrl-names = "default";
-			pinctrl-0 = <&spi0_flash_pins>;
-			status = "okay";
-
-			flash@0 {
-				compatible = "spi-nand";
-				reg = <0>;
-				spi-max-frequency = <52000000>;
-				spi-tx-bus-width = <4>;
-				spi-rx-bus-width = <4>;
-				mediatek,nmbm;
-				mediatek,bmt-max-ratio = <1>;
-				mediatek,bmt-max-reserved-blocks = <64>;
-
-				partitions {
-					compatible = "fixed-partitions";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					partition@0 {
-						label = "BL2";
-						reg = <0x00000 0x0100000>;
-						read-only;
-					};
-
-					partition@100000 {
-						label = "u-boot-env";
-						reg = <0x0100000 0x0080000>;
-					};
-
-					partition@180000 {
-						label = "Factory";
-						reg = <0x180000 0x0400000>;
-					};
-
-					partition@580000 {
-						label = "FIP";
-						reg = <0x580000 0x0200000>;
-					};
-
-					partition@780000 {
-						label = "ubi";
-						reg = <0x780000 0x7080000>;
-					};
-				};
-			};
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nor.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nor.dtso
deleted file mode 100644
index 33bd57b3fb63b3..00000000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nor.dtso
+++ /dev/null
@@ -1,59 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&spi2>;
-		__overlay__ {
-			pinctrl-names = "default";
-			pinctrl-0 = <&spi2_flash_pins>;
-			status = "okay";
-
-			flash@0 {
-				#address-cells = <1>;
-				#size-cells = <1>;
-				compatible = "jedec,spi-nor";
-				spi-cal-enable;
-				spi-cal-mode = "read-data";
-				spi-cal-datalen = <7>;
-				spi-cal-data = /bits/ 8 <
-					0x53 0x46 0x5F 0x42 0x4F 0x4F 0x54>; /* SF_BOOT */
-				spi-cal-addrlen = <1>;
-				spi-cal-addr = /bits/ 32 <0x0>;
-				reg = <0>;
-				spi-max-frequency = <52000000>;
-				spi-tx-bus-width = <4>;
-				spi-rx-bus-width = <4>;
-
-				partition@00000 {
-					label = "BL2";
-					reg = <0x00000 0x0040000>;
-				};
-				partition@40000 {
-					label = "u-boot-env";
-					reg = <0x40000 0x0010000>;
-				};
-				partition@50000 {
-					label = "Factory";
-					reg = <0x50000 0x0200000>;
-				};
-				partition@250000 {
-					label = "FIP";
-					reg = <0x250000 0x0080000>;
-				};
-				partition@2D0000 {
-					label = "firmware";
-					reg = <0x2D0000 0x1D30000>;
-				};
-			};
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dts b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dts
deleted file mode 100644
index 11dbf98301eb48..00000000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dts
+++ /dev/null
@@ -1,200 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-#include "mt7988a.dtsi"
-#include <dt-bindings/pinctrl/mt65xx.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/regulator/richtek,rt5190a-regulator.h>
-
-/ {
-	model = "MediaTek MT7988A Reference Board";
-	compatible = "mediatek,mt7988a-rfb",
-		     "mediatek,mt7988";
-
-	chosen {
-		bootargs = "console=ttyS0,115200n1 loglevel=8  \
-			    earlycon=uart8250,mmio32,0x11000000 \
-			    pci=pcie_bus_perf";
-	};
-
-	memory {
-		reg = <0 0x40000000 0 0x40000000>;
-	};
-};
-
-&eth {
-	pinctrl-0 = <&mdio0_pins>;
-	pinctrl-names = "default";
-};
-
-&gmac0 {
-	status = "okay";
-};
-
-&cpu0 {
-	proc-supply = <&rt5190_buck3>;
-};
-
-&cpu1 {
-	proc-supply = <&rt5190_buck3>;
-};
-
-&cpu2 {
-	proc-supply = <&rt5190_buck3>;
-};
-
-&cpu3 {
-	proc-supply = <&rt5190_buck3>;
-};
-
-&cci {
-	proc-supply = <&rt5190_buck3>;
-};
-
-&eth {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&gsw_phy0 {
-	pinctrl-names = "gbe-led";
-	pinctrl-0 = <&gbe0_led0_pins>;
-};
-
-&gsw_phy0_led0 {
-	status = "okay";
-	color = <LED_COLOR_ID_GREEN>;
-};
-
-&gsw_phy1 {
-	pinctrl-names = "gbe-led";
-	pinctrl-0 = <&gbe1_led0_pins>;
-};
-
-&gsw_phy1_led0 {
-	status = "okay";
-	color = <LED_COLOR_ID_GREEN>;
-};
-
-&gsw_phy2 {
-	pinctrl-names = "gbe-led";
-	pinctrl-0 = <&gbe2_led0_pins>;
-};
-
-&gsw_phy2_led0 {
-	status = "okay";
-	color = <LED_COLOR_ID_GREEN>;
-};
-
-&gsw_phy3 {
-	pinctrl-names = "gbe-led";
-	pinctrl-0 = <&gbe3_led0_pins>;
-};
-
-&gsw_phy3_led0 {
-	status = "okay";
-	color = <LED_COLOR_ID_GREEN>;
-};
-
-&i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c0_pins>;
-	status = "okay";
-
-	rt5190a_64: rt5190a@64 {
-		compatible = "richtek,rt5190a";
-		reg = <0x64>;
-		/*interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;*/
-		vin2-supply = <&rt5190_buck1>;
-		vin3-supply = <&rt5190_buck1>;
-		vin4-supply = <&rt5190_buck1>;
-
-		regulators {
-			rt5190_buck1: buck1 {
-				regulator-name = "rt5190a-buck1";
-				regulator-min-microvolt = <5090000>;
-				regulator-max-microvolt = <5090000>;
-				regulator-allowed-modes =
-				<RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-			buck2 {
-				regulator-name = "vcore";
-				regulator-min-microvolt = <600000>;
-				regulator-max-microvolt = <1400000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-			rt5190_buck3: buck3 {
-				regulator-name = "vproc";
-				regulator-min-microvolt = <600000>;
-				regulator-max-microvolt = <1400000>;
-				regulator-boot-on;
-			};
-			buck4 {
-				regulator-name = "rt5190a-buck4";
-				regulator-min-microvolt = <850000>;
-				regulator-max-microvolt = <850000>;
-				regulator-allowed-modes =
-				<RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-			ldo {
-				regulator-name = "rt5190a-ldo";
-				regulator-min-microvolt = <1200000>;
-				regulator-max-microvolt = <1200000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-		};
-	};
-};
-
-&pcie0 {
-	status = "okay";
-};
-
-&pcie1 {
-	status = "okay";
-};
-
-&pcie2 {
-	status = "disabled";
-};
-
-&pcie3 {
-	status = "okay";
-};
-
-&ssusb0 {
-	status = "okay";
-};
-
-&ssusb1 {
-	status = "okay";
-};
-
-&tphy {
-	status = "okay";
-};
-
-&uart0 {
-	status = "okay";
-};
-
-&watchdog {
-	status = "okay";
-};
-
-&xphy {
-	status = "okay";
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
deleted file mode 100644
index bda50936f2a839..00000000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ /dev/null
@@ -1,1441 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2023 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-#include <dt-bindings/clock/mediatek,mt7988-clk.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/phy/phy.h>
-#include <dt-bindings/pinctrl/mt65xx.h>
-#include <dt-bindings/reset/ti-syscon.h>
-#include <dt-bindings/thermal/thermal.h>
-
-/ {
-	compatible = "mediatek,mt7988";
-	interrupt-parent = <&gic>;
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	cci: cci {
-		compatible = "mediatek,mt7988-cci",
-			     "mediatek,mt8183-cci";
-		clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>,
-			 <&topckgen CLK_TOP_XTAL>;
-		clock-names = "cci", "intermediate";
-		operating-points-v2 = <&cci_opp>;
-	};
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		cpu0: cpu@0 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a73";
-			enable-method = "psci";
-			reg = <0x0>;
-			clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
-				 <&topckgen CLK_TOP_XTAL>;
-			clock-names = "cpu", "intermediate";
-			operating-points-v2 = <&cluster0_opp>;
-			mediatek,cci = <&cci>;
-		};
-
-		cpu1: cpu@1 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a73";
-			enable-method = "psci";
-			reg = <0x1>;
-			clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
-				 <&topckgen CLK_TOP_XTAL>;
-			clock-names = "cpu", "intermediate";
-			operating-points-v2 = <&cluster0_opp>;
-			mediatek,cci = <&cci>;
-		};
-
-		cpu2: cpu@2 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a73";
-			enable-method = "psci";
-			reg = <0x2>;
-			clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
-				 <&topckgen CLK_TOP_XTAL>;
-			clock-names = "cpu", "intermediate";
-			operating-points-v2 = <&cluster0_opp>;
-			mediatek,cci = <&cci>;
-		};
-
-		cpu3: cpu@3 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a73";
-			enable-method = "psci";
-			reg = <0x3>;
-			clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
-				 <&topckgen CLK_TOP_XTAL>;
-			clock-names = "cpu", "intermediate";
-			operating-points-v2 = <&cluster0_opp>;
-			mediatek,cci = <&cci>;
-		};
-
-		cluster0_opp: opp_table0 {
-			compatible = "operating-points-v2";
-			opp-shared;
-			opp00 {
-				opp-hz = /bits/ 64 <800000000>;
-				opp-microvolt = <850000>;
-			};
-			opp01 {
-				opp-hz = /bits/ 64 <1100000000>;
-				opp-microvolt = <850000>;
-			};
-			opp02 {
-				opp-hz = /bits/ 64 <1500000000>;
-				opp-microvolt = <850000>;
-			};
-			opp03 {
-				opp-hz = /bits/ 64 <1800000000>;
-				opp-microvolt = <900000>;
-			};
-		};
-	};
-
-	cci_opp: opp_table_cci {
-		compatible = "operating-points-v2";
-		opp-shared;
-		opp00 {
-			opp-hz = /bits/ 64 <480000000>;
-			opp-microvolt = <850000>;
-		};
-		opp01 {
-			opp-hz = /bits/ 64 <660000000>;
-			opp-microvolt = <850000>;
-		};
-		opp02 {
-			opp-hz = /bits/ 64 <900000000>;
-			opp-microvolt = <850000>;
-		};
-		opp03 {
-			opp-hz = /bits/ 64 <1080000000>;
-			opp-microvolt = <900000>;
-		};
-	};
-
-	clk40m: oscillator@0 {
-		compatible = "fixed-clock";
-		clock-frequency = <40000000>;
-		#clock-cells = <0>;
-		clock-output-names = "clkxtal";
-	};
-
-	pmu {
-		compatible = "arm,cortex-a73-pmu";
-		interrupt-parent = <&gic>;
-		interrupt = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
-	};
-
-	psci {
-		compatible  = "arm,psci-0.2";
-		method      = "smc";
-	};
-
-	reg_1p8v: regulator-1p8v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-1.8V";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	reg_3p3v: regulator-3p3v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-3.3V";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	reserved-memory {
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
-
-		/* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */
-		secmon_reserved: secmon@43000000 {
-			reg = <0 0x43000000 0 0x50000>;
-			no-map;
-		};
-	};
-
-	soc {
-		#address-cells = <2>;
-		#size-cells = <2>;
-		compatible = "simple-bus";
-		ranges;
-
-		gic: interrupt-controller@c000000 {
-			compatible = "arm,gic-v3";
-			#interrupt-cells = <3>;
-			interrupt-parent = <&gic>;
-			interrupt-controller;
-			reg = <0 0x0c000000 0 0x40000>,  /* GICD */
-			      <0 0x0c080000 0 0x200000>, /* GICR */
-			      <0 0x0c400000 0 0x2000>,   /* GICC */
-			      <0 0x0c410000 0 0x1000>,   /* GICH */
-			      <0 0x0c420000 0 0x2000>;   /* GICV */
-
-			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
-		};
-
-		phyfw: phy-firmware@f000000 {
-			compatible = "mediatek,2p5gphy-fw";
-			reg = <0 0x0f000000 0 0x8000>,
-			      <0 0x0f100000 0 0x20000>,
-			      <0 0x0f0f0000 0 0x200>;
-		};
-
-		infracfg: infracfg@10001000 {
-			compatible = "mediatek,mt7988-infracfg", "syscon";
-			reg = <0 0x10001000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		topckgen: topckgen@1001b000 {
-			compatible = "mediatek,mt7988-topckgen", "syscon";
-			reg = <0 0x1001b000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		watchdog: watchdog@1001c000 {
-			compatible = "mediatek,mt7988-wdt",
-				     "mediatek,mt6589-wdt",
-				     "syscon";
-			reg = <0 0x1001c000 0 0x1000>;
-			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
-			#reset-cells = <1>;
-		};
-
-		apmixedsys: apmixedsys@1001e000 {
-			compatible = "mediatek,mt7988-apmixedsys";
-			reg = <0 0x1001e000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		pio: pinctrl@1001f000 {
-			compatible = "mediatek,mt7988-pinctrl", "syscon";
-			reg = <0 0x1001f000 0 0x1000>,
-			<0 0x11c10000 0 0x1000>,
-			<0 0x11d00000 0 0x1000>,
-			<0 0x11d20000 0 0x1000>,
-			<0 0x11e00000 0 0x1000>,
-			<0 0x11f00000 0 0x1000>,
-			<0 0x1000b000 0 0x1000>;
-			reg-names = "gpio_base", "iocfg_tr_base",
-				    "iocfg_br_base", "iocfg_rb_base",
-				    "iocfg_lb_base", "iocfg_tl_base", "eint";
-			gpio-controller;
-			#gpio-cells = <2>;
-			gpio-ranges = <&pio 0 0 84>;
-			interrupt-controller;
-			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-parent = <&gic>;
-			#interrupt-cells = <2>;
-
-			mdio0_pins: mdio0-pins {
-				mux {
-					function = "eth";
-					groups = "mdc_mdio0";
-				};
-
-				conf {
-					groups = "mdc_mdio0";
-					drive-strength = <MTK_DRIVE_8mA>;
-				};
-			};
-
-			i2c0_pins: i2c0-pins-g0 {
-				mux {
-					function = "i2c";
-					groups = "i2c0_1";
-				};
-			};
-
-			i2c1_pins: i2c1-pins-g0 {
-				mux {
-					function = "i2c";
-					groups = "i2c1_0";
-				};
-			};
-
-			i2c1_sfp_pins: i2c1-sfp-pins-g0 {
-				mux {
-					function = "i2c";
-					groups = "i2c1_sfp";
-				};
-			};
-
-			i2c2_pins: i2c2-pins {
-				mux {
-					function = "i2c";
-					groups = "i2c2";
-				};
-			};
-
-			i2c2_0_pins: i2c2-pins-g0 {
-				mux {
-					function = "i2c";
-					groups = "i2c2_0";
-				};
-			};
-
-			i2c2_1_pins: i2c2-pins-g1 {
-				mux {
-					function = "i2c";
-					groups = "i2c2_1";
-				};
-			};
-
-			gbe0_led0_pins: gbe0-led0-pins {
-				mux {
-					function = "led";
-					groups = "gbe0_led0";
-				};
-			};
-
-			gbe1_led0_pins: gbe1-led0-pins {
-				mux {
-					function = "led";
-					groups = "gbe1_led0";
-				};
-			};
-
-			gbe2_led0_pins: gbe2-led0-pins {
-				mux {
-					function = "led";
-					groups = "gbe2_led0";
-				};
-			};
-
-			gbe3_led0_pins: gbe3-led0-pins {
-				mux {
-					function = "led";
-					groups = "gbe3_led0";
-				};
-			};
-
-			gbe0_led1_pins: gbe0-led1-pins {
-				mux {
-					function = "led";
-					groups = "gbe0_led1";
-				};
-			};
-
-			gbe1_led1_pins: gbe1-led1-pins {
-				mux {
-					function = "led";
-					groups = "gbe1_led1";
-				};
-			};
-
-			gbe2_led1_pins: gbe2-led1-pins {
-				mux {
-					function = "led";
-					groups = "gbe2_led1";
-				};
-			};
-
-			gbe3_led1_pins: gbe3-led1-pins {
-				mux {
-					function = "led";
-					groups = "gbe3_led1";
-				};
-			};
-
-			i2p5gbe_led0_pins: 2p5gbe-led0-pins {
-				mux {
-					function = "led";
-					groups = "2p5gbe_led0";
-				};
-			};
-
-			i2p5gbe_led1_pins: 2p5gbe-led1-pins {
-				mux {
-					function = "led";
-					groups = "2p5gbe_led1";
-				};
-			};
-
-			mmc0_pins_emmc_45: mmc0-pins-emmc-45 {
-				mux {
-					function = "flash";
-					groups = "emmc_45";
-				};
-			};
-
-			mmc0_pins_emmc_51: mmc0-pins-emmc-51 {
-				mux {
-					function = "flash";
-					groups = "emmc_51";
-				};
-			};
-
-			mmc0_pins_sdcard: mmc0-pins-sdcard {
-				mux {
-					function = "flash";
-					groups = "sdcard";
-				};
-			};
-
-			uart0_pins: uart0-pins {
-				mux {
-					function = "uart";
-					groups =  "uart0";
-				};
-			};
-
-			snfi_pins: snfi-pins {
-				mux {
-					function = "flash";
-					groups = "snfi";
-				};
-			};
-
-			spi0_pins: spi0-pins {
-				mux {
-					function = "spi";
-					groups = "spi0";
-				};
-			};
-
-			spi0_flash_pins: spi0-flash-pins {
-				mux {
-					function = "spi";
-					groups = "spi0", "spi0_wp_hold";
-				};
-			};
-
-			spi1_pins: spi1-pins {
-				mux {
-					function = "spi";
-					groups = "spi1";
-				};
-			};
-
-			spi2_pins: spi2-pins {
-				mux {
-					function = "spi";
-					groups = "spi2";
-				};
-			};
-
-			spi2_flash_pins: spi2-flash-pins {
-				mux {
-					function = "spi";
-					groups = "spi2", "spi2_wp_hold";
-				};
-			};
-
-			pcie0_pins: pcie0-pins {
-				mux {
-					function = "pcie";
-					groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0",
-						 "pcie_wake_n0_0";
-				};
-			};
-
-			pcie1_pins: pcie1-pins {
-				mux {
-					function = "pcie";
-					groups = "pcie_2l_1_pereset", "pcie_clk_req_n1",
-						 "pcie_wake_n1_0";
-				};
-			};
-
-			pcie2_pins: pcie2-pins {
-				mux {
-					function = "pcie";
-					groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0",
-						 "pcie_wake_n2_0";
-				};
-			};
-
-			pcie3_pins: pcie3-pins {
-				mux {
-					function = "pcie";
-					groups = "pcie_1l_1_pereset", "pcie_clk_req_n3",
-						 "pcie_wake_n3_0";
-				};
-			};
-		};
-
-		pwm: pwm@10048000 {
-			compatible = "mediatek,mt7988-pwm";
-			reg = <0 0x10048000 0 0x1000>;
-			#pwm-cells = <2>;
-			clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
-				 <&infracfg CLK_INFRA_66M_PWM_HCK>,
-				 <&infracfg CLK_INFRA_66M_PWM_CK1>,
-				 <&infracfg CLK_INFRA_66M_PWM_CK2>,
-				 <&infracfg CLK_INFRA_66M_PWM_CK3>,
-				 <&infracfg CLK_INFRA_66M_PWM_CK4>,
-				 <&infracfg CLK_INFRA_66M_PWM_CK5>,
-				 <&infracfg CLK_INFRA_66M_PWM_CK6>,
-				 <&infracfg CLK_INFRA_66M_PWM_CK7>,
-				 <&infracfg CLK_INFRA_66M_PWM_CK8>;
-			clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
-				      "pwm4","pwm5","pwm6","pwm7","pwm8";
-			status = "disabled";
-		};
-
-		sgmiisys0: syscon@10060000 {
-			compatible = "mediatek,mt7988-sgmiisys",
-				     "mediatek,mt7988-sgmiisys_0",
-				     "syscon";
-			reg = <0 0x10060000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		sgmiisys1: syscon@10070000 {
-			compatible = "mediatek,mt7988-sgmiisys",
-				     "mediatek,mt7988-sgmiisys_1",
-				     "syscon";
-			reg = <0 0x10070000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		usxgmiisys0: usxgmiisys@10080000 {
-			compatible = "mediatek,mt7988-usxgmiisys",
-				     "mediatek,mt7988-usxgmiisys_0",
-				     "syscon";
-			reg = <0 0x10080000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		usxgmiisys1: usxgmiisys@10081000 {
-			compatible = "mediatek,mt7988-usxgmiisys",
-				     "mediatek,mt7988-usxgmiisys_1",
-				     "syscon";
-			reg = <0 0x10081000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		mcusys: mcusys@100e0000 {
-			compatible = "mediatek,mt7988-mcusys", "syscon";
-			reg = <0 0x100e0000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		uart0: serial@11000000 {
-			compatible = "mediatek,mt7986-uart",
-				     "mediatek,mt6577-uart";
-			reg = <0 0x11000000 0 0x100>;
-			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
-			/*
-			 * 8250-mtk driver don't control "baud" clock since commit
-			 * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks
-			 * still need to be passed to the driver to prevent probe fail
-			 */
-			clocks = <&topckgen CLK_TOP_UART_SEL>,
-				 <&infracfg CLK_INFRA_52M_UART0_CK>;
-			clock-names = "baud", "bus";
-			assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
-					  <&infracfg CLK_INFRA_MUX_UART0_SEL>;
-			assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
-						 <&topckgen CLK_TOP_UART_SEL>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&uart0_pins>;
-			status = "disabled";
-		};
-
-		snand: spi@11001000 {
-			compatible = "mediatek,mt7986-snand";
-			reg = <0 0x11001000 0 0x1000>;
-			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&infracfg CLK_INFRA_SPINFI>,
-				 <&infracfg CLK_INFRA_NFI>;
-			clock-names = "pad_clk", "nfi_clk";
-			assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
-					  <&topckgen CLK_TOP_NFI1X_SEL>;
-			assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D8>,
-						 <&topckgen CLK_TOP_MPLL_D8>;
-			nand-ecc-engine = <&bch>;
-			mediatek,quad-spi;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&snfi_pins>;
-			status = "disabled";
-		};
-
-		bch: ecc@11002000 {
-			compatible = "mediatek,mt7686-ecc";
-			reg = <0 0x11002000 0 0x1000>;
-			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&topckgen CLK_TOP_NFI1X_SEL>;
-			clock-names = "nfiecc_clk";
-			status = "disabled";
-		};
-
-		i2c0: i2c@11003000 {
-			compatible = "mediatek,mt7988-i2c",
-				     "mediatek,mt7981-i2c";
-			reg = <0 0x11003000 0 0x1000>,
-			      <0 0x10217080 0 0x80>;
-			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
-			clock-div = <1>;
-			clocks = <&infracfg CLK_INFRA_I2C_BCK>,
-				 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
-			clock-names = "main", "dma";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-		};
-
-		i2c1: i2c@11004000 {
-			compatible = "mediatek,mt7988-i2c",
-				     "mediatek,mt7981-i2c";
-			reg = <0 0x11004000 0 0x1000>,
-			      <0 0x10217100 0 0x80>;
-			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
-			clock-div = <1>;
-			clocks = <&infracfg CLK_INFRA_I2C_BCK>,
-				 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
-			clock-names = "main", "dma";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-		};
-
-		i2c2: i2c@11005000 {
-			compatible = "mediatek,mt7988-i2c",
-				"mediatek,mt7981-i2c";
-			reg = <0 0x11005000 0 0x1000>,
-			      <0 0x10217180 0 0x80>;
-			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
-			clock-div = <1>;
-			clocks = <&infracfg CLK_INFRA_I2C_BCK>,
-				 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
-			clock-names = "main", "dma";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-		};
-
-		spi0: spi@11007000 {
-			compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm";
-			reg = <0 0x11007000 0 0x100>;
-			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&topckgen CLK_TOP_MPLL_D2>,
-				 <&topckgen CLK_TOP_SPI_SEL>,
-				 <&infracfg CLK_INFRA_104M_SPI0>,
-				 <&infracfg CLK_INFRA_66M_SPI0_HCK>;
-			clock-names = "parent-clk", "sel-clk", "spi-clk",
-				      "spi-hclk";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-		};
-
-		spi1: spi@11008000 {
-			compatible = "mediatek,ipm-spi-single", "mediatek,spi-ipm";
-			reg = <0 0x11008000 0 0x100>;
-			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&topckgen CLK_TOP_MPLL_D2>,
-				 <&topckgen CLK_TOP_SPI_SEL>,
-				 <&infracfg CLK_INFRA_104M_SPI1>,
-				 <&infracfg CLK_INFRA_66M_SPI1_HCK>;
-			clock-names = "parent-clk", "sel-clk", "spi-clk",
-				      "spi-hclk";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&spi1_pins>;
-			status = "disabled";
-		};
-
-		spi2: spi@11009000 {
-			compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm";
-			reg = <0 0x11009000 0 0x100>;
-			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&topckgen CLK_TOP_MPLL_D2>,
-				 <&topckgen CLK_TOP_SPI_SEL>,
-				 <&infracfg CLK_INFRA_104M_SPI2_BCK>,
-				 <&infracfg CLK_INFRA_66M_SPI2_HCK>;
-			clock-names = "parent-clk", "sel-clk", "spi-clk",
-				      "spi-hclk";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-		};
-
-		fan: pwm-fan {
-			compatible = "pwm-fan";
-			/* cooling level (0, 1, 2) : (0% duty, 50% duty, 100% duty) */
-			cooling-levels = <0 128 255>;
-			#cooling-cells = <2>;
-			#thermal-sensor-cells = <1>;
-			status = "disabled";
-		};
-
-		lvts: lvts@1100a000 {
-			compatible = "mediatek,mt7988-lvts";
-			#thermal-sensor-cells = <1>;
-			reg = <0 0x1100a000 0 0x1000>;
-			clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>;
-			clock-names = "lvts_clk";
-			nvmem-cells = <&lvts_calibration>;
-			nvmem-cell-names = "e_data1";
-		};
-
-		ssusb0: usb@11190000 {
-			compatible = "mediatek,mt7988-xhci",
-				     "mediatek,mtk-xhci";
-			reg = <0 0x11190000 0 0x2e00>,
-			      <0 0x11193e00 0 0x0100>;
-			reg-names = "mac", "ippc";
-			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
-			phys = <&xphyu2port0 PHY_TYPE_USB2>,
-			       <&xphyu3port0 PHY_TYPE_USB3>;
-			clocks = <&infracfg CLK_INFRA_USB_SYS>,
-				 <&infracfg CLK_INFRA_USB_XHCI>,
-				 <&infracfg CLK_INFRA_USB_REF>,
-				 <&infracfg CLK_INFRA_66M_USB_HCK>,
-				 <&infracfg CLK_INFRA_133M_USB_HCK>;
-			clock-names = "sys_ck",
-				      "xhci_ck",
-				      "ref_ck",
-				      "mcu_ck",
-				      "dma_ck";
-			#address-cells = <2>;
-			#size-cells = <2>;
-			mediatek,p0_speed_fixup;
-			status = "disabled";
-		};
-
-		ssusb1: usb@11200000 {
-			compatible = "mediatek,mt7988-xhci",
-				     "mediatek,mtk-xhci";
-			reg = <0 0x11200000 0 0x2e00>,
-			      <0 0x11203e00 0 0x0100>;
-			reg-names = "mac", "ippc";
-			interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
-			phys = <&tphyu2port0 PHY_TYPE_USB2>,
-			       <&tphyu3port0 PHY_TYPE_USB3>;
-			clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>,
-				 <&infracfg CLK_INFRA_USB_XHCI_CK_P1>,
-				 <&infracfg CLK_INFRA_USB_CK_P1>,
-				 <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>,
-				 <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>;
-			clock-names = "sys_ck",
-				      "xhci_ck",
-				      "ref_ck",
-				      "mcu_ck",
-				      "dma_ck";
-			#address-cells = <2>;
-			#size-cells = <2>;
-			status = "disabled";
-		};
-
-		afe: audio-controller@11210000 {
-			compatible = "mediatek,mt79xx-audio";
-			reg = <0 0x11210000 0 0x9000>;
-			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&infracfg CLK_INFRA_66M_AUD_SLV_BCK>,
-				 <&infracfg CLK_INFRA_AUD_26M>,
-				 <&infracfg CLK_INFRA_AUD_L>,
-				 <&infracfg CLK_INFRA_AUD_AUD>,
-				 <&infracfg CLK_INFRA_AUD_EG2>,
-				 <&topckgen CLK_TOP_AUD_SEL>,
-				 <&topckgen CLK_TOP_AUD_I2S_M>;
-			clock-names = "aud_bus_ck",
-				      "aud_26m_ck",
-				      "aud_l_ck",
-				      "aud_aud_ck",
-				      "aud_eg2_ck",
-				      "aud_sel",
-				      "aud_i2s_m";
-			assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
-					  <&topckgen CLK_TOP_A1SYS_SEL>,
-					  <&topckgen CLK_TOP_AUD_L_SEL>,
-					  <&topckgen CLK_TOP_A_TUNER_SEL>;
-			assigned-clock-parents = <&apmixedsys CLK_APMIXED_APLL2>,
-						 <&topckgen CLK_TOP_APLL2_D4>,
-						 <&apmixedsys CLK_APMIXED_APLL2>,
-						 <&topckgen CLK_TOP_APLL2_D4>;
-			status = "disabled";
-		};
-
-		mmc0: mmc@11230000 {
-			compatible = "mediatek,mt7986-mmc",
-				     "mediatek,mt7981-mmc";
-			reg = <0 0x11230000 0 0x1000>,
-			      <0 0x11D60000 0 0x1000>;
-			interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&infracfg CLK_INFRA_MSDC400>,
-				 <&infracfg CLK_INFRA_MSDC2_HCK>,
-				 <&infracfg CLK_INFRA_66M_MSDC_0_HCK>,
-				 <&infracfg CLK_INFRA_133M_MSDC_0_HCK>;
-			assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>,
-					  <&topckgen CLK_TOP_EMMC_400M_SEL>;
-			assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>,
-						 <&apmixedsys CLK_APMIXED_MSDCPLL>;
-			clock-names = "source",
-				      "hclk",
-				      "axi_cg",
-				      "ahb_cg";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-		};
-
-		pcie2: pcie@11280000 {
-			compatible = "mediatek,mt7988-pcie",
-				     "mediatek,mt7986-pcie",
-				     "mediatek,mt8192-pcie";
-			device_type = "pci";
-			#address-cells = <3>;
-			#size-cells = <2>;
-			reg = <0 0x11280000 0 0x2000>;
-			reg-names = "pcie-mac";
-			linux,pci-domain = <3>;
-			interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
-			bus-range = <0x00 0xff>;
-			ranges = <0x81000000 0x00 0x20000000 0x00
-				  0x20000000 0x00 0x00200000>,
-				 <0x82000000 0x00 0x20200000 0x00
-				  0x20200000 0x00 0x07e00000>;
-			clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>,
-				 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>,
-				 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>,
-				 <&infracfg CLK_INFRA_133M_PCIE_CK_P2>;
-			clock-names = "pl_250m", "tl_26m", "peri_26m",
-				      "top_133m";
-			pinctrl-names = "default";
-			pinctrl-0 = <&pcie2_pins>;
-			status = "disabled";
-
-			phys = <&xphyu3port0 PHY_TYPE_PCIE>;
-			phy-names = "pcie-phy";
-
-			#interrupt-cells = <1>;
-			interrupt-map-mask = <0 0 0 0x7>;
-			interrupt-map = <0 0 0 1 &pcie_intc2 0>,
-					<0 0 0 2 &pcie_intc2 1>,
-					<0 0 0 3 &pcie_intc2 2>,
-					<0 0 0 4 &pcie_intc2 3>;
-			pcie_intc2: interrupt-controller {
-				#address-cells = <0>;
-				#interrupt-cells = <1>;
-				interrupt-controller;
-			};
-		};
-
-		pcie3: pcie@11290000 {
-			compatible = "mediatek,mt7988-pcie",
-				     "mediatek,mt7986-pcie",
-				     "mediatek,mt8192-pcie";
-			device_type = "pci";
-			#address-cells = <3>;
-			#size-cells = <2>;
-			reg = <0 0x11290000 0 0x2000>;
-			reg-names = "pcie-mac";
-			linux,pci-domain = <2>;
-			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
-			bus-range = <0x00 0xff>;
-			ranges = <0x81000000 0x00 0x28000000 0x00
-				  0x28000000 0x00 0x00200000>,
-				 <0x82000000 0x00 0x28200000 0x00
-				  0x28200000 0x00 0x07e00000>;
-			clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>,
-				 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>,
-				 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>,
-				 <&infracfg CLK_INFRA_133M_PCIE_CK_P3>;
-			clock-names = "pl_250m", "tl_26m", "peri_26m",
-				      "top_133m";
-			pinctrl-names = "default";
-			pinctrl-0 = <&pcie3_pins>;
-			status = "disabled";
-
-			#interrupt-cells = <1>;
-			interrupt-map-mask = <0 0 0 0x7>;
-			interrupt-map = <0 0 0 1 &pcie_intc3 0>,
-					<0 0 0 2 &pcie_intc3 1>,
-					<0 0 0 3 &pcie_intc3 2>,
-					<0 0 0 4 &pcie_intc3 3>;
-			pcie_intc3: interrupt-controller {
-				#address-cells = <0>;
-				#interrupt-cells = <1>;
-				interrupt-controller;
-			};
-		};
-
-		pcie0: pcie@11300000 {
-			compatible = "mediatek,mt7988-pcie",
-				     "mediatek,mt7986-pcie",
-				     "mediatek,mt8192-pcie";
-			device_type = "pci";
-			#address-cells = <3>;
-			#size-cells = <2>;
-			reg = <0 0x11300000 0 0x2000>;
-			reg-names = "pcie-mac";
-			linux,pci-domain = <0>;
-			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
-			bus-range = <0x00 0xff>;
-			ranges = <0x81000000 0x00 0x30000000 0x00
-				  0x30000000 0x00 0x00200000>,
-				 <0x82000000 0x00 0x30200000 0x00
-				  0x30200000 0x00 0x07e00000>;
-			clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>,
-				 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>,
-				 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>,
-				 <&infracfg CLK_INFRA_133M_PCIE_CK_P0>;
-			clock-names = "pl_250m", "tl_26m", "peri_26m",
-				      "top_133m";
-			pinctrl-names = "default";
-			pinctrl-0 = <&pcie0_pins>;
-			status = "disabled";
-
-			#interrupt-cells = <1>;
-			interrupt-map-mask = <0 0 0 0x7>;
-			interrupt-map = <0 0 0 1 &pcie_intc0 0>,
-					<0 0 0 2 &pcie_intc0 1>,
-					<0 0 0 3 &pcie_intc0 2>,
-					<0 0 0 4 &pcie_intc0 3>;
-			pcie_intc0: interrupt-controller {
-				#address-cells = <0>;
-				#interrupt-cells = <1>;
-				interrupt-controller;
-			};
-		};
-
-		pcie1: pcie@11310000 {
-			compatible = "mediatek,mt7988-pcie",
-				     "mediatek,mt7986-pcie",
-				     "mediatek,mt8192-pcie";
-			device_type = "pci";
-			#address-cells = <3>;
-			#size-cells = <2>;
-			reg = <0 0x11310000 0 0x2000>;
-			reg-names = "pcie-mac";
-			linux,pci-domain = <1>;
-			interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
-			bus-range = <0x00 0xff>;
-			ranges = <0x81000000 0x00 0x38000000 0x00
-				  0x38000000 0x00 0x00200000>,
-				 <0x82000000 0x00 0x38200000 0x00
-				  0x38200000 0x00 0x07e00000>;
-			clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>,
-				 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>,
-				 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>,
-				 <&infracfg CLK_INFRA_133M_PCIE_CK_P1>;
-			clock-names = "pl_250m", "tl_26m", "peri_26m",
-				      "top_133m";
-			pinctrl-names = "default";
-			pinctrl-0 = <&pcie1_pins>;
-			status = "disabled";
-
-			#interrupt-cells = <1>;
-			interrupt-map-mask = <0 0 0 0x7>;
-			interrupt-map = <0 0 0 1 &pcie_intc1 0>,
-					<0 0 0 2 &pcie_intc1 1>,
-					<0 0 0 3 &pcie_intc1 2>,
-					<0 0 0 4 &pcie_intc1 3>;
-			pcie_intc1: interrupt-controller {
-				#address-cells = <0>;
-				#interrupt-cells = <1>;
-				interrupt-controller;
-			};
-		};
-
-		tphy: tphy@11c50000 {
-			compatible = "mediatek,mt7988",
-				     "mediatek,generic-tphy-v2";
-			#address-cells = <2>;
-			#size-cells = <2>;
-			ranges;
-			status = "disabled";
-			tphyu2port0: usb-phy@11c50000 {
-				reg = <0 0x11c50000 0 0x700>;
-				clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>;
-				clock-names = "ref";
-				#phy-cells = <1>;
-			};
-			tphyu3port0: usb-phy@11c50700 {
-				reg = <0 0x11c50700 0 0x900>;
-				clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>;
-				clock-names = "ref";
-				#phy-cells = <1>;
-				mediatek,usb3-pll-ssc-delta;
-				mediatek,usb3-pll-ssc-delta1;
-			};
-		};
-
-		topmisc: topmisc@11d10000 {
-			compatible = "mediatek,mt7988-topmisc", "syscon",
-				     "mediatek,mt7988-power-controller";
-			reg = <0 0x11d10000 0 0x10000>;
-			#clock-cells = <1>;
-			#power-domain-cells = <1>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-		};
-
-		xphy: xphy@11e10000 {
-			compatible = "mediatek,mt7988",
-				     "mediatek,xsphy";
-			#address-cells = <2>;
-			#size-cells = <2>;
-			ranges;
-			status = "disabled";
-
-			xphyu2port0: usb-phy@11e10000 {
-				reg = <0 0x11e10000 0 0x400>;
-				clocks = <&infracfg CLK_INFRA_USB_UTMI>;
-				clock-names = "ref";
-				#phy-cells = <1>;
-			};
-
-			xphyu3port0: usb-phy@11e13000 {
-				reg = <0 0x11e13400 0 0x500>;
-				clocks = <&infracfg CLK_INFRA_USB_PIPE>;
-				clock-names = "ref";
-				#phy-cells = <1>;
-				mediatek,syscon-type = <&topmisc 0x218 0>;
-			};
-		};
-
-		xfi_pextp0: xfi-pextp@11f20000 {
-			compatible = "mediatek,mt7988-xfi-pextp",
-				     "mediatek,mt7988-xfi-pextp_0",
-				     "syscon";
-			reg = <0 0x11f20000 0 0x10000>;
-			#clock-cells = <1>;
-		};
-
-		xfi_pextp1: xfi-pextp@11f30000 {
-			compatible = "mediatek,mt7988-xfi-pextp",
-				     "mediatek,mt7988-xfi-pextp_1",
-				     "syscon";
-			reg = <0 0x11f30000 0 0x10000>;
-			#clock-cells = <1>;
-		};
-
-		xfi_pll: xfi-pll@11f40000 {
-			compatible = "mediatek,mt7988-xfi-pll", "syscon";
-			reg = <0 0x11f40000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		efuse: efuse@11f50000 {
-			compatible = "mediatek,efuse";
-			reg = <0 0x11f50000 0 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			lvts_calibration: calib@918 {
-				reg = <0x918 0x28>;
-			};
-			phy_calibration_p0: calib@940 {
-				reg = <0x940 0x10>;
-			};
-			phy_calibration_p1: calib@954 {
-				reg = <0x954 0x10>;
-			};
-			phy_calibration_p2: calib@968 {
-				reg = <0x968 0x10>;
-			};
-			phy_calibration_p3: calib@97c {
-				reg = <0x97c 0x10>;
-			};
-			cpufreq_calibration: calib@278 {
-				reg = <0x278 0x1>;
-			};
-		};
-
-		ethsys: syscon@15000000 {
-			#address-cells = <1>;
-			#size-cells = <1>;
-			compatible = "mediatek,mt7988-ethsys", "syscon";
-			reg = <0 0x15000000 0 0x1000>;
-			#clock-cells = <1>;
-			#reset-cells = <1>;
-		};
-
-		switch: switch@15020000 {
-			#address-cells = <1>;
-			#size-cells = <1>;
-			compatible = "mediatek,mt7988-switch";
-			reg = <0 0x15020000 0 0x8000>;
-			interrupt-controller;
-			#interrupt-cells = <1>;
-			interrupt-parent = <&gic>;
-			interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
-			resets = <&ethrst 0>;
-
-			ports {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				port@0 {
-					reg = <0>;
-					label = "lan0";
-					phy-mode = "internal";
-					phy-handle = <&gsw_phy0>;
-				};
-
-				port@1 {
-					reg = <1>;
-					label = "lan1";
-					phy-mode = "internal";
-					phy-handle = <&gsw_phy1>;
-				};
-
-				port@2 {
-					reg = <2>;
-					label = "lan2";
-					phy-mode = "internal";
-					phy-handle = <&gsw_phy2>;
-				};
-
-				port@3 {
-					reg = <3>;
-					label = "lan3";
-					phy-mode = "internal";
-					phy-handle = <&gsw_phy3>;
-				};
-
-				port@6 {
-					reg = <6>;
-					ethernet = <&gmac0>;
-					phy-mode = "internal";
-
-					fixed-link {
-						speed = <10000>;
-						full-duplex;
-						pause;
-					};
-				};
-			};
-
-			mdio {
-				#address-cells = <1>;
-				#size-cells = <0>;
-				mediatek,pio = <&pio>;
-
-				gsw_phy0: ethernet-phy@0 {
-					compatible = "ethernet-phy-ieee802.3-c22";
-					reg = <0>;
-					phy-mode = "internal";
-					nvmem-cells = <&phy_calibration_p0>;
-					nvmem-cell-names = "phy-cal-data";
-
-					leds {
-						#address-cells = <1>;
-						#size-cells = <0>;
-
-						gsw_phy0_led0: gsw-phy0-led0@0 {
-							reg = <0>;
-							function = LED_FUNCTION_LAN;
-							status = "disabled";
-						};
-
-						gsw_phy0_led1: gsw-phy0-led1@1 {
-							reg = <1>;
-							function = LED_FUNCTION_LAN;
-							status = "disabled";
-						};
-					};
-				};
-
-				gsw_phy1: ethernet-phy@1 {
-					compatible = "ethernet-phy-ieee802.3-c22";
-					reg = <1>;
-					phy-mode = "internal";
-					nvmem-cells = <&phy_calibration_p1>;
-					nvmem-cell-names = "phy-cal-data";
-
-					leds {
-						#address-cells = <1>;
-						#size-cells = <0>;
-
-						gsw_phy1_led0: gsw-phy1-led0@0 {
-							reg = <0>;
-							function = LED_FUNCTION_LAN;
-							status = "disabled";
-						};
-
-						gsw_phy1_led1: gsw-phy1-led1@1 {
-							reg = <1>;
-							function = LED_FUNCTION_LAN;
-							status = "disabled";
-						};
-					};
-				};
-
-				gsw_phy2: ethernet-phy@2 {
-					compatible = "ethernet-phy-ieee802.3-c22";
-					reg = <2>;
-					phy-mode = "internal";
-					nvmem-cells = <&phy_calibration_p2>;
-					nvmem-cell-names = "phy-cal-data";
-
-					leds {
-						#address-cells = <1>;
-						#size-cells = <0>;
-
-						gsw_phy2_led0: gsw-phy2-led0@0 {
-							reg = <0>;
-							function = LED_FUNCTION_LAN;
-							status = "disabled";
-						};
-
-						gsw_phy2_led1: gsw-phy2-led1@1 {
-							reg = <1>;
-							function = LED_FUNCTION_LAN;
-							status = "disabled";
-						};
-					};
-				};
-
-				gsw_phy3: ethernet-phy@3 {
-					compatible = "ethernet-phy-ieee802.3-c22";
-					reg = <3>;
-					phy-mode = "internal";
-					nvmem-cells = <&phy_calibration_p3>;
-					nvmem-cell-names = "phy-cal-data";
-
-					leds {
-						#address-cells = <1>;
-						#size-cells = <0>;
-
-						gsw_phy3_led0: gsw-phy3-led0@0 {
-							reg = <0>;
-							function = LED_FUNCTION_LAN;
-							status = "disabled";
-						};
-
-						gsw_phy3_led1: gsw-phy3-led1@1 {
-							reg = <1>;
-							function = LED_FUNCTION_LAN;
-							status = "disabled";
-						};
-					};
-				};
-			};
-		};
-
-		ethwarp: syscon@15031000 {
-			compatible = "mediatek,mt7988-ethwarp", "syscon", "simple-mfd";
-			reg = <0 0x15031000 0 0x1000>;
-			#clock-cells = <1>;
-
-			ethrst: reset-controller {
-				compatible = "ti,syscon-reset";
-				#reset-cells = <1>;
-				ti,reset-bits = <
-					0x8 9 0x8 9 0 0 (ASSERT_SET | DEASSERT_CLEAR | STATUS_NONE)
-				>;
-			};
-		};
-
-		eth: ethernet@15100000 {
-			compatible = "mediatek,mt7988-eth";
-			reg = <0 0x15100000 0 0x80000>,
-			      <0 0x15400000 0 0x380000>;
-			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ethsys CLK_ETHDMA_XGP1_EN>,
-				 <&ethsys CLK_ETHDMA_XGP2_EN>,
-				 <&ethsys CLK_ETHDMA_XGP3_EN>,
-				 <&ethsys CLK_ETHDMA_FE_EN>,
-				 <&ethsys CLK_ETHDMA_GP2_EN>,
-				 <&ethsys CLK_ETHDMA_GP1_EN>,
-				 <&ethsys CLK_ETHDMA_GP3_EN>,
-				 <&ethsys CLK_ETHDMA_ESW_EN>,
-				 <&ethsys CLK_ETHDMA_CRYPT0_EN>,
-				 <&sgmiisys0 CLK_SGM0_TX_EN>,
-				 <&sgmiisys0 CLK_SGM0_RX_EN>,
-				 <&sgmiisys1 CLK_SGM1_TX_EN>,
-				 <&sgmiisys1 CLK_SGM1_RX_EN>,
-				 <&ethwarp CLK_ETHWARP_WOCPU2_EN>,
-				 <&ethwarp CLK_ETHWARP_WOCPU1_EN>,
-				 <&ethwarp CLK_ETHWARP_WOCPU0_EN>,
-				 <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
-				 <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
-				 <&topckgen CLK_TOP_SGM_0_SEL>,
-				 <&topckgen CLK_TOP_SGM_1_SEL>,
-				 <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>,
-				 <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>,
-				 <&topckgen CLK_TOP_ETH_GMII_SEL>,
-				 <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>,
-				 <&topckgen CLK_TOP_ETH_SYS_200M_SEL>,
-				 <&topckgen CLK_TOP_ETH_SYS_SEL>,
-				 <&topckgen CLK_TOP_ETH_XGMII_SEL>,
-				 <&topckgen CLK_TOP_ETH_MII_SEL>,
-				 <&topckgen CLK_TOP_NETSYS_SEL>,
-				 <&topckgen CLK_TOP_NETSYS_500M_SEL>,
-				 <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>,
-				 <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>,
-				 <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>,
-				 <&topckgen CLK_TOP_NETSYS_WARP_SEL>;
-			clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1",
-				      "gp3", "esw", "crypto", "sgmii_tx250m",
-				      "sgmii_rx250m", "sgmii2_tx250m", "sgmii2_rx250m",
-				      "ethwarp_wocpu2", "ethwarp_wocpu1",
-				      "ethwarp_wocpu0", "top_usxgmii0_sel",
-				      "top_usxgmii1_sel", "top_sgm0_sel",
-				      "top_sgm1_sel", "top_xfi_phy0_xtal_sel",
-				      "top_xfi_phy1_xtal_sel", "top_eth_gmii_sel",
-				      "top_eth_refck_50m_sel", "top_eth_sys_200m_sel",
-				      "top_eth_sys_sel", "top_eth_xgmii_sel",
-				      "top_eth_mii_sel", "top_netsys_sel",
-				      "top_netsys_500m_sel", "top_netsys_pao_2x_sel",
-				      "top_netsys_sync_250m_sel",
-				      "top_netsys_ppefb_250m_sel",
-				      "top_netsys_warp_sel";
-			assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
-					  <&topckgen CLK_TOP_NETSYS_GSW_SEL>,
-					  <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
-					  <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
-					  <&topckgen CLK_TOP_SGM_0_SEL>,
-					  <&topckgen CLK_TOP_SGM_1_SEL>;
-			assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
-						 <&topckgen CLK_TOP_NET1PLL_D4>,
-						 <&topckgen CLK_TOP_NET1PLL_D8_D4>,
-						 <&topckgen CLK_TOP_NET1PLL_D8_D4>,
-						 <&apmixedsys CLK_APMIXED_SGMPLL>,
-						 <&apmixedsys CLK_APMIXED_SGMPLL>;
-			mediatek,ethsys = <&ethsys>;
-			mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
-			mediatek,usxgmiisys = <&usxgmiisys0>, <&usxgmiisys1>;
-			mediatek,xfi-pextp = <&xfi_pextp0>, <&xfi_pextp1>;
-			mediatek,xfi-pll = <&xfi_pll>;
-			mediatek,infracfg = <&topmisc>;
-			mediatek,toprgu = <&watchdog>;
-			#reset-cells = <1>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			gmac0: mac@0 {
-				compatible = "mediatek,eth-mac";
-				reg = <0>;
-				phy-mode = "internal";
-				status = "disabled";
-
-				fixed-link {
-					speed = <10000>;
-					full-duplex;
-					pause;
-				};
-			};
-
-			gmac1: mac@1 {
-				compatible = "mediatek,eth-mac";
-				reg = <1>;
-				status = "disabled";
-			};
-
-			gmac2: mac@2 {
-				compatible = "mediatek,eth-mac";
-				reg = <2>;
-				status = "disabled";
-			};
-
-			mdio_bus: mdio-bus {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				/* internal 2.5G PHY */
-				int_2p5g_phy: ethernet-phy@15 {
-					reg = <15>;
-					compatible = "ethernet-phy-ieee802.3-c45";
-					phy-mode = "internal";
-				};
-			};
-		};
-
-		crypto: crypto@15600000 {
-			compatible = "inside-secure,safexcel-eip197b";
-			reg = <0 0x15600000 0 0x180000>;
-			interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "ring0", "ring1", "ring2", "ring3";
-			status = "okay";
-		};
-	};
-
-	thermal-zones {
-		cpu_thermal: cpu-thermal {
-			polling-delay-passive = <1000>;
-			polling-delay = <1000>;
-			thermal-sensors = <&lvts 0>;
-			trips {
-				cpu_trip_crit: crit {
-					temperature = <125000>;
-					hysteresis = <2000>;
-					type = "critical";
-				};
-
-				cpu_trip_hot: hot {
-					temperature = <120000>;
-					hysteresis = <2000>;
-					type = "hot";
-				};
-
-				cpu_trip_active_high: active-high {
-					temperature = <115000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-
-				cpu_trip_active_med: active-med {
-					temperature = <85000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-
-				cpu_trip_active_low: active-low {
-					temperature = <40000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-			};
-
-			cooling-maps {
-				cpu-active-high {
-				/* active: set fan to cooling level 2 */
-					cooling-device = <&fan 3 3>;
-					trip = <&cpu_trip_active_high>;
-				};
-
-				cpu-active-low {
-				/* active: set fan to cooling level 1 */
-					cooling-device = <&fan 2 2>;
-					trip = <&cpu_trip_active_med>;
-				};
-
-				cpu-passive {
-				/* passive: set fan to cooling level 0 */
-					cooling-device = <&fan 1 1>;
-					trip = <&cpu_trip_active_low>;
-				};
-			};
-		};
-	};
-
-	timer {
-		compatible = "arm,armv8-timer";
-		interrupt-parent = <&gic>;
-		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
-	};
-};
diff --git a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7981-apmixed.c b/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7981-apmixed.c
deleted file mode 100644
index 1647021de88d8d..00000000000000
--- a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7981-apmixed.c
+++ /dev/null
@@ -1,102 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2021 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
- * Author: Jianhui Zhao <zhaojh329@gmail.com>
- * Author: Daniel Golle <daniel@makrotopia.org>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include "clk-mtk.h"
-#include "clk-gate.h"
-#include "clk-mux.h"
-
-#include <dt-bindings/clock/mediatek,mt7981-clk.h>
-#include <linux/clk.h>
-
-#define MT7981_PLL_FMAX (2500UL * MHZ)
-#define CON0_MT7981_RST_BAR BIT(27)
-
-#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,       \
-		 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift,         \
-		 _div_table, _parent_name)                                     \
-	{                                                                      \
-		.id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg,    \
-		.en_mask = _en_mask, .flags = _flags,                          \
-		.rst_bar_mask = CON0_MT7981_RST_BAR, .fmax = MT7981_PLL_FMAX,  \
-		.pcwbits = _pcwbits, .pd_reg = _pd_reg, .pd_shift = _pd_shift, \
-		.tuner_reg = _tuner_reg, .pcw_reg = _pcw_reg,                  \
-		.pcw_shift = _pcw_shift, .div_table = _div_table,              \
-		.parent_name = _parent_name,                                   \
-	}
-
-#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg,   \
-	    _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift)                       \
-	PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,       \
-		 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, NULL,   \
-		 "clkxtal")
-
-static const struct mtk_pll_data plls[] = {
-	PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, PLL_AO,
-	    32, 0x0200, 4, 0, 0x0204, 0),
-	PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x00000001, 0, 32,
-	    0x0210, 4, 0, 0x0214, 0),
-	PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x00000001, 0, 32,
-	    0x0220, 4, 0, 0x0224, 0),
-	PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023C, 0x00000001, 0, 32,
-	    0x0230, 4, 0, 0x0234, 0),
-	PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024C, 0x00000001, 0, 32,
-	    0x0240, 4, 0, 0x0244, 0),
-	PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0250, 0x025C, 0x00000001, 0, 32,
-	    0x0250, 4, 0, 0x0254, 0),
-	PLL(CLK_APMIXED_MPLL, "mpll", 0x0260, 0x0270, 0x00000001, 0, 32,
-	    0x0260, 4, 0, 0x0264, 0),
-	PLL(CLK_APMIXED_APLL2, "apll2", 0x0278, 0x0288, 0x00000001, 0, 32,
-	    0x0278, 4, 0, 0x027C, 0),
-};
-
-static const struct of_device_id of_match_clk_mt7981_apmixed[] = {
-	{ .compatible = "mediatek,mt7981-apmixedsys", },
-	{}
-};
-
-static int clk_mt7981_apmixed_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
-
-	clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMPLL]);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_apmixed_data;
-	}
-	return r;
-
-free_apmixed_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
-
-static struct platform_driver clk_mt7981_apmixed_drv = {
-	.probe = clk_mt7981_apmixed_probe,
-	.driver = {
-		.name = "clk-mt7981-apmixed",
-		.of_match_table = of_match_clk_mt7981_apmixed,
-	},
-};
-builtin_platform_driver(clk_mt7981_apmixed_drv);
diff --git a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7981-eth.c b/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7981-eth.c
deleted file mode 100644
index 4aba657aa6f637..00000000000000
--- a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7981-eth.c
+++ /dev/null
@@ -1,139 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2021 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
- * Author: Jianhui Zhao <zhaojh329@gmail.com>
- * Author: Daniel Golle <daniel@makrotopia.org>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-
-#include "clk-mtk.h"
-#include "clk-gate.h"
-
-#include <dt-bindings/clock/mediatek,mt7981-clk.h>
-
-static const struct mtk_gate_regs sgmii0_cg_regs = {
-	.set_ofs = 0xE4,
-	.clr_ofs = 0xE4,
-	.sta_ofs = 0xE4,
-};
-
-#define GATE_SGMII0(_id, _name, _parent, _shift) {	\
-		.id = _id,				\
-		.name = _name,				\
-		.parent_name = _parent,			\
-		.regs = &sgmii0_cg_regs,			\
-		.shift = _shift,			\
-		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\
-	}
-
-static const struct mtk_gate sgmii0_clks[] __initconst = {
-	GATE_SGMII0(CLK_SGM0_TX_EN, "sgm0_tx_en", "usb_tx250m", 2),
-	GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", "usb_eq_rx250m", 3),
-	GATE_SGMII0(CLK_SGM0_CK0_EN, "sgm0_ck0_en", "usb_ln0", 4),
-	GATE_SGMII0(CLK_SGM0_CDR_CK0_EN, "sgm0_cdr_ck0_en", "usb_cdr", 5),
-};
-
-static const struct mtk_gate_regs sgmii1_cg_regs = {
-	.set_ofs = 0xE4,
-	.clr_ofs = 0xE4,
-	.sta_ofs = 0xE4,
-};
-
-#define GATE_SGMII1(_id, _name, _parent, _shift) {	\
-		.id = _id,				\
-		.name = _name,				\
-		.parent_name = _parent,			\
-		.regs = &sgmii1_cg_regs,			\
-		.shift = _shift,			\
-		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\
-	}
-
-static const struct mtk_gate sgmii1_clks[] __initconst = {
-	GATE_SGMII1(CLK_SGM1_TX_EN, "sgm1_tx_en", "usb_tx250m", 2),
-	GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", "usb_eq_rx250m", 3),
-	GATE_SGMII1(CLK_SGM1_CK1_EN, "sgm1_ck1_en", "usb_ln0", 4),
-	GATE_SGMII1(CLK_SGM1_CDR_CK1_EN, "sgm1_cdr_ck1_en", "usb_cdr", 5),
-};
-
-static const struct mtk_gate_regs eth_cg_regs = {
-	.set_ofs = 0x30,
-	.clr_ofs = 0x30,
-	.sta_ofs = 0x30,
-};
-
-#define GATE_ETH(_id, _name, _parent, _shift) {	\
-		.id = _id,				\
-		.name = _name,				\
-		.parent_name = _parent,			\
-		.regs = &eth_cg_regs,			\
-		.shift = _shift,			\
-		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\
-	}
-
-static const struct mtk_gate eth_clks[] __initconst = {
-	GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "netsys_2x", 6),
-	GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "sgm_325m", 7),
-	GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "sgm_325m", 8),
-	GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", "netsys_wed_mcu", 15),
-};
-
-static void __init mtk_sgmiisys_0_init(struct device_node *node)
-{
-	struct clk_onecell_data *clk_data;
-	int r;
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks));
-
-	mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks),
-			       clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-	if (r)
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-}
-CLK_OF_DECLARE(mtk_sgmiisys_0, "mediatek,mt7981-sgmiisys_0",
-	       mtk_sgmiisys_0_init);
-
-static void __init mtk_sgmiisys_1_init(struct device_node *node)
-{
-	struct clk_onecell_data *clk_data;
-	int r;
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks));
-
-	mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks),
-			       clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-
-	if (r)
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-}
-CLK_OF_DECLARE(mtk_sgmiisys_1, "mediatek,mt7981-sgmiisys_1",
-	       mtk_sgmiisys_1_init);
-
-static void __init mtk_ethsys_init(struct device_node *node)
-{
-	struct clk_onecell_data *clk_data;
-	int r;
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(eth_clks));
-
-	mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-
-	if (r)
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-}
-CLK_OF_DECLARE(mtk_ethsys, "mediatek,mt7981-ethsys", mtk_ethsys_init);
diff --git a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7981-infracfg.c b/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7981-infracfg.c
deleted file mode 100644
index 8416829e3580c5..00000000000000
--- a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7981-infracfg.c
+++ /dev/null
@@ -1,235 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2021 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
- * Author: Jianhui Zhao <zhaojh329@gmail.com>
- * Author: Daniel Golle <daniel@makrotopia.org>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include "clk-mtk.h"
-#include "clk-gate.h"
-#include "clk-mux.h"
-
-#include <dt-bindings/clock/mediatek,mt7981-clk.h>
-#include <linux/clk.h>
-
-static DEFINE_SPINLOCK(mt7981_clk_lock);
-
-static const struct mtk_fixed_factor infra_divs[] = {
-	FACTOR(CLK_INFRA_66M_MCK, "infra_66m_mck", "sysaxi_sel", 1, 2),
-};
-
-static const char *const infra_uart_parent[] __initconst = { "csw_f26m_sel",
-								"uart_sel" };
-
-static const char *const infra_spi0_parents[] __initconst = { "i2c_sel",
-							      "spi_sel" };
-
-static const char *const infra_spi1_parents[] __initconst = { "i2c_sel",
-							      "spim_mst_sel" };
-
-static const char *const infra_pwm1_parents[] __initconst = { "pwm_sel" };
-
-static const char *const infra_pwm_bsel_parents[] __initconst = {
-	"cb_rtc_32p7k", "csw_f26m_sel", "infra_66m_mck", "pwm_sel"
-};
-
-static const char *const infra_pcie_parents[] __initconst = {
-	"cb_rtc_32p7k", "csw_f26m_sel", "cb_cksq_40m", "pextp_tl_ck_sel"
-};
-
-static const struct mtk_mux infra_muxes[] = {
-	/* MODULE_CLK_SEL_0 */
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART0_SEL, "infra_uart0_sel",
-			     infra_uart_parent, 0x0018, 0x0010, 0x0014, 0, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART1_SEL, "infra_uart1_sel",
-			     infra_uart_parent, 0x0018, 0x0010, 0x0014, 1, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART2_SEL, "infra_uart2_sel",
-			     infra_uart_parent, 0x0018, 0x0010, 0x0014, 2, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI0_SEL, "infra_spi0_sel",
-			     infra_spi0_parents, 0x0018, 0x0010, 0x0014, 4, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI1_SEL, "infra_spi1_sel",
-			     infra_spi1_parents, 0x0018, 0x0010, 0x0014, 5, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI2_SEL, "infra_spi2_sel",
-			     infra_spi0_parents, 0x0018, 0x0010, 0x0014, 6, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel",
-			     infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 9, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel",
-			     infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 11, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM3_SEL, "infra_pwm3_sel",
-			     infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 15, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_BSEL, "infra_pwm_bsel",
-			     infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 13,
-			     2, -1, -1, -1),
-	/* MODULE_CLK_SEL_1 */
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_SEL, "infra_pcie_sel",
-			     infra_pcie_parents, 0x0028, 0x0020, 0x0024, 0, 2,
-			     -1, -1, -1),
-};
-
-static const struct mtk_gate_regs infra0_cg_regs = {
-	.set_ofs = 0x40,
-	.clr_ofs = 0x44,
-	.sta_ofs = 0x48,
-};
-
-static const struct mtk_gate_regs infra1_cg_regs = {
-	.set_ofs = 0x50,
-	.clr_ofs = 0x54,
-	.sta_ofs = 0x58,
-};
-
-static const struct mtk_gate_regs infra2_cg_regs = {
-	.set_ofs = 0x60,
-	.clr_ofs = 0x64,
-	.sta_ofs = 0x68,
-};
-
-#define GATE_INFRA0(_id, _name, _parent, _shift)                               \
-	{                                                                      \
-		.id = _id, .name = _name, .parent_name = _parent,              \
-		.regs = &infra0_cg_regs, .shift = _shift,                      \
-		.ops = &mtk_clk_gate_ops_setclr,                               \
-	}
-
-#define GATE_INFRA1(_id, _name, _parent, _shift)                               \
-	{                                                                      \
-		.id = _id, .name = _name, .parent_name = _parent,              \
-		.regs = &infra1_cg_regs, .shift = _shift,                      \
-		.ops = &mtk_clk_gate_ops_setclr,                               \
-	}
-
-#define GATE_INFRA2(_id, _name, _parent, _shift)                               \
-	{                                                                      \
-		.id = _id, .name = _name, .parent_name = _parent,              \
-		.regs = &infra2_cg_regs, .shift = _shift,                      \
-		.ops = &mtk_clk_gate_ops_setclr,                               \
-	}
-
-static const struct mtk_gate infra_clks[] = {
-	/* INFRA0 */
-	GATE_INFRA0(CLK_INFRA_GPT_STA, "infra_gpt_sta", "infra_66m_mck", 0),
-	GATE_INFRA0(CLK_INFRA_PWM_HCK, "infra_pwm_hck", "infra_66m_mck", 1),
-	GATE_INFRA0(CLK_INFRA_PWM_STA, "infra_pwm_sta", "infra_pwm_bsel", 2),
-	GATE_INFRA0(CLK_INFRA_PWM1_CK, "infra_pwm1", "infra_pwm1_sel", 3),
-	GATE_INFRA0(CLK_INFRA_PWM2_CK, "infra_pwm2", "infra_pwm2_sel", 4),
-	GATE_INFRA0(CLK_INFRA_CQ_DMA_CK, "infra_cq_dma", "sysaxi", 6),
-
-	GATE_INFRA0(CLK_INFRA_AUD_BUS_CK, "infra_aud_bus", "sysaxi", 8),
-	GATE_INFRA0(CLK_INFRA_AUD_26M_CK, "infra_aud_26m", "csw_f26m_sel", 9),
-	GATE_INFRA0(CLK_INFRA_AUD_L_CK, "infra_aud_l", "aud_l", 10),
-	GATE_INFRA0(CLK_INFRA_AUD_AUD_CK, "infra_aud_aud", "a1sys", 11),
-	GATE_INFRA0(CLK_INFRA_AUD_EG2_CK, "infra_aud_eg2", "a_tuner", 13),
-	GATE_INFRA0(CLK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", "csw_f26m_sel",
-		    14),
-	GATE_INFRA0(CLK_INFRA_DBG_CK, "infra_dbg", "infra_66m_mck", 15),
-	GATE_INFRA0(CLK_INFRA_AP_DMA_CK, "infra_ap_dma", "infra_66m_mck", 16),
-	GATE_INFRA0(CLK_INFRA_SEJ_CK, "infra_sej", "infra_66m_mck", 24),
-	GATE_INFRA0(CLK_INFRA_SEJ_13M_CK, "infra_sej_13m", "csw_f26m_sel", 25),
-	GATE_INFRA0(CLK_INFRA_PWM3_CK, "infra_pwm3", "infra_pwm3_sel", 27),
-	/* INFRA1 */
-	GATE_INFRA1(CLK_INFRA_THERM_CK, "infra_therm", "csw_f26m_sel", 0),
-	GATE_INFRA1(CLK_INFRA_I2C0_CK, "infra_i2c0", "i2c_bck", 1),
-	GATE_INFRA1(CLK_INFRA_UART0_CK, "infra_uart0", "infra_uart0_sel", 2),
-	GATE_INFRA1(CLK_INFRA_UART1_CK, "infra_uart1", "infra_uart1_sel", 3),
-	GATE_INFRA1(CLK_INFRA_UART2_CK, "infra_uart2", "infra_uart2_sel", 4),
-	GATE_INFRA1(CLK_INFRA_SPI2_CK, "infra_spi2", "infra_spi2_sel", 6),
-	GATE_INFRA1(CLK_INFRA_SPI2_HCK_CK, "infra_spi2_hck", "infra_66m_mck", 7),
-	GATE_INFRA1(CLK_INFRA_NFI1_CK, "infra_nfi1", "nfi1x", 8),
-	GATE_INFRA1(CLK_INFRA_SPINFI1_CK, "infra_spinfi1", "spinfi_bck", 9),
-	GATE_INFRA1(CLK_INFRA_NFI_HCK_CK, "infra_nfi_hck", "infra_66m_mck", 10),
-	GATE_INFRA1(CLK_INFRA_SPI0_CK, "infra_spi0", "infra_spi0_sel", 11),
-	GATE_INFRA1(CLK_INFRA_SPI1_CK, "infra_spi1", "infra_spi1_sel", 12),
-	GATE_INFRA1(CLK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", "infra_66m_mck",
-		    13),
-	GATE_INFRA1(CLK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", "infra_66m_mck",
-		    14),
-	GATE_INFRA1(CLK_INFRA_FRTC_CK, "infra_frtc", "cb_rtc_32k", 15),
-	GATE_INFRA1(CLK_INFRA_MSDC_CK, "infra_msdc", "emmc_400m", 16),
-	GATE_INFRA1(CLK_INFRA_MSDC_HCK_CK, "infra_msdc_hck", "emmc_208m", 17),
-	GATE_INFRA1(CLK_INFRA_MSDC_133M_CK, "infra_msdc_133m", "sysaxi", 18),
-	GATE_INFRA1(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", "sysaxi", 19),
-	GATE_INFRA1(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", "infra_adc_frc", 20),
-	GATE_INFRA1(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", "csw_f26m", 21),
-	GATE_INFRA1(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", "nfi1x", 23),
-	GATE_INFRA1(CLK_INFRA_I2C_MCK_CK, "infra_i2c_mck", "sysaxi", 25),
-	GATE_INFRA1(CLK_INFRA_I2C_PCK_CK, "infra_i2c_pck", "infra_66m_mck", 26),
-	/* INFRA2 */
-	GATE_INFRA2(CLK_INFRA_IUSB_133_CK, "infra_iusb_133", "sysaxi", 0),
-	GATE_INFRA2(CLK_INFRA_IUSB_66M_CK, "infra_iusb_66m", "sysaxi", 1),
-	GATE_INFRA2(CLK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", "u2u3_sys", 2),
-	GATE_INFRA2(CLK_INFRA_IUSB_CK, "infra_iusb", "u2u3_ref", 3),
-	GATE_INFRA2(CLK_INFRA_IPCIE_CK, "infra_ipcie", "pextp_tl", 12),
-	GATE_INFRA2(CLK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", "cb_cksq_40m",
-		    13),
-	GATE_INFRA2(CLK_INFRA_IPCIER_CK, "infra_ipcier", "csw_f26m", 14),
-	GATE_INFRA2(CLK_INFRA_IPCIEB_CK, "infra_ipcieb", "sysaxi", 15),
-};
-
-static int clk_mt7981_infracfg_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-	void __iomem *base;
-	int nr = ARRAY_SIZE(infra_divs) + ARRAY_SIZE(infra_muxes) +
-		 ARRAY_SIZE(infra_clks);
-
-	base = of_iomap(node, 0);
-	if (!base) {
-		pr_err("%s(): ioremap failed\n", __func__);
-		return -ENOMEM;
-	}
-
-	clk_data = mtk_alloc_clk_data(nr);
-
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
-	mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node,
-			       &mt7981_clk_lock, clk_data);
-	mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
-			       clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_infracfg_data;
-	}
-	return r;
-
-free_infracfg_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
-
-static const struct of_device_id of_match_clk_mt7981_infracfg[] = {
-	{ .compatible = "mediatek,mt7981-infracfg", },
-	{}
-};
-
-static struct platform_driver clk_mt7981_infracfg_drv = {
-	.probe = clk_mt7981_infracfg_probe,
-	.driver = {
-		.name = "clk-mt7981-infracfg",
-		.of_match_table = of_match_clk_mt7981_infracfg,
-	},
-};
-builtin_platform_driver(clk_mt7981_infracfg_drv);
diff --git a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7981-topckgen.c b/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7981-topckgen.c
deleted file mode 100644
index ce6dc18672665a..00000000000000
--- a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7981-topckgen.c
+++ /dev/null
@@ -1,450 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2021 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
- * Author: Jianhui Zhao <zhaojh329@gmail.com>
- */
-
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include "clk-mtk.h"
-#include "clk-gate.h"
-#include "clk-mux.h"
-
-#include <dt-bindings/clock/mediatek,mt7981-clk.h>
-#include <linux/clk.h>
-
-static DEFINE_SPINLOCK(mt7981_clk_lock);
-
-static const struct mtk_fixed_factor top_divs[] = {
-	FACTOR(CLK_TOP_CB_CKSQ_40M, "cb_cksq_40m", "clkxtal", 1, 1),
-	FACTOR(CLK_TOP_CB_M_416M, "cb_m_416m", "mpll", 1, 1),
-	FACTOR(CLK_TOP_CB_M_D2, "cb_m_d2", "mpll", 1, 2),
-	FACTOR(CLK_TOP_CB_M_D3, "cb_m_d3", "mpll", 1, 3),
-	FACTOR(CLK_TOP_M_D3_D2, "m_d3_d2", "mpll", 1, 2),
-	FACTOR(CLK_TOP_CB_M_D4, "cb_m_d4", "mpll", 1, 4),
-	FACTOR(CLK_TOP_CB_M_D8, "cb_m_d8", "mpll", 1, 8),
-	FACTOR(CLK_TOP_M_D8_D2, "m_d8_d2", "mpll", 1, 16),
-	FACTOR(CLK_TOP_CB_MM_720M, "cb_mm_720m", "mmpll", 1, 1),
-	FACTOR(CLK_TOP_CB_MM_D2, "cb_mm_d2", "mmpll", 1, 2),
-	FACTOR(CLK_TOP_CB_MM_D3, "cb_mm_d3", "mmpll", 1, 3),
-	FACTOR(CLK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", "mmpll", 1, 15),
-	FACTOR(CLK_TOP_CB_MM_D4, "cb_mm_d4", "mmpll", 1, 4),
-	FACTOR(CLK_TOP_CB_MM_D6, "cb_mm_d6", "mmpll", 1, 6),
-	FACTOR(CLK_TOP_MM_D6_D2, "mm_d6_d2", "mmpll", 1, 12),
-	FACTOR(CLK_TOP_CB_MM_D8, "cb_mm_d8", "mmpll", 1, 8),
-	FACTOR(CLK_TOP_CB_APLL2_196M, "cb_apll2_196m", "apll2", 1, 1),
-	FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2),
-	FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
-	FACTOR(CLK_TOP_NET1_2500M, "net1_2500m", "net1pll", 1, 1),
-	FACTOR(CLK_TOP_CB_NET1_D4, "cb_net1_d4", "net1pll", 1, 4),
-	FACTOR(CLK_TOP_CB_NET1_D5, "cb_net1_d5", "net1pll", 1, 5),
-	FACTOR(CLK_TOP_NET1_D5_D2, "net1_d5_d2", "net1pll", 1, 10),
-	FACTOR(CLK_TOP_NET1_D5_D4, "net1_d5_d4", "net1pll", 1, 20),
-	FACTOR(CLK_TOP_CB_NET1_D8, "cb_net1_d8", "net1pll", 1, 8),
-	FACTOR(CLK_TOP_NET1_D8_D2, "net1_d8_d2", "net1pll", 1, 16),
-	FACTOR(CLK_TOP_NET1_D8_D4, "net1_d8_d4", "net1pll", 1, 32),
-	FACTOR(CLK_TOP_CB_NET2_800M, "cb_net2_800m", "net2pll", 1, 1),
-	FACTOR(CLK_TOP_CB_NET2_D2, "cb_net2_d2", "net2pll", 1, 2),
-	FACTOR(CLK_TOP_CB_NET2_D4, "cb_net2_d4", "net2pll", 1, 4),
-	FACTOR(CLK_TOP_NET2_D4_D2, "net2_d4_d2", "net2pll", 1, 8),
-	FACTOR(CLK_TOP_NET2_D4_D4, "net2_d4_d4", "net2pll", 1, 16),
-	FACTOR(CLK_TOP_CB_NET2_D6, "cb_net2_d6", "net2pll", 1, 6),
-	FACTOR(CLK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m", "wedmcupll", 1, 1),
-	FACTOR(CLK_TOP_CB_SGM_325M, "cb_sgm_325m", "sgmpll", 1, 1),
-	FACTOR(CLK_TOP_CKSQ_40M_D2, "cksq_40m_d2", "cb_cksq_40m", 1, 2),
-	FACTOR(CLK_TOP_CB_RTC_32K, "cb_rtc_32k", "cb_cksq_40m", 1, 1250),
-	FACTOR(CLK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", "cb_cksq_40m", 1, 1220),
-	FACTOR(CLK_TOP_USB_TX250M, "usb_tx250m", "cb_cksq_40m", 1, 1),
-	FACTOR(CLK_TOP_FAUD, "faud", "aud_sel", 1, 1),
-	FACTOR(CLK_TOP_NFI1X, "nfi1x", "nfi1x_sel", 1, 1),
-	FACTOR(CLK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", "cb_cksq_40m", 1, 1),
-	FACTOR(CLK_TOP_USB_CDR_CK, "usb_cdr", "cb_cksq_40m", 1, 1),
-	FACTOR(CLK_TOP_USB_LN0_CK, "usb_ln0", "cb_cksq_40m", 1, 1),
-	FACTOR(CLK_TOP_SPINFI_BCK, "spinfi_bck", "spinfi_sel", 1, 1),
-	FACTOR(CLK_TOP_SPI, "spi", "spi_sel", 1, 1),
-	FACTOR(CLK_TOP_SPIM_MST, "spim_mst", "spim_mst_sel", 1, 1),
-	FACTOR(CLK_TOP_UART_BCK, "uart_bck", "uart_sel", 1, 1),
-	FACTOR(CLK_TOP_PWM_BCK, "pwm_bck", "pwm_sel", 1, 1),
-	FACTOR(CLK_TOP_I2C_BCK, "i2c_bck", "i2c_sel", 1, 1),
-	FACTOR(CLK_TOP_PEXTP_TL, "pextp_tl", "pextp_tl_ck_sel", 1, 1),
-	FACTOR(CLK_TOP_EMMC_208M, "emmc_208m", "emmc_208m_sel", 1, 1),
-	FACTOR(CLK_TOP_EMMC_400M, "emmc_400m", "emmc_400m_sel", 1, 1),
-	FACTOR(CLK_TOP_DRAMC_REF, "dramc_ref", "dramc_sel", 1, 1),
-	FACTOR(CLK_TOP_DRAMC_MD32, "dramc_md32", "dramc_md32_sel", 1, 1),
-	FACTOR(CLK_TOP_SYSAXI, "sysaxi", "sysaxi_sel", 1, 1),
-	FACTOR(CLK_TOP_SYSAPB, "sysapb", "sysapb_sel", 1, 1),
-	FACTOR(CLK_TOP_ARM_DB_MAIN, "arm_db_main", "arm_db_main_sel", 1, 1),
-	FACTOR(CLK_TOP_AP2CNN_HOST, "ap2cnn_host", "ap2cnn_host_sel", 1, 1),
-	FACTOR(CLK_TOP_NETSYS, "netsys", "netsys_sel", 1, 1),
-	FACTOR(CLK_TOP_NETSYS_500M, "netsys_500m", "netsys_500m_sel", 1, 1),
-	FACTOR(CLK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu", "netsys_mcu_sel", 1, 1),
-	FACTOR(CLK_TOP_NETSYS_2X, "netsys_2x", "netsys_2x_sel", 1, 1),
-	FACTOR(CLK_TOP_SGM_325M, "sgm_325m", "sgm_325m_sel", 1, 1),
-	FACTOR(CLK_TOP_SGM_REG, "sgm_reg", "sgm_reg_sel", 1, 1),
-	FACTOR(CLK_TOP_F26M, "csw_f26m", "csw_f26m_sel", 1, 1),
-	FACTOR(CLK_TOP_EIP97B, "eip97b", "eip97b_sel", 1, 1),
-	FACTOR(CLK_TOP_USB3_PHY, "usb3_phy", "usb3_phy_sel", 1, 1),
-	FACTOR(CLK_TOP_AUD, "aud", "faud", 1, 1),
-	FACTOR(CLK_TOP_A1SYS, "a1sys", "a1sys_sel", 1, 1),
-	FACTOR(CLK_TOP_AUD_L, "aud_l", "aud_l_sel", 1, 1),
-	FACTOR(CLK_TOP_A_TUNER, "a_tuner", "a_tuner_sel", 1, 1),
-	FACTOR(CLK_TOP_U2U3_REF, "u2u3_ref", "u2u3_sel", 1, 1),
-	FACTOR(CLK_TOP_U2U3_SYS, "u2u3_sys", "u2u3_sys_sel", 1, 1),
-	FACTOR(CLK_TOP_U2U3_XHCI, "u2u3_xhci", "u2u3_xhci_sel", 1, 1),
-	FACTOR(CLK_TOP_USB_FRMCNT, "usb_frmcnt", "usb_frmcnt_sel", 1, 1),
-};
-
-static const char * const nfi1x_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_mm_d4",
-	"net1_d8_d2",
-	"cb_net2_d6",
-	"cb_m_d4",
-	"cb_mm_d8",
-	"net1_d8_d4",
-	"cb_m_d8"
-};
-
-static const char * const spinfi_parents[] __initconst = {
-	"cksq_40m_d2",
-	"cb_cksq_40m",
-	"net1_d5_d4",
-	"cb_m_d4",
-	"cb_mm_d8",
-	"net1_d8_d4",
-	"mm_d6_d2",
-	"cb_m_d8"
-};
-
-static const char * const spi_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_m_d2",
-	"cb_mm_d4",
-	"net1_d8_d2",
-	"cb_net2_d6",
-	"net1_d5_d4",
-	"cb_m_d4",
-	"net1_d8_d4"
-};
-
-static const char * const uart_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_m_d8",
-	"m_d8_d2"
-};
-
-static const char * const pwm_parents[] __initconst = {
-	"cb_cksq_40m",
-	"net1_d8_d2",
-	"net1_d5_d4",
-	"cb_m_d4",
-	"m_d8_d2",
-	"cb_rtc_32k"
-};
-
-static const char * const i2c_parents[] __initconst = {
-	"cb_cksq_40m",
-	"net1_d5_d4",
-	"cb_m_d4",
-	"net1_d8_d4"
-};
-
-static const char * const pextp_tl_ck_parents[] __initconst = {
-	"cb_cksq_40m",
-	"net1_d5_d4",
-	"cb_m_d4",
-	"cb_rtc_32k"
-};
-
-static const char * const emmc_208m_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_m_d2",
-	"cb_net2_d4",
-	"cb_apll2_196m",
-	"cb_mm_d4",
-	"net1_d8_d2",
-	"cb_mm_d6"
-};
-
-static const char * const emmc_400m_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_net2_d2",
-	"cb_mm_d2",
-	"cb_net2_d2"
-};
-
-static const char * const csw_f26m_parents[] __initconst = {
-	"cksq_40m_d2",
-	"m_d8_d2"
-};
-
-static const char * const dramc_md32_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_m_d2",
-	"cb_wedmcu_208m"
-};
-
-static const char * const sysaxi_parents[] __initconst = {
-	"cb_cksq_40m",
-	"net1_d8_d2"
-};
-
-static const char * const sysapb_parents[] __initconst = {
-	"cb_cksq_40m",
-	"m_d3_d2"
-};
-
-static const char * const arm_db_main_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_net2_d6"
-};
-
-static const char * const ap2cnn_host_parents[] __initconst = {
-	"cb_cksq_40m",
-	"net1_d8_d4"
-};
-
-static const char * const netsys_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_mm_d2"
-};
-
-static const char * const netsys_500m_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_net1_d5"
-};
-
-static const char * const netsys_mcu_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_mm_720m",
-	"cb_net1_d4",
-	"cb_net1_d5",
-	"cb_m_416m"
-};
-
-static const char * const netsys_2x_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_net2_800m",
-	"cb_mm_720m"
-};
-
-static const char * const sgm_325m_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_sgm_325m"
-};
-
-static const char * const sgm_reg_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_net2_d4"
-};
-
-static const char * const eip97b_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_net1_d5",
-	"cb_m_416m",
-	"cb_mm_d2",
-	"net1_d5_d2"
-};
-
-static const char * const aud_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_apll2_196m"
-};
-
-static const char * const a1sys_parents[] __initconst = {
-	"cb_cksq_40m",
-	"apll2_d4"
-};
-
-static const char * const aud_l_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_apll2_196m",
-	"m_d8_d2"
-};
-
-static const char * const a_tuner_parents[] __initconst = {
-	"cb_cksq_40m",
-	"apll2_d4",
-	"m_d8_d2"
-};
-
-static const char * const u2u3_parents[] __initconst = {
-	"cb_cksq_40m",
-	"m_d8_d2"
-};
-
-static const char * const u2u3_sys_parents[] __initconst = {
-	"cb_cksq_40m",
-	"net1_d5_d4"
-};
-
-static const char * const usb_frmcnt_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_mm_d3_d5"
-};
-
-static const struct mtk_mux top_muxes[] = {
-	/* CLK_CFG_0 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents,
-			     0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents,
-			     0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents,
-			     0x000, 0x004, 0x008, 16, 3, 23, 0x1C0, 2),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents,
-			     0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3),
-	/* CLK_CFG_1 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
-			     0x010, 0x014, 0x018, 0, 2, 7, 0x1C0, 4),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
-			     0x010, 0x014, 0x018, 8, 3, 15, 0x1C0, 5),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents,
-			     0x010, 0x014, 0x018, 16, 2, 23, 0x1C0, 6),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel",
-			     pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2, 31,
-			     0x1C0, 7),
-	/* CLK_CFG_2 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_208M_SEL, "emmc_208m_sel",
-			     emmc_208m_parents, 0x020, 0x024, 0x028, 0, 3, 7,
-			     0x1C0, 8),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel",
-			     emmc_400m_parents, 0x020, 0x024, 0x028, 8, 2, 15,
-			     0x1C0, 9),
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_F26M_SEL, "csw_f26m_sel",
-				   csw_f26m_parents, 0x020, 0x024, 0x028, 16, 1, 23,
-				   0x1C0, 10,
-				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel",
-				   csw_f26m_parents, 0x020, 0x024, 0x028, 24, 1,
-				   31, 0x1C0, 11,
-				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
-	/* CLK_CFG_3 */
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
-				   dramc_md32_parents, 0x030, 0x034, 0x038, 0, 2,
-				   7, 0x1C0, 12,
-				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel",
-				   sysaxi_parents, 0x030, 0x034, 0x038, 8, 1, 15,
-				   0x1C0, 13,
-				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel",
-				   sysapb_parents, 0x030, 0x034, 0x038, 16, 1,
-				   23, 0x1C0, 14,
-				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel",
-			     arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1, 31,
-			     0x1C0, 15),
-	/* CLK_CFG_4 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel",
-			     ap2cnn_host_parents, 0x040, 0x044, 0x048, 0, 1, 7,
-			     0x1C0, 16),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents,
-			     0x040, 0x044, 0x048, 8, 1, 15, 0x1C0, 17),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel",
-			     netsys_500m_parents, 0x040, 0x044, 0x048, 16, 1, 23,
-			     0x1C0, 18),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel",
-			     netsys_mcu_parents, 0x040, 0x044, 0x048, 24, 3, 31,
-			     0x1C0, 19),
-	/* CLK_CFG_5 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel",
-			     netsys_2x_parents, 0x050, 0x054, 0x058, 0, 2, 7,
-			     0x1C0, 20),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel",
-			     sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15,
-			     0x1C0, 21),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents,
-			     0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP97B_SEL, "eip97b_sel", eip97b_parents,
-			     0x050, 0x054, 0x058, 24, 3, 31, 0x1C0, 23),
-	/* CLK_CFG_6 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB3_PHY_SEL, "usb3_phy_sel",
-			     csw_f26m_parents, 0x060, 0x064, 0x068, 0, 1,
-			     7, 0x1C0, 24),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x060,
-			     0x064, 0x068, 8, 1, 15, 0x1C0, 25),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents,
-			     0x060, 0x064, 0x068, 16, 1, 23, 0x1C0, 26),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents,
-			     0x060, 0x064, 0x068, 24, 2, 31, 0x1C0, 27),
-	/* CLK_CFG_7 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel",
-			     a_tuner_parents, 0x070, 0x074, 0x078, 0, 2, 7,
-			     0x1C0, 28),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SEL, "u2u3_sel", u2u3_parents, 0x070,
-			     0x074, 0x078, 8, 1, 15, 0x1C0, 29),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel",
-			     u2u3_sys_parents, 0x070, 0x074, 0x078, 16, 1, 23,
-			     0x1C0, 30),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel",
-			     u2u3_sys_parents, 0x070, 0x074, 0x078, 24, 1, 31,
-			     0x1C4, 0),
-	/* CLK_CFG_8 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel",
-			     usb_frmcnt_parents, 0x080, 0x084, 0x088, 0, 1, 7,
-			     0x1C4, 1),
-};
-
-static struct mtk_composite top_aud_divs[] = {
-	DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud",
-		0x0420, 0, 0x0420, 8, 8),
-};
-
-static int clk_mt7981_topckgen_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-	void __iomem *base;
-	int nr = ARRAY_SIZE(top_divs) + ARRAY_SIZE(top_muxes) +
-		 ARRAY_SIZE(top_aud_divs);
-
-	base = of_iomap(node, 0);
-	if (!base) {
-		pr_err("%s(): ioremap failed\n", __func__);
-		return -ENOMEM;
-	}
-
-	clk_data = mtk_alloc_clk_data(nr);
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
-	mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node,
-			       &mt7981_clk_lock, clk_data);
-	mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs), base,
-                        &mt7981_clk_lock, clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_topckgen_data;
-	}
-	return r;
-
-free_topckgen_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
-
-static const struct of_device_id of_match_clk_mt7981_topckgen[] = {
-	{ .compatible = "mediatek,mt7981-topckgen", },
-	{}
-};
-
-static struct platform_driver clk_mt7981_topckgen_drv = {
-	.probe = clk_mt7981_topckgen_probe,
-	.driver = {
-		.name = "clk-mt7981-topckgen",
-		.of_match_table = of_match_clk_mt7981_topckgen,
-	},
-};
-builtin_platform_driver(clk_mt7981_topckgen_drv);
diff --git a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7986-apmixed.c b/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7986-apmixed.c
deleted file mode 100644
index 76c8ebdeae96dc..00000000000000
--- a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7986-apmixed.c
+++ /dev/null
@@ -1,100 +0,0 @@
-// SPDX-License-Identifier: GPL-1.0
-/*
- * Copyright (c) 2021 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include "clk-mtk.h"
-#include "clk-gate.h"
-#include "clk-mux.h"
-
-#include <dt-bindings/clock/mt7986-clk.h>
-#include <linux/clk.h>
-
-#define MT7986_PLL_FMAX (2500UL * MHZ)
-#define CON0_MT7986_RST_BAR BIT(27)
-
-#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,       \
-		 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift,         \
-		 _div_table, _parent_name)                                     \
-	{                                                                      \
-		.id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg,    \
-		.en_mask = _en_mask, .flags = _flags,                          \
-		.rst_bar_mask = CON0_MT7986_RST_BAR, .fmax = MT7986_PLL_FMAX,  \
-		.pcwbits = _pcwbits, .pd_reg = _pd_reg, .pd_shift = _pd_shift, \
-		.tuner_reg = _tuner_reg, .pcw_reg = _pcw_reg,                  \
-		.pcw_shift = _pcw_shift, .div_table = _div_table,              \
-		.parent_name = _parent_name,                                   \
-	}
-
-#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg,   \
-	    _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift)                       \
-	PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,       \
-		 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, NULL,   \
-		 "clkxtal")
-
-static const struct mtk_pll_data plls[] = {
-	PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, 0, 32,
-	    0x0200, 4, 0, 0x0204, 0),
-	PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x00000001, 0, 32,
-	    0x0210, 4, 0, 0x0214, 0),
-	PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x00000001, 0, 32,
-	    0x0220, 4, 0, 0x0224, 0),
-	PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023c, 0x00000001, 0, 32,
-	    0x0230, 4, 0, 0x0234, 0),
-	PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024c, 0x00000001, 0,
-	    32, 0x0240, 4, 0, 0x0244, 0),
-	PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0250, 0x025c, 0x00000001, 0, 32,
-	    0x0250, 4, 0, 0x0254, 0),
-	PLL(CLK_APMIXED_MPLL, "mpll", 0x0260, 0x0270, 0x00000001, 0, 32, 0x0260,
-	    4, 0, 0x0264, 0),
-	PLL(CLK_APMIXED_APLL2, "apll2", 0x0278, 0x0288, 0x00000001, 0, 32,
-	    0x0278, 4, 0, 0x027c, 0),
-};
-
-static const struct of_device_id of_match_clk_mt7986_apmixed[] = {
-	{ .compatible = "mediatek,mt7986-apmixedsys", },
-	{}
-};
-
-static int clk_mt7986_apmixed_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
-
-	clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMPLL]);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_apmixed_data;
-	}
-	return r;
-
-free_apmixed_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
-
-static struct platform_driver clk_mt7986_apmixed_drv = {
-	.probe = clk_mt7986_apmixed_probe,
-	.driver = {
-		.name = "clk-mt7986-apmixed",
-		.of_match_table = of_match_clk_mt7986_apmixed,
-	},
-};
-builtin_platform_driver(clk_mt7986_apmixed_drv);
diff --git a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7986-eth.c b/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7986-eth.c
deleted file mode 100644
index ed2e7b20098770..00000000000000
--- a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7986-eth.c
+++ /dev/null
@@ -1,132 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2021 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-
-#include "clk-mtk.h"
-#include "clk-gate.h"
-
-#include <dt-bindings/clock/mt7986-clk.h>
-
-static const struct mtk_gate_regs sgmii0_cg_regs = {
-	.set_ofs = 0xe4,
-	.clr_ofs = 0xe4,
-	.sta_ofs = 0xe4,
-};
-
-#define GATE_SGMII0(_id, _name, _parent, _shift)                               \
-	{                                                                      \
-		.id = _id, .name = _name, .parent_name = _parent,              \
-		.regs = &sgmii0_cg_regs, .shift = _shift,                      \
-		.ops = &mtk_clk_gate_ops_no_setclr_inv,                        \
-	}
-
-static const struct mtk_gate sgmii0_clks[] __initconst = {
-	GATE_SGMII0(CLK_SGMII0_TX250M_EN, "sgmii0_tx250m_en", "top_xtal", 2),
-	GATE_SGMII0(CLK_SGMII0_RX250M_EN, "sgmii0_rx250m_en", "top_xtal", 3),
-	GATE_SGMII0(CLK_SGMII0_CDR_REF, "sgmii0_cdr_ref", "top_xtal", 4),
-	GATE_SGMII0(CLK_SGMII0_CDR_FB, "sgmii0_cdr_fb", "top_xtal", 5),
-};
-
-static const struct mtk_gate_regs sgmii1_cg_regs = {
-	.set_ofs = 0xe4,
-	.clr_ofs = 0xe4,
-	.sta_ofs = 0xe4,
-};
-
-#define GATE_SGMII1(_id, _name, _parent, _shift)                               \
-	{                                                                      \
-		.id = _id, .name = _name, .parent_name = _parent,              \
-		.regs = &sgmii1_cg_regs, .shift = _shift,                      \
-		.ops = &mtk_clk_gate_ops_no_setclr_inv,                        \
-	}
-
-static const struct mtk_gate sgmii1_clks[] __initconst = {
-	GATE_SGMII1(CLK_SGMII1_TX250M_EN, "sgmii1_tx250m_en", "top_xtal", 2),
-	GATE_SGMII1(CLK_SGMII1_RX250M_EN, "sgmii1_rx250m_en", "top_xtal", 3),
-	GATE_SGMII1(CLK_SGMII1_CDR_REF, "sgmii1_cdr_ref", "top_xtal", 4),
-	GATE_SGMII1(CLK_SGMII1_CDR_FB, "sgmii1_cdr_fb", "top_xtal", 5),
-};
-
-static const struct mtk_gate_regs eth_cg_regs = {
-	.set_ofs = 0x30,
-	.clr_ofs = 0x30,
-	.sta_ofs = 0x30,
-};
-
-#define GATE_ETH(_id, _name, _parent, _shift)                                  \
-	{                                                                      \
-		.id = _id, .name = _name, .parent_name = _parent,              \
-		.regs = &eth_cg_regs, .shift = _shift,                         \
-		.ops = &mtk_clk_gate_ops_no_setclr_inv,                        \
-	}
-
-static const struct mtk_gate eth_clks[] __initconst = {
-	GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "netsys_2x_sel", 6),
-	GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "sgm_325m_sel", 7),
-	GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "sgm_325m_sel", 8),
-	GATE_ETH(CLK_ETH_WOCPU1_EN, "eth_wocpu1_en", "netsys_mcu_sel", 14),
-	GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", "netsys_mcu_sel", 15),
-};
-
-static void __init mtk_sgmiisys_0_init(struct device_node *node)
-{
-	struct clk_onecell_data *clk_data;
-	int r;
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks));
-
-	mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks),
-			       clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-	if (r)
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-}
-CLK_OF_DECLARE(mtk_sgmiisys_0, "mediatek,mt7986-sgmiisys_0",
-	       mtk_sgmiisys_0_init);
-
-static void __init mtk_sgmiisys_1_init(struct device_node *node)
-{
-	struct clk_onecell_data *clk_data;
-	int r;
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks));
-
-	mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks),
-			       clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-
-	if (r)
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-}
-CLK_OF_DECLARE(mtk_sgmiisys_1, "mediatek,mt7986-sgmiisys_1",
-	       mtk_sgmiisys_1_init);
-
-static void __init mtk_ethsys_init(struct device_node *node)
-{
-	struct clk_onecell_data *clk_data;
-	int r;
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(eth_clks));
-
-	mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-
-	if (r)
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-}
-CLK_OF_DECLARE(mtk_ethsys, "mediatek,mt7986-ethsys", mtk_ethsys_init);
diff --git a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7986-infracfg.c b/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7986-infracfg.c
deleted file mode 100644
index 82279dfcf57137..00000000000000
--- a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7986-infracfg.c
+++ /dev/null
@@ -1,224 +0,0 @@
-// SPDX-License-Identifier: GPL-1.0
-/*
- * Copyright (c) 2021 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include "clk-mtk.h"
-#include "clk-gate.h"
-#include "clk-mux.h"
-
-#include <dt-bindings/clock/mt7986-clk.h>
-#include <linux/clk.h>
-
-static DEFINE_SPINLOCK(mt7986_clk_lock);
-
-static const struct mtk_fixed_factor infra_divs[] = {
-	FACTOR(CLK_INFRA_SYSAXI_D2, "infra_sysaxi_d2", "sysaxi_sel", 1, 2),
-};
-
-static const char *const infra_uart_parent[] __initconst = { "csw_f26m_sel",
-							     "uart_sel" };
-
-static const char *const infra_spi_parents[] __initconst = { "i2c_sel",
-							     "spi_sel" };
-
-static const char *const infra_pwm_bsel_parents[] __initconst = {
-	"top_rtc_32p7k", "csw_f26m_sel", "infra_sysaxi_d2", "pwm_sel"
-};
-
-static const char *const infra_pcie_parents[] __initconst = {
-	"top_rtc_32p7k", "csw_f26m_sel", "top_xtal", "pextp_tl_ck_sel"
-};
-
-static const struct mtk_mux infra_muxes[] = {
-	/* MODULE_CLK_SEL_0 */
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART0_SEL, "infra_uart0_sel",
-			     infra_uart_parent, 0x0018, 0x0010, 0x0014, 0, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART1_SEL, "infra_uart1_sel",
-			     infra_uart_parent, 0x0018, 0x0010, 0x0014, 1, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART2_SEL, "infra_uart2_sel",
-			     infra_uart_parent, 0x0018, 0x0010, 0x0014, 2, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI0_SEL, "infra_spi0_sel",
-			     infra_spi_parents, 0x0018, 0x0010, 0x0014, 4, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI1_SEL, "infra_spi1_sel",
-			     infra_spi_parents, 0x0018, 0x0010, 0x0014, 5, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel",
-			     infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 9,
-			     2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel",
-			     infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 11,
-			     2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_BSEL, "infra_pwm_bsel",
-			     infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 13,
-			     2, -1, -1, -1),
-	/* MODULE_CLK_SEL_1 */
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_SEL, "infra_pcie_sel",
-			     infra_pcie_parents, 0x0028, 0x0020, 0x0024, 0, 2,
-			     -1, -1, -1),
-};
-
-static const struct mtk_gate_regs infra0_cg_regs = {
-	.set_ofs = 0x40,
-	.clr_ofs = 0x44,
-	.sta_ofs = 0x48,
-};
-
-static const struct mtk_gate_regs infra1_cg_regs = {
-	.set_ofs = 0x50,
-	.clr_ofs = 0x54,
-	.sta_ofs = 0x58,
-};
-
-static const struct mtk_gate_regs infra2_cg_regs = {
-	.set_ofs = 0x60,
-	.clr_ofs = 0x64,
-	.sta_ofs = 0x68,
-};
-
-#define GATE_INFRA0(_id, _name, _parent, _shift)                               \
-	{                                                                      \
-		.id = _id, .name = _name, .parent_name = _parent,              \
-		.regs = &infra0_cg_regs, .shift = _shift,                      \
-		.ops = &mtk_clk_gate_ops_setclr,                               \
-	}
-
-#define GATE_INFRA1(_id, _name, _parent, _shift)                               \
-	{                                                                      \
-		.id = _id, .name = _name, .parent_name = _parent,              \
-		.regs = &infra1_cg_regs, .shift = _shift,                      \
-		.ops = &mtk_clk_gate_ops_setclr,                               \
-	}
-
-#define GATE_INFRA2(_id, _name, _parent, _shift)                               \
-	{                                                                      \
-		.id = _id, .name = _name, .parent_name = _parent,              \
-		.regs = &infra2_cg_regs, .shift = _shift,                      \
-		.ops = &mtk_clk_gate_ops_setclr,                               \
-	}
-
-static const struct mtk_gate infra_clks[] = {
-	/* INFRA0 */
-	GATE_INFRA0(CLK_INFRA_GPT_STA, "infra_gpt_sta", "infra_sysaxi_d2", 0),
-	GATE_INFRA0(CLK_INFRA_PWM_HCK, "infra_pwm_hck", "infra_sysaxi_d2", 1),
-	GATE_INFRA0(CLK_INFRA_PWM_STA, "infra_pwm_sta", "infra_pwm_bsel", 2),
-	GATE_INFRA0(CLK_INFRA_PWM1_CK, "infra_pwm1", "infra_pwm1_sel", 3),
-	GATE_INFRA0(CLK_INFRA_PWM2_CK, "infra_pwm2", "infra_pwm2_sel", 4),
-	GATE_INFRA0(CLK_INFRA_CQ_DMA_CK, "infra_cq_dma", "sysaxi_sel", 6),
-	GATE_INFRA0(CLK_INFRA_EIP97_CK, "infra_eip97", "eip_b_sel", 7),
-	GATE_INFRA0(CLK_INFRA_AUD_BUS_CK, "infra_aud_bus", "sysaxi_sel", 8),
-	GATE_INFRA0(CLK_INFRA_AUD_26M_CK, "infra_aud_26m", "csw_f26m_sel", 9),
-	GATE_INFRA0(CLK_INFRA_AUD_L_CK, "infra_aud_l", "aud_l_sel", 10),
-	GATE_INFRA0(CLK_INFRA_AUD_AUD_CK, "infra_aud_aud", "a1sys_sel", 11),
-	GATE_INFRA0(CLK_INFRA_AUD_EG2_CK, "infra_aud_eg2", "a_tuner_sel", 13),
-	GATE_INFRA0(CLK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", "csw_f26m_sel",
-		    14),
-	GATE_INFRA0(CLK_INFRA_DBG_CK, "infra_dbg", "infra_sysaxi_d2", 15),
-	GATE_INFRA0(CLK_INFRA_AP_DMA_CK, "infra_ap_dma", "infra_sysaxi_d2", 16),
-	GATE_INFRA0(CLK_INFRA_SEJ_CK, "infra_sej", "infra_sysaxi_d2", 24),
-	GATE_INFRA0(CLK_INFRA_SEJ_13M_CK, "infra_sej_13m", "csw_f26m_sel", 25),
-	GATE_INFRA0(CLK_INFRA_TRNG_CK, "infra_trng", "sysaxi_sel", 26),
-	/* INFRA1 */
-	GATE_INFRA1(CLK_INFRA_THERM_CK, "infra_therm", "csw_f26m_sel", 0),
-	GATE_INFRA1(CLK_INFRA_I2C0_CK, "infra_i2c0", "i2c_sel", 1),
-	GATE_INFRA1(CLK_INFRA_UART0_CK, "infra_uart0", "infra_uart0_sel", 2),
-	GATE_INFRA1(CLK_INFRA_UART1_CK, "infra_uart1", "infra_uart1_sel", 3),
-	GATE_INFRA1(CLK_INFRA_UART2_CK, "infra_uart2", "infra_uart2_sel", 4),
-	GATE_INFRA1(CLK_INFRA_NFI1_CK, "infra_nfi1", "nfi1x_sel", 8),
-	GATE_INFRA1(CLK_INFRA_SPINFI1_CK, "infra_spinfi1", "spinfi_sel", 9),
-	GATE_INFRA1(CLK_INFRA_NFI_HCK_CK, "infra_nfi_hck", "infra_sysaxi_d2",
-		    10),
-	GATE_INFRA1(CLK_INFRA_SPI0_CK, "infra_spi0", "infra_spi0_sel", 11),
-	GATE_INFRA1(CLK_INFRA_SPI1_CK, "infra_spi1", "infra_spi1_sel", 12),
-	GATE_INFRA1(CLK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", "infra_sysaxi_d2",
-		    13),
-	GATE_INFRA1(CLK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", "infra_sysaxi_d2",
-		    14),
-	GATE_INFRA1(CLK_INFRA_FRTC_CK, "infra_frtc", "top_rtc_32k", 15),
-	GATE_INFRA1(CLK_INFRA_MSDC_CK, "infra_msdc", "emmc_416m_sel", 16),
-	GATE_INFRA1(CLK_INFRA_MSDC_HCK_CK, "infra_msdc_hck", "emmc_250m_sel",
-		    17),
-	GATE_INFRA1(CLK_INFRA_MSDC_133M_CK, "infra_msdc_133m", "sysaxi_sel",
-		    18),
-	GATE_INFRA1(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", "infra_sysaxi_d2",
-		    19),
-	GATE_INFRA1(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", "infra_adc_frc", 20),
-	GATE_INFRA1(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", "csw_f26m_sel", 21),
-	GATE_INFRA1(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", "nfi1x_sel", 23),
-	/* INFRA2 */
-	GATE_INFRA2(CLK_INFRA_IUSB_133_CK, "infra_iusb_133", "sysaxi_sel", 0),
-	GATE_INFRA2(CLK_INFRA_IUSB_66M_CK, "infra_iusb_66m", "infra_sysaxi_d2",
-		    1),
-	GATE_INFRA2(CLK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", "u2u3_sys_sel", 2),
-	GATE_INFRA2(CLK_INFRA_IUSB_CK, "infra_iusb", "u2u3_sel", 3),
-	GATE_INFRA2(CLK_INFRA_IPCIE_CK, "infra_ipcie", "pextp_tl_ck_sel", 12),
-	GATE_INFRA2(CLK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", "top_xtal",
-		    13),
-	GATE_INFRA2(CLK_INFRA_IPCIER_CK, "infra_ipcier", "csw_f26m_sel", 14),
-	GATE_INFRA2(CLK_INFRA_IPCIEB_CK, "infra_ipcieb", "sysaxi_sel", 15),
-};
-
-static int clk_mt7986_infracfg_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-	void __iomem *base;
-	int nr = ARRAY_SIZE(infra_divs) + ARRAY_SIZE(infra_muxes) +
-		 ARRAY_SIZE(infra_clks);
-
-	base = of_iomap(node, 0);
-	if (!base) {
-		pr_err("%s(): ioremap failed\n", __func__);
-		return -ENOMEM;
-	}
-
-	clk_data = mtk_alloc_clk_data(nr);
-
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
-	mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node,
-			       &mt7986_clk_lock, clk_data);
-	mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
-			       clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_infracfg_data;
-	}
-	return r;
-
-free_infracfg_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-
-}
-
-static const struct of_device_id of_match_clk_mt7986_infracfg[] = {
-	{ .compatible = "mediatek,mt7986-infracfg", },
-	{}
-};
-
-static struct platform_driver clk_mt7986_infracfg_drv = {
-	.probe = clk_mt7986_infracfg_probe,
-	.driver = {
-		.name = "clk-mt7986-infracfg",
-		.of_match_table = of_match_clk_mt7986_infracfg,
-	},
-};
-builtin_platform_driver(clk_mt7986_infracfg_drv);
diff --git a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7986-topckgen.c b/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7986-topckgen.c
deleted file mode 100644
index 8550e2be7773db..00000000000000
--- a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7986-topckgen.c
+++ /dev/null
@@ -1,342 +0,0 @@
-// SPDX-License-Identifier: GPL-1.0
-/*
- * Copyright (c) 2021 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include "clk-mtk.h"
-#include "clk-gate.h"
-#include "clk-mux.h"
-
-#include <dt-bindings/clock/mt7986-clk.h>
-#include <linux/clk.h>
-
-static DEFINE_SPINLOCK(mt7986_clk_lock);
-
-static const struct mtk_fixed_clk top_fixed_clks[] = {
-	FIXED_CLK(CLK_TOP_XTAL, "top_xtal", "clkxtal", 40000000),
-	FIXED_CLK(CLK_TOP_JTAG, "top_jtag", "clkxtal", 50000000),
-};
-
-static const struct mtk_fixed_factor top_divs[] = {
-	/* XTAL */
-	FACTOR(CLK_TOP_XTAL_D2, "top_xtal_d2", "top_xtal", 1, 2),
-	FACTOR(CLK_TOP_RTC_32K, "top_rtc_32k", "top_xtal", 1, 1250),
-	FACTOR(CLK_TOP_RTC_32P7K, "top_rtc_32p7k", "top_xtal", 1, 1220),
-	/* MPLL */
-	FACTOR(CLK_TOP_MPLL_D2, "top_mpll_d2", "mpll", 1, 2),
-	FACTOR(CLK_TOP_MPLL_D4, "top_mpll_d4", "mpll", 1, 4),
-	FACTOR(CLK_TOP_MPLL_D8, "top_mpll_d8", "mpll", 1, 8),
-	FACTOR(CLK_TOP_MPLL_D8_D2, "top_mpll_d8_d2", "mpll", 1, 16),
-	FACTOR(CLK_TOP_MPLL_D3_D2, "top_mpll_d3_d2", "mpll", 1, 6),
-	/* MMPLL */
-	FACTOR(CLK_TOP_MMPLL_D2, "top_mmpll_d2", "mmpll", 1, 2),
-	FACTOR(CLK_TOP_MMPLL_D4, "top_mmpll_d4", "mmpll", 1, 4),
-	FACTOR(CLK_TOP_MMPLL_D8, "top_mmpll_d8", "mmpll", 1, 8),
-	FACTOR(CLK_TOP_MMPLL_D8_D2, "top_mmpll_d8_d2", "mmpll", 1, 16),
-	FACTOR(CLK_TOP_MMPLL_D3_D8, "top_mmpll_d3_d8", "mmpll", 1, 24),
-	FACTOR(CLK_TOP_MMPLL_U2PHY, "top_mmpll_u2phy", "mmpll", 1, 30),
-	/* APLL2 */
-	FACTOR(CLK_TOP_APLL2_D4, "top_apll2_d4", "apll2", 1, 4),
-	/* NET1PLL */
-	FACTOR(CLK_TOP_NET1PLL_D4, "top_net1pll_d4", "net1pll", 1, 4),
-	FACTOR(CLK_TOP_NET1PLL_D5, "top_net1pll_d5", "net1pll", 1, 5),
-	FACTOR(CLK_TOP_NET1PLL_D5_D2, "top_net1pll_d5_d2", "net1pll", 1, 10),
-	FACTOR(CLK_TOP_NET1PLL_D5_D4, "top_net1pll_d5_d4", "net1pll", 1, 20),
-	FACTOR(CLK_TOP_NET1PLL_D8_D2, "top_net1pll_d8_d2", "net1pll", 1, 16),
-	FACTOR(CLK_TOP_NET1PLL_D8_D4, "top_net1pll_d8_d4", "net1pll", 1, 32),
-	/* NET2PLL */
-	FACTOR(CLK_TOP_NET2PLL_D4, "top_net2pll_d4", "net2pll", 1, 4),
-	FACTOR(CLK_TOP_NET2PLL_D4_D2, "top_net2pll_d4_d2", "net2pll", 1, 8),
-	FACTOR(CLK_TOP_NET2PLL_D3_D2, "top_net2pll_d3_d2", "net2pll", 1, 2),
-	/* WEDMCUPLL */
-	FACTOR(CLK_TOP_WEDMCUPLL_D5_D2, "top_wedmcupll_d5_d2", "wedmcupll", 1,
-	       10),
-};
-
-static const char *const nfi1x_parents[] __initconst = { "top_xtal",
-							 "top_mmpll_d8",
-							 "top_net1pll_d8_d2",
-							 "top_net2pll_d3_d2",
-							 "top_mpll_d4",
-							 "top_mmpll_d8_d2",
-							 "top_wedmcupll_d5_d2",
-							 "top_mpll_d8" };
-
-static const char *const spinfi_parents[] __initconst = {
-	"top_xtal_d2",     "top_xtal",	"top_net1pll_d5_d4",
-	"top_mpll_d4",     "top_mmpll_d8_d2", "top_wedmcupll_d5_d2",
-	"top_mmpll_d3_d8", "top_mpll_d8"
-};
-
-static const char *const spi_parents[] __initconst = {
-	"top_xtal",	  "top_mpll_d2",	"top_mmpll_d8",
-	"top_net1pll_d8_d2", "top_net2pll_d3_d2",  "top_net1pll_d5_d4",
-	"top_mpll_d4",       "top_wedmcupll_d5_d2"
-};
-
-static const char *const uart_parents[] __initconst = { "top_xtal",
-							"top_mpll_d8",
-							"top_mpll_d8_d2" };
-
-static const char *const pwm_parents[] __initconst = {
-	"top_xtal", "top_net1pll_d8_d2", "top_net1pll_d5_d4", "top_mpll_d4"
-};
-
-static const char *const i2c_parents[] __initconst = {
-	"top_xtal", "top_net1pll_d5_d4", "top_mpll_d4", "top_net1pll_d8_d4"
-};
-
-static const char *const pextp_tl_ck_parents[] __initconst = {
-	"top_xtal", "top_net1pll_d5_d4", "top_net2pll_d4_d2", "top_rtc_32k"
-};
-
-static const char *const emmc_250m_parents[] __initconst = {
-	"top_xtal", "top_net1pll_d5_d2"
-};
-
-static const char *const emmc_416m_parents[] __initconst = { "top_xtal",
-							     "mpll" };
-
-static const char *const f_26m_adc_parents[] __initconst = { "top_xtal",
-							     "top_mpll_d8_d2" };
-
-static const char *const dramc_md32_parents[] __initconst = { "top_xtal",
-							      "top_mpll_d2" };
-
-static const char *const sysaxi_parents[] __initconst = { "top_xtal",
-							  "top_net1pll_d8_d2",
-							  "top_net2pll_d4" };
-
-static const char *const sysapb_parents[] __initconst = { "top_xtal",
-							  "top_mpll_d3_d2",
-							  "top_net2pll_d4_d2" };
-
-static const char *const arm_db_main_parents[] __initconst = {
-	"top_xtal", "top_net2pll_d3_d2"
-};
-
-static const char *const arm_db_jtsel_parents[] __initconst = { "top_jtag",
-								"top_xtal" };
-
-static const char *const netsys_parents[] __initconst = { "top_xtal",
-							  "top_mmpll_d4" };
-
-static const char *const netsys_500m_parents[] __initconst = {
-	"top_xtal", "top_net1pll_d5"
-};
-
-static const char *const netsys_mcu_parents[] __initconst = {
-	"top_xtal", "wedmcupll", "top_mmpll_d2", "top_net1pll_d4",
-	"top_net1pll_d5"
-};
-
-static const char *const netsys_2x_parents[] __initconst = {
-	"top_xtal", "net2pll", "wedmcupll", "top_mmpll_d2"
-};
-
-static const char *const sgm_325m_parents[] __initconst = { "top_xtal",
-							    "sgmpll" };
-
-static const char *const sgm_reg_parents[] __initconst = {
-	"top_xtal", "top_net1pll_d8_d4"
-};
-
-static const char *const a1sys_parents[] __initconst = { "top_xtal",
-							 "top_apll2_d4" };
-
-static const char *const conn_mcusys_parents[] __initconst = { "top_xtal",
-							       "top_mmpll_d2" };
-
-static const char *const eip_b_parents[] __initconst = { "top_xtal",
-							 "net2pll" };
-
-static const char *const aud_l_parents[] __initconst = { "top_xtal", "apll2",
-							 "top_mpll_d8_d2" };
-
-static const char *const a_tuner_parents[] __initconst = { "top_xtal",
-							   "top_apll2_d4",
-							   "top_mpll_d8_d2" };
-
-static const char *const u2u3_sys_parents[] __initconst = {
-	"top_xtal", "top_net1pll_d5_d4"
-};
-
-static const char *const da_u2_refsel_parents[] __initconst = {
-	"top_xtal", "top_mmpll_u2phy"
-};
-
-static const struct mtk_mux top_muxes[] = {
-	/* CLK_CFG_0 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents,
-			     0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents,
-			     0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x000,
-			     0x004, 0x008, 16, 3, 23, 0x1C0, 2),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents,
-			     0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3),
-	/* CLK_CFG_1 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010,
-			     0x014, 0x018, 0, 2, 7, 0x1C0, 4),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010,
-			     0x014, 0x018, 8, 2, 15, 0x1C0, 5),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x010,
-			     0x014, 0x018, 16, 2, 23, 0x1C0, 6),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel",
-			     pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2,
-			     31, 0x1C0, 7),
-	/* CLK_CFG_2 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel",
-			     emmc_250m_parents, 0x020, 0x024, 0x028, 0, 1, 7,
-			     0x1C0, 8),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_416M_SEL, "emmc_416m_sel",
-			     emmc_416m_parents, 0x020, 0x024, 0x028, 8, 1, 15,
-			     0x1C0, 9),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel",
-			     f_26m_adc_parents, 0x020, 0x024, 0x028, 16, 1, 23,
-			     0x1C0, 10),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_SEL, "dramc_sel", f_26m_adc_parents,
-			     0x020, 0x024, 0x028, 24, 1, 31, 0x1C0, 11),
-	/* CLK_CFG_3 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
-			     dramc_md32_parents, 0x030, 0x034, 0x038, 0, 1, 7,
-			     0x1C0, 12),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents,
-			     0x030, 0x034, 0x038, 8, 2, 15, 0x1C0, 13),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents,
-			     0x030, 0x034, 0x038, 16, 2, 23, 0x1C0, 14),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel",
-			     arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1,
-			     31, 0x1C0, 15),
-	/* CLK_CFG_4 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_JTSEL, "arm_db_jtsel",
-			     arm_db_jtsel_parents, 0x040, 0x044, 0x048, 0, 1, 7,
-			     0x1C0, 16),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents,
-			     0x040, 0x044, 0x048, 8, 1, 15, 0x1C0, 17),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel",
-			     netsys_500m_parents, 0x040, 0x044, 0x048, 16, 1,
-			     23, 0x1C0, 18),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel",
-			     netsys_mcu_parents, 0x040, 0x044, 0x048, 24, 3, 31,
-			     0x1C0, 19),
-	/* CLK_CFG_5 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel",
-			     netsys_2x_parents, 0x050, 0x054, 0x058, 0, 2, 7,
-			     0x1C0, 20),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel",
-			     sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15,
-			     0x1C0, 21),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel",
-			     sgm_reg_parents, 0x050, 0x054, 0x058, 16, 1, 23,
-			     0x1C0, 22),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents,
-			     0x050, 0x054, 0x058, 24, 1, 31, 0x1C0, 23),
-	/* CLK_CFG_6 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_CONN_MCUSYS_SEL, "conn_mcusys_sel",
-			     conn_mcusys_parents, 0x060, 0x064, 0x068, 0, 1, 7,
-			     0x1C0, 24),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP_B_SEL, "eip_b_sel", eip_b_parents,
-			     0x060, 0x064, 0x068, 8, 1, 15, 0x1C0, 25),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PCIE_PHY_SEL, "pcie_phy_sel",
-			     f_26m_adc_parents, 0x060, 0x064, 0x068, 16, 1, 23,
-			     0x1C0, 26),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB3_PHY_SEL, "usb3_phy_sel",
-			     f_26m_adc_parents, 0x060, 0x064, 0x068, 24, 1, 31,
-			     0x1C0, 27),
-	/* CLK_CFG_7 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_F26M_SEL, "csw_f26m_sel",
-			     f_26m_adc_parents, 0x070, 0x074, 0x078, 0, 1, 7,
-			     0x1C0, 28),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents,
-			     0x070, 0x074, 0x078, 8, 2, 15, 0x1C0, 29),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel",
-			     a_tuner_parents, 0x070, 0x074, 0x078, 16, 2, 23,
-			     0x1C0, 30),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SEL, "u2u3_sel", f_26m_adc_parents,
-			     0x070, 0x074, 0x078, 24, 1, 31, 0x1C4, 0),
-	/* CLK_CFG_8 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel",
-			     u2u3_sys_parents, 0x080, 0x084, 0x088, 0, 1, 7,
-			     0x1C4, 1),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel",
-			     u2u3_sys_parents, 0x080, 0x084, 0x088, 8, 1, 15,
-			     0x1C4, 2),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_U2_REFSEL, "da_u2_refsel",
-			     da_u2_refsel_parents, 0x080, 0x084, 0x088, 16, 1,
-			     23, 0x1C4, 3),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_U2_CK_1P_SEL, "da_u2_ck_1p_sel",
-			     da_u2_refsel_parents, 0x080, 0x084, 0x088, 24, 1,
-			     31, 0x1C4, 4),
-	/* CLK_CFG_9 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel",
-			     sgm_reg_parents, 0x090, 0x094, 0x098, 0, 1, 7,
-			     0x1C4, 5),
-};
-
-static int clk_mt7986_topckgen_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-	void __iomem *base;
-	int nr = ARRAY_SIZE(top_fixed_clks) + ARRAY_SIZE(top_divs) +
-		 ARRAY_SIZE(top_muxes);
-
-	base = of_iomap(node, 0);
-	if (!base) {
-		pr_err("%s(): ioremap failed\n", __func__);
-		return -ENOMEM;
-	}
-
-	clk_data = mtk_alloc_clk_data(nr);
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
-				    clk_data);
-	mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
-	mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node,
-			       &mt7986_clk_lock, clk_data);
-
-	clk_prepare_enable(clk_data->clks[CLK_TOP_SYSAXI_SEL]);
-	clk_prepare_enable(clk_data->clks[CLK_TOP_SYSAPB_SEL]);
-	clk_prepare_enable(clk_data->clks[CLK_TOP_DRAMC_SEL]);
-	clk_prepare_enable(clk_data->clks[CLK_TOP_DRAMC_MD32_SEL]);
-	clk_prepare_enable(clk_data->clks[CLK_TOP_F26M_SEL]);
-	clk_prepare_enable(clk_data->clks[CLK_TOP_SGM_REG_SEL]);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_topckgen_data;
-	}
-	return r;
-
-free_topckgen_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
-
-static const struct of_device_id of_match_clk_mt7986_topckgen[] = {
-	{ .compatible = "mediatek,mt7986-topckgen", },
-	{}
-};
-
-static struct platform_driver clk_mt7986_topckgen_drv = {
-	.probe = clk_mt7986_topckgen_probe,
-	.driver = {
-		.name = "clk-mt7986-topckgen",
-		.of_match_table = of_match_clk_mt7986_topckgen,
-	},
-};
-builtin_platform_driver(clk_mt7986_topckgen_drv);
diff --git a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-apmixed.c b/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-apmixed.c
deleted file mode 100644
index 587b70767eb21e..00000000000000
--- a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-apmixed.c
+++ /dev/null
@@ -1,113 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2023 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include "clk-mtk.h"
-#include "clk-gate.h"
-#include "clk-mux.h"
-#include <dt-bindings/clock/mediatek,mt7988-clk.h>
-
-#define MT7988_PLL_FMAX (2500UL * MHZ)
-#define MT7988_PCW_CHG_SHIFT 2
-
-#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \
-		 _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg,     \
-		 _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg,           \
-		 _div_table)                                                  \
-	{                                                                     \
-		.id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg,   \
-		.en_mask = _en_mask, .flags = _flags,                         \
-		.rst_bar_mask = BIT(_rst_bar_mask), .fmax = MT7988_PLL_FMAX,  \
-		.pcwbits = _pcwbits, .pd_reg = _pd_reg,                       \
-		.pd_shift = _pd_shift, .tuner_reg = _tuner_reg,               \
-		.tuner_en_reg = _tuner_en_reg, .tuner_en_bit = _tuner_en_bit, \
-		.pcw_reg = _pcw_reg, .pcw_shift = _pcw_shift,                 \
-		.pcw_chg_reg = _pcw_chg_reg,                                  \
-		.pcw_chg_shift = MT7988_PCW_CHG_SHIFT,                        \
-		.div_table = _div_table, .parent_name = "clkxtal",            \
-	}
-
-#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask,      \
-	    _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg,          \
-	    _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg)                \
-	PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \
-		 _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg,     \
-		 _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg, NULL)
-
-static const struct mtk_pll_data plls[] = {
-	PLL(CLK_APMIXED_NETSYSPLL, "netsyspll", 0x0104, 0x0110, 0x00000001, 0,
-	    0, 32, 0x0104, 4, 0, 0, 0, 0x0108, 0, 0x0104),
-	PLL(CLK_APMIXED_MPLL, "mpll", 0x0114, 0x0120, 0xff000001, HAVE_RST_BAR,
-	    23, 32, 0x0114, 4, 0, 0, 0, 0x0118, 0, 0x0114),
-	PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0124, 0x0130, 0xff000001,
-	    HAVE_RST_BAR, 23, 32, 0x0124, 4, 0, 0, 0, 0x0128, 0, 0x0124),
-	PLL(CLK_APMIXED_APLL2, "apll2", 0x0134, 0x0140, 0x00000001, 0, 0, 32,
-	    0x0134, 4, 0x0704, 0x0700, 1, 0x0138, 0, 0x0134),
-	PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0144, 0x0150, 0xff000001,
-	    HAVE_RST_BAR, 23, 32, 0x0144, 4, 0, 0, 0, 0x0148, 0, 0x0144),
-	PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0154, 0x0160, 0xff000001,
-	    (HAVE_RST_BAR | PLL_AO), 23, 32, 0x0154, 4, 0, 0, 0, 0x0158, 0,
-	    0x0154),
-	PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0164, 0x0170, 0x00000001, 0,
-	    0, 32, 0x0164, 4, 0, 0, 0, 0x0168, 0, 0x0164),
-	PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0174, 0x0180, 0x00000001, 0, 0, 32,
-	    0x0174, 4, 0, 0, 0, 0x0178, 0, 0x0174),
-	PLL(CLK_APMIXED_ARM_B, "arm_b", 0x0204, 0x0210, 0xff000001,
-	    (HAVE_RST_BAR | PLL_AO), 23, 32, 0x0204, 4, 0, 0, 0, 0x0208, 0,
-	    0x0204),
-	PLL(CLK_APMIXED_CCIPLL2_B, "ccipll2_b", 0x0214, 0x0220, 0xff000001,
-	    HAVE_RST_BAR, 23, 32, 0x0214, 4, 0, 0, 0, 0x0218, 0, 0x0214),
-	PLL(CLK_APMIXED_USXGMIIPLL, "usxgmiipll", 0x0304, 0x0310, 0xff000001,
-	    HAVE_RST_BAR, 23, 32, 0x0304, 4, 0, 0, 0, 0x0308, 0, 0x0304),
-	PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0314, 0x0320, 0x00000001, 0, 0,
-	    32, 0x0314, 4, 0, 0, 0, 0x0318, 0, 0x0314),
-};
-
-static const struct of_device_id of_match_clk_mt7988_apmixed[] = {
-	{
-		.compatible = "mediatek,mt7988-apmixedsys",
-	},
-	{}
-};
-
-static int clk_mt7988_apmixed_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_apmixed_data;
-	}
-	return r;
-
-free_apmixed_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
-
-static struct platform_driver clk_mt7988_apmixed_drv = {
-	.probe = clk_mt7988_apmixed_probe,
-	.driver = {
-		.name = "clk-mt7988-apmixed",
-		.of_match_table = of_match_clk_mt7988_apmixed,
-	},
-};
-builtin_platform_driver(clk_mt7988_apmixed_drv);
diff --git a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-eth.c b/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-eth.c
deleted file mode 100644
index 341d0f73fd3080..00000000000000
--- a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-eth.c
+++ /dev/null
@@ -1,299 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2023 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include "clk-mtk.h"
-#include "clk-gate.h"
-#include <dt-bindings/clock/mediatek,mt7988-clk.h>
-
-static const struct mtk_gate_regs ethdma_cg_regs = {
-	.set_ofs = 0x30,
-	.clr_ofs = 0x30,
-	.sta_ofs = 0x30,
-};
-
-#define GATE_ETHDMA(_id, _name, _parent, _shift)                              \
-	{                                                                     \
-		.id = _id, .name = _name, .parent_name = _parent,             \
-		.regs = &ethdma_cg_regs, .shift = _shift,                     \
-		.ops = &mtk_clk_gate_ops_no_setclr_inv,                       \
-	}
-
-static const struct mtk_gate ethdma_clks[] = {
-	GATE_ETHDMA(CLK_ETHDMA_XGP1_EN, "ethdma_xgp1_en", "top_xtal", 0),
-	GATE_ETHDMA(CLK_ETHDMA_XGP2_EN, "ethdma_xgp2_en", "top_xtal", 1),
-	GATE_ETHDMA(CLK_ETHDMA_XGP3_EN, "ethdma_xgp3_en", "top_xtal", 2),
-	GATE_ETHDMA(CLK_ETHDMA_FE_EN, "ethdma_fe_en", "netsys_2x_sel", 6),
-	GATE_ETHDMA(CLK_ETHDMA_GP2_EN, "ethdma_gp2_en", "top_xtal", 7),
-	GATE_ETHDMA(CLK_ETHDMA_GP1_EN, "ethdma_gp1_en", "top_xtal", 8),
-	GATE_ETHDMA(CLK_ETHDMA_GP3_EN, "ethdma_gp3_en", "top_xtal", 10),
-	GATE_ETHDMA(CLK_ETHDMA_ESW_EN, "ethdma_esw_en", "netsys_gsw_sel", 16),
-	GATE_ETHDMA(CLK_ETHDMA_CRYPT0_EN, "ethdma_crypt0_en", "eip197_sel",
-		    29),
-};
-
-static int clk_mt7988_ethsys_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-	void __iomem *base;
-
-	base = of_iomap(node, 0);
-	if (!base) {
-		pr_err("%s(): ioremap failed\n", __func__);
-		return -ENOMEM;
-	}
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(ethdma_clks));
-
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_gates(node, ethdma_clks, ARRAY_SIZE(ethdma_clks),
-			       clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_data;
-	}
-	return r;
-
-free_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
-
-static const struct mtk_gate_regs sgmii0_cg_regs = {
-	.set_ofs = 0xe4,
-	.clr_ofs = 0xe4,
-	.sta_ofs = 0xe4,
-};
-
-#define GATE_SGMII0(_id, _name, _parent, _shift)                              \
-	{                                                                     \
-		.id = _id, .name = _name, .parent_name = _parent,             \
-		.regs = &sgmii0_cg_regs, .shift = _shift,                     \
-		.ops = &mtk_clk_gate_ops_no_setclr_inv,                       \
-	}
-
-static const struct mtk_gate sgmii0_clks[] = {
-	GATE_SGMII0(CLK_SGM0_TX_EN, "sgm0_tx_en", "top_xtal", 2),
-	GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", "top_xtal", 3),
-};
-
-static int clk_mt7988_sgmii0_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-	void __iomem *base;
-
-	base = of_iomap(node, 0);
-	if (!base) {
-		pr_err("%s(): ioremap failed\n", __func__);
-		return -ENOMEM;
-	}
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks));
-
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks),
-			       clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_data;
-	}
-	return r;
-
-free_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
-
-static const struct mtk_gate_regs sgmii1_cg_regs = {
-	.set_ofs = 0xe4,
-	.clr_ofs = 0xe4,
-	.sta_ofs = 0xe4,
-};
-
-#define GATE_SGMII1(_id, _name, _parent, _shift)                              \
-	{                                                                     \
-		.id = _id, .name = _name, .parent_name = _parent,             \
-		.regs = &sgmii1_cg_regs, .shift = _shift,                     \
-		.ops = &mtk_clk_gate_ops_no_setclr_inv,                       \
-	}
-
-static const struct mtk_gate sgmii1_clks[] = {
-	GATE_SGMII1(CLK_SGM1_TX_EN, "sgm1_tx_en", "top_xtal", 2),
-	GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", "top_xtal", 3),
-};
-
-static int clk_mt7988_sgmii1_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-	void __iomem *base;
-
-	base = of_iomap(node, 0);
-	if (!base) {
-		pr_err("%s(): ioremap failed\n", __func__);
-		return -ENOMEM;
-	}
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks));
-
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks),
-			       clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_data;
-	}
-	return r;
-
-free_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
-
-static const struct mtk_gate_regs ethwarp_cg_regs = {
-	.set_ofs = 0x14,
-	.clr_ofs = 0x14,
-	.sta_ofs = 0x14,
-};
-
-#define GATE_ETHWARP(_id, _name, _parent, _shift)                             \
-	{                                                                     \
-		.id = _id, .name = _name, .parent_name = _parent,             \
-		.regs = &ethwarp_cg_regs, .shift = _shift,                    \
-		.ops = &mtk_clk_gate_ops_no_setclr_inv,                       \
-	}
-
-static const struct mtk_gate ethwarp_clks[] = {
-	GATE_ETHWARP(CLK_ETHWARP_WOCPU2_EN, "ethwarp_wocpu2_en",
-		     "netsys_mcu_sel", 13),
-	GATE_ETHWARP(CLK_ETHWARP_WOCPU1_EN, "ethwarp_wocpu1_en",
-		     "netsys_mcu_sel", 14),
-	GATE_ETHWARP(CLK_ETHWARP_WOCPU0_EN, "ethwarp_wocpu0_en",
-		     "netsys_mcu_sel", 15),
-};
-
-static int clk_mt7988_ethwarp_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-	void __iomem *base;
-
-	base = of_iomap(node, 0);
-	if (!base) {
-		pr_err("%s(): ioremap failed\n", __func__);
-		return -ENOMEM;
-	}
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(ethwarp_clks));
-
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_gates(node, ethwarp_clks, ARRAY_SIZE(ethwarp_clks),
-			       clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_data;
-	}
-	return r;
-
-free_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
-
-static const struct of_device_id of_match_clk_mt7988_ethsys[] = {
-	{
-		.compatible = "mediatek,mt7988-ethsys",
-	},
-	{}
-};
-
-static struct platform_driver clk_mt7988_ethsys_drv = {
-	.probe = clk_mt7988_ethsys_probe,
-	.driver = {
-		.name = "clk-mt7988-ethsys",
-		.of_match_table = of_match_clk_mt7988_ethsys,
-	},
-};
-builtin_platform_driver(clk_mt7988_ethsys_drv);
-
-static const struct of_device_id of_match_clk_mt7988_sgmii0[] = {
-	{
-		.compatible = "mediatek,mt7988-sgmiisys_0",
-	},
-	{}
-};
-
-static struct platform_driver clk_mt7988_sgmii0_drv = {
-	.probe = clk_mt7988_sgmii0_probe,
-	.driver = {
-		.name = "clk-mt7988-sgmiisys_0",
-		.of_match_table = of_match_clk_mt7988_sgmii0,
-	},
-};
-builtin_platform_driver(clk_mt7988_sgmii0_drv);
-
-static const struct of_device_id of_match_clk_mt7988_sgmii1[] = {
-	{
-		.compatible = "mediatek,mt7988-sgmiisys_1",
-	},
-	{}
-};
-
-static struct platform_driver clk_mt7988_sgmii1_drv = {
-	.probe = clk_mt7988_sgmii1_probe,
-	.driver = {
-		.name = "clk-mt7988-sgmiisys_1",
-		.of_match_table = of_match_clk_mt7988_sgmii1,
-	},
-};
-builtin_platform_driver(clk_mt7988_sgmii1_drv);
-
-static const struct of_device_id of_match_clk_mt7988_ethwarp[] = {
-	{
-		.compatible = "mediatek,mt7988-ethwarp",
-	},
-	{}
-};
-
-static struct platform_driver clk_mt7988_ethwarp_drv = {
-	.probe = clk_mt7988_ethwarp_probe,
-	.driver = {
-		.name = "clk-mt7988-ethwarp",
-		.of_match_table = of_match_clk_mt7988_ethwarp,
-	},
-};
-builtin_platform_driver(clk_mt7988_ethwarp_drv);
\ No newline at end of file
diff --git a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-infracfg.c b/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-infracfg.c
deleted file mode 100644
index bce8d563756794..00000000000000
--- a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-infracfg.c
+++ /dev/null
@@ -1,406 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2023 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include "clk-mtk.h"
-#include "clk-gate.h"
-#include "clk-mux.h"
-#include <dt-bindings/clock/mediatek,mt7988-clk.h>
-
-static DEFINE_SPINLOCK(mt7988_clk_lock);
-
-static const char *const infra_mux_uart0_parents[] __initconst = {
-	"csw_infra_f26m_sel", "uart_sel"
-};
-
-static const char *const infra_mux_uart1_parents[] __initconst = {
-	"csw_infra_f26m_sel", "uart_sel"
-};
-
-static const char *const infra_mux_uart2_parents[] __initconst = {
-	"csw_infra_f26m_sel", "uart_sel"
-};
-
-static const char *const infra_mux_spi0_parents[] __initconst = { "i2c_sel",
-								  "spi_sel" };
-
-static const char *const infra_mux_spi1_parents[] __initconst = {
-	"i2c_sel", "spim_mst_sel"
-};
-
-static const char *const infra_pwm_bck_parents[] __initconst = {
-	"top_rtc_32p7k", "csw_infra_f26m_sel", "sysaxi_sel", "pwm_sel"
-};
-
-static const char *const infra_pcie_gfmux_tl_ck_o_p0_parents[] __initconst = {
-	"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel",
-	"pextp_tl_sel"
-};
-
-static const char *const infra_pcie_gfmux_tl_ck_o_p1_parents[] __initconst = {
-	"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel",
-	"pextp_tl_p1_sel"
-};
-
-static const char *const infra_pcie_gfmux_tl_ck_o_p2_parents[] __initconst = {
-	"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel",
-	"pextp_tl_p2_sel"
-};
-
-static const char *const infra_pcie_gfmux_tl_ck_o_p3_parents[] __initconst = {
-	"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel",
-	"pextp_tl_p3_sel"
-};
-
-static const struct mtk_mux infra_muxes[] = {
-	/* MODULE_CLK_SEL_0 */
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel",
-			     infra_mux_uart0_parents, 0x0018, 0x0010, 0x0014,
-			     0, 1, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel",
-			     infra_mux_uart1_parents, 0x0018, 0x0010, 0x0014,
-			     1, 1, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel",
-			     infra_mux_uart2_parents, 0x0018, 0x0010, 0x0014,
-			     2, 1, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel",
-			     infra_mux_spi0_parents, 0x0018, 0x0010, 0x0014, 4,
-			     1, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel",
-			     infra_mux_spi1_parents, 0x0018, 0x0010, 0x0014, 5,
-			     1, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel",
-			     infra_mux_spi0_parents, 0x0018, 0x0010, 0x0014, 6,
-			     1, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_SEL, "infra_pwm_sel",
-			     infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 14,
-			     2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel",
-			     infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 16,
-			     2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel",
-			     infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 18,
-			     2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel",
-			     infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 20,
-			     2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel",
-			     infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 22,
-			     2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel",
-			     infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 24,
-			     2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel",
-			     infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 26,
-			     2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel",
-			     infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 28,
-			     2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel",
-			     infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 30,
-			     2, -1, -1, -1),
-	/* MODULE_CLK_SEL_1 */
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL,
-			     "infra_pcie_gfmux_tl_o_p0_sel",
-			     infra_pcie_gfmux_tl_ck_o_p0_parents, 0x0028,
-			     0x0020, 0x0024, 0, 2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL,
-			     "infra_pcie_gfmux_tl_o_p1_sel",
-			     infra_pcie_gfmux_tl_ck_o_p1_parents, 0x0028,
-			     0x0020, 0x0024, 2, 2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL,
-			     "infra_pcie_gfmux_tl_o_p2_sel",
-			     infra_pcie_gfmux_tl_ck_o_p2_parents, 0x0028,
-			     0x0020, 0x0024, 4, 2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL,
-			     "infra_pcie_gfmux_tl_o_p3_sel",
-			     infra_pcie_gfmux_tl_ck_o_p3_parents, 0x0028,
-			     0x0020, 0x0024, 6, 2, -1, -1, -1),
-};
-
-static const struct mtk_gate_regs infra0_cg_regs = {
-	.set_ofs = 0x10,
-	.clr_ofs = 0x14,
-	.sta_ofs = 0x18,
-};
-
-static const struct mtk_gate_regs infra1_cg_regs = {
-	.set_ofs = 0x40,
-	.clr_ofs = 0x44,
-	.sta_ofs = 0x48,
-};
-
-static const struct mtk_gate_regs infra2_cg_regs = {
-	.set_ofs = 0x50,
-	.clr_ofs = 0x54,
-	.sta_ofs = 0x58,
-};
-
-static const struct mtk_gate_regs infra3_cg_regs = {
-	.set_ofs = 0x60,
-	.clr_ofs = 0x64,
-	.sta_ofs = 0x68,
-};
-
-#define GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, _flags)                \
-	{                                                                     \
-		.id = _id, .name = _name, .parent_name = _parent,             \
-		.regs = &infra0_cg_regs, .shift = _shift,                     \
-		.ops = &mtk_clk_gate_ops_setclr, .flags = _flags,             \
-	}
-
-#define GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, _flags)                \
-	{                                                                     \
-		.id = _id, .name = _name, .parent_name = _parent,             \
-		.regs = &infra1_cg_regs, .shift = _shift,                     \
-		.ops = &mtk_clk_gate_ops_setclr, .flags = _flags,             \
-	}
-
-#define GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, _flags)                \
-	{                                                                     \
-		.id = _id, .name = _name, .parent_name = _parent,             \
-		.regs = &infra2_cg_regs, .shift = _shift,                     \
-		.ops = &mtk_clk_gate_ops_setclr, .flags = _flags,             \
-	}
-
-#define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flags)                \
-	{                                                                     \
-		.id = _id, .name = _name, .parent_name = _parent,             \
-		.regs = &infra3_cg_regs, .shift = _shift,                     \
-		.ops = &mtk_clk_gate_ops_setclr, .flags = _flags,             \
-	}
-
-#define GATE_INFRA0(_id, _name, _parent, _shift)                              \
-	GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, 0)
-
-#define GATE_INFRA1(_id, _name, _parent, _shift)                              \
-	GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, 0)
-
-#define GATE_INFRA2(_id, _name, _parent, _shift)                              \
-	GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, 0)
-
-#define GATE_INFRA3(_id, _name, _parent, _shift)                              \
-	GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, 0)
-
-#define GATE_CRITICAL(_id, _name, _parent, _regs, _shift) {                   \
-		.id = _id, .name = _name, .parent_name = _parent,             \
-		.regs = _regs, .shift = _shift,                               \
-		.flags = CLK_IS_CRITICAL,                                     \
-		.ops = &mtk_clk_gate_ops_setclr,                              \
-	}
-
-static const struct mtk_gate infra_clks[] = {
-	/* INFRA0 */
-	GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P0,
-		    "infra_pcie_peri_ck_26m_ck_p0", "csw_infra_f26m_sel", 7),
-	GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P1,
-		    "infra_pcie_peri_ck_26m_ck_p1", "csw_infra_f26m_sel", 8),
-	GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P2,
-		    "infra_pcie_peri_ck_26m_ck_p2", "csw_infra_f26m_sel", 9),
-	GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P3,
-		    "infra_pcie_peri_ck_26m_ck_p3", "csw_infra_f26m_sel", 10),
-	/* INFRA1 */
-	GATE_INFRA1(CLK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck",
-		    "sysaxi_sel", 0),
-	GATE_INFRA1(CLK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck",
-		    "sysaxi_sel", 1),
-	GATE_INFRA1(CLK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck",
-		    "infra_pwm_sel", 2),
-	GATE_INFRA1(CLK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1",
-		    "infra_pwm_ck1_sel", 3),
-	GATE_INFRA1(CLK_INFRA_66M_PWM_CK2, "infra_hf_66m_pwm_ck2",
-		    "infra_pwm_ck2_sel", 4),
-	GATE_INFRA1(CLK_INFRA_66M_PWM_CK3, "infra_hf_66m_pwm_ck3",
-		    "infra_pwm_ck3_sel", 5),
-	GATE_INFRA1(CLK_INFRA_66M_PWM_CK4, "infra_hf_66m_pwm_ck4",
-		    "infra_pwm_ck4_sel", 6),
-	GATE_INFRA1(CLK_INFRA_66M_PWM_CK5, "infra_hf_66m_pwm_ck5",
-		    "infra_pwm_ck5_sel", 7),
-	GATE_INFRA1(CLK_INFRA_66M_PWM_CK6, "infra_hf_66m_pwm_ck6",
-		    "infra_pwm_ck6_sel", 8),
-	GATE_INFRA1(CLK_INFRA_66M_PWM_CK7, "infra_hf_66m_pwm_ck7",
-		    "infra_pwm_ck7_sel", 9),
-	GATE_INFRA1(CLK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8",
-		    "infra_pwm_ck8_sel", 10),
-	GATE_INFRA1(CLK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck",
-		    "sysaxi_sel", 12),
-	GATE_INFRA1(CLK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck",
-		    "sysaxi_sel", 13),
-	GATE_INFRA1(CLK_INFRA_AUD_26M, "infra_f_faud_26m",
-		    "csw_infra_f26m_sel", 14),
-	GATE_INFRA1(CLK_INFRA_AUD_L, "infra_f_faud_l", "aud_l_sel", 15),
-	GATE_INFRA1(CLK_INFRA_AUD_AUD, "infra_f_aud_aud", "a1sys_sel", 16),
-	GATE_INFRA1(CLK_INFRA_AUD_EG2, "infra_f_faud_eg2", "a_tuner_sel", 18),
-	GATE_INFRA1_FLAGS(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m",
-			  "csw_infra_f26m_sel", 19, CLK_IS_CRITICAL),
-	// JTAG
-	GATE_INFRA1_FLAGS(CLK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm",
-			  "sysaxi_sel", 20, CLK_IS_CRITICAL),
-	GATE_INFRA1(CLK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck",
-		    "sysaxi_sel", 21),
-	GATE_INFRA1(CLK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck",
-		    "sysaxi_sel", 29),
-	GATE_INFRA1(CLK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m",
-		    "csw_infra_f26m_sel", 30),
-	/* INFRA2 */
-	GATE_INFRA2(CLK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system",
-		    "csw_infra_f26m_sel", 0),
-	GATE_INFRA2(CLK_INFRA_I2C_BCK, "infra_i2c_bck", "i2c_sel", 1),
-	GATE_INFRA2(CLK_INFRA_52M_UART0_CK, "infra_f_52m_uart0",
-		    "infra_mux_uart0_sel", 3),
-	GATE_INFRA2(CLK_INFRA_52M_UART1_CK, "infra_f_52m_uart1",
-		    "infra_mux_uart1_sel", 4),
-	GATE_INFRA2(CLK_INFRA_52M_UART2_CK, "infra_f_52m_uart2",
-		    "infra_mux_uart2_sel", 5),
-	GATE_INFRA2(CLK_INFRA_NFI, "infra_f_fnfi", "nfi1x_sel", 9),
-	GATE_INFRA2(CLK_INFRA_SPINFI, "infra_f_fspinfi", "spinfi_sel", 10),
-	GATE_INFRA2_FLAGS(CLK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck",
-			  "sysaxi_sel", 11, CLK_IS_CRITICAL),
-	GATE_INFRA2_FLAGS(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0",
-			  "infra_mux_spi0_sel", 12, CLK_IS_CRITICAL),
-	GATE_INFRA2(CLK_INFRA_104M_SPI1, "infra_hf_104m_spi1",
-		    "infra_mux_spi1_sel", 13),
-	GATE_INFRA2(CLK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck",
-		    "infra_mux_spi2_sel", 14),
-	GATE_INFRA2_FLAGS(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck",
-			  "sysaxi_sel", 15, CLK_IS_CRITICAL),
-	GATE_INFRA2(CLK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck",
-		    "sysaxi_sel", 16),
-	GATE_INFRA2(CLK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck",
-		    "sysaxi_sel", 17),
-	GATE_INFRA2(CLK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi",
-		    "sysaxi_sel", 18),
-	GATE_CRITICAL(CLK_INFRA_RTC, "infra_f_frtc", "top_rtc_32k", &infra2_cg_regs, 19),
-	GATE_INFRA2(CLK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck",
-		    "csw_infra_f26m_sel", 20),
-	GATE_INFRA2(CLK_INFRA_RC_ADC, "infra_f_frc_adc", "infra_f_26m_adc_bck",
-		    21),
-	GATE_INFRA2(CLK_INFRA_MSDC400, "infra_f_fmsdc400", "emmc_400m_sel",
-		    22),
-	GATE_INFRA2(CLK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck", "emmc_250m_sel",
-		    23),
-	GATE_INFRA2(CLK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck",
-		    "sysaxi_sel", 24),
-	GATE_INFRA2(CLK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck",
-		    "sysaxi_sel", 25),
-	GATE_INFRA2(CLK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck",
-		    "sysaxi_sel", 26),
-	GATE_INFRA2(CLK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", "nfi1x_sel", 27),
-	GATE_INFRA2(CLK_INFRA_I2C_X16W_MCK_CK_P1,
-		    "infra_hf_i2c_x16w_mck_ck_p1", "sysaxi_sel", 29),
-	GATE_INFRA2(CLK_INFRA_I2C_X16W_PCK_CK_P1,
-		    "infra_hf_i2c_x16w_pck_ck_p1", "sysaxi_sel", 31),
-	/* INFRA3 */
-	GATE_INFRA3(CLK_INFRA_133M_USB_HCK, "infra_133m_usb_hck", "sysaxi_sel",
-		    0),
-	GATE_INFRA3(CLK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1",
-		    "sysaxi_sel", 1),
-	GATE_INFRA3(CLK_INFRA_66M_USB_HCK, "infra_66m_usb_hck", "sysaxi_sel",
-		    2),
-	GATE_INFRA3(CLK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1",
-		    "sysaxi_sel", 3),
-	GATE_INFRA3(CLK_INFRA_USB_SYS, "infra_usb_sys", "usb_sys_sel", 4),
-	GATE_INFRA3(CLK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1",
-		    "usb_sys_p1_sel", 5),
-	GATE_INFRA3(CLK_INFRA_USB_REF, "infra_usb_ref", "top_xtal", 6),
-	GATE_INFRA3(CLK_INFRA_USB_CK_P1, "infra_usb_ck_p1", "top_xtal", 7),
-	GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT, "infra_usb_frmcnt",
-			  "usb_frmcnt_sel", 8, CLK_IS_CRITICAL),
-	GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1",
-			  "usb_frmcnt_p1_sel", 9, CLK_IS_CRITICAL),
-	GATE_INFRA3(CLK_INFRA_USB_PIPE, "infra_usb_pipe", "sspxtp_sel", 10),
-	GATE_INFRA3(CLK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1",
-		    "usb_phy_sel", 11),
-	GATE_INFRA3(CLK_INFRA_USB_UTMI, "infra_usb_utmi", "top_xtal", 12),
-	GATE_INFRA3(CLK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1",
-		    "top_xtal", 13),
-	GATE_INFRA3(CLK_INFRA_USB_XHCI, "infra_usb_xhci", "usb_xhci_sel", 14),
-	GATE_INFRA3(CLK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1",
-		    "usb_xhci_p1_sel", 15),
-	GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0",
-		    "infra_pcie_gfmux_tl_o_p0_sel", 20),
-	GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1",
-		    "infra_pcie_gfmux_tl_o_p1_sel", 21),
-	GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P2, "infra_pcie_gfmux_tl_ck_p2",
-		    "infra_pcie_gfmux_tl_o_p2_sel", 22),
-	GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3",
-		    "infra_pcie_gfmux_tl_o_p3_sel", 23),
-	GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0",
-		    "top_xtal", 24),
-	GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1",
-		    "top_xtal", 25),
-	GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2",
-		    "top_xtal", 26),
-	GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3",
-		    "top_xtal", 27),
-	GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0",
-		    "sysaxi_sel", 28),
-	GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1",
-		    "sysaxi_sel", 29),
-	GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2",
-		    "sysaxi_sel", 30),
-	GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3",
-		    "sysaxi_sel", 31),
-};
-
-static int clk_mt7988_infracfg_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-	void __iomem *base;
-	int nr = ARRAY_SIZE(infra_muxes) + ARRAY_SIZE(infra_clks);
-
-	base = of_iomap(node, 0);
-	if (!base) {
-		pr_err("%s(): ioremap failed\n", __func__);
-		return -ENOMEM;
-	}
-
-	clk_data = mtk_alloc_clk_data(nr);
-
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node,
-			       &mt7988_clk_lock, clk_data);
-
-	mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
-			       clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_infracfg_data;
-	}
-	return r;
-
-free_infracfg_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
-
-static const struct of_device_id of_match_clk_mt7988_infracfg[] = {
-	{
-		.compatible = "mediatek,mt7988-infracfg",
-	},
-	{}
-};
-
-static struct platform_driver clk_mt7988_infracfg_drv = {
-	.probe = clk_mt7988_infracfg_probe,
-	.driver = {
-		.name = "clk-mt7988-infracfg",
-		.of_match_table = of_match_clk_mt7988_infracfg,
-	},
-};
-builtin_platform_driver(clk_mt7988_infracfg_drv);
diff --git a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-topckgen.c b/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-topckgen.c
deleted file mode 100644
index 917302b6df682a..00000000000000
--- a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-topckgen.c
+++ /dev/null
@@ -1,522 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2023 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include "clk-mtk.h"
-#include "clk-gate.h"
-#include "clk-mux.h"
-#include <dt-bindings/clock/mediatek,mt7988-clk.h>
-
-static DEFINE_SPINLOCK(mt7988_clk_lock);
-
-static const struct mtk_fixed_clk top_fixed_clks[] = {
-	FIXED_CLK(CLK_TOP_XTAL, "top_xtal", "clkxtal", 40000000),
-};
-
-static const struct mtk_fixed_factor top_divs[] = {
-	FACTOR(CLK_TOP_XTAL_D2, "top_xtal_d2", "top_xtal", 1, 2),
-	FACTOR(CLK_TOP_RTC_32K, "top_rtc_32k", "top_xtal", 1, 1250),
-	FACTOR(CLK_TOP_RTC_32P7K, "top_rtc_32p7k", "top_xtal", 1, 1220),
-	FACTOR(CLK_TOP_MPLL_D2, "mpll_d2", "mpll", 1, 2),
-	FACTOR(CLK_TOP_MPLL_D3_D2, "mpll_d3_d2", "mpll", 1, 2),
-	FACTOR(CLK_TOP_MPLL_D4, "mpll_d4", "mpll", 1, 4),
-	FACTOR(CLK_TOP_MPLL_D8, "mpll_d8", "mpll", 1, 8),
-	FACTOR(CLK_TOP_MPLL_D8_D2, "mpll_d8_d2", "mpll", 1, 16),
-	FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
-	FACTOR(CLK_TOP_MMPLL_D3_D5, "mmpll_d3_d5", "mmpll", 1, 15),
-	FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4),
-	FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll", 1, 12),
-	FACTOR(CLK_TOP_MMPLL_D8, "mmpll_d8", "mmpll", 1, 8),
-	FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
-	FACTOR(CLK_TOP_NET1PLL_D4, "net1pll_d4", "net1pll", 1, 4),
-	FACTOR(CLK_TOP_NET1PLL_D5, "net1pll_d5", "net1pll", 1, 5),
-	FACTOR(CLK_TOP_NET1PLL_D5_D2, "net1pll_d5_d2", "net1pll", 1, 10),
-	FACTOR(CLK_TOP_NET1PLL_D5_D4, "net1pll_d5_d4", "net1pll", 1, 20),
-	FACTOR(CLK_TOP_NET1PLL_D8, "net1pll_d8", "net1pll", 1, 8),
-	FACTOR(CLK_TOP_NET1PLL_D8_D2, "net1pll_d8_d2", "net1pll", 1, 16),
-	FACTOR(CLK_TOP_NET1PLL_D8_D4, "net1pll_d8_d4", "net1pll", 1, 32),
-	FACTOR(CLK_TOP_NET1PLL_D8_D8, "net1pll_d8_d8", "net1pll", 1, 64),
-	FACTOR(CLK_TOP_NET1PLL_D8_D16, "net1pll_d8_d16", "net1pll", 1, 128),
-	FACTOR(CLK_TOP_NET2PLL_D2, "net2pll_d2", "net2pll", 1, 2),
-	FACTOR(CLK_TOP_NET2PLL_D4, "net2pll_d4", "net2pll", 1, 4),
-	FACTOR(CLK_TOP_NET2PLL_D4_D4, "net2pll_d4_d4", "net2pll", 1, 16),
-	FACTOR(CLK_TOP_NET2PLL_D4_D8, "net2pll_d4_d8", "net2pll", 1, 32),
-	FACTOR(CLK_TOP_NET2PLL_D6, "net2pll_d6", "net2pll", 1, 6),
-	FACTOR(CLK_TOP_NET2PLL_D8, "net2pll_d8", "net2pll", 1, 8),
-};
-
-static const char *const netsys_parents[] = { "top_xtal", "net2pll_d2",
-					      "mmpll_d2" };
-
-static const char *const netsys_500m_parents[] = { "top_xtal", "net1pll_d5",
-						   "net1pll_d5_d2" };
-
-static const char *const netsys_2x_parents[] = { "top_xtal", "net2pll",
-						 "mmpll" };
-
-static const char *const netsys_gsw_parents[] = { "top_xtal", "net1pll_d4",
-						  "net1pll_d5" };
-
-static const char *const eth_gmii_parents[] = { "top_xtal", "net1pll_d5_d4" };
-
-static const char *const netsys_mcu_parents[] = { "top_xtal",	"net2pll",
-						  "mmpll",	"net1pll_d4",
-						  "net1pll_d5", "mpll" };
-
-static const char *const eip197_parents[] = { "top_xtal",   "netsyspll",
-					      "net2pll",    "mmpll",
-					      "net1pll_d4", "net1pll_d5" };
-
-static const char *const axi_infra_parents[] = { "top_xtal", "net1pll_d8_d2" };
-
-static const char *const uart_parents[] = { "top_xtal", "mpll_d8",
-					    "mpll_d8_d2" };
-
-static const char *const emmc_250m_parents[] = { "top_xtal", "net1pll_d5_d2",
-						 "mmpll_d4" };
-
-static const char *const emmc_400m_parents[] = { "top_xtal", "msdcpll",
-						 "mmpll_d2", "mpll_d2",
-						 "mmpll_d4", "net1pll_d8_d2" };
-
-static const char *const spi_parents[] = { "top_xtal",	 "mpll_d2",
-					   "mmpll_d4",	 "net1pll_d8_d2",
-					   "net2pll_d6", "net1pll_d5_d4",
-					   "mpll_d4",	 "net1pll_d8_d4" };
-
-static const char *const nfi1x_parents[] = { "top_xtal",      "mmpll_d4",
-					     "net1pll_d8_d2", "net2pll_d6",
-					     "mpll_d4",	      "mmpll_d8",
-					     "net1pll_d8_d4", "mpll_d8" };
-
-static const char *const spinfi_parents[] = { "top_xtal_d2",   "top_xtal",
-					      "net1pll_d5_d4", "mpll_d4",
-					      "mmpll_d8",      "net1pll_d8_d4",
-					      "mmpll_d6_d2",   "mpll_d8" };
-
-static const char *const pwm_parents[] = { "top_xtal",	    "net1pll_d8_d2",
-					   "net1pll_d5_d4", "mpll_d4",
-					   "mpll_d8_d2",    "top_rtc_32k" };
-
-static const char *const i2c_parents[] = { "top_xtal", "net1pll_d5_d4",
-					   "mpll_d4", "net1pll_d8_d4" };
-
-static const char *const pcie_mbist_250m_parents[] = { "top_xtal",
-						       "net1pll_d5_d2" };
-
-static const char *const pextp_tl_ck_parents[] = { "top_xtal", "net2pll_d6",
-						   "mmpll_d8", "mpll_d8_d2",
-						   "top_rtc_32k" };
-
-static const char *const usb_frmcnt_parents[] = { "top_xtal", "mmpll_d3_d5" };
-
-static const char *const aud_parents[] = { "top_xtal", "apll2" };
-
-static const char *const a1sys_parents[] = { "top_xtal", "apll2_d4" };
-
-static const char *const aud_l_parents[] = { "top_xtal", "apll2",
-					     "mpll_d8_d2" };
-
-static const char *const sspxtp_parents[] = { "top_xtal_d2", "mpll_d8_d2" };
-
-static const char *const usxgmii_sbus_0_parents[] = { "top_xtal",
-						      "net1pll_d8_d4" };
-
-static const char *const sgm_0_parents[] = { "top_xtal", "sgmpll" };
-
-static const char *const sysapb_parents[] = { "top_xtal", "mpll_d3_d2" };
-
-static const char *const eth_refck_50m_parents[] = { "top_xtal",
-						     "net2pll_d4_d4" };
-
-static const char *const eth_sys_200m_parents[] = { "top_xtal", "net2pll_d4" };
-
-static const char *const eth_xgmii_parents[] = { "top_xtal_d2",
-						 "net1pll_d8_d8",
-						 "net1pll_d8_d16" };
-
-static const char *const bus_tops_parents[] = { "top_xtal", "net1pll_d5",
-						"net2pll_d2" };
-
-static const char *const npu_tops_parents[] = { "top_xtal", "net2pll" };
-
-static const char *const dramc_md32_parents[] = { "top_xtal", "mpll_d2",
-						  "wedmcupll" };
-
-static const char *const da_xtp_glb_p0_parents[] = { "top_xtal",
-						     "net2pll_d8" };
-
-static const char *const mcusys_backup_625m_parents[] = { "top_xtal",
-							  "net1pll_d4" };
-
-static const char *const macsec_parents[] = { "top_xtal", "sgmpll",
-					      "net1pll_d8" };
-
-static const char *const netsys_tops_400m_parents[] = { "top_xtal",
-							"net2pll_d2" };
-
-static const char *const eth_mii_parents[] = { "top_xtal_d2",
-					       "net2pll_d4_d8" };
-
-static const struct mtk_mux top_muxes[] = {
-	/* CLK_CFG_0 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents,
-			     0x000, 0x004, 0x008, 0, 2, 7, 0x1c0, 0),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel",
-			     netsys_500m_parents, 0x000, 0x004, 0x008, 8, 2,
-			     15, 0x1C0, 1),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel",
-			     netsys_2x_parents, 0x000, 0x004, 0x008, 16, 2, 23,
-			     0x1C0, 2),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel",
-			     netsys_gsw_parents, 0x000, 0x004, 0x008, 24, 2,
-			     31, 0x1C0, 3),
-	/* CLK_CFG_1 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_GMII_SEL, "eth_gmii_sel",
-			     eth_gmii_parents, 0x010, 0x014, 0x018, 0, 1, 7,
-			     0x1C0, 4),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel",
-			     netsys_mcu_parents, 0x010, 0x014, 0x018, 8, 3, 15,
-			     0x1C0, 5),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PAO_2X_SEL, "netsys_pao_2x_sel",
-			     netsys_mcu_parents, 0x010, 0x014, 0x018, 16, 3,
-			     23, 0x1C0, 6),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP197_SEL, "eip197_sel", eip197_parents,
-			     0x010, 0x014, 0x018, 24, 3, 31, 0x1c0, 7),
-	/* CLK_CFG_2 */
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_INFRA_SEL, "axi_infra_sel",
-				   axi_infra_parents, 0x020, 0x024, 0x028, 0,
-				   1, 7, 0x1C0, 8, CLK_IS_CRITICAL),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x020,
-			     0x024, 0x028, 8, 2, 15, 0x1c0, 9),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel",
-			     emmc_250m_parents, 0x020, 0x024, 0x028, 16, 2, 23,
-			     0x1C0, 10),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel",
-			     emmc_400m_parents, 0x020, 0x024, 0x028, 24, 3, 31,
-			     0x1C0, 11),
-	/* CLK_CFG_3 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x030,
-			     0x034, 0x038, 0, 3, 7, 0x1c0, 12),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents,
-			     0x030, 0x034, 0x038, 8, 3, 15, 0x1c0, 13),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents,
-			     0x030, 0x034, 0x038, 16, 3, 23, 0x1c0, 14),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents,
-			     0x030, 0x034, 0x038, 24, 3, 31, 0x1c0, 15),
-	/* CLK_CFG_4 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x040,
-			     0x044, 0x048, 0, 3, 7, 0x1c0, 16),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x040,
-			     0x044, 0x048, 8, 2, 15, 0x1c0, 17),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PCIE_MBIST_250M_SEL,
-			     "pcie_mbist_250m_sel", pcie_mbist_250m_parents,
-			     0x040, 0x044, 0x048, 16, 1, 23, 0x1C0, 18),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_sel",
-			     pextp_tl_ck_parents, 0x040, 0x044, 0x048, 24, 3,
-			     31, 0x1C0, 19),
-	/* CLK_CFG_5 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_p1_sel",
-			     pextp_tl_ck_parents, 0x050, 0x054, 0x058, 0, 3, 7,
-			     0x1C0, 20),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P2_SEL, "pextp_tl_p2_sel",
-			     pextp_tl_ck_parents, 0x050, 0x054, 0x058, 8, 3,
-			     15, 0x1C0, 21),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P3_SEL, "pextp_tl_p3_sel",
-			     pextp_tl_ck_parents, 0x050, 0x054, 0x058, 16, 3,
-			     23, 0x1C0, 22),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_SEL, "usb_sys_sel",
-			     eth_gmii_parents, 0x050, 0x054, 0x058, 24, 1, 31,
-			     0x1C0, 23),
-	/* CLK_CFG_6 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel",
-			     eth_gmii_parents, 0x060, 0x064, 0x068, 0, 1, 7,
-			     0x1C0, 24),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_SEL, "usb_xhci_sel",
-			     eth_gmii_parents, 0x060, 0x064, 0x068, 8, 1, 15,
-			     0x1C0, 25),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel",
-			     eth_gmii_parents, 0x060, 0x064, 0x068, 16, 1, 23,
-			     0x1C0, 26),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel",
-			     usb_frmcnt_parents, 0x060, 0x064, 0x068, 24, 1,
-			     31, 0x1C0, 27),
-	/* CLK_CFG_7 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_P1_SEL, "usb_frmcnt_p1_sel",
-			     usb_frmcnt_parents, 0x070, 0x074, 0x078, 0, 1, 7,
-			     0x1C0, 28),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x070,
-			     0x074, 0x078, 8, 1, 15, 0x1c0, 29),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents,
-			     0x070, 0x074, 0x078, 16, 1, 23, 0x1c0, 30),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents,
-			     0x070, 0x074, 0x078, 24, 2, 31, 0x1c4, 0),
-	/* CLK_CFG_8 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents,
-			     0x080, 0x084, 0x088, 0, 1, 7, 0x1c4, 1),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SSPXTP_SEL, "sspxtp_sel", sspxtp_parents,
-			     0x080, 0x084, 0x088, 8, 1, 15, 0x1c4, 2),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_PHY_SEL, "usb_phy_sel",
-			     sspxtp_parents, 0x080, 0x084, 0x088, 16, 1, 23,
-			     0x1c4, 3),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_0_SEL, "usxgmii_sbus_0_sel",
-			     usxgmii_sbus_0_parents, 0x080, 0x084, 0x088, 24,
-			     1, 31, 0x1C4, 4),
-	/* CLK_CFG_9 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_1_SEL, "usxgmii_sbus_1_sel",
-			     usxgmii_sbus_0_parents, 0x090, 0x094, 0x098, 0, 1,
-			     7, 0x1C4, 5),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents,
-			     0x090, 0x094, 0x098, 8, 1, 15, 0x1c4, 6),
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel",
-				   usxgmii_sbus_0_parents, 0x090, 0x094, 0x098,
-				   16, 1, 23, 0x1C4, 7, CLK_IS_CRITICAL),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents,
-			     0x090, 0x094, 0x098, 24, 1, 31, 0x1c4, 8),
-	/* CLK_CFG_10 */
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel",
-				   usxgmii_sbus_0_parents, 0x0a0, 0x0a4, 0x0a8,
-				   0, 1, 7, 0x1C4, 9, CLK_IS_CRITICAL),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_0_XTAL_SEL, "xfi_phy_0_xtal_sel",
-			     sspxtp_parents, 0x0a0, 0x0a4, 0x0a8, 8, 1, 15,
-			     0x1C4, 10),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_1_XTAL_SEL, "xfi_phy_1_xtal_sel",
-			     sspxtp_parents, 0x0a0, 0x0a4, 0x0a8, 16, 1, 23,
-			     0x1C4, 11),
-	/* CLK_CFG_11 */
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel",
-				   axi_infra_parents, 0x0a0, 0x0a4, 0x0a8, 24,
-				   1, 31, 0x1C4, 12, CLK_IS_CRITICAL),
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel",
-				   sysapb_parents, 0x0b0, 0x0b4, 0x0b8, 0, 1,
-				   7, 0x1c4, 13, CLK_IS_CRITICAL),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel",
-			     eth_refck_50m_parents, 0x0b0, 0x0b4, 0x0b8, 8, 1,
-			     15, 0x1C4, 14),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel",
-			     eth_sys_200m_parents, 0x0b0, 0x0b4, 0x0b8, 16, 1,
-			     23, 0x1C4, 15),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_SEL, "eth_sys_sel",
-			     pcie_mbist_250m_parents, 0x0b0, 0x0b4, 0x0b8, 24,
-			     1, 31, 0x1C4, 16),
-	/* CLK_CFG_12 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel",
-			     eth_xgmii_parents, 0x0c0, 0x0c4, 0x0c8, 0, 2, 7,
-			     0x1C4, 17),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_BUS_TOPS_SEL, "bus_tops_sel",
-			     bus_tops_parents, 0x0c0, 0x0c4, 0x0c8, 8, 2, 15,
-			     0x1C4, 18),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_TOPS_SEL, "npu_tops_sel",
-			     npu_tops_parents, 0x0c0, 0x0c4, 0x0c8, 16, 1, 23,
-			     0x1C4, 19),
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel",
-				   sspxtp_parents, 0x0c0, 0x0c4, 0x0c8, 24, 1,
-				   31, 0x1C4, 20, CLK_IS_CRITICAL),
-	/* CLK_CFG_13 */
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
-				   dramc_md32_parents, 0x0d0, 0x0d4, 0x0d8, 0,
-				   2, 7, 0x1C4, 21, CLK_IS_CRITICAL),
-	MUX_GATE_CLR_SET_UPD_FLAGS(
-		CLK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", sspxtp_parents,
-		0x0d0, 0x0d4, 0x0d8, 8, 1, 15, 0x1C4, 22, CLK_IS_CRITICAL),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P0_SEL, "pextp_p0_sel",
-			     sspxtp_parents, 0x0d0, 0x0d4, 0x0d8, 16, 1, 23,
-			     0x1C4, 23),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P1_SEL, "pextp_p1_sel",
-			     sspxtp_parents, 0x0d0, 0x0d4, 0x0d8, 24, 1, 31,
-			     0x1C4, 24),
-	/* CLK_CFG_14 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P2_SEL, "pextp_p2_sel",
-			     sspxtp_parents, 0x0e0, 0x0e4, 0x0e8, 0, 1, 7,
-			     0x1C4, 25),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P3_SEL, "pextp_p3_sel",
-			     sspxtp_parents, 0x0e0, 0x0e4, 0x0e8, 8, 1, 15,
-			     0x1C4, 26),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel",
-			     da_xtp_glb_p0_parents, 0x0e0, 0x0e4, 0x0e8, 16, 1,
-			     23, 0x1C4, 27),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel",
-			     da_xtp_glb_p0_parents, 0x0e0, 0x0e4, 0x0e8, 24, 1,
-			     31, 0x1C4, 28),
-	/* CLK_CFG_15 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P2_SEL, "da_xtp_glb_p2_sel",
-			     da_xtp_glb_p0_parents, 0x0f0, 0x0f4, 0x0f8, 0, 1,
-			     7, 0x1C4, 29),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P3_SEL, "da_xtp_glb_p3_sel",
-			     da_xtp_glb_p0_parents, 0x0f0, 0x0f4, 0x0f8, 8, 1,
-			     15, 0x1C4, 30),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_CKM_SEL, "ckm_sel", sspxtp_parents, 0x0F0,
-			     0x0f4, 0x0f8, 16, 1, 23, 0x1c8, 0),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_SEL, "da_sel", sspxtp_parents, 0x0f0,
-			     0x0f4, 0x0f8, 24, 1, 31, 0x1C8, 1),
-	/* CLK_CFG_16 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_SEL, "pextp_sel", sspxtp_parents,
-			     0x0100, 0x104, 0x108, 0, 1, 7, 0x1c8, 2),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_TOPS_P2_26M_SEL, "tops_p2_26m_sel",
-			     sspxtp_parents, 0x0100, 0x104, 0x108, 8, 1, 15,
-			     0x1C8, 3),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_MCUSYS_BACKUP_625M_SEL,
-			     "mcusys_backup_625m_sel",
-			     mcusys_backup_625m_parents, 0x0100, 0x104, 0x108,
-			     16, 1, 23, 0x1C8, 4),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SYNC_250M_SEL,
-			     "netsys_sync_250m_sel", pcie_mbist_250m_parents,
-			     0x0100, 0x104, 0x108, 24, 1, 31, 0x1c8, 5),
-	/* CLK_CFG_17 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_MACSEC_SEL, "macsec_sel", macsec_parents,
-			     0x0110, 0x114, 0x118, 0, 2, 7, 0x1c8, 6),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_TOPS_400M_SEL,
-			     "netsys_tops_400m_sel", netsys_tops_400m_parents,
-			     0x0110, 0x114, 0x118, 8, 1, 15, 0x1c8, 7),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PPEFB_250M_SEL,
-			     "netsys_ppefb_250m_sel", pcie_mbist_250m_parents,
-			     0x0110, 0x114, 0x118, 16, 1, 23, 0x1c8, 8),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_WARP_SEL, "netsys_warp_sel",
-			     netsys_parents, 0x0110, 0x114, 0x118, 24, 2, 31,
-			     0x1C8, 9),
-	/* CLK_CFG_18 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_MII_SEL, "eth_mii_sel",
-			     eth_mii_parents, 0x0120, 0x124, 0x128, 0, 1, 7,
-			     0x1c8, 10),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_SEL, "ck_npu_sel", netsys_2x_parents,
-			     0x0120, 0x124, 0x128, 8, 2, 15, 0x1c8, 11),
-};
-
-static const struct mtk_composite top_aud_divs[] = {
-	DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud_sel", 0x0420, 0, 0x0420,
-		 8, 8),
-};
-
-static int clk_mt7988_topckgen_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-	void __iomem *base;
-	int nr = ARRAY_SIZE(top_fixed_clks) + ARRAY_SIZE(top_divs) +
-		 ARRAY_SIZE(top_muxes) + ARRAY_SIZE(top_aud_divs);
-
-	base = of_iomap(node, 0);
-	if (!base) {
-		pr_err("%s(): ioremap failed\n", __func__);
-		return -ENOMEM;
-	}
-
-	clk_data = mtk_alloc_clk_data(nr);
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
-				    clk_data);
-
-	mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
-
-	mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node,
-			       &mt7988_clk_lock, clk_data);
-
-	mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs),
-				    base, &mt7988_clk_lock, clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_topckgen_data;
-	}
-	return r;
-
-free_topckgen_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
-
-static const char *const mcu_bus_div_parents[] = { "top_xtal", "ccipll2_b",
-						   "net1pll_d4" };
-
-static const char *const mcu_arm_div_parents[] = { "top_xtal", "arm_b",
-						   "net1pll_d4" };
-
-static struct mtk_composite mcu_muxes[] = {
-	/* bus_pll_divider_cfg */
-	MUX_GATE_FLAGS(CLK_MCU_BUS_DIV_SEL, "mcu_bus_div_sel",
-		       mcu_bus_div_parents, 0x7C0, 9, 2, -1, CLK_IS_CRITICAL),
-	/* mp2_pll_divider_cfg */
-	MUX_GATE_FLAGS(CLK_MCU_ARM_DIV_SEL, "mcu_arm_div_sel",
-		       mcu_arm_div_parents, 0x7A8, 9, 2, -1, CLK_IS_CRITICAL),
-};
-
-static int clk_mt7988_mcusys_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-	void __iomem *base;
-	int nr = ARRAY_SIZE(mcu_muxes);
-
-	base = of_iomap(node, 0);
-	if (!base) {
-		pr_err("%s(): ioremap failed\n", __func__);
-		return -ENOMEM;
-	}
-
-	clk_data = mtk_alloc_clk_data(nr);
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base,
-				    &mt7988_clk_lock, clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_mcusys_data;
-	}
-	return r;
-
-free_mcusys_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
-
-static const struct of_device_id of_match_clk_mt7988_topckgen[] = {
-	{
-		.compatible = "mediatek,mt7988-topckgen",
-	},
-	{}
-};
-
-static struct platform_driver clk_mt7988_topckgen_drv = {
-	.probe = clk_mt7988_topckgen_probe,
-	.driver = {
-		.name = "clk-mt7988-topckgen",
-		.of_match_table = of_match_clk_mt7988_topckgen,
-	},
-};
-builtin_platform_driver(clk_mt7988_topckgen_drv);
-
-static const struct of_device_id of_match_clk_mt7988_mcusys[] = {
-	{
-		.compatible = "mediatek,mt7988-mcusys",
-	},
-	{}
-};
-
-static struct platform_driver clk_mt7988_mcusys_drv = {
-	.probe = clk_mt7988_mcusys_probe,
-	.driver = {
-		.name = "clk-mt7988-mcusys",
-		.of_match_table = of_match_clk_mt7988_mcusys,
-	},
-};
-builtin_platform_driver(clk_mt7988_mcusys_drv);
\ No newline at end of file
diff --git a/target/linux/mediatek/files-5.15/drivers/net/phy/mediatek-2p5ge.c b/target/linux/mediatek/files-5.15/drivers/net/phy/mediatek-2p5ge.c
deleted file mode 100644
index c12e6b8eb6f8f6..00000000000000
--- a/target/linux/mediatek/files-5.15/drivers/net/phy/mediatek-2p5ge.c
+++ /dev/null
@@ -1,262 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-#include <linux/bitfield.h>
-#include <linux/firmware.h>
-#include <linux/module.h>
-#include <linux/nvmem-consumer.h>
-#include <linux/of_address.h>
-#include <linux/of_platform.h>
-#include <linux/pinctrl/consumer.h>
-#include <linux/phy.h>
-
-#define MEDAITEK_2P5GE_PHY_DMB_FW "mediatek/mediatek-2p5ge-phy-dmb.bin"
-#define MEDIATEK_2P5GE_PHY_PMB_FW "mediatek/mediatek-2p5ge-phy-pmb.bin"
-
-#define MD32_EN_CFG			0x18
-#define   MD32_EN			BIT(0)
-
-#define BASE100T_STATUS_EXTEND		0x10
-#define BASE1000T_STATUS_EXTEND		0x11
-#define EXTEND_CTRL_AND_STATUS		0x16
-
-#define PHY_AUX_CTRL_STATUS		0x1d
-#define   PHY_AUX_DPX_MASK		GENMASK(5, 5)
-#define   PHY_AUX_SPEED_MASK		GENMASK(4, 2)
-
-/* Registers on MDIO_MMD_VEND1 */
-#define MTK_PHY_LINK_STATUS_MISC	0xa2
-#define   MTK_PHY_FDX_ENABLE		BIT(5)
-
-/* Registers on MDIO_MMD_VEND2 */
-#define MTK_PHY_LED0_ON_CTRL		0x24
-#define   MTK_PHY_LED0_ON_LINK1000	BIT(0)
-#define   MTK_PHY_LED0_ON_LINK100	BIT(1)
-#define   MTK_PHY_LED0_ON_LINK10	BIT(2)
-#define   MTK_PHY_LED0_ON_LINK2500	BIT(7)
-#define   MTK_PHY_LED0_POLARITY		BIT(14)
-
-#define MTK_PHY_LED1_ON_CTRL		0x26
-#define   MTK_PHY_LED1_ON_FDX		BIT(4)
-#define   MTK_PHY_LED1_ON_HDX		BIT(5)
-#define   MTK_PHY_LED1_POLARITY		BIT(14)
-
-enum {
-	PHY_AUX_SPD_10 = 0,
-	PHY_AUX_SPD_100,
-	PHY_AUX_SPD_1000,
-	PHY_AUX_SPD_2500,
-};
-
-static int mt798x_2p5ge_phy_config_init(struct phy_device *phydev)
-{
-	int ret;
-	int i;
-	const struct firmware *fw;
-	struct device *dev = &phydev->mdio.dev;
-	struct device_node *np;
-	void __iomem *dmb_addr;
-	void __iomem *pmb_addr;
-	void __iomem *mcucsr_base;
-	u16 reg;
-	struct pinctrl *pinctrl;
-
-	np = of_find_compatible_node(NULL, NULL, "mediatek,2p5gphy-fw");
-	if (!np)
-		return -ENOENT;
-
-	dmb_addr = of_iomap(np, 0);
-	if (!dmb_addr)
-		return -ENOMEM;
-	pmb_addr = of_iomap(np, 1);
-	if (!pmb_addr)
-		return -ENOMEM;
-	mcucsr_base = of_iomap(np, 2);
-	if (!mcucsr_base)
-		return -ENOMEM;
-
-	ret = request_firmware(&fw, MEDAITEK_2P5GE_PHY_DMB_FW, dev);
-	if (ret) {
-		dev_err(dev, "failed to load firmware: %s, ret: %d\n",
-			MEDAITEK_2P5GE_PHY_DMB_FW, ret);
-		return ret;
-	}
-	for (i = 0; i < fw->size - 1; i += 4)
-		writel(*((uint32_t *)(fw->data + i)), dmb_addr + i);
-	release_firmware(fw);
-
-	ret = request_firmware(&fw, MEDIATEK_2P5GE_PHY_PMB_FW, dev);
-	if (ret) {
-		dev_err(dev, "failed to load firmware: %s, ret: %d\n",
-			MEDIATEK_2P5GE_PHY_PMB_FW, ret);
-		return ret;
-	}
-	for (i = 0; i < fw->size - 1; i += 4)
-		writel(*((uint32_t *)(fw->data + i)), pmb_addr + i);
-	release_firmware(fw);
-
-	reg = readw(mcucsr_base + MD32_EN_CFG);
-	writew(reg | MD32_EN, mcucsr_base + MD32_EN_CFG);
-	dev_dbg(dev, "Firmware loading/trigger ok.\n");
-
-	/* Setup LED */
-	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
-			   MTK_PHY_LED0_POLARITY);
-
-	phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
-			 MTK_PHY_LED0_ON_LINK10 |
-			 MTK_PHY_LED0_ON_LINK100 |
-			 MTK_PHY_LED0_ON_LINK1000 |
-			 MTK_PHY_LED0_ON_LINK2500);
-
-	phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL,
-			 MTK_PHY_LED1_ON_FDX | MTK_PHY_LED1_ON_HDX);
-
-	pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "i2p5gbe-led");
-	if (IS_ERR(pinctrl)) {
-		dev_err(&phydev->mdio.dev, "Fail to set LED pins!\n");
-		return PTR_ERR(pinctrl);
-	}
-
-	return 0;
-}
-
-static int mt798x_2p5ge_phy_config_aneg(struct phy_device *phydev)
-{
-	bool changed = false;
-	u32 adv;
-	int ret;
-
-	if (phydev->autoneg == AUTONEG_DISABLE) {
-		/* Configure half duplex with genphy_setup_forced,
-		 * because genphy_c45_pma_setup_forced does not support.
-		 */
-		return phydev->duplex != DUPLEX_FULL
-			? genphy_setup_forced(phydev)
-			: genphy_c45_pma_setup_forced(phydev);
-	}
-
-	ret = genphy_c45_an_config_aneg(phydev);
-	if (ret < 0)
-		return ret;
-	if (ret > 0)
-		changed = true;
-
-	adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
-	ret = phy_modify_changed(phydev, MII_CTRL1000,
-				 ADVERTISE_1000FULL | ADVERTISE_1000HALF,
-				 adv);
-	if (ret < 0)
-		return ret;
-	if (ret > 0)
-		changed = true;
-
-	return genphy_c45_check_and_restart_aneg(phydev, changed);
-}
-
-static int mt798x_2p5ge_phy_get_features(struct phy_device *phydev)
-{
-	int ret;
-
-	ret = genphy_read_abilities(phydev);
-	if (ret)
-		return ret;
-
-	/* We don't support HDX at MAC layer on mt798x.
-	 * So mask phy's HDX capabilities, too.
-	 */
-	linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
-			 phydev->supported);
-	linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
-			 phydev->supported);
-	linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
-			 phydev->supported);
-	linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
-			 phydev->supported);
-	linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
-
-	return 0;
-}
-
-static int mt798x_2p5ge_phy_read_status(struct phy_device *phydev)
-{
-	int ret;
-
-	ret = genphy_update_link(phydev);
-	if (ret)
-		return ret;
-
-	phydev->speed = SPEED_UNKNOWN;
-	phydev->duplex = DUPLEX_UNKNOWN;
-	phydev->pause = 0;
-	phydev->asym_pause = 0;
-
-	if (!phydev->link)
-		return 0;
-
-	if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) {
-		ret = genphy_c45_read_lpa(phydev);
-		if (ret < 0)
-			return ret;
-
-		/* Read the link partner's 1G advertisement */
-		ret = phy_read(phydev, MII_STAT1000);
-		if (ret < 0)
-			return ret;
-		mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, ret);
-	} else if (phydev->autoneg == AUTONEG_DISABLE) {
-		linkmode_zero(phydev->lp_advertising);
-	}
-
-	ret = phy_read(phydev, PHY_AUX_CTRL_STATUS);
-	if (ret < 0)
-		return ret;
-
-	switch (FIELD_GET(PHY_AUX_SPEED_MASK, ret)) {
-	case PHY_AUX_SPD_10:
-		phydev->speed = SPEED_10;
-		break;
-	case PHY_AUX_SPD_100:
-		phydev->speed = SPEED_100;
-		break;
-	case PHY_AUX_SPD_1000:
-		phydev->speed = SPEED_1000;
-		break;
-	case PHY_AUX_SPD_2500:
-		phydev->speed = SPEED_2500;
-		phydev->duplex = DUPLEX_FULL; /* 2.5G must be FDX */
-		break;
-	}
-
-	ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LINK_STATUS_MISC);
-	if (ret < 0)
-		return ret;
-
-	phydev->duplex = (ret & MTK_PHY_FDX_ENABLE) ? DUPLEX_FULL : DUPLEX_HALF;
-
-	return 0;
-}
-
-static struct phy_driver mtk_gephy_driver[] = {
-	{
-		PHY_ID_MATCH_EXACT(0x00339c11),
-		.name		= "MediaTek MT798x 2.5GbE PHY",
-		.config_init	= mt798x_2p5ge_phy_config_init,
-		.config_aneg    = mt798x_2p5ge_phy_config_aneg,
-		.get_features	= mt798x_2p5ge_phy_get_features,
-		.read_status	= mt798x_2p5ge_phy_read_status,
-	},
-};
-
-module_phy_driver(mtk_gephy_driver);
-
-static struct mdio_device_id __maybe_unused mtk_2p5ge_phy_tbl[] = {
-	{ PHY_ID_MATCH_VENDOR(0x00339c00) },
-	{ }
-};
-
-MODULE_DESCRIPTION("MediaTek 2.5Gb Ethernet PHY driver");
-MODULE_AUTHOR("SkyLake Huang <SkyLake.Huang@mediatek.com>");
-MODULE_LICENSE("GPL");
-
-MODULE_DEVICE_TABLE(mdio, mtk_2p5ge_phy_tbl);
-MODULE_FIRMWARE(MEDAITEK_2P5GE_PHY_DMB_FW);
-MODULE_FIRMWARE(MEDIATEK_2P5GE_PHY_PMB_FW);
diff --git a/target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7981.c b/target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7981.c
deleted file mode 100644
index 7c082dd207b491..00000000000000
--- a/target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7981.c
+++ /dev/null
@@ -1,1041 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * The MT7981 driver based on Linux generic pinctrl binding.
- *
- * Copyright (C) 2020 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- */
-
-#include "pinctrl-moore.h"
-
-#define MT7981_PIN(_number, _name)				\
-	MTK_PIN(_number, _name, 0, _number, DRV_GRP4)
-
-#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits)	\
-	PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,	\
-		       _x_bits, 32, 0)
-
-#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits)	\
-	PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,	\
-		      _x_bits, 32, 1)
-
-static const struct mtk_pin_field_calc mt7981_pin_mode_range[] = {
-	PIN_FIELD(0, 56, 0x300, 0x10, 0, 4),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_dir_range[] = {
-	PIN_FIELD(0, 56, 0x0, 0x10, 0, 1),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_di_range[] = {
-	PIN_FIELD(0, 56, 0x200, 0x10, 0, 1),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_do_range[] = {
-	PIN_FIELD(0, 56, 0x100, 0x10, 0, 1),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_ies_range[] = {
-	PIN_FIELD_BASE(0, 0, 1, 0x10, 0x10, 1, 1),
-	PIN_FIELD_BASE(1, 1, 1, 0x10, 0x10, 0, 1),
-	PIN_FIELD_BASE(2, 2, 5, 0x20, 0x10, 6, 1),
-	PIN_FIELD_BASE(3, 3, 4, 0x20, 0x10, 6, 1),
-	PIN_FIELD_BASE(4, 4, 4, 0x20, 0x10, 2, 1),
-	PIN_FIELD_BASE(5, 5, 4, 0x20, 0x10, 1, 1),
-	PIN_FIELD_BASE(6, 6, 4, 0x20, 0x10, 3, 1),
-	PIN_FIELD_BASE(7, 7, 4, 0x20, 0x10, 0, 1),
-	PIN_FIELD_BASE(8, 8, 4, 0x20, 0x10, 4, 1),
-
-	PIN_FIELD_BASE(9, 9, 5, 0x20, 0x10, 9, 1),
-	PIN_FIELD_BASE(10, 10, 5, 0x20, 0x10, 8, 1),
-	PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1),
-	PIN_FIELD_BASE(12, 12, 5, 0x20, 0x10, 7, 1),
-	PIN_FIELD_BASE(13, 13, 5, 0x20, 0x10, 11, 1),
-
-	PIN_FIELD_BASE(14, 14, 4, 0x20, 0x10, 8, 1),
-
-	PIN_FIELD_BASE(15, 15, 2, 0x20, 0x10, 0, 1),
-	PIN_FIELD_BASE(16, 16, 2, 0x20, 0x10, 1, 1),
-	PIN_FIELD_BASE(17, 17, 2, 0x20, 0x10, 5, 1),
-	PIN_FIELD_BASE(18, 18, 2, 0x20, 0x10, 4, 1),
-	PIN_FIELD_BASE(19, 19, 2, 0x20, 0x10, 2, 1),
-	PIN_FIELD_BASE(20, 20, 2, 0x20, 0x10, 3, 1),
-	PIN_FIELD_BASE(21, 21, 2, 0x20, 0x10, 6, 1),
-	PIN_FIELD_BASE(22, 22, 2, 0x20, 0x10, 7, 1),
-	PIN_FIELD_BASE(23, 23, 2, 0x20, 0x10, 10, 1),
-	PIN_FIELD_BASE(24, 24, 2, 0x20, 0x10, 9, 1),
-	PIN_FIELD_BASE(25, 25, 2, 0x20, 0x10, 8, 1),
-
-	PIN_FIELD_BASE(26, 26, 5, 0x20, 0x10, 0, 1),
-	PIN_FIELD_BASE(27, 27, 5, 0x20, 0x10, 4, 1),
-	PIN_FIELD_BASE(28, 28, 5, 0x20, 0x10, 3, 1),
-	PIN_FIELD_BASE(29, 29, 5, 0x20, 0x10, 1, 1),
-	PIN_FIELD_BASE(30, 30, 5, 0x20, 0x10, 2, 1),
-	PIN_FIELD_BASE(31, 31, 5, 0x20, 0x10, 5, 1),
-
-	PIN_FIELD_BASE(32, 32, 1, 0x10, 0x10, 2, 1),
-	PIN_FIELD_BASE(33, 33, 1, 0x10, 0x10, 3, 1),
-
-	PIN_FIELD_BASE(34, 34, 4, 0x20, 0x10, 5, 1),
-	PIN_FIELD_BASE(35, 35, 4, 0x20, 0x10, 7, 1),
-
-	PIN_FIELD_BASE(36, 36, 3, 0x10, 0x10, 2, 1),
-	PIN_FIELD_BASE(37, 37, 3, 0x10, 0x10, 3, 1),
-	PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 0, 1),
-	PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 1, 1),
-
-	PIN_FIELD_BASE(40, 40, 7, 0x30, 0x10, 1, 1),
-	PIN_FIELD_BASE(41, 41, 7, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(42, 42, 7, 0x30, 0x10, 9, 1),
-	PIN_FIELD_BASE(43, 43, 7, 0x30, 0x10, 7, 1),
-	PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1),
-	PIN_FIELD_BASE(45, 45, 7, 0x30, 0x10, 3, 1),
-	PIN_FIELD_BASE(46, 46, 7, 0x30, 0x10, 4, 1),
-	PIN_FIELD_BASE(47, 47, 7, 0x30, 0x10, 5, 1),
-	PIN_FIELD_BASE(48, 48, 7, 0x30, 0x10, 6, 1),
-	PIN_FIELD_BASE(49, 49, 7, 0x30, 0x10, 2, 1),
-
-	PIN_FIELD_BASE(50, 50, 6, 0x10, 0x10, 0, 1),
-	PIN_FIELD_BASE(51, 51, 6, 0x10, 0x10, 2, 1),
-	PIN_FIELD_BASE(52, 52, 6, 0x10, 0x10, 3, 1),
-	PIN_FIELD_BASE(53, 53, 6, 0x10, 0x10, 4, 1),
-	PIN_FIELD_BASE(54, 54, 6, 0x10, 0x10, 5, 1),
-	PIN_FIELD_BASE(55, 55, 6, 0x10, 0x10, 6, 1),
-	PIN_FIELD_BASE(56, 56, 6, 0x10, 0x10, 1, 1),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_smt_range[] = {
-	PIN_FIELD_BASE(0, 0, 1, 0x60, 0x10, 1, 1),
-	PIN_FIELD_BASE(1, 1, 1, 0x60, 0x10, 0, 1),
-	PIN_FIELD_BASE(2, 2, 5, 0x90, 0x10, 6, 1),
-	PIN_FIELD_BASE(3, 3, 4, 0x80, 0x10, 6, 1),
-	PIN_FIELD_BASE(4, 4, 4, 0x80, 0x10, 2, 1),
-	PIN_FIELD_BASE(5, 5, 4, 0x80, 0x10, 1, 1),
-	PIN_FIELD_BASE(6, 6, 4, 0x80, 0x10, 3, 1),
-	PIN_FIELD_BASE(7, 7, 4, 0x80, 0x10, 0, 1),
-	PIN_FIELD_BASE(8, 8, 4, 0x80, 0x10, 4, 1),
-
-	PIN_FIELD_BASE(9, 9, 5, 0x90, 0x10, 9, 1),
-	PIN_FIELD_BASE(10, 10, 5, 0x90, 0x10, 8, 1),
-	PIN_FIELD_BASE(11, 11, 5, 0x90, 0x10, 10, 1),
-	PIN_FIELD_BASE(12, 12, 5, 0x90, 0x10, 7, 1),
-	PIN_FIELD_BASE(13, 13, 5, 0x90, 0x10, 11, 1),
-
-	PIN_FIELD_BASE(14, 14, 4, 0x80, 0x10, 8, 1),
-
-	PIN_FIELD_BASE(15, 15, 2, 0x90, 0x10, 0, 1),
-	PIN_FIELD_BASE(16, 16, 2, 0x90, 0x10, 1, 1),
-	PIN_FIELD_BASE(17, 17, 2, 0x90, 0x10, 5, 1),
-	PIN_FIELD_BASE(18, 18, 2, 0x90, 0x10, 4, 1),
-	PIN_FIELD_BASE(19, 19, 2, 0x90, 0x10, 2, 1),
-	PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1),
-	PIN_FIELD_BASE(21, 21, 2, 0x90, 0x10, 6, 1),
-	PIN_FIELD_BASE(22, 22, 2, 0x90, 0x10, 7, 1),
-	PIN_FIELD_BASE(23, 23, 2, 0x90, 0x10, 10, 1),
-	PIN_FIELD_BASE(24, 24, 2, 0x90, 0x10, 9, 1),
-	PIN_FIELD_BASE(25, 25, 2, 0x90, 0x10, 8, 1),
-
-	PIN_FIELD_BASE(26, 26, 5, 0x90, 0x10, 0, 1),
-	PIN_FIELD_BASE(27, 27, 5, 0x90, 0x10, 4, 1),
-	PIN_FIELD_BASE(28, 28, 5, 0x90, 0x10, 3, 1),
-	PIN_FIELD_BASE(29, 29, 5, 0x90, 0x10, 1, 1),
-	PIN_FIELD_BASE(30, 30, 5, 0x90, 0x10, 2, 1),
-	PIN_FIELD_BASE(31, 31, 5, 0x90, 0x10, 5, 1),
-
-	PIN_FIELD_BASE(32, 32, 1, 0x60, 0x10, 2, 1),
-	PIN_FIELD_BASE(33, 33, 1, 0x60, 0x10, 3, 1),
-
-	PIN_FIELD_BASE(34, 34, 4, 0x80, 0x10, 5, 1),
-	PIN_FIELD_BASE(35, 35, 4, 0x80, 0x10, 7, 1),
-
-	PIN_FIELD_BASE(36, 36, 3, 0x60, 0x10, 2, 1),
-	PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 3, 1),
-	PIN_FIELD_BASE(38, 38, 3, 0x60, 0x10, 0, 1),
-	PIN_FIELD_BASE(39, 39, 3, 0x60, 0x10, 1, 1),
-
-	PIN_FIELD_BASE(40, 40, 7, 0x70, 0x10, 1, 1),
-	PIN_FIELD_BASE(41, 41, 7, 0x70, 0x10, 0, 1),
-	PIN_FIELD_BASE(42, 42, 7, 0x70, 0x10, 9, 1),
-	PIN_FIELD_BASE(43, 43, 7, 0x70, 0x10, 7, 1),
-	PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1),
-	PIN_FIELD_BASE(45, 45, 7, 0x70, 0x10, 3, 1),
-	PIN_FIELD_BASE(46, 46, 7, 0x70, 0x10, 4, 1),
-	PIN_FIELD_BASE(47, 47, 7, 0x70, 0x10, 5, 1),
-	PIN_FIELD_BASE(48, 48, 7, 0x70, 0x10, 6, 1),
-	PIN_FIELD_BASE(49, 49, 7, 0x70, 0x10, 2, 1),
-
-	PIN_FIELD_BASE(50, 50, 6, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(51, 51, 6, 0x50, 0x10, 2, 1),
-	PIN_FIELD_BASE(52, 52, 6, 0x50, 0x10, 3, 1),
-	PIN_FIELD_BASE(53, 53, 6, 0x50, 0x10, 4, 1),
-	PIN_FIELD_BASE(54, 54, 6, 0x50, 0x10, 5, 1),
-	PIN_FIELD_BASE(55, 55, 6, 0x50, 0x10, 6, 1),
-	PIN_FIELD_BASE(56, 56, 6, 0x50, 0x10, 1, 1),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_pu_range[] = {
-	PIN_FIELD_BASE(40, 40, 7, 0x50, 0x10, 1, 1),
-	PIN_FIELD_BASE(41, 41, 7, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(42, 42, 7, 0x50, 0x10, 9, 1),
-	PIN_FIELD_BASE(43, 43, 7, 0x50, 0x10, 7, 1),
-	PIN_FIELD_BASE(44, 44, 7, 0x50, 0x10, 8, 1),
-	PIN_FIELD_BASE(45, 45, 7, 0x50, 0x10, 3, 1),
-	PIN_FIELD_BASE(46, 46, 7, 0x50, 0x10, 4, 1),
-	PIN_FIELD_BASE(47, 47, 7, 0x50, 0x10, 5, 1),
-	PIN_FIELD_BASE(48, 48, 7, 0x50, 0x10, 6, 1),
-	PIN_FIELD_BASE(49, 49, 7, 0x50, 0x10, 2, 1),
-
-	PIN_FIELD_BASE(50, 50, 6, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(51, 51, 6, 0x30, 0x10, 2, 1),
-	PIN_FIELD_BASE(52, 52, 6, 0x30, 0x10, 3, 1),
-	PIN_FIELD_BASE(53, 53, 6, 0x30, 0x10, 4, 1),
-	PIN_FIELD_BASE(54, 54, 6, 0x30, 0x10, 5, 1),
-	PIN_FIELD_BASE(55, 55, 6, 0x30, 0x10, 6, 1),
-	PIN_FIELD_BASE(56, 56, 6, 0x30, 0x10, 1, 1),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_pd_range[] = {
-	PIN_FIELD_BASE(40, 40, 7, 0x40, 0x10, 1, 1),
-	PIN_FIELD_BASE(41, 41, 7, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(42, 42, 7, 0x40, 0x10, 9, 1),
-	PIN_FIELD_BASE(43, 43, 7, 0x40, 0x10, 7, 1),
-	PIN_FIELD_BASE(44, 44, 7, 0x40, 0x10, 8, 1),
-	PIN_FIELD_BASE(45, 45, 7, 0x40, 0x10, 3, 1),
-	PIN_FIELD_BASE(46, 46, 7, 0x40, 0x10, 4, 1),
-	PIN_FIELD_BASE(47, 47, 7, 0x40, 0x10, 5, 1),
-	PIN_FIELD_BASE(48, 48, 7, 0x40, 0x10, 6, 1),
-	PIN_FIELD_BASE(49, 49, 7, 0x40, 0x10, 2, 1),
-
-	PIN_FIELD_BASE(50, 50, 6, 0x20, 0x10, 0, 1),
-	PIN_FIELD_BASE(51, 51, 6, 0x20, 0x10, 2, 1),
-	PIN_FIELD_BASE(52, 52, 6, 0x20, 0x10, 3, 1),
-	PIN_FIELD_BASE(53, 53, 6, 0x20, 0x10, 4, 1),
-	PIN_FIELD_BASE(54, 54, 6, 0x20, 0x10, 5, 1),
-	PIN_FIELD_BASE(55, 55, 6, 0x20, 0x10, 6, 1),
-	PIN_FIELD_BASE(56, 56, 6, 0x20, 0x10, 1, 1),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_drv_range[] = {
-	PIN_FIELD_BASE(0, 0, 1, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(1, 1, 1, 0x00, 0x10, 0, 3),
-
-	PIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 18, 3),
-
-	PIN_FIELD_BASE(3, 3, 4, 0x00, 0x10, 18, 1),
-	PIN_FIELD_BASE(4, 4, 4, 0x00, 0x10, 6, 1),
-	PIN_FIELD_BASE(5, 5, 4, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(6, 6, 4, 0x00, 0x10, 9, 3),
-	PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 12, 3),
-
-	PIN_FIELD_BASE(9, 9, 5, 0x00, 0x10, 27, 3),
-	PIN_FIELD_BASE(10, 10, 5, 0x00, 0x10, 24, 3),
-	PIN_FIELD_BASE(11, 11, 5, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(12, 12, 5, 0x00, 0x10, 21, 3),
-	PIN_FIELD_BASE(13, 13, 5, 0x00, 0x10, 3, 3),
-
-	PIN_FIELD_BASE(14, 14, 4, 0x00, 0x10, 27, 3),
-
-	PIN_FIELD_BASE(15, 15, 2, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(16, 16, 2, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(17, 17, 2, 0x00, 0x10, 15, 3),
-	PIN_FIELD_BASE(18, 18, 2, 0x00, 0x10, 12, 3),
-	PIN_FIELD_BASE(19, 19, 2, 0x00, 0x10, 6, 3),
-	PIN_FIELD_BASE(20, 20, 2, 0x00, 0x10, 9, 3),
-	PIN_FIELD_BASE(21, 21, 2, 0x00, 0x10, 18, 3),
-	PIN_FIELD_BASE(22, 22, 2, 0x00, 0x10, 21, 3),
-	PIN_FIELD_BASE(23, 23, 2, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(24, 24, 2, 0x00, 0x10, 27, 3),
-	PIN_FIELD_BASE(25, 25, 2, 0x00, 0x10, 24, 3),
-
-	PIN_FIELD_BASE(26, 26, 5, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(27, 27, 5, 0x00, 0x10, 12, 3),
-	PIN_FIELD_BASE(28, 28, 5, 0x00, 0x10, 9, 3),
-	PIN_FIELD_BASE(29, 29, 5, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(30, 30, 5, 0x00, 0x10, 6, 3),
-	PIN_FIELD_BASE(31, 31, 5, 0x00, 0x10, 15, 3),
-
-	PIN_FIELD_BASE(32, 32, 1, 0x00, 0x10, 9, 3),
-	PIN_FIELD_BASE(33, 33, 1, 0x00, 0x10, 12, 3),
-
-	PIN_FIELD_BASE(34, 34, 4, 0x00, 0x10, 15, 3),
-	PIN_FIELD_BASE(35, 35, 4, 0x00, 0x10, 21, 3),
-
-	PIN_FIELD_BASE(36, 36, 3, 0x00, 0x10, 6, 3),
-	PIN_FIELD_BASE(37, 37, 3, 0x00, 0x10, 9, 3),
-	PIN_FIELD_BASE(38, 38, 3, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(39, 39, 3, 0x00, 0x10, 3, 3),
-
-	PIN_FIELD_BASE(40, 40, 7, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(41, 41, 7, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(42, 42, 7, 0x00, 0x10, 27, 3),
-	PIN_FIELD_BASE(43, 43, 7, 0x00, 0x10, 21, 3),
-	PIN_FIELD_BASE(44, 44, 7, 0x00, 0x10, 24, 3),
-	PIN_FIELD_BASE(45, 45, 7, 0x00, 0x10, 9, 3),
-	PIN_FIELD_BASE(46, 46, 7, 0x00, 0x10, 12, 3),
-	PIN_FIELD_BASE(47, 47, 7, 0x00, 0x10, 15, 3),
-	PIN_FIELD_BASE(48, 48, 7, 0x00, 0x10, 18, 3),
-	PIN_FIELD_BASE(49, 49, 7, 0x00, 0x10, 6, 3),
-
-	PIN_FIELD_BASE(50, 50, 6, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(51, 51, 6, 0x00, 0x10, 6, 3),
-	PIN_FIELD_BASE(52, 52, 6, 0x00, 0x10, 9, 3),
-	PIN_FIELD_BASE(53, 53, 6, 0x00, 0x10, 12, 3),
-	PIN_FIELD_BASE(54, 54, 6, 0x00, 0x10, 15, 3),
-	PIN_FIELD_BASE(55, 55, 6, 0x00, 0x10, 18, 3),
-	PIN_FIELD_BASE(56, 56, 6, 0x00, 0x10, 3, 3),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_pupd_range[] = {
-	PIN_FIELD_BASE(0, 0, 1, 0x20, 0x10, 1, 1),
-	PIN_FIELD_BASE(1, 1, 1, 0x20, 0x10, 0, 1),
-	PIN_FIELD_BASE(2, 2, 5, 0x30, 0x10, 6, 1),
-	PIN_FIELD_BASE(3, 3, 4, 0x30, 0x10, 6, 1),
-	PIN_FIELD_BASE(4, 4, 4, 0x30, 0x10, 2, 1),
-	PIN_FIELD_BASE(5, 5, 4, 0x30, 0x10, 1, 1),
-	PIN_FIELD_BASE(6, 6, 4, 0x30, 0x10, 3, 1),
-	PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 4, 1),
-
-	PIN_FIELD_BASE(9, 9, 5, 0x30, 0x10, 9, 1),
-	PIN_FIELD_BASE(10, 10, 5, 0x30, 0x10, 8, 1),
-	PIN_FIELD_BASE(11, 11, 5, 0x30, 0x10, 10, 1),
-	PIN_FIELD_BASE(12, 12, 5, 0x30, 0x10, 7, 1),
-	PIN_FIELD_BASE(13, 13, 5, 0x30, 0x10, 11, 1),
-
-	PIN_FIELD_BASE(14, 14, 4, 0x30, 0x10, 8, 1),
-
-	PIN_FIELD_BASE(15, 15, 2, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(16, 16, 2, 0x30, 0x10, 1, 1),
-	PIN_FIELD_BASE(17, 17, 2, 0x30, 0x10, 5, 1),
-	PIN_FIELD_BASE(18, 18, 2, 0x30, 0x10, 4, 1),
-	PIN_FIELD_BASE(19, 19, 2, 0x30, 0x10, 2, 1),
-	PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1),
-	PIN_FIELD_BASE(21, 21, 2, 0x30, 0x10, 6, 1),
-	PIN_FIELD_BASE(22, 22, 2, 0x30, 0x10, 7, 1),
-	PIN_FIELD_BASE(23, 23, 2, 0x30, 0x10, 10, 1),
-	PIN_FIELD_BASE(24, 24, 2, 0x30, 0x10, 9, 1),
-	PIN_FIELD_BASE(25, 25, 2, 0x30, 0x10, 8, 1),
-
-	PIN_FIELD_BASE(26, 26, 5, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(27, 27, 5, 0x30, 0x10, 4, 1),
-	PIN_FIELD_BASE(28, 28, 5, 0x30, 0x10, 3, 1),
-	PIN_FIELD_BASE(29, 29, 5, 0x30, 0x10, 1, 1),
-	PIN_FIELD_BASE(30, 30, 5, 0x30, 0x10, 2, 1),
-	PIN_FIELD_BASE(31, 31, 5, 0x30, 0x10, 5, 1),
-
-	PIN_FIELD_BASE(32, 32, 1, 0x20, 0x10, 2, 1),
-	PIN_FIELD_BASE(33, 33, 1, 0x20, 0x10, 3, 1),
-
-	PIN_FIELD_BASE(34, 34, 4, 0x30, 0x10, 5, 1),
-	PIN_FIELD_BASE(35, 35, 4, 0x30, 0x10, 7, 1),
-
-	PIN_FIELD_BASE(36, 36, 3, 0x20, 0x10, 2, 1),
-	PIN_FIELD_BASE(37, 37, 3, 0x20, 0x10, 3, 1),
-	PIN_FIELD_BASE(38, 38, 3, 0x20, 0x10, 0, 1),
-	PIN_FIELD_BASE(39, 39, 3, 0x20, 0x10, 1, 1),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_r0_range[] = {
-	PIN_FIELD_BASE(0, 0, 1, 0x30, 0x10, 1, 1),
-	PIN_FIELD_BASE(1, 1, 1, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(2, 2, 5, 0x40, 0x10, 6, 1),
-	PIN_FIELD_BASE(3, 3, 4, 0x40, 0x10, 6, 1),
-	PIN_FIELD_BASE(4, 4, 4, 0x40, 0x10, 2, 1),
-	PIN_FIELD_BASE(5, 5, 4, 0x40, 0x10, 1, 1),
-	PIN_FIELD_BASE(6, 6, 4, 0x40, 0x10, 3, 1),
-	PIN_FIELD_BASE(7, 7, 4, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1),
-
-	PIN_FIELD_BASE(9, 9, 5, 0x40, 0x10, 9, 1),
-	PIN_FIELD_BASE(10, 10, 5, 0x40, 0x10, 8, 1),
-	PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1),
-	PIN_FIELD_BASE(12, 12, 5, 0x40, 0x10, 7, 1),
-	PIN_FIELD_BASE(13, 13, 5, 0x40, 0x10, 11, 1),
-
-	PIN_FIELD_BASE(14, 14, 4, 0x40, 0x10, 8, 1),
-
-	PIN_FIELD_BASE(15, 15, 2, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(16, 16, 2, 0x40, 0x10, 1, 1),
-	PIN_FIELD_BASE(17, 17, 2, 0x40, 0x10, 5, 1),
-	PIN_FIELD_BASE(18, 18, 2, 0x40, 0x10, 4, 1),
-	PIN_FIELD_BASE(19, 19, 2, 0x40, 0x10, 2, 1),
-	PIN_FIELD_BASE(20, 20, 2, 0x40, 0x10, 3, 1),
-	PIN_FIELD_BASE(21, 21, 2, 0x40, 0x10, 6, 1),
-	PIN_FIELD_BASE(22, 22, 2, 0x40, 0x10, 7, 1),
-	PIN_FIELD_BASE(23, 23, 2, 0x40, 0x10, 10, 1),
-	PIN_FIELD_BASE(24, 24, 2, 0x40, 0x10, 9, 1),
-	PIN_FIELD_BASE(25, 25, 2, 0x40, 0x10, 8, 1),
-
-	PIN_FIELD_BASE(26, 26, 5, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(27, 27, 5, 0x40, 0x10, 4, 1),
-	PIN_FIELD_BASE(28, 28, 5, 0x40, 0x10, 3, 1),
-	PIN_FIELD_BASE(29, 29, 5, 0x40, 0x10, 1, 1),
-	PIN_FIELD_BASE(30, 30, 5, 0x40, 0x10, 2, 1),
-	PIN_FIELD_BASE(31, 31, 5, 0x40, 0x10, 5, 1),
-
-	PIN_FIELD_BASE(32, 32, 1, 0x30, 0x10, 2, 1),
-	PIN_FIELD_BASE(33, 33, 1, 0x30, 0x10, 3, 1),
-
-	PIN_FIELD_BASE(34, 34, 4, 0x40, 0x10, 5, 1),
-	PIN_FIELD_BASE(35, 35, 4, 0x40, 0x10, 7, 1),
-
-	PIN_FIELD_BASE(36, 36, 3, 0x30, 0x10, 2, 1),
-	PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 3, 1),
-	PIN_FIELD_BASE(38, 38, 3, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(39, 39, 3, 0x30, 0x10, 1, 1),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_r1_range[] = {
-	PIN_FIELD_BASE(0, 0, 1, 0x40, 0x10, 1, 1),
-	PIN_FIELD_BASE(1, 1, 1, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(2, 2, 5, 0x50, 0x10, 6, 1),
-	PIN_FIELD_BASE(3, 3, 4, 0x50, 0x10, 6, 1),
-	PIN_FIELD_BASE(4, 4, 4, 0x50, 0x10, 2, 1),
-	PIN_FIELD_BASE(5, 5, 4, 0x50, 0x10, 1, 1),
-	PIN_FIELD_BASE(6, 6, 4, 0x50, 0x10, 3, 1),
-	PIN_FIELD_BASE(7, 7, 4, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(8, 8, 4, 0x50, 0x10, 4, 1),
-
-	PIN_FIELD_BASE(9, 9, 5, 0x50, 0x10, 9, 1),
-	PIN_FIELD_BASE(10, 10, 5, 0x50, 0x10, 8, 1),
-	PIN_FIELD_BASE(11, 11, 5, 0x50, 0x10, 10, 1),
-	PIN_FIELD_BASE(12, 12, 5, 0x50, 0x10, 7, 1),
-	PIN_FIELD_BASE(13, 13, 5, 0x50, 0x10, 11, 1),
-
-	PIN_FIELD_BASE(14, 14, 4, 0x50, 0x10, 8, 1),
-
-	PIN_FIELD_BASE(15, 15, 2, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(16, 16, 2, 0x50, 0x10, 1, 1),
-	PIN_FIELD_BASE(17, 17, 2, 0x50, 0x10, 5, 1),
-	PIN_FIELD_BASE(18, 18, 2, 0x50, 0x10, 4, 1),
-	PIN_FIELD_BASE(19, 19, 2, 0x50, 0x10, 2, 1),
-	PIN_FIELD_BASE(20, 20, 2, 0x50, 0x10, 3, 1),
-	PIN_FIELD_BASE(21, 21, 2, 0x50, 0x10, 6, 1),
-	PIN_FIELD_BASE(22, 22, 2, 0x50, 0x10, 7, 1),
-	PIN_FIELD_BASE(23, 23, 2, 0x50, 0x10, 10, 1),
-	PIN_FIELD_BASE(24, 24, 2, 0x50, 0x10, 9, 1),
-	PIN_FIELD_BASE(25, 25, 2, 0x50, 0x10, 8, 1),
-
-	PIN_FIELD_BASE(26, 26, 5, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(27, 27, 5, 0x50, 0x10, 4, 1),
-	PIN_FIELD_BASE(28, 28, 5, 0x50, 0x10, 3, 1),
-	PIN_FIELD_BASE(29, 29, 5, 0x50, 0x10, 1, 1),
-	PIN_FIELD_BASE(30, 30, 5, 0x50, 0x10, 2, 1),
-	PIN_FIELD_BASE(31, 31, 5, 0x50, 0x10, 5, 1),
-
-	PIN_FIELD_BASE(32, 32, 1, 0x40, 0x10, 2, 1),
-	PIN_FIELD_BASE(33, 33, 1, 0x40, 0x10, 3, 1),
-
-	PIN_FIELD_BASE(34, 34, 4, 0x50, 0x10, 5, 1),
-	PIN_FIELD_BASE(35, 35, 4, 0x50, 0x10, 7, 1),
-
-	PIN_FIELD_BASE(36, 36, 3, 0x40, 0x10, 2, 1),
-	PIN_FIELD_BASE(37, 37, 3, 0x40, 0x10, 3, 1),
-	PIN_FIELD_BASE(38, 38, 3, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(39, 39, 3, 0x40, 0x10, 1, 1),
-};
-
-static const unsigned int mt7981_pull_type[] = {
-	MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PUPD_R1R0_TYPE,/*7*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*8*/ MTK_PULL_PUPD_R1R0_TYPE,/*9*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PUPD_R1R0_TYPE,/*13*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*16*/ MTK_PULL_PUPD_R1R0_TYPE,/*17*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/
-	MTK_PULL_PU_PD_TYPE,/*40*/ MTK_PULL_PU_PD_TYPE,/*41*/
-	MTK_PULL_PU_PD_TYPE,/*42*/ MTK_PULL_PU_PD_TYPE,/*43*/
-	MTK_PULL_PU_PD_TYPE,/*44*/ MTK_PULL_PU_PD_TYPE,/*45*/
-	MTK_PULL_PU_PD_TYPE,/*46*/ MTK_PULL_PU_PD_TYPE,/*47*/
-	MTK_PULL_PU_PD_TYPE,/*48*/ MTK_PULL_PU_PD_TYPE,/*49*/
-	MTK_PULL_PU_PD_TYPE,/*50*/ MTK_PULL_PU_PD_TYPE,/*51*/
-	MTK_PULL_PU_PD_TYPE,/*52*/ MTK_PULL_PU_PD_TYPE,/*53*/
-	MTK_PULL_PU_PD_TYPE,/*54*/ MTK_PULL_PU_PD_TYPE,/*55*/
-	MTK_PULL_PU_PD_TYPE,/*56*/
-};
-
-static const struct mtk_pin_reg_calc mt7981_reg_cals[] = {
-	[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7981_pin_mode_range),
-	[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7981_pin_dir_range),
-	[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7981_pin_di_range),
-	[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7981_pin_do_range),
-	[PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7981_pin_smt_range),
-	[PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7981_pin_ies_range),
-	[PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7981_pin_pu_range),
-	[PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7981_pin_pd_range),
-	[PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7981_pin_drv_range),
-	[PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7981_pin_pupd_range),
-	[PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7981_pin_r0_range),
-	[PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7981_pin_r1_range),
-};
-
-static const struct mtk_pin_desc mt7981_pins[] = {
-	MT7981_PIN(0, "GPIO_WPS"),
-	MT7981_PIN(1, "GPIO_RESET"),
-	MT7981_PIN(2, "SYS_WATCHDOG"),
-	MT7981_PIN(3, "PCIE_PERESET_N"),
-	MT7981_PIN(4, "JTAG_JTDO"),
-	MT7981_PIN(5, "JTAG_JTDI"),
-	MT7981_PIN(6, "JTAG_JTMS"),
-	MT7981_PIN(7, "JTAG_JTCLK"),
-	MT7981_PIN(8, "JTAG_JTRST_N"),
-	MT7981_PIN(9, "WO_JTAG_JTDO"),
-	MT7981_PIN(10, "WO_JTAG_JTDI"),
-	MT7981_PIN(11, "WO_JTAG_JTMS"),
-	MT7981_PIN(12, "WO_JTAG_JTCLK"),
-	MT7981_PIN(13, "WO_JTAG_JTRST_N"),
-	MT7981_PIN(14, "USB_VBUS"),
-	MT7981_PIN(15, "PWM0"),
-	MT7981_PIN(16, "SPI0_CLK"),
-	MT7981_PIN(17, "SPI0_MOSI"),
-	MT7981_PIN(18, "SPI0_MISO"),
-	MT7981_PIN(19, "SPI0_CS"),
-	MT7981_PIN(20, "SPI0_HOLD"),
-	MT7981_PIN(21, "SPI0_WP"),
-	MT7981_PIN(22, "SPI1_CLK"),
-	MT7981_PIN(23, "SPI1_MOSI"),
-	MT7981_PIN(24, "SPI1_MISO"),
-	MT7981_PIN(25, "SPI1_CS"),
-	MT7981_PIN(26, "SPI2_CLK"),
-	MT7981_PIN(27, "SPI2_MOSI"),
-	MT7981_PIN(28, "SPI2_MISO"),
-	MT7981_PIN(29, "SPI2_CS"),
-	MT7981_PIN(30, "SPI2_HOLD"),
-	MT7981_PIN(31, "SPI2_WP"),
-	MT7981_PIN(32, "UART0_RXD"),
-	MT7981_PIN(33, "UART0_TXD"),
-	MT7981_PIN(34, "PCIE_CLK_REQ"),
-	MT7981_PIN(35, "PCIE_WAKE_N"),
-	MT7981_PIN(36, "SMI_MDC"),
-	MT7981_PIN(37, "SMI_MDIO"),
-	MT7981_PIN(38, "GBE_INT"),
-	MT7981_PIN(39, "GBE_RESET"),
-	MT7981_PIN(40, "WF_DIG_RESETB"),
-	MT7981_PIN(41, "WF_CBA_RESETB"),
-	MT7981_PIN(42, "WF_XO_REQ"),
-	MT7981_PIN(43, "WF_TOP_CLK"),
-	MT7981_PIN(44, "WF_TOP_DATA"),
-	MT7981_PIN(45, "WF_HB1"),
-	MT7981_PIN(46, "WF_HB2"),
-	MT7981_PIN(47, "WF_HB3"),
-	MT7981_PIN(48, "WF_HB4"),
-	MT7981_PIN(49, "WF_HB0"),
-	MT7981_PIN(50, "WF_HB0_B"),
-	MT7981_PIN(51, "WF_HB5"),
-	MT7981_PIN(52, "WF_HB6"),
-	MT7981_PIN(53, "WF_HB7"),
-	MT7981_PIN(54, "WF_HB8"),
-	MT7981_PIN(55, "WF_HB9"),
-	MT7981_PIN(56, "WF_HB10"),
-};
-
-/* List all groups consisting of these pins dedicated to the enablement of
- * certain hardware block and the corresponding mode for all of the pins.
- * The hardware probably has multiple combinations of these pinouts.
- */
-
-/* WA_AICE */
-static int mt7981_wa_aice1_pins[] = { 0, 1, };
-static int mt7981_wa_aice1_funcs[] = { 2, 2, };
-
-static int mt7981_wa_aice2_pins[] = { 0, 1, };
-static int mt7981_wa_aice2_funcs[] = { 3, 3, };
-
-static int mt7981_wa_aice3_pins[] = { 28, 29, };
-static int mt7981_wa_aice3_funcs[] = { 3, 3, };
-
-static int mt7981_wm_aice1_pins[] = { 9, 10, };
-static int mt7981_wm_aice1_funcs[] = { 2, 2, };
-
-static int mt7981_wm_aice2_pins[] = { 30, 31, };
-static int mt7981_wm_aice2_funcs[] = { 5, 5, };
-
-/* WM_UART */
-static int mt7981_wm_uart_0_pins[] = { 0, 1, };
-static int mt7981_wm_uart_0_funcs[] = { 5, 5, };
-
-static int mt7981_wm_uart_1_pins[] = { 20, 21, };
-static int mt7981_wm_uart_1_funcs[] = { 4, 4, };
-
-static int mt7981_wm_uart_2_pins[] = { 30, 31, };
-static int mt7981_wm_uart_2_funcs[] = { 3, 3, };
-
-/* DFD */
-static int mt7981_dfd_pins[] = { 0, 1, 4, 5, };
-static int mt7981_dfd_funcs[] = { 5, 5, 6, 6, };
-
-/* SYS_WATCHDOG */
-static int mt7981_watchdog_pins[] = { 2, };
-static int mt7981_watchdog_funcs[] = { 1, };
-
-static int mt7981_watchdog1_pins[] = { 13, };
-static int mt7981_watchdog1_funcs[] = { 5, };
-
-/* PCIE_PERESET_N */
-static int mt7981_pcie_pereset_pins[] = { 3, };
-static int mt7981_pcie_pereset_funcs[] = { 1, };
-
-/* JTAG */
-static int mt7981_jtag_pins[] = { 4, 5, 6, 7, 8, };
-static int mt7981_jtag_funcs[] = { 1, 1, 1, 1, 1, };
-
-/* WM_JTAG */
-static int mt7981_wm_jtag_0_pins[] = { 4, 5, 6, 7, 8, };
-static int mt7981_wm_jtag_0_funcs[] = { 2, 2, 2, 2, 2, };
-
-static int mt7981_wm_jtag_1_pins[] = { 20, 21, 22, 23, 24, };
-static int mt7981_wm_jtag_1_funcs[] = { 5, 5, 5, 5, 5, };
-
-/* WO0_JTAG */
-static int mt7981_wo0_jtag_0_pins[] = { 9, 10, 11, 12, 13, };
-static int mt7981_wo0_jtag_0_funcs[] = { 1, 1, 1, 1, 1, };
-
-static int mt7981_wo0_jtag_1_pins[] = { 25, 26, 27, 28, 29, };
-static int mt7981_wo0_jtag_1_funcs[] = { 5, 5, 5, 5, 5, };
-
-/* UART2 */
-static int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, };
-static int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, };
-
-static int mt7981_uart2_0_tx_rx_pins[] = { 4, 5, };
-static int mt7981_uart2_0_tx_rx_funcs[] = { 3, 3, };
-
-/* GBE_LED0 */
-static int mt7981_gbe_led0_pins[] = { 8, };
-static int mt7981_gbe_led0_funcs[] = { 3, };
-
-/* PTA_EXT */
-static int mt7981_pta_ext_0_pins[] = { 4, 5, 6, };
-static int mt7981_pta_ext_0_funcs[] = { 4, 4, 4, };
-
-static int mt7981_pta_ext_1_pins[] = { 22, 23, 24, };
-static int mt7981_pta_ext_1_funcs[] = { 4, 4, 4, };
-
-/* PWM2 */
-static int mt7981_pwm2_pins[] = { 7, };
-static int mt7981_pwm2_funcs[] = { 4, };
-
-/* NET_WO0_UART_TXD */
-static int mt7981_net_wo0_uart_txd_0_pins[] = { 8, };
-static int mt7981_net_wo0_uart_txd_0_funcs[] = { 4, };
-
-static int mt7981_net_wo0_uart_txd_1_pins[] = { 14, };
-static int mt7981_net_wo0_uart_txd_1_funcs[] = { 3, };
-
-static int mt7981_net_wo0_uart_txd_2_pins[] = { 15, };
-static int mt7981_net_wo0_uart_txd_2_funcs[] = { 4, };
-
-/* SPI1 */
-static int mt7981_spi1_0_pins[] = { 4, 5, 6, 7, };
-static int mt7981_spi1_0_funcs[] = { 5, 5, 5, 5, };
-
-/* I2C */
-static int mt7981_i2c0_0_pins[] = { 6, 7, };
-static int mt7981_i2c0_0_funcs[] = { 6, 6, };
-
-static int mt7981_i2c0_1_pins[] = { 30, 31, };
-static int mt7981_i2c0_1_funcs[] = { 4, 4, };
-
-static int mt7981_i2c0_2_pins[] = { 36, 37, };
-static int mt7981_i2c0_2_funcs[] = { 2, 2, };
-
-static int mt7981_u2_phy_i2c_pins[] = { 30, 31, };
-static int mt7981_u2_phy_i2c_funcs[] = { 6, 6, };
-
-static int mt7981_u3_phy_i2c_pins[] = { 32, 33, };
-static int mt7981_u3_phy_i2c_funcs[] = { 3, 3, };
-
-static int mt7981_sgmii1_phy_i2c_pins[] = { 32, 33, };
-static int mt7981_sgmii1_phy_i2c_funcs[] = { 2, 2, };
-
-static int mt7981_sgmii0_phy_i2c_pins[] = { 32, 33, };
-static int mt7981_sgmii0_phy_i2c_funcs[] = { 5, 5, };
-
-/* DFD_NTRST */
-static int mt7981_dfd_ntrst_pins[] = { 8, };
-static int mt7981_dfd_ntrst_funcs[] = { 6, };
-
-/* PWM0 */
-static int mt7981_pwm0_0_pins[] = { 13, };
-static int mt7981_pwm0_0_funcs[] = { 2, };
-
-static int mt7981_pwm0_1_pins[] = { 15, };
-static int mt7981_pwm0_1_funcs[] = { 1, };
-
-/* PWM1 */
-static int mt7981_pwm1_0_pins[] = { 14, };
-static int mt7981_pwm1_0_funcs[] = { 2, };
-
-static int mt7981_pwm1_1_pins[] = { 15, };
-static int mt7981_pwm1_1_funcs[] = { 3, };
-
-/* GBE_LED1 */
-static int mt7981_gbe_led1_pins[] = { 13, };
-static int mt7981_gbe_led1_funcs[] = { 3, };
-
-/* PCM */
-static int mt7981_pcm_pins[] = { 9, 10, 11, 12, 13, 25 };
-static int mt7981_pcm_funcs[] = { 4, 4, 4, 4, 4, 4, };
-
-/* UDI */
-static int mt7981_udi_pins[] = { 9, 10, 11, 12, 13, };
-static int mt7981_udi_funcs[] = { 6, 6, 6, 6, 6, };
-
-/* DRV_VBUS */
-static int mt7981_drv_vbus_pins[] = { 14, };
-static int mt7981_drv_vbus_funcs[] = { 1, };
-
-/* EMMC */
-static int mt7981_emmc_45_pins[] = { 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, };
-static int mt7981_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
-
-/* SNFI */
-static int mt7981_snfi_pins[] = { 16, 17, 18, 19, 20, 21, };
-static int mt7981_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, };
-
-/* SPI0 */
-static int mt7981_spi0_pins[] = { 16, 17, 18, 19, };
-static int mt7981_spi0_funcs[] = { 1, 1, 1, 1, };
-
-/* SPI0 */
-static int mt7981_spi0_wp_hold_pins[] = { 20, 21, };
-static int mt7981_spi0_wp_hold_funcs[] = { 1, 1, };
-
-/* SPI1 */
-static int mt7981_spi1_1_pins[] = { 22, 23, 24, 25, };
-static int mt7981_spi1_1_funcs[] = { 1, 1, 1, 1, };
-
-/* SPI2 */
-static int mt7981_spi2_pins[] = { 26, 27, 28, 29, };
-static int mt7981_spi2_funcs[] = { 1, 1, 1, 1, };
-
-/* SPI2 */
-static int mt7981_spi2_wp_hold_pins[] = { 30, 31, };
-static int mt7981_spi2_wp_hold_funcs[] = { 1, 1, };
-
-/* UART1 */
-static int mt7981_uart1_0_pins[] = { 16, 17, 18, 19, };
-static int mt7981_uart1_0_funcs[] = { 4, 4, 4, 4, };
-
-static int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, };
-static int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, };
-
-static int mt7981_uart1_2_pins[] = { 9, 10, };
-static int mt7981_uart1_2_funcs[] = { 2, 2, };
-
-/* UART2 */
-static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, };
-static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, };
-
-/* UART0 */
-static int mt7981_uart0_pins[] = { 32, 33, };
-static int mt7981_uart0_funcs[] = { 1, 1, };
-
-/* PCIE_CLK_REQ */
-static int mt7981_pcie_clk_pins[] = { 34, };
-static int mt7981_pcie_clk_funcs[] = { 2, };
-
-/* PCIE_WAKE_N */
-static int mt7981_pcie_wake_pins[] = { 35, };
-static int mt7981_pcie_wake_funcs[] = { 2, };
-
-/* MDC_MDIO */
-static int mt7981_smi_mdc_mdio_pins[] = { 36, 37, };
-static int mt7981_smi_mdc_mdio_funcs[] = { 1, 1, };
-
-static int mt7981_gbe_ext_mdc_mdio_pins[] = { 36, 37, };
-static int mt7981_gbe_ext_mdc_mdio_funcs[] = { 3, 3, };
-
-/* WF0_MODE1 */
-static int mt7981_wf0_mode1_pins[] = { 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56 };
-static int mt7981_wf0_mode1_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
-
-/* WF0_MODE3 */
-static int mt7981_wf0_mode3_pins[] = { 45, 46, 47, 48, 49, 51 };
-static int mt7981_wf0_mode3_funcs[] = { 2, 2, 2, 2, 2, 2 };
-
-/* WF2G_LED */
-static int mt7981_wf2g_led0_pins[] = { 30, };
-static int mt7981_wf2g_led0_funcs[] = { 2, };
-
-static int mt7981_wf2g_led1_pins[] = { 34, };
-static int mt7981_wf2g_led1_funcs[] = { 1, };
-
-/* WF5G_LED */
-static int mt7981_wf5g_led0_pins[] = { 31, };
-static int mt7981_wf5g_led0_funcs[] = { 2, };
-
-static int mt7981_wf5g_led1_pins[] = { 35, };
-static int mt7981_wf5g_led1_funcs[] = { 1, };
-
-/* MT7531_INT */
-static int mt7981_mt7531_int_pins[] = { 38, };
-static int mt7981_mt7531_int_funcs[] = { 1, };
-
-/* ANT_SEL */
-static int mt7981_ant_sel_pins[] = { 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 34, 35 };
-static int mt7981_ant_sel_funcs[] = { 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6 };
-
-static const struct group_desc mt7981_groups[] = {
-	/* @GPIO(0,1): WA_AICE(2) */
-	PINCTRL_PIN_GROUP("wa_aice1", mt7981_wa_aice1),
-	/* @GPIO(0,1): WA_AICE(3) */
-	PINCTRL_PIN_GROUP("wa_aice2", mt7981_wa_aice2),
-	/* @GPIO(0,1): WM_UART(5) */
-	PINCTRL_PIN_GROUP("wm_uart_0", mt7981_wm_uart_0),
-	/* @GPIO(0,1,4,5): DFD(6) */
-	PINCTRL_PIN_GROUP("dfd", mt7981_dfd),
-	/* @GPIO(2): SYS_WATCHDOG(1) */
-	PINCTRL_PIN_GROUP("watchdog", mt7981_watchdog),
-	/* @GPIO(3): PCIE_PERESET_N(1) */
-	PINCTRL_PIN_GROUP("pcie_pereset", mt7981_pcie_pereset),
-	/* @GPIO(4,8) JTAG(1) */
-	PINCTRL_PIN_GROUP("jtag", mt7981_jtag),
-	/* @GPIO(4,8) WM_JTAG(2) */
-	PINCTRL_PIN_GROUP("wm_jtag_0", mt7981_wm_jtag_0),
-	/* @GPIO(9,13) WO0_JTAG(1) */
-	PINCTRL_PIN_GROUP("wo0_jtag_0", mt7981_wo0_jtag_0),
-	/* @GPIO(4,7) WM_JTAG(3) */
-	PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_0),
-	/* @GPIO(4,5) WM_JTAG(4) */
-	PINCTRL_PIN_GROUP("uart2_0_tx_rx", mt7981_uart2_0_tx_rx),
-	/* @GPIO(8) GBE_LED0(3) */
-	PINCTRL_PIN_GROUP("gbe_led0", mt7981_gbe_led0),
-	/* @GPIO(4,6) PTA_EXT(4) */
-	PINCTRL_PIN_GROUP("pta_ext_0", mt7981_pta_ext_0),
-	/* @GPIO(7) PWM2(4) */
-	PINCTRL_PIN_GROUP("pwm2", mt7981_pwm2),
-	/* @GPIO(8) NET_WO0_UART_TXD(4) */
-	PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7981_net_wo0_uart_txd_0),
-	/* @GPIO(4,7) SPI1(5) */
-	PINCTRL_PIN_GROUP("spi1_0", mt7981_spi1_0),
-	/* @GPIO(6,7) I2C(5) */
-	PINCTRL_PIN_GROUP("i2c0_0", mt7981_i2c0_0),
-	/* @GPIO(0,1,4,5): DFD_NTRST(6) */
-	PINCTRL_PIN_GROUP("dfd_ntrst", mt7981_dfd_ntrst),
-	/* @GPIO(9,10): WM_AICE(2) */
-	PINCTRL_PIN_GROUP("wm_aice1", mt7981_wm_aice1),
-	/* @GPIO(13): PWM0(2) */
-	PINCTRL_PIN_GROUP("pwm0_0", mt7981_pwm0_0),
-	/* @GPIO(15): PWM0(1) */
-	PINCTRL_PIN_GROUP("pwm0_1", mt7981_pwm0_1),
-	/* @GPIO(14): PWM1(2) */
-	PINCTRL_PIN_GROUP("pwm1_0", mt7981_pwm1_0),
-	/* @GPIO(15): PWM1(3) */
-	PINCTRL_PIN_GROUP("pwm1_1", mt7981_pwm1_1),
-	/* @GPIO(14) NET_WO0_UART_TXD(3) */
-	PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7981_net_wo0_uart_txd_1),
-	/* @GPIO(15) NET_WO0_UART_TXD(4) */
-	PINCTRL_PIN_GROUP("net_wo0_uart_txd_2", mt7981_net_wo0_uart_txd_2),
-	/* @GPIO(13) GBE_LED0(3) */
-	PINCTRL_PIN_GROUP("gbe_led1", mt7981_gbe_led1),
-	/* @GPIO(9,13) PCM(4) */
-	PINCTRL_PIN_GROUP("pcm", mt7981_pcm),
-	/* @GPIO(13): SYS_WATCHDOG1(5) */
-	PINCTRL_PIN_GROUP("watchdog1", mt7981_watchdog1),
-	/* @GPIO(9,13) UDI(4) */
-	PINCTRL_PIN_GROUP("udi", mt7981_udi),
-	/* @GPIO(14) DRV_VBUS(1) */
-	PINCTRL_PIN_GROUP("drv_vbus", mt7981_drv_vbus),
-	/* @GPIO(15,25): EMMC(2) */
-	PINCTRL_PIN_GROUP("emmc_45", mt7981_emmc_45),
-	/* @GPIO(16,21): SNFI(3) */
-	PINCTRL_PIN_GROUP("snfi", mt7981_snfi),
-	/* @GPIO(16,19): SPI0(1) */
-	PINCTRL_PIN_GROUP("spi0", mt7981_spi0),
-	/* @GPIO(20,21): SPI0(1) */
-	PINCTRL_PIN_GROUP("spi0_wp_hold", mt7981_spi0_wp_hold),
-	/* @GPIO(22,25) SPI1(1) */
-	PINCTRL_PIN_GROUP("spi1_1", mt7981_spi1_1),
-	/* @GPIO(26,29): SPI2(1) */
-	PINCTRL_PIN_GROUP("spi2", mt7981_spi2),
-	/* @GPIO(30,31): SPI0(1) */
-	PINCTRL_PIN_GROUP("spi2_wp_hold", mt7981_spi2_wp_hold),
-	/* @GPIO(16,19): UART1(4) */
-	PINCTRL_PIN_GROUP("uart1_0", mt7981_uart1_0),
-	/* @GPIO(26,29): UART1(2) */
-	PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1),
-	/* @GPIO(9,10): UART1(2) */
-	PINCTRL_PIN_GROUP("uart1_2", mt7981_uart1_2),
-	/* @GPIO(22,25): UART1(3) */
-	PINCTRL_PIN_GROUP("uart2_1", mt7981_uart2_1),
-	/* @GPIO(22,24) PTA_EXT(4) */
-	PINCTRL_PIN_GROUP("pta_ext_1", mt7981_pta_ext_1),
-	/* @GPIO(20,21): WM_UART(4) */
-	PINCTRL_PIN_GROUP("wm_aurt_1", mt7981_wm_uart_1),
-	/* @GPIO(30,31): WM_UART(3) */
-	PINCTRL_PIN_GROUP("wm_aurt_2", mt7981_wm_uart_2),
-	/* @GPIO(20,24) WM_JTAG(5) */
-	PINCTRL_PIN_GROUP("wm_jtag_1", mt7981_wm_jtag_1),
-	/* @GPIO(25,29) WO0_JTAG(5) */
-	PINCTRL_PIN_GROUP("wo0_jtag_1", mt7981_wo0_jtag_1),
-	/* @GPIO(28,29): WA_AICE(3) */
-	PINCTRL_PIN_GROUP("wa_aice3", mt7981_wa_aice3),
-	/* @GPIO(30,31): WM_AICE(5) */
-	PINCTRL_PIN_GROUP("wm_aice2", mt7981_wm_aice2),
-	/* @GPIO(30,31): I2C(4) */
-	PINCTRL_PIN_GROUP("i2c0_1", mt7981_i2c0_1),
-	/* @GPIO(30,31): I2C(6) */
-	PINCTRL_PIN_GROUP("u2_phy_i2c", mt7981_u2_phy_i2c),
-	/* @GPIO(32,33): I2C(1) */
-	PINCTRL_PIN_GROUP("uart0", mt7981_uart0),
-	/* @GPIO(32,33): I2C(2) */
-	PINCTRL_PIN_GROUP("sgmii1_phy_i2c", mt7981_sgmii1_phy_i2c),
-	/* @GPIO(32,33): I2C(3) */
-	PINCTRL_PIN_GROUP("u3_phy_i2c", mt7981_u3_phy_i2c),
-	/* @GPIO(32,33): I2C(5) */
-	PINCTRL_PIN_GROUP("sgmii0_phy_i2c", mt7981_sgmii0_phy_i2c),
-	/* @GPIO(34): PCIE_CLK_REQ(2) */
-	PINCTRL_PIN_GROUP("pcie_clk", mt7981_pcie_clk),
-	/* @GPIO(35): PCIE_WAKE_N(2) */
-	PINCTRL_PIN_GROUP("pcie_wake", mt7981_pcie_wake),
-	/* @GPIO(36,37): I2C(2) */
-	PINCTRL_PIN_GROUP("i2c0_2", mt7981_i2c0_2),
-	/* @GPIO(36,37): MDC_MDIO(1) */
-	PINCTRL_PIN_GROUP("smi_mdc_mdio", mt7981_smi_mdc_mdio),
-	/* @GPIO(36,37): MDC_MDIO(3) */
-	PINCTRL_PIN_GROUP("gbe_ext_mdc_mdio", mt7981_gbe_ext_mdc_mdio),
-	/* @GPIO(69,85): WF0_MODE1(1) */
-	PINCTRL_PIN_GROUP("wf0_mode1", mt7981_wf0_mode1),
-	/* @GPIO(74,80): WF0_MODE3(3) */
-	PINCTRL_PIN_GROUP("wf0_mode3", mt7981_wf0_mode3),
-	/* @GPIO(30): WF2G_LED(2) */
-	PINCTRL_PIN_GROUP("wf2g_led0", mt7981_wf2g_led0),
-	/* @GPIO(34): WF2G_LED(1) */
-	PINCTRL_PIN_GROUP("wf2g_led1", mt7981_wf2g_led1),
-	/* @GPIO(31): WF5G_LED(2) */
-	PINCTRL_PIN_GROUP("wf5g_led0", mt7981_wf5g_led0),
-	/* @GPIO(35): WF5G_LED(1) */
-	PINCTRL_PIN_GROUP("wf5g_led1", mt7981_wf5g_led1),
-	/* @GPIO(38): MT7531_INT(1) */
-	PINCTRL_PIN_GROUP("mt7531_int", mt7981_mt7531_int),
-	/* @GPIO(14,15,26,17,18,19,20,21,22,23,24,25,34,35): ANT_SEL(1) */
-	PINCTRL_PIN_GROUP("ant_sel", mt7981_ant_sel),
-};
-
-/* Joint those groups owning the same capability in user point of view which
- * allows that people tend to use through the device tree.
- */
-static const char *mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2", "wm_aice1_1",
-	"wa_aice3", "wm_aice1_2", };
-static const char *mt7981_uart_groups[] = { "wm_uart_0", "uart2_0",
-	"uart1_2", "uart2_0_tx_rx",
-	"net_wo0_uart_txd_0", "net_wo0_uart_txd_1", "net_wo0_uart_txd_2",
-	"uart1_0", "uart1_1", "uart2_1", "wm_aurt_1", "wm_aurt_2", "uart0", };
-static const char *mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", };
-static const char *mt7981_wdt_groups[] = { "watchdog", "watchdog1", };
-static const char *mt7981_pcie_groups[] = { "pcie_pereset", "pcie_clk", "pcie_wake", };
-static const char *mt7981_jtag_groups[] = { "jtag", "wm_jtag_0", "wo0_jtag_0",
-	"wo0_jtag_1", "wm_jtag_1", };
-static const char *mt7981_led_groups[] = { "gbe_led0", "gbe_led1", "wf2g_led0",
-	"wf2g_led1", "wf5g_led0", "wf5g_led1", };
-static const char *mt7981_pta_groups[] = { "pta_ext_0", "pta_ext_1", };
-static const char *mt7981_pwm_groups[] = { "pwm2", "pwm0_0", "pwm0_1",
-	"pwm1_0", "pwm1_1", };
-static const char *mt7981_spi_groups[] = { "spi1_0", "spi0", "spi0_wp_hold", "spi1_1", "spi2",
-	"spi2_wp_hold", };
-static const char *mt7981_i2c_groups[] = { "i2c0_0", "i2c0_1", "u2_phy_i2c",
-	"sgmii1_phy_i2c", "u3_phy_i2c", "sgmii0_phy_i2c", "i2c0_2", };
-static const char *mt7981_pcm_groups[] = { "pcm", };
-static const char *mt7981_udi_groups[] = { "udi", };
-static const char *mt7981_usb_groups[] = { "drv_vbus", };
-static const char *mt7981_flash_groups[] = { "emmc_45", "snfi", };
-static const char *mt7981_ethernet_groups[] = { "smi_mdc_mdio", "gbe_ext_mdc_mdio",
-	"wf0_mode1", "wf0_mode3", "mt7531_int", };
-static const char *mt7981_ant_groups[] = { "ant_sel", };
-
-static const struct function_desc mt7981_functions[] = {
-	{"wa_aice",	mt7981_wa_aice_groups, ARRAY_SIZE(mt7981_wa_aice_groups)},
-	{"dfd",	mt7981_dfd_groups, ARRAY_SIZE(mt7981_dfd_groups)},
-	{"jtag", mt7981_jtag_groups, ARRAY_SIZE(mt7981_jtag_groups)},
-	{"pta", mt7981_pta_groups, ARRAY_SIZE(mt7981_pta_groups)},
-	{"pcm", mt7981_pcm_groups, ARRAY_SIZE(mt7981_pcm_groups)},
-	{"udi", mt7981_udi_groups, ARRAY_SIZE(mt7981_udi_groups)},
-	{"usb", mt7981_usb_groups, ARRAY_SIZE(mt7981_usb_groups)},
-	{"ant", mt7981_ant_groups, ARRAY_SIZE(mt7981_ant_groups)},
-	{"eth",	mt7981_ethernet_groups, ARRAY_SIZE(mt7981_ethernet_groups)},
-	{"i2c", mt7981_i2c_groups, ARRAY_SIZE(mt7981_i2c_groups)},
-	{"led",	mt7981_led_groups, ARRAY_SIZE(mt7981_led_groups)},
-	{"pwm",	mt7981_pwm_groups, ARRAY_SIZE(mt7981_pwm_groups)},
-	{"spi",	mt7981_spi_groups, ARRAY_SIZE(mt7981_spi_groups)},
-	{"uart", mt7981_uart_groups, ARRAY_SIZE(mt7981_uart_groups)},
-	{"watchdog", mt7981_wdt_groups, ARRAY_SIZE(mt7981_wdt_groups)},
-	{"flash", mt7981_flash_groups, ARRAY_SIZE(mt7981_flash_groups)},
-	{"pcie", mt7981_pcie_groups, ARRAY_SIZE(mt7981_pcie_groups)},
-};
-
-static const struct mtk_eint_hw mt7981_eint_hw = {
-	.port_mask = 7,
-	.ports     = 7,
-	.ap_num    = ARRAY_SIZE(mt7981_pins),
-	.db_cnt    = 16,
-};
-
-static const char * const mt7981_pinctrl_register_base_names[] = {
-	"gpio", "iocfg_rt", "iocfg_rm", "iocfg_rb",
-	"iocfg_lb", "iocfg_bl", "iocfg_tm", "iocfg_tl",
-};
-
-static struct mtk_pin_soc mt7981_data = {
-	.reg_cal = mt7981_reg_cals,
-	.pins = mt7981_pins,
-	.npins = ARRAY_SIZE(mt7981_pins),
-	.grps = mt7981_groups,
-	.ngrps = ARRAY_SIZE(mt7981_groups),
-	.funcs = mt7981_functions,
-	.nfuncs = ARRAY_SIZE(mt7981_functions),
-	.eint_hw = &mt7981_eint_hw,
-	.gpio_m = 0,
-	.ies_present = false,
-	.base_names = mt7981_pinctrl_register_base_names,
-	.nbase_names = ARRAY_SIZE(mt7981_pinctrl_register_base_names),
-	.bias_disable_set = mtk_pinconf_bias_disable_set,
-	.bias_disable_get = mtk_pinconf_bias_disable_get,
-	.bias_set = mtk_pinconf_bias_set,
-	.bias_get = mtk_pinconf_bias_get,
-	.pull_type = mt7981_pull_type,
-	.bias_set_combo = mtk_pinconf_bias_set_combo,
-	.bias_get_combo = mtk_pinconf_bias_get_combo,
-	.drive_set = mtk_pinconf_drive_set_rev1,
-	.drive_get = mtk_pinconf_drive_get_rev1,
-	.adv_pull_get = mtk_pinconf_adv_pull_get,
-	.adv_pull_set = mtk_pinconf_adv_pull_set,
-};
-
-static const struct of_device_id mt7981_pinctrl_of_match[] = {
-	{ .compatible = "mediatek,mt7981-pinctrl", },
-	{}
-};
-
-static int mt7981_pinctrl_probe(struct platform_device *pdev)
-{
-	return mtk_moore_pinctrl_probe(pdev, &mt7981_data);
-}
-
-static struct platform_driver mt7981_pinctrl_driver = {
-	.driver = {
-		.name = "mt7981-pinctrl",
-		.of_match_table = mt7981_pinctrl_of_match,
-	},
-	.probe = mt7981_pinctrl_probe,
-};
-
-static int __init mt7981_pinctrl_init(void)
-{
-	return platform_driver_register(&mt7981_pinctrl_driver);
-}
-arch_initcall(mt7981_pinctrl_init);
diff --git a/target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7986.c b/target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7986.c
deleted file mode 100644
index acaac9b38aa8a7..00000000000000
--- a/target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7986.c
+++ /dev/null
@@ -1,1011 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * The MT7986 driver based on Linux generic pinctrl binding.
- *
- * Copyright (C) 2021 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- */
-
-#include "pinctrl-moore.h"
-
-#define MT7986_PIN(_number, _name) MTK_PIN(_number, _name, 0, _number, DRV_GRP4)
-#define MT7986_NOT_BALLOUT_PIN(_number) { .number = _number, .name = NULL }
-
-#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,	\
-			_x_bits)	\
-		PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,	\
-			_x_bits, 32, 0)
-
-/**
- * enum - Locking variants of the iocfg bases
- *
- * MT7986 have multiple bases to program pin configuration listed as the below:
- * iocfg_rt:0x11c30000, iocfg_rb:0x11c40000, iocfg_lt:0x11e20000,
- * iocfg_lb:0x11e30000, iocfg_tr:0x11f00000, iocfg_tl:0x11f10000,
- * _i_based could be used to indicate what base the pin should be mapped into.
- *
- * Each iocfg register base control different group of pads on the SoC
- *
- *
- *  chip carrier
- *
- *      A  B  C  D  E  F  G  H
- *    +------------------------+
- *  8 | o  o  o  o  o  o  o  o |
- *  7 | o  o  o  o  o  o  o  o |
- *  6 | o  o  o  o  o  o  o  o |
- *  5 | o  o  o  o  o  o  o  o |
- *  4 | o  o  o  o  o  o  o  o |
- *  3 | o  o  o  o  o  o  o  o |
- *  2 | o  o  o  o  o  o  o  o |
- *  1 | o  o  o  o  o  o  o  o |
- *    +------------------------+
- *
- *  inside Chip carrier
- *
- *      A  B  C  D  E  F  G  H
- *    +------------------------+
- *  8 |                        |
- *  7 |        TL  TR          |
- *  6 |      +---------+       |
- *  5 |   LT |         | RT    |
- *  4 |      |         |       |
- *  3 |   LB |         | RB    |
- *  2 |      +---------+       |
- *  1 |                        |
- *    +------------------------+
- *
- */
-
-enum {
-	GPIO_BASE,
-	IOCFG_RT_BASE,
-	IOCFG_RB_BASE,
-	IOCFG_LT_BASE,
-	IOCFG_LB_BASE,
-	IOCFG_TR_BASE,
-	IOCFG_TL_BASE,
-};
-
-static const char *const mt7986_pinctrl_register_base_names[] = {
-	"gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt", "iocfg_lb", "iocfg_tr",
-	"iocfg_tl",
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_mode_range[] = {
-	PIN_FIELD(0, 100, 0x300, 0x10, 0, 4),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_dir_range[] = {
-	PIN_FIELD(0, 100, 0x0, 0x10, 0, 1),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_di_range[] = {
-	PIN_FIELD(0, 100, 0x200, 0x10, 0, 1),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_do_range[] = {
-	PIN_FIELD(0, 100, 0x100, 0x10, 0, 1),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_ies_range[] = {
-	PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x40, 0x10, 17, 1),
-	PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x20, 0x10, 10, 1),
-	PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x20, 0x10, 0, 1),
-	PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x20, 0x10, 0, 1),
-	PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x40, 0x10, 8, 1),
-	PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x40, 0x10, 2, 1),
-	PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x30, 0x10, 12, 1),
-	PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x30, 0x10, 18, 1),
-	PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x30, 0x10, 17, 1),
-	PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x30, 0x10, 15, 1),
-	PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x30, 0x10, 19, 1),
-	PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x30, 0x10, 23, 1),
-	PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x30, 0x10, 22, 1),
-	PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x30, 0x10, 21, 1),
-	PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x20, 0x10, 4, 1),
-	PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x20, 0x10, 8, 1),
-	PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x20, 0x10, 7, 1),
-	PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x20, 0x10, 5, 1),
-	PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x20, 0x10, 9, 1),
-	PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x40, 0x10, 18, 1),
-	PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x40, 0x10, 12, 1),
-	PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x40, 0x10, 22, 1),
-	PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x40, 0x10, 20, 1),
-	PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x40, 0x10, 26, 1),
-	PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x40, 0x10, 24, 1),
-	PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x30, 0x10, 2, 1),
-	PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x30, 0x10, 1, 1),
-	PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x30, 0x10, 10, 1),
-	PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x40, 0x10, 15, 1),
-	PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x40, 0x10, 14, 1),
-	PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x40, 0x10, 13, 1),
-	PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x40, 0x10, 16, 1),
-	PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x20, 0x10, 2, 1),
-	PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x30, 0x10, 1, 1),
-	PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x30, 0x10, 16, 1),
-	PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x30, 0x10, 14, 1),
-	PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x30, 0x10, 4, 1),
-	PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x30, 0x10, 6, 1),
-	PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x30, 0x10, 2, 1),
-	PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x30, 0x10, 9, 1),
-	PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x30, 0x10, 5, 1),
-	PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x30, 0x10, 1, 1),
-	PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x30, 0x10, 14, 1),
-	PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x30, 0x10, 12, 1),
-	PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x30, 0x10, 4, 1),
-	PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x30, 0x10, 2, 1),
-	PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x30, 0x10, 8, 1),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_smt_range[] = {
-	PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0xf0, 0x10, 17, 1),
-	PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x90, 0x10, 10, 1),
-	PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x90, 0x10, 0, 1),
-	PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0xf0, 0x10, 0, 1),
-	PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x90, 0x10, 0, 1),
-	PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0xf0, 0x10, 8, 1),
-	PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0xf0, 0x10, 2, 1),
-	PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0xc0, 0x10, 12, 1),
-	PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0xc0, 0x10, 18, 1),
-	PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0xc0, 0x10, 17, 1),
-	PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0xc0, 0x10, 15, 1),
-	PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0xc0, 0x10, 19, 1),
-	PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0xc0, 0x10, 23, 1),
-	PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0xc0, 0x10, 22, 1),
-	PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0xc0, 0x10, 21, 1),
-	PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x90, 0x10, 4, 1),
-	PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x90, 0x10, 8, 1),
-	PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x90, 0x10, 7, 1),
-	PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x90, 0x10, 5, 1),
-	PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x90, 0x10, 9, 1),
-	PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0xf0, 0x10, 18, 1),
-	PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0xf0, 0x10, 12, 1),
-	PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0xf0, 0x10, 22, 1),
-	PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0xf0, 0x10, 20, 1),
-	PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0xf0, 0x10, 26, 1),
-	PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0xf0, 0x10, 24, 1),
-	PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0xc0, 0x10, 2, 1),
-	PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0xc0, 0x10, 1, 1),
-	PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0xc0, 0x10, 0, 1),
-	PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0xc0, 0x10, 10, 1),
-	PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0xf0, 0x10, 15, 1),
-	PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0xf0, 0x10, 14, 1),
-	PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0xf0, 0x10, 13, 1),
-	PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0xf0, 0x10, 16, 1),
-	PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x90, 0x10, 2, 1),
-	PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x80, 0x10, 1, 1),
-	PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x80, 0x10, 0, 1),
-	PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x80, 0x10, 16, 1),
-	PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x80, 0x10, 14, 1),
-	PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x80, 0x10, 4, 1),
-	PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x80, 0x10, 6, 1),
-	PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x80, 0x10, 2, 1),
-	PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x80, 0x10, 9, 1),
-	PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x80, 0x10, 5, 1),
-	PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x70, 0x10, 1, 1),
-	PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x70, 0x10, 0, 1),
-	PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x70, 0x10, 14, 1),
-	PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x70, 0x10, 12, 1),
-	PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x70, 0x10, 4, 1),
-	PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x70, 0x10, 2, 1),
-	PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x70, 0x10, 8, 1),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_pu_range[] = {
-	PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x50, 0x10, 1, 1),
-	PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x50, 0x10, 16, 1),
-	PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x50, 0x10, 14, 1),
-	PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x50, 0x10, 4, 1),
-	PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x50, 0x10, 6, 1),
-	PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x50, 0x10, 2, 1),
-	PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x50, 0x10, 9, 1),
-	PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x50, 0x10, 5, 1),
-	PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x50, 0x10, 1, 1),
-	PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x50, 0x10, 14, 1),
-	PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x50, 0x10, 12, 1),
-	PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x50, 0x10, 4, 1),
-	PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x50, 0x10, 2, 1),
-	PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x50, 0x10, 8, 1),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_pd_range[] = {
-	PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x40, 0x10, 1, 1),
-	PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x40, 0x10, 16, 1),
-	PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x40, 0x10, 14, 1),
-	PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x40, 0x10, 4, 1),
-	PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x40, 0x10, 6, 1),
-	PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x40, 0x10, 2, 1),
-	PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x40, 0x10, 9, 1),
-	PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x40, 0x10, 5, 1),
-	PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x40, 0x10, 1, 1),
-	PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x40, 0x10, 14, 1),
-	PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x40, 0x10, 12, 1),
-	PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x40, 0x10, 4, 1),
-	PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x40, 0x10, 2, 1),
-	PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x40, 0x10, 8, 1),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_drv_range[] = {
-	PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x10, 0x10, 21, 3),
-	PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x10, 0x10, 0, 3),
-	PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x00, 0x10, 0, 1),
-	PIN_FIELD_BASE(5, 5, IOCFG_RB_BASE, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(6, 6, IOCFG_RB_BASE, 0x00, 0x10, 21, 3),
-	PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(11, 12, IOCFG_RB_BASE, 0x00, 0x10, 24, 3),
-	PIN_FIELD_BASE(13, 14, IOCFG_RB_BASE, 0x10, 0x10, 0, 3),
-	PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x10, 0x10, 6, 3),
-	PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x10, 0x10, 24, 3),
-	PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x10, 0x10, 21, 3),
-	PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x10, 0x10, 15, 3),
-	PIN_FIELD_BASE(28, 28, IOCFG_RT_BASE, 0x10, 0x10, 27, 3),
-	PIN_FIELD_BASE(29, 29, IOCFG_RT_BASE, 0x20, 0x10, 0, 3),
-	PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x20, 0x10, 9, 3),
-	PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x20, 0x10, 6, 3),
-	PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x20, 0x10, 3, 3),
-	PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x00, 0x10, 12, 3),
-	PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x00, 0x10, 24, 3),
-	PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x00, 0x10, 21, 3),
-	PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x00, 0x10, 15, 3),
-	PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x00, 0x10, 27, 3),
-	PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x10, 0x10, 27, 3),
-	PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x20, 0x10, 0, 3),
-	PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x10, 0x10, 6, 3),
-	PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x20, 0x10, 9, 3),
-	PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x20, 0x10, 3, 3),
-	PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x20, 0x10, 21, 3),
-	PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x20, 0x10, 15, 3),
-	PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x00, 0x10, 6, 3),
-	PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x10, 0x10, 0, 3),
-	PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x10, 0x10, 15, 3),
-	PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x10, 0x10, 12, 3),
-	PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x10, 0x10, 9, 3),
-	PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x10, 0x10, 18, 3),
-	PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x00, 0x10, 2, 3),
-	PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x10, 0x10, 18, 3),
-	PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x10, 0x10, 12, 3),
-	PIN_FIELD_BASE(74, 77, IOCFG_TR_BASE, 0x00, 0x10, 15, 3),
-	PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x00, 0x10, 6, 3),
-	PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x00, 0x10, 27, 3),
-	PIN_FIELD_BASE(81, 84, IOCFG_TR_BASE, 0x10, 0x10, 0, 3),
-	PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x00, 0x10, 12, 3),
-	PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x10, 0x10, 12, 3),
-	PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x10, 0x10, 6, 3),
-	PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x00, 0x10, 12, 3),
-	PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x00, 0x10, 6, 3),
-	PIN_FIELD_BASE(97, 98, IOCFG_TL_BASE, 0x00, 0x10, 24, 3),
-	PIN_FIELD_BASE(99, 100, IOCFG_TL_BASE, 0x10, 0x10, 2, 3),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_pupd_range[] = {
-	PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x60, 0x10, 17, 1),
-	PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x30, 0x10, 10, 1),
-	PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x60, 0x10, 0, 1),
-	PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x60, 0x10, 8, 1),
-	PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x60, 0x10, 2, 1),
-	PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x40, 0x10, 12, 1),
-	PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x40, 0x10, 18, 1),
-	PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x40, 0x10, 17, 1),
-	PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x40, 0x10, 15, 1),
-	PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x40, 0x10, 19, 1),
-	PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x40, 0x10, 23, 1),
-	PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x40, 0x10, 22, 1),
-	PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x40, 0x10, 21, 1),
-	PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x30, 0x10, 4, 1),
-	PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x30, 0x10, 8, 1),
-	PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x30, 0x10, 7, 1),
-	PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x30, 0x10, 5, 1),
-	PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x30, 0x10, 9, 1),
-	PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x60, 0x10, 18, 1),
-	PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x60, 0x10, 12, 1),
-	PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x60, 0x10, 23, 1),
-	PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x60, 0x10, 21, 1),
-	PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x60, 0x10, 27, 1),
-	PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x60, 0x10, 25, 1),
-	PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x40, 0x10, 2, 1),
-	PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x40, 0x10, 1, 1),
-	PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x40, 0x10, 10, 1),
-	PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x60, 0x10, 15, 1),
-	PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x60, 0x10, 14, 1),
-	PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x60, 0x10, 13, 1),
-	PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x60, 0x10, 16, 1),
-	PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x40, 0x10, 2, 1),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_r0_range[] = {
-	PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x70, 0x10, 17, 1),
-	PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x40, 0x10, 10, 1),
-	PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x70, 0x10, 0, 1),
-	PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x70, 0x10, 8, 1),
-	PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x70, 0x10, 2, 1),
-	PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x50, 0x10, 12, 1),
-	PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x50, 0x10, 18, 1),
-	PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x50, 0x10, 17, 1),
-	PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x50, 0x10, 15, 1),
-	PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x50, 0x10, 19, 1),
-	PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x50, 0x10, 23, 1),
-	PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x50, 0x10, 22, 1),
-	PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x50, 0x10, 21, 1),
-	PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x40, 0x10, 4, 1),
-	PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x40, 0x10, 8, 1),
-	PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x40, 0x10, 7, 1),
-	PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x40, 0x10, 5, 1),
-	PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x40, 0x10, 9, 1),
-	PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x70, 0x10, 18, 1),
-	PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x70, 0x10, 12, 1),
-	PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x70, 0x10, 23, 1),
-	PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x70, 0x10, 21, 1),
-	PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x70, 0x10, 27, 1),
-	PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x70, 0x10, 25, 1),
-	PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x50, 0x10, 2, 1),
-	PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x50, 0x10, 1, 1),
-	PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x50, 0x10, 10, 1),
-	PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x70, 0x10, 15, 1),
-	PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x70, 0x10, 14, 1),
-	PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x70, 0x10, 13, 1),
-	PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x70, 0x10, 16, 1),
-	PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x50, 0x10, 2, 1),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_r1_range[] = {
-	PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x80, 0x10, 17, 1),
-	PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x50, 0x10, 10, 1),
-	PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x60, 0x10, 0, 1),
-	PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x80, 0x10, 0, 1),
-	PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x80, 0x10, 8, 1),
-	PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x80, 0x10, 2, 1),
-	PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x60, 0x10, 12, 1),
-	PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x60, 0x10, 18, 1),
-	PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x60, 0x10, 17, 1),
-	PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x60, 0x10, 15, 1),
-	PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x60, 0x10, 19, 1),
-	PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x60, 0x10, 23, 1),
-	PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x60, 0x10, 22, 1),
-	PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x60, 0x10, 21, 1),
-	PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x50, 0x10, 4, 1),
-	PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x50, 0x10, 8, 1),
-	PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x50, 0x10, 7, 1),
-	PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x50, 0x10, 5, 1),
-	PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x50, 0x10, 9, 1),
-	PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x80, 0x10, 18, 1),
-	PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x80, 0x10, 12, 1),
-	PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x80, 0x10, 23, 1),
-	PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x80, 0x10, 21, 1),
-	PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x80, 0x10, 27, 1),
-	PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x80, 0x10, 25, 1),
-	PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x60, 0x10, 2, 1),
-	PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x60, 0x10, 1, 1),
-	PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x60, 0x10, 0, 1),
-	PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x60, 0x10, 10, 1),
-	PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x80, 0x10, 15, 1),
-	PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x80, 0x10, 14, 1),
-	PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x80, 0x10, 13, 1),
-	PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x80, 0x10, 16, 1),
-	PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x60, 0x10, 2, 1),
-};
-
-static const unsigned int mt7986_pull_type[] = {
-	MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PUPD_R1R0_TYPE,/*7*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*8*/ MTK_PULL_PUPD_R1R0_TYPE,/*9*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PUPD_R1R0_TYPE,/*13*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*16*/ MTK_PULL_PUPD_R1R0_TYPE,/*17*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PUPD_R1R0_TYPE,/*63*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/
-	MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/
-	MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/
-	MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/
-	MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/
-	MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/
-	MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/
-	MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/
-	MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/
-	MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/
-	MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/
-	MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/
-	MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/
-	MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/
-	MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/
-	MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/
-	MTK_PULL_PU_PD_TYPE,/*100*/
-};
-
-static const struct mtk_pin_reg_calc mt7986_reg_cals[] = {
-	[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7986_pin_mode_range),
-	[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7986_pin_dir_range),
-	[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7986_pin_di_range),
-	[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7986_pin_do_range),
-	[PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7986_pin_smt_range),
-	[PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7986_pin_ies_range),
-	[PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7986_pin_drv_range),
-	[PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7986_pin_pu_range),
-	[PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7986_pin_pd_range),
-	[PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7986_pin_pupd_range),
-	[PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7986_pin_r0_range),
-	[PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7986_pin_r1_range),
-};
-
-static const struct mtk_pin_desc mt7986a_pins[] = {
-	MT7986_PIN(0, "SYS_WATCHDOG"),
-	MT7986_PIN(1, "WF2G_LED"),
-	MT7986_PIN(2, "WF5G_LED"),
-	MT7986_PIN(3, "I2C_SCL"),
-	MT7986_PIN(4, "I2C_SDA"),
-	MT7986_PIN(5, "GPIO_0"),
-	MT7986_PIN(6, "GPIO_1"),
-	MT7986_PIN(7, "GPIO_2"),
-	MT7986_PIN(8, "GPIO_3"),
-	MT7986_PIN(9, "GPIO_4"),
-	MT7986_PIN(10, "GPIO_5"),
-	MT7986_PIN(11, "GPIO_6"),
-	MT7986_PIN(12, "GPIO_7"),
-	MT7986_PIN(13, "GPIO_8"),
-	MT7986_PIN(14, "GPIO_9"),
-	MT7986_PIN(15, "GPIO_10"),
-	MT7986_PIN(16, "GPIO_11"),
-	MT7986_PIN(17, "GPIO_12"),
-	MT7986_PIN(18, "GPIO_13"),
-	MT7986_PIN(19, "GPIO_14"),
-	MT7986_PIN(20, "GPIO_15"),
-	MT7986_PIN(21, "PWM0"),
-	MT7986_PIN(22, "PWM1"),
-	MT7986_PIN(23, "SPI0_CLK"),
-	MT7986_PIN(24, "SPI0_MOSI"),
-	MT7986_PIN(25, "SPI0_MISO"),
-	MT7986_PIN(26, "SPI0_CS"),
-	MT7986_PIN(27, "SPI0_HOLD"),
-	MT7986_PIN(28, "SPI0_WP"),
-	MT7986_PIN(29, "SPI1_CLK"),
-	MT7986_PIN(30, "SPI1_MOSI"),
-	MT7986_PIN(31, "SPI1_MISO"),
-	MT7986_PIN(32, "SPI1_CS"),
-	MT7986_PIN(33, "SPI2_CLK"),
-	MT7986_PIN(34, "SPI2_MOSI"),
-	MT7986_PIN(35, "SPI2_MISO"),
-	MT7986_PIN(36, "SPI2_CS"),
-	MT7986_PIN(37, "SPI2_HOLD"),
-	MT7986_PIN(38, "SPI2_WP"),
-	MT7986_PIN(39, "UART0_RXD"),
-	MT7986_PIN(40, "UART0_TXD"),
-	MT7986_PIN(41, "PCIE_PERESET_N"),
-	MT7986_PIN(42, "UART1_RXD"),
-	MT7986_PIN(43, "UART1_TXD"),
-	MT7986_PIN(44, "UART1_CTS"),
-	MT7986_PIN(45, "UART1_RTS"),
-	MT7986_PIN(46, "UART2_RXD"),
-	MT7986_PIN(47, "UART2_TXD"),
-	MT7986_PIN(48, "UART2_CTS"),
-	MT7986_PIN(49, "UART2_RTS"),
-	MT7986_PIN(50, "EMMC_DATA_0"),
-	MT7986_PIN(51, "EMMC_DATA_1"),
-	MT7986_PIN(52, "EMMC_DATA_2"),
-	MT7986_PIN(53, "EMMC_DATA_3"),
-	MT7986_PIN(54, "EMMC_DATA_4"),
-	MT7986_PIN(55, "EMMC_DATA_5"),
-	MT7986_PIN(56, "EMMC_DATA_6"),
-	MT7986_PIN(57, "EMMC_DATA_7"),
-	MT7986_PIN(58, "EMMC_CMD"),
-	MT7986_PIN(59, "EMMC_CK"),
-	MT7986_PIN(60, "EMMC_DSL"),
-	MT7986_PIN(61, "EMMC_RSTB"),
-	MT7986_PIN(62, "PCM_DTX"),
-	MT7986_PIN(63, "PCM_DRX"),
-	MT7986_PIN(64, "PCM_CLK"),
-	MT7986_PIN(65, "PCM_FS"),
-	MT7986_PIN(66, "MT7531_INT"),
-	MT7986_PIN(67, "SMI_MDC"),
-	MT7986_PIN(68, "SMI_MDIO"),
-	MT7986_PIN(69, "WF0_DIG_RESETB"),
-	MT7986_PIN(70, "WF0_CBA_RESETB"),
-	MT7986_PIN(71, "WF0_XO_REQ"),
-	MT7986_PIN(72, "WF0_TOP_CLK"),
-	MT7986_PIN(73, "WF0_TOP_DATA"),
-	MT7986_PIN(74, "WF0_HB1"),
-	MT7986_PIN(75, "WF0_HB2"),
-	MT7986_PIN(76, "WF0_HB3"),
-	MT7986_PIN(77, "WF0_HB4"),
-	MT7986_PIN(78, "WF0_HB0"),
-	MT7986_PIN(79, "WF0_HB0_B"),
-	MT7986_PIN(80, "WF0_HB5"),
-	MT7986_PIN(81, "WF0_HB6"),
-	MT7986_PIN(82, "WF0_HB7"),
-	MT7986_PIN(83, "WF0_HB8"),
-	MT7986_PIN(84, "WF0_HB9"),
-	MT7986_PIN(85, "WF0_HB10"),
-	MT7986_PIN(86, "WF1_DIG_RESETB"),
-	MT7986_PIN(87, "WF1_CBA_RESETB"),
-	MT7986_PIN(88, "WF1_XO_REQ"),
-	MT7986_PIN(89, "WF1_TOP_CLK"),
-	MT7986_PIN(90, "WF1_TOP_DATA"),
-	MT7986_PIN(91, "WF1_HB1"),
-	MT7986_PIN(92, "WF1_HB2"),
-	MT7986_PIN(93, "WF1_HB3"),
-	MT7986_PIN(94, "WF1_HB4"),
-	MT7986_PIN(95, "WF1_HB0"),
-	MT7986_PIN(96, "WF1_HB0_B"),
-	MT7986_PIN(97, "WF1_HB5"),
-	MT7986_PIN(98, "WF1_HB6"),
-	MT7986_PIN(99, "WF1_HB7"),
-	MT7986_PIN(100, "WF1_HB8"),
-};
-
-static const struct mtk_pin_desc mt7986b_pins[] = {
-	MT7986_PIN(0, "SYS_WATCHDOG"),
-	MT7986_PIN(1, "WF2G_LED"),
-	MT7986_PIN(2, "WF5G_LED"),
-	MT7986_PIN(3, "I2C_SCL"),
-	MT7986_PIN(4, "I2C_SDA"),
-	MT7986_PIN(5, "GPIO_0"),
-	MT7986_PIN(6, "GPIO_1"),
-	MT7986_PIN(7, "GPIO_2"),
-	MT7986_PIN(8, "GPIO_3"),
-	MT7986_PIN(9, "GPIO_4"),
-	MT7986_PIN(10, "GPIO_5"),
-	MT7986_PIN(11, "GPIO_6"),
-	MT7986_PIN(12, "GPIO_7"),
-	MT7986_PIN(13, "GPIO_8"),
-	MT7986_PIN(14, "GPIO_9"),
-	MT7986_PIN(15, "GPIO_10"),
-	MT7986_PIN(16, "GPIO_11"),
-	MT7986_PIN(17, "GPIO_12"),
-	MT7986_PIN(18, "GPIO_13"),
-	MT7986_PIN(19, "GPIO_14"),
-	MT7986_PIN(20, "GPIO_15"),
-	MT7986_PIN(21, "PWM0"),
-	MT7986_PIN(22, "PWM1"),
-	MT7986_PIN(23, "SPI0_CLK"),
-	MT7986_PIN(24, "SPI0_MOSI"),
-	MT7986_PIN(25, "SPI0_MISO"),
-	MT7986_PIN(26, "SPI0_CS"),
-	MT7986_PIN(27, "SPI0_HOLD"),
-	MT7986_PIN(28, "SPI0_WP"),
-	MT7986_PIN(29, "SPI1_CLK"),
-	MT7986_PIN(30, "SPI1_MOSI"),
-	MT7986_PIN(31, "SPI1_MISO"),
-	MT7986_PIN(32, "SPI1_CS"),
-	MT7986_PIN(33, "SPI2_CLK"),
-	MT7986_PIN(34, "SPI2_MOSI"),
-	MT7986_PIN(35, "SPI2_MISO"),
-	MT7986_PIN(36, "SPI2_CS"),
-	MT7986_PIN(37, "SPI2_HOLD"),
-	MT7986_PIN(38, "SPI2_WP"),
-	MT7986_PIN(39, "UART0_RXD"),
-	MT7986_PIN(40, "UART0_TXD"),
-	MT7986_NOT_BALLOUT_PIN(41),
-	MT7986_NOT_BALLOUT_PIN(42),
-	MT7986_NOT_BALLOUT_PIN(43),
-	MT7986_NOT_BALLOUT_PIN(44),
-	MT7986_NOT_BALLOUT_PIN(45),
-	MT7986_NOT_BALLOUT_PIN(46),
-	MT7986_NOT_BALLOUT_PIN(47),
-	MT7986_NOT_BALLOUT_PIN(48),
-	MT7986_NOT_BALLOUT_PIN(49),
-	MT7986_NOT_BALLOUT_PIN(50),
-	MT7986_NOT_BALLOUT_PIN(51),
-	MT7986_NOT_BALLOUT_PIN(52),
-	MT7986_NOT_BALLOUT_PIN(53),
-	MT7986_NOT_BALLOUT_PIN(54),
-	MT7986_NOT_BALLOUT_PIN(55),
-	MT7986_NOT_BALLOUT_PIN(56),
-	MT7986_NOT_BALLOUT_PIN(57),
-	MT7986_NOT_BALLOUT_PIN(58),
-	MT7986_NOT_BALLOUT_PIN(59),
-	MT7986_NOT_BALLOUT_PIN(60),
-	MT7986_NOT_BALLOUT_PIN(61),
-	MT7986_NOT_BALLOUT_PIN(62),
-	MT7986_NOT_BALLOUT_PIN(63),
-	MT7986_NOT_BALLOUT_PIN(64),
-	MT7986_NOT_BALLOUT_PIN(65),
-	MT7986_PIN(66, "MT7531_INT"),
-	MT7986_PIN(67, "SMI_MDC"),
-	MT7986_PIN(68, "SMI_MDIO"),
-	MT7986_PIN(69, "WF0_DIG_RESETB"),
-	MT7986_PIN(70, "WF0_CBA_RESETB"),
-	MT7986_PIN(71, "WF0_XO_REQ"),
-	MT7986_PIN(72, "WF0_TOP_CLK"),
-	MT7986_PIN(73, "WF0_TOP_DATA"),
-	MT7986_PIN(74, "WF0_HB1"),
-	MT7986_PIN(75, "WF0_HB2"),
-	MT7986_PIN(76, "WF0_HB3"),
-	MT7986_PIN(77, "WF0_HB4"),
-	MT7986_PIN(78, "WF0_HB0"),
-	MT7986_PIN(79, "WF0_HB0_B"),
-	MT7986_PIN(80, "WF0_HB5"),
-	MT7986_PIN(81, "WF0_HB6"),
-	MT7986_PIN(82, "WF0_HB7"),
-	MT7986_PIN(83, "WF0_HB8"),
-	MT7986_PIN(84, "WF0_HB9"),
-	MT7986_PIN(85, "WF0_HB10"),
-	MT7986_PIN(86, "WF1_DIG_RESETB"),
-	MT7986_PIN(87, "WF1_CBA_RESETB"),
-	MT7986_PIN(88, "WF1_XO_REQ"),
-	MT7986_PIN(89, "WF1_TOP_CLK"),
-	MT7986_PIN(90, "WF1_TOP_DATA"),
-	MT7986_PIN(91, "WF1_HB1"),
-	MT7986_PIN(92, "WF1_HB2"),
-	MT7986_PIN(93, "WF1_HB3"),
-	MT7986_PIN(94, "WF1_HB4"),
-	MT7986_PIN(95, "WF1_HB0"),
-	MT7986_PIN(96, "WF1_HB0_B"),
-	MT7986_PIN(97, "WF1_HB5"),
-	MT7986_PIN(98, "WF1_HB6"),
-	MT7986_PIN(99, "WF1_HB7"),
-	MT7986_PIN(100, "WF1_HB8"),
-};
-
-/* List all groups consisting of these pins dedicated to the enablement of
- * certain hardware block and the corresponding mode for all of the pins.
- * The hardware probably has multiple combinations of these pinouts.
- */
-
-static int mt7986_watchdog_pins[] = { 0, };
-static int mt7986_watchdog_funcs[] = { 1, };
-
-static int mt7986_wifi_led_pins[] = { 1, 2, };
-static int mt7986_wifi_led_funcs[] = { 1, 1, };
-
-static int mt7986_i2c_pins[] = { 3, 4, };
-static int mt7986_i2c_funcs[] = { 1, 1, };
-
-static int mt7986_uart1_0_pins[] = { 7, 8, 9, 10, };
-static int mt7986_uart1_0_funcs[] = { 3, 3, 3, 3, };
-
-static int mt7986_spi1_0_pins[] = { 11, 12, 13, 14, };
-static int mt7986_spi1_0_funcs[] = { 3, 3, 3, 3, };
-
-static int mt7986_pwm1_1_pins[] = { 20, };
-static int mt7986_pwm1_1_funcs[] = { 2, };
-
-static int mt7986_pwm0_pins[] = { 21, };
-static int mt7986_pwm0_funcs[] = { 1, };
-
-static int mt7986_pwm1_0_pins[] = { 22, };
-static int mt7986_pwm1_0_funcs[] = { 1, };
-
-static int mt7986_emmc_45_pins[] = {
-	22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, };
-static int mt7986_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
-
-static int mt7986_snfi_pins[] = { 23, 24, 25, 26, 27, 28, };
-static int mt7986_snfi_funcs[] = { 1, 1, 1, 1, 1, 1, };
-
-static int mt7986_spi1_1_pins[] = { 23, 24, 25, 26, };
-static int mt7986_spi1_1_funcs[] = { 3, 3, 3, 3, };
-
-static int mt7986_uart1_1_pins[] = { 23, 24, 25, 26, };
-static int mt7986_uart1_1_funcs[] = { 4, 4, 4, 4, };
-
-static int mt7986_spi1_2_pins[] = { 29, 30, 31, 32, };
-static int mt7986_spi1_2_funcs[] = { 1, 1, 1, 1, };
-
-static int mt7986_uart1_2_rx_tx_pins[] = { 29, 30, };
-static int mt7986_uart1_2_rx_tx_funcs[] = { 3, 3, };
-
-static int mt7986_uart1_2_cts_rts_pins[] = { 31, 32, };
-static int mt7986_uart1_2_cts_rts_funcs[] = { 3, 3, };
-
-static int mt7986_uart2_0_rx_tx_pins[] = { 29, 30, };
-static int mt7986_uart2_0_rx_tx_funcs[] = { 4, 4, };
-
-static int mt7986_uart2_0_cts_rts_pins[] = { 31, 32, };
-static int mt7986_uart2_0_cts_rts_funcs[] = { 4, 4, };
-
-static int mt7986_spi0_pins[] = { 33, 34, 35, 36, };
-static int mt7986_spi0_funcs[] = { 1, 1, 1, 1, };
-
-static int mt7986_spi0_wp_hold_pins[] = { 37, 38, };
-static int mt7986_spi0_wp_hold_funcs[] = { 1, 1, };
-
-static int mt7986_uart2_1_pins[] = { 33, 34, 35, 36, };
-static int mt7986_uart2_1_funcs[] = { 3, 3, 3, 3, };
-
-static int mt7986_uart1_3_rx_tx_pins[] = { 35, 36, };
-static int mt7986_uart1_3_rx_tx_funcs[] = { 2, 2, };
-
-static int mt7986_uart1_3_cts_rts_pins[] = { 37, 38, };
-static int mt7986_uart1_3_cts_rts_funcs[] = { 2, 2, };
-
-static int mt7986_spi1_3_pins[] = { 33, 34, 35, 36, };
-static int mt7986_spi1_3_funcs[] = { 4, 4, 4, 4, };
-
-static int mt7986_uart0_pins[] = { 39, 40, };
-static int mt7986_uart0_funcs[] = { 1, 1, };
-
-static int mt7986_pcie_reset_pins[] = { 41, };
-static int mt7986_pcie_reset_funcs[] = { 1, };
-
-static int mt7986_uart1_pins[] = { 42, 43, 44, 45, };
-static int mt7986_uart1_funcs[] = { 1, 1, 1, 1, };
-
-static int mt7986_uart1_rx_tx_pins[] = { 42, 43, };
-static int mt7986_uart1_rx_tx_funcs[] = { 1, 1, };
-
-static int mt7986_uart1_cts_rts_pins[] = { 44, 45, };
-static int mt7986_uart1_cts_rts_funcs[] = { 1, 1, };
-
-static int mt7986_uart2_pins[] = { 46, 47, 48, 49, };
-static int mt7986_uart2_funcs[] = { 1, 1, 1, 1, };
-
-static int mt7986_emmc_51_pins[] = {
-	50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, };
-static int mt7986_emmc_51_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
-
-static int mt7986_pcm_pins[] = { 62, 63, 64, 65, };
-static int mt7986_pcm_funcs[] = { 1, 1, 1, 1, };
-
-static int mt7986_i2s_pins[] = { 62, 63, 64, 65, };
-static int mt7986_i2s_funcs[] = { 1, 1, 1, 1, };
-
-static int mt7986_switch_int_pins[] = { 66, };
-static int mt7986_switch_int_funcs[] = { 1, };
-
-static int mt7986_mdc_mdio_pins[] = { 67, 68, };
-static int mt7986_mdc_mdio_funcs[] = { 1, 1, };
-
-static int mt7986_wf_2g_pins[] = {74, 75, 76, 77, 78, 79, 80, 81, 82, 83, };
-static int mt7986_wf_2g_funcs[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
-
-static int mt7986_wf_5g_pins[] = {91, 92, 93, 94, 95, 96, 97, 98, 99, 100, };
-static int mt7986_wf_5g_funcs[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
-
-static int mt7986_wf_dbdc_pins[] = {
-	74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, };
-static int mt7986_wf_dbdc_funcs[] = {
-	2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
-
-static int mt7986_pcie_clk_pins[] = { 9, };
-static int mt7986_pcie_clk_funcs[] = { 1, };
-
-static int mt7986_pcie_wake_pins[] = { 10, };
-static int mt7986_pcie_wake_funcs[] = { 1, };
-
-static const struct group_desc mt7986_groups[] = {
-	PINCTRL_PIN_GROUP("watchdog", mt7986_watchdog),
-	PINCTRL_PIN_GROUP("wifi_led", mt7986_wifi_led),
-	PINCTRL_PIN_GROUP("i2c", mt7986_i2c),
-	PINCTRL_PIN_GROUP("uart1_0", mt7986_uart1_0),
-	PINCTRL_PIN_GROUP("uart1_rx_tx", mt7986_uart1_rx_tx),
-	PINCTRL_PIN_GROUP("uart1_cts_rts", mt7986_uart1_cts_rts),
-	PINCTRL_PIN_GROUP("pcie_clk", mt7986_pcie_clk),
-	PINCTRL_PIN_GROUP("pcie_wake", mt7986_pcie_wake),
-	PINCTRL_PIN_GROUP("spi1_0", mt7986_spi1_0),
-	PINCTRL_PIN_GROUP("pwm1_1", mt7986_pwm1_1),
-	PINCTRL_PIN_GROUP("pwm0", mt7986_pwm0),
-	PINCTRL_PIN_GROUP("pwm1_0", mt7986_pwm1_0),
-	PINCTRL_PIN_GROUP("emmc_45", mt7986_emmc_45),
-	PINCTRL_PIN_GROUP("snfi", mt7986_snfi),
-	PINCTRL_PIN_GROUP("spi1_1", mt7986_spi1_1),
-	PINCTRL_PIN_GROUP("uart1_1", mt7986_uart1_1),
-	PINCTRL_PIN_GROUP("spi1_2", mt7986_spi1_2),
-	PINCTRL_PIN_GROUP("uart1_2_rx_tx", mt7986_uart1_2_rx_tx),
-	PINCTRL_PIN_GROUP("uart1_2_cts_rts", mt7986_uart1_2_cts_rts),
-	PINCTRL_PIN_GROUP("uart2_0_rx_tx", mt7986_uart2_0_rx_tx),
-	PINCTRL_PIN_GROUP("uart2_0_cts_rts", mt7986_uart2_0_cts_rts),
-	PINCTRL_PIN_GROUP("spi0", mt7986_spi0),
-	PINCTRL_PIN_GROUP("spi0_wp_hold", mt7986_spi0_wp_hold),
-	PINCTRL_PIN_GROUP("uart2_1", mt7986_uart2_1),
-	PINCTRL_PIN_GROUP("uart1_3_rx_tx", mt7986_uart1_3_rx_tx),
-	PINCTRL_PIN_GROUP("uart1_3_cts_rts", mt7986_uart1_3_cts_rts),
-	PINCTRL_PIN_GROUP("spi1_3", mt7986_spi1_3),
-	PINCTRL_PIN_GROUP("uart0", mt7986_uart0),
-	PINCTRL_PIN_GROUP("switch_int", mt7986_switch_int),
-	PINCTRL_PIN_GROUP("mdc_mdio", mt7986_mdc_mdio),
-	PINCTRL_PIN_GROUP("pcie_pereset", mt7986_pcie_reset),
-	PINCTRL_PIN_GROUP("uart1", mt7986_uart1),
-	PINCTRL_PIN_GROUP("uart2", mt7986_uart2),
-	PINCTRL_PIN_GROUP("emmc_51", mt7986_emmc_51),
-	PINCTRL_PIN_GROUP("pcm", mt7986_pcm),
-	PINCTRL_PIN_GROUP("i2s", mt7986_i2s),
-	PINCTRL_PIN_GROUP("wf_2g", mt7986_wf_2g),
-	PINCTRL_PIN_GROUP("wf_5g", mt7986_wf_5g),
-	PINCTRL_PIN_GROUP("wf_dbdc", mt7986_wf_dbdc),
-};
-
-/* Joint those groups owning the same capability in user point of view which
- * allows that people tend to use through the device tree.
- */
-
-static const char *mt7986_audio_groups[] = { "pcm", "i2s" };
-static const char *mt7986_emmc_groups[] = {
-	"emmc_45", "emmc_51", };
-static const char *mt7986_ethernet_groups[] = {
-	"switch_int", "mdc_mdio", };
-static const char *mt7986_i2c_groups[] = { "i2c", };
-static const char *mt7986_led_groups[] = { "wifi_led", };
-static const char *mt7986_flash_groups[] = { "snfi", };
-static const char *mt7986_pcie_groups[] = {
-	"pcie_clk", "pcie_wake", "pcie_pereset" };
-static const char *mt7986_pwm_groups[] = { "pwm0", "pwm1_0", "pwm1_1", };
-static const char *mt7986_spi_groups[] = {
-	"spi0", "spi0_wp_hold", "spi1_0", "spi1_1", "spi1_2", "spi1_3", };
-static const char *mt7986_uart_groups[] = {
-	"uart1_0", "uart1_1", "uart1_rx_tx", "uart1_cts_rts",
-	"uart1_2_rx_tx", "uart1_2_cts_rts",
-	"uart1_3_rx_tx", "uart1_3_cts_rts", "uart2_0_rx_tx", "uart2_0_cts_rts",
-	"uart2_0", "uart2_1", "uart0", "uart1", "uart2",
-};
-static const char *mt7986_wdt_groups[] = { "watchdog", };
-static const char *mt7986_wf_groups[] = { "wf_2g", "wf_5g", "wf_dbdc", };
-
-static const struct function_desc mt7986_functions[] = {
-	{"audio", mt7986_audio_groups, ARRAY_SIZE(mt7986_audio_groups)},
-	{"emmc", mt7986_emmc_groups, ARRAY_SIZE(mt7986_emmc_groups)},
-	{"eth", mt7986_ethernet_groups, ARRAY_SIZE(mt7986_ethernet_groups)},
-	{"i2c", mt7986_i2c_groups, ARRAY_SIZE(mt7986_i2c_groups)},
-	{"led", mt7986_led_groups, ARRAY_SIZE(mt7986_led_groups)},
-	{"flash", mt7986_flash_groups, ARRAY_SIZE(mt7986_flash_groups)},
-	{"pcie", mt7986_pcie_groups, ARRAY_SIZE(mt7986_pcie_groups)},
-	{"pwm", mt7986_pwm_groups, ARRAY_SIZE(mt7986_pwm_groups)},
-	{"spi", mt7986_spi_groups, ARRAY_SIZE(mt7986_spi_groups)},
-	{"uart", mt7986_uart_groups, ARRAY_SIZE(mt7986_uart_groups)},
-	{"watchdog", mt7986_wdt_groups, ARRAY_SIZE(mt7986_wdt_groups)},
-	{"wifi", mt7986_wf_groups, ARRAY_SIZE(mt7986_wf_groups)},
-};
-
-static const struct mtk_eint_hw mt7986a_eint_hw = {
-	.port_mask = 7,
-	.ports = 7,
-	.ap_num = ARRAY_SIZE(mt7986a_pins),
-	.db_cnt = 16,
-	.db_time = debounce_time_mt6765,
-};
-
-static const struct mtk_eint_hw mt7986b_eint_hw = {
-	.port_mask = 7,
-	.ports = 7,
-	.ap_num = ARRAY_SIZE(mt7986b_pins),
-	.db_cnt = 16,
-	.db_time = debounce_time_mt6765,
-};
-
-static struct mtk_pin_soc mt7986a_data = {
-	.reg_cal = mt7986_reg_cals,
-	.pins = mt7986a_pins,
-	.npins = ARRAY_SIZE(mt7986a_pins),
-	.grps = mt7986_groups,
-	.ngrps = ARRAY_SIZE(mt7986_groups),
-	.funcs = mt7986_functions,
-	.nfuncs = ARRAY_SIZE(mt7986_functions),
-	.eint_hw = &mt7986a_eint_hw,
-	.gpio_m = 0,
-	.ies_present = false,
-	.base_names = mt7986_pinctrl_register_base_names,
-	.nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names),
-	.bias_disable_set = mtk_pinconf_bias_disable_set,
-	.bias_disable_get = mtk_pinconf_bias_disable_get,
-	.bias_set = mtk_pinconf_bias_set,
-	.bias_get = mtk_pinconf_bias_get,
-	.pull_type = mt7986_pull_type,
-	.bias_set_combo = mtk_pinconf_bias_set_combo,
-	.bias_get_combo = mtk_pinconf_bias_get_combo,
-	.drive_set = mtk_pinconf_drive_set_rev1,
-	.drive_get = mtk_pinconf_drive_get_rev1,
-	.adv_pull_get = mtk_pinconf_adv_pull_get,
-	.adv_pull_set = mtk_pinconf_adv_pull_set,
-};
-
-static struct mtk_pin_soc mt7986b_data = {
-	.reg_cal = mt7986_reg_cals,
-	.pins = mt7986b_pins,
-	.npins = ARRAY_SIZE(mt7986b_pins),
-	.grps = mt7986_groups,
-	.ngrps = ARRAY_SIZE(mt7986_groups),
-	.funcs = mt7986_functions,
-	.nfuncs = ARRAY_SIZE(mt7986_functions),
-	.eint_hw = &mt7986b_eint_hw,
-	.gpio_m = 0,
-	.ies_present = false,
-	.base_names = mt7986_pinctrl_register_base_names,
-	.nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names),
-	.bias_disable_set = mtk_pinconf_bias_disable_set,
-	.bias_disable_get = mtk_pinconf_bias_disable_get,
-	.bias_set = mtk_pinconf_bias_set,
-	.bias_get = mtk_pinconf_bias_get,
-	.pull_type = mt7986_pull_type,
-	.bias_set_combo = mtk_pinconf_bias_set_combo,
-	.bias_get_combo = mtk_pinconf_bias_get_combo,
-	.drive_set = mtk_pinconf_drive_set_rev1,
-	.drive_get = mtk_pinconf_drive_get_rev1,
-	.adv_pull_get = mtk_pinconf_adv_pull_get,
-	.adv_pull_set = mtk_pinconf_adv_pull_set,
-};
-
-static const struct of_device_id mt7986a_pinctrl_of_match[] = {
-	{.compatible = "mediatek,mt7986a-pinctrl",},
-	{}
-};
-
-static const struct of_device_id mt7986b_pinctrl_of_match[] = {
-	{.compatible = "mediatek,mt7986b-pinctrl",},
-	{}
-};
-
-static int mt7986a_pinctrl_probe(struct platform_device *pdev)
-{
-	return mtk_moore_pinctrl_probe(pdev, &mt7986a_data);
-}
-
-static int mt7986b_pinctrl_probe(struct platform_device *pdev)
-{
-	return mtk_moore_pinctrl_probe(pdev, &mt7986b_data);
-}
-
-static struct platform_driver mt7986a_pinctrl_driver = {
-	.driver = {
-		.name = "mt7986a-pinctrl",
-		.of_match_table = mt7986a_pinctrl_of_match,
-	},
-	.probe = mt7986a_pinctrl_probe,
-};
-
-static struct platform_driver mt7986b_pinctrl_driver = {
-	.driver = {
-		.name = "mt7986b-pinctrl",
-		.of_match_table = mt7986b_pinctrl_of_match,
-	},
-	.probe = mt7986b_pinctrl_probe,
-};
-
-static int __init mt7986a_pinctrl_init(void)
-{
-	return platform_driver_register(&mt7986a_pinctrl_driver);
-}
-
-static int __init mt7986b_pinctrl_init(void)
-{
-	return platform_driver_register(&mt7986b_pinctrl_driver);
-}
-
-arch_initcall(mt7986a_pinctrl_init);
-arch_initcall(mt7986b_pinctrl_init);
diff --git a/target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7988.c b/target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7988.c
deleted file mode 100644
index 659c83e997df61..00000000000000
--- a/target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7988.c
+++ /dev/null
@@ -1,1466 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * The MT7988 driver based on Linux generic pinctrl binding.
- *
- * Copyright (C) 2020 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- */
-
-#include "pinctrl-moore.h"
-
-enum MT7988_PINCTRL_REG_PAGE {
-	GPIO_BASE,
-	IOCFG_TR_BASE,
-	IOCFG_BR_BASE,
-	IOCFG_RB_BASE,
-	IOCFG_LB_BASE,
-	IOCFG_TL_BASE,
-};
-
-#define MT7988_PIN(_number, _name) MTK_PIN(_number, _name, 0, _number, DRV_GRP4)
-
-#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,     \
-		       _x_bits)                                                \
-	PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,     \
-		       _x_bits, 32, 0)
-
-#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,    \
-			_x_bits)                                               \
-	PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,     \
-		       _x_bits, 32, 1)
-
-static const struct mtk_pin_field_calc mt7988_pin_mode_range[] = {
-	PIN_FIELD(0, 83, 0x300, 0x10, 0, 4),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_dir_range[] = {
-	PIN_FIELD(0, 83, 0x0, 0x10, 0, 1),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_di_range[] = {
-	PIN_FIELD(0, 83, 0x200, 0x10, 0, 1),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_do_range[] = {
-	PIN_FIELD(0, 83, 0x100, 0x10, 0, 1),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_ies_range[] = {
-	PIN_FIELD_BASE(0, 0, 5, 0x30, 0x10, 13, 1),
-	PIN_FIELD_BASE(1, 1, 5, 0x30, 0x10, 14, 1),
-	PIN_FIELD_BASE(2, 2, 5, 0x30, 0x10, 11, 1),
-	PIN_FIELD_BASE(3, 3, 5, 0x30, 0x10, 12, 1),
-	PIN_FIELD_BASE(4, 4, 5, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(5, 5, 5, 0x30, 0x10, 9, 1),
-	PIN_FIELD_BASE(6, 6, 5, 0x30, 0x10, 10, 1),
-
-	PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 8, 1),
-	PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 6, 1),
-	PIN_FIELD_BASE(9, 9, 4, 0x30, 0x10, 5, 1),
-	PIN_FIELD_BASE(10, 10, 4, 0x30, 0x10, 3, 1),
-
-	PIN_FIELD_BASE(11, 11, 1, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(12, 12, 1, 0x40, 0x10, 21, 1),
-	PIN_FIELD_BASE(13, 13, 1, 0x40, 0x10, 1, 1),
-	PIN_FIELD_BASE(14, 14, 1, 0x40, 0x10, 2, 1),
-
-	PIN_FIELD_BASE(15, 15, 5, 0x30, 0x10, 7, 1),
-	PIN_FIELD_BASE(16, 16, 5, 0x30, 0x10, 8, 1),
-	PIN_FIELD_BASE(17, 17, 5, 0x30, 0x10, 3, 1),
-	PIN_FIELD_BASE(18, 18, 5, 0x30, 0x10, 4, 1),
-
-	PIN_FIELD_BASE(19, 19, 4, 0x30, 0x10, 7, 1),
-	PIN_FIELD_BASE(20, 20, 4, 0x30, 0x10, 4, 1),
-
-	PIN_FIELD_BASE(21, 21, 3, 0x50, 0x10, 17, 1),
-	PIN_FIELD_BASE(22, 22, 3, 0x50, 0x10, 23, 1),
-	PIN_FIELD_BASE(23, 23, 3, 0x50, 0x10, 20, 1),
-	PIN_FIELD_BASE(24, 24, 3, 0x50, 0x10, 19, 1),
-	PIN_FIELD_BASE(25, 25, 3, 0x50, 0x10, 21, 1),
-	PIN_FIELD_BASE(26, 26, 3, 0x50, 0x10, 22, 1),
-	PIN_FIELD_BASE(27, 27, 3, 0x50, 0x10, 18, 1),
-	PIN_FIELD_BASE(28, 28, 3, 0x50, 0x10, 25, 1),
-	PIN_FIELD_BASE(29, 29, 3, 0x50, 0x10, 26, 1),
-	PIN_FIELD_BASE(30, 30, 3, 0x50, 0x10, 27, 1),
-	PIN_FIELD_BASE(31, 31, 3, 0x50, 0x10, 24, 1),
-	PIN_FIELD_BASE(32, 32, 3, 0x50, 0x10, 28, 1),
-	PIN_FIELD_BASE(33, 33, 3, 0x60, 0x10, 0, 1),
-	PIN_FIELD_BASE(34, 34, 3, 0x50, 0x10, 31, 1),
-	PIN_FIELD_BASE(35, 35, 3, 0x50, 0x10, 29, 1),
-	PIN_FIELD_BASE(36, 36, 3, 0x50, 0x10, 30, 1),
-	PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 1, 1),
-	PIN_FIELD_BASE(38, 38, 3, 0x50, 0x10, 11, 1),
-	PIN_FIELD_BASE(39, 39, 3, 0x50, 0x10, 10, 1),
-	PIN_FIELD_BASE(40, 40, 3, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(41, 41, 3, 0x50, 0x10, 1, 1),
-	PIN_FIELD_BASE(42, 42, 3, 0x50, 0x10, 9, 1),
-	PIN_FIELD_BASE(43, 43, 3, 0x50, 0x10, 8, 1),
-	PIN_FIELD_BASE(44, 44, 3, 0x50, 0x10, 7, 1),
-	PIN_FIELD_BASE(45, 45, 3, 0x50, 0x10, 6, 1),
-	PIN_FIELD_BASE(46, 46, 3, 0x50, 0x10, 5, 1),
-	PIN_FIELD_BASE(47, 47, 3, 0x50, 0x10, 4, 1),
-	PIN_FIELD_BASE(48, 48, 3, 0x50, 0x10, 3, 1),
-	PIN_FIELD_BASE(49, 49, 3, 0x50, 0x10, 2, 1),
-	PIN_FIELD_BASE(50, 50, 3, 0x50, 0x10, 15, 1),
-	PIN_FIELD_BASE(51, 51, 3, 0x50, 0x10, 12, 1),
-	PIN_FIELD_BASE(52, 52, 3, 0x50, 0x10, 13, 1),
-	PIN_FIELD_BASE(53, 53, 3, 0x50, 0x10, 14, 1),
-	PIN_FIELD_BASE(54, 54, 3, 0x50, 0x10, 16, 1),
-
-	PIN_FIELD_BASE(55, 55, 1, 0x40, 0x10, 14, 1),
-	PIN_FIELD_BASE(56, 56, 1, 0x40, 0x10, 15, 1),
-	PIN_FIELD_BASE(57, 57, 1, 0x40, 0x10, 13, 1),
-	PIN_FIELD_BASE(58, 58, 1, 0x40, 0x10, 4, 1),
-	PIN_FIELD_BASE(59, 59, 1, 0x40, 0x10, 5, 1),
-	PIN_FIELD_BASE(60, 60, 1, 0x40, 0x10, 6, 1),
-	PIN_FIELD_BASE(61, 61, 1, 0x40, 0x10, 3, 1),
-	PIN_FIELD_BASE(62, 62, 1, 0x40, 0x10, 7, 1),
-	PIN_FIELD_BASE(63, 63, 1, 0x40, 0x10, 20, 1),
-	PIN_FIELD_BASE(64, 64, 1, 0x40, 0x10, 8, 1),
-	PIN_FIELD_BASE(65, 65, 1, 0x40, 0x10, 9, 1),
-	PIN_FIELD_BASE(66, 66, 1, 0x40, 0x10, 10, 1),
-	PIN_FIELD_BASE(67, 67, 1, 0x40, 0x10, 11, 1),
-	PIN_FIELD_BASE(68, 68, 1, 0x40, 0x10, 12, 1),
-
-	PIN_FIELD_BASE(69, 69, 5, 0x30, 0x10, 1, 1),
-	PIN_FIELD_BASE(70, 70, 5, 0x30, 0x10, 2, 1),
-	PIN_FIELD_BASE(71, 71, 5, 0x30, 0x10, 5, 1),
-	PIN_FIELD_BASE(72, 72, 5, 0x30, 0x10, 6, 1),
-
-	PIN_FIELD_BASE(73, 73, 4, 0x30, 0x10, 10, 1),
-	PIN_FIELD_BASE(74, 74, 4, 0x30, 0x10, 1, 1),
-	PIN_FIELD_BASE(75, 75, 4, 0x30, 0x10, 11, 1),
-	PIN_FIELD_BASE(76, 76, 4, 0x30, 0x10, 9, 1),
-	PIN_FIELD_BASE(77, 77, 4, 0x30, 0x10, 2, 1),
-	PIN_FIELD_BASE(78, 78, 4, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(79, 79, 4, 0x30, 0x10, 12, 1),
-
-	PIN_FIELD_BASE(80, 80, 1, 0x40, 0x10, 18, 1),
-	PIN_FIELD_BASE(81, 81, 1, 0x40, 0x10, 19, 1),
-	PIN_FIELD_BASE(82, 82, 1, 0x40, 0x10, 16, 1),
-	PIN_FIELD_BASE(83, 83, 1, 0x40, 0x10, 17, 1),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_smt_range[] = {
-	PIN_FIELD_BASE(0, 0, 5, 0xc0, 0x10, 13, 1),
-	PIN_FIELD_BASE(1, 1, 5, 0xc0, 0x10, 14, 1),
-	PIN_FIELD_BASE(2, 2, 5, 0xc0, 0x10, 11, 1),
-	PIN_FIELD_BASE(3, 3, 5, 0xc0, 0x10, 12, 1),
-	PIN_FIELD_BASE(4, 4, 5, 0xc0, 0x10, 0, 1),
-	PIN_FIELD_BASE(5, 5, 5, 0xc0, 0x10, 9, 1),
-	PIN_FIELD_BASE(6, 6, 5, 0xc0, 0x10, 10, 1),
-
-	PIN_FIELD_BASE(7, 7, 4, 0xb0, 0x10, 8, 1),
-	PIN_FIELD_BASE(8, 8, 4, 0xb0, 0x10, 6, 1),
-	PIN_FIELD_BASE(9, 9, 4, 0xb0, 0x10, 5, 1),
-	PIN_FIELD_BASE(10, 10, 4, 0xb0, 0x10, 3, 1),
-
-	PIN_FIELD_BASE(11, 11, 1, 0xe0, 0x10, 0, 1),
-	PIN_FIELD_BASE(12, 12, 1, 0xe0, 0x10, 21, 1),
-	PIN_FIELD_BASE(13, 13, 1, 0xe0, 0x10, 1, 1),
-	PIN_FIELD_BASE(14, 14, 1, 0xe0, 0x10, 2, 1),
-
-	PIN_FIELD_BASE(15, 15, 5, 0xc0, 0x10, 7, 1),
-	PIN_FIELD_BASE(16, 16, 5, 0xc0, 0x10, 8, 1),
-	PIN_FIELD_BASE(17, 17, 5, 0xc0, 0x10, 3, 1),
-	PIN_FIELD_BASE(18, 18, 5, 0xc0, 0x10, 4, 1),
-
-	PIN_FIELD_BASE(19, 19, 4, 0xb0, 0x10, 7, 1),
-	PIN_FIELD_BASE(20, 20, 4, 0xb0, 0x10, 4, 1),
-
-	PIN_FIELD_BASE(21, 21, 3, 0x140, 0x10, 17, 1),
-	PIN_FIELD_BASE(22, 22, 3, 0x140, 0x10, 23, 1),
-	PIN_FIELD_BASE(23, 23, 3, 0x140, 0x10, 20, 1),
-	PIN_FIELD_BASE(24, 24, 3, 0x140, 0x10, 19, 1),
-	PIN_FIELD_BASE(25, 25, 3, 0x140, 0x10, 21, 1),
-	PIN_FIELD_BASE(26, 26, 3, 0x140, 0x10, 22, 1),
-	PIN_FIELD_BASE(27, 27, 3, 0x140, 0x10, 18, 1),
-	PIN_FIELD_BASE(28, 28, 3, 0x140, 0x10, 25, 1),
-	PIN_FIELD_BASE(29, 29, 3, 0x140, 0x10, 26, 1),
-	PIN_FIELD_BASE(30, 30, 3, 0x140, 0x10, 27, 1),
-	PIN_FIELD_BASE(31, 31, 3, 0x140, 0x10, 24, 1),
-	PIN_FIELD_BASE(32, 32, 3, 0x140, 0x10, 28, 1),
-	PIN_FIELD_BASE(33, 33, 3, 0x150, 0x10, 0, 1),
-	PIN_FIELD_BASE(34, 34, 3, 0x140, 0x10, 31, 1),
-	PIN_FIELD_BASE(35, 35, 3, 0x140, 0x10, 29, 1),
-	PIN_FIELD_BASE(36, 36, 3, 0x140, 0x10, 30, 1),
-	PIN_FIELD_BASE(37, 37, 3, 0x150, 0x10, 1, 1),
-	PIN_FIELD_BASE(38, 38, 3, 0x140, 0x10, 11, 1),
-	PIN_FIELD_BASE(39, 39, 3, 0x140, 0x10, 10, 1),
-	PIN_FIELD_BASE(40, 40, 3, 0x140, 0x10, 0, 1),
-	PIN_FIELD_BASE(41, 41, 3, 0x140, 0x10, 1, 1),
-	PIN_FIELD_BASE(42, 42, 3, 0x140, 0x10, 9, 1),
-	PIN_FIELD_BASE(43, 43, 3, 0x140, 0x10, 8, 1),
-	PIN_FIELD_BASE(44, 44, 3, 0x140, 0x10, 7, 1),
-	PIN_FIELD_BASE(45, 45, 3, 0x140, 0x10, 6, 1),
-	PIN_FIELD_BASE(46, 46, 3, 0x140, 0x10, 5, 1),
-	PIN_FIELD_BASE(47, 47, 3, 0x140, 0x10, 4, 1),
-	PIN_FIELD_BASE(48, 48, 3, 0x140, 0x10, 3, 1),
-	PIN_FIELD_BASE(49, 49, 3, 0x140, 0x10, 2, 1),
-	PIN_FIELD_BASE(50, 50, 3, 0x140, 0x10, 15, 1),
-	PIN_FIELD_BASE(51, 51, 3, 0x140, 0x10, 12, 1),
-	PIN_FIELD_BASE(52, 52, 3, 0x140, 0x10, 13, 1),
-	PIN_FIELD_BASE(53, 53, 3, 0x140, 0x10, 14, 1),
-	PIN_FIELD_BASE(54, 54, 3, 0x140, 0x10, 16, 1),
-
-	PIN_FIELD_BASE(55, 55, 1, 0xe0, 0x10, 14, 1),
-	PIN_FIELD_BASE(56, 56, 1, 0xe0, 0x10, 15, 1),
-	PIN_FIELD_BASE(57, 57, 1, 0xe0, 0x10, 13, 1),
-	PIN_FIELD_BASE(58, 58, 1, 0xe0, 0x10, 4, 1),
-	PIN_FIELD_BASE(59, 59, 1, 0xe0, 0x10, 5, 1),
-	PIN_FIELD_BASE(60, 60, 1, 0xe0, 0x10, 6, 1),
-	PIN_FIELD_BASE(61, 61, 1, 0xe0, 0x10, 3, 1),
-	PIN_FIELD_BASE(62, 62, 1, 0xe0, 0x10, 7, 1),
-	PIN_FIELD_BASE(63, 63, 1, 0xe0, 0x10, 20, 1),
-	PIN_FIELD_BASE(64, 64, 1, 0xe0, 0x10, 8, 1),
-	PIN_FIELD_BASE(65, 65, 1, 0xe0, 0x10, 9, 1),
-	PIN_FIELD_BASE(66, 66, 1, 0xe0, 0x10, 10, 1),
-	PIN_FIELD_BASE(67, 67, 1, 0xe0, 0x10, 11, 1),
-	PIN_FIELD_BASE(68, 68, 1, 0xe0, 0x10, 12, 1),
-
-	PIN_FIELD_BASE(69, 69, 5, 0xc0, 0x10, 1, 1),
-	PIN_FIELD_BASE(70, 70, 5, 0xc0, 0x10, 2, 1),
-	PIN_FIELD_BASE(71, 71, 5, 0xc0, 0x10, 5, 1),
-	PIN_FIELD_BASE(72, 72, 5, 0xc0, 0x10, 6, 1),
-
-	PIN_FIELD_BASE(73, 73, 4, 0xb0, 0x10, 10, 1),
-	PIN_FIELD_BASE(74, 74, 4, 0xb0, 0x10, 1, 1),
-	PIN_FIELD_BASE(75, 75, 4, 0xb0, 0x10, 11, 1),
-	PIN_FIELD_BASE(76, 76, 4, 0xb0, 0x10, 9, 1),
-	PIN_FIELD_BASE(77, 77, 4, 0xb0, 0x10, 2, 1),
-	PIN_FIELD_BASE(78, 78, 4, 0xb0, 0x10, 0, 1),
-	PIN_FIELD_BASE(79, 79, 4, 0xb0, 0x10, 12, 1),
-
-	PIN_FIELD_BASE(80, 80, 1, 0xe0, 0x10, 18, 1),
-	PIN_FIELD_BASE(81, 81, 1, 0xe0, 0x10, 19, 1),
-	PIN_FIELD_BASE(82, 82, 1, 0xe0, 0x10, 16, 1),
-	PIN_FIELD_BASE(83, 83, 1, 0xe0, 0x10, 17, 1),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_pu_range[] = {
-	PIN_FIELD_BASE(7, 7, 4, 0x60, 0x10, 5, 1),
-	PIN_FIELD_BASE(8, 8, 4, 0x60, 0x10, 4, 1),
-	PIN_FIELD_BASE(9, 9, 4, 0x60, 0x10, 3, 1),
-	PIN_FIELD_BASE(10, 10, 4, 0x60, 0x10, 2, 1),
-
-	PIN_FIELD_BASE(13, 13, 1, 0x70, 0x10, 0, 1),
-	PIN_FIELD_BASE(14, 14, 1, 0x70, 0x10, 1, 1),
-	PIN_FIELD_BASE(63, 63, 1, 0x70, 0x10, 2, 1),
-
-	PIN_FIELD_BASE(75, 75, 4, 0x60, 0x10, 7, 1),
-	PIN_FIELD_BASE(76, 76, 4, 0x60, 0x10, 6, 1),
-	PIN_FIELD_BASE(77, 77, 4, 0x60, 0x10, 1, 1),
-	PIN_FIELD_BASE(78, 78, 4, 0x60, 0x10, 0, 1),
-	PIN_FIELD_BASE(79, 79, 4, 0x60, 0x10, 8, 1),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_pd_range[] = {
-	PIN_FIELD_BASE(7, 7, 4, 0x40, 0x10, 5, 1),
-	PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1),
-	PIN_FIELD_BASE(9, 9, 4, 0x40, 0x10, 3, 1),
-	PIN_FIELD_BASE(10, 10, 4, 0x40, 0x10, 2, 1),
-
-	PIN_FIELD_BASE(13, 13, 1, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(14, 14, 1, 0x50, 0x10, 1, 1),
-
-	PIN_FIELD_BASE(15, 15, 5, 0x40, 0x10, 4, 1),
-	PIN_FIELD_BASE(16, 16, 5, 0x40, 0x10, 5, 1),
-	PIN_FIELD_BASE(17, 17, 5, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(18, 18, 5, 0x40, 0x10, 1, 1),
-
-	PIN_FIELD_BASE(63, 63, 1, 0x50, 0x10, 2, 1),
-	PIN_FIELD_BASE(71, 71, 5, 0x40, 0x10, 2, 1),
-	PIN_FIELD_BASE(72, 72, 5, 0x40, 0x10, 3, 1),
-
-	PIN_FIELD_BASE(75, 75, 4, 0x40, 0x10, 7, 1),
-	PIN_FIELD_BASE(76, 76, 4, 0x40, 0x10, 6, 1),
-	PIN_FIELD_BASE(77, 77, 4, 0x40, 0x10, 1, 1),
-	PIN_FIELD_BASE(78, 78, 4, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(79, 79, 4, 0x40, 0x10, 8, 1),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = {
-	PIN_FIELD_BASE(0, 0, 5, 0x00, 0x10, 21, 3),
-	PIN_FIELD_BASE(1, 1, 5, 0x00, 0x10, 24, 3),
-	PIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 15, 3),
-	PIN_FIELD_BASE(3, 3, 5, 0x00, 0x10, 18, 3),
-	PIN_FIELD_BASE(4, 4, 5, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(5, 5, 5, 0x00, 0x10, 9, 3),
-	PIN_FIELD_BASE(6, 6, 5, 0x00, 0x10, 12, 3),
-
-	PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 24, 3),
-	PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 28, 3),
-	PIN_FIELD_BASE(9, 9, 4, 0x00, 0x10, 15, 3),
-	PIN_FIELD_BASE(10, 10, 4, 0x00, 0x10, 9, 3),
-
-	PIN_FIELD_BASE(11, 11, 1, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(12, 12, 1, 0x20, 0x10, 3, 3),
-	PIN_FIELD_BASE(13, 13, 1, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(14, 14, 1, 0x00, 0x10, 6, 3),
-
-	PIN_FIELD_BASE(19, 19, 4, 0x00, 0x10, 21, 3),
-	PIN_FIELD_BASE(20, 20, 4, 0x00, 0x10, 12, 3),
-
-	PIN_FIELD_BASE(21, 21, 3, 0x10, 0x10, 21, 3),
-	PIN_FIELD_BASE(22, 22, 3, 0x20, 0x10, 9, 3),
-	PIN_FIELD_BASE(23, 23, 3, 0x20, 0x10, 0, 3),
-	PIN_FIELD_BASE(24, 24, 3, 0x10, 0x10, 27, 3),
-	PIN_FIELD_BASE(25, 25, 3, 0x20, 0x10, 3, 3),
-	PIN_FIELD_BASE(26, 26, 3, 0x20, 0x10, 6, 3),
-	PIN_FIELD_BASE(27, 27, 3, 0x10, 0x10, 24, 3),
-	PIN_FIELD_BASE(28, 28, 3, 0x20, 0x10, 15, 3),
-	PIN_FIELD_BASE(29, 29, 3, 0x20, 0x10, 18, 3),
-	PIN_FIELD_BASE(30, 30, 3, 0x20, 0x10, 21, 3),
-	PIN_FIELD_BASE(31, 31, 3, 0x20, 0x10, 12, 3),
-	PIN_FIELD_BASE(32, 32, 3, 0x20, 0x10, 24, 3),
-	PIN_FIELD_BASE(33, 33, 3, 0x30, 0x10, 6, 3),
-	PIN_FIELD_BASE(34, 34, 3, 0x30, 0x10, 3, 3),
-	PIN_FIELD_BASE(35, 35, 3, 0x20, 0x10, 27, 3),
-	PIN_FIELD_BASE(36, 36, 3, 0x30, 0x10, 0, 3),
-	PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 9, 3),
-	PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 3, 3),
-	PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 0, 3),
-	PIN_FIELD_BASE(40, 40, 3, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(41, 41, 3, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(42, 42, 3, 0x00, 0x10, 27, 3),
-	PIN_FIELD_BASE(43, 43, 3, 0x00, 0x10, 24, 3),
-	PIN_FIELD_BASE(44, 44, 3, 0x00, 0x10, 21, 3),
-	PIN_FIELD_BASE(45, 45, 3, 0x00, 0x10, 18, 3),
-	PIN_FIELD_BASE(46, 46, 3, 0x00, 0x10, 15, 3),
-	PIN_FIELD_BASE(47, 47, 3, 0x00, 0x10, 12, 3),
-	PIN_FIELD_BASE(48, 48, 3, 0x00, 0x10, 9, 3),
-	PIN_FIELD_BASE(49, 49, 3, 0x00, 0x10, 6, 3),
-	PIN_FIELD_BASE(50, 50, 3, 0x10, 0x10, 15, 3),
-	PIN_FIELD_BASE(51, 51, 3, 0x10, 0x10, 6, 3),
-	PIN_FIELD_BASE(52, 52, 3, 0x10, 0x10, 9, 3),
-	PIN_FIELD_BASE(53, 53, 3, 0x10, 0x10, 12, 3),
-	PIN_FIELD_BASE(54, 54, 3, 0x10, 0x10, 18, 3),
-
-	PIN_FIELD_BASE(55, 55, 1, 0x10, 0x10, 12, 3),
-	PIN_FIELD_BASE(56, 56, 1, 0x10, 0x10, 15, 3),
-	PIN_FIELD_BASE(57, 57, 1, 0x10, 0x10, 9, 3),
-	PIN_FIELD_BASE(58, 58, 1, 0x00, 0x10, 12, 3),
-	PIN_FIELD_BASE(59, 59, 1, 0x00, 0x10, 15, 3),
-	PIN_FIELD_BASE(60, 60, 1, 0x00, 0x10, 18, 3),
-	PIN_FIELD_BASE(61, 61, 1, 0x00, 0x10, 9, 3),
-	PIN_FIELD_BASE(62, 62, 1, 0x00, 0x10, 21, 3),
-	PIN_FIELD_BASE(63, 63, 1, 0x20, 0x10, 0, 3),
-	PIN_FIELD_BASE(64, 64, 1, 0x00, 0x10, 24, 3),
-	PIN_FIELD_BASE(65, 65, 1, 0x00, 0x10, 27, 3),
-	PIN_FIELD_BASE(66, 66, 1, 0x10, 0x10, 0, 3),
-	PIN_FIELD_BASE(67, 67, 1, 0x10, 0x10, 3, 3),
-	PIN_FIELD_BASE(68, 68, 1, 0x10, 0x10, 6, 3),
-
-	PIN_FIELD_BASE(69, 69, 5, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(70, 70, 5, 0x00, 0x10, 6, 3),
-
-	PIN_FIELD_BASE(73, 73, 4, 0x10, 0x10, 0, 3),
-	PIN_FIELD_BASE(74, 74, 4, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(75, 75, 4, 0x10, 0x10, 3, 3),
-	PIN_FIELD_BASE(76, 76, 4, 0x00, 0x10, 27, 3),
-	PIN_FIELD_BASE(77, 77, 4, 0x00, 0x10, 6, 3),
-	PIN_FIELD_BASE(78, 78, 4, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(79, 79, 4, 0x10, 0x10, 6, 3),
-
-	PIN_FIELD_BASE(80, 80, 1, 0x10, 0x10, 24, 3),
-	PIN_FIELD_BASE(81, 81, 1, 0x10, 0x10, 27, 3),
-	PIN_FIELD_BASE(82, 82, 1, 0x10, 0x10, 18, 3),
-	PIN_FIELD_BASE(83, 83, 1, 0x10, 0x10, 21, 3),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_pupd_range[] = {
-	PIN_FIELD_BASE(0, 0, 5, 0x50, 0x10, 7, 1),
-	PIN_FIELD_BASE(1, 1, 5, 0x50, 0x10, 8, 1),
-	PIN_FIELD_BASE(2, 2, 5, 0x50, 0x10, 5, 1),
-	PIN_FIELD_BASE(3, 3, 5, 0x50, 0x10, 6, 1),
-	PIN_FIELD_BASE(4, 4, 5, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(5, 5, 5, 0x50, 0x10, 3, 1),
-	PIN_FIELD_BASE(6, 6, 5, 0x50, 0x10, 4, 1),
-
-	PIN_FIELD_BASE(11, 11, 1, 0x60, 0x10, 0, 1),
-	PIN_FIELD_BASE(12, 12, 1, 0x60, 0x10, 18, 1),
-
-	PIN_FIELD_BASE(19, 19, 4, 0x50, 0x10, 2, 1),
-	PIN_FIELD_BASE(20, 20, 4, 0x50, 0x10, 1, 1),
-
-	PIN_FIELD_BASE(21, 21, 3, 0x70, 0x10, 17, 1),
-	PIN_FIELD_BASE(22, 22, 3, 0x70, 0x10, 23, 1),
-	PIN_FIELD_BASE(23, 23, 3, 0x70, 0x10, 20, 1),
-	PIN_FIELD_BASE(24, 24, 3, 0x70, 0x10, 19, 1),
-	PIN_FIELD_BASE(25, 25, 3, 0x70, 0x10, 21, 1),
-	PIN_FIELD_BASE(26, 26, 3, 0x70, 0x10, 22, 1),
-	PIN_FIELD_BASE(27, 27, 3, 0x70, 0x10, 18, 1),
-	PIN_FIELD_BASE(28, 28, 3, 0x70, 0x10, 25, 1),
-	PIN_FIELD_BASE(29, 29, 3, 0x70, 0x10, 26, 1),
-	PIN_FIELD_BASE(30, 30, 3, 0x70, 0x10, 27, 1),
-	PIN_FIELD_BASE(31, 31, 3, 0x70, 0x10, 24, 1),
-	PIN_FIELD_BASE(32, 32, 3, 0x70, 0x10, 28, 1),
-	PIN_FIELD_BASE(33, 33, 3, 0x80, 0x10, 0, 1),
-	PIN_FIELD_BASE(34, 34, 3, 0x70, 0x10, 31, 1),
-	PIN_FIELD_BASE(35, 35, 3, 0x70, 0x10, 29, 1),
-	PIN_FIELD_BASE(36, 36, 3, 0x70, 0x10, 30, 1),
-	PIN_FIELD_BASE(37, 37, 3, 0x80, 0x10, 1, 1),
-	PIN_FIELD_BASE(38, 38, 3, 0x70, 0x10, 11, 1),
-	PIN_FIELD_BASE(39, 39, 3, 0x70, 0x10, 10, 1),
-	PIN_FIELD_BASE(40, 40, 3, 0x70, 0x10, 0, 1),
-	PIN_FIELD_BASE(41, 41, 3, 0x70, 0x10, 1, 1),
-	PIN_FIELD_BASE(42, 42, 3, 0x70, 0x10, 9, 1),
-	PIN_FIELD_BASE(43, 43, 3, 0x70, 0x10, 8, 1),
-	PIN_FIELD_BASE(44, 44, 3, 0x70, 0x10, 7, 1),
-	PIN_FIELD_BASE(45, 45, 3, 0x70, 0x10, 6, 1),
-	PIN_FIELD_BASE(46, 46, 3, 0x70, 0x10, 5, 1),
-	PIN_FIELD_BASE(47, 47, 3, 0x70, 0x10, 4, 1),
-	PIN_FIELD_BASE(48, 48, 3, 0x70, 0x10, 3, 1),
-	PIN_FIELD_BASE(49, 49, 3, 0x70, 0x10, 2, 1),
-	PIN_FIELD_BASE(50, 50, 3, 0x70, 0x10, 15, 1),
-	PIN_FIELD_BASE(51, 51, 3, 0x70, 0x10, 12, 1),
-	PIN_FIELD_BASE(52, 52, 3, 0x70, 0x10, 13, 1),
-	PIN_FIELD_BASE(53, 53, 3, 0x70, 0x10, 14, 1),
-	PIN_FIELD_BASE(54, 54, 3, 0x70, 0x10, 16, 1),
-
-	PIN_FIELD_BASE(55, 55, 1, 0x60, 0x10, 12, 1),
-	PIN_FIELD_BASE(56, 56, 1, 0x60, 0x10, 13, 1),
-	PIN_FIELD_BASE(57, 57, 1, 0x60, 0x10, 11, 1),
-	PIN_FIELD_BASE(58, 58, 1, 0x60, 0x10, 2, 1),
-	PIN_FIELD_BASE(59, 59, 1, 0x60, 0x10, 3, 1),
-	PIN_FIELD_BASE(60, 60, 1, 0x60, 0x10, 4, 1),
-	PIN_FIELD_BASE(61, 61, 1, 0x60, 0x10, 1, 1),
-	PIN_FIELD_BASE(62, 62, 1, 0x60, 0x10, 5, 1),
-	PIN_FIELD_BASE(64, 64, 1, 0x60, 0x10, 6, 1),
-	PIN_FIELD_BASE(65, 65, 1, 0x60, 0x10, 7, 1),
-	PIN_FIELD_BASE(66, 66, 1, 0x60, 0x10, 8, 1),
-	PIN_FIELD_BASE(67, 67, 1, 0x60, 0x10, 9, 1),
-	PIN_FIELD_BASE(68, 68, 1, 0x60, 0x10, 10, 1),
-
-	PIN_FIELD_BASE(69, 69, 5, 0x50, 0x10, 1, 1),
-	PIN_FIELD_BASE(70, 70, 5, 0x50, 0x10, 2, 1),
-
-	PIN_FIELD_BASE(73, 73, 4, 0x50, 0x10, 3, 1),
-	PIN_FIELD_BASE(74, 74, 4, 0x50, 0x10, 0, 1),
-
-	PIN_FIELD_BASE(80, 80, 1, 0x60, 0x10, 16, 1),
-	PIN_FIELD_BASE(81, 81, 1, 0x60, 0x10, 17, 1),
-	PIN_FIELD_BASE(82, 82, 1, 0x60, 0x10, 14, 1),
-	PIN_FIELD_BASE(83, 83, 1, 0x60, 0x10, 15, 1),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_r0_range[] = {
-	PIN_FIELD_BASE(0, 0, 5, 0x60, 0x10, 7, 1),
-	PIN_FIELD_BASE(1, 1, 5, 0x60, 0x10, 8, 1),
-	PIN_FIELD_BASE(2, 2, 5, 0x60, 0x10, 5, 1),
-	PIN_FIELD_BASE(3, 3, 5, 0x60, 0x10, 6, 1),
-	PIN_FIELD_BASE(4, 4, 5, 0x60, 0x10, 0, 1),
-	PIN_FIELD_BASE(5, 5, 5, 0x60, 0x10, 3, 1),
-	PIN_FIELD_BASE(6, 6, 5, 0x60, 0x10, 4, 1),
-
-	PIN_FIELD_BASE(11, 11, 1, 0x80, 0x10, 0, 1),
-	PIN_FIELD_BASE(12, 12, 1, 0x80, 0x10, 18, 1),
-
-	PIN_FIELD_BASE(19, 19, 4, 0x70, 0x10, 2, 1),
-	PIN_FIELD_BASE(20, 20, 4, 0x70, 0x10, 1, 1),
-
-	PIN_FIELD_BASE(21, 21, 3, 0x90, 0x10, 17, 1),
-	PIN_FIELD_BASE(22, 22, 3, 0x90, 0x10, 23, 1),
-	PIN_FIELD_BASE(23, 23, 3, 0x90, 0x10, 20, 1),
-	PIN_FIELD_BASE(24, 24, 3, 0x90, 0x10, 19, 1),
-	PIN_FIELD_BASE(25, 25, 3, 0x90, 0x10, 21, 1),
-	PIN_FIELD_BASE(26, 26, 3, 0x90, 0x10, 22, 1),
-	PIN_FIELD_BASE(27, 27, 3, 0x90, 0x10, 18, 1),
-	PIN_FIELD_BASE(28, 28, 3, 0x90, 0x10, 25, 1),
-	PIN_FIELD_BASE(29, 29, 3, 0x90, 0x10, 26, 1),
-	PIN_FIELD_BASE(30, 30, 3, 0x90, 0x10, 27, 1),
-	PIN_FIELD_BASE(31, 31, 3, 0x90, 0x10, 24, 1),
-	PIN_FIELD_BASE(32, 32, 3, 0x90, 0x10, 28, 1),
-	PIN_FIELD_BASE(33, 33, 3, 0xa0, 0x10, 0, 1),
-	PIN_FIELD_BASE(34, 34, 3, 0x90, 0x10, 31, 1),
-	PIN_FIELD_BASE(35, 35, 3, 0x90, 0x10, 29, 1),
-	PIN_FIELD_BASE(36, 36, 3, 0x90, 0x10, 30, 1),
-	PIN_FIELD_BASE(37, 37, 3, 0xa0, 0x10, 1, 1),
-	PIN_FIELD_BASE(38, 38, 3, 0x90, 0x10, 11, 1),
-	PIN_FIELD_BASE(39, 39, 3, 0x90, 0x10, 10, 1),
-	PIN_FIELD_BASE(40, 40, 3, 0x90, 0x10, 0, 1),
-	PIN_FIELD_BASE(41, 41, 3, 0x90, 0x10, 1, 1),
-	PIN_FIELD_BASE(42, 42, 3, 0x90, 0x10, 9, 1),
-	PIN_FIELD_BASE(43, 43, 3, 0x90, 0x10, 8, 1),
-	PIN_FIELD_BASE(44, 44, 3, 0x90, 0x10, 7, 1),
-	PIN_FIELD_BASE(45, 45, 3, 0x90, 0x10, 6, 1),
-	PIN_FIELD_BASE(46, 46, 3, 0x90, 0x10, 5, 1),
-	PIN_FIELD_BASE(47, 47, 3, 0x90, 0x10, 4, 1),
-	PIN_FIELD_BASE(48, 48, 3, 0x90, 0x10, 3, 1),
-	PIN_FIELD_BASE(49, 49, 3, 0x90, 0x10, 2, 1),
-	PIN_FIELD_BASE(50, 50, 3, 0x90, 0x10, 15, 1),
-	PIN_FIELD_BASE(51, 51, 3, 0x90, 0x10, 12, 1),
-	PIN_FIELD_BASE(52, 52, 3, 0x90, 0x10, 13, 1),
-	PIN_FIELD_BASE(53, 53, 3, 0x90, 0x10, 14, 1),
-	PIN_FIELD_BASE(54, 54, 3, 0x90, 0x10, 16, 1),
-
-	PIN_FIELD_BASE(55, 55, 1, 0x80, 0x10, 12, 1),
-	PIN_FIELD_BASE(56, 56, 1, 0x80, 0x10, 13, 1),
-	PIN_FIELD_BASE(57, 57, 1, 0x80, 0x10, 11, 1),
-	PIN_FIELD_BASE(58, 58, 1, 0x80, 0x10, 2, 1),
-	PIN_FIELD_BASE(59, 59, 1, 0x80, 0x10, 3, 1),
-	PIN_FIELD_BASE(60, 60, 1, 0x80, 0x10, 4, 1),
-	PIN_FIELD_BASE(61, 61, 1, 0x80, 0x10, 1, 1),
-	PIN_FIELD_BASE(62, 62, 1, 0x80, 0x10, 5, 1),
-	PIN_FIELD_BASE(64, 64, 1, 0x80, 0x10, 6, 1),
-	PIN_FIELD_BASE(65, 65, 1, 0x80, 0x10, 7, 1),
-	PIN_FIELD_BASE(66, 66, 1, 0x80, 0x10, 8, 1),
-	PIN_FIELD_BASE(67, 67, 1, 0x80, 0x10, 9, 1),
-	PIN_FIELD_BASE(68, 68, 1, 0x80, 0x10, 10, 1),
-
-	PIN_FIELD_BASE(69, 69, 5, 0x60, 0x10, 1, 1),
-	PIN_FIELD_BASE(70, 70, 5, 0x60, 0x10, 2, 1),
-
-	PIN_FIELD_BASE(73, 73, 4, 0x70, 0x10, 3, 1),
-	PIN_FIELD_BASE(74, 74, 4, 0x70, 0x10, 0, 1),
-
-	PIN_FIELD_BASE(80, 80, 1, 0x80, 0x10, 16, 1),
-	PIN_FIELD_BASE(81, 81, 1, 0x80, 0x10, 17, 1),
-	PIN_FIELD_BASE(82, 82, 1, 0x80, 0x10, 14, 1),
-	PIN_FIELD_BASE(83, 83, 1, 0x80, 0x10, 15, 1),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_r1_range[] = {
-	PIN_FIELD_BASE(0, 0, 5, 0x70, 0x10, 7, 1),
-	PIN_FIELD_BASE(1, 1, 5, 0x70, 0x10, 8, 1),
-	PIN_FIELD_BASE(2, 2, 5, 0x70, 0x10, 5, 1),
-	PIN_FIELD_BASE(3, 3, 5, 0x70, 0x10, 6, 1),
-	PIN_FIELD_BASE(4, 4, 5, 0x70, 0x10, 0, 1),
-	PIN_FIELD_BASE(5, 5, 5, 0x70, 0x10, 3, 1),
-	PIN_FIELD_BASE(6, 6, 5, 0x70, 0x10, 4, 1),
-
-	PIN_FIELD_BASE(11, 11, 1, 0x90, 0x10, 0, 1),
-	PIN_FIELD_BASE(12, 12, 1, 0x90, 0x10, 18, 1),
-
-	PIN_FIELD_BASE(19, 19, 4, 0x80, 0x10, 2, 1),
-	PIN_FIELD_BASE(20, 20, 4, 0x80, 0x10, 1, 1),
-
-	PIN_FIELD_BASE(21, 21, 3, 0xb0, 0x10, 17, 1),
-	PIN_FIELD_BASE(22, 22, 3, 0xb0, 0x10, 23, 1),
-	PIN_FIELD_BASE(23, 23, 3, 0xb0, 0x10, 20, 1),
-	PIN_FIELD_BASE(24, 24, 3, 0xb0, 0x10, 19, 1),
-	PIN_FIELD_BASE(25, 25, 3, 0xb0, 0x10, 21, 1),
-	PIN_FIELD_BASE(26, 26, 3, 0xb0, 0x10, 22, 1),
-	PIN_FIELD_BASE(27, 27, 3, 0xb0, 0x10, 18, 1),
-	PIN_FIELD_BASE(28, 28, 3, 0xb0, 0x10, 25, 1),
-	PIN_FIELD_BASE(29, 29, 3, 0xb0, 0x10, 26, 1),
-	PIN_FIELD_BASE(30, 30, 3, 0xb0, 0x10, 27, 1),
-	PIN_FIELD_BASE(31, 31, 3, 0xb0, 0x10, 24, 1),
-	PIN_FIELD_BASE(32, 32, 3, 0xb0, 0x10, 28, 1),
-	PIN_FIELD_BASE(33, 33, 3, 0xc0, 0x10, 0, 1),
-	PIN_FIELD_BASE(34, 34, 3, 0xb0, 0x10, 31, 1),
-	PIN_FIELD_BASE(35, 35, 3, 0xb0, 0x10, 29, 1),
-	PIN_FIELD_BASE(36, 36, 3, 0xb0, 0x10, 30, 1),
-	PIN_FIELD_BASE(37, 37, 3, 0xc0, 0x10, 1, 1),
-	PIN_FIELD_BASE(38, 38, 3, 0xb0, 0x10, 11, 1),
-	PIN_FIELD_BASE(39, 39, 3, 0xb0, 0x10, 10, 1),
-	PIN_FIELD_BASE(40, 40, 3, 0xb0, 0x10, 0, 1),
-	PIN_FIELD_BASE(41, 41, 3, 0xb0, 0x10, 1, 1),
-	PIN_FIELD_BASE(42, 42, 3, 0xb0, 0x10, 9, 1),
-	PIN_FIELD_BASE(43, 43, 3, 0xb0, 0x10, 8, 1),
-	PIN_FIELD_BASE(44, 44, 3, 0xb0, 0x10, 7, 1),
-	PIN_FIELD_BASE(45, 45, 3, 0xb0, 0x10, 6, 1),
-	PIN_FIELD_BASE(46, 46, 3, 0xb0, 0x10, 5, 1),
-	PIN_FIELD_BASE(47, 47, 3, 0xb0, 0x10, 4, 1),
-	PIN_FIELD_BASE(48, 48, 3, 0xb0, 0x10, 3, 1),
-	PIN_FIELD_BASE(49, 49, 3, 0xb0, 0x10, 2, 1),
-	PIN_FIELD_BASE(50, 50, 3, 0xb0, 0x10, 15, 1),
-	PIN_FIELD_BASE(51, 51, 3, 0xb0, 0x10, 12, 1),
-	PIN_FIELD_BASE(52, 52, 3, 0xb0, 0x10, 13, 1),
-	PIN_FIELD_BASE(53, 53, 3, 0xb0, 0x10, 14, 1),
-	PIN_FIELD_BASE(54, 54, 3, 0xb0, 0x10, 16, 1),
-
-	PIN_FIELD_BASE(55, 55, 1, 0x90, 0x10, 12, 1),
-	PIN_FIELD_BASE(56, 56, 1, 0x90, 0x10, 13, 1),
-	PIN_FIELD_BASE(57, 57, 1, 0x90, 0x10, 11, 1),
-	PIN_FIELD_BASE(58, 58, 1, 0x90, 0x10, 2, 1),
-	PIN_FIELD_BASE(59, 59, 1, 0x90, 0x10, 3, 1),
-	PIN_FIELD_BASE(60, 60, 1, 0x90, 0x10, 4, 1),
-	PIN_FIELD_BASE(61, 61, 1, 0x90, 0x10, 1, 1),
-	PIN_FIELD_BASE(62, 62, 1, 0x90, 0x10, 5, 1),
-	PIN_FIELD_BASE(64, 64, 1, 0x90, 0x10, 6, 1),
-	PIN_FIELD_BASE(65, 65, 1, 0x90, 0x10, 7, 1),
-	PIN_FIELD_BASE(66, 66, 1, 0x90, 0x10, 8, 1),
-	PIN_FIELD_BASE(67, 67, 1, 0x90, 0x10, 9, 1),
-	PIN_FIELD_BASE(68, 68, 1, 0x90, 0x10, 10, 1),
-
-	PIN_FIELD_BASE(69, 69, 5, 0x70, 0x10, 1, 1),
-	PIN_FIELD_BASE(70, 70, 5, 0x70, 0x10, 2, 1),
-
-	PIN_FIELD_BASE(73, 73, 4, 0x80, 0x10, 3, 1),
-	PIN_FIELD_BASE(74, 74, 4, 0x80, 0x10, 0, 1),
-
-	PIN_FIELD_BASE(80, 80, 1, 0x90, 0x10, 16, 1),
-	PIN_FIELD_BASE(81, 81, 1, 0x90, 0x10, 17, 1),
-	PIN_FIELD_BASE(82, 82, 1, 0x90, 0x10, 14, 1),
-	PIN_FIELD_BASE(83, 83, 1, 0x90, 0x10, 15, 1),
-};
-
-static const struct mtk_pin_reg_calc mt7988_reg_cals[] = {
-	[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7988_pin_mode_range),
-	[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7988_pin_dir_range),
-	[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7988_pin_di_range),
-	[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7988_pin_do_range),
-	[PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7988_pin_smt_range),
-	[PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7988_pin_ies_range),
-	[PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7988_pin_pu_range),
-	[PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7988_pin_pd_range),
-	[PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7988_pin_drv_range),
-	[PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7988_pin_pupd_range),
-	[PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7988_pin_r0_range),
-	[PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7988_pin_r1_range),
-};
-
-static const struct mtk_pin_desc mt7988_pins[] = {
-	MT7988_PIN(0, "UART2_RXD"),
-	MT7988_PIN(1, "UART2_TXD"),
-	MT7988_PIN(2, "UART2_CTS"),
-	MT7988_PIN(3, "UART2_RTS"),
-	MT7988_PIN(4, "GPIO_A"),
-	MT7988_PIN(5, "SMI_0_MDC"),
-	MT7988_PIN(6, "SMI_0_MDIO"),
-	MT7988_PIN(7, "PCIE30_2L_0_WAKE_N"),
-	MT7988_PIN(8, "PCIE30_2L_0_CLKREQ_N"),
-	MT7988_PIN(9, "PCIE30_1L_1_WAKE_N"),
-	MT7988_PIN(10, "PCIE30_1L_1_CLKREQ_N"),
-	MT7988_PIN(11, "GPIO_P"),
-	MT7988_PIN(12, "WATCHDOG"),
-	MT7988_PIN(13, "GPIO_RESET"),
-	MT7988_PIN(14, "GPIO_WPS"),
-	MT7988_PIN(15, "PMIC_I2C_SCL"),
-	MT7988_PIN(16, "PMIC_I2C_SDA"),
-	MT7988_PIN(17, "I2C_1_SCL"),
-	MT7988_PIN(18, "I2C_1_SDA"),
-	MT7988_PIN(19, "PCIE30_2L_0_PRESET_N"),
-	MT7988_PIN(20, "PCIE30_1L_1_PRESET_N"),
-	MT7988_PIN(21, "PWMD1"),
-	MT7988_PIN(22, "SPI0_WP"),
-	MT7988_PIN(23, "SPI0_HOLD"),
-	MT7988_PIN(24, "SPI0_CSB"),
-	MT7988_PIN(25, "SPI0_MISO"),
-	MT7988_PIN(26, "SPI0_MOSI"),
-	MT7988_PIN(27, "SPI0_CLK"),
-	MT7988_PIN(28, "SPI1_CSB"),
-	MT7988_PIN(29, "SPI1_MISO"),
-	MT7988_PIN(30, "SPI1_MOSI"),
-	MT7988_PIN(31, "SPI1_CLK"),
-	MT7988_PIN(32, "SPI2_CLK"),
-	MT7988_PIN(33, "SPI2_MOSI"),
-	MT7988_PIN(34, "SPI2_MISO"),
-	MT7988_PIN(35, "SPI2_CSB"),
-	MT7988_PIN(36, "SPI2_HOLD"),
-	MT7988_PIN(37, "SPI2_WP"),
-	MT7988_PIN(38, "EMMC_RSTB"),
-	MT7988_PIN(39, "EMMC_DSL"),
-	MT7988_PIN(40, "EMMC_CK"),
-	MT7988_PIN(41, "EMMC_CMD"),
-	MT7988_PIN(42, "EMMC_DATA_7"),
-	MT7988_PIN(43, "EMMC_DATA_6"),
-	MT7988_PIN(44, "EMMC_DATA_5"),
-	MT7988_PIN(45, "EMMC_DATA_4"),
-	MT7988_PIN(46, "EMMC_DATA_3"),
-	MT7988_PIN(47, "EMMC_DATA_2"),
-	MT7988_PIN(48, "EMMC_DATA_1"),
-	MT7988_PIN(49, "EMMC_DATA_0"),
-	MT7988_PIN(50, "PCM_FS_I2S_LRCK"),
-	MT7988_PIN(51, "PCM_CLK_I2S_BCLK"),
-	MT7988_PIN(52, "PCM_DRX_I2S_DIN"),
-	MT7988_PIN(53, "PCM_DTX_I2S_DOUT"),
-	MT7988_PIN(54, "PCM_MCK_I2S_MCLK"),
-	MT7988_PIN(55, "UART0_RXD"),
-	MT7988_PIN(56, "UART0_TXD"),
-	MT7988_PIN(57, "PWMD0"),
-	MT7988_PIN(58, "JTAG_JTDI"),
-	MT7988_PIN(59, "JTAG_JTDO"),
-	MT7988_PIN(60, "JTAG_JTMS"),
-	MT7988_PIN(61, "JTAG_JTCLK"),
-	MT7988_PIN(62, "JTAG_JTRST_N"),
-	MT7988_PIN(63, "USB_DRV_VBUS_P1"),
-	MT7988_PIN(64, "LED_A"),
-	MT7988_PIN(65, "LED_B"),
-	MT7988_PIN(66, "LED_C"),
-	MT7988_PIN(67, "LED_D"),
-	MT7988_PIN(68, "LED_E"),
-	MT7988_PIN(69, "GPIO_B"),
-	MT7988_PIN(70, "GPIO_C"),
-	MT7988_PIN(71, "I2C_2_SCL"),
-	MT7988_PIN(72, "I2C_2_SDA"),
-	MT7988_PIN(73, "PCIE30_2L_1_PRESET_N"),
-	MT7988_PIN(74, "PCIE30_1L_0_PRESET_N"),
-	MT7988_PIN(75, "PCIE30_2L_1_WAKE_N"),
-	MT7988_PIN(76, "PCIE30_2L_1_CLKREQ_N"),
-	MT7988_PIN(77, "PCIE30_1L_0_WAKE_N"),
-	MT7988_PIN(78, "PCIE30_1L_0_CLKREQ_N"),
-	MT7988_PIN(79, "USB_DRV_VBUS_P0"),
-	MT7988_PIN(80, "UART1_RXD"),
-	MT7988_PIN(81, "UART1_TXD"),
-	MT7988_PIN(82, "UART1_CTS"),
-	MT7988_PIN(83, "UART1_RTS"),
-};
-
-/* jtag */
-static int mt7988_tops_jtag0_0_pins[] = { 0, 1, 2, 3, 4 };
-static int mt7988_tops_jtag0_0_funcs[] = { 2, 2, 2, 2, 2 };
-
-static int mt7988_wo0_jtag_pins[] = { 50, 51, 52, 53, 54 };
-static int mt7988_wo0_jtag_funcs[] = { 3, 3, 3, 3, 3 };
-
-static int mt7988_wo1_jtag_pins[] = { 50, 51, 52, 53, 54 };
-static int mt7988_wo1_jtag_funcs[] = { 4, 4, 4, 4, 4 };
-
-static int mt7988_wo2_jtag_pins[] = { 50, 51, 52, 53, 54 };
-static int mt7988_wo2_jtag_funcs[] = { 5, 5, 5, 5, 5 };
-
-static int mt7988_jtag_pins[] = { 58, 59, 60, 61, 62 };
-static int mt7988_jtag_funcs[] = { 1, 1, 1, 1, 1 };
-
-static int mt7988_tops_jtag0_1_pins[] = { 58, 59, 60, 61, 62 };
-static int mt7988_tops_jtag0_1_funcs[] = { 4, 4, 4, 4, 4 };
-
-/* int_usxgmii */
-static int mt7988_int_usxgmii_pins[] = { 2, 3 };
-static int mt7988_int_usxgmii_funcs[] = { 3, 3 };
-
-/* pwm */
-static int mt7988_pwm0_pins[] = { 57 };
-static int mt7988_pwm0_funcs[] = { 1 };
-
-static int mt7988_pwm1_pins[] = { 21 };
-static int mt7988_pwm1_funcs[] = { 1 };
-
-static int mt7988_pwm2_pins[] = { 80 };
-static int mt7988_pwm2_funcs[] = { 2 };
-
-static int mt7988_pwm3_pins[] = { 81 };
-static int mt7988_pwm3_funcs[] = { 2 };
-
-static int mt7988_pwm4_pins[] = { 82 };
-static int mt7988_pwm4_funcs[] = { 2 };
-
-static int mt7988_pwm5_pins[] = { 83 };
-static int mt7988_pwm5_funcs[] = { 2 };
-
-static int mt7988_pwm6_pins[] = { 69 };
-static int mt7988_pwm6_funcs[] = { 3 };
-
-static int mt7988_pwm7_pins[] = { 70 };
-static int mt7988_pwm7_funcs[] = { 3 };
-
-/* dfd */
-static int mt7988_dfd_pins[] = { 0, 1, 2, 3, 4 };
-static int mt7988_dfd_funcs[] = { 4, 4, 4, 4, 4 };
-
-/* i2c */
-static int mt7988_xfi_phy0_i2c0_pins[] = { 0, 1 };
-static int mt7988_xfi_phy0_i2c0_funcs[] = { 5, 5 };
-
-static int mt7988_xfi_phy1_i2c0_pins[] = { 0, 1 };
-static int mt7988_xfi_phy1_i2c0_funcs[] = { 6, 6 };
-
-static int mt7988_xfi_phy_pll_i2c0_pins[] = { 3, 4 };
-static int mt7988_xfi_phy_pll_i2c0_funcs[] = { 5, 5 };
-
-static int mt7988_xfi_phy_pll_i2c1_pins[] = { 3, 4 };
-static int mt7988_xfi_phy_pll_i2c1_funcs[] = { 6, 6 };
-
-static int mt7988_i2c0_0_pins[] = { 5, 6 };
-static int mt7988_i2c0_0_funcs[] = { 2, 2 };
-
-static int mt7988_i2c1_sfp_pins[] = { 5, 6 };
-static int mt7988_i2c1_sfp_funcs[] = { 4, 4 };
-
-static int mt7988_xfi_pextp_phy0_i2c_pins[] = { 5, 6 };
-static int mt7988_xfi_pextp_phy0_i2c_funcs[] = { 5, 5 };
-
-static int mt7988_xfi_pextp_phy1_i2c_pins[] = { 5, 6 };
-static int mt7988_xfi_pextp_phy1_i2c_funcs[] = { 6, 6 };
-
-static int mt7988_i2c0_1_pins[] = { 15, 16 };
-static int mt7988_i2c0_1_funcs[] = { 1, 1 };
-
-static int mt7988_u30_phy_i2c0_pins[] = { 15, 16 };
-static int mt7988_u30_phy_i2c0_funcs[] = { 2, 2 };
-
-static int mt7988_u32_phy_i2c0_pins[] = { 15, 16 };
-static int mt7988_u32_phy_i2c0_funcs[] = { 3, 3 };
-
-static int mt7988_xfi_phy0_i2c1_pins[] = { 15, 16 };
-static int mt7988_xfi_phy0_i2c1_funcs[] = { 5, 5 };
-
-static int mt7988_xfi_phy1_i2c1_pins[] = { 15, 16 };
-static int mt7988_xfi_phy1_i2c1_funcs[] = { 6, 6 };
-
-static int mt7988_xfi_phy_pll_i2c2_pins[] = { 15, 16 };
-static int mt7988_xfi_phy_pll_i2c2_funcs[] = { 7, 7 };
-
-static int mt7988_i2c1_0_pins[] = { 17, 18 };
-static int mt7988_i2c1_0_funcs[] = { 1, 1 };
-
-static int mt7988_u30_phy_i2c1_pins[] = { 17, 18 };
-static int mt7988_u30_phy_i2c1_funcs[] = { 2, 2 };
-
-static int mt7988_u32_phy_i2c1_pins[] = { 17, 18 };
-static int mt7988_u32_phy_i2c1_funcs[] = { 3, 3 };
-
-static int mt7988_xfi_phy_pll_i2c3_pins[] = { 17, 18 };
-static int mt7988_xfi_phy_pll_i2c3_funcs[] = { 4, 4 };
-
-static int mt7988_sgmii0_i2c_pins[] = { 17, 18 };
-static int mt7988_sgmii0_i2c_funcs[] = { 5, 5 };
-
-static int mt7988_sgmii1_i2c_pins[] = { 17, 18 };
-static int mt7988_sgmii1_i2c_funcs[] = { 6, 6 };
-
-static int mt7988_i2c1_2_pins[] = { 69, 70 };
-static int mt7988_i2c1_2_funcs[] = { 2, 2 };
-
-static int mt7988_i2c2_0_pins[] = { 69, 70 };
-static int mt7988_i2c2_0_funcs[] = { 4, 4 };
-
-static int mt7988_i2c2_1_pins[] = { 71, 72 };
-static int mt7988_i2c2_1_funcs[] = { 1, 1 };
-
-/* eth */
-static int mt7988_mdc_mdio0_pins[] = { 5, 6 };
-static int mt7988_mdc_mdio0_funcs[] = { 1, 1 };
-
-static int mt7988_2p5g_ext_mdio_pins[] = { 28, 29 };
-static int mt7988_2p5g_ext_mdio_funcs[] = { 6, 6 };
-
-static int mt7988_gbe_ext_mdio_pins[] = { 30, 31 };
-static int mt7988_gbe_ext_mdio_funcs[] = { 6, 6 };
-
-static int mt7988_mdc_mdio1_pins[] = { 69, 70 };
-static int mt7988_mdc_mdio1_funcs[] = { 1, 1 };
-
-/* pcie */
-static int mt7988_pcie_wake_n0_0_pins[] = { 7 };
-static int mt7988_pcie_wake_n0_0_funcs[] = { 1 };
-
-static int mt7988_pcie_clk_req_n0_0_pins[] = { 8 };
-static int mt7988_pcie_clk_req_n0_0_funcs[] = { 1 };
-
-static int mt7988_pcie_wake_n3_0_pins[] = { 9 };
-static int mt7988_pcie_wake_n3_0_funcs[] = { 1 };
-
-static int mt7988_pcie_clk_req_n3_pins[] = { 10 };
-static int mt7988_pcie_clk_req_n3_funcs[] = { 1 };
-
-static int mt7988_pcie_clk_req_n0_1_pins[] = { 10 };
-static int mt7988_pcie_clk_req_n0_1_funcs[] = { 2 };
-
-static int mt7988_pcie_p0_phy_i2c_pins[] = { 7, 8 };
-static int mt7988_pcie_p0_phy_i2c_funcs[] = { 3, 3 };
-
-static int mt7988_pcie_p1_phy_i2c_pins[] = { 7, 8 };
-static int mt7988_pcie_p1_phy_i2c_funcs[] = { 4, 4 };
-
-static int mt7988_pcie_p3_phy_i2c_pins[] = { 9, 10 };
-static int mt7988_pcie_p3_phy_i2c_funcs[] = { 4, 4 };
-
-static int mt7988_pcie_p2_phy_i2c_pins[] = { 7, 8 };
-static int mt7988_pcie_p2_phy_i2c_funcs[] = { 5, 5 };
-
-static int mt7988_ckm_phy_i2c_pins[] = { 9, 10 };
-static int mt7988_ckm_phy_i2c_funcs[] = { 5, 5 };
-
-static int mt7988_pcie_wake_n0_1_pins[] = { 13 };
-static int mt7988_pcie_wake_n0_1_funcs[] = { 2 };
-
-static int mt7988_pcie_wake_n3_1_pins[] = { 14 };
-static int mt7988_pcie_wake_n3_1_funcs[] = { 2 };
-
-static int mt7988_pcie_2l_0_pereset_pins[] = { 19 };
-static int mt7988_pcie_2l_0_pereset_funcs[] = { 1 };
-
-static int mt7988_pcie_1l_1_pereset_pins[] = { 20 };
-static int mt7988_pcie_1l_1_pereset_funcs[] = { 1 };
-
-static int mt7988_pcie_clk_req_n2_1_pins[] = { 63 };
-static int mt7988_pcie_clk_req_n2_1_funcs[] = { 2 };
-
-static int mt7988_pcie_2l_1_pereset_pins[] = { 73 };
-static int mt7988_pcie_2l_1_pereset_funcs[] = { 1 };
-
-static int mt7988_pcie_1l_0_pereset_pins[] = { 74 };
-static int mt7988_pcie_1l_0_pereset_funcs[] = { 1 };
-
-static int mt7988_pcie_wake_n1_0_pins[] = { 75 };
-static int mt7988_pcie_wake_n1_0_funcs[] = { 1 };
-
-static int mt7988_pcie_clk_req_n1_pins[] = { 76 };
-static int mt7988_pcie_clk_req_n1_funcs[] = { 1 };
-
-static int mt7988_pcie_wake_n2_0_pins[] = { 77 };
-static int mt7988_pcie_wake_n2_0_funcs[] = { 1 };
-
-static int mt7988_pcie_clk_req_n2_0_pins[] = { 78 };
-static int mt7988_pcie_clk_req_n2_0_funcs[] = { 1 };
-
-static int mt7988_pcie_wake_n2_1_pins[] = { 79 };
-static int mt7988_pcie_wake_n2_1_funcs[] = { 2 };
-
-/* pmic */
-static int mt7988_pmic_pins[] = { 11 };
-static int mt7988_pmic_funcs[] = { 1 };
-
-/* watchdog */
-static int mt7988_watchdog_pins[] = { 12 };
-static int mt7988_watchdog_funcs[] = { 1 };
-
-/* spi */
-static int mt7988_spi0_wp_hold_pins[] = { 22, 23 };
-static int mt7988_spi0_wp_hold_funcs[] = { 1, 1 };
-
-static int mt7988_spi0_pins[] = { 24, 25, 26, 27 };
-static int mt7988_spi0_funcs[] = { 1, 1, 1, 1 };
-
-static int mt7988_spi1_pins[] = { 28, 29, 30, 31 };
-static int mt7988_spi1_funcs[] = { 1, 1, 1, 1 };
-
-static int mt7988_spi2_pins[] = { 32, 33, 34, 35 };
-static int mt7988_spi2_funcs[] = { 1, 1, 1, 1 };
-
-static int mt7988_spi2_wp_hold_pins[] = { 36, 37 };
-static int mt7988_spi2_wp_hold_funcs[] = { 1, 1 };
-
-/* flash */
-static int mt7988_snfi_pins[] = { 22, 23, 24, 25, 26, 27 };
-static int mt7988_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 };
-
-static int mt7988_emmc_45_pins[] = {
-	21, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37
-};
-static int mt7988_emmc_45_funcs[] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5 };
-
-static int mt7988_sdcard_pins[] = { 32, 33, 34, 35, 36, 37 };
-static int mt7988_sdcard_funcs[] = { 5, 5, 5, 5, 5, 5 };
-
-static int mt7988_emmc_51_pins[] = { 38, 39, 40, 41, 42, 43,
-				     44, 45, 46, 47, 48, 49 };
-static int mt7988_emmc_51_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
-
-/* uart */
-static int mt7988_uart2_pins[] = { 0, 1, 2, 3 };
-static int mt7988_uart2_funcs[] = { 1, 1, 1, 1 };
-
-static int mt7988_tops_uart0_0_pins[] = { 22, 23 };
-static int mt7988_tops_uart0_0_funcs[] = { 3, 3 };
-
-static int mt7988_uart2_0_pins[] = { 28, 29, 30, 31 };
-static int mt7988_uart2_0_funcs[] = { 2, 2, 2, 2 };
-
-static int mt7988_uart1_0_pins[] = { 32, 33, 34, 35 };
-static int mt7988_uart1_0_funcs[] = { 2, 2, 2, 2 };
-
-static int mt7988_uart2_1_pins[] = { 32, 33, 34, 35 };
-static int mt7988_uart2_1_funcs[] = { 3, 3, 3, 3 };
-
-static int mt7988_net_wo0_uart_txd_0_pins[] = { 28 };
-static int mt7988_net_wo0_uart_txd_0_funcs[] = { 3 };
-
-static int mt7988_net_wo1_uart_txd_0_pins[] = { 29 };
-static int mt7988_net_wo1_uart_txd_0_funcs[] = { 3 };
-
-static int mt7988_net_wo2_uart_txd_0_pins[] = { 30 };
-static int mt7988_net_wo2_uart_txd_0_funcs[] = { 3 };
-
-static int mt7988_tops_uart1_0_pins[] = { 28, 29 };
-static int mt7988_tops_uart1_0_funcs[] = { 4, 4 };
-
-static int mt7988_tops_uart0_1_pins[] = { 30, 31 };
-static int mt7988_tops_uart0_1_funcs[] = { 4, 4 };
-
-static int mt7988_tops_uart1_1_pins[] = { 36, 37 };
-static int mt7988_tops_uart1_1_funcs[] = { 3, 3 };
-
-static int mt7988_uart0_pins[] = { 55, 56 };
-static int mt7988_uart0_funcs[] = { 1, 1 };
-
-static int mt7988_tops_uart0_2_pins[] = { 55, 56 };
-static int mt7988_tops_uart0_2_funcs[] = { 2, 2 };
-
-static int mt7988_uart2_2_pins[] = { 50, 51, 52, 53 };
-static int mt7988_uart2_2_funcs[] = { 2, 2, 2, 2 };
-
-static int mt7988_uart1_1_pins[] = { 58, 59, 60, 61 };
-static int mt7988_uart1_1_funcs[] = { 2, 2, 2, 2 };
-
-static int mt7988_uart2_3_pins[] = { 58, 59, 60, 61 };
-static int mt7988_uart2_3_funcs[] = { 3, 3, 3, 3 };
-
-static int mt7988_uart1_2_pins[] = { 80, 81, 82, 83 };
-static int mt7988_uart1_2_funcs[] = { 1, 1, 1, 1 };
-
-static int mt7988_tops_uart1_2_pins[] = { 80, 81 };
-static int mt7988_tops_uart1_2_funcs[] = {
-	4,
-	4,
-};
-
-static int mt7988_net_wo0_uart_txd_1_pins[] = { 80 };
-static int mt7988_net_wo0_uart_txd_1_funcs[] = { 3 };
-
-static int mt7988_net_wo1_uart_txd_1_pins[] = { 81 };
-static int mt7988_net_wo1_uart_txd_1_funcs[] = { 3 };
-
-static int mt7988_net_wo2_uart_txd_1_pins[] = { 82 };
-static int mt7988_net_wo2_uart_txd_1_funcs[] = { 3 };
-
-/* udi */
-static int mt7988_udi_pins[] = { 32, 33, 34, 35, 36 };
-static int mt7988_udi_funcs[] = { 4, 4, 4, 4, 4 };
-
-/* i2s */
-static int mt7988_i2s_pins[] = { 50, 51, 52, 53, 54 };
-static int mt7988_i2s_funcs[] = { 1, 1, 1, 1, 1 };
-
-/* pcm */
-static int mt7988_pcm_pins[] = { 50, 51, 52, 53 };
-static int mt7988_pcm_funcs[] = { 1, 1, 1, 1 };
-
-/* led */
-static int mt7988_gbe0_led1_pins[] = { 58 };
-static int mt7988_gbe0_led1_funcs[] = { 6 };
-static int mt7988_gbe1_led1_pins[] = { 59 };
-static int mt7988_gbe1_led1_funcs[] = { 6 };
-static int mt7988_gbe2_led1_pins[] = { 60 };
-static int mt7988_gbe2_led1_funcs[] = { 6 };
-static int mt7988_gbe3_led1_pins[] = { 61 };
-static int mt7988_gbe3_led1_funcs[] = { 6 };
-
-static int mt7988_2p5gbe_led1_pins[] = { 62 };
-static int mt7988_2p5gbe_led1_funcs[] = { 6 };
-
-static int mt7988_gbe0_led0_pins[] = { 64 };
-static int mt7988_gbe0_led0_funcs[] = { 1 };
-static int mt7988_gbe1_led0_pins[] = { 65 };
-static int mt7988_gbe1_led0_funcs[] = { 1 };
-static int mt7988_gbe2_led0_pins[] = { 66 };
-static int mt7988_gbe2_led0_funcs[] = { 1 };
-static int mt7988_gbe3_led0_pins[] = { 67 };
-static int mt7988_gbe3_led0_funcs[] = { 1 };
-
-static int mt7988_2p5gbe_led0_pins[] = { 68 };
-static int mt7988_2p5gbe_led0_funcs[] = { 1 };
-
-/* usb */
-static int mt7988_drv_vbus_p1_pins[] = { 63 };
-static int mt7988_drv_vbus_p1_funcs[] = { 1 };
-
-static int mt7988_drv_vbus_pins[] = { 79 };
-static int mt7988_drv_vbus_funcs[] = { 1 };
-
-static const struct group_desc mt7988_groups[] = {
-	/*  @GPIO(0,1,2,3): uart2 */
-	PINCTRL_PIN_GROUP("uart2", mt7988_uart2),
-	/*  @GPIO(0,1,2,3,4): tops_jtag0_0 */
-	PINCTRL_PIN_GROUP("tops_jtag0_0", mt7988_tops_jtag0_0),
-	/*  @GPIO(2,3): int_usxgmii */
-	PINCTRL_PIN_GROUP("int_usxgmii", mt7988_int_usxgmii),
-	/*  @GPIO(0,1,2,3,4): dfd */
-	PINCTRL_PIN_GROUP("dfd", mt7988_dfd),
-	/*  @GPIO(0,1): xfi_phy0_i2c0 */
-	PINCTRL_PIN_GROUP("xfi_phy0_i2c0", mt7988_xfi_phy0_i2c0),
-	/*  @GPIO(0,1): xfi_phy1_i2c0 */
-	PINCTRL_PIN_GROUP("xfi_phy1_i2c0", mt7988_xfi_phy1_i2c0),
-	/*  @GPIO(3,4): xfi_phy_pll_i2c0 */
-	PINCTRL_PIN_GROUP("xfi_phy_pll_i2c0", mt7988_xfi_phy_pll_i2c0),
-	/*  @GPIO(3,4): xfi_phy_pll_i2c1 */
-	PINCTRL_PIN_GROUP("xfi_phy_pll_i2c1", mt7988_xfi_phy_pll_i2c1),
-	/*  @GPIO(5,6) i2c0_0 */
-	PINCTRL_PIN_GROUP("i2c0_0", mt7988_i2c0_0),
-	/*  @GPIO(5,6) i2c1_sfp */
-	PINCTRL_PIN_GROUP("i2c1_sfp", mt7988_i2c1_sfp),
-	/*  @GPIO(5,6) xfi_pextp_phy0_i2c */
-	PINCTRL_PIN_GROUP("xfi_pextp_phy0_i2c", mt7988_xfi_pextp_phy0_i2c),
-	/*  @GPIO(5,6) xfi_pextp_phy1_i2c */
-	PINCTRL_PIN_GROUP("xfi_pextp_phy1_i2c", mt7988_xfi_pextp_phy1_i2c),
-	/*  @GPIO(5,6) mdc_mdio0 */
-	PINCTRL_PIN_GROUP("mdc_mdio0", mt7988_mdc_mdio0),
-	/*  @GPIO(7): pcie_wake_n0_0 */
-	PINCTRL_PIN_GROUP("pcie_wake_n0_0", mt7988_pcie_wake_n0_0),
-	/*  @GPIO(8): pcie_clk_req_n0_0 */
-	PINCTRL_PIN_GROUP("pcie_clk_req_n0_0", mt7988_pcie_clk_req_n0_0),
-	/*  @GPIO(9): pcie_wake_n3_0 */
-	PINCTRL_PIN_GROUP("pcie_wake_n3_0", mt7988_pcie_wake_n3_0),
-	/*  @GPIO(10): pcie_clk_req_n3 */
-	PINCTRL_PIN_GROUP("pcie_clk_req_n3", mt7988_pcie_clk_req_n3),
-	/*  @GPIO(10): pcie_clk_req_n0_1 */
-	PINCTRL_PIN_GROUP("pcie_clk_req_n0_1", mt7988_pcie_clk_req_n0_1),
-	/*  @GPIO(7,8) pcie_p0_phy_i2c */
-	PINCTRL_PIN_GROUP("pcie_p0_phy_i2c", mt7988_pcie_p0_phy_i2c),
-	/*  @GPIO(7,8) pcie_p1_phy_i2c */
-	PINCTRL_PIN_GROUP("pcie_p1_phy_i2c", mt7988_pcie_p1_phy_i2c),
-	/*  @GPIO(7,8) pcie_p2_phy_i2c */
-	PINCTRL_PIN_GROUP("pcie_p2_phy_i2c", mt7988_pcie_p2_phy_i2c),
-	/*  @GPIO(9,10) pcie_p3_phy_i2c */
-	PINCTRL_PIN_GROUP("pcie_p3_phy_i2c", mt7988_pcie_p3_phy_i2c),
-	/*  @GPIO(9,10) ckm_phy_i2c */
-	PINCTRL_PIN_GROUP("ckm_phy_i2c", mt7988_ckm_phy_i2c),
-	/*  @GPIO(11): pmic */
-	PINCTRL_PIN_GROUP("pcie_pmic", mt7988_pmic),
-	/*  @GPIO(12): watchdog */
-	PINCTRL_PIN_GROUP("watchdog", mt7988_watchdog),
-	/*  @GPIO(13): pcie_wake_n0_1 */
-	PINCTRL_PIN_GROUP("pcie_wake_n0_1", mt7988_pcie_wake_n0_1),
-	/*  @GPIO(14): pcie_wake_n3_1 */
-	PINCTRL_PIN_GROUP("pcie_wake_n3_1", mt7988_pcie_wake_n3_1),
-	/*  @GPIO(15,16) i2c0_1 */
-	PINCTRL_PIN_GROUP("i2c0_1", mt7988_i2c0_1),
-	/*  @GPIO(15,16) u30_phy_i2c0 */
-	PINCTRL_PIN_GROUP("u30_phy_i2c0", mt7988_u30_phy_i2c0),
-	/*  @GPIO(15,16) u32_phy_i2c0 */
-	PINCTRL_PIN_GROUP("u32_phy_i2c0", mt7988_u32_phy_i2c0),
-	/*  @GPIO(15,16) xfi_phy0_i2c1 */
-	PINCTRL_PIN_GROUP("xfi_phy0_i2c1", mt7988_xfi_phy0_i2c1),
-	/*  @GPIO(15,16) xfi_phy1_i2c1 */
-	PINCTRL_PIN_GROUP("xfi_phy1_i2c1", mt7988_xfi_phy1_i2c1),
-	/*  @GPIO(15,16) xfi_phy_pll_i2c2 */
-	PINCTRL_PIN_GROUP("xfi_phy_pll_i2c2", mt7988_xfi_phy_pll_i2c2),
-	/*  @GPIO(17,18) i2c1_0 */
-	PINCTRL_PIN_GROUP("i2c1_0", mt7988_i2c1_0),
-	/*  @GPIO(17,18) u30_phy_i2c1 */
-	PINCTRL_PIN_GROUP("u30_phy_i2c1", mt7988_u30_phy_i2c1),
-	/*  @GPIO(17,18) u32_phy_i2c1 */
-	PINCTRL_PIN_GROUP("u32_phy_i2c1", mt7988_u32_phy_i2c1),
-	/*  @GPIO(17,18) xfi_phy_pll_i2c3 */
-	PINCTRL_PIN_GROUP("xfi_phy_pll_i2c3", mt7988_xfi_phy_pll_i2c3),
-	/*  @GPIO(17,18) sgmii0_i2c */
-	PINCTRL_PIN_GROUP("sgmii0_i2c", mt7988_sgmii0_i2c),
-	/*  @GPIO(17,18) sgmii1_i2c */
-	PINCTRL_PIN_GROUP("sgmii1_i2c", mt7988_sgmii1_i2c),
-	/*  @GPIO(19): pcie_2l_0_pereset */
-	PINCTRL_PIN_GROUP("pcie_2l_0_pereset", mt7988_pcie_2l_0_pereset),
-	/*  @GPIO(20): pcie_1l_1_pereset */
-	PINCTRL_PIN_GROUP("pcie_1l_1_pereset", mt7988_pcie_1l_1_pereset),
-	/*  @GPIO(21): pwm1 */
-	PINCTRL_PIN_GROUP("pwm1", mt7988_pwm1),
-	/*  @GPIO(22,23) spi0_wp_hold */
-	PINCTRL_PIN_GROUP("spi0_wp_hold", mt7988_spi0_wp_hold),
-	/*  @GPIO(24,25,26,27) spi0 */
-	PINCTRL_PIN_GROUP("spi0", mt7988_spi0),
-	/*  @GPIO(28,29,30,31) spi1 */
-	PINCTRL_PIN_GROUP("spi1", mt7988_spi1),
-	/*  @GPIO(32,33,34,35) spi2 */
-	PINCTRL_PIN_GROUP("spi2", mt7988_spi2),
-	/*  @GPIO(36,37) spi2_wp_hold */
-	PINCTRL_PIN_GROUP("spi2_wp_hold", mt7988_spi2_wp_hold),
-	/*  @GPIO(22,23,24,25,26,27) snfi */
-	PINCTRL_PIN_GROUP("snfi", mt7988_snfi),
-	/*  @GPIO(22,23) tops_uart0_0 */
-	PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart0_0),
-	/*  @GPIO(28,29,30,31) uart2_0 */
-	PINCTRL_PIN_GROUP("uart2_0", mt7988_uart2_0),
-	/*  @GPIO(32,33,34,35) uart1_0 */
-	PINCTRL_PIN_GROUP("uart1_0", mt7988_uart1_0),
-	/*  @GPIO(32,33,34,35) uart2_1 */
-	PINCTRL_PIN_GROUP("uart2_1", mt7988_uart2_1),
-	/*  @GPIO(28) net_wo0_uart_txd_0 */
-	PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0),
-	/*  @GPIO(29) net_wo1_uart_txd_0 */
-	PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0),
-	/*  @GPIO(30) net_wo2_uart_txd_0 */
-	PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0),
-	/*  @GPIO(28,29) tops_uart1_0 */
-	PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart1_0),
-	/*  @GPIO(30,31) tops_uart0_1 */
-	PINCTRL_PIN_GROUP("tops_uart0_1", mt7988_tops_uart0_1),
-	/*  @GPIO(36,37) tops_uart1_1 */
-	PINCTRL_PIN_GROUP("tops_uart1_1", mt7988_tops_uart1_1),
-	/*  @GPIO(32,33,34,35,36) udi */
-	PINCTRL_PIN_GROUP("udi", mt7988_udi),
-	/*  @GPIO(21,28,29,30,31,32,33,34,35,36,37) emmc_45 */
-	PINCTRL_PIN_GROUP("emmc_45", mt7988_emmc_45),
-	/*  @GPIO(32,33,34,35,36,37) sdcard */
-	PINCTRL_PIN_GROUP("sdcard", mt7988_sdcard),
-	/*  @GPIO(38,39,40,41,42,43,44,45,46,47,48,49) emmc_51 */
-	PINCTRL_PIN_GROUP("emmc_51", mt7988_emmc_51),
-	/*  @GPIO(28,29) 2p5g_ext_mdio */
-	PINCTRL_PIN_GROUP("2p5g_ext_mdio", mt7988_2p5g_ext_mdio),
-	/*  @GPIO(30,31) gbe_ext_mdio */
-	PINCTRL_PIN_GROUP("gbe_ext_mdio", mt7988_gbe_ext_mdio),
-	/*  @GPIO(50,51,52,53,54) i2s */
-	PINCTRL_PIN_GROUP("i2s", mt7988_i2s),
-	/*  @GPIO(50,51,52,53) pcm */
-	PINCTRL_PIN_GROUP("pcm", mt7988_pcm),
-	/*  @GPIO(55,56) uart0 */
-	PINCTRL_PIN_GROUP("uart0", mt7988_uart0),
-	/*  @GPIO(55,56) tops_uart0_2 */
-	PINCTRL_PIN_GROUP("tops_uart0_2", mt7988_tops_uart0_2),
-	/*  @GPIO(50,51,52,53) uart2_2 */
-	PINCTRL_PIN_GROUP("uart2_2", mt7988_uart2_2),
-	/*  @GPIO(50,51,52,53,54) wo0_jtag */
-	PINCTRL_PIN_GROUP("wo0_jtag", mt7988_wo0_jtag),
-	/*  @GPIO(50,51,52,53,54) wo1-wo1_jtag */
-	PINCTRL_PIN_GROUP("wo1_jtag", mt7988_wo1_jtag),
-	/*  @GPIO(50,51,52,53,54) wo2_jtag */
-	PINCTRL_PIN_GROUP("wo2_jtag", mt7988_wo2_jtag),
-	/*  @GPIO(57) pwm0 */
-	PINCTRL_PIN_GROUP("pwm0", mt7988_pwm0),
-	/*  @GPIO(58,59,60,61,62) jtag */
-	PINCTRL_PIN_GROUP("jtag", mt7988_jtag),
-	/*  @GPIO(58,59,60,61,62) tops_jtag0_1 */
-	PINCTRL_PIN_GROUP("tops_jtag0_1", mt7988_tops_jtag0_1),
-	/*  @GPIO(58,59,60,61) uart2_3 */
-	PINCTRL_PIN_GROUP("uart2_3", mt7988_uart2_3),
-	/*  @GPIO(58,59,60,61) uart1_1 */
-	PINCTRL_PIN_GROUP("uart1_1", mt7988_uart1_1),
-	/*  @GPIO(58,59,60,61) gbe_led1 */
-	PINCTRL_PIN_GROUP("gbe0_led1", mt7988_gbe0_led1),
-	PINCTRL_PIN_GROUP("gbe1_led1", mt7988_gbe1_led1),
-	PINCTRL_PIN_GROUP("gbe2_led1", mt7988_gbe2_led1),
-	PINCTRL_PIN_GROUP("gbe3_led1", mt7988_gbe3_led1),
-	/*  @GPIO(62) 2p5gbe_led1 */
-	PINCTRL_PIN_GROUP("2p5gbe_led1", mt7988_2p5gbe_led1),
-	/*  @GPIO(64,65,66,67) gbe_led0 */
-	PINCTRL_PIN_GROUP("gbe0_led0", mt7988_gbe0_led0),
-	PINCTRL_PIN_GROUP("gbe1_led0", mt7988_gbe1_led0),
-	PINCTRL_PIN_GROUP("gbe2_led0", mt7988_gbe2_led0),
-	PINCTRL_PIN_GROUP("gbe3_led0", mt7988_gbe3_led0),
-	/*  @GPIO(68) 2p5gbe_led0 */
-	PINCTRL_PIN_GROUP("2p5gbe_led0", mt7988_2p5gbe_led0),
-	/*  @GPIO(63) drv_vbus_p1 */
-	PINCTRL_PIN_GROUP("drv_vbus_p1", mt7988_drv_vbus_p1),
-	/*  @GPIO(63) pcie_clk_req_n2_1 */
-	PINCTRL_PIN_GROUP("pcie_clk_req_n2_1", mt7988_pcie_clk_req_n2_1),
-	/*  @GPIO(69, 70) mdc_mdio1 */
-	PINCTRL_PIN_GROUP("mdc_mdio1", mt7988_mdc_mdio1),
-	/*  @GPIO(69, 70) i2c1_2 */
-	PINCTRL_PIN_GROUP("i2c1_2", mt7988_i2c1_2),
-	/*  @GPIO(69) pwm6 */
-	PINCTRL_PIN_GROUP("pwm6", mt7988_pwm6),
-	/*  @GPIO(70) pwm7 */
-	PINCTRL_PIN_GROUP("pwm7", mt7988_pwm7),
-	/*  @GPIO(69,70) i2c2_0 */
-	PINCTRL_PIN_GROUP("i2c2_0", mt7988_i2c2_0),
-	/*  @GPIO(71,72) i2c2_1 */
-	PINCTRL_PIN_GROUP("i2c2_1", mt7988_i2c2_1),
-	/*  @GPIO(73) pcie_2l_1_pereset */
-	PINCTRL_PIN_GROUP("pcie_2l_1_pereset", mt7988_pcie_2l_1_pereset),
-	/*  @GPIO(74) pcie_1l_0_pereset */
-	PINCTRL_PIN_GROUP("pcie_1l_0_pereset", mt7988_pcie_1l_0_pereset),
-	/*  @GPIO(75) pcie_wake_n1_0 */
-	PINCTRL_PIN_GROUP("pcie_wake_n1_0", mt7988_pcie_wake_n1_0),
-	/*  @GPIO(76) pcie_clk_req_n1 */
-	PINCTRL_PIN_GROUP("pcie_clk_req_n1", mt7988_pcie_clk_req_n1),
-	/*  @GPIO(77) pcie_wake_n2_0 */
-	PINCTRL_PIN_GROUP("pcie_wake_n2_0", mt7988_pcie_wake_n2_0),
-	/*  @GPIO(78) pcie_clk_req_n2_0 */
-	PINCTRL_PIN_GROUP("pcie_clk_req_n2_0", mt7988_pcie_clk_req_n2_0),
-	/*  @GPIO(79) drv_vbus */
-	PINCTRL_PIN_GROUP("drv_vbus", mt7988_drv_vbus),
-	/*  @GPIO(79) pcie_wake_n2_1 */
-	PINCTRL_PIN_GROUP("pcie_wake_n2_1", mt7988_pcie_wake_n2_1),
-	/*  @GPIO(80,81,82,83) uart1_2 */
-	PINCTRL_PIN_GROUP("uart1_2", mt7988_uart1_2),
-	/*  @GPIO(80) pwm2 */
-	PINCTRL_PIN_GROUP("pwm2", mt7988_pwm2),
-	/*  @GPIO(81) pwm3 */
-	PINCTRL_PIN_GROUP("pwm3", mt7988_pwm3),
-	/*  @GPIO(82) pwm4 */
-	PINCTRL_PIN_GROUP("pwm4", mt7988_pwm4),
-	/*  @GPIO(83) pwm5 */
-	PINCTRL_PIN_GROUP("pwm5", mt7988_pwm5),
-	/*  @GPIO(80) net_wo0_uart_txd_0 */
-	PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0),
-	/*  @GPIO(81) net_wo1_uart_txd_0 */
-	PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0),
-	/*  @GPIO(82) net_wo2_uart_txd_0 */
-	PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0),
-	/*  @GPIO(80,81) tops_uart1_2 */
-	PINCTRL_PIN_GROUP("tops_uart1_2", mt7988_tops_uart1_2),
-	/*  @GPIO(80) net_wo0_uart_txd_1 */
-	PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7988_net_wo0_uart_txd_1),
-	/*  @GPIO(81) net_wo1_uart_txd_1 */
-	PINCTRL_PIN_GROUP("net_wo1_uart_txd_1", mt7988_net_wo1_uart_txd_1),
-	/*  @GPIO(82) net_wo2_uart_txd_1 */
-	PINCTRL_PIN_GROUP("net_wo2_uart_txd_1", mt7988_net_wo2_uart_txd_1),
-};
-
-/* Joint those groups owning the same capability in user point of view which
- * allows that people tend to use through the device tree.
- */
-static const char *mt7988_jtag_groups[] = {
-	"tops_jtag0_0", "wo0_jtag", "wo1_jtag",
-	"wo2_jtag",	"jtag",	    "tops_jtag0_1",
-};
-static const char *mt7988_int_usxgmii_groups[] = {
-	"int_usxgmii",
-};
-static const char *mt7988_pwm_groups[] = {
-	"pwm0", "pwm1", "pwm2", "pwm3", "pwm4",	"pwm5",	"pwm6", "pwm7"
-};
-static const char *mt7988_dfd_groups[] = {
-	"dfd",
-};
-static const char *mt7988_i2c_groups[] = {
-	"xfi_phy0_i2c0",
-	"xfi_phy1_i2c0",
-	"xfi_phy_pll_i2c0",
-	"xfi_phy_pll_i2c1",
-	"i2c0_0",
-	"i2c1_sfp",
-	"xfi_pextp_phy0_i2c",
-	"xfi_pextp_phy1_i2c",
-	"i2c0_1",
-	"u30_phy_i2c0",
-	"u32_phy_i2c0",
-	"xfi_phy0_i2c1",
-	"xfi_phy1_i2c1",
-	"xfi_phy_pll_i2c2",
-	"i2c1_0",
-	"u30_phy_i2c1",
-	"u32_phy_i2c1",
-	"xfi_phy_pll_i2c3",
-	"sgmii0_i2c",
-	"sgmii1_i2c",
-	"i2c1_2",
-	"i2c2_0",
-	"i2c2_1",
-};
-static const char *mt7988_ethernet_groups[] = {
-	"mdc_mdio0",
-	"2p5g_ext_mdio",
-	"gbe_ext_mdio",
-	"mdc_mdio1",
-};
-static const char *mt7988_pcie_groups[] = {
-	"pcie_wake_n0_0",    "pcie_clk_req_n0_0", "pcie_wake_n3_0",
-	"pcie_clk_req_n3",   "pcie_p0_phy_i2c",	  "pcie_p1_phy_i2c",
-	"pcie_p3_phy_i2c",   "pcie_p2_phy_i2c",	  "ckm_phy_i2c",
-	"pcie_wake_n0_1",    "pcie_wake_n3_1",	  "pcie_2l_0_pereset",
-	"pcie_1l_1_pereset", "pcie_clk_req_n2_1", "pcie_2l_1_pereset",
-	"pcie_1l_0_pereset", "pcie_wake_n1_0",	  "pcie_clk_req_n1",
-	"pcie_wake_n2_0",    "pcie_clk_req_n2_0", "pcie_wake_n2_1",
-	"pcie_clk_req_n0_1"
-};
-static const char *mt7988_pmic_groups[] = {
-	"pmic",
-};
-static const char *mt7988_wdt_groups[] = {
-	"watchdog",
-};
-static const char *mt7988_spi_groups[] = {
-	"spi0", "spi0_wp_hold", "spi1", "spi2", "spi2_wp_hold",
-};
-static const char *mt7988_flash_groups[] = { "emmc_45", "sdcard", "snfi",
-						    "emmc_51" };
-static const char *mt7988_uart_groups[] = {
-	"uart2",
-	"tops_uart0_0",
-	"uart2_0",
-	"uart1_0",
-	"uart2_1",
-	"net_wo0_uart_txd_0",
-	"net_wo1_uart_txd_0",
-	"net_wo2_uart_txd_0",
-	"tops_uart1_0",
-	"ops_uart0_1",
-	"ops_uart1_1",
-	"uart0",
-	"tops_uart0_2",
-	"uart1_1",
-	"uart2_3",
-	"uart1_2",
-	"tops_uart1_2",
-	"net_wo0_uart_txd_1",
-	"net_wo1_uart_txd_1",
-	"net_wo2_uart_txd_1",
-};
-static const char *mt7988_udi_groups[] = {
-	"udi",
-};
-static const char *mt7988_audio_groups[] = {
-	"i2s", "pcm",
-};
-static const char *mt7988_led_groups[] = {
-	"gbe0_led1", "gbe1_led1", "gbe2_led1", "gbe3_led1", "2p5gbe_led1",
-	"gbe0_led0", "gbe1_led0", "gbe2_led0", "gbe3_led0", "2p5gbe_led0",
-	"wf5g_led0",   "wf5g_led1",
-};
-static const char *mt7988_usb_groups[] = {
-	"drv_vbus",
-	"drv_vbus_p1",
-};
-
-static const struct function_desc mt7988_functions[] = {
-	{ "audio", mt7988_audio_groups, ARRAY_SIZE(mt7988_audio_groups) },
-	{ "jtag", mt7988_jtag_groups, ARRAY_SIZE(mt7988_jtag_groups) },
-	{ "int_usxgmii", mt7988_int_usxgmii_groups,
-	  ARRAY_SIZE(mt7988_int_usxgmii_groups) },
-	{ "pwm", mt7988_pwm_groups, ARRAY_SIZE(mt7988_pwm_groups) },
-	{ "dfd", mt7988_dfd_groups, ARRAY_SIZE(mt7988_dfd_groups) },
-	{ "i2c", mt7988_i2c_groups, ARRAY_SIZE(mt7988_i2c_groups) },
-	{ "eth", mt7988_ethernet_groups, ARRAY_SIZE(mt7988_ethernet_groups) },
-	{ "pcie", mt7988_pcie_groups, ARRAY_SIZE(mt7988_pcie_groups) },
-	{ "pmic", mt7988_pmic_groups, ARRAY_SIZE(mt7988_pmic_groups) },
-	{ "watchdog", mt7988_wdt_groups, ARRAY_SIZE(mt7988_wdt_groups) },
-	{ "spi", mt7988_spi_groups, ARRAY_SIZE(mt7988_spi_groups) },
-	{ "flash", mt7988_flash_groups, ARRAY_SIZE(mt7988_flash_groups) },
-	{ "uart", mt7988_uart_groups, ARRAY_SIZE(mt7988_uart_groups) },
-	{ "udi", mt7988_udi_groups, ARRAY_SIZE(mt7988_udi_groups) },
-	{ "usb", mt7988_usb_groups, ARRAY_SIZE(mt7988_usb_groups) },
-	{ "led", mt7988_led_groups, ARRAY_SIZE(mt7988_led_groups) },
-};
-
-static const struct mtk_eint_hw mt7988_eint_hw = {
-	.port_mask = 7,
-	.ports = 7,
-	.ap_num = ARRAY_SIZE(mt7988_pins),
-	.db_cnt = 16,
-};
-
-static const char *mt7988_pinctrl_register_base_names[] = {
-	"gpio_base",	 "iocfg_tr_base", "iocfg_br_base",
-	"iocfg_rb_base", "iocfg_lb_base", "iocfg_tl_base",
-};
-
-static struct mtk_pin_soc mt7988_data = {
-	.reg_cal = mt7988_reg_cals,
-	.pins = mt7988_pins,
-	.npins = ARRAY_SIZE(mt7988_pins),
-	.grps = mt7988_groups,
-	.ngrps = ARRAY_SIZE(mt7988_groups),
-	.funcs = mt7988_functions,
-	.nfuncs = ARRAY_SIZE(mt7988_functions),
-	.eint_hw = &mt7988_eint_hw,
-	.gpio_m = 0,
-	.ies_present = false,
-	.base_names = mt7988_pinctrl_register_base_names,
-	.nbase_names = ARRAY_SIZE(mt7988_pinctrl_register_base_names),
-	.bias_disable_set = mtk_pinconf_bias_disable_set,
-	.bias_disable_get = mtk_pinconf_bias_disable_get,
-	.bias_set = mtk_pinconf_bias_set,
-	.bias_get = mtk_pinconf_bias_get,
-	.drive_set = mtk_pinconf_drive_set_rev1,
-	.drive_get = mtk_pinconf_drive_get_rev1,
-	.adv_pull_get = mtk_pinconf_adv_pull_get,
-	.adv_pull_set = mtk_pinconf_adv_pull_set,
-};
-
-static const struct of_device_id mt7988_pinctrl_of_match[] = {
-	{
-		.compatible = "mediatek,mt7988-pinctrl",
-	},
-	{}
-};
-
-static int mt7988_pinctrl_probe(struct platform_device *pdev)
-{
-	return mtk_moore_pinctrl_probe(pdev, &mt7988_data);
-}
-
-static struct platform_driver mt7988_pinctrl_driver = {
-	.driver = {
-		.name = "mt7988-pinctrl",
-		.of_match_table = mt7988_pinctrl_of_match,
-	},
-	.probe = mt7988_pinctrl_probe,
-};
-
-static int __init mt7988_pinctrl_init(void)
-{
-	return platform_driver_register(&mt7988_pinctrl_driver);
-}
-arch_initcall(mt7988_pinctrl_init);
diff --git a/target/linux/mediatek/files-5.15/include/dt-bindings/clock/mediatek,mt7981-clk.h b/target/linux/mediatek/files-5.15/include/dt-bindings/clock/mediatek,mt7981-clk.h
deleted file mode 100644
index 192f8cefb589f4..00000000000000
--- a/target/linux/mediatek/files-5.15/include/dt-bindings/clock/mediatek,mt7981-clk.h
+++ /dev/null
@@ -1,215 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
-/*
- * Copyright (c) 2021 MediaTek Inc.
- * Author: Wenzhen.Yu <wenzhen.yu@mediatek.com>
- * Author: Jianhui Zhao <zhaojh329@gmail.com>
- * Author: Daniel Golle <daniel@makrotopia.org>
- */
-
-#ifndef _DT_BINDINGS_CLK_MT7981_H
-#define _DT_BINDINGS_CLK_MT7981_H
-
-/* TOPCKGEN */
-#define CLK_TOP_CB_CKSQ_40M		0
-#define CLK_TOP_CB_M_416M		1
-#define CLK_TOP_CB_M_D2			2
-#define CLK_TOP_CB_M_D3			3
-#define CLK_TOP_M_D3_D2			4
-#define CLK_TOP_CB_M_D4			5
-#define CLK_TOP_CB_M_D8			6
-#define CLK_TOP_M_D8_D2			7
-#define CLK_TOP_CB_MM_720M		8
-#define CLK_TOP_CB_MM_D2		9
-#define CLK_TOP_CB_MM_D3		10
-#define CLK_TOP_CB_MM_D3_D5		11
-#define CLK_TOP_CB_MM_D4		12
-#define CLK_TOP_CB_MM_D6		13
-#define CLK_TOP_MM_D6_D2		14
-#define CLK_TOP_CB_MM_D8		15
-#define CLK_TOP_CB_APLL2_196M		16
-#define CLK_TOP_APLL2_D2		17
-#define CLK_TOP_APLL2_D4		18
-#define CLK_TOP_NET1_2500M		19
-#define CLK_TOP_CB_NET1_D4		20
-#define CLK_TOP_CB_NET1_D5		21
-#define CLK_TOP_NET1_D5_D2		22
-#define CLK_TOP_NET1_D5_D4		23
-#define CLK_TOP_CB_NET1_D8		24
-#define CLK_TOP_NET1_D8_D2		25
-#define CLK_TOP_NET1_D8_D4		26
-#define CLK_TOP_CB_NET2_800M		27
-#define CLK_TOP_CB_NET2_D2		28
-#define CLK_TOP_CB_NET2_D4		29
-#define CLK_TOP_NET2_D4_D2		30
-#define CLK_TOP_NET2_D4_D4		31
-#define CLK_TOP_CB_NET2_D6		32
-#define CLK_TOP_CB_WEDMCU_208M		33
-#define CLK_TOP_CB_SGM_325M		34
-#define CLK_TOP_CKSQ_40M_D2		35
-#define CLK_TOP_CB_RTC_32K		36
-#define CLK_TOP_CB_RTC_32P7K		37
-#define CLK_TOP_USB_TX250M		38
-#define CLK_TOP_FAUD			39
-#define CLK_TOP_NFI1X			40
-#define CLK_TOP_USB_EQ_RX250M		41
-#define CLK_TOP_USB_CDR_CK		42
-#define CLK_TOP_USB_LN0_CK		43
-#define CLK_TOP_SPINFI_BCK		44
-#define CLK_TOP_SPI			45
-#define CLK_TOP_SPIM_MST		46
-#define CLK_TOP_UART_BCK		47
-#define CLK_TOP_PWM_BCK			48
-#define CLK_TOP_I2C_BCK			49
-#define CLK_TOP_PEXTP_TL		50
-#define CLK_TOP_EMMC_208M		51
-#define CLK_TOP_EMMC_400M		52
-#define CLK_TOP_DRAMC_REF		53
-#define CLK_TOP_DRAMC_MD32		54
-#define CLK_TOP_SYSAXI			55
-#define CLK_TOP_SYSAPB			56
-#define CLK_TOP_ARM_DB_MAIN		57
-#define CLK_TOP_AP2CNN_HOST		58
-#define CLK_TOP_NETSYS			59
-#define CLK_TOP_NETSYS_500M		60
-#define CLK_TOP_NETSYS_WED_MCU		61
-#define CLK_TOP_NETSYS_2X		62
-#define CLK_TOP_SGM_325M		63
-#define CLK_TOP_SGM_REG			64
-#define CLK_TOP_F26M			65
-#define CLK_TOP_EIP97B			66
-#define CLK_TOP_USB3_PHY		67
-#define CLK_TOP_AUD			68
-#define CLK_TOP_A1SYS			69
-#define CLK_TOP_AUD_L			70
-#define CLK_TOP_A_TUNER			71
-#define CLK_TOP_U2U3_REF		72
-#define CLK_TOP_U2U3_SYS		73
-#define CLK_TOP_U2U3_XHCI		74
-#define CLK_TOP_USB_FRMCNT		75
-#define CLK_TOP_NFI1X_SEL		76
-#define CLK_TOP_SPINFI_SEL		77
-#define CLK_TOP_SPI_SEL			78
-#define CLK_TOP_SPIM_MST_SEL		79
-#define CLK_TOP_UART_SEL		80
-#define CLK_TOP_PWM_SEL			81
-#define CLK_TOP_I2C_SEL			82
-#define CLK_TOP_PEXTP_TL_SEL		83
-#define CLK_TOP_EMMC_208M_SEL		84
-#define CLK_TOP_EMMC_400M_SEL		85
-#define CLK_TOP_F26M_SEL		86
-#define CLK_TOP_DRAMC_SEL		87
-#define CLK_TOP_DRAMC_MD32_SEL		88
-#define CLK_TOP_SYSAXI_SEL		89
-#define CLK_TOP_SYSAPB_SEL		90
-#define CLK_TOP_ARM_DB_MAIN_SEL		91
-#define CLK_TOP_AP2CNN_HOST_SEL		92
-#define CLK_TOP_NETSYS_SEL		93
-#define CLK_TOP_NETSYS_500M_SEL		94
-#define CLK_TOP_NETSYS_MCU_SEL		95
-#define CLK_TOP_NETSYS_2X_SEL		96
-#define CLK_TOP_SGM_325M_SEL		97
-#define CLK_TOP_SGM_REG_SEL		98
-#define CLK_TOP_EIP97B_SEL		99
-#define CLK_TOP_USB3_PHY_SEL		100
-#define CLK_TOP_AUD_SEL			101
-#define CLK_TOP_A1SYS_SEL		102
-#define CLK_TOP_AUD_L_SEL		103
-#define CLK_TOP_A_TUNER_SEL		104
-#define CLK_TOP_U2U3_SEL		105
-#define CLK_TOP_U2U3_SYS_SEL		106
-#define CLK_TOP_U2U3_XHCI_SEL		107
-#define CLK_TOP_USB_FRMCNT_SEL		108
-#define CLK_TOP_AUD_I2S_M		109
-
-/* INFRACFG */
-#define CLK_INFRA_66M_MCK		0
-#define CLK_INFRA_UART0_SEL		1
-#define CLK_INFRA_UART1_SEL		2
-#define CLK_INFRA_UART2_SEL		3
-#define CLK_INFRA_SPI0_SEL		4
-#define CLK_INFRA_SPI1_SEL		5
-#define CLK_INFRA_SPI2_SEL		6
-#define CLK_INFRA_PWM1_SEL		7
-#define CLK_INFRA_PWM2_SEL		8
-#define CLK_INFRA_PWM3_SEL		9
-#define CLK_INFRA_PWM_BSEL		10
-#define CLK_INFRA_PCIE_SEL		11
-#define CLK_INFRA_GPT_STA		12
-#define CLK_INFRA_PWM_HCK		13
-#define CLK_INFRA_PWM_STA		14
-#define CLK_INFRA_PWM1_CK		15
-#define CLK_INFRA_PWM2_CK		16
-#define CLK_INFRA_PWM3_CK		17
-#define CLK_INFRA_CQ_DMA_CK		18
-#define CLK_INFRA_AUD_BUS_CK		19
-#define CLK_INFRA_AUD_26M_CK		20
-#define CLK_INFRA_AUD_L_CK		21
-#define CLK_INFRA_AUD_AUD_CK		22
-#define CLK_INFRA_AUD_EG2_CK		23
-#define CLK_INFRA_DRAMC_26M_CK		24
-#define CLK_INFRA_DBG_CK		25
-#define CLK_INFRA_AP_DMA_CK		26
-#define CLK_INFRA_SEJ_CK		27
-#define CLK_INFRA_SEJ_13M_CK		28
-#define CLK_INFRA_THERM_CK		29
-#define CLK_INFRA_I2C0_CK		30
-#define CLK_INFRA_UART0_CK		31
-#define CLK_INFRA_UART1_CK		32
-#define CLK_INFRA_UART2_CK		33
-#define CLK_INFRA_SPI2_CK		34
-#define CLK_INFRA_SPI2_HCK_CK		35
-#define CLK_INFRA_NFI1_CK		36
-#define CLK_INFRA_SPINFI1_CK		37
-#define CLK_INFRA_NFI_HCK_CK		38
-#define CLK_INFRA_SPI0_CK		39
-#define CLK_INFRA_SPI1_CK		40
-#define CLK_INFRA_SPI0_HCK_CK		41
-#define CLK_INFRA_SPI1_HCK_CK		42
-#define CLK_INFRA_FRTC_CK		43
-#define CLK_INFRA_MSDC_CK		44
-#define CLK_INFRA_MSDC_HCK_CK		45
-#define CLK_INFRA_MSDC_133M_CK		46
-#define CLK_INFRA_MSDC_66M_CK		47
-#define CLK_INFRA_ADC_26M_CK		48
-#define CLK_INFRA_ADC_FRC_CK		49
-#define CLK_INFRA_FBIST2FPC_CK		50
-#define CLK_INFRA_I2C_MCK_CK		51
-#define CLK_INFRA_I2C_PCK_CK		52
-#define CLK_INFRA_IUSB_133_CK		53
-#define CLK_INFRA_IUSB_66M_CK		54
-#define CLK_INFRA_IUSB_SYS_CK		55
-#define CLK_INFRA_IUSB_CK		56
-#define CLK_INFRA_IPCIE_CK		57
-#define CLK_INFRA_IPCIE_PIPE_CK		58
-#define CLK_INFRA_IPCIER_CK		59
-#define CLK_INFRA_IPCIEB_CK		60
-
-/* APMIXEDSYS */
-#define CLK_APMIXED_ARMPLL		0
-#define CLK_APMIXED_NET2PLL		1
-#define CLK_APMIXED_MMPLL		2
-#define CLK_APMIXED_SGMPLL		3
-#define CLK_APMIXED_WEDMCUPLL		4
-#define CLK_APMIXED_NET1PLL		5
-#define CLK_APMIXED_MPLL		6
-#define CLK_APMIXED_APLL2		7
-
-/* SGMIISYS_0 */
-#define CLK_SGM0_TX_EN			0
-#define CLK_SGM0_RX_EN			1
-#define CLK_SGM0_CK0_EN			2
-#define CLK_SGM0_CDR_CK0_EN		3
-
-/* SGMIISYS_1 */
-#define CLK_SGM1_TX_EN			0
-#define CLK_SGM1_RX_EN			1
-#define CLK_SGM1_CK1_EN			2
-#define CLK_SGM1_CDR_CK1_EN		3
-
-/* ETHSYS */
-#define CLK_ETH_FE_EN			0
-#define CLK_ETH_GP2_EN			1
-#define CLK_ETH_GP1_EN			2
-#define CLK_ETH_WOCPU0_EN		3
-
-#endif /* _DT_BINDINGS_CLK_MT7981_H */
diff --git a/target/linux/mediatek/files-5.15/include/dt-bindings/clock/mediatek,mt7988-clk.h b/target/linux/mediatek/files-5.15/include/dt-bindings/clock/mediatek,mt7988-clk.h
deleted file mode 100644
index 77cfea4a8eaf6a..00000000000000
--- a/target/linux/mediatek/files-5.15/include/dt-bindings/clock/mediatek,mt7988-clk.h
+++ /dev/null
@@ -1,276 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
-/*
- * Copyright (c) 2023 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
- */
-
-#ifndef _DT_BINDINGS_CLK_MT7988_H
-#define _DT_BINDINGS_CLK_MT7988_H
-
-/* APMIXEDSYS */
-
-#define CLK_APMIXED_NETSYSPLL  0
-#define CLK_APMIXED_MPLL       1
-#define CLK_APMIXED_MMPLL      2
-#define CLK_APMIXED_APLL2      3
-#define CLK_APMIXED_NET1PLL    4
-#define CLK_APMIXED_NET2PLL    5
-#define CLK_APMIXED_WEDMCUPLL  6
-#define CLK_APMIXED_SGMPLL     7
-#define CLK_APMIXED_ARM_B      8
-#define CLK_APMIXED_CCIPLL2_B  9
-#define CLK_APMIXED_USXGMIIPLL 10
-#define CLK_APMIXED_MSDCPLL    11
-
-/* TOPCKGEN */
-
-#define CLK_TOP_XTAL		       0
-#define CLK_TOP_XTAL_D2		       1
-#define CLK_TOP_RTC_32K		       2
-#define CLK_TOP_RTC_32P7K	       3
-#define CLK_TOP_MPLL_D2		       4
-#define CLK_TOP_MPLL_D3_D2	       5
-#define CLK_TOP_MPLL_D4		       6
-#define CLK_TOP_MPLL_D8		       7
-#define CLK_TOP_MPLL_D8_D2	       8
-#define CLK_TOP_MMPLL_D2	       9
-#define CLK_TOP_MMPLL_D3_D5	       10
-#define CLK_TOP_MMPLL_D4	       11
-#define CLK_TOP_MMPLL_D6_D2	       12
-#define CLK_TOP_MMPLL_D8	       13
-#define CLK_TOP_APLL2_D4	       14
-#define CLK_TOP_NET1PLL_D4	       15
-#define CLK_TOP_NET1PLL_D5	       16
-#define CLK_TOP_NET1PLL_D5_D2	       17
-#define CLK_TOP_NET1PLL_D5_D4	       18
-#define CLK_TOP_NET1PLL_D8	       19
-#define CLK_TOP_NET1PLL_D8_D2	       20
-#define CLK_TOP_NET1PLL_D8_D4	       21
-#define CLK_TOP_NET1PLL_D8_D8	       22
-#define CLK_TOP_NET1PLL_D8_D16	       23
-#define CLK_TOP_NET2PLL_D2	       24
-#define CLK_TOP_NET2PLL_D4	       25
-#define CLK_TOP_NET2PLL_D4_D4	       26
-#define CLK_TOP_NET2PLL_D4_D8	       27
-#define CLK_TOP_NET2PLL_D6	       28
-#define CLK_TOP_NET2PLL_D8	       29
-#define CLK_TOP_NETSYS_SEL	       30
-#define CLK_TOP_NETSYS_500M_SEL	       31
-#define CLK_TOP_NETSYS_2X_SEL	       32
-#define CLK_TOP_NETSYS_GSW_SEL	       33
-#define CLK_TOP_ETH_GMII_SEL	       34
-#define CLK_TOP_NETSYS_MCU_SEL	       35
-#define CLK_TOP_NETSYS_PAO_2X_SEL      36
-#define CLK_TOP_EIP197_SEL	       37
-#define CLK_TOP_AXI_INFRA_SEL	       38
-#define CLK_TOP_UART_SEL	       39
-#define CLK_TOP_EMMC_250M_SEL	       40
-#define CLK_TOP_EMMC_400M_SEL	       41
-#define CLK_TOP_SPI_SEL		       42
-#define CLK_TOP_SPIM_MST_SEL	       43
-#define CLK_TOP_NFI1X_SEL	       44
-#define CLK_TOP_SPINFI_SEL	       45
-#define CLK_TOP_PWM_SEL		       46
-#define CLK_TOP_I2C_SEL		       47
-#define CLK_TOP_PCIE_MBIST_250M_SEL    48
-#define CLK_TOP_PEXTP_TL_SEL	       49
-#define CLK_TOP_PEXTP_TL_P1_SEL	       50
-#define CLK_TOP_PEXTP_TL_P2_SEL	       51
-#define CLK_TOP_PEXTP_TL_P3_SEL	       52
-#define CLK_TOP_USB_SYS_SEL	       53
-#define CLK_TOP_USB_SYS_P1_SEL	       54
-#define CLK_TOP_USB_XHCI_SEL	       55
-#define CLK_TOP_USB_XHCI_P1_SEL	       56
-#define CLK_TOP_USB_FRMCNT_SEL	       57
-#define CLK_TOP_USB_FRMCNT_P1_SEL      58
-#define CLK_TOP_AUD_SEL		       59
-#define CLK_TOP_A1SYS_SEL	       60
-#define CLK_TOP_AUD_L_SEL	       61
-#define CLK_TOP_A_TUNER_SEL	       62
-#define CLK_TOP_SSPXTP_SEL	       63
-#define CLK_TOP_USB_PHY_SEL	       64
-#define CLK_TOP_USXGMII_SBUS_0_SEL     65
-#define CLK_TOP_USXGMII_SBUS_1_SEL     66
-#define CLK_TOP_SGM_0_SEL	       67
-#define CLK_TOP_SGM_SBUS_0_SEL	       68
-#define CLK_TOP_SGM_1_SEL	       69
-#define CLK_TOP_SGM_SBUS_1_SEL	       70
-#define CLK_TOP_XFI_PHY_0_XTAL_SEL     71
-#define CLK_TOP_XFI_PHY_1_XTAL_SEL     72
-#define CLK_TOP_SYSAXI_SEL	       73
-#define CLK_TOP_SYSAPB_SEL	       74
-#define CLK_TOP_ETH_REFCK_50M_SEL      75
-#define CLK_TOP_ETH_SYS_200M_SEL       76
-#define CLK_TOP_ETH_SYS_SEL	       77
-#define CLK_TOP_ETH_XGMII_SEL	       78
-#define CLK_TOP_BUS_TOPS_SEL	       79
-#define CLK_TOP_NPU_TOPS_SEL	       80
-#define CLK_TOP_DRAMC_SEL	       81
-#define CLK_TOP_DRAMC_MD32_SEL	       82
-#define CLK_TOP_INFRA_F26M_SEL	       83
-#define CLK_TOP_PEXTP_P0_SEL	       84
-#define CLK_TOP_PEXTP_P1_SEL	       85
-#define CLK_TOP_PEXTP_P2_SEL	       86
-#define CLK_TOP_PEXTP_P3_SEL	       87
-#define CLK_TOP_DA_XTP_GLB_P0_SEL      88
-#define CLK_TOP_DA_XTP_GLB_P1_SEL      89
-#define CLK_TOP_DA_XTP_GLB_P2_SEL      90
-#define CLK_TOP_DA_XTP_GLB_P3_SEL      91
-#define CLK_TOP_CKM_SEL		       92
-#define CLK_TOP_DA_SEL		       93
-#define CLK_TOP_PEXTP_SEL	       94
-#define CLK_TOP_TOPS_P2_26M_SEL	       95
-#define CLK_TOP_MCUSYS_BACKUP_625M_SEL 96
-#define CLK_TOP_NETSYS_SYNC_250M_SEL   97
-#define CLK_TOP_MACSEC_SEL	       98
-#define CLK_TOP_NETSYS_TOPS_400M_SEL   99
-#define CLK_TOP_NETSYS_PPEFB_250M_SEL  100
-#define CLK_TOP_NETSYS_WARP_SEL	       101
-#define CLK_TOP_ETH_MII_SEL	       102
-#define CLK_TOP_NPU_SEL		       103
-#define CLK_TOP_AUD_I2S_M	       104
-
-/* MCUSYS */
-
-#define CLK_MCU_BUS_DIV_SEL 0
-#define CLK_MCU_ARM_DIV_SEL 1
-
-/* INFRACFG_AO */
-
-#define CLK_INFRA_MUX_UART0_SEL		 0
-#define CLK_INFRA_MUX_UART1_SEL		 1
-#define CLK_INFRA_MUX_UART2_SEL		 2
-#define CLK_INFRA_MUX_SPI0_SEL		 3
-#define CLK_INFRA_MUX_SPI1_SEL		 4
-#define CLK_INFRA_MUX_SPI2_SEL		 5
-#define CLK_INFRA_PWM_SEL		 6
-#define CLK_INFRA_PWM_CK1_SEL		 7
-#define CLK_INFRA_PWM_CK2_SEL		 8
-#define CLK_INFRA_PWM_CK3_SEL		 9
-#define CLK_INFRA_PWM_CK4_SEL		 10
-#define CLK_INFRA_PWM_CK5_SEL		 11
-#define CLK_INFRA_PWM_CK6_SEL		 12
-#define CLK_INFRA_PWM_CK7_SEL		 13
-#define CLK_INFRA_PWM_CK8_SEL		 14
-#define CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 15
-#define CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 16
-#define CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 17
-#define CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 18
-
-/* INFRACFG */
-
-#define CLK_INFRA_PCIE_PERI_26M_CK_P0 19
-#define CLK_INFRA_PCIE_PERI_26M_CK_P1 20
-#define CLK_INFRA_PCIE_PERI_26M_CK_P2 21
-#define CLK_INFRA_PCIE_PERI_26M_CK_P3 22
-#define CLK_INFRA_66M_GPT_BCK	      23
-#define CLK_INFRA_66M_PWM_HCK	      24
-#define CLK_INFRA_66M_PWM_BCK	      25
-#define CLK_INFRA_66M_PWM_CK1	      26
-#define CLK_INFRA_66M_PWM_CK2	      27
-#define CLK_INFRA_66M_PWM_CK3	      28
-#define CLK_INFRA_66M_PWM_CK4	      29
-#define CLK_INFRA_66M_PWM_CK5	      30
-#define CLK_INFRA_66M_PWM_CK6	      31
-#define CLK_INFRA_66M_PWM_CK7	      32
-#define CLK_INFRA_66M_PWM_CK8	      33
-#define CLK_INFRA_133M_CQDMA_BCK      34
-#define CLK_INFRA_66M_AUD_SLV_BCK     35
-#define CLK_INFRA_AUD_26M	      36
-#define CLK_INFRA_AUD_L		      37
-#define CLK_INFRA_AUD_AUD	      38
-#define CLK_INFRA_AUD_EG2	      39
-#define CLK_INFRA_DRAMC_F26M	      40
-#define CLK_INFRA_133M_DBG_ACKM	      41
-#define CLK_INFRA_66M_AP_DMA_BCK      42
-#define CLK_INFRA_66M_SEJ_BCK	      43
-#define CLK_INFRA_PRE_CK_SEJ_F13M     44
-#define CLK_INFRA_26M_THERM_SYSTEM    45
-#define CLK_INFRA_I2C_BCK	      46
-#define CLK_INFRA_52M_UART0_CK	      47
-#define CLK_INFRA_52M_UART1_CK	      48
-#define CLK_INFRA_52M_UART2_CK	      49
-#define CLK_INFRA_NFI		      50
-#define CLK_INFRA_SPINFI	      51
-#define CLK_INFRA_66M_NFI_HCK	      52
-#define CLK_INFRA_104M_SPI0	      53
-#define CLK_INFRA_104M_SPI1	      54
-#define CLK_INFRA_104M_SPI2_BCK	      55
-#define CLK_INFRA_66M_SPI0_HCK	      56
-#define CLK_INFRA_66M_SPI1_HCK	      57
-#define CLK_INFRA_66M_SPI2_HCK	      58
-#define CLK_INFRA_66M_FLASHIF_AXI     59
-#define CLK_INFRA_RTC		      60
-#define CLK_INFRA_26M_ADC_BCK	      61
-#define CLK_INFRA_RC_ADC	      62
-#define CLK_INFRA_MSDC400	      63
-#define CLK_INFRA_MSDC2_HCK	      64
-#define CLK_INFRA_133M_MSDC_0_HCK     65
-#define CLK_INFRA_66M_MSDC_0_HCK      66
-#define CLK_INFRA_133M_CPUM_BCK	      67
-#define CLK_INFRA_BIST2FPC	      68
-#define CLK_INFRA_I2C_X16W_MCK_CK_P1  69
-#define CLK_INFRA_I2C_X16W_PCK_CK_P1  70
-#define CLK_INFRA_133M_USB_HCK	      71
-#define CLK_INFRA_133M_USB_HCK_CK_P1  72
-#define CLK_INFRA_66M_USB_HCK	      73
-#define CLK_INFRA_66M_USB_HCK_CK_P1   74
-#define CLK_INFRA_USB_SYS	      75
-#define CLK_INFRA_USB_SYS_CK_P1	      76
-#define CLK_INFRA_USB_REF	      77
-#define CLK_INFRA_USB_CK_P1	      78
-#define CLK_INFRA_USB_FRMCNT	      79
-#define CLK_INFRA_USB_FRMCNT_CK_P1    80
-#define CLK_INFRA_USB_PIPE	      81
-#define CLK_INFRA_USB_PIPE_CK_P1      82
-#define CLK_INFRA_USB_UTMI	      83
-#define CLK_INFRA_USB_UTMI_CK_P1      84
-#define CLK_INFRA_USB_XHCI	      85
-#define CLK_INFRA_USB_XHCI_CK_P1      86
-#define CLK_INFRA_PCIE_GFMUX_TL_P0    87
-#define CLK_INFRA_PCIE_GFMUX_TL_P1    88
-#define CLK_INFRA_PCIE_GFMUX_TL_P2    89
-#define CLK_INFRA_PCIE_GFMUX_TL_P3    90
-#define CLK_INFRA_PCIE_PIPE_P0	      91
-#define CLK_INFRA_PCIE_PIPE_P1	      92
-#define CLK_INFRA_PCIE_PIPE_P2	      93
-#define CLK_INFRA_PCIE_PIPE_P3	      94
-#define CLK_INFRA_133M_PCIE_CK_P0     95
-#define CLK_INFRA_133M_PCIE_CK_P1     96
-#define CLK_INFRA_133M_PCIE_CK_P2     97
-#define CLK_INFRA_133M_PCIE_CK_P3     98
-
-/* ETHDMA */
-
-#define CLK_ETHDMA_XGP1_EN   0
-#define CLK_ETHDMA_XGP2_EN   1
-#define CLK_ETHDMA_XGP3_EN   2
-#define CLK_ETHDMA_FE_EN     3
-#define CLK_ETHDMA_GP2_EN    4
-#define CLK_ETHDMA_GP1_EN    5
-#define CLK_ETHDMA_GP3_EN    6
-#define CLK_ETHDMA_ESW_EN    7
-#define CLK_ETHDMA_CRYPT0_EN 8
-#define CLK_ETHDMA_NR_CLK    9
-
-/* SGMIISYS_0 */
-
-#define CLK_SGM0_TX_EN	  0
-#define CLK_SGM0_RX_EN	  1
-#define CLK_SGMII0_NR_CLK 2
-
-/* SGMIISYS_1 */
-
-#define CLK_SGM1_TX_EN	  0
-#define CLK_SGM1_RX_EN	  1
-#define CLK_SGMII1_NR_CLK 2
-
-/* ETHWARP */
-
-#define CLK_ETHWARP_WOCPU2_EN 0
-#define CLK_ETHWARP_WOCPU1_EN 1
-#define CLK_ETHWARP_WOCPU0_EN 2
-#define CLK_ETHWARP_NR_CLK    3
-
-#endif /* _DT_BINDINGS_CLK_MT7988_H */
diff --git a/target/linux/mediatek/files-5.15/include/dt-bindings/clock/mt7986-clk.h b/target/linux/mediatek/files-5.15/include/dt-bindings/clock/mt7986-clk.h
deleted file mode 100644
index 5a9b169324b065..00000000000000
--- a/target/linux/mediatek/files-5.15/include/dt-bindings/clock/mt7986-clk.h
+++ /dev/null
@@ -1,169 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
-/*
- * Copyright (c) 2021 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- */
-
-#ifndef _DT_BINDINGS_CLK_MT7986_H
-#define _DT_BINDINGS_CLK_MT7986_H
-
-/* APMIXEDSYS */
-
-#define CLK_APMIXED_ARMPLL		0
-#define CLK_APMIXED_NET2PLL		1
-#define CLK_APMIXED_MMPLL		2
-#define CLK_APMIXED_SGMPLL		3
-#define CLK_APMIXED_WEDMCUPLL		4
-#define CLK_APMIXED_NET1PLL		5
-#define CLK_APMIXED_MPLL		6
-#define CLK_APMIXED_APLL2		7
-
-/* TOPCKGEN */
-
-#define CLK_TOP_XTAL			0
-#define CLK_TOP_XTAL_D2			1
-#define CLK_TOP_RTC_32K			2
-#define CLK_TOP_RTC_32P7K		3
-#define CLK_TOP_MPLL_D2			4
-#define CLK_TOP_MPLL_D4			5
-#define CLK_TOP_MPLL_D8			6
-#define CLK_TOP_MPLL_D8_D2		7
-#define CLK_TOP_MPLL_D3_D2		8
-#define CLK_TOP_MMPLL_D2		9
-#define CLK_TOP_MMPLL_D4		10
-#define CLK_TOP_MMPLL_D8		11
-#define CLK_TOP_MMPLL_D8_D2		12
-#define CLK_TOP_MMPLL_D3_D8		13
-#define CLK_TOP_MMPLL_U2PHY		14
-#define CLK_TOP_APLL2_D4		15
-#define CLK_TOP_NET1PLL_D4		16
-#define CLK_TOP_NET1PLL_D5		17
-#define CLK_TOP_NET1PLL_D5_D2		18
-#define CLK_TOP_NET1PLL_D5_D4		19
-#define CLK_TOP_NET1PLL_D8_D2		20
-#define CLK_TOP_NET1PLL_D8_D4		21
-#define CLK_TOP_NET2PLL_D4		22
-#define CLK_TOP_NET2PLL_D4_D2		23
-#define CLK_TOP_NET2PLL_D3_D2		24
-#define CLK_TOP_WEDMCUPLL_D5_D2		25
-#define CLK_TOP_NFI1X_SEL		26
-#define CLK_TOP_SPINFI_SEL		27
-#define CLK_TOP_SPI_SEL			28
-#define CLK_TOP_SPIM_MST_SEL		29
-#define CLK_TOP_UART_SEL		30
-#define CLK_TOP_PWM_SEL			31
-#define CLK_TOP_I2C_SEL			32
-#define CLK_TOP_PEXTP_TL_SEL		33
-#define CLK_TOP_EMMC_250M_SEL		34
-#define CLK_TOP_EMMC_416M_SEL		35
-#define CLK_TOP_F_26M_ADC_SEL		36
-#define CLK_TOP_DRAMC_SEL		37
-#define CLK_TOP_DRAMC_MD32_SEL		38
-#define CLK_TOP_SYSAXI_SEL		39
-#define CLK_TOP_SYSAPB_SEL		40
-#define CLK_TOP_ARM_DB_MAIN_SEL		41
-#define CLK_TOP_ARM_DB_JTSEL		42
-#define CLK_TOP_NETSYS_SEL		43
-#define CLK_TOP_NETSYS_500M_SEL		44
-#define CLK_TOP_NETSYS_MCU_SEL		45
-#define CLK_TOP_NETSYS_2X_SEL		46
-#define CLK_TOP_SGM_325M_SEL		47
-#define CLK_TOP_SGM_REG_SEL		48
-#define CLK_TOP_A1SYS_SEL		49
-#define CLK_TOP_CONN_MCUSYS_SEL		50
-#define CLK_TOP_EIP_B_SEL		51
-#define CLK_TOP_PCIE_PHY_SEL		52
-#define CLK_TOP_USB3_PHY_SEL		53
-#define CLK_TOP_F26M_SEL		54
-#define CLK_TOP_AUD_L_SEL		55
-#define CLK_TOP_A_TUNER_SEL		56
-#define CLK_TOP_U2U3_SEL		57
-#define CLK_TOP_U2U3_SYS_SEL		58
-#define CLK_TOP_U2U3_XHCI_SEL		59
-#define CLK_TOP_DA_U2_REFSEL		60
-#define CLK_TOP_DA_U2_CK_1P_SEL		61
-#define CLK_TOP_AP2CNN_HOST_SEL		62
-#define CLK_TOP_JTAG			63
-
-/* INFRACFG */
-
-#define CLK_INFRA_SYSAXI_D2		0
-#define CLK_INFRA_UART0_SEL		1
-#define CLK_INFRA_UART1_SEL		2
-#define CLK_INFRA_UART2_SEL		3
-#define CLK_INFRA_SPI0_SEL		4
-#define CLK_INFRA_SPI1_SEL		5
-#define CLK_INFRA_PWM1_SEL		6
-#define CLK_INFRA_PWM2_SEL		7
-#define CLK_INFRA_PWM_BSEL		8
-#define CLK_INFRA_PCIE_SEL		9
-#define CLK_INFRA_GPT_STA		10
-#define CLK_INFRA_PWM_HCK		11
-#define CLK_INFRA_PWM_STA		12
-#define CLK_INFRA_PWM1_CK		13
-#define CLK_INFRA_PWM2_CK		14
-#define CLK_INFRA_CQ_DMA_CK		15
-#define CLK_INFRA_EIP97_CK		16
-#define CLK_INFRA_AUD_BUS_CK		17
-#define CLK_INFRA_AUD_26M_CK		18
-#define CLK_INFRA_AUD_L_CK		19
-#define CLK_INFRA_AUD_AUD_CK		20
-#define CLK_INFRA_AUD_EG2_CK		21
-#define CLK_INFRA_DRAMC_26M_CK		22
-#define CLK_INFRA_DBG_CK		23
-#define CLK_INFRA_AP_DMA_CK		24
-#define CLK_INFRA_SEJ_CK		25
-#define CLK_INFRA_SEJ_13M_CK		26
-#define CLK_INFRA_THERM_CK		27
-#define CLK_INFRA_I2C0_CK		28
-#define CLK_INFRA_UART0_CK		29
-#define CLK_INFRA_UART1_CK		30
-#define CLK_INFRA_UART2_CK		31
-#define CLK_INFRA_NFI1_CK		32
-#define CLK_INFRA_SPINFI1_CK		33
-#define CLK_INFRA_NFI_HCK_CK		34
-#define CLK_INFRA_SPI0_CK		35
-#define CLK_INFRA_SPI1_CK		36
-#define CLK_INFRA_SPI0_HCK_CK		37
-#define CLK_INFRA_SPI1_HCK_CK		38
-#define CLK_INFRA_FRTC_CK		39
-#define CLK_INFRA_MSDC_CK		40
-#define CLK_INFRA_MSDC_HCK_CK		41
-#define CLK_INFRA_MSDC_133M_CK		42
-#define CLK_INFRA_MSDC_66M_CK		43
-#define CLK_INFRA_ADC_26M_CK		44
-#define CLK_INFRA_ADC_FRC_CK		45
-#define CLK_INFRA_FBIST2FPC_CK		46
-#define CLK_INFRA_IUSB_133_CK		47
-#define CLK_INFRA_IUSB_66M_CK		48
-#define CLK_INFRA_IUSB_SYS_CK		49
-#define CLK_INFRA_IUSB_CK		50
-#define CLK_INFRA_IPCIE_CK		51
-#define CLK_INFRA_IPCIE_PIPE_CK		52
-#define CLK_INFRA_IPCIER_CK		53
-#define CLK_INFRA_IPCIEB_CK		54
-#define CLK_INFRA_TRNG_CK		55
-
-/* SGMIISYS_0 */
-
-#define CLK_SGMII0_TX250M_EN		0
-#define CLK_SGMII0_RX250M_EN		1
-#define CLK_SGMII0_CDR_REF		2
-#define CLK_SGMII0_CDR_FB		3
-
-/* SGMIISYS_1 */
-
-#define CLK_SGMII1_TX250M_EN		0
-#define CLK_SGMII1_RX250M_EN		1
-#define CLK_SGMII1_CDR_REF		2
-#define CLK_SGMII1_CDR_FB		3
-
-/* ETHSYS */
-
-#define CLK_ETH_FE_EN			0
-#define CLK_ETH_GP2_EN			1
-#define CLK_ETH_GP1_EN			2
-#define CLK_ETH_WOCPU1_EN		3
-#define CLK_ETH_WOCPU0_EN		4
-
-#endif /* _DT_BINDINGS_CLK_MT7986_H */
diff --git a/target/linux/mediatek/files-5.15/include/dt-bindings/reset/mt7986-resets.h b/target/linux/mediatek/files-5.15/include/dt-bindings/reset/mt7986-resets.h
deleted file mode 100644
index af3d16c81192f7..00000000000000
--- a/target/linux/mediatek/files-5.15/include/dt-bindings/reset/mt7986-resets.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
-/*
- * Copyright (c) 2022 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- */
-
-#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7986
-#define _DT_BINDINGS_RESET_CONTROLLER_MT7986
-
-/* INFRACFG resets */
-#define MT7986_INFRACFG_PEXTP_MAC_SW_RST	6
-#define MT7986_INFRACFG_SSUSB_SW_RST		7
-#define MT7986_INFRACFG_EIP97_SW_RST		8
-#define MT7986_INFRACFG_AUDIO_SW_RST		13
-#define MT7986_INFRACFG_CQ_DMA_SW_RST		14
-
-#define MT7986_INFRACFG_TRNG_SW_RST		17
-#define MT7986_INFRACFG_AP_DMA_SW_RST		32
-#define MT7986_INFRACFG_I2C_SW_RST		33
-#define MT7986_INFRACFG_NFI_SW_RST		34
-#define MT7986_INFRACFG_SPI0_SW_RST		35
-#define MT7986_INFRACFG_SPI1_SW_RST		36
-#define MT7986_INFRACFG_UART0_SW_RST		37
-#define MT7986_INFRACFG_UART1_SW_RST		38
-#define MT7986_INFRACFG_UART2_SW_RST		39
-#define MT7986_INFRACFG_AUXADC_SW_RST		43
-
-#define MT7986_INFRACFG_APXGPT_SW_RST		66
-#define MT7986_INFRACFG_PWM_SW_RST		68
-
-#define MT7986_INFRACFG_SW_RST_NUM		69
-
-/* TOPRGU resets */
-#define MT7986_TOPRGU_APMIXEDSYS_SW_RST		0
-#define MT7986_TOPRGU_SGMII0_SW_RST		1
-#define MT7986_TOPRGU_SGMII1_SW_RST		2
-#define MT7986_TOPRGU_INFRA_SW_RST		3
-#define MT7986_TOPRGU_U2PHY_SW_RST		5
-#define MT7986_TOPRGU_PCIE_SW_RST		6
-#define MT7986_TOPRGU_SSUSB_SW_RST		7
-#define MT7986_TOPRGU_ETHDMA_SW_RST		20
-#define MT7986_TOPRGU_CONSYS_SW_RST		23
-
-#define MT7986_TOPRGU_SW_RST_NUM		24
-
-/* ETHSYS Subsystem resets */
-#define MT7986_ETHSYS_FE_SW_RST			6
-#define MT7986_ETHSYS_PMTR_SW_RST		8
-#define MT7986_ETHSYS_GMAC_SW_RST		23
-#define MT7986_ETHSYS_PPE0_SW_RST		30
-#define MT7986_ETHSYS_PPE1_SW_RST		31
-
-#define MT7986_ETHSYS_SW_RST_NUM		32
-
-#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT7986 */
diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981.dtsi b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981.dtsi
index cb161df81e9d57..54cfd0b4b9f745 100644
--- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981.dtsi
+++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981.dtsi
@@ -27,30 +27,36 @@
 		#size-cells = <0>;
 
 		cpu@0 {
-			device_type = "cpu";
 			compatible = "arm,cortex-a53";
-			enable-method = "psci";
 			reg = <0x0>;
+			device_type = "cpu";
+			enable-method = "psci";
 		};
 
 		cpu@1 {
-			device_type = "cpu";
 			compatible = "arm,cortex-a53";
-			enable-method = "psci";
 			reg = <0x1>;
+			device_type = "cpu";
+			enable-method = "psci";
 		};
 	};
 
-	pwm: pwm@10048000 {
-		compatible = "mediatek,mt7981-pwm";
-		reg = <0 0x10048000 0 0x1000>;
-		#pwm-cells = <2>;
-		clocks = <&infracfg CLK_INFRA_PWM_STA>,
-			 <&infracfg CLK_INFRA_PWM_HCK>,
-			 <&infracfg CLK_INFRA_PWM1_CK>,
-			 <&infracfg CLK_INFRA_PWM2_CK>,
-			 <&infracfg CLK_INFRA_PWM3_CK>;
-		clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
+	ice: ice_debug {
+		compatible = "mediatek,mt7981-ice_debug", "mediatek,mt2701-ice_debug";
+		clocks = <&infracfg CLK_INFRA_DBG_CK>;
+		clock-names = "ice_dbg";
+	};
+
+	clk40m: oscillator-40m {
+		compatible = "fixed-clock";
+		clock-frequency = <40000000>;
+		clock-output-names = "clkxtal";
+		#clock-cells = <0>;
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
 	};
 
 	fan: pwm-fan {
@@ -61,121 +67,19 @@
 		status = "disabled";
 	};
 
-	thermal-zones {
-		cpu_thermal: cpu-thermal {
-			polling-delay-passive = <1000>;
-			polling-delay = <1000>;
-			thermal-sensors = <&thermal 0>;
-			trips {
-				cpu_trip_active_highest: active-highest {
-					temperature = <70000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-
-				cpu_trip_active_high: active-high {
-					temperature = <60000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-
-				cpu_trip_active_med: active-med {
-					temperature = <50000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-
-				cpu_trip_active_low: active-low {
-					temperature = <45000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-
-				cpu_trip_active_lowest: active-lowest {
-					temperature = <40000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-			};
-
-			cooling-maps {
-				cpu-active-highest {
-					/* active: set fan to cooling level 7 */
-					cooling-device = <&fan 7 7>;
-					trip = <&cpu_trip_active_highest>;
-				};
-
-				cpu-active-high {
-					/* active: set fan to cooling level 5 */
-					cooling-device = <&fan 5 5>;
-					trip = <&cpu_trip_active_high>;
-				};
-
-				cpu-active-med {
-					/* active: set fan to cooling level 3 */
-					cooling-device = <&fan 3 3>;
-					trip = <&cpu_trip_active_med>;
-				};
-
-				cpu-active-low {
-					/* active: set fan to cooling level 2 */
-					cooling-device = <&fan 2 2>;
-					trip = <&cpu_trip_active_low>;
-				};
-
-				cpu-active-lowest {
-					/* active: set fan to cooling level 1 */
-					cooling-device = <&fan 1 1>;
-					trip = <&cpu_trip_active_lowest>;
-				};
-			};
-		};
-	};
-
-	thermal: thermal@1100c800 {
-		#thermal-sensor-cells = <1>;
-		compatible = "mediatek,mt7981-thermal", "mediatek,mt7986-thermal";
-		reg = <0 0x1100c800 0 0x800>;
-		interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&infracfg CLK_INFRA_THERM_CK>,
-			 <&infracfg CLK_INFRA_ADC_26M_CK>;
-		clock-names = "therm", "auxadc";
-		mediatek,auxadc = <&auxadc>;
-		mediatek,apmixedsys = <&apmixedsys>;
-		nvmem-cells = <&thermal_calibration>;
-		nvmem-cell-names = "calibration-data";
-	};
-
-	auxadc: adc@1100d000 {
-		compatible = "mediatek,mt7981-auxadc",
-			     "mediatek,mt7986-auxadc",
-			     "mediatek,mt7622-auxadc";
-		reg = <0 0x1100d000 0 0x1000>;
-		clocks = <&infracfg CLK_INFRA_ADC_26M_CK>,
-			 <&infracfg CLK_INFRA_ADC_FRC_CK>;
-		clock-names = "main", "32k";
-		#io-channel-cells = <1>;
-	};
-
-	wdma: wdma@15104800 {
-		compatible = "mediatek,wed-wdma";
-		reg = <0 0x15104800 0 0x400>,
-		      <0 0x15104c00 0 0x400>;
-	};
-
-	ap2woccif: ap2woccif@151a5000 {
-		compatible = "mediatek,ap2woccif";
-		reg = <0 0x151a5000 0 0x1000>,
-		      <0 0x151ad000 0 0x1000>;
-		interrupt-parent = <&gic>;
-		interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
+	reg_3p3v: regulator-3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
 	};
 
 	reserved-memory {
+		ranges;
 		#address-cells = <2>;
 		#size-cells = <2>;
-		ranges;
 
 		/* 64 KiB reserved for ramoops/pstore */
 		ramoops@42ff0000 {
@@ -206,615 +110,713 @@
 		};
 	};
 
-	psci {
-		compatible  = "arm,psci-0.2";
-		method      = "smc";
-	};
+	soc {
+		compatible = "simple-bus";
+		ranges;
+		#address-cells = <2>;
+		#size-cells = <2>;
 
-	trng {
-		compatible = "mediatek,mt7981-rng";
-	};
+		gic: interrupt-controller@c000000 {
+			compatible = "arm,gic-v3";
+			reg = <0 0x0c000000 0 0x40000>,  /* GICD */
+			      <0 0x0c080000 0 0x200000>; /* GICR */
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+		};
 
-	clk40m: oscillator@0 {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <40000000>;
-		clock-output-names = "clkxtal";
-	};
+		consys: consys@10000000 {
+			compatible = "mediatek,mt7981-consys";
+			reg = <0 0x10000000 0 0x8600000>;
+			memory-region = <&wmcpu_emi>;
+		};
 
-	infracfg: infracfg@10001000 {
-		compatible = "mediatek,mt7981-infracfg", "syscon";
-		reg = <0 0x10001000 0 0x1000>;
-		#clock-cells = <1>;
-	};
+		infracfg: clock-controller@10001000 {
+			compatible = "mediatek,mt7981-infracfg", "syscon";
+			reg = <0 0x10001000 0 0x1000>;
+			#clock-cells = <1>;
+		};
 
-	topckgen: topckgen@1001B000 {
-		compatible = "mediatek,mt7981-topckgen", "syscon";
-		reg = <0 0x1001B000 0 0x1000>;
-		#clock-cells = <1>;
-	};
+		wed_pcie: wed_pcie@10003000 {
+			compatible = "mediatek,wed_pcie";
+			reg = <0 0x10003000 0 0x10>;
+		};
 
-	apmixedsys: apmixedsys@1001E000 {
-		compatible = "mediatek,mt7981-apmixedsys", "mediatek,mt7986-apmixedsys", "syscon";
-		reg = <0 0x1001E000 0 0x1000>;
-		#clock-cells = <1>;
-	};
+		topckgen: clock-controller@1001b000 {
+			compatible = "mediatek,mt7981-topckgen", "syscon";
+			reg = <0 0x1001b000 0 0x1000>;
+			#clock-cells = <1>;
+		};
 
-	timer {
-		compatible = "arm,armv8-timer";
-		interrupt-parent = <&gic>;
-		clock-frequency = <13000000>;
-		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+		watchdog: watchdog@1001c000 {
+			compatible = "mediatek,mt7986-wdt",
+				     "mediatek,mt6589-wdt";
+			reg = <0 0x1001c000 0 0x1000>;
+			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+			#reset-cells = <1>;
+			status = "disabled";
+		};
 
-	};
+		apmixedsys: clock-controller@1001e000 {
+			compatible = "mediatek,mt7981-apmixedsys", "syscon";
+			reg = <0 0x1001e000 0 0x1000>;
+			#clock-cells = <1>;
+		};
 
-	watchdog: watchdog@1001c000 {
-		compatible = "mediatek,mt7986-wdt",
-			     "mediatek,mt6589-wdt";
-		reg = <0 0x1001c000 0 0x1000>;
-		interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
-		#reset-cells = <1>;
-		status = "disabled";
-	};
+		pwm: pwm@10048000 {
+			compatible = "mediatek,mt7981-pwm";
+			reg = <0 0x10048000 0 0x1000>;
+			clocks = <&infracfg CLK_INFRA_PWM_STA>,
+				 <&infracfg CLK_INFRA_PWM_HCK>,
+				 <&infracfg CLK_INFRA_PWM1_CK>,
+				 <&infracfg CLK_INFRA_PWM2_CK>,
+				 <&infracfg CLK_INFRA_PWM3_CK>;
+			clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
+			#pwm-cells = <2>;
+		};
 
-	gic: interrupt-controller@c000000 {
-		compatible = "arm,gic-v3";
-		#interrupt-cells = <3>;
-		interrupt-parent = <&gic>;
-		interrupt-controller;
-		reg = <0 0x0c000000 0 0x40000>,  /* GICD */
-		      <0 0x0c080000 0 0x200000>; /* GICR */
+		sgmiisys0: syscon@10060000 {
+			compatible = "mediatek,mt7981-sgmiisys_0", "syscon";
+			reg = <0 0x10060000 0 0x1000>;
+			mediatek,pnswap;
+			#clock-cells = <1>;
+		};
 
-		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
-	};
+		sgmiisys1: syscon@10070000 {
+			compatible = "mediatek,mt7981-sgmiisys_1", "syscon";
+			reg = <0 0x10070000 0 0x1000>;
+			#clock-cells = <1>;
+		};
 
-	uart0: serial@11002000 {
-		compatible = "mediatek,mt6577-uart";
-		reg = <0 0x11002000 0 0x400>;
-		interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&infracfg CLK_INFRA_UART0_SEL>,
-			<&infracfg CLK_INFRA_UART0_CK>;
-		clock-names = "baud", "bus";
-		assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
-				  <&infracfg CLK_INFRA_UART0_SEL>;
-		assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
-					 <&topckgen CLK_TOP_UART_SEL>;
-		pinctrl-0 = <&uart0_pins>;
-		pinctrl-names = "default";
-		status = "disabled";
-	};
+		crypto: crypto@10320000 {
+			compatible = "inside-secure,safexcel-eip97";
+			reg = <0 0x10320000 0 0x40000>;
+			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "ring0", "ring1", "ring2", "ring3";
+			clocks = <&topckgen CLK_TOP_EIP97B>;
+			clock-names = "top_eip97_ck";
+			assigned-clocks = <&topckgen CLK_TOP_EIP97B_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_CB_NET1_D5>;
+		};
 
-	uart1: serial@11003000 {
-		compatible = "mediatek,mt6577-uart";
-		reg = <0 0x11003000 0 0x400>;
-		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&infracfg CLK_INFRA_UART1_SEL>,
-			<&infracfg CLK_INFRA_UART1_CK>;
-		clock-names = "baud", "bus";
-		assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
-				  <&infracfg CLK_INFRA_UART1_SEL>;
-		assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
-					 <&topckgen CLK_TOP_UART_SEL>;
-		status = "disabled";
-	};
+		uart0: serial@11002000 {
+			compatible = "mediatek,mt6577-uart";
+			reg = <0 0x11002000 0 0x400>;
+			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&infracfg CLK_INFRA_UART0_SEL>,
+				 <&infracfg CLK_INFRA_UART0_CK>;
+			clock-names = "baud", "bus";
+			assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
+					  <&infracfg CLK_INFRA_UART0_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
+						 <&topckgen CLK_TOP_UART_SEL>;
+			pinctrl-0 = <&uart0_pins>;
+			pinctrl-names = "default";
+			status = "disabled";
+		};
 
-	uart2: serial@11004000 {
-		compatible = "mediatek,mt6577-uart";
-		reg = <0 0x11004000 0 0x400>;
-		interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&infracfg CLK_INFRA_UART2_SEL>,
-			<&infracfg CLK_INFRA_UART2_CK>;
-		clock-names = "baud", "bus";
-		assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
-				  <&infracfg CLK_INFRA_UART2_SEL>;
-		assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
-					 <&topckgen CLK_TOP_UART_SEL>;
-		status = "disabled";
-	};
+		uart1: serial@11003000 {
+			compatible = "mediatek,mt6577-uart";
+			reg = <0 0x11003000 0 0x400>;
+			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&infracfg CLK_INFRA_UART1_SEL>,
+				 <&infracfg CLK_INFRA_UART1_CK>;
+			clock-names = "baud", "bus";
+			assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
+					  <&infracfg CLK_INFRA_UART1_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
+						 <&topckgen CLK_TOP_UART_SEL>;
+			status = "disabled";
+		};
 
-	i2c0: i2c@11007000 {
-		compatible = "mediatek,mt7981-i2c";
-		reg = <0 0x11007000 0 0x1000>,
-		      <0 0x10217080 0 0x80>;
-		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
-		clock-div = <1>;
-		clocks = <&infracfg CLK_INFRA_I2C0_CK>,
-			 <&infracfg CLK_INFRA_AP_DMA_CK>,
-			 <&infracfg CLK_INFRA_I2C_MCK_CK>,
-			 <&infracfg CLK_INFRA_I2C_PCK_CK>;
-		clock-names = "main", "dma", "arb", "pmic";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-	};
+		uart2: serial@11004000 {
+			compatible = "mediatek,mt6577-uart";
+			reg = <0 0x11004000 0 0x400>;
+			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&infracfg CLK_INFRA_UART2_SEL>,
+				 <&infracfg CLK_INFRA_UART2_CK>;
+			clock-names = "baud", "bus";
+			assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
+					  <&infracfg CLK_INFRA_UART2_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
+						 <&topckgen CLK_TOP_UART_SEL>;
+			status = "disabled";
+		};
 
-	pcie: pcie@11280000 {
-		compatible = "mediatek,mt7981-pcie",
-			     "mediatek,mt7986-pcie";
-		device_type = "pci";
-		reg = <0 0x11280000 0 0x4000>;
-		reg-names = "pcie-mac";
-		#address-cells = <3>;
-		#size-cells = <2>;
-		interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
-		bus-range = <0x00 0xff>;
-		ranges = <0x82000000 0 0x20000000
-			  0x0 0x20000000 0 0x10000000>;
-		status = "disabled";
+		snand: snfi@11005000 {
+			compatible = "mediatek,mt7986-snand";
+			reg = <0 0x11005000 0 0x1000>, <0 0x11006000 0 0x1000>;
+			reg-names = "nfi", "ecc";
+			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&infracfg CLK_INFRA_SPINFI1_CK>,
+				 <&infracfg CLK_INFRA_NFI1_CK>,
+				 <&infracfg CLK_INFRA_NFI_HCK_CK>;
+			clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
+			assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
+					  <&topckgen CLK_TOP_NFI1X_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D8>,
+						 <&topckgen CLK_TOP_CB_M_D8>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
 
-		clocks = <&infracfg CLK_INFRA_IPCIE_CK>,
-			 <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
-			 <&infracfg CLK_INFRA_IPCIER_CK>,
-			 <&infracfg CLK_INFRA_IPCIEB_CK>;
-
-		phys = <&u3port0 PHY_TYPE_PCIE>;
-		phy-names = "pcie-phy";
-
-		#interrupt-cells = <1>;
-		interrupt-map-mask = <0 0 0 7>;
-		interrupt-map = <0 0 0 1 &pcie_intc 0>,
-				<0 0 0 2 &pcie_intc 1>,
-				<0 0 0 3 &pcie_intc 2>,
-				<0 0 0 4 &pcie_intc 3>;
-		pcie_intc: interrupt-controller {
-			interrupt-controller;
-			#address-cells = <0>;
-			#interrupt-cells = <1>;
+		i2c0: i2c@11007000 {
+			compatible = "mediatek,mt7981-i2c";
+			reg = <0 0x11007000 0 0x1000>,
+			      <0 0x10217080 0 0x80>;
+			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+			clock-div = <1>;
+			clocks = <&infracfg CLK_INFRA_I2C0_CK>,
+				 <&infracfg CLK_INFRA_AP_DMA_CK>,
+				 <&infracfg CLK_INFRA_I2C_MCK_CK>,
+				 <&infracfg CLK_INFRA_I2C_PCK_CK>;
+			clock-names = "main", "dma", "arb", "pmic";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
 		};
-	};
 
-	crypto: crypto@10320000 {
-		compatible = "inside-secure,safexcel-eip97";
-		reg = <0 0x10320000 0 0x40000>;
-		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "ring0", "ring1", "ring2", "ring3";
-		clocks = <&topckgen CLK_TOP_EIP97B>;
-		clock-names = "top_eip97_ck";
-		assigned-clocks = <&topckgen CLK_TOP_EIP97B_SEL>;
-		assigned-clock-parents = <&topckgen CLK_TOP_CB_NET1_D5>;
-	};
+		spi2: spi@11009000 {
+			compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
+			reg = <0 0x11009000 0 0x100>;
+			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&topckgen CLK_TOP_CB_M_D2>,
+				 <&topckgen CLK_TOP_SPI_SEL>,
+				 <&infracfg CLK_INFRA_SPI2_CK>,
+				 <&infracfg CLK_INFRA_SPI2_HCK_CK>;
+			clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
 
-	pio: pinctrl@11d00000 {
-		compatible = "mediatek,mt7981-pinctrl";
-		reg = <0 0x11d00000 0 0x1000>,
-		      <0 0x11c00000 0 0x1000>,
-		      <0 0x11c10000 0 0x1000>,
-		      <0 0x11d20000 0 0x1000>,
-		      <0 0x11e00000 0 0x1000>,
-		      <0 0x11e20000 0 0x1000>,
-		      <0 0x11f00000 0 0x1000>,
-		      <0 0x11f10000 0 0x1000>,
-		      <0 0x1000b000 0 0x1000>;
-		reg-names = "gpio", "iocfg_rt", "iocfg_rm",
-			    "iocfg_rb", "iocfg_lb", "iocfg_bl",
-			    "iocfg_tm", "iocfg_tl", "eint";
-		gpio-controller;
-		#gpio-cells = <2>;
-		gpio-ranges = <&pio 0 0 56>;
-		interrupt-controller;
-		interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&gic>;
-		#interrupt-cells = <2>;
+		spi0: spi@1100a000 {
+			compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
+			reg = <0 0x1100a000 0 0x100>;
+			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&topckgen CLK_TOP_CB_M_D2>,
+				 <&topckgen CLK_TOP_SPI_SEL>,
+				 <&infracfg CLK_INFRA_SPI0_CK>,
+				 <&infracfg CLK_INFRA_SPI0_HCK_CK>;
+			clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
 
-		mdio_pins: mdc-mdio-pins {
-			mux {
-				function = "eth";
-				groups = "smi_mdc_mdio";
-			};
+		spi1: spi@1100b000 {
+			compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
+			reg = <0 0x1100b000 0 0x100>;
+			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&topckgen CLK_TOP_CB_M_D2>,
+				 <&topckgen CLK_TOP_SPIM_MST_SEL>,
+				 <&infracfg CLK_INFRA_SPI1_CK>,
+				 <&infracfg CLK_INFRA_SPI1_HCK_CK>;
+			clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
 		};
 
-		uart0_pins: uart0-pins {
-			mux {
-				function = "uart";
-				groups = "uart0";
-			};
+		thermal: thermal@1100c800 {
+			compatible = "mediatek,mt7981-thermal", "mediatek,mt7986-thermal";
+			reg = <0 0x1100c800 0 0x800>;
+			interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&infracfg CLK_INFRA_THERM_CK>,
+				 <&infracfg CLK_INFRA_ADC_26M_CK>;
+			clock-names = "therm", "auxadc";
+			nvmem-cells = <&thermal_calibration>;
+			nvmem-cell-names = "calibration-data";
+			#thermal-sensor-cells = <1>;
+			mediatek,auxadc = <&auxadc>;
+			mediatek,apmixedsys = <&apmixedsys>;
 		};
 
-		wifi_dbdc_pins: wifi-dbdc-pins {
-			mux {
-				function = "eth";
-				groups = "wf0_mode1";
-			};
-			conf {
-				pins = "WF_HB1", "WF_HB2", "WF_HB3", "WF_HB4",
-				       "WF_HB0", "WF_HB0_B", "WF_HB5", "WF_HB6",
-				       "WF_HB7", "WF_HB8", "WF_HB9", "WF_HB10",
-				       "WF_TOP_CLK", "WF_TOP_DATA", "WF_XO_REQ",
-				       "WF_CBA_RESETB", "WF_DIG_RESETB";
-				drive-strength = <4>;
-			};
+		auxadc: adc@1100d000 {
+			compatible = "mediatek,mt7981-auxadc",
+				     "mediatek,mt7986-auxadc",
+				     "mediatek,mt7622-auxadc";
+			reg = <0 0x1100d000 0 0x1000>;
+			clocks = <&infracfg CLK_INFRA_ADC_26M_CK>,
+				 <&infracfg CLK_INFRA_ADC_FRC_CK>;
+			clock-names = "main", "32k";
+			#io-channel-cells = <1>;
 		};
 
-		gbe_led0_pins: gbe-led0-pins {
-			mux {
-				function = "led";
-				groups = "gbe_led0";
-			};
+		xhci: usb@11200000 {
+			compatible = "mediatek,mt7986-xhci",
+				     "mediatek,mtk-xhci";
+			reg = <0 0x11200000 0 0x2e00>,
+			      <0 0x11203e00 0 0x0100>;
+			reg-names = "mac", "ippc";
+			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
+				 <&infracfg CLK_INFRA_IUSB_CK>,
+				 <&infracfg CLK_INFRA_IUSB_133_CK>,
+				 <&infracfg CLK_INFRA_IUSB_66M_CK>,
+				 <&topckgen CLK_TOP_U2U3_XHCI_SEL>;
+			clock-names = "sys_ck",
+				      "ref_ck",
+				      "mcu_ck",
+				      "dma_ck",
+				      "xhci_ck";
+			phys = <&u2port0 PHY_TYPE_USB2>,
+			       <&u3port0 PHY_TYPE_USB3>;
+			vusb33-supply = <&reg_3p3v>;
+			status = "disabled";
+		};
+
+		afe: audio-controller@11210000 {
+			compatible = "mediatek,mt79xx-audio";
+			reg = <0 0x11210000 0 0x9000>;
+			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&infracfg CLK_INFRA_AUD_BUS_CK>,
+				 <&infracfg CLK_INFRA_AUD_26M_CK>,
+				 <&infracfg CLK_INFRA_AUD_L_CK>,
+				 <&infracfg CLK_INFRA_AUD_AUD_CK>,
+				 <&infracfg CLK_INFRA_AUD_EG2_CK>,
+				 <&topckgen CLK_TOP_AUD_SEL>;
+			clock-names = "aud_bus_ck",
+				      "aud_26m_ck",
+				      "aud_l_ck",
+				      "aud_aud_ck",
+				      "aud_eg2_ck",
+				      "aud_sel";
+			assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
+					  <&topckgen CLK_TOP_A1SYS_SEL>,
+					  <&topckgen CLK_TOP_AUD_L_SEL>,
+					  <&topckgen CLK_TOP_A_TUNER_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_CB_APLL2_196M>,
+						 <&topckgen CLK_TOP_APLL2_D4>,
+						 <&topckgen CLK_TOP_CB_APLL2_196M>,
+						 <&topckgen CLK_TOP_APLL2_D4>;
+			status = "disabled";
+		};
+
+		mmc0: mmc@11230000 {
+			compatible = "mediatek,mt7986-mmc", "mediatek,mt7981-mmc";
+			reg = <0 0x11230000 0 0x1000>, <0 0x11c20000 0 0x1000>;
+			interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&infracfg CLK_INFRA_MSDC_CK>,
+				 <&infracfg CLK_INFRA_MSDC_HCK_CK>,
+				 <&infracfg CLK_INFRA_MSDC_66M_CK>,
+				 <&infracfg CLK_INFRA_MSDC_133M_CK>;
+			assigned-clocks = <&topckgen CLK_TOP_EMMC_208M_SEL>,
+					  <&topckgen CLK_TOP_EMMC_400M_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
+						 <&topckgen CLK_TOP_CB_NET2_D2>;
+			clock-names = "source", "hclk", "axi_cg", "ahb_cg";
+			status = "disabled";
 		};
 
-		gbe_led1_pins: gbe-led1-pins {
-			mux {
-				function = "led";
-				groups = "gbe_led1";
+		pcie: pcie@11280000 {
+			compatible = "mediatek,mt7981-pcie",
+				     "mediatek,mt7986-pcie";
+			reg = <0 0x11280000 0 0x4000>;
+			reg-names = "pcie-mac";
+			ranges = <0x82000000 0 0x20000000
+				  0x0 0x20000000 0 0x10000000>;
+			device_type = "pci";
+			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+			bus-range = <0x00 0xff>;
+			clocks = <&infracfg CLK_INFRA_IPCIE_CK>,
+				 <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
+				 <&infracfg CLK_INFRA_IPCIER_CK>,
+				 <&infracfg CLK_INFRA_IPCIEB_CK>;
+			phys = <&u3port0 PHY_TYPE_PCIE>;
+			phy-names = "pcie-phy";
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-map = <0 0 0 1 &pcie_intc 0>,
+					<0 0 0 2 &pcie_intc 1>,
+					<0 0 0 3 &pcie_intc 2>,
+					<0 0 0 4 &pcie_intc 3>;
+			#interrupt-cells = <1>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			status = "disabled";
+
+			pcie_intc: interrupt-controller {
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				#address-cells = <0>;
 			};
 		};
-	};
 
-	ethsys: syscon@15000000 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "mediatek,mt7981-ethsys",
-			     "mediatek,mt7986-ethsys",
-			     "syscon";
-		reg = <0 0x15000000 0 0x1000>;
-		#clock-cells = <1>;
-		#reset-cells = <1>;
-	};
+		pio: pinctrl@11d00000 {
+			compatible = "mediatek,mt7981-pinctrl";
+			reg = <0 0x11d00000 0 0x1000>,
+			      <0 0x11c00000 0 0x1000>,
+			      <0 0x11c10000 0 0x1000>,
+			      <0 0x11d20000 0 0x1000>,
+			      <0 0x11e00000 0 0x1000>,
+			      <0 0x11e20000 0 0x1000>,
+			      <0 0x11f00000 0 0x1000>,
+			      <0 0x11f10000 0 0x1000>,
+			      <0 0x1000b000 0 0x1000>;
+			reg-names = "gpio", "iocfg_rt", "iocfg_rm",
+				    "iocfg_rb", "iocfg_lb", "iocfg_bl",
+				    "iocfg_tm", "iocfg_tl", "eint";
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pio 0 0 56>;
+			interrupt-controller;
+			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-parent = <&gic>;
+			#interrupt-cells = <2>;
+
+			mdio_pins: mdc-mdio-pins {
+				mux {
+					function = "eth";
+					groups = "smi_mdc_mdio";
+				};
+			};
 
-	wed: wed@15010000 {
-		compatible = "mediatek,mt7981-wed",
-			     "mediatek,mt7986-wed",
-			     "syscon";
-		reg = <0 0x15010000 0 0x1000>;
-		interrupt-parent = <&gic>;
-		interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
-		memory-region = <&wo_emi0>, <&wo_data>;
-		memory-region-names = "wo-emi", "wo-data";
-		mediatek,wo-ccif = <&wo_ccif0>;
-		mediatek,wo-ilm = <&wo_ilm0>;
-		mediatek,wo-dlm = <&wo_dlm0>;
-		mediatek,wo-cpuboot = <&wo_cpuboot>;
-	};
+			uart0_pins: uart0-pins {
+				mux {
+					function = "uart";
+					groups = "uart0";
+				};
+			};
 
-	eth: ethernet@15100000 {
-		compatible = "mediatek,mt7981-eth";
-		reg = <0 0x15100000 0 0x80000>;
-		interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&ethsys CLK_ETH_FE_EN>,
-			<&ethsys CLK_ETH_GP2_EN>,
-			<&ethsys CLK_ETH_GP1_EN>,
-			<&ethsys CLK_ETH_WOCPU0_EN>,
-			<&sgmiisys0 CLK_SGM0_TX_EN>,
-			<&sgmiisys0 CLK_SGM0_RX_EN>,
-			<&sgmiisys0 CLK_SGM0_CK0_EN>,
-			<&sgmiisys0 CLK_SGM0_CDR_CK0_EN>,
-			<&sgmiisys1 CLK_SGM1_TX_EN>,
-			<&sgmiisys1 CLK_SGM1_RX_EN>,
-			<&sgmiisys1 CLK_SGM1_CK1_EN>,
-			<&sgmiisys1 CLK_SGM1_CDR_CK1_EN>,
-			<&topckgen CLK_TOP_SGM_REG>,
-			<&topckgen CLK_TOP_NETSYS_SEL>,
-			<&topckgen CLK_TOP_NETSYS_500M_SEL>;
-		clock-names = "fe", "gp2", "gp1", "wocpu0",
-					"sgmii_tx250m", "sgmii_rx250m",
-					"sgmii_cdr_ref", "sgmii_cdr_fb",
-					"sgmii2_tx250m", "sgmii2_rx250m",
-					"sgmii2_cdr_ref", "sgmii2_cdr_fb",
-					"sgmii_ck", "netsys0", "netsys1";
-		assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
-				  <&topckgen CLK_TOP_SGM_325M_SEL>;
-		assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_800M>,
-					 <&topckgen CLK_TOP_CB_SGM_325M>;
-		mediatek,ethsys = <&ethsys>;
-		mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
-		mediatek,infracfg = <&topmisc>;
-		mediatek,wed = <&wed>;
-		#reset-cells = <1>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
+			wifi_dbdc_pins: wifi-dbdc-pins {
+				mux {
+					function = "eth";
+					groups = "wf0_mode1";
+				};
 
-		mdio_bus: mdio-bus {
-			#address-cells = <1>;
-			#size-cells = <0>;
+				conf {
+					pins = "WF_HB1", "WF_HB2", "WF_HB3", "WF_HB4",
+					       "WF_HB0", "WF_HB0_B", "WF_HB5", "WF_HB6",
+					       "WF_HB7", "WF_HB8", "WF_HB9", "WF_HB10",
+					       "WF_TOP_CLK", "WF_TOP_DATA", "WF_XO_REQ",
+					       "WF_CBA_RESETB", "WF_DIG_RESETB";
+					drive-strength = <4>;
+				};
+			};
 
-			int_gbe_phy: ethernet-phy@0 {
-				reg = <0>;
-				compatible = "ethernet-phy-ieee802.3-c22";
-				phy-mode = "gmii";
-				phy-is-integrated;
-				nvmem-cells = <&phy_calibration>;
-				nvmem-cell-names = "phy-cal-data";
-
-				leds {
-					#address-cells = <1>;
-					#size-cells = <0>;
-
-					int_gbe_phy_led0: int-gbe-phy-led0@0 {
-						reg = <0>;
-						function = LED_FUNCTION_LAN;
-						status = "disabled";
-					};
+			gbe_led0_pins: gbe-led0-pins {
+				mux {
+					function = "led";
+					groups = "gbe_led0";
+				};
+			};
 
-					int_gbe_phy_led1: int-gbe-phy-led1@1 {
-						reg = <1>;
-						function = LED_FUNCTION_LAN;
-						status = "disabled";
-					};
+			gbe_led1_pins: gbe-led1-pins {
+				mux {
+					function = "led";
+					groups = "gbe_led1";
 				};
 			};
 		};
-	};
 
-	wo_dlm0: syscon@151e8000 {
-		compatible = "mediatek,mt7986-wo-dlm", "syscon";
-		reg = <0 0x151e8000 0 0x2000>;
-	};
+		topmisc: topmisc@11d10000 {
+			compatible = "mediatek,mt7981-topmisc", "syscon";
+			reg = <0 0x11d10000 0 0x10000>;
+			#clock-cells = <1>;
+		};
 
-	wo_ilm0: syscon@151e0000 {
-		compatible = "mediatek,mt7986-wo-ilm", "syscon";
-		reg = <0 0x151e0000 0 0x8000>;
-	};
+		usb_phy: usb-phy@11e10000 {
+			compatible = "mediatek,mt7981",
+				     "mediatek,generic-tphy-v2";
+			ranges = <0 0 0x11e10000 0x1700>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			status = "disabled";
+
+			u2port0: usb-phy@0 {
+				reg = <0x0 0x700>;
+				clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>;
+				clock-names = "ref";
+				#phy-cells = <1>;
+			};
 
-	wo_cpuboot: syscon@15194000 {
-		compatible = "mediatek,mt7986-wo-cpuboot", "syscon";
-		reg = <0 0x15194000 0 0x1000>;
-	};
+			u3port0: usb-phy@700 {
+				reg = <0x700 0x900>;
+				clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
+				clock-names = "ref";
+				#phy-cells = <1>;
+				mediatek,syscon-type = <&topmisc 0x218 0>;
+				status = "okay";
+			};
+		};
 
-	wo_ccif0: syscon@151a5000 {
-		compatible = "mediatek,mt7986-wo-ccif", "syscon";
-		reg = <0 0x151a5000 0 0x1000>;
-		interrupt-parent = <&gic>;
-		interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
-	};
+		efuse: efuse@11f20000 {
+			compatible = "mediatek,mt7981-efuse",
+				     "mediatek,efuse";
+			reg = <0 0x11f20000 0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			status = "okay";
 
-	sgmiisys0: syscon@10060000 {
-		compatible = "mediatek,mt7981-sgmiisys_0", "mediatek,mt7986-sgmiisys_0", "syscon";
-		reg = <0 0x10060000 0 0x1000>;
-		mediatek,pnswap;
-		#clock-cells = <1>;
-	};
+			thermal_calibration: thermal-calib@274 {
+				reg = <0x274 0xc>;
+			};
 
-	sgmiisys1: syscon@10070000 {
-		compatible = "mediatek,mt7981-sgmiisys_1", "mediatek,mt7986-sgmiisys_1", "syscon";
-		reg = <0 0x10070000 0 0x1000>;
-		#clock-cells = <1>;
-	};
+			phy_calibration: phy-calib@8dc {
+				reg = <0x8dc 0x10>;
+			};
 
-	topmisc: topmisc@11d10000 {
-		compatible = "mediatek,mt7981-topmisc", "syscon";
-		reg = <0 0x11d10000 0 0x10000>;
-		#clock-cells = <1>;
-	};
+			comb_rx_imp_p0: usb3-rx-imp@8c8 {
+				reg = <0x8c8 1>;
+				bits = <0 5>;
+			};
 
-	snand: snfi@11005000 {
-		compatible = "mediatek,mt7986-snand";
-		reg = <0 0x11005000 0 0x1000>, <0 0x11006000 0 0x1000>;
-		reg-names = "nfi", "ecc";
-		interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&infracfg CLK_INFRA_SPINFI1_CK>,
-			 <&infracfg CLK_INFRA_NFI1_CK>,
-			 <&infracfg CLK_INFRA_NFI_HCK_CK>;
-		clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
-		assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
-				  <&topckgen CLK_TOP_NFI1X_SEL>;
-		assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D8>,
-					 <&topckgen CLK_TOP_CB_M_D8>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-	};
+			comb_tx_imp_p0: usb3-tx-imp@8c8 {
+				reg = <0x8c8 2>;
+				bits = <5 5>;
+			};
 
-	mmc0: mmc@11230000 {
-		compatible = "mediatek,mt7986-mmc",
-					"mediatek,mt7981-mmc";
-		reg = <0 0x11230000 0 0x1000>, <0 0x11c20000 0 0x1000>;
-		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&infracfg CLK_INFRA_MSDC_CK>,
-			 <&infracfg CLK_INFRA_MSDC_HCK_CK>,
-			 <&infracfg CLK_INFRA_MSDC_66M_CK>,
-			 <&infracfg CLK_INFRA_MSDC_133M_CK>;
-		assigned-clocks = <&topckgen CLK_TOP_EMMC_208M_SEL>,
-				  <&topckgen CLK_TOP_EMMC_400M_SEL>;
-		assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
-					 <&topckgen CLK_TOP_CB_NET2_D2>;
-		clock-names = "source", "hclk", "axi_cg", "ahb_cg";
-		status = "disabled";
-	};
+			comb_intr_p0: usb3-intr@8c9 {
+				reg = <0x8c9 1>;
+				bits = <2 6>;
+			};
+		};
 
-	wed_pcie: wed_pcie@10003000 {
-		compatible = "mediatek,wed_pcie";
-		reg = <0 0x10003000 0 0x10>;
-	};
+		ethsys: clock-controller@15000000 {
+			compatible = "mediatek,mt7981-ethsys",
+				     "syscon";
+			reg = <0 0x15000000 0 0x1000>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+		};
 
-	spi0: spi@1100a000 {
-		compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0 0x1100a000 0 0x100>;
-		interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&topckgen CLK_TOP_CB_M_D2>,
-			 <&topckgen CLK_TOP_SPI_SEL>,
-			 <&infracfg CLK_INFRA_SPI0_CK>,
-			 <&infracfg CLK_INFRA_SPI0_HCK_CK>;
-
-		clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
-		status = "disabled";
-	};
+		wed: wed@15010000 {
+			compatible = "mediatek,mt7981-wed",
+				     "mediatek,mt7986-wed",
+				     "syscon";
+			reg = <0 0x15010000 0 0x1000>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+			memory-region = <&wo_emi0>, <&wo_data>;
+			memory-region-names = "wo-emi", "wo-data";
+			mediatek,wo-ccif = <&wo_ccif0>;
+			mediatek,wo-ilm = <&wo_ilm0>;
+			mediatek,wo-dlm = <&wo_dlm0>;
+			mediatek,wo-cpuboot = <&wo_cpuboot>;
+		};
 
-	spi1: spi@1100b000 {
-		compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0 0x1100b000 0 0x100>;
-		interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&topckgen CLK_TOP_CB_M_D2>,
-			 <&topckgen CLK_TOP_SPIM_MST_SEL>,
-			 <&infracfg CLK_INFRA_SPI1_CK>,
-			 <&infracfg CLK_INFRA_SPI1_HCK_CK>;
-		clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
-		status = "disabled";
-	};
+		eth: ethernet@15100000 {
+			compatible = "mediatek,mt7981-eth";
+			reg = <0 0x15100000 0 0x80000>;
+			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ethsys CLK_ETH_FE_EN>,
+				<&ethsys CLK_ETH_GP2_EN>,
+				<&ethsys CLK_ETH_GP1_EN>,
+				<&ethsys CLK_ETH_WOCPU0_EN>,
+				<&sgmiisys0 CLK_SGM0_TX_EN>,
+				<&sgmiisys0 CLK_SGM0_RX_EN>,
+				<&sgmiisys0 CLK_SGM0_CK0_EN>,
+				<&sgmiisys0 CLK_SGM0_CDR_CK0_EN>,
+				<&sgmiisys1 CLK_SGM1_TX_EN>,
+				<&sgmiisys1 CLK_SGM1_RX_EN>,
+				<&sgmiisys1 CLK_SGM1_CK1_EN>,
+				<&sgmiisys1 CLK_SGM1_CDR_CK1_EN>,
+				<&topckgen CLK_TOP_SGM_REG>,
+				<&topckgen CLK_TOP_NETSYS_SEL>,
+				<&topckgen CLK_TOP_NETSYS_500M_SEL>;
+			clock-names = "fe", "gp2", "gp1", "wocpu0",
+						"sgmii_tx250m", "sgmii_rx250m",
+						"sgmii_cdr_ref", "sgmii_cdr_fb",
+						"sgmii2_tx250m", "sgmii2_rx250m",
+						"sgmii2_cdr_ref", "sgmii2_cdr_fb",
+						"sgmii_ck", "netsys0", "netsys1";
+			assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
+					  <&topckgen CLK_TOP_SGM_325M_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_800M>,
+						 <&topckgen CLK_TOP_CB_SGM_325M>;
+			mediatek,ethsys = <&ethsys>;
+			mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
+			mediatek,infracfg = <&topmisc>;
+			mediatek,wed = <&wed>;
+			#reset-cells = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+
+			mdio_bus: mdio-bus {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				int_gbe_phy: ethernet-phy@0 {
+					compatible = "ethernet-phy-ieee802.3-c22";
+					reg = <0>;
+					phy-mode = "gmii";
+					phy-is-integrated;
+					nvmem-cells = <&phy_calibration>;
+					nvmem-cell-names = "phy-cal-data";
+
+					leds {
+						#address-cells = <1>;
+						#size-cells = <0>;
+
+						int_gbe_phy_led0: int-gbe-phy-led0@0 {
+							reg = <0>;
+							function = LED_FUNCTION_LAN;
+							status = "disabled";
+						};
+
+						int_gbe_phy_led1: int-gbe-phy-led1@1 {
+							reg = <1>;
+							function = LED_FUNCTION_LAN;
+							status = "disabled";
+						};
+					};
+				};
+			};
+		};
 
-	spi2: spi@11009000 {
-		compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0 0x11009000 0 0x100>;
-		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&topckgen CLK_TOP_CB_M_D2>,
-			 <&topckgen CLK_TOP_SPI_SEL>,
-			 <&infracfg CLK_INFRA_SPI2_CK>,
-			 <&infracfg CLK_INFRA_SPI2_HCK_CK>;
-		clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
-		status = "disabled";
-	};
+		wdma: wdma@15104800 {
+			compatible = "mediatek,wed-wdma";
+			reg = <0 0x15104800 0 0x400>,
+			      <0 0x15104c00 0 0x400>;
+		};
 
-	consys: consys@10000000 {
-		compatible = "mediatek,mt7981-consys";
-		reg = <0 0x10000000 0 0x8600000>;
-		memory-region = <&wmcpu_emi>;
-	};
+		wo_cpuboot: syscon@15194000 {
+			compatible = "mediatek,mt7986-wo-cpuboot", "syscon";
+			reg = <0 0x15194000 0 0x1000>;
+		};
 
-	xhci: usb@11200000 {
-		compatible = "mediatek,mt7986-xhci",
-			     "mediatek,mtk-xhci";
-		reg = <0 0x11200000 0 0x2e00>,
-		      <0 0x11203e00 0 0x0100>;
-		reg-names = "mac", "ippc";
-		interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
-			 <&infracfg CLK_INFRA_IUSB_CK>,
-			 <&infracfg CLK_INFRA_IUSB_133_CK>,
-			 <&infracfg CLK_INFRA_IUSB_66M_CK>,
-			 <&topckgen CLK_TOP_U2U3_XHCI_SEL>;
-		clock-names = "sys_ck",
-			      "ref_ck",
-			      "mcu_ck",
-			      "dma_ck",
-			      "xhci_ck";
-		phys = <&u2port0 PHY_TYPE_USB2>,
-		       <&u3port0 PHY_TYPE_USB3>;
-		vusb33-supply = <&reg_3p3v>;
-		status = "disabled";
-	};
+		ap2woccif: ap2woccif@151a5000 {
+			compatible = "mediatek,ap2woccif";
+			reg = <0 0x151a5000 0 0x1000>,
+			      <0 0x151ad000 0 0x1000>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
+		};
 
-	usb_phy: usb-phy@11e10000 {
-		compatible = "mediatek,mt7981",
-			     "mediatek,generic-tphy-v2";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0 0 0x11e10000 0x1700>;
-		status = "disabled";
+		wo_ccif0: syscon@151a5000 {
+			compatible = "mediatek,mt7986-wo-ccif", "syscon";
+			reg = <0 0x151a5000 0 0x1000>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
+		};
 
-		u2port0: usb-phy@0 {
-			reg = <0x0 0x700>;
-			clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>;
-			clock-names = "ref";
-			#phy-cells = <1>;
+		wo_ilm0: syscon@151e0000 {
+			compatible = "mediatek,mt7986-wo-ilm", "syscon";
+			reg = <0 0x151e0000 0 0x8000>;
 		};
 
-		u3port0: usb-phy@700 {
-			reg = <0x700 0x900>;
-			clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
-			clock-names = "ref";
-			#phy-cells = <1>;
-			mediatek,syscon-type = <&topmisc 0x218 0>;
-			status = "okay";
+		wo_dlm0: syscon@151e8000 {
+			compatible = "mediatek,mt7986-wo-dlm", "syscon";
+			reg = <0 0x151e8000 0 0x2000>;
 		};
-	};
 
-	reg_3p3v: regulator-3p3v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-3.3V";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		regulator-always-on;
+		wifi: wifi@18000000 {
+			compatible = "mediatek,mt7981-wmac";
+			reg = <0 0x18000000 0 0x1000000>,
+			      <0 0x10003000 0 0x1000>,
+			      <0 0x11d10000 0 0x1000>;
+			resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
+			reset-names = "consys";
+			pinctrl-0 = <&wifi_dbdc_pins>;
+			pinctrl-names = "dbdc";
+			clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>,
+				 <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
+			clock-names = "mcu", "ap2conn";
+			interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
+			memory-region = <&wmcpu_emi>;
+			status = "disabled";
+		};
 	};
 
-	efuse: efuse@11f20000 {
-		compatible = "mediatek,mt7981-efuse",
-			     "mediatek,efuse";
-		reg = <0 0x11f20000 0 0x1000>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		status = "okay";
+	thermal-zones {
+		cpu_thermal: cpu-thermal {
+			polling-delay-passive = <1000>;
+			polling-delay = <1000>;
+			thermal-sensors = <&thermal 0>;
 
-		thermal_calibration: thermal-calib@274 {
-			reg = <0x274 0xc>;
-		};
+			trips {
+				cpu_trip_active_highest: active-highest {
+					temperature = <70000>;
+					hysteresis = <2000>;
+					type = "active";
+				};
 
-		phy_calibration: phy-calib@8dc {
-			reg = <0x8dc 0x10>;
-		};
+				cpu_trip_active_high: active-high {
+					temperature = <60000>;
+					hysteresis = <2000>;
+					type = "active";
+				};
 
-		comb_rx_imp_p0: usb3-rx-imp@8c8 {
-			reg = <0x8c8 1>;
-			bits = <0 5>;
-		};
+				cpu_trip_active_med: active-med {
+					temperature = <50000>;
+					hysteresis = <2000>;
+					type = "active";
+				};
 
-		comb_tx_imp_p0: usb3-tx-imp@8c8 {
-			reg = <0x8c8 2>;
-			bits = <5 5>;
-		};
+				cpu_trip_active_low: active-low {
+					temperature = <45000>;
+					hysteresis = <2000>;
+					type = "active";
+				};
 
-		comb_intr_p0: usb3-intr@8c9 {
-			reg = <0x8c9 1>;
-			bits = <2 6>;
+				cpu_trip_active_lowest: active-lowest {
+					temperature = <40000>;
+					hysteresis = <2000>;
+					type = "active";
+				};
+			};
+
+			cooling-maps {
+				cpu-active-highest {
+					/* active: set fan to cooling level 7 */
+					cooling-device = <&fan 7 7>;
+					trip = <&cpu_trip_active_highest>;
+				};
+
+				cpu-active-high {
+					/* active: set fan to cooling level 5 */
+					cooling-device = <&fan 5 5>;
+					trip = <&cpu_trip_active_high>;
+				};
+
+				cpu-active-med {
+					/* active: set fan to cooling level 3 */
+					cooling-device = <&fan 3 3>;
+					trip = <&cpu_trip_active_med>;
+				};
+
+				cpu-active-low {
+					/* active: set fan to cooling level 2 */
+					cooling-device = <&fan 2 2>;
+					trip = <&cpu_trip_active_low>;
+				};
+
+				cpu-active-lowest {
+					/* active: set fan to cooling level 1 */
+					cooling-device = <&fan 1 1>;
+					trip = <&cpu_trip_active_lowest>;
+				};
+			};
 		};
 	};
 
-	afe: audio-controller@11210000 {
-		compatible = "mediatek,mt79xx-audio";
-		reg = <0 0x11210000 0 0x9000>;
-		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&infracfg CLK_INFRA_AUD_BUS_CK>,
-			 <&infracfg CLK_INFRA_AUD_26M_CK>,
-			 <&infracfg CLK_INFRA_AUD_L_CK>,
-			 <&infracfg CLK_INFRA_AUD_AUD_CK>,
-			 <&infracfg CLK_INFRA_AUD_EG2_CK>,
-			 <&topckgen CLK_TOP_AUD_SEL>;
-		clock-names = "aud_bus_ck",
-			      "aud_26m_ck",
-			      "aud_l_ck",
-			      "aud_aud_ck",
-			      "aud_eg2_ck",
-			      "aud_sel";
-		assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
-				  <&topckgen CLK_TOP_A1SYS_SEL>,
-				  <&topckgen CLK_TOP_AUD_L_SEL>,
-				  <&topckgen CLK_TOP_A_TUNER_SEL>;
-		assigned-clock-parents = <&topckgen CLK_TOP_CB_APLL2_196M>,
-					 <&topckgen CLK_TOP_APLL2_D4>,
-					 <&topckgen CLK_TOP_CB_APLL2_196M>,
-					 <&topckgen CLK_TOP_APLL2_D4>;
-		status = "disabled";
-	};
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupt-parent = <&gic>;
+		clock-frequency = <13000000>;
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 
-	ice: ice_debug {
-		compatible = "mediatek,mt7981-ice_debug",
-			   "mediatek,mt2701-ice_debug";
-		clocks = <&infracfg CLK_INFRA_DBG_CK>;
-		clock-names = "ice_dbg";
 	};
 
-	wifi: wifi@18000000 {
-		compatible = "mediatek,mt7981-wmac";
-		resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
-		reset-names = "consys";
-		pinctrl-0 = <&wifi_dbdc_pins>;
-		pinctrl-names = "dbdc";
-		clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>,
-			 <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
-		clock-names = "mcu", "ap2conn";
-		reg = <0 0x18000000 0 0x1000000>,
-		      <0 0x10003000 0 0x1000>,
-		      <0 0x11d10000 0 0x1000>;
-		interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
-		memory-region = <&wmcpu_emi>;
-		status = "disabled";
+	trng {
+		compatible = "mediatek,mt7981-rng";
 	};
 };
diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-emmc.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-emmc.dtso
new file mode 100644
index 00000000000000..4945185d699e85
--- /dev/null
+++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-emmc.dtso
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2021 MediaTek Inc.
+ * Author: Frank Wunderlich <frank-w@public-files.de>
+ */
+
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "bananapi,bpi-r4", "mediatek,mt7988a";
+
+	fragment@0 {
+		target-path = "/soc/mmc@11230000";
+		__overlay__ {
+			pinctrl-names = "default", "state_uhs";
+			pinctrl-0 = <&mmc0_pins_emmc_51>;
+			pinctrl-1 = <&mmc0_pins_emmc_51>;
+			bus-width = <8>;
+			max-frequency = <200000000>;
+			cap-mmc-highspeed;
+			mmc-hs200-1_8v;
+			mmc-hs400-1_8v;
+			hs400-ds-delay = <0x12814>;
+			vqmmc-supply = <&reg_1p8v>;
+			vmmc-supply = <&reg_3p3v>;
+			non-removable;
+			no-sd;
+			no-sdio;
+			status = "okay";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			card@0 {
+				compatible = "mmc-card";
+				reg = <0>;
+
+				block {
+					compatible = "block-device";
+					partitions {
+						block-partition-env {
+							partname = "ubootenv";
+							nvmem-layout {
+								compatible = "u-boot,env-layout";
+							};
+						};
+						emmc_rootfs: block-partition-production {
+							partname = "production";
+						};
+					};
+				};
+			};
+		};
+	};
+
+	fragment@2 {
+		target-path = "/chosen";
+		__overlay__ {
+			rootdisk-emmc = <&emmc_rootfs>;
+		};
+	};
+};
diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-rtc.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-rtc.dtso
new file mode 100644
index 00000000000000..39910b8cfee1a9
--- /dev/null
+++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-rtc.dtso
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023
+ * Author: Daniel Golle <daniel@makrotopia.org>
+ */
+
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "bananapi,bpi-r4", "mediatek,mt7988a";
+
+	fragment@0 {
+		target = <&pcf8563>;
+		__overlay__ {
+			status = "okay";
+		};
+	};
+};
diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-sd.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-sd.dtso
new file mode 100644
index 00000000000000..1f5e1491a471e9
--- /dev/null
+++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-sd.dtso
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 MediaTek Inc.
+ * Author: Frank Wunderlich <frank-w@public-files.de>
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	compatible = "bananapi,bpi-r4", "mediatek,mt7988a";
+
+	fragment@1 {
+		target-path = "/soc/mmc@11230000";
+		__overlay__ {
+			pinctrl-names = "default", "state_uhs";
+			pinctrl-0 = <&mmc0_pins_sdcard>;
+			pinctrl-1 = <&mmc0_pins_sdcard>;
+			cd-gpios = <&pio 12 GPIO_ACTIVE_LOW>;
+			bus-width = <4>;
+			max-frequency = <52000000>;
+			cap-sd-highspeed;
+			vmmc-supply = <&reg_3p3v>;
+			vqmmc-supply = <&reg_3p3v>;
+			no-mmc;
+			status = "okay";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			card@0 {
+				compatible = "mmc-card";
+				reg = <0>;
+
+				block {
+					compatible = "block-device";
+					partitions {
+						block-partition-env {
+							partname = "ubootenv";
+							nvmem-layout {
+								compatible = "u-boot,env-layout";
+							};
+						};
+						sd_rootfs: block-partition-production {
+							partname = "production";
+						};
+					};
+				};
+			};
+		};
+	};
+
+	fragment@2 {
+		target-path = "/chosen";
+		__overlay__ {
+			rootdisk-sd = <&sd_rootfs>;
+		};
+	};
+};
diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-wifi-mt7996a.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-wifi-mt7996a.dtso
new file mode 100644
index 00000000000000..8a029b149ff7cd
--- /dev/null
+++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-wifi-mt7996a.dtso
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	compatible = "bananapi,bpi-r4", "mediatek,mt7988a";
+
+	fragment@0 {
+		target-path = "/";
+		__overlay__ {
+			wifi_12v: regulator-wifi-12v {
+				compatible = "regulator-fixed";
+				regulator-name = "wifi";
+				regulator-min-microvolt = <12000000>;
+				regulator-max-microvolt = <12000000>;
+				gpio = <&pio 4 GPIO_ACTIVE_HIGH>;
+				enable-active-high;
+				regulator-always-on;
+			};
+		};
+	};
+
+	fragment@1 {
+		target = <&i2c_wifi>;
+		__overlay__ {
+			// 5G WIFI MAC Address EEPROM
+			wifi_eeprom@51 {
+				compatible = "atmel,24c02";
+				reg = <0x51>;
+				address-bits = <8>;
+				page-size = <8>;
+				size = <256>;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					macaddr_5g: macaddr@0 {
+						reg = <0x0 0x6>;
+					};
+				};
+			};
+
+			// 6G WIFI MAC Address EEPROM
+			wifi_eeprom@52 {
+				compatible = "atmel,24c02";
+				reg = <0x52>;
+				address-bits = <8>;
+				page-size = <8>;
+				size = <256>;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					macaddr_6g: macaddr@0 {
+						reg = <0x0 0x6>;
+					};
+				};
+			};
+		};
+	};
+
+	fragment@2 {
+		target = <&pcie0>;
+		__overlay__ {
+			pcie@0,0 {
+				reg = <0x0000 0 0 0 0>;
+
+				wifi@0,0 {
+					compatible = "mediatek,mt76";
+					reg = <0x0000 0 0 0 0>;
+					nvmem-cell-names = "mac-address";
+					nvmem-cells = <&macaddr_5g>;
+				};
+			};
+		};
+	};
+
+	fragment@3 {
+		target = <&pcie1>;
+		__overlay__ {
+			pcie@0,0 {
+				reg = <0x0000 0 0 0 0>;
+
+				wifi@0,0 {
+					compatible = "mediatek,mt76";
+					reg = <0x0000 0 0 0 0>;
+					nvmem-cell-names = "mac-address";
+					nvmem-cells = <&macaddr_6g>;
+				};
+			};
+		};
+	};
+};
diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
new file mode 100644
index 00000000000000..416958428f3c9c
--- /dev/null
+++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
@@ -0,0 +1,407 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Author: Sam.Shih <sam.shih@mediatek.com>
+ */
+
+/dts-v1/;
+#include "mt7988a.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/regulator/richtek,rt5190a-regulator.h>
+
+/ {
+	model = "Bananapi BPI-R4";
+	compatible = "bananapi,bpi-r4",
+		     "mediatek,mt7988";
+
+	aliases {
+		serial0 = &uart0;
+		led-boot = &led_green;
+		led-failsafe = &led_green;
+		led-running = &led_green;
+		led-upgrade = &led_green;
+	};
+
+	chosen {
+		stdout-path = &uart0;
+		bootargs = "console=ttyS0,115200n1 loglevel=8 pci=pcie_bus_perf ubi.block=0,fit root=/dev/fit0";
+		rootdisk-spim-nand = <&ubi_rootfs>;
+	};
+
+	memory {
+		reg = <0x00 0x40000000 0x00 0x10000000>;
+	};
+
+	/* SFP1 cage (WAN) */
+	sfp1: sfp1 {
+		compatible = "sff,sfp";
+		i2c-bus = <&i2c_sfp1>;
+		los-gpios = <&pio 54 GPIO_ACTIVE_HIGH>;
+		mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>;
+		tx-disable-gpios = <&pio 70 GPIO_ACTIVE_HIGH>;
+		tx-fault-gpios = <&pio 69 GPIO_ACTIVE_HIGH>;
+		rate-select0-gpios = <&pio 21 GPIO_ACTIVE_LOW>;
+		maximum-power-milliwatt = <3000>;
+	};
+
+	/* SFP2 cage (LAN) */
+	sfp2: sfp2 {
+		compatible = "sff,sfp";
+		i2c-bus = <&i2c_sfp2>;
+		los-gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
+		mod-def0-gpios = <&pio 83 GPIO_ACTIVE_LOW>;
+		tx-disable-gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
+		tx-fault-gpios = <&pio 1 GPIO_ACTIVE_HIGH>;
+		rate-select0-gpios = <&pio 3 GPIO_ACTIVE_LOW>;
+		maximum-power-milliwatt = <3000>;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		wps {
+			label = "WPS";
+			linux,code = <KEY_RESTART>;
+			gpios = <&pio 14 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		led_green: led-green {
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&pio 79 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		led_blue: led-blue {
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
+			gpios = <&pio 63 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+	};
+};
+
+&eth {
+	status = "okay";
+};
+
+&gmac0 {
+	status = "okay";
+};
+
+&gmac1 {
+	sfp = <&sfp2>;
+	managed = "in-band-status";
+	phy-mode = "usxgmii";
+	status = "okay";
+};
+
+&gmac2 {
+	sfp = <&sfp1>;
+	managed = "in-band-status";
+	phy-mode = "usxgmii";
+	status = "okay";
+};
+
+&switch {
+	status = "okay";
+};
+
+&gsw_phy0 {
+	pinctrl-names = "gbe-led";
+	pinctrl-0 = <&gbe0_led0_pins>;
+};
+
+&gsw_port0 {
+	label = "wan";
+};
+
+&gsw_phy0_led0 {
+	status = "okay";
+	color = <LED_COLOR_ID_GREEN>;
+};
+
+&gsw_phy1 {
+	pinctrl-names = "gbe-led";
+	pinctrl-0 = <&gbe1_led0_pins>;
+};
+
+&gsw_phy1_led0 {
+	status = "okay";
+	color = <LED_COLOR_ID_GREEN>;
+};
+
+&gsw_phy2 {
+	pinctrl-names = "gbe-led";
+	pinctrl-0 = <&gbe2_led0_pins>;
+};
+
+&gsw_phy2_led0 {
+	status = "okay";
+	color = <LED_COLOR_ID_GREEN>;
+};
+
+&gsw_phy3 {
+	pinctrl-names = "gbe-led";
+	pinctrl-0 = <&gbe3_led0_pins>;
+};
+
+&gsw_phy3_led0 {
+	status = "okay";
+	color = <LED_COLOR_ID_GREEN>;
+};
+
+&cpu0 {
+	proc-supply = <&rt5190_buck3>;
+};
+
+&cpu1 {
+	proc-supply = <&rt5190_buck3>;
+};
+
+&cpu2 {
+	proc-supply = <&rt5190_buck3>;
+};
+
+&cpu3 {
+	proc-supply = <&rt5190_buck3>;
+};
+
+&cci {
+	proc-supply = <&rt5190_buck3>;
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0_pins>;
+	status = "okay";
+
+	rt5190a_64: rt5190a@64 {
+		compatible = "richtek,rt5190a";
+		reg = <0x64>;
+		vin2-supply = <&rt5190_buck1>;
+		vin3-supply = <&rt5190_buck1>;
+		vin4-supply = <&rt5190_buck1>;
+
+		regulators {
+			rt5190_buck1: buck1 {
+				regulator-name = "rt5190a-buck1";
+				regulator-min-microvolt = <5090000>;
+				regulator-max-microvolt = <5090000>;
+				regulator-allowed-modes =
+				<RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			buck2 {
+				regulator-name = "vcore";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <1400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			rt5190_buck3: buck3 {
+				regulator-name = "vproc";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <1400000>;
+				regulator-boot-on;
+			};
+			buck4 {
+				regulator-name = "rt5190a-buck4";
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+				regulator-allowed-modes =
+				<RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			ldo {
+				regulator-name = "rt5190a-ldo";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&i2c2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c2_1_pins>;
+	status = "okay";
+
+	pca9545: i2c-switch@70 {
+		reg = <0x70>;
+		compatible = "nxp,pca9545";
+		reset-gpios = <&pio 5 GPIO_ACTIVE_LOW>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		i2c_rtc: i2c@0 { //eeprom,rtc,ngff
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+
+			eeprom@50 {
+				compatible = "atmel,24c02";
+				reg = <0x50>;
+				address-bits = <8>;
+				page-size = <8>;
+				size = <256>;
+			};
+
+			eeprom@57 {
+				compatible = "atmel,24c02";
+				reg = <0x57>;
+				address-bits = <8>;
+				page-size = <8>;
+				size = <256>;
+			};
+
+			pcf8563: rtc@51 {
+				compatible = "nxp,pcf8563";
+				reg = <0x51>;
+				status = "disabled";
+			};
+		};
+
+		i2c_sfp1: i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+		};
+
+		i2c_sfp2: i2c@2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <2>;
+		};
+
+		i2c_wifi: i2c@3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <3>;
+		};
+	};
+};
+
+/* mPCIe SIM2 */
+&pcie0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie0_pins>;
+	status = "okay";
+};
+
+/* mPCIe SIM3 */
+&pcie1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie1_pins>;
+	status = "okay";
+};
+
+/* M.2 key-B SIM1 */
+&pcie2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie2_pins>;
+	status = "okay";
+};
+
+/* M.2 key-M SSD */
+&pcie3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie3_pins>;
+	status = "okay";
+};
+
+&ssusb1 {
+	status = "okay";
+};
+
+&tphy {
+	status = "okay";
+};
+
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0_flash_pins>;
+	status = "okay";
+
+	spi_nand: spi_nand@0 {
+		compatible = "spi-nand";
+		reg = <0>;
+		spi-max-frequency = <52000000>;
+		spi-tx-buswidth = <4>;
+		spi-rx-buswidth = <4>;
+	};
+};
+
+&spi_nand {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			label = "bl2";
+			reg = <0x0 0x200000>;
+			read-only;
+		};
+
+		partition@200000 {
+			label = "ubi";
+			reg = <0x200000 0x7e00000>;
+			compatible = "linux,ubi";
+
+			volumes {
+				ubi-volume-ubootenv {
+					volname = "ubootenv";
+					nvmem-layout {
+						compatible = "u-boot,env-redundant-bool-layout";
+					};
+				};
+
+				ubi-volume-ubootenv2 {
+					volname = "ubootenv2";
+					nvmem-layout {
+						compatible = "u-boot,env-redundant-bool-layout";
+					};
+				};
+
+				ubi_rootfs: ubi-volume-fit {
+					volname = "fit";
+				};
+			};
+		};
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1_2_lite_pins>;
+};
+
+&uart2 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart2_3_pins>;
+};
+
+&watchdog {
+	status = "okay";
+};
+
+&xphy {
+	status = "okay";
+};
diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
index bda50936f2a839..904339335f3c15 100644
--- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -10,9 +10,18 @@
 #include <dt-bindings/leds/common.h>
 #include <dt-bindings/phy/phy.h>
 #include <dt-bindings/pinctrl/mt65xx.h>
-#include <dt-bindings/reset/ti-syscon.h>
+#include <dt-bindings/reset/mediatek,mt7988-resets.h>
 #include <dt-bindings/thermal/thermal.h>
 
+/* TOPRGU resets */
+#define MT7988_TOPRGU_SGMII0_GRST		1
+#define MT7988_TOPRGU_SGMII1_GRST		2
+#define MT7988_TOPRGU_XFI0_GRST			12
+#define MT7988_TOPRGU_XFI1_GRST			13
+#define MT7988_TOPRGU_XFI_PEXTP0_GRST		14
+#define MT7988_TOPRGU_XFI_PEXTP1_GRST		15
+#define MT7988_TOPRGU_XFI_PLL_GRST		16
+
 / {
 	compatible = "mediatek,mt7988";
 	interrupt-parent = <&gic>;
@@ -31,11 +40,12 @@
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
+
 		cpu0: cpu@0 {
-			device_type = "cpu";
 			compatible = "arm,cortex-a73";
-			enable-method = "psci";
 			reg = <0x0>;
+			device_type = "cpu";
+			enable-method = "psci";
 			clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
 				 <&topckgen CLK_TOP_XTAL>;
 			clock-names = "cpu", "intermediate";
@@ -44,10 +54,10 @@
 		};
 
 		cpu1: cpu@1 {
-			device_type = "cpu";
 			compatible = "arm,cortex-a73";
-			enable-method = "psci";
 			reg = <0x1>;
+			device_type = "cpu";
+			enable-method = "psci";
 			clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
 				 <&topckgen CLK_TOP_XTAL>;
 			clock-names = "cpu", "intermediate";
@@ -56,10 +66,10 @@
 		};
 
 		cpu2: cpu@2 {
-			device_type = "cpu";
 			compatible = "arm,cortex-a73";
-			enable-method = "psci";
 			reg = <0x2>;
+			device_type = "cpu";
+			enable-method = "psci";
 			clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
 				 <&topckgen CLK_TOP_XTAL>;
 			clock-names = "cpu", "intermediate";
@@ -68,10 +78,10 @@
 		};
 
 		cpu3: cpu@3 {
-			device_type = "cpu";
 			compatible = "arm,cortex-a73";
-			enable-method = "psci";
 			reg = <0x3>;
+			device_type = "cpu";
+			enable-method = "psci";
 			clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
 				 <&topckgen CLK_TOP_XTAL>;
 			clock-names = "cpu", "intermediate";
@@ -82,18 +92,22 @@
 		cluster0_opp: opp_table0 {
 			compatible = "operating-points-v2";
 			opp-shared;
+
 			opp00 {
 				opp-hz = /bits/ 64 <800000000>;
 				opp-microvolt = <850000>;
 			};
+
 			opp01 {
 				opp-hz = /bits/ 64 <1100000000>;
 				opp-microvolt = <850000>;
 			};
+
 			opp02 {
 				opp-hz = /bits/ 64 <1500000000>;
 				opp-microvolt = <850000>;
 			};
+
 			opp03 {
 				opp-hz = /bits/ 64 <1800000000>;
 				opp-microvolt = <900000>;
@@ -104,18 +118,22 @@
 	cci_opp: opp_table_cci {
 		compatible = "operating-points-v2";
 		opp-shared;
+
 		opp00 {
 			opp-hz = /bits/ 64 <480000000>;
 			opp-microvolt = <850000>;
 		};
+
 		opp01 {
 			opp-hz = /bits/ 64 <660000000>;
 			opp-microvolt = <850000>;
 		};
+
 		opp02 {
 			opp-hz = /bits/ 64 <900000000>;
 			opp-microvolt = <850000>;
 		};
+
 		opp03 {
 			opp-hz = /bits/ 64 <1080000000>;
 			opp-microvolt = <900000>;
@@ -129,6 +147,15 @@
 		clock-output-names = "clkxtal";
 	};
 
+	fan: pwm-fan {
+		compatible = "pwm-fan";
+		/* cooling level (0, 1, 2) : (0% duty, 50% duty, 100% duty) */
+		cooling-levels = <0 128 255>;
+		#cooling-cells = <2>;
+		#thermal-sensor-cells = <1>;
+		status = "disabled";
+	};
+
 	pmu {
 		compatible = "arm,cortex-a73-pmu";
 		interrupt-parent = <&gic>;
@@ -136,8 +163,8 @@
 	};
 
 	psci {
-		compatible  = "arm,psci-0.2";
-		method      = "smc";
+		compatible = "arm,psci-0.2";
+		method = "smc";
 	};
 
 	reg_1p8v: regulator-1p8v {
@@ -159,9 +186,9 @@
 	};
 
 	reserved-memory {
+		ranges;
 		#address-cells = <2>;
 		#size-cells = <2>;
-		ranges;
 
 		/* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */
 		secmon_reserved: secmon@43000000 {
@@ -171,36 +198,35 @@
 	};
 
 	soc {
-		#address-cells = <2>;
-		#size-cells = <2>;
 		compatible = "simple-bus";
 		ranges;
+		#address-cells = <2>;
+		#size-cells = <2>;
 
 		gic: interrupt-controller@c000000 {
 			compatible = "arm,gic-v3";
-			#interrupt-cells = <3>;
-			interrupt-parent = <&gic>;
-			interrupt-controller;
 			reg = <0 0x0c000000 0 0x40000>,  /* GICD */
 			      <0 0x0c080000 0 0x200000>, /* GICR */
 			      <0 0x0c400000 0 0x2000>,   /* GICC */
 			      <0 0x0c410000 0 0x1000>,   /* GICH */
 			      <0 0x0c420000 0 0x2000>;   /* GICV */
-
+			interrupt-parent = <&gic>;
 			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
 		};
 
 		phyfw: phy-firmware@f000000 {
 			compatible = "mediatek,2p5gphy-fw";
-			reg = <0 0x0f000000 0 0x8000>,
-			      <0 0x0f100000 0 0x20000>,
-			      <0 0x0f0f0000 0 0x200>;
+			reg = <0 0x0f100000 0 0x20000>,
+			      <0 0x0f0f0018 0 0x20>;
 		};
 
 		infracfg: infracfg@10001000 {
 			compatible = "mediatek,mt7988-infracfg", "syscon";
 			reg = <0 0x10001000 0 0x1000>;
 			#clock-cells = <1>;
+			#reset-cells = <1>;
 		};
 
 		topckgen: topckgen@1001b000 {
@@ -227,12 +253,12 @@
 		pio: pinctrl@1001f000 {
 			compatible = "mediatek,mt7988-pinctrl", "syscon";
 			reg = <0 0x1001f000 0 0x1000>,
-			<0 0x11c10000 0 0x1000>,
-			<0 0x11d00000 0 0x1000>,
-			<0 0x11d20000 0 0x1000>,
-			<0 0x11e00000 0 0x1000>,
-			<0 0x11f00000 0 0x1000>,
-			<0 0x1000b000 0 0x1000>;
+			      <0 0x11c10000 0 0x1000>,
+			      <0 0x11d00000 0 0x1000>,
+			      <0 0x11d20000 0 0x1000>,
+			      <0 0x11e00000 0 0x1000>,
+			      <0 0x11f00000 0 0x1000>,
+			      <0 0x1000b000 0 0x1000>;
 			reg-names = "gpio_base", "iocfg_tr_base",
 				    "iocfg_br_base", "iocfg_rb_base",
 				    "iocfg_lb_base", "iocfg_tl_base", "eint";
@@ -396,6 +422,69 @@
 				};
 			};
 
+			uart1_0_pins: uart1-0-pins {
+				mux {
+					function = "uart";
+					groups =  "uart1_0";
+				};
+			};
+
+			uart1_1_pins: uart1-1-pins {
+				mux {
+					function = "uart";
+					groups =  "uart1_1";
+				};
+			};
+
+			uart1_2_pins: uart1-2-pins {
+				mux {
+					function = "uart";
+					groups =  "uart1_2";
+				};
+			};
+
+			uart1_2_lite_pins: uart1-2-lite-pins {
+				mux {
+					function = "uart";
+					groups =  "uart1_2_lite";
+				};
+			};
+
+			uart2_pins: uart2-pins {
+				mux {
+					function = "uart";
+					groups =  "uart2";
+				};
+			};
+
+			uart2_0_pins: uart2-0-pins {
+				mux {
+					function = "uart";
+					groups =  "uart2_0";
+				};
+			};
+
+			uart2_1_pins: uart2-1-pins {
+				mux {
+					function = "uart";
+					groups =  "uart2_1";
+				};
+			};
+
+			uart2_2_pins: uart2-2-pins {
+				mux {
+					function = "uart";
+					groups =  "uart2_2";
+				};
+			};
+
+			uart2_3_pins: uart2-3-pins {
+				mux {
+					function = "uart";
+					groups =  "uart2_3";
+				};
+			};
+
 			snfi_pins: snfi-pins {
 				mux {
 					function = "flash";
@@ -492,34 +581,52 @@
 
 		sgmiisys0: syscon@10060000 {
 			compatible = "mediatek,mt7988-sgmiisys",
-				     "mediatek,mt7988-sgmiisys_0",
-				     "syscon";
+				     "mediatek,mt7988-sgmiisys0",
+				     "syscon",
+				     "simple-mfd";
 			reg = <0 0x10060000 0 0x1000>;
+			resets = <&watchdog MT7988_TOPRGU_SGMII0_GRST>;
 			#clock-cells = <1>;
+
+			sgmiipcs0: pcs {
+				compatible = "mediatek,mt7988-sgmii";
+				clocks = <&topckgen CLK_TOP_SGM_0_SEL>,
+					 <&sgmiisys0 CLK_SGM0_TX_EN>,
+					 <&sgmiisys0 CLK_SGM0_RX_EN>;
+				clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx";
+			};
 		};
 
 		sgmiisys1: syscon@10070000 {
 			compatible = "mediatek,mt7988-sgmiisys",
-				     "mediatek,mt7988-sgmiisys_1",
-				     "syscon";
+				     "mediatek,mt7988-sgmiisys1",
+				     "syscon",
+				     "simple-mfd";
 			reg = <0 0x10070000 0 0x1000>;
+			resets = <&watchdog MT7988_TOPRGU_SGMII1_GRST>;
 			#clock-cells = <1>;
+
+			sgmiipcs1: pcs {
+				compatible = "mediatek,mt7988-sgmii";
+				clocks = <&topckgen CLK_TOP_SGM_1_SEL>,
+					 <&sgmiisys1 CLK_SGM1_TX_EN>,
+					 <&sgmiisys1 CLK_SGM1_RX_EN>;
+				clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx";
+			};
 		};
 
-		usxgmiisys0: usxgmiisys@10080000 {
-			compatible = "mediatek,mt7988-usxgmiisys",
-				     "mediatek,mt7988-usxgmiisys_0",
-				     "syscon";
+		usxgmiisys0: pcs@10080000 {
+			compatible = "mediatek,mt7988-usxgmiisys";
 			reg = <0 0x10080000 0 0x1000>;
-			#clock-cells = <1>;
+			resets = <&watchdog MT7988_TOPRGU_XFI0_GRST>;
+			clocks = <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>;
 		};
 
-		usxgmiisys1: usxgmiisys@10081000 {
-			compatible = "mediatek,mt7988-usxgmiisys",
-				     "mediatek,mt7988-usxgmiisys_1",
-				     "syscon";
+		usxgmiisys1: pcs@10081000 {
+			compatible = "mediatek,mt7988-usxgmiisys";
 			reg = <0 0x10081000 0 0x1000>;
-			#clock-cells = <1>;
+			resets = <&watchdog MT7988_TOPRGU_XFI1_GRST>;
+			clocks = <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>;
 		};
 
 		mcusys: mcusys@100e0000 {
@@ -550,6 +657,46 @@
 			status = "disabled";
 		};
 
+		uart1: serial@11000100 {
+			compatible = "mediatek,mt7986-uart",
+				     "mediatek,mt6577-uart";
+			reg = <0 0x11000100 0 0x100>;
+			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+			/*
+			 * 8250-mtk driver don't control "baud" clock since commit
+			 * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks
+			 * still need to be passed to the driver to prevent probe fail
+			 */
+			clocks = <&topckgen CLK_TOP_UART_SEL>,
+				 <&infracfg CLK_INFRA_52M_UART1_CK>;
+			clock-names = "baud", "bus";
+			assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
+					  <&infracfg CLK_INFRA_MUX_UART1_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
+						 <&topckgen CLK_TOP_UART_SEL>;
+			status = "disabled";
+		};
+
+		uart2: serial@11000200 {
+			compatible = "mediatek,mt7986-uart",
+				     "mediatek,mt6577-uart";
+			reg = <0 0x11000200 0 0x100>;
+			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+			/*
+			 * 8250-mtk driver don't control "baud" clock since commit
+			 * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks
+			 * still need to be passed to the driver to prevent probe fail
+			 */
+			clocks = <&topckgen CLK_TOP_UART_SEL>,
+				 <&infracfg CLK_INFRA_52M_UART2_CK>;
+			clock-names = "baud", "bus";
+			assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
+					  <&infracfg CLK_INFRA_MUX_UART2_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
+						 <&topckgen CLK_TOP_UART_SEL>;
+			status = "disabled";
+		};
+
 		snand: spi@11001000 {
 			compatible = "mediatek,mt7986-snand";
 			reg = <0 0x11001000 0 0x1000>;
@@ -671,23 +818,16 @@
 			status = "disabled";
 		};
 
-		fan: pwm-fan {
-			compatible = "pwm-fan";
-			/* cooling level (0, 1, 2) : (0% duty, 50% duty, 100% duty) */
-			cooling-levels = <0 128 255>;
-			#cooling-cells = <2>;
-			#thermal-sensor-cells = <1>;
-			status = "disabled";
-		};
-
 		lvts: lvts@1100a000 {
-			compatible = "mediatek,mt7988-lvts";
-			#thermal-sensor-cells = <1>;
+			compatible = "mediatek,mt7988-lvts-ap";
 			reg = <0 0x1100a000 0 0x1000>;
 			clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>;
 			clock-names = "lvts_clk";
+			interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+			resets = <&infracfg MT7988_INFRA_RST1_THERM_CTRL_SWRST>;
 			nvmem-cells = <&lvts_calibration>;
-			nvmem-cell-names = "e_data1";
+			nvmem-cell-names = "lvts-calib-data-1";
+			#thermal-sensor-cells = <1>;
 		};
 
 		ssusb0: usb@11190000 {
@@ -795,18 +935,16 @@
 			compatible = "mediatek,mt7988-pcie",
 				     "mediatek,mt7986-pcie",
 				     "mediatek,mt8192-pcie";
-			device_type = "pci";
-			#address-cells = <3>;
-			#size-cells = <2>;
 			reg = <0 0x11280000 0 0x2000>;
 			reg-names = "pcie-mac";
-			linux,pci-domain = <3>;
-			interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
-			bus-range = <0x00 0xff>;
 			ranges = <0x81000000 0x00 0x20000000 0x00
 				  0x20000000 0x00 0x00200000>,
 				 <0x82000000 0x00 0x20200000 0x00
 				  0x20200000 0x00 0x07e00000>;
+			device_type = "pci";
+			linux,pci-domain = <3>;
+			interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+			bus-range = <0x00 0xff>;
 			clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>,
 				 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>,
 				 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>,
@@ -815,17 +953,18 @@
 				      "top_133m";
 			pinctrl-names = "default";
 			pinctrl-0 = <&pcie2_pins>;
-			status = "disabled";
-
 			phys = <&xphyu3port0 PHY_TYPE_PCIE>;
 			phy-names = "pcie-phy";
-
 			#interrupt-cells = <1>;
 			interrupt-map-mask = <0 0 0 0x7>;
 			interrupt-map = <0 0 0 1 &pcie_intc2 0>,
 					<0 0 0 2 &pcie_intc2 1>,
 					<0 0 0 3 &pcie_intc2 2>,
 					<0 0 0 4 &pcie_intc2 3>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			status = "disabled";
+
 			pcie_intc2: interrupt-controller {
 				#address-cells = <0>;
 				#interrupt-cells = <1>;
@@ -837,18 +976,16 @@
 			compatible = "mediatek,mt7988-pcie",
 				     "mediatek,mt7986-pcie",
 				     "mediatek,mt8192-pcie";
-			device_type = "pci";
-			#address-cells = <3>;
-			#size-cells = <2>;
 			reg = <0 0x11290000 0 0x2000>;
 			reg-names = "pcie-mac";
-			linux,pci-domain = <2>;
-			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
-			bus-range = <0x00 0xff>;
 			ranges = <0x81000000 0x00 0x28000000 0x00
 				  0x28000000 0x00 0x00200000>,
 				 <0x82000000 0x00 0x28200000 0x00
 				  0x28200000 0x00 0x07e00000>;
+			device_type = "pci";
+			linux,pci-domain = <2>;
+			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+			bus-range = <0x00 0xff>;
 			clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>,
 				 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>,
 				 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>,
@@ -857,14 +994,16 @@
 				      "top_133m";
 			pinctrl-names = "default";
 			pinctrl-0 = <&pcie3_pins>;
-			status = "disabled";
-
 			#interrupt-cells = <1>;
 			interrupt-map-mask = <0 0 0 0x7>;
 			interrupt-map = <0 0 0 1 &pcie_intc3 0>,
 					<0 0 0 2 &pcie_intc3 1>,
 					<0 0 0 3 &pcie_intc3 2>,
 					<0 0 0 4 &pcie_intc3 3>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			status = "disabled";
+
 			pcie_intc3: interrupt-controller {
 				#address-cells = <0>;
 				#interrupt-cells = <1>;
@@ -876,18 +1015,16 @@
 			compatible = "mediatek,mt7988-pcie",
 				     "mediatek,mt7986-pcie",
 				     "mediatek,mt8192-pcie";
-			device_type = "pci";
-			#address-cells = <3>;
-			#size-cells = <2>;
 			reg = <0 0x11300000 0 0x2000>;
 			reg-names = "pcie-mac";
-			linux,pci-domain = <0>;
-			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
-			bus-range = <0x00 0xff>;
 			ranges = <0x81000000 0x00 0x30000000 0x00
 				  0x30000000 0x00 0x00200000>,
 				 <0x82000000 0x00 0x30200000 0x00
 				  0x30200000 0x00 0x07e00000>;
+			device_type = "pci";
+			linux,pci-domain = <0>;
+			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+			bus-range = <0x00 0xff>;
 			clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>,
 				 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>,
 				 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>,
@@ -896,14 +1033,16 @@
 				      "top_133m";
 			pinctrl-names = "default";
 			pinctrl-0 = <&pcie0_pins>;
-			status = "disabled";
-
 			#interrupt-cells = <1>;
 			interrupt-map-mask = <0 0 0 0x7>;
 			interrupt-map = <0 0 0 1 &pcie_intc0 0>,
 					<0 0 0 2 &pcie_intc0 1>,
 					<0 0 0 3 &pcie_intc0 2>,
 					<0 0 0 4 &pcie_intc0 3>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			status = "disabled";
+
 			pcie_intc0: interrupt-controller {
 				#address-cells = <0>;
 				#interrupt-cells = <1>;
@@ -915,18 +1054,16 @@
 			compatible = "mediatek,mt7988-pcie",
 				     "mediatek,mt7986-pcie",
 				     "mediatek,mt8192-pcie";
-			device_type = "pci";
-			#address-cells = <3>;
-			#size-cells = <2>;
 			reg = <0 0x11310000 0 0x2000>;
 			reg-names = "pcie-mac";
-			linux,pci-domain = <1>;
-			interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
-			bus-range = <0x00 0xff>;
 			ranges = <0x81000000 0x00 0x38000000 0x00
 				  0x38000000 0x00 0x00200000>,
 				 <0x82000000 0x00 0x38200000 0x00
 				  0x38200000 0x00 0x07e00000>;
+			device_type = "pci";
+			linux,pci-domain = <1>;
+			interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+			bus-range = <0x00 0xff>;
 			clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>,
 				 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>,
 				 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>,
@@ -935,14 +1072,16 @@
 				      "top_133m";
 			pinctrl-names = "default";
 			pinctrl-0 = <&pcie1_pins>;
-			status = "disabled";
-
 			#interrupt-cells = <1>;
 			interrupt-map-mask = <0 0 0 0x7>;
 			interrupt-map = <0 0 0 1 &pcie_intc1 0>,
 					<0 0 0 2 &pcie_intc1 1>,
 					<0 0 0 3 &pcie_intc1 2>,
 					<0 0 0 4 &pcie_intc1 3>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			status = "disabled";
+
 			pcie_intc1: interrupt-controller {
 				#address-cells = <0>;
 				#interrupt-cells = <1>;
@@ -953,16 +1092,18 @@
 		tphy: tphy@11c50000 {
 			compatible = "mediatek,mt7988",
 				     "mediatek,generic-tphy-v2";
+			ranges;
 			#address-cells = <2>;
 			#size-cells = <2>;
-			ranges;
 			status = "disabled";
+
 			tphyu2port0: usb-phy@11c50000 {
 				reg = <0 0x11c50000 0 0x700>;
 				clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>;
 				clock-names = "ref";
 				#phy-cells = <1>;
 			};
+
 			tphyu3port0: usb-phy@11c50700 {
 				reg = <0 0x11c50700 0 0x900>;
 				clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>;
@@ -986,9 +1127,9 @@
 		xphy: xphy@11e10000 {
 			compatible = "mediatek,mt7988",
 				     "mediatek,xsphy";
+			ranges;
 			#address-cells = <2>;
 			#size-cells = <2>;
-			ranges;
 			status = "disabled";
 
 			xphyu2port0: usb-phy@11e10000 {
@@ -1007,25 +1148,29 @@
 			};
 		};
 
-		xfi_pextp0: xfi-pextp@11f20000 {
-			compatible = "mediatek,mt7988-xfi-pextp",
-				     "mediatek,mt7988-xfi-pextp_0",
-				     "syscon";
+		xfi_tphy0: phy@11f20000 {
+			compatible = "mediatek,mt7988-xfi-tphy";
 			reg = <0 0x11f20000 0 0x10000>;
-			#clock-cells = <1>;
+			resets = <&watchdog MT7988_TOPRGU_XFI_PEXTP0_GRST>;
+			clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>;
+			clock-names = "xfipll", "topxtal";
+			mediatek,usxgmii-performance-errata;
+			#phy-cells = <0>;
 		};
 
-		xfi_pextp1: xfi-pextp@11f30000 {
-			compatible = "mediatek,mt7988-xfi-pextp",
-				     "mediatek,mt7988-xfi-pextp_1",
-				     "syscon";
+		xfi_tphy1: phy@11f30000 {
+			compatible = "mediatek,mt7988-xfi-tphy";
 			reg = <0 0x11f30000 0 0x10000>;
-			#clock-cells = <1>;
+			resets = <&watchdog MT7988_TOPRGU_XFI_PEXTP1_GRST>;
+			clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>;
+			clock-names = "xfipll", "topxtal";
+			#phy-cells = <0>;
 		};
 
-		xfi_pll: xfi-pll@11f40000 {
-			compatible = "mediatek,mt7988-xfi-pll", "syscon";
+		xfi_pll: clock-controller@11f40000 {
+			compatible = "mediatek,mt7988-xfi-pll";
 			reg = <0 0x11f40000 0 0x1000>;
+			resets = <&watchdog MT7988_TOPRGU_XFI_PLL_GRST>;
 			#clock-cells = <1>;
 		};
 
@@ -1038,69 +1183,74 @@
 			lvts_calibration: calib@918 {
 				reg = <0x918 0x28>;
 			};
+
 			phy_calibration_p0: calib@940 {
 				reg = <0x940 0x10>;
 			};
+
 			phy_calibration_p1: calib@954 {
 				reg = <0x954 0x10>;
 			};
+
 			phy_calibration_p2: calib@968 {
 				reg = <0x968 0x10>;
 			};
+
 			phy_calibration_p3: calib@97c {
 				reg = <0x97c 0x10>;
 			};
+
 			cpufreq_calibration: calib@278 {
 				reg = <0x278 0x1>;
 			};
 		};
 
 		ethsys: syscon@15000000 {
-			#address-cells = <1>;
-			#size-cells = <1>;
 			compatible = "mediatek,mt7988-ethsys", "syscon";
 			reg = <0 0x15000000 0 0x1000>;
 			#clock-cells = <1>;
 			#reset-cells = <1>;
+			#address-cells = <1>;
+			#size-cells = <1>;
 		};
 
 		switch: switch@15020000 {
-			#address-cells = <1>;
-			#size-cells = <1>;
 			compatible = "mediatek,mt7988-switch";
 			reg = <0 0x15020000 0 0x8000>;
 			interrupt-controller;
 			#interrupt-cells = <1>;
 			interrupt-parent = <&gic>;
 			interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
-			resets = <&ethrst 0>;
+			resets = <&ethwarp MT7988_ETHWARP_RST_SWITCH>;
+			#address-cells = <1>;
+			#size-cells = <1>;
 
 			ports {
 				#address-cells = <1>;
 				#size-cells = <0>;
 
-				port@0 {
+				gsw_port0: port@0 {
 					reg = <0>;
 					label = "lan0";
 					phy-mode = "internal";
 					phy-handle = <&gsw_phy0>;
 				};
 
-				port@1 {
+				gsw_port1: port@1 {
 					reg = <1>;
 					label = "lan1";
 					phy-mode = "internal";
 					phy-handle = <&gsw_phy1>;
 				};
 
-				port@2 {
+				gsw_port2: port@2 {
 					reg = <2>;
 					label = "lan2";
 					phy-mode = "internal";
 					phy-handle = <&gsw_phy2>;
 				};
 
-				port@3 {
+				gsw_port3: port@3 {
 					reg = <3>;
 					label = "lan3";
 					phy-mode = "internal";
@@ -1227,18 +1377,11 @@
 			};
 		};
 
-		ethwarp: syscon@15031000 {
-			compatible = "mediatek,mt7988-ethwarp", "syscon", "simple-mfd";
+		ethwarp: clock-controller@15031000 {
+			compatible = "mediatek,mt7988-ethwarp";
 			reg = <0 0x15031000 0 0x1000>;
 			#clock-cells = <1>;
-
-			ethrst: reset-controller {
-				compatible = "ti,syscon-reset";
-				#reset-cells = <1>;
-				ti,reset-bits = <
-					0x8 9 0x8 9 0 0 (ASSERT_SET | DEASSERT_CLEAR | STATUS_NONE)
-				>;
-			};
+			#reset-cells = <1>;
 		};
 
 		eth: ethernet@15100000 {
@@ -1258,19 +1401,9 @@
 				 <&ethsys CLK_ETHDMA_GP3_EN>,
 				 <&ethsys CLK_ETHDMA_ESW_EN>,
 				 <&ethsys CLK_ETHDMA_CRYPT0_EN>,
-				 <&sgmiisys0 CLK_SGM0_TX_EN>,
-				 <&sgmiisys0 CLK_SGM0_RX_EN>,
-				 <&sgmiisys1 CLK_SGM1_TX_EN>,
-				 <&sgmiisys1 CLK_SGM1_RX_EN>,
 				 <&ethwarp CLK_ETHWARP_WOCPU2_EN>,
 				 <&ethwarp CLK_ETHWARP_WOCPU1_EN>,
 				 <&ethwarp CLK_ETHWARP_WOCPU0_EN>,
-				 <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
-				 <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
-				 <&topckgen CLK_TOP_SGM_0_SEL>,
-				 <&topckgen CLK_TOP_SGM_1_SEL>,
-				 <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>,
-				 <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>,
 				 <&topckgen CLK_TOP_ETH_GMII_SEL>,
 				 <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>,
 				 <&topckgen CLK_TOP_ETH_SYS_200M_SEL>,
@@ -1284,13 +1417,9 @@
 				 <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>,
 				 <&topckgen CLK_TOP_NETSYS_WARP_SEL>;
 			clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1",
-				      "gp3", "esw", "crypto", "sgmii_tx250m",
-				      "sgmii_rx250m", "sgmii2_tx250m", "sgmii2_rx250m",
+				      "gp3", "esw", "crypto",
 				      "ethwarp_wocpu2", "ethwarp_wocpu1",
-				      "ethwarp_wocpu0", "top_usxgmii0_sel",
-				      "top_usxgmii1_sel", "top_sgm0_sel",
-				      "top_sgm1_sel", "top_xfi_phy0_xtal_sel",
-				      "top_xfi_phy1_xtal_sel", "top_eth_gmii_sel",
+				      "ethwarp_wocpu0", "top_eth_gmii_sel",
 				      "top_eth_refck_50m_sel", "top_eth_sys_200m_sel",
 				      "top_eth_sys_sel", "top_eth_xgmii_sel",
 				      "top_eth_mii_sel", "top_netsys_sel",
@@ -1311,13 +1440,7 @@
 						 <&apmixedsys CLK_APMIXED_SGMPLL>,
 						 <&apmixedsys CLK_APMIXED_SGMPLL>;
 			mediatek,ethsys = <&ethsys>;
-			mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
-			mediatek,usxgmiisys = <&usxgmiisys0>, <&usxgmiisys1>;
-			mediatek,xfi-pextp = <&xfi_pextp0>, <&xfi_pextp1>;
-			mediatek,xfi-pll = <&xfi_pll>;
 			mediatek,infracfg = <&topmisc>;
-			mediatek,toprgu = <&watchdog>;
-			#reset-cells = <1>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 
@@ -1338,12 +1461,16 @@
 				compatible = "mediatek,eth-mac";
 				reg = <1>;
 				status = "disabled";
+				pcs-handle = <&sgmiipcs1>, <&usxgmiisys1>;
+				phys = <&xfi_tphy1>;
 			};
 
 			gmac2: mac@2 {
 				compatible = "mediatek,eth-mac";
 				reg = <2>;
 				status = "disabled";
+				pcs-handle = <&sgmiipcs0>, <&usxgmiisys0>;
+				phys = <&xfi_tphy0>;
 			};
 
 			mdio_bus: mdio-bus {
@@ -1352,8 +1479,8 @@
 
 				/* internal 2.5G PHY */
 				int_2p5g_phy: ethernet-phy@15 {
-					reg = <15>;
 					compatible = "ethernet-phy-ieee802.3-c45";
+					reg = <15>;
 					phy-mode = "internal";
 				};
 			};
@@ -1376,6 +1503,7 @@
 			polling-delay-passive = <1000>;
 			polling-delay = <1000>;
 			thermal-sensors = <&lvts 0>;
+
 			trips {
 				cpu_trip_crit: crit {
 					temperature = <125000>;
diff --git a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-apmixed.c b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-apmixed.c
deleted file mode 100644
index 3f1edc231e37a3..00000000000000
--- a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-apmixed.c
+++ /dev/null
@@ -1,113 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2023 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include "clk-mtk.h"
-#include "clk-gate.h"
-#include "clk-mux.h"
-#include "clk-pll.h"
-#include <dt-bindings/clock/mediatek,mt7988-clk.h>
-
-#define MT7988_PLL_FMAX (2500UL * MHZ)
-#define MT7988_PCW_CHG_SHIFT 2
-
-#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \
-		 _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg,     \
-		 _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg,           \
-		 _div_table)                                                  \
-	{                                                                     \
-		.id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg,   \
-		.en_mask = _en_mask, .flags = _flags,                         \
-		.rst_bar_mask = BIT(_rst_bar_mask), .fmax = MT7988_PLL_FMAX,  \
-		.pcwbits = _pcwbits, .pd_reg = _pd_reg,                       \
-		.pd_shift = _pd_shift, .tuner_reg = _tuner_reg,               \
-		.tuner_en_reg = _tuner_en_reg, .tuner_en_bit = _tuner_en_bit, \
-		.pcw_reg = _pcw_reg, .pcw_shift = _pcw_shift,                 \
-		.pcw_chg_reg = _pcw_chg_reg,                                  \
-		.pcw_chg_shift = MT7988_PCW_CHG_SHIFT,                        \
-		.div_table = _div_table, .parent_name = "clkxtal",            \
-	}
-
-#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask,      \
-	    _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg,          \
-	    _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg)                \
-	PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \
-		 _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg,     \
-		 _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg, NULL)
-
-static const struct mtk_pll_data plls[] = {
-	PLL(CLK_APMIXED_NETSYSPLL, "netsyspll", 0x0104, 0x0110, 0x00000001, 0,
-	    0, 32, 0x0104, 4, 0, 0, 0, 0x0108, 0, 0x0104),
-	PLL(CLK_APMIXED_MPLL, "mpll", 0x0114, 0x0120, 0xff000001, HAVE_RST_BAR,
-	    23, 32, 0x0114, 4, 0, 0, 0, 0x0118, 0, 0x0114),
-	PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0124, 0x0130, 0xff000001,
-	    HAVE_RST_BAR, 23, 32, 0x0124, 4, 0, 0, 0, 0x0128, 0, 0x0124),
-	PLL(CLK_APMIXED_APLL2, "apll2", 0x0134, 0x0140, 0x00000001, 0, 0, 32,
-	    0x0134, 4, 0x0704, 0x0700, 1, 0x0138, 0, 0x0134),
-	PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0144, 0x0150, 0xff000001,
-	    HAVE_RST_BAR, 23, 32, 0x0144, 4, 0, 0, 0, 0x0148, 0, 0x0144),
-	PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0154, 0x0160, 0xff000001,
-	    (HAVE_RST_BAR | PLL_AO), 23, 32, 0x0154, 4, 0, 0, 0, 0x0158, 0,
-	    0x0154),
-	PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0164, 0x0170, 0x00000001, 0,
-	    0, 32, 0x0164, 4, 0, 0, 0, 0x0168, 0, 0x0164),
-	PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0174, 0x0180, 0x00000001, 0, 0, 32,
-	    0x0174, 4, 0, 0, 0, 0x0178, 0, 0x0174),
-	PLL(CLK_APMIXED_ARM_B, "arm_b", 0x0204, 0x0210, 0xff000001,
-	    (HAVE_RST_BAR | PLL_AO), 23, 32, 0x0204, 4, 0, 0, 0, 0x0208, 0,
-	    0x0204),
-	PLL(CLK_APMIXED_CCIPLL2_B, "ccipll2_b", 0x0214, 0x0220, 0xff000001,
-	    HAVE_RST_BAR, 23, 32, 0x0214, 4, 0, 0, 0, 0x0218, 0, 0x0214),
-	PLL(CLK_APMIXED_USXGMIIPLL, "usxgmiipll", 0x0304, 0x0310, 0xff000001,
-	    HAVE_RST_BAR, 23, 32, 0x0304, 4, 0, 0, 0, 0x0308, 0, 0x0304),
-	PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0314, 0x0320, 0x00000001, 0, 0,
-	    32, 0x0314, 4, 0, 0, 0, 0x0318, 0, 0x0314),
-};
-
-static const struct of_device_id of_match_clk_mt7988_apmixed[] = {
-	{ .compatible = "mediatek,mt7988-apmixedsys", },
-	{ /* sentinel */ }
-};
-
-static int clk_mt7988_apmixed_probe(struct platform_device *pdev)
-{
-	struct clk_hw_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
-
-	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_apmixed_data;
-	}
-	return r;
-
-free_apmixed_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
-
-static struct platform_driver clk_mt7988_apmixed_drv = {
-	.probe = clk_mt7988_apmixed_probe,
-	.driver = {
-		.name = "clk-mt7988-apmixed",
-		.of_match_table = of_match_clk_mt7988_apmixed,
-	},
-};
-builtin_platform_driver(clk_mt7988_apmixed_drv);
-MODULE_LICENSE("GPL");
diff --git a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-eth.c b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-eth.c
deleted file mode 100644
index 14b877f8cb038a..00000000000000
--- a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-eth.c
+++ /dev/null
@@ -1,141 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2023 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include "clk-mtk.h"
-#include "clk-gate.h"
-#include <dt-bindings/clock/mediatek,mt7988-clk.h>
-
-static const struct mtk_gate_regs ethdma_cg_regs = {
-	.set_ofs = 0x30,
-	.clr_ofs = 0x30,
-	.sta_ofs = 0x30,
-};
-
-#define GATE_ETHDMA(_id, _name, _parent, _shift)                              \
-	{                                                                     \
-		.id = _id, .name = _name, .parent_name = _parent,             \
-		.regs = &ethdma_cg_regs, .shift = _shift,                     \
-		.ops = &mtk_clk_gate_ops_no_setclr_inv,                       \
-	}
-
-static const struct mtk_gate ethdma_clks[] = {
-	GATE_ETHDMA(CLK_ETHDMA_XGP1_EN, "ethdma_xgp1_en", "top_xtal", 0),
-	GATE_ETHDMA(CLK_ETHDMA_XGP2_EN, "ethdma_xgp2_en", "top_xtal", 1),
-	GATE_ETHDMA(CLK_ETHDMA_XGP3_EN, "ethdma_xgp3_en", "top_xtal", 2),
-	GATE_ETHDMA(CLK_ETHDMA_FE_EN, "ethdma_fe_en", "netsys_2x_sel", 6),
-	GATE_ETHDMA(CLK_ETHDMA_GP2_EN, "ethdma_gp2_en", "top_xtal", 7),
-	GATE_ETHDMA(CLK_ETHDMA_GP1_EN, "ethdma_gp1_en", "top_xtal", 8),
-	GATE_ETHDMA(CLK_ETHDMA_GP3_EN, "ethdma_gp3_en", "top_xtal", 10),
-	GATE_ETHDMA(CLK_ETHDMA_ESW_EN, "ethdma_esw_en", "netsys_gsw_sel", 16),
-	GATE_ETHDMA(CLK_ETHDMA_CRYPT0_EN, "ethdma_crypt0_en", "eip197_sel",
-		    29),
-};
-
-static const struct mtk_clk_desc ethdma_desc = {
-	.clks = ethdma_clks,
-	.num_clks = ARRAY_SIZE(ethdma_clks),
-};
-
-static const struct mtk_gate_regs sgmii0_cg_regs = {
-	.set_ofs = 0xe4,
-	.clr_ofs = 0xe4,
-	.sta_ofs = 0xe4,
-};
-
-#define GATE_SGMII0(_id, _name, _parent, _shift)                              \
-	{                                                                     \
-		.id = _id, .name = _name, .parent_name = _parent,             \
-		.regs = &sgmii0_cg_regs, .shift = _shift,                     \
-		.ops = &mtk_clk_gate_ops_no_setclr_inv,                       \
-	}
-
-static const struct mtk_gate sgmii0_clks[] = {
-	GATE_SGMII0(CLK_SGM0_TX_EN, "sgm0_tx_en", "top_xtal", 2),
-	GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", "top_xtal", 3),
-};
-
-static const struct mtk_clk_desc sgmii0_desc = {
-	.clks = sgmii0_clks,
-	.num_clks = ARRAY_SIZE(sgmii0_clks),
-};
-
-static const struct mtk_gate_regs sgmii1_cg_regs = {
-	.set_ofs = 0xe4,
-	.clr_ofs = 0xe4,
-	.sta_ofs = 0xe4,
-};
-
-#define GATE_SGMII1(_id, _name, _parent, _shift)                              \
-	{                                                                     \
-		.id = _id, .name = _name, .parent_name = _parent,             \
-		.regs = &sgmii1_cg_regs, .shift = _shift,                     \
-		.ops = &mtk_clk_gate_ops_no_setclr_inv,                       \
-	}
-
-static const struct mtk_gate sgmii1_clks[] = {
-	GATE_SGMII1(CLK_SGM1_TX_EN, "sgm1_tx_en", "top_xtal", 2),
-	GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", "top_xtal", 3),
-};
-
-static const struct mtk_clk_desc sgmii1_desc = {
-	.clks = sgmii1_clks,
-	.num_clks = ARRAY_SIZE(sgmii1_clks),
-};
-
-static const struct mtk_gate_regs ethwarp_cg_regs = {
-	.set_ofs = 0x14,
-	.clr_ofs = 0x14,
-	.sta_ofs = 0x14,
-};
-
-#define GATE_ETHWARP(_id, _name, _parent, _shift)                             \
-	{                                                                     \
-		.id = _id, .name = _name, .parent_name = _parent,             \
-		.regs = &ethwarp_cg_regs, .shift = _shift,                    \
-		.ops = &mtk_clk_gate_ops_no_setclr_inv,                       \
-	}
-
-static const struct mtk_gate ethwarp_clks[] = {
-	GATE_ETHWARP(CLK_ETHWARP_WOCPU2_EN, "ethwarp_wocpu2_en",
-		     "netsys_mcu_sel", 13),
-	GATE_ETHWARP(CLK_ETHWARP_WOCPU1_EN, "ethwarp_wocpu1_en",
-		     "netsys_mcu_sel", 14),
-	GATE_ETHWARP(CLK_ETHWARP_WOCPU0_EN, "ethwarp_wocpu0_en",
-		     "netsys_mcu_sel", 15),
-};
-
-static const struct mtk_clk_desc ethwarp_desc = {
-	.clks = ethwarp_clks,
-	.num_clks = ARRAY_SIZE(ethwarp_clks),
-};
-
-static const struct of_device_id of_match_clk_mt7986_eth[] = {
-	{ .compatible = "mediatek,mt7988-ethsys", .data = &ethdma_desc },
-	{ .compatible = "mediatek,mt7988-sgmiisys_0", .data = &sgmii0_desc },
-	{ .compatible = "mediatek,mt7988-sgmiisys_1", .data = &sgmii1_desc },
-	{ .compatible = "mediatek,mt7988-ethwarp", .data = &ethwarp_desc },
-	{ /* sentinel */ }
-};
-MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_eth);
-
-static struct platform_driver clk_mt7988_eth_drv = {
-	.driver = {
-		.name = "clk-mt7988-eth",
-		.of_match_table = of_match_clk_mt7986_eth,
-	},
-	.probe = mtk_clk_simple_probe,
-	.remove = mtk_clk_simple_remove,
-};
-module_platform_driver(clk_mt7988_eth_drv);
-
-MODULE_DESCRIPTION("MediaTek MT7988 Ethernet clocks driver");
-MODULE_LICENSE("GPL");
diff --git a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-infracfg.c b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-infracfg.c
deleted file mode 100644
index a5d21d756d5188..00000000000000
--- a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-infracfg.c
+++ /dev/null
@@ -1,376 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2023 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include "clk-mtk.h"
-#include "clk-gate.h"
-#include "clk-mux.h"
-#include <dt-bindings/clock/mediatek,mt7988-clk.h>
-
-static DEFINE_SPINLOCK(mt7988_clk_lock);
-
-static const char *const infra_mux_uart0_parents[] __initconst = {
-	"csw_infra_f26m_sel", "uart_sel"
-};
-
-static const char *const infra_mux_uart1_parents[] __initconst = {
-	"csw_infra_f26m_sel", "uart_sel"
-};
-
-static const char *const infra_mux_uart2_parents[] __initconst = {
-	"csw_infra_f26m_sel", "uart_sel"
-};
-
-static const char *const infra_mux_spi0_parents[] __initconst = { "i2c_sel",
-								  "spi_sel" };
-
-static const char *const infra_mux_spi1_parents[] __initconst = {
-	"i2c_sel", "spim_mst_sel"
-};
-
-static const char *const infra_pwm_bck_parents[] __initconst = {
-	"top_rtc_32p7k", "csw_infra_f26m_sel", "sysaxi_sel", "pwm_sel"
-};
-
-static const char *const infra_pcie_gfmux_tl_ck_o_p0_parents[] __initconst = {
-	"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel",
-	"pextp_tl_sel"
-};
-
-static const char *const infra_pcie_gfmux_tl_ck_o_p1_parents[] __initconst = {
-	"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel",
-	"pextp_tl_p1_sel"
-};
-
-static const char *const infra_pcie_gfmux_tl_ck_o_p2_parents[] __initconst = {
-	"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel",
-	"pextp_tl_p2_sel"
-};
-
-static const char *const infra_pcie_gfmux_tl_ck_o_p3_parents[] __initconst = {
-	"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel",
-	"pextp_tl_p3_sel"
-};
-
-static const struct mtk_mux infra_muxes[] = {
-	/* MODULE_CLK_SEL_0 */
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel",
-			     infra_mux_uart0_parents, 0x0018, 0x0010, 0x0014,
-			     0, 1, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel",
-			     infra_mux_uart1_parents, 0x0018, 0x0010, 0x0014,
-			     1, 1, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel",
-			     infra_mux_uart2_parents, 0x0018, 0x0010, 0x0014,
-			     2, 1, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel",
-			     infra_mux_spi0_parents, 0x0018, 0x0010, 0x0014, 4,
-			     1, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel",
-			     infra_mux_spi1_parents, 0x0018, 0x0010, 0x0014, 5,
-			     1, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel",
-			     infra_mux_spi0_parents, 0x0018, 0x0010, 0x0014, 6,
-			     1, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_SEL, "infra_pwm_sel",
-			     infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 14,
-			     2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel",
-			     infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 16,
-			     2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel",
-			     infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 18,
-			     2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel",
-			     infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 20,
-			     2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel",
-			     infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 22,
-			     2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel",
-			     infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 24,
-			     2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel",
-			     infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 26,
-			     2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel",
-			     infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 28,
-			     2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel",
-			     infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 30,
-			     2, -1, -1, -1),
-	/* MODULE_CLK_SEL_1 */
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL,
-			     "infra_pcie_gfmux_tl_o_p0_sel",
-			     infra_pcie_gfmux_tl_ck_o_p0_parents, 0x0028,
-			     0x0020, 0x0024, 0, 2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL,
-			     "infra_pcie_gfmux_tl_o_p1_sel",
-			     infra_pcie_gfmux_tl_ck_o_p1_parents, 0x0028,
-			     0x0020, 0x0024, 2, 2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL,
-			     "infra_pcie_gfmux_tl_o_p2_sel",
-			     infra_pcie_gfmux_tl_ck_o_p2_parents, 0x0028,
-			     0x0020, 0x0024, 4, 2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL,
-			     "infra_pcie_gfmux_tl_o_p3_sel",
-			     infra_pcie_gfmux_tl_ck_o_p3_parents, 0x0028,
-			     0x0020, 0x0024, 6, 2, -1, -1, -1),
-};
-
-static const struct mtk_gate_regs infra0_cg_regs = {
-	.set_ofs = 0x10,
-	.clr_ofs = 0x14,
-	.sta_ofs = 0x18,
-};
-
-static const struct mtk_gate_regs infra1_cg_regs = {
-	.set_ofs = 0x40,
-	.clr_ofs = 0x44,
-	.sta_ofs = 0x48,
-};
-
-static const struct mtk_gate_regs infra2_cg_regs = {
-	.set_ofs = 0x50,
-	.clr_ofs = 0x54,
-	.sta_ofs = 0x58,
-};
-
-static const struct mtk_gate_regs infra3_cg_regs = {
-	.set_ofs = 0x60,
-	.clr_ofs = 0x64,
-	.sta_ofs = 0x68,
-};
-
-#define GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, _flags)                \
-	{                                                                     \
-		.id = _id, .name = _name, .parent_name = _parent,             \
-		.regs = &infra0_cg_regs, .shift = _shift,                     \
-		.ops = &mtk_clk_gate_ops_setclr, .flags = _flags,             \
-	}
-
-#define GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, _flags)                \
-	{                                                                     \
-		.id = _id, .name = _name, .parent_name = _parent,             \
-		.regs = &infra1_cg_regs, .shift = _shift,                     \
-		.ops = &mtk_clk_gate_ops_setclr, .flags = _flags,             \
-	}
-
-#define GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, _flags)                \
-	{                                                                     \
-		.id = _id, .name = _name, .parent_name = _parent,             \
-		.regs = &infra2_cg_regs, .shift = _shift,                     \
-		.ops = &mtk_clk_gate_ops_setclr, .flags = _flags,             \
-	}
-
-#define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flags)                \
-	{                                                                     \
-		.id = _id, .name = _name, .parent_name = _parent,             \
-		.regs = &infra3_cg_regs, .shift = _shift,                     \
-		.ops = &mtk_clk_gate_ops_setclr, .flags = _flags,             \
-	}
-
-#define GATE_INFRA0(_id, _name, _parent, _shift)                              \
-	GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, 0)
-
-#define GATE_INFRA1(_id, _name, _parent, _shift)                              \
-	GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, 0)
-
-#define GATE_INFRA2(_id, _name, _parent, _shift)                              \
-	GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, 0)
-
-#define GATE_INFRA3(_id, _name, _parent, _shift)                              \
-	GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, 0)
-
-#define GATE_CRITICAL(_id, _name, _parent, _regs, _shift) {                   \
-		.id = _id, .name = _name, .parent_name = _parent,             \
-		.regs = _regs, .shift = _shift,                               \
-		.flags = CLK_IS_CRITICAL,                                     \
-		.ops = &mtk_clk_gate_ops_setclr,                              \
-	}
-
-static const struct mtk_gate infra_clks[] = {
-	/* INFRA0 */
-	GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P0,
-		    "infra_pcie_peri_ck_26m_ck_p0", "csw_infra_f26m_sel", 7),
-	GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P1,
-		    "infra_pcie_peri_ck_26m_ck_p1", "csw_infra_f26m_sel", 8),
-	GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P2,
-		    "infra_pcie_peri_ck_26m_ck_p2", "csw_infra_f26m_sel", 9),
-	GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P3,
-		    "infra_pcie_peri_ck_26m_ck_p3", "csw_infra_f26m_sel", 10),
-	/* INFRA1 */
-	GATE_INFRA1(CLK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck",
-		    "sysaxi_sel", 0),
-	GATE_INFRA1(CLK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck",
-		    "sysaxi_sel", 1),
-	GATE_INFRA1(CLK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck",
-		    "infra_pwm_sel", 2),
-	GATE_INFRA1(CLK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1",
-		    "infra_pwm_ck1_sel", 3),
-	GATE_INFRA1(CLK_INFRA_66M_PWM_CK2, "infra_hf_66m_pwm_ck2",
-		    "infra_pwm_ck2_sel", 4),
-	GATE_INFRA1(CLK_INFRA_66M_PWM_CK3, "infra_hf_66m_pwm_ck3",
-		    "infra_pwm_ck3_sel", 5),
-	GATE_INFRA1(CLK_INFRA_66M_PWM_CK4, "infra_hf_66m_pwm_ck4",
-		    "infra_pwm_ck4_sel", 6),
-	GATE_INFRA1(CLK_INFRA_66M_PWM_CK5, "infra_hf_66m_pwm_ck5",
-		    "infra_pwm_ck5_sel", 7),
-	GATE_INFRA1(CLK_INFRA_66M_PWM_CK6, "infra_hf_66m_pwm_ck6",
-		    "infra_pwm_ck6_sel", 8),
-	GATE_INFRA1(CLK_INFRA_66M_PWM_CK7, "infra_hf_66m_pwm_ck7",
-		    "infra_pwm_ck7_sel", 9),
-	GATE_INFRA1(CLK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8",
-		    "infra_pwm_ck8_sel", 10),
-	GATE_INFRA1(CLK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck",
-		    "sysaxi_sel", 12),
-	GATE_INFRA1(CLK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck",
-		    "sysaxi_sel", 13),
-	GATE_INFRA1(CLK_INFRA_AUD_26M, "infra_f_faud_26m",
-		    "csw_infra_f26m_sel", 14),
-	GATE_INFRA1(CLK_INFRA_AUD_L, "infra_f_faud_l", "aud_l_sel", 15),
-	GATE_INFRA1(CLK_INFRA_AUD_AUD, "infra_f_aud_aud", "a1sys_sel", 16),
-	GATE_INFRA1(CLK_INFRA_AUD_EG2, "infra_f_faud_eg2", "a_tuner_sel", 18),
-	GATE_INFRA1_FLAGS(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m",
-			  "csw_infra_f26m_sel", 19, CLK_IS_CRITICAL),
-	// JTAG
-	GATE_INFRA1_FLAGS(CLK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm",
-			  "sysaxi_sel", 20, CLK_IS_CRITICAL),
-	GATE_INFRA1(CLK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck",
-		    "sysaxi_sel", 21),
-	GATE_INFRA1(CLK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck",
-		    "sysaxi_sel", 29),
-	GATE_INFRA1(CLK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m",
-		    "csw_infra_f26m_sel", 30),
-	/* INFRA2 */
-	GATE_INFRA2(CLK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system",
-		    "csw_infra_f26m_sel", 0),
-	GATE_INFRA2(CLK_INFRA_I2C_BCK, "infra_i2c_bck", "i2c_sel", 1),
-	GATE_INFRA2(CLK_INFRA_52M_UART0_CK, "infra_f_52m_uart0",
-		    "infra_mux_uart0_sel", 3),
-	GATE_INFRA2(CLK_INFRA_52M_UART1_CK, "infra_f_52m_uart1",
-		    "infra_mux_uart1_sel", 4),
-	GATE_INFRA2(CLK_INFRA_52M_UART2_CK, "infra_f_52m_uart2",
-		    "infra_mux_uart2_sel", 5),
-	GATE_INFRA2(CLK_INFRA_NFI, "infra_f_fnfi", "nfi1x_sel", 9),
-	GATE_INFRA2(CLK_INFRA_SPINFI, "infra_f_fspinfi", "spinfi_sel", 10),
-	GATE_INFRA2_FLAGS(CLK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck",
-			  "sysaxi_sel", 11, CLK_IS_CRITICAL),
-	GATE_INFRA2_FLAGS(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0",
-			  "infra_mux_spi0_sel", 12, CLK_IS_CRITICAL),
-	GATE_INFRA2(CLK_INFRA_104M_SPI1, "infra_hf_104m_spi1",
-		    "infra_mux_spi1_sel", 13),
-	GATE_INFRA2(CLK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck",
-		    "infra_mux_spi2_sel", 14),
-	GATE_INFRA2_FLAGS(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck",
-			  "sysaxi_sel", 15, CLK_IS_CRITICAL),
-	GATE_INFRA2(CLK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck",
-		    "sysaxi_sel", 16),
-	GATE_INFRA2(CLK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck",
-		    "sysaxi_sel", 17),
-	GATE_INFRA2(CLK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi",
-		    "sysaxi_sel", 18),
-	GATE_CRITICAL(CLK_INFRA_RTC, "infra_f_frtc", "top_rtc_32k", &infra2_cg_regs, 19),
-	GATE_INFRA2(CLK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck",
-		    "csw_infra_f26m_sel", 20),
-	GATE_INFRA2(CLK_INFRA_RC_ADC, "infra_f_frc_adc", "infra_f_26m_adc_bck",
-		    21),
-	GATE_INFRA2(CLK_INFRA_MSDC400, "infra_f_fmsdc400", "emmc_400m_sel",
-		    22),
-	GATE_INFRA2(CLK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck", "emmc_250m_sel",
-		    23),
-	GATE_INFRA2(CLK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck",
-		    "sysaxi_sel", 24),
-	GATE_INFRA2(CLK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck",
-		    "sysaxi_sel", 25),
-	GATE_INFRA2(CLK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck",
-		    "sysaxi_sel", 26),
-	GATE_INFRA2(CLK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", "nfi1x_sel", 27),
-	GATE_INFRA2(CLK_INFRA_I2C_X16W_MCK_CK_P1,
-		    "infra_hf_i2c_x16w_mck_ck_p1", "sysaxi_sel", 29),
-	GATE_INFRA2(CLK_INFRA_I2C_X16W_PCK_CK_P1,
-		    "infra_hf_i2c_x16w_pck_ck_p1", "sysaxi_sel", 31),
-	/* INFRA3 */
-	GATE_INFRA3(CLK_INFRA_133M_USB_HCK, "infra_133m_usb_hck", "sysaxi_sel",
-		    0),
-	GATE_INFRA3(CLK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1",
-		    "sysaxi_sel", 1),
-	GATE_INFRA3(CLK_INFRA_66M_USB_HCK, "infra_66m_usb_hck", "sysaxi_sel",
-		    2),
-	GATE_INFRA3(CLK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1",
-		    "sysaxi_sel", 3),
-	GATE_INFRA3(CLK_INFRA_USB_SYS, "infra_usb_sys", "usb_sys_sel", 4),
-	GATE_INFRA3(CLK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1",
-		    "usb_sys_p1_sel", 5),
-	GATE_INFRA3(CLK_INFRA_USB_REF, "infra_usb_ref", "top_xtal", 6),
-	GATE_INFRA3(CLK_INFRA_USB_CK_P1, "infra_usb_ck_p1", "top_xtal", 7),
-	GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT, "infra_usb_frmcnt",
-			  "usb_frmcnt_sel", 8, CLK_IS_CRITICAL),
-	GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1",
-			  "usb_frmcnt_p1_sel", 9, CLK_IS_CRITICAL),
-	GATE_INFRA3(CLK_INFRA_USB_PIPE, "infra_usb_pipe", "sspxtp_sel", 10),
-	GATE_INFRA3(CLK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1",
-		    "usb_phy_sel", 11),
-	GATE_INFRA3(CLK_INFRA_USB_UTMI, "infra_usb_utmi", "top_xtal", 12),
-	GATE_INFRA3(CLK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1",
-		    "top_xtal", 13),
-	GATE_INFRA3(CLK_INFRA_USB_XHCI, "infra_usb_xhci", "usb_xhci_sel", 14),
-	GATE_INFRA3(CLK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1",
-		    "usb_xhci_p1_sel", 15),
-	GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0",
-		    "infra_pcie_gfmux_tl_o_p0_sel", 20),
-	GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1",
-		    "infra_pcie_gfmux_tl_o_p1_sel", 21),
-	GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P2, "infra_pcie_gfmux_tl_ck_p2",
-		    "infra_pcie_gfmux_tl_o_p2_sel", 22),
-	GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3",
-		    "infra_pcie_gfmux_tl_o_p3_sel", 23),
-	GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0",
-		    "top_xtal", 24),
-	GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1",
-		    "top_xtal", 25),
-	GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2",
-		    "top_xtal", 26),
-	GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3",
-		    "top_xtal", 27),
-	GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0",
-		    "sysaxi_sel", 28),
-	GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1",
-		    "sysaxi_sel", 29),
-	GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2",
-		    "sysaxi_sel", 30),
-	GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3",
-		    "sysaxi_sel", 31),
-};
-
-static const struct mtk_clk_desc infra_desc = {
-	.clks = infra_clks,
-	.num_clks = ARRAY_SIZE(infra_clks),
-	.mux_clks = infra_muxes,
-	.num_mux_clks = ARRAY_SIZE(infra_muxes),
-	.clk_lock = &mt7988_clk_lock,
-};
-
-static const struct of_device_id of_match_clk_mt7988_infracfg[] = {
-	{ .compatible = "mediatek,mt7988-infracfg", .data = &infra_desc },
-	{ /* sentinel */ }
-};
-MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_infracfg);
-
-static struct platform_driver clk_mt7988_infracfg_drv = {
-	.driver = {
-		.name = "clk-mt7988-infracfg",
-		.of_match_table = of_match_clk_mt7988_infracfg,
-	},
-	.probe = mtk_clk_simple_probe,
-	.remove = mtk_clk_simple_remove,
-};
-module_platform_driver(clk_mt7988_infracfg_drv);
diff --git a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-topckgen.c b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-topckgen.c
deleted file mode 100644
index b0745d65089eb2..00000000000000
--- a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-topckgen.c
+++ /dev/null
@@ -1,446 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2023 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include "clk-mtk.h"
-#include "clk-gate.h"
-#include "clk-mux.h"
-#include <dt-bindings/clock/mediatek,mt7988-clk.h>
-
-static DEFINE_SPINLOCK(mt7988_clk_lock);
-
-static const struct mtk_fixed_clk top_fixed_clks[] = {
-	FIXED_CLK(CLK_TOP_XTAL, "top_xtal", "clkxtal", 40000000),
-};
-
-static const struct mtk_fixed_factor top_divs[] = {
-	FACTOR(CLK_TOP_XTAL_D2, "top_xtal_d2", "top_xtal", 1, 2),
-	FACTOR(CLK_TOP_RTC_32K, "top_rtc_32k", "top_xtal", 1, 1250),
-	FACTOR(CLK_TOP_RTC_32P7K, "top_rtc_32p7k", "top_xtal", 1, 1220),
-	FACTOR(CLK_TOP_MPLL_D2, "mpll_d2", "mpll", 1, 2),
-	FACTOR(CLK_TOP_MPLL_D3_D2, "mpll_d3_d2", "mpll", 1, 2),
-	FACTOR(CLK_TOP_MPLL_D4, "mpll_d4", "mpll", 1, 4),
-	FACTOR(CLK_TOP_MPLL_D8, "mpll_d8", "mpll", 1, 8),
-	FACTOR(CLK_TOP_MPLL_D8_D2, "mpll_d8_d2", "mpll", 1, 16),
-	FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
-	FACTOR(CLK_TOP_MMPLL_D3_D5, "mmpll_d3_d5", "mmpll", 1, 15),
-	FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4),
-	FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll", 1, 12),
-	FACTOR(CLK_TOP_MMPLL_D8, "mmpll_d8", "mmpll", 1, 8),
-	FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
-	FACTOR(CLK_TOP_NET1PLL_D4, "net1pll_d4", "net1pll", 1, 4),
-	FACTOR(CLK_TOP_NET1PLL_D5, "net1pll_d5", "net1pll", 1, 5),
-	FACTOR(CLK_TOP_NET1PLL_D5_D2, "net1pll_d5_d2", "net1pll", 1, 10),
-	FACTOR(CLK_TOP_NET1PLL_D5_D4, "net1pll_d5_d4", "net1pll", 1, 20),
-	FACTOR(CLK_TOP_NET1PLL_D8, "net1pll_d8", "net1pll", 1, 8),
-	FACTOR(CLK_TOP_NET1PLL_D8_D2, "net1pll_d8_d2", "net1pll", 1, 16),
-	FACTOR(CLK_TOP_NET1PLL_D8_D4, "net1pll_d8_d4", "net1pll", 1, 32),
-	FACTOR(CLK_TOP_NET1PLL_D8_D8, "net1pll_d8_d8", "net1pll", 1, 64),
-	FACTOR(CLK_TOP_NET1PLL_D8_D16, "net1pll_d8_d16", "net1pll", 1, 128),
-	FACTOR(CLK_TOP_NET2PLL_D2, "net2pll_d2", "net2pll", 1, 2),
-	FACTOR(CLK_TOP_NET2PLL_D4, "net2pll_d4", "net2pll", 1, 4),
-	FACTOR(CLK_TOP_NET2PLL_D4_D4, "net2pll_d4_d4", "net2pll", 1, 16),
-	FACTOR(CLK_TOP_NET2PLL_D4_D8, "net2pll_d4_d8", "net2pll", 1, 32),
-	FACTOR(CLK_TOP_NET2PLL_D6, "net2pll_d6", "net2pll", 1, 6),
-	FACTOR(CLK_TOP_NET2PLL_D8, "net2pll_d8", "net2pll", 1, 8),
-};
-
-static const char *const netsys_parents[] = { "top_xtal", "net2pll_d2",
-					      "mmpll_d2" };
-
-static const char *const netsys_500m_parents[] = { "top_xtal", "net1pll_d5",
-						   "net1pll_d5_d2" };
-
-static const char *const netsys_2x_parents[] = { "top_xtal", "net2pll",
-						 "mmpll" };
-
-static const char *const netsys_gsw_parents[] = { "top_xtal", "net1pll_d4",
-						  "net1pll_d5" };
-
-static const char *const eth_gmii_parents[] = { "top_xtal", "net1pll_d5_d4" };
-
-static const char *const netsys_mcu_parents[] = { "top_xtal",	"net2pll",
-						  "mmpll",	"net1pll_d4",
-						  "net1pll_d5", "mpll" };
-
-static const char *const eip197_parents[] = { "top_xtal",   "netsyspll",
-					      "net2pll",    "mmpll",
-					      "net1pll_d4", "net1pll_d5" };
-
-static const char *const axi_infra_parents[] = { "top_xtal", "net1pll_d8_d2" };
-
-static const char *const uart_parents[] = { "top_xtal", "mpll_d8",
-					    "mpll_d8_d2" };
-
-static const char *const emmc_250m_parents[] = { "top_xtal", "net1pll_d5_d2",
-						 "mmpll_d4" };
-
-static const char *const emmc_400m_parents[] = { "top_xtal", "msdcpll",
-						 "mmpll_d2", "mpll_d2",
-						 "mmpll_d4", "net1pll_d8_d2" };
-
-static const char *const spi_parents[] = { "top_xtal",	 "mpll_d2",
-					   "mmpll_d4",	 "net1pll_d8_d2",
-					   "net2pll_d6", "net1pll_d5_d4",
-					   "mpll_d4",	 "net1pll_d8_d4" };
-
-static const char *const nfi1x_parents[] = { "top_xtal",      "mmpll_d4",
-					     "net1pll_d8_d2", "net2pll_d6",
-					     "mpll_d4",	      "mmpll_d8",
-					     "net1pll_d8_d4", "mpll_d8" };
-
-static const char *const spinfi_parents[] = { "top_xtal_d2",   "top_xtal",
-					      "net1pll_d5_d4", "mpll_d4",
-					      "mmpll_d8",      "net1pll_d8_d4",
-					      "mmpll_d6_d2",   "mpll_d8" };
-
-static const char *const pwm_parents[] = { "top_xtal",	    "net1pll_d8_d2",
-					   "net1pll_d5_d4", "mpll_d4",
-					   "mpll_d8_d2",    "top_rtc_32k" };
-
-static const char *const i2c_parents[] = { "top_xtal", "net1pll_d5_d4",
-					   "mpll_d4", "net1pll_d8_d4" };
-
-static const char *const pcie_mbist_250m_parents[] = { "top_xtal",
-						       "net1pll_d5_d2" };
-
-static const char *const pextp_tl_ck_parents[] = { "top_xtal", "net2pll_d6",
-						   "mmpll_d8", "mpll_d8_d2",
-						   "top_rtc_32k" };
-
-static const char *const usb_frmcnt_parents[] = { "top_xtal", "mmpll_d3_d5" };
-
-static const char *const aud_parents[] = { "top_xtal", "apll2" };
-
-static const char *const a1sys_parents[] = { "top_xtal", "apll2_d4" };
-
-static const char *const aud_l_parents[] = { "top_xtal", "apll2",
-					     "mpll_d8_d2" };
-
-static const char *const sspxtp_parents[] = { "top_xtal_d2", "mpll_d8_d2" };
-
-static const char *const usxgmii_sbus_0_parents[] = { "top_xtal",
-						      "net1pll_d8_d4" };
-
-static const char *const sgm_0_parents[] = { "top_xtal", "sgmpll" };
-
-static const char *const sysapb_parents[] = { "top_xtal", "mpll_d3_d2" };
-
-static const char *const eth_refck_50m_parents[] = { "top_xtal",
-						     "net2pll_d4_d4" };
-
-static const char *const eth_sys_200m_parents[] = { "top_xtal", "net2pll_d4" };
-
-static const char *const eth_xgmii_parents[] = { "top_xtal_d2",
-						 "net1pll_d8_d8",
-						 "net1pll_d8_d16" };
-
-static const char *const bus_tops_parents[] = { "top_xtal", "net1pll_d5",
-						"net2pll_d2" };
-
-static const char *const npu_tops_parents[] = { "top_xtal", "net2pll" };
-
-static const char *const dramc_md32_parents[] = { "top_xtal", "mpll_d2",
-						  "wedmcupll" };
-
-static const char *const da_xtp_glb_p0_parents[] = { "top_xtal",
-						     "net2pll_d8" };
-
-static const char *const mcusys_backup_625m_parents[] = { "top_xtal",
-							  "net1pll_d4" };
-
-static const char *const macsec_parents[] = { "top_xtal", "sgmpll",
-					      "net1pll_d8" };
-
-static const char *const netsys_tops_400m_parents[] = { "top_xtal",
-							"net2pll_d2" };
-
-static const char *const eth_mii_parents[] = { "top_xtal_d2",
-					       "net2pll_d4_d8" };
-
-static const struct mtk_mux top_muxes[] = {
-	/* CLK_CFG_0 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents,
-			     0x000, 0x004, 0x008, 0, 2, 7, 0x1c0, 0),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel",
-			     netsys_500m_parents, 0x000, 0x004, 0x008, 8, 2,
-			     15, 0x1C0, 1),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel",
-			     netsys_2x_parents, 0x000, 0x004, 0x008, 16, 2, 23,
-			     0x1C0, 2),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel",
-			     netsys_gsw_parents, 0x000, 0x004, 0x008, 24, 2,
-			     31, 0x1C0, 3),
-	/* CLK_CFG_1 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_GMII_SEL, "eth_gmii_sel",
-			     eth_gmii_parents, 0x010, 0x014, 0x018, 0, 1, 7,
-			     0x1C0, 4),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel",
-			     netsys_mcu_parents, 0x010, 0x014, 0x018, 8, 3, 15,
-			     0x1C0, 5),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PAO_2X_SEL, "netsys_pao_2x_sel",
-			     netsys_mcu_parents, 0x010, 0x014, 0x018, 16, 3,
-			     23, 0x1C0, 6),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP197_SEL, "eip197_sel", eip197_parents,
-			     0x010, 0x014, 0x018, 24, 3, 31, 0x1c0, 7),
-	/* CLK_CFG_2 */
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_INFRA_SEL, "axi_infra_sel",
-				   axi_infra_parents, 0x020, 0x024, 0x028, 0,
-				   1, 7, 0x1C0, 8, CLK_IS_CRITICAL),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x020,
-			     0x024, 0x028, 8, 2, 15, 0x1c0, 9),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel",
-			     emmc_250m_parents, 0x020, 0x024, 0x028, 16, 2, 23,
-			     0x1C0, 10),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel",
-			     emmc_400m_parents, 0x020, 0x024, 0x028, 24, 3, 31,
-			     0x1C0, 11),
-	/* CLK_CFG_3 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x030,
-			     0x034, 0x038, 0, 3, 7, 0x1c0, 12),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents,
-			     0x030, 0x034, 0x038, 8, 3, 15, 0x1c0, 13),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents,
-			     0x030, 0x034, 0x038, 16, 3, 23, 0x1c0, 14),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents,
-			     0x030, 0x034, 0x038, 24, 3, 31, 0x1c0, 15),
-	/* CLK_CFG_4 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x040,
-			     0x044, 0x048, 0, 3, 7, 0x1c0, 16),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x040,
-			     0x044, 0x048, 8, 2, 15, 0x1c0, 17),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PCIE_MBIST_250M_SEL,
-			     "pcie_mbist_250m_sel", pcie_mbist_250m_parents,
-			     0x040, 0x044, 0x048, 16, 1, 23, 0x1C0, 18),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_sel",
-			     pextp_tl_ck_parents, 0x040, 0x044, 0x048, 24, 3,
-			     31, 0x1C0, 19),
-	/* CLK_CFG_5 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_p1_sel",
-			     pextp_tl_ck_parents, 0x050, 0x054, 0x058, 0, 3, 7,
-			     0x1C0, 20),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P2_SEL, "pextp_tl_p2_sel",
-			     pextp_tl_ck_parents, 0x050, 0x054, 0x058, 8, 3,
-			     15, 0x1C0, 21),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P3_SEL, "pextp_tl_p3_sel",
-			     pextp_tl_ck_parents, 0x050, 0x054, 0x058, 16, 3,
-			     23, 0x1C0, 22),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_SEL, "usb_sys_sel",
-			     eth_gmii_parents, 0x050, 0x054, 0x058, 24, 1, 31,
-			     0x1C0, 23),
-	/* CLK_CFG_6 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel",
-			     eth_gmii_parents, 0x060, 0x064, 0x068, 0, 1, 7,
-			     0x1C0, 24),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_SEL, "usb_xhci_sel",
-			     eth_gmii_parents, 0x060, 0x064, 0x068, 8, 1, 15,
-			     0x1C0, 25),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel",
-			     eth_gmii_parents, 0x060, 0x064, 0x068, 16, 1, 23,
-			     0x1C0, 26),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel",
-			     usb_frmcnt_parents, 0x060, 0x064, 0x068, 24, 1,
-			     31, 0x1C0, 27),
-	/* CLK_CFG_7 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_P1_SEL, "usb_frmcnt_p1_sel",
-			     usb_frmcnt_parents, 0x070, 0x074, 0x078, 0, 1, 7,
-			     0x1C0, 28),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x070,
-			     0x074, 0x078, 8, 1, 15, 0x1c0, 29),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents,
-			     0x070, 0x074, 0x078, 16, 1, 23, 0x1c0, 30),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents,
-			     0x070, 0x074, 0x078, 24, 2, 31, 0x1c4, 0),
-	/* CLK_CFG_8 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents,
-			     0x080, 0x084, 0x088, 0, 1, 7, 0x1c4, 1),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SSPXTP_SEL, "sspxtp_sel", sspxtp_parents,
-			     0x080, 0x084, 0x088, 8, 1, 15, 0x1c4, 2),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_PHY_SEL, "usb_phy_sel",
-			     sspxtp_parents, 0x080, 0x084, 0x088, 16, 1, 23,
-			     0x1c4, 3),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_0_SEL, "usxgmii_sbus_0_sel",
-			     usxgmii_sbus_0_parents, 0x080, 0x084, 0x088, 24,
-			     1, 31, 0x1C4, 4),
-	/* CLK_CFG_9 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_1_SEL, "usxgmii_sbus_1_sel",
-			     usxgmii_sbus_0_parents, 0x090, 0x094, 0x098, 0, 1,
-			     7, 0x1C4, 5),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents,
-			     0x090, 0x094, 0x098, 8, 1, 15, 0x1c4, 6),
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel",
-				   usxgmii_sbus_0_parents, 0x090, 0x094, 0x098,
-				   16, 1, 23, 0x1C4, 7, CLK_IS_CRITICAL),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents,
-			     0x090, 0x094, 0x098, 24, 1, 31, 0x1c4, 8),
-	/* CLK_CFG_10 */
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel",
-				   usxgmii_sbus_0_parents, 0x0a0, 0x0a4, 0x0a8,
-				   0, 1, 7, 0x1C4, 9, CLK_IS_CRITICAL),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_0_XTAL_SEL, "xfi_phy_0_xtal_sel",
-			     sspxtp_parents, 0x0a0, 0x0a4, 0x0a8, 8, 1, 15,
-			     0x1C4, 10),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_1_XTAL_SEL, "xfi_phy_1_xtal_sel",
-			     sspxtp_parents, 0x0a0, 0x0a4, 0x0a8, 16, 1, 23,
-			     0x1C4, 11),
-	/* CLK_CFG_11 */
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel",
-				   axi_infra_parents, 0x0a0, 0x0a4, 0x0a8, 24,
-				   1, 31, 0x1C4, 12, CLK_IS_CRITICAL),
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel",
-				   sysapb_parents, 0x0b0, 0x0b4, 0x0b8, 0, 1,
-				   7, 0x1c4, 13, CLK_IS_CRITICAL),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel",
-			     eth_refck_50m_parents, 0x0b0, 0x0b4, 0x0b8, 8, 1,
-			     15, 0x1C4, 14),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel",
-			     eth_sys_200m_parents, 0x0b0, 0x0b4, 0x0b8, 16, 1,
-			     23, 0x1C4, 15),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_SEL, "eth_sys_sel",
-			     pcie_mbist_250m_parents, 0x0b0, 0x0b4, 0x0b8, 24,
-			     1, 31, 0x1C4, 16),
-	/* CLK_CFG_12 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel",
-			     eth_xgmii_parents, 0x0c0, 0x0c4, 0x0c8, 0, 2, 7,
-			     0x1C4, 17),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_BUS_TOPS_SEL, "bus_tops_sel",
-			     bus_tops_parents, 0x0c0, 0x0c4, 0x0c8, 8, 2, 15,
-			     0x1C4, 18),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_TOPS_SEL, "npu_tops_sel",
-			     npu_tops_parents, 0x0c0, 0x0c4, 0x0c8, 16, 1, 23,
-			     0x1C4, 19),
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel",
-				   sspxtp_parents, 0x0c0, 0x0c4, 0x0c8, 24, 1,
-				   31, 0x1C4, 20, CLK_IS_CRITICAL),
-	/* CLK_CFG_13 */
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
-				   dramc_md32_parents, 0x0d0, 0x0d4, 0x0d8, 0,
-				   2, 7, 0x1C4, 21, CLK_IS_CRITICAL),
-	MUX_GATE_CLR_SET_UPD_FLAGS(
-		CLK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", sspxtp_parents,
-		0x0d0, 0x0d4, 0x0d8, 8, 1, 15, 0x1C4, 22, CLK_IS_CRITICAL),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P0_SEL, "pextp_p0_sel",
-			     sspxtp_parents, 0x0d0, 0x0d4, 0x0d8, 16, 1, 23,
-			     0x1C4, 23),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P1_SEL, "pextp_p1_sel",
-			     sspxtp_parents, 0x0d0, 0x0d4, 0x0d8, 24, 1, 31,
-			     0x1C4, 24),
-	/* CLK_CFG_14 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P2_SEL, "pextp_p2_sel",
-			     sspxtp_parents, 0x0e0, 0x0e4, 0x0e8, 0, 1, 7,
-			     0x1C4, 25),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P3_SEL, "pextp_p3_sel",
-			     sspxtp_parents, 0x0e0, 0x0e4, 0x0e8, 8, 1, 15,
-			     0x1C4, 26),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel",
-			     da_xtp_glb_p0_parents, 0x0e0, 0x0e4, 0x0e8, 16, 1,
-			     23, 0x1C4, 27),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel",
-			     da_xtp_glb_p0_parents, 0x0e0, 0x0e4, 0x0e8, 24, 1,
-			     31, 0x1C4, 28),
-	/* CLK_CFG_15 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P2_SEL, "da_xtp_glb_p2_sel",
-			     da_xtp_glb_p0_parents, 0x0f0, 0x0f4, 0x0f8, 0, 1,
-			     7, 0x1C4, 29),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P3_SEL, "da_xtp_glb_p3_sel",
-			     da_xtp_glb_p0_parents, 0x0f0, 0x0f4, 0x0f8, 8, 1,
-			     15, 0x1C4, 30),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_CKM_SEL, "ckm_sel", sspxtp_parents, 0x0F0,
-			     0x0f4, 0x0f8, 16, 1, 23, 0x1c8, 0),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_SEL, "da_sel", sspxtp_parents, 0x0f0,
-			     0x0f4, 0x0f8, 24, 1, 31, 0x1C8, 1),
-	/* CLK_CFG_16 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_SEL, "pextp_sel", sspxtp_parents,
-			     0x0100, 0x104, 0x108, 0, 1, 7, 0x1c8, 2),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_TOPS_P2_26M_SEL, "tops_p2_26m_sel",
-			     sspxtp_parents, 0x0100, 0x104, 0x108, 8, 1, 15,
-			     0x1C8, 3),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_MCUSYS_BACKUP_625M_SEL,
-			     "mcusys_backup_625m_sel",
-			     mcusys_backup_625m_parents, 0x0100, 0x104, 0x108,
-			     16, 1, 23, 0x1C8, 4),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SYNC_250M_SEL,
-			     "netsys_sync_250m_sel", pcie_mbist_250m_parents,
-			     0x0100, 0x104, 0x108, 24, 1, 31, 0x1c8, 5),
-	/* CLK_CFG_17 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_MACSEC_SEL, "macsec_sel", macsec_parents,
-			     0x0110, 0x114, 0x118, 0, 2, 7, 0x1c8, 6),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_TOPS_400M_SEL,
-			     "netsys_tops_400m_sel", netsys_tops_400m_parents,
-			     0x0110, 0x114, 0x118, 8, 1, 15, 0x1c8, 7),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PPEFB_250M_SEL,
-			     "netsys_ppefb_250m_sel", pcie_mbist_250m_parents,
-			     0x0110, 0x114, 0x118, 16, 1, 23, 0x1c8, 8),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_WARP_SEL, "netsys_warp_sel",
-			     netsys_parents, 0x0110, 0x114, 0x118, 24, 2, 31,
-			     0x1C8, 9),
-	/* CLK_CFG_18 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_MII_SEL, "eth_mii_sel",
-			     eth_mii_parents, 0x0120, 0x124, 0x128, 0, 1, 7,
-			     0x1c8, 10),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_SEL, "ck_npu_sel", netsys_2x_parents,
-			     0x0120, 0x124, 0x128, 8, 2, 15, 0x1c8, 11),
-};
-
-static const struct mtk_composite top_aud_divs[] = {
-	DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud_sel", 0x0420, 0, 0x0420,
-		 8, 8),
-};
-
-static const struct mtk_clk_desc topck_desc = {
-	.fixed_clks = top_fixed_clks,
-	.num_fixed_clks = ARRAY_SIZE(top_fixed_clks),
-	.factor_clks = top_divs,
-	.num_factor_clks = ARRAY_SIZE(top_divs),
-	.mux_clks = top_muxes,
-	.num_mux_clks = ARRAY_SIZE(top_muxes),
-	.composite_clks = top_aud_divs,
-	.num_composite_clks = ARRAY_SIZE(top_aud_divs),
-	.clk_lock = &mt7988_clk_lock,
-};
-
-static const char *const mcu_bus_div_parents[] = { "top_xtal", "ccipll2_b",
-						   "net1pll_d4" };
-
-static const char *const mcu_arm_div_parents[] = { "top_xtal", "arm_b",
-						   "net1pll_d4" };
-
-static struct mtk_composite mcu_muxes[] = {
-	/* bus_pll_divider_cfg */
-	MUX_GATE_FLAGS(CLK_MCU_BUS_DIV_SEL, "mcu_bus_div_sel",
-		       mcu_bus_div_parents, 0x7C0, 9, 2, -1, CLK_IS_CRITICAL),
-	/* mp2_pll_divider_cfg */
-	MUX_GATE_FLAGS(CLK_MCU_ARM_DIV_SEL, "mcu_arm_div_sel",
-		       mcu_arm_div_parents, 0x7A8, 9, 2, -1, CLK_IS_CRITICAL),
-};
-
-static const struct mtk_clk_desc mcusys_desc = {
-	.composite_clks = mcu_muxes,
-	.num_composite_clks = ARRAY_SIZE(mcu_muxes),
-};
-
-static const struct of_device_id of_match_clk_mt7988_topckgen[] = {
-	{ .compatible = "mediatek,mt7988-topckgen", .data = &topck_desc },
-	{ .compatible = "mediatek,mt7988-mcusys", .data = &mcusys_desc },
-	{ /* sentinel */ }
-};
-MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_topckgen);
-
-static struct platform_driver clk_mt7988_topckgen_drv = {
-	.probe = mtk_clk_simple_probe,
-	.remove = mtk_clk_simple_remove,
-	.driver = {
-		.name = "clk-mt7988-topckgen",
-		.of_match_table = of_match_clk_mt7988_topckgen,
-	},
-};
-module_platform_driver(clk_mt7988_topckgen_drv);
-MODULE_LICENSE("GPL");
diff --git a/target/linux/mediatek/files-6.1/drivers/net/phy/mediatek-2p5ge.c b/target/linux/mediatek/files-6.1/drivers/net/phy/mediatek-2p5ge.c
index c12e6b8eb6f8f6..e2e06d1ecac8cf 100644
--- a/target/linux/mediatek/files-6.1/drivers/net/phy/mediatek-2p5ge.c
+++ b/target/linux/mediatek/files-6.1/drivers/net/phy/mediatek-2p5ge.c
@@ -7,37 +7,50 @@
 #include <linux/of_platform.h>
 #include <linux/pinctrl/consumer.h>
 #include <linux/phy.h>
+#include <linux/pm_domain.h>
+#include <linux/pm_runtime.h>
 
-#define MEDAITEK_2P5GE_PHY_DMB_FW "mediatek/mediatek-2p5ge-phy-dmb.bin"
-#define MEDIATEK_2P5GE_PHY_PMB_FW "mediatek/mediatek-2p5ge-phy-pmb.bin"
+#define MT7988_2P5GE_PMB "mediatek/mt7988/i2p5ge-phy-pmb.bin"
 
-#define MD32_EN_CFG			0x18
-#define   MD32_EN			BIT(0)
+#define MD32_EN					BIT(0)
+#define PMEM_PRIORITY				BIT(8)
+#define DMEM_PRIORITY				BIT(16)
 
-#define BASE100T_STATUS_EXTEND		0x10
-#define BASE1000T_STATUS_EXTEND		0x11
-#define EXTEND_CTRL_AND_STATUS		0x16
+#define BASE100T_STATUS_EXTEND			0x10
+#define BASE1000T_STATUS_EXTEND			0x11
+#define EXTEND_CTRL_AND_STATUS			0x16
 
-#define PHY_AUX_CTRL_STATUS		0x1d
-#define   PHY_AUX_DPX_MASK		GENMASK(5, 5)
-#define   PHY_AUX_SPEED_MASK		GENMASK(4, 2)
+#define PHY_AUX_CTRL_STATUS			0x1d
+#define   PHY_AUX_DPX_MASK			GENMASK(5, 5)
+#define   PHY_AUX_SPEED_MASK			GENMASK(4, 2)
 
 /* Registers on MDIO_MMD_VEND1 */
-#define MTK_PHY_LINK_STATUS_MISC	0xa2
-#define   MTK_PHY_FDX_ENABLE		BIT(5)
+#define MTK_PHY_LINK_STATUS_MISC		0xa2
+#define   MTK_PHY_FDX_ENABLE			BIT(5)
+
+#define MTK_PHY_LPI_PCS_DSP_CTRL		0x121
+#define   MTK_PHY_LPI_SIG_EN_LO_THRESH100_MASK	GENMASK(12, 8)
 
 /* Registers on MDIO_MMD_VEND2 */
-#define MTK_PHY_LED0_ON_CTRL		0x24
-#define   MTK_PHY_LED0_ON_LINK1000	BIT(0)
-#define   MTK_PHY_LED0_ON_LINK100	BIT(1)
-#define   MTK_PHY_LED0_ON_LINK10	BIT(2)
-#define   MTK_PHY_LED0_ON_LINK2500	BIT(7)
-#define   MTK_PHY_LED0_POLARITY		BIT(14)
-
-#define MTK_PHY_LED1_ON_CTRL		0x26
-#define   MTK_PHY_LED1_ON_FDX		BIT(4)
-#define   MTK_PHY_LED1_ON_HDX		BIT(5)
-#define   MTK_PHY_LED1_POLARITY		BIT(14)
+#define MTK_PHY_LED0_ON_CTRL			0x24
+#define   MTK_PHY_LED0_ON_LINK1000		BIT(0)
+#define   MTK_PHY_LED0_ON_LINK100		BIT(1)
+#define   MTK_PHY_LED0_ON_LINK10		BIT(2)
+#define   MTK_PHY_LED0_ON_LINK2500		BIT(7)
+#define   MTK_PHY_LED0_POLARITY			BIT(14)
+
+#define MTK_PHY_LED1_ON_CTRL			0x26
+#define   MTK_PHY_LED1_ON_FDX			BIT(4)
+#define   MTK_PHY_LED1_ON_HDX			BIT(5)
+#define   MTK_PHY_LED1_POLARITY			BIT(14)
+
+#define MTK_EXT_PAGE_ACCESS			0x1f
+#define MTK_PHY_PAGE_STANDARD			0x0000
+#define MTK_PHY_PAGE_EXTENDED_52B5		0x52b5
+
+struct mtk_i2p5ge_phy_priv {
+	bool fw_loaded;
+};
 
 enum {
 	PHY_AUX_SPD_10 = 0,
@@ -46,67 +59,89 @@ enum {
 	PHY_AUX_SPD_2500,
 };
 
-static int mt798x_2p5ge_phy_config_init(struct phy_device *phydev)
+static int mtk_2p5ge_phy_read_page(struct phy_device *phydev)
 {
-	int ret;
-	int i;
+	return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
+}
+
+static int mtk_2p5ge_phy_write_page(struct phy_device *phydev, int page)
+{
+	return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page);
+}
+
+static int mt7988_2p5ge_phy_probe(struct phy_device *phydev)
+{
+	struct mtk_i2p5ge_phy_priv *phy_priv;
+
+	phy_priv = devm_kzalloc(&phydev->mdio.dev,
+				sizeof(struct mtk_i2p5ge_phy_priv), GFP_KERNEL);
+	if (!phy_priv)
+		return -ENOMEM;
+
+	phydev->priv = phy_priv;
+
+	return 0;
+}
+
+static int mt7988_2p5ge_phy_config_init(struct phy_device *phydev)
+{
+	int ret, i;
 	const struct firmware *fw;
 	struct device *dev = &phydev->mdio.dev;
 	struct device_node *np;
-	void __iomem *dmb_addr;
 	void __iomem *pmb_addr;
-	void __iomem *mcucsr_base;
+	void __iomem *md32_en_cfg_base;
+	struct mtk_i2p5ge_phy_priv *phy_priv = phydev->priv;
 	u16 reg;
 	struct pinctrl *pinctrl;
 
-	np = of_find_compatible_node(NULL, NULL, "mediatek,2p5gphy-fw");
-	if (!np)
-		return -ENOENT;
+	if (!phy_priv->fw_loaded) {
+		np = of_find_compatible_node(NULL, NULL, "mediatek,2p5gphy-fw");
+		if (!np)
+			return -ENOENT;
+		pmb_addr = of_iomap(np, 0);
+		if (!pmb_addr)
+			return -ENOMEM;
+		md32_en_cfg_base = of_iomap(np, 1);
+		if (!md32_en_cfg_base)
+			return -ENOMEM;
+
+		ret = request_firmware(&fw, MT7988_2P5GE_PMB, dev);
+		if (ret) {
+			dev_err(dev, "failed to load firmware: %s, ret: %d\n",
+				MT7988_2P5GE_PMB, ret);
+			return ret;
+		}
+
+		reg = readw(md32_en_cfg_base);
+		if (reg & MD32_EN) {
+			phy_set_bits(phydev, 0, BIT(15));
+			usleep_range(10000, 11000);
+		}
+		phy_set_bits(phydev, 0, BIT(11));
 
-	dmb_addr = of_iomap(np, 0);
-	if (!dmb_addr)
-		return -ENOMEM;
-	pmb_addr = of_iomap(np, 1);
-	if (!pmb_addr)
-		return -ENOMEM;
-	mcucsr_base = of_iomap(np, 2);
-	if (!mcucsr_base)
-		return -ENOMEM;
+		/* Write magic number to safely stall MCU */
+		phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x800e, 0x1100);
+		phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x800f, 0x00df);
 
-	ret = request_firmware(&fw, MEDAITEK_2P5GE_PHY_DMB_FW, dev);
-	if (ret) {
-		dev_err(dev, "failed to load firmware: %s, ret: %d\n",
-			MEDAITEK_2P5GE_PHY_DMB_FW, ret);
-		return ret;
-	}
-	for (i = 0; i < fw->size - 1; i += 4)
-		writel(*((uint32_t *)(fw->data + i)), dmb_addr + i);
-	release_firmware(fw);
-
-	ret = request_firmware(&fw, MEDIATEK_2P5GE_PHY_PMB_FW, dev);
-	if (ret) {
-		dev_err(dev, "failed to load firmware: %s, ret: %d\n",
-			MEDIATEK_2P5GE_PHY_PMB_FW, ret);
-		return ret;
-	}
-	for (i = 0; i < fw->size - 1; i += 4)
-		writel(*((uint32_t *)(fw->data + i)), pmb_addr + i);
-	release_firmware(fw);
+		for (i = 0; i < fw->size - 1; i += 4)
+			writel(*((uint32_t *)(fw->data + i)), pmb_addr + i);
+		release_firmware(fw);
 
-	reg = readw(mcucsr_base + MD32_EN_CFG);
-	writew(reg | MD32_EN, mcucsr_base + MD32_EN_CFG);
-	dev_dbg(dev, "Firmware loading/trigger ok.\n");
+		writew(reg & ~MD32_EN, md32_en_cfg_base);
+		writew(reg | MD32_EN, md32_en_cfg_base);
+		phy_set_bits(phydev, 0, BIT(15));
+		dev_info(dev, "Firmware loading/trigger ok.\n");
 
-	/* Setup LED */
-	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
-			   MTK_PHY_LED0_POLARITY);
+		phy_priv->fw_loaded = true;
+	}
 
+	/* Setup LED */
 	phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
 			 MTK_PHY_LED0_ON_LINK10 |
 			 MTK_PHY_LED0_ON_LINK100 |
 			 MTK_PHY_LED0_ON_LINK1000 |
 			 MTK_PHY_LED0_ON_LINK2500);
-
 	phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL,
 			 MTK_PHY_LED1_ON_FDX | MTK_PHY_LED1_ON_HDX);
 
@@ -116,10 +151,20 @@ static int mt798x_2p5ge_phy_config_init(struct phy_device *phydev)
 		return PTR_ERR(pinctrl);
 	}
 
+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LPI_PCS_DSP_CTRL,
+		       MTK_PHY_LPI_SIG_EN_LO_THRESH100_MASK, 0);
+
+	/* Enable 16-bit next page exchange bit if 1000-BT isn't advertizing */
+	phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
+	__phy_write(phydev, 0x11, 0xfbfa);
+	__phy_write(phydev, 0x12, 0xc3);
+	__phy_write(phydev, 0x10, 0x87f8);
+	phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
+
 	return 0;
 }
 
-static int mt798x_2p5ge_phy_config_aneg(struct phy_device *phydev)
+static int mt7988_2p5ge_phy_config_aneg(struct phy_device *phydev)
 {
 	bool changed = false;
 	u32 adv;
@@ -152,7 +197,7 @@ static int mt798x_2p5ge_phy_config_aneg(struct phy_device *phydev)
 	return genphy_c45_check_and_restart_aneg(phydev, changed);
 }
 
-static int mt798x_2p5ge_phy_get_features(struct phy_device *phydev)
+static int mt7988_2p5ge_phy_get_features(struct phy_device *phydev)
 {
 	int ret;
 
@@ -160,7 +205,7 @@ static int mt798x_2p5ge_phy_get_features(struct phy_device *phydev)
 	if (ret)
 		return ret;
 
-	/* We don't support HDX at MAC layer on mt798x.
+	/* We don't support HDX at MAC layer on mt7988.
 	 * So mask phy's HDX capabilities, too.
 	 */
 	linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
@@ -176,7 +221,7 @@ static int mt798x_2p5ge_phy_get_features(struct phy_device *phydev)
 	return 0;
 }
 
-static int mt798x_2p5ge_phy_read_status(struct phy_device *phydev)
+static int mt7988_2p5ge_phy_read_status(struct phy_device *phydev)
 {
 	int ret;
 
@@ -189,9 +234,6 @@ static int mt798x_2p5ge_phy_read_status(struct phy_device *phydev)
 	phydev->pause = 0;
 	phydev->asym_pause = 0;
 
-	if (!phydev->link)
-		return 0;
-
 	if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) {
 		ret = genphy_c45_read_lpa(phydev);
 		if (ret < 0)
@@ -222,7 +264,6 @@ static int mt798x_2p5ge_phy_read_status(struct phy_device *phydev)
 		break;
 	case PHY_AUX_SPD_2500:
 		phydev->speed = SPEED_2500;
-		phydev->duplex = DUPLEX_FULL; /* 2.5G must be FDX */
 		break;
 	}
 
@@ -231,18 +272,32 @@ static int mt798x_2p5ge_phy_read_status(struct phy_device *phydev)
 		return ret;
 
 	phydev->duplex = (ret & MTK_PHY_FDX_ENABLE) ? DUPLEX_FULL : DUPLEX_HALF;
+	/* FIXME: The current firmware always enables rate adaptation mode. */
+	phydev->rate_matching = RATE_MATCH_PAUSE;
 
 	return 0;
 }
 
+static int mt7988_2p5ge_phy_get_rate_matching(struct phy_device *phydev,
+					      phy_interface_t iface)
+{
+	return RATE_MATCH_PAUSE;
+}
+
 static struct phy_driver mtk_gephy_driver[] = {
 	{
-		PHY_ID_MATCH_EXACT(0x00339c11),
+		PHY_ID_MATCH_MODEL(0x00339c11),
 		.name		= "MediaTek MT798x 2.5GbE PHY",
-		.config_init	= mt798x_2p5ge_phy_config_init,
-		.config_aneg    = mt798x_2p5ge_phy_config_aneg,
-		.get_features	= mt798x_2p5ge_phy_get_features,
-		.read_status	= mt798x_2p5ge_phy_read_status,
+		.probe		= mt7988_2p5ge_phy_probe,
+		.config_init	= mt7988_2p5ge_phy_config_init,
+		.config_aneg    = mt7988_2p5ge_phy_config_aneg,
+		.get_features	= mt7988_2p5ge_phy_get_features,
+		.read_status	= mt7988_2p5ge_phy_read_status,
+		.get_rate_matching	= mt7988_2p5ge_phy_get_rate_matching,
+		.suspend	= genphy_suspend,
+		.resume		= genphy_resume,
+		.read_page	= mtk_2p5ge_phy_read_page,
+		.write_page	= mtk_2p5ge_phy_write_page,
 	},
 };
 
@@ -258,5 +313,4 @@ MODULE_AUTHOR("SkyLake Huang <SkyLake.Huang@mediatek.com>");
 MODULE_LICENSE("GPL");
 
 MODULE_DEVICE_TABLE(mdio, mtk_2p5ge_phy_tbl);
-MODULE_FIRMWARE(MEDAITEK_2P5GE_PHY_DMB_FW);
-MODULE_FIRMWARE(MEDIATEK_2P5GE_PHY_PMB_FW);
+MODULE_FIRMWARE(MT7988_2P5GE_PMB);
diff --git a/target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7988.c b/target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7988.c
index 49c0be1bba0cf2..9f9291124522c9 100644
--- a/target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7988.c
+++ b/target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7988.c
@@ -596,6 +596,51 @@ static const struct mtk_pin_field_calc mt7988_pin_r1_range[] = {
 	PIN_FIELD_BASE(83, 83, 1, 0x90, 0x10, 15, 1),
 };
 
+static const unsigned int mt7988_pull_type[] = {
+	MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PU_PD_TYPE,    /*7*/
+	MTK_PULL_PU_PD_TYPE,    /*8*/ MTK_PULL_PU_PD_TYPE,    /*9*/
+	MTK_PULL_PU_PD_TYPE,    /*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PU_PD_TYPE,    /*13*/
+	MTK_PULL_PU_PD_TYPE,    /*14*/ MTK_PULL_PD_TYPE,       /*15*/
+	MTK_PULL_PD_TYPE,       /*16*/ MTK_PULL_PD_TYPE,       /*17*/
+	MTK_PULL_PD_TYPE,       /*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PU_PD_TYPE,    /*63*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PUPD_R1R0_TYPE,/*69*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*70*/ MTK_PULL_PD_TYPE,       /*71*/
+	MTK_PULL_PD_TYPE,       /*72*/ MTK_PULL_PUPD_R1R0_TYPE,/*73*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,    /*75*/
+	MTK_PULL_PU_PD_TYPE,    /*76*/ MTK_PULL_PU_PD_TYPE,    /*77*/
+	MTK_PULL_PU_PD_TYPE,    /*78*/ MTK_PULL_PU_PD_TYPE,    /*79*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*80*/ MTK_PULL_PUPD_R1R0_TYPE,/*81*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*82*/ MTK_PULL_PUPD_R1R0_TYPE,/*83*/
+};
+
 static const struct mtk_pin_reg_calc mt7988_reg_cals[] = {
 	[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7988_pin_mode_range),
 	[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7988_pin_dir_range),
@@ -992,11 +1037,11 @@ static int mt7988_uart2_3_funcs[] = { 3, 3, 3, 3 };
 static int mt7988_uart1_2_pins[] = { 80, 81, 82, 83 };
 static int mt7988_uart1_2_funcs[] = { 1, 1, 1, 1 };
 
+static int mt7988_uart1_2_lite_pins[] = { 80, 81 };
+static int mt7988_uart1_2_lite_funcs[] = { 1, 1 };
+
 static int mt7988_tops_uart1_2_pins[] = { 80, 81 };
-static int mt7988_tops_uart1_2_funcs[] = {
-	4,
-	4,
-};
+static int mt7988_tops_uart1_2_funcs[] = { 4, 4, };
 
 static int mt7988_net_wo0_uart_txd_1_pins[] = { 80 };
 static int mt7988_net_wo0_uart_txd_1_funcs[] = { 3 };
@@ -1254,6 +1299,8 @@ static const struct group_desc mt7988_groups[] = {
 	PINCTRL_PIN_GROUP("pcie_wake_n2_1", mt7988_pcie_wake_n2_1),
 	/*  @GPIO(80,81,82,83) uart1_2 */
 	PINCTRL_PIN_GROUP("uart1_2", mt7988_uart1_2),
+	/*  @GPIO(80,81) uart1_2_lite */
+	PINCTRL_PIN_GROUP("uart1_2_lite", mt7988_uart1_2_lite),
 	/*  @GPIO(80) pwm2 */
 	PINCTRL_PIN_GROUP("pwm2", mt7988_pwm2),
 	/*  @GPIO(81) pwm3 */
@@ -1363,6 +1410,7 @@ static const char * const mt7988_uart_groups[] = {
 	"uart1_1",
 	"uart2_3",
 	"uart1_2",
+	"uart1_2_lite",
 	"tops_uart1_2",
 	"net_wo0_uart_txd_1",
 	"net_wo1_uart_txd_1",
@@ -1433,6 +1481,9 @@ static struct mtk_pin_soc mt7988_data = {
 	.bias_disable_get = mtk_pinconf_bias_disable_get,
 	.bias_set = mtk_pinconf_bias_set,
 	.bias_get = mtk_pinconf_bias_get,
+	.pull_type = mt7988_pull_type,
+	.bias_set_combo = mtk_pinconf_bias_set_combo,
+	.bias_get_combo = mtk_pinconf_bias_get_combo,
 	.drive_set = mtk_pinconf_drive_set_rev1,
 	.drive_get = mtk_pinconf_drive_get_rev1,
 	.adv_pull_get = mtk_pinconf_adv_pull_get,
diff --git a/target/linux/mediatek/files-6.1/include/dt-bindings/clock/mediatek,mt7988-clk.h b/target/linux/mediatek/files-6.1/include/dt-bindings/clock/mediatek,mt7988-clk.h
deleted file mode 100644
index 77cfea4a8eaf6a..00000000000000
--- a/target/linux/mediatek/files-6.1/include/dt-bindings/clock/mediatek,mt7988-clk.h
+++ /dev/null
@@ -1,276 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
-/*
- * Copyright (c) 2023 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
- */
-
-#ifndef _DT_BINDINGS_CLK_MT7988_H
-#define _DT_BINDINGS_CLK_MT7988_H
-
-/* APMIXEDSYS */
-
-#define CLK_APMIXED_NETSYSPLL  0
-#define CLK_APMIXED_MPLL       1
-#define CLK_APMIXED_MMPLL      2
-#define CLK_APMIXED_APLL2      3
-#define CLK_APMIXED_NET1PLL    4
-#define CLK_APMIXED_NET2PLL    5
-#define CLK_APMIXED_WEDMCUPLL  6
-#define CLK_APMIXED_SGMPLL     7
-#define CLK_APMIXED_ARM_B      8
-#define CLK_APMIXED_CCIPLL2_B  9
-#define CLK_APMIXED_USXGMIIPLL 10
-#define CLK_APMIXED_MSDCPLL    11
-
-/* TOPCKGEN */
-
-#define CLK_TOP_XTAL		       0
-#define CLK_TOP_XTAL_D2		       1
-#define CLK_TOP_RTC_32K		       2
-#define CLK_TOP_RTC_32P7K	       3
-#define CLK_TOP_MPLL_D2		       4
-#define CLK_TOP_MPLL_D3_D2	       5
-#define CLK_TOP_MPLL_D4		       6
-#define CLK_TOP_MPLL_D8		       7
-#define CLK_TOP_MPLL_D8_D2	       8
-#define CLK_TOP_MMPLL_D2	       9
-#define CLK_TOP_MMPLL_D3_D5	       10
-#define CLK_TOP_MMPLL_D4	       11
-#define CLK_TOP_MMPLL_D6_D2	       12
-#define CLK_TOP_MMPLL_D8	       13
-#define CLK_TOP_APLL2_D4	       14
-#define CLK_TOP_NET1PLL_D4	       15
-#define CLK_TOP_NET1PLL_D5	       16
-#define CLK_TOP_NET1PLL_D5_D2	       17
-#define CLK_TOP_NET1PLL_D5_D4	       18
-#define CLK_TOP_NET1PLL_D8	       19
-#define CLK_TOP_NET1PLL_D8_D2	       20
-#define CLK_TOP_NET1PLL_D8_D4	       21
-#define CLK_TOP_NET1PLL_D8_D8	       22
-#define CLK_TOP_NET1PLL_D8_D16	       23
-#define CLK_TOP_NET2PLL_D2	       24
-#define CLK_TOP_NET2PLL_D4	       25
-#define CLK_TOP_NET2PLL_D4_D4	       26
-#define CLK_TOP_NET2PLL_D4_D8	       27
-#define CLK_TOP_NET2PLL_D6	       28
-#define CLK_TOP_NET2PLL_D8	       29
-#define CLK_TOP_NETSYS_SEL	       30
-#define CLK_TOP_NETSYS_500M_SEL	       31
-#define CLK_TOP_NETSYS_2X_SEL	       32
-#define CLK_TOP_NETSYS_GSW_SEL	       33
-#define CLK_TOP_ETH_GMII_SEL	       34
-#define CLK_TOP_NETSYS_MCU_SEL	       35
-#define CLK_TOP_NETSYS_PAO_2X_SEL      36
-#define CLK_TOP_EIP197_SEL	       37
-#define CLK_TOP_AXI_INFRA_SEL	       38
-#define CLK_TOP_UART_SEL	       39
-#define CLK_TOP_EMMC_250M_SEL	       40
-#define CLK_TOP_EMMC_400M_SEL	       41
-#define CLK_TOP_SPI_SEL		       42
-#define CLK_TOP_SPIM_MST_SEL	       43
-#define CLK_TOP_NFI1X_SEL	       44
-#define CLK_TOP_SPINFI_SEL	       45
-#define CLK_TOP_PWM_SEL		       46
-#define CLK_TOP_I2C_SEL		       47
-#define CLK_TOP_PCIE_MBIST_250M_SEL    48
-#define CLK_TOP_PEXTP_TL_SEL	       49
-#define CLK_TOP_PEXTP_TL_P1_SEL	       50
-#define CLK_TOP_PEXTP_TL_P2_SEL	       51
-#define CLK_TOP_PEXTP_TL_P3_SEL	       52
-#define CLK_TOP_USB_SYS_SEL	       53
-#define CLK_TOP_USB_SYS_P1_SEL	       54
-#define CLK_TOP_USB_XHCI_SEL	       55
-#define CLK_TOP_USB_XHCI_P1_SEL	       56
-#define CLK_TOP_USB_FRMCNT_SEL	       57
-#define CLK_TOP_USB_FRMCNT_P1_SEL      58
-#define CLK_TOP_AUD_SEL		       59
-#define CLK_TOP_A1SYS_SEL	       60
-#define CLK_TOP_AUD_L_SEL	       61
-#define CLK_TOP_A_TUNER_SEL	       62
-#define CLK_TOP_SSPXTP_SEL	       63
-#define CLK_TOP_USB_PHY_SEL	       64
-#define CLK_TOP_USXGMII_SBUS_0_SEL     65
-#define CLK_TOP_USXGMII_SBUS_1_SEL     66
-#define CLK_TOP_SGM_0_SEL	       67
-#define CLK_TOP_SGM_SBUS_0_SEL	       68
-#define CLK_TOP_SGM_1_SEL	       69
-#define CLK_TOP_SGM_SBUS_1_SEL	       70
-#define CLK_TOP_XFI_PHY_0_XTAL_SEL     71
-#define CLK_TOP_XFI_PHY_1_XTAL_SEL     72
-#define CLK_TOP_SYSAXI_SEL	       73
-#define CLK_TOP_SYSAPB_SEL	       74
-#define CLK_TOP_ETH_REFCK_50M_SEL      75
-#define CLK_TOP_ETH_SYS_200M_SEL       76
-#define CLK_TOP_ETH_SYS_SEL	       77
-#define CLK_TOP_ETH_XGMII_SEL	       78
-#define CLK_TOP_BUS_TOPS_SEL	       79
-#define CLK_TOP_NPU_TOPS_SEL	       80
-#define CLK_TOP_DRAMC_SEL	       81
-#define CLK_TOP_DRAMC_MD32_SEL	       82
-#define CLK_TOP_INFRA_F26M_SEL	       83
-#define CLK_TOP_PEXTP_P0_SEL	       84
-#define CLK_TOP_PEXTP_P1_SEL	       85
-#define CLK_TOP_PEXTP_P2_SEL	       86
-#define CLK_TOP_PEXTP_P3_SEL	       87
-#define CLK_TOP_DA_XTP_GLB_P0_SEL      88
-#define CLK_TOP_DA_XTP_GLB_P1_SEL      89
-#define CLK_TOP_DA_XTP_GLB_P2_SEL      90
-#define CLK_TOP_DA_XTP_GLB_P3_SEL      91
-#define CLK_TOP_CKM_SEL		       92
-#define CLK_TOP_DA_SEL		       93
-#define CLK_TOP_PEXTP_SEL	       94
-#define CLK_TOP_TOPS_P2_26M_SEL	       95
-#define CLK_TOP_MCUSYS_BACKUP_625M_SEL 96
-#define CLK_TOP_NETSYS_SYNC_250M_SEL   97
-#define CLK_TOP_MACSEC_SEL	       98
-#define CLK_TOP_NETSYS_TOPS_400M_SEL   99
-#define CLK_TOP_NETSYS_PPEFB_250M_SEL  100
-#define CLK_TOP_NETSYS_WARP_SEL	       101
-#define CLK_TOP_ETH_MII_SEL	       102
-#define CLK_TOP_NPU_SEL		       103
-#define CLK_TOP_AUD_I2S_M	       104
-
-/* MCUSYS */
-
-#define CLK_MCU_BUS_DIV_SEL 0
-#define CLK_MCU_ARM_DIV_SEL 1
-
-/* INFRACFG_AO */
-
-#define CLK_INFRA_MUX_UART0_SEL		 0
-#define CLK_INFRA_MUX_UART1_SEL		 1
-#define CLK_INFRA_MUX_UART2_SEL		 2
-#define CLK_INFRA_MUX_SPI0_SEL		 3
-#define CLK_INFRA_MUX_SPI1_SEL		 4
-#define CLK_INFRA_MUX_SPI2_SEL		 5
-#define CLK_INFRA_PWM_SEL		 6
-#define CLK_INFRA_PWM_CK1_SEL		 7
-#define CLK_INFRA_PWM_CK2_SEL		 8
-#define CLK_INFRA_PWM_CK3_SEL		 9
-#define CLK_INFRA_PWM_CK4_SEL		 10
-#define CLK_INFRA_PWM_CK5_SEL		 11
-#define CLK_INFRA_PWM_CK6_SEL		 12
-#define CLK_INFRA_PWM_CK7_SEL		 13
-#define CLK_INFRA_PWM_CK8_SEL		 14
-#define CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 15
-#define CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 16
-#define CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 17
-#define CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 18
-
-/* INFRACFG */
-
-#define CLK_INFRA_PCIE_PERI_26M_CK_P0 19
-#define CLK_INFRA_PCIE_PERI_26M_CK_P1 20
-#define CLK_INFRA_PCIE_PERI_26M_CK_P2 21
-#define CLK_INFRA_PCIE_PERI_26M_CK_P3 22
-#define CLK_INFRA_66M_GPT_BCK	      23
-#define CLK_INFRA_66M_PWM_HCK	      24
-#define CLK_INFRA_66M_PWM_BCK	      25
-#define CLK_INFRA_66M_PWM_CK1	      26
-#define CLK_INFRA_66M_PWM_CK2	      27
-#define CLK_INFRA_66M_PWM_CK3	      28
-#define CLK_INFRA_66M_PWM_CK4	      29
-#define CLK_INFRA_66M_PWM_CK5	      30
-#define CLK_INFRA_66M_PWM_CK6	      31
-#define CLK_INFRA_66M_PWM_CK7	      32
-#define CLK_INFRA_66M_PWM_CK8	      33
-#define CLK_INFRA_133M_CQDMA_BCK      34
-#define CLK_INFRA_66M_AUD_SLV_BCK     35
-#define CLK_INFRA_AUD_26M	      36
-#define CLK_INFRA_AUD_L		      37
-#define CLK_INFRA_AUD_AUD	      38
-#define CLK_INFRA_AUD_EG2	      39
-#define CLK_INFRA_DRAMC_F26M	      40
-#define CLK_INFRA_133M_DBG_ACKM	      41
-#define CLK_INFRA_66M_AP_DMA_BCK      42
-#define CLK_INFRA_66M_SEJ_BCK	      43
-#define CLK_INFRA_PRE_CK_SEJ_F13M     44
-#define CLK_INFRA_26M_THERM_SYSTEM    45
-#define CLK_INFRA_I2C_BCK	      46
-#define CLK_INFRA_52M_UART0_CK	      47
-#define CLK_INFRA_52M_UART1_CK	      48
-#define CLK_INFRA_52M_UART2_CK	      49
-#define CLK_INFRA_NFI		      50
-#define CLK_INFRA_SPINFI	      51
-#define CLK_INFRA_66M_NFI_HCK	      52
-#define CLK_INFRA_104M_SPI0	      53
-#define CLK_INFRA_104M_SPI1	      54
-#define CLK_INFRA_104M_SPI2_BCK	      55
-#define CLK_INFRA_66M_SPI0_HCK	      56
-#define CLK_INFRA_66M_SPI1_HCK	      57
-#define CLK_INFRA_66M_SPI2_HCK	      58
-#define CLK_INFRA_66M_FLASHIF_AXI     59
-#define CLK_INFRA_RTC		      60
-#define CLK_INFRA_26M_ADC_BCK	      61
-#define CLK_INFRA_RC_ADC	      62
-#define CLK_INFRA_MSDC400	      63
-#define CLK_INFRA_MSDC2_HCK	      64
-#define CLK_INFRA_133M_MSDC_0_HCK     65
-#define CLK_INFRA_66M_MSDC_0_HCK      66
-#define CLK_INFRA_133M_CPUM_BCK	      67
-#define CLK_INFRA_BIST2FPC	      68
-#define CLK_INFRA_I2C_X16W_MCK_CK_P1  69
-#define CLK_INFRA_I2C_X16W_PCK_CK_P1  70
-#define CLK_INFRA_133M_USB_HCK	      71
-#define CLK_INFRA_133M_USB_HCK_CK_P1  72
-#define CLK_INFRA_66M_USB_HCK	      73
-#define CLK_INFRA_66M_USB_HCK_CK_P1   74
-#define CLK_INFRA_USB_SYS	      75
-#define CLK_INFRA_USB_SYS_CK_P1	      76
-#define CLK_INFRA_USB_REF	      77
-#define CLK_INFRA_USB_CK_P1	      78
-#define CLK_INFRA_USB_FRMCNT	      79
-#define CLK_INFRA_USB_FRMCNT_CK_P1    80
-#define CLK_INFRA_USB_PIPE	      81
-#define CLK_INFRA_USB_PIPE_CK_P1      82
-#define CLK_INFRA_USB_UTMI	      83
-#define CLK_INFRA_USB_UTMI_CK_P1      84
-#define CLK_INFRA_USB_XHCI	      85
-#define CLK_INFRA_USB_XHCI_CK_P1      86
-#define CLK_INFRA_PCIE_GFMUX_TL_P0    87
-#define CLK_INFRA_PCIE_GFMUX_TL_P1    88
-#define CLK_INFRA_PCIE_GFMUX_TL_P2    89
-#define CLK_INFRA_PCIE_GFMUX_TL_P3    90
-#define CLK_INFRA_PCIE_PIPE_P0	      91
-#define CLK_INFRA_PCIE_PIPE_P1	      92
-#define CLK_INFRA_PCIE_PIPE_P2	      93
-#define CLK_INFRA_PCIE_PIPE_P3	      94
-#define CLK_INFRA_133M_PCIE_CK_P0     95
-#define CLK_INFRA_133M_PCIE_CK_P1     96
-#define CLK_INFRA_133M_PCIE_CK_P2     97
-#define CLK_INFRA_133M_PCIE_CK_P3     98
-
-/* ETHDMA */
-
-#define CLK_ETHDMA_XGP1_EN   0
-#define CLK_ETHDMA_XGP2_EN   1
-#define CLK_ETHDMA_XGP3_EN   2
-#define CLK_ETHDMA_FE_EN     3
-#define CLK_ETHDMA_GP2_EN    4
-#define CLK_ETHDMA_GP1_EN    5
-#define CLK_ETHDMA_GP3_EN    6
-#define CLK_ETHDMA_ESW_EN    7
-#define CLK_ETHDMA_CRYPT0_EN 8
-#define CLK_ETHDMA_NR_CLK    9
-
-/* SGMIISYS_0 */
-
-#define CLK_SGM0_TX_EN	  0
-#define CLK_SGM0_RX_EN	  1
-#define CLK_SGMII0_NR_CLK 2
-
-/* SGMIISYS_1 */
-
-#define CLK_SGM1_TX_EN	  0
-#define CLK_SGM1_RX_EN	  1
-#define CLK_SGMII1_NR_CLK 2
-
-/* ETHWARP */
-
-#define CLK_ETHWARP_WOCPU2_EN 0
-#define CLK_ETHWARP_WOCPU1_EN 1
-#define CLK_ETHWARP_WOCPU0_EN 2
-#define CLK_ETHWARP_NR_CLK    3
-
-#endif /* _DT_BINDINGS_CLK_MT7988_H */
diff --git a/target/linux/generic/files/block/partitions/fit.c b/target/linux/mediatek/files/block/partitions/fit.c
similarity index 98%
rename from target/linux/generic/files/block/partitions/fit.c
rename to target/linux/mediatek/files/block/partitions/fit.c
index 91b25e0581e7e0..463cd4e9abae6a 100644
--- a/target/linux/generic/files/block/partitions/fit.c
+++ b/target/linux/mediatek/files/block/partitions/fit.c
@@ -144,6 +144,10 @@ int parse_fit_partitions(struct parsed_partitions *state, u64 fit_start_sector,
 
 	np = of_find_node_by_path("/chosen");
 	if (np) {
+		/* new fitblk driver should take over if /chosen/rootdisk is defined */
+		if (of_get_property(np, "rootdisk", NULL))
+			return 0;
+
 		bootconf_c = of_get_property(np, "u-boot,bootconf", &bootconf_len);
 		if (bootconf_c && bootconf_len)
 			bootconf = kmemdup_nul(bootconf_c, bootconf_len, GFP_KERNEL);
diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/stat.c b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/stat.c
index 3a328b0ca415d4..2fed6d9fc897b0 100644
--- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/stat.c
+++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/stat.c
@@ -140,7 +140,7 @@ rtk_api_ret_t rtk_stat_global_get(rtk_stat_global_type_t cntr_idx, rtk_stat_coun
     if (cntr_idx!=DOT1D_TP_LEARNED_ENTRY_DISCARDS_INDEX)
         return RT_ERR_STAT_INVALID_GLOBAL_CNTR;
 
-    if ((retVal = rtl8367c_getAsicMIBsCounter(0, cntr_idx, pCntr)) != RT_ERR_OK)
+    if ((retVal = rtl8367c_getAsicMIBsCounter(0, (RTL8367C_MIBCOUNTER)cntr_idx, pCntr)) != RT_ERR_OK)
         return retVal;
 
     return RT_ERR_OK;
@@ -172,7 +172,7 @@ rtk_api_ret_t rtk_stat_global_getAll(rtk_stat_global_cntr_t *pGlobal_cntrs)
     if(NULL == pGlobal_cntrs)
         return RT_ERR_NULL_POINTER;
 
-    if ((retVal = rtl8367c_getAsicMIBsCounter(0,DOT1D_TP_LEARNED_ENTRY_DISCARDS_INDEX, &pGlobal_cntrs->dot1dTpLearnedEntryDiscards)) != RT_ERR_OK)
+    if ((retVal = rtl8367c_getAsicMIBsCounter(0, dot1dTpLearnedEntryDiscards, &pGlobal_cntrs->dot1dTpLearnedEntryDiscards)) != RT_ERR_OK)
         return retVal;
 
     return RT_ERR_OK;
diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/vlan.c b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/vlan.c
index f7480c4906fdb4..031eabf2efb297 100644
--- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/vlan.c
+++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/vlan.c
@@ -950,7 +950,7 @@ rtk_api_ret_t rtk_vlan_protoAndPortBasedVlan_add(rtk_port_t port, rtk_vlan_proto
     {
         if ((retVal = rtl8367c_getAsicVlanProtocolBasedGroupData(i, &ppb_data_cfg)) != RT_ERR_OK)
             return retVal;
-        tmp = pInfo->frame_type;
+        tmp = (rtl8367c_provlan_frametype)pInfo->frame_type;
         if (ppb_data_cfg.etherType == pInfo->proto_type && ppb_data_cfg.frameType == tmp)
         {
             /*Already exist*/
@@ -976,7 +976,7 @@ rtk_api_ret_t rtk_vlan_protoAndPortBasedVlan_add(rtk_port_t port, rtk_vlan_proto
     else if (empty<RTL8367C_PROTOVLAN_GROUPNO)
     {
         /*No exist index, but have empty index*/
-        ppb_data_cfg.frameType = pInfo->frame_type;
+        ppb_data_cfg.frameType = (rtl8367c_provlan_frametype)pInfo->frame_type;
         ppb_data_cfg.etherType = pInfo->proto_type;
         if ((retVal = rtl8367c_setAsicVlanProtocolBasedGroupData(empty, &ppb_data_cfg)) != RT_ERR_OK)
             return retVal;
@@ -1267,7 +1267,7 @@ rtk_api_ret_t rtk_vlan_tagMode_set(rtk_port_t port, rtk_vlan_tagMode_t tag_mode)
     if (tag_mode >= VLAN_TAG_MODE_END)
         return RT_ERR_PORT_ID;
 
-    if ((retVal = rtl8367c_setAsicVlanEgressTagMode(rtk_switch_port_L2P_get(port), tag_mode)) != RT_ERR_OK)
+    if ((retVal = rtl8367c_setAsicVlanEgressTagMode(rtk_switch_port_L2P_get(port), (rtl8367c_egtagmode)tag_mode)) != RT_ERR_OK)
         return retVal;
 
     return RT_ERR_OK;
diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds b/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds
index af3c3fe7e1018e..f599de68e354ad 100644
--- a/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds
+++ b/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds
@@ -16,6 +16,23 @@ confiabits,mt7981)
 	ucidef_set_led_netdev "lan3" "lan3" "blue:lan-3" "lan3" "link tx rx"
 	ucidef_set_led_netdev "wan" "wan" "blue:wan" "wan" "link tx rx"
 	;;
+bananapi,bpi-r3-mini)
+	ucidef_set_led_netdev "lan1" "LAN" "mdio-bus:0e:green:lan" "eth0" "link_2500 link_1000 tx rx"
+	ucidef_set_led_netdev "lan2" "LAN" "mdio-bus:0e:yellow:lan" "eth0" "link_2500 link_100 tx rx"
+	ucidef_set_led_netdev "wan1" "WAN" "mdio-bus:0f:green:wan" "eth1" "link_2500 link_1000 tx rx"
+	ucidef_set_led_netdev "wan2" "WAN" "mdio-bus:0f:yellow:wan" "eth1" "link_2500 link_100 tx rx"
+	ucidef_set_led_netdev "wlan2g" "WLAN2G" "blue:wlan-1" "phy0-ap0"
+	ucidef_set_led_netdev "wlan5g" "WLAN5G" "blue:wlan-2" "phy1-ap0"
+	;;
+bananapi,bpi-r4)
+	ucidef_set_led_netdev "wan" "wan" "mt7530-0:00:green:lan" "wan" "link tx rx"
+	ucidef_set_led_netdev "lan1" "lan1" "mt7530-0:01:green:lan" "lan1" "link tx rx"
+	ucidef_set_led_netdev "lan2" "lan2" "mt7530-0:02:green:lan" "lan2" "link tx rx"
+	ucidef_set_led_netdev "lan3" "lan3" "mt7530-0:03:green:lan" "lan3" "link tx rx"
+	;;
+cudy,re3000-v1)
+	ucidef_set_led_netdev "lan" "lan" "green:lan" "eth0" "link tx rx"
+	;;
 cudy,wr3000-v1)
 	ucidef_set_led_netdev "wan" "wan" "blue:wan" "wan"
 	;;
diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network
index 47e010bbdf1e0b..d16dc470970a12 100644
--- a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network
+++ b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network
@@ -36,13 +36,19 @@ mediatek_setup_interfaces()
 		ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 sfp2" "eth1 wan"
 		;;
 	bananapi,bpi-r3-mini)
-		ucidef_set_interfaces_lan_wan "eth0" "eth1"
+		ucidef_set_interfaces_lan_wan eth0 eth1
+		;;
+	bananapi,bpi-r4)
+		ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 eth1" "wan eth2"
 		;;
 	cmcc,rax3000m|\
 	h3c,magic-nx30-pro|\
 	zbtlink,zbt-z8103ax)
 		ucidef_set_interfaces_lan_wan "lan1 lan2 lan3" eth1
 		;;
+	comfast,cf-e393ax)
+		ucidef_set_interfaces_lan_wan "lan1" eth1
+		;;
 	glinet,gl-mt2500|\
 	glinet,gl-mt3000)
 		ucidef_set_interfaces_lan_wan eth1 eth0
@@ -64,6 +70,7 @@ mediatek_setup_interfaces()
 	mercusys,mr90x-v1)
 		ucidef_set_interfaces_lan_wan "lan0 lan1 lan2" eth1
 		;;
+	cudy,re3000-v1|\
 	netgear,wax220|\
 	ubnt,unifi-6-plus|\
 	zyxel,nwa50ax-pro)
@@ -103,14 +110,6 @@ mediatek_setup_macs()
 	local label_mac=""
 
 	case $board in
-	asus,rt-ax59u|\
-	asus,tuf-ax4200|\
-	asus,tuf-ax6000)
-		CI_UBIPART="UBI_DEV"
-		addr=$(mtd_get_mac_binary_ubi "Factory" 0x4)
-		wan_mac="${addr}"
-		lan_mac="${addr}"
-		;;
 	bananapi,bpi-r3)
 		wan_mac=$(macaddr_add $(cat /sys/class/net/eth0/address) 1)
 		;;
@@ -127,16 +126,6 @@ mediatek_setup_macs()
 		;;
 		esac
 		;;
-	glinet,gl-mt2500)
-		label_mac="$(get_mac_binary "/dev/mmcblk0boot1" 0xA)"
-		wan_mac="$label_mac"
-		lan_mac="$(macaddr_add $label_mac 1)"
-		;;
-	glinet,gl-mt6000)
-		label_mac=$(mmc_get_mac_binary factory 0x0a)
-		wan_mac=$label_mac
-		lan_mac=$(macaddr_add "$label_mac" 2)
-		;;
 	h3c,magic-nx30-pro)
 		wan_mac=$(mtd_get_mac_ascii pdt_data_1 ethaddr)
 		lan_mac=$(macaddr_add "$wan_mac" 1)
diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/05_compat-version b/target/linux/mediatek/filogic/base-files/etc/board.d/05_compat-version
index e0e1a8ecc73e3d..d0cfd8f0a1232e 100644
--- a/target/linux/mediatek/filogic/base-files/etc/board.d/05_compat-version
+++ b/target/linux/mediatek/filogic/base-files/etc/board.d/05_compat-version
@@ -6,7 +6,7 @@ board_config_update
 
 case "$(board_name)" in
 	bananapi,bpi-r3)
-		ucidef_set_compat_version "1.1"
+		ucidef_set_compat_version "1.2"
 		;;
 esac
 
diff --git a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/firmware/11-mt76-caldata b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/firmware/11-mt76-caldata
index 22ab26608f8ab6..bd68ef74156921 100644
--- a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/firmware/11-mt76-caldata
+++ b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/firmware/11-mt76-caldata
@@ -57,22 +57,8 @@ case "$FIRMWARE" in
 		;;
 	esac
 	;;
-"mediatek/mt7986_eeprom_mt7976_dbdc.bin")
-	case "$board" in
-	asus,rt-ax59u|\
-	asus,tuf-ax4200)
-		CI_UBIPART="UBI_DEV"
-		caldata_extract_ubi "Factory" 0x0 0x1000
-		;;
-	esac
-	;;
 "mediatek/mt7986_eeprom_mt7976_dual.bin")
 	case "$board" in
-	asus,tuf-ax6000)
-		CI_UBIPART="UBI_DEV"
-		caldata_extract_ubi "Factory" 0x0 0x1000
-		;;
-	glinet,gl-mt6000|\
 	jdcloud,re-cp-03)
 		caldata_extract_mmc "factory" 0x0 0x1000
 		;;
diff --git a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac
index f2ae887bd9172e..b9b9f96121a6d7 100644
--- a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac
+++ b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac
@@ -63,6 +63,15 @@ case "$board" in
 		esac
 		[ "$PHYNBR" = "1" ] && echo "$addr" > /sys${DEVPATH}/macaddress
 		;;
+	comfast,cf-e393ax)
+		addr=$(mtd_get_mac_binary "Factory" 0x8000)
+		[ "$PHYNBR" = "1" ] && macaddr_add $addr 1 > /sys${DEVPATH}/macaddress
+		;;
+	cudy,re3000-v1)
+		addr=$(mtd_get_mac_binary bdinfo 0xde00)
+		[ "$PHYNBR" = "0" ] && echo "$addr" > /sys${DEVPATH}/macaddress
+		[ "$PHYNBR" = "1" ] && macaddr_setbit_la $(macaddr_add $addr 1) > /sys${DEVPATH}/macaddress
+		;;
 	cudy,wr3000-v1)
 		addr=$(mtd_get_mac_binary bdinfo 0xde00)
 		# Originally, phy0 is phy1 mac with LA bit set. However, this would conflict
diff --git a/target/linux/mediatek/filogic/base-files/etc/uci-defaults/05_fix-compat-version b/target/linux/mediatek/filogic/base-files/etc/uci-defaults/05_fix-compat-version
index 4486f2f090c55a..f39d2575e13192 100644
--- a/target/linux/mediatek/filogic/base-files/etc/uci-defaults/05_fix-compat-version
+++ b/target/linux/mediatek/filogic/base-files/etc/uci-defaults/05_fix-compat-version
@@ -2,7 +2,7 @@
 
 case "$(board_name)" in
 	bananapi,bpi-r3)
-	uci set system.@system[0].compat_version="1.1"
+	uci set system.@system[0].compat_version="1.2"
 	uci commit system
 	;;
 esac
diff --git a/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh b/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh
index 2343b4028272fe..526de081610368 100755
--- a/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh
+++ b/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh
@@ -1,4 +1,5 @@
 REQUIRE_IMAGE_METADATA=1
+RAMFS_COPY_BIN='fitblk'
 
 asus_initial_setup()
 {
@@ -80,18 +81,18 @@ platform_do_upgrade() {
 		nand_do_upgrade "$1"
 		;;
 	bananapi,bpi-r3|\
-	bananapi,bpi-r3-mini)
-		local rootdev="$(cmdline_get_var root)"
-		rootdev="${rootdev##*/}"
-		rootdev="${rootdev%p[0-9]*}"
-		case "$rootdev" in
-		mmc*)
-			CI_ROOTDEV="$rootdev"
-			CI_KERNPART="production"
+	bananapi,bpi-r3-mini|\
+	bananapi,bpi-r4)
+		[ -e /dev/fit0 ] && fitblk /dev/fit0
+		[ -e /dev/fitrw ] && fitblk /dev/fitrw
+		bootdev="$(fitblk_get_bootdev)"
+		case "$bootdev" in
+		mmcblk*)
+			EMMC_KERN_DEV="/dev/$bootdev"
 			emmc_do_upgrade "$1"
 			;;
 		mtdblock*)
-			PART_NAME="fit"
+			PART_NAME="/dev/mtd${bootdev:8}"
 			default_do_upgrade "$1"
 			;;
 		ubiblock*)
@@ -112,6 +113,7 @@ platform_do_upgrade() {
 			;;
 		esac
 		;;
+	cudy,re3000-v1|\
 	cudy,wr3000-v1|\
 	yuncore,ax835)
 		default_do_upgrade "$1"
@@ -176,7 +178,7 @@ platform_check_image() {
 
 	case "$board" in
 	bananapi,bpi-r3|\
-	bananapi,bpi-r3-mini|\
+	bananapi,bpi-r4|\
 	cmcc,rax3000m)
 		[ "$magic" != "d00dfeed" ] && {
 			echo "Invalid image type."
@@ -195,8 +197,6 @@ platform_check_image() {
 
 platform_copy_config() {
 	case "$(board_name)" in
-	bananapi,bpi-r3|\
-	bananapi,bpi-r3-mini|\
 	cmcc,rax3000m)
 		case "$(cmdline_get_var root)" in
 		/dev/mmc*)
@@ -204,6 +204,15 @@ platform_copy_config() {
 			;;
 		esac
 		;;
+	bananapi,bpi-r3|\
+	bananapi,bpi-r3-mini|\
+	bananapi,bpi-r4)
+		case "$(fitblk_get_bootdev)" in
+		mmcblk*)
+			emmc_copy_config
+			;;
+		esac
+		;;
 	acer,predator-w6|\
 	glinet,gl-mt2500|\
 	glinet,gl-mt6000|\
diff --git a/target/linux/mediatek/filogic/config-5.15 b/target/linux/mediatek/filogic/config-5.15
deleted file mode 100644
index 8ba0b0efe8d656..00000000000000
--- a/target/linux/mediatek/filogic/config-5.15
+++ /dev/null
@@ -1,443 +0,0 @@
-CONFIG_64BIT=y
-# CONFIG_AHCI_MTK is not set
-CONFIG_AQUANTIA_PHY=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MEDIATEK=y
-CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
-CONFIG_ARCH_MMAP_RND_BITS=18
-CONFIG_ARCH_MMAP_RND_BITS_MAX=24
-CONFIG_ARCH_MMAP_RND_BITS_MIN=18
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
-CONFIG_ARCH_PROC_KCORE_TEXT=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_STACKWALK=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_WANTS_NO_INSTR=y
-CONFIG_ARM64=y
-CONFIG_ARM64_4K_PAGES=y
-CONFIG_ARM64_CRYPTO=y
-CONFIG_ARM64_ERRATUM_843419=y
-CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
-CONFIG_ARM64_PAGE_SHIFT=12
-CONFIG_ARM64_PA_BITS=48
-CONFIG_ARM64_PA_BITS_48=y
-CONFIG_ARM64_TAGGED_ADDR_ABI=y
-CONFIG_ARM64_VA_BITS=39
-CONFIG_ARM64_VA_BITS_39=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_GIC_V2M=y
-CONFIG_ARM_GIC_V3=y
-CONFIG_ARM_GIC_V3_ITS=y
-CONFIG_ARM_GIC_V3_ITS_PCI=y
-CONFIG_ARM_MEDIATEK_CPUFREQ=y
-CONFIG_ARM_PMU=y
-CONFIG_ARM_PSCI_FW=y
-CONFIG_ATA=y
-CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BLK_PM=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_BSD_PROCESS_ACCT_V3=y
-CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
-CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE_OVERRIDE=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_MEDIATEK=y
-# CONFIG_COMMON_CLK_MT2712 is not set
-# CONFIG_COMMON_CLK_MT6779 is not set
-# CONFIG_COMMON_CLK_MT6797 is not set
-# CONFIG_COMMON_CLK_MT7622 is not set
-CONFIG_COMMON_CLK_MT7981=y
-CONFIG_COMMON_CLK_MT7981_ETHSYS=y
-CONFIG_COMMON_CLK_MT7986=y
-CONFIG_COMMON_CLK_MT7986_ETHSYS=y
-CONFIG_COMMON_CLK_MT7988=y
-# CONFIG_COMMON_CLK_MT8173 is not set
-# CONFIG_COMMON_CLK_MT8183 is not set
-# CONFIG_COMMON_CLK_MT8516 is not set
-# CONFIG_COMPAT_32BIT_TIME is not set
-CONFIG_CONFIGFS_FS=y
-CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15
-# CONFIG_CPUFREQ_DT is not set
-CONFIG_CPU_FREQ=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_THERMAL=y
-CONFIG_CRC16=y
-CONFIG_CRYPTO_AES_ARM64=y
-CONFIG_CRYPTO_AES_ARM64_CE=y
-CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
-CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
-CONFIG_CRYPTO_CMAC=y
-CONFIG_CRYPTO_CRC32=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_CRYPTD=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_DRBG=y
-CONFIG_CRYPTO_DRBG_HMAC=y
-CONFIG_CRYPTO_DRBG_MENU=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_ECC=y
-CONFIG_CRYPTO_ECDH=y
-CONFIG_CRYPTO_GHASH_ARM64_CE=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_JITTERENTROPY=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_RNG_DEFAULT=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA256_ARM64=y
-CONFIG_CRYPTO_SHA2_ARM64_CE=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_SIMD=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_MISC=y
-CONFIG_DIMLIB=y
-CONFIG_DMADEVICES=y
-CONFIG_DMATEST=y
-CONFIG_DMA_DIRECT_REMAP=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_ENGINE_RAID=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_REMAP=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DTC=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EINT_MTK=y
-CONFIG_EXT4_FS=y
-CONFIG_F2FS_FS=y
-CONFIG_FIT_PARTITION=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FRAME_POINTER=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_CSUM=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_FIND_FIRST_BIT=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GLOB=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_WATCHDOG=y
-CONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y
-CONFIG_GRO_CELLS=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HWMON=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_MTK=y
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_MT65XX=y
-CONFIG_ICPLUS_PHY=y
-CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_TIME_ACCOUNTING=y
-CONFIG_IRQ_WORK=y
-CONFIG_JBD2=y
-CONFIG_JUMP_LABEL=y
-CONFIG_LEDS_SMARTRG_LED=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MAXLINEAR_GPHY=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEDIATEK_2P5G_PHY=y
-CONFIG_MEDIATEK_GE_PHY=y
-CONFIG_MEDIATEK_GE_SOC_PHY=y
-CONFIG_MEDIATEK_WATCHDOG=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_CQHCI=y
-CONFIG_MMC_MTK=y
-CONFIG_MODULES_TREE_LOOKUP=y
-CONFIG_MODULES_USE_ELF_RELA=y
-CONFIG_MTD_NAND_CORE=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_ECC_MEDIATEK=y
-CONFIG_MTD_NAND_ECC_SW_HAMMING=y
-CONFIG_MTD_NAND_MTK=y
-CONFIG_MTD_NAND_MTK_BMT=y
-CONFIG_MTD_PARSER_TRX=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_SPI_NAND=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_SPLIT_FIT_FW=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_UBI_FASTMAP=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-# CONFIG_MTK_CMDQ is not set
-# CONFIG_MTK_CQDMA is not set
-CONFIG_MTK_HSDMA=y
-CONFIG_MTK_INFRACFG=y
-CONFIG_MTK_PMIC_WRAP=y
-CONFIG_MTK_SCPSYS=y
-CONFIG_MTK_SCPSYS_PM_DOMAINS=y
-CONFIG_MTK_THERMAL=y
-CONFIG_MTK_TIMER=y
-# CONFIG_MTK_UART_APDMA is not set
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-CONFIG_NET_DEVLINK=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_MT7530=y
-CONFIG_NET_DSA_MT7530_MDIO=y
-CONFIG_NET_DSA_MT7530_MMIO=y
-CONFIG_NET_DSA_TAG_MTK=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_MEDIATEK_SOC=y
-CONFIG_NET_MEDIATEK_SOC_USXGMII=y
-CONFIG_NET_MEDIATEK_SOC_WED=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NET_VENDOR_MEDIATEK=y
-CONFIG_NLS=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=4
-CONFIG_NVMEM=y
-CONFIG_NVMEM_LAYOUTS=y
-CONFIG_NVMEM_MTK_EFUSE=y
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_DYNAMIC=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_OVERLAY=y
-CONFIG_OF_RESOLVE=y
-CONFIG_PADATA=y
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_POOL_STATS=y
-CONFIG_PARTITION_PERCPU=y
-CONFIG_PCI=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEASPM=y
-# CONFIG_PCIEASPM_DEFAULT is not set
-CONFIG_PCIEASPM_PERFORMANCE=y
-# CONFIG_PCIEASPM_POWERSAVE is not set
-# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
-CONFIG_PCIEPORTBUS=y
-# CONFIG_PCIE_MEDIATEK is not set
-CONFIG_PCIE_MEDIATEK_GEN3=y
-CONFIG_PCIE_PME=y
-CONFIG_PCI_DEBUG=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PCS_MTK_LYNXI=y
-CONFIG_PERF_EVENTS=y
-CONFIG_PGTABLE_LEVELS=3
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_PHY_MTK_TPHY=y
-# CONFIG_PHY_MTK_UFS is not set
-CONFIG_PHY_MTK_XSPHY=y
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_MT2712 is not set
-# CONFIG_PINCTRL_MT6765 is not set
-# CONFIG_PINCTRL_MT6797 is not set
-# CONFIG_PINCTRL_MT7622 is not set
-CONFIG_PINCTRL_MT7981=y
-CONFIG_PINCTRL_MT7986=y
-CONFIG_PINCTRL_MT7988=y
-# CONFIG_PINCTRL_MT8173 is not set
-# CONFIG_PINCTRL_MT8183 is not set
-CONFIG_PINCTRL_MT8516=y
-CONFIG_PINCTRL_MTK=y
-CONFIG_PINCTRL_MTK_MOORE=y
-CONFIG_PINCTRL_MTK_V2=y
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_PM_GENERIC_DOMAINS=y
-CONFIG_PM_GENERIC_DOMAINS_OF=y
-CONFIG_PM_OPP=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_SYSCON=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PRINTK_TIME=y
-CONFIG_PSTORE=y
-CONFIG_PSTORE_COMPRESS=y
-CONFIG_PSTORE_COMPRESS_DEFAULT="deflate"
-CONFIG_PSTORE_CONSOLE=y
-CONFIG_PSTORE_DEFLATE_COMPRESS=y
-CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y
-CONFIG_PSTORE_PMSG=y
-CONFIG_PSTORE_RAM=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PWM=y
-CONFIG_PWM_MEDIATEK=y
-# CONFIG_PWM_MTK_DISP is not set
-CONFIG_PWM_SYSFS=y
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_QUEUED_SPINLOCKS=y
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-# CONFIG_RAVE_SP_CORE is not set
-CONFIG_REALTEK_PHY=y
-CONFIG_REED_SOLOMON=y
-CONFIG_REED_SOLOMON_DEC8=y
-CONFIG_REED_SOLOMON_ENC8=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_MT6380=y
-CONFIG_REGULATOR_RT5190A=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RESET_TI_SYSCON=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_MT7622=y
-CONFIG_RTC_I2C_AND_SPI=y
-# CONFIG_RTL8367S_GSW is not set
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_SCHED_MC=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_MT6577=y
-CONFIG_SERIAL_8250_NR_UARTS=3
-CONFIG_SERIAL_8250_RUNTIME_UARTS=3
-CONFIG_SERIAL_DEV_BUS=y
-CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SG_POOL=y
-CONFIG_SMP=y
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SPARSEMEM=y
-CONFIG_SPARSEMEM_EXTREME=y
-CONFIG_SPARSEMEM_VMEMMAP=y
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_DYNAMIC=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_MT65XX=y
-CONFIG_SPI_MTK_NOR=y
-CONFIG_SPI_MTK_SNFI=y
-CONFIG_SRCU=y
-CONFIG_SWIOTLB=y
-CONFIG_SWPHY=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_GOV_BANG_BANG=y
-CONFIG_THERMAL_GOV_FAIR_SHARE=y
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_GOV_USER_SPACE=y
-CONFIG_THERMAL_HWMON=y
-CONFIG_THERMAL_OF=y
-CONFIG_THERMAL_WRITABLE_TRIPS=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UBIFS_FS=y
-# CONFIG_UCLAMP_TASK is not set
-# CONFIG_UNMAP_KERNEL_AT_EL0 is not set
-CONFIG_USB_SUPPORT=y
-CONFIG_VMAP_STACK=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y
-CONFIG_WATCHDOG_PRETIMEOUT_GOV=y
-# CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP is not set
-CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y
-CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m
-CONFIG_WATCHDOG_SYSFS=y
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZONE_DMA32=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
diff --git a/target/linux/mediatek/filogic/config-6.1 b/target/linux/mediatek/filogic/config-6.1
index 1687aadbc13f03..34aa2e76b66d8f 100644
--- a/target/linux/mediatek/filogic/config-6.1
+++ b/target/linux/mediatek/filogic/config-6.1
@@ -1,6 +1,5 @@
 CONFIG_64BIT=y
 # CONFIG_AHCI_MTK is not set
-CONFIG_AQUANTIA_PHY=y
 CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
 CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
 CONFIG_ARCH_DMA_ADDR_T_64BIT=y
@@ -44,6 +43,7 @@ CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_NVMEM=y
 CONFIG_BLK_PM=y
 CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_BSD_PROCESS_ACCT_V3=y
@@ -254,6 +254,7 @@ CONFIG_MTD_UBI=y
 CONFIG_MTD_UBI_BEB_LIMIT=20
 CONFIG_MTD_UBI_BLOCK=y
 CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_MTD_UBI_NVMEM=y
 CONFIG_MTD_UBI_WL_THRESHOLD=4096
 # CONFIG_MTK_CMDQ is not set
 # CONFIG_MTK_CQDMA is not set
@@ -264,6 +265,9 @@ CONFIG_MTK_SCPSYS=y
 CONFIG_MTK_SCPSYS_PM_DOMAINS=y
 # CONFIG_MTK_SVS is not set
 CONFIG_MTK_THERMAL=y
+CONFIG_MTK_SOC_THERMAL=y
+CONFIG_MTK_LVTS_THERMAL=y
+CONFIG_MTK_LVTS_THERMAL_DEBUGFS=y
 CONFIG_MTK_TIMER=y
 # CONFIG_MTK_UART_APDMA is not set
 CONFIG_MUTEX_SPIN_ON_OWNER=y
@@ -277,7 +281,6 @@ CONFIG_NET_DSA_MT7530_MMIO=y
 CONFIG_NET_DSA_TAG_MTK=y
 CONFIG_NET_FLOW_LIMIT=y
 CONFIG_NET_MEDIATEK_SOC=y
-CONFIG_NET_MEDIATEK_SOC_USXGMII=y
 CONFIG_NET_MEDIATEK_SOC_WED=y
 CONFIG_NET_SELFTESTS=y
 CONFIG_NET_SWITCHDEV=y
@@ -324,6 +327,7 @@ CONFIG_PCI_DOMAINS_GENERIC=y
 CONFIG_PCI_MSI=y
 CONFIG_PCI_MSI_IRQ_DOMAIN=y
 CONFIG_PCS_MTK_LYNXI=y
+CONFIG_PCS_MTK_USXGMII=y
 CONFIG_PERF_EVENTS=y
 CONFIG_PGTABLE_LEVELS=3
 CONFIG_PHYLIB=y
@@ -334,6 +338,7 @@ CONFIG_PHYS_ADDR_T_64BIT=y
 # CONFIG_PHY_MTK_PCIE is not set
 CONFIG_PHY_MTK_TPHY=y
 # CONFIG_PHY_MTK_UFS is not set
+CONFIG_PHY_MTK_XFI_TPHY=y
 CONFIG_PHY_MTK_XSPHY=y
 CONFIG_PINCTRL=y
 # CONFIG_PINCTRL_MT2712 is not set
@@ -458,6 +463,7 @@ CONFIG_TREE_RCU=y
 CONFIG_TREE_SRCU=y
 CONFIG_UBIFS_FS=y
 # CONFIG_UCLAMP_TASK is not set
+CONFIG_UIMAGE_FIT_BLK=y
 # CONFIG_UNMAP_KERNEL_AT_EL0 is not set
 CONFIG_USB_SUPPORT=y
 CONFIG_VMAP_STACK=y
diff --git a/target/linux/mediatek/filogic/target.mk b/target/linux/mediatek/filogic/target.mk
index 4e5cde3d6bb6c0..7c709aa1ed40c5 100644
--- a/target/linux/mediatek/filogic/target.mk
+++ b/target/linux/mediatek/filogic/target.mk
@@ -2,7 +2,7 @@ ARCH:=aarch64
 SUBTARGET:=filogic
 BOARDNAME:=Filogic 8x0 (MT798x)
 CPU_TYPE:=cortex-a53
-DEFAULT_PACKAGES += kmod-crypto-hw-safexcel kmod-mt7915e wpad-openssl uboot-envtools
+DEFAULT_PACKAGES += fitblk kmod-phy-aquantia kmod-crypto-hw-safexcel kmod-mt7915e wpad-openssl uboot-envtools
 KERNELNAME:=Image dtbs
 
 define Target/Description
diff --git a/target/linux/mediatek/image/filogic.mk b/target/linux/mediatek/image/filogic.mk
index e943913291bd29..b1c043bef20e37 100644
--- a/target/linux/mediatek/image/filogic.mk
+++ b/target/linux/mediatek/image/filogic.mk
@@ -227,7 +227,8 @@ define Device/bananapi_bpi-r3
 		       mt7986a-bananapi-bpi-r3-respeaker-2mics
   DEVICE_DTS_DIR := $(DTS_DIR)/
   DEVICE_DTS_LOADADDR := 0x43f00000
-  DEVICE_PACKAGES := kmod-hwmon-pwmfan kmod-i2c-gpio kmod-mt7986-firmware kmod-sfp kmod-usb3 e2fsprogs f2fsck mkf2fs mt7986-wo-firmware
+  DEVICE_PACKAGES := kmod-hwmon-pwmfan kmod-i2c-gpio kmod-mt7986-firmware kmod-sfp kmod-usb3 \
+		     e2fsprogs f2fsck mkf2fs mt7986-wo-firmware
   IMAGES := sysupgrade.itb
   KERNEL_LOADADDR := 0x44000000
   KERNEL_INITRAMFS_SUFFIX := -recovery.itb
@@ -240,7 +241,7 @@ define Device/bananapi_bpi-r3
   ARTIFACT/emmc-bl31-uboot.fip	:= mt7986-bl31-uboot bananapi_bpi-r3-emmc
   ARTIFACT/nor-preloader.bin	:= mt7986-bl2 nor-ddr4
   ARTIFACT/nor-bl31-uboot.fip	:= mt7986-bl31-uboot bananapi_bpi-r3-nor
-  ARTIFACT/snand-preloader.bin	:= mt7986-bl2 spim-nand-ddr4
+  ARTIFACT/snand-preloader.bin	:= mt7986-bl2 spim-nand-ubi-ddr4
   ARTIFACT/snand-bl31-uboot.fip	:= mt7986-bl31-uboot bananapi_bpi-r3-snand
   ARTIFACT/sdcard.img.gz	:= mt798x-gpt sdmmc |\
 				   pad-to 17k | mt7986-bl2 sdmmc-ddr4 |\
@@ -248,7 +249,7 @@ define Device/bananapi_bpi-r3
 				$(if $(CONFIG_TARGET_ROOTFS_INITRAMFS),\
 				   pad-to 12M | append-image-stage initramfs-recovery.itb | check-size 44m |\
 				) \
-				   pad-to 44M | mt7986-bl2 spim-nand-ddr4 |\
+				   pad-to 44M | mt7986-bl2 spim-nand-ubi-ddr4 |\
 				   pad-to 45M | mt7986-bl31-uboot bananapi_bpi-r3-snand |\
 				   pad-to 49M | mt7986-bl2 nor-ddr4 |\
 				   pad-to 50M | mt7986-bl31-uboot bananapi_bpi-r3-nor |\
@@ -267,42 +268,101 @@ endif
 	fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
   IMAGE/sysupgrade.itb := append-kernel | fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | pad-rootfs | append-metadata
   DEVICE_DTC_FLAGS := --pad 4096
-  DEVICE_COMPAT_VERSION := 1.1
-  DEVICE_COMPAT_MESSAGE := Device tree overlay mechanism needs bootloader update
+  DEVICE_COMPAT_VERSION := 1.2
+  DEVICE_COMPAT_MESSAGE := SPI-NAND flash layout changes require bootloader update
 endef
 TARGET_DEVICES += bananapi_bpi-r3
 
 define Device/bananapi_bpi-r3-mini
   DEVICE_VENDOR := Bananapi
-  DEVICE_MODEL := BPi-R3 mini
+  DEVICE_MODEL := BPi-R3 Mini
   DEVICE_DTS := mt7986a-bananapi-bpi-r3-mini
-  DEVICE_DTS_DIR := $(DTS_DIR)/
-  DEVICE_DTC_FLAGS := --pad 4096
+  DEVICE_DTS_CONFIG := config-mt7986a-bananapi-bpi-r3-mini
+  DEVICE_DTS_DIR := ../dts
   DEVICE_DTS_LOADADDR := 0x43f00000
-  DEVICE_PACKAGES := kmod-hwmon-pwmfan kmod-mmc kmod-i2c-gpio kmod-mt7986-firmware kmod-usb3 kmod-nvme e2fsprogs f2fsck mkf2fs mt7986-wo-firmware
-  IMAGES := sysupgrade.itb
+  DEVICE_PACKAGES := kmod-hwmon-pwmfan kmod-mt7986-firmware kmod-phy-airoha-en8811h \
+		     kmod-usb3 e2fsprogs f2fsck mkf2fs mt7986-wo-firmware
   KERNEL_LOADADDR := 0x44000000
   KERNEL := kernel-bin | gzip
   KERNEL_INITRAMFS := kernel-bin | lzma | \
-	fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
+    fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
   KERNEL_INITRAMFS_SUFFIX := -recovery.itb
+  BLOCKSIZE := 128k
+  PAGESIZE := 2048
+  KERNEL_IN_UBI := 1
+  UBOOTENV_IN_UBI := 1
+  IMAGES := snand-factory.bin sysupgrade.itb
 ifeq ($(DUMP),)
   IMAGE_SIZE := $$(shell expr 64 + $$(CONFIG_TARGET_ROOTFS_PARTSIZE))m
 endif
-  IMAGE/sysupgrade.itb := append-kernel | fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | pad-rootfs | append-metadata
+  IMAGE/sysupgrade.itb := append-kernel | \
+    fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | \
+    pad-rootfs | append-metadata
   ARTIFACTS := \
-       emmc-gpt.bin \
-       emmc-preloader.bin \
-       emmc-bl31-uboot.fip \
-       snand-preloader.bin snand-bl31-uboot.fip
+       emmc-gpt.bin emmc-preloader.bin emmc-bl31-uboot.fip \
+       snand-factory.bin snand-preloader.bin snand-bl31-uboot.fip
   ARTIFACT/emmc-gpt.bin := mt798x-gpt emmc
   ARTIFACT/emmc-preloader.bin := mt7986-bl2 emmc-ddr4
   ARTIFACT/emmc-bl31-uboot.fip := mt7986-bl31-uboot bananapi_bpi-r3-mini-emmc
-  ARTIFACT/snand-preloader.bin := mt7986-bl2 spim-nand-ddr4
+  ARTIFACT/snand-factory.bin := mt7986-bl2 spim-nand-ubi-ddr4 | pad-to 256k | \
+				mt7986-bl2 spim-nand-ubi-ddr4 | pad-to 512k | \
+				mt7986-bl2 spim-nand-ubi-ddr4 | pad-to 768k | \
+				mt7986-bl2 spim-nand-ubi-ddr4 | pad-to 2048k | \
+				ubinize-image fit squashfs-sysupgrade.itb
+  ARTIFACT/snand-preloader.bin := mt7986-bl2 spim-nand-ubi-ddr4
   ARTIFACT/snand-bl31-uboot.fip := mt7986-bl31-uboot bananapi_bpi-r3-mini-snand
+  UBINIZE_PARTS := fip=:$(STAGING_DIR_IMAGE)/mt7986_bananapi_bpi-r3-mini-snand-u-boot.fip
+ifneq ($(CONFIG_PACKAGE_airoha-en8811h-firmware),)
+  UBINIZE_PARTS += en8811h-fw=:$(STAGING_DIR_IMAGE)/EthMD32.bin
+endif
 endef
 TARGET_DEVICES += bananapi_bpi-r3-mini
 
+define Device/bananapi_bpi-r4
+  DEVICE_VENDOR := Bananapi
+  DEVICE_MODEL := BPi-R4
+  DEVICE_DTS := mt7988a-bananapi-bpi-r4
+  DEVICE_DTS_CONFIG := config-mt7988a-bananapi-bpi-r4
+  DEVICE_DTS_DIR := $(DTS_DIR)/
+  DEVICE_DTS_LOADADDR := 0x45f00000
+  DEVICE_DTS_OVERLAY:= mt7988a-bananapi-bpi-r4-emmc mt7988a-bananapi-bpi-r4-rtc mt7988a-bananapi-bpi-r4-sd mt7988a-bananapi-bpi-r4-wifi-mt7996a
+  DEVICE_DTC_FLAGS := --pad 4096
+  DEVICE_PACKAGES := kmod-hwmon-pwmfan kmod-i2c-mux-pca954x kmod-eeprom-at24 kmod-mt7996-firmware \
+		     kmod-rtc-pcf8563 kmod-sfp kmod-usb3 e2fsprogs f2fsck mkf2fs
+  IMAGES := sysupgrade.itb
+  KERNEL_LOADADDR := 0x46000000
+  KERNEL_INITRAMFS_SUFFIX := -recovery.itb
+  ARTIFACTS := \
+	       emmc-preloader.bin emmc-bl31-uboot.fip \
+	       sdcard.img.gz \
+	       snand-preloader.bin snand-bl31-uboot.fip
+  ARTIFACT/emmc-preloader.bin	:= mt7988-bl2 emmc-comb
+  ARTIFACT/emmc-bl31-uboot.fip	:= mt7988-bl31-uboot bananapi_bpi-r4-emmc
+  ARTIFACT/snand-preloader.bin	:= mt7988-bl2 spim-nand-ubi-comb
+  ARTIFACT/snand-bl31-uboot.fip	:= mt7988-bl31-uboot bananapi_bpi-r4-snand
+  ARTIFACT/sdcard.img.gz	:= mt798x-gpt sdmmc |\
+				   pad-to 17k | mt7988-bl2 sdmmc-comb |\
+				   pad-to 6656k | mt7988-bl31-uboot bananapi_bpi-r4-sdmmc |\
+				$(if $(CONFIG_TARGET_ROOTFS_INITRAMFS),\
+				   pad-to 12M | append-image-stage initramfs-recovery.itb | check-size 44m |\
+				) \
+				   pad-to 44M | mt7988-bl2 spim-nand-ubi-comb |\
+				   pad-to 45M | mt7988-bl31-uboot bananapi_bpi-r4-snand |\
+				   pad-to 51M | mt7988-bl2 emmc-comb |\
+				   pad-to 52M | mt7988-bl31-uboot bananapi_bpi-r4-emmc |\
+				   pad-to 56M | mt798x-gpt emmc |\
+				$(if $(CONFIG_TARGET_ROOTFS_SQUASHFS),\
+				   pad-to 64M | append-image squashfs-sysupgrade.itb | check-size |\
+				) \
+				  gzip
+  IMAGE_SIZE := $$(shell expr 64 + $$(CONFIG_TARGET_ROOTFS_PARTSIZE))m
+  KERNEL			:= kernel-bin | gzip
+  KERNEL_INITRAMFS := kernel-bin | lzma | \
+	fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
+  IMAGE/sysupgrade.itb := append-kernel | fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-with-rootfs | pad-rootfs | append-metadata
+endef
+TARGET_DEVICES += bananapi_bpi-r4
+
 define Device/cetron_ct3003
   DEVICE_VENDOR := Cetron
   DEVICE_MODEL := CT3003
@@ -353,6 +413,30 @@ define Device/cmcc_rax3000m
 endef
 TARGET_DEVICES += cmcc_rax3000m
 
+define Device/comfast_cf-e393ax
+  DEVICE_VENDOR := Comfast
+  DEVICE_MODEL := CF-E393AX
+  DEVICE_DTS := mt7981a-comfast-cf-e393ax
+  DEVICE_DTS_DIR := ../dts
+  DEVICE_DTC_FLAGS := --pad 4096
+  DEVICE_DTS_LOADADDR := 0x43f00000
+  DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware
+  KERNEL_LOADADDR := 0x44000000
+  KERNEL = kernel-bin | lzma | \
+       fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb
+  KERNEL_INITRAMFS = kernel-bin | lzma | \
+       fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd
+  UBINIZE_OPTS := -E 5
+  BLOCKSIZE := 128k
+  PAGESIZE := 2048
+  IMAGE_SIZE := 65536k
+  KERNEL_IN_UBI := 1
+  IMAGES := sysupgrade.bin factory.bin
+  IMAGE/factory.bin := append-ubi | check-size $$$$(IMAGE_SIZE)
+  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
+endef
+TARGET_DEVICES += comfast_cf-e393ax
+
 define Device/confiabits_mt7981
   DEVICE_VENDOR := Confiabits
   DEVICE_MODEL := MT7981
@@ -369,6 +453,25 @@ define Device/confiabits_mt7981
 endef
 TARGET_DEVICES += confiabits_mt7981
 
+define Device/cudy_re3000-v1
+  DEVICE_VENDOR := Cudy
+  DEVICE_MODEL := RE3000
+  DEVICE_VARIANT := v1
+  DEVICE_DTS := mt7981b-cudy-re3000-v1
+  DEVICE_DTS_DIR := ../dts
+  DEVICE_DTS_LOADADDR := 0x47000000
+  IMAGES := sysupgrade.bin
+  IMAGE_SIZE := 15424k
+  SUPPORTED_DEVICES += R36
+  KERNEL := kernel-bin | lzma | \
+	fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb
+  KERNEL_INITRAMFS := kernel-bin | lzma | \
+	fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
+  IMAGE/sysupgrade.bin := append-kernel | pad-to 128k | append-rootfs | pad-rootfs | check-size | append-metadata
+  DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware
+endef
+TARGET_DEVICES += cudy_re3000-v1
+
 define Device/cudy_wr3000-v1
   DEVICE_VENDOR := Cudy
   DEVICE_MODEL := WR3000
@@ -622,7 +725,7 @@ define Device/mediatek_mt7988a-rfb
   DEVICE_DTS_DIR := $(DTS_DIR)/
   DEVICE_DTC_FLAGS := --pad 4096
   DEVICE_DTS_LOADADDR := 0x45f00000
-  DEVICE_PACKAGES := kmod-sfp
+  DEVICE_PACKAGES := mt7988-2p5g-phy-firmware kmod-sfp
   KERNEL_LOADADDR := 0x46000000
   KERNEL := kernel-bin | gzip
   KERNEL_INITRAMFS := kernel-bin | lzma | \
diff --git a/target/linux/mediatek/image/mt7622.mk b/target/linux/mediatek/image/mt7622.mk
index 7df5eade8220ed..f06175041e68b2 100644
--- a/target/linux/mediatek/image/mt7622.mk
+++ b/target/linux/mediatek/image/mt7622.mk
@@ -98,7 +98,7 @@ define Device/bananapi_bpi-r64
   KERNEL_INITRAMFS_SUFFIX := -recovery.itb
   ARTIFACT/emmc-preloader.bin	:= bl2 emmc-2ddr
   ARTIFACT/emmc-bl31-uboot.fip	:= bl31-uboot bananapi_bpi-r64-emmc
-  ARTIFACT/snand-preloader.bin	:= bl2 snand-2ddr
+  ARTIFACT/snand-preloader.bin	:= bl2 snand-ubi-2ddr
   ARTIFACT/snand-bl31-uboot.fip	:= bl31-uboot bananapi_bpi-r64-snand
   ARTIFACT/sdcard.img.gz	:= mt7622-gpt sdmmc |\
 				   pad-to 512k | bl2 sdmmc-2ddr |\
@@ -109,7 +109,7 @@ define Device/bananapi_bpi-r64
 				   pad-to 38912k | mt7622-gpt emmc |\
 				   pad-to 39424k | bl2 emmc-2ddr |\
 				   pad-to 40960k | bl31-uboot bananapi_bpi-r64-emmc |\
-				   pad-to 43008k | bl2 snand-2ddr |\
+				   pad-to 43008k | bl2 snand-ubi-2ddr |\
 				   pad-to 43520k | bl31-uboot bananapi_bpi-r64-snand |\
 				$(if $(CONFIG_TARGET_ROOTFS_SQUASHFS), \
 				   pad-to 46080k | append-image squashfs-sysupgrade.itb | check-size |\
@@ -121,8 +121,8 @@ endif
   KERNEL			:= kernel-bin | gzip
   KERNEL_INITRAMFS		:= kernel-bin | lzma | fit lzma $$(DTS_DIR)/$$(DEVICE_DTS).dtb with-initrd | pad-to 128k
   IMAGE/sysupgrade.itb		:= append-kernel | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb external-static-with-rootfs | append-metadata
-  DEVICE_COMPAT_VERSION := 1.1
-  DEVICE_COMPAT_MESSAGE := Device tree overlay mechanism needs bootloader update
+  DEVICE_COMPAT_VERSION := 1.2
+  DEVICE_COMPAT_MESSAGE := SPI-NAND flash layout changes require bootloader update
 endef
 TARGET_DEVICES += bananapi_bpi-r64
 
@@ -270,8 +270,10 @@ define Device/linksys_e8450-ubi
   IMAGES := sysupgrade.itb
   IMAGE/sysupgrade.itb := append-kernel | fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | append-metadata
   ARTIFACTS := preloader.bin bl31-uboot.fip
-  ARTIFACT/preloader.bin := bl2 snand-1ddr
+  ARTIFACT/preloader.bin := bl2 snand-ubi-1ddr
   ARTIFACT/bl31-uboot.fip := bl31-uboot linksys_e8450
+  DEVICE_COMPAT_VERSION := 2.0
+  DEVICE_COMPAT_MESSAGE := SPI-NAND flash layout changes require bootloader update
 endef
 TARGET_DEVICES += linksys_e8450-ubi
 
@@ -293,7 +295,7 @@ define Device/mediatek_mt7622-rfb1-ubi
   UBINIZE_OPTS := -E 5
   BLOCKSIZE := 128k
   PAGESIZE := 2048
-  KERNEL_SIZE := 4194304
+  KERNEL_SIZE := 6291456
   IMAGE_SIZE := 32768k
   IMAGES += factory.bin
   IMAGE/factory.bin := append-kernel | pad-to $$(KERNEL_SIZE) | append-ubi | \
@@ -464,4 +466,4 @@ define Device/xiaomi_redmi-router-ax6s
   IMAGE/factory.bin := append-kernel | pad-to $$(KERNEL_SIZE) | append-ubi
   IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
 endef
-TARGET_DEVICES += xiaomi_redmi-router-ax6s
+# TARGET_DEVICES += xiaomi_redmi-router-ax6s
diff --git a/target/linux/mediatek/image/mt7623.mk b/target/linux/mediatek/image/mt7623.mk
index 2c4402da661949..24663551e0f7cb 100644
--- a/target/linux/mediatek/image/mt7623.mk
+++ b/target/linux/mediatek/image/mt7623.mk
@@ -116,6 +116,8 @@ endif
 			    gzip
   ARTIFACTS := u-boot.bin preloader.bin sdcard.img.gz
   SUPPORTED_DEVICES := bananapi,bpi-r2
+  DEVICE_COMPAT_VERSION := 1.1
+  DEVICE_COMPAT_MESSAGE := Bootloader update required for switch to fitblk
 endef
 TARGET_DEVICES += bananapi_bpi-r2
 
diff --git a/target/linux/mediatek/mt7622/base-files/etc/board.d/05_compat-version b/target/linux/mediatek/mt7622/base-files/etc/board.d/05_compat-version
index c8fb2c08f69915..68c397a95c47a5 100644
--- a/target/linux/mediatek/mt7622/base-files/etc/board.d/05_compat-version
+++ b/target/linux/mediatek/mt7622/base-files/etc/board.d/05_compat-version
@@ -6,7 +6,10 @@ board_config_update
 
 case "$(board_name)" in
 	bananapi,bpi-r64)
-		ucidef_set_compat_version "1.1"
+		ucidef_set_compat_version "1.2"
+		;;
+	linksys,e8450-ubi)
+		ucidef_set_compat_version "2.0"
 		;;
 esac
 
diff --git a/target/linux/mediatek/mt7622/base-files/etc/uci-defaults/05_fix-compat-version b/target/linux/mediatek/mt7622/base-files/etc/uci-defaults/05_fix-compat-version
index 83310378694da7..6309728e4bc08c 100644
--- a/target/linux/mediatek/mt7622/base-files/etc/uci-defaults/05_fix-compat-version
+++ b/target/linux/mediatek/mt7622/base-files/etc/uci-defaults/05_fix-compat-version
@@ -1,11 +1,18 @@
 . /lib/functions.sh
 
 case "$(board_name)" in
-	bananapi,bpi-r64|\
+	bananapi,bpi-r64)
+	uci set system.@system[0].compat_version="1.2"
+	uci commit system
+	;;
 	buffalo,wsr-2533dhp2)
 	uci set system.@system[0].compat_version="1.1"
 	uci commit system
 	;;
+	linksys,e8450-ubi)
+	uci set system.@system[0].compat_version="2.0"
+	uci commit system
+	;;
 esac
 
 exit 0
diff --git a/target/linux/mediatek/mt7622/base-files/lib/upgrade/platform.sh b/target/linux/mediatek/mt7622/base-files/lib/upgrade/platform.sh
index 3a2d7a4cd62d05..236e8fdfb05a80 100755
--- a/target/linux/mediatek/mt7622/base-files/lib/upgrade/platform.sh
+++ b/target/linux/mediatek/mt7622/base-files/lib/upgrade/platform.sh
@@ -1,26 +1,35 @@
 REQUIRE_IMAGE_METADATA=1
+RAMFS_COPY_BIN='fitblk'
 
 platform_do_upgrade() {
 	local board=$(board_name)
 	local file_type=$(identify $1)
 
 	case "$board" in
-	bananapi,bpi-r64)
-		local rootdev="$(cmdline_get_var root)"
-		rootdev="${rootdev##*/}"
-		rootdev="${rootdev%p[0-9]*}"
-		case "$rootdev" in
-		mmc*)
-			CI_ROOTDEV="$rootdev"
-			CI_KERNPART="production"
+	bananapi,bpi-r64|\
+	linksys,e8450-ubi|\
+	ubnt,unifi-6-lr-v1-ubootmod|\
+	ubnt,unifi-6-lr-v2-ubootmod|\
+	ubnt,unifi-6-lr-v3-ubootmod)
+		[ -e /dev/fit0 ] && fitblk /dev/fit0
+		[ -e /dev/fitrw ] && fitblk /dev/fitrw
+		bootdev="$(fitblk_get_bootdev)"
+		case "$bootdev" in
+		mmcblk*)
+			EMMC_KERN_DEV="/dev/$bootdev"
 			emmc_do_upgrade "$1"
 			;;
-		*)
+		mtdblock*)
+			PART_NAME="/dev/mtd${bootdev:8}"
+			default_do_upgrade "$1"
+			;;
+		ubiblock*)
 			CI_KERNPART="fit"
 			nand_do_upgrade "$1"
 			;;
 		esac
 		;;
+
 	buffalo,wsr-2533dhp2|\
 	buffalo,wsr-3200ax4s)
 		local magic="$(get_magic_long "$1")"
@@ -43,10 +52,6 @@ platform_do_upgrade() {
 	xiaomi,redmi-router-ax6s)
 		nand_do_upgrade "$1"
 		;;
-	linksys,e8450-ubi)
-		CI_KERNPART="fit"
-		nand_do_upgrade "$1"
-		;;
 	linksys,e8450)
 		if grep -q mtdparts=slave /proc/cmdline; then
 			PART_NAME=firmware2
@@ -99,9 +104,7 @@ platform_check_image() {
 platform_copy_config() {
 	case "$(board_name)" in
 	bananapi,bpi-r64)
-		export_bootdevice
-		export_partdevice rootdev 0
-		if echo $rootdev | grep -q mmc; then
+		if fitblk_get_bootdev | grep -q mmc; then
 			emmc_copy_config
 		fi
 		;;
diff --git a/target/linux/mediatek/mt7622/config-5.15 b/target/linux/mediatek/mt7622/config-5.15
deleted file mode 100644
index 7bca33c0aebb05..00000000000000
--- a/target/linux/mediatek/mt7622/config-5.15
+++ /dev/null
@@ -1,444 +0,0 @@
-CONFIG_64BIT=y
-# CONFIG_AHCI_MTK is not set
-CONFIG_AQUANTIA_PHY=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MEDIATEK=y
-CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
-CONFIG_ARCH_MMAP_RND_BITS=18
-CONFIG_ARCH_MMAP_RND_BITS_MAX=24
-CONFIG_ARCH_MMAP_RND_BITS_MIN=18
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
-CONFIG_ARCH_PROC_KCORE_TEXT=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_STACKWALK=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_WANTS_NO_INSTR=y
-CONFIG_ARM64=y
-CONFIG_ARM64_4K_PAGES=y
-CONFIG_ARM64_CRYPTO=y
-CONFIG_ARM64_ERRATUM_843419=y
-CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
-CONFIG_ARM64_PAGE_SHIFT=12
-CONFIG_ARM64_PA_BITS=48
-CONFIG_ARM64_PA_BITS_48=y
-CONFIG_ARM64_TAGGED_ADDR_ABI=y
-CONFIG_ARM64_VA_BITS=39
-CONFIG_ARM64_VA_BITS_39=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_GIC_V2M=y
-CONFIG_ARM_GIC_V3=y
-CONFIG_ARM_GIC_V3_ITS=y
-CONFIG_ARM_GIC_V3_ITS_PCI=y
-CONFIG_ARM_MEDIATEK_CPUFREQ=y
-CONFIG_ARM_PMU=y
-CONFIG_ARM_PSCI_FW=y
-CONFIG_ATA=y
-CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BLK_PM=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_BSD_PROCESS_ACCT_V3=y
-CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
-CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLONE_BACKWARDS=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_MEDIATEK=y
-CONFIG_COMMON_CLK_MT2712=y
-# CONFIG_COMMON_CLK_MT2712_BDPSYS is not set
-# CONFIG_COMMON_CLK_MT2712_IMGSYS is not set
-# CONFIG_COMMON_CLK_MT2712_JPGDECSYS is not set
-# CONFIG_COMMON_CLK_MT2712_MFGCFG is not set
-# CONFIG_COMMON_CLK_MT2712_MMSYS is not set
-# CONFIG_COMMON_CLK_MT2712_VDECSYS is not set
-# CONFIG_COMMON_CLK_MT2712_VENCSYS is not set
-# CONFIG_COMMON_CLK_MT6779 is not set
-# CONFIG_COMMON_CLK_MT6797 is not set
-CONFIG_COMMON_CLK_MT7622=y
-CONFIG_COMMON_CLK_MT7622_AUDSYS=y
-CONFIG_COMMON_CLK_MT7622_ETHSYS=y
-CONFIG_COMMON_CLK_MT7622_HIFSYS=y
-# CONFIG_COMMON_CLK_MT7981 is not set
-# CONFIG_COMMON_CLK_MT7986 is not set
-# CONFIG_COMMON_CLK_MT7988 is not set
-# CONFIG_COMMON_CLK_MT8173 is not set
-# CONFIG_COMMON_CLK_MT8183 is not set
-# CONFIG_COMMON_CLK_MT8516 is not set
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15
-# CONFIG_CPUFREQ_DT is not set
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_THERMAL=y
-CONFIG_CRC16=y
-CONFIG_CRYPTO_AES_ARM64=y
-CONFIG_CRYPTO_AES_ARM64_CE=y
-CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
-CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
-CONFIG_CRYPTO_CMAC=y
-CONFIG_CRYPTO_CRC32=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_CRYPTD=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_DRBG=y
-CONFIG_CRYPTO_DRBG_HMAC=y
-CONFIG_CRYPTO_DRBG_MENU=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_ECC=y
-CONFIG_CRYPTO_ECDH=y
-CONFIG_CRYPTO_GHASH_ARM64_CE=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_JITTERENTROPY=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_RNG_DEFAULT=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA256_ARM64=y
-CONFIG_CRYPTO_SHA2_ARM64_CE=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_SIMD=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_MISC=y
-CONFIG_DIMLIB=y
-CONFIG_DMADEVICES=y
-CONFIG_DMA_DIRECT_REMAP=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_REMAP=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DTC=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EINT_MTK=y
-CONFIG_EXT4_FS=y
-CONFIG_F2FS_FS=y
-CONFIG_FIT_PARTITION=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FRAME_POINTER=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_CSUM=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_FIND_FIRST_BIT=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GLOB=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GRO_CELLS=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_MTK=y
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_MT65XX=y
-CONFIG_ICPLUS_PHY=y
-CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_TIME_ACCOUNTING=y
-CONFIG_IRQ_WORK=y
-CONFIG_JBD2=y
-CONFIG_JUMP_LABEL=y
-# CONFIG_LEDS_SMARTRG_LED is not set
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-# CONFIG_MEDIATEK_2P5G_PHY is not set
-CONFIG_MEDIATEK_GE_PHY=y
-# CONFIG_MEDIATEK_GE_SOC_PHY is not set
-CONFIG_MEDIATEK_WATCHDOG=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_CQHCI=y
-CONFIG_MMC_MTK=y
-CONFIG_MODULES_TREE_LOOKUP=y
-CONFIG_MODULES_USE_ELF_RELA=y
-CONFIG_MTD_NAND_CORE=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_ECC_MEDIATEK=y
-CONFIG_MTD_NAND_ECC_SW_HAMMING=y
-CONFIG_MTD_NAND_MTK=y
-CONFIG_MTD_NAND_MTK_BMT=y
-CONFIG_MTD_PARSER_TRX=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_SPI_NAND=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_SPLIT_FIT_FW=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_UBI_FASTMAP=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-# CONFIG_MTK_CMDQ is not set
-# CONFIG_MTK_CQDMA is not set
-CONFIG_MTK_HSDMA=y
-CONFIG_MTK_INFRACFG=y
-CONFIG_MTK_PMIC_WRAP=y
-CONFIG_MTK_SCPSYS=y
-CONFIG_MTK_SCPSYS_PM_DOMAINS=y
-CONFIG_MTK_THERMAL=y
-CONFIG_MTK_TIMER=y
-# CONFIG_MTK_UART_APDMA is not set
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-CONFIG_NET_DEVLINK=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_MT7530=y
-CONFIG_NET_DSA_MT7530_MDIO=y
-# CONFIG_NET_DSA_MT7530_MMIO is not set
-CONFIG_NET_DSA_TAG_MTK=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_MEDIATEK_SOC=y
-# CONFIG_NET_MEDIATEK_SOC_USXGMII is not set
-CONFIG_NET_MEDIATEK_SOC_WED=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NET_VENDOR_MEDIATEK=y
-CONFIG_NLS=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=2
-CONFIG_NVMEM=y
-CONFIG_NVMEM_LAYOUTS=y
-CONFIG_NVMEM_MTK_EFUSE=y
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_DYNAMIC=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_OVERLAY=y
-CONFIG_OF_RESOLVE=y
-CONFIG_PADATA=y
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_POOL_STATS=y
-CONFIG_PARTITION_PERCPU=y
-CONFIG_PCI=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEASPM=y
-# CONFIG_PCIEASPM_DEFAULT is not set
-CONFIG_PCIEASPM_PERFORMANCE=y
-# CONFIG_PCIEASPM_POWERSAVE is not set
-# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_MEDIATEK=y
-CONFIG_PCIE_PME=y
-CONFIG_PCI_DEBUG=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PCS_MTK_LYNXI=y
-CONFIG_PERF_EVENTS=y
-CONFIG_PGTABLE_LEVELS=3
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_PHY_MTK_TPHY=y
-# CONFIG_PHY_MTK_UFS is not set
-# CONFIG_PHY_MTK_XSPHY is not set
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_MT2712 is not set
-# CONFIG_PINCTRL_MT6765 is not set
-# CONFIG_PINCTRL_MT6797 is not set
-CONFIG_PINCTRL_MT7622=y
-# CONFIG_PINCTRL_MT7981 is not set
-# CONFIG_PINCTRL_MT7986 is not set
-# CONFIG_PINCTRL_MT7988 is not set
-# CONFIG_PINCTRL_MT8173 is not set
-# CONFIG_PINCTRL_MT8183 is not set
-CONFIG_PINCTRL_MT8516=y
-CONFIG_PINCTRL_MTK=y
-CONFIG_PINCTRL_MTK_MOORE=y
-CONFIG_PINCTRL_MTK_V2=y
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_PM_GENERIC_DOMAINS=y
-CONFIG_PM_GENERIC_DOMAINS_OF=y
-CONFIG_PM_OPP=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_SYSCON=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PRINTK_TIME=y
-CONFIG_PSTORE=y
-CONFIG_PSTORE_COMPRESS=y
-CONFIG_PSTORE_COMPRESS_DEFAULT="deflate"
-CONFIG_PSTORE_CONSOLE=y
-CONFIG_PSTORE_DEFLATE_COMPRESS=y
-CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y
-CONFIG_PSTORE_PMSG=y
-CONFIG_PSTORE_RAM=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PWM=y
-CONFIG_PWM_MEDIATEK=y
-# CONFIG_PWM_MTK_DISP is not set
-CONFIG_PWM_SYSFS=y
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_QUEUED_SPINLOCKS=y
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-# CONFIG_RAVE_SP_CORE is not set
-CONFIG_REALTEK_PHY=y
-CONFIG_REED_SOLOMON=y
-CONFIG_REED_SOLOMON_DEC8=y
-CONFIG_REED_SOLOMON_ENC8=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_MT6380=y
-# CONFIG_REGULATOR_RT5190A is not set
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_MT7622=y
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RTL8367S_GSW=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_SCHED_MC=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_MT6577=y
-CONFIG_SERIAL_8250_NR_UARTS=3
-CONFIG_SERIAL_8250_RUNTIME_UARTS=3
-CONFIG_SERIAL_DEV_BUS=y
-CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SG_POOL=y
-CONFIG_SMP=y
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SPARSEMEM=y
-CONFIG_SPARSEMEM_EXTREME=y
-CONFIG_SPARSEMEM_VMEMMAP=y
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_DYNAMIC=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_MT65XX=y
-CONFIG_SPI_MTK_NOR=y
-CONFIG_SPI_MTK_SNFI=y
-CONFIG_SRCU=y
-CONFIG_SWCONFIG=y
-CONFIG_SWIOTLB=y
-CONFIG_SWPHY=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_EMULATION=y
-CONFIG_THERMAL_GOV_BANG_BANG=y
-CONFIG_THERMAL_GOV_FAIR_SHARE=y
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_GOV_USER_SPACE=y
-CONFIG_THERMAL_OF=y
-CONFIG_THERMAL_WRITABLE_TRIPS=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UBIFS_FS=y
-# CONFIG_UCLAMP_TASK is not set
-# CONFIG_UNMAP_KERNEL_AT_EL0 is not set
-CONFIG_USB_SUPPORT=y
-CONFIG_VMAP_STACK=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y
-CONFIG_WATCHDOG_PRETIMEOUT_GOV=y
-# CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP is not set
-CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y
-CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m
-CONFIG_WATCHDOG_SYSFS=y
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZONE_DMA32=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
diff --git a/target/linux/mediatek/mt7622/config-6.1 b/target/linux/mediatek/mt7622/config-6.1
index 89260f78eedf71..84af474e522f01 100644
--- a/target/linux/mediatek/mt7622/config-6.1
+++ b/target/linux/mediatek/mt7622/config-6.1
@@ -151,7 +151,7 @@ CONFIG_EINT_MTK=y
 CONFIG_EXCLUSIVE_SYSTEM_RAM=y
 CONFIG_EXT4_FS=y
 CONFIG_F2FS_FS=y
-CONFIG_FIT_PARTITION=y
+# CONFIG_FIT_PARTITION is not set
 CONFIG_FIXED_PHY=y
 CONFIG_FIX_EARLYCON_MEM=y
 CONFIG_FRAME_POINTER=y
@@ -257,6 +257,7 @@ CONFIG_MTD_UBI=y
 CONFIG_MTD_UBI_BEB_LIMIT=20
 CONFIG_MTD_UBI_BLOCK=y
 CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_MTD_UBI_NVMEM=y
 CONFIG_MTD_UBI_WL_THRESHOLD=4096
 # CONFIG_MTK_CMDQ is not set
 # CONFIG_MTK_CQDMA is not set
@@ -267,6 +268,8 @@ CONFIG_MTK_SCPSYS=y
 CONFIG_MTK_SCPSYS_PM_DOMAINS=y
 # CONFIG_MTK_SVS is not set
 CONFIG_MTK_THERMAL=y
+CONFIG_MTK_SOC_THERMAL=y
+# CONFIG_MTK_LVTS_THERMAL is not set
 CONFIG_MTK_TIMER=y
 # CONFIG_MTK_UART_APDMA is not set
 CONFIG_MUTEX_SPIN_ON_OWNER=y
@@ -453,6 +456,7 @@ CONFIG_TREE_RCU=y
 CONFIG_TREE_SRCU=y
 CONFIG_UBIFS_FS=y
 # CONFIG_UCLAMP_TASK is not set
+CONFIG_UIMAGE_FIT_BLK=y
 # CONFIG_UNMAP_KERNEL_AT_EL0 is not set
 CONFIG_USB_SUPPORT=y
 CONFIG_VMAP_STACK=y
diff --git a/target/linux/mediatek/mt7622/target.mk b/target/linux/mediatek/mt7622/target.mk
index 7742672a513b2e..ea0e22e314f203 100644
--- a/target/linux/mediatek/mt7622/target.mk
+++ b/target/linux/mediatek/mt7622/target.mk
@@ -2,7 +2,7 @@ ARCH:=aarch64
 SUBTARGET:=mt7622
 BOARDNAME:=MT7622
 CPU_TYPE:=cortex-a53
-DEFAULT_PACKAGES += kmod-mt7622-firmware wpad-basic-mbedtls uboot-envtools
+DEFAULT_PACKAGES += fitblk kmod-mt7622-firmware wpad-basic-mbedtls uboot-envtools
 KERNELNAME:=Image dtbs
 
 define Target/Description
diff --git a/target/linux/mediatek/mt7623/base-files/etc/board.d/05_compat-version b/target/linux/mediatek/mt7623/base-files/etc/board.d/05_compat-version
new file mode 100644
index 00000000000000..a4cf133a69b582
--- /dev/null
+++ b/target/linux/mediatek/mt7623/base-files/etc/board.d/05_compat-version
@@ -0,0 +1,14 @@
+. /lib/functions.sh
+. /lib/functions/uci-defaults.sh
+
+board_config_update
+
+case "$(board_name)" in
+bananapi,bpi-r2)
+	ucidef_set_compat_version "1.1"
+	;;
+esac
+
+board_config_flush
+
+exit 0
diff --git a/target/linux/mediatek/mt7623/base-files/etc/uci-defaults/05_fix-compat-version b/target/linux/mediatek/mt7623/base-files/etc/uci-defaults/05_fix-compat-version
new file mode 100644
index 00000000000000..ae3f16002f1df2
--- /dev/null
+++ b/target/linux/mediatek/mt7623/base-files/etc/uci-defaults/05_fix-compat-version
@@ -0,0 +1,10 @@
+. /lib/functions.sh
+
+case "$(board_name)" in
+bananapi,bpi-r2)
+	uci set system.@system[0].compat_version="1.1"
+	uci commit system
+	;;
+esac
+
+exit 0
diff --git a/target/linux/mediatek/mt7623/base-files/lib/upgrade/platform.sh b/target/linux/mediatek/mt7623/base-files/lib/upgrade/platform.sh
index 5d12b6989e574a..9cfb15cf3d4787 100755
--- a/target/linux/mediatek/mt7623/base-files/lib/upgrade/platform.sh
+++ b/target/linux/mediatek/mt7623/base-files/lib/upgrade/platform.sh
@@ -83,10 +83,10 @@ platform_do_upgrade() {
 	case "$board" in
 	bananapi,bpi-r2|\
 	unielec,u7623-02)
-		export_bootdevice
-		export_partdevice fitpart 3
-		[ "$fitpart" ] || return 1
-		EMMC_KERN_DEV="/dev/$fitpart"
+		[ -e /dev/fit0 ] && fitblk /dev/fit0
+		[ -e /dev/fitrw ] && fitblk /dev/fitrw
+		bootdev="$(fitblk_get_bootdev)"
+		EMMC_KERN_DEV="/dev/$bootdev"
 		emmc_do_upgrade "$1"
 		;;
 	unielec,u7623-02-emmc-512m)
diff --git a/target/linux/mediatek/mt7623/config-5.15 b/target/linux/mediatek/mt7623/config-5.15
deleted file mode 100644
index 2f12488327e8ad..00000000000000
--- a/target/linux/mediatek/mt7623/config-5.15
+++ /dev/null
@@ -1,577 +0,0 @@
-# CONFIG_AIO is not set
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MEDIATEK=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM=y
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-# CONFIG_ARM_ATAG_DTB_COMPAT is not set
-CONFIG_ARM_CPU_SUSPEND=y
-# CONFIG_ARM_CPU_TOPOLOGY is not set
-CONFIG_ARM_CRYPTO=y
-CONFIG_ARM_DMA_IOMMU_ALIGNMENT=8
-CONFIG_ARM_DMA_USE_IOMMU=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_HAS_SG_CHAIN=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-CONFIG_ARM_MEDIATEK_CPUFREQ=y
-CONFIG_ARM_PATCH_IDIV=y
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-# CONFIG_ARM_SMMU is not set
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_THUMBEE=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y
-CONFIG_ATAGS=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_GPIO=y
-CONFIG_BACKLIGHT_LED=y
-CONFIG_BACKLIGHT_PWM=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BLK_PM=y
-CONFIG_BOUNCE=y
-# CONFIG_CACHE_L2X0 is not set
-CONFIG_CLEANCACHE=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="earlyprintk console=ttyS0,115200 rootfstype=squashfs,jffs2"
-CONFIG_CMDLINE_FROM_BOOTLOADER=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-CONFIG_CMDLINE_PARTITION=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_MEDIATEK=y
-CONFIG_COMMON_CLK_MT2701=y
-CONFIG_COMMON_CLK_MT2701_AUDSYS=y
-CONFIG_COMMON_CLK_MT2701_BDPSYS=y
-CONFIG_COMMON_CLK_MT2701_ETHSYS=y
-CONFIG_COMMON_CLK_MT2701_G3DSYS=y
-CONFIG_COMMON_CLK_MT2701_HIFSYS=y
-CONFIG_COMMON_CLK_MT2701_IMGSYS=y
-CONFIG_COMMON_CLK_MT2701_MMSYS=y
-CONFIG_COMMON_CLK_MT2701_VDECSYS=y
-# CONFIG_COMMON_CLK_MT7622 is not set
-# CONFIG_COMMON_CLK_MT7629 is not set
-# CONFIG_COMMON_CLK_MT7981 is not set
-# CONFIG_COMMON_CLK_MT7986 is not set
-# CONFIG_COMMON_CLK_MT7988 is not set
-# CONFIG_COMMON_CLK_MT8135 is not set
-# CONFIG_COMMON_CLK_MT8173 is not set
-CONFIG_COMMON_CLK_MT8516=y
-# CONFIG_COMMON_CLK_MT8516_AUDSYS is not set
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_COREDUMP=y
-# CONFIG_CPUFREQ_DT is not set
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_SPECTRE=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRC16=y
-# CONFIG_CRC32_SARWATE is not set
-CONFIG_CRC32_SLICEBY8=y
-CONFIG_CROSS_MEMORY_ATTACH=y
-CONFIG_CRYPTO_CRC32=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_DRBG=y
-CONFIG_CRYPTO_DRBG_HMAC=y
-CONFIG_CRYPTO_DRBG_MENU=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_JITTERENTROPY=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_RNG_DEFAULT=y
-CONFIG_CRYPTO_SEQIV=y
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_ALIGN_RODATA=y
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_GPIO=y
-CONFIG_DEBUG_LL=y
-CONFIG_DEBUG_LL_INCLUDE="debug/8250.S"
-CONFIG_DEBUG_MISC=y
-CONFIG_DEBUG_MT6589_UART0=y
-# CONFIG_DEBUG_MT8127_UART0 is not set
-# CONFIG_DEBUG_MT8135_UART3 is not set
-CONFIG_DEBUG_PREEMPT=y
-CONFIG_DEBUG_UART_8250=y
-CONFIG_DEBUG_UART_8250_SHIFT=2
-CONFIG_DEBUG_UART_PHYS=0x11004000
-CONFIG_DEBUG_UART_VIRT=0xf1004000
-CONFIG_DEBUG_UNCOMPRESS=y
-# CONFIG_DEVFREQ_GOV_PASSIVE is not set
-# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set
-# CONFIG_DEVFREQ_GOV_POWERSAVE is not set
-CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
-# CONFIG_DEVFREQ_GOV_USERSPACE is not set
-# CONFIG_DEVFREQ_THERMAL is not set
-CONFIG_DIMLIB=y
-CONFIG_DMADEVICES=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_OPS=y
-CONFIG_DMA_REMAP=y
-CONFIG_DMA_SHARED_BUFFER=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DRM=y
-CONFIG_DRM_BRIDGE=y
-CONFIG_DRM_DISPLAY_CONNECTOR=y
-CONFIG_DRM_FBDEV_EMULATION=y
-CONFIG_DRM_FBDEV_OVERALLOC=100
-CONFIG_DRM_GEM_CMA_HELPER=y
-CONFIG_DRM_GEM_SHMEM_HELPER=y
-CONFIG_DRM_KMS_HELPER=y
-CONFIG_DRM_LIMA=y
-CONFIG_DRM_LVDS_CODEC=y
-CONFIG_DRM_MEDIATEK=y
-CONFIG_DRM_MEDIATEK_HDMI=y
-CONFIG_DRM_MIPI_DSI=y
-CONFIG_DRM_PANEL=y
-CONFIG_DRM_PANEL_BRIDGE=y
-CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
-CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=y
-CONFIG_DRM_SCHED=y
-CONFIG_DRM_SIMPLE_BRIDGE=y
-CONFIG_DTC=y
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EINT_MTK=y
-CONFIG_ELF_CORE=y
-CONFIG_EXT4_FS=y
-CONFIG_EXTCON=y
-CONFIG_F2FS_FS=y
-CONFIG_FB=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-CONFIG_FB_CMDLINE=y
-CONFIG_FB_DEFERRED_IO=y
-CONFIG_FB_SYS_COPYAREA=y
-CONFIG_FB_SYS_FILLRECT=y
-CONFIG_FB_SYS_FOPS=y
-CONFIG_FB_SYS_IMAGEBLIT=y
-CONFIG_FIT_PARTITION=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FONT_8x16=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_SUPPORT=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
-CONFIG_FREEZER=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_CACHE=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MIGRATION=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GENERIC_VDSO_32=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GRO_CELLS=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDEN_BRANCH_PREDICTOR=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HAVE_SMP=y
-CONFIG_HDMI=y
-CONFIG_HID=y
-CONFIG_HIGHMEM=y
-CONFIG_HIGHPTE=y
-CONFIG_HOTPLUG_CPU=y
-CONFIG_HWMON=y
-CONFIG_HW_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_MTK=y
-CONFIG_HZ_FIXED=0
-CONFIG_I2C=y
-CONFIG_I2C_ALGOBIT=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_MT65XX=y
-CONFIG_ICPLUS_PHY=y
-CONFIG_IIO=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_IOMMU_API=y
-# CONFIG_IOMMU_DEBUGFS is not set
-CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
-CONFIG_IOMMU_IO_PGTABLE=y
-CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y
-# CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST is not set
-# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
-CONFIG_IOMMU_SUPPORT=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_JBD2=y
-CONFIG_KALLSYMS=y
-CONFIG_KCMP=y
-CONFIG_KEYBOARD_MTK_PMIC=y
-CONFIG_KMAP_LOCAL=y
-CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
-CONFIG_LCD_CLASS_DEVICE=y
-CONFIG_LCD_PLATFORM=y
-CONFIG_LEDS_MT6323=y
-# CONFIG_LEDS_SMARTRG_LED is not set
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LOGO=y
-CONFIG_LOGO_LINUX_CLUT224=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-# CONFIG_MACH_MT2701 is not set
-# CONFIG_MACH_MT6589 is not set
-# CONFIG_MACH_MT6592 is not set
-CONFIG_MACH_MT7623=y
-# CONFIG_MACH_MT7629 is not set
-# CONFIG_MACH_MT8127 is not set
-# CONFIG_MACH_MT8135 is not set
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MAILBOX=y
-# CONFIG_MAILBOX_TEST is not set
-CONFIG_MDIO_BITBANG=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MDIO_GPIO=y
-CONFIG_MEDIATEK_GE_PHY=y
-CONFIG_MEDIATEK_MT6577_AUXADC=y
-CONFIG_MEDIATEK_WATCHDOG=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MEMORY=y
-CONFIG_MFD_CORE=y
-# CONFIG_MFD_HI6421_SPMI is not set
-CONFIG_MFD_MT6397=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_CQHCI=y
-CONFIG_MMC_MTK=y
-CONFIG_MMC_SDHCI=y
-# CONFIG_MMC_SDHCI_PCI is not set
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MTD_CMDLINE_PARTS=y
-# CONFIG_MTD_NAND_ECC_MEDIATEK is not set
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_SPLIT_UIMAGE_FW=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MTK_CMDQ=y
-CONFIG_MTK_CMDQ_MBOX=y
-CONFIG_MTK_CQDMA=y
-# CONFIG_MTK_HSDMA is not set
-CONFIG_MTK_INFRACFG=y
-CONFIG_MTK_IOMMU=y
-CONFIG_MTK_IOMMU_V1=y
-CONFIG_MTK_MMSYS=y
-CONFIG_MTK_PMIC_WRAP=y
-CONFIG_MTK_SCPSYS=y
-CONFIG_MTK_SCPSYS_PM_DOMAINS=y
-CONFIG_MTK_SMI=y
-CONFIG_MTK_THERMAL=y
-CONFIG_MTK_TIMER=y
-# CONFIG_MTK_UART_APDMA is not set
-# CONFIG_MUSB_PIO_ONLY is not set
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-CONFIG_NEON=y
-CONFIG_NET_DEVLINK=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_MT7530=y
-CONFIG_NET_DSA_MT7530_MDIO=y
-# CONFIG_NET_DSA_MT7530_MMIO is not set
-CONFIG_NET_DSA_TAG_MTK=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_MEDIATEK_SOC=y
-CONFIG_NET_MEDIATEK_SOC_WED=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NET_VENDOR_MEDIATEK=y
-# CONFIG_NET_VENDOR_WIZNET is not set
-CONFIG_NLS=y
-CONFIG_NOP_USB_XCEIV=y
-CONFIG_NO_HZ=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=4
-CONFIG_NVMEM=y
-CONFIG_NVMEM_MTK_EFUSE=y
-# CONFIG_NVMEM_SPMI_SDAM is not set
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_DYNAMIC=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IOMMU=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_OVERLAY=y
-CONFIG_OF_RESOLVE=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_PADATA=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_POOL_STATS=y
-CONFIG_PCI=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_MEDIATEK=y
-CONFIG_PCIE_PME=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PCS_MTK_LYNXI=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-CONFIG_PHY_MTK_HDMI=y
-CONFIG_PHY_MTK_MIPI_DSI=y
-CONFIG_PHY_MTK_TPHY=y
-# CONFIG_PHY_MTK_UFS is not set
-# CONFIG_PHY_MTK_XSPHY is not set
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_MT2701=y
-CONFIG_PINCTRL_MT6397=y
-CONFIG_PINCTRL_MT7623=y
-CONFIG_PINCTRL_MTK=y
-CONFIG_PINCTRL_MTK_MOORE=y
-CONFIG_PINCTRL_MTK_V2=y
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_PM_DEVFREQ=y
-# CONFIG_PM_DEVFREQ_EVENT is not set
-CONFIG_PM_GENERIC_DOMAINS=y
-CONFIG_PM_GENERIC_DOMAINS_OF=y
-CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
-CONFIG_PM_OPP=y
-CONFIG_PM_SLEEP=y
-CONFIG_PM_SLEEP_SMP=y
-CONFIG_POWER_RESET=y
-# CONFIG_POWER_RESET_MT6323 is not set
-CONFIG_POWER_SUPPLY=y
-CONFIG_POWER_SUPPLY_HWMON=y
-CONFIG_PREEMPT=y
-CONFIG_PREEMPTION=y
-CONFIG_PREEMPT_COUNT=y
-# CONFIG_PREEMPT_NONE is not set
-CONFIG_PREEMPT_RCU=y
-CONFIG_PRINTK_TIME=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PWM=y
-CONFIG_PWM_MEDIATEK=y
-# CONFIG_PWM_MTK_DISP is not set
-CONFIG_PWM_SYSFS=y
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_GPIO=y
-CONFIG_REGULATOR_MT6323=y
-# CONFIG_REGULATOR_MT6358 is not set
-# CONFIG_REGULATOR_MT6380 is not set
-# CONFIG_REGULATOR_MT6397 is not set
-# CONFIG_REGULATOR_RT5190A is not set
-# CONFIG_REGULATOR_QCOM_LABIBB is not set
-# CONFIG_REGULATOR_QCOM_SPMI is not set
-# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-# CONFIG_RTC_DRV_MT6397 is not set
-# CONFIG_RTC_DRV_MT7622 is not set
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RTC_MC146818_LIB=y
-# CONFIG_RTL8367S_GSW is not set
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-# CONFIG_SERIAL_8250_DMA is not set
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_MT6577=y
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_BITBANG=y
-CONFIG_SPI_DYNAMIC=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_MT65XX=y
-# CONFIG_SPI_MTK_NOR is not set
-CONFIG_SPMI=y
-# CONFIG_SPMI_HISI3670 is not set
-CONFIG_SRCU=y
-# CONFIG_STRIP_ASM_SYMS is not set
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-CONFIG_SWPHY=y
-CONFIG_SWP_EMULATE=y
-CONFIG_SYNC_FILE=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_OF=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TOUCHSCREEN_EDT_FT5X06=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-# CONFIG_UACCE is not set
-CONFIG_UBIFS_FS=y
-CONFIG_UEVENT_HELPER_PATH=""
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNINLINE_SPIN_UNLOCK=y
-CONFIG_UNWINDER_ARM=y
-CONFIG_USB=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_F_ACM=y
-CONFIG_USB_F_ECM=y
-CONFIG_USB_F_MASS_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GPIO_VBUS=y
-CONFIG_USB_G_MULTI=y
-CONFIG_USB_G_MULTI_CDC=y
-# CONFIG_USB_G_MULTI_RNDIS is not set
-CONFIG_USB_HID=y
-CONFIG_USB_HIDDEV=y
-CONFIG_USB_INVENTRA_DMA=y
-CONFIG_USB_LIBCOMPOSITE=y
-CONFIG_USB_MUSB_DUAL_ROLE=y
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_USB_MUSB_MEDIATEK=y
-CONFIG_USB_OTG=y
-CONFIG_USB_PHY=y
-CONFIG_USB_ROLE_SWITCH=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_U_ETHER=y
-CONFIG_USB_U_SERIAL=y
-CONFIG_USE_OF=y
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_VIDEOMODE_HELPERS=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_VT_CONSOLE_SLEEP=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
diff --git a/target/linux/mediatek/mt7623/config-6.1 b/target/linux/mediatek/mt7623/config-6.1
index 218016b200c3df..a083809e345be8 100644
--- a/target/linux/mediatek/mt7623/config-6.1
+++ b/target/linux/mediatek/mt7623/config-6.1
@@ -214,7 +214,7 @@ CONFIG_FB_SYS_COPYAREA=y
 CONFIG_FB_SYS_FILLRECT=y
 CONFIG_FB_SYS_FOPS=y
 CONFIG_FB_SYS_IMAGEBLIT=y
-CONFIG_FIT_PARTITION=y
+# CONFIG_FIT_PARTITION is not set
 CONFIG_FIXED_PHY=y
 CONFIG_FIX_EARLYCON_MEM=y
 CONFIG_FONT_8x16=y
@@ -385,6 +385,8 @@ CONFIG_MTK_SCPSYS_PM_DOMAINS=y
 CONFIG_MTK_SMI=y
 # CONFIG_MTK_SVS is not set
 CONFIG_MTK_THERMAL=y
+CONFIG_MTK_SOC_THERMAL=y
+# CONFIG_MTK_LVTS_THERMAL is not set
 CONFIG_MTK_TIMER=y
 # CONFIG_MTK_UART_APDMA is not set
 # CONFIG_MUSB_PIO_ONLY is not set
@@ -561,6 +563,7 @@ CONFIG_TREE_SRCU=y
 # CONFIG_UACCE is not set
 CONFIG_UBIFS_FS=y
 CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_UIMAGE_FIT_BLK=y
 CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
 CONFIG_UNINLINE_SPIN_UNLOCK=y
 CONFIG_UNWINDER_ARM=y
diff --git a/target/linux/mediatek/mt7623/target.mk b/target/linux/mediatek/mt7623/target.mk
index 1338b091e376f7..4f84a98ff45cbd 100644
--- a/target/linux/mediatek/mt7623/target.mk
+++ b/target/linux/mediatek/mt7623/target.mk
@@ -9,7 +9,7 @@ CPU_TYPE:=cortex-a7
 CPU_SUBTYPE:=neon-vfpv4
 KERNELNAME:=Image dtbs zImage
 FEATURES+=display usbgadget
-DEFAULT_PACKAGES+=kmod-crypto-hw-safexcel uboot-envtools
+DEFAULT_PACKAGES+=fitblk kmod-crypto-hw-safexcel uboot-envtools
 
 define Target/Description
 	Build firmware images for MediaTek mt7623 ARM based boards.
diff --git a/target/linux/mediatek/mt7629/config-5.15 b/target/linux/mediatek/mt7629/config-5.15
deleted file mode 100644
index 8cddb04d6677b7..00000000000000
--- a/target/linux/mediatek/mt7629/config-5.15
+++ /dev/null
@@ -1,326 +0,0 @@
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MEDIATEK=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-CONFIG_ARM_CRYPTO=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_HAS_SG_CHAIN=y
-CONFIG_ARM_HEAVY_MB=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-CONFIG_ARM_PATCH_IDIV=y
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_ATAGS=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BLK_PM=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_BSD_PROCESS_ACCT_V3=y
-CONFIG_CACHE_L2X0=y
-# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_CHR_DEV_SCH=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
-CONFIG_CMDLINE_FROM_BOOTLOADER=y
-CONFIG_CMDLINE_OVERRIDE=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_MEDIATEK=y
-# CONFIG_COMMON_CLK_MT2701 is not set
-# CONFIG_COMMON_CLK_MT7622 is not set
-CONFIG_COMMON_CLK_MT7629=y
-CONFIG_COMMON_CLK_MT7629_ETHSYS=y
-CONFIG_COMMON_CLK_MT7629_HIFSYS=y
-# CONFIG_COMMON_CLK_MT7981 is not set
-# CONFIG_COMMON_CLK_MT7986 is not set
-# CONFIG_COMMON_CLK_MT7988 is not set
-# CONFIG_COMMON_CLK_MT8135 is not set
-# CONFIG_COMMON_CLK_MT8173 is not set
-CONFIG_COMMON_CLK_MT8516=y
-# CONFIG_COMMON_CLK_MT8516_AUDSYS is not set
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_SPECTRE=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRC16=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-CONFIG_DEBUG_MISC=y
-CONFIG_DEFAULT_HOSTNAME="(mt7629)"
-CONFIG_DIMLIB=y
-CONFIG_DMA_OPS=y
-CONFIG_DMA_REMAP=y
-CONFIG_DTC=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EINT_MTK=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MIGRATION=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GENERIC_VDSO_32=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GRO_CELLS=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDEN_BRANCH_PREDICTOR=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HAVE_SMP=y
-CONFIG_HOTPLUG_CPU=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_MTK=y
-CONFIG_HZ_FIXED=0
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_TIME_ACCOUNTING=y
-CONFIG_IRQ_WORK=y
-# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
-# CONFIG_LEDS_SMARTRG_LED is not set
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-# CONFIG_MACH_MT2701 is not set
-# CONFIG_MACH_MT6589 is not set
-# CONFIG_MACH_MT6592 is not set
-# CONFIG_MACH_MT7623 is not set
-CONFIG_MACH_MT7629=y
-# CONFIG_MACH_MT8127 is not set
-# CONFIG_MACH_MT8135 is not set
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEDIATEK_GE_PHY=y
-CONFIG_MEDIATEK_WATCHDOG=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGRATION=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MTD_NAND_CORE=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_ECC_MEDIATEK=y
-CONFIG_MTD_NAND_ECC_SW_HAMMING=y
-CONFIG_MTD_NAND_MTK_BMT=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_SPI_NAND=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_SPLIT_FIT_FW=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-# CONFIG_MTK_CMDQ is not set
-CONFIG_MTK_INFRACFG=y
-# CONFIG_MTK_PMIC_WRAP is not set
-CONFIG_MTK_SCPSYS=y
-CONFIG_MTK_SCPSYS_PM_DOMAINS=y
-CONFIG_MTK_TIMER=y
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NETFILTER=y
-CONFIG_NET_DEVLINK=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_MT7530=y
-CONFIG_NET_DSA_MT7530_MDIO=y
-# CONFIG_NET_DSA_MT7530_MMIO is not set
-CONFIG_NET_DSA_TAG_MTK=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_MEDIATEK_SOC=y
-CONFIG_NET_MEDIATEK_SOC_WED=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NET_VENDOR_MEDIATEK=y
-CONFIG_NLS=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=2
-CONFIG_NVMEM=y
-# CONFIG_NVMEM_MTK_EFUSE is not set
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_OUTER_CACHE=y
-CONFIG_OUTER_CACHE_SYNC=y
-CONFIG_PADATA=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_POOL_STATS=y
-CONFIG_PCI=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_MEDIATEK=y
-CONFIG_PCIE_PME=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PCS_MTK_LYNXI=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-CONFIG_PHY_MTK_TPHY=y
-# CONFIG_PHY_MTK_UFS is not set
-# CONFIG_PHY_MTK_XSPHY is not set
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_MT7629=y
-CONFIG_PINCTRL_MTK_MOORE=y
-CONFIG_PINCTRL_MTK_V2=y
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_PM_GENERIC_DOMAINS=y
-CONFIG_PM_GENERIC_DOMAINS_OF=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PWM=y
-CONFIG_PWM_MEDIATEK=y
-# CONFIG_PWM_MTK_DISP is not set
-CONFIG_PWM_SYSFS=y
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-# CONFIG_RTL8367S_GSW is not set
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_MT6577=y
-CONFIG_SERIAL_8250_NR_UARTS=3
-CONFIG_SERIAL_8250_RUNTIME_UARTS=3
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SG_POOL=y
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_MT65XX=y
-CONFIG_SPI_MTK_NOR=y
-CONFIG_SPI_MTK_SNFI=y
-CONFIG_SRCU=y
-CONFIG_STACKTRACE=y
-# CONFIG_SWAP is not set
-CONFIG_SWCONFIG=y
-CONFIG_SWPHY=y
-CONFIG_SWP_EMULATE=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UBIFS_FS=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNWINDER_ARM=y
-CONFIG_USB=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_MTK=y
-# CONFIG_USB_XHCI_PLATFORM is not set
-CONFIG_USE_OF=y
-# CONFIG_VFP is not set
-CONFIG_WATCHDOG_CORE=y
-# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
diff --git a/target/linux/mediatek/mt7629/config-6.1 b/target/linux/mediatek/mt7629/config-6.1
index ad79b5ba9ecc74..d8dc50a67ace4c 100644
--- a/target/linux/mediatek/mt7629/config-6.1
+++ b/target/linux/mediatek/mt7629/config-6.1
@@ -107,6 +107,7 @@ CONFIG_EDAC_ATOMIC_SCRUB=y
 CONFIG_EDAC_SUPPORT=y
 CONFIG_EINT_MTK=y
 CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+# CONFIG_FIT_PARTITION is not set
 CONFIG_FIXED_PHY=y
 CONFIG_FIX_EARLYCON_MEM=y
 CONFIG_FRAME_WARN=1024
diff --git a/target/linux/mediatek/patches-5.15/100-dts-update-mt7622-rfb1.patch b/target/linux/mediatek/patches-5.15/100-dts-update-mt7622-rfb1.patch
deleted file mode 100644
index 1f9e24a4d29e77..00000000000000
--- a/target/linux/mediatek/patches-5.15/100-dts-update-mt7622-rfb1.patch
+++ /dev/null
@@ -1,119 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-@@ -1,7 +1,6 @@
- /*
-- * Copyright (c) 2017 MediaTek Inc.
-- * Author: Ming Huang <ming.huang@mediatek.com>
-- *	   Sean Wang <sean.wang@mediatek.com>
-+ * Copyright (c) 2018 MediaTek Inc.
-+ * Author: Ryder Lee <ryder.lee@mediatek.com>
-  *
-  * SPDX-License-Identifier: (GPL-2.0 OR MIT)
-  */
-@@ -23,7 +22,7 @@
- 
- 	chosen {
- 		stdout-path = "serial0:115200n8";
--		bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
-+		bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
- 	};
- 
- 	cpus {
-@@ -40,23 +39,22 @@
- 
- 	gpio-keys {
- 		compatible = "gpio-keys";
--		poll-interval = <100>;
- 
- 		factory {
- 			label = "factory";
- 			linux,code = <BTN_0>;
--			gpios = <&pio 0 0>;
-+			gpios = <&pio 0 GPIO_ACTIVE_LOW>;
- 		};
- 
- 		wps {
- 			label = "wps";
- 			linux,code = <KEY_WPS_BUTTON>;
--			gpios = <&pio 102 0>;
-+			gpios = <&pio 102 GPIO_ACTIVE_LOW>;
- 		};
- 	};
- 
- 	memory@40000000 {
--		reg = <0 0x40000000 0 0x20000000>;
-+		reg = <0 0x40000000 0 0x40000000>;
- 	};
- 
- 	reg_1p8v: regulator-1p8v {
-@@ -132,22 +130,22 @@
- 
- 				port@0 {
- 					reg = <0>;
--					label = "lan0";
-+					label = "lan1";
- 				};
- 
- 				port@1 {
- 					reg = <1>;
--					label = "lan1";
-+					label = "lan2";
- 				};
- 
- 				port@2 {
- 					reg = <2>;
--					label = "lan2";
-+					label = "lan3";
- 				};
- 
- 				port@3 {
- 					reg = <3>;
--					label = "lan3";
-+					label = "lan4";
- 				};
- 
- 				port@4 {
-@@ -236,15 +234,28 @@
- 
- &pcie {
- 	pinctrl-names = "default";
--	pinctrl-0 = <&pcie0_pins>;
-+	pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
- 	status = "okay";
- 
- 	pcie@0,0 {
- 		status = "okay";
- 	};
-+
-+	pcie@1,0 {
-+		status = "okay";
-+	};
- };
- 
- &pio {
-+	/* Attention: GPIO 90 is used to switch between PCIe@1,0 and
-+	 * SATA functions. i.e. output-high: PCIe, output-low: SATA
-+	 */
-+	asm_sel {
-+		gpio-hog;
-+		gpios = <90 GPIO_ACTIVE_HIGH>;
-+		output-high;
-+	};
-+
- 	/* eMMC is shared pin with parallel NAND */
- 	emmc_pins_default: emmc-pins-default {
- 		mux {
-@@ -521,11 +532,11 @@
- };
- 
- &sata {
--	status = "okay";
-+	status = "disabled";
- };
- 
- &sata_phy {
--	status = "okay";
-+	status = "disabled";
- };
- 
- &spi0 {
diff --git a/target/linux/mediatek/patches-5.15/101-dts-update-mt7629-rfb.patch b/target/linux/mediatek/patches-5.15/101-dts-update-mt7629-rfb.patch
deleted file mode 100644
index 254b5f9eb72f00..00000000000000
--- a/target/linux/mediatek/patches-5.15/101-dts-update-mt7629-rfb.patch
+++ /dev/null
@@ -1,60 +0,0 @@
---- a/arch/arm/boot/dts/mt7629-rfb.dts
-+++ b/arch/arm/boot/dts/mt7629-rfb.dts
-@@ -18,6 +18,7 @@
- 
- 	chosen {
- 		stdout-path = "serial0:115200n8";
-+		bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8";
- 	};
- 
- 	gpio-keys {
-@@ -70,6 +71,10 @@
- 		compatible = "mediatek,eth-mac";
- 		reg = <0>;
- 		phy-mode = "2500base-x";
-+
-+		nvmem-cells = <&macaddr_factory_2a>;
-+		nvmem-cell-names = "mac-address";
-+
- 		fixed-link {
- 			speed = <2500>;
- 			full-duplex;
-@@ -82,6 +87,9 @@
- 		reg = <1>;
- 		phy-mode = "gmii";
- 		phy-handle = <&phy0>;
-+
-+		nvmem-cells = <&macaddr_factory_24>;
-+		nvmem-cell-names = "mac-address";
- 	};
- 
- 	mdio: mdio-bus {
-@@ -133,8 +141,9 @@
- 			};
- 
- 			partition@b0000 {
--				label = "kernel";
-+				label = "firmware";
- 				reg = <0xb0000 0xb50000>;
-+				compatible = "denx,fit";
- 			};
- 		};
- 	};
-@@ -272,3 +281,17 @@
- 	pinctrl-0 = <&watchdog_pins>;
- 	status = "okay";
- };
-+
-+&factory {
-+	compatible = "nvmem-cells";
-+	#address-cells = <1>;
-+	#size-cells = <1>;
-+
-+	macaddr_factory_24: macaddr@24 {
-+		reg = <0x24 0x6>;
-+	};
-+
-+	macaddr_factory_2a: macaddr@2a {
-+		reg = <0x2a 0x6>;
-+	};
-+};
diff --git a/target/linux/mediatek/patches-5.15/103-mt7623-enable-arch-timer.patch b/target/linux/mediatek/patches-5.15/103-mt7623-enable-arch-timer.patch
deleted file mode 100644
index 04df7b927b1cb0..00000000000000
--- a/target/linux/mediatek/patches-5.15/103-mt7623-enable-arch-timer.patch
+++ /dev/null
@@ -1,20 +0,0 @@
-From d6a596012150960f0f3a214d31bbac4b607dbd1e Mon Sep 17 00:00:00 2001
-From: Chuanhong Guo <gch981213@gmail.com>
-Date: Fri, 29 Apr 2022 10:40:56 +0800
-Subject: [PATCH] arm: mediatek: select arch timer for mt7623
-
-Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
----
- arch/arm/mach-mediatek/Kconfig | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/arm/mach-mediatek/Kconfig
-+++ b/arch/arm/mach-mediatek/Kconfig
-@@ -26,6 +26,7 @@ config MACH_MT6592
- config MACH_MT7623
- 	bool "MediaTek MT7623 SoCs support"
- 	default ARCH_MEDIATEK
-+	select HAVE_ARM_ARCH_TIMER
- 
- config MACH_MT7629
- 	bool "MediaTek MT7629 SoCs support"
diff --git a/target/linux/mediatek/patches-5.15/104-mt7622-add-snor-irq.patch b/target/linux/mediatek/patches-5.15/104-mt7622-add-snor-irq.patch
deleted file mode 100644
index 79b051147a34ab..00000000000000
--- a/target/linux/mediatek/patches-5.15/104-mt7622-add-snor-irq.patch
+++ /dev/null
@@ -1,10 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -559,6 +559,7 @@
- 		compatible = "mediatek,mt7622-nor",
- 			     "mediatek,mt8173-nor";
- 		reg = <0 0x11014000 0 0xe0>;
-+		interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>;
- 		clocks = <&pericfg CLK_PERI_FLASH_PD>,
- 			 <&topckgen CLK_TOP_FLASH_SEL>;
- 		clock-names = "spi", "sf";
diff --git a/target/linux/mediatek/patches-5.15/105-dts-mt7622-enable-pstore.patch b/target/linux/mediatek/patches-5.15/105-dts-mt7622-enable-pstore.patch
deleted file mode 100644
index da42c07728a47d..00000000000000
--- a/target/linux/mediatek/patches-5.15/105-dts-mt7622-enable-pstore.patch
+++ /dev/null
@@ -1,25 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -111,7 +111,7 @@
- 	};
- 
- 	psci {
--		compatible  = "arm,psci-0.2";
-+		compatible  = "arm,psci-1.0";
- 		method      = "smc";
- 	};
- 
-@@ -127,6 +127,13 @@
- 		#size-cells = <2>;
- 		ranges;
- 
-+		/* 64 KiB reserved for ramoops/pstore */
-+		ramoops@42ff0000 {
-+			compatible = "ramoops";
-+			reg = <0 0x42ff0000 0 0x10000>;
-+			record-size = <0x1000>;
-+		};
-+
- 		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
- 		secmon_reserved: secmon@43000000 {
- 			reg = <0 0x43000000 0 0x30000>;
diff --git a/target/linux/mediatek/patches-5.15/110-dts-fix-bpi2-console.patch b/target/linux/mediatek/patches-5.15/110-dts-fix-bpi2-console.patch
deleted file mode 100644
index 8dc53d2985fac5..00000000000000
--- a/target/linux/mediatek/patches-5.15/110-dts-fix-bpi2-console.patch
+++ /dev/null
@@ -1,10 +0,0 @@
---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-@@ -19,6 +19,7 @@
- 
- 	chosen {
- 		stdout-path = "serial2:115200n8";
-+		bootargs = "console=ttyS2,115200n8 console=tty1";
- 	};
- 
- 	connector {
diff --git a/target/linux/mediatek/patches-5.15/111-dts-fix-bpi64-console.patch b/target/linux/mediatek/patches-5.15/111-dts-fix-bpi64-console.patch
deleted file mode 100644
index 07a2eae2454039..00000000000000
--- a/target/linux/mediatek/patches-5.15/111-dts-fix-bpi64-console.patch
+++ /dev/null
@@ -1,11 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -22,7 +22,7 @@
- 
- 	chosen {
- 		stdout-path = "serial0:115200n8";
--		bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
-+		bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
- 	};
- 
- 	cpus {
diff --git a/target/linux/mediatek/patches-5.15/112-dts-fix-bpi64-lan-names.patch b/target/linux/mediatek/patches-5.15/112-dts-fix-bpi64-lan-names.patch
deleted file mode 100644
index 6ce85efde9815e..00000000000000
--- a/target/linux/mediatek/patches-5.15/112-dts-fix-bpi64-lan-names.patch
+++ /dev/null
@@ -1,37 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -18,6 +18,7 @@
- 
- 	aliases {
- 		serial0 = &uart0;
-+		ethernet0 = &gmac0;
- 	};
- 
- 	chosen {
-@@ -160,22 +161,22 @@
- 
- 				port@1 {
- 					reg = <1>;
--					label = "lan0";
-+					label = "lan1";
- 				};
- 
- 				port@2 {
- 					reg = <2>;
--					label = "lan1";
-+					label = "lan2";
- 				};
- 
- 				port@3 {
- 					reg = <3>;
--					label = "lan2";
-+					label = "lan3";
- 				};
- 
- 				port@4 {
- 					reg = <4>;
--					label = "lan3";
-+					label = "lan4";
- 				};
- 
- 				port@6 {
diff --git a/target/linux/mediatek/patches-5.15/113-dts-fix-bpi64-leds-and-buttons.patch b/target/linux/mediatek/patches-5.15/113-dts-fix-bpi64-leds-and-buttons.patch
deleted file mode 100644
index f728b965642c7c..00000000000000
--- a/target/linux/mediatek/patches-5.15/113-dts-fix-bpi64-leds-and-buttons.patch
+++ /dev/null
@@ -1,56 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -19,6 +19,10 @@
- 	aliases {
- 		serial0 = &uart0;
- 		ethernet0 = &gmac0;
-+		led-boot = &led_system_green;
-+		led-failsafe = &led_system_blue;
-+		led-running = &led_system_green;
-+		led-upgrade = &led_system_blue;
- 	};
- 
- 	chosen {
-@@ -42,8 +46,8 @@
- 		compatible = "gpio-keys";
- 
- 		factory {
--			label = "factory";
--			linux,code = <BTN_0>;
-+			label = "reset";
-+			linux,code = <KEY_RESTART>;
- 			gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
- 		};
- 
-@@ -57,17 +61,25 @@
- 	leds {
- 		compatible = "gpio-leds";
- 
--		green {
--			label = "bpi-r64:pio:green";
--			gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
-+		led_system_blue: blue {
-+			label = "bpi-r64:pio:blue";
-+			gpios = <&pio 85 GPIO_ACTIVE_HIGH>;
- 			default-state = "off";
- 		};
- 
--		red {
--			label = "bpi-r64:pio:red";
--			gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
-+		led_system_green: green {
-+			label = "bpi-r64:pio:green";
-+			gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
- 			default-state = "off";
- 		};
-+
-+/*
-+ *		red {
-+ *			label = "bpi-r64:pio:red";
-+ *			gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
-+ *			default-state = "off";
-+ *		};
-+ */
- 	};
- 
- 	memory@40000000 {
diff --git a/target/linux/mediatek/patches-5.15/114-dts-bpi64-disable-rtc.patch b/target/linux/mediatek/patches-5.15/114-dts-bpi64-disable-rtc.patch
deleted file mode 100644
index 1f41142aacfb0c..00000000000000
--- a/target/linux/mediatek/patches-5.15/114-dts-bpi64-disable-rtc.patch
+++ /dev/null
@@ -1,21 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -564,12 +564,16 @@
- 	status = "okay";
- };
- 
-+&rtc {
-+	status = "disabled";
-+};
-+
- &sata {
--	status = "disable";
-+	status = "disabled";
- };
- 
- &sata_phy {
--	status = "disable";
-+	status = "disabled";
- };
- 
- &spi0 {
diff --git a/target/linux/mediatek/patches-5.15/115-dts-bpi64-add-snand-support.patch b/target/linux/mediatek/patches-5.15/115-dts-bpi64-add-snand-support.patch
deleted file mode 100644
index 34539a5d10199e..00000000000000
--- a/target/linux/mediatek/patches-5.15/115-dts-bpi64-add-snand-support.patch
+++ /dev/null
@@ -1,50 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -259,14 +259,42 @@
- 	status = "disabled";
- };
- 
--&nor_flash {
--	pinctrl-names = "default";
--	pinctrl-0 = <&spi_nor_pins>;
--	status = "disabled";
-+&bch {
-+	status = "okay";
-+};
- 
-+&snfi {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&serial_nand_pins>;
-+	status = "okay";
- 	flash@0 {
--		compatible = "jedec,spi-nor";
-+		compatible = "spi-nand";
- 		reg = <0>;
-+		spi-tx-bus-width = <4>;
-+		spi-rx-bus-width = <4>;
-+		nand-ecc-engine = <&snfi>;
-+		partitions {
-+			compatible = "fixed-partitions";
-+			#address-cells = <1>;
-+			#size-cells = <1>;
-+
-+			partition@0 {
-+				label = "bl2";
-+				reg = <0x0 0x80000>;
-+				read-only;
-+			};
-+
-+			partition@80000 {
-+				label = "fip";
-+				reg = <0x80000 0x200000>;
-+				read-only;
-+			};
-+
-+			partition@280000 {
-+				label = "ubi";
-+				reg = <0x280000 0x7d80000>;
-+			};
-+		};
- 	};
- };
- 
diff --git a/target/linux/mediatek/patches-5.15/120-01-v5.18-mtd-nand-ecc-Add-infrastructure-to-support-hardware-.patch b/target/linux/mediatek/patches-5.15/120-01-v5.18-mtd-nand-ecc-Add-infrastructure-to-support-hardware-.patch
deleted file mode 100644
index 7fb62e7403c741..00000000000000
--- a/target/linux/mediatek/patches-5.15/120-01-v5.18-mtd-nand-ecc-Add-infrastructure-to-support-hardware-.patch
+++ /dev/null
@@ -1,214 +0,0 @@
-From ad4944aa0b02cb043afe20bc2a018c161e65c992 Mon Sep 17 00:00:00 2001
-From: Miquel Raynal <miquel.raynal@bootlin.com>
-Date: Thu, 16 Dec 2021 12:16:38 +0100
-Subject: [PATCH 01/15] mtd: nand: ecc: Add infrastructure to support hardware
- engines
-
-Add the necessary helpers to register/unregister hardware ECC engines
-that will be called from ECC engine drivers.
-
-Also add helpers to get the right engine from the user
-perspective. Keep a reference of the in use ECC engine in order to
-prevent modules to be unloaded. Put the reference when the engine gets
-retired.
-
-A static list of hardware (only) ECC engines is setup to keep track of
-the registered engines.
-
-Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
-Link: https://lore.kernel.org/linux-mtd/20211216111654.238086-13-miquel.raynal@bootlin.com
-(cherry picked from commit 96489c1c0b53131b0e1ec33e2060538379ad6152)
----
- drivers/mtd/nand/core.c  | 10 +++--
- drivers/mtd/nand/ecc.c   | 88 ++++++++++++++++++++++++++++++++++++++++
- include/linux/mtd/nand.h | 28 +++++++++++++
- 3 files changed, 123 insertions(+), 3 deletions(-)
-
---- a/drivers/mtd/nand/core.c
-+++ b/drivers/mtd/nand/core.c
-@@ -232,7 +232,9 @@ static int nanddev_get_ecc_engine(struct
- 		nand->ecc.engine = nand_ecc_get_on_die_hw_engine(nand);
- 		break;
- 	case NAND_ECC_ENGINE_TYPE_ON_HOST:
--		pr_err("On-host hardware ECC engines not supported yet\n");
-+		nand->ecc.engine = nand_ecc_get_on_host_hw_engine(nand);
-+		if (PTR_ERR(nand->ecc.engine) == -EPROBE_DEFER)
-+			return -EPROBE_DEFER;
- 		break;
- 	default:
- 		pr_err("Missing ECC engine type\n");
-@@ -252,7 +254,7 @@ static int nanddev_put_ecc_engine(struct
- {
- 	switch (nand->ecc.ctx.conf.engine_type) {
- 	case NAND_ECC_ENGINE_TYPE_ON_HOST:
--		pr_err("On-host hardware ECC engines not supported yet\n");
-+		nand_ecc_put_on_host_hw_engine(nand);
- 		break;
- 	case NAND_ECC_ENGINE_TYPE_NONE:
- 	case NAND_ECC_ENGINE_TYPE_SOFT:
-@@ -297,7 +299,9 @@ int nanddev_ecc_engine_init(struct nand_
- 	/* Look for the ECC engine to use */
- 	ret = nanddev_get_ecc_engine(nand);
- 	if (ret) {
--		pr_err("No ECC engine found\n");
-+		if (ret != -EPROBE_DEFER)
-+			pr_err("No ECC engine found\n");
-+
- 		return ret;
- 	}
- 
---- a/drivers/mtd/nand/ecc.c
-+++ b/drivers/mtd/nand/ecc.c
-@@ -96,6 +96,12 @@
- #include <linux/module.h>
- #include <linux/mtd/nand.h>
- #include <linux/slab.h>
-+#include <linux/of.h>
-+#include <linux/of_device.h>
-+#include <linux/of_platform.h>
-+
-+static LIST_HEAD(on_host_hw_engines);
-+static DEFINE_MUTEX(on_host_hw_engines_mutex);
- 
- /**
-  * nand_ecc_init_ctx - Init the ECC engine context
-@@ -611,6 +617,88 @@ struct nand_ecc_engine *nand_ecc_get_on_
- }
- EXPORT_SYMBOL(nand_ecc_get_on_die_hw_engine);
- 
-+int nand_ecc_register_on_host_hw_engine(struct nand_ecc_engine *engine)
-+{
-+	struct nand_ecc_engine *item;
-+
-+	if (!engine)
-+		return -EINVAL;
-+
-+	/* Prevent multiple registrations of one engine */
-+	list_for_each_entry(item, &on_host_hw_engines, node)
-+		if (item == engine)
-+			return 0;
-+
-+	mutex_lock(&on_host_hw_engines_mutex);
-+	list_add_tail(&engine->node, &on_host_hw_engines);
-+	mutex_unlock(&on_host_hw_engines_mutex);
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(nand_ecc_register_on_host_hw_engine);
-+
-+int nand_ecc_unregister_on_host_hw_engine(struct nand_ecc_engine *engine)
-+{
-+	if (!engine)
-+		return -EINVAL;
-+
-+	mutex_lock(&on_host_hw_engines_mutex);
-+	list_del(&engine->node);
-+	mutex_unlock(&on_host_hw_engines_mutex);
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(nand_ecc_unregister_on_host_hw_engine);
-+
-+static struct nand_ecc_engine *nand_ecc_match_on_host_hw_engine(struct device *dev)
-+{
-+	struct nand_ecc_engine *item;
-+
-+	list_for_each_entry(item, &on_host_hw_engines, node)
-+		if (item->dev == dev)
-+			return item;
-+
-+	return NULL;
-+}
-+
-+struct nand_ecc_engine *nand_ecc_get_on_host_hw_engine(struct nand_device *nand)
-+{
-+	struct nand_ecc_engine *engine = NULL;
-+	struct device *dev = &nand->mtd.dev;
-+	struct platform_device *pdev;
-+	struct device_node *np;
-+
-+	if (list_empty(&on_host_hw_engines))
-+		return NULL;
-+
-+	/* Check for an explicit nand-ecc-engine property */
-+	np = of_parse_phandle(dev->of_node, "nand-ecc-engine", 0);
-+	if (np) {
-+		pdev = of_find_device_by_node(np);
-+		if (!pdev)
-+			return ERR_PTR(-EPROBE_DEFER);
-+
-+		engine = nand_ecc_match_on_host_hw_engine(&pdev->dev);
-+		platform_device_put(pdev);
-+		of_node_put(np);
-+
-+		if (!engine)
-+			return ERR_PTR(-EPROBE_DEFER);
-+	}
-+
-+	if (engine)
-+		get_device(engine->dev);
-+
-+	return engine;
-+}
-+EXPORT_SYMBOL(nand_ecc_get_on_host_hw_engine);
-+
-+void nand_ecc_put_on_host_hw_engine(struct nand_device *nand)
-+{
-+	put_device(nand->ecc.engine->dev);
-+}
-+EXPORT_SYMBOL(nand_ecc_put_on_host_hw_engine);
-+
- MODULE_LICENSE("GPL");
- MODULE_AUTHOR("Miquel Raynal <miquel.raynal@bootlin.com>");
- MODULE_DESCRIPTION("Generic ECC engine");
---- a/include/linux/mtd/nand.h
-+++ b/include/linux/mtd/nand.h
-@@ -264,11 +264,35 @@ struct nand_ecc_engine_ops {
- };
- 
- /**
-+ * enum nand_ecc_engine_integration - How the NAND ECC engine is integrated
-+ * @NAND_ECC_ENGINE_INTEGRATION_INVALID: Invalid value
-+ * @NAND_ECC_ENGINE_INTEGRATION_PIPELINED: Pipelined engine, performs on-the-fly
-+ *                                         correction, does not need to copy
-+ *                                         data around
-+ * @NAND_ECC_ENGINE_INTEGRATION_EXTERNAL: External engine, needs to bring the
-+ *                                        data into its own area before use
-+ */
-+enum nand_ecc_engine_integration {
-+	NAND_ECC_ENGINE_INTEGRATION_INVALID,
-+	NAND_ECC_ENGINE_INTEGRATION_PIPELINED,
-+	NAND_ECC_ENGINE_INTEGRATION_EXTERNAL,
-+};
-+
-+/**
-  * struct nand_ecc_engine - ECC engine abstraction for NAND devices
-+ * @dev: Host device
-+ * @node: Private field for registration time
-  * @ops: ECC engine operations
-+ * @integration: How the engine is integrated with the host
-+ *               (only relevant on %NAND_ECC_ENGINE_TYPE_ON_HOST engines)
-+ * @priv: Private data
-  */
- struct nand_ecc_engine {
-+	struct device *dev;
-+	struct list_head node;
- 	struct nand_ecc_engine_ops *ops;
-+	enum nand_ecc_engine_integration integration;
-+	void *priv;
- };
- 
- void of_get_nand_ecc_user_config(struct nand_device *nand);
-@@ -279,8 +303,12 @@ int nand_ecc_prepare_io_req(struct nand_
- int nand_ecc_finish_io_req(struct nand_device *nand,
- 			   struct nand_page_io_req *req);
- bool nand_ecc_is_strong_enough(struct nand_device *nand);
-+int nand_ecc_register_on_host_hw_engine(struct nand_ecc_engine *engine);
-+int nand_ecc_unregister_on_host_hw_engine(struct nand_ecc_engine *engine);
- struct nand_ecc_engine *nand_ecc_get_sw_engine(struct nand_device *nand);
- struct nand_ecc_engine *nand_ecc_get_on_die_hw_engine(struct nand_device *nand);
-+struct nand_ecc_engine *nand_ecc_get_on_host_hw_engine(struct nand_device *nand);
-+void nand_ecc_put_on_host_hw_engine(struct nand_device *nand);
- 
- #if IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING)
- struct nand_ecc_engine *nand_ecc_sw_hamming_get_engine(void);
diff --git a/target/linux/mediatek/patches-5.15/120-02-v5.18-mtd-nand-Add-a-new-helper-to-retrieve-the-ECC-contex.patch b/target/linux/mediatek/patches-5.15/120-02-v5.18-mtd-nand-Add-a-new-helper-to-retrieve-the-ECC-contex.patch
deleted file mode 100644
index 61a39ee0e59029..00000000000000
--- a/target/linux/mediatek/patches-5.15/120-02-v5.18-mtd-nand-Add-a-new-helper-to-retrieve-the-ECC-contex.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From 840b2f8dd2d0579e517140e1f9bbc482eaf4ed07 Mon Sep 17 00:00:00 2001
-From: Miquel Raynal <miquel.raynal@bootlin.com>
-Date: Thu, 16 Dec 2021 12:16:39 +0100
-Subject: [PATCH 02/15] mtd: nand: Add a new helper to retrieve the ECC context
-
-Introduce nand_to_ecc_ctx() which will allow to easily jump to the
-private pointer of an ECC context given a NAND device. This is very
-handy, from the prepare or finish ECC hook, to get the internal context
-out of the NAND device object.
-
-Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
-Link: https://lore.kernel.org/linux-mtd/20211216111654.238086-14-miquel.raynal@bootlin.com
-(cherry picked from commit cda32a618debd3fad8e42757b198719ae180f8f4)
----
- include/linux/mtd/nand.h | 5 +++++
- 1 file changed, 5 insertions(+)
-
---- a/include/linux/mtd/nand.h
-+++ b/include/linux/mtd/nand.h
-@@ -990,6 +990,11 @@ int nanddev_markbad(struct nand_device *
- int nanddev_ecc_engine_init(struct nand_device *nand);
- void nanddev_ecc_engine_cleanup(struct nand_device *nand);
- 
-+static inline void *nand_to_ecc_ctx(struct nand_device *nand)
-+{
-+	return nand->ecc.ctx.priv;
-+}
-+
- /* BBT related functions */
- enum nand_bbt_block_status {
- 	NAND_BBT_BLOCK_STATUS_UNKNOWN,
diff --git a/target/linux/mediatek/patches-5.15/120-03-v5.18-mtd-nand-ecc-Provide-a-helper-to-retrieve-a-pileline.patch b/target/linux/mediatek/patches-5.15/120-03-v5.18-mtd-nand-ecc-Provide-a-helper-to-retrieve-a-pileline.patch
deleted file mode 100644
index 29b62880abd316..00000000000000
--- a/target/linux/mediatek/patches-5.15/120-03-v5.18-mtd-nand-ecc-Provide-a-helper-to-retrieve-a-pileline.patch
+++ /dev/null
@@ -1,73 +0,0 @@
-From 784866bc4f9f25e0494b77750f95af2a2619e498 Mon Sep 17 00:00:00 2001
-From: Miquel Raynal <miquel.raynal@bootlin.com>
-Date: Thu, 16 Dec 2021 12:16:41 +0100
-Subject: [PATCH 03/15] mtd: nand: ecc: Provide a helper to retrieve a
- pilelined engine device
-
-In a pipelined engine situation, we might either have the host which
-internally has support for error correction, or have it using an
-external hardware block for this purpose. In the former case, the host
-is also the ECC engine. In the latter case, it is not. In order to get
-the right pointers on the right devices (for example: in order to devm_*
-allocate variables), let's introduce this helper which can safely be
-called by pipelined ECC engines in order to retrieve the right device
-structure.
-
-Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
-Link: https://lore.kernel.org/linux-mtd/20211216111654.238086-16-miquel.raynal@bootlin.com
-(cherry picked from commit 5145abeb0649acf810a32e63bd762e617a9b3309)
----
- drivers/mtd/nand/ecc.c   | 31 +++++++++++++++++++++++++++++++
- include/linux/mtd/nand.h |  1 +
- 2 files changed, 32 insertions(+)
-
---- a/drivers/mtd/nand/ecc.c
-+++ b/drivers/mtd/nand/ecc.c
-@@ -699,6 +699,37 @@ void nand_ecc_put_on_host_hw_engine(stru
- }
- EXPORT_SYMBOL(nand_ecc_put_on_host_hw_engine);
- 
-+/*
-+ * In the case of a pipelined engine, the device registering the ECC
-+ * engine is not necessarily the ECC engine itself but may be a host controller.
-+ * It is then useful to provide a helper to retrieve the right device object
-+ * which actually represents the ECC engine.
-+ */
-+struct device *nand_ecc_get_engine_dev(struct device *host)
-+{
-+	struct platform_device *ecc_pdev;
-+	struct device_node *np;
-+
-+	/*
-+	 * If the device node contains this property, it means we need to follow
-+	 * it in order to get the right ECC engine device we are looking for.
-+	 */
-+	np = of_parse_phandle(host->of_node, "nand-ecc-engine", 0);
-+	if (!np)
-+		return host;
-+
-+	ecc_pdev = of_find_device_by_node(np);
-+	if (!ecc_pdev) {
-+		of_node_put(np);
-+		return NULL;
-+	}
-+
-+	platform_device_put(ecc_pdev);
-+	of_node_put(np);
-+
-+	return &ecc_pdev->dev;
-+}
-+
- MODULE_LICENSE("GPL");
- MODULE_AUTHOR("Miquel Raynal <miquel.raynal@bootlin.com>");
- MODULE_DESCRIPTION("Generic ECC engine");
---- a/include/linux/mtd/nand.h
-+++ b/include/linux/mtd/nand.h
-@@ -309,6 +309,7 @@ struct nand_ecc_engine *nand_ecc_get_sw_
- struct nand_ecc_engine *nand_ecc_get_on_die_hw_engine(struct nand_device *nand);
- struct nand_ecc_engine *nand_ecc_get_on_host_hw_engine(struct nand_device *nand);
- void nand_ecc_put_on_host_hw_engine(struct nand_device *nand);
-+struct device *nand_ecc_get_engine_dev(struct device *host);
- 
- #if IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING)
- struct nand_ecc_engine *nand_ecc_sw_hamming_get_engine(void);
diff --git a/target/linux/mediatek/patches-5.15/120-04-v5.18-spi-spi-mem-Introduce-a-capability-structure.patch b/target/linux/mediatek/patches-5.15/120-04-v5.18-spi-spi-mem-Introduce-a-capability-structure.patch
deleted file mode 100644
index 1e7f572dd6648f..00000000000000
--- a/target/linux/mediatek/patches-5.15/120-04-v5.18-spi-spi-mem-Introduce-a-capability-structure.patch
+++ /dev/null
@@ -1,71 +0,0 @@
-From 3e45577e70cbf8fdc5c13033114989794a3797d5 Mon Sep 17 00:00:00 2001
-From: Miquel Raynal <miquel.raynal@bootlin.com>
-Date: Thu, 27 Jan 2022 10:17:56 +0100
-Subject: [PATCH 04/15] spi: spi-mem: Introduce a capability structure
-
-Create a spi_controller_mem_caps structure and put it within the
-spi_controller structure close to the spi_controller_mem_ops
-strucure. So far the only field in this structure is the support for dtr
-operations, but soon we will add another parameter.
-
-Also create a helper to parse the capabilities and check if the
-requested capability has been set or not.
-
-Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
-Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
-Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
-Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
-Reviewed-by: Mark Brown <broonie@kernel.org>
-Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-2-miquel.raynal@bootlin.com
-(cherry picked from commit 4a3cc7fb6e63bcfdedec25364738f1493345bd20)
----
- include/linux/spi/spi-mem.h | 11 +++++++++++
- include/linux/spi/spi.h     |  3 +++
- 2 files changed, 14 insertions(+)
-
---- a/include/linux/spi/spi-mem.h
-+++ b/include/linux/spi/spi-mem.h
-@@ -286,6 +286,17 @@ struct spi_controller_mem_ops {
- };
- 
- /**
-+ * struct spi_controller_mem_caps - SPI memory controller capabilities
-+ * @dtr: Supports DTR operations
-+ */
-+struct spi_controller_mem_caps {
-+	bool dtr;
-+};
-+
-+#define spi_mem_controller_is_capable(ctlr, cap)	\
-+	((ctlr)->mem_caps && (ctlr)->mem_caps->cap)
-+
-+/**
-  * struct spi_mem_driver - SPI memory driver
-  * @spidrv: inherit from a SPI driver
-  * @probe: probe a SPI memory. Usually where detection/initialization takes
---- a/include/linux/spi/spi.h
-+++ b/include/linux/spi/spi.h
-@@ -23,6 +23,7 @@ struct software_node;
- struct spi_controller;
- struct spi_transfer;
- struct spi_controller_mem_ops;
-+struct spi_controller_mem_caps;
- 
- /*
-  * INTERFACES between SPI master-side drivers and SPI slave protocol handlers,
-@@ -419,6 +420,7 @@ extern struct spi_device *spi_new_ancill
-  * @mem_ops: optimized/dedicated operations for interactions with SPI memory.
-  *	     This field is optional and should only be implemented if the
-  *	     controller has native support for memory like operations.
-+ * @mem_caps: controller capabilities for the handling of memory operations.
-  * @unprepare_message: undo any work done by prepare_message().
-  * @slave_abort: abort the ongoing transfer request on an SPI slave controller
-  * @cs_gpios: LEGACY: array of GPIO descs to use as chip select lines; one per
-@@ -643,6 +645,7 @@ struct spi_controller {
- 
- 	/* Optimized handlers for SPI memory-like operations. */
- 	const struct spi_controller_mem_ops *mem_ops;
-+	const struct spi_controller_mem_caps *mem_caps;
- 
- 	/* gpio chip select */
- 	int			*cs_gpios;
diff --git a/target/linux/mediatek/patches-5.15/120-05-v5.18-spi-spi-mem-Check-the-controller-extra-capabilities.patch b/target/linux/mediatek/patches-5.15/120-05-v5.18-spi-spi-mem-Check-the-controller-extra-capabilities.patch
deleted file mode 100644
index 9f01fdb83532ae..00000000000000
--- a/target/linux/mediatek/patches-5.15/120-05-v5.18-spi-spi-mem-Check-the-controller-extra-capabilities.patch
+++ /dev/null
@@ -1,51 +0,0 @@
-From c9cae7e1e5c87d0aa76b7bededa5191a0c8cf25a Mon Sep 17 00:00:00 2001
-From: Miquel Raynal <miquel.raynal@bootlin.com>
-Date: Thu, 27 Jan 2022 10:17:57 +0100
-Subject: [PATCH 05/15] spi: spi-mem: Check the controller extra capabilities
-
-Controllers can now provide a spi-mem capabilities structure. Let's make
-use of it in spi_mem_controller_default_supports_op(). As we want to
-check for DTR operations as well as normal operations in a single
-helper, let's pull the necessary checks from spi_mem_dtr_supports_op()
-for now.
-
-However, because no controller provide these extra capabilities, this
-change has no effect so far.
-
-Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
-Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
-Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
-Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
-Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-3-miquel.raynal@bootlin.com
-(cherry picked from commit cb7e96ee81edaa48c67d84c14df2cbe464391c37)
----
- drivers/spi/spi-mem.c | 17 +++++++++++++----
- 1 file changed, 13 insertions(+), 4 deletions(-)
-
---- a/drivers/spi/spi-mem.c
-+++ b/drivers/spi/spi-mem.c
-@@ -173,11 +173,20 @@ EXPORT_SYMBOL_GPL(spi_mem_dtr_supports_o
- bool spi_mem_default_supports_op(struct spi_mem *mem,
- 				 const struct spi_mem_op *op)
- {
--	if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr)
--		return false;
-+	struct spi_controller *ctlr = mem->spi->controller;
-+	bool op_is_dtr =
-+		op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr;
- 
--	if (op->cmd.nbytes != 1)
--		return false;
-+	if (op_is_dtr) {
-+		if (!spi_mem_controller_is_capable(ctlr, dtr))
-+			return false;
-+
-+		if (op->cmd.nbytes != 2)
-+			return false;
-+	} else {
-+		if (op->cmd.nbytes != 1)
-+			return false;
-+	}
- 
- 	return spi_mem_check_buswidth(mem, op);
- }
diff --git a/target/linux/mediatek/patches-5.15/120-06-v5.18-spi-spi-mem-Kill-the-spi_mem_dtr_supports_op-helper.patch b/target/linux/mediatek/patches-5.15/120-06-v5.18-spi-spi-mem-Kill-the-spi_mem_dtr_supports_op-helper.patch
deleted file mode 100644
index c313a455b607dd..00000000000000
--- a/target/linux/mediatek/patches-5.15/120-06-v5.18-spi-spi-mem-Kill-the-spi_mem_dtr_supports_op-helper.patch
+++ /dev/null
@@ -1,111 +0,0 @@
-From 2e5fba82e4aeb72d71230eef2541881615aaf7cf Mon Sep 17 00:00:00 2001
-From: Miquel Raynal <miquel.raynal@bootlin.com>
-Date: Thu, 27 Jan 2022 10:18:00 +0100
-Subject: [PATCH 06/15] spi: spi-mem: Kill the spi_mem_dtr_supports_op() helper
-
-Now that spi_mem_default_supports_op() has access to the static
-controller capabilities (relating to memory operations), and now that
-these capabilities have been filled by the relevant controllers, there
-is no need for a specific helper checking only DTR operations, so let's
-just kill spi_mem_dtr_supports_op() and simply use
-spi_mem_default_supports_op() instead.
-
-Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
-Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
-Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
-Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
-Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-6-miquel.raynal@bootlin.com
-(cherry picked from commit 9a15efc5d5e6b5beaed0883e5bdcd0b1384c1b20)
----
- drivers/spi/spi-cadence-quadspi.c |  5 +----
- drivers/spi/spi-mem.c             | 10 ----------
- drivers/spi/spi-mxic.c            | 10 +---------
- include/linux/spi/spi-mem.h       | 11 -----------
- 4 files changed, 2 insertions(+), 34 deletions(-)
-
---- a/drivers/spi/spi-cadence-quadspi.c
-+++ b/drivers/spi/spi-cadence-quadspi.c
-@@ -1249,10 +1249,7 @@ static bool cqspi_supports_mem_op(struct
- 		return false;
- 	}
- 
--	if (all_true)
--		return spi_mem_dtr_supports_op(mem, op);
--	else
--		return spi_mem_default_supports_op(mem, op);
-+	return spi_mem_default_supports_op(mem, op);
- }
- 
- static int cqspi_of_get_flash_pdata(struct platform_device *pdev,
---- a/drivers/spi/spi-mem.c
-+++ b/drivers/spi/spi-mem.c
-@@ -160,16 +160,6 @@ static bool spi_mem_check_buswidth(struc
- 	return true;
- }
- 
--bool spi_mem_dtr_supports_op(struct spi_mem *mem,
--			     const struct spi_mem_op *op)
--{
--	if (op->cmd.nbytes != 2)
--		return false;
--
--	return spi_mem_check_buswidth(mem, op);
--}
--EXPORT_SYMBOL_GPL(spi_mem_dtr_supports_op);
--
- bool spi_mem_default_supports_op(struct spi_mem *mem,
- 				 const struct spi_mem_op *op)
- {
---- a/drivers/spi/spi-mxic.c
-+++ b/drivers/spi/spi-mxic.c
-@@ -331,8 +331,6 @@ static int mxic_spi_data_xfer(struct mxi
- static bool mxic_spi_mem_supports_op(struct spi_mem *mem,
- 				     const struct spi_mem_op *op)
- {
--	bool all_false;
--
- 	if (op->data.buswidth > 8 || op->addr.buswidth > 8 ||
- 	    op->dummy.buswidth > 8 || op->cmd.buswidth > 8)
- 		return false;
-@@ -344,13 +342,7 @@ static bool mxic_spi_mem_supports_op(str
- 	if (op->addr.nbytes > 7)
- 		return false;
- 
--	all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr &&
--		    !op->data.dtr;
--
--	if (all_false)
--		return spi_mem_default_supports_op(mem, op);
--	else
--		return spi_mem_dtr_supports_op(mem, op);
-+	return spi_mem_default_supports_op(mem, op);
- }
- 
- static int mxic_spi_mem_exec_op(struct spi_mem *mem,
---- a/include/linux/spi/spi-mem.h
-+++ b/include/linux/spi/spi-mem.h
-@@ -330,10 +330,6 @@ void spi_controller_dma_unmap_mem_op_dat
- 
- bool spi_mem_default_supports_op(struct spi_mem *mem,
- 				 const struct spi_mem_op *op);
--
--bool spi_mem_dtr_supports_op(struct spi_mem *mem,
--			     const struct spi_mem_op *op);
--
- #else
- static inline int
- spi_controller_dma_map_mem_op_data(struct spi_controller *ctlr,
-@@ -356,13 +352,6 @@ bool spi_mem_default_supports_op(struct
- {
- 	return false;
- }
--
--static inline
--bool spi_mem_dtr_supports_op(struct spi_mem *mem,
--			     const struct spi_mem_op *op)
--{
--	return false;
--}
- #endif /* CONFIG_SPI_MEM */
- 
- int spi_mem_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op);
diff --git a/target/linux/mediatek/patches-5.15/120-07-v5.18-spi-spi-mem-Add-an-ecc-parameter-to-the-spi_mem_op-s.patch b/target/linux/mediatek/patches-5.15/120-07-v5.18-spi-spi-mem-Add-an-ecc-parameter-to-the-spi_mem_op-s.patch
deleted file mode 100644
index 6d7e47650b2da1..00000000000000
--- a/target/linux/mediatek/patches-5.15/120-07-v5.18-spi-spi-mem-Add-an-ecc-parameter-to-the-spi_mem_op-s.patch
+++ /dev/null
@@ -1,72 +0,0 @@
-From 9e7eb0ea442ecb1c3fe443289e288694f10c5148 Mon Sep 17 00:00:00 2001
-From: Miquel Raynal <miquel.raynal@bootlin.com>
-Date: Thu, 27 Jan 2022 10:18:01 +0100
-Subject: [PATCH 07/15] spi: spi-mem: Add an ecc parameter to the spi_mem_op
- structure
-
-Soon the SPI-NAND core will need a way to request a SPI controller to
-enable ECC support for a given operation. This is because of the
-pipelined integration of certain ECC engines, which are directly managed
-by the SPI controller itself.
-
-Introduce a spi_mem_op additional field for this purpose: ecc.
-
-So far this field is left unset and checked to be false by all
-the SPI controller drivers in their ->supports_op() hook, as they all
-call spi_mem_default_supports_op().
-
-Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
-Acked-by: Pratyush Yadav <p.yadav@ti.com>
-Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
-Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
-Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-7-miquel.raynal@bootlin.com
-(cherry picked from commit a433c2cbd75ab76f277364f44e76f32c7df306e7)
----
- drivers/spi/spi-mem.c       | 5 +++++
- include/linux/spi/spi-mem.h | 4 ++++
- 2 files changed, 9 insertions(+)
-
---- a/drivers/spi/spi-mem.c
-+++ b/drivers/spi/spi-mem.c
-@@ -178,6 +178,11 @@ bool spi_mem_default_supports_op(struct
- 			return false;
- 	}
- 
-+	if (op->data.ecc) {
-+		if (!spi_mem_controller_is_capable(ctlr, ecc))
-+			return false;
-+	}
-+
- 	return spi_mem_check_buswidth(mem, op);
- }
- EXPORT_SYMBOL_GPL(spi_mem_default_supports_op);
---- a/include/linux/spi/spi-mem.h
-+++ b/include/linux/spi/spi-mem.h
-@@ -89,6 +89,7 @@ enum spi_mem_data_dir {
-  * @dummy.dtr: whether the dummy bytes should be sent in DTR mode or not
-  * @data.buswidth: number of IO lanes used to send/receive the data
-  * @data.dtr: whether the data should be sent in DTR mode or not
-+ * @data.ecc: whether error correction is required or not
-  * @data.dir: direction of the transfer
-  * @data.nbytes: number of data bytes to send/receive. Can be zero if the
-  *		 operation does not involve transferring data
-@@ -119,6 +120,7 @@ struct spi_mem_op {
- 	struct {
- 		u8 buswidth;
- 		u8 dtr : 1;
-+		u8 ecc : 1;
- 		enum spi_mem_data_dir dir;
- 		unsigned int nbytes;
- 		union {
-@@ -288,9 +290,11 @@ struct spi_controller_mem_ops {
- /**
-  * struct spi_controller_mem_caps - SPI memory controller capabilities
-  * @dtr: Supports DTR operations
-+ * @ecc: Supports operations with error correction
-  */
- struct spi_controller_mem_caps {
- 	bool dtr;
-+	bool ecc;
- };
- 
- #define spi_mem_controller_is_capable(ctlr, cap)	\
diff --git a/target/linux/mediatek/patches-5.15/120-08-v5.18-mtd-spinand-Delay-a-little-bit-the-dirmap-creation.patch b/target/linux/mediatek/patches-5.15/120-08-v5.18-mtd-spinand-Delay-a-little-bit-the-dirmap-creation.patch
deleted file mode 100644
index 87c7b7cd297ac3..00000000000000
--- a/target/linux/mediatek/patches-5.15/120-08-v5.18-mtd-spinand-Delay-a-little-bit-the-dirmap-creation.patch
+++ /dev/null
@@ -1,50 +0,0 @@
-From 94ef3c35b935a63f6c156957c92f6cf33c9a8dae Mon Sep 17 00:00:00 2001
-From: Miquel Raynal <miquel.raynal@bootlin.com>
-Date: Thu, 27 Jan 2022 10:18:02 +0100
-Subject: [PATCH 08/15] mtd: spinand: Delay a little bit the dirmap creation
-
-As we will soon tweak the dirmap creation to act a little bit
-differently depending on the picked ECC engine, we need to initialize
-dirmaps after ECC engines. This should not have any effect as dirmaps
-are not yet used at this point.
-
-Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
-Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
-Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-8-miquel.raynal@bootlin.com
-(cherry picked from commit dc4c2cbf0be2d4a8e2a65013ea2815bb2c8ba949)
----
- drivers/mtd/nand/spi/core.c | 16 ++++++++--------
- 1 file changed, 8 insertions(+), 8 deletions(-)
-
---- a/drivers/mtd/nand/spi/core.c
-+++ b/drivers/mtd/nand/spi/core.c
-@@ -1221,14 +1221,6 @@ static int spinand_init(struct spinand_d
- 	if (ret)
- 		goto err_free_bufs;
- 
--	ret = spinand_create_dirmaps(spinand);
--	if (ret) {
--		dev_err(dev,
--			"Failed to create direct mappings for read/write operations (err = %d)\n",
--			ret);
--		goto err_manuf_cleanup;
--	}
--
- 	ret = nanddev_init(nand, &spinand_ops, THIS_MODULE);
- 	if (ret)
- 		goto err_manuf_cleanup;
-@@ -1263,6 +1255,14 @@ static int spinand_init(struct spinand_d
- 	mtd->ecc_strength = nanddev_get_ecc_conf(nand)->strength;
- 	mtd->ecc_step_size = nanddev_get_ecc_conf(nand)->step_size;
- 
-+	ret = spinand_create_dirmaps(spinand);
-+	if (ret) {
-+		dev_err(dev,
-+			"Failed to create direct mappings for read/write operations (err = %d)\n",
-+			ret);
-+		goto err_cleanup_ecc_engine;
-+	}
-+
- 	return 0;
- 
- err_cleanup_ecc_engine:
diff --git a/target/linux/mediatek/patches-5.15/120-09-v5.18-mtd-spinand-Create-direct-mapping-descriptors-for-EC.patch b/target/linux/mediatek/patches-5.15/120-09-v5.18-mtd-spinand-Create-direct-mapping-descriptors-for-EC.patch
deleted file mode 100644
index 35912cd2cd6b81..00000000000000
--- a/target/linux/mediatek/patches-5.15/120-09-v5.18-mtd-spinand-Create-direct-mapping-descriptors-for-EC.patch
+++ /dev/null
@@ -1,98 +0,0 @@
-From eb4a2d282c3c5752211d69be6dff2674119e5583 Mon Sep 17 00:00:00 2001
-From: Miquel Raynal <miquel.raynal@bootlin.com>
-Date: Thu, 27 Jan 2022 10:18:03 +0100
-Subject: [PATCH 09/15] mtd: spinand: Create direct mapping descriptors for ECC
- operations
-
-In order for pipelined ECC engines to be able to enable/disable the ECC
-engine only when needed and avoid races when future parallel-operations
-will be supported, we need to provide the information about the use of
-the ECC engine in the direct mapping hooks. As direct mapping
-configurations are meant to be static, it is best to create two new
-mappings: one for regular 'raw' accesses and one for accesses involving
-correction. It is up to the driver to use or not the new ECC enable
-boolean contained in the spi-mem operation.
-
-As dirmaps are not free (they consume a few pages of MMIO address space)
-and because these extra entries are only meant to be used by pipelined
-engines, let's limit their use to this specific type of engine and save
-a bit of memory with all the other setups.
-
-Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
-Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
-Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-9-miquel.raynal@bootlin.com
-(cherry picked from commit f9d7c7265bcff7d9a17425a8cddf702e8fe159c2)
----
- drivers/mtd/nand/spi/core.c | 35 +++++++++++++++++++++++++++++++++--
- include/linux/mtd/spinand.h |  2 ++
- 2 files changed, 35 insertions(+), 2 deletions(-)
-
---- a/drivers/mtd/nand/spi/core.c
-+++ b/drivers/mtd/nand/spi/core.c
-@@ -381,7 +381,10 @@ static int spinand_read_from_cache_op(st
- 		}
- 	}
- 
--	rdesc = spinand->dirmaps[req->pos.plane].rdesc;
-+	if (req->mode == MTD_OPS_RAW)
-+		rdesc = spinand->dirmaps[req->pos.plane].rdesc;
-+	else
-+		rdesc = spinand->dirmaps[req->pos.plane].rdesc_ecc;
- 
- 	while (nbytes) {
- 		ret = spi_mem_dirmap_read(rdesc, column, nbytes, buf);
-@@ -452,7 +455,10 @@ static int spinand_write_to_cache_op(str
- 			       req->ooblen);
- 	}
- 
--	wdesc = spinand->dirmaps[req->pos.plane].wdesc;
-+	if (req->mode == MTD_OPS_RAW)
-+		wdesc = spinand->dirmaps[req->pos.plane].wdesc;
-+	else
-+		wdesc = spinand->dirmaps[req->pos.plane].wdesc_ecc;
- 
- 	while (nbytes) {
- 		ret = spi_mem_dirmap_write(wdesc, column, nbytes, buf);
-@@ -875,6 +881,31 @@ static int spinand_create_dirmap(struct
- 
- 	spinand->dirmaps[plane].rdesc = desc;
- 
-+	if (nand->ecc.engine->integration != NAND_ECC_ENGINE_INTEGRATION_PIPELINED) {
-+		spinand->dirmaps[plane].wdesc_ecc = spinand->dirmaps[plane].wdesc;
-+		spinand->dirmaps[plane].rdesc_ecc = spinand->dirmaps[plane].rdesc;
-+
-+		return 0;
-+	}
-+
-+	info.op_tmpl = *spinand->op_templates.update_cache;
-+	info.op_tmpl.data.ecc = true;
-+	desc = devm_spi_mem_dirmap_create(&spinand->spimem->spi->dev,
-+					  spinand->spimem, &info);
-+	if (IS_ERR(desc))
-+		return PTR_ERR(desc);
-+
-+	spinand->dirmaps[plane].wdesc_ecc = desc;
-+
-+	info.op_tmpl = *spinand->op_templates.read_cache;
-+	info.op_tmpl.data.ecc = true;
-+	desc = devm_spi_mem_dirmap_create(&spinand->spimem->spi->dev,
-+					  spinand->spimem, &info);
-+	if (IS_ERR(desc))
-+		return PTR_ERR(desc);
-+
-+	spinand->dirmaps[plane].rdesc_ecc = desc;
-+
- 	return 0;
- }
- 
---- a/include/linux/mtd/spinand.h
-+++ b/include/linux/mtd/spinand.h
-@@ -392,6 +392,8 @@ struct spinand_info {
- struct spinand_dirmap {
- 	struct spi_mem_dirmap_desc *wdesc;
- 	struct spi_mem_dirmap_desc *rdesc;
-+	struct spi_mem_dirmap_desc *wdesc_ecc;
-+	struct spi_mem_dirmap_desc *rdesc_ecc;
- };
- 
- /**
diff --git a/target/linux/mediatek/patches-5.15/120-11-v5.19-mtd-nand-make-mtk_ecc.c-a-separated-module.patch b/target/linux/mediatek/patches-5.15/120-11-v5.19-mtd-nand-make-mtk_ecc.c-a-separated-module.patch
deleted file mode 100644
index fd9098eae96e45..00000000000000
--- a/target/linux/mediatek/patches-5.15/120-11-v5.19-mtd-nand-make-mtk_ecc.c-a-separated-module.patch
+++ /dev/null
@@ -1,1383 +0,0 @@
-From ebb9653d4a87c64fb679e4c339e867556dada719 Mon Sep 17 00:00:00 2001
-From: Chuanhong Guo <gch981213@gmail.com>
-Date: Tue, 22 Mar 2022 18:44:21 +0800
-Subject: [PATCH 11/15] mtd: nand: make mtk_ecc.c a separated module
-
-this code will be used in mediatek snfi spi-mem controller with
-pipelined ECC engine.
-
-Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
-(cherry picked from commit 316f47cec4ce5b81aa8006de202d8769c117a52d)
----
- drivers/mtd/nand/Kconfig                                   | 7 +++++++
- drivers/mtd/nand/Makefile                                  | 1 +
- drivers/mtd/nand/{raw/mtk_ecc.c => ecc-mtk.c}              | 3 +--
- drivers/mtd/nand/raw/Kconfig                               | 1 +
- drivers/mtd/nand/raw/Makefile                              | 2 +-
- drivers/mtd/nand/raw/mtk_nand.c                            | 2 +-
- .../nand/raw/mtk_ecc.h => include/linux/mtd/nand-ecc-mtk.h | 0
- 7 files changed, 12 insertions(+), 4 deletions(-)
- rename drivers/mtd/nand/{raw/mtk_ecc.c => ecc-mtk.c} (99%)
- rename drivers/mtd/nand/raw/mtk_ecc.h => include/linux/mtd/nand-ecc-mtk.h (100%)
-
---- a/drivers/mtd/nand/Kconfig
-+++ b/drivers/mtd/nand/Kconfig
-@@ -50,6 +50,13 @@ config MTD_NAND_MTK_BMT
- 	bool "Support MediaTek NAND Bad-block Management Table"
- 	default n
- 
-+config MTD_NAND_ECC_MEDIATEK
-+	tristate "Mediatek hardware ECC engine"
-+	depends on HAS_IOMEM
-+	select MTD_NAND_ECC
-+	help
-+	  This enables support for the hardware ECC engine from Mediatek.
-+
- endmenu
- 
- endmenu
---- a/drivers/mtd/nand/Makefile
-+++ b/drivers/mtd/nand/Makefile
-@@ -3,6 +3,7 @@
- nandcore-objs := core.o bbt.o
- obj-$(CONFIG_MTD_NAND_CORE) += nandcore.o
- obj-$(CONFIG_MTD_NAND_MTK_BMT)	+= mtk_bmt.o mtk_bmt_v2.o mtk_bmt_bbt.o mtk_bmt_nmbm.o
-+obj-$(CONFIG_MTD_NAND_ECC_MEDIATEK) += ecc-mtk.o
- 
- obj-y	+= onenand/
- obj-y	+= raw/
---- a/drivers/mtd/nand/raw/mtk_ecc.c
-+++ /dev/null
-@@ -1,599 +0,0 @@
--// SPDX-License-Identifier: GPL-2.0 OR MIT
--/*
-- * MTK ECC controller driver.
-- * Copyright (C) 2016  MediaTek Inc.
-- * Authors:	Xiaolei Li		<xiaolei.li@mediatek.com>
-- *		Jorge Ramirez-Ortiz	<jorge.ramirez-ortiz@linaro.org>
-- */
--
--#include <linux/platform_device.h>
--#include <linux/dma-mapping.h>
--#include <linux/interrupt.h>
--#include <linux/clk.h>
--#include <linux/module.h>
--#include <linux/iopoll.h>
--#include <linux/of.h>
--#include <linux/of_platform.h>
--#include <linux/mutex.h>
--
--#include "mtk_ecc.h"
--
--#define ECC_IDLE_MASK		BIT(0)
--#define ECC_IRQ_EN		BIT(0)
--#define ECC_PG_IRQ_SEL		BIT(1)
--#define ECC_OP_ENABLE		(1)
--#define ECC_OP_DISABLE		(0)
--
--#define ECC_ENCCON		(0x00)
--#define ECC_ENCCNFG		(0x04)
--#define		ECC_MS_SHIFT		(16)
--#define ECC_ENCDIADDR		(0x08)
--#define ECC_ENCIDLE		(0x0C)
--#define ECC_DECCON		(0x100)
--#define ECC_DECCNFG		(0x104)
--#define		DEC_EMPTY_EN		BIT(31)
--#define		DEC_CNFG_CORRECT	(0x3 << 12)
--#define ECC_DECIDLE		(0x10C)
--#define ECC_DECENUM0		(0x114)
--
--#define ECC_TIMEOUT		(500000)
--
--#define ECC_IDLE_REG(op)	((op) == ECC_ENCODE ? ECC_ENCIDLE : ECC_DECIDLE)
--#define ECC_CTL_REG(op)		((op) == ECC_ENCODE ? ECC_ENCCON : ECC_DECCON)
--
--struct mtk_ecc_caps {
--	u32 err_mask;
--	u32 err_shift;
--	const u8 *ecc_strength;
--	const u32 *ecc_regs;
--	u8 num_ecc_strength;
--	u8 ecc_mode_shift;
--	u32 parity_bits;
--	int pg_irq_sel;
--};
--
--struct mtk_ecc {
--	struct device *dev;
--	const struct mtk_ecc_caps *caps;
--	void __iomem *regs;
--	struct clk *clk;
--
--	struct completion done;
--	struct mutex lock;
--	u32 sectors;
--
--	u8 *eccdata;
--};
--
--/* ecc strength that each IP supports */
--static const u8 ecc_strength_mt2701[] = {
--	4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,
--	40, 44, 48, 52, 56, 60
--};
--
--static const u8 ecc_strength_mt2712[] = {
--	4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,
--	40, 44, 48, 52, 56, 60, 68, 72, 80
--};
--
--static const u8 ecc_strength_mt7622[] = {
--	4, 6, 8, 10, 12
--};
--
--enum mtk_ecc_regs {
--	ECC_ENCPAR00,
--	ECC_ENCIRQ_EN,
--	ECC_ENCIRQ_STA,
--	ECC_DECDONE,
--	ECC_DECIRQ_EN,
--	ECC_DECIRQ_STA,
--};
--
--static int mt2701_ecc_regs[] = {
--	[ECC_ENCPAR00] =        0x10,
--	[ECC_ENCIRQ_EN] =       0x80,
--	[ECC_ENCIRQ_STA] =      0x84,
--	[ECC_DECDONE] =         0x124,
--	[ECC_DECIRQ_EN] =       0x200,
--	[ECC_DECIRQ_STA] =      0x204,
--};
--
--static int mt2712_ecc_regs[] = {
--	[ECC_ENCPAR00] =        0x300,
--	[ECC_ENCIRQ_EN] =       0x80,
--	[ECC_ENCIRQ_STA] =      0x84,
--	[ECC_DECDONE] =         0x124,
--	[ECC_DECIRQ_EN] =       0x200,
--	[ECC_DECIRQ_STA] =      0x204,
--};
--
--static int mt7622_ecc_regs[] = {
--	[ECC_ENCPAR00] =        0x10,
--	[ECC_ENCIRQ_EN] =       0x30,
--	[ECC_ENCIRQ_STA] =      0x34,
--	[ECC_DECDONE] =         0x11c,
--	[ECC_DECIRQ_EN] =       0x140,
--	[ECC_DECIRQ_STA] =      0x144,
--};
--
--static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc,
--				     enum mtk_ecc_operation op)
--{
--	struct device *dev = ecc->dev;
--	u32 val;
--	int ret;
--
--	ret = readl_poll_timeout_atomic(ecc->regs + ECC_IDLE_REG(op), val,
--					val & ECC_IDLE_MASK,
--					10, ECC_TIMEOUT);
--	if (ret)
--		dev_warn(dev, "%s NOT idle\n",
--			 op == ECC_ENCODE ? "encoder" : "decoder");
--}
--
--static irqreturn_t mtk_ecc_irq(int irq, void *id)
--{
--	struct mtk_ecc *ecc = id;
--	u32 dec, enc;
--
--	dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA])
--		    & ECC_IRQ_EN;
--	if (dec) {
--		dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]);
--		if (dec & ecc->sectors) {
--			/*
--			 * Clear decode IRQ status once again to ensure that
--			 * there will be no extra IRQ.
--			 */
--			readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]);
--			ecc->sectors = 0;
--			complete(&ecc->done);
--		} else {
--			return IRQ_HANDLED;
--		}
--	} else {
--		enc = readl(ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_STA])
--		      & ECC_IRQ_EN;
--		if (enc)
--			complete(&ecc->done);
--		else
--			return IRQ_NONE;
--	}
--
--	return IRQ_HANDLED;
--}
--
--static int mtk_ecc_config(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
--{
--	u32 ecc_bit, dec_sz, enc_sz;
--	u32 reg, i;
--
--	for (i = 0; i < ecc->caps->num_ecc_strength; i++) {
--		if (ecc->caps->ecc_strength[i] == config->strength)
--			break;
--	}
--
--	if (i == ecc->caps->num_ecc_strength) {
--		dev_err(ecc->dev, "invalid ecc strength %d\n",
--			config->strength);
--		return -EINVAL;
--	}
--
--	ecc_bit = i;
--
--	if (config->op == ECC_ENCODE) {
--		/* configure ECC encoder (in bits) */
--		enc_sz = config->len << 3;
--
--		reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift);
--		reg |= (enc_sz << ECC_MS_SHIFT);
--		writel(reg, ecc->regs + ECC_ENCCNFG);
--
--		if (config->mode != ECC_NFI_MODE)
--			writel(lower_32_bits(config->addr),
--			       ecc->regs + ECC_ENCDIADDR);
--
--	} else {
--		/* configure ECC decoder (in bits) */
--		dec_sz = (config->len << 3) +
--			 config->strength * ecc->caps->parity_bits;
--
--		reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift);
--		reg |= (dec_sz << ECC_MS_SHIFT) | DEC_CNFG_CORRECT;
--		reg |= DEC_EMPTY_EN;
--		writel(reg, ecc->regs + ECC_DECCNFG);
--
--		if (config->sectors)
--			ecc->sectors = 1 << (config->sectors - 1);
--	}
--
--	return 0;
--}
--
--void mtk_ecc_get_stats(struct mtk_ecc *ecc, struct mtk_ecc_stats *stats,
--		       int sectors)
--{
--	u32 offset, i, err;
--	u32 bitflips = 0;
--
--	stats->corrected = 0;
--	stats->failed = 0;
--
--	for (i = 0; i < sectors; i++) {
--		offset = (i >> 2) << 2;
--		err = readl(ecc->regs + ECC_DECENUM0 + offset);
--		err = err >> ((i % 4) * ecc->caps->err_shift);
--		err &= ecc->caps->err_mask;
--		if (err == ecc->caps->err_mask) {
--			/* uncorrectable errors */
--			stats->failed++;
--			continue;
--		}
--
--		stats->corrected += err;
--		bitflips = max_t(u32, bitflips, err);
--	}
--
--	stats->bitflips = bitflips;
--}
--EXPORT_SYMBOL(mtk_ecc_get_stats);
--
--void mtk_ecc_release(struct mtk_ecc *ecc)
--{
--	clk_disable_unprepare(ecc->clk);
--	put_device(ecc->dev);
--}
--EXPORT_SYMBOL(mtk_ecc_release);
--
--static void mtk_ecc_hw_init(struct mtk_ecc *ecc)
--{
--	mtk_ecc_wait_idle(ecc, ECC_ENCODE);
--	writew(ECC_OP_DISABLE, ecc->regs + ECC_ENCCON);
--
--	mtk_ecc_wait_idle(ecc, ECC_DECODE);
--	writel(ECC_OP_DISABLE, ecc->regs + ECC_DECCON);
--}
--
--static struct mtk_ecc *mtk_ecc_get(struct device_node *np)
--{
--	struct platform_device *pdev;
--	struct mtk_ecc *ecc;
--
--	pdev = of_find_device_by_node(np);
--	if (!pdev)
--		return ERR_PTR(-EPROBE_DEFER);
--
--	ecc = platform_get_drvdata(pdev);
--	if (!ecc) {
--		put_device(&pdev->dev);
--		return ERR_PTR(-EPROBE_DEFER);
--	}
--
--	clk_prepare_enable(ecc->clk);
--	mtk_ecc_hw_init(ecc);
--
--	return ecc;
--}
--
--struct mtk_ecc *of_mtk_ecc_get(struct device_node *of_node)
--{
--	struct mtk_ecc *ecc = NULL;
--	struct device_node *np;
--
--	np = of_parse_phandle(of_node, "ecc-engine", 0);
--	if (np) {
--		ecc = mtk_ecc_get(np);
--		of_node_put(np);
--	}
--
--	return ecc;
--}
--EXPORT_SYMBOL(of_mtk_ecc_get);
--
--int mtk_ecc_enable(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
--{
--	enum mtk_ecc_operation op = config->op;
--	u16 reg_val;
--	int ret;
--
--	ret = mutex_lock_interruptible(&ecc->lock);
--	if (ret) {
--		dev_err(ecc->dev, "interrupted when attempting to lock\n");
--		return ret;
--	}
--
--	mtk_ecc_wait_idle(ecc, op);
--
--	ret = mtk_ecc_config(ecc, config);
--	if (ret) {
--		mutex_unlock(&ecc->lock);
--		return ret;
--	}
--
--	if (config->mode != ECC_NFI_MODE || op != ECC_ENCODE) {
--		init_completion(&ecc->done);
--		reg_val = ECC_IRQ_EN;
--		/*
--		 * For ECC_NFI_MODE, if ecc->caps->pg_irq_sel is 1, then it
--		 * means this chip can only generate one ecc irq during page
--		 * read / write. If is 0, generate one ecc irq each ecc step.
--		 */
--		if (ecc->caps->pg_irq_sel && config->mode == ECC_NFI_MODE)
--			reg_val |= ECC_PG_IRQ_SEL;
--		if (op == ECC_ENCODE)
--			writew(reg_val, ecc->regs +
--			       ecc->caps->ecc_regs[ECC_ENCIRQ_EN]);
--		else
--			writew(reg_val, ecc->regs +
--			       ecc->caps->ecc_regs[ECC_DECIRQ_EN]);
--	}
--
--	writew(ECC_OP_ENABLE, ecc->regs + ECC_CTL_REG(op));
--
--	return 0;
--}
--EXPORT_SYMBOL(mtk_ecc_enable);
--
--void mtk_ecc_disable(struct mtk_ecc *ecc)
--{
--	enum mtk_ecc_operation op = ECC_ENCODE;
--
--	/* find out the running operation */
--	if (readw(ecc->regs + ECC_CTL_REG(op)) != ECC_OP_ENABLE)
--		op = ECC_DECODE;
--
--	/* disable it */
--	mtk_ecc_wait_idle(ecc, op);
--	if (op == ECC_DECODE) {
--		/*
--		 * Clear decode IRQ status in case there is a timeout to wait
--		 * decode IRQ.
--		 */
--		readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]);
--		writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_EN]);
--	} else {
--		writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_EN]);
--	}
--
--	writew(ECC_OP_DISABLE, ecc->regs + ECC_CTL_REG(op));
--
--	mutex_unlock(&ecc->lock);
--}
--EXPORT_SYMBOL(mtk_ecc_disable);
--
--int mtk_ecc_wait_done(struct mtk_ecc *ecc, enum mtk_ecc_operation op)
--{
--	int ret;
--
--	ret = wait_for_completion_timeout(&ecc->done, msecs_to_jiffies(500));
--	if (!ret) {
--		dev_err(ecc->dev, "%s timeout - interrupt did not arrive)\n",
--			(op == ECC_ENCODE) ? "encoder" : "decoder");
--		return -ETIMEDOUT;
--	}
--
--	return 0;
--}
--EXPORT_SYMBOL(mtk_ecc_wait_done);
--
--int mtk_ecc_encode(struct mtk_ecc *ecc, struct mtk_ecc_config *config,
--		   u8 *data, u32 bytes)
--{
--	dma_addr_t addr;
--	u32 len;
--	int ret;
--
--	addr = dma_map_single(ecc->dev, data, bytes, DMA_TO_DEVICE);
--	ret = dma_mapping_error(ecc->dev, addr);
--	if (ret) {
--		dev_err(ecc->dev, "dma mapping error\n");
--		return -EINVAL;
--	}
--
--	config->op = ECC_ENCODE;
--	config->addr = addr;
--	ret = mtk_ecc_enable(ecc, config);
--	if (ret) {
--		dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE);
--		return ret;
--	}
--
--	ret = mtk_ecc_wait_done(ecc, ECC_ENCODE);
--	if (ret)
--		goto timeout;
--
--	mtk_ecc_wait_idle(ecc, ECC_ENCODE);
--
--	/* Program ECC bytes to OOB: per sector oob = FDM + ECC + SPARE */
--	len = (config->strength * ecc->caps->parity_bits + 7) >> 3;
--
--	/* write the parity bytes generated by the ECC back to temp buffer */
--	__ioread32_copy(ecc->eccdata,
--			ecc->regs + ecc->caps->ecc_regs[ECC_ENCPAR00],
--			round_up(len, 4));
--
--	/* copy into possibly unaligned OOB region with actual length */
--	memcpy(data + bytes, ecc->eccdata, len);
--timeout:
--
--	dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE);
--	mtk_ecc_disable(ecc);
--
--	return ret;
--}
--EXPORT_SYMBOL(mtk_ecc_encode);
--
--void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p)
--{
--	const u8 *ecc_strength = ecc->caps->ecc_strength;
--	int i;
--
--	for (i = 0; i < ecc->caps->num_ecc_strength; i++) {
--		if (*p <= ecc_strength[i]) {
--			if (!i)
--				*p = ecc_strength[i];
--			else if (*p != ecc_strength[i])
--				*p = ecc_strength[i - 1];
--			return;
--		}
--	}
--
--	*p = ecc_strength[ecc->caps->num_ecc_strength - 1];
--}
--EXPORT_SYMBOL(mtk_ecc_adjust_strength);
--
--unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc)
--{
--	return ecc->caps->parity_bits;
--}
--EXPORT_SYMBOL(mtk_ecc_get_parity_bits);
--
--static const struct mtk_ecc_caps mtk_ecc_caps_mt2701 = {
--	.err_mask = 0x3f,
--	.err_shift = 8,
--	.ecc_strength = ecc_strength_mt2701,
--	.ecc_regs = mt2701_ecc_regs,
--	.num_ecc_strength = 20,
--	.ecc_mode_shift = 5,
--	.parity_bits = 14,
--	.pg_irq_sel = 0,
--};
--
--static const struct mtk_ecc_caps mtk_ecc_caps_mt2712 = {
--	.err_mask = 0x7f,
--	.err_shift = 8,
--	.ecc_strength = ecc_strength_mt2712,
--	.ecc_regs = mt2712_ecc_regs,
--	.num_ecc_strength = 23,
--	.ecc_mode_shift = 5,
--	.parity_bits = 14,
--	.pg_irq_sel = 1,
--};
--
--static const struct mtk_ecc_caps mtk_ecc_caps_mt7622 = {
--	.err_mask = 0x1f,
--	.err_shift = 5,
--	.ecc_strength = ecc_strength_mt7622,
--	.ecc_regs = mt7622_ecc_regs,
--	.num_ecc_strength = 5,
--	.ecc_mode_shift = 4,
--	.parity_bits = 13,
--	.pg_irq_sel = 0,
--};
--
--static const struct of_device_id mtk_ecc_dt_match[] = {
--	{
--		.compatible = "mediatek,mt2701-ecc",
--		.data = &mtk_ecc_caps_mt2701,
--	}, {
--		.compatible = "mediatek,mt2712-ecc",
--		.data = &mtk_ecc_caps_mt2712,
--	}, {
--		.compatible = "mediatek,mt7622-ecc",
--		.data = &mtk_ecc_caps_mt7622,
--	},
--	{},
--};
--
--static int mtk_ecc_probe(struct platform_device *pdev)
--{
--	struct device *dev = &pdev->dev;
--	struct mtk_ecc *ecc;
--	struct resource *res;
--	u32 max_eccdata_size;
--	int irq, ret;
--
--	ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL);
--	if (!ecc)
--		return -ENOMEM;
--
--	ecc->caps = of_device_get_match_data(dev);
--
--	max_eccdata_size = ecc->caps->num_ecc_strength - 1;
--	max_eccdata_size = ecc->caps->ecc_strength[max_eccdata_size];
--	max_eccdata_size = (max_eccdata_size * ecc->caps->parity_bits + 7) >> 3;
--	max_eccdata_size = round_up(max_eccdata_size, 4);
--	ecc->eccdata = devm_kzalloc(dev, max_eccdata_size, GFP_KERNEL);
--	if (!ecc->eccdata)
--		return -ENOMEM;
--
--	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
--	ecc->regs = devm_ioremap_resource(dev, res);
--	if (IS_ERR(ecc->regs))
--		return PTR_ERR(ecc->regs);
--
--	ecc->clk = devm_clk_get(dev, NULL);
--	if (IS_ERR(ecc->clk)) {
--		dev_err(dev, "failed to get clock: %ld\n", PTR_ERR(ecc->clk));
--		return PTR_ERR(ecc->clk);
--	}
--
--	irq = platform_get_irq(pdev, 0);
--	if (irq < 0)
--		return irq;
--
--	ret = dma_set_mask(dev, DMA_BIT_MASK(32));
--	if (ret) {
--		dev_err(dev, "failed to set DMA mask\n");
--		return ret;
--	}
--
--	ret = devm_request_irq(dev, irq, mtk_ecc_irq, 0x0, "mtk-ecc", ecc);
--	if (ret) {
--		dev_err(dev, "failed to request irq\n");
--		return -EINVAL;
--	}
--
--	ecc->dev = dev;
--	mutex_init(&ecc->lock);
--	platform_set_drvdata(pdev, ecc);
--	dev_info(dev, "probed\n");
--
--	return 0;
--}
--
--#ifdef CONFIG_PM_SLEEP
--static int mtk_ecc_suspend(struct device *dev)
--{
--	struct mtk_ecc *ecc = dev_get_drvdata(dev);
--
--	clk_disable_unprepare(ecc->clk);
--
--	return 0;
--}
--
--static int mtk_ecc_resume(struct device *dev)
--{
--	struct mtk_ecc *ecc = dev_get_drvdata(dev);
--	int ret;
--
--	ret = clk_prepare_enable(ecc->clk);
--	if (ret) {
--		dev_err(dev, "failed to enable clk\n");
--		return ret;
--	}
--
--	return 0;
--}
--
--static SIMPLE_DEV_PM_OPS(mtk_ecc_pm_ops, mtk_ecc_suspend, mtk_ecc_resume);
--#endif
--
--MODULE_DEVICE_TABLE(of, mtk_ecc_dt_match);
--
--static struct platform_driver mtk_ecc_driver = {
--	.probe  = mtk_ecc_probe,
--	.driver = {
--		.name  = "mtk-ecc",
--		.of_match_table = of_match_ptr(mtk_ecc_dt_match),
--#ifdef CONFIG_PM_SLEEP
--		.pm = &mtk_ecc_pm_ops,
--#endif
--	},
--};
--
--module_platform_driver(mtk_ecc_driver);
--
--MODULE_AUTHOR("Xiaolei Li <xiaolei.li@mediatek.com>");
--MODULE_DESCRIPTION("MTK Nand ECC Driver");
--MODULE_LICENSE("Dual MIT/GPL");
---- /dev/null
-+++ b/drivers/mtd/nand/ecc-mtk.c
-@@ -0,0 +1,598 @@
-+// SPDX-License-Identifier: GPL-2.0 OR MIT
-+/*
-+ * MTK ECC controller driver.
-+ * Copyright (C) 2016  MediaTek Inc.
-+ * Authors:	Xiaolei Li		<xiaolei.li@mediatek.com>
-+ *		Jorge Ramirez-Ortiz	<jorge.ramirez-ortiz@linaro.org>
-+ */
-+
-+#include <linux/platform_device.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/interrupt.h>
-+#include <linux/clk.h>
-+#include <linux/module.h>
-+#include <linux/iopoll.h>
-+#include <linux/of.h>
-+#include <linux/of_platform.h>
-+#include <linux/mutex.h>
-+#include <linux/mtd/nand-ecc-mtk.h>
-+
-+#define ECC_IDLE_MASK		BIT(0)
-+#define ECC_IRQ_EN		BIT(0)
-+#define ECC_PG_IRQ_SEL		BIT(1)
-+#define ECC_OP_ENABLE		(1)
-+#define ECC_OP_DISABLE		(0)
-+
-+#define ECC_ENCCON		(0x00)
-+#define ECC_ENCCNFG		(0x04)
-+#define		ECC_MS_SHIFT		(16)
-+#define ECC_ENCDIADDR		(0x08)
-+#define ECC_ENCIDLE		(0x0C)
-+#define ECC_DECCON		(0x100)
-+#define ECC_DECCNFG		(0x104)
-+#define		DEC_EMPTY_EN		BIT(31)
-+#define		DEC_CNFG_CORRECT	(0x3 << 12)
-+#define ECC_DECIDLE		(0x10C)
-+#define ECC_DECENUM0		(0x114)
-+
-+#define ECC_TIMEOUT		(500000)
-+
-+#define ECC_IDLE_REG(op)	((op) == ECC_ENCODE ? ECC_ENCIDLE : ECC_DECIDLE)
-+#define ECC_CTL_REG(op)		((op) == ECC_ENCODE ? ECC_ENCCON : ECC_DECCON)
-+
-+struct mtk_ecc_caps {
-+	u32 err_mask;
-+	u32 err_shift;
-+	const u8 *ecc_strength;
-+	const u32 *ecc_regs;
-+	u8 num_ecc_strength;
-+	u8 ecc_mode_shift;
-+	u32 parity_bits;
-+	int pg_irq_sel;
-+};
-+
-+struct mtk_ecc {
-+	struct device *dev;
-+	const struct mtk_ecc_caps *caps;
-+	void __iomem *regs;
-+	struct clk *clk;
-+
-+	struct completion done;
-+	struct mutex lock;
-+	u32 sectors;
-+
-+	u8 *eccdata;
-+};
-+
-+/* ecc strength that each IP supports */
-+static const u8 ecc_strength_mt2701[] = {
-+	4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,
-+	40, 44, 48, 52, 56, 60
-+};
-+
-+static const u8 ecc_strength_mt2712[] = {
-+	4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,
-+	40, 44, 48, 52, 56, 60, 68, 72, 80
-+};
-+
-+static const u8 ecc_strength_mt7622[] = {
-+	4, 6, 8, 10, 12
-+};
-+
-+enum mtk_ecc_regs {
-+	ECC_ENCPAR00,
-+	ECC_ENCIRQ_EN,
-+	ECC_ENCIRQ_STA,
-+	ECC_DECDONE,
-+	ECC_DECIRQ_EN,
-+	ECC_DECIRQ_STA,
-+};
-+
-+static int mt2701_ecc_regs[] = {
-+	[ECC_ENCPAR00] =        0x10,
-+	[ECC_ENCIRQ_EN] =       0x80,
-+	[ECC_ENCIRQ_STA] =      0x84,
-+	[ECC_DECDONE] =         0x124,
-+	[ECC_DECIRQ_EN] =       0x200,
-+	[ECC_DECIRQ_STA] =      0x204,
-+};
-+
-+static int mt2712_ecc_regs[] = {
-+	[ECC_ENCPAR00] =        0x300,
-+	[ECC_ENCIRQ_EN] =       0x80,
-+	[ECC_ENCIRQ_STA] =      0x84,
-+	[ECC_DECDONE] =         0x124,
-+	[ECC_DECIRQ_EN] =       0x200,
-+	[ECC_DECIRQ_STA] =      0x204,
-+};
-+
-+static int mt7622_ecc_regs[] = {
-+	[ECC_ENCPAR00] =        0x10,
-+	[ECC_ENCIRQ_EN] =       0x30,
-+	[ECC_ENCIRQ_STA] =      0x34,
-+	[ECC_DECDONE] =         0x11c,
-+	[ECC_DECIRQ_EN] =       0x140,
-+	[ECC_DECIRQ_STA] =      0x144,
-+};
-+
-+static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc,
-+				     enum mtk_ecc_operation op)
-+{
-+	struct device *dev = ecc->dev;
-+	u32 val;
-+	int ret;
-+
-+	ret = readl_poll_timeout_atomic(ecc->regs + ECC_IDLE_REG(op), val,
-+					val & ECC_IDLE_MASK,
-+					10, ECC_TIMEOUT);
-+	if (ret)
-+		dev_warn(dev, "%s NOT idle\n",
-+			 op == ECC_ENCODE ? "encoder" : "decoder");
-+}
-+
-+static irqreturn_t mtk_ecc_irq(int irq, void *id)
-+{
-+	struct mtk_ecc *ecc = id;
-+	u32 dec, enc;
-+
-+	dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA])
-+		    & ECC_IRQ_EN;
-+	if (dec) {
-+		dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]);
-+		if (dec & ecc->sectors) {
-+			/*
-+			 * Clear decode IRQ status once again to ensure that
-+			 * there will be no extra IRQ.
-+			 */
-+			readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]);
-+			ecc->sectors = 0;
-+			complete(&ecc->done);
-+		} else {
-+			return IRQ_HANDLED;
-+		}
-+	} else {
-+		enc = readl(ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_STA])
-+		      & ECC_IRQ_EN;
-+		if (enc)
-+			complete(&ecc->done);
-+		else
-+			return IRQ_NONE;
-+	}
-+
-+	return IRQ_HANDLED;
-+}
-+
-+static int mtk_ecc_config(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
-+{
-+	u32 ecc_bit, dec_sz, enc_sz;
-+	u32 reg, i;
-+
-+	for (i = 0; i < ecc->caps->num_ecc_strength; i++) {
-+		if (ecc->caps->ecc_strength[i] == config->strength)
-+			break;
-+	}
-+
-+	if (i == ecc->caps->num_ecc_strength) {
-+		dev_err(ecc->dev, "invalid ecc strength %d\n",
-+			config->strength);
-+		return -EINVAL;
-+	}
-+
-+	ecc_bit = i;
-+
-+	if (config->op == ECC_ENCODE) {
-+		/* configure ECC encoder (in bits) */
-+		enc_sz = config->len << 3;
-+
-+		reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift);
-+		reg |= (enc_sz << ECC_MS_SHIFT);
-+		writel(reg, ecc->regs + ECC_ENCCNFG);
-+
-+		if (config->mode != ECC_NFI_MODE)
-+			writel(lower_32_bits(config->addr),
-+			       ecc->regs + ECC_ENCDIADDR);
-+
-+	} else {
-+		/* configure ECC decoder (in bits) */
-+		dec_sz = (config->len << 3) +
-+			 config->strength * ecc->caps->parity_bits;
-+
-+		reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift);
-+		reg |= (dec_sz << ECC_MS_SHIFT) | DEC_CNFG_CORRECT;
-+		reg |= DEC_EMPTY_EN;
-+		writel(reg, ecc->regs + ECC_DECCNFG);
-+
-+		if (config->sectors)
-+			ecc->sectors = 1 << (config->sectors - 1);
-+	}
-+
-+	return 0;
-+}
-+
-+void mtk_ecc_get_stats(struct mtk_ecc *ecc, struct mtk_ecc_stats *stats,
-+		       int sectors)
-+{
-+	u32 offset, i, err;
-+	u32 bitflips = 0;
-+
-+	stats->corrected = 0;
-+	stats->failed = 0;
-+
-+	for (i = 0; i < sectors; i++) {
-+		offset = (i >> 2) << 2;
-+		err = readl(ecc->regs + ECC_DECENUM0 + offset);
-+		err = err >> ((i % 4) * ecc->caps->err_shift);
-+		err &= ecc->caps->err_mask;
-+		if (err == ecc->caps->err_mask) {
-+			/* uncorrectable errors */
-+			stats->failed++;
-+			continue;
-+		}
-+
-+		stats->corrected += err;
-+		bitflips = max_t(u32, bitflips, err);
-+	}
-+
-+	stats->bitflips = bitflips;
-+}
-+EXPORT_SYMBOL(mtk_ecc_get_stats);
-+
-+void mtk_ecc_release(struct mtk_ecc *ecc)
-+{
-+	clk_disable_unprepare(ecc->clk);
-+	put_device(ecc->dev);
-+}
-+EXPORT_SYMBOL(mtk_ecc_release);
-+
-+static void mtk_ecc_hw_init(struct mtk_ecc *ecc)
-+{
-+	mtk_ecc_wait_idle(ecc, ECC_ENCODE);
-+	writew(ECC_OP_DISABLE, ecc->regs + ECC_ENCCON);
-+
-+	mtk_ecc_wait_idle(ecc, ECC_DECODE);
-+	writel(ECC_OP_DISABLE, ecc->regs + ECC_DECCON);
-+}
-+
-+static struct mtk_ecc *mtk_ecc_get(struct device_node *np)
-+{
-+	struct platform_device *pdev;
-+	struct mtk_ecc *ecc;
-+
-+	pdev = of_find_device_by_node(np);
-+	if (!pdev)
-+		return ERR_PTR(-EPROBE_DEFER);
-+
-+	ecc = platform_get_drvdata(pdev);
-+	if (!ecc) {
-+		put_device(&pdev->dev);
-+		return ERR_PTR(-EPROBE_DEFER);
-+	}
-+
-+	clk_prepare_enable(ecc->clk);
-+	mtk_ecc_hw_init(ecc);
-+
-+	return ecc;
-+}
-+
-+struct mtk_ecc *of_mtk_ecc_get(struct device_node *of_node)
-+{
-+	struct mtk_ecc *ecc = NULL;
-+	struct device_node *np;
-+
-+	np = of_parse_phandle(of_node, "ecc-engine", 0);
-+	if (np) {
-+		ecc = mtk_ecc_get(np);
-+		of_node_put(np);
-+	}
-+
-+	return ecc;
-+}
-+EXPORT_SYMBOL(of_mtk_ecc_get);
-+
-+int mtk_ecc_enable(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
-+{
-+	enum mtk_ecc_operation op = config->op;
-+	u16 reg_val;
-+	int ret;
-+
-+	ret = mutex_lock_interruptible(&ecc->lock);
-+	if (ret) {
-+		dev_err(ecc->dev, "interrupted when attempting to lock\n");
-+		return ret;
-+	}
-+
-+	mtk_ecc_wait_idle(ecc, op);
-+
-+	ret = mtk_ecc_config(ecc, config);
-+	if (ret) {
-+		mutex_unlock(&ecc->lock);
-+		return ret;
-+	}
-+
-+	if (config->mode != ECC_NFI_MODE || op != ECC_ENCODE) {
-+		init_completion(&ecc->done);
-+		reg_val = ECC_IRQ_EN;
-+		/*
-+		 * For ECC_NFI_MODE, if ecc->caps->pg_irq_sel is 1, then it
-+		 * means this chip can only generate one ecc irq during page
-+		 * read / write. If is 0, generate one ecc irq each ecc step.
-+		 */
-+		if (ecc->caps->pg_irq_sel && config->mode == ECC_NFI_MODE)
-+			reg_val |= ECC_PG_IRQ_SEL;
-+		if (op == ECC_ENCODE)
-+			writew(reg_val, ecc->regs +
-+			       ecc->caps->ecc_regs[ECC_ENCIRQ_EN]);
-+		else
-+			writew(reg_val, ecc->regs +
-+			       ecc->caps->ecc_regs[ECC_DECIRQ_EN]);
-+	}
-+
-+	writew(ECC_OP_ENABLE, ecc->regs + ECC_CTL_REG(op));
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(mtk_ecc_enable);
-+
-+void mtk_ecc_disable(struct mtk_ecc *ecc)
-+{
-+	enum mtk_ecc_operation op = ECC_ENCODE;
-+
-+	/* find out the running operation */
-+	if (readw(ecc->regs + ECC_CTL_REG(op)) != ECC_OP_ENABLE)
-+		op = ECC_DECODE;
-+
-+	/* disable it */
-+	mtk_ecc_wait_idle(ecc, op);
-+	if (op == ECC_DECODE) {
-+		/*
-+		 * Clear decode IRQ status in case there is a timeout to wait
-+		 * decode IRQ.
-+		 */
-+		readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]);
-+		writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_EN]);
-+	} else {
-+		writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_EN]);
-+	}
-+
-+	writew(ECC_OP_DISABLE, ecc->regs + ECC_CTL_REG(op));
-+
-+	mutex_unlock(&ecc->lock);
-+}
-+EXPORT_SYMBOL(mtk_ecc_disable);
-+
-+int mtk_ecc_wait_done(struct mtk_ecc *ecc, enum mtk_ecc_operation op)
-+{
-+	int ret;
-+
-+	ret = wait_for_completion_timeout(&ecc->done, msecs_to_jiffies(500));
-+	if (!ret) {
-+		dev_err(ecc->dev, "%s timeout - interrupt did not arrive)\n",
-+			(op == ECC_ENCODE) ? "encoder" : "decoder");
-+		return -ETIMEDOUT;
-+	}
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(mtk_ecc_wait_done);
-+
-+int mtk_ecc_encode(struct mtk_ecc *ecc, struct mtk_ecc_config *config,
-+		   u8 *data, u32 bytes)
-+{
-+	dma_addr_t addr;
-+	u32 len;
-+	int ret;
-+
-+	addr = dma_map_single(ecc->dev, data, bytes, DMA_TO_DEVICE);
-+	ret = dma_mapping_error(ecc->dev, addr);
-+	if (ret) {
-+		dev_err(ecc->dev, "dma mapping error\n");
-+		return -EINVAL;
-+	}
-+
-+	config->op = ECC_ENCODE;
-+	config->addr = addr;
-+	ret = mtk_ecc_enable(ecc, config);
-+	if (ret) {
-+		dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE);
-+		return ret;
-+	}
-+
-+	ret = mtk_ecc_wait_done(ecc, ECC_ENCODE);
-+	if (ret)
-+		goto timeout;
-+
-+	mtk_ecc_wait_idle(ecc, ECC_ENCODE);
-+
-+	/* Program ECC bytes to OOB: per sector oob = FDM + ECC + SPARE */
-+	len = (config->strength * ecc->caps->parity_bits + 7) >> 3;
-+
-+	/* write the parity bytes generated by the ECC back to temp buffer */
-+	__ioread32_copy(ecc->eccdata,
-+			ecc->regs + ecc->caps->ecc_regs[ECC_ENCPAR00],
-+			round_up(len, 4));
-+
-+	/* copy into possibly unaligned OOB region with actual length */
-+	memcpy(data + bytes, ecc->eccdata, len);
-+timeout:
-+
-+	dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE);
-+	mtk_ecc_disable(ecc);
-+
-+	return ret;
-+}
-+EXPORT_SYMBOL(mtk_ecc_encode);
-+
-+void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p)
-+{
-+	const u8 *ecc_strength = ecc->caps->ecc_strength;
-+	int i;
-+
-+	for (i = 0; i < ecc->caps->num_ecc_strength; i++) {
-+		if (*p <= ecc_strength[i]) {
-+			if (!i)
-+				*p = ecc_strength[i];
-+			else if (*p != ecc_strength[i])
-+				*p = ecc_strength[i - 1];
-+			return;
-+		}
-+	}
-+
-+	*p = ecc_strength[ecc->caps->num_ecc_strength - 1];
-+}
-+EXPORT_SYMBOL(mtk_ecc_adjust_strength);
-+
-+unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc)
-+{
-+	return ecc->caps->parity_bits;
-+}
-+EXPORT_SYMBOL(mtk_ecc_get_parity_bits);
-+
-+static const struct mtk_ecc_caps mtk_ecc_caps_mt2701 = {
-+	.err_mask = 0x3f,
-+	.err_shift = 8,
-+	.ecc_strength = ecc_strength_mt2701,
-+	.ecc_regs = mt2701_ecc_regs,
-+	.num_ecc_strength = 20,
-+	.ecc_mode_shift = 5,
-+	.parity_bits = 14,
-+	.pg_irq_sel = 0,
-+};
-+
-+static const struct mtk_ecc_caps mtk_ecc_caps_mt2712 = {
-+	.err_mask = 0x7f,
-+	.err_shift = 8,
-+	.ecc_strength = ecc_strength_mt2712,
-+	.ecc_regs = mt2712_ecc_regs,
-+	.num_ecc_strength = 23,
-+	.ecc_mode_shift = 5,
-+	.parity_bits = 14,
-+	.pg_irq_sel = 1,
-+};
-+
-+static const struct mtk_ecc_caps mtk_ecc_caps_mt7622 = {
-+	.err_mask = 0x1f,
-+	.err_shift = 5,
-+	.ecc_strength = ecc_strength_mt7622,
-+	.ecc_regs = mt7622_ecc_regs,
-+	.num_ecc_strength = 5,
-+	.ecc_mode_shift = 4,
-+	.parity_bits = 13,
-+	.pg_irq_sel = 0,
-+};
-+
-+static const struct of_device_id mtk_ecc_dt_match[] = {
-+	{
-+		.compatible = "mediatek,mt2701-ecc",
-+		.data = &mtk_ecc_caps_mt2701,
-+	}, {
-+		.compatible = "mediatek,mt2712-ecc",
-+		.data = &mtk_ecc_caps_mt2712,
-+	}, {
-+		.compatible = "mediatek,mt7622-ecc",
-+		.data = &mtk_ecc_caps_mt7622,
-+	},
-+	{},
-+};
-+
-+static int mtk_ecc_probe(struct platform_device *pdev)
-+{
-+	struct device *dev = &pdev->dev;
-+	struct mtk_ecc *ecc;
-+	struct resource *res;
-+	u32 max_eccdata_size;
-+	int irq, ret;
-+
-+	ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL);
-+	if (!ecc)
-+		return -ENOMEM;
-+
-+	ecc->caps = of_device_get_match_data(dev);
-+
-+	max_eccdata_size = ecc->caps->num_ecc_strength - 1;
-+	max_eccdata_size = ecc->caps->ecc_strength[max_eccdata_size];
-+	max_eccdata_size = (max_eccdata_size * ecc->caps->parity_bits + 7) >> 3;
-+	max_eccdata_size = round_up(max_eccdata_size, 4);
-+	ecc->eccdata = devm_kzalloc(dev, max_eccdata_size, GFP_KERNEL);
-+	if (!ecc->eccdata)
-+		return -ENOMEM;
-+
-+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	ecc->regs = devm_ioremap_resource(dev, res);
-+	if (IS_ERR(ecc->regs))
-+		return PTR_ERR(ecc->regs);
-+
-+	ecc->clk = devm_clk_get(dev, NULL);
-+	if (IS_ERR(ecc->clk)) {
-+		dev_err(dev, "failed to get clock: %ld\n", PTR_ERR(ecc->clk));
-+		return PTR_ERR(ecc->clk);
-+	}
-+
-+	irq = platform_get_irq(pdev, 0);
-+	if (irq < 0)
-+		return irq;
-+
-+	ret = dma_set_mask(dev, DMA_BIT_MASK(32));
-+	if (ret) {
-+		dev_err(dev, "failed to set DMA mask\n");
-+		return ret;
-+	}
-+
-+	ret = devm_request_irq(dev, irq, mtk_ecc_irq, 0x0, "mtk-ecc", ecc);
-+	if (ret) {
-+		dev_err(dev, "failed to request irq\n");
-+		return -EINVAL;
-+	}
-+
-+	ecc->dev = dev;
-+	mutex_init(&ecc->lock);
-+	platform_set_drvdata(pdev, ecc);
-+	dev_info(dev, "probed\n");
-+
-+	return 0;
-+}
-+
-+#ifdef CONFIG_PM_SLEEP
-+static int mtk_ecc_suspend(struct device *dev)
-+{
-+	struct mtk_ecc *ecc = dev_get_drvdata(dev);
-+
-+	clk_disable_unprepare(ecc->clk);
-+
-+	return 0;
-+}
-+
-+static int mtk_ecc_resume(struct device *dev)
-+{
-+	struct mtk_ecc *ecc = dev_get_drvdata(dev);
-+	int ret;
-+
-+	ret = clk_prepare_enable(ecc->clk);
-+	if (ret) {
-+		dev_err(dev, "failed to enable clk\n");
-+		return ret;
-+	}
-+
-+	return 0;
-+}
-+
-+static SIMPLE_DEV_PM_OPS(mtk_ecc_pm_ops, mtk_ecc_suspend, mtk_ecc_resume);
-+#endif
-+
-+MODULE_DEVICE_TABLE(of, mtk_ecc_dt_match);
-+
-+static struct platform_driver mtk_ecc_driver = {
-+	.probe  = mtk_ecc_probe,
-+	.driver = {
-+		.name  = "mtk-ecc",
-+		.of_match_table = of_match_ptr(mtk_ecc_dt_match),
-+#ifdef CONFIG_PM_SLEEP
-+		.pm = &mtk_ecc_pm_ops,
-+#endif
-+	},
-+};
-+
-+module_platform_driver(mtk_ecc_driver);
-+
-+MODULE_AUTHOR("Xiaolei Li <xiaolei.li@mediatek.com>");
-+MODULE_DESCRIPTION("MTK Nand ECC Driver");
-+MODULE_LICENSE("Dual MIT/GPL");
---- a/drivers/mtd/nand/raw/Kconfig
-+++ b/drivers/mtd/nand/raw/Kconfig
-@@ -360,6 +360,7 @@ config MTD_NAND_QCOM
- 
- config MTD_NAND_MTK
- 	tristate "MTK NAND controller"
-+	depends on MTD_NAND_ECC_MEDIATEK
- 	depends on ARCH_MEDIATEK || COMPILE_TEST
- 	depends on HAS_IOMEM
- 	help
---- a/drivers/mtd/nand/raw/Makefile
-+++ b/drivers/mtd/nand/raw/Makefile
-@@ -48,7 +48,7 @@ obj-$(CONFIG_MTD_NAND_SUNXI)		+= sunxi_n
- obj-$(CONFIG_MTD_NAND_HISI504)	        += hisi504_nand.o
- obj-$(CONFIG_MTD_NAND_BRCMNAND)		+= brcmnand/
- obj-$(CONFIG_MTD_NAND_QCOM)		+= qcom_nandc.o
--obj-$(CONFIG_MTD_NAND_MTK)		+= mtk_ecc.o mtk_nand.o
-+obj-$(CONFIG_MTD_NAND_MTK)		+= mtk_nand.o
- obj-$(CONFIG_MTD_NAND_MXIC)		+= mxic_nand.o
- obj-$(CONFIG_MTD_NAND_TEGRA)		+= tegra_nand.o
- obj-$(CONFIG_MTD_NAND_STM32_FMC2)	+= stm32_fmc2_nand.o
---- a/drivers/mtd/nand/raw/mtk_nand.c
-+++ b/drivers/mtd/nand/raw/mtk_nand.c
-@@ -17,7 +17,7 @@
- #include <linux/iopoll.h>
- #include <linux/of.h>
- #include <linux/of_device.h>
--#include "mtk_ecc.h"
-+#include <linux/mtd/nand-ecc-mtk.h>
- 
- /* NAND controller register definition */
- #define NFI_CNFG		(0x00)
---- a/drivers/mtd/nand/raw/mtk_ecc.h
-+++ /dev/null
-@@ -1,47 +0,0 @@
--/* SPDX-License-Identifier: GPL-2.0 OR MIT */
--/*
-- * MTK SDG1 ECC controller
-- *
-- * Copyright (c) 2016 Mediatek
-- * Authors:	Xiaolei Li		<xiaolei.li@mediatek.com>
-- *		Jorge Ramirez-Ortiz	<jorge.ramirez-ortiz@linaro.org>
-- */
--
--#ifndef __DRIVERS_MTD_NAND_MTK_ECC_H__
--#define __DRIVERS_MTD_NAND_MTK_ECC_H__
--
--#include <linux/types.h>
--
--enum mtk_ecc_mode {ECC_DMA_MODE = 0, ECC_NFI_MODE = 1};
--enum mtk_ecc_operation {ECC_ENCODE, ECC_DECODE};
--
--struct device_node;
--struct mtk_ecc;
--
--struct mtk_ecc_stats {
--	u32 corrected;
--	u32 bitflips;
--	u32 failed;
--};
--
--struct mtk_ecc_config {
--	enum mtk_ecc_operation op;
--	enum mtk_ecc_mode mode;
--	dma_addr_t addr;
--	u32 strength;
--	u32 sectors;
--	u32 len;
--};
--
--int mtk_ecc_encode(struct mtk_ecc *, struct mtk_ecc_config *, u8 *, u32);
--void mtk_ecc_get_stats(struct mtk_ecc *, struct mtk_ecc_stats *, int);
--int mtk_ecc_wait_done(struct mtk_ecc *, enum mtk_ecc_operation);
--int mtk_ecc_enable(struct mtk_ecc *, struct mtk_ecc_config *);
--void mtk_ecc_disable(struct mtk_ecc *);
--void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p);
--unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc);
--
--struct mtk_ecc *of_mtk_ecc_get(struct device_node *);
--void mtk_ecc_release(struct mtk_ecc *);
--
--#endif
---- /dev/null
-+++ b/include/linux/mtd/nand-ecc-mtk.h
-@@ -0,0 +1,47 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/*
-+ * MTK SDG1 ECC controller
-+ *
-+ * Copyright (c) 2016 Mediatek
-+ * Authors:	Xiaolei Li		<xiaolei.li@mediatek.com>
-+ *		Jorge Ramirez-Ortiz	<jorge.ramirez-ortiz@linaro.org>
-+ */
-+
-+#ifndef __DRIVERS_MTD_NAND_MTK_ECC_H__
-+#define __DRIVERS_MTD_NAND_MTK_ECC_H__
-+
-+#include <linux/types.h>
-+
-+enum mtk_ecc_mode {ECC_DMA_MODE = 0, ECC_NFI_MODE = 1};
-+enum mtk_ecc_operation {ECC_ENCODE, ECC_DECODE};
-+
-+struct device_node;
-+struct mtk_ecc;
-+
-+struct mtk_ecc_stats {
-+	u32 corrected;
-+	u32 bitflips;
-+	u32 failed;
-+};
-+
-+struct mtk_ecc_config {
-+	enum mtk_ecc_operation op;
-+	enum mtk_ecc_mode mode;
-+	dma_addr_t addr;
-+	u32 strength;
-+	u32 sectors;
-+	u32 len;
-+};
-+
-+int mtk_ecc_encode(struct mtk_ecc *, struct mtk_ecc_config *, u8 *, u32);
-+void mtk_ecc_get_stats(struct mtk_ecc *, struct mtk_ecc_stats *, int);
-+int mtk_ecc_wait_done(struct mtk_ecc *, enum mtk_ecc_operation);
-+int mtk_ecc_enable(struct mtk_ecc *, struct mtk_ecc_config *);
-+void mtk_ecc_disable(struct mtk_ecc *);
-+void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p);
-+unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc);
-+
-+struct mtk_ecc *of_mtk_ecc_get(struct device_node *);
-+void mtk_ecc_release(struct mtk_ecc *);
-+
-+#endif
diff --git a/target/linux/mediatek/patches-5.15/120-12-v5.19-spi-add-driver-for-MTK-SPI-NAND-Flash-Interface.patch b/target/linux/mediatek/patches-5.15/120-12-v5.19-spi-add-driver-for-MTK-SPI-NAND-Flash-Interface.patch
deleted file mode 100644
index ed209050123b7e..00000000000000
--- a/target/linux/mediatek/patches-5.15/120-12-v5.19-spi-add-driver-for-MTK-SPI-NAND-Flash-Interface.patch
+++ /dev/null
@@ -1,1537 +0,0 @@
-From 8170bafa8936e9fbfdce992932a63bd20eca3bc3 Mon Sep 17 00:00:00 2001
-From: Chuanhong Guo <gch981213@gmail.com>
-Date: Sat, 2 Apr 2022 10:16:11 +0800
-Subject: [PATCH v6 2/5] spi: add driver for MTK SPI NAND Flash Interface
-
-This driver implements support for the SPI-NAND mode of MTK NAND Flash
-Interface as a SPI-MEM controller with pipelined ECC capability.
-
-Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
-Tested-by: Daniel Golle <daniel@makrotopia.org>
----
-Change since v1:
-  fix CI warnings
-
-Changes since v2:
- use streamed DMA api to avoid an extra memory copy during read
- make ECC engine config a per-nand context
- take user-requested ECC strength into account
-
-Change since v3: none
-Changes since v4:
- fix missing OOB write
- print page format with dev_dbg
- replace uint*_t copied from vendor driver with u*
-
-Changes since v5:
- add missing nfi mode register configuration in probe
- fix an off-by-one bug in mtk_snand_mac_io
-
- drivers/spi/Kconfig        |   10 +
- drivers/spi/Makefile       |    1 +
- drivers/spi/spi-mtk-snfi.c | 1470 ++++++++++++++++++++++++++++++++++++
- 3 files changed, 1481 insertions(+)
- create mode 100644 drivers/spi/spi-mtk-snfi.c
-
---- a/drivers/spi/Kconfig
-+++ b/drivers/spi/Kconfig
-@@ -529,6 +529,16 @@ config SPI_MTK_NOR
- 	  SPI interface as well as several SPI NOR specific instructions
- 	  via SPI MEM interface.
- 
-+config SPI_MTK_SNFI
-+	tristate "MediaTek SPI NAND Flash Interface"
-+	depends on ARCH_MEDIATEK || COMPILE_TEST
-+	depends on MTD_NAND_ECC_MEDIATEK
-+	help
-+	  This enables support for SPI-NAND mode on the MediaTek NAND
-+	  Flash Interface found on MediaTek ARM SoCs. This controller
-+	  is implemented as a SPI-MEM controller with pipelined ECC
-+	  capcability.
-+
- config SPI_NPCM_FIU
- 	tristate "Nuvoton NPCM FLASH Interface Unit"
- 	depends on ARCH_NPCM || COMPILE_TEST
---- a/drivers/spi/Makefile
-+++ b/drivers/spi/Makefile
-@@ -71,6 +71,7 @@ obj-$(CONFIG_SPI_MPC52xx)		+= spi-mpc52x
- obj-$(CONFIG_SPI_MT65XX)                += spi-mt65xx.o
- obj-$(CONFIG_SPI_MT7621)		+= spi-mt7621.o
- obj-$(CONFIG_SPI_MTK_NOR)		+= spi-mtk-nor.o
-+obj-$(CONFIG_SPI_MTK_SNFI)		+= spi-mtk-snfi.o
- obj-$(CONFIG_SPI_MXIC)			+= spi-mxic.o
- obj-$(CONFIG_SPI_MXS)			+= spi-mxs.o
- obj-$(CONFIG_SPI_NPCM_FIU)		+= spi-npcm-fiu.o
---- /dev/null
-+++ b/drivers/spi/spi-mtk-snfi.c
-@@ -0,0 +1,1470 @@
-+// SPDX-License-Identifier: GPL-2.0
-+//
-+// Driver for the SPI-NAND mode of Mediatek NAND Flash Interface
-+//
-+// Copyright (c) 2022 Chuanhong Guo <gch981213@gmail.com>
-+//
-+// This driver is based on the SPI-NAND mtd driver from Mediatek SDK:
-+//
-+// Copyright (C) 2020 MediaTek Inc.
-+// Author: Weijie Gao <weijie.gao@mediatek.com>
-+//
-+// This controller organize the page data as several interleaved sectors
-+// like the following: (sizeof(FDM + ECC) = snf->nfi_cfg.spare_size)
-+// +---------+------+------+---------+------+------+-----+
-+// | Sector1 | FDM1 | ECC1 | Sector2 | FDM2 | ECC2 | ... |
-+// +---------+------+------+---------+------+------+-----+
-+// With auto-format turned on, DMA only returns this part:
-+// +---------+---------+-----+
-+// | Sector1 | Sector2 | ... |
-+// +---------+---------+-----+
-+// The FDM data will be filled to the registers, and ECC parity data isn't
-+// accessible.
-+// With auto-format off, all ((Sector+FDM+ECC)*nsectors) will be read over DMA
-+// in it's original order shown in the first table. ECC can't be turned on when
-+// auto-format is off.
-+//
-+// However, Linux SPI-NAND driver expects the data returned as:
-+// +------+-----+
-+// | Page | OOB |
-+// +------+-----+
-+// where the page data is continuously stored instead of interleaved.
-+// So we assume all instructions matching the page_op template between ECC
-+// prepare_io_req and finish_io_req are for page cache r/w.
-+// Here's how this spi-mem driver operates when reading:
-+//  1. Always set snf->autofmt = true in prepare_io_req (even when ECC is off).
-+//  2. Perform page ops and let the controller fill the DMA bounce buffer with
-+//     de-interleaved sector data and set FDM registers.
-+//  3. Return the data as:
-+//     +---------+---------+-----+------+------+-----+
-+//     | Sector1 | Sector2 | ... | FDM1 | FDM2 | ... |
-+//     +---------+---------+-----+------+------+-----+
-+//  4. For other matching spi_mem ops outside a prepare/finish_io_req pair,
-+//     read the data with auto-format off into the bounce buffer and copy
-+//     needed data to the buffer specified in the request.
-+//
-+// Write requests operates in a similar manner.
-+// As a limitation of this strategy, we won't be able to access any ECC parity
-+// data at all in Linux.
-+//
-+// Here's the bad block mark situation on MTK chips:
-+// In older chips like mt7622, MTK uses the first FDM byte in the first sector
-+// as the bad block mark. After de-interleaving, this byte appears at [pagesize]
-+// in the returned data, which is the BBM position expected by kernel. However,
-+// the conventional bad block mark is the first byte of the OOB, which is part
-+// of the last sector data in the interleaved layout. Instead of fixing their
-+// hardware, MTK decided to address this inconsistency in software. On these
-+// later chips, the BootROM expects the following:
-+// 1. The [pagesize] byte on a nand page is used as BBM, which will appear at
-+//    (page_size - (nsectors - 1) * spare_size) in the DMA buffer.
-+// 2. The original byte stored at that position in the DMA buffer will be stored
-+//    as the first byte of the FDM section in the last sector.
-+// We can't disagree with the BootROM, so after de-interleaving, we need to
-+// perform the following swaps in read:
-+// 1. Store the BBM at [page_size - (nsectors - 1) * spare_size] to [page_size],
-+//    which is the expected BBM position by kernel.
-+// 2. Store the page data byte at [pagesize + (nsectors-1) * fdm] back to
-+//    [page_size - (nsectors - 1) * spare_size]
-+// Similarly, when writing, we need to perform swaps in the other direction.
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/init.h>
-+#include <linux/device.h>
-+#include <linux/mutex.h>
-+#include <linux/clk.h>
-+#include <linux/interrupt.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/iopoll.h>
-+#include <linux/of_platform.h>
-+#include <linux/mtd/nand-ecc-mtk.h>
-+#include <linux/spi/spi.h>
-+#include <linux/spi/spi-mem.h>
-+#include <linux/mtd/nand.h>
-+
-+// NFI registers
-+#define NFI_CNFG 0x000
-+#define CNFG_OP_MODE_S 12
-+#define CNFG_OP_MODE_CUST 6
-+#define CNFG_OP_MODE_PROGRAM 3
-+#define CNFG_AUTO_FMT_EN BIT(9)
-+#define CNFG_HW_ECC_EN BIT(8)
-+#define CNFG_DMA_BURST_EN BIT(2)
-+#define CNFG_READ_MODE BIT(1)
-+#define CNFG_DMA_MODE BIT(0)
-+
-+#define NFI_PAGEFMT 0x0004
-+#define NFI_SPARE_SIZE_LS_S 16
-+#define NFI_FDM_ECC_NUM_S 12
-+#define NFI_FDM_NUM_S 8
-+#define NFI_SPARE_SIZE_S 4
-+#define NFI_SEC_SEL_512 BIT(2)
-+#define NFI_PAGE_SIZE_S 0
-+#define NFI_PAGE_SIZE_512_2K 0
-+#define NFI_PAGE_SIZE_2K_4K 1
-+#define NFI_PAGE_SIZE_4K_8K 2
-+#define NFI_PAGE_SIZE_8K_16K 3
-+
-+#define NFI_CON 0x008
-+#define CON_SEC_NUM_S 12
-+#define CON_BWR BIT(9)
-+#define CON_BRD BIT(8)
-+#define CON_NFI_RST BIT(1)
-+#define CON_FIFO_FLUSH BIT(0)
-+
-+#define NFI_INTR_EN 0x010
-+#define NFI_INTR_STA 0x014
-+#define NFI_IRQ_INTR_EN BIT(31)
-+#define NFI_IRQ_CUS_READ BIT(8)
-+#define NFI_IRQ_CUS_PG BIT(7)
-+
-+#define NFI_CMD 0x020
-+#define NFI_CMD_DUMMY_READ 0x00
-+#define NFI_CMD_DUMMY_WRITE 0x80
-+
-+#define NFI_STRDATA 0x040
-+#define STR_DATA BIT(0)
-+
-+#define NFI_STA 0x060
-+#define NFI_NAND_FSM GENMASK(28, 24)
-+#define NFI_FSM GENMASK(19, 16)
-+#define READ_EMPTY BIT(12)
-+
-+#define NFI_FIFOSTA 0x064
-+#define FIFO_WR_REMAIN_S 8
-+#define FIFO_RD_REMAIN_S 0
-+
-+#define NFI_ADDRCNTR 0x070
-+#define SEC_CNTR GENMASK(16, 12)
-+#define SEC_CNTR_S 12
-+#define NFI_SEC_CNTR(val) (((val)&SEC_CNTR) >> SEC_CNTR_S)
-+
-+#define NFI_STRADDR 0x080
-+
-+#define NFI_BYTELEN 0x084
-+#define BUS_SEC_CNTR(val) (((val)&SEC_CNTR) >> SEC_CNTR_S)
-+
-+#define NFI_FDM0L 0x0a0
-+#define NFI_FDM0M 0x0a4
-+#define NFI_FDML(n) (NFI_FDM0L + (n)*8)
-+#define NFI_FDMM(n) (NFI_FDM0M + (n)*8)
-+
-+#define NFI_DEBUG_CON1 0x220
-+#define WBUF_EN BIT(2)
-+
-+#define NFI_MASTERSTA 0x224
-+#define MAS_ADDR GENMASK(11, 9)
-+#define MAS_RD GENMASK(8, 6)
-+#define MAS_WR GENMASK(5, 3)
-+#define MAS_RDDLY GENMASK(2, 0)
-+#define NFI_MASTERSTA_MASK_7622 (MAS_ADDR | MAS_RD | MAS_WR | MAS_RDDLY)
-+
-+// SNFI registers
-+#define SNF_MAC_CTL 0x500
-+#define MAC_XIO_SEL BIT(4)
-+#define SF_MAC_EN BIT(3)
-+#define SF_TRIG BIT(2)
-+#define WIP_READY BIT(1)
-+#define WIP BIT(0)
-+
-+#define SNF_MAC_OUTL 0x504
-+#define SNF_MAC_INL 0x508
-+
-+#define SNF_RD_CTL2 0x510
-+#define DATA_READ_DUMMY_S 8
-+#define DATA_READ_MAX_DUMMY 0xf
-+#define DATA_READ_CMD_S 0
-+
-+#define SNF_RD_CTL3 0x514
-+
-+#define SNF_PG_CTL1 0x524
-+#define PG_LOAD_CMD_S 8
-+
-+#define SNF_PG_CTL2 0x528
-+
-+#define SNF_MISC_CTL 0x538
-+#define SW_RST BIT(28)
-+#define FIFO_RD_LTC_S 25
-+#define PG_LOAD_X4_EN BIT(20)
-+#define DATA_READ_MODE_S 16
-+#define DATA_READ_MODE GENMASK(18, 16)
-+#define DATA_READ_MODE_X1 0
-+#define DATA_READ_MODE_X2 1
-+#define DATA_READ_MODE_X4 2
-+#define DATA_READ_MODE_DUAL 5
-+#define DATA_READ_MODE_QUAD 6
-+#define PG_LOAD_CUSTOM_EN BIT(7)
-+#define DATARD_CUSTOM_EN BIT(6)
-+#define CS_DESELECT_CYC_S 0
-+
-+#define SNF_MISC_CTL2 0x53c
-+#define PROGRAM_LOAD_BYTE_NUM_S 16
-+#define READ_DATA_BYTE_NUM_S 11
-+
-+#define SNF_DLY_CTL3 0x548
-+#define SFCK_SAM_DLY_S 0
-+
-+#define SNF_STA_CTL1 0x550
-+#define CUS_PG_DONE BIT(28)
-+#define CUS_READ_DONE BIT(27)
-+#define SPI_STATE_S 0
-+#define SPI_STATE GENMASK(3, 0)
-+
-+#define SNF_CFG 0x55c
-+#define SPI_MODE BIT(0)
-+
-+#define SNF_GPRAM 0x800
-+#define SNF_GPRAM_SIZE 0xa0
-+
-+#define SNFI_POLL_INTERVAL 1000000
-+
-+static const u8 mt7622_spare_sizes[] = { 16, 26, 27, 28 };
-+
-+struct mtk_snand_caps {
-+	u16 sector_size;
-+	u16 max_sectors;
-+	u16 fdm_size;
-+	u16 fdm_ecc_size;
-+	u16 fifo_size;
-+
-+	bool bbm_swap;
-+	bool empty_page_check;
-+	u32 mastersta_mask;
-+
-+	const u8 *spare_sizes;
-+	u32 num_spare_size;
-+};
-+
-+static const struct mtk_snand_caps mt7622_snand_caps = {
-+	.sector_size = 512,
-+	.max_sectors = 8,
-+	.fdm_size = 8,
-+	.fdm_ecc_size = 1,
-+	.fifo_size = 32,
-+	.bbm_swap = false,
-+	.empty_page_check = false,
-+	.mastersta_mask = NFI_MASTERSTA_MASK_7622,
-+	.spare_sizes = mt7622_spare_sizes,
-+	.num_spare_size = ARRAY_SIZE(mt7622_spare_sizes)
-+};
-+
-+static const struct mtk_snand_caps mt7629_snand_caps = {
-+	.sector_size = 512,
-+	.max_sectors = 8,
-+	.fdm_size = 8,
-+	.fdm_ecc_size = 1,
-+	.fifo_size = 32,
-+	.bbm_swap = true,
-+	.empty_page_check = false,
-+	.mastersta_mask = NFI_MASTERSTA_MASK_7622,
-+	.spare_sizes = mt7622_spare_sizes,
-+	.num_spare_size = ARRAY_SIZE(mt7622_spare_sizes)
-+};
-+
-+struct mtk_snand_conf {
-+	size_t page_size;
-+	size_t oob_size;
-+	u8 nsectors;
-+	u8 spare_size;
-+};
-+
-+struct mtk_snand {
-+	struct spi_controller *ctlr;
-+	struct device *dev;
-+	struct clk *nfi_clk;
-+	struct clk *pad_clk;
-+	void __iomem *nfi_base;
-+	int irq;
-+	struct completion op_done;
-+	const struct mtk_snand_caps *caps;
-+	struct mtk_ecc_config *ecc_cfg;
-+	struct mtk_ecc *ecc;
-+	struct mtk_snand_conf nfi_cfg;
-+	struct mtk_ecc_stats ecc_stats;
-+	struct nand_ecc_engine ecc_eng;
-+	bool autofmt;
-+	u8 *buf;
-+	size_t buf_len;
-+};
-+
-+static struct mtk_snand *nand_to_mtk_snand(struct nand_device *nand)
-+{
-+	struct nand_ecc_engine *eng = nand->ecc.engine;
-+
-+	return container_of(eng, struct mtk_snand, ecc_eng);
-+}
-+
-+static inline int snand_prepare_bouncebuf(struct mtk_snand *snf, size_t size)
-+{
-+	if (snf->buf_len >= size)
-+		return 0;
-+	kfree(snf->buf);
-+	snf->buf = kmalloc(size, GFP_KERNEL);
-+	if (!snf->buf)
-+		return -ENOMEM;
-+	snf->buf_len = size;
-+	memset(snf->buf, 0xff, snf->buf_len);
-+	return 0;
-+}
-+
-+static inline u32 nfi_read32(struct mtk_snand *snf, u32 reg)
-+{
-+	return readl(snf->nfi_base + reg);
-+}
-+
-+static inline void nfi_write32(struct mtk_snand *snf, u32 reg, u32 val)
-+{
-+	writel(val, snf->nfi_base + reg);
-+}
-+
-+static inline void nfi_write16(struct mtk_snand *snf, u32 reg, u16 val)
-+{
-+	writew(val, snf->nfi_base + reg);
-+}
-+
-+static inline void nfi_rmw32(struct mtk_snand *snf, u32 reg, u32 clr, u32 set)
-+{
-+	u32 val;
-+
-+	val = readl(snf->nfi_base + reg);
-+	val &= ~clr;
-+	val |= set;
-+	writel(val, snf->nfi_base + reg);
-+}
-+
-+static void nfi_read_data(struct mtk_snand *snf, u32 reg, u8 *data, u32 len)
-+{
-+	u32 i, val = 0, es = sizeof(u32);
-+
-+	for (i = reg; i < reg + len; i++) {
-+		if (i == reg || i % es == 0)
-+			val = nfi_read32(snf, i & ~(es - 1));
-+
-+		*data++ = (u8)(val >> (8 * (i % es)));
-+	}
-+}
-+
-+static int mtk_nfi_reset(struct mtk_snand *snf)
-+{
-+	u32 val, fifo_mask;
-+	int ret;
-+
-+	nfi_write32(snf, NFI_CON, CON_FIFO_FLUSH | CON_NFI_RST);
-+
-+	ret = readw_poll_timeout(snf->nfi_base + NFI_MASTERSTA, val,
-+				 !(val & snf->caps->mastersta_mask), 0,
-+				 SNFI_POLL_INTERVAL);
-+	if (ret) {
-+		dev_err(snf->dev, "NFI master is still busy after reset\n");
-+		return ret;
-+	}
-+
-+	ret = readl_poll_timeout(snf->nfi_base + NFI_STA, val,
-+				 !(val & (NFI_FSM | NFI_NAND_FSM)), 0,
-+				 SNFI_POLL_INTERVAL);
-+	if (ret) {
-+		dev_err(snf->dev, "Failed to reset NFI\n");
-+		return ret;
-+	}
-+
-+	fifo_mask = ((snf->caps->fifo_size - 1) << FIFO_RD_REMAIN_S) |
-+		    ((snf->caps->fifo_size - 1) << FIFO_WR_REMAIN_S);
-+	ret = readw_poll_timeout(snf->nfi_base + NFI_FIFOSTA, val,
-+				 !(val & fifo_mask), 0, SNFI_POLL_INTERVAL);
-+	if (ret) {
-+		dev_err(snf->dev, "NFI FIFOs are not empty\n");
-+		return ret;
-+	}
-+
-+	return 0;
-+}
-+
-+static int mtk_snand_mac_reset(struct mtk_snand *snf)
-+{
-+	int ret;
-+	u32 val;
-+
-+	nfi_rmw32(snf, SNF_MISC_CTL, 0, SW_RST);
-+
-+	ret = readl_poll_timeout(snf->nfi_base + SNF_STA_CTL1, val,
-+				 !(val & SPI_STATE), 0, SNFI_POLL_INTERVAL);
-+	if (ret)
-+		dev_err(snf->dev, "Failed to reset SNFI MAC\n");
-+
-+	nfi_write32(snf, SNF_MISC_CTL,
-+		    (2 << FIFO_RD_LTC_S) | (10 << CS_DESELECT_CYC_S));
-+
-+	return ret;
-+}
-+
-+static int mtk_snand_mac_trigger(struct mtk_snand *snf, u32 outlen, u32 inlen)
-+{
-+	int ret;
-+	u32 val;
-+
-+	nfi_write32(snf, SNF_MAC_CTL, SF_MAC_EN);
-+	nfi_write32(snf, SNF_MAC_OUTL, outlen);
-+	nfi_write32(snf, SNF_MAC_INL, inlen);
-+
-+	nfi_write32(snf, SNF_MAC_CTL, SF_MAC_EN | SF_TRIG);
-+
-+	ret = readl_poll_timeout(snf->nfi_base + SNF_MAC_CTL, val,
-+				 val & WIP_READY, 0, SNFI_POLL_INTERVAL);
-+	if (ret) {
-+		dev_err(snf->dev, "Timed out waiting for WIP_READY\n");
-+		goto cleanup;
-+	}
-+
-+	ret = readl_poll_timeout(snf->nfi_base + SNF_MAC_CTL, val, !(val & WIP),
-+				 0, SNFI_POLL_INTERVAL);
-+	if (ret)
-+		dev_err(snf->dev, "Timed out waiting for WIP cleared\n");
-+
-+cleanup:
-+	nfi_write32(snf, SNF_MAC_CTL, 0);
-+
-+	return ret;
-+}
-+
-+static int mtk_snand_mac_io(struct mtk_snand *snf, const struct spi_mem_op *op)
-+{
-+	u32 rx_len = 0;
-+	u32 reg_offs = 0;
-+	u32 val = 0;
-+	const u8 *tx_buf = NULL;
-+	u8 *rx_buf = NULL;
-+	int i, ret;
-+	u8 b;
-+
-+	if (op->data.dir == SPI_MEM_DATA_IN) {
-+		rx_len = op->data.nbytes;
-+		rx_buf = op->data.buf.in;
-+	} else {
-+		tx_buf = op->data.buf.out;
-+	}
-+
-+	mtk_snand_mac_reset(snf);
-+
-+	for (i = 0; i < op->cmd.nbytes; i++, reg_offs++) {
-+		b = (op->cmd.opcode >> ((op->cmd.nbytes - i - 1) * 8)) & 0xff;
-+		val |= b << (8 * (reg_offs % 4));
-+		if (reg_offs % 4 == 3) {
-+			nfi_write32(snf, SNF_GPRAM + reg_offs - 3, val);
-+			val = 0;
-+		}
-+	}
-+
-+	for (i = 0; i < op->addr.nbytes; i++, reg_offs++) {
-+		b = (op->addr.val >> ((op->addr.nbytes - i - 1) * 8)) & 0xff;
-+		val |= b << (8 * (reg_offs % 4));
-+		if (reg_offs % 4 == 3) {
-+			nfi_write32(snf, SNF_GPRAM + reg_offs - 3, val);
-+			val = 0;
-+		}
-+	}
-+
-+	for (i = 0; i < op->dummy.nbytes; i++, reg_offs++) {
-+		if (reg_offs % 4 == 3) {
-+			nfi_write32(snf, SNF_GPRAM + reg_offs - 3, val);
-+			val = 0;
-+		}
-+	}
-+
-+	if (op->data.dir == SPI_MEM_DATA_OUT) {
-+		for (i = 0; i < op->data.nbytes; i++, reg_offs++) {
-+			val |= tx_buf[i] << (8 * (reg_offs % 4));
-+			if (reg_offs % 4 == 3) {
-+				nfi_write32(snf, SNF_GPRAM + reg_offs - 3, val);
-+				val = 0;
-+			}
-+		}
-+	}
-+
-+	if (reg_offs % 4)
-+		nfi_write32(snf, SNF_GPRAM + (reg_offs & ~3), val);
-+
-+	for (i = 0; i < reg_offs; i += 4)
-+		dev_dbg(snf->dev, "%d: %08X", i,
-+			nfi_read32(snf, SNF_GPRAM + i));
-+
-+	dev_dbg(snf->dev, "SNF TX: %u RX: %u", reg_offs, rx_len);
-+
-+	ret = mtk_snand_mac_trigger(snf, reg_offs, rx_len);
-+	if (ret)
-+		return ret;
-+
-+	if (!rx_len)
-+		return 0;
-+
-+	nfi_read_data(snf, SNF_GPRAM + reg_offs, rx_buf, rx_len);
-+	return 0;
-+}
-+
-+static int mtk_snand_setup_pagefmt(struct mtk_snand *snf, u32 page_size,
-+				   u32 oob_size)
-+{
-+	int spare_idx = -1;
-+	u32 spare_size, spare_size_shift, pagesize_idx;
-+	u32 sector_size_512;
-+	u8 nsectors;
-+	int i;
-+
-+	// skip if it's already configured as required.
-+	if (snf->nfi_cfg.page_size == page_size &&
-+	    snf->nfi_cfg.oob_size == oob_size)
-+		return 0;
-+
-+	nsectors = page_size / snf->caps->sector_size;
-+	if (nsectors > snf->caps->max_sectors) {
-+		dev_err(snf->dev, "too many sectors required.\n");
-+		goto err;
-+	}
-+
-+	if (snf->caps->sector_size == 512) {
-+		sector_size_512 = NFI_SEC_SEL_512;
-+		spare_size_shift = NFI_SPARE_SIZE_S;
-+	} else {
-+		sector_size_512 = 0;
-+		spare_size_shift = NFI_SPARE_SIZE_LS_S;
-+	}
-+
-+	switch (page_size) {
-+	case SZ_512:
-+		pagesize_idx = NFI_PAGE_SIZE_512_2K;
-+		break;
-+	case SZ_2K:
-+		if (snf->caps->sector_size == 512)
-+			pagesize_idx = NFI_PAGE_SIZE_2K_4K;
-+		else
-+			pagesize_idx = NFI_PAGE_SIZE_512_2K;
-+		break;
-+	case SZ_4K:
-+		if (snf->caps->sector_size == 512)
-+			pagesize_idx = NFI_PAGE_SIZE_4K_8K;
-+		else
-+			pagesize_idx = NFI_PAGE_SIZE_2K_4K;
-+		break;
-+	case SZ_8K:
-+		if (snf->caps->sector_size == 512)
-+			pagesize_idx = NFI_PAGE_SIZE_8K_16K;
-+		else
-+			pagesize_idx = NFI_PAGE_SIZE_4K_8K;
-+		break;
-+	case SZ_16K:
-+		pagesize_idx = NFI_PAGE_SIZE_8K_16K;
-+		break;
-+	default:
-+		dev_err(snf->dev, "unsupported page size.\n");
-+		goto err;
-+	}
-+
-+	spare_size = oob_size / nsectors;
-+	// If we're using the 1KB sector size, HW will automatically double the
-+	// spare size. We should only use half of the value in this case.
-+	if (snf->caps->sector_size == 1024)
-+		spare_size /= 2;
-+
-+	for (i = snf->caps->num_spare_size - 1; i >= 0; i--) {
-+		if (snf->caps->spare_sizes[i] <= spare_size) {
-+			spare_size = snf->caps->spare_sizes[i];
-+			if (snf->caps->sector_size == 1024)
-+				spare_size *= 2;
-+			spare_idx = i;
-+			break;
-+		}
-+	}
-+
-+	if (spare_idx < 0) {
-+		dev_err(snf->dev, "unsupported spare size: %u\n", spare_size);
-+		goto err;
-+	}
-+
-+	nfi_write32(snf, NFI_PAGEFMT,
-+		    (snf->caps->fdm_ecc_size << NFI_FDM_ECC_NUM_S) |
-+			    (snf->caps->fdm_size << NFI_FDM_NUM_S) |
-+			    (spare_idx << spare_size_shift) |
-+			    (pagesize_idx << NFI_PAGE_SIZE_S) |
-+			    sector_size_512);
-+
-+	snf->nfi_cfg.page_size = page_size;
-+	snf->nfi_cfg.oob_size = oob_size;
-+	snf->nfi_cfg.nsectors = nsectors;
-+	snf->nfi_cfg.spare_size = spare_size;
-+
-+	dev_dbg(snf->dev, "page format: (%u + %u) * %u\n",
-+		snf->caps->sector_size, spare_size, nsectors);
-+	return snand_prepare_bouncebuf(snf, page_size + oob_size);
-+err:
-+	dev_err(snf->dev, "page size %u + %u is not supported\n", page_size,
-+		oob_size);
-+	return -EOPNOTSUPP;
-+}
-+
-+static int mtk_snand_ooblayout_ecc(struct mtd_info *mtd, int section,
-+				   struct mtd_oob_region *oobecc)
-+{
-+	// ECC area is not accessible
-+	return -ERANGE;
-+}
-+
-+static int mtk_snand_ooblayout_free(struct mtd_info *mtd, int section,
-+				    struct mtd_oob_region *oobfree)
-+{
-+	struct nand_device *nand = mtd_to_nanddev(mtd);
-+	struct mtk_snand *ms = nand_to_mtk_snand(nand);
-+
-+	if (section >= ms->nfi_cfg.nsectors)
-+		return -ERANGE;
-+
-+	oobfree->length = ms->caps->fdm_size - 1;
-+	oobfree->offset = section * ms->caps->fdm_size + 1;
-+	return 0;
-+}
-+
-+static const struct mtd_ooblayout_ops mtk_snand_ooblayout = {
-+	.ecc = mtk_snand_ooblayout_ecc,
-+	.free = mtk_snand_ooblayout_free,
-+};
-+
-+static int mtk_snand_ecc_init_ctx(struct nand_device *nand)
-+{
-+	struct mtk_snand *snf = nand_to_mtk_snand(nand);
-+	struct nand_ecc_props *conf = &nand->ecc.ctx.conf;
-+	struct nand_ecc_props *reqs = &nand->ecc.requirements;
-+	struct nand_ecc_props *user = &nand->ecc.user_conf;
-+	struct mtd_info *mtd = nanddev_to_mtd(nand);
-+	int step_size = 0, strength = 0, desired_correction = 0, steps;
-+	bool ecc_user = false;
-+	int ret;
-+	u32 parity_bits, max_ecc_bytes;
-+	struct mtk_ecc_config *ecc_cfg;
-+
-+	ret = mtk_snand_setup_pagefmt(snf, nand->memorg.pagesize,
-+				      nand->memorg.oobsize);
-+	if (ret)
-+		return ret;
-+
-+	ecc_cfg = kzalloc(sizeof(*ecc_cfg), GFP_KERNEL);
-+	if (!ecc_cfg)
-+		return -ENOMEM;
-+
-+	nand->ecc.ctx.priv = ecc_cfg;
-+
-+	if (user->step_size && user->strength) {
-+		step_size = user->step_size;
-+		strength = user->strength;
-+		ecc_user = true;
-+	} else if (reqs->step_size && reqs->strength) {
-+		step_size = reqs->step_size;
-+		strength = reqs->strength;
-+	}
-+
-+	if (step_size && strength) {
-+		steps = mtd->writesize / step_size;
-+		desired_correction = steps * strength;
-+		strength = desired_correction / snf->nfi_cfg.nsectors;
-+	}
-+
-+	ecc_cfg->mode = ECC_NFI_MODE;
-+	ecc_cfg->sectors = snf->nfi_cfg.nsectors;
-+	ecc_cfg->len = snf->caps->sector_size + snf->caps->fdm_ecc_size;
-+
-+	// calculate the max possible strength under current page format
-+	parity_bits = mtk_ecc_get_parity_bits(snf->ecc);
-+	max_ecc_bytes = snf->nfi_cfg.spare_size - snf->caps->fdm_size;
-+	ecc_cfg->strength = max_ecc_bytes * 8 / parity_bits;
-+	mtk_ecc_adjust_strength(snf->ecc, &ecc_cfg->strength);
-+
-+	// if there's a user requested strength, find the minimum strength that
-+	// meets the requirement. Otherwise use the maximum strength which is
-+	// expected by BootROM.
-+	if (ecc_user && strength) {
-+		u32 s_next = ecc_cfg->strength - 1;
-+
-+		while (1) {
-+			mtk_ecc_adjust_strength(snf->ecc, &s_next);
-+			if (s_next >= ecc_cfg->strength)
-+				break;
-+			if (s_next < strength)
-+				break;
-+			s_next = ecc_cfg->strength - 1;
-+		}
-+	}
-+
-+	mtd_set_ooblayout(mtd, &mtk_snand_ooblayout);
-+
-+	conf->step_size = snf->caps->sector_size;
-+	conf->strength = ecc_cfg->strength;
-+
-+	if (ecc_cfg->strength < strength)
-+		dev_warn(snf->dev, "unable to fulfill ECC of %u bits.\n",
-+			 strength);
-+	dev_info(snf->dev, "ECC strength: %u bits per %u bytes\n",
-+		 ecc_cfg->strength, snf->caps->sector_size);
-+
-+	return 0;
-+}
-+
-+static void mtk_snand_ecc_cleanup_ctx(struct nand_device *nand)
-+{
-+	struct mtk_ecc_config *ecc_cfg = nand_to_ecc_ctx(nand);
-+
-+	kfree(ecc_cfg);
-+}
-+
-+static int mtk_snand_ecc_prepare_io_req(struct nand_device *nand,
-+					struct nand_page_io_req *req)
-+{
-+	struct mtk_snand *snf = nand_to_mtk_snand(nand);
-+	struct mtk_ecc_config *ecc_cfg = nand_to_ecc_ctx(nand);
-+	int ret;
-+
-+	ret = mtk_snand_setup_pagefmt(snf, nand->memorg.pagesize,
-+				      nand->memorg.oobsize);
-+	if (ret)
-+		return ret;
-+	snf->autofmt = true;
-+	snf->ecc_cfg = ecc_cfg;
-+	return 0;
-+}
-+
-+static int mtk_snand_ecc_finish_io_req(struct nand_device *nand,
-+				       struct nand_page_io_req *req)
-+{
-+	struct mtk_snand *snf = nand_to_mtk_snand(nand);
-+	struct mtd_info *mtd = nanddev_to_mtd(nand);
-+
-+	snf->ecc_cfg = NULL;
-+	snf->autofmt = false;
-+	if ((req->mode == MTD_OPS_RAW) || (req->type != NAND_PAGE_READ))
-+		return 0;
-+
-+	if (snf->ecc_stats.failed)
-+		mtd->ecc_stats.failed += snf->ecc_stats.failed;
-+	mtd->ecc_stats.corrected += snf->ecc_stats.corrected;
-+	return snf->ecc_stats.failed ? -EBADMSG : snf->ecc_stats.bitflips;
-+}
-+
-+static struct nand_ecc_engine_ops mtk_snfi_ecc_engine_ops = {
-+	.init_ctx = mtk_snand_ecc_init_ctx,
-+	.cleanup_ctx = mtk_snand_ecc_cleanup_ctx,
-+	.prepare_io_req = mtk_snand_ecc_prepare_io_req,
-+	.finish_io_req = mtk_snand_ecc_finish_io_req,
-+};
-+
-+static void mtk_snand_read_fdm(struct mtk_snand *snf, u8 *buf)
-+{
-+	u32 vall, valm;
-+	u8 *oobptr = buf;
-+	int i, j;
-+
-+	for (i = 0; i < snf->nfi_cfg.nsectors; i++) {
-+		vall = nfi_read32(snf, NFI_FDML(i));
-+		valm = nfi_read32(snf, NFI_FDMM(i));
-+
-+		for (j = 0; j < snf->caps->fdm_size; j++)
-+			oobptr[j] = (j >= 4 ? valm : vall) >> ((j % 4) * 8);
-+
-+		oobptr += snf->caps->fdm_size;
-+	}
-+}
-+
-+static void mtk_snand_write_fdm(struct mtk_snand *snf, const u8 *buf)
-+{
-+	u32 fdm_size = snf->caps->fdm_size;
-+	const u8 *oobptr = buf;
-+	u32 vall, valm;
-+	int i, j;
-+
-+	for (i = 0; i < snf->nfi_cfg.nsectors; i++) {
-+		vall = 0;
-+		valm = 0;
-+
-+		for (j = 0; j < 8; j++) {
-+			if (j < 4)
-+				vall |= (j < fdm_size ? oobptr[j] : 0xff)
-+					<< (j * 8);
-+			else
-+				valm |= (j < fdm_size ? oobptr[j] : 0xff)
-+					<< ((j - 4) * 8);
-+		}
-+
-+		nfi_write32(snf, NFI_FDML(i), vall);
-+		nfi_write32(snf, NFI_FDMM(i), valm);
-+
-+		oobptr += fdm_size;
-+	}
-+}
-+
-+static void mtk_snand_bm_swap(struct mtk_snand *snf, u8 *buf)
-+{
-+	u32 buf_bbm_pos, fdm_bbm_pos;
-+
-+	if (!snf->caps->bbm_swap || snf->nfi_cfg.nsectors == 1)
-+		return;
-+
-+	// swap [pagesize] byte on nand with the first fdm byte
-+	// in the last sector.
-+	buf_bbm_pos = snf->nfi_cfg.page_size -
-+		      (snf->nfi_cfg.nsectors - 1) * snf->nfi_cfg.spare_size;
-+	fdm_bbm_pos = snf->nfi_cfg.page_size +
-+		      (snf->nfi_cfg.nsectors - 1) * snf->caps->fdm_size;
-+
-+	swap(snf->buf[fdm_bbm_pos], buf[buf_bbm_pos]);
-+}
-+
-+static void mtk_snand_fdm_bm_swap(struct mtk_snand *snf)
-+{
-+	u32 fdm_bbm_pos1, fdm_bbm_pos2;
-+
-+	if (!snf->caps->bbm_swap || snf->nfi_cfg.nsectors == 1)
-+		return;
-+
-+	// swap the first fdm byte in the first and the last sector.
-+	fdm_bbm_pos1 = snf->nfi_cfg.page_size;
-+	fdm_bbm_pos2 = snf->nfi_cfg.page_size +
-+		       (snf->nfi_cfg.nsectors - 1) * snf->caps->fdm_size;
-+	swap(snf->buf[fdm_bbm_pos1], snf->buf[fdm_bbm_pos2]);
-+}
-+
-+static int mtk_snand_read_page_cache(struct mtk_snand *snf,
-+				     const struct spi_mem_op *op)
-+{
-+	u8 *buf = snf->buf;
-+	u8 *buf_fdm = buf + snf->nfi_cfg.page_size;
-+	// the address part to be sent by the controller
-+	u32 op_addr = op->addr.val;
-+	// where to start copying data from bounce buffer
-+	u32 rd_offset = 0;
-+	u32 dummy_clk = (op->dummy.nbytes * BITS_PER_BYTE / op->dummy.buswidth);
-+	u32 op_mode = 0;
-+	u32 dma_len = snf->buf_len;
-+	int ret = 0;
-+	u32 rd_mode, rd_bytes, val;
-+	dma_addr_t buf_dma;
-+
-+	if (snf->autofmt) {
-+		u32 last_bit;
-+		u32 mask;
-+
-+		dma_len = snf->nfi_cfg.page_size;
-+		op_mode = CNFG_AUTO_FMT_EN;
-+		if (op->data.ecc)
-+			op_mode |= CNFG_HW_ECC_EN;
-+		// extract the plane bit:
-+		// Find the highest bit set in (pagesize+oobsize).
-+		// Bits higher than that in op->addr are kept and sent over SPI
-+		// Lower bits are used as an offset for copying data from DMA
-+		// bounce buffer.
-+		last_bit = fls(snf->nfi_cfg.page_size + snf->nfi_cfg.oob_size);
-+		mask = (1 << last_bit) - 1;
-+		rd_offset = op_addr & mask;
-+		op_addr &= ~mask;
-+
-+		// check if we can dma to the caller memory
-+		if (rd_offset == 0 && op->data.nbytes >= snf->nfi_cfg.page_size)
-+			buf = op->data.buf.in;
-+	}
-+	mtk_snand_mac_reset(snf);
-+	mtk_nfi_reset(snf);
-+
-+	// command and dummy cycles
-+	nfi_write32(snf, SNF_RD_CTL2,
-+		    (dummy_clk << DATA_READ_DUMMY_S) |
-+			    (op->cmd.opcode << DATA_READ_CMD_S));
-+
-+	// read address
-+	nfi_write32(snf, SNF_RD_CTL3, op_addr);
-+
-+	// Set read op_mode
-+	if (op->data.buswidth == 4)
-+		rd_mode = op->addr.buswidth == 4 ? DATA_READ_MODE_QUAD :
-+						   DATA_READ_MODE_X4;
-+	else if (op->data.buswidth == 2)
-+		rd_mode = op->addr.buswidth == 2 ? DATA_READ_MODE_DUAL :
-+						   DATA_READ_MODE_X2;
-+	else
-+		rd_mode = DATA_READ_MODE_X1;
-+	rd_mode <<= DATA_READ_MODE_S;
-+	nfi_rmw32(snf, SNF_MISC_CTL, DATA_READ_MODE,
-+		  rd_mode | DATARD_CUSTOM_EN);
-+
-+	// Set bytes to read
-+	rd_bytes = (snf->nfi_cfg.spare_size + snf->caps->sector_size) *
-+		   snf->nfi_cfg.nsectors;
-+	nfi_write32(snf, SNF_MISC_CTL2,
-+		    (rd_bytes << PROGRAM_LOAD_BYTE_NUM_S) | rd_bytes);
-+
-+	// NFI read prepare
-+	nfi_write16(snf, NFI_CNFG,
-+		    (CNFG_OP_MODE_CUST << CNFG_OP_MODE_S) | CNFG_DMA_BURST_EN |
-+			    CNFG_READ_MODE | CNFG_DMA_MODE | op_mode);
-+
-+	nfi_write32(snf, NFI_CON, (snf->nfi_cfg.nsectors << CON_SEC_NUM_S));
-+
-+	buf_dma = dma_map_single(snf->dev, buf, dma_len, DMA_FROM_DEVICE);
-+	if (dma_mapping_error(snf->dev, buf_dma)) {
-+		dev_err(snf->dev, "DMA mapping failed.\n");
-+		goto cleanup;
-+	}
-+	nfi_write32(snf, NFI_STRADDR, buf_dma);
-+	if (op->data.ecc) {
-+		snf->ecc_cfg->op = ECC_DECODE;
-+		ret = mtk_ecc_enable(snf->ecc, snf->ecc_cfg);
-+		if (ret)
-+			goto cleanup_dma;
-+	}
-+	// Prepare for custom read interrupt
-+	nfi_write32(snf, NFI_INTR_EN, NFI_IRQ_INTR_EN | NFI_IRQ_CUS_READ);
-+	reinit_completion(&snf->op_done);
-+
-+	// Trigger NFI into custom mode
-+	nfi_write16(snf, NFI_CMD, NFI_CMD_DUMMY_READ);
-+
-+	// Start DMA read
-+	nfi_rmw32(snf, NFI_CON, 0, CON_BRD);
-+	nfi_write16(snf, NFI_STRDATA, STR_DATA);
-+
-+	if (!wait_for_completion_timeout(
-+		    &snf->op_done, usecs_to_jiffies(SNFI_POLL_INTERVAL))) {
-+		dev_err(snf->dev, "DMA timed out for reading from cache.\n");
-+		ret = -ETIMEDOUT;
-+		goto cleanup;
-+	}
-+
-+	// Wait for BUS_SEC_CNTR returning expected value
-+	ret = readl_poll_timeout(snf->nfi_base + NFI_BYTELEN, val,
-+				 BUS_SEC_CNTR(val) >= snf->nfi_cfg.nsectors, 0,
-+				 SNFI_POLL_INTERVAL);
-+	if (ret) {
-+		dev_err(snf->dev, "Timed out waiting for BUS_SEC_CNTR\n");
-+		goto cleanup2;
-+	}
-+
-+	// Wait for bus becoming idle
-+	ret = readl_poll_timeout(snf->nfi_base + NFI_MASTERSTA, val,
-+				 !(val & snf->caps->mastersta_mask), 0,
-+				 SNFI_POLL_INTERVAL);
-+	if (ret) {
-+		dev_err(snf->dev, "Timed out waiting for bus becoming idle\n");
-+		goto cleanup2;
-+	}
-+
-+	if (op->data.ecc) {
-+		ret = mtk_ecc_wait_done(snf->ecc, ECC_DECODE);
-+		if (ret) {
-+			dev_err(snf->dev, "wait ecc done timeout\n");
-+			goto cleanup2;
-+		}
-+		// save status before disabling ecc
-+		mtk_ecc_get_stats(snf->ecc, &snf->ecc_stats,
-+				  snf->nfi_cfg.nsectors);
-+	}
-+
-+	dma_unmap_single(snf->dev, buf_dma, dma_len, DMA_FROM_DEVICE);
-+
-+	if (snf->autofmt) {
-+		mtk_snand_read_fdm(snf, buf_fdm);
-+		if (snf->caps->bbm_swap) {
-+			mtk_snand_bm_swap(snf, buf);
-+			mtk_snand_fdm_bm_swap(snf);
-+		}
-+	}
-+
-+	// copy data back
-+	if (nfi_read32(snf, NFI_STA) & READ_EMPTY) {
-+		memset(op->data.buf.in, 0xff, op->data.nbytes);
-+		snf->ecc_stats.bitflips = 0;
-+		snf->ecc_stats.failed = 0;
-+		snf->ecc_stats.corrected = 0;
-+	} else {
-+		if (buf == op->data.buf.in) {
-+			u32 cap_len = snf->buf_len - snf->nfi_cfg.page_size;
-+			u32 req_left = op->data.nbytes - snf->nfi_cfg.page_size;
-+
-+			if (req_left)
-+				memcpy(op->data.buf.in + snf->nfi_cfg.page_size,
-+				       buf_fdm,
-+				       cap_len < req_left ? cap_len : req_left);
-+		} else if (rd_offset < snf->buf_len) {
-+			u32 cap_len = snf->buf_len - rd_offset;
-+
-+			if (op->data.nbytes < cap_len)
-+				cap_len = op->data.nbytes;
-+			memcpy(op->data.buf.in, snf->buf + rd_offset, cap_len);
-+		}
-+	}
-+cleanup2:
-+	if (op->data.ecc)
-+		mtk_ecc_disable(snf->ecc);
-+cleanup_dma:
-+	// unmap dma only if any error happens. (otherwise it's done before
-+	// data copying)
-+	if (ret)
-+		dma_unmap_single(snf->dev, buf_dma, dma_len, DMA_FROM_DEVICE);
-+cleanup:
-+	// Stop read
-+	nfi_write32(snf, NFI_CON, 0);
-+	nfi_write16(snf, NFI_CNFG, 0);
-+
-+	// Clear SNF done flag
-+	nfi_rmw32(snf, SNF_STA_CTL1, 0, CUS_READ_DONE);
-+	nfi_write32(snf, SNF_STA_CTL1, 0);
-+
-+	// Disable interrupt
-+	nfi_read32(snf, NFI_INTR_STA);
-+	nfi_write32(snf, NFI_INTR_EN, 0);
-+
-+	nfi_rmw32(snf, SNF_MISC_CTL, DATARD_CUSTOM_EN, 0);
-+	return ret;
-+}
-+
-+static int mtk_snand_write_page_cache(struct mtk_snand *snf,
-+				      const struct spi_mem_op *op)
-+{
-+	// the address part to be sent by the controller
-+	u32 op_addr = op->addr.val;
-+	// where to start copying data from bounce buffer
-+	u32 wr_offset = 0;
-+	u32 op_mode = 0;
-+	int ret = 0;
-+	u32 wr_mode = 0;
-+	u32 dma_len = snf->buf_len;
-+	u32 wr_bytes, val;
-+	size_t cap_len;
-+	dma_addr_t buf_dma;
-+
-+	if (snf->autofmt) {
-+		u32 last_bit;
-+		u32 mask;
-+
-+		dma_len = snf->nfi_cfg.page_size;
-+		op_mode = CNFG_AUTO_FMT_EN;
-+		if (op->data.ecc)
-+			op_mode |= CNFG_HW_ECC_EN;
-+
-+		last_bit = fls(snf->nfi_cfg.page_size + snf->nfi_cfg.oob_size);
-+		mask = (1 << last_bit) - 1;
-+		wr_offset = op_addr & mask;
-+		op_addr &= ~mask;
-+	}
-+	mtk_snand_mac_reset(snf);
-+	mtk_nfi_reset(snf);
-+
-+	if (wr_offset)
-+		memset(snf->buf, 0xff, wr_offset);
-+
-+	cap_len = snf->buf_len - wr_offset;
-+	if (op->data.nbytes < cap_len)
-+		cap_len = op->data.nbytes;
-+	memcpy(snf->buf + wr_offset, op->data.buf.out, cap_len);
-+	if (snf->autofmt) {
-+		if (snf->caps->bbm_swap) {
-+			mtk_snand_fdm_bm_swap(snf);
-+			mtk_snand_bm_swap(snf, snf->buf);
-+		}
-+		mtk_snand_write_fdm(snf, snf->buf + snf->nfi_cfg.page_size);
-+	}
-+
-+	// Command
-+	nfi_write32(snf, SNF_PG_CTL1, (op->cmd.opcode << PG_LOAD_CMD_S));
-+
-+	// write address
-+	nfi_write32(snf, SNF_PG_CTL2, op_addr);
-+
-+	// Set read op_mode
-+	if (op->data.buswidth == 4)
-+		wr_mode = PG_LOAD_X4_EN;
-+
-+	nfi_rmw32(snf, SNF_MISC_CTL, PG_LOAD_X4_EN,
-+		  wr_mode | PG_LOAD_CUSTOM_EN);
-+
-+	// Set bytes to write
-+	wr_bytes = (snf->nfi_cfg.spare_size + snf->caps->sector_size) *
-+		   snf->nfi_cfg.nsectors;
-+	nfi_write32(snf, SNF_MISC_CTL2,
-+		    (wr_bytes << PROGRAM_LOAD_BYTE_NUM_S) | wr_bytes);
-+
-+	// NFI write prepare
-+	nfi_write16(snf, NFI_CNFG,
-+		    (CNFG_OP_MODE_PROGRAM << CNFG_OP_MODE_S) |
-+			    CNFG_DMA_BURST_EN | CNFG_DMA_MODE | op_mode);
-+
-+	nfi_write32(snf, NFI_CON, (snf->nfi_cfg.nsectors << CON_SEC_NUM_S));
-+	buf_dma = dma_map_single(snf->dev, snf->buf, dma_len, DMA_TO_DEVICE);
-+	if (dma_mapping_error(snf->dev, buf_dma)) {
-+		dev_err(snf->dev, "DMA mapping failed.\n");
-+		goto cleanup;
-+	}
-+	nfi_write32(snf, NFI_STRADDR, buf_dma);
-+	if (op->data.ecc) {
-+		snf->ecc_cfg->op = ECC_ENCODE;
-+		ret = mtk_ecc_enable(snf->ecc, snf->ecc_cfg);
-+		if (ret)
-+			goto cleanup_dma;
-+	}
-+	// Prepare for custom write interrupt
-+	nfi_write32(snf, NFI_INTR_EN, NFI_IRQ_INTR_EN | NFI_IRQ_CUS_PG);
-+	reinit_completion(&snf->op_done);
-+	;
-+
-+	// Trigger NFI into custom mode
-+	nfi_write16(snf, NFI_CMD, NFI_CMD_DUMMY_WRITE);
-+
-+	// Start DMA write
-+	nfi_rmw32(snf, NFI_CON, 0, CON_BWR);
-+	nfi_write16(snf, NFI_STRDATA, STR_DATA);
-+
-+	if (!wait_for_completion_timeout(
-+		    &snf->op_done, usecs_to_jiffies(SNFI_POLL_INTERVAL))) {
-+		dev_err(snf->dev, "DMA timed out for program load.\n");
-+		ret = -ETIMEDOUT;
-+		goto cleanup_ecc;
-+	}
-+
-+	// Wait for NFI_SEC_CNTR returning expected value
-+	ret = readl_poll_timeout(snf->nfi_base + NFI_ADDRCNTR, val,
-+				 NFI_SEC_CNTR(val) >= snf->nfi_cfg.nsectors, 0,
-+				 SNFI_POLL_INTERVAL);
-+	if (ret)
-+		dev_err(snf->dev, "Timed out waiting for NFI_SEC_CNTR\n");
-+
-+cleanup_ecc:
-+	if (op->data.ecc)
-+		mtk_ecc_disable(snf->ecc);
-+cleanup_dma:
-+	dma_unmap_single(snf->dev, buf_dma, dma_len, DMA_TO_DEVICE);
-+cleanup:
-+	// Stop write
-+	nfi_write32(snf, NFI_CON, 0);
-+	nfi_write16(snf, NFI_CNFG, 0);
-+
-+	// Clear SNF done flag
-+	nfi_rmw32(snf, SNF_STA_CTL1, 0, CUS_PG_DONE);
-+	nfi_write32(snf, SNF_STA_CTL1, 0);
-+
-+	// Disable interrupt
-+	nfi_read32(snf, NFI_INTR_STA);
-+	nfi_write32(snf, NFI_INTR_EN, 0);
-+
-+	nfi_rmw32(snf, SNF_MISC_CTL, PG_LOAD_CUSTOM_EN, 0);
-+
-+	return ret;
-+}
-+
-+/**
-+ * mtk_snand_is_page_ops() - check if the op is a controller supported page op.
-+ * @op spi-mem op to check
-+ *
-+ * Check whether op can be executed with read_from_cache or program_load
-+ * mode in the controller.
-+ * This controller can execute typical Read From Cache and Program Load
-+ * instructions found on SPI-NAND with 2-byte address.
-+ * DTR and cmd buswidth & nbytes should be checked before calling this.
-+ *
-+ * Return: true if the op matches the instruction template
-+ */
-+static bool mtk_snand_is_page_ops(const struct spi_mem_op *op)
-+{
-+	if (op->addr.nbytes != 2)
-+		return false;
-+
-+	if (op->addr.buswidth != 1 && op->addr.buswidth != 2 &&
-+	    op->addr.buswidth != 4)
-+		return false;
-+
-+	// match read from page instructions
-+	if (op->data.dir == SPI_MEM_DATA_IN) {
-+		// check dummy cycle first
-+		if (op->dummy.nbytes * BITS_PER_BYTE / op->dummy.buswidth >
-+		    DATA_READ_MAX_DUMMY)
-+			return false;
-+		// quad io / quad out
-+		if ((op->addr.buswidth == 4 || op->addr.buswidth == 1) &&
-+		    op->data.buswidth == 4)
-+			return true;
-+
-+		// dual io / dual out
-+		if ((op->addr.buswidth == 2 || op->addr.buswidth == 1) &&
-+		    op->data.buswidth == 2)
-+			return true;
-+
-+		// standard spi
-+		if (op->addr.buswidth == 1 && op->data.buswidth == 1)
-+			return true;
-+	} else if (op->data.dir == SPI_MEM_DATA_OUT) {
-+		// check dummy cycle first
-+		if (op->dummy.nbytes)
-+			return false;
-+		// program load quad out
-+		if (op->addr.buswidth == 1 && op->data.buswidth == 4)
-+			return true;
-+		// standard spi
-+		if (op->addr.buswidth == 1 && op->data.buswidth == 1)
-+			return true;
-+	}
-+	return false;
-+}
-+
-+static bool mtk_snand_supports_op(struct spi_mem *mem,
-+				  const struct spi_mem_op *op)
-+{
-+	if (!spi_mem_default_supports_op(mem, op))
-+		return false;
-+	if (op->cmd.nbytes != 1 || op->cmd.buswidth != 1)
-+		return false;
-+	if (mtk_snand_is_page_ops(op))
-+		return true;
-+	return ((op->addr.nbytes == 0 || op->addr.buswidth == 1) &&
-+		(op->dummy.nbytes == 0 || op->dummy.buswidth == 1) &&
-+		(op->data.nbytes == 0 || op->data.buswidth == 1));
-+}
-+
-+static int mtk_snand_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
-+{
-+	struct mtk_snand *ms = spi_controller_get_devdata(mem->spi->master);
-+	// page ops transfer size must be exactly ((sector_size + spare_size) *
-+	// nsectors). Limit the op size if the caller requests more than that.
-+	// exec_op will read more than needed and discard the leftover if the
-+	// caller requests less data.
-+	if (mtk_snand_is_page_ops(op)) {
-+		size_t l;
-+		// skip adjust_op_size for page ops
-+		if (ms->autofmt)
-+			return 0;
-+		l = ms->caps->sector_size + ms->nfi_cfg.spare_size;
-+		l *= ms->nfi_cfg.nsectors;
-+		if (op->data.nbytes > l)
-+			op->data.nbytes = l;
-+	} else {
-+		size_t hl = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes;
-+
-+		if (hl >= SNF_GPRAM_SIZE)
-+			return -EOPNOTSUPP;
-+		if (op->data.nbytes > SNF_GPRAM_SIZE - hl)
-+			op->data.nbytes = SNF_GPRAM_SIZE - hl;
-+	}
-+	return 0;
-+}
-+
-+static int mtk_snand_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
-+{
-+	struct mtk_snand *ms = spi_controller_get_devdata(mem->spi->master);
-+
-+	dev_dbg(ms->dev, "OP %02x ADDR %08llX@%d:%u DATA %d:%u", op->cmd.opcode,
-+		op->addr.val, op->addr.buswidth, op->addr.nbytes,
-+		op->data.buswidth, op->data.nbytes);
-+	if (mtk_snand_is_page_ops(op)) {
-+		if (op->data.dir == SPI_MEM_DATA_IN)
-+			return mtk_snand_read_page_cache(ms, op);
-+		else
-+			return mtk_snand_write_page_cache(ms, op);
-+	} else {
-+		return mtk_snand_mac_io(ms, op);
-+	}
-+}
-+
-+static const struct spi_controller_mem_ops mtk_snand_mem_ops = {
-+	.adjust_op_size = mtk_snand_adjust_op_size,
-+	.supports_op = mtk_snand_supports_op,
-+	.exec_op = mtk_snand_exec_op,
-+};
-+
-+static const struct spi_controller_mem_caps mtk_snand_mem_caps = {
-+	.ecc = true,
-+};
-+
-+static irqreturn_t mtk_snand_irq(int irq, void *id)
-+{
-+	struct mtk_snand *snf = id;
-+	u32 sta, ien;
-+
-+	sta = nfi_read32(snf, NFI_INTR_STA);
-+	ien = nfi_read32(snf, NFI_INTR_EN);
-+
-+	if (!(sta & ien))
-+		return IRQ_NONE;
-+
-+	nfi_write32(snf, NFI_INTR_EN, 0);
-+	complete(&snf->op_done);
-+	return IRQ_HANDLED;
-+}
-+
-+static const struct of_device_id mtk_snand_ids[] = {
-+	{ .compatible = "mediatek,mt7622-snand", .data = &mt7622_snand_caps },
-+	{ .compatible = "mediatek,mt7629-snand", .data = &mt7629_snand_caps },
-+	{},
-+};
-+
-+MODULE_DEVICE_TABLE(of, mtk_snand_ids);
-+
-+static int mtk_snand_enable_clk(struct mtk_snand *ms)
-+{
-+	int ret;
-+
-+	ret = clk_prepare_enable(ms->nfi_clk);
-+	if (ret) {
-+		dev_err(ms->dev, "unable to enable nfi clk\n");
-+		return ret;
-+	}
-+	ret = clk_prepare_enable(ms->pad_clk);
-+	if (ret) {
-+		dev_err(ms->dev, "unable to enable pad clk\n");
-+		goto err1;
-+	}
-+	return 0;
-+err1:
-+	clk_disable_unprepare(ms->nfi_clk);
-+	return ret;
-+}
-+
-+static void mtk_snand_disable_clk(struct mtk_snand *ms)
-+{
-+	clk_disable_unprepare(ms->pad_clk);
-+	clk_disable_unprepare(ms->nfi_clk);
-+}
-+
-+static int mtk_snand_probe(struct platform_device *pdev)
-+{
-+	struct device_node *np = pdev->dev.of_node;
-+	const struct of_device_id *dev_id;
-+	struct spi_controller *ctlr;
-+	struct mtk_snand *ms;
-+	int ret;
-+
-+	dev_id = of_match_node(mtk_snand_ids, np);
-+	if (!dev_id)
-+		return -EINVAL;
-+
-+	ctlr = devm_spi_alloc_master(&pdev->dev, sizeof(*ms));
-+	if (!ctlr)
-+		return -ENOMEM;
-+	platform_set_drvdata(pdev, ctlr);
-+
-+	ms = spi_controller_get_devdata(ctlr);
-+
-+	ms->ctlr = ctlr;
-+	ms->caps = dev_id->data;
-+
-+	ms->ecc = of_mtk_ecc_get(np);
-+	if (IS_ERR(ms->ecc))
-+		return PTR_ERR(ms->ecc);
-+	else if (!ms->ecc)
-+		return -ENODEV;
-+
-+	ms->nfi_base = devm_platform_ioremap_resource(pdev, 0);
-+	if (IS_ERR(ms->nfi_base)) {
-+		ret = PTR_ERR(ms->nfi_base);
-+		goto release_ecc;
-+	}
-+
-+	ms->dev = &pdev->dev;
-+
-+	ms->nfi_clk = devm_clk_get(&pdev->dev, "nfi_clk");
-+	if (IS_ERR(ms->nfi_clk)) {
-+		ret = PTR_ERR(ms->nfi_clk);
-+		dev_err(&pdev->dev, "unable to get nfi_clk, err = %d\n", ret);
-+		goto release_ecc;
-+	}
-+
-+	ms->pad_clk = devm_clk_get(&pdev->dev, "pad_clk");
-+	if (IS_ERR(ms->pad_clk)) {
-+		ret = PTR_ERR(ms->pad_clk);
-+		dev_err(&pdev->dev, "unable to get pad_clk, err = %d\n", ret);
-+		goto release_ecc;
-+	}
-+
-+	ret = mtk_snand_enable_clk(ms);
-+	if (ret)
-+		goto release_ecc;
-+
-+	init_completion(&ms->op_done);
-+
-+	ms->irq = platform_get_irq(pdev, 0);
-+	if (ms->irq < 0) {
-+		ret = ms->irq;
-+		goto disable_clk;
-+	}
-+	ret = devm_request_irq(ms->dev, ms->irq, mtk_snand_irq, 0x0,
-+			       "mtk-snand", ms);
-+	if (ret) {
-+		dev_err(ms->dev, "failed to request snfi irq\n");
-+		goto disable_clk;
-+	}
-+
-+	ret = dma_set_mask(ms->dev, DMA_BIT_MASK(32));
-+	if (ret) {
-+		dev_err(ms->dev, "failed to set dma mask\n");
-+		goto disable_clk;
-+	}
-+
-+	// switch to SNFI mode
-+	nfi_write32(ms, SNF_CFG, SPI_MODE);
-+
-+	// setup an initial page format for ops matching page_cache_op template
-+	// before ECC is called.
-+	ret = mtk_snand_setup_pagefmt(ms, ms->caps->sector_size,
-+				      ms->caps->spare_sizes[0]);
-+	if (ret) {
-+		dev_err(ms->dev, "failed to set initial page format\n");
-+		goto disable_clk;
-+	}
-+
-+	// setup ECC engine
-+	ms->ecc_eng.dev = &pdev->dev;
-+	ms->ecc_eng.integration = NAND_ECC_ENGINE_INTEGRATION_PIPELINED;
-+	ms->ecc_eng.ops = &mtk_snfi_ecc_engine_ops;
-+	ms->ecc_eng.priv = ms;
-+
-+	ret = nand_ecc_register_on_host_hw_engine(&ms->ecc_eng);
-+	if (ret) {
-+		dev_err(&pdev->dev, "failed to register ecc engine.\n");
-+		goto disable_clk;
-+	}
-+
-+	ctlr->num_chipselect = 1;
-+	ctlr->mem_ops = &mtk_snand_mem_ops;
-+	ctlr->mem_caps = &mtk_snand_mem_caps;
-+	ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
-+	ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD;
-+	ctlr->dev.of_node = pdev->dev.of_node;
-+	ret = spi_register_controller(ctlr);
-+	if (ret) {
-+		dev_err(&pdev->dev, "spi_register_controller failed.\n");
-+		goto disable_clk;
-+	}
-+
-+	return 0;
-+disable_clk:
-+	mtk_snand_disable_clk(ms);
-+release_ecc:
-+	mtk_ecc_release(ms->ecc);
-+	return ret;
-+}
-+
-+static int mtk_snand_remove(struct platform_device *pdev)
-+{
-+	struct spi_controller *ctlr = platform_get_drvdata(pdev);
-+	struct mtk_snand *ms = spi_controller_get_devdata(ctlr);
-+
-+	spi_unregister_controller(ctlr);
-+	mtk_snand_disable_clk(ms);
-+	mtk_ecc_release(ms->ecc);
-+	kfree(ms->buf);
-+	return 0;
-+}
-+
-+static struct platform_driver mtk_snand_driver = {
-+	.probe = mtk_snand_probe,
-+	.remove = mtk_snand_remove,
-+	.driver = {
-+		.name = "mtk-snand",
-+		.of_match_table = mtk_snand_ids,
-+	},
-+};
-+
-+module_platform_driver(mtk_snand_driver);
-+
-+MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("Chuanhong Guo <gch981213@gmail.com>");
-+MODULE_DESCRIPTION("MeidaTek SPI-NAND Flash Controller Driver");
diff --git a/target/linux/mediatek/patches-5.15/120-13-v5.19-mtd-nand-mtk-ecc-also-parse-nand-ecc-engine-if-avail.patch b/target/linux/mediatek/patches-5.15/120-13-v5.19-mtd-nand-mtk-ecc-also-parse-nand-ecc-engine-if-avail.patch
deleted file mode 100644
index 01d9d12088cd87..00000000000000
--- a/target/linux/mediatek/patches-5.15/120-13-v5.19-mtd-nand-mtk-ecc-also-parse-nand-ecc-engine-if-avail.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From 433b76fa0f3ca2865841abc21538dd8077ca3edd Mon Sep 17 00:00:00 2001
-From: Chuanhong Guo <gch981213@gmail.com>
-Date: Mon, 4 Apr 2022 00:05:38 +0800
-Subject: [PATCH 13/15] mtd: nand: mtk-ecc: also parse nand-ecc-engine if
- available
-
-The recently added ECC engine support introduced a generic property
-named nand-ecc-engine for ecc engine phandle. This patch adds support
-for this new property.
-
-Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
-(cherry picked from commit a41f25feb6e47c1c4d8d3279ae990ccbd8dfab54)
----
- drivers/mtd/nand/ecc-mtk.c | 5 ++++-
- 1 file changed, 4 insertions(+), 1 deletion(-)
-
---- a/drivers/mtd/nand/ecc-mtk.c
-+++ b/drivers/mtd/nand/ecc-mtk.c
-@@ -279,7 +279,10 @@ struct mtk_ecc *of_mtk_ecc_get(struct de
- 	struct mtk_ecc *ecc = NULL;
- 	struct device_node *np;
- 
--	np = of_parse_phandle(of_node, "ecc-engine", 0);
-+	np = of_parse_phandle(of_node, "nand-ecc-engine", 0);
-+	/* for backward compatibility */
-+	if (!np)
-+		np = of_parse_phandle(of_node, "ecc-engine", 0);
- 	if (np) {
- 		ecc = mtk_ecc_get(np);
- 		of_node_put(np);
diff --git a/target/linux/mediatek/patches-5.15/120-14-v5.19-arm64-dts-mediatek-add-mtk-snfi-for-mt7622.patch b/target/linux/mediatek/patches-5.15/120-14-v5.19-arm64-dts-mediatek-add-mtk-snfi-for-mt7622.patch
deleted file mode 100644
index 15d267137230e3..00000000000000
--- a/target/linux/mediatek/patches-5.15/120-14-v5.19-arm64-dts-mediatek-add-mtk-snfi-for-mt7622.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From 9ba7c246063ae43baf2e53ccc8c8b5f8d025aaaa Mon Sep 17 00:00:00 2001
-From: Chuanhong Guo <gch981213@gmail.com>
-Date: Sun, 3 Apr 2022 10:19:29 +0800
-Subject: [PATCH 15/15] arm64: dts: mediatek: add mtk-snfi for mt7622
-
-This patch adds a device-tree node for the MTK SPI-NAND Flash Interface
-for MT7622 device tree.
-
-Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
-(cherry picked from commit 2e022641709011ef0843d0416b0f264b5fc217af)
----
- arch/arm64/boot/dts/mediatek/mt7622.dtsi | 12 ++++++++++++
- 1 file changed, 12 insertions(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -553,6 +553,18 @@
- 		status = "disabled";
- 	};
- 
-+	snfi: spi@1100d000 {
-+		compatible = "mediatek,mt7622-snand";
-+		reg = <0 0x1100d000 0 0x1000>;
-+		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
-+		clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>;
-+		clock-names = "nfi_clk", "pad_clk";
-+		nand-ecc-engine = <&bch>;
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		status = "disabled";
-+	};
-+
- 	bch: ecc@1100e000 {
- 		compatible = "mediatek,mt7622-ecc";
- 		reg = <0 0x1100e000 0 0x1000>;
diff --git a/target/linux/mediatek/patches-5.15/121-hack-spi-nand-1b-bbm.patch b/target/linux/mediatek/patches-5.15/121-hack-spi-nand-1b-bbm.patch
deleted file mode 100644
index ff5521c44eafd5..00000000000000
--- a/target/linux/mediatek/patches-5.15/121-hack-spi-nand-1b-bbm.patch
+++ /dev/null
@@ -1,20 +0,0 @@
---- a/drivers/mtd/nand/spi/core.c
-+++ b/drivers/mtd/nand/spi/core.c
-@@ -724,7 +724,7 @@ static int spinand_mtd_write(struct mtd_
- static bool spinand_isbad(struct nand_device *nand, const struct nand_pos *pos)
- {
- 	struct spinand_device *spinand = nand_to_spinand(nand);
--	u8 marker[2] = { };
-+	u8 marker[1] = { };
- 	struct nand_page_io_req req = {
- 		.pos = *pos,
- 		.ooblen = sizeof(marker),
-@@ -735,7 +735,7 @@ static bool spinand_isbad(struct nand_de
- 
- 	spinand_select_target(spinand, pos->target);
- 	spinand_read_page(spinand, &req);
--	if (marker[0] != 0xff || marker[1] != 0xff)
-+	if (marker[0] != 0xff)
- 		return true;
- 
- 	return false;
diff --git a/target/linux/mediatek/patches-5.15/130-dts-mt7629-add-snand-support.patch b/target/linux/mediatek/patches-5.15/130-dts-mt7629-add-snand-support.patch
deleted file mode 100644
index be0018a383752c..00000000000000
--- a/target/linux/mediatek/patches-5.15/130-dts-mt7629-add-snand-support.patch
+++ /dev/null
@@ -1,94 +0,0 @@
-From c813fbe806257c574240770ef716fbee19f7dbfa Mon Sep 17 00:00:00 2001
-From: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
-Date: Thu, 6 Jun 2019 16:29:04 +0800
-Subject: [PATCH] spi: spi-mem: Mediatek: Add SPI Nand support for MT7629
-
-Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
----
- arch/arm/boot/dts/mt7629-rfb.dts | 45 ++++++++++++++++++++++++++++++++
- arch/arm/boot/dts/mt7629.dtsi    | 22 ++++++++++++++++
- 3 files changed, 79 insertions(+)
-
---- a/arch/arm/boot/dts/mt7629.dtsi
-+++ b/arch/arm/boot/dts/mt7629.dtsi
-@@ -272,6 +272,27 @@
- 			status = "disabled";
- 		};
- 
-+		snfi: spi@1100d000 {
-+			compatible = "mediatek,mt7629-snand";
-+			reg = <0x1100d000 0x1000>;
-+			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
-+			clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>;
-+			clock-names = "nfi_clk", "pad_clk";
-+			nand-ecc-engine = <&bch>;
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "disabled";
-+		};
-+
-+		bch: ecc@1100e000 {
-+			compatible = "mediatek,mt7622-ecc";
-+			reg = <0x1100e000 0x1000>;
-+			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
-+			clocks = <&pericfg CLK_PERI_NFIECC_PD>;
-+			clock-names = "nfiecc_clk";
-+			status = "disabled";
-+		};
-+
- 		spi: spi@1100a000 {
- 			compatible = "mediatek,mt7629-spi",
- 				     "mediatek,mt7622-spi";
---- a/arch/arm/boot/dts/mt7629-rfb.dts
-+++ b/arch/arm/boot/dts/mt7629-rfb.dts
-@@ -254,6 +254,50 @@
- 	};
- };
- 
-+&bch {
-+	status = "okay";
-+};
-+
-+&snfi {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&serial_nand_pins>;
-+	status = "okay";
-+	flash@0 {
-+		compatible = "spi-nand";
-+		reg = <0>;
-+		spi-tx-bus-width = <4>;
-+		spi-rx-bus-width = <4>;
-+		nand-ecc-engine = <&snfi>;
-+
-+		partitions {
-+			compatible = "fixed-partitions";
-+			#address-cells = <1>;
-+			#size-cells = <1>;
-+
-+			partition@0 {
-+				label = "Bootloader";
-+				reg = <0x00000 0x0100000>;
-+				read-only;
-+			};
-+
-+			partition@100000 {
-+				label = "Config";
-+				reg = <0x100000 0x0040000>;
-+			};
-+
-+			partition@140000 {
-+				label = "factory";
-+				reg = <0x140000 0x0080000>;
-+			};
-+
-+			partition@1c0000 {
-+				label = "firmware";
-+				reg = <0x1c0000 0x1000000>;
-+			};
-+		};
-+	};
-+};
-+
- &spi {
- 	pinctrl-names = "default";
- 	pinctrl-0 = <&spi_pins>;
diff --git a/target/linux/mediatek/patches-5.15/131-dts-mt7622-add-snand-support.patch b/target/linux/mediatek/patches-5.15/131-dts-mt7622-add-snand-support.patch
deleted file mode 100644
index 134e5997e25098..00000000000000
--- a/target/linux/mediatek/patches-5.15/131-dts-mt7622-add-snand-support.patch
+++ /dev/null
@@ -1,68 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-@@ -539,6 +539,65 @@
- 	status = "disabled";
- };
- 
-+&bch {
-+	status = "okay";
-+};
-+
-+&snfi {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&serial_nand_pins>;
-+	status = "okay";
-+	flash@0 {
-+		compatible = "spi-nand";
-+		reg = <0>;
-+		spi-tx-bus-width = <4>;
-+		spi-rx-bus-width = <4>;
-+		nand-ecc-engine = <&snfi>;
-+
-+		partitions {
-+			compatible = "fixed-partitions";
-+			#address-cells = <1>;
-+			#size-cells = <1>;
-+
-+			partition@0 {
-+				label = "Preloader";
-+				reg = <0x00000 0x0080000>;
-+				read-only;
-+			};
-+
-+			partition@80000 {
-+				label = "ATF";
-+				reg = <0x80000 0x0040000>;
-+			};
-+
-+			partition@c0000 {
-+				label = "Bootloader";
-+				reg = <0xc0000 0x0080000>;
-+			};
-+
-+			partition@140000 {
-+				label = "Config";
-+				reg = <0x140000 0x0080000>;
-+			};
-+
-+			partition@1c0000 {
-+				label = "Factory";
-+				reg = <0x1c0000 0x0100000>;
-+			};
-+
-+			partition@200000 {
-+				label = "firmware";
-+				reg = <0x2c0000 0x2000000>;
-+			};
-+
-+			partition@2200000 {
-+				label = "User_data";
-+				reg = <0x22c0000 0x4000000>;
-+			};
-+		};
-+	};
-+};
-+
- &spi0 {
- 	pinctrl-names = "default";
- 	pinctrl-0 = <&spic0_pins>;
diff --git a/target/linux/mediatek/patches-5.15/140-dts-fix-wmac-support-for-mt7622-rfb1.patch b/target/linux/mediatek/patches-5.15/140-dts-fix-wmac-support-for-mt7622-rfb1.patch
deleted file mode 100644
index 8e6935b43449fe..00000000000000
--- a/target/linux/mediatek/patches-5.15/140-dts-fix-wmac-support-for-mt7622-rfb1.patch
+++ /dev/null
@@ -1,18 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-@@ -580,7 +580,7 @@
- 				reg = <0x140000 0x0080000>;
- 			};
- 
--			partition@1c0000 {
-+			factory: partition@1c0000 {
- 				label = "Factory";
- 				reg = <0x1c0000 0x0100000>;
- 			};
-@@ -641,5 +641,6 @@
- &wmac {
- 	pinctrl-names = "default";
- 	pinctrl-0 = <&wmac_pins>;
-+	mediatek,mtd-eeprom = <&factory 0x0000>;
- 	status = "okay";
- };
diff --git a/target/linux/mediatek/patches-5.15/150-dts-mt7623-eip97-inside-secure-support.patch b/target/linux/mediatek/patches-5.15/150-dts-mt7623-eip97-inside-secure-support.patch
deleted file mode 100644
index 5b63bf4226b0a6..00000000000000
--- a/target/linux/mediatek/patches-5.15/150-dts-mt7623-eip97-inside-secure-support.patch
+++ /dev/null
@@ -1,24 +0,0 @@
---- a/arch/arm/boot/dts/mt7623.dtsi
-+++ b/arch/arm/boot/dts/mt7623.dtsi
-@@ -951,17 +951,15 @@
- 	};
- 
- 	crypto: crypto@1b240000 {
--		compatible = "mediatek,eip97-crypto";
-+		compatible = "inside-secure,safexcel-eip97";
- 		reg = <0 0x1b240000 0 0x20000>;
- 		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
- 			     <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
- 			     <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
--			     <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
--			     <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
-+			     <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
-+		interrupt-names = "ring0", "ring1", "ring2", "ring3";
- 		clocks = <&ethsys CLK_ETHSYS_CRYPTO>;
--		clock-names = "cryp";
--		power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
--		status = "disabled";
-+		status = "okay";
- 	};
- 
- 	bdpsys: syscon@1c000000 {
diff --git a/target/linux/mediatek/patches-5.15/160-dts-mt7623-bpi-r2-earlycon.patch b/target/linux/mediatek/patches-5.15/160-dts-mt7623-bpi-r2-earlycon.patch
deleted file mode 100644
index 091cffc3c07c1f..00000000000000
--- a/target/linux/mediatek/patches-5.15/160-dts-mt7623-bpi-r2-earlycon.patch
+++ /dev/null
@@ -1,11 +0,0 @@
---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-@@ -19,7 +19,7 @@
- 
- 	chosen {
- 		stdout-path = "serial2:115200n8";
--		bootargs = "console=ttyS2,115200n8 console=tty1";
-+		bootargs = "earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200n8 console=tty1";
- 	};
- 
- 	connector {
diff --git a/target/linux/mediatek/patches-5.15/161-dts-mt7623-bpi-r2-mmc-device-order.patch b/target/linux/mediatek/patches-5.15/161-dts-mt7623-bpi-r2-mmc-device-order.patch
deleted file mode 100644
index d1bafc15260903..00000000000000
--- a/target/linux/mediatek/patches-5.15/161-dts-mt7623-bpi-r2-mmc-device-order.patch
+++ /dev/null
@@ -1,11 +0,0 @@
---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-@@ -15,6 +15,8 @@
- 
- 	aliases {
- 		serial2 = &uart2;
-+		mmc0 = &mmc0;
-+		mmc1 = &mmc1;
- 	};
- 
- 	chosen {
diff --git a/target/linux/mediatek/patches-5.15/162-dts-mt7623-bpi-r2-led-aliases.patch b/target/linux/mediatek/patches-5.15/162-dts-mt7623-bpi-r2-led-aliases.patch
deleted file mode 100644
index f6745add5b380d..00000000000000
--- a/target/linux/mediatek/patches-5.15/162-dts-mt7623-bpi-r2-led-aliases.patch
+++ /dev/null
@@ -1,29 +0,0 @@
---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-@@ -17,6 +17,10 @@
- 		serial2 = &uart2;
- 		mmc0 = &mmc0;
- 		mmc1 = &mmc1;
-+		led-boot = &led_system_green;
-+		led-failsafe = &led_system_blue;
-+		led-running = &led_system_green;
-+		led-upgrade = &led_system_blue;
- 	};
- 
- 	chosen {
-@@ -112,13 +116,13 @@
- 		pinctrl-names = "default";
- 		pinctrl-0 = <&led_pins_a>;
- 
--		blue {
-+		led_system_blue: blue {
- 			label = "bpi-r2:pio:blue";
- 			gpios = <&pio 240 GPIO_ACTIVE_LOW>;
- 			default-state = "off";
- 		};
- 
--		green {
-+		led_system_green: green {
- 			label = "bpi-r2:pio:green";
- 			gpios = <&pio 241 GPIO_ACTIVE_LOW>;
- 			default-state = "off";
diff --git a/target/linux/mediatek/patches-5.15/163-dts-mt7623-bpi-r2-ethernet-alias.patch b/target/linux/mediatek/patches-5.15/163-dts-mt7623-bpi-r2-ethernet-alias.patch
deleted file mode 100644
index b1dd75a41400a6..00000000000000
--- a/target/linux/mediatek/patches-5.15/163-dts-mt7623-bpi-r2-ethernet-alias.patch
+++ /dev/null
@@ -1,10 +0,0 @@
---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-@@ -15,6 +15,7 @@
- 
- 	aliases {
- 		serial2 = &uart2;
-+		ethernet0 = &gmac0;
- 		mmc0 = &mmc0;
- 		mmc1 = &mmc1;
- 		led-boot = &led_system_green;
diff --git a/target/linux/mediatek/patches-5.15/173-arm-dts-mt7623-add-musb-device-nodes.patch b/target/linux/mediatek/patches-5.15/173-arm-dts-mt7623-add-musb-device-nodes.patch
deleted file mode 100644
index ba1d1fe202b0a0..00000000000000
--- a/target/linux/mediatek/patches-5.15/173-arm-dts-mt7623-add-musb-device-nodes.patch
+++ /dev/null
@@ -1,69 +0,0 @@
-From 21d106f15262f5a2ef7531636e0703ee61c33c61 Mon Sep 17 00:00:00 2001
-From: Sungbo Eo <mans0n@gorani.run>
-Date: Sun, 8 Aug 2021 21:38:40 +0900
-Subject: [PATCH 2/2] arm: dts: mt7623: add musb device nodes
-
-MT7623 has an musb controller that is compatible with the one from MT2701.
-
-Signed-off-by: Sungbo Eo <mans0n@gorani.run>
----
- arch/arm/boot/dts/mt7623.dtsi  | 34 ++++++++++++++++++++++++++++++++++
- arch/arm/boot/dts/mt7623a.dtsi |  4 ++++
- 2 files changed, 38 insertions(+)
-
---- a/arch/arm/boot/dts/mt7623.dtsi
-+++ b/arch/arm/boot/dts/mt7623.dtsi
-@@ -585,6 +585,40 @@
- 		status = "disabled";
- 	};
- 
-+	usb0: usb@11200000 {
-+		compatible = "mediatek,mt7623-musb",
-+			     "mediatek,mtk-musb";
-+		reg = <0 0x11200000 0 0x1000>;
-+		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
-+		interrupt-names = "mc";
-+		phys = <&u2port2 PHY_TYPE_USB2>;
-+		dr_mode = "otg";
-+		clocks = <&pericfg CLK_PERI_USB0>,
-+			 <&pericfg CLK_PERI_USB0_MCU>,
-+			 <&pericfg CLK_PERI_USB_SLV>;
-+		clock-names = "main","mcu","univpll";
-+		power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
-+		status = "disabled";
-+	};
-+
-+	u2phy1: t-phy@11210000 {
-+		compatible = "mediatek,mt7623-tphy",
-+			     "mediatek,generic-tphy-v1";
-+		reg = <0 0x11210000 0 0x0800>;
-+		#address-cells = <2>;
-+		#size-cells = <2>;
-+		ranges;
-+		status = "disabled";
-+
-+		u2port2: usb-phy@11210800 {
-+			reg = <0 0x11210800 0 0x0100>;
-+			clocks = <&topckgen CLK_TOP_USB_PHY48M>;
-+			clock-names = "ref";
-+			#phy-cells = <1>;
-+			status = "okay";
-+		};
-+	};
-+
- 	audsys: clock-controller@11220000 {
- 		compatible = "mediatek,mt7623-audsys",
- 			     "mediatek,mt2701-audsys",
---- a/arch/arm/boot/dts/mt7623a.dtsi
-+++ b/arch/arm/boot/dts/mt7623a.dtsi
-@@ -35,6 +35,10 @@
- 	clock-names = "ethif";
- };
- 
-+&usb0 {
-+	power-domains = <&scpsys MT7623A_POWER_DOMAIN_IFR_MSC>;
-+};
-+
- &usb1 {
- 	power-domains = <&scpsys MT7623A_POWER_DOMAIN_HIF>;
- };
diff --git a/target/linux/mediatek/patches-5.15/180-dts-mt7622-bpi-r64-add-mt7531-irq.patch b/target/linux/mediatek/patches-5.15/180-dts-mt7622-bpi-r64-add-mt7531-irq.patch
deleted file mode 100644
index 80ceb490d4e43d..00000000000000
--- a/target/linux/mediatek/patches-5.15/180-dts-mt7622-bpi-r64-add-mt7531-irq.patch
+++ /dev/null
@@ -1,13 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -160,6 +160,10 @@
- 		switch@0 {
- 			compatible = "mediatek,mt7531";
- 			reg = <0>;
-+			interrupt-controller;
-+			#interrupt-cells = <1>;
-+			interrupt-parent = <&pio>;
-+			interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
- 			reset-gpios = <&pio 54 0>;
- 
- 			ports {
diff --git a/target/linux/mediatek/patches-5.15/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch b/target/linux/mediatek/patches-5.15/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch
deleted file mode 100644
index 39a9770d98fddf..00000000000000
--- a/target/linux/mediatek/patches-5.15/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch
+++ /dev/null
@@ -1,106 +0,0 @@
-From patchwork Tue Apr 26 19:51:36 2022
-Content-Type: text/plain; charset="utf-8"
-MIME-Version: 1.0
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- id 1njRDu-0006aF-4F; Tue, 26 Apr 2022 21:51:46 +0200
-Date: Tue, 26 Apr 2022 20:51:36 +0100
-From: Daniel Golle <daniel@makrotopia.org>
-To: devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org,
- linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
-Cc: Rob Herring <robh+dt@kernel.org>,
- Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
- Matthias Brugger <matthias.bgg@gmail.com>
-Subject: [PATCH] arm64: dts: mediatek: mt7622: fix GICv2 range
-Message-ID: <YmhNSLgp/yg8Vr1F@makrotopia.org>
-MIME-Version: 1.0
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-
-With the current range specified for the CPU interface there is an
-error message at boot:
-
-GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set
-
-Setting irqchip.gicv2_force_probe=1 in bootargs results in:
-
-GIC: Aliased GICv2 at 0x0000000010320000, trying to find the canonical range over 128kB
-GIC: Adjusting CPU interface base to 0x000000001032f000
-GIC: Using split EOI/Deactivate mode
-
-Using the adjusted CPU interface base and 8K size results in only the
-final line remaining and fully working system as well as /proc/interrupts
-showing additional IPI3,4,5,6:
-
-IPI3:         0          0       CPU stop (for crash dump) interrupts
-IPI4:         0          0       Timer broadcast interrupts
-IPI5:         0          0       IRQ work interrupts
-IPI6:         0          0       CPU wake-up interrupts
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- arch/arm64/boot/dts/mediatek/mt7622.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -339,7 +339,7 @@
- 		#interrupt-cells = <3>;
- 		interrupt-parent = <&gic>;
- 		reg = <0 0x10310000 0 0x1000>,
--		      <0 0x10320000 0 0x1000>,
-+		      <0 0x1032f000 0 0x2000>,
- 		      <0 0x10340000 0 0x2000>,
- 		      <0 0x10360000 0 0x2000>;
- 	};
diff --git a/target/linux/mediatek/patches-5.15/191-v5.19-arm64-dts-mt7622-specify-the-L2-cache-topology.patch b/target/linux/mediatek/patches-5.15/191-v5.19-arm64-dts-mt7622-specify-the-L2-cache-topology.patch
deleted file mode 100644
index 8851fefbb3a617..00000000000000
--- a/target/linux/mediatek/patches-5.15/191-v5.19-arm64-dts-mt7622-specify-the-L2-cache-topology.patch
+++ /dev/null
@@ -1,132 +0,0 @@
-From patchwork Thu Apr 28 22:57:55 2022
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-Subject: [PATCH] arm64: dts: mt7622: specify the L2 cache topology
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-
-On an MT7622 system, the kernel complains of not being able to detect the cache
-hierarchy of CPU 0. Specify the shared L2 cache node in the device tree, in
-order to fix this.
-
-Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com>
----
- arch/arm64/boot/dts/mediatek/mt7622.dtsi | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -80,6 +80,7 @@
- 			enable-method = "psci";
- 			clock-frequency = <1300000000>;
- 			cci-control-port = <&cci_control2>;
-+			next-level-cache = <&L2>;
- 		};
- 
- 		cpu1: cpu@1 {
-@@ -94,6 +95,12 @@
- 			enable-method = "psci";
- 			clock-frequency = <1300000000>;
- 			cci-control-port = <&cci_control2>;
-+			next-level-cache = <&L2>;
-+		};
-+
-+		L2: l2-cache {
-+			compatible = "cache";
-+			cache-level = <2>;
- 		};
- 	};
- 
diff --git a/target/linux/mediatek/patches-5.15/192-v5.19-arm64-dts-mt7622-specify-the-number-of-DMA-requests.patch b/target/linux/mediatek/patches-5.15/192-v5.19-arm64-dts-mt7622-specify-the-number-of-DMA-requests.patch
deleted file mode 100644
index 4fef9aea22d93a..00000000000000
--- a/target/linux/mediatek/patches-5.15/192-v5.19-arm64-dts-mt7622-specify-the-number-of-DMA-requests.patch
+++ /dev/null
@@ -1,122 +0,0 @@
-From patchwork Fri Apr 29 08:42:25 2022
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-From: Rui Salvaterra <rsalvaterra@gmail.com>
-To: linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org,
- linux-kernel@vger.kernel.org
-Cc: matthias.bgg@gmail.com, ryder.lee@mediatek.com, daniel@makrotopia.org,
- Rui Salvaterra <rsalvaterra@gmail.com>
-Subject: [PATCH] arm64: dts: mt7622: specify the number of DMA requests
-Date: Fri, 29 Apr 2022 09:42:25 +0100
-Message-Id: <20220429084225.298213-1-rsalvaterra@gmail.com>
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-
-The MT7622 device tree never bothered to specify the number of virtual DMA
-channels for the HSDMA controller, always falling back to the default value of
-3. Make this value explicit, in order to avoid the following dmesg notification:
-
-mtk_hsdma 1b007000.dma-controller: Using 3 as missing dma-requests property
-
-Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com>
----
- arch/arm64/boot/dts/mediatek/mt7622.dtsi | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -942,6 +942,7 @@
- 		clock-names = "hsdma";
- 		power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
- 		#dma-cells = <1>;
-+		dma-requests = <3>;
- 	};
- 
- 	pcie_mirror: pcie-mirror@10000400 {
diff --git a/target/linux/mediatek/patches-5.15/193-dts-mt7623-thermal_zone_fix.patch b/target/linux/mediatek/patches-5.15/193-dts-mt7623-thermal_zone_fix.patch
deleted file mode 100644
index 1cfb53d6208918..00000000000000
--- a/target/linux/mediatek/patches-5.15/193-dts-mt7623-thermal_zone_fix.patch
+++ /dev/null
@@ -1,48 +0,0 @@
-From 824d56e753a588fcfd650db1822e34a02a48bb77 Mon Sep 17 00:00:00 2001
-From: Bruno Umuarama <anonimou_eu@hotmail.com>
-Date: Thu, 13 Oct 2022 21:18:21 +0000
-Subject: [PATCH] mediatek: mt7623: fix thermal zone
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Raising the temperatures for passive and active trips. @VA1DER
-proposed at issue 9396 to remove passive trip. This commit relates to
-his suggestion.
-
-Without this patch. the CPU will be throttled all the way down to 98MHz
-if the temperature rises even a degree above the trip point, and it was
-further discovered that if the internal temperature of the device is
-above the first trip point temperature when it boots then it will start
-in a throttled state and even
-$ echo disabled > /sys/class/thermal/thermal_zone0/mode
-will have no effect.
-
-The patch increases the passive trip point and active cooling map. The
-throttling temperature will then be at 77°C and 82°C, which is still a
-low enough temperature for ARM devices to not be in the real danger
-zone, and gives some operational headroom.
-
-Signed-off-by: Bruno Umuarama <anonimou_eu@hotmail.com>
----
- arch/arm/boot/dts/mt7623.dtsi | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/arch/arm/boot/dts/mt7623.dtsi
-+++ b/arch/arm/boot/dts/mt7623.dtsi
-@@ -160,13 +160,13 @@
- 
- 				trips {
- 					cpu_passive: cpu-passive {
--						temperature = <57000>;
-+						temperature = <77000>;
- 						hysteresis = <2000>;
- 						type = "passive";
- 					};
- 
- 					cpu_active: cpu-active {
--						temperature = <67000>;
-+						temperature = <82000>;
- 						hysteresis = <2000>;
- 						type = "active";
- 					};
diff --git a/target/linux/mediatek/patches-5.15/194-dts-mt7968a-add-ramoops.patch b/target/linux/mediatek/patches-5.15/194-dts-mt7968a-add-ramoops.patch
deleted file mode 100644
index 161c1e75168cff..00000000000000
--- a/target/linux/mediatek/patches-5.15/194-dts-mt7968a-add-ramoops.patch
+++ /dev/null
@@ -1,17 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-@@ -68,6 +68,14 @@
- 		#address-cells = <2>;
- 		#size-cells = <2>;
- 		ranges;
-+
-+		/* 64 KiB reserved for ramoops/pstore */
-+		ramoops@42ff0000 {
-+			compatible = "ramoops";
-+			reg = <0 0x42ff0000 0 0x10000>;
-+			record-size = <0x1000>;
-+		};
-+
- 		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
- 		secmon_reserved: secmon@43000000 {
- 			reg = <0 0x43000000 0 0x30000>;
diff --git a/target/linux/mediatek/patches-5.15/195-dts-mt7986a-bpi-r3-leds-port-names-and-wifi-eeprom.patch b/target/linux/mediatek/patches-5.15/195-dts-mt7986a-bpi-r3-leds-port-names-and-wifi-eeprom.patch
deleted file mode 100644
index 336920bafea67a..00000000000000
--- a/target/linux/mediatek/patches-5.15/195-dts-mt7986a-bpi-r3-leds-port-names-and-wifi-eeprom.patch
+++ /dev/null
@@ -1,196 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
-@@ -23,6 +23,10 @@
- 		serial0 = &uart0;
- 		ethernet0 = &gmac0;
- 		ethernet1 = &gmac1;
-+		led-boot = &green_led;
-+		led-failsafe = &green_led;
-+		led-running = &green_led;
-+		led-upgrade = &blue_led;
- 	};
- 
- 	chosen {
-@@ -419,27 +423,27 @@
- 
- 		port@1 {
- 			reg = <1>;
--			label = "lan0";
-+			label = "lan1";
- 		};
- 
- 		port@2 {
- 			reg = <2>;
--			label = "lan1";
-+			label = "lan2";
- 		};
- 
- 		port@3 {
- 			reg = <3>;
--			label = "lan2";
-+			label = "lan3";
- 		};
- 
- 		port@4 {
- 			reg = <4>;
--			label = "lan3";
-+			label = "lan4";
- 		};
- 
- 		port5: port@5 {
- 			reg = <5>;
--			label = "lan4";
-+			label = "sfp2";
- 			phy-mode = "2500base-x";
- 			sfp = <&sfp2>;
- 			managed = "in-band-status";
-@@ -490,9 +494,137 @@
- 
- &wifi {
- 	status = "okay";
--	pinctrl-names = "default", "dbdc";
-+	pinctrl-names = "default";
- 	pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>;
--	pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>;
-+
-+	mediatek,eeprom-data = <0x86790900 0x000c4326 0x60000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x01000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000800 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x24649090 0x00280000 0x05100000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00021e00 0x021e0002 0x1e00021e 0x00022800 0x02280002 0x28000228 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00008080 0x8080fdf7
-+				0x0903150d 0x80808080 0x80808080 0x05050d0d 0x1313c6c6 0xc3c3c200 0x00c200c2 0x00008182
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-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x004b5763 0x0000004b 0x57630000 0x004b5763 0x0000004b 0x57630000 0x88888888 0x08474759
-+				0x69780849 0x49596d7a 0x0849495a 0x6d790848 0x48596c78 0x08484858 0x6a780848 0x48586a78
-+				0x08484858 0x6c78084a 0x4a5b6d79 0x08474759 0x697a0848 0x48596b79 0x08484859 0x6c7a0848
-+				0x48586c79 0x08484857 0x68770848 0x48576877 0x08484857 0x6a77084a 0x4a5a6a77 0x08464659
-+				0x69790848 0x48586b79 0x08484858 0x6c7a0848 0x48596c79 0x08484857 0x68770848 0x48576877
-+				0x08494958 0x6d7a084b 0x4b5c6c77 0x0847475a 0x6a7b0849 0x495a6e7c 0x0849495a 0x6e7c0849
-+				0x495b6e7c 0x08494959 0x6a7a0849 0x49596a7a 0x084a4a5a 0x6f7d084b 0x4b5c6e7b 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x85848484
-+				0xc3c4c4c5 0xc4c3c33f 0xc3c3c2c2 0xc2c2c03f 0xc3c3c3c4 0xc4c4c33f 0xc2c2c2c2 0xc1c3c1c1
-+				0xc0c08282 0x83848686 0x88880000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00001111 0x00000000
-+				0x8080f703 0x10808080 0x80050d13 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x000000a4 0xce000000 0x0000b684 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>;
- 
- 	led {
- 		led-active-low;
---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
-@@ -55,6 +55,7 @@
- 					partition@c00000 {
- 						label = "fit";
- 						reg = <0xc00000 0x1400000>;
-+						compatible = "denx,fit";
- 					};
- 				};
- 			};
diff --git a/target/linux/mediatek/patches-5.15/196-dts-mt7986a-bpi-r3-mini.patch b/target/linux/mediatek/patches-5.15/196-dts-mt7986a-bpi-r3-mini.patch
deleted file mode 100644
index 6b082b53d8303c..00000000000000
--- a/target/linux/mediatek/patches-5.15/196-dts-mt7986a-bpi-r3-mini.patch
+++ /dev/null
@@ -1,706 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-@@ -585,6 +585,14 @@
- 			status = "disabled";
- 		};
- 
-+		hnat: hnat@15000000 {
-+			compatible = "mediatek,mtk-hnat_v4";
-+			reg = <0 0x15100000 0 0x80000>;
-+			resets = <&ethsys 0>;
-+			reset-names = "mtketh";
-+			status = "disabled";
-+		};
-+
- 		wifi: wifi@18000000 {
- 			compatible = "mediatek,mt7986-wmac";
- 			resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
-@@ -599,6 +607,7 @@
- 				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
- 				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
- 				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
-+			chip_id = <0x7986>;
- 			memory-region = <&wmcpu_emi>;
- 		};
- 	};
---- a/dev/null
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-mini.dts
-@@ -0,0 +1,678 @@
-+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-+/*
-+ * Copyright (C) 2021 MediaTek Inc.
-+ * Authors: Sam.Shih <sam.shih@mediatek.com>
-+ *          Frank Wunderlich <frank-w@public-files.de>
-+ *          Daniel Golle <daniel@makrotopia.org>
-+ */
-+
-+/dts-v1/;
-+#include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/input/input.h>
-+#include <dt-bindings/leds/common.h>
-+#include <dt-bindings/pinctrl/mt65xx.h>
-+
-+#include "mt7986a.dtsi"
-+
-+/ {
-+	model = "Bananapi BPi-R3 mini";
-+	chassis-type = "embedded";
-+	compatible = "bananapi,bpi-r3-mini", "mediatek,mt7986a";
-+
-+	aliases {
-+		serial0 = &uart0;
-+		ethernet0 = &gmac0;
-+		ethernet1 = &gmac1;
-+
-+		led-boot = &status_led;
-+		led-failsafe = &status_led;
-+		led-running = &status_led;
-+		led-upgrade = &status_led;
-+	};
-+
-+	chosen {
-+		stdout-path = "serial0:115200n8";
-+	};
-+
-+	memory {
-+		reg = <0 0x40000000 0 0x80000000>;
-+	};
-+
-+	gpio-keys {
-+		compatible = "gpio-keys";
-+
-+		button-reset {
-+			label = "reset";
-+			linux,code = <KEY_RESTART>;
-+			gpios = <&pio 7 GPIO_ACTIVE_LOW>;
-+		};
-+	};
-+
-+	gpio-leds {
-+		compatible = "gpio-leds";
-+
-+		status_led: led-0 {
-+			label = "green:status";
-+			gpios = <&pio 19 GPIO_ACTIVE_HIGH>;
-+		};
-+
-+		led-1 {
-+			label = "blue:wlan2g";
-+			gpios = <&pio 1 GPIO_ACTIVE_HIGH>;
-+		};
-+
-+		led-2 {
-+			label = "blue:wlan5g";
-+			gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
-+		};
-+	};
-+
-+	reg_1p8v: regulator-1p8v {
-+		compatible = "regulator-fixed";
-+		regulator-name = "fixed-1.8V";
-+		regulator-min-microvolt = <1800000>;
-+		regulator-max-microvolt = <1800000>;
-+		regulator-boot-on;
-+		regulator-always-on;
-+	};
-+
-+	reg_3p3v: regulator-3p3v {
-+		compatible = "regulator-fixed";
-+		regulator-name = "fixed-3.3V";
-+		regulator-min-microvolt = <3300000>;
-+		regulator-max-microvolt = <3300000>;
-+		regulator-boot-on;
-+		regulator-always-on;
-+	};
-+
-+	reg_5v: regulator-5v {
-+		compatible = "regulator-fixed";
-+		regulator-name = "fixed-5V";
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+		regulator-boot-on;
-+		regulator-always-on;
-+	};
-+};
-+
-+&auxadc {
-+	status = "okay";
-+};
-+
-+&watchdog {
-+	status = "okay";
-+};
-+
-+&crypto {
-+	status = "okay";
-+};
-+
-+&eth {
-+	status = "okay";
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&eth_pins>;
-+
-+	gmac0: mac@0 {
-+		compatible = "mediatek,eth-mac";
-+		reg = <0>;
-+		phy-mode = "2500base-x";
-+
-+		fixed-link {
-+			speed = <2500>;
-+			full-duplex;
-+			pause;
-+		};
-+	};
-+
-+	gmac1: mac@1 {
-+		compatible = "mediatek,eth-mac";
-+		reg = <1>;
-+		phy-mode = "2500base-x";
-+
-+		fixed-link {
-+			speed = <2500>;
-+			full-duplex;
-+			pause;
-+		};
-+	};
-+
-+	mdio: mdio-bus {
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+
-+		phy14: phy@14 {
-+			/* EN8811H PHY ID */
-+			compatible = "ethernet-phy-id03a2.a411";
-+			/* PHY Address */
-+			reg = <14>;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&en8811_pwr_a>;
-+
-+			airoha,rx-pol-reverse;
-+
-+			interrupt-parent = <&pio>;
-+			interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
-+			reset-gpios = <&pio 49 1>;     /* GPIO49 */
-+			reset-assert-us = <10000>;
-+			reset-deassert-us = <20000>;
-+
-+			phy-mode = "2500base-x";
-+			full-duplex;
-+			pause;
-+		};
-+
-+		phy15: phy@15 {
-+			/* EN8811H PHY ID */
-+			compatible = "ethernet-phy-id03a2.a411";
-+			/* PHY Address */
-+			reg = <15>;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&en8811_pwr_b>;
-+
-+			airoha,rx-pol-reverse;
-+
-+			interrupt-parent = <&pio>;
-+			interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
-+			reset-gpios = <&pio 47 1>;     /* GPIO47 */
-+			reset-assert-us = <10000>;
-+			reset-deassert-us = <20000>;
-+
-+			phy-mode = "2500base-x";
-+			full-duplex;
-+			pause;
-+		};
-+	};
-+};
-+
-+&hnat {
-+	mtketh-wan = "eth1";
-+	mtketh-lan = "eth0";
-+	mtketh-max-gmac = <2>;
-+	status = "okay";
-+};
-+
-+&i2c0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&i2c_pins>;
-+	status = "okay";
-+
-+	/* MAC Address EEPROM */
-+	eeprom@50 {
-+		compatible = "atmel,24c02";
-+		reg = <0x50>;
-+		pagesize = <8>;
-+		size = <256>;
-+	};
-+
-+	wm8960: wm8960@1a {
-+		compatible = "wlf,wm8960";
-+		reg = <0x1a>;
-+	};
-+};
-+
-+&mmc0 {
-+	pinctrl-names = "default", "state_uhs";
-+	pinctrl-0 = <&mmc0_pins_default>;
-+	pinctrl-1 = <&mmc0_pins_uhs>;
-+	bus-width = <8>;
-+	max-frequency = <200000000>;
-+	cap-mmc-highspeed;
-+	mmc-hs200-1_8v;
-+	mmc-hs400-1_8v;
-+	hs400-ds-delay = <0x14014>;
-+	vmmc-supply = <&reg_3p3v>;
-+	vqmmc-supply = <&reg_1p8v>;
-+	non-removable;
-+	no-sd;
-+	no-sdio;
-+	status = "okay";
-+};
-+
-+&pcie {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&pcie_pins>;
-+	status = "okay";
-+};
-+
-+&pcie_phy {
-+	status = "okay";
-+};
-+
-+&pio {
-+	en8811_pwr_a: en8811-pwr-a {
-+		pins = "GPIO_11";
-+		drive-strength = <8>;
-+		mediatek,pull-down-adv = <1>;
-+		output-low;
-+	};
-+
-+	en8811_pwr_b: en8811-pwr-b {
-+		pins = "GPIO_12";
-+		drive-strength = <8>;
-+		mediatek,pull-down-adv = <1>;
-+		output-low;
-+	};
-+
-+	eth_pins: eth-pins {
-+		mux {
-+			function = "eth";
-+			groups = "mdc_mdio";
-+		};
-+	};
-+
-+	i2c_pins: i2c-pins {
-+		mux {
-+			function = "i2c";
-+			groups = "i2c";
-+		};
-+	};
-+
-+	mmc0_pins_default: mmc0-pins-default {
-+		mux {
-+			function = "emmc";
-+			groups = "emmc_51";
-+		};
-+		conf-cmd-dat {
-+			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
-+			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
-+			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
-+			input-enable;
-+			drive-strength = <4>;
-+			mediatek,pull-up-adv = <1>;
-+		};
-+		conf-clk {
-+			pins = "EMMC_CK";
-+			drive-strength = <6>;
-+			mediatek,pull-down-adv = <2>;
-+		};
-+		conf-ds {
-+			pins = "EMMC_DSL";
-+			mediatek,pull-down-adv = <2>;
-+		};
-+		conf-rst {
-+			pins = "EMMC_RSTB";
-+			drive-strength = <4>;
-+			mediatek,pull-up-adv = <1>;
-+		};
-+	};
-+
-+	mmc0_pins_uhs: mmc0-uhs-pins {
-+		mux {
-+			function = "emmc";
-+			groups = "emmc_51";
-+		};
-+		conf-cmd-dat {
-+			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
-+			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
-+			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
-+			input-enable;
-+			drive-strength = <4>;
-+			mediatek,pull-up-adv = <1>;
-+		};
-+		conf-clk {
-+			pins = "EMMC_CK";
-+			drive-strength = <6>;
-+			mediatek,pull-down-adv = <2>;
-+		};
-+		conf-ds {
-+			pins = "EMMC_DSL";
-+			mediatek,pull-down-adv = <2>;
-+		};
-+		conf-rst {
-+			pins = "EMMC_RSTB";
-+			drive-strength = <4>;
-+			mediatek,pull-up-adv = <1>;
-+		};
-+	};
-+
-+	pcie_pins: pcie-pins {
-+		mux {
-+			function = "pcie";
-+			groups = "pcie_clk", "pcie_wake", "pcie_pereset";
-+		};
-+	};
-+
-+	pwm_pins: pwm-pins {
-+		mux {
-+			function = "pwm";
-+			groups = "pwm0", "pwm1_0";
-+		};
-+	};
-+
-+	spi_flash_pins: spi-flash-pins {
-+		mux {
-+			function = "spi";
-+			groups = "spi0", "spi0_wp_hold";
-+		};
-+		conf-pu {
-+			pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
-+			drive-strength = <8>;
-+			mediatek,pull-up-adv = <0>;
-+		};
-+		conf-pd {
-+			pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
-+			drive-strength = <8>;
-+			mediatek,pull-down-adv = <0>;
-+		};
-+	};
-+
-+	spic_pins: spic-pins {
-+		mux {
-+			function = "spi";
-+			groups = "spi1_2";
-+		};
-+	};
-+
-+	uart1_pins: uart1-pins {
-+		mux {
-+			function = "uart";
-+			groups = "uart1";
-+		};
-+	};
-+
-+	uart2_pins: uart2-pins {
-+		mux {
-+			function = "uart";
-+			groups = "uart2";
-+		};
-+	};
-+
-+	usb_ngff_pins: usb-ngff-pins {
-+		ngff-pe-rst {
-+			pins = "GPIO_7";
-+			drive-strength = <8>;
-+			mediatek,pull-up-adv = <1>;
-+		};
-+		ngff-wwan-off {
-+			pins = "GPIO_8";
-+			drive-strength = <8>;
-+			mediatek,pull-up-adv = <1>;
-+		};
-+		ngff-pwr-off {
-+			pins = "GPIO_9";
-+			drive-strength = <8>;
-+			mediatek,pull-up-adv = <1>;
-+		};
-+		ngff-rst {
-+			pins = "GPIO_10";
-+			drive-strength = <8>;
-+			mediatek,pull-up-adv = <1>;
-+		};
-+	};
-+
-+	usb_pwwr_en: usb-pwwr-en {
-+		pins = "GPIO_15";
-+		drive-strength = <8>;
-+		mediatek,pull-down-adv = <1>;
-+	};
-+
-+	wf_2g_5g_pins: wf-2g-5g-pins {
-+		mux {
-+			function = "wifi";
-+			groups = "wf_2g", "wf_5g";
-+		};
-+		conf {
-+			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
-+			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
-+			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
-+			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
-+			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
-+			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
-+			       "WF1_TOP_CLK", "WF1_TOP_DATA";
-+			drive-strength = <4>;
-+		};
-+	};
-+
-+	wf_dbdc_pins: wf-dbdc-pins {
-+		mux {
-+			function = "wifi";
-+			groups = "wf_dbdc";
-+		};
-+		conf {
-+			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
-+			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
-+			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
-+			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
-+			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
-+			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
-+			       "WF1_TOP_CLK", "WF1_TOP_DATA";
-+			drive-strength = <4>;
-+		};
-+	};
-+};
-+
-+&pwm {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&pwm_pins>;
-+	status = "okay";
-+};
-+
-+&spi0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&spi_flash_pins>;
-+	cs-gpios = <0>, <0>;
-+	status = "okay";
-+
-+	flash@0 {
-+		compatible = "spi-nand";
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+		reg = <0>;
-+
-+		spi-max-frequency = <52000000>;
-+		spi-tx-bus-width = <4>;
-+		spi-rx-bus-width = <4>;
-+
-+		partitions {
-+			compatible = "fixed-partitions";
-+			#address-cells = <1>;
-+			#size-cells = <1>;
-+
-+			partition@0 {
-+				label = "bl2";
-+				reg = <0x00000 0x100000>;
-+				read-only;
-+			};
-+
-+			partition@100000 {
-+				label = "u-boot-env";
-+				reg = <0x100000 0x80000>;
-+			};
-+
-+			partition@180000 {
-+				label = "factory";
-+				reg = <0x180000 0x200000>;
-+			};
-+
-+			partition@380000 {
-+				label = "fip";
-+				reg = <0x380000 0x200000>;
-+				read-only;
-+			};
-+
-+			partition@580000 {
-+				label = "ubi";
-+				reg = <0x580000 0x7a80000>;
-+			};
-+		};
-+	};
-+};
-+
-+&spi1 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&spic_pins>;
-+	status = "okay";
-+};
-+
-+&ssusb {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&usb_pwwr_en>;
-+	pinctrl-1 = <&usb_ngff_pins>;
-+	vusb33-supply = <&reg_3p3v>;
-+	vbus-supply = <&reg_5v>;
-+	status = "okay";
-+};
-+
-+&trng {
-+	status = "okay";
-+};
-+
-+&uart0 {
-+	status = "okay";
-+};
-+
-+&uart1 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&uart1_pins>;
-+	status = "okay";
-+};
-+
-+&uart2 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&uart2_pins>;
-+	status = "disabled";
-+};
-+
-+&usb_phy {
-+	status = "okay";
-+};
-+
-+&watchdog {
-+	status = "okay";
-+};
-+
-+&wifi {
-+	pinctrl-names = "default", "dbdc";
-+	pinctrl-0 = <&wf_2g_5g_pins>;
-+	pinctrl-1 = <&wf_dbdc_pins>;
-+	status = "okay";
-+
-+	mediatek,eeprom-data = <0x86790200 0x000c4326 0x60000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x125b486c 0x00280000 0x05d00000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x0c000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000012 0x12120000 0x00000000 0x00000000 0x00002222 0x22223333 0x33333333
-+				0x33333333 0x33333333 0x33333333 0x33333333 0x33333333 0x33330000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00292929 0x29282828 0x28282828 0x28282828 0x28282828 0x28282828 0x28000000 0x00000000
-+				0x00000000 0x00242424 0x24222222 0x22242424 0x24222222 0x22242424 0x24222222 0x22242424
-+				0x24222222 0x22000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x007f7f7f 0xd1d1dddd 0xe9e9f5f5 0x01010909 0x1515d1d1 0xdddde9e9 0xf5f5fdfd
-+				0x09091515 0xd1d1dddd 0xe9e9f5f5 0xfdfd0909 0x1515d1d1 0xdddde9e9 0xf5f5fdfd 0x09091515
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x0efefc00 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x021e021e 0x02000200 0x02370237 0x02370237
-+				0x02370237 0x02370237 0x02370237 0x02370237 0x02370237 0x02370237 0x02370237 0x02370237
-+				0x02370237 0x02370237 0x02370237 0x02370237 0x002200c6 0xc6c4c4c3 0x0000c1c2 0xc1838383
-+				0x838686c1 0xc1838383 0x838686c2 0xc1c18181 0x82838585 0x8686c1c1 0x81818283 0x85858686
-+				0xc1c18181 0x82838585 0x8686c1c1 0x81818283 0x85858686 0xc1c18181 0x82838585 0x8686c5c5
-+				0xc3c100c2 0xc3c2c200 0x81828383 0xc2c2c200 0x81828383 0xc3c1c1c1 0x81828384 0x84c2c2c2
-+				0xc2008182 0x83838585 0xc2c2c200 0x81828383 0x8585c1c1 0xc1818283 0x84848686 0x82828484
-+				0x85868787 0x8989c2c2 0xc2008182 0x83838585 0xc2c2c200 0x81828383 0x8585c2c2 0xc2008182
-+				0x83838585 0xc4c4c2c1 0x00c3c3c3 0xc1008183 0x838686c3 0xc3c3c100 0x81838386 0x86c2c2c2
-+				0x00818284 0x84868682 0x82828485 0x8688888b 0x8bc3c3c3 0xc1008183 0x838686c3 0xc3c3c100
-+				0x81838386 0x86c3c3c3 0xc1008183 0x83868600 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00bd0000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00c50000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00495256 0x55555555 0x004a5251 0x51515151 0x004a5355 0x56565656 0x0049504e 0x51515151
-+				0x00495150 0x54545454 0x00495051 0x51515151 0x00495251 0x50505050 0x00495251 0x51515151
-+				0x00495251 0x54545454 0x00495150 0x54545454 0x00495352 0x51515151 0x00495353 0x52525252
-+				0x00495150 0x50505050 0x00495152 0x54545454 0x00495251 0x53535353 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0xd1d1dddd 0xe9e9f5f5 0xfdfd1414 0x1d1d0000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x85840000 0xc3c4c382 0x828281c1 0xc4c5c400 0x0000c1c3 0xc4c4c481 0x8181c1c2 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0xc0bbc0bb 0xc0bbc0bb 0x40c5c0c4 0xc0c3c0c3 0x40c340c5 0x40c4c0c3 0x40c3c0c2 0xc0c5c0c4
-+				0x40c440c4 0xc0c3c0c5 0xc0c440c4 0x40c4c0c3 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x40c640c6 0x40c640c6 0x40c640c6 0x40c640c6 0x40c640c6 0x40c640c6
-+				0x40c640c6 0x40c640c6 0x40c640c6 0x40c640c6 0x40c640c6 0x40c640c6 0x40c640c6 0x40c640c6
-+				0x40c640c6 0x40c640c6 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>;
-+};
diff --git a/target/linux/mediatek/patches-5.15/200-phy-phy-mtk-tphy-Add-hifsys-support.patch b/target/linux/mediatek/patches-5.15/200-phy-phy-mtk-tphy-Add-hifsys-support.patch
deleted file mode 100644
index cfb0556d1efd9c..00000000000000
--- a/target/linux/mediatek/patches-5.15/200-phy-phy-mtk-tphy-Add-hifsys-support.patch
+++ /dev/null
@@ -1,66 +0,0 @@
-From 28f9a5e2a3f5441ab5594669ed82da11e32277a9 Mon Sep 17 00:00:00 2001
-From: Kristian Evensen <kristian.evensen@gmail.com>
-Date: Mon, 30 Apr 2018 14:38:01 +0200
-Subject: [PATCH] phy: phy-mtk-tphy: Add hifsys-support
-
----
- drivers/phy/mediatek/phy-mtk-tphy.c | 20 ++++++++++++++++++++
- 1 file changed, 20 insertions(+)
-
---- a/drivers/phy/mediatek/phy-mtk-tphy.c
-+++ b/drivers/phy/mediatek/phy-mtk-tphy.c
-@@ -18,6 +18,8 @@
- #include <linux/phy/phy.h>
- #include <linux/platform_device.h>
- #include <linux/regmap.h>
-+#include <linux/mfd/syscon.h>
-+#include <linux/regmap.h>
- 
- /* version V1 sub-banks offset base address */
- /* banks shared by multiple phys */
-@@ -311,6 +313,9 @@
- 
- #define TPHY_CLKS_CNT	2
- 
-+#define HIF_SYSCFG1			0x14
-+#define HIF_SYSCFG1_PHY2_MASK		(0x3 << 20)
-+
- enum mtk_phy_version {
- 	MTK_PHY_V1 = 1,
- 	MTK_PHY_V2,
-@@ -377,6 +382,7 @@ struct mtk_tphy {
- 	void __iomem *sif_base;	/* only shared sif */
- 	const struct mtk_phy_pdata *pdata;
- 	struct mtk_phy_instance **phys;
-+	struct regmap *hif;
- 	int nphys;
- 	int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */
- 	int src_coef; /* coefficient for slew rate calibrate */
-@@ -730,6 +736,10 @@ static void pcie_phy_instance_init(struc
- 	if (tphy->pdata->version != MTK_PHY_V1)
- 		return;
- 
-+	if (tphy->hif)
-+		regmap_update_bits(tphy->hif, HIF_SYSCFG1,
-+				   HIF_SYSCFG1_PHY2_MASK, 0);
-+
- 	tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0);
- 	tmp &= ~(P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H);
- 	tmp |= P3A_RG_XTAL_EXT_PE1H_VAL(0x2) | P3A_RG_XTAL_EXT_PE2H_VAL(0x2);
-@@ -1437,6 +1447,16 @@ static int mtk_tphy_probe(struct platfor
- 					 &tphy->src_coef);
- 	}
- 
-+	if (of_find_property(np, "mediatek,phy-switch", NULL)) {
-+		tphy->hif = syscon_regmap_lookup_by_phandle(np,
-+							    "mediatek,phy-switch");
-+		if (IS_ERR(tphy->hif)) {
-+			dev_err(&pdev->dev,
-+				"missing \"mediatek,phy-switch\" phandle\n");
-+			return PTR_ERR(tphy->hif);
-+		}
-+	}
-+
- 	port = 0;
- 	for_each_child_of_node(np, child_np) {
- 		struct mtk_phy_instance *instance;
diff --git a/target/linux/mediatek/patches-5.15/210-v6.1-pinctrl-mediatek-add-support-for-MT7986-SoC.patch b/target/linux/mediatek/patches-5.15/210-v6.1-pinctrl-mediatek-add-support-for-MT7986-SoC.patch
deleted file mode 100644
index 0761e1da18080c..00000000000000
--- a/target/linux/mediatek/patches-5.15/210-v6.1-pinctrl-mediatek-add-support-for-MT7986-SoC.patch
+++ /dev/null
@@ -1,26 +0,0 @@
---- a/drivers/pinctrl/mediatek/Kconfig
-+++ b/drivers/pinctrl/mediatek/Kconfig
-@@ -120,6 +120,13 @@ config PINCTRL_MT7622
- 	default ARM64 && ARCH_MEDIATEK
- 	select PINCTRL_MTK_MOORE
- 
-+config PINCTRL_MT7986
-+	bool "Mediatek MT7986 pin control"
-+	depends on OF
-+	depends on ARM64 || COMPILE_TEST
-+	default ARM64 && ARCH_MEDIATEK
-+	select PINCTRL_MTK_MOORE
-+
- config PINCTRL_MT8167
- 	bool "Mediatek MT8167 pin control"
- 	depends on OF
---- a/drivers/pinctrl/mediatek/Makefile
-+++ b/drivers/pinctrl/mediatek/Makefile
-@@ -17,6 +17,7 @@ obj-$(CONFIG_PINCTRL_MT6797)	+= pinctrl-
- obj-$(CONFIG_PINCTRL_MT7622)	+= pinctrl-mt7622.o
- obj-$(CONFIG_PINCTRL_MT7623)	+= pinctrl-mt7623.o
- obj-$(CONFIG_PINCTRL_MT7629)	+= pinctrl-mt7629.o
-+obj-$(CONFIG_PINCTRL_MT7986)	+= pinctrl-mt7986.o
- obj-$(CONFIG_PINCTRL_MT8167)	+= pinctrl-mt8167.o
- obj-$(CONFIG_PINCTRL_MT8173)	+= pinctrl-mt8173.o
- obj-$(CONFIG_PINCTRL_MT8183)	+= pinctrl-mt8183.o
diff --git a/target/linux/mediatek/patches-5.15/211-v5.16-clk-mediatek-Add-API-for-clock-resource-recycle.patch b/target/linux/mediatek/patches-5.15/211-v5.16-clk-mediatek-Add-API-for-clock-resource-recycle.patch
deleted file mode 100644
index 15de8aa3d49ca6..00000000000000
--- a/target/linux/mediatek/patches-5.15/211-v5.16-clk-mediatek-Add-API-for-clock-resource-recycle.patch
+++ /dev/null
@@ -1,28 +0,0 @@
---- a/drivers/clk/mediatek/clk-mtk.c
-+++ b/drivers/clk/mediatek/clk-mtk.c
-@@ -43,6 +43,15 @@ err_out:
- 	return NULL;
- }
- 
-+void mtk_free_clk_data(struct clk_onecell_data *clk_data)
-+{
-+	if (!clk_data)
-+		return;
-+
-+	kfree(clk_data->clks);
-+	kfree(clk_data);
-+}
-+
- void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks,
- 		int num, struct clk_onecell_data *clk_data)
- {
---- a/drivers/clk/mediatek/clk-mtk.h
-+++ b/drivers/clk/mediatek/clk-mtk.h
-@@ -202,6 +202,7 @@ void mtk_clk_register_dividers(const str
- 				struct clk_onecell_data *clk_data);
- 
- struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num);
-+void mtk_free_clk_data(struct clk_onecell_data *clk_data);
- 
- #define HAVE_RST_BAR	BIT(0)
- #define PLL_AO		BIT(1)
diff --git a/target/linux/mediatek/patches-5.15/212-v5.17-clk-mediatek-add-mt7986-clock-support.patch b/target/linux/mediatek/patches-5.15/212-v5.17-clk-mediatek-add-mt7986-clock-support.patch
deleted file mode 100644
index 8e2365a498e8b8..00000000000000
--- a/target/linux/mediatek/patches-5.15/212-v5.17-clk-mediatek-add-mt7986-clock-support.patch
+++ /dev/null
@@ -1,39 +0,0 @@
---- a/drivers/clk/mediatek/Kconfig
-+++ b/drivers/clk/mediatek/Kconfig
-@@ -344,6 +344,23 @@ config COMMON_CLK_MT7629_HIFSYS
- 	  This driver supports MediaTek MT7629 HIFSYS clocks providing
- 	  to PCI-E and USB.
- 
-+config COMMON_CLK_MT7986
-+	bool "Clock driver for MediaTek MT7986"
-+	depends on ARCH_MEDIATEK || COMPILE_TEST
-+	select COMMON_CLK_MEDIATEK
-+	default ARCH_MEDIATEK
-+	help
-+	  This driver supports MediaTek MT7986 basic clocks and clocks
-+	  required for various periperals found on MediaTek.
-+
-+config COMMON_CLK_MT7986_ETHSYS
-+	bool "Clock driver for MediaTek MT7986 ETHSYS"
-+	depends on COMMON_CLK_MT7986
-+	default COMMON_CLK_MT7986
-+	help
-+	  This driver add support for clocks for Ethernet and SGMII
-+	  required on MediaTek MT7986 SoC.
-+
- config COMMON_CLK_MT8135
- 	bool "Clock driver for MediaTek MT8135"
- 	depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST
---- a/drivers/clk/mediatek/Makefile
-+++ b/drivers/clk/mediatek/Makefile
-@@ -46,6 +46,10 @@ obj-$(CONFIG_COMMON_CLK_MT7622_AUDSYS) +
- obj-$(CONFIG_COMMON_CLK_MT7629) += clk-mt7629.o
- obj-$(CONFIG_COMMON_CLK_MT7629_ETHSYS) += clk-mt7629-eth.o
- obj-$(CONFIG_COMMON_CLK_MT7629_HIFSYS) += clk-mt7629-hif.o
-+obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-apmixed.o
-+obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o
-+obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o
-+obj-$(CONFIG_COMMON_CLK_MT7986_ETHSYS) += clk-mt7986-eth.o
- obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
- obj-$(CONFIG_COMMON_CLK_MT8167) += clk-mt8167.o
- obj-$(CONFIG_COMMON_CLK_MT8167_AUDSYS) += clk-mt8167-aud.o
diff --git a/target/linux/mediatek/patches-5.15/213-spi-mediatek-add-mt7986-spi-support.patch b/target/linux/mediatek/patches-5.15/213-spi-mediatek-add-mt7986-spi-support.patch
deleted file mode 100644
index 04da1765f37873..00000000000000
--- a/target/linux/mediatek/patches-5.15/213-spi-mediatek-add-mt7986-spi-support.patch
+++ /dev/null
@@ -1,917 +0,0 @@
-From 7d99750f96fc6904d54affebdc8c9b0bfae1e9e8 Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Sun, 17 Apr 2022 11:40:22 +0800
-Subject: [PATCH] spi: mediatek: backport document and driver to support mt7986
- spi design
-
-this patch add the support of ipm design and upgrade devicetree binding
-
-The patch is comming from following threads
-- https://lore.kernel.org/all/20220315032411.2826-1-leilk.liu@mediatek.com/
-- https://lore.kernel.org/all/20220401071616.8874-1-leilk.liu@mediatek.com/
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
----
- .../bindings/spi/mediatek,spi-mt65xx.yaml     | 111 ++++
- drivers/spi/spi-mt65xx.c                      | 509 ++++++++++++++++--
- 2 files changed, 572 insertions(+), 48 deletions(-)
- create mode 100644 Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml
-@@ -0,0 +1,111 @@
-+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/spi/mediatek,spi-mt65xx.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: SPI Bus controller for MediaTek ARM SoCs
-+
-+maintainers:
-+  - Leilk Liu <leilk.liu@mediatek.com>
-+
-+allOf:
-+  - $ref: "/schemas/spi/spi-controller.yaml#"
-+
-+properties:
-+  compatible:
-+    oneOf:
-+      - items:
-+          - enum:
-+              - mediatek,mt7629-spi
-+          - const: mediatek,mt7622-spi
-+      - items:
-+          - enum:
-+              - mediatek,mt8516-spi
-+          - const: mediatek,mt2712-spi
-+      - items:
-+          - enum:
-+              - mediatek,mt6779-spi
-+              - mediatek,mt8186-spi
-+              - mediatek,mt8192-spi
-+              - mediatek,mt8195-spi
-+          - const: mediatek,mt6765-spi
-+      - items:
-+          - enum:
-+              - mediatek,mt7986-spi-ipm
-+          - const: mediatek,spi-ipm
-+      - items:
-+          - enum:
-+              - mediatek,mt2701-spi
-+              - mediatek,mt2712-spi
-+              - mediatek,mt6589-spi
-+              - mediatek,mt6765-spi
-+              - mediatek,mt6893-spi
-+              - mediatek,mt7622-spi
-+              - mediatek,mt8135-spi
-+              - mediatek,mt8173-spi
-+              - mediatek,mt8183-spi
-+
-+  reg:
-+    maxItems: 1
-+
-+  interrupts:
-+    maxItems: 1
-+
-+  clocks:
-+    minItems: 3
-+    items:
-+      - description: clock used for the parent clock
-+      - description: clock used for the muxes clock
-+      - description: clock used for the clock gate
-+      - description: clock used for the AHB bus, this clock is optional
-+
-+  clock-names:
-+    minItems: 3
-+    items:
-+      - const: parent-clk
-+      - const: sel-clk
-+      - const: spi-clk
-+      - const: hclk
-+
-+  mediatek,pad-select:
-+    $ref: /schemas/types.yaml#/definitions/uint32-array
-+    minItems: 1
-+    maxItems: 4
-+    items:
-+      enum: [0, 1, 2, 3]
-+    description:
-+      specify which pins group(ck/mi/mo/cs) spi controller used.
-+      This is an array.
-+
-+required:
-+  - compatible
-+  - reg
-+  - interrupts
-+  - clocks
-+  - clock-names
-+  - '#address-cells'
-+  - '#size-cells'
-+
-+unevaluatedProperties: false
-+
-+examples:
-+  - |
-+    #include <dt-bindings/clock/mt8173-clk.h>
-+    #include <dt-bindings/gpio/gpio.h>
-+    #include <dt-bindings/interrupt-controller/arm-gic.h>
-+    #include <dt-bindings/interrupt-controller/irq.h>
-+
-+    spi@1100a000 {
-+      compatible = "mediatek,mt8173-spi";
-+      #address-cells = <1>;
-+      #size-cells = <0>;
-+      reg = <0x1100a000 0x1000>;
-+      interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
-+      clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
-+               <&topckgen CLK_TOP_SPI_SEL>,
-+               <&pericfg CLK_PERI_SPI0>;
-+      clock-names = "parent-clk", "sel-clk", "spi-clk";
-+      cs-gpios = <&pio 105 GPIO_ACTIVE_LOW>, <&pio 72 GPIO_ACTIVE_LOW>;
-+      mediatek,pad-select = <1>, <0>;
-+    };
---- a/drivers/spi/spi-mt65xx.c
-+++ b/drivers/spi/spi-mt65xx.c
-@@ -12,11 +12,12 @@
- #include <linux/ioport.h>
- #include <linux/module.h>
- #include <linux/of.h>
--#include <linux/of_gpio.h>
-+#include <linux/gpio/consumer.h>
- #include <linux/platform_device.h>
- #include <linux/platform_data/spi-mt65xx.h>
- #include <linux/pm_runtime.h>
- #include <linux/spi/spi.h>
-+#include <linux/spi/spi-mem.h>
- #include <linux/dma-mapping.h>
- 
- #define SPI_CFG0_REG                      0x0000
-@@ -31,6 +32,7 @@
- #define SPI_CFG2_REG                      0x0028
- #define SPI_TX_SRC_REG_64                 0x002c
- #define SPI_RX_DST_REG_64                 0x0030
-+#define SPI_CFG3_IPM_REG                  0x0040
- 
- #define SPI_CFG0_SCK_HIGH_OFFSET          0
- #define SPI_CFG0_SCK_LOW_OFFSET           8
-@@ -51,6 +53,7 @@
- #define SPI_CFG1_CS_IDLE_MASK             0xff
- #define SPI_CFG1_PACKET_LOOP_MASK         0xff00
- #define SPI_CFG1_PACKET_LENGTH_MASK       0x3ff0000
-+#define SPI_CFG1_IPM_PACKET_LENGTH_MASK   GENMASK(31, 16)
- #define SPI_CFG2_SCK_HIGH_OFFSET          0
- #define SPI_CFG2_SCK_LOW_OFFSET           16
- 
-@@ -71,6 +74,24 @@
- #define SPI_CMD_TX_ENDIAN            BIT(15)
- #define SPI_CMD_FINISH_IE            BIT(16)
- #define SPI_CMD_PAUSE_IE             BIT(17)
-+#define SPI_CMD_IPM_NONIDLE_MODE     BIT(19)
-+#define SPI_CMD_IPM_SPIM_LOOP        BIT(21)
-+#define SPI_CMD_IPM_GET_TICKDLY_OFFSET    22
-+
-+#define SPI_CMD_IPM_GET_TICKDLY_MASK	GENMASK(24, 22)
-+
-+#define PIN_MODE_CFG(x)	((x) / 2)
-+
-+#define SPI_CFG3_IPM_HALF_DUPLEX_DIR		BIT(2)
-+#define SPI_CFG3_IPM_HALF_DUPLEX_EN		BIT(3)
-+#define SPI_CFG3_IPM_XMODE_EN			BIT(4)
-+#define SPI_CFG3_IPM_NODATA_FLAG		BIT(5)
-+#define SPI_CFG3_IPM_CMD_BYTELEN_OFFSET		8
-+#define SPI_CFG3_IPM_ADDR_BYTELEN_OFFSET	12
-+
-+#define SPI_CFG3_IPM_CMD_PIN_MODE_MASK		GENMASK(1, 0)
-+#define SPI_CFG3_IPM_CMD_BYTELEN_MASK		GENMASK(11, 8)
-+#define SPI_CFG3_IPM_ADDR_BYTELEN_MASK		GENMASK(15, 12)
- 
- #define MT8173_SPI_MAX_PAD_SEL 3
- 
-@@ -81,6 +102,9 @@
- 
- #define MTK_SPI_MAX_FIFO_SIZE 32U
- #define MTK_SPI_PACKET_SIZE 1024
-+#define MTK_SPI_IPM_PACKET_SIZE SZ_64K
-+#define MTK_SPI_IPM_PACKET_LOOP SZ_256
-+
- #define MTK_SPI_32BITS_MASK  (0xffffffff)
- 
- #define DMA_ADDR_EXT_BITS (36)
-@@ -96,6 +120,8 @@ struct mtk_spi_compatible {
- 	bool dma_ext;
- 	/* some IC no need unprepare SPI clk */
- 	bool no_need_unprepare;
-+	/* IPM design adjust and extend register to support more features */
-+	bool ipm_design;
- };
- 
- struct mtk_spi {
-@@ -103,7 +129,7 @@ struct mtk_spi {
- 	u32 state;
- 	int pad_num;
- 	u32 *pad_sel;
--	struct clk *parent_clk, *sel_clk, *spi_clk;
-+	struct clk *parent_clk, *sel_clk, *spi_clk, *spi_hclk;
- 	struct spi_transfer *cur_transfer;
- 	u32 xfer_len;
- 	u32 num_xfered;
-@@ -111,6 +137,11 @@ struct mtk_spi {
- 	u32 tx_sgl_len, rx_sgl_len;
- 	const struct mtk_spi_compatible *dev_comp;
- 	u32 spi_clk_hz;
-+	struct completion spimem_done;
-+	bool use_spimem;
-+	struct device *dev;
-+	dma_addr_t tx_dma;
-+	dma_addr_t rx_dma;
- };
- 
- static const struct mtk_spi_compatible mtk_common_compat;
-@@ -119,6 +150,12 @@ static const struct mtk_spi_compatible m
- 	.must_tx = true,
- };
- 
-+static const struct mtk_spi_compatible mtk_ipm_compat = {
-+	.enhance_timing = true,
-+	.dma_ext = true,
-+	.ipm_design = true,
-+};
-+
- static const struct mtk_spi_compatible mt6765_compat = {
- 	.need_pad_sel = true,
- 	.must_tx = true,
-@@ -160,6 +197,9 @@ static const struct mtk_chip_config mtk_
- };
- 
- static const struct of_device_id mtk_spi_of_match[] = {
-+	{ .compatible = "mediatek,spi-ipm",
-+		.data = (void *)&mtk_ipm_compat,
-+	},
- 	{ .compatible = "mediatek,mt2701-spi",
- 		.data = (void *)&mtk_common_compat,
- 	},
-@@ -278,12 +318,11 @@ static int mtk_spi_set_hw_cs_timing(stru
- 	return 0;
- }
- 
--static int mtk_spi_prepare_message(struct spi_master *master,
--				   struct spi_message *msg)
-+static int mtk_spi_hw_init(struct spi_master *master,
-+			   struct spi_device *spi)
- {
- 	u16 cpha, cpol;
- 	u32 reg_val;
--	struct spi_device *spi = msg->spi;
- 	struct mtk_chip_config *chip_config = spi->controller_data;
- 	struct mtk_spi *mdata = spi_master_get_devdata(master);
- 
-@@ -291,6 +330,15 @@ static int mtk_spi_prepare_message(struc
- 	cpol = spi->mode & SPI_CPOL ? 1 : 0;
- 
- 	reg_val = readl(mdata->base + SPI_CMD_REG);
-+	if (mdata->dev_comp->ipm_design) {
-+		/* SPI transfer without idle time until packet length done */
-+		reg_val |= SPI_CMD_IPM_NONIDLE_MODE;
-+		if (spi->mode & SPI_LOOP)
-+			reg_val |= SPI_CMD_IPM_SPIM_LOOP;
-+		else
-+			reg_val &= ~SPI_CMD_IPM_SPIM_LOOP;
-+	}
-+
- 	if (cpha)
- 		reg_val |= SPI_CMD_CPHA;
- 	else
-@@ -348,23 +396,39 @@ static int mtk_spi_prepare_message(struc
- 		       mdata->base + SPI_PAD_SEL_REG);
- 
- 	/* tick delay */
--	reg_val = readl(mdata->base + SPI_CFG1_REG);
- 	if (mdata->dev_comp->enhance_timing) {
--		reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK;
--		reg_val |= ((chip_config->tick_delay & 0x7)
--			    << SPI_CFG1_GET_TICK_DLY_OFFSET);
-+		if (mdata->dev_comp->ipm_design) {
-+			reg_val = readl(mdata->base + SPI_CMD_REG);
-+			reg_val &= ~SPI_CMD_IPM_GET_TICKDLY_MASK;
-+			reg_val |= ((chip_config->tick_delay & 0x7)
-+				    << SPI_CMD_IPM_GET_TICKDLY_OFFSET);
-+			writel(reg_val, mdata->base + SPI_CMD_REG);
-+		} else {
-+			reg_val = readl(mdata->base + SPI_CFG1_REG);
-+			reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK;
-+			reg_val |= ((chip_config->tick_delay & 0x7)
-+				    << SPI_CFG1_GET_TICK_DLY_OFFSET);
-+			writel(reg_val, mdata->base + SPI_CFG1_REG);
-+		}
- 	} else {
-+		reg_val = readl(mdata->base + SPI_CFG1_REG);
- 		reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK_V1;
- 		reg_val |= ((chip_config->tick_delay & 0x3)
- 			    << SPI_CFG1_GET_TICK_DLY_OFFSET_V1);
-+		writel(reg_val, mdata->base + SPI_CFG1_REG);
- 	}
--	writel(reg_val, mdata->base + SPI_CFG1_REG);
- 
- 	/* set hw cs timing */
- 	mtk_spi_set_hw_cs_timing(spi);
- 	return 0;
- }
- 
-+static int mtk_spi_prepare_message(struct spi_master *master,
-+				   struct spi_message *msg)
-+{
-+	return mtk_spi_hw_init(master, msg->spi);
-+}
-+
- static void mtk_spi_set_cs(struct spi_device *spi, bool enable)
- {
- 	u32 reg_val;
-@@ -386,13 +450,13 @@ static void mtk_spi_set_cs(struct spi_de
- }
- 
- static void mtk_spi_prepare_transfer(struct spi_master *master,
--				     struct spi_transfer *xfer)
-+				     u32 speed_hz)
- {
- 	u32 div, sck_time, reg_val;
- 	struct mtk_spi *mdata = spi_master_get_devdata(master);
- 
--	if (xfer->speed_hz < mdata->spi_clk_hz / 2)
--		div = DIV_ROUND_UP(mdata->spi_clk_hz, xfer->speed_hz);
-+	if (speed_hz < mdata->spi_clk_hz / 2)
-+		div = DIV_ROUND_UP(mdata->spi_clk_hz, speed_hz);
- 	else
- 		div = 1;
- 
-@@ -423,12 +487,24 @@ static void mtk_spi_setup_packet(struct
- 	u32 packet_size, packet_loop, reg_val;
- 	struct mtk_spi *mdata = spi_master_get_devdata(master);
- 
--	packet_size = min_t(u32, mdata->xfer_len, MTK_SPI_PACKET_SIZE);
-+	if (mdata->dev_comp->ipm_design)
-+		packet_size = min_t(u32,
-+				    mdata->xfer_len,
-+				    MTK_SPI_IPM_PACKET_SIZE);
-+	else
-+		packet_size = min_t(u32,
-+				    mdata->xfer_len,
-+				    MTK_SPI_PACKET_SIZE);
-+
- 	packet_loop = mdata->xfer_len / packet_size;
- 
- 	reg_val = readl(mdata->base + SPI_CFG1_REG);
--	reg_val &= ~(SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK);
-+	if (mdata->dev_comp->ipm_design)
-+		reg_val &= ~SPI_CFG1_IPM_PACKET_LENGTH_MASK;
-+	else
-+		reg_val &= ~SPI_CFG1_PACKET_LENGTH_MASK;
- 	reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET;
-+	reg_val &= ~SPI_CFG1_PACKET_LOOP_MASK;
- 	reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET;
- 	writel(reg_val, mdata->base + SPI_CFG1_REG);
- }
-@@ -523,7 +599,7 @@ static int mtk_spi_fifo_transfer(struct
- 	mdata->cur_transfer = xfer;
- 	mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, xfer->len);
- 	mdata->num_xfered = 0;
--	mtk_spi_prepare_transfer(master, xfer);
-+	mtk_spi_prepare_transfer(master, xfer->speed_hz);
- 	mtk_spi_setup_packet(master);
- 
- 	if (xfer->tx_buf) {
-@@ -556,7 +632,7 @@ static int mtk_spi_dma_transfer(struct s
- 	mdata->cur_transfer = xfer;
- 	mdata->num_xfered = 0;
- 
--	mtk_spi_prepare_transfer(master, xfer);
-+	mtk_spi_prepare_transfer(master, xfer->speed_hz);
- 
- 	cmd = readl(mdata->base + SPI_CMD_REG);
- 	if (xfer->tx_buf)
-@@ -591,6 +667,19 @@ static int mtk_spi_transfer_one(struct s
- 				struct spi_device *spi,
- 				struct spi_transfer *xfer)
- {
-+	struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
-+	u32 reg_val = 0;
-+
-+	/* prepare xfer direction and duplex mode */
-+	if (mdata->dev_comp->ipm_design) {
-+		if (!xfer->tx_buf || !xfer->rx_buf) {
-+			reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN;
-+			if (xfer->rx_buf)
-+				reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR;
-+		}
-+		writel(reg_val, mdata->base + SPI_CFG3_IPM_REG);
-+	}
-+
- 	if (master->can_dma(master, spi, xfer))
- 		return mtk_spi_dma_transfer(master, spi, xfer);
- 	else
-@@ -614,8 +703,9 @@ static int mtk_spi_setup(struct spi_devi
- 	if (!spi->controller_data)
- 		spi->controller_data = (void *)&mtk_default_chip_info;
- 
--	if (mdata->dev_comp->need_pad_sel && gpio_is_valid(spi->cs_gpio))
--		gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
-+	if (mdata->dev_comp->need_pad_sel && spi->cs_gpiod)
-+		/* CS de-asserted, gpiolib will handle inversion */
-+		gpiod_direction_output(spi->cs_gpiod, 0);
- 
- 	return 0;
- }
-@@ -633,6 +723,12 @@ static irqreturn_t mtk_spi_interrupt(int
- 	else
- 		mdata->state = MTK_SPI_IDLE;
- 
-+	/* SPI-MEM ops */
-+	if (mdata->use_spimem) {
-+		complete(&mdata->spimem_done);
-+		return IRQ_HANDLED;
-+	}
-+
- 	if (!master->can_dma(master, NULL, trans)) {
- 		if (trans->rx_buf) {
- 			cnt = mdata->xfer_len / 4;
-@@ -716,6 +812,274 @@ static irqreturn_t mtk_spi_interrupt(int
- 	return IRQ_HANDLED;
- }
- 
-+static int mtk_spi_mem_adjust_op_size(struct spi_mem *mem,
-+				      struct spi_mem_op *op)
-+{
-+	int opcode_len;
-+
-+	if (op->data.dir != SPI_MEM_NO_DATA) {
-+		opcode_len = 1 + op->addr.nbytes + op->dummy.nbytes;
-+		if (opcode_len + op->data.nbytes > MTK_SPI_IPM_PACKET_SIZE) {
-+			op->data.nbytes = MTK_SPI_IPM_PACKET_SIZE - opcode_len;
-+			/* force data buffer dma-aligned. */
-+			op->data.nbytes -= op->data.nbytes % 4;
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static bool mtk_spi_mem_supports_op(struct spi_mem *mem,
-+				    const struct spi_mem_op *op)
-+{
-+	if (!spi_mem_default_supports_op(mem, op))
-+		return false;
-+
-+	if (op->addr.nbytes && op->dummy.nbytes &&
-+	    op->addr.buswidth != op->dummy.buswidth)
-+		return false;
-+
-+	if (op->addr.nbytes + op->dummy.nbytes > 16)
-+		return false;
-+
-+	if (op->data.nbytes > MTK_SPI_IPM_PACKET_SIZE) {
-+		if (op->data.nbytes / MTK_SPI_IPM_PACKET_SIZE >
-+		    MTK_SPI_IPM_PACKET_LOOP ||
-+		    op->data.nbytes % MTK_SPI_IPM_PACKET_SIZE != 0)
-+			return false;
-+	}
-+
-+	return true;
-+}
-+
-+static void mtk_spi_mem_setup_dma_xfer(struct spi_master *master,
-+				       const struct spi_mem_op *op)
-+{
-+	struct mtk_spi *mdata = spi_master_get_devdata(master);
-+
-+	writel((u32)(mdata->tx_dma & MTK_SPI_32BITS_MASK),
-+	       mdata->base + SPI_TX_SRC_REG);
-+#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
-+	if (mdata->dev_comp->dma_ext)
-+		writel((u32)(mdata->tx_dma >> 32),
-+		       mdata->base + SPI_TX_SRC_REG_64);
-+#endif
-+
-+	if (op->data.dir == SPI_MEM_DATA_IN) {
-+		writel((u32)(mdata->rx_dma & MTK_SPI_32BITS_MASK),
-+		       mdata->base + SPI_RX_DST_REG);
-+#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
-+		if (mdata->dev_comp->dma_ext)
-+			writel((u32)(mdata->rx_dma >> 32),
-+			       mdata->base + SPI_RX_DST_REG_64);
-+#endif
-+	}
-+}
-+
-+static int mtk_spi_transfer_wait(struct spi_mem *mem,
-+				 const struct spi_mem_op *op)
-+{
-+	struct mtk_spi *mdata = spi_master_get_devdata(mem->spi->master);
-+	/*
-+	 * For each byte we wait for 8 cycles of the SPI clock.
-+	 * Since speed is defined in Hz and we want milliseconds,
-+	 * so it should be 8 * 1000.
-+	 */
-+	u64 ms = 8000LL;
-+
-+	if (op->data.dir == SPI_MEM_NO_DATA)
-+		ms *= 32; /* prevent we may get 0 for short transfers. */
-+	else
-+		ms *= op->data.nbytes;
-+	ms = div_u64(ms, mem->spi->max_speed_hz);
-+	ms += ms + 1000; /* 1s tolerance */
-+
-+	if (ms > UINT_MAX)
-+		ms = UINT_MAX;
-+
-+	if (!wait_for_completion_timeout(&mdata->spimem_done,
-+					 msecs_to_jiffies(ms))) {
-+		dev_err(mdata->dev, "spi-mem transfer timeout\n");
-+		return -ETIMEDOUT;
-+	}
-+
-+	return 0;
-+}
-+
-+static int mtk_spi_mem_exec_op(struct spi_mem *mem,
-+			       const struct spi_mem_op *op)
-+{
-+	struct mtk_spi *mdata = spi_master_get_devdata(mem->spi->master);
-+	u32 reg_val, nio, tx_size;
-+	char *tx_tmp_buf, *rx_tmp_buf;
-+	int ret = 0;
-+
-+	mdata->use_spimem = true;
-+	reinit_completion(&mdata->spimem_done);
-+
-+	mtk_spi_reset(mdata);
-+	mtk_spi_hw_init(mem->spi->master, mem->spi);
-+	mtk_spi_prepare_transfer(mem->spi->master, mem->spi->max_speed_hz);
-+
-+	reg_val = readl(mdata->base + SPI_CFG3_IPM_REG);
-+	/* opcode byte len */
-+	reg_val &= ~SPI_CFG3_IPM_CMD_BYTELEN_MASK;
-+	reg_val |= 1 << SPI_CFG3_IPM_CMD_BYTELEN_OFFSET;
-+
-+	/* addr & dummy byte len */
-+	reg_val &= ~SPI_CFG3_IPM_ADDR_BYTELEN_MASK;
-+	if (op->addr.nbytes || op->dummy.nbytes)
-+		reg_val |= (op->addr.nbytes + op->dummy.nbytes) <<
-+			    SPI_CFG3_IPM_ADDR_BYTELEN_OFFSET;
-+
-+	/* data byte len */
-+	if (op->data.dir == SPI_MEM_NO_DATA) {
-+		reg_val |= SPI_CFG3_IPM_NODATA_FLAG;
-+		writel(0, mdata->base + SPI_CFG1_REG);
-+	} else {
-+		reg_val &= ~SPI_CFG3_IPM_NODATA_FLAG;
-+		mdata->xfer_len = op->data.nbytes;
-+		mtk_spi_setup_packet(mem->spi->master);
-+	}
-+
-+	if (op->addr.nbytes || op->dummy.nbytes) {
-+		if (op->addr.buswidth == 1 || op->dummy.buswidth == 1)
-+			reg_val |= SPI_CFG3_IPM_XMODE_EN;
-+		else
-+			reg_val &= ~SPI_CFG3_IPM_XMODE_EN;
-+	}
-+
-+	if (op->addr.buswidth == 2 ||
-+	    op->dummy.buswidth == 2 ||
-+	    op->data.buswidth == 2)
-+		nio = 2;
-+	else if (op->addr.buswidth == 4 ||
-+		 op->dummy.buswidth == 4 ||
-+		 op->data.buswidth == 4)
-+		nio = 4;
-+	else
-+		nio = 1;
-+
-+	reg_val &= ~SPI_CFG3_IPM_CMD_PIN_MODE_MASK;
-+	reg_val |= PIN_MODE_CFG(nio);
-+
-+	reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN;
-+	if (op->data.dir == SPI_MEM_DATA_IN)
-+		reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR;
-+	else
-+		reg_val &= ~SPI_CFG3_IPM_HALF_DUPLEX_DIR;
-+	writel(reg_val, mdata->base + SPI_CFG3_IPM_REG);
-+
-+	tx_size = 1 + op->addr.nbytes + op->dummy.nbytes;
-+	if (op->data.dir == SPI_MEM_DATA_OUT)
-+		tx_size += op->data.nbytes;
-+
-+	tx_size = max_t(u32, tx_size, 32);
-+
-+	tx_tmp_buf = kzalloc(tx_size, GFP_KERNEL | GFP_DMA);
-+	if (!tx_tmp_buf) {
-+		mdata->use_spimem = false;
-+		return -ENOMEM;
-+	}
-+
-+	tx_tmp_buf[0] = op->cmd.opcode;
-+
-+	if (op->addr.nbytes) {
-+		int i;
-+
-+		for (i = 0; i < op->addr.nbytes; i++)
-+			tx_tmp_buf[i + 1] = op->addr.val >>
-+					(8 * (op->addr.nbytes - i - 1));
-+	}
-+
-+	if (op->dummy.nbytes)
-+		memset(tx_tmp_buf + op->addr.nbytes + 1,
-+		       0xff,
-+		       op->dummy.nbytes);
-+
-+	if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
-+		memcpy(tx_tmp_buf + op->dummy.nbytes + op->addr.nbytes + 1,
-+		       op->data.buf.out,
-+		       op->data.nbytes);
-+
-+	mdata->tx_dma = dma_map_single(mdata->dev, tx_tmp_buf,
-+				       tx_size, DMA_TO_DEVICE);
-+	if (dma_mapping_error(mdata->dev, mdata->tx_dma)) {
-+		ret = -ENOMEM;
-+		goto err_exit;
-+	}
-+
-+	if (op->data.dir == SPI_MEM_DATA_IN) {
-+		if (!IS_ALIGNED((size_t)op->data.buf.in, 4)) {
-+			rx_tmp_buf = kzalloc(op->data.nbytes,
-+					     GFP_KERNEL | GFP_DMA);
-+			if (!rx_tmp_buf) {
-+				ret = -ENOMEM;
-+				goto unmap_tx_dma;
-+			}
-+		} else {
-+			rx_tmp_buf = op->data.buf.in;
-+		}
-+
-+		mdata->rx_dma = dma_map_single(mdata->dev,
-+					       rx_tmp_buf,
-+					       op->data.nbytes,
-+					       DMA_FROM_DEVICE);
-+		if (dma_mapping_error(mdata->dev, mdata->rx_dma)) {
-+			ret = -ENOMEM;
-+			goto kfree_rx_tmp_buf;
-+		}
-+	}
-+
-+	reg_val = readl(mdata->base + SPI_CMD_REG);
-+	reg_val |= SPI_CMD_TX_DMA;
-+	if (op->data.dir == SPI_MEM_DATA_IN)
-+		reg_val |= SPI_CMD_RX_DMA;
-+	writel(reg_val, mdata->base + SPI_CMD_REG);
-+
-+	mtk_spi_mem_setup_dma_xfer(mem->spi->master, op);
-+
-+	mtk_spi_enable_transfer(mem->spi->master);
-+
-+	/* Wait for the interrupt. */
-+	ret = mtk_spi_transfer_wait(mem, op);
-+	if (ret)
-+		goto unmap_rx_dma;
-+
-+	/* spi disable dma */
-+	reg_val = readl(mdata->base + SPI_CMD_REG);
-+	reg_val &= ~SPI_CMD_TX_DMA;
-+	if (op->data.dir == SPI_MEM_DATA_IN)
-+		reg_val &= ~SPI_CMD_RX_DMA;
-+	writel(reg_val, mdata->base + SPI_CMD_REG);
-+
-+unmap_rx_dma:
-+	if (op->data.dir == SPI_MEM_DATA_IN) {
-+		dma_unmap_single(mdata->dev, mdata->rx_dma,
-+				 op->data.nbytes, DMA_FROM_DEVICE);
-+		if (!IS_ALIGNED((size_t)op->data.buf.in, 4))
-+			memcpy(op->data.buf.in, rx_tmp_buf, op->data.nbytes);
-+	}
-+kfree_rx_tmp_buf:
-+	if (op->data.dir == SPI_MEM_DATA_IN &&
-+	    !IS_ALIGNED((size_t)op->data.buf.in, 4))
-+		kfree(rx_tmp_buf);
-+unmap_tx_dma:
-+	dma_unmap_single(mdata->dev, mdata->tx_dma,
-+			 tx_size, DMA_TO_DEVICE);
-+err_exit:
-+	kfree(tx_tmp_buf);
-+	mdata->use_spimem = false;
-+
-+	return ret;
-+}
-+
-+static const struct spi_controller_mem_ops mtk_spi_mem_ops = {
-+	.adjust_op_size = mtk_spi_mem_adjust_op_size,
-+	.supports_op = mtk_spi_mem_supports_op,
-+	.exec_op = mtk_spi_mem_exec_op,
-+};
-+
- static int mtk_spi_probe(struct platform_device *pdev)
- {
- 	struct spi_master *master;
-@@ -739,6 +1103,7 @@ static int mtk_spi_probe(struct platform
- 	master->can_dma = mtk_spi_can_dma;
- 	master->setup = mtk_spi_setup;
- 	master->set_cs_timing = mtk_spi_set_hw_cs_timing;
-+	master->use_gpio_descriptors = true;
- 
- 	of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node);
- 	if (!of_id) {
-@@ -755,6 +1120,14 @@ static int mtk_spi_probe(struct platform
- 
- 	if (mdata->dev_comp->must_tx)
- 		master->flags = SPI_MASTER_MUST_TX;
-+	if (mdata->dev_comp->ipm_design)
-+		master->mode_bits |= SPI_LOOP;
-+
-+	if (mdata->dev_comp->ipm_design) {
-+		mdata->dev = &pdev->dev;
-+		master->mem_ops = &mtk_spi_mem_ops;
-+		init_completion(&mdata->spimem_done);
-+	}
- 
- 	if (mdata->dev_comp->need_pad_sel) {
- 		mdata->pad_num = of_property_count_u32_elems(
-@@ -831,25 +1204,40 @@ static int mtk_spi_probe(struct platform
- 		goto err_put_master;
- 	}
- 
-+	mdata->spi_hclk = devm_clk_get_optional(&pdev->dev, "hclk");
-+	if (IS_ERR(mdata->spi_hclk)) {
-+		ret = PTR_ERR(mdata->spi_hclk);
-+		dev_err(&pdev->dev, "failed to get hclk: %d\n", ret);
-+		goto err_put_master;
-+	}
-+
-+	ret = clk_prepare_enable(mdata->spi_hclk);
-+	if (ret < 0) {
-+		dev_err(&pdev->dev, "failed to enable hclk (%d)\n", ret);
-+		goto err_put_master;
-+	}
-+
- 	ret = clk_prepare_enable(mdata->spi_clk);
- 	if (ret < 0) {
- 		dev_err(&pdev->dev, "failed to enable spi_clk (%d)\n", ret);
--		goto err_put_master;
-+		goto err_disable_spi_hclk;
- 	}
- 
- 	ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk);
- 	if (ret < 0) {
- 		dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret);
--		clk_disable_unprepare(mdata->spi_clk);
--		goto err_put_master;
-+		goto err_disable_spi_clk;
- 	}
- 
- 	mdata->spi_clk_hz = clk_get_rate(mdata->spi_clk);
- 
--	if (mdata->dev_comp->no_need_unprepare)
-+	if (mdata->dev_comp->no_need_unprepare) {
- 		clk_disable(mdata->spi_clk);
--	else
-+		clk_disable(mdata->spi_hclk);
-+	} else {
- 		clk_disable_unprepare(mdata->spi_clk);
-+		clk_disable_unprepare(mdata->spi_hclk);
-+	}
- 
- 	pm_runtime_enable(&pdev->dev);
- 
-@@ -862,25 +1250,12 @@ static int mtk_spi_probe(struct platform
- 			goto err_disable_runtime_pm;
- 		}
- 
--		if (!master->cs_gpios && master->num_chipselect > 1) {
-+		if (!master->cs_gpiods && master->num_chipselect > 1) {
- 			dev_err(&pdev->dev,
- 				"cs_gpios not specified and num_chipselect > 1\n");
- 			ret = -EINVAL;
- 			goto err_disable_runtime_pm;
- 		}
--
--		if (master->cs_gpios) {
--			for (i = 0; i < master->num_chipselect; i++) {
--				ret = devm_gpio_request(&pdev->dev,
--							master->cs_gpios[i],
--							dev_name(&pdev->dev));
--				if (ret) {
--					dev_err(&pdev->dev,
--						"can't get CS GPIO %i\n", i);
--					goto err_disable_runtime_pm;
--				}
--			}
--		}
- 	}
- 
- 	if (mdata->dev_comp->dma_ext)
-@@ -902,6 +1277,10 @@ static int mtk_spi_probe(struct platform
- 
- err_disable_runtime_pm:
- 	pm_runtime_disable(&pdev->dev);
-+err_disable_spi_clk:
-+	clk_disable_unprepare(mdata->spi_clk);
-+err_disable_spi_hclk:
-+	clk_disable_unprepare(mdata->spi_hclk);
- err_put_master:
- 	spi_master_put(master);
- 
-@@ -920,8 +1299,10 @@ static int mtk_spi_remove(struct platfor
- 
- 	mtk_spi_reset(mdata);
- 
--	if (mdata->dev_comp->no_need_unprepare)
-+	if (mdata->dev_comp->no_need_unprepare) {
- 		clk_unprepare(mdata->spi_clk);
-+		clk_unprepare(mdata->spi_hclk);
-+	}
- 
- 	pm_runtime_put_noidle(&pdev->dev);
- 	pm_runtime_disable(&pdev->dev);
-@@ -940,8 +1321,10 @@ static int mtk_spi_suspend(struct device
- 	if (ret)
- 		return ret;
- 
--	if (!pm_runtime_suspended(dev))
-+	if (!pm_runtime_suspended(dev)) {
- 		clk_disable_unprepare(mdata->spi_clk);
-+		clk_disable_unprepare(mdata->spi_hclk);
-+	}
- 
- 	return ret;
- }
-@@ -958,11 +1341,20 @@ static int mtk_spi_resume(struct device
- 			dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
- 			return ret;
- 		}
-+
-+		ret = clk_prepare_enable(mdata->spi_hclk);
-+		if (ret < 0) {
-+			dev_err(dev, "failed to enable spi_hclk (%d)\n", ret);
-+			clk_disable_unprepare(mdata->spi_clk);
-+			return ret;
-+		}
- 	}
- 
- 	ret = spi_master_resume(master);
--	if (ret < 0)
-+	if (ret < 0) {
- 		clk_disable_unprepare(mdata->spi_clk);
-+		clk_disable_unprepare(mdata->spi_hclk);
-+	}
- 
- 	return ret;
- }
-@@ -974,10 +1366,13 @@ static int mtk_spi_runtime_suspend(struc
- 	struct spi_master *master = dev_get_drvdata(dev);
- 	struct mtk_spi *mdata = spi_master_get_devdata(master);
- 
--	if (mdata->dev_comp->no_need_unprepare)
-+	if (mdata->dev_comp->no_need_unprepare) {
- 		clk_disable(mdata->spi_clk);
--	else
-+		clk_disable(mdata->spi_hclk);
-+	} else {
- 		clk_disable_unprepare(mdata->spi_clk);
-+		clk_disable_unprepare(mdata->spi_hclk);
-+	}
- 
- 	return 0;
- }
-@@ -988,13 +1383,31 @@ static int mtk_spi_runtime_resume(struct
- 	struct mtk_spi *mdata = spi_master_get_devdata(master);
- 	int ret;
- 
--	if (mdata->dev_comp->no_need_unprepare)
-+	if (mdata->dev_comp->no_need_unprepare) {
- 		ret = clk_enable(mdata->spi_clk);
--	else
-+		if (ret < 0) {
-+			dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
-+			return ret;
-+		}
-+		ret = clk_enable(mdata->spi_hclk);
-+		if (ret < 0) {
-+			dev_err(dev, "failed to enable spi_hclk (%d)\n", ret);
-+			clk_disable(mdata->spi_clk);
-+			return ret;
-+		}
-+	} else {
- 		ret = clk_prepare_enable(mdata->spi_clk);
--	if (ret < 0) {
--		dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
--		return ret;
-+		if (ret < 0) {
-+			dev_err(dev, "failed to prepare_enable spi_clk (%d)\n", ret);
-+			return ret;
-+		}
-+
-+		ret = clk_prepare_enable(mdata->spi_hclk);
-+		if (ret < 0) {
-+			dev_err(dev, "failed to prepare_enable spi_hclk (%d)\n", ret);
-+			clk_disable_unprepare(mdata->spi_clk);
-+			return ret;
-+		}
- 	}
- 
- 	return 0;
diff --git a/target/linux/mediatek/patches-5.15/214-v6.3-clk-mediatek-add-mt7981-clock-support.patch b/target/linux/mediatek/patches-5.15/214-v6.3-clk-mediatek-add-mt7981-clock-support.patch
deleted file mode 100644
index 631eb04092dfc0..00000000000000
--- a/target/linux/mediatek/patches-5.15/214-v6.3-clk-mediatek-add-mt7981-clock-support.patch
+++ /dev/null
@@ -1,39 +0,0 @@
---- a/drivers/clk/mediatek/Kconfig
-+++ b/drivers/clk/mediatek/Kconfig
-@@ -344,6 +344,23 @@ config COMMON_CLK_MT7629_HIFSYS
- 	  This driver supports MediaTek MT7629 HIFSYS clocks providing
- 	  to PCI-E and USB.
- 
-+config COMMON_CLK_MT7981
-+	bool "Clock driver for MediaTek MT7981"
-+	depends on ARCH_MEDIATEK || COMPILE_TEST
-+	select COMMON_CLK_MEDIATEK
-+	default ARCH_MEDIATEK
-+	help
-+	  This driver supports MediaTek MT7981 basic clocks and clocks
-+	  required for various periperals found on MediaTek.
-+
-+config COMMON_CLK_MT7981_ETHSYS
-+	bool "Clock driver for MediaTek MT7981 ETHSYS"
-+	depends on COMMON_CLK_MT7981
-+	default COMMON_CLK_MT7981
-+	help
-+	  This driver add support for clocks for Ethernet and SGMII
-+	  required on MediaTek MT7981 SoC.
-+
- config COMMON_CLK_MT7986
- 	bool "Clock driver for MediaTek MT7986"
- 	depends on ARCH_MEDIATEK || COMPILE_TEST
---- a/drivers/clk/mediatek/Makefile
-+++ b/drivers/clk/mediatek/Makefile
-@@ -46,6 +46,10 @@ obj-$(CONFIG_COMMON_CLK_MT7622_AUDSYS) +
- obj-$(CONFIG_COMMON_CLK_MT7629) += clk-mt7629.o
- obj-$(CONFIG_COMMON_CLK_MT7629_ETHSYS) += clk-mt7629-eth.o
- obj-$(CONFIG_COMMON_CLK_MT7629_HIFSYS) += clk-mt7629-hif.o
-+obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-apmixed.o
-+obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-topckgen.o
-+obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-infracfg.o
-+obj-$(CONFIG_COMMON_CLK_MT7981_ETHSYS) += clk-mt7981-eth.o
- obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-apmixed.o
- obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o
- obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o
diff --git a/target/linux/mediatek/patches-5.15/215-v6.3-pinctrl-mediatek-add-support-for-MT7981-SoC.patch b/target/linux/mediatek/patches-5.15/215-v6.3-pinctrl-mediatek-add-support-for-MT7981-SoC.patch
deleted file mode 100644
index ae99685df4c70f..00000000000000
--- a/target/linux/mediatek/patches-5.15/215-v6.3-pinctrl-mediatek-add-support-for-MT7981-SoC.patch
+++ /dev/null
@@ -1,26 +0,0 @@
---- a/drivers/pinctrl/mediatek/Kconfig
-+++ b/drivers/pinctrl/mediatek/Kconfig
-@@ -120,6 +120,13 @@ config PINCTRL_MT7622
- 	default ARM64 && ARCH_MEDIATEK
- 	select PINCTRL_MTK_MOORE
- 
-+config PINCTRL_MT7981
-+	bool "Mediatek MT7981 pin control"
-+	depends on OF
-+	depends on ARM64 || COMPILE_TEST
-+	default ARM64 && ARCH_MEDIATEK
-+	select PINCTRL_MTK_MOORE
-+
- config PINCTRL_MT7986
- 	bool "Mediatek MT7986 pin control"
- 	depends on OF
---- a/drivers/pinctrl/mediatek/Makefile
-+++ b/drivers/pinctrl/mediatek/Makefile
-@@ -17,6 +17,7 @@ obj-$(CONFIG_PINCTRL_MT6797)	+= pinctrl-
- obj-$(CONFIG_PINCTRL_MT7622)	+= pinctrl-mt7622.o
- obj-$(CONFIG_PINCTRL_MT7623)	+= pinctrl-mt7623.o
- obj-$(CONFIG_PINCTRL_MT7629)	+= pinctrl-mt7629.o
-+obj-$(CONFIG_PINCTRL_MT7986)	+= pinctrl-mt7981.o
- obj-$(CONFIG_PINCTRL_MT7986)	+= pinctrl-mt7986.o
- obj-$(CONFIG_PINCTRL_MT8167)	+= pinctrl-mt8167.o
- obj-$(CONFIG_PINCTRL_MT8173)	+= pinctrl-mt8173.o
diff --git a/target/linux/mediatek/patches-5.15/240-pinctrl-mediatek-add-support-for-MT7988-SoC.patch b/target/linux/mediatek/patches-5.15/240-pinctrl-mediatek-add-support-for-MT7988-SoC.patch
deleted file mode 100644
index cbee45bc1f89d2..00000000000000
--- a/target/linux/mediatek/patches-5.15/240-pinctrl-mediatek-add-support-for-MT7988-SoC.patch
+++ /dev/null
@@ -1,26 +0,0 @@
---- a/drivers/pinctrl/mediatek/Kconfig
-+++ b/drivers/pinctrl/mediatek/Kconfig
-@@ -134,6 +134,13 @@ config PINCTRL_MT7986
- 	default ARM64 && ARCH_MEDIATEK
- 	select PINCTRL_MTK_MOORE
- 
-+config PINCTRL_MT7988
-+	bool "Mediatek MT7988 pin control"
-+	depends on OF
-+	depends on ARM64 || COMPILE_TEST
-+	default ARCH_MEDIATEK
-+	select PINCTRL_MTK_MOORE
-+
- config PINCTRL_MT8167
- 	bool "Mediatek MT8167 pin control"
- 	depends on OF
---- a/drivers/pinctrl/mediatek/Makefile
-+++ b/drivers/pinctrl/mediatek/Makefile
-@@ -19,6 +19,7 @@ obj-$(CONFIG_PINCTRL_MT7623)	+= pinctrl-
- obj-$(CONFIG_PINCTRL_MT7629)	+= pinctrl-mt7629.o
- obj-$(CONFIG_PINCTRL_MT7986)	+= pinctrl-mt7981.o
- obj-$(CONFIG_PINCTRL_MT7986)	+= pinctrl-mt7986.o
-+obj-$(CONFIG_PINCTRL_MT7988)	+= pinctrl-mt7988.o
- obj-$(CONFIG_PINCTRL_MT8167)	+= pinctrl-mt8167.o
- obj-$(CONFIG_PINCTRL_MT8173)	+= pinctrl-mt8173.o
- obj-$(CONFIG_PINCTRL_MT8183)	+= pinctrl-mt8183.o
diff --git a/target/linux/mediatek/patches-5.15/241-clk-mediatek-Add-pcw-chg-shift-control.patch b/target/linux/mediatek/patches-5.15/241-clk-mediatek-Add-pcw-chg-shift-control.patch
deleted file mode 100644
index 23a5b7c911a5da..00000000000000
--- a/target/linux/mediatek/patches-5.15/241-clk-mediatek-Add-pcw-chg-shift-control.patch
+++ /dev/null
@@ -1,24 +0,0 @@
---- a/drivers/clk/mediatek/clk-mtk.h
-+++ b/drivers/clk/mediatek/clk-mtk.h
-@@ -233,6 +233,7 @@ struct mtk_pll_data {
- 	u32 pcw_reg;
- 	int pcw_shift;
- 	u32 pcw_chg_reg;
-+	int pcw_chg_shift;
- 	const struct mtk_pll_div_table *div_table;
- 	const char *parent_name;
- 	u32 en_reg;
---- a/drivers/clk/mediatek/clk-pll.c
-+++ b/drivers/clk/mediatek/clk-pll.c
-@@ -137,7 +137,10 @@ static void mtk_pll_set_rate_regs(struct
- 			pll->data->pcw_shift);
- 	val |= pcw << pll->data->pcw_shift;
- 	writel(val, pll->pcw_addr);
--	chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;
-+	if (pll->data->pcw_chg_shift)
-+		chg = readl(pll->pcw_chg_addr) | BIT(pll->data->pcw_chg_shift);
-+	else
-+		chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;
- 	writel(chg, pll->pcw_chg_addr);
- 	if (pll->tuner_addr)
- 		writel(val + 1, pll->tuner_addr);
diff --git a/target/linux/mediatek/patches-5.15/242-clk-mediatek-add-mt7988-clock-support.patch b/target/linux/mediatek/patches-5.15/242-clk-mediatek-add-mt7988-clock-support.patch
deleted file mode 100644
index bf9146352a6154..00000000000000
--- a/target/linux/mediatek/patches-5.15/242-clk-mediatek-add-mt7988-clock-support.patch
+++ /dev/null
@@ -1,31 +0,0 @@
---- a/drivers/clk/mediatek/Kconfig
-+++ b/drivers/clk/mediatek/Kconfig
-@@ -378,6 +378,15 @@ config COMMON_CLK_MT7986_ETHSYS
- 	  This driver add support for clocks for Ethernet and SGMII
- 	  required on MediaTek MT7986 SoC.
- 
-+config COMMON_CLK_MT7988
-+	bool "Clock driver for MediaTek MT7988"
-+	depends on ARCH_MEDIATEK || COMPILE_TEST
-+	select COMMON_CLK_MEDIATEK
-+	default ARCH_MEDIATEK
-+	help
-+	  This driver supports MediaTek MT7988 basic clocks and clocks
-+	  required for various periperals found on MediaTek.
-+
- config COMMON_CLK_MT8135
- 	bool "Clock driver for MediaTek MT8135"
- 	depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST
---- a/drivers/clk/mediatek/Makefile
-+++ b/drivers/clk/mediatek/Makefile
-@@ -54,6 +54,10 @@ obj-$(CONFIG_COMMON_CLK_MT7986) += clk-m
- obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o
- obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o
- obj-$(CONFIG_COMMON_CLK_MT7986_ETHSYS) += clk-mt7986-eth.o
-+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-apmixed.o
-+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-topckgen.o
-+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-infracfg.o
-+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-eth.o
- obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
- obj-$(CONFIG_COMMON_CLK_MT8167) += clk-mt8167.o
- obj-$(CONFIG_COMMON_CLK_MT8167_AUDSYS) += clk-mt8167-aud.o
diff --git a/target/linux/mediatek/patches-5.15/320-mmc-mediatek-add-support-for-MT7986-SoC.patch b/target/linux/mediatek/patches-5.15/320-mmc-mediatek-add-support-for-MT7986-SoC.patch
deleted file mode 100644
index 56ffa73c00cf59..00000000000000
--- a/target/linux/mediatek/patches-5.15/320-mmc-mediatek-add-support-for-MT7986-SoC.patch
+++ /dev/null
@@ -1,44 +0,0 @@
-From 1a7963e9843f6f1e4b02a30926d20b314c03e4df Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Sat, 25 Jun 2022 02:10:13 +0800
-Subject: [PATCH] mmc: mediatek: add support for MT7986 SoC
-
-Adding mt7986 own characteristics and of_device_id to have support
-of MT7986 SoC.
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Change-Id: I07cf8406cbe8c1a7114b304f35fc3e689e512e5a
----
- drivers/mmc/host/mtk-sd.c | 14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
---- a/drivers/mmc/host/mtk-sd.c
-+++ b/drivers/mmc/host/mtk-sd.c
-@@ -540,6 +540,19 @@ static const struct mtk_mmc_compatible m
- 	.support_64g = false,
- };
- 
-+static const struct mtk_mmc_compatible mt7986_compat = {
-+	.clk_div_bits = 12,
-+	.recheck_sdio_irq = true,
-+	.hs400_tune = false,
-+	.pad_tune_reg = MSDC_PAD_TUNE0,
-+	.async_fifo = true,
-+	.data_tune = true,
-+	.busy_check = true,
-+	.stop_clk_fix = true,
-+	.enhance_rx = true,
-+	.support_64g = true,
-+};
-+
- static const struct mtk_mmc_compatible mt8516_compat = {
- 	.clk_div_bits = 12,
- 	.recheck_sdio_irq = true,
-@@ -584,6 +597,7 @@ static const struct of_device_id msdc_of
- 	{ .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat},
- 	{ .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat},
- 	{ .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat},
-+	{ .compatible = "mediatek,mt7986-mmc", .data = &mt7986_compat},
- 	{ .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat},
- 	{ .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat},
- 	{ .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat},
diff --git a/target/linux/mediatek/patches-5.15/330-snand-mtk-bmt-support.patch b/target/linux/mediatek/patches-5.15/330-snand-mtk-bmt-support.patch
deleted file mode 100644
index 6814e5f5e983e0..00000000000000
--- a/target/linux/mediatek/patches-5.15/330-snand-mtk-bmt-support.patch
+++ /dev/null
@@ -1,34 +0,0 @@
---- a/drivers/mtd/nand/spi/core.c
-+++ b/drivers/mtd/nand/spi/core.c
-@@ -19,6 +19,7 @@
- #include <linux/string.h>
- #include <linux/spi/spi.h>
- #include <linux/spi/spi-mem.h>
-+#include <linux/mtd/mtk_bmt.h>
- 
- static int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val)
- {
-@@ -1343,6 +1344,7 @@ static int spinand_probe(struct spi_mem
- 	if (ret)
- 		return ret;
- 
-+	mtk_bmt_attach(mtd);
- 	ret = mtd_device_register(mtd, NULL, 0);
- 	if (ret)
- 		goto err_spinand_cleanup;
-@@ -1350,6 +1352,7 @@ static int spinand_probe(struct spi_mem
- 	return 0;
- 
- err_spinand_cleanup:
-+	mtk_bmt_detach(mtd);
- 	spinand_cleanup(spinand);
- 
- 	return ret;
-@@ -1368,6 +1371,7 @@ static int spinand_remove(struct spi_mem
- 	if (ret)
- 		return ret;
- 
-+	mtk_bmt_detach(mtd);
- 	spinand_cleanup(spinand);
- 
- 	return 0;
diff --git a/target/linux/mediatek/patches-5.15/331-mt7622-rfb1-enable-bmt.patch b/target/linux/mediatek/patches-5.15/331-mt7622-rfb1-enable-bmt.patch
deleted file mode 100644
index 9c1a8f284abcd9..00000000000000
--- a/target/linux/mediatek/patches-5.15/331-mt7622-rfb1-enable-bmt.patch
+++ /dev/null
@@ -1,10 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-@@ -553,6 +553,7 @@
- 		spi-tx-bus-width = <4>;
- 		spi-rx-bus-width = <4>;
- 		nand-ecc-engine = <&snfi>;
-+		mediatek,bmt-v2;
- 
- 		partitions {
- 			compatible = "fixed-partitions";
diff --git a/target/linux/mediatek/patches-5.15/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch b/target/linux/mediatek/patches-5.15/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch
deleted file mode 100644
index 6baa32879bf7c4..00000000000000
--- a/target/linux/mediatek/patches-5.15/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch
+++ /dev/null
@@ -1,122 +0,0 @@
-From 5f49a5c9b16330e0df8f639310e4715dcad71947 Mon Sep 17 00:00:00 2001
-From: Davide Fioravanti <pantanastyle@gmail.com>
-Date: Fri, 8 Jan 2021 15:35:24 +0100
-Subject: [PATCH] mtd: spinand: Add support for the Fidelix FM35X1GA
-
-Datasheet: http://www.hobos.com.cn/upload/datasheet/DS35X1GAXXX_100_rev00.pdf
-
-Signed-off-by: Davide Fioravanti <pantanastyle@gmail.com>
----
- drivers/mtd/nand/spi/Makefile  |  2 +-
- drivers/mtd/nand/spi/core.c    |  1 +
- drivers/mtd/nand/spi/fidelix.c | 76 ++++++++++++++++++++++++++++++++++
- include/linux/mtd/spinand.h    |  1 +
- 4 files changed, 79 insertions(+), 1 deletion(-)
- create mode 100644 drivers/mtd/nand/spi/fidelix.c
-
---- a/drivers/mtd/nand/spi/Makefile
-+++ b/drivers/mtd/nand/spi/Makefile
-@@ -1,3 +1,3 @@
- # SPDX-License-Identifier: GPL-2.0
--spinand-objs := core.o esmt.o etron.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o
-+spinand-objs := core.o esmt.o etron.o fidelix.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o
- obj-$(CONFIG_MTD_SPI_NAND) += spinand.o
---- a/drivers/mtd/nand/spi/core.c
-+++ b/drivers/mtd/nand/spi/core.c
-@@ -939,6 +939,7 @@ static const struct nand_ops spinand_ops
- 
- static const struct spinand_manufacturer *spinand_manufacturers[] = {
- 	&esmt_c8_spinand_manufacturer,
-+	&fidelix_spinand_manufacturer,
- 	&gigadevice_spinand_manufacturer,
- 	&etron_spinand_manufacturer,
- 	&macronix_spinand_manufacturer,
---- /dev/null
-+++ b/drivers/mtd/nand/spi/fidelix.c
-@@ -0,0 +1,76 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2020 Davide Fioravanti <pantanastyle@gmail.com>
-+ */
-+
-+#include <linux/device.h>
-+#include <linux/kernel.h>
-+#include <linux/mtd/spinand.h>
-+
-+#define SPINAND_MFR_FIDELIX		0xE5
-+#define FIDELIX_ECCSR_MASK		0x0F
-+
-+static SPINAND_OP_VARIANTS(read_cache_variants,
-+		SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
-+		SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
-+		SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
-+
-+static SPINAND_OP_VARIANTS(write_cache_variants,
-+		SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
-+		SPINAND_PROG_LOAD(true, 0, NULL, 0));
-+
-+static SPINAND_OP_VARIANTS(update_cache_variants,
-+		SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
-+		SPINAND_PROG_LOAD(false, 0, NULL, 0));
-+
-+static int fm35x1ga_ooblayout_ecc(struct mtd_info *mtd, int section,
-+				  struct mtd_oob_region *region)
-+{
-+	if (section > 3)
-+		return -ERANGE;
-+
-+	region->offset = (16 * section) + 8;
-+	region->length = 8;
-+
-+	return 0;
-+}
-+
-+static int fm35x1ga_ooblayout_free(struct mtd_info *mtd, int section,
-+				   struct mtd_oob_region *region)
-+{
-+	if (section > 3)
-+		return -ERANGE;
-+
-+	region->offset = (16 * section) + 2;
-+	region->length = 6;
-+
-+	return 0;
-+}
-+
-+static const struct mtd_ooblayout_ops fm35x1ga_ooblayout = {
-+	.ecc = fm35x1ga_ooblayout_ecc,
-+	.free = fm35x1ga_ooblayout_free,
-+};
-+
-+static const struct spinand_info fidelix_spinand_table[] = {
-+	SPINAND_INFO("FM35X1GA",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x71),
-+		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
-+		     NAND_ECCREQ(4, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&fm35x1ga_ooblayout, NULL)),
-+};
-+
-+static const struct spinand_manufacturer_ops fidelix_spinand_manuf_ops = {
-+};
-+
-+const struct spinand_manufacturer fidelix_spinand_manufacturer = {
-+	.id = SPINAND_MFR_FIDELIX,
-+	.name = "Fidelix",
-+	.chips = fidelix_spinand_table,
-+	.nchips = ARRAY_SIZE(fidelix_spinand_table),
-+	.ops = &fidelix_spinand_manuf_ops,
-+};
---- a/include/linux/mtd/spinand.h
-+++ b/include/linux/mtd/spinand.h
-@@ -262,6 +262,7 @@ struct spinand_manufacturer {
- /* SPI NAND manufacturers */
- extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer;
- extern const struct spinand_manufacturer etron_spinand_manufacturer;
-+extern const struct spinand_manufacturer fidelix_spinand_manufacturer;
- extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;
- extern const struct spinand_manufacturer macronix_spinand_manufacturer;
- extern const struct spinand_manufacturer micron_spinand_manufacturer;
diff --git a/target/linux/mediatek/patches-5.15/350-01-cpufreq-mediatek-Cleanup-variables-and-error-handlin.patch b/target/linux/mediatek/patches-5.15/350-01-cpufreq-mediatek-Cleanup-variables-and-error-handlin.patch
deleted file mode 100644
index 8fad64a5702aa0..00000000000000
--- a/target/linux/mediatek/patches-5.15/350-01-cpufreq-mediatek-Cleanup-variables-and-error-handlin.patch
+++ /dev/null
@@ -1,166 +0,0 @@
-From 7a768326fdba542144833b9198a6d0edab52fad2 Mon Sep 17 00:00:00 2001
-From: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Date: Fri, 8 Apr 2022 12:58:56 +0800
-Subject: [PATCH 01/21] cpufreq: mediatek: Cleanup variables and error handling
- in mtk_cpu_dvfs_info_init()
-
-- Remove several unnecessary varaibles in mtk_cpu_dvfs_info_init().
-- Unify error message format and use dev_err_probe() if possible.
-
-Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 89 ++++++++++++------------------
- 1 file changed, 34 insertions(+), 55 deletions(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -302,96 +302,75 @@ static int mtk_cpufreq_set_target(struct
- static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
- {
- 	struct device *cpu_dev;
--	struct regulator *proc_reg = ERR_PTR(-ENODEV);
--	struct regulator *sram_reg = ERR_PTR(-ENODEV);
--	struct clk *cpu_clk = ERR_PTR(-ENODEV);
--	struct clk *inter_clk = ERR_PTR(-ENODEV);
- 	struct dev_pm_opp *opp;
- 	unsigned long rate;
- 	int ret;
- 
- 	cpu_dev = get_cpu_device(cpu);
- 	if (!cpu_dev) {
--		pr_err("failed to get cpu%d device\n", cpu);
-+		dev_err(cpu_dev, "failed to get cpu%d device\n", cpu);
- 		return -ENODEV;
- 	}
-+	info->cpu_dev = cpu_dev;
- 
--	cpu_clk = clk_get(cpu_dev, "cpu");
--	if (IS_ERR(cpu_clk)) {
--		if (PTR_ERR(cpu_clk) == -EPROBE_DEFER)
--			pr_warn("cpu clk for cpu%d not ready, retry.\n", cpu);
--		else
--			pr_err("failed to get cpu clk for cpu%d\n", cpu);
--
--		ret = PTR_ERR(cpu_clk);
--		return ret;
--	}
--
--	inter_clk = clk_get(cpu_dev, "intermediate");
--	if (IS_ERR(inter_clk)) {
--		if (PTR_ERR(inter_clk) == -EPROBE_DEFER)
--			pr_warn("intermediate clk for cpu%d not ready, retry.\n",
--				cpu);
--		else
--			pr_err("failed to get intermediate clk for cpu%d\n",
--			       cpu);
-+	info->cpu_clk = clk_get(cpu_dev, "cpu");
-+	if (IS_ERR(info->cpu_clk)) {
-+		ret = PTR_ERR(info->cpu_clk);
-+		return dev_err_probe(cpu_dev, ret,
-+				     "cpu%d: failed to get cpu clk\n", cpu);
-+	}
- 
--		ret = PTR_ERR(inter_clk);
-+	info->inter_clk = clk_get(cpu_dev, "intermediate");
-+	if (IS_ERR(info->inter_clk)) {
-+		ret = PTR_ERR(info->inter_clk);
-+		dev_err_probe(cpu_dev, ret,
-+			      "cpu%d: failed to get intermediate clk\n", cpu);
- 		goto out_free_resources;
- 	}
- 
--	proc_reg = regulator_get_optional(cpu_dev, "proc");
--	if (IS_ERR(proc_reg)) {
--		if (PTR_ERR(proc_reg) == -EPROBE_DEFER)
--			pr_warn("proc regulator for cpu%d not ready, retry.\n",
--				cpu);
--		else
--			pr_err("failed to get proc regulator for cpu%d\n",
--			       cpu);
--
--		ret = PTR_ERR(proc_reg);
-+	info->proc_reg = regulator_get_optional(cpu_dev, "proc");
-+	if (IS_ERR(info->proc_reg)) {
-+		ret = PTR_ERR(info->proc_reg);
-+		dev_err_probe(cpu_dev, ret,
-+			      "cpu%d: failed to get proc regulator\n", cpu);
- 		goto out_free_resources;
- 	}
- 
- 	/* Both presence and absence of sram regulator are valid cases. */
--	sram_reg = regulator_get_exclusive(cpu_dev, "sram");
-+	info->sram_reg = regulator_get_exclusive(cpu_dev, "sram");
-+	if (IS_ERR(info->sram_reg))
-+		info->sram_reg = NULL;
- 
- 	/* Get OPP-sharing information from "operating-points-v2" bindings */
- 	ret = dev_pm_opp_of_get_sharing_cpus(cpu_dev, &info->cpus);
- 	if (ret) {
--		pr_err("failed to get OPP-sharing information for cpu%d\n",
--		       cpu);
-+		dev_err(cpu_dev,
-+			"cpu%d: failed to get OPP-sharing information\n", cpu);
- 		goto out_free_resources;
- 	}
- 
- 	ret = dev_pm_opp_of_cpumask_add_table(&info->cpus);
- 	if (ret) {
--		pr_warn("no OPP table for cpu%d\n", cpu);
-+		dev_warn(cpu_dev, "cpu%d: no OPP table\n", cpu);
- 		goto out_free_resources;
- 	}
- 
- 	/* Search a safe voltage for intermediate frequency. */
--	rate = clk_get_rate(inter_clk);
-+	rate = clk_get_rate(info->inter_clk);
- 	opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
- 	if (IS_ERR(opp)) {
--		pr_err("failed to get intermediate opp for cpu%d\n", cpu);
-+		dev_err(cpu_dev, "cpu%d: failed to get intermediate opp\n", cpu);
- 		ret = PTR_ERR(opp);
- 		goto out_free_opp_table;
- 	}
- 	info->intermediate_voltage = dev_pm_opp_get_voltage(opp);
- 	dev_pm_opp_put(opp);
- 
--	info->cpu_dev = cpu_dev;
--	info->proc_reg = proc_reg;
--	info->sram_reg = IS_ERR(sram_reg) ? NULL : sram_reg;
--	info->cpu_clk = cpu_clk;
--	info->inter_clk = inter_clk;
--
- 	/*
- 	 * If SRAM regulator is present, software "voltage tracking" is needed
- 	 * for this CPU power domain.
- 	 */
--	info->need_voltage_tracking = !IS_ERR(sram_reg);
-+	info->need_voltage_tracking = (info->sram_reg != NULL);
- 
- 	return 0;
- 
-@@ -399,14 +378,14 @@ out_free_opp_table:
- 	dev_pm_opp_of_cpumask_remove_table(&info->cpus);
- 
- out_free_resources:
--	if (!IS_ERR(proc_reg))
--		regulator_put(proc_reg);
--	if (!IS_ERR(sram_reg))
--		regulator_put(sram_reg);
--	if (!IS_ERR(cpu_clk))
--		clk_put(cpu_clk);
--	if (!IS_ERR(inter_clk))
--		clk_put(inter_clk);
-+	if (!IS_ERR(info->proc_reg))
-+		regulator_put(info->proc_reg);
-+	if (!IS_ERR(info->sram_reg))
-+		regulator_put(info->sram_reg);
-+	if (!IS_ERR(info->cpu_clk))
-+		clk_put(info->cpu_clk);
-+	if (!IS_ERR(info->inter_clk))
-+		clk_put(info->inter_clk);
- 
- 	return ret;
- }
diff --git a/target/linux/mediatek/patches-5.15/350-02-cpufreq-mediatek-Remove-unused-headers.patch b/target/linux/mediatek/patches-5.15/350-02-cpufreq-mediatek-Remove-unused-headers.patch
deleted file mode 100644
index eebeeb09028518..00000000000000
--- a/target/linux/mediatek/patches-5.15/350-02-cpufreq-mediatek-Remove-unused-headers.patch
+++ /dev/null
@@ -1,25 +0,0 @@
-From 756104b856d4bc3121420af3ced342f5fc2b2123 Mon Sep 17 00:00:00 2001
-From: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Date: Fri, 8 Apr 2022 12:58:57 +0800
-Subject: [PATCH 02/21] cpufreq: mediatek: Remove unused headers
-
-Remove unused headers.
-
-Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 2 --
- 1 file changed, 2 deletions(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -13,8 +13,6 @@
- #include <linux/platform_device.h>
- #include <linux/pm_opp.h>
- #include <linux/regulator/consumer.h>
--#include <linux/slab.h>
--#include <linux/thermal.h>
- 
- #define MIN_VOLT_SHIFT		(100000)
- #define MAX_VOLT_SHIFT		(200000)
diff --git a/target/linux/mediatek/patches-5.15/350-03-cpufreq-mediatek-Enable-clocks-and-regulators.patch b/target/linux/mediatek/patches-5.15/350-03-cpufreq-mediatek-Enable-clocks-and-regulators.patch
deleted file mode 100644
index c97d5fc3d91d82..00000000000000
--- a/target/linux/mediatek/patches-5.15/350-03-cpufreq-mediatek-Enable-clocks-and-regulators.patch
+++ /dev/null
@@ -1,117 +0,0 @@
-From 342d5545e9f40496db9ae0d31c2427dd5f369a43 Mon Sep 17 00:00:00 2001
-From: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Date: Fri, 8 Apr 2022 12:58:58 +0800
-Subject: [PATCH 03/21] cpufreq: mediatek: Enable clocks and regulators
-
-We need to enable regulators so that the max and min requested values will
-be recorded.
-The intermediate clock is not always enabled by CCF in different projects,
-so we should enable it in the cpufreq driver.
-
-Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
-Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 50 +++++++++++++++++++++++++++---
- 1 file changed, 45 insertions(+), 5 deletions(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -334,10 +334,23 @@ static int mtk_cpu_dvfs_info_init(struct
- 		goto out_free_resources;
- 	}
- 
-+	ret = regulator_enable(info->proc_reg);
-+	if (ret) {
-+		dev_warn(cpu_dev, "cpu%d: failed to enable vproc\n", cpu);
-+		goto out_free_resources;
-+	}
-+
- 	/* Both presence and absence of sram regulator are valid cases. */
- 	info->sram_reg = regulator_get_exclusive(cpu_dev, "sram");
- 	if (IS_ERR(info->sram_reg))
- 		info->sram_reg = NULL;
-+	else {
-+		ret = regulator_enable(info->sram_reg);
-+		if (ret) {
-+			dev_warn(cpu_dev, "cpu%d: failed to enable vsram\n", cpu);
-+			goto out_free_resources;
-+		}
-+	}
- 
- 	/* Get OPP-sharing information from "operating-points-v2" bindings */
- 	ret = dev_pm_opp_of_get_sharing_cpus(cpu_dev, &info->cpus);
-@@ -353,13 +366,21 @@ static int mtk_cpu_dvfs_info_init(struct
- 		goto out_free_resources;
- 	}
- 
-+	ret = clk_prepare_enable(info->cpu_clk);
-+	if (ret)
-+		goto out_free_opp_table;
-+
-+	ret = clk_prepare_enable(info->inter_clk);
-+	if (ret)
-+		goto out_disable_mux_clock;
-+
- 	/* Search a safe voltage for intermediate frequency. */
- 	rate = clk_get_rate(info->inter_clk);
- 	opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
- 	if (IS_ERR(opp)) {
- 		dev_err(cpu_dev, "cpu%d: failed to get intermediate opp\n", cpu);
- 		ret = PTR_ERR(opp);
--		goto out_free_opp_table;
-+		goto out_disable_inter_clock;
- 	}
- 	info->intermediate_voltage = dev_pm_opp_get_voltage(opp);
- 	dev_pm_opp_put(opp);
-@@ -372,10 +393,21 @@ static int mtk_cpu_dvfs_info_init(struct
- 
- 	return 0;
- 
-+out_disable_inter_clock:
-+	clk_disable_unprepare(info->inter_clk);
-+
-+out_disable_mux_clock:
-+	clk_disable_unprepare(info->cpu_clk);
-+
- out_free_opp_table:
- 	dev_pm_opp_of_cpumask_remove_table(&info->cpus);
- 
- out_free_resources:
-+	if (regulator_is_enabled(info->proc_reg))
-+		regulator_disable(info->proc_reg);
-+	if (info->sram_reg && regulator_is_enabled(info->sram_reg))
-+		regulator_disable(info->sram_reg);
-+
- 	if (!IS_ERR(info->proc_reg))
- 		regulator_put(info->proc_reg);
- 	if (!IS_ERR(info->sram_reg))
-@@ -390,14 +422,22 @@ out_free_resources:
- 
- static void mtk_cpu_dvfs_info_release(struct mtk_cpu_dvfs_info *info)
- {
--	if (!IS_ERR(info->proc_reg))
-+	if (!IS_ERR(info->proc_reg)) {
-+		regulator_disable(info->proc_reg);
- 		regulator_put(info->proc_reg);
--	if (!IS_ERR(info->sram_reg))
-+	}
-+	if (!IS_ERR(info->sram_reg)) {
-+		regulator_disable(info->sram_reg);
- 		regulator_put(info->sram_reg);
--	if (!IS_ERR(info->cpu_clk))
-+	}
-+	if (!IS_ERR(info->cpu_clk)) {
-+		clk_disable_unprepare(info->cpu_clk);
- 		clk_put(info->cpu_clk);
--	if (!IS_ERR(info->inter_clk))
-+	}
-+	if (!IS_ERR(info->inter_clk)) {
-+		clk_disable_unprepare(info->inter_clk);
- 		clk_put(info->inter_clk);
-+	}
- 
- 	dev_pm_opp_of_cpumask_remove_table(&info->cpus);
- }
diff --git a/target/linux/mediatek/patches-5.15/350-04-cpufreq-mediatek-Use-device-print-to-show-logs.patch b/target/linux/mediatek/patches-5.15/350-04-cpufreq-mediatek-Use-device-print-to-show-logs.patch
deleted file mode 100644
index 18e1da728a877a..00000000000000
--- a/target/linux/mediatek/patches-5.15/350-04-cpufreq-mediatek-Use-device-print-to-show-logs.patch
+++ /dev/null
@@ -1,161 +0,0 @@
-From a02e2b359141035d2d6999940bc1b9f83ec88587 Mon Sep 17 00:00:00 2001
-From: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Date: Fri, 22 Apr 2022 15:52:27 +0800
-Subject: [PATCH 04/21] cpufreq: mediatek: Use device print to show logs
-
-- Replace pr_* with dev_* to show logs.
-- Remove usage of __func__.
-
-Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 54 ++++++++++++++++--------------
- 1 file changed, 28 insertions(+), 26 deletions(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -67,7 +67,8 @@ static int mtk_cpufreq_voltage_tracking(
- 
- 	old_vproc = regulator_get_voltage(proc_reg);
- 	if (old_vproc < 0) {
--		pr_err("%s: invalid Vproc value: %d\n", __func__, old_vproc);
-+		dev_err(info->cpu_dev,
-+			"invalid Vproc value: %d\n", old_vproc);
- 		return old_vproc;
- 	}
- 	/* Vsram should not exceed the maximum allowed voltage of SoC. */
-@@ -83,14 +84,14 @@ static int mtk_cpufreq_voltage_tracking(
- 		do {
- 			old_vsram = regulator_get_voltage(sram_reg);
- 			if (old_vsram < 0) {
--				pr_err("%s: invalid Vsram value: %d\n",
--				       __func__, old_vsram);
-+				dev_err(info->cpu_dev,
-+					"invalid Vsram value: %d\n", old_vsram);
- 				return old_vsram;
- 			}
- 			old_vproc = regulator_get_voltage(proc_reg);
- 			if (old_vproc < 0) {
--				pr_err("%s: invalid Vproc value: %d\n",
--				       __func__, old_vproc);
-+				dev_err(info->cpu_dev,
-+					"invalid Vproc value: %d\n", old_vproc);
- 				return old_vproc;
- 			}
- 
-@@ -138,14 +139,14 @@ static int mtk_cpufreq_voltage_tracking(
- 		do {
- 			old_vproc = regulator_get_voltage(proc_reg);
- 			if (old_vproc < 0) {
--				pr_err("%s: invalid Vproc value: %d\n",
--				       __func__, old_vproc);
-+				dev_err(info->cpu_dev,
-+					"invalid Vproc value: %d\n", old_vproc);
- 				return old_vproc;
- 			}
- 			old_vsram = regulator_get_voltage(sram_reg);
- 			if (old_vsram < 0) {
--				pr_err("%s: invalid Vsram value: %d\n",
--				       __func__, old_vsram);
-+				dev_err(info->cpu_dev,
-+					"invalid Vsram value: %d\n", old_vsram);
- 				return old_vsram;
- 			}
- 
-@@ -216,7 +217,7 @@ static int mtk_cpufreq_set_target(struct
- 	old_freq_hz = clk_get_rate(cpu_clk);
- 	old_vproc = regulator_get_voltage(info->proc_reg);
- 	if (old_vproc < 0) {
--		pr_err("%s: invalid Vproc value: %d\n", __func__, old_vproc);
-+		dev_err(cpu_dev, "invalid Vproc value: %d\n", old_vproc);
- 		return old_vproc;
- 	}
- 
-@@ -224,8 +225,8 @@ static int mtk_cpufreq_set_target(struct
- 
- 	opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
- 	if (IS_ERR(opp)) {
--		pr_err("cpu%d: failed to find OPP for %ld\n",
--		       policy->cpu, freq_hz);
-+		dev_err(cpu_dev, "cpu%d: failed to find OPP for %ld\n",
-+			policy->cpu, freq_hz);
- 		return PTR_ERR(opp);
- 	}
- 	vproc = dev_pm_opp_get_voltage(opp);
-@@ -239,8 +240,8 @@ static int mtk_cpufreq_set_target(struct
- 	if (old_vproc < target_vproc) {
- 		ret = mtk_cpufreq_set_voltage(info, target_vproc);
- 		if (ret) {
--			pr_err("cpu%d: failed to scale up voltage!\n",
--			       policy->cpu);
-+			dev_err(cpu_dev,
-+				"cpu%d: failed to scale up voltage!\n", policy->cpu);
- 			mtk_cpufreq_set_voltage(info, old_vproc);
- 			return ret;
- 		}
-@@ -249,8 +250,8 @@ static int mtk_cpufreq_set_target(struct
- 	/* Reparent the CPU clock to intermediate clock. */
- 	ret = clk_set_parent(cpu_clk, info->inter_clk);
- 	if (ret) {
--		pr_err("cpu%d: failed to re-parent cpu clock!\n",
--		       policy->cpu);
-+		dev_err(cpu_dev,
-+			"cpu%d: failed to re-parent cpu clock!\n", policy->cpu);
- 		mtk_cpufreq_set_voltage(info, old_vproc);
- 		WARN_ON(1);
- 		return ret;
-@@ -259,8 +260,8 @@ static int mtk_cpufreq_set_target(struct
- 	/* Set the original PLL to target rate. */
- 	ret = clk_set_rate(armpll, freq_hz);
- 	if (ret) {
--		pr_err("cpu%d: failed to scale cpu clock rate!\n",
--		       policy->cpu);
-+		dev_err(cpu_dev,
-+			"cpu%d: failed to scale cpu clock rate!\n", policy->cpu);
- 		clk_set_parent(cpu_clk, armpll);
- 		mtk_cpufreq_set_voltage(info, old_vproc);
- 		return ret;
-@@ -269,8 +270,8 @@ static int mtk_cpufreq_set_target(struct
- 	/* Set parent of CPU clock back to the original PLL. */
- 	ret = clk_set_parent(cpu_clk, armpll);
- 	if (ret) {
--		pr_err("cpu%d: failed to re-parent cpu clock!\n",
--		       policy->cpu);
-+		dev_err(cpu_dev,
-+			"cpu%d: failed to re-parent cpu clock!\n", policy->cpu);
- 		mtk_cpufreq_set_voltage(info, inter_vproc);
- 		WARN_ON(1);
- 		return ret;
-@@ -283,8 +284,8 @@ static int mtk_cpufreq_set_target(struct
- 	if (vproc < inter_vproc || vproc < old_vproc) {
- 		ret = mtk_cpufreq_set_voltage(info, vproc);
- 		if (ret) {
--			pr_err("cpu%d: failed to scale down voltage!\n",
--			       policy->cpu);
-+			dev_err(cpu_dev,
-+				"cpu%d: failed to scale down voltage!\n", policy->cpu);
- 			clk_set_parent(cpu_clk, info->inter_clk);
- 			clk_set_rate(armpll, old_freq_hz);
- 			clk_set_parent(cpu_clk, armpll);
-@@ -450,15 +451,16 @@ static int mtk_cpufreq_init(struct cpufr
- 
- 	info = mtk_cpu_dvfs_info_lookup(policy->cpu);
- 	if (!info) {
--		pr_err("dvfs info for cpu%d is not initialized.\n",
--		       policy->cpu);
-+		dev_err(info->cpu_dev,
-+			"dvfs info for cpu%d is not initialized.\n", policy->cpu);
- 		return -EINVAL;
- 	}
- 
- 	ret = dev_pm_opp_init_cpufreq_table(info->cpu_dev, &freq_table);
- 	if (ret) {
--		pr_err("failed to init cpufreq table for cpu%d: %d\n",
--		       policy->cpu, ret);
-+		dev_err(info->cpu_dev,
-+			"failed to init cpufreq table for cpu%d: %d\n",
-+			policy->cpu, ret);
- 		return ret;
- 	}
- 
diff --git a/target/linux/mediatek/patches-5.15/350-05-cpufreq-mediatek-Replace-old_-with-pre_.patch b/target/linux/mediatek/patches-5.15/350-05-cpufreq-mediatek-Replace-old_-with-pre_.patch
deleted file mode 100644
index 8506f4e47769f9..00000000000000
--- a/target/linux/mediatek/patches-5.15/350-05-cpufreq-mediatek-Replace-old_-with-pre_.patch
+++ /dev/null
@@ -1,201 +0,0 @@
-From 35832d9f9c5c1da01420d962dc56e7e61d104829 Mon Sep 17 00:00:00 2001
-From: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Date: Fri, 22 Apr 2022 15:52:28 +0800
-Subject: [PATCH 05/21] cpufreq: mediatek: Replace old_* with pre_*
-
-To make driver more readable, replace old_* with pre_*.
-
-Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 84 +++++++++++++++---------------
- 1 file changed, 42 insertions(+), 42 deletions(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -63,18 +63,18 @@ static int mtk_cpufreq_voltage_tracking(
- {
- 	struct regulator *proc_reg = info->proc_reg;
- 	struct regulator *sram_reg = info->sram_reg;
--	int old_vproc, old_vsram, new_vsram, vsram, vproc, ret;
-+	int pre_vproc, pre_vsram, new_vsram, vsram, vproc, ret;
- 
--	old_vproc = regulator_get_voltage(proc_reg);
--	if (old_vproc < 0) {
-+	pre_vproc = regulator_get_voltage(proc_reg);
-+	if (pre_vproc < 0) {
- 		dev_err(info->cpu_dev,
--			"invalid Vproc value: %d\n", old_vproc);
--		return old_vproc;
-+			"invalid Vproc value: %d\n", pre_vproc);
-+		return pre_vproc;
- 	}
- 	/* Vsram should not exceed the maximum allowed voltage of SoC. */
- 	new_vsram = min(new_vproc + MIN_VOLT_SHIFT, MAX_VOLT_LIMIT);
- 
--	if (old_vproc < new_vproc) {
-+	if (pre_vproc < new_vproc) {
- 		/*
- 		 * When scaling up voltages, Vsram and Vproc scale up step
- 		 * by step. At each step, set Vsram to (Vproc + 200mV) first,
-@@ -82,20 +82,20 @@ static int mtk_cpufreq_voltage_tracking(
- 		 * Keep doing it until Vsram and Vproc hit target voltages.
- 		 */
- 		do {
--			old_vsram = regulator_get_voltage(sram_reg);
--			if (old_vsram < 0) {
-+			pre_vsram = regulator_get_voltage(sram_reg);
-+			if (pre_vsram < 0) {
- 				dev_err(info->cpu_dev,
--					"invalid Vsram value: %d\n", old_vsram);
--				return old_vsram;
-+					"invalid Vsram value: %d\n", pre_vsram);
-+				return pre_vsram;
- 			}
--			old_vproc = regulator_get_voltage(proc_reg);
--			if (old_vproc < 0) {
-+			pre_vproc = regulator_get_voltage(proc_reg);
-+			if (pre_vproc < 0) {
- 				dev_err(info->cpu_dev,
--					"invalid Vproc value: %d\n", old_vproc);
--				return old_vproc;
-+					"invalid Vproc value: %d\n", pre_vproc);
-+				return pre_vproc;
- 			}
- 
--			vsram = min(new_vsram, old_vproc + MAX_VOLT_SHIFT);
-+			vsram = min(new_vsram, pre_vproc + MAX_VOLT_SHIFT);
- 
- 			if (vsram + VOLT_TOL >= MAX_VOLT_LIMIT) {
- 				vsram = MAX_VOLT_LIMIT;
-@@ -124,12 +124,12 @@ static int mtk_cpufreq_voltage_tracking(
- 			ret = regulator_set_voltage(proc_reg, vproc,
- 						    vproc + VOLT_TOL);
- 			if (ret) {
--				regulator_set_voltage(sram_reg, old_vsram,
--						      old_vsram);
-+				regulator_set_voltage(sram_reg, pre_vsram,
-+						      pre_vsram);
- 				return ret;
- 			}
- 		} while (vproc < new_vproc || vsram < new_vsram);
--	} else if (old_vproc > new_vproc) {
-+	} else if (pre_vproc > new_vproc) {
- 		/*
- 		 * When scaling down voltages, Vsram and Vproc scale down step
- 		 * by step. At each step, set Vproc to (Vsram - 200mV) first,
-@@ -137,20 +137,20 @@ static int mtk_cpufreq_voltage_tracking(
- 		 * Keep doing it until Vsram and Vproc hit target voltages.
- 		 */
- 		do {
--			old_vproc = regulator_get_voltage(proc_reg);
--			if (old_vproc < 0) {
-+			pre_vproc = regulator_get_voltage(proc_reg);
-+			if (pre_vproc < 0) {
- 				dev_err(info->cpu_dev,
--					"invalid Vproc value: %d\n", old_vproc);
--				return old_vproc;
-+					"invalid Vproc value: %d\n", pre_vproc);
-+				return pre_vproc;
- 			}
--			old_vsram = regulator_get_voltage(sram_reg);
--			if (old_vsram < 0) {
-+			pre_vsram = regulator_get_voltage(sram_reg);
-+			if (pre_vsram < 0) {
- 				dev_err(info->cpu_dev,
--					"invalid Vsram value: %d\n", old_vsram);
--				return old_vsram;
-+					"invalid Vsram value: %d\n", pre_vsram);
-+				return pre_vsram;
- 			}
- 
--			vproc = max(new_vproc, old_vsram - MAX_VOLT_SHIFT);
-+			vproc = max(new_vproc, pre_vsram - MAX_VOLT_SHIFT);
- 			ret = regulator_set_voltage(proc_reg, vproc,
- 						    vproc + VOLT_TOL);
- 			if (ret)
-@@ -180,8 +180,8 @@ static int mtk_cpufreq_voltage_tracking(
- 			}
- 
- 			if (ret) {
--				regulator_set_voltage(proc_reg, old_vproc,
--						      old_vproc);
-+				regulator_set_voltage(proc_reg, pre_vproc,
-+						      pre_vproc);
- 				return ret;
- 			}
- 		} while (vproc > new_vproc + VOLT_TOL ||
-@@ -209,16 +209,16 @@ static int mtk_cpufreq_set_target(struct
- 	struct mtk_cpu_dvfs_info *info = policy->driver_data;
- 	struct device *cpu_dev = info->cpu_dev;
- 	struct dev_pm_opp *opp;
--	long freq_hz, old_freq_hz;
--	int vproc, old_vproc, inter_vproc, target_vproc, ret;
-+	long freq_hz, pre_freq_hz;
-+	int vproc, pre_vproc, inter_vproc, target_vproc, ret;
- 
- 	inter_vproc = info->intermediate_voltage;
- 
--	old_freq_hz = clk_get_rate(cpu_clk);
--	old_vproc = regulator_get_voltage(info->proc_reg);
--	if (old_vproc < 0) {
--		dev_err(cpu_dev, "invalid Vproc value: %d\n", old_vproc);
--		return old_vproc;
-+	pre_freq_hz = clk_get_rate(cpu_clk);
-+	pre_vproc = regulator_get_voltage(info->proc_reg);
-+	if (pre_vproc < 0) {
-+		dev_err(cpu_dev, "invalid Vproc value: %d\n", pre_vproc);
-+		return pre_vproc;
- 	}
- 
- 	freq_hz = freq_table[index].frequency * 1000;
-@@ -237,12 +237,12 @@ static int mtk_cpufreq_set_target(struct
- 	 * current voltage, scale up voltage first.
- 	 */
- 	target_vproc = (inter_vproc > vproc) ? inter_vproc : vproc;
--	if (old_vproc < target_vproc) {
-+	if (pre_vproc < target_vproc) {
- 		ret = mtk_cpufreq_set_voltage(info, target_vproc);
- 		if (ret) {
- 			dev_err(cpu_dev,
- 				"cpu%d: failed to scale up voltage!\n", policy->cpu);
--			mtk_cpufreq_set_voltage(info, old_vproc);
-+			mtk_cpufreq_set_voltage(info, pre_vproc);
- 			return ret;
- 		}
- 	}
-@@ -252,7 +252,7 @@ static int mtk_cpufreq_set_target(struct
- 	if (ret) {
- 		dev_err(cpu_dev,
- 			"cpu%d: failed to re-parent cpu clock!\n", policy->cpu);
--		mtk_cpufreq_set_voltage(info, old_vproc);
-+		mtk_cpufreq_set_voltage(info, pre_vproc);
- 		WARN_ON(1);
- 		return ret;
- 	}
-@@ -263,7 +263,7 @@ static int mtk_cpufreq_set_target(struct
- 		dev_err(cpu_dev,
- 			"cpu%d: failed to scale cpu clock rate!\n", policy->cpu);
- 		clk_set_parent(cpu_clk, armpll);
--		mtk_cpufreq_set_voltage(info, old_vproc);
-+		mtk_cpufreq_set_voltage(info, pre_vproc);
- 		return ret;
- 	}
- 
-@@ -281,13 +281,13 @@ static int mtk_cpufreq_set_target(struct
- 	 * If the new voltage is lower than the intermediate voltage or the
- 	 * original voltage, scale down to the new voltage.
- 	 */
--	if (vproc < inter_vproc || vproc < old_vproc) {
-+	if (vproc < inter_vproc || vproc < pre_vproc) {
- 		ret = mtk_cpufreq_set_voltage(info, vproc);
- 		if (ret) {
- 			dev_err(cpu_dev,
- 				"cpu%d: failed to scale down voltage!\n", policy->cpu);
- 			clk_set_parent(cpu_clk, info->inter_clk);
--			clk_set_rate(armpll, old_freq_hz);
-+			clk_set_rate(armpll, pre_freq_hz);
- 			clk_set_parent(cpu_clk, armpll);
- 			return ret;
- 		}
diff --git a/target/linux/mediatek/patches-5.15/350-06-cpufreq-mediatek-Record-previous-target-vproc-value.patch b/target/linux/mediatek/patches-5.15/350-06-cpufreq-mediatek-Record-previous-target-vproc-value.patch
deleted file mode 100644
index 94e6617d267aad..00000000000000
--- a/target/linux/mediatek/patches-5.15/350-06-cpufreq-mediatek-Record-previous-target-vproc-value.patch
+++ /dev/null
@@ -1,64 +0,0 @@
-From 34737eb8d0daa0d4183f10286a2f55d8788066bc Mon Sep 17 00:00:00 2001
-From: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Date: Fri, 22 Apr 2022 15:52:29 +0800
-Subject: [PATCH 06/21] cpufreq: mediatek: Record previous target vproc value
-
-We found the buck voltage may not be exactly the same with what we set
-because CPU may share the same buck with other module.
-Therefore, we need to record the previous desired value instead of reading
-it from regulators.
-
-Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
-Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 20 ++++++++++++++++----
- 1 file changed, 16 insertions(+), 4 deletions(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -40,6 +40,7 @@ struct mtk_cpu_dvfs_info {
- 	struct list_head list_head;
- 	int intermediate_voltage;
- 	bool need_voltage_tracking;
-+	int pre_vproc;
- };
- 
- static struct platform_device *cpufreq_pdev;
-@@ -193,11 +194,17 @@ static int mtk_cpufreq_voltage_tracking(
- 
- static int mtk_cpufreq_set_voltage(struct mtk_cpu_dvfs_info *info, int vproc)
- {
-+	int ret;
-+
- 	if (info->need_voltage_tracking)
--		return mtk_cpufreq_voltage_tracking(info, vproc);
-+		ret = mtk_cpufreq_voltage_tracking(info, vproc);
- 	else
--		return regulator_set_voltage(info->proc_reg, vproc,
--					     vproc + VOLT_TOL);
-+		ret = regulator_set_voltage(info->proc_reg, vproc,
-+					    MAX_VOLT_LIMIT);
-+	if (!ret)
-+		info->pre_vproc = vproc;
-+
-+	return ret;
- }
- 
- static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
-@@ -215,7 +222,12 @@ static int mtk_cpufreq_set_target(struct
- 	inter_vproc = info->intermediate_voltage;
- 
- 	pre_freq_hz = clk_get_rate(cpu_clk);
--	pre_vproc = regulator_get_voltage(info->proc_reg);
-+
-+	if (unlikely(info->pre_vproc <= 0))
-+		pre_vproc = regulator_get_voltage(info->proc_reg);
-+	else
-+		pre_vproc = info->pre_vproc;
-+
- 	if (pre_vproc < 0) {
- 		dev_err(cpu_dev, "invalid Vproc value: %d\n", pre_vproc);
- 		return pre_vproc;
diff --git a/target/linux/mediatek/patches-5.15/350-07-cpufreq-mediatek-Make-sram-regulator-optional.patch b/target/linux/mediatek/patches-5.15/350-07-cpufreq-mediatek-Make-sram-regulator-optional.patch
deleted file mode 100644
index 4b74873b158fe6..00000000000000
--- a/target/linux/mediatek/patches-5.15/350-07-cpufreq-mediatek-Make-sram-regulator-optional.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From f6114c2bc563a8050e9dc874ad87e1448865f031 Mon Sep 17 00:00:00 2001
-From: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Date: Fri, 22 Apr 2022 15:52:33 +0800
-Subject: [PATCH 07/21] cpufreq: mediatek: Make sram regulator optional
-
-For some MediaTek SoCs, like MT8186, it's possible that the sram regulator
-is shared between CPU and CCI.
-We hope regulator framework can return error for error handling rather
-than a dummy handler from regulator_get api.
-Therefore, we choose to use regulator_get_optional.
-
-Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -354,7 +354,7 @@ static int mtk_cpu_dvfs_info_init(struct
- 	}
- 
- 	/* Both presence and absence of sram regulator are valid cases. */
--	info->sram_reg = regulator_get_exclusive(cpu_dev, "sram");
-+	info->sram_reg = regulator_get_optional(cpu_dev, "sram");
- 	if (IS_ERR(info->sram_reg))
- 		info->sram_reg = NULL;
- 	else {
diff --git a/target/linux/mediatek/patches-5.15/350-08-cpufreq-mediatek-Fix-NULL-pointer-dereference-in-med.patch b/target/linux/mediatek/patches-5.15/350-08-cpufreq-mediatek-Fix-NULL-pointer-dereference-in-med.patch
deleted file mode 100644
index f2f572a753faec..00000000000000
--- a/target/linux/mediatek/patches-5.15/350-08-cpufreq-mediatek-Fix-NULL-pointer-dereference-in-med.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From fa7030d8ad4638acfd9e0fac84a20716d031dc95 Mon Sep 17 00:00:00 2001
-From: Wan Jiabing <wanjiabing@vivo.com>
-Date: Tue, 26 Apr 2022 19:17:14 +0800
-Subject: [PATCH 08/21] cpufreq: mediatek: Fix NULL pointer dereference in
- mediatek-cpufreq
-
-Fix following coccicheck error:
-drivers/cpufreq/mediatek-cpufreq.c:464:16-23: ERROR: info is NULL but dereferenced.
-
-Use pr_err instead of dev_err to avoid dereferring a NULL pointer.
-
-Fixes: f52b16ba9fe4 ("cpufreq: mediatek: Use device print to show logs")
-Signed-off-by: Wan Jiabing <wanjiabing@vivo.com>
-Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -463,8 +463,8 @@ static int mtk_cpufreq_init(struct cpufr
- 
- 	info = mtk_cpu_dvfs_info_lookup(policy->cpu);
- 	if (!info) {
--		dev_err(info->cpu_dev,
--			"dvfs info for cpu%d is not initialized.\n", policy->cpu);
-+		pr_err("dvfs info for cpu%d is not initialized.\n",
-+			policy->cpu);
- 		return -EINVAL;
- 	}
- 
diff --git a/target/linux/mediatek/patches-5.15/350-09-cpufreq-mediatek-Move-voltage-limits-to-platform-dat.patch b/target/linux/mediatek/patches-5.15/350-09-cpufreq-mediatek-Move-voltage-limits-to-platform-dat.patch
deleted file mode 100644
index 23b319648dc937..00000000000000
--- a/target/linux/mediatek/patches-5.15/350-09-cpufreq-mediatek-Move-voltage-limits-to-platform-dat.patch
+++ /dev/null
@@ -1,227 +0,0 @@
-From be2354b064e6bafbbad599ae2e10569ba4f7d5a6 Mon Sep 17 00:00:00 2001
-From: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Date: Thu, 5 May 2022 19:52:19 +0800
-Subject: [PATCH 09/21] cpufreq: mediatek: Move voltage limits to platform data
-
-Voltages and shifts are defined as macros originally.
-There are different requirements of these values for each MediaTek SoCs.
-Therefore, we add the platform data and move these values into it.
-
-Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 84 +++++++++++++++++++++---------
- 1 file changed, 58 insertions(+), 26 deletions(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -10,15 +10,21 @@
- #include <linux/cpumask.h>
- #include <linux/module.h>
- #include <linux/of.h>
-+#include <linux/of_platform.h>
- #include <linux/platform_device.h>
- #include <linux/pm_opp.h>
- #include <linux/regulator/consumer.h>
- 
--#define MIN_VOLT_SHIFT		(100000)
--#define MAX_VOLT_SHIFT		(200000)
--#define MAX_VOLT_LIMIT		(1150000)
- #define VOLT_TOL		(10000)
- 
-+struct mtk_cpufreq_platform_data {
-+	int min_volt_shift;
-+	int max_volt_shift;
-+	int proc_max_volt;
-+	int sram_min_volt;
-+	int sram_max_volt;
-+};
-+
- /*
-  * The struct mtk_cpu_dvfs_info holds necessary information for doing CPU DVFS
-  * on each CPU power/clock domain of Mediatek SoCs. Each CPU cluster in
-@@ -41,6 +47,7 @@ struct mtk_cpu_dvfs_info {
- 	int intermediate_voltage;
- 	bool need_voltage_tracking;
- 	int pre_vproc;
-+	const struct mtk_cpufreq_platform_data *soc_data;
- };
- 
- static struct platform_device *cpufreq_pdev;
-@@ -62,6 +69,7 @@ static struct mtk_cpu_dvfs_info *mtk_cpu
- static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info,
- 					int new_vproc)
- {
-+	const struct mtk_cpufreq_platform_data *soc_data = info->soc_data;
- 	struct regulator *proc_reg = info->proc_reg;
- 	struct regulator *sram_reg = info->sram_reg;
- 	int pre_vproc, pre_vsram, new_vsram, vsram, vproc, ret;
-@@ -73,7 +81,8 @@ static int mtk_cpufreq_voltage_tracking(
- 		return pre_vproc;
- 	}
- 	/* Vsram should not exceed the maximum allowed voltage of SoC. */
--	new_vsram = min(new_vproc + MIN_VOLT_SHIFT, MAX_VOLT_LIMIT);
-+	new_vsram = min(new_vproc + soc_data->min_volt_shift,
-+			soc_data->sram_max_volt);
- 
- 	if (pre_vproc < new_vproc) {
- 		/*
-@@ -96,10 +105,11 @@ static int mtk_cpufreq_voltage_tracking(
- 				return pre_vproc;
- 			}
- 
--			vsram = min(new_vsram, pre_vproc + MAX_VOLT_SHIFT);
-+			vsram = min(new_vsram,
-+				    pre_vproc + soc_data->min_volt_shift);
- 
--			if (vsram + VOLT_TOL >= MAX_VOLT_LIMIT) {
--				vsram = MAX_VOLT_LIMIT;
-+			if (vsram + VOLT_TOL >= soc_data->sram_max_volt) {
-+				vsram = soc_data->sram_max_volt;
- 
- 				/*
- 				 * If the target Vsram hits the maximum voltage,
-@@ -117,7 +127,7 @@ static int mtk_cpufreq_voltage_tracking(
- 				ret = regulator_set_voltage(sram_reg, vsram,
- 							    vsram + VOLT_TOL);
- 
--				vproc = vsram - MIN_VOLT_SHIFT;
-+				vproc = vsram - soc_data->min_volt_shift;
- 			}
- 			if (ret)
- 				return ret;
-@@ -151,7 +161,8 @@ static int mtk_cpufreq_voltage_tracking(
- 				return pre_vsram;
- 			}
- 
--			vproc = max(new_vproc, pre_vsram - MAX_VOLT_SHIFT);
-+			vproc = max(new_vproc,
-+				    pre_vsram - soc_data->max_volt_shift);
- 			ret = regulator_set_voltage(proc_reg, vproc,
- 						    vproc + VOLT_TOL);
- 			if (ret)
-@@ -160,10 +171,11 @@ static int mtk_cpufreq_voltage_tracking(
- 			if (vproc == new_vproc)
- 				vsram = new_vsram;
- 			else
--				vsram = max(new_vsram, vproc + MIN_VOLT_SHIFT);
-+				vsram = max(new_vsram,
-+					    vproc + soc_data->min_volt_shift);
- 
--			if (vsram + VOLT_TOL >= MAX_VOLT_LIMIT) {
--				vsram = MAX_VOLT_LIMIT;
-+			if (vsram + VOLT_TOL >= soc_data->sram_max_volt) {
-+				vsram = soc_data->sram_max_volt;
- 
- 				/*
- 				 * If the target Vsram hits the maximum voltage,
-@@ -194,13 +206,14 @@ static int mtk_cpufreq_voltage_tracking(
- 
- static int mtk_cpufreq_set_voltage(struct mtk_cpu_dvfs_info *info, int vproc)
- {
-+	const struct mtk_cpufreq_platform_data *soc_data = info->soc_data;
- 	int ret;
- 
- 	if (info->need_voltage_tracking)
- 		ret = mtk_cpufreq_voltage_tracking(info, vproc);
- 	else
- 		ret = regulator_set_voltage(info->proc_reg, vproc,
--					    MAX_VOLT_LIMIT);
-+					    soc_data->proc_max_volt);
- 	if (!ret)
- 		info->pre_vproc = vproc;
- 
-@@ -509,9 +522,17 @@ static struct cpufreq_driver mtk_cpufreq
- 
- static int mtk_cpufreq_probe(struct platform_device *pdev)
- {
-+	const struct mtk_cpufreq_platform_data *data;
- 	struct mtk_cpu_dvfs_info *info, *tmp;
- 	int cpu, ret;
- 
-+	data = dev_get_platdata(&pdev->dev);
-+	if (!data) {
-+		dev_err(&pdev->dev,
-+			"failed to get mtk cpufreq platform data\n");
-+		return -ENODEV;
-+	}
-+
- 	for_each_possible_cpu(cpu) {
- 		info = mtk_cpu_dvfs_info_lookup(cpu);
- 		if (info)
-@@ -523,6 +544,7 @@ static int mtk_cpufreq_probe(struct plat
- 			goto release_dvfs_info_list;
- 		}
- 
-+		info->soc_data = data;
- 		ret = mtk_cpu_dvfs_info_init(info, cpu);
- 		if (ret) {
- 			dev_err(&pdev->dev,
-@@ -558,20 +580,27 @@ static struct platform_driver mtk_cpufre
- 	.probe		= mtk_cpufreq_probe,
- };
- 
-+static const struct mtk_cpufreq_platform_data mt2701_platform_data = {
-+	.min_volt_shift = 100000,
-+	.max_volt_shift = 200000,
-+	.proc_max_volt = 1150000,
-+	.sram_min_volt = 0,
-+	.sram_max_volt = 1150000,
-+};
-+
- /* List of machines supported by this driver */
- static const struct of_device_id mtk_cpufreq_machines[] __initconst = {
--	{ .compatible = "mediatek,mt2701", },
--	{ .compatible = "mediatek,mt2712", },
--	{ .compatible = "mediatek,mt7622", },
--	{ .compatible = "mediatek,mt7623", },
--	{ .compatible = "mediatek,mt8167", },
--	{ .compatible = "mediatek,mt817x", },
--	{ .compatible = "mediatek,mt8173", },
--	{ .compatible = "mediatek,mt8176", },
--	{ .compatible = "mediatek,mt8183", },
--	{ .compatible = "mediatek,mt8365", },
--	{ .compatible = "mediatek,mt8516", },
--
-+	{ .compatible = "mediatek,mt2701", .data = &mt2701_platform_data },
-+	{ .compatible = "mediatek,mt2712", .data = &mt2701_platform_data },
-+	{ .compatible = "mediatek,mt7622", .data = &mt2701_platform_data },
-+	{ .compatible = "mediatek,mt7623", .data = &mt2701_platform_data },
-+	{ .compatible = "mediatek,mt8167", .data = &mt2701_platform_data },
-+	{ .compatible = "mediatek,mt817x", .data = &mt2701_platform_data },
-+	{ .compatible = "mediatek,mt8173", .data = &mt2701_platform_data },
-+	{ .compatible = "mediatek,mt8176", .data = &mt2701_platform_data },
-+	{ .compatible = "mediatek,mt8183", .data = &mt2701_platform_data },
-+	{ .compatible = "mediatek,mt8365", .data = &mt2701_platform_data },
-+	{ .compatible = "mediatek,mt8516", .data = &mt2701_platform_data },
- 	{ }
- };
- MODULE_DEVICE_TABLE(of, mtk_cpufreq_machines);
-@@ -580,6 +609,7 @@ static int __init mtk_cpufreq_driver_ini
- {
- 	struct device_node *np;
- 	const struct of_device_id *match;
-+	const struct mtk_cpufreq_platform_data *data;
- 	int err;
- 
- 	np = of_find_node_by_path("/");
-@@ -592,6 +622,7 @@ static int __init mtk_cpufreq_driver_ini
- 		pr_debug("Machine is not compatible with mtk-cpufreq\n");
- 		return -ENODEV;
- 	}
-+	data = match->data;
- 
- 	err = platform_driver_register(&mtk_cpufreq_platdrv);
- 	if (err)
-@@ -603,7 +634,8 @@ static int __init mtk_cpufreq_driver_ini
- 	 * and the device registration codes are put here to handle defer
- 	 * probing.
- 	 */
--	cpufreq_pdev = platform_device_register_simple("mtk-cpufreq", -1, NULL, 0);
-+	cpufreq_pdev = platform_device_register_data(NULL, "mtk-cpufreq", -1,
-+						     data, sizeof(*data));
- 	if (IS_ERR(cpufreq_pdev)) {
- 		pr_err("failed to register mtk-cpufreq platform device\n");
- 		platform_driver_unregister(&mtk_cpufreq_platdrv);
diff --git a/target/linux/mediatek/patches-5.15/350-10-cpufreq-mediatek-Refine-mtk_cpufreq_voltage_tracking.patch b/target/linux/mediatek/patches-5.15/350-10-cpufreq-mediatek-Refine-mtk_cpufreq_voltage_tracking.patch
deleted file mode 100644
index 0ba9471ffa7128..00000000000000
--- a/target/linux/mediatek/patches-5.15/350-10-cpufreq-mediatek-Refine-mtk_cpufreq_voltage_tracking.patch
+++ /dev/null
@@ -1,255 +0,0 @@
-From 944b041c91f1e1cd762c39c1222f078550149486 Mon Sep 17 00:00:00 2001
-From: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Date: Thu, 5 May 2022 19:52:20 +0800
-Subject: [PATCH 10/21] cpufreq: mediatek: Refine
- mtk_cpufreq_voltage_tracking()
-
-Because the difference of sram and proc should in a range of min_volt_shift
-and max_volt_shift. We need to adjust the sram and proc step by step.
-
-We replace VOLT_TOL (voltage tolerance) with the platform data and update the
-logic to determine the voltage boundary and invoking regulator_set_voltage.
-
-- Use 'sram_min_volt' and 'sram_max_volt' to determine the voltage boundary
-  of sram regulator.
-- Use (sram_min_volt - min_volt_shift) and 'proc_max_volt' to determine the
-  voltage boundary of vproc regulator.
-
-Moreover, to prevent infinite loop when tracking voltage, we calculate the
-maximum value for each platform data.
-We assume min voltage is 0 and tracking target voltage using
-min_volt_shift for each iteration.
-The retry_max is 3 times of expeted iteration count.
-
-Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 147 ++++++++++-------------------
- 1 file changed, 51 insertions(+), 96 deletions(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -8,6 +8,7 @@
- #include <linux/cpu.h>
- #include <linux/cpufreq.h>
- #include <linux/cpumask.h>
-+#include <linux/minmax.h>
- #include <linux/module.h>
- #include <linux/of.h>
- #include <linux/of_platform.h>
-@@ -15,8 +16,6 @@
- #include <linux/pm_opp.h>
- #include <linux/regulator/consumer.h>
- 
--#define VOLT_TOL		(10000)
--
- struct mtk_cpufreq_platform_data {
- 	int min_volt_shift;
- 	int max_volt_shift;
-@@ -48,6 +47,7 @@ struct mtk_cpu_dvfs_info {
- 	bool need_voltage_tracking;
- 	int pre_vproc;
- 	const struct mtk_cpufreq_platform_data *soc_data;
-+	int vtrack_max;
- };
- 
- static struct platform_device *cpufreq_pdev;
-@@ -73,6 +73,7 @@ static int mtk_cpufreq_voltage_tracking(
- 	struct regulator *proc_reg = info->proc_reg;
- 	struct regulator *sram_reg = info->sram_reg;
- 	int pre_vproc, pre_vsram, new_vsram, vsram, vproc, ret;
-+	int retry = info->vtrack_max;
- 
- 	pre_vproc = regulator_get_voltage(proc_reg);
- 	if (pre_vproc < 0) {
-@@ -80,91 +81,44 @@ static int mtk_cpufreq_voltage_tracking(
- 			"invalid Vproc value: %d\n", pre_vproc);
- 		return pre_vproc;
- 	}
--	/* Vsram should not exceed the maximum allowed voltage of SoC. */
--	new_vsram = min(new_vproc + soc_data->min_volt_shift,
--			soc_data->sram_max_volt);
--
--	if (pre_vproc < new_vproc) {
--		/*
--		 * When scaling up voltages, Vsram and Vproc scale up step
--		 * by step. At each step, set Vsram to (Vproc + 200mV) first,
--		 * then set Vproc to (Vsram - 100mV).
--		 * Keep doing it until Vsram and Vproc hit target voltages.
--		 */
--		do {
--			pre_vsram = regulator_get_voltage(sram_reg);
--			if (pre_vsram < 0) {
--				dev_err(info->cpu_dev,
--					"invalid Vsram value: %d\n", pre_vsram);
--				return pre_vsram;
--			}
--			pre_vproc = regulator_get_voltage(proc_reg);
--			if (pre_vproc < 0) {
--				dev_err(info->cpu_dev,
--					"invalid Vproc value: %d\n", pre_vproc);
--				return pre_vproc;
--			}
- 
--			vsram = min(new_vsram,
--				    pre_vproc + soc_data->min_volt_shift);
-+	pre_vsram = regulator_get_voltage(sram_reg);
-+	if (pre_vsram < 0) {
-+		dev_err(info->cpu_dev, "invalid Vsram value: %d\n", pre_vsram);
-+		return pre_vsram;
-+	}
- 
--			if (vsram + VOLT_TOL >= soc_data->sram_max_volt) {
--				vsram = soc_data->sram_max_volt;
-+	new_vsram = clamp(new_vproc + soc_data->min_volt_shift,
-+			  soc_data->sram_min_volt, soc_data->sram_max_volt);
-+
-+	do {
-+		if (pre_vproc <= new_vproc) {
-+			vsram = clamp(pre_vproc + soc_data->max_volt_shift,
-+				      soc_data->sram_min_volt, new_vsram);
-+			ret = regulator_set_voltage(sram_reg, vsram,
-+						    soc_data->sram_max_volt);
- 
--				/*
--				 * If the target Vsram hits the maximum voltage,
--				 * try to set the exact voltage value first.
--				 */
--				ret = regulator_set_voltage(sram_reg, vsram,
--							    vsram);
--				if (ret)
--					ret = regulator_set_voltage(sram_reg,
--							vsram - VOLT_TOL,
--							vsram);
-+			if (ret)
-+				return ret;
- 
-+			if (vsram == soc_data->sram_max_volt ||
-+			    new_vsram == soc_data->sram_min_volt)
- 				vproc = new_vproc;
--			} else {
--				ret = regulator_set_voltage(sram_reg, vsram,
--							    vsram + VOLT_TOL);
--
-+			else
- 				vproc = vsram - soc_data->min_volt_shift;
--			}
--			if (ret)
--				return ret;
- 
- 			ret = regulator_set_voltage(proc_reg, vproc,
--						    vproc + VOLT_TOL);
-+						    soc_data->proc_max_volt);
- 			if (ret) {
- 				regulator_set_voltage(sram_reg, pre_vsram,
--						      pre_vsram);
-+						      soc_data->sram_max_volt);
- 				return ret;
- 			}
--		} while (vproc < new_vproc || vsram < new_vsram);
--	} else if (pre_vproc > new_vproc) {
--		/*
--		 * When scaling down voltages, Vsram and Vproc scale down step
--		 * by step. At each step, set Vproc to (Vsram - 200mV) first,
--		 * then set Vproc to (Vproc + 100mV).
--		 * Keep doing it until Vsram and Vproc hit target voltages.
--		 */
--		do {
--			pre_vproc = regulator_get_voltage(proc_reg);
--			if (pre_vproc < 0) {
--				dev_err(info->cpu_dev,
--					"invalid Vproc value: %d\n", pre_vproc);
--				return pre_vproc;
--			}
--			pre_vsram = regulator_get_voltage(sram_reg);
--			if (pre_vsram < 0) {
--				dev_err(info->cpu_dev,
--					"invalid Vsram value: %d\n", pre_vsram);
--				return pre_vsram;
--			}
--
-+		} else if (pre_vproc > new_vproc) {
- 			vproc = max(new_vproc,
- 				    pre_vsram - soc_data->max_volt_shift);
- 			ret = regulator_set_voltage(proc_reg, vproc,
--						    vproc + VOLT_TOL);
-+						    soc_data->proc_max_volt);
- 			if (ret)
- 				return ret;
- 
-@@ -174,32 +128,24 @@ static int mtk_cpufreq_voltage_tracking(
- 				vsram = max(new_vsram,
- 					    vproc + soc_data->min_volt_shift);
- 
--			if (vsram + VOLT_TOL >= soc_data->sram_max_volt) {
--				vsram = soc_data->sram_max_volt;
--
--				/*
--				 * If the target Vsram hits the maximum voltage,
--				 * try to set the exact voltage value first.
--				 */
--				ret = regulator_set_voltage(sram_reg, vsram,
--							    vsram);
--				if (ret)
--					ret = regulator_set_voltage(sram_reg,
--							vsram - VOLT_TOL,
--							vsram);
--			} else {
--				ret = regulator_set_voltage(sram_reg, vsram,
--							    vsram + VOLT_TOL);
--			}
--
-+			ret = regulator_set_voltage(sram_reg, vsram,
-+						    soc_data->sram_max_volt);
- 			if (ret) {
- 				regulator_set_voltage(proc_reg, pre_vproc,
--						      pre_vproc);
-+						      soc_data->proc_max_volt);
- 				return ret;
- 			}
--		} while (vproc > new_vproc + VOLT_TOL ||
--			 vsram > new_vsram + VOLT_TOL);
--	}
-+		}
-+
-+		pre_vproc = vproc;
-+		pre_vsram = vsram;
-+
-+		if (--retry < 0) {
-+			dev_err(info->cpu_dev,
-+				"over loop count, failed to set voltage\n");
-+			return -EINVAL;
-+		}
-+	} while (vproc != new_vproc || vsram != new_vsram);
- 
- 	return 0;
- }
-@@ -261,8 +207,8 @@ static int mtk_cpufreq_set_target(struct
- 	 * If the new voltage or the intermediate voltage is higher than the
- 	 * current voltage, scale up voltage first.
- 	 */
--	target_vproc = (inter_vproc > vproc) ? inter_vproc : vproc;
--	if (pre_vproc < target_vproc) {
-+	target_vproc = max(inter_vproc, vproc);
-+	if (pre_vproc <= target_vproc) {
- 		ret = mtk_cpufreq_set_voltage(info, target_vproc);
- 		if (ret) {
- 			dev_err(cpu_dev,
-@@ -417,6 +363,15 @@ static int mtk_cpu_dvfs_info_init(struct
- 	 */
- 	info->need_voltage_tracking = (info->sram_reg != NULL);
- 
-+	/*
-+	 * We assume min voltage is 0 and tracking target voltage using
-+	 * min_volt_shift for each iteration.
-+	 * The vtrack_max is 3 times of expeted iteration count.
-+	 */
-+	info->vtrack_max = 3 * DIV_ROUND_UP(max(info->soc_data->sram_max_volt,
-+						info->soc_data->proc_max_volt),
-+					    info->soc_data->min_volt_shift);
-+
- 	return 0;
- 
- out_disable_inter_clock:
diff --git a/target/linux/mediatek/patches-5.15/350-11-cpufreq-mediatek-Add-opp-notification-support.patch b/target/linux/mediatek/patches-5.15/350-11-cpufreq-mediatek-Add-opp-notification-support.patch
deleted file mode 100644
index 2cb99b907a6e2f..00000000000000
--- a/target/linux/mediatek/patches-5.15/350-11-cpufreq-mediatek-Add-opp-notification-support.patch
+++ /dev/null
@@ -1,184 +0,0 @@
-From 01be227eff7e5fc01f7c8de8f6daddd5fb17ddd1 Mon Sep 17 00:00:00 2001
-From: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Date: Thu, 5 May 2022 19:52:21 +0800
-Subject: [PATCH 11/21] cpufreq: mediatek: Add opp notification support
-
-From this opp notifier, cpufreq should listen to opp notification and do
-proper actions when receiving events of disable and voltage adjustment.
-
-One of the user for this opp notifier is MediaTek SVS.
-The MediaTek Smart Voltage Scaling (SVS) is a hardware which calculates
-suitable SVS bank voltages to OPP voltage table.
-
-Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
-Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-[ Viresh: Renamed opp_freq as current_freq and moved its initialization ]
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 90 +++++++++++++++++++++++++++---
- 1 file changed, 82 insertions(+), 8 deletions(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -46,6 +46,11 @@ struct mtk_cpu_dvfs_info {
- 	int intermediate_voltage;
- 	bool need_voltage_tracking;
- 	int pre_vproc;
-+	/* Avoid race condition for regulators between notify and policy */
-+	struct mutex reg_lock;
-+	struct notifier_block opp_nb;
-+	unsigned int opp_cpu;
-+	unsigned long current_freq;
- 	const struct mtk_cpufreq_platform_data *soc_data;
- 	int vtrack_max;
- };
-@@ -182,6 +187,8 @@ static int mtk_cpufreq_set_target(struct
- 
- 	pre_freq_hz = clk_get_rate(cpu_clk);
- 
-+	mutex_lock(&info->reg_lock);
-+
- 	if (unlikely(info->pre_vproc <= 0))
- 		pre_vproc = regulator_get_voltage(info->proc_reg);
- 	else
-@@ -214,7 +221,7 @@ static int mtk_cpufreq_set_target(struct
- 			dev_err(cpu_dev,
- 				"cpu%d: failed to scale up voltage!\n", policy->cpu);
- 			mtk_cpufreq_set_voltage(info, pre_vproc);
--			return ret;
-+			goto out;
- 		}
- 	}
- 
-@@ -224,8 +231,7 @@ static int mtk_cpufreq_set_target(struct
- 		dev_err(cpu_dev,
- 			"cpu%d: failed to re-parent cpu clock!\n", policy->cpu);
- 		mtk_cpufreq_set_voltage(info, pre_vproc);
--		WARN_ON(1);
--		return ret;
-+		goto out;
- 	}
- 
- 	/* Set the original PLL to target rate. */
-@@ -235,7 +241,7 @@ static int mtk_cpufreq_set_target(struct
- 			"cpu%d: failed to scale cpu clock rate!\n", policy->cpu);
- 		clk_set_parent(cpu_clk, armpll);
- 		mtk_cpufreq_set_voltage(info, pre_vproc);
--		return ret;
-+		goto out;
- 	}
- 
- 	/* Set parent of CPU clock back to the original PLL. */
-@@ -244,8 +250,7 @@ static int mtk_cpufreq_set_target(struct
- 		dev_err(cpu_dev,
- 			"cpu%d: failed to re-parent cpu clock!\n", policy->cpu);
- 		mtk_cpufreq_set_voltage(info, inter_vproc);
--		WARN_ON(1);
--		return ret;
-+		goto out;
- 	}
- 
- 	/*
-@@ -260,15 +265,72 @@ static int mtk_cpufreq_set_target(struct
- 			clk_set_parent(cpu_clk, info->inter_clk);
- 			clk_set_rate(armpll, pre_freq_hz);
- 			clk_set_parent(cpu_clk, armpll);
--			return ret;
-+			goto out;
- 		}
- 	}
- 
--	return 0;
-+	info->current_freq = freq_hz;
-+
-+out:
-+	mutex_unlock(&info->reg_lock);
-+
-+	return ret;
- }
- 
- #define DYNAMIC_POWER "dynamic-power-coefficient"
- 
-+static int mtk_cpufreq_opp_notifier(struct notifier_block *nb,
-+				    unsigned long event, void *data)
-+{
-+	struct dev_pm_opp *opp = data;
-+	struct dev_pm_opp *new_opp;
-+	struct mtk_cpu_dvfs_info *info;
-+	unsigned long freq, volt;
-+	struct cpufreq_policy *policy;
-+	int ret = 0;
-+
-+	info = container_of(nb, struct mtk_cpu_dvfs_info, opp_nb);
-+
-+	if (event == OPP_EVENT_ADJUST_VOLTAGE) {
-+		freq = dev_pm_opp_get_freq(opp);
-+
-+		mutex_lock(&info->reg_lock);
-+		if (info->current_freq == freq) {
-+			volt = dev_pm_opp_get_voltage(opp);
-+			ret = mtk_cpufreq_set_voltage(info, volt);
-+			if (ret)
-+				dev_err(info->cpu_dev,
-+					"failed to scale voltage: %d\n", ret);
-+		}
-+		mutex_unlock(&info->reg_lock);
-+	} else if (event == OPP_EVENT_DISABLE) {
-+		freq = dev_pm_opp_get_freq(opp);
-+
-+		/* case of current opp item is disabled */
-+		if (info->current_freq == freq) {
-+			freq = 1;
-+			new_opp = dev_pm_opp_find_freq_ceil(info->cpu_dev,
-+							    &freq);
-+			if (IS_ERR(new_opp)) {
-+				dev_err(info->cpu_dev,
-+					"all opp items are disabled\n");
-+				ret = PTR_ERR(new_opp);
-+				return notifier_from_errno(ret);
-+			}
-+
-+			dev_pm_opp_put(new_opp);
-+			policy = cpufreq_cpu_get(info->opp_cpu);
-+			if (policy) {
-+				cpufreq_driver_target(policy, freq / 1000,
-+						      CPUFREQ_RELATION_L);
-+				cpufreq_cpu_put(policy);
-+			}
-+		}
-+	}
-+
-+	return notifier_from_errno(ret);
-+}
-+
- static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
- {
- 	struct device *cpu_dev;
-@@ -357,6 +419,17 @@ static int mtk_cpu_dvfs_info_init(struct
- 	info->intermediate_voltage = dev_pm_opp_get_voltage(opp);
- 	dev_pm_opp_put(opp);
- 
-+	mutex_init(&info->reg_lock);
-+	info->current_freq = clk_get_rate(info->cpu_clk);
-+
-+	info->opp_cpu = cpu;
-+	info->opp_nb.notifier_call = mtk_cpufreq_opp_notifier;
-+	ret = dev_pm_opp_register_notifier(cpu_dev, &info->opp_nb);
-+	if (ret) {
-+		dev_err(cpu_dev, "cpu%d: failed to register opp notifier\n", cpu);
-+		goto out_disable_inter_clock;
-+	}
-+
- 	/*
- 	 * If SRAM regulator is present, software "voltage tracking" is needed
- 	 * for this CPU power domain.
-@@ -421,6 +494,7 @@ static void mtk_cpu_dvfs_info_release(st
- 	}
- 
- 	dev_pm_opp_of_cpumask_remove_table(&info->cpus);
-+	dev_pm_opp_unregister_notifier(info->cpu_dev, &info->opp_nb);
- }
- 
- static int mtk_cpufreq_init(struct cpufreq_policy *policy)
diff --git a/target/linux/mediatek/patches-5.15/350-12-cpufreq-mediatek-Fix-potential-deadlock-problem-in-m.patch b/target/linux/mediatek/patches-5.15/350-12-cpufreq-mediatek-Fix-potential-deadlock-problem-in-m.patch
deleted file mode 100644
index 76bd795c004afb..00000000000000
--- a/target/linux/mediatek/patches-5.15/350-12-cpufreq-mediatek-Fix-potential-deadlock-problem-in-m.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From 6a1bd7cf4ed7a1948f564aaf16d34b7352c0029b Mon Sep 17 00:00:00 2001
-From: Wan Jiabing <wanjiabing@vivo.com>
-Date: Tue, 10 May 2022 17:05:31 +0800
-Subject: [PATCH 12/21] cpufreq: mediatek: Fix potential deadlock problem in
- mtk_cpufreq_set_target
-
-Fix following coccichek error:
-./drivers/cpufreq/mediatek-cpufreq.c:199:2-8: preceding lock on line
-./drivers/cpufreq/mediatek-cpufreq.c:208:2-8: preceding lock on line
-
-mutex_lock is acquired but not released before return.
-Use 'goto out' to help releasing the mutex_lock.
-
-Fixes: c210063b40ac ("cpufreq: mediatek: Add opp notification support")
-Signed-off-by: Wan Jiabing <wanjiabing@vivo.com>
-Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 6 ++++--
- 1 file changed, 4 insertions(+), 2 deletions(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -196,7 +196,8 @@ static int mtk_cpufreq_set_target(struct
- 
- 	if (pre_vproc < 0) {
- 		dev_err(cpu_dev, "invalid Vproc value: %d\n", pre_vproc);
--		return pre_vproc;
-+		ret = pre_vproc;
-+		goto out;
- 	}
- 
- 	freq_hz = freq_table[index].frequency * 1000;
-@@ -205,7 +206,8 @@ static int mtk_cpufreq_set_target(struct
- 	if (IS_ERR(opp)) {
- 		dev_err(cpu_dev, "cpu%d: failed to find OPP for %ld\n",
- 			policy->cpu, freq_hz);
--		return PTR_ERR(opp);
-+		ret = PTR_ERR(opp);
-+		goto out;
- 	}
- 	vproc = dev_pm_opp_get_voltage(opp);
- 	dev_pm_opp_put(opp);
diff --git a/target/linux/mediatek/patches-5.15/350-13-cpufreq-mediatek-Link-CCI-device-to-CPU.patch b/target/linux/mediatek/patches-5.15/350-13-cpufreq-mediatek-Link-CCI-device-to-CPU.patch
deleted file mode 100644
index eeaa466c326d07..00000000000000
--- a/target/linux/mediatek/patches-5.15/350-13-cpufreq-mediatek-Link-CCI-device-to-CPU.patch
+++ /dev/null
@@ -1,188 +0,0 @@
-From 15aaf74fb734a3e69b10d00b97b322711b81e222 Mon Sep 17 00:00:00 2001
-From: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Date: Thu, 5 May 2022 19:52:22 +0800
-Subject: [PATCH 13/21] cpufreq: mediatek: Link CCI device to CPU
-
-In some MediaTek SoCs, like MT8183, CPU and CCI share the same power
-supplies. Cpufreq needs to check if CCI devfreq exists and wait until
-CCI devfreq ready before scaling frequency.
-
-Before CCI devfreq is ready, we record the voltage when booting to
-kernel and use the max(cpu target voltage, booting voltage) to
-prevent cpufreq adjust to the lower voltage which will cause the CCI
-crash because of high frequency and low voltage.
-
-- Add is_ccifreq_ready() to link CCI device to CPI, and CPU will start
-  DVFS when CCI is ready.
-- Add platform data for MT8183.
-
-Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Kevin Hilman <khilman@baylibre.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 82 +++++++++++++++++++++++++++++-
- 1 file changed, 81 insertions(+), 1 deletion(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -22,6 +22,7 @@ struct mtk_cpufreq_platform_data {
- 	int proc_max_volt;
- 	int sram_min_volt;
- 	int sram_max_volt;
-+	bool ccifreq_supported;
- };
- 
- /*
-@@ -38,6 +39,7 @@ struct mtk_cpufreq_platform_data {
- struct mtk_cpu_dvfs_info {
- 	struct cpumask cpus;
- 	struct device *cpu_dev;
-+	struct device *cci_dev;
- 	struct regulator *proc_reg;
- 	struct regulator *sram_reg;
- 	struct clk *cpu_clk;
-@@ -45,6 +47,7 @@ struct mtk_cpu_dvfs_info {
- 	struct list_head list_head;
- 	int intermediate_voltage;
- 	bool need_voltage_tracking;
-+	int vproc_on_boot;
- 	int pre_vproc;
- 	/* Avoid race condition for regulators between notify and policy */
- 	struct mutex reg_lock;
-@@ -53,6 +56,7 @@ struct mtk_cpu_dvfs_info {
- 	unsigned long current_freq;
- 	const struct mtk_cpufreq_platform_data *soc_data;
- 	int vtrack_max;
-+	bool ccifreq_bound;
- };
- 
- static struct platform_device *cpufreq_pdev;
-@@ -171,6 +175,28 @@ static int mtk_cpufreq_set_voltage(struc
- 	return ret;
- }
- 
-+static bool is_ccifreq_ready(struct mtk_cpu_dvfs_info *info)
-+{
-+	struct device_link *sup_link;
-+
-+	if (info->ccifreq_bound)
-+		return true;
-+
-+	sup_link = device_link_add(info->cpu_dev, info->cci_dev,
-+				   DL_FLAG_AUTOREMOVE_CONSUMER);
-+	if (!sup_link) {
-+		dev_err(info->cpu_dev, "cpu%d: sup_link is NULL\n", info->opp_cpu);
-+		return false;
-+	}
-+
-+	if (sup_link->supplier->links.status != DL_DEV_DRIVER_BOUND)
-+		return false;
-+
-+	info->ccifreq_bound = true;
-+
-+	return true;
-+}
-+
- static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
- 				  unsigned int index)
- {
-@@ -213,6 +239,14 @@ static int mtk_cpufreq_set_target(struct
- 	dev_pm_opp_put(opp);
- 
- 	/*
-+	 * If MediaTek cci is supported but is not ready, we will use the value
-+	 * of max(target cpu voltage, booting voltage) to prevent high freqeuncy
-+	 * low voltage crash.
-+	 */
-+	if (info->soc_data->ccifreq_supported && !is_ccifreq_ready(info))
-+		vproc = max(vproc, info->vproc_on_boot);
-+
-+	/*
- 	 * If the new voltage or the intermediate voltage is higher than the
- 	 * current voltage, scale up voltage first.
- 	 */
-@@ -333,6 +367,23 @@ static int mtk_cpufreq_opp_notifier(stru
- 	return notifier_from_errno(ret);
- }
- 
-+static struct device *of_get_cci(struct device *cpu_dev)
-+{
-+	struct device_node *np;
-+	struct platform_device *pdev;
-+
-+	np = of_parse_phandle(cpu_dev->of_node, "mediatek,cci", 0);
-+	if (IS_ERR_OR_NULL(np))
-+		return NULL;
-+
-+	pdev = of_find_device_by_node(np);
-+	of_node_put(np);
-+	if (IS_ERR_OR_NULL(pdev))
-+		return NULL;
-+
-+	return &pdev->dev;
-+}
-+
- static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
- {
- 	struct device *cpu_dev;
-@@ -347,6 +398,16 @@ static int mtk_cpu_dvfs_info_init(struct
- 	}
- 	info->cpu_dev = cpu_dev;
- 
-+	info->ccifreq_bound = false;
-+	if (info->soc_data->ccifreq_supported) {
-+		info->cci_dev = of_get_cci(info->cpu_dev);
-+		if (IS_ERR_OR_NULL(info->cci_dev)) {
-+			ret = PTR_ERR(info->cci_dev);
-+			dev_err(cpu_dev, "cpu%d: failed to get cci device\n", cpu);
-+			return -ENODEV;
-+		}
-+	}
-+
- 	info->cpu_clk = clk_get(cpu_dev, "cpu");
- 	if (IS_ERR(info->cpu_clk)) {
- 		ret = PTR_ERR(info->cpu_clk);
-@@ -410,6 +471,15 @@ static int mtk_cpu_dvfs_info_init(struct
- 	if (ret)
- 		goto out_disable_mux_clock;
- 
-+	if (info->soc_data->ccifreq_supported) {
-+		info->vproc_on_boot = regulator_get_voltage(info->proc_reg);
-+		if (info->vproc_on_boot < 0) {
-+			dev_err(info->cpu_dev,
-+				"invalid Vproc value: %d\n", info->vproc_on_boot);
-+			goto out_disable_inter_clock;
-+		}
-+	}
-+
- 	/* Search a safe voltage for intermediate frequency. */
- 	rate = clk_get_rate(info->inter_clk);
- 	opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
-@@ -617,6 +687,16 @@ static const struct mtk_cpufreq_platform
- 	.proc_max_volt = 1150000,
- 	.sram_min_volt = 0,
- 	.sram_max_volt = 1150000,
-+	.ccifreq_supported = false,
-+};
-+
-+static const struct mtk_cpufreq_platform_data mt8183_platform_data = {
-+	.min_volt_shift = 100000,
-+	.max_volt_shift = 200000,
-+	.proc_max_volt = 1150000,
-+	.sram_min_volt = 0,
-+	.sram_max_volt = 1150000,
-+	.ccifreq_supported = true,
- };
- 
- /* List of machines supported by this driver */
-@@ -629,7 +709,7 @@ static const struct of_device_id mtk_cpu
- 	{ .compatible = "mediatek,mt817x", .data = &mt2701_platform_data },
- 	{ .compatible = "mediatek,mt8173", .data = &mt2701_platform_data },
- 	{ .compatible = "mediatek,mt8176", .data = &mt2701_platform_data },
--	{ .compatible = "mediatek,mt8183", .data = &mt2701_platform_data },
-+	{ .compatible = "mediatek,mt8183", .data = &mt8183_platform_data },
- 	{ .compatible = "mediatek,mt8365", .data = &mt2701_platform_data },
- 	{ .compatible = "mediatek,mt8516", .data = &mt2701_platform_data },
- 	{ }
diff --git a/target/linux/mediatek/patches-5.15/350-14-cpufreq-mediatek-Add-support-for-MT8186.patch b/target/linux/mediatek/patches-5.15/350-14-cpufreq-mediatek-Add-support-for-MT8186.patch
deleted file mode 100644
index 31000cfbe058fa..00000000000000
--- a/target/linux/mediatek/patches-5.15/350-14-cpufreq-mediatek-Add-support-for-MT8186.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From b6be0baa6615afc65c3963adab674e36af1d4d5f Mon Sep 17 00:00:00 2001
-From: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Date: Thu, 5 May 2022 19:52:23 +0800
-Subject: [PATCH 14/21] cpufreq: mediatek: Add support for MT8186
-
-The platform data of MT8186 is different from previous MediaTek SoCs,
-so we add a new compatible and platform data for it.
-
-Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -699,6 +699,15 @@ static const struct mtk_cpufreq_platform
- 	.ccifreq_supported = true,
- };
- 
-+static const struct mtk_cpufreq_platform_data mt8186_platform_data = {
-+	.min_volt_shift = 100000,
-+	.max_volt_shift = 250000,
-+	.proc_max_volt = 1118750,
-+	.sram_min_volt = 850000,
-+	.sram_max_volt = 1118750,
-+	.ccifreq_supported = true,
-+};
-+
- /* List of machines supported by this driver */
- static const struct of_device_id mtk_cpufreq_machines[] __initconst = {
- 	{ .compatible = "mediatek,mt2701", .data = &mt2701_platform_data },
-@@ -710,6 +719,7 @@ static const struct of_device_id mtk_cpu
- 	{ .compatible = "mediatek,mt8173", .data = &mt2701_platform_data },
- 	{ .compatible = "mediatek,mt8176", .data = &mt2701_platform_data },
- 	{ .compatible = "mediatek,mt8183", .data = &mt8183_platform_data },
-+	{ .compatible = "mediatek,mt8186", .data = &mt8186_platform_data },
- 	{ .compatible = "mediatek,mt8365", .data = &mt2701_platform_data },
- 	{ .compatible = "mediatek,mt8516", .data = &mt2701_platform_data },
- 	{ }
diff --git a/target/linux/mediatek/patches-5.15/350-15-cpufreq-mediatek-Handle-sram-regulator-probe-deferra.patch b/target/linux/mediatek/patches-5.15/350-15-cpufreq-mediatek-Handle-sram-regulator-probe-deferra.patch
deleted file mode 100644
index c0137894c93413..00000000000000
--- a/target/linux/mediatek/patches-5.15/350-15-cpufreq-mediatek-Handle-sram-regulator-probe-deferra.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From 75d19b24aa3203d6c78e4c431c2cc07157ce12fe Mon Sep 17 00:00:00 2001
-From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Date: Wed, 13 Jul 2022 13:15:36 +0200
-Subject: [PATCH 15/21] cpufreq: mediatek: Handle sram regulator probe deferral
-
-If the regulator_get_optional() call for the SRAM regulator returns
-a probe deferral, we must bail out and retry probing later: failing
-to do this will produce unstabilities on platforms requiring the
-handling for this regulator.
-
-Fixes: ffa7bdf7f344 ("cpufreq: mediatek: Make sram regulator optional")
-Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 8 ++++++--
- 1 file changed, 6 insertions(+), 2 deletions(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -439,9 +439,13 @@ static int mtk_cpu_dvfs_info_init(struct
- 
- 	/* Both presence and absence of sram regulator are valid cases. */
- 	info->sram_reg = regulator_get_optional(cpu_dev, "sram");
--	if (IS_ERR(info->sram_reg))
-+	if (IS_ERR(info->sram_reg)) {
-+		ret = PTR_ERR(info->sram_reg);
-+		if (ret == -EPROBE_DEFER)
-+			goto out_free_resources;
-+
- 		info->sram_reg = NULL;
--	else {
-+	} else {
- 		ret = regulator_enable(info->sram_reg);
- 		if (ret) {
- 			dev_warn(cpu_dev, "cpu%d: failed to enable vsram\n", cpu);
diff --git a/target/linux/mediatek/patches-5.15/350-16-cpufreq-mediatek-fix-error-return-code-in-mtk_cpu_dv.patch b/target/linux/mediatek/patches-5.15/350-16-cpufreq-mediatek-fix-error-return-code-in-mtk_cpu_dv.patch
deleted file mode 100644
index 45c4477ff1ab1f..00000000000000
--- a/target/linux/mediatek/patches-5.15/350-16-cpufreq-mediatek-fix-error-return-code-in-mtk_cpu_dv.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From dd1174c21dacacd6c0129c1dabc5decad35c02c2 Mon Sep 17 00:00:00 2001
-From: Yang Yingliang <yangyingliang@huawei.com>
-Date: Tue, 17 May 2022 21:34:50 +0800
-Subject: [PATCH 16/21] cpufreq: mediatek: fix error return code in
- mtk_cpu_dvfs_info_init()
-
-If regulator_get_voltage() fails, it should return the error code in
-mtk_cpu_dvfs_info_init().
-
-Fixes: 0daa47325bae ("cpufreq: mediatek: Link CCI device to CPU")
-Reported-by: Hulk Robot <hulkci@huawei.com>
-Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -478,6 +478,7 @@ static int mtk_cpu_dvfs_info_init(struct
- 	if (info->soc_data->ccifreq_supported) {
- 		info->vproc_on_boot = regulator_get_voltage(info->proc_reg);
- 		if (info->vproc_on_boot < 0) {
-+			ret = info->vproc_on_boot;
- 			dev_err(info->cpu_dev,
- 				"invalid Vproc value: %d\n", info->vproc_on_boot);
- 			goto out_disable_inter_clock;
diff --git a/target/linux/mediatek/patches-5.15/350-17-cpufreq-mediatek-fix-passing-zero-to-PTR_ERR.patch b/target/linux/mediatek/patches-5.15/350-17-cpufreq-mediatek-fix-passing-zero-to-PTR_ERR.patch
deleted file mode 100644
index 557d02b822b3a9..00000000000000
--- a/target/linux/mediatek/patches-5.15/350-17-cpufreq-mediatek-fix-passing-zero-to-PTR_ERR.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From 230a74d459244411db91bfd678f17fcf7aedfcd0 Mon Sep 17 00:00:00 2001
-From: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Date: Fri, 24 Mar 2023 18:11:27 +0800
-Subject: [PATCH 17/21] cpufreq: mediatek: fix passing zero to 'PTR_ERR'
-
-In order to prevent passing zero to 'PTR_ERR' in
-mtk_cpu_dvfs_info_init(), we fix the return value of of_get_cci() using
-error pointer by explicitly casting error number.
-
-Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Fixes: 0daa47325bae ("cpufreq: mediatek: Link CCI device to CPU")
-Reported-by: Dan Carpenter <error27@gmail.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 10 +++++-----
- 1 file changed, 5 insertions(+), 5 deletions(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -373,13 +373,13 @@ static struct device *of_get_cci(struct
- 	struct platform_device *pdev;
- 
- 	np = of_parse_phandle(cpu_dev->of_node, "mediatek,cci", 0);
--	if (IS_ERR_OR_NULL(np))
--		return NULL;
-+	if (!np)
-+		return ERR_PTR(-ENODEV);
- 
- 	pdev = of_find_device_by_node(np);
- 	of_node_put(np);
--	if (IS_ERR_OR_NULL(pdev))
--		return NULL;
-+	if (!pdev)
-+		return ERR_PTR(-ENODEV);
- 
- 	return &pdev->dev;
- }
-@@ -401,7 +401,7 @@ static int mtk_cpu_dvfs_info_init(struct
- 	info->ccifreq_bound = false;
- 	if (info->soc_data->ccifreq_supported) {
- 		info->cci_dev = of_get_cci(info->cpu_dev);
--		if (IS_ERR_OR_NULL(info->cci_dev)) {
-+		if (IS_ERR(info->cci_dev)) {
- 			ret = PTR_ERR(info->cci_dev);
- 			dev_err(cpu_dev, "cpu%d: failed to get cci device\n", cpu);
- 			return -ENODEV;
diff --git a/target/linux/mediatek/patches-5.15/350-18-cpufreq-mediatek-fix-KP-caused-by-handler-usage-afte.patch b/target/linux/mediatek/patches-5.15/350-18-cpufreq-mediatek-fix-KP-caused-by-handler-usage-afte.patch
deleted file mode 100644
index 61531d38ad2910..00000000000000
--- a/target/linux/mediatek/patches-5.15/350-18-cpufreq-mediatek-fix-KP-caused-by-handler-usage-afte.patch
+++ /dev/null
@@ -1,149 +0,0 @@
-From fced531b7c7e18192e7982637c8e8f20c29aad64 Mon Sep 17 00:00:00 2001
-From: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Date: Fri, 24 Mar 2023 18:11:28 +0800
-Subject: [PATCH 18/21] cpufreq: mediatek: fix KP caused by handler usage after
- regulator_put/clk_put
-
-Any kind of failure in mtk_cpu_dvfs_info_init() will lead to calling
-regulator_put() or clk_put() and the KP will occur since the regulator/clk
-handlers are used after released in mtk_cpu_dvfs_info_release().
-
-To prevent the usage after regulator_put()/clk_put(), the regulator/clk
-handlers are addressed in a way of "Free the Last Thing Style".
-
-Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Fixes: 4b9ceb757bbb ("cpufreq: mediatek: Enable clocks and regulators")
-Suggested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Suggested-by: Dan Carpenter <error27@gmail.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 62 +++++++++++++++---------------
- 1 file changed, 30 insertions(+), 32 deletions(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -420,7 +420,7 @@ static int mtk_cpu_dvfs_info_init(struct
- 		ret = PTR_ERR(info->inter_clk);
- 		dev_err_probe(cpu_dev, ret,
- 			      "cpu%d: failed to get intermediate clk\n", cpu);
--		goto out_free_resources;
-+		goto out_free_mux_clock;
- 	}
- 
- 	info->proc_reg = regulator_get_optional(cpu_dev, "proc");
-@@ -428,13 +428,13 @@ static int mtk_cpu_dvfs_info_init(struct
- 		ret = PTR_ERR(info->proc_reg);
- 		dev_err_probe(cpu_dev, ret,
- 			      "cpu%d: failed to get proc regulator\n", cpu);
--		goto out_free_resources;
-+		goto out_free_inter_clock;
- 	}
- 
- 	ret = regulator_enable(info->proc_reg);
- 	if (ret) {
- 		dev_warn(cpu_dev, "cpu%d: failed to enable vproc\n", cpu);
--		goto out_free_resources;
-+		goto out_free_proc_reg;
- 	}
- 
- 	/* Both presence and absence of sram regulator are valid cases. */
-@@ -442,14 +442,14 @@ static int mtk_cpu_dvfs_info_init(struct
- 	if (IS_ERR(info->sram_reg)) {
- 		ret = PTR_ERR(info->sram_reg);
- 		if (ret == -EPROBE_DEFER)
--			goto out_free_resources;
-+			goto out_disable_proc_reg;
- 
- 		info->sram_reg = NULL;
- 	} else {
- 		ret = regulator_enable(info->sram_reg);
- 		if (ret) {
- 			dev_warn(cpu_dev, "cpu%d: failed to enable vsram\n", cpu);
--			goto out_free_resources;
-+			goto out_free_sram_reg;
- 		}
- 	}
- 
-@@ -458,13 +458,13 @@ static int mtk_cpu_dvfs_info_init(struct
- 	if (ret) {
- 		dev_err(cpu_dev,
- 			"cpu%d: failed to get OPP-sharing information\n", cpu);
--		goto out_free_resources;
-+		goto out_disable_sram_reg;
- 	}
- 
- 	ret = dev_pm_opp_of_cpumask_add_table(&info->cpus);
- 	if (ret) {
- 		dev_warn(cpu_dev, "cpu%d: no OPP table\n", cpu);
--		goto out_free_resources;
-+		goto out_disable_sram_reg;
- 	}
- 
- 	ret = clk_prepare_enable(info->cpu_clk);
-@@ -533,43 +533,41 @@ out_disable_mux_clock:
- out_free_opp_table:
- 	dev_pm_opp_of_cpumask_remove_table(&info->cpus);
- 
--out_free_resources:
--	if (regulator_is_enabled(info->proc_reg))
--		regulator_disable(info->proc_reg);
--	if (info->sram_reg && regulator_is_enabled(info->sram_reg))
-+out_disable_sram_reg:
-+	if (info->sram_reg)
- 		regulator_disable(info->sram_reg);
- 
--	if (!IS_ERR(info->proc_reg))
--		regulator_put(info->proc_reg);
--	if (!IS_ERR(info->sram_reg))
-+out_free_sram_reg:
-+	if (info->sram_reg)
- 		regulator_put(info->sram_reg);
--	if (!IS_ERR(info->cpu_clk))
--		clk_put(info->cpu_clk);
--	if (!IS_ERR(info->inter_clk))
--		clk_put(info->inter_clk);
-+
-+out_disable_proc_reg:
-+	regulator_disable(info->proc_reg);
-+
-+out_free_proc_reg:
-+	regulator_put(info->proc_reg);
-+
-+out_free_inter_clock:
-+	clk_put(info->inter_clk);
-+
-+out_free_mux_clock:
-+	clk_put(info->cpu_clk);
- 
- 	return ret;
- }
- 
- static void mtk_cpu_dvfs_info_release(struct mtk_cpu_dvfs_info *info)
- {
--	if (!IS_ERR(info->proc_reg)) {
--		regulator_disable(info->proc_reg);
--		regulator_put(info->proc_reg);
--	}
--	if (!IS_ERR(info->sram_reg)) {
-+	regulator_disable(info->proc_reg);
-+	regulator_put(info->proc_reg);
-+	if (info->sram_reg) {
- 		regulator_disable(info->sram_reg);
- 		regulator_put(info->sram_reg);
- 	}
--	if (!IS_ERR(info->cpu_clk)) {
--		clk_disable_unprepare(info->cpu_clk);
--		clk_put(info->cpu_clk);
--	}
--	if (!IS_ERR(info->inter_clk)) {
--		clk_disable_unprepare(info->inter_clk);
--		clk_put(info->inter_clk);
--	}
--
-+	clk_disable_unprepare(info->cpu_clk);
-+	clk_put(info->cpu_clk);
-+	clk_disable_unprepare(info->inter_clk);
-+	clk_put(info->inter_clk);
- 	dev_pm_opp_of_cpumask_remove_table(&info->cpus);
- 	dev_pm_opp_unregister_notifier(info->cpu_dev, &info->opp_nb);
- }
diff --git a/target/linux/mediatek/patches-5.15/350-19-cpufreq-mediatek-raise-proc-sram-max-voltage-for-MT8.patch b/target/linux/mediatek/patches-5.15/350-19-cpufreq-mediatek-raise-proc-sram-max-voltage-for-MT8.patch
deleted file mode 100644
index 2b7d229f1c5d47..00000000000000
--- a/target/linux/mediatek/patches-5.15/350-19-cpufreq-mediatek-raise-proc-sram-max-voltage-for-MT8.patch
+++ /dev/null
@@ -1,55 +0,0 @@
-From 24bc42a2d44cb821818717a5c607270921ec5d20 Mon Sep 17 00:00:00 2001
-From: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Date: Fri, 24 Mar 2023 18:11:29 +0800
-Subject: [PATCH 19/21] cpufreq: mediatek: raise proc/sram max voltage for
- MT8516
-
-Since the upper boundary of proc/sram voltage of MT8516 is 1300 mV,
-which is greater than the value of MT2701 1150 mV, we fix it by adding
-the corresponding platform data and specify proc/sram_max_volt to
-support MT8516.
-
-Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Fixes: ead858bd128d ("cpufreq: mediatek: Move voltage limits to platform data")
-Fixes: 6a17b3876bc8 ("cpufreq: mediatek: Refine mtk_cpufreq_voltage_tracking()")
-Reported-by: Nick Hainke <vincent@systemli.org>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 13 +++++++++++--
- 1 file changed, 11 insertions(+), 2 deletions(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -711,20 +711,29 @@ static const struct mtk_cpufreq_platform
- 	.ccifreq_supported = true,
- };
- 
-+static const struct mtk_cpufreq_platform_data mt8516_platform_data = {
-+	.min_volt_shift = 100000,
-+	.max_volt_shift = 200000,
-+	.proc_max_volt = 1310000,
-+	.sram_min_volt = 0,
-+	.sram_max_volt = 1310000,
-+	.ccifreq_supported = false,
-+};
-+
- /* List of machines supported by this driver */
- static const struct of_device_id mtk_cpufreq_machines[] __initconst = {
- 	{ .compatible = "mediatek,mt2701", .data = &mt2701_platform_data },
- 	{ .compatible = "mediatek,mt2712", .data = &mt2701_platform_data },
- 	{ .compatible = "mediatek,mt7622", .data = &mt2701_platform_data },
- 	{ .compatible = "mediatek,mt7623", .data = &mt2701_platform_data },
--	{ .compatible = "mediatek,mt8167", .data = &mt2701_platform_data },
-+	{ .compatible = "mediatek,mt8167", .data = &mt8516_platform_data },
- 	{ .compatible = "mediatek,mt817x", .data = &mt2701_platform_data },
- 	{ .compatible = "mediatek,mt8173", .data = &mt2701_platform_data },
- 	{ .compatible = "mediatek,mt8176", .data = &mt2701_platform_data },
- 	{ .compatible = "mediatek,mt8183", .data = &mt8183_platform_data },
- 	{ .compatible = "mediatek,mt8186", .data = &mt8186_platform_data },
- 	{ .compatible = "mediatek,mt8365", .data = &mt2701_platform_data },
--	{ .compatible = "mediatek,mt8516", .data = &mt2701_platform_data },
-+	{ .compatible = "mediatek,mt8516", .data = &mt8516_platform_data },
- 	{ }
- };
- MODULE_DEVICE_TABLE(of, mtk_cpufreq_machines);
diff --git a/target/linux/mediatek/patches-5.15/350-20-cpufreq-mediatek-Raise-proc-and-sram-max-voltage-for.patch b/target/linux/mediatek/patches-5.15/350-20-cpufreq-mediatek-Raise-proc-and-sram-max-voltage-for.patch
deleted file mode 100644
index 2de8eb6394ca2d..00000000000000
--- a/target/linux/mediatek/patches-5.15/350-20-cpufreq-mediatek-Raise-proc-and-sram-max-voltage-for.patch
+++ /dev/null
@@ -1,58 +0,0 @@
-From fe6ef09358dc0cfead9d383a8676fbe7a40fcef7 Mon Sep 17 00:00:00 2001
-From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Date: Fri, 24 Mar 2023 18:11:30 +0800
-Subject: [PATCH 20/21] cpufreq: mediatek: Raise proc and sram max voltage for
- MT7622/7623
-
-During the addition of SRAM voltage tracking for CCI scaling, this
-driver got some voltage limits set for the vtrack algorithm: these
-were moved to platform data first, then enforced in a later commit
-6a17b3876bc8 ("cpufreq: mediatek: Refine mtk_cpufreq_voltage_tracking()")
-using these as max values for the regulator_set_voltage() calls.
-
-In this case, the vsram/vproc constraints for MT7622 and MT7623
-were supposed to be the same as MT2701 (and a number of other SoCs),
-but that turned out to be a mistake because the aforementioned two
-SoCs' maximum voltage for both VPROC and VPROC_SRAM is 1.36V.
-
-Fix that by adding new platform data for MT7622/7623 declaring the
-right {proc,sram}_max_volt parameter.
-
-Fixes: ead858bd128d ("cpufreq: mediatek: Move voltage limits to platform data")
-Fixes: 6a17b3876bc8 ("cpufreq: mediatek: Refine mtk_cpufreq_voltage_tracking()")
-Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 13 +++++++++++--
- 1 file changed, 11 insertions(+), 2 deletions(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -693,6 +693,15 @@ static const struct mtk_cpufreq_platform
- 	.ccifreq_supported = false,
- };
- 
-+static const struct mtk_cpufreq_platform_data mt7622_platform_data = {
-+	.min_volt_shift = 100000,
-+	.max_volt_shift = 200000,
-+	.proc_max_volt = 1360000,
-+	.sram_min_volt = 0,
-+	.sram_max_volt = 1360000,
-+	.ccifreq_supported = false,
-+};
-+
- static const struct mtk_cpufreq_platform_data mt8183_platform_data = {
- 	.min_volt_shift = 100000,
- 	.max_volt_shift = 200000,
-@@ -724,8 +733,8 @@ static const struct mtk_cpufreq_platform
- static const struct of_device_id mtk_cpufreq_machines[] __initconst = {
- 	{ .compatible = "mediatek,mt2701", .data = &mt2701_platform_data },
- 	{ .compatible = "mediatek,mt2712", .data = &mt2701_platform_data },
--	{ .compatible = "mediatek,mt7622", .data = &mt2701_platform_data },
--	{ .compatible = "mediatek,mt7623", .data = &mt2701_platform_data },
-+	{ .compatible = "mediatek,mt7622", .data = &mt7622_platform_data },
-+	{ .compatible = "mediatek,mt7623", .data = &mt7622_platform_data },
- 	{ .compatible = "mediatek,mt8167", .data = &mt8516_platform_data },
- 	{ .compatible = "mediatek,mt817x", .data = &mt2701_platform_data },
- 	{ .compatible = "mediatek,mt8173", .data = &mt2701_platform_data },
diff --git a/target/linux/mediatek/patches-5.15/350-21-cpufreq-mediatek-Add-support-for-MT7988.patch b/target/linux/mediatek/patches-5.15/350-21-cpufreq-mediatek-Add-support-for-MT7988.patch
deleted file mode 100644
index 6acd3d607fbb3b..00000000000000
--- a/target/linux/mediatek/patches-5.15/350-21-cpufreq-mediatek-Add-support-for-MT7988.patch
+++ /dev/null
@@ -1,41 +0,0 @@
-From 4983a1517e7ddbc6f53fc07607e4ebeb51412843 Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Tue, 28 Feb 2023 19:59:22 +0800
-Subject: [PATCH 21/21] cpufreq: mediatek: Add support for MT7988
-
-This add cpufreq support for mediatek MT7988 SoC.
-
-The platform data of MT7988 is different from previous MediaTek SoCs,
-so we add a new compatible and platform data for it.
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
----
- drivers/cpufreq/mediatek-cpufreq.c | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -702,6 +702,15 @@ static const struct mtk_cpufreq_platform
- 	.ccifreq_supported = false,
- };
- 
-+static const struct mtk_cpufreq_platform_data mt7988_platform_data = {
-+	.min_volt_shift = 100000,
-+	.max_volt_shift = 200000,
-+	.proc_max_volt = 900000,
-+	.sram_min_volt = 0,
-+	.sram_max_volt = 1150000,
-+	.ccifreq_supported = true,
-+};
-+
- static const struct mtk_cpufreq_platform_data mt8183_platform_data = {
- 	.min_volt_shift = 100000,
- 	.max_volt_shift = 200000,
-@@ -735,6 +744,7 @@ static const struct of_device_id mtk_cpu
- 	{ .compatible = "mediatek,mt2712", .data = &mt2701_platform_data },
- 	{ .compatible = "mediatek,mt7622", .data = &mt7622_platform_data },
- 	{ .compatible = "mediatek,mt7623", .data = &mt7622_platform_data },
-+	{ .compatible = "mediatek,mt7988", .data = &mt7988_platform_data },
- 	{ .compatible = "mediatek,mt8167", .data = &mt8516_platform_data },
- 	{ .compatible = "mediatek,mt817x", .data = &mt2701_platform_data },
- 	{ .compatible = "mediatek,mt8173", .data = &mt2701_platform_data },
diff --git a/target/linux/mediatek/patches-5.15/351-cpufreq-mediatek-correct-voltages-for-MT7622-and-MT7.patch b/target/linux/mediatek/patches-5.15/351-cpufreq-mediatek-correct-voltages-for-MT7622-and-MT7.patch
deleted file mode 100644
index 6ab05b897c3e39..00000000000000
--- a/target/linux/mediatek/patches-5.15/351-cpufreq-mediatek-correct-voltages-for-MT7622-and-MT7.patch
+++ /dev/null
@@ -1,53 +0,0 @@
-From e7697814c142c99f470c3458d49e41b25a575f23 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Fri, 26 May 2023 10:31:40 +0100
-Subject: [PATCH] cpufreq: mediatek: correct voltages for MT7622 and MT7623
-
-The MT6380 regulator typically used together with MT7622 does not
-support the current maximum processor and SRAM voltage in the cpufreq
-driver (1360000uV).
-For MT7622 limit processor and SRAM supply voltages to 1350000uV to
-avoid having the tracking algorithm request unsupported voltages from
-the regulator.
-
-On MT7623 there is no separate SRAM supply and the maximum voltage used
-is 1300000uV. Create dedicated platform data for MT7623 to cover that
-case as well.
-
-Fixes: 0883426fd07e3 ("cpufreq: mediatek: Raise proc and sram max voltage for MT7622/7623")
-Suggested-by: Jia-wei Chang <Jia-wei.Chang@mediatek.com>
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 13 ++++++++++---
- 1 file changed, 10 insertions(+), 3 deletions(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -696,9 +696,16 @@ static const struct mtk_cpufreq_platform
- static const struct mtk_cpufreq_platform_data mt7622_platform_data = {
- 	.min_volt_shift = 100000,
- 	.max_volt_shift = 200000,
--	.proc_max_volt = 1360000,
-+	.proc_max_volt = 1350000,
- 	.sram_min_volt = 0,
--	.sram_max_volt = 1360000,
-+	.sram_max_volt = 1350000,
-+	.ccifreq_supported = false,
-+};
-+
-+static const struct mtk_cpufreq_platform_data mt7623_platform_data = {
-+	.min_volt_shift = 100000,
-+	.max_volt_shift = 200000,
-+	.proc_max_volt = 1300000,
- 	.ccifreq_supported = false,
- };
- 
-@@ -743,7 +750,7 @@ static const struct of_device_id mtk_cpu
- 	{ .compatible = "mediatek,mt2701", .data = &mt2701_platform_data },
- 	{ .compatible = "mediatek,mt2712", .data = &mt2701_platform_data },
- 	{ .compatible = "mediatek,mt7622", .data = &mt7622_platform_data },
--	{ .compatible = "mediatek,mt7623", .data = &mt7622_platform_data },
-+	{ .compatible = "mediatek,mt7623", .data = &mt7623_platform_data },
- 	{ .compatible = "mediatek,mt7988", .data = &mt7988_platform_data },
- 	{ .compatible = "mediatek,mt8167", .data = &mt8516_platform_data },
- 	{ .compatible = "mediatek,mt817x", .data = &mt2701_platform_data },
diff --git a/target/linux/mediatek/patches-5.15/400-crypto-add-eip97-inside-secure-support.patch b/target/linux/mediatek/patches-5.15/400-crypto-add-eip97-inside-secure-support.patch
deleted file mode 100644
index 25ca9485e41bd9..00000000000000
--- a/target/linux/mediatek/patches-5.15/400-crypto-add-eip97-inside-secure-support.patch
+++ /dev/null
@@ -1,27 +0,0 @@
---- a/drivers/crypto/inside-secure/safexcel.c
-+++ b/drivers/crypto/inside-secure/safexcel.c
-@@ -600,6 +600,14 @@ static int safexcel_hw_init(struct safex
- 		val |= EIP197_MST_CTRL_TX_MAX_CMD(5);
- 		writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL);
- 	}
-+	/*
-+	 * Set maximum number of TX commands to 2^4 = 16 for EIP97 HW2.1/HW2.3
-+	 */
-+	else {
-+		val = 0;
-+		val |= EIP97_MST_CTRL_TX_MAX_CMD(4);
-+		writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL);
-+	}
- 
- 	/* Configure wr/rd cache values */
- 	writel(EIP197_MST_CTRL_RD_CACHE(RD_CACHE_4BITS) |
---- a/drivers/crypto/inside-secure/safexcel.h
-+++ b/drivers/crypto/inside-secure/safexcel.h
-@@ -315,6 +315,7 @@
- #define EIP197_MST_CTRL_RD_CACHE(n)		(((n) & 0xf) << 0)
- #define EIP197_MST_CTRL_WD_CACHE(n)		(((n) & 0xf) << 4)
- #define EIP197_MST_CTRL_TX_MAX_CMD(n)		(((n) & 0xf) << 20)
-+#define EIP97_MST_CTRL_TX_MAX_CMD(n)		(((n) & 0xf) << 4)
- #define EIP197_MST_CTRL_BYTE_SWAP		BIT(24)
- #define EIP197_MST_CTRL_NO_BYTE_SWAP		BIT(25)
- #define EIP197_MST_CTRL_BYTE_SWAP_BITS          GENMASK(25, 24)
diff --git a/target/linux/mediatek/patches-5.15/401-crypto-fix-eip97-cache-incoherent.patch b/target/linux/mediatek/patches-5.15/401-crypto-fix-eip97-cache-incoherent.patch
deleted file mode 100644
index 186c66f6878a1c..00000000000000
--- a/target/linux/mediatek/patches-5.15/401-crypto-fix-eip97-cache-incoherent.patch
+++ /dev/null
@@ -1,26 +0,0 @@
---- a/drivers/crypto/inside-secure/safexcel.h
-+++ b/drivers/crypto/inside-secure/safexcel.h
-@@ -737,6 +737,9 @@ enum safexcel_eip_version {
- /* Priority we use for advertising our algorithms */
- #define SAFEXCEL_CRA_PRIORITY		300
- 
-+/* System cache line size */
-+#define SYSTEM_CACHELINE_SIZE		64
-+
- /* SM3 digest result for zero length message */
- #define EIP197_SM3_ZEROM_HASH	"\x1A\xB2\x1D\x83\x55\xCF\xA1\x7F" \
- 				"\x8E\x61\x19\x48\x31\xE8\x1A\x8F" \
---- a/drivers/crypto/inside-secure/safexcel_hash.c
-+++ b/drivers/crypto/inside-secure/safexcel_hash.c
-@@ -55,9 +55,9 @@ struct safexcel_ahash_req {
- 	u8 block_sz;    /* block size, only set once */
- 	u8 digest_sz;   /* output digest size, only set once */
- 	__le32 state[SHA3_512_BLOCK_SIZE /
--		     sizeof(__le32)] __aligned(sizeof(__le32));
-+		     sizeof(__le32)] __aligned(SYSTEM_CACHELINE_SIZE);
- 
--	u64 len;
-+	u64 len __aligned(SYSTEM_CACHELINE_SIZE);
- 	u64 processed;
- 
- 	u8 cache[HASH_CACHE_SIZE] __aligned(sizeof(u32));
diff --git a/target/linux/mediatek/patches-5.15/405-mt7986-trng-add-rng-support.patch b/target/linux/mediatek/patches-5.15/405-mt7986-trng-add-rng-support.patch
deleted file mode 100644
index 332f17bae73e7d..00000000000000
--- a/target/linux/mediatek/patches-5.15/405-mt7986-trng-add-rng-support.patch
+++ /dev/null
@@ -1,41 +0,0 @@
-From f6ba5e17bee38f8ffe118c47fbfef3cf90eb87ff Mon Sep 17 00:00:00 2001
-From: "Mingming.Su" <Mingming.Su@mediatek.com>
-Date: Wed, 30 Jun 2021 16:59:32 +0800
-Subject: [PATCH] mt7986: trng: add rng support
-
-1. Add trng compatible name for MT7986
-2. Fix mtk_rng_wait_ready() function
-
-Signed-off-by: Mingming.Su <Mingming.Su@mediatek.com>
----
- drivers/char/hw_random/mtk-rng.c | 5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
---- a/drivers/char/hw_random/mtk-rng.c
-+++ b/drivers/char/hw_random/mtk-rng.c
-@@ -22,7 +22,7 @@
- #define RNG_AUTOSUSPEND_TIMEOUT		100
- 
- #define USEC_POLL			2
--#define TIMEOUT_POLL			20
-+#define TIMEOUT_POLL			60
- 
- #define RNG_CTRL			0x00
- #define RNG_EN				BIT(0)
-@@ -77,7 +77,7 @@ static bool mtk_rng_wait_ready(struct hw
- 		readl_poll_timeout_atomic(priv->base + RNG_CTRL, ready,
- 					  ready & RNG_READY, USEC_POLL,
- 					  TIMEOUT_POLL);
--	return !!ready;
-+	return !!(ready & RNG_READY);
- }
- 
- static int mtk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
-@@ -179,6 +179,7 @@ static const struct dev_pm_ops mtk_rng_p
- #endif	/* CONFIG_PM */
- 
- static const struct of_device_id mtk_rng_match[] = {
-+	{ .compatible = "mediatek,mt7986-rng" },
- 	{ .compatible = "mediatek,mt7623-rng" },
- 	{},
- };
diff --git a/target/linux/mediatek/patches-5.15/410-bt-mtk-serial-fix.patch b/target/linux/mediatek/patches-5.15/410-bt-mtk-serial-fix.patch
deleted file mode 100644
index 3f4597c65d68f8..00000000000000
--- a/target/linux/mediatek/patches-5.15/410-bt-mtk-serial-fix.patch
+++ /dev/null
@@ -1,33 +0,0 @@
---- a/drivers/tty/serial/8250/8250.h
-+++ b/drivers/tty/serial/8250/8250.h
-@@ -85,6 +85,7 @@ struct serial8250_config {
- #define UART_CAP_MINI	BIT(17)	/* Mini UART on BCM283X family lacks:
- 					 * STOP PARITY EPAR SPAR WLEN5 WLEN6
- 					 */
-+#define UART_CAP_NMOD	(1 << 18)	/* UART doesn't do termios */
- 
- #define UART_BUG_QUOT	BIT(0)	/* UART has buggy quot LSB */
- #define UART_BUG_TXEN	BIT(1)	/* UART has buggy TX IIR status */
---- a/drivers/tty/serial/8250/8250_port.c
-+++ b/drivers/tty/serial/8250/8250_port.c
-@@ -289,7 +289,7 @@ static const struct serial8250_config ua
- 		.tx_loadsz	= 16,
- 		.fcr		= UART_FCR_ENABLE_FIFO |
- 				  UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
--		.flags		= UART_CAP_FIFO,
-+		.flags		= UART_CAP_FIFO | UART_CAP_NMOD,
- 	},
- 	[PORT_NPCM] = {
- 		.name		= "Nuvoton 16550",
-@@ -2766,6 +2766,11 @@ serial8250_do_set_termios(struct uart_po
- 	unsigned long flags;
- 	unsigned int baud, quot, frac = 0;
- 
-+	if (up->capabilities & UART_CAP_NMOD) {
-+		termios->c_cflag = 0;
-+		return;
-+	}
-+
- 	if (up->capabilities & UART_CAP_MINI) {
- 		termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR);
- 		if ((termios->c_cflag & CSIZE) == CS5 ||
diff --git a/target/linux/mediatek/patches-5.15/420-mtd-spi-nor-add-support-for-Winbond-W25Q512JV.patch b/target/linux/mediatek/patches-5.15/420-mtd-spi-nor-add-support-for-Winbond-W25Q512JV.patch
deleted file mode 100644
index cc9e9c55e36abf..00000000000000
--- a/target/linux/mediatek/patches-5.15/420-mtd-spi-nor-add-support-for-Winbond-W25Q512JV.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From: David Bauer <mail@david-bauer.net>
-To: linux-mtd@lists.infradead.org
-Subject: [PATCH] mtd: spi-nor: add support for Winbond W25Q512JV
-Date: Sat, 13 Feb 2021 16:10:47 +0100
-
-The Winbond W25Q512JV is a 512mb SPI-NOR chip. It supports 4K
-sectors as well as block protection and Dual-/Quad-read.
-
-Tested on: Ubiquiti UniFi 6 LR
-
-Signed-off-by: David Bauer <mail@david-bauer.net>
----
- drivers/mtd/spi-nor/winbond.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/drivers/mtd/spi-nor/winbond.c
-+++ b/drivers/mtd/spi-nor/winbond.c
-@@ -98,6 +98,10 @@ static const struct flash_info winbond_p
- 			     SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
- 	{ "w25q256jw", INFO(0xef6019, 0, 64 * 1024, 512,
- 			     SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
-+	{ "w25q512jv", INFO(0xef4020, 0, 64 * 1024, 1024,
-+			    SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ |
-+			    SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 |
-+			    SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP) },
- 	{ "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024,
- 			    SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ) },
- 	{ "w25q512jvq", INFO(0xef4020, 0, 64 * 1024, 1024,
diff --git a/target/linux/mediatek/patches-5.15/431-drivers-spi-mt65xx-Move-chip_config-to-driver-s-priv.patch b/target/linux/mediatek/patches-5.15/431-drivers-spi-mt65xx-Move-chip_config-to-driver-s-priv.patch
deleted file mode 100644
index a57ee253938433..00000000000000
--- a/target/linux/mediatek/patches-5.15/431-drivers-spi-mt65xx-Move-chip_config-to-driver-s-priv.patch
+++ /dev/null
@@ -1,130 +0,0 @@
-From bfd3acc428085742d754a6d328d1a93ebf9451df Mon Sep 17 00:00:00 2001
-From: "SkyLake.Huang" <skylake.huang@mediatek.com>
-Date: Thu, 23 Jun 2022 18:29:51 +0800
-Subject: [PATCH 1/6] drivers: spi-mt65xx: Move chip_config to driver's private
- data
-
-Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
----
- drivers/spi/spi-mt65xx.c                 | 29 +++++++++---------------
- include/linux/platform_data/spi-mt65xx.h | 17 --------------
- 2 files changed, 11 insertions(+), 35 deletions(-)
- delete mode 100644 include/linux/platform_data/spi-mt65xx.h
-
---- a/drivers/spi/spi-mt65xx.c
-+++ b/drivers/spi/spi-mt65xx.c
-@@ -14,7 +14,6 @@
- #include <linux/of.h>
- #include <linux/gpio/consumer.h>
- #include <linux/platform_device.h>
--#include <linux/platform_data/spi-mt65xx.h>
- #include <linux/pm_runtime.h>
- #include <linux/spi/spi.h>
- #include <linux/spi/spi-mem.h>
-@@ -142,6 +141,8 @@ struct mtk_spi {
- 	struct device *dev;
- 	dma_addr_t tx_dma;
- 	dma_addr_t rx_dma;
-+	u32 sample_sel;
-+	u32 get_tick_dly;
- };
- 
- static const struct mtk_spi_compatible mtk_common_compat;
-@@ -187,15 +188,6 @@ static const struct mtk_spi_compatible m
- 	.no_need_unprepare = true,
- };
- 
--/*
-- * A piece of default chip info unless the platform
-- * supplies it.
-- */
--static const struct mtk_chip_config mtk_default_chip_info = {
--	.sample_sel = 0,
--	.tick_delay = 0,
--};
--
- static const struct of_device_id mtk_spi_of_match[] = {
- 	{ .compatible = "mediatek,spi-ipm",
- 		.data = (void *)&mtk_ipm_compat,
-@@ -323,7 +315,6 @@ static int mtk_spi_hw_init(struct spi_ma
- {
- 	u16 cpha, cpol;
- 	u32 reg_val;
--	struct mtk_chip_config *chip_config = spi->controller_data;
- 	struct mtk_spi *mdata = spi_master_get_devdata(master);
- 
- 	cpha = spi->mode & SPI_CPHA ? 1 : 0;
-@@ -373,7 +364,7 @@ static int mtk_spi_hw_init(struct spi_ma
- 		else
- 			reg_val &= ~SPI_CMD_CS_POL;
- 
--		if (chip_config->sample_sel)
-+		if (mdata->sample_sel)
- 			reg_val |= SPI_CMD_SAMPLE_SEL;
- 		else
- 			reg_val &= ~SPI_CMD_SAMPLE_SEL;
-@@ -400,20 +391,20 @@ static int mtk_spi_hw_init(struct spi_ma
- 		if (mdata->dev_comp->ipm_design) {
- 			reg_val = readl(mdata->base + SPI_CMD_REG);
- 			reg_val &= ~SPI_CMD_IPM_GET_TICKDLY_MASK;
--			reg_val |= ((chip_config->tick_delay & 0x7)
-+			reg_val |= ((mdata->get_tick_dly & 0x7)
- 				    << SPI_CMD_IPM_GET_TICKDLY_OFFSET);
- 			writel(reg_val, mdata->base + SPI_CMD_REG);
- 		} else {
- 			reg_val = readl(mdata->base + SPI_CFG1_REG);
- 			reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK;
--			reg_val |= ((chip_config->tick_delay & 0x7)
-+			reg_val |= ((mdata->get_tick_dly & 0x7)
- 				    << SPI_CFG1_GET_TICK_DLY_OFFSET);
- 			writel(reg_val, mdata->base + SPI_CFG1_REG);
- 		}
- 	} else {
- 		reg_val = readl(mdata->base + SPI_CFG1_REG);
- 		reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK_V1;
--		reg_val |= ((chip_config->tick_delay & 0x3)
-+		reg_val |= ((mdata->get_tick_dly & 0x3)
- 			    << SPI_CFG1_GET_TICK_DLY_OFFSET_V1);
- 		writel(reg_val, mdata->base + SPI_CFG1_REG);
- 	}
-@@ -700,9 +691,6 @@ static int mtk_spi_setup(struct spi_devi
- {
- 	struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
- 
--	if (!spi->controller_data)
--		spi->controller_data = (void *)&mtk_default_chip_info;
--
- 	if (mdata->dev_comp->need_pad_sel && spi->cs_gpiod)
- 		/* CS de-asserted, gpiolib will handle inversion */
- 		gpiod_direction_output(spi->cs_gpiod, 0);
-@@ -1115,6 +1103,10 @@ static int mtk_spi_probe(struct platform
- 	mdata = spi_master_get_devdata(master);
- 	mdata->dev_comp = of_id->data;
- 
-+	/* Set device configs to default first. Calibrate it later. */
-+	mdata->sample_sel = 0;
-+	mdata->get_tick_dly = 2;
-+
- 	if (mdata->dev_comp->enhance_timing)
- 		master->mode_bits |= SPI_CS_HIGH;
- 
---- a/include/linux/platform_data/spi-mt65xx.h
-+++ /dev/null
-@@ -1,17 +0,0 @@
--/* SPDX-License-Identifier: GPL-2.0-only */
--/*
-- *  MTK SPI bus driver definitions
-- *
-- * Copyright (c) 2015 MediaTek Inc.
-- * Author: Leilk Liu <leilk.liu@mediatek.com>
-- */
--
--#ifndef ____LINUX_PLATFORM_DATA_SPI_MTK_H
--#define ____LINUX_PLATFORM_DATA_SPI_MTK_H
--
--/* Board specific platform_data */
--struct mtk_chip_config {
--	u32 sample_sel;
--	u32 tick_delay;
--};
--#endif
diff --git a/target/linux/mediatek/patches-5.15/432-drivers-spi-Add-support-for-dynamic-calibration.patch b/target/linux/mediatek/patches-5.15/432-drivers-spi-Add-support-for-dynamic-calibration.patch
deleted file mode 100644
index e795eda3b2b77f..00000000000000
--- a/target/linux/mediatek/patches-5.15/432-drivers-spi-Add-support-for-dynamic-calibration.patch
+++ /dev/null
@@ -1,236 +0,0 @@
-From 2ade0172154e50c8a2bfd8634c6eff943cffea29 Mon Sep 17 00:00:00 2001
-From: "SkyLake.Huang" <skylake.huang@mediatek.com>
-Date: Thu, 23 Jun 2022 18:35:52 +0800
-Subject: [PATCH 2/6] drivers: spi: Add support for dynamic calibration
-
-Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
----
- drivers/spi/spi.c       | 137 ++++++++++++++++++++++++++++++++++++++++
- include/linux/spi/spi.h |  42 ++++++++++++
- 2 files changed, 179 insertions(+)
-
---- a/drivers/spi/spi.c
-+++ b/drivers/spi/spi.c
-@@ -1246,6 +1246,70 @@ static int spi_transfer_wait(struct spi_
- 	return 0;
- }
- 
-+int spi_do_calibration(struct spi_controller *ctlr, struct spi_device *spi,
-+	int (*cal_read)(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen), void *drv_priv)
-+{
-+	int datalen = ctlr->cal_rule->datalen;
-+	int addrlen = ctlr->cal_rule->addrlen;
-+	u8 *buf;
-+	int ret;
-+	int i;
-+	struct list_head *cal_head, *listptr;
-+	struct spi_cal_target *target;
-+
-+	/* Calculate calibration result */
-+	int hit_val, total_hit, origin;
-+	bool hit;
-+
-+	/* Make sure we can start calibration */
-+	if(!ctlr->cal_target || !ctlr->cal_rule || !ctlr->append_caldata)
-+		return 0;
-+
-+	buf = kzalloc(datalen * sizeof(u8), GFP_KERNEL);
-+	if(!buf)
-+		return -ENOMEM;
-+
-+	ret = ctlr->append_caldata(ctlr);
-+	if (ret)
-+		goto cal_end;
-+
-+	cal_head = ctlr->cal_target;
-+	list_for_each(listptr, cal_head) {
-+		target = list_entry(listptr, struct spi_cal_target, list);
-+
-+		hit = false;
-+		hit_val = 0;
-+		total_hit = 0;
-+		origin = *target->cal_item;
-+
-+		for(i=target->cal_min; i<=target->cal_max; i+=target->step) {
-+			*target->cal_item = i;
-+			ret = (*cal_read)(drv_priv, ctlr->cal_rule->addr, addrlen, buf, datalen);
-+			if(ret)
-+				break;
-+			dev_dbg(&spi->dev, "controller cal item value: 0x%x\n", i);
-+			if(memcmp(ctlr->cal_rule->match_data, buf, datalen * sizeof(u8)) == 0) {
-+				hit = true;
-+				hit_val += i;
-+				total_hit++;
-+				dev_dbg(&spi->dev, "golden data matches data read!\n");
-+			}
-+		}
-+		if(hit) {
-+			*target->cal_item = DIV_ROUND_CLOSEST(hit_val, total_hit);
-+			dev_info(&spi->dev, "calibration result: 0x%x", *target->cal_item);
-+		} else {
-+			*target->cal_item = origin;
-+			dev_warn(&spi->dev, "calibration failed, fallback to default: 0x%x", origin);
-+		}
-+	}
-+
-+cal_end:
-+	kfree(buf);
-+	return ret? ret: 0;
-+}
-+EXPORT_SYMBOL_GPL(spi_do_calibration);
-+
- static void _spi_transfer_delay_ns(u32 ns)
- {
- 	if (!ns)
-@@ -2033,6 +2097,75 @@ void spi_flush_queue(struct spi_controll
- /*-------------------------------------------------------------------------*/
- 
- #if defined(CONFIG_OF)
-+static inline void alloc_cal_data(struct list_head **cal_target,
-+	struct spi_cal_rule **cal_rule, bool enable)
-+{
-+	if(enable) {
-+		*cal_target = kmalloc(sizeof(struct list_head), GFP_KERNEL);
-+		INIT_LIST_HEAD(*cal_target);
-+		*cal_rule = kmalloc(sizeof(struct spi_cal_rule), GFP_KERNEL);
-+	} else {
-+		kfree(*cal_target);
-+		kfree(*cal_rule);
-+	}
-+}
-+
-+static int of_spi_parse_cal_dt(struct spi_controller *ctlr, struct spi_device *spi,
-+			   struct device_node *nc)
-+{
-+	u32 value;
-+	int rc;
-+	const char *cal_mode;
-+
-+	rc = of_property_read_bool(nc, "spi-cal-enable");
-+	if (rc)
-+		alloc_cal_data(&ctlr->cal_target, &ctlr->cal_rule, true);
-+	else
-+		return 0;
-+
-+	rc = of_property_read_string(nc, "spi-cal-mode", &cal_mode);
-+	if(!rc) {
-+		if(strcmp("read-data", cal_mode) == 0){
-+			ctlr->cal_rule->mode = SPI_CAL_READ_DATA;
-+		} else if(strcmp("read-pp", cal_mode) == 0) {
-+			ctlr->cal_rule->mode = SPI_CAL_READ_PP;
-+			return 0;
-+		} else if(strcmp("read-sfdp", cal_mode) == 0){
-+			ctlr->cal_rule->mode = SPI_CAL_READ_SFDP;
-+			return 0;
-+		}
-+	} else
-+		goto err;
-+
-+	ctlr->cal_rule->datalen = 0;
-+	rc = of_property_read_u32(nc, "spi-cal-datalen", &value);
-+	if(!rc && value > 0) {
-+		ctlr->cal_rule->datalen = value;
-+
-+		ctlr->cal_rule->match_data = kzalloc(value * sizeof(u8), GFP_KERNEL);
-+		rc = of_property_read_u8_array(nc, "spi-cal-data",
-+				ctlr->cal_rule->match_data, value);
-+		if(rc)
-+			kfree(ctlr->cal_rule->match_data);
-+	}
-+
-+	rc = of_property_read_u32(nc, "spi-cal-addrlen", &value);
-+	if(!rc && value > 0) {
-+		ctlr->cal_rule->addrlen = value;
-+
-+		ctlr->cal_rule->addr = kzalloc(value * sizeof(u32), GFP_KERNEL);
-+		rc = of_property_read_u32_array(nc, "spi-cal-addr",
-+				ctlr->cal_rule->addr, value);
-+		if(rc)
-+			kfree(ctlr->cal_rule->addr);
-+	}
-+	return 0;
-+
-+err:
-+	alloc_cal_data(&ctlr->cal_target, &ctlr->cal_rule, false);
-+	return 0;
-+}
-+
- static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi,
- 			   struct device_node *nc)
- {
-@@ -2151,6 +2284,10 @@ of_register_spi_device(struct spi_contro
- 	if (rc)
- 		goto err_out;
- 
-+	rc = of_spi_parse_cal_dt(ctlr, spi, nc);
-+	if (rc)
-+		goto err_out;
-+
- 	/* Store a pointer to the node in the device structure */
- 	of_node_get(nc);
- 	spi->dev.of_node = nc;
---- a/include/linux/spi/spi.h
-+++ b/include/linux/spi/spi.h
-@@ -290,6 +290,40 @@ struct spi_driver {
- 	struct device_driver	driver;
- };
- 
-+enum {
-+	SPI_CAL_READ_DATA = 0,
-+	SPI_CAL_READ_PP = 1, /* only for SPI-NAND */
-+	SPI_CAL_READ_SFDP = 2, /* only for SPI-NOR */
-+};
-+
-+struct nand_addr {
-+	unsigned int lun;
-+	unsigned int plane;
-+	unsigned int eraseblock;
-+	unsigned int page;
-+	unsigned int dataoffs;
-+};
-+
-+/**
-+ * Read calibration rule from device dts node.
-+ * Once calibration result matches the rule, we regard is as success.
-+ */
-+struct spi_cal_rule {
-+	int datalen;
-+	u8 *match_data;
-+	int addrlen;
-+	u32 *addr;
-+	int mode;
-+};
-+
-+struct spi_cal_target {
-+	u32 *cal_item;
-+	int cal_min; /* min of cal_item */
-+	int cal_max; /* max of cal_item */
-+	int step; /* Increase/decrease cal_item */
-+	struct list_head list;
-+};
-+
- static inline struct spi_driver *to_spi_driver(struct device_driver *drv)
- {
- 	return drv ? container_of(drv, struct spi_driver, driver) : NULL;
-@@ -665,6 +699,11 @@ struct spi_controller {
- 	void			*dummy_rx;
- 	void			*dummy_tx;
- 
-+	/* For calibration */
-+	int (*append_caldata)(struct spi_controller *ctlr);
-+	struct list_head *cal_target;
-+	struct spi_cal_rule *cal_rule;
-+
- 	int (*fw_translate_cs)(struct spi_controller *ctlr, unsigned cs);
- 
- 	/*
-@@ -1477,6 +1516,9 @@ spi_register_board_info(struct spi_board
- 	{ return 0; }
- #endif
- 
-+extern int spi_do_calibration(struct spi_controller *ctlr,
-+	struct spi_device *spi, int (*cal_read)(void *, u32 *, int, u8 *, int), void *drv_priv);
-+
- /* If you're hotplugging an adapter with devices (parport, usb, etc)
-  * use spi_new_device() to describe each device.  You can also call
-  * spi_unregister_device() to start making that device vanish, but
diff --git a/target/linux/mediatek/patches-5.15/433-drivers-spi-mem-Add-spi-calibration-hook.patch b/target/linux/mediatek/patches-5.15/433-drivers-spi-mem-Add-spi-calibration-hook.patch
deleted file mode 100644
index aaacab01312972..00000000000000
--- a/target/linux/mediatek/patches-5.15/433-drivers-spi-mem-Add-spi-calibration-hook.patch
+++ /dev/null
@@ -1,41 +0,0 @@
-From 06640a5da2973318c06e516da16a5b579622e7c5 Mon Sep 17 00:00:00 2001
-From: "SkyLake.Huang" <skylake.huang@mediatek.com>
-Date: Thu, 23 Jun 2022 18:37:55 +0800
-Subject: [PATCH 3/6] drivers: spi-mem: Add spi calibration hook
-
-Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
----
- drivers/spi/spi-mem.c       | 8 ++++++++
- include/linux/spi/spi-mem.h | 4 ++++
- 2 files changed, 12 insertions(+)
-
---- a/drivers/spi/spi-mem.c
-+++ b/drivers/spi/spi-mem.c
-@@ -410,6 +410,14 @@ int spi_mem_exec_op(struct spi_mem *mem,
- }
- EXPORT_SYMBOL_GPL(spi_mem_exec_op);
- 
-+int spi_mem_do_calibration(struct spi_mem *mem,
-+	int (*cal_read)(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen),
-+	void *priv)
-+{
-+	return spi_do_calibration(mem->spi->controller, mem->spi, cal_read, priv);
-+}
-+EXPORT_SYMBOL_GPL(spi_mem_do_calibration);
-+
- /**
-  * spi_mem_get_name() - Return the SPI mem device name to be used by the
-  *			upper layer if necessary
---- a/include/linux/spi/spi-mem.h
-+++ b/include/linux/spi/spi-mem.h
-@@ -366,6 +366,10 @@ bool spi_mem_supports_op(struct spi_mem
- int spi_mem_exec_op(struct spi_mem *mem,
- 		    const struct spi_mem_op *op);
- 
-+int spi_mem_do_calibration(struct spi_mem *mem,
-+			int (*cal_read)(void *, u32 *, int, u8 *, int),
-+			void *priv);
-+
- const char *spi_mem_get_name(struct spi_mem *mem);
- 
- struct spi_mem_dirmap_desc *
diff --git a/target/linux/mediatek/patches-5.15/434-drivers-spi-mt65xx-Add-controller-s-calibration-para.patch b/target/linux/mediatek/patches-5.15/434-drivers-spi-mt65xx-Add-controller-s-calibration-para.patch
deleted file mode 100644
index a64d6229819bac..00000000000000
--- a/target/linux/mediatek/patches-5.15/434-drivers-spi-mt65xx-Add-controller-s-calibration-para.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From d278c7a0bf730318a7ccf8d0a8b434c813e23fd0 Mon Sep 17 00:00:00 2001
-From: "SkyLake.Huang" <skylake.huang@mediatek.com>
-Date: Thu, 23 Jun 2022 18:39:03 +0800
-Subject: [PATCH 4/6] drivers: spi-mt65xx: Add controller's calibration
- paramter
-
-Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
----
- drivers/spi/spi-mt65xx.c | 16 ++++++++++++++++
- 1 file changed, 16 insertions(+)
-
---- a/drivers/spi/spi-mt65xx.c
-+++ b/drivers/spi/spi-mt65xx.c
-@@ -800,6 +800,21 @@ static irqreturn_t mtk_spi_interrupt(int
- 	return IRQ_HANDLED;
- }
- 
-+static int mtk_spi_append_caldata(struct spi_controller *ctlr)
-+{
-+	struct spi_cal_target *cal_target = kmalloc(sizeof(*cal_target), GFP_KERNEL);
-+	struct mtk_spi *mdata = spi_master_get_devdata(ctlr);
-+
-+	cal_target->cal_item = &mdata->get_tick_dly;
-+	cal_target->cal_min = 0;
-+	cal_target->cal_max = 7;
-+	cal_target->step = 1;
-+
-+	list_add(&cal_target->list, ctlr->cal_target);
-+
-+	return 0;
-+}
-+
- static int mtk_spi_mem_adjust_op_size(struct spi_mem *mem,
- 				      struct spi_mem_op *op)
- {
-@@ -1092,6 +1107,7 @@ static int mtk_spi_probe(struct platform
- 	master->setup = mtk_spi_setup;
- 	master->set_cs_timing = mtk_spi_set_hw_cs_timing;
- 	master->use_gpio_descriptors = true;
-+	master->append_caldata = mtk_spi_append_caldata;
- 
- 	of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node);
- 	if (!of_id) {
diff --git a/target/linux/mediatek/patches-5.15/435-drivers-mtd-spinand-Add-calibration-support-for-spin.patch b/target/linux/mediatek/patches-5.15/435-drivers-mtd-spinand-Add-calibration-support-for-spin.patch
deleted file mode 100644
index e2684eebb74992..00000000000000
--- a/target/linux/mediatek/patches-5.15/435-drivers-mtd-spinand-Add-calibration-support-for-spin.patch
+++ /dev/null
@@ -1,81 +0,0 @@
-From 7670ec4a14891a1a182b98a9c403ffbf6b49e4b1 Mon Sep 17 00:00:00 2001
-From: "SkyLake.Huang" <skylake.huang@mediatek.com>
-Date: Thu, 23 Jun 2022 18:39:56 +0800
-Subject: [PATCH 5/6] drivers: mtd: spinand: Add calibration support for
- spinand
-
-Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
----
- drivers/mtd/nand/spi/core.c | 54 +++++++++++++++++++++++++++++++++++++
- 1 file changed, 54 insertions(+)
-
---- a/drivers/mtd/nand/spi/core.c
-+++ b/drivers/mtd/nand/spi/core.c
-@@ -977,6 +977,56 @@ static int spinand_manufacturer_match(st
- 	return -ENOTSUPP;
- }
- 
-+int spinand_cal_read(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen) {
-+	struct spinand_device *spinand = (struct spinand_device *)priv;
-+	struct device *dev = &spinand->spimem->spi->dev;
-+	struct spi_mem_op op = SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, buf, readlen);
-+	struct nand_pos pos;
-+	struct nand_page_io_req req;
-+	u8 status;
-+	int ret;
-+
-+	if(addrlen != sizeof(struct nand_addr)/sizeof(unsigned int)) {
-+		dev_err(dev, "Must provide correct addr(length) for spinand calibration\n");
-+		return -EINVAL;
-+	}
-+
-+	ret = spinand_reset_op(spinand);
-+	if (ret)
-+		return ret;
-+
-+	/* We should store our golden data in first target because
-+	 * we can't switch target at this moment.
-+	 */
-+	pos = (struct nand_pos){
-+		.target = 0,
-+		.lun = *addr,
-+		.plane = *(addr+1),
-+		.eraseblock = *(addr+2),
-+		.page = *(addr+3),
-+	};
-+
-+	req = (struct nand_page_io_req){
-+		.pos = pos,
-+		.dataoffs = *(addr+4),
-+		.datalen = readlen,
-+		.databuf.in = buf,
-+		.mode = MTD_OPS_AUTO_OOB,
-+	};
-+
-+	ret = spinand_load_page_op(spinand, &req);
-+	if (ret)
-+		return ret;
-+
-+	ret = spinand_wait(spinand, &status);
-+	if (ret < 0)
-+		return ret;
-+
-+	ret = spi_mem_exec_op(spinand->spimem, &op);
-+
-+	return 0;
-+}
-+
- static int spinand_id_detect(struct spinand_device *spinand)
- {
- 	u8 *id = spinand->id.data;
-@@ -1227,6 +1277,10 @@ static int spinand_init(struct spinand_d
- 	if (!spinand->scratchbuf)
- 		return -ENOMEM;
- 
-+	ret = spi_mem_do_calibration(spinand->spimem, spinand_cal_read, spinand);
-+	if (ret)
-+		dev_err(dev, "Failed to calibrate SPI-NAND (err = %d)\n", ret);
-+
- 	ret = spinand_detect(spinand);
- 	if (ret)
- 		goto err_free_bufs;
diff --git a/target/linux/mediatek/patches-5.15/436-drivers-mtd-spi-nor-Add-calibration-support-for-spi-.patch b/target/linux/mediatek/patches-5.15/436-drivers-mtd-spi-nor-Add-calibration-support-for-spi-.patch
deleted file mode 100644
index 61712982fb2607..00000000000000
--- a/target/linux/mediatek/patches-5.15/436-drivers-mtd-spi-nor-Add-calibration-support-for-spi-.patch
+++ /dev/null
@@ -1,57 +0,0 @@
-From f3fe3b15eca7908eaac57f9b8387a5dbc45ec5b2 Mon Sep 17 00:00:00 2001
-From: "SkyLake.Huang" <skylake.huang@mediatek.com>
-Date: Thu, 23 Jun 2022 18:40:59 +0800
-Subject: [PATCH 6/6] drivers: mtd: spi-nor: Add calibration support for
- spi-nor
-
-Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
----
- drivers/mtd/nand/spi/core.c |  5 ++++-
- drivers/mtd/spi-nor/core.c  | 15 +++++++++++++++
- 2 files changed, 19 insertions(+), 1 deletion(-)
-
---- a/drivers/mtd/nand/spi/core.c
-+++ b/drivers/mtd/nand/spi/core.c
-@@ -1018,7 +1018,10 @@ int spinand_cal_read(void *priv, u32 *ad
- 	if (ret)
- 		return ret;
- 
--	ret = spinand_wait(spinand, &status);
-+	ret = spinand_wait(spinand,
-+			   SPINAND_READ_INITIAL_DELAY_US,
-+			   SPINAND_READ_POLL_DELAY_US,
-+			   &status);
- 	if (ret < 0)
- 		return ret;
- 
---- a/drivers/mtd/spi-nor/core.c
-+++ b/drivers/mtd/spi-nor/core.c
-@@ -3061,6 +3061,18 @@ static void spi_nor_debugfs_init(struct
- 					 info->id_len, info->id);
- }
- 
-+static int spi_nor_cal_read(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen)
-+{
-+	struct spi_nor *nor = (struct spi_nor *)priv;
-+
-+	nor->reg_proto = SNOR_PROTO_1_1_1;
-+	nor->read_proto = SNOR_PROTO_1_1_1;
-+	nor->read_opcode = SPINOR_OP_READ;
-+	nor->read_dummy = 0;
-+
-+	return nor->controller_ops->read(nor, *addr, readlen, buf);
-+}
-+
- static const struct flash_info *spi_nor_get_flash_info(struct spi_nor *nor,
- 						       const char *name)
- {
-@@ -3134,6 +3146,9 @@ int spi_nor_scan(struct spi_nor *nor, co
- 	if (!nor->bouncebuf)
- 		return -ENOMEM;
- 
-+	if(nor->spimem)
-+		spi_mem_do_calibration(nor->spimem, spi_nor_cal_read, nor);
-+
- 	info = spi_nor_get_flash_info(nor, name);
- 	if (IS_ERR(info))
- 		return PTR_ERR(info);
diff --git a/target/linux/mediatek/patches-5.15/500-gsw-rtl8367s-mt7622-support.patch b/target/linux/mediatek/patches-5.15/500-gsw-rtl8367s-mt7622-support.patch
deleted file mode 100644
index 977bdeb5b18cdd..00000000000000
--- a/target/linux/mediatek/patches-5.15/500-gsw-rtl8367s-mt7622-support.patch
+++ /dev/null
@@ -1,25 +0,0 @@
---- a/drivers/net/phy/Kconfig
-+++ b/drivers/net/phy/Kconfig
-@@ -364,6 +364,12 @@ config ROCKCHIP_PHY
- 	help
- 	  Currently supports the integrated Ethernet PHY.
- 
-+config RTL8367S_GSW
-+	tristate "rtl8367 Gigabit Switch support for mt7622"
-+	depends on NET_VENDOR_MEDIATEK
-+	help
-+	  This driver supports rtl8367s in mt7622
-+
- config SMSC_PHY
- 	tristate "SMSC PHYs"
- 	help
---- a/drivers/net/phy/Makefile
-+++ b/drivers/net/phy/Makefile
-@@ -91,6 +91,7 @@ obj-$(CONFIG_QSEMI_PHY)		+= qsemi.o
- obj-$(CONFIG_REALTEK_PHY)	+= realtek.o
- obj-$(CONFIG_RENESAS_PHY)	+= uPD60620.o
- obj-$(CONFIG_ROCKCHIP_PHY)	+= rockchip.o
-+obj-$(CONFIG_RTL8367S_GSW)	+= rtk/
- obj-$(CONFIG_SMSC_PHY)		+= smsc.o
- obj-$(CONFIG_STE10XP)		+= ste10Xp.o
- obj-$(CONFIG_TERANETICS_PHY)	+= teranetics.o
diff --git a/target/linux/mediatek/patches-5.15/600-v5.16-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-and-MT.patch b/target/linux/mediatek/patches-5.15/600-v5.16-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-and-MT.patch
deleted file mode 100644
index 6a84ff47db1808..00000000000000
--- a/target/linux/mediatek/patches-5.15/600-v5.16-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-and-MT.patch
+++ /dev/null
@@ -1,332 +0,0 @@
-From: Chuanjia Liu <chuanjia.liu@mediatek.com>
-Date: Mon, 23 Aug 2021 11:27:59 +0800
-Subject: [PATCH] arm64: dts: mediatek: Split PCIe node for MT2712 and MT7622
-
-There are two independent PCIe controllers in MT2712 and MT7622
-platform. Each of them should contain an independent MSI domain.
-
-In old dts architecture, MSI domain will be inherited from the root
-bridge, and all of the devices will share the same MSI domain.
-Hence that, the PCIe devices will not work properly if the irq number
-which required is more than 32.
-
-Split the PCIe node for MT2712 and MT7622 platform to comply with
-the hardware design and fix MSI issue.
-
-Signed-off-by: Chuanjia Liu <chuanjia.liu@mediatek.com>
-Acked-by: Ryder Lee <ryder.lee@mediatek.com>
-Link: https://lore.kernel.org/r/20210823032800.1660-6-chuanjia.liu@mediatek.com
-Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
----
-
---- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
-@@ -915,64 +915,67 @@
- 		};
- 	};
- 
--	pcie: pcie@11700000 {
-+	pcie1: pcie@112ff000 {
- 		compatible = "mediatek,mt2712-pcie";
- 		device_type = "pci";
--		reg = <0 0x11700000 0 0x1000>,
--		      <0 0x112ff000 0 0x1000>;
--		reg-names = "port0", "port1";
-+		reg = <0 0x112ff000 0 0x1000>;
-+		reg-names = "port1";
-+		linux,pci-domain = <1>;
- 		#address-cells = <3>;
- 		#size-cells = <2>;
--		interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
--			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
--		clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
--			 <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
--			 <&pericfg CLK_PERI_PCIE0>,
-+		interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
-+		interrupt-names = "pcie_irq";
-+		clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
- 			 <&pericfg CLK_PERI_PCIE1>;
--		clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1";
--		phys = <&u3port0 PHY_TYPE_PCIE>, <&u3port1 PHY_TYPE_PCIE>;
--		phy-names = "pcie-phy0", "pcie-phy1";
-+		clock-names = "sys_ck1", "ahb_ck1";
-+		phys = <&u3port1 PHY_TYPE_PCIE>;
-+		phy-names = "pcie-phy1";
- 		bus-range = <0x00 0xff>;
--		ranges = <0x82000000 0 0x20000000  0x0 0x20000000  0 0x10000000>;
-+		ranges = <0x82000000 0 0x11400000  0x0 0x11400000  0 0x300000>;
-+		status = "disabled";
- 
--		pcie0: pcie@0,0 {
--			device_type = "pci";
--			status = "disabled";
--			reg = <0x0000 0 0 0 0>;
--			#address-cells = <3>;
--			#size-cells = <2>;
-+		#interrupt-cells = <1>;
-+		interrupt-map-mask = <0 0 0 7>;
-+		interrupt-map = <0 0 0 1 &pcie_intc1 0>,
-+				<0 0 0 2 &pcie_intc1 1>,
-+				<0 0 0 3 &pcie_intc1 2>,
-+				<0 0 0 4 &pcie_intc1 3>;
-+		pcie_intc1: interrupt-controller {
-+			interrupt-controller;
-+			#address-cells = <0>;
- 			#interrupt-cells = <1>;
--			ranges;
--			interrupt-map-mask = <0 0 0 7>;
--			interrupt-map = <0 0 0 1 &pcie_intc0 0>,
--					<0 0 0 2 &pcie_intc0 1>,
--					<0 0 0 3 &pcie_intc0 2>,
--					<0 0 0 4 &pcie_intc0 3>;
--			pcie_intc0: interrupt-controller {
--				interrupt-controller;
--				#address-cells = <0>;
--				#interrupt-cells = <1>;
--			};
- 		};
-+	};
-+
-+	pcie0: pcie@11700000 {
-+		compatible = "mediatek,mt2712-pcie";
-+		device_type = "pci";
-+		reg = <0 0x11700000 0 0x1000>;
-+		reg-names = "port0";
-+		linux,pci-domain = <0>;
-+		#address-cells = <3>;
-+		#size-cells = <2>;
-+		interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
-+		interrupt-names = "pcie_irq";
-+		clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
-+			 <&pericfg CLK_PERI_PCIE0>;
-+		clock-names = "sys_ck0", "ahb_ck0";
-+		phys = <&u3port0 PHY_TYPE_PCIE>;
-+		phy-names = "pcie-phy0";
-+		bus-range = <0x00 0xff>;
-+		ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
-+		status = "disabled";
- 
--		pcie1: pcie@1,0 {
--			device_type = "pci";
--			status = "disabled";
--			reg = <0x0800 0 0 0 0>;
--			#address-cells = <3>;
--			#size-cells = <2>;
-+		#interrupt-cells = <1>;
-+		interrupt-map-mask = <0 0 0 7>;
-+		interrupt-map = <0 0 0 1 &pcie_intc0 0>,
-+				<0 0 0 2 &pcie_intc0 1>,
-+				<0 0 0 3 &pcie_intc0 2>,
-+				<0 0 0 4 &pcie_intc0 3>;
-+		pcie_intc0: interrupt-controller {
-+			interrupt-controller;
-+			#address-cells = <0>;
- 			#interrupt-cells = <1>;
--			ranges;
--			interrupt-map-mask = <0 0 0 7>;
--			interrupt-map = <0 0 0 1 &pcie_intc1 0>,
--					<0 0 0 2 &pcie_intc1 1>,
--					<0 0 0 3 &pcie_intc1 2>,
--					<0 0 0 4 &pcie_intc1 3>;
--			pcie_intc1: interrupt-controller {
--				interrupt-controller;
--				#address-cells = <0>;
--				#interrupt-cells = <1>;
--			};
- 		};
- 	};
- 
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -302,18 +302,16 @@
- 	};
- };
- 
--&pcie {
-+&pcie0 {
- 	pinctrl-names = "default";
--	pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
-+	pinctrl-0 = <&pcie0_pins>;
- 	status = "okay";
-+};
- 
--	pcie@0,0 {
--		status = "okay";
--	};
--
--	pcie@1,0 {
--		status = "okay";
--	};
-+&pcie1 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&pcie1_pins>;
-+	status = "okay";
- };
- 
- &pio {
---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-@@ -232,18 +232,16 @@
- 	};
- };
- 
--&pcie {
-+&pcie0 {
- 	pinctrl-names = "default";
--	pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
-+	pinctrl-0 = <&pcie0_pins>;
- 	status = "okay";
-+};
- 
--	pcie@0,0 {
--		status = "okay";
--	};
--
--	pcie@1,0 {
--		status = "okay";
--	};
-+&pcie1 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&pcie1_pins>;
-+	status = "okay";
- };
- 
- &pio {
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -809,75 +809,83 @@
- 		#reset-cells = <1>;
- 	};
- 
--	pcie: pcie@1a140000 {
-+	pciecfg: pciecfg@1a140000 {
-+		compatible = "mediatek,generic-pciecfg", "syscon";
-+		reg = <0 0x1a140000 0 0x1000>;
-+	};
-+
-+	pcie0: pcie@1a143000 {
- 		compatible = "mediatek,mt7622-pcie";
- 		device_type = "pci";
--		reg = <0 0x1a140000 0 0x1000>,
--		      <0 0x1a143000 0 0x1000>,
--		      <0 0x1a145000 0 0x1000>;
--		reg-names = "subsys", "port0", "port1";
-+		reg = <0 0x1a143000 0 0x1000>;
-+		reg-names = "port0";
-+		linux,pci-domain = <0>;
- 		#address-cells = <3>;
- 		#size-cells = <2>;
--		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
--			     <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
-+		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
-+		interrupt-names = "pcie_irq";
- 		clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
--			 <&pciesys CLK_PCIE_P1_MAC_EN>,
--			 <&pciesys CLK_PCIE_P0_AHB_EN>,
- 			 <&pciesys CLK_PCIE_P0_AHB_EN>,
- 			 <&pciesys CLK_PCIE_P0_AUX_EN>,
--			 <&pciesys CLK_PCIE_P1_AUX_EN>,
- 			 <&pciesys CLK_PCIE_P0_AXI_EN>,
--			 <&pciesys CLK_PCIE_P1_AXI_EN>,
- 			 <&pciesys CLK_PCIE_P0_OBFF_EN>,
--			 <&pciesys CLK_PCIE_P1_OBFF_EN>,
--			 <&pciesys CLK_PCIE_P0_PIPE_EN>,
--			 <&pciesys CLK_PCIE_P1_PIPE_EN>;
--		clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
--			      "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
--			      "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
-+			 <&pciesys CLK_PCIE_P0_PIPE_EN>;
-+		clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
-+			      "axi_ck0", "obff_ck0", "pipe_ck0";
-+
- 		power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
- 		bus-range = <0x00 0xff>;
--		ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
-+		ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>;
- 		status = "disabled";
- 
--		pcie0: pcie@0,0 {
--			reg = <0x0000 0 0 0 0>;
--			#address-cells = <3>;
--			#size-cells = <2>;
-+		#interrupt-cells = <1>;
-+		interrupt-map-mask = <0 0 0 7>;
-+		interrupt-map = <0 0 0 1 &pcie_intc0 0>,
-+				<0 0 0 2 &pcie_intc0 1>,
-+				<0 0 0 3 &pcie_intc0 2>,
-+				<0 0 0 4 &pcie_intc0 3>;
-+		pcie_intc0: interrupt-controller {
-+			interrupt-controller;
-+			#address-cells = <0>;
- 			#interrupt-cells = <1>;
--			ranges;
--			status = "disabled";
--
--			interrupt-map-mask = <0 0 0 7>;
--			interrupt-map = <0 0 0 1 &pcie_intc0 0>,
--					<0 0 0 2 &pcie_intc0 1>,
--					<0 0 0 3 &pcie_intc0 2>,
--					<0 0 0 4 &pcie_intc0 3>;
--			pcie_intc0: interrupt-controller {
--				interrupt-controller;
--				#address-cells = <0>;
--				#interrupt-cells = <1>;
--			};
- 		};
-+	};
- 
--		pcie1: pcie@1,0 {
--			reg = <0x0800 0 0 0 0>;
--			#address-cells = <3>;
--			#size-cells = <2>;
--			#interrupt-cells = <1>;
--			ranges;
--			status = "disabled";
-+	pcie1: pcie@1a145000 {
-+		compatible = "mediatek,mt7622-pcie";
-+		device_type = "pci";
-+		reg = <0 0x1a145000 0 0x1000>;
-+		reg-names = "port1";
-+		linux,pci-domain = <1>;
-+		#address-cells = <3>;
-+		#size-cells = <2>;
-+		interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
-+		interrupt-names = "pcie_irq";
-+		clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
-+			 /* designer has connect RC1 with p0_ahb clock */
-+			 <&pciesys CLK_PCIE_P0_AHB_EN>,
-+			 <&pciesys CLK_PCIE_P1_AUX_EN>,
-+			 <&pciesys CLK_PCIE_P1_AXI_EN>,
-+			 <&pciesys CLK_PCIE_P1_OBFF_EN>,
-+			 <&pciesys CLK_PCIE_P1_PIPE_EN>;
-+		clock-names = "sys_ck1", "ahb_ck1", "aux_ck1",
-+			      "axi_ck1", "obff_ck1", "pipe_ck1";
-+
-+		power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
-+		bus-range = <0x00 0xff>;
-+		ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>;
-+		status = "disabled";
- 
--			interrupt-map-mask = <0 0 0 7>;
--			interrupt-map = <0 0 0 1 &pcie_intc1 0>,
--					<0 0 0 2 &pcie_intc1 1>,
--					<0 0 0 3 &pcie_intc1 2>,
--					<0 0 0 4 &pcie_intc1 3>;
--			pcie_intc1: interrupt-controller {
--				interrupt-controller;
--				#address-cells = <0>;
--				#interrupt-cells = <1>;
--			};
-+		#interrupt-cells = <1>;
-+		interrupt-map-mask = <0 0 0 7>;
-+		interrupt-map = <0 0 0 1 &pcie_intc1 0>,
-+				<0 0 0 2 &pcie_intc1 1>,
-+				<0 0 0 3 &pcie_intc1 2>,
-+				<0 0 0 4 &pcie_intc1 3>;
-+		pcie_intc1: interrupt-controller {
-+			interrupt-controller;
-+			#address-cells = <0>;
-+			#interrupt-cells = <1>;
- 		};
- 	};
- 
diff --git a/target/linux/mediatek/patches-5.15/601-PCI-mediatek-Assert-PERST-for-100ms-for-power-and-cl.patch b/target/linux/mediatek/patches-5.15/601-PCI-mediatek-Assert-PERST-for-100ms-for-power-and-cl.patch
deleted file mode 100644
index ff482272108307..00000000000000
--- a/target/linux/mediatek/patches-5.15/601-PCI-mediatek-Assert-PERST-for-100ms-for-power-and-cl.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From: qizhong cheng <qizhong.cheng@mediatek.com>
-Date: Mon, 27 Dec 2021 21:31:10 +0800
-Subject: [PATCH] PCI: mediatek: Assert PERST# for 100ms for power and clock to
- stabilize
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
-2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should
-be delayed 100ms (TPVPERL) for the power and clock to become stable.
-
-Link: https://lore.kernel.org/r/20211227133110.14500-1-qizhong.cheng@mediatek.com
-Signed-off-by: qizhong cheng <qizhong.cheng@mediatek.com>
-Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
-Acked-by: Pali Rohár <pali@kernel.org>
----
-
---- a/drivers/pci/controller/pcie-mediatek.c
-+++ b/drivers/pci/controller/pcie-mediatek.c
-@@ -702,6 +702,13 @@ static int mtk_pcie_startup_port_v2(stru
- 	 */
- 	writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
- 
-+	/*
-+	 * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
-+	 * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should
-+	 * be delayed 100ms (TPVPERL) for the power and clock to become stable.
-+	 */
-+	msleep(100);
-+
- 	/* De-assert PHY, PE, PIPE, MAC and configuration reset	*/
- 	val = readl(port->base + PCIE_RST_CTRL);
- 	val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
diff --git a/target/linux/mediatek/patches-5.15/602-arm64-dts-mediatek-add-mt7622-pcie-slot-node.patch b/target/linux/mediatek/patches-5.15/602-arm64-dts-mediatek-add-mt7622-pcie-slot-node.patch
deleted file mode 100644
index bf479ab53b2cc6..00000000000000
--- a/target/linux/mediatek/patches-5.15/602-arm64-dts-mediatek-add-mt7622-pcie-slot-node.patch
+++ /dev/null
@@ -1,28 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -849,6 +849,12 @@
- 			#address-cells = <0>;
- 			#interrupt-cells = <1>;
- 		};
-+
-+		slot0: pcie@0,0 {
-+			reg = <0x0000 0 0 0 0>;
-+			#address-cells = <3>;
-+			#size-cells = <2>;
-+		};
- 	};
- 
- 	pcie1: pcie@1a145000 {
-@@ -887,6 +893,12 @@
- 			#address-cells = <0>;
- 			#interrupt-cells = <1>;
- 		};
-+
-+		slot1: pcie@1,0 {
-+			reg = <0x0800 0 0 0 0>;
-+			#address-cells = <3>;
-+			#size-cells = <2>;
-+		};
- 	};
- 
- 	sata: sata@1a200000 {
diff --git a/target/linux/mediatek/patches-5.15/603-v5.16-ARM-dts-mediatek-Update-mt7629-PCIe-node.patch b/target/linux/mediatek/patches-5.15/603-v5.16-ARM-dts-mediatek-Update-mt7629-PCIe-node.patch
deleted file mode 100644
index 252ef080f59fc0..00000000000000
--- a/target/linux/mediatek/patches-5.15/603-v5.16-ARM-dts-mediatek-Update-mt7629-PCIe-node.patch
+++ /dev/null
@@ -1,203 +0,0 @@
-From patchwork Thu May 28 06:16:48 2020
-Content-Type: text/plain; charset="utf-8"
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-Subject: [PATCH v2 4/4] ARM: dts: mediatek: Update mt7629 PCIe node
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-From: "chuanjia.liu" <Chuanjia.Liu@mediatek.com>
-
-Remove unused property and add pciecfg node.
-
-Signed-off-by: chuanjia.liu <Chuanjia.Liu@mediatek.com>
----
- arch/arm/boot/dts/mt7629-rfb.dts |  3 ++-
- arch/arm/boot/dts/mt7629.dtsi    | 23 +++++++++++++----------
- 2 files changed, 15 insertions(+), 11 deletions(-)
-
---- a/arch/arm/boot/dts/mt7629-rfb.dts
-+++ b/arch/arm/boot/dts/mt7629-rfb.dts
-@@ -149,9 +149,10 @@
- 	};
- };
- 
--&pcie {
-+&pcie1 {
- 	pinctrl-names = "default";
- 	pinctrl-0 = <&pcie_pins>;
-+	status = "okay";
- };
- 
- &pciephy1 {
---- a/arch/arm/boot/dts/mt7629.dtsi
-+++ b/arch/arm/boot/dts/mt7629.dtsi
-@@ -382,16 +382,21 @@
- 			#reset-cells = <1>;
- 		};
- 
--		pcie: pcie@1a140000 {
-+		pciecfg: pciecfg@1a140000 {
-+			compatible = "mediatek,mt7629-pciecfg", "syscon";
-+			reg = <0x1a140000 0x1000>;
-+		};
-+
-+		pcie1: pcie@1a145000 {
- 			compatible = "mediatek,mt7629-pcie";
- 			device_type = "pci";
--			reg = <0x1a140000 0x1000>,
--			      <0x1a145000 0x1000>;
--			reg-names = "subsys","port1";
-+			reg = <0x1a145000 0x1000>;
-+			reg-names = "port1";
-+			mediatek,pcie-cfg = <&pciecfg>;
- 			#address-cells = <3>;
- 			#size-cells = <2>;
--			interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>,
--				     <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
-+			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
-+			interrupt-names = "pcie_irq";
- 			clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
- 				 <&pciesys CLK_PCIE_P0_AHB_EN>,
- 				 <&pciesys CLK_PCIE_P1_AUX_EN>,
-@@ -412,21 +417,19 @@
- 			power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
- 			bus-range = <0x00 0xff>;
- 			ranges = <0x82000000 0 0x20000000 0x20000000 0 0x10000000>;
-+			status = "disabled";
- 
--			pcie1: pcie@1,0 {
--				device_type = "pci";
-+			slot1: pcie@1,0 {
- 				reg = <0x0800 0 0 0 0>;
- 				#address-cells = <3>;
- 				#size-cells = <2>;
- 				#interrupt-cells = <1>;
- 				ranges;
--				num-lanes = <1>;
- 				interrupt-map-mask = <0 0 0 7>;
- 				interrupt-map = <0 0 0 1 &pcie_intc1 0>,
- 						<0 0 0 2 &pcie_intc1 1>,
- 						<0 0 0 3 &pcie_intc1 2>,
- 						<0 0 0 4 &pcie_intc1 3>;
--
- 				pcie_intc1: interrupt-controller {
- 					interrupt-controller;
- 					#address-cells = <0>;
diff --git a/target/linux/mediatek/patches-5.15/610-pcie-mediatek-fix-clearing-interrupt-status.patch b/target/linux/mediatek/patches-5.15/610-pcie-mediatek-fix-clearing-interrupt-status.patch
deleted file mode 100644
index 2bebfddf5c6952..00000000000000
--- a/target/linux/mediatek/patches-5.15/610-pcie-mediatek-fix-clearing-interrupt-status.patch
+++ /dev/null
@@ -1,23 +0,0 @@
-From: Felix Fietkau <nbd@nbd.name>
-Date: Fri, 4 Sep 2020 18:33:27 +0200
-Subject: [PATCH] pcie-mediatek: fix clearing interrupt status
-
-Clearing the status needs to happen after running the handler, otherwise
-we will get an extra spurious interrupt after the cause has been cleared
-
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
-
---- a/drivers/pci/controller/pcie-mediatek.c
-+++ b/drivers/pci/controller/pcie-mediatek.c
-@@ -614,9 +614,9 @@ static void mtk_pcie_intr_handler(struct
- 	if (status & INTX_MASK) {
- 		for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) {
- 			/* Clear the INTx */
--			writel(1 << bit, port->base + PCIE_INT_STATUS);
- 			generic_handle_domain_irq(port->irq_domain,
- 						  bit - INTX_SHIFT);
-+			writel(1 << bit, port->base + PCIE_INT_STATUS);
- 		}
- 	}
- 
diff --git a/target/linux/mediatek/patches-5.15/611-pcie-mediatek-gen3-PERST-for-100ms.patch b/target/linux/mediatek/patches-5.15/611-pcie-mediatek-gen3-PERST-for-100ms.patch
deleted file mode 100644
index d526aded85a7b9..00000000000000
--- a/target/linux/mediatek/patches-5.15/611-pcie-mediatek-gen3-PERST-for-100ms.patch
+++ /dev/null
@@ -1,17 +0,0 @@
---- a/drivers/pci/controller/pcie-mediatek-gen3.c
-+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
-@@ -319,7 +319,13 @@ static int mtk_pcie_startup_port(struct
- 	msleep(100);
- 
- 	/* De-assert reset signals */
--	val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB);
-+	val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB);
-+	writel_relaxed(val, port->base + PCIE_RST_CTRL_REG);
-+
-+	msleep(100);
-+
-+	/* De-assert PERST# signals */
-+	val &= ~(PCIE_PE_RSTB);
- 	writel_relaxed(val, port->base + PCIE_RST_CTRL_REG);
- 
- 	/* Check if the link is up or not */
diff --git a/target/linux/mediatek/patches-5.15/702-v5.17-net-mdio-add-helpers-to-extract-clause-45-regad-and-.patch b/target/linux/mediatek/patches-5.15/702-v5.17-net-mdio-add-helpers-to-extract-clause-45-regad-and-.patch
deleted file mode 100644
index da33aaa72f30c8..00000000000000
--- a/target/linux/mediatek/patches-5.15/702-v5.17-net-mdio-add-helpers-to-extract-clause-45-regad-and-.patch
+++ /dev/null
@@ -1,53 +0,0 @@
-From c6af53f038aa32cec12e8a305ba07c7ef168f1b0 Mon Sep 17 00:00:00 2001
-From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
-Date: Tue, 4 Jan 2022 12:07:00 +0000
-Subject: [PATCH 2/3] net: mdio: add helpers to extract clause 45 regad and
- devad fields
-
-Add a couple of helpers and definitions to extract the clause 45 regad
-and devad fields from the regnum passed into MDIO drivers.
-
-Tested-by: Daniel Golle <daniel@makrotopia.org>
-Reviewed-by: Andrew Lunn <andrew@lunn.ch>
-Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- include/linux/mdio.h | 12 ++++++++++++
- 1 file changed, 12 insertions(+)
-
---- a/include/linux/mdio.h
-+++ b/include/linux/mdio.h
-@@ -7,6 +7,7 @@
- #define __LINUX_MDIO_H__
- 
- #include <uapi/linux/mdio.h>
-+#include <linux/bitfield.h>
- #include <linux/mod_devicetable.h>
- 
- /* Or MII_ADDR_C45 into regnum for read/write on mii_bus to enable the 21 bit
-@@ -14,6 +15,7 @@
-  */
- #define MII_ADDR_C45		(1<<30)
- #define MII_DEVADDR_C45_SHIFT	16
-+#define MII_DEVADDR_C45_MASK	GENMASK(20, 16)
- #define MII_REGADDR_C45_MASK	GENMASK(15, 0)
- 
- struct gpio_desc;
-@@ -355,6 +357,16 @@ static inline u32 mdiobus_c45_addr(int d
- 	return MII_ADDR_C45 | devad << MII_DEVADDR_C45_SHIFT | regnum;
- }
- 
-+static inline u16 mdiobus_c45_regad(u32 regnum)
-+{
-+	return FIELD_GET(MII_REGADDR_C45_MASK, regnum);
-+}
-+
-+static inline u16 mdiobus_c45_devad(u32 regnum)
-+{
-+	return FIELD_GET(MII_DEVADDR_C45_MASK, regnum);
-+}
-+
- static inline int __mdiobus_c45_read(struct mii_bus *bus, int prtad, int devad,
- 				     u16 regnum)
- {
diff --git a/target/linux/mediatek/patches-5.15/703-v5.17-net-ethernet-mtk_eth_soc-implement-Clause-45-MDIO-ac.patch b/target/linux/mediatek/patches-5.15/703-v5.17-net-ethernet-mtk_eth_soc-implement-Clause-45-MDIO-ac.patch
deleted file mode 100644
index 3f73277aa6b368..00000000000000
--- a/target/linux/mediatek/patches-5.15/703-v5.17-net-ethernet-mtk_eth_soc-implement-Clause-45-MDIO-ac.patch
+++ /dev/null
@@ -1,128 +0,0 @@
-From e2e7f6e29c99a1c6afc0e0aa4b9ea80302d28720 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Tue, 4 Jan 2022 12:07:46 +0000
-Subject: [PATCH 3/3] net: ethernet: mtk_eth_soc: implement Clause 45 MDIO
- access
-
-Implement read and write access to IEEE 802.3 Clause 45 Ethernet
-phy registers while making use of new mdiobus_c45_regad and
-mdiobus_c45_devad helpers.
-
-Tested on the Ubiquiti UniFi 6 LR access point featuring
-MediaTek MT7622BV WiSoC with Aquantia AQR112C.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 70 +++++++++++++++++----
- drivers/net/ethernet/mediatek/mtk_eth_soc.h |  3 +
- 2 files changed, 60 insertions(+), 13 deletions(-)
-
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -324,13 +324,35 @@ static int _mtk_mdio_write(struct mtk_et
- 	if (ret < 0)
- 		return ret;
- 
--	mtk_w32(eth, PHY_IAC_ACCESS |
--		     PHY_IAC_START_C22 |
--		     PHY_IAC_CMD_WRITE |
--		     PHY_IAC_REG(phy_reg) |
--		     PHY_IAC_ADDR(phy_addr) |
--		     PHY_IAC_DATA(write_data),
--		MTK_PHY_IAC);
-+	if (phy_reg & MII_ADDR_C45) {
-+		mtk_w32(eth, PHY_IAC_ACCESS |
-+			     PHY_IAC_START_C45 |
-+			     PHY_IAC_CMD_C45_ADDR |
-+			     PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) |
-+			     PHY_IAC_ADDR(phy_addr) |
-+			     PHY_IAC_DATA(mdiobus_c45_regad(phy_reg)),
-+			MTK_PHY_IAC);
-+
-+		ret = mtk_mdio_busy_wait(eth);
-+		if (ret < 0)
-+			return ret;
-+
-+		mtk_w32(eth, PHY_IAC_ACCESS |
-+			     PHY_IAC_START_C45 |
-+			     PHY_IAC_CMD_WRITE |
-+			     PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) |
-+			     PHY_IAC_ADDR(phy_addr) |
-+			     PHY_IAC_DATA(write_data),
-+			MTK_PHY_IAC);
-+	} else {
-+		mtk_w32(eth, PHY_IAC_ACCESS |
-+			     PHY_IAC_START_C22 |
-+			     PHY_IAC_CMD_WRITE |
-+			     PHY_IAC_REG(phy_reg) |
-+			     PHY_IAC_ADDR(phy_addr) |
-+			     PHY_IAC_DATA(write_data),
-+			MTK_PHY_IAC);
-+	}
- 
- 	ret = mtk_mdio_busy_wait(eth);
- 	if (ret < 0)
-@@ -347,12 +369,33 @@ static int _mtk_mdio_read(struct mtk_eth
- 	if (ret < 0)
- 		return ret;
- 
--	mtk_w32(eth, PHY_IAC_ACCESS |
--		     PHY_IAC_START_C22 |
--		     PHY_IAC_CMD_C22_READ |
--		     PHY_IAC_REG(phy_reg) |
--		     PHY_IAC_ADDR(phy_addr),
--		MTK_PHY_IAC);
-+	if (phy_reg & MII_ADDR_C45) {
-+		mtk_w32(eth, PHY_IAC_ACCESS |
-+			     PHY_IAC_START_C45 |
-+			     PHY_IAC_CMD_C45_ADDR |
-+			     PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) |
-+			     PHY_IAC_ADDR(phy_addr) |
-+			     PHY_IAC_DATA(mdiobus_c45_regad(phy_reg)),
-+			MTK_PHY_IAC);
-+
-+		ret = mtk_mdio_busy_wait(eth);
-+		if (ret < 0)
-+			return ret;
-+
-+		mtk_w32(eth, PHY_IAC_ACCESS |
-+			     PHY_IAC_START_C45 |
-+			     PHY_IAC_CMD_C45_READ |
-+			     PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) |
-+			     PHY_IAC_ADDR(phy_addr),
-+			MTK_PHY_IAC);
-+	} else {
-+		mtk_w32(eth, PHY_IAC_ACCESS |
-+			     PHY_IAC_START_C22 |
-+			     PHY_IAC_CMD_C22_READ |
-+			     PHY_IAC_REG(phy_reg) |
-+			     PHY_IAC_ADDR(phy_addr),
-+			MTK_PHY_IAC);
-+	}
- 
- 	ret = mtk_mdio_busy_wait(eth);
- 	if (ret < 0)
-@@ -899,6 +942,7 @@ static int mtk_mdio_init(struct mtk_eth
- 	eth->mii_bus->name = "mdio";
- 	eth->mii_bus->read = mtk_mdio_read;
- 	eth->mii_bus->write = mtk_mdio_write;
-+	eth->mii_bus->probe_capabilities = MDIOBUS_C22_C45;
- 	eth->mii_bus->priv = eth;
- 	eth->mii_bus->parent = eth->dev;
- 
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -402,9 +402,12 @@
- #define PHY_IAC_ADDR_MASK	GENMASK(24, 20)
- #define PHY_IAC_ADDR(x)		FIELD_PREP(PHY_IAC_ADDR_MASK, (x))
- #define PHY_IAC_CMD_MASK	GENMASK(19, 18)
-+#define PHY_IAC_CMD_C45_ADDR	FIELD_PREP(PHY_IAC_CMD_MASK, 0)
- #define PHY_IAC_CMD_WRITE	FIELD_PREP(PHY_IAC_CMD_MASK, 1)
- #define PHY_IAC_CMD_C22_READ	FIELD_PREP(PHY_IAC_CMD_MASK, 2)
-+#define PHY_IAC_CMD_C45_READ	FIELD_PREP(PHY_IAC_CMD_MASK, 3)
- #define PHY_IAC_START_MASK	GENMASK(17, 16)
-+#define PHY_IAC_START_C45	FIELD_PREP(PHY_IAC_START_MASK, 0)
- #define PHY_IAC_START_C22	FIELD_PREP(PHY_IAC_START_MASK, 1)
- #define PHY_IAC_DATA_MASK	GENMASK(15, 0)
- #define PHY_IAC_DATA(x)		FIELD_PREP(PHY_IAC_DATA_MASK, (x))
diff --git a/target/linux/mediatek/patches-5.15/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch b/target/linux/mediatek/patches-5.15/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch
deleted file mode 100644
index de64eda8277d5c..00000000000000
--- a/target/linux/mediatek/patches-5.15/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch
+++ /dev/null
@@ -1,82 +0,0 @@
-From: Felix Fietkau <nbd@nbd.name>
-Date: Fri, 4 Sep 2020 18:42:42 +0200
-Subject: [PATCH] pci: pcie-mediatek: add support for coherent DMA
-
-It improves performance by eliminating the need for a cache flush for DMA on
-attached devices
-
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
-
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -837,6 +837,9 @@
- 		bus-range = <0x00 0xff>;
- 		ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>;
- 		status = "disabled";
-+		dma-coherent;
-+		mediatek,hifsys = <&hifsys>;
-+		mediatek,cci-control = <&cci_control2>;
- 
- 		#interrupt-cells = <1>;
- 		interrupt-map-mask = <0 0 0 7>;
-@@ -881,6 +884,9 @@
- 		bus-range = <0x00 0xff>;
- 		ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>;
- 		status = "disabled";
-+		dma-coherent;
-+		mediatek,hifsys = <&hifsys>;
-+		mediatek,cci-control = <&cci_control2>;
- 
- 		#interrupt-cells = <1>;
- 		interrupt-map-mask = <0 0 0 7>;
---- a/drivers/pci/controller/pcie-mediatek.c
-+++ b/drivers/pci/controller/pcie-mediatek.c
-@@ -20,6 +20,7 @@
- #include <linux/of_address.h>
- #include <linux/of_pci.h>
- #include <linux/of_platform.h>
-+#include <linux/of_address.h>
- #include <linux/pci.h>
- #include <linux/phy/phy.h>
- #include <linux/platform_device.h>
-@@ -139,6 +140,11 @@
- #define PCIE_LINK_STATUS_V2	0x804
- #define PCIE_PORT_LINKUP_V2	BIT(10)
- 
-+/* DMA channel mapping */
-+#define HIFSYS_DMA_AG_MAP	0x008
-+#define HIFSYS_DMA_AG_MAP_PCIE0	BIT(0)
-+#define HIFSYS_DMA_AG_MAP_PCIE1	BIT(1)
-+
- struct mtk_pcie_port;
- 
- /**
-@@ -1054,6 +1060,27 @@ static int mtk_pcie_setup(struct mtk_pci
- 	struct mtk_pcie_port *port, *tmp;
- 	int err, slot;
- 
-+	if (of_dma_is_coherent(node)) {
-+		struct regmap *con;
-+		u32 mask;
-+
-+		con = syscon_regmap_lookup_by_phandle(node,
-+						      "mediatek,cci-control");
-+		/* enable CPU/bus coherency */
-+		if (!IS_ERR(con))
-+			regmap_write(con, 0, 3);
-+
-+		con = syscon_regmap_lookup_by_phandle(node,
-+						      "mediatek,hifsys");
-+		if (IS_ERR(con)) {
-+			dev_err(dev, "missing hifsys node\n");
-+			return PTR_ERR(con);
-+		}
-+
-+		mask = HIFSYS_DMA_AG_MAP_PCIE0 | HIFSYS_DMA_AG_MAP_PCIE1;
-+		regmap_update_bits(con, HIFSYS_DMA_AG_MAP, mask, mask);
-+	}
-+
- 	slot = of_get_pci_domain_nr(dev->of_node);
- 	if (slot < 0) {
- 		for_each_available_child_of_node(node, child) {
diff --git a/target/linux/mediatek/patches-5.15/721-dts-mt7622-mediatek-fix-300mhz.patch b/target/linux/mediatek/patches-5.15/721-dts-mt7622-mediatek-fix-300mhz.patch
deleted file mode 100644
index f9a5fdbd0d837d..00000000000000
--- a/target/linux/mediatek/patches-5.15/721-dts-mt7622-mediatek-fix-300mhz.patch
+++ /dev/null
@@ -1,27 +0,0 @@
-From: Jip de Beer <gpk6x3591g0l@opayq.com>
-Date: Sun, 9 Jan 2022 13:14:04 +0100
-Subject: [PATCH] mediatek mt7622: fix 300mhz typo in dts
-
-The lowest frequency should be 300MHz, since that is the label
-assigned to the OPP in the mt7622.dtsi device tree, while there is one
-missing zero in the actual value.
-
-To be clear, the lowest frequency should be 300MHz instead of 30MHz.
-
-As mentioned @dangowrt on the OpenWrt forum there is no benefit in
-leaving 30MHz as the lowest frequency.
-
-Signed-off-by: Jip de Beer <gpk6x3591g0l@opayq.com>
-Signed-off-by: Fritz D. Ansel <fdansel@yandex.ru>
----
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -24,7 +24,7 @@
- 		compatible = "operating-points-v2";
- 		opp-shared;
- 		opp-300000000 {
--			opp-hz = /bits/ 64 <30000000>;
-+			opp-hz = /bits/ 64 <300000000>;
- 			opp-microvolt = <950000>;
- 		};
- 
diff --git a/target/linux/mediatek/patches-5.15/722-remove-300Hz-to-prevent-freeze.patch b/target/linux/mediatek/patches-5.15/722-remove-300Hz-to-prevent-freeze.patch
deleted file mode 100644
index 52069496ca822b..00000000000000
--- a/target/linux/mediatek/patches-5.15/722-remove-300Hz-to-prevent-freeze.patch
+++ /dev/null
@@ -1,25 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -23,11 +23,17 @@
- 	cpu_opp_table: opp-table {
- 		compatible = "operating-points-v2";
- 		opp-shared;
--		opp-300000000 {
--			opp-hz = /bits/ 64 <300000000>;
--			opp-microvolt = <950000>;
--		};
--
-+		/* Due to the bug described at the link below, remove the 300 MHz clock to avoid a low
-+		 * voltage condition that can cause a hang when rebooting the RT3200/E8450.
-+		 *
-+		 * https://forum.openwrt.org/t/belkin-rt3200-linksys-e8450-wifi-ax-discussion/94302/1490
-+		 *
-+		 * opp-300000000 {
-+		 *	opp-hz = /bits/ 64 <300000000>;
-+		 *	opp-microvolt = <950000>;
-+		 * };
-+		 *
-+		 */
- 		opp-437500000 {
- 			opp-hz = /bits/ 64 <437500000>;
- 			opp-microvolt = <1000000>;
diff --git a/target/linux/mediatek/patches-5.15/730-v6.5-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch b/target/linux/mediatek/patches-5.15/730-v6.5-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch
deleted file mode 100644
index 72ad2a9846485f..00000000000000
--- a/target/linux/mediatek/patches-5.15/730-v6.5-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch
+++ /dev/null
@@ -1,1204 +0,0 @@
-From 98c485eaf509bc0e2a85f9b58d17cd501f274c4e Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Sun, 11 Jun 2023 00:48:10 +0100
-Subject: [PATCH] net: phy: add driver for MediaTek SoC built-in GE PHYs
-
-Some of MediaTek's Filogic SoCs come with built-in gigabit Ethernet
-PHYs which require calibration data from the SoC's efuse.
-Despite the similar design the driver doesn't share any code with the
-existing mediatek-ge.c.
-Add support for such PHYs by introducing a new driver with basic
-support for MediaTek SoCs MT7981 and MT7988 built-in 1GE PHYs.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Reviewed-by: Andrew Lunn <andrew@lunn.ch>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- MAINTAINERS                       |    9 +
- drivers/net/phy/Kconfig           |   12 +
- drivers/net/phy/Makefile          |    1 +
- drivers/net/phy/mediatek-ge-soc.c | 1116 +++++++++++++++++++++++++++++
- drivers/net/phy/mediatek-ge.c     |    3 +-
- 5 files changed, 1140 insertions(+), 1 deletion(-)
- create mode 100644 drivers/net/phy/mediatek-ge-soc.c
-
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -11791,6 +11791,15 @@ S:	Maintained
- F:	drivers/net/pcs/pcs-mtk-lynxi.c
- F:	include/linux/pcs/pcs-mtk-lynxi.h
- 
-+MEDIATEK ETHERNET PHY DRIVERS
-+M:	Daniel Golle <daniel@makrotopia.org>
-+M:	Qingfang Deng <dqfext@gmail.com>
-+M:	SkyLake Huang <SkyLake.Huang@mediatek.com>
-+L:	netdev@vger.kernel.org
-+S:	Maintained
-+F:	drivers/net/phy/mediatek-ge-soc.c
-+F:	drivers/net/phy/mediatek-ge.c
-+
- MEDIATEK I2C CONTROLLER DRIVER
- M:	Qii Wang <qii.wang@mediatek.com>
- L:	linux-i2c@vger.kernel.org
---- a/drivers/net/phy/Kconfig
-+++ b/drivers/net/phy/Kconfig
-@@ -290,6 +290,18 @@ config MEDIATEK_GE_PHY
- 	help
- 	  Supports the MediaTek Gigabit Ethernet PHYs.
- 
-+config MEDIATEK_GE_SOC_PHY
-+	tristate "MediaTek SoC Ethernet PHYs"
-+	depends on (ARM64 && ARCH_MEDIATEK) || COMPILE_TEST
-+	select NVMEM_MTK_EFUSE
-+	help
-+	  Supports MediaTek SoC built-in Gigabit Ethernet PHYs.
-+
-+	  Include support for built-in Ethernet PHYs which are present in
-+	  the MT7981 and MT7988 SoCs. These PHYs need calibration data
-+	  present in the SoCs efuse and will dynamically calibrate VCM
-+	  (common-mode voltage) during startup.
-+
- config MICREL_PHY
- 	tristate "Micrel PHYs"
- 	help
---- a/drivers/net/phy/Makefile
-+++ b/drivers/net/phy/Makefile
-@@ -77,6 +77,7 @@ obj-$(CONFIG_MARVELL_PHY)	+= marvell.o
- obj-$(CONFIG_MARVELL_88X2222_PHY)	+= marvell-88x2222.o
- obj-$(CONFIG_MAXLINEAR_GPHY)	+= mxl-gpy.o
- obj-$(CONFIG_MEDIATEK_GE_PHY)	+= mediatek-ge.o
-+obj-$(CONFIG_MEDIATEK_GE_SOC_PHY)	+= mediatek-ge-soc.o
- obj-$(CONFIG_MESON_GXL_PHY)	+= meson-gxl.o
- obj-$(CONFIG_MICREL_KS8995MA)	+= spi_ks8995.o
- obj-$(CONFIG_MICREL_PHY)	+= micrel.o
---- /dev/null
-+++ b/drivers/net/phy/mediatek-ge-soc.c
-@@ -0,0 +1,1116 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+#include <linux/bitfield.h>
-+#include <linux/module.h>
-+#include <linux/nvmem-consumer.h>
-+#include <linux/of_address.h>
-+#include <linux/of_platform.h>
-+#include <linux/pinctrl/consumer.h>
-+#include <linux/phy.h>
-+
-+#define MTK_GPHY_ID_MT7981			0x03a29461
-+#define MTK_GPHY_ID_MT7988			0x03a29481
-+
-+#define MTK_EXT_PAGE_ACCESS			0x1f
-+#define MTK_PHY_PAGE_STANDARD			0x0000
-+#define MTK_PHY_PAGE_EXTENDED_3			0x0003
-+
-+#define MTK_PHY_LPI_REG_14			0x14
-+#define MTK_PHY_LPI_WAKE_TIMER_1000_MASK	GENMASK(8, 0)
-+
-+#define MTK_PHY_LPI_REG_1c			0x1c
-+#define MTK_PHY_SMI_DET_ON_THRESH_MASK		GENMASK(13, 8)
-+
-+#define MTK_PHY_PAGE_EXTENDED_2A30		0x2a30
-+#define MTK_PHY_PAGE_EXTENDED_52B5		0x52b5
-+
-+#define ANALOG_INTERNAL_OPERATION_MAX_US	20
-+#define TXRESERVE_MIN				0
-+#define TXRESERVE_MAX				7
-+
-+#define MTK_PHY_ANARG_RG			0x10
-+#define   MTK_PHY_TCLKOFFSET_MASK		GENMASK(12, 8)
-+
-+/* Registers on MDIO_MMD_VEND1 */
-+#define MTK_PHY_TXVLD_DA_RG			0x12
-+#define   MTK_PHY_DA_TX_I2MPB_A_GBE_MASK	GENMASK(15, 10)
-+#define   MTK_PHY_DA_TX_I2MPB_A_TBT_MASK	GENMASK(5, 0)
-+
-+#define MTK_PHY_TX_I2MPB_TEST_MODE_A2		0x16
-+#define   MTK_PHY_DA_TX_I2MPB_A_HBT_MASK	GENMASK(15, 10)
-+#define   MTK_PHY_DA_TX_I2MPB_A_TST_MASK	GENMASK(5, 0)
-+
-+#define MTK_PHY_TX_I2MPB_TEST_MODE_B1		0x17
-+#define   MTK_PHY_DA_TX_I2MPB_B_GBE_MASK	GENMASK(13, 8)
-+#define   MTK_PHY_DA_TX_I2MPB_B_TBT_MASK	GENMASK(5, 0)
-+
-+#define MTK_PHY_TX_I2MPB_TEST_MODE_B2		0x18
-+#define   MTK_PHY_DA_TX_I2MPB_B_HBT_MASK	GENMASK(13, 8)
-+#define   MTK_PHY_DA_TX_I2MPB_B_TST_MASK	GENMASK(5, 0)
-+
-+#define MTK_PHY_TX_I2MPB_TEST_MODE_C1		0x19
-+#define   MTK_PHY_DA_TX_I2MPB_C_GBE_MASK	GENMASK(13, 8)
-+#define   MTK_PHY_DA_TX_I2MPB_C_TBT_MASK	GENMASK(5, 0)
-+
-+#define MTK_PHY_TX_I2MPB_TEST_MODE_C2		0x20
-+#define   MTK_PHY_DA_TX_I2MPB_C_HBT_MASK	GENMASK(13, 8)
-+#define   MTK_PHY_DA_TX_I2MPB_C_TST_MASK	GENMASK(5, 0)
-+
-+#define MTK_PHY_TX_I2MPB_TEST_MODE_D1		0x21
-+#define   MTK_PHY_DA_TX_I2MPB_D_GBE_MASK	GENMASK(13, 8)
-+#define   MTK_PHY_DA_TX_I2MPB_D_TBT_MASK	GENMASK(5, 0)
-+
-+#define MTK_PHY_TX_I2MPB_TEST_MODE_D2		0x22
-+#define   MTK_PHY_DA_TX_I2MPB_D_HBT_MASK	GENMASK(13, 8)
-+#define   MTK_PHY_DA_TX_I2MPB_D_TST_MASK	GENMASK(5, 0)
-+
-+#define MTK_PHY_RXADC_CTRL_RG7			0xc6
-+#define   MTK_PHY_DA_AD_BUF_BIAS_LP_MASK	GENMASK(9, 8)
-+
-+#define MTK_PHY_RXADC_CTRL_RG9			0xc8
-+#define   MTK_PHY_DA_RX_PSBN_TBT_MASK		GENMASK(14, 12)
-+#define   MTK_PHY_DA_RX_PSBN_HBT_MASK		GENMASK(10, 8)
-+#define   MTK_PHY_DA_RX_PSBN_GBE_MASK		GENMASK(6, 4)
-+#define   MTK_PHY_DA_RX_PSBN_LP_MASK		GENMASK(2, 0)
-+
-+#define MTK_PHY_LDO_OUTPUT_V			0xd7
-+
-+#define MTK_PHY_RG_ANA_CAL_RG0			0xdb
-+#define   MTK_PHY_RG_CAL_CKINV			BIT(12)
-+#define   MTK_PHY_RG_ANA_CALEN			BIT(8)
-+#define   MTK_PHY_RG_ZCALEN_A			BIT(0)
-+
-+#define MTK_PHY_RG_ANA_CAL_RG1			0xdc
-+#define   MTK_PHY_RG_ZCALEN_B			BIT(12)
-+#define   MTK_PHY_RG_ZCALEN_C			BIT(8)
-+#define   MTK_PHY_RG_ZCALEN_D			BIT(4)
-+#define   MTK_PHY_RG_TXVOS_CALEN		BIT(0)
-+
-+#define MTK_PHY_RG_ANA_CAL_RG5			0xe0
-+#define   MTK_PHY_RG_REXT_TRIM_MASK		GENMASK(13, 8)
-+
-+#define MTK_PHY_RG_TX_FILTER			0xfe
-+
-+#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120	0x120
-+#define   MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK	GENMASK(12, 8)
-+#define   MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK	GENMASK(4, 0)
-+
-+#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122	0x122
-+#define   MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK	GENMASK(7, 0)
-+
-+#define MTK_PHY_RG_TESTMUX_ADC_CTRL		0x144
-+#define   MTK_PHY_RG_TXEN_DIG_MASK		GENMASK(5, 5)
-+
-+#define MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B		0x172
-+#define   MTK_PHY_CR_TX_AMP_OFFSET_A_MASK	GENMASK(13, 8)
-+#define   MTK_PHY_CR_TX_AMP_OFFSET_B_MASK	GENMASK(6, 0)
-+
-+#define MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D		0x173
-+#define   MTK_PHY_CR_TX_AMP_OFFSET_C_MASK	GENMASK(13, 8)
-+#define   MTK_PHY_CR_TX_AMP_OFFSET_D_MASK	GENMASK(6, 0)
-+
-+#define MTK_PHY_RG_AD_CAL_COMP			0x17a
-+#define   MTK_PHY_AD_CAL_COMP_OUT_SHIFT		(8)
-+
-+#define MTK_PHY_RG_AD_CAL_CLK			0x17b
-+#define   MTK_PHY_DA_CAL_CLK			BIT(0)
-+
-+#define MTK_PHY_RG_AD_CALIN			0x17c
-+#define   MTK_PHY_DA_CALIN_FLAG			BIT(0)
-+
-+#define MTK_PHY_RG_DASN_DAC_IN0_A		0x17d
-+#define   MTK_PHY_DASN_DAC_IN0_A_MASK		GENMASK(9, 0)
-+
-+#define MTK_PHY_RG_DASN_DAC_IN0_B		0x17e
-+#define   MTK_PHY_DASN_DAC_IN0_B_MASK		GENMASK(9, 0)
-+
-+#define MTK_PHY_RG_DASN_DAC_IN0_C		0x17f
-+#define   MTK_PHY_DASN_DAC_IN0_C_MASK		GENMASK(9, 0)
-+
-+#define MTK_PHY_RG_DASN_DAC_IN0_D		0x180
-+#define   MTK_PHY_DASN_DAC_IN0_D_MASK		GENMASK(9, 0)
-+
-+#define MTK_PHY_RG_DASN_DAC_IN1_A		0x181
-+#define   MTK_PHY_DASN_DAC_IN1_A_MASK		GENMASK(9, 0)
-+
-+#define MTK_PHY_RG_DASN_DAC_IN1_B		0x182
-+#define   MTK_PHY_DASN_DAC_IN1_B_MASK		GENMASK(9, 0)
-+
-+#define MTK_PHY_RG_DASN_DAC_IN1_C		0x183
-+#define   MTK_PHY_DASN_DAC_IN1_C_MASK		GENMASK(9, 0)
-+
-+#define MTK_PHY_RG_DASN_DAC_IN1_D		0x184
-+#define   MTK_PHY_DASN_DAC_IN1_D_MASK		GENMASK(9, 0)
-+
-+#define MTK_PHY_RG_DEV1E_REG19b			0x19b
-+#define   MTK_PHY_BYPASS_DSP_LPI_READY		BIT(8)
-+
-+#define MTK_PHY_RG_LP_IIR2_K1_L			0x22a
-+#define MTK_PHY_RG_LP_IIR2_K1_U			0x22b
-+#define MTK_PHY_RG_LP_IIR2_K2_L			0x22c
-+#define MTK_PHY_RG_LP_IIR2_K2_U			0x22d
-+#define MTK_PHY_RG_LP_IIR2_K3_L			0x22e
-+#define MTK_PHY_RG_LP_IIR2_K3_U			0x22f
-+#define MTK_PHY_RG_LP_IIR2_K4_L			0x230
-+#define MTK_PHY_RG_LP_IIR2_K4_U			0x231
-+#define MTK_PHY_RG_LP_IIR2_K5_L			0x232
-+#define MTK_PHY_RG_LP_IIR2_K5_U			0x233
-+
-+#define MTK_PHY_RG_DEV1E_REG234			0x234
-+#define   MTK_PHY_TR_OPEN_LOOP_EN_MASK		GENMASK(0, 0)
-+#define   MTK_PHY_LPF_X_AVERAGE_MASK		GENMASK(7, 4)
-+#define   MTK_PHY_TR_LP_IIR_EEE_EN		BIT(12)
-+
-+#define MTK_PHY_RG_LPF_CNT_VAL			0x235
-+
-+#define MTK_PHY_RG_DEV1E_REG238			0x238
-+#define   MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK	GENMASK(8, 0)
-+#define   MTK_PHY_LPI_SLV_SEND_TX_EN		BIT(12)
-+
-+#define MTK_PHY_RG_DEV1E_REG239			0x239
-+#define   MTK_PHY_LPI_SEND_LOC_TIMER_MASK	GENMASK(8, 0)
-+#define   MTK_PHY_LPI_TXPCS_LOC_RCV		BIT(12)
-+
-+#define MTK_PHY_RG_DEV1E_REG27C			0x27c
-+#define   MTK_PHY_VGASTATE_FFE_THR_ST1_MASK	GENMASK(12, 8)
-+#define MTK_PHY_RG_DEV1E_REG27D			0x27d
-+#define   MTK_PHY_VGASTATE_FFE_THR_ST2_MASK	GENMASK(4, 0)
-+
-+#define MTK_PHY_RG_DEV1E_REG2C7			0x2c7
-+#define   MTK_PHY_MAX_GAIN_MASK			GENMASK(4, 0)
-+#define   MTK_PHY_MIN_GAIN_MASK			GENMASK(12, 8)
-+
-+#define MTK_PHY_RG_DEV1E_REG2D1			0x2d1
-+#define   MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK	GENMASK(7, 0)
-+#define   MTK_PHY_LPI_SKIP_SD_SLV_TR		BIT(8)
-+#define   MTK_PHY_LPI_TR_READY			BIT(9)
-+#define   MTK_PHY_LPI_VCO_EEE_STG0_EN		BIT(10)
-+
-+#define MTK_PHY_RG_DEV1E_REG323			0x323
-+#define   MTK_PHY_EEE_WAKE_MAS_INT_DC		BIT(0)
-+#define   MTK_PHY_EEE_WAKE_SLV_INT_DC		BIT(4)
-+
-+#define MTK_PHY_RG_DEV1E_REG324			0x324
-+#define   MTK_PHY_SMI_DETCNT_MAX_MASK		GENMASK(5, 0)
-+#define   MTK_PHY_SMI_DET_MAX_EN		BIT(8)
-+
-+#define MTK_PHY_RG_DEV1E_REG326			0x326
-+#define   MTK_PHY_LPI_MODE_SD_ON		BIT(0)
-+#define   MTK_PHY_RESET_RANDUPD_CNT		BIT(1)
-+#define   MTK_PHY_TREC_UPDATE_ENAB_CLR		BIT(2)
-+#define   MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF	BIT(4)
-+#define   MTK_PHY_TR_READY_SKIP_AFE_WAKEUP	BIT(5)
-+
-+#define MTK_PHY_LDO_PUMP_EN_PAIRAB		0x502
-+#define MTK_PHY_LDO_PUMP_EN_PAIRCD		0x503
-+
-+#define MTK_PHY_DA_TX_R50_PAIR_A		0x53d
-+#define MTK_PHY_DA_TX_R50_PAIR_B		0x53e
-+#define MTK_PHY_DA_TX_R50_PAIR_C		0x53f
-+#define MTK_PHY_DA_TX_R50_PAIR_D		0x540
-+
-+#define MTK_PHY_RG_BG_RASEL			0x115
-+#define   MTK_PHY_RG_BG_RASEL_MASK		GENMASK(2, 0)
-+
-+/* These macro privides efuse parsing for internal phy. */
-+#define EFS_DA_TX_I2MPB_A(x)			(((x) >> 0) & GENMASK(5, 0))
-+#define EFS_DA_TX_I2MPB_B(x)			(((x) >> 6) & GENMASK(5, 0))
-+#define EFS_DA_TX_I2MPB_C(x)			(((x) >> 12) & GENMASK(5, 0))
-+#define EFS_DA_TX_I2MPB_D(x)			(((x) >> 18) & GENMASK(5, 0))
-+#define EFS_DA_TX_AMP_OFFSET_A(x)		(((x) >> 24) & GENMASK(5, 0))
-+
-+#define EFS_DA_TX_AMP_OFFSET_B(x)		(((x) >> 0) & GENMASK(5, 0))
-+#define EFS_DA_TX_AMP_OFFSET_C(x)		(((x) >> 6) & GENMASK(5, 0))
-+#define EFS_DA_TX_AMP_OFFSET_D(x)		(((x) >> 12) & GENMASK(5, 0))
-+#define EFS_DA_TX_R50_A(x)			(((x) >> 18) & GENMASK(5, 0))
-+#define EFS_DA_TX_R50_B(x)			(((x) >> 24) & GENMASK(5, 0))
-+
-+#define EFS_DA_TX_R50_C(x)			(((x) >> 0) & GENMASK(5, 0))
-+#define EFS_DA_TX_R50_D(x)			(((x) >> 6) & GENMASK(5, 0))
-+
-+#define EFS_RG_BG_RASEL(x)			(((x) >> 4) & GENMASK(2, 0))
-+#define EFS_RG_REXT_TRIM(x)			(((x) >> 7) & GENMASK(5, 0))
-+
-+enum {
-+	NO_PAIR,
-+	PAIR_A,
-+	PAIR_B,
-+	PAIR_C,
-+	PAIR_D,
-+};
-+
-+enum {
-+	GPHY_PORT0,
-+	GPHY_PORT1,
-+	GPHY_PORT2,
-+	GPHY_PORT3,
-+};
-+
-+enum calibration_mode {
-+	EFUSE_K,
-+	SW_K
-+};
-+
-+enum CAL_ITEM {
-+	REXT,
-+	TX_OFFSET,
-+	TX_AMP,
-+	TX_R50,
-+	TX_VCM
-+};
-+
-+enum CAL_MODE {
-+	EFUSE_M,
-+	SW_M
-+};
-+
-+static int mtk_socphy_read_page(struct phy_device *phydev)
-+{
-+	return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
-+}
-+
-+static int mtk_socphy_write_page(struct phy_device *phydev, int page)
-+{
-+	return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page);
-+}
-+
-+/* One calibration cycle consists of:
-+ * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high
-+ *   until AD_CAL_COMP is ready to output calibration result.
-+ * 2.Wait until DA_CAL_CLK is available.
-+ * 3.Fetch AD_CAL_COMP_OUT.
-+ */
-+static int cal_cycle(struct phy_device *phydev, int devad,
-+		     u32 regnum, u16 mask, u16 cal_val)
-+{
-+	int reg_val;
-+	int ret;
-+
-+	phy_modify_mmd(phydev, devad, regnum,
-+		       mask, cal_val);
-+	phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN,
-+			 MTK_PHY_DA_CALIN_FLAG);
-+
-+	ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
-+					MTK_PHY_RG_AD_CAL_CLK, reg_val,
-+					reg_val & MTK_PHY_DA_CAL_CLK, 500,
-+					ANALOG_INTERNAL_OPERATION_MAX_US, false);
-+	if (ret) {
-+		phydev_err(phydev, "Calibration cycle timeout\n");
-+		return ret;
-+	}
-+
-+	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN,
-+			   MTK_PHY_DA_CALIN_FLAG);
-+	ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP) >>
-+			   MTK_PHY_AD_CAL_COMP_OUT_SHIFT;
-+	phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret);
-+
-+	return ret;
-+}
-+
-+static int rext_fill_result(struct phy_device *phydev, u16 *buf)
-+{
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5,
-+		       MTK_PHY_RG_REXT_TRIM_MASK, buf[0] << 8);
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_BG_RASEL,
-+		       MTK_PHY_RG_BG_RASEL_MASK, buf[1]);
-+
-+	return 0;
-+}
-+
-+static int rext_cal_efuse(struct phy_device *phydev, u32 *buf)
-+{
-+	u16 rext_cal_val[2];
-+
-+	rext_cal_val[0] = EFS_RG_REXT_TRIM(buf[3]);
-+	rext_cal_val[1] = EFS_RG_BG_RASEL(buf[3]);
-+	rext_fill_result(phydev, rext_cal_val);
-+
-+	return 0;
-+}
-+
-+static int tx_offset_fill_result(struct phy_device *phydev, u16 *buf)
-+{
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B,
-+		       MTK_PHY_CR_TX_AMP_OFFSET_A_MASK, buf[0] << 8);
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B,
-+		       MTK_PHY_CR_TX_AMP_OFFSET_B_MASK, buf[1]);
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D,
-+		       MTK_PHY_CR_TX_AMP_OFFSET_C_MASK, buf[2] << 8);
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D,
-+		       MTK_PHY_CR_TX_AMP_OFFSET_D_MASK, buf[3]);
-+
-+	return 0;
-+}
-+
-+static int tx_offset_cal_efuse(struct phy_device *phydev, u32 *buf)
-+{
-+	u16 tx_offset_cal_val[4];
-+
-+	tx_offset_cal_val[0] = EFS_DA_TX_AMP_OFFSET_A(buf[0]);
-+	tx_offset_cal_val[1] = EFS_DA_TX_AMP_OFFSET_B(buf[1]);
-+	tx_offset_cal_val[2] = EFS_DA_TX_AMP_OFFSET_C(buf[1]);
-+	tx_offset_cal_val[3] = EFS_DA_TX_AMP_OFFSET_D(buf[1]);
-+
-+	tx_offset_fill_result(phydev, tx_offset_cal_val);
-+
-+	return 0;
-+}
-+
-+static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf)
-+{
-+	int i;
-+	int bias[16] = {};
-+	const int vals_9461[16] = { 7, 1, 4, 7,
-+				    7, 1, 4, 7,
-+				    7, 1, 4, 7,
-+				    7, 1, 4, 7 };
-+	const int vals_9481[16] = { 10, 6, 6, 10,
-+				    10, 6, 6, 10,
-+				    10, 6, 6, 10,
-+				    10, 6, 6, 10 };
-+	switch (phydev->drv->phy_id) {
-+	case MTK_GPHY_ID_MT7981:
-+		/* We add some calibration to efuse values
-+		 * due to board level influence.
-+		 * GBE: +7, TBT: +1, HBT: +4, TST: +7
-+		 */
-+		memcpy(bias, (const void *)vals_9461, sizeof(bias));
-+		break;
-+	case MTK_GPHY_ID_MT7988:
-+		memcpy(bias, (const void *)vals_9481, sizeof(bias));
-+		break;
-+	}
-+
-+	/* Prevent overflow */
-+	for (i = 0; i < 12; i++) {
-+		if (buf[i >> 2] + bias[i] > 63) {
-+			buf[i >> 2] = 63;
-+			bias[i] = 0;
-+		}
-+	}
-+
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG,
-+		       MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, (buf[0] + bias[0]) << 10);
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG,
-+		       MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, buf[0] + bias[1]);
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2,
-+		       MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, (buf[0] + bias[2]) << 10);
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2,
-+		       MTK_PHY_DA_TX_I2MPB_A_TST_MASK, buf[0] + bias[3]);
-+
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1,
-+		       MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, (buf[1] + bias[4]) << 8);
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1,
-+		       MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, buf[1] + bias[5]);
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2,
-+		       MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, (buf[1] + bias[6]) << 8);
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2,
-+		       MTK_PHY_DA_TX_I2MPB_B_TST_MASK, buf[1] + bias[7]);
-+
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1,
-+		       MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, (buf[2] + bias[8]) << 8);
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1,
-+		       MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, buf[2] + bias[9]);
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2,
-+		       MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, (buf[2] + bias[10]) << 8);
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2,
-+		       MTK_PHY_DA_TX_I2MPB_C_TST_MASK, buf[2] + bias[11]);
-+
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1,
-+		       MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, (buf[3] + bias[12]) << 8);
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1,
-+		       MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, buf[3] + bias[13]);
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2,
-+		       MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, (buf[3] + bias[14]) << 8);
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2,
-+		       MTK_PHY_DA_TX_I2MPB_D_TST_MASK, buf[3] + bias[15]);
-+
-+	return 0;
-+}
-+
-+static int tx_amp_cal_efuse(struct phy_device *phydev, u32 *buf)
-+{
-+	u16 tx_amp_cal_val[4];
-+
-+	tx_amp_cal_val[0] = EFS_DA_TX_I2MPB_A(buf[0]);
-+	tx_amp_cal_val[1] = EFS_DA_TX_I2MPB_B(buf[0]);
-+	tx_amp_cal_val[2] = EFS_DA_TX_I2MPB_C(buf[0]);
-+	tx_amp_cal_val[3] = EFS_DA_TX_I2MPB_D(buf[0]);
-+	tx_amp_fill_result(phydev, tx_amp_cal_val);
-+
-+	return 0;
-+}
-+
-+static int tx_r50_fill_result(struct phy_device *phydev, u16 tx_r50_cal_val,
-+			      u8 txg_calen_x)
-+{
-+	int bias = 0;
-+	u16 reg, val;
-+
-+	if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988)
-+		bias = -2;
-+
-+	val = clamp_val(bias + tx_r50_cal_val, 0, 63);
-+
-+	switch (txg_calen_x) {
-+	case PAIR_A:
-+		reg = MTK_PHY_DA_TX_R50_PAIR_A;
-+		break;
-+	case PAIR_B:
-+		reg = MTK_PHY_DA_TX_R50_PAIR_B;
-+		break;
-+	case PAIR_C:
-+		reg = MTK_PHY_DA_TX_R50_PAIR_C;
-+		break;
-+	case PAIR_D:
-+		reg = MTK_PHY_DA_TX_R50_PAIR_D;
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, val | val << 8);
-+
-+	return 0;
-+}
-+
-+static int tx_r50_cal_efuse(struct phy_device *phydev, u32 *buf,
-+			    u8 txg_calen_x)
-+{
-+	u16 tx_r50_cal_val;
-+
-+	switch (txg_calen_x) {
-+	case PAIR_A:
-+		tx_r50_cal_val = EFS_DA_TX_R50_A(buf[1]);
-+		break;
-+	case PAIR_B:
-+		tx_r50_cal_val = EFS_DA_TX_R50_B(buf[1]);
-+		break;
-+	case PAIR_C:
-+		tx_r50_cal_val = EFS_DA_TX_R50_C(buf[2]);
-+		break;
-+	case PAIR_D:
-+		tx_r50_cal_val = EFS_DA_TX_R50_D(buf[2]);
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+	tx_r50_fill_result(phydev, tx_r50_cal_val, txg_calen_x);
-+
-+	return 0;
-+}
-+
-+static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x)
-+{
-+	u8 lower_idx, upper_idx, txreserve_val;
-+	u8 lower_ret, upper_ret;
-+	int ret;
-+
-+	phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
-+			 MTK_PHY_RG_ANA_CALEN);
-+	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
-+			   MTK_PHY_RG_CAL_CKINV);
-+	phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
-+			 MTK_PHY_RG_TXVOS_CALEN);
-+
-+	switch (rg_txreserve_x) {
-+	case PAIR_A:
-+		phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
-+				   MTK_PHY_RG_DASN_DAC_IN0_A,
-+				   MTK_PHY_DASN_DAC_IN0_A_MASK);
-+		phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
-+				   MTK_PHY_RG_DASN_DAC_IN1_A,
-+				   MTK_PHY_DASN_DAC_IN1_A_MASK);
-+		phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
-+				 MTK_PHY_RG_ANA_CAL_RG0,
-+				 MTK_PHY_RG_ZCALEN_A);
-+		break;
-+	case PAIR_B:
-+		phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
-+				   MTK_PHY_RG_DASN_DAC_IN0_B,
-+				   MTK_PHY_DASN_DAC_IN0_B_MASK);
-+		phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
-+				   MTK_PHY_RG_DASN_DAC_IN1_B,
-+				   MTK_PHY_DASN_DAC_IN1_B_MASK);
-+		phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
-+				 MTK_PHY_RG_ANA_CAL_RG1,
-+				 MTK_PHY_RG_ZCALEN_B);
-+		break;
-+	case PAIR_C:
-+		phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
-+				   MTK_PHY_RG_DASN_DAC_IN0_C,
-+				   MTK_PHY_DASN_DAC_IN0_C_MASK);
-+		phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
-+				   MTK_PHY_RG_DASN_DAC_IN1_C,
-+				   MTK_PHY_DASN_DAC_IN1_C_MASK);
-+		phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
-+				 MTK_PHY_RG_ANA_CAL_RG1,
-+				 MTK_PHY_RG_ZCALEN_C);
-+		break;
-+	case PAIR_D:
-+		phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
-+				   MTK_PHY_RG_DASN_DAC_IN0_D,
-+				   MTK_PHY_DASN_DAC_IN0_D_MASK);
-+		phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
-+				   MTK_PHY_RG_DASN_DAC_IN1_D,
-+				   MTK_PHY_DASN_DAC_IN1_D_MASK);
-+		phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
-+				 MTK_PHY_RG_ANA_CAL_RG1,
-+				 MTK_PHY_RG_ZCALEN_D);
-+		break;
-+	default:
-+		ret = -EINVAL;
-+		goto restore;
-+	}
-+
-+	lower_idx = TXRESERVE_MIN;
-+	upper_idx = TXRESERVE_MAX;
-+
-+	phydev_dbg(phydev, "Start TX-VCM SW cal.\n");
-+	while ((upper_idx - lower_idx) > 1) {
-+		txreserve_val = DIV_ROUND_CLOSEST(lower_idx + upper_idx, 2);
-+		ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
-+				MTK_PHY_DA_RX_PSBN_TBT_MASK |
-+				MTK_PHY_DA_RX_PSBN_HBT_MASK |
-+				MTK_PHY_DA_RX_PSBN_GBE_MASK |
-+				MTK_PHY_DA_RX_PSBN_LP_MASK,
-+				txreserve_val << 12 | txreserve_val << 8 |
-+				txreserve_val << 4 | txreserve_val);
-+		if (ret == 1) {
-+			upper_idx = txreserve_val;
-+			upper_ret = ret;
-+		} else if (ret == 0) {
-+			lower_idx = txreserve_val;
-+			lower_ret = ret;
-+		} else {
-+			goto restore;
-+		}
-+	}
-+
-+	if (lower_idx == TXRESERVE_MIN) {
-+		lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1,
-+				      MTK_PHY_RXADC_CTRL_RG9,
-+				      MTK_PHY_DA_RX_PSBN_TBT_MASK |
-+				      MTK_PHY_DA_RX_PSBN_HBT_MASK |
-+				      MTK_PHY_DA_RX_PSBN_GBE_MASK |
-+				      MTK_PHY_DA_RX_PSBN_LP_MASK,
-+				      lower_idx << 12 | lower_idx << 8 |
-+				      lower_idx << 4 | lower_idx);
-+		ret = lower_ret;
-+	} else if (upper_idx == TXRESERVE_MAX) {
-+		upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1,
-+				      MTK_PHY_RXADC_CTRL_RG9,
-+				      MTK_PHY_DA_RX_PSBN_TBT_MASK |
-+				      MTK_PHY_DA_RX_PSBN_HBT_MASK |
-+				      MTK_PHY_DA_RX_PSBN_GBE_MASK |
-+				      MTK_PHY_DA_RX_PSBN_LP_MASK,
-+				      upper_idx << 12 | upper_idx << 8 |
-+				      upper_idx << 4 | upper_idx);
-+		ret = upper_ret;
-+	}
-+	if (ret < 0)
-+		goto restore;
-+
-+	/* We calibrate TX-VCM in different logic. Check upper index and then
-+	 * lower index. If this calibration is valid, apply lower index's result.
-+	 */
-+	ret = upper_ret - lower_ret;
-+	if (ret == 1) {
-+		ret = 0;
-+		/* Make sure we use upper_idx in our calibration system */
-+		cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
-+			  MTK_PHY_DA_RX_PSBN_TBT_MASK |
-+			  MTK_PHY_DA_RX_PSBN_HBT_MASK |
-+			  MTK_PHY_DA_RX_PSBN_GBE_MASK |
-+			  MTK_PHY_DA_RX_PSBN_LP_MASK,
-+			  upper_idx << 12 | upper_idx << 8 |
-+			  upper_idx << 4 | upper_idx);
-+		phydev_dbg(phydev, "TX-VCM SW cal result: 0x%x\n", upper_idx);
-+	} else if (lower_idx == TXRESERVE_MIN && upper_ret == 1 &&
-+		   lower_ret == 1) {
-+		ret = 0;
-+		cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
-+			  MTK_PHY_DA_RX_PSBN_TBT_MASK |
-+			  MTK_PHY_DA_RX_PSBN_HBT_MASK |
-+			  MTK_PHY_DA_RX_PSBN_GBE_MASK |
-+			  MTK_PHY_DA_RX_PSBN_LP_MASK,
-+			  lower_idx << 12 | lower_idx << 8 |
-+			  lower_idx << 4 | lower_idx);
-+		phydev_warn(phydev, "TX-VCM SW cal result at low margin 0x%x\n",
-+			    lower_idx);
-+	} else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 &&
-+		   lower_ret == 0) {
-+		ret = 0;
-+		phydev_warn(phydev, "TX-VCM SW cal result at high margin 0x%x\n",
-+			    upper_idx);
-+	} else {
-+		ret = -EINVAL;
-+	}
-+
-+restore:
-+	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
-+			   MTK_PHY_RG_ANA_CALEN);
-+	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
-+			   MTK_PHY_RG_TXVOS_CALEN);
-+	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
-+			   MTK_PHY_RG_ZCALEN_A);
-+	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
-+			   MTK_PHY_RG_ZCALEN_B | MTK_PHY_RG_ZCALEN_C |
-+			   MTK_PHY_RG_ZCALEN_D);
-+
-+	return ret;
-+}
-+
-+static void mt798x_phy_common_finetune(struct phy_device *phydev)
-+{
-+	phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
-+	/* EnabRandUpdTrig = 1 */
-+	__phy_write(phydev, 0x11, 0x2f00);
-+	__phy_write(phydev, 0x12, 0xe);
-+	__phy_write(phydev, 0x10, 0x8fb0);
-+
-+	/* NormMseLoThresh = 85 */
-+	__phy_write(phydev, 0x11, 0x55a0);
-+	__phy_write(phydev, 0x12, 0x0);
-+	__phy_write(phydev, 0x10, 0x83aa);
-+
-+	/* TrFreeze = 0 */
-+	__phy_write(phydev, 0x11, 0x0);
-+	__phy_write(phydev, 0x12, 0x0);
-+	__phy_write(phydev, 0x10, 0x9686);
-+
-+	/* SSTrKp1000Slv = 5 */
-+	__phy_write(phydev, 0x11, 0xbaef);
-+	__phy_write(phydev, 0x12, 0x2e);
-+	__phy_write(phydev, 0x10, 0x968c);
-+
-+	/* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2,
-+	 * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2
-+	 */
-+	__phy_write(phydev, 0x11, 0xd10a);
-+	__phy_write(phydev, 0x12, 0x34);
-+	__phy_write(phydev, 0x10, 0x8f82);
-+
-+	/* VcoSlicerThreshBitsHigh */
-+	__phy_write(phydev, 0x11, 0x5555);
-+	__phy_write(phydev, 0x12, 0x55);
-+	__phy_write(phydev, 0x10, 0x8ec0);
-+	phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-+
-+	/* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
-+		       MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK,
-+		       BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9));
-+
-+	/* rg_tr_lpf_cnt_val = 512 */
-+	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200);
-+
-+	/* IIR2 related */
-+	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82);
-+	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0);
-+	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103);
-+	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0);
-+	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82);
-+	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0);
-+	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177);
-+	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3);
-+	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82);
-+	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe);
-+
-+	/* FFE peaking */
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C,
-+		       MTK_PHY_VGASTATE_FFE_THR_ST1_MASK, 0x1b << 8);
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D,
-+		       MTK_PHY_VGASTATE_FFE_THR_ST2_MASK, 0x1e);
-+
-+	/* Disable LDO pump */
-+	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0);
-+	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0);
-+	/* Adjust LDO output voltage */
-+	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222);
-+}
-+
-+static void mt7981_phy_finetune(struct phy_device *phydev)
-+{
-+	u16 val[8] = { 0x01ce, 0x01c1,
-+		       0x020f, 0x0202,
-+		       0x03d0, 0x03c0,
-+		       0x0013, 0x0005 };
-+	int i, k;
-+
-+	/* 100M eye finetune:
-+	 * Keep middle level of TX MLT3 shapper as default.
-+	 * Only change TX MLT3 overshoot level here.
-+	 */
-+	for (k = 0, i = 1; i < 12; i++) {
-+		if (i % 3 == 0)
-+			continue;
-+		phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]);
-+	}
-+
-+	phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
-+	/* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */
-+	__phy_write(phydev, 0x11, 0xc71);
-+	__phy_write(phydev, 0x12, 0xc);
-+	__phy_write(phydev, 0x10, 0x8fae);
-+
-+	/* ResetSyncOffset = 6 */
-+	__phy_write(phydev, 0x11, 0x600);
-+	__phy_write(phydev, 0x12, 0x0);
-+	__phy_write(phydev, 0x10, 0x8fc0);
-+
-+	/* VgaDecRate = 1 */
-+	__phy_write(phydev, 0x11, 0x4c2a);
-+	__phy_write(phydev, 0x12, 0x3e);
-+	__phy_write(phydev, 0x10, 0x8fa4);
-+
-+	/* FfeUpdGainForce = 4 */
-+	__phy_write(phydev, 0x11, 0x240);
-+	__phy_write(phydev, 0x12, 0x0);
-+	__phy_write(phydev, 0x10, 0x9680);
-+
-+	phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-+}
-+
-+static void mt7988_phy_finetune(struct phy_device *phydev)
-+{
-+	u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182,
-+			0x020d, 0x0206, 0x0384, 0x03d0,
-+			0x03c6, 0x030a, 0x0011, 0x0005 };
-+	int i;
-+
-+	/* Set default MLT3 shaper first */
-+	for (i = 0; i < 12; i++)
-+		phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[i]);
-+
-+	/* TCT finetune */
-+	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5);
-+
-+	/* Disable TX power saving */
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
-+		       MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8);
-+
-+	phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
-+
-+	/* SlvDSPreadyTime = 24, MasDSPreadyTime = 12 */
-+	__phy_write(phydev, 0x11, 0x671);
-+	__phy_write(phydev, 0x12, 0xc);
-+	__phy_write(phydev, 0x10, 0x8fae);
-+
-+	/* ResetSyncOffset = 5 */
-+	__phy_write(phydev, 0x11, 0x500);
-+	__phy_write(phydev, 0x12, 0x0);
-+	__phy_write(phydev, 0x10, 0x8fc0);
-+
-+	/* VgaDecRate is 1 at default on mt7988 */
-+
-+	phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-+
-+	phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_2A30);
-+	/* TxClkOffset = 2 */
-+	__phy_modify(phydev, MTK_PHY_ANARG_RG, MTK_PHY_TCLKOFFSET_MASK,
-+		     FIELD_PREP(MTK_PHY_TCLKOFFSET_MASK, 0x2));
-+	phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-+}
-+
-+static void mt798x_phy_eee(struct phy_device *phydev)
-+{
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1,
-+		       MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120,
-+		       MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK |
-+		       MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK,
-+		       FIELD_PREP(MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK, 0x0) |
-+		       FIELD_PREP(MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 0x14));
-+
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1,
-+		       MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122,
-+		       MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
-+		       FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
-+				  0xff));
-+
-+	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
-+			   MTK_PHY_RG_TESTMUX_ADC_CTRL,
-+			   MTK_PHY_RG_TXEN_DIG_MASK);
-+
-+	phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
-+			 MTK_PHY_RG_DEV1E_REG19b, MTK_PHY_BYPASS_DSP_LPI_READY);
-+
-+	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
-+			   MTK_PHY_RG_DEV1E_REG234, MTK_PHY_TR_LP_IIR_EEE_EN);
-+
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG238,
-+		       MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK |
-+		       MTK_PHY_LPI_SLV_SEND_TX_EN,
-+		       FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120));
-+
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239,
-+		       MTK_PHY_LPI_SEND_LOC_TIMER_MASK |
-+		       MTK_PHY_LPI_TXPCS_LOC_RCV,
-+		       FIELD_PREP(MTK_PHY_LPI_SEND_LOC_TIMER_MASK, 0x117));
-+
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7,
-+		       MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK,
-+		       FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) |
-+		       FIELD_PREP(MTK_PHY_MIN_GAIN_MASK, 0x13));
-+
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2D1,
-+		       MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK,
-+		       FIELD_PREP(MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK,
-+				  0x33) |
-+		       MTK_PHY_LPI_SKIP_SD_SLV_TR | MTK_PHY_LPI_TR_READY |
-+		       MTK_PHY_LPI_VCO_EEE_STG0_EN);
-+
-+	phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG323,
-+			 MTK_PHY_EEE_WAKE_MAS_INT_DC |
-+			 MTK_PHY_EEE_WAKE_SLV_INT_DC);
-+
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG324,
-+		       MTK_PHY_SMI_DETCNT_MAX_MASK,
-+		       FIELD_PREP(MTK_PHY_SMI_DETCNT_MAX_MASK, 0x3f) |
-+		       MTK_PHY_SMI_DET_MAX_EN);
-+
-+	phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG326,
-+			 MTK_PHY_LPI_MODE_SD_ON | MTK_PHY_RESET_RANDUPD_CNT |
-+			 MTK_PHY_TREC_UPDATE_ENAB_CLR |
-+			 MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF |
-+			 MTK_PHY_TR_READY_SKIP_AFE_WAKEUP);
-+
-+	phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
-+	/* Regsigdet_sel_1000 = 0 */
-+	__phy_write(phydev, 0x11, 0xb);
-+	__phy_write(phydev, 0x12, 0x0);
-+	__phy_write(phydev, 0x10, 0x9690);
-+
-+	/* REG_EEE_st2TrKf1000 = 3 */
-+	__phy_write(phydev, 0x11, 0x114f);
-+	__phy_write(phydev, 0x12, 0x2);
-+	__phy_write(phydev, 0x10, 0x969a);
-+
-+	/* RegEEE_slv_wake_tr_timer_tar = 6, RegEEE_slv_remtx_timer_tar = 20 */
-+	__phy_write(phydev, 0x11, 0x3028);
-+	__phy_write(phydev, 0x12, 0x0);
-+	__phy_write(phydev, 0x10, 0x969e);
-+
-+	/* RegEEE_slv_wake_int_timer_tar = 8 */
-+	__phy_write(phydev, 0x11, 0x5010);
-+	__phy_write(phydev, 0x12, 0x0);
-+	__phy_write(phydev, 0x10, 0x96a0);
-+
-+	/* RegEEE_trfreeze_timer2 = 586 */
-+	__phy_write(phydev, 0x11, 0x24a);
-+	__phy_write(phydev, 0x12, 0x0);
-+	__phy_write(phydev, 0x10, 0x96a8);
-+
-+	/* RegEEE100Stg1_tar = 16 */
-+	__phy_write(phydev, 0x11, 0x3210);
-+	__phy_write(phydev, 0x12, 0x0);
-+	__phy_write(phydev, 0x10, 0x96b8);
-+
-+	/* REGEEE_wake_slv_tr_wait_dfesigdet_en = 1 */
-+	__phy_write(phydev, 0x11, 0x1463);
-+	__phy_write(phydev, 0x12, 0x0);
-+	__phy_write(phydev, 0x10, 0x96ca);
-+
-+	/* DfeTailEnableVgaThresh1000 = 27 */
-+	__phy_write(phydev, 0x11, 0x36);
-+	__phy_write(phydev, 0x12, 0x0);
-+	__phy_write(phydev, 0x10, 0x8f80);
-+	phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-+
-+	phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3);
-+	__phy_modify(phydev, MTK_PHY_LPI_REG_14, MTK_PHY_LPI_WAKE_TIMER_1000_MASK,
-+		     FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 0x19c));
-+
-+	__phy_modify(phydev, MTK_PHY_LPI_REG_1c, MTK_PHY_SMI_DET_ON_THRESH_MASK,
-+		     FIELD_PREP(MTK_PHY_SMI_DET_ON_THRESH_MASK, 0xc));
-+	phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-+
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1,
-+		       MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122,
-+		       MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
-+		       FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 0xff));
-+}
-+
-+static int cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item,
-+		  u8 start_pair, u8 end_pair)
-+{
-+	u8 pair_n;
-+	int ret;
-+
-+	for (pair_n = start_pair; pair_n <= end_pair; pair_n++) {
-+		/* TX_OFFSET & TX_AMP have no SW calibration. */
-+		switch (cal_item) {
-+		case TX_VCM:
-+			ret = tx_vcm_cal_sw(phydev, pair_n);
-+			break;
-+		default:
-+			return -EINVAL;
-+		}
-+		if (ret)
-+			return ret;
-+	}
-+	return 0;
-+}
-+
-+static int cal_efuse(struct phy_device *phydev, enum CAL_ITEM cal_item,
-+		     u8 start_pair, u8 end_pair, u32 *buf)
-+{
-+	u8 pair_n;
-+	int ret;
-+
-+	for (pair_n = start_pair; pair_n <= end_pair; pair_n++) {
-+		/* TX_VCM has no efuse calibration. */
-+		switch (cal_item) {
-+		case REXT:
-+			ret = rext_cal_efuse(phydev, buf);
-+			break;
-+		case TX_OFFSET:
-+			ret = tx_offset_cal_efuse(phydev, buf);
-+			break;
-+		case TX_AMP:
-+			ret = tx_amp_cal_efuse(phydev, buf);
-+			break;
-+		case TX_R50:
-+			ret = tx_r50_cal_efuse(phydev, buf, pair_n);
-+			break;
-+		default:
-+			return -EINVAL;
-+		}
-+		if (ret)
-+			return ret;
-+	}
-+
-+	return 0;
-+}
-+
-+static int start_cal(struct phy_device *phydev, enum CAL_ITEM cal_item,
-+		     enum CAL_MODE cal_mode, u8 start_pair,
-+		     u8 end_pair, u32 *buf)
-+{
-+	int ret;
-+
-+	switch (cal_mode) {
-+	case EFUSE_M:
-+		ret = cal_efuse(phydev, cal_item, start_pair,
-+				end_pair, buf);
-+		break;
-+	case SW_M:
-+		ret = cal_sw(phydev, cal_item, start_pair, end_pair);
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	if (ret) {
-+		phydev_err(phydev, "cal %d failed\n", cal_item);
-+		return -EIO;
-+	}
-+
-+	return 0;
-+}
-+
-+static int mt798x_phy_calibration(struct phy_device *phydev)
-+{
-+	int ret = 0;
-+	u32 *buf;
-+	size_t len;
-+	struct nvmem_cell *cell;
-+
-+	cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data");
-+	if (IS_ERR(cell)) {
-+		if (PTR_ERR(cell) == -EPROBE_DEFER)
-+			return PTR_ERR(cell);
-+		return 0;
-+	}
-+
-+	buf = (u32 *)nvmem_cell_read(cell, &len);
-+	if (IS_ERR(buf))
-+		return PTR_ERR(buf);
-+	nvmem_cell_put(cell);
-+
-+	if (!buf[0] || !buf[1] || !buf[2] || !buf[3] || len < 4 * sizeof(u32)) {
-+		phydev_err(phydev, "invalid efuse data\n");
-+		ret = -EINVAL;
-+		goto out;
-+	}
-+
-+	ret = start_cal(phydev, REXT, EFUSE_M, NO_PAIR, NO_PAIR, buf);
-+	if (ret)
-+		goto out;
-+	ret = start_cal(phydev, TX_OFFSET, EFUSE_M, NO_PAIR, NO_PAIR, buf);
-+	if (ret)
-+		goto out;
-+	ret = start_cal(phydev, TX_AMP, EFUSE_M, NO_PAIR, NO_PAIR, buf);
-+	if (ret)
-+		goto out;
-+	ret = start_cal(phydev, TX_R50, EFUSE_M, PAIR_A, PAIR_D, buf);
-+	if (ret)
-+		goto out;
-+	ret = start_cal(phydev, TX_VCM, SW_M, PAIR_A, PAIR_A, buf);
-+	if (ret)
-+		goto out;
-+
-+out:
-+	kfree(buf);
-+	return ret;
-+}
-+
-+static int mt798x_phy_config_init(struct phy_device *phydev)
-+{
-+	switch (phydev->drv->phy_id) {
-+	case MTK_GPHY_ID_MT7981:
-+		mt7981_phy_finetune(phydev);
-+		break;
-+	case MTK_GPHY_ID_MT7988:
-+		mt7988_phy_finetune(phydev);
-+		break;
-+	}
-+
-+	mt798x_phy_common_finetune(phydev);
-+	mt798x_phy_eee(phydev);
-+
-+	return mt798x_phy_calibration(phydev);
-+}
-+
-+static struct phy_driver mtk_socphy_driver[] = {
-+	{
-+		PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981),
-+		.name		= "MediaTek MT7981 PHY",
-+		.config_init	= mt798x_phy_config_init,
-+		.config_intr	= genphy_no_config_intr,
-+		.handle_interrupt = genphy_handle_interrupt_no_ack,
-+		.probe		= mt798x_phy_calibration,
-+		.suspend	= genphy_suspend,
-+		.resume		= genphy_resume,
-+		.read_page	= mtk_socphy_read_page,
-+		.write_page	= mtk_socphy_write_page,
-+	},
-+	{
-+		PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988),
-+		.name		= "MediaTek MT7988 PHY",
-+		.config_init	= mt798x_phy_config_init,
-+		.config_intr	= genphy_no_config_intr,
-+		.handle_interrupt = genphy_handle_interrupt_no_ack,
-+		.probe		= mt798x_phy_calibration,
-+		.suspend	= genphy_suspend,
-+		.resume		= genphy_resume,
-+		.read_page	= mtk_socphy_read_page,
-+		.write_page	= mtk_socphy_write_page,
-+	},
-+};
-+
-+module_phy_driver(mtk_socphy_driver);
-+
-+static struct mdio_device_id __maybe_unused mtk_socphy_tbl[] = {
-+	{ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981) },
-+	{ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988) },
-+	{ }
-+};
-+
-+MODULE_DESCRIPTION("MediaTek SoC Gigabit Ethernet PHY driver");
-+MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
-+MODULE_AUTHOR("SkyLake Huang <SkyLake.Huang@mediatek.com>");
-+MODULE_LICENSE("GPL");
-+
-+MODULE_DEVICE_TABLE(mdio, mtk_socphy_tbl);
---- a/drivers/net/phy/mediatek-ge.c
-+++ b/drivers/net/phy/mediatek-ge.c
-@@ -136,7 +136,8 @@ static struct phy_driver mtk_gephy_drive
- module_phy_driver(mtk_gephy_driver);
- 
- static struct mdio_device_id __maybe_unused mtk_gephy_tbl[] = {
--	{ PHY_ID_MATCH_VENDOR(0x03a29400) },
-+	{ PHY_ID_MATCH_EXACT(0x03a29441) },
-+	{ PHY_ID_MATCH_EXACT(0x03a29412) },
- 	{ }
- };
- 
diff --git a/target/linux/mediatek/patches-5.15/731-net-phy-mediatek-ge-soc-initialize-MT7988-PHY-LEDs-d.patch b/target/linux/mediatek/patches-5.15/731-net-phy-mediatek-ge-soc-initialize-MT7988-PHY-LEDs-d.patch
deleted file mode 100644
index 83d0f26bf41824..00000000000000
--- a/target/linux/mediatek/patches-5.15/731-net-phy-mediatek-ge-soc-initialize-MT7988-PHY-LEDs-d.patch
+++ /dev/null
@@ -1,213 +0,0 @@
-From 5d2d78860f98eb5c03bc404eb024606878901ac8 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Tue, 13 Jun 2023 03:27:14 +0100
-Subject: [PATCH] net: phy: mediatek-ge-soc: initialize MT7988 PHY LEDs default
- state
-
-Initialize LEDs and set sane default values.
-Read boottrap register and apply LED polarities accordingly to get
-uniform behavior from all LEDs on MT7988.
-Requires syscon phandle 'mediatek,pio' present in parenting MDIO bus
-which should point to the syscon holding the boottrap register.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/net/phy/mediatek-ge-soc.c | 144 ++++++++++++++++++++++++++++--
- 1 file changed, 136 insertions(+), 8 deletions(-)
-
---- a/drivers/net/phy/mediatek-ge-soc.c
-+++ b/drivers/net/phy/mediatek-ge-soc.c
-@@ -1,11 +1,13 @@
- // SPDX-License-Identifier: GPL-2.0+
- #include <linux/bitfield.h>
-+#include <linux/mfd/syscon.h>
- #include <linux/module.h>
- #include <linux/nvmem-consumer.h>
- #include <linux/of_address.h>
- #include <linux/of_platform.h>
- #include <linux/pinctrl/consumer.h>
- #include <linux/phy.h>
-+#include <linux/regmap.h>
- 
- #define MTK_GPHY_ID_MT7981			0x03a29461
- #define MTK_GPHY_ID_MT7988			0x03a29481
-@@ -208,9 +210,40 @@
- #define MTK_PHY_DA_TX_R50_PAIR_C		0x53f
- #define MTK_PHY_DA_TX_R50_PAIR_D		0x540
- 
-+/* Registers on MDIO_MMD_VEND2 */
-+#define MTK_PHY_LED0_ON_CTRL			0x24
-+#define MTK_PHY_LED1_ON_CTRL			0x26
-+#define   MTK_PHY_LED_ON_MASK			GENMASK(6, 0)
-+#define   MTK_PHY_LED_ON_LINK1000		BIT(0)
-+#define   MTK_PHY_LED_ON_LINK100		BIT(1)
-+#define   MTK_PHY_LED_ON_LINK10			BIT(2)
-+#define   MTK_PHY_LED_ON_LINKDOWN		BIT(3)
-+#define   MTK_PHY_LED_ON_FDX			BIT(4) /* Full duplex */
-+#define   MTK_PHY_LED_ON_HDX			BIT(5) /* Half duplex */
-+#define   MTK_PHY_LED_FORCE_ON			BIT(6)
-+#define   MTK_PHY_LED_POLARITY			BIT(14)
-+#define   MTK_PHY_LED_ENABLE			BIT(15)
-+
-+#define MTK_PHY_LED0_BLINK_CTRL			0x25
-+#define MTK_PHY_LED1_BLINK_CTRL			0x27
-+#define   MTK_PHY_LED_1000TX			BIT(0)
-+#define   MTK_PHY_LED_1000RX			BIT(1)
-+#define   MTK_PHY_LED_100TX			BIT(2)
-+#define   MTK_PHY_LED_100RX			BIT(3)
-+#define   MTK_PHY_LED_10TX			BIT(4)
-+#define   MTK_PHY_LED_10RX			BIT(5)
-+#define   MTK_PHY_LED_COLLISION			BIT(6)
-+#define   MTK_PHY_LED_RX_CRC_ERR		BIT(7)
-+#define   MTK_PHY_LED_RX_IDLE_ERR		BIT(8)
-+#define   MTK_PHY_LED_FORCE_BLINK		BIT(9)
-+
- #define MTK_PHY_RG_BG_RASEL			0x115
- #define   MTK_PHY_RG_BG_RASEL_MASK		GENMASK(2, 0)
- 
-+/* Register in boottrap syscon defining the initial state of the 4 PHY LEDs */
-+#define RG_GPIO_MISC_TPBANK0			0x6f0
-+#define   RG_GPIO_MISC_TPBANK0_BOOTMODE		GENMASK(11, 8)
-+
- /* These macro privides efuse parsing for internal phy. */
- #define EFS_DA_TX_I2MPB_A(x)			(((x) >> 0) & GENMASK(5, 0))
- #define EFS_DA_TX_I2MPB_B(x)			(((x) >> 6) & GENMASK(5, 0))
-@@ -238,13 +271,6 @@ enum {
- 	PAIR_D,
- };
- 
--enum {
--	GPHY_PORT0,
--	GPHY_PORT1,
--	GPHY_PORT2,
--	GPHY_PORT3,
--};
--
- enum calibration_mode {
- 	EFUSE_K,
- 	SW_K
-@@ -263,6 +289,10 @@ enum CAL_MODE {
- 	SW_M
- };
- 
-+struct mtk_socphy_shared {
-+	u32			boottrap;
-+};
-+
- static int mtk_socphy_read_page(struct phy_device *phydev)
- {
- 	return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
-@@ -1073,6 +1103,104 @@ static int mt798x_phy_config_init(struct
- 	return mt798x_phy_calibration(phydev);
- }
- 
-+static int mt798x_phy_setup_led(struct phy_device *phydev, bool inverted)
-+{
-+	struct pinctrl *pinctrl;
-+	const u16 led_on_ctrl_defaults = MTK_PHY_LED_ENABLE      |
-+					 MTK_PHY_LED_ON_LINK1000 |
-+					 MTK_PHY_LED_ON_LINK100  |
-+					 MTK_PHY_LED_ON_LINK10;
-+	const u16 led_blink_defaults = MTK_PHY_LED_1000TX |
-+				       MTK_PHY_LED_1000RX |
-+				       MTK_PHY_LED_100TX  |
-+				       MTK_PHY_LED_100RX  |
-+				       MTK_PHY_LED_10TX   |
-+				       MTK_PHY_LED_10RX;
-+
-+	phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
-+		      led_on_ctrl_defaults ^
-+		      (inverted ? MTK_PHY_LED_POLARITY : 0));
-+
-+	phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL,
-+		      led_on_ctrl_defaults);
-+
-+	phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_BLINK_CTRL,
-+		      led_blink_defaults);
-+
-+	phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_BLINK_CTRL,
-+		      led_blink_defaults);
-+
-+	pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led");
-+	if (IS_ERR(pinctrl))
-+		dev_err(&phydev->mdio.bus->dev, "Failed to setup PHY LED\n");
-+
-+	return 0;
-+}
-+
-+static int mt7988_phy_probe_shared(struct phy_device *phydev)
-+{
-+	struct device_node *np = dev_of_node(&phydev->mdio.bus->dev);
-+	struct mtk_socphy_shared *priv = phydev->shared->priv;
-+	struct regmap *regmap;
-+	u32 reg;
-+	int ret;
-+
-+	/* The LED0 of the 4 PHYs in MT7988 are wired to SoC pins LED_A, LED_B,
-+	 * LED_C and LED_D respectively. At the same time those pins are used to
-+	 * bootstrap configuration of the reference clock source (LED_A),
-+	 * DRAM DDRx16b x2/x1 (LED_B) and boot device (LED_C, LED_D).
-+	 * In practise this is done using a LED and a resistor pulling the pin
-+	 * either to GND or to VIO.
-+	 * The detected value at boot time is accessible at run-time using the
-+	 * TPBANK0 register located in the gpio base of the pinctrl, in order
-+	 * to read it here it needs to be referenced by a phandle called
-+	 * 'mediatek,pio' in the MDIO bus hosting the PHY.
-+	 * The 4 bits in TPBANK0 are kept as package shared data and are used to
-+	 * set LED polarity for each of the LED0.
-+	 */
-+	regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,pio");
-+	if (IS_ERR(regmap))
-+		return PTR_ERR(regmap);
-+
-+	ret = regmap_read(regmap, RG_GPIO_MISC_TPBANK0, &reg);
-+	if (ret)
-+		return ret;
-+
-+	priv->boottrap = FIELD_GET(RG_GPIO_MISC_TPBANK0_BOOTMODE, reg);
-+
-+	return 0;
-+}
-+
-+static bool mt7988_phy_get_boottrap_polarity(struct phy_device *phydev)
-+{
-+	struct mtk_socphy_shared *priv = phydev->shared->priv;
-+
-+	if (priv->boottrap & BIT(phydev->mdio.addr))
-+		return false;
-+
-+	return true;
-+}
-+
-+static int mt7988_phy_probe(struct phy_device *phydev)
-+{
-+	int err;
-+
-+	err = devm_phy_package_join(&phydev->mdio.dev, phydev, 0,
-+				    sizeof(struct mtk_socphy_shared));
-+	if (err)
-+		return err;
-+
-+	if (phy_package_probe_once(phydev)) {
-+		err = mt7988_phy_probe_shared(phydev);
-+		if (err)
-+			return err;
-+	}
-+
-+	mt798x_phy_setup_led(phydev, mt7988_phy_get_boottrap_polarity(phydev));
-+
-+	return mt798x_phy_calibration(phydev);
-+}
-+
- static struct phy_driver mtk_socphy_driver[] = {
- 	{
- 		PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981),
-@@ -1092,7 +1220,7 @@ static struct phy_driver mtk_socphy_driv
- 		.config_init	= mt798x_phy_config_init,
- 		.config_intr	= genphy_no_config_intr,
- 		.handle_interrupt = genphy_handle_interrupt_no_ack,
--		.probe		= mt798x_phy_calibration,
-+		.probe		= mt7988_phy_probe,
- 		.suspend	= genphy_suspend,
- 		.resume		= genphy_resume,
- 		.read_page	= mtk_socphy_read_page,
diff --git a/target/linux/mediatek/patches-5.15/732-net-phy-mxl-gpy-don-t-use-SGMII-AN-if-using-phylink.patch b/target/linux/mediatek/patches-5.15/732-net-phy-mxl-gpy-don-t-use-SGMII-AN-if-using-phylink.patch
deleted file mode 100644
index 6df4436ab9b29b..00000000000000
--- a/target/linux/mediatek/patches-5.15/732-net-phy-mxl-gpy-don-t-use-SGMII-AN-if-using-phylink.patch
+++ /dev/null
@@ -1,63 +0,0 @@
-From a969b663c866129ed9eb217785a6574fbe826f1d Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Thu, 6 Apr 2023 23:36:50 +0100
-Subject: [PATCH] net: phy: mxl-gpy: don't use SGMII AN if using phylink
-
-MAC drivers using phylink expect SGMII in-band-status to be switched off
-when attached to a PHY. Make sure this is the case also for mxl-gpy which
-keeps SGMII in-band-status in case of SGMII interface mode is used.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/net/phy/mxl-gpy.c | 19 ++++++++++++++++---
- 1 file changed, 16 insertions(+), 3 deletions(-)
-
---- a/drivers/net/phy/mxl-gpy.c
-+++ b/drivers/net/phy/mxl-gpy.c
-@@ -195,8 +195,11 @@ static bool gpy_2500basex_chk(struct phy
- 
- 	phydev->speed = SPEED_2500;
- 	phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
--	phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
--		       VSPEC1_SGMII_CTRL_ANEN, 0);
-+
-+	if (!phydev->phylink)
-+		phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
-+			       VSPEC1_SGMII_CTRL_ANEN, 0);
-+
- 	return true;
- }
- 
-@@ -220,6 +223,14 @@ static int gpy_config_aneg(struct phy_de
- 	u32 adv;
- 	int ret;
- 
-+	/* Disable SGMII auto-negotiation if using phylink */
-+	if (phydev->phylink) {
-+		ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
-+				     VSPEC1_SGMII_CTRL_ANEN, 0);
-+		if (ret < 0)
-+			return ret;
-+	}
-+
- 	if (phydev->autoneg == AUTONEG_DISABLE) {
- 		/* Configure half duplex with genphy_setup_forced,
- 		 * because genphy_c45_pma_setup_forced does not support.
-@@ -310,6 +321,8 @@ static void gpy_update_interface(struct
- 	switch (phydev->speed) {
- 	case SPEED_2500:
- 		phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
-+		if (phydev->phylink)
-+			break;
- 		ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
- 				     VSPEC1_SGMII_CTRL_ANEN, 0);
- 		if (ret < 0)
-@@ -321,7 +334,7 @@ static void gpy_update_interface(struct
- 	case SPEED_100:
- 	case SPEED_10:
- 		phydev->interface = PHY_INTERFACE_MODE_SGMII;
--		if (gpy_sgmii_aneg_en(phydev))
-+		if (phydev->phylink || gpy_sgmii_aneg_en(phydev))
- 			break;
- 		/* Enable and restart SGMII ANEG for 10/100/1000Mbps link speed
- 		 * if ANEG is disabled (in 2500-BaseX mode).
diff --git a/target/linux/mediatek/patches-5.15/733-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch b/target/linux/mediatek/patches-5.15/733-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch
deleted file mode 100644
index 76008192469d7b..00000000000000
--- a/target/linux/mediatek/patches-5.15/733-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From 128dc09b0af36772062142ce9e85b19c84ac789a Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Tue, 28 Feb 2023 17:53:37 +0000
-Subject: [PATCH] net: phy: add driver for MediaTek 2.5G PHY
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/net/phy/Kconfig          |   7 ++
- drivers/net/phy/Makefile         |   1 +
- drivers/net/phy/mediatek-2p5ge.c | 220 +++++++++++++++++++++++++++++++
- 3 files changed, 226 insertions(+)
- create mode 100644 drivers/net/phy/mediatek-2p5ge.c
-
---- a/drivers/net/phy/Kconfig
-+++ b/drivers/net/phy/Kconfig
-@@ -302,6 +302,13 @@ config MEDIATEK_GE_SOC_PHY
- 	  present in the SoCs efuse and will dynamically calibrate VCM
- 	  (common-mode voltage) during startup.
- 
-+config MEDIATEK_2P5G_PHY
-+	tristate "MediaTek 2.5G Ethernet PHY"
-+	depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
-+	default NET_MEDIATEK_SOC
-+	help
-+	  Supports the MediaTek 2.5G Ethernet PHY.
-+
- config MICREL_PHY
- 	tristate "Micrel PHYs"
- 	help
---- a/drivers/net/phy/Makefile
-+++ b/drivers/net/phy/Makefile
-@@ -76,6 +76,7 @@ obj-$(CONFIG_MARVELL_10G_PHY)	+= marvell
- obj-$(CONFIG_MARVELL_PHY)	+= marvell.o
- obj-$(CONFIG_MARVELL_88X2222_PHY)	+= marvell-88x2222.o
- obj-$(CONFIG_MAXLINEAR_GPHY)	+= mxl-gpy.o
-+obj-$(CONFIG_MEDIATEK_2P5G_PHY)	+= mediatek-2p5ge.o
- obj-$(CONFIG_MEDIATEK_GE_PHY)	+= mediatek-ge.o
- obj-$(CONFIG_MEDIATEK_GE_SOC_PHY)	+= mediatek-ge-soc.o
- obj-$(CONFIG_MESON_GXL_PHY)	+= meson-gxl.o
diff --git a/target/linux/mediatek/patches-5.15/750-net-phy-add-driver-for-Airoha-EN8811-2.5G-PHY.patch b/target/linux/mediatek/patches-5.15/750-net-phy-add-driver-for-Airoha-EN8811-2.5G-PHY.patch
deleted file mode 100644
index c017ad2701fd71..00000000000000
--- a/target/linux/mediatek/patches-5.15/750-net-phy-add-driver-for-Airoha-EN8811-2.5G-PHY.patch
+++ /dev/null
@@ -1,48 +0,0 @@
-From 4a6ecbd197764499d808309f372341370a89f88c Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Sun, 11 Jun 2023 01:59:14 +0100
-Subject: [PATCH] net: phy: add driver for Airoha EN8811 2.5G PHY
-
-2500Base-T PHY with ID 0x03a2a411, needs firmware upload
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/net/phy/Kconfig       |   5 +
- drivers/net/phy/Makefile      |   1 +
- drivers/net/phy/air_en8811h.c | 708 ++++++++++++++++++++++++++++++++++
- drivers/net/phy/air_en8811h.h | 151 ++++++++
- 4 files changed, 865 insertions(+)
- create mode 100644 drivers/net/phy/air_en8811h.c
- create mode 100644 drivers/net/phy/air_en8811h.h
-
---- a/drivers/net/phy/Kconfig
-+++ b/drivers/net/phy/Kconfig
-@@ -149,6 +149,17 @@ config MESON_GXL_PHY
- 	help
- 	  Currently has a driver for the Amlogic Meson GXL Internal PHY
- 
-+config AIROHA_EN8811H_PHY
-+	tristate "Airoha EN8811H 2.5G Gigabit PHY"
-+	help
-+	  Currently supports the Airoha EN8811H PHY.
-+
-+config AIROHA_EN8811H_PHY_DEBUGFS
-+	bool "EN8811H debugfs support"
-+	depends on AIROHA_EN8811H_PHY
-+	help
-+	  Enable creation of debugfs files for the EN8811H drivers.
-+
- config ADIN_PHY
- 	tristate "Analog Devices Industrial Ethernet PHYs"
- 	help
---- a/drivers/net/phy/Makefile
-+++ b/drivers/net/phy/Makefile
-@@ -51,6 +51,8 @@ aquantia-objs			+= aquantia_main.o
- ifdef CONFIG_HWMON
- aquantia-objs			+= aquantia_hwmon.o
- endif
-+air_en8811h-y			:= air_en8811h_main.o air_en8811h_api.o
-+obj-$(CONFIG_AIROHA_EN8811H_PHY)	+= air_en8811h.o
- obj-$(CONFIG_AQUANTIA_PHY)	+= aquantia.o
- obj-$(CONFIG_AT803X_PHY)	+= at803x.o
- obj-$(CONFIG_AX88796B_PHY)	+= ax88796b.o
diff --git a/target/linux/mediatek/patches-5.15/801-phy-phy-mtk-tphy-Add-PCIe-2-lane-efuse-support.patch b/target/linux/mediatek/patches-5.15/801-phy-phy-mtk-tphy-Add-PCIe-2-lane-efuse-support.patch
deleted file mode 100644
index 691a7c0398e46b..00000000000000
--- a/target/linux/mediatek/patches-5.15/801-phy-phy-mtk-tphy-Add-PCIe-2-lane-efuse-support.patch
+++ /dev/null
@@ -1,225 +0,0 @@
-From 41ffe32e7ec23f592e21c508b5108899ad393059 Mon Sep 17 00:00:00 2001
-From: Zhanyong Wang <zhanyong.wang@mediatek.com>
-Date: Tue, 25 Jan 2022 16:50:47 +0800
-Subject: [PATCH 4/5] phy: phy-mtk-tphy: Add PCIe 2 lane efuse support
-
-Add PCIe 2 lane efuse support in tphy driver.
-
-Signed-off-by: Jie Yang <jieyy.yang@mediatek.com>
-Signed-off-by: Zhanyong Wang <zhanyong.wang@mediatek.com>
----
- drivers/phy/mediatek/phy-mtk-tphy.c | 140 ++++++++++++++++++++++++++++
- 1 file changed, 140 insertions(+)
-
---- a/drivers/phy/mediatek/phy-mtk-tphy.c
-+++ b/drivers/phy/mediatek/phy-mtk-tphy.c
-@@ -44,6 +44,15 @@
- #define SSUSB_SIFSLV_V2_U3PHYD		0x200
- #define SSUSB_SIFSLV_V2_U3PHYA		0x400
- 
-+/* version V4 sub-banks offset base address */
-+/* pcie phy banks */
-+#define SSUSB_SIFSLV_V4_SPLLC		0x000
-+#define SSUSB_SIFSLV_V4_CHIP		0x100
-+#define SSUSB_SIFSLV_V4_U3PHYD		0x900
-+#define SSUSB_SIFSLV_V4_U3PHYA		0xb00
-+
-+#define SSUSB_LN1_OFFSET		0x10000
-+
- #define U3P_MISC_REG1		0x04
- #define MR1_EFUSE_AUTO_LOAD_DIS		BIT(6)
- 
-@@ -320,6 +329,7 @@ enum mtk_phy_version {
- 	MTK_PHY_V1 = 1,
- 	MTK_PHY_V2,
- 	MTK_PHY_V3,
-+	MTK_PHY_V4,
- };
- 
- struct mtk_phy_pdata {
-@@ -369,6 +379,9 @@ struct mtk_phy_instance {
- 	u32 efuse_intr;
- 	u32 efuse_tx_imp;
- 	u32 efuse_rx_imp;
-+	u32 efuse_intr_ln1;
-+	u32 efuse_tx_imp_ln1;
-+	u32 efuse_rx_imp_ln1;
- 	int eye_src;
- 	int eye_vrt;
- 	int eye_term;
-@@ -946,6 +959,36 @@ static void phy_v2_banks_init(struct mtk
- 	}
- }
- 
-+static void phy_v4_banks_init(struct mtk_tphy *tphy,
-+			      struct mtk_phy_instance *instance)
-+{
-+	struct u2phy_banks *u2_banks = &instance->u2_banks;
-+	struct u3phy_banks *u3_banks = &instance->u3_banks;
-+
-+	switch (instance->type) {
-+	case PHY_TYPE_USB2:
-+		u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC;
-+		u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ;
-+		u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM;
-+		break;
-+	case PHY_TYPE_USB3:
-+		u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC;
-+		u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP;
-+		u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD;
-+		u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA;
-+		break;
-+	case PHY_TYPE_PCIE:
-+		u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V4_SPLLC;
-+		u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V4_CHIP;
-+		u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V4_U3PHYD;
-+		u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V4_U3PHYA;
-+		break;
-+	default:
-+		dev_err(tphy->dev, "incompatible PHY type\n");
-+		return;
-+	}
-+}
-+
- static void phy_parse_property(struct mtk_tphy *tphy,
- 				struct mtk_phy_instance *instance)
- {
-@@ -1144,6 +1187,40 @@ static int phy_efuse_get(struct mtk_tphy
- 
- 		dev_dbg(dev, "u3 efuse - intr %x, rx_imp %x, tx_imp %x\n",
- 			instance->efuse_intr, instance->efuse_rx_imp,instance->efuse_tx_imp);
-+
-+		if (tphy->pdata->version != MTK_PHY_V4)
-+			break;
-+
-+		ret = nvmem_cell_read_variable_le_u32(dev, "intr_ln1", &instance->efuse_intr_ln1);
-+		if (ret) {
-+			dev_err(dev, "fail to get u3 lane1 intr efuse, %d\n", ret);
-+			break;
-+		}
-+
-+		ret = nvmem_cell_read_variable_le_u32(dev, "rx_imp_ln1", &instance->efuse_rx_imp_ln1);
-+		if (ret) {
-+			dev_err(dev, "fail to get u3 lane1 rx_imp efuse, %d\n", ret);
-+			break;
-+		}
-+
-+		ret = nvmem_cell_read_variable_le_u32(dev, "tx_imp_ln1", &instance->efuse_tx_imp_ln1);
-+		if (ret) {
-+			dev_err(dev, "fail to get u3 lane1 tx_imp efuse, %d\n", ret);
-+			break;
-+		}
-+
-+		/* no efuse, ignore it */
-+		if (!instance->efuse_intr_ln1 &&
-+		    !instance->efuse_rx_imp_ln1 &&
-+		    !instance->efuse_tx_imp_ln1) {
-+			dev_warn(dev, "no u3 lane1 efuse, but dts enable it\n");
-+			instance->efuse_sw_en = 0;
-+			break;
-+		}
-+
-+		dev_info(dev, "u3 lane1 efuse - intr %x, rx_imp %x, tx_imp %x\n",
-+			 instance->efuse_intr_ln1, instance->efuse_rx_imp_ln1,
-+			 instance->efuse_tx_imp_ln1);
- 		break;
- 	default:
- 		dev_err(dev, "no sw efuse for type %d\n", instance->type);
-@@ -1175,6 +1252,31 @@ static void phy_efuse_set(struct mtk_phy
- 		writel(tmp, u2_banks->com + U3P_USBPHYACR1);
- 		break;
- 	case PHY_TYPE_USB3:
-+		tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV);
-+		tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS;
-+		writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RSV);
-+
-+		tmp = readl(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0);
-+		tmp &= ~P3D_RG_TX_IMPEL;
-+		tmp |= P3D_RG_TX_IMPEL_VAL(instance->efuse_tx_imp);
-+		tmp |= P3D_RG_FORCE_TX_IMPEL;
-+		writel(tmp, u3_banks->phyd + U3P_U3_PHYD_IMPCAL0);
-+
-+		tmp = readl(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1);
-+		tmp &= ~P3D_RG_RX_IMPEL;
-+		tmp |= P3D_RG_RX_IMPEL_VAL(instance->efuse_rx_imp);
-+		tmp |= P3D_RG_FORCE_RX_IMPEL;
-+		writel(tmp, u3_banks->phyd + U3P_U3_PHYD_IMPCAL1);
-+
-+		tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG0);
-+		tmp &= ~P3A_RG_IEXT_INTR;
-+		tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr);
-+		writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0);
-+		pr_err("%s set efuse, tx_imp %x, rx_imp %x intr %x\n",
-+			__func__, instance->efuse_tx_imp,
-+			instance->efuse_rx_imp, instance->efuse_intr);
-+
-+		break;
- 	case PHY_TYPE_PCIE:
- 		tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV);
- 		tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS;
-@@ -1196,6 +1298,34 @@ static void phy_efuse_set(struct mtk_phy
- 		tmp &= ~P3A_RG_IEXT_INTR;
- 		tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr);
- 		writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0);
-+		if (!instance->efuse_intr_ln1 &&
-+		    !instance->efuse_rx_imp_ln1 &&
-+		    !instance->efuse_tx_imp_ln1)
-+			break;
-+
-+		tmp = readl(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_RSV);
-+		tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS;
-+		writel(tmp, u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_RSV);
-+
-+		tmp = readl(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL0);
-+		tmp &= ~P3D_RG_TX_IMPEL;
-+		tmp |= P3D_RG_TX_IMPEL_VAL(instance->efuse_tx_imp_ln1);
-+		tmp |= P3D_RG_FORCE_TX_IMPEL;
-+		writel(tmp, u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL0);
-+
-+		tmp = readl(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL1);
-+		tmp &= ~P3D_RG_RX_IMPEL;
-+		tmp |= P3D_RG_RX_IMPEL_VAL(instance->efuse_rx_imp_ln1);
-+		tmp |= P3D_RG_FORCE_RX_IMPEL;
-+		writel(tmp, u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL1);
-+
-+		tmp = readl(u3_banks->phya + SSUSB_LN1_OFFSET + U3P_U3_PHYA_REG0);
-+		tmp &= ~P3A_RG_IEXT_INTR;
-+		tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr_ln1);
-+		writel(tmp, u3_banks->phya + SSUSB_LN1_OFFSET + U3P_U3_PHYA_REG0);
-+		dev_info(dev, "%s set LN1 efuse, tx_imp %x, rx_imp %x intr %x\n",
-+			 __func__, instance->efuse_tx_imp_ln1,
-+			 instance->efuse_rx_imp_ln1, instance->efuse_intr_ln1);
- 		break;
- 	default:
- 		dev_warn(dev, "no sw efuse for type %d\n", instance->type);
-@@ -1335,6 +1465,9 @@ static struct phy *mtk_phy_xlate(struct
- 	case MTK_PHY_V3:
- 		phy_v2_banks_init(tphy, instance);
- 		break;
-+	case MTK_PHY_V4:
-+		phy_v4_banks_init(tphy, instance);
-+		break;
- 	default:
- 		dev_err(dev, "phy version is not supported\n");
- 		return ERR_PTR(-EINVAL);
-@@ -1375,6 +1508,12 @@ static const struct mtk_phy_pdata tphy_v
- 	.version = MTK_PHY_V3,
- };
- 
-+static const struct mtk_phy_pdata tphy_v4_pdata = {
-+	.avoid_rx_sen_degradation = false,
-+	.sw_efuse_supported = true,
-+	.version = MTK_PHY_V4,
-+};
-+
- static const struct mtk_phy_pdata mt8173_pdata = {
- 	.avoid_rx_sen_degradation = true,
- 	.version = MTK_PHY_V1,
-@@ -1394,6 +1533,7 @@ static const struct of_device_id mtk_tph
- 	{ .compatible = "mediatek,generic-tphy-v1", .data = &tphy_v1_pdata },
- 	{ .compatible = "mediatek,generic-tphy-v2", .data = &tphy_v2_pdata },
- 	{ .compatible = "mediatek,generic-tphy-v3", .data = &tphy_v3_pdata },
-+	{ .compatible = "mediatek,generic-tphy-v4", .data = &tphy_v4_pdata },
- 	{ },
- };
- MODULE_DEVICE_TABLE(of, mtk_tphy_id_table);
diff --git a/target/linux/mediatek/patches-5.15/802-phy-phy-mtk-tphy-add-auto-load-valid-check-mechanism.patch b/target/linux/mediatek/patches-5.15/802-phy-phy-mtk-tphy-add-auto-load-valid-check-mechanism.patch
deleted file mode 100644
index 3b8285bf479ab0..00000000000000
--- a/target/linux/mediatek/patches-5.15/802-phy-phy-mtk-tphy-add-auto-load-valid-check-mechanism.patch
+++ /dev/null
@@ -1,149 +0,0 @@
-From 1d5819e90f2ef6dead11809744372a9863227a92 Mon Sep 17 00:00:00 2001
-From: Zhanyong Wang <zhanyong.wang@mediatek.com>
-Date: Tue, 25 Jan 2022 19:03:34 +0800
-Subject: [PATCH 5/5] phy: phy-mtk-tphy: add auto-load-valid check mechanism
- support
-
-add auto-load-valid check mechanism support
-
-Signed-off-by: Zhanyong Wang <zhanyong.wang@mediatek.com>
----
- drivers/phy/mediatek/phy-mtk-tphy.c | 67 +++++++++++++++++++++++++++--
- 1 file changed, 64 insertions(+), 3 deletions(-)
-
---- a/drivers/phy/mediatek/phy-mtk-tphy.c
-+++ b/drivers/phy/mediatek/phy-mtk-tphy.c
-@@ -376,9 +376,13 @@ struct mtk_phy_instance {
- 	u32 type_sw_reg;
- 	u32 type_sw_index;
- 	u32 efuse_sw_en;
-+	bool efuse_alv_en;
-+	u32 efuse_autoloadvalid;
- 	u32 efuse_intr;
- 	u32 efuse_tx_imp;
- 	u32 efuse_rx_imp;
-+	bool efuse_alv_ln1_en;
-+	u32 efuse_ln1_autoloadvalid;
- 	u32 efuse_intr_ln1;
- 	u32 efuse_tx_imp_ln1;
- 	u32 efuse_rx_imp_ln1;
-@@ -1126,6 +1130,7 @@ static int phy_efuse_get(struct mtk_tphy
- {
- 	struct device *dev = &instance->phy->dev;
- 	int ret = 0;
-+	bool alv = false;
- 
- 	/* tphy v1 doesn't support sw efuse, skip it */
- 	if (!tphy->pdata->sw_efuse_supported) {
-@@ -1140,6 +1145,20 @@ static int phy_efuse_get(struct mtk_tphy
- 
- 	switch (instance->type) {
- 	case PHY_TYPE_USB2:
-+		alv = of_property_read_bool(dev->of_node, "auto_load_valid");
-+		if (alv) {
-+			instance->efuse_alv_en = alv;
-+			ret = nvmem_cell_read_variable_le_u32(dev, "auto_load_valid",
-+							&instance->efuse_autoloadvalid);
-+			if (ret) {
-+				dev_err(dev, "fail to get u2 alv efuse, %d\n", ret);
-+				break;
-+			}
-+			dev_info(dev,
-+				"u2 auto load valid efuse: ENABLE with value: %u\n",
-+				instance->efuse_autoloadvalid);
-+		}
-+
- 		ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr);
- 		if (ret) {
- 			dev_err(dev, "fail to get u2 intr efuse, %d\n", ret);
-@@ -1158,6 +1177,20 @@ static int phy_efuse_get(struct mtk_tphy
- 
- 	case PHY_TYPE_USB3:
- 	case PHY_TYPE_PCIE:
-+		alv = of_property_read_bool(dev->of_node, "auto_load_valid");
-+		if (alv) {
-+			instance->efuse_alv_en = alv;
-+			ret = nvmem_cell_read_variable_le_u32(dev, "auto_load_valid",
-+							&instance->efuse_autoloadvalid);
-+			if (ret) {
-+				dev_err(dev, "fail to get u3(pcei) alv efuse, %d\n", ret);
-+				break;
-+			}
-+			dev_info(dev,
-+				"u3 auto load valid efuse: ENABLE with value: %u\n",
-+				instance->efuse_autoloadvalid);
-+		}
-+
- 		ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr);
- 		if (ret) {
- 			dev_err(dev, "fail to get u3 intr efuse, %d\n", ret);
-@@ -1191,6 +1224,20 @@ static int phy_efuse_get(struct mtk_tphy
- 		if (tphy->pdata->version != MTK_PHY_V4)
- 			break;
- 
-+		alv = of_property_read_bool(dev->of_node, "auto_load_valid_ln1");
-+		if (alv) {
-+			instance->efuse_alv_ln1_en = alv;
-+			ret = nvmem_cell_read_variable_le_u32(dev, "auto_load_valid_ln1",
-+							&instance->efuse_ln1_autoloadvalid);
-+			if (ret) {
-+				dev_err(dev, "fail to get pcie auto_load_valid efuse, %d\n", ret);
-+				break;
-+			}
-+			dev_info(dev,
-+				"pcie auto load valid efuse: ENABLE with value: %u\n",
-+				instance->efuse_ln1_autoloadvalid);
-+		}
-+
- 		ret = nvmem_cell_read_variable_le_u32(dev, "intr_ln1", &instance->efuse_intr_ln1);
- 		if (ret) {
- 			dev_err(dev, "fail to get u3 lane1 intr efuse, %d\n", ret);
-@@ -1242,6 +1289,10 @@ static void phy_efuse_set(struct mtk_phy
- 
- 	switch (instance->type) {
- 	case PHY_TYPE_USB2:
-+		if (instance->efuse_alv_en &&
-+		    instance->efuse_autoloadvalid == 1)
-+			break;
-+
- 		tmp = readl(u2_banks->misc + U3P_MISC_REG1);
- 		tmp |= MR1_EFUSE_AUTO_LOAD_DIS;
- 		writel(tmp, u2_banks->misc + U3P_MISC_REG1);
-@@ -1252,6 +1303,10 @@ static void phy_efuse_set(struct mtk_phy
- 		writel(tmp, u2_banks->com + U3P_USBPHYACR1);
- 		break;
- 	case PHY_TYPE_USB3:
-+		if (instance->efuse_alv_en &&
-+		    instance->efuse_autoloadvalid == 1)
-+			break;
-+
- 		tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV);
- 		tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS;
- 		writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RSV);
-@@ -1278,6 +1333,10 @@ static void phy_efuse_set(struct mtk_phy
- 
- 		break;
- 	case PHY_TYPE_PCIE:
-+		if (instance->efuse_alv_en &&
-+		    instance->efuse_autoloadvalid == 1)
-+			break;
-+
- 		tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV);
- 		tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS;
- 		writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RSV);
-@@ -1298,9 +1357,12 @@ static void phy_efuse_set(struct mtk_phy
- 		tmp &= ~P3A_RG_IEXT_INTR;
- 		tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr);
- 		writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0);
--		if (!instance->efuse_intr_ln1 &&
--		    !instance->efuse_rx_imp_ln1 &&
--		    !instance->efuse_tx_imp_ln1)
-+
-+		if ((!instance->efuse_intr_ln1 &&
-+		     !instance->efuse_rx_imp_ln1 &&
-+		     !instance->efuse_tx_imp_ln1) ||
-+		    (instance->efuse_alv_ln1_en &&
-+		     instance->efuse_ln1_autoloadvalid == 1))
- 			break;
- 
- 		tmp = readl(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_RSV);
diff --git a/target/linux/mediatek/patches-5.15/804-pwm-add-mt7986-support.patch b/target/linux/mediatek/patches-5.15/804-pwm-add-mt7986-support.patch
deleted file mode 100644
index 7a10dac051c020..00000000000000
--- a/target/linux/mediatek/patches-5.15/804-pwm-add-mt7986-support.patch
+++ /dev/null
@@ -1,23 +0,0 @@
---- a/drivers/pwm/pwm-mediatek.c
-+++ b/drivers/pwm/pwm-mediatek.c
-@@ -302,6 +302,12 @@ static const struct pwm_mediatek_of_data
- 	.has_ck_26m_sel = true,
- };
- 
-+static const struct pwm_mediatek_of_data mt7986_pwm_data = {
-+	.num_pwms = 2,
-+	.pwm45_fixup = false,
-+	.has_ck_26m_sel = true,
-+};
-+
- static const struct pwm_mediatek_of_data mt8516_pwm_data = {
- 	.num_pwms = 5,
- 	.pwm45_fixup = false,
-@@ -314,6 +320,7 @@ static const struct of_device_id pwm_med
- 	{ .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data },
- 	{ .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data },
- 	{ .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },
-+	{ .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data },
- 	{ .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data },
- 	{ .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data },
- 	{ },
diff --git a/target/linux/mediatek/patches-5.15/805-v6.2-thermal-drivers-mtk-use-function-pointer-for-raw_to_.patch b/target/linux/mediatek/patches-5.15/805-v6.2-thermal-drivers-mtk-use-function-pointer-for-raw_to_.patch
deleted file mode 100644
index c58ae96403ad7d..00000000000000
--- a/target/linux/mediatek/patches-5.15/805-v6.2-thermal-drivers-mtk-use-function-pointer-for-raw_to_.patch
+++ /dev/null
@@ -1,56 +0,0 @@
-From 69c17529e8418da3eec703dde31e1b01e5b0f7e8 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Wed, 18 Jan 2023 02:48:41 +0000
-Subject: [PATCH 1/2] thermal/drivers/mtk: use function pointer for
- raw_to_mcelsius
-
-Instead of having if-else logic selecting either raw_to_mcelsius_v1 or
-raw_to_mcelsius_v2 in mtk_thermal_bank_temperature introduce a function
-pointer raw_to_mcelsius to struct mtk_thermal which is initialized in the
-probe function.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/thermal/mtk_thermal.c | 17 ++++++++++-------
- 1 file changed, 10 insertions(+), 7 deletions(-)
-
---- a/drivers/thermal/mtk_thermal.c
-+++ b/drivers/thermal/mtk_thermal.c
-@@ -292,6 +292,8 @@ struct mtk_thermal {
- 
- 	const struct mtk_thermal_data *conf;
- 	struct mtk_thermal_bank banks[MAX_NUM_ZONES];
-+
-+	int (*raw_to_mcelsius)(struct mtk_thermal *mt, int sensno, s32 raw);
- };
- 
- /* MT8183 thermal sensor data */
-@@ -656,13 +658,9 @@ static int mtk_thermal_bank_temperature(
- 	for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) {
- 		raw = readl(mt->thermal_base + conf->msr[i]);
- 
--		if (mt->conf->version == MTK_THERMAL_V1) {
--			temp = raw_to_mcelsius_v1(
--				mt, conf->bank_data[bank->id].sensors[i], raw);
--		} else {
--			temp = raw_to_mcelsius_v2(
--				mt, conf->bank_data[bank->id].sensors[i], raw);
--		}
-+		temp = mt->raw_to_mcelsius(
-+			mt, conf->bank_data[bank->id].sensors[i], raw);
-+
- 
- 		/*
- 		 * The first read of a sensor often contains very high bogus
-@@ -1075,6 +1073,11 @@ static int mtk_thermal_probe(struct plat
- 		mtk_thermal_release_periodic_ts(mt, auxadc_base);
- 	}
- 
-+	if (mt->conf->version == MTK_THERMAL_V1)
-+		mt->raw_to_mcelsius = raw_to_mcelsius_v1;
-+	else
-+		mt->raw_to_mcelsius = raw_to_mcelsius_v2;
-+
- 	for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++)
- 		for (i = 0; i < mt->conf->num_banks; i++)
- 			mtk_thermal_init_bank(mt, i, apmixed_phys_base,
diff --git a/target/linux/mediatek/patches-5.15/806-v6.2-thermal-mediatek-add-support-for-MT7986-and-MT7981.patch b/target/linux/mediatek/patches-5.15/806-v6.2-thermal-mediatek-add-support-for-MT7986-and-MT7981.patch
deleted file mode 100644
index 65311d5718d9f9..00000000000000
--- a/target/linux/mediatek/patches-5.15/806-v6.2-thermal-mediatek-add-support-for-MT7986-and-MT7981.patch
+++ /dev/null
@@ -1,240 +0,0 @@
-From aa957c759b1182aee00cc35178667f849f941b42 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Wed, 30 Nov 2022 13:19:39 +0000
-Subject: [PATCH 2/2] thermal: mediatek: add support for MT7986 and MT7981
-
-Add support for V3 generation thermal found in MT7986 and MT7981 SoCs.
-Brings code to assign values from efuse as well as new function to
-convert raw temperature to millidegree celsius, as found in MediaTek's
-SDK sources (but cleaned up and de-duplicated)
-
-[1]: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/baf36c7eef477aae1f8f2653b6c29e2caf48475b
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/thermal/mtk_thermal.c | 137 ++++++++++++++++++++++++++++++++--
- 1 file changed, 132 insertions(+), 5 deletions(-)
-
---- a/drivers/thermal/mtk_thermal.c
-+++ b/drivers/thermal/mtk_thermal.c
-@@ -150,6 +150,20 @@
- #define CALIB_BUF1_VALID_V2(x)		(((x) >> 4) & 0x1)
- #define CALIB_BUF1_O_SLOPE_SIGN_V2(x)	(((x) >> 3) & 0x1)
- 
-+/*
-+ * Layout of the fuses providing the calibration data
-+ * These macros can be used for MT7981 and MT7986.
-+ */
-+#define CALIB_BUF0_ADC_GE_V3(x)		(((x) >> 0) & 0x3ff)
-+#define CALIB_BUF0_DEGC_CALI_V3(x)	(((x) >> 20) & 0x3f)
-+#define CALIB_BUF0_O_SLOPE_V3(x)	(((x) >> 26) & 0x3f)
-+#define CALIB_BUF1_VTS_TS1_V3(x)	(((x) >> 0) & 0x1ff)
-+#define CALIB_BUF1_VTS_TS2_V3(x)	(((x) >> 21) & 0x1ff)
-+#define CALIB_BUF1_VTS_TSABB_V3(x)	(((x) >> 9) & 0x1ff)
-+#define CALIB_BUF1_VALID_V3(x)		(((x) >> 18) & 0x1)
-+#define CALIB_BUF1_O_SLOPE_SIGN_V3(x)	(((x) >> 19) & 0x1)
-+#define CALIB_BUF1_ID_V3(x)		(((x) >> 20) & 0x1)
-+
- enum {
- 	VTS1,
- 	VTS2,
-@@ -163,6 +177,7 @@ enum {
- enum mtk_thermal_version {
- 	MTK_THERMAL_V1 = 1,
- 	MTK_THERMAL_V2,
-+	MTK_THERMAL_V3,
- };
- 
- /* MT2701 thermal sensors */
-@@ -245,6 +260,27 @@ enum mtk_thermal_version {
- /* The calibration coefficient of sensor  */
- #define MT8183_CALIBRATION	153
- 
-+/* AUXADC channel 11 is used for the temperature sensors */
-+#define MT7986_TEMP_AUXADC_CHANNEL	11
-+
-+/* The total number of temperature sensors in the MT7986 */
-+#define MT7986_NUM_SENSORS		1
-+
-+/* The number of banks in the MT7986 */
-+#define MT7986_NUM_ZONES		1
-+
-+/* The number of sensing points per bank */
-+#define MT7986_NUM_SENSORS_PER_ZONE	1
-+
-+/* MT7986 thermal sensors */
-+#define MT7986_TS1			0
-+
-+/* The number of controller in the MT7986 */
-+#define MT7986_NUM_CONTROLLER		1
-+
-+/* The calibration coefficient of sensor  */
-+#define MT7986_CALIBRATION		165
-+
- struct mtk_thermal;
- 
- struct thermal_bank_cfg {
-@@ -388,6 +424,14 @@ static const int mt7622_mux_values[MT762
- static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 };
- static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, };
- 
-+/* MT7986 thermal sensor data */
-+static const int mt7986_bank_data[MT7986_NUM_SENSORS] = { MT7986_TS1, };
-+static const int mt7986_msr[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, };
-+static const int mt7986_adcpnp[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, };
-+static const int mt7986_mux_values[MT7986_NUM_SENSORS] = { 0, };
-+static const int mt7986_vts_index[MT7986_NUM_SENSORS] = { VTS1 };
-+static const int mt7986_tc_offset[MT7986_NUM_CONTROLLER] = { 0x0, };
-+
- /*
-  * The MT8173 thermal controller has four banks. Each bank can read up to
-  * four temperature sensors simultaneously. The MT8173 has a total of 5
-@@ -551,6 +595,30 @@ static const struct mtk_thermal_data mt8
- 	.version = MTK_THERMAL_V1,
- };
- 
-+/*
-+ * MT7986 uses AUXADC Channel 11 for raw data access.
-+ */
-+static const struct mtk_thermal_data mt7986_thermal_data = {
-+	.auxadc_channel = MT7986_TEMP_AUXADC_CHANNEL,
-+	.num_banks = MT7986_NUM_ZONES,
-+	.num_sensors = MT7986_NUM_SENSORS,
-+	.vts_index = mt7986_vts_index,
-+	.cali_val = MT7986_CALIBRATION,
-+	.num_controller = MT7986_NUM_CONTROLLER,
-+	.controller_offset = mt7986_tc_offset,
-+	.need_switch_bank = true,
-+	.bank_data = {
-+		{
-+			.num_sensors = 1,
-+			.sensors = mt7986_bank_data,
-+		},
-+	},
-+	.msr = mt7986_msr,
-+	.adcpnp = mt7986_adcpnp,
-+	.sensor_mux_values = mt7986_mux_values,
-+	.version = MTK_THERMAL_V3,
-+};
-+
- /**
-  * raw_to_mcelsius - convert a raw ADC value to mcelsius
-  * @mt:	The thermal controller
-@@ -605,6 +673,22 @@ static int raw_to_mcelsius_v2(struct mtk
- 	return (format_2 - tmp) * 100;
- }
- 
-+static int raw_to_mcelsius_v3(struct mtk_thermal *mt, int sensno, s32 raw)
-+{
-+	s32 tmp;
-+
-+	if (raw == 0)
-+		return 0;
-+
-+	raw &= 0xfff;
-+	tmp = 100000 * 15 / 16 * 10000;
-+	tmp /= 4096 - 512 + mt->adc_ge;
-+	tmp /= 1490;
-+	tmp *= raw - mt->vts[sensno] - 2900;
-+
-+	return mt->degc_cali * 500 - tmp;
-+}
-+
- /**
-  * mtk_thermal_get_bank - get bank
-  * @bank:	The bank
-@@ -885,6 +969,25 @@ static int mtk_thermal_extract_efuse_v2(
- 	return 0;
- }
- 
-+static int mtk_thermal_extract_efuse_v3(struct mtk_thermal *mt, u32 *buf)
-+{
-+	if (!CALIB_BUF1_VALID_V3(buf[1]))
-+		return -EINVAL;
-+
-+	mt->adc_ge = CALIB_BUF0_ADC_GE_V3(buf[0]);
-+	mt->degc_cali = CALIB_BUF0_DEGC_CALI_V3(buf[0]);
-+	mt->o_slope = CALIB_BUF0_O_SLOPE_V3(buf[0]);
-+	mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V3(buf[1]);
-+	mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V3(buf[1]);
-+	mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V3(buf[1]);
-+	mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V3(buf[1]);
-+
-+	if (CALIB_BUF1_ID_V3(buf[1]) == 0)
-+		mt->o_slope = 0;
-+
-+	return 0;
-+}
-+
- static int mtk_thermal_get_calibration_data(struct device *dev,
- 					    struct mtk_thermal *mt)
- {
-@@ -895,6 +998,7 @@ static int mtk_thermal_get_calibration_d
- 
- 	/* Start with default values */
- 	mt->adc_ge = 512;
-+	mt->adc_oe = 512;
- 	for (i = 0; i < mt->conf->num_sensors; i++)
- 		mt->vts[i] = 260;
- 	mt->degc_cali = 40;
-@@ -920,10 +1024,20 @@ static int mtk_thermal_get_calibration_d
- 		goto out;
- 	}
- 
--	if (mt->conf->version == MTK_THERMAL_V1)
-+	switch (mt->conf->version) {
-+	case MTK_THERMAL_V1:
- 		ret = mtk_thermal_extract_efuse_v1(mt, buf);
--	else
-+		break;
-+	case MTK_THERMAL_V2:
- 		ret = mtk_thermal_extract_efuse_v2(mt, buf);
-+		break;
-+	case MTK_THERMAL_V3:
-+		ret = mtk_thermal_extract_efuse_v3(mt, buf);
-+		break;
-+	default:
-+		ret = -EINVAL;
-+		break;
-+	}
- 
- 	if (ret) {
- 		dev_info(dev, "Device not calibrated, using default calibration values\n");
-@@ -954,6 +1068,10 @@ static const struct of_device_id mtk_the
- 		.data = (void *)&mt7622_thermal_data,
- 	},
- 	{
-+		.compatible = "mediatek,mt7986-thermal",
-+		.data = (void *)&mt7986_thermal_data,
-+	},
-+	{
- 		.compatible = "mediatek,mt8183-thermal",
- 		.data = (void *)&mt8183_thermal_data,
- 	}, {
-@@ -1068,15 +1186,24 @@ static int mtk_thermal_probe(struct plat
- 		goto err_disable_clk_auxadc;
- 	}
- 
--	if (mt->conf->version == MTK_THERMAL_V2) {
-+	if (mt->conf->version != MTK_THERMAL_V1) {
- 		mtk_thermal_turn_on_buffer(apmixed_base);
- 		mtk_thermal_release_periodic_ts(mt, auxadc_base);
- 	}
- 
--	if (mt->conf->version == MTK_THERMAL_V1)
-+	switch (mt->conf->version) {
-+	case MTK_THERMAL_V1:
- 		mt->raw_to_mcelsius = raw_to_mcelsius_v1;
--	else
-+		break;
-+	case MTK_THERMAL_V2:
- 		mt->raw_to_mcelsius = raw_to_mcelsius_v2;
-+		break;
-+	case MTK_THERMAL_V3:
-+		mt->raw_to_mcelsius = raw_to_mcelsius_v3;
-+		break;
-+	default:
-+		break;
-+	}
- 
- 	for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++)
- 		for (i = 0; i < mt->conf->num_banks; i++)
diff --git a/target/linux/mediatek/patches-5.15/811-pwm-mediatek-Add-support-for-MT7981.patch b/target/linux/mediatek/patches-5.15/811-pwm-mediatek-Add-support-for-MT7981.patch
deleted file mode 100644
index 8f27462cbdc355..00000000000000
--- a/target/linux/mediatek/patches-5.15/811-pwm-mediatek-Add-support-for-MT7981.patch
+++ /dev/null
@@ -1,122 +0,0 @@
-From 73d20ebc21c562fbe79d02fa0fa38e095e716fa9 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Wed, 19 Apr 2023 20:25:51 +0100
-Subject: [PATCH] pwm: mediatek: Add support for MT7981
-
-The PWM unit on MT7981 uses different register offsets than previous
-MediaTek PWM units. Add support for these new offsets and add support
-for PWM on MT7981 which has 3 PWM channels, one of them is typically
-used for a temperature controlled fan.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/pwm/pwm-mediatek.c | 41 ++++++++++++++++++++++++++++++--------
- 1 file changed, 33 insertions(+), 8 deletions(-)
-
---- a/drivers/pwm/pwm-mediatek.c
-+++ b/drivers/pwm/pwm-mediatek.c
-@@ -38,6 +38,7 @@ struct pwm_mediatek_of_data {
- 	unsigned int num_pwms;
- 	bool pwm45_fixup;
- 	bool has_ck_26m_sel;
-+	const unsigned int *reg_offset;
- };
- 
- /**
-@@ -59,10 +60,14 @@ struct pwm_mediatek_chip {
- 	const struct pwm_mediatek_of_data *soc;
- };
- 
--static const unsigned int pwm_mediatek_reg_offset[] = {
-+static const unsigned int mtk_pwm_reg_offset_v1[] = {
- 	0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220
- };
- 
-+static const unsigned int mtk_pwm_reg_offset_v2[] = {
-+	0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240
-+};
-+
- static inline struct pwm_mediatek_chip *
- to_pwm_mediatek_chip(struct pwm_chip *chip)
- {
-@@ -111,7 +116,7 @@ static inline void pwm_mediatek_writel(s
- 				       unsigned int num, unsigned int offset,
- 				       u32 value)
- {
--	writel(value, chip->regs + pwm_mediatek_reg_offset[num] + offset);
-+	writel(value, chip->regs + chip->soc->reg_offset[num] + offset);
- }
- 
- static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
-@@ -270,48 +275,63 @@ static const struct pwm_mediatek_of_data
- 	.num_pwms = 8,
- 	.pwm45_fixup = false,
- 	.has_ck_26m_sel = false,
-+	.reg_offset = mtk_pwm_reg_offset_v1,
- };
- 
- static const struct pwm_mediatek_of_data mt7622_pwm_data = {
- 	.num_pwms = 6,
- 	.pwm45_fixup = false,
- 	.has_ck_26m_sel = true,
-+	.reg_offset = mtk_pwm_reg_offset_v1,
- };
- 
- static const struct pwm_mediatek_of_data mt7623_pwm_data = {
- 	.num_pwms = 5,
- 	.pwm45_fixup = true,
- 	.has_ck_26m_sel = false,
-+	.reg_offset = mtk_pwm_reg_offset_v1,
- };
- 
- static const struct pwm_mediatek_of_data mt7628_pwm_data = {
- 	.num_pwms = 4,
- 	.pwm45_fixup = true,
- 	.has_ck_26m_sel = false,
-+	.reg_offset = mtk_pwm_reg_offset_v1,
- };
- 
- static const struct pwm_mediatek_of_data mt7629_pwm_data = {
- 	.num_pwms = 1,
- 	.pwm45_fixup = false,
- 	.has_ck_26m_sel = false,
-+	.reg_offset = mtk_pwm_reg_offset_v1,
- };
- 
- static const struct pwm_mediatek_of_data mt8183_pwm_data = {
- 	.num_pwms = 4,
- 	.pwm45_fixup = false,
- 	.has_ck_26m_sel = true,
-+	.reg_offset = mtk_pwm_reg_offset_v1,
-+};
-+
-+static const struct pwm_mediatek_of_data mt7981_pwm_data = {
-+	.num_pwms = 3,
-+	.pwm45_fixup = false,
-+	.has_ck_26m_sel = true,
-+	.reg_offset = mtk_pwm_reg_offset_v2,
- };
- 
- static const struct pwm_mediatek_of_data mt7986_pwm_data = {
- 	.num_pwms = 2,
- 	.pwm45_fixup = false,
- 	.has_ck_26m_sel = true,
-+	.reg_offset = mtk_pwm_reg_offset_v1,
- };
- 
- static const struct pwm_mediatek_of_data mt8516_pwm_data = {
- 	.num_pwms = 5,
- 	.pwm45_fixup = false,
- 	.has_ck_26m_sel = true,
-+	.reg_offset = mtk_pwm_reg_offset_v1,
- };
- 
- static const struct of_device_id pwm_mediatek_of_match[] = {
-@@ -320,6 +340,7 @@ static const struct of_device_id pwm_med
- 	{ .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data },
- 	{ .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data },
- 	{ .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },
-+	{ .compatible = "mediatek,mt7981-pwm", .data = &mt7981_pwm_data },
- 	{ .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data },
- 	{ .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data },
- 	{ .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data },
diff --git a/target/linux/mediatek/patches-5.15/820-v5.16-dt-bindings-pinctrl-mt8195-add-rsel-define.patch b/target/linux/mediatek/patches-5.15/820-v5.16-dt-bindings-pinctrl-mt8195-add-rsel-define.patch
deleted file mode 100644
index f2be737146e19c..00000000000000
--- a/target/linux/mediatek/patches-5.15/820-v5.16-dt-bindings-pinctrl-mt8195-add-rsel-define.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From 26564c44357e19d03c124550bbd0b5851e6638c2 Mon Sep 17 00:00:00 2001
-From: Zhiyong Tao <zhiyong.tao@mediatek.com>
-Date: Fri, 24 Sep 2021 16:06:28 +0800
-Subject: [PATCH] dt-bindings: pinctrl: mt8195: add rsel define
-
-This patch adds rsel define for mt8195.
-
-Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
-Acked-by: Rob Herring <robh@kernel.org>
-Link: https://lore.kernel.org/r/20210924080632.28410-2-zhiyong.tao@mediatek.com
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- include/dt-bindings/pinctrl/mt65xx.h | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
---- a/include/dt-bindings/pinctrl/mt65xx.h
-+++ b/include/dt-bindings/pinctrl/mt65xx.h
-@@ -16,6 +16,15 @@
- #define MTK_PUPD_SET_R1R0_10 102
- #define MTK_PUPD_SET_R1R0_11 103
- 
-+#define MTK_PULL_SET_RSEL_000  200
-+#define MTK_PULL_SET_RSEL_001  201
-+#define MTK_PULL_SET_RSEL_010  202
-+#define MTK_PULL_SET_RSEL_011  203
-+#define MTK_PULL_SET_RSEL_100  204
-+#define MTK_PULL_SET_RSEL_101  205
-+#define MTK_PULL_SET_RSEL_110  206
-+#define MTK_PULL_SET_RSEL_111  207
-+
- #define MTK_DRIVE_2mA  2
- #define MTK_DRIVE_4mA  4
- #define MTK_DRIVE_6mA  6
diff --git a/target/linux/mediatek/patches-5.15/821-v5.16-pinctrl-mediatek-moore-check-if-pin_desc-is-valid-be.patch b/target/linux/mediatek/patches-5.15/821-v5.16-pinctrl-mediatek-moore-check-if-pin_desc-is-valid-be.patch
deleted file mode 100644
index aa9f879e3aa746..00000000000000
--- a/target/linux/mediatek/patches-5.15/821-v5.16-pinctrl-mediatek-moore-check-if-pin_desc-is-valid-be.patch
+++ /dev/null
@@ -1,93 +0,0 @@
-From d8b94c9ff96c2024a527086d850eb0b314337ff9 Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Tue, 14 Sep 2021 16:51:32 +0800
-Subject: [PATCH] pinctrl: mediatek: moore: check if pin_desc is valid before
- use
-
-Certain SoC are missing the middle part gpios in consecutive pins,
-it's better to check if mtk_pin_desc is a valid pin for the extensibility
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Acked-by: Sean Wang <sean.wang@mediatek.com>
-Link: https://lore.kernel.org/r/20210914085137.31761-5-sam.shih@mediatek.com
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- drivers/pinctrl/mediatek/pinctrl-moore.c | 18 ++++++++++++++++++
- 1 file changed, 18 insertions(+)
-
---- a/drivers/pinctrl/mediatek/pinctrl-moore.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-moore.c
-@@ -60,6 +60,8 @@ static int mtk_pinmux_set_mux(struct pin
- 		int pin = grp->pins[i];
- 
- 		desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
-+		if (!desc->name)
-+			return -ENOTSUPP;
- 
- 		mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
- 				 pin_modes[i]);
-@@ -76,6 +78,8 @@ static int mtk_pinmux_gpio_request_enabl
- 	const struct mtk_pin_desc *desc;
- 
- 	desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
-+	if (!desc->name)
-+		return -ENOTSUPP;
- 
- 	return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
- 				hw->soc->gpio_m);
-@@ -89,6 +93,8 @@ static int mtk_pinmux_gpio_set_direction
- 	const struct mtk_pin_desc *desc;
- 
- 	desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
-+	if (!desc->name)
-+		return -ENOTSUPP;
- 
- 	/* hardware would take 0 as input direction */
- 	return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !input);
-@@ -103,6 +109,8 @@ static int mtk_pinconf_get(struct pinctr
- 	const struct mtk_pin_desc *desc;
- 
- 	desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
-+	if (!desc->name)
-+		return -ENOTSUPP;
- 
- 	switch (param) {
- 	case PIN_CONFIG_BIAS_DISABLE:
-@@ -218,6 +226,8 @@ static int mtk_pinconf_set(struct pinctr
- 	int cfg, err = 0;
- 
- 	desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
-+	if (!desc->name)
-+		return -ENOTSUPP;
- 
- 	for (cfg = 0; cfg < num_configs; cfg++) {
- 		param = pinconf_to_config_param(configs[cfg]);
-@@ -435,6 +445,8 @@ static int mtk_gpio_get(struct gpio_chip
- 	int value, err;
- 
- 	desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
-+	if (!desc->name)
-+		return -ENOTSUPP;
- 
- 	err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value);
- 	if (err)
-@@ -449,6 +461,10 @@ static void mtk_gpio_set(struct gpio_chi
- 	const struct mtk_pin_desc *desc;
- 
- 	desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
-+	if (!desc->name) {
-+		dev_err(hw->dev, "Failed to set gpio %d\n", gpio);
-+		return;
-+	}
- 
- 	mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, !!value);
- }
-@@ -490,6 +506,8 @@ static int mtk_gpio_set_config(struct gp
- 	u32 debounce;
- 
- 	desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
-+	if (!desc->name)
-+		return -ENOTSUPP;
- 
- 	if (!hw->eint ||
- 	    pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE ||
diff --git a/target/linux/mediatek/patches-5.15/822-v5.16-pinctrl-mediatek-support-rsel-feature.patch b/target/linux/mediatek/patches-5.15/822-v5.16-pinctrl-mediatek-support-rsel-feature.patch
deleted file mode 100644
index 0f5c0495feffdb..00000000000000
--- a/target/linux/mediatek/patches-5.15/822-v5.16-pinctrl-mediatek-support-rsel-feature.patch
+++ /dev/null
@@ -1,457 +0,0 @@
-From fb34a9ae383ae26326d4889fd2513e49f1019b88 Mon Sep 17 00:00:00 2001
-From: Zhiyong Tao <zhiyong.tao@mediatek.com>
-Date: Fri, 24 Sep 2021 16:06:31 +0800
-Subject: [PATCH] pinctrl: mediatek: support rsel feature
-
-This patch supports rsel(resistance selection) feature for I2C pins.
-It provides more resistance selection solution in different ICs.
-It provides rsel define and si unit solution by identifying
-"mediatek,rsel_resistance_in_si_unit" property in pio dtsi node.
-
-Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
-Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
-Link: https://lore.kernel.org/r/20210924080632.28410-5-zhiyong.tao@mediatek.com
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- .../pinctrl/mediatek/pinctrl-mtk-common-v2.c  | 231 +++++++++++++++---
- .../pinctrl/mediatek/pinctrl-mtk-common-v2.h  |  46 ++++
- drivers/pinctrl/mediatek/pinctrl-paris.c      |  60 +++--
- 3 files changed, 289 insertions(+), 48 deletions(-)
-
---- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
-@@ -665,6 +665,181 @@ out:
- 	return err;
- }
- 
-+static int mtk_hw_pin_rsel_lookup(struct mtk_pinctrl *hw,
-+				  const struct mtk_pin_desc *desc,
-+				  u32 pullup, u32 arg, u32 *rsel_val)
-+{
-+	const struct mtk_pin_rsel *rsel;
-+	int check;
-+	bool found = false;
-+
-+	rsel = hw->soc->pin_rsel;
-+
-+	for (check = 0; check <= hw->soc->npin_rsel - 1; check++) {
-+		if (desc->number >= rsel[check].s_pin &&
-+		    desc->number <= rsel[check].e_pin) {
-+			if (pullup) {
-+				if (rsel[check].up_rsel == arg) {
-+					found = true;
-+					*rsel_val = rsel[check].rsel_index;
-+					break;
-+				}
-+			} else {
-+				if (rsel[check].down_rsel == arg) {
-+					found = true;
-+					*rsel_val = rsel[check].rsel_index;
-+					break;
-+				}
-+			}
-+		}
-+	}
-+
-+	if (!found) {
-+		dev_err(hw->dev, "Not support rsel value %d Ohm for pin = %d (%s)\n",
-+			arg, desc->number, desc->name);
-+		return -ENOTSUPP;
-+	}
-+
-+	return 0;
-+}
-+
-+static int mtk_pinconf_bias_set_rsel(struct mtk_pinctrl *hw,
-+				     const struct mtk_pin_desc *desc,
-+				     u32 pullup, u32 arg)
-+{
-+	int err, rsel_val;
-+
-+	if (hw->rsel_si_unit) {
-+		/* find pin rsel_index from pin_rsel array*/
-+		err = mtk_hw_pin_rsel_lookup(hw, desc, pullup, arg, &rsel_val);
-+		if (err)
-+			goto out;
-+	} else {
-+		if (arg < MTK_PULL_SET_RSEL_000 ||
-+		    arg > MTK_PULL_SET_RSEL_111) {
-+			err = -EINVAL;
-+			goto out;
-+		}
-+
-+		rsel_val = arg - MTK_PULL_SET_RSEL_000;
-+	}
-+
-+	err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_RSEL, rsel_val);
-+	if (err)
-+		goto out;
-+
-+	err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, MTK_ENABLE);
-+
-+out:
-+	return err;
-+}
-+
-+int mtk_pinconf_bias_set_combo(struct mtk_pinctrl *hw,
-+			       const struct mtk_pin_desc *desc,
-+			       u32 pullup, u32 arg)
-+{
-+	int err = -ENOTSUPP;
-+	u32 try_all_type;
-+
-+	if (hw->soc->pull_type)
-+		try_all_type = hw->soc->pull_type[desc->number];
-+	else
-+		try_all_type = MTK_PULL_TYPE_MASK;
-+
-+	if (try_all_type & MTK_PULL_RSEL_TYPE) {
-+		err = mtk_pinconf_bias_set_rsel(hw, desc, pullup, arg);
-+		if (!err)
-+			return err;
-+	}
-+
-+	if (try_all_type & MTK_PULL_PU_PD_TYPE) {
-+		err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg);
-+		if (!err)
-+			return err;
-+	}
-+
-+	if (try_all_type & MTK_PULL_PULLSEL_TYPE) {
-+		err = mtk_pinconf_bias_set_pullsel_pullen(hw, desc,
-+							  pullup, arg);
-+		if (!err)
-+			return err;
-+	}
-+
-+	if (try_all_type & MTK_PULL_PUPD_R1R0_TYPE)
-+		err = mtk_pinconf_bias_set_pupd_r1_r0(hw, desc, pullup, arg);
-+
-+	if (err)
-+		dev_err(hw->dev, "Invalid pull argument\n");
-+
-+	return err;
-+}
-+EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set_combo);
-+
-+static int mtk_rsel_get_si_unit(struct mtk_pinctrl *hw,
-+				const struct mtk_pin_desc *desc,
-+				u32 pullup, u32 rsel_val, u32 *si_unit)
-+{
-+	const struct mtk_pin_rsel *rsel;
-+	int check;
-+
-+	rsel = hw->soc->pin_rsel;
-+
-+	for (check = 0; check <= hw->soc->npin_rsel - 1; check++) {
-+		if (desc->number >= rsel[check].s_pin &&
-+		    desc->number <= rsel[check].e_pin) {
-+			if (rsel_val == rsel[check].rsel_index) {
-+				if (pullup)
-+					*si_unit = rsel[check].up_rsel;
-+				else
-+					*si_unit = rsel[check].down_rsel;
-+				break;
-+			}
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int mtk_pinconf_bias_get_rsel(struct mtk_pinctrl *hw,
-+				     const struct mtk_pin_desc *desc,
-+				     u32 *pullup, u32 *enable)
-+{
-+	int pu, pd, rsel, err;
-+
-+	err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_RSEL, &rsel);
-+	if (err)
-+		goto out;
-+
-+	err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PU, &pu);
-+	if (err)
-+		goto out;
-+
-+	err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &pd);
-+
-+	if (pu == 0 && pd == 0) {
-+		*pullup = 0;
-+		*enable = MTK_DISABLE;
-+	} else if (pu == 1 && pd == 0) {
-+		*pullup = 1;
-+		if (hw->rsel_si_unit)
-+			mtk_rsel_get_si_unit(hw, desc, *pullup, rsel, enable);
-+		else
-+			*enable = rsel + MTK_PULL_SET_RSEL_000;
-+	} else if (pu == 0 && pd == 1) {
-+		*pullup = 0;
-+		if (hw->rsel_si_unit)
-+			mtk_rsel_get_si_unit(hw, desc, *pullup, rsel, enable);
-+		else
-+			*enable = rsel + MTK_PULL_SET_RSEL_000;
-+	} else {
-+		err = -EINVAL;
-+		goto out;
-+	}
-+
-+out:
-+	return err;
-+}
-+
- static int mtk_pinconf_bias_get_pu_pd(struct mtk_pinctrl *hw,
- 				const struct mtk_pin_desc *desc,
- 				u32 *pullup, u32 *enable)
-@@ -746,44 +921,40 @@ out:
- 	return err;
- }
- 
--int mtk_pinconf_bias_set_combo(struct mtk_pinctrl *hw,
--				const struct mtk_pin_desc *desc,
--				u32 pullup, u32 arg)
--{
--	int err;
--
--	err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg);
--	if (!err)
--		goto out;
--
--	err = mtk_pinconf_bias_set_pullsel_pullen(hw, desc, pullup, arg);
--	if (!err)
--		goto out;
--
--	err = mtk_pinconf_bias_set_pupd_r1_r0(hw, desc, pullup, arg);
--
--out:
--	return err;
--}
--EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set_combo);
--
- int mtk_pinconf_bias_get_combo(struct mtk_pinctrl *hw,
- 			      const struct mtk_pin_desc *desc,
- 			      u32 *pullup, u32 *enable)
- {
--	int err;
-+	int err = -ENOTSUPP;
-+	u32 try_all_type;
- 
--	err = mtk_pinconf_bias_get_pu_pd(hw, desc, pullup, enable);
--	if (!err)
--		goto out;
-+	if (hw->soc->pull_type)
-+		try_all_type = hw->soc->pull_type[desc->number];
-+	else
-+		try_all_type = MTK_PULL_TYPE_MASK;
- 
--	err = mtk_pinconf_bias_get_pullsel_pullen(hw, desc, pullup, enable);
--	if (!err)
--		goto out;
-+	if (try_all_type & MTK_PULL_RSEL_TYPE) {
-+		err = mtk_pinconf_bias_get_rsel(hw, desc, pullup, enable);
-+		if (!err)
-+			return err;
-+	}
-+
-+	if (try_all_type & MTK_PULL_PU_PD_TYPE) {
-+		err = mtk_pinconf_bias_get_pu_pd(hw, desc, pullup, enable);
-+		if (!err)
-+			return err;
-+	}
-+
-+	if (try_all_type & MTK_PULL_PULLSEL_TYPE) {
-+		err = mtk_pinconf_bias_get_pullsel_pullen(hw, desc,
-+							  pullup, enable);
-+		if (!err)
-+			return err;
-+	}
- 
--	err = mtk_pinconf_bias_get_pupd_r1_r0(hw, desc, pullup, enable);
-+	if (try_all_type & MTK_PULL_PUPD_R1R0_TYPE)
-+		err = mtk_pinconf_bias_get_pupd_r1_r0(hw, desc, pullup, enable);
- 
--out:
- 	return err;
- }
- EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get_combo);
---- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
-+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
-@@ -17,6 +17,22 @@
- #define MTK_ENABLE     1
- #define MTK_PULLDOWN   0
- #define MTK_PULLUP     1
-+#define MTK_PULL_PU_PD_TYPE		BIT(0)
-+#define MTK_PULL_PULLSEL_TYPE		BIT(1)
-+#define MTK_PULL_PUPD_R1R0_TYPE		BIT(2)
-+/* MTK_PULL_RSEL_TYPE can select resistance and can be
-+ * turned on/off itself. But it can't be selected pull up/down
-+ */
-+#define MTK_PULL_RSEL_TYPE		BIT(3)
-+/* MTK_PULL_PU_PD_RSEL_TYPE is a type which is controlled by
-+ * MTK_PULL_PU_PD_TYPE and MTK_PULL_RSEL_TYPE.
-+ */
-+#define MTK_PULL_PU_PD_RSEL_TYPE	(MTK_PULL_PU_PD_TYPE \
-+					| MTK_PULL_RSEL_TYPE)
-+#define MTK_PULL_TYPE_MASK	(MTK_PULL_PU_PD_TYPE |\
-+				 MTK_PULL_PULLSEL_TYPE |\
-+				 MTK_PULL_PUPD_R1R0_TYPE |\
-+				 MTK_PULL_RSEL_TYPE)
- 
- #define EINT_NA	U16_MAX
- #define NO_EINT_SUPPORT	EINT_NA
-@@ -42,6 +58,14 @@
- 	PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit,	\
- 		       _x_bits, 32, 1)
- 
-+#define PIN_RSEL(_s_pin, _e_pin, _rsel_index, _up_resl, _down_rsel) {	\
-+		.s_pin = _s_pin,					\
-+		.e_pin = _e_pin,					\
-+		.rsel_index = _rsel_index,				\
-+		.up_rsel = _up_resl,					\
-+		.down_rsel = _down_rsel,				\
-+	}
-+
- /* List these attributes which could be modified for the pin */
- enum {
- 	PINCTRL_PIN_REG_MODE,
-@@ -67,6 +91,7 @@ enum {
- 	PINCTRL_PIN_REG_DRV_E0,
- 	PINCTRL_PIN_REG_DRV_E1,
- 	PINCTRL_PIN_REG_DRV_ADV,
-+	PINCTRL_PIN_REG_RSEL,
- 	PINCTRL_PIN_REG_MAX,
- };
- 
-@@ -129,6 +154,22 @@ struct mtk_pin_field_calc {
- 	u8  fixed;
- };
- 
-+/**
-+ * struct mtk_pin_rsel - the structure that provides bias resistance selection.
-+ * @s_pin:		the start pin within the rsel range
-+ * @e_pin:		the end pin within the rsel range
-+ * @rsel_index:	the rsel bias resistance index
-+ * @up_rsel:	the pullup rsel bias resistance value
-+ * @down_rsel:	the pulldown rsel bias resistance value
-+ */
-+struct mtk_pin_rsel {
-+	u16 s_pin;
-+	u16 e_pin;
-+	u16 rsel_index;
-+	u32 up_rsel;
-+	u32 down_rsel;
-+};
-+
- /* struct mtk_pin_reg_calc - the structure that holds all ranges used to
-  *			     determine which register the pin would make use of
-  *			     for certain pin attribute.
-@@ -206,6 +247,9 @@ struct mtk_pin_soc {
- 	bool				ies_present;
- 	const char * const		*base_names;
- 	unsigned int			nbase_names;
-+	const unsigned int		*pull_type;
-+	const struct mtk_pin_rsel	*pin_rsel;
-+	unsigned int			npin_rsel;
- 
- 	/* Specific pinconfig operations */
- 	int (*bias_disable_set)(struct mtk_pinctrl *hw,
-@@ -254,6 +298,8 @@ struct mtk_pinctrl {
- 	const char          **grp_names;
- 	/* lock pin's register resource to avoid multiple threads issue*/
- 	spinlock_t lock;
-+	/* identify rsel setting by si unit or rsel define in dts node */
-+	bool rsel_si_unit;
- };
- 
- void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set);
---- a/drivers/pinctrl/mediatek/pinctrl-paris.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-paris.c
-@@ -574,8 +574,9 @@ static int mtk_hw_get_value_wrap(struct
- ssize_t mtk_pctrl_show_one_pin(struct mtk_pinctrl *hw,
- 	unsigned int gpio, char *buf, unsigned int buf_len)
- {
--	int pinmux, pullup = 0, pullen = 0, len = 0, r1 = -1, r0 = -1;
-+	int pinmux, pullup = 0, pullen = 0, len = 0, r1 = -1, r0 = -1, rsel = -1;
- 	const struct mtk_pin_desc *desc;
-+	u32 try_all_type;
- 
- 	if (gpio >= hw->soc->npins)
- 		return -EINVAL;
-@@ -589,24 +590,39 @@ ssize_t mtk_pctrl_show_one_pin(struct mt
- 		pinmux -= hw->soc->nfuncs;
- 
- 	mtk_pinconf_bias_get_combo(hw, desc, &pullup, &pullen);
--	if (pullen == MTK_PUPD_SET_R1R0_00) {
--		pullen = 0;
--		r1 = 0;
--		r0 = 0;
--	} else if (pullen == MTK_PUPD_SET_R1R0_01) {
--		pullen = 1;
--		r1 = 0;
--		r0 = 1;
--	} else if (pullen == MTK_PUPD_SET_R1R0_10) {
--		pullen = 1;
--		r1 = 1;
--		r0 = 0;
--	} else if (pullen == MTK_PUPD_SET_R1R0_11) {
-+
-+	if (hw->soc->pull_type)
-+		try_all_type = hw->soc->pull_type[desc->number];
-+
-+	if (hw->rsel_si_unit && (try_all_type & MTK_PULL_RSEL_TYPE)) {
-+		rsel = pullen;
- 		pullen = 1;
--		r1 = 1;
--		r0 = 1;
--	} else if (pullen != MTK_DISABLE && pullen != MTK_ENABLE) {
--		pullen = 0;
-+	} else {
-+		/* Case for: R1R0 */
-+		if (pullen == MTK_PUPD_SET_R1R0_00) {
-+			pullen = 0;
-+			r1 = 0;
-+			r0 = 0;
-+		} else if (pullen == MTK_PUPD_SET_R1R0_01) {
-+			pullen = 1;
-+			r1 = 0;
-+			r0 = 1;
-+		} else if (pullen == MTK_PUPD_SET_R1R0_10) {
-+			pullen = 1;
-+			r1 = 1;
-+			r0 = 0;
-+		} else if (pullen == MTK_PUPD_SET_R1R0_11) {
-+			pullen = 1;
-+			r1 = 1;
-+			r0 = 1;
-+		}
-+
-+		/* Case for: RSEL */
-+		if (pullen >= MTK_PULL_SET_RSEL_000 &&
-+		    pullen <= MTK_PULL_SET_RSEL_111) {
-+			rsel = pullen - MTK_PULL_SET_RSEL_000;
-+			pullen = 1;
-+		}
- 	}
- 	len += scnprintf(buf + len, buf_len - len,
- 			"%03d: %1d%1d%1d%1d%02d%1d%1d%1d%1d",
-@@ -624,6 +640,8 @@ ssize_t mtk_pctrl_show_one_pin(struct mt
- 	if (r1 != -1) {
- 		len += scnprintf(buf + len, buf_len - len, " (%1d %1d)\n",
- 			r1, r0);
-+	} else if (rsel != -1) {
-+		len += scnprintf(buf + len, buf_len - len, " (%1d)\n", rsel);
- 	} else {
- 		len += scnprintf(buf + len, buf_len - len, "\n");
- 	}
-@@ -966,6 +984,12 @@ int mtk_paris_pinctrl_probe(struct platf
- 
- 	hw->nbase = hw->soc->nbase_names;
- 
-+	if (of_find_property(hw->dev->of_node,
-+			     "mediatek,rsel_resistance_in_si_unit", NULL))
-+		hw->rsel_si_unit = true;
-+	else
-+		hw->rsel_si_unit = false;
-+
- 	spin_lock_init(&hw->lock);
- 
- 	err = mtk_pctrl_build_state(pdev);
diff --git a/target/linux/mediatek/patches-5.15/823-v5.17-pinctrl-mediatek-add-a-check-for-error-in-mtk_pincon.patch b/target/linux/mediatek/patches-5.15/823-v5.17-pinctrl-mediatek-add-a-check-for-error-in-mtk_pincon.patch
deleted file mode 100644
index 6752b4093b4175..00000000000000
--- a/target/linux/mediatek/patches-5.15/823-v5.17-pinctrl-mediatek-add-a-check-for-error-in-mtk_pincon.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From 9f9d17c228c89e38ed612500126daf626270be9a Mon Sep 17 00:00:00 2001
-From: Dan Carpenter <dan.carpenter@oracle.com>
-Date: Sat, 27 Nov 2021 17:08:36 +0300
-Subject: [PATCH] pinctrl: mediatek: add a check for error in
- mtk_pinconf_bias_get_rsel()
-
-All the other mtk_hw_get_value() calls have a check for "if (err)" so
-we can add one here as well.  This silences a Smatch warning:
-
-    drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c:819 mtk_pinconf_bias_get_rsel()
-    error: uninitialized symbol 'pd'.
-
-Fixes: fb34a9ae383a ("pinctrl: mediatek: support rsel feature")
-Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
-Link: https://lore.kernel.org/r/20211127140836.GB24002@kili
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
-@@ -815,6 +815,8 @@ static int mtk_pinconf_bias_get_rsel(str
- 		goto out;
- 
- 	err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &pd);
-+	if (err)
-+		goto out;
- 
- 	if (pu == 0 && pd == 0) {
- 		*pullup = 0;
diff --git a/target/linux/mediatek/patches-5.15/824-v6.1-pinctrl-mediatek-Fix-EINT-pins-input-debounce-time-c.patch b/target/linux/mediatek/patches-5.15/824-v6.1-pinctrl-mediatek-Fix-EINT-pins-input-debounce-time-c.patch
deleted file mode 100644
index 47a29fbdba442a..00000000000000
--- a/target/linux/mediatek/patches-5.15/824-v6.1-pinctrl-mediatek-Fix-EINT-pins-input-debounce-time-c.patch
+++ /dev/null
@@ -1,297 +0,0 @@
-From e1ff91f9d2303cd4e706cc908bfca21cd17b9927 Mon Sep 17 00:00:00 2001
-From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Date: Fri, 11 Nov 2022 10:41:06 +0100
-Subject: [PATCH] pinctrl: mediatek: Fix EINT pins input debounce time
- configuration
-
-The External Interrupt Controller (EINTC) on all of the supported
-MediaTek SoCs does support input debouncing, but not all of them
-index the debounce time values (DBNC_SETTING registers) the same way.
-
-Before this change, in some cases, as an example, requesting a debounce
-time of 16 milliseconds would mistakenly set the relative DBNC_SETTING
-register to 0x2, resulting in a way shorter debounce time of 500uS.
-
-To fix the aforementioned issue, define three different debounce_time
-arrays, reflecting the correct register index for each value and for
-each register index variant, and make sure that each SoC pinctrl
-driver uses the right one.
-
-Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20221111094106.18486-1-angelogioacchino.delregno@collabora.com
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- drivers/pinctrl/mediatek/mtk-eint.c       | 31 +++++++++++++++++++----
- drivers/pinctrl/mediatek/mtk-eint.h       |  6 +++++
- drivers/pinctrl/mediatek/pinctrl-mt2701.c |  1 +
- drivers/pinctrl/mediatek/pinctrl-mt2712.c |  1 +
- drivers/pinctrl/mediatek/pinctrl-mt6765.c |  1 +
- drivers/pinctrl/mediatek/pinctrl-mt6779.c |  1 +
- drivers/pinctrl/mediatek/pinctrl-mt7622.c |  1 +
- drivers/pinctrl/mediatek/pinctrl-mt7623.c |  1 +
- drivers/pinctrl/mediatek/pinctrl-mt7629.c |  1 +
- drivers/pinctrl/mediatek/pinctrl-mt8127.c |  1 +
- drivers/pinctrl/mediatek/pinctrl-mt8135.c |  1 +
- drivers/pinctrl/mediatek/pinctrl-mt8167.c |  1 +
- drivers/pinctrl/mediatek/pinctrl-mt8173.c |  1 +
- drivers/pinctrl/mediatek/pinctrl-mt8183.c |  1 +
- drivers/pinctrl/mediatek/pinctrl-mt8192.c |  1 +
- drivers/pinctrl/mediatek/pinctrl-mt8195.c |  1 +
- drivers/pinctrl/mediatek/pinctrl-mt8365.c |  1 +
- drivers/pinctrl/mediatek/pinctrl-mt8516.c |  1 +
- 22 files changed, 53 insertions(+), 5 deletions(-)
-
---- a/drivers/pinctrl/mediatek/mtk-eint.c
-+++ b/drivers/pinctrl/mediatek/mtk-eint.c
-@@ -24,6 +24,7 @@
- #define MTK_EINT_EDGE_SENSITIVE           0
- #define MTK_EINT_LEVEL_SENSITIVE          1
- #define MTK_EINT_DBNC_SET_DBNC_BITS	  4
-+#define MTK_EINT_DBNC_MAX		  16
- #define MTK_EINT_DBNC_RST_BIT		  (0x1 << 1)
- #define MTK_EINT_DBNC_SET_EN		  (0x1 << 0)
- 
-@@ -48,6 +49,18 @@ static const struct mtk_eint_regs mtk_ge
- 	.dbnc_clr  = 0x700,
- };
- 
-+const unsigned int debounce_time_mt2701[] = {
-+	500, 1000, 16000, 32000, 64000, 128000, 256000, 0
-+};
-+
-+const unsigned int debounce_time_mt6765[] = {
-+	125, 250, 500, 1000, 16000, 32000, 64000, 128000, 256000, 512000, 0
-+};
-+
-+const unsigned int debounce_time_mt6795[] = {
-+	500, 1000, 16000, 32000, 64000, 128000, 256000, 512000, 0
-+};
-+
- static void __iomem *mtk_eint_get_offset(struct mtk_eint *eint,
- 					 unsigned int eint_num,
- 					 unsigned int offset)
-@@ -407,10 +420,11 @@ int mtk_eint_set_debounce(struct mtk_ein
- 	int virq, eint_offset;
- 	unsigned int set_offset, bit, clr_bit, clr_offset, rst, i, unmask,
- 		     dbnc;
--	static const unsigned int debounce_time[] = {500, 1000, 16000, 32000,
--						     64000, 128000, 256000};
- 	struct irq_data *d;
- 
-+	if (!eint->hw->db_time)
-+		return -EOPNOTSUPP;
-+
- 	virq = irq_find_mapping(eint->domain, eint_num);
- 	eint_offset = (eint_num % 4) * 8;
- 	d = irq_get_irq_data(virq);
-@@ -421,9 +435,9 @@ int mtk_eint_set_debounce(struct mtk_ein
- 	if (!mtk_eint_can_en_debounce(eint, eint_num))
- 		return -EINVAL;
- 
--	dbnc = ARRAY_SIZE(debounce_time);
--	for (i = 0; i < ARRAY_SIZE(debounce_time); i++) {
--		if (debounce <= debounce_time[i]) {
-+	dbnc = eint->num_db_time;
-+	for (i = 0; i < eint->num_db_time; i++) {
-+		if (debounce <= eint->hw->db_time[i]) {
- 			dbnc = i;
- 			break;
- 		}
-@@ -497,6 +511,13 @@ int mtk_eint_do_init(struct mtk_eint *ei
- 	if (!eint->domain)
- 		return -ENOMEM;
- 
-+	if (eint->hw->db_time) {
-+		for (i = 0; i < MTK_EINT_DBNC_MAX; i++)
-+			if (eint->hw->db_time[i] == 0)
-+				break;
-+		eint->num_db_time = i;
-+	}
-+
- 	mtk_eint_hw_init(eint);
- 	for (i = 0; i < eint->hw->ap_num; i++) {
- 		int virq = irq_create_mapping(eint->domain, i);
---- a/drivers/pinctrl/mediatek/mtk-eint.h
-+++ b/drivers/pinctrl/mediatek/mtk-eint.h
-@@ -37,8 +37,13 @@ struct mtk_eint_hw {
- 	u8		ports;
- 	unsigned int	ap_num;
- 	unsigned int	db_cnt;
-+	const unsigned int *db_time;
- };
- 
-+extern const unsigned int debounce_time_mt2701[];
-+extern const unsigned int debounce_time_mt6765[];
-+extern const unsigned int debounce_time_mt6795[];
-+
- struct mtk_eint;
- 
- struct mtk_eint_xt {
-@@ -62,6 +67,7 @@ struct mtk_eint {
- 	/* Used to fit into various EINT device */
- 	const struct mtk_eint_hw *hw;
- 	const struct mtk_eint_regs *regs;
-+	u16 num_db_time;
- 
- 	/* Used to fit into various pinctrl device */
- 	void *pctl;
---- a/drivers/pinctrl/mediatek/pinctrl-mt2701.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt2701.c
-@@ -531,6 +531,7 @@ static const struct mtk_pinctrl_devdata
- 		.ports     = 6,
- 		.ap_num    = 169,
- 		.db_cnt    = 16,
-+		.db_time   = debounce_time_mt2701,
- 	},
- };
- 
---- a/drivers/pinctrl/mediatek/pinctrl-mt2712.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt2712.c
-@@ -584,6 +584,7 @@ static const struct mtk_pinctrl_devdata
- 		.ports     = 8,
- 		.ap_num    = 229,
- 		.db_cnt    = 40,
-+		.db_time   = debounce_time_mt2701,
- 	},
- };
- 
---- a/drivers/pinctrl/mediatek/pinctrl-mt6765.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt6765.c
-@@ -1062,6 +1062,7 @@ static const struct mtk_eint_hw mt6765_e
- 	.ports     = 6,
- 	.ap_num    = 160,
- 	.db_cnt    = 13,
-+	.db_time   = debounce_time_mt6765,
- };
- 
- static const struct mtk_pin_soc mt6765_data = {
---- a/drivers/pinctrl/mediatek/pinctrl-mt6779.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt6779.c
-@@ -737,6 +737,7 @@ static const struct mtk_eint_hw mt6779_e
- 	.ports     = 6,
- 	.ap_num    = 195,
- 	.db_cnt    = 13,
-+	.db_time   = debounce_time_mt2701,
- };
- 
- static const struct mtk_pin_soc mt6779_data = {
---- a/drivers/pinctrl/mediatek/pinctrl-mt7622.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt7622.c
-@@ -846,6 +846,7 @@ static const struct mtk_eint_hw mt7622_e
- 	.ports     = 7,
- 	.ap_num    = ARRAY_SIZE(mt7622_pins),
- 	.db_cnt    = 20,
-+	.db_time   = debounce_time_mt6765,
- };
- 
- static const struct mtk_pin_soc mt7622_data = {
---- a/drivers/pinctrl/mediatek/pinctrl-mt7623.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt7623.c
-@@ -1369,6 +1369,7 @@ static const struct mtk_eint_hw mt7623_e
- 	.ports     = 6,
- 	.ap_num    = 169,
- 	.db_cnt    = 20,
-+	.db_time   = debounce_time_mt2701,
- };
- 
- static struct mtk_pin_soc mt7623_data = {
---- a/drivers/pinctrl/mediatek/pinctrl-mt7629.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt7629.c
-@@ -402,6 +402,7 @@ static const struct mtk_eint_hw mt7629_e
- 	.ports     = 7,
- 	.ap_num    = ARRAY_SIZE(mt7629_pins),
- 	.db_cnt    = 16,
-+	.db_time   = debounce_time_mt2701,
- };
- 
- static struct mtk_pin_soc mt7629_data = {
---- a/drivers/pinctrl/mediatek/pinctrl-mt8127.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt8127.c
-@@ -300,6 +300,7 @@ static const struct mtk_pinctrl_devdata
- 		.ports     = 6,
- 		.ap_num    = 143,
- 		.db_cnt    = 16,
-+		.db_time = debounce_time_mt2701,
- 	},
- };
- 
---- a/drivers/pinctrl/mediatek/pinctrl-mt8135.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt8135.c
-@@ -313,6 +313,7 @@ static const struct mtk_pinctrl_devdata
- 		.ports     = 6,
- 		.ap_num    = 192,
- 		.db_cnt    = 16,
-+		.db_time = debounce_time_mt2701,
- 	},
- };
- 
---- a/drivers/pinctrl/mediatek/pinctrl-mt8167.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt8167.c
-@@ -332,6 +332,7 @@ static const struct mtk_pinctrl_devdata
- 		.ports     = 6,
- 		.ap_num    = 169,
- 		.db_cnt    = 64,
-+		.db_time = debounce_time_mt6795,
- 	},
- };
- 
---- a/drivers/pinctrl/mediatek/pinctrl-mt8173.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt8173.c
-@@ -340,6 +340,7 @@ static const struct mtk_pinctrl_devdata
- 		.ports     = 6,
- 		.ap_num    = 224,
- 		.db_cnt    = 16,
-+		.db_time   = debounce_time_mt2701,
- 	},
- };
- 
---- a/drivers/pinctrl/mediatek/pinctrl-mt8183.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt8183.c
-@@ -545,6 +545,7 @@ static const struct mtk_eint_hw mt8183_e
- 	.ports     = 6,
- 	.ap_num    = 212,
- 	.db_cnt    = 13,
-+	.db_time   = debounce_time_mt6765,
- };
- 
- static const struct mtk_pin_soc mt8183_data = {
---- a/drivers/pinctrl/mediatek/pinctrl-mt8192.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt8192.c
-@@ -1339,6 +1339,7 @@ static const struct mtk_eint_hw mt8192_e
- 	.ports     = 7,
- 	.ap_num    = 224,
- 	.db_cnt    = 32,
-+	.db_time   = debounce_time_mt6765,
- };
- 
- static const struct mtk_pin_reg_calc mt8192_reg_cals[PINCTRL_PIN_REG_MAX] = {
---- a/drivers/pinctrl/mediatek/pinctrl-mt8195.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt8195.c
-@@ -805,6 +805,7 @@ static const struct mtk_eint_hw mt8195_e
- 	.ports     = 7,
- 	.ap_num    = 225,
- 	.db_cnt    = 32,
-+	.db_time   = debounce_time_mt6765,
- };
- 
- static const struct mtk_pin_soc mt8195_data = {
---- a/drivers/pinctrl/mediatek/pinctrl-mt8365.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt8365.c
-@@ -466,6 +466,7 @@ static const struct mtk_pinctrl_devdata
- 		.ports     = 5,
- 		.ap_num = 160,
- 		.db_cnt = 160,
-+		.db_time   = debounce_time_mt6765,
- 	},
- };
- 
---- a/drivers/pinctrl/mediatek/pinctrl-mt8516.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt8516.c
-@@ -332,6 +332,7 @@ static const struct mtk_pinctrl_devdata
- 		.ports     = 6,
- 		.ap_num    = 169,
- 		.db_cnt    = 64,
-+		.db_time   = debounce_time_mt6795,
- 	},
- };
- 
diff --git a/target/linux/mediatek/patches-5.15/825-v6.1-pinctrl-mediatek-Export-debounce-time-tables.patch b/target/linux/mediatek/patches-5.15/825-v6.1-pinctrl-mediatek-Export-debounce-time-tables.patch
deleted file mode 100644
index 92f4e842e8acc6..00000000000000
--- a/target/linux/mediatek/patches-5.15/825-v6.1-pinctrl-mediatek-Export-debounce-time-tables.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From 2e35b25dd8e666b8619355fc3defb1b246a5dc02 Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Tue, 15 Nov 2022 09:11:07 +0100
-Subject: [PATCH] pinctrl: mediatek: Export debounce time tables
-
-The kernel test robot complains that in certain combinations
-when building the Mediatek drivers as modules we lack some
-debounce table symbols, so export them.
-
-Reported-by: kernel test robot <lkp@intel.com>
-Fixes: e1ff91f9d230 ("pinctrl: mediatek: Fix EINT pins input debounce time configuration")
-Cc: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- drivers/pinctrl/mediatek/mtk-eint.c | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/drivers/pinctrl/mediatek/mtk-eint.c
-+++ b/drivers/pinctrl/mediatek/mtk-eint.c
-@@ -52,14 +52,17 @@ static const struct mtk_eint_regs mtk_ge
- const unsigned int debounce_time_mt2701[] = {
- 	500, 1000, 16000, 32000, 64000, 128000, 256000, 0
- };
-+EXPORT_SYMBOL_GPL(debounce_time_mt2701);
- 
- const unsigned int debounce_time_mt6765[] = {
- 	125, 250, 500, 1000, 16000, 32000, 64000, 128000, 256000, 512000, 0
- };
-+EXPORT_SYMBOL_GPL(debounce_time_mt6765);
- 
- const unsigned int debounce_time_mt6795[] = {
- 	500, 1000, 16000, 32000, 64000, 128000, 256000, 512000, 0
- };
-+EXPORT_SYMBOL_GPL(debounce_time_mt6795);
- 
- static void __iomem *mtk_eint_get_offset(struct mtk_eint *eint,
- 					 unsigned int eint_num,
diff --git a/target/linux/mediatek/patches-5.15/826-v6.2-pinctrl-mediatek-extend-pinctrl-moore-to-support-new.patch b/target/linux/mediatek/patches-5.15/826-v6.2-pinctrl-mediatek-extend-pinctrl-moore-to-support-new.patch
deleted file mode 100644
index f130fdbc566909..00000000000000
--- a/target/linux/mediatek/patches-5.15/826-v6.2-pinctrl-mediatek-extend-pinctrl-moore-to-support-new.patch
+++ /dev/null
@@ -1,129 +0,0 @@
-From fae82621ac33e2a4a96220c56e90d1ec6237d394 Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Sun, 6 Nov 2022 09:01:12 +0100
-Subject: [PATCH] pinctrl: mediatek: extend pinctrl-moore to support new bias
- functions
-
-Commit fb34a9ae383a ("pinctrl: mediatek: support rsel feature")
-introduced SoC specify 'pull_type' attribute to mtk_pinconf_bias_set_combo
-and mtk_pinconf_bias_get_combo, and make the functions able to support
-almost all Mediatek SoCs that use pinctrl-mtk-common-v2.c.
-
-This patch enables pinctrl_moore to support these functions.
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20221106080114.7426-6-linux@fw-web.de
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- drivers/pinctrl/mediatek/pinctrl-moore.c | 49 ++++++++++++++++++++----
- 1 file changed, 42 insertions(+), 7 deletions(-)
-
---- a/drivers/pinctrl/mediatek/pinctrl-moore.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-moore.c
-@@ -8,6 +8,7 @@
-  *
-  */
- 
-+#include <dt-bindings/pinctrl/mt65xx.h>
- #include <linux/gpio/driver.h>
- #include "pinctrl-moore.h"
- 
-@@ -105,7 +106,7 @@ static int mtk_pinconf_get(struct pinctr
- {
- 	struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
- 	u32 param = pinconf_to_config_param(*config);
--	int val, val2, err, reg, ret = 1;
-+	int val, val2, err, pullup, reg, ret = 1;
- 	const struct mtk_pin_desc *desc;
- 
- 	desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
-@@ -114,7 +115,13 @@ static int mtk_pinconf_get(struct pinctr
- 
- 	switch (param) {
- 	case PIN_CONFIG_BIAS_DISABLE:
--		if (hw->soc->bias_disable_get) {
-+		if (hw->soc->bias_get_combo) {
-+			err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret);
-+			if (err)
-+				return err;
-+			if (ret != MTK_PUPD_SET_R1R0_00 && ret != MTK_DISABLE)
-+				return -EINVAL;
-+		} else if (hw->soc->bias_disable_get) {
- 			err = hw->soc->bias_disable_get(hw, desc, &ret);
- 			if (err)
- 				return err;
-@@ -123,7 +130,15 @@ static int mtk_pinconf_get(struct pinctr
- 		}
- 		break;
- 	case PIN_CONFIG_BIAS_PULL_UP:
--		if (hw->soc->bias_get) {
-+		if (hw->soc->bias_get_combo) {
-+			err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret);
-+			if (err)
-+				return err;
-+			if (ret == MTK_PUPD_SET_R1R0_00 || ret == MTK_DISABLE)
-+				return -EINVAL;
-+			if (!pullup)
-+				return -EINVAL;
-+		} else if (hw->soc->bias_get) {
- 			err = hw->soc->bias_get(hw, desc, 1, &ret);
- 			if (err)
- 				return err;
-@@ -132,7 +147,15 @@ static int mtk_pinconf_get(struct pinctr
- 		}
- 		break;
- 	case PIN_CONFIG_BIAS_PULL_DOWN:
--		if (hw->soc->bias_get) {
-+		if (hw->soc->bias_get_combo) {
-+			err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret);
-+			if (err)
-+				return err;
-+			if (ret == MTK_PUPD_SET_R1R0_00 || ret == MTK_DISABLE)
-+				return -EINVAL;
-+			if (pullup)
-+				return -EINVAL;
-+		} else if (hw->soc->bias_get) {
- 			err = hw->soc->bias_get(hw, desc, 0, &ret);
- 			if (err)
- 				return err;
-@@ -235,7 +258,11 @@ static int mtk_pinconf_set(struct pinctr
- 
- 		switch (param) {
- 		case PIN_CONFIG_BIAS_DISABLE:
--			if (hw->soc->bias_disable_set) {
-+			if (hw->soc->bias_set_combo) {
-+				err = hw->soc->bias_set_combo(hw, desc, 0, MTK_DISABLE);
-+				if (err)
-+					return err;
-+			} else if (hw->soc->bias_disable_set) {
- 				err = hw->soc->bias_disable_set(hw, desc);
- 				if (err)
- 					return err;
-@@ -244,7 +271,11 @@ static int mtk_pinconf_set(struct pinctr
- 			}
- 			break;
- 		case PIN_CONFIG_BIAS_PULL_UP:
--			if (hw->soc->bias_set) {
-+			if (hw->soc->bias_set_combo) {
-+				err = hw->soc->bias_set_combo(hw, desc, 1, arg);
-+				if (err)
-+					return err;
-+			} else if (hw->soc->bias_set) {
- 				err = hw->soc->bias_set(hw, desc, 1);
- 				if (err)
- 					return err;
-@@ -253,7 +284,11 @@ static int mtk_pinconf_set(struct pinctr
- 			}
- 			break;
- 		case PIN_CONFIG_BIAS_PULL_DOWN:
--			if (hw->soc->bias_set) {
-+			if (hw->soc->bias_set_combo) {
-+				err = hw->soc->bias_set_combo(hw, desc, 0, arg);
-+				if (err)
-+					return err;
-+			} else if (hw->soc->bias_set) {
- 				err = hw->soc->bias_set(hw, desc, 0);
- 				if (err)
- 					return err;
diff --git a/target/linux/mediatek/patches-5.15/830-v5.18-regulator-Add-bindings-for-Richtek-RT5190A-PMIC.patch b/target/linux/mediatek/patches-5.15/830-v5.18-regulator-Add-bindings-for-Richtek-RT5190A-PMIC.patch
deleted file mode 100644
index 30891d34872b5f..00000000000000
--- a/target/linux/mediatek/patches-5.15/830-v5.18-regulator-Add-bindings-for-Richtek-RT5190A-PMIC.patch
+++ /dev/null
@@ -1,180 +0,0 @@
-From b77e70f6b8f2cc62fba847f3008a430a09ef275d Mon Sep 17 00:00:00 2001
-From: ChiYuan Huang <cy_huang@richtek.com>
-Date: Wed, 9 Mar 2022 16:01:42 +0800
-Subject: [PATCH 1/2] regulator: Add bindings for Richtek RT5190A PMIC
-
-Add bindings for Richtek RT5190A PMIC.
-
-Signed-off-by: ChiYuan Huang <cy_huang@richtek.com>
-Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
-Link: https://lore.kernel.org/r/1646812903-32496-2-git-send-email-u0084500@gmail.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- .../regulator/richtek,rt5190a-regulator.yaml  | 141 ++++++++++++++++++
- .../regulator/richtek,rt5190a-regulator.h     |  15 ++
- 2 files changed, 156 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/regulator/richtek,rt5190a-regulator.yaml
- create mode 100644 include/dt-bindings/regulator/richtek,rt5190a-regulator.h
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/regulator/richtek,rt5190a-regulator.yaml
-@@ -0,0 +1,141 @@
-+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/regulator/richtek,rt5190a-regulator.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: Richtek RT5190A PMIC Regulator
-+
-+maintainers:
-+  - ChiYuan Huang <cy_huang@richtek.com>
-+
-+description: |
-+  The RT5190A integrates 1 channel buck controller, 3 channels high efficiency
-+  synchronous buck converters, 1 LDO, I2C control interface and peripherial
-+  logical control.
-+
-+  It also supports mute AC OFF depop sound and quick setting storage while
-+  input power is removed.
-+
-+properties:
-+  compatible:
-+    enum:
-+      - richtek,rt5190a
-+
-+  reg:
-+    maxItems: 1
-+
-+  interrupts:
-+    maxItems: 1
-+
-+  vin2-supply:
-+    description: phandle to buck2 input voltage.
-+
-+  vin3-supply:
-+    description: phandle to buck3 input voltage.
-+
-+  vin4-supply:
-+    description: phandle to buck4 input voltage.
-+
-+  vinldo-supply:
-+    description: phandle to ldo input voltage
-+
-+  richtek,mute-enable:
-+    description: |
-+      The mute function uses 'mutein', 'muteout', and 'vdet' pins as the control
-+      signal. When enabled, The normal behavior is to bypass the 'mutein' signal
-+      'muteout'. But if the power source removal is detected from 'vdet',
-+      whatever the 'mutein' signal is, it will pull down the 'muteout' to force
-+      speakers mute. this function is commonly used to prevent the speaker pop
-+      noise during AC power turned off in the modern TV system design.
-+    type: boolean
-+
-+  regulators:
-+    type: object
-+
-+    patternProperties:
-+      "^buck[1-4]$|^ldo$":
-+        type: object
-+        $ref: regulator.yaml#
-+        description: |
-+          regulator description for buck1 and buck4.
-+
-+        properties:
-+          regulator-allowed-modes:
-+            description: |
-+             buck operating mode, only buck1/4 support mode operating.
-+              0: auto mode
-+              1: force pwm mode
-+            items:
-+              enum: [0, 1]
-+
-+          richtek,latchup-enable:
-+            type: boolean
-+            description: |
-+              If specified, undervolt protection mode changes from the default
-+              hiccup to latchup.
-+
-+        unevaluatedProperties: false
-+
-+    additionalProperties: false
-+
-+required:
-+  - compatible
-+  - reg
-+  - regulators
-+
-+additionalProperties: false
-+
-+examples:
-+  - |
-+    #include <dt-bindings/interrupt-controller/irq.h>
-+    #include <dt-bindings/regulator/richtek,rt5190a-regulator.h>
-+
-+    i2c {
-+      #address-cells = <1>;
-+      #size-cells = <0>;
-+
-+      pmic@64 {
-+        compatible = "richtek,rt5190a";
-+        reg = <0x64>;
-+        interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;
-+        vin2-supply = <&rt5190_buck1>;
-+        vin3-supply = <&rt5190_buck1>;
-+        vin4-supply = <&rt5190_buck1>;
-+
-+        regulators {
-+          rt5190_buck1: buck1 {
-+            regulator-name = "rt5190a-buck1";
-+            regulator-min-microvolt = <5090000>;
-+            regulator-max-microvolt = <5090000>;
-+            regulator-allowed-modes = <RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
-+            regulator-boot-on;
-+          };
-+          buck2 {
-+            regulator-name = "rt5190a-buck2";
-+            regulator-min-microvolt = <600000>;
-+            regulator-max-microvolt = <1400000>;
-+            regulator-boot-on;
-+          };
-+          buck3 {
-+            regulator-name = "rt5190a-buck3";
-+            regulator-min-microvolt = <600000>;
-+            regulator-max-microvolt = <1400000>;
-+            regulator-boot-on;
-+          };
-+          buck4 {
-+            regulator-name = "rt5190a-buck4";
-+            regulator-min-microvolt = <850000>;
-+            regulator-max-microvolt = <850000>;
-+            regulator-allowed-modes = <RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
-+            regulator-boot-on;
-+          };
-+          ldo {
-+            regulator-name = "rt5190a-ldo";
-+            regulator-min-microvolt = <1200000>;
-+            regulator-max-microvolt = <1200000>;
-+            regulator-boot-on;
-+          };
-+        };
-+      };
-+    };
---- /dev/null
-+++ b/include/dt-bindings/regulator/richtek,rt5190a-regulator.h
-@@ -0,0 +1,15 @@
-+/* SPDX-License-Identifier: GPL-2.0 */
-+
-+#ifndef __DT_BINDINGS_RICHTEK_RT5190A_REGULATOR_H__
-+#define __DT_BINDINGS_RICHTEK_RT5190A_REGULATOR_H__
-+
-+/*
-+ * BUCK/LDO mode constants which may be used in devicetree properties
-+ * (eg. regulator-allowed-modes).
-+ * See the manufacturer's datasheet for more information on these modes.
-+ */
-+
-+#define RT5190A_OPMODE_AUTO	0
-+#define RT5190A_OPMODE_FPWM	1
-+
-+#endif
diff --git a/target/linux/mediatek/patches-5.15/831-v5.18-regulator-rt5190a-Add-support-for-Richtek-RT5190A-PM.patch b/target/linux/mediatek/patches-5.15/831-v5.18-regulator-rt5190a-Add-support-for-Richtek-RT5190A-PM.patch
deleted file mode 100644
index 0e0f099e5058df..00000000000000
--- a/target/linux/mediatek/patches-5.15/831-v5.18-regulator-rt5190a-Add-support-for-Richtek-RT5190A-PM.patch
+++ /dev/null
@@ -1,562 +0,0 @@
-From 760423dfad53877b468490758fe7ea968ded9402 Mon Sep 17 00:00:00 2001
-From: ChiYuan Huang <cy_huang@richtek.com>
-Date: Wed, 9 Mar 2022 16:01:43 +0800
-Subject: [PATCH 2/2] regulator: rt5190a: Add support for Richtek RT5190A PMIC
-
-Add support for Richtek RT5190A PMIC.
-
-Signed-off-by: ChiYuan Huang <cy_huang@richtek.com>
-Link: https://lore.kernel.org/r/1646812903-32496-3-git-send-email-u0084500@gmail.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- drivers/regulator/Kconfig             |  10 +
- drivers/regulator/Makefile            |   1 +
- drivers/regulator/rt5190a-regulator.c | 513 ++++++++++++++++++++++++++
- 3 files changed, 524 insertions(+)
- create mode 100644 drivers/regulator/rt5190a-regulator.c
-
---- a/drivers/regulator/Kconfig
-+++ b/drivers/regulator/Kconfig
-@@ -1037,6 +1037,16 @@ config REGULATOR_RT5033
- 	  RT5033 PMIC. The device supports multiple regulators like
- 	  current source, LDO and Buck.
- 
-+config REGULATOR_RT5190A
-+	tristate "Richtek RT5190A PMIC"
-+	depends on I2C
-+	select REGMAP_I2C
-+	help
-+	  This adds support for voltage regulator in Richtek RT5190A PMIC.
-+	  It integratas 1 channel buck controller, 3 channels high efficiency
-+	  buck converters, 1 LDO, mute AC OFF depop function, with the general
-+	  I2C control interface.
-+
- config REGULATOR_RT6160
- 	tristate "Richtek RT6160 BuckBoost voltage regulator"
- 	depends on I2C
---- a/drivers/regulator/Makefile
-+++ b/drivers/regulator/Makefile
-@@ -125,6 +125,7 @@ obj-$(CONFIG_REGULATOR_ROHM)	+= rohm-reg
- obj-$(CONFIG_REGULATOR_RT4801)	+= rt4801-regulator.o
- obj-$(CONFIG_REGULATOR_RT4831)	+= rt4831-regulator.o
- obj-$(CONFIG_REGULATOR_RT5033)	+= rt5033-regulator.o
-+obj-$(CONFIG_REGULATOR_RT5190A) += rt5190a-regulator.o
- obj-$(CONFIG_REGULATOR_RT6160)	+= rt6160-regulator.o
- obj-$(CONFIG_REGULATOR_RT6245)	+= rt6245-regulator.o
- obj-$(CONFIG_REGULATOR_RTMV20)	+= rtmv20-regulator.o
---- /dev/null
-+++ b/drivers/regulator/rt5190a-regulator.c
-@@ -0,0 +1,513 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+
-+#include <dt-bindings/regulator/richtek,rt5190a-regulator.h>
-+#include <linux/bits.h>
-+#include <linux/i2c.h>
-+#include <linux/interrupt.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/property.h>
-+#include <linux/regmap.h>
-+#include <linux/regulator/driver.h>
-+#include <linux/regulator/machine.h>
-+#include <linux/regulator/of_regulator.h>
-+
-+#define RT5190A_REG_MANUFACTURE		0x00
-+#define RT5190A_REG_BUCK2VSEL		0x04
-+#define RT5190A_REG_BUCK3VSEL		0x05
-+#define RT5190A_REG_DCDCCNTL		0x06
-+#define RT5190A_REG_ENABLE		0x07
-+#define RT5190A_REG_DISCHARGE		0x09
-+#define RT5190A_REG_PROTMODE		0x0A
-+#define RT5190A_REG_MUTECNTL		0x0B
-+#define RT5190A_REG_PGSTAT		0x0F
-+#define RT5190A_REG_OVINT		0x10
-+#define RT5190A_REG_HOTDIEMASK		0x17
-+
-+#define RT5190A_VSEL_MASK		GENMASK(6, 0)
-+#define RT5190A_RID_BITMASK(rid)	BIT(rid + 1)
-+#define RT5190A_BUCK1_DISCHG_MASK	GENMASK(1, 0)
-+#define RT5190A_BUCK1_DISCHG_ONVAL	0x01
-+#define RT5190A_OVERVOLT_MASK		GENMASK(7, 0)
-+#define RT5190A_UNDERVOLT_MASK		GENMASK(15, 8)
-+#define RT5190A_CH234OT_MASK		BIT(29)
-+#define RT5190A_CHIPOT_MASK		BIT(28)
-+
-+#define RT5190A_BUCK23_MINUV		600000
-+#define RT5190A_BUCK23_MAXUV		1400000
-+#define RT5190A_BUCK23_STEPUV		10000
-+#define RT5190A_BUCK23_STEPNUM		((1400000 - 600000) / 10000 + 1)
-+
-+enum {
-+	RT5190A_IDX_BUCK1 = 0,
-+	RT5190A_IDX_BUCK2,
-+	RT5190A_IDX_BUCK3,
-+	RT5190A_IDX_BUCK4,
-+	RT5190A_IDX_LDO,
-+	RT5190A_MAX_IDX
-+};
-+
-+struct rt5190a_priv {
-+	struct device *dev;
-+	struct regmap *regmap;
-+	struct regulator_desc rdesc[RT5190A_MAX_IDX];
-+	struct regulator_dev *rdev[RT5190A_MAX_IDX];
-+};
-+
-+static int rt5190a_get_error_flags(struct regulator_dev *rdev,
-+				   unsigned int *flags)
-+{
-+	struct regmap *regmap = rdev_get_regmap(rdev);
-+	int rid = rdev_get_id(rdev);
-+	unsigned int pgood_stat;
-+	int ret;
-+
-+	ret = regmap_read(regmap, RT5190A_REG_PGSTAT, &pgood_stat);
-+	if (ret)
-+		return ret;
-+
-+	if (!(pgood_stat & RT5190A_RID_BITMASK(rid)))
-+		*flags = REGULATOR_ERROR_FAIL;
-+	else
-+		*flags = 0;
-+
-+	return 0;
-+}
-+
-+static int rt5190a_fixed_buck_set_mode(struct regulator_dev *rdev,
-+				       unsigned int mode)
-+{
-+	struct regmap *regmap = rdev_get_regmap(rdev);
-+	int rid = rdev_get_id(rdev);
-+	unsigned int mask = RT5190A_RID_BITMASK(rid), val;
-+
-+	switch (mode) {
-+	case REGULATOR_MODE_FAST:
-+		val = mask;
-+		break;
-+	case REGULATOR_MODE_NORMAL:
-+		val = 0;
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	return regmap_update_bits(regmap, RT5190A_REG_DCDCCNTL, mask, val);
-+}
-+
-+static unsigned int rt5190a_fixed_buck_get_mode(struct regulator_dev *rdev)
-+{
-+	struct regmap *regmap = rdev_get_regmap(rdev);
-+	int rid = rdev_get_id(rdev);
-+	unsigned int val;
-+	int ret;
-+
-+	ret = regmap_read(regmap, RT5190A_REG_DCDCCNTL, &val);
-+	if (ret) {
-+		dev_err(&rdev->dev, "Failed to get mode [%d]\n", ret);
-+		return ret;
-+	}
-+
-+	if (val & RT5190A_RID_BITMASK(rid))
-+		return REGULATOR_MODE_FAST;
-+
-+	return REGULATOR_MODE_NORMAL;
-+}
-+
-+static const struct regulator_ops rt5190a_ranged_buck_ops = {
-+	.enable	= regulator_enable_regmap,
-+	.disable = regulator_disable_regmap,
-+	.is_enabled = regulator_is_enabled_regmap,
-+	.set_voltage_sel = regulator_set_voltage_sel_regmap,
-+	.get_voltage_sel = regulator_get_voltage_sel_regmap,
-+	.list_voltage = regulator_list_voltage_linear,
-+	.set_active_discharge = regulator_set_active_discharge_regmap,
-+	.get_error_flags = rt5190a_get_error_flags,
-+};
-+
-+static const struct regulator_ops rt5190a_fixed_buck_ops = {
-+	.enable	= regulator_enable_regmap,
-+	.disable = regulator_disable_regmap,
-+	.is_enabled = regulator_is_enabled_regmap,
-+	.set_active_discharge = regulator_set_active_discharge_regmap,
-+	.set_mode = rt5190a_fixed_buck_set_mode,
-+	.get_mode = rt5190a_fixed_buck_get_mode,
-+	.get_error_flags = rt5190a_get_error_flags,
-+};
-+
-+static const struct regulator_ops rt5190a_fixed_ldo_ops = {
-+	.enable	= regulator_enable_regmap,
-+	.disable = regulator_disable_regmap,
-+	.is_enabled = regulator_is_enabled_regmap,
-+	.set_active_discharge = regulator_set_active_discharge_regmap,
-+	.get_error_flags = rt5190a_get_error_flags,
-+};
-+
-+static irqreturn_t rt5190a_irq_handler(int irq, void *data)
-+{
-+	struct rt5190a_priv *priv = data;
-+	__le32 raws;
-+	unsigned int events, fields;
-+	static const struct {
-+		unsigned int bitmask;
-+		unsigned int report;
-+	} event_tbl[] = {
-+		{ RT5190A_OVERVOLT_MASK, REGULATOR_ERROR_REGULATION_OUT },
-+		{ RT5190A_UNDERVOLT_MASK, REGULATOR_ERROR_UNDER_VOLTAGE }
-+	};
-+	int i, j, ret;
-+
-+	ret = regmap_raw_read(priv->regmap, RT5190A_REG_OVINT, &raws,
-+			      sizeof(raws));
-+	if (ret) {
-+		dev_err(priv->dev, "Failed to read events\n");
-+		return IRQ_NONE;
-+	}
-+
-+	events = le32_to_cpu(raws);
-+
-+	ret = regmap_raw_write(priv->regmap, RT5190A_REG_OVINT, &raws,
-+			       sizeof(raws));
-+	if (ret)
-+		dev_err(priv->dev, "Failed to write-clear events\n");
-+
-+	/* Handle OV,UV events */
-+	for (i = 0; i < ARRAY_SIZE(event_tbl); i++) {
-+		fields = events & event_tbl[i].bitmask;
-+		fields >>= ffs(event_tbl[i].bitmask) - 1;
-+
-+		for (j = 0; j < RT5190A_MAX_IDX; j++) {
-+			if (!(fields & RT5190A_RID_BITMASK(j)))
-+				continue;
-+
-+			regulator_notifier_call_chain(priv->rdev[j],
-+						      event_tbl[i].report,
-+						      NULL);
-+		}
-+	}
-+
-+	/* Handle CH234 OT event */
-+	if (events & RT5190A_CH234OT_MASK) {
-+		for (j = RT5190A_IDX_BUCK2; j < RT5190A_IDX_LDO; j++) {
-+			regulator_notifier_call_chain(priv->rdev[j],
-+						      REGULATOR_ERROR_OVER_TEMP,
-+						      NULL);
-+		}
-+	}
-+
-+	/* Warning if CHIP OT occur */
-+	if (events & RT5190A_CHIPOT_MASK)
-+		dev_warn(priv->dev, "CHIP overheat\n");
-+
-+	return IRQ_HANDLED;
-+}
-+
-+static unsigned int rt5190a_of_map_mode(unsigned int mode)
-+{
-+	switch (mode) {
-+	case RT5190A_OPMODE_AUTO:
-+		return REGULATOR_MODE_NORMAL;
-+	case RT5190A_OPMODE_FPWM:
-+		return REGULATOR_MODE_FAST;
-+	default:
-+		return REGULATOR_MODE_INVALID;
-+	}
-+}
-+
-+static int rt5190a_of_parse_cb(struct rt5190a_priv *priv, int rid,
-+			       struct of_regulator_match *match)
-+{
-+	struct regulator_desc *desc = priv->rdesc + rid;
-+	struct regulator_init_data *init_data = match->init_data;
-+	struct device_node *np = match->of_node;
-+	bool latchup_enable;
-+	unsigned int mask = RT5190A_RID_BITMASK(rid), val;
-+
-+	switch (rid) {
-+	case RT5190A_IDX_BUCK1:
-+	case RT5190A_IDX_BUCK4:
-+	case RT5190A_IDX_LDO:
-+		init_data->constraints.apply_uV = 0;
-+
-+		if (init_data->constraints.min_uV ==
-+				init_data->constraints.max_uV)
-+			desc->fixed_uV = init_data->constraints.min_uV;
-+		else {
-+			dev_err(priv->dev,
-+				"Variable voltage for fixed regulator\n");
-+			return -EINVAL;
-+		}
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	latchup_enable = of_property_read_bool(np, "richtek,latchup-enable");
-+
-+	/* latchup: 0, default hiccup: 1 */
-+	val = !latchup_enable ? mask : 0;
-+
-+	return regmap_update_bits(priv->regmap, RT5190A_REG_PROTMODE, mask, val);
-+}
-+
-+static void rt5190a_fillin_regulator_desc(struct regulator_desc *desc, int rid)
-+{
-+	static const char * const regu_name[] = { "buck1", "buck2",
-+						  "buck3", "buck4",
-+						  "ldo" };
-+	static const char * const supply[] = { NULL, "vin2", "vin3", "vin4",
-+					       "vinldo" };
-+
-+	desc->name = regu_name[rid];
-+	desc->supply_name = supply[rid];
-+	desc->owner = THIS_MODULE;
-+	desc->type = REGULATOR_VOLTAGE;
-+	desc->id = rid;
-+	desc->enable_reg = RT5190A_REG_ENABLE;
-+	desc->enable_mask = RT5190A_RID_BITMASK(rid);
-+	desc->active_discharge_reg = RT5190A_REG_DISCHARGE;
-+	desc->active_discharge_mask = RT5190A_RID_BITMASK(rid);
-+	desc->active_discharge_on = RT5190A_RID_BITMASK(rid);
-+
-+	switch (rid) {
-+	case RT5190A_IDX_BUCK1:
-+		desc->active_discharge_mask = RT5190A_BUCK1_DISCHG_MASK;
-+		desc->active_discharge_on = RT5190A_BUCK1_DISCHG_ONVAL;
-+		desc->n_voltages = 1;
-+		desc->ops = &rt5190a_fixed_buck_ops;
-+		desc->of_map_mode = rt5190a_of_map_mode;
-+		break;
-+	case RT5190A_IDX_BUCK2:
-+		desc->vsel_reg = RT5190A_REG_BUCK2VSEL;
-+		desc->vsel_mask = RT5190A_VSEL_MASK;
-+		desc->min_uV = RT5190A_BUCK23_MINUV;
-+		desc->uV_step = RT5190A_BUCK23_STEPUV;
-+		desc->n_voltages = RT5190A_BUCK23_STEPNUM;
-+		desc->ops = &rt5190a_ranged_buck_ops;
-+		break;
-+	case RT5190A_IDX_BUCK3:
-+		desc->vsel_reg = RT5190A_REG_BUCK3VSEL;
-+		desc->vsel_mask = RT5190A_VSEL_MASK;
-+		desc->min_uV = RT5190A_BUCK23_MINUV;
-+		desc->uV_step = RT5190A_BUCK23_STEPUV;
-+		desc->n_voltages = RT5190A_BUCK23_STEPNUM;
-+		desc->ops = &rt5190a_ranged_buck_ops;
-+		break;
-+	case RT5190A_IDX_BUCK4:
-+		desc->n_voltages = 1;
-+		desc->ops = &rt5190a_fixed_buck_ops;
-+		desc->of_map_mode = rt5190a_of_map_mode;
-+		break;
-+	case RT5190A_IDX_LDO:
-+		desc->n_voltages = 1;
-+		desc->ops = &rt5190a_fixed_ldo_ops;
-+		break;
-+	}
-+}
-+
-+static struct of_regulator_match rt5190a_regulator_match[] = {
-+	{ .name = "buck1", },
-+	{ .name = "buck2", },
-+	{ .name = "buck3", },
-+	{ .name = "buck4", },
-+	{ .name = "ldo", }
-+};
-+
-+static int rt5190a_parse_regulator_dt_data(struct rt5190a_priv *priv)
-+{
-+	struct device_node *regulator_np;
-+	struct regulator_desc *reg_desc;
-+	struct of_regulator_match *match;
-+	int i, ret;
-+
-+	for (i = 0; i < RT5190A_MAX_IDX; i++) {
-+		reg_desc = priv->rdesc + i;
-+		match = rt5190a_regulator_match + i;
-+
-+		rt5190a_fillin_regulator_desc(reg_desc, i);
-+
-+		match->desc = reg_desc;
-+	}
-+
-+	regulator_np = of_get_child_by_name(priv->dev->of_node, "regulators");
-+	if (!regulator_np) {
-+		dev_err(priv->dev, "Could not find 'regulators' node\n");
-+		return -ENODEV;
-+	}
-+
-+	ret = of_regulator_match(priv->dev, regulator_np,
-+				 rt5190a_regulator_match,
-+				 ARRAY_SIZE(rt5190a_regulator_match));
-+
-+	of_node_put(regulator_np);
-+
-+	if (ret < 0) {
-+		dev_err(priv->dev,
-+			"Error parsing regulator init data: %d\n", ret);
-+		return ret;
-+	}
-+
-+	for (i = 0; i < RT5190A_MAX_IDX; i++) {
-+		match = rt5190a_regulator_match + i;
-+
-+		ret = rt5190a_of_parse_cb(priv, i, match);
-+		if (ret) {
-+			dev_err(priv->dev, "Failed in [%d] of_parse_cb\n", i);
-+			return ret;
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static const struct reg_sequence rt5190a_init_patch[] = {
-+	{ 0x09, 0x3d, },
-+	{ 0x0a, 0x3e, },
-+	{ 0x0b, 0x01, },
-+	{ 0x10, 0xff, },
-+	{ 0x11, 0xff, },
-+	{ 0x12, 0xff, },
-+	{ 0x13, 0xff, },
-+	{ 0x14, 0, },
-+	{ 0x15, 0, },
-+	{ 0x16, 0x3e, },
-+	{ 0x17, 0, }
-+};
-+
-+static int rt5190a_device_initialize(struct rt5190a_priv *priv)
-+{
-+	bool mute_enable;
-+	int ret;
-+
-+	ret = regmap_register_patch(priv->regmap, rt5190a_init_patch,
-+				    ARRAY_SIZE(rt5190a_init_patch));
-+	if (ret) {
-+		dev_err(priv->dev, "Failed to do register patch\n");
-+		return ret;
-+	}
-+
-+	mute_enable = device_property_read_bool(priv->dev,
-+						"richtek,mute-enable");
-+
-+	if (mute_enable) {
-+		ret = regmap_write(priv->regmap, RT5190A_REG_MUTECNTL, 0x00);
-+		if (ret) {
-+			dev_err(priv->dev, "Failed to enable mute function\n");
-+			return ret;
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int rt5190a_device_check(struct rt5190a_priv *priv)
-+{
-+	u16 devid;
-+	int ret;
-+
-+	ret = regmap_raw_read(priv->regmap, RT5190A_REG_MANUFACTURE, &devid,
-+			      sizeof(devid));
-+	if (ret)
-+		return ret;
-+
-+	if (devid) {
-+		dev_err(priv->dev, "Incorrect device id 0x%04x\n", devid);
-+		return -ENODEV;
-+	}
-+
-+	return 0;
-+}
-+
-+static const struct regmap_config rt5190a_regmap_config = {
-+	.reg_bits = 8,
-+	.val_bits = 8,
-+	.max_register = RT5190A_REG_HOTDIEMASK,
-+};
-+
-+static int rt5190a_probe(struct i2c_client *i2c)
-+{
-+	struct rt5190a_priv *priv;
-+	struct regulator_config cfg = {};
-+	int i, ret;
-+
-+	priv = devm_kzalloc(&i2c->dev, sizeof(*priv), GFP_KERNEL);
-+	if (!priv)
-+		return -ENOMEM;
-+
-+	priv->dev = &i2c->dev;
-+
-+	priv->regmap = devm_regmap_init_i2c(i2c, &rt5190a_regmap_config);
-+	if (IS_ERR(priv->regmap)) {
-+		dev_err(&i2c->dev, "Failed to allocate regmap\n");
-+		return PTR_ERR(priv->regmap);
-+	}
-+
-+	ret = rt5190a_device_check(priv);
-+	if (ret) {
-+		dev_err(&i2c->dev, "Failed to check device %d\n", ret);
-+		return ret;
-+	}
-+
-+	ret = rt5190a_device_initialize(priv);
-+	if (ret) {
-+		dev_err(&i2c->dev, "Failed to initialize the device\n");
-+		return ret;
-+	}
-+
-+	ret = rt5190a_parse_regulator_dt_data(priv);
-+	if (ret) {
-+		dev_err(&i2c->dev, "Failed to parse regulator dt\n");
-+		return ret;
-+	}
-+
-+	cfg.dev = &i2c->dev;
-+	cfg.regmap = priv->regmap;
-+
-+	for (i = 0; i < RT5190A_MAX_IDX; i++) {
-+		struct regulator_desc *desc = priv->rdesc + i;
-+		struct of_regulator_match *match = rt5190a_regulator_match + i;
-+
-+		cfg.init_data = match->init_data;
-+		cfg.of_node = match->of_node;
-+
-+		priv->rdev[i] = devm_regulator_register(&i2c->dev, desc, &cfg);
-+		if (IS_ERR(priv->rdev[i])) {
-+			dev_err(&i2c->dev, "Failed to register regulator %s\n",
-+				desc->name);
-+			return PTR_ERR(priv->rdev[i]);
-+		}
-+	}
-+
-+	if (i2c->irq) {
-+		ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
-+						rt5190a_irq_handler,
-+						IRQF_ONESHOT,
-+						dev_name(&i2c->dev), priv);
-+		if (ret) {
-+			dev_err(&i2c->dev, "Failed to register interrupt\n");
-+			return ret;
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static const struct of_device_id __maybe_unused rt5190a_device_table[] = {
-+	{ .compatible = "richtek,rt5190a", },
-+	{}
-+};
-+MODULE_DEVICE_TABLE(of, rt5190a_device_table);
-+
-+static struct i2c_driver rt5190a_driver = {
-+	.driver = {
-+		.name = "rt5190a",
-+		.of_match_table = rt5190a_device_table,
-+	},
-+	.probe_new = rt5190a_probe,
-+};
-+module_i2c_driver(rt5190a_driver);
-+
-+MODULE_AUTHOR("ChiYuan Huang <cy_huang@richtek.com>");
-+MODULE_DESCRIPTION("Richtek RT5190A Regulator Driver");
-+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/mediatek/patches-5.15/840-v5.16-i2c-mediatek-Reset-the-handshake-signal-between-i2c-.patch b/target/linux/mediatek/patches-5.15/840-v5.16-i2c-mediatek-Reset-the-handshake-signal-between-i2c-.patch
deleted file mode 100644
index 8b0119640984c9..00000000000000
--- a/target/linux/mediatek/patches-5.15/840-v5.16-i2c-mediatek-Reset-the-handshake-signal-between-i2c-.patch
+++ /dev/null
@@ -1,74 +0,0 @@
-From 95e4dfbf33dc0a0843ba20db811f7ea271235e1e Mon Sep 17 00:00:00 2001
-From: Kewei Xu <kewei.xu@mediatek.com>
-Date: Sun, 10 Oct 2021 15:05:12 +0800
-Subject: [PATCH 01/16] i2c: mediatek: Reset the handshake signal between i2c
- and dma
-
-Due to changes in the hardware design of the handshaking signal
-between i2c and dma, it is necessary to reset the handshaking
-signal before each transfer to ensure that the multi-msgs can
-be transferred correctly.
-
-Signed-off-by: Kewei Xu <kewei.xu@mediatek.com>
-Reviewed-by: Qii Wang <qii.wang@mediatek.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/i2c-mt65xx.c | 26 ++++++++++++++++++++++++++
- 1 file changed, 26 insertions(+)
-
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -15,6 +15,7 @@
- #include <linux/init.h>
- #include <linux/interrupt.h>
- #include <linux/io.h>
-+#include <linux/iopoll.h>
- #include <linux/kernel.h>
- #include <linux/mm.h>
- #include <linux/module.h>
-@@ -49,6 +50,8 @@
- #define I2C_RD_TRANAC_VALUE		0x0001
- #define I2C_SCL_MIS_COMP_VALUE		0x0000
- #define I2C_CHN_CLR_FLAG		0x0000
-+#define I2C_RELIABILITY		0x0010
-+#define I2C_DMAACK_ENABLE		0x0008
- 
- #define I2C_DMA_CON_TX			0x0000
- #define I2C_DMA_CON_RX			0x0001
-@@ -851,6 +854,7 @@ static int mtk_i2c_do_transfer(struct mt
- 	u16 restart_flag = 0;
- 	u16 dma_sync = 0;
- 	u32 reg_4g_mode;
-+	u32 reg_dma_reset;
- 	u8 *dma_rd_buf = NULL;
- 	u8 *dma_wr_buf = NULL;
- 	dma_addr_t rpaddr = 0;
-@@ -864,6 +868,28 @@ static int mtk_i2c_do_transfer(struct mt
- 
- 	reinit_completion(&i2c->msg_complete);
- 
-+	if (i2c->dev_comp->apdma_sync &&
-+	    i2c->op != I2C_MASTER_WRRD && num > 1) {
-+		mtk_i2c_writew(i2c, 0x00, OFFSET_DEBUGCTRL);
-+		writel(I2C_DMA_HANDSHAKE_RST | I2C_DMA_WARM_RST,
-+		       i2c->pdmabase + OFFSET_RST);
-+
-+		ret = readw_poll_timeout(i2c->pdmabase + OFFSET_RST,
-+					 reg_dma_reset,
-+					 !(reg_dma_reset & I2C_DMA_WARM_RST),
-+					 0, 100);
-+		if (ret) {
-+			dev_err(i2c->dev, "DMA warm reset timeout\n");
-+			return -ETIMEDOUT;
-+		}
-+
-+		writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
-+		mtk_i2c_writew(i2c, I2C_HANDSHAKE_RST, OFFSET_SOFTRESET);
-+		mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_SOFTRESET);
-+		mtk_i2c_writew(i2c, I2C_RELIABILITY | I2C_DMAACK_ENABLE,
-+			       OFFSET_DEBUGCTRL);
-+	}
-+
- 	control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) &
- 			~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS);
- 	if ((i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) || (left_num >= 1))
diff --git a/target/linux/mediatek/patches-5.15/841-v5.16-i2c-mediatek-Dump-i2c-dma-register-when-a-timeout-oc.patch b/target/linux/mediatek/patches-5.15/841-v5.16-i2c-mediatek-Dump-i2c-dma-register-when-a-timeout-oc.patch
deleted file mode 100644
index a2d2521c772f87..00000000000000
--- a/target/linux/mediatek/patches-5.15/841-v5.16-i2c-mediatek-Dump-i2c-dma-register-when-a-timeout-oc.patch
+++ /dev/null
@@ -1,102 +0,0 @@
-From 5b8e29e566e086ef9b5b9ea0d054370a295e1d05 Mon Sep 17 00:00:00 2001
-From: Kewei Xu <kewei.xu@mediatek.com>
-Date: Sun, 10 Oct 2021 15:05:13 +0800
-Subject: [PATCH 02/16] i2c: mediatek: Dump i2c/dma register when a timeout
- occurs
-
-When a timeout error occurs in i2c transter, it is usually related
-to the i2c/dma IP hardware configuration. Therefore, the purpose of
-this patch is to dump the key register values of i2c/dma when a
-timeout occurs in i2c for debugging.
-
-Signed-off-by: Kewei Xu <kewei.xu@mediatek.com>
-Reviewed-by: Qii Wang <qii.wang@mediatek.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/i2c-mt65xx.c | 54 +++++++++++++++++++++++++++++++++
- 1 file changed, 54 insertions(+)
-
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -130,6 +130,7 @@ enum I2C_REGS_OFFSET {
- 	OFFSET_HS,
- 	OFFSET_SOFTRESET,
- 	OFFSET_DCM_EN,
-+	OFFSET_MULTI_DMA,
- 	OFFSET_PATH_DIR,
- 	OFFSET_DEBUGSTAT,
- 	OFFSET_DEBUGCTRL,
-@@ -197,6 +198,7 @@ static const u16 mt_i2c_regs_v2[] = {
- 	[OFFSET_TRANSFER_LEN_AUX] = 0x44,
- 	[OFFSET_CLOCK_DIV] = 0x48,
- 	[OFFSET_SOFTRESET] = 0x50,
-+	[OFFSET_MULTI_DMA] = 0x8c,
- 	[OFFSET_SCL_MIS_COMP_POINT] = 0x90,
- 	[OFFSET_DEBUGSTAT] = 0xe4,
- 	[OFFSET_DEBUGCTRL] = 0xe8,
-@@ -845,6 +847,57 @@ static int mtk_i2c_set_speed(struct mtk_
- 	return 0;
- }
- 
-+static void i2c_dump_register(struct mtk_i2c *i2c)
-+{
-+	dev_dbg(i2c->dev, "SLAVE_ADDR: 0x%x, INTR_MASK: 0x%x\n",
-+		mtk_i2c_readw(i2c, OFFSET_SLAVE_ADDR),
-+		mtk_i2c_readw(i2c, OFFSET_INTR_MASK));
-+	dev_dbg(i2c->dev, "INTR_STAT: 0x%x, CONTROL: 0x%x\n",
-+		mtk_i2c_readw(i2c, OFFSET_INTR_STAT),
-+		mtk_i2c_readw(i2c, OFFSET_CONTROL));
-+	dev_dbg(i2c->dev, "TRANSFER_LEN: 0x%x, TRANSAC_LEN: 0x%x\n",
-+		mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN),
-+		mtk_i2c_readw(i2c, OFFSET_TRANSAC_LEN));
-+	dev_dbg(i2c->dev, "DELAY_LEN: 0x%x, HTIMING: 0x%x\n",
-+		mtk_i2c_readw(i2c, OFFSET_DELAY_LEN),
-+		mtk_i2c_readw(i2c, OFFSET_TIMING));
-+	dev_dbg(i2c->dev, "START: 0x%x, EXT_CONF: 0x%x\n",
-+		mtk_i2c_readw(i2c, OFFSET_START),
-+		mtk_i2c_readw(i2c, OFFSET_EXT_CONF));
-+	dev_dbg(i2c->dev, "HS: 0x%x, IO_CONFIG: 0x%x\n",
-+		mtk_i2c_readw(i2c, OFFSET_HS),
-+		mtk_i2c_readw(i2c, OFFSET_IO_CONFIG));
-+	dev_dbg(i2c->dev, "DCM_EN: 0x%x, TRANSFER_LEN_AUX: 0x%x\n",
-+		mtk_i2c_readw(i2c, OFFSET_DCM_EN),
-+		mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN_AUX));
-+	dev_dbg(i2c->dev, "CLOCK_DIV: 0x%x, FIFO_STAT: 0x%x\n",
-+		mtk_i2c_readw(i2c, OFFSET_CLOCK_DIV),
-+		mtk_i2c_readw(i2c, OFFSET_FIFO_STAT));
-+	dev_dbg(i2c->dev, "DEBUGCTRL : 0x%x, DEBUGSTAT: 0x%x\n",
-+		mtk_i2c_readw(i2c, OFFSET_DEBUGCTRL),
-+		mtk_i2c_readw(i2c, OFFSET_DEBUGSTAT));
-+	if (i2c->dev_comp->regs == mt_i2c_regs_v2) {
-+		dev_dbg(i2c->dev, "LTIMING: 0x%x, MULTI_DMA: 0x%x\n",
-+			mtk_i2c_readw(i2c, OFFSET_LTIMING),
-+			mtk_i2c_readw(i2c, OFFSET_MULTI_DMA));
-+	}
-+	dev_dbg(i2c->dev, "\nDMA_INT_FLAG: 0x%x, DMA_INT_EN: 0x%x\n",
-+		readl(i2c->pdmabase + OFFSET_INT_FLAG),
-+		readl(i2c->pdmabase + OFFSET_INT_EN));
-+	dev_dbg(i2c->dev, "DMA_EN: 0x%x, DMA_CON: 0x%x\n",
-+		readl(i2c->pdmabase + OFFSET_EN),
-+		readl(i2c->pdmabase + OFFSET_CON));
-+	dev_dbg(i2c->dev, "DMA_TX_MEM_ADDR: 0x%x, DMA_RX_MEM_ADDR: 0x%x\n",
-+		readl(i2c->pdmabase + OFFSET_TX_MEM_ADDR),
-+		readl(i2c->pdmabase + OFFSET_RX_MEM_ADDR));
-+	dev_dbg(i2c->dev, "DMA_TX_LEN: 0x%x, DMA_RX_LEN: 0x%x\n",
-+		readl(i2c->pdmabase + OFFSET_TX_LEN),
-+		readl(i2c->pdmabase + OFFSET_RX_LEN));
-+	dev_dbg(i2c->dev, "DMA_TX_4G_MODE: 0x%x, DMA_RX_4G_MODE: 0x%x",
-+		readl(i2c->pdmabase + OFFSET_TX_4G_MODE),
-+		readl(i2c->pdmabase + OFFSET_RX_4G_MODE));
-+}
-+
- static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
- 			       int num, int left_num)
- {
-@@ -1075,6 +1128,7 @@ static int mtk_i2c_do_transfer(struct mt
- 
- 	if (ret == 0) {
- 		dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr);
-+		i2c_dump_register(i2c);
- 		mtk_i2c_init_hw(i2c);
- 		return -ETIMEDOUT;
- 	}
diff --git a/target/linux/mediatek/patches-5.15/842-v5.18-i2c-mediatek-Add-i2c-compatible-for-Mediatek-MT8186.patch b/target/linux/mediatek/patches-5.15/842-v5.18-i2c-mediatek-Add-i2c-compatible-for-Mediatek-MT8186.patch
deleted file mode 100644
index 184fe94ff80bde..00000000000000
--- a/target/linux/mediatek/patches-5.15/842-v5.18-i2c-mediatek-Add-i2c-compatible-for-Mediatek-MT8186.patch
+++ /dev/null
@@ -1,45 +0,0 @@
-From 83630e3c6147bf7bb18a18f3d5a99462464f450b Mon Sep 17 00:00:00 2001
-From: Kewei Xu <kewei.xu@mediatek.com>
-Date: Tue, 25 Jan 2022 19:04:13 +0800
-Subject: [PATCH 03/16] i2c: mediatek: Add i2c compatible for Mediatek MT8186
-
-Add i2c compatible for MT8186. Compare to MT8192 i2c controller,
-MT8186 doesn't need handshake signal witch apdma.
-
-Signed-off-by: Kewei Xu <kewei.xu@mediatek.com>
-Reviewed-by: Qii Wang <qii.wang@mediatek.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/i2c-mt65xx.c | 14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -397,6 +397,19 @@ static const struct mtk_i2c_compatible m
- 	.max_dma_support = 33,
- };
- 
-+static const struct mtk_i2c_compatible mt8186_compat = {
-+	.regs = mt_i2c_regs_v2,
-+	.pmic_i2c = 0,
-+	.dcm = 0,
-+	.auto_restart = 1,
-+	.aux_len_reg = 1,
-+	.timing_adjust = 1,
-+	.dma_sync = 0,
-+	.ltiming_adjust = 1,
-+	.apdma_sync = 0,
-+	.max_dma_support = 36,
-+};
-+
- static const struct mtk_i2c_compatible mt8192_compat = {
- 	.quirks = &mt8183_i2c_quirks,
- 	.regs = mt_i2c_regs_v2,
-@@ -418,6 +431,7 @@ static const struct of_device_id mtk_i2c
- 	{ .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat },
- 	{ .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
- 	{ .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat },
-+	{ .compatible = "mediatek,mt8186-i2c", .data = &mt8186_compat },
- 	{ .compatible = "mediatek,mt8192-i2c", .data = &mt8192_compat },
- 	{}
- };
diff --git a/target/linux/mediatek/patches-5.15/843-v5.18-i2c-mediatek-modify-bus-speed-calculation-formula.patch b/target/linux/mediatek/patches-5.15/843-v5.18-i2c-mediatek-modify-bus-speed-calculation-formula.patch
deleted file mode 100644
index 0ace4a6701c5d5..00000000000000
--- a/target/linux/mediatek/patches-5.15/843-v5.18-i2c-mediatek-modify-bus-speed-calculation-formula.patch
+++ /dev/null
@@ -1,132 +0,0 @@
-From f606aab3f1a49d723d66e14e545f6ca45005bda6 Mon Sep 17 00:00:00 2001
-From: Kewei Xu <kewei.xu@mediatek.com>
-Date: Thu, 17 Feb 2022 20:22:43 +0800
-Subject: [PATCH 04/16] i2c: mediatek: modify bus speed calculation formula
-
-When clock-div is 0 or greater than 1, the bus speed
-calculated by the old speed calculation formula will be
-larger than the target speed. So we update the formula.
-
-Signed-off-by: Kewei Xu <kewei.xu@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Qii Wang <qii.wang@mediatek.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/i2c-mt65xx.c | 51 ++++++++++++++++++++++++++-------
- 1 file changed, 41 insertions(+), 10 deletions(-)
-
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -67,11 +67,12 @@
- 
- #define MAX_SAMPLE_CNT_DIV		8
- #define MAX_STEP_CNT_DIV		64
--#define MAX_CLOCK_DIV			256
-+#define MAX_CLOCK_DIV_8BITS		256
-+#define MAX_CLOCK_DIV_5BITS		32
- #define MAX_HS_STEP_CNT_DIV		8
--#define I2C_STANDARD_MODE_BUFFER	(1000 / 2)
--#define I2C_FAST_MODE_BUFFER		(300 / 2)
--#define I2C_FAST_MODE_PLUS_BUFFER	(20 / 2)
-+#define I2C_STANDARD_MODE_BUFFER	(1000 / 3)
-+#define I2C_FAST_MODE_BUFFER		(300 / 3)
-+#define I2C_FAST_MODE_PLUS_BUFFER	(20 / 3)
- 
- #define I2C_CONTROL_RS                  (0x1 << 1)
- #define I2C_CONTROL_DMA_EN              (0x1 << 2)
-@@ -604,6 +605,31 @@ static int mtk_i2c_max_step_cnt(unsigned
- 		return MAX_STEP_CNT_DIV;
- }
- 
-+static int mtk_i2c_get_clk_div_restri(struct mtk_i2c *i2c,
-+				      unsigned int sample_cnt)
-+{
-+	int clk_div_restri = 0;
-+
-+	if (i2c->dev_comp->ltiming_adjust == 0)
-+		return 0;
-+
-+	if (sample_cnt == 1) {
-+		if (i2c->ac_timing.inter_clk_div == 0)
-+			clk_div_restri = 0;
-+		else
-+			clk_div_restri = 1;
-+	} else {
-+		if (i2c->ac_timing.inter_clk_div == 0)
-+			clk_div_restri = -1;
-+		else if (i2c->ac_timing.inter_clk_div == 1)
-+			clk_div_restri = 0;
-+		else
-+			clk_div_restri = 1;
-+	}
-+
-+	return clk_div_restri;
-+}
-+
- /*
-  * Check and Calculate i2c ac-timing
-  *
-@@ -732,6 +758,7 @@ static int mtk_i2c_calculate_speed(struc
- 	unsigned int best_mul;
- 	unsigned int cnt_mul;
- 	int ret = -EINVAL;
-+	int clk_div_restri = 0;
- 
- 	if (target_speed > I2C_MAX_HIGH_SPEED_MODE_FREQ)
- 		target_speed = I2C_MAX_HIGH_SPEED_MODE_FREQ;
-@@ -749,7 +776,8 @@ static int mtk_i2c_calculate_speed(struc
- 	 * optimizing for sample_cnt * step_cnt being minimal
- 	 */
- 	for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) {
--		step_cnt = DIV_ROUND_UP(opt_div, sample_cnt);
-+		clk_div_restri = mtk_i2c_get_clk_div_restri(i2c, sample_cnt);
-+		step_cnt = DIV_ROUND_UP(opt_div + clk_div_restri, sample_cnt);
- 		cnt_mul = step_cnt * sample_cnt;
- 		if (step_cnt > max_step_cnt)
- 			continue;
-@@ -763,7 +791,7 @@ static int mtk_i2c_calculate_speed(struc
- 			best_mul = cnt_mul;
- 			base_sample_cnt = sample_cnt;
- 			base_step_cnt = step_cnt;
--			if (best_mul == opt_div)
-+			if (best_mul == (opt_div + clk_div_restri))
- 				break;
- 		}
- 	}
-@@ -774,7 +802,8 @@ static int mtk_i2c_calculate_speed(struc
- 	sample_cnt = base_sample_cnt;
- 	step_cnt = base_step_cnt;
- 
--	if ((clk_src / (2 * sample_cnt * step_cnt)) > target_speed) {
-+	if ((clk_src / (2 * (sample_cnt * step_cnt - clk_div_restri))) >
-+		target_speed) {
- 		/* In this case, hardware can't support such
- 		 * low i2c_bus_freq
- 		 */
-@@ -803,13 +832,16 @@ static int mtk_i2c_set_speed(struct mtk_
- 	target_speed = i2c->speed_hz;
- 	parent_clk /= i2c->clk_src_div;
- 
--	if (i2c->dev_comp->timing_adjust)
--		max_clk_div = MAX_CLOCK_DIV;
-+	if (i2c->dev_comp->timing_adjust && i2c->dev_comp->ltiming_adjust)
-+		max_clk_div = MAX_CLOCK_DIV_5BITS;
-+	else if (i2c->dev_comp->timing_adjust)
-+		max_clk_div = MAX_CLOCK_DIV_8BITS;
- 	else
- 		max_clk_div = 1;
- 
- 	for (clk_div = 1; clk_div <= max_clk_div; clk_div++) {
- 		clk_src = parent_clk / clk_div;
-+		i2c->ac_timing.inter_clk_div = clk_div - 1;
- 
- 		if (target_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) {
- 			/* Set master code speed register */
-@@ -856,7 +888,6 @@ static int mtk_i2c_set_speed(struct mtk_
- 		break;
- 	}
- 
--	i2c->ac_timing.inter_clk_div = clk_div - 1;
- 
- 	return 0;
- }
diff --git a/target/linux/mediatek/patches-5.15/844-v5.18-i2c-mediatek-remove-redundant-null-check.patch b/target/linux/mediatek/patches-5.15/844-v5.18-i2c-mediatek-remove-redundant-null-check.patch
deleted file mode 100644
index 8f3c965a8d4e32..00000000000000
--- a/target/linux/mediatek/patches-5.15/844-v5.18-i2c-mediatek-remove-redundant-null-check.patch
+++ /dev/null
@@ -1,41 +0,0 @@
-From eb4a2ae019815946f574cd9f8209e12bdcd8fd34 Mon Sep 17 00:00:00 2001
-From: Xu Wang <vulab@iscas.ac.cn>
-Date: Wed, 30 Sep 2020 08:42:33 +0000
-Subject: [PATCH 05/16] i2c: mediatek: remove redundant null check
-
-Because clk_disable_unprepare already checked NULL clock parameter,
-so the additional checks are unnecessary, just remove it
-
-Signed-off-by: Xu Wang <vulab@iscas.ac.cn>
-Reviewed-by: Qii Wang <qii.wang@mediatek.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/i2c-mt65xx.c | 9 +++------
- 1 file changed, 3 insertions(+), 6 deletions(-)
-
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -476,8 +476,7 @@ static int mtk_i2c_clock_enable(struct m
- 	return 0;
- 
- err_arb:
--	if (i2c->have_pmic)
--		clk_disable_unprepare(i2c->clk_pmic);
-+	clk_disable_unprepare(i2c->clk_pmic);
- err_pmic:
- 	clk_disable_unprepare(i2c->clk_main);
- err_main:
-@@ -488,11 +487,9 @@ err_main:
- 
- static void mtk_i2c_clock_disable(struct mtk_i2c *i2c)
- {
--	if (i2c->clk_arb)
--		clk_disable_unprepare(i2c->clk_arb);
-+	clk_disable_unprepare(i2c->clk_arb);
- 
--	if (i2c->have_pmic)
--		clk_disable_unprepare(i2c->clk_pmic);
-+	clk_disable_unprepare(i2c->clk_pmic);
- 
- 	clk_disable_unprepare(i2c->clk_main);
- 	clk_disable_unprepare(i2c->clk_dma);
diff --git a/target/linux/mediatek/patches-5.15/845-v5.18-i2c-mt65xx-Simplify-with-clk-bulk.patch b/target/linux/mediatek/patches-5.15/845-v5.18-i2c-mt65xx-Simplify-with-clk-bulk.patch
deleted file mode 100644
index 71d083f31a9565..00000000000000
--- a/target/linux/mediatek/patches-5.15/845-v5.18-i2c-mt65xx-Simplify-with-clk-bulk.patch
+++ /dev/null
@@ -1,234 +0,0 @@
-From cc6faa5e0772296d815fd298c231277d47308a6a Mon Sep 17 00:00:00 2001
-From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Date: Thu, 3 Mar 2022 10:15:47 +0100
-Subject: [PATCH 06/16] i2c: mt65xx: Simplify with clk-bulk
-
-Since depending on the SoC or specific bus functionality some clocks
-may be optional, we cannot get the benefit of using devm_clk_bulk_get()
-but, by migrating to clk-bulk, we are able to remove the custom functions
-mtk_i2c_clock_enable() and mtk_i2c_clock_disable(), increasing common
-APIs usage, hence (lightly) decreasing kernel footprint.
-
-Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Qii Wang <qii.wang@mediatek.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/i2c-mt65xx.c | 124 +++++++++++++-------------------
- 1 file changed, 51 insertions(+), 73 deletions(-)
-
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -86,6 +86,27 @@
- 
- #define I2C_DRV_NAME		"i2c-mt65xx"
- 
-+/**
-+ * enum i2c_mt65xx_clks - Clocks enumeration for MT65XX I2C
-+ *
-+ * @I2C_MT65XX_CLK_MAIN: main clock for i2c bus
-+ * @I2C_MT65XX_CLK_DMA:  DMA clock for i2c via DMA
-+ * @I2C_MT65XX_CLK_PMIC: PMIC clock for i2c from PMIC
-+ * @I2C_MT65XX_CLK_ARB:  Arbitrator clock for i2c
-+ * @I2C_MT65XX_CLK_MAX:  Number of supported clocks
-+ */
-+enum i2c_mt65xx_clks {
-+	I2C_MT65XX_CLK_MAIN = 0,
-+	I2C_MT65XX_CLK_DMA,
-+	I2C_MT65XX_CLK_PMIC,
-+	I2C_MT65XX_CLK_ARB,
-+	I2C_MT65XX_CLK_MAX
-+};
-+
-+static const char * const i2c_mt65xx_clk_ids[I2C_MT65XX_CLK_MAX] = {
-+	"main", "dma", "pmic", "arb"
-+};
-+
- enum DMA_REGS_OFFSET {
- 	OFFSET_INT_FLAG = 0x0,
- 	OFFSET_INT_EN = 0x04,
-@@ -244,10 +265,7 @@ struct mtk_i2c {
- 	/* set in i2c probe */
- 	void __iomem *base;		/* i2c base addr */
- 	void __iomem *pdmabase;		/* dma base address*/
--	struct clk *clk_main;		/* main clock for i2c bus */
--	struct clk *clk_dma;		/* DMA clock for i2c via DMA */
--	struct clk *clk_pmic;		/* PMIC clock for i2c from PMIC */
--	struct clk *clk_arb;		/* Arbitrator clock for i2c */
-+	struct clk_bulk_data clocks[I2C_MT65XX_CLK_MAX]; /* clocks for i2c */
- 	bool have_pmic;			/* can use i2c pins from PMIC */
- 	bool use_push_pull;		/* IO config push-pull mode */
- 
-@@ -449,52 +467,6 @@ static void mtk_i2c_writew(struct mtk_i2
- 	writew(val, i2c->base + i2c->dev_comp->regs[reg]);
- }
- 
--static int mtk_i2c_clock_enable(struct mtk_i2c *i2c)
--{
--	int ret;
--
--	ret = clk_prepare_enable(i2c->clk_dma);
--	if (ret)
--		return ret;
--
--	ret = clk_prepare_enable(i2c->clk_main);
--	if (ret)
--		goto err_main;
--
--	if (i2c->have_pmic) {
--		ret = clk_prepare_enable(i2c->clk_pmic);
--		if (ret)
--			goto err_pmic;
--	}
--
--	if (i2c->clk_arb) {
--		ret = clk_prepare_enable(i2c->clk_arb);
--		if (ret)
--			goto err_arb;
--	}
--
--	return 0;
--
--err_arb:
--	clk_disable_unprepare(i2c->clk_pmic);
--err_pmic:
--	clk_disable_unprepare(i2c->clk_main);
--err_main:
--	clk_disable_unprepare(i2c->clk_dma);
--
--	return ret;
--}
--
--static void mtk_i2c_clock_disable(struct mtk_i2c *i2c)
--{
--	clk_disable_unprepare(i2c->clk_arb);
--
--	clk_disable_unprepare(i2c->clk_pmic);
--
--	clk_disable_unprepare(i2c->clk_main);
--	clk_disable_unprepare(i2c->clk_dma);
--}
--
- static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
- {
- 	u16 control_reg;
-@@ -1191,7 +1163,7 @@ static int mtk_i2c_transfer(struct i2c_a
- 	int left_num = num;
- 	struct mtk_i2c *i2c = i2c_get_adapdata(adap);
- 
--	ret = mtk_i2c_clock_enable(i2c);
-+	ret = clk_bulk_prepare_enable(I2C_MT65XX_CLK_MAX, i2c->clocks);
- 	if (ret)
- 		return ret;
- 
-@@ -1245,7 +1217,7 @@ static int mtk_i2c_transfer(struct i2c_a
- 	ret = num;
- 
- err_exit:
--	mtk_i2c_clock_disable(i2c);
-+	clk_bulk_disable_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks);
- 	return ret;
- }
- 
-@@ -1323,9 +1295,8 @@ static int mtk_i2c_probe(struct platform
- {
- 	int ret = 0;
- 	struct mtk_i2c *i2c;
--	struct clk *clk;
- 	struct resource *res;
--	int irq;
-+	int i, irq, speed_clk;
- 
- 	i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
- 	if (!i2c)
-@@ -1371,35 +1342,42 @@ static int mtk_i2c_probe(struct platform
- 	if (i2c->have_pmic && !i2c->dev_comp->pmic_i2c)
- 		return -EINVAL;
- 
--	i2c->clk_main = devm_clk_get(&pdev->dev, "main");
--	if (IS_ERR(i2c->clk_main)) {
-+	/* Fill in clk-bulk IDs */
-+	for (i = 0; i < I2C_MT65XX_CLK_MAX; i++)
-+		i2c->clocks[i].id = i2c_mt65xx_clk_ids[i];
-+
-+	/* Get clocks one by one, some may be optional */
-+	i2c->clocks[I2C_MT65XX_CLK_MAIN].clk = devm_clk_get(&pdev->dev, "main");
-+	if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_MAIN].clk)) {
- 		dev_err(&pdev->dev, "cannot get main clock\n");
--		return PTR_ERR(i2c->clk_main);
-+		return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_MAIN].clk);
- 	}
- 
--	i2c->clk_dma = devm_clk_get(&pdev->dev, "dma");
--	if (IS_ERR(i2c->clk_dma)) {
-+	i2c->clocks[I2C_MT65XX_CLK_DMA].clk = devm_clk_get(&pdev->dev, "dma");
-+	if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_DMA].clk)) {
- 		dev_err(&pdev->dev, "cannot get dma clock\n");
--		return PTR_ERR(i2c->clk_dma);
-+		return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_DMA].clk);
- 	}
- 
--	i2c->clk_arb = devm_clk_get(&pdev->dev, "arb");
--	if (IS_ERR(i2c->clk_arb))
--		i2c->clk_arb = NULL;
-+	i2c->clocks[I2C_MT65XX_CLK_ARB].clk = devm_clk_get_optional(&pdev->dev, "arb");
-+	if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk))
-+		return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk);
- 
--	clk = i2c->clk_main;
- 	if (i2c->have_pmic) {
--		i2c->clk_pmic = devm_clk_get(&pdev->dev, "pmic");
--		if (IS_ERR(i2c->clk_pmic)) {
-+		i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = devm_clk_get(&pdev->dev, "pmic");
-+		if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk)) {
- 			dev_err(&pdev->dev, "cannot get pmic clock\n");
--			return PTR_ERR(i2c->clk_pmic);
-+			return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk);
- 		}
--		clk = i2c->clk_pmic;
-+		speed_clk = I2C_MT65XX_CLK_PMIC;
-+	} else {
-+		i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = NULL;
-+		speed_clk = I2C_MT65XX_CLK_MAIN;
- 	}
- 
- 	strlcpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name));
- 
--	ret = mtk_i2c_set_speed(i2c, clk_get_rate(clk));
-+	ret = mtk_i2c_set_speed(i2c, clk_get_rate(i2c->clocks[speed_clk].clk));
- 	if (ret) {
- 		dev_err(&pdev->dev, "Failed to set the speed.\n");
- 		return -EINVAL;
-@@ -1414,13 +1392,13 @@ static int mtk_i2c_probe(struct platform
- 		}
- 	}
- 
--	ret = mtk_i2c_clock_enable(i2c);
-+	ret = clk_bulk_prepare_enable(I2C_MT65XX_CLK_MAX, i2c->clocks);
- 	if (ret) {
- 		dev_err(&pdev->dev, "clock enable failed!\n");
- 		return ret;
- 	}
- 	mtk_i2c_init_hw(i2c);
--	mtk_i2c_clock_disable(i2c);
-+	clk_bulk_disable_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks);
- 
- 	ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq,
- 			       IRQF_NO_SUSPEND | IRQF_TRIGGER_NONE,
-@@ -1465,7 +1443,7 @@ static int mtk_i2c_resume_noirq(struct d
- 	int ret;
- 	struct mtk_i2c *i2c = dev_get_drvdata(dev);
- 
--	ret = mtk_i2c_clock_enable(i2c);
-+	ret = clk_bulk_prepare_enable(I2C_MT65XX_CLK_MAX, i2c->clocks);
- 	if (ret) {
- 		dev_err(dev, "clock enable failed!\n");
- 		return ret;
-@@ -1473,7 +1451,7 @@ static int mtk_i2c_resume_noirq(struct d
- 
- 	mtk_i2c_init_hw(i2c);
- 
--	mtk_i2c_clock_disable(i2c);
-+	clk_bulk_disable_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks);
- 
- 	i2c_mark_adapter_resumed(&i2c->adap);
- 
diff --git a/target/linux/mediatek/patches-5.15/846-v5.18-i2c-mediatek-Add-i2c-compatible-for-Mediatek-MT8168.patch b/target/linux/mediatek/patches-5.15/846-v5.18-i2c-mediatek-Add-i2c-compatible-for-Mediatek-MT8168.patch
deleted file mode 100644
index fe5be94fca446e..00000000000000
--- a/target/linux/mediatek/patches-5.15/846-v5.18-i2c-mediatek-Add-i2c-compatible-for-Mediatek-MT8168.patch
+++ /dev/null
@@ -1,46 +0,0 @@
-From de054c03f90b3ea22bc346fbf78ac716df192b2d Mon Sep 17 00:00:00 2001
-From: Kewei Xu <kewei.xu@mediatek.com>
-Date: Mon, 7 Mar 2022 11:36:49 +0800
-Subject: [PATCH 07/16] i2c: mediatek: Add i2c compatible for Mediatek MT8168
-
-Add i2c compatible for MT8168. Compare to MT2712 i2c controller,
-MT8168 need to synchronize signal with dma.
-
-Signed-off-by: Kewei Xu <kewei.xu@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Qii Wang <qii.wang@mediatek.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/i2c-mt65xx.c | 14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -389,6 +389,19 @@ static const struct mtk_i2c_compatible m
- 	.max_dma_support = 32,
- };
- 
-+static const struct mtk_i2c_compatible mt8168_compat = {
-+	.regs = mt_i2c_regs_v1,
-+	.pmic_i2c = 0,
-+	.dcm = 1,
-+	.auto_restart = 1,
-+	.aux_len_reg = 1,
-+	.timing_adjust = 1,
-+	.dma_sync = 1,
-+	.ltiming_adjust = 0,
-+	.apdma_sync = 0,
-+	.max_dma_support = 33,
-+};
-+
- static const struct mtk_i2c_compatible mt8173_compat = {
- 	.regs = mt_i2c_regs_v1,
- 	.pmic_i2c = 0,
-@@ -448,6 +461,7 @@ static const struct of_device_id mtk_i2c
- 	{ .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat },
- 	{ .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat },
- 	{ .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat },
-+	{ .compatible = "mediatek,mt8168-i2c", .data = &mt8168_compat },
- 	{ .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
- 	{ .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat },
- 	{ .compatible = "mediatek,mt8186-i2c", .data = &mt8186_compat },
diff --git a/target/linux/mediatek/patches-5.15/847-v5.19-i2c-mediatek-Optimize-master_xfer-and-avoid-circular.patch b/target/linux/mediatek/patches-5.15/847-v5.19-i2c-mediatek-Optimize-master_xfer-and-avoid-circular.patch
deleted file mode 100644
index 5c4ce40765c058..00000000000000
--- a/target/linux/mediatek/patches-5.15/847-v5.19-i2c-mediatek-Optimize-master_xfer-and-avoid-circular.patch
+++ /dev/null
@@ -1,101 +0,0 @@
-From 2831f9a53ec3a16012d2d23590e3ebad6084b763 Mon Sep 17 00:00:00 2001
-From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Date: Mon, 11 Apr 2022 15:21:07 +0200
-Subject: [PATCH 08/16] i2c: mediatek: Optimize master_xfer() and avoid
- circular locking
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Especially (but not only) during probe, it may happen that multiple
-devices are communicating via i2c (or multiple i2c busses) and
-sometimes while others are probing asynchronously.
-For example, a Cr50 TPM may be filling entropy (or userspace may be
-reading random data) while the rt5682 (i2c) codec driver reads/sets
-some registers, like while getting/setting a clock's rate, which
-happens both during probe and during system operation.
-
-In this driver, the mtk_i2c_transfer() function (which is the i2c
-.master_xfer() callback) was granularly managing the clocks by
-performing a clk_bulk_prepare_enable() to start them and its inverse.
-This is not only creating possible circular locking dependencies in
-the some cases (like former explanation), but it's also suboptimal,
-as clk_core prepare/unprepare operations are using mutex locking,
-which creates a bit of unwanted overhead (for example, i2c trackpads
-will call master_xfer() every few milliseconds!).
-
-With this commit, we avoid both the circular locking and additional
-overhead by changing how we handle the clocks in this driver:
-- Prepare the clocks during probe (and PM resume)
-- Enable/disable clocks in mtk_i2c_transfer()
-- Unprepare the clocks only for driver removal (and PM suspend)
-
-For the sake of providing a full explanation: during probe, the
-clocks are not only prepared but also enabled, as this is needed
-for some hardware initialization but, after that, we are disabling
-but not unpreparing them, leaving an expected state for the
-aforementioned clock handling strategy.
-
-Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
-Reviewed-by: Qii Wang <qii.wang@mediatek.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/i2c-mt65xx.c | 11 +++++++----
- 1 file changed, 7 insertions(+), 4 deletions(-)
-
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -1177,7 +1177,7 @@ static int mtk_i2c_transfer(struct i2c_a
- 	int left_num = num;
- 	struct mtk_i2c *i2c = i2c_get_adapdata(adap);
- 
--	ret = clk_bulk_prepare_enable(I2C_MT65XX_CLK_MAX, i2c->clocks);
-+	ret = clk_bulk_enable(I2C_MT65XX_CLK_MAX, i2c->clocks);
- 	if (ret)
- 		return ret;
- 
-@@ -1231,7 +1231,7 @@ static int mtk_i2c_transfer(struct i2c_a
- 	ret = num;
- 
- err_exit:
--	clk_bulk_disable_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks);
-+	clk_bulk_disable(I2C_MT65XX_CLK_MAX, i2c->clocks);
- 	return ret;
- }
- 
-@@ -1412,7 +1412,7 @@ static int mtk_i2c_probe(struct platform
- 		return ret;
- 	}
- 	mtk_i2c_init_hw(i2c);
--	clk_bulk_disable_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks);
-+	clk_bulk_disable(I2C_MT65XX_CLK_MAX, i2c->clocks);
- 
- 	ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq,
- 			       IRQF_NO_SUSPEND | IRQF_TRIGGER_NONE,
-@@ -1439,6 +1439,8 @@ static int mtk_i2c_remove(struct platfor
- 
- 	i2c_del_adapter(&i2c->adap);
- 
-+	clk_bulk_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks);
-+
- 	return 0;
- }
- 
-@@ -1448,6 +1450,7 @@ static int mtk_i2c_suspend_noirq(struct
- 	struct mtk_i2c *i2c = dev_get_drvdata(dev);
- 
- 	i2c_mark_adapter_suspended(&i2c->adap);
-+	clk_bulk_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks);
- 
- 	return 0;
- }
-@@ -1465,7 +1468,7 @@ static int mtk_i2c_resume_noirq(struct d
- 
- 	mtk_i2c_init_hw(i2c);
- 
--	clk_bulk_disable_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks);
-+	clk_bulk_disable(I2C_MT65XX_CLK_MAX, i2c->clocks);
- 
- 	i2c_mark_adapter_resumed(&i2c->adap);
- 
diff --git a/target/linux/mediatek/patches-5.15/848-v5.19-i2c-mediatek-Fix-an-error-handling-path-in-mtk_i2c_p.patch b/target/linux/mediatek/patches-5.15/848-v5.19-i2c-mediatek-Fix-an-error-handling-path-in-mtk_i2c_p.patch
deleted file mode 100644
index 354f12e2146495..00000000000000
--- a/target/linux/mediatek/patches-5.15/848-v5.19-i2c-mediatek-Fix-an-error-handling-path-in-mtk_i2c_p.patch
+++ /dev/null
@@ -1,48 +0,0 @@
-From 6f3a5814c7aaea4176e0ac8b1ec6dc0a65aa2808 Mon Sep 17 00:00:00 2001
-From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
-Date: Sun, 22 May 2022 14:22:07 +0200
-Subject: [PATCH 09/16] i2c: mediatek: Fix an error handling path in
- mtk_i2c_probe()
-
-The clsk are prepared, enabled, then disabled. So if an error occurs after
-the disable step, they are still prepared.
-
-Add an error handling path to unprepare the clks in such a case, as already
-done in the .remove function.
-
-Fixes: 8b4fc246c3ff ("i2c: mediatek: Optimize master_xfer() and avoid circular locking")
-Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Qii Wang <qii.wang@mediatek.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/i2c-mt65xx.c | 9 +++++++--
- 1 file changed, 7 insertions(+), 2 deletions(-)
-
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -1420,17 +1420,22 @@ static int mtk_i2c_probe(struct platform
- 	if (ret < 0) {
- 		dev_err(&pdev->dev,
- 			"Request I2C IRQ %d fail\n", irq);
--		return ret;
-+		goto err_bulk_unprepare;
- 	}
- 
- 	i2c_set_adapdata(&i2c->adap, i2c);
- 	ret = i2c_add_adapter(&i2c->adap);
- 	if (ret)
--		return ret;
-+		goto err_bulk_unprepare;
- 
- 	platform_set_drvdata(pdev, i2c);
- 
- 	return 0;
-+
-+err_bulk_unprepare:
-+	clk_bulk_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks);
-+
-+	return ret;
- }
- 
- static int mtk_i2c_remove(struct platform_device *pdev)
diff --git a/target/linux/mediatek/patches-5.15/849-v6.0-i2c-mediatek-add-i2c-compatible-for-MT8188.patch b/target/linux/mediatek/patches-5.15/849-v6.0-i2c-mediatek-add-i2c-compatible-for-MT8188.patch
deleted file mode 100644
index 744aa96ed0c49b..00000000000000
--- a/target/linux/mediatek/patches-5.15/849-v6.0-i2c-mediatek-add-i2c-compatible-for-MT8188.patch
+++ /dev/null
@@ -1,82 +0,0 @@
-From 94c7f8af2c0a399c8aa66f2522b60c5784b5be6c Mon Sep 17 00:00:00 2001
-From: Kewei Xu <kewei.xu@mediatek.com>
-Date: Sat, 6 Aug 2022 18:02:49 +0800
-Subject: [PATCH 10/16] i2c: mediatek: add i2c compatible for MT8188
-
-Add i2c compatible for MT8188 and added mt_i2c_regs_v3[], since
-MT8188 i2c OFFSET_SLAVE_ADDR register changed from 0x04 to 0x94.
-
-Signed-off-by: Kewei Xu <kewei.xu@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Qii Wang <qii.wang@mediatek.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/i2c-mt65xx.c | 43 +++++++++++++++++++++++++++++++++
- 1 file changed, 43 insertions(+)
-
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -229,6 +229,35 @@ static const u16 mt_i2c_regs_v2[] = {
- 	[OFFSET_DCM_EN] = 0xf88,
- };
- 
-+static const u16 mt_i2c_regs_v3[] = {
-+	[OFFSET_DATA_PORT] = 0x0,
-+	[OFFSET_INTR_MASK] = 0x8,
-+	[OFFSET_INTR_STAT] = 0xc,
-+	[OFFSET_CONTROL] = 0x10,
-+	[OFFSET_TRANSFER_LEN] = 0x14,
-+	[OFFSET_TRANSAC_LEN] = 0x18,
-+	[OFFSET_DELAY_LEN] = 0x1c,
-+	[OFFSET_TIMING] = 0x20,
-+	[OFFSET_START] = 0x24,
-+	[OFFSET_EXT_CONF] = 0x28,
-+	[OFFSET_LTIMING] = 0x2c,
-+	[OFFSET_HS] = 0x30,
-+	[OFFSET_IO_CONFIG] = 0x34,
-+	[OFFSET_FIFO_ADDR_CLR] = 0x38,
-+	[OFFSET_SDA_TIMING] = 0x3c,
-+	[OFFSET_TRANSFER_LEN_AUX] = 0x44,
-+	[OFFSET_CLOCK_DIV] = 0x48,
-+	[OFFSET_SOFTRESET] = 0x50,
-+	[OFFSET_MULTI_DMA] = 0x8c,
-+	[OFFSET_SCL_MIS_COMP_POINT] = 0x90,
-+	[OFFSET_SLAVE_ADDR] = 0x94,
-+	[OFFSET_DEBUGSTAT] = 0xe4,
-+	[OFFSET_DEBUGCTRL] = 0xe8,
-+	[OFFSET_FIFO_STAT] = 0xf4,
-+	[OFFSET_FIFO_THRESH] = 0xf8,
-+	[OFFSET_DCM_EN] = 0xf88,
-+};
-+
- struct mtk_i2c_compatible {
- 	const struct i2c_adapter_quirks *quirks;
- 	const u16 *regs;
-@@ -442,6 +471,19 @@ static const struct mtk_i2c_compatible m
- 	.max_dma_support = 36,
- };
- 
-+static const struct mtk_i2c_compatible mt8188_compat = {
-+	.regs = mt_i2c_regs_v3,
-+	.pmic_i2c = 0,
-+	.dcm = 0,
-+	.auto_restart = 1,
-+	.aux_len_reg = 1,
-+	.timing_adjust = 1,
-+	.dma_sync = 0,
-+	.ltiming_adjust = 1,
-+	.apdma_sync = 1,
-+	.max_dma_support = 36,
-+};
-+
- static const struct mtk_i2c_compatible mt8192_compat = {
- 	.quirks = &mt8183_i2c_quirks,
- 	.regs = mt_i2c_regs_v2,
-@@ -465,6 +507,7 @@ static const struct of_device_id mtk_i2c
- 	{ .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
- 	{ .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat },
- 	{ .compatible = "mediatek,mt8186-i2c", .data = &mt8186_compat },
-+	{ .compatible = "mediatek,mt8188-i2c", .data = &mt8188_compat },
- 	{ .compatible = "mediatek,mt8192-i2c", .data = &mt8192_compat },
- 	{}
- };
diff --git a/target/linux/mediatek/patches-5.15/850-v6.0-i2c-move-drivers-from-strlcpy-to-strscpy.patch b/target/linux/mediatek/patches-5.15/850-v6.0-i2c-move-drivers-from-strlcpy-to-strscpy.patch
deleted file mode 100644
index d5c8a4e3008b59..00000000000000
--- a/target/linux/mediatek/patches-5.15/850-v6.0-i2c-move-drivers-from-strlcpy-to-strscpy.patch
+++ /dev/null
@@ -1,579 +0,0 @@
-From 2f4ca256a98cc19787b7c861109dd1150a21b0bf Mon Sep 17 00:00:00 2001
-From: Wolfram Sang <wsa+renesas@sang-engineering.com>
-Date: Thu, 11 Aug 2022 09:10:30 +0200
-Subject: [PATCH 11/16] i2c: move drivers from strlcpy to strscpy
-
-Follow the advice of the below link and prefer 'strscpy'. Conversion is
-easy because no driver used the return value and has been done with a
-simple sed invocation.
-
-Link: https://lore.kernel.org/r/CAHk-=wgfRnXz0W3D37d01q3JFkr_i_uTL=V6A6G1oUZcprmknw@mail.gmail.com/
-Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/i2c-altera.c         | 2 +-
- drivers/i2c/busses/i2c-aspeed.c         | 2 +-
- drivers/i2c/busses/i2c-au1550.c         | 2 +-
- drivers/i2c/busses/i2c-axxia.c          | 2 +-
- drivers/i2c/busses/i2c-bcm-kona.c       | 2 +-
- drivers/i2c/busses/i2c-cbus-gpio.c      | 2 +-
- drivers/i2c/busses/i2c-cht-wc.c         | 2 +-
- drivers/i2c/busses/i2c-cros-ec-tunnel.c | 2 +-
- drivers/i2c/busses/i2c-davinci.c        | 2 +-
- drivers/i2c/busses/i2c-digicolor.c      | 2 +-
- drivers/i2c/busses/i2c-eg20t.c          | 2 +-
- drivers/i2c/busses/i2c-emev2.c          | 2 +-
- drivers/i2c/busses/i2c-exynos5.c        | 2 +-
- drivers/i2c/busses/i2c-gpio.c           | 2 +-
- drivers/i2c/busses/i2c-highlander.c     | 2 +-
- drivers/i2c/busses/i2c-hix5hd2.c        | 2 +-
- drivers/i2c/busses/i2c-i801.c           | 4 ++--
- drivers/i2c/busses/i2c-ibm_iic.c        | 2 +-
- drivers/i2c/busses/i2c-icy.c            | 2 +-
- drivers/i2c/busses/i2c-imx-lpi2c.c      | 2 +-
- drivers/i2c/busses/i2c-lpc2k.c          | 2 +-
- drivers/i2c/busses/i2c-meson.c          | 2 +-
- drivers/i2c/busses/i2c-mt65xx.c         | 2 +-
- drivers/i2c/busses/i2c-mt7621.c         | 2 +-
- drivers/i2c/busses/i2c-mv64xxx.c        | 2 +-
- drivers/i2c/busses/i2c-mxs.c            | 2 +-
- drivers/i2c/busses/i2c-nvidia-gpu.c     | 2 +-
- drivers/i2c/busses/i2c-omap.c           | 2 +-
- drivers/i2c/busses/i2c-opal.c           | 4 ++--
- drivers/i2c/busses/i2c-parport.c        | 2 +-
- drivers/i2c/busses/i2c-pxa.c            | 2 +-
- drivers/i2c/busses/i2c-qcom-geni.c      | 2 +-
- drivers/i2c/busses/i2c-qup.c            | 2 +-
- drivers/i2c/busses/i2c-rcar.c           | 2 +-
- drivers/i2c/busses/i2c-riic.c           | 2 +-
- drivers/i2c/busses/i2c-rk3x.c           | 2 +-
- drivers/i2c/busses/i2c-s3c2410.c        | 2 +-
- drivers/i2c/busses/i2c-sh_mobile.c      | 2 +-
- drivers/i2c/busses/i2c-simtec.c         | 2 +-
- drivers/i2c/busses/i2c-taos-evm.c       | 2 +-
- drivers/i2c/busses/i2c-tegra-bpmp.c     | 2 +-
- drivers/i2c/busses/i2c-tegra.c          | 2 +-
- drivers/i2c/busses/i2c-uniphier-f.c     | 2 +-
- drivers/i2c/busses/i2c-uniphier.c       | 2 +-
- drivers/i2c/busses/i2c-versatile.c      | 2 +-
- drivers/i2c/busses/i2c-wmt.c            | 2 +-
- 46 files changed, 48 insertions(+), 48 deletions(-)
-
---- a/drivers/i2c/busses/i2c-altera.c
-+++ b/drivers/i2c/busses/i2c-altera.c
-@@ -447,7 +447,7 @@ static int altr_i2c_probe(struct platfor
- 	mutex_unlock(&idev->isr_mutex);
- 
- 	i2c_set_adapdata(&idev->adapter, idev);
--	strlcpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name));
-+	strscpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name));
- 	idev->adapter.owner = THIS_MODULE;
- 	idev->adapter.algo = &altr_i2c_algo;
- 	idev->adapter.dev.parent = &pdev->dev;
---- a/drivers/i2c/busses/i2c-aspeed.c
-+++ b/drivers/i2c/busses/i2c-aspeed.c
-@@ -1044,7 +1044,7 @@ static int aspeed_i2c_probe_bus(struct p
- 	bus->adap.algo = &aspeed_i2c_algo;
- 	bus->adap.dev.parent = &pdev->dev;
- 	bus->adap.dev.of_node = pdev->dev.of_node;
--	strlcpy(bus->adap.name, pdev->name, sizeof(bus->adap.name));
-+	strscpy(bus->adap.name, pdev->name, sizeof(bus->adap.name));
- 	i2c_set_adapdata(&bus->adap, bus);
- 
- 	bus->dev = &pdev->dev;
---- a/drivers/i2c/busses/i2c-au1550.c
-+++ b/drivers/i2c/busses/i2c-au1550.c
-@@ -321,7 +321,7 @@ i2c_au1550_probe(struct platform_device
- 	priv->adap.algo = &au1550_algo;
- 	priv->adap.algo_data = priv;
- 	priv->adap.dev.parent = &pdev->dev;
--	strlcpy(priv->adap.name, "Au1xxx PSC I2C", sizeof(priv->adap.name));
-+	strscpy(priv->adap.name, "Au1xxx PSC I2C", sizeof(priv->adap.name));
- 
- 	/* Now, set up the PSC for SMBus PIO mode. */
- 	i2c_au1550_setup(priv);
---- a/drivers/i2c/busses/i2c-axxia.c
-+++ b/drivers/i2c/busses/i2c-axxia.c
-@@ -783,7 +783,7 @@ static int axxia_i2c_probe(struct platfo
- 	}
- 
- 	i2c_set_adapdata(&idev->adapter, idev);
--	strlcpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name));
-+	strscpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name));
- 	idev->adapter.owner = THIS_MODULE;
- 	idev->adapter.algo = &axxia_i2c_algo;
- 	idev->adapter.bus_recovery_info = &axxia_i2c_recovery_info;
---- a/drivers/i2c/busses/i2c-bcm-kona.c
-+++ b/drivers/i2c/busses/i2c-bcm-kona.c
-@@ -849,7 +849,7 @@ static int bcm_kona_i2c_probe(struct pla
- 	adap = &dev->adapter;
- 	i2c_set_adapdata(adap, dev);
- 	adap->owner = THIS_MODULE;
--	strlcpy(adap->name, "Broadcom I2C adapter", sizeof(adap->name));
-+	strscpy(adap->name, "Broadcom I2C adapter", sizeof(adap->name));
- 	adap->algo = &bcm_algo;
- 	adap->dev.parent = &pdev->dev;
- 	adap->dev.of_node = pdev->dev.of_node;
---- a/drivers/i2c/busses/i2c-cbus-gpio.c
-+++ b/drivers/i2c/busses/i2c-cbus-gpio.c
-@@ -245,7 +245,7 @@ static int cbus_i2c_probe(struct platfor
- 	adapter->nr		= pdev->id;
- 	adapter->timeout	= HZ;
- 	adapter->algo		= &cbus_i2c_algo;
--	strlcpy(adapter->name, "CBUS I2C adapter", sizeof(adapter->name));
-+	strscpy(adapter->name, "CBUS I2C adapter", sizeof(adapter->name));
- 
- 	spin_lock_init(&chost->lock);
- 	chost->dev = &pdev->dev;
---- a/drivers/i2c/busses/i2c-cht-wc.c
-+++ b/drivers/i2c/busses/i2c-cht-wc.c
-@@ -334,7 +334,7 @@ static int cht_wc_i2c_adap_i2c_probe(str
- 	adap->adapter.class = I2C_CLASS_HWMON;
- 	adap->adapter.algo = &cht_wc_i2c_adap_algo;
- 	adap->adapter.lock_ops = &cht_wc_i2c_adap_lock_ops;
--	strlcpy(adap->adapter.name, "PMIC I2C Adapter",
-+	strscpy(adap->adapter.name, "PMIC I2C Adapter",
- 		sizeof(adap->adapter.name));
- 	adap->adapter.dev.parent = &pdev->dev;
- 
---- a/drivers/i2c/busses/i2c-cros-ec-tunnel.c
-+++ b/drivers/i2c/busses/i2c-cros-ec-tunnel.c
-@@ -267,7 +267,7 @@ static int ec_i2c_probe(struct platform_
- 	bus->dev = dev;
- 
- 	bus->adap.owner = THIS_MODULE;
--	strlcpy(bus->adap.name, "cros-ec-i2c-tunnel", sizeof(bus->adap.name));
-+	strscpy(bus->adap.name, "cros-ec-i2c-tunnel", sizeof(bus->adap.name));
- 	bus->adap.algo = &ec_i2c_algorithm;
- 	bus->adap.algo_data = bus;
- 	bus->adap.dev.parent = &pdev->dev;
---- a/drivers/i2c/busses/i2c-davinci.c
-+++ b/drivers/i2c/busses/i2c-davinci.c
-@@ -847,7 +847,7 @@ static int davinci_i2c_probe(struct plat
- 	i2c_set_adapdata(adap, dev);
- 	adap->owner = THIS_MODULE;
- 	adap->class = I2C_CLASS_DEPRECATED;
--	strlcpy(adap->name, "DaVinci I2C adapter", sizeof(adap->name));
-+	strscpy(adap->name, "DaVinci I2C adapter", sizeof(adap->name));
- 	adap->algo = &i2c_davinci_algo;
- 	adap->dev.parent = &pdev->dev;
- 	adap->timeout = DAVINCI_I2C_TIMEOUT;
---- a/drivers/i2c/busses/i2c-digicolor.c
-+++ b/drivers/i2c/busses/i2c-digicolor.c
-@@ -322,7 +322,7 @@ static int dc_i2c_probe(struct platform_
- 	if (ret < 0)
- 		return ret;
- 
--	strlcpy(i2c->adap.name, "Conexant Digicolor I2C adapter",
-+	strscpy(i2c->adap.name, "Conexant Digicolor I2C adapter",
- 		sizeof(i2c->adap.name));
- 	i2c->adap.owner = THIS_MODULE;
- 	i2c->adap.algo = &dc_i2c_algorithm;
---- a/drivers/i2c/busses/i2c-eg20t.c
-+++ b/drivers/i2c/busses/i2c-eg20t.c
-@@ -773,7 +773,7 @@ static int pch_i2c_probe(struct pci_dev
- 
- 		pch_adap->owner = THIS_MODULE;
- 		pch_adap->class = I2C_CLASS_HWMON;
--		strlcpy(pch_adap->name, KBUILD_MODNAME, sizeof(pch_adap->name));
-+		strscpy(pch_adap->name, KBUILD_MODNAME, sizeof(pch_adap->name));
- 		pch_adap->algo = &pch_algorithm;
- 		pch_adap->algo_data = &adap_info->pch_data[i];
- 
---- a/drivers/i2c/busses/i2c-emev2.c
-+++ b/drivers/i2c/busses/i2c-emev2.c
-@@ -371,7 +371,7 @@ static int em_i2c_probe(struct platform_
- 	if (IS_ERR(priv->base))
- 		return PTR_ERR(priv->base);
- 
--	strlcpy(priv->adap.name, "EMEV2 I2C", sizeof(priv->adap.name));
-+	strscpy(priv->adap.name, "EMEV2 I2C", sizeof(priv->adap.name));
- 
- 	priv->sclk = devm_clk_get(&pdev->dev, "sclk");
- 	if (IS_ERR(priv->sclk))
---- a/drivers/i2c/busses/i2c-exynos5.c
-+++ b/drivers/i2c/busses/i2c-exynos5.c
-@@ -751,7 +751,7 @@ static int exynos5_i2c_probe(struct plat
- 	if (of_property_read_u32(np, "clock-frequency", &i2c->op_clock))
- 		i2c->op_clock = I2C_MAX_STANDARD_MODE_FREQ;
- 
--	strlcpy(i2c->adap.name, "exynos5-i2c", sizeof(i2c->adap.name));
-+	strscpy(i2c->adap.name, "exynos5-i2c", sizeof(i2c->adap.name));
- 	i2c->adap.owner   = THIS_MODULE;
- 	i2c->adap.algo    = &exynos5_i2c_algorithm;
- 	i2c->adap.retries = 3;
---- a/drivers/i2c/busses/i2c-gpio.c
-+++ b/drivers/i2c/busses/i2c-gpio.c
-@@ -436,7 +436,7 @@ static int i2c_gpio_probe(struct platfor
- 
- 	adap->owner = THIS_MODULE;
- 	if (np)
--		strlcpy(adap->name, dev_name(dev), sizeof(adap->name));
-+		strscpy(adap->name, dev_name(dev), sizeof(adap->name));
- 	else
- 		snprintf(adap->name, sizeof(adap->name), "i2c-gpio%d", pdev->id);
- 
---- a/drivers/i2c/busses/i2c-highlander.c
-+++ b/drivers/i2c/busses/i2c-highlander.c
-@@ -402,7 +402,7 @@ static int highlander_i2c_probe(struct p
- 	i2c_set_adapdata(adap, dev);
- 	adap->owner = THIS_MODULE;
- 	adap->class = I2C_CLASS_HWMON;
--	strlcpy(adap->name, "HL FPGA I2C adapter", sizeof(adap->name));
-+	strscpy(adap->name, "HL FPGA I2C adapter", sizeof(adap->name));
- 	adap->algo = &highlander_i2c_algo;
- 	adap->dev.parent = &pdev->dev;
- 	adap->nr = pdev->id;
---- a/drivers/i2c/busses/i2c-hix5hd2.c
-+++ b/drivers/i2c/busses/i2c-hix5hd2.c
-@@ -423,7 +423,7 @@ static int hix5hd2_i2c_probe(struct plat
- 	}
- 	clk_prepare_enable(priv->clk);
- 
--	strlcpy(priv->adap.name, "hix5hd2-i2c", sizeof(priv->adap.name));
-+	strscpy(priv->adap.name, "hix5hd2-i2c", sizeof(priv->adap.name));
- 	priv->dev = &pdev->dev;
- 	priv->adap.owner = THIS_MODULE;
- 	priv->adap.algo = &hix5hd2_i2c_algorithm;
---- a/drivers/i2c/busses/i2c-i801.c
-+++ b/drivers/i2c/busses/i2c-i801.c
-@@ -1110,7 +1110,7 @@ static void dmi_check_onboard_device(u8
- 
- 		memset(&info, 0, sizeof(struct i2c_board_info));
- 		info.addr = dmi_devices[i].i2c_addr;
--		strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
-+		strscpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
- 		i2c_new_client_device(adap, &info);
- 		break;
- 	}
-@@ -1266,7 +1266,7 @@ static void register_dell_lis3lv02d_i2c_
- 
- 	memset(&info, 0, sizeof(struct i2c_board_info));
- 	info.addr = dell_lis3lv02d_devices[i].i2c_addr;
--	strlcpy(info.type, "lis3lv02d", I2C_NAME_SIZE);
-+	strscpy(info.type, "lis3lv02d", I2C_NAME_SIZE);
- 	i2c_new_client_device(&priv->adapter, &info);
- }
- 
---- a/drivers/i2c/busses/i2c-ibm_iic.c
-+++ b/drivers/i2c/busses/i2c-ibm_iic.c
-@@ -736,7 +736,7 @@ static int iic_probe(struct platform_dev
- 	adap = &dev->adap;
- 	adap->dev.parent = &ofdev->dev;
- 	adap->dev.of_node = of_node_get(np);
--	strlcpy(adap->name, "IBM IIC", sizeof(adap->name));
-+	strscpy(adap->name, "IBM IIC", sizeof(adap->name));
- 	i2c_set_adapdata(adap, dev);
- 	adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
- 	adap->algo = &iic_algo;
---- a/drivers/i2c/busses/i2c-icy.c
-+++ b/drivers/i2c/busses/i2c-icy.c
-@@ -141,7 +141,7 @@ static int icy_probe(struct zorro_dev *z
- 	i2c->adapter.owner = THIS_MODULE;
- 	/* i2c->adapter.algo assigned by i2c_pcf_add_bus() */
- 	i2c->adapter.algo_data = algo_data;
--	strlcpy(i2c->adapter.name, "ICY I2C Zorro adapter",
-+	strscpy(i2c->adapter.name, "ICY I2C Zorro adapter",
- 		sizeof(i2c->adapter.name));
- 
- 	if (!devm_request_mem_region(&z->dev,
---- a/drivers/i2c/busses/i2c-imx-lpi2c.c
-+++ b/drivers/i2c/busses/i2c-imx-lpi2c.c
-@@ -564,7 +564,7 @@ static int lpi2c_imx_probe(struct platfo
- 	lpi2c_imx->adapter.algo		= &lpi2c_imx_algo;
- 	lpi2c_imx->adapter.dev.parent	= &pdev->dev;
- 	lpi2c_imx->adapter.dev.of_node	= pdev->dev.of_node;
--	strlcpy(lpi2c_imx->adapter.name, pdev->name,
-+	strscpy(lpi2c_imx->adapter.name, pdev->name,
- 		sizeof(lpi2c_imx->adapter.name));
- 
- 	lpi2c_imx->clk = devm_clk_get(&pdev->dev, NULL);
---- a/drivers/i2c/busses/i2c-lpc2k.c
-+++ b/drivers/i2c/busses/i2c-lpc2k.c
-@@ -417,7 +417,7 @@ static int i2c_lpc2k_probe(struct platfo
- 
- 	i2c_set_adapdata(&i2c->adap, i2c);
- 	i2c->adap.owner = THIS_MODULE;
--	strlcpy(i2c->adap.name, "LPC2K I2C adapter", sizeof(i2c->adap.name));
-+	strscpy(i2c->adap.name, "LPC2K I2C adapter", sizeof(i2c->adap.name));
- 	i2c->adap.algo = &i2c_lpc2k_algorithm;
- 	i2c->adap.dev.parent = &pdev->dev;
- 	i2c->adap.dev.of_node = pdev->dev.of_node;
---- a/drivers/i2c/busses/i2c-meson.c
-+++ b/drivers/i2c/busses/i2c-meson.c
-@@ -451,7 +451,7 @@ static int meson_i2c_probe(struct platfo
- 		return ret;
- 	}
- 
--	strlcpy(i2c->adap.name, "Meson I2C adapter",
-+	strscpy(i2c->adap.name, "Meson I2C adapter",
- 		sizeof(i2c->adap.name));
- 	i2c->adap.owner = THIS_MODULE;
- 	i2c->adap.algo = &meson_i2c_algorithm;
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -1432,7 +1432,7 @@ static int mtk_i2c_probe(struct platform
- 		speed_clk = I2C_MT65XX_CLK_MAIN;
- 	}
- 
--	strlcpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name));
-+	strscpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name));
- 
- 	ret = mtk_i2c_set_speed(i2c, clk_get_rate(i2c->clocks[speed_clk].clk));
- 	if (ret) {
---- a/drivers/i2c/busses/i2c-mt7621.c
-+++ b/drivers/i2c/busses/i2c-mt7621.c
-@@ -315,7 +315,7 @@ static int mtk_i2c_probe(struct platform
- 	adap->dev.parent = &pdev->dev;
- 	i2c_set_adapdata(adap, i2c);
- 	adap->dev.of_node = pdev->dev.of_node;
--	strlcpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name));
-+	strscpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name));
- 
- 	platform_set_drvdata(pdev, i2c);
- 
---- a/drivers/i2c/busses/i2c-mv64xxx.c
-+++ b/drivers/i2c/busses/i2c-mv64xxx.c
-@@ -1000,7 +1000,7 @@ mv64xxx_i2c_probe(struct platform_device
- 	if (IS_ERR(drv_data->reg_base))
- 		return PTR_ERR(drv_data->reg_base);
- 
--	strlcpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter",
-+	strscpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter",
- 		sizeof(drv_data->adapter.name));
- 
- 	init_waitqueue_head(&drv_data->waitq);
---- a/drivers/i2c/busses/i2c-mxs.c
-+++ b/drivers/i2c/busses/i2c-mxs.c
-@@ -838,7 +838,7 @@ static int mxs_i2c_probe(struct platform
- 		return err;
- 
- 	adap = &i2c->adapter;
--	strlcpy(adap->name, "MXS I2C adapter", sizeof(adap->name));
-+	strscpy(adap->name, "MXS I2C adapter", sizeof(adap->name));
- 	adap->owner = THIS_MODULE;
- 	adap->algo = &mxs_i2c_algo;
- 	adap->quirks = &mxs_i2c_quirks;
---- a/drivers/i2c/busses/i2c-nvidia-gpu.c
-+++ b/drivers/i2c/busses/i2c-nvidia-gpu.c
-@@ -319,7 +319,7 @@ static int gpu_i2c_probe(struct pci_dev
- 
- 	i2c_set_adapdata(&i2cd->adapter, i2cd);
- 	i2cd->adapter.owner = THIS_MODULE;
--	strlcpy(i2cd->adapter.name, "NVIDIA GPU I2C adapter",
-+	strscpy(i2cd->adapter.name, "NVIDIA GPU I2C adapter",
- 		sizeof(i2cd->adapter.name));
- 	i2cd->adapter.algo = &gpu_i2c_algorithm;
- 	i2cd->adapter.quirks = &gpu_i2c_quirks;
---- a/drivers/i2c/busses/i2c-omap.c
-+++ b/drivers/i2c/busses/i2c-omap.c
-@@ -1488,7 +1488,7 @@ omap_i2c_probe(struct platform_device *p
- 	i2c_set_adapdata(adap, omap);
- 	adap->owner = THIS_MODULE;
- 	adap->class = I2C_CLASS_DEPRECATED;
--	strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
-+	strscpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
- 	adap->algo = &omap_i2c_algo;
- 	adap->quirks = &omap_i2c_quirks;
- 	adap->dev.parent = &pdev->dev;
---- a/drivers/i2c/busses/i2c-opal.c
-+++ b/drivers/i2c/busses/i2c-opal.c
-@@ -220,9 +220,9 @@ static int i2c_opal_probe(struct platfor
- 	adapter->dev.of_node = of_node_get(pdev->dev.of_node);
- 	pname = of_get_property(pdev->dev.of_node, "ibm,port-name", NULL);
- 	if (pname)
--		strlcpy(adapter->name, pname, sizeof(adapter->name));
-+		strscpy(adapter->name, pname, sizeof(adapter->name));
- 	else
--		strlcpy(adapter->name, "opal", sizeof(adapter->name));
-+		strscpy(adapter->name, "opal", sizeof(adapter->name));
- 
- 	platform_set_drvdata(pdev, adapter);
- 	rc = i2c_add_adapter(adapter);
---- a/drivers/i2c/busses/i2c-parport.c
-+++ b/drivers/i2c/busses/i2c-parport.c
-@@ -308,7 +308,7 @@ static void i2c_parport_attach(struct pa
- 	/* Fill the rest of the structure */
- 	adapter->adapter.owner = THIS_MODULE;
- 	adapter->adapter.class = I2C_CLASS_HWMON;
--	strlcpy(adapter->adapter.name, "Parallel port adapter",
-+	strscpy(adapter->adapter.name, "Parallel port adapter",
- 		sizeof(adapter->adapter.name));
- 	adapter->algo_data = parport_algo_data;
- 	/* Slow down if we can't sense SCL */
---- a/drivers/i2c/busses/i2c-pxa.c
-+++ b/drivers/i2c/busses/i2c-pxa.c
-@@ -1463,7 +1463,7 @@ static int i2c_pxa_probe(struct platform
- 	spin_lock_init(&i2c->lock);
- 	init_waitqueue_head(&i2c->wait);
- 
--	strlcpy(i2c->adap.name, "pxa_i2c-i2c", sizeof(i2c->adap.name));
-+	strscpy(i2c->adap.name, "pxa_i2c-i2c", sizeof(i2c->adap.name));
- 
- 	i2c->clk = devm_clk_get(&dev->dev, NULL);
- 	if (IS_ERR(i2c->clk)) {
---- a/drivers/i2c/busses/i2c-qcom-geni.c
-+++ b/drivers/i2c/busses/i2c-qcom-geni.c
-@@ -577,7 +577,7 @@ static int geni_i2c_probe(struct platfor
- 	i2c_set_adapdata(&gi2c->adap, gi2c);
- 	gi2c->adap.dev.parent = dev;
- 	gi2c->adap.dev.of_node = dev->of_node;
--	strlcpy(gi2c->adap.name, "Geni-I2C", sizeof(gi2c->adap.name));
-+	strscpy(gi2c->adap.name, "Geni-I2C", sizeof(gi2c->adap.name));
- 
- 	ret = geni_icc_get(&gi2c->se, "qup-memory");
- 	if (ret)
---- a/drivers/i2c/busses/i2c-qup.c
-+++ b/drivers/i2c/busses/i2c-qup.c
-@@ -1885,7 +1885,7 @@ nodma:
- 	qup->adap.dev.of_node = pdev->dev.of_node;
- 	qup->is_last = true;
- 
--	strlcpy(qup->adap.name, "QUP I2C adapter", sizeof(qup->adap.name));
-+	strscpy(qup->adap.name, "QUP I2C adapter", sizeof(qup->adap.name));
- 
- 	pm_runtime_set_autosuspend_delay(qup->dev, MSEC_PER_SEC);
- 	pm_runtime_use_autosuspend(qup->dev);
---- a/drivers/i2c/busses/i2c-rcar.c
-+++ b/drivers/i2c/busses/i2c-rcar.c
-@@ -1059,7 +1059,7 @@ static int rcar_i2c_probe(struct platfor
- 	adap->bus_recovery_info = &rcar_i2c_bri;
- 	adap->quirks = &rcar_i2c_quirks;
- 	i2c_set_adapdata(adap, priv);
--	strlcpy(adap->name, pdev->name, sizeof(adap->name));
-+	strscpy(adap->name, pdev->name, sizeof(adap->name));
- 
- 	/* Init DMA */
- 	sg_init_table(&priv->sg, 1);
---- a/drivers/i2c/busses/i2c-riic.c
-+++ b/drivers/i2c/busses/i2c-riic.c
-@@ -447,7 +447,7 @@ static int riic_i2c_probe(struct platfor
- 
- 	adap = &riic->adapter;
- 	i2c_set_adapdata(adap, riic);
--	strlcpy(adap->name, "Renesas RIIC adapter", sizeof(adap->name));
-+	strscpy(adap->name, "Renesas RIIC adapter", sizeof(adap->name));
- 	adap->owner = THIS_MODULE;
- 	adap->algo = &riic_algo;
- 	adap->dev.parent = &pdev->dev;
---- a/drivers/i2c/busses/i2c-rk3x.c
-+++ b/drivers/i2c/busses/i2c-rk3x.c
-@@ -1240,7 +1240,7 @@ static int rk3x_i2c_probe(struct platfor
- 	/* use common interface to get I2C timing properties */
- 	i2c_parse_fw_timings(&pdev->dev, &i2c->t, true);
- 
--	strlcpy(i2c->adap.name, "rk3x-i2c", sizeof(i2c->adap.name));
-+	strscpy(i2c->adap.name, "rk3x-i2c", sizeof(i2c->adap.name));
- 	i2c->adap.owner = THIS_MODULE;
- 	i2c->adap.algo = &rk3x_i2c_algorithm;
- 	i2c->adap.retries = 3;
---- a/drivers/i2c/busses/i2c-s3c2410.c
-+++ b/drivers/i2c/busses/i2c-s3c2410.c
-@@ -1076,7 +1076,7 @@ static int s3c24xx_i2c_probe(struct plat
- 	else
- 		s3c24xx_i2c_parse_dt(pdev->dev.of_node, i2c);
- 
--	strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name));
-+	strscpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name));
- 	i2c->adap.owner = THIS_MODULE;
- 	i2c->adap.algo = &s3c24xx_i2c_algorithm;
- 	i2c->adap.retries = 2;
---- a/drivers/i2c/busses/i2c-sh_mobile.c
-+++ b/drivers/i2c/busses/i2c-sh_mobile.c
-@@ -930,7 +930,7 @@ static int sh_mobile_i2c_probe(struct pl
- 	adap->nr = dev->id;
- 	adap->dev.of_node = dev->dev.of_node;
- 
--	strlcpy(adap->name, dev->name, sizeof(adap->name));
-+	strscpy(adap->name, dev->name, sizeof(adap->name));
- 
- 	spin_lock_init(&pd->lock);
- 	init_waitqueue_head(&pd->wait);
---- a/drivers/i2c/busses/i2c-simtec.c
-+++ b/drivers/i2c/busses/i2c-simtec.c
-@@ -99,7 +99,7 @@ static int simtec_i2c_probe(struct platf
- 	pd->adap.algo_data = &pd->bit;
- 	pd->adap.dev.parent = &dev->dev;
- 
--	strlcpy(pd->adap.name, "Simtec I2C", sizeof(pd->adap.name));
-+	strscpy(pd->adap.name, "Simtec I2C", sizeof(pd->adap.name));
- 
- 	pd->bit.data = pd;
- 	pd->bit.setsda = simtec_i2c_setsda;
---- a/drivers/i2c/busses/i2c-taos-evm.c
-+++ b/drivers/i2c/busses/i2c-taos-evm.c
-@@ -239,7 +239,7 @@ static int taos_connect(struct serio *se
- 		dev_err(&serio->dev, "TAOS EVM identification failed\n");
- 		goto exit_close;
- 	}
--	strlcpy(adapter->name, name, sizeof(adapter->name));
-+	strscpy(adapter->name, name, sizeof(adapter->name));
- 
- 	/* Turn echo off for better performance */
- 	taos->state = TAOS_STATE_EOFF;
---- a/drivers/i2c/busses/i2c-tegra-bpmp.c
-+++ b/drivers/i2c/busses/i2c-tegra-bpmp.c
-@@ -305,7 +305,7 @@ static int tegra_bpmp_i2c_probe(struct p
- 
- 	i2c_set_adapdata(&i2c->adapter, i2c);
- 	i2c->adapter.owner = THIS_MODULE;
--	strlcpy(i2c->adapter.name, "Tegra BPMP I2C adapter",
-+	strscpy(i2c->adapter.name, "Tegra BPMP I2C adapter",
- 		sizeof(i2c->adapter.name));
- 	i2c->adapter.algo = &tegra_bpmp_i2c_algo;
- 	i2c->adapter.dev.parent = &pdev->dev;
---- a/drivers/i2c/busses/i2c-tegra.c
-+++ b/drivers/i2c/busses/i2c-tegra.c
-@@ -1799,7 +1799,7 @@ static int tegra_i2c_probe(struct platfo
- 	if (i2c_dev->hw->supports_bus_clear)
- 		i2c_dev->adapter.bus_recovery_info = &tegra_i2c_recovery_info;
- 
--	strlcpy(i2c_dev->adapter.name, dev_name(i2c_dev->dev),
-+	strscpy(i2c_dev->adapter.name, dev_name(i2c_dev->dev),
- 		sizeof(i2c_dev->adapter.name));
- 
- 	err = i2c_add_numbered_adapter(&i2c_dev->adapter);
---- a/drivers/i2c/busses/i2c-uniphier-f.c
-+++ b/drivers/i2c/busses/i2c-uniphier-f.c
-@@ -564,7 +564,7 @@ static int uniphier_fi2c_probe(struct pl
- 	priv->adap.algo = &uniphier_fi2c_algo;
- 	priv->adap.dev.parent = dev;
- 	priv->adap.dev.of_node = dev->of_node;
--	strlcpy(priv->adap.name, "UniPhier FI2C", sizeof(priv->adap.name));
-+	strscpy(priv->adap.name, "UniPhier FI2C", sizeof(priv->adap.name));
- 	priv->adap.bus_recovery_info = &uniphier_fi2c_bus_recovery_info;
- 	i2c_set_adapdata(&priv->adap, priv);
- 	platform_set_drvdata(pdev, priv);
---- a/drivers/i2c/busses/i2c-uniphier.c
-+++ b/drivers/i2c/busses/i2c-uniphier.c
-@@ -358,7 +358,7 @@ static int uniphier_i2c_probe(struct pla
- 	priv->adap.algo = &uniphier_i2c_algo;
- 	priv->adap.dev.parent = dev;
- 	priv->adap.dev.of_node = dev->of_node;
--	strlcpy(priv->adap.name, "UniPhier I2C", sizeof(priv->adap.name));
-+	strscpy(priv->adap.name, "UniPhier I2C", sizeof(priv->adap.name));
- 	priv->adap.bus_recovery_info = &uniphier_i2c_bus_recovery_info;
- 	i2c_set_adapdata(&priv->adap, priv);
- 	platform_set_drvdata(pdev, priv);
---- a/drivers/i2c/busses/i2c-versatile.c
-+++ b/drivers/i2c/busses/i2c-versatile.c
-@@ -79,7 +79,7 @@ static int i2c_versatile_probe(struct pl
- 	writel(SCL | SDA, i2c->base + I2C_CONTROLS);
- 
- 	i2c->adap.owner = THIS_MODULE;
--	strlcpy(i2c->adap.name, "Versatile I2C adapter", sizeof(i2c->adap.name));
-+	strscpy(i2c->adap.name, "Versatile I2C adapter", sizeof(i2c->adap.name));
- 	i2c->adap.algo_data = &i2c->algo;
- 	i2c->adap.dev.parent = &dev->dev;
- 	i2c->adap.dev.of_node = dev->dev.of_node;
---- a/drivers/i2c/busses/i2c-wmt.c
-+++ b/drivers/i2c/busses/i2c-wmt.c
-@@ -413,7 +413,7 @@ static int wmt_i2c_probe(struct platform
- 
- 	adap = &i2c_dev->adapter;
- 	i2c_set_adapdata(adap, i2c_dev);
--	strlcpy(adap->name, "WMT I2C adapter", sizeof(adap->name));
-+	strscpy(adap->name, "WMT I2C adapter", sizeof(adap->name));
- 	adap->owner = THIS_MODULE;
- 	adap->algo = &wmt_i2c_algo;
- 	adap->dev.parent = &pdev->dev;
diff --git a/target/linux/mediatek/patches-5.15/851-v6.2-i2c-mediatek-add-mt7986-support.patch b/target/linux/mediatek/patches-5.15/851-v6.2-i2c-mediatek-add-mt7986-support.patch
deleted file mode 100644
index 4c398c59f93551..00000000000000
--- a/target/linux/mediatek/patches-5.15/851-v6.2-i2c-mediatek-add-mt7986-support.patch
+++ /dev/null
@@ -1,44 +0,0 @@
-From 11f9a0f4e51887ad7b4a2898a368fcd0c2984e89 Mon Sep 17 00:00:00 2001
-From: Frank Wunderlich <frank-w@public-files.de>
-Date: Sun, 9 Oct 2022 12:16:31 +0200
-Subject: [PATCH 12/16] i2c: mediatek: add mt7986 support
-
-Add i2c support for MT7986 SoC.
-
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/i2c-mt65xx.c | 14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -431,6 +431,19 @@ static const struct mtk_i2c_compatible m
- 	.max_dma_support = 33,
- };
- 
-+static const struct mtk_i2c_compatible mt7986_compat = {
-+	.quirks = &mt7622_i2c_quirks,
-+	.regs = mt_i2c_regs_v1,
-+	.pmic_i2c = 0,
-+	.dcm = 1,
-+	.auto_restart = 1,
-+	.aux_len_reg = 1,
-+	.timing_adjust = 0,
-+	.dma_sync = 1,
-+	.ltiming_adjust = 0,
-+	.max_dma_support = 32,
-+};
-+
- static const struct mtk_i2c_compatible mt8173_compat = {
- 	.regs = mt_i2c_regs_v1,
- 	.pmic_i2c = 0,
-@@ -503,6 +516,7 @@ static const struct of_device_id mtk_i2c
- 	{ .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat },
- 	{ .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat },
- 	{ .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat },
-+	{ .compatible = "mediatek,mt7986-i2c", .data = &mt7986_compat },
- 	{ .compatible = "mediatek,mt8168-i2c", .data = &mt8168_compat },
- 	{ .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
- 	{ .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat },
diff --git a/target/linux/mediatek/patches-5.15/852-v6.3-i2c-mt65xx-Use-devm_platform_get_and_ioremap_resourc.patch b/target/linux/mediatek/patches-5.15/852-v6.3-i2c-mt65xx-Use-devm_platform_get_and_ioremap_resourc.patch
deleted file mode 100644
index 18c66cdac52910..00000000000000
--- a/target/linux/mediatek/patches-5.15/852-v6.3-i2c-mt65xx-Use-devm_platform_get_and_ioremap_resourc.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From 98204ccafd45a8a6109ff2d60e2c179b95d92578 Mon Sep 17 00:00:00 2001
-From: ye xingchen <ye.xingchen@zte.com.cn>
-Date: Thu, 19 Jan 2023 17:19:58 +0800
-Subject: [PATCH 13/16] i2c: mt65xx: Use
- devm_platform_get_and_ioremap_resource()
-
-Convert platform_get_resource(), devm_ioremap_resource() to a single
-call to devm_platform_get_and_ioremap_resource(), as this is exactly
-what this function does.
-
-Signed-off-by: ye xingchen <ye.xingchen@zte.com.cn>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/i2c-mt65xx.c | 7 ++-----
- 1 file changed, 2 insertions(+), 5 deletions(-)
-
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -1366,20 +1366,17 @@ static int mtk_i2c_probe(struct platform
- {
- 	int ret = 0;
- 	struct mtk_i2c *i2c;
--	struct resource *res;
- 	int i, irq, speed_clk;
- 
- 	i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
- 	if (!i2c)
- 		return -ENOMEM;
- 
--	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
--	i2c->base = devm_ioremap_resource(&pdev->dev, res);
-+	i2c->base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
- 	if (IS_ERR(i2c->base))
- 		return PTR_ERR(i2c->base);
- 
--	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
--	i2c->pdmabase = devm_ioremap_resource(&pdev->dev, res);
-+	i2c->pdmabase = devm_platform_get_and_ioremap_resource(pdev, 1, NULL);
- 	if (IS_ERR(i2c->pdmabase))
- 		return PTR_ERR(i2c->pdmabase);
- 
diff --git a/target/linux/mediatek/patches-5.15/853-v6.3-i2c-mt65xx-drop-of_match_ptr-for-ID-table.patch b/target/linux/mediatek/patches-5.15/853-v6.3-i2c-mt65xx-drop-of_match_ptr-for-ID-table.patch
deleted file mode 100644
index d000d535226f42..00000000000000
--- a/target/linux/mediatek/patches-5.15/853-v6.3-i2c-mt65xx-drop-of_match_ptr-for-ID-table.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From 8106fa2e0ae6082833fe1df97829c46c0183eaea Mon Sep 17 00:00:00 2001
-From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Date: Sat, 11 Mar 2023 12:16:54 +0100
-Subject: [PATCH 14/16] i2c: mt65xx: drop of_match_ptr for ID table
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The driver can match only via the DT table so the table should be always
-used and the of_match_ptr does not have any sense (this also allows ACPI
-matching via PRP0001, even though it might not be relevant here).
-
-  drivers/i2c/busses/i2c-mt65xx.c:514:34: error: ‘mtk_i2c_of_match’ defined but not used [-Werror=unused-const-variable=]
-
-Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Reviewed-by: Guenter Roeck <groeck@chromium.org>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/i2c-mt65xx.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -1546,7 +1546,7 @@ static struct platform_driver mtk_i2c_dr
- 	.driver = {
- 		.name = I2C_DRV_NAME,
- 		.pm = &mtk_i2c_pm,
--		.of_match_table = of_match_ptr(mtk_i2c_of_match),
-+		.of_match_table = mtk_i2c_of_match,
- 	},
- };
- 
diff --git a/target/linux/mediatek/patches-5.15/854-v6.4-i2c-mediatek-add-support-for-MT7981-SoC.patch b/target/linux/mediatek/patches-5.15/854-v6.4-i2c-mediatek-add-support-for-MT7981-SoC.patch
deleted file mode 100644
index e0973741e29d68..00000000000000
--- a/target/linux/mediatek/patches-5.15/854-v6.4-i2c-mediatek-add-support-for-MT7981-SoC.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From f69f3d662ba3bf999c36d9ac1e684540c4487bc3 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Mon, 10 Apr 2023 17:19:38 +0100
-Subject: [PATCH 15/16] i2c: mediatek: add support for MT7981 SoC
-
-Add support for the I2C units found in the MediaTek MT7981 and MT7988
-SoCs. Just like other recent MediaTek I2C units that also uses v3
-register offsets (which differ from v2 only by OFFSET_SLAVE_ADDR being
-0x94 instead of 0x4).
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/i2c-mt65xx.c | 13 +++++++++++++
- 1 file changed, 13 insertions(+)
-
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -431,6 +431,18 @@ static const struct mtk_i2c_compatible m
- 	.max_dma_support = 33,
- };
- 
-+static const struct mtk_i2c_compatible mt7981_compat = {
-+	.regs = mt_i2c_regs_v3,
-+	.pmic_i2c = 0,
-+	.dcm = 0,
-+	.auto_restart = 1,
-+	.aux_len_reg = 1,
-+	.timing_adjust = 1,
-+	.dma_sync = 1,
-+	.ltiming_adjust = 1,
-+	.max_dma_support = 33
-+};
-+
- static const struct mtk_i2c_compatible mt7986_compat = {
- 	.quirks = &mt7622_i2c_quirks,
- 	.regs = mt_i2c_regs_v1,
-@@ -516,6 +528,7 @@ static const struct of_device_id mtk_i2c
- 	{ .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat },
- 	{ .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat },
- 	{ .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat },
-+	{ .compatible = "mediatek,mt7981-i2c", .data = &mt7981_compat },
- 	{ .compatible = "mediatek,mt7986-i2c", .data = &mt7986_compat },
- 	{ .compatible = "mediatek,mt8168-i2c", .data = &mt8168_compat },
- 	{ .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
diff --git a/target/linux/mediatek/patches-5.15/855-i2c-mt65xx-allow-optional-pmic-clock.patch b/target/linux/mediatek/patches-5.15/855-i2c-mt65xx-allow-optional-pmic-clock.patch
deleted file mode 100644
index 69cc155d8d2307..00000000000000
--- a/target/linux/mediatek/patches-5.15/855-i2c-mt65xx-allow-optional-pmic-clock.patch
+++ /dev/null
@@ -1,45 +0,0 @@
-From 3bf827929a44c17bfb1bf1000b143c02ce26a929 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Sat, 26 Aug 2023 21:56:51 +0100
-Subject: [PATCH] i2c: mt65xx: allow optional pmic clock
-
-Using the I2C host controller on the MT7981 SoC requires 4 clocks to
-be enabled. One of them, the pmic clk, is only enabled in case
-'mediatek,have-pmic' is also set which has other consequences which
-are not desired in this case.
-
-Allow defining a pmic clk even in case the 'mediatek,have-pmic' propterty
-is not present and the bus is not used to connect to a pmic, but may
-still require to enable the pmic clock.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/i2c/busses/i2c-mt65xx.c | 12 ++++++++----
- 1 file changed, 8 insertions(+), 4 deletions(-)
-
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -1444,15 +1444,19 @@ static int mtk_i2c_probe(struct platform
- 	if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk))
- 		return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk);
- 
-+	i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = devm_clk_get_optional(&pdev->dev, "pmic");
-+	if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk)) {
-+		dev_err(&pdev->dev, "cannot get pmic clock\n");
-+		return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk);
-+	}
-+
- 	if (i2c->have_pmic) {
--		i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = devm_clk_get(&pdev->dev, "pmic");
--		if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk)) {
-+		if (!i2c->clocks[I2C_MT65XX_CLK_PMIC].clk) {
- 			dev_err(&pdev->dev, "cannot get pmic clock\n");
--			return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk);
-+			return -ENODEV;
- 		}
- 		speed_clk = I2C_MT65XX_CLK_PMIC;
- 	} else {
--		i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = NULL;
- 		speed_clk = I2C_MT65XX_CLK_MAIN;
- 	}
- 
diff --git a/target/linux/mediatek/patches-5.15/860-v6.6-01-ASoC-mediatek-mt7986-add-common-header.patch b/target/linux/mediatek/patches-5.15/860-v6.6-01-ASoC-mediatek-mt7986-add-common-header.patch
deleted file mode 100644
index 9607eec821082b..00000000000000
--- a/target/linux/mediatek/patches-5.15/860-v6.6-01-ASoC-mediatek-mt7986-add-common-header.patch
+++ /dev/null
@@ -1,269 +0,0 @@
-From d35469096915f2551ed1d26da1ab12ff500fc963 Mon Sep 17 00:00:00 2001
-From: Maso Huang <maso.huang@mediatek.com>
-Date: Thu, 17 Aug 2023 18:13:33 +0800
-Subject: [PATCH 1/9] ASoC: mediatek: mt7986: add common header
-
-Add header files for register definition and structure.
-
-Signed-off-by: Maso Huang <maso.huang@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20230817101338.18782-2-maso.huang@mediatek.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- sound/soc/mediatek/mt7986/mt7986-afe-common.h |  49 +++++
- sound/soc/mediatek/mt7986/mt7986-reg.h        | 196 ++++++++++++++++++
- 2 files changed, 245 insertions(+)
- create mode 100644 sound/soc/mediatek/mt7986/mt7986-afe-common.h
- create mode 100644 sound/soc/mediatek/mt7986/mt7986-reg.h
-
---- /dev/null
-+++ b/sound/soc/mediatek/mt7986/mt7986-afe-common.h
-@@ -0,0 +1,49 @@
-+/* SPDX-License-Identifier: GPL-2.0 */
-+/*
-+ * mt7986-afe-common.h  --  MediaTek 7986 audio driver definitions
-+ *
-+ * Copyright (c) 2023 MediaTek Inc.
-+ * Authors: Vic Wu <vic.wu@mediatek.com>
-+ *          Maso Huang <maso.huang@mediatek.com>
-+ */
-+
-+#ifndef _MT_7986_AFE_COMMON_H_
-+#define _MT_7986_AFE_COMMON_H_
-+
-+#include <sound/soc.h>
-+#include <linux/clk.h>
-+#include <linux/list.h>
-+#include <linux/regmap.h>
-+#include "../common/mtk-base-afe.h"
-+
-+enum {
-+	MT7986_MEMIF_DL1,
-+	MT7986_MEMIF_VUL12,
-+	MT7986_MEMIF_NUM,
-+	MT7986_DAI_ETDM = MT7986_MEMIF_NUM,
-+	MT7986_DAI_NUM,
-+};
-+
-+enum {
-+	MT7986_IRQ_0,
-+	MT7986_IRQ_1,
-+	MT7986_IRQ_2,
-+	MT7986_IRQ_NUM,
-+};
-+
-+struct mt7986_afe_private {
-+	struct clk_bulk_data *clks;
-+	int num_clks;
-+
-+	int pm_runtime_bypass_reg_ctl;
-+
-+	/* dai */
-+	void *dai_priv[MT7986_DAI_NUM];
-+};
-+
-+unsigned int mt7986_afe_rate_transform(struct device *dev,
-+				       unsigned int rate);
-+
-+/* dai register */
-+int mt7986_dai_etdm_register(struct mtk_base_afe *afe);
-+#endif
---- /dev/null
-+++ b/sound/soc/mediatek/mt7986/mt7986-reg.h
-@@ -0,0 +1,196 @@
-+/* SPDX-License-Identifier: GPL-2.0 */
-+/*
-+ * mt7986-reg.h  --  MediaTek 7986 audio driver reg definition
-+ *
-+ * Copyright (c) 2023 MediaTek Inc.
-+ * Authors: Vic Wu <vic.wu@mediatek.com>
-+ *          Maso Huang <maso.huang@mediatek.com>
-+ */
-+
-+#ifndef _MT7986_REG_H_
-+#define _MT7986_REG_H_
-+
-+#define AUDIO_TOP_CON2                  0x0008
-+#define AUDIO_TOP_CON4                  0x0010
-+#define AUDIO_ENGEN_CON0                0x0014
-+#define AFE_IRQ_MCU_EN                  0x0100
-+#define AFE_IRQ_MCU_STATUS              0x0120
-+#define AFE_IRQ_MCU_CLR                 0x0128
-+#define AFE_IRQ0_MCU_CFG0               0x0140
-+#define AFE_IRQ0_MCU_CFG1               0x0144
-+#define AFE_IRQ1_MCU_CFG0               0x0148
-+#define AFE_IRQ1_MCU_CFG1               0x014c
-+#define AFE_IRQ2_MCU_CFG0               0x0150
-+#define AFE_IRQ2_MCU_CFG1               0x0154
-+#define ETDM_IN5_CON0                   0x13f0
-+#define ETDM_IN5_CON1                   0x13f4
-+#define ETDM_IN5_CON2                   0x13f8
-+#define ETDM_IN5_CON3                   0x13fc
-+#define ETDM_IN5_CON4                   0x1400
-+#define ETDM_OUT5_CON0                  0x1570
-+#define ETDM_OUT5_CON4                  0x1580
-+#define ETDM_OUT5_CON5                  0x1584
-+#define ETDM_4_7_COWORK_CON0            0x15e0
-+#define ETDM_4_7_COWORK_CON1            0x15e4
-+#define AFE_CONN018_1                   0x1b44
-+#define AFE_CONN018_4                   0x1b50
-+#define AFE_CONN019_1                   0x1b64
-+#define AFE_CONN019_4                   0x1b70
-+#define AFE_CONN124_1                   0x2884
-+#define AFE_CONN124_4                   0x2890
-+#define AFE_CONN125_1                   0x28a4
-+#define AFE_CONN125_4                   0x28b0
-+#define AFE_CONN_RS_0                   0x3920
-+#define AFE_CONN_RS_3                   0x392c
-+#define AFE_CONN_16BIT_0                0x3960
-+#define AFE_CONN_16BIT_3                0x396c
-+#define AFE_CONN_24BIT_0                0x3980
-+#define AFE_CONN_24BIT_3                0x398c
-+#define AFE_MEMIF_CON0                  0x3d98
-+#define AFE_MEMIF_RD_MON                0x3da0
-+#define AFE_MEMIF_WR_MON                0x3da4
-+#define AFE_DL0_BASE_MSB                0x3e40
-+#define AFE_DL0_BASE                    0x3e44
-+#define AFE_DL0_CUR_MSB                 0x3e48
-+#define AFE_DL0_CUR                     0x3e4c
-+#define AFE_DL0_END_MSB                 0x3e50
-+#define AFE_DL0_END                     0x3e54
-+#define AFE_DL0_RCH_MON                 0x3e58
-+#define AFE_DL0_LCH_MON                 0x3e5c
-+#define AFE_DL0_CON0                    0x3e60
-+#define AFE_VUL0_BASE_MSB               0x4220
-+#define AFE_VUL0_BASE                   0x4224
-+#define AFE_VUL0_CUR_MSB                0x4228
-+#define AFE_VUL0_CUR                    0x422c
-+#define AFE_VUL0_END_MSB                0x4230
-+#define AFE_VUL0_END                    0x4234
-+#define AFE_VUL0_CON0                   0x4238
-+
-+#define AFE_MAX_REGISTER AFE_VUL0_CON0
-+#define AFE_IRQ_STATUS_BITS             0x7
-+#define AFE_IRQ_CNT_SHIFT               0
-+#define AFE_IRQ_CNT_MASK	        0xffffff
-+
-+/* AUDIO_TOP_CON2 */
-+#define CLK_OUT5_PDN                    BIT(14)
-+#define CLK_OUT5_PDN_MASK               BIT(14)
-+#define CLK_IN5_PDN                     BIT(7)
-+#define CLK_IN5_PDN_MASK                BIT(7)
-+
-+/* AUDIO_TOP_CON4 */
-+#define PDN_APLL_TUNER2                 BIT(12)
-+#define PDN_APLL_TUNER2_MASK            BIT(12)
-+
-+/* AUDIO_ENGEN_CON0 */
-+#define AUD_APLL2_EN                    BIT(3)
-+#define AUD_APLL2_EN_MASK               BIT(3)
-+#define AUD_26M_EN                      BIT(0)
-+#define AUD_26M_EN_MASK                 BIT(0)
-+
-+/* AFE_DL0_CON0 */
-+#define DL0_ON_SFT                      28
-+#define DL0_ON_MASK                     0x1
-+#define DL0_ON_MASK_SFT                 BIT(28)
-+#define DL0_MINLEN_SFT                  20
-+#define DL0_MINLEN_MASK                 0xf
-+#define DL0_MINLEN_MASK_SFT             (0xf << 20)
-+#define DL0_MODE_SFT                    8
-+#define DL0_MODE_MASK                   0x1f
-+#define DL0_MODE_MASK_SFT               (0x1f << 8)
-+#define DL0_PBUF_SIZE_SFT               5
-+#define DL0_PBUF_SIZE_MASK              0x3
-+#define DL0_PBUF_SIZE_MASK_SFT          (0x3 << 5)
-+#define DL0_MONO_SFT                    4
-+#define DL0_MONO_MASK                   0x1
-+#define DL0_MONO_MASK_SFT               BIT(4)
-+#define DL0_HALIGN_SFT                  2
-+#define DL0_HALIGN_MASK                 0x1
-+#define DL0_HALIGN_MASK_SFT             BIT(2)
-+#define DL0_HD_MODE_SFT                 0
-+#define DL0_HD_MODE_MASK                0x3
-+#define DL0_HD_MODE_MASK_SFT            (0x3 << 0)
-+
-+/* AFE_VUL0_CON0 */
-+#define VUL0_ON_SFT                     28
-+#define VUL0_ON_MASK                    0x1
-+#define VUL0_ON_MASK_SFT                BIT(28)
-+#define VUL0_MODE_SFT                   8
-+#define VUL0_MODE_MASK                  0x1f
-+#define VUL0_MODE_MASK_SFT              (0x1f << 8)
-+#define VUL0_MONO_SFT                   4
-+#define VUL0_MONO_MASK                  0x1
-+#define VUL0_MONO_MASK_SFT              BIT(4)
-+#define VUL0_HALIGN_SFT                 2
-+#define VUL0_HALIGN_MASK                0x1
-+#define VUL0_HALIGN_MASK_SFT            BIT(2)
-+#define VUL0_HD_MODE_SFT                0
-+#define VUL0_HD_MODE_MASK               0x3
-+#define VUL0_HD_MODE_MASK_SFT           (0x3 << 0)
-+
-+/* AFE_IRQ_MCU_CON */
-+#define IRQ_MCU_MODE_SFT                4
-+#define IRQ_MCU_MODE_MASK               0x1f
-+#define IRQ_MCU_MODE_MASK_SFT           (0x1f << 4)
-+#define IRQ_MCU_ON_SFT                  0
-+#define IRQ_MCU_ON_MASK                 0x1
-+#define IRQ_MCU_ON_MASK_SFT             BIT(0)
-+#define IRQ0_MCU_CLR_SFT                0
-+#define IRQ0_MCU_CLR_MASK               0x1
-+#define IRQ0_MCU_CLR_MASK_SFT           BIT(0)
-+#define IRQ1_MCU_CLR_SFT                1
-+#define IRQ1_MCU_CLR_MASK               0x1
-+#define IRQ1_MCU_CLR_MASK_SFT           BIT(1)
-+#define IRQ2_MCU_CLR_SFT                2
-+#define IRQ2_MCU_CLR_MASK               0x1
-+#define IRQ2_MCU_CLR_MASK_SFT           BIT(2)
-+
-+/* ETDM_IN5_CON2 */
-+#define IN_CLK_SRC(x)                   ((x) << 10)
-+#define IN_CLK_SRC_SFT                  10
-+#define IN_CLK_SRC_MASK                 GENMASK(12, 10)
-+
-+/* ETDM_IN5_CON3 */
-+#define IN_SEL_FS(x)                    ((x) << 26)
-+#define IN_SEL_FS_SFT                   26
-+#define IN_SEL_FS_MASK                  GENMASK(30, 26)
-+
-+/* ETDM_IN5_CON4 */
-+#define IN_RELATCH(x)                   ((x) << 20)
-+#define IN_RELATCH_SFT                  20
-+#define IN_RELATCH_MASK                 GENMASK(24, 20)
-+#define IN_CLK_INV                      BIT(18)
-+#define IN_CLK_INV_MASK                 BIT(18)
-+
-+/* ETDM_IN5_CON0 & ETDM_OUT5_CON0 */
-+#define RELATCH_SRC_MASK                GENMASK(30, 28)
-+#define ETDM_CH_NUM_MASK                GENMASK(27, 23)
-+#define ETDM_WRD_LEN_MASK               GENMASK(20, 16)
-+#define ETDM_BIT_LEN_MASK               GENMASK(15, 11)
-+#define ETDM_FMT_MASK                   GENMASK(8, 6)
-+#define ETDM_SYNC                       BIT(1)
-+#define ETDM_SYNC_MASK                  BIT(1)
-+#define ETDM_EN                         BIT(0)
-+#define ETDM_EN_MASK                    BIT(0)
-+
-+/* ETDM_OUT5_CON4 */
-+#define OUT_RELATCH(x)                  ((x) << 24)
-+#define OUT_RELATCH_SFT                 24
-+#define OUT_RELATCH_MASK                GENMASK(28, 24)
-+#define OUT_CLK_SRC(x)                  ((x) << 6)
-+#define OUT_CLK_SRC_SFT                 6
-+#define OUT_CLK_SRC_MASK                GENMASK(8, 6)
-+#define OUT_SEL_FS(x)                   (x)
-+#define OUT_SEL_FS_SFT                  0
-+#define OUT_SEL_FS_MASK                 GENMASK(4, 0)
-+
-+/* ETDM_OUT5_CON5 */
-+#define ETDM_CLK_DIV                    BIT(12)
-+#define ETDM_CLK_DIV_MASK               BIT(12)
-+#define OUT_CLK_INV                     BIT(9)
-+#define OUT_CLK_INV_MASK                BIT(9)
-+
-+/* ETDM_4_7_COWORK_CON0 */
-+#define OUT_SEL(x)                      ((x) << 12)
-+#define OUT_SEL_SFT                     12
-+#define OUT_SEL_MASK                    GENMASK(15, 12)
-+#endif
diff --git a/target/linux/mediatek/patches-5.15/860-v6.6-02-ASoC-mediatek-mt7986-support-etdm-in-platform-driver.patch b/target/linux/mediatek/patches-5.15/860-v6.6-02-ASoC-mediatek-mt7986-support-etdm-in-platform-driver.patch
deleted file mode 100644
index f22add580fe012..00000000000000
--- a/target/linux/mediatek/patches-5.15/860-v6.6-02-ASoC-mediatek-mt7986-support-etdm-in-platform-driver.patch
+++ /dev/null
@@ -1,430 +0,0 @@
-From 948a288897015fb3ee63b3f720b396b590c17fd7 Mon Sep 17 00:00:00 2001
-From: Maso Huang <maso.huang@mediatek.com>
-Date: Thu, 17 Aug 2023 18:13:34 +0800
-Subject: [PATCH 2/9] ASoC: mediatek: mt7986: support etdm in platform driver
-
-Add mt7986 etdm dai driver support.
-
-Signed-off-by: Maso Huang <maso.huang@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20230817101338.18782-3-maso.huang@mediatek.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- sound/soc/mediatek/mt7986/mt7986-dai-etdm.c | 411 ++++++++++++++++++++
- 1 file changed, 411 insertions(+)
- create mode 100644 sound/soc/mediatek/mt7986/mt7986-dai-etdm.c
-
---- /dev/null
-+++ b/sound/soc/mediatek/mt7986/mt7986-dai-etdm.c
-@@ -0,0 +1,411 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * MediaTek ALSA SoC Audio DAI eTDM Control
-+ *
-+ * Copyright (c) 2023 MediaTek Inc.
-+ * Authors: Vic Wu <vic.wu@mediatek.com>
-+ *          Maso Huang <maso.huang@mediatek.com>
-+ */
-+
-+#include <linux/bitfield.h>
-+#include <linux/bitops.h>
-+#include <linux/regmap.h>
-+#include <sound/pcm_params.h>
-+#include "mt7986-afe-common.h"
-+#include "mt7986-reg.h"
-+
-+#define HOPPING_CLK  0
-+#define APLL_CLK     1
-+#define MTK_DAI_ETDM_FORMAT_I2S   0
-+#define MTK_DAI_ETDM_FORMAT_DSPA  4
-+#define MTK_DAI_ETDM_FORMAT_DSPB  5
-+
-+enum {
-+	MTK_ETDM_RATE_8K = 0,
-+	MTK_ETDM_RATE_12K = 1,
-+	MTK_ETDM_RATE_16K = 2,
-+	MTK_ETDM_RATE_24K = 3,
-+	MTK_ETDM_RATE_32K = 4,
-+	MTK_ETDM_RATE_48K = 5,
-+	MTK_ETDM_RATE_96K = 7,
-+	MTK_ETDM_RATE_192K = 9,
-+	MTK_ETDM_RATE_11K = 16,
-+	MTK_ETDM_RATE_22K = 17,
-+	MTK_ETDM_RATE_44K = 18,
-+	MTK_ETDM_RATE_88K = 19,
-+	MTK_ETDM_RATE_176K = 20,
-+};
-+
-+struct mtk_dai_etdm_priv {
-+	bool bck_inv;
-+	bool lrck_inv;
-+	bool slave_mode;
-+	unsigned int format;
-+};
-+
-+static unsigned int mt7986_etdm_rate_transform(struct device *dev, unsigned int rate)
-+{
-+	switch (rate) {
-+	case 8000:
-+		return MTK_ETDM_RATE_8K;
-+	case 11025:
-+		return MTK_ETDM_RATE_11K;
-+	case 12000:
-+		return MTK_ETDM_RATE_12K;
-+	case 16000:
-+		return MTK_ETDM_RATE_16K;
-+	case 22050:
-+		return MTK_ETDM_RATE_22K;
-+	case 24000:
-+		return MTK_ETDM_RATE_24K;
-+	case 32000:
-+		return MTK_ETDM_RATE_32K;
-+	case 44100:
-+		return MTK_ETDM_RATE_44K;
-+	case 48000:
-+		return MTK_ETDM_RATE_48K;
-+	case 88200:
-+		return MTK_ETDM_RATE_88K;
-+	case 96000:
-+		return MTK_ETDM_RATE_96K;
-+	case 176400:
-+		return MTK_ETDM_RATE_176K;
-+	case 192000:
-+		return MTK_ETDM_RATE_192K;
-+	default:
-+		dev_warn(dev, "%s(), rate %u invalid, using %d!!!\n",
-+			 __func__, rate, MTK_ETDM_RATE_48K);
-+		return MTK_ETDM_RATE_48K;
-+	}
-+}
-+
-+static int get_etdm_wlen(unsigned int bitwidth)
-+{
-+	return bitwidth <= 16 ? 16 : 32;
-+}
-+
-+/* dai component */
-+/* interconnection */
-+
-+static const struct snd_kcontrol_new o124_mix[] = {
-+	SOC_DAPM_SINGLE_AUTODISABLE("I032_Switch", AFE_CONN124_1, 0, 1, 0),
-+};
-+
-+static const struct snd_kcontrol_new o125_mix[] = {
-+	SOC_DAPM_SINGLE_AUTODISABLE("I033_Switch", AFE_CONN125_1, 1, 1, 0),
-+};
-+
-+static const struct snd_soc_dapm_widget mtk_dai_etdm_widgets[] = {
-+
-+	/* DL */
-+	SND_SOC_DAPM_MIXER("I150", SND_SOC_NOPM, 0, 0, NULL, 0),
-+	SND_SOC_DAPM_MIXER("I151", SND_SOC_NOPM, 0, 0, NULL, 0),
-+	/* UL */
-+	SND_SOC_DAPM_MIXER("O124", SND_SOC_NOPM, 0, 0, o124_mix, ARRAY_SIZE(o124_mix)),
-+	SND_SOC_DAPM_MIXER("O125", SND_SOC_NOPM, 0, 0, o125_mix, ARRAY_SIZE(o125_mix)),
-+};
-+
-+static const struct snd_soc_dapm_route mtk_dai_etdm_routes[] = {
-+	{"I150", NULL, "ETDM Capture"},
-+	{"I151", NULL, "ETDM Capture"},
-+	{"ETDM Playback", NULL, "O124"},
-+	{"ETDM Playback", NULL, "O125"},
-+	{"O124", "I032_Switch", "I032"},
-+	{"O125", "I033_Switch", "I033"},
-+};
-+
-+/* dai ops */
-+static int mtk_dai_etdm_startup(struct snd_pcm_substream *substream,
-+				struct snd_soc_dai *dai)
-+{
-+	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
-+	struct mt7986_afe_private *afe_priv = afe->platform_priv;
-+	int ret;
-+
-+	ret = clk_bulk_prepare_enable(afe_priv->num_clks, afe_priv->clks);
-+	if (ret)
-+		return dev_err_probe(afe->dev, ret, "Failed to enable clocks\n");
-+
-+	regmap_update_bits(afe->regmap, AUDIO_TOP_CON2, CLK_OUT5_PDN_MASK, 0);
-+	regmap_update_bits(afe->regmap, AUDIO_TOP_CON2, CLK_IN5_PDN_MASK, 0);
-+
-+	return 0;
-+}
-+
-+static void mtk_dai_etdm_shutdown(struct snd_pcm_substream *substream,
-+				  struct snd_soc_dai *dai)
-+{
-+	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
-+	struct mt7986_afe_private *afe_priv = afe->platform_priv;
-+
-+	regmap_update_bits(afe->regmap, AUDIO_TOP_CON2, CLK_OUT5_PDN_MASK,
-+			   CLK_OUT5_PDN);
-+	regmap_update_bits(afe->regmap, AUDIO_TOP_CON2, CLK_IN5_PDN_MASK,
-+			   CLK_IN5_PDN);
-+
-+	clk_bulk_disable_unprepare(afe_priv->num_clks, afe_priv->clks);
-+}
-+
-+static unsigned int get_etdm_ch_fixup(unsigned int channels)
-+{
-+	if (channels > 16)
-+		return 24;
-+	else if (channels > 8)
-+		return 16;
-+	else if (channels > 4)
-+		return 8;
-+	else if (channels > 2)
-+		return 4;
-+	else
-+		return 2;
-+}
-+
-+static int mtk_dai_etdm_config(struct mtk_base_afe *afe,
-+			       struct snd_pcm_hw_params *params,
-+			       struct snd_soc_dai *dai,
-+			       int stream)
-+{
-+	struct mt7986_afe_private *afe_priv = afe->platform_priv;
-+	struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai->id];
-+	unsigned int rate = params_rate(params);
-+	unsigned int etdm_rate = mt7986_etdm_rate_transform(afe->dev, rate);
-+	unsigned int afe_rate = mt7986_afe_rate_transform(afe->dev, rate);
-+	unsigned int channels = params_channels(params);
-+	unsigned int bit_width = params_width(params);
-+	unsigned int wlen = get_etdm_wlen(bit_width);
-+	unsigned int val = 0;
-+	unsigned int mask = 0;
-+
-+	dev_dbg(afe->dev, "%s(), stream %d, rate %u, bitwidth %u\n",
-+		 __func__, stream, rate, bit_width);
-+
-+	/* CON0 */
-+	mask |= ETDM_BIT_LEN_MASK;
-+	val |= FIELD_PREP(ETDM_BIT_LEN_MASK, bit_width - 1);
-+	mask |= ETDM_WRD_LEN_MASK;
-+	val |= FIELD_PREP(ETDM_WRD_LEN_MASK, wlen - 1);
-+	mask |= ETDM_FMT_MASK;
-+	val |= FIELD_PREP(ETDM_FMT_MASK, etdm_data->format);
-+	mask |= ETDM_CH_NUM_MASK;
-+	val |= FIELD_PREP(ETDM_CH_NUM_MASK, get_etdm_ch_fixup(channels) - 1);
-+	mask |= RELATCH_SRC_MASK;
-+	val |= FIELD_PREP(RELATCH_SRC_MASK, APLL_CLK);
-+
-+	switch (stream) {
-+	case SNDRV_PCM_STREAM_PLAYBACK:
-+		/* set ETDM_OUT5_CON0 */
-+		regmap_update_bits(afe->regmap, ETDM_OUT5_CON0, mask, val);
-+
-+		/* set ETDM_OUT5_CON4 */
-+		regmap_update_bits(afe->regmap, ETDM_OUT5_CON4,
-+				   OUT_RELATCH_MASK, OUT_RELATCH(afe_rate));
-+		regmap_update_bits(afe->regmap, ETDM_OUT5_CON4,
-+				   OUT_CLK_SRC_MASK, OUT_CLK_SRC(APLL_CLK));
-+		regmap_update_bits(afe->regmap, ETDM_OUT5_CON4,
-+				   OUT_SEL_FS_MASK, OUT_SEL_FS(etdm_rate));
-+
-+		/* set ETDM_OUT5_CON5 */
-+		regmap_update_bits(afe->regmap, ETDM_OUT5_CON5,
-+				   ETDM_CLK_DIV_MASK, ETDM_CLK_DIV);
-+		break;
-+	case SNDRV_PCM_STREAM_CAPTURE:
-+		/* set ETDM_IN5_CON0 */
-+		regmap_update_bits(afe->regmap, ETDM_IN5_CON0, mask, val);
-+		regmap_update_bits(afe->regmap, ETDM_IN5_CON0,
-+				   ETDM_SYNC_MASK, ETDM_SYNC);
-+
-+		/* set ETDM_IN5_CON2 */
-+		regmap_update_bits(afe->regmap, ETDM_IN5_CON2,
-+				   IN_CLK_SRC_MASK, IN_CLK_SRC(APLL_CLK));
-+
-+		/* set ETDM_IN5_CON3 */
-+		regmap_update_bits(afe->regmap, ETDM_IN5_CON3,
-+				   IN_SEL_FS_MASK, IN_SEL_FS(etdm_rate));
-+
-+		/* set ETDM_IN5_CON4 */
-+		regmap_update_bits(afe->regmap, ETDM_IN5_CON4,
-+				   IN_RELATCH_MASK, IN_RELATCH(afe_rate));
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	return 0;
-+}
-+
-+static int mtk_dai_etdm_hw_params(struct snd_pcm_substream *substream,
-+				  struct snd_pcm_hw_params *params,
-+				  struct snd_soc_dai *dai)
-+{
-+	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
-+
-+	mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_PLAYBACK);
-+	mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_CAPTURE);
-+
-+	return 0;
-+}
-+
-+static int mtk_dai_etdm_trigger(struct snd_pcm_substream *substream, int cmd,
-+				struct snd_soc_dai *dai)
-+{
-+	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
-+
-+	dev_dbg(afe->dev, "%s(), cmd %d, dai id %d\n", __func__, cmd, dai->id);
-+	switch (cmd) {
-+	case SNDRV_PCM_TRIGGER_START:
-+	case SNDRV_PCM_TRIGGER_RESUME:
-+		regmap_update_bits(afe->regmap, ETDM_IN5_CON0, ETDM_EN_MASK,
-+				   ETDM_EN);
-+		regmap_update_bits(afe->regmap, ETDM_OUT5_CON0, ETDM_EN_MASK,
-+				   ETDM_EN);
-+		break;
-+	case SNDRV_PCM_TRIGGER_STOP:
-+	case SNDRV_PCM_TRIGGER_SUSPEND:
-+		regmap_update_bits(afe->regmap, ETDM_IN5_CON0, ETDM_EN_MASK,
-+				   0);
-+		regmap_update_bits(afe->regmap, ETDM_OUT5_CON0, ETDM_EN_MASK,
-+				   0);
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	return 0;
-+}
-+
-+static int mtk_dai_etdm_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
-+{
-+	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
-+	struct mt7986_afe_private *afe_priv = afe->platform_priv;
-+	struct mtk_dai_etdm_priv *etdm_data;
-+	void *priv_data;
-+
-+	switch (dai->id) {
-+	case MT7986_DAI_ETDM:
-+		break;
-+	default:
-+		dev_warn(afe->dev, "%s(), id %d not support\n",
-+			 __func__, dai->id);
-+		return -EINVAL;
-+	}
-+
-+	priv_data = devm_kzalloc(afe->dev, sizeof(struct mtk_dai_etdm_priv),
-+				 GFP_KERNEL);
-+	if (!priv_data)
-+		return -ENOMEM;
-+
-+	afe_priv->dai_priv[dai->id] = priv_data;
-+	etdm_data = afe_priv->dai_priv[dai->id];
-+
-+	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
-+	case SND_SOC_DAIFMT_I2S:
-+		etdm_data->format = MTK_DAI_ETDM_FORMAT_I2S;
-+		break;
-+	case SND_SOC_DAIFMT_DSP_A:
-+		etdm_data->format = MTK_DAI_ETDM_FORMAT_DSPA;
-+		break;
-+	case SND_SOC_DAIFMT_DSP_B:
-+		etdm_data->format = MTK_DAI_ETDM_FORMAT_DSPB;
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
-+	case SND_SOC_DAIFMT_NB_NF:
-+		etdm_data->bck_inv = false;
-+		etdm_data->lrck_inv = false;
-+		break;
-+	case SND_SOC_DAIFMT_NB_IF:
-+		etdm_data->bck_inv = false;
-+		etdm_data->lrck_inv = true;
-+		break;
-+	case SND_SOC_DAIFMT_IB_NF:
-+		etdm_data->bck_inv = true;
-+		etdm_data->lrck_inv = false;
-+		break;
-+	case SND_SOC_DAIFMT_IB_IF:
-+		etdm_data->bck_inv = true;
-+		etdm_data->lrck_inv = true;
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
-+	case SND_SOC_DAIFMT_CBM_CFM:
-+		etdm_data->slave_mode = true;
-+		break;
-+	case SND_SOC_DAIFMT_CBS_CFS:
-+		etdm_data->slave_mode = false;
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+
-+static const struct snd_soc_dai_ops mtk_dai_etdm_ops = {
-+	.startup = mtk_dai_etdm_startup,
-+	.shutdown = mtk_dai_etdm_shutdown,
-+	.hw_params = mtk_dai_etdm_hw_params,
-+	.trigger = mtk_dai_etdm_trigger,
-+	.set_fmt = mtk_dai_etdm_set_fmt,
-+};
-+
-+/* dai driver */
-+#define MTK_ETDM_RATES (SNDRV_PCM_RATE_8000_48000 |\
-+			SNDRV_PCM_RATE_88200 |\
-+			SNDRV_PCM_RATE_96000 |\
-+			SNDRV_PCM_RATE_176400 |\
-+			SNDRV_PCM_RATE_192000)
-+
-+#define MTK_ETDM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
-+			  SNDRV_PCM_FMTBIT_S24_LE |\
-+			  SNDRV_PCM_FMTBIT_S32_LE)
-+
-+static struct snd_soc_dai_driver mtk_dai_etdm_driver[] = {
-+	{
-+		.name = "ETDM",
-+		.id = MT7986_DAI_ETDM,
-+		.capture = {
-+			.stream_name = "ETDM Capture",
-+			.channels_min = 1,
-+			.channels_max = 2,
-+			.rates = MTK_ETDM_RATES,
-+			.formats = MTK_ETDM_FORMATS,
-+		},
-+		.playback = {
-+			.stream_name = "ETDM Playback",
-+			.channels_min = 1,
-+			.channels_max = 2,
-+			.rates = MTK_ETDM_RATES,
-+			.formats = MTK_ETDM_FORMATS,
-+		},
-+		.ops = &mtk_dai_etdm_ops,
-+		.symmetric_rate = 1,
-+		.symmetric_sample_bits = 1,
-+	},
-+};
-+
-+int mt7986_dai_etdm_register(struct mtk_base_afe *afe)
-+{
-+	struct mtk_base_afe_dai *dai;
-+
-+	dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
-+	if (!dai)
-+		return -ENOMEM;
-+
-+	list_add(&dai->list, &afe->sub_dais);
-+
-+	dai->dai_drivers = mtk_dai_etdm_driver;
-+	dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_etdm_driver);
-+
-+	dai->dapm_widgets = mtk_dai_etdm_widgets;
-+	dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_etdm_widgets);
-+	dai->dapm_routes = mtk_dai_etdm_routes;
-+	dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_etdm_routes);
-+
-+	return 0;
-+}
diff --git a/target/linux/mediatek/patches-5.15/860-v6.6-03-ASoC-mediatek-mt7986-add-platform-driver.patch b/target/linux/mediatek/patches-5.15/860-v6.6-03-ASoC-mediatek-mt7986-add-platform-driver.patch
deleted file mode 100644
index 8139fdc66832c5..00000000000000
--- a/target/linux/mediatek/patches-5.15/860-v6.6-03-ASoC-mediatek-mt7986-add-platform-driver.patch
+++ /dev/null
@@ -1,685 +0,0 @@
-From fc7776dee86bc07d22820a904760a95f49a2f12e Mon Sep 17 00:00:00 2001
-From: Maso Huang <maso.huang@mediatek.com>
-Date: Thu, 17 Aug 2023 18:13:35 +0800
-Subject: [PATCH 3/9] ASoC: mediatek: mt7986: add platform driver
-
-Add mt7986 platform driver.
-
-Signed-off-by: Maso Huang <maso.huang@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20230817101338.18782-4-maso.huang@mediatek.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- sound/soc/mediatek/Kconfig                 |  10 +
- sound/soc/mediatek/Makefile                |   1 +
- sound/soc/mediatek/mt7986/Makefile         |   8 +
- sound/soc/mediatek/mt7986/mt7986-afe-pcm.c | 622 +++++++++++++++++++++
- 4 files changed, 641 insertions(+)
- create mode 100644 sound/soc/mediatek/mt7986/Makefile
- create mode 100644 sound/soc/mediatek/mt7986/mt7986-afe-pcm.c
-
---- a/sound/soc/mediatek/Kconfig
-+++ b/sound/soc/mediatek/Kconfig
-@@ -54,6 +54,16 @@ config SND_SOC_MT6797_MT6351
- 	  Select Y if you have such device.
- 	  If unsure select "N".
- 
-+config SND_SOC_MT7986
-+	tristate "ASoC support for Mediatek MT7986 chip"
-+	depends on ARCH_MEDIATEK
-+	select SND_SOC_MEDIATEK
-+	help
-+	  This adds ASoC platform driver support for MediaTek MT7986 chip
-+	  that can be used with other codecs.
-+	  Select Y if you have such device.
-+	  If unsure select "N".
-+
- config SND_SOC_MT8173
- 	tristate "ASoC support for Mediatek MT8173 chip"
- 	depends on ARCH_MEDIATEK
---- a/sound/soc/mediatek/Makefile
-+++ b/sound/soc/mediatek/Makefile
-@@ -2,6 +2,7 @@
- obj-$(CONFIG_SND_SOC_MEDIATEK) += common/
- obj-$(CONFIG_SND_SOC_MT2701) += mt2701/
- obj-$(CONFIG_SND_SOC_MT6797) += mt6797/
-+obj-$(CONFIG_SND_SOC_MT7986) += mt7986/
- obj-$(CONFIG_SND_SOC_MT8173) += mt8173/
- obj-$(CONFIG_SND_SOC_MT8183) += mt8183/
- obj-$(CONFIG_SND_SOC_MT8192) += mt8192/
---- /dev/null
-+++ b/sound/soc/mediatek/mt7986/Makefile
-@@ -0,0 +1,8 @@
-+# SPDX-License-Identifier: GPL-2.0
-+
-+# platform driver
-+snd-soc-mt7986-afe-objs := \
-+	mt7986-afe-pcm.o \
-+	mt7986-dai-etdm.o
-+
-+obj-$(CONFIG_SND_SOC_MT7986) += snd-soc-mt7986-afe.o
---- /dev/null
-+++ b/sound/soc/mediatek/mt7986/mt7986-afe-pcm.c
-@@ -0,0 +1,622 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * MediaTek ALSA SoC AFE platform driver for MT7986
-+ *
-+ * Copyright (c) 2023 MediaTek Inc.
-+ * Authors: Vic Wu <vic.wu@mediatek.com>
-+ *          Maso Huang <maso.huang@mediatek.com>
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/delay.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/of_address.h>
-+#include <linux/pm_runtime.h>
-+
-+#include "mt7986-afe-common.h"
-+#include "mt7986-reg.h"
-+#include "../common/mtk-afe-platform-driver.h"
-+#include "../common/mtk-afe-fe-dai.h"
-+
-+enum {
-+	MTK_AFE_RATE_8K = 0,
-+	MTK_AFE_RATE_11K = 1,
-+	MTK_AFE_RATE_12K = 2,
-+	MTK_AFE_RATE_16K = 4,
-+	MTK_AFE_RATE_22K = 5,
-+	MTK_AFE_RATE_24K = 6,
-+	MTK_AFE_RATE_32K = 8,
-+	MTK_AFE_RATE_44K = 9,
-+	MTK_AFE_RATE_48K = 10,
-+	MTK_AFE_RATE_88K = 13,
-+	MTK_AFE_RATE_96K = 14,
-+	MTK_AFE_RATE_176K = 17,
-+	MTK_AFE_RATE_192K = 18,
-+};
-+
-+enum {
-+	CLK_INFRA_AUD_BUS_CK = 0,
-+	CLK_INFRA_AUD_26M_CK,
-+	CLK_INFRA_AUD_L_CK,
-+	CLK_INFRA_AUD_AUD_CK,
-+	CLK_INFRA_AUD_EG2_CK,
-+	CLK_NUM
-+};
-+
-+static const char *aud_clks[CLK_NUM] = {
-+	[CLK_INFRA_AUD_BUS_CK] = "aud_bus_ck",
-+	[CLK_INFRA_AUD_26M_CK] = "aud_26m_ck",
-+	[CLK_INFRA_AUD_L_CK] = "aud_l_ck",
-+	[CLK_INFRA_AUD_AUD_CK] = "aud_aud_ck",
-+	[CLK_INFRA_AUD_EG2_CK] = "aud_eg2_ck",
-+};
-+
-+unsigned int mt7986_afe_rate_transform(struct device *dev, unsigned int rate)
-+{
-+	switch (rate) {
-+	case 8000:
-+		return MTK_AFE_RATE_8K;
-+	case 11025:
-+		return MTK_AFE_RATE_11K;
-+	case 12000:
-+		return MTK_AFE_RATE_12K;
-+	case 16000:
-+		return MTK_AFE_RATE_16K;
-+	case 22050:
-+		return MTK_AFE_RATE_22K;
-+	case 24000:
-+		return MTK_AFE_RATE_24K;
-+	case 32000:
-+		return MTK_AFE_RATE_32K;
-+	case 44100:
-+		return MTK_AFE_RATE_44K;
-+	case 48000:
-+		return MTK_AFE_RATE_48K;
-+	case 88200:
-+		return MTK_AFE_RATE_88K;
-+	case 96000:
-+		return MTK_AFE_RATE_96K;
-+	case 176400:
-+		return MTK_AFE_RATE_176K;
-+	case 192000:
-+		return MTK_AFE_RATE_192K;
-+	default:
-+		dev_warn(dev, "%s(), rate %u invalid, using %d!!!\n",
-+			 __func__, rate, MTK_AFE_RATE_48K);
-+		return MTK_AFE_RATE_48K;
-+	}
-+}
-+
-+static const struct snd_pcm_hardware mt7986_afe_hardware = {
-+	.info = SNDRV_PCM_INFO_MMAP |
-+		SNDRV_PCM_INFO_INTERLEAVED |
-+		SNDRV_PCM_INFO_MMAP_VALID,
-+	.formats = SNDRV_PCM_FMTBIT_S16_LE |
-+		   SNDRV_PCM_FMTBIT_S24_LE |
-+		   SNDRV_PCM_FMTBIT_S32_LE,
-+	.period_bytes_min = 256,
-+	.period_bytes_max = 4 * 48 * 1024,
-+	.periods_min = 2,
-+	.periods_max = 256,
-+	.buffer_bytes_max = 8 * 48 * 1024,
-+	.fifo_size = 0,
-+};
-+
-+static int mt7986_memif_fs(struct snd_pcm_substream *substream,
-+			   unsigned int rate)
-+{
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
-+	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
-+
-+	return mt7986_afe_rate_transform(afe->dev, rate);
-+}
-+
-+static int mt7986_irq_fs(struct snd_pcm_substream *substream,
-+			 unsigned int rate)
-+{
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
-+	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
-+
-+	return mt7986_afe_rate_transform(afe->dev, rate);
-+}
-+
-+#define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 |\
-+		       SNDRV_PCM_RATE_88200 |\
-+		       SNDRV_PCM_RATE_96000 |\
-+		       SNDRV_PCM_RATE_176400 |\
-+		       SNDRV_PCM_RATE_192000)
-+
-+#define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
-+			 SNDRV_PCM_FMTBIT_S24_LE |\
-+			 SNDRV_PCM_FMTBIT_S32_LE)
-+
-+static struct snd_soc_dai_driver mt7986_memif_dai_driver[] = {
-+	/* FE DAIs: memory intefaces to CPU */
-+	{
-+		.name = "DL1",
-+		.id = MT7986_MEMIF_DL1,
-+		.playback = {
-+			.stream_name = "DL1",
-+			.channels_min = 1,
-+			.channels_max = 2,
-+			.rates = MTK_PCM_RATES,
-+			.formats = MTK_PCM_FORMATS,
-+		},
-+		.ops = &mtk_afe_fe_ops,
-+	},
-+	{
-+		.name = "UL1",
-+		.id = MT7986_MEMIF_VUL12,
-+		.capture = {
-+			.stream_name = "UL1",
-+			.channels_min = 1,
-+			.channels_max = 2,
-+			.rates = MTK_PCM_RATES,
-+			.formats = MTK_PCM_FORMATS,
-+		},
-+		.ops = &mtk_afe_fe_ops,
-+	},
-+};
-+
-+static const struct snd_kcontrol_new o018_mix[] = {
-+	SOC_DAPM_SINGLE_AUTODISABLE("I150_Switch", AFE_CONN018_4, 22, 1, 0),
-+};
-+
-+static const struct snd_kcontrol_new o019_mix[] = {
-+	SOC_DAPM_SINGLE_AUTODISABLE("I151_Switch", AFE_CONN019_4, 23, 1, 0),
-+};
-+
-+static const struct snd_soc_dapm_widget mt7986_memif_widgets[] = {
-+	/* DL */
-+	SND_SOC_DAPM_MIXER("I032", SND_SOC_NOPM, 0, 0, NULL, 0),
-+	SND_SOC_DAPM_MIXER("I033", SND_SOC_NOPM, 0, 0, NULL, 0),
-+
-+	/* UL */
-+	SND_SOC_DAPM_MIXER("O018", SND_SOC_NOPM, 0, 0,
-+			   o018_mix, ARRAY_SIZE(o018_mix)),
-+	SND_SOC_DAPM_MIXER("O019", SND_SOC_NOPM, 0, 0,
-+			   o019_mix, ARRAY_SIZE(o019_mix)),
-+};
-+
-+static const struct snd_soc_dapm_route mt7986_memif_routes[] = {
-+	{"I032", NULL, "DL1"},
-+	{"I033", NULL, "DL1"},
-+	{"UL1", NULL, "O018"},
-+	{"UL1", NULL, "O019"},
-+	{"O018", "I150_Switch", "I150"},
-+	{"O019", "I151_Switch", "I151"},
-+};
-+
-+static const struct snd_soc_component_driver mt7986_afe_pcm_dai_component = {
-+	.name = "mt7986-afe-pcm-dai",
-+};
-+
-+static const struct mtk_base_memif_data memif_data[MT7986_MEMIF_NUM] = {
-+	[MT7986_MEMIF_DL1] = {
-+		.name = "DL1",
-+		.id = MT7986_MEMIF_DL1,
-+		.reg_ofs_base = AFE_DL0_BASE,
-+		.reg_ofs_cur = AFE_DL0_CUR,
-+		.reg_ofs_end = AFE_DL0_END,
-+		.reg_ofs_base_msb = AFE_DL0_BASE_MSB,
-+		.reg_ofs_cur_msb = AFE_DL0_CUR_MSB,
-+		.reg_ofs_end_msb = AFE_DL0_END_MSB,
-+		.fs_reg = AFE_DL0_CON0,
-+		.fs_shift =  DL0_MODE_SFT,
-+		.fs_maskbit =  DL0_MODE_MASK,
-+		.mono_reg = AFE_DL0_CON0,
-+		.mono_shift = DL0_MONO_SFT,
-+		.enable_reg = AFE_DL0_CON0,
-+		.enable_shift = DL0_ON_SFT,
-+		.hd_reg = AFE_DL0_CON0,
-+		.hd_shift = DL0_HD_MODE_SFT,
-+		.hd_align_reg = AFE_DL0_CON0,
-+		.hd_align_mshift = DL0_HALIGN_SFT,
-+		.pbuf_reg = AFE_DL0_CON0,
-+		.pbuf_shift = DL0_PBUF_SIZE_SFT,
-+		.minlen_reg = AFE_DL0_CON0,
-+		.minlen_shift = DL0_MINLEN_SFT,
-+	},
-+	[MT7986_MEMIF_VUL12] = {
-+		.name = "VUL12",
-+		.id = MT7986_MEMIF_VUL12,
-+		.reg_ofs_base = AFE_VUL0_BASE,
-+		.reg_ofs_cur = AFE_VUL0_CUR,
-+		.reg_ofs_end = AFE_VUL0_END,
-+		.reg_ofs_base_msb = AFE_VUL0_BASE_MSB,
-+		.reg_ofs_cur_msb = AFE_VUL0_CUR_MSB,
-+		.reg_ofs_end_msb = AFE_VUL0_END_MSB,
-+		.fs_reg = AFE_VUL0_CON0,
-+		.fs_shift = VUL0_MODE_SFT,
-+		.fs_maskbit = VUL0_MODE_MASK,
-+		.mono_reg = AFE_VUL0_CON0,
-+		.mono_shift = VUL0_MONO_SFT,
-+		.enable_reg = AFE_VUL0_CON0,
-+		.enable_shift = VUL0_ON_SFT,
-+		.hd_reg = AFE_VUL0_CON0,
-+		.hd_shift = VUL0_HD_MODE_SFT,
-+		.hd_align_reg = AFE_VUL0_CON0,
-+		.hd_align_mshift = VUL0_HALIGN_SFT,
-+	},
-+};
-+
-+static const struct mtk_base_irq_data irq_data[MT7986_IRQ_NUM] = {
-+	[MT7986_IRQ_0] = {
-+		.id = MT7986_IRQ_0,
-+		.irq_cnt_reg = AFE_IRQ0_MCU_CFG1,
-+		.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
-+		.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
-+		.irq_fs_reg = AFE_IRQ0_MCU_CFG0,
-+		.irq_fs_shift = IRQ_MCU_MODE_SFT,
-+		.irq_fs_maskbit = IRQ_MCU_MODE_MASK,
-+		.irq_en_reg = AFE_IRQ0_MCU_CFG0,
-+		.irq_en_shift = IRQ_MCU_ON_SFT,
-+		.irq_clr_reg = AFE_IRQ_MCU_CLR,
-+		.irq_clr_shift = IRQ0_MCU_CLR_SFT,
-+	},
-+	[MT7986_IRQ_1] = {
-+		.id = MT7986_IRQ_1,
-+		.irq_cnt_reg = AFE_IRQ1_MCU_CFG1,
-+		.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
-+		.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
-+		.irq_fs_reg = AFE_IRQ1_MCU_CFG0,
-+		.irq_fs_shift = IRQ_MCU_MODE_SFT,
-+		.irq_fs_maskbit = IRQ_MCU_MODE_MASK,
-+		.irq_en_reg = AFE_IRQ1_MCU_CFG0,
-+		.irq_en_shift = IRQ_MCU_ON_SFT,
-+		.irq_clr_reg = AFE_IRQ_MCU_CLR,
-+		.irq_clr_shift = IRQ1_MCU_CLR_SFT,
-+	},
-+	[MT7986_IRQ_2] = {
-+		.id = MT7986_IRQ_2,
-+		.irq_cnt_reg = AFE_IRQ2_MCU_CFG1,
-+		.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
-+		.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
-+		.irq_fs_reg = AFE_IRQ2_MCU_CFG0,
-+		.irq_fs_shift = IRQ_MCU_MODE_SFT,
-+		.irq_fs_maskbit = IRQ_MCU_MODE_MASK,
-+		.irq_en_reg = AFE_IRQ2_MCU_CFG0,
-+		.irq_en_shift = IRQ_MCU_ON_SFT,
-+		.irq_clr_reg = AFE_IRQ_MCU_CLR,
-+		.irq_clr_shift = IRQ2_MCU_CLR_SFT,
-+	},
-+};
-+
-+static bool mt7986_is_volatile_reg(struct device *dev, unsigned int reg)
-+{
-+	/*
-+	 * Those auto-gen regs are read-only, so put it as volatile because
-+	 * volatile registers cannot be cached, which means that they cannot
-+	 * be set when power is off
-+	 */
-+
-+	switch (reg) {
-+	case AFE_DL0_CUR_MSB:
-+	case AFE_DL0_CUR:
-+	case AFE_DL0_RCH_MON:
-+	case AFE_DL0_LCH_MON:
-+	case AFE_VUL0_CUR_MSB:
-+	case AFE_VUL0_CUR:
-+	case AFE_IRQ_MCU_STATUS:
-+	case AFE_MEMIF_RD_MON:
-+	case AFE_MEMIF_WR_MON:
-+		return true;
-+	default:
-+		return false;
-+	};
-+}
-+
-+static const struct regmap_config mt7986_afe_regmap_config = {
-+	.reg_bits = 32,
-+	.reg_stride = 4,
-+	.val_bits = 32,
-+	.volatile_reg = mt7986_is_volatile_reg,
-+	.max_register = AFE_MAX_REGISTER,
-+	.num_reg_defaults_raw = ((AFE_MAX_REGISTER / 4) + 1),
-+};
-+
-+static int mt7986_init_clock(struct mtk_base_afe *afe)
-+{
-+	struct mt7986_afe_private *afe_priv = afe->platform_priv;
-+	int ret, i;
-+
-+	afe_priv->clks = devm_kcalloc(afe->dev, CLK_NUM,
-+				sizeof(*afe_priv->clks), GFP_KERNEL);
-+	if (!afe_priv->clks)
-+		return -ENOMEM;
-+	afe_priv->num_clks = CLK_NUM;
-+
-+	for (i = 0; i < afe_priv->num_clks; i++)
-+		afe_priv->clks[i].id = aud_clks[i];
-+
-+	ret = devm_clk_bulk_get(afe->dev, afe_priv->num_clks, afe_priv->clks);
-+	if (ret)
-+		return dev_err_probe(afe->dev, ret, "Failed to get clocks\n");
-+
-+	return 0;
-+}
-+
-+static irqreturn_t mt7986_afe_irq_handler(int irq_id, void *dev)
-+{
-+	struct mtk_base_afe *afe = dev;
-+	struct mtk_base_afe_irq *irq;
-+	u32 mcu_en, status, status_mcu;
-+	int i, ret;
-+	irqreturn_t irq_ret = IRQ_HANDLED;
-+
-+	/* get irq that is sent to MCU */
-+	regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &mcu_en);
-+
-+	ret = regmap_read(afe->regmap, AFE_IRQ_MCU_STATUS, &status);
-+	/* only care IRQ which is sent to MCU */
-+	status_mcu = status & mcu_en & AFE_IRQ_STATUS_BITS;
-+
-+	if (ret || status_mcu == 0) {
-+		dev_err(afe->dev, "%s(), irq status err, ret %d, status 0x%x, mcu_en 0x%x\n",
-+			__func__, ret, status, mcu_en);
-+
-+		irq_ret = IRQ_NONE;
-+		goto err_irq;
-+	}
-+
-+	for (i = 0; i < MT7986_MEMIF_NUM; i++) {
-+		struct mtk_base_afe_memif *memif = &afe->memif[i];
-+
-+		if (!memif->substream)
-+			continue;
-+
-+		if (memif->irq_usage < 0)
-+			continue;
-+
-+		irq = &afe->irqs[memif->irq_usage];
-+
-+		if (status_mcu & (1 << irq->irq_data->irq_en_shift))
-+			snd_pcm_period_elapsed(memif->substream);
-+	}
-+
-+err_irq:
-+	/* clear irq */
-+	regmap_write(afe->regmap, AFE_IRQ_MCU_CLR, status_mcu);
-+
-+	return irq_ret;
-+}
-+
-+static int mt7986_afe_runtime_suspend(struct device *dev)
-+{
-+	struct mtk_base_afe *afe = dev_get_drvdata(dev);
-+	struct mt7986_afe_private *afe_priv = afe->platform_priv;
-+
-+	if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)
-+		goto skip_regmap;
-+
-+	/* disable clk*/
-+	regmap_update_bits(afe->regmap, AUDIO_TOP_CON4, 0x3fff, 0x3fff);
-+	regmap_update_bits(afe->regmap, AUDIO_ENGEN_CON0, AUD_APLL2_EN_MASK, 0);
-+	regmap_update_bits(afe->regmap, AUDIO_ENGEN_CON0, AUD_26M_EN_MASK, 0);
-+
-+	/* make sure all irq status are cleared, twice intended */
-+	regmap_update_bits(afe->regmap, AFE_IRQ_MCU_CLR, 0xffff, 0xffff);
-+
-+skip_regmap:
-+	clk_bulk_disable_unprepare(afe_priv->num_clks, afe_priv->clks);
-+
-+	return 0;
-+}
-+
-+static int mt7986_afe_runtime_resume(struct device *dev)
-+{
-+	struct mtk_base_afe *afe = dev_get_drvdata(dev);
-+	struct mt7986_afe_private *afe_priv = afe->platform_priv;
-+	int ret;
-+
-+	ret = clk_bulk_prepare_enable(afe_priv->num_clks, afe_priv->clks);
-+	if (ret)
-+		return dev_err_probe(afe->dev, ret, "Failed to enable clocks\n");
-+
-+	if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)
-+		return 0;
-+
-+	/* enable clk*/
-+	regmap_update_bits(afe->regmap, AUDIO_TOP_CON4, 0x3fff, 0);
-+	regmap_update_bits(afe->regmap, AUDIO_ENGEN_CON0, AUD_APLL2_EN_MASK,
-+			   AUD_APLL2_EN);
-+	regmap_update_bits(afe->regmap, AUDIO_ENGEN_CON0, AUD_26M_EN_MASK,
-+			   AUD_26M_EN);
-+
-+	return 0;
-+}
-+
-+static int mt7986_afe_component_probe(struct snd_soc_component *component)
-+{
-+	return mtk_afe_add_sub_dai_control(component);
-+}
-+
-+static const struct snd_soc_component_driver mt7986_afe_component = {
-+	.name = AFE_PCM_NAME,
-+	.probe = mt7986_afe_component_probe,
-+	.pointer	= mtk_afe_pcm_pointer,
-+	.pcm_construct	= mtk_afe_pcm_new,
-+};
-+
-+static int mt7986_dai_memif_register(struct mtk_base_afe *afe)
-+{
-+	struct mtk_base_afe_dai *dai;
-+
-+	dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
-+	if (!dai)
-+		return -ENOMEM;
-+
-+	list_add(&dai->list, &afe->sub_dais);
-+
-+	dai->dai_drivers = mt7986_memif_dai_driver;
-+	dai->num_dai_drivers = ARRAY_SIZE(mt7986_memif_dai_driver);
-+
-+	dai->dapm_widgets = mt7986_memif_widgets;
-+	dai->num_dapm_widgets = ARRAY_SIZE(mt7986_memif_widgets);
-+	dai->dapm_routes = mt7986_memif_routes;
-+	dai->num_dapm_routes = ARRAY_SIZE(mt7986_memif_routes);
-+
-+	return 0;
-+}
-+
-+typedef int (*dai_register_cb)(struct mtk_base_afe *);
-+static const dai_register_cb dai_register_cbs[] = {
-+	mt7986_dai_etdm_register,
-+	mt7986_dai_memif_register,
-+};
-+
-+static int mt7986_afe_pcm_dev_probe(struct platform_device *pdev)
-+{
-+	struct mtk_base_afe *afe;
-+	struct mt7986_afe_private *afe_priv;
-+	struct device *dev;
-+	int i, irq_id, ret;
-+
-+	afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
-+	if (!afe)
-+		return -ENOMEM;
-+	platform_set_drvdata(pdev, afe);
-+
-+	afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv),
-+					  GFP_KERNEL);
-+	if (!afe->platform_priv)
-+		return -ENOMEM;
-+
-+	afe_priv = afe->platform_priv;
-+	afe->dev = &pdev->dev;
-+	dev = afe->dev;
-+
-+	afe->base_addr = devm_platform_ioremap_resource(pdev, 0);
-+	if (IS_ERR(afe->base_addr))
-+		return PTR_ERR(afe->base_addr);
-+
-+	/* initial audio related clock */
-+	ret = mt7986_init_clock(afe);
-+	if (ret)
-+		return dev_err_probe(dev, ret, "Cannot initialize clocks\n");
-+
-+	ret = devm_pm_runtime_enable(dev);
-+	if (ret)
-+		return ret;
-+
-+	/* enable clock for regcache get default value from hw */
-+	afe_priv->pm_runtime_bypass_reg_ctl = true;
-+	pm_runtime_get_sync(&pdev->dev);
-+
-+	afe->regmap = devm_regmap_init_mmio(&pdev->dev, afe->base_addr,
-+		      &mt7986_afe_regmap_config);
-+
-+	pm_runtime_put_sync(&pdev->dev);
-+	if (IS_ERR(afe->regmap))
-+		return PTR_ERR(afe->regmap);
-+
-+	afe_priv->pm_runtime_bypass_reg_ctl = false;
-+
-+	/* init memif */
-+	afe->memif_size = MT7986_MEMIF_NUM;
-+	afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif),
-+				  GFP_KERNEL);
-+	if (!afe->memif)
-+		return -ENOMEM;
-+
-+	for (i = 0; i < afe->memif_size; i++) {
-+		afe->memif[i].data = &memif_data[i];
-+		afe->memif[i].irq_usage = -1;
-+	}
-+
-+	mutex_init(&afe->irq_alloc_lock);
-+
-+	/* irq initialize */
-+	afe->irqs_size = MT7986_IRQ_NUM;
-+	afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),
-+				 GFP_KERNEL);
-+	if (!afe->irqs)
-+		return -ENOMEM;
-+
-+	for (i = 0; i < afe->irqs_size; i++)
-+		afe->irqs[i].irq_data = &irq_data[i];
-+
-+	/* request irq */
-+	irq_id = platform_get_irq(pdev, 0);
-+	if (irq_id < 0) {
-+		ret = irq_id;
-+		return dev_err_probe(dev, ret, "No irq found\n");
-+	}
-+	ret = devm_request_irq(dev, irq_id, mt7986_afe_irq_handler,
-+			       IRQF_TRIGGER_NONE, "asys-isr", (void *)afe);
-+	if (ret)
-+		return dev_err_probe(dev, ret, "Failed to request irq for asys-isr\n");
-+
-+	/* init sub_dais */
-+	INIT_LIST_HEAD(&afe->sub_dais);
-+
-+	for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) {
-+		ret = dai_register_cbs[i](afe);
-+		if (ret)
-+			return dev_err_probe(dev, ret, "DAI register failed, i: %d\n", i);
-+	}
-+
-+	/* init dai_driver and component_driver */
-+	ret = mtk_afe_combine_sub_dai(afe);
-+	if (ret)
-+		return dev_err_probe(dev, ret, "mtk_afe_combine_sub_dai fail\n");
-+
-+	afe->mtk_afe_hardware = &mt7986_afe_hardware;
-+	afe->memif_fs = mt7986_memif_fs;
-+	afe->irq_fs = mt7986_irq_fs;
-+
-+	afe->runtime_resume = mt7986_afe_runtime_resume;
-+	afe->runtime_suspend = mt7986_afe_runtime_suspend;
-+
-+	/* register component */
-+	ret = devm_snd_soc_register_component(&pdev->dev,
-+					      &mt7986_afe_component,
-+					      NULL, 0);
-+	if (ret)
-+		return dev_err_probe(dev, ret, "Cannot register AFE component\n");
-+
-+	ret = devm_snd_soc_register_component(afe->dev,
-+					      &mt7986_afe_pcm_dai_component,
-+					      afe->dai_drivers,
-+					      afe->num_dai_drivers);
-+	if (ret)
-+		return dev_err_probe(dev, ret, "Cannot register PCM DAI component\n");
-+
-+	return 0;
-+}
-+
-+static void mt7986_afe_pcm_dev_remove(struct platform_device *pdev)
-+{
-+	pm_runtime_disable(&pdev->dev);
-+	if (!pm_runtime_status_suspended(&pdev->dev))
-+		mt7986_afe_runtime_suspend(&pdev->dev);
-+}
-+
-+static const struct of_device_id mt7986_afe_pcm_dt_match[] = {
-+	{ .compatible = "mediatek,mt7986-afe" },
-+	{ /* sentinel */ }
-+};
-+MODULE_DEVICE_TABLE(of, mt7986_afe_pcm_dt_match);
-+
-+static const struct dev_pm_ops mt7986_afe_pm_ops = {
-+	SET_RUNTIME_PM_OPS(mt7986_afe_runtime_suspend,
-+			   mt7986_afe_runtime_resume, NULL)
-+};
-+
-+static struct platform_driver mt7986_afe_pcm_driver = {
-+	.driver = {
-+		   .name = "mt7986-audio",
-+		   .of_match_table = mt7986_afe_pcm_dt_match,
-+		   .pm = &mt7986_afe_pm_ops,
-+	},
-+	.probe = mt7986_afe_pcm_dev_probe,
-+	.remove_new = mt7986_afe_pcm_dev_remove,
-+};
-+module_platform_driver(mt7986_afe_pcm_driver);
-+
-+MODULE_DESCRIPTION("MediaTek SoC AFE platform driver for ALSA MT7986");
-+MODULE_AUTHOR("Vic Wu <vic.wu@mediatek.com>");
-+MODULE_LICENSE("GPL");
diff --git a/target/linux/mediatek/patches-5.15/860-v6.6-04-ASoC-mediatek-mt7986-add-machine-driver-with-wm8960.patch b/target/linux/mediatek/patches-5.15/860-v6.6-04-ASoC-mediatek-mt7986-add-machine-driver-with-wm8960.patch
deleted file mode 100644
index dd354c04e3d318..00000000000000
--- a/target/linux/mediatek/patches-5.15/860-v6.6-04-ASoC-mediatek-mt7986-add-machine-driver-with-wm8960.patch
+++ /dev/null
@@ -1,243 +0,0 @@
-From ddf6abc1c78072f8ccad59166be95f0ca5af8ca4 Mon Sep 17 00:00:00 2001
-From: Maso Huang <maso.huang@mediatek.com>
-Date: Thu, 17 Aug 2023 18:13:36 +0800
-Subject: [PATCH 4/9] ASoC: mediatek: mt7986: add machine driver with wm8960
-
-Add support for mt7986 board with wm8960.
-
-Signed-off-by: Maso Huang <maso.huang@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20230817101338.18782-5-maso.huang@mediatek.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- sound/soc/mediatek/Kconfig                |  10 ++
- sound/soc/mediatek/mt7986/Makefile        |   1 +
- sound/soc/mediatek/mt7986/mt7986-wm8960.c | 196 ++++++++++++++++++++++
- 3 files changed, 207 insertions(+)
- create mode 100644 sound/soc/mediatek/mt7986/mt7986-wm8960.c
-
---- a/sound/soc/mediatek/Kconfig
-+++ b/sound/soc/mediatek/Kconfig
-@@ -64,6 +64,16 @@ config SND_SOC_MT7986
- 	  Select Y if you have such device.
- 	  If unsure select "N".
- 
-+config SND_SOC_MT7986_WM8960
-+	tristate "ASoc Audio driver for MT7986 with WM8960 codec"
-+	depends on SND_SOC_MT7986 && I2C
-+	select SND_SOC_WM8960
-+	help
-+	  This adds support for ASoC machine driver for MediaTek MT7986
-+	  boards with the WM8960 codecs.
-+	  Select Y if you have such device.
-+	  If unsure select "N".
-+
- config SND_SOC_MT8173
- 	tristate "ASoC support for Mediatek MT8173 chip"
- 	depends on ARCH_MEDIATEK
---- a/sound/soc/mediatek/mt7986/Makefile
-+++ b/sound/soc/mediatek/mt7986/Makefile
-@@ -6,3 +6,4 @@ snd-soc-mt7986-afe-objs := \
- 	mt7986-dai-etdm.o
- 
- obj-$(CONFIG_SND_SOC_MT7986) += snd-soc-mt7986-afe.o
-+obj-$(CONFIG_SND_SOC_MT7986_WM8960) += mt7986-wm8960.o
---- /dev/null
-+++ b/sound/soc/mediatek/mt7986/mt7986-wm8960.c
-@@ -0,0 +1,196 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * mt7986-wm8960.c  --  MT7986-WM8960 ALSA SoC machine driver
-+ *
-+ * Copyright (c) 2023 MediaTek Inc.
-+ * Authors: Vic Wu <vic.wu@mediatek.com>
-+ *          Maso Huang <maso.huang@mediatek.com>
-+ */
-+
-+#include <linux/module.h>
-+#include <sound/soc.h>
-+
-+#include "mt7986-afe-common.h"
-+
-+struct mt7986_wm8960_priv {
-+	struct device_node *platform_node;
-+	struct device_node *codec_node;
-+};
-+
-+static const struct snd_soc_dapm_widget mt7986_wm8960_widgets[] = {
-+	SND_SOC_DAPM_HP("Headphone", NULL),
-+	SND_SOC_DAPM_MIC("AMIC", NULL),
-+};
-+
-+static const struct snd_kcontrol_new mt7986_wm8960_controls[] = {
-+	SOC_DAPM_PIN_SWITCH("Headphone"),
-+	SOC_DAPM_PIN_SWITCH("AMIC"),
-+};
-+
-+SND_SOC_DAILINK_DEFS(playback,
-+	DAILINK_COMP_ARRAY(COMP_CPU("DL1")),
-+	DAILINK_COMP_ARRAY(COMP_DUMMY()),
-+	DAILINK_COMP_ARRAY(COMP_EMPTY()));
-+
-+SND_SOC_DAILINK_DEFS(capture,
-+	DAILINK_COMP_ARRAY(COMP_CPU("UL1")),
-+	DAILINK_COMP_ARRAY(COMP_DUMMY()),
-+	DAILINK_COMP_ARRAY(COMP_EMPTY()));
-+
-+SND_SOC_DAILINK_DEFS(codec,
-+	DAILINK_COMP_ARRAY(COMP_CPU("ETDM")),
-+	DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "wm8960-hifi")),
-+	DAILINK_COMP_ARRAY(COMP_EMPTY()));
-+
-+static struct snd_soc_dai_link mt7986_wm8960_dai_links[] = {
-+	/* FE */
-+	{
-+		.name = "wm8960-playback",
-+		.stream_name = "wm8960-playback",
-+		.trigger = {SND_SOC_DPCM_TRIGGER_POST,
-+			    SND_SOC_DPCM_TRIGGER_POST},
-+		.dynamic = 1,
-+		.dpcm_playback = 1,
-+		SND_SOC_DAILINK_REG(playback),
-+	},
-+	{
-+		.name = "wm8960-capture",
-+		.stream_name = "wm8960-capture",
-+		.trigger = {SND_SOC_DPCM_TRIGGER_POST,
-+			    SND_SOC_DPCM_TRIGGER_POST},
-+		.dynamic = 1,
-+		.dpcm_capture = 1,
-+		SND_SOC_DAILINK_REG(capture),
-+	},
-+	/* BE */
-+	{
-+		.name = "wm8960-codec",
-+		.no_pcm = 1,
-+		.dai_fmt = SND_SOC_DAIFMT_I2S |
-+			SND_SOC_DAIFMT_NB_NF |
-+			SND_SOC_DAIFMT_CBS_CFS |
-+			SND_SOC_DAIFMT_GATED,
-+		.dpcm_playback = 1,
-+		.dpcm_capture = 1,
-+		SND_SOC_DAILINK_REG(codec),
-+	},
-+};
-+
-+static struct snd_soc_card mt7986_wm8960_card = {
-+	.name = "mt7986-wm8960",
-+	.owner = THIS_MODULE,
-+	.dai_link = mt7986_wm8960_dai_links,
-+	.num_links = ARRAY_SIZE(mt7986_wm8960_dai_links),
-+	.controls = mt7986_wm8960_controls,
-+	.num_controls = ARRAY_SIZE(mt7986_wm8960_controls),
-+	.dapm_widgets = mt7986_wm8960_widgets,
-+	.num_dapm_widgets = ARRAY_SIZE(mt7986_wm8960_widgets),
-+};
-+
-+static int mt7986_wm8960_machine_probe(struct platform_device *pdev)
-+{
-+	struct snd_soc_card *card = &mt7986_wm8960_card;
-+	struct snd_soc_dai_link *dai_link;
-+	struct device_node *platform, *codec;
-+	struct mt7986_wm8960_priv *priv;
-+	int ret, i;
-+
-+	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
-+	if (!priv)
-+		return -ENOMEM;
-+
-+	platform = of_get_child_by_name(pdev->dev.of_node, "platform");
-+
-+	if (platform) {
-+		priv->platform_node = of_parse_phandle(platform, "sound-dai", 0);
-+		of_node_put(platform);
-+
-+		if (!priv->platform_node) {
-+			dev_err(&pdev->dev, "Failed to parse platform/sound-dai property\n");
-+			return -EINVAL;
-+		}
-+	} else {
-+		dev_err(&pdev->dev, "Property 'platform' missing or invalid\n");
-+		return -EINVAL;
-+	}
-+
-+	for_each_card_prelinks(card, i, dai_link) {
-+		if (dai_link->platforms->name)
-+			continue;
-+		dai_link->platforms->of_node = priv->platform_node;
-+	}
-+
-+	card->dev = &pdev->dev;
-+
-+	codec = of_get_child_by_name(pdev->dev.of_node, "codec");
-+
-+	if (codec) {
-+		priv->codec_node = of_parse_phandle(codec, "sound-dai", 0);
-+		of_node_put(codec);
-+
-+		if (!priv->codec_node) {
-+			of_node_put(priv->platform_node);
-+			dev_err(&pdev->dev, "Failed to parse codec/sound-dai property\n");
-+			return -EINVAL;
-+		}
-+	} else {
-+		of_node_put(priv->platform_node);
-+		dev_err(&pdev->dev, "Property 'codec' missing or invalid\n");
-+		return -EINVAL;
-+	}
-+
-+	for_each_card_prelinks(card, i, dai_link) {
-+		if (dai_link->codecs->name)
-+			continue;
-+		dai_link->codecs->of_node = priv->codec_node;
-+	}
-+
-+	ret = snd_soc_of_parse_audio_routing(card, "audio-routing");
-+	if (ret) {
-+		dev_err(&pdev->dev, "Failed to parse audio-routing: %d\n", ret);
-+		goto err_of_node_put;
-+	}
-+
-+	ret = devm_snd_soc_register_card(&pdev->dev, card);
-+	if (ret) {
-+		dev_err(&pdev->dev, "%s snd_soc_register_card fail: %d\n", __func__, ret);
-+		goto err_of_node_put;
-+	}
-+
-+err_of_node_put:
-+	of_node_put(priv->codec_node);
-+	of_node_put(priv->platform_node);
-+	return ret;
-+}
-+
-+static void mt7986_wm8960_machine_remove(struct platform_device *pdev)
-+{
-+	struct snd_soc_card *card = platform_get_drvdata(pdev);
-+	struct mt7986_wm8960_priv *priv = snd_soc_card_get_drvdata(card);
-+
-+	of_node_put(priv->codec_node);
-+	of_node_put(priv->platform_node);
-+}
-+
-+static const struct of_device_id mt7986_wm8960_machine_dt_match[] = {
-+	{.compatible = "mediatek,mt7986-wm8960-sound"},
-+	{ /* sentinel */ }
-+};
-+MODULE_DEVICE_TABLE(of, mt7986_wm8960_machine_dt_match);
-+
-+static struct platform_driver mt7986_wm8960_machine = {
-+	.driver = {
-+		.name = "mt7986-wm8960",
-+		.of_match_table = mt7986_wm8960_machine_dt_match,
-+	},
-+	.probe = mt7986_wm8960_machine_probe,
-+	.remove_new = mt7986_wm8960_machine_remove,
-+};
-+
-+module_platform_driver(mt7986_wm8960_machine);
-+
-+/* Module information */
-+MODULE_DESCRIPTION("MT7986 WM8960 ALSA SoC machine driver");
-+MODULE_AUTHOR("Vic Wu <vic.wu@mediatek.com>");
-+MODULE_LICENSE("GPL");
-+MODULE_ALIAS("mt7986 wm8960 soc card");
diff --git a/target/linux/mediatek/patches-5.15/860-v6.6-05-ASoC-dt-bindings-mediatek-mt7986-wm8960-add-mt7986-w.patch b/target/linux/mediatek/patches-5.15/860-v6.6-05-ASoC-dt-bindings-mediatek-mt7986-wm8960-add-mt7986-w.patch
deleted file mode 100644
index 8cf0b5464a964b..00000000000000
--- a/target/linux/mediatek/patches-5.15/860-v6.6-05-ASoC-dt-bindings-mediatek-mt7986-wm8960-add-mt7986-w.patch
+++ /dev/null
@@ -1,87 +0,0 @@
-From 72469f950b629e57e60fbcbefed45e083619b986 Mon Sep 17 00:00:00 2001
-From: Maso Huang <maso.huang@mediatek.com>
-Date: Thu, 17 Aug 2023 18:13:37 +0800
-Subject: [PATCH 5/9] ASoC: dt-bindings: mediatek,mt7986-wm8960: add
- mt7986-wm8960 document
-
-Add document for mt7986 board with wm8960.
-
-Signed-off-by: Maso Huang <maso.huang@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20230817101338.18782-6-maso.huang@mediatek.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- .../sound/mediatek,mt7986-wm8960.yaml         | 67 +++++++++++++++++++
- 1 file changed, 67 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/sound/mediatek,mt7986-wm8960.yaml
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/sound/mediatek,mt7986-wm8960.yaml
-@@ -0,0 +1,67 @@
-+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/sound/mediatek,mt7986-wm8960.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: MediaTek MT7986 sound card with WM8960 codec
-+
-+maintainers:
-+  - Maso Huang <maso.huang@mediatek.com>
-+
-+allOf:
-+  - $ref: sound-card-common.yaml#
-+
-+properties:
-+  compatible:
-+    const: mediatek,mt7986-wm8960-sound
-+
-+  platform:
-+    type: object
-+    additionalProperties: false
-+    properties:
-+      sound-dai:
-+        description: The phandle of MT7986 platform.
-+        maxItems: 1
-+    required:
-+      - sound-dai
-+
-+  codec:
-+    type: object
-+    additionalProperties: false
-+    properties:
-+      sound-dai:
-+        description: The phandle of wm8960 codec.
-+        maxItems: 1
-+    required:
-+      - sound-dai
-+
-+unevaluatedProperties: false
-+
-+required:
-+  - compatible
-+  - audio-routing
-+  - platform
-+  - codec
-+
-+examples:
-+  - |
-+    sound {
-+        compatible = "mediatek,mt7986-wm8960-sound";
-+        model = "mt7986-wm8960";
-+        audio-routing =
-+            "Headphone", "HP_L",
-+            "Headphone", "HP_R",
-+            "LINPUT1", "AMIC",
-+            "RINPUT1", "AMIC";
-+
-+        platform {
-+            sound-dai = <&afe>;
-+        };
-+
-+        codec {
-+            sound-dai = <&wm8960>;
-+        };
-+    };
-+
-+...
diff --git a/target/linux/mediatek/patches-5.15/860-v6.6-06-ASoC-dt-bindings-mediatek-mt7986-afe-add-audio-afe-d.patch b/target/linux/mediatek/patches-5.15/860-v6.6-06-ASoC-dt-bindings-mediatek-mt7986-afe-add-audio-afe-d.patch
deleted file mode 100644
index 236d6a217c50cb..00000000000000
--- a/target/linux/mediatek/patches-5.15/860-v6.6-06-ASoC-dt-bindings-mediatek-mt7986-afe-add-audio-afe-d.patch
+++ /dev/null
@@ -1,180 +0,0 @@
-From d16202eb38585adbc16e32d11188dbc2127015de Mon Sep 17 00:00:00 2001
-From: Maso Huang <maso.huang@mediatek.com>
-Date: Thu, 17 Aug 2023 18:13:38 +0800
-Subject: [PATCH 6/9] ASoC: dt-bindings: mediatek,mt7986-afe: add audio afe
- document
-
-Add mt7986 audio afe document.
-
-Signed-off-by: Maso Huang <maso.huang@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20230817101338.18782-7-maso.huang@mediatek.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- .../bindings/sound/mediatek,mt7986-afe.yaml   | 160 ++++++++++++++++++
- 1 file changed, 160 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/sound/mediatek,mt7986-afe.yaml
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/sound/mediatek,mt7986-afe.yaml
-@@ -0,0 +1,160 @@
-+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/sound/mediatek,mt7986-afe.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: MediaTek AFE PCM controller for MT7986
-+
-+maintainers:
-+  - Maso Huang <maso.huang@mediatek.com>
-+
-+properties:
-+  compatible:
-+    oneOf:
-+      - const: mediatek,mt7986-afe
-+      - items:
-+          - enum:
-+              - mediatek,mt7981-afe
-+              - mediatek,mt7988-afe
-+          - const: mediatek,mt7986-afe
-+
-+  reg:
-+    maxItems: 1
-+
-+  interrupts:
-+    maxItems: 1
-+
-+  clocks:
-+    minItems: 5
-+    items:
-+      - description: audio bus clock
-+      - description: audio 26M clock
-+      - description: audio intbus clock
-+      - description: audio hopping clock
-+      - description: audio pll clock
-+      - description: mux for pcm_mck
-+      - description: audio i2s/pcm mck
-+
-+  clock-names:
-+    minItems: 5
-+    items:
-+      - const: bus_ck
-+      - const: 26m_ck
-+      - const: l_ck
-+      - const: aud_ck
-+      - const: eg2_ck
-+      - const: sel
-+      - const: i2s_m
-+
-+required:
-+  - compatible
-+  - reg
-+  - interrupts
-+  - clocks
-+  - clock-names
-+
-+allOf:
-+  - if:
-+      properties:
-+        compatible:
-+          contains:
-+            const: mediatek,mt7986-afe
-+    then:
-+      properties:
-+        clocks:
-+          items:
-+            - description: audio bus clock
-+            - description: audio 26M clock
-+            - description: audio intbus clock
-+            - description: audio hopping clock
-+            - description: audio pll clock
-+        clock-names:
-+          items:
-+            - const: bus_ck
-+            - const: 26m_ck
-+            - const: l_ck
-+            - const: aud_ck
-+            - const: eg2_ck
-+
-+  - if:
-+      properties:
-+        compatible:
-+          contains:
-+            const: mediatek,mt7981-afe
-+    then:
-+      properties:
-+        clocks:
-+          items:
-+            - description: audio bus clock
-+            - description: audio 26M clock
-+            - description: audio intbus clock
-+            - description: audio hopping clock
-+            - description: audio pll clock
-+            - description: mux for pcm_mck
-+        clock-names:
-+          items:
-+            - const: bus_ck
-+            - const: 26m_ck
-+            - const: l_ck
-+            - const: aud_ck
-+            - const: eg2_ck
-+            - const: sel
-+
-+  - if:
-+      properties:
-+        compatible:
-+          contains:
-+            const: mediatek,mt7988-afe
-+    then:
-+      properties:
-+        clocks:
-+          items:
-+            - description: audio bus clock
-+            - description: audio 26M clock
-+            - description: audio intbus clock
-+            - description: audio hopping clock
-+            - description: audio pll clock
-+            - description: mux for pcm_mck
-+            - description: audio i2s/pcm mck
-+        clock-names:
-+          items:
-+            - const: bus_ck
-+            - const: 26m_ck
-+            - const: l_ck
-+            - const: aud_ck
-+            - const: eg2_ck
-+            - const: sel
-+            - const: i2s_m
-+
-+additionalProperties: false
-+
-+examples:
-+  - |
-+    #include <dt-bindings/interrupt-controller/arm-gic.h>
-+    #include <dt-bindings/interrupt-controller/irq.h>
-+    #include <dt-bindings/clock/mt7986-clk.h>
-+
-+    afe@11210000 {
-+        compatible = "mediatek,mt7986-afe";
-+        reg = <0x11210000 0x9000>;
-+        interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
-+        clocks = <&infracfg_ao CLK_INFRA_AUD_BUS_CK>,
-+                 <&infracfg_ao CLK_INFRA_AUD_26M_CK>,
-+                 <&infracfg_ao CLK_INFRA_AUD_L_CK>,
-+                 <&infracfg_ao CLK_INFRA_AUD_AUD_CK>,
-+                 <&infracfg_ao CLK_INFRA_AUD_EG2_CK>;
-+        clock-names = "bus_ck",
-+                      "26m_ck",
-+                      "l_ck",
-+                      "aud_ck",
-+                      "eg2_ck";
-+        assigned-clocks = <&topckgen CLK_TOP_A1SYS_SEL>,
-+                          <&topckgen CLK_TOP_AUD_L_SEL>,
-+                          <&topckgen CLK_TOP_A_TUNER_SEL>;
-+        assigned-clock-parents = <&topckgen CLK_TOP_APLL2_D4>,
-+                                 <&apmixedsys CLK_APMIXED_APLL2>,
-+                                 <&topckgen CLK_TOP_APLL2_D4>;
-+    };
-+
-+...
diff --git a/target/linux/mediatek/patches-5.15/860-v6.7-07-ASoC-mediatek-mt7986-drop-the-remove-callback-of-mt7.patch b/target/linux/mediatek/patches-5.15/860-v6.7-07-ASoC-mediatek-mt7986-drop-the-remove-callback-of-mt7.patch
deleted file mode 100644
index 413db8233f0517..00000000000000
--- a/target/linux/mediatek/patches-5.15/860-v6.7-07-ASoC-mediatek-mt7986-drop-the-remove-callback-of-mt7.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From f3f0934e5c7b9c16e0cb2435be3555382e6293ad Mon Sep 17 00:00:00 2001
-From: Maso Huang <maso.huang@mediatek.com>
-Date: Tue, 24 Oct 2023 11:50:17 +0800
-Subject: [PATCH 7/9] ASoC: mediatek: mt7986: drop the remove callback of
- mt7986_wm8960
-
-Drop the remove callback of mt7986_wm8960.
-
-Signed-off-by: Maso Huang <maso.huang@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20231024035019.11732-2-maso.huang@mediatek.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- sound/soc/mediatek/mt7986/mt7986-wm8960.c | 10 ----------
- 1 file changed, 10 deletions(-)
-
---- a/sound/soc/mediatek/mt7986/mt7986-wm8960.c
-+++ b/sound/soc/mediatek/mt7986/mt7986-wm8960.c
-@@ -163,15 +163,6 @@ err_of_node_put:
- 	return ret;
- }
- 
--static void mt7986_wm8960_machine_remove(struct platform_device *pdev)
--{
--	struct snd_soc_card *card = platform_get_drvdata(pdev);
--	struct mt7986_wm8960_priv *priv = snd_soc_card_get_drvdata(card);
--
--	of_node_put(priv->codec_node);
--	of_node_put(priv->platform_node);
--}
--
- static const struct of_device_id mt7986_wm8960_machine_dt_match[] = {
- 	{.compatible = "mediatek,mt7986-wm8960-sound"},
- 	{ /* sentinel */ }
-@@ -184,7 +175,6 @@ static struct platform_driver mt7986_wm8
- 		.of_match_table = mt7986_wm8960_machine_dt_match,
- 	},
- 	.probe = mt7986_wm8960_machine_probe,
--	.remove_new = mt7986_wm8960_machine_remove,
- };
- 
- module_platform_driver(mt7986_wm8960_machine);
diff --git a/target/linux/mediatek/patches-5.15/860-v6.7-08-ASoC-mediatek-mt7986-remove-the-mt7986_wm8960_priv-s.patch b/target/linux/mediatek/patches-5.15/860-v6.7-08-ASoC-mediatek-mt7986-remove-the-mt7986_wm8960_priv-s.patch
deleted file mode 100644
index 5c596fc49c9b58..00000000000000
--- a/target/linux/mediatek/patches-5.15/860-v6.7-08-ASoC-mediatek-mt7986-remove-the-mt7986_wm8960_priv-s.patch
+++ /dev/null
@@ -1,105 +0,0 @@
-From 98b8fb2cb4fcab1903d0baf611bf0c3f822a08dc Mon Sep 17 00:00:00 2001
-From: Maso Huang <maso.huang@mediatek.com>
-Date: Tue, 24 Oct 2023 11:50:18 +0800
-Subject: [PATCH 8/9] ASoC: mediatek: mt7986: remove the mt7986_wm8960_priv
- structure
-
-Remove the mt7986_wm8960_priv structure.
-
-Signed-off-by: Maso Huang <maso.huang@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20231024035019.11732-3-maso.huang@mediatek.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- sound/soc/mediatek/mt7986/mt7986-wm8960.c | 33 +++++++++--------------
- 1 file changed, 12 insertions(+), 21 deletions(-)
-
---- a/sound/soc/mediatek/mt7986/mt7986-wm8960.c
-+++ b/sound/soc/mediatek/mt7986/mt7986-wm8960.c
-@@ -12,11 +12,6 @@
- 
- #include "mt7986-afe-common.h"
- 
--struct mt7986_wm8960_priv {
--	struct device_node *platform_node;
--	struct device_node *codec_node;
--};
--
- static const struct snd_soc_dapm_widget mt7986_wm8960_widgets[] = {
- 	SND_SOC_DAPM_HP("Headphone", NULL),
- 	SND_SOC_DAPM_MIC("AMIC", NULL),
-@@ -92,20 +87,18 @@ static int mt7986_wm8960_machine_probe(s
- 	struct snd_soc_card *card = &mt7986_wm8960_card;
- 	struct snd_soc_dai_link *dai_link;
- 	struct device_node *platform, *codec;
--	struct mt7986_wm8960_priv *priv;
-+	struct device_node *platform_dai_node, *codec_dai_node;
- 	int ret, i;
- 
--	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
--	if (!priv)
--		return -ENOMEM;
-+	card->dev = &pdev->dev;
- 
- 	platform = of_get_child_by_name(pdev->dev.of_node, "platform");
- 
- 	if (platform) {
--		priv->platform_node = of_parse_phandle(platform, "sound-dai", 0);
-+		platform_dai_node = of_parse_phandle(platform, "sound-dai", 0);
- 		of_node_put(platform);
- 
--		if (!priv->platform_node) {
-+		if (!platform_dai_node) {
- 			dev_err(&pdev->dev, "Failed to parse platform/sound-dai property\n");
- 			return -EINVAL;
- 		}
-@@ -117,24 +110,22 @@ static int mt7986_wm8960_machine_probe(s
- 	for_each_card_prelinks(card, i, dai_link) {
- 		if (dai_link->platforms->name)
- 			continue;
--		dai_link->platforms->of_node = priv->platform_node;
-+		dai_link->platforms->of_node = platform_dai_node;
- 	}
- 
--	card->dev = &pdev->dev;
--
- 	codec = of_get_child_by_name(pdev->dev.of_node, "codec");
- 
- 	if (codec) {
--		priv->codec_node = of_parse_phandle(codec, "sound-dai", 0);
-+		codec_dai_node = of_parse_phandle(codec, "sound-dai", 0);
- 		of_node_put(codec);
- 
--		if (!priv->codec_node) {
--			of_node_put(priv->platform_node);
-+		if (!codec_dai_node) {
-+			of_node_put(platform_dai_node);
- 			dev_err(&pdev->dev, "Failed to parse codec/sound-dai property\n");
- 			return -EINVAL;
- 		}
- 	} else {
--		of_node_put(priv->platform_node);
-+		of_node_put(platform_dai_node);
- 		dev_err(&pdev->dev, "Property 'codec' missing or invalid\n");
- 		return -EINVAL;
- 	}
-@@ -142,7 +133,7 @@ static int mt7986_wm8960_machine_probe(s
- 	for_each_card_prelinks(card, i, dai_link) {
- 		if (dai_link->codecs->name)
- 			continue;
--		dai_link->codecs->of_node = priv->codec_node;
-+		dai_link->codecs->of_node = codec_dai_node;
- 	}
- 
- 	ret = snd_soc_of_parse_audio_routing(card, "audio-routing");
-@@ -158,8 +149,8 @@ static int mt7986_wm8960_machine_probe(s
- 	}
- 
- err_of_node_put:
--	of_node_put(priv->codec_node);
--	of_node_put(priv->platform_node);
-+	of_node_put(platform_dai_node);
-+	of_node_put(codec_dai_node);
- 	return ret;
- }
- 
diff --git a/target/linux/mediatek/patches-5.15/860-v6.7-09-ASoC-mediatek-mt7986-add-sample-rate-checker.patch b/target/linux/mediatek/patches-5.15/860-v6.7-09-ASoC-mediatek-mt7986-add-sample-rate-checker.patch
deleted file mode 100644
index d4128deabcc4ce..00000000000000
--- a/target/linux/mediatek/patches-5.15/860-v6.7-09-ASoC-mediatek-mt7986-add-sample-rate-checker.patch
+++ /dev/null
@@ -1,49 +0,0 @@
-From 4e229f4264f4be7a6a554487714c0913ef59cf7f Mon Sep 17 00:00:00 2001
-From: Maso Huang <maso.huang@mediatek.com>
-Date: Tue, 24 Oct 2023 11:50:19 +0800
-Subject: [PATCH 9/9] ASoC: mediatek: mt7986: add sample rate checker
-
-mt7986 only supports 8/12/16/24/32/48/96/192 kHz
-
-Signed-off-by: Maso Huang <maso.huang@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20231024035019.11732-4-maso.huang@mediatek.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- sound/soc/mediatek/mt7986/mt7986-dai-etdm.c | 23 +++++++++++++++++----
- 1 file changed, 19 insertions(+), 4 deletions(-)
-
---- a/sound/soc/mediatek/mt7986/mt7986-dai-etdm.c
-+++ b/sound/soc/mediatek/mt7986/mt7986-dai-etdm.c
-@@ -237,12 +237,27 @@ static int mtk_dai_etdm_hw_params(struct
- 				  struct snd_pcm_hw_params *params,
- 				  struct snd_soc_dai *dai)
- {
-+	unsigned int rate = params_rate(params);
- 	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
- 
--	mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_PLAYBACK);
--	mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_CAPTURE);
--
--	return 0;
-+	switch (rate) {
-+	case 8000:
-+	case 12000:
-+	case 16000:
-+	case 24000:
-+	case 32000:
-+	case 48000:
-+	case 96000:
-+	case 192000:
-+		mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_PLAYBACK);
-+		mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_CAPTURE);
-+		return 0;
-+	default:
-+		dev_err(afe->dev,
-+			"Sample rate %d invalid. Supported rates: 8/12/16/24/32/48/96/192 kHz\n",
-+			rate);
-+		return -EINVAL;
-+	}
- }
- 
- static int mtk_dai_etdm_trigger(struct snd_pcm_substream *substream, int cmd,
diff --git a/target/linux/mediatek/patches-5.15/861-pending-10-ASoC-mediatek-mt7986-silence-error-in-case-of-EPROBE.patch b/target/linux/mediatek/patches-5.15/861-pending-10-ASoC-mediatek-mt7986-silence-error-in-case-of-EPROBE.patch
deleted file mode 100644
index a40c249257c513..00000000000000
--- a/target/linux/mediatek/patches-5.15/861-pending-10-ASoC-mediatek-mt7986-silence-error-in-case-of-EPROBE.patch
+++ /dev/null
@@ -1,26 +0,0 @@
-From e4cde335d1771863a60b6931e51357b8470e85c4 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Sun, 10 Dec 2023 22:41:39 +0000
-Subject: [PATCH] ASoC: mediatek: mt7986: silence error in case of
- -EPROBE_DEFER
-
-If probe is defered no error should be printed. Mute it.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- sound/soc/mediatek/mt7986/mt7986-wm8960.c | 4 +++-
- 1 file changed, 3 insertions(+), 1 deletion(-)
-
---- a/sound/soc/mediatek/mt7986/mt7986-wm8960.c
-+++ b/sound/soc/mediatek/mt7986/mt7986-wm8960.c
-@@ -144,7 +144,9 @@ static int mt7986_wm8960_machine_probe(s
- 
- 	ret = devm_snd_soc_register_card(&pdev->dev, card);
- 	if (ret) {
--		dev_err(&pdev->dev, "%s snd_soc_register_card fail: %d\n", __func__, ret);
-+		if (ret != -EPROBE_DEFER)
-+			dev_err(&pdev->dev, "%s snd_soc_register_card fail: %d\n", __func__, ret);
-+
- 		goto err_of_node_put;
- 	}
- 
diff --git a/target/linux/mediatek/patches-5.15/862-arm64-dts-mt7986-add-afe.patch b/target/linux/mediatek/patches-5.15/862-arm64-dts-mt7986-add-afe.patch
deleted file mode 100644
index b31710fe69405f..00000000000000
--- a/target/linux/mediatek/patches-5.15/862-arm64-dts-mt7986-add-afe.patch
+++ /dev/null
@@ -1,40 +0,0 @@
-From 1c09b694a1e9378931085e77d834a4d9786a5356 Mon Sep 17 00:00:00 2001
-From: Maso Huang <maso.huang@mediatek.com>
-Date: Thu, 7 Sep 2023 10:54:37 +0800
-Subject: [PATCH] arm64: dts: mt7986: add afe
-
----
- arch/arm64/boot/dts/mediatek/mt7986a.dtsi     | 23 +++++++++++
- 1 files changed, 23 insertions(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-@@ -248,6 +248,28 @@
- 			status = "disabled";
- 		};
- 
-+		afe: audio-controller@11210000 {
-+			compatible = "mediatek,mt7986-afe";
-+			reg = <0 0x11210000 0 0x9000>;
-+			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&infracfg CLK_INFRA_AUD_BUS_CK>,
-+				 <&infracfg CLK_INFRA_AUD_26M_CK>,
-+				 <&infracfg CLK_INFRA_AUD_L_CK>,
-+				 <&infracfg CLK_INFRA_AUD_AUD_CK>,
-+				 <&infracfg CLK_INFRA_AUD_EG2_CK>;
-+			clock-names = "aud_bus_ck",
-+				      "aud_26m_ck",
-+				      "aud_l_ck",
-+				      "aud_aud_ck",
-+				      "aud_eg2_ck";
-+			assigned-clocks = <&topckgen CLK_TOP_A1SYS_SEL>,
-+					  <&topckgen CLK_TOP_AUD_L_SEL>,
-+					  <&topckgen CLK_TOP_A_TUNER_SEL>;
-+			assigned-clock-parents = <&topckgen CLK_TOP_APLL2_D4>,
-+						 <&apmixedsys CLK_APMIXED_APLL2>,
-+						 <&topckgen CLK_TOP_APLL2_D4>;
-+		};
-+
- 		pwm: pwm@10048000 {
- 			compatible = "mediatek,mt7986-pwm";
- 			reg = <0 0x10048000 0 0x1000>;
diff --git a/target/linux/mediatek/patches-5.15/863-arm64-dts-mt7986-add-sound-wm8960.patch b/target/linux/mediatek/patches-5.15/863-arm64-dts-mt7986-add-sound-wm8960.patch
deleted file mode 100644
index 15e30dec56cf42..00000000000000
--- a/target/linux/mediatek/patches-5.15/863-arm64-dts-mt7986-add-sound-wm8960.patch
+++ /dev/null
@@ -1,61 +0,0 @@
-From 1c09b694a1e9378931085e77d834a4d9786a5356 Mon Sep 17 00:00:00 2001
-From: Maso Huang <maso.huang@mediatek.com>
-Date: Thu, 7 Sep 2023 10:54:37 +0800
-Subject: [PATCH] arm64: dts: mt7986: add sound wm8960
-
----
- .../dts/mediatek/mt7986a-rfb-spim-nand.dts    | 39 +++++++++++++++++++
- 1 files changed, 39 insertions(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts
-@@ -4,6 +4,35 @@
- 
- / {
- 	compatible = "mediatek,mt7986a-rfb-snand";
-+
-+	sound_wm8960 {
-+		compatible = "mediatek,mt7986-wm8960-sound";
-+		audio-routing = "Headphone", "HP_L",
-+				"Headphone", "HP_R",
-+				"LINPUT1", "AMIC",
-+				"RINPUT1", "AMIC";
-+
-+		status = "okay";
-+
-+		platform {
-+			sound-dai = <&afe>;
-+		};
-+
-+		codec {
-+			sound-dai = <&wm8960>;
-+		};
-+	};
-+};
-+
-+&i2c0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&i2c_pins>;
-+	status = "okay";
-+
-+	wm8960: wm8960@1a {
-+		compatible = "wlf,wm8960";
-+		reg = <0x1a>;
-+	};
- };
- 
- &spi0 {
-@@ -50,3 +79,13 @@
- &wifi {
- 	mediatek,mtd-eeprom = <&factory 0>;
- };
-+
-+&pio {
-+	i2c_pins: i2c-pins-3-4 {
-+		mux {
-+			function = "i2c";
-+			groups = "i2c";
-+		};
-+	};
-+};
-+
diff --git a/target/linux/mediatek/patches-5.15/864-arm64-dts-mt7986-add-sound-overlay-for-bpi-r3.patch b/target/linux/mediatek/patches-5.15/864-arm64-dts-mt7986-add-sound-overlay-for-bpi-r3.patch
deleted file mode 100644
index 4fc12bf40298ec..00000000000000
--- a/target/linux/mediatek/patches-5.15/864-arm64-dts-mt7986-add-sound-overlay-for-bpi-r3.patch
+++ /dev/null
@@ -1,65 +0,0 @@
---- /dev/null
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-respeaker-2mics.dtso
-@@ -0,0 +1,62 @@
-+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-+/*
-+ * Copyright (C) 2023 MediaTek Inc.
-+ * Author: Maso Huang <Maso.Huang@mediatek.com>
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
-+
-+	fragment@0 {
-+		target-path = "/";
-+		__overlay__ {
-+			sound_wm8960 {
-+				compatible = "mediatek,mt7986-wm8960-sound";
-+				audio-routing = "Headphone", "HP_L",
-+					"Headphone", "HP_R",
-+					"LINPUT1", "AMIC",
-+					"RINPUT1", "AMIC";
-+
-+				status = "okay";
-+
-+				platform {
-+					sound-dai = <&afe>;
-+				};
-+
-+				codec {
-+					sound-dai = <&wm8960>;
-+				};
-+			};
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&i2c0>;
-+		__overlay__ {
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&i2c_pins>;
-+			clock-frequency = <400000>;
-+			status = "okay";
-+
-+			wm8960: wm8960@1a {
-+				compatible = "wlf,wm8960";
-+				reg = <0x1a>;
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&pio>;
-+		__overlay__ {
-+			i2c_pins: i2c-pins-3-4 {
-+				mux {
-+					function = "i2c";
-+					groups = "i2c";
-+				};
-+			};
-+		};
-+	};
-+};
diff --git a/target/linux/mediatek/patches-5.15/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch b/target/linux/mediatek/patches-5.15/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch
deleted file mode 100644
index f779c1e0473ab2..00000000000000
--- a/target/linux/mediatek/patches-5.15/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch
+++ /dev/null
@@ -1,65 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -318,7 +318,7 @@
- 	/* Attention: GPIO 90 is used to switch between PCIe@1,0 and
- 	 * SATA functions. i.e. output-high: PCIe, output-low: SATA
- 	 */
--	asm_sel {
-+	asmsel: asm_sel {
- 		gpio-hog;
- 		gpios = <90 GPIO_ACTIVE_HIGH>;
- 		output-high;
---- /dev/null
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-sata.dtso
-@@ -0,0 +1,31 @@
-+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-+
-+#include <dt-bindings/gpio/gpio.h>
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "bananapi,bpi-r64", "mediatek,mt7622";
-+
-+	fragment@0 {
-+		target = <&asmsel>;
-+		__overlay__ {
-+			gpios = <90 GPIO_ACTIVE_LOW>;
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&sata>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&sata_phy>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+};
---- /dev/null
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-pcie1.dtso
-@@ -0,0 +1,17 @@
-+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-+
-+#include <dt-bindings/gpio/gpio.h>
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "bananapi,bpi-r64", "mediatek,mt7622";
-+
-+	fragment@0 {
-+		target = <&asmsel>;
-+		__overlay__ {
-+			gpios = <90 GPIO_ACTIVE_HIGH>;
-+		};
-+	};
-+};
diff --git a/target/linux/mediatek/patches-5.15/901-arm-add-cmdline-override.patch b/target/linux/mediatek/patches-5.15/901-arm-add-cmdline-override.patch
deleted file mode 100644
index 54901f5549ef46..00000000000000
--- a/target/linux/mediatek/patches-5.15/901-arm-add-cmdline-override.patch
+++ /dev/null
@@ -1,54 +0,0 @@
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -1730,6 +1730,14 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
- 
- endchoice
- 
-+config CMDLINE_OVERRIDE
-+	bool "Use alternative cmdline from device tree"
-+	help
-+	  Some bootloaders may have uneditable bootargs. While CMDLINE_FORCE can
-+	  be used, this is not a good option for kernels that are shared across
-+	  devices. This setting enables using "chosen/cmdline-override" as the
-+	  cmdline if it exists in the device tree.
-+
- config CMDLINE
- 	string "Default kernel command string"
- 	default ""
---- a/drivers/of/fdt.c
-+++ b/drivers/of/fdt.c
-@@ -1162,6 +1162,17 @@ int __init early_init_dt_scan_chosen(uns
- 	if (p != NULL && l > 0)
- 		strlcat(data, p, min_t(int, strlen(data) + (int)l, COMMAND_LINE_SIZE));
- 
-+	/* CONFIG_CMDLINE_OVERRIDE is used to fallback to a different
-+	 * device tree option of chosen/bootargs-override. This is
-+	 * helpful on boards where u-boot sets bootargs, and is unable
-+	 * to be modified.
-+	 */
-+#ifdef CONFIG_CMDLINE_OVERRIDE
-+	p = of_get_flat_dt_prop(node, "bootargs-override", &l);
-+	if (p != NULL && l > 0)
-+		strlcpy(data, p, min((int)l, COMMAND_LINE_SIZE));
-+#endif
-+
- 	/*
- 	 * CONFIG_CMDLINE is meant to be a default in case nothing else
- 	 * managed to set the command line, unless CONFIG_CMDLINE_FORCE
---- a/arch/arm64/Kconfig
-+++ b/arch/arm64/Kconfig
-@@ -2059,6 +2059,14 @@ config CMDLINE_FORCE
- 
- endchoice
- 
-+config CMDLINE_OVERRIDE
-+	bool "Use alternative cmdline from device tree"
-+	help
-+	  Some bootloaders may have uneditable bootargs. While CMDLINE_FORCE can
-+	  be used, this is not a good option for kernels that are shared across
-+	  devices. This setting enables using "chosen/cmdline-override" as the
-+	  cmdline if it exists in the device tree.
-+
- config EFI_STUB
- 	bool
- 
diff --git a/target/linux/mediatek/patches-5.15/910-dts-mt7622-bpi-r64-wifi-eeprom.patch b/target/linux/mediatek/patches-5.15/910-dts-mt7622-bpi-r64-wifi-eeprom.patch
deleted file mode 100644
index 2a863aecf93665..00000000000000
--- a/target/linux/mediatek/patches-5.15/910-dts-mt7622-bpi-r64-wifi-eeprom.patch
+++ /dev/null
@@ -1,31 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -645,5 +645,28 @@
- };
- 
- &wmac {
-+	mediatek,eeprom-data = <0x22760500	0x0		0x0		0x0
-+				0x0		0x0		0x0		0x0
-+				0x0		0x0		0x0		0x0
-+				0x0		0x44000020	0x0		0x10002000
-+				0x4400		0x4000000	0x0		0x0
-+				0x200000b3	0x40b6c3c3	0x26000000	0x41c42600
-+				0x41c4		0x26000000	0xc0c52600	0x0
-+				0x0		0x0		0x0		0x0
-+				0x0		0x0		0x0		0x0
-+				0x0		0x0		0x0		0x0
-+				0x0		0x0		0x0		0x0
-+				0x0		0x0		0x0		0xc6c6
-+				0xc3c3c2c1	0xc300c3	0x818181	0x83c1c182
-+				0x83838382	0x0		0x0		0x0
-+				0x0		0x0		0x0		0x0
-+				0x84002e00	0x90000087	0x8a000000	0x0
-+				0x0		0x0		0x0		0x0
-+				0x0		0x0		0x0		0x0
-+				0xb000009	0x0		0x0		0x0
-+				0x0		0x0		0x0		0x0
-+				0x0		0x0		0x0		0x0
-+				0x0		0x0		0x0		0x7707>;
-+
- 	status = "okay";
- };
diff --git a/target/linux/mediatek/patches-5.15/920-v5.16-watchdog-mtk-add-disable_wdt_extrst-support.patch b/target/linux/mediatek/patches-5.15/920-v5.16-watchdog-mtk-add-disable_wdt_extrst-support.patch
deleted file mode 100644
index d9379721fb8a58..00000000000000
--- a/target/linux/mediatek/patches-5.15/920-v5.16-watchdog-mtk-add-disable_wdt_extrst-support.patch
+++ /dev/null
@@ -1,50 +0,0 @@
-From 59b0f51335644ee603260faaa4298c0115fb7187 Mon Sep 17 00:00:00 2001
-From: Fengquan Chen <Fengquan.Chen@mediatek.com>
-Date: Tue, 14 Sep 2021 20:34:54 +0800
-Subject: [PATCH] watchdog: mtk: add disable_wdt_extrst support
-
-In some cases, we may need watchdog just to trigger an
-internal soc reset without sending any output signal.
-
-Provide a disable_wdt_extrst parameter for configuration.
-We can disable or enable it just by configuring dts.
-
-Signed-off-by: Fengquan Chen <fengquan.chen@mediatek.com>
-Reviewed-by: Guenter Roeck <linux@roeck-us.net>
-Link: https://lore.kernel.org/r/20210914123454.32603-3-Fengquan.Chen@mediatek.com
-Signed-off-by: Guenter Roeck <linux@roeck-us.net>
-Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
----
- drivers/watchdog/mtk_wdt.c | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/drivers/watchdog/mtk_wdt.c
-+++ b/drivers/watchdog/mtk_wdt.c
-@@ -65,6 +65,7 @@ struct mtk_wdt_dev {
- 	void __iomem *wdt_base;
- 	spinlock_t lock; /* protects WDT_SWSYSRST reg */
- 	struct reset_controller_dev rcdev;
-+	bool disable_wdt_extrst;
- };
- 
- struct mtk_wdt_data {
-@@ -256,6 +257,8 @@ static int mtk_wdt_start(struct watchdog
- 		reg |= (WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN);
- 	else
- 		reg &= ~(WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN);
-+	if (mtk_wdt->disable_wdt_extrst)
-+		reg &= ~WDT_MODE_EXRST_EN;
- 	reg |= (WDT_MODE_EN | WDT_MODE_KEY);
- 	iowrite32(reg, wdt_base + WDT_MODE);
- 
-@@ -381,6 +384,10 @@ static int mtk_wdt_probe(struct platform
- 		if (err)
- 			return err;
- 	}
-+
-+	mtk_wdt->disable_wdt_extrst =
-+		of_property_read_bool(dev->of_node, "mediatek,disable-extrst");
-+
- 	return 0;
- }
- 
diff --git a/target/linux/mediatek/patches-5.15/921-v5.19-watchdog-mtk_wdt-mt7986-Add-toprgu-reset-controller.patch b/target/linux/mediatek/patches-5.15/921-v5.19-watchdog-mtk_wdt-mt7986-Add-toprgu-reset-controller.patch
deleted file mode 100644
index 96fb215f76c04e..00000000000000
--- a/target/linux/mediatek/patches-5.15/921-v5.19-watchdog-mtk_wdt-mt7986-Add-toprgu-reset-controller.patch
+++ /dev/null
@@ -1,49 +0,0 @@
-From 711a5b25bac95dcd1111521ed71693330e74a926 Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Wed, 5 Jan 2022 18:04:56 +0800
-Subject: [PATCH] watchdog: mtk_wdt: mt7986: Add toprgu reset controller
- support
-
-Besides watchdog, the mt7986 toprgu module also provides software reset
-functionality for various peripheral subsystems
-(eg, ethernet, pcie, and connectivity)
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
-Reviewed-by: Guenter Roeck <linux@roeck-us.net>
-Link: https://lore.kernel.org/r/20220105100456.7126-3-sam.shih@mediatek.com
-Signed-off-by: Guenter Roeck <linux@roeck-us.net>
-Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
----
- drivers/watchdog/mtk_wdt.c | 6 ++++++
- 1 file changed, 6 insertions(+)
-
---- a/drivers/watchdog/mtk_wdt.c
-+++ b/drivers/watchdog/mtk_wdt.c
-@@ -10,6 +10,7 @@
-  */
- 
- #include <dt-bindings/reset-controller/mt2712-resets.h>
-+#include <dt-bindings/reset/mt7986-resets.h>
- #include <dt-bindings/reset-controller/mt8183-resets.h>
- #include <dt-bindings/reset-controller/mt8192-resets.h>
- #include <dt-bindings/reset/mt8195-resets.h>
-@@ -76,6 +77,10 @@ static const struct mtk_wdt_data mt2712_
- 	.toprgu_sw_rst_num = MT2712_TOPRGU_SW_RST_NUM,
- };
- 
-+static const struct mtk_wdt_data mt7986_data = {
-+	.toprgu_sw_rst_num = MT7986_TOPRGU_SW_RST_NUM,
-+};
-+
- static const struct mtk_wdt_data mt8183_data = {
- 	.toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM,
- };
-@@ -418,6 +423,7 @@ static int mtk_wdt_resume(struct device
- static const struct of_device_id mtk_wdt_dt_ids[] = {
- 	{ .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data },
- 	{ .compatible = "mediatek,mt6589-wdt" },
-+	{ .compatible = "mediatek,mt7986-wdt", .data = &mt7986_data },
- 	{ .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data },
- 	{ .compatible = "mediatek,mt8192-wdt", .data = &mt8192_data },
- 	{ .compatible = "mediatek,mt8195-wdt", .data = &mt8195_data },
diff --git a/target/linux/mediatek/patches-5.15/922-v6.1-PCI-mediatek-gen3-change-driver-name-to-mtk-pcie-gen.patch b/target/linux/mediatek/patches-5.15/922-v6.1-PCI-mediatek-gen3-change-driver-name-to-mtk-pcie-gen.patch
deleted file mode 100644
index f026f5573ce177..00000000000000
--- a/target/linux/mediatek/patches-5.15/922-v6.1-PCI-mediatek-gen3-change-driver-name-to-mtk-pcie-gen.patch
+++ /dev/null
@@ -1,20 +0,0 @@
-From: Felix Fietkau <nbd@nbd.name>
-Date: Wed, 4 May 2022 12:03:42 +0200
-Subject: [PATCH] PCI: mediatek-gen3: change driver name to mtk-pcie-gen3
-
-This allows it to coexist with the other mtk pcie driver in the same kernel
-
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
-
---- a/drivers/pci/controller/pcie-mediatek-gen3.c
-+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
-@@ -1031,7 +1031,7 @@ static struct platform_driver mtk_pcie_d
- 	.probe = mtk_pcie_probe,
- 	.remove = mtk_pcie_remove,
- 	.driver = {
--		.name = "mtk-pcie",
-+		.name = "mtk-pcie-gen3",
- 		.of_match_table = mtk_pcie_of_match,
- 		.pm = &mtk_pcie_pm_ops,
- 	},
diff --git a/target/linux/mediatek/patches-5.15/930-spi-mt65xx-enable-sel-clk.patch b/target/linux/mediatek/patches-5.15/930-spi-mt65xx-enable-sel-clk.patch
deleted file mode 100644
index ebb6c060b54c65..00000000000000
--- a/target/linux/mediatek/patches-5.15/930-spi-mt65xx-enable-sel-clk.patch
+++ /dev/null
@@ -1,29 +0,0 @@
---- a/drivers/spi/spi-mt65xx.c
-+++ b/drivers/spi/spi-mt65xx.c
-@@ -1231,10 +1231,16 @@ static int mtk_spi_probe(struct platform
- 		goto err_disable_spi_hclk;
- 	}
- 
-+	ret = clk_prepare_enable(mdata->sel_clk);
-+	if (ret < 0) {
-+		dev_err(&pdev->dev, "failed to enable sel_clk (%d)\n", ret);
-+		goto err_disable_spi_clk;
-+	}
-+
- 	ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk);
- 	if (ret < 0) {
- 		dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret);
--		goto err_disable_spi_clk;
-+		goto err_disable_spi_sel_clk;
- 	}
- 
- 	mdata->spi_clk_hz = clk_get_rate(mdata->spi_clk);
-@@ -1285,6 +1291,8 @@ static int mtk_spi_probe(struct platform
- 
- err_disable_runtime_pm:
- 	pm_runtime_disable(&pdev->dev);
-+err_disable_spi_sel_clk:
-+	clk_disable_unprepare(mdata->sel_clk);
- err_disable_spi_clk:
- 	clk_disable_unprepare(mdata->spi_clk);
- err_disable_spi_hclk:
diff --git a/target/linux/mediatek/patches-5.15/940-net-ethernet-mtk_wed-rename-mtk_wed_get_memory_regio.patch b/target/linux/mediatek/patches-5.15/940-net-ethernet-mtk_wed-rename-mtk_wed_get_memory_regio.patch
deleted file mode 100644
index 30be53518ac19c..00000000000000
--- a/target/linux/mediatek/patches-5.15/940-net-ethernet-mtk_wed-rename-mtk_wed_get_memory_regio.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From 3cf212c4ce6cd72c09bc47f35f539ba0afd4d106 Mon Sep 17 00:00:00 2001
-Message-Id: <3cf212c4ce6cd72c09bc47f35f539ba0afd4d106.1678716918.git.lorenzo@kernel.org>
-From: Lorenzo Bianconi <lorenzo@kernel.org>
-Date: Sun, 12 Mar 2023 16:40:31 +0100
-Subject: [PATCH net-next 1/2] net: ethernet: mtk_wed: rename
- mtk_wed_get_memory_region in mtk_wed_get_reserved_memory_region
-
-This is a preliminary patch to move wed ilm/dlm and cpuboot properties in
-dedicated dts nodes.
-
-Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
----
- drivers/net/ethernet/mediatek/mtk_wed_mcu.c | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
---- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
-+++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
-@@ -234,8 +234,8 @@ int mtk_wed_mcu_msg_update(struct mtk_we
- }
- 
- static int
--mtk_wed_get_memory_region(struct mtk_wed_hw *hw, int index,
--			  struct mtk_wed_wo_memory_region *region)
-+mtk_wed_get_reserved_memory_region(struct mtk_wed_hw *hw, int index,
-+				   struct mtk_wed_wo_memory_region *region)
- {
- 	struct reserved_mem *rmem;
- 	struct device_node *np;
-@@ -321,7 +321,7 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
- 		if (index < 0)
- 			continue;
- 
--		ret = mtk_wed_get_memory_region(wo->hw, index, &mem_region[i]);
-+		ret = mtk_wed_get_reserved_memory_region(wo->hw, index, &mem_region[i]);
- 		if (ret)
- 			return ret;
- 	}
diff --git a/target/linux/mediatek/patches-5.15/941-arm64-dts-mt7986-move-cpuboot-in-a-dedicated-node.patch b/target/linux/mediatek/patches-5.15/941-arm64-dts-mt7986-move-cpuboot-in-a-dedicated-node.patch
deleted file mode 100644
index 3ba485346c7938..00000000000000
--- a/target/linux/mediatek/patches-5.15/941-arm64-dts-mt7986-move-cpuboot-in-a-dedicated-node.patch
+++ /dev/null
@@ -1,66 +0,0 @@
-From 247e566e3459481f1fa98733534bfed767e18b42 Mon Sep 17 00:00:00 2001
-Message-Id: <247e566e3459481f1fa98733534bfed767e18b42.1678620342.git.lorenzo@kernel.org>
-From: Lorenzo Bianconi <lorenzo@kernel.org>
-Date: Sat, 11 Mar 2023 16:32:41 +0100
-Subject: [PATCH net-next] arm64: dts: mt7986: move cpuboot in a dedicated node
-
-Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
----
- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 21 +++++++++++----------
- 1 file changed, 11 insertions(+), 10 deletions(-)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-@@ -121,12 +121,6 @@
- 			reg = <0 0x151f8000 0 0x2000>;
- 			no-map;
- 		};
--
--		wo_boot: wo-boot@15194000 {
--			reg = <0 0x15194000 0 0x1000>;
--			no-map;
--		};
--
- 	};
- 
- 	timer {
-@@ -540,10 +534,11 @@
- 			interrupt-parent = <&gic>;
- 			interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
- 			memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>,
--					<&wo_data>, <&wo_boot>;
-+					<&wo_data>;
- 			memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
--					      "wo-data", "wo-boot";
-+					      "wo-data";
- 			mediatek,wo-ccif = <&wo_ccif0>;
-+			mediatek,wo-cpuboot = <&wo_cpuboot>;
- 		};
- 
- 		wed1: wed@15011000 {
-@@ -553,10 +548,11 @@
- 			interrupt-parent = <&gic>;
- 			interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
- 			memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>,
--					<&wo_data>, <&wo_boot>;
-+					<&wo_data>;
- 			memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
--					      "wo-data", "wo-boot";
-+					      "wo-data";
- 			mediatek,wo-ccif = <&wo_ccif1>;
-+			mediatek,wo-cpuboot = <&wo_cpuboot>;
- 		};
- 
- 		wo_ccif0: syscon@151a5000 {
-@@ -573,6 +569,11 @@
- 			interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
- 		};
- 
-+		wo_cpuboot: syscon@15194000 {
-+			compatible = "mediatek,mt7986-wo-cpuboot", "syscon";
-+			reg = <0 0x15194000 0 0x1000>;
-+		};
-+
- 		eth: ethernet@15100000 {
- 			compatible = "mediatek,mt7986-eth";
- 			reg = <0 0x15100000 0 0x80000>;
diff --git a/target/linux/mediatek/patches-5.15/942-net-ethernet-mtk_wed-move-cpuboot-in-a-dedicated-dts.patch b/target/linux/mediatek/patches-5.15/942-net-ethernet-mtk_wed-move-cpuboot-in-a-dedicated-dts.patch
deleted file mode 100644
index b4bea2087b3d80..00000000000000
--- a/target/linux/mediatek/patches-5.15/942-net-ethernet-mtk_wed-move-cpuboot-in-a-dedicated-dts.patch
+++ /dev/null
@@ -1,81 +0,0 @@
-From f292d1bf83ec160bef2532b58aa08f5b71041923 Mon Sep 17 00:00:00 2001
-Message-Id: <f292d1bf83ec160bef2532b58aa08f5b71041923.1678716918.git.lorenzo@kernel.org>
-In-Reply-To: <3cf212c4ce6cd72c09bc47f35f539ba0afd4d106.1678716918.git.lorenzo@kernel.org>
-References: <3cf212c4ce6cd72c09bc47f35f539ba0afd4d106.1678716918.git.lorenzo@kernel.org>
-From: Lorenzo Bianconi <lorenzo@kernel.org>
-Date: Sat, 11 Mar 2023 18:13:04 +0100
-Subject: [PATCH net-next 2/2] net: ethernet: mtk_wed: move cpuboot in a
- dedicated dts node
-
-Since the cpuboot memory region is not part of the RAM SoC, move cpuboot
-in a deidicated syscon node.
-This patch helps to keep backward-compatibility with older version of
-uboot codebase where we have a limit of 8 reserved-memory dts child
-nodes.
-Keep backward-compatibility with older dts version where cpuboot was
-defined as reserved-memory child node.
-
-Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
----
- drivers/net/ethernet/mediatek/mtk_wed_mcu.c | 34 +++++++++++++++++----
- drivers/net/ethernet/mediatek/mtk_wed_wo.h  |  3 +-
- 2 files changed, 30 insertions(+), 7 deletions(-)
-
---- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
-+++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
-@@ -34,12 +34,23 @@ static struct mtk_wed_wo_memory_region m
- 
- static u32 wo_r32(struct mtk_wed_wo *wo, u32 reg)
- {
--	return readl(mem_region[MTK_WED_WO_REGION_BOOT].addr + reg);
-+	u32 val;
-+
-+	if (!wo->boot_regmap)
-+		return readl(mem_region[MTK_WED_WO_REGION_BOOT].addr + reg);
-+
-+	if (regmap_read(wo->boot_regmap, reg, &val))
-+		val = ~0;
-+
-+	return val;
- }
- 
- static void wo_w32(struct mtk_wed_wo *wo, u32 reg, u32 val)
- {
--	writel(val, mem_region[MTK_WED_WO_REGION_BOOT].addr + reg);
-+	if (wo->boot_regmap)
-+		regmap_write(wo->boot_regmap, reg, val);
-+	else
-+		writel(val, mem_region[MTK_WED_WO_REGION_BOOT].addr + reg);
- }
- 
- static struct sk_buff *
-@@ -313,6 +324,9 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
- 	u32 val, boot_cr;
- 	int ret, i;
- 
-+	wo->boot_regmap = syscon_regmap_lookup_by_phandle(wo->hw->node,
-+							  "mediatek,wo-cpuboot");
-+
- 	/* load firmware region metadata */
- 	for (i = 0; i < ARRAY_SIZE(mem_region); i++) {
- 		int index = of_property_match_string(wo->hw->node,
-@@ -321,6 +335,9 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
- 		if (index < 0)
- 			continue;
- 
-+		if (index == MTK_WED_WO_REGION_BOOT && !IS_ERR(wo->boot_regmap))
-+			continue;
-+
- 		ret = mtk_wed_get_reserved_memory_region(wo->hw, index, &mem_region[i]);
- 		if (ret)
- 			return ret;
---- a/drivers/net/ethernet/mediatek/mtk_wed_wo.h
-+++ b/drivers/net/ethernet/mediatek/mtk_wed_wo.h
-@@ -231,6 +231,7 @@ struct mtk_wed_wo_queue {
- struct mtk_wed_wo {
- 	struct mtk_wed_hw *hw;
- 
-+	struct regmap *boot_regmap;
- 	struct mtk_wed_wo_queue q_tx;
- 	struct mtk_wed_wo_queue q_rx;
- 
diff --git a/target/linux/mediatek/patches-5.15/943-net-ethernet-mtk_wed-move-ilm-a-dedicated-dts-node.patch b/target/linux/mediatek/patches-5.15/943-net-ethernet-mtk_wed-move-ilm-a-dedicated-dts-node.patch
deleted file mode 100644
index b4ba5b0d2df4be..00000000000000
--- a/target/linux/mediatek/patches-5.15/943-net-ethernet-mtk_wed-move-ilm-a-dedicated-dts-node.patch
+++ /dev/null
@@ -1,86 +0,0 @@
-From f3565e6c2276411275e707a5442d3f69cc111273 Mon Sep 17 00:00:00 2001
-Message-Id: <f3565e6c2276411275e707a5442d3f69cc111273.1678718888.git.lorenzo@kernel.org>
-From: Lorenzo Bianconi <lorenzo@kernel.org>
-Date: Sun, 12 Mar 2023 18:51:47 +0100
-Subject: [PATCH net-next 1/3] net: ethernet: mtk_wed: move ilm a dedicated dts
- node
-
-Since the ilm memory region is not part of the RAM SoC, move ilm in a
-deidicated syscon node.
-This patch helps to keep backward-compatibility with older version of
-uboot codebase where we have a limit of 8 reserved-memory dts child
-nodes.
-Keep backward-compatibility with older dts version where ilm was defined
-as reserved-memory child node.
-
-Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
----
- drivers/net/ethernet/mediatek/mtk_wed_mcu.c | 55 ++++++++++++++++++---
- 1 file changed, 49 insertions(+), 6 deletions(-)
-
---- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
-+++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
-@@ -316,6 +316,39 @@ next:
- }
- 
- static int
-+mtk_wed_mcu_load_ilm(struct mtk_wed_wo *wo)
-+{
-+	struct mtk_wed_wo_memory_region *ilm_region;
-+	struct resource res;
-+	struct device_node *np;
-+	int ret;
-+
-+	np = of_parse_phandle(wo->hw->node, "mediatek,wo-ilm", 0);
-+	if (!np)
-+		return 0;
-+
-+	ret = of_address_to_resource(np, 0, &res);
-+	of_node_put(np);
-+
-+	if (ret < 0)
-+		return ret;
-+
-+	ilm_region = &mem_region[MTK_WED_WO_REGION_ILM];
-+	ilm_region->phy_addr = res.start;
-+	ilm_region->size = resource_size(&res);
-+	ilm_region->addr = devm_ioremap(wo->hw->dev, res.start,
-+					resource_size(&res));
-+
-+	if (!IS_ERR(ilm_region->addr))
-+		return 0;
-+
-+	ret = PTR_ERR(ilm_region->addr);
-+	ilm_region->addr = NULL;
-+
-+	return ret;
-+}
-+
-+static int
- mtk_wed_mcu_load_firmware(struct mtk_wed_wo *wo)
- {
- 	const struct mtk_wed_fw_trailer *trailer;
-@@ -324,14 +357,20 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
- 	u32 val, boot_cr;
- 	int ret, i;
- 
-+	mtk_wed_mcu_load_ilm(wo);
- 	wo->boot_regmap = syscon_regmap_lookup_by_phandle(wo->hw->node,
- 							  "mediatek,wo-cpuboot");
- 
- 	/* load firmware region metadata */
- 	for (i = 0; i < ARRAY_SIZE(mem_region); i++) {
--		int index = of_property_match_string(wo->hw->node,
--						     "memory-region-names",
--						     mem_region[i].name);
-+		int index;
-+
-+		if (mem_region[i].addr)
-+			continue;
-+
-+		index = of_property_match_string(wo->hw->node,
-+						 "memory-region-names",
-+						 mem_region[i].name);
- 		if (index < 0)
- 			continue;
- 
diff --git a/target/linux/mediatek/patches-5.15/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch b/target/linux/mediatek/patches-5.15/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch
deleted file mode 100644
index c92fcd43cee97b..00000000000000
--- a/target/linux/mediatek/patches-5.15/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch
+++ /dev/null
@@ -1,57 +0,0 @@
-From b74ba226be2c45091b93bd49192bdd6d2178729e Mon Sep 17 00:00:00 2001
-Message-Id: <b74ba226be2c45091b93bd49192bdd6d2178729e.1678718888.git.lorenzo@kernel.org>
-In-Reply-To: <f3565e6c2276411275e707a5442d3f69cc111273.1678718888.git.lorenzo@kernel.org>
-References: <f3565e6c2276411275e707a5442d3f69cc111273.1678718888.git.lorenzo@kernel.org>
-From: Lorenzo Bianconi <lorenzo@kernel.org>
-Date: Mon, 13 Mar 2023 15:45:16 +0100
-Subject: [PATCH net-next 3/3] net: ethernet: mtk_wed: move dlm a dedicated dts
- node
-
-Since the dlm memory region is not part of the RAM SoC, move dlm in a
-deidicated syscon node.
-This patch helps to keep backward-compatibility with older version of
-uboot codebase where we have a limit of 8 reserved-memory dts child
-nodes.
-Keep backward-compatibility with older dts version where dlm was defined
-as reserved-memory child node.
-
-Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
----
- drivers/net/ethernet/mediatek/mtk_wed.c | 19 +++++++++++++++++++
- 1 file changed, 19 insertions(+)
-
---- a/drivers/net/ethernet/mediatek/mtk_wed.c
-+++ b/drivers/net/ethernet/mediatek/mtk_wed.c
-@@ -1320,6 +1320,24 @@ mtk_wed_rro_alloc(struct mtk_wed_device
- 	struct device_node *np;
- 	int index;
- 
-+	np = of_parse_phandle(dev->hw->node, "mediatek,wo-dlm", 0);
-+	if (np) {
-+		struct resource res;
-+		int ret;
-+
-+		ret = of_address_to_resource(np, 0, &res);
-+		of_node_put(np);
-+
-+		if (ret < 0)
-+			return ret;
-+
-+		dev->rro.miod_phys = res.start;
-+		goto out;
-+	}
-+
-+	/* For backward compatibility, we need to check if DLM
-+	 * node is defined through reserved memory property.
-+	 */
- 	index = of_property_match_string(dev->hw->node, "memory-region-names",
- 					 "wo-dlm");
- 	if (index < 0)
-@@ -1336,6 +1354,7 @@ mtk_wed_rro_alloc(struct mtk_wed_device
- 		return -ENODEV;
- 
- 	dev->rro.miod_phys = rmem->base;
-+out:
- 	dev->rro.fdbk_phys = MTK_WED_MIOD_COUNT + dev->rro.miod_phys;
- 
- 	return mtk_wed_rro_ring_alloc(dev, &dev->rro.ring,
diff --git a/target/linux/mediatek/patches-5.15/945-arm64-dts-mt7986-move-ilm-in-a-dedicated-node.patch b/target/linux/mediatek/patches-5.15/945-arm64-dts-mt7986-move-ilm-in-a-dedicated-node.patch
deleted file mode 100644
index 0ba9bd7cf0b8a4..00000000000000
--- a/target/linux/mediatek/patches-5.15/945-arm64-dts-mt7986-move-ilm-in-a-dedicated-node.patch
+++ /dev/null
@@ -1,83 +0,0 @@
-From 01561065af5bf1d2a4244896d897e3a1eafbcd46 Mon Sep 17 00:00:00 2001
-Message-Id: <01561065af5bf1d2a4244896d897e3a1eafbcd46.1678717704.git.lorenzo@kernel.org>
-From: Lorenzo Bianconi <lorenzo@kernel.org>
-Date: Mon, 13 Mar 2023 15:10:56 +0100
-Subject: [PATCH net-next] arm64: dts: mt7986: move ilm in a dedicated node
-
-Since the ilm memory region is not part of the RAM SoC, move ilm in a
-deidicated syscon node.
-This patch helps to keep backward-compatibility with older version of
-uboot codebase where we have a limit of 8 reserved-memory dts child
-nodes.
-
-Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
----
- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 34 +++++++++++------------
- 1 file changed, 16 insertions(+), 18 deletions(-)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-@@ -97,16 +97,6 @@
- 			no-map;
- 		};
- 
--		wo_ilm0: wo-ilm@151e0000 {
--			reg = <0 0x151e0000 0 0x8000>;
--			no-map;
--		};
--
--		wo_ilm1: wo-ilm@151f0000 {
--			reg = <0 0x151f0000 0 0x8000>;
--			no-map;
--		};
--
- 		wo_data: wo-data@4fd80000 {
- 			reg = <0 0x4fd80000 0 0x240000>;
- 			no-map;
-@@ -533,11 +523,10 @@
- 			reg = <0 0x15010000 0 0x1000>;
- 			interrupt-parent = <&gic>;
- 			interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
--			memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>,
--					<&wo_data>;
--			memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
--					      "wo-data";
-+			memory-region = <&wo_emi0>, <&wo_dlm0>, <&wo_data>;
-+			memory-region-names = "wo-emi", "wo-dlm", "wo-data";
- 			mediatek,wo-ccif = <&wo_ccif0>;
-+			mediatek,wo-ilm = <&wo_ilm0>;
- 			mediatek,wo-cpuboot = <&wo_cpuboot>;
- 		};
- 
-@@ -547,11 +536,10 @@
- 			reg = <0 0x15011000 0 0x1000>;
- 			interrupt-parent = <&gic>;
- 			interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
--			memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>,
--					<&wo_data>;
--			memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
--					      "wo-data";
-+			memory-region = <&wo_emi1>, <&wo_dlm1>, <&wo_data>;
-+			memory-region-names = "wo-emi", "wo-dlm", "wo-data";
- 			mediatek,wo-ccif = <&wo_ccif1>;
-+			mediatek,wo-ilm = <&wo_ilm1>;
- 			mediatek,wo-cpuboot = <&wo_cpuboot>;
- 		};
- 
-@@ -569,6 +557,16 @@
- 			interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
- 		};
- 
-+		wo_ilm0: syscon@151e0000 {
-+			compatible = "mediatek,mt7986-wo-ilm", "syscon";
-+			reg = <0 0x151e0000 0 0x8000>;
-+		};
-+
-+		wo_ilm1: syscon@151f0000 {
-+			compatible = "mediatek,mt7986-wo-ilm", "syscon";
-+			reg = <0 0x151f0000 0 0x8000>;
-+		};
-+
- 		wo_cpuboot: syscon@15194000 {
- 			compatible = "mediatek,mt7986-wo-cpuboot", "syscon";
- 			reg = <0 0x15194000 0 0x1000>;
diff --git a/target/linux/mediatek/patches-5.15/946-arm64-dts-mt7986-move-dlm-in-a-dedicated-node.patch b/target/linux/mediatek/patches-5.15/946-arm64-dts-mt7986-move-dlm-in-a-dedicated-node.patch
deleted file mode 100644
index 90b2bb91a2709d..00000000000000
--- a/target/linux/mediatek/patches-5.15/946-arm64-dts-mt7986-move-dlm-in-a-dedicated-node.patch
+++ /dev/null
@@ -1,81 +0,0 @@
-From 9f76be683a8ec498563c294bc1cc279468058302 Mon Sep 17 00:00:00 2001
-Message-Id: <9f76be683a8ec498563c294bc1cc279468058302.1678719283.git.lorenzo@kernel.org>
-From: Lorenzo Bianconi <lorenzo@kernel.org>
-Date: Mon, 13 Mar 2023 15:53:30 +0100
-Subject: [PATCH net-next] arm64: dts: mt7986: move dlm in a dedicated node
-
-Since the dlm memory region is not part of the RAM SoC, move dlm in a
-deidicated syscon node.
-This patch helps to keep backward-compatibility with older version of
-uboot codebase where we have a limit of 8 reserved-memory dts child
-nodes.
-
-Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
----
- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 30 ++++++++++++-----------
- 1 file changed, 16 insertions(+), 14 deletions(-)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-@@ -101,16 +101,6 @@
- 			reg = <0 0x4fd80000 0 0x240000>;
- 			no-map;
- 		};
--
--		wo_dlm0: wo-dlm@151e8000 {
--			reg = <0 0x151e8000 0 0x2000>;
--			no-map;
--		};
--
--		wo_dlm1: wo-dlm@151f8000 {
--			reg = <0 0x151f8000 0 0x2000>;
--			no-map;
--		};
- 	};
- 
- 	timer {
-@@ -523,10 +513,11 @@
- 			reg = <0 0x15010000 0 0x1000>;
- 			interrupt-parent = <&gic>;
- 			interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
--			memory-region = <&wo_emi0>, <&wo_dlm0>, <&wo_data>;
--			memory-region-names = "wo-emi", "wo-dlm", "wo-data";
-+			memory-region = <&wo_emi0>, <&wo_data>;
-+			memory-region-names = "wo-emi", "wo-data";
- 			mediatek,wo-ccif = <&wo_ccif0>;
- 			mediatek,wo-ilm = <&wo_ilm0>;
-+			mediatek,wo-dlm = <&wo_dlm0>;
- 			mediatek,wo-cpuboot = <&wo_cpuboot>;
- 		};
- 
-@@ -536,10 +527,11 @@
- 			reg = <0 0x15011000 0 0x1000>;
- 			interrupt-parent = <&gic>;
- 			interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
--			memory-region = <&wo_emi1>, <&wo_dlm1>, <&wo_data>;
--			memory-region-names = "wo-emi", "wo-dlm", "wo-data";
-+			memory-region = <&wo_emi1>, <&wo_data>;
-+			memory-region-names = "wo-emi", "wo-data";
- 			mediatek,wo-ccif = <&wo_ccif1>;
- 			mediatek,wo-ilm = <&wo_ilm1>;
-+			mediatek,wo-dlm = <&wo_dlm1>;
- 			mediatek,wo-cpuboot = <&wo_cpuboot>;
- 		};
- 
-@@ -567,6 +559,16 @@
- 			reg = <0 0x151f0000 0 0x8000>;
- 		};
- 
-+		wo_dlm0: syscon@151e8000 {
-+			compatible = "mediatek,mt7986-wo-dlm", "syscon";
-+			reg = <0 0x151e8000 0 0x2000>;
-+		};
-+
-+		wo_dlm1: syscon@151f8000 {
-+			compatible = "mediatek,mt7986-wo-dlm", "syscon";
-+			reg = <0 0x151f8000 0 0x2000>;
-+		};
-+
- 		wo_cpuboot: syscon@15194000 {
- 			compatible = "mediatek,mt7986-wo-cpuboot", "syscon";
- 			reg = <0 0x15194000 0 0x1000>;
diff --git a/target/linux/mediatek/patches-5.15/950-smartrg-i2c-led-driver.patch b/target/linux/mediatek/patches-5.15/950-smartrg-i2c-led-driver.patch
deleted file mode 100644
index 9f7b4ef338e32a..00000000000000
--- a/target/linux/mediatek/patches-5.15/950-smartrg-i2c-led-driver.patch
+++ /dev/null
@@ -1,34 +0,0 @@
----
- drivers/leds/Kconfig  |   10 ++++++++++
- drivers/leds/Makefile |    1 +
- 2 files changed, 11 insertions(+)
-
---- a/drivers/leds/Kconfig
-+++ b/drivers/leds/Kconfig
-@@ -877,6 +877,16 @@ source "drivers/leds/blink/Kconfig"
- comment "Flash and Torch LED drivers"
- source "drivers/leds/flash/Kconfig"
- 
-+config LEDS_SMARTRG_LED
-+	tristate "LED support for Adtran SmartRG"
-+	depends on LEDS_CLASS && I2C && OF
-+	help
-+	  This option enables support for the Adtran SmartRG platform
-+	  system LED driver.
-+
-+	  To compile this driver as a module, choose M here: the module
-+	  will be called leds-smartrg-system.
-+
- comment "LED Triggers"
- source "drivers/leds/trigger/Kconfig"
- 
---- a/drivers/leds/Makefile
-+++ b/drivers/leds/Makefile
-@@ -77,6 +77,7 @@ obj-$(CONFIG_LEDS_PWM)			+= leds-pwm.o
- obj-$(CONFIG_LEDS_REGULATOR)		+= leds-regulator.o
- obj-$(CONFIG_LEDS_S3C24XX)		+= leds-s3c24xx.o
- obj-$(CONFIG_LEDS_SC27XX_BLTC)		+= leds-sc27xx-bltc.o
-+obj-$(CONFIG_LEDS_SMARTRG_LED)		+= leds-smartrg-system.o
- obj-$(CONFIG_LEDS_SUNFIRE)		+= leds-sunfire.o
- obj-$(CONFIG_LEDS_SYSCON)		+= leds-syscon.o
- obj-$(CONFIG_LEDS_TCA6507)		+= leds-tca6507.o
diff --git a/target/linux/mediatek/patches-5.15/961-net-ethernet-mediatek-split-tx-and-rx-fields-in-mtk_.patch b/target/linux/mediatek/patches-5.15/961-net-ethernet-mediatek-split-tx-and-rx-fields-in-mtk_.patch
deleted file mode 100644
index b0c20ab5450a55..00000000000000
--- a/target/linux/mediatek/patches-5.15/961-net-ethernet-mediatek-split-tx-and-rx-fields-in-mtk_.patch
+++ /dev/null
@@ -1,599 +0,0 @@
-From: Lorenzo Bianconi <lorenzo@kernel.org>
-Date: Thu, 2 Nov 2023 16:47:07 +0100
-Subject: [PATCH net-next 1/2] net: ethernet: mediatek: split tx and rx fields
- in mtk_soc_data struct
-
-Split tx and rx fields in mtk_soc_data struct. This is a preliminary
-patch to roll back to QDMA for MT7986 SoC in order to fix a hw hang
-if the device receives a corrupted packet.
-
-Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
----
- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 210 ++++++++++++--------
- drivers/net/ethernet/mediatek/mtk_eth_soc.h |  29 +--
- 2 files changed, 139 insertions(+), 100 deletions(-)
-
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1239,7 +1239,7 @@ static int mtk_init_fq_dma(struct mtk_et
- 		eth->scratch_ring = eth->sram_base;
- 	else
- 		eth->scratch_ring = dma_alloc_coherent(eth->dma_dev,
--						       cnt * soc->txrx.txd_size,
-+						       cnt * soc->tx.desc_size,
- 						       &eth->phy_scratch_ring,
- 						       GFP_KERNEL);
- 	if (unlikely(!eth->scratch_ring))
-@@ -1255,16 +1255,16 @@ static int mtk_init_fq_dma(struct mtk_et
- 	if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr)))
- 		return -ENOMEM;
- 
--	phy_ring_tail = eth->phy_scratch_ring + soc->txrx.txd_size * (cnt - 1);
-+	phy_ring_tail = eth->phy_scratch_ring + soc->tx.desc_size * (cnt - 1);
- 
- 	for (i = 0; i < cnt; i++) {
- 		struct mtk_tx_dma_v2 *txd;
- 
--		txd = eth->scratch_ring + i * soc->txrx.txd_size;
-+		txd = eth->scratch_ring + i * soc->tx.desc_size;
- 		txd->txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE;
- 		if (i < cnt - 1)
- 			txd->txd2 = eth->phy_scratch_ring +
--				    (i + 1) * soc->txrx.txd_size;
-+				    (i + 1) * soc->tx.desc_size;
- 
- 		txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE);
- 		txd->txd4 = 0;
-@@ -1511,7 +1511,7 @@ static int mtk_tx_map(struct sk_buff *sk
- 	if (itxd == ring->last_free)
- 		return -ENOMEM;
- 
--	itx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size);
-+	itx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->tx.desc_size);
- 	memset(itx_buf, 0, sizeof(*itx_buf));
- 
- 	txd_info.addr = dma_map_single(eth->dma_dev, skb->data, txd_info.size,
-@@ -1552,7 +1552,7 @@ static int mtk_tx_map(struct sk_buff *sk
- 
- 			memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info));
- 			txd_info.size = min_t(unsigned int, frag_size,
--					      soc->txrx.dma_max_len);
-+					      soc->tx.dma_max_len);
- 			txd_info.qid = queue;
- 			txd_info.last = i == skb_shinfo(skb)->nr_frags - 1 &&
- 					!(frag_size - txd_info.size);
-@@ -1565,7 +1565,7 @@ static int mtk_tx_map(struct sk_buff *sk
- 			mtk_tx_set_dma_desc(dev, txd, &txd_info);
- 
- 			tx_buf = mtk_desc_to_tx_buf(ring, txd,
--						    soc->txrx.txd_size);
-+						    soc->tx.desc_size);
- 			if (new_desc)
- 				memset(tx_buf, 0, sizeof(*tx_buf));
- 			tx_buf->data = (void *)MTK_DMA_DUMMY_DESC;
-@@ -1608,7 +1608,7 @@ static int mtk_tx_map(struct sk_buff *sk
- 	} else {
- 		int next_idx;
- 
--		next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->txrx.txd_size),
-+		next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->tx.desc_size),
- 					 ring->dma_size);
- 		mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0);
- 	}
-@@ -1617,7 +1617,7 @@ static int mtk_tx_map(struct sk_buff *sk
- 
- err_dma:
- 	do {
--		tx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size);
-+		tx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->tx.desc_size);
- 
- 		/* unmap dma */
- 		mtk_tx_unmap(eth, tx_buf, false);
-@@ -1642,7 +1642,7 @@ static int mtk_cal_txd_req(struct mtk_et
- 		for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
- 			frag = &skb_shinfo(skb)->frags[i];
- 			nfrags += DIV_ROUND_UP(skb_frag_size(frag),
--					       eth->soc->txrx.dma_max_len);
-+					       eth->soc->tx.dma_max_len);
- 		}
- 	} else {
- 		nfrags += skb_shinfo(skb)->nr_frags;
-@@ -1783,7 +1783,7 @@ static struct mtk_rx_ring *mtk_get_rx_ri
- 
- 		ring = &eth->rx_ring[i];
- 		idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
--		rxd = ring->dma + idx * eth->soc->txrx.rxd_size;
-+		rxd = ring->dma + idx * eth->soc->rx.desc_size;
- 		if (rxd->rxd2 & RX_DMA_DONE) {
- 			ring->calc_idx_update = true;
- 			return ring;
-@@ -1951,7 +1951,7 @@ static int mtk_xdp_submit_frame(struct m
- 	}
- 	htxd = txd;
- 
--	tx_buf = mtk_desc_to_tx_buf(ring, txd, soc->txrx.txd_size);
-+	tx_buf = mtk_desc_to_tx_buf(ring, txd, soc->tx.desc_size);
- 	memset(tx_buf, 0, sizeof(*tx_buf));
- 	htx_buf = tx_buf;
- 
-@@ -1971,7 +1971,7 @@ static int mtk_xdp_submit_frame(struct m
- 				goto unmap;
- 
- 			tx_buf = mtk_desc_to_tx_buf(ring, txd,
--						    soc->txrx.txd_size);
-+						    soc->tx.desc_size);
- 			memset(tx_buf, 0, sizeof(*tx_buf));
- 			n_desc++;
- 		}
-@@ -2008,7 +2008,7 @@ static int mtk_xdp_submit_frame(struct m
- 	} else {
- 		int idx;
- 
--		idx = txd_to_idx(ring, txd, soc->txrx.txd_size);
-+		idx = txd_to_idx(ring, txd, soc->tx.desc_size);
- 		mtk_w32(eth, NEXT_DESP_IDX(idx, ring->dma_size),
- 			MT7628_TX_CTX_IDX0);
- 	}
-@@ -2020,7 +2020,7 @@ static int mtk_xdp_submit_frame(struct m
- unmap:
- 	while (htxd != txd) {
- 		txd_pdma = qdma_to_pdma(ring, htxd);
--		tx_buf = mtk_desc_to_tx_buf(ring, htxd, soc->txrx.txd_size);
-+		tx_buf = mtk_desc_to_tx_buf(ring, htxd, soc->tx.desc_size);
- 		mtk_tx_unmap(eth, tx_buf, false);
- 
- 		htxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
-@@ -2148,7 +2148,7 @@ static int mtk_poll_rx(struct napi_struc
- 			goto rx_done;
- 
- 		idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
--		rxd = ring->dma + idx * eth->soc->txrx.rxd_size;
-+		rxd = ring->dma + idx * eth->soc->rx.desc_size;
- 		data = ring->data[idx];
- 
- 		if (!mtk_rx_get_desc(eth, &trxd, rxd))
-@@ -2283,7 +2283,7 @@ static int mtk_poll_rx(struct napi_struc
- 			rxdcsum = &trxd.rxd4;
- 		}
- 
--		if (*rxdcsum & eth->soc->txrx.rx_dma_l4_valid)
-+		if (*rxdcsum & eth->soc->rx.dma_l4_valid)
- 			skb->ip_summed = CHECKSUM_UNNECESSARY;
- 		else
- 			skb_checksum_none_assert(skb);
-@@ -2405,7 +2405,7 @@ static int mtk_poll_tx_qdma(struct mtk_e
- 			break;
- 
- 		tx_buf = mtk_desc_to_tx_buf(ring, desc,
--					    eth->soc->txrx.txd_size);
-+					    eth->soc->tx.desc_size);
- 		if (!tx_buf->data)
- 			break;
- 
-@@ -2453,7 +2453,7 @@ static int mtk_poll_tx_pdma(struct mtk_e
- 		}
- 		mtk_tx_unmap(eth, tx_buf, true);
- 
--		desc = ring->dma + cpu * eth->soc->txrx.txd_size;
-+		desc = ring->dma + cpu * eth->soc->tx.desc_size;
- 		ring->last_free = desc;
- 		atomic_inc(&ring->free_count);
- 
-@@ -2542,7 +2542,7 @@ static int mtk_napi_rx(struct napi_struc
- 	do {
- 		int rx_done;
- 
--		mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask,
-+		mtk_w32(eth, eth->soc->rx.irq_done_mask,
- 			reg_map->pdma.irq_status);
- 		rx_done = mtk_poll_rx(napi, budget - rx_done_total, eth);
- 		rx_done_total += rx_done;
-@@ -2558,10 +2558,10 @@ static int mtk_napi_rx(struct napi_struc
- 			return budget;
- 
- 	} while (mtk_r32(eth, reg_map->pdma.irq_status) &
--		 eth->soc->txrx.rx_irq_done_mask);
-+		 eth->soc->rx.irq_done_mask);
- 
- 	if (napi_complete_done(napi, rx_done_total))
--		mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask);
-+		mtk_rx_irq_enable(eth, eth->soc->rx.irq_done_mask);
- 
- 	return rx_done_total;
- }
-@@ -2570,7 +2570,7 @@ static int mtk_tx_alloc(struct mtk_eth *
- {
- 	const struct mtk_soc_data *soc = eth->soc;
- 	struct mtk_tx_ring *ring = &eth->tx_ring;
--	int i, sz = soc->txrx.txd_size;
-+	int i, sz = soc->tx.desc_size;
- 	struct mtk_tx_dma_v2 *txd;
- 	int ring_size;
- 	u32 ofs, val;
-@@ -2693,14 +2693,14 @@ static void mtk_tx_clean(struct mtk_eth
- 	}
- 	if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && ring->dma) {
- 		dma_free_coherent(eth->dma_dev,
--				  ring->dma_size * soc->txrx.txd_size,
-+				  ring->dma_size * soc->tx.desc_size,
- 				  ring->dma, ring->phys);
- 		ring->dma = NULL;
- 	}
- 
- 	if (ring->dma_pdma) {
- 		dma_free_coherent(eth->dma_dev,
--				  ring->dma_size * soc->txrx.txd_size,
-+				  ring->dma_size * soc->tx.desc_size,
- 				  ring->dma_pdma, ring->phys_pdma);
- 		ring->dma_pdma = NULL;
- 	}
-@@ -2755,15 +2755,15 @@ static int mtk_rx_alloc(struct mtk_eth *
- 	if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM) ||
- 	    rx_flag != MTK_RX_FLAGS_NORMAL) {
- 		ring->dma = dma_alloc_coherent(eth->dma_dev,
--					       rx_dma_size * eth->soc->txrx.rxd_size,
--					       &ring->phys, GFP_KERNEL);
-+				rx_dma_size * eth->soc->rx.desc_size,
-+				&ring->phys, GFP_KERNEL);
- 	} else {
- 		struct mtk_tx_ring *tx_ring = &eth->tx_ring;
- 
- 		ring->dma = tx_ring->dma + tx_ring_size *
--			    eth->soc->txrx.txd_size * (ring_no + 1);
-+			    eth->soc->tx.desc_size * (ring_no + 1);
- 		ring->phys = tx_ring->phys + tx_ring_size *
--			     eth->soc->txrx.txd_size * (ring_no + 1);
-+			     eth->soc->tx.desc_size * (ring_no + 1);
- 	}
- 
- 	if (!ring->dma)
-@@ -2774,7 +2774,7 @@ static int mtk_rx_alloc(struct mtk_eth *
- 		dma_addr_t dma_addr;
- 		void *data;
- 
--		rxd = ring->dma + i * eth->soc->txrx.rxd_size;
-+		rxd = ring->dma + i * eth->soc->rx.desc_size;
- 		if (ring->page_pool) {
- 			data = mtk_page_pool_get_buff(ring->page_pool,
- 						      &dma_addr, GFP_KERNEL);
-@@ -2863,7 +2863,7 @@ static void mtk_rx_clean(struct mtk_eth
- 			if (!ring->data[i])
- 				continue;
- 
--			rxd = ring->dma + i * eth->soc->txrx.rxd_size;
-+			rxd = ring->dma + i * eth->soc->rx.desc_size;
- 			if (!rxd->rxd1)
- 				continue;
- 
-@@ -2880,7 +2880,7 @@ static void mtk_rx_clean(struct mtk_eth
- 
- 	if (!in_sram && ring->dma) {
- 		dma_free_coherent(eth->dma_dev,
--				  ring->dma_size * eth->soc->txrx.rxd_size,
-+				  ring->dma_size * eth->soc->rx.desc_size,
- 				  ring->dma, ring->phys);
- 		ring->dma = NULL;
- 	}
-@@ -3243,7 +3243,7 @@ static void mtk_dma_free(struct mtk_eth
- 			netdev_reset_queue(eth->netdev[i]);
- 	if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && eth->scratch_ring) {
- 		dma_free_coherent(eth->dma_dev,
--				  MTK_QDMA_RING_SIZE * soc->txrx.txd_size,
-+				  MTK_QDMA_RING_SIZE * soc->tx.desc_size,
- 				  eth->scratch_ring, eth->phy_scratch_ring);
- 		eth->scratch_ring = NULL;
- 		eth->phy_scratch_ring = 0;
-@@ -3293,7 +3293,7 @@ static irqreturn_t mtk_handle_irq_rx(int
- 
- 	eth->rx_events++;
- 	if (likely(napi_schedule_prep(&eth->rx_napi))) {
--		mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask);
-+		mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask);
- 		__napi_schedule(&eth->rx_napi);
- 	}
- 
-@@ -3319,9 +3319,9 @@ static irqreturn_t mtk_handle_irq(int ir
- 	const struct mtk_reg_map *reg_map = eth->soc->reg_map;
- 
- 	if (mtk_r32(eth, reg_map->pdma.irq_mask) &
--	    eth->soc->txrx.rx_irq_done_mask) {
-+	    eth->soc->rx.irq_done_mask) {
- 		if (mtk_r32(eth, reg_map->pdma.irq_status) &
--		    eth->soc->txrx.rx_irq_done_mask)
-+		    eth->soc->rx.irq_done_mask)
- 			mtk_handle_irq_rx(irq, _eth);
- 	}
- 	if (mtk_r32(eth, reg_map->tx_irq_mask) & MTK_TX_DONE_INT) {
-@@ -3339,10 +3339,10 @@ static void mtk_poll_controller(struct n
- 	struct mtk_eth *eth = mac->hw;
- 
- 	mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
--	mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask);
-+	mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask);
- 	mtk_handle_irq_rx(eth->irq[2], dev);
- 	mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
--	mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask);
-+	mtk_rx_irq_enable(eth, eth->soc->rx.irq_done_mask);
- }
- #endif
- 
-@@ -3507,7 +3507,7 @@ static int mtk_open(struct net_device *d
- 		napi_enable(&eth->tx_napi);
- 		napi_enable(&eth->rx_napi);
- 		mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
--		mtk_rx_irq_enable(eth, soc->txrx.rx_irq_done_mask);
-+		mtk_rx_irq_enable(eth, soc->rx.irq_done_mask);
- 		refcount_set(&eth->dma_refcnt, 1);
- 	}
- 	else
-@@ -3590,7 +3590,7 @@ static int mtk_stop(struct net_device *d
- 	mtk_gdm_config(eth, MTK_GDMA_DROP_ALL);
- 
- 	mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
--	mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask);
-+	mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask);
- 	napi_disable(&eth->tx_napi);
- 	napi_disable(&eth->rx_napi);
- 
-@@ -4066,9 +4066,9 @@ static int mtk_hw_init(struct mtk_eth *e
- 
- 	/* FE int grouping */
- 	mtk_w32(eth, MTK_TX_DONE_INT, reg_map->pdma.int_grp);
--	mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->pdma.int_grp + 4);
-+	mtk_w32(eth, eth->soc->rx.irq_done_mask, reg_map->pdma.int_grp + 4);
- 	mtk_w32(eth, MTK_TX_DONE_INT, reg_map->qdma.int_grp);
--	mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4);
-+	mtk_w32(eth, eth->soc->rx.irq_done_mask, reg_map->qdma.int_grp + 4);
- 	mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
- 
- 	if (mtk_is_netsys_v3_or_greater(eth)) {
-@@ -5165,11 +5165,15 @@ static const struct mtk_soc_data mt2701_
- 	.required_clks = MT7623_CLKS_BITMAP,
- 	.required_pctl = true,
- 	.version = 1,
--	.txrx = {
--		.txd_size = sizeof(struct mtk_tx_dma),
--		.rxd_size = sizeof(struct mtk_rx_dma),
--		.rx_irq_done_mask = MTK_RX_DONE_INT,
--		.rx_dma_l4_valid = RX_DMA_L4_VALID,
-+	.tx = {
-+		.desc_size = sizeof(struct mtk_tx_dma),
-+		.dma_max_len = MTK_TX_DMA_BUF_LEN,
-+		.dma_len_offset = 16,
-+	},
-+	.rx = {
-+		.desc_size = sizeof(struct mtk_rx_dma),
-+		.irq_done_mask = MTK_RX_DONE_INT,
-+		.dma_l4_valid = RX_DMA_L4_VALID,
- 		.dma_max_len = MTK_TX_DMA_BUF_LEN,
- 		.dma_len_offset = 16,
- 	},
-@@ -5185,11 +5189,15 @@ static const struct mtk_soc_data mt7621_
- 	.offload_version = 1,
- 	.hash_offset = 2,
- 	.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
--	.txrx = {
--		.txd_size = sizeof(struct mtk_tx_dma),
--		.rxd_size = sizeof(struct mtk_rx_dma),
--		.rx_irq_done_mask = MTK_RX_DONE_INT,
--		.rx_dma_l4_valid = RX_DMA_L4_VALID,
-+	.tx = {
-+		.desc_size = sizeof(struct mtk_tx_dma),
-+		.dma_max_len = MTK_TX_DMA_BUF_LEN,
-+		.dma_len_offset = 16,
-+	},
-+	.rx = {
-+		.desc_size = sizeof(struct mtk_rx_dma),
-+		.irq_done_mask = MTK_RX_DONE_INT,
-+		.dma_l4_valid = RX_DMA_L4_VALID,
- 		.dma_max_len = MTK_TX_DMA_BUF_LEN,
- 		.dma_len_offset = 16,
- 	},
-@@ -5207,11 +5215,15 @@ static const struct mtk_soc_data mt7622_
- 	.hash_offset = 2,
- 	.has_accounting = true,
- 	.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
--	.txrx = {
--		.txd_size = sizeof(struct mtk_tx_dma),
--		.rxd_size = sizeof(struct mtk_rx_dma),
--		.rx_irq_done_mask = MTK_RX_DONE_INT,
--		.rx_dma_l4_valid = RX_DMA_L4_VALID,
-+	.tx = {
-+		.desc_size = sizeof(struct mtk_tx_dma),
-+		.dma_max_len = MTK_TX_DMA_BUF_LEN,
-+		.dma_len_offset = 16,
-+	},
-+	.rx = {
-+		.desc_size = sizeof(struct mtk_rx_dma),
-+		.irq_done_mask = MTK_RX_DONE_INT,
-+		.dma_l4_valid = RX_DMA_L4_VALID,
- 		.dma_max_len = MTK_TX_DMA_BUF_LEN,
- 		.dma_len_offset = 16,
- 	},
-@@ -5228,11 +5240,15 @@ static const struct mtk_soc_data mt7623_
- 	.hash_offset = 2,
- 	.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
- 	.disable_pll_modes = true,
--	.txrx = {
--		.txd_size = sizeof(struct mtk_tx_dma),
--		.rxd_size = sizeof(struct mtk_rx_dma),
--		.rx_irq_done_mask = MTK_RX_DONE_INT,
--		.rx_dma_l4_valid = RX_DMA_L4_VALID,
-+	.tx = {
-+		.desc_size = sizeof(struct mtk_tx_dma),
-+		.dma_max_len = MTK_TX_DMA_BUF_LEN,
-+		.dma_len_offset = 16,
-+	},
-+	.rx = {
-+		.desc_size = sizeof(struct mtk_rx_dma),
-+		.irq_done_mask = MTK_RX_DONE_INT,
-+		.dma_l4_valid = RX_DMA_L4_VALID,
- 		.dma_max_len = MTK_TX_DMA_BUF_LEN,
- 		.dma_len_offset = 16,
- 	},
-@@ -5247,11 +5263,15 @@ static const struct mtk_soc_data mt7629_
- 	.required_pctl = false,
- 	.has_accounting = true,
- 	.version = 1,
--	.txrx = {
--		.txd_size = sizeof(struct mtk_tx_dma),
--		.rxd_size = sizeof(struct mtk_rx_dma),
--		.rx_irq_done_mask = MTK_RX_DONE_INT,
--		.rx_dma_l4_valid = RX_DMA_L4_VALID,
-+	.tx = {
-+		.desc_size = sizeof(struct mtk_tx_dma),
-+		.dma_max_len = MTK_TX_DMA_BUF_LEN,
-+		.dma_len_offset = 16,
-+	},
-+	.rx = {
-+		.desc_size = sizeof(struct mtk_rx_dma),
-+		.irq_done_mask = MTK_RX_DONE_INT,
-+		.dma_l4_valid = RX_DMA_L4_VALID,
- 		.dma_max_len = MTK_TX_DMA_BUF_LEN,
- 		.dma_len_offset = 16,
- 	},
-@@ -5269,11 +5289,15 @@ static const struct mtk_soc_data mt7981_
- 	.hash_offset = 4,
- 	.has_accounting = true,
- 	.foe_entry_size = MTK_FOE_ENTRY_V2_SIZE,
--	.txrx = {
--		.txd_size = sizeof(struct mtk_tx_dma_v2),
--		.rxd_size = sizeof(struct mtk_rx_dma_v2),
--		.rx_irq_done_mask = MTK_RX_DONE_INT_V2,
--		.rx_dma_l4_valid = RX_DMA_L4_VALID_V2,
-+	.tx = {
-+		.desc_size = sizeof(struct mtk_tx_dma_v2),
-+		.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
-+		.dma_len_offset = 8,
-+	},
-+	.rx = {
-+		.desc_size = sizeof(struct mtk_rx_dma_v2),
-+		.irq_done_mask = MTK_RX_DONE_INT_V2,
-+		.dma_l4_valid = RX_DMA_L4_VALID_V2,
- 		.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
- 		.dma_len_offset = 8,
- 	},
-@@ -5291,11 +5315,15 @@ static const struct mtk_soc_data mt7986_
- 	.hash_offset = 4,
- 	.has_accounting = true,
- 	.foe_entry_size = MTK_FOE_ENTRY_V2_SIZE,
--	.txrx = {
--		.txd_size = sizeof(struct mtk_tx_dma_v2),
--		.rxd_size = sizeof(struct mtk_rx_dma_v2),
--		.rx_irq_done_mask = MTK_RX_DONE_INT_V2,
--		.rx_dma_l4_valid = RX_DMA_L4_VALID_V2,
-+	.tx = {
-+		.desc_size = sizeof(struct mtk_tx_dma_v2),
-+		.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
-+		.dma_len_offset = 8,
-+	},
-+	.rx = {
-+		.desc_size = sizeof(struct mtk_rx_dma_v2),
-+		.irq_done_mask = MTK_RX_DONE_INT_V2,
-+		.dma_l4_valid = RX_DMA_L4_VALID_V2,
- 		.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
- 		.dma_len_offset = 8,
- 	},
-@@ -5313,11 +5341,15 @@ static const struct mtk_soc_data mt7988_
- 	.hash_offset = 4,
- 	.has_accounting = true,
- 	.foe_entry_size = MTK_FOE_ENTRY_V3_SIZE,
--	.txrx = {
--		.txd_size = sizeof(struct mtk_tx_dma_v2),
--		.rxd_size = sizeof(struct mtk_rx_dma_v2),
--		.rx_irq_done_mask = MTK_RX_DONE_INT_V2,
--		.rx_dma_l4_valid = RX_DMA_L4_VALID_V2,
-+	.tx = {
-+		.desc_size = sizeof(struct mtk_tx_dma_v2),
-+		.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
-+		.dma_len_offset = 8,
-+	},
-+	.rx = {
-+		.desc_size = sizeof(struct mtk_rx_dma_v2),
-+		.irq_done_mask = MTK_RX_DONE_INT_V2,
-+		.dma_l4_valid = RX_DMA_L4_VALID_V2,
- 		.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
- 		.dma_len_offset = 8,
- 	},
-@@ -5330,11 +5362,15 @@ static const struct mtk_soc_data rt5350_
- 	.required_clks = MT7628_CLKS_BITMAP,
- 	.required_pctl = false,
- 	.version = 1,
--	.txrx = {
--		.txd_size = sizeof(struct mtk_tx_dma),
--		.rxd_size = sizeof(struct mtk_rx_dma),
--		.rx_irq_done_mask = MTK_RX_DONE_INT,
--		.rx_dma_l4_valid = RX_DMA_L4_VALID_PDMA,
-+	.tx = {
-+		.desc_size = sizeof(struct mtk_tx_dma),
-+		.dma_max_len = MTK_TX_DMA_BUF_LEN,
-+		.dma_len_offset = 16,
-+	},
-+	.rx = {
-+		.desc_size = sizeof(struct mtk_rx_dma),
-+		.irq_done_mask = MTK_RX_DONE_INT,
-+		.dma_l4_valid = RX_DMA_L4_VALID_PDMA,
- 		.dma_max_len = MTK_TX_DMA_BUF_LEN,
- 		.dma_len_offset = 16,
- 	},
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -326,8 +326,8 @@
- /* QDMA descriptor txd3 */
- #define TX_DMA_OWNER_CPU	BIT(31)
- #define TX_DMA_LS0		BIT(30)
--#define TX_DMA_PLEN0(x)		(((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset)
--#define TX_DMA_PLEN1(x)		((x) & eth->soc->txrx.dma_max_len)
-+#define TX_DMA_PLEN0(x)		(((x) & eth->soc->tx.dma_max_len) << eth->soc->tx.dma_len_offset)
-+#define TX_DMA_PLEN1(x)		((x) & eth->soc->tx.dma_max_len)
- #define TX_DMA_SWC		BIT(14)
- #define TX_DMA_PQID		GENMASK(3, 0)
- #define TX_DMA_ADDR64_MASK	GENMASK(3, 0)
-@@ -347,8 +347,8 @@
- /* QDMA descriptor rxd2 */
- #define RX_DMA_DONE		BIT(31)
- #define RX_DMA_LSO		BIT(30)
--#define RX_DMA_PREP_PLEN0(x)	(((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset)
--#define RX_DMA_GET_PLEN0(x)	(((x) >> eth->soc->txrx.dma_len_offset) & eth->soc->txrx.dma_max_len)
-+#define RX_DMA_PREP_PLEN0(x)	(((x) & eth->soc->rx.dma_max_len) << eth->soc->rx.dma_len_offset)
-+#define RX_DMA_GET_PLEN0(x)	(((x) >> eth->soc->rx.dma_len_offset) & eth->soc->rx.dma_max_len)
- #define RX_DMA_VTAG		BIT(15)
- #define RX_DMA_ADDR64_MASK	GENMASK(3, 0)
- #if IS_ENABLED(CONFIG_64BIT)
-@@ -1279,10 +1279,9 @@ struct mtk_reg_map {
-  * @foe_entry_size		Foe table entry size.
-  * @has_accounting		Bool indicating support for accounting of
-  *				offloaded flows.
-- * @txd_size			Tx DMA descriptor size.
-- * @rxd_size			Rx DMA descriptor size.
-- * @rx_irq_done_mask		Rx irq done register mask.
-- * @rx_dma_l4_valid		Rx DMA valid register mask.
-+ * @desc_size			Tx/Rx DMA descriptor size.
-+ * @irq_done_mask		Rx irq done register mask.
-+ * @dma_l4_valid		Rx DMA valid register mask.
-  * @dma_max_len			Max DMA tx/rx buffer length.
-  * @dma_len_offset		Tx/Rx DMA length field offset.
-  */
-@@ -1300,13 +1299,17 @@ struct mtk_soc_data {
- 	bool		has_accounting;
- 	bool		disable_pll_modes;
- 	struct {
--		u32	txd_size;
--		u32	rxd_size;
--		u32	rx_irq_done_mask;
--		u32	rx_dma_l4_valid;
-+		u32	desc_size;
- 		u32	dma_max_len;
- 		u32	dma_len_offset;
--	} txrx;
-+	} tx;
-+	struct {
-+		u32	desc_size;
-+		u32	irq_done_mask;
-+		u32	dma_l4_valid;
-+		u32	dma_max_len;
-+		u32	dma_len_offset;
-+	} rx;
- };
- 
- #define MTK_DMA_MONITOR_TIMEOUT		msecs_to_jiffies(1000)
diff --git a/target/linux/mediatek/patches-5.15/962-net-ethernet-mediatek-use-QDMA-instead-of-ADMAv2-on-.patch b/target/linux/mediatek/patches-5.15/962-net-ethernet-mediatek-use-QDMA-instead-of-ADMAv2-on-.patch
deleted file mode 100644
index dd191f7afd0996..00000000000000
--- a/target/linux/mediatek/patches-5.15/962-net-ethernet-mediatek-use-QDMA-instead-of-ADMAv2-on-.patch
+++ /dev/null
@@ -1,123 +0,0 @@
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Tue, 10 Oct 2023 21:06:43 +0200
-Subject: [PATCH net-next 2/2] net: ethernet: mediatek: use QDMA instead of
- ADMAv2 on MT7981 and MT7986
-
-ADMA is plagued by RX hangs which can't easily detected and happen upon
-receival of a corrupted package.
-Use QDMA just like on netsys v1 which is also still present and usable, and
-doesn't suffer from that problem.
-
-Co-developed-by: Lorenzo Bianconi <lorenzo@kernel.org>
-Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 46 ++++++++++-----------
- 1 file changed, 23 insertions(+), 23 deletions(-)
-
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -108,16 +108,16 @@ static const struct mtk_reg_map mt7986_r
- 	.tx_irq_mask		= 0x461c,
- 	.tx_irq_status		= 0x4618,
- 	.pdma = {
--		.rx_ptr		= 0x6100,
--		.rx_cnt_cfg	= 0x6104,
--		.pcrx_ptr	= 0x6108,
--		.glo_cfg	= 0x6204,
--		.rst_idx	= 0x6208,
--		.delay_irq	= 0x620c,
--		.irq_status	= 0x6220,
--		.irq_mask	= 0x6228,
--		.adma_rx_dbg0	= 0x6238,
--		.int_grp	= 0x6250,
-+		.rx_ptr		= 0x4100,
-+		.rx_cnt_cfg	= 0x4104,
-+		.pcrx_ptr	= 0x4108,
-+		.glo_cfg	= 0x4204,
-+		.rst_idx	= 0x4208,
-+		.delay_irq	= 0x420c,
-+		.irq_status	= 0x4220,
-+		.irq_mask	= 0x4228,
-+		.adma_rx_dbg0	= 0x4238,
-+		.int_grp	= 0x4250,
- 	},
- 	.qdma = {
- 		.qtx_cfg	= 0x4400,
-@@ -1207,7 +1207,7 @@ static bool mtk_rx_get_desc(struct mtk_e
- 	rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
- 	rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
- 	rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
--	if (mtk_is_netsys_v2_or_greater(eth)) {
-+	if (mtk_is_netsys_v3_or_greater(eth)) {
- 		rxd->rxd5 = READ_ONCE(dma_rxd->rxd5);
- 		rxd->rxd6 = READ_ONCE(dma_rxd->rxd6);
- 	}
-@@ -2155,7 +2155,7 @@ static int mtk_poll_rx(struct napi_struc
- 			break;
- 
- 		/* find out which mac the packet come from. values start at 1 */
--		if (mtk_is_netsys_v2_or_greater(eth)) {
-+		if (mtk_is_netsys_v3_or_greater(eth)) {
- 			u32 val = RX_DMA_GET_SPORT_V2(trxd.rxd5);
- 
- 			switch (val) {
-@@ -2267,7 +2267,7 @@ static int mtk_poll_rx(struct napi_struc
- 		skb->dev = netdev;
- 		bytes += skb->len;
- 
--		if (mtk_is_netsys_v2_or_greater(eth)) {
-+		if (mtk_is_netsys_v3_or_greater(eth)) {
- 			reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5);
- 			hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY;
- 			if (hash != MTK_RXD5_FOE_ENTRY)
-@@ -2809,7 +2809,7 @@ static int mtk_rx_alloc(struct mtk_eth *
- 
- 		rxd->rxd3 = 0;
- 		rxd->rxd4 = 0;
--		if (mtk_is_netsys_v2_or_greater(eth)) {
-+		if (mtk_is_netsys_v3_or_greater(eth)) {
- 			rxd->rxd5 = 0;
- 			rxd->rxd6 = 0;
- 			rxd->rxd7 = 0;
-@@ -4012,7 +4012,7 @@ static int mtk_hw_init(struct mtk_eth *e
- 	else
- 		mtk_hw_reset(eth);
- 
--	if (mtk_is_netsys_v2_or_greater(eth)) {
-+	if (mtk_is_netsys_v3_or_greater(eth)) {
- 		/* Set FE to PDMAv2 if necessary */
- 		val = mtk_r32(eth, MTK_FE_GLO_MISC);
- 		mtk_w32(eth,  val | BIT(4), MTK_FE_GLO_MISC);
-@@ -5295,11 +5295,11 @@ static const struct mtk_soc_data mt7981_
- 		.dma_len_offset = 8,
- 	},
- 	.rx = {
--		.desc_size = sizeof(struct mtk_rx_dma_v2),
--		.irq_done_mask = MTK_RX_DONE_INT_V2,
-+		.desc_size = sizeof(struct mtk_rx_dma),
-+		.irq_done_mask = MTK_RX_DONE_INT,
- 		.dma_l4_valid = RX_DMA_L4_VALID_V2,
--		.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
--		.dma_len_offset = 8,
-+		.dma_max_len = MTK_TX_DMA_BUF_LEN,
-+		.dma_len_offset = 16,
- 	},
- };
- 
-@@ -5321,11 +5321,11 @@ static const struct mtk_soc_data mt7986_
- 		.dma_len_offset = 8,
- 	},
- 	.rx = {
--		.desc_size = sizeof(struct mtk_rx_dma_v2),
--		.irq_done_mask = MTK_RX_DONE_INT_V2,
-+		.desc_size = sizeof(struct mtk_rx_dma),
-+		.irq_done_mask = MTK_RX_DONE_INT,
- 		.dma_l4_valid = RX_DMA_L4_VALID_V2,
--		.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
--		.dma_len_offset = 8,
-+		.dma_max_len = MTK_TX_DMA_BUF_LEN,
-+		.dma_len_offset = 16,
- 	},
- };
- 
diff --git a/target/linux/mediatek/patches-5.15/963-net-ethernet-mtk_eth_soc-fix-WED-wifi-reset.patch b/target/linux/mediatek/patches-5.15/963-net-ethernet-mtk_eth_soc-fix-WED-wifi-reset.patch
deleted file mode 100644
index 11b52d07ab3481..00000000000000
--- a/target/linux/mediatek/patches-5.15/963-net-ethernet-mtk_eth_soc-fix-WED-wifi-reset.patch
+++ /dev/null
@@ -1,49 +0,0 @@
-From: Felix Fietkau <nbd@nbd.name>
-Date: Thu, 18 Jan 2024 12:51:32 +0100
-Subject: [PATCH] net: ethernet: mtk_eth_soc: fix WED + wifi reset
-
-The WLAN + WED reset sequence relies on being able to receive interrupts from
-the card, in order to synchronize individual steps with the firmware.
-When WED is stopped, leave interrupts running and rely on the driver turning
-off unwanted ones.
-WED DMA also needs to be disabled before resetting.
-
-Fixes: f78cd9c783e0 ("net: ethernet: mtk_wed: update mtk_wed_stop")
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
-
---- a/drivers/net/ethernet/mediatek/mtk_wed.c
-+++ b/drivers/net/ethernet/mediatek/mtk_wed.c
-@@ -1071,13 +1071,13 @@ mtk_wed_dma_disable(struct mtk_wed_devic
- static void
- mtk_wed_stop(struct mtk_wed_device *dev)
- {
-+	mtk_wed_dma_disable(dev);
- 	mtk_wed_set_ext_int(dev, false);
- 
- 	wed_w32(dev, MTK_WED_WPDMA_INT_TRIGGER, 0);
- 	wed_w32(dev, MTK_WED_WDMA_INT_TRIGGER, 0);
- 	wdma_w32(dev, MTK_WDMA_INT_MASK, 0);
- 	wdma_w32(dev, MTK_WDMA_INT_GRP2, 0);
--	wed_w32(dev, MTK_WED_WPDMA_INT_MASK, 0);
- 
- 	if (!mtk_wed_get_rx_capa(dev))
- 		return;
-@@ -1090,7 +1090,6 @@ static void
- mtk_wed_deinit(struct mtk_wed_device *dev)
- {
- 	mtk_wed_stop(dev);
--	mtk_wed_dma_disable(dev);
- 
- 	wed_clr(dev, MTK_WED_CTRL,
- 		MTK_WED_CTRL_WDMA_INT_AGENT_EN |
-@@ -2621,9 +2620,6 @@ mtk_wed_irq_get(struct mtk_wed_device *d
- static void
- mtk_wed_irq_set_mask(struct mtk_wed_device *dev, u32 mask)
- {
--	if (!dev->running)
--		return;
--
- 	mtk_wed_set_ext_int(dev, !!mask);
- 	wed_w32(dev, MTK_WED_INT_MASK, mask);
- }
diff --git a/target/linux/mediatek/patches-6.1/020-arm64-dts-mt7986-define-3W-max-power-to-both-SFP-on-.patch b/target/linux/mediatek/patches-6.1/020-v6.7-arm64-dts-mt7986-define-3W-max-power-to-both-SFP-on-.patch
similarity index 100%
rename from target/linux/mediatek/patches-6.1/020-arm64-dts-mt7986-define-3W-max-power-to-both-SFP-on-.patch
rename to target/linux/mediatek/patches-6.1/020-v6.7-arm64-dts-mt7986-define-3W-max-power-to-both-SFP-on-.patch
diff --git a/target/linux/mediatek/patches-6.1/021-arm64-dts-mt7986-change-cooling-trips.patch b/target/linux/mediatek/patches-6.1/021-v6.7-arm64-dts-mt7986-change-cooling-trips.patch
similarity index 100%
rename from target/linux/mediatek/patches-6.1/021-arm64-dts-mt7986-change-cooling-trips.patch
rename to target/linux/mediatek/patches-6.1/021-v6.7-arm64-dts-mt7986-change-cooling-trips.patch
diff --git a/target/linux/mediatek/patches-6.1/022-arm64-dts-mt7986-change-thermal-trips-on-BPI-R3.patch b/target/linux/mediatek/patches-6.1/022-v6.7-arm64-dts-mt7986-change-thermal-trips-on-BPI-R3.patch
similarity index 100%
rename from target/linux/mediatek/patches-6.1/022-arm64-dts-mt7986-change-thermal-trips-on-BPI-R3.patch
rename to target/linux/mediatek/patches-6.1/022-v6.7-arm64-dts-mt7986-change-thermal-trips-on-BPI-R3.patch
diff --git a/target/linux/mediatek/patches-6.1/041-block-fit-partition-parser.patch b/target/linux/mediatek/patches-6.1/041-block-fit-partition-parser.patch
new file mode 100644
index 00000000000000..bb87c20a91e15e
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/041-block-fit-partition-parser.patch
@@ -0,0 +1,216 @@
+From 69357074558daf6ff24c9f58714935e9e095a865 Mon Sep 17 00:00:00 2001
+From: OpenWrt community <openwrt-devel@lists.openwrt.org>
+Date: Wed, 13 Jul 2022 13:37:33 +0200
+Subject: [PATCH] kernel: add block fit partition parser
+
+---
+ block/blk.h                     |  2 ++
+ block/partitions/Kconfig        |  7 +++++++
+ block/partitions/Makefile       |  1 +
+ block/partitions/check.h        |  3 +++
+ block/partitions/core.c         | 17 +++++++++++++++++
+ block/partitions/efi.c          |  8 ++++++++
+ block/partitions/efi.h          |  3 +++
+ block/partitions/msdos.c        | 10 ++++++++++
+ drivers/mtd/mtd_blkdevs.c       |  2 ++
+ drivers/mtd/ubi/block.c         |  3 +++
+ include/linux/msdos_partition.h |  1 +
+ 11 files changed, 57 insertions(+)
+
+--- a/block/blk.h
++++ b/block/blk.h
+@@ -414,6 +414,8 @@ void blk_free_ext_minor(unsigned int min
+ #define ADDPART_FLAG_NONE	0
+ #define ADDPART_FLAG_RAID	1
+ #define ADDPART_FLAG_WHOLEDISK	2
++#define ADDPART_FLAG_READONLY	4
++#define ADDPART_FLAG_ROOTDEV	8
+ int bdev_add_partition(struct gendisk *disk, int partno, sector_t start,
+ 		sector_t length);
+ int bdev_del_partition(struct gendisk *disk, int partno);
+--- a/block/partitions/Kconfig
++++ b/block/partitions/Kconfig
+@@ -103,6 +103,13 @@ config ATARI_PARTITION
+ 	  Say Y here if you would like to use hard disks under Linux which
+ 	  were partitioned under the Atari OS.
+ 
++config FIT_PARTITION
++	bool "Flattened-Image-Tree (FIT) partition support" if PARTITION_ADVANCED
++	default n
++	help
++	  Say Y here if your system needs to mount the filesystem part of
++	  a Flattened-Image-Tree (FIT) image commonly used with Das U-Boot.
++
+ config IBM_PARTITION
+ 	bool "IBM disk label and partition support"
+ 	depends on PARTITION_ADVANCED && S390
+--- a/block/partitions/Makefile
++++ b/block/partitions/Makefile
+@@ -8,6 +8,7 @@ obj-$(CONFIG_ACORN_PARTITION) += acorn.o
+ obj-$(CONFIG_AMIGA_PARTITION) += amiga.o
+ obj-$(CONFIG_ATARI_PARTITION) += atari.o
+ obj-$(CONFIG_AIX_PARTITION) += aix.o
++obj-$(CONFIG_FIT_PARTITION) += fit.o
+ obj-$(CONFIG_CMDLINE_PARTITION) += cmdline.o
+ obj-$(CONFIG_MAC_PARTITION) += mac.o
+ obj-$(CONFIG_LDM_PARTITION) += ldm.o
+--- a/block/partitions/check.h
++++ b/block/partitions/check.h
+@@ -57,6 +57,7 @@ int amiga_partition(struct parsed_partit
+ int atari_partition(struct parsed_partitions *state);
+ int cmdline_partition(struct parsed_partitions *state);
+ int efi_partition(struct parsed_partitions *state);
++int fit_partition(struct parsed_partitions *state);
+ int ibm_partition(struct parsed_partitions *);
+ int karma_partition(struct parsed_partitions *state);
+ int ldm_partition(struct parsed_partitions *state);
+@@ -67,3 +68,5 @@ int sgi_partition(struct parsed_partitio
+ int sun_partition(struct parsed_partitions *state);
+ int sysv68_partition(struct parsed_partitions *state);
+ int ultrix_partition(struct parsed_partitions *state);
++
++int parse_fit_partitions(struct parsed_partitions *state, u64 start_sector, u64 nr_sectors, int *slot, int add_remain);
+--- a/block/partitions/core.c
++++ b/block/partitions/core.c
+@@ -11,6 +11,9 @@
+ #include <linux/vmalloc.h>
+ #include <linux/raid/detect.h>
+ #include <linux/property.h>
++#ifdef CONFIG_FIT_PARTITION
++#include <linux/root_dev.h>
++#endif
+ 
+ #include "check.h"
+ 
+@@ -48,6 +51,9 @@ static int (*check_part[])(struct parsed
+ #ifdef CONFIG_EFI_PARTITION
+ 	efi_partition,		/* this must come before msdos */
+ #endif
++#ifdef CONFIG_FIT_PARTITION
++	fit_partition,
++#endif
+ #ifdef CONFIG_SGI_PARTITION
+ 	sgi_partition,
+ #endif
+@@ -439,6 +445,11 @@ static struct block_device *add_partitio
+ 			goto out_del;
+ 	}
+ 
++#ifdef CONFIG_FIT_PARTITION
++	if (flags & ADDPART_FLAG_READONLY)
++		bdev->bd_read_only = true;
++#endif
++
+ 	/* everything is up and running, commence */
+ 	err = xa_insert(&disk->part_tbl, partno, bdev, GFP_KERNEL);
+ 	if (err)
+@@ -631,6 +642,11 @@ static bool blk_add_partition(struct gen
+ 	    (state->parts[p].flags & ADDPART_FLAG_RAID))
+ 		md_autodetect_dev(part->bd_dev);
+ 
++#ifdef CONFIG_FIT_PARTITION
++	if ((state->parts[p].flags & ADDPART_FLAG_ROOTDEV) && ROOT_DEV == 0)
++		ROOT_DEV = part->bd_dev;
++#endif
++
+ 	return true;
+ }
+ 
+--- a/block/partitions/efi.c
++++ b/block/partitions/efi.c
+@@ -716,6 +716,9 @@ int efi_partition(struct parsed_partitio
+ 	gpt_entry *ptes = NULL;
+ 	u32 i;
+ 	unsigned ssz = queue_logical_block_size(state->disk->queue) / 512;
++#ifdef CONFIG_FIT_PARTITION
++	u32 extra_slot = 64;
++#endif
+ 
+ 	if (!find_valid_gpt(state, &gpt, &ptes) || !gpt || !ptes) {
+ 		kfree(gpt);
+@@ -749,6 +752,11 @@ int efi_partition(struct parsed_partitio
+ 				ARRAY_SIZE(ptes[i].partition_name));
+ 		utf16_le_to_7bit(ptes[i].partition_name, label_max, info->volname);
+ 		state->parts[i + 1].has_info = true;
++#ifdef CONFIG_FIT_PARTITION
++		/* If this is a U-Boot FIT volume it may have subpartitions */
++		if (!efi_guidcmp(ptes[i].partition_type_guid, PARTITION_LINUX_FIT_GUID))
++			(void) parse_fit_partitions(state, start * ssz, size * ssz, &extra_slot, 1);
++#endif
+ 	}
+ 	kfree(ptes);
+ 	kfree(gpt);
+--- a/block/partitions/efi.h
++++ b/block/partitions/efi.h
+@@ -51,6 +51,9 @@
+ #define PARTITION_LINUX_LVM_GUID \
+     EFI_GUID( 0xe6d6d379, 0xf507, 0x44c2, \
+               0xa2, 0x3c, 0x23, 0x8f, 0x2a, 0x3d, 0xf9, 0x28)
++#define PARTITION_LINUX_FIT_GUID \
++    EFI_GUID( 0xcae9be83, 0xb15f, 0x49cc, \
++              0x86, 0x3f, 0x08, 0x1b, 0x74, 0x4a, 0x2d, 0x93)
+ 
+ typedef struct _gpt_header {
+ 	__le64 signature;
+--- a/block/partitions/msdos.c
++++ b/block/partitions/msdos.c
+@@ -564,6 +564,15 @@ static void parse_minix(struct parsed_pa
+ #endif /* CONFIG_MINIX_SUBPARTITION */
+ }
+ 
++static void parse_fit_mbr(struct parsed_partitions *state,
++			  sector_t offset, sector_t size, int origin)
++{
++#ifdef CONFIG_FIT_PARTITION
++	u32 extra_slot = 64;
++	(void) parse_fit_partitions(state, offset, size, &extra_slot, 1);
++#endif /* CONFIG_FIT_PARTITION */
++}
++
+ static struct {
+ 	unsigned char id;
+ 	void (*parse)(struct parsed_partitions *, sector_t, sector_t, int);
+@@ -575,6 +584,7 @@ static struct {
+ 	{UNIXWARE_PARTITION, parse_unixware},
+ 	{SOLARIS_X86_PARTITION, parse_solaris_x86},
+ 	{NEW_SOLARIS_X86_PARTITION, parse_solaris_x86},
++	{FIT_PARTITION, parse_fit_mbr},
+ 	{0, NULL},
+ };
+ 
+--- a/drivers/mtd/mtd_blkdevs.c
++++ b/drivers/mtd/mtd_blkdevs.c
+@@ -359,7 +359,9 @@ int add_mtd_blktrans_dev(struct mtd_blkt
+ 	} else {
+ 		snprintf(gd->disk_name, sizeof(gd->disk_name),
+ 			 "%s%d", tr->name, new->devnum);
+-		gd->flags |= GENHD_FL_NO_PART;
++
++		if (!IS_ENABLED(CONFIG_FIT_PARTITION) || mtd_type_is_nand(new->mtd))
++			gd->flags |= GENHD_FL_NO_PART;
+ 	}
+ 
+ 	set_capacity(gd, ((u64)new->size * tr->blksize) >> 9);
+--- a/drivers/mtd/ubi/block.c
++++ b/drivers/mtd/ubi/block.c
+@@ -432,7 +432,9 @@ int ubiblock_create(struct ubi_volume_in
+ 		ret = -ENODEV;
+ 		goto out_cleanup_disk;
+ 	}
+-	gd->flags |= GENHD_FL_NO_PART;
++	if (!IS_ENABLED(CONFIG_FIT_PARTITION))
++		gd->flags |= GENHD_FL_NO_PART;
++
+ 	gd->private_data = dev;
+ 	sprintf(gd->disk_name, "ubiblock%d_%d", dev->ubi_num, dev->vol_id);
+ 	set_capacity(gd, disk_capacity);
+--- a/include/linux/msdos_partition.h
++++ b/include/linux/msdos_partition.h
+@@ -31,6 +31,7 @@ enum msdos_sys_ind {
+ 	LINUX_LVM_PARTITION = 0x8e,
+ 	LINUX_RAID_PARTITION = 0xfd,	/* autodetect RAID partition */
+ 
++	FIT_PARTITION = 0x2e,		/* U-Boot uImage.FIT */
+ 	SOLARIS_X86_PARTITION =	0x82,	/* also Linux swap partitions */
+ 	NEW_SOLARIS_X86_PARTITION = 0xbf,
+ 
diff --git a/target/linux/mediatek/patches-6.1/113-dts-fix-bpi64-leds-and-buttons.patch b/target/linux/mediatek/patches-6.1/113-dts-fix-bpi64-leds-and-buttons.patch
index bf1912a9163aaf..1cca6f353410f2 100644
--- a/target/linux/mediatek/patches-6.1/113-dts-fix-bpi64-leds-and-buttons.patch
+++ b/target/linux/mediatek/patches-6.1/113-dts-fix-bpi64-leds-and-buttons.patch
@@ -1,6 +1,6 @@
 --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
 +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -21,6 +21,10 @@
+@@ -21,6 +21,12 @@
  	aliases {
  		serial0 = &uart0;
  		ethernet0 = &gmac0;
@@ -8,10 +8,12 @@
 +		led-failsafe = &led_system_blue;
 +		led-running = &led_system_green;
 +		led-upgrade = &led_system_blue;
++		mmc0 = &mmc0;
++		mmc1 = &mmc1;
  	};
  
  	chosen {
-@@ -44,8 +48,8 @@
+@@ -44,8 +50,8 @@
  		compatible = "gpio-keys";
  
  		factory-key {
@@ -22,7 +24,7 @@
  			gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
  		};
  
-@@ -59,17 +63,17 @@
+@@ -59,17 +65,17 @@
  	leds {
  		compatible = "gpio-leds";
  
diff --git a/target/linux/mediatek/patches-6.1/114-dts-bpi64-disable-rtc.patch b/target/linux/mediatek/patches-6.1/114-dts-bpi64-disable-rtc.patch
index e30d9e5e12a7e6..0d324084b1ca73 100644
--- a/target/linux/mediatek/patches-6.1/114-dts-bpi64-disable-rtc.patch
+++ b/target/linux/mediatek/patches-6.1/114-dts-bpi64-disable-rtc.patch
@@ -1,6 +1,6 @@
 --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
 +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -554,12 +554,16 @@
+@@ -556,12 +556,16 @@
  	status = "okay";
  };
  
diff --git a/target/linux/mediatek/patches-6.1/115-dts-bpi64-add-snand-support.patch b/target/linux/mediatek/patches-6.1/115-dts-bpi64-add-snand-support.patch
deleted file mode 100644
index 93f87fe697f6f2..00000000000000
--- a/target/linux/mediatek/patches-6.1/115-dts-bpi64-add-snand-support.patch
+++ /dev/null
@@ -1,50 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -251,14 +251,42 @@
- 	status = "disabled";
- };
- 
--&nor_flash {
--	pinctrl-names = "default";
--	pinctrl-0 = <&spi_nor_pins>;
--	status = "disabled";
-+&bch {
-+	status = "okay";
-+};
- 
-+&snfi {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&serial_nand_pins>;
-+	status = "okay";
- 	flash@0 {
--		compatible = "jedec,spi-nor";
-+		compatible = "spi-nand";
- 		reg = <0>;
-+		spi-tx-bus-width = <4>;
-+		spi-rx-bus-width = <4>;
-+		nand-ecc-engine = <&snfi>;
-+		partitions {
-+			compatible = "fixed-partitions";
-+			#address-cells = <1>;
-+			#size-cells = <1>;
-+
-+			partition@0 {
-+				label = "bl2";
-+				reg = <0x0 0x80000>;
-+				read-only;
-+			};
-+
-+			partition@80000 {
-+				label = "fip";
-+				reg = <0x80000 0x200000>;
-+				read-only;
-+			};
-+
-+			partition@280000 {
-+				label = "ubi";
-+				reg = <0x280000 0x7d80000>;
-+			};
-+		};
- 	};
- };
- 
diff --git a/target/linux/mediatek/patches-6.1/115-v6.5-arm64-dts-mt7622-declare-SPI-NAND-present-on-BPI-R64.patch b/target/linux/mediatek/patches-6.1/115-v6.5-arm64-dts-mt7622-declare-SPI-NAND-present-on-BPI-R64.patch
new file mode 100644
index 00000000000000..5fc55314cebbcc
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/115-v6.5-arm64-dts-mt7622-declare-SPI-NAND-present-on-BPI-R64.patch
@@ -0,0 +1,70 @@
+From d278f43f25beedfd0cb784d1dd0a9e7e8c8f123f Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Wed, 19 Apr 2023 20:15:53 +0100
+Subject: [PATCH] arm64: dts: mt7622: declare SPI-NAND present on BPI-R64
+
+The SPI-NOR node in the device tree of the BananaPi R64 has most likely
+been copied from the reference board's device tree even though the R64
+comes with an SPI-NAND chip rather than SPI-NOR.
+
+Setup the Serial NAND Flash Interface (SNFI) controller, enable
+hardware BCH error detection and correction engine and add the SPI-NAND
+chip including basic partitions,
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Link: https://lore.kernel.org/r/ZEA96dmaXqTpk8u8@makrotopia.org
+Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
+---
+ .../dts/mediatek/mt7622-bananapi-bpi-r64.dts  | 38 ++++++++++++++++---
+ 1 file changed, 33 insertions(+), 5 deletions(-)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+@@ -253,14 +253,42 @@
+ 	status = "disabled";
+ };
+ 
+-&nor_flash {
+-	pinctrl-names = "default";
+-	pinctrl-0 = <&spi_nor_pins>;
+-	status = "disabled";
++&bch {
++	status = "okay";
++};
+ 
++&snfi {
++	pinctrl-names = "default";
++	pinctrl-0 = <&serial_nand_pins>;
++	status = "okay";
+ 	flash@0 {
+-		compatible = "jedec,spi-nor";
++		compatible = "spi-nand";
+ 		reg = <0>;
++		spi-tx-bus-width = <4>;
++		spi-rx-bus-width = <4>;
++		nand-ecc-engine = <&snfi>;
++		partitions {
++			compatible = "fixed-partitions";
++			#address-cells = <1>;
++			#size-cells = <1>;
++
++			partition@0 {
++				label = "bl2";
++				reg = <0x0 0x80000>;
++				read-only;
++			};
++
++			partition@80000 {
++				label = "fip";
++				reg = <0x80000 0x200000>;
++				read-only;
++			};
++
++			ubi: partition@280000 {
++				label = "ubi";
++				reg = <0x280000 0x7d80000>;
++			};
++		};
+ 	};
+ };
+ 
diff --git a/target/linux/mediatek/patches-6.1/164-dts-mt7623-bpi-r2-rootdisk-for-fitblk.patch b/target/linux/mediatek/patches-6.1/164-dts-mt7623-bpi-r2-rootdisk-for-fitblk.patch
new file mode 100644
index 00000000000000..2675aa2589abd0
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/164-dts-mt7623-bpi-r2-rootdisk-for-fitblk.patch
@@ -0,0 +1,55 @@
+--- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
++++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
+@@ -26,7 +26,9 @@
+ 
+ 	chosen {
+ 		stdout-path = "serial2:115200n8";
+-		bootargs = "earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200n8 console=tty1";
++		bootargs = "root=/dev/fit0 earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200n8 console=tty1";
++		rootdisk-emmc = <&emmc_rootdisk>;
++		rootdisk-sd = <&sd_rootdisk>;
+ 	};
+ 
+ 	connector {
+@@ -315,6 +317,20 @@
+ 	vmmc-supply = <&reg_3p3v>;
+ 	vqmmc-supply = <&reg_1p8v>;
+ 	non-removable;
++
++	card@0 {
++		compatible = "mmc-card";
++		reg = <0>;
++
++		block {
++			compatible = "block-device";
++			partitions {
++				emmc_rootdisk: block-partition-fit {
++					partno = <3>;
++				};
++			};
++		};
++	};
+ };
+ 
+ &mmc1 {
+@@ -328,6 +344,20 @@
+ 	cd-gpios = <&pio 261 GPIO_ACTIVE_LOW>;
+ 	vmmc-supply = <&reg_3p3v>;
+ 	vqmmc-supply = <&reg_3p3v>;
++
++	card@0 {
++		compatible = "mmc-card";
++		reg = <0>;
++
++		block {
++			compatible = "block-device";
++			partitions {
++				sd_rootdisk: block-partition-fit {
++					partno = <3>;
++				};
++			};
++		};
++	};
+ };
+ 
+ &mt6323_leds {
diff --git a/target/linux/mediatek/patches-6.1/180-dts-mt7622-bpi-r64-add-mt7531-irq.patch b/target/linux/mediatek/patches-6.1/180-dts-mt7622-bpi-r64-add-mt7531-irq.patch
deleted file mode 100644
index 676c09f656cd06..00000000000000
--- a/target/linux/mediatek/patches-6.1/180-dts-mt7622-bpi-r64-add-mt7531-irq.patch
+++ /dev/null
@@ -1,13 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -152,6 +152,10 @@
- 		switch@0 {
- 			compatible = "mediatek,mt7531";
- 			reg = <0>;
-+			interrupt-controller;
-+			#interrupt-cells = <1>;
-+			interrupt-parent = <&pio>;
-+			interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
- 			reset-gpios = <&pio 54 0>;
- 
- 			ports {
diff --git a/target/linux/mediatek/patches-6.1/180-v6.5-arm64-dts-mt7622-handle-interrupts-from-MT7531-switc.patch b/target/linux/mediatek/patches-6.1/180-v6.5-arm64-dts-mt7622-handle-interrupts-from-MT7531-switc.patch
new file mode 100644
index 00000000000000..0a971c1f457678
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/180-v6.5-arm64-dts-mt7622-handle-interrupts-from-MT7531-switc.patch
@@ -0,0 +1,32 @@
+From 983f37ee08acb60435744f1b1e2afea2d2a09c48 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Wed, 19 Apr 2023 20:16:29 +0100
+Subject: [PATCH] arm64: dts: mt7622: handle interrupts from MT7531 switch on
+ BPI-R64
+
+Since commit ba751e28d442 ("net: dsa: mt7530: add interrupt support")
+the mt7530 driver can act as an interrupt controller. Wire up irq line
+of the MT7531 switch on the BananaPi BPi-R64 board, so the status of
+the PHYs of the five 1000Base-T ports doesn't need to be polled any
+more.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Link: https://lore.kernel.org/r/ZEA-DV_OsmFg5egL@makrotopia.org
+Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
+---
+ arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+@@ -154,6 +154,10 @@
+ 		switch@0 {
+ 			compatible = "mediatek,mt7531";
+ 			reg = <0>;
++			interrupt-controller;
++			#interrupt-cells = <1>;
++			interrupt-parent = <&pio>;
++			interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
+ 			reset-gpios = <&pio 54 0>;
+ 
+ 			ports {
diff --git a/target/linux/mediatek/patches-6.1/196-dts-mt7986a-bpi-r3-use-all-ubi-nand-layout.patch b/target/linux/mediatek/patches-6.1/196-dts-mt7986a-bpi-r3-use-all-ubi-nand-layout.patch
new file mode 100644
index 00000000000000..38510c0fc7911a
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/196-dts-mt7986a-bpi-r3-use-all-ubi-nand-layout.patch
@@ -0,0 +1,131 @@
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso
+@@ -23,7 +23,27 @@
+ 			no-sd;
+ 			no-sdio;
+ 			status = "okay";
++
++			card@0 {
++				compatible = "mmc-card";
++				reg = <0>;
++
++				block {
++					compatible = "block-device";
++					partitions {
++						emmc_rootdisk: block-partition-production {
++							partname = "production";
++						};
++					};
++				};
++			};
+ 		};
+ 	};
+-};
+ 
++	fragment@1 {
++		target-path = "/chosen";
++		__overlay__ {
++			rootdisk-emmc = <&emmc_rootdisk>;
++		};
++	};
++};
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
+@@ -29,27 +29,30 @@
+ 
+ 					partition@0 {
+ 						label = "bl2";
+-						reg = <0x0 0x100000>;
++						reg = <0x0 0x200000>;
+ 						read-only;
+ 					};
+ 
+-					partition@100000 {
+-						label = "reserved";
+-						reg = <0x100000 0x280000>;
+-					};
+-
+-					partition@380000 {
+-						label = "fip";
+-						reg = <0x380000 0x200000>;
+-						read-only;
+-					};
+-
+-					partition@580000 {
++					partition@200000 {
+ 						label = "ubi";
+-						reg = <0x580000 0x7a80000>;
++						reg = <0x200000 0x7e00000>;
++						compatible = "linux,ubi";
++
++						volumes {
++							nand_rootdisk: ubi-volume-fit {
++								volname = "fit";
++							};
++						};
+ 					};
+ 				};
+ 			};
+ 		};
+ 	};
++
++	fragment@1 {
++		target-path = "/chosen";
++		__overlay__ {
++			rootdisk-spim-nand = <&nand_rootdisk>;
++		};
++	};
+ };
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
+@@ -52,7 +52,7 @@
+ 						reg = <0x180000 0xa80000>;
+ 					};
+ 
+-					partition@c00000 {
++					nor_rootdisk: partition@c00000 {
+ 						label = "fit";
+ 						reg = <0xc00000 0x1400000>;
+ 						compatible = "denx,fit";
+@@ -61,4 +61,11 @@
+ 			};
+ 		};
+ 	};
++
++	fragment@1 {
++		target-path = "/chosen";
++		__overlay__ {
++			rootdisk-nor = <&nor_rootdisk>;
++		};
++	};
+ };
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso
+@@ -17,6 +17,27 @@
+ 			max-frequency = <52000000>;
+ 			cap-sd-highspeed;
+ 			status = "okay";
++
++			card@0 {
++				compatible = "mmc-card";
++				reg = <0>;
++
++				block {
++					compatible = "block-device";
++					partitions {
++						sd_rootdisk: block-partition-production {
++							partname = "production";
++						};
++					};
++				};
++			};
++		};
++	};
++
++	fragment@1 {
++		target-path = "/chosen";
++		__overlay__ {
++			rootdisk-sd = <&sd_rootdisk>;
+ 		};
+ 	};
+ };
diff --git a/target/linux/mediatek/patches-6.1/219-pinctrl-mediatek-assign-functions-to-configure-pin-b.patch b/target/linux/mediatek/patches-6.1/219-v6.6-pinctrl-mediatek-assign-functions-to-configure-pin-b.patch
similarity index 100%
rename from target/linux/mediatek/patches-6.1/219-pinctrl-mediatek-assign-functions-to-configure-pin-b.patch
rename to target/linux/mediatek/patches-6.1/219-v6.6-pinctrl-mediatek-assign-functions-to-configure-pin-b.patch
diff --git a/target/linux/mediatek/patches-6.1/232-clk-mediatek-mt7981-topckgen-flag-SGM_REG_SEL-as-cri.patch b/target/linux/mediatek/patches-6.1/232-clk-mediatek-mt7981-topckgen-flag-SGM_REG_SEL-as-cri.patch
new file mode 100644
index 00000000000000..8820d57f01fe35
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/232-clk-mediatek-mt7981-topckgen-flag-SGM_REG_SEL-as-cri.patch
@@ -0,0 +1,30 @@
+From fc157139e6b7f8dfb6430ac7191ba754027705e8 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Sun, 18 Feb 2024 01:59:59 +0000
+Subject: [PATCH] clk: mediatek: mt7981-topckgen: flag SGM_REG_SEL as critical
+
+Without the SGM_REG_SEL clock enabled the system freezes if trying to
+access registers used by MT7981 clock drivers itself.
+Mark SGM_REG_SEL as critical to make sure it is always enabled to
+prevent freezes on boot depending on probe order.
+
+Fixes: 813c3b53b55ba ("clk: mediatek: add MT7981 clock support")
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/clk/mediatek/clk-mt7981-topckgen.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+--- a/drivers/clk/mediatek/clk-mt7981-topckgen.c
++++ b/drivers/clk/mediatek/clk-mt7981-topckgen.c
+@@ -359,8 +359,9 @@ static const struct mtk_mux top_muxes[]
+ 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel",
+ 			     sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15,
+ 			     0x1C0, 21),
+-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents,
+-			     0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22),
++	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents,
++				   0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22,
++				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
+ 	MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP97B_SEL, "eip97b_sel", eip97b_parents,
+ 			     0x050, 0x054, 0x058, 24, 3, 31, 0x1C0, 23),
+ 	/* CLK_CFG_6 */
diff --git a/target/linux/mediatek/patches-6.1/241-clk-mediatek-Add-pcw-chg-shift-control.patch b/target/linux/mediatek/patches-6.1/241-clk-mediatek-Add-pcw-chg-shift-control.patch
deleted file mode 100644
index 75ca114a589aaf..00000000000000
--- a/target/linux/mediatek/patches-6.1/241-clk-mediatek-Add-pcw-chg-shift-control.patch
+++ /dev/null
@@ -1,24 +0,0 @@
---- a/drivers/clk/mediatek/clk-pll.c
-+++ b/drivers/clk/mediatek/clk-pll.c
-@@ -141,7 +141,10 @@ static void mtk_pll_set_rate_regs(struct
- 			pll->data->pcw_shift);
- 	val |= pcw << pll->data->pcw_shift;
- 	writel(val, pll->pcw_addr);
--	chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;
-+	if (pll->data->pcw_chg_shift)
-+		chg = readl(pll->pcw_chg_addr) | BIT(pll->data->pcw_chg_shift);
-+	else
-+		chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;
- 	writel(chg, pll->pcw_chg_addr);
- 	if (pll->tuner_addr)
- 		writel(val + 1, pll->tuner_addr);
---- a/drivers/clk/mediatek/clk-pll.h
-+++ b/drivers/clk/mediatek/clk-pll.h
-@@ -42,6 +42,7 @@ struct mtk_pll_data {
- 	u32 pcw_reg;
- 	int pcw_shift;
- 	u32 pcw_chg_reg;
-+	int pcw_chg_shift;
- 	const struct mtk_pll_div_table *div_table;
- 	const char *parent_name;
- 	u32 en_reg;
diff --git a/target/linux/mediatek/patches-6.1/241-v6.3-dt-bindings-clock-Add-compatibles-for-MT7981.patch b/target/linux/mediatek/patches-6.1/241-v6.3-dt-bindings-clock-Add-compatibles-for-MT7981.patch
new file mode 100644
index 00000000000000..ad4ecdf83ffd38
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/241-v6.3-dt-bindings-clock-Add-compatibles-for-MT7981.patch
@@ -0,0 +1,75 @@
+From cc4d9e0c77494fcf6bccbc57e23db0007cf681b7 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Thu, 26 Jan 2023 03:33:46 +0000
+Subject: [PATCH] dt-bindings: clock: Add compatibles for MT7981
+
+Add compatible string for MT7981 to existing bindings at
+ - mediatek,apmixedsys.yaml
+ - mediatek,topckgen.yaml
+ - mediatek,ethsys.txt
+ - mediatek,infracfg.yaml
+ - mediatek,sgmiisys.txt
+
+Signed-off-by: Jianhui Zhao <zhaojh329@gmail.com>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Link: https://lore.kernel.org/r/cc85ee470c781ff4013f6c21c92c0a21574b12b2.1674703830.git.daniel@makrotopia.org
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+---
+ .../devicetree/bindings/arm/mediatek/mediatek,ethsys.txt        | 1 +
+ .../devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml     | 1 +
+ .../devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt      | 2 ++
+ .../devicetree/bindings/clock/mediatek,apmixedsys.yaml          | 1 +
+ Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml  | 1 +
+ 5 files changed, 6 insertions(+)
+
+--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
+@@ -10,6 +10,7 @@ Required Properties:
+ 	- "mediatek,mt7622-ethsys", "syscon"
+ 	- "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon"
+ 	- "mediatek,mt7629-ethsys", "syscon"
++	- "mediatek,mt7981-ethsys", "syscon"
+ 	- "mediatek,mt7986-ethsys", "syscon"
+ - #clock-cells: Must be 1
+ - #reset-cells: Must be 1
+--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
+@@ -28,6 +28,7 @@ properties:
+               - mediatek,mt6797-infracfg
+               - mediatek,mt7622-infracfg
+               - mediatek,mt7629-infracfg
++              - mediatek,mt7981-infracfg
+               - mediatek,mt7986-infracfg
+               - mediatek,mt8135-infracfg
+               - mediatek,mt8167-infracfg
+--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
+@@ -8,6 +8,8 @@ Required Properties:
+ - compatible: Should be:
+ 	- "mediatek,mt7622-sgmiisys", "syscon"
+ 	- "mediatek,mt7629-sgmiisys", "syscon"
++	- "mediatek,mt7981-sgmiisys_0", "syscon"
++	- "mediatek,mt7981-sgmiisys_1", "syscon"
+ 	- "mediatek,mt7986-sgmiisys_0", "syscon"
+ 	- "mediatek,mt7986-sgmiisys_1", "syscon"
+ - #clock-cells: Must be 1
+--- a/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml
++++ b/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml
+@@ -20,6 +20,7 @@ properties:
+       - enum:
+           - mediatek,mt6797-apmixedsys
+           - mediatek,mt7622-apmixedsys
++          - mediatek,mt7981-apmixedsys
+           - mediatek,mt7986-apmixedsys
+           - mediatek,mt8135-apmixedsys
+           - mediatek,mt8173-apmixedsys
+--- a/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml
++++ b/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml
+@@ -35,6 +35,7 @@ properties:
+               - mediatek,mt6779-topckgen
+               - mediatek,mt6795-topckgen
+               - mediatek,mt7629-topckgen
++              - mediatek,mt7981-topckgen
+               - mediatek,mt7986-topckgen
+               - mediatek,mt8167-topckgen
+               - mediatek,mt8183-topckgen
diff --git a/target/linux/mediatek/patches-6.1/242-clk-mediatek-add-mt7988-clock-support.patch b/target/linux/mediatek/patches-6.1/242-clk-mediatek-add-mt7988-clock-support.patch
deleted file mode 100644
index 3ced012495b18d..00000000000000
--- a/target/linux/mediatek/patches-6.1/242-clk-mediatek-add-mt7988-clock-support.patch
+++ /dev/null
@@ -1,31 +0,0 @@
---- a/drivers/clk/mediatek/Kconfig
-+++ b/drivers/clk/mediatek/Kconfig
-@@ -415,6 +415,15 @@ config COMMON_CLK_MT7986_ETHSYS
- 	  This driver adds support for clocks for Ethernet and SGMII
- 	  required on MediaTek MT7986 SoC.
- 
-+config COMMON_CLK_MT7988
-+	bool "Clock driver for MediaTek MT7988"
-+	depends on ARCH_MEDIATEK || COMPILE_TEST
-+	select COMMON_CLK_MEDIATEK
-+	default ARCH_MEDIATEK
-+	help
-+	  This driver supports MediaTek MT7988 basic clocks and clocks
-+	  required for various periperals found on MediaTek.
-+
- config COMMON_CLK_MT8135
- 	bool "Clock driver for MediaTek MT8135"
- 	depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST
---- a/drivers/clk/mediatek/Makefile
-+++ b/drivers/clk/mediatek/Makefile
-@@ -60,6 +60,10 @@ obj-$(CONFIG_COMMON_CLK_MT7986) += clk-m
- obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o
- obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o
- obj-$(CONFIG_COMMON_CLK_MT7986_ETHSYS) += clk-mt7986-eth.o
-+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-apmixed.o
-+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-topckgen.o
-+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-infracfg.o
-+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-eth.o
- obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
- obj-$(CONFIG_COMMON_CLK_MT8167) += clk-mt8167.o
- obj-$(CONFIG_COMMON_CLK_MT8167_AUDSYS) += clk-mt8167-aud.o
diff --git a/target/linux/mediatek/patches-6.1/242-v6.4-dt-bindings-arm-mediatek-sgmiisys-Convert-to-DT-sche.patch b/target/linux/mediatek/patches-6.1/242-v6.4-dt-bindings-arm-mediatek-sgmiisys-Convert-to-DT-sche.patch
new file mode 100644
index 00000000000000..48d3d4e90cec0c
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/242-v6.4-dt-bindings-arm-mediatek-sgmiisys-Convert-to-DT-sche.patch
@@ -0,0 +1,107 @@
+From d4f08a703565abf47baa5a77d05365cf4598d55c Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Sun, 19 Mar 2023 12:56:52 +0000
+Subject: [PATCH 1/2] dt-bindings: arm: mediatek: sgmiisys: Convert to DT
+ schema
+
+Convert mediatek,sgmiiisys bindings to DT schema format.
+Add maintainer Matthias Brugger, no maintainers were listed in the
+original documentation.
+As this node is also referenced by the Ethernet controller and used
+as SGMII PCS add this fact to the description.
+Move the file to Documentation/devicetree/bindings/net/pcs/ which seems
+more appropriate given that the great majority of registers are related
+to SGMII PCS functionality and only one register represents clock bits.
+
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ .../arm/mediatek/mediatek,sgmiisys.txt        | 27 ----------
+ .../bindings/net/pcs/mediatek,sgmiisys.yaml   | 49 +++++++++++++++++++
+ 2 files changed, 49 insertions(+), 27 deletions(-)
+ delete mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
+ create mode 100644 Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
+
+--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
++++ /dev/null
+@@ -1,27 +0,0 @@
+-MediaTek SGMIISYS controller
+-============================
+-
+-The MediaTek SGMIISYS controller provides various clocks to the system.
+-
+-Required Properties:
+-
+-- compatible: Should be:
+-	- "mediatek,mt7622-sgmiisys", "syscon"
+-	- "mediatek,mt7629-sgmiisys", "syscon"
+-	- "mediatek,mt7981-sgmiisys_0", "syscon"
+-	- "mediatek,mt7981-sgmiisys_1", "syscon"
+-	- "mediatek,mt7986-sgmiisys_0", "syscon"
+-	- "mediatek,mt7986-sgmiisys_1", "syscon"
+-- #clock-cells: Must be 1
+-
+-The SGMIISYS controller uses the common clk binding from
+-Documentation/devicetree/bindings/clock/clock-bindings.txt
+-The available clocks are defined in dt-bindings/clock/mt*-clk.h.
+-
+-Example:
+-
+-sgmiisys: sgmiisys@1b128000 {
+-	compatible = "mediatek,mt7622-sgmiisys", "syscon";
+-	reg = <0 0x1b128000 0 0x1000>;
+-	#clock-cells = <1>;
+-};
+--- /dev/null
++++ b/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
+@@ -0,0 +1,49 @@
++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/net/pcs/mediatek,sgmiisys.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: MediaTek SGMIISYS Controller
++
++maintainers:
++  - Matthias Brugger <matthias.bgg@gmail.com>
++
++description:
++  The MediaTek SGMIISYS controller provides a SGMII PCS and some clocks
++  to the ethernet subsystem to which it is attached.
++
++properties:
++  compatible:
++    items:
++      - enum:
++          - mediatek,mt7622-sgmiisys
++          - mediatek,mt7629-sgmiisys
++          - mediatek,mt7986-sgmiisys_0
++          - mediatek,mt7986-sgmiisys_1
++      - const: syscon
++
++  reg:
++    maxItems: 1
++
++  '#clock-cells':
++    const: 1
++
++required:
++  - compatible
++  - reg
++  - '#clock-cells'
++
++additionalProperties: false
++
++examples:
++  - |
++    soc {
++      #address-cells = <2>;
++      #size-cells = <2>;
++      sgmiisys: syscon@1b128000 {
++        compatible = "mediatek,mt7622-sgmiisys", "syscon";
++        reg = <0 0x1b128000 0 0x1000>;
++        #clock-cells = <1>;
++      };
++    };
diff --git a/target/linux/mediatek/patches-6.1/243-v6.4-dt-bindings-net-pcs-mediatek-sgmiisys-add-MT7981-SoC.patch b/target/linux/mediatek/patches-6.1/243-v6.4-dt-bindings-net-pcs-mediatek-sgmiisys-add-MT7981-SoC.patch
new file mode 100644
index 00000000000000..62a64b9dd03a2d
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/243-v6.4-dt-bindings-net-pcs-mediatek-sgmiisys-add-MT7981-SoC.patch
@@ -0,0 +1,37 @@
+From 4f7eb19c4f44078100659f6ba073b0cc7191bc91 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Sun, 19 Mar 2023 12:57:04 +0000
+Subject: [PATCH 2/2] dt-bindings: net: pcs: mediatek,sgmiisys: add MT7981 SoC
+
+Add mediatek,pnswap boolean property needed on many boards using the
+MediaTek MT7981 SoC.
+
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ .../devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml      | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
++++ b/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
+@@ -19,6 +19,8 @@ properties:
+       - enum:
+           - mediatek,mt7622-sgmiisys
+           - mediatek,mt7629-sgmiisys
++          - mediatek,mt7981-sgmiisys_0
++          - mediatek,mt7981-sgmiisys_1
+           - mediatek,mt7986-sgmiisys_0
+           - mediatek,mt7986-sgmiisys_1
+       - const: syscon
+@@ -29,6 +31,10 @@ properties:
+   '#clock-cells':
+     const: 1
+ 
++  mediatek,pnswap:
++    description: Invert polarity of the SGMII data lanes
++    type: boolean
++
+ required:
+   - compatible
+   - reg
diff --git a/target/linux/mediatek/patches-6.1/244-v6.8-dt-bindings-arm-mediatek-move-ethsys-controller-conv.patch b/target/linux/mediatek/patches-6.1/244-v6.8-dt-bindings-arm-mediatek-move-ethsys-controller-conv.patch
new file mode 100644
index 00000000000000..946db82235c6e9
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/244-v6.8-dt-bindings-arm-mediatek-move-ethsys-controller-conv.patch
@@ -0,0 +1,113 @@
+From 94b0f301f6ee92f79a2fe2c655dfdbdfe2aec536 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Sun, 19 Nov 2023 22:24:16 +0100
+Subject: [PATCH] dt-bindings: arm: mediatek: move ethsys controller & convert
+ to DT schema
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+DT schema helps validating DTS files. Binding was moved to clock/ as
+this hardware is a clock provider. Example required a small fix for
+"reg" value (1 address cell + 1 size cell).
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Link: https://lore.kernel.org/r/20231119212416.2682-1-zajec5@gmail.com
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+---
+ .../bindings/arm/mediatek/mediatek,ethsys.txt | 29 ----------
+ .../bindings/clock/mediatek,ethsys.yaml       | 54 +++++++++++++++++++
+ 2 files changed, 54 insertions(+), 29 deletions(-)
+ delete mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
+ create mode 100644 Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml
+
+--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
++++ /dev/null
+@@ -1,29 +0,0 @@
+-Mediatek ethsys controller
+-============================
+-
+-The Mediatek ethsys controller provides various clocks to the system.
+-
+-Required Properties:
+-
+-- compatible: Should be:
+-	- "mediatek,mt2701-ethsys", "syscon"
+-	- "mediatek,mt7622-ethsys", "syscon"
+-	- "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon"
+-	- "mediatek,mt7629-ethsys", "syscon"
+-	- "mediatek,mt7981-ethsys", "syscon"
+-	- "mediatek,mt7986-ethsys", "syscon"
+-- #clock-cells: Must be 1
+-- #reset-cells: Must be 1
+-
+-The ethsys controller uses the common clk binding from
+-Documentation/devicetree/bindings/clock/clock-bindings.txt
+-The available clocks are defined in dt-bindings/clock/mt*-clk.h.
+-
+-Example:
+-
+-ethsys: clock-controller@1b000000 {
+-	compatible = "mediatek,mt2701-ethsys", "syscon";
+-	reg = <0 0x1b000000 0 0x1000>;
+-	#clock-cells = <1>;
+-	#reset-cells = <1>;
+-};
+--- /dev/null
++++ b/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml
+@@ -0,0 +1,54 @@
++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/clock/mediatek,ethsys.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Mediatek ethsys controller
++
++description:
++  The available clocks are defined in dt-bindings/clock/mt*-clk.h.
++
++maintainers:
++  - James Liao <jamesjj.liao@mediatek.com>
++
++properties:
++  compatible:
++    oneOf:
++      - items:
++          - enum:
++              - mediatek,mt2701-ethsys
++              - mediatek,mt7622-ethsys
++              - mediatek,mt7629-ethsys
++              - mediatek,mt7981-ethsys
++              - mediatek,mt7986-ethsys
++          - const: syscon
++      - items:
++          - const: mediatek,mt7623-ethsys
++          - const: mediatek,mt2701-ethsys
++          - const: syscon
++
++  reg:
++    maxItems: 1
++
++  "#clock-cells":
++    const: 1
++
++  "#reset-cells":
++    const: 1
++
++required:
++  - reg
++  - "#clock-cells"
++  - "#reset-cells"
++
++additionalProperties: false
++
++examples:
++  - |
++    clock-controller@1b000000 {
++        compatible = "mediatek,mt2701-ethsys", "syscon";
++        reg = <0x1b000000 0x1000>;
++        #clock-cells = <1>;
++        #reset-cells = <1>;
++    };
diff --git a/target/linux/mediatek/patches-6.1/245-v6.8-dt-bindings-reset-mediatek-add-MT7988-ethwarp-reset-.patch b/target/linux/mediatek/patches-6.1/245-v6.8-dt-bindings-reset-mediatek-add-MT7988-ethwarp-reset-.patch
new file mode 100644
index 00000000000000..47f05e93c620f0
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/245-v6.8-dt-bindings-reset-mediatek-add-MT7988-ethwarp-reset-.patch
@@ -0,0 +1,35 @@
+From 5cfa3beb7761cb84be77225902e018d9d3f9b973 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Sun, 17 Dec 2023 21:49:45 +0000
+Subject: [PATCH 1/4] dt-bindings: reset: mediatek: add MT7988 ethwarp reset
+ IDs
+
+Add reset ID for ethwarp subsystem allowing to reset the built-in
+Ethernet switch of the MediaTek MT7988 SoC.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Link: https://lore.kernel.org/r/0c14bbacf471683af67ffa7572bfa1d5c45a0b5d.1702849494.git.daniel@makrotopia.org
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+---
+ include/dt-bindings/reset/mediatek,mt7988-resets.h | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+ create mode 100644 include/dt-bindings/reset/mediatek,mt7988-resets.h
+
+--- /dev/null
++++ b/include/dt-bindings/reset/mediatek,mt7988-resets.h
+@@ -0,0 +1,13 @@
++/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
++/*
++ * Copyright (c) 2023 Daniel Golle <daniel@makrotopia.org>
++ * Author: Daniel Golle <daniel@makrotopia.org>
++ */
++
++#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7988
++#define _DT_BINDINGS_RESET_CONTROLLER_MT7988
++
++/* ETHWARP resets */
++#define MT7988_ETHWARP_RST_SWITCH		0
++
++#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT7988 */
diff --git a/target/linux/mediatek/patches-6.1/246-v6.8-dt-bindings-clock-mediatek-add-MT7988-clock-IDs.patch b/target/linux/mediatek/patches-6.1/246-v6.8-dt-bindings-clock-mediatek-add-MT7988-clock-IDs.patch
new file mode 100644
index 00000000000000..cf5cae634105f2
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/246-v6.8-dt-bindings-clock-mediatek-add-MT7988-clock-IDs.patch
@@ -0,0 +1,302 @@
+From 8187e001de156e99ef95366ffd10d627ed090826 Mon Sep 17 00:00:00 2001
+From: Sam Shih <sam.shih@mediatek.com>
+Date: Sun, 17 Dec 2023 21:49:33 +0000
+Subject: [PATCH] dt-bindings: clock: mediatek: add MT7988 clock IDs
+
+Add MT7988 clock dt-bindings for topckgen, apmixedsys, infracfg,
+ethernet and xfipll subsystem clocks.
+
+Signed-off-by: Sam Shih <sam.shih@mediatek.com>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Link: https://lore.kernel.org/r/27f99db432e9ccc804cc5b6501d7d17d72cae879.1702849494.git.daniel@makrotopia.org
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+---
+ .../dt-bindings/clock/mediatek,mt7988-clk.h   | 280 ++++++++++++++++++
+ 1 file changed, 280 insertions(+)
+ create mode 100644 include/dt-bindings/clock/mediatek,mt7988-clk.h
+
+--- /dev/null
++++ b/include/dt-bindings/clock/mediatek,mt7988-clk.h
+@@ -0,0 +1,280 @@
++/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
++/*
++ * Copyright (c) 2023 MediaTek Inc.
++ * Author: Sam Shih <sam.shih@mediatek.com>
++ * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
++ */
++
++#ifndef _DT_BINDINGS_CLK_MT7988_H
++#define _DT_BINDINGS_CLK_MT7988_H
++
++/* APMIXEDSYS */
++
++#define CLK_APMIXED_NETSYSPLL			0
++#define CLK_APMIXED_MPLL			1
++#define CLK_APMIXED_MMPLL			2
++#define CLK_APMIXED_APLL2			3
++#define CLK_APMIXED_NET1PLL			4
++#define CLK_APMIXED_NET2PLL			5
++#define CLK_APMIXED_WEDMCUPLL			6
++#define CLK_APMIXED_SGMPLL			7
++#define CLK_APMIXED_ARM_B			8
++#define CLK_APMIXED_CCIPLL2_B			9
++#define CLK_APMIXED_USXGMIIPLL			10
++#define CLK_APMIXED_MSDCPLL			11
++
++/* TOPCKGEN */
++
++#define CLK_TOP_XTAL				0
++#define CLK_TOP_XTAL_D2				1
++#define CLK_TOP_RTC_32K				2
++#define CLK_TOP_RTC_32P7K			3
++#define CLK_TOP_MPLL_D2				4
++#define CLK_TOP_MPLL_D3_D2			5
++#define CLK_TOP_MPLL_D4				6
++#define CLK_TOP_MPLL_D8				7
++#define CLK_TOP_MPLL_D8_D2			8
++#define CLK_TOP_MMPLL_D2			9
++#define CLK_TOP_MMPLL_D3_D5			10
++#define CLK_TOP_MMPLL_D4			11
++#define CLK_TOP_MMPLL_D6_D2			12
++#define CLK_TOP_MMPLL_D8			13
++#define CLK_TOP_APLL2_D4			14
++#define CLK_TOP_NET1PLL_D4			15
++#define CLK_TOP_NET1PLL_D5			16
++#define CLK_TOP_NET1PLL_D5_D2			17
++#define CLK_TOP_NET1PLL_D5_D4			18
++#define CLK_TOP_NET1PLL_D8			19
++#define CLK_TOP_NET1PLL_D8_D2			20
++#define CLK_TOP_NET1PLL_D8_D4			21
++#define CLK_TOP_NET1PLL_D8_D8			22
++#define CLK_TOP_NET1PLL_D8_D16			23
++#define CLK_TOP_NET2PLL_D2			24
++#define CLK_TOP_NET2PLL_D4			25
++#define CLK_TOP_NET2PLL_D4_D4			26
++#define CLK_TOP_NET2PLL_D4_D8			27
++#define CLK_TOP_NET2PLL_D6			28
++#define CLK_TOP_NET2PLL_D8			29
++#define CLK_TOP_NETSYS_SEL			30
++#define CLK_TOP_NETSYS_500M_SEL			31
++#define CLK_TOP_NETSYS_2X_SEL			32
++#define CLK_TOP_NETSYS_GSW_SEL			33
++#define CLK_TOP_ETH_GMII_SEL			34
++#define CLK_TOP_NETSYS_MCU_SEL			35
++#define CLK_TOP_NETSYS_PAO_2X_SEL		36
++#define CLK_TOP_EIP197_SEL			37
++#define CLK_TOP_AXI_INFRA_SEL			38
++#define CLK_TOP_UART_SEL			39
++#define CLK_TOP_EMMC_250M_SEL			40
++#define CLK_TOP_EMMC_400M_SEL			41
++#define CLK_TOP_SPI_SEL				42
++#define CLK_TOP_SPIM_MST_SEL			43
++#define CLK_TOP_NFI1X_SEL			44
++#define CLK_TOP_SPINFI_SEL			45
++#define CLK_TOP_PWM_SEL				46
++#define CLK_TOP_I2C_SEL				47
++#define CLK_TOP_PCIE_MBIST_250M_SEL		48
++#define CLK_TOP_PEXTP_TL_SEL			49
++#define CLK_TOP_PEXTP_TL_P1_SEL			50
++#define CLK_TOP_PEXTP_TL_P2_SEL			51
++#define CLK_TOP_PEXTP_TL_P3_SEL			52
++#define CLK_TOP_USB_SYS_SEL			53
++#define CLK_TOP_USB_SYS_P1_SEL			54
++#define CLK_TOP_USB_XHCI_SEL			55
++#define CLK_TOP_USB_XHCI_P1_SEL			56
++#define CLK_TOP_USB_FRMCNT_SEL			57
++#define CLK_TOP_USB_FRMCNT_P1_SEL		58
++#define CLK_TOP_AUD_SEL				59
++#define CLK_TOP_A1SYS_SEL			60
++#define CLK_TOP_AUD_L_SEL			61
++#define CLK_TOP_A_TUNER_SEL			62
++#define CLK_TOP_SSPXTP_SEL			63
++#define CLK_TOP_USB_PHY_SEL			64
++#define CLK_TOP_USXGMII_SBUS_0_SEL		65
++#define CLK_TOP_USXGMII_SBUS_1_SEL		66
++#define CLK_TOP_SGM_0_SEL			67
++#define CLK_TOP_SGM_SBUS_0_SEL			68
++#define CLK_TOP_SGM_1_SEL			69
++#define CLK_TOP_SGM_SBUS_1_SEL			70
++#define CLK_TOP_XFI_PHY_0_XTAL_SEL		71
++#define CLK_TOP_XFI_PHY_1_XTAL_SEL		72
++#define CLK_TOP_SYSAXI_SEL			73
++#define CLK_TOP_SYSAPB_SEL			74
++#define CLK_TOP_ETH_REFCK_50M_SEL		75
++#define CLK_TOP_ETH_SYS_200M_SEL		76
++#define CLK_TOP_ETH_SYS_SEL			77
++#define CLK_TOP_ETH_XGMII_SEL			78
++#define CLK_TOP_BUS_TOPS_SEL			79
++#define CLK_TOP_NPU_TOPS_SEL			80
++#define CLK_TOP_DRAMC_SEL			81
++#define CLK_TOP_DRAMC_MD32_SEL			82
++#define CLK_TOP_INFRA_F26M_SEL			83
++#define CLK_TOP_PEXTP_P0_SEL			84
++#define CLK_TOP_PEXTP_P1_SEL			85
++#define CLK_TOP_PEXTP_P2_SEL			86
++#define CLK_TOP_PEXTP_P3_SEL			87
++#define CLK_TOP_DA_XTP_GLB_P0_SEL		88
++#define CLK_TOP_DA_XTP_GLB_P1_SEL		89
++#define CLK_TOP_DA_XTP_GLB_P2_SEL		90
++#define CLK_TOP_DA_XTP_GLB_P3_SEL		91
++#define CLK_TOP_CKM_SEL				92
++#define CLK_TOP_DA_SEL				93
++#define CLK_TOP_PEXTP_SEL			94
++#define CLK_TOP_TOPS_P2_26M_SEL			95
++#define CLK_TOP_MCUSYS_BACKUP_625M_SEL		96
++#define CLK_TOP_NETSYS_SYNC_250M_SEL		97
++#define CLK_TOP_MACSEC_SEL			98
++#define CLK_TOP_NETSYS_TOPS_400M_SEL		99
++#define CLK_TOP_NETSYS_PPEFB_250M_SEL		100
++#define CLK_TOP_NETSYS_WARP_SEL			101
++#define CLK_TOP_ETH_MII_SEL			102
++#define CLK_TOP_NPU_SEL				103
++#define CLK_TOP_AUD_I2S_M			104
++
++/* MCUSYS */
++
++#define CLK_MCU_BUS_DIV_SEL			0
++#define CLK_MCU_ARM_DIV_SEL			1
++
++/* INFRACFG_AO */
++
++#define CLK_INFRA_MUX_UART0_SEL			0
++#define CLK_INFRA_MUX_UART1_SEL			1
++#define CLK_INFRA_MUX_UART2_SEL			2
++#define CLK_INFRA_MUX_SPI0_SEL			3
++#define CLK_INFRA_MUX_SPI1_SEL			4
++#define CLK_INFRA_MUX_SPI2_SEL			5
++#define CLK_INFRA_PWM_SEL			6
++#define CLK_INFRA_PWM_CK1_SEL			7
++#define CLK_INFRA_PWM_CK2_SEL			8
++#define CLK_INFRA_PWM_CK3_SEL			9
++#define CLK_INFRA_PWM_CK4_SEL			10
++#define CLK_INFRA_PWM_CK5_SEL			11
++#define CLK_INFRA_PWM_CK6_SEL			12
++#define CLK_INFRA_PWM_CK7_SEL			13
++#define CLK_INFRA_PWM_CK8_SEL			14
++#define CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL	15
++#define CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL	16
++#define CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL	17
++#define CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL	18
++
++/* INFRACFG */
++
++#define CLK_INFRA_PCIE_PERI_26M_CK_P0		19
++#define CLK_INFRA_PCIE_PERI_26M_CK_P1		20
++#define CLK_INFRA_PCIE_PERI_26M_CK_P2		21
++#define CLK_INFRA_PCIE_PERI_26M_CK_P3		22
++#define CLK_INFRA_66M_GPT_BCK			23
++#define CLK_INFRA_66M_PWM_HCK			24
++#define CLK_INFRA_66M_PWM_BCK			25
++#define CLK_INFRA_66M_PWM_CK1			26
++#define CLK_INFRA_66M_PWM_CK2			27
++#define CLK_INFRA_66M_PWM_CK3			28
++#define CLK_INFRA_66M_PWM_CK4			29
++#define CLK_INFRA_66M_PWM_CK5			30
++#define CLK_INFRA_66M_PWM_CK6			31
++#define CLK_INFRA_66M_PWM_CK7			32
++#define CLK_INFRA_66M_PWM_CK8			33
++#define CLK_INFRA_133M_CQDMA_BCK		34
++#define CLK_INFRA_66M_AUD_SLV_BCK		35
++#define CLK_INFRA_AUD_26M			36
++#define CLK_INFRA_AUD_L				37
++#define CLK_INFRA_AUD_AUD			38
++#define CLK_INFRA_AUD_EG2			39
++#define CLK_INFRA_DRAMC_F26M			40
++#define CLK_INFRA_133M_DBG_ACKM			41
++#define CLK_INFRA_66M_AP_DMA_BCK		42
++#define CLK_INFRA_66M_SEJ_BCK			43
++#define CLK_INFRA_PRE_CK_SEJ_F13M		44
++#define CLK_INFRA_26M_THERM_SYSTEM		45
++#define CLK_INFRA_I2C_BCK			46
++#define CLK_INFRA_52M_UART0_CK			47
++#define CLK_INFRA_52M_UART1_CK			48
++#define CLK_INFRA_52M_UART2_CK			49
++#define CLK_INFRA_NFI				50
++#define CLK_INFRA_SPINFI			51
++#define CLK_INFRA_66M_NFI_HCK			52
++#define CLK_INFRA_104M_SPI0			53
++#define CLK_INFRA_104M_SPI1			54
++#define CLK_INFRA_104M_SPI2_BCK			55
++#define CLK_INFRA_66M_SPI0_HCK			56
++#define CLK_INFRA_66M_SPI1_HCK			57
++#define CLK_INFRA_66M_SPI2_HCK			58
++#define CLK_INFRA_66M_FLASHIF_AXI		59
++#define CLK_INFRA_RTC				60
++#define CLK_INFRA_26M_ADC_BCK			61
++#define CLK_INFRA_RC_ADC			62
++#define CLK_INFRA_MSDC400			63
++#define CLK_INFRA_MSDC2_HCK			64
++#define CLK_INFRA_133M_MSDC_0_HCK		65
++#define CLK_INFRA_66M_MSDC_0_HCK		66
++#define CLK_INFRA_133M_CPUM_BCK			67
++#define CLK_INFRA_BIST2FPC			68
++#define CLK_INFRA_I2C_X16W_MCK_CK_P1		69
++#define CLK_INFRA_I2C_X16W_PCK_CK_P1		70
++#define CLK_INFRA_133M_USB_HCK			71
++#define CLK_INFRA_133M_USB_HCK_CK_P1		72
++#define CLK_INFRA_66M_USB_HCK			73
++#define CLK_INFRA_66M_USB_HCK_CK_P1		74
++#define CLK_INFRA_USB_SYS			75
++#define CLK_INFRA_USB_SYS_CK_P1			76
++#define CLK_INFRA_USB_REF			77
++#define CLK_INFRA_USB_CK_P1			78
++#define CLK_INFRA_USB_FRMCNT			79
++#define CLK_INFRA_USB_FRMCNT_CK_P1		80
++#define CLK_INFRA_USB_PIPE			81
++#define CLK_INFRA_USB_PIPE_CK_P1		82
++#define CLK_INFRA_USB_UTMI			83
++#define CLK_INFRA_USB_UTMI_CK_P1		84
++#define CLK_INFRA_USB_XHCI			85
++#define CLK_INFRA_USB_XHCI_CK_P1		86
++#define CLK_INFRA_PCIE_GFMUX_TL_P0		87
++#define CLK_INFRA_PCIE_GFMUX_TL_P1		88
++#define CLK_INFRA_PCIE_GFMUX_TL_P2		89
++#define CLK_INFRA_PCIE_GFMUX_TL_P3		90
++#define CLK_INFRA_PCIE_PIPE_P0			91
++#define CLK_INFRA_PCIE_PIPE_P1			92
++#define CLK_INFRA_PCIE_PIPE_P2			93
++#define CLK_INFRA_PCIE_PIPE_P3			94
++#define CLK_INFRA_133M_PCIE_CK_P0		95
++#define CLK_INFRA_133M_PCIE_CK_P1		96
++#define CLK_INFRA_133M_PCIE_CK_P2		97
++#define CLK_INFRA_133M_PCIE_CK_P3		98
++
++/* ETHDMA */
++
++#define CLK_ETHDMA_XGP1_EN			0
++#define CLK_ETHDMA_XGP2_EN			1
++#define CLK_ETHDMA_XGP3_EN			2
++#define CLK_ETHDMA_FE_EN			3
++#define CLK_ETHDMA_GP2_EN			4
++#define CLK_ETHDMA_GP1_EN			5
++#define CLK_ETHDMA_GP3_EN			6
++#define CLK_ETHDMA_ESW_EN			7
++#define CLK_ETHDMA_CRYPT0_EN			8
++#define CLK_ETHDMA_NR_CLK			9
++
++/* SGMIISYS_0 */
++
++#define CLK_SGM0_TX_EN				0
++#define CLK_SGM0_RX_EN				1
++#define CLK_SGMII0_NR_CLK			2
++
++/* SGMIISYS_1 */
++
++#define CLK_SGM1_TX_EN				0
++#define CLK_SGM1_RX_EN				1
++#define CLK_SGMII1_NR_CLK			2
++
++/* ETHWARP */
++
++#define CLK_ETHWARP_WOCPU2_EN			0
++#define CLK_ETHWARP_WOCPU1_EN			1
++#define CLK_ETHWARP_WOCPU0_EN			2
++#define CLK_ETHWARP_NR_CLK			3
++
++/* XFIPLL */
++#define CLK_XFIPLL_PLL				0
++#define CLK_XFIPLL_PLL_EN			1
++
++#endif /* _DT_BINDINGS_CLK_MT7988_H */
diff --git a/target/linux/mediatek/patches-6.1/247-v6.8-dt-bindings-clock-mediatek-add-clock-controllers-of-.patch b/target/linux/mediatek/patches-6.1/247-v6.8-dt-bindings-clock-mediatek-add-clock-controllers-of-.patch
new file mode 100644
index 00000000000000..79088b461be3f7
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/247-v6.8-dt-bindings-clock-mediatek-add-clock-controllers-of-.patch
@@ -0,0 +1,260 @@
+From afd36e9d91b0a840983b829a9e95407d8151f7e7 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Sun, 17 Dec 2023 21:49:55 +0000
+Subject: [PATCH 2/4] dt-bindings: clock: mediatek: add clock controllers of
+ MT7988
+
+Add various clock controllers found in the MT7988 SoC to existing
+bindings (if applicable) and add files for the new ethwarp, mcusys
+and xfi-pll clock controllers not previously present in any SoC.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Link: https://lore.kernel.org/r/07e76a544ce4392bcb88e34d5480e99bb7994618.1702849494.git.daniel@makrotopia.org
+Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+---
+ .../arm/mediatek/mediatek,infracfg.yaml       |  1 +
+ .../bindings/clock/mediatek,apmixedsys.yaml   |  1 +
+ .../bindings/clock/mediatek,ethsys.yaml       |  1 +
+ .../clock/mediatek,mt7988-ethwarp.yaml        | 52 +++++++++++++++
+ .../clock/mediatek,mt7988-xfi-pll.yaml        | 48 ++++++++++++++
+ .../bindings/clock/mediatek,topckgen.yaml     |  2 +
+ .../bindings/net/pcs/mediatek,sgmiisys.yaml   | 65 ++++++++++++++++---
+ 7 files changed, 161 insertions(+), 9 deletions(-)
+ create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7988-ethwarp.yaml
+ create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7988-xfi-pll.yaml
+
+--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
+@@ -30,6 +30,7 @@ properties:
+               - mediatek,mt7629-infracfg
+               - mediatek,mt7981-infracfg
+               - mediatek,mt7986-infracfg
++              - mediatek,mt7988-infracfg
+               - mediatek,mt8135-infracfg
+               - mediatek,mt8167-infracfg
+               - mediatek,mt8173-infracfg
+--- a/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml
++++ b/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml
+@@ -22,6 +22,7 @@ properties:
+           - mediatek,mt7622-apmixedsys
+           - mediatek,mt7981-apmixedsys
+           - mediatek,mt7986-apmixedsys
++          - mediatek,mt7988-apmixedsys
+           - mediatek,mt8135-apmixedsys
+           - mediatek,mt8173-apmixedsys
+           - mediatek,mt8516-apmixedsys
+--- a/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml
++++ b/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml
+@@ -22,6 +22,7 @@ properties:
+               - mediatek,mt7629-ethsys
+               - mediatek,mt7981-ethsys
+               - mediatek,mt7986-ethsys
++              - mediatek,mt7988-ethsys
+           - const: syscon
+       - items:
+           - const: mediatek,mt7623-ethsys
+--- /dev/null
++++ b/Documentation/devicetree/bindings/clock/mediatek,mt7988-ethwarp.yaml
+@@ -0,0 +1,52 @@
++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/clock/mediatek,mt7988-ethwarp.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: MediaTek MT7988 ethwarp Controller
++
++maintainers:
++  - Daniel Golle <daniel@makrotopia.org>
++
++description:
++  The Mediatek MT7988 ethwarp controller provides clocks and resets for the
++  Ethernet related subsystems found the MT7988 SoC.
++  The clock values can be found in <dt-bindings/clock/mt*-clk.h>.
++
++properties:
++  compatible:
++    items:
++      - const: mediatek,mt7988-ethwarp
++
++  reg:
++    maxItems: 1
++
++  '#clock-cells':
++    const: 1
++
++  '#reset-cells':
++    const: 1
++
++required:
++  - compatible
++  - reg
++  - '#clock-cells'
++  - '#reset-cells'
++
++additionalProperties: false
++
++examples:
++  - |
++    #include <dt-bindings/reset/ti-syscon.h>
++    soc {
++        #address-cells = <2>;
++        #size-cells = <2>;
++
++        clock-controller@15031000 {
++            compatible = "mediatek,mt7988-ethwarp";
++            reg = <0 0x15031000 0 0x1000>;
++            #clock-cells = <1>;
++            #reset-cells = <1>;
++        };
++    };
+--- /dev/null
++++ b/Documentation/devicetree/bindings/clock/mediatek,mt7988-xfi-pll.yaml
+@@ -0,0 +1,48 @@
++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/clock/mediatek,mt7988-xfi-pll.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: MediaTek MT7988 XFI PLL Clock Controller
++
++maintainers:
++  - Daniel Golle <daniel@makrotopia.org>
++
++description:
++  The MediaTek XFI PLL controller provides the 156.25MHz clock for the
++  Ethernet SerDes PHY from the 40MHz top_xtal clock.
++
++properties:
++  compatible:
++    const: mediatek,mt7988-xfi-pll
++
++  reg:
++    maxItems: 1
++
++  resets:
++    maxItems: 1
++
++  '#clock-cells':
++    const: 1
++
++required:
++  - compatible
++  - reg
++  - resets
++  - '#clock-cells'
++
++additionalProperties: false
++
++examples:
++  - |
++    soc {
++        #address-cells = <2>;
++        #size-cells = <2>;
++        clock-controller@11f40000 {
++            compatible = "mediatek,mt7988-xfi-pll";
++            reg = <0 0x11f40000 0 0x1000>;
++            resets = <&watchdog 16>;
++            #clock-cells = <1>;
++        };
++    };
+--- a/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml
++++ b/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml
+@@ -37,6 +37,8 @@ properties:
+               - mediatek,mt7629-topckgen
+               - mediatek,mt7981-topckgen
+               - mediatek,mt7986-topckgen
++              - mediatek,mt7988-mcusys
++              - mediatek,mt7988-topckgen
+               - mediatek,mt8167-topckgen
+               - mediatek,mt8183-topckgen
+           - const: syscon
+--- a/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
++++ b/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
+@@ -15,15 +15,22 @@ description:
+ 
+ properties:
+   compatible:
+-    items:
+-      - enum:
+-          - mediatek,mt7622-sgmiisys
+-          - mediatek,mt7629-sgmiisys
+-          - mediatek,mt7981-sgmiisys_0
+-          - mediatek,mt7981-sgmiisys_1
+-          - mediatek,mt7986-sgmiisys_0
+-          - mediatek,mt7986-sgmiisys_1
+-      - const: syscon
++    oneOf:
++      - items:
++          - enum:
++              - mediatek,mt7622-sgmiisys
++              - mediatek,mt7629-sgmiisys
++              - mediatek,mt7981-sgmiisys_0
++              - mediatek,mt7981-sgmiisys_1
++              - mediatek,mt7986-sgmiisys_0
++              - mediatek,mt7986-sgmiisys_1
++          - const: syscon
++      - items:
++          - enum:
++              - mediatek,mt7988-sgmiisys0
++              - mediatek,mt7988-sgmiisys1
++          - const: simple-mfd
++          - const: syscon
+ 
+   reg:
+     maxItems: 1
+@@ -35,11 +42,51 @@ properties:
+     description: Invert polarity of the SGMII data lanes
+     type: boolean
+ 
++  pcs:
++    type: object
++    description: MediaTek LynxI HSGMII PCS
++    properties:
++      compatible:
++        const: mediatek,mt7988-sgmii
++
++      clocks:
++        maxItems: 3
++
++      clock-names:
++        items:
++          - const: sgmii_sel
++          - const: sgmii_tx
++          - const: sgmii_rx
++
++    required:
++      - compatible
++      - clocks
++      - clock-names
++
++    additionalProperties: false
++
+ required:
+   - compatible
+   - reg
+   - '#clock-cells'
+ 
++allOf:
++  - if:
++      properties:
++        compatible:
++          contains:
++            enum:
++              - mediatek,mt7988-sgmiisys0
++              - mediatek,mt7988-sgmiisys1
++
++    then:
++      required:
++        - pcs
++
++    else:
++      properties:
++        pcs: false
++
+ additionalProperties: false
+ 
+ examples:
diff --git a/target/linux/mediatek/patches-6.1/248-v6.8-clk-mediatek-add-pcw_chg_bit-control-for-PLLs-of-MT7.patch b/target/linux/mediatek/patches-6.1/248-v6.8-clk-mediatek-add-pcw_chg_bit-control-for-PLLs-of-MT7.patch
new file mode 100644
index 00000000000000..ca37fc793a791a
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/248-v6.8-clk-mediatek-add-pcw_chg_bit-control-for-PLLs-of-MT7.patch
@@ -0,0 +1,50 @@
+From d9bf944beaaad1890ad3fcb755c61e1c7e4c5630 Mon Sep 17 00:00:00 2001
+From: Sam Shih <sam.shih@mediatek.com>
+Date: Sun, 17 Dec 2023 21:50:07 +0000
+Subject: [PATCH 3/4] clk: mediatek: add pcw_chg_bit control for PLLs of MT7988
+
+Introduce pcw_chg_bit member to struct mtk_pll_data and use it instead
+of the previously hardcoded PCW_CHG_MASK macro if set.
+This will needed for clocks on the MT7988 SoC.
+
+Signed-off-by: Sam Shih <sam.shih@mediatek.com>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Link: https://lore.kernel.org/r/3b9c65ddb08c8bedf790aacf29871af026b6f0b7.1702849494.git.daniel@makrotopia.org
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+---
+ drivers/clk/mediatek/clk-pll.c | 5 +++--
+ drivers/clk/mediatek/clk-pll.h | 1 +
+ 2 files changed, 4 insertions(+), 2 deletions(-)
+
+--- a/drivers/clk/mediatek/clk-pll.c
++++ b/drivers/clk/mediatek/clk-pll.c
+@@ -23,7 +23,7 @@
+ #define CON0_BASE_EN		BIT(0)
+ #define CON0_PWR_ON		BIT(0)
+ #define CON0_ISO_EN		BIT(1)
+-#define PCW_CHG_MASK		BIT(31)
++#define PCW_CHG_BIT		31
+ 
+ #define AUDPLL_TUNER_EN		BIT(31)
+ 
+@@ -141,7 +141,8 @@ static void mtk_pll_set_rate_regs(struct
+ 			pll->data->pcw_shift);
+ 	val |= pcw << pll->data->pcw_shift;
+ 	writel(val, pll->pcw_addr);
+-	chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;
++	chg = readl(pll->pcw_chg_addr) |
++	      BIT(pll->data->pcw_chg_bit ? : PCW_CHG_BIT);
+ 	writel(chg, pll->pcw_chg_addr);
+ 	if (pll->tuner_addr)
+ 		writel(val + 1, pll->tuner_addr);
+--- a/drivers/clk/mediatek/clk-pll.h
++++ b/drivers/clk/mediatek/clk-pll.h
+@@ -46,6 +46,7 @@ struct mtk_pll_data {
+ 	const char *parent_name;
+ 	u32 en_reg;
+ 	u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */
++	u8 pcw_chg_bit;
+ };
+ 
+ int mtk_clk_register_plls(struct device_node *node,
diff --git a/target/linux/mediatek/patches-6.1/249-v6.8-clk-mediatek-add-drivers-for-MT7988-SoC.patch b/target/linux/mediatek/patches-6.1/249-v6.8-clk-mediatek-add-drivers-for-MT7988-SoC.patch
new file mode 100644
index 00000000000000..61664b934cbb63
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/249-v6.8-clk-mediatek-add-drivers-for-MT7988-SoC.patch
@@ -0,0 +1,1026 @@
+From 4b4719437d85f0173d344f2c76fa1a5b7f7d184b Mon Sep 17 00:00:00 2001
+From: Sam Shih <sam.shih@mediatek.com>
+Date: Sun, 17 Dec 2023 21:50:15 +0000
+Subject: [PATCH 4/4] clk: mediatek: add drivers for MT7988 SoC
+
+Add APMIXED, ETH, INFRACFG and TOPCKGEN clock drivers which are
+typical MediaTek designs.
+
+Also add driver for XFIPLL clock generating the 156.25MHz clock for
+the XFI SerDes. It needs an undocumented software workaround and has
+an unknown internal design.
+
+Signed-off-by: Sam Shih <sam.shih@mediatek.com>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Link: https://lore.kernel.org/r/c7574d808e2da1a530182f0fd790c1337c336e1b.1702849494.git.daniel@makrotopia.org
+[sboyd@kernel.org: Add module license to infracfg file]
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+---
+ drivers/clk/mediatek/Kconfig               |   9 +
+ drivers/clk/mediatek/Makefile              |   5 +
+ drivers/clk/mediatek/clk-mt7988-apmixed.c  | 114 ++++++++
+ drivers/clk/mediatek/clk-mt7988-eth.c      | 150 ++++++++++
+ drivers/clk/mediatek/clk-mt7988-infracfg.c | 275 +++++++++++++++++
+ drivers/clk/mediatek/clk-mt7988-topckgen.c | 325 +++++++++++++++++++++
+ drivers/clk/mediatek/clk-mt7988-xfipll.c   |  82 ++++++
+ 7 files changed, 960 insertions(+)
+ create mode 100644 drivers/clk/mediatek/clk-mt7988-apmixed.c
+ create mode 100644 drivers/clk/mediatek/clk-mt7988-eth.c
+ create mode 100644 drivers/clk/mediatek/clk-mt7988-infracfg.c
+ create mode 100644 drivers/clk/mediatek/clk-mt7988-topckgen.c
+ create mode 100644 drivers/clk/mediatek/clk-mt7988-xfipll.c
+
+--- a/drivers/clk/mediatek/Kconfig
++++ b/drivers/clk/mediatek/Kconfig
+@@ -415,6 +415,15 @@ config COMMON_CLK_MT7986_ETHSYS
+ 	  This driver adds support for clocks for Ethernet and SGMII
+ 	  required on MediaTek MT7986 SoC.
+ 
++config COMMON_CLK_MT7988
++	tristate "Clock driver for MediaTek MT7988"
++	depends on ARCH_MEDIATEK || COMPILE_TEST
++	select COMMON_CLK_MEDIATEK
++	default ARCH_MEDIATEK
++	help
++	  This driver supports MediaTek MT7988 basic clocks and clocks
++	  required for various periperals found on this SoC.
++
+ config COMMON_CLK_MT8135
+ 	bool "Clock driver for MediaTek MT8135"
+ 	depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST
+--- a/drivers/clk/mediatek/Makefile
++++ b/drivers/clk/mediatek/Makefile
+@@ -60,6 +60,11 @@ obj-$(CONFIG_COMMON_CLK_MT7986) += clk-m
+ obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o
+ obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o
+ obj-$(CONFIG_COMMON_CLK_MT7986_ETHSYS) += clk-mt7986-eth.o
++obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-apmixed.o
++obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-topckgen.o
++obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-infracfg.o
++obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-eth.o
++obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-xfipll.o
+ obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
+ obj-$(CONFIG_COMMON_CLK_MT8167) += clk-mt8167.o
+ obj-$(CONFIG_COMMON_CLK_MT8167_AUDSYS) += clk-mt8167-aud.o
+--- /dev/null
++++ b/drivers/clk/mediatek/clk-mt7988-apmixed.c
+@@ -0,0 +1,114 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2023 MediaTek Inc.
++ * Author: Sam Shih <sam.shih@mediatek.com>
++ * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
++ */
++
++#include <linux/clk-provider.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include "clk-mtk.h"
++#include "clk-gate.h"
++#include "clk-mux.h"
++#include "clk-pll.h"
++#include <dt-bindings/clock/mediatek,mt7988-clk.h>
++
++#define MT7988_PLL_FMAX (2500UL * MHZ)
++#define MT7988_PCW_CHG_BIT 2
++
++#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, _pcwbits, _pd_reg,	\
++	    _pd_shift, _tuner_reg, _tuner_en_reg, _tuner_en_bit, _pcw_reg, _pcw_shift,		\
++	    _pcw_chg_reg)									\
++	{											\
++		.id = _id,									\
++		.name = _name,									\
++		.reg = _reg,									\
++		.pwr_reg = _pwr_reg,								\
++		.en_mask = _en_mask,								\
++		.flags = _flags,								\
++		.rst_bar_mask = BIT(_rst_bar_mask),						\
++		.fmax = MT7988_PLL_FMAX,							\
++		.pcwbits = _pcwbits,								\
++		.pd_reg = _pd_reg,								\
++		.pd_shift = _pd_shift,								\
++		.tuner_reg = _tuner_reg,							\
++		.tuner_en_reg = _tuner_en_reg,							\
++		.tuner_en_bit = _tuner_en_bit,							\
++		.pcw_reg = _pcw_reg,								\
++		.pcw_shift = _pcw_shift,							\
++		.pcw_chg_reg = _pcw_chg_reg,							\
++		.pcw_chg_bit = MT7988_PCW_CHG_BIT,						\
++		.parent_name = "clkxtal",							\
++	}
++
++static const struct mtk_pll_data plls[] = {
++	PLL(CLK_APMIXED_NETSYSPLL, "netsyspll", 0x0104, 0x0110, 0x00000001, 0, 0, 32, 0x0104, 4, 0,
++	    0, 0, 0x0108, 0, 0x0104),
++	PLL(CLK_APMIXED_MPLL, "mpll", 0x0114, 0x0120, 0xff000001, HAVE_RST_BAR, 23, 32, 0x0114, 4,
++	    0, 0, 0, 0x0118, 0, 0x0114),
++	PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0124, 0x0130, 0xff000001, HAVE_RST_BAR, 23, 32, 0x0124, 4,
++	    0, 0, 0, 0x0128, 0, 0x0124),
++	PLL(CLK_APMIXED_APLL2, "apll2", 0x0134, 0x0140, 0x00000001, 0, 0, 32, 0x0134, 4, 0x0704,
++	    0x0700, 1, 0x0138, 0, 0x0134),
++	PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0144, 0x0150, 0xff000001, HAVE_RST_BAR, 23, 32,
++	    0x0144, 4, 0, 0, 0, 0x0148, 0, 0x0144),
++	PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0154, 0x0160, 0xff000001, (HAVE_RST_BAR | PLL_AO), 23,
++	    32, 0x0154, 4, 0, 0, 0, 0x0158, 0, 0x0154),
++	PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0164, 0x0170, 0x00000001, 0, 0, 32, 0x0164, 4, 0,
++	    0, 0, 0x0168, 0, 0x0164),
++	PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0174, 0x0180, 0x00000001, 0, 0, 32, 0x0174, 4, 0, 0, 0,
++	    0x0178, 0, 0x0174),
++	PLL(CLK_APMIXED_ARM_B, "arm_b", 0x0204, 0x0210, 0xff000001, (HAVE_RST_BAR | PLL_AO), 23, 32,
++	    0x0204, 4, 0, 0, 0, 0x0208, 0, 0x0204),
++	PLL(CLK_APMIXED_CCIPLL2_B, "ccipll2_b", 0x0214, 0x0220, 0xff000001, HAVE_RST_BAR, 23, 32,
++	    0x0214, 4, 0, 0, 0, 0x0218, 0, 0x0214),
++	PLL(CLK_APMIXED_USXGMIIPLL, "usxgmiipll", 0x0304, 0x0310, 0xff000001, HAVE_RST_BAR, 23, 32,
++	    0x0304, 4, 0, 0, 0, 0x0308, 0, 0x0304),
++	PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0314, 0x0320, 0x00000001, 0, 0, 32, 0x0314, 4, 0, 0,
++	    0, 0x0318, 0, 0x0314),
++};
++
++static const struct of_device_id of_match_clk_mt7988_apmixed[] = {
++	{ .compatible = "mediatek,mt7988-apmixedsys" },
++	{ /* sentinel */ }
++};
++
++static int clk_mt7988_apmixed_probe(struct platform_device *pdev)
++{
++	struct clk_hw_onecell_data *clk_data;
++	struct device_node *node = pdev->dev.of_node;
++	int r;
++
++	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
++	if (!clk_data)
++		return -ENOMEM;
++
++	r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
++	if (r)
++		goto free_apmixed_data;
++
++	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
++	if (r)
++		goto unregister_plls;
++
++	return r;
++
++unregister_plls:
++	mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
++free_apmixed_data:
++	mtk_free_clk_data(clk_data);
++	return r;
++}
++
++static struct platform_driver clk_mt7988_apmixed_drv = {
++	.probe = clk_mt7988_apmixed_probe,
++	.driver = {
++		.name = "clk-mt7988-apmixed",
++		.of_match_table = of_match_clk_mt7988_apmixed,
++	},
++};
++builtin_platform_driver(clk_mt7988_apmixed_drv);
++MODULE_LICENSE("GPL");
+--- /dev/null
++++ b/drivers/clk/mediatek/clk-mt7988-eth.c
+@@ -0,0 +1,150 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2023 MediaTek Inc.
++ * Author: Sam Shih <sam.shih@mediatek.com>
++ * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
++ */
++
++#include <linux/clk-provider.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include "clk-mtk.h"
++#include "clk-gate.h"
++#include "reset.h"
++#include <dt-bindings/clock/mediatek,mt7988-clk.h>
++#include <dt-bindings/reset/mediatek,mt7988-resets.h>
++
++static const struct mtk_gate_regs ethdma_cg_regs = {
++	.set_ofs = 0x30,
++	.clr_ofs = 0x30,
++	.sta_ofs = 0x30,
++};
++
++#define GATE_ETHDMA(_id, _name, _parent, _shift)		\
++	{							\
++		.id = _id,					\
++		.name = _name,					\
++		.parent_name = _parent,				\
++		.regs = &ethdma_cg_regs,			\
++		.shift = _shift,				\
++		.ops = &mtk_clk_gate_ops_no_setclr_inv,		\
++	}
++
++static const struct mtk_gate ethdma_clks[] = {
++	GATE_ETHDMA(CLK_ETHDMA_XGP1_EN, "ethdma_xgp1_en", "top_xtal", 0),
++	GATE_ETHDMA(CLK_ETHDMA_XGP2_EN, "ethdma_xgp2_en", "top_xtal", 1),
++	GATE_ETHDMA(CLK_ETHDMA_XGP3_EN, "ethdma_xgp3_en", "top_xtal", 2),
++	GATE_ETHDMA(CLK_ETHDMA_FE_EN, "ethdma_fe_en", "netsys_2x_sel", 6),
++	GATE_ETHDMA(CLK_ETHDMA_GP2_EN, "ethdma_gp2_en", "top_xtal", 7),
++	GATE_ETHDMA(CLK_ETHDMA_GP1_EN, "ethdma_gp1_en", "top_xtal", 8),
++	GATE_ETHDMA(CLK_ETHDMA_GP3_EN, "ethdma_gp3_en", "top_xtal", 10),
++	GATE_ETHDMA(CLK_ETHDMA_ESW_EN, "ethdma_esw_en", "netsys_gsw_sel", 16),
++	GATE_ETHDMA(CLK_ETHDMA_CRYPT0_EN, "ethdma_crypt0_en", "eip197_sel", 29),
++};
++
++static const struct mtk_clk_desc ethdma_desc = {
++	.clks = ethdma_clks,
++	.num_clks = ARRAY_SIZE(ethdma_clks),
++};
++
++static const struct mtk_gate_regs sgmii_cg_regs = {
++	.set_ofs = 0xe4,
++	.clr_ofs = 0xe4,
++	.sta_ofs = 0xe4,
++};
++
++#define GATE_SGMII(_id, _name, _parent, _shift)			\
++	{							\
++		.id = _id,					\
++		.name = _name,					\
++		.parent_name = _parent,				\
++		.regs = &sgmii_cg_regs,				\
++		.shift = _shift,				\
++		.ops = &mtk_clk_gate_ops_no_setclr_inv,		\
++	}
++
++static const struct mtk_gate sgmii0_clks[] = {
++	GATE_SGMII(CLK_SGM0_TX_EN, "sgm0_tx_en", "top_xtal", 2),
++	GATE_SGMII(CLK_SGM0_RX_EN, "sgm0_rx_en", "top_xtal", 3),
++};
++
++static const struct mtk_clk_desc sgmii0_desc = {
++	.clks = sgmii0_clks,
++	.num_clks = ARRAY_SIZE(sgmii0_clks),
++};
++
++static const struct mtk_gate sgmii1_clks[] = {
++	GATE_SGMII(CLK_SGM1_TX_EN, "sgm1_tx_en", "top_xtal", 2),
++	GATE_SGMII(CLK_SGM1_RX_EN, "sgm1_rx_en", "top_xtal", 3),
++};
++
++static const struct mtk_clk_desc sgmii1_desc = {
++	.clks = sgmii1_clks,
++	.num_clks = ARRAY_SIZE(sgmii1_clks),
++};
++
++static const struct mtk_gate_regs ethwarp_cg_regs = {
++	.set_ofs = 0x14,
++	.clr_ofs = 0x14,
++	.sta_ofs = 0x14,
++};
++
++#define GATE_ETHWARP(_id, _name, _parent, _shift)		\
++	{							\
++		.id = _id,					\
++		.name = _name,					\
++		.parent_name = _parent,				\
++		.regs = &ethwarp_cg_regs,			\
++		.shift = _shift,				\
++		.ops = &mtk_clk_gate_ops_no_setclr_inv,		\
++	}
++
++static const struct mtk_gate ethwarp_clks[] = {
++	GATE_ETHWARP(CLK_ETHWARP_WOCPU2_EN, "ethwarp_wocpu2_en", "netsys_mcu_sel", 13),
++	GATE_ETHWARP(CLK_ETHWARP_WOCPU1_EN, "ethwarp_wocpu1_en", "netsys_mcu_sel", 14),
++	GATE_ETHWARP(CLK_ETHWARP_WOCPU0_EN, "ethwarp_wocpu0_en", "netsys_mcu_sel", 15),
++};
++
++static u16 ethwarp_rst_ofs[] = { 0x8 };
++
++static u16 ethwarp_idx_map[] = {
++	[MT7988_ETHWARP_RST_SWITCH] = 9,
++};
++
++static const struct mtk_clk_rst_desc ethwarp_rst_desc = {
++	.version = MTK_RST_SIMPLE,
++	.rst_bank_ofs = ethwarp_rst_ofs,
++	.rst_bank_nr = ARRAY_SIZE(ethwarp_rst_ofs),
++	.rst_idx_map = ethwarp_idx_map,
++	.rst_idx_map_nr = ARRAY_SIZE(ethwarp_idx_map),
++};
++
++static const struct mtk_clk_desc ethwarp_desc = {
++	.clks = ethwarp_clks,
++	.num_clks = ARRAY_SIZE(ethwarp_clks),
++	.rst_desc = &ethwarp_rst_desc,
++};
++
++static const struct of_device_id of_match_clk_mt7988_eth[] = {
++	{ .compatible = "mediatek,mt7988-ethsys", .data = &ethdma_desc },
++	{ .compatible = "mediatek,mt7988-sgmiisys0", .data = &sgmii0_desc },
++	{ .compatible = "mediatek,mt7988-sgmiisys1", .data = &sgmii1_desc },
++	{ .compatible = "mediatek,mt7988-ethwarp", .data = &ethwarp_desc },
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_eth);
++
++static struct platform_driver clk_mt7988_eth_drv = {
++	.driver = {
++		.name = "clk-mt7988-eth",
++		.of_match_table = of_match_clk_mt7988_eth,
++	},
++	.probe = mtk_clk_simple_probe,
++	.remove = mtk_clk_simple_remove,
++};
++module_platform_driver(clk_mt7988_eth_drv);
++
++MODULE_DESCRIPTION("MediaTek MT7988 Ethernet clocks driver");
++MODULE_LICENSE("GPL");
+--- /dev/null
++++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c
+@@ -0,0 +1,275 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2023 MediaTek Inc.
++ * Author: Sam Shih <sam.shih@mediatek.com>
++ * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
++ */
++
++#include <linux/clk-provider.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include "clk-mtk.h"
++#include "clk-gate.h"
++#include "clk-mux.h"
++#include <dt-bindings/clock/mediatek,mt7988-clk.h>
++
++static DEFINE_SPINLOCK(mt7988_clk_lock);
++
++static const char *const infra_mux_uart0_parents[] __initconst = { "csw_infra_f26m_sel",
++								   "uart_sel" };
++
++static const char *const infra_mux_uart1_parents[] __initconst = { "csw_infra_f26m_sel",
++								   "uart_sel" };
++
++static const char *const infra_mux_uart2_parents[] __initconst = { "csw_infra_f26m_sel",
++								   "uart_sel" };
++
++static const char *const infra_mux_spi0_parents[] __initconst = { "i2c_sel", "spi_sel" };
++
++static const char *const infra_mux_spi1_parents[] __initconst = { "i2c_sel", "spim_mst_sel" };
++
++static const char *const infra_pwm_bck_parents[] __initconst = { "top_rtc_32p7k",
++								 "csw_infra_f26m_sel", "sysaxi_sel",
++								 "pwm_sel" };
++
++static const char *const infra_pcie_gfmux_tl_ck_o_p0_parents[] __initconst = {
++	"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_sel"
++};
++
++static const char *const infra_pcie_gfmux_tl_ck_o_p1_parents[] __initconst = {
++	"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_p1_sel"
++};
++
++static const char *const infra_pcie_gfmux_tl_ck_o_p2_parents[] __initconst = {
++	"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_p2_sel"
++};
++
++static const char *const infra_pcie_gfmux_tl_ck_o_p3_parents[] __initconst = {
++	"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_p3_sel"
++};
++
++static const struct mtk_mux infra_muxes[] = {
++	/* MODULE_CLK_SEL_0 */
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel",
++			     infra_mux_uart0_parents, 0x0018, 0x0010, 0x0014, 0, 1, -1, -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel",
++			     infra_mux_uart1_parents, 0x0018, 0x0010, 0x0014, 1, 1, -1, -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel",
++			     infra_mux_uart2_parents, 0x0018, 0x0010, 0x0014, 2, 1, -1, -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel", infra_mux_spi0_parents,
++			     0x0018, 0x0010, 0x0014, 4, 1, -1, -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel", infra_mux_spi1_parents,
++			     0x0018, 0x0010, 0x0014, 5, 1, -1, -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel", infra_mux_spi0_parents,
++			     0x0018, 0x0010, 0x0014, 6, 1, -1, -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_SEL, "infra_pwm_sel", infra_pwm_bck_parents, 0x0018,
++			     0x0010, 0x0014, 14, 2, -1, -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel", infra_pwm_bck_parents,
++			     0x0018, 0x0010, 0x0014, 16, 2, -1, -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel", infra_pwm_bck_parents,
++			     0x0018, 0x0010, 0x0014, 18, 2, -1, -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel", infra_pwm_bck_parents,
++			     0x0018, 0x0010, 0x0014, 20, 2, -1, -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel", infra_pwm_bck_parents,
++			     0x0018, 0x0010, 0x0014, 22, 2, -1, -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel", infra_pwm_bck_parents,
++			     0x0018, 0x0010, 0x0014, 24, 2, -1, -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel", infra_pwm_bck_parents,
++			     0x0018, 0x0010, 0x0014, 26, 2, -1, -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel", infra_pwm_bck_parents,
++			     0x0018, 0x0010, 0x0014, 28, 2, -1, -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel", infra_pwm_bck_parents,
++			     0x0018, 0x0010, 0x0014, 30, 2, -1, -1, -1),
++	/* MODULE_CLK_SEL_1 */
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, "infra_pcie_gfmux_tl_o_p0_sel",
++			     infra_pcie_gfmux_tl_ck_o_p0_parents, 0x0028, 0x0020, 0x0024, 0, 2, -1,
++			     -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, "infra_pcie_gfmux_tl_o_p1_sel",
++			     infra_pcie_gfmux_tl_ck_o_p1_parents, 0x0028, 0x0020, 0x0024, 2, 2, -1,
++			     -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, "infra_pcie_gfmux_tl_o_p2_sel",
++			     infra_pcie_gfmux_tl_ck_o_p2_parents, 0x0028, 0x0020, 0x0024, 4, 2, -1,
++			     -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, "infra_pcie_gfmux_tl_o_p3_sel",
++			     infra_pcie_gfmux_tl_ck_o_p3_parents, 0x0028, 0x0020, 0x0024, 6, 2, -1,
++			     -1, -1),
++};
++
++static const struct mtk_gate_regs infra0_cg_regs = {
++	.set_ofs = 0x10,
++	.clr_ofs = 0x14,
++	.sta_ofs = 0x18,
++};
++
++static const struct mtk_gate_regs infra1_cg_regs = {
++	.set_ofs = 0x40,
++	.clr_ofs = 0x44,
++	.sta_ofs = 0x48,
++};
++
++static const struct mtk_gate_regs infra2_cg_regs = {
++	.set_ofs = 0x50,
++	.clr_ofs = 0x54,
++	.sta_ofs = 0x58,
++};
++
++static const struct mtk_gate_regs infra3_cg_regs = {
++	.set_ofs = 0x60,
++	.clr_ofs = 0x64,
++	.sta_ofs = 0x68,
++};
++
++#define GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, _flags)                                 \
++	GATE_MTK_FLAGS(_id, _name, _parent, &infra0_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \
++		       _flags)
++
++#define GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, _flags)                                 \
++	GATE_MTK_FLAGS(_id, _name, _parent, &infra1_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \
++		       _flags)
++
++#define GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, _flags)                                 \
++	GATE_MTK_FLAGS(_id, _name, _parent, &infra2_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \
++		       _flags)
++
++#define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flags)                                 \
++	GATE_MTK_FLAGS(_id, _name, _parent, &infra3_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \
++		       _flags)
++
++#define GATE_INFRA0(_id, _name, _parent, _shift) GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, 0)
++
++#define GATE_INFRA1(_id, _name, _parent, _shift) GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, 0)
++
++#define GATE_INFRA2(_id, _name, _parent, _shift) GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, 0)
++
++#define GATE_INFRA3(_id, _name, _parent, _shift) GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, 0)
++
++static const struct mtk_gate infra_clks[] = {
++	/* INFRA0 */
++	GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P0, "infra_pcie_peri_ck_26m_ck_p0",
++		    "csw_infra_f26m_sel", 7),
++	GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P1, "infra_pcie_peri_ck_26m_ck_p1",
++		    "csw_infra_f26m_sel", 8),
++	GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P2, "infra_pcie_peri_ck_26m_ck_p2",
++		    "csw_infra_f26m_sel", 9),
++	GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P3, "infra_pcie_peri_ck_26m_ck_p3",
++		    "csw_infra_f26m_sel", 10),
++	/* INFRA1 */
++	GATE_INFRA1(CLK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck", "sysaxi_sel", 0),
++	GATE_INFRA1(CLK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck", "sysaxi_sel", 1),
++	GATE_INFRA1(CLK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck", "infra_pwm_sel", 2),
++	GATE_INFRA1(CLK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1", "infra_pwm_ck1_sel", 3),
++	GATE_INFRA1(CLK_INFRA_66M_PWM_CK2, "infra_hf_66m_pwm_ck2", "infra_pwm_ck2_sel", 4),
++	GATE_INFRA1(CLK_INFRA_66M_PWM_CK3, "infra_hf_66m_pwm_ck3", "infra_pwm_ck3_sel", 5),
++	GATE_INFRA1(CLK_INFRA_66M_PWM_CK4, "infra_hf_66m_pwm_ck4", "infra_pwm_ck4_sel", 6),
++	GATE_INFRA1(CLK_INFRA_66M_PWM_CK5, "infra_hf_66m_pwm_ck5", "infra_pwm_ck5_sel", 7),
++	GATE_INFRA1(CLK_INFRA_66M_PWM_CK6, "infra_hf_66m_pwm_ck6", "infra_pwm_ck6_sel", 8),
++	GATE_INFRA1(CLK_INFRA_66M_PWM_CK7, "infra_hf_66m_pwm_ck7", "infra_pwm_ck7_sel", 9),
++	GATE_INFRA1(CLK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8", "infra_pwm_ck8_sel", 10),
++	GATE_INFRA1(CLK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck", "sysaxi_sel", 12),
++	GATE_INFRA1(CLK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck", "sysaxi_sel", 13),
++	GATE_INFRA1(CLK_INFRA_AUD_26M, "infra_f_faud_26m", "csw_infra_f26m_sel", 14),
++	GATE_INFRA1(CLK_INFRA_AUD_L, "infra_f_faud_l", "aud_l_sel", 15),
++	GATE_INFRA1(CLK_INFRA_AUD_AUD, "infra_f_aud_aud", "a1sys_sel", 16),
++	GATE_INFRA1(CLK_INFRA_AUD_EG2, "infra_f_faud_eg2", "a_tuner_sel", 18),
++	GATE_INFRA1_FLAGS(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", "csw_infra_f26m_sel", 19,
++			  CLK_IS_CRITICAL),
++	/* JTAG */
++	GATE_INFRA1_FLAGS(CLK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm", "sysaxi_sel", 20,
++			  CLK_IS_CRITICAL),
++	GATE_INFRA1(CLK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck", "sysaxi_sel", 21),
++	GATE_INFRA1(CLK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck", "sysaxi_sel", 29),
++	GATE_INFRA1(CLK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m", "csw_infra_f26m_sel", 30),
++	/* INFRA2 */
++	GATE_INFRA2(CLK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system", "csw_infra_f26m_sel",
++		    0),
++	GATE_INFRA2(CLK_INFRA_I2C_BCK, "infra_i2c_bck", "i2c_sel", 1),
++	GATE_INFRA2(CLK_INFRA_52M_UART0_CK, "infra_f_52m_uart0", "infra_mux_uart0_sel", 3),
++	GATE_INFRA2(CLK_INFRA_52M_UART1_CK, "infra_f_52m_uart1", "infra_mux_uart1_sel", 4),
++	GATE_INFRA2(CLK_INFRA_52M_UART2_CK, "infra_f_52m_uart2", "infra_mux_uart2_sel", 5),
++	GATE_INFRA2(CLK_INFRA_NFI, "infra_f_fnfi", "nfi1x_sel", 9),
++	GATE_INFRA2(CLK_INFRA_SPINFI, "infra_f_fspinfi", "spinfi_sel", 10),
++	GATE_INFRA2_FLAGS(CLK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck", "sysaxi_sel", 11,
++			  CLK_IS_CRITICAL),
++	GATE_INFRA2_FLAGS(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0", "infra_mux_spi0_sel", 12,
++			  CLK_IS_CRITICAL),
++	GATE_INFRA2(CLK_INFRA_104M_SPI1, "infra_hf_104m_spi1", "infra_mux_spi1_sel", 13),
++	GATE_INFRA2(CLK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck", "infra_mux_spi2_sel", 14),
++	GATE_INFRA2_FLAGS(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck", "sysaxi_sel", 15,
++			  CLK_IS_CRITICAL),
++	GATE_INFRA2(CLK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck", "sysaxi_sel", 16),
++	GATE_INFRA2(CLK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck", "sysaxi_sel", 17),
++	GATE_INFRA2(CLK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi", "sysaxi_sel", 18),
++	GATE_INFRA2_FLAGS(CLK_INFRA_RTC, "infra_f_frtc", "top_rtc_32k", 19, CLK_IS_CRITICAL),
++	GATE_INFRA2(CLK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck", "csw_infra_f26m_sel", 20),
++	GATE_INFRA2(CLK_INFRA_RC_ADC, "infra_f_frc_adc", "infra_f_26m_adc_bck", 21),
++	GATE_INFRA2(CLK_INFRA_MSDC400, "infra_f_fmsdc400", "emmc_400m_sel", 22),
++	GATE_INFRA2(CLK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck", "emmc_250m_sel", 23),
++	GATE_INFRA2(CLK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck", "sysaxi_sel", 24),
++	GATE_INFRA2(CLK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck", "sysaxi_sel", 25),
++	GATE_INFRA2(CLK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck", "sysaxi_sel", 26),
++	GATE_INFRA2(CLK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", "nfi1x_sel", 27),
++	GATE_INFRA2(CLK_INFRA_I2C_X16W_MCK_CK_P1, "infra_hf_i2c_x16w_mck_ck_p1", "sysaxi_sel", 29),
++	GATE_INFRA2(CLK_INFRA_I2C_X16W_PCK_CK_P1, "infra_hf_i2c_x16w_pck_ck_p1", "sysaxi_sel", 31),
++	/* INFRA3 */
++	GATE_INFRA3(CLK_INFRA_133M_USB_HCK, "infra_133m_usb_hck", "sysaxi_sel", 0),
++	GATE_INFRA3(CLK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1", "sysaxi_sel", 1),
++	GATE_INFRA3(CLK_INFRA_66M_USB_HCK, "infra_66m_usb_hck", "sysaxi_sel", 2),
++	GATE_INFRA3(CLK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1", "sysaxi_sel", 3),
++	GATE_INFRA3(CLK_INFRA_USB_SYS, "infra_usb_sys", "usb_sys_sel", 4),
++	GATE_INFRA3(CLK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1", "usb_sys_p1_sel", 5),
++	GATE_INFRA3(CLK_INFRA_USB_REF, "infra_usb_ref", "top_xtal", 6),
++	GATE_INFRA3(CLK_INFRA_USB_CK_P1, "infra_usb_ck_p1", "top_xtal", 7),
++	GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT, "infra_usb_frmcnt", "usb_frmcnt_sel", 8,
++			  CLK_IS_CRITICAL),
++	GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1", "usb_frmcnt_p1_sel",
++			  9, CLK_IS_CRITICAL),
++	GATE_INFRA3(CLK_INFRA_USB_PIPE, "infra_usb_pipe", "sspxtp_sel", 10),
++	GATE_INFRA3(CLK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1", "usb_phy_sel", 11),
++	GATE_INFRA3(CLK_INFRA_USB_UTMI, "infra_usb_utmi", "top_xtal", 12),
++	GATE_INFRA3(CLK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1", "top_xtal", 13),
++	GATE_INFRA3(CLK_INFRA_USB_XHCI, "infra_usb_xhci", "usb_xhci_sel", 14),
++	GATE_INFRA3(CLK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1", "usb_xhci_p1_sel", 15),
++	GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0",
++		    "infra_pcie_gfmux_tl_o_p0_sel", 20),
++	GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1",
++		    "infra_pcie_gfmux_tl_o_p1_sel", 21),
++	GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P2, "infra_pcie_gfmux_tl_ck_p2",
++		    "infra_pcie_gfmux_tl_o_p2_sel", 22),
++	GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3",
++		    "infra_pcie_gfmux_tl_o_p3_sel", 23),
++	GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0", "top_xtal", 24),
++	GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1", "top_xtal", 25),
++	GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2", "top_xtal", 26),
++	GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3", "top_xtal", 27),
++	GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0", "sysaxi_sel", 28),
++	GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1", "sysaxi_sel", 29),
++	GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2", "sysaxi_sel", 30),
++	GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3", "sysaxi_sel", 31),
++};
++
++static const struct mtk_clk_desc infra_desc = {
++	.clks = infra_clks,
++	.num_clks = ARRAY_SIZE(infra_clks),
++	.mux_clks = infra_muxes,
++	.num_mux_clks = ARRAY_SIZE(infra_muxes),
++	.clk_lock = &mt7988_clk_lock,
++};
++
++static const struct of_device_id of_match_clk_mt7988_infracfg[] = {
++	{ .compatible = "mediatek,mt7988-infracfg", .data = &infra_desc },
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_infracfg);
++
++static struct platform_driver clk_mt7988_infracfg_drv = {
++	.driver = {
++		.name = "clk-mt7988-infracfg",
++		.of_match_table = of_match_clk_mt7988_infracfg,
++	},
++	.probe = mtk_clk_simple_probe,
++	.remove = mtk_clk_simple_remove,
++};
++module_platform_driver(clk_mt7988_infracfg_drv);
++MODULE_LICENSE("GPL");
+--- /dev/null
++++ b/drivers/clk/mediatek/clk-mt7988-topckgen.c
+@@ -0,0 +1,325 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2023 MediaTek Inc.
++ * Author: Sam Shih <sam.shih@mediatek.com>
++ * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
++ */
++
++#include <linux/clk-provider.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include "clk-mtk.h"
++#include "clk-gate.h"
++#include "clk-mux.h"
++#include <dt-bindings/clock/mediatek,mt7988-clk.h>
++
++static DEFINE_SPINLOCK(mt7988_clk_lock);
++
++static const struct mtk_fixed_clk top_fixed_clks[] = {
++	FIXED_CLK(CLK_TOP_XTAL, "top_xtal", "clkxtal", 40000000),
++};
++
++static const struct mtk_fixed_factor top_divs[] = {
++	FACTOR(CLK_TOP_XTAL_D2, "top_xtal_d2", "top_xtal", 1, 2),
++	FACTOR(CLK_TOP_RTC_32K, "top_rtc_32k", "top_xtal", 1, 1250),
++	FACTOR(CLK_TOP_RTC_32P7K, "top_rtc_32p7k", "top_xtal", 1, 1220),
++	FACTOR(CLK_TOP_MPLL_D2, "mpll_d2", "mpll", 1, 2),
++	FACTOR(CLK_TOP_MPLL_D3_D2, "mpll_d3_d2", "mpll", 1, 2),
++	FACTOR(CLK_TOP_MPLL_D4, "mpll_d4", "mpll", 1, 4),
++	FACTOR(CLK_TOP_MPLL_D8, "mpll_d8", "mpll", 1, 8),
++	FACTOR(CLK_TOP_MPLL_D8_D2, "mpll_d8_d2", "mpll", 1, 16),
++	FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
++	FACTOR(CLK_TOP_MMPLL_D3_D5, "mmpll_d3_d5", "mmpll", 1, 15),
++	FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4),
++	FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll", 1, 12),
++	FACTOR(CLK_TOP_MMPLL_D8, "mmpll_d8", "mmpll", 1, 8),
++	FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
++	FACTOR(CLK_TOP_NET1PLL_D4, "net1pll_d4", "net1pll", 1, 4),
++	FACTOR(CLK_TOP_NET1PLL_D5, "net1pll_d5", "net1pll", 1, 5),
++	FACTOR(CLK_TOP_NET1PLL_D5_D2, "net1pll_d5_d2", "net1pll", 1, 10),
++	FACTOR(CLK_TOP_NET1PLL_D5_D4, "net1pll_d5_d4", "net1pll", 1, 20),
++	FACTOR(CLK_TOP_NET1PLL_D8, "net1pll_d8", "net1pll", 1, 8),
++	FACTOR(CLK_TOP_NET1PLL_D8_D2, "net1pll_d8_d2", "net1pll", 1, 16),
++	FACTOR(CLK_TOP_NET1PLL_D8_D4, "net1pll_d8_d4", "net1pll", 1, 32),
++	FACTOR(CLK_TOP_NET1PLL_D8_D8, "net1pll_d8_d8", "net1pll", 1, 64),
++	FACTOR(CLK_TOP_NET1PLL_D8_D16, "net1pll_d8_d16", "net1pll", 1, 128),
++	FACTOR(CLK_TOP_NET2PLL_D2, "net2pll_d2", "net2pll", 1, 2),
++	FACTOR(CLK_TOP_NET2PLL_D4, "net2pll_d4", "net2pll", 1, 4),
++	FACTOR(CLK_TOP_NET2PLL_D4_D4, "net2pll_d4_d4", "net2pll", 1, 16),
++	FACTOR(CLK_TOP_NET2PLL_D4_D8, "net2pll_d4_d8", "net2pll", 1, 32),
++	FACTOR(CLK_TOP_NET2PLL_D6, "net2pll_d6", "net2pll", 1, 6),
++	FACTOR(CLK_TOP_NET2PLL_D8, "net2pll_d8", "net2pll", 1, 8),
++};
++
++static const char *const netsys_parents[] = { "top_xtal", "net2pll_d2", "mmpll_d2" };
++static const char *const netsys_500m_parents[] = { "top_xtal", "net1pll_d5", "net1pll_d5_d2" };
++static const char *const netsys_2x_parents[] = { "top_xtal", "net2pll", "mmpll" };
++static const char *const netsys_gsw_parents[] = { "top_xtal", "net1pll_d4", "net1pll_d5" };
++static const char *const eth_gmii_parents[] = { "top_xtal", "net1pll_d5_d4" };
++static const char *const netsys_mcu_parents[] = { "top_xtal",	"net2pll",    "mmpll",
++						  "net1pll_d4", "net1pll_d5", "mpll" };
++static const char *const eip197_parents[] = { "top_xtal", "netsyspll",	"net2pll",
++					      "mmpll",	  "net1pll_d4", "net1pll_d5" };
++static const char *const axi_infra_parents[] = { "top_xtal", "net1pll_d8_d2" };
++static const char *const uart_parents[] = { "top_xtal", "mpll_d8", "mpll_d8_d2" };
++static const char *const emmc_250m_parents[] = { "top_xtal", "net1pll_d5_d2", "mmpll_d4" };
++static const char *const emmc_400m_parents[] = { "top_xtal", "msdcpll",	 "mmpll_d2",
++						 "mpll_d2",  "mmpll_d4", "net1pll_d8_d2" };
++static const char *const spi_parents[] = { "top_xtal",	    "mpll_d2",	    "mmpll_d4",
++					   "net1pll_d8_d2", "net2pll_d6",   "net1pll_d5_d4",
++					   "mpll_d4",	    "net1pll_d8_d4" };
++static const char *const nfi1x_parents[] = { "top_xtal", "mmpll_d4", "net1pll_d8_d2", "net2pll_d6",
++					     "mpll_d4",	 "mmpll_d8", "net1pll_d8_d4", "mpll_d8" };
++static const char *const spinfi_parents[] = { "top_xtal_d2", "top_xtal", "net1pll_d5_d4",
++					      "mpll_d4",     "mmpll_d8", "net1pll_d8_d4",
++					      "mmpll_d6_d2", "mpll_d8" };
++static const char *const pwm_parents[] = { "top_xtal", "net1pll_d8_d2", "net1pll_d5_d4",
++					   "mpll_d4",  "mpll_d8_d2",	"top_rtc_32k" };
++static const char *const i2c_parents[] = { "top_xtal", "net1pll_d5_d4", "mpll_d4",
++					   "net1pll_d8_d4" };
++static const char *const pcie_mbist_250m_parents[] = { "top_xtal", "net1pll_d5_d2" };
++static const char *const pextp_tl_ck_parents[] = { "top_xtal", "net2pll_d6", "mmpll_d8",
++						   "mpll_d8_d2", "top_rtc_32k" };
++static const char *const usb_frmcnt_parents[] = { "top_xtal", "mmpll_d3_d5" };
++static const char *const aud_parents[] = { "top_xtal", "apll2" };
++static const char *const a1sys_parents[] = { "top_xtal", "apll2_d4" };
++static const char *const aud_l_parents[] = { "top_xtal", "apll2", "mpll_d8_d2" };
++static const char *const sspxtp_parents[] = { "top_xtal_d2", "mpll_d8_d2" };
++static const char *const usxgmii_sbus_0_parents[] = { "top_xtal", "net1pll_d8_d4" };
++static const char *const sgm_0_parents[] = { "top_xtal", "sgmpll" };
++static const char *const sysapb_parents[] = { "top_xtal", "mpll_d3_d2" };
++static const char *const eth_refck_50m_parents[] = { "top_xtal", "net2pll_d4_d4" };
++static const char *const eth_sys_200m_parents[] = { "top_xtal", "net2pll_d4" };
++static const char *const eth_xgmii_parents[] = { "top_xtal_d2", "net1pll_d8_d8", "net1pll_d8_d16" };
++static const char *const bus_tops_parents[] = { "top_xtal", "net1pll_d5", "net2pll_d2" };
++static const char *const npu_tops_parents[] = { "top_xtal", "net2pll" };
++static const char *const dramc_md32_parents[] = { "top_xtal", "mpll_d2", "wedmcupll" };
++static const char *const da_xtp_glb_p0_parents[] = { "top_xtal", "net2pll_d8" };
++static const char *const mcusys_backup_625m_parents[] = { "top_xtal", "net1pll_d4" };
++static const char *const macsec_parents[] = { "top_xtal", "sgmpll", "net1pll_d8" };
++static const char *const netsys_tops_400m_parents[] = { "top_xtal", "net2pll_d2" };
++static const char *const eth_mii_parents[] = { "top_xtal_d2", "net2pll_d4_d8" };
++
++static const struct mtk_mux top_muxes[] = {
++	/* CLK_CFG_0 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x000, 0x004, 0x008,
++			     0, 2, 7, 0x1c0, 0),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents, 0x000,
++			     0x004, 0x008, 8, 2, 15, 0x1C0, 1),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x000,
++			     0x004, 0x008, 16, 2, 23, 0x1C0, 2),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel", netsys_gsw_parents, 0x000,
++			     0x004, 0x008, 24, 2, 31, 0x1C0, 3),
++	/* CLK_CFG_1 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_GMII_SEL, "eth_gmii_sel", eth_gmii_parents, 0x010, 0x014,
++			     0x018, 0, 1, 7, 0x1C0, 4),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents, 0x010,
++			     0x014, 0x018, 8, 3, 15, 0x1C0, 5),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PAO_2X_SEL, "netsys_pao_2x_sel", netsys_mcu_parents,
++			     0x010, 0x014, 0x018, 16, 3, 23, 0x1C0, 6),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP197_SEL, "eip197_sel", eip197_parents, 0x010, 0x014, 0x018,
++			     24, 3, 31, 0x1c0, 7),
++	/* CLK_CFG_2 */
++	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_INFRA_SEL, "axi_infra_sel", axi_infra_parents, 0x020,
++				   0x024, 0x028, 0, 1, 7, 0x1C0, 8, CLK_IS_CRITICAL),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x020, 0x024, 0x028, 8, 2,
++			     15, 0x1c0, 9),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, 0x020,
++			     0x024, 0x028, 16, 2, 23, 0x1C0, 10),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents, 0x020,
++			     0x024, 0x028, 24, 3, 31, 0x1C0, 11),
++	/* CLK_CFG_3 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x030, 0x034, 0x038, 0, 3, 7,
++			     0x1c0, 12),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x030, 0x034, 0x038,
++			     8, 3, 15, 0x1c0, 13),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x030, 0x034, 0x038, 16,
++			     3, 23, 0x1c0, 14),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x030, 0x034, 0x038,
++			     24, 3, 31, 0x1c0, 15),
++	/* CLK_CFG_4 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x040, 0x044, 0x048, 0, 3, 7,
++			     0x1c0, 16),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x040, 0x044, 0x048, 8, 2, 15,
++			     0x1c0, 17),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_PCIE_MBIST_250M_SEL, "pcie_mbist_250m_sel",
++			     pcie_mbist_250m_parents, 0x040, 0x044, 0x048, 16, 1, 23, 0x1C0, 18),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_sel", pextp_tl_ck_parents, 0x040,
++			     0x044, 0x048, 24, 3, 31, 0x1C0, 19),
++	/* CLK_CFG_5 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_p1_sel", pextp_tl_ck_parents, 0x050,
++			     0x054, 0x058, 0, 3, 7, 0x1C0, 20),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P2_SEL, "pextp_tl_p2_sel", pextp_tl_ck_parents, 0x050,
++			     0x054, 0x058, 8, 3, 15, 0x1C0, 21),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P3_SEL, "pextp_tl_p3_sel", pextp_tl_ck_parents, 0x050,
++			     0x054, 0x058, 16, 3, 23, 0x1C0, 22),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_SEL, "usb_sys_sel", eth_gmii_parents, 0x050, 0x054,
++			     0x058, 24, 1, 31, 0x1C0, 23),
++	/* CLK_CFG_6 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel", eth_gmii_parents, 0x060,
++			     0x064, 0x068, 0, 1, 7, 0x1C0, 24),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_SEL, "usb_xhci_sel", eth_gmii_parents, 0x060, 0x064,
++			     0x068, 8, 1, 15, 0x1C0, 25),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel", eth_gmii_parents, 0x060,
++			     0x064, 0x068, 16, 1, 23, 0x1C0, 26),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", usb_frmcnt_parents, 0x060,
++			     0x064, 0x068, 24, 1, 31, 0x1C0, 27),
++	/* CLK_CFG_7 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_P1_SEL, "usb_frmcnt_p1_sel", usb_frmcnt_parents,
++			     0x070, 0x074, 0x078, 0, 1, 7, 0x1C0, 28),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x070, 0x074, 0x078, 8, 1, 15,
++			     0x1c0, 29),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x070, 0x074, 0x078, 16,
++			     1, 23, 0x1c0, 30),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x070, 0x074, 0x078, 24,
++			     2, 31, 0x1c4, 0),
++	/* CLK_CFG_8 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents, 0x080, 0x084, 0x088,
++			     0, 1, 7, 0x1c4, 1),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_SSPXTP_SEL, "sspxtp_sel", sspxtp_parents, 0x080, 0x084, 0x088,
++			     8, 1, 15, 0x1c4, 2),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_PHY_SEL, "usb_phy_sel", sspxtp_parents, 0x080, 0x084,
++			     0x088, 16, 1, 23, 0x1c4, 3),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_0_SEL, "usxgmii_sbus_0_sel",
++			     usxgmii_sbus_0_parents, 0x080, 0x084, 0x088, 24, 1, 31, 0x1C4, 4),
++	/* CLK_CFG_9 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_1_SEL, "usxgmii_sbus_1_sel",
++			     usxgmii_sbus_0_parents, 0x090, 0x094, 0x098, 0, 1, 7, 0x1C4, 5),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents, 0x090, 0x094, 0x098, 8,
++			     1, 15, 0x1c4, 6),
++	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel", usxgmii_sbus_0_parents,
++				   0x090, 0x094, 0x098, 16, 1, 23, 0x1C4, 7, CLK_IS_CRITICAL),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents, 0x090, 0x094, 0x098, 24,
++			     1, 31, 0x1c4, 8),
++	/* CLK_CFG_10 */
++	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel", usxgmii_sbus_0_parents,
++				   0x0a0, 0x0a4, 0x0a8, 0, 1, 7, 0x1C4, 9, CLK_IS_CRITICAL),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_0_XTAL_SEL, "xfi_phy_0_xtal_sel", sspxtp_parents,
++			     0x0a0, 0x0a4, 0x0a8, 8, 1, 15, 0x1C4, 10),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_1_XTAL_SEL, "xfi_phy_1_xtal_sel", sspxtp_parents,
++			     0x0a0, 0x0a4, 0x0a8, 16, 1, 23, 0x1C4, 11),
++	/* CLK_CFG_11 */
++	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", axi_infra_parents, 0x0a0,
++				   0x0a4, 0x0a8, 24, 1, 31, 0x1C4, 12, CLK_IS_CRITICAL),
++	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0x0b0, 0x0b4,
++				   0x0b8, 0, 1, 7, 0x1c4, 13, CLK_IS_CRITICAL),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel", eth_refck_50m_parents,
++			     0x0b0, 0x0b4, 0x0b8, 8, 1, 15, 0x1C4, 14),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel", eth_sys_200m_parents,
++			     0x0b0, 0x0b4, 0x0b8, 16, 1, 23, 0x1C4, 15),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_SEL, "eth_sys_sel", pcie_mbist_250m_parents, 0x0b0,
++			     0x0b4, 0x0b8, 24, 1, 31, 0x1C4, 16),
++	/* CLK_CFG_12 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel", eth_xgmii_parents, 0x0c0,
++			     0x0c4, 0x0c8, 0, 2, 7, 0x1C4, 17),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_BUS_TOPS_SEL, "bus_tops_sel", bus_tops_parents, 0x0c0, 0x0c4,
++			     0x0c8, 8, 2, 15, 0x1C4, 18),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_TOPS_SEL, "npu_tops_sel", npu_tops_parents, 0x0c0, 0x0c4,
++			     0x0c8, 16, 1, 23, 0x1C4, 19),
++	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel", sspxtp_parents, 0x0c0, 0x0c4,
++				   0x0c8, 24, 1, 31, 0x1C4, 20, CLK_IS_CRITICAL),
++	/* CLK_CFG_13 */
++	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents,
++				   0x0d0, 0x0d4, 0x0d8, 0, 2, 7, 0x1C4, 21, CLK_IS_CRITICAL),
++	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", sspxtp_parents,
++				   0x0d0, 0x0d4, 0x0d8, 8, 1, 15, 0x1C4, 22, CLK_IS_CRITICAL),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P0_SEL, "pextp_p0_sel", sspxtp_parents, 0x0d0, 0x0d4,
++			     0x0d8, 16, 1, 23, 0x1C4, 23),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P1_SEL, "pextp_p1_sel", sspxtp_parents, 0x0d0, 0x0d4,
++			     0x0d8, 24, 1, 31, 0x1C4, 24),
++	/* CLK_CFG_14 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P2_SEL, "pextp_p2_sel", sspxtp_parents, 0x0e0, 0x0e4,
++			     0x0e8, 0, 1, 7, 0x1C4, 25),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P3_SEL, "pextp_p3_sel", sspxtp_parents, 0x0e0, 0x0e4,
++			     0x0e8, 8, 1, 15, 0x1C4, 26),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel", da_xtp_glb_p0_parents,
++			     0x0e0, 0x0e4, 0x0e8, 16, 1, 23, 0x1C4, 27),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel", da_xtp_glb_p0_parents,
++			     0x0e0, 0x0e4, 0x0e8, 24, 1, 31, 0x1C4, 28),
++	/* CLK_CFG_15 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P2_SEL, "da_xtp_glb_p2_sel", da_xtp_glb_p0_parents,
++			     0x0f0, 0x0f4, 0x0f8, 0, 1, 7, 0x1C4, 29),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P3_SEL, "da_xtp_glb_p3_sel", da_xtp_glb_p0_parents,
++			     0x0f0, 0x0f4, 0x0f8, 8, 1, 15, 0x1C4, 30),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_CKM_SEL, "ckm_sel", sspxtp_parents, 0x0F0, 0x0f4, 0x0f8, 16, 1,
++			     23, 0x1c8, 0),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_SEL, "da_sel", sspxtp_parents, 0x0f0, 0x0f4, 0x0f8, 24, 1,
++			     31, 0x1C8, 1),
++	/* CLK_CFG_16 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_SEL, "pextp_sel", sspxtp_parents, 0x0100, 0x104, 0x108,
++			     0, 1, 7, 0x1c8, 2),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_TOPS_P2_26M_SEL, "tops_p2_26m_sel", sspxtp_parents, 0x0100,
++			     0x104, 0x108, 8, 1, 15, 0x1C8, 3),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_MCUSYS_BACKUP_625M_SEL, "mcusys_backup_625m_sel",
++			     mcusys_backup_625m_parents, 0x0100, 0x104, 0x108, 16, 1, 23, 0x1C8, 4),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SYNC_250M_SEL, "netsys_sync_250m_sel",
++			     pcie_mbist_250m_parents, 0x0100, 0x104, 0x108, 24, 1, 31, 0x1c8, 5),
++	/* CLK_CFG_17 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_MACSEC_SEL, "macsec_sel", macsec_parents, 0x0110, 0x114, 0x118,
++			     0, 2, 7, 0x1c8, 6),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_TOPS_400M_SEL, "netsys_tops_400m_sel",
++			     netsys_tops_400m_parents, 0x0110, 0x114, 0x118, 8, 1, 15, 0x1c8, 7),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PPEFB_250M_SEL, "netsys_ppefb_250m_sel",
++			     pcie_mbist_250m_parents, 0x0110, 0x114, 0x118, 16, 1, 23, 0x1c8, 8),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_WARP_SEL, "netsys_warp_sel", netsys_parents, 0x0110,
++			     0x114, 0x118, 24, 2, 31, 0x1C8, 9),
++	/* CLK_CFG_18 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_MII_SEL, "eth_mii_sel", eth_mii_parents, 0x0120, 0x124,
++			     0x128, 0, 1, 7, 0x1c8, 10),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_SEL, "ck_npu_sel", netsys_2x_parents, 0x0120, 0x124, 0x128,
++			     8, 2, 15, 0x1c8, 11),
++};
++
++static const struct mtk_composite top_aud_divs[] = {
++	DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud_sel", 0x0420, 0, 0x0420, 8, 8),
++};
++
++static const struct mtk_clk_desc topck_desc = {
++	.fixed_clks = top_fixed_clks,
++	.num_fixed_clks = ARRAY_SIZE(top_fixed_clks),
++	.factor_clks = top_divs,
++	.num_factor_clks = ARRAY_SIZE(top_divs),
++	.mux_clks = top_muxes,
++	.num_mux_clks = ARRAY_SIZE(top_muxes),
++	.composite_clks = top_aud_divs,
++	.num_composite_clks = ARRAY_SIZE(top_aud_divs),
++	.clk_lock = &mt7988_clk_lock,
++};
++
++static const char *const mcu_bus_div_parents[] = { "top_xtal", "ccipll2_b", "net1pll_d4" };
++
++static const char *const mcu_arm_div_parents[] = { "top_xtal", "arm_b", "net1pll_d4" };
++
++static struct mtk_composite mcu_muxes[] = {
++	/* bus_pll_divider_cfg */
++	MUX_GATE_FLAGS(CLK_MCU_BUS_DIV_SEL, "mcu_bus_div_sel", mcu_bus_div_parents, 0x7C0, 9, 2, -1,
++		       CLK_IS_CRITICAL),
++	/* mp2_pll_divider_cfg */
++	MUX_GATE_FLAGS(CLK_MCU_ARM_DIV_SEL, "mcu_arm_div_sel", mcu_arm_div_parents, 0x7A8, 9, 2, -1,
++		       CLK_IS_CRITICAL),
++};
++
++static const struct mtk_clk_desc mcusys_desc = {
++	.composite_clks = mcu_muxes,
++	.num_composite_clks = ARRAY_SIZE(mcu_muxes),
++};
++
++static const struct of_device_id of_match_clk_mt7988_topckgen[] = {
++	{ .compatible = "mediatek,mt7988-topckgen", .data = &topck_desc },
++	{ .compatible = "mediatek,mt7988-mcusys", .data = &mcusys_desc },
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_topckgen);
++
++static struct platform_driver clk_mt7988_topckgen_drv = {
++	.probe = mtk_clk_simple_probe,
++	.remove = mtk_clk_simple_remove,
++	.driver = {
++		.name = "clk-mt7988-topckgen",
++		.of_match_table = of_match_clk_mt7988_topckgen,
++	},
++};
++module_platform_driver(clk_mt7988_topckgen_drv);
++MODULE_LICENSE("GPL");
+--- /dev/null
++++ b/drivers/clk/mediatek/clk-mt7988-xfipll.c
+@@ -0,0 +1,82 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2023 Daniel Golle <daniel@makrotopia.org>
++ */
++
++#include <linux/clk-provider.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include "clk-mtk.h"
++#include "clk-gate.h"
++#include <dt-bindings/clock/mediatek,mt7988-clk.h>
++
++/* Register to control USXGMII XFI PLL analog */
++#define XFI_PLL_ANA_GLB8		0x108
++#define RG_XFI_PLL_ANA_SWWA		0x02283248
++
++static const struct mtk_gate_regs xfipll_cg_regs = {
++	.set_ofs = 0x8,
++	.clr_ofs = 0x8,
++	.sta_ofs = 0x8,
++};
++
++#define GATE_XFIPLL(_id, _name, _parent, _shift)		\
++	{							\
++		.id = _id,					\
++		.name = _name,					\
++		.parent_name = _parent,				\
++		.regs = &xfipll_cg_regs,			\
++		.shift = _shift,				\
++		.ops = &mtk_clk_gate_ops_no_setclr_inv,		\
++	}
++
++static const struct mtk_fixed_factor xfipll_divs[] = {
++	FACTOR(CLK_XFIPLL_PLL, "xfipll_pll", "top_xtal", 125, 32),
++};
++
++static const struct mtk_gate xfipll_clks[] = {
++	GATE_XFIPLL(CLK_XFIPLL_PLL_EN, "xfipll_pll_en", "xfipll_pll", 31),
++};
++
++static const struct mtk_clk_desc xfipll_desc = {
++	.clks = xfipll_clks,
++	.num_clks = ARRAY_SIZE(xfipll_clks),
++	.factor_clks = xfipll_divs,
++	.num_factor_clks = ARRAY_SIZE(xfipll_divs),
++};
++
++static int clk_mt7988_xfipll_probe(struct platform_device *pdev)
++{
++	struct device_node *node = pdev->dev.of_node;
++	void __iomem *base = of_iomap(node, 0);
++
++	if (!base)
++		return -ENOMEM;
++
++	/* Apply software workaround for USXGMII PLL TCL issue */
++	writel(RG_XFI_PLL_ANA_SWWA, base + XFI_PLL_ANA_GLB8);
++	iounmap(base);
++
++	return mtk_clk_simple_probe(pdev);
++};
++
++static const struct of_device_id of_match_clk_mt7988_xfipll[] = {
++	{ .compatible = "mediatek,mt7988-xfi-pll", .data = &xfipll_desc },
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_xfipll);
++
++static struct platform_driver clk_mt7988_xfipll_drv = {
++	.driver = {
++		.name = "clk-mt7988-xfipll",
++		.of_match_table = of_match_clk_mt7988_xfipll,
++	},
++	.probe = clk_mt7988_xfipll_probe,
++	.remove = mtk_clk_simple_remove,
++};
++module_platform_driver(clk_mt7988_xfipll_drv);
++
++MODULE_DESCRIPTION("MediaTek MT7988 XFI PLL clock driver");
++MODULE_LICENSE("GPL");
diff --git a/target/linux/mediatek/patches-6.1/250-clk-mediatek-add-infracfg-reset-controller-for-mt798.patch b/target/linux/mediatek/patches-6.1/250-clk-mediatek-add-infracfg-reset-controller-for-mt798.patch
new file mode 100644
index 00000000000000..cecf095e92c1de
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/250-clk-mediatek-add-infracfg-reset-controller-for-mt798.patch
@@ -0,0 +1,57 @@
+From 26ced94177b150710d94cf365002a09cc48950e9 Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <frank-w@public-files.de>
+Date: Wed, 17 Jan 2024 19:41:11 +0100
+Subject: [PATCH] clk: mediatek: add infracfg reset controller for mt7988
+
+Infracfg can also operate as reset controller, add support for it.
+
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+---
+ drivers/clk/mediatek/clk-mt7988-infracfg.c | 23 ++++++++++++++++++++++
+ 1 file changed, 23 insertions(+)
+
+--- a/drivers/clk/mediatek/clk-mt7988-infracfg.c
++++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c
+@@ -14,6 +14,10 @@
+ #include "clk-gate.h"
+ #include "clk-mux.h"
+ #include <dt-bindings/clock/mediatek,mt7988-clk.h>
++#include <dt-bindings/reset/mediatek,mt7988-resets.h>
++
++#define	MT7988_INFRA_RST0_SET_OFFSET	0x70
++#define	MT7988_INFRA_RST1_SET_OFFSET	0x80
+ 
+ static DEFINE_SPINLOCK(mt7988_clk_lock);
+ 
+@@ -249,12 +253,31 @@ static const struct mtk_gate infra_clks[
+ 	GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3", "sysaxi_sel", 31),
+ };
+ 
++static u16 infra_rst_ofs[] = {
++	MT7988_INFRA_RST0_SET_OFFSET,
++	MT7988_INFRA_RST1_SET_OFFSET,
++};
++
++static u16 infra_idx_map[] = {
++	[MT7988_INFRA_RST0_PEXTP_MAC_SWRST] = 0 * RST_NR_PER_BANK + 6,
++	[MT7988_INFRA_RST1_THERM_CTRL_SWRST] = 1 * RST_NR_PER_BANK + 9,
++};
++
++static struct mtk_clk_rst_desc infra_rst_desc = {
++	.version = MTK_RST_SET_CLR,
++	.rst_bank_ofs = infra_rst_ofs,
++	.rst_bank_nr = ARRAY_SIZE(infra_rst_ofs),
++	.rst_idx_map = infra_idx_map,
++	.rst_idx_map_nr = ARRAY_SIZE(infra_idx_map),
++};
++
+ static const struct mtk_clk_desc infra_desc = {
+ 	.clks = infra_clks,
+ 	.num_clks = ARRAY_SIZE(infra_clks),
+ 	.mux_clks = infra_muxes,
+ 	.num_mux_clks = ARRAY_SIZE(infra_muxes),
+ 	.clk_lock = &mt7988_clk_lock,
++	.rst_desc = &infra_rst_desc,
+ };
+ 
+ static const struct of_device_id of_match_clk_mt7988_infracfg[] = {
diff --git a/target/linux/mediatek/patches-6.1/250-dt-bindings-reset-mediatek-add-MT7988-reset-IDs.patch b/target/linux/mediatek/patches-6.1/250-dt-bindings-reset-mediatek-add-MT7988-reset-IDs.patch
new file mode 100644
index 00000000000000..d353074e84a0f7
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/250-dt-bindings-reset-mediatek-add-MT7988-reset-IDs.patch
@@ -0,0 +1,25 @@
+From 3c810da3206f2e52c92f9f15a87f05db4bbba734 Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <frank-w@public-files.de>
+Date: Wed, 17 Jan 2024 19:41:10 +0100
+Subject: [PATCH] dt-bindings: reset: mediatek: add MT7988 reset IDs
+
+Add reset constants for using as index in driver and dts.
+
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+---
+ include/dt-bindings/reset/mediatek,mt7988-resets.h | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/include/dt-bindings/reset/mediatek,mt7988-resets.h
++++ b/include/dt-bindings/reset/mediatek,mt7988-resets.h
+@@ -10,4 +10,10 @@
+ /* ETHWARP resets */
+ #define MT7988_ETHWARP_RST_SWITCH		0
+ 
++/* INFRA resets */
++#define MT7988_INFRA_RST0_PEXTP_MAC_SWRST	0
++#define MT7988_INFRA_RST1_THERM_CTRL_SWRST	1
++
++
+ #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT7988 */
++
diff --git a/target/linux/mediatek/patches-6.1/251-v6.8-watchdog-mediatek-mt7988-add-wdt-support.patch b/target/linux/mediatek/patches-6.1/251-v6.8-watchdog-mediatek-mt7988-add-wdt-support.patch
new file mode 100644
index 00000000000000..cb49ce1d253139
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/251-v6.8-watchdog-mediatek-mt7988-add-wdt-support.patch
@@ -0,0 +1,125 @@
+From 137c9e08e5e542d58aa606b0bb4f0990117309a0 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 20 Nov 2023 18:22:31 +0000
+Subject: [PATCH] watchdog: mediatek: mt7988: add wdt support
+
+Add support for watchdog and reset generator unit of the MediaTek
+MT7988 SoC.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Reviewed-by: Guenter Roeck <linux@roeck-us.net>
+Link: https://lore.kernel.org/r/c0cf5f701801cce60470853fa15f1d9dced78c4f.1700504385.git.daniel@makrotopia.org
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
+---
+ drivers/watchdog/mtk_wdt.c | 42 ++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 42 insertions(+)
+
+--- a/drivers/watchdog/mtk_wdt.c
++++ b/drivers/watchdog/mtk_wdt.c
+@@ -56,9 +56,13 @@
+ #define WDT_SWSYSRST		0x18U
+ #define WDT_SWSYS_RST_KEY	0x88000000
+ 
++#define WDT_SWSYSRST_EN		0xfc
++
+ #define DRV_NAME		"mtk-wdt"
+ #define DRV_VERSION		"1.0"
+ 
++#define MT7988_TOPRGU_SW_RST_NUM	24
++
+ static bool nowayout = WATCHDOG_NOWAYOUT;
+ static unsigned int timeout;
+ 
+@@ -68,10 +72,12 @@ struct mtk_wdt_dev {
+ 	spinlock_t lock; /* protects WDT_SWSYSRST reg */
+ 	struct reset_controller_dev rcdev;
+ 	bool disable_wdt_extrst;
++	bool has_swsysrst_en;
+ };
+ 
+ struct mtk_wdt_data {
+ 	int toprgu_sw_rst_num;
++	bool has_swsysrst_en;
+ };
+ 
+ static const struct mtk_wdt_data mt2712_data = {
+@@ -82,6 +88,11 @@ static const struct mtk_wdt_data mt7986_
+ 	.toprgu_sw_rst_num = MT7986_TOPRGU_SW_RST_NUM,
+ };
+ 
++static const struct mtk_wdt_data mt7988_data = {
++	.toprgu_sw_rst_num = MT7988_TOPRGU_SW_RST_NUM,
++	.has_swsysrst_en = true,
++};
++
+ static const struct mtk_wdt_data mt8183_data = {
+ 	.toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM,
+ };
+@@ -98,6 +109,28 @@ static const struct mtk_wdt_data mt8195_
+ 	.toprgu_sw_rst_num = MT8195_TOPRGU_SW_RST_NUM,
+ };
+ 
++/**
++ * toprgu_reset_sw_en_unlocked() - enable/disable software control for reset bit
++ * @data: Pointer to instance of driver data.
++ * @id: Bit number identifying the reset to be enabled or disabled.
++ * @enable: If true, enable software control for that bit, disable otherwise.
++ *
++ * Context: The caller must hold lock of struct mtk_wdt_dev.
++ */
++static void toprgu_reset_sw_en_unlocked(struct mtk_wdt_dev *data,
++					unsigned long id, bool enable)
++{
++	u32 tmp;
++
++	tmp = readl(data->wdt_base + WDT_SWSYSRST_EN);
++	if (enable)
++		tmp |= BIT(id);
++	else
++		tmp &= ~BIT(id);
++
++	writel(tmp, data->wdt_base + WDT_SWSYSRST_EN);
++}
++
+ static int toprgu_reset_update(struct reset_controller_dev *rcdev,
+ 			       unsigned long id, bool assert)
+ {
+@@ -108,6 +141,9 @@ static int toprgu_reset_update(struct re
+ 
+ 	spin_lock_irqsave(&data->lock, flags);
+ 
++	if (assert && data->has_swsysrst_en)
++		toprgu_reset_sw_en_unlocked(data, id, true);
++
+ 	tmp = readl(data->wdt_base + WDT_SWSYSRST);
+ 	if (assert)
+ 		tmp |= BIT(id);
+@@ -116,6 +152,9 @@ static int toprgu_reset_update(struct re
+ 	tmp |= WDT_SWSYS_RST_KEY;
+ 	writel(tmp, data->wdt_base + WDT_SWSYSRST);
+ 
++	if (!assert && data->has_swsysrst_en)
++		toprgu_reset_sw_en_unlocked(data, id, false);
++
+ 	spin_unlock_irqrestore(&data->lock, flags);
+ 
+ 	return 0;
+@@ -393,6 +432,8 @@ static int mtk_wdt_probe(struct platform
+ 						       wdt_data->toprgu_sw_rst_num);
+ 		if (err)
+ 			return err;
++
++		mtk_wdt->has_swsysrst_en = wdt_data->has_swsysrst_en;
+ 	}
+ 
+ 	mtk_wdt->disable_wdt_extrst =
+@@ -427,6 +468,7 @@ static const struct of_device_id mtk_wdt
+ 	{ .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data },
+ 	{ .compatible = "mediatek,mt6589-wdt" },
+ 	{ .compatible = "mediatek,mt7986-wdt", .data = &mt7986_data },
++	{ .compatible = "mediatek,mt7988-wdt", .data = &mt7988_data },
+ 	{ .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data },
+ 	{ .compatible = "mediatek,mt8186-wdt", .data = &mt8186_data },
+ 	{ .compatible = "mediatek,mt8192-wdt", .data = &mt8192_data },
diff --git a/target/linux/mediatek/patches-6.1/351-pinctrl-add-mt7988-pd-pulltype-support.patch b/target/linux/mediatek/patches-6.1/351-pinctrl-add-mt7988-pd-pulltype-support.patch
new file mode 100644
index 00000000000000..1fcb1e64c7dd80
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/351-pinctrl-add-mt7988-pd-pulltype-support.patch
@@ -0,0 +1,99 @@
+--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
++++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
+@@ -601,6 +601,30 @@ out:
+ 	return err;
+ }
+ 
++static int mtk_pinconf_bias_set_pd(struct mtk_pinctrl *hw,
++				const struct mtk_pin_desc *desc,
++				u32 pullup, u32 arg)
++{
++    int err, pd;
++
++	if (arg == MTK_DISABLE)
++		pd = 0;
++	else if ((arg == MTK_ENABLE) && pullup)
++		pd = 0;
++	else if ((arg == MTK_ENABLE) && !pullup)
++		pd = 1;
++	else {
++		err = -EINVAL;
++		goto out;
++	}
++
++	err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd);
++
++out:
++	return err;
++
++}
++
+ static int mtk_pinconf_bias_set_pullsel_pullen(struct mtk_pinctrl *hw,
+ 				const struct mtk_pin_desc *desc,
+ 				u32 pullup, u32 arg)
+@@ -755,6 +779,12 @@ int mtk_pinconf_bias_set_combo(struct mt
+ 			return err;
+ 	}
+ 
++	if (try_all_type & MTK_PULL_PD_TYPE) {
++		err = mtk_pinconf_bias_set_pd(hw, desc, pullup, arg);
++		if (!err)
++			return err;
++    }
++
+ 	if (try_all_type & MTK_PULL_PU_PD_TYPE) {
+ 		err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg);
+ 		if (!err)
+@@ -875,6 +905,29 @@ out:
+ 	return err;
+ }
+ 
++static int mtk_pinconf_bias_get_pd(struct mtk_pinctrl *hw,
++				const struct mtk_pin_desc *desc,
++				u32 *pullup, u32 *enable)
++{
++	int err, pd;
++
++	err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &pd);
++	if (err)
++		goto out;
++
++	if (pd == 0) {
++		*pullup = 0;
++		*enable = MTK_DISABLE;
++	} else if (pd == 1) {
++		*pullup = 0;
++		*enable = MTK_ENABLE;
++	} else
++		err = -EINVAL;
++
++out:
++	return err;
++}
++
+ static int mtk_pinconf_bias_get_pullsel_pullen(struct mtk_pinctrl *hw,
+ 				const struct mtk_pin_desc *desc,
+ 				u32 *pullup, u32 *enable)
+@@ -943,6 +996,12 @@ int mtk_pinconf_bias_get_combo(struct mt
+ 		if (!err)
+ 			return err;
+ 	}
++
++	if (try_all_type & MTK_PULL_PD_TYPE) {
++		err = mtk_pinconf_bias_get_pd(hw, desc, pullup, enable);
++		if (!err)
++			return err;
++	}
+ 
+ 	if (try_all_type & MTK_PULL_PU_PD_TYPE) {
+ 		err = mtk_pinconf_bias_get_pu_pd(hw, desc, pullup, enable);
+--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
++++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
+@@ -24,6 +24,7 @@
+  * turned on/off itself. But it can't be selected pull up/down
+  */
+ #define MTK_PULL_RSEL_TYPE		BIT(3)
++#define MTK_PULL_PD_TYPE        BIT(4)
+ /* MTK_PULL_PU_PD_RSEL_TYPE is a type which is controlled by
+  * MTK_PULL_PU_PD_TYPE and MTK_PULL_RSEL_TYPE.
+  */
diff --git a/target/linux/mediatek/patches-6.1/432-drivers-spi-Add-support-for-dynamic-calibration.patch b/target/linux/mediatek/patches-6.1/432-drivers-spi-Add-support-for-dynamic-calibration.patch
index 9aeeb786589bcd..b2c9df4386a446 100644
--- a/target/linux/mediatek/patches-6.1/432-drivers-spi-Add-support-for-dynamic-calibration.patch
+++ b/target/linux/mediatek/patches-6.1/432-drivers-spi-Add-support-for-dynamic-calibration.patch
@@ -82,7 +82,7 @@ Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
  static void _spi_transfer_delay_ns(u32 ns)
  {
  	if (!ns)
-@@ -2219,6 +2283,75 @@ void spi_flush_queue(struct spi_controll
+@@ -2223,6 +2287,75 @@ void spi_flush_queue(struct spi_controll
  /*-------------------------------------------------------------------------*/
  
  #if defined(CONFIG_OF)
@@ -158,7 +158,7 @@ Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
  static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi,
  			   struct device_node *nc)
  {
-@@ -2337,6 +2470,10 @@ of_register_spi_device(struct spi_contro
+@@ -2341,6 +2474,10 @@ of_register_spi_device(struct spi_contro
  	if (rc)
  		goto err_out;
  
diff --git a/target/linux/mediatek/patches-6.1/500-gsw-rtl8367s-mt7622-support.patch b/target/linux/mediatek/patches-6.1/500-gsw-rtl8367s-mt7622-support.patch
index 9c575d694b1cf1..487990ab77ca52 100644
--- a/target/linux/mediatek/patches-6.1/500-gsw-rtl8367s-mt7622-support.patch
+++ b/target/linux/mediatek/patches-6.1/500-gsw-rtl8367s-mt7622-support.patch
@@ -1,6 +1,6 @@
 --- a/drivers/net/phy/Kconfig
 +++ b/drivers/net/phy/Kconfig
-@@ -386,6 +386,12 @@ config ROCKCHIP_PHY
+@@ -384,6 +384,12 @@ config ROCKCHIP_PHY
  	help
  	  Currently supports the integrated Ethernet PHY.
  
@@ -15,7 +15,7 @@
  	help
 --- a/drivers/net/phy/Makefile
 +++ b/drivers/net/phy/Makefile
-@@ -94,6 +94,7 @@ obj-$(CONFIG_QSEMI_PHY)		+= qsemi.o
+@@ -95,6 +95,7 @@ obj-$(CONFIG_QSEMI_PHY)		+= qsemi.o
  obj-$(CONFIG_REALTEK_PHY)	+= realtek.o
  obj-$(CONFIG_RENESAS_PHY)	+= uPD60620.o
  obj-$(CONFIG_ROCKCHIP_PHY)	+= rockchip.o
diff --git a/target/linux/mediatek/patches-6.1/601-PCI-mediatek-Assert-PERST-for-100ms-for-power-and-cl.patch b/target/linux/mediatek/patches-6.1/601-PCI-mediatek-Assert-PERST-for-100ms-for-power-and-cl.patch
index 05a6ff0fdb08d5..983fde707f2445 100644
--- a/target/linux/mediatek/patches-6.1/601-PCI-mediatek-Assert-PERST-for-100ms-for-power-and-cl.patch
+++ b/target/linux/mediatek/patches-6.1/601-PCI-mediatek-Assert-PERST-for-100ms-for-power-and-cl.patch
@@ -18,7 +18,7 @@ Acked-by: Pali Rohár <pali@kernel.org>
 
 --- a/drivers/pci/controller/pcie-mediatek.c
 +++ b/drivers/pci/controller/pcie-mediatek.c
-@@ -702,6 +702,13 @@ static int mtk_pcie_startup_port_v2(stru
+@@ -708,6 +708,13 @@ static int mtk_pcie_startup_port_v2(stru
  	 */
  	msleep(100);
  
diff --git a/target/linux/mediatek/patches-6.1/611-pcie-mediatek-gen3-PERST-for-100ms.patch b/target/linux/mediatek/patches-6.1/611-pcie-mediatek-gen3-PERST-for-100ms.patch
index 5e343d01ccef1f..32b4237d822cc6 100644
--- a/target/linux/mediatek/patches-6.1/611-pcie-mediatek-gen3-PERST-for-100ms.patch
+++ b/target/linux/mediatek/patches-6.1/611-pcie-mediatek-gen3-PERST-for-100ms.patch
@@ -1,6 +1,6 @@
 --- a/drivers/pci/controller/pcie-mediatek-gen3.c
 +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
-@@ -350,7 +350,13 @@ static int mtk_pcie_startup_port(struct
+@@ -375,7 +375,13 @@ static int mtk_pcie_startup_port(struct
  	msleep(100);
  
  	/* De-assert reset signals */
diff --git a/target/linux/mediatek/patches-6.1/615-phy-phy-mtk-xsphy-support-type-switch-by-pericfg.patch b/target/linux/mediatek/patches-6.1/615-phy-phy-mtk-xsphy-support-type-switch-by-pericfg.patch
new file mode 100644
index 00000000000000..a597f70caa549c
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/615-phy-phy-mtk-xsphy-support-type-switch-by-pericfg.patch
@@ -0,0 +1,167 @@
+From 50cefacc6c001eea1d9b1c78ba27304566f304f1 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Fri, 2 Jun 2023 13:06:26 +0800
+Subject: [PATCH] phy: mediatek: xsphy: support type switch by pericfg
+
+Patch from Sam Shih <sam.shih@mediatek.com> found in MediaTek SDK
+released under GPL.
+
+Get syscon and use it to set the PHY type.
+Extend support to PCIe and SGMII mode in addition to USB2 and USB3.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/phy/mediatek/phy-mtk-xsphy.c | 81 +++++++++++++++++++++++++++-
+ 1 file changed, 80 insertions(+), 1 deletion(-)
+
+--- a/drivers/phy/mediatek/phy-mtk-xsphy.c
++++ b/drivers/phy/mediatek/phy-mtk-xsphy.c
+@@ -11,10 +11,12 @@
+ #include <linux/clk.h>
+ #include <linux/delay.h>
+ #include <linux/iopoll.h>
++#include <linux/mfd/syscon.h>
+ #include <linux/module.h>
+ #include <linux/of_address.h>
+ #include <linux/phy/phy.h>
+ #include <linux/platform_device.h>
++#include <linux/regmap.h>
+ 
+ #include "phy-mtk-io.h"
+ 
+@@ -81,12 +83,22 @@
+ #define XSP_SR_COEF_DIVISOR	1000
+ #define XSP_FM_DET_CYCLE_CNT	1024
+ 
++/* PHY switch between pcie/usb3/sgmii */
++#define USB_PHY_SWITCH_CTRL	0x0
++#define RG_PHY_SW_TYPE		GENMASK(3, 0)
++#define RG_PHY_SW_PCIE		0x0
++#define RG_PHY_SW_USB3		0x1
++#define RG_PHY_SW_SGMII		0x2
++
+ struct xsphy_instance {
+ 	struct phy *phy;
+ 	void __iomem *port_base;
+ 	struct clk *ref_clk;	/* reference clock of anolog phy */
+ 	u32 index;
+ 	u32 type;
++	struct regmap *type_sw;
++	u32 type_sw_reg;
++	u32 type_sw_index;
+ 	/* only for HQA test */
+ 	int efuse_intr;
+ 	int efuse_tx_imp;
+@@ -259,6 +271,10 @@ static void phy_parse_property(struct mt
+ 			inst->efuse_intr, inst->efuse_tx_imp,
+ 			inst->efuse_rx_imp);
+ 		break;
++	case PHY_TYPE_PCIE:
++	case PHY_TYPE_SGMII:
++		/* nothing to do */
++		break;
+ 	default:
+ 		dev_err(xsphy->dev, "incompatible phy type\n");
+ 		return;
+@@ -305,6 +321,62 @@ static void u3_phy_props_set(struct mtk_
+ 				     RG_XTP_LN0_RX_IMPSEL, inst->efuse_rx_imp);
+ }
+ 
++/* type switch for usb3/pcie/sgmii */
++static int phy_type_syscon_get(struct xsphy_instance *instance,
++			       struct device_node *dn)
++{
++	struct of_phandle_args args;
++	int ret;
++
++	/* type switch function is optional */
++	if (!of_property_read_bool(dn, "mediatek,syscon-type"))
++		return 0;
++
++	ret = of_parse_phandle_with_fixed_args(dn, "mediatek,syscon-type",
++					       2, 0, &args);
++	if (ret)
++		return ret;
++
++	instance->type_sw_reg = args.args[0];
++	instance->type_sw_index = args.args[1] & 0x3; /* <=3 */
++	instance->type_sw = syscon_node_to_regmap(args.np);
++	of_node_put(args.np);
++	dev_info(&instance->phy->dev, "type_sw - reg %#x, index %d\n",
++		 instance->type_sw_reg, instance->type_sw_index);
++
++	return PTR_ERR_OR_ZERO(instance->type_sw);
++}
++
++static int phy_type_set(struct xsphy_instance *instance)
++{
++	int type;
++	u32 offset;
++
++	if (!instance->type_sw)
++		return 0;
++
++	switch (instance->type) {
++	case PHY_TYPE_USB3:
++		type = RG_PHY_SW_USB3;
++		break;
++	case PHY_TYPE_PCIE:
++		type = RG_PHY_SW_PCIE;
++		break;
++	case PHY_TYPE_SGMII:
++		type = RG_PHY_SW_SGMII;
++		break;
++	case PHY_TYPE_USB2:
++	default:
++		return 0;
++	}
++
++	offset = instance->type_sw_index * BITS_PER_BYTE;
++	regmap_update_bits(instance->type_sw, instance->type_sw_reg,
++			   RG_PHY_SW_TYPE << offset, type << offset);
++
++	return 0;
++}
++
+ static int mtk_phy_init(struct phy *phy)
+ {
+ 	struct xsphy_instance *inst = phy_get_drvdata(phy);
+@@ -325,6 +397,10 @@ static int mtk_phy_init(struct phy *phy)
+ 	case PHY_TYPE_USB3:
+ 		u3_phy_props_set(xsphy, inst);
+ 		break;
++	case PHY_TYPE_PCIE:
++	case PHY_TYPE_SGMII:
++		/* nothing to do, only used to set type */
++		break;
+ 	default:
+ 		dev_err(xsphy->dev, "incompatible phy type\n");
+ 		clk_disable_unprepare(inst->ref_clk);
+@@ -403,12 +479,15 @@ static struct phy *mtk_phy_xlate(struct
+ 
+ 	inst->type = args->args[0];
+ 	if (!(inst->type == PHY_TYPE_USB2 ||
+-	      inst->type == PHY_TYPE_USB3)) {
++	      inst->type == PHY_TYPE_USB3 ||
++	      inst->type == PHY_TYPE_PCIE ||
++	      inst->type == PHY_TYPE_SGMII)) {
+ 		dev_err(dev, "unsupported phy type: %d\n", inst->type);
+ 		return ERR_PTR(-EINVAL);
+ 	}
+ 
+ 	phy_parse_property(xsphy, inst);
++	phy_type_set(inst);
+ 
+ 	return inst->phy;
+ }
+@@ -515,6 +594,10 @@ static int mtk_xsphy_probe(struct platfo
+ 			retval = PTR_ERR(inst->ref_clk);
+ 			goto put_child;
+ 		}
++
++		retval = phy_type_syscon_get(inst, child_np);
++		if (retval)
++			goto put_child;
+ 	}
+ 
+ 	provider = devm_of_phy_provider_register(dev, mtk_phy_xlate);
diff --git a/target/linux/mediatek/patches-6.1/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch b/target/linux/mediatek/patches-6.1/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch
index de64eda8277d5c..76ee2fc89abdad 100644
--- a/target/linux/mediatek/patches-6.1/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch
+++ b/target/linux/mediatek/patches-6.1/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch
@@ -52,7 +52,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  struct mtk_pcie_port;
  
  /**
-@@ -1054,6 +1060,27 @@ static int mtk_pcie_setup(struct mtk_pci
+@@ -1060,6 +1066,27 @@ static int mtk_pcie_setup(struct mtk_pci
  	struct mtk_pcie_port *port, *tmp;
  	int err, slot;
  
diff --git a/target/linux/mediatek/patches-6.1/730-v6.5-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch b/target/linux/mediatek/patches-6.1/730-v6.5-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch
index f4e972f658829e..0bbf9ac7735e1d 100644
--- a/target/linux/mediatek/patches-6.1/730-v6.5-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch
+++ b/target/linux/mediatek/patches-6.1/730-v6.5-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch
@@ -24,9 +24,9 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
-@@ -12936,6 +12936,15 @@ S:	Maintained
- F:	drivers/net/pcs/pcs-mtk-lynxi.c
+@@ -12938,6 +12938,15 @@ F:	drivers/net/pcs/pcs-mtk-usxgmii.c
  F:	include/linux/pcs/pcs-mtk-lynxi.h
+ F:	include/linux/pcs/pcs-mtk-usxgmii.h
  
 +MEDIATEK ETHERNET PHY DRIVERS
 +M:	Daniel Golle <daniel@makrotopia.org>
@@ -42,7 +42,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  L:	linux-i2c@vger.kernel.org
 --- a/drivers/net/phy/Kconfig
 +++ b/drivers/net/phy/Kconfig
-@@ -311,6 +311,18 @@ config MEDIATEK_GE_PHY
+@@ -314,6 +314,18 @@ config MEDIATEK_GE_PHY
  	help
  	  Supports the MediaTek Gigabit Ethernet PHYs.
  
diff --git a/target/linux/mediatek/patches-6.1/733-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch b/target/linux/mediatek/patches-6.1/733-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch
index a3dcefd3f1824f..b4c07a4b1f0ad6 100644
--- a/target/linux/mediatek/patches-6.1/733-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch
+++ b/target/linux/mediatek/patches-6.1/733-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch
@@ -13,7 +13,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 
 --- a/drivers/net/phy/Kconfig
 +++ b/drivers/net/phy/Kconfig
-@@ -323,6 +323,13 @@ config MEDIATEK_GE_SOC_PHY
+@@ -326,6 +326,13 @@ config MEDIATEK_GE_SOC_PHY
  	  present in the SoCs efuse and will dynamically calibrate VCM
  	  (common-mode voltage) during startup.
  
diff --git a/target/linux/mediatek/patches-6.1/734-v6.8-net-phy-mediatek-ge-soc-sync-driver-with-MediaTek-SD.patch b/target/linux/mediatek/patches-6.1/734-v6.8-net-phy-mediatek-ge-soc-sync-driver-with-MediaTek-SD.patch
new file mode 100644
index 00000000000000..5daa62b6b79230
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/734-v6.8-net-phy-mediatek-ge-soc-sync-driver-with-MediaTek-SD.patch
@@ -0,0 +1,270 @@
+From f2195279c234c0f618946424b8236026126bc595 Mon Sep 17 00:00:00 2001
+Message-ID: <f2195279c234c0f618946424b8236026126bc595.1706071311.git.daniel@makrotopia.org>
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Wed, 24 Jan 2024 02:27:04 +0000
+Subject: [PATCH net] net: phy: mediatek-ge-soc: sync driver with MediaTek SDK
+To: Daniel Golle <daniel@makrotopia.org>,
+    Qingfang Deng <dqfext@gmail.com>,
+    SkyLake Huang <SkyLake.Huang@mediatek.com>,
+    Andrew Lunn <andrew@lunn.ch>,
+    Heiner Kallweit <hkallweit1@gmail.com>,
+    Russell King <linux@armlinux.org.uk>,
+    David S. Miller <davem@davemloft.net>,
+    Eric Dumazet <edumazet@google.com>,
+    Jakub Kicinski <kuba@kernel.org>,
+    Paolo Abeni <pabeni@redhat.com>,
+    Matthias Brugger <matthias.bgg@gmail.com>,
+    AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
+    netdev@vger.kernel.org,
+    linux-kernel@vger.kernel.org,
+    linux-arm-kernel@lists.infradead.org,
+    linux-mediatek@lists.infradead.org
+
+Sync initialization and calibration routines with MediaTek's reference
+driver. Improves compliance and resolves link stability issues with
+CH340 IoT devices connected to MT798x built-in PHYs.
+
+Fixes: 98c485eaf509 ("net: phy: add driver for MediaTek SoC built-in GE PHYs")
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/net/phy/mediatek-ge-soc.c | 147 ++++++++++++++++--------------
+ 1 file changed, 81 insertions(+), 66 deletions(-)
+
+--- a/drivers/net/phy/mediatek-ge-soc.c
++++ b/drivers/net/phy/mediatek-ge-soc.c
+@@ -491,7 +491,7 @@ static int tx_r50_fill_result(struct phy
+ 	u16 reg, val;
+ 
+ 	if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988)
+-		bias = -2;
++		bias = -1;
+ 
+ 	val = clamp_val(bias + tx_r50_cal_val, 0, 63);
+ 
+@@ -707,6 +707,11 @@ restore:
+ static void mt798x_phy_common_finetune(struct phy_device *phydev)
+ {
+ 	phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
++	/* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */
++	__phy_write(phydev, 0x11, 0xc71);
++	__phy_write(phydev, 0x12, 0xc);
++	__phy_write(phydev, 0x10, 0x8fae);
++
+ 	/* EnabRandUpdTrig = 1 */
+ 	__phy_write(phydev, 0x11, 0x2f00);
+ 	__phy_write(phydev, 0x12, 0xe);
+@@ -717,15 +722,56 @@ static void mt798x_phy_common_finetune(s
+ 	__phy_write(phydev, 0x12, 0x0);
+ 	__phy_write(phydev, 0x10, 0x83aa);
+ 
+-	/* TrFreeze = 0 */
++	/* FfeUpdGainForce = 1(Enable), FfeUpdGainForceVal = 4 */
++	__phy_write(phydev, 0x11, 0x240);
++	__phy_write(phydev, 0x12, 0x0);
++	__phy_write(phydev, 0x10, 0x9680);
++
++	/* TrFreeze = 0 (mt7988 default) */
+ 	__phy_write(phydev, 0x11, 0x0);
+ 	__phy_write(phydev, 0x12, 0x0);
+ 	__phy_write(phydev, 0x10, 0x9686);
+ 
++	/* SSTrKp100 = 5 */
++	/* SSTrKf100 = 6 */
++	/* SSTrKp1000Mas = 5 */
++	/* SSTrKf1000Mas = 6 */
+ 	/* SSTrKp1000Slv = 5 */
++	/* SSTrKf1000Slv = 6 */
+ 	__phy_write(phydev, 0x11, 0xbaef);
+ 	__phy_write(phydev, 0x12, 0x2e);
+ 	__phy_write(phydev, 0x10, 0x968c);
++	phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
++}
++
++static void mt7981_phy_finetune(struct phy_device *phydev)
++{
++	u16 val[8] = { 0x01ce, 0x01c1,
++		       0x020f, 0x0202,
++		       0x03d0, 0x03c0,
++		       0x0013, 0x0005 };
++	int i, k;
++
++	/* 100M eye finetune:
++	 * Keep middle level of TX MLT3 shapper as default.
++	 * Only change TX MLT3 overshoot level here.
++	 */
++	for (k = 0, i = 1; i < 12; i++) {
++		if (i % 3 == 0)
++			continue;
++		phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]);
++	}
++
++	phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
++	/* ResetSyncOffset = 6 */
++	__phy_write(phydev, 0x11, 0x600);
++	__phy_write(phydev, 0x12, 0x0);
++	__phy_write(phydev, 0x10, 0x8fc0);
++
++	/* VgaDecRate = 1 */
++	__phy_write(phydev, 0x11, 0x4c2a);
++	__phy_write(phydev, 0x12, 0x3e);
++	__phy_write(phydev, 0x10, 0x8fa4);
+ 
+ 	/* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2,
+ 	 * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2
+@@ -740,7 +786,7 @@ static void mt798x_phy_common_finetune(s
+ 	__phy_write(phydev, 0x10, 0x8ec0);
+ 	phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
+ 
+-	/* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/
++	/* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9 */
+ 	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
+ 		       MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK,
+ 		       BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9));
+@@ -773,48 +819,6 @@ static void mt798x_phy_common_finetune(s
+ 	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222);
+ }
+ 
+-static void mt7981_phy_finetune(struct phy_device *phydev)
+-{
+-	u16 val[8] = { 0x01ce, 0x01c1,
+-		       0x020f, 0x0202,
+-		       0x03d0, 0x03c0,
+-		       0x0013, 0x0005 };
+-	int i, k;
+-
+-	/* 100M eye finetune:
+-	 * Keep middle level of TX MLT3 shapper as default.
+-	 * Only change TX MLT3 overshoot level here.
+-	 */
+-	for (k = 0, i = 1; i < 12; i++) {
+-		if (i % 3 == 0)
+-			continue;
+-		phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]);
+-	}
+-
+-	phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
+-	/* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */
+-	__phy_write(phydev, 0x11, 0xc71);
+-	__phy_write(phydev, 0x12, 0xc);
+-	__phy_write(phydev, 0x10, 0x8fae);
+-
+-	/* ResetSyncOffset = 6 */
+-	__phy_write(phydev, 0x11, 0x600);
+-	__phy_write(phydev, 0x12, 0x0);
+-	__phy_write(phydev, 0x10, 0x8fc0);
+-
+-	/* VgaDecRate = 1 */
+-	__phy_write(phydev, 0x11, 0x4c2a);
+-	__phy_write(phydev, 0x12, 0x3e);
+-	__phy_write(phydev, 0x10, 0x8fa4);
+-
+-	/* FfeUpdGainForce = 4 */
+-	__phy_write(phydev, 0x11, 0x240);
+-	__phy_write(phydev, 0x12, 0x0);
+-	__phy_write(phydev, 0x10, 0x9680);
+-
+-	phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
+-}
+-
+ static void mt7988_phy_finetune(struct phy_device *phydev)
+ {
+ 	u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182,
+@@ -829,17 +833,7 @@ static void mt7988_phy_finetune(struct p
+ 	/* TCT finetune */
+ 	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5);
+ 
+-	/* Disable TX power saving */
+-	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
+-		       MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8);
+-
+ 	phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
+-
+-	/* SlvDSPreadyTime = 24, MasDSPreadyTime = 12 */
+-	__phy_write(phydev, 0x11, 0x671);
+-	__phy_write(phydev, 0x12, 0xc);
+-	__phy_write(phydev, 0x10, 0x8fae);
+-
+ 	/* ResetSyncOffset = 5 */
+ 	__phy_write(phydev, 0x11, 0x500);
+ 	__phy_write(phydev, 0x12, 0x0);
+@@ -847,13 +841,27 @@ static void mt7988_phy_finetune(struct p
+ 
+ 	/* VgaDecRate is 1 at default on mt7988 */
+ 
+-	phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
++	/* MrvlTrFix100Kp = 6, MrvlTrFix100Kf = 7,
++	 * MrvlTrFix1000Kp = 6, MrvlTrFix1000Kf = 7
++	 */
++	__phy_write(phydev, 0x11, 0xb90a);
++	__phy_write(phydev, 0x12, 0x6f);
++	__phy_write(phydev, 0x10, 0x8f82);
++
++	/* RemAckCntLimitCtrl = 1 */
++	__phy_write(phydev, 0x11, 0xfbba);
++	__phy_write(phydev, 0x12, 0xc3);
++	__phy_write(phydev, 0x10, 0x87f8);
+ 
+-	phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_2A30);
+-	/* TxClkOffset = 2 */
+-	__phy_modify(phydev, MTK_PHY_ANARG_RG, MTK_PHY_TCLKOFFSET_MASK,
+-		     FIELD_PREP(MTK_PHY_TCLKOFFSET_MASK, 0x2));
+ 	phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
++
++	/* TR_OPEN_LOOP_EN = 1, lpf_x_average = 10 */
++	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
++		       MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK,
++		       BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0xa));
++
++	/* rg_tr_lpf_cnt_val = 1023 */
++	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x3ff);
+ }
+ 
+ static void mt798x_phy_eee(struct phy_device *phydev)
+@@ -886,11 +894,11 @@ static void mt798x_phy_eee(struct phy_de
+ 		       MTK_PHY_LPI_SLV_SEND_TX_EN,
+ 		       FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120));
+ 
+-	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239,
+-		       MTK_PHY_LPI_SEND_LOC_TIMER_MASK |
+-		       MTK_PHY_LPI_TXPCS_LOC_RCV,
+-		       FIELD_PREP(MTK_PHY_LPI_SEND_LOC_TIMER_MASK, 0x117));
++	/* Keep MTK_PHY_LPI_SEND_LOC_TIMER as 375 */
++	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239,
++			   MTK_PHY_LPI_TXPCS_LOC_RCV);
+ 
++	/* This also fixes some IoT issues, such as CH340 */
+ 	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7,
+ 		       MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK,
+ 		       FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) |
+@@ -924,7 +932,7 @@ static void mt798x_phy_eee(struct phy_de
+ 	__phy_write(phydev, 0x12, 0x0);
+ 	__phy_write(phydev, 0x10, 0x9690);
+ 
+-	/* REG_EEE_st2TrKf1000 = 3 */
++	/* REG_EEE_st2TrKf1000 = 2 */
+ 	__phy_write(phydev, 0x11, 0x114f);
+ 	__phy_write(phydev, 0x12, 0x2);
+ 	__phy_write(phydev, 0x10, 0x969a);
+@@ -949,7 +957,7 @@ static void mt798x_phy_eee(struct phy_de
+ 	__phy_write(phydev, 0x12, 0x0);
+ 	__phy_write(phydev, 0x10, 0x96b8);
+ 
+-	/* REGEEE_wake_slv_tr_wait_dfesigdet_en = 1 */
++	/* REGEEE_wake_slv_tr_wait_dfesigdet_en = 0 */
+ 	__phy_write(phydev, 0x11, 0x1463);
+ 	__phy_write(phydev, 0x12, 0x0);
+ 	__phy_write(phydev, 0x10, 0x96ca);
+@@ -1461,6 +1469,13 @@ static int mt7988_phy_probe(struct phy_d
+ 	if (err)
+ 		return err;
+ 
++	/* Disable TX power saving at probing to:
++	 * 1. Meet common mode compliance test criteria
++	 * 2. Make sure that TX-VCM calibration works fine
++	 */
++	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
++		       MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8);
++
+ 	return mt798x_phy_calibration(phydev);
+ }
+ 
diff --git a/target/linux/mediatek/patches-6.1/804-pwm-add-mt7986-support.patch b/target/linux/mediatek/patches-6.1/804-v6.2-pwm-add-mt7986-support.patch
similarity index 100%
rename from target/linux/mediatek/patches-6.1/804-pwm-add-mt7986-support.patch
rename to target/linux/mediatek/patches-6.1/804-v6.2-pwm-add-mt7986-support.patch
diff --git a/target/linux/mediatek/patches-6.1/805-v6.2-thermal-drivers-mtk-use-function-pointer-for-raw_to_.patch b/target/linux/mediatek/patches-6.1/805-v6.2-thermal-drivers-mtk-use-function-pointer-for-raw_to_.patch
deleted file mode 100644
index c58ae96403ad7d..00000000000000
--- a/target/linux/mediatek/patches-6.1/805-v6.2-thermal-drivers-mtk-use-function-pointer-for-raw_to_.patch
+++ /dev/null
@@ -1,56 +0,0 @@
-From 69c17529e8418da3eec703dde31e1b01e5b0f7e8 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Wed, 18 Jan 2023 02:48:41 +0000
-Subject: [PATCH 1/2] thermal/drivers/mtk: use function pointer for
- raw_to_mcelsius
-
-Instead of having if-else logic selecting either raw_to_mcelsius_v1 or
-raw_to_mcelsius_v2 in mtk_thermal_bank_temperature introduce a function
-pointer raw_to_mcelsius to struct mtk_thermal which is initialized in the
-probe function.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/thermal/mtk_thermal.c | 17 ++++++++++-------
- 1 file changed, 10 insertions(+), 7 deletions(-)
-
---- a/drivers/thermal/mtk_thermal.c
-+++ b/drivers/thermal/mtk_thermal.c
-@@ -292,6 +292,8 @@ struct mtk_thermal {
- 
- 	const struct mtk_thermal_data *conf;
- 	struct mtk_thermal_bank banks[MAX_NUM_ZONES];
-+
-+	int (*raw_to_mcelsius)(struct mtk_thermal *mt, int sensno, s32 raw);
- };
- 
- /* MT8183 thermal sensor data */
-@@ -656,13 +658,9 @@ static int mtk_thermal_bank_temperature(
- 	for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) {
- 		raw = readl(mt->thermal_base + conf->msr[i]);
- 
--		if (mt->conf->version == MTK_THERMAL_V1) {
--			temp = raw_to_mcelsius_v1(
--				mt, conf->bank_data[bank->id].sensors[i], raw);
--		} else {
--			temp = raw_to_mcelsius_v2(
--				mt, conf->bank_data[bank->id].sensors[i], raw);
--		}
-+		temp = mt->raw_to_mcelsius(
-+			mt, conf->bank_data[bank->id].sensors[i], raw);
-+
- 
- 		/*
- 		 * The first read of a sensor often contains very high bogus
-@@ -1075,6 +1073,11 @@ static int mtk_thermal_probe(struct plat
- 		mtk_thermal_release_periodic_ts(mt, auxadc_base);
- 	}
- 
-+	if (mt->conf->version == MTK_THERMAL_V1)
-+		mt->raw_to_mcelsius = raw_to_mcelsius_v1;
-+	else
-+		mt->raw_to_mcelsius = raw_to_mcelsius_v2;
-+
- 	for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++)
- 		for (i = 0; i < mt->conf->num_banks; i++)
- 			mtk_thermal_init_bank(mt, i, apmixed_phys_base,
diff --git a/target/linux/mediatek/patches-6.1/806-v6.2-thermal-mediatek-add-support-for-MT7986-and-MT7981.patch b/target/linux/mediatek/patches-6.1/806-v6.2-thermal-mediatek-add-support-for-MT7986-and-MT7981.patch
deleted file mode 100644
index 65311d5718d9f9..00000000000000
--- a/target/linux/mediatek/patches-6.1/806-v6.2-thermal-mediatek-add-support-for-MT7986-and-MT7981.patch
+++ /dev/null
@@ -1,240 +0,0 @@
-From aa957c759b1182aee00cc35178667f849f941b42 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Wed, 30 Nov 2022 13:19:39 +0000
-Subject: [PATCH 2/2] thermal: mediatek: add support for MT7986 and MT7981
-
-Add support for V3 generation thermal found in MT7986 and MT7981 SoCs.
-Brings code to assign values from efuse as well as new function to
-convert raw temperature to millidegree celsius, as found in MediaTek's
-SDK sources (but cleaned up and de-duplicated)
-
-[1]: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/baf36c7eef477aae1f8f2653b6c29e2caf48475b
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/thermal/mtk_thermal.c | 137 ++++++++++++++++++++++++++++++++--
- 1 file changed, 132 insertions(+), 5 deletions(-)
-
---- a/drivers/thermal/mtk_thermal.c
-+++ b/drivers/thermal/mtk_thermal.c
-@@ -150,6 +150,20 @@
- #define CALIB_BUF1_VALID_V2(x)		(((x) >> 4) & 0x1)
- #define CALIB_BUF1_O_SLOPE_SIGN_V2(x)	(((x) >> 3) & 0x1)
- 
-+/*
-+ * Layout of the fuses providing the calibration data
-+ * These macros can be used for MT7981 and MT7986.
-+ */
-+#define CALIB_BUF0_ADC_GE_V3(x)		(((x) >> 0) & 0x3ff)
-+#define CALIB_BUF0_DEGC_CALI_V3(x)	(((x) >> 20) & 0x3f)
-+#define CALIB_BUF0_O_SLOPE_V3(x)	(((x) >> 26) & 0x3f)
-+#define CALIB_BUF1_VTS_TS1_V3(x)	(((x) >> 0) & 0x1ff)
-+#define CALIB_BUF1_VTS_TS2_V3(x)	(((x) >> 21) & 0x1ff)
-+#define CALIB_BUF1_VTS_TSABB_V3(x)	(((x) >> 9) & 0x1ff)
-+#define CALIB_BUF1_VALID_V3(x)		(((x) >> 18) & 0x1)
-+#define CALIB_BUF1_O_SLOPE_SIGN_V3(x)	(((x) >> 19) & 0x1)
-+#define CALIB_BUF1_ID_V3(x)		(((x) >> 20) & 0x1)
-+
- enum {
- 	VTS1,
- 	VTS2,
-@@ -163,6 +177,7 @@ enum {
- enum mtk_thermal_version {
- 	MTK_THERMAL_V1 = 1,
- 	MTK_THERMAL_V2,
-+	MTK_THERMAL_V3,
- };
- 
- /* MT2701 thermal sensors */
-@@ -245,6 +260,27 @@ enum mtk_thermal_version {
- /* The calibration coefficient of sensor  */
- #define MT8183_CALIBRATION	153
- 
-+/* AUXADC channel 11 is used for the temperature sensors */
-+#define MT7986_TEMP_AUXADC_CHANNEL	11
-+
-+/* The total number of temperature sensors in the MT7986 */
-+#define MT7986_NUM_SENSORS		1
-+
-+/* The number of banks in the MT7986 */
-+#define MT7986_NUM_ZONES		1
-+
-+/* The number of sensing points per bank */
-+#define MT7986_NUM_SENSORS_PER_ZONE	1
-+
-+/* MT7986 thermal sensors */
-+#define MT7986_TS1			0
-+
-+/* The number of controller in the MT7986 */
-+#define MT7986_NUM_CONTROLLER		1
-+
-+/* The calibration coefficient of sensor  */
-+#define MT7986_CALIBRATION		165
-+
- struct mtk_thermal;
- 
- struct thermal_bank_cfg {
-@@ -388,6 +424,14 @@ static const int mt7622_mux_values[MT762
- static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 };
- static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, };
- 
-+/* MT7986 thermal sensor data */
-+static const int mt7986_bank_data[MT7986_NUM_SENSORS] = { MT7986_TS1, };
-+static const int mt7986_msr[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, };
-+static const int mt7986_adcpnp[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, };
-+static const int mt7986_mux_values[MT7986_NUM_SENSORS] = { 0, };
-+static const int mt7986_vts_index[MT7986_NUM_SENSORS] = { VTS1 };
-+static const int mt7986_tc_offset[MT7986_NUM_CONTROLLER] = { 0x0, };
-+
- /*
-  * The MT8173 thermal controller has four banks. Each bank can read up to
-  * four temperature sensors simultaneously. The MT8173 has a total of 5
-@@ -551,6 +595,30 @@ static const struct mtk_thermal_data mt8
- 	.version = MTK_THERMAL_V1,
- };
- 
-+/*
-+ * MT7986 uses AUXADC Channel 11 for raw data access.
-+ */
-+static const struct mtk_thermal_data mt7986_thermal_data = {
-+	.auxadc_channel = MT7986_TEMP_AUXADC_CHANNEL,
-+	.num_banks = MT7986_NUM_ZONES,
-+	.num_sensors = MT7986_NUM_SENSORS,
-+	.vts_index = mt7986_vts_index,
-+	.cali_val = MT7986_CALIBRATION,
-+	.num_controller = MT7986_NUM_CONTROLLER,
-+	.controller_offset = mt7986_tc_offset,
-+	.need_switch_bank = true,
-+	.bank_data = {
-+		{
-+			.num_sensors = 1,
-+			.sensors = mt7986_bank_data,
-+		},
-+	},
-+	.msr = mt7986_msr,
-+	.adcpnp = mt7986_adcpnp,
-+	.sensor_mux_values = mt7986_mux_values,
-+	.version = MTK_THERMAL_V3,
-+};
-+
- /**
-  * raw_to_mcelsius - convert a raw ADC value to mcelsius
-  * @mt:	The thermal controller
-@@ -605,6 +673,22 @@ static int raw_to_mcelsius_v2(struct mtk
- 	return (format_2 - tmp) * 100;
- }
- 
-+static int raw_to_mcelsius_v3(struct mtk_thermal *mt, int sensno, s32 raw)
-+{
-+	s32 tmp;
-+
-+	if (raw == 0)
-+		return 0;
-+
-+	raw &= 0xfff;
-+	tmp = 100000 * 15 / 16 * 10000;
-+	tmp /= 4096 - 512 + mt->adc_ge;
-+	tmp /= 1490;
-+	tmp *= raw - mt->vts[sensno] - 2900;
-+
-+	return mt->degc_cali * 500 - tmp;
-+}
-+
- /**
-  * mtk_thermal_get_bank - get bank
-  * @bank:	The bank
-@@ -885,6 +969,25 @@ static int mtk_thermal_extract_efuse_v2(
- 	return 0;
- }
- 
-+static int mtk_thermal_extract_efuse_v3(struct mtk_thermal *mt, u32 *buf)
-+{
-+	if (!CALIB_BUF1_VALID_V3(buf[1]))
-+		return -EINVAL;
-+
-+	mt->adc_ge = CALIB_BUF0_ADC_GE_V3(buf[0]);
-+	mt->degc_cali = CALIB_BUF0_DEGC_CALI_V3(buf[0]);
-+	mt->o_slope = CALIB_BUF0_O_SLOPE_V3(buf[0]);
-+	mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V3(buf[1]);
-+	mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V3(buf[1]);
-+	mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V3(buf[1]);
-+	mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V3(buf[1]);
-+
-+	if (CALIB_BUF1_ID_V3(buf[1]) == 0)
-+		mt->o_slope = 0;
-+
-+	return 0;
-+}
-+
- static int mtk_thermal_get_calibration_data(struct device *dev,
- 					    struct mtk_thermal *mt)
- {
-@@ -895,6 +998,7 @@ static int mtk_thermal_get_calibration_d
- 
- 	/* Start with default values */
- 	mt->adc_ge = 512;
-+	mt->adc_oe = 512;
- 	for (i = 0; i < mt->conf->num_sensors; i++)
- 		mt->vts[i] = 260;
- 	mt->degc_cali = 40;
-@@ -920,10 +1024,20 @@ static int mtk_thermal_get_calibration_d
- 		goto out;
- 	}
- 
--	if (mt->conf->version == MTK_THERMAL_V1)
-+	switch (mt->conf->version) {
-+	case MTK_THERMAL_V1:
- 		ret = mtk_thermal_extract_efuse_v1(mt, buf);
--	else
-+		break;
-+	case MTK_THERMAL_V2:
- 		ret = mtk_thermal_extract_efuse_v2(mt, buf);
-+		break;
-+	case MTK_THERMAL_V3:
-+		ret = mtk_thermal_extract_efuse_v3(mt, buf);
-+		break;
-+	default:
-+		ret = -EINVAL;
-+		break;
-+	}
- 
- 	if (ret) {
- 		dev_info(dev, "Device not calibrated, using default calibration values\n");
-@@ -954,6 +1068,10 @@ static const struct of_device_id mtk_the
- 		.data = (void *)&mt7622_thermal_data,
- 	},
- 	{
-+		.compatible = "mediatek,mt7986-thermal",
-+		.data = (void *)&mt7986_thermal_data,
-+	},
-+	{
- 		.compatible = "mediatek,mt8183-thermal",
- 		.data = (void *)&mt8183_thermal_data,
- 	}, {
-@@ -1068,15 +1186,24 @@ static int mtk_thermal_probe(struct plat
- 		goto err_disable_clk_auxadc;
- 	}
- 
--	if (mt->conf->version == MTK_THERMAL_V2) {
-+	if (mt->conf->version != MTK_THERMAL_V1) {
- 		mtk_thermal_turn_on_buffer(apmixed_base);
- 		mtk_thermal_release_periodic_ts(mt, auxadc_base);
- 	}
- 
--	if (mt->conf->version == MTK_THERMAL_V1)
-+	switch (mt->conf->version) {
-+	case MTK_THERMAL_V1:
- 		mt->raw_to_mcelsius = raw_to_mcelsius_v1;
--	else
-+		break;
-+	case MTK_THERMAL_V2:
- 		mt->raw_to_mcelsius = raw_to_mcelsius_v2;
-+		break;
-+	case MTK_THERMAL_V3:
-+		mt->raw_to_mcelsius = raw_to_mcelsius_v3;
-+		break;
-+	default:
-+		break;
-+	}
- 
- 	for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++)
- 		for (i = 0; i < mt->conf->num_banks; i++)
diff --git a/target/linux/mediatek/patches-6.1/830-v6.3-01-thermal-drivers-mtk_thermal-Fix-kernel-doc-function-.patch b/target/linux/mediatek/patches-6.1/830-v6.3-01-thermal-drivers-mtk_thermal-Fix-kernel-doc-function-.patch
new file mode 100644
index 00000000000000..694b73a2b1c3b0
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.3-01-thermal-drivers-mtk_thermal-Fix-kernel-doc-function-.patch
@@ -0,0 +1,37 @@
+From f167da186acf90847e1a6d3716e253825a6218ec Mon Sep 17 00:00:00 2001
+From: Randy Dunlap <rdunlap@infradead.org>
+Date: Thu, 12 Jan 2023 22:44:49 -0800
+Subject: [PATCH 01/42] thermal/drivers/mtk_thermal: Fix kernel-doc function
+ name
+
+Use the correct function name in a kernel-doc comment to prevent
+a warning:
+
+drivers/thermal/mtk_thermal.c:562: warning: expecting prototype for raw_to_mcelsius(). Prototype was for raw_to_mcelsius_v1() instead
+
+Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
+Cc: "Rafael J. Wysocki" <rafael@kernel.org>
+Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
+Cc: Amit Kucheria <amitk@kernel.org>
+Cc: Zhang Rui <rui.zhang@intel.com>
+Cc: Matthias Brugger <matthias.bgg@gmail.com>
+Cc: linux-pm@vger.kernel.org
+Cc: linux-arm-kernel@lists.infradead.org
+Cc: linux-mediatek@lists.infradead.org
+Link: https://lore.kernel.org/r/20230113064449.15061-1-rdunlap@infradead.org
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+---
+ drivers/thermal/mtk_thermal.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/thermal/mtk_thermal.c
++++ b/drivers/thermal/mtk_thermal.c
+@@ -550,7 +550,7 @@ static const struct mtk_thermal_data mt8
+ };
+ 
+ /**
+- * raw_to_mcelsius - convert a raw ADC value to mcelsius
++ * raw_to_mcelsius_v1 - convert a raw ADC value to mcelsius
+  * @mt:	The thermal controller
+  * @sensno:	sensor number
+  * @raw:	raw ADC value
diff --git a/target/linux/mediatek/patches-6.1/830-v6.3-02-thermal-drivers-mtk_thermal-Use-devm_platform_get_an.patch b/target/linux/mediatek/patches-6.1/830-v6.3-02-thermal-drivers-mtk_thermal-Use-devm_platform_get_an.patch
new file mode 100644
index 00000000000000..aaed9d7e90c34c
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.3-02-thermal-drivers-mtk_thermal-Use-devm_platform_get_an.patch
@@ -0,0 +1,37 @@
+From 255509232417ee71fd606cb957d44cf6544f0c43 Mon Sep 17 00:00:00 2001
+From: ye xingchen <ye.xingchen@zte.com.cn>
+Date: Wed, 18 Jan 2023 16:37:47 +0800
+Subject: [PATCH 02/42] thermal/drivers/mtk_thermal: Use
+ devm_platform_get_and_ioremap_resource()
+
+Convert platform_get_resource(), devm_ioremap_resource() to a single
+call to devm_platform_get_and_ioremap_resource(), as this is exactly
+what this function does.
+
+Signed-off-by: ye xingchen <ye.xingchen@zte.com.cn>
+Link: https://lore.kernel.org/r/202301181637472073620@zte.com.cn
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+---
+ drivers/thermal/mtk_thermal.c | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+--- a/drivers/thermal/mtk_thermal.c
++++ b/drivers/thermal/mtk_thermal.c
+@@ -990,7 +990,6 @@ static int mtk_thermal_probe(struct plat
+ 	int ret, i, ctrl_id;
+ 	struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node;
+ 	struct mtk_thermal *mt;
+-	struct resource *res;
+ 	u64 auxadc_phys_base, apmixed_phys_base;
+ 	struct thermal_zone_device *tzdev;
+ 	void __iomem *apmixed_base, *auxadc_base;
+@@ -1009,8 +1008,7 @@ static int mtk_thermal_probe(struct plat
+ 	if (IS_ERR(mt->clk_auxadc))
+ 		return PTR_ERR(mt->clk_auxadc);
+ 
+-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+-	mt->thermal_base = devm_ioremap_resource(&pdev->dev, res);
++	mt->thermal_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
+ 	if (IS_ERR(mt->thermal_base))
+ 		return PTR_ERR(mt->thermal_base);
+ 
diff --git a/target/linux/mediatek/patches-6.1/830-v6.3-03-thermal-drivers-mtk-Use-function-pointer-for-raw_to_.patch b/target/linux/mediatek/patches-6.1/830-v6.3-03-thermal-drivers-mtk-Use-function-pointer-for-raw_to_.patch
new file mode 100644
index 00000000000000..215b0fd7dec997
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.3-03-thermal-drivers-mtk-Use-function-pointer-for-raw_to_.patch
@@ -0,0 +1,60 @@
+From ca86dbd309ba03bef38ae91f037e2030bb671ab7 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Wed, 18 Jan 2023 15:40:39 +0000
+Subject: [PATCH 03/42] thermal/drivers/mtk: Use function pointer for
+ raw_to_mcelsius
+
+Instead of having if-else logic selecting either raw_to_mcelsius_v1 or
+raw_to_mcelsius_v2 in mtk_thermal_bank_temperature introduce a function
+pointer raw_to_mcelsius to struct mtk_thermal which is initialized in the
+probe function.
+
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
+Link: https://lore.kernel.org/r/69c17529e8418da3eec703dde31e1b01e5b0f7e8.1674055882.git.daniel@makrotopia.org
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+---
+ drivers/thermal/mtk_thermal.c | 17 ++++++++++-------
+ 1 file changed, 10 insertions(+), 7 deletions(-)
+
+--- a/drivers/thermal/mtk_thermal.c
++++ b/drivers/thermal/mtk_thermal.c
+@@ -292,6 +292,8 @@ struct mtk_thermal {
+ 
+ 	const struct mtk_thermal_data *conf;
+ 	struct mtk_thermal_bank banks[MAX_NUM_ZONES];
++
++	int (*raw_to_mcelsius)(struct mtk_thermal *mt, int sensno, s32 raw);
+ };
+ 
+ /* MT8183 thermal sensor data */
+@@ -656,13 +658,9 @@ static int mtk_thermal_bank_temperature(
+ 	for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) {
+ 		raw = readl(mt->thermal_base + conf->msr[i]);
+ 
+-		if (mt->conf->version == MTK_THERMAL_V1) {
+-			temp = raw_to_mcelsius_v1(
+-				mt, conf->bank_data[bank->id].sensors[i], raw);
+-		} else {
+-			temp = raw_to_mcelsius_v2(
+-				mt, conf->bank_data[bank->id].sensors[i], raw);
+-		}
++		temp = mt->raw_to_mcelsius(
++			mt, conf->bank_data[bank->id].sensors[i], raw);
++
+ 
+ 		/*
+ 		 * The first read of a sensor often contains very high bogus
+@@ -1073,6 +1071,11 @@ static int mtk_thermal_probe(struct plat
+ 		mtk_thermal_release_periodic_ts(mt, auxadc_base);
+ 	}
+ 
++	if (mt->conf->version == MTK_THERMAL_V1)
++		mt->raw_to_mcelsius = raw_to_mcelsius_v1;
++	else
++		mt->raw_to_mcelsius = raw_to_mcelsius_v2;
++
+ 	for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++)
+ 		for (i = 0; i < mt->conf->num_banks; i++)
+ 			mtk_thermal_init_bank(mt, i, apmixed_phys_base,
diff --git a/target/linux/mediatek/patches-6.1/830-v6.3-04-thermal-drivers-mtk-Add-support-for-MT7986-and-MT798.patch b/target/linux/mediatek/patches-6.1/830-v6.3-04-thermal-drivers-mtk-Add-support-for-MT7986-and-MT798.patch
new file mode 100644
index 00000000000000..ef2006775a34d4
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.3-04-thermal-drivers-mtk-Add-support-for-MT7986-and-MT798.patch
@@ -0,0 +1,236 @@
+From aec1d89dccc7cba04fdb3e52dfda328f3302ba17 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Wed, 18 Jan 2023 15:40:58 +0000
+Subject: [PATCH 04/42] thermal/drivers/mtk: Add support for MT7986 and MT7981
+
+Add support for V3 generation thermal found in MT7986 and MT7981 SoCs.
+Brings code to assign values from efuse as well as new function to
+convert raw temperature to millidegree celsius, as found in MediaTek's
+SDK sources (but cleaned up and de-duplicated)
+
+[1]: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/baf36c7eef477aae1f8f2653b6c29e2caf48475b
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Link: https://lore.kernel.org/r/2d341fc45266217249586eb4bd3be3ac4ca83a12.1674055882.git.daniel@makrotopia.org
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+---
+ drivers/thermal/mtk_thermal.c | 128 ++++++++++++++++++++++++++++++++--
+ 1 file changed, 124 insertions(+), 4 deletions(-)
+
+--- a/drivers/thermal/mtk_thermal.c
++++ b/drivers/thermal/mtk_thermal.c
+@@ -150,6 +150,20 @@
+ #define CALIB_BUF1_VALID_V2(x)		(((x) >> 4) & 0x1)
+ #define CALIB_BUF1_O_SLOPE_SIGN_V2(x)	(((x) >> 3) & 0x1)
+ 
++/*
++ * Layout of the fuses providing the calibration data
++ * These macros can be used for MT7981 and MT7986.
++ */
++#define CALIB_BUF0_ADC_GE_V3(x)		(((x) >> 0) & 0x3ff)
++#define CALIB_BUF0_DEGC_CALI_V3(x)	(((x) >> 20) & 0x3f)
++#define CALIB_BUF0_O_SLOPE_V3(x)	(((x) >> 26) & 0x3f)
++#define CALIB_BUF1_VTS_TS1_V3(x)	(((x) >> 0) & 0x1ff)
++#define CALIB_BUF1_VTS_TS2_V3(x)	(((x) >> 21) & 0x1ff)
++#define CALIB_BUF1_VTS_TSABB_V3(x)	(((x) >> 9) & 0x1ff)
++#define CALIB_BUF1_VALID_V3(x)		(((x) >> 18) & 0x1)
++#define CALIB_BUF1_O_SLOPE_SIGN_V3(x)	(((x) >> 19) & 0x1)
++#define CALIB_BUF1_ID_V3(x)		(((x) >> 20) & 0x1)
++
+ enum {
+ 	VTS1,
+ 	VTS2,
+@@ -163,6 +177,7 @@ enum {
+ enum mtk_thermal_version {
+ 	MTK_THERMAL_V1 = 1,
+ 	MTK_THERMAL_V2,
++	MTK_THERMAL_V3,
+ };
+ 
+ /* MT2701 thermal sensors */
+@@ -245,6 +260,27 @@ enum mtk_thermal_version {
+ /* The calibration coefficient of sensor  */
+ #define MT8183_CALIBRATION	153
+ 
++/* AUXADC channel 11 is used for the temperature sensors */
++#define MT7986_TEMP_AUXADC_CHANNEL	11
++
++/* The total number of temperature sensors in the MT7986 */
++#define MT7986_NUM_SENSORS		1
++
++/* The number of banks in the MT7986 */
++#define MT7986_NUM_ZONES		1
++
++/* The number of sensing points per bank */
++#define MT7986_NUM_SENSORS_PER_ZONE	1
++
++/* MT7986 thermal sensors */
++#define MT7986_TS1			0
++
++/* The number of controller in the MT7986 */
++#define MT7986_NUM_CONTROLLER		1
++
++/* The calibration coefficient of sensor  */
++#define MT7986_CALIBRATION		165
++
+ struct mtk_thermal;
+ 
+ struct thermal_bank_cfg {
+@@ -388,6 +424,14 @@ static const int mt7622_mux_values[MT762
+ static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 };
+ static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, };
+ 
++/* MT7986 thermal sensor data */
++static const int mt7986_bank_data[MT7986_NUM_SENSORS] = { MT7986_TS1, };
++static const int mt7986_msr[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, };
++static const int mt7986_adcpnp[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, };
++static const int mt7986_mux_values[MT7986_NUM_SENSORS] = { 0, };
++static const int mt7986_vts_index[MT7986_NUM_SENSORS] = { VTS1 };
++static const int mt7986_tc_offset[MT7986_NUM_CONTROLLER] = { 0x0, };
++
+ /*
+  * The MT8173 thermal controller has four banks. Each bank can read up to
+  * four temperature sensors simultaneously. The MT8173 has a total of 5
+@@ -551,6 +595,30 @@ static const struct mtk_thermal_data mt8
+ 	.version = MTK_THERMAL_V1,
+ };
+ 
++/*
++ * MT7986 uses AUXADC Channel 11 for raw data access.
++ */
++static const struct mtk_thermal_data mt7986_thermal_data = {
++	.auxadc_channel = MT7986_TEMP_AUXADC_CHANNEL,
++	.num_banks = MT7986_NUM_ZONES,
++	.num_sensors = MT7986_NUM_SENSORS,
++	.vts_index = mt7986_vts_index,
++	.cali_val = MT7986_CALIBRATION,
++	.num_controller = MT7986_NUM_CONTROLLER,
++	.controller_offset = mt7986_tc_offset,
++	.need_switch_bank = true,
++	.bank_data = {
++		{
++			.num_sensors = 1,
++			.sensors = mt7986_bank_data,
++		},
++	},
++	.msr = mt7986_msr,
++	.adcpnp = mt7986_adcpnp,
++	.sensor_mux_values = mt7986_mux_values,
++	.version = MTK_THERMAL_V3,
++};
++
+ /**
+  * raw_to_mcelsius_v1 - convert a raw ADC value to mcelsius
+  * @mt:	The thermal controller
+@@ -605,6 +673,22 @@ static int raw_to_mcelsius_v2(struct mtk
+ 	return (format_2 - tmp) * 100;
+ }
+ 
++static int raw_to_mcelsius_v3(struct mtk_thermal *mt, int sensno, s32 raw)
++{
++	s32 tmp;
++
++	if (raw == 0)
++		return 0;
++
++	raw &= 0xfff;
++	tmp = 100000 * 15 / 16 * 10000;
++	tmp /= 4096 - 512 + mt->adc_ge;
++	tmp /= 1490;
++	tmp *= raw - mt->vts[sensno] - 2900;
++
++	return mt->degc_cali * 500 - tmp;
++}
++
+ /**
+  * mtk_thermal_get_bank - get bank
+  * @bank:	The bank
+@@ -885,6 +969,25 @@ static int mtk_thermal_extract_efuse_v2(
+ 	return 0;
+ }
+ 
++static int mtk_thermal_extract_efuse_v3(struct mtk_thermal *mt, u32 *buf)
++{
++	if (!CALIB_BUF1_VALID_V3(buf[1]))
++		return -EINVAL;
++
++	mt->adc_ge = CALIB_BUF0_ADC_GE_V3(buf[0]);
++	mt->degc_cali = CALIB_BUF0_DEGC_CALI_V3(buf[0]);
++	mt->o_slope = CALIB_BUF0_O_SLOPE_V3(buf[0]);
++	mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V3(buf[1]);
++	mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V3(buf[1]);
++	mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V3(buf[1]);
++	mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V3(buf[1]);
++
++	if (CALIB_BUF1_ID_V3(buf[1]) == 0)
++		mt->o_slope = 0;
++
++	return 0;
++}
++
+ static int mtk_thermal_get_calibration_data(struct device *dev,
+ 					    struct mtk_thermal *mt)
+ {
+@@ -895,6 +998,7 @@ static int mtk_thermal_get_calibration_d
+ 
+ 	/* Start with default values */
+ 	mt->adc_ge = 512;
++	mt->adc_oe = 512;
+ 	for (i = 0; i < mt->conf->num_sensors; i++)
+ 		mt->vts[i] = 260;
+ 	mt->degc_cali = 40;
+@@ -920,10 +1024,20 @@ static int mtk_thermal_get_calibration_d
+ 		goto out;
+ 	}
+ 
+-	if (mt->conf->version == MTK_THERMAL_V1)
++	switch (mt->conf->version) {
++	case MTK_THERMAL_V1:
+ 		ret = mtk_thermal_extract_efuse_v1(mt, buf);
+-	else
++		break;
++	case MTK_THERMAL_V2:
+ 		ret = mtk_thermal_extract_efuse_v2(mt, buf);
++		break;
++	case MTK_THERMAL_V3:
++		ret = mtk_thermal_extract_efuse_v3(mt, buf);
++		break;
++	default:
++		ret = -EINVAL;
++		break;
++	}
+ 
+ 	if (ret) {
+ 		dev_info(dev, "Device not calibrated, using default calibration values\n");
+@@ -954,6 +1068,10 @@ static const struct of_device_id mtk_the
+ 		.data = (void *)&mt7622_thermal_data,
+ 	},
+ 	{
++		.compatible = "mediatek,mt7986-thermal",
++		.data = (void *)&mt7986_thermal_data,
++	},
++	{
+ 		.compatible = "mediatek,mt8183-thermal",
+ 		.data = (void *)&mt8183_thermal_data,
+ 	}, {
+@@ -1066,15 +1184,17 @@ static int mtk_thermal_probe(struct plat
+ 		goto err_disable_clk_auxadc;
+ 	}
+ 
+-	if (mt->conf->version == MTK_THERMAL_V2) {
++	if (mt->conf->version != MTK_THERMAL_V1) {
+ 		mtk_thermal_turn_on_buffer(apmixed_base);
+ 		mtk_thermal_release_periodic_ts(mt, auxadc_base);
+ 	}
+ 
+ 	if (mt->conf->version == MTK_THERMAL_V1)
+ 		mt->raw_to_mcelsius = raw_to_mcelsius_v1;
+-	else
++	else if (mt->conf->version == MTK_THERMAL_V2)
+ 		mt->raw_to_mcelsius = raw_to_mcelsius_v2;
++	else
++		mt->raw_to_mcelsius = raw_to_mcelsius_v3;
+ 
+ 	for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++)
+ 		for (i = 0; i < mt->conf->num_banks; i++)
diff --git a/target/linux/mediatek/patches-6.1/830-v6.3-05-thermal-drivers-mediatek-Relocate-driver-to-mediatek.patch b/target/linux/mediatek/patches-6.1/830-v6.3-05-thermal-drivers-mediatek-Relocate-driver-to-mediatek.patch
new file mode 100644
index 00000000000000..e102a338cdc344
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.3-05-thermal-drivers-mediatek-Relocate-driver-to-mediatek.patch
@@ -0,0 +1,2602 @@
+From 5e3aac197a74914ccec2732a89c29d960730d28f Mon Sep 17 00:00:00 2001
+From: Balsam CHIHI <bchihi@baylibre.com>
+Date: Thu, 9 Feb 2023 11:56:23 +0100
+Subject: [PATCH 05/42] thermal/drivers/mediatek: Relocate driver to mediatek
+ folder
+
+Add MediaTek proprietary folder to upstream more thermal zone and cooler
+drivers, relocate the original thermal controller driver to it, and rename it
+as "auxadc_thermal.c" to show its purpose more clearly.
+
+Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Link: https://lore.kernel.org/r/20230209105628.50294-2-bchihi@baylibre.com
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+---
+ drivers/thermal/Kconfig                       | 14 ++++---------
+ drivers/thermal/Makefile                      |  2 +-
+ drivers/thermal/mediatek/Kconfig              | 21 +++++++++++++++++++
+ drivers/thermal/mediatek/Makefile             |  1 +
+ .../auxadc_thermal.c}                         |  2 +-
+ 5 files changed, 28 insertions(+), 12 deletions(-)
+ create mode 100644 drivers/thermal/mediatek/Kconfig
+ create mode 100644 drivers/thermal/mediatek/Makefile
+ rename drivers/thermal/{mtk_thermal.c => mediatek/auxadc_thermal.c} (99%)
+
+--- a/drivers/thermal/Kconfig
++++ b/drivers/thermal/Kconfig
+@@ -412,16 +412,10 @@ config DA9062_THERMAL
+ 	  zone.
+ 	  Compatible with the DA9062 and DA9061 PMICs.
+ 
+-config MTK_THERMAL
+-	tristate "Temperature sensor driver for mediatek SoCs"
+-	depends on ARCH_MEDIATEK || COMPILE_TEST
+-	depends on HAS_IOMEM
+-	depends on NVMEM || NVMEM=n
+-	depends on RESET_CONTROLLER
+-	default y
+-	help
+-	  Enable this option if you want to have support for thermal management
+-	  controller present in Mediatek SoCs
++menu "Mediatek thermal drivers"
++depends on ARCH_MEDIATEK || COMPILE_TEST
++source "drivers/thermal/mediatek/Kconfig"
++endmenu
+ 
+ config AMLOGIC_THERMAL
+ 	tristate "Amlogic Thermal Support"
+--- a/drivers/thermal/Makefile
++++ b/drivers/thermal/Makefile
+@@ -55,7 +55,7 @@ obj-y				+= st/
+ obj-y				+= qcom/
+ obj-y				+= tegra/
+ obj-$(CONFIG_HISI_THERMAL)     += hisi_thermal.o
+-obj-$(CONFIG_MTK_THERMAL)	+= mtk_thermal.o
++obj-y				+= mediatek/
+ obj-$(CONFIG_GENERIC_ADC_THERMAL)	+= thermal-generic-adc.o
+ obj-$(CONFIG_UNIPHIER_THERMAL)	+= uniphier_thermal.o
+ obj-$(CONFIG_AMLOGIC_THERMAL)     += amlogic_thermal.o
+--- /dev/null
++++ b/drivers/thermal/mediatek/Kconfig
+@@ -0,0 +1,21 @@
++config MTK_THERMAL
++	tristate "MediaTek thermal drivers"
++	depends on THERMAL_OF
++	help
++	  This is the option for MediaTek thermal software solutions.
++	  Please enable corresponding options to get temperature
++	  information from thermal sensors or turn on throttle
++	  mechaisms for thermal mitigation.
++
++if MTK_THERMAL
++
++config MTK_SOC_THERMAL
++	tristate "AUXADC temperature sensor driver for MediaTek SoCs"
++	depends on HAS_IOMEM
++	help
++	  Enable this option if you want to get SoC temperature
++	  information for MediaTek platforms.
++	  This driver configures thermal controllers to collect
++	  temperature via AUXADC interface.
++
++endif
+--- /dev/null
++++ b/drivers/thermal/mediatek/Makefile
+@@ -0,0 +1 @@
++obj-$(CONFIG_MTK_SOC_THERMAL)	+= auxadc_thermal.o
+--- a/drivers/thermal/mtk_thermal.c
++++ /dev/null
+@@ -1,1254 +0,0 @@
+-// SPDX-License-Identifier: GPL-2.0-only
+-/*
+- * Copyright (c) 2015 MediaTek Inc.
+- * Author: Hanyi Wu <hanyi.wu@mediatek.com>
+- *         Sascha Hauer <s.hauer@pengutronix.de>
+- *         Dawei Chien <dawei.chien@mediatek.com>
+- *         Louis Yu <louis.yu@mediatek.com>
+- */
+-
+-#include <linux/clk.h>
+-#include <linux/delay.h>
+-#include <linux/interrupt.h>
+-#include <linux/kernel.h>
+-#include <linux/module.h>
+-#include <linux/nvmem-consumer.h>
+-#include <linux/of.h>
+-#include <linux/of_address.h>
+-#include <linux/of_device.h>
+-#include <linux/platform_device.h>
+-#include <linux/slab.h>
+-#include <linux/io.h>
+-#include <linux/thermal.h>
+-#include <linux/reset.h>
+-#include <linux/types.h>
+-
+-#include "thermal_hwmon.h"
+-
+-/* AUXADC Registers */
+-#define AUXADC_CON1_SET_V	0x008
+-#define AUXADC_CON1_CLR_V	0x00c
+-#define AUXADC_CON2_V		0x010
+-#define AUXADC_DATA(channel)	(0x14 + (channel) * 4)
+-
+-#define APMIXED_SYS_TS_CON1	0x604
+-
+-/* Thermal Controller Registers */
+-#define TEMP_MONCTL0		0x000
+-#define TEMP_MONCTL1		0x004
+-#define TEMP_MONCTL2		0x008
+-#define TEMP_MONIDET0		0x014
+-#define TEMP_MONIDET1		0x018
+-#define TEMP_MSRCTL0		0x038
+-#define TEMP_MSRCTL1		0x03c
+-#define TEMP_AHBPOLL		0x040
+-#define TEMP_AHBTO		0x044
+-#define TEMP_ADCPNP0		0x048
+-#define TEMP_ADCPNP1		0x04c
+-#define TEMP_ADCPNP2		0x050
+-#define TEMP_ADCPNP3		0x0b4
+-
+-#define TEMP_ADCMUX		0x054
+-#define TEMP_ADCEN		0x060
+-#define TEMP_PNPMUXADDR		0x064
+-#define TEMP_ADCMUXADDR		0x068
+-#define TEMP_ADCENADDR		0x074
+-#define TEMP_ADCVALIDADDR	0x078
+-#define TEMP_ADCVOLTADDR	0x07c
+-#define TEMP_RDCTRL		0x080
+-#define TEMP_ADCVALIDMASK	0x084
+-#define TEMP_ADCVOLTAGESHIFT	0x088
+-#define TEMP_ADCWRITECTRL	0x08c
+-#define TEMP_MSR0		0x090
+-#define TEMP_MSR1		0x094
+-#define TEMP_MSR2		0x098
+-#define TEMP_MSR3		0x0B8
+-
+-#define TEMP_SPARE0		0x0f0
+-
+-#define TEMP_ADCPNP0_1          0x148
+-#define TEMP_ADCPNP1_1          0x14c
+-#define TEMP_ADCPNP2_1          0x150
+-#define TEMP_MSR0_1             0x190
+-#define TEMP_MSR1_1             0x194
+-#define TEMP_MSR2_1             0x198
+-#define TEMP_ADCPNP3_1          0x1b4
+-#define TEMP_MSR3_1             0x1B8
+-
+-#define PTPCORESEL		0x400
+-
+-#define TEMP_MONCTL1_PERIOD_UNIT(x)	((x) & 0x3ff)
+-
+-#define TEMP_MONCTL2_FILTER_INTERVAL(x)	(((x) & 0x3ff) << 16)
+-#define TEMP_MONCTL2_SENSOR_INTERVAL(x)	((x) & 0x3ff)
+-
+-#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x)	(x)
+-
+-#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE		BIT(0)
+-#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE		BIT(1)
+-
+-#define TEMP_ADCVALIDMASK_VALID_HIGH		BIT(5)
+-#define TEMP_ADCVALIDMASK_VALID_POS(bit)	(bit)
+-
+-/* MT8173 thermal sensors */
+-#define MT8173_TS1	0
+-#define MT8173_TS2	1
+-#define MT8173_TS3	2
+-#define MT8173_TS4	3
+-#define MT8173_TSABB	4
+-
+-/* AUXADC channel 11 is used for the temperature sensors */
+-#define MT8173_TEMP_AUXADC_CHANNEL	11
+-
+-/* The total number of temperature sensors in the MT8173 */
+-#define MT8173_NUM_SENSORS		5
+-
+-/* The number of banks in the MT8173 */
+-#define MT8173_NUM_ZONES		4
+-
+-/* The number of sensing points per bank */
+-#define MT8173_NUM_SENSORS_PER_ZONE	4
+-
+-/* The number of controller in the MT8173 */
+-#define MT8173_NUM_CONTROLLER		1
+-
+-/* The calibration coefficient of sensor  */
+-#define MT8173_CALIBRATION	165
+-
+-/*
+- * Layout of the fuses providing the calibration data
+- * These macros could be used for MT8183, MT8173, MT2701, and MT2712.
+- * MT8183 has 6 sensors and needs 6 VTS calibration data.
+- * MT8173 has 5 sensors and needs 5 VTS calibration data.
+- * MT2701 has 3 sensors and needs 3 VTS calibration data.
+- * MT2712 has 4 sensors and needs 4 VTS calibration data.
+- */
+-#define CALIB_BUF0_VALID_V1		BIT(0)
+-#define CALIB_BUF1_ADC_GE_V1(x)		(((x) >> 22) & 0x3ff)
+-#define CALIB_BUF0_VTS_TS1_V1(x)	(((x) >> 17) & 0x1ff)
+-#define CALIB_BUF0_VTS_TS2_V1(x)	(((x) >> 8) & 0x1ff)
+-#define CALIB_BUF1_VTS_TS3_V1(x)	(((x) >> 0) & 0x1ff)
+-#define CALIB_BUF2_VTS_TS4_V1(x)	(((x) >> 23) & 0x1ff)
+-#define CALIB_BUF2_VTS_TS5_V1(x)	(((x) >> 5) & 0x1ff)
+-#define CALIB_BUF2_VTS_TSABB_V1(x)	(((x) >> 14) & 0x1ff)
+-#define CALIB_BUF0_DEGC_CALI_V1(x)	(((x) >> 1) & 0x3f)
+-#define CALIB_BUF0_O_SLOPE_V1(x)	(((x) >> 26) & 0x3f)
+-#define CALIB_BUF0_O_SLOPE_SIGN_V1(x)	(((x) >> 7) & 0x1)
+-#define CALIB_BUF1_ID_V1(x)		(((x) >> 9) & 0x1)
+-
+-/*
+- * Layout of the fuses providing the calibration data
+- * These macros could be used for MT7622.
+- */
+-#define CALIB_BUF0_ADC_OE_V2(x)		(((x) >> 22) & 0x3ff)
+-#define CALIB_BUF0_ADC_GE_V2(x)		(((x) >> 12) & 0x3ff)
+-#define CALIB_BUF0_DEGC_CALI_V2(x)	(((x) >> 6) & 0x3f)
+-#define CALIB_BUF0_O_SLOPE_V2(x)	(((x) >> 0) & 0x3f)
+-#define CALIB_BUF1_VTS_TS1_V2(x)	(((x) >> 23) & 0x1ff)
+-#define CALIB_BUF1_VTS_TS2_V2(x)	(((x) >> 14) & 0x1ff)
+-#define CALIB_BUF1_VTS_TSABB_V2(x)	(((x) >> 5) & 0x1ff)
+-#define CALIB_BUF1_VALID_V2(x)		(((x) >> 4) & 0x1)
+-#define CALIB_BUF1_O_SLOPE_SIGN_V2(x)	(((x) >> 3) & 0x1)
+-
+-/*
+- * Layout of the fuses providing the calibration data
+- * These macros can be used for MT7981 and MT7986.
+- */
+-#define CALIB_BUF0_ADC_GE_V3(x)		(((x) >> 0) & 0x3ff)
+-#define CALIB_BUF0_DEGC_CALI_V3(x)	(((x) >> 20) & 0x3f)
+-#define CALIB_BUF0_O_SLOPE_V3(x)	(((x) >> 26) & 0x3f)
+-#define CALIB_BUF1_VTS_TS1_V3(x)	(((x) >> 0) & 0x1ff)
+-#define CALIB_BUF1_VTS_TS2_V3(x)	(((x) >> 21) & 0x1ff)
+-#define CALIB_BUF1_VTS_TSABB_V3(x)	(((x) >> 9) & 0x1ff)
+-#define CALIB_BUF1_VALID_V3(x)		(((x) >> 18) & 0x1)
+-#define CALIB_BUF1_O_SLOPE_SIGN_V3(x)	(((x) >> 19) & 0x1)
+-#define CALIB_BUF1_ID_V3(x)		(((x) >> 20) & 0x1)
+-
+-enum {
+-	VTS1,
+-	VTS2,
+-	VTS3,
+-	VTS4,
+-	VTS5,
+-	VTSABB,
+-	MAX_NUM_VTS,
+-};
+-
+-enum mtk_thermal_version {
+-	MTK_THERMAL_V1 = 1,
+-	MTK_THERMAL_V2,
+-	MTK_THERMAL_V3,
+-};
+-
+-/* MT2701 thermal sensors */
+-#define MT2701_TS1	0
+-#define MT2701_TS2	1
+-#define MT2701_TSABB	2
+-
+-/* AUXADC channel 11 is used for the temperature sensors */
+-#define MT2701_TEMP_AUXADC_CHANNEL	11
+-
+-/* The total number of temperature sensors in the MT2701 */
+-#define MT2701_NUM_SENSORS	3
+-
+-/* The number of sensing points per bank */
+-#define MT2701_NUM_SENSORS_PER_ZONE	3
+-
+-/* The number of controller in the MT2701 */
+-#define MT2701_NUM_CONTROLLER		1
+-
+-/* The calibration coefficient of sensor  */
+-#define MT2701_CALIBRATION	165
+-
+-/* MT2712 thermal sensors */
+-#define MT2712_TS1	0
+-#define MT2712_TS2	1
+-#define MT2712_TS3	2
+-#define MT2712_TS4	3
+-
+-/* AUXADC channel 11 is used for the temperature sensors */
+-#define MT2712_TEMP_AUXADC_CHANNEL	11
+-
+-/* The total number of temperature sensors in the MT2712 */
+-#define MT2712_NUM_SENSORS	4
+-
+-/* The number of sensing points per bank */
+-#define MT2712_NUM_SENSORS_PER_ZONE	4
+-
+-/* The number of controller in the MT2712 */
+-#define MT2712_NUM_CONTROLLER		1
+-
+-/* The calibration coefficient of sensor  */
+-#define MT2712_CALIBRATION	165
+-
+-#define MT7622_TEMP_AUXADC_CHANNEL	11
+-#define MT7622_NUM_SENSORS		1
+-#define MT7622_NUM_ZONES		1
+-#define MT7622_NUM_SENSORS_PER_ZONE	1
+-#define MT7622_TS1	0
+-#define MT7622_NUM_CONTROLLER		1
+-
+-/* The maximum number of banks */
+-#define MAX_NUM_ZONES		8
+-
+-/* The calibration coefficient of sensor  */
+-#define MT7622_CALIBRATION	165
+-
+-/* MT8183 thermal sensors */
+-#define MT8183_TS1	0
+-#define MT8183_TS2	1
+-#define MT8183_TS3	2
+-#define MT8183_TS4	3
+-#define MT8183_TS5	4
+-#define MT8183_TSABB	5
+-
+-/* AUXADC channel  is used for the temperature sensors */
+-#define MT8183_TEMP_AUXADC_CHANNEL	11
+-
+-/* The total number of temperature sensors in the MT8183 */
+-#define MT8183_NUM_SENSORS	6
+-
+-/* The number of banks in the MT8183 */
+-#define MT8183_NUM_ZONES               1
+-
+-/* The number of sensing points per bank */
+-#define MT8183_NUM_SENSORS_PER_ZONE	 6
+-
+-/* The number of controller in the MT8183 */
+-#define MT8183_NUM_CONTROLLER		2
+-
+-/* The calibration coefficient of sensor  */
+-#define MT8183_CALIBRATION	153
+-
+-/* AUXADC channel 11 is used for the temperature sensors */
+-#define MT7986_TEMP_AUXADC_CHANNEL	11
+-
+-/* The total number of temperature sensors in the MT7986 */
+-#define MT7986_NUM_SENSORS		1
+-
+-/* The number of banks in the MT7986 */
+-#define MT7986_NUM_ZONES		1
+-
+-/* The number of sensing points per bank */
+-#define MT7986_NUM_SENSORS_PER_ZONE	1
+-
+-/* MT7986 thermal sensors */
+-#define MT7986_TS1			0
+-
+-/* The number of controller in the MT7986 */
+-#define MT7986_NUM_CONTROLLER		1
+-
+-/* The calibration coefficient of sensor  */
+-#define MT7986_CALIBRATION		165
+-
+-struct mtk_thermal;
+-
+-struct thermal_bank_cfg {
+-	unsigned int num_sensors;
+-	const int *sensors;
+-};
+-
+-struct mtk_thermal_bank {
+-	struct mtk_thermal *mt;
+-	int id;
+-};
+-
+-struct mtk_thermal_data {
+-	s32 num_banks;
+-	s32 num_sensors;
+-	s32 auxadc_channel;
+-	const int *vts_index;
+-	const int *sensor_mux_values;
+-	const int *msr;
+-	const int *adcpnp;
+-	const int cali_val;
+-	const int num_controller;
+-	const int *controller_offset;
+-	bool need_switch_bank;
+-	struct thermal_bank_cfg bank_data[MAX_NUM_ZONES];
+-	enum mtk_thermal_version version;
+-};
+-
+-struct mtk_thermal {
+-	struct device *dev;
+-	void __iomem *thermal_base;
+-
+-	struct clk *clk_peri_therm;
+-	struct clk *clk_auxadc;
+-	/* lock: for getting and putting banks */
+-	struct mutex lock;
+-
+-	/* Calibration values */
+-	s32 adc_ge;
+-	s32 adc_oe;
+-	s32 degc_cali;
+-	s32 o_slope;
+-	s32 o_slope_sign;
+-	s32 vts[MAX_NUM_VTS];
+-
+-	const struct mtk_thermal_data *conf;
+-	struct mtk_thermal_bank banks[MAX_NUM_ZONES];
+-
+-	int (*raw_to_mcelsius)(struct mtk_thermal *mt, int sensno, s32 raw);
+-};
+-
+-/* MT8183 thermal sensor data */
+-static const int mt8183_bank_data[MT8183_NUM_SENSORS] = {
+-	MT8183_TS1, MT8183_TS2, MT8183_TS3, MT8183_TS4, MT8183_TS5, MT8183_TSABB
+-};
+-
+-static const int mt8183_msr[MT8183_NUM_SENSORS_PER_ZONE] = {
+-	TEMP_MSR0_1, TEMP_MSR1_1, TEMP_MSR2_1, TEMP_MSR1, TEMP_MSR0, TEMP_MSR3_1
+-};
+-
+-static const int mt8183_adcpnp[MT8183_NUM_SENSORS_PER_ZONE] = {
+-	TEMP_ADCPNP0_1, TEMP_ADCPNP1_1, TEMP_ADCPNP2_1,
+-	TEMP_ADCPNP1, TEMP_ADCPNP0, TEMP_ADCPNP3_1
+-};
+-
+-static const int mt8183_mux_values[MT8183_NUM_SENSORS] = { 0, 1, 2, 3, 4, 0 };
+-static const int mt8183_tc_offset[MT8183_NUM_CONTROLLER] = {0x0, 0x100};
+-
+-static const int mt8183_vts_index[MT8183_NUM_SENSORS] = {
+-	VTS1, VTS2, VTS3, VTS4, VTS5, VTSABB
+-};
+-
+-/* MT8173 thermal sensor data */
+-static const int mt8173_bank_data[MT8173_NUM_ZONES][3] = {
+-	{ MT8173_TS2, MT8173_TS3 },
+-	{ MT8173_TS2, MT8173_TS4 },
+-	{ MT8173_TS1, MT8173_TS2, MT8173_TSABB },
+-	{ MT8173_TS2 },
+-};
+-
+-static const int mt8173_msr[MT8173_NUM_SENSORS_PER_ZONE] = {
+-	TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3
+-};
+-
+-static const int mt8173_adcpnp[MT8173_NUM_SENSORS_PER_ZONE] = {
+-	TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3
+-};
+-
+-static const int mt8173_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 };
+-static const int mt8173_tc_offset[MT8173_NUM_CONTROLLER] = { 0x0, };
+-
+-static const int mt8173_vts_index[MT8173_NUM_SENSORS] = {
+-	VTS1, VTS2, VTS3, VTS4, VTSABB
+-};
+-
+-/* MT2701 thermal sensor data */
+-static const int mt2701_bank_data[MT2701_NUM_SENSORS] = {
+-	MT2701_TS1, MT2701_TS2, MT2701_TSABB
+-};
+-
+-static const int mt2701_msr[MT2701_NUM_SENSORS_PER_ZONE] = {
+-	TEMP_MSR0, TEMP_MSR1, TEMP_MSR2
+-};
+-
+-static const int mt2701_adcpnp[MT2701_NUM_SENSORS_PER_ZONE] = {
+-	TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2
+-};
+-
+-static const int mt2701_mux_values[MT2701_NUM_SENSORS] = { 0, 1, 16 };
+-static const int mt2701_tc_offset[MT2701_NUM_CONTROLLER] = { 0x0, };
+-
+-static const int mt2701_vts_index[MT2701_NUM_SENSORS] = {
+-	VTS1, VTS2, VTS3
+-};
+-
+-/* MT2712 thermal sensor data */
+-static const int mt2712_bank_data[MT2712_NUM_SENSORS] = {
+-	MT2712_TS1, MT2712_TS2, MT2712_TS3, MT2712_TS4
+-};
+-
+-static const int mt2712_msr[MT2712_NUM_SENSORS_PER_ZONE] = {
+-	TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3
+-};
+-
+-static const int mt2712_adcpnp[MT2712_NUM_SENSORS_PER_ZONE] = {
+-	TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3
+-};
+-
+-static const int mt2712_mux_values[MT2712_NUM_SENSORS] = { 0, 1, 2, 3 };
+-static const int mt2712_tc_offset[MT2712_NUM_CONTROLLER] = { 0x0, };
+-
+-static const int mt2712_vts_index[MT2712_NUM_SENSORS] = {
+-	VTS1, VTS2, VTS3, VTS4
+-};
+-
+-/* MT7622 thermal sensor data */
+-static const int mt7622_bank_data[MT7622_NUM_SENSORS] = { MT7622_TS1, };
+-static const int mt7622_msr[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, };
+-static const int mt7622_adcpnp[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, };
+-static const int mt7622_mux_values[MT7622_NUM_SENSORS] = { 0, };
+-static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 };
+-static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, };
+-
+-/* MT7986 thermal sensor data */
+-static const int mt7986_bank_data[MT7986_NUM_SENSORS] = { MT7986_TS1, };
+-static const int mt7986_msr[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, };
+-static const int mt7986_adcpnp[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, };
+-static const int mt7986_mux_values[MT7986_NUM_SENSORS] = { 0, };
+-static const int mt7986_vts_index[MT7986_NUM_SENSORS] = { VTS1 };
+-static const int mt7986_tc_offset[MT7986_NUM_CONTROLLER] = { 0x0, };
+-
+-/*
+- * The MT8173 thermal controller has four banks. Each bank can read up to
+- * four temperature sensors simultaneously. The MT8173 has a total of 5
+- * temperature sensors. We use each bank to measure a certain area of the
+- * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple
+- * areas, hence is used in different banks.
+- *
+- * The thermal core only gets the maximum temperature of all banks, so
+- * the bank concept wouldn't be necessary here. However, the SVS (Smart
+- * Voltage Scaling) unit makes its decisions based on the same bank
+- * data, and this indeed needs the temperatures of the individual banks
+- * for making better decisions.
+- */
+-static const struct mtk_thermal_data mt8173_thermal_data = {
+-	.auxadc_channel = MT8173_TEMP_AUXADC_CHANNEL,
+-	.num_banks = MT8173_NUM_ZONES,
+-	.num_sensors = MT8173_NUM_SENSORS,
+-	.vts_index = mt8173_vts_index,
+-	.cali_val = MT8173_CALIBRATION,
+-	.num_controller = MT8173_NUM_CONTROLLER,
+-	.controller_offset = mt8173_tc_offset,
+-	.need_switch_bank = true,
+-	.bank_data = {
+-		{
+-			.num_sensors = 2,
+-			.sensors = mt8173_bank_data[0],
+-		}, {
+-			.num_sensors = 2,
+-			.sensors = mt8173_bank_data[1],
+-		}, {
+-			.num_sensors = 3,
+-			.sensors = mt8173_bank_data[2],
+-		}, {
+-			.num_sensors = 1,
+-			.sensors = mt8173_bank_data[3],
+-		},
+-	},
+-	.msr = mt8173_msr,
+-	.adcpnp = mt8173_adcpnp,
+-	.sensor_mux_values = mt8173_mux_values,
+-	.version = MTK_THERMAL_V1,
+-};
+-
+-/*
+- * The MT2701 thermal controller has one bank, which can read up to
+- * three temperature sensors simultaneously. The MT2701 has a total of 3
+- * temperature sensors.
+- *
+- * The thermal core only gets the maximum temperature of this one bank,
+- * so the bank concept wouldn't be necessary here. However, the SVS (Smart
+- * Voltage Scaling) unit makes its decisions based on the same bank
+- * data.
+- */
+-static const struct mtk_thermal_data mt2701_thermal_data = {
+-	.auxadc_channel = MT2701_TEMP_AUXADC_CHANNEL,
+-	.num_banks = 1,
+-	.num_sensors = MT2701_NUM_SENSORS,
+-	.vts_index = mt2701_vts_index,
+-	.cali_val = MT2701_CALIBRATION,
+-	.num_controller = MT2701_NUM_CONTROLLER,
+-	.controller_offset = mt2701_tc_offset,
+-	.need_switch_bank = true,
+-	.bank_data = {
+-		{
+-			.num_sensors = 3,
+-			.sensors = mt2701_bank_data,
+-		},
+-	},
+-	.msr = mt2701_msr,
+-	.adcpnp = mt2701_adcpnp,
+-	.sensor_mux_values = mt2701_mux_values,
+-	.version = MTK_THERMAL_V1,
+-};
+-
+-/*
+- * The MT2712 thermal controller has one bank, which can read up to
+- * four temperature sensors simultaneously. The MT2712 has a total of 4
+- * temperature sensors.
+- *
+- * The thermal core only gets the maximum temperature of this one bank,
+- * so the bank concept wouldn't be necessary here. However, the SVS (Smart
+- * Voltage Scaling) unit makes its decisions based on the same bank
+- * data.
+- */
+-static const struct mtk_thermal_data mt2712_thermal_data = {
+-	.auxadc_channel = MT2712_TEMP_AUXADC_CHANNEL,
+-	.num_banks = 1,
+-	.num_sensors = MT2712_NUM_SENSORS,
+-	.vts_index = mt2712_vts_index,
+-	.cali_val = MT2712_CALIBRATION,
+-	.num_controller = MT2712_NUM_CONTROLLER,
+-	.controller_offset = mt2712_tc_offset,
+-	.need_switch_bank = true,
+-	.bank_data = {
+-		{
+-			.num_sensors = 4,
+-			.sensors = mt2712_bank_data,
+-		},
+-	},
+-	.msr = mt2712_msr,
+-	.adcpnp = mt2712_adcpnp,
+-	.sensor_mux_values = mt2712_mux_values,
+-	.version = MTK_THERMAL_V1,
+-};
+-
+-/*
+- * MT7622 have only one sensing point which uses AUXADC Channel 11 for raw data
+- * access.
+- */
+-static const struct mtk_thermal_data mt7622_thermal_data = {
+-	.auxadc_channel = MT7622_TEMP_AUXADC_CHANNEL,
+-	.num_banks = MT7622_NUM_ZONES,
+-	.num_sensors = MT7622_NUM_SENSORS,
+-	.vts_index = mt7622_vts_index,
+-	.cali_val = MT7622_CALIBRATION,
+-	.num_controller = MT7622_NUM_CONTROLLER,
+-	.controller_offset = mt7622_tc_offset,
+-	.need_switch_bank = true,
+-	.bank_data = {
+-		{
+-			.num_sensors = 1,
+-			.sensors = mt7622_bank_data,
+-		},
+-	},
+-	.msr = mt7622_msr,
+-	.adcpnp = mt7622_adcpnp,
+-	.sensor_mux_values = mt7622_mux_values,
+-	.version = MTK_THERMAL_V2,
+-};
+-
+-/*
+- * The MT8183 thermal controller has one bank for the current SW framework.
+- * The MT8183 has a total of 6 temperature sensors.
+- * There are two thermal controller to control the six sensor.
+- * The first one bind 2 sensor, and the other bind 4 sensors.
+- * The thermal core only gets the maximum temperature of all sensor, so
+- * the bank concept wouldn't be necessary here. However, the SVS (Smart
+- * Voltage Scaling) unit makes its decisions based on the same bank
+- * data, and this indeed needs the temperatures of the individual banks
+- * for making better decisions.
+- */
+-static const struct mtk_thermal_data mt8183_thermal_data = {
+-	.auxadc_channel = MT8183_TEMP_AUXADC_CHANNEL,
+-	.num_banks = MT8183_NUM_ZONES,
+-	.num_sensors = MT8183_NUM_SENSORS,
+-	.vts_index = mt8183_vts_index,
+-	.cali_val = MT8183_CALIBRATION,
+-	.num_controller = MT8183_NUM_CONTROLLER,
+-	.controller_offset = mt8183_tc_offset,
+-	.need_switch_bank = false,
+-	.bank_data = {
+-		{
+-			.num_sensors = 6,
+-			.sensors = mt8183_bank_data,
+-		},
+-	},
+-
+-	.msr = mt8183_msr,
+-	.adcpnp = mt8183_adcpnp,
+-	.sensor_mux_values = mt8183_mux_values,
+-	.version = MTK_THERMAL_V1,
+-};
+-
+-/*
+- * MT7986 uses AUXADC Channel 11 for raw data access.
+- */
+-static const struct mtk_thermal_data mt7986_thermal_data = {
+-	.auxadc_channel = MT7986_TEMP_AUXADC_CHANNEL,
+-	.num_banks = MT7986_NUM_ZONES,
+-	.num_sensors = MT7986_NUM_SENSORS,
+-	.vts_index = mt7986_vts_index,
+-	.cali_val = MT7986_CALIBRATION,
+-	.num_controller = MT7986_NUM_CONTROLLER,
+-	.controller_offset = mt7986_tc_offset,
+-	.need_switch_bank = true,
+-	.bank_data = {
+-		{
+-			.num_sensors = 1,
+-			.sensors = mt7986_bank_data,
+-		},
+-	},
+-	.msr = mt7986_msr,
+-	.adcpnp = mt7986_adcpnp,
+-	.sensor_mux_values = mt7986_mux_values,
+-	.version = MTK_THERMAL_V3,
+-};
+-
+-/**
+- * raw_to_mcelsius_v1 - convert a raw ADC value to mcelsius
+- * @mt:	The thermal controller
+- * @sensno:	sensor number
+- * @raw:	raw ADC value
+- *
+- * This converts the raw ADC value to mcelsius using the SoC specific
+- * calibration constants
+- */
+-static int raw_to_mcelsius_v1(struct mtk_thermal *mt, int sensno, s32 raw)
+-{
+-	s32 tmp;
+-
+-	raw &= 0xfff;
+-
+-	tmp = 203450520 << 3;
+-	tmp /= mt->conf->cali_val + mt->o_slope;
+-	tmp /= 10000 + mt->adc_ge;
+-	tmp *= raw - mt->vts[sensno] - 3350;
+-	tmp >>= 3;
+-
+-	return mt->degc_cali * 500 - tmp;
+-}
+-
+-static int raw_to_mcelsius_v2(struct mtk_thermal *mt, int sensno, s32 raw)
+-{
+-	s32 format_1;
+-	s32 format_2;
+-	s32 g_oe;
+-	s32 g_gain;
+-	s32 g_x_roomt;
+-	s32 tmp;
+-
+-	if (raw == 0)
+-		return 0;
+-
+-	raw &= 0xfff;
+-	g_gain = 10000 + (((mt->adc_ge - 512) * 10000) >> 12);
+-	g_oe = mt->adc_oe - 512;
+-	format_1 = mt->vts[VTS2] + 3105 - g_oe;
+-	format_2 = (mt->degc_cali * 10) >> 1;
+-	g_x_roomt = (((format_1 * 10000) >> 12) * 10000) / g_gain;
+-
+-	tmp = (((((raw - g_oe) * 10000) >> 12) * 10000) / g_gain) - g_x_roomt;
+-	tmp = tmp * 10 * 100 / 11;
+-
+-	if (mt->o_slope_sign == 0)
+-		tmp = tmp / (165 - mt->o_slope);
+-	else
+-		tmp = tmp / (165 + mt->o_slope);
+-
+-	return (format_2 - tmp) * 100;
+-}
+-
+-static int raw_to_mcelsius_v3(struct mtk_thermal *mt, int sensno, s32 raw)
+-{
+-	s32 tmp;
+-
+-	if (raw == 0)
+-		return 0;
+-
+-	raw &= 0xfff;
+-	tmp = 100000 * 15 / 16 * 10000;
+-	tmp /= 4096 - 512 + mt->adc_ge;
+-	tmp /= 1490;
+-	tmp *= raw - mt->vts[sensno] - 2900;
+-
+-	return mt->degc_cali * 500 - tmp;
+-}
+-
+-/**
+- * mtk_thermal_get_bank - get bank
+- * @bank:	The bank
+- *
+- * The bank registers are banked, we have to select a bank in the
+- * PTPCORESEL register to access it.
+- */
+-static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank)
+-{
+-	struct mtk_thermal *mt = bank->mt;
+-	u32 val;
+-
+-	if (mt->conf->need_switch_bank) {
+-		mutex_lock(&mt->lock);
+-
+-		val = readl(mt->thermal_base + PTPCORESEL);
+-		val &= ~0xf;
+-		val |= bank->id;
+-		writel(val, mt->thermal_base + PTPCORESEL);
+-	}
+-}
+-
+-/**
+- * mtk_thermal_put_bank - release bank
+- * @bank:	The bank
+- *
+- * release a bank previously taken with mtk_thermal_get_bank,
+- */
+-static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank)
+-{
+-	struct mtk_thermal *mt = bank->mt;
+-
+-	if (mt->conf->need_switch_bank)
+-		mutex_unlock(&mt->lock);
+-}
+-
+-/**
+- * mtk_thermal_bank_temperature - get the temperature of a bank
+- * @bank:	The bank
+- *
+- * The temperature of a bank is considered the maximum temperature of
+- * the sensors associated to the bank.
+- */
+-static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank)
+-{
+-	struct mtk_thermal *mt = bank->mt;
+-	const struct mtk_thermal_data *conf = mt->conf;
+-	int i, temp = INT_MIN, max = INT_MIN;
+-	u32 raw;
+-
+-	for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) {
+-		raw = readl(mt->thermal_base + conf->msr[i]);
+-
+-		temp = mt->raw_to_mcelsius(
+-			mt, conf->bank_data[bank->id].sensors[i], raw);
+-
+-
+-		/*
+-		 * The first read of a sensor often contains very high bogus
+-		 * temperature value. Filter these out so that the system does
+-		 * not immediately shut down.
+-		 */
+-		if (temp > 200000)
+-			temp = 0;
+-
+-		if (temp > max)
+-			max = temp;
+-	}
+-
+-	return max;
+-}
+-
+-static int mtk_read_temp(struct thermal_zone_device *tz, int *temperature)
+-{
+-	struct mtk_thermal *mt = tz->devdata;
+-	int i;
+-	int tempmax = INT_MIN;
+-
+-	for (i = 0; i < mt->conf->num_banks; i++) {
+-		struct mtk_thermal_bank *bank = &mt->banks[i];
+-
+-		mtk_thermal_get_bank(bank);
+-
+-		tempmax = max(tempmax, mtk_thermal_bank_temperature(bank));
+-
+-		mtk_thermal_put_bank(bank);
+-	}
+-
+-	*temperature = tempmax;
+-
+-	return 0;
+-}
+-
+-static const struct thermal_zone_device_ops mtk_thermal_ops = {
+-	.get_temp = mtk_read_temp,
+-};
+-
+-static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num,
+-				  u32 apmixed_phys_base, u32 auxadc_phys_base,
+-				  int ctrl_id)
+-{
+-	struct mtk_thermal_bank *bank = &mt->banks[num];
+-	const struct mtk_thermal_data *conf = mt->conf;
+-	int i;
+-
+-	int offset = mt->conf->controller_offset[ctrl_id];
+-	void __iomem *controller_base = mt->thermal_base + offset;
+-
+-	bank->id = num;
+-	bank->mt = mt;
+-
+-	mtk_thermal_get_bank(bank);
+-
+-	/* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */
+-	writel(TEMP_MONCTL1_PERIOD_UNIT(12), controller_base + TEMP_MONCTL1);
+-
+-	/*
+-	 * filt interval is 1 * 46.540us = 46.54us,
+-	 * sen interval is 429 * 46.540us = 19.96ms
+-	 */
+-	writel(TEMP_MONCTL2_FILTER_INTERVAL(1) |
+-			TEMP_MONCTL2_SENSOR_INTERVAL(429),
+-			controller_base + TEMP_MONCTL2);
+-
+-	/* poll is set to 10u */
+-	writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768),
+-	       controller_base + TEMP_AHBPOLL);
+-
+-	/* temperature sampling control, 1 sample */
+-	writel(0x0, controller_base + TEMP_MSRCTL0);
+-
+-	/* exceed this polling time, IRQ would be inserted */
+-	writel(0xffffffff, controller_base + TEMP_AHBTO);
+-
+-	/* number of interrupts per event, 1 is enough */
+-	writel(0x0, controller_base + TEMP_MONIDET0);
+-	writel(0x0, controller_base + TEMP_MONIDET1);
+-
+-	/*
+-	 * The MT8173 thermal controller does not have its own ADC. Instead it
+-	 * uses AHB bus accesses to control the AUXADC. To do this the thermal
+-	 * controller has to be programmed with the physical addresses of the
+-	 * AUXADC registers and with the various bit positions in the AUXADC.
+-	 * Also the thermal controller controls a mux in the APMIXEDSYS register
+-	 * space.
+-	 */
+-
+-	/*
+-	 * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0)
+-	 * automatically by hw
+-	 */
+-	writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCMUX);
+-
+-	/* AHB address for auxadc mux selection */
+-	writel(auxadc_phys_base + AUXADC_CON1_CLR_V,
+-	       controller_base + TEMP_ADCMUXADDR);
+-
+-	if (mt->conf->version == MTK_THERMAL_V1) {
+-		/* AHB address for pnp sensor mux selection */
+-		writel(apmixed_phys_base + APMIXED_SYS_TS_CON1,
+-		       controller_base + TEMP_PNPMUXADDR);
+-	}
+-
+-	/* AHB value for auxadc enable */
+-	writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCEN);
+-
+-	/* AHB address for auxadc enable (channel 0 immediate mode selected) */
+-	writel(auxadc_phys_base + AUXADC_CON1_SET_V,
+-	       controller_base + TEMP_ADCENADDR);
+-
+-	/* AHB address for auxadc valid bit */
+-	writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
+-	       controller_base + TEMP_ADCVALIDADDR);
+-
+-	/* AHB address for auxadc voltage output */
+-	writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
+-	       controller_base + TEMP_ADCVOLTADDR);
+-
+-	/* read valid & voltage are at the same register */
+-	writel(0x0, controller_base + TEMP_RDCTRL);
+-
+-	/* indicate where the valid bit is */
+-	writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12),
+-	       controller_base + TEMP_ADCVALIDMASK);
+-
+-	/* no shift */
+-	writel(0x0, controller_base + TEMP_ADCVOLTAGESHIFT);
+-
+-	/* enable auxadc mux write transaction */
+-	writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
+-		controller_base + TEMP_ADCWRITECTRL);
+-
+-	for (i = 0; i < conf->bank_data[num].num_sensors; i++)
+-		writel(conf->sensor_mux_values[conf->bank_data[num].sensors[i]],
+-		       mt->thermal_base + conf->adcpnp[i]);
+-
+-	writel((1 << conf->bank_data[num].num_sensors) - 1,
+-	       controller_base + TEMP_MONCTL0);
+-
+-	writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE |
+-	       TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
+-	       controller_base + TEMP_ADCWRITECTRL);
+-
+-	mtk_thermal_put_bank(bank);
+-}
+-
+-static u64 of_get_phys_base(struct device_node *np)
+-{
+-	u64 size64;
+-	const __be32 *regaddr_p;
+-
+-	regaddr_p = of_get_address(np, 0, &size64, NULL);
+-	if (!regaddr_p)
+-		return OF_BAD_ADDR;
+-
+-	return of_translate_address(np, regaddr_p);
+-}
+-
+-static int mtk_thermal_extract_efuse_v1(struct mtk_thermal *mt, u32 *buf)
+-{
+-	int i;
+-
+-	if (!(buf[0] & CALIB_BUF0_VALID_V1))
+-		return -EINVAL;
+-
+-	mt->adc_ge = CALIB_BUF1_ADC_GE_V1(buf[1]);
+-
+-	for (i = 0; i < mt->conf->num_sensors; i++) {
+-		switch (mt->conf->vts_index[i]) {
+-		case VTS1:
+-			mt->vts[VTS1] = CALIB_BUF0_VTS_TS1_V1(buf[0]);
+-			break;
+-		case VTS2:
+-			mt->vts[VTS2] = CALIB_BUF0_VTS_TS2_V1(buf[0]);
+-			break;
+-		case VTS3:
+-			mt->vts[VTS3] = CALIB_BUF1_VTS_TS3_V1(buf[1]);
+-			break;
+-		case VTS4:
+-			mt->vts[VTS4] = CALIB_BUF2_VTS_TS4_V1(buf[2]);
+-			break;
+-		case VTS5:
+-			mt->vts[VTS5] = CALIB_BUF2_VTS_TS5_V1(buf[2]);
+-			break;
+-		case VTSABB:
+-			mt->vts[VTSABB] =
+-				CALIB_BUF2_VTS_TSABB_V1(buf[2]);
+-			break;
+-		default:
+-			break;
+-		}
+-	}
+-
+-	mt->degc_cali = CALIB_BUF0_DEGC_CALI_V1(buf[0]);
+-	if (CALIB_BUF1_ID_V1(buf[1]) &
+-	    CALIB_BUF0_O_SLOPE_SIGN_V1(buf[0]))
+-		mt->o_slope = -CALIB_BUF0_O_SLOPE_V1(buf[0]);
+-	else
+-		mt->o_slope = CALIB_BUF0_O_SLOPE_V1(buf[0]);
+-
+-	return 0;
+-}
+-
+-static int mtk_thermal_extract_efuse_v2(struct mtk_thermal *mt, u32 *buf)
+-{
+-	if (!CALIB_BUF1_VALID_V2(buf[1]))
+-		return -EINVAL;
+-
+-	mt->adc_oe = CALIB_BUF0_ADC_OE_V2(buf[0]);
+-	mt->adc_ge = CALIB_BUF0_ADC_GE_V2(buf[0]);
+-	mt->degc_cali = CALIB_BUF0_DEGC_CALI_V2(buf[0]);
+-	mt->o_slope = CALIB_BUF0_O_SLOPE_V2(buf[0]);
+-	mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V2(buf[1]);
+-	mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V2(buf[1]);
+-	mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V2(buf[1]);
+-	mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V2(buf[1]);
+-
+-	return 0;
+-}
+-
+-static int mtk_thermal_extract_efuse_v3(struct mtk_thermal *mt, u32 *buf)
+-{
+-	if (!CALIB_BUF1_VALID_V3(buf[1]))
+-		return -EINVAL;
+-
+-	mt->adc_ge = CALIB_BUF0_ADC_GE_V3(buf[0]);
+-	mt->degc_cali = CALIB_BUF0_DEGC_CALI_V3(buf[0]);
+-	mt->o_slope = CALIB_BUF0_O_SLOPE_V3(buf[0]);
+-	mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V3(buf[1]);
+-	mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V3(buf[1]);
+-	mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V3(buf[1]);
+-	mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V3(buf[1]);
+-
+-	if (CALIB_BUF1_ID_V3(buf[1]) == 0)
+-		mt->o_slope = 0;
+-
+-	return 0;
+-}
+-
+-static int mtk_thermal_get_calibration_data(struct device *dev,
+-					    struct mtk_thermal *mt)
+-{
+-	struct nvmem_cell *cell;
+-	u32 *buf;
+-	size_t len;
+-	int i, ret = 0;
+-
+-	/* Start with default values */
+-	mt->adc_ge = 512;
+-	mt->adc_oe = 512;
+-	for (i = 0; i < mt->conf->num_sensors; i++)
+-		mt->vts[i] = 260;
+-	mt->degc_cali = 40;
+-	mt->o_slope = 0;
+-
+-	cell = nvmem_cell_get(dev, "calibration-data");
+-	if (IS_ERR(cell)) {
+-		if (PTR_ERR(cell) == -EPROBE_DEFER)
+-			return PTR_ERR(cell);
+-		return 0;
+-	}
+-
+-	buf = (u32 *)nvmem_cell_read(cell, &len);
+-
+-	nvmem_cell_put(cell);
+-
+-	if (IS_ERR(buf))
+-		return PTR_ERR(buf);
+-
+-	if (len < 3 * sizeof(u32)) {
+-		dev_warn(dev, "invalid calibration data\n");
+-		ret = -EINVAL;
+-		goto out;
+-	}
+-
+-	switch (mt->conf->version) {
+-	case MTK_THERMAL_V1:
+-		ret = mtk_thermal_extract_efuse_v1(mt, buf);
+-		break;
+-	case MTK_THERMAL_V2:
+-		ret = mtk_thermal_extract_efuse_v2(mt, buf);
+-		break;
+-	case MTK_THERMAL_V3:
+-		ret = mtk_thermal_extract_efuse_v3(mt, buf);
+-		break;
+-	default:
+-		ret = -EINVAL;
+-		break;
+-	}
+-
+-	if (ret) {
+-		dev_info(dev, "Device not calibrated, using default calibration values\n");
+-		ret = 0;
+-	}
+-
+-out:
+-	kfree(buf);
+-
+-	return ret;
+-}
+-
+-static const struct of_device_id mtk_thermal_of_match[] = {
+-	{
+-		.compatible = "mediatek,mt8173-thermal",
+-		.data = (void *)&mt8173_thermal_data,
+-	},
+-	{
+-		.compatible = "mediatek,mt2701-thermal",
+-		.data = (void *)&mt2701_thermal_data,
+-	},
+-	{
+-		.compatible = "mediatek,mt2712-thermal",
+-		.data = (void *)&mt2712_thermal_data,
+-	},
+-	{
+-		.compatible = "mediatek,mt7622-thermal",
+-		.data = (void *)&mt7622_thermal_data,
+-	},
+-	{
+-		.compatible = "mediatek,mt7986-thermal",
+-		.data = (void *)&mt7986_thermal_data,
+-	},
+-	{
+-		.compatible = "mediatek,mt8183-thermal",
+-		.data = (void *)&mt8183_thermal_data,
+-	}, {
+-	},
+-};
+-MODULE_DEVICE_TABLE(of, mtk_thermal_of_match);
+-
+-static void mtk_thermal_turn_on_buffer(void __iomem *apmixed_base)
+-{
+-	int tmp;
+-
+-	tmp = readl(apmixed_base + APMIXED_SYS_TS_CON1);
+-	tmp &= ~(0x37);
+-	tmp |= 0x1;
+-	writel(tmp, apmixed_base + APMIXED_SYS_TS_CON1);
+-	udelay(200);
+-}
+-
+-static void mtk_thermal_release_periodic_ts(struct mtk_thermal *mt,
+-					    void __iomem *auxadc_base)
+-{
+-	int tmp;
+-
+-	writel(0x800, auxadc_base + AUXADC_CON1_SET_V);
+-	writel(0x1, mt->thermal_base + TEMP_MONCTL0);
+-	tmp = readl(mt->thermal_base + TEMP_MSRCTL1);
+-	writel((tmp & (~0x10e)), mt->thermal_base + TEMP_MSRCTL1);
+-}
+-
+-static int mtk_thermal_probe(struct platform_device *pdev)
+-{
+-	int ret, i, ctrl_id;
+-	struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node;
+-	struct mtk_thermal *mt;
+-	u64 auxadc_phys_base, apmixed_phys_base;
+-	struct thermal_zone_device *tzdev;
+-	void __iomem *apmixed_base, *auxadc_base;
+-
+-	mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL);
+-	if (!mt)
+-		return -ENOMEM;
+-
+-	mt->conf = of_device_get_match_data(&pdev->dev);
+-
+-	mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm");
+-	if (IS_ERR(mt->clk_peri_therm))
+-		return PTR_ERR(mt->clk_peri_therm);
+-
+-	mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc");
+-	if (IS_ERR(mt->clk_auxadc))
+-		return PTR_ERR(mt->clk_auxadc);
+-
+-	mt->thermal_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
+-	if (IS_ERR(mt->thermal_base))
+-		return PTR_ERR(mt->thermal_base);
+-
+-	ret = mtk_thermal_get_calibration_data(&pdev->dev, mt);
+-	if (ret)
+-		return ret;
+-
+-	mutex_init(&mt->lock);
+-
+-	mt->dev = &pdev->dev;
+-
+-	auxadc = of_parse_phandle(np, "mediatek,auxadc", 0);
+-	if (!auxadc) {
+-		dev_err(&pdev->dev, "missing auxadc node\n");
+-		return -ENODEV;
+-	}
+-
+-	auxadc_base = of_iomap(auxadc, 0);
+-	auxadc_phys_base = of_get_phys_base(auxadc);
+-
+-	of_node_put(auxadc);
+-
+-	if (auxadc_phys_base == OF_BAD_ADDR) {
+-		dev_err(&pdev->dev, "Can't get auxadc phys address\n");
+-		return -EINVAL;
+-	}
+-
+-	apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0);
+-	if (!apmixedsys) {
+-		dev_err(&pdev->dev, "missing apmixedsys node\n");
+-		return -ENODEV;
+-	}
+-
+-	apmixed_base = of_iomap(apmixedsys, 0);
+-	apmixed_phys_base = of_get_phys_base(apmixedsys);
+-
+-	of_node_put(apmixedsys);
+-
+-	if (apmixed_phys_base == OF_BAD_ADDR) {
+-		dev_err(&pdev->dev, "Can't get auxadc phys address\n");
+-		return -EINVAL;
+-	}
+-
+-	ret = device_reset_optional(&pdev->dev);
+-	if (ret)
+-		return ret;
+-
+-	ret = clk_prepare_enable(mt->clk_auxadc);
+-	if (ret) {
+-		dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret);
+-		return ret;
+-	}
+-
+-	ret = clk_prepare_enable(mt->clk_peri_therm);
+-	if (ret) {
+-		dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret);
+-		goto err_disable_clk_auxadc;
+-	}
+-
+-	if (mt->conf->version != MTK_THERMAL_V1) {
+-		mtk_thermal_turn_on_buffer(apmixed_base);
+-		mtk_thermal_release_periodic_ts(mt, auxadc_base);
+-	}
+-
+-	if (mt->conf->version == MTK_THERMAL_V1)
+-		mt->raw_to_mcelsius = raw_to_mcelsius_v1;
+-	else if (mt->conf->version == MTK_THERMAL_V2)
+-		mt->raw_to_mcelsius = raw_to_mcelsius_v2;
+-	else
+-		mt->raw_to_mcelsius = raw_to_mcelsius_v3;
+-
+-	for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++)
+-		for (i = 0; i < mt->conf->num_banks; i++)
+-			mtk_thermal_init_bank(mt, i, apmixed_phys_base,
+-					      auxadc_phys_base, ctrl_id);
+-
+-	platform_set_drvdata(pdev, mt);
+-
+-	tzdev = devm_thermal_of_zone_register(&pdev->dev, 0, mt,
+-					      &mtk_thermal_ops);
+-	if (IS_ERR(tzdev)) {
+-		ret = PTR_ERR(tzdev);
+-		goto err_disable_clk_peri_therm;
+-	}
+-
+-	ret = devm_thermal_add_hwmon_sysfs(tzdev);
+-	if (ret)
+-		dev_warn(&pdev->dev, "error in thermal_add_hwmon_sysfs");
+-
+-	return 0;
+-
+-err_disable_clk_peri_therm:
+-	clk_disable_unprepare(mt->clk_peri_therm);
+-err_disable_clk_auxadc:
+-	clk_disable_unprepare(mt->clk_auxadc);
+-
+-	return ret;
+-}
+-
+-static int mtk_thermal_remove(struct platform_device *pdev)
+-{
+-	struct mtk_thermal *mt = platform_get_drvdata(pdev);
+-
+-	clk_disable_unprepare(mt->clk_peri_therm);
+-	clk_disable_unprepare(mt->clk_auxadc);
+-
+-	return 0;
+-}
+-
+-static struct platform_driver mtk_thermal_driver = {
+-	.probe = mtk_thermal_probe,
+-	.remove = mtk_thermal_remove,
+-	.driver = {
+-		.name = "mtk-thermal",
+-		.of_match_table = mtk_thermal_of_match,
+-	},
+-};
+-
+-module_platform_driver(mtk_thermal_driver);
+-
+-MODULE_AUTHOR("Michael Kao <michael.kao@mediatek.com>");
+-MODULE_AUTHOR("Louis Yu <louis.yu@mediatek.com>");
+-MODULE_AUTHOR("Dawei Chien <dawei.chien@mediatek.com>");
+-MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
+-MODULE_AUTHOR("Hanyi Wu <hanyi.wu@mediatek.com>");
+-MODULE_DESCRIPTION("Mediatek thermal driver");
+-MODULE_LICENSE("GPL v2");
+--- /dev/null
++++ b/drivers/thermal/mediatek/auxadc_thermal.c
+@@ -0,0 +1,1254 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * Copyright (c) 2015 MediaTek Inc.
++ * Author: Hanyi Wu <hanyi.wu@mediatek.com>
++ *         Sascha Hauer <s.hauer@pengutronix.de>
++ *         Dawei Chien <dawei.chien@mediatek.com>
++ *         Louis Yu <louis.yu@mediatek.com>
++ */
++
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/interrupt.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/nvmem-consumer.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++#include <linux/io.h>
++#include <linux/thermal.h>
++#include <linux/reset.h>
++#include <linux/types.h>
++
++#include "../thermal_hwmon.h"
++
++/* AUXADC Registers */
++#define AUXADC_CON1_SET_V	0x008
++#define AUXADC_CON1_CLR_V	0x00c
++#define AUXADC_CON2_V		0x010
++#define AUXADC_DATA(channel)	(0x14 + (channel) * 4)
++
++#define APMIXED_SYS_TS_CON1	0x604
++
++/* Thermal Controller Registers */
++#define TEMP_MONCTL0		0x000
++#define TEMP_MONCTL1		0x004
++#define TEMP_MONCTL2		0x008
++#define TEMP_MONIDET0		0x014
++#define TEMP_MONIDET1		0x018
++#define TEMP_MSRCTL0		0x038
++#define TEMP_MSRCTL1		0x03c
++#define TEMP_AHBPOLL		0x040
++#define TEMP_AHBTO		0x044
++#define TEMP_ADCPNP0		0x048
++#define TEMP_ADCPNP1		0x04c
++#define TEMP_ADCPNP2		0x050
++#define TEMP_ADCPNP3		0x0b4
++
++#define TEMP_ADCMUX		0x054
++#define TEMP_ADCEN		0x060
++#define TEMP_PNPMUXADDR		0x064
++#define TEMP_ADCMUXADDR		0x068
++#define TEMP_ADCENADDR		0x074
++#define TEMP_ADCVALIDADDR	0x078
++#define TEMP_ADCVOLTADDR	0x07c
++#define TEMP_RDCTRL		0x080
++#define TEMP_ADCVALIDMASK	0x084
++#define TEMP_ADCVOLTAGESHIFT	0x088
++#define TEMP_ADCWRITECTRL	0x08c
++#define TEMP_MSR0		0x090
++#define TEMP_MSR1		0x094
++#define TEMP_MSR2		0x098
++#define TEMP_MSR3		0x0B8
++
++#define TEMP_SPARE0		0x0f0
++
++#define TEMP_ADCPNP0_1          0x148
++#define TEMP_ADCPNP1_1          0x14c
++#define TEMP_ADCPNP2_1          0x150
++#define TEMP_MSR0_1             0x190
++#define TEMP_MSR1_1             0x194
++#define TEMP_MSR2_1             0x198
++#define TEMP_ADCPNP3_1          0x1b4
++#define TEMP_MSR3_1             0x1B8
++
++#define PTPCORESEL		0x400
++
++#define TEMP_MONCTL1_PERIOD_UNIT(x)	((x) & 0x3ff)
++
++#define TEMP_MONCTL2_FILTER_INTERVAL(x)	(((x) & 0x3ff) << 16)
++#define TEMP_MONCTL2_SENSOR_INTERVAL(x)	((x) & 0x3ff)
++
++#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x)	(x)
++
++#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE		BIT(0)
++#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE		BIT(1)
++
++#define TEMP_ADCVALIDMASK_VALID_HIGH		BIT(5)
++#define TEMP_ADCVALIDMASK_VALID_POS(bit)	(bit)
++
++/* MT8173 thermal sensors */
++#define MT8173_TS1	0
++#define MT8173_TS2	1
++#define MT8173_TS3	2
++#define MT8173_TS4	3
++#define MT8173_TSABB	4
++
++/* AUXADC channel 11 is used for the temperature sensors */
++#define MT8173_TEMP_AUXADC_CHANNEL	11
++
++/* The total number of temperature sensors in the MT8173 */
++#define MT8173_NUM_SENSORS		5
++
++/* The number of banks in the MT8173 */
++#define MT8173_NUM_ZONES		4
++
++/* The number of sensing points per bank */
++#define MT8173_NUM_SENSORS_PER_ZONE	4
++
++/* The number of controller in the MT8173 */
++#define MT8173_NUM_CONTROLLER		1
++
++/* The calibration coefficient of sensor  */
++#define MT8173_CALIBRATION	165
++
++/*
++ * Layout of the fuses providing the calibration data
++ * These macros could be used for MT8183, MT8173, MT2701, and MT2712.
++ * MT8183 has 6 sensors and needs 6 VTS calibration data.
++ * MT8173 has 5 sensors and needs 5 VTS calibration data.
++ * MT2701 has 3 sensors and needs 3 VTS calibration data.
++ * MT2712 has 4 sensors and needs 4 VTS calibration data.
++ */
++#define CALIB_BUF0_VALID_V1		BIT(0)
++#define CALIB_BUF1_ADC_GE_V1(x)		(((x) >> 22) & 0x3ff)
++#define CALIB_BUF0_VTS_TS1_V1(x)	(((x) >> 17) & 0x1ff)
++#define CALIB_BUF0_VTS_TS2_V1(x)	(((x) >> 8) & 0x1ff)
++#define CALIB_BUF1_VTS_TS3_V1(x)	(((x) >> 0) & 0x1ff)
++#define CALIB_BUF2_VTS_TS4_V1(x)	(((x) >> 23) & 0x1ff)
++#define CALIB_BUF2_VTS_TS5_V1(x)	(((x) >> 5) & 0x1ff)
++#define CALIB_BUF2_VTS_TSABB_V1(x)	(((x) >> 14) & 0x1ff)
++#define CALIB_BUF0_DEGC_CALI_V1(x)	(((x) >> 1) & 0x3f)
++#define CALIB_BUF0_O_SLOPE_V1(x)	(((x) >> 26) & 0x3f)
++#define CALIB_BUF0_O_SLOPE_SIGN_V1(x)	(((x) >> 7) & 0x1)
++#define CALIB_BUF1_ID_V1(x)		(((x) >> 9) & 0x1)
++
++/*
++ * Layout of the fuses providing the calibration data
++ * These macros could be used for MT7622.
++ */
++#define CALIB_BUF0_ADC_OE_V2(x)		(((x) >> 22) & 0x3ff)
++#define CALIB_BUF0_ADC_GE_V2(x)		(((x) >> 12) & 0x3ff)
++#define CALIB_BUF0_DEGC_CALI_V2(x)	(((x) >> 6) & 0x3f)
++#define CALIB_BUF0_O_SLOPE_V2(x)	(((x) >> 0) & 0x3f)
++#define CALIB_BUF1_VTS_TS1_V2(x)	(((x) >> 23) & 0x1ff)
++#define CALIB_BUF1_VTS_TS2_V2(x)	(((x) >> 14) & 0x1ff)
++#define CALIB_BUF1_VTS_TSABB_V2(x)	(((x) >> 5) & 0x1ff)
++#define CALIB_BUF1_VALID_V2(x)		(((x) >> 4) & 0x1)
++#define CALIB_BUF1_O_SLOPE_SIGN_V2(x)	(((x) >> 3) & 0x1)
++
++/*
++ * Layout of the fuses providing the calibration data
++ * These macros can be used for MT7981 and MT7986.
++ */
++#define CALIB_BUF0_ADC_GE_V3(x)		(((x) >> 0) & 0x3ff)
++#define CALIB_BUF0_DEGC_CALI_V3(x)	(((x) >> 20) & 0x3f)
++#define CALIB_BUF0_O_SLOPE_V3(x)	(((x) >> 26) & 0x3f)
++#define CALIB_BUF1_VTS_TS1_V3(x)	(((x) >> 0) & 0x1ff)
++#define CALIB_BUF1_VTS_TS2_V3(x)	(((x) >> 21) & 0x1ff)
++#define CALIB_BUF1_VTS_TSABB_V3(x)	(((x) >> 9) & 0x1ff)
++#define CALIB_BUF1_VALID_V3(x)		(((x) >> 18) & 0x1)
++#define CALIB_BUF1_O_SLOPE_SIGN_V3(x)	(((x) >> 19) & 0x1)
++#define CALIB_BUF1_ID_V3(x)		(((x) >> 20) & 0x1)
++
++enum {
++	VTS1,
++	VTS2,
++	VTS3,
++	VTS4,
++	VTS5,
++	VTSABB,
++	MAX_NUM_VTS,
++};
++
++enum mtk_thermal_version {
++	MTK_THERMAL_V1 = 1,
++	MTK_THERMAL_V2,
++	MTK_THERMAL_V3,
++};
++
++/* MT2701 thermal sensors */
++#define MT2701_TS1	0
++#define MT2701_TS2	1
++#define MT2701_TSABB	2
++
++/* AUXADC channel 11 is used for the temperature sensors */
++#define MT2701_TEMP_AUXADC_CHANNEL	11
++
++/* The total number of temperature sensors in the MT2701 */
++#define MT2701_NUM_SENSORS	3
++
++/* The number of sensing points per bank */
++#define MT2701_NUM_SENSORS_PER_ZONE	3
++
++/* The number of controller in the MT2701 */
++#define MT2701_NUM_CONTROLLER		1
++
++/* The calibration coefficient of sensor  */
++#define MT2701_CALIBRATION	165
++
++/* MT2712 thermal sensors */
++#define MT2712_TS1	0
++#define MT2712_TS2	1
++#define MT2712_TS3	2
++#define MT2712_TS4	3
++
++/* AUXADC channel 11 is used for the temperature sensors */
++#define MT2712_TEMP_AUXADC_CHANNEL	11
++
++/* The total number of temperature sensors in the MT2712 */
++#define MT2712_NUM_SENSORS	4
++
++/* The number of sensing points per bank */
++#define MT2712_NUM_SENSORS_PER_ZONE	4
++
++/* The number of controller in the MT2712 */
++#define MT2712_NUM_CONTROLLER		1
++
++/* The calibration coefficient of sensor  */
++#define MT2712_CALIBRATION	165
++
++#define MT7622_TEMP_AUXADC_CHANNEL	11
++#define MT7622_NUM_SENSORS		1
++#define MT7622_NUM_ZONES		1
++#define MT7622_NUM_SENSORS_PER_ZONE	1
++#define MT7622_TS1	0
++#define MT7622_NUM_CONTROLLER		1
++
++/* The maximum number of banks */
++#define MAX_NUM_ZONES		8
++
++/* The calibration coefficient of sensor  */
++#define MT7622_CALIBRATION	165
++
++/* MT8183 thermal sensors */
++#define MT8183_TS1	0
++#define MT8183_TS2	1
++#define MT8183_TS3	2
++#define MT8183_TS4	3
++#define MT8183_TS5	4
++#define MT8183_TSABB	5
++
++/* AUXADC channel  is used for the temperature sensors */
++#define MT8183_TEMP_AUXADC_CHANNEL	11
++
++/* The total number of temperature sensors in the MT8183 */
++#define MT8183_NUM_SENSORS	6
++
++/* The number of banks in the MT8183 */
++#define MT8183_NUM_ZONES               1
++
++/* The number of sensing points per bank */
++#define MT8183_NUM_SENSORS_PER_ZONE	 6
++
++/* The number of controller in the MT8183 */
++#define MT8183_NUM_CONTROLLER		2
++
++/* The calibration coefficient of sensor  */
++#define MT8183_CALIBRATION	153
++
++/* AUXADC channel 11 is used for the temperature sensors */
++#define MT7986_TEMP_AUXADC_CHANNEL	11
++
++/* The total number of temperature sensors in the MT7986 */
++#define MT7986_NUM_SENSORS		1
++
++/* The number of banks in the MT7986 */
++#define MT7986_NUM_ZONES		1
++
++/* The number of sensing points per bank */
++#define MT7986_NUM_SENSORS_PER_ZONE	1
++
++/* MT7986 thermal sensors */
++#define MT7986_TS1			0
++
++/* The number of controller in the MT7986 */
++#define MT7986_NUM_CONTROLLER		1
++
++/* The calibration coefficient of sensor  */
++#define MT7986_CALIBRATION		165
++
++struct mtk_thermal;
++
++struct thermal_bank_cfg {
++	unsigned int num_sensors;
++	const int *sensors;
++};
++
++struct mtk_thermal_bank {
++	struct mtk_thermal *mt;
++	int id;
++};
++
++struct mtk_thermal_data {
++	s32 num_banks;
++	s32 num_sensors;
++	s32 auxadc_channel;
++	const int *vts_index;
++	const int *sensor_mux_values;
++	const int *msr;
++	const int *adcpnp;
++	const int cali_val;
++	const int num_controller;
++	const int *controller_offset;
++	bool need_switch_bank;
++	struct thermal_bank_cfg bank_data[MAX_NUM_ZONES];
++	enum mtk_thermal_version version;
++};
++
++struct mtk_thermal {
++	struct device *dev;
++	void __iomem *thermal_base;
++
++	struct clk *clk_peri_therm;
++	struct clk *clk_auxadc;
++	/* lock: for getting and putting banks */
++	struct mutex lock;
++
++	/* Calibration values */
++	s32 adc_ge;
++	s32 adc_oe;
++	s32 degc_cali;
++	s32 o_slope;
++	s32 o_slope_sign;
++	s32 vts[MAX_NUM_VTS];
++
++	const struct mtk_thermal_data *conf;
++	struct mtk_thermal_bank banks[MAX_NUM_ZONES];
++
++	int (*raw_to_mcelsius)(struct mtk_thermal *mt, int sensno, s32 raw);
++};
++
++/* MT8183 thermal sensor data */
++static const int mt8183_bank_data[MT8183_NUM_SENSORS] = {
++	MT8183_TS1, MT8183_TS2, MT8183_TS3, MT8183_TS4, MT8183_TS5, MT8183_TSABB
++};
++
++static const int mt8183_msr[MT8183_NUM_SENSORS_PER_ZONE] = {
++	TEMP_MSR0_1, TEMP_MSR1_1, TEMP_MSR2_1, TEMP_MSR1, TEMP_MSR0, TEMP_MSR3_1
++};
++
++static const int mt8183_adcpnp[MT8183_NUM_SENSORS_PER_ZONE] = {
++	TEMP_ADCPNP0_1, TEMP_ADCPNP1_1, TEMP_ADCPNP2_1,
++	TEMP_ADCPNP1, TEMP_ADCPNP0, TEMP_ADCPNP3_1
++};
++
++static const int mt8183_mux_values[MT8183_NUM_SENSORS] = { 0, 1, 2, 3, 4, 0 };
++static const int mt8183_tc_offset[MT8183_NUM_CONTROLLER] = {0x0, 0x100};
++
++static const int mt8183_vts_index[MT8183_NUM_SENSORS] = {
++	VTS1, VTS2, VTS3, VTS4, VTS5, VTSABB
++};
++
++/* MT8173 thermal sensor data */
++static const int mt8173_bank_data[MT8173_NUM_ZONES][3] = {
++	{ MT8173_TS2, MT8173_TS3 },
++	{ MT8173_TS2, MT8173_TS4 },
++	{ MT8173_TS1, MT8173_TS2, MT8173_TSABB },
++	{ MT8173_TS2 },
++};
++
++static const int mt8173_msr[MT8173_NUM_SENSORS_PER_ZONE] = {
++	TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3
++};
++
++static const int mt8173_adcpnp[MT8173_NUM_SENSORS_PER_ZONE] = {
++	TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3
++};
++
++static const int mt8173_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 };
++static const int mt8173_tc_offset[MT8173_NUM_CONTROLLER] = { 0x0, };
++
++static const int mt8173_vts_index[MT8173_NUM_SENSORS] = {
++	VTS1, VTS2, VTS3, VTS4, VTSABB
++};
++
++/* MT2701 thermal sensor data */
++static const int mt2701_bank_data[MT2701_NUM_SENSORS] = {
++	MT2701_TS1, MT2701_TS2, MT2701_TSABB
++};
++
++static const int mt2701_msr[MT2701_NUM_SENSORS_PER_ZONE] = {
++	TEMP_MSR0, TEMP_MSR1, TEMP_MSR2
++};
++
++static const int mt2701_adcpnp[MT2701_NUM_SENSORS_PER_ZONE] = {
++	TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2
++};
++
++static const int mt2701_mux_values[MT2701_NUM_SENSORS] = { 0, 1, 16 };
++static const int mt2701_tc_offset[MT2701_NUM_CONTROLLER] = { 0x0, };
++
++static const int mt2701_vts_index[MT2701_NUM_SENSORS] = {
++	VTS1, VTS2, VTS3
++};
++
++/* MT2712 thermal sensor data */
++static const int mt2712_bank_data[MT2712_NUM_SENSORS] = {
++	MT2712_TS1, MT2712_TS2, MT2712_TS3, MT2712_TS4
++};
++
++static const int mt2712_msr[MT2712_NUM_SENSORS_PER_ZONE] = {
++	TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3
++};
++
++static const int mt2712_adcpnp[MT2712_NUM_SENSORS_PER_ZONE] = {
++	TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3
++};
++
++static const int mt2712_mux_values[MT2712_NUM_SENSORS] = { 0, 1, 2, 3 };
++static const int mt2712_tc_offset[MT2712_NUM_CONTROLLER] = { 0x0, };
++
++static const int mt2712_vts_index[MT2712_NUM_SENSORS] = {
++	VTS1, VTS2, VTS3, VTS4
++};
++
++/* MT7622 thermal sensor data */
++static const int mt7622_bank_data[MT7622_NUM_SENSORS] = { MT7622_TS1, };
++static const int mt7622_msr[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, };
++static const int mt7622_adcpnp[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, };
++static const int mt7622_mux_values[MT7622_NUM_SENSORS] = { 0, };
++static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 };
++static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, };
++
++/* MT7986 thermal sensor data */
++static const int mt7986_bank_data[MT7986_NUM_SENSORS] = { MT7986_TS1, };
++static const int mt7986_msr[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, };
++static const int mt7986_adcpnp[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, };
++static const int mt7986_mux_values[MT7986_NUM_SENSORS] = { 0, };
++static const int mt7986_vts_index[MT7986_NUM_SENSORS] = { VTS1 };
++static const int mt7986_tc_offset[MT7986_NUM_CONTROLLER] = { 0x0, };
++
++/*
++ * The MT8173 thermal controller has four banks. Each bank can read up to
++ * four temperature sensors simultaneously. The MT8173 has a total of 5
++ * temperature sensors. We use each bank to measure a certain area of the
++ * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple
++ * areas, hence is used in different banks.
++ *
++ * The thermal core only gets the maximum temperature of all banks, so
++ * the bank concept wouldn't be necessary here. However, the SVS (Smart
++ * Voltage Scaling) unit makes its decisions based on the same bank
++ * data, and this indeed needs the temperatures of the individual banks
++ * for making better decisions.
++ */
++static const struct mtk_thermal_data mt8173_thermal_data = {
++	.auxadc_channel = MT8173_TEMP_AUXADC_CHANNEL,
++	.num_banks = MT8173_NUM_ZONES,
++	.num_sensors = MT8173_NUM_SENSORS,
++	.vts_index = mt8173_vts_index,
++	.cali_val = MT8173_CALIBRATION,
++	.num_controller = MT8173_NUM_CONTROLLER,
++	.controller_offset = mt8173_tc_offset,
++	.need_switch_bank = true,
++	.bank_data = {
++		{
++			.num_sensors = 2,
++			.sensors = mt8173_bank_data[0],
++		}, {
++			.num_sensors = 2,
++			.sensors = mt8173_bank_data[1],
++		}, {
++			.num_sensors = 3,
++			.sensors = mt8173_bank_data[2],
++		}, {
++			.num_sensors = 1,
++			.sensors = mt8173_bank_data[3],
++		},
++	},
++	.msr = mt8173_msr,
++	.adcpnp = mt8173_adcpnp,
++	.sensor_mux_values = mt8173_mux_values,
++	.version = MTK_THERMAL_V1,
++};
++
++/*
++ * The MT2701 thermal controller has one bank, which can read up to
++ * three temperature sensors simultaneously. The MT2701 has a total of 3
++ * temperature sensors.
++ *
++ * The thermal core only gets the maximum temperature of this one bank,
++ * so the bank concept wouldn't be necessary here. However, the SVS (Smart
++ * Voltage Scaling) unit makes its decisions based on the same bank
++ * data.
++ */
++static const struct mtk_thermal_data mt2701_thermal_data = {
++	.auxadc_channel = MT2701_TEMP_AUXADC_CHANNEL,
++	.num_banks = 1,
++	.num_sensors = MT2701_NUM_SENSORS,
++	.vts_index = mt2701_vts_index,
++	.cali_val = MT2701_CALIBRATION,
++	.num_controller = MT2701_NUM_CONTROLLER,
++	.controller_offset = mt2701_tc_offset,
++	.need_switch_bank = true,
++	.bank_data = {
++		{
++			.num_sensors = 3,
++			.sensors = mt2701_bank_data,
++		},
++	},
++	.msr = mt2701_msr,
++	.adcpnp = mt2701_adcpnp,
++	.sensor_mux_values = mt2701_mux_values,
++	.version = MTK_THERMAL_V1,
++};
++
++/*
++ * The MT2712 thermal controller has one bank, which can read up to
++ * four temperature sensors simultaneously. The MT2712 has a total of 4
++ * temperature sensors.
++ *
++ * The thermal core only gets the maximum temperature of this one bank,
++ * so the bank concept wouldn't be necessary here. However, the SVS (Smart
++ * Voltage Scaling) unit makes its decisions based on the same bank
++ * data.
++ */
++static const struct mtk_thermal_data mt2712_thermal_data = {
++	.auxadc_channel = MT2712_TEMP_AUXADC_CHANNEL,
++	.num_banks = 1,
++	.num_sensors = MT2712_NUM_SENSORS,
++	.vts_index = mt2712_vts_index,
++	.cali_val = MT2712_CALIBRATION,
++	.num_controller = MT2712_NUM_CONTROLLER,
++	.controller_offset = mt2712_tc_offset,
++	.need_switch_bank = true,
++	.bank_data = {
++		{
++			.num_sensors = 4,
++			.sensors = mt2712_bank_data,
++		},
++	},
++	.msr = mt2712_msr,
++	.adcpnp = mt2712_adcpnp,
++	.sensor_mux_values = mt2712_mux_values,
++	.version = MTK_THERMAL_V1,
++};
++
++/*
++ * MT7622 have only one sensing point which uses AUXADC Channel 11 for raw data
++ * access.
++ */
++static const struct mtk_thermal_data mt7622_thermal_data = {
++	.auxadc_channel = MT7622_TEMP_AUXADC_CHANNEL,
++	.num_banks = MT7622_NUM_ZONES,
++	.num_sensors = MT7622_NUM_SENSORS,
++	.vts_index = mt7622_vts_index,
++	.cali_val = MT7622_CALIBRATION,
++	.num_controller = MT7622_NUM_CONTROLLER,
++	.controller_offset = mt7622_tc_offset,
++	.need_switch_bank = true,
++	.bank_data = {
++		{
++			.num_sensors = 1,
++			.sensors = mt7622_bank_data,
++		},
++	},
++	.msr = mt7622_msr,
++	.adcpnp = mt7622_adcpnp,
++	.sensor_mux_values = mt7622_mux_values,
++	.version = MTK_THERMAL_V2,
++};
++
++/*
++ * The MT8183 thermal controller has one bank for the current SW framework.
++ * The MT8183 has a total of 6 temperature sensors.
++ * There are two thermal controller to control the six sensor.
++ * The first one bind 2 sensor, and the other bind 4 sensors.
++ * The thermal core only gets the maximum temperature of all sensor, so
++ * the bank concept wouldn't be necessary here. However, the SVS (Smart
++ * Voltage Scaling) unit makes its decisions based on the same bank
++ * data, and this indeed needs the temperatures of the individual banks
++ * for making better decisions.
++ */
++static const struct mtk_thermal_data mt8183_thermal_data = {
++	.auxadc_channel = MT8183_TEMP_AUXADC_CHANNEL,
++	.num_banks = MT8183_NUM_ZONES,
++	.num_sensors = MT8183_NUM_SENSORS,
++	.vts_index = mt8183_vts_index,
++	.cali_val = MT8183_CALIBRATION,
++	.num_controller = MT8183_NUM_CONTROLLER,
++	.controller_offset = mt8183_tc_offset,
++	.need_switch_bank = false,
++	.bank_data = {
++		{
++			.num_sensors = 6,
++			.sensors = mt8183_bank_data,
++		},
++	},
++
++	.msr = mt8183_msr,
++	.adcpnp = mt8183_adcpnp,
++	.sensor_mux_values = mt8183_mux_values,
++	.version = MTK_THERMAL_V1,
++};
++
++/*
++ * MT7986 uses AUXADC Channel 11 for raw data access.
++ */
++static const struct mtk_thermal_data mt7986_thermal_data = {
++	.auxadc_channel = MT7986_TEMP_AUXADC_CHANNEL,
++	.num_banks = MT7986_NUM_ZONES,
++	.num_sensors = MT7986_NUM_SENSORS,
++	.vts_index = mt7986_vts_index,
++	.cali_val = MT7986_CALIBRATION,
++	.num_controller = MT7986_NUM_CONTROLLER,
++	.controller_offset = mt7986_tc_offset,
++	.need_switch_bank = true,
++	.bank_data = {
++		{
++			.num_sensors = 1,
++			.sensors = mt7986_bank_data,
++		},
++	},
++	.msr = mt7986_msr,
++	.adcpnp = mt7986_adcpnp,
++	.sensor_mux_values = mt7986_mux_values,
++	.version = MTK_THERMAL_V3,
++};
++
++/**
++ * raw_to_mcelsius_v1 - convert a raw ADC value to mcelsius
++ * @mt:	The thermal controller
++ * @sensno:	sensor number
++ * @raw:	raw ADC value
++ *
++ * This converts the raw ADC value to mcelsius using the SoC specific
++ * calibration constants
++ */
++static int raw_to_mcelsius_v1(struct mtk_thermal *mt, int sensno, s32 raw)
++{
++	s32 tmp;
++
++	raw &= 0xfff;
++
++	tmp = 203450520 << 3;
++	tmp /= mt->conf->cali_val + mt->o_slope;
++	tmp /= 10000 + mt->adc_ge;
++	tmp *= raw - mt->vts[sensno] - 3350;
++	tmp >>= 3;
++
++	return mt->degc_cali * 500 - tmp;
++}
++
++static int raw_to_mcelsius_v2(struct mtk_thermal *mt, int sensno, s32 raw)
++{
++	s32 format_1;
++	s32 format_2;
++	s32 g_oe;
++	s32 g_gain;
++	s32 g_x_roomt;
++	s32 tmp;
++
++	if (raw == 0)
++		return 0;
++
++	raw &= 0xfff;
++	g_gain = 10000 + (((mt->adc_ge - 512) * 10000) >> 12);
++	g_oe = mt->adc_oe - 512;
++	format_1 = mt->vts[VTS2] + 3105 - g_oe;
++	format_2 = (mt->degc_cali * 10) >> 1;
++	g_x_roomt = (((format_1 * 10000) >> 12) * 10000) / g_gain;
++
++	tmp = (((((raw - g_oe) * 10000) >> 12) * 10000) / g_gain) - g_x_roomt;
++	tmp = tmp * 10 * 100 / 11;
++
++	if (mt->o_slope_sign == 0)
++		tmp = tmp / (165 - mt->o_slope);
++	else
++		tmp = tmp / (165 + mt->o_slope);
++
++	return (format_2 - tmp) * 100;
++}
++
++static int raw_to_mcelsius_v3(struct mtk_thermal *mt, int sensno, s32 raw)
++{
++	s32 tmp;
++
++	if (raw == 0)
++		return 0;
++
++	raw &= 0xfff;
++	tmp = 100000 * 15 / 16 * 10000;
++	tmp /= 4096 - 512 + mt->adc_ge;
++	tmp /= 1490;
++	tmp *= raw - mt->vts[sensno] - 2900;
++
++	return mt->degc_cali * 500 - tmp;
++}
++
++/**
++ * mtk_thermal_get_bank - get bank
++ * @bank:	The bank
++ *
++ * The bank registers are banked, we have to select a bank in the
++ * PTPCORESEL register to access it.
++ */
++static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank)
++{
++	struct mtk_thermal *mt = bank->mt;
++	u32 val;
++
++	if (mt->conf->need_switch_bank) {
++		mutex_lock(&mt->lock);
++
++		val = readl(mt->thermal_base + PTPCORESEL);
++		val &= ~0xf;
++		val |= bank->id;
++		writel(val, mt->thermal_base + PTPCORESEL);
++	}
++}
++
++/**
++ * mtk_thermal_put_bank - release bank
++ * @bank:	The bank
++ *
++ * release a bank previously taken with mtk_thermal_get_bank,
++ */
++static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank)
++{
++	struct mtk_thermal *mt = bank->mt;
++
++	if (mt->conf->need_switch_bank)
++		mutex_unlock(&mt->lock);
++}
++
++/**
++ * mtk_thermal_bank_temperature - get the temperature of a bank
++ * @bank:	The bank
++ *
++ * The temperature of a bank is considered the maximum temperature of
++ * the sensors associated to the bank.
++ */
++static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank)
++{
++	struct mtk_thermal *mt = bank->mt;
++	const struct mtk_thermal_data *conf = mt->conf;
++	int i, temp = INT_MIN, max = INT_MIN;
++	u32 raw;
++
++	for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) {
++		raw = readl(mt->thermal_base + conf->msr[i]);
++
++		temp = mt->raw_to_mcelsius(
++			mt, conf->bank_data[bank->id].sensors[i], raw);
++
++
++		/*
++		 * The first read of a sensor often contains very high bogus
++		 * temperature value. Filter these out so that the system does
++		 * not immediately shut down.
++		 */
++		if (temp > 200000)
++			temp = 0;
++
++		if (temp > max)
++			max = temp;
++	}
++
++	return max;
++}
++
++static int mtk_read_temp(struct thermal_zone_device *tz, int *temperature)
++{
++	struct mtk_thermal *mt = tz->devdata;
++	int i;
++	int tempmax = INT_MIN;
++
++	for (i = 0; i < mt->conf->num_banks; i++) {
++		struct mtk_thermal_bank *bank = &mt->banks[i];
++
++		mtk_thermal_get_bank(bank);
++
++		tempmax = max(tempmax, mtk_thermal_bank_temperature(bank));
++
++		mtk_thermal_put_bank(bank);
++	}
++
++	*temperature = tempmax;
++
++	return 0;
++}
++
++static const struct thermal_zone_device_ops mtk_thermal_ops = {
++	.get_temp = mtk_read_temp,
++};
++
++static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num,
++				  u32 apmixed_phys_base, u32 auxadc_phys_base,
++				  int ctrl_id)
++{
++	struct mtk_thermal_bank *bank = &mt->banks[num];
++	const struct mtk_thermal_data *conf = mt->conf;
++	int i;
++
++	int offset = mt->conf->controller_offset[ctrl_id];
++	void __iomem *controller_base = mt->thermal_base + offset;
++
++	bank->id = num;
++	bank->mt = mt;
++
++	mtk_thermal_get_bank(bank);
++
++	/* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */
++	writel(TEMP_MONCTL1_PERIOD_UNIT(12), controller_base + TEMP_MONCTL1);
++
++	/*
++	 * filt interval is 1 * 46.540us = 46.54us,
++	 * sen interval is 429 * 46.540us = 19.96ms
++	 */
++	writel(TEMP_MONCTL2_FILTER_INTERVAL(1) |
++			TEMP_MONCTL2_SENSOR_INTERVAL(429),
++			controller_base + TEMP_MONCTL2);
++
++	/* poll is set to 10u */
++	writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768),
++	       controller_base + TEMP_AHBPOLL);
++
++	/* temperature sampling control, 1 sample */
++	writel(0x0, controller_base + TEMP_MSRCTL0);
++
++	/* exceed this polling time, IRQ would be inserted */
++	writel(0xffffffff, controller_base + TEMP_AHBTO);
++
++	/* number of interrupts per event, 1 is enough */
++	writel(0x0, controller_base + TEMP_MONIDET0);
++	writel(0x0, controller_base + TEMP_MONIDET1);
++
++	/*
++	 * The MT8173 thermal controller does not have its own ADC. Instead it
++	 * uses AHB bus accesses to control the AUXADC. To do this the thermal
++	 * controller has to be programmed with the physical addresses of the
++	 * AUXADC registers and with the various bit positions in the AUXADC.
++	 * Also the thermal controller controls a mux in the APMIXEDSYS register
++	 * space.
++	 */
++
++	/*
++	 * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0)
++	 * automatically by hw
++	 */
++	writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCMUX);
++
++	/* AHB address for auxadc mux selection */
++	writel(auxadc_phys_base + AUXADC_CON1_CLR_V,
++	       controller_base + TEMP_ADCMUXADDR);
++
++	if (mt->conf->version == MTK_THERMAL_V1) {
++		/* AHB address for pnp sensor mux selection */
++		writel(apmixed_phys_base + APMIXED_SYS_TS_CON1,
++		       controller_base + TEMP_PNPMUXADDR);
++	}
++
++	/* AHB value for auxadc enable */
++	writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCEN);
++
++	/* AHB address for auxadc enable (channel 0 immediate mode selected) */
++	writel(auxadc_phys_base + AUXADC_CON1_SET_V,
++	       controller_base + TEMP_ADCENADDR);
++
++	/* AHB address for auxadc valid bit */
++	writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
++	       controller_base + TEMP_ADCVALIDADDR);
++
++	/* AHB address for auxadc voltage output */
++	writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
++	       controller_base + TEMP_ADCVOLTADDR);
++
++	/* read valid & voltage are at the same register */
++	writel(0x0, controller_base + TEMP_RDCTRL);
++
++	/* indicate where the valid bit is */
++	writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12),
++	       controller_base + TEMP_ADCVALIDMASK);
++
++	/* no shift */
++	writel(0x0, controller_base + TEMP_ADCVOLTAGESHIFT);
++
++	/* enable auxadc mux write transaction */
++	writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
++		controller_base + TEMP_ADCWRITECTRL);
++
++	for (i = 0; i < conf->bank_data[num].num_sensors; i++)
++		writel(conf->sensor_mux_values[conf->bank_data[num].sensors[i]],
++		       mt->thermal_base + conf->adcpnp[i]);
++
++	writel((1 << conf->bank_data[num].num_sensors) - 1,
++	       controller_base + TEMP_MONCTL0);
++
++	writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE |
++	       TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
++	       controller_base + TEMP_ADCWRITECTRL);
++
++	mtk_thermal_put_bank(bank);
++}
++
++static u64 of_get_phys_base(struct device_node *np)
++{
++	u64 size64;
++	const __be32 *regaddr_p;
++
++	regaddr_p = of_get_address(np, 0, &size64, NULL);
++	if (!regaddr_p)
++		return OF_BAD_ADDR;
++
++	return of_translate_address(np, regaddr_p);
++}
++
++static int mtk_thermal_extract_efuse_v1(struct mtk_thermal *mt, u32 *buf)
++{
++	int i;
++
++	if (!(buf[0] & CALIB_BUF0_VALID_V1))
++		return -EINVAL;
++
++	mt->adc_ge = CALIB_BUF1_ADC_GE_V1(buf[1]);
++
++	for (i = 0; i < mt->conf->num_sensors; i++) {
++		switch (mt->conf->vts_index[i]) {
++		case VTS1:
++			mt->vts[VTS1] = CALIB_BUF0_VTS_TS1_V1(buf[0]);
++			break;
++		case VTS2:
++			mt->vts[VTS2] = CALIB_BUF0_VTS_TS2_V1(buf[0]);
++			break;
++		case VTS3:
++			mt->vts[VTS3] = CALIB_BUF1_VTS_TS3_V1(buf[1]);
++			break;
++		case VTS4:
++			mt->vts[VTS4] = CALIB_BUF2_VTS_TS4_V1(buf[2]);
++			break;
++		case VTS5:
++			mt->vts[VTS5] = CALIB_BUF2_VTS_TS5_V1(buf[2]);
++			break;
++		case VTSABB:
++			mt->vts[VTSABB] =
++				CALIB_BUF2_VTS_TSABB_V1(buf[2]);
++			break;
++		default:
++			break;
++		}
++	}
++
++	mt->degc_cali = CALIB_BUF0_DEGC_CALI_V1(buf[0]);
++	if (CALIB_BUF1_ID_V1(buf[1]) &
++	    CALIB_BUF0_O_SLOPE_SIGN_V1(buf[0]))
++		mt->o_slope = -CALIB_BUF0_O_SLOPE_V1(buf[0]);
++	else
++		mt->o_slope = CALIB_BUF0_O_SLOPE_V1(buf[0]);
++
++	return 0;
++}
++
++static int mtk_thermal_extract_efuse_v2(struct mtk_thermal *mt, u32 *buf)
++{
++	if (!CALIB_BUF1_VALID_V2(buf[1]))
++		return -EINVAL;
++
++	mt->adc_oe = CALIB_BUF0_ADC_OE_V2(buf[0]);
++	mt->adc_ge = CALIB_BUF0_ADC_GE_V2(buf[0]);
++	mt->degc_cali = CALIB_BUF0_DEGC_CALI_V2(buf[0]);
++	mt->o_slope = CALIB_BUF0_O_SLOPE_V2(buf[0]);
++	mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V2(buf[1]);
++	mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V2(buf[1]);
++	mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V2(buf[1]);
++	mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V2(buf[1]);
++
++	return 0;
++}
++
++static int mtk_thermal_extract_efuse_v3(struct mtk_thermal *mt, u32 *buf)
++{
++	if (!CALIB_BUF1_VALID_V3(buf[1]))
++		return -EINVAL;
++
++	mt->adc_ge = CALIB_BUF0_ADC_GE_V3(buf[0]);
++	mt->degc_cali = CALIB_BUF0_DEGC_CALI_V3(buf[0]);
++	mt->o_slope = CALIB_BUF0_O_SLOPE_V3(buf[0]);
++	mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V3(buf[1]);
++	mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V3(buf[1]);
++	mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V3(buf[1]);
++	mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V3(buf[1]);
++
++	if (CALIB_BUF1_ID_V3(buf[1]) == 0)
++		mt->o_slope = 0;
++
++	return 0;
++}
++
++static int mtk_thermal_get_calibration_data(struct device *dev,
++					    struct mtk_thermal *mt)
++{
++	struct nvmem_cell *cell;
++	u32 *buf;
++	size_t len;
++	int i, ret = 0;
++
++	/* Start with default values */
++	mt->adc_ge = 512;
++	mt->adc_oe = 512;
++	for (i = 0; i < mt->conf->num_sensors; i++)
++		mt->vts[i] = 260;
++	mt->degc_cali = 40;
++	mt->o_slope = 0;
++
++	cell = nvmem_cell_get(dev, "calibration-data");
++	if (IS_ERR(cell)) {
++		if (PTR_ERR(cell) == -EPROBE_DEFER)
++			return PTR_ERR(cell);
++		return 0;
++	}
++
++	buf = (u32 *)nvmem_cell_read(cell, &len);
++
++	nvmem_cell_put(cell);
++
++	if (IS_ERR(buf))
++		return PTR_ERR(buf);
++
++	if (len < 3 * sizeof(u32)) {
++		dev_warn(dev, "invalid calibration data\n");
++		ret = -EINVAL;
++		goto out;
++	}
++
++	switch (mt->conf->version) {
++	case MTK_THERMAL_V1:
++		ret = mtk_thermal_extract_efuse_v1(mt, buf);
++		break;
++	case MTK_THERMAL_V2:
++		ret = mtk_thermal_extract_efuse_v2(mt, buf);
++		break;
++	case MTK_THERMAL_V3:
++		ret = mtk_thermal_extract_efuse_v3(mt, buf);
++		break;
++	default:
++		ret = -EINVAL;
++		break;
++	}
++
++	if (ret) {
++		dev_info(dev, "Device not calibrated, using default calibration values\n");
++		ret = 0;
++	}
++
++out:
++	kfree(buf);
++
++	return ret;
++}
++
++static const struct of_device_id mtk_thermal_of_match[] = {
++	{
++		.compatible = "mediatek,mt8173-thermal",
++		.data = (void *)&mt8173_thermal_data,
++	},
++	{
++		.compatible = "mediatek,mt2701-thermal",
++		.data = (void *)&mt2701_thermal_data,
++	},
++	{
++		.compatible = "mediatek,mt2712-thermal",
++		.data = (void *)&mt2712_thermal_data,
++	},
++	{
++		.compatible = "mediatek,mt7622-thermal",
++		.data = (void *)&mt7622_thermal_data,
++	},
++	{
++		.compatible = "mediatek,mt7986-thermal",
++		.data = (void *)&mt7986_thermal_data,
++	},
++	{
++		.compatible = "mediatek,mt8183-thermal",
++		.data = (void *)&mt8183_thermal_data,
++	}, {
++	},
++};
++MODULE_DEVICE_TABLE(of, mtk_thermal_of_match);
++
++static void mtk_thermal_turn_on_buffer(void __iomem *apmixed_base)
++{
++	int tmp;
++
++	tmp = readl(apmixed_base + APMIXED_SYS_TS_CON1);
++	tmp &= ~(0x37);
++	tmp |= 0x1;
++	writel(tmp, apmixed_base + APMIXED_SYS_TS_CON1);
++	udelay(200);
++}
++
++static void mtk_thermal_release_periodic_ts(struct mtk_thermal *mt,
++					    void __iomem *auxadc_base)
++{
++	int tmp;
++
++	writel(0x800, auxadc_base + AUXADC_CON1_SET_V);
++	writel(0x1, mt->thermal_base + TEMP_MONCTL0);
++	tmp = readl(mt->thermal_base + TEMP_MSRCTL1);
++	writel((tmp & (~0x10e)), mt->thermal_base + TEMP_MSRCTL1);
++}
++
++static int mtk_thermal_probe(struct platform_device *pdev)
++{
++	int ret, i, ctrl_id;
++	struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node;
++	struct mtk_thermal *mt;
++	u64 auxadc_phys_base, apmixed_phys_base;
++	struct thermal_zone_device *tzdev;
++	void __iomem *apmixed_base, *auxadc_base;
++
++	mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL);
++	if (!mt)
++		return -ENOMEM;
++
++	mt->conf = of_device_get_match_data(&pdev->dev);
++
++	mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm");
++	if (IS_ERR(mt->clk_peri_therm))
++		return PTR_ERR(mt->clk_peri_therm);
++
++	mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc");
++	if (IS_ERR(mt->clk_auxadc))
++		return PTR_ERR(mt->clk_auxadc);
++
++	mt->thermal_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
++	if (IS_ERR(mt->thermal_base))
++		return PTR_ERR(mt->thermal_base);
++
++	ret = mtk_thermal_get_calibration_data(&pdev->dev, mt);
++	if (ret)
++		return ret;
++
++	mutex_init(&mt->lock);
++
++	mt->dev = &pdev->dev;
++
++	auxadc = of_parse_phandle(np, "mediatek,auxadc", 0);
++	if (!auxadc) {
++		dev_err(&pdev->dev, "missing auxadc node\n");
++		return -ENODEV;
++	}
++
++	auxadc_base = of_iomap(auxadc, 0);
++	auxadc_phys_base = of_get_phys_base(auxadc);
++
++	of_node_put(auxadc);
++
++	if (auxadc_phys_base == OF_BAD_ADDR) {
++		dev_err(&pdev->dev, "Can't get auxadc phys address\n");
++		return -EINVAL;
++	}
++
++	apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0);
++	if (!apmixedsys) {
++		dev_err(&pdev->dev, "missing apmixedsys node\n");
++		return -ENODEV;
++	}
++
++	apmixed_base = of_iomap(apmixedsys, 0);
++	apmixed_phys_base = of_get_phys_base(apmixedsys);
++
++	of_node_put(apmixedsys);
++
++	if (apmixed_phys_base == OF_BAD_ADDR) {
++		dev_err(&pdev->dev, "Can't get auxadc phys address\n");
++		return -EINVAL;
++	}
++
++	ret = device_reset_optional(&pdev->dev);
++	if (ret)
++		return ret;
++
++	ret = clk_prepare_enable(mt->clk_auxadc);
++	if (ret) {
++		dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret);
++		return ret;
++	}
++
++	ret = clk_prepare_enable(mt->clk_peri_therm);
++	if (ret) {
++		dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret);
++		goto err_disable_clk_auxadc;
++	}
++
++	if (mt->conf->version != MTK_THERMAL_V1) {
++		mtk_thermal_turn_on_buffer(apmixed_base);
++		mtk_thermal_release_periodic_ts(mt, auxadc_base);
++	}
++
++	if (mt->conf->version == MTK_THERMAL_V1)
++		mt->raw_to_mcelsius = raw_to_mcelsius_v1;
++	else if (mt->conf->version == MTK_THERMAL_V2)
++		mt->raw_to_mcelsius = raw_to_mcelsius_v2;
++	else
++		mt->raw_to_mcelsius = raw_to_mcelsius_v3;
++
++	for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++)
++		for (i = 0; i < mt->conf->num_banks; i++)
++			mtk_thermal_init_bank(mt, i, apmixed_phys_base,
++					      auxadc_phys_base, ctrl_id);
++
++	platform_set_drvdata(pdev, mt);
++
++	tzdev = devm_thermal_of_zone_register(&pdev->dev, 0, mt,
++					      &mtk_thermal_ops);
++	if (IS_ERR(tzdev)) {
++		ret = PTR_ERR(tzdev);
++		goto err_disable_clk_peri_therm;
++	}
++
++	ret = devm_thermal_add_hwmon_sysfs(tzdev);
++	if (ret)
++		dev_warn(&pdev->dev, "error in thermal_add_hwmon_sysfs");
++
++	return 0;
++
++err_disable_clk_peri_therm:
++	clk_disable_unprepare(mt->clk_peri_therm);
++err_disable_clk_auxadc:
++	clk_disable_unprepare(mt->clk_auxadc);
++
++	return ret;
++}
++
++static int mtk_thermal_remove(struct platform_device *pdev)
++{
++	struct mtk_thermal *mt = platform_get_drvdata(pdev);
++
++	clk_disable_unprepare(mt->clk_peri_therm);
++	clk_disable_unprepare(mt->clk_auxadc);
++
++	return 0;
++}
++
++static struct platform_driver mtk_thermal_driver = {
++	.probe = mtk_thermal_probe,
++	.remove = mtk_thermal_remove,
++	.driver = {
++		.name = "mtk-thermal",
++		.of_match_table = mtk_thermal_of_match,
++	},
++};
++
++module_platform_driver(mtk_thermal_driver);
++
++MODULE_AUTHOR("Michael Kao <michael.kao@mediatek.com>");
++MODULE_AUTHOR("Louis Yu <louis.yu@mediatek.com>");
++MODULE_AUTHOR("Dawei Chien <dawei.chien@mediatek.com>");
++MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
++MODULE_AUTHOR("Hanyi Wu <hanyi.wu@mediatek.com>");
++MODULE_DESCRIPTION("Mediatek thermal driver");
++MODULE_LICENSE("GPL v2");
diff --git a/target/linux/mediatek/patches-6.1/830-v6.3-06-thermal-drivers-mediatek-Add-the-Low-Voltage-Thermal.patch b/target/linux/mediatek/patches-6.1/830-v6.3-06-thermal-drivers-mediatek-Add-the-Low-Voltage-Thermal.patch
new file mode 100644
index 00000000000000..2ae3734e409665
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.3-06-thermal-drivers-mediatek-Add-the-Low-Voltage-Thermal.patch
@@ -0,0 +1,1298 @@
+From 325fadf27b21f7d79843c3cc282b7f3e6620ad3d Mon Sep 17 00:00:00 2001
+From: Balsam CHIHI <bchihi@baylibre.com>
+Date: Thu, 9 Feb 2023 11:56:26 +0100
+Subject: [PATCH 06/42] thermal/drivers/mediatek: Add the Low Voltage Thermal
+ Sensor driver
+
+The Low Voltage Thermal Sensor (LVTS) is a multiple sensors, multi
+controllers contained in a thermal domain.
+
+A thermal domains can be the MCU or the AP.
+
+Each thermal domains contain up to seven controllers, each thermal
+controller handle up to four thermal sensors.
+
+The LVTS has two Finite State Machines (FSM), one to handle the
+functionin temperatures range like hot or cold temperature and another
+one to handle monitoring trip point. The FSM notifies via interrupts
+when a trip point is crossed.
+
+The interrupt is managed at the thermal controller level, so when an
+interrupt occurs, the driver has to find out which sensor triggered
+such an interrupt.
+
+The sampling of the thermal can be filtered or immediate. For the
+former, the LVTS measures several points and applies a low pass
+filter.
+
+Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+
+On MT8195 Tomato Chromebook:
+
+Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Link: https://lore.kernel.org/r/20230209105628.50294-5-bchihi@baylibre.com
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+---
+ drivers/thermal/mediatek/Kconfig        |   16 +
+ drivers/thermal/mediatek/Makefile       |    1 +
+ drivers/thermal/mediatek/lvts_thermal.c | 1224 +++++++++++++++++++++++
+ 3 files changed, 1241 insertions(+)
+ create mode 100644 drivers/thermal/mediatek/lvts_thermal.c
+
+--- a/drivers/thermal/mediatek/Kconfig
++++ b/drivers/thermal/mediatek/Kconfig
+@@ -18,4 +18,20 @@ config MTK_SOC_THERMAL
+ 	  This driver configures thermal controllers to collect
+ 	  temperature via AUXADC interface.
+ 
++config MTK_LVTS_THERMAL
++        tristate "LVTS Thermal Driver for MediaTek SoCs"
++        depends on HAS_IOMEM
++        help
++          Enable this option if you want to get SoC temperature
++          information for supported MediaTek platforms.
++          This driver configures LVTS (Low Voltage Thermal Sensor)
++          thermal controllers to collect temperatures via ASIF
++          (Analog Serial Interface).
++
++config MTK_LVTS_THERMAL_DEBUGFS
++       bool "LVTS thermal debugfs"
++       depends on MTK_LVTS_THERMAL && DEBUG_FS
++       help
++         Enable this option to debug the internals of the device driver.
++
+ endif
+--- a/drivers/thermal/mediatek/Makefile
++++ b/drivers/thermal/mediatek/Makefile
+@@ -1 +1,2 @@
+ obj-$(CONFIG_MTK_SOC_THERMAL)	+= auxadc_thermal.o
++obj-$(CONFIG_MTK_LVTS_THERMAL)	+= lvts_thermal.o
+--- /dev/null
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -0,0 +1,1224 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * Copyright (c) 2023 MediaTek Inc.
++ * Author: Balsam CHIHI <bchihi@baylibre.com>
++ */
++
++#include <linux/clk.h>
++#include <linux/clk-provider.h>
++#include <linux/delay.h>
++#include <linux/debugfs.h>
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/iopoll.h>
++#include <linux/kernel.h>
++#include <linux/nvmem-consumer.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include <linux/reset.h>
++#include <linux/thermal.h>
++#include <dt-bindings/thermal/mediatek,lvts-thermal.h>
++
++#define LVTS_MONCTL0(__base)	(__base + 0x0000)
++#define LVTS_MONCTL1(__base)	(__base + 0x0004)
++#define LVTS_MONCTL2(__base)	(__base + 0x0008)
++#define LVTS_MONINT(__base)		(__base + 0x000C)
++#define LVTS_MONINTSTS(__base)	(__base + 0x0010)
++#define LVTS_MONIDET0(__base)	(__base + 0x0014)
++#define LVTS_MONIDET1(__base)	(__base + 0x0018)
++#define LVTS_MONIDET2(__base)	(__base + 0x001C)
++#define LVTS_MONIDET3(__base)	(__base + 0x0020)
++#define LVTS_H2NTHRE(__base)	(__base + 0x0024)
++#define LVTS_HTHRE(__base)		(__base + 0x0028)
++#define LVTS_OFFSETH(__base)	(__base + 0x0030)
++#define LVTS_OFFSETL(__base)	(__base + 0x0034)
++#define LVTS_MSRCTL0(__base)	(__base + 0x0038)
++#define LVTS_MSRCTL1(__base)	(__base + 0x003C)
++#define LVTS_TSSEL(__base)		(__base + 0x0040)
++#define LVTS_CALSCALE(__base)	(__base + 0x0048)
++#define LVTS_ID(__base)			(__base + 0x004C)
++#define LVTS_CONFIG(__base)		(__base + 0x0050)
++#define LVTS_EDATA00(__base)	(__base + 0x0054)
++#define LVTS_EDATA01(__base)	(__base + 0x0058)
++#define LVTS_EDATA02(__base)	(__base + 0x005C)
++#define LVTS_EDATA03(__base)	(__base + 0x0060)
++#define LVTS_MSR0(__base)		(__base + 0x0090)
++#define LVTS_MSR1(__base)		(__base + 0x0094)
++#define LVTS_MSR2(__base)		(__base + 0x0098)
++#define LVTS_MSR3(__base)		(__base + 0x009C)
++#define LVTS_IMMD0(__base)		(__base + 0x00A0)
++#define LVTS_IMMD1(__base)		(__base + 0x00A4)
++#define LVTS_IMMD2(__base)		(__base + 0x00A8)
++#define LVTS_IMMD3(__base)		(__base + 0x00AC)
++#define LVTS_PROTCTL(__base)	(__base + 0x00C0)
++#define LVTS_PROTTA(__base)		(__base + 0x00C4)
++#define LVTS_PROTTB(__base)		(__base + 0x00C8)
++#define LVTS_PROTTC(__base)		(__base + 0x00CC)
++#define LVTS_CLKEN(__base)		(__base + 0x00E4)
++
++#define LVTS_PERIOD_UNIT			((118 * 1000) / (256 * 38))
++#define LVTS_GROUP_INTERVAL			1
++#define LVTS_FILTER_INTERVAL		1
++#define LVTS_SENSOR_INTERVAL		1
++#define LVTS_HW_FILTER				0x2
++#define LVTS_TSSEL_CONF				0x13121110
++#define LVTS_CALSCALE_CONF			0x300
++#define LVTS_MONINT_CONF			0x9FBF7BDE
++
++#define LVTS_INT_SENSOR0			0x0009001F
++#define LVTS_INT_SENSOR1			0X000881F0
++#define LVTS_INT_SENSOR2			0x00247C00
++#define LVTS_INT_SENSOR3			0x1FC00000
++
++#define LVTS_SENSOR_MAX				4
++#define LVTS_GOLDEN_TEMP_MAX		62
++#define LVTS_GOLDEN_TEMP_DEFAULT	50
++#define LVTS_COEFF_A				-250460
++#define LVTS_COEFF_B				250460
++
++#define LVTS_MSR_IMMEDIATE_MODE		0
++#define LVTS_MSR_FILTERED_MODE		1
++
++#define LVTS_HW_SHUTDOWN_MT8195		105000
++
++static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT;
++static int coeff_b = LVTS_COEFF_B;
++
++struct lvts_sensor_data {
++	int dt_id;
++};
++
++struct lvts_ctrl_data {
++	struct lvts_sensor_data lvts_sensor[LVTS_SENSOR_MAX];
++	int cal_offset[LVTS_SENSOR_MAX];
++	int hw_tshut_temp;
++	int num_lvts_sensor;
++	int offset;
++	int mode;
++};
++
++struct lvts_data {
++	const struct lvts_ctrl_data *lvts_ctrl;
++	int num_lvts_ctrl;
++};
++
++struct lvts_sensor {
++	struct thermal_zone_device *tz;
++	void __iomem *msr;
++	void __iomem *base;
++	int id;
++	int dt_id;
++};
++
++struct lvts_ctrl {
++	struct lvts_sensor sensors[LVTS_SENSOR_MAX];
++	u32 calibration[LVTS_SENSOR_MAX];
++	u32 hw_tshut_raw_temp;
++	int num_lvts_sensor;
++	int mode;
++	void __iomem *base;
++};
++
++struct lvts_domain {
++	struct lvts_ctrl *lvts_ctrl;
++	struct reset_control *reset;
++	struct clk *clk;
++	int num_lvts_ctrl;
++	void __iomem *base;
++	size_t calib_len;
++	u8 *calib;
++#ifdef CONFIG_DEBUG_FS
++	struct dentry *dom_dentry;
++#endif
++};
++
++#ifdef CONFIG_MTK_LVTS_THERMAL_DEBUGFS
++
++#define LVTS_DEBUG_FS_REGS(__reg)		\
++{						\
++	.name = __stringify(__reg),		\
++	.offset = __reg(0),			\
++}
++
++static const struct debugfs_reg32 lvts_regs[] = {
++	LVTS_DEBUG_FS_REGS(LVTS_MONCTL0),
++	LVTS_DEBUG_FS_REGS(LVTS_MONCTL1),
++	LVTS_DEBUG_FS_REGS(LVTS_MONCTL2),
++	LVTS_DEBUG_FS_REGS(LVTS_MONINT),
++	LVTS_DEBUG_FS_REGS(LVTS_MONINTSTS),
++	LVTS_DEBUG_FS_REGS(LVTS_MONIDET0),
++	LVTS_DEBUG_FS_REGS(LVTS_MONIDET1),
++	LVTS_DEBUG_FS_REGS(LVTS_MONIDET2),
++	LVTS_DEBUG_FS_REGS(LVTS_MONIDET3),
++	LVTS_DEBUG_FS_REGS(LVTS_H2NTHRE),
++	LVTS_DEBUG_FS_REGS(LVTS_HTHRE),
++	LVTS_DEBUG_FS_REGS(LVTS_OFFSETH),
++	LVTS_DEBUG_FS_REGS(LVTS_OFFSETL),
++	LVTS_DEBUG_FS_REGS(LVTS_MSRCTL0),
++	LVTS_DEBUG_FS_REGS(LVTS_MSRCTL1),
++	LVTS_DEBUG_FS_REGS(LVTS_TSSEL),
++	LVTS_DEBUG_FS_REGS(LVTS_CALSCALE),
++	LVTS_DEBUG_FS_REGS(LVTS_ID),
++	LVTS_DEBUG_FS_REGS(LVTS_CONFIG),
++	LVTS_DEBUG_FS_REGS(LVTS_EDATA00),
++	LVTS_DEBUG_FS_REGS(LVTS_EDATA01),
++	LVTS_DEBUG_FS_REGS(LVTS_EDATA02),
++	LVTS_DEBUG_FS_REGS(LVTS_EDATA03),
++	LVTS_DEBUG_FS_REGS(LVTS_MSR0),
++	LVTS_DEBUG_FS_REGS(LVTS_MSR1),
++	LVTS_DEBUG_FS_REGS(LVTS_MSR2),
++	LVTS_DEBUG_FS_REGS(LVTS_MSR3),
++	LVTS_DEBUG_FS_REGS(LVTS_IMMD0),
++	LVTS_DEBUG_FS_REGS(LVTS_IMMD1),
++	LVTS_DEBUG_FS_REGS(LVTS_IMMD2),
++	LVTS_DEBUG_FS_REGS(LVTS_IMMD3),
++	LVTS_DEBUG_FS_REGS(LVTS_PROTCTL),
++	LVTS_DEBUG_FS_REGS(LVTS_PROTTA),
++	LVTS_DEBUG_FS_REGS(LVTS_PROTTB),
++	LVTS_DEBUG_FS_REGS(LVTS_PROTTC),
++	LVTS_DEBUG_FS_REGS(LVTS_CLKEN),
++};
++
++static int lvts_debugfs_init(struct device *dev, struct lvts_domain *lvts_td)
++{
++	struct debugfs_regset32 *regset;
++	struct lvts_ctrl *lvts_ctrl;
++	struct dentry *dentry;
++	char name[64];
++	int i;
++
++	lvts_td->dom_dentry = debugfs_create_dir(dev_name(dev), NULL);
++	if (!lvts_td->dom_dentry)
++		return 0;
++
++	for (i = 0; i < lvts_td->num_lvts_ctrl; i++) {
++
++		lvts_ctrl = &lvts_td->lvts_ctrl[i];
++
++		sprintf(name, "controller%d", i);
++		dentry = debugfs_create_dir(name, lvts_td->dom_dentry);
++		if (!dentry)
++			continue;
++
++		regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL);
++		if (!regset)
++			continue;
++
++		regset->base = lvts_ctrl->base;
++		regset->regs = lvts_regs;
++		regset->nregs = ARRAY_SIZE(lvts_regs);
++
++		debugfs_create_regset32("registers", 0400, dentry, regset);
++	}
++
++	return 0;
++}
++
++static void lvts_debugfs_exit(struct lvts_domain *lvts_td)
++{
++	debugfs_remove_recursive(lvts_td->dom_dentry);
++}
++
++#else
++
++static inline int lvts_debugfs_init(struct device *dev,
++				    struct lvts_domain *lvts_td)
++{
++	return 0;
++}
++
++static void lvts_debugfs_exit(struct lvts_domain *lvts_td) { }
++
++#endif
++
++static int lvts_raw_to_temp(u32 raw_temp)
++{
++	int temperature;
++
++	temperature = ((s64)(raw_temp & 0xFFFF) * LVTS_COEFF_A) >> 14;
++	temperature += coeff_b;
++
++	return temperature;
++}
++
++static u32 lvts_temp_to_raw(int temperature)
++{
++	u32 raw_temp = ((s64)(coeff_b - temperature)) << 14;
++
++	raw_temp = div_s64(raw_temp, -LVTS_COEFF_A);
++
++	return raw_temp;
++}
++
++static int lvts_get_temp(struct thermal_zone_device *tz, int *temp)
++{
++	struct lvts_sensor *lvts_sensor = tz->devdata;
++	void __iomem *msr = lvts_sensor->msr;
++	u32 value;
++
++	/*
++	 * Measurement registers:
++	 *
++	 * LVTS_MSR[0-3] / LVTS_IMMD[0-3]
++	 *
++	 * Bits:
++	 *
++	 * 32-17: Unused
++	 * 16	: Valid temperature
++	 * 15-0	: Raw temperature
++	 */
++	value = readl(msr);
++
++	/*
++	 * As the thermal zone temperature will read before the
++	 * hardware sensor is fully initialized, we have to check the
++	 * validity of the temperature returned when reading the
++	 * measurement register. The thermal controller will set the
++	 * valid bit temperature only when it is totally initialized.
++	 *
++	 * Otherwise, we may end up with garbage values out of the
++	 * functionning temperature and directly jump to a system
++	 * shutdown.
++	 */
++	if (!(value & BIT(16)))
++		return -EAGAIN;
++
++	*temp = lvts_raw_to_temp(value & 0xFFFF);
++
++	return 0;
++}
++
++static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high)
++{
++	struct lvts_sensor *lvts_sensor = tz->devdata;
++	void __iomem *base = lvts_sensor->base;
++	u32 raw_low = lvts_temp_to_raw(low);
++	u32 raw_high = lvts_temp_to_raw(high);
++
++	/*
++	 * Hot to normal temperature threshold
++	 *
++	 * LVTS_H2NTHRE
++	 *
++	 * Bits:
++	 *
++	 * 14-0 : Raw temperature for threshold
++	 */
++	if (low != -INT_MAX) {
++		dev_dbg(&tz->device, "Setting low limit temperature interrupt: %d\n", low);
++		writel(raw_low, LVTS_H2NTHRE(base));
++	}
++
++	/*
++	 * Hot temperature threshold
++	 *
++	 * LVTS_HTHRE
++	 *
++	 * Bits:
++	 *
++	 * 14-0 : Raw temperature for threshold
++	 */
++	dev_dbg(&tz->device, "Setting high limit temperature interrupt: %d\n", high);
++	writel(raw_high, LVTS_HTHRE(base));
++
++	return 0;
++}
++
++static irqreturn_t lvts_ctrl_irq_handler(struct lvts_ctrl *lvts_ctrl)
++{
++	irqreturn_t iret = IRQ_NONE;
++	u32 value;
++	u32 masks[] = {
++		LVTS_INT_SENSOR0,
++		LVTS_INT_SENSOR1,
++		LVTS_INT_SENSOR2,
++		LVTS_INT_SENSOR3
++	};
++	int i;
++
++	/*
++	 * Interrupt monitoring status
++	 *
++	 * LVTS_MONINTST
++	 *
++	 * Bits:
++	 *
++	 * 31 : Interrupt for stage 3
++	 * 30 : Interrupt for stage 2
++	 * 29 : Interrupt for state 1
++	 * 28 : Interrupt using filter on sensor 3
++	 *
++	 * 27 : Interrupt using immediate on sensor 3
++	 * 26 : Interrupt normal to hot on sensor 3
++	 * 25 : Interrupt high offset on sensor 3
++	 * 24 : Interrupt low offset on sensor 3
++	 *
++	 * 23 : Interrupt hot threshold on sensor 3
++	 * 22 : Interrupt cold threshold on sensor 3
++	 * 21 : Interrupt using filter on sensor 2
++	 * 20 : Interrupt using filter on sensor 1
++	 *
++	 * 19 : Interrupt using filter on sensor 0
++	 * 18 : Interrupt using immediate on sensor 2
++	 * 17 : Interrupt using immediate on sensor 1
++	 * 16 : Interrupt using immediate on sensor 0
++	 *
++	 * 15 : Interrupt device access timeout interrupt
++	 * 14 : Interrupt normal to hot on sensor 2
++	 * 13 : Interrupt high offset interrupt on sensor 2
++	 * 12 : Interrupt low offset interrupt on sensor 2
++	 *
++	 * 11 : Interrupt hot threshold on sensor 2
++	 * 10 : Interrupt cold threshold on sensor 2
++	 *  9 : Interrupt normal to hot on sensor 1
++	 *  8 : Interrupt high offset interrupt on sensor 1
++	 *
++	 *  7 : Interrupt low offset interrupt on sensor 1
++	 *  6 : Interrupt hot threshold on sensor 1
++	 *  5 : Interrupt cold threshold on sensor 1
++	 *  4 : Interrupt normal to hot on sensor 0
++	 *
++	 *  3 : Interrupt high offset interrupt on sensor 0
++	 *  2 : Interrupt low offset interrupt on sensor 0
++	 *  1 : Interrupt hot threshold on sensor 0
++	 *  0 : Interrupt cold threshold on sensor 0
++	 *
++	 * We are interested in the sensor(s) responsible of the
++	 * interrupt event. We update the thermal framework with the
++	 * thermal zone associated with the sensor. The framework will
++	 * take care of the rest whatever the kind of interrupt, we
++	 * are only interested in which sensor raised the interrupt.
++	 *
++	 * sensor 3 interrupt: 0001 1111 1100 0000 0000 0000 0000 0000
++	 *                  => 0x1FC00000
++	 * sensor 2 interrupt: 0000 0000 0010 0100 0111 1100 0000 0000
++	 *                  => 0x00247C00
++	 * sensor 1 interrupt: 0000 0000 0001 0001 0000 0011 1110 0000
++	 *                  => 0X000881F0
++	 * sensor 0 interrupt: 0000 0000 0000 1001 0000 0000 0001 1111
++	 *                  => 0x0009001F
++	 */
++	value = readl(LVTS_MONINTSTS(lvts_ctrl->base));
++
++	/*
++	 * Let's figure out which sensors raised the interrupt
++	 *
++	 * NOTE: the masks array must be ordered with the index
++	 * corresponding to the sensor id eg. index=0, mask for
++	 * sensor0.
++	 */
++	for (i = 0; i < ARRAY_SIZE(masks); i++) {
++
++		if (!(value & masks[i]))
++			continue;
++
++		thermal_zone_device_update(lvts_ctrl->sensors[i].tz,
++					   THERMAL_TRIP_VIOLATED);
++		iret = IRQ_HANDLED;
++	}
++
++	/*
++	 * Write back to clear the interrupt status (W1C)
++	 */
++	writel(value, LVTS_MONINTSTS(lvts_ctrl->base));
++
++	return iret;
++}
++
++/*
++ * Temperature interrupt handler. Even if the driver supports more
++ * interrupt modes, we use the interrupt when the temperature crosses
++ * the hot threshold the way up and the way down (modulo the
++ * hysteresis).
++ *
++ * Each thermal domain has a couple of interrupts, one for hardware
++ * reset and another one for all the thermal events happening on the
++ * different sensors.
++ *
++ * The interrupt is configured for thermal events when crossing the
++ * hot temperature limit. At each interrupt, we check in every
++ * controller if there is an interrupt pending.
++ */
++static irqreturn_t lvts_irq_handler(int irq, void *data)
++{
++	struct lvts_domain *lvts_td = data;
++	irqreturn_t aux, iret = IRQ_NONE;
++	int i;
++
++	for (i = 0; i < lvts_td->num_lvts_ctrl; i++) {
++
++		aux = lvts_ctrl_irq_handler(lvts_td->lvts_ctrl);
++		if (aux != IRQ_HANDLED)
++			continue;
++
++		iret = IRQ_HANDLED;
++	}
++
++	return iret;
++}
++
++static struct thermal_zone_device_ops lvts_ops = {
++	.get_temp = lvts_get_temp,
++	.set_trips = lvts_set_trips,
++};
++
++static int lvts_sensor_init(struct device *dev, struct lvts_ctrl *lvts_ctrl,
++					const struct lvts_ctrl_data *lvts_ctrl_data)
++{
++	struct lvts_sensor *lvts_sensor = lvts_ctrl->sensors;
++	void __iomem *msr_regs[] = {
++		LVTS_MSR0(lvts_ctrl->base),
++		LVTS_MSR1(lvts_ctrl->base),
++		LVTS_MSR2(lvts_ctrl->base),
++		LVTS_MSR3(lvts_ctrl->base)
++	};
++
++	void __iomem *imm_regs[] = {
++		LVTS_IMMD0(lvts_ctrl->base),
++		LVTS_IMMD1(lvts_ctrl->base),
++		LVTS_IMMD2(lvts_ctrl->base),
++		LVTS_IMMD3(lvts_ctrl->base)
++	};
++
++	int i;
++
++	for (i = 0; i < lvts_ctrl_data->num_lvts_sensor; i++) {
++
++		int dt_id = lvts_ctrl_data->lvts_sensor[i].dt_id;
++
++		/*
++		 * At this point, we don't know which id matches which
++		 * sensor. Let's set arbitrally the id from the index.
++		 */
++		lvts_sensor[i].id = i;
++
++		/*
++		 * The thermal zone registration will set the trip
++		 * point interrupt in the thermal controller
++		 * register. But this one will be reset in the
++		 * initialization after. So we need to post pone the
++		 * thermal zone creation after the controller is
++		 * setup. For this reason, we store the device tree
++		 * node id from the data in the sensor structure
++		 */
++		lvts_sensor[i].dt_id = dt_id;
++
++		/*
++		 * We assign the base address of the thermal
++		 * controller as a back pointer. So it will be
++		 * accessible from the different thermal framework ops
++		 * as we pass the lvts_sensor pointer as thermal zone
++		 * private data.
++		 */
++		lvts_sensor[i].base = lvts_ctrl->base;
++
++		/*
++		 * Each sensor has its own register address to read from.
++		 */
++		lvts_sensor[i].msr = lvts_ctrl_data->mode == LVTS_MSR_IMMEDIATE_MODE ?
++			imm_regs[i] : msr_regs[i];
++	};
++
++	lvts_ctrl->num_lvts_sensor = lvts_ctrl_data->num_lvts_sensor;
++
++	return 0;
++}
++
++/*
++ * The efuse blob values follows the sensor enumeration per thermal
++ * controller. The decoding of the stream is as follow:
++ *
++ *                        <--?-> <----big0 ???---> <-sensor0-> <-0->
++ *                        ------------------------------------------
++ * index in the stream: : | 0x0 | 0x1 | 0x2 | 0x3 | 0x4 | 0x5 | 0x6 |
++ *                        ------------------------------------------
++ *
++ *                        <--sensor1--><-0-> <----big1 ???---> <-sen
++ *                        ------------------------------------------
++ *                        | 0x7 | 0x8 | 0x9 | 0xA | 0xB | OxC | OxD |
++ *                        ------------------------------------------
++ *
++ *                        sor0-> <-0-> <-sensor1-> <-0-> ..........
++ *                        ------------------------------------------
++ *                        | 0x7 | 0x8 | 0x9 | 0xA | 0xB | OxC | OxD |
++ *                        ------------------------------------------
++ *
++ * And so on ...
++ *
++ * The data description gives the offset of the calibration data in
++ * this bytes stream for each sensor.
++ *
++ * Each thermal controller can handle up to 4 sensors max, we don't
++ * care if there are less as the array of calibration is sized to 4
++ * anyway. The unused sensor slot will be zeroed.
++ */
++static int lvts_calibration_init(struct device *dev, struct lvts_ctrl *lvts_ctrl,
++					const struct lvts_ctrl_data *lvts_ctrl_data,
++					u8 *efuse_calibration)
++{
++	int i;
++
++	for (i = 0; i < lvts_ctrl_data->num_lvts_sensor; i++)
++		memcpy(&lvts_ctrl->calibration[i],
++		       efuse_calibration + lvts_ctrl_data->cal_offset[i], 2);
++
++	return 0;
++}
++
++/*
++ * The efuse bytes stream can be split into different chunk of
++ * nvmems. This function reads and concatenate those into a single
++ * buffer so it can be read sequentially when initializing the
++ * calibration data.
++ */
++static int lvts_calibration_read(struct device *dev, struct lvts_domain *lvts_td,
++					const struct lvts_data *lvts_data)
++{
++	struct device_node *np = dev_of_node(dev);
++	struct nvmem_cell *cell;
++	struct property *prop;
++	const char *cell_name;
++
++	of_property_for_each_string(np, "nvmem-cell-names", prop, cell_name) {
++		size_t len;
++		u8 *efuse;
++
++		cell = of_nvmem_cell_get(np, cell_name);
++		if (IS_ERR(cell)) {
++			dev_err(dev, "Failed to get cell '%s'\n", cell_name);
++			return PTR_ERR(cell);
++		}
++
++		efuse = nvmem_cell_read(cell, &len);
++
++		nvmem_cell_put(cell);
++
++		if (IS_ERR(efuse)) {
++			dev_err(dev, "Failed to read cell '%s'\n", cell_name);
++			return PTR_ERR(efuse);
++		}
++
++		lvts_td->calib = devm_krealloc(dev, lvts_td->calib,
++					       lvts_td->calib_len + len, GFP_KERNEL);
++		if (!lvts_td->calib)
++			return -ENOMEM;
++
++		memcpy(lvts_td->calib + lvts_td->calib_len, efuse, len);
++
++		lvts_td->calib_len += len;
++
++		kfree(efuse);
++	}
++
++	return 0;
++}
++
++static int lvts_golden_temp_init(struct device *dev, u32 *value)
++{
++	u32 gt;
++
++	gt = (*value) >> 24;
++
++	if (gt && gt < LVTS_GOLDEN_TEMP_MAX)
++		golden_temp = gt;
++
++	coeff_b = golden_temp * 500 + LVTS_COEFF_B;
++
++	return 0;
++}
++
++static int lvts_ctrl_init(struct device *dev, struct lvts_domain *lvts_td,
++					const struct lvts_data *lvts_data)
++{
++	size_t size = sizeof(*lvts_td->lvts_ctrl) * lvts_data->num_lvts_ctrl;
++	struct lvts_ctrl *lvts_ctrl;
++	int i, ret;
++
++	/*
++	 * Create the calibration bytes stream from efuse data
++	 */
++	ret = lvts_calibration_read(dev, lvts_td, lvts_data);
++	if (ret)
++		return ret;
++
++	/*
++	 * The golden temp information is contained in the first chunk
++	 * of efuse data.
++	 */
++	ret = lvts_golden_temp_init(dev, (u32 *)lvts_td->calib);
++	if (ret)
++		return ret;
++
++	lvts_ctrl = devm_kzalloc(dev, size, GFP_KERNEL);
++	if (!lvts_ctrl)
++		return -ENOMEM;
++
++	for (i = 0; i < lvts_data->num_lvts_ctrl; i++) {
++
++		lvts_ctrl[i].base = lvts_td->base + lvts_data->lvts_ctrl[i].offset;
++
++		ret = lvts_sensor_init(dev, &lvts_ctrl[i],
++				       &lvts_data->lvts_ctrl[i]);
++		if (ret)
++			return ret;
++
++		ret = lvts_calibration_init(dev, &lvts_ctrl[i],
++					    &lvts_data->lvts_ctrl[i],
++					    lvts_td->calib);
++		if (ret)
++			return ret;
++
++		/*
++		 * The mode the ctrl will use to read the temperature
++		 * (filtered or immediate)
++		 */
++		lvts_ctrl[i].mode = lvts_data->lvts_ctrl[i].mode;
++
++		/*
++		 * The temperature to raw temperature must be done
++		 * after initializing the calibration.
++		 */
++		lvts_ctrl[i].hw_tshut_raw_temp =
++			lvts_temp_to_raw(lvts_data->lvts_ctrl[i].hw_tshut_temp);
++	}
++
++	/*
++	 * We no longer need the efuse bytes stream, let's free it
++	 */
++	devm_kfree(dev, lvts_td->calib);
++
++	lvts_td->lvts_ctrl = lvts_ctrl;
++	lvts_td->num_lvts_ctrl = lvts_data->num_lvts_ctrl;
++
++	return 0;
++}
++
++/*
++ * At this point the configuration register is the only place in the
++ * driver where we write multiple values. Per hardware constraint,
++ * each write in the configuration register must be separated by a
++ * delay of 2 us.
++ */
++static void lvts_write_config(struct lvts_ctrl *lvts_ctrl, u32 *cmds, int nr_cmds)
++{
++	int i;
++
++	/*
++	 * Configuration register
++	 */
++	for (i = 0; i < nr_cmds; i++) {
++		writel(cmds[i], LVTS_CONFIG(lvts_ctrl->base));
++		usleep_range(2, 4);
++	}
++}
++
++static int lvts_irq_init(struct lvts_ctrl *lvts_ctrl)
++{
++	/*
++	 * LVTS_PROTCTL : Thermal Protection Sensor Selection
++	 *
++	 * Bits:
++	 *
++	 * 19-18 : Sensor to base the protection on
++	 * 17-16 : Strategy:
++	 *         00 : Average of 4 sensors
++	 *         01 : Max of 4 sensors
++	 *         10 : Selected sensor with bits 19-18
++	 *         11 : Reserved
++	 */
++	writel(BIT(16), LVTS_PROTCTL(lvts_ctrl->base));
++
++	/*
++	 * LVTS_PROTTA : Stage 1 temperature threshold
++	 * LVTS_PROTTB : Stage 2 temperature threshold
++	 * LVTS_PROTTC : Stage 3 temperature threshold
++	 *
++	 * Bits:
++	 *
++	 * 14-0: Raw temperature threshold
++	 *
++	 * writel(0x0, LVTS_PROTTA(lvts_ctrl->base));
++	 * writel(0x0, LVTS_PROTTB(lvts_ctrl->base));
++	 */
++	writel(lvts_ctrl->hw_tshut_raw_temp, LVTS_PROTTC(lvts_ctrl->base));
++
++	/*
++	 * LVTS_MONINT : Interrupt configuration register
++	 *
++	 * The LVTS_MONINT register layout is the same as the LVTS_MONINTSTS
++	 * register, except we set the bits to enable the interrupt.
++	 */
++	writel(LVTS_MONINT_CONF, LVTS_MONINT(lvts_ctrl->base));
++
++	return 0;
++}
++
++static int lvts_domain_reset(struct device *dev, struct reset_control *reset)
++{
++	int ret;
++
++	ret = reset_control_assert(reset);
++	if (ret)
++		return ret;
++
++	return reset_control_deassert(reset);
++}
++
++/*
++ * Enable or disable the clocks of a specified thermal controller
++ */
++static int lvts_ctrl_set_enable(struct lvts_ctrl *lvts_ctrl, int enable)
++{
++	/*
++	 * LVTS_CLKEN : Internal LVTS clock
++	 *
++	 * Bits:
++	 *
++	 * 0 : enable / disable clock
++	 */
++	writel(enable, LVTS_CLKEN(lvts_ctrl->base));
++
++	return 0;
++}
++
++static int lvts_ctrl_connect(struct device *dev, struct lvts_ctrl *lvts_ctrl)
++{
++	u32 id, cmds[] = { 0xC103FFFF, 0xC502FF55 };
++
++	lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds));
++
++	/*
++	 * LVTS_ID : Get ID and status of the thermal controller
++	 *
++	 * Bits:
++	 *
++	 * 0-5	: thermal controller id
++	 *   7	: thermal controller connection is valid
++	 */
++	id = readl(LVTS_ID(lvts_ctrl->base));
++	if (!(id & BIT(7)))
++		return -EIO;
++
++	return 0;
++}
++
++static int lvts_ctrl_initialize(struct device *dev, struct lvts_ctrl *lvts_ctrl)
++{
++	/*
++	 * Write device mask: 0xC1030000
++	 */
++	u32 cmds[] = {
++		0xC1030E01, 0xC1030CFC, 0xC1030A8C, 0xC103098D, 0xC10308F1,
++		0xC10307A6, 0xC10306B8, 0xC1030500, 0xC1030420, 0xC1030300,
++		0xC1030030, 0xC10300F6, 0xC1030050, 0xC1030060, 0xC10300AC,
++		0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1
++	};
++
++	lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds));
++
++	return 0;
++}
++
++static int lvts_ctrl_calibrate(struct device *dev, struct lvts_ctrl *lvts_ctrl)
++{
++	int i;
++	void __iomem *lvts_edata[] = {
++		LVTS_EDATA00(lvts_ctrl->base),
++		LVTS_EDATA01(lvts_ctrl->base),
++		LVTS_EDATA02(lvts_ctrl->base),
++		LVTS_EDATA03(lvts_ctrl->base)
++	};
++
++	/*
++	 * LVTS_EDATA0X : Efuse calibration reference value for sensor X
++	 *
++	 * Bits:
++	 *
++	 * 20-0 : Efuse value for normalization data
++	 */
++	for (i = 0; i < LVTS_SENSOR_MAX; i++)
++		writel(lvts_ctrl->calibration[i], lvts_edata[i]);
++
++	return 0;
++}
++
++static int lvts_ctrl_configure(struct device *dev, struct lvts_ctrl *lvts_ctrl)
++{
++	u32 value;
++
++	/*
++	 * LVTS_TSSEL : Sensing point index numbering
++	 *
++	 * Bits:
++	 *
++	 * 31-24: ADC Sense 3
++	 * 23-16: ADC Sense 2
++	 * 15-8	: ADC Sense 1
++	 * 7-0	: ADC Sense 0
++	 */
++	value = LVTS_TSSEL_CONF;
++	writel(value, LVTS_TSSEL(lvts_ctrl->base));
++
++	/*
++	 * LVTS_CALSCALE : ADC voltage round
++	 */
++	value = 0x300;
++	value = LVTS_CALSCALE_CONF;
++
++	/*
++	 * LVTS_MSRCTL0 : Sensor filtering strategy
++	 *
++	 * Filters:
++	 *
++	 * 000 : One sample
++	 * 001 : Avg 2 samples
++	 * 010 : 4 samples, drop min and max, avg 2 samples
++	 * 011 : 6 samples, drop min and max, avg 4 samples
++	 * 100 : 10 samples, drop min and max, avg 8 samples
++	 * 101 : 18 samples, drop min and max, avg 16 samples
++	 *
++	 * Bits:
++	 *
++	 * 0-2  : Sensor0 filter
++	 * 3-5  : Sensor1 filter
++	 * 6-8  : Sensor2 filter
++	 * 9-11 : Sensor3 filter
++	 */
++	value = LVTS_HW_FILTER << 9 |  LVTS_HW_FILTER << 6 |
++			LVTS_HW_FILTER << 3 | LVTS_HW_FILTER;
++	writel(value, LVTS_MSRCTL0(lvts_ctrl->base));
++
++	/*
++	 * LVTS_MSRCTL1 : Measurement control
++	 *
++	 * Bits:
++	 *
++	 * 9: Ignore MSRCTL0 config and do immediate measurement on sensor3
++	 * 6: Ignore MSRCTL0 config and do immediate measurement on sensor2
++	 * 5: Ignore MSRCTL0 config and do immediate measurement on sensor1
++	 * 4: Ignore MSRCTL0 config and do immediate measurement on sensor0
++	 *
++	 * That configuration will ignore the filtering and the delays
++	 * introduced below in MONCTL1 and MONCTL2
++	 */
++	if (lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE) {
++		value = BIT(9) | BIT(6) | BIT(5) | BIT(4);
++		writel(value, LVTS_MSRCTL1(lvts_ctrl->base));
++	}
++
++	/*
++	 * LVTS_MONCTL1 : Period unit and group interval configuration
++	 *
++	 * The clock source of LVTS thermal controller is 26MHz.
++	 *
++	 * The period unit is a time base for all the interval delays
++	 * specified in the registers. By default we use 12. The time
++	 * conversion is done by multiplying by 256 and 1/26.10^6
++	 *
++	 * An interval delay multiplied by the period unit gives the
++	 * duration in seconds.
++	 *
++	 * - Filter interval delay is a delay between two samples of
++	 * the same sensor.
++	 *
++	 * - Sensor interval delay is a delay between two samples of
++	 * different sensors.
++	 *
++	 * - Group interval delay is a delay between different rounds.
++	 *
++	 * For example:
++	 *     If Period unit = C, filter delay = 1, sensor delay = 2, group delay = 1,
++	 *     and two sensors, TS1 and TS2, are in a LVTS thermal controller
++	 *     and then
++	 *     Period unit time = C * 1/26M * 256 = 12 * 38.46ns * 256 = 118.149us
++	 *     Filter interval delay = 1 * Period unit = 118.149us
++	 *     Sensor interval delay = 2 * Period unit = 236.298us
++	 *     Group interval delay = 1 * Period unit = 118.149us
++	 *
++	 *     TS1    TS1 ... TS1    TS2    TS2 ... TS2    TS1...
++	 *        <--> Filter interval delay
++	 *                       <--> Sensor interval delay
++	 *                                             <--> Group interval delay
++	 * Bits:
++	 *      29 - 20 : Group interval
++	 *      16 - 13 : Send a single interrupt when crossing the hot threshold (1)
++	 *                or an interrupt everytime the hot threshold is crossed (0)
++	 *       9 - 0  : Period unit
++	 *
++	 */
++	value = LVTS_GROUP_INTERVAL << 20 | LVTS_PERIOD_UNIT;
++	writel(value, LVTS_MONCTL1(lvts_ctrl->base));
++
++	/*
++	 * LVTS_MONCTL2 : Filtering and sensor interval
++	 *
++	 * Bits:
++	 *
++	 *      25-16 : Interval unit in PERIOD_UNIT between sample on
++	 *              the same sensor, filter interval
++	 *       9-0  : Interval unit in PERIOD_UNIT between each sensor
++	 *
++	 */
++	value = LVTS_FILTER_INTERVAL << 16 | LVTS_SENSOR_INTERVAL;
++	writel(value, LVTS_MONCTL2(lvts_ctrl->base));
++
++	return lvts_irq_init(lvts_ctrl);
++}
++
++static int lvts_ctrl_start(struct device *dev, struct lvts_ctrl *lvts_ctrl)
++{
++	struct lvts_sensor *lvts_sensors = lvts_ctrl->sensors;
++	struct thermal_zone_device *tz;
++	u32 sensor_map = 0;
++	int i;
++
++	for (i = 0; i < lvts_ctrl->num_lvts_sensor; i++) {
++
++		int dt_id = lvts_sensors[i].dt_id;
++
++		tz = devm_thermal_of_zone_register(dev, dt_id, &lvts_sensors[i],
++						   &lvts_ops);
++		if (IS_ERR(tz)) {
++			/*
++			 * This thermal zone is not described in the
++			 * device tree. It is not an error from the
++			 * thermal OF code POV, we just continue.
++			 */
++			if (PTR_ERR(tz) == -ENODEV)
++				continue;
++
++			return PTR_ERR(tz);
++		}
++
++		/*
++		 * The thermal zone pointer will be needed in the
++		 * interrupt handler, we store it in the sensor
++		 * structure. The thermal domain structure will be
++		 * passed to the interrupt handler private data as the
++		 * interrupt is shared for all the controller
++		 * belonging to the thermal domain.
++		 */
++		lvts_sensors[i].tz = tz;
++
++		/*
++		 * This sensor was correctly associated with a thermal
++		 * zone, let's set the corresponding bit in the sensor
++		 * map, so we can enable the temperature monitoring in
++		 * the hardware thermal controller.
++		 */
++		sensor_map |= BIT(i);
++	}
++
++	/*
++	 * Bits:
++	 *      9: Single point access flow
++	 *    0-3: Enable sensing point 0-3
++	 *
++	 * The initialization of the thermal zones give us
++	 * which sensor point to enable. If any thermal zone
++	 * was not described in the device tree, it won't be
++	 * enabled here in the sensor map.
++	 */
++	writel(sensor_map | BIT(9), LVTS_MONCTL0(lvts_ctrl->base));
++
++	return 0;
++}
++
++static int lvts_domain_init(struct device *dev, struct lvts_domain *lvts_td,
++					const struct lvts_data *lvts_data)
++{
++	struct lvts_ctrl *lvts_ctrl;
++	int i, ret;
++
++	ret = lvts_ctrl_init(dev, lvts_td, lvts_data);
++	if (ret)
++		return ret;
++
++	ret = lvts_domain_reset(dev, lvts_td->reset);
++	if (ret) {
++		dev_dbg(dev, "Failed to reset domain");
++		return ret;
++	}
++
++	for (i = 0; i < lvts_td->num_lvts_ctrl; i++) {
++
++		lvts_ctrl = &lvts_td->lvts_ctrl[i];
++
++		/*
++		 * Initialization steps:
++		 *
++		 * - Enable the clock
++		 * - Connect to the LVTS
++		 * - Initialize the LVTS
++		 * - Prepare the calibration data
++		 * - Select monitored sensors
++		 * [ Configure sampling ]
++		 * [ Configure the interrupt ]
++		 * - Start measurement
++		 */
++		ret = lvts_ctrl_set_enable(lvts_ctrl, true);
++		if (ret) {
++			dev_dbg(dev, "Failed to enable LVTS clock");
++			return ret;
++		}
++
++		ret = lvts_ctrl_connect(dev, lvts_ctrl);
++		if (ret) {
++			dev_dbg(dev, "Failed to connect to LVTS controller");
++			return ret;
++		}
++
++		ret = lvts_ctrl_initialize(dev, lvts_ctrl);
++		if (ret) {
++			dev_dbg(dev, "Failed to initialize controller");
++			return ret;
++		}
++
++		ret = lvts_ctrl_calibrate(dev, lvts_ctrl);
++		if (ret) {
++			dev_dbg(dev, "Failed to calibrate controller");
++			return ret;
++		}
++
++		ret = lvts_ctrl_configure(dev, lvts_ctrl);
++		if (ret) {
++			dev_dbg(dev, "Failed to configure controller");
++			return ret;
++		}
++
++		ret = lvts_ctrl_start(dev, lvts_ctrl);
++		if (ret) {
++			dev_dbg(dev, "Failed to start controller");
++			return ret;
++		}
++	}
++
++	return lvts_debugfs_init(dev, lvts_td);
++}
++
++static int lvts_probe(struct platform_device *pdev)
++{
++	const struct lvts_data *lvts_data;
++	struct lvts_domain *lvts_td;
++	struct device *dev = &pdev->dev;
++	struct resource *res;
++	int irq, ret;
++
++	lvts_td = devm_kzalloc(dev, sizeof(*lvts_td), GFP_KERNEL);
++	if (!lvts_td)
++		return -ENOMEM;
++
++	lvts_data = of_device_get_match_data(dev);
++
++	lvts_td->clk = devm_clk_get_enabled(dev, NULL);
++	if (IS_ERR(lvts_td->clk))
++		return dev_err_probe(dev, PTR_ERR(lvts_td->clk), "Failed to retrieve clock\n");
++
++	res = platform_get_mem_or_io(pdev, 0);
++	if (!res)
++		return dev_err_probe(dev, (-ENXIO), "No IO resource\n");
++
++	lvts_td->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
++	if (IS_ERR(lvts_td->base))
++		return dev_err_probe(dev, PTR_ERR(lvts_td->base), "Failed to map io resource\n");
++
++	lvts_td->reset = devm_reset_control_get_by_index(dev, 0);
++	if (IS_ERR(lvts_td->reset))
++		return dev_err_probe(dev, PTR_ERR(lvts_td->reset), "Failed to get reset control\n");
++
++	irq = platform_get_irq(pdev, 0);
++	if (irq < 0)
++		return dev_err_probe(dev, irq, "No irq resource\n");
++
++	ret = lvts_domain_init(dev, lvts_td, lvts_data);
++	if (ret)
++		return dev_err_probe(dev, ret, "Failed to initialize the lvts domain\n");
++
++	/*
++	 * At this point the LVTS is initialized and enabled. We can
++	 * safely enable the interrupt.
++	 */
++	ret = devm_request_threaded_irq(dev, irq, NULL, lvts_irq_handler,
++					IRQF_ONESHOT, dev_name(dev), lvts_td);
++	if (ret)
++		return dev_err_probe(dev, ret, "Failed to request interrupt\n");
++
++	platform_set_drvdata(pdev, lvts_td);
++
++	return 0;
++}
++
++static int lvts_remove(struct platform_device *pdev)
++{
++	struct lvts_domain *lvts_td;
++	int i;
++
++	lvts_td = platform_get_drvdata(pdev);
++
++	for (i = 0; i < lvts_td->num_lvts_ctrl; i++)
++		lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false);
++
++	lvts_debugfs_exit(lvts_td);
++
++	return 0;
++}
++
++static const struct lvts_ctrl_data mt8195_lvts_data_ctrl[] = {
++	{
++		.cal_offset = { 0x04, 0x07 },
++		.lvts_sensor = {
++			{ .dt_id = MT8195_MCU_BIG_CPU0 },
++			{ .dt_id = MT8195_MCU_BIG_CPU1 }
++		},
++		.num_lvts_sensor = 2,
++		.offset = 0x0,
++		.hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
++	},
++	{
++		.cal_offset = { 0x0d, 0x10 },
++		.lvts_sensor = {
++			{ .dt_id = MT8195_MCU_BIG_CPU2 },
++			{ .dt_id = MT8195_MCU_BIG_CPU3 }
++		},
++		.num_lvts_sensor = 2,
++		.offset = 0x100,
++		.hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
++	},
++	{
++		.cal_offset = { 0x16, 0x19, 0x1c, 0x1f },
++		.lvts_sensor = {
++			{ .dt_id = MT8195_MCU_LITTLE_CPU0 },
++			{ .dt_id = MT8195_MCU_LITTLE_CPU1 },
++			{ .dt_id = MT8195_MCU_LITTLE_CPU2 },
++			{ .dt_id = MT8195_MCU_LITTLE_CPU3 }
++		},
++		.num_lvts_sensor = 4,
++		.offset = 0x200,
++		.hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
++	}
++};
++
++static const struct lvts_data mt8195_lvts_mcu_data = {
++	.lvts_ctrl	= mt8195_lvts_data_ctrl,
++	.num_lvts_ctrl	= ARRAY_SIZE(mt8195_lvts_data_ctrl),
++};
++
++static const struct of_device_id lvts_of_match[] = {
++	{ .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data },
++	{},
++};
++MODULE_DEVICE_TABLE(of, lvts_of_match);
++
++static struct platform_driver lvts_driver = {
++	.probe = lvts_probe,
++	.remove = lvts_remove,
++	.driver = {
++		.name = "mtk-lvts-thermal",
++		.of_match_table = lvts_of_match,
++	},
++};
++module_platform_driver(lvts_driver);
++
++MODULE_AUTHOR("Balsam CHIHI <bchihi@baylibre.com>");
++MODULE_DESCRIPTION("MediaTek LVTS Thermal Driver");
++MODULE_LICENSE("GPL");
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-07-dt-bindings-thermal-mediatek-Add-LVTS-thermal-contro.patch b/target/linux/mediatek/patches-6.1/830-v6.4-07-dt-bindings-thermal-mediatek-Add-LVTS-thermal-contro.patch
new file mode 100644
index 00000000000000..b6a5f64090111f
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-07-dt-bindings-thermal-mediatek-Add-LVTS-thermal-contro.patch
@@ -0,0 +1,186 @@
+From 498e2f7a6e69dcbca24715de2b4b97569fdfeff4 Mon Sep 17 00:00:00 2001
+From: Balsam CHIHI <bchihi@baylibre.com>
+Date: Thu, 9 Feb 2023 11:56:24 +0100
+Subject: [PATCH] dt-bindings: thermal: mediatek: Add LVTS thermal controllers
+
+Add LVTS thermal controllers dt-binding definition for mt8192 and mt8195.
+
+Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Link: https://lore.kernel.org/r/20230209105628.50294-3-bchihi@baylibre.com
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+---
+ .../thermal/mediatek,lvts-thermal.yaml        | 142 ++++++++++++++++++
+ .../thermal/mediatek,lvts-thermal.h           |  19 +++
+ 2 files changed, 161 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml
+ create mode 100644 include/dt-bindings/thermal/mediatek,lvts-thermal.h
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml
+@@ -0,0 +1,142 @@
++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/thermal/mediatek,lvts-thermal.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: MediaTek SoC Low Voltage Thermal Sensor (LVTS)
++
++maintainers:
++  - Balsam CHIHI <bchihi@baylibre.com>
++
++description: |
++  LVTS is a thermal management architecture composed of three subsystems,
++  a Sensing device - Thermal Sensing Micro Circuit Unit (TSMCU),
++  a Converter - Low Voltage Thermal Sensor converter (LVTS), and
++  a Digital controller (LVTS_CTRL).
++
++properties:
++  compatible:
++    enum:
++      - mediatek,mt8192-lvts-ap
++      - mediatek,mt8192-lvts-mcu
++      - mediatek,mt8195-lvts-ap
++      - mediatek,mt8195-lvts-mcu
++
++  reg:
++    maxItems: 1
++
++  interrupts:
++    maxItems: 1
++
++  clocks:
++    maxItems: 1
++
++  resets:
++    maxItems: 1
++    description: LVTS reset for clearing temporary data on AP/MCU.
++
++  nvmem-cells:
++    minItems: 1
++    items:
++      - description: Calibration eFuse data 1 for LVTS
++      - description: Calibration eFuse data 2 for LVTS
++
++  nvmem-cell-names:
++    minItems: 1
++    items:
++      - const: lvts-calib-data-1
++      - const: lvts-calib-data-2
++
++  "#thermal-sensor-cells":
++    const: 1
++
++allOf:
++  - $ref: thermal-sensor.yaml#
++
++  - if:
++      properties:
++        compatible:
++          contains:
++            enum:
++              - mediatek,mt8192-lvts-ap
++              - mediatek,mt8192-lvts-mcu
++    then:
++      properties:
++        nvmem-cells:
++          maxItems: 1
++
++        nvmem-cell-names:
++          maxItems: 1
++
++  - if:
++      properties:
++        compatible:
++          contains:
++            enum:
++              - mediatek,mt8195-lvts-ap
++              - mediatek,mt8195-lvts-mcu
++    then:
++      properties:
++        nvmem-cells:
++          minItems: 2
++
++        nvmem-cell-names:
++          minItems: 2
++
++required:
++  - compatible
++  - reg
++  - interrupts
++  - clocks
++  - resets
++  - nvmem-cells
++  - nvmem-cell-names
++  - "#thermal-sensor-cells"
++
++additionalProperties: false
++
++examples:
++  - |
++    #include <dt-bindings/interrupt-controller/arm-gic.h>
++    #include <dt-bindings/clock/mt8195-clk.h>
++    #include <dt-bindings/reset/mt8195-resets.h>
++    #include <dt-bindings/thermal/mediatek,lvts-thermal.h>
++
++    soc {
++      #address-cells = <2>;
++      #size-cells = <2>;
++
++      lvts_mcu: thermal-sensor@11278000 {
++        compatible = "mediatek,mt8195-lvts-mcu";
++        reg = <0 0x11278000 0 0x1000>;
++        interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>;
++        clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
++        resets = <&infracfg_ao MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST>;
++        nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>;
++        nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
++        #thermal-sensor-cells = <1>;
++      };
++    };
++
++    thermal_zones: thermal-zones {
++      cpu0-thermal {
++        polling-delay = <1000>;
++        polling-delay-passive = <250>;
++        thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU0>;
++
++        trips {
++          cpu0_alert: trip-alert {
++            temperature = <85000>;
++            hysteresis = <2000>;
++            type = "passive";
++          };
++
++          cpu0_crit: trip-crit {
++            temperature = <100000>;
++            hysteresis = <2000>;
++            type = "critical";
++          };
++        };
++      };
++    };
+--- /dev/null
++++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h
+@@ -0,0 +1,19 @@
++/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
++/*
++ * Copyright (c) 2023 MediaTek Inc.
++ * Author: Balsam CHIHI <bchihi@baylibre.com>
++ */
++
++#ifndef __MEDIATEK_LVTS_DT_H
++#define __MEDIATEK_LVTS_DT_H
++
++#define MT8195_MCU_BIG_CPU0     0
++#define MT8195_MCU_BIG_CPU1     1
++#define MT8195_MCU_BIG_CPU2     2
++#define MT8195_MCU_BIG_CPU3     3
++#define MT8195_MCU_LITTLE_CPU0  4
++#define MT8195_MCU_LITTLE_CPU1  5
++#define MT8195_MCU_LITTLE_CPU2  6
++#define MT8195_MCU_LITTLE_CPU3  7
++
++#endif /* __MEDIATEK_LVTS_DT_H */
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-08-dt-bindings-thermal-mediatek-Add-AP-domain-to-LVTS-t.patch b/target/linux/mediatek/patches-6.1/830-v6.4-08-dt-bindings-thermal-mediatek-Add-AP-domain-to-LVTS-t.patch
new file mode 100644
index 00000000000000..efb0d8b64fb3ba
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-08-dt-bindings-thermal-mediatek-Add-AP-domain-to-LVTS-t.patch
@@ -0,0 +1,35 @@
+From 05aaa7fdb0736262e224369b9b9f1410320fc71b Mon Sep 17 00:00:00 2001
+From: Balsam CHIHI <bchihi@baylibre.com>
+Date: Tue, 7 Mar 2023 16:45:21 +0100
+Subject: [PATCH] dt-bindings: thermal: mediatek: Add AP domain to LVTS thermal
+ controllers for mt8195
+
+Add AP Domain to LVTS thermal controllers dt-binding definition for mt8195.
+
+Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
+Acked-by: Rob Herring <robh@kernel.org>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Tested-by: Chen-Yu Tsai <wenst@chromium.org>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230307154524.118541-2-bchihi@baylibre.com
+---
+ include/dt-bindings/thermal/mediatek,lvts-thermal.h | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+--- a/include/dt-bindings/thermal/mediatek,lvts-thermal.h
++++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h
+@@ -16,4 +16,14 @@
+ #define MT8195_MCU_LITTLE_CPU2  6
+ #define MT8195_MCU_LITTLE_CPU3  7
+ 
++#define MT8195_AP_VPU0  8
++#define MT8195_AP_VPU1  9
++#define MT8195_AP_GPU0  10
++#define MT8195_AP_GPU1  11
++#define MT8195_AP_VDEC  12
++#define MT8195_AP_IMG   13
++#define MT8195_AP_INFRA 14
++#define MT8195_AP_CAM0  15
++#define MT8195_AP_CAM1  16
++
+ #endif /* __MEDIATEK_LVTS_DT_H */
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-09-thermal-core-Add-a-thermal-zone-devdata-accessor.patch b/target/linux/mediatek/patches-6.1/830-v6.4-09-thermal-core-Add-a-thermal-zone-devdata-accessor.patch
new file mode 100644
index 00000000000000..c68969321e5a51
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-09-thermal-core-Add-a-thermal-zone-devdata-accessor.patch
@@ -0,0 +1,65 @@
+From a6ff3c0021468721b96e84892a8cae24bde8d65f Mon Sep 17 00:00:00 2001
+From: Daniel Lezcano <daniel.lezcano@linaro.org>
+Date: Wed, 1 Mar 2023 21:14:29 +0100
+Subject: [PATCH] thermal/core: Add a thermal zone 'devdata' accessor
+
+The thermal zone device structure is exposed to the different drivers
+and obviously they access the internals while that should be
+restricted to the core thermal code.
+
+In order to self-encapsulate the thermal core code, we need to prevent
+the drivers accessing directly the thermal zone structure and provide
+accessor functions to deal with.
+
+Provide an accessor to the 'devdata' structure and make use of it in
+the different drivers.
+
+No functional changes intended.
+
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+Acked-by: Mark Brown <broonie@kernel.org>
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+---
+ drivers/thermal/thermal_core.c | 6 ++++++
+ include/linux/thermal.h        | 7 +++++++
+ 2 files changed, 13 insertions(+)
+
+--- a/drivers/thermal/thermal_core.c
++++ b/drivers/thermal/thermal_core.c
+@@ -1346,6 +1346,12 @@ struct thermal_zone_device *thermal_zone
+ }
+ EXPORT_SYMBOL_GPL(thermal_zone_device_register);
+ 
++void *thermal_zone_device_priv(struct thermal_zone_device *tzd)
++{
++	return tzd->devdata;
++}
++EXPORT_SYMBOL_GPL(thermal_zone_device_priv);
++
+ /**
+  * thermal_zone_device_unregister - removes the registered thermal zone device
+  * @tz: the thermal zone device to remove
+--- a/include/linux/thermal.h
++++ b/include/linux/thermal.h
+@@ -346,6 +346,8 @@ thermal_zone_device_register_with_trips(
+ 					void *, struct thermal_zone_device_ops *,
+ 					struct thermal_zone_params *, int, int);
+ 
++void *thermal_zone_device_priv(struct thermal_zone_device *tzd);
++
+ int thermal_zone_bind_cooling_device(struct thermal_zone_device *, int,
+ 				     struct thermal_cooling_device *,
+ 				     unsigned long, unsigned long,
+@@ -417,6 +419,11 @@ static inline int thermal_zone_get_offse
+ 		struct thermal_zone_device *tz)
+ { return -ENODEV; }
+ 
++static inline void *thermal_zone_device_priv(struct thermal_zone_device *tz)
++{
++	return NULL;
++}
++
+ static inline int thermal_zone_device_enable(struct thermal_zone_device *tz)
+ { return -ENODEV; }
+ 
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-10-thermal-core-Add-thermal_zone_device-structure-type-.patch b/target/linux/mediatek/patches-6.1/830-v6.4-10-thermal-core-Add-thermal_zone_device-structure-type-.patch
new file mode 100644
index 00000000000000..66d3c9e302891f
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-10-thermal-core-Add-thermal_zone_device-structure-type-.patch
@@ -0,0 +1,55 @@
+From 072e35c98806100182c0a7263cf4cba09ce43463 Mon Sep 17 00:00:00 2001
+From: Daniel Lezcano <daniel.lezcano@linaro.org>
+Date: Wed, 1 Mar 2023 21:14:38 +0100
+Subject: [PATCH] thermal/core: Add thermal_zone_device structure 'type'
+ accessor
+
+The thermal zone device structure is exposed via the exported
+thermal.h header. This structure should stay private the thermal core
+code. In order to encapsulate the structure, let's add an accessor to
+get the 'type' of the thermal zone.
+
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+---
+ drivers/thermal/thermal_core.c | 6 ++++++
+ include/linux/thermal.h        | 6 ++++++
+ 2 files changed, 12 insertions(+)
+
+--- a/drivers/thermal/thermal_core.c
++++ b/drivers/thermal/thermal_core.c
+@@ -1352,6 +1352,12 @@ void *thermal_zone_device_priv(struct th
+ }
+ EXPORT_SYMBOL_GPL(thermal_zone_device_priv);
+ 
++const char *thermal_zone_device_type(struct thermal_zone_device *tzd)
++{
++	return tzd->type;
++}
++EXPORT_SYMBOL_GPL(thermal_zone_device_type);
++
+ /**
+  * thermal_zone_device_unregister - removes the registered thermal zone device
+  * @tz: the thermal zone device to remove
+--- a/include/linux/thermal.h
++++ b/include/linux/thermal.h
+@@ -347,6 +347,7 @@ thermal_zone_device_register_with_trips(
+ 					struct thermal_zone_params *, int, int);
+ 
+ void *thermal_zone_device_priv(struct thermal_zone_device *tzd);
++const char *thermal_zone_device_type(struct thermal_zone_device *tzd);
+ 
+ int thermal_zone_bind_cooling_device(struct thermal_zone_device *, int,
+ 				     struct thermal_cooling_device *,
+@@ -423,6 +424,11 @@ static inline void *thermal_zone_device_
+ {
+ 	return NULL;
+ }
++
++static inline const char *thermal_zone_device_type(struct thermal_zone_device *tzd)
++{
++	return NULL;
++}
+ 
+ static inline int thermal_zone_device_enable(struct thermal_zone_device *tz)
+ { return -ENODEV; }
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-11-thermal-core-Use-the-thermal-zone-devdata-accessor-i.patch b/target/linux/mediatek/patches-6.1/830-v6.4-11-thermal-core-Use-the-thermal-zone-devdata-accessor-i.patch
new file mode 100644
index 00000000000000..57bc910d3e3cc4
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-11-thermal-core-Use-the-thermal-zone-devdata-accessor-i.patch
@@ -0,0 +1,74 @@
+From 7d78bab533eb9aa0e5240e25a204e8f416723ed6 Mon Sep 17 00:00:00 2001
+From: Daniel Lezcano <daniel.lezcano@linaro.org>
+Date: Wed, 1 Mar 2023 21:14:30 +0100
+Subject: [PATCH 07/42] thermal/core: Use the thermal zone 'devdata' accessor
+ in thermal located drivers
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The thermal zone device structure is exposed to the different drivers
+and obviously they access the internals while that should be
+restricted to the core thermal code.
+
+In order to self-encapsulate the thermal core code, we need to prevent
+the drivers accessing directly the thermal zone structure and provide
+accessor functions to deal with.
+
+Use the devdata accessor introduced in the previous patch.
+
+No functional changes intended.
+
+[skipped drivers not relevant for mediatek target]
+
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> #R-Car
+Acked-by: Mark Brown <broonie@kernel.org>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> #MediaTek auxadc and lvts
+Reviewed-by: Balsam CHIHI <bchihi@baylibre.com> #Mediatek lvts
+Reviewed-by: Adam Ward <DLG-Adam.Ward.opensource@dm.renesas.com> #da9062
+Reviewed-by: Baolin Wang <baolin.wang@linux.alibaba.com>  #spread
+Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> #sun8i_thermal
+Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+Acked-by: Florian Fainelli <f.fainelli@gmail.com> #Broadcom
+Reviewed-by: Dhruva Gole <d-gole@ti.com> # K3 bandgap
+Acked-by: Linus Walleij <linus.walleij@linaro.org>
+Acked-by: Heiko Stuebner <heiko@sntech.de> #rockchip
+Reviewed-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> #uniphier
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+---
+ drivers/thermal/mediatek/auxadc_thermal.c           |  2 +-
+ drivers/thermal/mediatek/lvts_thermal.c             |  4 ++--
+ 43 files changed, 71 insertions(+), 73 deletions(-)
+
+--- a/drivers/thermal/mediatek/auxadc_thermal.c
++++ b/drivers/thermal/mediatek/auxadc_thermal.c
+@@ -763,7 +763,7 @@ static int mtk_thermal_bank_temperature(
+ 
+ static int mtk_read_temp(struct thermal_zone_device *tz, int *temperature)
+ {
+-	struct mtk_thermal *mt = tz->devdata;
++	struct mtk_thermal *mt = thermal_zone_device_priv(tz);
+ 	int i;
+ 	int tempmax = INT_MIN;
+ 
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -252,7 +252,7 @@ static u32 lvts_temp_to_raw(int temperat
+ 
+ static int lvts_get_temp(struct thermal_zone_device *tz, int *temp)
+ {
+-	struct lvts_sensor *lvts_sensor = tz->devdata;
++	struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz);
+ 	void __iomem *msr = lvts_sensor->msr;
+ 	u32 value;
+ 
+@@ -290,7 +290,7 @@ static int lvts_get_temp(struct thermal_
+ 
+ static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high)
+ {
+-	struct lvts_sensor *lvts_sensor = tz->devdata;
++	struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz);
+ 	void __iomem *base = lvts_sensor->base;
+ 	u32 raw_low = lvts_temp_to_raw(low);
+ 	u32 raw_high = lvts_temp_to_raw(high);
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-12-thermal-hwmon-Use-the-right-device-for-devm_thermal_.patch b/target/linux/mediatek/patches-6.1/830-v6.4-12-thermal-hwmon-Use-the-right-device-for-devm_thermal_.patch
new file mode 100644
index 00000000000000..647b3b0eca11a4
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-12-thermal-hwmon-Use-the-right-device-for-devm_thermal_.patch
@@ -0,0 +1,201 @@
+From cc9c60e9cfeeac45d63361fa8c085c43c4bdfe3a Mon Sep 17 00:00:00 2001
+From: Daniel Lezcano <daniel.lezcano@linaro.org>
+Date: Wed, 1 Mar 2023 21:14:36 +0100
+Subject: [PATCH 08/42] thermal/hwmon: Use the right device for
+ devm_thermal_add_hwmon_sysfs()
+
+The devres variant of thermal_add_hwmon_sysfs() only takes the thermal
+zone structure pointer as parameter.
+
+Actually, it uses the tz->device to add it in the devres list.
+
+It is preferable to use the device registering the thermal zone
+instead of the thermal zone device itself. That prevents the driver
+accessing the thermal zone structure internals and it is from my POV
+more correct regarding how devm_ is used.
+
+[skipped imx thermal which did not apply cleanly and irrelevant on
+mediatek target]
+
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> #amlogic_thermal
+Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> #sun8i_thermal
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> #MediaTek auxadc
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+---
+ drivers/thermal/amlogic_thermal.c                  | 2 +-
+ drivers/thermal/imx_sc_thermal.c                   | 2 +-
+ drivers/thermal/k3_bandgap.c                       | 2 +-
+ drivers/thermal/mediatek/auxadc_thermal.c          | 2 +-
+ drivers/thermal/qcom/qcom-spmi-adc-tm5.c           | 2 +-
+ drivers/thermal/qcom/qcom-spmi-temp-alarm.c        | 2 +-
+ drivers/thermal/qcom/tsens.c                       | 2 +-
+ drivers/thermal/qoriq_thermal.c                    | 2 +-
+ drivers/thermal/sun8i_thermal.c                    | 2 +-
+ drivers/thermal/tegra/tegra30-tsensor.c            | 2 +-
+ drivers/thermal/thermal_hwmon.c                    | 4 ++--
+ drivers/thermal/thermal_hwmon.h                    | 4 ++--
+ drivers/thermal/ti-soc-thermal/ti-thermal-common.c | 2 +-
+ 13 files changed, 15 insertions(+), 15 deletions(-)
+
+--- a/drivers/thermal/amlogic_thermal.c
++++ b/drivers/thermal/amlogic_thermal.c
+@@ -286,7 +286,7 @@ static int amlogic_thermal_probe(struct
+ 		return ret;
+ 	}
+ 
+-	if (devm_thermal_add_hwmon_sysfs(pdata->tzd))
++	if (devm_thermal_add_hwmon_sysfs(&pdev->dev, pdata->tzd))
+ 		dev_warn(&pdev->dev, "Failed to add hwmon sysfs attributes\n");
+ 
+ 	ret = amlogic_thermal_initialize(pdata);
+--- a/drivers/thermal/imx_sc_thermal.c
++++ b/drivers/thermal/imx_sc_thermal.c
+@@ -120,7 +120,7 @@ static int imx_sc_thermal_probe(struct p
+ 			return ret;
+ 		}
+ 
+-		if (devm_thermal_add_hwmon_sysfs(sensor->tzd))
++		if (devm_thermal_add_hwmon_sysfs(&pdev->dev, sensor->tzd))
+ 			dev_warn(&pdev->dev, "failed to add hwmon sysfs attributes\n");
+ 	}
+ 
+--- a/drivers/thermal/k3_bandgap.c
++++ b/drivers/thermal/k3_bandgap.c
+@@ -222,7 +222,7 @@ static int k3_bandgap_probe(struct platf
+ 			goto err_alloc;
+ 		}
+ 
+-		if (devm_thermal_add_hwmon_sysfs(data[id].tzd))
++		if (devm_thermal_add_hwmon_sysfs(dev, data[id].tzd))
+ 			dev_warn(dev, "Failed to add hwmon sysfs attributes\n");
+ 	}
+ 
+--- a/drivers/thermal/mediatek/auxadc_thermal.c
++++ b/drivers/thermal/mediatek/auxadc_thermal.c
+@@ -1210,7 +1210,7 @@ static int mtk_thermal_probe(struct plat
+ 		goto err_disable_clk_peri_therm;
+ 	}
+ 
+-	ret = devm_thermal_add_hwmon_sysfs(tzdev);
++	ret = devm_thermal_add_hwmon_sysfs(&pdev->dev, tzdev);
+ 	if (ret)
+ 		dev_warn(&pdev->dev, "error in thermal_add_hwmon_sysfs");
+ 
+--- a/drivers/thermal/qcom/qcom-spmi-adc-tm5.c
++++ b/drivers/thermal/qcom/qcom-spmi-adc-tm5.c
+@@ -688,7 +688,7 @@ static int adc_tm5_register_tzd(struct a
+ 			return PTR_ERR(tzd);
+ 		}
+ 		adc_tm->channels[i].tzd = tzd;
+-		if (devm_thermal_add_hwmon_sysfs(tzd))
++		if (devm_thermal_add_hwmon_sysfs(adc_tm->dev, tzd))
+ 			dev_warn(adc_tm->dev,
+ 				 "Failed to add hwmon sysfs attributes\n");
+ 	}
+--- a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c
++++ b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c
+@@ -460,7 +460,7 @@ static int qpnp_tm_probe(struct platform
+ 		return ret;
+ 	}
+ 
+-	if (devm_thermal_add_hwmon_sysfs(chip->tz_dev))
++	if (devm_thermal_add_hwmon_sysfs(&pdev->dev, chip->tz_dev))
+ 		dev_warn(&pdev->dev,
+ 			 "Failed to add hwmon sysfs attributes\n");
+ 
+--- a/drivers/thermal/qcom/tsens.c
++++ b/drivers/thermal/qcom/tsens.c
+@@ -1056,7 +1056,7 @@ static int tsens_register(struct tsens_p
+ 		if (priv->ops->enable)
+ 			priv->ops->enable(priv, i);
+ 
+-		if (devm_thermal_add_hwmon_sysfs(tzd))
++		if (devm_thermal_add_hwmon_sysfs(priv->dev, tzd))
+ 			dev_warn(priv->dev,
+ 				 "Failed to add hwmon sysfs attributes\n");
+ 	}
+--- a/drivers/thermal/qoriq_thermal.c
++++ b/drivers/thermal/qoriq_thermal.c
+@@ -158,7 +158,7 @@ static int qoriq_tmu_register_tmu_zone(s
+ 			return ret;
+ 		}
+ 
+-		if (devm_thermal_add_hwmon_sysfs(tzd))
++		if (devm_thermal_add_hwmon_sysfs(dev, tzd))
+ 			dev_warn(dev,
+ 				 "Failed to add hwmon sysfs attributes\n");
+ 
+--- a/drivers/thermal/sun8i_thermal.c
++++ b/drivers/thermal/sun8i_thermal.c
+@@ -468,7 +468,7 @@ static int sun8i_ths_register(struct ths
+ 		if (IS_ERR(tmdev->sensor[i].tzd))
+ 			return PTR_ERR(tmdev->sensor[i].tzd);
+ 
+-		if (devm_thermal_add_hwmon_sysfs(tmdev->sensor[i].tzd))
++		if (devm_thermal_add_hwmon_sysfs(tmdev->dev, tmdev->sensor[i].tzd))
+ 			dev_warn(tmdev->dev,
+ 				 "Failed to add hwmon sysfs attributes\n");
+ 	}
+--- a/drivers/thermal/tegra/tegra30-tsensor.c
++++ b/drivers/thermal/tegra/tegra30-tsensor.c
+@@ -530,7 +530,7 @@ static int tegra_tsensor_register_channe
+ 		return 0;
+ 	}
+ 
+-	if (devm_thermal_add_hwmon_sysfs(tsc->tzd))
++	if (devm_thermal_add_hwmon_sysfs(ts->dev, tsc->tzd))
+ 		dev_warn(ts->dev, "failed to add hwmon sysfs attributes\n");
+ 
+ 	return 0;
+--- a/drivers/thermal/thermal_hwmon.c
++++ b/drivers/thermal/thermal_hwmon.c
+@@ -255,7 +255,7 @@ static void devm_thermal_hwmon_release(s
+ 	thermal_remove_hwmon_sysfs(*(struct thermal_zone_device **)res);
+ }
+ 
+-int devm_thermal_add_hwmon_sysfs(struct thermal_zone_device *tz)
++int devm_thermal_add_hwmon_sysfs(struct device *dev, struct thermal_zone_device *tz)
+ {
+ 	struct thermal_zone_device **ptr;
+ 	int ret;
+@@ -272,7 +272,7 @@ int devm_thermal_add_hwmon_sysfs(struct
+ 	}
+ 
+ 	*ptr = tz;
+-	devres_add(&tz->device, ptr);
++	devres_add(dev, ptr);
+ 
+ 	return ret;
+ }
+--- a/drivers/thermal/thermal_hwmon.h
++++ b/drivers/thermal/thermal_hwmon.h
+@@ -17,7 +17,7 @@
+ 
+ #ifdef CONFIG_THERMAL_HWMON
+ int thermal_add_hwmon_sysfs(struct thermal_zone_device *tz);
+-int devm_thermal_add_hwmon_sysfs(struct thermal_zone_device *tz);
++int devm_thermal_add_hwmon_sysfs(struct device *dev, struct thermal_zone_device *tz);
+ void thermal_remove_hwmon_sysfs(struct thermal_zone_device *tz);
+ #else
+ static inline int
+@@ -27,7 +27,7 @@ thermal_add_hwmon_sysfs(struct thermal_z
+ }
+ 
+ static inline int
+-devm_thermal_add_hwmon_sysfs(struct thermal_zone_device *tz)
++devm_thermal_add_hwmon_sysfs(struct device *dev, struct thermal_zone_device *tz)
+ {
+ 	return 0;
+ }
+--- a/drivers/thermal/ti-soc-thermal/ti-thermal-common.c
++++ b/drivers/thermal/ti-soc-thermal/ti-thermal-common.c
+@@ -182,7 +182,7 @@ int ti_thermal_expose_sensor(struct ti_b
+ 	ti_bandgap_set_sensor_data(bgp, id, data);
+ 	ti_bandgap_write_update_interval(bgp, data->sensor_id, interval);
+ 
+-	if (devm_thermal_add_hwmon_sysfs(data->ti_thermal))
++	if (devm_thermal_add_hwmon_sysfs(bgp->dev, data->ti_thermal))
+ 		dev_warn(bgp->dev, "failed to add hwmon sysfs attributes\n");
+ 
+ 	return 0;
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-13-thermal-Don-t-use-device-internal-thermal-zone-struc.patch b/target/linux/mediatek/patches-6.1/830-v6.4-13-thermal-Don-t-use-device-internal-thermal-zone-struc.patch
new file mode 100644
index 00000000000000..9dedc2cb685279
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-13-thermal-Don-t-use-device-internal-thermal-zone-struc.patch
@@ -0,0 +1,79 @@
+From 5a72b8e4bac753e4dc74dc0a1335d120f63df97a Mon Sep 17 00:00:00 2001
+From: Daniel Lezcano <daniel.lezcano@linaro.org>
+Date: Wed, 1 Mar 2023 21:14:37 +0100
+Subject: [PATCH 09/42] thermal: Don't use 'device' internal thermal zone
+ structure field
+
+Some drivers are directly using the thermal zone's 'device' structure
+field.
+
+Use the driver device pointer instead of the thermal zone device when
+it is available.
+
+Remove the traces when they are duplicate with the traces in the core
+code.
+
+[again skipped imx_thermal.c]
+
+Cc: Jean Delvare <jdelvare@suse.com>
+Cc: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Reviewed-by: Balsam CHIHI <bchihi@baylibre.com> #Mediatek LVTS
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> #MediaTek LVTS
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+---
+ drivers/thermal/mediatek/lvts_thermal.c            | 4 ++--
+ drivers/thermal/thermal_hwmon.c                    | 4 ++--
+ drivers/thermal/ti-soc-thermal/ti-thermal-common.c | 2 +-
+ 3 files changed, 5 insertions(+), 5 deletions(-)
+
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -305,7 +305,7 @@ static int lvts_set_trips(struct thermal
+ 	 * 14-0 : Raw temperature for threshold
+ 	 */
+ 	if (low != -INT_MAX) {
+-		dev_dbg(&tz->device, "Setting low limit temperature interrupt: %d\n", low);
++		pr_debug("%s: Setting low limit temperature interrupt: %d\n", tz->type, low);
+ 		writel(raw_low, LVTS_H2NTHRE(base));
+ 	}
+ 
+@@ -318,7 +318,7 @@ static int lvts_set_trips(struct thermal
+ 	 *
+ 	 * 14-0 : Raw temperature for threshold
+ 	 */
+-	dev_dbg(&tz->device, "Setting high limit temperature interrupt: %d\n", high);
++	pr_debug("%s: Setting high limit temperature interrupt: %d\n", tz->type, high);
+ 	writel(raw_high, LVTS_HTHRE(base));
+ 
+ 	return 0;
+--- a/drivers/thermal/thermal_hwmon.c
++++ b/drivers/thermal/thermal_hwmon.c
+@@ -220,14 +220,14 @@ void thermal_remove_hwmon_sysfs(struct t
+ 	hwmon = thermal_hwmon_lookup_by_type(tz);
+ 	if (unlikely(!hwmon)) {
+ 		/* Should never happen... */
+-		dev_dbg(&tz->device, "hwmon device lookup failed!\n");
++		dev_dbg(hwmon->device, "hwmon device lookup failed!\n");
+ 		return;
+ 	}
+ 
+ 	temp = thermal_hwmon_lookup_temp(hwmon, tz);
+ 	if (unlikely(!temp)) {
+ 		/* Should never happen... */
+-		dev_dbg(&tz->device, "temperature input lookup failed!\n");
++		dev_dbg(hwmon->device, "temperature input lookup failed!\n");
+ 		return;
+ 	}
+ 
+--- a/drivers/thermal/ti-soc-thermal/ti-thermal-common.c
++++ b/drivers/thermal/ti-soc-thermal/ti-thermal-common.c
+@@ -43,7 +43,7 @@ static void ti_thermal_work(struct work_
+ 
+ 	thermal_zone_device_update(data->ti_thermal, THERMAL_EVENT_UNSPECIFIED);
+ 
+-	dev_dbg(&data->ti_thermal->device, "updated thermal zone %s\n",
++	dev_dbg(data->bgp->dev, "updated thermal zone %s\n",
+ 		data->ti_thermal->type);
+ }
+ 
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-14-thermal-Use-thermal_zone_device_type-accessor.patch b/target/linux/mediatek/patches-6.1/830-v6.4-14-thermal-Use-thermal_zone_device_type-accessor.patch
new file mode 100644
index 00000000000000..8cec9aba97729c
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-14-thermal-Use-thermal_zone_device_type-accessor.patch
@@ -0,0 +1,62 @@
+From 66b3a292d3fc749e8ec7ac5278a17e8a5757ecbc Mon Sep 17 00:00:00 2001
+From: Daniel Lezcano <daniel.lezcano@linaro.org>
+Date: Wed, 1 Mar 2023 21:14:41 +0100
+Subject: [PATCH 10/42] thermal: Use thermal_zone_device_type() accessor
+
+Replace the accesses to 'tz->type' by its accessor version in order to
+self-encapsulate the thermal_zone_device structure.
+
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Reviewed-by: Ido Schimmel <idosch@nvidia.com> #mlxsw
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> #MediaTek LVTS
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+---
+ drivers/net/ethernet/mellanox/mlxsw/core_thermal.c | 2 +-
+ drivers/thermal/mediatek/lvts_thermal.c            | 6 ++++--
+ drivers/thermal/ti-soc-thermal/ti-thermal-common.c | 2 +-
+ 3 files changed, 6 insertions(+), 4 deletions(-)
+
+--- a/drivers/net/ethernet/mellanox/mlxsw/core_thermal.c
++++ b/drivers/net/ethernet/mellanox/mlxsw/core_thermal.c
+@@ -168,7 +168,7 @@ mlxsw_thermal_module_trips_update(struct
+ 
+ 	if (crit_temp > emerg_temp) {
+ 		dev_warn(dev, "%s : Critical threshold %d is above emergency threshold %d\n",
+-			 tz->tzdev->type, crit_temp, emerg_temp);
++			 thermal_zone_device_type(tz->tzdev), crit_temp, emerg_temp);
+ 		return 0;
+ 	}
+ 
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -305,7 +305,8 @@ static int lvts_set_trips(struct thermal
+ 	 * 14-0 : Raw temperature for threshold
+ 	 */
+ 	if (low != -INT_MAX) {
+-		pr_debug("%s: Setting low limit temperature interrupt: %d\n", tz->type, low);
++		pr_debug("%s: Setting low limit temperature interrupt: %d\n",
++			 thermal_zone_device_type(tz), low);
+ 		writel(raw_low, LVTS_H2NTHRE(base));
+ 	}
+ 
+@@ -318,7 +319,8 @@ static int lvts_set_trips(struct thermal
+ 	 *
+ 	 * 14-0 : Raw temperature for threshold
+ 	 */
+-	pr_debug("%s: Setting high limit temperature interrupt: %d\n", tz->type, high);
++	pr_debug("%s: Setting high limit temperature interrupt: %d\n",
++		 thermal_zone_device_type(tz), high);
+ 	writel(raw_high, LVTS_HTHRE(base));
+ 
+ 	return 0;
+--- a/drivers/thermal/ti-soc-thermal/ti-thermal-common.c
++++ b/drivers/thermal/ti-soc-thermal/ti-thermal-common.c
+@@ -44,7 +44,7 @@ static void ti_thermal_work(struct work_
+ 	thermal_zone_device_update(data->ti_thermal, THERMAL_EVENT_UNSPECIFIED);
+ 
+ 	dev_dbg(data->bgp->dev, "updated thermal zone %s\n",
+-		data->ti_thermal->type);
++		thermal_zone_device_type(data->ti_thermal));
+ }
+ 
+ /**
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-15-thermal-drivers-mediatek-Control-buffer-enablement-t.patch b/target/linux/mediatek/patches-6.1/830-v6.4-15-thermal-drivers-mediatek-Control-buffer-enablement-t.patch
new file mode 100644
index 00000000000000..68f41fdd168d98
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-15-thermal-drivers-mediatek-Control-buffer-enablement-t.patch
@@ -0,0 +1,81 @@
+From f6658c1c4ae98477d6be00495226c0617354fe76 Mon Sep 17 00:00:00 2001
+From: Markus Schneider-Pargmann <msp@baylibre.com>
+Date: Fri, 27 Jan 2023 16:44:43 +0100
+Subject: [PATCH 11/42] thermal/drivers/mediatek: Control buffer enablement
+ tweaks
+
+Add logic in order to be able to turn on the control buffer on MT8365.
+This change now allows to have control buffer support for MTK_THERMAL_V1,
+and it allows to define the register offset, and mask used to enable it.
+
+Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
+Signed-off-by: Fabien Parent <fparent@baylibre.com>
+Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Link: https://lore.kernel.org/r/20221018-up-i350-thermal-bringup-v9-2-55a1ae14af74@baylibre.com
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+---
+ drivers/thermal/mediatek/auxadc_thermal.c | 28 +++++++++++++++--------
+ 1 file changed, 19 insertions(+), 9 deletions(-)
+
+--- a/drivers/thermal/mediatek/auxadc_thermal.c
++++ b/drivers/thermal/mediatek/auxadc_thermal.c
+@@ -307,6 +307,9 @@ struct mtk_thermal_data {
+ 	bool need_switch_bank;
+ 	struct thermal_bank_cfg bank_data[MAX_NUM_ZONES];
+ 	enum mtk_thermal_version version;
++	u32 apmixed_buffer_ctl_reg;
++	u32 apmixed_buffer_ctl_mask;
++	u32 apmixed_buffer_ctl_set;
+ };
+ 
+ struct mtk_thermal {
+@@ -560,6 +563,9 @@ static const struct mtk_thermal_data mt7
+ 	.adcpnp = mt7622_adcpnp,
+ 	.sensor_mux_values = mt7622_mux_values,
+ 	.version = MTK_THERMAL_V2,
++	.apmixed_buffer_ctl_reg = APMIXED_SYS_TS_CON1,
++	.apmixed_buffer_ctl_mask = GENMASK(31, 6) | BIT(3),
++	.apmixed_buffer_ctl_set = BIT(0),
+ };
+ 
+ /*
+@@ -1079,14 +1085,18 @@ static const struct of_device_id mtk_the
+ };
+ MODULE_DEVICE_TABLE(of, mtk_thermal_of_match);
+ 
+-static void mtk_thermal_turn_on_buffer(void __iomem *apmixed_base)
++static void mtk_thermal_turn_on_buffer(struct mtk_thermal *mt,
++				       void __iomem *apmixed_base)
+ {
+-	int tmp;
++	u32 tmp;
++
++	if (!mt->conf->apmixed_buffer_ctl_reg)
++		return;
+ 
+-	tmp = readl(apmixed_base + APMIXED_SYS_TS_CON1);
+-	tmp &= ~(0x37);
+-	tmp |= 0x1;
+-	writel(tmp, apmixed_base + APMIXED_SYS_TS_CON1);
++	tmp = readl(apmixed_base + mt->conf->apmixed_buffer_ctl_reg);
++	tmp &= mt->conf->apmixed_buffer_ctl_mask;
++	tmp |= mt->conf->apmixed_buffer_ctl_set;
++	writel(tmp, apmixed_base + mt->conf->apmixed_buffer_ctl_reg);
+ 	udelay(200);
+ }
+ 
+@@ -1184,10 +1194,10 @@ static int mtk_thermal_probe(struct plat
+ 		goto err_disable_clk_auxadc;
+ 	}
+ 
+-	if (mt->conf->version != MTK_THERMAL_V1) {
+-		mtk_thermal_turn_on_buffer(apmixed_base);
++	mtk_thermal_turn_on_buffer(mt, apmixed_base);
++
++	if (mt->conf->version != MTK_THERMAL_V2)
+ 		mtk_thermal_release_periodic_ts(mt, auxadc_base);
+-	}
+ 
+ 	if (mt->conf->version == MTK_THERMAL_V1)
+ 		mt->raw_to_mcelsius = raw_to_mcelsius_v1;
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-16-thermal-drivers-mediatek-Add-support-for-MT8365-SoC.patch b/target/linux/mediatek/patches-6.1/830-v6.4-16-thermal-drivers-mediatek-Add-support-for-MT8365-SoC.patch
new file mode 100644
index 00000000000000..285c6f6a7b3aa0
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-16-thermal-drivers-mediatek-Add-support-for-MT8365-SoC.patch
@@ -0,0 +1,123 @@
+From c4eff784465f88218dc5eb51320320464db83d3f Mon Sep 17 00:00:00 2001
+From: Fabien Parent <fparent@baylibre.com>
+Date: Fri, 27 Jan 2023 16:44:44 +0100
+Subject: [PATCH 12/42] thermal/drivers/mediatek: Add support for MT8365 SoC
+
+MT8365 is similar to the other SoCs supported by the driver. It has only
+one bank and 3 actual sensors that can be multiplexed. There is another
+one sensor that does not have usable data.
+
+Signed-off-by: Fabien Parent <fparent@baylibre.com>
+Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Link: https://lore.kernel.org/r/20221018-up-i350-thermal-bringup-v9-3-55a1ae14af74@baylibre.com
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+---
+ drivers/thermal/mediatek/auxadc_thermal.c | 68 +++++++++++++++++++++++
+ 1 file changed, 68 insertions(+)
+
+--- a/drivers/thermal/mediatek/auxadc_thermal.c
++++ b/drivers/thermal/mediatek/auxadc_thermal.c
+@@ -31,6 +31,7 @@
+ #define AUXADC_CON2_V		0x010
+ #define AUXADC_DATA(channel)	(0x14 + (channel) * 4)
+ 
++#define APMIXED_SYS_TS_CON0	0x600
+ #define APMIXED_SYS_TS_CON1	0x604
+ 
+ /* Thermal Controller Registers */
+@@ -281,6 +282,17 @@ enum mtk_thermal_version {
+ /* The calibration coefficient of sensor  */
+ #define MT7986_CALIBRATION		165
+ 
++/* MT8365 */
++#define MT8365_TEMP_AUXADC_CHANNEL 11
++#define MT8365_CALIBRATION 164
++#define MT8365_NUM_CONTROLLER 1
++#define MT8365_NUM_BANKS 1
++#define MT8365_NUM_SENSORS 3
++#define MT8365_NUM_SENSORS_PER_ZONE 3
++#define MT8365_TS1 0
++#define MT8365_TS2 1
++#define MT8365_TS3 2
++
+ struct mtk_thermal;
+ 
+ struct thermal_bank_cfg {
+@@ -435,6 +447,24 @@ static const int mt7986_mux_values[MT798
+ static const int mt7986_vts_index[MT7986_NUM_SENSORS] = { VTS1 };
+ static const int mt7986_tc_offset[MT7986_NUM_CONTROLLER] = { 0x0, };
+ 
++/* MT8365 thermal sensor data */
++static const int mt8365_bank_data[MT8365_NUM_SENSORS] = {
++	MT8365_TS1, MT8365_TS2, MT8365_TS3
++};
++
++static const int mt8365_msr[MT8365_NUM_SENSORS_PER_ZONE] = {
++	TEMP_MSR0, TEMP_MSR1, TEMP_MSR2
++};
++
++static const int mt8365_adcpnp[MT8365_NUM_SENSORS_PER_ZONE] = {
++	TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2
++};
++
++static const int mt8365_mux_values[MT8365_NUM_SENSORS] = { 0, 1, 2 };
++static const int mt8365_tc_offset[MT8365_NUM_CONTROLLER] = { 0 };
++
++static const int mt8365_vts_index[MT8365_NUM_SENSORS] = { VTS1, VTS2, VTS3 };
++
+ /*
+  * The MT8173 thermal controller has four banks. Each bank can read up to
+  * four temperature sensors simultaneously. The MT8173 has a total of 5
+@@ -510,6 +540,40 @@ static const struct mtk_thermal_data mt2
+ };
+ 
+ /*
++ * The MT8365 thermal controller has one bank, which can read up to
++ * four temperature sensors simultaneously. The MT8365 has a total of 3
++ * temperature sensors.
++ *
++ * The thermal core only gets the maximum temperature of this one bank,
++ * so the bank concept wouldn't be necessary here. However, the SVS (Smart
++ * Voltage Scaling) unit makes its decisions based on the same bank
++ * data.
++ */
++static const struct mtk_thermal_data mt8365_thermal_data = {
++	.auxadc_channel = MT8365_TEMP_AUXADC_CHANNEL,
++	.num_banks = MT8365_NUM_BANKS,
++	.num_sensors = MT8365_NUM_SENSORS,
++	.vts_index = mt8365_vts_index,
++	.cali_val = MT8365_CALIBRATION,
++	.num_controller = MT8365_NUM_CONTROLLER,
++	.controller_offset = mt8365_tc_offset,
++	.need_switch_bank = false,
++	.bank_data = {
++		{
++			.num_sensors = MT8365_NUM_SENSORS,
++			.sensors = mt8365_bank_data
++		},
++	},
++	.msr = mt8365_msr,
++	.adcpnp = mt8365_adcpnp,
++	.sensor_mux_values = mt8365_mux_values,
++	.version = MTK_THERMAL_V1,
++	.apmixed_buffer_ctl_reg = APMIXED_SYS_TS_CON0,
++	.apmixed_buffer_ctl_mask = (u32) ~GENMASK(29, 28),
++	.apmixed_buffer_ctl_set = 0,
++};
++
++/*
+  * The MT2712 thermal controller has one bank, which can read up to
+  * four temperature sensors simultaneously. The MT2712 has a total of 4
+  * temperature sensors.
+@@ -1080,6 +1144,10 @@ static const struct of_device_id mtk_the
+ 	{
+ 		.compatible = "mediatek,mt8183-thermal",
+ 		.data = (void *)&mt8183_thermal_data,
++	},
++	{
++		.compatible = "mediatek,mt8365-thermal",
++		.data = (void *)&mt8365_thermal_data,
+ 	}, {
+ 	},
+ };
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-17-thermal-drivers-mediatek-Add-delay-after-thermal-ban.patch b/target/linux/mediatek/patches-6.1/830-v6.4-17-thermal-drivers-mediatek-Add-delay-after-thermal-ban.patch
new file mode 100644
index 00000000000000..5c99aa80c1ed72
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-17-thermal-drivers-mediatek-Add-delay-after-thermal-ban.patch
@@ -0,0 +1,50 @@
+From 4eead70db74922bc61e9d0b4591524369a335751 Mon Sep 17 00:00:00 2001
+From: Amjad Ouled-Ameur <aouledameur@baylibre.com>
+Date: Fri, 27 Jan 2023 16:44:46 +0100
+Subject: [PATCH 13/42] thermal/drivers/mediatek: Add delay after thermal banks
+ initialization
+
+Thermal sensor reads performed immediately after thermal bank
+initialization returns bogus values. This is currently tackled by returning
+0 if the temperature is bogus (exceeding 200000).
+
+Instead, add a delay between the bank init and the thermal zone device
+register to properly fix this.
+
+Signed-off-by: Michael Kao <michael.kao@mediatek.com>
+Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
+Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Link: https://lore.kernel.org/r/20221018-up-i350-thermal-bringup-v9-5-55a1ae14af74@baylibre.com
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+---
+ drivers/thermal/mediatek/auxadc_thermal.c | 11 +++--------
+ 1 file changed, 3 insertions(+), 8 deletions(-)
+
+--- a/drivers/thermal/mediatek/auxadc_thermal.c
++++ b/drivers/thermal/mediatek/auxadc_thermal.c
+@@ -816,14 +816,6 @@ static int mtk_thermal_bank_temperature(
+ 			mt, conf->bank_data[bank->id].sensors[i], raw);
+ 
+ 
+-		/*
+-		 * The first read of a sensor often contains very high bogus
+-		 * temperature value. Filter these out so that the system does
+-		 * not immediately shut down.
+-		 */
+-		if (temp > 200000)
+-			temp = 0;
+-
+ 		if (temp > max)
+ 			max = temp;
+ 	}
+@@ -1281,6 +1273,9 @@ static int mtk_thermal_probe(struct plat
+ 
+ 	platform_set_drvdata(pdev, mt);
+ 
++	/* Delay for thermal banks to be ready */
++	msleep(30);
++
+ 	tzdev = devm_thermal_of_zone_register(&pdev->dev, 0, mt,
+ 					      &mtk_thermal_ops);
+ 	if (IS_ERR(tzdev)) {
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-18-thermal-drivers-mediatek-lvts_thermal-Fix-sensor-1-i.patch b/target/linux/mediatek/patches-6.1/830-v6.4-18-thermal-drivers-mediatek-lvts_thermal-Fix-sensor-1-i.patch
new file mode 100644
index 00000000000000..734f5c1e770ede
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-18-thermal-drivers-mediatek-lvts_thermal-Fix-sensor-1-i.patch
@@ -0,0 +1,46 @@
+From ad9dc9e92367803a4f9576aea0dab110d03fc510 Mon Sep 17 00:00:00 2001
+From: Chen-Yu Tsai <wenst@chromium.org>
+Date: Tue, 28 Mar 2023 11:10:17 +0800
+Subject: [PATCH 14/42] thermal/drivers/mediatek/lvts_thermal: Fix sensor 1
+ interrupt status bitmask
+
+The binary representation for sensor 1 interrupt status was incorrectly
+assembled, when compared to the full table given in the same comment
+section. The conversion into hex was also incorrect, leading to
+incorrect interrupt status bitmask for sensor 1. This would cause the
+driver to incorrectly identify changes for sensor 1, when in fact it
+was sensor 0, or a sensor access time out.
+
+Fix the binary and hex representations in the comments, and the actual
+bitmask macro.
+
+Fixes: f5f633b18234 ("thermal/drivers/mediatek: Add the Low Voltage Thermal Sensor driver")
+Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230328031017.1360976-1-wenst@chromium.org
+---
+ drivers/thermal/mediatek/lvts_thermal.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -66,7 +66,7 @@
+ #define LVTS_MONINT_CONF			0x9FBF7BDE
+ 
+ #define LVTS_INT_SENSOR0			0x0009001F
+-#define LVTS_INT_SENSOR1			0X000881F0
++#define LVTS_INT_SENSOR1			0x001203E0
+ #define LVTS_INT_SENSOR2			0x00247C00
+ #define LVTS_INT_SENSOR3			0x1FC00000
+ 
+@@ -395,8 +395,8 @@ static irqreturn_t lvts_ctrl_irq_handler
+ 	 *                  => 0x1FC00000
+ 	 * sensor 2 interrupt: 0000 0000 0010 0100 0111 1100 0000 0000
+ 	 *                  => 0x00247C00
+-	 * sensor 1 interrupt: 0000 0000 0001 0001 0000 0011 1110 0000
+-	 *                  => 0X000881F0
++	 * sensor 1 interrupt: 0000 0000 0001 0010 0000 0011 1110 0000
++	 *                  => 0X001203E0
+ 	 * sensor 0 interrupt: 0000 0000 0000 1001 0000 0000 0001 1111
+ 	 *                  => 0x0009001F
+ 	 */
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-19-thermal-drivers-mediatek-lvts_thermal-Add-AP-domain-.patch b/target/linux/mediatek/patches-6.1/830-v6.4-19-thermal-drivers-mediatek-lvts_thermal-Add-AP-domain-.patch
new file mode 100644
index 00000000000000..d09c2055a3ef87
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-19-thermal-drivers-mediatek-lvts_thermal-Add-AP-domain-.patch
@@ -0,0 +1,149 @@
+From 9aad43ad3285fc21158fb416830a6156a9a31fa5 Mon Sep 17 00:00:00 2001
+From: Balsam CHIHI <bchihi@baylibre.com>
+Date: Tue, 7 Mar 2023 16:45:22 +0100
+Subject: [PATCH 15/42] thermal/drivers/mediatek/lvts_thermal: Add AP domain
+ for mt8195
+
+Add MT8195 AP Domain support to LVTS Driver.
+
+Take the opportunity to update the comments to show calibration data
+information related to the new domain.
+
+[dlezcano]: Massaged a bit the changelog
+
+Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
+Tested-by: Chen-Yu Tsai <wenst@chromium.org>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230307154524.118541-3-bchihi@baylibre.com
+---
+ drivers/thermal/mediatek/lvts_thermal.c | 94 +++++++++++++++++++------
+ 1 file changed, 74 insertions(+), 20 deletions(-)
+
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -530,29 +530,33 @@ static int lvts_sensor_init(struct devic
+  * The efuse blob values follows the sensor enumeration per thermal
+  * controller. The decoding of the stream is as follow:
+  *
+- *                        <--?-> <----big0 ???---> <-sensor0-> <-0->
+- *                        ------------------------------------------
+- * index in the stream: : | 0x0 | 0x1 | 0x2 | 0x3 | 0x4 | 0x5 | 0x6 |
+- *                        ------------------------------------------
++ * stream index map for MCU Domain :
+  *
+- *                        <--sensor1--><-0-> <----big1 ???---> <-sen
+- *                        ------------------------------------------
+- *                        | 0x7 | 0x8 | 0x9 | 0xA | 0xB | OxC | OxD |
+- *                        ------------------------------------------
++ * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1----->
++ *  0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09
+  *
+- *                        sor0-> <-0-> <-sensor1-> <-0-> ..........
+- *                        ------------------------------------------
+- *                        | 0x7 | 0x8 | 0x9 | 0xA | 0xB | OxC | OxD |
+- *                        ------------------------------------------
++ * <-----mcu-tc#1-----> <-----sensor#2-----> <-----sensor#3----->
++ *  0x0A | 0x0B | 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12
+  *
+- * And so on ...
++ * <-----mcu-tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7----->
++ *  0x13 | 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21
++ *
++ * stream index map for AP Domain :
++ *
++ * <-----ap--tc#0-----> <-----sensor#0-----> <-----sensor#1----->
++ *  0x22 | 0x23 | 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A
++ *
++ * <-----ap--tc#1-----> <-----sensor#2-----> <-----sensor#3----->
++ *  0x2B | 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33
++ *
++ * <-----ap--tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6----->
++ *  0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B | 0x3C | 0x3D | 0x3E | 0x3F
++ *
++ * <-----ap--tc#3-----> <-----sensor#7-----> <-----sensor#8----->
++ *  0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 | 0x48
+  *
+  * The data description gives the offset of the calibration data in
+  * this bytes stream for each sensor.
+- *
+- * Each thermal controller can handle up to 4 sensors max, we don't
+- * care if there are less as the array of calibration is sized to 4
+- * anyway. The unused sensor slot will be zeroed.
+  */
+ static int lvts_calibration_init(struct device *dev, struct lvts_ctrl *lvts_ctrl,
+ 					const struct lvts_ctrl_data *lvts_ctrl_data,
+@@ -1165,7 +1169,7 @@ static int lvts_remove(struct platform_d
+ 	return 0;
+ }
+ 
+-static const struct lvts_ctrl_data mt8195_lvts_data_ctrl[] = {
++static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = {
+ 	{
+ 		.cal_offset = { 0x04, 0x07 },
+ 		.lvts_sensor = {
+@@ -1200,13 +1204,63 @@ static const struct lvts_ctrl_data mt819
+ 	}
+ };
+ 
++static const struct lvts_ctrl_data mt8195_lvts_ap_data_ctrl[] = {
++		{
++		.cal_offset = { 0x25, 0x28 },
++		.lvts_sensor = {
++			{ .dt_id = MT8195_AP_VPU0 },
++			{ .dt_id = MT8195_AP_VPU1 }
++		},
++		.num_lvts_sensor = 2,
++		.offset = 0x0,
++		.hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
++	},
++	{
++		.cal_offset = { 0x2e, 0x31 },
++		.lvts_sensor = {
++			{ .dt_id = MT8195_AP_GPU0 },
++			{ .dt_id = MT8195_AP_GPU1 }
++		},
++		.num_lvts_sensor = 2,
++		.offset = 0x100,
++		.hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
++	},
++	{
++		.cal_offset = { 0x37, 0x3a, 0x3d },
++		.lvts_sensor = {
++			{ .dt_id = MT8195_AP_VDEC },
++			{ .dt_id = MT8195_AP_IMG },
++			{ .dt_id = MT8195_AP_INFRA },
++		},
++		.num_lvts_sensor = 3,
++		.offset = 0x200,
++		.hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
++	},
++	{
++		.cal_offset = { 0x43, 0x46 },
++		.lvts_sensor = {
++			{ .dt_id = MT8195_AP_CAM0 },
++			{ .dt_id = MT8195_AP_CAM1 }
++		},
++		.num_lvts_sensor = 2,
++		.offset = 0x300,
++		.hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
++	}
++};
++
+ static const struct lvts_data mt8195_lvts_mcu_data = {
+-	.lvts_ctrl	= mt8195_lvts_data_ctrl,
+-	.num_lvts_ctrl	= ARRAY_SIZE(mt8195_lvts_data_ctrl),
++	.lvts_ctrl	= mt8195_lvts_mcu_data_ctrl,
++	.num_lvts_ctrl	= ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl),
++};
++
++static const struct lvts_data mt8195_lvts_ap_data = {
++	.lvts_ctrl	= mt8195_lvts_ap_data_ctrl,
++	.num_lvts_ctrl	= ARRAY_SIZE(mt8195_lvts_ap_data_ctrl),
+ };
+ 
+ static const struct of_device_id lvts_of_match[] = {
+ 	{ .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data },
++	{ .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data },
+ 	{},
+ };
+ MODULE_DEVICE_TABLE(of, lvts_of_match);
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-20-Revert-thermal-drivers-mediatek-Add-delay-after-ther.patch b/target/linux/mediatek/patches-6.1/830-v6.4-20-Revert-thermal-drivers-mediatek-Add-delay-after-ther.patch
new file mode 100644
index 00000000000000..a48ea3742bb16e
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-20-Revert-thermal-drivers-mediatek-Add-delay-after-ther.patch
@@ -0,0 +1,53 @@
+From 7105a86760bd9e4d107075cefc75016b693a5542 Mon Sep 17 00:00:00 2001
+From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Date: Wed, 19 Apr 2023 08:11:45 +0200
+Subject: [PATCH 16/42] Revert "thermal/drivers/mediatek: Add delay after
+ thermal banks initialization"
+
+Some more testing revealed that this commit introduces a regression on some
+MT8173 Chromebooks and at least on one MT6795 Sony Xperia M5 smartphone due
+to the delay being apparently variable and machine specific.
+
+Another solution would be to delay for a bit more (~70ms) but this is not
+feasible for two reasons: first of all, we're adding an even bigger delay
+in a probe function; second, some machines need less, some may need even
+more, making the msleep at probe solution highly suboptimal.
+
+This reverts commit 10debf8c2da8011c8009dd4b3f6d0ab85891c81b.
+
+Fixes: 10debf8c2da8 ("thermal/drivers/mediatek: Add delay after thermal banks initialization")
+Reported-by: "kernelci.org bot" <bot@kernelci.org>
+Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230419061146.22246-2-angelogioacchino.delregno@collabora.com
+---
+ drivers/thermal/mediatek/auxadc_thermal.c | 11 ++++++++---
+ 1 file changed, 8 insertions(+), 3 deletions(-)
+
+--- a/drivers/thermal/mediatek/auxadc_thermal.c
++++ b/drivers/thermal/mediatek/auxadc_thermal.c
+@@ -816,6 +816,14 @@ static int mtk_thermal_bank_temperature(
+ 			mt, conf->bank_data[bank->id].sensors[i], raw);
+ 
+ 
++		/*
++		 * The first read of a sensor often contains very high bogus
++		 * temperature value. Filter these out so that the system does
++		 * not immediately shut down.
++		 */
++		if (temp > 200000)
++			temp = 0;
++
+ 		if (temp > max)
+ 			max = temp;
+ 	}
+@@ -1273,9 +1281,6 @@ static int mtk_thermal_probe(struct plat
+ 
+ 	platform_set_drvdata(pdev, mt);
+ 
+-	/* Delay for thermal banks to be ready */
+-	msleep(30);
+-
+ 	tzdev = devm_thermal_of_zone_register(&pdev->dev, 0, mt,
+ 					      &mtk_thermal_ops);
+ 	if (IS_ERR(tzdev)) {
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-21-thermal-drivers-mediatek-Add-temperature-constraints.patch b/target/linux/mediatek/patches-6.1/830-v6.4-21-thermal-drivers-mediatek-Add-temperature-constraints.patch
new file mode 100644
index 00000000000000..aae87af5d1cc42
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-21-thermal-drivers-mediatek-Add-temperature-constraints.patch
@@ -0,0 +1,78 @@
+From 681b652c9dfc4037d4a55b2733e091a4e1a5de18 Mon Sep 17 00:00:00 2001
+From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Date: Wed, 19 Apr 2023 08:11:46 +0200
+Subject: [PATCH 17/42] thermal/drivers/mediatek: Add temperature constraints
+ to validate read
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The AUXADC thermal v1 allows reading temperature range between -20°C to
+150°C and any value out of this range is invalid.
+
+Add new definitions for MT8173_TEMP_{MIN_MAX} and a new small helper
+mtk_thermal_temp_is_valid() to check if new readings are in range: if
+not, we tell to the API that the reading is invalid by returning
+THERMAL_TEMP_INVALID.
+
+It was chosen to introduce the helper function because, even though this
+temperature range is realistically ok for all, it comes from a downstream
+kernel driver for version 1, but here we also support v2 and v3 which may
+may have wider constraints.
+
+Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230419061146.22246-3-angelogioacchino.delregno@collabora.com
+---
+ drivers/thermal/mediatek/auxadc_thermal.c | 24 +++++++++++++++++------
+ 1 file changed, 18 insertions(+), 6 deletions(-)
+
+--- a/drivers/thermal/mediatek/auxadc_thermal.c
++++ b/drivers/thermal/mediatek/auxadc_thermal.c
+@@ -116,6 +116,10 @@
+ /* The calibration coefficient of sensor  */
+ #define MT8173_CALIBRATION	165
+ 
++/* Valid temperatures range */
++#define MT8173_TEMP_MIN		-20000
++#define MT8173_TEMP_MAX		150000
++
+ /*
+  * Layout of the fuses providing the calibration data
+  * These macros could be used for MT8183, MT8173, MT2701, and MT2712.
+@@ -689,6 +693,11 @@ static const struct mtk_thermal_data mt7
+ 	.version = MTK_THERMAL_V3,
+ };
+ 
++static bool mtk_thermal_temp_is_valid(int temp)
++{
++	return (temp >= MT8173_TEMP_MIN) && (temp <= MT8173_TEMP_MAX);
++}
++
+ /**
+  * raw_to_mcelsius_v1 - convert a raw ADC value to mcelsius
+  * @mt:	The thermal controller
+@@ -815,14 +824,17 @@ static int mtk_thermal_bank_temperature(
+ 		temp = mt->raw_to_mcelsius(
+ 			mt, conf->bank_data[bank->id].sensors[i], raw);
+ 
+-
+ 		/*
+-		 * The first read of a sensor often contains very high bogus
+-		 * temperature value. Filter these out so that the system does
+-		 * not immediately shut down.
++		 * Depending on the filt/sen intervals and ADC polling time,
++		 * we may need up to 60 milliseconds after initialization: this
++		 * will result in the first reading containing an out of range
++		 * temperature value.
++		 * Validate the reading to both address the aforementioned issue
++		 * and to eventually avoid bogus readings during runtime in the
++		 * event that the AUXADC gets unstable due to high EMI, etc.
+ 		 */
+-		if (temp > 200000)
+-			temp = 0;
++		if (!mtk_thermal_temp_is_valid(temp))
++			temp = THERMAL_TEMP_INVALID;
+ 
+ 		if (temp > max)
+ 			max = temp;
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-22-thermal-drivers-mediatek-Use-devm_of_iomap-to-avoid-.patch b/target/linux/mediatek/patches-6.1/830-v6.4-22-thermal-drivers-mediatek-Use-devm_of_iomap-to-avoid-.patch
new file mode 100644
index 00000000000000..782684aacc6839
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-22-thermal-drivers-mediatek-Use-devm_of_iomap-to-avoid-.patch
@@ -0,0 +1,53 @@
+From 458fa1d508de3f17e49d974a0158d9aeff273a58 Mon Sep 17 00:00:00 2001
+From: Kang Chen <void0red@hust.edu.cn>
+Date: Wed, 19 Apr 2023 10:07:48 +0800
+Subject: [PATCH 18/42] thermal/drivers/mediatek: Use devm_of_iomap to avoid
+ resource leak in mtk_thermal_probe
+
+Smatch reports:
+1. mtk_thermal_probe() warn: 'apmixed_base' from of_iomap() not released.
+2. mtk_thermal_probe() warn: 'auxadc_base' from of_iomap() not released.
+
+The original code forgets to release iomap resource when handling errors,
+fix it by switch to devm_of_iomap.
+
+Fixes: 89945047b166 ("thermal: mediatek: Add tsensor support for V2 thermal system")
+Signed-off-by: Kang Chen <void0red@hust.edu.cn>
+Reviewed-by: Dongliang Mu <dzm91@hust.edu.cn>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230419020749.621257-1-void0red@hust.edu.cn
+---
+ drivers/thermal/mediatek/auxadc_thermal.c | 14 ++++++++++++--
+ 1 file changed, 12 insertions(+), 2 deletions(-)
+
+--- a/drivers/thermal/mediatek/auxadc_thermal.c
++++ b/drivers/thermal/mediatek/auxadc_thermal.c
+@@ -1232,7 +1232,12 @@ static int mtk_thermal_probe(struct plat
+ 		return -ENODEV;
+ 	}
+ 
+-	auxadc_base = of_iomap(auxadc, 0);
++	auxadc_base = devm_of_iomap(&pdev->dev, auxadc, 0, NULL);
++	if (IS_ERR(auxadc_base)) {
++		of_node_put(auxadc);
++		return PTR_ERR(auxadc_base);
++	}
++
+ 	auxadc_phys_base = of_get_phys_base(auxadc);
+ 
+ 	of_node_put(auxadc);
+@@ -1248,7 +1253,12 @@ static int mtk_thermal_probe(struct plat
+ 		return -ENODEV;
+ 	}
+ 
+-	apmixed_base = of_iomap(apmixedsys, 0);
++	apmixed_base = devm_of_iomap(&pdev->dev, apmixedsys, 0, NULL);
++	if (IS_ERR(apmixed_base)) {
++		of_node_put(apmixedsys);
++		return PTR_ERR(apmixed_base);
++	}
++
+ 	apmixed_phys_base = of_get_phys_base(apmixedsys);
+ 
+ 	of_node_put(apmixedsys);
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-23-thermal-drivers-mediatek-Change-clk_prepare_enable-t.patch b/target/linux/mediatek/patches-6.1/830-v6.4-23-thermal-drivers-mediatek-Change-clk_prepare_enable-t.patch
new file mode 100644
index 00000000000000..d7896dbd60a7a5
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-23-thermal-drivers-mediatek-Change-clk_prepare_enable-t.patch
@@ -0,0 +1,100 @@
+From 227d1856924ec00a4f5bdf5afcf77bc7f3f04e86 Mon Sep 17 00:00:00 2001
+From: Kang Chen <void0red@hust.edu.cn>
+Date: Wed, 19 Apr 2023 10:07:49 +0800
+Subject: [PATCH 19/42] thermal/drivers/mediatek: Change clk_prepare_enable to
+ devm_clk_get_enabled in mtk_thermal_probe
+
+Use devm_clk_get_enabled to do automatic resource management.
+Meanwhile, remove error handling labels in the probe function and
+the whole remove function.
+
+Signed-off-by: Kang Chen <void0red@hust.edu.cn>
+Reviewed-by: Dongliang Mu <dzm91@hust.edu.cn>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230419020749.621257-2-void0red@hust.edu.cn
+---
+ drivers/thermal/mediatek/auxadc_thermal.c | 44 +++++------------------
+ 1 file changed, 9 insertions(+), 35 deletions(-)
+
+--- a/drivers/thermal/mediatek/auxadc_thermal.c
++++ b/drivers/thermal/mediatek/auxadc_thermal.c
+@@ -1206,14 +1206,6 @@ static int mtk_thermal_probe(struct plat
+ 
+ 	mt->conf = of_device_get_match_data(&pdev->dev);
+ 
+-	mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm");
+-	if (IS_ERR(mt->clk_peri_therm))
+-		return PTR_ERR(mt->clk_peri_therm);
+-
+-	mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc");
+-	if (IS_ERR(mt->clk_auxadc))
+-		return PTR_ERR(mt->clk_auxadc);
+-
+ 	mt->thermal_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
+ 	if (IS_ERR(mt->thermal_base))
+ 		return PTR_ERR(mt->thermal_base);
+@@ -1272,16 +1264,18 @@ static int mtk_thermal_probe(struct plat
+ 	if (ret)
+ 		return ret;
+ 
+-	ret = clk_prepare_enable(mt->clk_auxadc);
+-	if (ret) {
++	mt->clk_auxadc = devm_clk_get_enabled(&pdev->dev, "auxadc");
++	if (IS_ERR(mt->clk_auxadc)) {
++		ret = PTR_ERR(mt->clk_auxadc);
+ 		dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret);
+ 		return ret;
+ 	}
+ 
+-	ret = clk_prepare_enable(mt->clk_peri_therm);
+-	if (ret) {
++	mt->clk_peri_therm = devm_clk_get_enabled(&pdev->dev, "therm");
++	if (IS_ERR(mt->clk_peri_therm)) {
++		ret = PTR_ERR(mt->clk_peri_therm);
+ 		dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret);
+-		goto err_disable_clk_auxadc;
++		return ret;
+ 	}
+ 
+ 	mtk_thermal_turn_on_buffer(mt, apmixed_base);
+@@ -1305,38 +1299,18 @@ static int mtk_thermal_probe(struct plat
+ 
+ 	tzdev = devm_thermal_of_zone_register(&pdev->dev, 0, mt,
+ 					      &mtk_thermal_ops);
+-	if (IS_ERR(tzdev)) {
+-		ret = PTR_ERR(tzdev);
+-		goto err_disable_clk_peri_therm;
+-	}
++	if (IS_ERR(tzdev))
++		return PTR_ERR(tzdev);
+ 
+ 	ret = devm_thermal_add_hwmon_sysfs(&pdev->dev, tzdev);
+ 	if (ret)
+ 		dev_warn(&pdev->dev, "error in thermal_add_hwmon_sysfs");
+ 
+ 	return 0;
+-
+-err_disable_clk_peri_therm:
+-	clk_disable_unprepare(mt->clk_peri_therm);
+-err_disable_clk_auxadc:
+-	clk_disable_unprepare(mt->clk_auxadc);
+-
+-	return ret;
+-}
+-
+-static int mtk_thermal_remove(struct platform_device *pdev)
+-{
+-	struct mtk_thermal *mt = platform_get_drvdata(pdev);
+-
+-	clk_disable_unprepare(mt->clk_peri_therm);
+-	clk_disable_unprepare(mt->clk_auxadc);
+-
+-	return 0;
+ }
+ 
+ static struct platform_driver mtk_thermal_driver = {
+ 	.probe = mtk_thermal_probe,
+-	.remove = mtk_thermal_remove,
+ 	.driver = {
+ 		.name = "mtk-thermal",
+ 		.of_match_table = mtk_thermal_of_match,
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-24-thermal-drivers-mediatek-Use-of_address_to_resource.patch b/target/linux/mediatek/patches-6.1/830-v6.4-24-thermal-drivers-mediatek-Use-of_address_to_resource.patch
new file mode 100644
index 00000000000000..fd18a5365c0ab8
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-24-thermal-drivers-mediatek-Use-of_address_to_resource.patch
@@ -0,0 +1,36 @@
+From 655fe2533ac05323a07c19ba079bf2064e7741af Mon Sep 17 00:00:00 2001
+From: Rob Herring <robh@kernel.org>
+Date: Sun, 19 Mar 2023 11:32:31 -0500
+Subject: [PATCH 20/42] thermal/drivers/mediatek: Use of_address_to_resource()
+
+Replace of_get_address() and of_translate_address() calls with single
+call to of_address_to_resource().
+
+Signed-off-by: Rob Herring <robh@kernel.org>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230319163231.226738-1-robh@kernel.org
+---
+ drivers/thermal/mediatek/auxadc_thermal.c | 8 +++-----
+ 1 file changed, 3 insertions(+), 5 deletions(-)
+
+--- a/drivers/thermal/mediatek/auxadc_thermal.c
++++ b/drivers/thermal/mediatek/auxadc_thermal.c
+@@ -979,14 +979,12 @@ static void mtk_thermal_init_bank(struct
+ 
+ static u64 of_get_phys_base(struct device_node *np)
+ {
+-	u64 size64;
+-	const __be32 *regaddr_p;
++	struct resource res;
+ 
+-	regaddr_p = of_get_address(np, 0, &size64, NULL);
+-	if (!regaddr_p)
++	if (of_address_to_resource(np, 0, &res))
+ 		return OF_BAD_ADDR;
+ 
+-	return of_translate_address(np, regaddr_p);
++	return res.start;
+ }
+ 
+ static int mtk_thermal_extract_efuse_v1(struct mtk_thermal *mt, u32 *buf)
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-25-Revert-thermal-drivers-mediatek-Use-devm_of_iomap-to.patch b/target/linux/mediatek/patches-6.1/830-v6.4-25-Revert-thermal-drivers-mediatek-Use-devm_of_iomap-to.patch
new file mode 100644
index 00000000000000..c3ff17d5173e5c
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-25-Revert-thermal-drivers-mediatek-Use-devm_of_iomap-to.patch
@@ -0,0 +1,57 @@
+From 2c380d07215e6fce3ac66cc5af059bc2c2a69f7a Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ricardo=20Ca=C3=B1uelo?= <ricardo.canuelo@collabora.com>
+Date: Thu, 25 May 2023 14:18:11 +0200
+Subject: [PATCH 21/42] Revert "thermal/drivers/mediatek: Use devm_of_iomap to
+ avoid resource leak in mtk_thermal_probe"
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This reverts commit f05c7b7d9ea9477fcc388476c6f4ade8c66d2d26.
+
+That change was causing a regression in the generic-adc-thermal-probed
+bootrr test as reported in the kernelci-results list [1].
+A proper rework will take longer, so revert it for now.
+
+[1] https://groups.io/g/kernelci-results/message/42660
+
+Fixes: f05c7b7d9ea9 ("thermal/drivers/mediatek: Use devm_of_iomap to avoid resource leak in mtk_thermal_probe")
+Signed-off-by: Ricardo Cañuelo <ricardo.canuelo@collabora.com>
+Suggested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230525121811.3360268-1-ricardo.canuelo@collabora.com
+---
+ drivers/thermal/mediatek/auxadc_thermal.c | 14 ++------------
+ 1 file changed, 2 insertions(+), 12 deletions(-)
+
+--- a/drivers/thermal/mediatek/auxadc_thermal.c
++++ b/drivers/thermal/mediatek/auxadc_thermal.c
+@@ -1222,12 +1222,7 @@ static int mtk_thermal_probe(struct plat
+ 		return -ENODEV;
+ 	}
+ 
+-	auxadc_base = devm_of_iomap(&pdev->dev, auxadc, 0, NULL);
+-	if (IS_ERR(auxadc_base)) {
+-		of_node_put(auxadc);
+-		return PTR_ERR(auxadc_base);
+-	}
+-
++	auxadc_base = of_iomap(auxadc, 0);
+ 	auxadc_phys_base = of_get_phys_base(auxadc);
+ 
+ 	of_node_put(auxadc);
+@@ -1243,12 +1238,7 @@ static int mtk_thermal_probe(struct plat
+ 		return -ENODEV;
+ 	}
+ 
+-	apmixed_base = devm_of_iomap(&pdev->dev, apmixedsys, 0, NULL);
+-	if (IS_ERR(apmixed_base)) {
+-		of_node_put(apmixedsys);
+-		return PTR_ERR(apmixed_base);
+-	}
+-
++	apmixed_base = of_iomap(apmixedsys, 0);
+ 	apmixed_phys_base = of_get_phys_base(apmixedsys);
+ 
+ 	of_node_put(apmixedsys);
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-26-thermal-drivers-mediatek-lvts_thermal-Register-therm.patch b/target/linux/mediatek/patches-6.1/830-v6.4-26-thermal-drivers-mediatek-lvts_thermal-Register-therm.patch
new file mode 100644
index 00000000000000..c4456529c1c4e1
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-26-thermal-drivers-mediatek-lvts_thermal-Register-therm.patch
@@ -0,0 +1,37 @@
+From 496f4b08981d8a788ad5a2073fa1c65a2af1862b Mon Sep 17 00:00:00 2001
+From: Chen-Yu Tsai <wenst@chromium.org>
+Date: Tue, 13 Jun 2023 17:13:16 +0800
+Subject: [PATCH 22/42] thermal/drivers/mediatek/lvts_thermal: Register thermal
+ zones as hwmon sensors
+
+Register thermal zones as hwmon sensors to let userspace read
+temperatures using standard hwmon interface.
+
+Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230613091317.1691247-1-wenst@chromium.org
+---
+ drivers/thermal/mediatek/lvts_thermal.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -19,6 +19,8 @@
+ #include <linux/thermal.h>
+ #include <dt-bindings/thermal/mediatek,lvts-thermal.h>
+ 
++#include "../thermal_hwmon.h"
++
+ #define LVTS_MONCTL0(__base)	(__base + 0x0000)
+ #define LVTS_MONCTL1(__base)	(__base + 0x0004)
+ #define LVTS_MONCTL2(__base)	(__base + 0x0008)
+@@ -996,6 +998,9 @@ static int lvts_ctrl_start(struct device
+ 			return PTR_ERR(tz);
+ 		}
+ 
++		if (devm_thermal_add_hwmon_sysfs(dev, tz))
++			dev_warn(dev, "zone %d: Failed to add hwmon sysfs attributes\n", dt_id);
++
+ 		/*
+ 		 * The thermal zone pointer will be needed in the
+ 		 * interrupt handler, we store it in the sensor
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-27-thermal-drivers-mediatek-lvts_thermal-Remove-redunda.patch b/target/linux/mediatek/patches-6.1/830-v6.4-27-thermal-drivers-mediatek-lvts_thermal-Remove-redunda.patch
new file mode 100644
index 00000000000000..22e7a954edec82
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-27-thermal-drivers-mediatek-lvts_thermal-Remove-redunda.patch
@@ -0,0 +1,28 @@
+From 885b9768ce2a66ed5d250822aed53d5114c895da Mon Sep 17 00:00:00 2001
+From: Yangtao Li <frank.li@vivo.com>
+Date: Tue, 20 Jun 2023 17:07:31 +0800
+Subject: [PATCH 23/42] thermal/drivers/mediatek/lvts_thermal: Remove redundant
+ msg in lvts_ctrl_start()
+
+The upper-layer devm_thermal_add_hwmon_sysfs() function can directly
+print error information.
+
+Signed-off-by: Yangtao Li <frank.li@vivo.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230620090732.50025-10-frank.li@vivo.com
+---
+ drivers/thermal/mediatek/lvts_thermal.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -998,8 +998,7 @@ static int lvts_ctrl_start(struct device
+ 			return PTR_ERR(tz);
+ 		}
+ 
+-		if (devm_thermal_add_hwmon_sysfs(dev, tz))
+-			dev_warn(dev, "zone %d: Failed to add hwmon sysfs attributes\n", dt_id);
++		devm_thermal_add_hwmon_sysfs(dev, tz);
+ 
+ 		/*
+ 		 * The thermal zone pointer will be needed in the
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-29-thermal-drivers-mediatek-lvts_thermal-Handle-IRQ-on-.patch b/target/linux/mediatek/patches-6.1/830-v6.4-29-thermal-drivers-mediatek-lvts_thermal-Handle-IRQ-on-.patch
new file mode 100644
index 00000000000000..bc67727423d0f8
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-29-thermal-drivers-mediatek-lvts_thermal-Handle-IRQ-on-.patch
@@ -0,0 +1,40 @@
+From 27b389d9f62c2174f95fe4002b11e77d4cb3ce80 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?=
+ <nfraprado@collabora.com>
+Date: Thu, 6 Jul 2023 11:37:32 -0400
+Subject: [PATCH 25/42] thermal/drivers/mediatek/lvts_thermal: Handle IRQ on
+ all controllers
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+There is a single IRQ handler for each LVTS thermal domain, and it is
+supposed to check each of its underlying controllers for the origin of
+the interrupt and clear its status. However due to a typo, only the
+first controller was ever being handled, which resulted in the interrupt
+never being cleared when it happened on the other controllers. Add the
+missing index so interrupts are handled for all controllers.
+
+Fixes: f5f633b18234 ("thermal/drivers/mediatek: Add the Low Voltage Thermal Sensor driver")
+Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Tested-by: Chen-Yu Tsai <wenst@chromium.org>
+Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
+Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230706153823.201943-2-nfraprado@collabora.com
+---
+ drivers/thermal/mediatek/lvts_thermal.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -451,7 +451,7 @@ static irqreturn_t lvts_irq_handler(int
+ 
+ 	for (i = 0; i < lvts_td->num_lvts_ctrl; i++) {
+ 
+-		aux = lvts_ctrl_irq_handler(lvts_td->lvts_ctrl);
++		aux = lvts_ctrl_irq_handler(&lvts_td->lvts_ctrl[i]);
+ 		if (aux != IRQ_HANDLED)
+ 			continue;
+ 
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-30-thermal-drivers-mediatek-lvts_thermal-Honor-sensors-.patch b/target/linux/mediatek/patches-6.1/830-v6.4-30-thermal-drivers-mediatek-lvts_thermal-Honor-sensors-.patch
new file mode 100644
index 00000000000000..51d119c05b85e9
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-30-thermal-drivers-mediatek-lvts_thermal-Honor-sensors-.patch
@@ -0,0 +1,120 @@
+From 6d827142643ee10c13ff9a1d90f38fb399aa9fff Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?=
+ <nfraprado@collabora.com>
+Date: Thu, 6 Jul 2023 11:37:33 -0400
+Subject: [PATCH 26/42] thermal/drivers/mediatek/lvts_thermal: Honor sensors in
+ immediate mode
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Each controller can be configured to operate on immediate or filtered
+mode. On filtered mode, the sensors are enabled by setting the
+corresponding bits in MONCTL0, while on immediate mode, by setting
+MSRCTL1.
+
+Previously, the code would set MSRCTL1 for all four sensors when
+configured to immediate mode, but given that the controller might not
+have all four sensors connected, this would cause interrupts to trigger
+for non-existent sensors. Fix this by handling the MSRCTL1 register
+analogously to the MONCTL0: only enable the sensors that were declared.
+
+Fixes: f5f633b18234 ("thermal/drivers/mediatek: Add the Low Voltage Thermal Sensor driver")
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Tested-by: Chen-Yu Tsai <wenst@chromium.org>
+Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
+Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230706153823.201943-3-nfraprado@collabora.com
+---
+ drivers/thermal/mediatek/lvts_thermal.c | 57 ++++++++++++++-----------
+ 1 file changed, 33 insertions(+), 24 deletions(-)
+
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -897,24 +897,6 @@ static int lvts_ctrl_configure(struct de
+ 	writel(value, LVTS_MSRCTL0(lvts_ctrl->base));
+ 
+ 	/*
+-	 * LVTS_MSRCTL1 : Measurement control
+-	 *
+-	 * Bits:
+-	 *
+-	 * 9: Ignore MSRCTL0 config and do immediate measurement on sensor3
+-	 * 6: Ignore MSRCTL0 config and do immediate measurement on sensor2
+-	 * 5: Ignore MSRCTL0 config and do immediate measurement on sensor1
+-	 * 4: Ignore MSRCTL0 config and do immediate measurement on sensor0
+-	 *
+-	 * That configuration will ignore the filtering and the delays
+-	 * introduced below in MONCTL1 and MONCTL2
+-	 */
+-	if (lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE) {
+-		value = BIT(9) | BIT(6) | BIT(5) | BIT(4);
+-		writel(value, LVTS_MSRCTL1(lvts_ctrl->base));
+-	}
+-
+-	/*
+ 	 * LVTS_MONCTL1 : Period unit and group interval configuration
+ 	 *
+ 	 * The clock source of LVTS thermal controller is 26MHz.
+@@ -979,6 +961,15 @@ static int lvts_ctrl_start(struct device
+ 	struct thermal_zone_device *tz;
+ 	u32 sensor_map = 0;
+ 	int i;
++	/*
++	 * Bitmaps to enable each sensor on immediate and filtered modes, as
++	 * described in MSRCTL1 and MONCTL0 registers below, respectively.
++	 */
++	u32 sensor_imm_bitmap[] = { BIT(4), BIT(5), BIT(6), BIT(9) };
++	u32 sensor_filt_bitmap[] = { BIT(0), BIT(1), BIT(2), BIT(3) };
++
++	u32 *sensor_bitmap = lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE ?
++			     sensor_imm_bitmap : sensor_filt_bitmap;
+ 
+ 	for (i = 0; i < lvts_ctrl->num_lvts_sensor; i++) {
+ 
+@@ -1016,20 +1007,38 @@ static int lvts_ctrl_start(struct device
+ 		 * map, so we can enable the temperature monitoring in
+ 		 * the hardware thermal controller.
+ 		 */
+-		sensor_map |= BIT(i);
++		sensor_map |= sensor_bitmap[i];
+ 	}
+ 
+ 	/*
+-	 * Bits:
+-	 *      9: Single point access flow
+-	 *    0-3: Enable sensing point 0-3
+-	 *
+ 	 * The initialization of the thermal zones give us
+ 	 * which sensor point to enable. If any thermal zone
+ 	 * was not described in the device tree, it won't be
+ 	 * enabled here in the sensor map.
+ 	 */
+-	writel(sensor_map | BIT(9), LVTS_MONCTL0(lvts_ctrl->base));
++	if (lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE) {
++		/*
++		 * LVTS_MSRCTL1 : Measurement control
++		 *
++		 * Bits:
++		 *
++		 * 9: Ignore MSRCTL0 config and do immediate measurement on sensor3
++		 * 6: Ignore MSRCTL0 config and do immediate measurement on sensor2
++		 * 5: Ignore MSRCTL0 config and do immediate measurement on sensor1
++		 * 4: Ignore MSRCTL0 config and do immediate measurement on sensor0
++		 *
++		 * That configuration will ignore the filtering and the delays
++		 * introduced in MONCTL1 and MONCTL2
++		 */
++		writel(sensor_map, LVTS_MSRCTL1(lvts_ctrl->base));
++	} else {
++		/*
++		 * Bits:
++		 *      9: Single point access flow
++		 *    0-3: Enable sensing point 0-3
++		 */
++		writel(sensor_map | BIT(9), LVTS_MONCTL0(lvts_ctrl->base));
++	}
+ 
+ 	return 0;
+ }
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-31-thermal-drivers-mediatek-lvts_thermal-Use-offset-thr.patch b/target/linux/mediatek/patches-6.1/830-v6.4-31-thermal-drivers-mediatek-lvts_thermal-Use-offset-thr.patch
new file mode 100644
index 00000000000000..bfbadee3503107
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-31-thermal-drivers-mediatek-lvts_thermal-Use-offset-thr.patch
@@ -0,0 +1,77 @@
+From 93bb11dd19bdcc1fc97c7ceababd0db9fde128ad Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?=
+ <nfraprado@collabora.com>
+Date: Thu, 6 Jul 2023 11:37:34 -0400
+Subject: [PATCH 27/42] thermal/drivers/mediatek/lvts_thermal: Use offset
+ threshold for IRQ
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+There are two kinds of temperature monitoring interrupts available:
+* High Offset, Low Offset
+* Hot, Hot to normal, Cold
+
+The code currently uses the hot/h2n/cold interrupts, however in a way
+that doesn't work: the cold threshold is left uninitialized, which
+prevents the other thresholds from ever triggering, and the h2n
+interrupt is used as the lower threshold, which prevents the hot
+interrupt from triggering again after the thresholds are updated by the
+thermal framework, since a hot interrupt can only trigger again after
+the hot to normal interrupt has been triggered.
+
+But better yet than addressing those issues, is to use the high/low
+offset interrupts instead. This way only two thresholds need to be
+managed, which have a simpler state machine, making them a better match
+to the thermal framework's high and low thresholds.
+
+Fixes: f5f633b18234 ("thermal/drivers/mediatek: Add the Low Voltage Thermal Sensor driver")
+Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
+Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230706153823.201943-4-nfraprado@collabora.com
+---
+ drivers/thermal/mediatek/lvts_thermal.c | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -298,9 +298,9 @@ static int lvts_set_trips(struct thermal
+ 	u32 raw_high = lvts_temp_to_raw(high);
+ 
+ 	/*
+-	 * Hot to normal temperature threshold
++	 * Low offset temperature threshold
+ 	 *
+-	 * LVTS_H2NTHRE
++	 * LVTS_OFFSETL
+ 	 *
+ 	 * Bits:
+ 	 *
+@@ -309,13 +309,13 @@ static int lvts_set_trips(struct thermal
+ 	if (low != -INT_MAX) {
+ 		pr_debug("%s: Setting low limit temperature interrupt: %d\n",
+ 			 thermal_zone_device_type(tz), low);
+-		writel(raw_low, LVTS_H2NTHRE(base));
++		writel(raw_low, LVTS_OFFSETL(base));
+ 	}
+ 
+ 	/*
+-	 * Hot temperature threshold
++	 * High offset temperature threshold
+ 	 *
+-	 * LVTS_HTHRE
++	 * LVTS_OFFSETH
+ 	 *
+ 	 * Bits:
+ 	 *
+@@ -323,7 +323,7 @@ static int lvts_set_trips(struct thermal
+ 	 */
+ 	pr_debug("%s: Setting high limit temperature interrupt: %d\n",
+ 		 thermal_zone_device_type(tz), high);
+-	writel(raw_high, LVTS_HTHRE(base));
++	writel(raw_high, LVTS_OFFSETH(base));
+ 
+ 	return 0;
+ }
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-32-thermal-drivers-mediatek-lvts_thermal-Disable-undesi.patch b/target/linux/mediatek/patches-6.1/830-v6.4-32-thermal-drivers-mediatek-lvts_thermal-Disable-undesi.patch
new file mode 100644
index 00000000000000..1c35d0ad1996a4
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-32-thermal-drivers-mediatek-lvts_thermal-Disable-undesi.patch
@@ -0,0 +1,51 @@
+From 8f8cab9d3e90acf1db278ef44ad05f10aefb973f Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?=
+ <nfraprado@collabora.com>
+Date: Thu, 6 Jul 2023 11:37:35 -0400
+Subject: [PATCH 28/42] thermal/drivers/mediatek/lvts_thermal: Disable
+ undesired interrupts
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Out of the many interrupts supported by the hardware, the only ones of
+interest to the driver currently are:
+* The temperature went over the high offset threshold, for any of the
+  sensors
+* The temperature went below the low offset threshold, for any of the
+  sensors
+* The temperature went over the stage3 threshold
+
+These are the only thresholds configured by the driver through the
+OFFSETH, OFFSETL, and PROTTC registers, respectively.
+
+The current interrupt mask in LVTS_MONINT_CONF, enables many more
+interrupts, including data ready on sensors for both filtered and
+immediate mode. These are not only not handled by the driver, but they
+are also triggered too often, causing unneeded overhead. Disable these
+unnecessary interrupts.
+
+The meaning of each bit can be seen in the comment describing
+LVTS_MONINTST in the IRQ handler.
+
+Fixes: f5f633b18234 ("thermal/drivers/mediatek: Add the Low Voltage Thermal Sensor driver")
+Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230706153823.201943-5-nfraprado@collabora.com
+---
+ drivers/thermal/mediatek/lvts_thermal.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -65,7 +65,7 @@
+ #define LVTS_HW_FILTER				0x2
+ #define LVTS_TSSEL_CONF				0x13121110
+ #define LVTS_CALSCALE_CONF			0x300
+-#define LVTS_MONINT_CONF			0x9FBF7BDE
++#define LVTS_MONINT_CONF			0x8300318C
+ 
+ #define LVTS_INT_SENSOR0			0x0009001F
+ #define LVTS_INT_SENSOR1			0x001203E0
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-33-thermal-drivers-mediatek-lvts_thermal-Don-t-leave-th.patch b/target/linux/mediatek/patches-6.1/830-v6.4-33-thermal-drivers-mediatek-lvts_thermal-Don-t-leave-th.patch
new file mode 100644
index 00000000000000..60942fdb895dd9
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-33-thermal-drivers-mediatek-lvts_thermal-Don-t-leave-th.patch
@@ -0,0 +1,70 @@
+From bd1ccf9408e6155564530af5e09b53ae497fe332 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?=
+ <nfraprado@collabora.com>
+Date: Thu, 6 Jul 2023 11:37:36 -0400
+Subject: [PATCH 29/42] thermal/drivers/mediatek/lvts_thermal: Don't leave
+ threshold zeroed
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The thermal framework might leave the low threshold unset if there
+aren't any lower trip points. This leaves the register zeroed, which
+translates to a very high temperature for the low threshold. The
+interrupt for this threshold is then immediately triggered, and the
+state machine gets stuck, preventing any other temperature monitoring
+interrupts to ever trigger.
+
+(The same happens by not setting the Cold or Hot to Normal thresholds
+when using those)
+
+Set the unused threshold to a valid low value. This value was chosen so
+that for any valid golden temperature read from the efuse, when the
+value is converted to raw and back again to milliCelsius, the result
+doesn't underflow.
+
+Fixes: f5f633b18234 ("thermal/drivers/mediatek: Add the Low Voltage Thermal Sensor driver")
+Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
+Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230706153823.201943-6-nfraprado@collabora.com
+---
+ drivers/thermal/mediatek/lvts_thermal.c | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -83,6 +83,8 @@
+ 
+ #define LVTS_HW_SHUTDOWN_MT8195		105000
+ 
++#define LVTS_MINIMUM_THRESHOLD		20000
++
+ static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT;
+ static int coeff_b = LVTS_COEFF_B;
+ 
+@@ -294,7 +296,7 @@ static int lvts_set_trips(struct thermal
+ {
+ 	struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz);
+ 	void __iomem *base = lvts_sensor->base;
+-	u32 raw_low = lvts_temp_to_raw(low);
++	u32 raw_low = lvts_temp_to_raw(low != -INT_MAX ? low : LVTS_MINIMUM_THRESHOLD);
+ 	u32 raw_high = lvts_temp_to_raw(high);
+ 
+ 	/*
+@@ -306,11 +308,9 @@ static int lvts_set_trips(struct thermal
+ 	 *
+ 	 * 14-0 : Raw temperature for threshold
+ 	 */
+-	if (low != -INT_MAX) {
+-		pr_debug("%s: Setting low limit temperature interrupt: %d\n",
+-			 thermal_zone_device_type(tz), low);
+-		writel(raw_low, LVTS_OFFSETL(base));
+-	}
++	pr_debug("%s: Setting low limit temperature interrupt: %d\n",
++		 thermal_zone_device_type(tz), low);
++	writel(raw_low, LVTS_OFFSETL(base));
+ 
+ 	/*
+ 	 * High offset temperature threshold
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-34-thermal-drivers-mediatek-lvts_thermal-Manage-thresho.patch b/target/linux/mediatek/patches-6.1/830-v6.4-34-thermal-drivers-mediatek-lvts_thermal-Manage-thresho.patch
new file mode 100644
index 00000000000000..e99aa0cdfd9b61
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-34-thermal-drivers-mediatek-lvts_thermal-Manage-thresho.patch
@@ -0,0 +1,156 @@
+From d4dd09968cab3249e6148e1c3fccb51824edb411 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?=
+ <nfraprado@collabora.com>
+Date: Thu, 6 Jul 2023 11:37:37 -0400
+Subject: [PATCH 30/42] thermal/drivers/mediatek/lvts_thermal: Manage threshold
+ between sensors
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Each LVTS thermal controller can have up to four sensors, each capable
+of triggering its own interrupt when its measured temperature crosses
+the configured threshold. The threshold for each sensor is handled
+separately by the thermal framework, since each one is registered with
+its own thermal zone and trips. However, the temperature thresholds are
+configured on the controller, and therefore are shared between all
+sensors on that controller.
+
+When the temperature measured by the sensors is different enough to
+cause the thermal framework to configure different thresholds for each
+one, interrupts start triggering on sensors outside the last threshold
+configured.
+
+To address the issue, track the thresholds required by each sensor and
+only actually set the highest one in the hardware, and disable
+interrupts for all sensors outside the current configured range.
+
+Fixes: f5f633b18234 ("thermal/drivers/mediatek: Add the Low Voltage Thermal Sensor driver")
+Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
+Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230706153823.201943-7-nfraprado@collabora.com
+---
+ drivers/thermal/mediatek/lvts_thermal.c | 69 +++++++++++++++++++++++++
+ 1 file changed, 69 insertions(+)
+
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -67,6 +67,11 @@
+ #define LVTS_CALSCALE_CONF			0x300
+ #define LVTS_MONINT_CONF			0x8300318C
+ 
++#define LVTS_MONINT_OFFSET_SENSOR0		0xC
++#define LVTS_MONINT_OFFSET_SENSOR1		0x180
++#define LVTS_MONINT_OFFSET_SENSOR2		0x3000
++#define LVTS_MONINT_OFFSET_SENSOR3		0x3000000
++
+ #define LVTS_INT_SENSOR0			0x0009001F
+ #define LVTS_INT_SENSOR1			0x001203E0
+ #define LVTS_INT_SENSOR2			0x00247C00
+@@ -112,6 +117,8 @@ struct lvts_sensor {
+ 	void __iomem *base;
+ 	int id;
+ 	int dt_id;
++	int low_thresh;
++	int high_thresh;
+ };
+ 
+ struct lvts_ctrl {
+@@ -121,6 +128,8 @@ struct lvts_ctrl {
+ 	int num_lvts_sensor;
+ 	int mode;
+ 	void __iomem *base;
++	int low_thresh;
++	int high_thresh;
+ };
+ 
+ struct lvts_domain {
+@@ -292,12 +301,66 @@ static int lvts_get_temp(struct thermal_
+ 	return 0;
+ }
+ 
++static void lvts_update_irq_mask(struct lvts_ctrl *lvts_ctrl)
++{
++	u32 masks[] = {
++		LVTS_MONINT_OFFSET_SENSOR0,
++		LVTS_MONINT_OFFSET_SENSOR1,
++		LVTS_MONINT_OFFSET_SENSOR2,
++		LVTS_MONINT_OFFSET_SENSOR3,
++	};
++	u32 value = 0;
++	int i;
++
++	value = readl(LVTS_MONINT(lvts_ctrl->base));
++
++	for (i = 0; i < ARRAY_SIZE(masks); i++) {
++		if (lvts_ctrl->sensors[i].high_thresh == lvts_ctrl->high_thresh
++		    && lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh)
++			value |= masks[i];
++		else
++			value &= ~masks[i];
++	}
++
++	writel(value, LVTS_MONINT(lvts_ctrl->base));
++}
++
++static bool lvts_should_update_thresh(struct lvts_ctrl *lvts_ctrl, int high)
++{
++	int i;
++
++	if (high > lvts_ctrl->high_thresh)
++		return true;
++
++	for (i = 0; i < lvts_ctrl->num_lvts_sensor; i++)
++		if (lvts_ctrl->sensors[i].high_thresh == lvts_ctrl->high_thresh
++		    && lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh)
++			return false;
++
++	return true;
++}
++
+ static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high)
+ {
+ 	struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz);
++	struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl, sensors[lvts_sensor->id]);
+ 	void __iomem *base = lvts_sensor->base;
+ 	u32 raw_low = lvts_temp_to_raw(low != -INT_MAX ? low : LVTS_MINIMUM_THRESHOLD);
+ 	u32 raw_high = lvts_temp_to_raw(high);
++	bool should_update_thresh;
++
++	lvts_sensor->low_thresh = low;
++	lvts_sensor->high_thresh = high;
++
++	should_update_thresh = lvts_should_update_thresh(lvts_ctrl, high);
++	if (should_update_thresh) {
++		lvts_ctrl->high_thresh = high;
++		lvts_ctrl->low_thresh = low;
++	}
++	lvts_update_irq_mask(lvts_ctrl);
++
++	if (!should_update_thresh)
++		return 0;
+ 
+ 	/*
+ 	 * Low offset temperature threshold
+@@ -521,6 +584,9 @@ static int lvts_sensor_init(struct devic
+ 		 */
+ 		lvts_sensor[i].msr = lvts_ctrl_data->mode == LVTS_MSR_IMMEDIATE_MODE ?
+ 			imm_regs[i] : msr_regs[i];
++
++		lvts_sensor[i].low_thresh = INT_MIN;
++		lvts_sensor[i].high_thresh = INT_MIN;
+ 	};
+ 
+ 	lvts_ctrl->num_lvts_sensor = lvts_ctrl_data->num_lvts_sensor;
+@@ -688,6 +754,9 @@ static int lvts_ctrl_init(struct device
+ 		 */
+ 		lvts_ctrl[i].hw_tshut_raw_temp =
+ 			lvts_temp_to_raw(lvts_data->lvts_ctrl[i].hw_tshut_temp);
++
++		lvts_ctrl[i].low_thresh = INT_MIN;
++		lvts_ctrl[i].high_thresh = INT_MIN;
+ 	}
+ 
+ 	/*
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-35-thermal-drivers-mediatek-lvts-Fix-parameter-check-in.patch b/target/linux/mediatek/patches-6.1/830-v6.4-35-thermal-drivers-mediatek-lvts-Fix-parameter-check-in.patch
new file mode 100644
index 00000000000000..9ce3eeb74b53c8
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-35-thermal-drivers-mediatek-lvts-Fix-parameter-check-in.patch
@@ -0,0 +1,29 @@
+From 5af4904adc8b840987000724977c13c706d3b7d8 Mon Sep 17 00:00:00 2001
+From: Minjie Du <duminjie@vivo.com>
+Date: Thu, 13 Jul 2023 12:24:12 +0800
+Subject: [PATCH 31/42] thermal/drivers/mediatek/lvts: Fix parameter check in
+ lvts_debugfs_init()
+
+The documentation says "If an error occurs, ERR_PTR(-ERROR) will be
+returned" but the current code checks against a NULL pointer returned.
+
+Fix this by checking if IS_ERR().
+
+Signed-off-by: Minjie Du <duminjie@vivo.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230713042413.2519-1-duminjie@vivo.com
+---
+ drivers/thermal/mediatek/lvts_thermal.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -201,7 +201,7 @@ static int lvts_debugfs_init(struct devi
+ 	int i;
+ 
+ 	lvts_td->dom_dentry = debugfs_create_dir(dev_name(dev), NULL);
+-	if (!lvts_td->dom_dentry)
++	if (IS_ERR(lvts_td->dom_dentry))
+ 		return 0;
+ 
+ 	for (i = 0; i < lvts_td->num_lvts_ctrl; i++) {
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-36-thermal-drivers-mediatek-Clean-up-redundant-dev_err_.patch b/target/linux/mediatek/patches-6.1/830-v6.4-36-thermal-drivers-mediatek-Clean-up-redundant-dev_err_.patch
new file mode 100644
index 00000000000000..4841054917577c
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-36-thermal-drivers-mediatek-Clean-up-redundant-dev_err_.patch
@@ -0,0 +1,33 @@
+From 6186be80317d1dbda34d35c06c084a083938f2d3 Mon Sep 17 00:00:00 2001
+From: Chen Jiahao <chenjiahao16@huawei.com>
+Date: Wed, 2 Aug 2023 17:45:27 +0800
+Subject: [PATCH 32/42] thermal/drivers/mediatek: Clean up redundant
+ dev_err_probe()
+
+Referring to platform_get_irq()'s definition, the return value has
+already been checked if ret < 0, and printed via dev_err_probe().
+Calling dev_err_probe() one more time outside platform_get_irq()
+is obviously redundant.
+
+Removing dev_err_probe() outside platform_get_irq() to clean up
+above problem.
+
+Signed-off-by: Chen Jiahao <chenjiahao16@huawei.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230802094527.988842-1-chenjiahao16@huawei.com
+---
+ drivers/thermal/mediatek/lvts_thermal.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -1216,7 +1216,7 @@ static int lvts_probe(struct platform_de
+ 
+ 	irq = platform_get_irq(pdev, 0);
+ 	if (irq < 0)
+-		return dev_err_probe(dev, irq, "No irq resource\n");
++		return irq;
+ 
+ 	ret = lvts_domain_init(dev, lvts_td, lvts_data);
+ 	if (ret)
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-37-thermal-drivers-mediatek-lvts_thermal-Make-readings-.patch b/target/linux/mediatek/patches-6.1/830-v6.4-37-thermal-drivers-mediatek-lvts_thermal-Make-readings-.patch
new file mode 100644
index 00000000000000..c88bf984fa7952
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-37-thermal-drivers-mediatek-lvts_thermal-Make-readings-.patch
@@ -0,0 +1,95 @@
+From c2ab54ab0425388e65901a7af2fbf69ead968708 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?=
+ <nfraprado@collabora.com>
+Date: Thu, 13 Jul 2023 11:42:37 -0400
+Subject: [PATCH 33/42] thermal/drivers/mediatek/lvts_thermal: Make readings
+ valid in filtered mode
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Currently, when a controller is configured to use filtered mode, thermal
+readings are valid only about 30% of the time.
+
+Upon testing, it was noticed that lowering any of the interval settings
+resulted in an improved rate of valid data. The same was observed when
+decreasing the number of samples for each sensor (which also results in
+quicker measurements).
+
+Retrying the read with a timeout longer than the time it takes to
+resample (about 344us with these settings and 4 sensors) also improves
+the rate.
+
+Lower all timing settings to the minimum, configure the filtering to
+single sample, and poll the measurement register for at least one period
+to improve the data validity on filtered mode.  With these changes in
+place, out of 100000 reads, a single one failed, ie 99.999% of the data
+was valid.
+
+Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
+Tested-by: Chen-Yu Tsai <wenst@chromium.org>
+Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
+Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230713154743.611870-1-nfraprado@collabora.com
+---
+ drivers/thermal/mediatek/lvts_thermal.c | 19 ++++++++++++-------
+ 1 file changed, 12 insertions(+), 7 deletions(-)
+
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -58,11 +58,11 @@
+ #define LVTS_PROTTC(__base)		(__base + 0x00CC)
+ #define LVTS_CLKEN(__base)		(__base + 0x00E4)
+ 
+-#define LVTS_PERIOD_UNIT			((118 * 1000) / (256 * 38))
+-#define LVTS_GROUP_INTERVAL			1
+-#define LVTS_FILTER_INTERVAL		1
+-#define LVTS_SENSOR_INTERVAL		1
+-#define LVTS_HW_FILTER				0x2
++#define LVTS_PERIOD_UNIT			0
++#define LVTS_GROUP_INTERVAL			0
++#define LVTS_FILTER_INTERVAL		0
++#define LVTS_SENSOR_INTERVAL		0
++#define LVTS_HW_FILTER				0x0
+ #define LVTS_TSSEL_CONF				0x13121110
+ #define LVTS_CALSCALE_CONF			0x300
+ #define LVTS_MONINT_CONF			0x8300318C
+@@ -86,6 +86,9 @@
+ #define LVTS_MSR_IMMEDIATE_MODE		0
+ #define LVTS_MSR_FILTERED_MODE		1
+ 
++#define LVTS_MSR_READ_TIMEOUT_US	400
++#define LVTS_MSR_READ_WAIT_US		(LVTS_MSR_READ_TIMEOUT_US / 2)
++
+ #define LVTS_HW_SHUTDOWN_MT8195		105000
+ 
+ #define LVTS_MINIMUM_THRESHOLD		20000
+@@ -268,6 +271,7 @@ static int lvts_get_temp(struct thermal_
+ 	struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz);
+ 	void __iomem *msr = lvts_sensor->msr;
+ 	u32 value;
++	int rc;
+ 
+ 	/*
+ 	 * Measurement registers:
+@@ -280,7 +284,8 @@ static int lvts_get_temp(struct thermal_
+ 	 * 16	: Valid temperature
+ 	 * 15-0	: Raw temperature
+ 	 */
+-	value = readl(msr);
++	rc = readl_poll_timeout(msr, value, value & BIT(16),
++				LVTS_MSR_READ_WAIT_US, LVTS_MSR_READ_TIMEOUT_US);
+ 
+ 	/*
+ 	 * As the thermal zone temperature will read before the
+@@ -293,7 +298,7 @@ static int lvts_get_temp(struct thermal_
+ 	 * functionning temperature and directly jump to a system
+ 	 * shutdown.
+ 	 */
+-	if (!(value & BIT(16)))
++	if (rc)
+ 		return -EAGAIN;
+ 
+ 	*temp = lvts_raw_to_temp(value & 0xFFFF);
diff --git a/target/linux/mediatek/patches-6.1/830-v6.6-38-thermal-drivers-mediatek-auxadc_thermal-Removed-call.patch b/target/linux/mediatek/patches-6.1/830-v6.6-38-thermal-drivers-mediatek-auxadc_thermal-Removed-call.patch
new file mode 100644
index 00000000000000..994461cdb161bc
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.6-38-thermal-drivers-mediatek-auxadc_thermal-Removed-call.patch
@@ -0,0 +1,30 @@
+From c864ff9de3b225b43bb8e08dedb223632323e059 Mon Sep 17 00:00:00 2001
+From: Andrei Coardos <aboutphysycs@gmail.com>
+Date: Fri, 11 Aug 2023 22:28:47 +0300
+Subject: [PATCH 34/42] thermal/drivers/mediatek/auxadc_thermal: Removed call
+ to platform_set_drvdata()
+
+This function call was found to be unnecessary as there is no equivalent
+platform_get_drvdata() call to access the private data of the driver. Also,
+the private data is defined in this driver, so there is no risk of it being
+accessed outside of this driver file.
+
+Signed-off-by: Andrei Coardos <aboutphysycs@gmail.com>
+Reviewed-by: Alexandru Ardelean <alex@shruggie.ro>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230811192847.3838-1-aboutphysycs@gmail.com
+---
+ drivers/thermal/mediatek/auxadc_thermal.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+--- a/drivers/thermal/mediatek/auxadc_thermal.c
++++ b/drivers/thermal/mediatek/auxadc_thermal.c
+@@ -1283,8 +1283,6 @@ static int mtk_thermal_probe(struct plat
+ 			mtk_thermal_init_bank(mt, i, apmixed_phys_base,
+ 					      auxadc_phys_base, ctrl_id);
+ 
+-	platform_set_drvdata(pdev, mt);
+-
+ 	tzdev = devm_thermal_of_zone_register(&pdev->dev, 0, mt,
+ 					      &mtk_thermal_ops);
+ 	if (IS_ERR(tzdev))
diff --git a/target/linux/mediatek/patches-6.1/830-v6.7-39-thermal-lvts-Convert-to-platform-remove-callback-ret.patch b/target/linux/mediatek/patches-6.1/830-v6.7-39-thermal-lvts-Convert-to-platform-remove-callback-ret.patch
new file mode 100644
index 00000000000000..b3bfa37458c8b9
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.7-39-thermal-lvts-Convert-to-platform-remove-callback-ret.patch
@@ -0,0 +1,58 @@
+From 6cf96078969ec00b873db99bae4e47001290685e Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
+Date: Wed, 27 Sep 2023 21:37:23 +0200
+Subject: [PATCH 35/42] thermal: lvts: Convert to platform remove callback
+ returning void
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The .remove() callback for a platform driver returns an int which makes
+many driver authors wrongly assume it's possible to do error handling by
+returning an error code. However the value returned is ignored (apart
+from emitting a warning) and this typically results in resource leaks.
+
+To improve here there is a quest to make the remove callback return
+void. In the first step of this quest all drivers are converted to
+.remove_new(), which already returns void. Eventually after all drivers
+are converted, .remove_new() will be renamed to .remove().
+
+Trivially convert this driver from always returning zero in the remove
+callback to the void returning variant.
+
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+---
+ drivers/thermal/mediatek/lvts_thermal.c | 6 ++----
+ 1 file changed, 2 insertions(+), 4 deletions(-)
+
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -1241,7 +1241,7 @@ static int lvts_probe(struct platform_de
+ 	return 0;
+ }
+ 
+-static int lvts_remove(struct platform_device *pdev)
++static void lvts_remove(struct platform_device *pdev)
+ {
+ 	struct lvts_domain *lvts_td;
+ 	int i;
+@@ -1252,8 +1252,6 @@ static int lvts_remove(struct platform_d
+ 		lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false);
+ 
+ 	lvts_debugfs_exit(lvts_td);
+-
+-	return 0;
+ }
+ 
+ static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = {
+@@ -1354,7 +1352,7 @@ MODULE_DEVICE_TABLE(of, lvts_of_match);
+ 
+ static struct platform_driver lvts_driver = {
+ 	.probe = lvts_probe,
+-	.remove = lvts_remove,
++	.remove_new = lvts_remove,
+ 	.driver = {
+ 		.name = "mtk-lvts-thermal",
+ 		.of_match_table = lvts_of_match,
diff --git a/target/linux/mediatek/patches-6.1/830-v6.7-40-thermal-drivers-mediatek-lvts_thermal-Make-coeff-con.patch b/target/linux/mediatek/patches-6.1/830-v6.7-40-thermal-drivers-mediatek-lvts_thermal-Make-coeff-con.patch
new file mode 100644
index 00000000000000..16a32f564bf352
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.7-40-thermal-drivers-mediatek-lvts_thermal-Make-coeff-con.patch
@@ -0,0 +1,198 @@
+From 26cc18a3d6d9eac21c4f4b4bb96147b2c6617c86 Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <frank-w@public-files.de>
+Date: Fri, 22 Sep 2023 07:50:19 +0200
+Subject: [PATCH 36/42] thermal/drivers/mediatek/lvts_thermal: Make coeff
+ configurable
+
+The upcoming mt7988 has different temperature coefficients so we
+cannot use constants in the functions lvts_golden_temp_init,
+lvts_golden_temp_init and lvts_raw_to_temp anymore.
+
+Add a field in the lvts_ctrl pointing to the lvts_data which now
+contains the soc-specific temperature coefficents.
+
+To make the code better readable, rename static int coeff_b to
+golden_temp_offset, COEFF_A to temp_factor and COEFF_B to temp_offset.
+
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Tested-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230922055020.6436-4-linux@fw-web.de
+---
+ drivers/thermal/mediatek/lvts_thermal.c | 51 ++++++++++++++++---------
+ 1 file changed, 34 insertions(+), 17 deletions(-)
+
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -80,8 +80,8 @@
+ #define LVTS_SENSOR_MAX				4
+ #define LVTS_GOLDEN_TEMP_MAX		62
+ #define LVTS_GOLDEN_TEMP_DEFAULT	50
+-#define LVTS_COEFF_A				-250460
+-#define LVTS_COEFF_B				250460
++#define LVTS_COEFF_A_MT8195			-250460
++#define LVTS_COEFF_B_MT8195			250460
+ 
+ #define LVTS_MSR_IMMEDIATE_MODE		0
+ #define LVTS_MSR_FILTERED_MODE		1
+@@ -94,7 +94,7 @@
+ #define LVTS_MINIMUM_THRESHOLD		20000
+ 
+ static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT;
+-static int coeff_b = LVTS_COEFF_B;
++static int golden_temp_offset;
+ 
+ struct lvts_sensor_data {
+ 	int dt_id;
+@@ -112,6 +112,8 @@ struct lvts_ctrl_data {
+ struct lvts_data {
+ 	const struct lvts_ctrl_data *lvts_ctrl;
+ 	int num_lvts_ctrl;
++	int temp_factor;
++	int temp_offset;
+ };
+ 
+ struct lvts_sensor {
+@@ -126,6 +128,7 @@ struct lvts_sensor {
+ 
+ struct lvts_ctrl {
+ 	struct lvts_sensor sensors[LVTS_SENSOR_MAX];
++	const struct lvts_data *lvts_data;
+ 	u32 calibration[LVTS_SENSOR_MAX];
+ 	u32 hw_tshut_raw_temp;
+ 	int num_lvts_sensor;
+@@ -247,21 +250,21 @@ static void lvts_debugfs_exit(struct lvt
+ 
+ #endif
+ 
+-static int lvts_raw_to_temp(u32 raw_temp)
++static int lvts_raw_to_temp(u32 raw_temp, int temp_factor)
+ {
+ 	int temperature;
+ 
+-	temperature = ((s64)(raw_temp & 0xFFFF) * LVTS_COEFF_A) >> 14;
+-	temperature += coeff_b;
++	temperature = ((s64)(raw_temp & 0xFFFF) * temp_factor) >> 14;
++	temperature += golden_temp_offset;
+ 
+ 	return temperature;
+ }
+ 
+-static u32 lvts_temp_to_raw(int temperature)
++static u32 lvts_temp_to_raw(int temperature, int temp_factor)
+ {
+-	u32 raw_temp = ((s64)(coeff_b - temperature)) << 14;
++	u32 raw_temp = ((s64)(golden_temp_offset - temperature)) << 14;
+ 
+-	raw_temp = div_s64(raw_temp, -LVTS_COEFF_A);
++	raw_temp = div_s64(raw_temp, -temp_factor);
+ 
+ 	return raw_temp;
+ }
+@@ -269,6 +272,9 @@ static u32 lvts_temp_to_raw(int temperat
+ static int lvts_get_temp(struct thermal_zone_device *tz, int *temp)
+ {
+ 	struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz);
++	struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl,
++						   sensors[lvts_sensor->id]);
++	const struct lvts_data *lvts_data = lvts_ctrl->lvts_data;
+ 	void __iomem *msr = lvts_sensor->msr;
+ 	u32 value;
+ 	int rc;
+@@ -301,7 +307,7 @@ static int lvts_get_temp(struct thermal_
+ 	if (rc)
+ 		return -EAGAIN;
+ 
+-	*temp = lvts_raw_to_temp(value & 0xFFFF);
++	*temp = lvts_raw_to_temp(value & 0xFFFF, lvts_data->temp_factor);
+ 
+ 	return 0;
+ }
+@@ -348,10 +354,13 @@ static bool lvts_should_update_thresh(st
+ static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high)
+ {
+ 	struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz);
+-	struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl, sensors[lvts_sensor->id]);
++	struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl,
++						   sensors[lvts_sensor->id]);
++	const struct lvts_data *lvts_data = lvts_ctrl->lvts_data;
+ 	void __iomem *base = lvts_sensor->base;
+-	u32 raw_low = lvts_temp_to_raw(low != -INT_MAX ? low : LVTS_MINIMUM_THRESHOLD);
+-	u32 raw_high = lvts_temp_to_raw(high);
++	u32 raw_low = lvts_temp_to_raw(low != -INT_MAX ? low : LVTS_MINIMUM_THRESHOLD,
++				       lvts_data->temp_factor);
++	u32 raw_high = lvts_temp_to_raw(high, lvts_data->temp_factor);
+ 	bool should_update_thresh;
+ 
+ 	lvts_sensor->low_thresh = low;
+@@ -692,7 +701,7 @@ static int lvts_calibration_read(struct
+ 	return 0;
+ }
+ 
+-static int lvts_golden_temp_init(struct device *dev, u32 *value)
++static int lvts_golden_temp_init(struct device *dev, u32 *value, int temp_offset)
+ {
+ 	u32 gt;
+ 
+@@ -701,7 +710,7 @@ static int lvts_golden_temp_init(struct
+ 	if (gt && gt < LVTS_GOLDEN_TEMP_MAX)
+ 		golden_temp = gt;
+ 
+-	coeff_b = golden_temp * 500 + LVTS_COEFF_B;
++	golden_temp_offset = golden_temp * 500 + temp_offset;
+ 
+ 	return 0;
+ }
+@@ -724,7 +733,7 @@ static int lvts_ctrl_init(struct device
+ 	 * The golden temp information is contained in the first chunk
+ 	 * of efuse data.
+ 	 */
+-	ret = lvts_golden_temp_init(dev, (u32 *)lvts_td->calib);
++	ret = lvts_golden_temp_init(dev, (u32 *)lvts_td->calib, lvts_data->temp_offset);
+ 	if (ret)
+ 		return ret;
+ 
+@@ -735,6 +744,7 @@ static int lvts_ctrl_init(struct device
+ 	for (i = 0; i < lvts_data->num_lvts_ctrl; i++) {
+ 
+ 		lvts_ctrl[i].base = lvts_td->base + lvts_data->lvts_ctrl[i].offset;
++		lvts_ctrl[i].lvts_data = lvts_data;
+ 
+ 		ret = lvts_sensor_init(dev, &lvts_ctrl[i],
+ 				       &lvts_data->lvts_ctrl[i]);
+@@ -758,7 +768,8 @@ static int lvts_ctrl_init(struct device
+ 		 * after initializing the calibration.
+ 		 */
+ 		lvts_ctrl[i].hw_tshut_raw_temp =
+-			lvts_temp_to_raw(lvts_data->lvts_ctrl[i].hw_tshut_temp);
++			lvts_temp_to_raw(lvts_data->lvts_ctrl[i].hw_tshut_temp,
++					 lvts_data->temp_factor);
+ 
+ 		lvts_ctrl[i].low_thresh = INT_MIN;
+ 		lvts_ctrl[i].high_thresh = INT_MIN;
+@@ -1223,6 +1234,8 @@ static int lvts_probe(struct platform_de
+ 	if (irq < 0)
+ 		return irq;
+ 
++	golden_temp_offset = lvts_data->temp_offset;
++
+ 	ret = lvts_domain_init(dev, lvts_td, lvts_data);
+ 	if (ret)
+ 		return dev_err_probe(dev, ret, "Failed to initialize the lvts domain\n");
+@@ -1336,11 +1349,15 @@ static const struct lvts_ctrl_data mt819
+ static const struct lvts_data mt8195_lvts_mcu_data = {
+ 	.lvts_ctrl	= mt8195_lvts_mcu_data_ctrl,
+ 	.num_lvts_ctrl	= ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl),
++	.temp_factor	= LVTS_COEFF_A_MT8195,
++	.temp_offset	= LVTS_COEFF_B_MT8195,
+ };
+ 
+ static const struct lvts_data mt8195_lvts_ap_data = {
+ 	.lvts_ctrl	= mt8195_lvts_ap_data_ctrl,
+ 	.num_lvts_ctrl	= ARRAY_SIZE(mt8195_lvts_ap_data_ctrl),
++	.temp_factor	= LVTS_COEFF_A_MT8195,
++	.temp_offset	= LVTS_COEFF_B_MT8195,
+ };
+ 
+ static const struct of_device_id lvts_of_match[] = {
diff --git a/target/linux/mediatek/patches-6.1/830-v6.7-41-dt-bindings-thermal-mediatek-Add-LVTS-thermal-sensor.patch b/target/linux/mediatek/patches-6.1/830-v6.7-41-dt-bindings-thermal-mediatek-Add-LVTS-thermal-sensor.patch
new file mode 100644
index 00000000000000..1c2146f43f91e5
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.7-41-dt-bindings-thermal-mediatek-Add-LVTS-thermal-sensor.patch
@@ -0,0 +1,35 @@
+From be2cc09bd5b46f13629d4fcdeac7ad1b18bb1a0b Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <frank-w@public-files.de>
+Date: Fri, 22 Sep 2023 07:50:18 +0200
+Subject: [PATCH] dt-bindings: thermal: mediatek: Add LVTS thermal sensors for
+ mt7988
+
+Add sensor constants for MT7988.
+
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Acked-by: Conor Dooley <conor.dooley@microchip.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230922055020.6436-3-linux@fw-web.de
+---
+ include/dt-bindings/thermal/mediatek,lvts-thermal.h | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+--- a/include/dt-bindings/thermal/mediatek,lvts-thermal.h
++++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h
+@@ -7,6 +7,15 @@
+ #ifndef __MEDIATEK_LVTS_DT_H
+ #define __MEDIATEK_LVTS_DT_H
+ 
++#define MT7988_CPU_0		0
++#define MT7988_CPU_1		1
++#define MT7988_ETH2P5G_0	2
++#define MT7988_ETH2P5G_1	3
++#define MT7988_TOPS_0		4
++#define MT7988_TOPS_1		5
++#define MT7988_ETHWARP_0	6
++#define MT7988_ETHWARP_1	7
++
+ #define MT8195_MCU_BIG_CPU0     0
+ #define MT8195_MCU_BIG_CPU1     1
+ #define MT8195_MCU_BIG_CPU2     2
diff --git a/target/linux/mediatek/patches-6.1/830-v6.7-42-thermal-drivers-mediatek-lvts_thermal-Add-mt7988-sup.patch b/target/linux/mediatek/patches-6.1/830-v6.7-42-thermal-drivers-mediatek-lvts_thermal-Add-mt7988-sup.patch
new file mode 100644
index 00000000000000..97c803a820bbe8
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.7-42-thermal-drivers-mediatek-lvts_thermal-Add-mt7988-sup.patch
@@ -0,0 +1,91 @@
+From 9924e9b91b43aaa1610a1d59c4caa43785948cf6 Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <frank-w@public-files.de>
+Date: Fri, 22 Sep 2023 07:50:20 +0200
+Subject: [PATCH 37/42] thermal/drivers/mediatek/lvts_thermal: Add mt7988
+ support
+
+Add Support for Mediatek Filogic 880/MT7988 LVTS.
+
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Tested-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230922055020.6436-5-linux@fw-web.de
+---
+ drivers/thermal/mediatek/lvts_thermal.c | 38 +++++++++++++++++++++++++
+ 1 file changed, 38 insertions(+)
+
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -82,6 +82,8 @@
+ #define LVTS_GOLDEN_TEMP_DEFAULT	50
+ #define LVTS_COEFF_A_MT8195			-250460
+ #define LVTS_COEFF_B_MT8195			250460
++#define LVTS_COEFF_A_MT7988			-204650
++#define LVTS_COEFF_B_MT7988			204650
+ 
+ #define LVTS_MSR_IMMEDIATE_MODE		0
+ #define LVTS_MSR_FILTERED_MODE		1
+@@ -89,6 +91,7 @@
+ #define LVTS_MSR_READ_TIMEOUT_US	400
+ #define LVTS_MSR_READ_WAIT_US		(LVTS_MSR_READ_TIMEOUT_US / 2)
+ 
++#define LVTS_HW_SHUTDOWN_MT7988		105000
+ #define LVTS_HW_SHUTDOWN_MT8195		105000
+ 
+ #define LVTS_MINIMUM_THRESHOLD		20000
+@@ -1267,6 +1270,33 @@ static void lvts_remove(struct platform_
+ 	lvts_debugfs_exit(lvts_td);
+ }
+ 
++static const struct lvts_ctrl_data mt7988_lvts_ap_data_ctrl[] = {
++	{
++		.cal_offset = { 0x00, 0x04, 0x08, 0x0c },
++		.lvts_sensor = {
++			{ .dt_id = MT7988_CPU_0 },
++			{ .dt_id = MT7988_CPU_1 },
++			{ .dt_id = MT7988_ETH2P5G_0 },
++			{ .dt_id = MT7988_ETH2P5G_1 }
++		},
++		.num_lvts_sensor = 4,
++		.offset = 0x0,
++		.hw_tshut_temp = LVTS_HW_SHUTDOWN_MT7988,
++	},
++	{
++		.cal_offset = { 0x14, 0x18, 0x1c, 0x20 },
++		.lvts_sensor = {
++			{ .dt_id = MT7988_TOPS_0},
++			{ .dt_id = MT7988_TOPS_1},
++			{ .dt_id = MT7988_ETHWARP_0},
++			{ .dt_id = MT7988_ETHWARP_1}
++		},
++		.num_lvts_sensor = 4,
++		.offset = 0x100,
++		.hw_tshut_temp = LVTS_HW_SHUTDOWN_MT7988,
++	}
++};
++
+ static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = {
+ 	{
+ 		.cal_offset = { 0x04, 0x07 },
+@@ -1346,6 +1376,13 @@ static const struct lvts_ctrl_data mt819
+ 	}
+ };
+ 
++static const struct lvts_data mt7988_lvts_ap_data = {
++	.lvts_ctrl	= mt7988_lvts_ap_data_ctrl,
++	.num_lvts_ctrl	= ARRAY_SIZE(mt7988_lvts_ap_data_ctrl),
++	.temp_factor	= LVTS_COEFF_A_MT7988,
++	.temp_offset	= LVTS_COEFF_B_MT7988,
++};
++
+ static const struct lvts_data mt8195_lvts_mcu_data = {
+ 	.lvts_ctrl	= mt8195_lvts_mcu_data_ctrl,
+ 	.num_lvts_ctrl	= ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl),
+@@ -1361,6 +1398,7 @@ static const struct lvts_data mt8195_lvt
+ };
+ 
+ static const struct of_device_id lvts_of_match[] = {
++	{ .compatible = "mediatek,mt7988-lvts-ap", .data = &mt7988_lvts_ap_data },
+ 	{ .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data },
+ 	{ .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data },
+ 	{},
diff --git a/target/linux/mediatek/patches-6.1/830-v6.7-43-thermal-drivers-mediatek-lvts_thermal-Fix-error-chec.patch b/target/linux/mediatek/patches-6.1/830-v6.7-43-thermal-drivers-mediatek-lvts_thermal-Fix-error-chec.patch
new file mode 100644
index 00000000000000..5b212a2a372ea4
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.7-43-thermal-drivers-mediatek-lvts_thermal-Fix-error-chec.patch
@@ -0,0 +1,30 @@
+From fb1bbb5b63e4e3c788a978724749ced57d208054 Mon Sep 17 00:00:00 2001
+From: Minjie Du <duminjie@vivo.com>
+Date: Thu, 21 Sep 2023 17:10:50 +0800
+Subject: [PATCH 38/42] thermal/drivers/mediatek/lvts_thermal: Fix error check
+ in lvts_debugfs_init()
+
+debugfs_create_dir() function returns an error value embedded in
+the pointer (PTR_ERR). Evaluate the return value using IS_ERR
+rather than checking for NULL.
+
+Signed-off-by: Minjie Du <duminjie@vivo.com>
+Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
+Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230921091057.3812-1-duminjie@vivo.com
+---
+ drivers/thermal/mediatek/lvts_thermal.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -219,7 +219,7 @@ static int lvts_debugfs_init(struct devi
+ 
+ 		sprintf(name, "controller%d", i);
+ 		dentry = debugfs_create_dir(name, lvts_td->dom_dentry);
+-		if (!dentry)
++		if (IS_ERR(dentry))
+ 			continue;
+ 
+ 		regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL);
diff --git a/target/linux/mediatek/patches-6.1/830-v6.7-44-thermal-drivers-mediatek-Fix-probe-for-THERMAL_V2.patch b/target/linux/mediatek/patches-6.1/830-v6.7-44-thermal-drivers-mediatek-Fix-probe-for-THERMAL_V2.patch
new file mode 100644
index 00000000000000..88f383c4aecc5b
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.7-44-thermal-drivers-mediatek-Fix-probe-for-THERMAL_V2.patch
@@ -0,0 +1,33 @@
+From e6f43063f2fe9f08b34797bc6d223f7d63b01910 Mon Sep 17 00:00:00 2001
+From: Markus Schneider-Pargmann <msp@baylibre.com>
+Date: Mon, 18 Sep 2023 12:07:06 +0200
+Subject: [PATCH 39/42] thermal/drivers/mediatek: Fix probe for THERMAL_V2
+
+Fix the probe function to call mtk_thermal_release_periodic_ts for
+everything != MTK_THERMAL_V1. This was accidentally changed from V1
+to V2 in the original patch.
+
+Reported-by: Frank Wunderlich <frank-w@public-files.de>
+Closes: https://lore.kernel.org/lkml/B0B3775B-B8D1-4284-814F-4F41EC22F532@public-files.de/
+Reported-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Closes: https://lore.kernel.org/lkml/07a569b9-e691-64ea-dd65-3b49842af33d@linaro.org/
+Fixes: 33140e668b10 ("thermal/drivers/mediatek: Control buffer enablement tweaks")
+Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230918100706.1229239-1-msp@baylibre.com
+---
+ drivers/thermal/mediatek/auxadc_thermal.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/thermal/mediatek/auxadc_thermal.c
++++ b/drivers/thermal/mediatek/auxadc_thermal.c
+@@ -1268,7 +1268,7 @@ static int mtk_thermal_probe(struct plat
+ 
+ 	mtk_thermal_turn_on_buffer(mt, apmixed_base);
+ 
+-	if (mt->conf->version != MTK_THERMAL_V2)
++	if (mt->conf->version != MTK_THERMAL_V1)
+ 		mtk_thermal_release_periodic_ts(mt, auxadc_base);
+ 
+ 	if (mt->conf->version == MTK_THERMAL_V1)
diff --git a/target/linux/mediatek/patches-6.1/830-v6.7-45-thermal-drivers-mediatek-lvts_thermal-Add-suspend-an.patch b/target/linux/mediatek/patches-6.1/830-v6.7-45-thermal-drivers-mediatek-lvts_thermal-Add-suspend-an.patch
new file mode 100644
index 00000000000000..7b4b124b561fcc
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.7-45-thermal-drivers-mediatek-lvts_thermal-Add-suspend-an.patch
@@ -0,0 +1,83 @@
+From a1d874ef3376295ee8ed89b3b5315f4c840ff00b Mon Sep 17 00:00:00 2001
+From: Balsam CHIHI <bchihi@baylibre.com>
+Date: Tue, 17 Oct 2023 21:05:42 +0200
+Subject: [PATCH 40/42] thermal/drivers/mediatek/lvts_thermal: Add suspend and
+ resume
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add suspend and resume support to LVTS driver.
+
+Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
+[bero@baylibre.com: suspend/resume in noirq phase]
+Co-developed-by: Bernhard Rosenkränzer <bero@baylibre.com>
+Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
+Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
+Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20231017190545.157282-3-bero@baylibre.com
+---
+ drivers/thermal/mediatek/lvts_thermal.c | 37 +++++++++++++++++++++++++
+ 1 file changed, 37 insertions(+)
+
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -1297,6 +1297,38 @@ static const struct lvts_ctrl_data mt798
+ 	}
+ };
+ 
++static int lvts_suspend(struct device *dev)
++{
++	struct lvts_domain *lvts_td;
++	int i;
++
++	lvts_td = dev_get_drvdata(dev);
++
++	for (i = 0; i < lvts_td->num_lvts_ctrl; i++)
++		lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false);
++
++	clk_disable_unprepare(lvts_td->clk);
++
++	return 0;
++}
++
++static int lvts_resume(struct device *dev)
++{
++	struct lvts_domain *lvts_td;
++	int i, ret;
++
++	lvts_td = dev_get_drvdata(dev);
++
++	ret = clk_prepare_enable(lvts_td->clk);
++	if (ret)
++		return ret;
++
++	for (i = 0; i < lvts_td->num_lvts_ctrl; i++)
++		lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], true);
++
++	return 0;
++}
++
+ static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = {
+ 	{
+ 		.cal_offset = { 0x04, 0x07 },
+@@ -1405,12 +1437,17 @@ static const struct of_device_id lvts_of
+ };
+ MODULE_DEVICE_TABLE(of, lvts_of_match);
+ 
++static const struct dev_pm_ops lvts_pm_ops = {
++	NOIRQ_SYSTEM_SLEEP_PM_OPS(lvts_suspend, lvts_resume)
++};
++
+ static struct platform_driver lvts_driver = {
+ 	.probe = lvts_probe,
+ 	.remove_new = lvts_remove,
+ 	.driver = {
+ 		.name = "mtk-lvts-thermal",
+ 		.of_match_table = lvts_of_match,
++		.pm = &lvts_pm_ops,
+ 	},
+ };
+ module_platform_driver(lvts_driver);
diff --git a/target/linux/mediatek/patches-6.1/830-v6.7-46-dt-bindings-thermal-mediatek-Add-LVTS-thermal-contro.patch b/target/linux/mediatek/patches-6.1/830-v6.7-46-dt-bindings-thermal-mediatek-Add-LVTS-thermal-contro.patch
new file mode 100644
index 00000000000000..c278168610f5e8
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.7-46-dt-bindings-thermal-mediatek-Add-LVTS-thermal-contro.patch
@@ -0,0 +1,49 @@
+From 0bb4937b58ab712f158588376dbac97f8e9df68e Mon Sep 17 00:00:00 2001
+From: Balsam CHIHI <bchihi@baylibre.com>
+Date: Tue, 17 Oct 2023 21:05:41 +0200
+Subject: [PATCH] dt-bindings: thermal: mediatek: Add LVTS thermal controller
+ definition for mt8192
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add LVTS thermal controller definition for MT8192.
+
+Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
+Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
+Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20231017190545.157282-2-bero@baylibre.com
+---
+ .../thermal/mediatek,lvts-thermal.h           | 19 +++++++++++++++++++
+ 1 file changed, 19 insertions(+)
+
+--- a/include/dt-bindings/thermal/mediatek,lvts-thermal.h
++++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h
+@@ -35,4 +35,23 @@
+ #define MT8195_AP_CAM0  15
+ #define MT8195_AP_CAM1  16
+ 
++#define MT8192_MCU_BIG_CPU0     0
++#define MT8192_MCU_BIG_CPU1     1
++#define MT8192_MCU_BIG_CPU2     2
++#define MT8192_MCU_BIG_CPU3     3
++#define MT8192_MCU_LITTLE_CPU0  4
++#define MT8192_MCU_LITTLE_CPU1  5
++#define MT8192_MCU_LITTLE_CPU2  6
++#define MT8192_MCU_LITTLE_CPU3  7
++
++#define MT8192_AP_VPU0  8
++#define MT8192_AP_VPU1  9
++#define MT8192_AP_GPU0  10
++#define MT8192_AP_GPU1  11
++#define MT8192_AP_INFRA 12
++#define MT8192_AP_CAM   13
++#define MT8192_AP_MD0   14
++#define MT8192_AP_MD1   15
++#define MT8192_AP_MD2   16
++
+ #endif /* __MEDIATEK_LVTS_DT_H */
diff --git a/target/linux/mediatek/patches-6.1/830-v6.7-47-thermal-drivers-mediatek-lvts_thermal-Add-mt8192-sup.patch b/target/linux/mediatek/patches-6.1/830-v6.7-47-thermal-drivers-mediatek-lvts_thermal-Add-mt8192-sup.patch
new file mode 100644
index 00000000000000..6d68a6cd5799c6
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.7-47-thermal-drivers-mediatek-lvts_thermal-Add-mt8192-sup.patch
@@ -0,0 +1,151 @@
+From 7d8b3864b38d881cf105328ff8569f47446811ad Mon Sep 17 00:00:00 2001
+From: Balsam CHIHI <bchihi@baylibre.com>
+Date: Tue, 17 Oct 2023 21:05:43 +0200
+Subject: [PATCH 41/42] thermal/drivers/mediatek/lvts_thermal: Add mt8192
+ support
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add LVTS Driver support for MT8192.
+
+Co-developed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
+Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
+Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
+Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
+[bero@baylibre.com: cosmetic changes, rebase]
+Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
+Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
+Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20231017190545.157282-4-bero@baylibre.com
+---
+ drivers/thermal/mediatek/lvts_thermal.c | 95 +++++++++++++++++++++++++
+ 1 file changed, 95 insertions(+)
+
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -92,6 +92,7 @@
+ #define LVTS_MSR_READ_WAIT_US		(LVTS_MSR_READ_TIMEOUT_US / 2)
+ 
+ #define LVTS_HW_SHUTDOWN_MT7988		105000
++#define LVTS_HW_SHUTDOWN_MT8192		105000
+ #define LVTS_HW_SHUTDOWN_MT8195		105000
+ 
+ #define LVTS_MINIMUM_THRESHOLD		20000
+@@ -1329,6 +1330,88 @@ static int lvts_resume(struct device *de
+ 	return 0;
+ }
+ 
++static const struct lvts_ctrl_data mt8192_lvts_mcu_data_ctrl[] = {
++	{
++		.cal_offset = { 0x04, 0x08 },
++		.lvts_sensor = {
++			{ .dt_id = MT8192_MCU_BIG_CPU0 },
++			{ .dt_id = MT8192_MCU_BIG_CPU1 }
++		},
++		.num_lvts_sensor = 2,
++		.offset = 0x0,
++		.hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
++		.mode = LVTS_MSR_FILTERED_MODE,
++	},
++	{
++		.cal_offset = { 0x0c, 0x10 },
++		.lvts_sensor = {
++			{ .dt_id = MT8192_MCU_BIG_CPU2 },
++			{ .dt_id = MT8192_MCU_BIG_CPU3 }
++		},
++		.num_lvts_sensor = 2,
++		.offset = 0x100,
++		.hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
++		.mode = LVTS_MSR_FILTERED_MODE,
++	},
++	{
++		.cal_offset = { 0x14, 0x18, 0x1c, 0x20 },
++		.lvts_sensor = {
++			{ .dt_id = MT8192_MCU_LITTLE_CPU0 },
++			{ .dt_id = MT8192_MCU_LITTLE_CPU1 },
++			{ .dt_id = MT8192_MCU_LITTLE_CPU2 },
++			{ .dt_id = MT8192_MCU_LITTLE_CPU3 }
++		},
++		.num_lvts_sensor = 4,
++		.offset = 0x200,
++		.hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
++		.mode = LVTS_MSR_FILTERED_MODE,
++	}
++};
++
++static const struct lvts_ctrl_data mt8192_lvts_ap_data_ctrl[] = {
++		{
++		.cal_offset = { 0x24, 0x28 },
++		.lvts_sensor = {
++			{ .dt_id = MT8192_AP_VPU0 },
++			{ .dt_id = MT8192_AP_VPU1 }
++		},
++		.num_lvts_sensor = 2,
++		.offset = 0x0,
++		.hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
++	},
++	{
++		.cal_offset = { 0x2c, 0x30 },
++		.lvts_sensor = {
++			{ .dt_id = MT8192_AP_GPU0 },
++			{ .dt_id = MT8192_AP_GPU1 }
++		},
++		.num_lvts_sensor = 2,
++		.offset = 0x100,
++		.hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
++	},
++	{
++		.cal_offset = { 0x34, 0x38 },
++		.lvts_sensor = {
++			{ .dt_id = MT8192_AP_INFRA },
++			{ .dt_id = MT8192_AP_CAM },
++		},
++		.num_lvts_sensor = 2,
++		.offset = 0x200,
++		.hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
++	},
++	{
++		.cal_offset = { 0x3c, 0x40, 0x44 },
++		.lvts_sensor = {
++			{ .dt_id = MT8192_AP_MD0 },
++			{ .dt_id = MT8192_AP_MD1 },
++			{ .dt_id = MT8192_AP_MD2 }
++		},
++		.num_lvts_sensor = 3,
++		.offset = 0x300,
++		.hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
++	}
++};
++
+ static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = {
+ 	{
+ 		.cal_offset = { 0x04, 0x07 },
+@@ -1415,6 +1498,16 @@ static const struct lvts_data mt7988_lvt
+ 	.temp_offset	= LVTS_COEFF_B_MT7988,
+ };
+ 
++static const struct lvts_data mt8192_lvts_mcu_data = {
++	.lvts_ctrl	= mt8192_lvts_mcu_data_ctrl,
++	.num_lvts_ctrl	= ARRAY_SIZE(mt8192_lvts_mcu_data_ctrl),
++};
++
++static const struct lvts_data mt8192_lvts_ap_data = {
++	.lvts_ctrl	= mt8192_lvts_ap_data_ctrl,
++	.num_lvts_ctrl	= ARRAY_SIZE(mt8192_lvts_ap_data_ctrl),
++};
++
+ static const struct lvts_data mt8195_lvts_mcu_data = {
+ 	.lvts_ctrl	= mt8195_lvts_mcu_data_ctrl,
+ 	.num_lvts_ctrl	= ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl),
+@@ -1431,6 +1524,8 @@ static const struct lvts_data mt8195_lvt
+ 
+ static const struct of_device_id lvts_of_match[] = {
+ 	{ .compatible = "mediatek,mt7988-lvts-ap", .data = &mt7988_lvts_ap_data },
++	{ .compatible = "mediatek,mt8192-lvts-mcu", .data = &mt8192_lvts_mcu_data },
++	{ .compatible = "mediatek,mt8192-lvts-ap", .data = &mt8192_lvts_ap_data },
+ 	{ .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data },
+ 	{ .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data },
+ 	{},
diff --git a/target/linux/mediatek/patches-6.1/830-v6.7-48-thermal-drivers-mediatek-lvts_thermal-Update-calibra.patch b/target/linux/mediatek/patches-6.1/830-v6.7-48-thermal-drivers-mediatek-lvts_thermal-Update-calibra.patch
new file mode 100644
index 00000000000000..c20c0b5f2e3dfe
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.7-48-thermal-drivers-mediatek-lvts_thermal-Update-calibra.patch
@@ -0,0 +1,70 @@
+From 5d126a3c87cf7964b28bacf3826eea4266265bce Mon Sep 17 00:00:00 2001
+From: Balsam CHIHI <bchihi@baylibre.com>
+Date: Tue, 17 Oct 2023 21:05:45 +0200
+Subject: [PATCH 42/42] thermal/drivers/mediatek/lvts_thermal: Update
+ calibration data documentation
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Update LVTS calibration data documentation for mt8192 and mt8195.
+
+Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
+Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
+[bero@baylibre.com: Fix issues pointed out by Nícolas F. R. A. Prado <nfraprado@collabora.com>]
+Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20231017190545.157282-6-bero@baylibre.com
+---
+ drivers/thermal/mediatek/lvts_thermal.c | 31 +++++++++++++++++++++++--
+ 1 file changed, 29 insertions(+), 2 deletions(-)
+
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -616,7 +616,34 @@ static int lvts_sensor_init(struct devic
+  * The efuse blob values follows the sensor enumeration per thermal
+  * controller. The decoding of the stream is as follow:
+  *
+- * stream index map for MCU Domain :
++ * MT8192 :
++ * Stream index map for MCU Domain mt8192 :
++ *
++ * <-----mcu-tc#0-----> <-----sensor#0----->        <-----sensor#1----->
++ *  0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 | 0x0A | 0x0B
++ *
++ * <-----sensor#2----->        <-----sensor#3----->
++ *  0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12 | 0x13
++ *
++ * <-----sensor#4----->        <-----sensor#5----->        <-----sensor#6----->        <-----sensor#7----->
++ *  0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21 | 0x22 | 0x23
++ *
++ * Stream index map for AP Domain mt8192 :
++ *
++ * <-----sensor#0----->        <-----sensor#1----->
++ *  0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A | 0x2B
++ *
++ * <-----sensor#2----->        <-----sensor#3----->
++ *  0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33
++ *
++ * <-----sensor#4----->        <-----sensor#5----->
++ *  0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B
++ *
++ * <-----sensor#6----->        <-----sensor#7----->        <-----sensor#8----->
++ *  0x3C | 0x3D | 0x3E | 0x3F | 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47
++ *
++ * MT8195 :
++ * Stream index map for MCU Domain mt8195 :
+  *
+  * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1----->
+  *  0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09
+@@ -627,7 +654,7 @@ static int lvts_sensor_init(struct devic
+  * <-----mcu-tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7----->
+  *  0x13 | 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21
+  *
+- * stream index map for AP Domain :
++ * Stream index map for AP Domain mt8195 :
+  *
+  * <-----ap--tc#0-----> <-----sensor#0-----> <-----sensor#1----->
+  *  0x22 | 0x23 | 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A
diff --git a/target/linux/mediatek/patches-6.1/831-thermal-drivers-mediatek-Fix-control-buffer-enablement-on-MT7896.patch b/target/linux/mediatek/patches-6.1/831-thermal-drivers-mediatek-Fix-control-buffer-enablement-on-MT7896.patch
new file mode 100644
index 00000000000000..fc173646e053f7
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/831-thermal-drivers-mediatek-Fix-control-buffer-enablement-on-MT7896.patch
@@ -0,0 +1,59 @@
+From patchwork Thu Sep  7 11:20:18 2023
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+X-Patchwork-Submitter: Frank Wunderlich <linux@fw-web.de>
+X-Patchwork-Id: 13376356
+From: Frank Wunderlich <linux@fw-web.de>
+To: linux-mediatek@lists.infradead.org
+Subject: [PATCH] thermal/drivers/mediatek: Fix control buffer enablement on
+ MT7896
+Date: Thu,  7 Sep 2023 13:20:18 +0200
+Message-Id: <20230907112018.52811-1-linux@fw-web.de>
+X-Mailer: git-send-email 2.34.1
+MIME-Version: 1.0
+X-Mail-ID: e7eeb8e1-00de-41f6-a5df-ce2e9164136e
+X-BeenThere: linux-mediatek@lists.infradead.org
+X-Mailman-Version: 2.1.34
+Precedence: list
+List-Id: <linux-mediatek.lists.infradead.org>
+Cc: Daniel Lezcano <daniel.lezcano@linaro.org>,
+ "Rafael J. Wysocki" <rafael@kernel.org>, linux-pm@vger.kernel.org,
+ Amit Kucheria <amitk@kernel.org>, Daniel Golle <daniel@makrotopia.org>,
+ stable@vger.kernel.org, linux-kernel@vger.kernel.org,
+ Matthias Brugger <matthias.bgg@gmail.com>, Zhang Rui <rui.zhang@intel.com>,
+ linux-arm-kernel@lists.infradead.org,
+ AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Sender: "Linux-mediatek" <linux-mediatek-bounces@lists.infradead.org>
+
+From: Frank Wunderlich <frank-w@public-files.de>
+
+Reading thermal sensor on mt7986 devices returns invalid temperature:
+
+bpi-r3 ~ # cat /sys/class/thermal/thermal_zone0/temp
+ -274000
+
+Fix this by adding missing members in mtk_thermal_data struct which were
+used in mtk_thermal_turn_on_buffer after commit 33140e668b10.
+
+Cc: stable@vger.kernel.org
+Fixes: 33140e668b10 ("thermal/drivers/mediatek: Control buffer enablement tweaks")
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Reviewed-by: Markus Schneider-Pargmann <msp@baylibre.com>
+---
+ drivers/thermal/mediatek/auxadc_thermal.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/drivers/thermal/mediatek/auxadc_thermal.c
++++ b/drivers/thermal/mediatek/auxadc_thermal.c
+@@ -691,6 +691,9 @@ static const struct mtk_thermal_data mt7
+ 	.adcpnp = mt7986_adcpnp,
+ 	.sensor_mux_values = mt7986_mux_values,
+ 	.version = MTK_THERMAL_V3,
++	.apmixed_buffer_ctl_reg = APMIXED_SYS_TS_CON1,
++	.apmixed_buffer_ctl_mask = GENMASK(31, 6) | BIT(3),
++	.apmixed_buffer_ctl_set = BIT(0),
+ };
+ 
+ static bool mtk_thermal_temp_is_valid(int temp)
diff --git a/target/linux/mediatek/patches-6.1/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch b/target/linux/mediatek/patches-6.1/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch
index 8e56be9ff44a72..6dede02003a4ea 100644
--- a/target/linux/mediatek/patches-6.1/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch
+++ b/target/linux/mediatek/patches-6.1/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch
@@ -1,6 +1,6 @@
 --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
 +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -310,7 +310,7 @@
+@@ -312,7 +312,7 @@
  	/* Attention: GPIO 90 is used to switch between PCIe@1,0 and
  	 * SATA functions. i.e. output-high: PCIe, output-low: SATA
  	 */
diff --git a/target/linux/mediatek/patches-6.1/901-arm-add-cmdline-override.patch b/target/linux/mediatek/patches-6.1/901-arm-add-cmdline-override.patch
index 72e4d1500950f8..bfca4b63894b50 100644
--- a/target/linux/mediatek/patches-6.1/901-arm-add-cmdline-override.patch
+++ b/target/linux/mediatek/patches-6.1/901-arm-add-cmdline-override.patch
@@ -37,7 +37,7 @@
  	 * CONFIG_CMDLINE is meant to be a default in case nothing else
 --- a/arch/arm64/Kconfig
 +++ b/arch/arm64/Kconfig
-@@ -2236,6 +2236,14 @@ config CMDLINE_FORCE
+@@ -2240,6 +2240,14 @@ config CMDLINE_FORCE
  
  endchoice
  
diff --git a/target/linux/mediatek/patches-6.1/910-dts-mt7622-bpi-r64-wifi-eeprom.patch b/target/linux/mediatek/patches-6.1/910-dts-mt7622-bpi-r64-wifi-eeprom.patch
index b6762e29ac02b4..09ce417c3512e0 100644
--- a/target/linux/mediatek/patches-6.1/910-dts-mt7622-bpi-r64-wifi-eeprom.patch
+++ b/target/linux/mediatek/patches-6.1/910-dts-mt7622-bpi-r64-wifi-eeprom.patch
@@ -1,6 +1,6 @@
 --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
 +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -637,5 +637,28 @@
+@@ -639,5 +639,28 @@
  };
  
  &wmac {
diff --git a/target/linux/mediatek/patches-6.1/911-dts-mt7622-bpi-r64-add-rootdisk.patch b/target/linux/mediatek/patches-6.1/911-dts-mt7622-bpi-r64-add-rootdisk.patch
new file mode 100644
index 00000000000000..5d3153ded4d897
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/911-dts-mt7622-bpi-r64-add-rootdisk.patch
@@ -0,0 +1,103 @@
+--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+@@ -32,6 +32,9 @@
+ 	chosen {
+ 		stdout-path = "serial0:115200n8";
+ 		bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
++		rootdisk-emmc = <&emmc_rootfs>;
++		rootdisk-sd = <&sd_rootfs>;
++		rootdisk-snfi = <&ubi_rootfs>;
+ 	};
+ 
+ 	cpus {
+@@ -233,6 +236,26 @@
+ 	assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
+ 	assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
+ 	non-removable;
++
++	card@0 {
++		compatible = "mmc-card";
++		reg = <0>;
++
++		block {
++			compatible = "block-device";
++			partitions {
++				block-partition-env {
++					partname = "ubootenv";
++					nvmem-layout {
++						compatible = "u-boot,env-layout";
++					};
++				};
++				emmc_rootfs: block-partition-production {
++					partname = "production";
++				};
++			};
++		};
++	};
+ };
+ 
+ &mmc1 {
+@@ -249,6 +272,26 @@
+ 	vqmmc-supply = <&reg_3p3v>;
+ 	assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
+ 	assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
++
++	card@0 {
++		compatible = "mmc-card";
++		reg = <0>;
++
++		block {
++			compatible = "block-device";
++			partitions {
++				block-partition-env {
++					partname = "ubootenv";
++					nvmem-layout {
++						compatible = "u-boot,env-layout";
++					};
++				};
++				sd_rootfs: block-partition-production {
++					partname = "production";
++				};
++			};
++		};
++	};
+ };
+ 
+ &nandc {
+@@ -283,14 +326,29 @@
+ 			};
+ 
+ 			partition@80000 {
+-				label = "fip";
+-				reg = <0x80000 0x200000>;
+-				read-only;
+-			};
+-
+-			ubi: partition@280000 {
+ 				label = "ubi";
+-				reg = <0x280000 0x7d80000>;
++				reg = <0x80000 0x7f80000>;
++				compatible = "linux,ubi";
++
++				volumes {
++					ubi-volume-ubootenv {
++						volname = "ubootenv";
++						nvmem-layout {
++							compatible = "u-boot,env-redundant-bool-layout";
++						};
++					};
++
++					ubi-volume-ubootenv2 {
++						volname = "ubootenv2";
++						nvmem-layout {
++							compatible = "u-boot,env-redundant-bool-layout";
++						};
++					};
++
++					ubi_rootfs: ubi-volume-fit {
++						volname = "fit";
++					};
++				};
+ 			};
+ 		};
+ 	};
diff --git a/target/linux/mediatek/patches-6.1/950-smartrg-i2c-led-driver.patch b/target/linux/mediatek/patches-6.1/950-smartrg-i2c-led-driver.patch
index a98cca19a56fbd..8b86c5042972d2 100644
--- a/target/linux/mediatek/patches-6.1/950-smartrg-i2c-led-driver.patch
+++ b/target/linux/mediatek/patches-6.1/950-smartrg-i2c-led-driver.patch
@@ -5,7 +5,7 @@
 
 --- a/drivers/leds/Kconfig
 +++ b/drivers/leds/Kconfig
-@@ -873,6 +873,16 @@ source "drivers/leds/flash/Kconfig"
+@@ -874,6 +874,16 @@ source "drivers/leds/flash/Kconfig"
  comment "RGB LED drivers"
  source "drivers/leds/rgb/Kconfig"
  
diff --git a/target/linux/mediatek/patches-6.1/961-net-ethernet-mediatek-split-tx-and-rx-fields-in-mtk_.patch b/target/linux/mediatek/patches-6.1/961-net-ethernet-mediatek-split-tx-and-rx-fields-in-mtk_.patch
index df37a61c237ff4..71cb3006ab8da0 100644
--- a/target/linux/mediatek/patches-6.1/961-net-ethernet-mediatek-split-tx-and-rx-fields-in-mtk_.patch
+++ b/target/linux/mediatek/patches-6.1/961-net-ethernet-mediatek-split-tx-and-rx-fields-in-mtk_.patch
@@ -15,7 +15,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1239,7 +1239,7 @@ static int mtk_init_fq_dma(struct mtk_et
+@@ -1264,7 +1264,7 @@ static int mtk_init_fq_dma(struct mtk_et
  		eth->scratch_ring = eth->sram_base;
  	else
  		eth->scratch_ring = dma_alloc_coherent(eth->dma_dev,
@@ -24,7 +24,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  						       &eth->phy_scratch_ring,
  						       GFP_KERNEL);
  	if (unlikely(!eth->scratch_ring))
-@@ -1255,16 +1255,16 @@ static int mtk_init_fq_dma(struct mtk_et
+@@ -1280,16 +1280,16 @@ static int mtk_init_fq_dma(struct mtk_et
  	if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr)))
  		return -ENOMEM;
  
@@ -44,7 +44,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  
  		txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE);
  		txd->txd4 = 0;
-@@ -1513,7 +1513,7 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -1538,7 +1538,7 @@ static int mtk_tx_map(struct sk_buff *sk
  	if (itxd == ring->last_free)
  		return -ENOMEM;
  
@@ -53,7 +53,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  	memset(itx_buf, 0, sizeof(*itx_buf));
  
  	txd_info.addr = dma_map_single(eth->dma_dev, skb->data, txd_info.size,
-@@ -1554,7 +1554,7 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -1579,7 +1579,7 @@ static int mtk_tx_map(struct sk_buff *sk
  
  			memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info));
  			txd_info.size = min_t(unsigned int, frag_size,
@@ -62,7 +62,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  			txd_info.qid = queue;
  			txd_info.last = i == skb_shinfo(skb)->nr_frags - 1 &&
  					!(frag_size - txd_info.size);
-@@ -1567,7 +1567,7 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -1592,7 +1592,7 @@ static int mtk_tx_map(struct sk_buff *sk
  			mtk_tx_set_dma_desc(dev, txd, &txd_info);
  
  			tx_buf = mtk_desc_to_tx_buf(ring, txd,
@@ -71,7 +71,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  			if (new_desc)
  				memset(tx_buf, 0, sizeof(*tx_buf));
  			tx_buf->data = (void *)MTK_DMA_DUMMY_DESC;
-@@ -1610,7 +1610,7 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -1635,7 +1635,7 @@ static int mtk_tx_map(struct sk_buff *sk
  	} else {
  		int next_idx;
  
@@ -80,7 +80,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  					 ring->dma_size);
  		mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0);
  	}
-@@ -1619,7 +1619,7 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -1644,7 +1644,7 @@ static int mtk_tx_map(struct sk_buff *sk
  
  err_dma:
  	do {
@@ -89,7 +89,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  
  		/* unmap dma */
  		mtk_tx_unmap(eth, tx_buf, NULL, false);
-@@ -1644,7 +1644,7 @@ static int mtk_cal_txd_req(struct mtk_et
+@@ -1669,7 +1669,7 @@ static int mtk_cal_txd_req(struct mtk_et
  		for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  			frag = &skb_shinfo(skb)->frags[i];
  			nfrags += DIV_ROUND_UP(skb_frag_size(frag),
@@ -98,7 +98,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  		}
  	} else {
  		nfrags += skb_shinfo(skb)->nr_frags;
-@@ -1785,7 +1785,7 @@ static struct mtk_rx_ring *mtk_get_rx_ri
+@@ -1810,7 +1810,7 @@ static struct mtk_rx_ring *mtk_get_rx_ri
  
  		ring = &eth->rx_ring[i];
  		idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
@@ -107,7 +107,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  		if (rxd->rxd2 & RX_DMA_DONE) {
  			ring->calc_idx_update = true;
  			return ring;
-@@ -1953,7 +1953,7 @@ static int mtk_xdp_submit_frame(struct m
+@@ -1978,7 +1978,7 @@ static int mtk_xdp_submit_frame(struct m
  	}
  	htxd = txd;
  
@@ -116,7 +116,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  	memset(tx_buf, 0, sizeof(*tx_buf));
  	htx_buf = tx_buf;
  
-@@ -1972,7 +1972,7 @@ static int mtk_xdp_submit_frame(struct m
+@@ -1997,7 +1997,7 @@ static int mtk_xdp_submit_frame(struct m
  				goto unmap;
  
  			tx_buf = mtk_desc_to_tx_buf(ring, txd,
@@ -125,7 +125,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  			memset(tx_buf, 0, sizeof(*tx_buf));
  			n_desc++;
  		}
-@@ -2010,7 +2010,7 @@ static int mtk_xdp_submit_frame(struct m
+@@ -2035,7 +2035,7 @@ static int mtk_xdp_submit_frame(struct m
  	} else {
  		int idx;
  
@@ -134,7 +134,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  		mtk_w32(eth, NEXT_DESP_IDX(idx, ring->dma_size),
  			MT7628_TX_CTX_IDX0);
  	}
-@@ -2021,7 +2021,7 @@ static int mtk_xdp_submit_frame(struct m
+@@ -2046,7 +2046,7 @@ static int mtk_xdp_submit_frame(struct m
  
  unmap:
  	while (htxd != txd) {
@@ -143,7 +143,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  		mtk_tx_unmap(eth, tx_buf, NULL, false);
  
  		htxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
-@@ -2152,7 +2152,7 @@ static int mtk_poll_rx(struct napi_struc
+@@ -2177,7 +2177,7 @@ static int mtk_poll_rx(struct napi_struc
  			goto rx_done;
  
  		idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
@@ -152,7 +152,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  		data = ring->data[idx];
  
  		if (!mtk_rx_get_desc(eth, &trxd, rxd))
-@@ -2287,7 +2287,7 @@ static int mtk_poll_rx(struct napi_struc
+@@ -2312,7 +2312,7 @@ static int mtk_poll_rx(struct napi_struc
  			rxdcsum = &trxd.rxd4;
  		}
  
@@ -161,7 +161,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  			skb->ip_summed = CHECKSUM_UNNECESSARY;
  		else
  			skb_checksum_none_assert(skb);
-@@ -2411,7 +2411,7 @@ static int mtk_poll_tx_qdma(struct mtk_e
+@@ -2436,7 +2436,7 @@ static int mtk_poll_tx_qdma(struct mtk_e
  			break;
  
  		tx_buf = mtk_desc_to_tx_buf(ring, desc,
@@ -170,7 +170,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  		if (!tx_buf->data)
  			break;
  
-@@ -2462,7 +2462,7 @@ static int mtk_poll_tx_pdma(struct mtk_e
+@@ -2487,7 +2487,7 @@ static int mtk_poll_tx_pdma(struct mtk_e
  		}
  		mtk_tx_unmap(eth, tx_buf, &bq, true);
  
@@ -179,7 +179,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  		ring->last_free = desc;
  		atomic_inc(&ring->free_count);
  
-@@ -2552,7 +2552,7 @@ static int mtk_napi_rx(struct napi_struc
+@@ -2577,7 +2577,7 @@ static int mtk_napi_rx(struct napi_struc
  	do {
  		int rx_done;
  
@@ -188,7 +188,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  			reg_map->pdma.irq_status);
  		rx_done = mtk_poll_rx(napi, budget - rx_done_total, eth);
  		rx_done_total += rx_done;
-@@ -2568,10 +2568,10 @@ static int mtk_napi_rx(struct napi_struc
+@@ -2593,10 +2593,10 @@ static int mtk_napi_rx(struct napi_struc
  			return budget;
  
  	} while (mtk_r32(eth, reg_map->pdma.irq_status) &
@@ -201,7 +201,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  
  	return rx_done_total;
  }
-@@ -2580,7 +2580,7 @@ static int mtk_tx_alloc(struct mtk_eth *
+@@ -2605,7 +2605,7 @@ static int mtk_tx_alloc(struct mtk_eth *
  {
  	const struct mtk_soc_data *soc = eth->soc;
  	struct mtk_tx_ring *ring = &eth->tx_ring;
@@ -210,7 +210,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  	struct mtk_tx_dma_v2 *txd;
  	int ring_size;
  	u32 ofs, val;
-@@ -2703,14 +2703,14 @@ static void mtk_tx_clean(struct mtk_eth
+@@ -2728,14 +2728,14 @@ static void mtk_tx_clean(struct mtk_eth
  	}
  	if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && ring->dma) {
  		dma_free_coherent(eth->dma_dev,
@@ -227,7 +227,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  				  ring->dma_pdma, ring->phys_pdma);
  		ring->dma_pdma = NULL;
  	}
-@@ -2765,15 +2765,15 @@ static int mtk_rx_alloc(struct mtk_eth *
+@@ -2790,15 +2790,15 @@ static int mtk_rx_alloc(struct mtk_eth *
  	if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM) ||
  	    rx_flag != MTK_RX_FLAGS_NORMAL) {
  		ring->dma = dma_alloc_coherent(eth->dma_dev,
@@ -247,7 +247,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  	}
  
  	if (!ring->dma)
-@@ -2784,7 +2784,7 @@ static int mtk_rx_alloc(struct mtk_eth *
+@@ -2809,7 +2809,7 @@ static int mtk_rx_alloc(struct mtk_eth *
  		dma_addr_t dma_addr;
  		void *data;
  
@@ -256,7 +256,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  		if (ring->page_pool) {
  			data = mtk_page_pool_get_buff(ring->page_pool,
  						      &dma_addr, GFP_KERNEL);
-@@ -2875,7 +2875,7 @@ static void mtk_rx_clean(struct mtk_eth
+@@ -2900,7 +2900,7 @@ static void mtk_rx_clean(struct mtk_eth
  			if (!ring->data[i])
  				continue;
  
@@ -265,7 +265,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  			if (!rxd->rxd1)
  				continue;
  
-@@ -2892,7 +2892,7 @@ static void mtk_rx_clean(struct mtk_eth
+@@ -2917,7 +2917,7 @@ static void mtk_rx_clean(struct mtk_eth
  
  	if (!in_sram && ring->dma) {
  		dma_free_coherent(eth->dma_dev,
@@ -274,7 +274,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  				  ring->dma, ring->phys);
  		ring->dma = NULL;
  	}
-@@ -3255,7 +3255,7 @@ static void mtk_dma_free(struct mtk_eth
+@@ -3280,7 +3280,7 @@ static void mtk_dma_free(struct mtk_eth
  			netdev_reset_queue(eth->netdev[i]);
  	if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && eth->scratch_ring) {
  		dma_free_coherent(eth->dma_dev,
@@ -283,7 +283,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  				  eth->scratch_ring, eth->phy_scratch_ring);
  		eth->scratch_ring = NULL;
  		eth->phy_scratch_ring = 0;
-@@ -3305,7 +3305,7 @@ static irqreturn_t mtk_handle_irq_rx(int
+@@ -3330,7 +3330,7 @@ static irqreturn_t mtk_handle_irq_rx(int
  
  	eth->rx_events++;
  	if (likely(napi_schedule_prep(&eth->rx_napi))) {
@@ -292,7 +292,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  		__napi_schedule(&eth->rx_napi);
  	}
  
-@@ -3331,9 +3331,9 @@ static irqreturn_t mtk_handle_irq(int ir
+@@ -3356,9 +3356,9 @@ static irqreturn_t mtk_handle_irq(int ir
  	const struct mtk_reg_map *reg_map = eth->soc->reg_map;
  
  	if (mtk_r32(eth, reg_map->pdma.irq_mask) &
@@ -304,7 +304,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  			mtk_handle_irq_rx(irq, _eth);
  	}
  	if (mtk_r32(eth, reg_map->tx_irq_mask) & MTK_TX_DONE_INT) {
-@@ -3351,10 +3351,10 @@ static void mtk_poll_controller(struct n
+@@ -3376,10 +3376,10 @@ static void mtk_poll_controller(struct n
  	struct mtk_eth *eth = mac->hw;
  
  	mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
@@ -317,7 +317,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  }
  #endif
  
-@@ -3517,7 +3517,7 @@ static int mtk_open(struct net_device *d
+@@ -3545,7 +3545,7 @@ static int mtk_open(struct net_device *d
  		napi_enable(&eth->tx_napi);
  		napi_enable(&eth->rx_napi);
  		mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
@@ -326,7 +326,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  		refcount_set(&eth->dma_refcnt, 1);
  	}
  	else
-@@ -3600,7 +3600,7 @@ static int mtk_stop(struct net_device *d
+@@ -3628,7 +3628,7 @@ static int mtk_stop(struct net_device *d
  	mtk_gdm_config(eth, MTK_GDMA_DROP_ALL);
  
  	mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
@@ -335,7 +335,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  	napi_disable(&eth->tx_napi);
  	napi_disable(&eth->rx_napi);
  
-@@ -4076,9 +4076,9 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -4107,9 +4107,9 @@ static int mtk_hw_init(struct mtk_eth *e
  
  	/* FE int grouping */
  	mtk_w32(eth, MTK_TX_DONE_INT, reg_map->pdma.int_grp);
@@ -347,7 +347,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  	mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
  
  	if (mtk_is_netsys_v3_or_greater(eth)) {
-@@ -5173,11 +5173,15 @@ static const struct mtk_soc_data mt2701_
+@@ -5270,11 +5270,15 @@ static const struct mtk_soc_data mt2701_
  	.required_clks = MT7623_CLKS_BITMAP,
  	.required_pctl = true,
  	.version = 1,
@@ -368,7 +368,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  		.dma_max_len = MTK_TX_DMA_BUF_LEN,
  		.dma_len_offset = 16,
  	},
-@@ -5193,11 +5197,15 @@ static const struct mtk_soc_data mt7621_
+@@ -5290,11 +5294,15 @@ static const struct mtk_soc_data mt7621_
  	.offload_version = 1,
  	.hash_offset = 2,
  	.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
@@ -389,7 +389,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  		.dma_max_len = MTK_TX_DMA_BUF_LEN,
  		.dma_len_offset = 16,
  	},
-@@ -5215,11 +5223,15 @@ static const struct mtk_soc_data mt7622_
+@@ -5312,11 +5320,15 @@ static const struct mtk_soc_data mt7622_
  	.hash_offset = 2,
  	.has_accounting = true,
  	.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
@@ -410,7 +410,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  		.dma_max_len = MTK_TX_DMA_BUF_LEN,
  		.dma_len_offset = 16,
  	},
-@@ -5236,11 +5248,15 @@ static const struct mtk_soc_data mt7623_
+@@ -5333,11 +5345,15 @@ static const struct mtk_soc_data mt7623_
  	.hash_offset = 2,
  	.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
  	.disable_pll_modes = true,
@@ -431,7 +431,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  		.dma_max_len = MTK_TX_DMA_BUF_LEN,
  		.dma_len_offset = 16,
  	},
-@@ -5255,11 +5271,15 @@ static const struct mtk_soc_data mt7629_
+@@ -5352,11 +5368,15 @@ static const struct mtk_soc_data mt7629_
  	.required_pctl = false,
  	.has_accounting = true,
  	.version = 1,
@@ -452,7 +452,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  		.dma_max_len = MTK_TX_DMA_BUF_LEN,
  		.dma_len_offset = 16,
  	},
-@@ -5277,11 +5297,15 @@ static const struct mtk_soc_data mt7981_
+@@ -5374,11 +5394,15 @@ static const struct mtk_soc_data mt7981_
  	.hash_offset = 4,
  	.has_accounting = true,
  	.foe_entry_size = MTK_FOE_ENTRY_V2_SIZE,
@@ -473,7 +473,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  		.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
  		.dma_len_offset = 8,
  	},
-@@ -5299,11 +5323,15 @@ static const struct mtk_soc_data mt7986_
+@@ -5396,11 +5420,15 @@ static const struct mtk_soc_data mt7986_
  	.hash_offset = 4,
  	.has_accounting = true,
  	.foe_entry_size = MTK_FOE_ENTRY_V2_SIZE,
@@ -494,7 +494,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  		.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
  		.dma_len_offset = 8,
  	},
-@@ -5321,11 +5349,15 @@ static const struct mtk_soc_data mt7988_
+@@ -5418,11 +5446,15 @@ static const struct mtk_soc_data mt7988_
  	.hash_offset = 4,
  	.has_accounting = true,
  	.foe_entry_size = MTK_FOE_ENTRY_V3_SIZE,
@@ -515,7 +515,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  		.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
  		.dma_len_offset = 8,
  	},
-@@ -5338,11 +5370,15 @@ static const struct mtk_soc_data rt5350_
+@@ -5435,11 +5467,15 @@ static const struct mtk_soc_data rt5350_
  	.required_clks = MT7628_CLKS_BITMAP,
  	.required_pctl = false,
  	.version = 1,
@@ -538,7 +538,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  	},
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -326,8 +326,8 @@
+@@ -327,8 +327,8 @@
  /* QDMA descriptor txd3 */
  #define TX_DMA_OWNER_CPU	BIT(31)
  #define TX_DMA_LS0		BIT(30)
@@ -549,7 +549,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  #define TX_DMA_SWC		BIT(14)
  #define TX_DMA_PQID		GENMASK(3, 0)
  #define TX_DMA_ADDR64_MASK	GENMASK(3, 0)
-@@ -347,8 +347,8 @@
+@@ -348,8 +348,8 @@
  /* QDMA descriptor rxd2 */
  #define RX_DMA_DONE		BIT(31)
  #define RX_DMA_LSO		BIT(30)
@@ -560,7 +560,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  #define RX_DMA_VTAG		BIT(15)
  #define RX_DMA_ADDR64_MASK	GENMASK(3, 0)
  #if IS_ENABLED(CONFIG_64BIT)
-@@ -1279,10 +1279,9 @@ struct mtk_reg_map {
+@@ -1209,10 +1209,9 @@ struct mtk_reg_map {
   * @foe_entry_size		Foe table entry size.
   * @has_accounting		Bool indicating support for accounting of
   *				offloaded flows.
@@ -574,7 +574,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
   * @dma_max_len			Max DMA tx/rx buffer length.
   * @dma_len_offset		Tx/Rx DMA length field offset.
   */
-@@ -1300,13 +1299,17 @@ struct mtk_soc_data {
+@@ -1230,13 +1229,17 @@ struct mtk_soc_data {
  	bool		has_accounting;
  	bool		disable_pll_modes;
  	struct {
diff --git a/target/linux/mediatek/patches-6.1/962-net-ethernet-mediatek-use-QDMA-instead-of-ADMAv2-on-.patch b/target/linux/mediatek/patches-6.1/962-net-ethernet-mediatek-use-QDMA-instead-of-ADMAv2-on-.patch
index 66c28eaaaa8689..8b7d5c0a1c904a 100644
--- a/target/linux/mediatek/patches-6.1/962-net-ethernet-mediatek-use-QDMA-instead-of-ADMAv2-on-.patch
+++ b/target/linux/mediatek/patches-6.1/962-net-ethernet-mediatek-use-QDMA-instead-of-ADMAv2-on-.patch
@@ -17,7 +17,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -108,16 +108,16 @@ static const struct mtk_reg_map mt7986_r
+@@ -110,16 +110,16 @@ static const struct mtk_reg_map mt7986_r
  	.tx_irq_mask		= 0x461c,
  	.tx_irq_status		= 0x4618,
  	.pdma = {
@@ -44,7 +44,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  	},
  	.qdma = {
  		.qtx_cfg	= 0x4400,
-@@ -1207,7 +1207,7 @@ static bool mtk_rx_get_desc(struct mtk_e
+@@ -1232,7 +1232,7 @@ static bool mtk_rx_get_desc(struct mtk_e
  	rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
  	rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
  	rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
@@ -53,7 +53,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  		rxd->rxd5 = READ_ONCE(dma_rxd->rxd5);
  		rxd->rxd6 = READ_ONCE(dma_rxd->rxd6);
  	}
-@@ -2159,7 +2159,7 @@ static int mtk_poll_rx(struct napi_struc
+@@ -2184,7 +2184,7 @@ static int mtk_poll_rx(struct napi_struc
  			break;
  
  		/* find out which mac the packet come from. values start at 1 */
@@ -62,7 +62,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  			u32 val = RX_DMA_GET_SPORT_V2(trxd.rxd5);
  
  			switch (val) {
-@@ -2271,7 +2271,7 @@ static int mtk_poll_rx(struct napi_struc
+@@ -2296,7 +2296,7 @@ static int mtk_poll_rx(struct napi_struc
  		skb->dev = netdev;
  		bytes += skb->len;
  
@@ -71,7 +71,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  			reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5);
  			hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY;
  			if (hash != MTK_RXD5_FOE_ENTRY)
-@@ -2821,7 +2821,7 @@ static int mtk_rx_alloc(struct mtk_eth *
+@@ -2846,7 +2846,7 @@ static int mtk_rx_alloc(struct mtk_eth *
  
  		rxd->rxd3 = 0;
  		rxd->rxd4 = 0;
@@ -80,7 +80,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  			rxd->rxd5 = 0;
  			rxd->rxd6 = 0;
  			rxd->rxd7 = 0;
-@@ -4022,7 +4022,7 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -4053,7 +4053,7 @@ static int mtk_hw_init(struct mtk_eth *e
  	else
  		mtk_hw_reset(eth);
  
@@ -89,7 +89,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  		/* Set FE to PDMAv2 if necessary */
  		val = mtk_r32(eth, MTK_FE_GLO_MISC);
  		mtk_w32(eth,  val | BIT(4), MTK_FE_GLO_MISC);
-@@ -5303,11 +5303,11 @@ static const struct mtk_soc_data mt7981_
+@@ -5400,11 +5400,11 @@ static const struct mtk_soc_data mt7981_
  		.dma_len_offset = 8,
  	},
  	.rx = {
@@ -105,7 +105,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  	},
  };
  
-@@ -5329,11 +5329,11 @@ static const struct mtk_soc_data mt7986_
+@@ -5426,11 +5426,11 @@ static const struct mtk_soc_data mt7986_
  		.dma_len_offset = 8,
  	},
  	.rx = {
diff --git a/target/linux/mpc85xx/files/arch/powerpc/boot/dts/br200-wp.dts b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/br200-wp.dts
index 39c3f137da699f..81364b9682bcc1 100644
--- a/target/linux/mpc85xx/files/arch/powerpc/boot/dts/br200-wp.dts
+++ b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/br200-wp.dts
@@ -293,14 +293,12 @@
 
 		led_attention: led-0 {
 			gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
-			label = "amber:status";
 			color = <LED_COLOR_ID_AMBER>;
 			function = LED_FUNCTION_STATUS;
 		};
 
 		led_status: led-1 {
 			gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
-			label = "white:status";
 			color = <LED_COLOR_ID_WHITE>;
 			function = LED_FUNCTION_STATUS;
 		};
diff --git a/target/linux/mpc85xx/files/arch/powerpc/boot/dts/firebox-t10.dts b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/firebox-t10.dts
index 89d8afe463a4a1..087138bbc2fc62 100644
--- a/target/linux/mpc85xx/files/arch/powerpc/boot/dts/firebox-t10.dts
+++ b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/firebox-t10.dts
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later or MIT
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/gpio/gpio.h>
 
 /include/ "fsl/p1010si-pre.dtsi"
@@ -36,7 +37,8 @@
 
 		status_red {
 			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 		};
 
 		led_mode: mode_green {
diff --git a/target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3715i.dts b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3715i.dts
index 764c8a31c8ae18..5d214e38a4e968 100644
--- a/target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3715i.dts
+++ b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3715i.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 /include/ "fsl/p1010si-pre.dtsi"
 
@@ -42,12 +43,14 @@
 
 		led_power_green: power_green {
 			gpios = <&spi_gpio 0 GPIO_ACTIVE_HIGH>;
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 		};
 
 		led_power_red: power_red {
 			gpios = <&spi_gpio 1 GPIO_ACTIVE_HIGH>;
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 		};
 
 		lan1_red {
diff --git a/target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3825i.dts b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3825i.dts
index bdc5e81df28c9c..30fae7f7d6a11a 100644
--- a/target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3825i.dts
+++ b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3825i.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Extreme Networks WS-AP3825i";
@@ -47,12 +48,14 @@
 
 		led_power_green: power_green {
 			gpios = <&spi_gpio 0 GPIO_ACTIVE_HIGH>;
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 		};
 
 		led_power_red: power_red {
 			gpios = <&spi_gpio 1 GPIO_ACTIVE_HIGH>;
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 		};
 
 		lan1_red {
diff --git a/target/linux/mvebu/Makefile b/target/linux/mvebu/Makefile
index 9f5d374abd9702..316bf1dfa001c1 100644
--- a/target/linux/mvebu/Makefile
+++ b/target/linux/mvebu/Makefile
@@ -9,8 +9,7 @@ BOARDNAME:=Marvell EBU Armada
 FEATURES:=fpu usb pci pcie gpio nand squashfs ramdisk boot-part rootfs-part legacy-sdcard targz
 SUBTARGETS:=cortexa9 cortexa53 cortexa72
 
-KERNEL_PATCHVER:=5.15
-KERNEL_TESTING_PATCHVER:=6.1
+KERNEL_PATCHVER:=6.1
 
 include $(INCLUDE_DIR)/target.mk
 
diff --git a/target/linux/mvebu/config-5.15 b/target/linux/mvebu/config-5.15
deleted file mode 100644
index 0811ee6d4ce082..00000000000000
--- a/target/linux/mvebu/config-5.15
+++ /dev/null
@@ -1,435 +0,0 @@
-CONFIG_AHCI_MVEBU=y
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_MVEBU=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM=y
-CONFIG_ARMADA_370_CLK=y
-CONFIG_ARMADA_370_XP_IRQ=y
-CONFIG_ARMADA_370_XP_TIMER=y
-# CONFIG_ARMADA_37XX_WATCHDOG is not set
-CONFIG_ARMADA_38X_CLK=y
-CONFIG_ARMADA_THERMAL=y
-CONFIG_ARMADA_XP_CLK=y
-CONFIG_ARM_APPENDED_DTB=y
-# CONFIG_ARM_ARMADA_37XX_CPUFREQ is not set
-# CONFIG_ARM_ARMADA_8K_CPUFREQ is not set
-CONFIG_ARM_ATAG_DTB_COMPAT=y
-# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set
-CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE=y
-CONFIG_ARM_CPU_SUSPEND=y
-CONFIG_ARM_CRYPTO=y
-CONFIG_ARM_ERRATA_720789=y
-CONFIG_ARM_ERRATA_764369=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_GLOBAL_TIMER=y
-CONFIG_ARM_GT_INITIAL_PRESCALER_VAL=1
-CONFIG_ARM_HAS_SG_CHAIN=y
-CONFIG_ARM_HEAVY_MB=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-CONFIG_ARM_MVEBU_V7_CPUIDLE=y
-CONFIG_ARM_PATCH_IDIV=y
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y
-CONFIG_ATA=y
-CONFIG_ATAGS=y
-CONFIG_ATA_LEDS=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_NVME=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BOUNCE=y
-# CONFIG_CACHE_FEROCEON_L2 is not set
-CONFIG_CACHE_L2X0=y
-CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CPUFREQ_DT=y
-CONFIG_CPUFREQ_DT_PLATDEV=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
-# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_PJ4B=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_SPECTRE=y
-CONFIG_CPU_THERMAL=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRC16=y
-CONFIG_CRYPTO_AES_ARM=y
-CONFIG_CRYPTO_AES_ARM_BS=y
-CONFIG_CRYPTO_AUTHENC=y
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_CRC32=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_CRYPTD=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_DES=y
-CONFIG_CRYPTO_DEV_MARVELL=y
-CONFIG_CRYPTO_DEV_MARVELL_CESA=y
-CONFIG_CRYPTO_ESSIV=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_LIB_DES=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_SHA1_ARM=y
-CONFIG_CRYPTO_SHA1_ARM_NEON=y
-CONFIG_CRYPTO_SHA256_ARM=y
-CONFIG_CRYPTO_SHA512_ARM=y
-CONFIG_CRYPTO_SIMD=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_ALIGN_RODATA=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_LL=y
-CONFIG_DEBUG_LL_INCLUDE="debug/8250.S"
-CONFIG_DEBUG_MVEBU_UART0=y
-# CONFIG_DEBUG_MVEBU_UART0_ALTERNATE is not set
-# CONFIG_DEBUG_MVEBU_UART1_ALTERNATE is not set
-CONFIG_DEBUG_UART_8250=y
-CONFIG_DEBUG_UART_8250_SHIFT=2
-CONFIG_DEBUG_UART_PHYS=0xd0012000
-CONFIG_DEBUG_UART_VIRT=0xfec12000
-CONFIG_DEBUG_UNCOMPRESS=y
-CONFIG_DEBUG_USER=y
-CONFIG_DMADEVICES=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_ENGINE_RAID=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_OPS=y
-CONFIG_DMA_REMAP=y
-CONFIG_DTC=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EXT4_FS=y
-CONFIG_EXTCON=y
-CONFIG_F2FS_FS=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MIGRATION=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GENERIC_VDSO_32=y
-CONFIG_GLOB=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_GENERIC=y
-CONFIG_GPIO_GENERIC_PLATFORM=y
-CONFIG_GPIO_MVEBU=y
-CONFIG_GPIO_PCA953X=y
-CONFIG_GPIO_PCA953X_IRQ=y
-CONFIG_GRO_CELLS=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDEN_BRANCH_PREDICTOR=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HAVE_SMP=y
-CONFIG_HIGHMEM=y
-CONFIG_HIGHPTE=y
-CONFIG_HOTPLUG_CPU=y
-CONFIG_HWBM=y
-CONFIG_HWMON=y
-CONFIG_HW_RANDOM=y
-CONFIG_HZ_FIXED=0
-CONFIG_HZ_PERIODIC=y
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_MV64XXX=y
-# CONFIG_I2C_PXA is not set
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-# CONFIG_IWMMXT is not set
-CONFIG_JBD2=y
-CONFIG_KMAP_LOCAL=y
-CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_PCA963X=y
-CONFIG_LEDS_TLC591XX=y
-CONFIG_LEDS_TRIGGER_DISK=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MACH_ARMADA_370=y
-# CONFIG_MACH_ARMADA_375 is not set
-CONFIG_MACH_ARMADA_38X=y
-# CONFIG_MACH_ARMADA_39X is not set
-CONFIG_MACH_ARMADA_XP=y
-# CONFIG_MACH_DOVE is not set
-CONFIG_MACH_MVEBU_ANY=y
-CONFIG_MACH_MVEBU_V7=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MANGLE_BOOTARGS=y
-CONFIG_MARVELL_PHY=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MDIO_I2C=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MEMORY=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_MVSDIO=y
-CONFIG_MMC_SDHCI=y
-# CONFIG_MMC_SDHCI_PCI is not set
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MMC_SDHCI_PXAV3=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MTD_CFI_STAA=y
-CONFIG_MTD_NAND_CORE=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_ECC_SW_HAMMING=y
-CONFIG_MTD_NAND_MARVELL=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_MVEBU_CLK_COMMON=y
-CONFIG_MVEBU_CLK_COREDIV=y
-CONFIG_MVEBU_CLK_CPU=y
-CONFIG_MVEBU_DEVBUS=y
-CONFIG_MVEBU_MBUS=y
-CONFIG_MVMDIO=y
-CONFIG_MVNETA=y
-CONFIG_MVNETA_BM=y
-CONFIG_MVNETA_BM_ENABLE=y
-# CONFIG_MVPP2 is not set
-CONFIG_MV_XOR=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEON=y
-CONFIG_NET_DEVLINK=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_MV88E6XXX=y
-CONFIG_NET_DSA_TAG_DSA=y
-CONFIG_NET_DSA_TAG_DSA_COMMON=y
-CONFIG_NET_DSA_TAG_EDSA=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NLS=y
-CONFIG_NOP_USB_XCEIV=y
-CONFIG_NR_CPUS=4
-CONFIG_NVMEM=y
-CONFIG_NVME_CORE=y
-# CONFIG_NVME_HWMON is not set
-# CONFIG_NVME_MULTIPATH is not set
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_ORION_WATCHDOG=y
-CONFIG_OUTER_CACHE=y
-CONFIG_OUTER_CACHE_SYNC=y
-CONFIG_PADATA=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PAGE_POOL=y
-CONFIG_PCI=y
-CONFIG_PCI_BRIDGE_EMUL=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PCI_MVEBU=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-# CONFIG_PHY_MVEBU_A3700_COMPHY is not set
-# CONFIG_PHY_MVEBU_A3700_UTMI is not set
-# CONFIG_PHY_MVEBU_A38X_COMPHY is not set
-# CONFIG_PHY_MVEBU_CP110_COMPHY is not set
-# CONFIG_PHY_MVEBU_CP110_UTMI is not set
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_ARMADA_370=y
-CONFIG_PINCTRL_ARMADA_38X=y
-CONFIG_PINCTRL_ARMADA_XP=y
-CONFIG_PINCTRL_MVEBU=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PJ4B_ERRATA_4742=y
-CONFIG_PL310_ERRATA_753970=y
-CONFIG_PLAT_ORION=y
-CONFIG_PM_OPP=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_GPIO=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PWM=y
-CONFIG_PWM_SYSFS=y
-CONFIG_RATIONAL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_ARMADA38X=y
-# CONFIG_RTC_DRV_MV is not set
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RTC_MC146818_LIB=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_SATA_AHCI_PLATFORM=y
-CONFIG_SATA_HOST=y
-CONFIG_SATA_MV=y
-CONFIG_SATA_PMP=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-CONFIG_SENSORS_PWM_FAN=y
-CONFIG_SENSORS_TMP421=y
-CONFIG_SERIAL_8250_DW=y
-CONFIG_SERIAL_8250_DWLIB=y
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_MVEBU_CONSOLE=y
-CONFIG_SERIAL_MVEBU_UART=y
-CONFIG_SFP=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SG_POOL=y
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SOC_BUS=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-# CONFIG_SPI_ARMADA_3700 is not set
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_ORION=y
-CONFIG_SRAM=y
-CONFIG_SRAM_EXEC=y
-CONFIG_SRCU=y
-CONFIG_SWPHY=y
-CONFIG_SWP_EMULATE=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_HWMON=y
-CONFIG_THERMAL_OF=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UBIFS_FS=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNWINDER_ARM=y
-CONFIG_USB=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_HCD_ORION=y
-CONFIG_USB_EHCI_HCD_PLATFORM=y
-CONFIG_USB_LEDS_TRIGGER_USBPORT=y
-CONFIG_USB_PHY=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_MVEBU=y
-CONFIG_USB_XHCI_PLATFORM=y
-CONFIG_USE_OF=y
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
diff --git a/target/linux/mvebu/cortexa53/config-5.15 b/target/linux/mvebu/cortexa53/config-5.15
deleted file mode 100644
index 27d410f68b915f..00000000000000
--- a/target/linux/mvebu/cortexa53/config-5.15
+++ /dev/null
@@ -1,83 +0,0 @@
-CONFIG_64BIT=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
-CONFIG_ARCH_MMAP_RND_BITS=18
-CONFIG_ARCH_MMAP_RND_BITS_MAX=24
-CONFIG_ARCH_MMAP_RND_BITS_MIN=18
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
-CONFIG_ARCH_PROC_KCORE_TEXT=y
-CONFIG_ARCH_STACKWALK=y
-CONFIG_ARCH_WANTS_NO_INSTR=y
-CONFIG_ARM64=y
-CONFIG_ARM64_4K_PAGES=y
-CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
-CONFIG_ARM64_PAGE_SHIFT=12
-CONFIG_ARM64_PA_BITS=48
-CONFIG_ARM64_PA_BITS_48=y
-CONFIG_ARM64_TAGGED_ADDR_ABI=y
-CONFIG_ARM64_VA_BITS=39
-CONFIG_ARM64_VA_BITS_39=y
-CONFIG_ARMADA_37XX_CLK=y
-CONFIG_ARMADA_37XX_RWTM_MBOX=y
-CONFIG_ARMADA_37XX_WATCHDOG=y
-CONFIG_ARMADA_AP806_SYSCON=y
-CONFIG_ARMADA_AP_CP_HELPER=y
-CONFIG_ARMADA_CP110_SYSCON=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_ARCH_TIMER=y
-# CONFIG_ARM_ARCH_TIMER_EVTSTREAM is not set
-CONFIG_ARM_ARMADA_37XX_CPUFREQ=y
-CONFIG_ARM_GIC_V2M=y
-CONFIG_ARM_GIC_V3=y
-CONFIG_ARM_GIC_V3_ITS=y
-CONFIG_ARM_GIC_V3_ITS_PCI=y
-# CONFIG_ARM_MHU_V2 is not set
-# CONFIG_ARM_PL172_MPMC is not set
-CONFIG_ARM_PSCI_FW=y
-CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
-CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_DMA_DIRECT_REMAP=y
-CONFIG_FRAME_POINTER=y
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_GENERIC_CSUM=y
-CONFIG_GENERIC_FIND_FIRST_BIT=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
-CONFIG_MAILBOX=y
-# CONFIG_MAILBOX_TEST is not set
-CONFIG_MFD_SYSCON=y
-CONFIG_MMC_SDHCI_XENON=y
-CONFIG_MODULES_USE_ELF_RELA=y
-CONFIG_MVEBU_GICP=y
-CONFIG_MVEBU_ICU=y
-CONFIG_MVEBU_ODMI=y
-CONFIG_MVEBU_PIC=y
-CONFIG_MVEBU_SEI=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-CONFIG_PARTITION_PERCPU=y
-CONFIG_PCI_AARDVARK=y
-CONFIG_PGTABLE_LEVELS=3
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_PHY_MVEBU_A3700_COMPHY=y
-CONFIG_PHY_MVEBU_A3700_UTMI=y
-CONFIG_PINCTRL_ARMADA_37XX=y
-CONFIG_PINCTRL_ARMADA_AP806=y
-CONFIG_PINCTRL_ARMADA_CP110=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_QUEUED_SPINLOCKS=y
-CONFIG_REGULATOR_GPIO=y
-CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
-CONFIG_SPARSEMEM=y
-CONFIG_SPARSEMEM_EXTREME=y
-CONFIG_SPARSEMEM_VMEMMAP=y
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_SPI_ARMADA_3700=y
-CONFIG_SWIOTLB=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TURRIS_MOX_RWTM=y
-CONFIG_UNMAP_KERNEL_AT_EL0=y
-CONFIG_VMAP_STACK=y
-CONFIG_ZONE_DMA32=y
diff --git a/target/linux/mvebu/cortexa72/base-files/etc/board.d/02_network b/target/linux/mvebu/cortexa72/base-files/etc/board.d/02_network
index 6a5861084e536f..93dadf491bbcb5 100644
--- a/target/linux/mvebu/cortexa72/base-files/etc/board.d/02_network
+++ b/target/linux/mvebu/cortexa72/base-files/etc/board.d/02_network
@@ -32,6 +32,9 @@ marvell,armada7040-db)
 marvell,armada8040-clearfog-gt-8k)
 	ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 eth2" "eth0 eth1"
 	;;
+solidrun,clearfog-pro)
+	ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 lan5 lan6 eth0 eth1" "eth2"
+	;;
 *)
 	ucidef_set_interface_lan "eth0"
 	;;
diff --git a/target/linux/mvebu/cortexa72/base-files/lib/upgrade/platform.sh b/target/linux/mvebu/cortexa72/base-files/lib/upgrade/platform.sh
index dc964a31176b4c..c7f20a6d7c7d6e 100755
--- a/target/linux/mvebu/cortexa72/base-files/lib/upgrade/platform.sh
+++ b/target/linux/mvebu/cortexa72/base-files/lib/upgrade/platform.sh
@@ -14,7 +14,8 @@ platform_check_image() {
 	iei,puzzle-m902|\
 	marvell,armada8040-mcbin-doubleshot|\
 	marvell,armada8040-mcbin-singleshot|\
-	marvell,armada8040-clearfog-gt-8k)
+	marvell,armada8040-clearfog-gt-8k|\
+	solidrun,clearfog-pro)
 		legacy_sdcard_check_image "$1"
 		;;
 	*)
@@ -32,7 +33,8 @@ platform_do_upgrade() {
 	globalscale,mochabin|\
 	marvell,armada8040-mcbin-doubleshot|\
 	marvell,armada8040-mcbin-singleshot|\
-	marvell,armada8040-clearfog-gt-8k)
+	marvell,armada8040-clearfog-gt-8k|\
+	solidrun,clearfog-pro)
 		legacy_sdcard_do_upgrade "$1"
 		;;
 	*)
@@ -47,7 +49,8 @@ platform_copy_config() {
 	iei,puzzle-m902|\
 	marvell,armada8040-mcbin-doubleshot|\
 	marvell,armada8040-mcbin-singleshot|\
-	marvell,armada8040-clearfog-gt-8k)
+	marvell,armada8040-clearfog-gt-8k|\
+	solidrun,clearfog-pro)
 		legacy_sdcard_copy_config
 		;;
 	esac
diff --git a/target/linux/mvebu/cortexa72/config-5.15 b/target/linux/mvebu/cortexa72/config-5.15
deleted file mode 100644
index 978208f1cb5a2a..00000000000000
--- a/target/linux/mvebu/cortexa72/config-5.15
+++ /dev/null
@@ -1,98 +0,0 @@
-CONFIG_64BIT=y
-CONFIG_AQUANTIA_PHY=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
-CONFIG_ARCH_MMAP_RND_BITS=18
-CONFIG_ARCH_MMAP_RND_BITS_MAX=24
-CONFIG_ARCH_MMAP_RND_BITS_MIN=18
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
-CONFIG_ARCH_PROC_KCORE_TEXT=y
-CONFIG_ARCH_STACKWALK=y
-CONFIG_ARCH_WANTS_NO_INSTR=y
-CONFIG_ARM64=y
-CONFIG_ARM64_4K_PAGES=y
-CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
-CONFIG_ARM64_ERRATUM_1742098=y
-CONFIG_ARM64_PAGE_SHIFT=12
-CONFIG_ARM64_PA_BITS=48
-CONFIG_ARM64_PA_BITS_48=y
-CONFIG_ARM64_SVE=y
-# CONFIG_ARM64_TAGGED_ADDR_ABI is not set
-CONFIG_ARM64_VA_BITS=39
-CONFIG_ARM64_VA_BITS_39=y
-CONFIG_ARMADA_37XX_CLK=y
-CONFIG_ARMADA_AP806_SYSCON=y
-CONFIG_ARMADA_AP_CPU_CLK=y
-CONFIG_ARMADA_AP_CP_HELPER=y
-CONFIG_ARMADA_CP110_SYSCON=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_ARCH_TIMER=y
-# CONFIG_ARM_ARCH_TIMER_EVTSTREAM is not set
-CONFIG_ARM_ARMADA_8K_CPUFREQ=y
-CONFIG_ARM_GIC_V2M=y
-CONFIG_ARM_GIC_V3=y
-CONFIG_ARM_GIC_V3_ITS=y
-CONFIG_ARM_GIC_V3_ITS_PCI=y
-# CONFIG_ARM_PL172_MPMC is not set
-CONFIG_ARM_PSCI_FW=y
-CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
-CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_DMA_DIRECT_REMAP=y
-CONFIG_FRAME_POINTER=y
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_GENERIC_CSUM=y
-CONFIG_GENERIC_FIND_FIRST_BIT=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_HW_RANDOM_OMAP=y
-CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
-CONFIG_LEDS_IEI_WT61P803_PUZZLE=y
-CONFIG_LEDS_IS31FL319X=y
-CONFIG_MARVELL_10G_PHY=y
-CONFIG_MFD_CORE=y
-CONFIG_MFD_IEI_WT61P803_PUZZLE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MMC_SDHCI_XENON=y
-CONFIG_MODULES_USE_ELF_RELA=y
-CONFIG_MVEBU_GICP=y
-CONFIG_MVEBU_ICU=y
-CONFIG_MVEBU_ODMI=y
-CONFIG_MVEBU_PIC=y
-CONFIG_MVEBU_SEI=y
-CONFIG_MVPP2=y
-CONFIG_MV_XOR_V2=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-CONFIG_PARTITION_PERCPU=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_ARMADA_8K=y
-CONFIG_PCIE_DW=y
-CONFIG_PCIE_DW_HOST=y
-# CONFIG_PCI_AARDVARK is not set
-CONFIG_PGTABLE_LEVELS=3
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_PHY_MVEBU_CP110_COMPHY=y
-CONFIG_PHY_MVEBU_CP110_UTMI=y
-CONFIG_PINCTRL_ARMADA_37XX=y
-CONFIG_PINCTRL_ARMADA_AP806=y
-CONFIG_PINCTRL_ARMADA_CP110=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_QUEUED_SPINLOCKS=y
-CONFIG_RAS=y
-# CONFIG_RAVE_SP_CORE is not set
-CONFIG_REGULATOR_GPIO=y
-# CONFIG_RODATA_FULL_DEFAULT_ENABLED is not set
-CONFIG_SENSORS_IEI_WT61P803_PUZZLE_HWMON=y
-CONFIG_SERIAL_DEV_BUS=y
-CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
-CONFIG_SPARSEMEM=y
-CONFIG_SPARSEMEM_EXTREME=y
-CONFIG_SPARSEMEM_VMEMMAP=y
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_SWIOTLB=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_UNMAP_KERNEL_AT_EL0=y
-CONFIG_VMAP_STACK=y
-CONFIG_ZONE_DMA32=y
diff --git a/target/linux/mvebu/cortexa72/config-6.1 b/target/linux/mvebu/cortexa72/config-6.1
index 535b67225e70b5..3c398dcd8fe3e8 100644
--- a/target/linux/mvebu/cortexa72/config-6.1
+++ b/target/linux/mvebu/cortexa72/config-6.1
@@ -41,7 +41,9 @@ CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
 CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
 CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
 CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CRC_CCITT=y
 CONFIG_DMA_DIRECT_REMAP=y
+CONFIG_EEPROM_AT24=y
 CONFIG_FRAME_POINTER=y
 CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS=y
 CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
@@ -66,6 +68,9 @@ CONFIG_MVEBU_SEI=y
 CONFIG_MVPP2=y
 CONFIG_MV_XOR_V2=y
 CONFIG_NEED_SG_DMA_LENGTH=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_NVMEM_LAYOUT_ONIE_TLV=y
+CONFIG_NVMEM_SYSFS=y
 CONFIG_PARTITION_PERCPU=y
 CONFIG_PCIEAER=y
 CONFIG_PCIEPORTBUS=y
@@ -74,6 +79,7 @@ CONFIG_PCIE_DW=y
 CONFIG_PCIE_DW_HOST=y
 # CONFIG_PCI_AARDVARK is not set
 CONFIG_PGTABLE_LEVELS=3
+CONFIG_PHYLIB_LEDS=y
 CONFIG_PHYS_ADDR_T_64BIT=y
 CONFIG_PHY_MVEBU_CP110_COMPHY=y
 CONFIG_PHY_MVEBU_CP110_UTMI=y
diff --git a/target/linux/mvebu/cortexa9/config-5.15 b/target/linux/mvebu/cortexa9/config-5.15
deleted file mode 100644
index 266596d6384e96..00000000000000
--- a/target/linux/mvebu/cortexa9/config-5.15
+++ /dev/null
@@ -1,7 +0,0 @@
-CONFIG_LED_TRIGGER_PHY=y
-CONFIG_MTD_SPLIT_SEIL_FW=y
-CONFIG_MTD_SPLIT_UIMAGE_FW=y
-CONFIG_MTD_VIRT_CONCAT=y
-CONFIG_PHY_MVEBU_A38X_COMPHY=y
-CONFIG_POWER_RESET_QNAP=y
-CONFIG_RTC_DRV_MV=y
diff --git a/target/linux/mvebu/files/arch/arm/boot/dts/armada-370-buffalo-ls220de.dts b/target/linux/mvebu/files/arch/arm/boot/dts/armada-370-buffalo-ls220de.dts
index 3de9ac5473e573..11be6a40286c1c 100644
--- a/target/linux/mvebu/files/arch/arm/boot/dts/armada-370-buffalo-ls220de.dts
+++ b/target/linux/mvebu/files/arch/arm/boot/dts/armada-370-buffalo-ls220de.dts
@@ -134,7 +134,6 @@
 		};
 
 		led_power: power_white {
-			label = "white:power";
 			function = LED_FUNCTION_POWER;
 			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
@@ -142,21 +141,18 @@
 		};
 
 		led_failsafe: power_red {
-			label = "red:power";
 			function = LED_FUNCTION_POWER;
 			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_upgrade: power_orange {
-			label = "amber:power";
 			function = LED_FUNCTION_POWER;
 			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_boot: indicator_white {
-			label = "white:indicator";
 			function = LED_FUNCTION_INDICATOR;
 			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
diff --git a/target/linux/mvebu/files/arch/arm/boot/dts/armada-370-c200-v2.dts b/target/linux/mvebu/files/arch/arm/boot/dts/armada-370-c200-v2.dts
index c1c227a5e91078..0d5ec567eab430 100644
--- a/target/linux/mvebu/files/arch/arm/boot/dts/armada-370-c200-v2.dts
+++ b/target/linux/mvebu/files/arch/arm/boot/dts/armada-370-c200-v2.dts
@@ -178,7 +178,6 @@
 		};
 
 		led_status_red: led-10 {
-			label = "red:status";
 			function = LED_FUNCTION_STATUS;
 			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
@@ -193,7 +192,6 @@
 		};
 
 		led_status_green: led-12 {
-			label = "green:status";
 			function = LED_FUNCTION_STATUS;
 			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio1 26 GPIO_ACTIVE_LOW>;
diff --git a/target/linux/mvebu/files/arch/arm/boot/dts/armada-380-iij-sa-w2.dts b/target/linux/mvebu/files/arch/arm/boot/dts/armada-380-iij-sa-w2.dts
index 09604e20176f90..335a2ecf96e840 100644
--- a/target/linux/mvebu/files/arch/arm/boot/dts/armada-380-iij-sa-w2.dts
+++ b/target/linux/mvebu/files/arch/arm/boot/dts/armada-380-iij-sa-w2.dts
@@ -66,71 +66,60 @@
 		pinctrl-0 = <&pmx_leds_pins>;
 
 		led-0 {
-			label = "green:wlan5g";
 			gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_GREEN>;
 			linux,default-trigger = "phy0tpt";
 		};
 
 		led-1 {
-			label = "red:wlan5g";
 			gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_RED>;
 		};
 
 		led-2 {
-			label = "green:status";
 			gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_STATUS;
 		};
 
 		led-3 {
-			label = "red:status";
 			gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_RED>;
 			function = LED_FUNCTION_STATUS;
 		};
 
 		led-4 {
-			label = "green:mobile";
 			gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_GREEN>;
 		};
 
 		led-5 {
-			label = "red:mobile";
 			gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_RED>;
 		};
 
 		led-6 {
-			label = "green:wlan2g";
 			gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_GREEN>;
 			linux,default-trigger = "phy1tpt";
 		};
 
 		led-7 {
-			label = "red:wlan2g";
 			gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_RED>;
 		};
 
 		led_power_green: led-8 {
-			label = "green:power";
 			gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
 			color = <LED_COLOR_ID_GREEN>;
 		};
 
 		led_power_red: led-9 {
-			label = "red:power";
 			gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_RED>;
 		};
 
 		led-10 {
-			label = "green:usb1";
 			gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;
 			color = <LED_COLOR_ID_GREEN>;
 			linux,default-trigger = "usbport";
@@ -138,7 +127,6 @@
 		};
 
 		led-11 {
-			label = "green:usb0";
 			gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
 			color = <LED_COLOR_ID_GREEN>;
 			linux,default-trigger = "usbport";
diff --git a/target/linux/mvebu/files/arch/arm/boot/dts/armada-385-fortinet-fg-30e.dts b/target/linux/mvebu/files/arch/arm/boot/dts/armada-385-fortinet-fg-30e.dts
index 8788f022f23fea..c0900d7126d7ce 100644
--- a/target/linux/mvebu/files/arch/arm/boot/dts/armada-385-fortinet-fg-30e.dts
+++ b/target/linux/mvebu/files/arch/arm/boot/dts/armada-385-fortinet-fg-30e.dts
@@ -14,14 +14,12 @@
 
 &gpio_leds {
 	led-14 {
-		label = "amber:speed_wan";
 		gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
 		color = <LED_COLOR_ID_AMBER>;
 		linux,default-trigger = "mv88e6xxx-1:00:100Mbps";
 	};
 
 	led-15 {
-		label = "green:speed_wan";
 		gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
 		color = <LED_COLOR_ID_GREEN>;
 		linux,default-trigger = "mv88e6xxx-1:00:1Gbps";
diff --git a/target/linux/mvebu/files/arch/arm/boot/dts/armada-385-fortinet-fg-50e.dts b/target/linux/mvebu/files/arch/arm/boot/dts/armada-385-fortinet-fg-50e.dts
index 4deca093c2dda9..d202d71c7f721d 100644
--- a/target/linux/mvebu/files/arch/arm/boot/dts/armada-385-fortinet-fg-50e.dts
+++ b/target/linux/mvebu/files/arch/arm/boot/dts/armada-385-fortinet-fg-50e.dts
@@ -14,28 +14,24 @@
 
 &gpio_leds {
 	led-14 {
-		label = "green:speed_wan1";
 		gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>;
 		color = <LED_COLOR_ID_GREEN>;
 		linux,default-trigger = "f1072004.mdio-mii:00:1Gbps";
 	};
 
 	led-15 {
-		label = "green:speed_wan2";
 		gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
 		color = <LED_COLOR_ID_GREEN>;
 		linux,default-trigger = "f1072004.mdio-mii:01:1Gbps";
 	};
 
 	led-16 {
-		label = "amber:speed_lan5";
 		gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
 		color = <LED_COLOR_ID_AMBER>;
 		linux,default-trigger = "mv88e6xxx-1:00:100Mbps";
 	};
 
 	led-17 {
-		label = "green:speed_lan5";
 		gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
 		color = <LED_COLOR_ID_GREEN>;
 		linux,default-trigger = "mv88e6xxx-1:00:1Gbps";
diff --git a/target/linux/mvebu/files/arch/arm/boot/dts/armada-385-fortinet-fg-x0e.dtsi b/target/linux/mvebu/files/arch/arm/boot/dts/armada-385-fortinet-fg-x0e.dtsi
index 91458299a209ec..8cc2d6bc4afc8a 100644
--- a/target/linux/mvebu/files/arch/arm/boot/dts/armada-385-fortinet-fg-x0e.dtsi
+++ b/target/linux/mvebu/files/arch/arm/boot/dts/armada-385-fortinet-fg-x0e.dtsi
@@ -46,96 +46,82 @@
 		pinctrl-0 = <&pmx_gpio_leds_pins>;
 
 		led-0 {
-			label = "red:alarm";
 			gpios = <&gpio0 30 GPIO_ACTIVE_LOW>;
 			color = <LED_COLOR_ID_RED>;
 			function = LED_FUNCTION_ALARM;
 		};
 
 		led-1 {
-			label = "red:ha";
 			gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
 			color = <LED_COLOR_ID_RED>;
 		};
 
 		led_status_green: led-2 {
-			label = "green:sta";
 			gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_STATUS;
 		};
 
 		led-3 {
-			label = "green:ha";
 			gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
 			color = <LED_COLOR_ID_GREEN>;
 		};
 
 		led-4 {
-			label = "amber:alarm";
 			gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
 			color = <LED_COLOR_ID_AMBER>;
 			function = LED_FUNCTION_ALARM;
 		};
 
 		led_status_red: led-5 {
-			label = "red:sta";
 			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
 			color = <LED_COLOR_ID_RED>;
 			function = LED_FUNCTION_STATUS;
 		};
 
 		led-6 {
-			label = "green:speed_lan4";
 			gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
 			color = <LED_COLOR_ID_GREEN>;
 			linux,default-trigger = "mv88e6xxx-1:01:1Gbps";
 		};
 
 		led-7 {
-			label = "amber:speed_lan4";
 			gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
 			color = <LED_COLOR_ID_AMBER>;
 			linux,default-trigger = "mv88e6xxx-1:01:100Mbps";
 		};
 
 		led-8 {
-			label = "amber:speed_lan3";
 			gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
 			color = <LED_COLOR_ID_AMBER>;
 			linux,default-trigger = "mv88e6xxx-1:02:100Mbps";
 		};
 
 		led-9 {
-			label = "green:speed_lan3";
 			gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
 			color = <LED_COLOR_ID_GREEN>;
 			linux,default-trigger = "mv88e6xxx-1:02:1Gbps";
 		};
 
 		led-10 {
-			label = "green:speed_lan1";
 			gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
 			color = <LED_COLOR_ID_GREEN>;
 			linux,default-trigger = "mv88e6xxx-1:04:1Gbps";
 		};
 
 		led-11 {
-			label = "amber:speed_lan1";
 			gpios = <&gpio2 13 GPIO_ACTIVE_LOW>;
 			color = <LED_COLOR_ID_AMBER>;
 			linux,default-trigger = "mv88e6xxx-1:04:100Mbps";
 		};
 
 		led-12 {
-			label = "green:speed_lan2";
 			gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
 			color = <LED_COLOR_ID_GREEN>;
 			linux,default-trigger = "mv88e6xxx-1:03:1Gbps";
 		};
 
 		led-13 {
-			label = "amber:speed_lan2";
 			gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
 			color = <LED_COLOR_ID_AMBER>;
 			linux,default-trigger = "mv88e6xxx-1:03:100Mbps";
diff --git a/target/linux/mvebu/files/arch/arm/boot/dts/armada-385-nas1dual.dts b/target/linux/mvebu/files/arch/arm/boot/dts/armada-385-nas1dual.dts
index 494487a8b410b2..f1fd72a93c961c 100644
--- a/target/linux/mvebu/files/arch/arm/boot/dts/armada-385-nas1dual.dts
+++ b/target/linux/mvebu/files/arch/arm/boot/dts/armada-385-nas1dual.dts
@@ -12,6 +12,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include "armada-385.dtsi"
 
 / {
@@ -86,7 +87,8 @@
 		};
 
 		usb {
-			label = "blue:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>;
 			trigger-sources = <&usb3_0_port1 &usb3_0_port2>;
 			linux,default-trigger = "usbport";
diff --git a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts
index 22dcbfac35fe04..07400fce3ae336 100644
--- a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts
+++ b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts
@@ -3,6 +3,7 @@
 /dts-v1/;
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include "armada-372x.dtsi"
 
 / {
@@ -63,12 +64,14 @@
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpionb 12 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpionb 13 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
diff --git a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9130-clearfog-pro.dts b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9130-clearfog-pro.dts
new file mode 100644
index 00000000000000..b5cc630781e593
--- /dev/null
+++ b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9130-clearfog-pro.dts
@@ -0,0 +1,513 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright SolidRun Ltd.
+ * Copyright (C) 2024 Tobias Schramm <tobias@t-sys.eu>
+ *
+ * Device tree for the CN9130-based ClearFog Pro
+ */
+
+#include "cn9130.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+	model = "SolidRun ClearFog Pro";
+	compatible = "solidrun,clearfog-pro", "marvell,armada-ap807-quad",
+		     "marvell,armada-ap807";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	aliases {
+		gpio1 = &cp0_gpio1;
+		gpio2 = &cp0_gpio2;
+		i2c0 = &cp0_i2c0;
+		ethernet0 = &cp0_eth0;
+		ethernet1 = &cp0_eth1;
+		ethernet2 = &cp0_eth2;
+		spi1 = &cp0_spi1;
+	};
+
+	memory@00000000 {
+		reg = <0x0 0x0 0x1 0x0>;
+		device_type = "memory";
+	};
+
+	/* Virtual regulator, root of power tree */
+	vin: regulator-vin {
+		compatible = "regulator-fixed";
+		regulator-name = "vin";
+		regulator-always-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	/* Regulators supplied by vin */
+	v_5v0: regulator-v_5v0 {
+		compatible = "regulator-fixed";
+		regulator-name = "v_5v0";
+		regulator-always-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vin>;
+	};
+
+	v_3v3: regulator-v_3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "v_3v3";
+		regulator-always-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vin>;
+	};
+
+	/* Regulators supplied by v_5v0 */
+	v_1v8: regulator-v_1v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "v_1v8";
+		regulator-always-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&v_5v0>;
+	};
+
+	v_5v0_usb3_hst_vbus: regulator-v_5v0_usb3_hst_vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "v_5v0_usb3_hst_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&expander0 6 GPIO_ACTIVE_LOW>;
+		vin-supply = <&v_5v0>;
+	};
+
+	/* Regulators internal to SOM */
+	vqmmc: regulator-vqmmc {
+		compatible = "regulator-fixed";
+		regulator-name = "vqmmc";
+		regulator-always-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&v_5v0>;
+	};
+
+	cp0_usb3_0_phy1: cp0_usb3_phy@1 {
+		compatible = "usb-nop-xceiv";
+		vbus-supply = <&v_5v0_usb3_hst_vbus>;
+	};
+
+	cp0_sfp_eth0: sfp-eth@0 {
+		compatible = "sff,sfp";
+		i2c-bus = <&cp0_i2c1>;
+		los-gpio = <&expander0 12 GPIO_ACTIVE_HIGH>;
+		mod-def0-gpio = <&expander0 15 GPIO_ACTIVE_LOW>;
+		tx-disable-gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
+		tx-fault-gpio = <&expander0 13 GPIO_ACTIVE_HIGH>;
+		maximum-power-milliwatt = <2000>;
+	};
+
+	keys {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&cp0_button_pin>;
+
+		reset {
+			label = "Reset";
+			linux,code = <KEY_RESTART>;
+			gpios = <&cp0_gpio2 0 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+/* on-board eMMC  */
+&ap_sdhci0 {
+	bus-width = <8>;
+	pinctrl-names = "default";
+	vqmmc-supply = <&vqmmc>;
+	status = "okay";
+};
+
+&cp0_crypto {
+	status = "okay";
+};
+
+&cp0_ethernet {
+	status = "okay";
+};
+
+&cp0_gpio1 {
+	status = "okay";
+};
+
+&cp0_gpio2 {
+	status = "okay";
+};
+
+&cp0_i2c0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&cp0_i2c0_pins>;
+	clock-frequency = <100000>;
+
+	/*
+	 * PCA9655 GPIO expander, up to 1MHz clock.
+	 *  0-CON3 CLKREQ#
+	 *  1-CON3 PERST#
+	 *  2-CON2 PERST#
+	 *  3-CON3 W_DISABLE
+	 *  4-CON2 CLKREQ#
+	 *  5-USB3 overcurrent
+	 *  6-USB3 power
+	 *  7-CON2 W_DISABLE
+	 *  8-JP4 P1
+	 *  9-JP4 P4
+	 * 10-JP4 P5
+	 * 11-m.2 DEVSLP
+	 * 12-SFP_LOS
+	 * 13-SFP_TX_FAULT
+	 * 14-SFP_TX_DISABLE
+	 * 15-SFP_MOD_DEF0
+	 */
+	expander0: gpio-expander@20 {
+		compatible = "nxp,pca9555";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&cp0_gpio1>;
+		interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&cp0_expander0_pins>;
+		vcc-supply = <&v_3v3>;
+
+		pcie1_0_clkreq {
+			gpio-hog;
+			gpios = <0 GPIO_ACTIVE_LOW>;
+			input;
+			line-name = "pcie1.0-clkreq";
+		};
+
+		pcie1_0_w_disable {
+			gpio-hog;
+			gpios = <3 GPIO_ACTIVE_LOW>;
+			output-low;
+			line-name = "pcie1.0-w-disable";
+		};
+
+		pcie2_0_clkreq {
+			gpio-hog;
+			gpios = <4 GPIO_ACTIVE_LOW>;
+			input;
+			line-name = "pcie2.0-clkreq";
+		};
+
+		pcie2_0_w_disable {
+			gpio-hog;
+			gpios = <7 GPIO_ACTIVE_LOW>;
+			output-low;
+			line-name = "pcie2.0-w-disable";
+		};
+
+		usb3_ilimit {
+			gpio-hog;
+			gpios = <5 GPIO_ACTIVE_LOW>;
+			input;
+			line-name = "usb3-current-limit";
+		};
+
+		m2_devslp {
+			gpio-hog;
+			gpios = <11 GPIO_ACTIVE_HIGH>;
+			output-low;
+			line-name = "m.2 devslp";
+		};
+	};
+
+	/* ADC only for mikroBUS connector */
+	mcp3021@4c {
+		compatible = "microchip,mcp3021";
+		reg = <0x4c>;
+	};
+
+	/* EEPROM on the SOM */
+	eeprom@53 {
+		compatible = "atmel,24c02";
+		reg = <0x53>;
+		pagesize = <16>;
+		read-only;
+
+		nvmem-layout {
+			compatible = "onie,tlv-layout";
+
+			onie_tlv_macaddr: mac-address {
+				#nvmem-cell-cells = <1>;
+			};
+		};
+	};
+};
+
+/* SMBUS on mini PCIe sockets */
+&cp0_i2c1 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&cp0_i2c1_pins>;
+	clock-frequency = <100000>;
+};
+
+&cp0_mdio {
+	status = "okay";
+
+	phy0: ethernet-phy@0 {
+		reg = <0>;
+		/* Green led blinks on activity, orange LED on link */
+		marvell,reg-init = <3 16 0 0x0064>;
+	};
+
+	switch@4 {
+		compatible = "marvell,mv88e6085";
+		reg = <4>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&cp0_gpio1>;
+		interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&cp0_dsa0_pins>;
+		reset-gpios = <&cp0_gpio1 27 GPIO_ACTIVE_LOW>;
+
+		mdio-external {
+			compatible = "marvell,mv88e6xxx-mdio-external";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/* 88E1512 PHY */
+			port6_phy: ethernet-phy@1 {
+				reg = <1>;
+			};
+		};
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				label = "lan5";
+			};
+
+			port@1 {
+				reg = <1>;
+				label = "lan4";
+			};
+
+			port@2 {
+				reg = <2>;
+				label = "lan3";
+			};
+
+			port@3 {
+				reg = <3>;
+				label = "lan2";
+			};
+
+			port@4 {
+				reg = <4>;
+				label = "lan1";
+			};
+
+			port@5 {
+				reg = <5>;
+				ethernet = <&cp0_eth1>;
+				label = "cpu";
+				phy-mode = "rgmii-id";
+
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+				};
+			};
+
+			port@6 {
+				/* 88E1512 external phy */
+				reg = <6>;
+				label = "lan6";
+				phy-handle = <&port6_phy>;
+				phy-mode = "rgmii-id";
+			};
+		};
+	};
+};
+
+/* SRDS #0 - SATA on bottom M.2 B-Key connector */
+&cp0_sata0 {
+	status = "okay";
+
+	sata-port@0 {
+		status = "disabled";
+	};
+
+	sata-port@1 {
+		phys = <&cp0_comphy0 1>;
+		target-supply = <&v_3v3>;
+	};
+};
+
+&cp0_utmi {
+	status = "okay";
+};
+
+/* mini PCIe slot far from SOM, USB 2.0 only, SS lanes unused */
+&cp0_usb3_0 {
+	status = "okay";
+	phys = <&cp0_utmi0>;
+	phy-names = "utmi";
+	dr_mode = "host";
+};
+
+/* SRDS #1 - USB-A 3.0 host port */
+&cp0_usb3_1 {
+	status = "okay";
+	phys = <&cp0_utmi1>, <&cp0_comphy1 0>;
+	phy-names = "utmi", "usb";
+	usb-phy = <&cp0_usb3_0_phy1>;
+	dr_mode = "host";
+};
+
+/* SRDS #2 - SFP+ 10GE */
+&cp0_eth0 {
+	status = "okay";
+	phy-mode = "10gbase-r";
+	phys = <&cp0_comphy2 0>;
+	managed = "in-band-status";
+	nvmem-cells = <&onie_tlv_macaddr 0>;
+	nvmem-cell-names = "mac-address";
+	sfp = <&cp0_sfp_eth0>;
+};
+
+/* SRDS #3 - SGMII 1GE to L2 switch */
+&cp0_eth1 {
+	status = "okay";
+	phys = <&cp0_comphy3 1>;
+	phy-mode = "sgmii";
+	nvmem-cells = <&onie_tlv_macaddr 1>;
+	nvmem-cell-names = "mac-address";
+
+	fixed-link {
+		speed = <1000>;
+		full-duplex;
+	};
+};
+
+/* SRDS #4 - mini PCIe slot near SOM */
+&cp0_pcie1 {
+	status = "okay";
+	phys = <&cp0_comphy4 1>;
+	num-lanes = <1>;
+	reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
+};
+
+/* SRDS #5 - mini PCIe slot far from SOM */
+&cp0_pcie2 {
+	status = "okay";
+	phys = <&cp0_comphy5 2>;
+	num-lanes = <1>;
+	reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
+};
+
+/* GE PHY RGMII */
+&cp0_eth2 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&cp0_ge2_rgmii_pins>;
+	phy = <&phy0>;
+	phy-mode = "rgmii-id";
+	nvmem-cells = <&onie_tlv_macaddr 2>;
+	nvmem-cell-names = "mac-address";
+};
+
+/* micro SD card slot */
+&cp0_sdhci0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&cp0_sdhci_pins &cp0_sdhci_cd_pins>;
+	bus-width = <4>;
+	cd-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>;
+	no-1-8-v;
+	vqmmc-supply = <&v_3v3>;
+	vmmc-supply = <&v_3v3>;
+};
+
+&cp0_spi1 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&cp0_spi1_pins>;
+
+	spi-flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0x0>;
+		#address-cells = <0x1>;
+		#size-cells = <0x1>;
+		spi-max-frequency = <10000000>;
+	};
+};
+
+&cp0_syscon0 {
+	cp0_pinctrl: pinctrl {
+		compatible = "marvell,cp115-standalone-pinctrl";
+
+		cp0_i2c0_pins: cp0-i2c0-pins {
+			marvell,pins = "mpp37", "mpp38";
+			marvell,function = "i2c0";
+		};
+
+		cp0_i2c1_pins: cp0-i2c1-pins {
+			marvell,pins = "mpp35", "mpp36";
+			marvell,function = "i2c1";
+		};
+
+		cp0_ge2_rgmii_pins: cp0-ge2-rgmii-pins {
+			marvell,pins = "mpp44", "mpp45", "mpp46",
+				       "mpp47", "mpp48", "mpp49",
+				       "mpp50", "mpp51", "mpp52",
+				       "mpp53", "mpp54", "mpp55";
+			marvell,function = "ge1";
+		};
+
+		cp0_sdhci_cd_pins: cp0-sdhci-cd-pins {
+			marvell,pins = "mpp43";
+			marvell,function = "sdio";
+		};
+
+		cp0_sdhci_pins: cp0-sdhci-pins {
+			marvell,pins = "mpp56", "mpp57", "mpp58",
+				       "mpp59", "mpp60", "mpp61";
+			marvell,function = "sdio";
+		};
+
+		cp0_spi1_pins: cp0-spi1-pins {
+			marvell,pins = "mpp12", "mpp13", "mpp14",
+				       "mpp15", "mpp16";
+			marvell,function = "spi1";
+		};
+
+		cp0_dsa0_pins: cp0-dsa0-pins {
+			marvell,pins = "mpp27", "mpp29";
+			marvell,function = "gpio";
+		};
+
+		cp0_button_pin: cp0-button-pin {
+			marvell,pins = "mpp32";
+			marvell,function = "gpio";
+		};
+
+		cp0_expander0_pins: cp0-expander0-pins {
+			marvell,pins = "mpp4";
+			marvell,function = "gpio";
+		};
+	};
+};
diff --git a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9131-puzzle-m901.dts b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9131-puzzle-m901.dts
index 5bc3a846e0d5f8..a33f8394ca649c 100644
--- a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9131-puzzle-m901.dts
+++ b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9131-puzzle-m901.dts
@@ -10,6 +10,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "iEi Puzzle-M901";
@@ -96,7 +97,8 @@
 
 			led_power: led@3 {
 				reg = <3>;
-				label = "yellow:power";
+				function = LED_FUNCTION_POWER;
+				color = <LED_COLOR_ID_YELLOW>;
 				active-low;
 				default-state = "on";
 			};
diff --git a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9132-puzzle-m902.dts b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9132-puzzle-m902.dts
index 671b592e67a744..4b153fdc8c483e 100644
--- a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9132-puzzle-m902.dts
+++ b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9132-puzzle-m902.dts
@@ -10,6 +10,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "iEi Puzzle-M902";
@@ -141,7 +142,8 @@
 
 			led_power: led@3 {
 				reg = <3>;
-				label = "yellow:power";
+				function = LED_FUNCTION_POWER;
+				color = <LED_COLOR_ID_YELLOW>;
 				active-low;
 				default-state = "on";
 			};
diff --git a/target/linux/mvebu/image/clearfog-pro.bootscript b/target/linux/mvebu/image/clearfog-pro.bootscript
new file mode 100644
index 00000000000000..2e152445eb02d6
--- /dev/null
+++ b/target/linux/mvebu/image/clearfog-pro.bootscript
@@ -0,0 +1,16 @@
+# Standard Boot-Script
+# use only well-known variable names provided by U-Boot Distro boot
+# This script assumes the boot partition to be partition 1
+# and that the root partition is always partition 2.
+# The vendor u-boot ships without setexpr compiled in.
+
+# figure out partition uuid to pass to the kernel as root=
+part uuid ${devtype} ${devnum}:2 uuid
+
+# generate bootargs (rootfs)
+setenv bootargs root=PARTUUID=${uuid} rootfstype=auto rootwait
+
+echo "Booting Linux with ${bootargs}"
+load ${devtype} ${devnum}:${distro_bootpart} ${fdt_addr_r} @DTB@.dtb
+load ${devtype} ${devnum}:${distro_bootpart} ${kernel_addr_r} Image
+booti ${kernel_addr_r} - ${fdt_addr_r}
diff --git a/target/linux/mvebu/image/cortexa72.mk b/target/linux/mvebu/image/cortexa72.mk
index 26b02e19247dcc..17904dc6c34986 100644
--- a/target/linux/mvebu/image/cortexa72.mk
+++ b/target/linux/mvebu/image/cortexa72.mk
@@ -80,3 +80,13 @@ define Device/iei_puzzle-m902
   DEVICE_PACKAGES += kmod-rtc-ds1307
 endef
 TARGET_DEVICES += iei_puzzle-m902
+
+define Device/solidrun_clearfog-pro
+  $(call Device/Default-arm64)
+  SOC := cn9130
+  DEVICE_VENDOR := SolidRun
+  DEVICE_MODEL := ClearFog Pro
+  DEVICE_PACKAGES += kmod-i2c-mux-pca954x
+  BOOT_SCRIPT := clearfog-pro
+endef
+TARGET_DEVICES += solidrun_clearfog-pro
diff --git a/target/linux/mvebu/image/cortexa9.mk b/target/linux/mvebu/image/cortexa9.mk
index a49401d904c64e..d97509f4d63021 100644
--- a/target/linux/mvebu/image/cortexa9.mk
+++ b/target/linux/mvebu/image/cortexa9.mk
@@ -104,7 +104,7 @@ define Device/cznic_turris-omnia
   DEVICE_PACKAGES :=  \
     mkf2fs e2fsprogs kmod-fs-vfat kmod-nls-cp437 kmod-nls-iso8859-1 \
     wpad-basic-mbedtls kmod-ath9k kmod-ath10k-ct ath10k-firmware-qca988x-ct \
-    partx-utils kmod-i2c-mux-pca954x kmod-leds-turris-omnia
+    kmod-mt7915-firmware partx-utils kmod-i2c-mux-pca954x kmod-leds-turris-omnia
   IMAGES := sysupgrade.img.gz
   IMAGE/sysupgrade.img.gz := boot-scr | boot-img | sdcard-img | gzip | append-metadata
   SUPPORTED_DEVICES += armada-385-turris-omnia
diff --git a/target/linux/mvebu/patches-5.15/100-ARM-dts-turris-omnia-configure-LED-0-pin-function-to.patch b/target/linux/mvebu/patches-5.15/100-ARM-dts-turris-omnia-configure-LED-0-pin-function-to.patch
deleted file mode 100644
index 67beb0654162a0..00000000000000
--- a/target/linux/mvebu/patches-5.15/100-ARM-dts-turris-omnia-configure-LED-0-pin-function-to.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From 81c0004a6433ff90fa6129418802c3c367e453c2 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>
-Date: Mon, 4 Jul 2022 13:36:21 +0200
-Subject: [PATCH 1/5] ARM: dts: turris-omnia: configure LED[0] pin function to
- link/activity
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The marvell PHY driver changes the LED[0] pin function to "On - 1000
-Mbps Link, Off - Else".
-
-Turris Omnia expects that the function is "On - Link, Blink - Activity,
-Off - No link".
-
-Use the `marvell,reg-init` DT property to change the function.
-
-In the future, once netdev trigger will support HW offloading, we will
-be able to have this configured via the combination of PHY driver and
-leds-turris-omnia driver.
-
-Signed-off-by: Marek Behún <kabel@kernel.org>
----
- arch/arm/boot/dts/armada-385-turris-omnia.dts | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
---- a/arch/arm/boot/dts/armada-385-turris-omnia.dts
-+++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts
-@@ -396,7 +396,8 @@
- 	phy1: ethernet-phy@1 {
- 		compatible = "ethernet-phy-ieee802.3-c22";
- 		reg = <1>;
--		marvell,reg-init = <3 18 0 0x4985>;
-+		marvell,reg-init = <3 18 0 0x4985>,
-+				   <3 16 0xfff0 0x0001>;
- 
- 		/* irq is connected to &pcawan pin 7 */
- 	};
diff --git a/target/linux/mvebu/patches-5.15/100-aardvark-workaround-PCIe.patch b/target/linux/mvebu/patches-5.15/100-aardvark-workaround-PCIe.patch
deleted file mode 100644
index 975eadb80e2746..00000000000000
--- a/target/linux/mvebu/patches-5.15/100-aardvark-workaround-PCIe.patch
+++ /dev/null
@@ -1,81 +0,0 @@
-Subject: [PATCH v2] PCI: aardvark: Implement workaround for PCIe Completion Timeout
-Date:   Tue,  2 Aug 2022 14:38:16 +0200
-Message-Id: <20220802123816.21817-1-pali@kernel.org>
-X-Mailer: git-send-email 2.20.1
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-Precedence: bulk
-List-ID: <linux-pci.vger.kernel.org>
-X-Mailing-List: linux-pci@vger.kernel.org
-
-Marvell Armada 3700 Functional Errata, Guidelines, and Restrictions
-document describes in erratum 3.12 PCIe Completion Timeout (Ref #: 251),
-that PCIe IP does not support a strong-ordered model for inbound posted vs.
-outbound completion.
-
-As a workaround for this erratum, DIS_ORD_CHK flag in Debug Mux Control
-register must be set. It disables the ordering check in the core between
-Completions and Posted requests received from the link.
-
-Marvell also suggests to do full memory barrier at the beginning of
-aardvark summary interrupt handler before calling interrupt handlers of
-endpoint drivers in order to minimize the risk for the race condition
-documented in the Erratum between the DMA done status reading and the
-completion of writing to the host memory.
-
-More details about this issue and suggested workarounds are in discussion:
-https://lore.kernel.org/linux-pci/BN9PR18MB425154FE5019DCAF2028A1D5DB8D9@BN9PR18MB4251.namprd18.prod.outlook.com/t/#u
-
-It was reported that enabling this workaround fixes instability issues and
-"Unhandled fault" errors when using 60 GHz WiFi 802.11ad card with Qualcomm
-QCA6335 chip under significant load which were caused by interrupt status
-stuck in the outbound CMPLT queue traced back to this erratum.
-
-This workaround fixes also kernel panic triggered after some minutes of
-usage 5 GHz WiFi 802.11ax card with Mediatek MT7915 chip:
-
-    Internal error: synchronous external abort: 96000210 [#1] SMP
-    Kernel panic - not syncing: Fatal exception in interrupt
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
-Signed-off-by: Pali Rohár <pali@kernel.org>
-Fixes: 8c39d710363c ("PCI: aardvark: Add Aardvark PCI host controller driver")
-Cc: stable@vger.kernel.org
----
- drivers/pci/controller/pci-aardvark.c | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
---- a/drivers/pci/controller/pci-aardvark.c
-+++ b/drivers/pci/controller/pci-aardvark.c
-@@ -210,6 +210,8 @@ enum {
- };
- 
- #define VENDOR_ID_REG				(LMI_BASE_ADDR + 0x44)
-+#define DEBUG_MUX_CTRL_REG			(LMI_BASE_ADDR + 0x208)
-+#define     DIS_ORD_CHK				BIT(30)
- 
- /* PCIe core controller registers */
- #define CTRL_CORE_BASE_ADDR			0x18000
-@@ -558,6 +560,11 @@ static void advk_pcie_setup_hw(struct ad
- 		PCIE_CORE_CTRL2_TD_ENABLE;
- 	advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
- 
-+	/* Disable ordering checks, workaround for erratum 3.12 "PCIe completion timeout" */
-+	reg = advk_readl(pcie, DEBUG_MUX_CTRL_REG);
-+	reg |= DIS_ORD_CHK;
-+	advk_writel(pcie, reg, DEBUG_MUX_CTRL_REG);
-+
- 	/* Set lane X1 */
- 	reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
- 	reg &= ~LANE_CNT_MSK;
-@@ -1580,6 +1587,9 @@ static irqreturn_t advk_pcie_irq_handler
- 	struct advk_pcie *pcie = arg;
- 	u32 status;
- 
-+	/* Full memory barrier (ARM dsb sy), workaround for erratum 3.12 "PCIe completion timeout" */
-+	mb();
-+
- 	status = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG);
- 	if (!(status & PCIE_IRQ_CORE_INT))
- 		return IRQ_NONE;
diff --git a/target/linux/mvebu/patches-5.15/101-ARM-dts-turris-omnia-enable-LED-controller-node.patch b/target/linux/mvebu/patches-5.15/101-ARM-dts-turris-omnia-enable-LED-controller-node.patch
deleted file mode 100644
index ecfb43553f517c..00000000000000
--- a/target/linux/mvebu/patches-5.15/101-ARM-dts-turris-omnia-enable-LED-controller-node.patch
+++ /dev/null
@@ -1,48 +0,0 @@
-From fed7cef5e4f2df8c6a79bebf5da1fdd3783ff6f3 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>
-Date: Mon, 4 Jul 2022 13:36:22 +0200
-Subject: [PATCH] ARM: dts: turris-omnia: enable LED controller node
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The LED controller node is disabled because the leds-turris-omnia driver
-does not support setting the LED blinking to be controlled by the MCU.
-
-The patches for that have now been sent [1], so let's enable the node.
-
-[1] https://lore.kernel.org/linux-leds/20220704105955.15474-1-kabel@kernel.org/T/
-
-Signed-off-by: Marek Behún <kabel@kernel.org>
----
- arch/arm/boot/dts/armada-385-turris-omnia.dts | 7 ++-----
- 1 file changed, 2 insertions(+), 5 deletions(-)
-
---- a/arch/arm/boot/dts/armada-385-turris-omnia.dts
-+++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts
-@@ -194,15 +194,13 @@
- 				reg = <0x2b>;
- 				#address-cells = <1>;
- 				#size-cells = <0>;
-+				status = "okay";
- 
- 				/*
- 				 * LEDs are controlled by MCU (STM32F0) at
- 				 * address 0x2b.
- 				 *
--				 * The driver does not support HW control mode
--				 * for the LEDs yet. Disable the LEDs for now.
--				 *
--				 * Also LED functions are not stable yet:
-+				 * LED functions are not stable yet:
- 				 * - there are 3 LEDs connected via MCU to PCIe
- 				 *   ports. One of these ports supports mSATA.
- 				 *   There is no mSATA nor PCIe function.
-@@ -213,7 +211,6 @@
- 				 *   B. Again there is no such function defined.
- 				 *   For now we use LED_FUNCTION_INDICATOR
- 				 */
--				status = "disabled";
- 
- 				multi-led@0 {
- 					reg = <0x0>;
diff --git a/target/linux/mvebu/patches-5.15/105-power-reset-linkstation-poweroff-add-ls220de.patch b/target/linux/mvebu/patches-5.15/105-power-reset-linkstation-poweroff-add-ls220de.patch
deleted file mode 100644
index 32238612344b57..00000000000000
--- a/target/linux/mvebu/patches-5.15/105-power-reset-linkstation-poweroff-add-ls220de.patch
+++ /dev/null
@@ -1,15 +0,0 @@
---- a/drivers/power/reset/linkstation-poweroff.c
-+++ b/drivers/power/reset/linkstation-poweroff.c
-@@ -142,6 +142,12 @@ static void linkstation_poweroff(void)
- }
- 
- static const struct of_device_id ls_poweroff_of_match[] = {
-+	{ .compatible = "buffalo,ls220d",
-+	  .data = &linkstation_power_off_cfg,
-+	},
-+	{ .compatible = "buffalo,ls220de",
-+	  .data = &linkstation_power_off_cfg,
-+	},
- 	{ .compatible = "buffalo,ls421d",
- 	  .data = &linkstation_power_off_cfg,
- 	},
diff --git a/target/linux/mvebu/patches-5.15/300-mvebu-Mangle-bootloader-s-kernel-arguments.patch b/target/linux/mvebu/patches-5.15/300-mvebu-Mangle-bootloader-s-kernel-arguments.patch
deleted file mode 100644
index bedeea4784c4fe..00000000000000
--- a/target/linux/mvebu/patches-5.15/300-mvebu-Mangle-bootloader-s-kernel-arguments.patch
+++ /dev/null
@@ -1,279 +0,0 @@
-From 71270226b14733a4b1f2cde58ea9265caa50b38d Mon Sep 17 00:00:00 2001
-From: Adrian Panella <ianchi74@outlook.com>
-Date: Thu, 9 Mar 2017 09:37:17 +0100
-Subject: [PATCH 67/69] generic: Mangle bootloader's kernel arguments
-
-The command-line arguments provided by the boot loader will be
-appended to a new device tree property: bootloader-args.
-If there is a property "append-rootblock" in DT under /chosen
-and a root= option in bootloaders command line it will be parsed
-and added to DT bootargs with the form: <append-rootblock>XX.
-Only command line ATAG will be processed, the rest of the ATAGs
-sent by bootloader will be ignored.
-This is usefull in dual boot systems, to get the current root partition
-without afecting the rest of the system.
-
-Signed-off-by: Adrian Panella <ianchi74@outlook.com>
-
-This patch has been modified to be mvebu specific. The original patch 
-did not pass the bootloader cmdline on if no append-rootblock stanza 
-was found, resulting in blank cmdline and failure to boot.
-
-Signed-off-by: Michael Gray <michael.gray@lantisproject.com>
----
- arch/arm/Kconfig                        | 11 ++++
- arch/arm/boot/compressed/atags_to_fdt.c | 85 ++++++++++++++++++++++++-
- init/main.c                             | 16 +++++
- 3 files changed, 111 insertions(+), 1 deletion(-)
-
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -1728,6 +1728,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
- 	  The command-line arguments provided by the boot loader will be
- 	  appended to the the device tree bootargs property.
- 
-+config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
-+	bool "Append rootblock parsing bootloader's kernel arguments"
-+	help
-+	  The command-line arguments provided by the boot loader will be
-+	  appended to a new device tree property: bootloader-args.
-+	  If there is a property "append-rootblock" in DT under /chosen 
-+	  and a root= option in bootloaders command line it will be parsed 
-+	  and added to DT bootargs with the form: <append-rootblock>XX.
-+	  Only command line ATAG will be processed, the rest of the ATAGs
-+	  sent by bootloader will be ignored.
-+
- endchoice
- 
- config CMDLINE
---- a/arch/arm/boot/compressed/atags_to_fdt.c
-+++ b/arch/arm/boot/compressed/atags_to_fdt.c
-@@ -5,6 +5,8 @@
- 
- #if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND)
- #define do_extend_cmdline 1
-+#elif defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
-+#define do_extend_cmdline 1
- #else
- #define do_extend_cmdline 0
- #endif
-@@ -20,6 +22,7 @@ static int node_offset(void *fdt, const
- 	return offset;
- }
- 
-+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
- static int setprop(void *fdt, const char *node_path, const char *property,
- 		   void *val_array, int size)
- {
-@@ -28,6 +31,7 @@ static int setprop(void *fdt, const char
- 		return offset;
- 	return fdt_setprop(fdt, offset, property, val_array, size);
- }
-+#endif
- 
- static int setprop_string(void *fdt, const char *node_path,
- 			  const char *property, const char *string)
-@@ -38,6 +42,7 @@ static int setprop_string(void *fdt, con
- 	return fdt_setprop_string(fdt, offset, property, string);
- }
- 
-+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
- static int setprop_cell(void *fdt, const char *node_path,
- 			const char *property, uint32_t val)
- {
-@@ -46,6 +51,7 @@ static int setprop_cell(void *fdt, const
- 		return offset;
- 	return fdt_setprop_cell(fdt, offset, property, val);
- }
-+#endif
- 
- static const void *getprop(const void *fdt, const char *node_path,
- 			   const char *property, int *len)
-@@ -58,6 +64,7 @@ static const void *getprop(const void *f
- 	return fdt_getprop(fdt, offset, property, len);
- }
- 
-+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
- static uint32_t get_cell_size(const void *fdt)
- {
- 	int len;
-@@ -69,6 +76,74 @@ static uint32_t get_cell_size(const void
- 	return cell_size;
- }
- 
-+#endif
-+
-+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
-+
-+static char *append_rootblock(char *dest, const char *str, int len, void *fdt)
-+{
-+	const char *ptr, *end;
-+	const char *root="root=";
-+	int i, l;
-+	const char *rootblock;
-+
-+	//ARM doesn't have __HAVE_ARCH_STRSTR, so search manually
-+	ptr = str - 1;
-+
-+	do {
-+		//first find an 'r' at the begining or after a space
-+		do {
-+			ptr++;
-+			ptr = strchr(ptr, 'r');
-+			if (!ptr)
-+				goto no_append;
-+
-+		} while (ptr != str && *(ptr-1) != ' ');
-+
-+		//then check for the rest
-+		for(i = 1; i <= 4; i++)
-+			if(*(ptr+i) != *(root+i)) break;
-+
-+	} while (i != 5);
-+
-+	end = strchr(ptr, ' ');
-+	end = end ? (end - 1) : (strchr(ptr, 0) - 1);
-+
-+	//find partition number (assumes format root=/dev/mtdXX | /dev/mtdblockXX | yy:XX )
-+	for( i = 0; end >= ptr && *end >= '0' && *end <= '9'; end--, i++);
-+	ptr = end + 1;
-+
-+	/* if append-rootblock property is set use it to append to command line */
-+	rootblock = getprop(fdt, "/chosen", "append-rootblock", &l);
-+	if (rootblock == NULL)
-+		goto no_append;
-+
-+	if (*dest != ' ') {
-+		*dest = ' ';
-+		dest++;
-+		len++;
-+	}
-+
-+	if (len + l + i <= COMMAND_LINE_SIZE) {
-+		memcpy(dest, rootblock, l);
-+		dest += l - 1;
-+		memcpy(dest, ptr, i);
-+		dest += i;
-+	}
-+
-+	return dest;
-+
-+no_append:
-+	len = strlen(str);
-+	if (len + 1 < COMMAND_LINE_SIZE) {
-+		memcpy(dest, str, len);
-+		dest += len;
-+	}
-+
-+	return dest;
-+}
-+#endif
-+
- static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline)
- {
- 	char cmdline[COMMAND_LINE_SIZE];
-@@ -88,18 +163,28 @@ static void merge_fdt_bootargs(void *fdt
- 
- 	/* and append the ATAG_CMDLINE */
- 	if (fdt_cmdline) {
-+
-+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
-+		//save original bootloader args
-+		//and append ubi.mtd with root partition number to current cmdline
-+		setprop_string(fdt, "/chosen", "bootloader-args", fdt_cmdline);
-+		ptr = append_rootblock(ptr, fdt_cmdline, len, fdt);
-+
-+#else
- 		len = strlen(fdt_cmdline);
- 		if (ptr - cmdline + len + 2 < COMMAND_LINE_SIZE) {
- 			*ptr++ = ' ';
- 			memcpy(ptr, fdt_cmdline, len);
- 			ptr += len;
- 		}
-+#endif
- 	}
- 	*ptr = '\0';
- 
- 	setprop_string(fdt, "/chosen", "bootargs", cmdline);
- }
- 
-+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
- static void hex_str(char *out, uint32_t value)
- {
- 	uint32_t digit;
-@@ -117,6 +202,7 @@ static void hex_str(char *out, uint32_t
- 	}
- 	*out = '\0';
- }
-+#endif
- 
- /*
-  * Convert and fold provided ATAGs into the provided FDT.
-@@ -131,9 +217,11 @@ int atags_to_fdt(void *atag_list, void *
- 	struct tag *atag = atag_list;
- 	/* In the case of 64 bits memory size, need to reserve 2 cells for
- 	 * address and size for each bank */
-+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
- 	__be32 mem_reg_property[2 * 2 * NR_BANKS];
--	int memcount = 0;
--	int ret, memsize;
-+	int memsize, memcount = 0;
-+#endif
-+	int ret;
- 
- 	/* make sure we've got an aligned pointer */
- 	if ((u32)atag_list & 0x3)
-@@ -168,7 +256,9 @@ int atags_to_fdt(void *atag_list, void *
- 			else
- 				setprop_string(fdt, "/chosen", "bootargs",
- 					       atag->u.cmdline.cmdline);
--		} else if (atag->hdr.tag == ATAG_MEM) {
-+		}
-+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
-+		else if (atag->hdr.tag == ATAG_MEM) {
- 			if (memcount >= sizeof(mem_reg_property)/4)
- 				continue;
- 			if (!atag->u.mem.size)
-@@ -212,6 +302,10 @@ int atags_to_fdt(void *atag_list, void *
- 		setprop(fdt, "/memory", "reg", mem_reg_property,
- 			4 * memcount * memsize);
- 	}
-+#else
-+
-+	}
-+#endif
- 
- 	return fdt_pack(fdt);
- }
---- a/init/main.c
-+++ b/init/main.c
-@@ -112,6 +112,10 @@
- 
- #include <kunit/test.h>
- 
-+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
-+#include <linux/of.h>
-+#endif
-+
- static int kernel_init(void *);
- 
- extern void init_IRQ(void);
-@@ -992,6 +996,18 @@ asmlinkage __visible void __init __no_sa
- 	page_alloc_init();
- 
- 	pr_notice("Kernel command line: %s\n", saved_command_line);
-+
-+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
-+	//Show bootloader's original command line for reference
-+	if(of_chosen) {
-+		const char *prop = of_get_property(of_chosen, "bootloader-args", NULL);
-+		if(prop)
-+			pr_notice("Bootloader command line (ignored): %s\n", prop);
-+		else
-+			pr_notice("Bootloader command line not present\n");
-+	}
-+#endif
-+
- 	/* parameters may set static keys */
- 	jump_label_init();
- 	parse_early_param();
diff --git a/target/linux/mvebu/patches-5.15/301-mvebu-armada-38x-enable-libata-leds.patch b/target/linux/mvebu/patches-5.15/301-mvebu-armada-38x-enable-libata-leds.patch
deleted file mode 100644
index 615caac24f4b19..00000000000000
--- a/target/linux/mvebu/patches-5.15/301-mvebu-armada-38x-enable-libata-leds.patch
+++ /dev/null
@@ -1,10 +0,0 @@
---- a/arch/arm/mach-mvebu/Kconfig
-+++ b/arch/arm/mach-mvebu/Kconfig
-@@ -67,6 +67,7 @@ config MACH_ARMADA_38X
- 	select HAVE_ARM_TWD if SMP
- 	select MACH_MVEBU_V7
- 	select PINCTRL_ARMADA_38X
-+	select ARCH_WANT_LIBATA_LEDS
- 	help
- 	  Say 'Y' here if you want your kernel to support boards based
- 	  on the Marvell Armada 380/385 SoC with device tree.
diff --git a/target/linux/mvebu/patches-5.15/302-add_powertables.patch b/target/linux/mvebu/patches-5.15/302-add_powertables.patch
deleted file mode 100644
index 93ad5de2cc40b1..00000000000000
--- a/target/linux/mvebu/patches-5.15/302-add_powertables.patch
+++ /dev/null
@@ -1,770 +0,0 @@
---- a/arch/arm/boot/dts/armada-385-linksys.dtsi
-+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi
-@@ -214,11 +214,19 @@
- &pcie1 {
- 	/* Marvell 88W8864, 5GHz-only */
- 	status = "okay";
-+
-+	mwlwifi {
-+		marvell,2ghz = <0>;
-+	};
- };
- 
- &pcie2 {
- 	/* Marvell 88W8864, 2GHz-only */
- 	status = "okay";
-+
-+	mwlwifi {
-+		marvell,5ghz = <0>;
-+	};
- };
- 
- &pinctrl {
---- a/arch/arm/boot/dts/armada-385-linksys-caiman.dts
-+++ b/arch/arm/boot/dts/armada-385-linksys-caiman.dts
-@@ -142,3 +142,205 @@
- 		};
- 	};
- };
-+
-+&pcie1 {
-+	mwlwifi {
-+		marvell,chainmask = <2 2>;
-+		marvell,powertable {
-+			AU =
-+				<36 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<40 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<44 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<48 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<52 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<56 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<60 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<64 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<100 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+				<104 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+				<108 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+				<112 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+				<116 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+				<120 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+				<124 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+				<128 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+				<132 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+				<136 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+				<140 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+				<149 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>,
-+				<153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>,
-+				<157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>,
-+				<161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>,
-+				<165 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>;
-+			CA =
-+				<36 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>,
-+				<40 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>,
-+				<44 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>,
-+				<48 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>,
-+				<52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<149 0 0x1a 0x1a 0x18 0x17 0x19 0x19 0x17 0x15 0x18 0x18 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
-+				<153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
-+				<157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
-+				<161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
-+				<165 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>;
-+			CN =
-+				<36 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<40 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<44 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<48 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<52 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<56 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<60 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<64 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<100 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<104 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<108 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<112 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<116 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<120 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<124 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<128 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<132 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<136 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<140 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<149 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x11 0x11 0x11 0x11 0 0xf>,
-+				<153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>,
-+				<157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>,
-+				<161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>,
-+				<165 0 0x15 0x15 0x15 0x15 0x16 0x16 0x16 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>;
-+			ETSI =
-+				<36 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<40 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<44 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<48 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<52 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<56 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<60 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<64 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<100 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<104 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<108 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<112 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<116 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<120 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<124 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<128 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<132 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<136 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<140 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<149 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>;
-+			FCC =
-+				<36 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<40 0 0x19 0x19 0x18 0x17 0x19 0x19 0x17 0x15 0x17 0x17 0x17 0x14 0x10 0x10 0x10 0x10 0 0xf>,
-+				<44 0 0x19 0x19 0x18 0x17 0x19 0x19 0x17 0x15 0x17 0x17 0x17 0x14 0x10 0x10 0x10 0x10 0 0xf>,
-+				<48 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x17 0x17 0x17 0x14 0x10 0x10 0x10 0x10 0 0xf>,
-+				<52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<149 0 0x1a 0x1a 0x18 0x17 0x19 0x19 0x17 0x15 0x18 0x18 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
-+				<153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
-+				<157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
-+				<161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
-+				<165 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>;
-+		};
-+	};
-+};
-+
-+&pcie2 {
-+	mwlwifi {
-+		marvell,chainmask = <2 2>;
-+		marvell,powertable {
-+			AU =
-+				<1 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<2 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<3 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<4 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<5 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<6 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<7 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<8 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<9 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<10 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<11 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>;
-+			CA =
-+				<1 0 0x19 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x10 0x10 0x10 0x10 0x00 0x00 0x00 0x00 0 0xf>,
-+				<2 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
-+				<3 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
-+				<4 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
-+				<5 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
-+				<6 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
-+				<7 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
-+				<8 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
-+				<9 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
-+				<10 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
-+				<11 0 0x19 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x00 0x00 0x00 0x00 0 0xf>;
-+			CN =
-+				<1 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<2 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<3 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<4 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<5 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<6 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<7 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<8 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<9 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<10 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<11 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<12 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<13 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<14 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>;
-+			ETSI =
-+				<1 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<2 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<3 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<4 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<5 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<6 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<7 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<8 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<9 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<10 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<11 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<12 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<13 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>;
-+			FCC =
-+				<1 0 0x19 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
-+				<2 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
-+				<3 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
-+				<4 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
-+				<5 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
-+				<6 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
-+				<7 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
-+				<8 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
-+				<9 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
-+				<10 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
-+				<11 0 0x19 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x0 0x0 0x0 0x0 0 0xf>;
-+		};
-+	};
-+};
---- a/arch/arm/boot/dts/armada-385-linksys-cobra.dts
-+++ b/arch/arm/boot/dts/armada-385-linksys-cobra.dts
-@@ -142,3 +142,205 @@
- 		};
- 	};
- };
-+
-+&pcie1 {
-+	mwlwifi {
-+		marvell,chainmask = <4 4>;
-+		marvell,powertable {
-+			AU =
-+				<36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<104 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<108 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<112 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<116 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<120 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<124 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<128 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<132 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<136 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<140 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<149 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
-+				<153 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
-+				<157 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
-+				<161 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
-+				<165 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>;
-+			CA =
-+				<36 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+				<40 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+				<44 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+				<48 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+				<52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+				<153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+				<157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+				<161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+				<165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>;
-+			CN =
-+				<36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<149 0 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
-+				<157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
-+				<161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
-+				<165 0 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>;
-+			ETSI =
-+				<36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<149 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>;
-+			FCC =
-+				<36 0 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0 0xf>,
-+				<40 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
-+				<44 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
-+				<48 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
-+				<52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+				<153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+				<157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+				<161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+				<165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>;
-+		};
-+	};
-+};
-+
-+&pcie2 {
-+	mwlwifi {
-+		marvell,chainmask = <4 4>;
-+		marvell,powertable {
-+			AU =
-+				<1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
-+			CA =
-+				<1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>,
-+				<2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>;
-+			CN =
-+				<1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<14 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
-+			ETSI =
-+				<1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
-+			FCC =
-+				<1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>,
-+				<2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>;
-+		};
-+	};
-+};
---- a/arch/arm/boot/dts/armada-385-linksys-shelby.dts
-+++ b/arch/arm/boot/dts/armada-385-linksys-shelby.dts
-@@ -142,3 +142,205 @@
- 		};
- 	};
- };
-+
-+&pcie1 {
-+	mwlwifi {
-+		marvell,chainmask = <4 4>;
-+		marvell,powertable {
-+			AU =
-+				<36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<104 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<108 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<112 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<116 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<120 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<124 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<128 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<132 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<136 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<140 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<149 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
-+				<153 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
-+				<157 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
-+				<161 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
-+				<165 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>;
-+			CA =
-+				<36 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+				<40 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+				<44 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+				<48 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+				<52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+				<153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+				<157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+				<161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+				<165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>;
-+			CN =
-+				<36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<149 0 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
-+				<157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
-+				<161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
-+				<165 0 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>;
-+			ETSI =
-+				<36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<149 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>;
-+			FCC =
-+				<36 0 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0 0xf>,
-+				<40 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
-+				<44 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
-+				<48 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
-+				<52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+				<153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+				<157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+				<161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+				<165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>;
-+		};
-+	};
-+};
-+
-+&pcie2 {
-+	mwlwifi {
-+		marvell,chainmask = <4 4>;
-+		marvell,powertable {
-+			AU =
-+				<1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
-+			CA =
-+				<1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>,
-+				<2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>;
-+			CN =
-+				<1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<14 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
-+			ETSI =
-+				<1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
-+			FCC =
-+				<1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>,
-+				<2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>;
-+		};
-+	};
-+};
---- a/arch/arm/boot/dts/armada-385-linksys-rango.dts
-+++ b/arch/arm/boot/dts/armada-385-linksys-rango.dts
-@@ -157,6 +157,18 @@
- 	};
- };
- 
-+&pcie1 {
-+	mwlwifi {
-+		marvell,chainmask = <4 4>;
-+	};
-+};
-+
-+&pcie2 {
-+	mwlwifi {
-+		marvell,chainmask = <4 4>;
-+	};
-+};
-+
- &sdhci {
- 	pinctrl-names = "default";
- 	pinctrl-0 = <&sdhci_pins>;
---- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-@@ -225,12 +225,100 @@
- 	pcie@2,0 {
- 		/* Port 0, Lane 1 */
- 		status = "okay";
-+
-+		mwlwifi {
-+			marvell,5ghz = <0>;
-+			marvell,chainmask = <4 4>;
-+			marvell,powertable {
-+				FCC =
-+					<1 0 0x17 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>,
-+					<2 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
-+					<3 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
-+					<4 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
-+					<5 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
-+					<6 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
-+					<7 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
-+					<8 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
-+					<9 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
-+					<10 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
-+					<11 0 0x17 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>;
-+
-+				ETSI =
-+					<1 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+					<2 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+					<3 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+					<4 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+					<5 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+					<6 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+					<7 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+					<8 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+					<9 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+					<10 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+					<11 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+					<12 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+					<13 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>;
-+			};
-+		};
- 	};
- 
- 	/* Second mini-PCIe port */
- 	pcie@3,0 {
- 		/* Port 0, Lane 3 */
- 		status = "okay";
-+
-+		mwlwifi {
-+			marvell,2ghz = <0>;
-+			marvell,chainmask = <4 4>;
-+			marvell,powertable {
-+				FCC =
-+					<36 0 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+					<40 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+					<44 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+					<48 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+					<52 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>,
-+					<56 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>,
-+					<60 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>,
-+					<64 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>,
-+					<100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+					<104 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+					<108 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+					<112 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+					<116 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+					<120 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+					<124 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+					<128 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+					<132 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+					<136 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+					<140 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+					<149 0 0x16 0x16 0x16 0x16 0x14 0x14 0x14 0x14 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>,
-+					<153 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>,
-+					<157 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>,
-+					<161 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>,
-+					<165 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>;
-+
-+				ETSI =
-+					<36 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<40 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<44 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<48 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<52 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<56 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<60 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<64 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<100 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<104 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<108 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<112 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<116 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<120 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<124 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<128 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<132 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<136 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<140 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<149 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>;
-+			};
-+		};
- 	};
- };
- 
diff --git a/target/linux/mvebu/patches-5.15/304-revert_i2c_delay.patch b/target/linux/mvebu/patches-5.15/304-revert_i2c_delay.patch
deleted file mode 100644
index 930c0f94942b6b..00000000000000
--- a/target/linux/mvebu/patches-5.15/304-revert_i2c_delay.patch
+++ /dev/null
@@ -1,15 +0,0 @@
---- a/arch/arm/boot/dts/armada-xp.dtsi
-+++ b/arch/arm/boot/dts/armada-xp.dtsi
-@@ -237,12 +237,10 @@
- };
- 
- &i2c0 {
--	compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
- 	reg = <0x11000 0x100>;
- };
- 
- &i2c1 {
--	compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
- 	reg = <0x11100 0x100>;
- };
- 
diff --git a/target/linux/mvebu/patches-5.15/305-armada-385-rd-mtd-partitions.patch b/target/linux/mvebu/patches-5.15/305-armada-385-rd-mtd-partitions.patch
deleted file mode 100644
index 31bd53b1f3be82..00000000000000
--- a/target/linux/mvebu/patches-5.15/305-armada-385-rd-mtd-partitions.patch
+++ /dev/null
@@ -1,19 +0,0 @@
---- a/arch/arm/boot/dts/armada-388-rd.dts
-+++ b/arch/arm/boot/dts/armada-388-rd.dts
-@@ -103,6 +103,16 @@
- 		compatible = "st,m25p128", "jedec,spi-nor";
- 		reg = <0>; /* Chip select 0 */
- 		spi-max-frequency = <108000000>;
-+
-+		partition@0 {
-+			label = "uboot";
-+			reg = <0 0x400000>;
-+		};
-+
-+		partition@1 {
-+			label = "firmware";
-+			reg = <0x400000 0xc00000>;
-+		};
- 	};
- };
- 
diff --git a/target/linux/mvebu/patches-5.15/306-ARM-mvebu-385-ap-Add-partitions.patch b/target/linux/mvebu/patches-5.15/306-ARM-mvebu-385-ap-Add-partitions.patch
deleted file mode 100644
index 2057e31c7e9759..00000000000000
--- a/target/linux/mvebu/patches-5.15/306-ARM-mvebu-385-ap-Add-partitions.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From 9861f93a59142a3131870df2521eb2deb73026d7 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Tue, 13 Jan 2015 11:14:09 +0100
-Subject: [PATCH 2/2] ARM: mvebu: 385-ap: Add partitions
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/armada-385-db-ap.dts | 15 +++++++++++++++
- 1 file changed, 15 insertions(+)
-
---- a/arch/arm/boot/dts/armada-385-db-ap.dts
-+++ b/arch/arm/boot/dts/armada-385-db-ap.dts
-@@ -218,19 +218,19 @@
- 			#size-cells = <1>;
- 
- 			partition@0 {
--				label = "U-Boot";
-+				label = "u-boot";
- 				reg = <0x00000000 0x00800000>;
- 				read-only;
- 			};
- 
- 			partition@800000 {
--				label = "uImage";
-+				label = "kernel";
- 				reg = <0x00800000 0x00400000>;
- 				read-only;
- 			};
- 
- 			partition@c00000 {
--				label = "Root";
-+				label = "ubi";
- 				reg = <0x00c00000 0x3f400000>;
- 			};
- 		};
diff --git a/target/linux/mvebu/patches-5.15/307-armada-xp-linksys-mamba-broken-idle.patch b/target/linux/mvebu/patches-5.15/307-armada-xp-linksys-mamba-broken-idle.patch
deleted file mode 100644
index 16112d53fc99c7..00000000000000
--- a/target/linux/mvebu/patches-5.15/307-armada-xp-linksys-mamba-broken-idle.patch
+++ /dev/null
@@ -1,10 +0,0 @@
---- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-@@ -485,3 +485,7 @@
- 		};
- 	};
- };
-+
-+&coherencyfab {
-+	broken-idle;
-+};
diff --git a/target/linux/mvebu/patches-5.15/308-armada-xp-linksys-mamba-wan.patch b/target/linux/mvebu/patches-5.15/308-armada-xp-linksys-mamba-wan.patch
deleted file mode 100644
index 4315abc7d22ade..00000000000000
--- a/target/linux/mvebu/patches-5.15/308-armada-xp-linksys-mamba-wan.patch
+++ /dev/null
@@ -1,11 +0,0 @@
---- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-@@ -387,7 +387,7 @@
- 
- 			port@4 {
- 				reg = <4>;
--				label = "internet";
-+				label = "wan";
- 			};
- 
- 			port@5 {
diff --git a/target/linux/mvebu/patches-5.15/309-linksys-status-led.patch b/target/linux/mvebu/patches-5.15/309-linksys-status-led.patch
deleted file mode 100644
index e5e83572c9e242..00000000000000
--- a/target/linux/mvebu/patches-5.15/309-linksys-status-led.patch
+++ /dev/null
@@ -1,50 +0,0 @@
---- a/arch/arm/boot/dts/armada-385-linksys.dtsi
-+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi
-@@ -14,6 +14,13 @@
- 	compatible = "linksys,armada385", "marvell,armada385",
- 		     "marvell,armada380";
- 
-+	aliases {
-+		led-boot = &led_power;
-+		led-failsafe = &led_power;
-+		led-running = &led_power;
-+		led-upgrade = &led_power;
-+	};
-+
- 	chosen {
- 		stdout-path = "serial0:115200n8";
- 	};
-@@ -71,7 +78,7 @@
- 		pinctrl-0 = <&gpio_leds_pins>;
- 		pinctrl-names = "default";
- 
--		power {
-+		led_power: power {
- 			gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
- 			default-state = "on";
- 		};
---- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-@@ -26,6 +26,13 @@
- 	compatible = "linksys,mamba", "marvell,armadaxp-mv78230",
- 		     "marvell,armadaxp", "marvell,armada-370-xp";
- 
-+	aliases {
-+		led-boot = &led_power;
-+		led-failsafe = &led_power;
-+		led-running = &led_power;
-+		led-upgrade = &led_power;
-+	};
-+
- 	chosen {
- 		bootargs = "console=ttyS0,115200";
- 		stdout-path = &uart0;
-@@ -197,7 +204,7 @@
- 		pinctrl-0 = <&power_led_pin>;
- 		pinctrl-names = "default";
- 
--		power {
-+		led_power: power {
- 			label = "mamba:white:power";
- 			gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
- 			default-state = "on";
diff --git a/target/linux/mvebu/patches-5.15/310-linksys-use-eth0-as-cpu-port.patch b/target/linux/mvebu/patches-5.15/310-linksys-use-eth0-as-cpu-port.patch
deleted file mode 100644
index 84d49a004b85b3..00000000000000
--- a/target/linux/mvebu/patches-5.15/310-linksys-use-eth0-as-cpu-port.patch
+++ /dev/null
@@ -1,25 +0,0 @@
---- a/arch/arm/boot/dts/armada-385-linksys.dtsi
-+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi
-@@ -116,7 +116,7 @@
- };
- 
- &eth2 {
--	status = "okay";
-+	status = "disabled";
- 	phy-mode = "sgmii";
- 	buffer-manager = <&bm>;
- 	bm,pool-long = <2>;
-@@ -200,10 +200,10 @@
- 				label = "wan";
- 			};
- 
--			port@5 {
--				reg = <5>;
-+			port@6 {
-+				reg = <6>;
- 				label = "cpu";
--				ethernet = <&eth2>;
-+				ethernet = <&eth0>;
- 
- 				fixed-link {
- 					speed = <1000>;
diff --git a/target/linux/mvebu/patches-5.15/311-adjust-compatible-for-linksys.patch b/target/linux/mvebu/patches-5.15/311-adjust-compatible-for-linksys.patch
deleted file mode 100644
index a5d3e6381064e5..00000000000000
--- a/target/linux/mvebu/patches-5.15/311-adjust-compatible-for-linksys.patch
+++ /dev/null
@@ -1,68 +0,0 @@
---- a/arch/arm/boot/dts/armada-385-linksys-rango.dts
-+++ b/arch/arm/boot/dts/armada-385-linksys-rango.dts
-@@ -12,8 +12,8 @@
- 
- / {
- 	model = "Linksys WRT3200ACM";
--	compatible = "linksys,rango", "linksys,armada385", "marvell,armada385",
--		     "marvell,armada380";
-+	compatible = "linksys,wrt3200acm", "linksys,rango", "linksys,armada385",
-+		     "marvell,armada385", "marvell,armada380";
- };
- 
- &expander0 {
---- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-@@ -22,9 +22,10 @@
- #include "armada-xp-mv78230.dtsi"
- 
- / {
--	model = "Linksys WRT1900AC";
--	compatible = "linksys,mamba", "marvell,armadaxp-mv78230",
--		     "marvell,armadaxp", "marvell,armada-370-xp";
-+	model = "Linksys WRT1900AC v1";
-+	compatible = "linksys,wrt1900ac-v1", "linksys,mamba",
-+		     "marvell,armadaxp-mv78230", "marvell,armadaxp",
-+		     "marvell,armada-370-xp";
- 
- 	aliases {
- 		led-boot = &led_power;
---- a/arch/arm/boot/dts/armada-385-linksys-cobra.dts
-+++ b/arch/arm/boot/dts/armada-385-linksys-cobra.dts
-@@ -9,8 +9,9 @@
- #include "armada-385-linksys.dtsi"
- 
- / {
--	model = "Linksys WRT1900ACv2";
--	compatible = "linksys,cobra", "linksys,armada385", "marvell,armada385",
-+	model = "Linksys WRT1900AC v2";
-+	compatible = "linksys,wrt1900ac-v2", "linksys,cobra",
-+		     "linksys,armada385", "marvell,armada385",
- 		     "marvell,armada380";
- };
- 
---- a/arch/arm/boot/dts/armada-385-linksys-caiman.dts
-+++ b/arch/arm/boot/dts/armada-385-linksys-caiman.dts
-@@ -10,8 +10,8 @@
- 
- / {
- 	model = "Linksys WRT1200AC";
--	compatible = "linksys,caiman", "linksys,armada385", "marvell,armada385",
--		     "marvell,armada380";
-+	compatible = "linksys,wrt1200ac", "linksys,caiman", "linksys,armada385",
-+		     "marvell,armada385", "marvell,armada380";
- };
- 
- &expander0 {
---- a/arch/arm/boot/dts/armada-385-linksys-shelby.dts
-+++ b/arch/arm/boot/dts/armada-385-linksys-shelby.dts
-@@ -10,7 +10,8 @@
- 
- / {
- 	model = "Linksys WRT1900ACS";
--	compatible = "linksys,shelby", "linksys,armada385", "marvell,armada385",
-+	compatible = "linksys,wrt1900acs", "linksys,shelby",
-+		     "linksys,armada385", "marvell,armada385",
- 		     "marvell,armada380";
- };
- 
diff --git a/target/linux/mvebu/patches-5.15/312-ARM-dts-armada388-clearfog-emmc-on-clearfog-base.patch b/target/linux/mvebu/patches-5.15/312-ARM-dts-armada388-clearfog-emmc-on-clearfog-base.patch
deleted file mode 100644
index dd2bef7f6321e5..00000000000000
--- a/target/linux/mvebu/patches-5.15/312-ARM-dts-armada388-clearfog-emmc-on-clearfog-base.patch
+++ /dev/null
@@ -1,87 +0,0 @@
-From 8137da20701c776ad3481115305a5e8e410871ba Mon Sep 17 00:00:00 2001
-From: Russell King <rmk+kernel@armlinux.org.uk>
-Date: Tue, 29 Nov 2016 10:15:45 +0000
-Subject: ARM: dts: armada388-clearfog: emmc on clearfog base
-
-Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
----
- arch/arm/boot/dts/armada-388-clearfog-base.dts     |  1 +
- .../dts/armada-38x-solidrun-microsom-emmc.dtsi     | 62 ++++++++++++++++++++++
- 2 files changed, 63 insertions(+)
- create mode 100644 arch/arm/boot/dts/armada-38x-solidrun-microsom-emmc.dtsi
-
---- a/arch/arm/boot/dts/armada-388-clearfog-base.dts
-+++ b/arch/arm/boot/dts/armada-388-clearfog-base.dts
-@@ -7,6 +7,7 @@
- 
- /dts-v1/;
- #include "armada-388-clearfog.dtsi"
-+#include "armada-38x-solidrun-microsom-emmc.dtsi"
- 
- / {
- 	model = "SolidRun Clearfog Base A1";
---- /dev/null
-+++ b/arch/arm/boot/dts/armada-38x-solidrun-microsom-emmc.dtsi
-@@ -0,0 +1,62 @@
-+/*
-+ * Device Tree file for SolidRun Armada 38x Microsom add-on for eMMC
-+ *
-+ *  Copyright (C) 2015 Russell King
-+ *
-+ * This board is in development; the contents of this file work with
-+ * the A1 rev 2.0 of the board, which does not represent final
-+ * production board.  Things will change, don't expect this file to
-+ * remain compatible info the future.
-+ *
-+ * This file is dual-licensed: you can use it either under the terms
-+ * of the GPL or the X11 license, at your option. Note that this dual
-+ * licensing only applies to this file, and not this project as a
-+ * whole.
-+ *
-+ *  a) This file is free software; you can redistribute it and/or
-+ *     modify it under the terms of the GNU General Public License
-+ *     version 2 as published by the Free Software Foundation.
-+ *
-+ *     This file is distributed in the hope that it will be useful
-+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ *     GNU General Public License for more details.
-+ *
-+ * Or, alternatively
-+ *
-+ *  b) Permission is hereby granted, free of charge, to any person
-+ *     obtaining a copy of this software and associated documentation
-+ *     files (the "Software"), to deal in the Software without
-+ *     restriction, including without limitation the rights to use
-+ *     copy, modify, merge, publish, distribute, sublicense, and/or
-+ *     sell copies of the Software, and to permit persons to whom the
-+ *     Software is furnished to do so, subject to the following
-+ *     conditions:
-+ *
-+ *     The above copyright notice and this permission notice shall be
-+ *     included in all copies or substantial portions of the Software.
-+ *
-+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
-+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
-+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ *     OTHER DEALINGS IN THE SOFTWARE.
-+ */
-+/ {
-+	soc {
-+		internal-regs {
-+			sdhci@d8000 {
-+				bus-width = <4>;
-+				no-1-8-v;
-+				non-removable;
-+				pinctrl-0 = <&microsom_sdhci_pins>;
-+				pinctrl-names = "default";
-+				status = "okay";
-+				wp-inverted;
-+			};
-+		};
-+	};
-+};
diff --git a/target/linux/mvebu/patches-5.15/313-helios4-dts-status-led-alias.patch b/target/linux/mvebu/patches-5.15/313-helios4-dts-status-led-alias.patch
deleted file mode 100644
index 607f436297126d..00000000000000
--- a/target/linux/mvebu/patches-5.15/313-helios4-dts-status-led-alias.patch
+++ /dev/null
@@ -1,28 +0,0 @@
---- a/arch/arm/boot/dts/armada-388-helios4.dts
-+++ b/arch/arm/boot/dts/armada-388-helios4.dts
-@@ -15,6 +15,13 @@
- 	model = "Helios4";
- 	compatible = "kobol,helios4", "marvell,armada388",
- 		"marvell,armada385", "marvell,armada380";
-+		
-+	aliases {
-+		led-boot = &led_status;
-+		led-failsafe = &led_status;
-+		led-running = &led_status;
-+		led-upgrade = &led_status;
-+	};
- 
- 	memory {
- 		device_type = "memory";
-@@ -73,10 +80,9 @@
- 		pinctrl-names = "default";
- 		pinctrl-0 = <&helios_system_led_pins>;
- 
--		status-led {
-+		led_status: status-led {
- 			label = "helios4:green:status";
- 			gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
--			linux,default-trigger = "heartbeat";
- 			default-state = "on";
- 		};
- 
diff --git a/target/linux/mvebu/patches-5.15/314-arm64-dts-marvell-enable-heartbeat-LED-by-default.patch b/target/linux/mvebu/patches-5.15/314-arm64-dts-marvell-enable-heartbeat-LED-by-default.patch
deleted file mode 100644
index 7221e04de1ddc7..00000000000000
--- a/target/linux/mvebu/patches-5.15/314-arm64-dts-marvell-enable-heartbeat-LED-by-default.patch
+++ /dev/null
@@ -1,22 +0,0 @@
-From: Tomasz Maciej Nowak <tmn505@gmail.com>
-Date: Fri, 7 Jul 2023 19:06:05 +0200
-Subject: [PATCH] arm64: dts: marvell: enable heartbeat LED by default
-
-Some boards could be placed in an enclosure, so enable LED18 by default,
-since that'll be the only visible indicator that the board is operating.
-
-Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
----
- arch/arm64/boot/dts/marvell/armada-8040-mcbin-singleshot.dts | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin-singleshot.dts
-+++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin-singleshot.dts
-@@ -25,6 +25,7 @@
- 			function = LED_FUNCTION_HEARTBEAT;
- 			color = <LED_COLOR_ID_GREEN>;
- 			linux,default-trigger = "heartbeat";
-+			default-state = "on";
- 		};
- 	};
- };
diff --git a/target/linux/mvebu/patches-5.15/315-armada-xp-linksys-mamba-resize-kernel.patch b/target/linux/mvebu/patches-5.15/315-armada-xp-linksys-mamba-resize-kernel.patch
deleted file mode 100644
index f1fddceff4b093..00000000000000
--- a/target/linux/mvebu/patches-5.15/315-armada-xp-linksys-mamba-resize-kernel.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From 258233f00bcd013050efee00c5d9128ef8cd62dd Mon Sep 17 00:00:00 2001
-From: Tad <tad@spotco.us>
-Date: Fri, 5 Feb 2021 22:32:11 -0500
-Subject: [PATCH] ARM: dts: armada-xp-linksys-mamba: Increase kernel
- partition to 4MB
-
-Signed-off-by: Tad Davanzo <tad@spotco.us>
----
- arch/arm/boot/dts/armada-xp-linksys-mamba.dts | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
---- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-@@ -456,9 +456,9 @@
- 				reg = <0xa00000 0x2800000>;  /* 40MB */
- 			};
- 
--			partition@d00000 {
-+			partition@e00000 {
- 				label = "rootfs1";
--				reg = <0xd00000 0x2500000>;  /* 37MB */
-+				reg = <0xe00000 0x2400000>;  /* 36MB */
- 			};
- 
- 			/* kernel2 overlaps with rootfs2 by design */
-@@ -467,9 +467,9 @@
- 				reg = <0x3200000 0x2800000>; /* 40MB */
- 			};
- 
--			partition@3500000 {
-+			partition@3600000 {
- 				label = "rootfs2";
--				reg = <0x3500000 0x2500000>; /* 37MB */
-+				reg = <0x3600000 0x2400000>; /* 36MB */
- 			};
- 
- 			/*
diff --git a/target/linux/mvebu/patches-5.15/316-armada-370-dts-fix-crypto-engine.patch b/target/linux/mvebu/patches-5.15/316-armada-370-dts-fix-crypto-engine.patch
deleted file mode 100644
index 19378870ef7400..00000000000000
--- a/target/linux/mvebu/patches-5.15/316-armada-370-dts-fix-crypto-engine.patch
+++ /dev/null
@@ -1,29 +0,0 @@
---- a/arch/arm/boot/dts/armada-370.dtsi
-+++ b/arch/arm/boot/dts/armada-370.dtsi
-@@ -234,7 +234,7 @@
- 				clocks = <&gateclk 23>;
- 				clock-names = "cesa0";
- 				marvell,crypto-srams = <&crypto_sram>;
--				marvell,crypto-sram-size = <0x7e0>;
-+				marvell,crypto-sram-size = <0x800>;
- 			};
- 		};
- 
-@@ -255,12 +255,17 @@
- 			 * cpuidle workaround.
- 			 */
- 			idle-sram@0 {
-+				status = "disabled";
- 				reg = <0x0 0x20>;
- 			};
- 		};
- 	};
- };
- 
-+&coherencyfab {
-+	broken-idle;
-+};
-+
- /*
-  * Default UART pinctrl setting without RTS/CTS, can be overwritten on
-  * board level if a different configuration is used.
diff --git a/target/linux/mvebu/patches-5.15/320-arm-dts-armada-370-synology-ds213j-mtd-parts.patch b/target/linux/mvebu/patches-5.15/320-arm-dts-armada-370-synology-ds213j-mtd-parts.patch
deleted file mode 100644
index 280fc5957e49ce..00000000000000
--- a/target/linux/mvebu/patches-5.15/320-arm-dts-armada-370-synology-ds213j-mtd-parts.patch
+++ /dev/null
@@ -1,134 +0,0 @@
---- a/arch/arm/boot/dts/armada-370-synology-ds213j.dts
-+++ b/arch/arm/boot/dts/armada-370-synology-ds213j.dts
-@@ -31,6 +31,7 @@
- 
- 	chosen {
- 		stdout-path = "serial0:115200n8";
-+		append-rootblock = "nullparameter="; /* override the bootloader args */
- 	};
- 
- 	memory@0 {
-@@ -94,6 +95,8 @@
- 			       status = "okay";
- 			       phy = <&phy1>;
- 			       phy-mode = "sgmii";
-+		               nvmem-cells = <&macaddr_vendor_0>;
-+        		       nvmem-cell-names = "mac-address";
- 			};
- 
- 			sata@a0000 {
-@@ -175,6 +178,24 @@
- 			gpio = <&gpio1 30 GPIO_ACTIVE_HIGH>;
- 		};
- 	};
-+
-+	virtual_flash {
-+		compatible = "mtd-concat";
-+
-+		devices = <&mtd_kernel &mtd_gap &mtd_gap2>;
-+
-+		partitions {
-+			compatible = "fixed-partitions";
-+			#address-cells = <1>;
-+			#size-cells = <1>;
-+
-+			partition@0 {
-+				compatible = "openwrt,uimage", "denx,uimage";
-+				label = "firmware";
-+				reg = <0x0 0x0>;
-+			};
-+		};
-+	};
- };
- 
- &mdio {
-@@ -265,48 +286,52 @@
- 		reg = <0>; /* Chip select 0 */
- 		spi-max-frequency = <20000000>;
- 
--		/*
--		 * Warning!
--		 *
--		 * Synology u-boot uses its compiled-in environment
--		 * and it seems Synology did not care to change u-boot
--		 * default configuration in order to allow saving a
--		 * modified environment at a sensible location. So,
--		 * if you do a 'saveenv' under u-boot, your modified
--		 * environment will be saved at 1MB after the start
--		 * of the flash, i.e. in the middle of the uImage.
--		 * For that reason, it is strongly advised not to
--		 * change the default environment, unless you know
--		 * what you are doing.
--		 */
--		partition@0 { /* u-boot */
--			label = "RedBoot";
--			reg = <0x00000000 0x000c0000>; /* 768KB */
--		};
-+		partitions {
-+			compatible = "fixed-partitions";
- 
--		partition@c0000 { /* uImage */
--			label = "zImage";
--			reg = <0x000c0000 0x002d0000>; /* 2880KB */
--		};
-+			partition@0 { /* u-boot */
-+				label = "u-boot";
-+				reg = <0x00000000 0x000c0000>; /* 768KB */
-+				read-only;
-+			};
- 
--		partition@390000 { /* uInitramfs */
--			label = "rd.gz";
--			reg = <0x00390000 0x00440000>; /* 4250KB */
--		};
-+			mtd_gap: partition@c0000 { /* gap */
-+				label = "gap";
-+				reg = <0x000c0000 0x00040000>; /* 256KB */
-+			};
- 
--		partition@7d0000 { /* MAC address and serial number */
--			label = "vendor";
--			reg = <0x007d0000 0x00010000>; /* 64KB */
--		};
-+			partition@100000 { /* u-boot-env */
-+				label = "u-boot-env";
-+				reg = <0x00100000 0x00010000>; /* 64KB */
-+			};
- 
--		partition@7e0000 {
--			label = "RedBoot config";
--			reg = <0x007e0000 0x00010000>; /* 64KB */
--		};
-+			mtd_kernel: partition@110000 {
-+				label = "kernel";
-+				reg = <0x00110000 0x006c0000>; /* 6912KB */
-+			};
- 
--		partition@7f0000 {
--			label = "FIS directory";
--			reg = <0x007f0000 0x00010000>; /* 64KB */
-+			partition@7d0000 { /* MAC address and serial number */
-+				reg = <0x007d0000 0x00010000>; /* 64KB */
-+				label = "vendor";
-+				read-only;
-+
-+				compatible = "nvmem-cells";
-+
-+				nvmem-layout {
-+					compatible = "fixed-layout";
-+					#address-cells = <1>;
-+					#size-cells = <1>;
-+
-+					macaddr_vendor_0: macaddr@0 {
-+						reg = <0x0 0x6>;
-+					};
-+				};
-+			};
-+
-+			mtd_gap2: partition@7e0000 {
-+				label = "gap2";
-+				reg = <0x007e0000 0x00020000>; /* 128KB */
-+			};
- 		};
- 	};
- };
diff --git a/target/linux/mvebu/patches-5.15/400-find_active_root.patch b/target/linux/mvebu/patches-5.15/400-find_active_root.patch
deleted file mode 100644
index 5582d20c6828d2..00000000000000
--- a/target/linux/mvebu/patches-5.15/400-find_active_root.patch
+++ /dev/null
@@ -1,60 +0,0 @@
-The WRT1900AC among other Linksys routers uses a dual-firmware layout.
-Dynamically rename the active partition to "ubi".
-
-Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
-
---- a/drivers/mtd/parsers/ofpart_core.c
-+++ b/drivers/mtd/parsers/ofpart_core.c
-@@ -38,6 +38,8 @@ static bool node_has_compatible(struct d
- 	return of_get_property(pp, "compatible", NULL);
- }
- 
-+static int mangled_rootblock;
-+
- static int parse_fixed_partitions(struct mtd_info *master,
- 				  const struct mtd_partition **pparts,
- 				  struct mtd_part_parser_data *data)
-@@ -48,6 +50,7 @@ static int parse_fixed_partitions(struct
- 	struct device_node *mtd_node;
- 	struct device_node *ofpart_node;
- 	const char *partname;
-+	const char *owrtpart = "ubi";
- 	struct device_node *pp;
- 	int nr_parts, i, ret = 0;
- 	bool dedicated = true;
-@@ -133,9 +136,13 @@ static int parse_fixed_partitions(struct
- 		parts[i].size = of_read_number(reg + a_cells, s_cells);
- 		parts[i].of_node = pp;
- 
--		partname = of_get_property(pp, "label", &len);
--		if (!partname)
--			partname = of_get_property(pp, "name", &len);
-+		if (mangled_rootblock && (i == mangled_rootblock)) {
-+			partname = owrtpart;
-+		} else {
-+			partname = of_get_property(pp, "label", &len);
-+			if (!partname)
-+				partname = of_get_property(pp, "name", &len);
-+		}
- 		parts[i].name = partname;
- 
- 		if (of_get_property(pp, "read-only", &len))
-@@ -252,6 +259,18 @@ static int __init ofpart_parser_init(voi
- 	return 0;
- }
- 
-+static int __init active_root(char *str)
-+{
-+	get_option(&str, &mangled_rootblock);
-+
-+	if (!mangled_rootblock)
-+		return 1;
-+
-+	return 1;
-+}
-+
-+__setup("mangled_rootblock=", active_root);
-+
- static void __exit ofpart_parser_exit(void)
- {
- 	deregister_mtd_parser(&ofpart_parser);
diff --git a/target/linux/mvebu/patches-5.15/700-mvneta-tx-queue-workaround.patch b/target/linux/mvebu/patches-5.15/700-mvneta-tx-queue-workaround.patch
deleted file mode 100644
index 32e8ef4b7d8727..00000000000000
--- a/target/linux/mvebu/patches-5.15/700-mvneta-tx-queue-workaround.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-The hardware queue scheduling is apparently configured with fixed
-priorities, which creates a nasty fairness issue where traffic from one
-CPU can starve traffic from all other CPUs.
-
-Work around this issue by forcing all tx packets to go through one CPU,
-until this issue is fixed properly.
-
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
---- a/drivers/net/ethernet/marvell/mvneta.c
-+++ b/drivers/net/ethernet/marvell/mvneta.c
-@@ -5006,6 +5006,16 @@ static int mvneta_setup_tc(struct net_de
- 	}
- }
- 
-+#ifndef CONFIG_ARM64
-+static u16 mvneta_select_queue(struct net_device *dev, struct sk_buff *skb,
-+			       struct net_device *sb_dev)
-+{
-+	/* XXX: hardware queue scheduling is broken,
-+	 * use only one queue until it is fixed */
-+	return 0;
-+}
-+#endif
-+
- static const struct net_device_ops mvneta_netdev_ops = {
- 	.ndo_open            = mvneta_open,
- 	.ndo_stop            = mvneta_stop,
-@@ -5016,6 +5026,9 @@ static const struct net_device_ops mvnet
- 	.ndo_fix_features    = mvneta_fix_features,
- 	.ndo_get_stats64     = mvneta_get_stats64,
- 	.ndo_eth_ioctl        = mvneta_ioctl,
-+#ifndef CONFIG_ARM64
-+	.ndo_select_queue    = mvneta_select_queue,
-+#endif
- 	.ndo_bpf	     = mvneta_xdp,
- 	.ndo_xdp_xmit        = mvneta_xdp_xmit,
- 	.ndo_setup_tc	     = mvneta_setup_tc,
diff --git a/target/linux/mvebu/patches-5.15/702-net-next-ethernet-marvell-mvnetaMQPrioOffload.patch b/target/linux/mvebu/patches-5.15/702-net-next-ethernet-marvell-mvnetaMQPrioOffload.patch
deleted file mode 100644
index 019b9528c360e5..00000000000000
--- a/target/linux/mvebu/patches-5.15/702-net-next-ethernet-marvell-mvnetaMQPrioOffload.patch
+++ /dev/null
@@ -1,66 +0,0 @@
-From 75fa71e3acadbb4ab5eda18505277eb9a1f69b23 Mon Sep 17 00:00:00 2001
-From: Maxime Chevallier <maxime.chevallier@bootlin.com>
-Date: Fri, 26 Nov 2021 12:20:53 +0100
-Subject: net: mvneta: Use struct tc_mqprio_qopt_offload for MQPrio
- configuration
-
-The struct tc_mqprio_qopt_offload is a container for struct tc_mqprio_qopt,
-that allows passing extra parameters, such as traffic shaping. This commit
-converts the current mqprio code to that new struct.
-
-Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/ethernet/marvell/mvneta.c | 17 ++++++++++-------
- 1 file changed, 10 insertions(+), 7 deletions(-)
-
-(limited to 'drivers/net/ethernet/marvell/mvneta.c')
-
---- a/drivers/net/ethernet/marvell/mvneta.c
-+++ b/drivers/net/ethernet/marvell/mvneta.c
-@@ -38,6 +38,7 @@
- #include <net/ipv6.h>
- #include <net/tso.h>
- #include <net/page_pool.h>
-+#include <net/pkt_cls.h>
- #include <linux/bpf_trace.h>
- 
- /* Registers */
-@@ -4966,14 +4967,14 @@ static void mvneta_setup_rx_prio_map(str
- }
- 
- static int mvneta_setup_mqprio(struct net_device *dev,
--			       struct tc_mqprio_qopt *qopt)
-+			       struct tc_mqprio_qopt_offload *mqprio)
- {
- 	struct mvneta_port *pp = netdev_priv(dev);
- 	u8 num_tc;
- 	int i;
- 
--	qopt->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
--	num_tc = qopt->num_tc;
-+	mqprio->qopt.hw = TC_MQPRIO_HW_OFFLOAD_TCS;
-+	num_tc = mqprio->qopt.num_tc;
- 
- 	if (num_tc > rxq_number)
- 		return -EINVAL;
-@@ -4984,13 +4985,15 @@ static int mvneta_setup_mqprio(struct ne
- 		return 0;
- 	}
- 
--	memcpy(pp->prio_tc_map, qopt->prio_tc_map, sizeof(pp->prio_tc_map));
-+	memcpy(pp->prio_tc_map, mqprio->qopt.prio_tc_map,
-+	       sizeof(pp->prio_tc_map));
- 
- 	mvneta_setup_rx_prio_map(pp);
- 
--	netdev_set_num_tc(dev, qopt->num_tc);
--	for (i = 0; i < qopt->num_tc; i++)
--		netdev_set_tc_queue(dev, i, qopt->count[i], qopt->offset[i]);
-+	netdev_set_num_tc(dev, mqprio->qopt.num_tc);
-+	for (i = 0; i < mqprio->qopt.num_tc; i++)
-+		netdev_set_tc_queue(dev, i, mqprio->qopt.count[i],
-+				    mqprio->qopt.offset[i]);
- 
- 	return 0;
- }
diff --git a/target/linux/mvebu/patches-5.15/703-net-next-ethernet-marvell-mvnetaMQPrioFlag.patch b/target/linux/mvebu/patches-5.15/703-net-next-ethernet-marvell-mvnetaMQPrioFlag.patch
deleted file mode 100644
index c878a288439216..00000000000000
--- a/target/linux/mvebu/patches-5.15/703-net-next-ethernet-marvell-mvnetaMQPrioFlag.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From e7ca75fe6662f78bfeb0112671c812e4c7b8e214 Mon Sep 17 00:00:00 2001
-From: Maxime Chevallier <maxime.chevallier@bootlin.com>
-Date: Fri, 26 Nov 2021 12:20:54 +0100
-Subject: net: mvneta: Don't force-set the offloading flag
-
-The qopt->hw flag is set by the TC code according to the offloading mode
-asked by user. Don't force-set it in the driver, but instead read it to
-make sure we do what's asked.
-
-Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/ethernet/marvell/mvneta.c | 4 +++-
- 1 file changed, 3 insertions(+), 1 deletion(-)
-
-(limited to 'drivers/net/ethernet/marvell/mvneta.c')
-
---- a/drivers/net/ethernet/marvell/mvneta.c
-+++ b/drivers/net/ethernet/marvell/mvneta.c
-@@ -4973,7 +4973,9 @@ static int mvneta_setup_mqprio(struct ne
- 	u8 num_tc;
- 	int i;
- 
--	mqprio->qopt.hw = TC_MQPRIO_HW_OFFLOAD_TCS;
-+	if (mqprio->qopt.hw != TC_MQPRIO_HW_OFFLOAD_TCS)
-+		return 0;
-+
- 	num_tc = mqprio->qopt.num_tc;
- 
- 	if (num_tc > rxq_number)
diff --git a/target/linux/mvebu/patches-5.15/704-net-next-ethernet-marvell-mvnetaMQPrioQueue.patch b/target/linux/mvebu/patches-5.15/704-net-next-ethernet-marvell-mvnetaMQPrioQueue.patch
deleted file mode 100644
index 546a8486ef0588..00000000000000
--- a/target/linux/mvebu/patches-5.15/704-net-next-ethernet-marvell-mvnetaMQPrioQueue.patch
+++ /dev/null
@@ -1,97 +0,0 @@
-From e9f7099d0730341b24c057acbf545dd019581db6 Mon Sep 17 00:00:00 2001
-From: Maxime Chevallier <maxime.chevallier@bootlin.com>
-Date: Fri, 26 Nov 2021 12:20:55 +0100
-Subject: net: mvneta: Allow having more than one queue per TC
-
-The current mqprio implementation assumed that we are only using one
-queue per TC. Use the offset and count parameters to allow using
-multiple queues per TC. In that case, the controller will use a standard
-round-robin algorithm to pick queues assigned to the same TC, with the
-same priority.
-
-This only applies to VLAN priorities in ingress traffic, each TC
-corresponding to a vlan priority.
-
-Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/ethernet/marvell/mvneta.c | 35 ++++++++++++++++++++---------------
- 1 file changed, 20 insertions(+), 15 deletions(-)
-
-(limited to 'drivers/net/ethernet/marvell/mvneta.c')
-
---- a/drivers/net/ethernet/marvell/mvneta.c
-+++ b/drivers/net/ethernet/marvell/mvneta.c
-@@ -498,7 +498,6 @@ struct mvneta_port {
- 	u8 mcast_count[256];
- 	u16 tx_ring_size;
- 	u16 rx_ring_size;
--	u8 prio_tc_map[8];
- 
- 	phy_interface_t phy_interface;
- 	struct device_node *dn;
-@@ -4955,13 +4954,12 @@ static void mvneta_clear_rx_prio_map(str
- 	mvreg_write(pp, MVNETA_VLAN_PRIO_TO_RXQ, 0);
- }
- 
--static void mvneta_setup_rx_prio_map(struct mvneta_port *pp)
-+static void mvneta_map_vlan_prio_to_rxq(struct mvneta_port *pp, u8 pri, u8 rxq)
- {
--	u32 val = 0;
--	int i;
-+	u32 val = mvreg_read(pp, MVNETA_VLAN_PRIO_TO_RXQ);
- 
--	for (i = 0; i < rxq_number; i++)
--		val |= MVNETA_VLAN_PRIO_RXQ_MAP(i, pp->prio_tc_map[i]);
-+	val &= ~MVNETA_VLAN_PRIO_RXQ_MAP(pri, 0x7);
-+	val |= MVNETA_VLAN_PRIO_RXQ_MAP(pri, rxq);
- 
- 	mvreg_write(pp, MVNETA_VLAN_PRIO_TO_RXQ, val);
- }
-@@ -4970,8 +4968,8 @@ static int mvneta_setup_mqprio(struct ne
- 			       struct tc_mqprio_qopt_offload *mqprio)
- {
- 	struct mvneta_port *pp = netdev_priv(dev);
-+	int rxq, tc;
- 	u8 num_tc;
--	int i;
- 
- 	if (mqprio->qopt.hw != TC_MQPRIO_HW_OFFLOAD_TCS)
- 		return 0;
-@@ -4981,21 +4979,28 @@ static int mvneta_setup_mqprio(struct ne
- 	if (num_tc > rxq_number)
- 		return -EINVAL;
- 
-+	mvneta_clear_rx_prio_map(pp);
-+
- 	if (!num_tc) {
--		mvneta_clear_rx_prio_map(pp);
- 		netdev_reset_tc(dev);
- 		return 0;
- 	}
- 
--	memcpy(pp->prio_tc_map, mqprio->qopt.prio_tc_map,
--	       sizeof(pp->prio_tc_map));
-+	netdev_set_num_tc(dev, mqprio->qopt.num_tc);
- 
--	mvneta_setup_rx_prio_map(pp);
-+	for (tc = 0; tc < mqprio->qopt.num_tc; tc++) {
-+		netdev_set_tc_queue(dev, tc, mqprio->qopt.count[tc],
-+				    mqprio->qopt.offset[tc]);
-+
-+		for (rxq = mqprio->qopt.offset[tc];
-+		     rxq < mqprio->qopt.count[tc] + mqprio->qopt.offset[tc];
-+		     rxq++) {
-+			if (rxq >= rxq_number)
-+				return -EINVAL;
- 
--	netdev_set_num_tc(dev, mqprio->qopt.num_tc);
--	for (i = 0; i < mqprio->qopt.num_tc; i++)
--		netdev_set_tc_queue(dev, i, mqprio->qopt.count[i],
--				    mqprio->qopt.offset[i]);
-+			mvneta_map_vlan_prio_to_rxq(pp, tc, rxq);
-+		}
-+	}
- 
- 	return 0;
- }
diff --git a/target/linux/mvebu/patches-5.15/705-net-next-ethernet-marvell-mvnetaMQPrioTCOffload.patch b/target/linux/mvebu/patches-5.15/705-net-next-ethernet-marvell-mvnetaMQPrioTCOffload.patch
deleted file mode 100644
index 1d4a055a71938e..00000000000000
--- a/target/linux/mvebu/patches-5.15/705-net-next-ethernet-marvell-mvnetaMQPrioTCOffload.patch
+++ /dev/null
@@ -1,182 +0,0 @@
-From 2551dc9e398c37a15e52122d385c29a8b06be45f Mon Sep 17 00:00:00 2001
-From: Maxime Chevallier <maxime.chevallier@bootlin.com>
-Date: Fri, 26 Nov 2021 12:20:56 +0100
-Subject: net: mvneta: Add TC traffic shaping offload
-
-The mvneta controller is able to do some tocken-bucket per-queue traffic
-shaping. This commit adds support for setting these using the TC mqprio
-interface.
-
-The token-bucket parameters are customisable, but the current
-implementation configures them to have a 10kbps resolution for the
-rate limitation, since it allows to cover the whole range of max_rate
-values from 10kbps to 5Gbps with 10kbps increments.
-
-Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/ethernet/marvell/mvneta.c | 120 +++++++++++++++++++++++++++++++++-
- 1 file changed, 119 insertions(+), 1 deletion(-)
-
-(limited to 'drivers/net/ethernet/marvell/mvneta.c')
-
---- a/drivers/net/ethernet/marvell/mvneta.c
-+++ b/drivers/net/ethernet/marvell/mvneta.c
-@@ -248,12 +248,39 @@
- #define      MVNETA_TXQ_SENT_DESC_MASK           0x3fff0000
- #define MVNETA_PORT_TX_RESET                     0x3cf0
- #define      MVNETA_PORT_TX_DMA_RESET            BIT(0)
-+#define MVNETA_TXQ_CMD1_REG			 0x3e00
-+#define      MVNETA_TXQ_CMD1_BW_LIM_SEL_V1	 BIT(3)
-+#define      MVNETA_TXQ_CMD1_BW_LIM_EN		 BIT(0)
-+#define MVNETA_REFILL_NUM_CLK_REG		 0x3e08
-+#define      MVNETA_REFILL_MAX_NUM_CLK		 0x0000ffff
- #define MVNETA_TX_MTU                            0x3e0c
- #define MVNETA_TX_TOKEN_SIZE                     0x3e14
- #define      MVNETA_TX_TOKEN_SIZE_MAX            0xffffffff
-+#define MVNETA_TXQ_BUCKET_REFILL_REG(q)		 (0x3e20 + ((q) << 2))
-+#define      MVNETA_TXQ_BUCKET_REFILL_PERIOD_MASK	0x3ff00000
-+#define      MVNETA_TXQ_BUCKET_REFILL_PERIOD_SHIFT	20
-+#define      MVNETA_TXQ_BUCKET_REFILL_VALUE_MAX	 0x0007ffff
- #define MVNETA_TXQ_TOKEN_SIZE_REG(q)             (0x3e40 + ((q) << 2))
- #define      MVNETA_TXQ_TOKEN_SIZE_MAX           0x7fffffff
- 
-+/* The values of the bucket refill base period and refill period are taken from
-+ * the reference manual, and adds up to a base resolution of 10Kbps. This allows
-+ * to cover all rate-limit values from 10Kbps up to 5Gbps
-+ */
-+
-+/* Base period for the rate limit algorithm */
-+#define MVNETA_TXQ_BUCKET_REFILL_BASE_PERIOD_NS	100
-+
-+/* Number of Base Period to wait between each bucket refill */
-+#define MVNETA_TXQ_BUCKET_REFILL_PERIOD	1000
-+
-+/* The base resolution for rate limiting, in bps. Any max_rate value should be
-+ * a multiple of that value.
-+ */
-+#define MVNETA_TXQ_RATE_LIMIT_RESOLUTION (NSEC_PER_SEC / \
-+					 (MVNETA_TXQ_BUCKET_REFILL_BASE_PERIOD_NS * \
-+					  MVNETA_TXQ_BUCKET_REFILL_PERIOD))
-+
- #define MVNETA_LPI_CTRL_0                        0x2cc0
- #define MVNETA_LPI_CTRL_1                        0x2cc4
- #define      MVNETA_LPI_REQUEST_ENABLE           BIT(0)
-@@ -4964,11 +4991,74 @@ static void mvneta_map_vlan_prio_to_rxq(
- 	mvreg_write(pp, MVNETA_VLAN_PRIO_TO_RXQ, val);
- }
- 
-+static int mvneta_enable_per_queue_rate_limit(struct mvneta_port *pp)
-+{
-+	unsigned long core_clk_rate;
-+	u32 refill_cycles;
-+	u32 val;
-+
-+	core_clk_rate = clk_get_rate(pp->clk);
-+	if (!core_clk_rate)
-+		return -EINVAL;
-+
-+	refill_cycles = MVNETA_TXQ_BUCKET_REFILL_BASE_PERIOD_NS /
-+			(NSEC_PER_SEC / core_clk_rate);
-+
-+	if (refill_cycles > MVNETA_REFILL_MAX_NUM_CLK)
-+		return -EINVAL;
-+
-+	/* Enable bw limit algorithm version 3 */
-+	val = mvreg_read(pp, MVNETA_TXQ_CMD1_REG);
-+	val &= ~(MVNETA_TXQ_CMD1_BW_LIM_SEL_V1 | MVNETA_TXQ_CMD1_BW_LIM_EN);
-+	mvreg_write(pp, MVNETA_TXQ_CMD1_REG, val);
-+
-+	/* Set the base refill rate */
-+	mvreg_write(pp, MVNETA_REFILL_NUM_CLK_REG, refill_cycles);
-+
-+	return 0;
-+}
-+
-+static void mvneta_disable_per_queue_rate_limit(struct mvneta_port *pp)
-+{
-+	u32 val = mvreg_read(pp, MVNETA_TXQ_CMD1_REG);
-+
-+	val |= (MVNETA_TXQ_CMD1_BW_LIM_SEL_V1 | MVNETA_TXQ_CMD1_BW_LIM_EN);
-+	mvreg_write(pp, MVNETA_TXQ_CMD1_REG, val);
-+}
-+
-+static int mvneta_setup_queue_rates(struct mvneta_port *pp, int queue,
-+				    u64 min_rate, u64 max_rate)
-+{
-+	u32 refill_val, rem;
-+	u32 val = 0;
-+
-+	/* Convert to from Bps to bps */
-+	max_rate *= 8;
-+
-+	if (min_rate)
-+		return -EINVAL;
-+
-+	refill_val = div_u64_rem(max_rate, MVNETA_TXQ_RATE_LIMIT_RESOLUTION,
-+				 &rem);
-+
-+	if (rem || !refill_val ||
-+	    refill_val > MVNETA_TXQ_BUCKET_REFILL_VALUE_MAX)
-+		return -EINVAL;
-+
-+	val = refill_val;
-+	val |= (MVNETA_TXQ_BUCKET_REFILL_PERIOD <<
-+		MVNETA_TXQ_BUCKET_REFILL_PERIOD_SHIFT);
-+
-+	mvreg_write(pp, MVNETA_TXQ_BUCKET_REFILL_REG(queue), val);
-+
-+	return 0;
-+}
-+
- static int mvneta_setup_mqprio(struct net_device *dev,
- 			       struct tc_mqprio_qopt_offload *mqprio)
- {
- 	struct mvneta_port *pp = netdev_priv(dev);
--	int rxq, tc;
-+	int rxq, txq, tc, ret;
- 	u8 num_tc;
- 
- 	if (mqprio->qopt.hw != TC_MQPRIO_HW_OFFLOAD_TCS)
-@@ -4982,6 +5072,7 @@ static int mvneta_setup_mqprio(struct ne
- 	mvneta_clear_rx_prio_map(pp);
- 
- 	if (!num_tc) {
-+		mvneta_disable_per_queue_rate_limit(pp);
- 		netdev_reset_tc(dev);
- 		return 0;
- 	}
-@@ -5002,6 +5093,33 @@ static int mvneta_setup_mqprio(struct ne
- 		}
- 	}
- 
-+	if (mqprio->shaper != TC_MQPRIO_SHAPER_BW_RATE) {
-+		mvneta_disable_per_queue_rate_limit(pp);
-+		return 0;
-+	}
-+
-+	if (mqprio->qopt.num_tc > txq_number)
-+		return -EINVAL;
-+
-+	ret = mvneta_enable_per_queue_rate_limit(pp);
-+	if (ret)
-+		return ret;
-+
-+	for (tc = 0; tc < mqprio->qopt.num_tc; tc++) {
-+		for (txq = mqprio->qopt.offset[tc];
-+		     txq < mqprio->qopt.count[tc] + mqprio->qopt.offset[tc];
-+		     txq++) {
-+			if (txq >= txq_number)
-+				return -EINVAL;
-+
-+			ret = mvneta_setup_queue_rates(pp, txq,
-+						       mqprio->min_rate[tc],
-+						       mqprio->max_rate[tc]);
-+			if (ret)
-+				return ret;
-+		}
-+	}
-+
- 	return 0;
- }
- 
diff --git a/target/linux/mvebu/patches-5.15/710-v6.2-phy-marvell-phy-mvebu-a3700-comphy-Reset-COMPHY-regi.patch b/target/linux/mvebu/patches-5.15/710-v6.2-phy-marvell-phy-mvebu-a3700-comphy-Reset-COMPHY-regi.patch
deleted file mode 100644
index a852dc1fc11f78..00000000000000
--- a/target/linux/mvebu/patches-5.15/710-v6.2-phy-marvell-phy-mvebu-a3700-comphy-Reset-COMPHY-regi.patch
+++ /dev/null
@@ -1,50 +0,0 @@
-From b01d622d76134e9401970ffd3fbbb9a7051f976a Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
-Date: Tue, 20 Sep 2022 14:11:54 +0200
-Subject: [PATCH] phy: marvell: phy-mvebu-a3700-comphy: Reset COMPHY registers
- before USB 3.0 power on
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Turris MOX board with older ARM Trusted Firmware version v1.5 is not able
-to detect any USB 3.0 device connected to USB-A port on Mox-A module after
-commit 0a6fc70d76bd ("phy: marvell: phy-mvebu-a3700-comphy: Remove broken
-reset support"). On the other hand USB 2.0 devices connected to the same
-USB-A port are working fine.
-
-It looks as if the older firmware configures COMPHY registers for USB 3.0
-somehow incompatibly for kernel driver. Experiments show that resetting
-COMPHY registers via setting SFT_RST auto-clearing bit in COMPHY_SFT_RESET
-register fixes this issue.
-
-Reset the COMPHY in mvebu_a3700_comphy_usb3_power_on() function as a first
-step after selecting COMPHY lane and USB 3.0 function. With this change
-Turris MOX board can successfully detect USB 3.0 devices again.
-
-Before the above mentioned commit this reset was implemented in PHY reset
-method, so this is the reason why there was no issue with older firmware
-version then.
-
-Fixes: 0a6fc70d76bd ("phy: marvell: phy-mvebu-a3700-comphy: Remove broken reset support")
-Reported-by: Marek Behún <kabel@kernel.org>
-Signed-off-by: Pali Rohár <pali@kernel.org>
-Tested-by: Shin'ichiro Kawasaki <shinichiro.kawasaki@wdc.com>
-Link: https://lore.kernel.org/r/20220920121154.30115-1-pali@kernel.org
-Signed-off-by: Vinod Koul <vkoul@kernel.org>
----
- drivers/phy/marvell/phy-mvebu-a3700-comphy.c | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/drivers/phy/marvell/phy-mvebu-a3700-comphy.c
-+++ b/drivers/phy/marvell/phy-mvebu-a3700-comphy.c
-@@ -826,6 +826,9 @@ mvebu_a3700_comphy_usb3_power_on(struct
- 	if (ret)
- 		return ret;
- 
-+	/* COMPHY register reset (cleared automatically) */
-+	comphy_lane_reg_set(lane, COMPHY_SFT_RESET, SFT_RST, SFT_RST);
-+
- 	/*
- 	 * 0. Set PHY OTG Control(0x5d034), bit 4, Power up OTG module The
- 	 * register belong to UTMI module, so it is set in UTMI phy driver.
diff --git a/target/linux/mvebu/patches-5.15/800-cpuidle-mvebu-indicate-failure-to-enter-deeper-sleep.patch b/target/linux/mvebu/patches-5.15/800-cpuidle-mvebu-indicate-failure-to-enter-deeper-sleep.patch
deleted file mode 100644
index 29f36be460d22a..00000000000000
--- a/target/linux/mvebu/patches-5.15/800-cpuidle-mvebu-indicate-failure-to-enter-deeper-sleep.patch
+++ /dev/null
@@ -1,40 +0,0 @@
-From c28b2d367da8a471482e6a4aa8337ab6369a80c2 Mon Sep 17 00:00:00 2001
-From: Russell King <rmk+kernel@arm.linux.org.uk>
-Date: Sat, 3 Oct 2015 09:13:05 +0100
-Subject: cpuidle: mvebu: indicate failure to enter deeper sleep states
-
-The cpuidle ->enter method expects the return value to be the sleep
-state we entered.  Returning negative numbers or other codes is not
-permissible since coupled CPU idle was merged.
-
-At least some of the mvebu_v7_cpu_suspend() implementations return the
-value from cpu_suspend(), which returns zero if the CPU vectors back
-into the kernel via cpu_resume() (the success case), or the non-zero
-return value of the suspend actor, or one (failure cases).
-
-We do not want to be returning the failure case value back to CPU idle
-as that indicates that we successfully entered one of the deeper idle
-states.  Always return zero instead, indicating that we slept for the
-shortest amount of time.
-
-Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
----
- drivers/cpuidle/cpuidle-mvebu-v7.c | 6 +++++-
- 1 file changed, 5 insertions(+), 1 deletion(-)
-
---- a/drivers/cpuidle/cpuidle-mvebu-v7.c
-+++ b/drivers/cpuidle/cpuidle-mvebu-v7.c
-@@ -39,8 +39,12 @@ static int mvebu_v7_enter_idle(struct cp
- 	ret = mvebu_v7_cpu_suspend(deepidle);
- 	cpu_pm_exit();
- 
-+	/*
-+	 * If we failed to enter the desired state, indicate that we
-+	 * slept lightly.
-+	 */
- 	if (ret)
--		return ret;
-+		return 0;
- 
- 	return index;
- }
diff --git a/target/linux/mvebu/patches-5.15/801-pci-mvebu-time-out-reset-on-link-up.patch b/target/linux/mvebu/patches-5.15/801-pci-mvebu-time-out-reset-on-link-up.patch
deleted file mode 100644
index dba12536993133..00000000000000
--- a/target/linux/mvebu/patches-5.15/801-pci-mvebu-time-out-reset-on-link-up.patch
+++ /dev/null
@@ -1,60 +0,0 @@
-From 287b9df160b6159f8d385424904f8bac501280c1 Mon Sep 17 00:00:00 2001
-From: Russell King <rmk+kernel@armlinux.org.uk>
-Date: Sat, 9 Jul 2016 10:58:16 +0100
-Subject: pci: mvebu: time out reset on link up
-
-If the port reports that the link is up while we are resetting, there's
-little point in waiting for the full duration.
-
-Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
----
- drivers/pci/controller/pci-mvebu.c | 20 ++++++++++++++------
- 1 file changed, 14 insertions(+), 6 deletions(-)
-
---- a/drivers/pci/controller/pci-mvebu.c
-+++ b/drivers/pci/controller/pci-mvebu.c
-@@ -1023,6 +1023,7 @@ static int mvebu_pcie_powerup(struct mve
- 
- 	if (port->reset_gpio) {
- 		u32 reset_udelay = PCI_PM_D3COLD_WAIT * 1000;
-+		unsigned int i;
- 
- 		of_property_read_u32(port->dn, "reset-delay-us",
- 				     &reset_udelay);
-@@ -1030,7 +1031,13 @@ static int mvebu_pcie_powerup(struct mve
- 		udelay(100);
- 
- 		gpiod_set_value_cansleep(port->reset_gpio, 0);
--		msleep(reset_udelay / 1000);
-+		for (i = 0; i < reset_udelay; i += 1000) {
-+			if (mvebu_pcie_link_up(port))
-+				break;
-+			msleep(1);
-+		}
-+
-+		printk("%s: reset completed in %dus\n", port->name, i);
- 	}
- 
- 	return 0;
-@@ -1190,15 +1197,16 @@ static int mvebu_pcie_probe(struct platf
- 		if (!child)
- 			continue;
- 
--		ret = mvebu_pcie_powerup(port);
--		if (ret < 0)
--			continue;
--
- 		port->base = mvebu_pcie_map_registers(pdev, child, port);
- 		if (IS_ERR(port->base)) {
- 			dev_err(dev, "%s: cannot map registers\n", port->name);
- 			port->base = NULL;
--			mvebu_pcie_powerdown(port);
-+			continue;
-+		}
-+
-+		ret = mvebu_pcie_powerup(port);
-+		if (ret < 0) {
-+			port->base = NULL;
- 			continue;
- 		}
- 
diff --git a/target/linux/mvebu/patches-5.15/901-dt-bindings-Add-IEI-vendor-prefix-and-IEI-WT61P803-P.patch b/target/linux/mvebu/patches-5.15/901-dt-bindings-Add-IEI-vendor-prefix-and-IEI-WT61P803-P.patch
deleted file mode 100644
index 3446086cadfed3..00000000000000
--- a/target/linux/mvebu/patches-5.15/901-dt-bindings-Add-IEI-vendor-prefix-and-IEI-WT61P803-P.patch
+++ /dev/null
@@ -1,218 +0,0 @@
-From aa4a0ccc41997f2da172165c92803abace43bd1c Mon Sep 17 00:00:00 2001
-From: Luka Kovacic <luka.kovacic () sartura ! hr>
-Date: Tue, 24 Aug 2021 12:44:32 +0000
-Subject: [PATCH 1/7] dt-bindings: Add IEI vendor prefix and IEI WT61P803
- PUZZLE driver bindings
-
-Add the IEI WT61P803 PUZZLE Device Tree bindings for MFD, HWMON and LED
-drivers. A new vendor prefix is also added accordingly for
-IEI Integration Corp.
-
-Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
-Signed-off-by: Pavo Banicevic <pavo.banicevic@sartura.hr>
-Cc: Luka Perkov <luka.perkov@sartura.hr>
-Cc: Robert Marko <robert.marko@sartura.hr>
----
- .../hwmon/iei,wt61p803-puzzle-hwmon.yaml      | 53 ++++++++++++
- .../leds/iei,wt61p803-puzzle-leds.yaml        | 39 +++++++++
- .../bindings/mfd/iei,wt61p803-puzzle.yaml     | 82 +++++++++++++++++++
- .../devicetree/bindings/vendor-prefixes.yaml  |  2 +
- 4 files changed, 176 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/hwmon/iei,wt61p803-puzzle-hwmon.yaml
- create mode 100644 Documentation/devicetree/bindings/leds/iei,wt61p803-puzzle-leds.yaml
- create mode 100644 Documentation/devicetree/bindings/mfd/iei,wt61p803-puzzle.yaml
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/hwmon/iei,wt61p803-puzzle-hwmon.yaml
-@@ -0,0 +1,53 @@
-+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/hwmon/iei,wt61p803-puzzle-hwmon.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: IEI WT61P803 PUZZLE MCU HWMON module from IEI Integration Corp.
-+
-+maintainers:
-+  - Luka Kovacic <luka.kovacic@sartura.hr>
-+
-+description: |
-+  This module is a part of the IEI WT61P803 PUZZLE MFD device. For more details
-+  see Documentation/devicetree/bindings/mfd/iei,wt61p803-puzzle.yaml.
-+
-+  The HWMON module is a sub-node of the MCU node in the Device Tree.
-+
-+properties:
-+  compatible:
-+    const: iei,wt61p803-puzzle-hwmon
-+
-+  "#address-cells":
-+    const: 1
-+
-+  "#size-cells":
-+    const: 0
-+
-+patternProperties:
-+  "^fan-group@[0-1]$":
-+    type: object
-+    properties:
-+      reg:
-+        minimum: 0
-+        maximum: 1
-+        description:
-+          Fan group ID
-+
-+      cooling-levels:
-+        minItems: 1
-+        maxItems: 255
-+        description:
-+          Cooling levels for the fans (PWM value mapping)
-+    description: |
-+      Properties for each fan group.
-+    required:
-+      - reg
-+
-+required:
-+  - compatible
-+  - "#address-cells"
-+  - "#size-cells"
-+
-+additionalProperties: false
---- /dev/null
-+++ b/Documentation/devicetree/bindings/leds/iei,wt61p803-puzzle-leds.yaml
-@@ -0,0 +1,39 @@
-+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/leds/iei,wt61p803-puzzle-leds.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: IEI WT61P803 PUZZLE MCU LED module from IEI Integration Corp.
-+
-+maintainers:
-+  - Luka Kovacic <luka.kovacic@sartura.hr>
-+
-+description: |
-+  This module is a part of the IEI WT61P803 PUZZLE MFD device. For more details
-+  see Documentation/devicetree/bindings/mfd/iei,wt61p803-puzzle.yaml.
-+
-+  The LED module is a sub-node of the MCU node in the Device Tree.
-+
-+properties:
-+  compatible:
-+    const: iei,wt61p803-puzzle-leds
-+
-+  "#address-cells":
-+    const: 1
-+
-+  "#size-cells":
-+    const: 0
-+
-+  led@0:
-+    type: object
-+    $ref: common.yaml
-+    description: |
-+      Properties for a single LED.
-+
-+required:
-+  - compatible
-+  - "#address-cells"
-+  - "#size-cells"
-+
-+additionalProperties: false
---- /dev/null
-+++ b/Documentation/devicetree/bindings/mfd/iei,wt61p803-puzzle.yaml
-@@ -0,0 +1,82 @@
-+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/mfd/iei,wt61p803-puzzle.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: IEI WT61P803 PUZZLE MCU from IEI Integration Corp.
-+
-+maintainers:
-+  - Luka Kovacic <luka.kovacic@sartura.hr>
-+
-+description: |
-+  IEI WT61P803 PUZZLE MCU is embedded in some IEI Puzzle series boards.
-+  It's used for controlling system power states, fans, LEDs and temperature
-+  sensors.
-+
-+  For Device Tree bindings of other sub-modules (HWMON, LEDs) refer to the
-+  binding documents under the respective subsystem directories.
-+
-+properties:
-+  compatible:
-+    const: iei,wt61p803-puzzle
-+
-+  current-speed:
-+    description:
-+      Serial bus speed in bps
-+    maxItems: 1
-+
-+  enable-beep: true
-+
-+  hwmon:
-+    $ref: /schemas/hwmon/iei,wt61p803-puzzle-hwmon.yaml
-+
-+  leds:
-+    $ref: /schemas/leds/iei,wt61p803-puzzle-leds.yaml
-+
-+required:
-+  - compatible
-+  - current-speed
-+
-+additionalProperties: false
-+
-+examples:
-+  - |
-+    #include <dt-bindings/leds/common.h>
-+    serial {
-+        mcu {
-+            compatible = "iei,wt61p803-puzzle";
-+            current-speed = <115200>;
-+            enable-beep;
-+
-+            leds {
-+                compatible = "iei,wt61p803-puzzle-leds";
-+                #address-cells = <1>;
-+                #size-cells = <0>;
-+
-+                led@0 {
-+                    reg = <0>;
-+                    function = LED_FUNCTION_POWER;
-+                    color = <LED_COLOR_ID_BLUE>;
-+                };
-+            };
-+
-+            hwmon {
-+                compatible = "iei,wt61p803-puzzle-hwmon";
-+                #address-cells = <1>;
-+                #size-cells = <0>;
-+
-+                fan-group@0 {
-+                    #cooling-cells = <2>;
-+                    reg = <0x00>;
-+                    cooling-levels = <64 102 170 230 250>;
-+                };
-+
-+                fan-group@1 {
-+                    #cooling-cells = <2>;
-+                    reg = <0x01>;
-+                    cooling-levels = <64 102 170 230 250>;
-+                };
-+            };
-+        };
-+    };
---- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
-+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
-@@ -519,6 +519,8 @@ patternProperties:
-     description: IC Plus Corp.
-   "^idt,.*":
-     description: Integrated Device Technologies, Inc.
-+  "^iei,.*":
-+    description: IEI Integration Corp.
-   "^ifi,.*":
-     description: Ingenieurburo Fur Ic-Technologie (I/F/I)
-   "^ilitek,.*":
diff --git a/target/linux/mvebu/patches-5.15/902-drivers-mfd-Add-a-driver-for-IEI-WT61P803-PUZZLE-MCU.patch b/target/linux/mvebu/patches-5.15/902-drivers-mfd-Add-a-driver-for-IEI-WT61P803-PUZZLE-MCU.patch
deleted file mode 100644
index 0e546b426edd0d..00000000000000
--- a/target/linux/mvebu/patches-5.15/902-drivers-mfd-Add-a-driver-for-IEI-WT61P803-PUZZLE-MCU.patch
+++ /dev/null
@@ -1,1034 +0,0 @@
-From 692cfa85272dd12995b427c0a7a585ced5d54f32 Mon Sep 17 00:00:00 2001
-From: Luka Kovacic <luka.kovacic () sartura ! hr>
-Date: Tue, 24 Aug 2021 12:44:33 +0000
-Subject: [PATCH 2/7] drivers: mfd: Add a driver for IEI WT61P803 PUZZLE MCU
-
-Add a driver for the IEI WT61P803 PUZZLE microcontroller, used in some
-IEI Puzzle series devices. The microcontroller controls system power,
-temperature sensors, fans and LEDs.
-
-This driver implements the core functionality for device communication
-over the system serial (serdev bus). It handles MCU messages and the
-internal MCU properties. Some properties can be managed over sysfs.
-
-Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
-Signed-off-by: Pavo Banicevic <pavo.banicevic@sartura.hr>
-Cc: Luka Perkov <luka.perkov@sartura.hr>
-Cc: Robert Marko <robert.marko@sartura.hr>
----
- drivers/mfd/Kconfig                     |   8 +
- drivers/mfd/Makefile                    |   1 +
- drivers/mfd/iei-wt61p803-puzzle.c       | 908 ++++++++++++++++++++++++
- include/linux/mfd/iei-wt61p803-puzzle.h |  66 ++
- 4 files changed, 983 insertions(+)
- create mode 100644 drivers/mfd/iei-wt61p803-puzzle.c
- create mode 100644 include/linux/mfd/iei-wt61p803-puzzle.h
-
---- a/drivers/mfd/Kconfig
-+++ b/drivers/mfd/Kconfig
-@@ -2189,6 +2189,15 @@ config SGI_MFD_IOC3
- 	  If you have an SGI Origin, Octane, or a PCI IOC3 card,
- 	  then say Y. Otherwise say N.
- 
-+config MFD_IEI_WT61P803_PUZZLE
-+	tristate "IEI WT61P803 PUZZLE MCU driver"
-+	depends on SERIAL_DEV_BUS
-+	select MFD_CORE
-+	help
-+	  IEI WT61P803 PUZZLE is a system power management microcontroller
-+	  used for fan control, temperature sensor reading, LED control
-+	  and system identification.
-+
- config MFD_INTEL_M10_BMC
- 	tristate "Intel MAX 10 Board Management Controller"
- 	depends on SPI_MASTER
---- a/drivers/mfd/Makefile
-+++ b/drivers/mfd/Makefile
-@@ -237,6 +237,7 @@ obj-$(CONFIG_MFD_DLN2)		+= dln2.o
- obj-$(CONFIG_MFD_RT4831)	+= rt4831.o
- obj-$(CONFIG_MFD_RT5033)	+= rt5033.o
- obj-$(CONFIG_MFD_SKY81452)	+= sky81452.o
-+obj-$(CONFIG_MFD_IEI_WT61P803_PUZZLE)	+= iei-wt61p803-puzzle.o
- 
- intel-soc-pmic-objs		:= intel_soc_pmic_core.o intel_soc_pmic_crc.o
- obj-$(CONFIG_INTEL_SOC_PMIC)	+= intel-soc-pmic.o
---- /dev/null
-+++ b/drivers/mfd/iei-wt61p803-puzzle.c
-@@ -0,0 +1,908 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+/* IEI WT61P803 PUZZLE MCU Driver
-+ * System management microcontroller for fan control, temperature sensor reading,
-+ * LED control and system identification on IEI Puzzle series ARM-based appliances.
-+ *
-+ * Copyright (C) 2020 Sartura Ltd.
-+ * Author: Luka Kovacic <luka.kovacic@sartura.hr>
-+ */
-+
-+#include <linux/atomic.h>
-+#include <linux/delay.h>
-+#include <linux/export.h>
-+#include <linux/init.h>
-+#include <linux/kernel.h>
-+#include <linux/mfd/core.h>
-+#include <linux/mfd/iei-wt61p803-puzzle.h>
-+#include <linux/mod_devicetable.h>
-+#include <linux/module.h>
-+#include <linux/of_platform.h>
-+#include <linux/property.h>
-+#include <linux/sched.h>
-+#include <linux/serdev.h>
-+#include <linux/slab.h>
-+#include <linux/sysfs.h>
-+#include <asm/unaligned.h>
-+
-+/* start, payload and XOR checksum at end */
-+#define IEI_WT61P803_PUZZLE_MAX_COMMAND_LENGTH	(1 + 20 + 1)
-+#define IEI_WT61P803_PUZZLE_RESP_BUF_SIZE	512
-+
-+#define IEI_WT61P803_PUZZLE_MAC_LENGTH			17
-+#define IEI_WT61P803_PUZZLE_SN_LENGTH			36
-+#define IEI_WT61P803_PUZZLE_VERSION_LENGTH		 6
-+#define IEI_WT61P803_PUZZLE_BUILD_INFO_LENGTH		16
-+#define IEI_WT61P803_PUZZLE_PROTOCOL_VERSION_LENGTH	 8
-+#define IEI_WT61P803_PUZZLE_NB_MAC			 8
-+
-+/* Use HZ as a timeout value throughout the driver */
-+#define IEI_WT61P803_PUZZLE_GENERAL_TIMEOUT HZ
-+
-+enum iei_wt61p803_puzzle_attribute_type {
-+	IEI_WT61P803_PUZZLE_VERSION,
-+	IEI_WT61P803_PUZZLE_BUILD_INFO,
-+	IEI_WT61P803_PUZZLE_BOOTLOADER_MODE,
-+	IEI_WT61P803_PUZZLE_PROTOCOL_VERSION,
-+	IEI_WT61P803_PUZZLE_SERIAL_NUMBER,
-+	IEI_WT61P803_PUZZLE_MAC_ADDRESS,
-+	IEI_WT61P803_PUZZLE_AC_RECOVERY_STATUS,
-+	IEI_WT61P803_PUZZLE_POWER_LOSS_RECOVERY,
-+	IEI_WT61P803_PUZZLE_POWER_STATUS,
-+};
-+
-+struct iei_wt61p803_puzzle_device_attribute {
-+	struct device_attribute dev_attr;
-+	enum iei_wt61p803_puzzle_attribute_type type;
-+	u8 index;
-+};
-+
-+/**
-+ * struct iei_wt61p803_puzzle_mcu_status - MCU flags state
-+ * @ac_recovery_status_flag:	AC Recovery Status Flag
-+ * @power_loss_recovery:	System recovery after power loss
-+ * @power_status:		System Power-on Method
-+ */
-+struct iei_wt61p803_puzzle_mcu_status {
-+	u8 ac_recovery_status_flag;
-+	u8 power_loss_recovery;
-+	u8 power_status;
-+};
-+
-+/**
-+ * struct iei_wt61p803_puzzle_reply - MCU reply
-+ * @size:	Size of the MCU reply
-+ * @data:	Full MCU reply buffer
-+ * @state:	Current state of the packet
-+ * @received:	Was the response fullfilled
-+ */
-+struct iei_wt61p803_puzzle_reply {
-+	size_t size;
-+	unsigned char data[IEI_WT61P803_PUZZLE_RESP_BUF_SIZE];
-+	struct completion received;
-+};
-+
-+/**
-+ * struct iei_wt61p803_puzzle_mcu_version - MCU version status
-+ * @version:		Primary firmware version
-+ * @build_info:		Build date and time
-+ * @bootloader_mode:	Status of the MCU operation
-+ * @protocol_version:	MCU communication protocol version
-+ * @serial_number:	Device factory serial number
-+ * @mac_address:	Device factory MAC addresses
-+ *
-+ * Last element of arrays is reserved for '\0'.
-+ */
-+struct iei_wt61p803_puzzle_mcu_version {
-+	char version[IEI_WT61P803_PUZZLE_VERSION_LENGTH + 1];
-+	char build_info[IEI_WT61P803_PUZZLE_BUILD_INFO_LENGTH + 1];
-+	bool bootloader_mode;
-+	char protocol_version[IEI_WT61P803_PUZZLE_PROTOCOL_VERSION_LENGTH + 1];
-+	char serial_number[IEI_WT61P803_PUZZLE_SN_LENGTH + 1];
-+	char mac_address[IEI_WT61P803_PUZZLE_NB_MAC][IEI_WT61P803_PUZZLE_MAC_LENGTH + 1];
-+};
-+
-+/**
-+ * struct iei_wt61p803_puzzle - IEI WT61P803 PUZZLE MCU Driver
-+ * @serdev:		Pointer to underlying serdev device
-+ * @dev:		Pointer to underlying dev device
-+ * @reply_lock:		Reply mutex lock
-+ * @reply:		Pointer to the iei_wt61p803_puzzle_reply struct
-+ * @version:		MCU version related data
-+ * @status:		MCU status related data
-+ * @response_buffer	Command response buffer allocation
-+ * @lock		General member mutex lock
-+ */
-+struct iei_wt61p803_puzzle {
-+	struct serdev_device *serdev;
-+	struct device *dev;
-+	struct mutex reply_lock; /* lock to prevent multiple firmware calls */
-+	struct iei_wt61p803_puzzle_reply *reply;
-+	struct iei_wt61p803_puzzle_mcu_version version;
-+	struct iei_wt61p803_puzzle_mcu_status status;
-+	unsigned char response_buffer[IEI_WT61P803_PUZZLE_BUF_SIZE];
-+	struct mutex lock; /* lock to protect response buffer */
-+};
-+
-+static unsigned char iei_wt61p803_puzzle_checksum(unsigned char *buf, size_t len)
-+{
-+	unsigned char checksum = 0;
-+	size_t i;
-+
-+	for (i = 0; i < len; i++)
-+		checksum ^= buf[i];
-+	return checksum;
-+}
-+
-+static int iei_wt61p803_puzzle_process_resp(struct iei_wt61p803_puzzle *mcu,
-+					    const unsigned char *raw_resp_data, size_t size)
-+{
-+	unsigned char checksum;
-+
-+	/* Check the incoming frame header */
-+	if (!(raw_resp_data[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START ||
-+	      raw_resp_data[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START_OTHER ||
-+	     (raw_resp_data[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_EEPROM &&
-+	      raw_resp_data[1] == IEI_WT61P803_PUZZLE_CMD_EEPROM_READ))) {
-+		if (mcu->reply->size + size >= sizeof(mcu->reply->data))
-+			return -EIO;
-+
-+		/* Append the frame to existing data */
-+		memcpy(mcu->reply->data + mcu->reply->size, raw_resp_data, size);
-+		mcu->reply->size += size;
-+	} else {
-+		if (size >= sizeof(mcu->reply->data))
-+			return -EIO;
-+
-+		/* Start processing a new frame */
-+		memcpy(mcu->reply->data, raw_resp_data, size);
-+		mcu->reply->size = size;
-+	}
-+
-+	checksum = iei_wt61p803_puzzle_checksum(mcu->reply->data, mcu->reply->size - 1);
-+	if (checksum != mcu->reply->data[mcu->reply->size - 1]) {
-+		/* The checksum isn't matched yet, wait for new frames */
-+		return size;
-+	}
-+
-+	/* Received all the data */
-+	complete(&mcu->reply->received);
-+
-+	return size;
-+}
-+
-+static int iei_wt61p803_puzzle_recv_buf(struct serdev_device *serdev,
-+					const unsigned char *data, size_t size)
-+{
-+	struct iei_wt61p803_puzzle *mcu = serdev_device_get_drvdata(serdev);
-+	int ret;
-+
-+	ret = iei_wt61p803_puzzle_process_resp(mcu, data, size);
-+	/* Return the number of processed bytes if function returns error,
-+	 * discard the remaining incoming data, since the frame this data
-+	 * belongs to is broken anyway
-+	 */
-+	if (ret < 0)
-+		return size;
-+
-+	return ret;
-+}
-+
-+static const struct serdev_device_ops iei_wt61p803_puzzle_serdev_device_ops = {
-+	.receive_buf  = iei_wt61p803_puzzle_recv_buf,
-+	.write_wakeup = serdev_device_write_wakeup,
-+};
-+
-+/**
-+ * iei_wt61p803_puzzle_write_command_watchdog() - Watchdog of the normal cmd
-+ * @mcu: Pointer to the iei_wt61p803_puzzle core MFD struct
-+ * @cmd: Pointer to the char array to send (size should be content + 1 (xor))
-+ * @size: Size of the cmd char array
-+ * @reply_data: Pointer to the reply/response data array (should be allocated)
-+ * @reply_size: Pointer to size_t (size of reply_data)
-+ * @retry_count: Number of times to retry sending the command to the MCU
-+ */
-+int iei_wt61p803_puzzle_write_command_watchdog(struct iei_wt61p803_puzzle *mcu,
-+					       unsigned char *cmd, size_t size,
-+					       unsigned char *reply_data,
-+					       size_t *reply_size, int retry_count)
-+{
-+	struct device *dev = &mcu->serdev->dev;
-+	int ret, i;
-+
-+	for (i = 0; i < retry_count; i++) {
-+		ret = iei_wt61p803_puzzle_write_command(mcu, cmd, size,
-+							reply_data, reply_size);
-+		if (ret != -ETIMEDOUT)
-+			return ret;
-+	}
-+
-+	dev_err(dev, "Command response timed out. Retries: %d\n", retry_count);
-+
-+	return -ETIMEDOUT;
-+}
-+EXPORT_SYMBOL_GPL(iei_wt61p803_puzzle_write_command_watchdog);
-+
-+/**
-+ * iei_wt61p803_puzzle_write_command() - Send a structured command to the MCU
-+ * @mcu: Pointer to the iei_wt61p803_puzzle core MFD struct
-+ * @cmd: Pointer to the char array to send (size should be content + 1 (xor))
-+ * @size: Size of the cmd char array
-+ * @reply_data: Pointer to the reply/response data array (should be allocated)
-+ *
-+ * Sends a structured command to the MCU.
-+ */
-+int iei_wt61p803_puzzle_write_command(struct iei_wt61p803_puzzle *mcu,
-+				      unsigned char *cmd, size_t size,
-+				      unsigned char *reply_data,
-+				      size_t *reply_size)
-+{
-+	struct device *dev = &mcu->serdev->dev;
-+	int ret;
-+
-+	if (size <= 1 || size > IEI_WT61P803_PUZZLE_MAX_COMMAND_LENGTH)
-+		return -EINVAL;
-+
-+	mutex_lock(&mcu->reply_lock);
-+
-+	cmd[size - 1] = iei_wt61p803_puzzle_checksum(cmd, size - 1);
-+
-+	/* Initialize reply struct */
-+	reinit_completion(&mcu->reply->received);
-+	mcu->reply->size = 0;
-+	usleep_range(2000, 10000);
-+	serdev_device_write_flush(mcu->serdev);
-+	ret = serdev_device_write_buf(mcu->serdev, cmd, size);
-+	if (ret < 0)
-+		goto exit;
-+
-+	serdev_device_wait_until_sent(mcu->serdev, IEI_WT61P803_PUZZLE_GENERAL_TIMEOUT);
-+	ret = wait_for_completion_timeout(&mcu->reply->received,
-+					  IEI_WT61P803_PUZZLE_GENERAL_TIMEOUT);
-+	if (ret == 0) {
-+		dev_err(dev, "Command reply receive timeout\n");
-+		ret = -ETIMEDOUT;
-+		goto exit;
-+	}
-+
-+	*reply_size = mcu->reply->size;
-+	/* Copy the received data, as it will not be available after a new frame is received */
-+	memcpy(reply_data, mcu->reply->data, mcu->reply->size);
-+	ret = 0;
-+exit:
-+	mutex_unlock(&mcu->reply_lock);
-+	return ret;
-+}
-+EXPORT_SYMBOL_GPL(iei_wt61p803_puzzle_write_command);
-+
-+static int iei_wt61p803_puzzle_buzzer(struct iei_wt61p803_puzzle *mcu, bool long_beep)
-+{
-+	unsigned char *resp_buf = mcu->response_buffer;
-+	unsigned char buzzer_cmd[4] = {};
-+	size_t reply_size;
-+	int ret;
-+
-+	buzzer_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START;
-+	buzzer_cmd[1] = IEI_WT61P803_PUZZLE_CMD_FUNCTION_SINGLE;
-+	buzzer_cmd[2] = long_beep ? '3' : '2'; /* Buzzer 1.5 / 0.5 second beep */
-+
-+	mutex_lock(&mcu->lock);
-+	ret = iei_wt61p803_puzzle_write_command(mcu, buzzer_cmd, sizeof(buzzer_cmd),
-+						resp_buf, &reply_size);
-+	if (ret)
-+		goto exit;
-+
-+	if (reply_size != 3) {
-+		ret = -EIO;
-+		goto exit;
-+	}
-+
-+	if (!(resp_buf[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START &&
-+	      resp_buf[1] == IEI_WT61P803_PUZZLE_CMD_RESPONSE_OK &&
-+	      resp_buf[2] == IEI_WT61P803_PUZZLE_CHECKSUM_RESPONSE_OK)) {
-+		ret = -EPROTO;
-+		goto exit;
-+	}
-+exit:
-+	mutex_unlock(&mcu->lock);
-+	return ret;
-+}
-+
-+static int iei_wt61p803_puzzle_get_version(struct iei_wt61p803_puzzle *mcu)
-+{
-+	unsigned char version_cmd[3] = {
-+		IEI_WT61P803_PUZZLE_CMD_HEADER_START_OTHER,
-+		IEI_WT61P803_PUZZLE_CMD_OTHER_VERSION,
-+	};
-+	unsigned char build_info_cmd[3] = {
-+		IEI_WT61P803_PUZZLE_CMD_HEADER_START_OTHER,
-+		IEI_WT61P803_PUZZLE_CMD_OTHER_BUILD,
-+	};
-+	unsigned char bootloader_mode_cmd[3] = {
-+		IEI_WT61P803_PUZZLE_CMD_HEADER_START_OTHER,
-+		IEI_WT61P803_PUZZLE_CMD_OTHER_BOOTLOADER_MODE,
-+	};
-+	unsigned char protocol_version_cmd[3] = {
-+		IEI_WT61P803_PUZZLE_CMD_HEADER_START_OTHER,
-+		IEI_WT61P803_PUZZLE_CMD_OTHER_PROTOCOL_VERSION,
-+	};
-+	unsigned char *rb = mcu->response_buffer;
-+	size_t reply_size;
-+	int ret;
-+
-+	mutex_lock(&mcu->lock);
-+
-+	ret = iei_wt61p803_puzzle_write_command(mcu, version_cmd, sizeof(version_cmd),
-+						rb, &reply_size);
-+	if (ret)
-+		goto err;
-+	if (reply_size < 7) {
-+		ret = -EIO;
-+		goto err;
-+	}
-+	sprintf(mcu->version.version, "v%c.%.3s", rb[2], &rb[3]);
-+
-+	ret = iei_wt61p803_puzzle_write_command(mcu, build_info_cmd,
-+						sizeof(build_info_cmd),	rb,
-+						&reply_size);
-+	if (ret)
-+		goto err;
-+	if (reply_size < 15) {
-+		ret = -EIO;
-+		goto err;
-+	}
-+	sprintf(mcu->version.build_info, "%c%c/%c%c/%.4s %c%c:%c%c",
-+		rb[8], rb[9], rb[6], rb[7], &rb[2], rb[10], rb[11],
-+		rb[12], rb[13]);
-+
-+	ret = iei_wt61p803_puzzle_write_command(mcu, bootloader_mode_cmd,
-+						sizeof(bootloader_mode_cmd), rb,
-+						&reply_size);
-+	if (ret)
-+		goto err;
-+	if (reply_size < 4) {
-+		ret = -EIO;
-+		goto err;
-+	}
-+	if (rb[2] == IEI_WT61P803_PUZZLE_CMD_OTHER_MODE_APPS)
-+		mcu->version.bootloader_mode = false;
-+	else if (rb[2] == IEI_WT61P803_PUZZLE_CMD_OTHER_MODE_BOOTLOADER)
-+		mcu->version.bootloader_mode = true;
-+
-+	ret = iei_wt61p803_puzzle_write_command(mcu, protocol_version_cmd,
-+						sizeof(protocol_version_cmd), rb,
-+						&reply_size);
-+	if (ret)
-+		goto err;
-+	if (reply_size < 9) {
-+		ret = -EIO;
-+		goto err;
-+	}
-+	sprintf(mcu->version.protocol_version, "v%c.%c%c%c%c%c",
-+		rb[7], rb[6], rb[5], rb[4], rb[3], rb[2]);
-+err:
-+	mutex_unlock(&mcu->lock);
-+	return ret;
-+}
-+
-+static int iei_wt61p803_puzzle_get_mcu_status(struct iei_wt61p803_puzzle *mcu)
-+{
-+	unsigned char mcu_status_cmd[5] = {
-+		IEI_WT61P803_PUZZLE_CMD_HEADER_START,
-+		IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER,
-+		IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_STATUS,
-+		IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_STATUS,
-+	};
-+	unsigned char *resp_buf = mcu->response_buffer;
-+	size_t reply_size;
-+	int ret;
-+
-+	mutex_lock(&mcu->lock);
-+	ret = iei_wt61p803_puzzle_write_command(mcu, mcu_status_cmd, sizeof(mcu_status_cmd),
-+						resp_buf, &reply_size);
-+	if (ret)
-+		goto exit;
-+	if (reply_size < 20) {
-+		ret = -EIO;
-+		goto exit;
-+	}
-+
-+	/* Response format:
-+	 * (IDX	RESPONSE)
-+	 * 0	@
-+	 * 1	O
-+	 * 2	S
-+	 * 3	S
-+	 * ...
-+	 * 5	AC Recovery Status Flag
-+	 * ...
-+	 * 10	Power Loss Recovery
-+	 * ...
-+	 * 19	Power Status (system power on method)
-+	 * 20	XOR checksum
-+	 */
-+	if (resp_buf[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START &&
-+	    resp_buf[1] == IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER &&
-+	    resp_buf[2] == IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_STATUS &&
-+	    resp_buf[3] == IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_STATUS) {
-+		mcu->status.ac_recovery_status_flag = resp_buf[5];
-+		mcu->status.power_loss_recovery = resp_buf[10];
-+		mcu->status.power_status = resp_buf[19];
-+	}
-+exit:
-+	mutex_unlock(&mcu->lock);
-+	return ret;
-+}
-+
-+static int iei_wt61p803_puzzle_get_serial_number(struct iei_wt61p803_puzzle *mcu)
-+{
-+	unsigned char *resp_buf = mcu->response_buffer;
-+	unsigned char serial_number_cmd[5] = {
-+		IEI_WT61P803_PUZZLE_CMD_HEADER_EEPROM,
-+		IEI_WT61P803_PUZZLE_CMD_EEPROM_READ,
-+		0x00,	/* EEPROM read address */
-+		0x24,	/* Data length */
-+	};
-+	size_t reply_size;
-+	int ret;
-+
-+	mutex_lock(&mcu->lock);
-+	ret = iei_wt61p803_puzzle_write_command(mcu, serial_number_cmd,
-+						sizeof(serial_number_cmd),
-+						resp_buf, &reply_size);
-+	if (ret)
-+		goto err;
-+
-+	if (reply_size < IEI_WT61P803_PUZZLE_SN_LENGTH + 4) {
-+		ret = -EIO;
-+		goto err;
-+	}
-+
-+	sprintf(mcu->version.serial_number, "%.*s",
-+		IEI_WT61P803_PUZZLE_SN_LENGTH, resp_buf + 4);
-+err:
-+	mutex_unlock(&mcu->lock);
-+	return ret;
-+}
-+
-+static int iei_wt61p803_puzzle_write_serial_number(struct iei_wt61p803_puzzle *mcu,
-+						   unsigned char serial_number[36])
-+{
-+	unsigned char *resp_buf = mcu->response_buffer;
-+	unsigned char serial_number_header[4] = {
-+		IEI_WT61P803_PUZZLE_CMD_HEADER_EEPROM,
-+		IEI_WT61P803_PUZZLE_CMD_EEPROM_WRITE,
-+		0x00,	/* EEPROM write address */
-+		0xC,	/* Data length */
-+	};
-+	unsigned char serial_number_cmd[4 + 12 + 1]; /* header, serial number, XOR checksum */
-+	int ret, sn_counter;
-+	size_t reply_size;
-+
-+	/* The MCU can only handle 22 byte messages, send the S/N in 12 byte chunks */
-+	mutex_lock(&mcu->lock);
-+	for (sn_counter = 0; sn_counter < 3; sn_counter++) {
-+		serial_number_header[2] = 0x0 + 0xC * sn_counter;
-+
-+		memcpy(serial_number_cmd, serial_number_header, sizeof(serial_number_header));
-+		memcpy(serial_number_cmd + sizeof(serial_number_header),
-+		       serial_number + 0xC * sn_counter, 0xC);
-+
-+		ret = iei_wt61p803_puzzle_write_command(mcu, serial_number_cmd,
-+							sizeof(serial_number_cmd),
-+							resp_buf, &reply_size);
-+		if (ret)
-+			goto err;
-+		if (reply_size != 3) {
-+			ret = -EIO;
-+			goto err;
-+		}
-+		if (!(resp_buf[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START &&
-+		      resp_buf[1] == IEI_WT61P803_PUZZLE_CMD_RESPONSE_OK &&
-+		      resp_buf[2] == IEI_WT61P803_PUZZLE_CHECKSUM_RESPONSE_OK)) {
-+			ret = -EPROTO;
-+			goto err;
-+		}
-+	}
-+
-+	sprintf(mcu->version.serial_number, "%.*s",
-+		IEI_WT61P803_PUZZLE_SN_LENGTH, serial_number);
-+err:
-+	mutex_unlock(&mcu->lock);
-+	return ret;
-+}
-+
-+static int iei_wt61p803_puzzle_get_mac_address(struct iei_wt61p803_puzzle *mcu, int index)
-+{
-+	unsigned char *resp_buf = mcu->response_buffer;
-+	unsigned char mac_address_cmd[5] = {
-+		IEI_WT61P803_PUZZLE_CMD_HEADER_EEPROM,
-+		IEI_WT61P803_PUZZLE_CMD_EEPROM_READ,
-+		0x00,	/* EEPROM read address */
-+		0x11,	/* Data length */
-+	};
-+	size_t reply_size;
-+	int ret;
-+
-+	mutex_lock(&mcu->lock);
-+	mac_address_cmd[2] = 0x24 + 0x11 * index;
-+
-+	ret = iei_wt61p803_puzzle_write_command(mcu, mac_address_cmd,
-+						sizeof(mac_address_cmd),
-+						resp_buf, &reply_size);
-+	if (ret)
-+		goto err;
-+
-+	if (reply_size < 22) {
-+		ret = -EIO;
-+		goto err;
-+	}
-+
-+	sprintf(mcu->version.mac_address[index], "%.*s",
-+		IEI_WT61P803_PUZZLE_MAC_LENGTH, resp_buf + 4);
-+err:
-+	mutex_unlock(&mcu->lock);
-+	return ret;
-+}
-+
-+static int
-+iei_wt61p803_puzzle_write_mac_address(struct iei_wt61p803_puzzle *mcu,
-+				      unsigned char mac_address[IEI_WT61P803_PUZZLE_MAC_LENGTH],
-+				      int mac_address_idx)
-+{
-+	unsigned char mac_address_cmd[4 + IEI_WT61P803_PUZZLE_MAC_LENGTH + 1];
-+	unsigned char *resp_buf = mcu->response_buffer;
-+	unsigned char mac_address_header[4] = {
-+		IEI_WT61P803_PUZZLE_CMD_HEADER_EEPROM,
-+		IEI_WT61P803_PUZZLE_CMD_EEPROM_WRITE,
-+		0x00,	/* EEPROM write address */
-+		0x11,	/* Data length */
-+	};
-+	size_t reply_size;
-+	int ret;
-+
-+	if (mac_address_idx < 0 || mac_address_idx >= IEI_WT61P803_PUZZLE_NB_MAC)
-+		return -EINVAL;
-+
-+	mac_address_header[2] = 0x24 + 0x11 * mac_address_idx;
-+
-+	/* Concat mac_address_header, mac_address to mac_address_cmd */
-+	memcpy(mac_address_cmd, mac_address_header, sizeof(mac_address_header));
-+	memcpy(mac_address_cmd + sizeof(mac_address_header), mac_address,
-+	       IEI_WT61P803_PUZZLE_MAC_LENGTH);
-+
-+	mutex_lock(&mcu->lock);
-+	ret = iei_wt61p803_puzzle_write_command(mcu, mac_address_cmd,
-+						sizeof(mac_address_cmd),
-+						resp_buf, &reply_size);
-+	if (ret)
-+		goto err;
-+	if (reply_size != 3) {
-+		ret = -EIO;
-+		goto err;
-+	}
-+	if (!(resp_buf[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START &&
-+	      resp_buf[1] == IEI_WT61P803_PUZZLE_CMD_RESPONSE_OK &&
-+	      resp_buf[2] == IEI_WT61P803_PUZZLE_CHECKSUM_RESPONSE_OK)) {
-+		ret = -EPROTO;
-+		goto err;
-+	}
-+
-+	sprintf(mcu->version.mac_address[mac_address_idx], "%.*s",
-+		IEI_WT61P803_PUZZLE_MAC_LENGTH, mac_address);
-+err:
-+	mutex_unlock(&mcu->lock);
-+	return ret;
-+}
-+
-+static int iei_wt61p803_puzzle_write_power_loss_recovery(struct iei_wt61p803_puzzle *mcu,
-+							 int power_loss_recovery_action)
-+{
-+	unsigned char *resp_buf = mcu->response_buffer;
-+	unsigned char power_loss_recovery_cmd[5] = {};
-+	size_t reply_size;
-+	int ret;
-+
-+	if (power_loss_recovery_action < 0 || power_loss_recovery_action > 4)
-+		return -EINVAL;
-+
-+	power_loss_recovery_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START;
-+	power_loss_recovery_cmd[1] = IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER;
-+	power_loss_recovery_cmd[2] = IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_POWER_LOSS;
-+	power_loss_recovery_cmd[3] = hex_asc[power_loss_recovery_action];
-+
-+	mutex_lock(&mcu->lock);
-+	ret = iei_wt61p803_puzzle_write_command(mcu, power_loss_recovery_cmd,
-+						sizeof(power_loss_recovery_cmd),
-+						resp_buf, &reply_size);
-+	if (ret)
-+		goto exit;
-+	mcu->status.power_loss_recovery = power_loss_recovery_action;
-+exit:
-+	mutex_unlock(&mcu->lock);
-+	return ret;
-+}
-+
-+#define to_puzzle_dev_attr(_attr) \
-+	container_of(_attr, struct iei_wt61p803_puzzle_device_attribute, dev_attr)
-+
-+static ssize_t show_output(struct device *dev,
-+			   struct device_attribute *attr, char *buf)
-+{
-+	struct iei_wt61p803_puzzle *mcu = dev_get_drvdata(dev);
-+	struct iei_wt61p803_puzzle_device_attribute *pattr = to_puzzle_dev_attr(attr);
-+	int ret;
-+
-+	switch (pattr->type) {
-+	case IEI_WT61P803_PUZZLE_VERSION:
-+		return scnprintf(buf, PAGE_SIZE, "%s\n", mcu->version.version);
-+	case IEI_WT61P803_PUZZLE_BUILD_INFO:
-+		return scnprintf(buf, PAGE_SIZE, "%s\n", mcu->version.build_info);
-+	case IEI_WT61P803_PUZZLE_BOOTLOADER_MODE:
-+		return scnprintf(buf, PAGE_SIZE, "%d\n", mcu->version.bootloader_mode);
-+	case IEI_WT61P803_PUZZLE_PROTOCOL_VERSION:
-+		return scnprintf(buf, PAGE_SIZE, "%s\n", mcu->version.protocol_version);
-+	case IEI_WT61P803_PUZZLE_SERIAL_NUMBER:
-+		ret = iei_wt61p803_puzzle_get_serial_number(mcu);
-+		if (!ret)
-+			ret = scnprintf(buf, PAGE_SIZE, "%s\n", mcu->version.serial_number);
-+		else
-+			ret = 0;
-+		return ret;
-+	case IEI_WT61P803_PUZZLE_MAC_ADDRESS:
-+		ret = iei_wt61p803_puzzle_get_mac_address(mcu, pattr->index);
-+		if (!ret)
-+			ret = scnprintf(buf, PAGE_SIZE, "%s\n",
-+					mcu->version.mac_address[pattr->index]);
-+		else
-+			ret = 0;
-+		return ret;
-+	case IEI_WT61P803_PUZZLE_AC_RECOVERY_STATUS:
-+	case IEI_WT61P803_PUZZLE_POWER_LOSS_RECOVERY:
-+	case IEI_WT61P803_PUZZLE_POWER_STATUS:
-+		ret = iei_wt61p803_puzzle_get_mcu_status(mcu);
-+		if (ret)
-+			return ret;
-+
-+		mutex_lock(&mcu->lock);
-+		switch (pattr->type) {
-+		case IEI_WT61P803_PUZZLE_AC_RECOVERY_STATUS:
-+			ret = scnprintf(buf, PAGE_SIZE, "%x\n",
-+					mcu->status.ac_recovery_status_flag);
-+			break;
-+		case IEI_WT61P803_PUZZLE_POWER_LOSS_RECOVERY:
-+			ret = scnprintf(buf, PAGE_SIZE, "%x\n", mcu->status.power_loss_recovery);
-+			break;
-+		case IEI_WT61P803_PUZZLE_POWER_STATUS:
-+			ret = scnprintf(buf, PAGE_SIZE, "%x\n", mcu->status.power_status);
-+			break;
-+		default:
-+			ret = 0;
-+			break;
-+		}
-+		mutex_unlock(&mcu->lock);
-+		return ret;
-+	default:
-+		return 0;
-+	}
-+
-+	return 0;
-+}
-+
-+static ssize_t store_output(struct device *dev,
-+			    struct device_attribute *attr,
-+			    const char *buf, size_t len)
-+{
-+	unsigned char serial_number[IEI_WT61P803_PUZZLE_SN_LENGTH];
-+	unsigned char mac_address[IEI_WT61P803_PUZZLE_MAC_LENGTH];
-+	struct iei_wt61p803_puzzle *mcu = dev_get_drvdata(dev);
-+	struct iei_wt61p803_puzzle_device_attribute *pattr = to_puzzle_dev_attr(attr);
-+	int power_loss_recovery_action = 0;
-+	int ret;
-+
-+	switch (pattr->type) {
-+	case IEI_WT61P803_PUZZLE_SERIAL_NUMBER:
-+		if (len != (size_t)(IEI_WT61P803_PUZZLE_SN_LENGTH + 1))
-+			return -EINVAL;
-+		memcpy(serial_number, buf, sizeof(serial_number));
-+		ret = iei_wt61p803_puzzle_write_serial_number(mcu, serial_number);
-+		if (ret)
-+			return ret;
-+		return len;
-+	case IEI_WT61P803_PUZZLE_MAC_ADDRESS:
-+		if (len != (size_t)(IEI_WT61P803_PUZZLE_MAC_LENGTH + 1))
-+			return -EINVAL;
-+
-+		memcpy(mac_address, buf, sizeof(mac_address));
-+
-+		if (strlen(attr->attr.name) != 13)
-+			return -EIO;
-+
-+		ret = iei_wt61p803_puzzle_write_mac_address(mcu, mac_address, pattr->index);
-+		if (ret)
-+			return ret;
-+		return len;
-+	case IEI_WT61P803_PUZZLE_POWER_LOSS_RECOVERY:
-+		ret = kstrtoint(buf, 10, &power_loss_recovery_action);
-+		if (ret)
-+			return ret;
-+		ret = iei_wt61p803_puzzle_write_power_loss_recovery(mcu,
-+								    power_loss_recovery_action);
-+		if (ret)
-+			return ret;
-+		return len;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+
-+#define IEI_WT61P803_PUZZLE_ATTR(_name, _mode, _show, _store, _type, _index) \
-+	struct iei_wt61p803_puzzle_device_attribute dev_attr_##_name = \
-+		{ .dev_attr	= __ATTR(_name, _mode, _show, _store), \
-+		  .type		= _type, \
-+		  .index	= _index }
-+
-+#define IEI_WT61P803_PUZZLE_ATTR_RO(_name, _type, _id) \
-+	IEI_WT61P803_PUZZLE_ATTR(_name, 0444, show_output, NULL, _type, _id)
-+
-+#define IEI_WT61P803_PUZZLE_ATTR_RW(_name, _type, _id) \
-+	IEI_WT61P803_PUZZLE_ATTR(_name, 0644, show_output, store_output, _type, _id)
-+
-+static IEI_WT61P803_PUZZLE_ATTR_RO(version, IEI_WT61P803_PUZZLE_VERSION, 0);
-+static IEI_WT61P803_PUZZLE_ATTR_RO(build_info, IEI_WT61P803_PUZZLE_BUILD_INFO, 0);
-+static IEI_WT61P803_PUZZLE_ATTR_RO(bootloader_mode, IEI_WT61P803_PUZZLE_BOOTLOADER_MODE, 0);
-+static IEI_WT61P803_PUZZLE_ATTR_RO(protocol_version, IEI_WT61P803_PUZZLE_PROTOCOL_VERSION, 0);
-+static IEI_WT61P803_PUZZLE_ATTR_RW(serial_number, IEI_WT61P803_PUZZLE_SERIAL_NUMBER, 0);
-+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_0, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 0);
-+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_1, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 1);
-+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_2, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 2);
-+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_3, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 3);
-+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_4, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 4);
-+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_5, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 5);
-+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_6, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 6);
-+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_7, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 7);
-+static IEI_WT61P803_PUZZLE_ATTR_RO(ac_recovery_status, IEI_WT61P803_PUZZLE_AC_RECOVERY_STATUS, 0);
-+static IEI_WT61P803_PUZZLE_ATTR_RW(power_loss_recovery, IEI_WT61P803_PUZZLE_POWER_LOSS_RECOVERY, 0);
-+static IEI_WT61P803_PUZZLE_ATTR_RO(power_status, IEI_WT61P803_PUZZLE_POWER_STATUS, 0);
-+
-+static struct attribute *iei_wt61p803_puzzle_attrs[] = {
-+	&dev_attr_version.dev_attr.attr,
-+	&dev_attr_build_info.dev_attr.attr,
-+	&dev_attr_bootloader_mode.dev_attr.attr,
-+	&dev_attr_protocol_version.dev_attr.attr,
-+	&dev_attr_serial_number.dev_attr.attr,
-+	&dev_attr_mac_address_0.dev_attr.attr,
-+	&dev_attr_mac_address_1.dev_attr.attr,
-+	&dev_attr_mac_address_2.dev_attr.attr,
-+	&dev_attr_mac_address_3.dev_attr.attr,
-+	&dev_attr_mac_address_4.dev_attr.attr,
-+	&dev_attr_mac_address_5.dev_attr.attr,
-+	&dev_attr_mac_address_6.dev_attr.attr,
-+	&dev_attr_mac_address_7.dev_attr.attr,
-+	&dev_attr_ac_recovery_status.dev_attr.attr,
-+	&dev_attr_power_loss_recovery.dev_attr.attr,
-+	&dev_attr_power_status.dev_attr.attr,
-+	NULL
-+};
-+ATTRIBUTE_GROUPS(iei_wt61p803_puzzle);
-+
-+static int iei_wt61p803_puzzle_sysfs_create(struct device *dev,
-+					    struct iei_wt61p803_puzzle *mcu)
-+{
-+	int ret;
-+
-+	ret = sysfs_create_groups(&mcu->dev->kobj, iei_wt61p803_puzzle_groups);
-+	if (ret)
-+		mfd_remove_devices(mcu->dev);
-+
-+	return ret;
-+}
-+
-+static int iei_wt61p803_puzzle_sysfs_remove(struct device *dev,
-+					    struct iei_wt61p803_puzzle *mcu)
-+{
-+	/* Remove sysfs groups */
-+	sysfs_remove_groups(&mcu->dev->kobj, iei_wt61p803_puzzle_groups);
-+	mfd_remove_devices(mcu->dev);
-+
-+	return 0;
-+}
-+
-+static int iei_wt61p803_puzzle_probe(struct serdev_device *serdev)
-+{
-+	struct device *dev = &serdev->dev;
-+	struct iei_wt61p803_puzzle *mcu;
-+	u32 baud;
-+	int ret;
-+
-+	/* Read the baud rate from 'current-speed', because the MCU supports different rates */
-+	if (device_property_read_u32(dev, "current-speed", &baud)) {
-+		dev_err(dev,
-+			"'current-speed' is not specified in device node\n");
-+		return -EINVAL;
-+	}
-+	dev_dbg(dev, "Driver baud rate: %d\n", baud);
-+
-+	/* Allocate the memory */
-+	mcu = devm_kzalloc(dev, sizeof(*mcu), GFP_KERNEL);
-+	if (!mcu)
-+		return -ENOMEM;
-+
-+	mcu->reply = devm_kzalloc(dev, sizeof(*mcu->reply), GFP_KERNEL);
-+	if (!mcu->reply)
-+		return -ENOMEM;
-+
-+	/* Initialize device struct data */
-+	mcu->serdev = serdev;
-+	mcu->dev = dev;
-+	init_completion(&mcu->reply->received);
-+	mutex_init(&mcu->reply_lock);
-+	mutex_init(&mcu->lock);
-+
-+	/* Setup UART interface */
-+	serdev_device_set_drvdata(serdev, mcu);
-+	serdev_device_set_client_ops(serdev, &iei_wt61p803_puzzle_serdev_device_ops);
-+	ret = devm_serdev_device_open(dev, serdev);
-+	if (ret)
-+		return ret;
-+	serdev_device_set_baudrate(serdev, baud);
-+	serdev_device_set_flow_control(serdev, false);
-+	ret = serdev_device_set_parity(serdev, SERDEV_PARITY_NONE);
-+	if (ret) {
-+		dev_err(dev, "Failed to set parity\n");
-+		return ret;
-+	}
-+
-+	ret = iei_wt61p803_puzzle_get_version(mcu);
-+	if (ret)
-+		return ret;
-+
-+	dev_dbg(dev, "MCU version: %s\n", mcu->version.version);
-+	dev_dbg(dev, "MCU firmware build info: %s\n", mcu->version.build_info);
-+	dev_dbg(dev, "MCU in bootloader mode: %s\n",
-+		mcu->version.bootloader_mode ? "true" : "false");
-+	dev_dbg(dev, "MCU protocol version: %s\n", mcu->version.protocol_version);
-+
-+	if (device_property_read_bool(dev, "enable-beep")) {
-+		ret = iei_wt61p803_puzzle_buzzer(mcu, false);
-+		if (ret)
-+			return ret;
-+	}
-+
-+	ret = iei_wt61p803_puzzle_sysfs_create(dev, mcu);
-+	if (ret)
-+		return ret;
-+
-+	return devm_of_platform_populate(dev);
-+}
-+
-+static void iei_wt61p803_puzzle_remove(struct serdev_device *serdev)
-+{
-+	struct device *dev = &serdev->dev;
-+	struct iei_wt61p803_puzzle *mcu = dev_get_drvdata(dev);
-+
-+	iei_wt61p803_puzzle_sysfs_remove(dev, mcu);
-+}
-+
-+static const struct of_device_id iei_wt61p803_puzzle_dt_ids[] = {
-+	{ .compatible = "iei,wt61p803-puzzle" },
-+	{ }
-+};
-+
-+MODULE_DEVICE_TABLE(of, iei_wt61p803_puzzle_dt_ids);
-+
-+static struct serdev_device_driver iei_wt61p803_puzzle_drv = {
-+	.probe			= iei_wt61p803_puzzle_probe,
-+	.remove			= iei_wt61p803_puzzle_remove,
-+	.driver = {
-+		.name		= "iei-wt61p803-puzzle",
-+		.of_match_table	= iei_wt61p803_puzzle_dt_ids,
-+	},
-+};
-+
-+module_serdev_device_driver(iei_wt61p803_puzzle_drv);
-+
-+MODULE_LICENSE("GPL v2");
-+MODULE_AUTHOR("Luka Kovacic <luka.kovacic@sartura.hr>");
-+MODULE_DESCRIPTION("IEI WT61P803 PUZZLE MCU Driver");
---- /dev/null
-+++ b/include/linux/mfd/iei-wt61p803-puzzle.h
-@@ -0,0 +1,66 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+/* IEI WT61P803 PUZZLE MCU Driver
-+ * System management microcontroller for fan control, temperature sensor reading,
-+ * LED control and system identification on IEI Puzzle series ARM-based appliances.
-+ *
-+ * Copyright (C) 2020 Sartura Ltd.
-+ * Author: Luka Kovacic <luka.kovacic@sartura.hr>
-+ */
-+
-+#ifndef _MFD_IEI_WT61P803_PUZZLE_H_
-+#define _MFD_IEI_WT61P803_PUZZLE_H_
-+
-+#define IEI_WT61P803_PUZZLE_BUF_SIZE 512
-+
-+/* Command magic numbers */
-+#define IEI_WT61P803_PUZZLE_CMD_HEADER_START		0x40 /* @ */
-+#define IEI_WT61P803_PUZZLE_CMD_HEADER_START_OTHER	0x25 /* % */
-+#define IEI_WT61P803_PUZZLE_CMD_HEADER_EEPROM		0xF7
-+
-+#define IEI_WT61P803_PUZZLE_CMD_RESPONSE_OK		0x30 /* 0 */
-+#define IEI_WT61P803_PUZZLE_CHECKSUM_RESPONSE_OK	0x70
-+
-+#define IEI_WT61P803_PUZZLE_CMD_EEPROM_READ		0xA1
-+#define IEI_WT61P803_PUZZLE_CMD_EEPROM_WRITE		0xA0
-+
-+#define IEI_WT61P803_PUZZLE_CMD_OTHER_VERSION		0x56 /* V */
-+#define IEI_WT61P803_PUZZLE_CMD_OTHER_BUILD		0x42 /* B */
-+#define IEI_WT61P803_PUZZLE_CMD_OTHER_BOOTLOADER_MODE	0x4D /* M */
-+#define IEI_WT61P803_PUZZLE_CMD_OTHER_MODE_BOOTLOADER	0x30
-+#define IEI_WT61P803_PUZZLE_CMD_OTHER_MODE_APPS		0x31
-+#define IEI_WT61P803_PUZZLE_CMD_OTHER_PROTOCOL_VERSION	0x50 /* P */
-+
-+#define IEI_WT61P803_PUZZLE_CMD_FUNCTION_SINGLE		0x43 /* C */
-+#define IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER		0x4F /* O */
-+#define IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_STATUS	0x53 /* S */
-+#define IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_POWER_LOSS 0x41 /* A */
-+
-+#define IEI_WT61P803_PUZZLE_CMD_LED			0x52 /* R */
-+#define IEI_WT61P803_PUZZLE_CMD_LED_POWER		0x31 /* 1 */
-+
-+#define IEI_WT61P803_PUZZLE_CMD_TEMP			0x54 /* T */
-+#define IEI_WT61P803_PUZZLE_CMD_TEMP_ALL		0x41 /* A */
-+
-+#define IEI_WT61P803_PUZZLE_CMD_FAN			0x46 /* F */
-+#define IEI_WT61P803_PUZZLE_CMD_FAN_PWM_READ		0x5A /* Z */
-+#define IEI_WT61P803_PUZZLE_CMD_FAN_PWM_WRITE		0x57 /* W */
-+#define IEI_WT61P803_PUZZLE_CMD_FAN_PWM_BASE		0x30
-+#define IEI_WT61P803_PUZZLE_CMD_FAN_RPM_BASE		0x41 /* A */
-+
-+#define IEI_WT61P803_PUZZLE_CMD_FAN_PWM(x) (IEI_WT61P803_PUZZLE_CMD_FAN_PWM_BASE + (x)) /* 0 - 1 */
-+#define IEI_WT61P803_PUZZLE_CMD_FAN_RPM(x) (IEI_WT61P803_PUZZLE_CMD_FAN_RPM_BASE + (x)) /* 0 - 5 */
-+
-+struct iei_wt61p803_puzzle_mcu_version;
-+struct iei_wt61p803_puzzle_reply;
-+struct iei_wt61p803_puzzle;
-+
-+int iei_wt61p803_puzzle_write_command_watchdog(struct iei_wt61p803_puzzle *mcu,
-+					       unsigned char *cmd, size_t size,
-+					       unsigned char *reply_data, size_t *reply_size,
-+					       int retry_count);
-+
-+int iei_wt61p803_puzzle_write_command(struct iei_wt61p803_puzzle *mcu,
-+				      unsigned char *cmd, size_t size,
-+				      unsigned char *reply_data, size_t *reply_size);
-+
-+#endif /* _MFD_IEI_WT61P803_PUZZLE_H_ */
diff --git a/target/linux/mvebu/patches-5.15/903-drivers-hwmon-Add-the-IEI-WT61P803-PUZZLE-HWMON-driv.patch b/target/linux/mvebu/patches-5.15/903-drivers-hwmon-Add-the-IEI-WT61P803-PUZZLE-HWMON-driv.patch
deleted file mode 100644
index 023495373b86ed..00000000000000
--- a/target/linux/mvebu/patches-5.15/903-drivers-hwmon-Add-the-IEI-WT61P803-PUZZLE-HWMON-driv.patch
+++ /dev/null
@@ -1,501 +0,0 @@
-From e3310a638cd310bfd93dbbc6d2732ab6aea18dd2 Mon Sep 17 00:00:00 2001
-From: Luka Kovacic <luka.kovacic () sartura ! hr>
-Date: Tue, 24 Aug 2021 12:44:34 +0000
-Subject: [PATCH 3/7] drivers: hwmon: Add the IEI WT61P803 PUZZLE HWMON driver
-
-Add the IEI WT61P803 PUZZLE HWMON driver, that handles the fan speed
-control via PWM, reading fan speed and reading on-board temperature
-sensors.
-
-The driver registers a HWMON device and a simple thermal cooling device to
-enable in-kernel fan management.
-
-This driver depends on the IEI WT61P803 PUZZLE MFD driver.
-
-Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
-Signed-off-by: Pavo Banicevic <pavo.banicevic@sartura.hr>
-Acked-by: Guenter Roeck <linux@roeck-us.net>
-Cc: Luka Perkov <luka.perkov@sartura.hr>
-Cc: Robert Marko <robert.marko@sartura.hr>
----
- drivers/hwmon/Kconfig                     |   8 +
- drivers/hwmon/Makefile                    |   1 +
- drivers/hwmon/iei-wt61p803-puzzle-hwmon.c | 413 ++++++++++++++++++++++
- 3 files changed, 422 insertions(+)
- create mode 100644 drivers/hwmon/iei-wt61p803-puzzle-hwmon.c
-
---- a/drivers/hwmon/Kconfig
-+++ b/drivers/hwmon/Kconfig
-@@ -732,6 +732,14 @@ config SENSORS_IBMPOWERNV
- 	  This driver can also be built as a module. If so, the module
- 	  will be called ibmpowernv.
- 
-+config SENSORS_IEI_WT61P803_PUZZLE_HWMON
-+	tristate "IEI WT61P803 PUZZLE MFD HWMON Driver"
-+	depends on MFD_IEI_WT61P803_PUZZLE
-+	help
-+	  The IEI WT61P803 PUZZLE MFD HWMON Driver handles reading fan speed
-+	  and writing fan PWM values. It also supports reading on-board
-+	  temperature sensors.
-+
- config SENSORS_IIO_HWMON
- 	tristate "Hwmon driver that uses channels specified via iio maps"
- 	depends on IIO
---- a/drivers/hwmon/Makefile
-+++ b/drivers/hwmon/Makefile
-@@ -84,6 +84,7 @@ obj-$(CONFIG_SENSORS_HIH6130)	+= hih6130
- obj-$(CONFIG_SENSORS_ULTRA45)	+= ultra45_env.o
- obj-$(CONFIG_SENSORS_I5500)	+= i5500_temp.o
- obj-$(CONFIG_SENSORS_I5K_AMB)	+= i5k_amb.o
-+obj-$(CONFIG_SENSORS_IEI_WT61P803_PUZZLE_HWMON) += iei-wt61p803-puzzle-hwmon.o
- obj-$(CONFIG_SENSORS_IBMAEM)	+= ibmaem.o
- obj-$(CONFIG_SENSORS_IBMPEX)	+= ibmpex.o
- obj-$(CONFIG_SENSORS_IBMPOWERNV)+= ibmpowernv.o
---- /dev/null
-+++ b/drivers/hwmon/iei-wt61p803-puzzle-hwmon.c
-@@ -0,0 +1,445 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+/* IEI WT61P803 PUZZLE MCU HWMON Driver
-+ *
-+ * Copyright (C) 2020 Sartura Ltd.
-+ * Author: Luka Kovacic <luka.kovacic@sartura.hr>
-+ */
-+
-+#include <linux/err.h>
-+#include <linux/hwmon.h>
-+#include <linux/interrupt.h>
-+#include <linux/irq.h>
-+#include <linux/math64.h>
-+#include <linux/mfd/iei-wt61p803-puzzle.h>
-+#include <linux/mod_devicetable.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/property.h>
-+#include <linux/slab.h>
-+#include <linux/thermal.h>
-+
-+#define IEI_WT61P803_PUZZLE_HWMON_MAX_PWM	2
-+#define IEI_WT61P803_PUZZLE_HWMON_MAX_PWM_VAL	255
-+
-+/**
-+ * struct iei_wt61p803_puzzle_thermal_cooling_device - Thermal cooling device instance
-+ * @mcu_hwmon:		Parent driver struct pointer
-+ * @tcdev:		Thermal cooling device pointer
-+ * @name:		Thermal cooling device name
-+ * @pwm_channel:	Controlled PWM channel (0 or 1)
-+ * @cooling_levels:	Thermal cooling device cooling levels (DT)
-+ * @cur_level:		Current cooling level
-+ * @num_levels:	Number of cooling levels
-+ */
-+struct iei_wt61p803_puzzle_thermal_cooling_device {
-+	struct iei_wt61p803_puzzle_hwmon *mcu_hwmon;
-+	struct thermal_cooling_device *tcdev;
-+	char name[THERMAL_NAME_LENGTH];
-+	int pwm_channel;
-+	u32 *cooling_levels;
-+	int cur_level;
-+	u8 num_levels;
-+};
-+
-+/**
-+ * struct iei_wt61p803_puzzle_hwmon - MCU HWMON Driver
-+ * @mcu:				MCU struct pointer
-+ * @response_buffer			Global MCU response buffer
-+ * @thermal_cooling_dev_present:	Per-channel thermal cooling device control indicator
-+ * @cdev:				Per-channel thermal cooling device private structure
-+ */
-+struct iei_wt61p803_puzzle_hwmon {
-+	struct iei_wt61p803_puzzle *mcu;
-+	unsigned char response_buffer[IEI_WT61P803_PUZZLE_BUF_SIZE];
-+	bool thermal_cooling_dev_present[IEI_WT61P803_PUZZLE_HWMON_MAX_PWM];
-+	struct iei_wt61p803_puzzle_thermal_cooling_device
-+		*cdev[IEI_WT61P803_PUZZLE_HWMON_MAX_PWM];
-+	struct mutex lock; /* mutex to protect response_buffer array */
-+};
-+
-+#define raw_temp_to_milidegree_celsius(x) (((x) - 0x80) * 1000)
-+static int iei_wt61p803_puzzle_read_temp_sensor(struct iei_wt61p803_puzzle_hwmon *mcu_hwmon,
-+						int channel, long *value)
-+{
-+	unsigned char *resp_buf = mcu_hwmon->response_buffer;
-+	unsigned char temp_sensor_ntc_cmd[4] = {
-+		IEI_WT61P803_PUZZLE_CMD_HEADER_START,
-+		IEI_WT61P803_PUZZLE_CMD_TEMP,
-+		IEI_WT61P803_PUZZLE_CMD_TEMP_ALL,
-+	};
-+	size_t reply_size;
-+	int ret;
-+
-+	mutex_lock(&mcu_hwmon->lock);
-+	ret = iei_wt61p803_puzzle_write_command(mcu_hwmon->mcu, temp_sensor_ntc_cmd,
-+						sizeof(temp_sensor_ntc_cmd), resp_buf,
-+						&reply_size);
-+	if (ret)
-+		goto exit;
-+
-+	if (reply_size != 7) {
-+		ret = -EIO;
-+		goto exit;
-+	}
-+
-+	/* Check the number of NTC values */
-+	if (resp_buf[3] != '2') {
-+		ret = -EIO;
-+		goto exit;
-+	}
-+
-+	*value = raw_temp_to_milidegree_celsius(resp_buf[4 + channel]);
-+exit:
-+	mutex_unlock(&mcu_hwmon->lock);
-+	return ret;
-+}
-+
-+#define raw_fan_val_to_rpm(x, y) ((((x) << 8 | (y)) / 2) * 60)
-+static int iei_wt61p803_puzzle_read_fan_speed(struct iei_wt61p803_puzzle_hwmon *mcu_hwmon,
-+					      int channel, long *value)
-+{
-+	unsigned char *resp_buf = mcu_hwmon->response_buffer;
-+	unsigned char fan_speed_cmd[4] = {};
-+	size_t reply_size;
-+	int ret;
-+
-+	fan_speed_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START;
-+	fan_speed_cmd[1] = IEI_WT61P803_PUZZLE_CMD_FAN;
-+	fan_speed_cmd[2] = IEI_WT61P803_PUZZLE_CMD_FAN_RPM(channel);
-+
-+	mutex_lock(&mcu_hwmon->lock);
-+	ret = iei_wt61p803_puzzle_write_command(mcu_hwmon->mcu, fan_speed_cmd,
-+						sizeof(fan_speed_cmd), resp_buf,
-+						&reply_size);
-+	if (ret)
-+		goto exit;
-+
-+	if (reply_size != 7) {
-+		ret = -EIO;
-+		goto exit;
-+	}
-+
-+	*value = raw_fan_val_to_rpm(resp_buf[3], resp_buf[4]);
-+exit:
-+	mutex_unlock(&mcu_hwmon->lock);
-+	return ret;
-+}
-+
-+static int iei_wt61p803_puzzle_write_pwm_channel(struct iei_wt61p803_puzzle_hwmon *mcu_hwmon,
-+						 int channel, long pwm_set_val)
-+{
-+	unsigned char *resp_buf = mcu_hwmon->response_buffer;
-+	unsigned char pwm_set_cmd[6] = {};
-+	size_t reply_size;
-+	int ret;
-+
-+	pwm_set_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START;
-+	pwm_set_cmd[1] = IEI_WT61P803_PUZZLE_CMD_FAN;
-+	pwm_set_cmd[2] = IEI_WT61P803_PUZZLE_CMD_FAN_PWM_WRITE;
-+	pwm_set_cmd[3] = IEI_WT61P803_PUZZLE_CMD_FAN_PWM(channel);
-+	pwm_set_cmd[4] = pwm_set_val;
-+
-+	mutex_lock(&mcu_hwmon->lock);
-+	ret = iei_wt61p803_puzzle_write_command(mcu_hwmon->mcu, pwm_set_cmd,
-+						sizeof(pwm_set_cmd), resp_buf,
-+						&reply_size);
-+	if (ret)
-+		goto exit;
-+
-+	if (reply_size != 3) {
-+		ret = -EIO;
-+		goto exit;
-+	}
-+
-+	if (!(resp_buf[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START &&
-+	      resp_buf[1] == IEI_WT61P803_PUZZLE_CMD_RESPONSE_OK &&
-+	      resp_buf[2] == IEI_WT61P803_PUZZLE_CHECKSUM_RESPONSE_OK)) {
-+		ret = -EIO;
-+		goto exit;
-+	}
-+exit:
-+	mutex_unlock(&mcu_hwmon->lock);
-+	return ret;
-+}
-+
-+static int iei_wt61p803_puzzle_read_pwm_channel(struct iei_wt61p803_puzzle_hwmon *mcu_hwmon,
-+						int channel, long *value)
-+{
-+	unsigned char *resp_buf = mcu_hwmon->response_buffer;
-+	unsigned char pwm_get_cmd[5] = {};
-+	size_t reply_size;
-+	int ret;
-+
-+	pwm_get_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START;
-+	pwm_get_cmd[1] = IEI_WT61P803_PUZZLE_CMD_FAN;
-+	pwm_get_cmd[2] = IEI_WT61P803_PUZZLE_CMD_FAN_PWM_READ;
-+	pwm_get_cmd[3] = IEI_WT61P803_PUZZLE_CMD_FAN_PWM(channel);
-+
-+	ret = iei_wt61p803_puzzle_write_command(mcu_hwmon->mcu, pwm_get_cmd,
-+						sizeof(pwm_get_cmd), resp_buf,
-+						&reply_size);
-+	if (ret)
-+		return ret;
-+
-+	if (reply_size != 5)
-+		return -EIO;
-+
-+	if (resp_buf[2] != IEI_WT61P803_PUZZLE_CMD_FAN_PWM_READ)
-+		return -EIO;
-+
-+	*value = resp_buf[3];
-+
-+	return 0;
-+}
-+
-+static int iei_wt61p803_puzzle_read(struct device *dev, enum hwmon_sensor_types type,
-+				    u32 attr, int channel, long *val)
-+{
-+	struct iei_wt61p803_puzzle_hwmon *mcu_hwmon = dev_get_drvdata(dev->parent);
-+
-+	switch (type) {
-+	case hwmon_pwm:
-+		return iei_wt61p803_puzzle_read_pwm_channel(mcu_hwmon, channel, val);
-+	case hwmon_fan:
-+		return iei_wt61p803_puzzle_read_fan_speed(mcu_hwmon, channel, val);
-+	case hwmon_temp:
-+		return iei_wt61p803_puzzle_read_temp_sensor(mcu_hwmon, channel, val);
-+	default:
-+		return -EINVAL;
-+	}
-+}
-+
-+static int iei_wt61p803_puzzle_write(struct device *dev, enum hwmon_sensor_types type,
-+				     u32 attr, int channel, long val)
-+{
-+	struct iei_wt61p803_puzzle_hwmon *mcu_hwmon = dev_get_drvdata(dev->parent);
-+
-+	return iei_wt61p803_puzzle_write_pwm_channel(mcu_hwmon, channel, val);
-+}
-+
-+static umode_t iei_wt61p803_puzzle_is_visible(const void *data, enum hwmon_sensor_types type,
-+					      u32 attr, int channel)
-+{
-+	const struct iei_wt61p803_puzzle_hwmon *mcu_hwmon = data;
-+
-+	switch (type) {
-+	case hwmon_pwm:
-+		if (mcu_hwmon->thermal_cooling_dev_present[channel])
-+			return 0444;
-+		if (attr == hwmon_pwm_input)
-+			return 0644;
-+		break;
-+	case hwmon_fan:
-+		if (attr == hwmon_fan_input)
-+			return 0444;
-+		break;
-+	case hwmon_temp:
-+		if (attr == hwmon_temp_input)
-+			return 0444;
-+		break;
-+	default:
-+		return 0;
-+	}
-+
-+	return 0;
-+}
-+
-+static const struct hwmon_ops iei_wt61p803_puzzle_hwmon_ops = {
-+	.is_visible = iei_wt61p803_puzzle_is_visible,
-+	.read = iei_wt61p803_puzzle_read,
-+	.write = iei_wt61p803_puzzle_write,
-+};
-+
-+static const struct hwmon_channel_info *iei_wt61p803_puzzle_info[] = {
-+	HWMON_CHANNEL_INFO(pwm,
-+			   HWMON_PWM_INPUT,
-+			   HWMON_PWM_INPUT),
-+	HWMON_CHANNEL_INFO(fan,
-+			   HWMON_F_INPUT,
-+			   HWMON_F_INPUT,
-+			   HWMON_F_INPUT,
-+			   HWMON_F_INPUT,
-+			   HWMON_F_INPUT),
-+	HWMON_CHANNEL_INFO(temp,
-+			   HWMON_T_INPUT,
-+			   HWMON_T_INPUT),
-+	NULL
-+};
-+
-+static const struct hwmon_chip_info iei_wt61p803_puzzle_chip_info = {
-+	.ops = &iei_wt61p803_puzzle_hwmon_ops,
-+	.info = iei_wt61p803_puzzle_info,
-+};
-+
-+static int iei_wt61p803_puzzle_get_max_state(struct thermal_cooling_device *tcdev,
-+					     unsigned long *state)
-+{
-+	struct iei_wt61p803_puzzle_thermal_cooling_device *cdev = tcdev->devdata;
-+
-+	if (!cdev)
-+		return -EINVAL;
-+
-+	*state = cdev->num_levels - 1;
-+	return 0;
-+}
-+
-+static int iei_wt61p803_puzzle_get_cur_state(struct thermal_cooling_device *tcdev,
-+					     unsigned long *state)
-+{
-+	struct iei_wt61p803_puzzle_thermal_cooling_device *cdev = tcdev->devdata;
-+
-+	if (!cdev)
-+		return -EINVAL;
-+
-+	if (cdev->cur_level < 0)
-+		return -EAGAIN;
-+
-+	*state = cdev->cur_level;
-+	return 0;
-+}
-+
-+static int iei_wt61p803_puzzle_set_cur_state(struct thermal_cooling_device *tcdev,
-+					     unsigned long state)
-+{
-+	struct iei_wt61p803_puzzle_thermal_cooling_device *cdev = tcdev->devdata;
-+	u8 pwm_level;
-+
-+	if (!cdev)
-+		return -EINVAL;
-+
-+	if (state >= cdev->num_levels)
-+		return -EINVAL;
-+
-+	if (state == cdev->cur_level)
-+		return 0;
-+
-+	cdev->cur_level = state;
-+	pwm_level = cdev->cooling_levels[state];
-+
-+	return iei_wt61p803_puzzle_write_pwm_channel(cdev->mcu_hwmon, cdev->pwm_channel, pwm_level);
-+}
-+
-+static const struct thermal_cooling_device_ops iei_wt61p803_puzzle_cooling_ops = {
-+	.get_max_state = iei_wt61p803_puzzle_get_max_state,
-+	.get_cur_state = iei_wt61p803_puzzle_get_cur_state,
-+	.set_cur_state = iei_wt61p803_puzzle_set_cur_state,
-+};
-+
-+static int
-+iei_wt61p803_puzzle_enable_thermal_cooling_dev(struct device *dev,
-+					       struct fwnode_handle *child,
-+					       struct iei_wt61p803_puzzle_hwmon *mcu_hwmon)
-+{
-+	struct iei_wt61p803_puzzle_thermal_cooling_device *cdev;
-+	u32 pwm_channel;
-+	u8 num_levels;
-+	int i, ret;
-+
-+	ret = fwnode_property_read_u32(child, "reg", &pwm_channel);
-+	if (ret)
-+		return ret;
-+
-+	mcu_hwmon->thermal_cooling_dev_present[pwm_channel] = true;
-+
-+	num_levels = fwnode_property_count_u32(child, "cooling-levels");
-+	if (!num_levels)
-+		return -EINVAL;
-+
-+	cdev = devm_kzalloc(dev, sizeof(*cdev), GFP_KERNEL);
-+	if (!cdev)
-+		return -ENOMEM;
-+
-+	cdev->cooling_levels = devm_kmalloc_array(dev, num_levels, sizeof(u32), GFP_KERNEL);
-+	if (!cdev->cooling_levels)
-+		return -ENOMEM;
-+
-+	ret = fwnode_property_read_u32_array(child, "cooling-levels",
-+					     cdev->cooling_levels,
-+					     num_levels);
-+	if (ret) {
-+		dev_err(dev, "Couldn't read property 'cooling-levels'\n");
-+		return ret;
-+	}
-+
-+	for (i = 0; i < num_levels; i++) {
-+		if (cdev->cooling_levels[i] >
-+		    IEI_WT61P803_PUZZLE_HWMON_MAX_PWM_VAL) {
-+			dev_err(dev, "iei_wt61p803_fan state[%d]:%d > %d\n", i,
-+				cdev->cooling_levels[i],
-+				IEI_WT61P803_PUZZLE_HWMON_MAX_PWM_VAL);
-+			return -EINVAL;
-+		}
-+	}
-+
-+	cdev->mcu_hwmon = mcu_hwmon;
-+	cdev->pwm_channel = pwm_channel;
-+	cdev->num_levels = num_levels;
-+	cdev->cur_level = -1;
-+	mcu_hwmon->cdev[pwm_channel] = cdev;
-+
-+	snprintf(cdev->name, THERMAL_NAME_LENGTH, "wt61p803_puzzle_%d", pwm_channel);
-+	cdev->tcdev = devm_thermal_of_cooling_device_register(dev, to_of_node(child), cdev->name,
-+							      cdev, &iei_wt61p803_puzzle_cooling_ops);
-+	if (IS_ERR(cdev->tcdev))
-+		return PTR_ERR(cdev->tcdev);
-+
-+	return 0;
-+}
-+
-+static int iei_wt61p803_puzzle_hwmon_probe(struct platform_device *pdev)
-+{
-+	struct device *dev = &pdev->dev;
-+	struct iei_wt61p803_puzzle *mcu = dev_get_drvdata(dev->parent);
-+	struct iei_wt61p803_puzzle_hwmon *mcu_hwmon;
-+	struct fwnode_handle *child;
-+	struct device *hwmon_dev;
-+	int ret;
-+
-+	mcu_hwmon = devm_kzalloc(dev, sizeof(*mcu_hwmon), GFP_KERNEL);
-+	if (!mcu_hwmon)
-+		return -ENOMEM;
-+
-+	mcu_hwmon->mcu = mcu;
-+	platform_set_drvdata(pdev, mcu_hwmon);
-+	mutex_init(&mcu_hwmon->lock);
-+
-+	hwmon_dev = devm_hwmon_device_register_with_info(dev, "iei_wt61p803_puzzle",
-+							 mcu_hwmon,
-+							 &iei_wt61p803_puzzle_chip_info,
-+							 NULL);
-+	if (IS_ERR(hwmon_dev))
-+		return PTR_ERR(hwmon_dev);
-+
-+	/* Control fans via PWM lines via Linux Kernel */
-+	if (IS_ENABLED(CONFIG_THERMAL)) {
-+		device_for_each_child_node(dev, child) {
-+			ret = iei_wt61p803_puzzle_enable_thermal_cooling_dev(dev, child, mcu_hwmon);
-+			if (ret) {
-+				dev_err(dev, "Enabling the PWM fan failed\n");
-+				fwnode_handle_put(child);
-+				return ret;
-+			}
-+		}
-+	}
-+	return 0;
-+}
-+
-+static const struct of_device_id iei_wt61p803_puzzle_hwmon_id_table[] = {
-+	{ .compatible = "iei,wt61p803-puzzle-hwmon" },
-+	{}
-+};
-+MODULE_DEVICE_TABLE(of, iei_wt61p803_puzzle_hwmon_id_table);
-+
-+static struct platform_driver iei_wt61p803_puzzle_hwmon_driver = {
-+	.driver = {
-+		.name = "iei-wt61p803-puzzle-hwmon",
-+		.of_match_table = iei_wt61p803_puzzle_hwmon_id_table,
-+	},
-+	.probe = iei_wt61p803_puzzle_hwmon_probe,
-+};
-+
-+module_platform_driver(iei_wt61p803_puzzle_hwmon_driver);
-+
-+MODULE_DESCRIPTION("IEI WT61P803 PUZZLE MCU HWMON Driver");
-+MODULE_AUTHOR("Luka Kovacic <luka.kovacic@sartura.hr>");
-+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/mvebu/patches-5.15/904-drivers-leds-Add-the-IEI-WT61P803-PUZZLE-LED-driver.patch b/target/linux/mvebu/patches-5.15/904-drivers-leds-Add-the-IEI-WT61P803-PUZZLE-LED-driver.patch
deleted file mode 100644
index a3fc731c471967..00000000000000
--- a/target/linux/mvebu/patches-5.15/904-drivers-leds-Add-the-IEI-WT61P803-PUZZLE-LED-driver.patch
+++ /dev/null
@@ -1,207 +0,0 @@
-From f3b44eb69cc561cf05d00506dcec0dd9be003ed8 Mon Sep 17 00:00:00 2001
-From: Luka Kovacic <luka.kovacic () sartura ! hr>
-Date: Tue, 24 Aug 2021 12:44:35 +0000
-Subject: [PATCH 4/7] drivers: leds: Add the IEI WT61P803 PUZZLE LED driver
-
-Add support for the IEI WT61P803 PUZZLE LED driver.
-Currently only the front panel power LED is supported,
-since it is the only LED on this board wired through the
-MCU.
-
-The LED is wired directly to the on-board MCU controller
-and is toggled using an MCU command.
-
-Support for more LEDs is going to be added in case more
-boards implement this microcontroller, as LEDs use many
-different GPIOs.
-
-This driver depends on the IEI WT61P803 PUZZLE MFD driver.
-
-Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
-Signed-off-by: Pavo Banicevic <pavo.banicevic@sartura.hr>
-Cc: Luka Perkov <luka.perkov@sartura.hr>
-Cc: Robert Marko <robert.marko@sartura.hr>
----
- drivers/leds/Kconfig                    |   8 ++
- drivers/leds/Makefile                   |   1 +
- drivers/leds/leds-iei-wt61p803-puzzle.c | 147 ++++++++++++++++++++++++
- 3 files changed, 156 insertions(+)
- create mode 100644 drivers/leds/leds-iei-wt61p803-puzzle.c
-
---- a/drivers/leds/Kconfig
-+++ b/drivers/leds/Kconfig
-@@ -306,6 +306,14 @@ config LEDS_IPAQ_MICRO
- 	  Choose this option if you want to use the notification LED on
- 	  Compaq/HP iPAQ h3100 and h3600.
- 
-+config LEDS_IEI_WT61P803_PUZZLE
-+	tristate "LED Support for the IEI WT61P803 PUZZLE MCU"
-+	depends on LEDS_CLASS
-+	depends on MFD_IEI_WT61P803_PUZZLE
-+	help
-+	  This option enables support for LEDs controlled by the IEI WT61P803
-+	  M801 MCU.
-+
- config LEDS_HP6XX
- 	tristate "LED Support for the HP Jornada 6xx"
- 	depends on LEDS_CLASS
---- a/drivers/leds/Makefile
-+++ b/drivers/leds/Makefile
-@@ -33,6 +33,7 @@ obj-$(CONFIG_LEDS_HP6XX)		+= leds-hp6xx.
- obj-$(CONFIG_LEDS_INTEL_SS4200)		+= leds-ss4200.o
- obj-$(CONFIG_LEDS_IP30)			+= leds-ip30.o
- obj-$(CONFIG_LEDS_IPAQ_MICRO)		+= leds-ipaq-micro.o
-+obj-$(CONFIG_LEDS_IEI_WT61P803_PUZZLE)	+= leds-iei-wt61p803-puzzle.o
- obj-$(CONFIG_LEDS_IS31FL319X)		+= leds-is31fl319x.o
- obj-$(CONFIG_LEDS_IS31FL32XX)		+= leds-is31fl32xx.o
- obj-$(CONFIG_LEDS_LM3530)		+= leds-lm3530.o
---- /dev/null
-+++ b/drivers/leds/leds-iei-wt61p803-puzzle.c
-@@ -0,0 +1,147 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+/* IEI WT61P803 PUZZLE MCU LED Driver
-+ *
-+ * Copyright (C) 2020 Sartura Ltd.
-+ * Author: Luka Kovacic <luka.kovacic@sartura.hr>
-+ */
-+
-+#include <linux/leds.h>
-+#include <linux/mfd/iei-wt61p803-puzzle.h>
-+#include <linux/mod_devicetable.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/property.h>
-+#include <linux/slab.h>
-+
-+enum iei_wt61p803_puzzle_led_state {
-+	IEI_LED_OFF = 0x30,
-+	IEI_LED_ON = 0x31,
-+	IEI_LED_BLINK_5HZ = 0x32,
-+	IEI_LED_BLINK_1HZ = 0x33,
-+};
-+
-+/**
-+ * struct iei_wt61p803_puzzle_led - MCU LED Driver
-+ * @cdev:		LED classdev
-+ * @mcu:		MCU struct pointer
-+ * @response_buffer	Global MCU response buffer
-+ * @lock:		General mutex lock to protect simultaneous R/W access to led_power_state
-+ * @led_power_state:	State of the front panel power LED
-+ */
-+struct iei_wt61p803_puzzle_led {
-+	struct led_classdev cdev;
-+	struct iei_wt61p803_puzzle *mcu;
-+	unsigned char response_buffer[IEI_WT61P803_PUZZLE_BUF_SIZE];
-+	struct mutex lock; /* mutex to protect led_power_state */
-+	int led_power_state;
-+};
-+
-+static inline struct iei_wt61p803_puzzle_led *cdev_to_iei_wt61p803_puzzle_led
-+	(struct led_classdev *led_cdev)
-+{
-+	return container_of(led_cdev, struct iei_wt61p803_puzzle_led, cdev);
-+}
-+
-+static int iei_wt61p803_puzzle_led_brightness_set_blocking(struct led_classdev *cdev,
-+							   enum led_brightness brightness)
-+{
-+	struct iei_wt61p803_puzzle_led *priv = cdev_to_iei_wt61p803_puzzle_led(cdev);
-+	unsigned char *resp_buf = priv->response_buffer;
-+	unsigned char led_power_cmd[5] = {};
-+	size_t reply_size;
-+	int ret;
-+
-+	led_power_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START;
-+	led_power_cmd[1] = IEI_WT61P803_PUZZLE_CMD_LED;
-+	led_power_cmd[2] = IEI_WT61P803_PUZZLE_CMD_LED_POWER;
-+	led_power_cmd[3] = brightness == LED_OFF ? IEI_LED_OFF : IEI_LED_ON;
-+
-+	ret = iei_wt61p803_puzzle_write_command(priv->mcu, led_power_cmd,
-+						sizeof(led_power_cmd),
-+						resp_buf,
-+						&reply_size);
-+	if (ret)
-+		return ret;
-+
-+	if (reply_size != 3)
-+		return -EIO;
-+
-+	if (!(resp_buf[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START &&
-+	      resp_buf[1] == IEI_WT61P803_PUZZLE_CMD_RESPONSE_OK &&
-+	      resp_buf[2] == IEI_WT61P803_PUZZLE_CHECKSUM_RESPONSE_OK))
-+		return -EIO;
-+
-+	mutex_lock(&priv->lock);
-+	priv->led_power_state = brightness;
-+	mutex_unlock(&priv->lock);
-+
-+	return 0;
-+}
-+
-+static enum led_brightness iei_wt61p803_puzzle_led_brightness_get(struct led_classdev *cdev)
-+{
-+	struct iei_wt61p803_puzzle_led *priv = cdev_to_iei_wt61p803_puzzle_led(cdev);
-+	int led_state;
-+
-+	mutex_lock(&priv->lock);
-+	led_state = priv->led_power_state;
-+	mutex_unlock(&priv->lock);
-+
-+	return led_state;
-+}
-+
-+static int iei_wt61p803_puzzle_led_probe(struct platform_device *pdev)
-+{
-+	struct device *dev = &pdev->dev;
-+	struct iei_wt61p803_puzzle *mcu = dev_get_drvdata(dev->parent);
-+	struct iei_wt61p803_puzzle_led *priv;
-+	struct led_init_data init_data = {};
-+	struct fwnode_handle *child;
-+	int ret;
-+
-+	if (device_get_child_node_count(dev) != 1)
-+		return -EINVAL;
-+
-+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
-+	if (!priv)
-+		return -ENOMEM;
-+
-+	priv->mcu = mcu;
-+	priv->led_power_state = 1;
-+	mutex_init(&priv->lock);
-+	dev_set_drvdata(dev, priv);
-+
-+	child = device_get_next_child_node(dev, NULL);
-+	init_data.fwnode = child;
-+
-+	priv->cdev.brightness_set_blocking = iei_wt61p803_puzzle_led_brightness_set_blocking;
-+	priv->cdev.brightness_get = iei_wt61p803_puzzle_led_brightness_get;
-+	priv->cdev.max_brightness = 1;
-+
-+	ret = devm_led_classdev_register_ext(dev, &priv->cdev, &init_data);
-+	if (ret)
-+		dev_err(dev, "Could not register LED\n");
-+
-+	fwnode_handle_put(child);
-+	return ret;
-+}
-+
-+static const struct of_device_id iei_wt61p803_puzzle_led_of_match[] = {
-+	{ .compatible = "iei,wt61p803-puzzle-leds" },
-+	{ }
-+};
-+MODULE_DEVICE_TABLE(of, iei_wt61p803_puzzle_led_of_match);
-+
-+static struct platform_driver iei_wt61p803_puzzle_led_driver = {
-+	.driver = {
-+		.name = "iei-wt61p803-puzzle-led",
-+		.of_match_table = iei_wt61p803_puzzle_led_of_match,
-+	},
-+	.probe = iei_wt61p803_puzzle_led_probe,
-+};
-+module_platform_driver(iei_wt61p803_puzzle_led_driver);
-+
-+MODULE_DESCRIPTION("IEI WT61P803 PUZZLE front panel LED driver");
-+MODULE_AUTHOR("Luka Kovacic <luka.kovacic@sartura.hr>");
-+MODULE_LICENSE("GPL v2");
-+MODULE_ALIAS("platform:leds-iei-wt61p803-puzzle");
diff --git a/target/linux/mvebu/patches-5.15/905-Documentation-ABI-Add-iei-wt61p803-puzzle-driver-sys.patch b/target/linux/mvebu/patches-5.15/905-Documentation-ABI-Add-iei-wt61p803-puzzle-driver-sys.patch
deleted file mode 100644
index b1d420ef0a90a6..00000000000000
--- a/target/linux/mvebu/patches-5.15/905-Documentation-ABI-Add-iei-wt61p803-puzzle-driver-sys.patch
+++ /dev/null
@@ -1,82 +0,0 @@
-From 2fab3b4956c5b2f83c1e1abffc1df39de2933d83 Mon Sep 17 00:00:00 2001
-From: Luka Kovacic <luka.kovacic () sartura ! hr>
-Date: Tue, 24 Aug 2021 12:44:36 +0000
-Subject: [PATCH 5/7] Documentation/ABI: Add iei-wt61p803-puzzle driver sysfs
- interface documentation
-
-Add the iei-wt61p803-puzzle driver sysfs interface documentation to allow
-monitoring and control of the microcontroller from user space.
-
-Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
-Signed-off-by: Pavo Banicevic <pavo.banicevic@sartura.hr>
-Cc: Luka Perkov <luka.perkov@sartura.hr>
-Cc: Robert Marko <robert.marko@sartura.hr>
----
- .../testing/sysfs-driver-iei-wt61p803-puzzle  | 61 +++++++++++++++++++
- 1 file changed, 61 insertions(+)
- create mode 100644 Documentation/ABI/testing/sysfs-driver-iei-wt61p803-puzzle
-
---- /dev/null
-+++ b/Documentation/ABI/testing/sysfs-driver-iei-wt61p803-puzzle
-@@ -0,0 +1,61 @@
-+What:		/sys/bus/serial/devices/.../mac_address_*
-+Date:		September 2020
-+Contact:	Luka Kovacic <luka.kovacic@sartura.hr>
-+Description:	(RW) Internal factory assigned MAC address values
-+
-+What:		/sys/bus/serial/devices/.../serial_number
-+Date:		September 2020
-+Contact:	Luka Kovacic <luka.kovacic@sartura.hr>
-+Description:	(RW) Internal factory assigned serial number
-+
-+What:		/sys/bus/serial/devices/.../version
-+Date:		September 2020
-+Contact:	Luka Kovacic <luka.kovacic@sartura.hr>
-+Description:	(RO) Internal MCU firmware version
-+
-+What:		/sys/bus/serial/devices/.../protocol_version
-+Date:		September 2020
-+Contact:	Luka Kovacic <luka.kovacic@sartura.hr>
-+Description:	(RO) Internal MCU communication protocol version
-+
-+What:		/sys/bus/serial/devices/.../power_loss_recovery
-+Date:		September 2020
-+Contact:	Luka Kovacic <luka.kovacic@sartura.hr>
-+Description:	(RW) Host platform power loss recovery settings
-+		Value mapping: 0 - Always-On, 1 - Always-Off, 2 - Always-AC, 3 - Always-WA
-+
-+What:		/sys/bus/serial/devices/.../bootloader_mode
-+Date:		September 2020
-+Contact:	Luka Kovacic <luka.kovacic@sartura.hr>
-+Description:	(RO) Internal MCU bootloader mode status
-+		Value mapping:
-+		0 - normal mode
-+		1 - bootloader mode
-+
-+What:		/sys/bus/serial/devices/.../power_status
-+Date:		September 2020
-+Contact:	Luka Kovacic <luka.kovacic@sartura.hr>
-+Description:	(RO) Power status indicates the host platform power on method.
-+		Value mapping (bitwise list):
-+		0x80 - Null
-+		0x40 - Firmware flag
-+		0x20 - Power loss detection flag (powered off)
-+		0x10 - Power loss detection flag (AC mode)
-+		0x08 - Button power on
-+		0x04 - Wake-on-LAN power on
-+		0x02 - RTC alarm power on
-+		0x01 - AC recover power on
-+
-+What:		/sys/bus/serial/devices/.../build_info
-+Date:		September 2020
-+Contact:	Luka Kovacic <luka.kovacic@sartura.hr>
-+Description:	(RO) Internal MCU firmware build date
-+		Format: yyyy/mm/dd hh:mm
-+
-+What:		/sys/bus/serial/devices/.../ac_recovery_status
-+Date:		September 2020
-+Contact:	Luka Kovacic <luka.kovacic@sartura.hr>
-+Description:	(RO) Host platform AC recovery status value
-+		Value mapping:
-+		0 - board has not been recovered from power down
-+		1 - board has been recovered from power down
diff --git a/target/linux/mvebu/patches-5.15/906-Documentation-hwmon-Add-iei-wt61p803-puzzle-hwmon-dr.patch b/target/linux/mvebu/patches-5.15/906-Documentation-hwmon-Add-iei-wt61p803-puzzle-hwmon-dr.patch
deleted file mode 100644
index 9015436f6a4c9c..00000000000000
--- a/target/linux/mvebu/patches-5.15/906-Documentation-hwmon-Add-iei-wt61p803-puzzle-hwmon-dr.patch
+++ /dev/null
@@ -1,74 +0,0 @@
-From 0aff3e5923fecc6842473ad07a688d6e2f2c2d55 Mon Sep 17 00:00:00 2001
-From: Luka Kovacic <luka.kovacic () sartura ! hr>
-Date: Tue, 24 Aug 2021 12:44:37 +0000
-Subject: [PATCH 6/7] Documentation/hwmon: Add iei-wt61p803-puzzle hwmon driver
- documentation
-
-Add the iei-wt61p803-puzzle driver hwmon driver interface documentation.
-
-Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
-Signed-off-by: Pavo Banicevic <pavo.banicevic@sartura.hr>
-Cc: Luka Perkov <luka.perkov@sartura.hr>
-Cc: Robert Marko <robert.marko@sartura.hr>
----
- .../hwmon/iei-wt61p803-puzzle-hwmon.rst       | 43 +++++++++++++++++++
- Documentation/hwmon/index.rst                 |  1 +
- 2 files changed, 44 insertions(+)
- create mode 100644 Documentation/hwmon/iei-wt61p803-puzzle-hwmon.rst
-
---- /dev/null
-+++ b/Documentation/hwmon/iei-wt61p803-puzzle-hwmon.rst
-@@ -0,0 +1,43 @@
-+.. SPDX-License-Identifier: GPL-2.0-only
-+
-+Kernel driver iei-wt61p803-puzzle-hwmon
-+=======================================
-+
-+Supported chips:
-+ * IEI WT61P803 PUZZLE for IEI Puzzle M801
-+
-+   Prefix: 'iei-wt61p803-puzzle-hwmon'
-+
-+Author: Luka Kovacic <luka.kovacic@sartura.hr>
-+
-+
-+Description
-+-----------
-+
-+This driver adds fan and temperature sensor reading for some IEI Puzzle
-+series boards.
-+
-+Sysfs attributes
-+----------------
-+
-+The following attributes are supported:
-+
-+- IEI WT61P803 PUZZLE for IEI Puzzle M801
-+
-+/sys files in hwmon subsystem
-+-----------------------------
-+
-+================= == =====================================================
-+fan[1-5]_input    RO files for fan speed (in RPM)
-+pwm[1-2]          RW files for fan[1-2] target duty cycle (0..255)
-+temp[1-2]_input   RO files for temperature sensors, in millidegree Celsius
-+================= == =====================================================
-+
-+/sys files in thermal subsystem
-+-------------------------------
-+
-+================= == =====================================================
-+cur_state         RW file for current cooling state of the cooling device
-+                     (0..max_state)
-+max_state         RO file for maximum cooling state of the cooling device
-+================= == =====================================================
---- a/Documentation/hwmon/index.rst
-+++ b/Documentation/hwmon/index.rst
-@@ -74,6 +74,7 @@ Hardware Monitoring Kernel Drivers
-    ibmaem
-    ibm-cffps
-    ibmpowernv
-+   iei-wt61p803-puzzle-hwmon
-    ina209
-    ina2xx
-    ina3221
diff --git a/target/linux/mvebu/patches-5.15/907-MAINTAINERS-Add-an-entry-for-the-IEI-WT61P803-PUZZLE.patch b/target/linux/mvebu/patches-5.15/907-MAINTAINERS-Add-an-entry-for-the-IEI-WT61P803-PUZZLE.patch
deleted file mode 100644
index 0b6891343d2106..00000000000000
--- a/target/linux/mvebu/patches-5.15/907-MAINTAINERS-Add-an-entry-for-the-IEI-WT61P803-PUZZLE.patch
+++ /dev/null
@@ -1,41 +0,0 @@
-From 12479baad28d2a08c6cb9e83471057635fa1635c Mon Sep 17 00:00:00 2001
-From: Luka Kovacic <luka.kovacic () sartura ! hr>
-Date: Tue, 24 Aug 2021 12:44:38 +0000
-Subject: [PATCH 7/7] MAINTAINERS: Add an entry for the IEI WT61P803 PUZZLE
- driver
-
-Add an entry for the IEI WT61P803 PUZZLE driver (MFD, HWMON, LED drivers).
-
-Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
-Signed-off-by: Pavo Banicevic <pavo.banicevic@sartura.hr>
-Cc: Luka Perkov <luka.perkov@sartura.hr>
-Cc: Robert Marko <robert.marko@sartura.hr>
----
- MAINTAINERS | 16 ++++++++++++++++
- 1 file changed, 16 insertions(+)
-
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -9057,6 +9057,22 @@ F:	include/net/nl802154.h
- F:	net/ieee802154/
- F:	net/mac802154/
- 
-+IEI WT61P803 M801 MFD DRIVER
-+M:	Luka Kovacic <luka.kovacic@sartura.hr>
-+M:	Luka Perkov <luka.perkov@sartura.hr>
-+M:	Goran Medic <goran.medic@sartura.hr>
-+L:	linux-kernel@vger.kernel.org
-+S:	Maintained
-+F:	Documentation/ABI/stable/sysfs-driver-iei-wt61p803-puzzle
-+F:	Documentation/devicetree/bindings/hwmon/iei,wt61p803-puzzle-hwmon.yaml
-+F:	Documentation/devicetree/bindings/leds/iei,wt61p803-puzzle-leds.yaml
-+F:	Documentation/devicetree/bindings/mfd/iei,wt61p803-puzzle.yaml
-+F:	Documentation/hwmon/iei-wt61p803-puzzle-hwmon.rst
-+F:	drivers/hwmon/iei-wt61p803-puzzle-hwmon.c
-+F:	drivers/leds/leds-iei-wt61p803-puzzle.c
-+F:	drivers/mfd/iei-wt61p803-puzzle.c
-+F:	include/linux/mfd/iei-wt61p803-puzzle.h
-+
- IFE PROTOCOL
- M:	Yotam Gigi <yotam.gi@gmail.com>
- M:	Jamal Hadi Salim <jhs@mojatatu.com>
diff --git a/target/linux/mvebu/patches-5.15/910-drivers-leds-wt61p803-puzzle-improvements.patch b/target/linux/mvebu/patches-5.15/910-drivers-leds-wt61p803-puzzle-improvements.patch
deleted file mode 100644
index 150a65498cd3d4..00000000000000
--- a/target/linux/mvebu/patches-5.15/910-drivers-leds-wt61p803-puzzle-improvements.patch
+++ /dev/null
@@ -1,271 +0,0 @@
---- a/drivers/leds/leds-iei-wt61p803-puzzle.c
-+++ b/drivers/leds/leds-iei-wt61p803-puzzle.c
-@@ -9,9 +9,13 @@
- #include <linux/mfd/iei-wt61p803-puzzle.h>
- #include <linux/mod_devicetable.h>
- #include <linux/module.h>
-+#include <linux/of.h>
- #include <linux/platform_device.h>
- #include <linux/property.h>
- #include <linux/slab.h>
-+#include <linux/workqueue.h>
-+
-+#define IEI_LEDS_MAX		4
- 
- enum iei_wt61p803_puzzle_led_state {
- 	IEI_LED_OFF = 0x30,
-@@ -33,7 +37,11 @@ struct iei_wt61p803_puzzle_led {
- 	struct iei_wt61p803_puzzle *mcu;
- 	unsigned char response_buffer[IEI_WT61P803_PUZZLE_BUF_SIZE];
- 	struct mutex lock; /* mutex to protect led_power_state */
-+	struct work_struct work;
- 	int led_power_state;
-+	int id;
-+	u8 blinking;
-+	bool active_low;
- };
- 
- static inline struct iei_wt61p803_puzzle_led *cdev_to_iei_wt61p803_puzzle_led
-@@ -51,10 +59,18 @@ static int iei_wt61p803_puzzle_led_brigh
- 	size_t reply_size;
- 	int ret;
- 
-+	if (priv->blinking) {
-+		if (brightness == LED_OFF)
-+			priv->blinking = 0;
-+		else
-+			return 0;
-+	}
-+
- 	led_power_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START;
- 	led_power_cmd[1] = IEI_WT61P803_PUZZLE_CMD_LED;
--	led_power_cmd[2] = IEI_WT61P803_PUZZLE_CMD_LED_POWER;
--	led_power_cmd[3] = brightness == LED_OFF ? IEI_LED_OFF : IEI_LED_ON;
-+	led_power_cmd[2] = IEI_WT61P803_PUZZLE_CMD_LED_SET(priv->id);
-+	led_power_cmd[3] = ((brightness == LED_OFF) ^ priv->active_low) ?
-+				IEI_LED_OFF : priv->blinking?priv->blinking:IEI_LED_ON;
- 
- 	ret = iei_wt61p803_puzzle_write_command(priv->mcu, led_power_cmd,
- 						sizeof(led_power_cmd),
-@@ -90,39 +106,166 @@ static enum led_brightness iei_wt61p803_
- 	return led_state;
- }
- 
-+static void iei_wt61p803_puzzle_led_apply_blink(struct work_struct *work)
-+{
-+	struct iei_wt61p803_puzzle_led *priv = container_of(work, struct iei_wt61p803_puzzle_led, work);
-+	unsigned char led_blink_cmd[5] = {};
-+	unsigned char resp_buf[IEI_WT61P803_PUZZLE_BUF_SIZE];
-+	size_t reply_size;
-+
-+	led_blink_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START;
-+	led_blink_cmd[1] = IEI_WT61P803_PUZZLE_CMD_LED;
-+	led_blink_cmd[2] = IEI_WT61P803_PUZZLE_CMD_LED_SET(priv->id);
-+	led_blink_cmd[3] = priv->blinking;
-+
-+	iei_wt61p803_puzzle_write_command(priv->mcu, led_blink_cmd,
-+					  sizeof(led_blink_cmd),
-+					  resp_buf,
-+					  &reply_size);
-+
-+	return;
-+}
-+
-+static int iei_wt61p803_puzzle_led_set_blink(struct led_classdev *cdev,
-+					     unsigned long *delay_on,
-+					     unsigned long *delay_off)
-+{
-+	struct iei_wt61p803_puzzle_led *priv = cdev_to_iei_wt61p803_puzzle_led(cdev);
-+	u8 blink_mode = 0;
-+	int ret = 0;
-+
-+	/* set defaults */
-+	if (!*delay_on && !*delay_off) {
-+		*delay_on = 500;
-+		*delay_off = 500;
-+	}
-+
-+	/* minimum delay for soft-driven blinking is 100ms to keep load low */
-+	if (*delay_on < 100)
-+		*delay_on = 100;
-+
-+	if (*delay_off < 100)
-+		*delay_off = 100;
-+
-+	/* offload blinking to hardware, if possible */
-+	if (*delay_on != *delay_off) {
-+		ret = -EINVAL;
-+	} else if (*delay_on == 100) {
-+		blink_mode = IEI_LED_BLINK_5HZ;
-+		*delay_on = 100;
-+		*delay_off = 100;
-+	} else if (*delay_on <= 500) {
-+		blink_mode = IEI_LED_BLINK_1HZ;
-+		*delay_on = 500;
-+		*delay_off = 500;
-+	} else {
-+		ret = -EINVAL;
-+	}
-+
-+	mutex_lock(&priv->lock);
-+	priv->blinking = blink_mode;
-+	mutex_unlock(&priv->lock);
-+
-+	if (blink_mode)
-+		schedule_work(&priv->work);
-+
-+	return ret;
-+}
-+
-+
-+static int iei_wt61p803_puzzle_led_set_dt_default(struct led_classdev *cdev,
-+				     struct device_node *np)
-+{
-+	const char *state;
-+	int ret = 0;
-+
-+	state = of_get_property(np, "default-state", NULL);
-+	if (state) {
-+		if (!strcmp(state, "on")) {
-+			ret =
-+			iei_wt61p803_puzzle_led_brightness_set_blocking(
-+				cdev, cdev->max_brightness);
-+		} else  {
-+			ret = iei_wt61p803_puzzle_led_brightness_set_blocking(
-+				cdev, LED_OFF);
-+		}
-+	}
-+
-+	return ret;
-+}
-+
- static int iei_wt61p803_puzzle_led_probe(struct platform_device *pdev)
- {
- 	struct device *dev = &pdev->dev;
-+	struct device_node *np = dev_of_node(dev);
-+	struct device_node *child;
- 	struct iei_wt61p803_puzzle *mcu = dev_get_drvdata(dev->parent);
- 	struct iei_wt61p803_puzzle_led *priv;
--	struct led_init_data init_data = {};
--	struct fwnode_handle *child;
- 	int ret;
-+	u32 reg;
- 
--	if (device_get_child_node_count(dev) != 1)
-+	if (device_get_child_node_count(dev) > IEI_LEDS_MAX)
- 		return -EINVAL;
- 
--	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
--	if (!priv)
--		return -ENOMEM;
--
--	priv->mcu = mcu;
--	priv->led_power_state = 1;
--	mutex_init(&priv->lock);
--	dev_set_drvdata(dev, priv);
--
--	child = device_get_next_child_node(dev, NULL);
--	init_data.fwnode = child;
--
--	priv->cdev.brightness_set_blocking = iei_wt61p803_puzzle_led_brightness_set_blocking;
--	priv->cdev.brightness_get = iei_wt61p803_puzzle_led_brightness_get;
--	priv->cdev.max_brightness = 1;
-+	for_each_available_child_of_node(np, child) {
-+		struct led_init_data init_data = {};
- 
--	ret = devm_led_classdev_register_ext(dev, &priv->cdev, &init_data);
--	if (ret)
--		dev_err(dev, "Could not register LED\n");
-+		ret = of_property_read_u32(child, "reg", &reg);
-+		if (ret) {
-+			dev_err(dev, "Failed to read led 'reg' property\n");
-+			goto put_child_node;
-+		}
-+
-+		if (reg > IEI_LEDS_MAX) {
-+			dev_err(dev, "Invalid led reg %u\n", reg);
-+			ret = -EINVAL;
-+			goto put_child_node;
-+		}
-+
-+		priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
-+		if (!priv) {
-+			ret = -ENOMEM;
-+			goto put_child_node;
-+		}
-+
-+		mutex_init(&priv->lock);
-+
-+		dev_set_drvdata(dev, priv);
-+
-+		if (of_property_read_bool(child, "active-low"))
-+			priv->active_low = true;
-+
-+		priv->mcu = mcu;
-+		priv->id = reg;
-+		priv->led_power_state = 1;
-+		priv->blinking = 0;
-+		init_data.fwnode = of_fwnode_handle(child);
-+
-+		priv->cdev.brightness_set_blocking = iei_wt61p803_puzzle_led_brightness_set_blocking;
-+		priv->cdev.brightness_get = iei_wt61p803_puzzle_led_brightness_get;
-+		priv->cdev.blink_set = iei_wt61p803_puzzle_led_set_blink;
-+
-+		priv->cdev.max_brightness = 1;
-+
-+		INIT_WORK(&priv->work, iei_wt61p803_puzzle_led_apply_blink);
-+
-+		ret = iei_wt61p803_puzzle_led_set_dt_default(&priv->cdev, child);
-+		if (ret) {
-+			dev_err(dev, "Could apply default from DT\n");
-+			goto put_child_node;
-+		}
-+
-+		ret = devm_led_classdev_register_ext(dev, &priv->cdev, &init_data);
-+		if (ret) {
-+			dev_err(dev, "Could not register LED\n");
-+			goto put_child_node;
-+		}
-+	}
-+
-+	return ret;
- 
--	fwnode_handle_put(child);
-+put_child_node:
-+	of_node_put(child);
- 	return ret;
- }
- 
---- a/include/linux/mfd/iei-wt61p803-puzzle.h
-+++ b/include/linux/mfd/iei-wt61p803-puzzle.h
-@@ -36,7 +36,7 @@
- #define IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_POWER_LOSS 0x41 /* A */
- 
- #define IEI_WT61P803_PUZZLE_CMD_LED			0x52 /* R */
--#define IEI_WT61P803_PUZZLE_CMD_LED_POWER		0x31 /* 1 */
-+#define IEI_WT61P803_PUZZLE_CMD_LED_SET(n)		(0x30 | (n))
- 
- #define IEI_WT61P803_PUZZLE_CMD_TEMP			0x54 /* T */
- #define IEI_WT61P803_PUZZLE_CMD_TEMP_ALL		0x41 /* A */
---- a/drivers/mfd/iei-wt61p803-puzzle.c
-+++ b/drivers/mfd/iei-wt61p803-puzzle.c
-@@ -176,6 +176,9 @@ static int iei_wt61p803_puzzle_recv_buf(
- 	struct iei_wt61p803_puzzle *mcu = serdev_device_get_drvdata(serdev);
- 	int ret;
- 
-+	print_hex_dump_debug("puzzle-mcu rx: ", DUMP_PREFIX_NONE,
-+			     16, 1, data, size, false);
-+
- 	ret = iei_wt61p803_puzzle_process_resp(mcu, data, size);
- 	/* Return the number of processed bytes if function returns error,
- 	 * discard the remaining incoming data, since the frame this data
-@@ -246,6 +249,9 @@ int iei_wt61p803_puzzle_write_command(st
- 
- 	cmd[size - 1] = iei_wt61p803_puzzle_checksum(cmd, size - 1);
- 
-+	print_hex_dump_debug("puzzle-mcu tx: ", DUMP_PREFIX_NONE,
-+			     16, 1, cmd, size, false);
-+
- 	/* Initialize reply struct */
- 	reinit_completion(&mcu->reply->received);
- 	mcu->reply->size = 0;
diff --git a/target/linux/mvebu/patches-5.15/911-drivers-leds-wt61p803-puzzle-mcu-retry.patch b/target/linux/mvebu/patches-5.15/911-drivers-leds-wt61p803-puzzle-mcu-retry.patch
deleted file mode 100644
index 2f0b1788ff68f2..00000000000000
--- a/target/linux/mvebu/patches-5.15/911-drivers-leds-wt61p803-puzzle-mcu-retry.patch
+++ /dev/null
@@ -1,63 +0,0 @@
---- a/drivers/mfd/iei-wt61p803-puzzle.c
-+++ b/drivers/mfd/iei-wt61p803-puzzle.c
-@@ -241,6 +241,7 @@ int iei_wt61p803_puzzle_write_command(st
- {
- 	struct device *dev = &mcu->serdev->dev;
- 	int ret;
-+	int retries;
- 
- 	if (size <= 1 || size > IEI_WT61P803_PUZZLE_MAX_COMMAND_LENGTH)
- 		return -EINVAL;
-@@ -252,24 +253,36 @@ int iei_wt61p803_puzzle_write_command(st
- 	print_hex_dump_debug("puzzle-mcu tx: ", DUMP_PREFIX_NONE,
- 			     16, 1, cmd, size, false);
- 
-+	retries = 3;
- 	/* Initialize reply struct */
--	reinit_completion(&mcu->reply->received);
--	mcu->reply->size = 0;
--	usleep_range(2000, 10000);
--	serdev_device_write_flush(mcu->serdev);
--	ret = serdev_device_write_buf(mcu->serdev, cmd, size);
--	if (ret < 0)
--		goto exit;
--
--	serdev_device_wait_until_sent(mcu->serdev, IEI_WT61P803_PUZZLE_GENERAL_TIMEOUT);
--	ret = wait_for_completion_timeout(&mcu->reply->received,
--					  IEI_WT61P803_PUZZLE_GENERAL_TIMEOUT);
--	if (ret == 0) {
--		dev_err(dev, "Command reply receive timeout\n");
--		ret = -ETIMEDOUT;
--		goto exit;
-+	while (retries) {
-+		reinit_completion(&mcu->reply->received);
-+		mcu->reply->size = 0;
-+		usleep_range(2000, 10000);
-+		serdev_device_write_flush(mcu->serdev);
-+		ret = serdev_device_write_buf(mcu->serdev, cmd, size);
-+		if (ret < 0)
-+			goto exit;
-+
-+		serdev_device_wait_until_sent(mcu->serdev, IEI_WT61P803_PUZZLE_GENERAL_TIMEOUT);
-+		ret = wait_for_completion_timeout(&mcu->reply->received,
-+						  IEI_WT61P803_PUZZLE_GENERAL_TIMEOUT);
-+		retries--;
-+		if (ret == 0) {
-+			if (retries == 0) {
-+				dev_err(dev, "Command reply receive timeout\n");
-+				ret = -ETIMEDOUT;
-+				goto exit;
-+			}
-+		}
-+		else {
-+			if (mcu->reply->data[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START &&
-+				mcu->reply->data[1] == IEI_WT61P803_PUZZLE_CMD_RESPONSE_OK &&
-+				mcu->reply->data[2] == IEI_WT61P803_PUZZLE_CHECKSUM_RESPONSE_OK) {
-+				break;
-+			}
-+		}
- 	}
--
- 	*reply_size = mcu->reply->size;
- 	/* Copy the received data, as it will not be available after a new frame is received */
- 	memcpy(reply_data, mcu->reply->data, mcu->reply->size);
diff --git a/target/linux/mvebu/patches-6.1/000-cpufreq-armada-8k-add-ap807-support.patch b/target/linux/mvebu/patches-6.1/000-cpufreq-armada-8k-add-ap807-support.patch
new file mode 100644
index 00000000000000..354d262015214e
--- /dev/null
+++ b/target/linux/mvebu/patches-6.1/000-cpufreq-armada-8k-add-ap807-support.patch
@@ -0,0 +1,59 @@
+From 8eec6e740b564ec5e1da59ab7070b89aa23c9973 Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Fri, 16 Jun 2023 12:41:30 +0100
+Subject: [PATCH] cpufreq: armada-8k: add ap807 support
+
+Add support for the Armada AP807 die to armada-8k. This uses a
+different compatible for the CPU clock which needs to be added to
+the cpufreq driver.
+
+This commit takes a different approach to the WindRiver patch
+"cpufreq: armada: enable ap807-cpu-clk" in that rather than calling
+of_find_compatible_node() for each compatible, we use a table of
+IDs instead.
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
+---
+ drivers/cpufreq/armada-8k-cpufreq.c | 16 +++++++++-------
+ 1 file changed, 9 insertions(+), 7 deletions(-)
+
+--- a/drivers/cpufreq/armada-8k-cpufreq.c
++++ b/drivers/cpufreq/armada-8k-cpufreq.c
+@@ -21,6 +21,13 @@
+ #include <linux/pm_opp.h>
+ #include <linux/slab.h>
+ 
++static const struct of_device_id __maybe_unused armada_8k_cpufreq_of_match[] = {
++	{ .compatible = "marvell,ap806-cpu-clock" },
++	{ .compatible = "marvell,ap807-cpu-clock" },
++	{ },
++};
++MODULE_DEVICE_TABLE(of, armada_8k_cpufreq_of_match);
++
+ /*
+  * Setup the opps list with the divider for the max frequency, that
+  * will be filled at runtime.
+@@ -127,7 +134,8 @@ static int __init armada_8k_cpufreq_init
+ 	struct device_node *node;
+ 	struct cpumask cpus;
+ 
+-	node = of_find_compatible_node(NULL, NULL, "marvell,ap806-cpu-clock");
++	node = of_find_matching_node_and_match(NULL, armada_8k_cpufreq_of_match,
++					       NULL);
+ 	if (!node || !of_device_is_available(node)) {
+ 		of_node_put(node);
+ 		return -ENODEV;
+@@ -204,12 +212,6 @@ static void __exit armada_8k_cpufreq_exi
+ }
+ module_exit(armada_8k_cpufreq_exit);
+ 
+-static const struct of_device_id __maybe_unused armada_8k_cpufreq_of_match[] = {
+-	{ .compatible = "marvell,ap806-cpu-clock" },
+-	{ },
+-};
+-MODULE_DEVICE_TABLE(of, armada_8k_cpufreq_of_match);
+-
+ MODULE_AUTHOR("Gregory Clement <gregory.clement@bootlin.com>");
+ MODULE_DESCRIPTION("Armada 8K cpufreq driver");
+ MODULE_LICENSE("GPL");
diff --git a/target/linux/mvebu/patches-6.1/400-find_active_root.patch b/target/linux/mvebu/patches-6.1/400-find_active_root.patch
index 5582d20c6828d2..90164adcd43d78 100644
--- a/target/linux/mvebu/patches-6.1/400-find_active_root.patch
+++ b/target/linux/mvebu/patches-6.1/400-find_active_root.patch
@@ -22,7 +22,7 @@ Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
  	struct device_node *pp;
  	int nr_parts, i, ret = 0;
  	bool dedicated = true;
-@@ -133,9 +136,13 @@ static int parse_fixed_partitions(struct
+@@ -152,9 +155,13 @@ static int parse_fixed_partitions(struct
  		parts[i].size = of_read_number(reg + a_cells, s_cells);
  		parts[i].of_node = pp;
  
@@ -39,7 +39,7 @@ Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
  		parts[i].name = partname;
  
  		if (of_get_property(pp, "read-only", &len))
-@@ -252,6 +259,18 @@ static int __init ofpart_parser_init(voi
+@@ -271,6 +278,18 @@ static int __init ofpart_parser_init(voi
  	return 0;
  }
  
diff --git a/target/linux/mvebu/patches-6.1/700-mvneta-tx-queue-workaround.patch b/target/linux/mvebu/patches-6.1/700-mvneta-tx-queue-workaround.patch
index 15762be81d40ec..14f93592fe3a75 100644
--- a/target/linux/mvebu/patches-6.1/700-mvneta-tx-queue-workaround.patch
+++ b/target/linux/mvebu/patches-6.1/700-mvneta-tx-queue-workaround.patch
@@ -1,3 +1,6 @@
+From: Felix Fietkau <nbd@nbd.name>
+Subject: mvneta: tx queue workaround
+
 The hardware queue scheduling is apparently configured with fixed
 priorities, which creates a nasty fairness issue where traffic from one
 CPU can starve traffic from all other CPUs.
@@ -5,11 +8,13 @@ CPU can starve traffic from all other CPUs.
 Work around this issue by forcing all tx packets to go through one CPU,
 until this issue is fixed properly.
 
+Ref: https://github.com/openwrt/openwrt/issues/5411
+
 Signed-off-by: Felix Fietkau <nbd@nbd.name>
 ---
 --- a/drivers/net/ethernet/marvell/mvneta.c
 +++ b/drivers/net/ethernet/marvell/mvneta.c
-@@ -5234,6 +5234,16 @@ static int mvneta_setup_tc(struct net_de
+@@ -5233,6 +5233,16 @@ static int mvneta_setup_tc(struct net_de
  	}
  }
  
@@ -26,7 +31,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  static const struct net_device_ops mvneta_netdev_ops = {
  	.ndo_open            = mvneta_open,
  	.ndo_stop            = mvneta_stop,
-@@ -5244,6 +5254,9 @@ static const struct net_device_ops mvnet
+@@ -5243,6 +5253,9 @@ static const struct net_device_ops mvnet
  	.ndo_fix_features    = mvneta_fix_features,
  	.ndo_get_stats64     = mvneta_get_stats64,
  	.ndo_eth_ioctl        = mvneta_ioctl,
diff --git a/target/linux/mvebu/patches-6.1/701-mvpp2-read-mac-address-from-nvmem.patch b/target/linux/mvebu/patches-6.1/701-mvpp2-read-mac-address-from-nvmem.patch
new file mode 100644
index 00000000000000..1c4194776aac3c
--- /dev/null
+++ b/target/linux/mvebu/patches-6.1/701-mvpp2-read-mac-address-from-nvmem.patch
@@ -0,0 +1,27 @@
+From: Tobias Schramm <tobias@t-sys.eu>
+Subject: mvpp2: support fetching mac address from nvmem
+
+The mvpp2 driver did not query nvmem for hardware mac addresses. This
+patch adds querying of mac addresses stored in nvmem cells as a further
+fallback option before assigning a random address.
+Purposely added separately to fwnode_get_mac_address() above to maintain
+existing behaviour with builtin adapter mac address still taking
+precedence.
+
+Signed-off-by: Tobias Schramm <tobias@t-sys.eu>
+---
+--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
++++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+@@ -6134,6 +6134,12 @@ static void mvpp2_port_copy_mac_addr(str
+ 		}
+ 	}
+ 
++	if (!of_get_mac_address(to_of_node(fwnode), hw_mac_addr)) {
++		*mac_from = "nvmem cell";
++		eth_hw_addr_set(dev, hw_mac_addr);
++		return;
++	}
++
+ 	*mac_from = "random";
+ 	eth_hw_addr_random(dev);
+ }
diff --git a/target/linux/mvebu/patches-6.1/902-drivers-mfd-Add-a-driver-for-IEI-WT61P803-PUZZLE-MCU.patch b/target/linux/mvebu/patches-6.1/902-drivers-mfd-Add-a-driver-for-IEI-WT61P803-PUZZLE-MCU.patch
index d2134042500102..47d9e3a263761b 100644
--- a/target/linux/mvebu/patches-6.1/902-drivers-mfd-Add-a-driver-for-IEI-WT61P803-PUZZLE-MCU.patch
+++ b/target/linux/mvebu/patches-6.1/902-drivers-mfd-Add-a-driver-for-IEI-WT61P803-PUZZLE-MCU.patch
@@ -26,7 +26,7 @@ Cc: Robert Marko <robert.marko@sartura.hr>
 
 --- a/drivers/mfd/Kconfig
 +++ b/drivers/mfd/Kconfig
-@@ -2221,6 +2221,15 @@ config SGI_MFD_IOC3
+@@ -2222,6 +2222,15 @@ config SGI_MFD_IOC3
  	  If you have an SGI Origin, Octane, or a PCI IOC3 card,
  	  then say Y. Otherwise say N.
  
diff --git a/target/linux/mvebu/patches-6.1/904-drivers-leds-Add-the-IEI-WT61P803-PUZZLE-LED-driver.patch b/target/linux/mvebu/patches-6.1/904-drivers-leds-Add-the-IEI-WT61P803-PUZZLE-LED-driver.patch
index ec783256e32559..1abb1b94166be1 100644
--- a/target/linux/mvebu/patches-6.1/904-drivers-leds-Add-the-IEI-WT61P803-PUZZLE-LED-driver.patch
+++ b/target/linux/mvebu/patches-6.1/904-drivers-leds-Add-the-IEI-WT61P803-PUZZLE-LED-driver.patch
@@ -30,7 +30,7 @@ Cc: Robert Marko <robert.marko@sartura.hr>
 
 --- a/drivers/leds/Kconfig
 +++ b/drivers/leds/Kconfig
-@@ -299,6 +299,14 @@ config LEDS_IPAQ_MICRO
+@@ -300,6 +300,14 @@ config LEDS_IPAQ_MICRO
  	  Choose this option if you want to use the notification LED on
  	  Compaq/HP iPAQ h3100 and h3600.
  
diff --git a/target/linux/octeon/files/arch/mips/boot/dts/cavium-octeon/cn7130_ubnt_edgerouter-e300.dtsi b/target/linux/octeon/files/arch/mips/boot/dts/cavium-octeon/cn7130_ubnt_edgerouter-e300.dtsi
index ad73a08a1e2454..0da92abca8b541 100644
--- a/target/linux/octeon/files/arch/mips/boot/dts/cavium-octeon/cn7130_ubnt_edgerouter-e300.dtsi
+++ b/target/linux/octeon/files/arch/mips/boot/dts/cavium-octeon/cn7130_ubnt_edgerouter-e300.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "ubnt,edgerouter-e300", "cavium,cn7130";
@@ -32,12 +33,14 @@
 		compatible = "gpio-leds";
 
 		led_power_blue: power_blue {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_power_white: power_white {
-			label = "white:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
 		};
 	};
diff --git a/target/linux/octeontx/base-files/etc/board.d/02_network b/target/linux/octeontx/base-files/etc/board.d/02_network
index 1397dffa5ef329..2727e44e438b5b 100644
--- a/target/linux/octeontx/base-files/etc/board.d/02_network
+++ b/target/linux/octeontx/base-files/etc/board.d/02_network
@@ -9,6 +9,17 @@ board=$(board_name)
 board_config_update
 
 case "$board" in
+gw,gw610x|\
+gw,gw6903)
+	ucidef_set_interfaces_lan 'eth0'
+	;;
+gw,gw620x|\
+gw,gw630x)
+	ucidef_set_interfaces_lan_wan 'eth0' 'eth1'
+	;;
+gw,gw640x)
+	ucidef_set_interfaces_lan_wan 'eth0 eth1 eth2 eth3' 'eth4'
+	;;
 esac
 
 board_config_flush
diff --git a/target/linux/octeontx/patches-5.15/0004-PCI-add-quirk-for-Gateworks-PLX-PEX860x-switch-with-.patch b/target/linux/octeontx/patches-5.15/0004-PCI-add-quirk-for-Gateworks-PLX-PEX860x-switch-with-.patch
index 0400d1e9ddc841..6dd02bed54a5ce 100644
--- a/target/linux/octeontx/patches-5.15/0004-PCI-add-quirk-for-Gateworks-PLX-PEX860x-switch-with-.patch
+++ b/target/linux/octeontx/patches-5.15/0004-PCI-add-quirk-for-Gateworks-PLX-PEX860x-switch-with-.patch
@@ -22,7 +22,7 @@ Signed-off-by: Tim Harvey <tharvey@gateworks.com>
  #include <linux/platform_data/x86/apple.h>
  #include <linux/pm_runtime.h>
  #include <linux/suspend.h>
-@@ -5879,3 +5880,34 @@ static void nvidia_ion_ahci_fixup(struct
+@@ -5883,3 +5884,34 @@ static void nvidia_ion_ahci_fixup(struct
  	pdev->dev_flags |= PCI_DEV_FLAGS_HAS_MSI_MASKING;
  }
  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0ab8, nvidia_ion_ahci_fixup);
diff --git a/target/linux/omap/Makefile b/target/linux/omap/Makefile
index f995b5eae4dc25..fc0842d056e448 100644
--- a/target/linux/omap/Makefile
+++ b/target/linux/omap/Makefile
@@ -12,7 +12,7 @@ CPU_TYPE:=cortex-a8
 CPU_SUBTYPE:=vfpv3
 SUBTARGETS:=generic
 
-KERNEL_PATCHVER:=5.15
+KERNEL_PATCHVER:=6.1
 
 KERNELNAME:=zImage dtbs
 
diff --git a/target/linux/omap/config-5.15 b/target/linux/omap/config-5.15
deleted file mode 100644
index 888345c75a85d2..00000000000000
--- a/target/linux/omap/config-5.15
+++ /dev/null
@@ -1,691 +0,0 @@
-# CONFIG_AHCI_DM816 is not set
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_AM335X_CONTROL_USB=y
-CONFIG_AM335X_PHY_USB=y
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_ARCH_OMAP2PLUS_TYPICAL=y
-CONFIG_ARCH_OMAP3=y
-CONFIG_ARCH_OMAP4=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM=y
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_ARM_ATAG_DTB_COMPAT=y
-CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
-CONFIG_ARM_CPUIDLE=y
-CONFIG_ARM_CPU_SUSPEND=y
-CONFIG_ARM_CRYPTO=y
-CONFIG_ARM_ERRATA_430973=y
-CONFIG_ARM_ERRATA_720789=y
-CONFIG_ARM_ERRATA_754322=y
-CONFIG_ARM_ERRATA_775420=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_HAS_SG_CHAIN=y
-CONFIG_ARM_HEAVY_MB=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-CONFIG_ARM_OMAP2PLUS_CPUFREQ=y
-CONFIG_ARM_PATCH_IDIV=y
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_THUMBEE=y
-CONFIG_ARM_TI_CPUFREQ=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_ASSOCIATIVE_ARRAY=y
-CONFIG_AT803X_PHY=y
-CONFIG_ATA=y
-CONFIG_AUDIT=y
-CONFIG_AUDITSYSCALL=y
-CONFIG_AUDIT_GENERIC=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_TPS65217 is not set
-CONFIG_BCH=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=16384
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_PM=y
-CONFIG_BOUNCE=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_CACHE_L2X0=y
-CONFIG_CEC_CORE=y
-# CONFIG_CHARGER_TPS65217 is not set
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLKSRC_TI_32K=y
-CONFIG_CLK_TWL6040=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMA=y
-CONFIG_CMA_ALIGNMENT=8
-CONFIG_CMA_AREAS=7
-# CONFIG_CMA_DEBUG is not set
-# CONFIG_CMA_DEBUGFS is not set
-CONFIG_CMA_SIZE_MBYTES=16
-# CONFIG_CMA_SIZE_SEL_MAX is not set
-CONFIG_CMA_SIZE_SEL_MBYTES=y
-# CONFIG_CMA_SIZE_SEL_MIN is not set
-# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
-# CONFIG_CMA_SYSFS is not set
-CONFIG_CMDLINE="root=/dev/mmcblk0p2 rootwait console=ttyO2,115200"
-CONFIG_CMDLINE_FROM_BOOTLOADER=y
-CONFIG_COMMON_CLK=y
-# CONFIG_COMMON_CLK_PALMAS is not set
-# CONFIG_COMMON_CLK_TI_ADPLL is not set
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_CONNECTOR=y
-CONFIG_CONTIG_ALLOC=y
-CONFIG_CPUFREQ_DT=y
-CONFIG_CPUFREQ_DT_PLATDEV=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_SPECTRE=y
-CONFIG_CPU_THERMAL=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRAMFS=y
-CONFIG_CRC16=y
-CONFIG_CRC7=y
-CONFIG_CRC_CCITT=y
-CONFIG_CRC_ITU_T=y
-CONFIG_CRC_T10DIF=y
-CONFIG_CRYPTO_AES_ARM=y
-CONFIG_CRYPTO_AES_ARM_BS=y
-CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_CHACHA20_NEON=y
-CONFIG_CRYPTO_CRC32=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_CRCT10DIF=y
-CONFIG_CRYPTO_CRYPTD=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_DES=y
-CONFIG_CRYPTO_DEV_OMAP=y
-CONFIG_CRYPTO_DEV_OMAP_AES=y
-CONFIG_CRYPTO_DEV_OMAP_DES=y
-CONFIG_CRYPTO_DEV_OMAP_SHAM=y
-CONFIG_CRYPTO_DRBG=y
-CONFIG_CRYPTO_DRBG_HMAC=y
-CONFIG_CRYPTO_DRBG_MENU=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_ENGINE=y
-CONFIG_CRYPTO_GHASH_ARM_CE=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_JITTERENTROPY=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_DES=y
-CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_RNG_DEFAULT=y
-CONFIG_CRYPTO_SEQIV=y
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_SHA1_ARM=y
-CONFIG_CRYPTO_SHA1_ARM_NEON=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA256_ARM=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_SHA512_ARM=y
-CONFIG_CRYPTO_SIMD=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DDR=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-CONFIG_DM9000=y
-# CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set
-CONFIG_DMADEVICES=y
-CONFIG_DMA_CMA=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_OMAP=y
-CONFIG_DMA_OPS=y
-CONFIG_DMA_REMAP=y
-CONFIG_DMA_SHARED_BUFFER=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DNS_RESOLVER=y
-CONFIG_DRM=y
-CONFIG_DRM_BRIDGE=y
-CONFIG_DRM_DISPLAY_CONNECTOR=y
-CONFIG_DRM_KMS_HELPER=y
-CONFIG_DRM_MIPI_DSI=y
-CONFIG_DRM_OMAP=y
-CONFIG_DRM_PANEL=y
-CONFIG_DRM_PANEL_BRIDGE=y
-CONFIG_DRM_PANEL_LG_LB035Q02=y
-CONFIG_DRM_PANEL_NEC_NL8048HL11=y
-CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
-CONFIG_DRM_PANEL_SHARP_LS037V7DW01=y
-CONFIG_DRM_PANEL_SONY_ACX565AKM=y
-CONFIG_DRM_PANEL_TPO_TD028TTEC1=y
-CONFIG_DRM_PANEL_TPO_TD043MTEA1=y
-CONFIG_DRM_SIMPLE_BRIDGE=y
-CONFIG_DRM_TI_TFP410=y
-CONFIG_DRM_TI_TPD12S015=y
-CONFIG_DTC=y
-CONFIG_DT_IDLE_STATES=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EEPROM_93CX6=y
-CONFIG_EXT4_FS=y
-CONFIG_EXTCON=y
-CONFIG_EXTCON_PALMAS=y
-CONFIG_EXTCON_USB_GPIO=y
-CONFIG_F2FS_FS=y
-CONFIG_FANOTIFY=y
-CONFIG_FAT_FS=y
-CONFIG_FB_CMDLINE=y
-CONFIG_FHANDLE=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FS_POSIX_ACL=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GENERIC_VDSO_32=y
-CONFIG_GLOB=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_OMAP=y
-CONFIG_GPIO_PALMAS=y
-CONFIG_GPIO_PCA953X=y
-CONFIG_GPIO_PCA953X_IRQ=y
-CONFIG_GPIO_PCF857X=y
-# CONFIG_GPIO_TPS65218 is not set
-CONFIG_GPIO_TPS65910=y
-CONFIG_GPIO_TWL4030=y
-CONFIG_GPIO_TWL6040=y
-CONFIG_GRACE_PERIOD=y
-CONFIG_GRO_CELLS=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDEN_BRANCH_PREDICTOR=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HAVE_SMP=y
-CONFIG_HDMI=y
-CONFIG_HIGHMEM=y
-CONFIG_HIGHPTE=y
-CONFIG_HSI=y
-CONFIG_HSI_BOARDINFO=y
-# CONFIG_HSI_CHAR is not set
-CONFIG_HWMON=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_OMAP=y
-CONFIG_HZ_FIXED=0
-CONFIG_I2C=y
-CONFIG_I2C_ALGOBIT=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_OMAP=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_RARP=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_JBD2=y
-CONFIG_JFFS2_LZO=y
-CONFIG_JFFS2_RUBIN=y
-CONFIG_KALLSYMS=y
-CONFIG_KALLSYMS_ALL=y
-CONFIG_KCMP=y
-CONFIG_KEYS=y
-CONFIG_KMAP_LOCAL=y
-CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
-CONFIG_KPROBES=y
-CONFIG_KRETPROBES=y
-CONFIG_KS8851=y
-CONFIG_KS8851_MLL=y
-CONFIG_LCD_CLASS_DEVICE=y
-CONFIG_LCD_PLATFORM=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_PWM=y
-CONFIG_LEDS_TRIGGER_BACKLIGHT=y
-CONFIG_LEDS_TRIGGER_CPU=y
-CONFIG_LEDS_TRIGGER_GPIO=y
-CONFIG_LEDS_TRIGGER_ONESHOT=y
-CONFIG_LIBCRC32C=y
-CONFIG_LIBFDT=y
-CONFIG_LOCKD=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MACH_OMAP_GENERIC=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MDIO_BITBANG=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-# CONFIG_MDIO_GPIO is not set
-CONFIG_MEMFD_CREATE=y
-CONFIG_MEMORY=y
-CONFIG_MEMORY_ISOLATION=y
-CONFIG_MFD_CORE=y
-CONFIG_MFD_PALMAS=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MFD_TI_AM335X_TSCADC=y
-CONFIG_MFD_TPS65217=y
-CONFIG_MFD_TPS65218=y
-CONFIG_MFD_TPS65910=y
-CONFIG_MFD_TWL4030_AUDIO=y
-CONFIG_MICREL_PHY=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-# CONFIG_MMC_OMAP is not set
-CONFIG_MMC_OMAP_HS=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_EXTERNAL_DMA=y
-CONFIG_MMC_SDHCI_OMAP=y
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MSDOS_FS=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_NAND_CORE=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_ECC_SW_HAMMING=y
-CONFIG_MTD_NAND_OMAP2=y
-CONFIG_MTD_NAND_OMAP_BCH=y
-CONFIG_MTD_NAND_OMAP_BCH_BUILD=y
-CONFIG_MTD_ONENAND=y
-# CONFIG_MTD_ONENAND_2X_PROGRAM is not set
-# CONFIG_MTD_ONENAND_GENERIC is not set
-CONFIG_MTD_ONENAND_OMAP2=y
-# CONFIG_MTD_ONENAND_OTP is not set
-CONFIG_MTD_ONENAND_VERIFY_WRITE=y
-CONFIG_MTD_OOPS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-# CONFIG_MTD_UBI_BLOCK is not set
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-# CONFIG_MUSB_PIO_ONLY is not set
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEON=y
-CONFIG_NET_DEVLINK=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_KEY=y
-CONFIG_NET_KEY_MIGRATE=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NFS_ACL_SUPPORT=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_USE_KERNEL_DNS=y
-# CONFIG_NFS_USE_LEGACY_DNS is not set
-CONFIG_NFS_V3_ACL=y
-CONFIG_NFS_V4=y
-CONFIG_NLS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NOP_USB_XCEIV=y
-CONFIG_NO_HZ=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=4
-CONFIG_NVMEM=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OID_REGISTRY=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_OMAP2_DSS_DPI=y
-CONFIG_OMAP2_DSS_DSI=y
-CONFIG_OMAP2_DSS_HDMI_COMMON=y
-CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0
-CONFIG_OMAP2_DSS_SDI=y
-CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET=y
-CONFIG_OMAP2_DSS_VENC=y
-# CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE is not set
-# CONFIG_OMAP3_SDRC_AC_TIMING is not set
-CONFIG_OMAP3_THERMAL=y
-CONFIG_OMAP4_DSS_HDMI=y
-CONFIG_OMAP4_DSS_HDMI_CEC=y
-CONFIG_OMAP4_THERMAL=y
-CONFIG_OMAP5_DSS_HDMI=y
-CONFIG_OMAP_32K_TIMER=y
-CONFIG_OMAP_CONTROL_PHY=y
-CONFIG_OMAP_DM_TIMER=y
-CONFIG_OMAP_GPMC=y
-# CONFIG_OMAP_GPMC_DEBUG is not set
-CONFIG_OMAP_HWMOD=y
-CONFIG_OMAP_INTERCONNECT=y
-CONFIG_OMAP_INTERCONNECT_BARRIER=y
-CONFIG_OMAP_IRQCHIP=y
-CONFIG_OMAP_OCP2SCP=y
-CONFIG_OMAP_RESET_CLOCKS=y
-# CONFIG_OMAP_SSI is not set
-CONFIG_OMAP_USB2=y
-CONFIG_OMAP_WATCHDOG=y
-CONFIG_OPTPROBES=y
-CONFIG_OUTER_CACHE=y
-CONFIG_OUTER_CACHE_SYNC=y
-CONFIG_PADATA=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PAGE_POOL=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-# CONFIG_PHY_DM816X_USB is not set
-CONFIG_PHY_TI_GMII_SEL=y
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_PALMAS is not set
-CONFIG_PL310_ERRATA_588369=y
-CONFIG_PL310_ERRATA_727915=y
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_PM_GENERIC_DOMAINS=y
-CONFIG_PM_GENERIC_DOMAINS_OF=y
-CONFIG_PM_OPP=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_POSIX_MQUEUE_SYSCTL=y
-CONFIG_POWER_AVS_OMAP=y
-CONFIG_POWER_AVS_OMAP_CLASS3=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PPS=y
-CONFIG_PRINTK_TIME=y
-CONFIG_PRINT_QUOTA_WARNING=y
-CONFIG_PROC_EVENTS=y
-CONFIG_PROFILING=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PWM=y
-# CONFIG_PWM_OMAP_DMTIMER is not set
-CONFIG_PWM_SYSFS=y
-CONFIG_PWM_TIECAP=y
-CONFIG_PWM_TIEHRPWM=y
-# CONFIG_PWM_TWL is not set
-# CONFIG_PWM_TWL_LED is not set
-CONFIG_QFMT_V2=y
-CONFIG_QUOTA=y
-CONFIG_QUOTACTL=y
-CONFIG_QUOTA_TREE=y
-CONFIG_RATIONAL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_IRQ=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGMAP_SPI=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_PALMAS=y
-CONFIG_REGULATOR_PBIAS=y
-CONFIG_REGULATOR_TI_ABB=y
-CONFIG_REGULATOR_TPS62360=y
-CONFIG_REGULATOR_TPS65023=y
-CONFIG_REGULATOR_TPS6507X=y
-CONFIG_REGULATOR_TPS65217=y
-CONFIG_REGULATOR_TPS65218=y
-CONFIG_REGULATOR_TPS65910=y
-CONFIG_REGULATOR_TWL4030=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RFS_ACCEL=y
-CONFIG_ROOT_NFS=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_DS1307=y
-CONFIG_RTC_DRV_OMAP=y
-CONFIG_RTC_DRV_PALMAS=y
-# CONFIG_RTC_DRV_TPS65910 is not set
-CONFIG_RTC_DRV_TWL4030=y
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RTC_MC146818_LIB=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_SATA_AHCI_PLATFORM=y
-CONFIG_SATA_HOST=y
-CONFIG_SCHEDSTATS=y
-CONFIG_SCHED_INFO=y
-CONFIG_SCHED_MC=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-CONFIG_SCSI_SCAN_ASYNC=y
-CONFIG_SDIO_UART=y
-CONFIG_SECCOMP=y
-CONFIG_SECCOMP_FILTER=y
-CONFIG_SENSORS_GPIO_FAN=y
-CONFIG_SENSORS_LM75=y
-CONFIG_SENSORS_TMP102=y
-CONFIG_SENSORS_TSL2550=y
-CONFIG_SERIAL_8250_DETECT_IRQ=y
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_MANY_PORTS=y
-CONFIG_SERIAL_8250_NR_UARTS=32
-# CONFIG_SERIAL_8250_OMAP is not set
-CONFIG_SERIAL_8250_RSA=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SERIAL_OMAP=y
-CONFIG_SERIAL_OMAP_CONSOLE=y
-CONFIG_SERIO=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SG_POOL=y
-CONFIG_SG_SPLIT=y
-CONFIG_SKB_EXTENSIONS=y
-CONFIG_SMC91X=y
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-CONFIG_SMSC911X=y
-CONFIG_SMSC_PHY=y
-CONFIG_SND=y
-# CONFIG_SND_COMPRESS_OFFLOAD is not set
-CONFIG_SND_DMAENGINE_PCM=y
-CONFIG_SND_JACK=y
-CONFIG_SND_PCM=y
-CONFIG_SND_PCM_OSS=y
-CONFIG_SND_SIMPLE_CARD=y
-CONFIG_SND_SIMPLE_CARD_UTILS=y
-CONFIG_SND_SOC=y
-CONFIG_SND_SOC_DAVINCI_MCASP=y
-CONFIG_SND_SOC_DMIC=y
-CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
-CONFIG_SND_SOC_I2C_AND_SPI=y
-# CONFIG_SND_SOC_NOKIA_RX51 is not set
-# CONFIG_SND_SOC_OMAP3_PANDORA is not set
-CONFIG_SND_SOC_OMAP3_TWL4030=y
-CONFIG_SND_SOC_OMAP_ABE_TWL6040=y
-CONFIG_SND_SOC_OMAP_DMIC=y
-CONFIG_SND_SOC_OMAP_HDMI=y
-CONFIG_SND_SOC_OMAP_MCBSP=y
-CONFIG_SND_SOC_OMAP_MCPDM=y
-CONFIG_SND_SOC_TI_EDMA_PCM=y
-CONFIG_SND_SOC_TI_SDMA_PCM=y
-CONFIG_SND_SOC_TI_UDMA_PCM=y
-CONFIG_SND_SOC_TWL4030=y
-CONFIG_SND_SOC_TWL6040=y
-CONFIG_SND_VERBOSE_PRINTK=y
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SOC_AM33XX=y
-CONFIG_SOC_AM43XX=y
-CONFIG_SOC_BUS=y
-CONFIG_SOC_HAS_OMAP2_SDRC=y
-CONFIG_SOC_OMAP3430=y
-# CONFIG_SOC_TI81XX is not set
-CONFIG_SOUND=y
-CONFIG_SOUND_OSS_CORE=y
-CONFIG_SOUND_OSS_CORE_PRECLAIM=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_OMAP24XX=y
-CONFIG_SPI_TI_QSPI=y
-CONFIG_SRAM=y
-CONFIG_SRAM_EXEC=y
-CONFIG_SRCU=y
-CONFIG_STACKTRACE=y
-CONFIG_SUNRPC=y
-CONFIG_SUNRPC_GSS=y
-CONFIG_SWPHY=y
-CONFIG_SWP_EMULATE=y
-CONFIG_SYNC_FILE=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_GOV_FAIR_SHARE=y
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_GOV_USER_SPACE=y
-CONFIG_THERMAL_OF=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TI_CPPI41=y
-CONFIG_TI_CPSW=y
-CONFIG_TI_CPSW_SWITCHDEV=y
-CONFIG_TI_CPTS=y
-CONFIG_TI_DAVINCI_EMAC=y
-CONFIG_TI_DAVINCI_MDIO=y
-CONFIG_TI_DMA_CROSSBAR=y
-CONFIG_TI_EDMA=y
-CONFIG_TI_EMIF=y
-# CONFIG_TI_EMIF_SRAM is not set
-CONFIG_TI_PIPE3=y
-CONFIG_TI_PWMSS=y
-CONFIG_TI_SOC_THERMAL=y
-CONFIG_TI_SYSC=y
-CONFIG_TI_THERMAL=y
-CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_TWL4030_CORE=y
-CONFIG_TWL4030_POWER=y
-CONFIG_TWL4030_USB=y
-CONFIG_TWL4030_WATCHDOG=y
-# CONFIG_TWL6030_USB is not set
-CONFIG_TWL6040_CORE=y
-CONFIG_UBIFS_FS=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNWINDER_ARM=y
-CONFIG_USB=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_DUAL_ROLE=y
-# CONFIG_USB_DWC3_GADGET is not set
-# CONFIG_USB_DWC3_HOST is not set
-CONFIG_USB_DWC3_OMAP=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_HCD_OMAP=y
-# CONFIG_USB_EHCI_HCD_PLATFORM is not set
-CONFIG_USB_GADGET=y
-CONFIG_USB_INVENTRA_DMA=y
-CONFIG_USB_MUSB_AM35X=y
-CONFIG_USB_MUSB_DSPS=y
-CONFIG_USB_MUSB_DUAL_ROLE=y
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_USB_MUSB_OMAP2PLUS=y
-CONFIG_USB_MUSB_TUSB6010=y
-CONFIG_USB_PHY=y
-CONFIG_USB_ROLE_SWITCH=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_TI_CPPI41_DMA=y
-CONFIG_USB_TUSB_OMAP_DMA=y
-CONFIG_USE_OF=y
-CONFIG_VFAT_FS=y
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_VIDEOMODE_HELPERS=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_XFRM_ALGO=y
-CONFIG_XFRM_MIGRATE=y
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
diff --git a/target/linux/omap/config-6.1 b/target/linux/omap/config-6.1
new file mode 100644
index 00000000000000..d5ed19afe15af2
--- /dev/null
+++ b/target/linux/omap/config-6.1
@@ -0,0 +1,711 @@
+# CONFIG_AHCI_DM816 is not set
+CONFIG_ALIGNMENT_TRAP=y
+CONFIG_AM335X_CONTROL_USB=y
+CONFIG_AM335X_PHY_USB=y
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MULTIPLATFORM=y
+CONFIG_ARCH_MULTI_V6_V7=y
+CONFIG_ARCH_MULTI_V7=y
+CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED=y
+CONFIG_ARCH_NR_GPIO=0
+CONFIG_ARCH_OMAP=y
+CONFIG_ARCH_OMAP2PLUS=y
+CONFIG_ARCH_OMAP2PLUS_TYPICAL=y
+CONFIG_ARCH_OMAP3=y
+CONFIG_ARCH_OMAP4=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARM=y
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
+CONFIG_ARM_CPUIDLE=y
+CONFIG_ARM_CPU_SUSPEND=y
+CONFIG_ARM_ERRATA_430973=y
+CONFIG_ARM_ERRATA_720789=y
+CONFIG_ARM_ERRATA_754322=y
+CONFIG_ARM_ERRATA_775420=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_HAS_GROUP_RELOCS=y
+CONFIG_ARM_HEAVY_MB=y
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+CONFIG_ARM_OMAP2PLUS_CPUFREQ=y
+CONFIG_ARM_PATCH_IDIV=y
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_THUMBEE=y
+CONFIG_ARM_TI_CPUFREQ=y
+CONFIG_ARM_UNWIND=y
+CONFIG_ARM_VIRT_EXT=y
+CONFIG_ASSOCIATIVE_ARRAY=y
+CONFIG_AT803X_PHY=y
+CONFIG_ATA=y
+CONFIG_AUDIT=y
+CONFIG_AUDITSYSCALL=y
+CONFIG_AUDIT_GENERIC=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_TPS65217 is not set
+CONFIG_BCH=y
+CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_PM=y
+CONFIG_BOUNCE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_CACHE_L2X0=y
+CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CEC_CORE=y
+# CONFIG_CHARGER_TPS65217 is not set
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLKSRC_TI_32K=y
+CONFIG_CLK_TWL6040=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMA=y
+CONFIG_CMA_ALIGNMENT=8
+CONFIG_CMA_AREAS=7
+# CONFIG_CMA_DEBUG is not set
+# CONFIG_CMA_DEBUGFS is not set
+CONFIG_CMA_SIZE_MBYTES=16
+# CONFIG_CMA_SIZE_SEL_MAX is not set
+CONFIG_CMA_SIZE_SEL_MBYTES=y
+# CONFIG_CMA_SIZE_SEL_MIN is not set
+# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
+# CONFIG_CMA_SYSFS is not set
+CONFIG_CMDLINE="root=/dev/mmcblk0p2 rootwait console=ttyO2,115200"
+CONFIG_CMDLINE_FROM_BOOTLOADER=y
+CONFIG_COMMON_CLK=y
+# CONFIG_COMMON_CLK_PALMAS is not set
+# CONFIG_COMMON_CLK_TI_ADPLL is not set
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_CONNECTOR=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CONTIG_ALLOC=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_CPUFREQ_DT_PLATDEV=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_SPECTRE=y
+CONFIG_CPU_THERMAL=y
+CONFIG_CPU_THUMB_CAPABLE=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_V7=y
+CONFIG_CRAMFS=y
+CONFIG_CRC16=y
+CONFIG_CRC7=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRYPTO_AES_ARM=y
+CONFIG_CRYPTO_AES_ARM_BS=y
+CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CHACHA20_NEON=y
+CONFIG_CRYPTO_CRC32=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_CRCT10DIF=y
+CONFIG_CRYPTO_CRYPTD=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_DEV_OMAP=y
+CONFIG_CRYPTO_DEV_OMAP_AES=y
+CONFIG_CRYPTO_DEV_OMAP_DES=y
+CONFIG_CRYPTO_DEV_OMAP_SHAM=y
+CONFIG_CRYPTO_DRBG=y
+CONFIG_CRYPTO_DRBG_HMAC=y
+CONFIG_CRYPTO_DRBG_MENU=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_ENGINE=y
+CONFIG_CRYPTO_GHASH_ARM_CE=y
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_DES=y
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_SHA256=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RNG_DEFAULT=y
+CONFIG_CRYPTO_SEQIV=y
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA1_ARM=y
+CONFIG_CRYPTO_SHA1_ARM_NEON=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA256_ARM=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_SHA512_ARM=y
+CONFIG_CRYPTO_SIMD=y
+CONFIG_CRYPTO_ZSTD=y
+CONFIG_CURRENT_POINTER_IN_TPIDRURO=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DDR=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+CONFIG_DMADEVICES=y
+CONFIG_DMA_CMA=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_OMAP=y
+CONFIG_DMA_OPS=y
+CONFIG_DMA_SHARED_BUFFER=y
+CONFIG_DMA_VIRTUAL_CHANNELS=y
+CONFIG_DNS_RESOLVER=y
+CONFIG_DRM=y
+CONFIG_DRM_BRIDGE=y
+CONFIG_DRM_DISPLAY_CONNECTOR=y
+CONFIG_DRM_KMS_HELPER=y
+CONFIG_DRM_MIPI_DSI=y
+CONFIG_DRM_NOMODESET=y
+CONFIG_DRM_OMAP=y
+CONFIG_DRM_PANEL=y
+CONFIG_DRM_PANEL_BRIDGE=y
+CONFIG_DRM_PANEL_LG_LB035Q02=y
+CONFIG_DRM_PANEL_NEC_NL8048HL11=y
+CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
+CONFIG_DRM_PANEL_SHARP_LS037V7DW01=y
+CONFIG_DRM_PANEL_SONY_ACX565AKM=y
+CONFIG_DRM_PANEL_TPO_TD028TTEC1=y
+CONFIG_DRM_PANEL_TPO_TD043MTEA1=y
+CONFIG_DRM_SIMPLE_BRIDGE=y
+CONFIG_DRM_TI_TFP410=y
+CONFIG_DRM_TI_TPD12S015=y
+CONFIG_DTC=y
+CONFIG_DT_IDLE_STATES=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EEPROM_93CX6=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_EXT4_FS=y
+CONFIG_EXTCON=y
+CONFIG_EXTCON_PALMAS=y
+CONFIG_EXTCON_USB_GPIO=y
+CONFIG_F2FS_FS=y
+CONFIG_FANOTIFY=y
+CONFIG_FAT_FS=y
+CONFIG_FB_CMDLINE=y
+CONFIG_FHANDLE=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC11_NO_ARRAY_BOUNDS=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_VDSO_32=y
+CONFIG_GLOB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_OMAP=y
+CONFIG_GPIO_PALMAS=y
+CONFIG_GPIO_PCA953X=y
+CONFIG_GPIO_PCA953X_IRQ=y
+CONFIG_GPIO_PCF857X=y
+# CONFIG_GPIO_TPS65218 is not set
+CONFIG_GPIO_TPS65910=y
+CONFIG_GPIO_TWL4030=y
+CONFIG_GPIO_TWL6040=y
+CONFIG_GRACE_PERIOD=y
+CONFIG_GRO_CELLS=y
+CONFIG_HARDEN_BRANCH_PREDICTOR=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HAVE_SMP=y
+CONFIG_HDMI=y
+CONFIG_HIGHMEM=y
+CONFIG_HIGHPTE=y
+CONFIG_HSI=y
+CONFIG_HSI_BOARDINFO=y
+# CONFIG_HSI_CHAR is not set
+CONFIG_HWMON=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_OMAP=y
+CONFIG_HZ_FIXED=0
+CONFIG_I2C=y
+CONFIG_I2C_ALGOBIT=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_OMAP=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_RARP=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQSTACKS=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+CONFIG_JBD2=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_RUBIN=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_KCMP=y
+CONFIG_KEYS=y
+CONFIG_KMAP_LOCAL=y
+CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
+CONFIG_KPROBES=y
+CONFIG_KRETPROBES=y
+CONFIG_KS8851=y
+CONFIG_KS8851_MLL=y
+CONFIG_LCD_CLASS_DEVICE=y
+CONFIG_LCD_PLATFORM=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_PWM=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LEDS_TRIGGER_ONESHOT=y
+CONFIG_LIBCRC32C=y
+CONFIG_LIBFDT=y
+CONFIG_LOCKD=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MACH_OMAP_GENERIC=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MDIO_BITBANG=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+# CONFIG_MDIO_GPIO is not set
+CONFIG_MEMFD_CREATE=y
+CONFIG_MEMORY=y
+CONFIG_MEMORY_ISOLATION=y
+CONFIG_MFD_CORE=y
+CONFIG_MFD_PALMAS=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MFD_TI_AM335X_TSCADC=y
+CONFIG_MFD_TPS65217=y
+CONFIG_MFD_TPS65218=y
+CONFIG_MFD_TPS65910=y
+CONFIG_MFD_TWL4030_AUDIO=y
+CONFIG_MICREL_PHY=y
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
+CONFIG_MIGRATION=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+# CONFIG_MMC_OMAP is not set
+CONFIG_MMC_OMAP_HS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_EXTERNAL_DMA=y
+CONFIG_MMC_SDHCI_OMAP=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MSDOS_FS=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+CONFIG_MTD_NAND_OMAP2=y
+CONFIG_MTD_NAND_OMAP_BCH=y
+CONFIG_MTD_NAND_OMAP_BCH_BUILD=y
+CONFIG_MTD_ONENAND=y
+# CONFIG_MTD_ONENAND_2X_PROGRAM is not set
+# CONFIG_MTD_ONENAND_GENERIC is not set
+CONFIG_MTD_ONENAND_OMAP2=y
+# CONFIG_MTD_ONENAND_OTP is not set
+CONFIG_MTD_ONENAND_VERIFY_WRITE=y
+CONFIG_MTD_OOPS=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+# CONFIG_MTD_UBI_BLOCK is not set
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+# CONFIG_MUSB_PIO_ONLY is not set
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEON=y
+CONFIG_NET_DEVLINK=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_KEY=y
+CONFIG_NET_KEY_MIGRATE=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_SWITCHDEV=y
+CONFIG_NFS_ACL_SUPPORT=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_USE_KERNEL_DNS=y
+# CONFIG_NFS_USE_LEGACY_DNS is not set
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_NLS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_NO_HZ=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NR_CPUS=4
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OID_REGISTRY=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_OMAP2_DSS_DPI=y
+CONFIG_OMAP2_DSS_DSI=y
+CONFIG_OMAP2_DSS_HDMI_COMMON=y
+CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0
+CONFIG_OMAP2_DSS_SDI=y
+CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET=y
+CONFIG_OMAP2_DSS_VENC=y
+# CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE is not set
+# CONFIG_OMAP3_SDRC_AC_TIMING is not set
+CONFIG_OMAP3_THERMAL=y
+CONFIG_OMAP4_DSS_HDMI=y
+CONFIG_OMAP4_DSS_HDMI_CEC=y
+CONFIG_OMAP4_THERMAL=y
+CONFIG_OMAP5_DSS_HDMI=y
+CONFIG_OMAP_CONTROL_PHY=y
+CONFIG_OMAP_DM_SYSTIMER=y
+CONFIG_OMAP_DM_TIMER=y
+CONFIG_OMAP_GPMC=y
+# CONFIG_OMAP_GPMC_DEBUG is not set
+CONFIG_OMAP_HWMOD=y
+CONFIG_OMAP_INTERCONNECT=y
+CONFIG_OMAP_INTERCONNECT_BARRIER=y
+CONFIG_OMAP_IRQCHIP=y
+CONFIG_OMAP_OCP2SCP=y
+# CONFIG_OMAP_SSI is not set
+CONFIG_OMAP_USB2=y
+CONFIG_OMAP_WATCHDOG=y
+CONFIG_OPTPROBES=y
+CONFIG_OUTER_CACHE=y
+CONFIG_OUTER_CACHE_SYNC=y
+CONFIG_PADATA=y
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+# CONFIG_PHY_DM816X_USB is not set
+CONFIG_PHY_TI_GMII_SEL=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_PALMAS is not set
+CONFIG_PL310_ERRATA_588369=y
+CONFIG_PL310_ERRATA_727915=y
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+CONFIG_PM_GENERIC_DOMAINS=y
+CONFIG_PM_GENERIC_DOMAINS_OF=y
+CONFIG_PM_OPP=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+CONFIG_POWER_AVS_OMAP=y
+CONFIG_POWER_AVS_OMAP_CLASS3=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PPS=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PRINTK_TIME=y
+CONFIG_PRINT_QUOTA_WARNING=y
+CONFIG_PROC_EVENTS=y
+CONFIG_PROFILING=y
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_PWM=y
+# CONFIG_PWM_OMAP_DMTIMER is not set
+CONFIG_PWM_SYSFS=y
+CONFIG_PWM_TIECAP=y
+CONFIG_PWM_TIEHRPWM=y
+# CONFIG_PWM_TWL is not set
+# CONFIG_PWM_TWL_LED is not set
+CONFIG_QCOM_NET_PHYLIB=y
+CONFIG_QFMT_V2=y
+CONFIG_QUOTA=y
+CONFIG_QUOTACTL=y
+CONFIG_QUOTA_TREE=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RATIONAL=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_IRQ=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGMAP_SPI=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_PALMAS=y
+CONFIG_REGULATOR_PBIAS=y
+CONFIG_REGULATOR_TI_ABB=y
+CONFIG_REGULATOR_TPS62360=y
+CONFIG_REGULATOR_TPS65023=y
+CONFIG_REGULATOR_TPS6507X=y
+CONFIG_REGULATOR_TPS65217=y
+CONFIG_REGULATOR_TPS65218=y
+CONFIG_REGULATOR_TPS65910=y
+CONFIG_REGULATOR_TWL4030=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RFS_ACCEL=y
+CONFIG_ROOT_NFS=y
+CONFIG_RPS=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_DS1307=y
+CONFIG_RTC_DRV_OMAP=y
+CONFIG_RTC_DRV_PALMAS=y
+# CONFIG_RTC_DRV_TPS65910 is not set
+CONFIG_RTC_DRV_TWL4030=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RTC_MC146818_LIB=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_SATA_HOST=y
+CONFIG_SCHEDSTATS=y
+CONFIG_SCHED_INFO=y
+CONFIG_SCHED_MC=y
+CONFIG_SCSI=y
+CONFIG_SCSI_COMMON=y
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SDIO_UART=y
+CONFIG_SECCOMP=y
+CONFIG_SECCOMP_FILTER=y
+CONFIG_SENSORS_GPIO_FAN=y
+CONFIG_SENSORS_LM75=y
+CONFIG_SENSORS_TMP102=y
+CONFIG_SENSORS_TSL2550=y
+CONFIG_SERIAL_8250_DETECT_IRQ=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_NR_UARTS=32
+# CONFIG_SERIAL_8250_OMAP is not set
+CONFIG_SERIAL_8250_RSA=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_OMAP=y
+CONFIG_SERIAL_OMAP_CONSOLE=y
+CONFIG_SERIO=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SG_POOL=y
+CONFIG_SG_SPLIT=y
+CONFIG_SKB_EXTENSIONS=y
+CONFIG_SMC91X=y
+CONFIG_SMP=y
+CONFIG_SMP_ON_UP=y
+CONFIG_SMSC911X=y
+CONFIG_SMSC_PHY=y
+CONFIG_SND=y
+# CONFIG_SND_COMPRESS_OFFLOAD is not set
+CONFIG_SND_DMAENGINE_PCM=y
+CONFIG_SND_JACK=y
+CONFIG_SND_PCM=y
+CONFIG_SND_PCM_OSS=y
+CONFIG_SND_SIMPLE_CARD=y
+CONFIG_SND_SIMPLE_CARD_UTILS=y
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_DAVINCI_MCASP=y
+CONFIG_SND_SOC_DMIC=y
+CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+# CONFIG_SND_SOC_NOKIA_RX51 is not set
+# CONFIG_SND_SOC_OMAP3_PANDORA is not set
+CONFIG_SND_SOC_OMAP3_TWL4030=y
+CONFIG_SND_SOC_OMAP_ABE_TWL6040=y
+CONFIG_SND_SOC_OMAP_DMIC=y
+CONFIG_SND_SOC_OMAP_HDMI=y
+CONFIG_SND_SOC_OMAP_MCBSP=y
+CONFIG_SND_SOC_OMAP_MCPDM=y
+CONFIG_SND_SOC_TI_EDMA_PCM=y
+CONFIG_SND_SOC_TI_SDMA_PCM=y
+CONFIG_SND_SOC_TI_UDMA_PCM=y
+CONFIG_SND_SOC_TWL4030=y
+CONFIG_SND_SOC_TWL6040=y
+CONFIG_SND_VERBOSE_PRINTK=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SOC_AM33XX=y
+CONFIG_SOC_AM43XX=y
+CONFIG_SOC_BUS=y
+CONFIG_SOC_HAS_OMAP2_SDRC=y
+CONFIG_SOC_OMAP3430=y
+# CONFIG_SOC_TI81XX is not set
+CONFIG_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SPI_OMAP24XX=y
+CONFIG_SPI_TI_QSPI=y
+CONFIG_SRAM=y
+CONFIG_SRAM_EXEC=y
+CONFIG_SRCU=y
+CONFIG_STACKTRACE=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_SWPHY=y
+CONFIG_SWP_EMULATE=y
+CONFIG_SYNC_FILE=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_GOV_FAIR_SHARE=y
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_GOV_USER_SPACE=y
+CONFIG_THERMAL_OF=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TI_CPPI41=y
+CONFIG_TI_CPSW=y
+CONFIG_TI_CPSW_SWITCHDEV=y
+CONFIG_TI_CPTS=y
+CONFIG_TI_DAVINCI_EMAC=y
+CONFIG_TI_DAVINCI_MDIO=y
+CONFIG_TI_DMA_CROSSBAR=y
+CONFIG_TI_EDMA=y
+CONFIG_TI_EMIF=y
+# CONFIG_TI_EMIF_SRAM is not set
+CONFIG_TI_PIPE3=y
+CONFIG_TI_PWMSS=y
+CONFIG_TI_SOC_THERMAL=y
+CONFIG_TI_SYSC=y
+CONFIG_TI_THERMAL=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_TWL4030_CORE=y
+CONFIG_TWL4030_POWER=y
+CONFIG_TWL4030_USB=y
+CONFIG_TWL4030_WATCHDOG=y
+# CONFIG_TWL6030_USB is not set
+CONFIG_TWL6040_CORE=y
+CONFIG_UBIFS_FS=y
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_UNWINDER_ARM=y
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_DUAL_ROLE=y
+# CONFIG_USB_DWC3_GADGET is not set
+# CONFIG_USB_DWC3_HOST is not set
+CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_OMAP=y
+# CONFIG_USB_EHCI_HCD_PLATFORM is not set
+CONFIG_USB_GADGET=y
+CONFIG_USB_INVENTRA_DMA=y
+CONFIG_USB_MUSB_AM35X=y
+CONFIG_USB_MUSB_DSPS=y
+CONFIG_USB_MUSB_DUAL_ROLE=y
+CONFIG_USB_MUSB_HDRC=y
+CONFIG_USB_MUSB_OMAP2PLUS=y
+CONFIG_USB_MUSB_TUSB6010=y
+CONFIG_USB_PHY=y
+CONFIG_USB_ROLE_SWITCH=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_TI_CPPI41_DMA=y
+CONFIG_USB_TUSB_OMAP_DMA=y
+CONFIG_USE_OF=y
+CONFIG_VFAT_FS=y
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_VIDEOMODE_HELPERS=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_XFRM_ALGO=y
+CONFIG_XFRM_MIGRATE=y
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZSTD_COMMON=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y
diff --git a/target/linux/qualcommax/Makefile b/target/linux/qualcommax/Makefile
index a9d4c06b77aea1..1ce391ad22a4b8 100644
--- a/target/linux/qualcommax/Makefile
+++ b/target/linux/qualcommax/Makefile
@@ -6,7 +6,7 @@ BOARDNAME:=Qualcomm Atheros 802.11ax WiSoC-s
 FEATURES:=squashfs ramdisk fpu nand rtc emmc
 KERNELNAME:=Image dtbs
 CPU_TYPE:=cortex-a53
-SUBTARGETS:=ipq807x
+SUBTARGETS:=ipq807x ipq60xx
 
 KERNEL_PATCHVER:=6.1
 
diff --git a/target/linux/qualcommax/config-6.1 b/target/linux/qualcommax/config-6.1
index ad08d05f70cd45..acfdc99b22e8f1 100644
--- a/target/linux/qualcommax/config-6.1
+++ b/target/linux/qualcommax/config-6.1
@@ -127,6 +127,7 @@ CONFIG_CRYPTO_SHA256=y
 CONFIG_CRYPTO_XTS=y
 CONFIG_CRYPTO_ZSTD=y
 CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_BUGVERBOSE=y
 CONFIG_DEBUG_INFO=y
 CONFIG_DEV_COREDUMP=y
 CONFIG_DMADEVICES=y
@@ -146,6 +147,7 @@ CONFIG_FWNODE_MDIO=y
 CONFIG_FW_LOADER_PAGED_BUF=y
 CONFIG_FW_LOADER_SYSFS=y
 CONFIG_GCC11_NO_ARRAY_BOUNDS=y
+CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y
 CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS=y
 CONFIG_GENERIC_ALLOCATOR=y
 CONFIG_GENERIC_ARCH_TOPOLOGY=y
@@ -274,6 +276,7 @@ CONFIG_NO_HZ_IDLE=y
 CONFIG_NR_CPUS=4
 CONFIG_NVIDIA_CARMEL_CNP_ERRATUM=y
 CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
 CONFIG_NVMEM_QCOM_QFPROM=y
 # CONFIG_NVMEM_QCOM_SEC_QFPROM is not set
 CONFIG_NVMEM_SYSFS=y
@@ -290,6 +293,7 @@ CONFIG_PADATA=y
 CONFIG_PAGE_POOL=y
 CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
 CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
 CONFIG_PARTITION_PERCPU=y
 CONFIG_PCI=y
 CONFIG_PCIEAER=y
@@ -309,6 +313,7 @@ CONFIG_PCI_MSI=y
 CONFIG_PCI_MSI_IRQ_DOMAIN=y
 CONFIG_PGTABLE_LEVELS=3
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
 CONFIG_PHYS_ADDR_T_64BIT=y
 # CONFIG_PHY_QCOM_APQ8064_SATA is not set
 # CONFIG_PHY_QCOM_EDP is not set
@@ -352,6 +357,8 @@ CONFIG_POWER_SUPPLY=y
 CONFIG_PREEMPT_NONE_BUILD=y
 CONFIG_PRINTK_TIME=y
 CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_QCA807X_PHY=y
+CONFIG_QCA808X_PHY=y
 # CONFIG_QCM_DISPCC_2290 is not set
 # CONFIG_QCM_GCC_2290 is not set
 # CONFIG_QCOM_A53PLL is not set
@@ -375,6 +382,7 @@ CONFIG_QCOM_BAM_DMA=y
 # CONFIG_QCOM_LLCC is not set
 CONFIG_QCOM_MDT_LOADER=y
 # CONFIG_QCOM_MPM is not set
+CONFIG_QCOM_NET_PHYLIB=y
 # CONFIG_QCOM_OCMEM is not set
 # CONFIG_QCOM_PDC is not set
 CONFIG_QCOM_PIL_INFO=y
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6010-mango-dvk.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6010-mango-dvk.dts
new file mode 100644
index 00000000000000..27247524a3e870
--- /dev/null
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6010-mango-dvk.dts
@@ -0,0 +1,360 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+/dts-v1/;
+
+#include "ipq6018.dtsi"
+#include "ipq6018-cp-cpu.dtsi"
+#include "ipq6018-ess.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+	model = "8devices Mango-DVK";
+	compatible = "8devices,mango-dvk", "qcom,ipq6018";
+
+	aliases {
+		serial0 = &blsp1_uart3;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	keys {
+		compatible = "gpio-keys";
+
+		wps {
+			label = "wps";
+			gpios = <&tlmm 79 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WPS_BUTTON>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-0 = <&led_pins>;
+		pinctrl-names = "default";
+
+		wlan5g {
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_WLAN;
+			function-enumerator = <0>;
+			gpios = <&tlmm 66 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "phy0radio";
+		};
+
+		wlan2g {
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_WLAN;
+			function-enumerator = <1>;
+			gpios = <&tlmm 67 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "phy1radio";
+		};
+	};
+};
+
+&tlmm {
+	mdio_pins: mdio-pins {
+		mdc {
+			pins = "gpio64";
+			function = "mdc";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+
+		mdio {
+			pins = "gpio65";
+			function = "mdio";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+	};
+
+	spi_0_pins: spi-0-pins {
+		pins = "gpio38", "gpio39", "gpio40", "gpio41";
+		function = "blsp0_spi";
+		drive-strength = <8>;
+		bias-pull-down;
+	};
+
+	led_pins: led_pins {
+		leds {
+			pins = "gpio66", "gpio67";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+	};
+
+	sd_pins: sd_pins {
+		sd_cd {
+			 pins = "gpio62";
+			 function = "gpio";
+			 drive-strength = <8>;
+			 bias-pull-up;
+		};
+	};
+};
+
+&blsp1_uart3 {
+	pinctrl-0 = <&serial_3_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&blsp1_spi1 {
+	pinctrl-0 = <&spi_0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		compatible = "jedec,spi-nor";
+		spi-max-frequency = <25000000>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "0:SBL1";
+				reg = <0x00000000 0x000c0000>;
+			};
+
+			partition@c0000 {
+				label = "0:MIBIB";
+				reg = <0x000c0000 0x00010000>;
+			};
+
+			partition@d0000 {
+				label = "0:QSEE";
+				reg = <0x000d0000 0x001a0000>;
+			};
+
+			partition@270000 {
+				label = "0:DEVCFG";
+				reg = <0x00270000 0x00010000>;
+			};
+
+			partition@280000 {
+				label = "0:RPM";
+				reg = <0x00280000 0x00020000>;
+			};
+
+			partition@2a0000 {
+				label = "0:CDT";
+				reg = <0x002a0000 0x00010000>;
+			};
+
+			partition@2b0000 {
+				label = "0:APPSBLENV";
+				reg = <0x002b0000 0x00010000>;
+			};
+
+			partition@2c0000 {
+				label = "0:APPSBL";
+				reg = <0x002c0000 0x000a0000>;
+			};
+
+			partition@360000 {
+				compatible = "nvmem-cells";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				label = "0:ART";
+				reg = <0x00360000 0x00040000>;
+
+				macaddr_eth0: macaddr@0 {
+					reg = <0x0 0x6>;
+				};
+
+				macaddr_eth1: macaddr@6 {
+					reg = <0x6 0x6>;
+				};
+
+				macaddr_eth2: macaddr@c {
+					reg = <0xc 0x6>;
+				};
+			};
+
+			partition@3a0000 {
+				label = "config";
+				reg = <0x003a0000 0x00040000>;
+			};
+
+			partition@3e0000 {
+				label = "data";
+				reg = <0x003e0000 0x00100000>;
+			};
+
+			partition@4e0000 {
+				label = "firmware";
+				compatible = "denx,fit";
+				reg = <0x004e0000 0x1b20000>;
+			};
+		};
+	};
+};
+
+&dp3 {
+	status = "okay";
+
+	phy-handle = <&qca8072_1>;
+	nvmem-cells = <&macaddr_eth1>;
+	nvmem-cell-names = "mac-address";
+	label = "lan2";
+};
+
+&dp4 {
+	status = "okay";
+
+	phy-handle = <&qca8072_0>;
+	nvmem-cells = <&macaddr_eth0>;
+	nvmem-cell-names = "mac-address";
+	label = "lan1";
+};
+
+&dp5 {
+	status = "okay";
+
+	phy-handle = <&qca8081>;
+	nvmem-cells = <&macaddr_eth2>;
+	nvmem-cell-names = "mac-address";
+	label = "wan";
+};
+
+&edma {
+	status = "okay";
+};
+
+&mdio {
+	status = "okay";
+	pinctrl-0 = <&mdio_pins>;
+	pinctrl-names = "default";
+	reset-gpios = <&tlmm 75 GPIO_ACTIVE_LOW>;
+	reset-delay-us = <10000>;
+	reset-post-delay-us = <50000>;
+
+	ethernet-phy-package@0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "qcom,qca8075-package";
+		reg = <0>;
+
+		qcom,package-mode = "psgmii";
+
+		qca8072_0: ethernet-phy@3 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <3>;
+		};
+
+		qca8072_1: ethernet-phy@4 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <4>;
+		};
+	};
+
+	qca8081: ethernet-phy@24 {
+		compatible = "ethernet-phy-id004d.d101";
+		reg = <24>;
+		reset-gpios = <&tlmm 77 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&sdhc_1 {
+	pinctrl-0 = <&sd_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	vqmmc-supply = <&ipq6018_l2>;
+	cd-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>;
+};
+
+&switch {
+	status = "okay";
+
+	switch_lan_bmp = <(ESS_PORT3 | ESS_PORT4)>;
+	switch_wan_bmp = <ESS_PORT5>;
+	switch_mac_mode = <MAC_MODE_PSGMII>;
+	switch_mac_mode1 = <MAC_MODE_SGMII_PLUS>;
+	port3_pcs_channel = <4>;
+
+	qcom,port_phyinfo {
+		port@3 {
+			port_id = <3>;
+			phy_address = <4>;
+		};
+		port@4 {
+			port_id = <4>;
+			phy_address = <3>;
+		};
+		port@5 {
+			port_id = <5>;
+			phy_address = <24>;
+			port_mac_sel = "QGMAC_PORT";
+		};
+	};
+};
+
+&qpic_bam {
+	status = "okay";
+};
+
+&qpic_nand {
+	status = "okay";
+
+	nand@0 {
+		reg = <0>;
+
+		nand-ecc-strength = <4>;
+		nand-ecc-step-size = <512>;
+		nand-bus-width = <8>;
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "nand_data";
+				reg = <0x0000000 0x10000000>;
+			};
+		};
+	};
+};
+
+&pcie_phy {
+	status = "okay";
+};
+
+&pcie0 {
+	status = "okay";
+	perst-gpio = <&tlmm 60 GPIO_ACTIVE_LOW>;
+};
+
+&wifi {
+	status = "okay";
+	qcom,ath11k-calibration-variant = "8devices-Mango";
+};
+
+&qusb_phy_1 {
+	status = "okay";
+};
+
+&usb2 {
+	status = "okay";
+};
+
+&qusb_phy_0 {
+	status = "okay";
+};
+
+&ssphy_0 {
+	status = "okay";
+};
+
+&usb3 {
+	status = "okay";
+};
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6018-cp-cpu.dtsi b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6018-cp-cpu.dtsi
new file mode 100644
index 00000000000000..2dee366e1eaa5f
--- /dev/null
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6018-cp-cpu.dtsi
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include "ipq6018-cpr-regulator.dtsi"
+
+&CPU0 {
+	cpu-supply = <&apc_vreg>;
+};
+
+&CPU1 {
+	cpu-supply = <&apc_vreg>;
+};
+
+&CPU2 {
+	cpu-supply = <&apc_vreg>;
+};
+
+&CPU3 {
+	cpu-supply = <&apc_vreg>;
+};
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6018-cpr-regulator.dtsi b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6018-cpr-regulator.dtsi
new file mode 100644
index 00000000000000..738123296f02f2
--- /dev/null
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6018-cpr-regulator.dtsi
@@ -0,0 +1,124 @@
+/*
+ * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+&soc {
+	apc_apm: apm@b111000 {
+		compatible = "qcom,ipq807x-apm";
+		reg = <0x0 0xb111000 0x0 0x1000>;
+		reg-names = "pm-apcc-glb";
+		qcom,apm-post-halt-delay = <0x2>;
+		qcom,apm-halt-clk-delay = <0x11>;
+		qcom,apm-resume-clk-delay = <0x10>;
+		qcom,apm-sel-switch-delay = <0x01>;
+	};
+
+	apc_cpr: cpr4-ctrl@b018000 {
+		compatible = "qcom,cpr4-ipq6018-apss-regulator";
+		reg = <0x0 0xb018000 0x0 0x4000>, <0x0 0xa4000 0x0 0x1000>, <0x0 0x0193d008 0x0 0x4>;
+		reg-names = "cpr_ctrl", "fuse_base", "cpr_tcsr_reg";
+		interrupts = <GIC_SPI 15 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "cpr";
+		qcom,cpr-ctrl-name = "apc";
+		qcom,cpr-sensor-time = <1000>;
+		qcom,cpr-loop-time = <5000000>;
+		qcom,cpr-idle-cycles = <15>;
+		qcom,cpr-step-quot-init-min = <0>;
+		qcom,cpr-step-quot-init-max = <15>;
+		qcom,cpr-count-mode = <0>;		/* All-at-once */
+		qcom,cpr-count-repeat = <1>;
+		qcom,cpr-down-error-step-limit = <1>;
+		qcom,cpr-up-error-step-limit = <1>;
+		qcom,apm-ctrl = <&apc_apm>;
+		qcom,apm-threshold-voltage = <850000>;
+		vdd-supply = <&ipq6018_s2>;
+		qcom,voltage-step = <12500>;
+
+		thread@0 {
+			qcom,cpr-thread-id = <0>;
+			qcom,cpr-consecutive-up = <2>;
+			qcom,cpr-consecutive-down = <2>;
+			qcom,cpr-up-threshold = <2>;
+			qcom,cpr-down-threshold = <2>;
+
+			apc_vreg: regulator {
+				regulator-name = "apc_corner";
+				regulator-min-microvolt = <1>;
+				regulator-max-microvolt = <6>;
+				qcom,cpr-fuse-corners = <4>;
+				qcom,cpr-fuse-combos = <8>;
+				qcom,cpr-corners = <6>;
+				qcom,cpr-speed-bins = <1>;
+				qcom,cpr-speed-bin-corners = <6>;
+				qcom,cpr-corner-fmax-map = <1 3 5 6>;
+				qcom,allow-voltage-interpolation;
+				qcom,allow-quotient-interpolation;
+				qcom,cpr-voltage-ceiling =
+					<725000 787500 862500
+					 925000 987500 1062500>;
+				qcom,cpr-voltage-floor =
+					<587500 650000 712500
+					 750000 787500 850000>;
+				qcom,corner-frequencies =
+					<864000000 1056000000 1320000000
+					1440000000 1608000000 1800000000>;
+				qcom,cpr-ro-sel =
+					/* Speed bin 0; CPR rev 0..7 */
+					<     0      0      0     0>,
+					<     7      7      7     7>,
+					<     0      0      0     0>,
+					<     0      0      0     0>,
+					<     0      0      0     0>,
+					<     0      0      0     0>,
+					<     0      0      0     0>,
+					<     0      0      0     0>;
+
+				qcom,cpr-open-loop-voltage-fuse-adjustment =
+					/* Speed bin 0; CPR rev 0..7 */
+					/*   SVS  Nominal Turbo Turbo_L1 */
+					<     0      0      0     0>,
+					<     0      0  15000     0>,
+					<     0      0  15000     0>,
+					<     0      0      0     0>,
+					<     0      0      0     0>,
+					<     0      0      0     0>,
+					<     0      0      0     0>,
+					<     0      0      0     0>;
+
+				qcom,cpr-closed-loop-voltage-fuse-adjustment =
+					/* Speed bin 0; CPR rev 0..7 */
+					<     0      0      0     0>,
+					< 13000      0  13000 13000>,
+					< 13000      0  13000 13000>,
+					<     0      0      0     0>,
+					<     0      0      0     0>,
+					<     0      0      0     0>,
+					<     0      0      0     0>,
+					<     0      0      0     0>;
+
+				qcom,cpr-ro-scaling-factor =
+					< 2000 1770 1900 1670 1930 1770 1910 1800
+					  1870 1730 2000 1840 1800 2030 1700 1890 >,
+					< 2000 1770 1900 1670 1930 1770 1910 1800
+					  1870 1730 2000 1840 1800 2030 1700 1890 >,
+					< 2000 1770 1900 1670 1930 1770 1910 1800
+					  1870 1730 2000 1840 1800 2030 1700 1890 >,
+					< 2000 1770 1900 1670 1930 1770 1910 1800
+					  1870 1730 2000 1840 1800 2030 1700 1890 >;
+				regulator-always-on;
+			};
+		};
+	};
+};
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6018-ess.dtsi b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6018-ess.dtsi
new file mode 100644
index 00000000000000..ad4357bb37d077
--- /dev/null
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6018-ess.dtsi
@@ -0,0 +1,507 @@
+#include <dt-bindings/net/qcom-ipq-ess.h>
+
+&soc {
+	bias_pll_cc_clk: bias-pll-cc-clk {
+		compatible = "fixed-clock";
+		clock-frequency = <300000000>;
+		clock-output-names = "bias_pll_cc_clk";
+		#clock-cells = <0>;
+	};
+
+	bias_pll_nss_noc_clk: bias-pll-nss-noc-clk {
+		compatible = "fixed-clock";
+		clock-frequency = <416500000>;
+		clock-output-names = "bias_pll_nss_noc_clk";
+		#clock-cells = <0>;
+	};
+
+	edma: edma@3ab00000 {
+		compatible = "qcom,edma";
+		reg = <0x0 0x3ab00000 0x0 0xabe00>;
+		reg-names = "edma-reg-base";
+		qcom,txdesc-ring-start = <23>;
+		qcom,txdesc-rings = <1>;
+		qcom,txcmpl-ring-start = <23>;
+		qcom,txcmpl-rings = <1>;
+		qcom,rxfill-ring-start = <7>;
+		qcom,rxfill-rings = <1>;
+		qcom,rxdesc-ring-start = <15>;
+		qcom,rxdesc-rings = <1>;
+		interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+		resets = <&gcc GCC_EDMA_HW_RESET>;
+		reset-names = "edma_rst";
+		status = "disabled";
+	};
+
+	ess_instance: ess-instance {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		num_devices = <1>;
+
+		switch: ess-switch@3a000000 {
+			compatible = "qcom,ess-switch-ipq60xx";
+			reg = <0x3a000000 0x1000000>;
+			switch_access_mode = "local bus";
+			clocks = <&gcc GCC_CMN_12GPLL_AHB_CLK>,
+				 <&gcc GCC_CMN_12GPLL_SYS_CLK>,
+				 <&gcc GCC_UNIPHY0_AHB_CLK>,
+				 <&gcc GCC_UNIPHY0_SYS_CLK>,
+				 <&gcc GCC_UNIPHY1_AHB_CLK>,
+				 <&gcc GCC_UNIPHY1_SYS_CLK>,
+				 <&gcc GCC_PORT1_MAC_CLK>,
+				 <&gcc GCC_PORT2_MAC_CLK>,
+				 <&gcc GCC_PORT3_MAC_CLK>,
+				 <&gcc GCC_PORT4_MAC_CLK>,
+				 <&gcc GCC_PORT5_MAC_CLK>,
+				 <&gcc GCC_NSS_PPE_CLK>,
+				 <&gcc GCC_NSS_PPE_CFG_CLK>,
+				 <&gcc GCC_NSSNOC_PPE_CLK>,
+				 <&gcc GCC_NSSNOC_PPE_CFG_CLK>,
+				 <&gcc GCC_NSS_EDMA_CLK>,
+				 <&gcc GCC_NSS_EDMA_CFG_CLK>,
+				 <&gcc GCC_NSS_PPE_IPE_CLK>,
+				 <&gcc GCC_MDIO_AHB_CLK>,
+				 <&gcc GCC_NSS_NOC_CLK>,
+				 <&gcc GCC_NSSNOC_SNOC_CLK>,
+				 <&gcc GCC_NSS_CRYPTO_CLK>,
+				 <&gcc GCC_NSS_PTP_REF_CLK>,
+				 <&gcc GCC_NSS_PORT1_RX_CLK>,
+				 <&gcc GCC_NSS_PORT1_TX_CLK>,
+				 <&gcc GCC_NSS_PORT2_RX_CLK>,
+				 <&gcc GCC_NSS_PORT2_TX_CLK>,
+				 <&gcc GCC_NSS_PORT3_RX_CLK>,
+				 <&gcc GCC_NSS_PORT3_TX_CLK>,
+				 <&gcc GCC_NSS_PORT4_RX_CLK>,
+				 <&gcc GCC_NSS_PORT4_TX_CLK>,
+				 <&gcc GCC_NSS_PORT5_RX_CLK>,
+				 <&gcc GCC_NSS_PORT5_TX_CLK>,
+				 <&gcc GCC_UNIPHY0_PORT1_RX_CLK>,
+				 <&gcc GCC_UNIPHY0_PORT1_TX_CLK>,
+				 <&gcc GCC_UNIPHY0_PORT2_RX_CLK>,
+				 <&gcc GCC_UNIPHY0_PORT2_TX_CLK>,
+				 <&gcc GCC_UNIPHY0_PORT3_RX_CLK>,
+				 <&gcc GCC_UNIPHY0_PORT3_TX_CLK>,
+				 <&gcc GCC_UNIPHY0_PORT4_RX_CLK>,
+				 <&gcc GCC_UNIPHY0_PORT4_TX_CLK>,
+				 <&gcc GCC_UNIPHY0_PORT5_RX_CLK>,
+				 <&gcc GCC_UNIPHY0_PORT5_TX_CLK>,
+				 <&gcc GCC_UNIPHY1_PORT5_RX_CLK>,
+				 <&gcc GCC_UNIPHY1_PORT5_TX_CLK>,
+				 <&gcc NSS_PORT5_RX_CLK_SRC>,
+				 <&gcc NSS_PORT5_TX_CLK_SRC>,
+				 <&gcc GCC_SNOC_NSSNOC_CLK>;
+			clock-names = "cmn_ahb_clk", "cmn_sys_clk",
+					"uniphy0_ahb_clk", "uniphy0_sys_clk",
+					"uniphy1_ahb_clk", "uniphy1_sys_clk",
+					"port1_mac_clk", "port2_mac_clk",
+					"port3_mac_clk", "port4_mac_clk",
+					"port5_mac_clk",
+					"nss_ppe_clk", "nss_ppe_cfg_clk",
+					"nssnoc_ppe_clk", "nssnoc_ppe_cfg_clk",
+					"nss_edma_clk", "nss_edma_cfg_clk",
+					"nss_ppe_ipe_clk",
+					"gcc_mdio_ahb_clk", "gcc_nss_noc_clk",
+					"gcc_nssnoc_snoc_clk",
+					"gcc_nss_crypto_clk",
+					"gcc_nss_ptp_ref_clk",
+					"nss_port1_rx_clk", "nss_port1_tx_clk",
+					"nss_port2_rx_clk", "nss_port2_tx_clk",
+					"nss_port3_rx_clk", "nss_port3_tx_clk",
+					"nss_port4_rx_clk", "nss_port4_tx_clk",
+					"nss_port5_rx_clk", "nss_port5_tx_clk",
+					"uniphy0_port1_rx_clk",
+					"uniphy0_port1_tx_clk",
+					"uniphy0_port2_rx_clk",
+					"uniphy0_port2_tx_clk",
+					"uniphy0_port3_rx_clk",
+					"uniphy0_port3_tx_clk",
+					"uniphy0_port4_rx_clk",
+					"uniphy0_port4_tx_clk",
+					"uniphy0_port5_rx_clk",
+					"uniphy0_port5_tx_clk",
+					"uniphy1_port5_rx_clk",
+					"uniphy1_port5_tx_clk",
+					"nss_port5_rx_clk_src",
+					"nss_port5_tx_clk_src",
+					"gcc_snoc_nssnoc_clk";
+			resets = <&gcc GCC_PPE_FULL_RESET>,
+				 <&gcc GCC_UNIPHY0_SOFT_RESET>,
+				 <&gcc GCC_UNIPHY0_XPCS_RESET>,
+				 <&gcc GCC_UNIPHY1_SOFT_RESET>,
+				 <&gcc GCC_UNIPHY1_XPCS_RESET>,
+				 <&gcc GCC_NSSPORT1_RESET>,
+				 <&gcc GCC_NSSPORT2_RESET>,
+				 <&gcc GCC_NSSPORT3_RESET>,
+				 <&gcc GCC_NSSPORT4_RESET>,
+				 <&gcc GCC_NSSPORT5_RESET>,
+				 <&gcc GCC_UNIPHY0_PORT1_ARES>,
+				 <&gcc GCC_UNIPHY0_PORT2_ARES>,
+				 <&gcc GCC_UNIPHY0_PORT3_ARES>,
+				 <&gcc GCC_UNIPHY0_PORT4_ARES>,
+				 <&gcc GCC_UNIPHY0_PORT5_ARES>,
+				 <&gcc GCC_UNIPHY0_PORT_4_5_RESET>,
+				 <&gcc GCC_UNIPHY0_PORT_4_RESET>;
+			reset-names = "ppe_rst", "uniphy0_soft_rst",
+					"uniphy0_xpcs_rst", "uniphy1_soft_rst",
+					"uniphy1_xpcs_rst", "nss_port1_rst",
+					"nss_port2_rst", "nss_port3_rst",
+					"nss_port4_rst", "nss_port5_rst",
+					"uniphy0_port1_dis",
+					"uniphy0_port2_dis",
+					"uniphy0_port3_dis",
+					"uniphy0_port4_dis",
+					"uniphy0_port5_dis",
+					"uniphy0_port_4_5_rst",
+					"uniphy0_port_4_rst";
+			mdio-bus = <&mdio>;
+
+			switch_cpu_bmp = <ESS_PORT0>;  /* cpu port bitmap */
+			switch_inner_bmp = <(ESS_PORT6 | ESS_PORT7)>; /*inner port bitmap*/
+			switch_mac_mode = <MAC_MODE_DISABLED>; /* MAC mode for UNIPHY instance 0 */
+			switch_mac_mode1 = <MAC_MODE_DISABLED>; /* MAC mode for UNIPHY instance 1 */
+			switch_mac_mode2 = <MAC_MODE_DISABLED>; /* MAC mode for UNIPHY instance 2 */
+
+			status = "disabled";
+
+			bm_tick_mode = <0>; /* bm tick mode */
+			tm_tick_mode = <0>; /* tm tick mode */
+
+			port_scheduler_resource {
+				port@0 {
+					port_id = <0>;
+					ucast_queue = <0 143>;
+					mcast_queue = <256 271>;
+					l0sp = <0 35>;
+					l0cdrr = <0 47>;
+					l0edrr = <0 47>;
+					l1cdrr = <0 7>;
+					l1edrr = <0 7>;
+				};
+				port@1 {
+					port_id = <1>;
+					ucast_queue = <144 159>;
+					mcast_queue = <272 275>;
+					l0sp = <36 39>;
+					l0cdrr = <48 63>;
+					l0edrr = <48 63>;
+					l1cdrr = <8 11>;
+					l1edrr = <8 11>;
+				};
+				port@2 {
+					port_id = <2>;
+					ucast_queue = <160 175>;
+					mcast_queue = <276 279>;
+					l0sp = <40 43>;
+					l0cdrr = <64 79>;
+					l0edrr = <64 79>;
+					l1cdrr = <12 15>;
+					l1edrr = <12 15>;
+				};
+				port@3 {
+					port_id = <3>;
+					ucast_queue = <176 191>;
+					mcast_queue = <280 283>;
+					l0sp = <44 47>;
+					l0cdrr = <80 95>;
+					l0edrr = <80 95>;
+					l1cdrr = <16 19>;
+					l1edrr = <16 19>;
+				};
+				port@4 {
+					port_id = <4>;
+					ucast_queue = <192 207>;
+					mcast_queue = <284 287>;
+					l0sp = <48 51>;
+					l0cdrr = <96 111>;
+					l0edrr = <96 111>;
+					l1cdrr = <20 23>;
+					l1edrr = <20 23>;
+				};
+				port@5 {
+					port_id = <5>;
+					ucast_queue = <208 223>;
+					mcast_queue = <288 291>;
+					l0sp = <52 55>;
+					l0cdrr = <112 127>;
+					l0edrr = <112 127>;
+					l1cdrr = <24 27>;
+					l1edrr = <24 27>;
+				};
+				port@6 {
+					port_id = <6>;
+					ucast_queue = <224 239>;
+					mcast_queue = <292 295>;
+					l0sp = <56 59>;
+					l0cdrr = <128 143>;
+					l0edrr = <128 143>;
+					l1cdrr = <28 31>;
+					l1edrr = <28 31>;
+				};
+				port@7 {
+					port_id = <7>;
+					ucast_queue = <240 255>;
+					mcast_queue = <296 299>;
+					l0sp = <60 63>;
+					l0cdrr = <144 159>;
+					l0edrr = <144 159>;
+					l1cdrr = <32 35>;
+					l1edrr = <32 35>;
+				};
+			};
+			port_scheduler_config {
+				port@0 {
+					port_id = <0>;
+					l1scheduler {
+						group@0 {
+							sp = <0 1>; /*L0 SPs*/
+							/*cpri cdrr epri edrr*/
+							cfg = <0 0 0 0>;
+						};
+					};
+					l0scheduler {
+						group@0 {
+							/*unicast queues*/
+							ucast_queue = <0 4 8>;
+							/*multicast queues*/
+							mcast_queue = <256 260>;
+							/*sp cpricdrrepriedrr*/
+							cfg = <0 0 0 0 0>;
+						};
+						group@1 {
+							ucast_queue = <1 5 9>;
+							mcast_queue = <257 261>;
+							cfg = <0 1 1 1 1>;
+						};
+						group@2 {
+							ucast_queue = <2 6 10>;
+							mcast_queue = <258 262>;
+							cfg = <0 2 2 2 2>;
+						};
+						group@3 {
+							ucast_queue = <3 7 11>;
+							mcast_queue = <259 263>;
+							cfg = <0 3 3 3 3>;
+						};
+					};
+				};
+				port@1 {
+					port_id = <1>;
+					l1scheduler {
+						group@0 {
+							sp = <36>;
+							cfg = <0 8 0 8>;
+						};
+						group@1 {
+							sp = <37>;
+							cfg = <1 9 1 9>;
+						};
+					};
+					l0scheduler {
+						group@0 {
+							ucast_queue = <144>;
+							ucast_loop_pri = <16>;
+							mcast_queue = <272>;
+							mcast_loop_pri = <4>;
+							cfg = <36 0 48 0 48>;
+						};
+					};
+				};
+				port@2 {
+					port_id = <2>;
+					l1scheduler {
+						group@0 {
+							sp = <40>;
+							cfg = <0 12 0 12>;
+						};
+						group@1 {
+							sp = <41>;
+							cfg = <1 13 1 13>;
+						};
+					};
+					l0scheduler {
+						group@0 {
+							ucast_queue = <160>;
+							ucast_loop_pri = <16>;
+							mcast_queue = <276>;
+							mcast_loop_pri = <4>;
+							cfg = <40 0 64 0 64>;
+						};
+					};
+				};
+				port@3 {
+					port_id = <3>;
+					l1scheduler {
+						group@0 {
+							sp = <44>;
+							cfg = <0 16 0 16>;
+						};
+						group@1 {
+							sp = <45>;
+							cfg = <1 17 1 17>;
+						};
+					};
+					l0scheduler {
+						group@0 {
+							ucast_queue = <176>;
+							ucast_loop_pri = <16>;
+							mcast_queue = <280>;
+							mcast_loop_pri = <4>;
+							cfg = <44 0 80 0 80>;
+						};
+					};
+				};
+				port@4 {
+					port_id = <4>;
+					l1scheduler {
+						group@0 {
+							sp = <48>;
+							cfg = <0 20 0 20>;
+						};
+						group@1 {
+							sp = <49>;
+							cfg = <1 21 1 21>;
+						};
+					};
+					l0scheduler {
+						group@0 {
+							ucast_queue = <192>;
+							ucast_loop_pri = <16>;
+							mcast_queue = <284>;
+							mcast_loop_pri = <4>;
+							cfg = <48 0 96 0 96>;
+						};
+					};
+				};
+				port@5 {
+					port_id = <5>;
+					l1scheduler {
+						group@0 {
+							sp = <52>;
+							cfg = <0 24 0 24>;
+						};
+						group@1 {
+							sp = <53>;
+							cfg = <1 25 1 25>;
+						};
+					};
+					l0scheduler {
+						group@0 {
+							ucast_queue = <208>;
+							ucast_loop_pri = <16>;
+							mcast_queue = <288>;
+							mcast_loop_pri = <4>;
+							cfg = <52 0 112 0 112>;
+						};
+					};
+				};
+				port@6 {
+					port_id = <6>;
+					l1scheduler {
+						group@0 {
+							sp = <56>;
+							cfg = <0 28 0 28>;
+						};
+						group@1 {
+							sp = <57>;
+							cfg = <1 29 1 29>;
+						};
+					};
+					l0scheduler {
+						group@0 {
+							ucast_queue = <224>;
+							ucast_loop_pri = <16>;
+							mcast_queue = <292>;
+							mcast_loop_pri = <4>;
+							cfg = <56 0 128 0 128>;
+						};
+					};
+				};
+				port@7 {
+					port_id = <7>;
+					l1scheduler {
+						group@0 {
+							sp = <60>;
+							cfg = <0 32 0 32>;
+						};
+						group@1 {
+							sp = <61>;
+							cfg = <1 33 1 33>;
+						};
+					};
+					l0scheduler {
+						group@0 {
+							ucast_queue = <240>;
+							ucast_loop_pri = <16>;
+							mcast_queue = <296>;
+							cfg = <60 0 144 0 144>;
+						};
+					};
+				};
+			};
+		};
+
+		ess-uniphy@7a00000 {
+			compatible = "qcom,ess-uniphy";
+			reg = <0x7a00000 0x30000>;
+			uniphy_access_mode = "local bus";
+		};
+	};
+
+	dp1: dp1 {
+		device_type = "network";
+		compatible = "qcom,nss-dp";
+		qcom,id = <1>;
+		reg = <0x0 0x3a001000 0x0 0x200>;
+		qcom,mactype = <0>;
+		local-mac-address = [000000000000];
+		phy-mode = "psgmii";
+		status = "disabled";
+	};
+
+	dp2: dp2 {
+		device_type = "network";
+		compatible = "qcom,nss-dp";
+		qcom,id = <2>;
+		reg = <0x0 0x3a001200 0x0 0x200>;
+		qcom,mactype = <0>;
+		local-mac-address = [000000000000];
+		phy-mode = "psgmii";
+		status = "disabled";
+	};
+
+	dp3: dp3 {
+		device_type = "network";
+		compatible = "qcom,nss-dp";
+		qcom,id = <3>;
+		reg = <0x0 0x3a001400 0x0 0x200>;
+		qcom,mactype = <0>;
+		local-mac-address = [000000000000];
+		phy-mode = "psgmii";
+		status = "disabled";
+	};
+
+	dp4: dp4 {
+		device_type = "network";
+		compatible = "qcom,nss-dp";
+		qcom,id = <4>;
+		reg = <0x0 0x3a001600 0x0 0x200>;
+		qcom,mactype = <0>;
+		local-mac-address = [000000000000];
+		phy-mode = "psgmii";
+		status = "disabled";
+	};
+
+	dp5: dp5 {
+		device_type = "network";
+		compatible = "qcom,nss-dp";
+		qcom,id = <5>;
+		reg = <0x0 0x3a001800 0x0 0x200>;
+		qcom,mactype = <0>;
+		local-mac-address = [000000000000];
+		phy-mode = "sgmii";
+		status = "disabled";
+	};
+};
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8070-cax1800.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8070-cax1800.dts
index 0ca2edcb2ca7c3..e62ae314fb5d82 100644
--- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8070-cax1800.dts
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8070-cax1800.dts
@@ -262,9 +262,16 @@
 
 	reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
 
-	qca8075: ethernet-phy@4 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <4>;
+	ethernet-phy-package@0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "qcom,qca8075-package";
+		reg = <0>;
+
+		qca8075_4: ethernet-phy@4 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <4>;
+		};
 	};
 };
 
@@ -288,7 +295,7 @@
 
 &dp5 {
 	status = "okay";
-	phy-handle = <&qca8075>;
+	phy-handle = <&qca8075_4>;
 	label = "lan";
 };
 
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8070-rm2-6.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8070-rm2-6.dts
new file mode 100644
index 00000000000000..d935e19ad248c4
--- /dev/null
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8070-rm2-6.dts
@@ -0,0 +1,310 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+/dts-v1/;
+
+#include "ipq8074-512m.dtsi"
+#include "ipq8074-ac-cpu.dtsi"
+#include "ipq8074-ess.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+	model = "CMCC RM2-6";
+	compatible = "cmcc,rm2-6", "qcom,ipq8074";
+
+	aliases {
+		serial0 = &blsp1_uart5;
+		serial1 = &blsp1_uart3;
+		led-boot = &led_status_red;
+		led-failsafe = &led_status_red;
+		led-running = &led_status_blue;
+		led-upgrade = &led_status_amber;
+		/*
+		 * Aliases as required by u-boot
+		 * to patch MAC addresses
+		 */
+		ethernet0 = &dp4;
+		ethernet1 = &dp2;
+		ethernet2 = &dp5;
+		label-mac-device = &dp4;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+		bootargs-append = " root=/dev/ubiblock0_1";
+	};
+
+	keys {
+		compatible = "gpio-keys";
+
+		wps {
+			label = "wps";
+			linux,code = <KEY_WPS_BUTTON>;
+			gpios = <&tlmm 27 GPIO_ACTIVE_LOW>;
+		};
+
+		reset {
+			label = "reset";
+			linux,code = <KEY_RESTART>;
+			gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_status_amber: status-amber {
+			color = <LED_COLOR_ID_AMBER>;
+			function = LED_FUNCTION_STATUS;
+			gpio = <&tlmm 25 GPIO_ACTIVE_HIGH>;
+		};
+
+		led_status_blue: status-blue {
+			color = <LED_COLOR_ID_BLUE>;
+			function = LED_FUNCTION_STATUS;
+			gpio = <&tlmm 26 GPIO_ACTIVE_HIGH>;
+		};
+
+		led_status_red: status-red {
+			color = <LED_COLOR_ID_RED>;
+			function = LED_FUNCTION_STATUS;
+			gpio = <&tlmm 31 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	fan: gpio-fan {
+		#cooling-cells = <2>;
+		compatible = "gpio-fan";
+		gpio = <&tlmm 29 GPIO_ACTIVE_HIGH>;
+		gpio-fan,speed-map = <0 0>, <1 1>;
+	};
+};
+
+&tlmm {
+	mdio_pins: mdio-pins {
+		mdc {
+			pins = "gpio68";
+			function = "mdc";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+
+		mdio {
+			pins = "gpio69";
+			function = "mdio";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+	};
+};
+
+&blsp1_uart3 {
+	status = "okay";
+};
+
+&blsp1_uart5 {
+	status = "okay";
+};
+
+&cryptobam {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
+&qpic_bam {
+	status = "okay";
+};
+
+&qpic_nand {
+	status = "okay";
+
+	nand@0 {
+		reg = <0>;
+		nand-ecc-strength = <8>;
+		nand-ecc-step-size = <512>;
+		nand-bus-width = <8>;
+
+		partitions {
+			compatible = "qcom,smem-part";
+		};
+	};
+};
+
+&cpu0_thermal {
+	trips {
+		cpu0_trip_active: cpu-active {
+			temperature = <60000>;
+			hysteresis = <2000>;
+			type = "active";
+		};
+	};
+
+	cooling-maps {
+		cpu-active {
+			cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+			trip = <&cpu0_trip_active>;
+		};
+	};
+};
+
+&cpu1_thermal {
+	trips {
+		cpu1_trip_active: cpu-active {
+			temperature = <60000>;
+			hysteresis = <2000>;
+			type = "active";
+		};
+	};
+
+	cooling-maps {
+		cpu-active {
+			cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+			trip = <&cpu1_trip_active>;
+		};
+	};
+};
+
+&cpu2_thermal {
+	trips {
+		cpu2_trip_active: cpu-active {
+			temperature = <60000>;
+			hysteresis = <2000>;
+			type = "active";
+		};
+	};
+
+	cooling-maps {
+		cpu-active {
+			cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+			trip = <&cpu2_trip_active>;
+		};
+	};
+};
+
+&cpu3_thermal {
+	trips {
+		cpu3_trip_active: cpu-active {
+			temperature = <60000>;
+			hysteresis = <2000>;
+			type = "active";
+		};
+	};
+
+	cooling-maps {
+		cpu-active {
+			cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+			trip = <&cpu3_trip_active>;
+		};
+	};
+};
+
+&cluster_thermal {
+	trips {
+		cluster_active: cluster-active {
+			temperature = <60000>;
+			hysteresis = <2000>;
+			type = "active";
+		};
+	};
+
+	cooling-maps {
+		cluster-active {
+			cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+			trip = <&cluster_active>;
+		};
+	};
+};
+
+&mdio {
+	status = "okay";
+
+	pinctrl-0 = <&mdio_pins>;
+	pinctrl-names = "default";
+	reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
+
+	ethernet-phy-package@0 {
+		compatible = "qcom,qca8075-package";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0>;
+
+		qca8075_1: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+		};
+
+		qca8075_3: ethernet-phy@3 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <3>;
+		};
+
+		qca8075_4: ethernet-phy@4 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <4>;
+		};
+	};
+};
+
+&switch {
+	status = "okay";
+
+	switch_lan_bmp = <(ESS_PORT2 | ESS_PORT4)>;
+	switch_wan_bmp = <ESS_PORT5>;
+	switch_mac_mode = <MAC_MODE_PSGMII>;
+
+	qcom,port_phyinfo {
+		port@2 {
+			port_id = <2>;
+			phy_address = <1>;
+		};
+		port@4 {
+			port_id = <4>;
+			phy_address = <3>;
+		};
+		port@5 {
+			port_id = <5>;
+			phy_address = <4>;
+		};
+	};
+};
+
+&edma {
+	status = "okay";
+};
+
+/*
+ * Directly connect to the Hi5630
+ * PLC (Power Line Communication)
+ */
+&dp2 {
+	status = "okay";
+	phy-handle = <&qca8075_1>;
+	label = "plc";
+};
+
+&dp4 {
+	status = "okay";
+	phy-handle = <&qca8075_3>;
+	label = "lan";
+};
+
+&dp5 {
+	status = "okay";
+	phy-handle = <&qca8075_4>;
+	label = "wan";
+};
+
+&wifi {
+	status = "okay";
+
+	qcom,ath11k-calibration-variant = "CMCC-RM2-6";
+	qcom,ath11k-fw-memory-mode = <1>;
+};
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-ax3600.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-ax3600.dts
index f3e82e22511875..c6889df25d8de9 100644
--- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-ax3600.dts
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-ax3600.dts
@@ -4,6 +4,7 @@
 /dts-v1/;
 
 #include "ipq8071-ax3600.dtsi"
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Xiaomi AX3600";
@@ -71,3 +72,59 @@
 &wifi {
 	qcom,ath11k-calibration-variant = "Xiaomi-AX3600";
 };
+
+&qca8075_1 {
+	leds {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		led@0 {
+			reg = <0>;
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_WAN;
+			default-state = "keep";
+		};
+	};
+};
+
+&qca8075_2 {
+	leds {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		led@0 {
+			reg = <0>;
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_LAN;
+			default-state = "keep";
+		};
+	};
+};
+
+&qca8075_3 {
+	leds {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		led@0 {
+			reg = <0>;
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_LAN;
+			default-state = "keep";
+		};
+	};
+};
+
+&qca8075_4 {
+	leds {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		led@0 {
+			reg = <0>;
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_LAN;
+			default-state = "keep";
+		};
+	};
+};
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-ax3600.dtsi b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-ax3600.dtsi
index 2bb2cce157ca45..6afafb35546e00 100644
--- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-ax3600.dtsi
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-ax3600.dtsi
@@ -213,24 +213,31 @@
 	pinctrl-names = "default";
 	reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
 
-	qca8075_1: ethernet-phy@1 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <1>;
-	};
+	ethernet-phy-package@0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "qcom,qca8075-package";
+		reg = <0>;
 
-	qca8075_2: ethernet-phy@2 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <2>;
-	};
+		qca8075_1: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+		};
 
-	qca8075_3: ethernet-phy@3 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <3>;
-	};
+		qca8075_2: ethernet-phy@2 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <2>;
+		};
+
+		qca8075_3: ethernet-phy@3 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <3>;
+		};
 
-	qca8075_4: ethernet-phy@4 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <4>;
+		qca8075_4: ethernet-phy@4 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <4>;
+		};
 	};
 };
 
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-eap102.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-eap102.dts
index 9503f4b92aec76..f3d2fa34126470 100644
--- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-eap102.dts
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-eap102.dts
@@ -8,6 +8,7 @@
 #include "ipq8074-ess.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Edgecore EAP102";
@@ -64,7 +65,8 @@
 		};
 
 		led_system_green: led_system {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&tlmm 50 GPIO_ACTIVE_HIGH>;
 		};
 	};
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-mf269.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-mf269.dts
index 51bb533d1e85ea..3ca92a7a8f3f13 100644
--- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-mf269.dts
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-mf269.dts
@@ -7,6 +7,7 @@
 #include "ipq8074-ess.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "ZTE MF269";
@@ -48,7 +49,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "white:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_WHITE>;
 			gpio = <&tlmm 56 GPIO_ACTIVE_HIGH>;
 		};
 	};
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-301w.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-301w.dts
index 572812ec393dcb..081e932b5c7eb8 100644
--- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-301w.dts
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-301w.dts
@@ -61,97 +61,81 @@
 		pinctrl-names = "default";
 
 		led_system_green: led-system-green {
-			label = "green:system";
 			gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_GREEN>;
 		};
 
 		led_system_red: led-system-red {
-			label = "red:system";
 			gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_RED>;
 		};
 
 		led_pwr_green: led-pwr-green {
-			label = "green:pwr";
 			gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_GREEN>;
 		};
 
 		led-wifi-green {
-			label = "green:wifi";
 			gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_GREEN>;
 		};
 
 		led-lan4-green {
-			label = "green:lan4";
 			gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_GREEN>;
 		};
 
 		led-lan4-amber {
-			label = "amber:lan4";
 			gpios = <&tlmm 7 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_AMBER>;
 		};
 
 		led-lan3-green {
-			label = "green:lan3";
 			gpios = <&tlmm 8 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_GREEN>;
 		};
 
 		led-lan3-amber {
-			label = "amber:lan3";
 			gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_AMBER>;
 		};
 
 		led-lan2-green {
-			label = "green:lan2";
 			gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_GREEN>;
 		};
 
 		led-lan2-amber {
-			label = "amber:lan2";
 			gpios = <&tlmm 13 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_AMBER>;
 		};
 
 		led-lan1-green {
-			label = "green:lan1";
 			gpios = <&tlmm 14 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_GREEN>;
 		};
 
 		led-lan1-amber {
-			label = "amber:lan1";
 			gpios = <&tlmm 15 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_AMBER>;
 		};
 
 		led-10g-1-green {
-			label = "green:10g_1";
 			gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_GREEN>;
 		};
 
 		led-10g-1-amber {
-			label = "amber:10g_1";
 			gpios = <&tlmm 56 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_AMBER>;
 		};
 
 		led-10g-2-green {
-			label = "green:10g_2";
 			gpios = <&tlmm 51 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_GREEN>;
 		};
 
 		led-10g-2-amber {
-			label = "amber:10g_2";
 			gpios = <&tlmm 52 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_AMBER>;
 		};
@@ -382,24 +366,33 @@
 		nvmem-cells = <&aqr1_fw>;
 	};
 
-	qca8075_16: ethernet-phy@16 {
-		compatible = "ethernet-phy-ieee802.3-c22";
+	ethernet-phy-package@16 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "qcom,qca8075-package";
 		reg = <16>;
-	};
 
-	qca8075_17: ethernet-phy@17 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <17>;
-	};
+		qcom,package-mode = "qsgmii";
 
-	qca8075_18: ethernet-phy@18 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <18>;
-	};
+		qca8075_16: ethernet-phy@16 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <16>;
+		};
 
-	qca8075_19: ethernet-phy@19 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <19>;
+		qca8075_17: ethernet-phy@17 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <17>;
+		};
+
+		qca8075_18: ethernet-phy@18 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <18>;
+		};
+
+		qca8075_19: ethernet-phy@19 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <19>;
+		};
 	};
 };
 
@@ -421,7 +414,6 @@
 
 	switch_lan_bmp = <(ESS_PORT1 | ESS_PORT2 | ESS_PORT3 | ESS_PORT4 | ESS_PORT6)>; /* lan port bitmap */
 	switch_wan_bmp = <ESS_PORT5>; /* wan port bitmap */
-	malibu_first_phy_addr = <16>; /* PHY addr of the first malibu PHY */
 	switch_mac_mode = <MAC_MODE_QSGMII>; /* mac mode for uniphy instance0*/
 	switch_mac_mode1 = <MAC_MODE_USXGMII>; /* mac mode for uniphy instance1*/
 	switch_mac_mode2 = <MAC_MODE_USXGMII>; /* mac mode for uniphy instance2*/
@@ -464,24 +456,28 @@
 
 &dp1 {
 	status = "okay";
+	phy-mode = "qsgmii";
 	phy-handle = <&qca8075_16>;
 	label = "lan4";
 };
 
 &dp2 {
 	status = "okay";
+	phy-mode = "qsgmii";
 	phy-handle = <&qca8075_17>;
 	label = "lan3";
 };
 
 &dp3 {
 	status = "okay";
+	phy-mode = "qsgmii";
 	phy-handle = <&qca8075_18>;
 	label = "lan2";
 };
 
 &dp4 {
 	status = "okay";
+	phy-mode = "qsgmii";
 	phy-handle = <&qca8075_19>;
 	label = "lan1";
 };
@@ -489,12 +485,14 @@
 &dp5 {
 	status = "okay";
 	qcom,mactype = <1>;
+	phy-mode = "usxgmii";
 	phy-handle = <&aqr113c_8>;
 	label = "10g-1";
 };
 
 &dp6_syn {
 	status = "okay";
+	phy-mode = "usxgmii";
 	phy-handle = <&aqr113c_0>;
 	label = "10g-2";
 };
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-aw1000.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-aw1000.dts
index 877a487b978f7f..c85e9f1993aa33 100644
--- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-aw1000.dts
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-aw1000.dts
@@ -8,6 +8,7 @@
 #include "ipq8074-ess.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Arcadyan AW1000";
@@ -109,7 +110,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&led_gpio 0 GPIO_ACTIVE_HIGH>;
 		};
 
@@ -244,24 +246,33 @@
 	pinctrl-names = "default";
 	reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
 
-	qca8075_0: ethernet-phy@0 {
-		compatible = "ethernet-phy-ieee802.3-c22";
+	ethernet-phy-package@0 {
+		compatible = "qcom,qca8075-package";
+		#address-cells = <1>;
+		#size-cells = <0>;
 		reg = <0>;
-	};
 
-	qca8075_1: ethernet-phy@1 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <1>;
-	};
+		qcom,package-mode = "qsgmii";
 
-	qca8075_2: ethernet-phy@2 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <2>;
-	};
+		qca8075_0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+		};
 
-	qca8075_3: ethernet-phy@3 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <3>;
+		qca8075_1: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+		};
+
+		qca8075_2: ethernet-phy@2 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <2>;
+		};
+
+		qca8075_3: ethernet-phy@3 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <3>;
+		};
 	};
 
 	qca8081: ethernet-phy@28 {
@@ -269,6 +280,19 @@
 		reg = <28>;
 		reset-deassert-us = <10000>;
 		reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>;
+
+		leds {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			led@2 {
+				reg = <2>;
+				active-low;
+				color = <LED_COLOR_ID_GREEN>;
+				function = LED_FUNCTION_WAN;
+				default-state = "keep";
+			};
+		};
 	};
 };
 
@@ -311,24 +335,28 @@
 
 &dp1 {
 	status = "okay";
+	phy-mode = "qsgmii";
 	phy-handle = <&qca8075_0>;
 	label = "lan1";
 };
 
 &dp2 {
 	status = "okay";
+	phy-mode = "qsgmii";
 	phy-handle = <&qca8075_1>;
 	label = "lan2";
 };
 
 &dp3 {
 	status = "okay";
+	phy-mode = "qsgmii";
 	phy-handle = <&qca8075_2>;
 	label = "lan3";
 };
 
 &dp4 {
 	status = "okay";
+	phy-mode = "qsgmii";
 	phy-handle = <&qca8075_3>;
 	label = "lan4";
 };
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-ax880.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-ax880.dts
index 7133969d35fc53..5364daad454741 100644
--- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-ax880.dts
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-ax880.dts
@@ -48,20 +48,17 @@
 		compatible = "gpio-leds";
 
 		led_system: system {
-			label = "system";
 			color = "red";
 			gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
 		};
 
 		wlan2g {
-			label = "wlan2g";
 			color = "green";
 			linux,default-trigger = "phy0tpt";
 			gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
 		};
 
 		wlan5g {
-			label = "wlan5g";
 			color = "blue";
 			linux,default-trigger = "phy1tpt";
 			gpios = <&tlmm 9 GPIO_ACTIVE_HIGH>;
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-ax9000.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-ax9000.dts
index 0ebdeb81940c78..805a2fc0bcf096 100644
--- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-ax9000.dts
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-ax9000.dts
@@ -48,45 +48,38 @@
 		compatible = "gpio-leds";
 
 		led_system_blue: system-blue {
-			label = "blue:system";
 			gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_BLUE>;
 		};
 
 		led_system_yellow: system-yellow {
-			label = "yellow:system";
 			gpios = <&tlmm 52 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_YELLOW>;
 		};
 
 		network-yellow {
-			label = "yellow:network";
 			gpios = <&tlmm 50 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_YELLOW>;
 		};
 
 		network-blue {
-			label = "blue:network";
 			gpios = <&tlmm 51 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_BLUE>;
 		};
 
 		top-red {
-			label = "red:top";
 			gpios = <&tlmm 63 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_RED>;
 			default-state = "keep";
 		};
 
 		top-green {
-			label = "green:top";
 			gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_GREEN>;
 			default-state = "keep";
 		};
 
 		top-blue {
-			label = "blue:top";
 			gpios = <&tlmm 66 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_BLUE>;
 			default-state = "keep";
@@ -354,24 +347,81 @@
 	pinctrl-names = "default";
 	reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
 
-	qca8075_0: ethernet-phy@0 {
-		compatible = "ethernet-phy-ieee802.3-c22";
+	ethernet-phy-package@0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "qcom,qca8075-package";
 		reg = <0>;
-	};
 
-	qca8075_1: ethernet-phy@1 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <1>;
-	};
+		qcom,package-mode = "qsgmii";
 
-	qca8075_2: ethernet-phy@2 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <2>;
-	};
+		qca8075_0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
 
-	qca8075_3: ethernet-phy@3 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <3>;
+				led@0 {
+					reg = <0>;
+					color = <LED_COLOR_ID_GREEN>;
+					function = LED_FUNCTION_LAN;
+					default-state = "keep";
+				};
+			};
+		};
+
+		qca8075_1: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					color = <LED_COLOR_ID_GREEN>;
+					function = LED_FUNCTION_LAN;
+					default-state = "keep";
+				};
+			};
+		};
+
+		qca8075_2: ethernet-phy@2 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <2>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					color = <LED_COLOR_ID_GREEN>;
+					function = LED_FUNCTION_LAN;
+					default-state = "keep";
+				};
+			};
+		};
+
+		qca8075_3: ethernet-phy@3 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <3>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					color = <LED_COLOR_ID_GREEN>;
+					function = LED_FUNCTION_LAN;
+					default-state = "keep";
+				};
+			};
+		};
 	};
 
 	qca8081: ethernet-phy@24 {
@@ -433,6 +483,7 @@
 
 &dp1 {
 	status = "okay";
+	phy-mode = "qsgmii";
 	phy-handle = <&qca8075_0>;
 	label = "lan4";
 	nvmem-cells = <&macaddr_dp1>;
@@ -441,6 +492,7 @@
 
 &dp2 {
 	status = "okay";
+	phy-mode = "qsgmii";
 	phy-handle = <&qca8075_1>;
 	label = "lan3";
 	nvmem-cells = <&macaddr_dp2>;
@@ -449,6 +501,7 @@
 
 &dp3 {
 	status = "okay";
+	phy-mode = "qsgmii";
 	phy-handle = <&qca8075_2>;
 	label = "lan2";
 	nvmem-cells = <&macaddr_dp3>;
@@ -457,6 +510,7 @@
 
 &dp4 {
 	status = "okay";
+	phy-mode = "qsgmii";
 	phy-handle = <&qca8075_3>;
 	label = "lan1";
 	nvmem-cells = <&macaddr_dp4>;
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-dl-wrx36.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-dl-wrx36.dts
index 3dec53f156af3c..c5c089c00f7dd4 100644
--- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-dl-wrx36.dts
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-dl-wrx36.dts
@@ -54,13 +54,11 @@
 		compatible = "gpio-leds";
 
 		led_system_blue: system-blue {
-			label = "blue:system";
 			gpios = <&tlmm 26 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_BLUE>;
 		};
 
 		led_system_red: system-red {
-			label = "red:system";
 			gpios = <&tlmm 25 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_RED>;
 		};
@@ -139,24 +137,33 @@
 	pinctrl-names = "default";
 	reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
 
-	qca8075_0: ethernet-phy@0 {
-		compatible = "ethernet-phy-ieee802.3-c22";
+	ethernet-phy-package@0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "qcom,qca8075-package";
 		reg = <0>;
-	};
 
-	qca8075_1: ethernet-phy@1 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <1>;
-	};
+		qcom,package-mode = "qsgmii";
 
-	qca8075_2: ethernet-phy@2 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <2>;
-	};
+		qca8075_0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+		};
 
-	qca8075_3: ethernet-phy@3 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <3>;
+		qca8075_1: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+		};
+
+		qca8075_2: ethernet-phy@2 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <2>;
+		};
+
+		qca8075_3: ethernet-phy@3 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <3>;
+		};
 	};
 
 	qca8081: ethernet-phy@28 {
@@ -225,24 +232,28 @@
 
 &dp1 {
 	status = "okay";
+	phy-mode = "qsgmii";
 	phy-handle = <&qca8075_0>;
 	label = "lan4";
 };
 
 &dp2 {
 	status = "okay";
+	phy-mode = "qsgmii";
 	phy-handle = <&qca8075_1>;
 	label = "lan3";
 };
 
 &dp3 {
 	status = "okay";
+	phy-mode = "qsgmii";
 	phy-handle = <&qca8075_2>;
 	label = "lan2";
 };
 
 &dp4 {
 	status = "okay";
+	phy-mode = "qsgmii";
 	phy-handle = <&qca8075_3>;
 	label = "lan1";
 };
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-haze.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-haze.dts
index 8fdfe981f9ce15..289680d678be07 100644
--- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-haze.dts
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-haze.dts
@@ -161,24 +161,31 @@
 	pinctrl-names = "default";
 	reset-gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
 
-	qca8075_1: ethernet-phy@0 {
-		compatible = "ethernet-phy-ieee802.3-c22";
+	ethernet-phy-package@0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "qcom,qca8075-package";
 		reg = <0>;
-	};
 
-	qca8075_2: ethernet-phy@1 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <1>;
-	};
+		qca8075_0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+		};
 
-	qca8075_3: ethernet-phy@2 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <2>;
-	};
+		qca8075_1: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+		};
 
-	qca8075_4: ethernet-phy@3 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <3>;
+		qca8075_2: ethernet-phy@2 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <2>;
+		};
+
+		qca8075_3: ethernet-phy@3 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <3>;
+		};
 	};
 
 	aqr113c: ethernet-phy@5 {
@@ -236,31 +243,32 @@
 /* Dummy LAN port */
 &dp1 {
 	status = "disabled";
-	phy-handle = <&qca8075_1>;
+	phy-handle = <&qca8075_0>;
 	label = "lan4";
 };
 
 &dp2 {
 	status = "okay";
-	phy-handle = <&qca8075_2>;
+	phy-handle = <&qca8075_1>;
 	label = "lan3";
 };
 
 &dp3 {
 	status = "okay";
-	phy-handle = <&qca8075_3>;
+	phy-handle = <&qca8075_2>;
 	label = "lan2";
 };
 
 &dp4 {
 	status = "okay";
-	phy-handle = <&qca8075_4>;
+	phy-handle = <&qca8075_3>;
 	label = "lan1";
 };
 
 &dp6_syn {
 	status = "okay";
 	qcom,mactype = <1>;
+	phy-mode = "usxgmii";
 	phy-handle = <&aqr113c>;
 	label = "wan";
 };
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-mx5300.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-mx5300.dts
new file mode 100644
index 00000000000000..e44731a1be7b34
--- /dev/null
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-mx5300.dts
@@ -0,0 +1,544 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+/dts-v1/;
+
+#include "ipq8074.dtsi"
+#include "ipq8074-hk-cpu.dtsi"
+#include "ipq8074-ess.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+	model = "Linksys MX5300";
+	compatible = "linksys,mx5300", "qcom,ipq8074";
+
+	aliases {
+		serial0 = &blsp1_uart5;
+		/*
+		 * Aliases as required by u-boot
+		 * to patch MAC addresses
+		 */
+		ethernet0 = &dp1;
+		ethernet1 = &dp2;
+		ethernet2 = &dp3;
+		ethernet3 = &dp4;
+		ethernet4 = &dp5;
+		led-boot = &led_system_blue;
+		led-running = &led_system_blue;
+		led-failsafe = &led_system_red;
+		led-upgrade = &led_system_green;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+		bootargs-append = " root=/dev/ubiblock0_0 rootfstype=squashfs ro";
+	};
+
+	keys {
+		compatible = "gpio-keys";
+		pinctrl-0 = <&button_pins>;
+		pinctrl-names = "default";
+
+		reset-button {
+			label = "reset";
+			gpios = <&tlmm 67 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+
+		wps-button {
+			label = "wps";
+			gpios = <&tlmm 54 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WPS_BUTTON>;
+		};
+	};
+};
+
+&tlmm {
+	button_pins: button-state {
+		pins = "gpio54", "gpio67";
+		function = "gpio";
+		drive-strength = <8>;
+		bias-pull-up;
+	};
+
+	mdio_pins: mdio-state {
+		mdc-pins {
+			pins = "gpio68";
+			function = "mdc";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+
+		mdio-pins {
+			pins = "gpio69";
+			function = "mdio";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+	};
+
+	/*
+	 * QCA4024 is not currently supported, keep for documentation purposes
+	 *spi_3_pins: spi-3-state {
+	 *	spi-pins {
+	 *		pins = "gpio50", "gpio52", "gpio53";
+	 *		function = "blsp3_spi";
+	 *		drive-strength = <8>;
+	 *		bias-disable;
+	 *	};
+	 *
+	 *	cs-pins {
+	 *		pins = "gpio22";
+	 *		function = "blsp3_spi2";
+	 *		drive-strength = <8>;
+	 *		bias-disable;
+	 *	};
+	 *};
+	 *
+	 *quartz_pins: quartz-state {
+	 *	interrupt-pins {
+	 *		pins = "gpio48";
+	 *		function = "gpio";
+	 *		bias-disable;
+	 *		input;
+	 *	};
+	 *
+	 *	reset-pins {
+	 *		pins = "gpio21";
+	 *		function = "gpio";
+	 *		bias-disable;
+	 *		output-high;
+	 *	};
+	 *};
+	 */
+};
+
+&blsp1_uart5 {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
+&cryptobam {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
+
+&qpic_bam {
+	status = "okay";
+};
+
+&qpic_nand {
+	status = "okay";
+
+	/*
+	 * Bootloader will find the NAND DT node by the compatible and
+	 * then "fixup" it by adding the partitions from the SMEM table
+	 * using the legacy bindings thus making it impossible for us
+	 * to change the partition table or utilize NVMEM for calibration.
+	 * So add a dummy partitions node that bootloader will populate
+	 * and set it as disabled so the kernel ignores it instead of
+	 * printing warnings due to the broken way bootloader adds the
+	 * partitions.
+	 */
+	partitions {
+		status = "disabled";
+	};
+
+	nand@0 {
+		reg = <0>;
+		nand-ecc-strength = <4>;
+		nand-ecc-step-size = <512>;
+		nand-bus-width = <8>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "0:sbl1";
+				reg = <0x0 0x100000>;
+				read-only;
+			};
+
+			partition@100000 {
+				label = "0:mibib";
+				reg = <0x100000 0x100000>;
+				read-only;
+			};
+
+			partition@200000 {
+				label = "0:bootconfig";
+				reg = <0x200000 0x80000>;
+				read-only;
+			};
+
+			partition@280000 {
+				label = "0:bootconfig1";
+				reg = <0x280000 0x80000>;
+				read-only;
+			};
+
+			partition@300000 {
+				label = "0:qsee";
+				reg = <0x300000 0x300000>;
+				read-only;
+			};
+
+			partition@600000 {
+				label = "0:qsee_1";
+				reg = <0x600000 0x300000>;
+				read-only;
+			};
+
+			partition@900000 {
+				label = "0:devcfg";
+				reg = <0x900000 0x80000>;
+				read-only;
+			};
+
+			partition@980000 {
+				label = "0:devcfg_1";
+				reg = <0x980000 0x80000>;
+				read-only;
+			};
+
+			partition@a00000 {
+				label = "0:apdp";
+				reg = <0xa00000 0x80000>;
+				read-only;
+			};
+
+			partition@a80000 {
+				label = "0:apdp_1";
+				reg = <0xa80000 0x80000>;
+				read-only;
+			};
+
+			partition@b00000 {
+				label = "0:rpm";
+				reg = <0xb00000 0x80000>;
+				read-only;
+			};
+
+			partition@b80000 {
+				label = "0:rpm_1";
+				reg = <0xb80000 0x80000>;
+				read-only;
+			};
+
+			partition@c00000 {
+				label = "0:cdt";
+				reg = <0xc00000 0x80000>;
+				read-only;
+			};
+
+			partition@c80000 {
+				label = "0:cdt_1";
+				reg = <0xc80000 0x80000>;
+				read-only;
+			};
+
+			partition@d00000 {
+				label = "0:appsblenv";
+				reg = <0xd00000 0x80000>;
+			};
+
+			partition@d80000 {
+				label = "0:appsbl";
+				reg = <0xd80000 0x100000>;
+				read-only;
+			};
+
+			partition@e80000 {
+				label = "0:appsbl_1";
+				reg = <0xe80000 0x100000>;
+				read-only;
+			};
+
+			partition@f80000 {
+				label = "0:art";
+				reg = <0xf80000 0x80000>;
+				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					caldata_qca9984: caldata@33000 {
+						reg = <0x33000 0x2f20>;
+					};
+				};
+			};
+
+			partition@1000000 {
+				label = "u_env";
+				reg = <0x1000000 0x40000>;
+			};
+
+			partition@1040000 {
+				label = "s_env";
+				reg = <0x1040000 0x20000>;
+			};
+
+			partition@1060000 {
+				label = "devinfo";
+				reg = <0x1060000 0x20000>;
+				read-only;
+			};
+
+			partition@1080000 {
+				label = "kernel";
+				reg = <0x1080000 0x9600000>;
+			};
+
+			partition@1680000 {
+				label = "rootfs";
+				reg = <0x1680000 0x9000000>;
+			};
+
+			partition@a680000 {
+				label = "alt_kernel";
+				reg = <0xa680000 0x9600000>;
+			};
+
+			partition@ac80000 {
+				label = "alt_rootfs";
+				reg = <0xac80000 0x9000000>;
+			};
+			partition@13c80000 {
+				label = "sysdiag";
+				reg = <0x13c80000 0x200000>;
+				read-only;
+			};
+			partition@13e80000 {
+				label = "0:ethphyfw";
+				reg = <0x13e80000 0x80000>;
+				read-only;
+			};
+			partition@13f00000 {
+				label = "syscfg";
+				reg = <0x13f00000 0xb800000>;
+				read-only;
+			};
+			partition@1f700000 {
+				label = "0:wififw";
+				reg = <0x1f700000 0x900000>;
+				read-only;
+			};
+		};
+	};
+};
+
+&blsp1_i2c2 {
+	status = "okay";
+
+	led-controller@62 {
+		compatible = "nxp,pca9633";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x62>;
+		nxp,hw-blink;
+
+		led_system_red: led@0 {
+			reg = <0>;
+			color = <LED_COLOR_ID_RED>;
+			function = LED_FUNCTION_STATUS;
+		};
+
+		led_system_green: led@1 {
+			reg = <1>;
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_STATUS;
+		};
+
+		led_system_blue: led@2 {
+			reg = <2>;
+			color = <LED_COLOR_ID_BLUE>;
+			function = LED_FUNCTION_STATUS;
+		};
+	};
+
+	rtc@68 {
+		compatible = "dallas,ds1307";
+		reg = <0x68>;
+	};
+};
+
+/*
+ * QCA4024 is not currently supported, keep for documentation purposes
+ *&blsp1_spi4 {
+ *	status = "okay";
+ *
+ *	pinctrl-0 = <&spi_3_pins &quartz_pins>;
+ *	pinctrl-names = "default";
+ *
+ *	iot@3 {
+ *		compatible = "qca,qca4024";
+ *		reg = <0>;
+ *		spi-max-frequency = <24000000>;
+ *	};
+ *};
+ */
+
+&mdio {
+	status = "okay";
+
+	pinctrl-0 = <&mdio_pins>;
+	pinctrl-names = "default";
+	reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
+
+	ethernet-phy-package@0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "qcom,qca8075-package";
+		reg = <0>;
+
+		qca8075_0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+		};
+
+		qca8075_1: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+		};
+
+		qca8075_2: ethernet-phy@2 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <2>;
+		};
+
+		qca8075_3: ethernet-phy@3 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <3>;
+		};
+
+		qca8075_4: ethernet-phy@4 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <4>;
+		};
+	};
+};
+
+&switch {
+	status = "okay";
+
+	switch_lan_bmp = <(ESS_PORT1 | ESS_PORT2 | ESS_PORT3 | ESS_PORT4)>; /* lan port bitmap */
+	switch_wan_bmp = <ESS_PORT5>; /* wan port bitmap */
+	switch_mac_mode = <MAC_MODE_PSGMII>; /* mac mode for uniphy instance0*/
+
+	qcom,port_phyinfo {
+		port@1 {
+			port_id = <1>;
+			phy_address = <0>;
+		};
+		port@2 {
+			port_id = <2>;
+			phy_address = <1>;
+		};
+		port@3 {
+			port_id = <3>;
+			phy_address = <2>;
+		};
+		port@4 {
+			port_id = <4>;
+			phy_address = <3>;
+		};
+		port@5 {
+			port_id = <5>;
+			phy_address = <4>;
+		};
+	};
+};
+
+&edma {
+	status = "okay";
+};
+
+&dp1 {
+	status = "okay";
+	phy-handle = <&qca8075_0>;
+	label = "lan1";
+};
+
+&dp2 {
+	status = "okay";
+	phy-handle = <&qca8075_1>;
+	label = "lan2";
+};
+
+&dp3 {
+	status = "okay";
+	phy-handle = <&qca8075_2>;
+	label = "lan3";
+};
+
+&dp4 {
+	status = "okay";
+	phy-handle = <&qca8075_3>;
+	label = "lan4";
+};
+
+&dp5 {
+	status = "okay";
+	phy-handle = <&qca8075_4>;
+	label = "wan";
+};
+
+&ssphy_0 {
+	status = "okay";
+};
+
+&qusb_phy_0 {
+	status = "okay";
+};
+
+&usb_0 {
+	status = "okay";
+};
+
+&pcie_qmp1 {
+	status = "okay";
+};
+
+&pcie1 {
+	status = "okay";
+
+	perst-gpio = <&tlmm 58 GPIO_ACTIVE_LOW>;
+
+	bridge@0,0 {
+		reg = <0x00000000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+
+		wifi0: wifi@1,0 {
+			status = "okay";
+
+			compatible = "qcom,ath10k";
+			reg = <0x00010000 0 0 0 0>;
+
+			qcom,ath10k-calibration-variant = "Linksys-MX5300";
+			nvmem-cell-names = "pre-calibration";
+			nvmem-cells = <&caldata_qca9984>;
+		};
+	};
+};
+
+&wifi {
+	status = "okay";
+
+	qcom,ath11k-calibration-variant = "Linksys-MX5300";
+};
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-wax218.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-wax218.dts
index 33a618851c7b43..0e71faea72a220 100644
--- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-wax218.dts
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-wax218.dts
@@ -5,6 +5,7 @@
 #include "ipq8074-ess.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/gpio/gpio.h>
 
 / {
@@ -61,12 +62,14 @@
 		compatible = "gpio-leds";
 
 		led_power_amber: led_power {
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&led_gpio 1 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_lan {
-			label = "blue:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&led_gpio 2 GPIO_ACTIVE_HIGH>;
 		};
 
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-wpq873.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-wpq873.dts
index a450fbca25ca5e..7d7f54ea62141a 100644
--- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-wpq873.dts
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-wpq873.dts
@@ -47,31 +47,26 @@
 		compatible = "gpio-leds";
 
 		led_power_red: power-red {
-			label = "red:power";
 			gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_RED>;
 		};
 
 		led_power_blue: power-blue {
-			label = "blue:power";
 			gpios = <&tlmm 43 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_BLUE>;
 		};
 
 		led_system_red: system-red {
-			label = "red:system";
 			gpios = <&tlmm 28 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_RED>;
 		};
 
 		led_system_green: system-green {
-			label = "green:system";
 			gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_GREEN>;
 		};
 
 		led_system_blue: system-blue {
-			label = "blue:system";
 			gpios = <&tlmm 19 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_BLUE>;
 		};
@@ -362,19 +357,26 @@
 	pinctrl-names = "default";
 	reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
 
-	qca8075_1: ethernet-phy@1 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <1>;
-	};
+	ethernet-phy-package@0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "qcom,qca8075-package";
+		reg = <0>;
 
-	qca8075_2: ethernet-phy@2 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <2>;
-	};
+		qca8075_1: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+		};
 
-	qca8075_3: ethernet-phy@3 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <3>;
+		qca8075_2: ethernet-phy@2 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <2>;
+		};
+
+		qca8075_3: ethernet-phy@3 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <3>;
+		};
 	};
 
 	qca8081: ethernet-phy@28 {
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-ess.dtsi b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-ess.dtsi
index d3f4211ecf9095..76838b86c579e5 100644
--- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-ess.dtsi
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-ess.dtsi
@@ -23,24 +23,6 @@
 		switch_access_mode = "local bus";
 		switch_cpu_bmp = <ESS_PORT0>;  /* cpu port bitmap */
 		switch_inner_bmp = <ESS_PORT7>; /*inner port bitmap*/
-		/* This is a special binding that controls how the malibu PHY are
-		 * init. This value reflect the PHY addr of the first malibu PHY.
-		 * Malibu PHY are in a bundle of 5 PHY.
-		 * Some device might have some port not connected.
-		 * SSDK still needs the addrs of the first PHY (even if not connected)
-		 * to correctly setup the malibu PHY.
-		 *
-		 * This is needed as previously SSDK based this on the port bmp, but
-		 * this can be problematic now that we specify correct bmp.
-		 *
-		 * Most common configuration have the malibu PHY placed at 0.
-		 * But some device might have it placed at address 16.
-		 * To drive the correct value, check the port id of the malibu PHY
-		 * and try to understand what is the first one in devices where some
-		 * port are missing. port_phyinfo is normally the way to go to derive
-		 * this value in the few special cases.
-		 */
-		malibu_first_phy_addr = <0>;
 		clocks = <&gcc GCC_CMN_12GPLL_AHB_CLK>,
 			 <&gcc GCC_CMN_12GPLL_SYS_CLK>,
 			 <&gcc GCC_UNIPHY0_AHB_CLK>,
@@ -476,7 +458,7 @@
 		reg = <0x3a001000 0x200>;
 		qcom,mactype = <0>;
 		local-mac-address = [000000000000];
-		phy-mode = "sgmii";
+		phy-mode = "psgmii";
 		status = "disabled";
 	};
 
@@ -487,7 +469,7 @@
 		reg = <0x3a001200 0x200>;
 		qcom,mactype = <0>;
 		local-mac-address = [000000000000];
-		phy-mode = "sgmii";
+		phy-mode = "psgmii";
 		status = "disabled";
 	};
 
@@ -498,7 +480,7 @@
 		reg = <0x3a001400 0x200>;
 		qcom,mactype = <0>;
 		local-mac-address = [000000000000];
-		phy-mode = "sgmii";
+		phy-mode = "psgmii";
 		status = "disabled";
 	};
 
@@ -509,7 +491,7 @@
 		reg = <0x3a001600 0x200>;
 		qcom,mactype = <0>;
 		local-mac-address = [000000000000];
-		phy-mode = "sgmii";
+		phy-mode = "psgmii";
 		status = "disabled";
 	};
 
@@ -520,7 +502,7 @@
 		reg = <0x3a001800 0x200>;
 		qcom,mactype = <0>;
 		local-mac-address = [000000000000];
-		phy-mode = "sgmii";
+		phy-mode = "psgmii";
 		status = "disabled";
 	};
 
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-nbg7815.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-nbg7815.dts
index be6953f9423a2b..ac3077b29d94df 100644
--- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-nbg7815.dts
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-nbg7815.dts
@@ -271,27 +271,34 @@
 	pinctrl-names = "default";
 	reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
 
-	qca8075_1: ethernet-phy@0 {
-		compatible = "ethernet-phy-ieee802.3-c22";
+	ethernet-phy-package@0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "qcom,qca8075-package";
 		reg = <0>;
-	};
 
-	qca8075_2: ethernet-phy@1 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <1>;
-	};
+		qca8075_0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+		};
 
-	qca8075_3: ethernet-phy@2 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <2>;
-	};
+		qca8075_1: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+		};
+
+		qca8075_2: ethernet-phy@2 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <2>;
+		};
 
-	qca8075_4: ethernet-phy@3 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <3>;
+		qca8075_3: ethernet-phy@3 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <3>;
+		};
 	};
 
-	qca8081: ethernet-phy@4{
+	qca8081: ethernet-phy@28 {
 		compatible = "ethernet-phy-id004d.d101";
 		reg = <28>;
 		reset-deassert-us = <10000>;
@@ -358,7 +365,7 @@
 
 &dp1 {
 	status = "okay";
-	phy-handle = <&qca8075_1>;
+	phy-handle = <&qca8075_0>;
 	label = "lan1";
 	nvmem-cells = <&macaddr_lan 0>;
 	nvmem-cell-names = "mac-address";
@@ -366,7 +373,7 @@
 
 &dp2 {
 	status = "okay";
-	phy-handle = <&qca8075_2>;
+	phy-handle = <&qca8075_1>;
 	label = "lan2";
 	nvmem-cells = <&macaddr_lan 0>;
 	nvmem-cell-names = "mac-address";
@@ -374,7 +381,7 @@
 
 &dp3 {
 	status = "okay";
-	phy-handle = <&qca8075_3>;
+	phy-handle = <&qca8075_2>;
 	label = "lan3";
 	nvmem-cells = <&macaddr_lan 0>;
 	nvmem-cell-names = "mac-address";
@@ -382,7 +389,7 @@
 
 &dp4 {
 	status = "okay";
-	phy-handle = <&qca8075_4>;
+	phy-handle = <&qca8075_3>;
 	label = "lan4";
 	nvmem-cells = <&macaddr_lan 0>;
 	nvmem-cell-names = "mac-address";
@@ -398,6 +405,7 @@
 
 &dp6_syn {
 	status = "okay";
+	phy-mode = "usxgmii";
 	phy-handle = <&aqr113c>;
 	label = "10g";
 	nvmem-cells = <&macaddr_lan 0>;
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-rax120v2.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-rax120v2.dts
index 0949d19171a6cf..0be50603ba5946 100644
--- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-rax120v2.dts
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-rax120v2.dts
@@ -72,63 +72,53 @@
 		compatible = "gpio-leds";
 
 		led_system_white: system-white {
-			label = "white:system";
 			gpios = <&led_gpio 0 GPIO_ACTIVE_LOW>;
 			color = <LED_COLOR_ID_WHITE>;
 		};
 
 		led_24g_white {
-			label = "white:24g";
 			gpios = <&led_gpio 1 GPIO_ACTIVE_LOW>;
 			color = <LED_COLOR_ID_WHITE>;
 			linux,default-trigger = "phy1radio";
 		};
 
 		led_5g_white {
-			label = "white:5g";
 			gpios = <&led_gpio 2 GPIO_ACTIVE_LOW>;
 			color = <LED_COLOR_ID_WHITE>;
 			linux,default-trigger = "phy0radio";
 		};
 
 		led_usb1_white {
-			label = "white:usb1";
 			gpios = <&led_gpio 3 GPIO_ACTIVE_LOW>;
 			color = <LED_COLOR_ID_WHITE>;
 		};
 
 		led_usb2_white {
-			label = "white:usb2";
 			gpios = <&led_gpio 4 GPIO_ACTIVE_LOW>;
 			color = <LED_COLOR_ID_WHITE>;
 		};
 
 		led_wan_white: wan-white {
-			label = "white:wan";
 			gpios = <&led_gpio 5 GPIO_ACTIVE_LOW>;
 			color = <LED_COLOR_ID_WHITE>;
 		};
 
 		led_aqr_green {
-			label = "green:aqr";
 			gpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;
 			color = <LED_COLOR_ID_GREEN>;
 		};
 
 		led_aqr_red {
-			label = "red:aqr";
 			gpios = <&led_gpio 10 GPIO_ACTIVE_LOW>;
 			color = <LED_COLOR_ID_RED>;
 		};
 
 		led_aqr_white {
-			label = "white:aqr";
 			gpios = <&led_gpio 11 GPIO_ACTIVE_LOW>;
 			color = <LED_COLOR_ID_WHITE>;
 		};
 
 		led_wps_white {
-			label = "white:wps";
 			gpios = <&tlmm 40 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_WHITE>;
 		};
@@ -160,29 +150,37 @@
 	pinctrl-names = "default";
 	reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
 
-	qca8075_0: ethernet-phy@0 {
-		compatible = "ethernet-phy-ieee802.3-c22";
+	ethernet-phy-package@0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
 		reg = <0>;
-	};
 
-	qca8075_1: ethernet-phy@1 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <1>;
-	};
+		compatible = "qcom,qca8075-package";
 
-	qca8075_2: ethernet-phy@2 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <2>;
-	};
+		qca8075_0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+		};
 
-	qca8075_3: ethernet-phy@3 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <3>;
-	};
+		qca8075_1: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+		};
+
+		qca8075_2: ethernet-phy@2 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <2>;
+		};
 
-	qca8075_4: ethernet-phy@4 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <4>;
+		qca8075_3: ethernet-phy@3 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <3>;
+		};
+
+		qca8075_4: ethernet-phy@4 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <4>;
+		};
 	};
 
 	aqr111b0: ethernet-phy@7 {
@@ -276,6 +274,7 @@
 
 &dp6_syn {
 	status = "okay";
+	phy-mode = "usxgmii";
 	phy-handle = <&aqr111b0>;
 	label = "lan5";
 	nvmem-cells = <&macaddr_dp6_syn>;
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-wax630.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-wax630.dts
index 48b1fee1ea543b..35f0c3e220c456 100644
--- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-wax630.dts
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-wax630.dts
@@ -153,7 +153,7 @@
 
 	switch_lan_bmp = <(ESS_PORT4 | ESS_PORT6)>;
 	switch_mac_mode = <MAC_MODE_PSGMII>;
-	switch_mac_mode2 = <MAC_MODE_USXGMII>;
+	switch_mac_mode2 = <MAC_MODE_SGMII_PLUS>;
 
 	qcom,port_phyinfo {
 		port@4 {
@@ -194,9 +194,16 @@
 	pinctrl-names = "default";
 	reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
 
-	qca8075: ethernet-phy@3 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <3>;
+	ethernet-phy-package@0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "qcom,qca8075-package";
+		reg = <0>;
+
+		qca8075_3: ethernet-phy@3 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <3>;
+		};
 	};
 
 	qca8081: ethernet-phy@28 {
@@ -209,7 +216,7 @@
 
 &dp4 {
 	status = "okay";
-	phy-handle = <&qca8075>;
+	phy-handle = <&qca8075_3>;
 	label = "lan2";
 };
 
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-wxr-5950ax12.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-wxr-5950ax12.dts
index 325a391ca0605e..d6411e4fa5ec5f 100644
--- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-wxr-5950ax12.dts
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-wxr-5950ax12.dts
@@ -31,52 +31,44 @@
 		compatible = "gpio-leds";
 
 		led-0 {
-			label = "white:router";
 			gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_WHITE>;
 		};
 
 		led-1 {
-			label = "red:router";
 			gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_RED>;
 		};
 
 		led_power_red: led-2 {
-			label = "red:power";
 			gpios = <&tlmm 31 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_RED>;
 			function = LED_FUNCTION_POWER;
 		};
 
 		led_power_white: led-3 {
-			label = "white:power";
 			gpios = <&tlmm 34 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_WHITE>;
 			function = LED_FUNCTION_POWER;
 		};
 
 		led-4 {
-			label = "white:internet";
 			gpios = <&tlmm 43 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_WHITE>;
 		};
 
 		led-5 {
-			label = "red:internet";
 			gpios = <&tlmm 44 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_RED>;
 		};
 
 		led-6 {
-			label = "red:wireless";
 			gpios = <&tlmm 55 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_RED>;
 			function = LED_FUNCTION_WLAN;
 		};
 
 		led-7 {
-			label = "white:wireless";
 			gpios = <&tlmm 56 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_WHITE>;
 			function = LED_FUNCTION_WLAN;
@@ -238,48 +230,41 @@
 		reg = <0x8>;
 	};
 
-	qca8075_1: ethernet-phy@18 {
-		compatible = "ethernet-phy-ieee802.3-c22";
+	ethernet-phy-package@17 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "qcom,qca8075-package";
 		reg = <0x18>;
-	};
 
-	qca8075_2: ethernet-phy@19 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <0x19>;
-	};
+		qcom,package-mode = "qsgmii";
 
-	qca8075_3: ethernet-phy@1a {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <0x1a>;
-	};
+		qca8075_1: ethernet-phy@19 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0x19>;
+		};
 
-	qca8075_4: ethernet-phy@1b {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <0x1b>;
-	};
+		qca8075_2: ethernet-phy@1a {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0x1a>;
+		};
 
-	qca8075_5: ethernet-phy@1c {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <0x1c>;
+		qca8075_3: ethernet-phy@1b {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0x1b>;
+		};
 	};
 };
 
 &switch {
 	status = "okay";
 
-	switch_lan_bmp = <(ESS_PORT1 | ESS_PORT2 | ESS_PORT3 | ESS_PORT4 | ESS_PORT5)>;
-	switch_wan_bmp = <ESS_PORT6>;
-	malibu_first_phy_addr = <0x18>;
+	switch_lan_bmp = <(ESS_PORT2 | ESS_PORT3 | ESS_PORT4 | ESS_PORT6)>;
+	switch_wan_bmp = <ESS_PORT5>;
 	switch_mac_mode = <MAC_MODE_QSGMII>;
 	switch_mac_mode1 = <MAC_MODE_USXGMII>;
 	switch_mac_mode2 = <MAC_MODE_USXGMII>;
 
 	qcom,port_phyinfo {
-		port@1 {
-			port_id = <1>;
-			phy_address = <0x18>;
-		};
-
 		port@2 {
 			port_id = <2>;
 			phy_address = <0x19>;
@@ -315,7 +300,8 @@
 
 &dp2 {
 	status = "okay";
-	phy-handle = <&qca8075_2>;
+	phy-mode = "qsgmii";
+	phy-handle = <&qca8075_1>;
 	label = "lan4";
 	nvmem-cells = <&macaddr_appsblenv_ethaddr>;
 	nvmem-cell-names = "mac-address";
@@ -323,7 +309,8 @@
 
 &dp3 {
 	status = "okay";
-	phy-handle = <&qca8075_3>;
+	phy-mode = "qsgmii";
+	phy-handle = <&qca8075_2>;
 	label = "lan3";
 	nvmem-cells = <&macaddr_appsblenv_ethaddr>;
 	nvmem-cell-names = "mac-address";
@@ -331,7 +318,8 @@
 
 &dp4 {
 	status = "okay";
-	phy-handle = <&qca8075_4>;
+	phy-mode = "qsgmii";
+	phy-handle = <&qca8075_3>;
 	label = "lan2";
 	nvmem-cells = <&macaddr_appsblenv_ethaddr>;
 	nvmem-cell-names = "mac-address";
@@ -339,6 +327,7 @@
 
 &dp5_syn {
 	status = "okay";
+	phy-mode = "usxgmii";
 	phy-handle = <&aqr113c_1>;
 	label = "wan";
 	nvmem-cells = <&macaddr_appsblenv_ethaddr>;
@@ -347,6 +336,7 @@
 
 &dp6_syn {
 	status = "okay";
+	phy-mode = "usxgmii";
 	phy-handle = <&aqr113c_2>;
 	label = "lan1";
 	nvmem-cells = <&macaddr_appsblenv_ethaddr>;
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8174-mx4200.dtsi b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8174-mx4200.dtsi
index ef67742c035b24..13ce8d16016860 100644
--- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8174-mx4200.dtsi
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8174-mx4200.dtsi
@@ -350,24 +350,31 @@
 	pinctrl-names = "default";
 	reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
 
-	qca8075_1: ethernet-phy@1 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <1>;
-	};
+	ethernet-phy-package@0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "qcom,qca8075-package";
+		reg = <0>;
 
-	qca8075_2: ethernet-phy@2 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <2>;
-	};
+		qca8075_1: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+		};
 
-	qca8075_3: ethernet-phy@3 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <3>;
-	};
+		qca8075_2: ethernet-phy@2 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <2>;
+		};
 
-	qca8075_4: ethernet-phy@4 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <4>;
+		qca8075_3: ethernet-phy@3 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <3>;
+		};
+
+		qca8075_4: ethernet-phy@4 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <4>;
+		};
 	};
 };
 
diff --git a/target/linux/qualcommax/image/Makefile b/target/linux/qualcommax/image/Makefile
index f59ad0c15fdb1c..c12fc97807544e 100644
--- a/target/linux/qualcommax/image/Makefile
+++ b/target/linux/qualcommax/image/Makefile
@@ -12,6 +12,30 @@ define Device/Default
 	IMAGE/sysupgrade.bin/squashfs :=
 endef
 
+define Device/FitImage
+	KERNEL_SUFFIX := -uImage.itb
+	KERNEL = kernel-bin | libdeflate-gzip | fit gzip $$(KDIR)/image-$$(DEVICE_DTS).dtb
+	KERNEL_NAME := Image
+endef
+
+define Device/FitImageLzma
+	KERNEL_SUFFIX := -uImage.itb
+	KERNEL = kernel-bin | lzma | fit lzma $$(KDIR)/image-$$(DEVICE_DTS).dtb
+	KERNEL_NAME := Image
+endef
+
+define Device/EmmcImage
+	IMAGES += factory.bin
+	IMAGE/factory.bin := append-rootfs | pad-rootfs | pad-to 64k
+	IMAGE/sysupgrade.bin/squashfs := append-rootfs | pad-to 64k | sysupgrade-tar rootfs=$$$$@ | append-metadata
+endef
+
+define Device/UbiFit
+	KERNEL_IN_UBI := 1
+	IMAGES += factory.ubi
+	IMAGE/factory.ubi := append-ubi
+endef
+
 include $(SUBTARGET).mk
 
 $(eval $(call BuildImage))
diff --git a/target/linux/qualcommax/image/ipq60xx.mk b/target/linux/qualcommax/image/ipq60xx.mk
new file mode 100644
index 00000000000000..00dead93ad1f29
--- /dev/null
+++ b/target/linux/qualcommax/image/ipq60xx.mk
@@ -0,0 +1,12 @@
+define Device/8devices_mango-dvk
+	$(call Device/FitImageLzma)
+	DEVICE_VENDOR := 8devices
+	DEVICE_MODEL := Mango-DVK
+	IMAGE_SIZE := 27776k
+	BLOCKSIZE := 64k
+	SOC := ipq6010
+	SUPPORTED_DEVICES += 8devices,mango
+	IMAGE/sysupgrade.bin := append-kernel | pad-to 64k | append-rootfs | pad-rootfs | check-size | append-metadata
+	DEVICE_PACKAGES := ipq-wifi-8devices_mango
+endef
+TARGET_DEVICES += 8devices_mango-dvk
diff --git a/target/linux/qualcommax/image/ipq807x.mk b/target/linux/qualcommax/image/ipq807x.mk
index f5f0e261405b42..74fe15a9978d1b 100644
--- a/target/linux/qualcommax/image/ipq807x.mk
+++ b/target/linux/qualcommax/image/ipq807x.mk
@@ -1,28 +1,3 @@
-define Device/FitImage
-	KERNEL_SUFFIX := -uImage.itb
-	KERNEL = kernel-bin | libdeflate-gzip | fit gzip $$(KDIR)/image-$$(DEVICE_DTS).dtb
-	KERNEL_NAME := Image
-endef
-
-define Device/FitImageLzma
-	KERNEL_SUFFIX := -uImage.itb
-	KERNEL = kernel-bin | lzma | fit lzma $$(KDIR)/image-$$(DEVICE_DTS).dtb
-	KERNEL_NAME := Image
-endef
-
-define Device/EmmcImage
-	IMAGES += factory.bin sysupgrade.bin
-	IMAGE/factory.bin := append-rootfs | pad-rootfs | pad-to 64k
-	IMAGE/sysupgrade.bin/squashfs := append-rootfs | pad-to 64k | sysupgrade-tar rootfs=$$$$@ | append-metadata
-endef
-
-define Device/UbiFit
-	KERNEL_IN_UBI := 1
-	IMAGES := factory.ubi sysupgrade.bin
-	IMAGE/factory.ubi := append-ubi
-	IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
-endef
-
 define Build/wax6xx-netgear-tar
 	mkdir $@.tmp
 	mv $@ $@.tmp/nand-ipq807x-apps.img
@@ -55,12 +30,25 @@ define Device/buffalo_wxr-5950ax12
 	PAGESIZE := 2048
 	DEVICE_DTS_CONFIG := config@hk01
 	SOC := ipq8074
-	IMAGES := sysupgrade.bin
-	IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
 	DEVICE_PACKAGES := ipq-wifi-buffalo_wxr-5950ax12
 endef
 TARGET_DEVICES += buffalo_wxr-5950ax12
 
+define Device/cmcc_rm2-6
+	$(call Device/FitImage)
+	$(call Device/UbiFit)
+	DEVICE_VENDOR := CMCC
+	DEVICE_MODEL := RM2-6
+	BLOCKSIZE := 128k
+	PAGESIZE := 2048
+	DEVICE_DTS_CONFIG := config@ac02
+	SOC := ipq8070
+	IMAGES += factory.bin
+	IMAGE/factory.bin := append-ubi | qsdk-ipq-factory-nand
+	DEVICE_PACKAGES := ipq-wifi-cmcc_rm2-6 kmod-hwmon-gpiofan
+endef
+TARGET_DEVICES += cmcc_rm2-6
+
 define Device/compex_wpq873
 	$(call Device/FitImage)
 	$(call Device/UbiFit)
@@ -117,7 +105,6 @@ TARGET_DEVICES += edimax_cax1800
 
 define Device/linksys_mx4200v1
 	$(call Device/FitImage)
-	$(call Device/UbiFit)
 	DEVICE_VENDOR := Linksys
 	DEVICE_MODEL := MX4200
 	DEVICE_VARIANT := v1
@@ -126,7 +113,6 @@ define Device/linksys_mx4200v1
 	KERNEL_SIZE := 6144k
 	IMAGE_SIZE := 147456k
 	NAND_SIZE := 512m
-	KERNEL_IN_UBI :=
 	SOC := ipq8174
 	IMAGES += factory.bin
 	IMAGE/factory.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi | linksys-image type=MX4200
@@ -140,6 +126,23 @@ define Device/linksys_mx4200v2
 endef
 TARGET_DEVICES += linksys_mx4200v2
 
+define Device/linksys_mx5300
+	$(call Device/FitImage)
+	DEVICE_VENDOR := Linksys
+	DEVICE_MODEL := MX5300
+	BLOCKSIZE := 128k
+	PAGESIZE := 2048
+	KERNEL_SIZE := 6144k
+	IMAGE_SIZE := 147456k
+	NAND_SIZE := 512m
+	SOC := ipq8072
+	IMAGES += factory.bin
+	IMAGE/factory.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi | linksys-image type=MX5300
+	DEVICE_PACKAGES := kmod-leds-pca963x kmod-rtc-ds1307 \
+		ipq-wifi-linksys_mx5300 kmod-ath10k-ct ath10k-firmware-qca9984-ct
+endef
+TARGET_DEVICES += linksys_mx5300
+
 define Device/netgear_rax120v2
 	$(call Device/FitImage)
 	$(call Device/UbiFit)
@@ -154,7 +157,7 @@ define Device/netgear_rax120v2
 	NETGEAR_HW_ID := 29765589+0+512+1024+4x4+8x8
 	DEVICE_PACKAGES := ipq-wifi-netgear_rax120v2 kmod-spi-gpio \
 		kmod-spi-bitbang kmod-gpio-nxp-74hc164 kmod-hwmon-g761
-	IMAGES = web-ui-factory.img sysupgrade.bin
+	IMAGES += web-ui-factory.img
 	IMAGE/web-ui-factory.img := append-image initramfs-uImage.itb | \
 		pad-offset $$$$(BLOCKSIZE) 64 | append-uImage-fakehdr filesystem | \
 		netgear-dni
@@ -192,7 +195,7 @@ define Device/netgear_wax620
 	BLOCKSIZE := 128k
 	PAGESIZE := 2048
 	SOC := ipq8072
-	DEVICE_PACKAGES += kmod-spi-gpio kmod-gpio-nxp-74hc164 \
+	DEVICE_PACKAGES := kmod-spi-gpio kmod-gpio-nxp-74hc164 \
 		ipq-wifi-netgear_wax620
 endef
 TARGET_DEVICES += netgear_wax620
@@ -206,9 +209,9 @@ define Device/netgear_wax630
 	BLOCKSIZE := 128k
 	PAGESIZE := 2048
 	SOC := ipq8074
-	IMAGES := ui-factory.tar factory.ubi sysupgrade.bin
+	IMAGES += ui-factory.tar
 	IMAGE/ui-factory.tar := append-ubi | wax6xx-netgear-tar
-	DEVICE_PACKAGES += kmod-spi-gpio ipq-wifi-netgear_wax630
+	DEVICE_PACKAGES := kmod-spi-gpio ipq-wifi-netgear_wax630
 endef
 TARGET_DEVICES += netgear_wax630
 
@@ -219,7 +222,7 @@ define Device/prpl_haze
 	DEVICE_MODEL := Haze
 	DEVICE_DTS_CONFIG := config@hk09
 	SOC := ipq8072
-	DEVICE_PACKAGES += ath11k-firmware-qcn9074 ipq-wifi-prpl_haze kmod-ath11k-pci \
+	DEVICE_PACKAGES := ath11k-firmware-qcn9074 ipq-wifi-prpl_haze kmod-ath11k-pci \
 		mkf2fs f2fsck kmod-fs-f2fs kmod-leds-lp5562
 endef
 TARGET_DEVICES += prpl_haze
@@ -232,7 +235,7 @@ define Device/qnap_301w
 	DEVICE_DTS_CONFIG := config@hk01
 	KERNEL_SIZE := 16384k
 	SOC := ipq8072
-	DEVICE_PACKAGES += ipq-wifi-qnap_301w
+	DEVICE_PACKAGES := ipq-wifi-qnap_301w
 endef
 TARGET_DEVICES += qnap_301w
 
@@ -273,7 +276,7 @@ define Device/xiaomi_ax9000
 	SOC := ipq8072
 	KERNEL_SIZE := 57344k
 	DEVICE_PACKAGES := ipq-wifi-xiaomi_ax9000 kmod-ath11k-pci ath11k-firmware-qcn9074 \
-	kmod-ath10k-ct ath10k-firmware-qca9887-ct
+		kmod-ath10k-ct ath10k-firmware-qca9887-ct
 ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),)
 	ARTIFACTS := initramfs-factory.ubi
 	ARTIFACT/initramfs-factory.ubi := append-image-stage initramfs-uImage.itb | ubinize-kernel
@@ -317,7 +320,7 @@ define Device/zyxel_nbg7815
 	DEVICE_MODEL := NBG7815
 	DEVICE_DTS_CONFIG := config@nbg7815
 	SOC := ipq8074
-	DEVICE_PACKAGES += ipq-wifi-zyxel_nbg7815 kmod-ath11k-pci \
+	DEVICE_PACKAGES := ipq-wifi-zyxel_nbg7815 kmod-ath11k-pci \
 		kmod-bluetooth kmod-hwmon-tmp103
 endef
 TARGET_DEVICES += zyxel_nbg7815
diff --git a/target/linux/qualcommax/ipq60xx/base-files/etc/board.d/02_network b/target/linux/qualcommax/ipq60xx/base-files/etc/board.d/02_network
new file mode 100644
index 00000000000000..081d894e1eed39
--- /dev/null
+++ b/target/linux/qualcommax/ipq60xx/base-files/etc/board.d/02_network
@@ -0,0 +1,28 @@
+#
+# Copyright (c) 2015 The Linux Foundation. All rights reserved.
+# Copyright (c) 2011-2015 OpenWrt.org
+#
+
+. /lib/functions/uci-defaults.sh
+. /lib/functions/system.sh
+
+ipq60xx_setup_interfaces()
+{
+	local board="$1"
+
+	case "$board" in
+	8devices,mango-dvk)
+		ucidef_set_interfaces_lan_wan "lan1 lan2" "wan"
+		;;
+	*)
+		echo "Unsupported hardware. Network interfaces not initialized"
+		;;
+	esac
+}
+
+board_config_update
+board=$(board_name)
+ipq60xx_setup_interfaces $board
+board_config_flush
+
+exit 0
diff --git a/target/linux/qualcommax/ipq60xx/base-files/etc/hotplug.d/firmware/11-ath11-caldata b/target/linux/qualcommax/ipq60xx/base-files/etc/hotplug.d/firmware/11-ath11-caldata
new file mode 100644
index 00000000000000..c14722c799c430
--- /dev/null
+++ b/target/linux/qualcommax/ipq60xx/base-files/etc/hotplug.d/firmware/11-ath11-caldata
@@ -0,0 +1,20 @@
+#!/bin/sh
+
+[ -e /lib/firmware/$FIRMWARE ] && exit 0
+
+. /lib/functions/caldata.sh
+
+board=$(board_name)
+
+case "$FIRMWARE" in
+"ath11k/IPQ6018/hw1.0/cal-ahb-c000000.wifi.bin")
+	case "$board" in
+	8devices,mango-dvk)
+		caldata_extract "0:ART" 0x1000 0x20000
+		;;
+	esac
+	;;
+*)
+	exit 1
+	;;
+esac
diff --git a/target/linux/qualcommax/ipq60xx/base-files/lib/upgrade/platform.sh b/target/linux/qualcommax/ipq60xx/base-files/lib/upgrade/platform.sh
new file mode 100644
index 00000000000000..3d3c17b3b90d16
--- /dev/null
+++ b/target/linux/qualcommax/ipq60xx/base-files/lib/upgrade/platform.sh
@@ -0,0 +1,17 @@
+PART_NAME=firmware
+REQUIRE_IMAGE_METADATA=1
+
+RAMFS_COPY_BIN='fw_printenv fw_setenv head'
+RAMFS_COPY_DATA='/etc/fw_env.config /var/lock/fw_printenv.lock'
+
+platform_check_image() {
+	return 0;
+}
+
+platform_do_upgrade() {
+	case "$(board_name)" in
+	*)
+		default_do_upgrade "$1"
+		;;
+	esac
+}
diff --git a/target/linux/qualcommax/ipq60xx/config-default b/target/linux/qualcommax/ipq60xx/config-default
new file mode 100644
index 00000000000000..9ce4b04293900f
--- /dev/null
+++ b/target/linux/qualcommax/ipq60xx/config-default
@@ -0,0 +1,11 @@
+CONFIG_IPQ_GCC_6018=y
+CONFIG_MTD_SPLIT_FIT_FW=y
+CONFIG_PINCTRL_IPQ6018=y
+CONFIG_QCOM_APM=y
+# CONFIG_QCOM_CLK_SMD_RPM is not set
+# CONFIG_QCOM_RPMPD is not set
+CONFIG_QCOM_SMD_RPM=y
+CONFIG_REGULATOR_CPR3=y
+# CONFIG_REGULATOR_CPR3_NPU is not set
+CONFIG_REGULATOR_CPR4_APSS=y
+CONFIG_REGULATOR_QCOM_SMD_RPM=y
diff --git a/target/linux/qualcommax/ipq60xx/target.mk b/target/linux/qualcommax/ipq60xx/target.mk
new file mode 100644
index 00000000000000..dc3a2ceff607b7
--- /dev/null
+++ b/target/linux/qualcommax/ipq60xx/target.mk
@@ -0,0 +1,8 @@
+SUBTARGET:=ipq60xx
+FEATURES += source-only
+BOARDNAME:=Qualcomm Atheros IPQ60xx
+DEFAULT_PACKAGES += ath11k-firmware-ipq6018
+
+define Target/Description
+	Build firmware images for Qualcomm Atheros IPQ60xx based boards.
+endef
diff --git a/target/linux/qualcommax/ipq807x/base-files/etc/board.d/01_leds b/target/linux/qualcommax/ipq807x/base-files/etc/board.d/01_leds
index f3e67311c3acf3..d6f5db7093f529 100644
--- a/target/linux/qualcommax/ipq807x/base-files/etc/board.d/01_leds
+++ b/target/linux/qualcommax/ipq807x/base-files/etc/board.d/01_leds
@@ -9,6 +9,7 @@ case "$board" in
 arcadyan,aw1000)
 	ucidef_set_led_netdev "5g" "5G" "green:5g" "wwan0"
 	ucidef_set_led_netdev "wan" "WAN" "green:internet" "wan"
+	ucidef_set_led_netdev "wan-port-link" "WAN-PORT-LINK" "90000.mdio-1:1c:green:wan" "wan" "tx rx link_10 link_100 link_1000 link_2500"
 	;;
 dynalink,dl-wrx36)
 	ucidef_set_led_netdev "wan-port-link-green" "WAN-PORT-LINK-GREEN" "90000.mdio-1:1c:green:wan" "wan" "link_2500"
@@ -32,12 +33,22 @@ netgear,wax630)
 	ucidef_set_led_netdev "lan1" "LAN1" "lan1:green" "lan1"
 	ucidef_set_led_netdev "lan2" "LAN2" "lan2:green" "lan2"
 	;;
-redmi,ax6|\
+redmi,ax6)
+	ucidef_set_led_netdev "wan" "WAN" "blue:network" "wan"
+	;;
 xiaomi,ax3600)
+	ucidef_set_led_netdev "wan-port-link" "WAN-PORT-LINK" "90000.mdio-1:01:green:wan" "wan" "tx rx link_10 link_100 link_1000"
+	ucidef_set_led_netdev "lan1-port-link" "LAN1-PORT-LINK" "90000.mdio-1:02:green:lan" "lan1" "tx rx link_10 link_100 link_1000"
+	ucidef_set_led_netdev "lan2-port-link" "LAN2-PORT-LINK" "90000.mdio-1:03:green:lan" "lan2" "tx rx link_10 link_100 link_1000"
+	ucidef_set_led_netdev "lan3-port-link" "LAN3-PORT-LINK" "90000.mdio-1:04:green:lan" "lan3" "tx rx link_10 link_100 link_1000"
 	ucidef_set_led_netdev "wan" "WAN" "blue:network" "wan"
 	;;
 xiaomi,ax9000)
 	ucidef_set_led_netdev "wan-port-link" "WAN-PORT-LINK" "90000.mdio-1:18:green:wan" "wan" "tx rx link_10 link_100 link_1000 link_2500"
+	ucidef_set_led_netdev "lan1-port-link" "LAN1-PORT-LINK" "90000.mdio-1:03:green:lan" "lan1" "tx rx link_10 link_100 link_1000"
+	ucidef_set_led_netdev "lan2-port-link" "LAN2-PORT-LINK" "90000.mdio-1:02:green:lan" "lan2" "tx rx link_10 link_100 link_1000"
+	ucidef_set_led_netdev "lan3-port-link" "LAN3-PORT-LINK" "90000.mdio-1:01:green:lan" "lan3" "tx rx link_10 link_100 link_1000"
+	ucidef_set_led_netdev "lan4-port-link" "LAN4-PORT-LINK" "90000.mdio-1:00:green:lan" "lan4" "tx rx link_10 link_100 link_1000"
 	;;
 qnap,301w)
 	ucidef_set_led_netdev "lan1" "LAN1" "green:lan1" "lan1"
diff --git a/target/linux/qualcommax/ipq807x/base-files/etc/board.d/02_network b/target/linux/qualcommax/ipq807x/base-files/etc/board.d/02_network
index f38c4b6698446e..fb3fec6fc97ea6 100644
--- a/target/linux/qualcommax/ipq807x/base-files/etc/board.d/02_network
+++ b/target/linux/qualcommax/ipq807x/base-files/etc/board.d/02_network
@@ -14,12 +14,17 @@ ipq807x_setup_interfaces()
 	arcadyan,aw1000|\
 	buffalo,wxr-5950ax12|\
 	dynalink,dl-wrx36|\
+	linksys,mx5300|\
 	xiaomi,ax9000)
 		ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" "wan"
 		;;
+	cmcc,rm2-6)
+		ucidef_set_interfaces_lan_wan "lan plc" "wan"
+		;;
 	compex,wpq873|\
 	linksys,mx4200v1|\
 	linksys,mx4200v2|\
+	prpl,haze|\
 	redmi,ax6|\
 	xiaomi,ax3600)
 		ucidef_set_interfaces_lan_wan "lan1 lan2 lan3" "wan"
@@ -42,9 +47,6 @@ ipq807x_setup_interfaces()
 	netgear,wax630)
 		ucidef_set_interface_lan "lan1 lan2" "dhcp"
 		;;
-	prpl,haze)
-		ucidef_set_interfaces_lan_wan "lan1 lan2 lan3" "wan"
-		;;
 	qnap,301w)
 		ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 10g-2" "10g-1"
 		;;
diff --git a/target/linux/qualcommax/ipq807x/base-files/etc/hotplug.d/firmware/11-ath11k-caldata b/target/linux/qualcommax/ipq807x/base-files/etc/hotplug.d/firmware/11-ath11k-caldata
index 85d107079ee50b..88ba972407fa6a 100644
--- a/target/linux/qualcommax/ipq807x/base-files/etc/hotplug.d/firmware/11-ath11k-caldata
+++ b/target/linux/qualcommax/ipq807x/base-files/etc/hotplug.d/firmware/11-ath11k-caldata
@@ -11,12 +11,14 @@ case "$FIRMWARE" in
 	case "$board" in
 	arcadyan,aw1000|\
 	buffalo,wxr-5950ax12|\
+	cmcc,rm2-6|\
 	compex,wpq873|\
 	dynalink,dl-wrx36|\
 	edgecore,eap102|\
 	edimax,cax1800|\
 	linksys,mx4200v1|\
 	linksys,mx4200v2|\
+	linksys,mx5300|\
 	netgear,rax120v2|\
 	netgear,wax218|\
 	netgear,wax620|\
diff --git a/target/linux/qualcommax/ipq807x/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac b/target/linux/qualcommax/ipq807x/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac
index 343e42d6346e1e..500f01c31f13cd 100644
--- a/target/linux/qualcommax/ipq807x/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac
+++ b/target/linux/qualcommax/ipq807x/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac
@@ -18,6 +18,11 @@ case "$board" in
 		[ "$PHYNBR" = "0" ] && macaddr_add $(get_mac_label)  8 > /sys${DEVPATH}/macaddress
 		[ "$PHYNBR" = "1" ] && macaddr_add $(get_mac_label) 16 > /sys${DEVPATH}/macaddress
 		;;
+	cmcc,rm2-6|\
+	zte,mf269)
+		[ "$PHYNBR" = "0" ] && macaddr_add $(get_mac_label) 2 > /sys${DEVPATH}/macaddress
+		[ "$PHYNBR" = "1" ] && macaddr_add $(get_mac_label) 3 > /sys${DEVPATH}/macaddress
+		;;
 	linksys,mx4200v1|\
 	linksys,mx4200v2)
 		label_mac=$(mtd_get_mac_ascii devinfo hw_mac_addr)
@@ -25,8 +30,4 @@ case "$board" in
 		[ "$PHYNBR" = "1" ] && macaddr_add $label_mac 1 > /sys${DEVPATH}/macaddress
 		[ "$PHYNBR" = "2" ] && macaddr_add $label_mac 3 > /sys${DEVPATH}/macaddress
 		;;
-	zte,mf269)
-		[ "$PHYNBR" = "0" ] && macaddr_add $(get_mac_label) 2 > /sys${DEVPATH}/macaddress
-		[ "$PHYNBR" = "1" ] && macaddr_add $(get_mac_label) 3 > /sys${DEVPATH}/macaddress
-		;;
 esac
diff --git a/target/linux/qualcommax/ipq807x/base-files/etc/init.d/bootcount b/target/linux/qualcommax/ipq807x/base-files/etc/init.d/bootcount
index f5f6c909e9b424..3e81caf63f2e47 100755
--- a/target/linux/qualcommax/ipq807x/base-files/etc/init.d/bootcount
+++ b/target/linux/qualcommax/ipq807x/base-files/etc/init.d/bootcount
@@ -11,7 +11,8 @@ boot() {
 		fw_setenv changed
 	;;
 	linksys,mx4200v1|\
-	linksys,mx4200v2)
+	linksys,mx4200v2|\
+	linksys,mx5300)
 		mtd resetbc s_env || true
 	;;
 	esac
diff --git a/target/linux/qualcommax/ipq807x/base-files/lib/upgrade/platform.sh b/target/linux/qualcommax/ipq807x/base-files/lib/upgrade/platform.sh
index 78842e1c4d3035..bffca41e020f47 100644
--- a/target/linux/qualcommax/ipq807x/base-files/lib/upgrade/platform.sh
+++ b/target/linux/qualcommax/ipq807x/base-files/lib/upgrade/platform.sh
@@ -44,6 +44,7 @@ platform_pre_upgrade() {
 platform_do_upgrade() {
 	case "$(board_name)" in
 	arcadyan,aw1000|\
+	cmcc,rm2-6|\
 	compex,wpq873|\
 	dynalink,dl-wrx36|\
 	edimax,cax1800|\
@@ -74,7 +75,8 @@ platform_do_upgrade() {
 		nand_do_upgrade "$1"
 		;;
 	linksys,mx4200v1|\
-	linksys,mx4200v2)
+	linksys,mx4200v2|\
+	linksys,mx5300)
 		boot_part="$(fw_printenv -n boot_part)"
 		if [ "$boot_part" -eq "1" ]; then
 			fw_setenv boot_part 2
diff --git a/target/linux/qualcommax/patches-6.1/0008-v6.2-arm64-dts-qcom-ipq6018-fix-NAND-node-name.patch b/target/linux/qualcommax/patches-6.1/0008-v6.2-arm64-dts-qcom-ipq6018-fix-NAND-node-name.patch
new file mode 100644
index 00000000000000..a87ae4b8ad0e46
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.1/0008-v6.2-arm64-dts-qcom-ipq6018-fix-NAND-node-name.patch
@@ -0,0 +1,28 @@
+From 8857b0ab6a562c473c5bded0efda9390b82a84d4 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Tue, 27 Sep 2022 22:12:17 +0200
+Subject: [PATCH] arm64: dts: qcom: ipq6018: fix NAND node name
+
+Per schema it should be nand-controller@79b0000 instead of nand@79b0000.
+Fix it to match nand-controller.yaml requirements.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20220927201218.1264506-1-robimarko@gmail.com
+---
+ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+@@ -348,7 +348,7 @@
+ 			status = "disabled";
+ 		};
+ 
+-		qpic_nand: nand@79b0000 {
++		qpic_nand: nand-controller@79b0000 {
+ 			compatible = "qcom,ipq6018-nand";
+ 			reg = <0x0 0x079b0000 0x0 0x10000>;
+ 			#address-cells = <1>;
diff --git a/target/linux/qualcommax/patches-6.1/0018-v6.2-arm64-dts-qcom-ipq6018-align-TLMM-pin-configuration-.patch b/target/linux/qualcommax/patches-6.1/0018-v6.2-arm64-dts-qcom-ipq6018-align-TLMM-pin-configuration-.patch
new file mode 100644
index 00000000000000..ceaf68bf7ace24
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.1/0018-v6.2-arm64-dts-qcom-ipq6018-align-TLMM-pin-configuration-.patch
@@ -0,0 +1,56 @@
+From 20afb6751739264ea41993877de93923911dfdc3 Mon Sep 17 00:00:00 2001
+From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Date: Thu, 6 Oct 2022 14:46:27 +0200
+Subject: [PATCH] arm64: dts: qcom: ipq6018: align TLMM pin configuration with
+ DT schema
+
+DT schema expects TLMM pin configuration nodes to be named with
+'-state' suffix and their optional children with '-pins' suffix.
+
+Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Reviewed-by: Bjorn Andersson <andersson@kernel.org>
+Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20221006124659.217540-3-krzysztof.kozlowski@linaro.org
+---
+ arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 4 ++--
+ arch/arm64/boot/dts/qcom/ipq6018.dtsi        | 4 ++--
+ 2 files changed, 4 insertions(+), 4 deletions(-)
+
+--- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
++++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
+@@ -51,13 +51,13 @@
+ };
+ 
+ &tlmm {
+-	i2c_1_pins: i2c-1-pins {
++	i2c_1_pins: i2c-1-state {
+ 		pins = "gpio42", "gpio43";
+ 		function = "blsp2_i2c";
+ 		drive-strength = <8>;
+ 	};
+ 
+-	spi_0_pins: spi-0-pins {
++	spi_0_pins: spi-0-state {
+ 		pins = "gpio38", "gpio39", "gpio40", "gpio41";
+ 		function = "blsp0_spi";
+ 		drive-strength = <8>;
+--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+@@ -218,14 +218,14 @@
+ 			interrupt-controller;
+ 			#interrupt-cells = <2>;
+ 
+-			serial_3_pins: serial3-pinmux {
++			serial_3_pins: serial3-state {
+ 				pins = "gpio44", "gpio45";
+ 				function = "blsp2_uart";
+ 				drive-strength = <8>;
+ 				bias-pull-down;
+ 			};
+ 
+-			qpic_pins: qpic-pins {
++			qpic_pins: qpic-state {
+ 				pins = "gpio1", "gpio3", "gpio4",
+ 					"gpio5", "gpio6", "gpio7",
+ 					"gpio8", "gpio10", "gpio11",
diff --git a/target/linux/qualcommax/patches-6.1/0022-v6.4-arm64-dts-qcom-ipq8074-add-compatible-fallback-to.patch b/target/linux/qualcommax/patches-6.1/0022-v6.4-arm64-dts-qcom-ipq8074-add-compatible-fallback-to.patch
new file mode 100644
index 00000000000000..f85be793cde78e
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.1/0022-v6.4-arm64-dts-qcom-ipq8074-add-compatible-fallback-to.patch
@@ -0,0 +1,26 @@
+From d93bd4630ce163f3761aedc0b342b072bee6db6b Mon Sep 17 00:00:00 2001
+From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Date: Wed, 22 Mar 2023 18:41:40 +0100
+Subject: [PATCH] arm64: dts: qcom: ipq8074: add compatible fallback to mailbox
+
+IPQ8074 mailbox is compatible with IPQ6018.
+
+Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20230322174148.810938-4-krzysztof.kozlowski@linaro.org
+---
+ arch/arm64/boot/dts/qcom/ipq8074.dtsi | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+@@ -682,7 +682,8 @@
+ 		};
+ 
+ 		apcs_glb: mailbox@b111000 {
+-			compatible = "qcom,ipq8074-apcs-apps-global";
++			compatible = "qcom,ipq8074-apcs-apps-global",
++				     "qcom,ipq6018-apcs-apps-global";
+ 			reg = <0x0b111000 0x1000>;
+ 			clocks = <&a53pll>, <&xo>;
+ 			clock-names = "pll", "xo";
diff --git a/target/linux/qualcommax/patches-6.1/0023-v6.5-arm64-dts-qcom-ipq8074-add-critical-thermal-trips.patch b/target/linux/qualcommax/patches-6.1/0023-v6.5-arm64-dts-qcom-ipq8074-add-critical-thermal-trips.patch
index 98e0a08a27f43f..737bb067523359 100644
--- a/target/linux/qualcommax/patches-6.1/0023-v6.5-arm64-dts-qcom-ipq8074-add-critical-thermal-trips.patch
+++ b/target/linux/qualcommax/patches-6.1/0023-v6.5-arm64-dts-qcom-ipq8074-add-critical-thermal-trips.patch
@@ -17,7 +17,7 @@ Link: https://lore.kernel.org/r/20230607184448.2512179-1-robimarko@gmail.com
 
 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
 +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -898,6 +898,14 @@
+@@ -899,6 +899,14 @@
  			polling-delay = <1000>;
  
  			thermal-sensors = <&tsens 4>;
@@ -32,7 +32,7 @@ Link: https://lore.kernel.org/r/20230607184448.2512179-1-robimarko@gmail.com
  		};
  
  		nss0-thermal {
-@@ -905,6 +913,14 @@
+@@ -906,6 +914,14 @@
  			polling-delay = <1000>;
  
  			thermal-sensors = <&tsens 5>;
@@ -47,7 +47,7 @@ Link: https://lore.kernel.org/r/20230607184448.2512179-1-robimarko@gmail.com
  		};
  
  		nss1-thermal {
-@@ -912,6 +928,14 @@
+@@ -913,6 +929,14 @@
  			polling-delay = <1000>;
  
  			thermal-sensors = <&tsens 6>;
@@ -62,7 +62,7 @@ Link: https://lore.kernel.org/r/20230607184448.2512179-1-robimarko@gmail.com
  		};
  
  		wcss-phya0-thermal {
-@@ -919,6 +943,14 @@
+@@ -920,6 +944,14 @@
  			polling-delay = <1000>;
  
  			thermal-sensors = <&tsens 7>;
@@ -77,7 +77,7 @@ Link: https://lore.kernel.org/r/20230607184448.2512179-1-robimarko@gmail.com
  		};
  
  		wcss-phya1-thermal {
-@@ -926,6 +958,14 @@
+@@ -927,6 +959,14 @@
  			polling-delay = <1000>;
  
  			thermal-sensors = <&tsens 8>;
@@ -92,7 +92,7 @@ Link: https://lore.kernel.org/r/20230607184448.2512179-1-robimarko@gmail.com
  		};
  
  		cpu0_thermal: cpu0-thermal {
-@@ -933,6 +973,14 @@
+@@ -934,6 +974,14 @@
  			polling-delay = <1000>;
  
  			thermal-sensors = <&tsens 9>;
@@ -107,7 +107,7 @@ Link: https://lore.kernel.org/r/20230607184448.2512179-1-robimarko@gmail.com
  		};
  
  		cpu1_thermal: cpu1-thermal {
-@@ -940,6 +988,14 @@
+@@ -941,6 +989,14 @@
  			polling-delay = <1000>;
  
  			thermal-sensors = <&tsens 10>;
@@ -122,7 +122,7 @@ Link: https://lore.kernel.org/r/20230607184448.2512179-1-robimarko@gmail.com
  		};
  
  		cpu2_thermal: cpu2-thermal {
-@@ -947,6 +1003,14 @@
+@@ -948,6 +1004,14 @@
  			polling-delay = <1000>;
  
  			thermal-sensors = <&tsens 11>;
@@ -137,7 +137,7 @@ Link: https://lore.kernel.org/r/20230607184448.2512179-1-robimarko@gmail.com
  		};
  
  		cpu3_thermal: cpu3-thermal {
-@@ -954,6 +1018,14 @@
+@@ -955,6 +1019,14 @@
  			polling-delay = <1000>;
  
  			thermal-sensors = <&tsens 12>;
@@ -152,7 +152,7 @@ Link: https://lore.kernel.org/r/20230607184448.2512179-1-robimarko@gmail.com
  		};
  
  		cluster_thermal: cluster-thermal {
-@@ -961,6 +1033,14 @@
+@@ -962,6 +1034,14 @@
  			polling-delay = <1000>;
  
  			thermal-sensors = <&tsens 13>;
@@ -167,7 +167,7 @@ Link: https://lore.kernel.org/r/20230607184448.2512179-1-robimarko@gmail.com
  		};
  
  		wcss-phyb0-thermal {
-@@ -968,6 +1048,14 @@
+@@ -969,6 +1049,14 @@
  			polling-delay = <1000>;
  
  			thermal-sensors = <&tsens 14>;
@@ -182,7 +182,7 @@ Link: https://lore.kernel.org/r/20230607184448.2512179-1-robimarko@gmail.com
  		};
  
  		wcss-phyb1-thermal {
-@@ -975,6 +1063,14 @@
+@@ -976,6 +1064,14 @@
  			polling-delay = <1000>;
  
  			thermal-sensors = <&tsens 15>;
diff --git a/target/linux/qualcommax/patches-6.1/0025-v6.7-cpufreq-qcom-nvmem-add-support-for-IPQ6018.patch b/target/linux/qualcommax/patches-6.1/0025-v6.7-cpufreq-qcom-nvmem-add-support-for-IPQ6018.patch
new file mode 100644
index 00000000000000..63e2f22db7dbfd
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.1/0025-v6.7-cpufreq-qcom-nvmem-add-support-for-IPQ6018.patch
@@ -0,0 +1,123 @@
+From 47e161a7873b0891f4e01a69a839f6161d816ea8 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Wed, 25 Oct 2023 14:57:57 +0530
+Subject: [PATCH] cpufreq: qcom-nvmem: add support for IPQ6018
+
+IPQ6018 SoC series comes in multiple SKU-s, and not all of them support
+high frequency OPP points.
+
+SoC itself does however have a single bit in QFPROM to indicate the CPU
+speed-bin.
+That bit is used to indicate frequency limit of 1.5GHz, but that alone is
+not enough as IPQ6000 only goes up to 1.2GHz, but SMEM ID can be used to
+limit it further.
+
+IPQ6018 compatible is blacklisted from DT platdev as the cpufreq device
+will get created by NVMEM CPUFreq driver.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+[ Viresh: Fixed rebase conflict. ]
+Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
+---
+ drivers/cpufreq/cpufreq-dt-platdev.c |  1 +
+ drivers/cpufreq/qcom-cpufreq-nvmem.c | 58 ++++++++++++++++++++++++++++
+ 2 files changed, 59 insertions(+)
+
+--- a/drivers/cpufreq/cpufreq-dt-platdev.c
++++ b/drivers/cpufreq/cpufreq-dt-platdev.c
+@@ -163,6 +163,7 @@ static const struct of_device_id blockli
+ 	{ .compatible = "ti,dra7", },
+ 	{ .compatible = "ti,omap3", },
+ 
++	{ .compatible = "qcom,ipq6018", },
+ 	{ .compatible = "qcom,ipq8064", },
+ 	{ .compatible = "qcom,apq8064", },
+ 	{ .compatible = "qcom,msm8974", },
+--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
++++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
+@@ -31,6 +31,8 @@
+ 
+ #include <dt-bindings/arm/qcom,ids.h>
+ 
++#define IPQ6000_VERSION	BIT(2)
++
+ struct qcom_cpufreq_drv;
+ 
+ struct qcom_cpufreq_match_data {
+@@ -204,6 +206,57 @@ len_error:
+ 	return ret;
+ }
+ 
++static int qcom_cpufreq_ipq6018_name_version(struct device *cpu_dev,
++					     struct nvmem_cell *speedbin_nvmem,
++					     char **pvs_name,
++					     struct qcom_cpufreq_drv *drv)
++{
++	u32 msm_id;
++	int ret;
++	u8 *speedbin;
++	*pvs_name = NULL;
++
++	ret = qcom_smem_get_soc_id(&msm_id);
++	if (ret)
++		return ret;
++
++	speedbin = nvmem_cell_read(speedbin_nvmem, NULL);
++	if (IS_ERR(speedbin))
++		return PTR_ERR(speedbin);
++
++	switch (msm_id) {
++	case QCOM_ID_IPQ6005:
++	case QCOM_ID_IPQ6010:
++	case QCOM_ID_IPQ6018:
++	case QCOM_ID_IPQ6028:
++		/* Fuse Value    Freq    BIT to set
++		 * ---------------------------------
++		 *   2’b0     No Limit     BIT(0)
++		 *   2’b1     1.5 GHz      BIT(1)
++		 */
++		drv->versions = 1 << (unsigned int)(*speedbin);
++		break;
++	case QCOM_ID_IPQ6000:
++		/*
++		 * IPQ6018 family only has one bit to advertise the CPU
++		 * speed-bin, but that is not enough for IPQ6000 which
++		 * is only rated up to 1.2GHz.
++		 * So for IPQ6000 manually set BIT(2) based on SMEM ID.
++		 */
++		drv->versions = IPQ6000_VERSION;
++		break;
++	default:
++		dev_err(cpu_dev,
++			"SoC ID %u is not part of IPQ6018 family, limiting to 1.2GHz!\n",
++			msm_id);
++		drv->versions = IPQ6000_VERSION;
++		break;
++	}
++
++	kfree(speedbin);
++	return 0;
++}
++
+ static const struct qcom_cpufreq_match_data match_data_kryo = {
+ 	.get_version = qcom_cpufreq_kryo_name_version,
+ };
+@@ -218,6 +271,10 @@ static const struct qcom_cpufreq_match_d
+ 	.genpd_names = qcs404_genpd_names,
+ };
+ 
++static const struct qcom_cpufreq_match_data match_data_ipq6018 = {
++	.get_version = qcom_cpufreq_ipq6018_name_version,
++};
++
+ static int qcom_cpufreq_probe(struct platform_device *pdev)
+ {
+ 	struct qcom_cpufreq_drv *drv;
+@@ -362,6 +419,7 @@ static const struct of_device_id qcom_cp
+ 	{ .compatible = "qcom,apq8096", .data = &match_data_kryo },
+ 	{ .compatible = "qcom,msm8996", .data = &match_data_kryo },
+ 	{ .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
++	{ .compatible = "qcom,ipq6018", .data = &match_data_ipq6018 },
+ 	{ .compatible = "qcom,ipq8064", .data = &match_data_krait },
+ 	{ .compatible = "qcom,apq8064", .data = &match_data_krait },
+ 	{ .compatible = "qcom,msm8974", .data = &match_data_krait },
diff --git a/target/linux/qualcommax/patches-6.1/0025-v6.7-cpufreq-qcom-nvmem-add-support-for-IPQ8074.patch b/target/linux/qualcommax/patches-6.1/0025-v6.7-cpufreq-qcom-nvmem-add-support-for-IPQ8074.patch
deleted file mode 100644
index 61cc2a459bb1b5..00000000000000
--- a/target/linux/qualcommax/patches-6.1/0025-v6.7-cpufreq-qcom-nvmem-add-support-for-IPQ8074.patch
+++ /dev/null
@@ -1,112 +0,0 @@
-From df75a00c60c6e58bc36e4c63e9d7f1910412b132 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Fri, 13 Oct 2023 19:20:02 +0200
-Subject: [PATCH] cpufreq: qcom-nvmem: add support for IPQ8074
-
-IPQ8074 comes in 3 families:
-* IPQ8070A/IPQ8071A (Acorn) up to 1.4GHz
-* IPQ8172/IPQ8173/IPQ8174 (Oak) up to 1.4GHz
-* IPQ8072A/IPQ8074A/IPQ8076A/IPQ8078A (Hawkeye) up to 2.2GHz
-
-So, in order to be able to share one OPP table lets add support for IPQ8074
-family based of SMEM SoC ID-s as speedbin fuse is always 0 on IPQ8074.
-
-IPQ8074 compatible is blacklisted from DT platdev as the cpufreq device
-will get created by NVMEM CPUFreq driver.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/cpufreq-dt-platdev.c |  1 +
- drivers/cpufreq/qcom-cpufreq-nvmem.c | 48 ++++++++++++++++++++++++++++
- 2 files changed, 49 insertions(+)
-
---- a/drivers/cpufreq/cpufreq-dt-platdev.c
-+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
-@@ -164,6 +164,7 @@ static const struct of_device_id blockli
- 	{ .compatible = "ti,omap3", },
- 
- 	{ .compatible = "qcom,ipq8064", },
-+	{ .compatible = "qcom,ipq8074", },
- 	{ .compatible = "qcom,apq8064", },
- 	{ .compatible = "qcom,msm8974", },
- 	{ .compatible = "qcom,msm8960", },
---- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
-+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
-@@ -31,6 +31,11 @@
- 
- #include <dt-bindings/arm/qcom,ids.h>
- 
-+enum ipq8074_versions {
-+	IPQ8074_HAWKEYE_VERSION = 0,
-+	IPQ8074_ACORN_VERSION,
-+};
-+
- struct qcom_cpufreq_drv;
- 
- struct qcom_cpufreq_match_data {
-@@ -204,6 +209,44 @@ len_error:
- 	return ret;
- }
- 
-+static int qcom_cpufreq_ipq8074_name_version(struct device *cpu_dev,
-+					     struct nvmem_cell *speedbin_nvmem,
-+					     char **pvs_name,
-+					     struct qcom_cpufreq_drv *drv)
-+{
-+	u32 msm_id;
-+	int ret;
-+	*pvs_name = NULL;
-+
-+	ret = qcom_smem_get_soc_id(&msm_id);
-+	if (ret)
-+		return ret;
-+
-+	switch (msm_id) {
-+	case QCOM_ID_IPQ8070A:
-+	case QCOM_ID_IPQ8071A:
-+	case QCOM_ID_IPQ8172:
-+	case QCOM_ID_IPQ8173:
-+	case QCOM_ID_IPQ8174:
-+		drv->versions = BIT(IPQ8074_ACORN_VERSION);
-+		break;
-+	case QCOM_ID_IPQ8072A:
-+	case QCOM_ID_IPQ8074A:
-+	case QCOM_ID_IPQ8076A:
-+	case QCOM_ID_IPQ8078A:
-+		drv->versions = BIT(IPQ8074_HAWKEYE_VERSION);
-+		break;
-+	default:
-+		dev_err(cpu_dev,
-+			"SoC ID %u is not part of IPQ8074 family, limiting to 1.4GHz!\n",
-+			msm_id);
-+		drv->versions = BIT(IPQ8074_ACORN_VERSION);
-+		break;
-+	}
-+
-+	return 0;
-+}
-+
- static const struct qcom_cpufreq_match_data match_data_kryo = {
- 	.get_version = qcom_cpufreq_kryo_name_version,
- };
-@@ -218,6 +261,10 @@ static const struct qcom_cpufreq_match_d
- 	.genpd_names = qcs404_genpd_names,
- };
- 
-+static const struct qcom_cpufreq_match_data match_data_ipq8074 = {
-+	.get_version = qcom_cpufreq_ipq8074_name_version,
-+};
-+
- static int qcom_cpufreq_probe(struct platform_device *pdev)
- {
- 	struct qcom_cpufreq_drv *drv;
-@@ -363,6 +410,7 @@ static const struct of_device_id qcom_cp
- 	{ .compatible = "qcom,msm8996", .data = &match_data_kryo },
- 	{ .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
- 	{ .compatible = "qcom,ipq8064", .data = &match_data_krait },
-+	{ .compatible = "qcom,ipq8074", .data = &match_data_ipq8074 },
- 	{ .compatible = "qcom,apq8064", .data = &match_data_krait },
- 	{ .compatible = "qcom,msm8974", .data = &match_data_krait },
- 	{ .compatible = "qcom,msm8960", .data = &match_data_krait },
diff --git a/target/linux/qualcommax/patches-6.1/0026-v6.7-cpufreq-qcom-nvmem-add-support-for-IPQ8074.patch b/target/linux/qualcommax/patches-6.1/0026-v6.7-cpufreq-qcom-nvmem-add-support-for-IPQ8074.patch
new file mode 100644
index 00000000000000..cbd7b770f4e741
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.1/0026-v6.7-cpufreq-qcom-nvmem-add-support-for-IPQ8074.patch
@@ -0,0 +1,113 @@
+From 0b9cd949136f1b63f7aa9424b6e583a1ab261e36 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Fri, 13 Oct 2023 19:20:02 +0200
+Subject: [PATCH] cpufreq: qcom-nvmem: add support for IPQ8074
+
+IPQ8074 comes in 3 families:
+* IPQ8070A/IPQ8071A (Acorn) up to 1.4GHz
+* IPQ8172/IPQ8173/IPQ8174 (Oak) up to 1.4GHz
+* IPQ8072A/IPQ8074A/IPQ8076A/IPQ8078A (Hawkeye) up to 2.2GHz
+
+So, in order to be able to share one OPP table lets add support for IPQ8074
+family based of SMEM SoC ID-s as speedbin fuse is always 0 on IPQ8074.
+
+IPQ8074 compatible is blacklisted from DT platdev as the cpufreq device
+will get created by NVMEM CPUFreq driver.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
+[ Viresh: Fixed rebase conflict. ]
+Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
+---
+ drivers/cpufreq/cpufreq-dt-platdev.c |  1 +
+ drivers/cpufreq/qcom-cpufreq-nvmem.c | 48 ++++++++++++++++++++++++++++
+ 2 files changed, 49 insertions(+)
+
+--- a/drivers/cpufreq/cpufreq-dt-platdev.c
++++ b/drivers/cpufreq/cpufreq-dt-platdev.c
+@@ -165,6 +165,7 @@ static const struct of_device_id blockli
+ 
+ 	{ .compatible = "qcom,ipq6018", },
+ 	{ .compatible = "qcom,ipq8064", },
++	{ .compatible = "qcom,ipq8074", },
+ 	{ .compatible = "qcom,apq8064", },
+ 	{ .compatible = "qcom,msm8974", },
+ 	{ .compatible = "qcom,msm8960", },
+--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
++++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
+@@ -33,6 +33,11 @@
+ 
+ #define IPQ6000_VERSION	BIT(2)
+ 
++enum ipq8074_versions {
++	IPQ8074_HAWKEYE_VERSION = 0,
++	IPQ8074_ACORN_VERSION,
++};
++
+ struct qcom_cpufreq_drv;
+ 
+ struct qcom_cpufreq_match_data {
+@@ -257,6 +262,44 @@ static int qcom_cpufreq_ipq6018_name_ver
+ 	return 0;
+ }
+ 
++static int qcom_cpufreq_ipq8074_name_version(struct device *cpu_dev,
++					     struct nvmem_cell *speedbin_nvmem,
++					     char **pvs_name,
++					     struct qcom_cpufreq_drv *drv)
++{
++	u32 msm_id;
++	int ret;
++	*pvs_name = NULL;
++
++	ret = qcom_smem_get_soc_id(&msm_id);
++	if (ret)
++		return ret;
++
++	switch (msm_id) {
++	case QCOM_ID_IPQ8070A:
++	case QCOM_ID_IPQ8071A:
++	case QCOM_ID_IPQ8172:
++	case QCOM_ID_IPQ8173:
++	case QCOM_ID_IPQ8174:
++		drv->versions = BIT(IPQ8074_ACORN_VERSION);
++		break;
++	case QCOM_ID_IPQ8072A:
++	case QCOM_ID_IPQ8074A:
++	case QCOM_ID_IPQ8076A:
++	case QCOM_ID_IPQ8078A:
++		drv->versions = BIT(IPQ8074_HAWKEYE_VERSION);
++		break;
++	default:
++		dev_err(cpu_dev,
++			"SoC ID %u is not part of IPQ8074 family, limiting to 1.4GHz!\n",
++			msm_id);
++		drv->versions = BIT(IPQ8074_ACORN_VERSION);
++		break;
++	}
++
++	return 0;
++}
++
+ static const struct qcom_cpufreq_match_data match_data_kryo = {
+ 	.get_version = qcom_cpufreq_kryo_name_version,
+ };
+@@ -275,6 +318,10 @@ static const struct qcom_cpufreq_match_d
+ 	.get_version = qcom_cpufreq_ipq6018_name_version,
+ };
+ 
++static const struct qcom_cpufreq_match_data match_data_ipq8074 = {
++	.get_version = qcom_cpufreq_ipq8074_name_version,
++};
++
+ static int qcom_cpufreq_probe(struct platform_device *pdev)
+ {
+ 	struct qcom_cpufreq_drv *drv;
+@@ -421,6 +468,7 @@ static const struct of_device_id qcom_cp
+ 	{ .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
+ 	{ .compatible = "qcom,ipq6018", .data = &match_data_ipq6018 },
+ 	{ .compatible = "qcom,ipq8064", .data = &match_data_krait },
++	{ .compatible = "qcom,ipq8074", .data = &match_data_ipq8074 },
+ 	{ .compatible = "qcom,apq8064", .data = &match_data_krait },
+ 	{ .compatible = "qcom,msm8974", .data = &match_data_krait },
+ 	{ .compatible = "qcom,msm8960", .data = &match_data_krait },
diff --git a/target/linux/qualcommax/patches-6.1/0028-v6.7-arm64-dts-qcom-ipq8074-include-the-GPLL0-as-clock-pr.patch b/target/linux/qualcommax/patches-6.1/0028-v6.7-arm64-dts-qcom-ipq8074-include-the-GPLL0-as-clock-pr.patch
index dee770e4cd13ba..fb7011de95de71 100644
--- a/target/linux/qualcommax/patches-6.1/0028-v6.7-arm64-dts-qcom-ipq8074-include-the-GPLL0-as-clock-pr.patch
+++ b/target/linux/qualcommax/patches-6.1/0028-v6.7-arm64-dts-qcom-ipq8074-include-the-GPLL0-as-clock-pr.patch
@@ -19,9 +19,9 @@ Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
 
 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
 +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -684,8 +684,8 @@
- 		apcs_glb: mailbox@b111000 {
- 			compatible = "qcom,ipq8074-apcs-apps-global";
+@@ -685,8 +685,8 @@
+ 			compatible = "qcom,ipq8074-apcs-apps-global",
+ 				     "qcom,ipq6018-apcs-apps-global";
  			reg = <0x0b111000 0x1000>;
 -			clocks = <&a53pll>, <&xo>;
 -			clock-names = "pll", "xo";
diff --git a/target/linux/qualcommax/patches-6.1/0033-v6.2-arm64-dts-qcom-ipq6018-move-ARMv8-timer-out-of-SoC.patch b/target/linux/qualcommax/patches-6.1/0033-v6.2-arm64-dts-qcom-ipq6018-move-ARMv8-timer-out-of-SoC.patch
new file mode 100644
index 00000000000000..c3e94a2ae008ef
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.1/0033-v6.2-arm64-dts-qcom-ipq6018-move-ARMv8-timer-out-of-SoC.patch
@@ -0,0 +1,52 @@
+From feeef118fda562cf9081edef8ad464d89db070f4 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Tue, 27 Sep 2022 22:12:18 +0200
+Subject: [PATCH] arm64: dts: qcom: ipq6018: move ARMv8 timer out of SoC node
+
+The ARM timer is usually considered not part of SoC node, just like
+other ARM designed blocks (PMU, PSCI).  This fixes dtbs_check warning:
+
+arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dtb: soc: timer: {'compatible': ['arm,armv8-timer'], 'interrupts': [[1, 2, 3848], [1, 3, 3848], [1, 4, 3848], [1, 1, 3848]]} should not be valid under {'type': 'object'}
+	From schema: dtschema/schemas/simple-bus.yaml
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20220927201218.1264506-2-robimarko@gmail.com
+---
+ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 16 ++++++++--------
+ 1 file changed, 8 insertions(+), 8 deletions(-)
+
+--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+@@ -510,14 +510,6 @@
+ 			clock-names = "xo";
+ 		};
+ 
+-		timer {
+-			compatible = "arm,armv8-timer";
+-			interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+-				     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+-				     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+-				     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+-		};
+-
+ 		timer@b120000 {
+ 			#address-cells = <1>;
+ 			#size-cells = <1>;
+@@ -769,6 +761,14 @@
+ 		};
+ 	};
+ 
++	timer {
++		compatible = "arm,armv8-timer";
++		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
++			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
++			     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
++			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
++	};
++
+ 	wcss: wcss-smp2p {
+ 		compatible = "qcom,smp2p";
+ 		qcom,smem = <435>, <428>;
diff --git a/target/linux/qualcommax/patches-6.1/0034-v6.3-arm64-dts-qcom-ipq6018-Sort-nodes-properly.patch b/target/linux/qualcommax/patches-6.1/0034-v6.3-arm64-dts-qcom-ipq6018-Sort-nodes-properly.patch
new file mode 100644
index 00000000000000..ad32e64fe1b582
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.1/0034-v6.3-arm64-dts-qcom-ipq6018-Sort-nodes-properly.patch
@@ -0,0 +1,605 @@
+From 2c6e322a41c5e1ca45be50b9d5fbcda62dc23a0d Mon Sep 17 00:00:00 2001
+From: Konrad Dybcio <konrad.dybcio@linaro.org>
+Date: Mon, 2 Jan 2023 10:46:28 +0100
+Subject: [PATCH] arm64: dts: qcom: ipq6018: Sort nodes properly
+
+Order nodes by unit address if one exists and alphabetically otherwise.
+
+Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20230102094642.74254-4-konrad.dybcio@linaro.org
+---
+ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 562 +++++++++++++-------------
+ 1 file changed, 281 insertions(+), 281 deletions(-)
+
+--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+@@ -87,6 +87,12 @@
+ 		};
+ 	};
+ 
++	firmware {
++		scm {
++			compatible = "qcom,scm-ipq6018", "qcom,scm";
++		};
++	};
++
+ 	cpu_opp_table: opp-table-cpu {
+ 		compatible = "operating-points-v2";
+ 		opp-shared;
+@@ -123,12 +129,6 @@
+ 		};
+ 	};
+ 
+-	firmware {
+-		scm {
+-			compatible = "qcom,scm-ipq6018", "qcom,scm";
+-		};
+-	};
+-
+ 	pmuv8: pmu {
+ 		compatible = "arm,cortex-a53-pmu";
+ 		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
+@@ -166,6 +166,28 @@
+ 		};
+ 	};
+ 
++	rpm-glink {
++		compatible = "qcom,glink-rpm";
++		interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
++		qcom,rpm-msg-ram = <&rpm_msg_ram>;
++		mboxes = <&apcs_glb 0>;
++
++		rpm_requests: glink-channel {
++			compatible = "qcom,rpm-ipq6018";
++			qcom,glink-channels = "rpm_requests";
++
++			regulators {
++				compatible = "qcom,rpm-mp5496-regulators";
++
++				ipq6018_s2: s2 {
++					regulator-min-microvolt = <725000>;
++					regulator-max-microvolt = <1062500>;
++					regulator-always-on;
++				};
++			};
++		};
++	};
++
+ 	smem {
+ 		compatible = "qcom,smem";
+ 		memory-region = <&smem_region>;
+@@ -179,6 +201,102 @@
+ 		dma-ranges;
+ 		compatible = "simple-bus";
+ 
++		qusb_phy_1: qusb@59000 {
++			compatible = "qcom,ipq6018-qusb2-phy";
++			reg = <0x0 0x00059000 0x0 0x180>;
++			#phy-cells = <0>;
++
++			clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
++				 <&xo>;
++			clock-names = "cfg_ahb", "ref";
++
++			resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
++			status = "disabled";
++		};
++
++		ssphy_0: ssphy@78000 {
++			compatible = "qcom,ipq6018-qmp-usb3-phy";
++			reg = <0x0 0x00078000 0x0 0x1c4>;
++			#address-cells = <2>;
++			#size-cells = <2>;
++			ranges;
++
++			clocks = <&gcc GCC_USB0_AUX_CLK>,
++				 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, <&xo>;
++			clock-names = "aux", "cfg_ahb", "ref";
++
++			resets = <&gcc GCC_USB0_PHY_BCR>,
++				 <&gcc GCC_USB3PHY_0_PHY_BCR>;
++			reset-names = "phy","common";
++			status = "disabled";
++
++			usb0_ssphy: phy@78200 {
++				reg = <0x0 0x00078200 0x0 0x130>, /* Tx */
++				      <0x0 0x00078400 0x0 0x200>, /* Rx */
++				      <0x0 0x00078800 0x0 0x1f8>, /* PCS */
++				      <0x0 0x00078600 0x0 0x044>; /* PCS misc */
++				#phy-cells = <0>;
++				#clock-cells = <0>;
++				clocks = <&gcc GCC_USB0_PIPE_CLK>;
++				clock-names = "pipe0";
++				clock-output-names = "gcc_usb0_pipe_clk_src";
++			};
++		};
++
++		qusb_phy_0: qusb@79000 {
++			compatible = "qcom,ipq6018-qusb2-phy";
++			reg = <0x0 0x00079000 0x0 0x180>;
++			#phy-cells = <0>;
++
++			clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
++				<&xo>;
++			clock-names = "cfg_ahb", "ref";
++
++			resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
++			status = "disabled";
++		};
++
++		pcie_phy: phy@84000 {
++			compatible = "qcom,ipq6018-qmp-pcie-phy";
++			reg = <0x0 0x00084000 0x0 0x1bc>; /* Serdes PLL */
++			status = "disabled";
++			#address-cells = <2>;
++			#size-cells = <2>;
++			ranges;
++
++			clocks = <&gcc GCC_PCIE0_AUX_CLK>,
++				<&gcc GCC_PCIE0_AHB_CLK>;
++			clock-names = "aux", "cfg_ahb";
++
++			resets = <&gcc GCC_PCIE0_PHY_BCR>,
++				<&gcc GCC_PCIE0PHY_PHY_BCR>;
++			reset-names = "phy",
++				      "common";
++
++			pcie_phy0: phy@84200 {
++				reg = <0x0 0x00084200 0x0 0x16c>, /* Serdes Tx */
++				      <0x0 0x00084400 0x0 0x200>, /* Serdes Rx */
++				      <0x0 0x00084800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */
++				      <0x0 0x00084c00 0x0 0xf4>; /* pcs_misc */
++				#phy-cells = <0>;
++
++				clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
++				clock-names = "pipe0";
++				clock-output-names = "gcc_pcie0_pipe_clk_src";
++				#clock-cells = <0>;
++			};
++		};
++
++		mdio: mdio@90000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio";
++			reg = <0x0 0x00090000 0x0 0x64>;
++			clocks = <&gcc GCC_MDIO_AHB_CLK>;
++			clock-names = "gcc_mdio_ahb_clk";
++			status = "disabled";
++		};
++
+ 		prng: qrng@e1000 {
+ 			compatible = "qcom,prng-ee";
+ 			reg = <0x0 0x000e3000 0x0 0x1000>;
+@@ -257,6 +375,41 @@
+ 			reg = <0x0 0x01937000 0x0 0x21000>;
+ 		};
+ 
++		usb2: usb@70f8800 {
++			compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
++			reg = <0x0 0x070F8800 0x0 0x400>;
++			#address-cells = <2>;
++			#size-cells = <2>;
++			ranges;
++			clocks = <&gcc GCC_USB1_MASTER_CLK>,
++				 <&gcc GCC_USB1_SLEEP_CLK>,
++				 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
++			clock-names = "core",
++				      "sleep",
++				      "mock_utmi";
++
++			assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>,
++					  <&gcc GCC_USB1_MOCK_UTMI_CLK>;
++			assigned-clock-rates = <133330000>,
++					       <24000000>;
++			resets = <&gcc GCC_USB1_BCR>;
++			status = "disabled";
++
++			dwc_1: usb@7000000 {
++				compatible = "snps,dwc3";
++				reg = <0x0 0x07000000 0x0 0xcd00>;
++				interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
++				phys = <&qusb_phy_1>;
++				phy-names = "usb2-phy";
++				tx-fifo-resize;
++				snps,is-utmi-l1-suspend;
++				snps,hird-threshold = /bits/ 8 <0x0>;
++				snps,dis_u2_susphy_quirk;
++				snps,dis_u3_susphy_quirk;
++				dr_mode = "host";
++			};
++		};
++
+ 		blsp_dma: dma-controller@7884000 {
+ 			compatible = "qcom,bam-v1.7.0";
+ 			reg = <0x0 0x07884000 0x0 0x2b000>;
+@@ -366,6 +519,49 @@
+ 			status = "disabled";
+ 		};
+ 
++		usb3: usb@8af8800 {
++			compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
++			reg = <0x0 0x08af8800 0x0 0x400>;
++			#address-cells = <2>;
++			#size-cells = <2>;
++			ranges;
++
++			clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
++				<&gcc GCC_USB0_MASTER_CLK>,
++				<&gcc GCC_USB0_SLEEP_CLK>,
++				<&gcc GCC_USB0_MOCK_UTMI_CLK>;
++			clock-names = "cfg_noc",
++				"core",
++				"sleep",
++				"mock_utmi";
++
++			assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
++					  <&gcc GCC_USB0_MASTER_CLK>,
++					  <&gcc GCC_USB0_MOCK_UTMI_CLK>;
++			assigned-clock-rates = <133330000>,
++					       <133330000>,
++					       <24000000>;
++
++			resets = <&gcc GCC_USB0_BCR>;
++			status = "disabled";
++
++			dwc_0: usb@8a00000 {
++				compatible = "snps,dwc3";
++				reg = <0x0 0x08a00000 0x0 0xcd00>;
++				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
++				phys = <&qusb_phy_0>, <&usb0_ssphy>;
++				phy-names = "usb2-phy", "usb3-phy";
++				clocks = <&xo>;
++				clock-names = "ref";
++				tx-fifo-resize;
++				snps,is-utmi-l1-suspend;
++				snps,hird-threshold = /bits/ 8 <0x0>;
++				snps,dis_u2_susphy_quirk;
++				snps,dis_u3_susphy_quirk;
++				dr_mode = "host";
++			};
++		};
++
+ 		intc: interrupt-controller@b000000 {
+ 			compatible = "qcom,msm-qgic2";
+ 			#address-cells = <2>;
+@@ -386,105 +582,6 @@
+ 			};
+ 		};
+ 
+-		pcie_phy: phy@84000 {
+-			compatible = "qcom,ipq6018-qmp-pcie-phy";
+-			reg = <0x0 0x00084000 0x0 0x1bc>; /* Serdes PLL */
+-			status = "disabled";
+-			#address-cells = <2>;
+-			#size-cells = <2>;
+-			ranges;
+-
+-			clocks = <&gcc GCC_PCIE0_AUX_CLK>,
+-				<&gcc GCC_PCIE0_AHB_CLK>;
+-			clock-names = "aux", "cfg_ahb";
+-
+-			resets = <&gcc GCC_PCIE0_PHY_BCR>,
+-				<&gcc GCC_PCIE0PHY_PHY_BCR>;
+-			reset-names = "phy",
+-				      "common";
+-
+-			pcie_phy0: phy@84200 {
+-				reg = <0x0 0x00084200 0x0 0x16c>, /* Serdes Tx */
+-				      <0x0 0x00084400 0x0 0x200>, /* Serdes Rx */
+-				      <0x0 0x00084800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */
+-				      <0x0 0x00084c00 0x0 0xf4>; /* pcs_misc */
+-				#phy-cells = <0>;
+-
+-				clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
+-				clock-names = "pipe0";
+-				clock-output-names = "gcc_pcie0_pipe_clk_src";
+-				#clock-cells = <0>;
+-			};
+-		};
+-
+-		pcie0: pci@20000000 {
+-			compatible = "qcom,pcie-ipq6018";
+-			reg = <0x0 0x20000000 0x0 0xf1d>,
+-			      <0x0 0x20000f20 0x0 0xa8>,
+-			      <0x0 0x20001000 0x0 0x1000>,
+-			      <0x0 0x80000 0x0 0x4000>,
+-			      <0x0 0x20100000 0x0 0x1000>;
+-			reg-names = "dbi", "elbi", "atu", "parf", "config";
+-
+-			device_type = "pci";
+-			linux,pci-domain = <0>;
+-			bus-range = <0x00 0xff>;
+-			num-lanes = <1>;
+-			max-link-speed = <3>;
+-			#address-cells = <3>;
+-			#size-cells = <2>;
+-
+-			phys = <&pcie_phy0>;
+-			phy-names = "pciephy";
+-
+-			ranges = <0x81000000 0x0 0x00000000 0x0 0x20200000 0x0 0x10000>,
+-				 <0x82000000 0x0 0x20220000 0x0 0x20220000 0x0 0xfde0000>;
+-
+-			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+-			interrupt-names = "msi";
+-
+-			#interrupt-cells = <1>;
+-			interrupt-map-mask = <0 0 0 0x7>;
+-			interrupt-map = <0 0 0 1 &intc 0 75
+-					 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+-					<0 0 0 2 &intc 0 78
+-					 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+-					<0 0 0 3 &intc 0 79
+-					 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+-					<0 0 0 4 &intc 0 83
+-					 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+-
+-			clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
+-				 <&gcc GCC_PCIE0_AXI_M_CLK>,
+-				 <&gcc GCC_PCIE0_AXI_S_CLK>,
+-				 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
+-				 <&gcc PCIE0_RCHNG_CLK>;
+-			clock-names = "iface",
+-				      "axi_m",
+-				      "axi_s",
+-				      "axi_bridge",
+-				      "rchng";
+-
+-			resets = <&gcc GCC_PCIE0_PIPE_ARES>,
+-				 <&gcc GCC_PCIE0_SLEEP_ARES>,
+-				 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
+-				 <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
+-				 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
+-				 <&gcc GCC_PCIE0_AHB_ARES>,
+-				 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
+-				 <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
+-			reset-names = "pipe",
+-				      "sleep",
+-				      "sticky",
+-				      "axi_m",
+-				      "axi_s",
+-				      "ahb",
+-				      "axi_m_sticky",
+-				      "axi_s_sticky";
+-
+-			status = "disabled";
+-		};
+-
+ 		watchdog@b017000 {
+ 			compatible = "qcom,kpss-wdt";
+ 			interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
+@@ -617,147 +714,74 @@
+ 			};
+ 		};
+ 
+-		mdio: mdio@90000 {
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio";
+-			reg = <0x0 0x00090000 0x0 0x64>;
+-			clocks = <&gcc GCC_MDIO_AHB_CLK>;
+-			clock-names = "gcc_mdio_ahb_clk";
+-			status = "disabled";
+-		};
+-
+-		qusb_phy_1: qusb@59000 {
+-			compatible = "qcom,ipq6018-qusb2-phy";
+-			reg = <0x0 0x00059000 0x0 0x180>;
+-			#phy-cells = <0>;
+-
+-			clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
+-				 <&xo>;
+-			clock-names = "cfg_ahb", "ref";
+-
+-			resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
+-			status = "disabled";
+-		};
+-
+-		usb2: usb@70f8800 {
+-			compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
+-			reg = <0x0 0x070F8800 0x0 0x400>;
+-			#address-cells = <2>;
+-			#size-cells = <2>;
+-			ranges;
+-			clocks = <&gcc GCC_USB1_MASTER_CLK>,
+-				 <&gcc GCC_USB1_SLEEP_CLK>,
+-				 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
+-			clock-names = "core",
+-				      "sleep",
+-				      "mock_utmi";
+-
+-			assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>,
+-					  <&gcc GCC_USB1_MOCK_UTMI_CLK>;
+-			assigned-clock-rates = <133330000>,
+-					       <24000000>;
+-			resets = <&gcc GCC_USB1_BCR>;
+-			status = "disabled";
+-
+-			dwc_1: usb@7000000 {
+-				compatible = "snps,dwc3";
+-				reg = <0x0 0x07000000 0x0 0xcd00>;
+-				interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+-				phys = <&qusb_phy_1>;
+-				phy-names = "usb2-phy";
+-				tx-fifo-resize;
+-				snps,is-utmi-l1-suspend;
+-				snps,hird-threshold = /bits/ 8 <0x0>;
+-				snps,dis_u2_susphy_quirk;
+-				snps,dis_u3_susphy_quirk;
+-				dr_mode = "host";
+-			};
+-		};
++		pcie0: pci@20000000 {
++			compatible = "qcom,pcie-ipq6018";
++			reg = <0x0 0x20000000 0x0 0xf1d>,
++			      <0x0 0x20000f20 0x0 0xa8>,
++			      <0x0 0x20001000 0x0 0x1000>,
++			      <0x0 0x80000 0x0 0x4000>,
++			      <0x0 0x20100000 0x0 0x1000>;
++			reg-names = "dbi", "elbi", "atu", "parf", "config";
+ 
+-		ssphy_0: ssphy@78000 {
+-			compatible = "qcom,ipq6018-qmp-usb3-phy";
+-			reg = <0x0 0x00078000 0x0 0x1c4>;
+-			#address-cells = <2>;
++			device_type = "pci";
++			linux,pci-domain = <0>;
++			bus-range = <0x00 0xff>;
++			num-lanes = <1>;
++			max-link-speed = <3>;
++			#address-cells = <3>;
+ 			#size-cells = <2>;
+-			ranges;
+-
+-			clocks = <&gcc GCC_USB0_AUX_CLK>,
+-				 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, <&xo>;
+-			clock-names = "aux", "cfg_ahb", "ref";
+-
+-			resets = <&gcc GCC_USB0_PHY_BCR>,
+-				 <&gcc GCC_USB3PHY_0_PHY_BCR>;
+-			reset-names = "phy","common";
+-			status = "disabled";
+-
+-			usb0_ssphy: phy@78200 {
+-				reg = <0x0 0x00078200 0x0 0x130>, /* Tx */
+-				      <0x0 0x00078400 0x0 0x200>, /* Rx */
+-				      <0x0 0x00078800 0x0 0x1f8>, /* PCS */
+-				      <0x0 0x00078600 0x0 0x044>; /* PCS misc */
+-				#phy-cells = <0>;
+-				#clock-cells = <0>;
+-				clocks = <&gcc GCC_USB0_PIPE_CLK>;
+-				clock-names = "pipe0";
+-				clock-output-names = "gcc_usb0_pipe_clk_src";
+-			};
+-		};
+ 
+-		qusb_phy_0: qusb@79000 {
+-			compatible = "qcom,ipq6018-qusb2-phy";
+-			reg = <0x0 0x00079000 0x0 0x180>;
+-			#phy-cells = <0>;
++			phys = <&pcie_phy0>;
++			phy-names = "pciephy";
+ 
+-			clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+-				<&xo>;
+-			clock-names = "cfg_ahb", "ref";
++			ranges = <0x81000000 0 0x20200000 0 0x20200000
++				  0 0x10000>, /* downstream I/O */
++				 <0x82000000 0 0x20220000 0 0x20220000
++				  0 0xfde0000>; /* non-prefetchable memory */
+ 
+-			resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
+-			status = "disabled";
+-		};
++			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "msi";
+ 
+-		usb3: usb@8af8800 {
+-			compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
+-			reg = <0x0 0x8af8800 0x0 0x400>;
+-			#address-cells = <2>;
+-			#size-cells = <2>;
+-			ranges;
++			#interrupt-cells = <1>;
++			interrupt-map-mask = <0 0 0 0x7>;
++			interrupt-map = <0 0 0 1 &intc 0 75
++					 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
++					<0 0 0 2 &intc 0 78
++					 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
++					<0 0 0 3 &intc 0 79
++					 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
++					<0 0 0 4 &intc 0 83
++					 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+ 
+-			clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
+-				<&gcc GCC_USB0_MASTER_CLK>,
+-				<&gcc GCC_USB0_SLEEP_CLK>,
+-				<&gcc GCC_USB0_MOCK_UTMI_CLK>;
+-			clock-names = "cfg_noc",
+-				"core",
+-				"sleep",
+-				"mock_utmi";
++			clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
++				 <&gcc GCC_PCIE0_AXI_M_CLK>,
++				 <&gcc GCC_PCIE0_AXI_S_CLK>,
++				 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
++				 <&gcc PCIE0_RCHNG_CLK>;
++			clock-names = "iface",
++				      "axi_m",
++				      "axi_s",
++				      "axi_bridge",
++				      "rchng";
+ 
+-			assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
+-					  <&gcc GCC_USB0_MASTER_CLK>,
+-					  <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+-			assigned-clock-rates = <133330000>,
+-					       <133330000>,
+-					       <24000000>;
++			resets = <&gcc GCC_PCIE0_PIPE_ARES>,
++				 <&gcc GCC_PCIE0_SLEEP_ARES>,
++				 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
++				 <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
++				 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
++				 <&gcc GCC_PCIE0_AHB_ARES>,
++				 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
++				 <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
++			reset-names = "pipe",
++				      "sleep",
++				      "sticky",
++				      "axi_m",
++				      "axi_s",
++				      "ahb",
++				      "axi_m_sticky",
++				      "axi_s_sticky";
+ 
+-			resets = <&gcc GCC_USB0_BCR>;
+ 			status = "disabled";
+-
+-			dwc_0: usb@8a00000 {
+-				compatible = "snps,dwc3";
+-				reg = <0x0 0x8a00000 0x0 0xcd00>;
+-				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+-				phys = <&qusb_phy_0>, <&usb0_ssphy>;
+-				phy-names = "usb2-phy", "usb3-phy";
+-				clocks = <&xo>;
+-				clock-names = "ref";
+-				tx-fifo-resize;
+-				snps,is-utmi-l1-suspend;
+-				snps,hird-threshold = /bits/ 8 <0x0>;
+-				snps,dis_u2_susphy_quirk;
+-				snps,dis_u3_susphy_quirk;
+-				dr_mode = "host";
+-			};
+ 		};
+ 	};
+ 
+@@ -792,26 +816,4 @@
+ 			#interrupt-cells = <2>;
+ 		};
+ 	};
+-
+-	rpm-glink {
+-		compatible = "qcom,glink-rpm";
+-		interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
+-		qcom,rpm-msg-ram = <&rpm_msg_ram>;
+-		mboxes = <&apcs_glb 0>;
+-
+-		rpm_requests: glink-channel {
+-			compatible = "qcom,rpm-ipq6018";
+-			qcom,glink-channels = "rpm_requests";
+-
+-			regulators {
+-				compatible = "qcom,rpm-mp5496-regulators";
+-
+-				ipq6018_s2: s2 {
+-					regulator-min-microvolt = <725000>;
+-					regulator-max-microvolt = <1062500>;
+-					regulator-always-on;
+-				};
+-			};
+-		};
+-	};
+ };
diff --git a/target/linux/qualcommax/patches-6.1/0035-v6.3-arm64-dts-qcom-ipq6018-Add-remove-some-newlines.patch b/target/linux/qualcommax/patches-6.1/0035-v6.3-arm64-dts-qcom-ipq6018-Add-remove-some-newlines.patch
new file mode 100644
index 00000000000000..a883e305dfd82b
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.1/0035-v6.3-arm64-dts-qcom-ipq6018-Add-remove-some-newlines.patch
@@ -0,0 +1,92 @@
+From 6db9ed9a128cbae1423d043f3debd8bfa77783fd Mon Sep 17 00:00:00 2001
+From: Konrad Dybcio <konrad.dybcio@linaro.org>
+Date: Mon, 2 Jan 2023 10:46:29 +0100
+Subject: [PATCH] arm64: dts: qcom: ipq6018: Add/remove some newlines
+
+Some lines were broken very aggresively, presumably to fit under 80 chars
+and some places could have used a newline, particularly between subsequent
+nodes. Address all that and remove redundant comments near PCIe ranges
+while at it so as not to exceed 100 chars needlessly.
+
+Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20230102094642.74254-5-konrad.dybcio@linaro.org
+---
+ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 26 ++++++++++++--------------
+ 1 file changed, 12 insertions(+), 14 deletions(-)
+
+--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+@@ -102,26 +102,31 @@
+ 			opp-microvolt = <725000>;
+ 			clock-latency-ns = <200000>;
+ 		};
++
+ 		opp-1056000000 {
+ 			opp-hz = /bits/ 64 <1056000000>;
+ 			opp-microvolt = <787500>;
+ 			clock-latency-ns = <200000>;
+ 		};
++
+ 		opp-1320000000 {
+ 			opp-hz = /bits/ 64 <1320000000>;
+ 			opp-microvolt = <862500>;
+ 			clock-latency-ns = <200000>;
+ 		};
++
+ 		opp-1440000000 {
+ 			opp-hz = /bits/ 64 <1440000000>;
+ 			opp-microvolt = <925000>;
+ 			clock-latency-ns = <200000>;
+ 		};
++
+ 		opp-1608000000 {
+ 			opp-hz = /bits/ 64 <1608000000>;
+ 			opp-microvolt = <987500>;
+ 			clock-latency-ns = <200000>;
+ 		};
++
+ 		opp-1800000000 {
+ 			opp-hz = /bits/ 64 <1800000000>;
+ 			opp-microvolt = <1062500>;
+@@ -131,8 +136,7 @@
+ 
+ 	pmuv8: pmu {
+ 		compatible = "arm,cortex-a53-pmu";
+-		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
+-					 IRQ_TYPE_LEVEL_HIGH)>;
++		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ 	};
+ 
+ 	psci: psci {
+@@ -734,24 +738,18 @@
+ 			phys = <&pcie_phy0>;
+ 			phy-names = "pciephy";
+ 
+-			ranges = <0x81000000 0 0x20200000 0 0x20200000
+-				  0 0x10000>, /* downstream I/O */
+-				 <0x82000000 0 0x20220000 0 0x20220000
+-				  0 0xfde0000>; /* non-prefetchable memory */
++			ranges = <0x81000000 0 0x20200000 0 0x20200000 0 0x10000>,
++				 <0x82000000 0 0x20220000 0 0x20220000 0 0xfde0000>;
+ 
+ 			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ 			interrupt-names = "msi";
+ 
+ 			#interrupt-cells = <1>;
+ 			interrupt-map-mask = <0 0 0 0x7>;
+-			interrupt-map = <0 0 0 1 &intc 0 75
+-					 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+-					<0 0 0 2 &intc 0 78
+-					 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+-					<0 0 0 3 &intc 0 79
+-					 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+-					<0 0 0 4 &intc 0 83
+-					 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
++			interrupt-map = <0 0 0 1 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
++					<0 0 0 2 &intc 0 78 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
++					<0 0 0 3 &intc 0 79 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
++					<0 0 0 4 &intc 0 83 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+ 
+ 			clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
+ 				 <&gcc GCC_PCIE0_AXI_M_CLK>,
diff --git a/target/linux/qualcommax/patches-6.1/0036-v6.3-arm64-dts-qcom-ipq6018-Use-lowercase-hex.patch b/target/linux/qualcommax/patches-6.1/0036-v6.3-arm64-dts-qcom-ipq6018-Use-lowercase-hex.patch
new file mode 100644
index 00000000000000..35aa46bb10aec9
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.1/0036-v6.3-arm64-dts-qcom-ipq6018-Use-lowercase-hex.patch
@@ -0,0 +1,25 @@
+From 7356ae3e10abd1d71f06ff0b8a8e72aa7c955c57 Mon Sep 17 00:00:00 2001
+From: Konrad Dybcio <konrad.dybcio@linaro.org>
+Date: Mon, 2 Jan 2023 10:46:30 +0100
+Subject: [PATCH] arm64: dts: qcom: ipq6018: Use lowercase hex
+
+One value escaped my previous lowercase hexification. Take care of it.
+
+Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20230102094642.74254-6-konrad.dybcio@linaro.org
+---
+ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+@@ -381,7 +381,7 @@
+ 
+ 		usb2: usb@70f8800 {
+ 			compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
+-			reg = <0x0 0x070F8800 0x0 0x400>;
++			reg = <0x0 0x070f8800 0x0 0x400>;
+ 			#address-cells = <2>;
+ 			#size-cells = <2>;
+ 			ranges;
diff --git a/target/linux/qualcommax/patches-6.1/0037-v6.3-arm64-dts-qcom-ipq6018-align-RPM-G-Link-node-with.patch b/target/linux/qualcommax/patches-6.1/0037-v6.3-arm64-dts-qcom-ipq6018-align-RPM-G-Link-node-with.patch
new file mode 100644
index 00000000000000..c939d126bf70cb
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.1/0037-v6.3-arm64-dts-qcom-ipq6018-align-RPM-G-Link-node-with.patch
@@ -0,0 +1,28 @@
+From 679ee73bbee28cab441008f8cca38160cc8f3d05 Mon Sep 17 00:00:00 2001
+From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Date: Wed, 8 Feb 2023 11:15:39 +0100
+Subject: [PATCH] arm64: dts: qcom: ipq6018: align RPM G-Link node with
+ bindings
+
+Bindings expect (and most of DTS use) the RPM G-Link node name to be
+"rpm-requests".
+
+Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20230208101545.45711-1-krzysztof.kozlowski@linaro.org
+---
+ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+@@ -176,7 +176,7 @@
+ 		qcom,rpm-msg-ram = <&rpm_msg_ram>;
+ 		mboxes = <&apcs_glb 0>;
+ 
+-		rpm_requests: glink-channel {
++		rpm_requests: rpm-requests {
+ 			compatible = "qcom,rpm-ipq6018";
+ 			qcom,glink-channels = "rpm_requests";
+ 
diff --git a/target/linux/qualcommax/patches-6.1/0038-v6.4-arm64-dts-qcom-ipq6018-cp01-c1-drop-SPI-cs-select.patch b/target/linux/qualcommax/patches-6.1/0038-v6.4-arm64-dts-qcom-ipq6018-cp01-c1-drop-SPI-cs-select.patch
new file mode 100644
index 00000000000000..28688069b8e87f
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.1/0038-v6.4-arm64-dts-qcom-ipq6018-cp01-c1-drop-SPI-cs-select.patch
@@ -0,0 +1,27 @@
+From afa8eb675fc6dd606783ed2350de90927d6fb9d3 Mon Sep 17 00:00:00 2001
+From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Date: Wed, 8 Mar 2023 13:59:01 +0100
+Subject: [PATCH] arm64: dts: qcom: ipq6018-cp01-c1: drop SPI cs-select
+
+The SPI controller nodes do not use/allow cs-select property:
+
+  ipq6018-cp01-c1.dtb: spi@78b5000: Unevaluated properties are not allowed ('cs-select' was unexpected)
+
+Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20230308125906.236885-6-krzysztof.kozlowski@linaro.org
+---
+ arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 1 -
+ 1 file changed, 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
++++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
+@@ -36,7 +36,6 @@
+ };
+ 
+ &blsp1_spi1 {
+-	cs-select = <0>;
+ 	pinctrl-0 = <&spi_0_pins>;
+ 	pinctrl-names = "default";
+ 	status = "okay";
diff --git a/target/linux/qualcommax/patches-6.1/0039-v6.5-arm64-dts-qcom-add-few-more-reserved-memory-region.patch b/target/linux/qualcommax/patches-6.1/0039-v6.5-arm64-dts-qcom-add-few-more-reserved-memory-region.patch
new file mode 100644
index 00000000000000..d1280b528bec62
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.1/0039-v6.5-arm64-dts-qcom-add-few-more-reserved-memory-region.patch
@@ -0,0 +1,92 @@
+From 0cd4e90cb2dec02ff859f5c98f744f43a23aea65 Mon Sep 17 00:00:00 2001
+From: Vignesh Viswanathan <quic_viswanat@quicinc.com>
+Date: Fri, 26 May 2023 16:36:53 +0530
+Subject: [PATCH] arm64: dts: qcom: add few more reserved memory region
+
+In IPQ SoCs, bootloader will collect the system RAM contents upon crash
+for the post morterm analysis. If we don't reserve the memory region used
+by bootloader, obviously linux will consume it and upon next boot on
+crash, bootloader will be loaded in the same region, which will lead to
+loose some of the data, sometimes we may miss out critical information.
+So lets reserve the region used by the bootloader.
+
+Similarly SBL copies some data into the reserved region and it will be
+used in the crash scenario. So reserve 1MB for SBL as well.
+
+While at it, drop the size padding in the reserved memory region,
+wherever applicable.
+
+Signed-off-by: Vignesh Viswanathan <quic_viswanat@quicinc.com>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20230526110653.27777-4-quic_viswanat@quicinc.com
+---
+ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 16 +++++++++++++---
+ arch/arm64/boot/dts/qcom/ipq8074.dtsi | 14 ++++++++++++--
+ 2 files changed, 25 insertions(+), 5 deletions(-)
+
+--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+@@ -154,18 +154,28 @@
+ 			no-map;
+ 		};
+ 
++		bootloader@4a100000 {
++			reg = <0x0 0x4a100000 0x0 0x400000>;
++			no-map;
++		};
++
++		sbl@4a500000 {
++			reg = <0x0 0x4a500000 0x0 0x100000>;
++			no-map;
++		};
++
+ 		tz: memory@4a600000 {
+-			reg = <0x0 0x4a600000 0x0 0x00400000>;
++			reg = <0x0 0x4a600000 0x0 0x400000>;
+ 			no-map;
+ 		};
+ 
+ 		smem_region: memory@4aa00000 {
+-			reg = <0x0 0x4aa00000 0x0 0x00100000>;
++			reg = <0x0 0x4aa00000 0x0 0x100000>;
+ 			no-map;
+ 		};
+ 
+ 		q6_region: memory@4ab00000 {
+-			reg = <0x0 0x4ab00000 0x0 0x05500000>;
++			reg = <0x0 0x4ab00000 0x0 0x5500000>;
+ 			no-map;
+ 		};
+ 	};
+--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+@@ -85,17 +85,27 @@
+ 		#size-cells = <2>;
+ 		ranges;
+ 
++		bootloader@4a600000 {
++			reg = <0x0 0x4a600000 0x0 0x400000>;
++			no-map;
++		};
++
++		sbl@4aa00000 {
++			reg = <0x0 0x4aa00000 0x0 0x100000>;
++			no-map;
++		};
++
+ 		smem@4ab00000 {
+ 			compatible = "qcom,smem";
+-			reg = <0x0 0x4ab00000 0x0 0x00100000>;
++			reg = <0x0 0x4ab00000 0x0 0x100000>;
+ 			no-map;
+ 
+ 			hwlocks = <&tcsr_mutex 3>;
+ 		};
+ 
+ 		memory@4ac00000 {
++			reg = <0x0 0x4ac00000 0x0 0x400000>;
+ 			no-map;
+-			reg = <0x0 0x4ac00000 0x0 0x00400000>;
+ 		};
+ 	};
+ 
diff --git a/target/linux/qualcommax/patches-6.1/0040-v6.5-arm64-dts-qcom-enable-the-download-mode-support.patch b/target/linux/qualcommax/patches-6.1/0040-v6.5-arm64-dts-qcom-enable-the-download-mode-support.patch
new file mode 100644
index 00000000000000..6dd185f6e0607f
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.1/0040-v6.5-arm64-dts-qcom-enable-the-download-mode-support.patch
@@ -0,0 +1,49 @@
+From 9b2406aaba7841863ac041225316c1ec1c86ea36 Mon Sep 17 00:00:00 2001
+From: Vignesh Viswanathan <quic_viswanat@quicinc.com>
+Date: Fri, 26 May 2023 16:36:52 +0530
+Subject: [PATCH] arm64: dts: qcom: enable the download mode support
+
+Like any other Qualcomm SoCs, IPQ8074 and IPQ6018 also supports the
+download mode to collect the RAM dumps if system crashes, to perform
+the post mortem analysis. Add support for the same.
+
+Signed-off-by: Vignesh Viswanathan <quic_viswanat@quicinc.com>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20230526110653.27777-3-quic_viswanat@quicinc.com
+---
+ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 1 +
+ arch/arm64/boot/dts/qcom/ipq8074.dtsi | 6 ++++++
+ 2 files changed, 7 insertions(+)
+
+--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+@@ -90,6 +90,7 @@
+ 	firmware {
+ 		scm {
+ 			compatible = "qcom,scm-ipq6018", "qcom,scm";
++			qcom,dload-mode = <&tcsr 0x6100>;
+ 		};
+ 	};
+ 
+--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+@@ -112,6 +112,7 @@
+ 	firmware {
+ 		scm {
+ 			compatible = "qcom,scm-ipq8074", "qcom,scm";
++			qcom,dload-mode = <&tcsr 0x6100>;
+ 		};
+ 	};
+ 
+@@ -386,6 +387,11 @@
+ 			#hwlock-cells = <1>;
+ 		};
+ 
++		tcsr: syscon@1937000 {
++			compatible = "qcom,tcsr-ipq8074", "syscon";
++			reg = <0x01937000 0x21000>;
++		};
++
+ 		spmi_bus: spmi@200f000 {
+ 			compatible = "qcom,spmi-pmic-arb";
+ 			reg = <0x0200f000 0x001000>,
diff --git a/target/linux/qualcommax/patches-6.1/0041-v6.5-arm64-dts-qcom-ipq6018-correct-qrng-unit-address.patch b/target/linux/qualcommax/patches-6.1/0041-v6.5-arm64-dts-qcom-ipq6018-correct-qrng-unit-address.patch
new file mode 100644
index 00000000000000..e9b92b596e92b2
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.1/0041-v6.5-arm64-dts-qcom-ipq6018-correct-qrng-unit-address.patch
@@ -0,0 +1,29 @@
+From 085058786a7890dd44ec623fe5ac74db870f6b93 Mon Sep 17 00:00:00 2001
+From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Date: Wed, 19 Apr 2023 23:18:39 +0200
+Subject: [PATCH] arm64: dts: qcom: ipq6018: correct qrng unit address
+
+Match unit-address to reg entry to fix dtbs W=1 warnings:
+
+  Warning (simple_bus_reg): /soc/qrng@e1000: simple-bus unit address format error, expected "e3000"
+
+Fixes: 5bf635621245 ("arm64: dts: ipq6018: Add a few device nodes")
+Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20230419211856.79332-1-krzysztof.kozlowski@linaro.org
+---
+ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+@@ -312,7 +312,7 @@
+ 			status = "disabled";
+ 		};
+ 
+-		prng: qrng@e1000 {
++		prng: qrng@e3000 {
+ 			compatible = "qcom,prng-ee";
+ 			reg = <0x0 0x000e3000 0x0 0x1000>;
+ 			clocks = <&gcc GCC_PRNG_AHB_CLK>;
diff --git a/target/linux/qualcommax/patches-6.1/0042-v6.5-arm64-dts-qcom-ipq6018-add-unit-address-to-soc-node.patch b/target/linux/qualcommax/patches-6.1/0042-v6.5-arm64-dts-qcom-ipq6018-add-unit-address-to-soc-node.patch
new file mode 100644
index 00000000000000..821c9890c6a6dd
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.1/0042-v6.5-arm64-dts-qcom-ipq6018-add-unit-address-to-soc-node.patch
@@ -0,0 +1,28 @@
+From 393595d4ffbd0a1fafd5548f8de1b8487a037cf2 Mon Sep 17 00:00:00 2001
+From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Date: Thu, 20 Apr 2023 08:36:04 +0200
+Subject: [PATCH] arm64: dts: qcom: ipq6018: add unit address to soc node
+
+"soc" node is supposed to have unit address:
+
+  Warning (unit_address_vs_reg): /soc: node has a reg or ranges property, but no unit name
+
+Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20230420063610.11068-1-krzysztof.kozlowski@linaro.org
+---
+ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+@@ -209,7 +209,7 @@
+ 		hwlocks = <&tcsr_mutex 3>;
+ 	};
+ 
+-	soc: soc {
++	soc: soc@0 {
+ 		#address-cells = <2>;
+ 		#size-cells = <2>;
+ 		ranges = <0 0 0 0 0x0 0xffffffff>;
diff --git a/target/linux/qualcommax/patches-6.1/0043-v6.5-arm64-dts-qcom-ipq6018-add-QFPROM-node.patch b/target/linux/qualcommax/patches-6.1/0043-v6.5-arm64-dts-qcom-ipq6018-add-QFPROM-node.patch
new file mode 100644
index 00000000000000..68895c5c962df2
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.1/0043-v6.5-arm64-dts-qcom-ipq6018-add-QFPROM-node.patch
@@ -0,0 +1,34 @@
+From 546f0617a22a481f3ca1f7e058aea0c40517c64e Mon Sep 17 00:00:00 2001
+From: Kathiravan T <quic_kathirav@quicinc.com>
+Date: Fri, 26 May 2023 18:23:04 +0530
+Subject: [PATCH] arm64: dts: qcom: ipq6018: add QFPROM node
+
+IPQ6018 has efuse region to determine the various HW quirks. Lets
+add the initial support and the individual fuses will be added as they
+are required.
+
+Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
+Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20230526125305.19626-4-quic_kathirav@quicinc.com
+---
+ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+@@ -312,6 +312,13 @@
+ 			status = "disabled";
+ 		};
+ 
++		qfprom: efuse@a4000 {
++			compatible = "qcom,ipq6018-qfprom", "qcom,qfprom";
++			reg = <0x0 0x000a4000 0x0 0x2000>;
++			#address-cells = <1>;
++			#size-cells = <1>;
++		};
++
+ 		prng: qrng@e3000 {
+ 			compatible = "qcom,prng-ee";
+ 			reg = <0x0 0x000e3000 0x0 0x1000>;
diff --git a/target/linux/qualcommax/patches-6.1/0044-v6.5-arm64-dts-qcom-ipq6018-drop-incorrect-SPI-bus.patch b/target/linux/qualcommax/patches-6.1/0044-v6.5-arm64-dts-qcom-ipq6018-drop-incorrect-SPI-bus.patch
new file mode 100644
index 00000000000000..b2057e588ea495
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.1/0044-v6.5-arm64-dts-qcom-ipq6018-drop-incorrect-SPI-bus.patch
@@ -0,0 +1,37 @@
+From b8420d478aa3fc739fcdba6b4b945850b356cb3b Mon Sep 17 00:00:00 2001
+From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Date: Sun, 16 Apr 2023 14:37:25 +0200
+Subject: [PATCH] arm64: dts: qcom: ipq6018: drop incorrect SPI bus
+ spi-max-frequency
+
+The spi-max-frequency property belongs to SPI devices, not SPI
+controller:
+
+  ipq6018-cp01-c1.dtb: spi@78b5000: Unevaluated properties are not allowed ('spi-max-frequency' was unexpected)
+
+Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20230416123730.300863-1-krzysztof.kozlowski@linaro.org
+---
+ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 --
+ 1 file changed, 2 deletions(-)
+
+--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+@@ -458,7 +458,6 @@
+ 			#size-cells = <0>;
+ 			reg = <0x0 0x078b5000 0x0 0x600>;
+ 			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+-			spi-max-frequency = <50000000>;
+ 			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
+ 				 <&gcc GCC_BLSP1_AHB_CLK>;
+ 			clock-names = "core", "iface";
+@@ -473,7 +472,6 @@
+ 			#size-cells = <0>;
+ 			reg = <0x0 0x078b6000 0x0 0x600>;
+ 			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+-			spi-max-frequency = <50000000>;
+ 			clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
+ 				 <&gcc GCC_BLSP1_AHB_CLK>;
+ 			clock-names = "core", "iface";
diff --git a/target/linux/qualcommax/patches-6.1/0045-v6.5-arm64-dts-qcom-ipq8074-drop-incorrect-SPI-bus.patch b/target/linux/qualcommax/patches-6.1/0045-v6.5-arm64-dts-qcom-ipq8074-drop-incorrect-SPI-bus.patch
new file mode 100644
index 00000000000000..52ba16cc9f34cd
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.1/0045-v6.5-arm64-dts-qcom-ipq8074-drop-incorrect-SPI-bus.patch
@@ -0,0 +1,29 @@
+From e6e0e706940b64e3a77e0a4840037692f109bd5f Mon Sep 17 00:00:00 2001
+From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Date: Sun, 16 Apr 2023 14:37:26 +0200
+Subject: [PATCH] arm64: dts: qcom: ipq8074: drop incorrect SPI bus
+ spi-max-frequency
+
+The spi-max-frequency property belongs to SPI devices, not SPI
+controller:
+
+  ipq8074-hk01.dtb: spi@78b5000: Unevaluated properties are not allowed ('spi-max-frequency' was unexpected)
+
+Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20230416123730.300863-2-krzysztof.kozlowski@linaro.org
+---
+ arch/arm64/boot/dts/qcom/ipq8074.dtsi | 1 -
+ 1 file changed, 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+@@ -487,7 +487,6 @@
+ 			#size-cells = <0>;
+ 			reg = <0x078b5000 0x600>;
+ 			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+-			spi-max-frequency = <50000000>;
+ 			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
+ 				<&gcc GCC_BLSP1_AHB_CLK>;
+ 			clock-names = "core", "iface";
diff --git a/target/linux/qualcommax/patches-6.1/0046-v6.6-clk-qcom-gcc-ipq6018-Use-floor-ops-for-sdcc-clocks.patch b/target/linux/qualcommax/patches-6.1/0046-v6.6-clk-qcom-gcc-ipq6018-Use-floor-ops-for-sdcc-clocks.patch
new file mode 100644
index 00000000000000..9ae72730d8f711
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.1/0046-v6.6-clk-qcom-gcc-ipq6018-Use-floor-ops-for-sdcc-clocks.patch
@@ -0,0 +1,27 @@
+From 56e5ae0116aef87273cf1812d608645b076e4f02 Mon Sep 17 00:00:00 2001
+From: Mantas Pucka <mantas@8devices.com>
+Date: Tue, 25 Apr 2023 12:11:49 +0300
+Subject: [PATCH] clk: qcom: gcc-ipq6018: Use floor ops for sdcc clocks
+
+SDCC clocks must be rounded down to avoid overclocking the controller.
+
+Fixes: d9db07f088af ("clk: qcom: Add ipq6018 Global Clock Controller support")
+Signed-off-by: Mantas Pucka <mantas@8devices.com>
+Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/1682413909-24927-1-git-send-email-mantas@8devices.com
+---
+ drivers/clk/qcom/gcc-ipq6018.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/clk/qcom/gcc-ipq6018.c
++++ b/drivers/clk/qcom/gcc-ipq6018.c
+@@ -1702,7 +1702,7 @@ static struct clk_rcg2 usb0_mock_utmi_cl
+ 		.name = "usb0_mock_utmi_clk_src",
+ 		.parent_data = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
+ 		.num_parents = 4,
+-		.ops = &clk_rcg2_ops,
++		.ops = &clk_rcg2_floor_ops,
+ 	},
+ };
+ 
diff --git a/target/linux/qualcommax/patches-6.1/0047-v6.6-clk-qcom-gcc-ipq6018-drop-redundant-F-define.patch b/target/linux/qualcommax/patches-6.1/0047-v6.6-clk-qcom-gcc-ipq6018-drop-redundant-F-define.patch
new file mode 100644
index 00000000000000..19dc9482e67df4
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.1/0047-v6.6-clk-qcom-gcc-ipq6018-drop-redundant-F-define.patch
@@ -0,0 +1,27 @@
+From 923f7d678b2ae3d522543058514d5605c185633b Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Mon, 17 Apr 2023 19:44:07 +0200
+Subject: [PATCH] clk: qcom: gcc-ipq6018: drop redundant F define
+
+The same exact F frequency table entry is defined in clk-rcg.h
+Drop the redundant define to cleanup code.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20230417174408.23722-1-ansuelsmth@gmail.com
+---
+ drivers/clk/qcom/gcc-ipq6018.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+--- a/drivers/clk/qcom/gcc-ipq6018.c
++++ b/drivers/clk/qcom/gcc-ipq6018.c
+@@ -26,8 +26,6 @@
+ #include "clk-regmap-mux.h"
+ #include "reset.h"
+ 
+-#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
+-
+ enum {
+ 	P_XO,
+ 	P_BIAS_PLL,
diff --git a/target/linux/qualcommax/patches-6.1/0048-v6.6-clk-qcom-gcc-ipq6018-update-UBI32-PLL.patch b/target/linux/qualcommax/patches-6.1/0048-v6.6-clk-qcom-gcc-ipq6018-update-UBI32-PLL.patch
new file mode 100644
index 00000000000000..e38b40278cb4ef
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.1/0048-v6.6-clk-qcom-gcc-ipq6018-update-UBI32-PLL.patch
@@ -0,0 +1,39 @@
+From f4f0c8acee0e41c5fbae7a7ad06087668ddce0d6 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Fri, 26 May 2023 21:08:54 +0200
+Subject: [PATCH] clk: qcom: gcc-ipq6018: update UBI32 PLL
+
+Update the UBI32 alpha PLL config to the latest values from the downstream
+QCA 5.4 kernel.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20230526190855.2941291-1-robimarko@gmail.com
+---
+ drivers/clk/qcom/gcc-ipq6018.c | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+--- a/drivers/clk/qcom/gcc-ipq6018.c
++++ b/drivers/clk/qcom/gcc-ipq6018.c
+@@ -4143,15 +4143,20 @@ static struct clk_branch gcc_dcc_clk = {
+ 
+ static const struct alpha_pll_config ubi32_pll_config = {
+ 	.l = 0x3e,
+-	.alpha = 0x57,
++	.alpha = 0x6667,
+ 	.config_ctl_val = 0x240d6aa8,
+ 	.config_ctl_hi_val = 0x3c2,
++	.config_ctl_val = 0x240d4828,
++	.config_ctl_hi_val = 0x6,
+ 	.main_output_mask = BIT(0),
+ 	.aux_output_mask = BIT(1),
+ 	.pre_div_val = 0x0,
+ 	.pre_div_mask = BIT(12),
+ 	.post_div_val = 0x0,
+ 	.post_div_mask = GENMASK(9, 8),
++	.alpha_en_mask = BIT(24),
++	.test_ctl_val = 0x1C0000C0,
++	.test_ctl_hi_val = 0x4000,
+ };
+ 
+ static const struct alpha_pll_config nss_crypto_pll_config = {
diff --git a/target/linux/qualcommax/patches-6.1/0049-v6.6-clk-qcom-gcc-ipq6018-remove-duplicate-initializers.patch b/target/linux/qualcommax/patches-6.1/0049-v6.6-clk-qcom-gcc-ipq6018-remove-duplicate-initializers.patch
new file mode 100644
index 00000000000000..e4faac1b6e2c64
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.1/0049-v6.6-clk-qcom-gcc-ipq6018-remove-duplicate-initializers.patch
@@ -0,0 +1,38 @@
+From 5ae7899765607e97e5eb34486336898c8d9ec654 Mon Sep 17 00:00:00 2001
+From: Arnd Bergmann <arnd@arndb.de>
+Date: Thu, 1 Jun 2023 23:34:12 +0200
+Subject: [PATCH] clk: qcom: gcc-ipq6018: remove duplicate initializers
+
+A recent change added new initializers for .config_ctl_val and
+.config_ctl_hi_val but left the old values in place:
+
+drivers/clk/qcom/gcc-ipq6018.c:4155:27: error: initialized field overwritten [-Werror=override-init]
+ 4155 |         .config_ctl_val = 0x240d4828,
+      |                           ^~~~~~~~~~
+drivers/clk/qcom/gcc-ipq6018.c:4156:30: error: initialized field overwritten [-Werror=override-init]
+ 4156 |         .config_ctl_hi_val = 0x6,
+      |                              ^~~
+
+Remove the unused ones now to avoid confusion.
+
+Fixes: f4f0c8acee0e4 ("clk: qcom: gcc-ipq6018: update UBI32 PLL")
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+Reviewed-by: Robert Marko <robimarko@gmail.com>
+Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20230601213416.3373599-1-arnd@kernel.org
+---
+ drivers/clk/qcom/gcc-ipq6018.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+--- a/drivers/clk/qcom/gcc-ipq6018.c
++++ b/drivers/clk/qcom/gcc-ipq6018.c
+@@ -4144,8 +4144,6 @@ static struct clk_branch gcc_dcc_clk = {
+ static const struct alpha_pll_config ubi32_pll_config = {
+ 	.l = 0x3e,
+ 	.alpha = 0x6667,
+-	.config_ctl_val = 0x240d6aa8,
+-	.config_ctl_hi_val = 0x3c2,
+ 	.config_ctl_val = 0x240d4828,
+ 	.config_ctl_hi_val = 0x6,
+ 	.main_output_mask = BIT(0),
diff --git a/target/linux/qualcommax/patches-6.1/0050-v6.6-soc-qcom-Add-RPM-processor-subsystem-driver.patch b/target/linux/qualcommax/patches-6.1/0050-v6.6-soc-qcom-Add-RPM-processor-subsystem-driver.patch
new file mode 100644
index 00000000000000..c2c26fb079830b
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.1/0050-v6.6-soc-qcom-Add-RPM-processor-subsystem-driver.patch
@@ -0,0 +1,132 @@
+From 8ddfa81d090c71fd6cb3cb8ca1d420c0da33a575 Mon Sep 17 00:00:00 2001
+From: Stephan Gerhold <stephan@gerhold.net>
+Date: Thu, 15 Jun 2023 18:50:42 +0200
+Subject: [PATCH] soc: qcom: Add RPM processor/subsystem driver
+
+Add a simple driver for the qcom,rpm-proc compatible that registers the
+"smd-edge" and populates other children defined in the device tree.
+
+Note that the DT schema belongs to the remoteproc subsystem while this
+driver is added inside soc/qcom. I argue that the RPM *is* a remoteproc,
+but as an implementation detail in Linux it can currently not benefit
+from anything provided by the remoteproc subsystem. The RPM firmware is
+usually already loaded and started by earlier components in the boot
+chain and is not meant to be ever restarted.
+
+To avoid breaking existing kernel configurations the driver is always
+built when smd-rpm.c is also built. They belong closely together anyway.
+To avoid build errors CONFIG_RPMSG_QCOM_SMD must be also built-in if
+rpm-proc is.
+
+Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
+Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
+Link: https://lore.kernel.org/r/20230531-rpm-rproc-v3-9-a07dcdefd918@gerhold.net
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+---
+ drivers/soc/qcom/Kconfig    |  1 +
+ drivers/soc/qcom/Makefile   |  2 +-
+ drivers/soc/qcom/rpm-proc.c | 77 +++++++++++++++++++++++++++++++++++++
+ 3 files changed, 79 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/soc/qcom/rpm-proc.c
+
+--- a/drivers/soc/qcom/Kconfig
++++ b/drivers/soc/qcom/Kconfig
+@@ -153,6 +153,7 @@ config QCOM_SMD_RPM
+ 	tristate "Qualcomm Resource Power Manager (RPM) over SMD"
+ 	depends on ARCH_QCOM || COMPILE_TEST
+ 	depends on RPMSG
++	depends on RPMSG_QCOM_SMD || RPMSG_QCOM_SMD=n
+ 	help
+ 	  If you say yes to this option, support will be included for the
+ 	  Resource Power Manager system found in the Qualcomm 8974 based
+--- a/drivers/soc/qcom/Makefile
++++ b/drivers/soc/qcom/Makefile
+@@ -14,7 +14,7 @@ obj-$(CONFIG_QCOM_RMTFS_MEM)	+= rmtfs_me
+ obj-$(CONFIG_QCOM_RPMH)		+= qcom_rpmh.o
+ qcom_rpmh-y			+= rpmh-rsc.o
+ qcom_rpmh-y			+= rpmh.o
+-obj-$(CONFIG_QCOM_SMD_RPM)	+= smd-rpm.o
++obj-$(CONFIG_QCOM_SMD_RPM)	+= rpm-proc.o smd-rpm.o
+ obj-$(CONFIG_QCOM_SMEM) +=	smem.o
+ obj-$(CONFIG_QCOM_SMEM_STATE) += smem_state.o
+ obj-$(CONFIG_QCOM_SMP2P)	+= smp2p.o
+--- /dev/null
++++ b/drivers/soc/qcom/rpm-proc.c
+@@ -0,0 +1,77 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/* Copyright (c) 2021-2023, Stephan Gerhold <stephan@gerhold.net> */
++
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_platform.h>
++#include <linux/platform_device.h>
++#include <linux/rpmsg/qcom_smd.h>
++
++static int rpm_proc_probe(struct platform_device *pdev)
++{
++	struct qcom_smd_edge *edge = NULL;
++	struct device *dev = &pdev->dev;
++	struct device_node *edge_node;
++	int ret;
++
++	edge_node = of_get_child_by_name(dev->of_node, "smd-edge");
++	if (edge_node) {
++		edge = qcom_smd_register_edge(dev, edge_node);
++		of_node_put(edge_node);
++		if (IS_ERR(edge))
++			return dev_err_probe(dev, PTR_ERR(edge),
++					     "Failed to register smd-edge\n");
++	}
++
++	ret = devm_of_platform_populate(dev);
++	if (ret) {
++		dev_err(dev, "Failed to populate child devices: %d\n", ret);
++		goto err;
++	}
++
++	platform_set_drvdata(pdev, edge);
++	return 0;
++err:
++	if (edge)
++		qcom_smd_unregister_edge(edge);
++	return ret;
++}
++
++static void rpm_proc_remove(struct platform_device *pdev)
++{
++	struct qcom_smd_edge *edge = platform_get_drvdata(pdev);
++
++	if (edge)
++		qcom_smd_unregister_edge(edge);
++}
++
++static const struct of_device_id rpm_proc_of_match[] = {
++	{ .compatible = "qcom,rpm-proc", },
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, rpm_proc_of_match);
++
++static struct platform_driver rpm_proc_driver = {
++	.probe = rpm_proc_probe,
++	.remove_new = rpm_proc_remove,
++	.driver = {
++		.name = "qcom-rpm-proc",
++		.of_match_table = rpm_proc_of_match,
++	},
++};
++
++static int __init rpm_proc_init(void)
++{
++	return platform_driver_register(&rpm_proc_driver);
++}
++arch_initcall(rpm_proc_init);
++
++static void __exit rpm_proc_exit(void)
++{
++	platform_driver_unregister(&rpm_proc_driver);
++}
++module_exit(rpm_proc_exit);
++
++MODULE_DESCRIPTION("Qualcomm RPM processor/subsystem driver");
++MODULE_AUTHOR("Stephan Gerhold <stephan@gerhold.net>");
++MODULE_LICENSE("GPL");
diff --git a/target/linux/qualcommax/patches-6.1/0051-v6.6-arm64-dts-qcom-Add-rpm-proc-node-for-GLINK.patch b/target/linux/qualcommax/patches-6.1/0051-v6.6-arm64-dts-qcom-Add-rpm-proc-node-for-GLINK.patch
new file mode 100644
index 00000000000000..746a391b42e8fc
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.1/0051-v6.6-arm64-dts-qcom-Add-rpm-proc-node-for-GLINK.patch
@@ -0,0 +1,93 @@
+From 7e1acc8b92a3b67db1e5255adae2851d58d74434 Mon Sep 17 00:00:00 2001
+From: Stephan Gerhold <stephan@gerhold.net>
+Date: Thu, 15 Jun 2023 18:50:44 +0200
+Subject: [PATCH] arm64: dts: qcom: Add rpm-proc node for GLINK gplatforms
+
+Rather than having the RPM GLINK channels as the only child of a dummy
+top-level rpm-glink node, switch to representing the RPM as remoteproc
+like all the other remoteprocs (modem DSP, ...).
+
+This allows assigning additional subdevices to it like the MPM
+interrupt-controller or rpm-master-stats.
+
+Tested-by: Konrad Dybcio <konrad.dybcio@linaro.org> # SM6375
+Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
+Link: https://lore.kernel.org/r/20230531-rpm-rproc-v3-11-a07dcdefd918@gerhold.net
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+---
+ arch/arm64/boot/dts/qcom/ipq6018.dtsi |  48 ++++----
+ arch/arm64/boot/dts/qcom/ipq9574.dtsi |  28 +++--
+ arch/arm64/boot/dts/qcom/msm8996.dtsi | 113 +++++++++----------
+ arch/arm64/boot/dts/qcom/msm8998.dtsi | 102 ++++++++---------
+ arch/arm64/boot/dts/qcom/qcm2290.dtsi | 126 ++++++++++-----------
+ arch/arm64/boot/dts/qcom/qcs404.dtsi  | 152 +++++++++++++-------------
+ arch/arm64/boot/dts/qcom/sdm630.dtsi  | 132 +++++++++++-----------
+ arch/arm64/boot/dts/qcom/sm6115.dtsi  | 128 +++++++++++-----------
+ arch/arm64/boot/dts/qcom/sm6125.dtsi  | 140 ++++++++++++------------
+ arch/arm64/boot/dts/qcom/sm6375.dtsi  | 126 ++++++++++-----------
+ 10 files changed, 566 insertions(+), 529 deletions(-)
+
+--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+@@ -145,6 +145,32 @@
+ 		method = "smc";
+ 	};
+ 
++	rpm: remoteproc {
++		compatible = "qcom,ipq6018-rpm-proc", "qcom,rpm-proc";
++
++		glink-edge {
++			compatible = "qcom,glink-rpm";
++			interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
++			qcom,rpm-msg-ram = <&rpm_msg_ram>;
++			mboxes = <&apcs_glb 0>;
++
++			rpm_requests: rpm-requests {
++				compatible = "qcom,rpm-ipq6018";
++				qcom,glink-channels = "rpm_requests";
++
++				regulators {
++					compatible = "qcom,rpm-mp5496-regulators";
++
++					ipq6018_s2: s2 {
++						regulator-min-microvolt = <725000>;
++						regulator-max-microvolt = <1062500>;
++						regulator-always-on;
++					};
++				};
++			};
++		};
++	};
++
+ 	reserved-memory {
+ 		#address-cells = <2>;
+ 		#size-cells = <2>;
+@@ -181,28 +207,6 @@
+ 		};
+ 	};
+ 
+-	rpm-glink {
+-		compatible = "qcom,glink-rpm";
+-		interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
+-		qcom,rpm-msg-ram = <&rpm_msg_ram>;
+-		mboxes = <&apcs_glb 0>;
+-
+-		rpm_requests: rpm-requests {
+-			compatible = "qcom,rpm-ipq6018";
+-			qcom,glink-channels = "rpm_requests";
+-
+-			regulators {
+-				compatible = "qcom,rpm-mp5496-regulators";
+-
+-				ipq6018_s2: s2 {
+-					regulator-min-microvolt = <725000>;
+-					regulator-max-microvolt = <1062500>;
+-					regulator-always-on;
+-				};
+-			};
+-		};
+-	};
+-
+ 	smem {
+ 		compatible = "qcom,smem";
+ 		memory-region = <&smem_region>;
diff --git a/target/linux/qualcommax/patches-6.1/0052-v6.7-arm64-dts-qcom-ipq6018-include-the-GPLL0-as.patch b/target/linux/qualcommax/patches-6.1/0052-v6.7-arm64-dts-qcom-ipq6018-include-the-GPLL0-as.patch
new file mode 100644
index 00000000000000..b70d7bf69c0af4
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.1/0052-v6.7-arm64-dts-qcom-ipq6018-include-the-GPLL0-as.patch
@@ -0,0 +1,35 @@
+From 0133c7af3aa0420778d106cb90db708cfa45f2c6 Mon Sep 17 00:00:00 2001
+From: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
+Date: Thu, 14 Sep 2023 12:29:59 +0530
+Subject: [PATCH] arm64: dts: qcom: ipq6018: include the GPLL0 as clock
+ provider for mailbox
+
+While the kernel is booting up, APSS clock / CPU clock will be running
+at 800MHz with GPLL0 as source. Once the cpufreq driver is available,
+APSS PLL will be configured to the rate based on the opp table and the
+source also will be changed to APSS_PLL_EARLY. So allow the mailbox to
+consume the GPLL0, with this inclusion, CPU Freq correctly reports that
+CPU is running at 800MHz rather than 24MHz.
+
+Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
+Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
+Link: https://lore.kernel.org/r/20230913-gpll_cleanup-v2-9-c8ceb1a37680@quicinc.com
+[bjorn: Updated commit message, as requested by Kathiravan]
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+---
+ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+@@ -618,8 +618,8 @@
+ 			compatible = "qcom,ipq6018-apcs-apps-global";
+ 			reg = <0x0 0x0b111000 0x0 0x1000>;
+ 			#clock-cells = <1>;
+-			clocks = <&a53pll>, <&xo>;
+-			clock-names = "pll", "xo";
++			clocks = <&a53pll>, <&xo>, <&gcc GPLL0>;
++			clock-names = "pll", "xo", "gpll0";
+ 			#mbox-cells = <1>;
+ 		};
+ 
diff --git a/target/linux/qualcommax/patches-6.1/0053-v6.7-clk-qcom-gcc-ipq6018-add-QUP6-I2C-clock.patch b/target/linux/qualcommax/patches-6.1/0053-v6.7-clk-qcom-gcc-ipq6018-add-QUP6-I2C-clock.patch
new file mode 100644
index 00000000000000..08585289332e07
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.1/0053-v6.7-clk-qcom-gcc-ipq6018-add-QUP6-I2C-clock.patch
@@ -0,0 +1,57 @@
+From 3dcf7b59393812a5fbd83f8cd8d34b94afb4c4d1 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Sat, 21 Oct 2023 13:55:18 +0200
+Subject: [PATCH] clk: qcom: gcc-ipq6018: add QUP6 I2C clock
+
+QUP6 I2C clock is listed in the dt bindings but it was never included in
+the GCC driver.
+So lets add support for it, it is marked as criticial as it is used by RPM
+to communicate to the external PMIC over I2C so this clock must not be
+disabled.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Reviewed-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
+Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
+Link: https://lore.kernel.org/r/20231021115545.229060-1-robimarko@gmail.com
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+---
+ drivers/clk/qcom/gcc-ipq6018.c | 21 +++++++++++++++++++++
+ 1 file changed, 21 insertions(+)
+
+--- a/drivers/clk/qcom/gcc-ipq6018.c
++++ b/drivers/clk/qcom/gcc-ipq6018.c
+@@ -2120,6 +2120,26 @@ static struct clk_branch gcc_blsp1_qup5_
+ 	},
+ };
+ 
++static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
++	.halt_reg = 0x07010,
++	.clkr = {
++		.enable_reg = 0x07010,
++		.enable_mask = BIT(0),
++		.hw.init = &(struct clk_init_data){
++			.name = "gcc_blsp1_qup6_i2c_apps_clk",
++			.parent_hws = (const struct clk_hw *[]){
++					&blsp1_qup6_i2c_apps_clk_src.clkr.hw },
++			.num_parents = 1,
++			/*
++			 * RPM uses QUP6 I2C to communicate with the external
++			 * PMIC so it must not be disabled.
++			 */
++			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
++			.ops = &clk_branch2_ops,
++		},
++	},
++};
++
+ static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
+ 	.halt_reg = 0x0700c,
+ 	.clkr = {
+@@ -4276,6 +4296,7 @@ static struct clk_regmap *gcc_ipq6018_cl
+ 	[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
+ 	[GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
+ 	[GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
++	[GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
+ 	[GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
+ 	[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
+ 	[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
diff --git a/target/linux/qualcommax/patches-6.1/0054-v6.8-arm64-dts-qcom-ipq6018-use-CPUFreq-NVMEM.patch b/target/linux/qualcommax/patches-6.1/0054-v6.8-arm64-dts-qcom-ipq6018-use-CPUFreq-NVMEM.patch
new file mode 100644
index 00000000000000..1369a90a8a72b0
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.1/0054-v6.8-arm64-dts-qcom-ipq6018-use-CPUFreq-NVMEM.patch
@@ -0,0 +1,85 @@
+From 83afcf14edb9217e58837eb119da96d734a4b3b1 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Sat, 21 Oct 2023 14:00:07 +0200
+Subject: [PATCH] arm64: dts: qcom: ipq6018: use CPUFreq NVMEM
+
+IPQ6018 comes in multiple SKU-s and some of them dont support all of the
+OPP-s that are current set, so lets utilize CPUFreq NVMEM to allow only
+supported OPP-s based on the SoC dynamically.
+
+As an example, IPQ6018 is generaly rated at 1.8GHz but some silicon only
+goes up to 1.5GHz and is marked as such via an eFuse.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
+Link: https://lore.kernel.org/r/20231021120048.231239-1-robimarko@gmail.com
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+---
+ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 14 +++++++++++++-
+ 1 file changed, 13 insertions(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+@@ -95,42 +95,49 @@
+ 	};
+ 
+ 	cpu_opp_table: opp-table-cpu {
+-		compatible = "operating-points-v2";
++		compatible = "operating-points-v2-kryo-cpu";
++		nvmem-cells = <&cpu_speed_bin>;
+ 		opp-shared;
+ 
+ 		opp-864000000 {
+ 			opp-hz = /bits/ 64 <864000000>;
+ 			opp-microvolt = <725000>;
++			opp-supported-hw = <0xf>;
+ 			clock-latency-ns = <200000>;
+ 		};
+ 
+ 		opp-1056000000 {
+ 			opp-hz = /bits/ 64 <1056000000>;
+ 			opp-microvolt = <787500>;
++			opp-supported-hw = <0xf>;
+ 			clock-latency-ns = <200000>;
+ 		};
+ 
+ 		opp-1320000000 {
+ 			opp-hz = /bits/ 64 <1320000000>;
+ 			opp-microvolt = <862500>;
++			opp-supported-hw = <0x3>;
+ 			clock-latency-ns = <200000>;
+ 		};
+ 
+ 		opp-1440000000 {
+ 			opp-hz = /bits/ 64 <1440000000>;
+ 			opp-microvolt = <925000>;
++			opp-supported-hw = <0x3>;
+ 			clock-latency-ns = <200000>;
+ 		};
+ 
+ 		opp-1608000000 {
+ 			opp-hz = /bits/ 64 <1608000000>;
+ 			opp-microvolt = <987500>;
++			opp-supported-hw = <0x1>;
+ 			clock-latency-ns = <200000>;
+ 		};
+ 
+ 		opp-1800000000 {
+ 			opp-hz = /bits/ 64 <1800000000>;
+ 			opp-microvolt = <1062500>;
++			opp-supported-hw = <0x1>;
+ 			clock-latency-ns = <200000>;
+ 		};
+ 	};
+@@ -321,6 +328,11 @@
+ 			reg = <0x0 0x000a4000 0x0 0x2000>;
+ 			#address-cells = <1>;
+ 			#size-cells = <1>;
++
++			cpu_speed_bin: cpu-speed-bin@135 {
++				reg = <0x135 0x1>;
++				bits = <7 1>;
++			};
+ 		};
+ 
+ 		prng: qrng@e3000 {
diff --git a/target/linux/qualcommax/patches-6.1/0055-v6.8-arm64-dts-ipq6018-Add-remaining-QUP-UART-node.patch b/target/linux/qualcommax/patches-6.1/0055-v6.8-arm64-dts-ipq6018-Add-remaining-QUP-UART-node.patch
new file mode 100644
index 00000000000000..ca3c89604706e0
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.1/0055-v6.8-arm64-dts-ipq6018-Add-remaining-QUP-UART-node.patch
@@ -0,0 +1,81 @@
+From e6c32770ef83f3e8cc057f3920b1c06aa9d1c9c2 Mon Sep 17 00:00:00 2001
+From: Chukun Pan <amadeus@jmu.edu.cn>
+Date: Sun, 3 Dec 2023 23:39:14 +0800
+Subject: [PATCH] arm64: dts: qcom: ipq6018: Add remaining QUP UART node
+
+Add node to support all the QUP UART node controller inside of IPQ6018.
+Some routers use these bus to connect Bluetooth chips.
+
+Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
+Link: https://lore.kernel.org/r/20231203153914.532654-1-amadeus@jmu.edu.cn
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+---
+ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 50 +++++++++++++++++++++++++++
+ 1 file changed, 50 insertions(+)
+
+--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+@@ -458,6 +458,26 @@
+ 			qcom,ee = <0>;
+ 		};
+ 
++		blsp1_uart1: serial@78af000 {
++			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
++			reg = <0x0 0x78af000 0x0 0x200>;
++			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
++				 <&gcc GCC_BLSP1_AHB_CLK>;
++			clock-names = "core", "iface";
++			status = "disabled";
++		};
++
++		blsp1_uart2: serial@78b0000 {
++			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
++			reg = <0x0 0x78b0000 0x0 0x200>;
++			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
++				 <&gcc GCC_BLSP1_AHB_CLK>;
++			clock-names = "core", "iface";
++			status = "disabled";
++		};
++
+ 		blsp1_uart3: serial@78b1000 {
+ 			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ 			reg = <0x0 0x078b1000 0x0 0x200>;
+@@ -466,6 +486,36 @@
+ 				 <&gcc GCC_BLSP1_AHB_CLK>;
+ 			clock-names = "core", "iface";
+ 			status = "disabled";
++		};
++
++		blsp1_uart4: serial@78b2000 {
++			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
++			reg = <0x0 0x078b2000 0x0 0x200>;
++			interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>,
++				 <&gcc GCC_BLSP1_AHB_CLK>;
++			clock-names = "core", "iface";
++			status = "disabled";
++		};
++
++		blsp1_uart5: serial@78b3000 {
++			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
++			reg = <0x0 0x78b3000 0x0 0x200>;
++			interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
++				 <&gcc GCC_BLSP1_AHB_CLK>;
++			clock-names = "core", "iface";
++			status = "disabled";
++		};
++
++		blsp1_uart6: serial@78b4000 {
++			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
++			reg = <0x0 0x078b4000 0x0 0x200>;
++			interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>,
++				 <&gcc GCC_BLSP1_AHB_CLK>;
++			clock-names = "core", "iface";
++			status = "disabled";
+ 		};
+ 
+ 		blsp1_spi1: spi@78b5000 {
diff --git a/target/linux/qualcommax/patches-6.1/0056-v6.9-arm64-dts-qcom-Fix-hs_phy_irq-for-QUSB2-targets.patch b/target/linux/qualcommax/patches-6.1/0056-v6.9-arm64-dts-qcom-Fix-hs_phy_irq-for-QUSB2-targets.patch
new file mode 100644
index 00000000000000..0f1b3e6a386ba5
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.1/0056-v6.9-arm64-dts-qcom-Fix-hs_phy_irq-for-QUSB2-targets.patch
@@ -0,0 +1,95 @@
+From 2c6597c72e9722ac020102d5af40126df0437b82 Mon Sep 17 00:00:00 2001
+From: Krishna Kurapati <quic_kriskura@quicinc.com>
+Date: Fri, 26 Jan 2024 00:29:18 +0530
+Subject: [PATCH] arm64: dts: qcom: Fix hs_phy_irq for QUSB2 targets
+
+On several QUSB2 Targets, the hs_phy_irq mentioned is actually
+qusb2_phy interrupt specific to QUSB2 PHY's. Rename hs_phy_irq
+to qusb2_phy for such targets.
+
+In actuality, the hs_phy_irq is also present in these targets, but
+kept in for debug purposes in hw test environments. This is not
+triggered by default and its functionality is mutually exclusive
+to that of qusb2_phy interrupt.
+
+Add missing hs_phy_irq's, pwr_event irq's for QUSB2 PHY targets.
+Add missing ss_phy_irq on some targets which allows for remote
+wakeup to work on a Super Speed link.
+
+Also modify order of interrupts in accordance to bindings update.
+Since driver looks up for interrupts by name and not by index, it
+is safe to modify order of these interrupts in the DT.
+
+Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
+Link: https://lore.kernel.org/r/20240125185921.5062-2-quic_kriskura@quicinc.com
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+---
+ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 13 +++++++++++++
+ arch/arm64/boot/dts/qcom/ipq8074.dtsi | 14 ++++++++++++++
+ arch/arm64/boot/dts/qcom/msm8953.dtsi |  7 +++++--
+ arch/arm64/boot/dts/qcom/msm8996.dtsi |  8 ++++++--
+ arch/arm64/boot/dts/qcom/msm8998.dtsi |  7 +++++--
+ arch/arm64/boot/dts/qcom/sdm630.dtsi  | 17 +++++++++++++----
+ arch/arm64/boot/dts/qcom/sm6115.dtsi  |  9 +++++++--
+ arch/arm64/boot/dts/qcom/sm6125.dtsi  |  9 +++++++--
+ 8 files changed, 70 insertions(+), 14 deletions(-)
+
+--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+@@ -430,6 +430,12 @@
+ 					  <&gcc GCC_USB1_MOCK_UTMI_CLK>;
+ 			assigned-clock-rates = <133330000>,
+ 					       <24000000>;
++
++			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "pwr_event",
++					  "qusb2_phy";
++
+ 			resets = <&gcc GCC_USB1_BCR>;
+ 			status = "disabled";
+ 
+@@ -628,6 +634,13 @@
+ 					       <133330000>,
+ 					       <24000000>;
+ 
++			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "pwr_event",
++					  "qusb2_phy",
++					  "ss_phy_irq";
++
+ 			resets = <&gcc GCC_USB0_BCR>;
+ 			status = "disabled";
+ 
+--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+@@ -611,6 +611,13 @@
+ 						<133330000>,
+ 						<19200000>;
+ 
++			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "pwr_event",
++					  "qusb2_phy",
++					  "ss_phy_irq";
++
+ 			power-domains = <&gcc USB0_GDSC>;
+ 
+ 			resets = <&gcc GCC_USB0_BCR>;
+@@ -653,6 +660,13 @@
+ 						<133330000>,
+ 						<19200000>;
+ 
++			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "pwr_event",
++					  "qusb2_phy",
++					  "ss_phy_irq";
++
+ 			power-domains = <&gcc USB1_GDSC>;
+ 
+ 			resets = <&gcc GCC_USB1_BCR>;
diff --git a/target/linux/qualcommax/patches-6.1/0057-v6.8-hwspinlock-qcom-Remove-IPQ6018-SOC-specific-.patch b/target/linux/qualcommax/patches-6.1/0057-v6.8-hwspinlock-qcom-Remove-IPQ6018-SOC-specific-.patch
new file mode 100644
index 00000000000000..25d56870a475df
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.1/0057-v6.8-hwspinlock-qcom-Remove-IPQ6018-SOC-specific-.patch
@@ -0,0 +1,32 @@
+From c3dc3d079d191c9149496b3c7fe1ece909386d93 Mon Sep 17 00:00:00 2001
+From: Vignesh Viswanathan <quic_viswanat@quicinc.com>
+Date: Tue, 5 Sep 2023 15:25:35 +0530
+Subject: [PATCH] hwspinlock: qcom: Remove IPQ6018 SOC specific compatible
+
+IPQ6018 has 32 tcsr_mutex hwlock registers with stride 0x1000.
+The compatible string qcom,ipq6018-tcsr-mutex is mapped to
+of_msm8226_tcsr_mutex which has 32 locks configured with stride of 0x80
+and doesn't match the HW present in IPQ6018.
+
+Remove IPQ6018 specific compatible string so that it fallsback to
+of_tcsr_mutex data which maps to the correct configuration for IPQ6018.
+
+Fixes: 5d4753f741d8 ("hwspinlock: qcom: add support for MMIO on older SoCs")
+Signed-off-by: Vignesh Viswanathan <quic_viswanat@quicinc.com>
+Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
+Link: https://lore.kernel.org/r/20230905095535.1263113-3-quic_viswanat@quicinc.com
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+---
+ drivers/hwspinlock/qcom_hwspinlock.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+--- a/drivers/hwspinlock/qcom_hwspinlock.c
++++ b/drivers/hwspinlock/qcom_hwspinlock.c
+@@ -115,7 +115,6 @@ static const struct of_device_id qcom_hw
+ 	{ .compatible = "qcom,sfpb-mutex", .data = &of_sfpb_mutex },
+ 	{ .compatible = "qcom,tcsr-mutex", .data = &of_tcsr_mutex },
+ 	{ .compatible = "qcom,apq8084-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },
+-	{ .compatible = "qcom,ipq6018-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },
+ 	{ .compatible = "qcom,msm8226-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },
+ 	{ .compatible = "qcom,msm8974-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },
+ 	{ .compatible = "qcom,msm8994-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },
diff --git a/target/linux/qualcommax/patches-6.1/0058-v6.9-arm64-dts-qcom-ipq6018-add-tsens-node.patch b/target/linux/qualcommax/patches-6.1/0058-v6.9-arm64-dts-qcom-ipq6018-add-tsens-node.patch
new file mode 100644
index 00000000000000..9de90e4da62c3b
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.1/0058-v6.9-arm64-dts-qcom-ipq6018-add-tsens-node.patch
@@ -0,0 +1,34 @@
+From 0b17197055b528da22e9385200e61b847b499d48 Mon Sep 17 00:00:00 2001
+From: Mantas Pucka <mantas@8devices.com>
+Date: Thu, 25 Jan 2024 11:04:11 +0200
+Subject: [PATCH] arm64: dts: qcom: ipq6018: add tsens node
+
+IPQ6018 has temperature sensing HW block compatible with IPQ8074. Add
+node for it.
+
+Signed-off-by: Mantas Pucka <mantas@8devices.com>
+Link: https://lore.kernel.org/r/1706173452-1017-3-git-send-email-mantas@8devices.com
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+---
+ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+@@ -342,6 +342,16 @@
+ 			clock-names = "core";
+ 		};
+ 
++		tsens: thermal-sensor@4a9000 {
++			compatible = "qcom,ipq6018-tsens", "qcom,ipq8074-tsens";
++			reg = <0x0 0x004a9000 0x0 0x1000>,
++			      <0x0 0x004a8000 0x0 0x1000>;
++			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "combined";
++			#qcom,sensors = <16>;
++			#thermal-sensor-cells = <1>;
++		};
++
+ 		cryptobam: dma-controller@704000 {
+ 			compatible = "qcom,bam-v1.7.0";
+ 			reg = <0x0 0x00704000 0x0 0x20000>;
diff --git a/target/linux/qualcommax/patches-6.1/0059-v6.9-arm64-dts-qcom-ipq6018-add-thermal-zones.patch b/target/linux/qualcommax/patches-6.1/0059-v6.9-arm64-dts-qcom-ipq6018-add-thermal-zones.patch
new file mode 100644
index 00000000000000..dab433348a3dfb
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.1/0059-v6.9-arm64-dts-qcom-ipq6018-add-thermal-zones.patch
@@ -0,0 +1,180 @@
+From 8f053e5616352943e16966f195f5a7a161e6fe7d Mon Sep 17 00:00:00 2001
+From: Mantas Pucka <mantas@8devices.com>
+Date: Thu, 25 Jan 2024 11:04:12 +0200
+Subject: [PATCH] arm64: dts: qcom: ipq6018: add thermal zones
+
+Add thermal zones to make use of thermal sensors data. For CPU zone,
+add cooling device that uses CPU frequency scaling.
+
+Signed-off-by: Mantas Pucka <mantas@8devices.com>
+Link: https://lore.kernel.org/r/1706173452-1017-4-git-send-email-mantas@8devices.com
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+---
+ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 121 ++++++++++++++++++++++++++
+ 1 file changed, 121 insertions(+)
+
+--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+@@ -9,6 +9,7 @@
+ #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
+ #include <dt-bindings/reset/qcom,gcc-ipq6018.h>
+ #include <dt-bindings/clock/qcom,apss-ipq.h>
++#include <dt-bindings/thermal/thermal.h>
+ 
+ / {
+ 	#address-cells = <2>;
+@@ -43,6 +44,7 @@
+ 			clock-names = "cpu";
+ 			operating-points-v2 = <&cpu_opp_table>;
+ 			cpu-supply = <&ipq6018_s2>;
++			#cooling-cells = <2>;
+ 		};
+ 
+ 		CPU1: cpu@1 {
+@@ -55,6 +57,7 @@
+ 			clock-names = "cpu";
+ 			operating-points-v2 = <&cpu_opp_table>;
+ 			cpu-supply = <&ipq6018_s2>;
++			#cooling-cells = <2>;
+ 		};
+ 
+ 		CPU2: cpu@2 {
+@@ -67,6 +70,7 @@
+ 			clock-names = "cpu";
+ 			operating-points-v2 = <&cpu_opp_table>;
+ 			cpu-supply = <&ipq6018_s2>;
++			#cooling-cells = <2>;
+ 		};
+ 
+ 		CPU3: cpu@3 {
+@@ -79,6 +83,7 @@
+ 			clock-names = "cpu";
+ 			operating-points-v2 = <&cpu_opp_table>;
+ 			cpu-supply = <&ipq6018_s2>;
++			#cooling-cells = <2>;
+ 		};
+ 
+ 		L2_0: l2-cache {
+@@ -888,6 +893,122 @@
+ 		};
+ 	};
+ 
++	thermal-zones {
++		nss-top-thermal {
++			polling-delay-passive = <250>;
++			polling-delay = <1000>;
++			thermal-sensors = <&tsens 4>;
++
++			trips {
++				nss-top-critical {
++					temperature = <125000>;
++					hysteresis = <1000>;
++					type = "critical";
++				};
++			};
++		};
++
++		nss-thermal {
++			polling-delay-passive = <250>;
++			polling-delay = <1000>;
++			thermal-sensors = <&tsens 5>;
++
++			trips {
++				nss-critical {
++					temperature = <125000>;
++					hysteresis = <1000>;
++					type = "critical";
++				};
++			};
++		};
++
++		wcss-phya0-thermal {
++			polling-delay-passive = <250>;
++			polling-delay = <1000>;
++			thermal-sensors = <&tsens 7>;
++
++			trips {
++				wcss-phya0-critical {
++					temperature = <125000>;
++					hysteresis = <1000>;
++					type = "critical";
++				};
++			};
++		};
++
++		wcss-phya1-thermal {
++			polling-delay-passive = <250>;
++			polling-delay = <1000>;
++			thermal-sensors = <&tsens 8>;
++
++			trips {
++				wcss-phya1-critical {
++					temperature = <125000>;
++					hysteresis = <1000>;
++					type = "critical";
++				};
++			};
++		};
++
++		cpu-thermal {
++			polling-delay-passive = <250>;
++			polling-delay = <1000>;
++			thermal-sensors = <&tsens 13>;
++
++			trips {
++				cpu-critical {
++					temperature = <125000>;
++					hysteresis = <1000>;
++					type = "critical";
++				};
++
++				cpu_alert: cpu-passive {
++					temperature = <110000>;
++					hysteresis = <1000>;
++					type = "passive";
++				};
++			};
++
++			cooling-maps {
++				map0 {
++					trip = <&cpu_alert>;
++					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
++							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
++							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
++							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
++				};
++			};
++		};
++
++		lpass-thermal {
++			polling-delay-passive = <250>;
++			polling-delay = <1000>;
++			thermal-sensors = <&tsens 14>;
++
++			trips {
++				lpass-critical {
++					temperature = <125000>;
++					hysteresis = <1000>;
++					type = "critical";
++				};
++			};
++		};
++
++		ddrss-top-thermal {
++			polling-delay-passive = <250>;
++			polling-delay = <1000>;
++			thermal-sensors = <&tsens 15>;
++
++			trips {
++				ddrss-top-critical {
++					temperature = <125000>;
++					hysteresis = <1000>;
++					type = "critical";
++				};
++			};
++		};
++	};
++
+ 	timer {
+ 		compatible = "arm,armv8-timer";
+ 		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
diff --git a/target/linux/qualcommax/patches-6.1/0060-v6.9-clk-qcom-gcc-ipq6018-add-qdss_at-clock-needed-for-wi.patch b/target/linux/qualcommax/patches-6.1/0060-v6.9-clk-qcom-gcc-ipq6018-add-qdss_at-clock-needed-for-wi.patch
new file mode 100644
index 00000000000000..e72d1180c58c94
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.1/0060-v6.9-clk-qcom-gcc-ipq6018-add-qdss_at-clock-needed-for-wi.patch
@@ -0,0 +1,50 @@
+From fd712118aa1aa758da1fd1546b3f8a1b00e42cbc Mon Sep 17 00:00:00 2001
+From: Mantas Pucka <mantas@8devices.com>
+Date: Tue, 23 Jan 2024 11:26:09 +0200
+Subject: [PATCH] clk: qcom: gcc-ipq6018: add qdss_at clock needed for wifi
+ operation
+
+Without it system hangs upon wifi firmware load. It should be enabled by
+remoteproc/wifi driver. Bindings already exist for it, so add it based
+on vendor code.
+
+Signed-off-by: Mantas Pucka <mantas@8devices.com>
+Link: https://lore.kernel.org/r/1706001970-26032-1-git-send-email-mantas@8devices.com
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+---
+ drivers/clk/qcom/gcc-ipq6018.c | 17 +++++++++++++++++
+ 1 file changed, 17 insertions(+)
+
+--- a/drivers/clk/qcom/gcc-ipq6018.c
++++ b/drivers/clk/qcom/gcc-ipq6018.c
+@@ -3523,6 +3523,22 @@ static struct clk_branch gcc_prng_ahb_cl
+ 	},
+ };
+ 
++static struct clk_branch gcc_qdss_at_clk = {
++	.halt_reg = 0x29024,
++	.clkr = {
++		.enable_reg = 0x29024,
++		.enable_mask = BIT(0),
++		.hw.init = &(struct clk_init_data){
++			.name = "gcc_qdss_at_clk",
++			.parent_hws = (const struct clk_hw *[]){
++				&qdss_at_clk_src.clkr.hw },
++			.num_parents = 1,
++			.flags = CLK_SET_RATE_PARENT,
++			.ops = &clk_branch2_ops,
++		},
++	},
++};
++
+ static struct clk_branch gcc_qdss_dap_clk = {
+ 	.halt_reg = 0x29084,
+ 	.clkr = {
+@@ -4362,6 +4378,7 @@ static struct clk_regmap *gcc_ipq6018_cl
+ 	[GCC_SYS_NOC_PCIE0_AXI_CLK] = &gcc_sys_noc_pcie0_axi_clk.clkr,
+ 	[GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
+ 	[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
++	[GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr,
+ 	[GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
+ 	[GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
+ 	[GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
diff --git a/target/linux/qualcommax/patches-6.1/0061-v6.8-phy-qcom-qmp-usb-fix-serdes-init-sequence-for-IPQ6018.patch b/target/linux/qualcommax/patches-6.1/0061-v6.8-phy-qcom-qmp-usb-fix-serdes-init-sequence-for-IPQ6018.patch
new file mode 100644
index 00000000000000..97b46f74ef5052
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.1/0061-v6.8-phy-qcom-qmp-usb-fix-serdes-init-sequence-for-IPQ6018.patch
@@ -0,0 +1,102 @@
+From 62a5df451ab911421da96655fcc4d1e269ff6e2f Mon Sep 17 00:00:00 2001
+From: Mantas Pucka <mantas@8devices.com>
+Date: Tue, 23 Jan 2024 18:09:20 +0200
+Subject: [PATCH] phy: qcom-qmp-usb: fix serdes init sequence for IPQ6018
+
+Commit 23fd679249df ("phy: qcom-qmp: add USB3 PHY support for IPQ6018")
+noted that IPQ6018 init is identical to IPQ8074. Yet downstream uses
+separate serdes init sequence for IPQ6018. Since already existing IPQ9574
+serdes init sequence is identical, just reuse it and fix failing USB3 mode
+in IPQ6018.
+
+Fixes: 23fd679249df ("phy: qcom-qmp: add USB3 PHY support for IPQ6018")
+Signed-off-by: Mantas Pucka <mantas@8devices.com>
+Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Link: https://lore.kernel.org/r/1706026160-17520-3-git-send-email-mantas@8devices.com
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+---
+ drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 20 +++++++++++++++++++-
+ 1 file changed, 19 insertions(+), 1 deletion(-)
+
+--- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
++++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+@@ -233,6 +233,43 @@ static const struct qmp_phy_init_tbl ipq
+ 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
+ };
+ 
++static const struct qmp_phy_init_tbl ipq9574_usb3_serdes_tbl[] = {
++	QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
++	QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++	QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++	QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++	QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++	QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++	QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++	QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++	QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
++	/* PLL and Loop filter settings */
++	QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x68),
++	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0xab),
++	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0xaa),
++	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x02),
++	QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x09),
++	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++	QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0xa0),
++	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xaa),
++	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x29),
++	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++	QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++	QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++	/* SSC settings */
++	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x7d),
++	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
++	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x0a),
++	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x05),
++};
++
+ static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
+ 	QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
+ 	QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
+@@ -1591,6 +1628,26 @@ static const char * const qmp_phy_vreg_l
+ 	"vdda-phy", "vdda-pll",
+ };
+ 
++static const struct qmp_phy_cfg ipq6018_usb3phy_cfg = {
++	.lanes			= 1,
++
++	.serdes_tbl		= ipq9574_usb3_serdes_tbl,
++	.serdes_tbl_num		= ARRAY_SIZE(ipq9574_usb3_serdes_tbl),
++	.tx_tbl			= msm8996_usb3_tx_tbl,
++	.tx_tbl_num		= ARRAY_SIZE(msm8996_usb3_tx_tbl),
++	.rx_tbl			= ipq8074_usb3_rx_tbl,
++	.rx_tbl_num		= ARRAY_SIZE(ipq8074_usb3_rx_tbl),
++	.pcs_tbl		= ipq8074_usb3_pcs_tbl,
++	.pcs_tbl_num		= ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
++	.clk_list		= msm8996_phy_clk_l,
++	.num_clks		= ARRAY_SIZE(msm8996_phy_clk_l),
++	.reset_list		= msm8996_usb3phy_reset_l,
++	.num_resets		= ARRAY_SIZE(msm8996_usb3phy_reset_l),
++	.vreg_list		= qmp_phy_vreg_l,
++	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
++	.regs			= qmp_v3_usb3phy_regs_layout,
++};
++
+ static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
+ 	.lanes			= 1,
+ 
+@@ -2534,7 +2591,7 @@ static const struct of_device_id qmp_usb
+ 		.data = &msm8996_usb3phy_cfg,
+ 	}, {
+ 		.compatible = "qcom,ipq6018-qmp-usb3-phy",
+-		.data = &ipq8074_usb3phy_cfg,
++		.data = &ipq6018_usb3phy_cfg,
+ 	}, {
+ 		.compatible = "qcom,sc7180-qmp-usb3-phy",
+ 		.data = &sc7180_usb3phy_cfg,
diff --git a/target/linux/qualcommax/patches-6.1/0062-v6.8-arm64-dts-qcom-ipq8074-Add-QUP4-SPI-node.patch b/target/linux/qualcommax/patches-6.1/0062-v6.8-arm64-dts-qcom-ipq8074-Add-QUP4-SPI-node.patch
new file mode 100644
index 00000000000000..1525726640b78a
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.1/0062-v6.8-arm64-dts-qcom-ipq8074-Add-QUP4-SPI-node.patch
@@ -0,0 +1,38 @@
+From 6a25e70214fde6dcf900271c819c8d7fe7b9a4b0 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Thu, 23 Nov 2023 13:12:54 +0100
+Subject: [PATCH] arm64: dts: qcom: ipq8074: Add QUP4 SPI node
+
+Add node to support the QUP4 SPI controller inside of IPQ8074.
+Some devices use this bus to communicate to a Bluetooth controller.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Link: https://lore.kernel.org/r/20231123121324.1046164-1-robimarko@gmail.com
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+---
+ arch/arm64/boot/dts/qcom/ipq8074.dtsi | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+@@ -529,6 +529,20 @@
+ 			status = "disabled";
+ 		};
+ 
++		blsp1_spi4: spi@78b8000 {
++			compatible = "qcom,spi-qup-v2.2.1";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x78b8000 0x600>;
++			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
++				 <&gcc GCC_BLSP1_AHB_CLK>;
++			clock-names = "core", "iface";
++			dmas = <&blsp_dma 18>, <&blsp_dma 19>;
++			dma-names = "tx", "rx";
++			status = "disabled";
++		};
++
+ 		blsp1_i2c5: i2c@78b9000 {
+ 			compatible = "qcom,i2c-qup-v2.2.1";
+ 			#address-cells = <1>;
diff --git a/target/linux/qualcommax/patches-6.1/0102-arm64-dts-ipq8074-add-reserved-memory-nodes.patch b/target/linux/qualcommax/patches-6.1/0102-arm64-dts-ipq8074-add-reserved-memory-nodes.patch
index af53c077ff1eca..3996d15d9d983e 100644
--- a/target/linux/qualcommax/patches-6.1/0102-arm64-dts-ipq8074-add-reserved-memory-nodes.patch
+++ b/target/linux/qualcommax/patches-6.1/0102-arm64-dts-ipq8074-add-reserved-memory-nodes.patch
@@ -19,7 +19,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
 
 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
 +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -85,6 +85,26 @@
+@@ -85,6 +85,16 @@
  		#size-cells = <2>;
  		ranges;
  
@@ -33,22 +33,12 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
 +			reg = <0x0 0x4a400000 0x0 0x00200000>;
 +		};
 +
-+		uboot@4a600000 {
-+			no-map;
-+			reg = <0x0 0x4a600000 0x0 0x00400000>;
-+		};
-+
-+		sbl@4aa00000 {
-+			no-map;
-+			reg = <0x0 0x4aa00000 0x0 0x00100000>;
-+		};
-+
- 		smem@4ab00000 {
- 			compatible = "qcom,smem";
- 			reg = <0x0 0x4ab00000 0x0 0x00100000>;
-@@ -97,6 +117,21 @@
+ 		bootloader@4a600000 {
+ 			reg = <0x0 0x4a600000 0x0 0x400000>;
+ 			no-map;
+@@ -107,6 +117,21 @@
+ 			reg = <0x0 0x4ac00000 0x0 0x400000>;
  			no-map;
- 			reg = <0x0 0x4ac00000 0x0 0x00400000>;
  		};
 +
 +		q6_region: wcnss@4b000000 {
diff --git a/target/linux/qualcommax/patches-6.1/0110-arm64-dts-qcom-ipq8074-pass-QMP-PCI-PHY-PIPE-clocks-.patch b/target/linux/qualcommax/patches-6.1/0110-arm64-dts-qcom-ipq8074-pass-QMP-PCI-PHY-PIPE-clocks-.patch
index 4bd0d9298f8a6a..fd97663513e7d0 100644
--- a/target/linux/qualcommax/patches-6.1/0110-arm64-dts-qcom-ipq8074-pass-QMP-PCI-PHY-PIPE-clocks-.patch
+++ b/target/linux/qualcommax/patches-6.1/0110-arm64-dts-qcom-ipq8074-pass-QMP-PCI-PHY-PIPE-clocks-.patch
@@ -17,7 +17,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
 
 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
 +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -398,8 +398,8 @@
+@@ -399,8 +399,8 @@
  		gcc: gcc@1800000 {
  			compatible = "qcom,gcc-ipq8074";
  			reg = <0x01800000 0x80000>;
diff --git a/target/linux/qualcommax/patches-6.1/0111-arm64-dts-qcom-ipq8074-use-msi-parent-for-PCIe.patch b/target/linux/qualcommax/patches-6.1/0111-arm64-dts-qcom-ipq8074-use-msi-parent-for-PCIe.patch
index 2aedbd7028039c..9163cd76fecd42 100644
--- a/target/linux/qualcommax/patches-6.1/0111-arm64-dts-qcom-ipq8074-use-msi-parent-for-PCIe.patch
+++ b/target/linux/qualcommax/patches-6.1/0111-arm64-dts-qcom-ipq8074-use-msi-parent-for-PCIe.patch
@@ -12,7 +12,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
 
 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
 +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -701,7 +701,7 @@
+@@ -734,7 +734,7 @@
  			reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
  			ranges = <0 0xb00a000 0xffd>;
  
@@ -21,7 +21,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
  				compatible = "arm,gic-v2m-frame";
  				msi-controller;
  				reg = <0x0 0xffd>;
-@@ -813,8 +813,7 @@
+@@ -847,8 +847,7 @@
  			ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>,   /* I/O */
  				 <0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */
  
@@ -31,7 +31,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
  			#interrupt-cells = <1>;
  			interrupt-map-mask = <0 0 0 0x7>;
  			interrupt-map = <0 0 0 1 &intc 0 142
-@@ -875,8 +874,7 @@
+@@ -909,8 +908,7 @@
  			ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>,   /* I/O */
  				 <0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000>; /* MEM */
  
diff --git a/target/linux/qualcommax/patches-6.1/0120-arm64-dts-qcom-Enable-Q6v5-WCSS-for-ipq8074-SoC.patch b/target/linux/qualcommax/patches-6.1/0120-arm64-dts-qcom-Enable-Q6v5-WCSS-for-ipq8074-SoC.patch
index f5f93d389ef746..17ecd069a6e4e4 100644
--- a/target/linux/qualcommax/patches-6.1/0120-arm64-dts-qcom-Enable-Q6v5-WCSS-for-ipq8074-SoC.patch
+++ b/target/linux/qualcommax/patches-6.1/0120-arm64-dts-qcom-Enable-Q6v5-WCSS-for-ipq8074-SoC.patch
@@ -16,7 +16,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
 
 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
 +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -140,6 +140,32 @@
+@@ -141,6 +141,32 @@
  		};
  	};
  
@@ -49,8 +49,8 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
  	soc: soc {
  		#address-cells = <0x1>;
  		#size-cells = <0x1>;
-@@ -411,6 +437,11 @@
- 			#hwlock-cells = <1>;
+@@ -417,6 +443,11 @@
+ 			reg = <0x01937000 0x21000>;
  		};
  
 +		tcsr_q6: syscon@1945000 {
@@ -61,7 +61,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
  		spmi_bus: spmi@200f000 {
  			compatible = "qcom,spmi-pmic-arb";
  			reg = <0x0200f000 0x001000>,
-@@ -915,6 +946,56 @@
+@@ -949,6 +980,56 @@
  				      "axi_s_sticky";
  			status = "disabled";
  		};
diff --git a/target/linux/qualcommax/patches-6.1/0121-arm64-dts-ipq8074-Add-WLAN-node.patch b/target/linux/qualcommax/patches-6.1/0121-arm64-dts-ipq8074-Add-WLAN-node.patch
index 1aaa187d8acea6..76d3f35dd24acf 100644
--- a/target/linux/qualcommax/patches-6.1/0121-arm64-dts-ipq8074-Add-WLAN-node.patch
+++ b/target/linux/qualcommax/patches-6.1/0121-arm64-dts-ipq8074-Add-WLAN-node.patch
@@ -15,7 +15,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
 
 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
 +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -996,6 +996,117 @@
+@@ -1030,6 +1030,117 @@
  				};
  			};
  		};
diff --git a/target/linux/qualcommax/patches-6.1/0129-arm64-dts-qcom-ipq8074-add-QFPROM-fuses.patch b/target/linux/qualcommax/patches-6.1/0129-arm64-dts-qcom-ipq8074-add-QFPROM-fuses.patch
index 5776ab1af74173..8ec46601236368 100644
--- a/target/linux/qualcommax/patches-6.1/0129-arm64-dts-qcom-ipq8074-add-QFPROM-fuses.patch
+++ b/target/linux/qualcommax/patches-6.1/0129-arm64-dts-qcom-ipq8074-add-QFPROM-fuses.patch
@@ -12,7 +12,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
 
 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
 +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -342,6 +342,113 @@
+@@ -343,6 +343,113 @@
  			status = "disabled";
  		};
  
diff --git a/target/linux/qualcommax/patches-6.1/0136-remoteproc-qcom-wcss-populate-driver-data-for-IPQ601.patch b/target/linux/qualcommax/patches-6.1/0136-remoteproc-qcom-wcss-populate-driver-data-for-IPQ601.patch
new file mode 100644
index 00000000000000..9a5a3407e19a30
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.1/0136-remoteproc-qcom-wcss-populate-driver-data-for-IPQ601.patch
@@ -0,0 +1,61 @@
+From 9dd19a9ae36bc60d58287d0c52e53024d484e64d Mon Sep 17 00:00:00 2001
+From:   Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
+Date:   Fri, 29 Jan 2021 22:41:59 +0530
+Subject: [PATCH 2/3] remoteproc: qcom: wcss: populate driver data for IPQ6018
+
+Populate hardcoded param using driver data for IPQ6018 SoCs.
+
+Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
+---
+ drivers/remoteproc/qcom_q6v5_wcss.c | 19 +++++++++++++++++--
+ 1 file changed, 17 insertions(+), 2 deletions(-)
+
+--- a/drivers/remoteproc/qcom_q6v5_wcss.c
++++ b/drivers/remoteproc/qcom_q6v5_wcss.c
+@@ -970,7 +970,7 @@ static int q6v5_alloc_memory_region(stru
+ 	return 0;
+ }
+ 
+-static int ipq8074_init_clock(struct q6v5_wcss *wcss)
++static int ipq_init_clock(struct q6v5_wcss *wcss)
+ {
+ 	int ret;
+ 
+@@ -1179,7 +1179,7 @@ static int q6v5_wcss_remove(struct platf
+ }
+ 
+ static const struct wcss_data wcss_ipq8074_res_init = {
+-	.init_clock = ipq8074_init_clock,
++	.init_clock = ipq_init_clock,
+ 	.q6_firmware_name = "IPQ8074/q6_fw.mdt",
+ 	.m3_firmware_name = "IPQ8074/m3_fw.mdt",
+ 	.crash_reason_smem = WCSS_CRASH_REASON,
+@@ -1193,6 +1193,20 @@ static const struct wcss_data wcss_ipq80
+ 	.need_auto_boot = false,
+ };
+ 
++static const struct wcss_data wcss_ipq6018_res_init = {
++	.init_clock = ipq_init_clock,
++	.q6_firmware_name = "IPQ6018/q6_fw.mdt",
++	.m3_firmware_name = "IPQ6018/m3_fw.mdt",
++	.crash_reason_smem = WCSS_CRASH_REASON,
++	.aon_reset_required = true,
++	.wcss_q6_reset_required = true,
++	.bcr_reset_required = false,
++	.ssr_name = "q6wcss",
++	.ops = &q6v5_wcss_ipq8074_ops,
++	.requires_force_stop = true,
++	.need_mem_protection = true,
++};
++
+ static const struct wcss_data wcss_qcs404_res_init = {
+ 	.init_clock = qcs404_init_clock,
+ 	.init_regulator = qcs404_init_regulator,
+@@ -1212,6 +1226,7 @@ static const struct wcss_data wcss_qcs40
+ 
+ static const struct of_device_id q6v5_wcss_of_match[] = {
+ 	{ .compatible = "qcom,ipq8074-wcss-pil", .data = &wcss_ipq8074_res_init },
++	{ .compatible = "qcom,ipq6018-wcss-pil", .data = &wcss_ipq6018_res_init },
+ 	{ .compatible = "qcom,qcs404-wcss-pil", .data = &wcss_qcs404_res_init },
+ 	{ },
+ };
diff --git a/target/linux/qualcommax/patches-6.1/0137-arm64-dts-qcom-ipq6018-add-SDHCI-node.patch b/target/linux/qualcommax/patches-6.1/0137-arm64-dts-qcom-ipq6018-add-SDHCI-node.patch
new file mode 100644
index 00000000000000..bfca74ba766e12
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.1/0137-arm64-dts-qcom-ipq6018-add-SDHCI-node.patch
@@ -0,0 +1,45 @@
+From e4d7544ce092807e8c5aeb618cec30e2eb9b40c2 Mon Sep 17 00:00:00 2001
+From: Mantas Pucka <mantas@8devices.com>
+Date: Mon, 24 Apr 2023 15:13:32 +0300
+Subject: [PATCH 3/3] arm64: dts: qcom: ipq6018: add SDHCI node
+
+IPQ6018 has one SD/eMMC controller, add node for it.
+
+Signed-off-by: Mantas Pucka <mantas@8devices.com>
+Tested-by: Robert Marko <robimarko@gmail.com>
+---
+ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 23 +++++++++++++++++++++++
+ 1 file changed, 23 insertions(+)
+
+--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+@@ -469,6 +469,29 @@
+ 			};
+ 		};
+ 
++		sdhc_1: mmc@7804000 {
++			compatible = "qcom,ipq6018-sdhci", "qcom,sdhci-msm-v5";
++			reg = <0x0 0x07804000 0x0 0x1000>,
++			      <0x0 0x07805000 0x0 0x1000>,
++			      <0x0 0x07808000 0x0 0x2000>;
++			reg-names = "hc", "cqhci", "ice";
++
++			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "hc_irq", "pwr_irq";
++
++			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
++				 <&gcc GCC_SDCC1_APPS_CLK>,
++				 <&xo>,
++				 <&gcc GCC_SDCC1_ICE_CORE_CLK>;
++			clock-names = "iface", "core", "xo", "ice";
++
++			resets = <&gcc GCC_SDCC1_BCR>;
++			supports-cqe;
++			bus-width = <8>;
++			status = "disabled";
++		};
++
+ 		blsp_dma: dma-controller@7884000 {
+ 			compatible = "qcom,bam-v1.7.0";
+ 			reg = <0x0 0x07884000 0x0 0x2b000>;
diff --git a/target/linux/qualcommax/patches-6.1/0139-arm64-dts-qcom-ipq6018-add-LDOA2-regulator.patch b/target/linux/qualcommax/patches-6.1/0139-arm64-dts-qcom-ipq6018-add-LDOA2-regulator.patch
new file mode 100644
index 00000000000000..8889db97f91d65
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.1/0139-arm64-dts-qcom-ipq6018-add-LDOA2-regulator.patch
@@ -0,0 +1,27 @@
+From d24bc08bfc66f47d6e0a294a080d62893a7696b5 Mon Sep 17 00:00:00 2001
+From: Chukun Pan <amadeus@jmu.edu.cn>
+Date: Thu, 18 Jan 2024 21:30:21 +0800
+Subject: [PATCH] arm64: dts: qcom: ipq6018: add LDOA2 regulator
+
+Add LDOA2 regulator of MP5496 to support SDCC voltage scaling.
+
+Suggested-by: Robert Marko <robimarko@gmail.com>
+Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
+---
+ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+@@ -178,6 +178,11 @@
+ 						regulator-max-microvolt = <1062500>;
+ 						regulator-always-on;
+ 					};
++
++					ipq6018_l2: l2 {
++						regulator-min-microvolt = <1800000>;
++						regulator-max-microvolt = <3300000>;
++					};
+ 				};
+ 			};
+ 		};
diff --git a/target/linux/qualcommax/patches-6.1/0903-psci-dont-advertise-OSI-support-for-IPQ6018.patch b/target/linux/qualcommax/patches-6.1/0903-psci-dont-advertise-OSI-support-for-IPQ6018.patch
new file mode 100644
index 00000000000000..5fcb90098f3749
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.1/0903-psci-dont-advertise-OSI-support-for-IPQ6018.patch
@@ -0,0 +1,40 @@
+From 563db68137475d011b355bfe674d1b7a24778091 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Sat, 8 Oct 2022 22:26:31 +0200
+Subject: [PATCH] psci: dont advertise OSI support for IPQ6018
+
+Some older IPQ60xx SoC series boards ship with TrustZone/QSEE firmware
+older than TZ.WNS.5.1-00084 which will advertise OSI[1] but are broken
+and trying to use OSI will cause the board to hang until WDT kicks in.
+
+So workaround it by checking for SoC compatible and returning false so
+OSI is not used.
+
+[1] https://www.spinics.net/lists/linux-arm-msm/msg79916.html
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+---
+ drivers/firmware/psci/psci.c | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+--- a/drivers/firmware/psci/psci.c
++++ b/drivers/firmware/psci/psci.c
+@@ -87,6 +87,18 @@ static inline bool psci_has_ext_power_st
+ 
+ bool psci_has_osi_support(void)
+ {
++	/*
++	 * Some older IPQ60xx SoC series boards ship with
++	 * TrustZone/QSEE firmware older than TZ.WNS.5.1-00084
++	 * which will advertise OSI but is broken and trying
++	 * to use OSI will cause the board to hang until WDT
++	 * kicks in.
++	 * So workaround it by checking for SoC compatible
++	 * and returning false so OSI is not used.
++	 */
++	if (of_machine_is_compatible("qcom,ipq6018"))
++		return false;
++
+ 	return psci_cpu_suspend_feature & PSCI_1_0_OS_INITIATED;
+ }
+ 
diff --git a/target/linux/qualcommax/patches-6.1/0904-clk-qcom-ipq6018-workaround-networking-clock-parenti.patch b/target/linux/qualcommax/patches-6.1/0904-clk-qcom-ipq6018-workaround-networking-clock-parenti.patch
new file mode 100644
index 00000000000000..175d47584935b8
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.1/0904-clk-qcom-ipq6018-workaround-networking-clock-parenti.patch
@@ -0,0 +1,109 @@
+From 0c5b5243ad55ae744e790ba90c5ad37a93bd1377 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Tue, 11 Oct 2022 23:38:45 +0200
+Subject: [PATCH] clk: qcom: ipq6018: workaround networking clock parenting
+
+Currently, networking clocks are only looked up by fw_name however,
+these are registered and setup by SSDK and are not available to the
+GCC driver at all, so work around that by providing a global name
+fallback.
+
+While we are here, provide global fallback for bias_pll_cc_clk and
+bias_pll_nss_noc_clk as well as these are fixed clocks also not available
+to the driver.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+---
+ drivers/clk/qcom/gcc-ipq6018.c | 39 +++++++++++++++++-----------------
+ 1 file changed, 19 insertions(+), 20 deletions(-)
+
+--- a/drivers/clk/qcom/gcc-ipq6018.c
++++ b/drivers/clk/qcom/gcc-ipq6018.c
+@@ -361,7 +361,7 @@ static const struct freq_tbl ftbl_nss_pp
+ 
+ static const struct clk_parent_data gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
+ 	{ .fw_name = "xo" },
+-	{ .fw_name = "bias_pll_cc_clk" },
++	{ .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
+ 	{ .hw = &gpll0.clkr.hw },
+ 	{ .hw = &gpll4.clkr.hw },
+ 	{ .hw = &nss_crypto_pll.clkr.hw },
+@@ -527,12 +527,12 @@ static const struct freq_tbl ftbl_nss_po
+ static const struct clk_parent_data
+ gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
+ 	{ .fw_name = "xo" },
+-	{ .fw_name = "uniphy0_gcc_rx_clk" },
+-	{ .fw_name = "uniphy0_gcc_tx_clk" },
+-	{ .fw_name = "uniphy1_gcc_rx_clk" },
+-	{ .fw_name = "uniphy1_gcc_tx_clk" },
++	{ .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
++	{ .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
++	{ .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
++	{ .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
+ 	{ .hw = &ubi32_pll.clkr.hw },
+-	{ .fw_name = "bias_pll_cc_clk" },
++	{ .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
+ };
+ 
+ static const struct parent_map
+@@ -574,12 +574,12 @@ static const struct freq_tbl ftbl_nss_po
+ static const struct clk_parent_data
+ gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
+ 	{ .fw_name = "xo" },
+-	{ .fw_name = "uniphy0_gcc_tx_clk" },
+-	{ .fw_name = "uniphy0_gcc_rx_clk" },
+-	{ .fw_name = "uniphy1_gcc_tx_clk" },
+-	{ .fw_name = "uniphy1_gcc_rx_clk" },
++	{ .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
++	{ .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
++	{ .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
++	{ .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
+ 	{ .hw = &ubi32_pll.clkr.hw },
+-	{ .fw_name = "bias_pll_cc_clk" },
++	{ .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
+ };
+ 
+ static const struct parent_map
+@@ -715,10 +715,10 @@ static const struct freq_tbl ftbl_nss_po
+ 
+ static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
+ 	{ .fw_name = "xo" },
+-	{ .fw_name = "uniphy0_gcc_rx_clk" },
+-	{ .fw_name = "uniphy0_gcc_tx_clk" },
++	{ .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
++	{ .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
+ 	{ .hw = &ubi32_pll.clkr.hw },
+-	{ .fw_name = "bias_pll_cc_clk" },
++	{ .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
+ };
+ 
+ static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
+@@ -751,10 +751,10 @@ static const struct freq_tbl ftbl_nss_po
+ 
+ static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
+ 	{ .fw_name = "xo" },
+-	{ .fw_name = "uniphy0_gcc_tx_clk" },
+-	{ .fw_name = "uniphy0_gcc_rx_clk" },
++	{ .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
++	{ .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
+ 	{ .hw = &ubi32_pll.clkr.hw },
+-	{ .fw_name = "bias_pll_cc_clk" },
++	{ .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
+ };
+ 
+ static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
+@@ -1898,12 +1898,11 @@ static const struct freq_tbl ftbl_ubi32_
+ 	{ }
+ };
+ 
+-static const struct clk_parent_data
+-			gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk[] = {
++static const struct clk_parent_data gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk[] = {
+ 	{ .fw_name = "xo" },
+ 	{ .hw = &gpll0.clkr.hw },
+ 	{ .hw = &gpll2.clkr.hw },
+-	{ .fw_name = "bias_pll_nss_noc_clk" },
++	{ .fw_name = "bias_pll_nss_noc_clk", .name = "bias_pll_nss_noc_clk" },
+ };
+ 
+ static const struct parent_map gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk_map[] = {
diff --git a/target/linux/qualcommax/patches-6.1/0905-remoteproc-q6v5_wcss-change-ssr-name-for-ipq6018-wif.patch b/target/linux/qualcommax/patches-6.1/0905-remoteproc-q6v5_wcss-change-ssr-name-for-ipq6018-wif.patch
new file mode 100644
index 00000000000000..58bea43892f372
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.1/0905-remoteproc-q6v5_wcss-change-ssr-name-for-ipq6018-wif.patch
@@ -0,0 +1,40 @@
+From 505f9c8653fc218ca47a153ec58ebc16bef5502f Mon Sep 17 00:00:00 2001
+From: Mantas Pucka <mantas@8devices.com>
+Date: Tue, 16 Jan 2024 10:42:40 +0200
+Subject: [PATCH 16/19] remoteproc: q6v5_wcss: change ssr name for ipq6018 wifi
+ subsystem
+
+On IPQ6018 this string ends up being sent to RPM when remoteproc stops
+(on crash or rmmod ath11k). "q6wcss" is not a valid name (not found by
+`strings` in rpm.mbn), so this causes RPM do 'something' (presumably crash)
+causing a system reboot followed by hang in XBL, with no WDT running.
+Let's change ssr_name to a more sensible 'wcnss', that does not cause such
+issues.
+
+Signed-off-by: Mantas Pucka <mantas@8devices.com>
+---
+ drivers/remoteproc/qcom_q6v5_wcss.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+--- a/drivers/remoteproc/qcom_q6v5_wcss.c
++++ b/drivers/remoteproc/qcom_q6v5_wcss.c
+@@ -1143,8 +1143,8 @@ static int q6v5_wcss_probe(struct platfo
+ 	if (ret)
+ 		goto free_rproc;
+ 
+-	qcom_add_glink_subdev(rproc, &wcss->glink_subdev, "q6wcss");
+-	qcom_add_ssr_subdev(rproc, &wcss->ssr_subdev, "q6wcss");
++	qcom_add_glink_subdev(rproc, &wcss->glink_subdev, desc->ssr_name);
++	qcom_add_ssr_subdev(rproc, &wcss->ssr_subdev, desc->ssr_name);
+ 
+ 	if (desc->ssctl_id)
+ 		wcss->sysmon = qcom_add_sysmon_subdev(rproc,
+@@ -1201,7 +1201,7 @@ static const struct wcss_data wcss_ipq60
+ 	.aon_reset_required = true,
+ 	.wcss_q6_reset_required = true,
+ 	.bcr_reset_required = false,
+-	.ssr_name = "q6wcss",
++	.ssr_name = "wcnss",
+ 	.ops = &q6v5_wcss_ipq8074_ops,
+ 	.requires_force_stop = true,
+ 	.need_mem_protection = true,
diff --git a/target/linux/qualcommax/patches-6.1/0906-arm64-dts-qcom-ipq6018-add-wifi-node.patch b/target/linux/qualcommax/patches-6.1/0906-arm64-dts-qcom-ipq6018-add-wifi-node.patch
new file mode 100644
index 00000000000000..247df110fff7f2
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.1/0906-arm64-dts-qcom-ipq6018-add-wifi-node.patch
@@ -0,0 +1,120 @@
+From 153c74fc80b9f33ed1a50d7790bf6979fdceb370 Mon Sep 17 00:00:00 2001
+From: Mantas Pucka <mantas@8devices.com>
+Date: Tue, 16 Jan 2024 11:41:06 +0200
+Subject: [PATCH 19/19] arm64: dts: qcom: ipq6018: add wifi node
+
+IPQ6018 has a AHB based Q6v5 802.11ax radios that are supported
+by the ath11k.
+
+Add the required DT node to enable the built-in radios.
+
+Signed-off-by: Mantas Pucka <mantas@8devices.com>
+---
+ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 96 +++++++++++++++++++++++++++++++++++
+ 1 file changed, 96 insertions(+)
+
+--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+@@ -807,6 +807,102 @@
+ 			};
+ 		};
+ 
++		wifi: wifi@c000000 {
++			compatible = "qcom,ipq6018-wifi";
++			reg = <0x0 0xc000000 0x0 0x1000000>;
++			qcom,rproc = <&q6v5_wcss>;
++			interrupts = <GIC_SPI 320 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 319 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 317 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 316 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 310 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 302 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 301 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 294 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 293 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 290 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 288 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 239 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 235 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 234 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 233 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 232 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 231 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 230 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 224 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 223 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 180 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 160 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
++			interrupt-names = "misc-pulse1", "misc-latch", "sw-exception",
++					  "watchdog", "ce0", "ce1", "ce2", "ce3", "ce4",
++					  "ce5", "ce6", "ce7", "ce8", "ce9", "ce10",
++					  "ce11", "host2wbm-desc-feed",
++					  "host2reo-re-injection", "host2reo-command",
++					  "host2rxdma-monitor-ring3",
++					  "host2rxdma-monitor-ring2",
++					  "host2rxdma-monitor-ring1",
++					  "reo2ost-exception", "wbm2host-rx-release",
++					  "reo2host-status",
++					  "reo2host-destination-ring4",
++					  "reo2host-destination-ring3",
++					  "reo2host-destination-ring2",
++					  "reo2host-destination-ring1",
++					  "rxdma2host-monitor-destination-mac3",
++					  "rxdma2host-monitor-destination-mac2",
++					  "rxdma2host-monitor-destination-mac1",
++					  "ppdu-end-interrupts-mac3",
++					  "ppdu-end-interrupts-mac2",
++					  "ppdu-end-interrupts-mac1",
++					  "rxdma2host-monitor-status-ring-mac3",
++					  "rxdma2host-monitor-status-ring-mac2",
++					  "rxdma2host-monitor-status-ring-mac1",
++					  "host2rxdma-host-buf-ring-mac3",
++					  "host2rxdma-host-buf-ring-mac2",
++					  "host2rxdma-host-buf-ring-mac1",
++					  "rxdma2host-destination-ring-mac3",
++					  "rxdma2host-destination-ring-mac2",
++					  "rxdma2host-destination-ring-mac1",
++					  "host2tcl-input-ring4",
++					  "host2tcl-input-ring3",
++					  "host2tcl-input-ring2",
++					  "host2tcl-input-ring1",
++					  "wbm2host-tx-completions-ring3",
++					  "wbm2host-tx-completions-ring2",
++					  "wbm2host-tx-completions-ring1",
++					  "tcl2host-status-ring";
++			status = "disabled";
++		};
++
+ 		q6v5_wcss: remoteproc@cd00000 {
+ 			compatible = "qcom,ipq6018-wcss-pil";
+ 			reg = <0x0 0x0cd00000 0x0 0x4040>,
diff --git a/target/linux/qualcommax/patches-6.1/0907-soc-qcom-fix-smp2p-ack-on-ipq6018.patch b/target/linux/qualcommax/patches-6.1/0907-soc-qcom-fix-smp2p-ack-on-ipq6018.patch
new file mode 100644
index 00000000000000..88e294562d01a2
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.1/0907-soc-qcom-fix-smp2p-ack-on-ipq6018.patch
@@ -0,0 +1,53 @@
+From d93936f175bd914067df8f63f5fbe6e3b77bb4d2 Mon Sep 17 00:00:00 2001
+From: Mantas Pucka <mantas@8devices.com>
+Date: Tue, 23 May 2023 14:46:28 +0300
+Subject: [PATCH 11/19] soc: qcom: fix smp2p ack on ipq6018
+
+IPQ6018 seem to need different ack mechanism for smp2p messaging. This
+fixes q6v5_wcss remoteproc firmware reloading. Without this first load
+is OK, but subsequent loads would hang and fail to complete.
+
+Signed-off-by: Mantas Pucka <mantas@8devices.com>
+---
+ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 1 +
+ drivers/soc/qcom/smp2p.c              | 6 +++++-
+ 2 files changed, 6 insertions(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+@@ -1155,6 +1155,7 @@
+ 
+ 		wcss_smp2p_out: master-kernel {
+ 			qcom,entry-name = "master-kernel";
++			qcom,smp2p-feature-ssr-ack;
+ 			#qcom,smem-state-cells = <1>;
+ 		};
+ 
+--- a/drivers/soc/qcom/smp2p.c
++++ b/drivers/soc/qcom/smp2p.c
+@@ -158,6 +158,8 @@ struct qcom_smp2p {
+ 
+ 	struct list_head inbound;
+ 	struct list_head outbound;
++
++	bool need_ssr_ack;
+ };
+ 
+ static void qcom_smp2p_kick(struct qcom_smp2p *smp2p)
+@@ -306,7 +308,7 @@ static irqreturn_t qcom_smp2p_intr(int i
+ 		ack_restart = qcom_smp2p_check_ssr(smp2p);
+ 		qcom_smp2p_notify_in(smp2p);
+ 
+-		if (ack_restart)
++		if (ack_restart || smp2p->need_ssr_ack)
+ 			qcom_smp2p_do_ssr_ack(smp2p);
+ 	}
+ 
+@@ -427,6 +429,7 @@ static int qcom_smp2p_outbound_entry(str
+ 
+ 	/* Make the logical entry reference the physical value */
+ 	entry->value = &out->entries[out->valid_entries].value;
++	smp2p->need_ssr_ack = of_property_read_bool(node, "qcom,smp2p-feature-ssr-ack");
+ 
+ 	out->valid_entries++;
+ 
diff --git a/target/linux/qualcommax/patches-6.1/0908-remoteproc-qcom_q6v5_wcss-add-optional-qdss_at-clock.patch b/target/linux/qualcommax/patches-6.1/0908-remoteproc-qcom_q6v5_wcss-add-optional-qdss_at-clock.patch
new file mode 100644
index 00000000000000..cfc9adda043019
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.1/0908-remoteproc-qcom_q6v5_wcss-add-optional-qdss_at-clock.patch
@@ -0,0 +1,55 @@
+From 87dbcc69a7e3fe6ccddf4fe9bdbf51330f5e4a77 Mon Sep 17 00:00:00 2001
+From: Mantas Pucka <mantas@8devices.com>
+Date: Tue, 23 Jan 2024 11:04:04 +0200
+Subject: [PATCH] remoteproc: qcom_q6v5_wcss: add optional qdss_at clock
+
+IPQ6018 needs QDSS_AT clock enabled when loading wifi. Optionally enable it
+when provided by DT.
+
+Signed-off-by: Mantas Pucka <mantas@8devices.com>
+---
+ drivers/remoteproc/qcom_q6v5_wcss.c | 24 ++++++++++++++++++++++++
+ 1 file changed, 24 insertions(+)
+
+--- a/drivers/remoteproc/qcom_q6v5_wcss.c
++++ b/drivers/remoteproc/qcom_q6v5_wcss.c
+@@ -120,6 +120,7 @@ struct q6v5_wcss {
+ 	struct clk *qdsp6ss_core_gfmux;
+ 	struct clk *lcc_bcr_sleep;
+ 	struct clk *prng_clk;
++	struct clk *qdss_clk;
+ 	struct regulator *cx_supply;
+ 	struct qcom_sysmon *sysmon;
+ 
+@@ -259,6 +260,9 @@ static int q6v5_wcss_start(struct rproc
+ 		return ret;
+ 	}
+ 
++	if (wcss->qdss_clk)
++		clk_prepare_enable(wcss->qdss_clk);
++
+ 	qcom_q6v5_prepare(&wcss->q6v5);
+ 
+ 	if (wcss->need_mem_protection) {
+@@ -772,6 +776,8 @@ static int q6v5_wcss_stop(struct rproc *
+ 	}
+ 
+ pas_done:
++	if (wcss->qdss_clk)
++		clk_disable_unprepare(wcss->qdss_clk);
+ 	clk_disable_unprepare(wcss->prng_clk);
+ 	qcom_q6v5_unprepare(&wcss->q6v5);
+ 
+@@ -981,6 +987,12 @@ static int ipq_init_clock(struct q6v5_wc
+ 			dev_err(wcss->dev, "Failed to get prng clock\n");
+ 		return ret;
+ 	}
++
++	wcss->qdss_clk = devm_clk_get(wcss->dev, "qdss");
++	if (IS_ERR(wcss->qdss_clk)) {
++		wcss->qdss_clk = NULL;
++	}
++
+ 	return 0;
+ }
+ 
diff --git a/target/linux/qualcommax/patches-6.1/0909-arm64-dts-qcom-ipq6018-assign-QDSS_AT-clock-to-wifi-.patch b/target/linux/qualcommax/patches-6.1/0909-arm64-dts-qcom-ipq6018-assign-QDSS_AT-clock-to-wifi-.patch
new file mode 100644
index 00000000000000..0a7a100f6ac87b
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.1/0909-arm64-dts-qcom-ipq6018-assign-QDSS_AT-clock-to-wifi-.patch
@@ -0,0 +1,26 @@
+From 71f30e25d21ae4981ecef6653a4ba7dfeb80db7b Mon Sep 17 00:00:00 2001
+From: Mantas Pucka <mantas@8devices.com>
+Date: Tue, 23 Jan 2024 11:04:57 +0200
+Subject: [PATCH] arm64: dts: qcom: ipq6018: assign QDSS_AT clock to wifi remoteproc
+
+IPQ6018 needs to enable QDSS_AT clock when loading wifi firmware,
+add it to wifi remoteproc clock list.
+
+Signed-off-by: Mantas Pucka <mantas@8devices.com>
+---
+ arch/arm64/boot/dts/qcom/ipq6018.dtsi          | 15 ++++++++-------
+ 1 file changed, 9 insertions(+), 8 deletions(-)
+
+--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+@@ -928,8 +928,8 @@
+ 				      "wcss_reset",
+ 				      "wcss_q6_reset";
+ 
+-			clocks = <&gcc GCC_PRNG_AHB_CLK>;
+-			clock-names = "prng";
++			clocks = <&gcc GCC_PRNG_AHB_CLK>, <&gcc GCC_QDSS_AT_CLK>;
++			clock-names = "prng", "qdss" ;
+ 
+ 			qcom,halt-regs = <&tcsr 0x18000 0x1b000 0xe000>;
+ 
diff --git a/target/linux/qualcommax/patches-6.1/0910-arm64-dts-qcom-ipq6018-change-voltage-to-perf-levels.patch b/target/linux/qualcommax/patches-6.1/0910-arm64-dts-qcom-ipq6018-change-voltage-to-perf-levels.patch
new file mode 100644
index 00000000000000..17784235c352df
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.1/0910-arm64-dts-qcom-ipq6018-change-voltage-to-perf-levels.patch
@@ -0,0 +1,65 @@
+From c67a1814bb1d0df290cf1e3f9c966f04aa41b9b9 Mon Sep 17 00:00:00 2001
+From: Mantas Pucka <mantas@8devices.com>
+Date: Tue, 30 Jan 2024 12:43:56 +0200
+Subject: [PATCH] arm64: dts: qcom: ipq6018: change voltage to perf levels for
+ CPR4 driver
+
+Current CPR4 driver requires opp-microvolt to be an abstract
+performance level instead of actual voltage level.
+
+Signed-off-by: Mantas Pucka <mantas@8devices.com>
+---
+ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+@@ -106,42 +106,42 @@
+ 
+ 		opp-864000000 {
+ 			opp-hz = /bits/ 64 <864000000>;
+-			opp-microvolt = <725000>;
++			opp-microvolt = <1>;
+ 			opp-supported-hw = <0xf>;
+ 			clock-latency-ns = <200000>;
+ 		};
+ 
+ 		opp-1056000000 {
+ 			opp-hz = /bits/ 64 <1056000000>;
+-			opp-microvolt = <787500>;
++			opp-microvolt = <2>;
+ 			opp-supported-hw = <0xf>;
+ 			clock-latency-ns = <200000>;
+ 		};
+ 
+ 		opp-1320000000 {
+ 			opp-hz = /bits/ 64 <1320000000>;
+-			opp-microvolt = <862500>;
++			opp-microvolt = <3>;
+ 			opp-supported-hw = <0x3>;
+ 			clock-latency-ns = <200000>;
+ 		};
+ 
+ 		opp-1440000000 {
+ 			opp-hz = /bits/ 64 <1440000000>;
+-			opp-microvolt = <925000>;
++			opp-microvolt = <4>;
+ 			opp-supported-hw = <0x3>;
+ 			clock-latency-ns = <200000>;
+ 		};
+ 
+ 		opp-1608000000 {
+ 			opp-hz = /bits/ 64 <1608000000>;
+-			opp-microvolt = <987500>;
++			opp-microvolt = <5>;
+ 			opp-supported-hw = <0x1>;
+ 			clock-latency-ns = <200000>;
+ 		};
+ 
+ 		opp-1800000000 {
+ 			opp-hz = /bits/ 64 <1800000000>;
+-			opp-microvolt = <1062500>;
++			opp-microvolt = <6>;
+ 			opp-supported-hw = <0x1>;
+ 			clock-latency-ns = <200000>;
+ 		};
diff --git a/target/linux/ramips/Makefile b/target/linux/ramips/Makefile
index 77b82d5334c220..1aaa8473450815 100644
--- a/target/linux/ramips/Makefile
+++ b/target/linux/ramips/Makefile
@@ -11,6 +11,7 @@ SUBTARGETS:=mt7620 mt7621 mt76x8 rt288x rt305x rt3883
 FEATURES:=squashfs gpio
 
 KERNEL_PATCHVER:=5.15
+KERNEL_TESTING_PATCHVER:=6.1
 
 define Target/Description
 	Build firmware images for Ralink RT288x/RT3xxx based boards.
diff --git a/target/linux/ramips/dts/mt7620a_aigale_ai-br100.dts b/target/linux/ramips/dts/mt7620a_aigale_ai-br100.dts
index bbd8c47a829498..00f0b528054f6c 100644
--- a/target/linux/ramips/dts/mt7620a_aigale_ai-br100.dts
+++ b/target/linux/ramips/dts/mt7620a_aigale_ai-br100.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "aigale,ai-br100", "ralink,mt7620a-soc";
@@ -18,12 +19,14 @@
 		compatible = "gpio-leds";
 
 		wan {
-			label = "blue:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
 		};
 
 		led_wlan: wlan {
-			label = "blue:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -72,7 +75,7 @@
 				read-only;
 			};
 
-			factory: partition@30000 {
+			partition@30000 {
 				label = "factory";
 				reg = <0x30000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_alfa-network_ac1200rm.dts b/target/linux/ramips/dts/mt7620a_alfa-network_ac1200rm.dts
index 8ac74f70628a23..1b04903ef53911 100644
--- a/target/linux/ramips/dts/mt7620a_alfa-network_ac1200rm.dts
+++ b/target/linux/ramips/dts/mt7620a_alfa-network_ac1200rm.dts
@@ -8,6 +8,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "alfa-network,ac1200rm", "ralink,mt7620a-soc";
@@ -41,7 +42,8 @@
 		};
 
 		led_wps: wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
 		};
 	};
@@ -132,7 +134,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_alfa-network_r36m-e4g.dts b/target/linux/ramips/dts/mt7620a_alfa-network_r36m-e4g.dts
index 2325d53153daa7..1eefd4d396bb97 100644
--- a/target/linux/ramips/dts/mt7620a_alfa-network_r36m-e4g.dts
+++ b/target/linux/ramips/dts/mt7620a_alfa-network_r36m-e4g.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "alfa-network,r36m-e4g", "ralink,mt7620a-soc";
@@ -86,7 +87,8 @@
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
 		};
 
@@ -109,12 +111,14 @@
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
 		};
 
 		wlan {
-			label = "orange:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0radio";
 		};
@@ -188,7 +192,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_alfa-network_tube-e4g.dts b/target/linux/ramips/dts/mt7620a_alfa-network_tube-e4g.dts
index f5fa410090890e..95ba2c7cdf5b1d 100644
--- a/target/linux/ramips/dts/mt7620a_alfa-network_tube-e4g.dts
+++ b/target/linux/ramips/dts/mt7620a_alfa-network_tube-e4g.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "alfa-network,tube-e4g", "ralink,mt7620a-soc";
@@ -74,12 +75,14 @@
 		};
 
 		lan {
-			label = "blue:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
 		};
 
 		power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
 			default-state = "keep";
 		};
@@ -161,7 +164,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_asus_rp-n53.dts b/target/linux/ramips/dts/mt7620a_asus_rp-n53.dts
index a32cb96f66fa88..f7d8d96d4e8bc7 100644
--- a/target/linux/ramips/dts/mt7620a_asus_rp-n53.dts
+++ b/target/linux/ramips/dts/mt7620a_asus_rp-n53.dts
@@ -119,7 +119,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_asus_rt-ac5x.dtsi b/target/linux/ramips/dts/mt7620a_asus_rt-ac5x.dtsi
index 92119ff8127ccd..9c441f74309a95 100644
--- a/target/linux/ramips/dts/mt7620a_asus_rt-ac5x.dtsi
+++ b/target/linux/ramips/dts/mt7620a_asus_rt-ac5x.dtsi
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -32,12 +33,14 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
 		};
 
 		usb {
-			label = "blue:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&ohci_port1>, <&ehci_port1>;
 			linux,default-trigger = "usbport";
@@ -78,7 +81,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_bdcom_wap2100-sk.dts b/target/linux/ramips/dts/mt7620a_bdcom_wap2100-sk.dts
index 4d442825a97b4e..39d79c8ed629ea 100644
--- a/target/linux/ramips/dts/mt7620a_bdcom_wap2100-sk.dts
+++ b/target/linux/ramips/dts/mt7620a_bdcom_wap2100-sk.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "bdcom,wap2100-sk", "ralink,mt7620a-soc";
@@ -22,14 +23,16 @@
 		compatible = "gpio-leds";
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&ohci_port1>, <&ehci_port1>;
 			linux,default-trigger = "usbport";
 		};
 
 		led_power: wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
 		};
 
@@ -81,7 +84,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_buffalo_whr-1166d.dts b/target/linux/ramips/dts/mt7620a_buffalo_whr-1166d.dts
index 17bf2f8272eed9..83080b38db9164 100644
--- a/target/linux/ramips/dts/mt7620a_buffalo_whr-1166d.dts
+++ b/target/linux/ramips/dts/mt7620a_buffalo_whr-1166d.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "buffalo,whr-1166d", "ralink,mt7620a-soc";
@@ -18,7 +19,8 @@
 		compatible = "gpio-leds";
 
 		power {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
 		};
 
@@ -28,7 +30,8 @@
 		};
 
 		led_power_green: power2 {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
 		};
 
@@ -113,7 +116,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_buffalo_whr-300hp2.dts b/target/linux/ramips/dts/mt7620a_buffalo_whr-300hp2.dts
index 85946ca1e0bb13..05d5a494ed6e2a 100644
--- a/target/linux/ramips/dts/mt7620a_buffalo_whr-300hp2.dts
+++ b/target/linux/ramips/dts/mt7620a_buffalo_whr-300hp2.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "buffalo,whr-300hp2", "ralink,mt7620a-soc";
@@ -18,7 +19,8 @@
 		compatible = "gpio-leds";
 
 		power {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
 		};
 
@@ -28,7 +30,8 @@
 		};
 
 		led_power_green: power2 {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
 		};
 
@@ -113,7 +116,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_buffalo_whr-600d.dts b/target/linux/ramips/dts/mt7620a_buffalo_whr-600d.dts
index b571d122cf366e..5eab3f83ac07f1 100644
--- a/target/linux/ramips/dts/mt7620a_buffalo_whr-600d.dts
+++ b/target/linux/ramips/dts/mt7620a_buffalo_whr-600d.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "buffalo,whr-600d", "ralink,mt7620a-soc";
@@ -18,7 +19,8 @@
 		compatible = "gpio-leds";
 
 		power {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
 		};
 
@@ -28,7 +30,8 @@
 		};
 
 		led_power_green: power2 {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
 		};
 
@@ -113,7 +116,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_cameo_810.dtsi b/target/linux/ramips/dts/mt7620a_cameo_810.dtsi
index d09f4d292ebdf0..2ca25d217964bb 100644
--- a/target/linux/ramips/dts/mt7620a_cameo_810.dtsi
+++ b/target/linux/ramips/dts/mt7620a_cameo_810.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -34,22 +35,26 @@
 		compatible = "gpio-leds";
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
 		};
 
 		wan_orange {
-			label = "orange:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
 		};
 
 		wan_green {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
 		};
 
 		power_orange {
-			label = "orange:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
 		};
 	};
@@ -80,7 +85,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
@@ -106,7 +111,7 @@
 				};
 			};
 
-			factory5g: partition@50000 {
+			partition@50000 {
 				label = "factory5g";
 				reg = <0x50000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_dlink_dch-m225.dts b/target/linux/ramips/dts/mt7620a_dlink_dch-m225.dts
index 6d5d461c8fa5fe..7ea288615c7917 100644
--- a/target/linux/ramips/dts/mt7620a_dlink_dch-m225.dts
+++ b/target/linux/ramips/dts/mt7620a_dlink_dch-m225.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "dlink,dch-m225", "ralink,mt7620a-soc";
@@ -34,13 +35,15 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		status {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -118,7 +121,7 @@
 				read-only;
 			};
 
-			factory: partition@34000 {
+			partition@34000 {
 				label = "factory";
 				reg = <0x34000 0x4000>;
 				read-only;
@@ -138,7 +141,7 @@
 				};
 			};
 
-			nvram: partition@38000 {
+			partition@38000 {
 				label = "nvram";
 				reg = <0x38000 0x8000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_dlink_dir-510l.dts b/target/linux/ramips/dts/mt7620a_dlink_dir-510l.dts
index febfd2e32eda96..03f57390916e4f 100644
--- a/target/linux/ramips/dts/mt7620a_dlink_dir-510l.dts
+++ b/target/linux/ramips/dts/mt7620a_dlink_dir-510l.dts
@@ -3,6 +3,7 @@
 #include "mt7620a.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/mtd/partitions/uimage.h>
 
@@ -41,12 +42,14 @@
 		compatible = "gpio-leds";
 
 		led_status: status {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
 		};
 
 		status-red {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
 		};
 	};
@@ -93,7 +96,7 @@
 				reg = <0x210000 0xde0000>;
 			};
 
-			config: partition@ff0000 {
+			partition@ff0000 {
 				label = "config";
 				reg = <0xff0000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_dlink_dir-806a-b1.dts b/target/linux/ramips/dts/mt7620a_dlink_dir-806a-b1.dts
index 52739f511461f9..3faabba9be2591 100644
--- a/target/linux/ramips/dts/mt7620a_dlink_dir-806a-b1.dts
+++ b/target/linux/ramips/dts/mt7620a_dlink_dir-806a-b1.dts
@@ -31,14 +31,12 @@
 		compatible = "gpio-leds";
 
 		wifi_led: 2.4g {
-			label = "green:wlan";
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_WLAN;
 			gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;	// #72
 		};
 
 		wps_led: wps {
-			label = "green:wps";
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_WPS;
 			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;	// #39
@@ -90,7 +88,7 @@
 				reg = <0x30000 0x10000>;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "Factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_dlink_dwr-118-a1.dts b/target/linux/ramips/dts/mt7620a_dlink_dwr-118-a1.dts
index 97fc4f0935c45b..978de470f0a182 100644
--- a/target/linux/ramips/dts/mt7620a_dlink_dwr-118-a1.dts
+++ b/target/linux/ramips/dts/mt7620a_dlink_dwr-118-a1.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/mtd/partitions/uimage.h>
 
 / {
@@ -36,7 +37,8 @@
 		compatible = "gpio-leds";
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
 		};
 
@@ -46,7 +48,8 @@
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
 		};
 
@@ -56,7 +59,8 @@
 		};
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&ohci_port1>, <&ehci_port1>;
 			linux,default-trigger = "usbport";
@@ -114,7 +118,7 @@
 				reg = <0x10000 0xfe0000>;
 			};
 
-			config: partition@ff0000 {
+			partition@ff0000 {
 				label = "config";
 				reg = <0xff0000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_dlink_dwr-118-a2.dts b/target/linux/ramips/dts/mt7620a_dlink_dwr-118-a2.dts
index 5f11b73ad9e40d..c99febdd8515f0 100644
--- a/target/linux/ramips/dts/mt7620a_dlink_dwr-118-a2.dts
+++ b/target/linux/ramips/dts/mt7620a_dlink_dwr-118-a2.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/mtd/partitions/uimage.h>
 
 / {
@@ -33,7 +34,8 @@
 		compatible = "gpio-leds";
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
 		};
 
@@ -43,7 +45,8 @@
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
 		};
 
@@ -53,7 +56,8 @@
 		};
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&ohci_port1>, <&ehci_port1>;
 			linux,default-trigger = "usbport";
@@ -111,7 +115,7 @@
 				reg = <0x10000 0xfe0000>;
 			};
 
-			config: partition@ff0000 {
+			partition@ff0000 {
 				label = "config";
 				reg = <0xff0000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_dlink_dwr-96x.dtsi b/target/linux/ramips/dts/mt7620a_dlink_dwr-96x.dtsi
index 11cd15922cc161..a83a7377ad7072 100644
--- a/target/linux/ramips/dts/mt7620a_dlink_dwr-96x.dtsi
+++ b/target/linux/ramips/dts/mt7620a_dlink_dwr-96x.dtsi
@@ -7,6 +7,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/mtd/partitions/uimage.h>
 
 / {
@@ -38,17 +39,20 @@
 		compatible = "gpio-leds";
 
 		led_status: status {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
 		};
 
@@ -150,7 +154,7 @@
 				reg = <0x10000 0xfe0000>;
 			};
 
-			config: partition@ff0000 {
+			partition@ff0000 {
 				label = "config";
 				reg = <0xff0000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_domywifi.dtsi b/target/linux/ramips/dts/mt7620a_domywifi.dtsi
index 778de63f1bc9db..e2bd8e103bda08 100644
--- a/target/linux/ramips/dts/mt7620a_domywifi.dtsi
+++ b/target/linux/ramips/dts/mt7620a_domywifi.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -67,7 +68,8 @@
 		};
 
 		wan {
-			label = "amber:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
 		};
 
@@ -113,7 +115,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_dovado_tiny-ac.dts b/target/linux/ramips/dts/mt7620a_dovado_tiny-ac.dts
index 821aa04f9531e9..cbc67c942ea4c2 100644
--- a/target/linux/ramips/dts/mt7620a_dovado_tiny-ac.dts
+++ b/target/linux/ramips/dts/mt7620a_dovado_tiny-ac.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "dovado,tiny-ac", "ralink,mt7620a-soc";
@@ -11,7 +12,8 @@
 		compatible = "gpio-leds";
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&ohci_port1>, <&ehci_port1>;
 			linux,default-trigger = "usbport";
@@ -78,7 +80,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_edimax_br-6208ac-v2.dts b/target/linux/ramips/dts/mt7620a_edimax_br-6208ac-v2.dts
index 34b62a025aa0ad..23af7db0d415d9 100644
--- a/target/linux/ramips/dts/mt7620a_edimax_br-6208ac-v2.dts
+++ b/target/linux/ramips/dts/mt7620a_edimax_br-6208ac-v2.dts
@@ -37,7 +37,6 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_POWER;
 			gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
@@ -45,14 +44,12 @@
 
 		// RALINK_REG_PIO3924DATA 39-24
 		led_internet: internet {
-			label = "green:internet";
 			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
 		};
 
 		// RALINK_REG_PIO7140DATA 44-40
 		led_wlan_2_4ghz: wlan_2_4ghz {
-			label = "green:wlan2g";
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_WLAN;
 			gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
@@ -61,7 +58,6 @@
 
 		// RALINK_REG_PIO7140DATA 43-40
 		led_wlan_5ghz: wlan_5ghz {
-			label = "green:wlan5g";
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_WLAN;
 			gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
@@ -70,7 +66,6 @@
 
 		// RALINK_REG_PIO7140DATA 42-40
 		led_firmware: firmware {
-			label = "green:firmware";
 			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
 			// default-state = "keep";
@@ -78,7 +73,6 @@
 
 		// RALINK_REG_PIO7140DATA 41-40
 		led_vpn: vpn {
-			label = "green:vpn";
 			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
 		};
@@ -140,7 +134,7 @@
 			};
 
 			// Factory
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_edimax_br-6478ac-v2.dts b/target/linux/ramips/dts/mt7620a_edimax_br-6478ac-v2.dts
index 486f6399df4911..fe8ce7953b86e5 100644
--- a/target/linux/ramips/dts/mt7620a_edimax_br-6478ac-v2.dts
+++ b/target/linux/ramips/dts/mt7620a_edimax_br-6478ac-v2.dts
@@ -9,6 +9,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/mtd/partitions/uimage.h>
 
 / {
@@ -36,7 +37,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "white:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
 		};
 
@@ -46,12 +48,14 @@
 		};
 
 		wlan {
-			label = "blue:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
 		};
 
 		usb {
-			label = "blue:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&ohci_port1>, <&ehci_port1>;
 			linux,default-trigger = "usbport";
@@ -98,7 +102,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_edimax_ew-7478apc.dts b/target/linux/ramips/dts/mt7620a_edimax_ew-7478apc.dts
index 5759774f6ee210..091f6ecd784c57 100644
--- a/target/linux/ramips/dts/mt7620a_edimax_ew-7478apc.dts
+++ b/target/linux/ramips/dts/mt7620a_edimax_ew-7478apc.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/mtd/partitions/uimage.h>
 
 / {
@@ -31,7 +32,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "white:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
 		};
 
@@ -41,12 +43,14 @@
 		};
 
 		wlan {
-			label = "blue:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
 		};
 
 		usb {
-			label = "blue:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&ohci_port1>, <&ehci_port1>;
 			linux,default-trigger = "usbport";
@@ -90,7 +94,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_edimax_ew-747x.dtsi b/target/linux/ramips/dts/mt7620a_edimax_ew-747x.dtsi
index eb21ff7d6f9676..65b69a576aa96a 100644
--- a/target/linux/ramips/dts/mt7620a_edimax_ew-747x.dtsi
+++ b/target/linux/ramips/dts/mt7620a_edimax_ew-747x.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/mtd/partitions/uimage.h>
 
 / {
@@ -30,17 +31,20 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio2 27 GPIO_ACTIVE_LOW>;
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -79,7 +83,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_engenius_epg600.dts b/target/linux/ramips/dts/mt7620a_engenius_epg600.dts
index 4b3332d2f0742c..85911a68d8ac1d 100644
--- a/target/linux/ramips/dts/mt7620a_engenius_epg600.dts
+++ b/target/linux/ramips/dts/mt7620a_engenius_epg600.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "engenius,epg600", "ralink,mt7620a-soc";
@@ -46,7 +47,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
@@ -115,7 +117,7 @@
 				reg = <0x30000 0x10000>;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
@@ -131,7 +133,7 @@
 				};
 			};
 
-			rf: partition@50000 {
+			partition@50000 {
 				label = "rf";
 				reg = <0x50000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_engenius_esr600.dts b/target/linux/ramips/dts/mt7620a_engenius_esr600.dts
index beee73f11c8749..f8429a021b8f80 100644
--- a/target/linux/ramips/dts/mt7620a_engenius_esr600.dts
+++ b/target/linux/ramips/dts/mt7620a_engenius_esr600.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "engenius,esr600", "ralink,mt7620a-soc";
@@ -24,7 +25,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
 		};
 
@@ -97,7 +99,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
@@ -113,7 +115,7 @@
 				};
 			};
 
-			iNIC_rf: partition@50000 {
+			partition@50000 {
 				label = "iNIC_rf";
 				reg = <0x50000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_fon_fon2601.dts b/target/linux/ramips/dts/mt7620a_fon_fon2601.dts
index 7adf0faf868d22..2e81c2038b4641 100644
--- a/target/linux/ramips/dts/mt7620a_fon_fon2601.dts
+++ b/target/linux/ramips/dts/mt7620a_fon_fon2601.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "fon,fon2601", "ralink,mt7620a-soc";
@@ -20,7 +21,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power_r {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
 		};
 
@@ -76,7 +78,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_glinet_gl-mt300a.dts b/target/linux/ramips/dts/mt7620a_glinet_gl-mt300a.dts
index 122654d6792616..8c4ff5d1d1bf57 100644
--- a/target/linux/ramips/dts/mt7620a_glinet_gl-mt300a.dts
+++ b/target/linux/ramips/dts/mt7620a_glinet_gl-mt300a.dts
@@ -94,7 +94,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_glinet_gl-mt300n.dts b/target/linux/ramips/dts/mt7620a_glinet_gl-mt300n.dts
index 9b21689d8d1195..8dc36558833320 100644
--- a/target/linux/ramips/dts/mt7620a_glinet_gl-mt300n.dts
+++ b/target/linux/ramips/dts/mt7620a_glinet_gl-mt300n.dts
@@ -89,7 +89,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_glinet_gl-mt750.dts b/target/linux/ramips/dts/mt7620a_glinet_gl-mt750.dts
index b595c581fe9468..177cd7873d2d32 100644
--- a/target/linux/ramips/dts/mt7620a_glinet_gl-mt750.dts
+++ b/target/linux/ramips/dts/mt7620a_glinet_gl-mt750.dts
@@ -89,7 +89,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_head-weblink_hdrm200.dts b/target/linux/ramips/dts/mt7620a_head-weblink_hdrm200.dts
index db00daaec225e2..55936219e3bbf2 100644
--- a/target/linux/ramips/dts/mt7620a_head-weblink_hdrm200.dts
+++ b/target/linux/ramips/dts/mt7620a_head-weblink_hdrm200.dts
@@ -81,7 +81,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
@@ -105,7 +105,7 @@
 				};
 			};
 
-			firmware: partition@50000 {
+			partition@50000 {
 				compatible = "denx,uimage";
 				label = "firmware";
 				reg = <0x50000 0xfb0000>;
diff --git a/target/linux/ramips/dts/mt7620a_hiwifi_hc5x61.dtsi b/target/linux/ramips/dts/mt7620a_hiwifi_hc5x61.dtsi
index 885c1bac49c17b..7fcd68e6ba2ea8 100644
--- a/target/linux/ramips/dts/mt7620a_hiwifi_hc5x61.dtsi
+++ b/target/linux/ramips/dts/mt7620a_hiwifi_hc5x61.dtsi
@@ -51,7 +51,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
@@ -87,7 +87,7 @@
 				read-only;
 			};
 
-			bdinfo: partition@fe0000 {
+			partition@fe0000 {
 				label = "bdinfo";
 				reg = <0xfe0000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_hnet_c108.dts b/target/linux/ramips/dts/mt7620a_hnet_c108.dts
index 60c6b2a7d4ae51..6f62243ecfb043 100644
--- a/target/linux/ramips/dts/mt7620a_hnet_c108.dts
+++ b/target/linux/ramips/dts/mt7620a_hnet_c108.dts
@@ -8,6 +8,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "hnet,c108", "ralink,mt7620a-soc";
@@ -54,12 +55,14 @@
 		};
 
 		lan_red {
-			label = "red:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_lan_green: lan_green {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>;
 		};
 	};
@@ -108,7 +111,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_humax_e2.dts b/target/linux/ramips/dts/mt7620a_humax_e2.dts
index 453208eb34ed90..dc5635e65e94d2 100644
--- a/target/linux/ramips/dts/mt7620a_humax_e2.dts
+++ b/target/linux/ramips/dts/mt7620a_humax_e2.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/mtd/partitions/uimage.h>
 
 / {
@@ -22,7 +23,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
 		};
 
@@ -32,17 +34,20 @@
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -87,7 +92,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x30000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_iodata_wn-ac1167gr.dts b/target/linux/ramips/dts/mt7620a_iodata_wn-ac1167gr.dts
index 6f95bd015149f4..e80ff16f31e9cb 100644
--- a/target/linux/ramips/dts/mt7620a_iodata_wn-ac1167gr.dts
+++ b/target/linux/ramips/dts/mt7620a_iodata_wn-ac1167gr.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "iodata,wn-ac1167gr", "ralink,mt7620a-soc";
@@ -20,7 +21,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
@@ -90,7 +92,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x8000>;
 				read-only;
@@ -110,7 +112,7 @@
 				};
 			};
 
-			iNIC_rf: partition@48000 {
+			partition@48000 {
 				label = "iNIC_rf";
 				reg = <0x48000 0x8000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_iodata_wn-ac733gr3.dts b/target/linux/ramips/dts/mt7620a_iodata_wn-ac733gr3.dts
index bc674fa4b3044f..d95a4ad99df190 100644
--- a/target/linux/ramips/dts/mt7620a_iodata_wn-ac733gr3.dts
+++ b/target/linux/ramips/dts/mt7620a_iodata_wn-ac733gr3.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "iodata,wn-ac733gr3", "ralink,mt7620a-soc";
@@ -20,7 +21,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
@@ -104,7 +106,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x8000>;
 				read-only;
@@ -124,7 +126,7 @@
 				};
 			};
 
-			iNIC_rf: partition@48000 {
+			partition@48000 {
 				label = "iNIC_rf";
 				reg = <0x48000 0x8000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_iptime.dtsi b/target/linux/ramips/dts/mt7620a_iptime.dtsi
index 2b7421de9b79f5..1de1328aa5371c 100644
--- a/target/linux/ramips/dts/mt7620a_iptime.dtsi
+++ b/target/linux/ramips/dts/mt7620a_iptime.dtsi
@@ -28,7 +28,7 @@
 			#address-cells = <1>;
 			#size-cells = <1>;
 
-			uboot: partition@0 {
+			partition@0 {
 				label = "u-boot";
 				reg = <0x0 0x20000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_iptime_a1004ns.dts b/target/linux/ramips/dts/mt7620a_iptime_a1004ns.dts
index 6270af3b15895b..5c5637c1988d82 100644
--- a/target/linux/ramips/dts/mt7620a_iptime_a1004ns.dts
+++ b/target/linux/ramips/dts/mt7620a_iptime_a1004ns.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "mt7620a_iptime.dtsi"
 
 / {
@@ -17,12 +19,14 @@
 		compatible = "gpio-leds";
 
 		led_cpu: cpu {
-			label = "blue:cpu";
+			function = LED_FUNCTION_CPU;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
 		};
 
 		usb {
-			label = "blue:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&ohci_port1>, <&ehci_port1>;
 			linux,default-trigger = "usbport";
diff --git a/target/linux/ramips/dts/mt7620a_iptime_a104ns.dts b/target/linux/ramips/dts/mt7620a_iptime_a104ns.dts
index c997d68cd12fbe..f76d184c44a917 100644
--- a/target/linux/ramips/dts/mt7620a_iptime_a104ns.dts
+++ b/target/linux/ramips/dts/mt7620a_iptime_a104ns.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "mt7620a_iptime.dtsi"
 
 / {
@@ -17,14 +19,16 @@
 		compatible = "gpio-leds";
 
 		usb {
-			label = "blue:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&ohci_port1>, <&ehci_port1>;
 			linux,default-trigger = "usbport";
 		};
 
 		led_cpu: cpu {
-			label = "blue:cpu";
+			function = LED_FUNCTION_CPU;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/mt7620a_kimax_u25awf-h1.dts b/target/linux/ramips/dts/mt7620a_kimax_u25awf-h1.dts
index 772cab32e2ae0b..ad82fac69aaef8 100644
--- a/target/linux/ramips/dts/mt7620a_kimax_u25awf-h1.dts
+++ b/target/linux/ramips/dts/mt7620a_kimax_u25awf-h1.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 /{
 	compatible = "kimax,u25awf-h1","ralink,mt7620a-soc";
@@ -33,7 +34,8 @@
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -72,7 +74,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_lava_lr-25g001.dts b/target/linux/ramips/dts/mt7620a_lava_lr-25g001.dts
index f43aa2d3bca643..e0346922d7d0da 100644
--- a/target/linux/ramips/dts/mt7620a_lava_lr-25g001.dts
+++ b/target/linux/ramips/dts/mt7620a_lava_lr-25g001.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/mtd/partitions/uimage.h>
 
 / {
@@ -35,7 +36,8 @@
 		compatible = "gpio-leds";
 
 		led_status: status {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
 		};
 
@@ -91,7 +93,7 @@
 				reg = <0x10000 0xfe0000>;
 			};
 
-			config: partition@ff0000 {
+			partition@ff0000 {
 				label = "config";
 				reg = <0xff0000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_lb-link_bl-w1200.dts b/target/linux/ramips/dts/mt7620a_lb-link_bl-w1200.dts
index cefc3c3e925de8..3473ed54b04866 100644
--- a/target/linux/ramips/dts/mt7620a_lb-link_bl-w1200.dts
+++ b/target/linux/ramips/dts/mt7620a_lb-link_bl-w1200.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "lb-link,bl-w1200", "ralink,mt7620a-soc";
@@ -29,7 +30,8 @@
 		compatible = "gpio-leds";
 
 		led_wps: wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -64,7 +66,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_lenovo_newifi-y1.dts b/target/linux/ramips/dts/mt7620a_lenovo_newifi-y1.dts
index 24b79711c5e4af..19e349528cc4ab 100644
--- a/target/linux/ramips/dts/mt7620a_lenovo_newifi-y1.dts
+++ b/target/linux/ramips/dts/mt7620a_lenovo_newifi-y1.dts
@@ -1,3 +1,5 @@
+#include <dt-bindings/leds/common.h>
+
 #include "mt7620a_lenovo_newifi-y1.dtsi"
 
 / {
@@ -16,7 +18,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
 		};
 
@@ -31,14 +34,16 @@
 		};
 
 		usb {
-			label = "blue:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&ohci_port1>, <&ehci_port1>;
 			linux,default-trigger = "usbport";
 		};
 
 		lan {
-			label = "blue:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ramips/dts/mt7620a_lenovo_newifi-y1.dtsi b/target/linux/ramips/dts/mt7620a_lenovo_newifi-y1.dtsi
index 4ba9779dfdc796..8b9d14702161d1 100644
--- a/target/linux/ramips/dts/mt7620a_lenovo_newifi-y1.dtsi
+++ b/target/linux/ramips/dts/mt7620a_lenovo_newifi-y1.dtsi
@@ -54,7 +54,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_lenovo_newifi-y1s.dts b/target/linux/ramips/dts/mt7620a_lenovo_newifi-y1s.dts
index f1d2c873371166..8d0dad10e93bb5 100644
--- a/target/linux/ramips/dts/mt7620a_lenovo_newifi-y1s.dts
+++ b/target/linux/ramips/dts/mt7620a_lenovo_newifi-y1s.dts
@@ -1,3 +1,5 @@
+#include <dt-bindings/leds/common.h>
+
 #include "mt7620a_lenovo_newifi-y1.dtsi"
 
 / {
@@ -37,12 +39,14 @@
 		compatible = "gpio-leds";
 
 		power1 {
-			label = "yellow:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_YELLOW>;
 			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_blue: power2 {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
 		};
 
@@ -57,12 +61,14 @@
 		};
 
 		usb1 {
-			label = "yellow:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_YELLOW>;
 			gpios = <&gpio2 13 GPIO_ACTIVE_LOW>;
 		};
 
 		usb2 {
-			label = "blue:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&ohci_port1>, <&ehci_port1>;
 			linux,default-trigger = "usbport";
diff --git a/target/linux/ramips/dts/mt7620a_linksys_e1700.dts b/target/linux/ramips/dts/mt7620a_linksys_e1700.dts
index 4310f9dfc7fadf..caa6780d600a4d 100644
--- a/target/linux/ramips/dts/mt7620a_linksys_e1700.dts
+++ b/target/linux/ramips/dts/mt7620a_linksys_e1700.dts
@@ -7,6 +7,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "linksys,e1700", "ralink,mt7620a-soc";
@@ -39,12 +40,14 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
 		};
 
 		wan {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -75,7 +78,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_microduino_microwrt.dts b/target/linux/ramips/dts/mt7620a_microduino_microwrt.dts
index afba7a06f33a0e..a9aa27652b7045 100644
--- a/target/linux/ramips/dts/mt7620a_microduino_microwrt.dts
+++ b/target/linux/ramips/dts/mt7620a_microduino_microwrt.dts
@@ -53,7 +53,7 @@
 				read-only;
 			};
 
-			factory: partition@30000 {
+			partition@30000 {
 				label = "factory";
 				reg = <0x30000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_netcore_nw5212.dts b/target/linux/ramips/dts/mt7620a_netcore_nw5212.dts
index 34c3d4f42d878e..2e112c71791f20 100644
--- a/target/linux/ramips/dts/mt7620a_netcore_nw5212.dts
+++ b/target/linux/ramips/dts/mt7620a_netcore_nw5212.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "netcore,nw5212", "ralink,mt7620a-soc";
@@ -37,7 +38,8 @@
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
 		};
 
@@ -92,7 +94,7 @@
 				reg = <0x30000 0x10000>;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_netgear_ex2700.dts b/target/linux/ramips/dts/mt7620a_netgear_ex2700.dts
index 79b622b1bb38c1..c39984dbf9fd35 100644
--- a/target/linux/ramips/dts/mt7620a_netgear_ex2700.dts
+++ b/target/linux/ramips/dts/mt7620a_netgear_ex2700.dts
@@ -7,6 +7,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "netgear,ex2700", "ralink,mt7620a-soc";
@@ -39,13 +40,15 @@
 		compatible = "gpio-leds";
 
 		led_power_green: power_g {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		power_r {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
 		};
 
@@ -70,7 +73,8 @@
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -111,7 +115,7 @@
 				reg = <0x40000 0x3b0000>;
 			};
 
-			art: partition@3f0000 {
+			partition@3f0000 {
 				label = "art";
 				reg = <0x3f0000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_netgear_ex3x00_ex61xx.dtsi b/target/linux/ramips/dts/mt7620a_netgear_ex3x00_ex61xx.dtsi
index fe26c3b8594945..d06a89821a182c 100644
--- a/target/linux/ramips/dts/mt7620a_netgear_ex3x00_ex61xx.dtsi
+++ b/target/linux/ramips/dts/mt7620a_netgear_ex3x00_ex61xx.dtsi
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -31,13 +32,15 @@
 		compatible = "gpio-leds";
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		led_power_amber: power_amber {
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
 		};
 
@@ -62,7 +65,8 @@
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio2 27 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -97,7 +101,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_netgear_wn3x00rp.dtsi b/target/linux/ramips/dts/mt7620a_netgear_wn3x00rp.dtsi
index 8810742e6718d4..1ecd9fc4a76681 100644
--- a/target/linux/ramips/dts/mt7620a_netgear_wn3x00rp.dtsi
+++ b/target/linux/ramips/dts/mt7620a_netgear_wn3x00rp.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -33,13 +34,15 @@
 		compatible = "gpio-leds";
 
 		led_power_green: power_g {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		power_r {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
 		};
 
@@ -64,7 +67,8 @@
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
 		};
 
@@ -115,7 +119,7 @@
 				reg = <0x40000 0x7b0000>;
 			};
 
-			art: partition@7f0000 {
+			partition@7f0000 {
 				label = "art";
 				reg = <0x7f0000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_netis_wf2770.dts b/target/linux/ramips/dts/mt7620a_netis_wf2770.dts
index c2ef1426231388..dd66b120401e6f 100644
--- a/target/linux/ramips/dts/mt7620a_netis_wf2770.dts
+++ b/target/linux/ramips/dts/mt7620a_netis_wf2770.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "netis,wf2770", "ralink,mt7620a-soc";
@@ -13,7 +14,8 @@
 		compatible = "gpio-leds";
 
 		wlan {
-			label = "blue:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
@@ -73,7 +75,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_ohyeah_oy-0001.dts b/target/linux/ramips/dts/mt7620a_ohyeah_oy-0001.dts
index 2c503db80dece9..f842c3d1732961 100644
--- a/target/linux/ramips/dts/mt7620a_ohyeah_oy-0001.dts
+++ b/target/linux/ramips/dts/mt7620a_ohyeah_oy-0001.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "ohyeah,oy-0001", "ralink,mt7620a-soc";
@@ -22,7 +23,8 @@
 		compatible = "gpio-leds";
 
 		led_power: powerled {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
 		};
 
@@ -72,7 +74,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_phicomm_k2x.dtsi b/target/linux/ramips/dts/mt7620a_phicomm_k2x.dtsi
index 588789239f09e3..4faa45933fd86b 100644
--- a/target/linux/ramips/dts/mt7620a_phicomm_k2x.dtsi
+++ b/target/linux/ramips/dts/mt7620a_phicomm_k2x.dtsi
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -25,18 +26,21 @@
 		compatible = "gpio-leds";
 
 		led_blue: blue {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		yellow {
-			label = "yellow:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_YELLOW>;
 			gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
 		};
 
 		red {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
 		};
 	};
@@ -68,7 +72,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_phicomm_psg1208.dts b/target/linux/ramips/dts/mt7620a_phicomm_psg1208.dts
index 74faef8dea62f1..c5c4d01835b81d 100644
--- a/target/linux/ramips/dts/mt7620a_phicomm_psg1208.dts
+++ b/target/linux/ramips/dts/mt7620a_phicomm_psg1208.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "phicomm,psg1208", "ralink,mt7620a-soc";
@@ -18,7 +19,8 @@
 		compatible = "gpio-leds";
 
 		led_wps: wps {
-			label = "white:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
 		};
 
@@ -73,7 +75,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_planex_cs-qr10.dts b/target/linux/ramips/dts/mt7620a_planex_cs-qr10.dts
index eeeb7cf65766fa..db4b286c6b167b 100644
--- a/target/linux/ramips/dts/mt7620a_planex_cs-qr10.dts
+++ b/target/linux/ramips/dts/mt7620a_planex_cs-qr10.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "planex,cs-qr10", "ralink,mt7620a-soc";
@@ -18,7 +19,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -79,7 +81,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_planex_db-wrt01.dts b/target/linux/ramips/dts/mt7620a_planex_db-wrt01.dts
index 53c0215e0ce619..3659f82d279459 100644
--- a/target/linux/ramips/dts/mt7620a_planex_db-wrt01.dts
+++ b/target/linux/ramips/dts/mt7620a_planex_db-wrt01.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "planex,db-wrt01", "ralink,mt7620a-soc";
@@ -18,7 +19,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "orange:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -63,7 +65,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_planex_mzk-750dhp.dts b/target/linux/ramips/dts/mt7620a_planex_mzk-750dhp.dts
index 3c6f7c582ef7ab..4a1d589ab68edb 100644
--- a/target/linux/ramips/dts/mt7620a_planex_mzk-750dhp.dts
+++ b/target/linux/ramips/dts/mt7620a_planex_mzk-750dhp.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "planex,mzk-750dhp", "ralink,mt7620a-soc";
@@ -18,12 +19,14 @@
 		compatible = "gpio-leds";
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
 		};
 
@@ -83,7 +86,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_planex_mzk-ex300np.dts b/target/linux/ramips/dts/mt7620a_planex_mzk-ex300np.dts
index 2879f6d870f473..1c3439b46feb8b 100644
--- a/target/linux/ramips/dts/mt7620a_planex_mzk-ex300np.dts
+++ b/target/linux/ramips/dts/mt7620a_planex_mzk-ex300np.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "planex,mzk-ex300np", "ralink,mt7620a-soc";
@@ -23,7 +24,8 @@
 		};
 
 		led_wps: wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
 		};
 
@@ -98,7 +100,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_planex_mzk-ex750np.dts b/target/linux/ramips/dts/mt7620a_planex_mzk-ex750np.dts
index de4df5d277d4b7..c51739d94a8fb4 100644
--- a/target/linux/ramips/dts/mt7620a_planex_mzk-ex750np.dts
+++ b/target/linux/ramips/dts/mt7620a_planex_mzk-ex750np.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "planex,mzk-ex750np", "ralink,mt7620a-soc";
@@ -18,7 +19,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
 		};
 
@@ -28,7 +30,8 @@
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
 		};
 
@@ -103,7 +106,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_ralink_mt7620a-evb.dts b/target/linux/ramips/dts/mt7620a_ralink_mt7620a-evb.dts
index ae3594150743fb..38edb6bd5e1bb3 100644
--- a/target/linux/ramips/dts/mt7620a_ralink_mt7620a-evb.dts
+++ b/target/linux/ramips/dts/mt7620a_ralink_mt7620a-evb.dts
@@ -49,7 +49,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_ralink_mt7620a-mt7530-evb.dts b/target/linux/ramips/dts/mt7620a_ralink_mt7620a-mt7530-evb.dts
index f7d8cae1602593..c20e9c0df01d4e 100644
--- a/target/linux/ramips/dts/mt7620a_ralink_mt7620a-mt7530-evb.dts
+++ b/target/linux/ramips/dts/mt7620a_ralink_mt7620a-mt7530-evb.dts
@@ -30,7 +30,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_ralink_mt7620a-mt7610e-evb.dts b/target/linux/ramips/dts/mt7620a_ralink_mt7620a-mt7610e-evb.dts
index 02481e5e5575b8..f67c8251831b5d 100644
--- a/target/linux/ramips/dts/mt7620a_ralink_mt7620a-mt7610e-evb.dts
+++ b/target/linux/ramips/dts/mt7620a_ralink_mt7620a-mt7610e-evb.dts
@@ -49,7 +49,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_ralink_mt7620a-v22sg-evb.dts b/target/linux/ramips/dts/mt7620a_ralink_mt7620a-v22sg-evb.dts
index 0e963e1f02aa23..e02e62cd7da3b6 100644
--- a/target/linux/ramips/dts/mt7620a_ralink_mt7620a-v22sg-evb.dts
+++ b/target/linux/ramips/dts/mt7620a_ralink_mt7620a-v22sg-evb.dts
@@ -43,7 +43,7 @@
 				read-only;
 			};
 
-			factory: partition@60000 {
+			partition@60000 {
 				label = "factory";
 				reg = <0x60000 0x20000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_sanlinking_d240.dts b/target/linux/ramips/dts/mt7620a_sanlinking_d240.dts
index 415ecf1bd9fab1..8de20599dfa2c5 100644
--- a/target/linux/ramips/dts/mt7620a_sanlinking_d240.dts
+++ b/target/linux/ramips/dts/mt7620a_sanlinking_d240.dts
@@ -8,6 +8,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "sanlinking,d240", "ralink,mt7620a-soc";
@@ -45,12 +46,14 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
 		};
 
 		usb {
-			label = "blue:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
 			trigger-sources = <&ohci_port1>, <&ehci_port1>;
 			linux,default-trigger = "usbport";
@@ -110,7 +113,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_sercomm_na930.dts b/target/linux/ramips/dts/mt7620a_sercomm_na930.dts
index 1ffc0a2bc815c0..c0452fdcd59d8d 100644
--- a/target/linux/ramips/dts/mt7620a_sercomm_na930.dts
+++ b/target/linux/ramips/dts/mt7620a_sercomm_na930.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "sercomm,na930", "ralink,mt7620a-soc";
@@ -83,7 +84,8 @@
 		};
 
 		status {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&ohci_port1>, <&ehci_port1>;
 			linux,default-trigger = "usbport";
@@ -95,7 +97,8 @@
 		};
 
 		led_power: power {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio2 29 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/mt7620a_sitecom_wlr-4100-v1-002.dts b/target/linux/ramips/dts/mt7620a_sitecom_wlr-4100-v1-002.dts
index d94331a87d9872..e941c55cf43b0e 100644
--- a/target/linux/ramips/dts/mt7620a_sitecom_wlr-4100-v1-002.dts
+++ b/target/linux/ramips/dts/mt7620a_sitecom_wlr-4100-v1-002.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "sitecom,wlr-4100-v1-002", "ralink,mt7620a-soc";
@@ -24,7 +25,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
@@ -36,7 +38,8 @@
 		};
 
 		wps {
-			label = "white:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -102,7 +105,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_tplink_archer-c2-v1.dts b/target/linux/ramips/dts/mt7620a_tplink_archer-c2-v1.dts
index 88d241601019ab..33642114cbeff8 100644
--- a/target/linux/ramips/dts/mt7620a_tplink_archer-c2-v1.dts
+++ b/target/linux/ramips/dts/mt7620a_tplink_archer-c2-v1.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "tplink,archer-c2-v1", "ralink,mt7620a-soc";
@@ -22,29 +23,34 @@
 		compatible = "gpio-leds";
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
 		};
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&ohci_port1>, <&ehci_port1>;
 			linux,default-trigger = "usbport";
 		};
 
 		led_wps: wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy1tpt";
 		};
@@ -67,7 +73,7 @@
 	};
 
 	rtl8367rb {
-		compatible = "realtek,rtl8367b", "rtl8367b";
+		compatible = "realtek,rtl8367b";
 		cpu_port = <6>;
 		realtek,extif1 = <1 0 1 1 1 1 1 1 2>;
 		mii-bus = <&mdio0>;
@@ -105,7 +111,7 @@
 				read-only;
 			};
 
-			rom: partition@7d0000 {
+			partition@7d0000 {
 				label = "rom";
 				reg = <0x7d0000 0x10000>;
 				read-only;
@@ -129,7 +135,7 @@
 				read-only;
 			};
 
-			radio: partition@7f0000 {
+			partition@7f0000 {
 				label = "radio";
 				reg = <0x7f0000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_tplink_archer-c20-v1.dts b/target/linux/ramips/dts/mt7620a_tplink_archer-c20-v1.dts
index e631f6f4e48fcc..726a86ae172128 100644
--- a/target/linux/ramips/dts/mt7620a_tplink_archer-c20-v1.dts
+++ b/target/linux/ramips/dts/mt7620a_tplink_archer-c20-v1.dts
@@ -1,3 +1,5 @@
+#include <dt-bindings/leds/common.h>
+
 #include "mt7620a_tplink_archer.dtsi"
 
 / {
@@ -15,30 +17,35 @@
 		compatible = "gpio-leds";
 
 		lan {
-			label = "blue:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power: power {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
 			default-state = "keep";
 		};
 
 		usb {
-			label = "blue:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&ohci_port1>, <&ehci_port1>;
 			linux,default-trigger = "usbport";
 		};
 
 		wan {
-			label = "blue:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
 		};
 
 		wan_orange {
-			label = "orange:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
 		};
 
@@ -55,7 +62,8 @@
 		};
 
 		wps {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -73,11 +81,11 @@
 	pinctrl-0 = <&pa_pins>;
 	pinctrl-1 = <&pa_gpio_pins>;
 
-	nvmem-cells = <&macaddr_rom_f100 (-2)>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&eeprom_radio_0>, <&macaddr_rom_f100 (-2)>;
+	nvmem-cell-names = "eeprom", "mac-address";
 };
 
 &wifi {
-	nvmem-cells = <&macaddr_rom_f100 (-1)>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&eeprom_radio_8000>, <&macaddr_rom_f100 (-1)>;
+	nvmem-cell-names = "eeprom", "mac-address";
 };
diff --git a/target/linux/ramips/dts/mt7620a_tplink_archer-c20i.dts b/target/linux/ramips/dts/mt7620a_tplink_archer-c20i.dts
index d00d2195eeb5f2..a977156e5fa8fc 100644
--- a/target/linux/ramips/dts/mt7620a_tplink_archer-c20i.dts
+++ b/target/linux/ramips/dts/mt7620a_tplink_archer-c20i.dts
@@ -1,3 +1,5 @@
+#include <dt-bindings/leds/common.h>
+
 #include "mt7620a_tplink_archer.dtsi"
 
 / {
@@ -16,29 +18,34 @@
 		compatible = "gpio-leds";
 
 		lan {
-			label = "blue:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
 		};
 
 		usb {
-			label = "blue:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&ohci_port1>, <&ehci_port1>;
 			linux,default-trigger = "usbport";
 		};
 
 		led_wps: wps {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
 		};
 
 		wan {
-			label = "blue:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
 		};
 
 		wlan {
-			label = "blue:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy1tpt";
 		};
@@ -53,11 +60,11 @@
 };
 
 &wmac {
-	nvmem-cells = <&macaddr_rom_f100 0>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&eeprom_radio_0>, <&macaddr_rom_f100 0>;
+	nvmem-cell-names = "eeprom", "mac-address";
 };
 
 &wifi {
-	nvmem-cells = <&macaddr_rom_f100 (-1)>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&eeprom_radio_8000>, <&macaddr_rom_f100 (-1)>;
+	nvmem-cell-names = "eeprom", "mac-address";
 };
diff --git a/target/linux/ramips/dts/mt7620a_tplink_archer-c5-v4.dts b/target/linux/ramips/dts/mt7620a_tplink_archer-c5-v4.dts
new file mode 100644
index 00000000000000..c02b341d098357
--- /dev/null
+++ b/target/linux/ramips/dts/mt7620a_tplink_archer-c5-v4.dts
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include <dt-bindings/leds/common.h>
+
+#include "mt7620a_tplink_archer.dtsi"
+
+/ {
+	compatible = "tplink,archer-c5-v4", "ralink,mt7620a-soc";
+	model = "TP-Link Archer C5 v4";
+
+	aliases {
+		led-boot = &led_power;
+		led-failsafe = &led_power;
+		led-running = &led_power;
+		led-upgrade = &led_power;
+		label-mac-device = &ethernet;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_power: led-0 {
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
+		};
+
+		led-1 {
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
+			function-enumerator = <2>;
+			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
+			linux,default-trigger = "phy1tpt";
+		};
+
+		led-2 {
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
+			function-enumerator = <5>;
+			gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
+			linux,default-trigger = "phy0tpt";
+		};
+
+		led-3 {
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
+		};
+
+		led-4 {
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_ORANGE>;
+			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
+		};
+
+		led-5 {
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
+		};
+
+		led-6 {
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
+			trigger-sources = <&ohci_port1>, <&ehci_port1>;
+			linux,default-trigger = "usbport";
+		};
+
+		led-7 {
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	rtl8367s {
+		compatible = "realtek,rtl8367b";
+		cpu_port = <7>;
+		realtek,extif2 = <1 0 1 1 1 1 1 1 2>;
+		mii-bus = <&mdio0>;
+		phy-id = <29>;
+	};
+};
+
+&spi0 {
+	flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+	};
+};
+
+&state_default {
+	gpio {
+		groups = "i2c", "uartf", "ephy", "rgmii2";
+		function = "gpio";
+	};
+};
+
+&ethernet {
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii1_pins &mdio_pins>;
+
+	port@5 {
+		status = "okay";
+		mediatek,fixed-link = <1000 1 1 1>;
+		phy-mode = "rgmii";
+	};
+
+	mdio0: mdio-bus {
+		status = "okay";
+		reset-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>;
+		reset-delay-us = <10000>;
+	};
+};
+
+&wmac {
+	pinctrl-names = "default", "pa_gpio";
+	pinctrl-0 = <&pa_pins>;
+	pinctrl-1 = <&pa_gpio_pins>;
+
+	nvmem-cells = <&eeprom_radio_0>, <&macaddr_rom_f100 0>;
+	nvmem-cell-names = "eeprom", "mac-address";
+};
+
+&wifi {
+	nvmem-cells = <&eeprom_radio_8000>, <&macaddr_rom_f100 2>;
+	nvmem-cell-names = "eeprom", "mac-address";
+};
diff --git a/target/linux/ramips/dts/mt7620a_tplink_archer-c50-v1.dts b/target/linux/ramips/dts/mt7620a_tplink_archer-c50-v1.dts
index 439bc36dc3a21d..cfb31b47fe0c9f 100644
--- a/target/linux/ramips/dts/mt7620a_tplink_archer-c50-v1.dts
+++ b/target/linux/ramips/dts/mt7620a_tplink_archer-c50-v1.dts
@@ -1,3 +1,5 @@
+#include <dt-bindings/leds/common.h>
+
 #include "mt7620a_tplink_archer.dtsi"
 
 / {
@@ -15,30 +17,35 @@
 		compatible = "gpio-leds";
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&ohci_port1>, <&ehci_port1>;
 			linux,default-trigger = "usbport";
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
 		};
 
 		wan_orange {
-			label = "orange:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
 		};
 
@@ -55,7 +62,8 @@
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -73,11 +81,11 @@
 	pinctrl-0 = <&pa_pins>;
 	pinctrl-1 = <&pa_gpio_pins>;
 
-	nvmem-cells = <&macaddr_rom_f100 (-2)>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&eeprom_radio_0>, <&macaddr_rom_f100 (-2)>;
+	nvmem-cell-names = "eeprom", "mac-address";
 };
 
 &wifi {
-	nvmem-cells = <&macaddr_rom_f100 (-1)>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&eeprom_radio_8000>, <&macaddr_rom_f100 (-1)>;
+	nvmem-cell-names = "eeprom", "mac-address";
 };
diff --git a/target/linux/ramips/dts/mt7620a_tplink_archer-mr200.dts b/target/linux/ramips/dts/mt7620a_tplink_archer-mr200.dts
index cc947e212e5120..858ea8703f45e4 100644
--- a/target/linux/ramips/dts/mt7620a_tplink_archer-mr200.dts
+++ b/target/linux/ramips/dts/mt7620a_tplink_archer-mr200.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "tplink,archer-mr200", "ralink,mt7620a-soc";
@@ -22,17 +23,20 @@
 		compatible = "gpio-leds";
 
 		lan {
-			label = "white:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
 		};
 
 		wan {
-			label = "white:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power: power {
-			label = "white:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
 		};
 
@@ -42,7 +46,8 @@
 		};
 
 		wps {
-			label = "white:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
 		};
 
@@ -67,7 +72,8 @@
 		};
 
 		wlan {
-			label = "white:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy1tpt";
 		};
@@ -138,7 +144,7 @@
 				reg = <0x20000 0x7b0000>;
 			};
 
-			rom: partition@7d0000 {
+			partition@7d0000 {
 				label = "rom";
 				reg = <0x7d0000 0x10000>;
 				read-only;
@@ -160,7 +166,7 @@
 				read-only;
 			};
 
-			radio: partition@7f0000 {
+			partition@7f0000 {
 				label = "radio";
 				reg = <0x7f0000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_tplink_archer.dtsi b/target/linux/ramips/dts/mt7620a_tplink_archer.dtsi
index 50a91be8ec5fcd..4ba19be495aff1 100644
--- a/target/linux/ramips/dts/mt7620a_tplink_archer.dtsi
+++ b/target/linux/ramips/dts/mt7620a_tplink_archer.dtsi
@@ -68,7 +68,7 @@
 				read-only;
 			};
 
-			rom: partition@7d0000 {
+			partition@7d0000 {
 				label = "rom";
 				reg = <0x7d0000 0x10000>;
 				read-only;
@@ -92,7 +92,7 @@
 				read-only;
 			};
 
-			radio: partition@7f0000 {
+			partition@7f0000 {
 				label = "radio";
 				reg = <0x7f0000 0x10000>;
 				read-only;
@@ -118,7 +118,7 @@
 &ethernet {
 	pinctrl-names = "default";
 
-	nvmem-cells = <&macaddr_rom_f100>;
+	nvmem-cells = <&macaddr_rom_f100 0>;
 	nvmem-cell-names = "mac-address";
 
 	mediatek,portmap = "wllll";
diff --git a/target/linux/ramips/dts/mt7620a_tplink_re200-v1.dts b/target/linux/ramips/dts/mt7620a_tplink_re200-v1.dts
index d2f5207fac1477..fccda507000a01 100644
--- a/target/linux/ramips/dts/mt7620a_tplink_re200-v1.dts
+++ b/target/linux/ramips/dts/mt7620a_tplink_re200-v1.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "mt7620a_tplink_re2x0-v1.dtsi"
 
 / {
@@ -17,17 +19,20 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ramips/dts/mt7620a_tplink_re210-v1.dts b/target/linux/ramips/dts/mt7620a_tplink_re210-v1.dts
index 57cd0ed539f8bc..c92c6e7f0d6257 100644
--- a/target/linux/ramips/dts/mt7620a_tplink_re210-v1.dts
+++ b/target/linux/ramips/dts/mt7620a_tplink_re210-v1.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "mt7620a_tplink_re2x0-v1.dtsi"
 
 / {
@@ -17,7 +19,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ramips/dts/mt7620a_tplink_re2x0-v1.dtsi b/target/linux/ramips/dts/mt7620a_tplink_re2x0-v1.dtsi
index 02f03afc487e60..5f06dd420880ea 100644
--- a/target/linux/ramips/dts/mt7620a_tplink_re2x0-v1.dtsi
+++ b/target/linux/ramips/dts/mt7620a_tplink_re2x0-v1.dtsi
@@ -44,7 +44,7 @@
 			#address-cells = <1>;
 			#size-cells = <1>;
 
-			uboot: partition@0 {
+			partition@0 {
 				label = "u-boot";
 				reg = <0x0 0x20000>;
 				read-only;
@@ -74,7 +74,7 @@
 				read-only;
 			};
 
-			radio: partition@7f0000 {
+			partition@7f0000 {
 				label = "radio";
 				reg = <0x7f0000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_wavlink_wl-wn530hg4.dts b/target/linux/ramips/dts/mt7620a_wavlink_wl-wn530hg4.dts
index 687b3ced37b4a7..dde6d325857a98 100644
--- a/target/linux/ramips/dts/mt7620a_wavlink_wl-wn530hg4.dts
+++ b/target/linux/ramips/dts/mt7620a_wavlink_wl-wn530hg4.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "wavlink,wl-wn530hg4", "ralink,mt7620a-soc";
@@ -20,17 +21,20 @@
 		compatible = "gpio-leds";
 
 		led_status_blue: status_blue {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
 		};
 
 		status_yellow {
-			label = "yellow:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_YELLOW>;
 			gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
 		};
 
 		status_red {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
 		};
 	};
@@ -71,7 +75,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_wavlink_wl-wn535k1.dts b/target/linux/ramips/dts/mt7620a_wavlink_wl-wn535k1.dts
index 48f1a7f3c0df96..e1ce8e58344960 100644
--- a/target/linux/ramips/dts/mt7620a_wavlink_wl-wn535k1.dts
+++ b/target/linux/ramips/dts/mt7620a_wavlink_wl-wn535k1.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "wavlink,wl-wn535k1", "ralink,mt7620a-soc";
@@ -37,12 +38,14 @@
 		compatible = "gpio-leds";
 
 		led_status_blue: status_blue {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_status_red: status_red {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
 		};
 
@@ -57,7 +60,8 @@
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -92,7 +96,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_wavlink_wl-wn579x3.dts b/target/linux/ramips/dts/mt7620a_wavlink_wl-wn579x3.dts
index b2b762d63a7f75..4ee8de90cd6cf3 100644
--- a/target/linux/ramips/dts/mt7620a_wavlink_wl-wn579x3.dts
+++ b/target/linux/ramips/dts/mt7620a_wavlink_wl-wn579x3.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "wavlink,wl-wn579x3", "ralink,mt7620a-soc";
@@ -50,17 +51,20 @@
 		compatible = "gpio-leds";
 
 		led_wps: wps {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
 		};
 
 		lan {
-			label = "blue:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
 		};
 
 		wan {
-			label = "blue:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
 		};
 
@@ -120,7 +124,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_wevo_air-duo.dts b/target/linux/ramips/dts/mt7620a_wevo_air-duo.dts
index 05e61fe614e34e..39a48a62140e9c 100644
--- a/target/linux/ramips/dts/mt7620a_wevo_air-duo.dts
+++ b/target/linux/ramips/dts/mt7620a_wevo_air-duo.dts
@@ -22,7 +22,6 @@
 		compatible = "gpio-leds";
 
 		led_status: led-0 {
-			label = "blue:status";
 			color = <LED_COLOR_ID_BLUE>;
 			function = LED_FUNCTION_STATUS;
 			gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
@@ -81,7 +80,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_xiaomi_miwifi-mini.dts b/target/linux/ramips/dts/mt7620a_xiaomi_miwifi-mini.dts
index 8ed6b7764dcff3..c0141b196dabbf 100644
--- a/target/linux/ramips/dts/mt7620a_xiaomi_miwifi-mini.dts
+++ b/target/linux/ramips/dts/mt7620a_xiaomi_miwifi-mini.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "xiaomi,miwifi-mini", "ralink,mt7620a-soc";
@@ -23,22 +24,26 @@
 		compatible = "gpio-leds";
 
 		led_blue: blue {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
 		};
 
 		led_yellow: yellow {
-			label = "yellow:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_YELLOW>;
 			gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
 		};
 
 		led_red: red {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
 		};
 
@@ -97,7 +102,7 @@
 				reg = <0x30000 0x10000>;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_youku_yk-l1.dtsi b/target/linux/ramips/dts/mt7620a_youku_yk-l1.dtsi
index fc758a455648d3..2f9920fc4561d7 100644
--- a/target/linux/ramips/dts/mt7620a_youku_yk-l1.dtsi
+++ b/target/linux/ramips/dts/mt7620a_youku_yk-l1.dtsi
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -16,20 +17,23 @@
 		compatible = "gpio-leds";
 
 		led_wlan: wlan {
-			label = "blue:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
 
 		usb {
-			label = "blue:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&ohci_port1>, <&ehci_port1>;
 			linux,default-trigger = "usbport";
 		};
 
 		led_power: power {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -79,7 +83,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_yukai_bocco.dts b/target/linux/ramips/dts/mt7620a_yukai_bocco.dts
index db00c20f4f3554..f4fbf5ffb6a786 100644
--- a/target/linux/ramips/dts/mt7620a_yukai_bocco.dts
+++ b/target/linux/ramips/dts/mt7620a_yukai_bocco.dts
@@ -102,7 +102,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_zbtlink_zbt-ape522ii.dts b/target/linux/ramips/dts/mt7620a_zbtlink_zbt-ape522ii.dts
index e41a9947330a56..8197e6539b539c 100644
--- a/target/linux/ramips/dts/mt7620a_zbtlink_zbt-ape522ii.dts
+++ b/target/linux/ramips/dts/mt7620a_zbtlink_zbt-ape522ii.dts
@@ -79,7 +79,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_zbtlink_zbt-we1026-5g.dtsi b/target/linux/ramips/dts/mt7620a_zbtlink_zbt-we1026-5g.dtsi
index 39c50c7366df56..b5065aa97b69fe 100644
--- a/target/linux/ramips/dts/mt7620a_zbtlink_zbt-we1026-5g.dtsi
+++ b/target/linux/ramips/dts/mt7620a_zbtlink_zbt-we1026-5g.dtsi
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "mt7620a_zbtlink_zbt-we1026.dtsi"
 
 / {
@@ -10,12 +12,14 @@
 		compatible = "gpio-leds";
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
 		};
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
 			trigger-sources = <&ohci_port1>, <&ehci_port1>;
 			linux,default-trigger = "usbport";
diff --git a/target/linux/ramips/dts/mt7620a_zbtlink_zbt-we1026-h.dtsi b/target/linux/ramips/dts/mt7620a_zbtlink_zbt-we1026-h.dtsi
index 09f0ba773c09db..c1aff2f8681115 100644
--- a/target/linux/ramips/dts/mt7620a_zbtlink_zbt-we1026-h.dtsi
+++ b/target/linux/ramips/dts/mt7620a_zbtlink_zbt-we1026-h.dtsi
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "mt7620a_zbtlink_zbt-we1026.dtsi"
 
 / {
@@ -10,17 +12,20 @@
 		compatible = "gpio-leds";
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ramips/dts/mt7620a_zbtlink_zbt-we1026.dtsi b/target/linux/ramips/dts/mt7620a_zbtlink_zbt-we1026.dtsi
index 30d2fba263d3ac..b2cb08473bda81 100644
--- a/target/linux/ramips/dts/mt7620a_zbtlink_zbt-we1026.dtsi
+++ b/target/linux/ramips/dts/mt7620a_zbtlink_zbt-we1026.dtsi
@@ -52,7 +52,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_zbtlink_zbt-we826.dtsi b/target/linux/ramips/dts/mt7620a_zbtlink_zbt-we826.dtsi
index b3032af63f388e..91601f6f8eb2a4 100644
--- a/target/linux/ramips/dts/mt7620a_zbtlink_zbt-we826.dtsi
+++ b/target/linux/ramips/dts/mt7620a_zbtlink_zbt-we826.dtsi
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "zbtlink,zbt-we826", "ralink,mt7620a-soc";
@@ -21,12 +22,14 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
 		};
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
 			trigger-sources = <&ohci_port1>, <&ehci_port1>;
 			linux,default-trigger = "usbport";
@@ -74,7 +77,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_zte_q7.dts b/target/linux/ramips/dts/mt7620a_zte_q7.dts
index 3848f7317e606e..04a655b54df7f4 100644
--- a/target/linux/ramips/dts/mt7620a_zte_q7.dts
+++ b/target/linux/ramips/dts/mt7620a_zte_q7.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "zte,q7", "ralink,mt7620a-soc";
@@ -18,12 +19,14 @@
 		compatible = "gpio-leds";
 
 		statred {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status_blue: statblue {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -68,7 +71,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620a_zyxel_keenetic-viva.dts b/target/linux/ramips/dts/mt7620a_zyxel_keenetic-viva.dts
index abeb4c2a2d1630..e96ca9ace698b8 100644
--- a/target/linux/ramips/dts/mt7620a_zyxel_keenetic-viva.dts
+++ b/target/linux/ramips/dts/mt7620a_zyxel_keenetic-viva.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "zyxel,keenetic-viva", "ralink,mt7620a-soc";
@@ -18,19 +19,22 @@
 		compatible = "gpio-leds";
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
 		};
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&ohci_port1>, <&ehci_port1>;
 			linux,default-trigger = "usbport";
 		};
 
 		power_alert {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
 		};
 
@@ -40,7 +44,8 @@
 		};
 
 		led_power_green: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -111,7 +116,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620n_asus_rt-n12p.dts b/target/linux/ramips/dts/mt7620n_asus_rt-n12p.dts
index 29350a85565791..307f71f6edc3dc 100644
--- a/target/linux/ramips/dts/mt7620n_asus_rt-n12p.dts
+++ b/target/linux/ramips/dts/mt7620n_asus_rt-n12p.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "asus,rt-n12p", "ralink,mt7620n-soc";
@@ -22,17 +23,20 @@
 		compatible = "gpio-leds";
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
 		};
 
@@ -90,7 +94,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620n_asus_rt-n14u.dts b/target/linux/ramips/dts/mt7620n_asus_rt-n14u.dts
index c467ed0dde54ac..89b32572001713 100644
--- a/target/linux/ramips/dts/mt7620n_asus_rt-n14u.dts
+++ b/target/linux/ramips/dts/mt7620n_asus_rt-n14u.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "asus,rt-n14u", "ralink,mt7620n-soc";
@@ -18,24 +19,28 @@
 		compatible = "gpio-leds";
 
 		wan {
-			label = "blue:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
 		};
 
 		lan {
-			label = "blue:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
 		};
 
 		usb {
-			label = "blue:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&ohci_port1>, <&ehci_port1>;
 			linux,default-trigger = "usbport";
 		};
 
 		led_power: power {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
 		};
 
@@ -95,7 +100,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620n_buffalo_wmr-300.dts b/target/linux/ramips/dts/mt7620n_buffalo_wmr-300.dts
index a714960b7f336e..cacb685190d49e 100644
--- a/target/linux/ramips/dts/mt7620n_buffalo_wmr-300.dts
+++ b/target/linux/ramips/dts/mt7620n_buffalo_wmr-300.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "buffalo,wmr-300", "ralink,mt7620n-soc";
@@ -28,7 +29,8 @@
 		};
 
 		led_status: status {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -79,7 +81,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620n_comfast_cf-wr800n.dts b/target/linux/ramips/dts/mt7620n_comfast_cf-wr800n.dts
index 19e968bf948a38..bc35b82033b789 100644
--- a/target/linux/ramips/dts/mt7620n_comfast_cf-wr800n.dts
+++ b/target/linux/ramips/dts/mt7620n_comfast_cf-wr800n.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "comfast,cf-wr800n", "ralink,mt7620n-soc";
@@ -32,7 +33,8 @@
 		};
 
 		led_wps: wps {
-			label = "white:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -85,7 +87,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620n_dlink_dwr-116-a1.dts b/target/linux/ramips/dts/mt7620n_dlink_dwr-116-a1.dts
index 1c1a700630db4e..8ac68fcede20eb 100644
--- a/target/linux/ramips/dts/mt7620n_dlink_dwr-116-a1.dts
+++ b/target/linux/ramips/dts/mt7620n_dlink_dwr-116-a1.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/mtd/partitions/uimage.h>
 
 / {
@@ -35,7 +36,8 @@
 		compatible = "gpio-leds";
 
 		led_status: status {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
 		};
 
@@ -77,7 +79,7 @@
 				reg = <0x10000 0x7e0000>;
 			};
 
-			config: partition@7f0000 {
+			partition@7f0000 {
 				label = "config";
 				reg = <0x7f0000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620n_dlink_dwr-921-c1.dts b/target/linux/ramips/dts/mt7620n_dlink_dwr-921-c1.dts
index 95a93ea4deb0c3..9d8db730f3b4b2 100644
--- a/target/linux/ramips/dts/mt7620n_dlink_dwr-921-c1.dts
+++ b/target/linux/ramips/dts/mt7620n_dlink_dwr-921-c1.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/mtd/partitions/uimage.h>
 
 / {
@@ -38,7 +39,8 @@
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
 		};
 
@@ -119,7 +121,7 @@
 				reg = <0x10000 0xfe0000>;
 			};
 
-			config: partition@ff0000 {
+			partition@ff0000 {
 				label = "config";
 				reg = <0xff0000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620n_dlink_dwr-922-e2.dts b/target/linux/ramips/dts/mt7620n_dlink_dwr-922-e2.dts
index 22bff2c948a94d..1c1c2929cde0d4 100644
--- a/target/linux/ramips/dts/mt7620n_dlink_dwr-922-e2.dts
+++ b/target/linux/ramips/dts/mt7620n_dlink_dwr-922-e2.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/mtd/partitions/uimage.h>
 
 / {
@@ -41,7 +42,8 @@
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
 		};
 
@@ -122,7 +124,7 @@
 				reg = <0x10000 0xfe0000>;
 			};
 
-			config: partition@ff0000 {
+			partition@ff0000 {
 				label = "config";
 				reg = <0xff0000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620n_elecom_wrh-300cr.dts b/target/linux/ramips/dts/mt7620n_elecom_wrh-300cr.dts
index afb14b118895e5..3b3dc2ef51bee7 100644
--- a/target/linux/ramips/dts/mt7620n_elecom_wrh-300cr.dts
+++ b/target/linux/ramips/dts/mt7620n_elecom_wrh-300cr.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "elecom,wrh-300cr", "ralink,mt7620n-soc";
@@ -18,7 +19,8 @@
 		compatible = "gpio-leds";
 
 		led_wps: wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
 		};
 
@@ -28,7 +30,8 @@
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -82,7 +85,7 @@
 				reg = <0x30000 0x10000>;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620n_hootoo_ht-tm05.dts b/target/linux/ramips/dts/mt7620n_hootoo_ht-tm05.dts
index 1c408bcaa1a9b9..e77e439ac4100f 100644
--- a/target/linux/ramips/dts/mt7620n_hootoo_ht-tm05.dts
+++ b/target/linux/ramips/dts/mt7620n_hootoo_ht-tm05.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "mt7620n_sunvalley_filehub.dtsi"
 
 / {
@@ -17,7 +19,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
diff --git a/target/linux/ramips/dts/mt7620n_kimax_u35wf.dts b/target/linux/ramips/dts/mt7620n_kimax_u35wf.dts
index 9296d54d5927af..d882356244b018 100644
--- a/target/linux/ramips/dts/mt7620n_kimax_u35wf.dts
+++ b/target/linux/ramips/dts/mt7620n_kimax_u35wf.dts
@@ -72,7 +72,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620n_kingston_mlw221.dts b/target/linux/ramips/dts/mt7620n_kingston_mlw221.dts
index ce1f0e9f8b864b..5fc4152031528e 100644
--- a/target/linux/ramips/dts/mt7620n_kingston_mlw221.dts
+++ b/target/linux/ramips/dts/mt7620n_kingston_mlw221.dts
@@ -78,7 +78,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620n_kingston_mlwg2.dts b/target/linux/ramips/dts/mt7620n_kingston_mlwg2.dts
index 0293b89bfa329b..caa1739823b407 100644
--- a/target/linux/ramips/dts/mt7620n_kingston_mlwg2.dts
+++ b/target/linux/ramips/dts/mt7620n_kingston_mlwg2.dts
@@ -78,7 +78,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620n_netgear_jwnr2010-v5.dts b/target/linux/ramips/dts/mt7620n_netgear_jwnr2010-v5.dts
index 63cf38dec55e5b..0c4958e9e9c1df 100644
--- a/target/linux/ramips/dts/mt7620n_netgear_jwnr2010-v5.dts
+++ b/target/linux/ramips/dts/mt7620n_netgear_jwnr2010-v5.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "mt7620n_netgear_n300.dtsi"
 
 / {
@@ -18,17 +20,20 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0radio";
 		};
diff --git a/target/linux/ramips/dts/mt7620n_netgear_n300.dtsi b/target/linux/ramips/dts/mt7620n_netgear_n300.dtsi
index 1c2e5174663535..4e83e9d9765f14 100644
--- a/target/linux/ramips/dts/mt7620n_netgear_n300.dtsi
+++ b/target/linux/ramips/dts/mt7620n_netgear_n300.dtsi
@@ -56,7 +56,7 @@
 				read-only;
 			};
 
-			factory: partition@3f0000 {
+			partition@3f0000 {
 				label = "factory";
 				reg = <0x3f0000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620n_netgear_pr2000.dts b/target/linux/ramips/dts/mt7620n_netgear_pr2000.dts
index f06b97498221ac..8f64798527b5fc 100644
--- a/target/linux/ramips/dts/mt7620n_netgear_pr2000.dts
+++ b/target/linux/ramips/dts/mt7620n_netgear_pr2000.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "netgear,pr2000", "ralink,mt7620n-soc";
@@ -28,7 +29,8 @@
 		};
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&ohci_port1>, <&ehci_port1>;
 			linux,default-trigger = "usbport";
@@ -103,7 +105,7 @@
 				reg = <0x40000 0xf20000>;
 			};
 
-			factory: partition@f60000 {
+			partition@f60000 {
 				label = "factory";
 				reg = <0xf60000 0x10000>;
 				read-only;
@@ -119,7 +121,7 @@
 				};
 			};
 
-			board_data: partition@f70000 {
+			partition@f70000 {
 				label = "board_data";
 				reg = <0xf70000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620n_nexx_wt3020.dtsi b/target/linux/ramips/dts/mt7620n_nexx_wt3020.dtsi
index 8903ab5c36ab46..be126d1e2752bf 100644
--- a/target/linux/ramips/dts/mt7620n_nexx_wt3020.dtsi
+++ b/target/linux/ramips/dts/mt7620n_nexx_wt3020.dtsi
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "nexx,wt3020", "ralink,mt7620n-soc";
@@ -28,7 +29,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -59,7 +61,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620n_snr_cpe-w4n-mt.dts b/target/linux/ramips/dts/mt7620n_snr_cpe-w4n-mt.dts
index 25af8d53301477..6aecfa66989913 100644
--- a/target/linux/ramips/dts/mt7620n_snr_cpe-w4n-mt.dts
+++ b/target/linux/ramips/dts/mt7620n_snr_cpe-w4n-mt.dts
@@ -21,7 +21,6 @@
 		compatible = "gpio-leds";
 
 		led_sys: sys {
-			label = "green:sys";
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_STATUS;
 			gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; // GPIO#38
@@ -29,14 +28,12 @@
 		};
 
 		led_wps: wps {
-			label = "green:wps";
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_WPS;
 			gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; // GPIO#39
 		};
 
 		wlan {
-			label = "green:wlan";
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_WLAN;
 			gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; // GPIO#72
@@ -90,7 +87,7 @@
 				reg = <0x30000 0x10000>;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "Factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620n_sunvalley_filehub.dtsi b/target/linux/ramips/dts/mt7620n_sunvalley_filehub.dtsi
index 88958bba141e8d..e14130a2efedab 100644
--- a/target/linux/ramips/dts/mt7620n_sunvalley_filehub.dtsi
+++ b/target/linux/ramips/dts/mt7620n_sunvalley_filehub.dtsi
@@ -79,7 +79,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620n_vonets_var11n-300.dts b/target/linux/ramips/dts/mt7620n_vonets_var11n-300.dts
index 53229ed8656dbb..b6b06bea93aead 100644
--- a/target/linux/ramips/dts/mt7620n_vonets_var11n-300.dts
+++ b/target/linux/ramips/dts/mt7620n_vonets_var11n-300.dts
@@ -59,7 +59,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620n_wrtnode_wrtnode.dts b/target/linux/ramips/dts/mt7620n_wrtnode_wrtnode.dts
index 8e608bba2e4c29..c0accaddf85d45 100644
--- a/target/linux/ramips/dts/mt7620n_wrtnode_wrtnode.dts
+++ b/target/linux/ramips/dts/mt7620n_wrtnode_wrtnode.dts
@@ -1,6 +1,7 @@
 #include "mt7620n.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "wrtnode,wrtnode", "ralink,mt7620n-soc";
@@ -17,7 +18,8 @@
 		compatible = "gpio-leds";
 
 		led_indicator: indicator {
-			label = "blue:indicator";
+			function = LED_FUNCTION_INDICATOR;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -52,7 +54,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620n_zbtlink_zbt-cpe102.dts b/target/linux/ramips/dts/mt7620n_zbtlink_zbt-cpe102.dts
index 1510b19b17d535..8e95ab9f09bdfd 100644
--- a/target/linux/ramips/dts/mt7620n_zbtlink_zbt-cpe102.dts
+++ b/target/linux/ramips/dts/mt7620n_zbtlink_zbt-cpe102.dts
@@ -75,7 +75,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620n_zbtlink_zbt-wa05.dts b/target/linux/ramips/dts/mt7620n_zbtlink_zbt-wa05.dts
index 52c497645b0c13..8dd88549bf83a3 100644
--- a/target/linux/ramips/dts/mt7620n_zbtlink_zbt-wa05.dts
+++ b/target/linux/ramips/dts/mt7620n_zbtlink_zbt-wa05.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "zbtlink,zbt-wa05", "ralink,mt7620n-soc";
@@ -22,12 +23,14 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
 		};
 
 		usb {
-			label = "blue:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
 			trigger-sources = <&ohci_port1>, <&ehci_port1>;
 			linux,default-trigger = "usbport";
@@ -83,7 +86,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620n_zbtlink_zbt-we2026.dts b/target/linux/ramips/dts/mt7620n_zbtlink_zbt-we2026.dts
index 7000447c6ce5e2..6187200e6f44ed 100644
--- a/target/linux/ramips/dts/mt7620n_zbtlink_zbt-we2026.dts
+++ b/target/linux/ramips/dts/mt7620n_zbtlink_zbt-we2026.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "zbtlink,zbt-we2026", "ralink,mt7620n-soc";
@@ -22,12 +23,14 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -76,7 +79,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620n_zbtlink_zbt-wr8305rt.dts b/target/linux/ramips/dts/mt7620n_zbtlink_zbt-wr8305rt.dts
index 20063e2b47d790..137b6f6e0a2ccc 100644
--- a/target/linux/ramips/dts/mt7620n_zbtlink_zbt-wr8305rt.dts
+++ b/target/linux/ramips/dts/mt7620n_zbtlink_zbt-wr8305rt.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "zbtlink,zbt-wr8305rt", "ralink,mt7620n-soc";
@@ -23,7 +24,8 @@
 		};
 
 		lan {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&ohci_port1>, <&ehci_port1>;
 			linux,default-trigger = "usbport";
@@ -79,7 +81,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620n_zyxel_keenetic-lite-iii-a.dts b/target/linux/ramips/dts/mt7620n_zyxel_keenetic-lite-iii-a.dts
index 2241b27673a652..899479781e27ae 100644
--- a/target/linux/ramips/dts/mt7620n_zyxel_keenetic-lite-iii-a.dts
+++ b/target/linux/ramips/dts/mt7620n_zyxel_keenetic-lite-iii-a.dts
@@ -55,14 +55,12 @@
 		compatible = "gpio-leds";
 
 		led_wan: wan {
-			label = "green:wan";
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_STATUS;
 			gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; // #GPIO38
 		};
 
 		wifi {
-			label = "green:wifi";
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_WLAN;
 			gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; // #GPIO72
@@ -107,7 +105,7 @@
 				reg = <0x30000 0x10000>;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "RF-EEPROM";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620n_zyxel_keenetic-omni-ii.dts b/target/linux/ramips/dts/mt7620n_zyxel_keenetic-omni-ii.dts
index 1937c3a14c1f65..dd1d256f41184e 100644
--- a/target/linux/ramips/dts/mt7620n_zyxel_keenetic-omni-ii.dts
+++ b/target/linux/ramips/dts/mt7620n_zyxel_keenetic-omni-ii.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "zyxel,keenetic-omni-ii", "ralink,mt7620n-soc";
@@ -18,12 +19,14 @@
 		compatible = "gpio-leds";
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
 		};
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&ohci_port1>, <&ehci_port1>;
 			linux,default-trigger = "usbport";
@@ -35,7 +38,8 @@
 		};
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -107,7 +111,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7620n_zyxel_keenetic-omni.dts b/target/linux/ramips/dts/mt7620n_zyxel_keenetic-omni.dts
index 8faab1cc6b2049..0ba185b7eb940e 100644
--- a/target/linux/ramips/dts/mt7620n_zyxel_keenetic-omni.dts
+++ b/target/linux/ramips/dts/mt7620n_zyxel_keenetic-omni.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "zyxel,keenetic-omni", "ralink,mt7620n-soc";
@@ -18,12 +19,14 @@
 		compatible = "gpio-leds";
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
 		};
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&ohci_port1>, <&ehci_port1>;
 			linux,default-trigger = "usbport";
@@ -35,7 +38,8 @@
 		};
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -107,7 +111,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_adslr_g7.dts b/target/linux/ramips/dts/mt7621_adslr_g7.dts
index ef3a64e031a23b..6ca9eccd2d788e 100644
--- a/target/linux/ramips/dts/mt7621_adslr_g7.dts
+++ b/target/linux/ramips/dts/mt7621_adslr_g7.dts
@@ -63,7 +63,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_afoundry_ew1200.dts b/target/linux/ramips/dts/mt7621_afoundry_ew1200.dts
index d63ae33311fb96..4f942f160203e9 100644
--- a/target/linux/ramips/dts/mt7621_afoundry_ew1200.dts
+++ b/target/linux/ramips/dts/mt7621_afoundry_ew1200.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "afoundry,ew1200", "mediatek,mt7621-soc";
@@ -33,7 +34,8 @@
 		};
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&xhci_ehci_port1>, <&ehci_port2>;
 			linux,default-trigger = "usbport";
@@ -70,7 +72,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_alfa-network_ax1800rm.dts b/target/linux/ramips/dts/mt7621_alfa-network_ax1800rm.dts
index e07cddefc58044..85fda96ce5c606 100644
--- a/target/linux/ramips/dts/mt7621_alfa-network_ax1800rm.dts
+++ b/target/linux/ramips/dts/mt7621_alfa-network_ax1800rm.dts
@@ -42,42 +42,36 @@
 		compatible = "gpio-leds";
 
 		lan1 {
-			label = "green:lan1";
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_LAN;
 			gpios = <&gpio 3 GPIO_ACTIVE_HIGH>;
 		};
 
 		lan2 {
-			label = "green:lan2";
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_LAN;
 			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
 		};
 
 		lan3 {
-			label = "green:lan3";
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_LAN;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power: power {
-			label = "green:power";
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_POWER;
 			gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
 		};
 
 		wan_green {
-			label = "green:wan";
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_WAN;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 		};
 
 		led_wan_red: wan_red {
-			label = "red:wan";
 			color = <LED_COLOR_ID_RED>;
 			function = LED_FUNCTION_WAN;
 			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
diff --git a/target/linux/ramips/dts/mt7621_alfa-network_quad-e4g.dts b/target/linux/ramips/dts/mt7621_alfa-network_quad-e4g.dts
index 2bc0fad9c58d92..3ffa3ad0c7bfce 100644
--- a/target/linux/ramips/dts/mt7621_alfa-network_quad-e4g.dts
+++ b/target/linux/ramips/dts/mt7621_alfa-network_quad-e4g.dts
@@ -241,7 +241,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_ampedwireless_ally.dtsi b/target/linux/ramips/dts/mt7621_ampedwireless_ally.dtsi
index 35274afbf3acf5..b4c4feacb601be 100644
--- a/target/linux/ramips/dts/mt7621_ampedwireless_ally.dtsi
+++ b/target/linux/ramips/dts/mt7621_ampedwireless_ally.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -40,17 +41,20 @@
 		compatible = "gpio-leds";
 
 		led_status_green: status_green {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_status_red: status_red {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 12 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_status_amber: status_amber {
-			label = "amber:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
 		};
 	};
@@ -106,7 +110,7 @@
 			reg = <0x80000 0x80000>;
 		};
 
-		factory: partition@100000 {
+		partition@100000 {
 			label = "factory";
 			reg = <0x100000 0x40000>;
 			read-only;
diff --git a/target/linux/ramips/dts/mt7621_arcadyan_we420223-99.dts b/target/linux/ramips/dts/mt7621_arcadyan_we420223-99.dts
index fbf276c320e15b..48506907ebf8dc 100644
--- a/target/linux/ramips/dts/mt7621_arcadyan_we420223-99.dts
+++ b/target/linux/ramips/dts/mt7621_arcadyan_we420223-99.dts
@@ -42,7 +42,6 @@
 		compatible = "gpio-leds";
 
 		led_power_green: power_green {
-			label = "green:power";
 			gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_POWER;
@@ -50,48 +49,41 @@
 		};
 
 		led_power_red: power_red {
-			label = "red:power";
 			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
 			color = <LED_COLOR_ID_RED>;
 			function = LED_FUNCTION_FAULT;
 		};
 
 		led_wifi_blue: wifi_blue {
-			label = "blue:wifi";
 			gpios = <&gpio 41 GPIO_ACTIVE_LOW>;
 			color = <LED_COLOR_ID_BLUE>;
 			function = LED_FUNCTION_WLAN;
 		};
 
 		led_wifi_green: wifi_green {
-			label = "green:wifi";
 			gpios = <&gpio 43 GPIO_ACTIVE_LOW>;
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_WLAN;
 		};
 
 		led_wps_red: wps_red {
-			label = "red:wps";
 			gpios = <&gpio 45 GPIO_ACTIVE_LOW>;
 			color = <LED_COLOR_ID_RED>;
 			function = LED_FUNCTION_WPS;
 		};
 
 		led_wps_green: wps_green {
-			label = "green:wps";
 			gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_WPS;
 		};
 
 		led_followme_r: followme_red {
-			label = "red:followme";
 			gpios = <&gpio 47 GPIO_ACTIVE_LOW>;
 			color = <LED_COLOR_ID_RED>;
 		};
 
 		led_followme_g: followme_green {
-			label = "green:followme";
 			gpios = <&gpio 48 GPIO_ACTIVE_LOW>;
 			color = <LED_COLOR_ID_GREEN>;
 		};
@@ -129,7 +121,7 @@
 				reg = <0x30000 0x10000>;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "Factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_arcadyan_wg4xx223.dtsi b/target/linux/ramips/dts/mt7621_arcadyan_wg4xx223.dtsi
index 93570823b3a381..78627b2157ec6d 100644
--- a/target/linux/ramips/dts/mt7621_arcadyan_wg4xx223.dtsi
+++ b/target/linux/ramips/dts/mt7621_arcadyan_wg4xx223.dtsi
@@ -76,7 +76,7 @@
 			reg = <0x100000 0x100000>;
 		};
 
-		factory: partition@200000 {
+		partition@200000 {
 			label = "Factory";
 			reg = <0x200000 0x100000>;
 			read-only;
diff --git a/target/linux/ramips/dts/mt7621_asiarf_ap7621.dtsi b/target/linux/ramips/dts/mt7621_asiarf_ap7621.dtsi
index acb2c81a0d8858..edfdc9b173f037 100644
--- a/target/linux/ramips/dts/mt7621_asiarf_ap7621.dtsi
+++ b/target/linux/ramips/dts/mt7621_asiarf_ap7621.dtsi
@@ -74,7 +74,7 @@
 				reg = <0x38000 0x8000>;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_asus_rp-ac56.dts b/target/linux/ramips/dts/mt7621_asus_rp-ac56.dts
index d9fdb3b675f832..617624f4c2e77b 100644
--- a/target/linux/ramips/dts/mt7621_asus_rp-ac56.dts
+++ b/target/linux/ramips/dts/mt7621_asus_rp-ac56.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "asus,rp-ac56", "mediatek,mt7621-soc";
@@ -53,17 +54,20 @@
 		};
 
 		led_power_white: power_white {
-			label = "white:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 48 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_power_orange: power_orange {
-			label = "orange:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_power_blue: power_blue {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 46 GPIO_ACTIVE_HIGH>;
 		};
 	};
@@ -135,7 +139,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
@@ -165,7 +169,7 @@
 				reg = <0x50000 0xfa0000>;
 			};
 
-			radio: partition@ff0000 {
+			partition@ff0000 {
 				label = "radio";
 				reg = <0xff0000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_asus_rp-ac87.dts b/target/linux/ramips/dts/mt7621_asus_rp-ac87.dts
index 34e64182cf5649..02c19bd1c68eef 100644
--- a/target/linux/ramips/dts/mt7621_asus_rp-ac87.dts
+++ b/target/linux/ramips/dts/mt7621_asus_rp-ac87.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "asus,rp-ac87", "mediatek,mt7621-soc";
@@ -37,7 +38,8 @@
 		compatible = "gpio-leds";
 
 		led_wps: wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
 		};
 
@@ -109,7 +111,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_asus_rt-ac57u-v1.dts b/target/linux/ramips/dts/mt7621_asus_rt-ac57u-v1.dts
index 6790b37d1aefa7..4915f8125e8380 100644
--- a/target/linux/ramips/dts/mt7621_asus_rt-ac57u-v1.dts
+++ b/target/linux/ramips/dts/mt7621_asus_rt-ac57u-v1.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "asus,rt-ac57u-v1", "mediatek,mt7621-soc";
@@ -20,12 +21,14 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 48 GPIO_ACTIVE_LOW>;
 		};
 
 		usb {
-			label = "blue:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 47 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&ehci_port2>;
 			linux,default-trigger = "usbport";
@@ -85,7 +88,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_asus_rt-acx5p.dtsi b/target/linux/ramips/dts/mt7621_asus_rt-acx5p.dtsi
index 7c607f962dbbbe..5bccddec0b6ff4 100644
--- a/target/linux/ramips/dts/mt7621_asus_rt-acx5p.dtsi
+++ b/target/linux/ramips/dts/mt7621_asus_rt-acx5p.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -33,7 +34,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
 		};
 
@@ -79,7 +81,7 @@
 			read-only;
 		};
 
-		factory: partition@1e0000 {
+		partition@1e0000 {
 			label = "factory";
 			reg = <0x1e0000 0x100000>;
 			read-only;
@@ -103,7 +105,7 @@
 			};
 		};
 
-		factory2: partition@2e0000 {
+		partition@2e0000 {
 			label = "factory2";
 			reg = <0x2e0000 0x100000>;
 			read-only;
diff --git a/target/linux/ramips/dts/mt7621_asus_rt-ax53u.dts b/target/linux/ramips/dts/mt7621_asus_rt-ax53u.dts
index c7d0e1e748d3a0..faf58e0187b639 100644
--- a/target/linux/ramips/dts/mt7621_asus_rt-ax53u.dts
+++ b/target/linux/ramips/dts/mt7621_asus_rt-ax53u.dts
@@ -27,14 +27,12 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "blue:power";
 			color = <LED_COLOR_ID_BLUE>;
 			function = LED_FUNCTION_POWER;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 		};
 
 		led_usb {
-			label = "blue:usb";
 			color = <LED_COLOR_ID_BLUE>;
 			function = LED_FUNCTION_USB;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
@@ -94,7 +92,7 @@
 			read-only;
 		};
 
-		factory: partition@1e0000 {
+		partition@1e0000 {
 			label = "factory";
 			reg = <0x1e0000 0x100000>;
 			read-only;
@@ -118,7 +116,7 @@
 			};
 		};
 
-		factory2: partition@2e0000 {
+		partition@2e0000 {
 			label = "factory2";
 			reg = <0x2e0000 0x100000>;
 			read-only;
diff --git a/target/linux/ramips/dts/mt7621_asus_rt-ax54.dts b/target/linux/ramips/dts/mt7621_asus_rt-ax54.dts
index 94825f9de3d95f..7bb375cb298637 100644
--- a/target/linux/ramips/dts/mt7621_asus_rt-ax54.dts
+++ b/target/linux/ramips/dts/mt7621_asus_rt-ax54.dts
@@ -27,7 +27,6 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "blue:power";
 			color = <LED_COLOR_ID_BLUE>;
 			function = LED_FUNCTION_POWER;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
@@ -86,7 +85,7 @@
 			read-only;
 		};
 
-		factory: partition@1e0000 {
+		partition@1e0000 {
 			label = "factory";
 			reg = <0x1e0000 0x100000>;
 			read-only;
@@ -110,7 +109,7 @@
 			};
 		};
 
-		factory2: partition@2e0000 {
+		partition@2e0000 {
 			label = "factory2";
 			reg = <0x2e0000 0x100000>;
 			read-only;
diff --git a/target/linux/ramips/dts/mt7621_asus_rt-n56u-b1.dts b/target/linux/ramips/dts/mt7621_asus_rt-n56u-b1.dts
index cfc8330fe5c55f..b18bd113dad9b4 100644
--- a/target/linux/ramips/dts/mt7621_asus_rt-n56u-b1.dts
+++ b/target/linux/ramips/dts/mt7621_asus_rt-n56u-b1.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "asus,rt-n56u-b1", "mediatek,mt7621-soc";
@@ -25,7 +26,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
 		};
 
@@ -42,17 +44,20 @@
 		};
 
 		wan {
-			label = "blue:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
 		};
 
 		lan {
-			label = "blue:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
 		};
 
 		usb {
-			label = "blue:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&xhci_ehci_port1>, <&ehci_port2>;
 			linux,default-trigger = "usbport";
@@ -104,7 +109,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_beeline_smartbox-giga.dts b/target/linux/ramips/dts/mt7621_beeline_smartbox-giga.dts
index c1bf5c899b0a24..12ff04ed28d299 100644
--- a/target/linux/ramips/dts/mt7621_beeline_smartbox-giga.dts
+++ b/target/linux/ramips/dts/mt7621_beeline_smartbox-giga.dts
@@ -90,7 +90,7 @@
 			sercomm,scpart-id = <1>;
 		};
 
-		factory: partition@200000 {
+		partition@200000 {
 			label = "Factory";
 			reg = <0x200000 0x100000>;
 			sercomm,scpart-id = <2>;
diff --git a/target/linux/ramips/dts/mt7621_beeline_smartbox-turbo-plus.dts b/target/linux/ramips/dts/mt7621_beeline_smartbox-turbo-plus.dts
index 4af425a648c9dd..84ec15b872076d 100644
--- a/target/linux/ramips/dts/mt7621_beeline_smartbox-turbo-plus.dts
+++ b/target/linux/ramips/dts/mt7621_beeline_smartbox-turbo-plus.dts
@@ -96,7 +96,7 @@
 			read-only;
 		};
 
-		factory: partition@200000 {
+		partition@200000 {
 			label = "Factory";
 			reg = <0x200000 0x100000>;
 			sercomm,scpart-id = <2>;
diff --git a/target/linux/ramips/dts/mt7621_belkin_rt1800.dts b/target/linux/ramips/dts/mt7621_belkin_rt1800.dts
index e7acc55e500f4e..25fc335c56a651 100644
--- a/target/linux/ramips/dts/mt7621_belkin_rt1800.dts
+++ b/target/linux/ramips/dts/mt7621_belkin_rt1800.dts
@@ -47,7 +47,8 @@
 		};
 
 		led_power: led-power {
-			label = "white:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
@@ -85,7 +86,7 @@
 			reg = <0x80000 0x80000>;
 		};
 
-		factory: partition@100000 {
+		partition@100000 {
 			label = "Factory";
 			reg = <0x100000 0x80000>;
 			read-only;
diff --git a/target/linux/ramips/dts/mt7621_bolt_arion.dts b/target/linux/ramips/dts/mt7621_bolt_arion.dts
index 83855f9dc898bf..869aba69bf8db5 100644
--- a/target/linux/ramips/dts/mt7621_bolt_arion.dts
+++ b/target/linux/ramips/dts/mt7621_bolt_arion.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "bolt,arion", "mediatek,mt7621-soc";
@@ -21,12 +22,14 @@
 		compatible = "gpio-leds";
 
 		led_wlan_blue: wlan_blue {
-			label = "blue:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 43 GPIO_ACTIVE_LOW>;
 		};
 
 		led_wlan_red: wlan_red {
-			label = "red:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 86 GPIO_ACTIVE_LOW>;
 		};
 
@@ -99,7 +102,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_buffalo_wsr-1166dhp.dts b/target/linux/ramips/dts/mt7621_buffalo_wsr-1166dhp.dts
index f176691aacc8e0..c065997ea1eb19 100644
--- a/target/linux/ramips/dts/mt7621_buffalo_wsr-1166dhp.dts
+++ b/target/linux/ramips/dts/mt7621_buffalo_wsr-1166dhp.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "buffalo,wsr-1166dhp", "mediatek,mt7621-soc";
@@ -43,7 +44,8 @@
 		};
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
 		};
 
@@ -132,7 +134,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_buffalo_wsr-2533dhpl.dts b/target/linux/ramips/dts/mt7621_buffalo_wsr-2533dhpl.dts
index b4ba1519d3df37..66b47d2fa027db 100644
--- a/target/linux/ramips/dts/mt7621_buffalo_wsr-2533dhpl.dts
+++ b/target/linux/ramips/dts/mt7621_buffalo_wsr-2533dhpl.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "buffalo,wsr-2533dhpl", "mediatek,mt7621-soc";
@@ -46,7 +47,8 @@
 		};
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
 		};
 
@@ -130,7 +132,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_buffalo_wsr-600dhp.dts b/target/linux/ramips/dts/mt7621_buffalo_wsr-600dhp.dts
index e1b82816f0cfa4..e3b165c640534f 100644
--- a/target/linux/ramips/dts/mt7621_buffalo_wsr-600dhp.dts
+++ b/target/linux/ramips/dts/mt7621_buffalo_wsr-600dhp.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "buffalo,wsr-600dhp", "mediatek,mt7621-soc";
@@ -18,7 +19,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
 		};
 
@@ -132,7 +134,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_comfast_cf-e390ax.dts b/target/linux/ramips/dts/mt7621_comfast_cf-e390ax.dts
index 5730ca04d31c70..d7facb61a09cc0 100644
--- a/target/linux/ramips/dts/mt7621_comfast_cf-e390ax.dts
+++ b/target/linux/ramips/dts/mt7621_comfast_cf-e390ax.dts
@@ -28,17 +28,20 @@
 		compatible = "gpio-leds";
 
 		led_status_green: status_green {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status_blue: status_blue {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status_red: status_red {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -87,7 +90,7 @@
 				read-only;
 			};
 
-			factory: partition@50000 {
+			partition@50000 {
 				label = "factory";
 				reg = <0x50000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_comfast_cf-ew72-v2.dts b/target/linux/ramips/dts/mt7621_comfast_cf-ew72-v2.dts
index a915a5d79f0f8a..788684163ba277 100644
--- a/target/linux/ramips/dts/mt7621_comfast_cf-ew72-v2.dts
+++ b/target/linux/ramips/dts/mt7621_comfast_cf-ew72-v2.dts
@@ -70,7 +70,8 @@
 		};
 
 		wlan_blue {
-			label = "blue:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -105,7 +106,7 @@
 				read-only;
 			};
 			
-			factory: partition@40000  {
+			partition@40000  {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_cudy_m1800.dts b/target/linux/ramips/dts/mt7621_cudy_m1800.dts
index 2c9ab5cce6a5c1..12f5ce3ec92d3b 100644
--- a/target/linux/ramips/dts/mt7621_cudy_m1800.dts
+++ b/target/linux/ramips/dts/mt7621_cudy_m1800.dts
@@ -113,7 +113,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_cudy_wr1300-v1.dts b/target/linux/ramips/dts/mt7621_cudy_wr1300-v1.dts
index e87209fbb1d866..9d5701a7cca82d 100644
--- a/target/linux/ramips/dts/mt7621_cudy_wr1300-v1.dts
+++ b/target/linux/ramips/dts/mt7621_cudy_wr1300-v1.dts
@@ -3,6 +3,7 @@
 #include "mt7621.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/gpio/gpio.h>
 
 / {
@@ -46,14 +47,16 @@
 		};
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
 			trigger-sources = <&xhci_ehci_port1>, <&ehci_port2>;
 			linux,default-trigger = "usbport";
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -84,7 +87,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
@@ -122,7 +125,7 @@
 				read-only;
 			};
 
-			bdinfo: partition@ff0000 {
+			partition@ff0000 {
 				label = "bdinfo";
 				reg = <0xff0000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_cudy_wr1300-v2v3.dtsi b/target/linux/ramips/dts/mt7621_cudy_wr1300-v2v3.dtsi
index b4c61fb7c66765..55da73dcdab12b 100644
--- a/target/linux/ramips/dts/mt7621_cudy_wr1300-v2v3.dtsi
+++ b/target/linux/ramips/dts/mt7621_cudy_wr1300-v2v3.dtsi
@@ -3,6 +3,7 @@
 #include "mt7621.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/gpio/gpio.h>
 
 / {
@@ -43,7 +44,8 @@
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/mt7621_cudy_wr2100.dts b/target/linux/ramips/dts/mt7621_cudy_wr2100.dts
index afccce15ccdd43..5b21cff130567f 100644
--- a/target/linux/ramips/dts/mt7621_cudy_wr2100.dts
+++ b/target/linux/ramips/dts/mt7621_cudy_wr2100.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "cudy,wr2100", "mediatek,mt7621-soc";
@@ -51,7 +52,8 @@
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 		};
 
@@ -131,7 +133,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
@@ -169,7 +171,7 @@
 				read-only;
 			};
 
-			bdinfo: partition@ff0000 {
+			partition@ff0000 {
 				label = "bdinfo";
 				reg = <0xff0000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_cudy_x6.dtsi b/target/linux/ramips/dts/mt7621_cudy_x6.dtsi
index 8b3baa9f8473cb..81a34e9302eff0 100644
--- a/target/linux/ramips/dts/mt7621_cudy_x6.dtsi
+++ b/target/linux/ramips/dts/mt7621_cudy_x6.dtsi
@@ -75,7 +75,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_d-team_newifi-d2.dts b/target/linux/ramips/dts/mt7621_d-team_newifi-d2.dts
index 82160cff03f20c..9d426fb17df106 100644
--- a/target/linux/ramips/dts/mt7621_d-team_newifi-d2.dts
+++ b/target/linux/ramips/dts/mt7621_d-team_newifi-d2.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "d-team,newifi-d2", "mediatek,mt7621-soc";
@@ -23,12 +24,14 @@
 		compatible = "gpio-leds";
 
 		power-amber {
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_blue: power-blue {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 		};
 
@@ -53,7 +56,8 @@
 		};
 
 		usb {
-			label = "blue:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&xhci_ehci_port1>, <&ehci_port2>;
 			linux,default-trigger = "usbport";
@@ -114,7 +118,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_d-team_pbr-m1.dts b/target/linux/ramips/dts/mt7621_d-team_pbr-m1.dts
index 29c212671cccb8..5a192cacf38fc1 100644
--- a/target/linux/ramips/dts/mt7621_d-team_pbr-m1.dts
+++ b/target/linux/ramips/dts/mt7621_d-team_pbr-m1.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "d-team,pbr-m1", "mediatek,mt7621-soc";
@@ -22,7 +23,8 @@
 		compatible = "gpio-leds";
 
 		power {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 31 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
@@ -128,7 +130,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_dlink_covr-x1860-a1.dts b/target/linux/ramips/dts/mt7621_dlink_covr-x1860-a1.dts
index 7a5fbeeddb564c..90a5c196fc710f 100644
--- a/target/linux/ramips/dts/mt7621_dlink_covr-x1860-a1.dts
+++ b/target/linux/ramips/dts/mt7621_dlink_covr-x1860-a1.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "dlink,covr-x1860-a1", "mediatek,mt7621-soc";
@@ -40,18 +41,21 @@
 		compatible = "gpio-leds";
 
 		status_white: power {
-			label = "white:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
 		};
 
 		status_orange: status_orange {
-			label = "orange:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		status_red: status_red {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -94,7 +98,7 @@
 			read-only;
 		};
 
-		factory: partition@100000 {
+		partition@100000 {
 			label = "factory";
 			reg = <0x100000 0x80000>;
 			read-only;
diff --git a/target/linux/ramips/dts/mt7621_dlink_dap-x1860-a1.dts b/target/linux/ramips/dts/mt7621_dlink_dap-x1860-a1.dts
index 82b7c8070e29dc..0dbf03d35445a0 100644
--- a/target/linux/ramips/dts/mt7621_dlink_dap-x1860-a1.dts
+++ b/target/linux/ramips/dts/mt7621_dlink_dap-x1860-a1.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "dlink,dap-x1860-a1", "mediatek,mt7621-soc";
@@ -41,18 +42,21 @@
 		compatible = "gpio-leds";
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		led_power_red: power_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
 		};
 
 		power_orange {
-			label = "orange:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
 		};
 
@@ -124,7 +128,7 @@
 			read-only;
 		};
 
-		factory: partition@100000 {
+		partition@100000 {
 			label = "factory";
 			reg = <0x100000 0x80000>;
 			read-only;
diff --git a/target/linux/ramips/dts/mt7621_dlink_dir-1935-a1.dts b/target/linux/ramips/dts/mt7621_dlink_dir-1935-a1.dts
index 0ce07141a377e1..60b5b35621ee25 100644
--- a/target/linux/ramips/dts/mt7621_dlink_dir-1935-a1.dts
+++ b/target/linux/ramips/dts/mt7621_dlink_dir-1935-a1.dts
@@ -6,18 +6,4 @@
 / {
 	compatible = "dlink,dir-1935-a1", "mediatek,mt7621-soc";
 	model = "D-Link DIR-1935 A1";
-
-	aliases {
-		label-mac-device = &gmac0;
-	};
-};
-
-&gmac0 {
-	nvmem-cells = <&macaddr_factory_e000>;
-	nvmem-cell-names = "mac-address";
-};
-
-&gmac1 {
-	nvmem-cells = <&macaddr_factory_e006>;
-	nvmem-cell-names = "mac-address";
 };
diff --git a/target/linux/ramips/dts/mt7621_dlink_dir-1960-a1.dts b/target/linux/ramips/dts/mt7621_dlink_dir-1960-a1.dts
index e0a714c9dc6461..13883f9f74041c 100644
--- a/target/linux/ramips/dts/mt7621_dlink_dir-1960-a1.dts
+++ b/target/linux/ramips/dts/mt7621_dlink_dir-1960-a1.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "mt7621_dlink_dir-xx60-a1.dtsi"
 
 / {
@@ -9,7 +11,8 @@
 
 &leds {
 	usb_white {
-		label = "white:usb";
+		function = LED_FUNCTION_USB;
+		color = <LED_COLOR_ID_WHITE>;
 		gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		trigger-sources = <&xhci_ehci_port1>;
 		linux,default-trigger = "usbport";
diff --git a/target/linux/ramips/dts/mt7621_dlink_dir-3060-a1.dts b/target/linux/ramips/dts/mt7621_dlink_dir-3060-a1.dts
index 1cca6f6b57851c..f581095a81d5ac 100644
--- a/target/linux/ramips/dts/mt7621_dlink_dir-3060-a1.dts
+++ b/target/linux/ramips/dts/mt7621_dlink_dir-3060-a1.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "dlink,dir-3060-a1", "mediatek,mt7621-soc";
@@ -37,12 +38,14 @@
 		compatible = "gpio-leds";
 
 		led_power_orange: power_orange {
-			label = "orange:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_white: power_white {
-			label = "white:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
 		};
 
@@ -110,7 +113,7 @@
 			read-only;
 		};
 
-		factory: partition@100000 {
+		partition@100000 {
 			label = "factory";
 			reg = <0x100000 0x40000>;
 			read-only;
diff --git a/target/linux/ramips/dts/mt7621_dlink_dir-853-a1.dts b/target/linux/ramips/dts/mt7621_dlink_dir-853-a1.dts
index 8e5e35945a6469..7e5809ed3a3f01 100644
--- a/target/linux/ramips/dts/mt7621_dlink_dir-853-a1.dts
+++ b/target/linux/ramips/dts/mt7621_dlink_dir-853-a1.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "dlink,dir-853-a1", "mediatek,mt7621-soc";
@@ -54,19 +55,22 @@
 		};
 
 		usb_blue {
-			label = "blue:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&xhci_ehci_port1>;
 			linux,default-trigger = "usbport";
 		};
 
 		led_power_orange: power_orange {
-			label = "orange:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_blue: power_blue {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		};
 
@@ -107,7 +111,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_dlink_dir-853-a3.dts b/target/linux/ramips/dts/mt7621_dlink_dir-853-a3.dts
index 747d1de18a0649..434a6d9f1a506d 100644
--- a/target/linux/ramips/dts/mt7621_dlink_dir-853-a3.dts
+++ b/target/linux/ramips/dts/mt7621_dlink_dir-853-a3.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "dlink,dir-853-a3", "mediatek,mt7621-soc";
@@ -44,12 +45,14 @@
 		compatible = "gpio-leds";
 
 		led_power_orange: power_orange {
-			label = "orange:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_blue: power_blue {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		};
 
@@ -64,7 +67,8 @@
 		};
 
 		usb_blue {
-			label = "blue:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&xhci_ehci_port1>;
 			linux,default-trigger = "usbport";
@@ -104,7 +108,7 @@
 			read-only;
 		};
 
-		factory: partition@100000 {
+		partition@100000 {
 			label = "factory";
 			reg = <0x100000 0x40000>;
 			read-only;
diff --git a/target/linux/ramips/dts/mt7621_dlink_dir-853-r1.dts b/target/linux/ramips/dts/mt7621_dlink_dir-853-r1.dts
index bce0e6996befa2..a3753f37d4315a 100644
--- a/target/linux/ramips/dts/mt7621_dlink_dir-853-r1.dts
+++ b/target/linux/ramips/dts/mt7621_dlink_dir-853-r1.dts
@@ -6,6 +6,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "dlink,dir-853-r1", "mediatek,mt7621-soc";
@@ -24,12 +25,14 @@
 		compatible = "gpio-leds";
 
 		led_power_orange: power_orange {
-			label = "orange:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_blue: power_blue {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		};
 
@@ -44,7 +47,8 @@
 		};
 
 		usb_blue {
-			label = "blue:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&xhci_ehci_port1>;
 			linux,default-trigger = "usbport";
diff --git a/target/linux/ramips/dts/mt7621_dlink_dir-860l-b1.dts b/target/linux/ramips/dts/mt7621_dlink_dir-860l-b1.dts
index 451722743d96ce..8939e523fedbbe 100644
--- a/target/linux/ramips/dts/mt7621_dlink_dir-860l-b1.dts
+++ b/target/linux/ramips/dts/mt7621_dlink_dir-860l-b1.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "dlink,dir-860l-b1", "mediatek,mt7621-soc";
@@ -20,12 +21,14 @@
 		compatible = "gpio-leds";
 
 		power {
-			label = "orange:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_green: power2 {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 		};
 
@@ -82,7 +85,7 @@
 				read-only;
 			};
 
-			radio: partition@34000 {
+			partition@34000 {
 				label = "radio";
 				reg = <0x34000 0x4000>;
 				read-only;
@@ -106,7 +109,7 @@
 				};
 			};
 
-			factory: partition@38000 {
+			partition@38000 {
 				label = "factory";
 				reg = <0x38000 0x8000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_dlink_dir-867-a1.dts b/target/linux/ramips/dts/mt7621_dlink_dir-867-a1.dts
index ab5a110333507b..e02eb9eebf375a 100644
--- a/target/linux/ramips/dts/mt7621_dlink_dir-867-a1.dts
+++ b/target/linux/ramips/dts/mt7621_dlink_dir-867-a1.dts
@@ -6,18 +6,4 @@
 / {
 	compatible = "dlink,dir-867-a1", "mediatek,mt7621-soc";
 	model = "D-Link DIR-867 A1";
-
-	aliases {
-		label-mac-device = &gmac0;
-	};
-};
-
-&gmac0 {
-	nvmem-cells = <&macaddr_factory_e000>;
-	nvmem-cell-names = "mac-address";
-};
-
-&gmac1 {
-	nvmem-cells = <&macaddr_factory_e006>;
-	nvmem-cell-names = "mac-address";
 };
diff --git a/target/linux/ramips/dts/mt7621_dlink_dir-878-a1.dts b/target/linux/ramips/dts/mt7621_dlink_dir-878-a1.dts
index f9ed0ddcefdfd6..1f1d5824f2f0f1 100644
--- a/target/linux/ramips/dts/mt7621_dlink_dir-878-a1.dts
+++ b/target/linux/ramips/dts/mt7621_dlink_dir-878-a1.dts
@@ -6,18 +6,4 @@
 / {
 	compatible = "dlink,dir-878-a1", "mediatek,mt7621-soc";
 	model = "D-Link DIR-878 A1";
-
-	aliases {
-		label-mac-device = &gmac0;
-	};
-};
-
-&gmac0 {
-	nvmem-cells = <&macaddr_factory_e000>;
-	nvmem-cell-names = "mac-address";
-};
-
-&gmac1 {
-	nvmem-cells = <&macaddr_factory_e006>;
-	nvmem-cell-names = "mac-address";
 };
diff --git a/target/linux/ramips/dts/mt7621_dlink_dir-878-r1.dts b/target/linux/ramips/dts/mt7621_dlink_dir-878-r1.dts
index 1a17dddc115bfe..0bacd6569f8e37 100644
--- a/target/linux/ramips/dts/mt7621_dlink_dir-878-r1.dts
+++ b/target/linux/ramips/dts/mt7621_dlink_dir-878-r1.dts
@@ -6,18 +6,4 @@
 / {
 	compatible = "dlink,dir-878-r1", "mediatek,mt7621-soc";
 	model = "D-Link DIR-878 R1";
-
-	aliases {
-		label-mac-device = &gmac0;
-	};
-};
-
-&gmac0 {
-	nvmem-cells = <&macaddr_factory_e000>;
-	nvmem-cell-names = "mac-address";
-};
-
-&gmac1 {
-	nvmem-cells = <&macaddr_factory_e006>;
-	nvmem-cell-names = "mac-address";
 };
diff --git a/target/linux/ramips/dts/mt7621_dlink_dir-882-a1.dts b/target/linux/ramips/dts/mt7621_dlink_dir-882-a1.dts
index 2f45eda02d282a..01739fc258c036 100644
--- a/target/linux/ramips/dts/mt7621_dlink_dir-882-a1.dts
+++ b/target/linux/ramips/dts/mt7621_dlink_dir-882-a1.dts
@@ -6,10 +6,6 @@
 / {
 	compatible = "dlink,dir-882-a1", "mediatek,mt7621-soc";
 	model = "D-Link DIR-882 A1";
-
-	aliases {
-		label-mac-device = &gmac0;
-	};
 };
 
 &leds {
@@ -27,13 +23,3 @@
 		linux,default-trigger = "usbport";
 	};
 };
-
-&gmac0 {
-	nvmem-cells = <&macaddr_factory_e000>;
-	nvmem-cell-names = "mac-address";
-};
-
-&gmac1 {
-	nvmem-cells = <&macaddr_factory_e006>;
-	nvmem-cell-names = "mac-address";
-};
diff --git a/target/linux/ramips/dts/mt7621_dlink_dir-882-r1.dts b/target/linux/ramips/dts/mt7621_dlink_dir-882-r1.dts
index 019ad7edcf30a7..9b0cd8e7be8fae 100644
--- a/target/linux/ramips/dts/mt7621_dlink_dir-882-r1.dts
+++ b/target/linux/ramips/dts/mt7621_dlink_dir-882-r1.dts
@@ -6,10 +6,6 @@
 / {
 	compatible = "dlink,dir-882-r1", "mediatek,mt7621-soc";
 	model = "D-Link DIR-882 R1";
-
-	aliases {
-		label-mac-device = &gmac0;
-	};
 };
 
 &leds {
@@ -27,13 +23,3 @@
 		linux,default-trigger = "usbport";
 	};
 };
-
-&gmac0 {
-	nvmem-cells = <&macaddr_factory_e000>;
-	nvmem-cell-names = "mac-address";
-};
-
-&gmac1 {
-	nvmem-cells = <&macaddr_factory_e006>;
-	nvmem-cell-names = "mac-address";
-};
diff --git a/target/linux/ramips/dts/mt7621_dlink_dir-8xx.dtsi b/target/linux/ramips/dts/mt7621_dlink_dir-8xx.dtsi
index bd8fd6f8a15d64..11d673dc871915 100644
--- a/target/linux/ramips/dts/mt7621_dlink_dir-8xx.dtsi
+++ b/target/linux/ramips/dts/mt7621_dlink_dir-8xx.dtsi
@@ -4,9 +4,11 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
+		label-mac-device = &gmac0;
 		led-boot = &led_power_orange;
 		led-failsafe = &led_power_green;
 		led-running = &led_power_green;
@@ -39,12 +41,14 @@
 		compatible = "gpio-leds";
 
 		led_power_orange: power_orange {
-			label = "orange:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
 		};
 
@@ -68,8 +72,8 @@
 	wifi@0,0 {
 		compatible = "mediatek,mt76";
 		reg = <0x0000 0 0 0 0>;
-		nvmem-cells = <&eeprom_factory_0>;
-		nvmem-cell-names = "eeprom";
+		nvmem-cells = <&eeprom_factory_0>, <&macaddr_factory_e000 1>;
+		nvmem-cell-names = "eeprom", "mac-address";
 		ieee80211-freq-limit = <2400000 2500000>;
 
 		led {
@@ -82,8 +86,8 @@
 	wifi@0,0 {
 		compatible = "mediatek,mt76";
 		reg = <0x0000 0 0 0 0>;
-		nvmem-cells = <&eeprom_factory_8000>;
-		nvmem-cell-names = "eeprom";
+		nvmem-cells = <&eeprom_factory_8000>, <&macaddr_factory_e000 2>;
+		nvmem-cell-names = "eeprom", "mac-address";
 		ieee80211-freq-limit = <5000000 6000000>;
 
 		led {
@@ -92,10 +96,18 @@
 	};
 };
 
+&gmac0 {
+	nvmem-cells = <&macaddr_factory_e000 0>;
+	nvmem-cell-names = "mac-address";
+};
+
 &gmac1 {
 	status = "okay";
 	label = "wan";
 	phy-handle = <&ethphy4>;
+
+	nvmem-cells = <&macaddr_factory_e006 0>;
+	nvmem-cell-names = "mac-address";
 };
 
 &mdio {
diff --git a/target/linux/ramips/dts/mt7621_dlink_dir-xx60-a1.dtsi b/target/linux/ramips/dts/mt7621_dlink_dir-xx60-a1.dtsi
index 6eb3f3cdd9bf7d..7b7228b8c36d6a 100644
--- a/target/linux/ramips/dts/mt7621_dlink_dir-xx60-a1.dtsi
+++ b/target/linux/ramips/dts/mt7621_dlink_dir-xx60-a1.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -34,12 +35,14 @@
 		compatible = "gpio-leds";
 
 		led_power_orange: power_orange {
-			label = "orange:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_white: power_white {
-			label = "white:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
 		};
 
@@ -75,7 +78,7 @@
 			read-only;
 		};
 
-		factory: partition@100000 {
+		partition@100000 {
 			label = "factory";
 			reg = <0x100000 0x40000>;
 			read-only;
@@ -98,10 +101,6 @@
 					reg = <0xe000 0x6>;
 					#nvmem-cell-cells = <1>;
 				};
-
-				macaddr_factory_e006: macaddr@e006 {
-					reg = <0xe006 0x6>;
-				};
 			};
 		};
 
@@ -151,8 +150,8 @@
 	wifi0: wifi@0,0 {
 		compatible = "mediatek,mt76";
 		reg = <0x0000 0 0 0 0>;
-		nvmem-cells = <&macaddr_factory_e000 1>;
-		nvmem-cell-names = "eeprom";
+		nvmem-cells = <&eeprom_factory_0>, <&macaddr_factory_e000 1>;
+		nvmem-cell-names = "eeprom", "mac-address";
 		ieee80211-freq-limit = <2400000 2500000>;
 
 		led {
@@ -165,8 +164,8 @@
 	wifi1: wifi@0,0 {
 		compatible = "mediatek,mt76";
 		reg = <0x0000 0 0 0 0>;
-		nvmem-cells = <&macaddr_factory_e000 2>;
-		nvmem-cell-names = "eeprom";
+		nvmem-cells = <&eeprom_factory_8000>, <&macaddr_factory_e000 2>;
+		nvmem-cell-names = "eeprom", "mac-address";
 		ieee80211-freq-limit = <5000000 6000000>;
 
 		led {
@@ -185,7 +184,7 @@
 	label = "wan";
 	phy-handle = <&ethphy4>;
 
-	nvmem-cells = <&macaddr_factory_e006>;
+	nvmem-cells = <&macaddr_factory_e000 3>;
 	nvmem-cell-names = "mac-address";
 };
 
diff --git a/target/linux/ramips/dts/mt7621_dlink_dxx-1xx0-x1.dtsi b/target/linux/ramips/dts/mt7621_dlink_dxx-1xx0-x1.dtsi
index a933b14925094e..0f25750c5cf5a2 100644
--- a/target/linux/ramips/dts/mt7621_dlink_dxx-1xx0-x1.dtsi
+++ b/target/linux/ramips/dts/mt7621_dlink_dxx-1xx0-x1.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -36,12 +37,14 @@
 		compatible = "gpio-leds";
 
 		led_status_red: status_red {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status_green: status_green {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 		};
 
@@ -92,7 +95,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_dlink_flash-16m-a1.dtsi b/target/linux/ramips/dts/mt7621_dlink_flash-16m-a1.dtsi
index 021c9e17c6581a..96a6b286fe6c72 100644
--- a/target/linux/ramips/dts/mt7621_dlink_flash-16m-a1.dtsi
+++ b/target/linux/ramips/dts/mt7621_dlink_flash-16m-a1.dtsi
@@ -25,7 +25,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x20000>;
 				read-only;
@@ -44,7 +44,9 @@
 					};
 
 					macaddr_factory_e000: macaddr@e000 {
+						compatible = "mac-base";
 						reg = <0xe000 0x6>;
+						#nvmem-cell-cells = <1>;
 					};
 
 					macaddr_factory_e006: macaddr@e006 {
diff --git a/target/linux/ramips/dts/mt7621_dlink_flash-16m-r1.dtsi b/target/linux/ramips/dts/mt7621_dlink_flash-16m-r1.dtsi
index bccd19b12d8e4c..6d77044aa45d6e 100644
--- a/target/linux/ramips/dts/mt7621_dlink_flash-16m-r1.dtsi
+++ b/target/linux/ramips/dts/mt7621_dlink_flash-16m-r1.dtsi
@@ -25,7 +25,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
@@ -50,7 +50,9 @@
 					};
 
 					macaddr_factory_e000: macaddr@e000 {
+						compatible = "mac-base";
 						reg = <0xe000 0x6>;
+						#nvmem-cell-cells = <1>;
 					};
 
 					macaddr_factory_e006: macaddr@e006 {
diff --git a/target/linux/ramips/dts/mt7621_dual-q_h721.dts b/target/linux/ramips/dts/mt7621_dual-q_h721.dts
index 2c35a8839cb637..039072cf503744 100644
--- a/target/linux/ramips/dts/mt7621_dual-q_h721.dts
+++ b/target/linux/ramips/dts/mt7621_dual-q_h721.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "dual-q,h721", "mediatek,mt7621-soc";
@@ -86,7 +87,8 @@
 		};
 
 		led_status: status {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 27 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/mt7621_edimax_re23s.dts b/target/linux/ramips/dts/mt7621_edimax_re23s.dts
index 80a271f6e33d4a..00a746f579bb1d 100644
--- a/target/linux/ramips/dts/mt7621_edimax_re23s.dts
+++ b/target/linux/ramips/dts/mt7621_edimax_re23s.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/mtd/partitions/uimage.h>
 
 / {
@@ -22,7 +23,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 13 GPIO_ACTIVE_HIGH>;
 		};
 
@@ -85,7 +87,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_edimax_rx21s.dtsi b/target/linux/ramips/dts/mt7621_edimax_rx21s.dtsi
index 464e2a74441997..d7309dbdfea768 100644
--- a/target/linux/ramips/dts/mt7621_edimax_rx21s.dtsi
+++ b/target/linux/ramips/dts/mt7621_edimax_rx21s.dtsi
@@ -80,7 +80,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_elecom_wrc-1167ghbk2-s.dts b/target/linux/ramips/dts/mt7621_elecom_wrc-1167ghbk2-s.dts
index 9c0353ae28b737..bbc135ad83a971 100644
--- a/target/linux/ramips/dts/mt7621_elecom_wrc-1167ghbk2-s.dts
+++ b/target/linux/ramips/dts/mt7621_elecom_wrc-1167ghbk2-s.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "elecom,wrc-1167ghbk2-s", "mediatek,mt7621-soc";
@@ -29,22 +30,26 @@
 		};
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
 		};
 
 		power_blue {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
 		};
 
 		wps {
-			label = "red:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
 		};
 
 		power_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
 		};
 	};
@@ -135,7 +140,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_elecom_wrc-2533ghbk.dtsi b/target/linux/ramips/dts/mt7621_elecom_wrc-2533ghbk.dtsi
index 618b07e798ded9..418b0cfa9a7b72 100644
--- a/target/linux/ramips/dts/mt7621_elecom_wrc-2533ghbk.dtsi
+++ b/target/linux/ramips/dts/mt7621_elecom_wrc-2533ghbk.dtsi
@@ -18,21 +18,18 @@
 		compatible = "gpio-leds";
 
 		wps {
-			label = "red:wps";
 			gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_RED>;
 			function = LED_FUNCTION_WPS;
 		};
 
 		led_power: power {
-			label = "white:power";
 			gpios = <&gpio 12 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_WHITE>;
 			function = LED_FUNCTION_POWER;
 		};
 
 		wlan2g {
-			label = "white:wlan2g";
 			gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_WHITE>;
 			function = LED_FUNCTION_WLAN;
@@ -41,7 +38,6 @@
 		};
 
 		wlan5g {
-			label = "white:wlan5g";
 			gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_WHITE>;
 			function = LED_FUNCTION_WLAN;
@@ -99,7 +95,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_elecom_wrc-gs.dtsi b/target/linux/ramips/dts/mt7621_elecom_wrc-gs.dtsi
index 30b8d4e0104c93..dae247f4ceaac8 100644
--- a/target/linux/ramips/dts/mt7621_elecom_wrc-gs.dtsi
+++ b/target/linux/ramips/dts/mt7621_elecom_wrc-gs.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -18,22 +19,26 @@
 		compatible = "gpio-leds";
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
 		};
 
 		power_blue {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
 		};
 
 		wps {
-			label = "red:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
 		};
 
 		power_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
 		};
 	};
diff --git a/target/linux/ramips/dts/mt7621_etisalat_s3.dts b/target/linux/ramips/dts/mt7621_etisalat_s3.dts
index 2581e05a90ea0d..2fb3aedaff3dda 100644
--- a/target/linux/ramips/dts/mt7621_etisalat_s3.dts
+++ b/target/linux/ramips/dts/mt7621_etisalat_s3.dts
@@ -96,7 +96,7 @@
 			read-only;
 		};
 
-		factory: partition@200000 {
+		partition@200000 {
 			label = "Factory";
 			reg = <0x200000 0x100000>;
 			sercomm,scpart-id = <2>;
diff --git a/target/linux/ramips/dts/mt7621_firefly_firewrt.dts b/target/linux/ramips/dts/mt7621_firefly_firewrt.dts
index c2c2acac9f2841..7afec5e5541ca4 100644
--- a/target/linux/ramips/dts/mt7621_firefly_firewrt.dts
+++ b/target/linux/ramips/dts/mt7621_firefly_firewrt.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "firefly,firewrt", "mediatek,mt7621-soc";
@@ -18,7 +19,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -69,7 +71,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_gehua_ghl-r-001.dts b/target/linux/ramips/dts/mt7621_gehua_ghl-r-001.dts
index d224fd388d7fc7..9030c051f1e71b 100644
--- a/target/linux/ramips/dts/mt7621_gehua_ghl-r-001.dts
+++ b/target/linux/ramips/dts/mt7621_gehua_ghl-r-001.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "gehua,ghl-r-001", "mediatek,mt7621-soc";
@@ -18,7 +19,8 @@
 		};
 
 		usb {
-			label = "blue:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&xhci_ehci_port1>, <&ehci_port2>;
 			linux,default-trigger = "usbport";
@@ -67,7 +69,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_glinet_gl-mt1300.dts b/target/linux/ramips/dts/mt7621_glinet_gl-mt1300.dts
index 891fe7c730f26a..849074111be043 100644
--- a/target/linux/ramips/dts/mt7621_glinet_gl-mt1300.dts
+++ b/target/linux/ramips/dts/mt7621_glinet_gl-mt1300.dts
@@ -87,7 +87,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_gnubee_gb-pc1.dts b/target/linux/ramips/dts/mt7621_gnubee_gb-pc1.dts
index 6bdba25b2b4ce6..7ef7201faf7a5a 100644
--- a/target/linux/ramips/dts/mt7621_gnubee_gb-pc1.dts
+++ b/target/linux/ramips/dts/mt7621_gnubee_gb-pc1.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "gnubee,gb-pc1", "mediatek,mt7621-soc";
@@ -28,7 +29,8 @@
 		compatible = "gpio-leds";
 
 		power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "default-on";
 		};
@@ -71,7 +73,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_gnubee_gb-pc2.dts b/target/linux/ramips/dts/mt7621_gnubee_gb-pc2.dts
index 9a2cffeb97cfae..e898046eaf9086 100644
--- a/target/linux/ramips/dts/mt7621_gnubee_gb-pc2.dts
+++ b/target/linux/ramips/dts/mt7621_gnubee_gb-pc2.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "gnubee,gb-pc2", "mediatek,mt7621-soc";
@@ -48,7 +49,8 @@
 		};
 
 		power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "default-on";
 		};
@@ -91,7 +93,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_h3c_tx180x.dtsi b/target/linux/ramips/dts/mt7621_h3c_tx180x.dtsi
index 59b49fbefc8b02..88148c6759a2d2 100644
--- a/target/linux/ramips/dts/mt7621_h3c_tx180x.dtsi
+++ b/target/linux/ramips/dts/mt7621_h3c_tx180x.dtsi
@@ -39,14 +39,12 @@
 		compatible = "gpio-leds";
 
 		led_status_amber: led-0 {
-			label = "amber:status";
 			color = <LED_COLOR_ID_AMBER>;
 			function = LED_FUNCTION_STATUS;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status_green: led-1 {
-			label = "green:status";
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_STATUS;
 			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
@@ -96,7 +94,7 @@
 			read-only;
 		};
 
-		factory: partition@180000 {
+		partition@180000 {
 			label = "factory";
 			reg = <0x0180000 0x0080000>;
 			read-only;
diff --git a/target/linux/ramips/dts/mt7621_haier-sim_wr1800k.dtsi b/target/linux/ramips/dts/mt7621_haier-sim_wr1800k.dtsi
index 6549abaec95697..53c59123979d52 100644
--- a/target/linux/ramips/dts/mt7621_haier-sim_wr1800k.dtsi
+++ b/target/linux/ramips/dts/mt7621_haier-sim_wr1800k.dtsi
@@ -40,21 +40,18 @@
 		compatible = "gpio-leds";
 
 		led_status_blue: led-0 {
-			label = "blue:status";
 			color = <LED_COLOR_ID_BLUE>;
 			function = LED_FUNCTION_STATUS;
 			gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status_green: led-1 {
-			label = "green:status";
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_STATUS;
 			gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status_red: led-2 {
-			label = "red:status";
 			color = <LED_COLOR_ID_RED>;
 			function = LED_FUNCTION_STATUS;
 			gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
@@ -101,7 +98,7 @@
 			reg = <0x0080000 0x0080000>;
 		};
 
-		factory: partition@100000 {
+		partition@100000 {
 			label = "factory";
 			reg = <0x0100000 0x0080000>;
 			read-only;
diff --git a/target/linux/ramips/dts/mt7621_hanyang_hyc-g920.dts b/target/linux/ramips/dts/mt7621_hanyang_hyc-g920.dts
index 5737c0ce68f126..432aa5abd2083c 100644
--- a/target/linux/ramips/dts/mt7621_hanyang_hyc-g920.dts
+++ b/target/linux/ramips/dts/mt7621_hanyang_hyc-g920.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "hanyang,hyc-g920", "mediatek,mt7621-soc";
@@ -25,12 +26,14 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
 		};
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&ehci_port2>;
 			linux,default-trigger = "usbport";
@@ -74,7 +77,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_hilink_hlk-7621a-evb.dts b/target/linux/ramips/dts/mt7621_hilink_hlk-7621a-evb.dts
index 41ed5088c0ab7e..cae9f717b1eaf0 100644
--- a/target/linux/ramips/dts/mt7621_hilink_hlk-7621a-evb.dts
+++ b/target/linux/ramips/dts/mt7621_hilink_hlk-7621a-evb.dts
@@ -46,7 +46,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_hiwifi_hc5962.dts b/target/linux/ramips/dts/mt7621_hiwifi_hc5962.dts
index a21a6a455b3ad5..1bf66401378678 100644
--- a/target/linux/ramips/dts/mt7621_hiwifi_hc5962.dts
+++ b/target/linux/ramips/dts/mt7621_hiwifi_hc5962.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "hiwifi,hc5962", "mediatek,mt7621-soc";
@@ -22,7 +23,8 @@
 		compatible = "gpio-leds";
 
 		led_status: status {
-			label = "white:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
 		};
 
@@ -80,7 +82,7 @@
 			read-only;
 		};
 
-		factory: partition@100000 {
+		partition@100000 {
 			label = "factory";
 			reg = <0x100000 0x40000>;
 			read-only;
diff --git a/target/linux/ramips/dts/mt7621_huasifei_ws1208v2.dts b/target/linux/ramips/dts/mt7621_huasifei_ws1208v2.dts
index 9b9a9831087731..a7610070de21c3 100644
--- a/target/linux/ramips/dts/mt7621_huasifei_ws1208v2.dts
+++ b/target/linux/ramips/dts/mt7621_huasifei_ws1208v2.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "huasifei,ws1208v2", "mediatek,mt7621-soc";
@@ -33,7 +34,8 @@
 		compatible = "gpio-leds";
 
 		led_status: led-status {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
 		};
 
@@ -55,7 +57,8 @@
 		};
 
 		led-usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 11 GPIO_ACTIVE_HIGH>;
 			trigger-sources = <&xhci_ehci_port1>;
 			linux,default-trigger = "usbport";
@@ -92,7 +95,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_humax_e10.dts b/target/linux/ramips/dts/mt7621_humax_e10.dts
index be5f23ca7d6e6a..dfa91ad43a72e3 100644
--- a/target/linux/ramips/dts/mt7621_humax_e10.dts
+++ b/target/linux/ramips/dts/mt7621_humax_e10.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/mtd/partitions/uimage.h>
 
 / {
@@ -32,7 +33,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 6 GPIO_ACTIVE_HIGH>;
 		};
 
@@ -42,12 +44,14 @@
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 12 GPIO_ACTIVE_HIGH>;
 		};
 	};
@@ -88,7 +92,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x30000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_iodata_wn-ax1167gr.dts b/target/linux/ramips/dts/mt7621_iodata_wn-ax1167gr.dts
index b46ba87f39407d..4f84302417622c 100644
--- a/target/linux/ramips/dts/mt7621_iodata_wn-ax1167gr.dts
+++ b/target/linux/ramips/dts/mt7621_iodata_wn-ax1167gr.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "iodata,wn-ax1167gr", "mediatek,mt7621-soc";
@@ -22,12 +23,14 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -88,7 +91,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
@@ -110,7 +113,7 @@
 				};
 			};
 
-			iNIC_rf: partition@50000 {
+			partition@50000 {
 				label = "iNIC_rf";
 				reg = <0x50000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_iodata_wn-deax1800gr.dts b/target/linux/ramips/dts/mt7621_iodata_wn-deax1800gr.dts
index c21f456a745056..4543f45a9fee40 100644
--- a/target/linux/ramips/dts/mt7621_iodata_wn-deax1800gr.dts
+++ b/target/linux/ramips/dts/mt7621_iodata_wn-deax1800gr.dts
@@ -25,28 +25,24 @@
 		compatible = "gpio-leds";
 
 		led_status_green: led-0 {
-			label = "green:status";
 			gpios = <&gpio 3 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_STATUS;
 		};
 
 		led_status_red: led-1 {
-			label = "red:status";
 			gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_RED>;
 			function = LED_FUNCTION_STATUS;
 		};
 
 		led-2 {
-			label = "green:wps_wifi";
 			gpios = <&gpio 13 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_WPS;
 		};
 
 		led-3 {
-			label = "green:power";
 			gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_POWER;
@@ -54,14 +50,12 @@
 		};
 
 		led-4 {
-			label = "green:router";
 			gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_INDICATOR;
 		};
 
 		led-5 {
-			label = "green:internet";
 			gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_WAN;
diff --git a/target/linux/ramips/dts/mt7621_iodata_wn-dx1200gr.dts b/target/linux/ramips/dts/mt7621_iodata_wn-dx1200gr.dts
index 9680aadfbbf970..9de7297405d9e6 100644
--- a/target/linux/ramips/dts/mt7621_iodata_wn-dx1200gr.dts
+++ b/target/linux/ramips/dts/mt7621_iodata_wn-dx1200gr.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "iodata,wn-dx1200gr", "mediatek,mt7621-soc";
@@ -21,12 +22,14 @@
 		compatible = "gpio-leds";
 
 		wps {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 9 GPIO_ACTIVE_HIGH>;
 		};
 	};
@@ -80,7 +83,7 @@
 			read-only;
 		};
 
-		factory: partition@200000 {
+		partition@200000 {
 			label = "factory";
 			reg = <0x200000 0x200000>;
 
diff --git a/target/linux/ramips/dts/mt7621_iodata_wn-gx300gr.dts b/target/linux/ramips/dts/mt7621_iodata_wn-gx300gr.dts
index 6bd5e733f4a6fd..b055afc3adb927 100644
--- a/target/linux/ramips/dts/mt7621_iodata_wn-gx300gr.dts
+++ b/target/linux/ramips/dts/mt7621_iodata_wn-gx300gr.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "iodata,wn-gx300gr", "mediatek,mt7621-soc";
@@ -22,12 +23,14 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -88,7 +91,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_iodata_wn-xx-xr.dtsi b/target/linux/ramips/dts/mt7621_iodata_wn-xx-xr.dtsi
index 5ed92cf0e7dc6e..b3063a333edc19 100644
--- a/target/linux/ramips/dts/mt7621_iodata_wn-xx-xr.dtsi
+++ b/target/linux/ramips/dts/mt7621_iodata_wn-xx-xr.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -18,12 +19,14 @@
 		compatible = "gpio-leds";
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 9 GPIO_ACTIVE_HIGH>;
 		};
 	};
@@ -77,7 +80,7 @@
 			read-only;
 		};
 
-		factory: partition@200000 {
+		partition@200000 {
 			label = "factory";
 			reg = <0x0200000 0x0100000>;
 
diff --git a/target/linux/ramips/dts/mt7621_iodata_wnpr2600g.dts b/target/linux/ramips/dts/mt7621_iodata_wnpr2600g.dts
index 1c46f57e584b2d..790668cc410d64 100644
--- a/target/linux/ramips/dts/mt7621_iodata_wnpr2600g.dts
+++ b/target/linux/ramips/dts/mt7621_iodata_wnpr2600g.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "iodata,wnpr2600g", "mediatek,mt7621-soc";
@@ -20,7 +21,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
 			default-state = "on";
 		};
@@ -92,7 +94,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x040000 0x010000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_iptime_a3002mesh.dts b/target/linux/ramips/dts/mt7621_iptime_a3002mesh.dts
index 05346a10d4a7d5..e8c7f12d01efa1 100644
--- a/target/linux/ramips/dts/mt7621_iptime_a3002mesh.dts
+++ b/target/linux/ramips/dts/mt7621_iptime_a3002mesh.dts
@@ -21,7 +21,6 @@
 		compatible = "gpio-leds";
 
 		led_cpu: led-0 {
-			label = "amber:cpu";
 			color = <LED_COLOR_ID_AMBER>;
 			function = LED_FUNCTION_CPU;
 			gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
@@ -92,7 +91,7 @@
 				read-only;
 			};
 
-			factory: partition@30000 {
+			partition@30000 {
 				label = "factory";
 				reg = <0x30000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_iptime_a3004ns-dual.dts b/target/linux/ramips/dts/mt7621_iptime_a3004ns-dual.dts
index 3bf0600e5fec7d..6990d31e391903 100644
--- a/target/linux/ramips/dts/mt7621_iptime_a3004ns-dual.dts
+++ b/target/linux/ramips/dts/mt7621_iptime_a3004ns-dual.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "iptime,a3004ns-dual", "mediatek,mt7621-soc";
@@ -20,12 +21,14 @@
 		compatible = "gpio-leds";
 
 		led_cpu: cpu {
-			label = "blue:cpu";
+			function = LED_FUNCTION_CPU;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
 		};
 
 		usb {
-			label = "blue:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&xhci_ehci_port1>;
 			linux,default-trigger = "usbport";
@@ -62,7 +65,7 @@
 			#address-cells = <1>;
 			#size-cells = <1>;
 
-			uboot: partition@0 {
+			partition@0 {
 				label = "u-boot";
 				reg = <0x0 0x20000>;
 				read-only;
@@ -88,7 +91,7 @@
 				read-only;
 			};
 
-			factory: partition@30000 {
+			partition@30000 {
 				label = "factory";
 				reg = <0x30000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_iptime_a3004t.dts b/target/linux/ramips/dts/mt7621_iptime_a3004t.dts
index 2394a343c2464e..a96e89b3f30daf 100644
--- a/target/linux/ramips/dts/mt7621_iptime_a3004t.dts
+++ b/target/linux/ramips/dts/mt7621_iptime_a3004t.dts
@@ -21,7 +21,6 @@
 		compatible = "gpio-leds";
 
 		led_cpu: led-0 {
-			label = "amber:cpu";
 			color = <LED_COLOR_ID_AMBER>;
 			function = LED_FUNCTION_CPU;
 			gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
@@ -75,7 +74,7 @@
 			read-only;
 		};
 
-		factory: partition@a0000 {
+		partition@a0000 {
 			label = "factory";
 			reg = <0xa0000 0x20000>;
 			read-only;
diff --git a/target/linux/ramips/dts/mt7621_iptime_a6004ns-m.dtsi b/target/linux/ramips/dts/mt7621_iptime_a6004ns-m.dtsi
index ef58382ab61cd6..848891056a3181 100644
--- a/target/linux/ramips/dts/mt7621_iptime_a6004ns-m.dtsi
+++ b/target/linux/ramips/dts/mt7621_iptime_a6004ns-m.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -18,7 +19,8 @@
 		compatible = "gpio-leds";
 
 		usb {
-			label = "blue:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&xhci_ehci_port1>;
 			linux,default-trigger = "usbport";
@@ -37,7 +39,8 @@
 		};
 
 		led_cpu: cpu {
-			label = "blue:cpu";
+			function = LED_FUNCTION_CPU;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -73,7 +76,7 @@
 			#address-cells = <1>;
 			#size-cells = <1>;
 
-			uboot: partition@0 {
+			partition@0 {
 				label = "u-boot";
 				reg = <0x0 0x20000>;
 				read-only;
@@ -99,7 +102,7 @@
 				read-only;
 			};
 
-			factory: partition@30000 {
+			partition@30000 {
 				label = "factory";
 				reg = <0x30000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_iptime_a8004t.dts b/target/linux/ramips/dts/mt7621_iptime_a8004t.dts
index 7be11315c540e9..249904da6a37e6 100644
--- a/target/linux/ramips/dts/mt7621_iptime_a8004t.dts
+++ b/target/linux/ramips/dts/mt7621_iptime_a8004t.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "iptime,a8004t", "mediatek,mt7621-soc";
@@ -20,7 +21,8 @@
 		compatible = "gpio-leds";
 
 		led_cpu: cpu {
-			label = "orange:cpu";
+			function = LED_FUNCTION_CPU;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
 		};
 
@@ -67,7 +69,7 @@
 			#address-cells = <1>;
 			#size-cells = <1>;
 
-			uboot: partition@0 {
+			partition@0 {
 				label = "u-boot";
 				reg = <0x0 0x20000>;
 				read-only;
@@ -93,7 +95,7 @@
 				read-only;
 			};
 
-			factory: partition@30000 {
+			partition@30000 {
 				label = "factory";
 				reg = <0x30000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_iptime_ax2004m.dts b/target/linux/ramips/dts/mt7621_iptime_ax2004m.dts
index a0df60234e743f..51be0d49391555 100644
--- a/target/linux/ramips/dts/mt7621_iptime_ax2004m.dts
+++ b/target/linux/ramips/dts/mt7621_iptime_ax2004m.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "iptime,ax2004m", "mediatek,mt7621-soc";
@@ -24,7 +25,8 @@
 		compatible = "gpio-leds";
 
 		led_cpu: cpu {
-			label = "amber:cpu";
+			function = LED_FUNCTION_CPU;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
 		};
 
@@ -72,7 +74,7 @@
 			read-only;
 		};
 
-		factory: partition@100000 {
+		partition@100000 {
 			label = "factory";
 			reg = <0x100000 0x80000>;
 			read-only;
diff --git a/target/linux/ramips/dts/mt7621_iptime_t5004.dts b/target/linux/ramips/dts/mt7621_iptime_t5004.dts
index ee82ffbd85742d..bba039a63ccdfc 100644
--- a/target/linux/ramips/dts/mt7621_iptime_t5004.dts
+++ b/target/linux/ramips/dts/mt7621_iptime_t5004.dts
@@ -21,7 +21,6 @@
 		compatible = "gpio-leds";
 
 		led_cpu: led-0 {
-			label = "blue:cpu";
 			color = <LED_COLOR_ID_BLUE>;
 			function = LED_FUNCTION_CPU;
 			gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
diff --git a/target/linux/ramips/dts/mt7621_jcg_jhr-ac876m.dts b/target/linux/ramips/dts/mt7621_jcg_jhr-ac876m.dts
index fd9bd66bf8c74b..05980caa6f448f 100644
--- a/target/linux/ramips/dts/mt7621_jcg_jhr-ac876m.dts
+++ b/target/linux/ramips/dts/mt7621_jcg_jhr-ac876m.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "jcg,jhr-ac876m", "mediatek,mt7621-soc";
@@ -35,7 +36,8 @@
 		};
 
 		led_wps: wps {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -83,7 +85,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_jcg_q20.dts b/target/linux/ramips/dts/mt7621_jcg_q20.dts
index 349773e22cd906..49f51ded7fb28a 100644
--- a/target/linux/ramips/dts/mt7621_jcg_q20.dts
+++ b/target/linux/ramips/dts/mt7621_jcg_q20.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "jcg,q20", "mediatek,mt7621-soc";
@@ -25,12 +26,14 @@
 		compatible = "gpio-leds";
 
 		led_status_red: status_red {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_status_blue: status_blue {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -87,7 +90,7 @@
 			reg = <0x80000 0x80000>;
 		};
 
-		factory: partition@100000 {
+		partition@100000 {
 			label = "Factory";
 			reg = <0x100000 0x80000>;
 			read-only;
diff --git a/target/linux/ramips/dts/mt7621_jcg_y2.dts b/target/linux/ramips/dts/mt7621_jcg_y2.dts
index 2cec1af23e2033..54141cc2a29256 100644
--- a/target/linux/ramips/dts/mt7621_jcg_y2.dts
+++ b/target/linux/ramips/dts/mt7621_jcg_y2.dts
@@ -61,7 +61,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_keenetic_kn-3010.dts b/target/linux/ramips/dts/mt7621_keenetic_kn-3010.dts
index 264c908c45b61b..35d09832f2b857 100644
--- a/target/linux/ramips/dts/mt7621_keenetic_kn-3010.dts
+++ b/target/linux/ramips/dts/mt7621_keenetic_kn-3010.dts
@@ -3,6 +3,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "keenetic,kn-3010", "mediatek,mt7621-soc";
@@ -24,7 +25,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 45 GPIO_ACTIVE_HIGH>;
 		};
 
@@ -105,7 +107,7 @@
 		reg = <0>;
 		spi-max-frequency = <31000000>;
 
-		partitions: partitions {
+		partitions {
 			compatible = "fixed-partitions";
 			#address-cells = <1>;
 			#size-cells = <1>;
@@ -122,7 +124,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "rf-eeprom";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_lenovo_newifi-d1.dts b/target/linux/ramips/dts/mt7621_lenovo_newifi-d1.dts
index dd8d22445429b3..03237699901b1f 100644
--- a/target/linux/ramips/dts/mt7621_lenovo_newifi-d1.dts
+++ b/target/linux/ramips/dts/mt7621_lenovo_newifi-d1.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "lenovo,newifi-d1", "mediatek,mt7621-soc";
@@ -23,17 +24,20 @@
 		compatible = "gpio-leds";
 
 		status-red {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		};
 
 		status-green {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 		};
 
 		led_blue: status-blue {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
@@ -103,7 +107,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_linksys_e5600.dts b/target/linux/ramips/dts/mt7621_linksys_e5600.dts
index 3f23aa69a4325d..a059fd0698ac1f 100644
--- a/target/linux/ramips/dts/mt7621_linksys_e5600.dts
+++ b/target/linux/ramips/dts/mt7621_linksys_e5600.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "linksys,e5600", "mediatek,mt7621-soc";
@@ -40,23 +41,27 @@
 		compatible = "gpio-leds";
 
 		wps {
-			label = "amber:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_power: power {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
 			default-state = "on";
 		};
 
 		wan_amber {
-			label = "amber:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 13 GPIO_ACTIVE_HIGH>;
 		};
 
 		wan_blue {
-			label = "blue:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
 		};
 	};
@@ -82,7 +87,7 @@
 			read-only;
 		};
 
-		factory: partition@c0000 {
+		partition@c0000 {
 			label = "factory";
 			reg = <0xc0000 0x40000>;
 			read-only;
diff --git a/target/linux/ramips/dts/mt7621_linksys_e7350.dts b/target/linux/ramips/dts/mt7621_linksys_e7350.dts
index 2bce2d75901922..77c123720fe17f 100644
--- a/target/linux/ramips/dts/mt7621_linksys_e7350.dts
+++ b/target/linux/ramips/dts/mt7621_linksys_e7350.dts
@@ -47,7 +47,8 @@
 		};
 
 		led_power: led-power {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
@@ -79,7 +80,7 @@
 			reg = <0x80000 0x80000>;
 		};
 
-		factory: partition@100000 {
+		partition@100000 {
 			label = "Factory";
 			reg = <0x100000 0x80000>;
 			read-only;
diff --git a/target/linux/ramips/dts/mt7621_linksys_ea7xxx.dtsi b/target/linux/ramips/dts/mt7621_linksys_ea7xxx.dtsi
index 4980b4fe9b4a77..5804f215918ac0 100644
--- a/target/linux/ramips/dts/mt7621_linksys_ea7xxx.dtsi
+++ b/target/linux/ramips/dts/mt7621_linksys_ea7xxx.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -37,7 +38,8 @@
 		compatible = "gpio-leds";
 
 		wan_green {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
 		};
 
@@ -62,12 +64,14 @@
 		};
 
 		led_power: power {
-			label = "white:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
 		};
 	};
@@ -97,7 +101,7 @@
 			reg = <0x80000 0x40000>;
 		};
 
-		factory: partition@c0000 {
+		partition@c0000 {
 			label = "factory";
 			reg = <0xc0000 0x40000>;
 			read-only;
diff --git a/target/linux/ramips/dts/mt7621_linksys_re6500.dts b/target/linux/ramips/dts/mt7621_linksys_re6500.dts
index 3a682245268551..d269899980976e 100644
--- a/target/linux/ramips/dts/mt7621_linksys_re6500.dts
+++ b/target/linux/ramips/dts/mt7621_linksys_re6500.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "linksys,re6500", "mediatek,mt7621-soc";
@@ -23,7 +24,8 @@
 		};
 
 		led_power: power {
-			label = "white:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 9 GPIO_ACTIVE_HIGH>;
 		};
 	};
@@ -70,7 +72,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_linksys_re7000.dts b/target/linux/ramips/dts/mt7621_linksys_re7000.dts
index 9b9c84a048762f..c016f5753b266d 100644
--- a/target/linux/ramips/dts/mt7621_linksys_re7000.dts
+++ b/target/linux/ramips/dts/mt7621_linksys_re7000.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "linksys,re7000", "mediatek,mt7621-soc";
@@ -26,12 +27,14 @@
 		};
 
 		wps {
-			label = "orange:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
 		};
 	};
@@ -83,7 +86,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_mediatek_ap-mt7621a-v60.dts b/target/linux/ramips/dts/mt7621_mediatek_ap-mt7621a-v60.dts
index 8e2d866b3b913b..aaa75b057320da 100644
--- a/target/linux/ramips/dts/mt7621_mediatek_ap-mt7621a-v60.dts
+++ b/target/linux/ramips/dts/mt7621_mediatek_ap-mt7621a-v60.dts
@@ -93,7 +93,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_mercusys_mr70x-v1.dts b/target/linux/ramips/dts/mt7621_mercusys_mr70x-v1.dts
index 9004e5f0fde845..fb14bd7829fb08 100644
--- a/target/linux/ramips/dts/mt7621_mercusys_mr70x-v1.dts
+++ b/target/linux/ramips/dts/mt7621_mercusys_mr70x-v1.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "mercusys,mr70x-v1", "mediatek,mt7621-soc";
@@ -35,12 +36,14 @@
 		compatible = "gpio-leds";
 
 		led_power_green: power-green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_orange: power-orange {
-			label = "orange:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -71,7 +74,7 @@
 				reg = <0x040000 0xf60000>;
 			};
 
-			config: partition@fa0000 {
+			partition@fa0000 {
 				label = "config";
 				reg = <0xfa0000 0x010000>;
 				read-only;
@@ -95,7 +98,7 @@
 				read-only;
 			};
 
-			radio: partition@ff0000 {
+			partition@ff0000 {
 				label = "radio";
 				reg = <0xff0000 0x010000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_mqmaker_witi.dts b/target/linux/ramips/dts/mt7621_mqmaker_witi.dts
index 0052040f369321..0fbf51169cb6a9 100644
--- a/target/linux/ramips/dts/mt7621_mqmaker_witi.dts
+++ b/target/linux/ramips/dts/mt7621_mqmaker_witi.dts
@@ -57,7 +57,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 
diff --git a/target/linux/ramips/dts/mt7621_mtc_wr1201.dts b/target/linux/ramips/dts/mt7621_mtc_wr1201.dts
index 43b021fa13ae81..31f3eb86570bd8 100644
--- a/target/linux/ramips/dts/mt7621_mtc_wr1201.dts
+++ b/target/linux/ramips/dts/mt7621_mtc_wr1201.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "mtc,wr1201", "mediatek,mt7621-soc";
@@ -19,12 +20,14 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 24 GPIO_ACTIVE_LOW>;
 		};
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&xhci_ehci_port1>, <&ehci_port2>;
 			linux,default-trigger = "usbport";
@@ -36,7 +39,8 @@
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -77,7 +81,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_netgear_eax12.dts b/target/linux/ramips/dts/mt7621_netgear_eax12.dts
index d0e0eb247ad946..e467783ad1bd79 100644
--- a/target/linux/ramips/dts/mt7621_netgear_eax12.dts
+++ b/target/linux/ramips/dts/mt7621_netgear_eax12.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "netgear,eax12", "mediatek,mt7621-soc";
@@ -40,12 +41,14 @@
 		compatible = "gpio-leds";
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_red: power_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
 		};
 
@@ -70,7 +73,8 @@
 		};
 
 		wps_green {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
 		};
 
@@ -106,7 +110,7 @@
 			read-only;
 		};
 
-		factory: partition@100000 {
+		partition@100000 {
 			label = "Factory";
 			reg = <0x100000 0x80000>;
 			read-only;
diff --git a/target/linux/ramips/dts/mt7621_netgear_ex6150.dts b/target/linux/ramips/dts/mt7621_netgear_ex6150.dts
index 41e603c16058b3..7ad421d1a0beac 100644
--- a/target/linux/ramips/dts/mt7621_netgear_ex6150.dts
+++ b/target/linux/ramips/dts/mt7621_netgear_ex6150.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "netgear,ex6150", "mediatek,mt7621-soc";
@@ -20,17 +21,20 @@
 		compatible = "gpio-leds";
 
 		power_amber: power_amber {
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 		};
 
 		power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
 		};
 
@@ -117,7 +121,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_netgear_r6220.dts b/target/linux/ramips/dts/mt7621_netgear_r6220.dts
index 132210cb0ce9bd..807b9b11e9ab07 100644
--- a/target/linux/ramips/dts/mt7621_netgear_r6220.dts
+++ b/target/linux/ramips/dts/mt7621_netgear_r6220.dts
@@ -41,7 +41,7 @@
 			reg = <0x600000 0x1c00000>;
 		};
 
-		factory: partition@2e00000 {
+		partition@2e00000 {
 			label = "factory";
 			reg = <0x2e00000 0x100000>;
 			read-only;
diff --git a/target/linux/ramips/dts/mt7621_netgear_sercomm_ayx.dtsi b/target/linux/ramips/dts/mt7621_netgear_sercomm_ayx.dtsi
index 052b2a4babe60b..6e225c0825c0b1 100644
--- a/target/linux/ramips/dts/mt7621_netgear_sercomm_ayx.dtsi
+++ b/target/linux/ramips/dts/mt7621_netgear_sercomm_ayx.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "mediatek,mt7621-soc";
@@ -41,19 +42,22 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
 		};
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&xhci_ehci_port1>, <&ehci_port2>;
 			linux,default-trigger = "usbport";
 		};
 
 		internet {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 		};
 
@@ -64,7 +68,8 @@
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/mt7621_netgear_sercomm_bzv.dtsi b/target/linux/ramips/dts/mt7621_netgear_sercomm_bzv.dtsi
index 1ae7fd0f57215b..61c3ec37613d02 100644
--- a/target/linux/ramips/dts/mt7621_netgear_sercomm_bzv.dtsi
+++ b/target/linux/ramips/dts/mt7621_netgear_sercomm_bzv.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "mediatek,mt7621-soc";
@@ -43,22 +44,26 @@
 
 		led_power_orange: power_orange {
 			gpios = <&gpio_expander 0 GPIO_ACTIVE_LOW>;
-			label = "orange:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_ORANGE>;
 		};
 
 		led_power_white: power_white {
 			gpios = <&gpio_expander 1 GPIO_ACTIVE_LOW>;
-			label = "white:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_WHITE>;
 		};
 
 		wan_orange {
 			gpios = <&gpio_expander 2 GPIO_ACTIVE_LOW>;
-			label = "orange:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_ORANGE>;
 		};
 
 		wan_white {
 			gpios = <&gpio_expander 3 GPIO_ACTIVE_LOW>;
-			label = "white:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_WHITE>;
 		};
 
 		wlan2g {
@@ -122,12 +127,14 @@
 
 		wps {
 			gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
-			label = "white:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_WHITE>;
 		};
 
 		wlan {
 			gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
-			label = "white:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_WHITE>;
 		};
 	};
 };
@@ -339,7 +346,7 @@
 			read-only;
 		};
 
-		factory: partition@4600000 {
+		partition@4600000 {
 			label = "factory";
 			reg = <0x4600000 0x200000>;
 			sercomm,scpart-id = <16>;
diff --git a/target/linux/ramips/dts/mt7621_netgear_sercomm_chj.dtsi b/target/linux/ramips/dts/mt7621_netgear_sercomm_chj.dtsi
index 72ff75cefa9a96..13ce338588bb92 100644
--- a/target/linux/ramips/dts/mt7621_netgear_sercomm_chj.dtsi
+++ b/target/linux/ramips/dts/mt7621_netgear_sercomm_chj.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "mediatek,mt7621-soc";
@@ -20,19 +21,22 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
 		};
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&xhci_ehci_port1>, <&ehci_port2>;
 			linux,default-trigger = "usbport";
 		};
 
 		internet {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 		};
 
@@ -266,7 +270,7 @@
 			read-only;
 		};
 
-		factory: partition@4600000 {
+		partition@4600000 {
 			label = "factory";
 			reg = <0x4600000 0x200000>;
 			sercomm,scpart-id = <16>;
diff --git a/target/linux/ramips/dts/mt7621_netgear_wac104.dts b/target/linux/ramips/dts/mt7621_netgear_wac104.dts
index 48a3302e79c454..9c706530d4b4b2 100644
--- a/target/linux/ramips/dts/mt7621_netgear_wac104.dts
+++ b/target/linux/ramips/dts/mt7621_netgear_wac104.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "netgear,wac104", "mediatek,mt7621-soc";
@@ -43,12 +44,14 @@
 		compatible = "gpio-leds";
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
 		};
 
@@ -95,7 +98,7 @@
 			reg = <0x600000 0x1c00000>;
 		};
 
-		factory: partition@2e00000 {
+		partition@2e00000 {
 			label = "factory";
 			reg = <0x2e00000 0x100000>;
 			read-only;
diff --git a/target/linux/ramips/dts/mt7621_netgear_wax202.dts b/target/linux/ramips/dts/mt7621_netgear_wax202.dts
index c0c3500af25ad9..bf580de6b88f9e 100644
--- a/target/linux/ramips/dts/mt7621_netgear_wax202.dts
+++ b/target/linux/ramips/dts/mt7621_netgear_wax202.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "netgear,wax202", "mediatek,mt7621-soc";
@@ -34,12 +35,14 @@
 		compatible = "gpio-leds";
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_orange: power_orange {
-			label = "orange:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
 		};
 
@@ -112,7 +115,7 @@
 			read-only;
 		};
 
-		factory: partition@100000 {
+		partition@100000 {
 			label = "Factory";
 			reg = <0x100000 0x80000>;
 			read-only;
diff --git a/target/linux/ramips/dts/mt7621_netgear_wndr3700-v5.dts b/target/linux/ramips/dts/mt7621_netgear_wndr3700-v5.dts
index 8252d2b9ff7d8d..fb94d07eeaf313 100644
--- a/target/linux/ramips/dts/mt7621_netgear_wndr3700-v5.dts
+++ b/target/linux/ramips/dts/mt7621_netgear_wndr3700-v5.dts
@@ -36,7 +36,7 @@
 				read-only;
 			};
 
-			factory: partition@f30000 {
+			partition@f30000 {
 				label = "factory";
 				reg = <0xf30000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_netis_wf2881.dts b/target/linux/ramips/dts/mt7621_netis_wf2881.dts
index c58e32377e800b..58d2c70655ca5b 100644
--- a/target/linux/ramips/dts/mt7621_netis_wf2881.dts
+++ b/target/linux/ramips/dts/mt7621_netis_wf2881.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "netis,wf2881", "mediatek,mt7621-soc";
@@ -19,14 +20,16 @@
 		compatible = "gpio-leds";
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&xhci_ehci_port1>, <&ehci_port2>;
 			linux,default-trigger = "usbport";
 		};
 
 		led_wps: wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -62,7 +65,7 @@
 			read-only;
 		};
 
-		factory: partition@100000 {
+		partition@100000 {
 			label = "factory";
 			reg = <0x100000 0x40000>;
 			read-only;
diff --git a/target/linux/ramips/dts/mt7621_oraybox_x3a.dts b/target/linux/ramips/dts/mt7621_oraybox_x3a.dts
index 239159996337e2..7b33efd6e66a66 100644
--- a/target/linux/ramips/dts/mt7621_oraybox_x3a.dts
+++ b/target/linux/ramips/dts/mt7621_oraybox_x3a.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "oraybox,x3a", "mediatek,mt7621-soc";
@@ -25,17 +26,20 @@
 		compatible = "gpio-leds";
 
 		led_status_red: status-red {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status_blue: status-blue {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status_green: status-green {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -76,7 +80,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_phicomm_k2p.dts b/target/linux/ramips/dts/mt7621_phicomm_k2p.dts
index 85cf8ecfd3ef60..6a733698d2a113 100644
--- a/target/linux/ramips/dts/mt7621_phicomm_k2p.dts
+++ b/target/linux/ramips/dts/mt7621_phicomm_k2p.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "phicomm,k2p", "mediatek,mt7621-soc";
@@ -18,17 +19,20 @@
 		compatible = "gpio-leds";
 
 		stat_r {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 13 GPIO_ACTIVE_HIGH>;
 		};
 
 		stat_y {
-			label = "yellow:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_YELLOW>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		};
 
 		led_blue: stat_b {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -69,7 +73,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_planex_vr500.dts b/target/linux/ramips/dts/mt7621_planex_vr500.dts
index 93e7280b4c06f9..4d281670ef9e84 100644
--- a/target/linux/ramips/dts/mt7621_planex_vr500.dts
+++ b/target/linux/ramips/dts/mt7621_planex_vr500.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "planex,vr500", "mediatek,mt7621-soc";
@@ -18,7 +19,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 45 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -59,7 +61,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_raisecom_msg1500-x-00.dts b/target/linux/ramips/dts/mt7621_raisecom_msg1500-x-00.dts
index 4a9e420370a47b..98a2ffad5f7f17 100644
--- a/target/linux/ramips/dts/mt7621_raisecom_msg1500-x-00.dts
+++ b/target/linux/ramips/dts/mt7621_raisecom_msg1500-x-00.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "raisecom,msg1500-x-00", "mediatek,mt7621-soc";
@@ -32,7 +33,8 @@
 		};
 
 		led_usb: usb {
-			label = "blue:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&ehci_port2>;
 			linux,default-trigger = "usbport";
@@ -100,7 +102,7 @@
 			};
 		};
 
-		factory: partition@100000 {
+		partition@100000 {
 			label = "Factory";
 			reg = <0x100000 0x40000>;
 			read-only;
diff --git a/target/linux/ramips/dts/mt7621_renkforce_ws-wn530hp3-a.dts b/target/linux/ramips/dts/mt7621_renkforce_ws-wn530hp3-a.dts
index 8a32a86e7bb045..b3aaffeafed1c6 100644
--- a/target/linux/ramips/dts/mt7621_renkforce_ws-wn530hp3-a.dts
+++ b/target/linux/ramips/dts/mt7621_renkforce_ws-wn530hp3-a.dts
@@ -67,7 +67,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_samknows_whitebox-v8.dts b/target/linux/ramips/dts/mt7621_samknows_whitebox-v8.dts
index c3c5a2ff4a8200..5afed4c695608b 100644
--- a/target/linux/ramips/dts/mt7621_samknows_whitebox-v8.dts
+++ b/target/linux/ramips/dts/mt7621_samknows_whitebox-v8.dts
@@ -1,6 +1,7 @@
 #include "mt7621.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/gpio/gpio.h>
 
 / {
@@ -18,12 +19,14 @@
 		compatible = "gpio-leds";
 
 		led_wps: wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
 		};
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 47 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&xhci_ehci_port1>, <&ehci_port2>;
 			linux,default-trigger = "usbport";
@@ -71,7 +74,7 @@
 				reg = <0x30000 0x10000>;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_sercomm_dxx_nand_256m.dtsi b/target/linux/ramips/dts/mt7621_sercomm_dxx_nand_256m.dtsi
index 0416a5f980db62..fd952cbc931fd6 100644
--- a/target/linux/ramips/dts/mt7621_sercomm_dxx_nand_256m.dtsi
+++ b/target/linux/ramips/dts/mt7621_sercomm_dxx_nand_256m.dtsi
@@ -94,7 +94,7 @@
 			read-only;
 		};
 
-		factory: partition@200000 {
+		partition@200000 {
 			label = "Factory";
 			reg = <0x200000 0x100000>;
 			sercomm,scpart-id = <2>;
diff --git a/target/linux/ramips/dts/mt7621_sercomm_na502.dts b/target/linux/ramips/dts/mt7621_sercomm_na502.dts
index 44b1077bc60abc..049dd35fa7d238 100644
--- a/target/linux/ramips/dts/mt7621_sercomm_na502.dts
+++ b/target/linux/ramips/dts/mt7621_sercomm_na502.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "sercomm,na502", "mediatek,mt7621-soc";
@@ -20,7 +21,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		};
 
@@ -51,7 +53,8 @@
 		};
 
 		bluetooth {
-			label = "green:bluetooth";
+			function = LED_FUNCTION_BLUETOOTH;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 25 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -124,7 +127,7 @@
 			read-only;
 		};
 
-		factory: partition@100000 {
+		partition@100000 {
 			label = "factory";
 			reg = <0x100000 0x40000>;
 
diff --git a/target/linux/ramips/dts/mt7621_sercomm_na502s.dts b/target/linux/ramips/dts/mt7621_sercomm_na502s.dts
index bea5998935f6bd..e794ef88750790 100644
--- a/target/linux/ramips/dts/mt7621_sercomm_na502s.dts
+++ b/target/linux/ramips/dts/mt7621_sercomm_na502s.dts
@@ -3,6 +3,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "sercomm,na502s", "mediatek,mt7621-soc";
@@ -19,7 +20,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
 		};
 
@@ -40,7 +42,8 @@
 		};
 
 		bluetooth {
-			label = "green:bluetooth";
+			function = LED_FUNCTION_BLUETOOTH;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio_expander1 3 GPIO_ACTIVE_LOW>;
 		};
 
@@ -228,7 +231,7 @@
 			read-only;
 		};
 
-		factory: partition@100000 {
+		partition@100000 {
 			label = "factory";
 			reg = <0x100000 0x40000>;
 
diff --git a/target/linux/ramips/dts/mt7621_sercomm_s1500.dtsi b/target/linux/ramips/dts/mt7621_sercomm_s1500.dtsi
index d03e0da548e153..e5a073f3148695 100644
--- a/target/linux/ramips/dts/mt7621_sercomm_s1500.dtsi
+++ b/target/linux/ramips/dts/mt7621_sercomm_s1500.dtsi
@@ -159,7 +159,7 @@
 			read-only;
 		};
 
-		factory: partition@100000 {
+		partition@100000 {
 			label = "Factory";
 			reg = <0x100000 0x100000>;
 			read-only;
diff --git a/target/linux/ramips/dts/mt7621_snr_snr-cpe-me1.dts b/target/linux/ramips/dts/mt7621_snr_snr-cpe-me1.dts
index 7383ba1e20942e..6ea2c199e310a9 100644
--- a/target/linux/ramips/dts/mt7621_snr_snr-cpe-me1.dts
+++ b/target/linux/ramips/dts/mt7621_snr_snr-cpe-me1.dts
@@ -145,7 +145,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "Factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_snr_snr-cpe-me2-lite.dts b/target/linux/ramips/dts/mt7621_snr_snr-cpe-me2-lite.dts
index 51425b9a1569f1..3b474819e1630a 100644
--- a/target/linux/ramips/dts/mt7621_snr_snr-cpe-me2-lite.dts
+++ b/target/linux/ramips/dts/mt7621_snr_snr-cpe-me2-lite.dts
@@ -13,14 +13,12 @@
 		compatible = "gpio-leds";
 
 		led_sys: led-0 {
-			label = "green:sys";
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_STATUS;
 			gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_vpn: led-1 {
-			label = "green:vpn";
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_STATUS;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
@@ -73,7 +71,7 @@
 				reg = <0x30000 0x10000>;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_snr_snr-cpe-me2-sfp.dts b/target/linux/ramips/dts/mt7621_snr_snr-cpe-me2-sfp.dts
index 65f33f615bec2e..6249eb65208b52 100644
--- a/target/linux/ramips/dts/mt7621_snr_snr-cpe-me2-sfp.dts
+++ b/target/linux/ramips/dts/mt7621_snr_snr-cpe-me2-sfp.dts
@@ -20,21 +20,18 @@
 		compatible = "gpio-leds";
 
 		led_sys: sys {
-			label = "green:sys";
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_STATUS;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 		};
 
 		vpn {
-			label = "green:vpn";
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_STATUS;
 			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
 		};
 
 		usb {
-			label = "green:usb";
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_USB;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
@@ -112,7 +109,7 @@
 				reg = <0x30000 0x10000>;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_storylink_sap-g3200u3.dts b/target/linux/ramips/dts/mt7621_storylink_sap-g3200u3.dts
index 60817edbbff7bb..7b89ee67274835 100644
--- a/target/linux/ramips/dts/mt7621_storylink_sap-g3200u3.dts
+++ b/target/linux/ramips/dts/mt7621_storylink_sap-g3200u3.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "storylink,sap-g3200u3", "mediatek,mt7621-soc";
@@ -11,7 +12,8 @@
 		compatible = "gpio-leds";
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&xhci_ehci_port1>, <&ehci_port2>;
 			linux,default-trigger = "usbport";
@@ -66,7 +68,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_telco-electronics_x1.dts b/target/linux/ramips/dts/mt7621_telco-electronics_x1.dts
index 4d8fa7f320d94a..2ec5992de154bd 100644
--- a/target/linux/ramips/dts/mt7621_telco-electronics_x1.dts
+++ b/target/linux/ramips/dts/mt7621_telco-electronics_x1.dts
@@ -105,7 +105,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
@@ -131,7 +131,7 @@
 				};
 			};
 
-			firmware: partition@50000 {
+			partition@50000 {
 				compatible = "denx,uimage";
 				label = "firmware";
 				reg = <0x50000 0xfb0000>;
diff --git a/target/linux/ramips/dts/mt7621_tenbay_t-mb5eu-v01.dts b/target/linux/ramips/dts/mt7621_tenbay_t-mb5eu-v01.dts
index 7b1e5d863b5c1c..d1310ad95499d8 100644
--- a/target/linux/ramips/dts/mt7621_tenbay_t-mb5eu-v01.dts
+++ b/target/linux/ramips/dts/mt7621_tenbay_t-mb5eu-v01.dts
@@ -193,7 +193,7 @@
 				read-only;
 			};
 
-			factory: partition@50000 {
+			partition@50000 {
 				label = "factory";
 				reg = <0x50000 0x40000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_thunder_timecloud.dts b/target/linux/ramips/dts/mt7621_thunder_timecloud.dts
index da1db0366f461e..82efb0352e5f77 100644
--- a/target/linux/ramips/dts/mt7621_thunder_timecloud.dts
+++ b/target/linux/ramips/dts/mt7621_thunder_timecloud.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "thunder,timecloud", "mediatek,mt7621-soc";
@@ -22,12 +23,14 @@
 		compatible = "gpio-leds";
 
 		statw {
-			label = "white:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_statuso: stato {
-			label = "orange:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
 		};
 	};
@@ -78,7 +81,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_totolink_a7000r.dts b/target/linux/ramips/dts/mt7621_totolink_a7000r.dts
index dd6cc5d844b783..8c0062973d4703 100644
--- a/target/linux/ramips/dts/mt7621_totolink_a7000r.dts
+++ b/target/linux/ramips/dts/mt7621_totolink_a7000r.dts
@@ -62,7 +62,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_totolink_x5000r.dts b/target/linux/ramips/dts/mt7621_totolink_x5000r.dts
index d2c242be6f4328..24606904e14d26 100644
--- a/target/linux/ramips/dts/mt7621_totolink_x5000r.dts
+++ b/target/linux/ramips/dts/mt7621_totolink_x5000r.dts
@@ -69,7 +69,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_tozed_zlt-s12-pro.dts b/target/linux/ramips/dts/mt7621_tozed_zlt-s12-pro.dts
index 2d8717e3cdd082..0c3079f097b2b9 100644
--- a/target/linux/ramips/dts/mt7621_tozed_zlt-s12-pro.dts
+++ b/target/linux/ramips/dts/mt7621_tozed_zlt-s12-pro.dts
@@ -36,12 +36,14 @@
 		};
 
 		led_power_blue: led-power-blue {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_yellow: led-power-yellow {
-			label = "yellow:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_YELLOW>;
 			gpios = <&gpio 29 GPIO_ACTIVE_LOW>;
 		};
 
@@ -159,7 +161,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_tplink_archer-ax23-v1.dts b/target/linux/ramips/dts/mt7621_tplink_archer-ax23-v1.dts
index 4de71d9e429580..71ef4bc6b6155e 100644
--- a/target/linux/ramips/dts/mt7621_tplink_archer-ax23-v1.dts
+++ b/target/linux/ramips/dts/mt7621_tplink_archer-ax23-v1.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "tplink,archer-ax23-v1", "mediatek,mt7621-soc";
@@ -41,7 +42,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
 		};
 
@@ -58,22 +60,26 @@
 		};
 
 		wan-green {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		};
 
 		wan-orange {
-			label = "orange:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -104,7 +110,7 @@
 				reg = <0x040000 0xf60000>;
 			};
 
-			config: partition@fa0000 {
+			partition@fa0000 {
 				label = "config";
 				reg = <0xfa0000 0x010000>;
 				read-only;
@@ -128,7 +134,7 @@
 				read-only;
 			};
 
-			radio: partition@ff0000 {
+			partition@ff0000 {
 				label = "radio";
 				reg = <0xff0000 0x010000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_tplink_archer-c6u-v1.dts b/target/linux/ramips/dts/mt7621_tplink_archer-c6u-v1.dts
index 522408b220c809..e9879128a30bae 100644
--- a/target/linux/ramips/dts/mt7621_tplink_archer-c6u-v1.dts
+++ b/target/linux/ramips/dts/mt7621_tplink_archer-c6u-v1.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "tplink,archer-c6u-v1", "mediatek,mt7621-soc";
@@ -41,24 +42,28 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
 		};
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&ehci_port2>;
 			linux,default-trigger = "usbport";
 		};
 
 		wan-orange {
-			label = "orange:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 		};
 
@@ -75,7 +80,8 @@
 		};
 
 		wan-green {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 45 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -115,7 +121,7 @@
 				reg = <0x040000 0xf60000>;
 			};
 
-			config: partition@fa0000 {
+			partition@fa0000 {
 				label = "config";
 				reg = <0xfa0000 0x010000>;
 				read-only;
@@ -139,7 +145,7 @@
 				read-only;
 			};
 
-			radio: partition@ff0000 {
+			partition@ff0000 {
 				label = "radio";
 				reg = <0xff0000 0x010000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_tplink_archer-x6-v3.dtsi b/target/linux/ramips/dts/mt7621_tplink_archer-x6-v3.dtsi
index d3db8cd602cb76..83864975416dca 100644
--- a/target/linux/ramips/dts/mt7621_tplink_archer-x6-v3.dtsi
+++ b/target/linux/ramips/dts/mt7621_tplink_archer-x6-v3.dtsi
@@ -41,7 +41,6 @@
 		compatible = "gpio-leds";
 
 		led_power: led-power {
-			label = "green:power";
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_POWER;
 			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
@@ -108,7 +107,7 @@
 				reg = <0x40000 0xf60000>;
 			};
 
-			config: partition@fa0000 {
+			partition@fa0000 {
 				label = "config";
 				reg = <0xfa0000 0x50000>;
 				read-only;
@@ -126,7 +125,7 @@
 				};
 			};
 
-			radio: partition@ff0000 {
+			partition@ff0000 {
 				label = "radio";
 				reg = <0xff0000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_tplink_deco-m4r-v4.dts b/target/linux/ramips/dts/mt7621_tplink_deco-m4r-v4.dts
index 087910233e28c1..9f30f935509a6a 100644
--- a/target/linux/ramips/dts/mt7621_tplink_deco-m4r-v4.dts
+++ b/target/linux/ramips/dts/mt7621_tplink_deco-m4r-v4.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "tplink,deco-m4r-v4", "mediatek,mt7621-soc";
@@ -55,7 +56,8 @@
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
 		};
 
@@ -126,7 +128,7 @@
 				reg = <0x40000 0xf60000>;
 			};
 
-			config: partition@fa0000 {
+			partition@fa0000 {
 				label = "config";
 				reg = <0xfa0000 0x010000>;
 				read-only;
@@ -148,7 +150,7 @@
 				read-only;
 			};
 
-			radio: partition@ff0000 {
+			partition@ff0000 {
 				label = "radio";
 				reg = <0xff0000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_tplink_eap235-wall-v1.dts b/target/linux/ramips/dts/mt7621_tplink_eap235-wall-v1.dts
index a91a18efc75808..d814cba261e167 100644
--- a/target/linux/ramips/dts/mt7621_tplink_eap235-wall-v1.dts
+++ b/target/linux/ramips/dts/mt7621_tplink_eap235-wall-v1.dts
@@ -22,7 +22,6 @@
 		compatible = "gpio-leds";
 
 		led_status: status {
-			label = "white:status";
 			color = <LED_COLOR_ID_WHITE>;
 			function = LED_FUNCTION_STATUS;
 			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
@@ -81,7 +80,7 @@
 				read-only;
 			};
 
-			info: partition@90000 {
+			partition@90000 {
 				label = "product-info";
 				reg = <0x90000 0x10000>;
 				read-only;
@@ -125,7 +124,7 @@
 				read-only;
 			};
 
-			radio: partition@ff0000 {
+			partition@ff0000 {
 				label = "radio";
 				reg = <0xff0000 0x010000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_tplink_eap613-v1.dts b/target/linux/ramips/dts/mt7621_tplink_eap613-v1.dts
index 6c66401580cc82..e14873f61add84 100644
--- a/target/linux/ramips/dts/mt7621_tplink_eap613-v1.dts
+++ b/target/linux/ramips/dts/mt7621_tplink_eap613-v1.dts
@@ -26,7 +26,6 @@
 		compatible = "gpio-leds";
 
 		led_status: status {
-			label = "blue:status";
 			color = <LED_COLOR_ID_BLUE>;
 			function = LED_FUNCTION_STATUS;
 			gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
@@ -109,7 +108,7 @@
 				read-only;
 			};
 
-			radio: partition@ff0000 {
+			partition@ff0000 {
 				label = "radio";
 				reg = <0xff0000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_tplink_eap615-wall-v1.dts b/target/linux/ramips/dts/mt7621_tplink_eap615-wall-v1.dts
index b8564885393cdc..2aea6bbbc00760 100644
--- a/target/linux/ramips/dts/mt7621_tplink_eap615-wall-v1.dts
+++ b/target/linux/ramips/dts/mt7621_tplink_eap615-wall-v1.dts
@@ -26,7 +26,6 @@
 		compatible = "gpio-leds";
 
 		led_status: status {
-			label = "white:status";
 			color = <LED_COLOR_ID_WHITE>;
 			function = LED_FUNCTION_STATUS;
 			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
@@ -89,7 +88,7 @@
 				read-only;
 			};
 
-			info: partition@90000 {
+			partition@90000 {
 				label = "product-info";
 				reg = <0x90000 0x10000>;
 				read-only;
@@ -129,7 +128,7 @@
 				read-only;
 			};
 
-			radio: partition@ff0000 {
+			partition@ff0000 {
 				label = "radio";
 				reg = <0xff0000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_tplink_ec330-g5u-v1.dts b/target/linux/ramips/dts/mt7621_tplink_ec330-g5u-v1.dts
index a1b458edd58419..6203308515f3b7 100644
--- a/target/linux/ramips/dts/mt7621_tplink_ec330-g5u-v1.dts
+++ b/target/linux/ramips/dts/mt7621_tplink_ec330-g5u-v1.dts
@@ -211,7 +211,7 @@
 			reg = <0x7400000 0x400000>;
 		};
 
-		factory: partition@7800000 {
+		partition@7800000 {
 			label = "factory";
 			reg = <0x7800000 0x400000>;
 			read-only;
diff --git a/target/linux/ramips/dts/mt7621_tplink_er605-v2.dts b/target/linux/ramips/dts/mt7621_tplink_er605-v2.dts
index 04935e3e99b438..33070ef6cafcb3 100644
--- a/target/linux/ramips/dts/mt7621_tplink_er605-v2.dts
+++ b/target/linux/ramips/dts/mt7621_tplink_er605-v2.dts
@@ -29,14 +29,12 @@
 		compatible = "gpio-leds";
 
 		led_usb: usb {
-			label = "green:usb";
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_STATUS;
 			gpios = <&gpio 11 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_power: power {
-			label = "green:power";
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_STATUS;
 			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
@@ -44,7 +42,6 @@
 		};
 
 		led_system: system {
-			label = "green:system";
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_STATUS;
 			gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
@@ -140,7 +137,7 @@
 			read-only;
 		};
 
-		factory: partition@100000 {
+		partition@100000 {
 			label = "factory";
 			reg = <0x100000 0x40000>;
 			read-only;
diff --git a/target/linux/ramips/dts/mt7621_tplink_ex220-v1.dts b/target/linux/ramips/dts/mt7621_tplink_ex220-v1.dts
index ffefd07d853249..c501727ca837d4 100644
--- a/target/linux/ramips/dts/mt7621_tplink_ex220-v1.dts
+++ b/target/linux/ramips/dts/mt7621_tplink_ex220-v1.dts
@@ -82,7 +82,6 @@
 		};
 
 		led_power: led-power {
-			label = "green:power"; // to be removed once #13837 is merged
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_POWER;
 			gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
@@ -157,7 +156,7 @@
 				read-only;
 			};
 
-			radio: partition@90000 {
+			partition@90000 {
 				label = "radio";
 				reg = <0x90000 0x20000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_tplink_mr600-v2-eu.dts b/target/linux/ramips/dts/mt7621_tplink_mr600-v2-eu.dts
index 6b73ffff24f182..db460b43b2a1b2 100644
--- a/target/linux/ramips/dts/mt7621_tplink_mr600-v2-eu.dts
+++ b/target/linux/ramips/dts/mt7621_tplink_mr600-v2-eu.dts
@@ -42,16 +42,19 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "white:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
 		};
 		wlan {
-			label = "white:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy1tpt";
 		};
 		wan {
-			label = "white:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
 		};
 
@@ -75,7 +78,8 @@
 			gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
 		};
 		lan {
-			label = "white:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -108,7 +112,7 @@
 				reg = <0x20000 0xfa0000>;
 			};
 
-			romfile: partition@fc0000 {
+			partition@fc0000 {
 				label = "romfile";
 				reg = <0xfc0000 0x10000>;
 				read-only;
@@ -132,7 +136,7 @@
 				read-only;
 			};
 
-			radio: partition@fe0000 {
+			partition@fe0000 {
 				label = "radio";
 				reg = <0xfe0000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_tplink_re350-v1.dts b/target/linux/ramips/dts/mt7621_tplink_re350-v1.dts
index be23abf4c83edf..6437cba7b1933c 100644
--- a/target/linux/ramips/dts/mt7621_tplink_re350-v1.dts
+++ b/target/linux/ramips/dts/mt7621_tplink_re350-v1.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "tplink,re350-v1", "mediatek,mt7621-soc";
@@ -18,7 +19,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
 		};
 
@@ -33,12 +35,14 @@
 		};
 
 		wps_r {
-			label = "red:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
 		};
 
 		wps_b {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 26 GPIO_ACTIVE_HIGH>;
 		};
 
@@ -107,7 +111,7 @@
 				reg = <0x20000 0x5e0000>;
 			};
 
-			config: partition@600000 {
+			partition@600000 {
 				label = "config";
 				reg = <0x600000 0x50000>;
 				read-only;
@@ -125,7 +129,7 @@
 				};
 			};
 
-			radio: partition@7f0000 {
+			partition@7f0000 {
 				label = "radio";
 				reg = <0x7f0000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_tplink_re650-v2.dts b/target/linux/ramips/dts/mt7621_tplink_re650-v2.dts
index 7dcd5e553cd79c..ef066f5a9430b5 100644
--- a/target/linux/ramips/dts/mt7621_tplink_re650-v2.dts
+++ b/target/linux/ramips/dts/mt7621_tplink_re650-v2.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "tplink,re650-v2", "mediatek,mt7621-soc";
@@ -53,7 +54,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
 		};
 
@@ -70,12 +72,14 @@
 		};
 
 		wps_red {
-			label = "red:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 26 GPIO_ACTIVE_HIGH>;
 		};
 
 		wps_blue {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 27 GPIO_ACTIVE_HIGH>;
 		};
 
@@ -116,7 +120,7 @@
 				reg = <0x20000 0x7a0000>;
 			};
 
-			config: partition@7c0000 {
+			partition@7c0000 {
 				label = "config";
 				reg = <0x7c0000 0x2d440>;
 				read-only;
@@ -134,7 +138,7 @@
 				};
 			};
 
-			radio: partition@7f0000 {
+			partition@7f0000 {
 				label = "radio";
 				reg = <0x7f0000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_tplink_rexx0-v1.dtsi b/target/linux/ramips/dts/mt7621_tplink_rexx0-v1.dtsi
index 3784a4f3c952f9..e915e37eea9269 100644
--- a/target/linux/ramips/dts/mt7621_tplink_rexx0-v1.dtsi
+++ b/target/linux/ramips/dts/mt7621_tplink_rexx0-v1.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -50,7 +51,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
 		};
 
@@ -67,12 +69,14 @@
 		};
 
 		wps_red {
-			label = "red:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 26 GPIO_ACTIVE_HIGH>;
 		};
 
 		wps_blue {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 27 GPIO_ACTIVE_HIGH>;
 		};
 
@@ -113,7 +117,7 @@
 				reg = <0x20000 0xde0000>;
 			};
 
-			config: partition@e00000 {
+			partition@e00000 {
 				label = "config";
 				reg = <0xe00000 0x50000>;
 				read-only;
@@ -135,7 +139,7 @@
 			 * firmware, so we do not use it either
 			 */
 
-			radio: partition@ff0000 {
+			partition@ff0000 {
 				label = "radio";
 				reg = <0xff0000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_tplink_tl-wpa8631p-v3.dts b/target/linux/ramips/dts/mt7621_tplink_tl-wpa8631p-v3.dts
index 1e0fd2023970ca..54f3b88e579d9b 100644
--- a/target/linux/ramips/dts/mt7621_tplink_tl-wpa8631p-v3.dts
+++ b/target/linux/ramips/dts/mt7621_tplink_tl-wpa8631p-v3.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "tplink,tl-wpa8631p-v3", "mediatek,mt7621-soc";
@@ -53,12 +54,14 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 29 GPIO_ACTIVE_LOW>;
 		};
 
@@ -111,7 +114,7 @@
 				reg = <0x20000 0x710000>;
 			};
 
-			config: partition@730000 {
+			partition@730000 {
 				label = "config";
 				reg = <0x730000 0xc0000>;
 				read-only;
@@ -129,7 +132,7 @@
 				};
 			};
 
-			radio: partition@7f0000 {
+			partition@7f0000 {
 				label = "radio";
 				reg = <0x7f0000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_ubnt_edgerouter-x.dtsi b/target/linux/ramips/dts/mt7621_ubnt_edgerouter-x.dtsi
index b2b78aba6322d9..0902ad56b961ff 100644
--- a/target/linux/ramips/dts/mt7621_ubnt_edgerouter-x.dtsi
+++ b/target/linux/ramips/dts/mt7621_ubnt_edgerouter-x.dtsi
@@ -82,7 +82,7 @@
 			read-only;
 		};
 
-		factory: partition@e0000 {
+		partition@e0000 {
 			label = "factory";
 			reg = <0xe0000 0x60000>;
 
diff --git a/target/linux/ramips/dts/mt7621_ubnt_unifi-6-lite.dts b/target/linux/ramips/dts/mt7621_ubnt_unifi-6-lite.dts
index d439e124e3f408..9149904809a903 100644
--- a/target/linux/ramips/dts/mt7621_ubnt_unifi-6-lite.dts
+++ b/target/linux/ramips/dts/mt7621_ubnt_unifi-6-lite.dts
@@ -36,7 +36,7 @@
 				read-only;
 			};
 
-			factory: partition@70000 {
+			partition@70000 {
 				label = "factory";
 				reg = <0x70000 0x40000>;
 				read-only;
@@ -60,7 +60,7 @@
 				};
 			};
 
-			eeprom: partition@b0000 {
+			partition@b0000 {
 				label = "eeprom";
 				reg = <0xb0000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_ubnt_unifi-flexhd.dts b/target/linux/ramips/dts/mt7621_ubnt_unifi-flexhd.dts
index d458b91ca6d954..2451545a5ef5d8 100644
--- a/target/linux/ramips/dts/mt7621_ubnt_unifi-flexhd.dts
+++ b/target/linux/ramips/dts/mt7621_ubnt_unifi-flexhd.dts
@@ -57,7 +57,7 @@
 				read-only;
 			};
 
-			factory: partition@70000 {
+			partition@70000 {
 				label = "factory";
 				reg = <0x70000 0x10000>;
 				read-only;
@@ -77,7 +77,7 @@
 				};
 			};
 
-			eeprom: partition@80000 {
+			partition@80000 {
 				label = "eeprom";
 				reg = <0x80000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_ubnt_unifi-nanohd.dts b/target/linux/ramips/dts/mt7621_ubnt_unifi-nanohd.dts
index d81a23852d721c..5b25c79841a8bf 100644
--- a/target/linux/ramips/dts/mt7621_ubnt_unifi-nanohd.dts
+++ b/target/linux/ramips/dts/mt7621_ubnt_unifi-nanohd.dts
@@ -32,7 +32,7 @@
 				read-only;
 			};
 
-			factory: partition@70000 {
+			partition@70000 {
 				label = "factory";
 				reg = <0x70000 0x10000>;
 				read-only;
@@ -52,7 +52,7 @@
 				};
 			};
 
-			eeprom: partition@80000 {
+			partition@80000 {
 				label = "eeprom";
 				reg = <0x80000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_ubnt_usw-flex.dts b/target/linux/ramips/dts/mt7621_ubnt_usw-flex.dts
index f09ccba58556fb..0d6d50022292f1 100644
--- a/target/linux/ramips/dts/mt7621_ubnt_usw-flex.dts
+++ b/target/linux/ramips/dts/mt7621_ubnt_usw-flex.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Ubiquiti UniFi Switch Flex";
@@ -33,12 +34,14 @@
 		compatible = "gpio-leds";
 
 		led_blue: status_blue {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 13 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_white: status_white {
-			label = "white:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
 		};
 	};
@@ -137,7 +140,7 @@
 				read-only;
 			};
 
-			part_eeprom: partition@80000 {
+			partition@80000 {
 				label = "eeprom";
 				reg = <0x80000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_unielec_u7621-01-16m.dts b/target/linux/ramips/dts/mt7621_unielec_u7621-01-16m.dts
index d6189f3d58a99d..1ba361c3db7c5d 100644
--- a/target/linux/ramips/dts/mt7621_unielec_u7621-01-16m.dts
+++ b/target/linux/ramips/dts/mt7621_unielec_u7621-01-16m.dts
@@ -32,7 +32,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_unielec_u7621-01.dtsi b/target/linux/ramips/dts/mt7621_unielec_u7621-01.dtsi
index 813ddc7327a06a..b193aed1034dac 100644
--- a/target/linux/ramips/dts/mt7621_unielec_u7621-01.dtsi
+++ b/target/linux/ramips/dts/mt7621_unielec_u7621-01.dtsi
@@ -4,17 +4,11 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "unielec,u7621-01", "mediatek,mt7621-soc";
 
-	aliases {
-		led-boot = &led_status;
-		led-failsafe = &led_status;
-		led-running = &led_status;
-		led-upgrade = &led_status;
-	};
-
 	gpio-export {
 		compatible = "gpio-export";
 		#size-cells = <0>;
@@ -35,15 +29,6 @@
 			linux,code = <KEY_RESTART>;
 		};
 	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		led_status: status {
-			label = "green:status";
-			gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
-		};
-	};
 };
 
 &pcie {
diff --git a/target/linux/ramips/dts/mt7621_unielec_u7621-06-16m.dts b/target/linux/ramips/dts/mt7621_unielec_u7621-06-16m.dts
index c51b6eebee0aca..73a505a1917df6 100644
--- a/target/linux/ramips/dts/mt7621_unielec_u7621-06-16m.dts
+++ b/target/linux/ramips/dts/mt7621_unielec_u7621-06-16m.dts
@@ -37,7 +37,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
@@ -57,7 +57,7 @@
 				};
 			};
 
-			firmware: partition@50000 {
+			partition@50000 {
 				compatible = "denx,uimage";
 				label = "firmware";
 				reg = <0x50000 0xfb0000>;
diff --git a/target/linux/ramips/dts/mt7621_unielec_u7621-06-32m.dts b/target/linux/ramips/dts/mt7621_unielec_u7621-06-32m.dts
index 4d34a787b6682d..0fb38984b714f4 100644
--- a/target/linux/ramips/dts/mt7621_unielec_u7621-06-32m.dts
+++ b/target/linux/ramips/dts/mt7621_unielec_u7621-06-32m.dts
@@ -38,7 +38,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
@@ -58,7 +58,7 @@
 				};
 			};
 
-			firmware: partition@50000 {
+			partition@50000 {
 				compatible = "denx,uimage";
 				label = "firmware";
 				reg = <0x50000 0x1fb0000>;
diff --git a/target/linux/ramips/dts/mt7621_unielec_u7621-06-64m.dts b/target/linux/ramips/dts/mt7621_unielec_u7621-06-64m.dts
index edc3a7723a2618..0cccc5b6de283f 100644
--- a/target/linux/ramips/dts/mt7621_unielec_u7621-06-64m.dts
+++ b/target/linux/ramips/dts/mt7621_unielec_u7621-06-64m.dts
@@ -38,7 +38,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
@@ -58,7 +58,7 @@
 				};
 			};
 
-			firmware: partition@50000 {
+			partition@50000 {
 				compatible = "denx,uimage";
 				label = "firmware";
 				reg = <0x50000 0x3fb0000>;
diff --git a/target/linux/ramips/dts/mt7621_unielec_u7621-06.dtsi b/target/linux/ramips/dts/mt7621_unielec_u7621-06.dtsi
index 9e91a0a2993d9b..42f6cea2d3c0e2 100644
--- a/target/linux/ramips/dts/mt7621_unielec_u7621-06.dtsi
+++ b/target/linux/ramips/dts/mt7621_unielec_u7621-06.dtsi
@@ -9,6 +9,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "unielec,u7621-06", "mediatek,mt7621-soc";
@@ -49,7 +50,8 @@
 		compatible = "gpio-leds";
 
 		led_status: status {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ramips/dts/mt7621_wavlink_wl-wn53xax.dtsi b/target/linux/ramips/dts/mt7621_wavlink_wl-wn53xax.dtsi
index 7df61c4eb30d20..d082a15f068639 100644
--- a/target/linux/ramips/dts/mt7621_wavlink_wl-wn53xax.dtsi
+++ b/target/linux/ramips/dts/mt7621_wavlink_wl-wn53xax.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -45,12 +46,14 @@
 		compatible = "gpio-leds";
 
 		led_status_blue: status_blue {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_status_red: status_red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
 		};
 
@@ -91,7 +94,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_wavlink_wl-wn573hx1.dts b/target/linux/ramips/dts/mt7621_wavlink_wl-wn573hx1.dts
index ec94e30a8c6565..05d8e4a5aebdd7 100644
--- a/target/linux/ramips/dts/mt7621_wavlink_wl-wn573hx1.dts
+++ b/target/linux/ramips/dts/mt7621_wavlink_wl-wn573hx1.dts
@@ -87,7 +87,7 @@
 				reg = <0x30000 0x10000>;
 			};
 
-			factory: partition@50000 {
+			partition@50000 {
 				label = "factory";
 				reg = <0x50000 0x40000>;
 
diff --git a/target/linux/ramips/dts/mt7621_wavlink_ws-wn572hp3-4g.dts b/target/linux/ramips/dts/mt7621_wavlink_ws-wn572hp3-4g.dts
index 55e828a29557f1..f9e37bee6e0f65 100644
--- a/target/linux/ramips/dts/mt7621_wavlink_ws-wn572hp3-4g.dts
+++ b/target/linux/ramips/dts/mt7621_wavlink_ws-wn572hp3-4g.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "wavlink,ws-wn572hp3-4g", "mediatek,mt7621-soc";
@@ -50,7 +51,8 @@
 		};
 
 		led_status_blue: status_blue {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
 		};
 
@@ -83,7 +85,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_wevo_w2914ns-v2.dtsi b/target/linux/ramips/dts/mt7621_wevo_w2914ns-v2.dtsi
index 8b018e18ae4402..3264a8673c1eaf 100644
--- a/target/linux/ramips/dts/mt7621_wevo_w2914ns-v2.dtsi
+++ b/target/linux/ramips/dts/mt7621_wevo_w2914ns-v2.dtsi
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -12,7 +13,8 @@
 		compatible = "gpio-leds";
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 27 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&xhci_ehci_port1>, <&ehci_port2>;
 			linux,default-trigger = "usbport";
@@ -62,7 +64,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_winstars_ws-wn583a6.dts b/target/linux/ramips/dts/mt7621_winstars_ws-wn583a6.dts
index 78f81314fc1274..7090869c4e0c4f 100644
--- a/target/linux/ramips/dts/mt7621_winstars_ws-wn583a6.dts
+++ b/target/linux/ramips/dts/mt7621_winstars_ws-wn583a6.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "winstars,ws-wn583a6", "mediatek,mt7621-soc";
@@ -25,17 +26,20 @@
 		};
 
 		led_status_blue: status_blue {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
 		};
 
 		status_amber {
-			label = "amber:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 24 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status_red: status_red {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 25 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -83,7 +87,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_xiaomi_mi-router-3-pro.dts b/target/linux/ramips/dts/mt7621_xiaomi_mi-router-3-pro.dts
index a403cd3e14ff18..f0c7646b26030b 100644
--- a/target/linux/ramips/dts/mt7621_xiaomi_mi-router-3-pro.dts
+++ b/target/linux/ramips/dts/mt7621_xiaomi_mi-router-3-pro.dts
@@ -26,28 +26,24 @@
 		compatible = "gpio-leds";
 
 		led_status_red: led-0 {
-			label = "red:status";
 			color = <LED_COLOR_ID_RED>;
 			function = LED_FUNCTION_STATUS;
 			gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status_blue: led-1 {
-			label = "blue:status";
 			color = <LED_COLOR_ID_BLUE>;
 			function = LED_FUNCTION_STATUS;
 			gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status_yellow: led-2 {
-			label = "yellow:status";
 			color = <LED_COLOR_ID_YELLOW>;
 			function = LED_FUNCTION_STATUS;
 			gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
 		};
 
 		led-3 {
-			label = "amber:wan";
 			color = <LED_COLOR_ID_AMBER>;
 			function = LED_FUNCTION_WAN;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
@@ -55,7 +51,6 @@
 		};
 
 		led-4 {
-			label = "amber:lan3";
 			color = <LED_COLOR_ID_AMBER>;
 			function = LED_FUNCTION_LAN;
 			function-enumerator = <3>;
@@ -64,7 +59,6 @@
 		};
 
 		led-5 {
-			label = "amber:lan2";
 			color = <LED_COLOR_ID_AMBER>;
 			function = LED_FUNCTION_LAN;
 			function-enumerator = <2>;
@@ -73,7 +67,6 @@
 		};
 
 		led-6 {
-			label = "amber:lan1";
 			color = <LED_COLOR_ID_AMBER>;
 			function = LED_FUNCTION_LAN;
 			function-enumerator = <1>;
@@ -131,7 +124,7 @@
 			read-only;
 		};
 
-		factory: partition@c0000 {
+		partition@c0000 {
 			label = "factory";
 			reg = <0x0c0000 0x40000>;
 			read-only;
diff --git a/target/linux/ramips/dts/mt7621_xiaomi_mi-router-3g.dts b/target/linux/ramips/dts/mt7621_xiaomi_mi-router-3g.dts
index bd8400c8985a09..ad9c18f8ffb628 100644
--- a/target/linux/ramips/dts/mt7621_xiaomi_mi-router-3g.dts
+++ b/target/linux/ramips/dts/mt7621_xiaomi_mi-router-3g.dts
@@ -17,28 +17,24 @@
 		compatible = "gpio-leds";
 
 		led_status_red: led-0 {
-			label = "red:status";
 			color = <LED_COLOR_ID_RED>;
 			function = LED_FUNCTION_STATUS;
 			gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status_blue: led-1 {
-			label = "blue:status";
 			color = <LED_COLOR_ID_BLUE>;
 			function = LED_FUNCTION_STATUS;
 			gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status_yellow: led-2 {
-			label = "yellow:status";
 			color = <LED_COLOR_ID_YELLOW>;
 			function = LED_FUNCTION_STATUS;
 			gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
 		};
 
 		led-3 {
-			label = "amber:wan";
 			color = <LED_COLOR_ID_AMBER>;
 			function = LED_FUNCTION_WAN;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
@@ -46,7 +42,6 @@
 		};
 
 		led-4 {
-			label = "amber:lan1";
 			color = <LED_COLOR_ID_AMBER>;
 			function = LED_FUNCTION_LAN;
 			function-enumerator = <1>;
@@ -55,7 +50,6 @@
 		};
 
 		led-5 {
-			label = "amber:lan2";
 			color = <LED_COLOR_ID_AMBER>;
 			function = LED_FUNCTION_LAN;
 			function-enumerator = <2>;
diff --git a/target/linux/ramips/dts/mt7621_xiaomi_mi-router-4.dts b/target/linux/ramips/dts/mt7621_xiaomi_mi-router-4.dts
index a9b62b1b28d3ae..1dfded14b1dd5c 100644
--- a/target/linux/ramips/dts/mt7621_xiaomi_mi-router-4.dts
+++ b/target/linux/ramips/dts/mt7621_xiaomi_mi-router-4.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "mt7621_xiaomi_nand_128m.dtsi"
 
 / {
@@ -18,17 +20,20 @@
 		compatible = "gpio-leds";
 
 		led_status_red: status_red {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status_blue: status_blue {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status_yellow: status_yellow {
-			label = "yellow:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_YELLOW>;
 			gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/mt7621_xiaomi_mi-router-4a-3g-v2.dtsi b/target/linux/ramips/dts/mt7621_xiaomi_mi-router-4a-3g-v2.dtsi
index 8f88eb175dd60e..61359e8b21b120 100644
--- a/target/linux/ramips/dts/mt7621_xiaomi_mi-router-4a-3g-v2.dtsi
+++ b/target/linux/ramips/dts/mt7621_xiaomi_mi-router-4a-3g-v2.dtsi
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "mt7621_xiaomi_mi-router-4a-common.dtsi"
 
 / {
@@ -11,12 +13,14 @@
 		compatible = "gpio-leds";
 
 		led_status_blue: status_blue {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status_yellow: status_yellow {
-			label = "yellow:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_YELLOW>;
 			gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/mt7621_xiaomi_mi-router-4a-common.dtsi b/target/linux/ramips/dts/mt7621_xiaomi_mi-router-4a-common.dtsi
index 7b8c4e8dfdc221..783189dfae33af 100644
--- a/target/linux/ramips/dts/mt7621_xiaomi_mi-router-4a-common.dtsi
+++ b/target/linux/ramips/dts/mt7621_xiaomi_mi-router-4a-common.dtsi
@@ -60,7 +60,7 @@
 				read-only;
 			};
 
-			factory: partition@50000 {
+			partition@50000 {
 				label = "factory";
 				reg = <0x50000 0x10000>;
 				read-only;
@@ -106,7 +106,7 @@
 				read-only;
 			};
 
-			firmware: partition@180000 {
+			partition@180000 {
 				compatible = "denx,uimage";
 				label = "firmware";
 				reg = <0x180000 0xe80000>;
diff --git a/target/linux/ramips/dts/mt7621_xiaomi_mi-router-4a-gigabit-v2.dts b/target/linux/ramips/dts/mt7621_xiaomi_mi-router-4a-gigabit-v2.dts
index 719d430fd87456..779b87816124af 100644
--- a/target/linux/ramips/dts/mt7621_xiaomi_mi-router-4a-gigabit-v2.dts
+++ b/target/linux/ramips/dts/mt7621_xiaomi_mi-router-4a-gigabit-v2.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "mt7621_xiaomi_mi-router-4a-common.dtsi"
 
 / {
@@ -14,22 +16,26 @@
 		compatible = "gpio-leds";
 
 		led_status_blue: status_blue {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status_yellow: status_yellow {
-			label = "yellow:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_YELLOW>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 		};
 
 		wan_blue {
-			label = "blue:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		};
 
 		wan_yellow {
-			label = "yellow:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_YELLOW>;
 			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/mt7621_xiaomi_mi-router-ac2100.dts b/target/linux/ramips/dts/mt7621_xiaomi_mi-router-ac2100.dts
index 6cca16a79b5298..d3221315bfb226 100644
--- a/target/linux/ramips/dts/mt7621_xiaomi_mi-router-ac2100.dts
+++ b/target/linux/ramips/dts/mt7621_xiaomi_mi-router-ac2100.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "mt7621_xiaomi_router-ac2100.dtsi"
 
 / {
@@ -18,22 +20,26 @@
 		compatible = "gpio-leds";
 
 		wan_yellow {
-			label = "yellow:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_YELLOW>;
 			gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
 		};
 
 		wan_blue {
-			label = "blue:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status_yellow: status_yellow {
-			label = "yellow:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_YELLOW>;
 			gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status_blue: status_blue {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/mt7621_xiaomi_mi-router-cr660x.dtsi b/target/linux/ramips/dts/mt7621_xiaomi_mi-router-cr660x.dtsi
index d1a2c08c6dee62..ef637278afb5fd 100644
--- a/target/linux/ramips/dts/mt7621_xiaomi_mi-router-cr660x.dtsi
+++ b/target/linux/ramips/dts/mt7621_xiaomi_mi-router-cr660x.dtsi
@@ -85,7 +85,7 @@
 			read-only;
 		};
 
-		factory: partition@100000 {
+		partition@100000 {
 			label = "Factory";
 			reg = <0x100000 0x80000>;
 			read-only;
diff --git a/target/linux/ramips/dts/mt7621_xiaomi_nand_128m.dtsi b/target/linux/ramips/dts/mt7621_xiaomi_nand_128m.dtsi
index 3a877e9bec3415..cd39968b9cdc33 100644
--- a/target/linux/ramips/dts/mt7621_xiaomi_nand_128m.dtsi
+++ b/target/linux/ramips/dts/mt7621_xiaomi_nand_128m.dtsi
@@ -46,7 +46,7 @@
 			read-only;
 		};
 
-		factory: partition@100000 {
+		partition@100000 {
 			label = "factory";
 			reg = <0x100000 0x40000>;
 			read-only;
diff --git a/target/linux/ramips/dts/mt7621_xiaomi_redmi-router-ac2100.dts b/target/linux/ramips/dts/mt7621_xiaomi_redmi-router-ac2100.dts
index 4299de318bf19c..9ccfd25d57640e 100644
--- a/target/linux/ramips/dts/mt7621_xiaomi_redmi-router-ac2100.dts
+++ b/target/linux/ramips/dts/mt7621_xiaomi_redmi-router-ac2100.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "mt7621_xiaomi_router-ac2100.dtsi"
 
 / {
@@ -18,22 +20,26 @@
 		compatible = "gpio-leds";
 
 		led_status_amber: status_amber {
-			label = "amber:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status_white: status_white {
-			label = "white:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
 		};
 
 		wan_amber {
-			label = "amber:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
 		};
 
 		wan_white {
-			label = "white:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/mt7621_xiaoyu_xy-c5.dts b/target/linux/ramips/dts/mt7621_xiaoyu_xy-c5.dts
index 7bb90e542ec230..f1227552e881a4 100644
--- a/target/linux/ramips/dts/mt7621_xiaoyu_xy-c5.dts
+++ b/target/linux/ramips/dts/mt7621_xiaoyu_xy-c5.dts
@@ -66,7 +66,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_xzwifi_creativebox-v1.dts b/target/linux/ramips/dts/mt7621_xzwifi_creativebox-v1.dts
index 147713ddce19cf..6bf806722af0a2 100644
--- a/target/linux/ramips/dts/mt7621_xzwifi_creativebox-v1.dts
+++ b/target/linux/ramips/dts/mt7621_xzwifi_creativebox-v1.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "xzwifi,creativebox-v1", "mediatek,mt7621-soc";
@@ -24,7 +25,8 @@
 		compatible = "gpio-leds";
 
 		power {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 31 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
@@ -112,7 +114,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_youhua_wr1200js.dts b/target/linux/ramips/dts/mt7621_youhua_wr1200js.dts
index e715237a401243..c47e34a5d69c84 100644
--- a/target/linux/ramips/dts/mt7621_youhua_wr1200js.dts
+++ b/target/linux/ramips/dts/mt7621_youhua_wr1200js.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "youhua,wr1200js", "mediatek,mt7621-soc";
@@ -25,12 +26,14 @@
 		};
 
 		led_wps: wps {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
 		};
 
 		usb {
-			label = "blue:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&xhci_ehci_port1>, <&ehci_port2>;
 			linux,default-trigger = "usbport";
@@ -85,7 +88,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_youku_yk-l2.dts b/target/linux/ramips/dts/mt7621_youku_yk-l2.dts
index 98d2e6892254b0..9f4e8cf1ce4f1b 100644
--- a/target/linux/ramips/dts/mt7621_youku_yk-l2.dts
+++ b/target/linux/ramips/dts/mt7621_youku_yk-l2.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "youku,yk-l2", "mediatek,mt7621-soc";
@@ -24,18 +25,21 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		led_wps: wps {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		};
 
 		usb {
-			label = "blue:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&xhci_ehci_port1>, <&ehci_port2>;
 			linux,default-trigger = "usbport";
@@ -88,7 +92,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_yuncore_ax820.dts b/target/linux/ramips/dts/mt7621_yuncore_ax820.dts
index bca9498be8059f..0cdad1bfe5f32a 100644
--- a/target/linux/ramips/dts/mt7621_yuncore_ax820.dts
+++ b/target/linux/ramips/dts/mt7621_yuncore_ax820.dts
@@ -111,7 +111,7 @@
 			 * firmware, so we do not use it either
 			 */
 
-			factory: partition@50000 {
+			partition@50000 {
 				label = "Factory";
 				reg = <0x50000 0x40000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_yuncore_fap640.dts b/target/linux/ramips/dts/mt7621_yuncore_fap640.dts
index c61189c4bc1927..2cc3435a894e30 100644
--- a/target/linux/ramips/dts/mt7621_yuncore_fap640.dts
+++ b/target/linux/ramips/dts/mt7621_yuncore_fap640.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "yuncore,fap640", "mediatek,mt7621-soc";
@@ -25,22 +26,26 @@
 		compatible = "gpio-leds";
 
 		led_status_green: status_green {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status_red: status_red {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status_blue: status_blue {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&switch0 12 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "mt7530-0:04:link";
 		};
@@ -119,7 +124,7 @@
 			 * firmware, so we do not use it either
 			 */
 
-			factory: partition@50000 {
+			partition@50000 {
 				label = "Factory";
 				reg = <0x50000 0x40000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_yuncore_fap690.dts b/target/linux/ramips/dts/mt7621_yuncore_fap690.dts
index caebe0b589a3ec..9f7ca430922f36 100644
--- a/target/linux/ramips/dts/mt7621_yuncore_fap690.dts
+++ b/target/linux/ramips/dts/mt7621_yuncore_fap690.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "yuncore,fap690", "mediatek,mt7621-soc";
@@ -25,17 +26,20 @@
 		compatible = "gpio-leds";
 
 		led_status_green: status_green {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status_red: status_red {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status_blue: status_blue {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -89,7 +93,7 @@
 			 * firmware, so we do not use it either
 			 */
 
-			factory: partition@50000 {
+			partition@50000 {
 				label = "Factory";
 				reg = <0x50000 0x40000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_zbtlink_zbt-we1326.dts b/target/linux/ramips/dts/mt7621_zbtlink_zbt-we1326.dts
index 2c78dea114f6e8..e15c676c8aefd3 100644
--- a/target/linux/ramips/dts/mt7621_zbtlink_zbt-we1326.dts
+++ b/target/linux/ramips/dts/mt7621_zbtlink_zbt-we1326.dts
@@ -58,7 +58,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_zbtlink_zbt-we3526.dts b/target/linux/ramips/dts/mt7621_zbtlink_zbt-we3526.dts
index 571b50d3c770d3..dfa49a2bc5f6bf 100644
--- a/target/linux/ramips/dts/mt7621_zbtlink_zbt-we3526.dts
+++ b/target/linux/ramips/dts/mt7621_zbtlink_zbt-we3526.dts
@@ -55,7 +55,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
@@ -83,7 +83,7 @@
 				};
 			};
 
-			firmware: partition@50000 {
+			partition@50000 {
 				compatible = "denx,uimage";
 				label = "firmware";
 				reg = <0x50000 0xfb0000>;
diff --git a/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg1602-v04.dtsi b/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg1602-v04.dtsi
index 1a3387326a6b90..bbf121036c2147 100644
--- a/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg1602-v04.dtsi
+++ b/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg1602-v04.dtsi
@@ -110,7 +110,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg1602.dtsi b/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg1602.dtsi
index e92982a8796b8f..b0182ee8961a41 100644
--- a/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg1602.dtsi
+++ b/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg1602.dtsi
@@ -109,7 +109,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg1608.dtsi b/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg1608.dtsi
index d1697060a84d42..321274bb15ccfe 100644
--- a/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg1608.dtsi
+++ b/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg1608.dtsi
@@ -83,7 +83,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg2626.dts b/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg2626.dts
index 3756baa14efe01..af91279cfaf695 100644
--- a/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg2626.dts
+++ b/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg2626.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "zbtlink,zbt-wg2626", "mediatek,mt7621-soc";
@@ -32,7 +33,8 @@
 		compatible = "gpio-leds";
 
 		led_status: status {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 24 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -71,7 +73,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg3526.dtsi b/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg3526.dtsi
index 87ed1c71297058..8b6739e8010ca8 100644
--- a/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg3526.dtsi
+++ b/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg3526.dtsi
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "zbtlink,zbt-wg3526", "mediatek,mt7621-soc";
@@ -32,7 +33,8 @@
 		compatible = "gpio-leds";
 
 		led_status: status {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 24 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -71,7 +73,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7621_zyxel_lte3301-plus.dts b/target/linux/ramips/dts/mt7621_zyxel_lte3301-plus.dts
index abbb61d5341880..edc861db61a616 100644
--- a/target/linux/ramips/dts/mt7621_zyxel_lte3301-plus.dts
+++ b/target/linux/ramips/dts/mt7621_zyxel_lte3301-plus.dts
@@ -125,7 +125,7 @@
 			label = "uboot_env";
 			reg = <0x80000 0x80000>; /* 64 KB */
 		};
-		factory: partition@100000 {
+		partition@100000 {
 			label = "factory";
 			reg = <0x100000 0x40000>;
 
diff --git a/target/linux/ramips/dts/mt7621_zyxel_lte5398-m904.dts b/target/linux/ramips/dts/mt7621_zyxel_lte5398-m904.dts
index 307819e746e903..ca8adfe10efedf 100644
--- a/target/linux/ramips/dts/mt7621_zyxel_lte5398-m904.dts
+++ b/target/linux/ramips/dts/mt7621_zyxel_lte5398-m904.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "zyxel,lte5398-m904", "mediatek,mt7621-soc";
@@ -37,12 +38,14 @@
 		compatible = "gpio-leds";
 
 		led_power_green: power_green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
 		};
 
 		power_blue {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "usbport";
 			trigger-sources = <&ehci_port2>;
@@ -117,7 +120,7 @@
 			reg = <0x80000 0x80000>;
 		};
 
-		factory: partition@100000 {
+		partition@100000 {
 			label = "Factory";
 			reg = <0x100000 0x40000>;
 			read-only;
diff --git a/target/linux/ramips/dts/mt7621_zyxel_nr7101.dts b/target/linux/ramips/dts/mt7621_zyxel_nr7101.dts
index 2ceb6228b26040..756d4bd6e6c735 100644
--- a/target/linux/ramips/dts/mt7621_zyxel_nr7101.dts
+++ b/target/linux/ramips/dts/mt7621_zyxel_nr7101.dts
@@ -88,7 +88,7 @@
 			reg = <0x80000 0x80000>;
 		};
 
-		factory: partition@100000 {
+		partition@100000 {
 			label = "Factory";
 			reg = <0x100000 0x40000>;
 			read-only;
diff --git a/target/linux/ramips/dts/mt7621_zyxel_nwa-ax.dtsi b/target/linux/ramips/dts/mt7621_zyxel_nwa-ax.dtsi
index 6272b178ec39c5..499d166890af67 100644
--- a/target/linux/ramips/dts/mt7621_zyxel_nwa-ax.dtsi
+++ b/target/linux/ramips/dts/mt7621_zyxel_nwa-ax.dtsi
@@ -36,7 +36,7 @@
 			read-only;
 		};
 
-		factory: partition@100000 {
+		partition@100000 {
 			label = "factory";
 			reg = <0x100000 0x80000>;
 			read-only;
@@ -106,7 +106,7 @@
 			reg = <0x7700000 0x80000>;
 		};
 
-		mrd: partition@7780000 {
+		partition@7780000 {
 			label = "mrd";
 			reg = <0x7780000 0x80000>;
 			read-only;
diff --git a/target/linux/ramips/dts/mt7621_zyxel_wap6805.dts b/target/linux/ramips/dts/mt7621_zyxel_wap6805.dts
index 2f6654da5c3e87..eabfcc2ef0636f 100644
--- a/target/linux/ramips/dts/mt7621_zyxel_wap6805.dts
+++ b/target/linux/ramips/dts/mt7621_zyxel_wap6805.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "zyxel,wap6805", "mediatek,mt7621-soc";
@@ -21,7 +22,8 @@
 		compatible = "gpio-leds";
 
 		led_status_red: status_red {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 4 GPIO_ACTIVE_HIGH>;
 		};
 
@@ -31,7 +33,8 @@
 		};
 
 		led_status_green: status_green {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 13 GPIO_ACTIVE_HIGH>;
 		};
 	};
@@ -73,7 +76,7 @@
 			read-only;
 		};
 
-		factory: partition@200000 {
+		partition@200000 {
 			label = "Factory";
 			reg = <0x200000 0x100000>;
 			read-only;
diff --git a/target/linux/ramips/dts/mt7621_zyxel_wsm20.dts b/target/linux/ramips/dts/mt7621_zyxel_wsm20.dts
index a283b55c11701d..b82a8669b3f39c 100644
--- a/target/linux/ramips/dts/mt7621_zyxel_wsm20.dts
+++ b/target/linux/ramips/dts/mt7621_zyxel_wsm20.dts
@@ -102,7 +102,7 @@
 			label = "Config";
 		};
 
-		factory: partition@200000 {
+		partition@200000 {
 			reg = <0x200000 0x1c0000>;
 			label = "Factory";
 			read-only;
diff --git a/target/linux/ramips/dts/mt7628an_alfa-network_awusfree1.dts b/target/linux/ramips/dts/mt7628an_alfa-network_awusfree1.dts
index 641844ccc0d864..70616a478bf41f 100644
--- a/target/linux/ramips/dts/mt7628an_alfa-network_awusfree1.dts
+++ b/target/linux/ramips/dts/mt7628an_alfa-network_awusfree1.dts
@@ -8,6 +8,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "alfa-network,awusfree1", "mediatek,mt7628an-soc";
@@ -43,7 +44,8 @@
 		};
 
 		wlan {
-			label = "blue:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -113,7 +115,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_asus_rt-ac1200.dts b/target/linux/ramips/dts/mt7628an_asus_rt-ac1200.dts
index abb86456da8544..833a44cc712471 100644
--- a/target/linux/ramips/dts/mt7628an_asus_rt-ac1200.dts
+++ b/target/linux/ramips/dts/mt7628an_asus_rt-ac1200.dts
@@ -2,6 +2,8 @@
 // Copyright (c) 2022 Ray Wang
 // Copyright (c) 2022 Ivan Pavlov
 
+#include <dt-bindings/leds/common.h>
+
 #include "mt7628an_asus_rt-ac1200.dtsi"
 
 / {
@@ -12,7 +14,8 @@
 		compatible = "gpio-leds";
 
 		usb {
-			label = "blue:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 6 GPIO_ACTIVE_HIGH>;
 			trigger-sources = <&ohci_port1>, <&ehci_port1>;
 			linux,default-trigger = "usbport";
diff --git a/target/linux/ramips/dts/mt7628an_asus_rt-ac1200.dtsi b/target/linux/ramips/dts/mt7628an_asus_rt-ac1200.dtsi
index e91f1b60297913..e56648d4d1351b 100644
--- a/target/linux/ramips/dts/mt7628an_asus_rt-ac1200.dtsi
+++ b/target/linux/ramips/dts/mt7628an_asus_rt-ac1200.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -34,7 +35,8 @@
 		compatible = "gpio-leds";
 
 		led_wps: wps {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
 		};
 
@@ -55,7 +57,7 @@
 		spi-max-frequency = <58000000>;
 		m25p,fast-read;
 
-		partitions: partitions {
+		partitions {
 			compatible = "fixed-partitions";
 			#address-cells = <1>;
 			#size-cells = <1>;
@@ -72,7 +74,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_asus_rt-n1x.dtsi b/target/linux/ramips/dts/mt7628an_asus_rt-n1x.dtsi
index aa642da11fdd50..fc911eb99739f2 100644
--- a/target/linux/ramips/dts/mt7628an_asus_rt-n1x.dtsi
+++ b/target/linux/ramips/dts/mt7628an_asus_rt-n1x.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -27,23 +28,27 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 43 GPIO_ACTIVE_LOW>;
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -74,7 +79,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_buffalo_wcr-1166ds.dts b/target/linux/ramips/dts/mt7628an_buffalo_wcr-1166ds.dts
index 1b9e0047ccc735..b6d2416f604bd9 100644
--- a/target/linux/ramips/dts/mt7628an_buffalo_wcr-1166ds.dts
+++ b/target/linux/ramips/dts/mt7628an_buffalo_wcr-1166ds.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "buffalo,wcr-1166ds", "mediatek,mt7628an-soc";
@@ -76,7 +77,8 @@
 		};
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -140,7 +142,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_comfast_cf-wr617ac.dts b/target/linux/ramips/dts/mt7628an_comfast_cf-wr617ac.dts
index 1d6304cfa771ad..9757e1119b26b8 100644
--- a/target/linux/ramips/dts/mt7628an_comfast_cf-wr617ac.dts
+++ b/target/linux/ramips/dts/mt7628an_comfast_cf-wr617ac.dts
@@ -4,6 +4,7 @@
 #include "mt7628an.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "comfast,cf-wr617ac", "mediatek,mt7628an-soc";
@@ -21,11 +22,13 @@
 	leds {
 		compatible = "gpio-leds";
 		led_status_blue: status_blue {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
 		};
 		led_status_red: status_red {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -69,7 +72,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_comfast_cf-wr758ac.dtsi b/target/linux/ramips/dts/mt7628an_comfast_cf-wr758ac.dtsi
index 9cab562bda2d01..470c0d5cff535d 100644
--- a/target/linux/ramips/dts/mt7628an_comfast_cf-wr758ac.dtsi
+++ b/target/linux/ramips/dts/mt7628an_comfast_cf-wr758ac.dtsi
@@ -84,7 +84,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_cudy_wr1000.dts b/target/linux/ramips/dts/mt7628an_cudy_wr1000.dts
index 883459d2f303ec..f7746febb5793e 100644
--- a/target/linux/ramips/dts/mt7628an_cudy_wr1000.dts
+++ b/target/linux/ramips/dts/mt7628an_cudy_wr1000.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "cudy,wr1000", "mediatek,mt7628an-soc";
@@ -46,7 +47,8 @@
 		};
 
 		wan {
-			label = "blue:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 39 GPIO_ACTIVE_LOW>;
 		};
 
@@ -57,7 +59,8 @@
 		};
 
 		led_wps: wps {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -88,7 +91,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_d-team_pbr-d1.dts b/target/linux/ramips/dts/mt7628an_d-team_pbr-d1.dts
index f5e9a169d4da7e..940104d47eea69 100644
--- a/target/linux/ramips/dts/mt7628an_d-team_pbr-d1.dts
+++ b/target/linux/ramips/dts/mt7628an_d-team_pbr-d1.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "d-team,pbr-d1", "mediatek,mt7628an-soc";
@@ -26,14 +27,16 @@
 		compatible = "gpio-leds";
 
 		usb {
-			label = "orange:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&ohci_port1>, <&ehci_port1>;
 			linux,default-trigger = "usbport";
 		};
 
 		led_power: power {
-			label = "orange:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
@@ -112,7 +115,7 @@
 				reg = <0x30000 0x10000>;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_dlink_dap-1325-a1.dts b/target/linux/ramips/dts/mt7628an_dlink_dap-1325-a1.dts
index 3ad34c51c1a9e3..24e69a2b35158e 100644
--- a/target/linux/ramips/dts/mt7628an_dlink_dap-1325-a1.dts
+++ b/target/linux/ramips/dts/mt7628an_dlink_dap-1325-a1.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "dlink,dap-1325-a1", "mediatek,mt7628an-soc";
@@ -20,12 +21,14 @@
 		compatible = "gpio-leds";
 
 		led_status_red: status_red {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status_green: status_green {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 		};
 
@@ -114,7 +117,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_duzun_dm06.dts b/target/linux/ramips/dts/mt7628an_duzun_dm06.dts
index e37b90d38ee684..59d411f88fb15c 100644
--- a/target/linux/ramips/dts/mt7628an_duzun_dm06.dts
+++ b/target/linux/ramips/dts/mt7628an_duzun_dm06.dts
@@ -116,7 +116,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_elecom_wrc-1167fs.dts b/target/linux/ramips/dts/mt7628an_elecom_wrc-1167fs.dts
index 9d8b360c6a3faf..afe66daf9c27ac 100644
--- a/target/linux/ramips/dts/mt7628an_elecom_wrc-1167fs.dts
+++ b/target/linux/ramips/dts/mt7628an_elecom_wrc-1167fs.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "elecom,wrc-1167fs", "mediatek,mt7628an-soc";
@@ -20,7 +21,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
 		};
 
@@ -31,7 +33,8 @@
 		};
 
 		wps {
-			label = "red:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
 		};
 
@@ -41,7 +44,8 @@
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 40 GPIO_ACTIVE_LOW>;
 		};
 
@@ -101,7 +105,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_glinet_gl-mt300n-v2.dts b/target/linux/ramips/dts/mt7628an_glinet_gl-mt300n-v2.dts
index d84290d4c12354..7c480ade989b79 100644
--- a/target/linux/ramips/dts/mt7628an_glinet_gl-mt300n-v2.dts
+++ b/target/linux/ramips/dts/mt7628an_glinet_gl-mt300n-v2.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 /{
 	compatible = "glinet,gl-mt300n-v2", "mediatek,mt7628an-soc";
@@ -23,18 +24,21 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			default-state = "on";
 			gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 43 GPIO_ACTIVE_LOW>;
 		};
 
 		wlan {
-			label = "red:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -117,7 +121,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_glinet_vixmini_microuter.dtsi b/target/linux/ramips/dts/mt7628an_glinet_vixmini_microuter.dtsi
index a40be00887f185..94a1e15f243d6f 100644
--- a/target/linux/ramips/dts/mt7628an_glinet_vixmini_microuter.dtsi
+++ b/target/linux/ramips/dts/mt7628an_glinet_vixmini_microuter.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -23,12 +24,14 @@
 		compatible = "gpio-leds";
 
 		led_power_blue: power {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
 		};
 
 		wlan {
-			label = "white:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
@@ -72,7 +75,7 @@
 		reg = <0>;
 		spi-max-frequency = <10000000>;
 
-		partitions: partitions {
+		partitions {
 			compatible = "fixed-partitions";
 			#address-cells = <1>;
 			#size-cells = <1>;
@@ -89,7 +92,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_hak5_wifi-pineapple-mk7.dts b/target/linux/ramips/dts/mt7628an_hak5_wifi-pineapple-mk7.dts
index aebbc7fa888b75..51731c3c649b12 100644
--- a/target/linux/ramips/dts/mt7628an_hak5_wifi-pineapple-mk7.dts
+++ b/target/linux/ramips/dts/mt7628an_hak5_wifi-pineapple-mk7.dts
@@ -100,7 +100,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_hilink_hlk-7628n.dts b/target/linux/ramips/dts/mt7628an_hilink_hlk-7628n.dts
index 69e22f6dd7d673..c84e820b809c57 100644
--- a/target/linux/ramips/dts/mt7628an_hilink_hlk-7628n.dts
+++ b/target/linux/ramips/dts/mt7628an_hilink_hlk-7628n.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "hilink,hlk-7628n", "mediatek,mt7628an-soc";
@@ -23,7 +24,8 @@
 		compatible = "gpio-leds";
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -66,7 +68,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_hilink_hlk-7688a.dts b/target/linux/ramips/dts/mt7628an_hilink_hlk-7688a.dts
index 121a24b5025052..f347ec94a6e96b 100644
--- a/target/linux/ramips/dts/mt7628an_hilink_hlk-7688a.dts
+++ b/target/linux/ramips/dts/mt7628an_hilink_hlk-7688a.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "hilink,hlk-7688a", "mediatek,mt7628an-soc";
@@ -29,7 +30,8 @@
 		compatible = "gpio-leds";
 
 		led_wlan: wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
@@ -80,7 +82,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_hiwifi_hc5x61a.dtsi b/target/linux/ramips/dts/mt7628an_hiwifi_hc5x61a.dtsi
index 034a6de6c2dfb0..42bb804c6571de 100644
--- a/target/linux/ramips/dts/mt7628an_hiwifi_hc5x61a.dtsi
+++ b/target/linux/ramips/dts/mt7628an_hiwifi_hc5x61a.dtsi
@@ -56,7 +56,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
@@ -96,7 +96,7 @@
 				read-only;
 			};
 
-			bdinfo: partition@fe0000 {
+			partition@fe0000 {
 				label = "bdinfo";
 				reg = <0xfe0000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_iptime.dtsi b/target/linux/ramips/dts/mt7628an_iptime.dtsi
index 9c98c6f5ca10e2..f190215a439066 100644
--- a/target/linux/ramips/dts/mt7628an_iptime.dtsi
+++ b/target/linux/ramips/dts/mt7628an_iptime.dtsi
@@ -42,7 +42,7 @@
 			#address-cells = <1>;
 			#size-cells = <1>;
 
-			uboot: partition@0 {
+			partition@0 {
 				label = "u-boot";
 				reg = <0x0 0x20000>;
 				read-only;
@@ -64,7 +64,7 @@
 				read-only;
 			};
 
-			factory: partition@30000 {
+			partition@30000 {
 				label = "factory";
 				reg = <0x30000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_iptime_a3.dts b/target/linux/ramips/dts/mt7628an_iptime_a3.dts
index d90a075af564ee..405c10ffb71d46 100644
--- a/target/linux/ramips/dts/mt7628an_iptime_a3.dts
+++ b/target/linux/ramips/dts/mt7628an_iptime_a3.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "mt7628an_iptime.dtsi"
 
 / {
@@ -17,12 +19,14 @@
 		compatible = "gpio-leds";
 
 		led_cpu: cpu {
-			label = "blue:cpu";
+			function = LED_FUNCTION_CPU;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 		};
 
 		wlan {
-			label = "blue:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ramips/dts/mt7628an_iptime_a604m.dts b/target/linux/ramips/dts/mt7628an_iptime_a604m.dts
index 2f626f1adf7031..cbc2f3027f9f49 100644
--- a/target/linux/ramips/dts/mt7628an_iptime_a604m.dts
+++ b/target/linux/ramips/dts/mt7628an_iptime_a604m.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "mt7628an_iptime.dtsi"
 
 / {
@@ -23,7 +25,8 @@
 		};
 
 		led_cpu: cpu {
-			label = "blue:cpu";
+			function = LED_FUNCTION_CPU;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ramips/dts/mt7628an_jotale_js76x8.dtsi b/target/linux/ramips/dts/mt7628an_jotale_js76x8.dtsi
index 643f599246c045..96d36f66e07908 100644
--- a/target/linux/ramips/dts/mt7628an_jotale_js76x8.dtsi
+++ b/target/linux/ramips/dts/mt7628an_jotale_js76x8.dtsi
@@ -80,7 +80,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_keenetic_kn-1613.dts b/target/linux/ramips/dts/mt7628an_keenetic_kn-1613.dts
index 475426896619a7..4b124c92954245 100644
--- a/target/linux/ramips/dts/mt7628an_keenetic_kn-1613.dts
+++ b/target/linux/ramips/dts/mt7628an_keenetic_kn-1613.dts
@@ -3,6 +3,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "keenetic,kn-1613", "mediatek,mt7628an-soc";
@@ -23,7 +24,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 		};
 
@@ -112,7 +114,7 @@
 		reg = <0>;
 		spi-max-frequency = <32000000>;
 
-		partitions: partitions {
+		partitions {
 			compatible = "fixed-partitions";
 			#address-cells = <1>;
 			#size-cells = <1>;
@@ -129,7 +131,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "rf-eeprom";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_kroks.dtsi b/target/linux/ramips/dts/mt7628an_kroks.dtsi
index bfe29398a9f36a..db5ea4f32c0512 100644
--- a/target/linux/ramips/dts/mt7628an_kroks.dtsi
+++ b/target/linux/ramips/dts/mt7628an_kroks.dtsi
@@ -49,7 +49,7 @@
 		spi-max-frequency = <25000000>;
 		m25p,fast-read;
 
-		partitions: partitions {
+		partitions {
 			compatible = "fixed-partitions";
 			#address-cells = <1>;
 			#size-cells = <1>;
@@ -64,7 +64,7 @@
 				reg = <0x30000 0x10000>;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 
diff --git a/target/linux/ramips/dts/mt7628an_kroks_kndrt31r16.dts b/target/linux/ramips/dts/mt7628an_kroks_kndrt31r16.dts
index b0b41f0420d91a..8e1c6d81740f25 100644
--- a/target/linux/ramips/dts/mt7628an_kroks_kndrt31r16.dts
+++ b/target/linux/ramips/dts/mt7628an_kroks_kndrt31r16.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "mt7628an_kroks.dtsi"
 
 / {
@@ -8,7 +10,8 @@
 
 	leds {
 		status {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 2 GPIO_ACTIVE_HIGH>;
 		};
 
diff --git a/target/linux/ramips/dts/mt7628an_kroks_kndrt31r19.dts b/target/linux/ramips/dts/mt7628an_kroks_kndrt31r19.dts
index eb36c986f6d4c2..d641fa078f9f44 100644
--- a/target/linux/ramips/dts/mt7628an_kroks_kndrt31r19.dts
+++ b/target/linux/ramips/dts/mt7628an_kroks_kndrt31r19.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "mt7628an_kroks.dtsi"
 
 / {
@@ -8,7 +10,8 @@
 
 	leds {
 		status {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 		};
 
 		wifi {
diff --git a/target/linux/ramips/dts/mt7628an_linksys_e5400.dts b/target/linux/ramips/dts/mt7628an_linksys_e5400.dts
index 26ff86dac2d255..ce5099e9b0fe58 100644
--- a/target/linux/ramips/dts/mt7628an_linksys_e5400.dts
+++ b/target/linux/ramips/dts/mt7628an_linksys_e5400.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "linksys,e5400", "mediatek,mt7628an-soc";
@@ -46,7 +47,8 @@
 		compatible = "gpio-leds";
 
 		led_wps: wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -77,7 +79,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_mediatek_linkit-smart-7688.dts b/target/linux/ramips/dts/mt7628an_mediatek_linkit-smart-7688.dts
index 1bd7f8e6daa15e..37b4b9baa5c3f7 100644
--- a/target/linux/ramips/dts/mt7628an_mediatek_linkit-smart-7688.dts
+++ b/target/linux/ramips/dts/mt7628an_mediatek_linkit-smart-7688.dts
@@ -107,7 +107,7 @@
 				reg = <0x30000 0x10000>;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_mediatek_mt7628an-eval-board.dts b/target/linux/ramips/dts/mt7628an_mediatek_mt7628an-eval-board.dts
index 7f19ab6947591a..5428ddc62edb97 100644
--- a/target/linux/ramips/dts/mt7628an_mediatek_mt7628an-eval-board.dts
+++ b/target/linux/ramips/dts/mt7628an_mediatek_mt7628an-eval-board.dts
@@ -37,7 +37,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_mercury_mac1200r-v2.dts b/target/linux/ramips/dts/mt7628an_mercury_mac1200r-v2.dts
index 074011fbb9b2c4..e189dbf5ffb48b 100644
--- a/target/linux/ramips/dts/mt7628an_mercury_mac1200r-v2.dts
+++ b/target/linux/ramips/dts/mt7628an_mercury_mac1200r-v2.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "mercury,mac1200r-v2", "mediatek,mt7628an-soc";
@@ -18,7 +19,8 @@
 		compatible = "gpio-leds";
 
 		led_status: status {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -42,7 +44,7 @@
 				reg = <0x0 0x1d800>;
 			};
 
-			factory: partition@1d800 {
+			partition@1d800 {
 				label = "factory_info";
 				reg = <0x1d800 0x800>;
 				read-only;
@@ -62,7 +64,7 @@
 				};
 			};
 
-			art: partition@1e000 {
+			partition@1e000 {
 				label = "art";
 				reg = <0x1e000 0x2000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_minew_g1-c.dts b/target/linux/ramips/dts/mt7628an_minew_g1-c.dts
index a1b40e09d0134d..3912f23a9e2247 100644
--- a/target/linux/ramips/dts/mt7628an_minew_g1-c.dts
+++ b/target/linux/ramips/dts/mt7628an_minew_g1-c.dts
@@ -104,7 +104,7 @@
 				reg = <0x30000 0x10000>;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_motorola_mwr03.dts b/target/linux/ramips/dts/mt7628an_motorola_mwr03.dts
index ebaa4326aea988..1c57fce196bb84 100644
--- a/target/linux/ramips/dts/mt7628an_motorola_mwr03.dts
+++ b/target/linux/ramips/dts/mt7628an_motorola_mwr03.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Motorola MWR03";
@@ -30,12 +31,14 @@
 		compatible = "gpio-leds";
 
 		led_status_orange: status_orange {
-			label = "orange:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status_white: status_white {
-			label = "white:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -67,7 +70,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_netgear_r6xxx.dtsi b/target/linux/ramips/dts/mt7628an_netgear_r6xxx.dtsi
index 98d132e891f1ab..7e75950acbf810 100644
--- a/target/linux/ramips/dts/mt7628an_netgear_r6xxx.dtsi
+++ b/target/linux/ramips/dts/mt7628an_netgear_r6xxx.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -27,12 +28,14 @@
 		compatible = "gpio-leds";
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 43 GPIO_ACTIVE_LOW>;
 		};
 
@@ -48,12 +51,14 @@
 		};
 
 		wan_green {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 40 GPIO_ACTIVE_LOW>;
 		};
 
 		wan_orange {
-			label = "orange:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 39 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -79,7 +84,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x20000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_onion_omega2.dtsi b/target/linux/ramips/dts/mt7628an_onion_omega2.dtsi
index 001dc227bc0949..983c7fc03e9e6c 100644
--- a/target/linux/ramips/dts/mt7628an_onion_omega2.dtsi
+++ b/target/linux/ramips/dts/mt7628an_onion_omega2.dtsi
@@ -117,7 +117,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_oraybox_x1.dts b/target/linux/ramips/dts/mt7628an_oraybox_x1.dts
index 9f43e46fac0cc0..7e203e611f352c 100644
--- a/target/linux/ramips/dts/mt7628an_oraybox_x1.dts
+++ b/target/linux/ramips/dts/mt7628an_oraybox_x1.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "oraybox,x1", "mediatek,mt7628an-soc";
@@ -24,17 +25,20 @@
 		compatible = "gpio-leds";
 
 		led_status_blue: status-blue {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_status_red: status-red {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_status_white: status-white {
-			label = "white:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;
 		};
 	};
@@ -87,7 +91,7 @@
 				reg = <0x50000 0xf00000>;
 			};
 
-			bdinfo: partition@fe0000 {
+			partition@fe0000 {
 				label = "bdinfo";
 				reg = <0xfe0000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_rakwireless_rak633.dts b/target/linux/ramips/dts/mt7628an_rakwireless_rak633.dts
index 46dca444b57fe9..720d98e5e346b4 100644
--- a/target/linux/ramips/dts/mt7628an_rakwireless_rak633.dts
+++ b/target/linux/ramips/dts/mt7628an_rakwireless_rak633.dts
@@ -51,7 +51,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_ravpower_rp-wd009.dts b/target/linux/ramips/dts/mt7628an_ravpower_rp-wd009.dts
index 7c0e7551ce2aad..607787f68e13fd 100644
--- a/target/linux/ramips/dts/mt7628an_ravpower_rp-wd009.dts
+++ b/target/linux/ramips/dts/mt7628an_ravpower_rp-wd009.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "ravpower,rp-wd009", "mediatek,mt7628an-soc";
@@ -37,12 +38,14 @@
 		};
 
 		sd_white {
-			label = "white:sd";
+			function = LED_FUNCTION_SD;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 41 GPIO_ACTIVE_LOW>;
 		};
 
 		sd_red {
-			label = "red:sd";
+			function = LED_FUNCTION_SD;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -137,7 +140,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_skylab_skw92a.dts b/target/linux/ramips/dts/mt7628an_skylab_skw92a.dts
index fc111019a7d9f0..738041d071e80b 100644
--- a/target/linux/ramips/dts/mt7628an_skylab_skw92a.dts
+++ b/target/linux/ramips/dts/mt7628an_skylab_skw92a.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "skylab,skw92a", "mediatek,mt7628an-soc";
@@ -18,12 +19,14 @@
 		compatible = "gpio-leds";
 
 		led_power: wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -83,7 +86,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_tama_w06.dts b/target/linux/ramips/dts/mt7628an_tama_w06.dts
index dfe5192e12c5b9..ead678391167f3 100644
--- a/target/linux/ramips/dts/mt7628an_tama_w06.dts
+++ b/target/linux/ramips/dts/mt7628an_tama_w06.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "tama,w06", "mediatek,mt7628an-soc";
@@ -11,17 +12,20 @@
 		compatible = "gpio-leds";
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 43 GPIO_ACTIVE_LOW>;
 		};
 
 		wireless {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -74,7 +78,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_totolink_a3.dts b/target/linux/ramips/dts/mt7628an_totolink_a3.dts
index 246dfadddd897c..c8a4f91958118f 100644
--- a/target/linux/ramips/dts/mt7628an_totolink_a3.dts
+++ b/target/linux/ramips/dts/mt7628an_totolink_a3.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "mt7628an_iptime.dtsi"
 
 / {
@@ -17,12 +19,14 @@
 		compatible = "gpio-leds";
 
 		led_cpu: cpu {
-			label = "blue:cpu";
+			function = LED_FUNCTION_CPU;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 		};
 
 		wlan {
-			label = "blue:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ramips/dts/mt7628an_totolink_lr1200.dts b/target/linux/ramips/dts/mt7628an_totolink_lr1200.dts
index 83bde6b9ecfe89..8ee4dd33148860 100644
--- a/target/linux/ramips/dts/mt7628an_totolink_lr1200.dts
+++ b/target/linux/ramips/dts/mt7628an_totolink_lr1200.dts
@@ -143,7 +143,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_tplink_8m-split-uboot.dtsi b/target/linux/ramips/dts/mt7628an_tplink_8m-split-uboot.dtsi
index a5c9267c8d7ac6..8709cbc02dd3b1 100644
--- a/target/linux/ramips/dts/mt7628an_tplink_8m-split-uboot.dtsi
+++ b/target/linux/ramips/dts/mt7628an_tplink_8m-split-uboot.dtsi
@@ -52,7 +52,7 @@
 				read-only;
 			};
 
-			rom: partition@7d0000 {
+			partition@7d0000 {
 				label = "rom";
 				reg = <0x7d0000 0x10000>;
 				read-only;
@@ -75,7 +75,7 @@
 				reg = <0x7e0000 0x10000>;
 			};
 
-			radio: partition@7f0000 {
+			partition@7f0000 {
 				label = "radio";
 				reg = <0x7f0000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_tplink_archer-c20-v4.dts b/target/linux/ramips/dts/mt7628an_tplink_archer-c20-v4.dts
index 0d09e5434564d2..66e2cfdde778d4 100644
--- a/target/linux/ramips/dts/mt7628an_tplink_archer-c20-v4.dts
+++ b/target/linux/ramips/dts/mt7628an_tplink_archer-c20-v4.dts
@@ -1,3 +1,5 @@
+#include <dt-bindings/leds/common.h>
+
 #include "mt7628an_tplink_8m.dtsi"
 
 / {
@@ -15,22 +17,26 @@
 		compatible = "gpio-leds";
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 43 GPIO_ACTIVE_LOW>;
 		};
 
 		wan_orange {
-			label = "orange:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 		};
 
@@ -47,7 +53,8 @@
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 41 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/mt7628an_tplink_archer-c20-v5.dts b/target/linux/ramips/dts/mt7628an_tplink_archer-c20-v5.dts
index 93695660aebb7c..eef9635e16a4b1 100644
--- a/target/linux/ramips/dts/mt7628an_tplink_archer-c20-v5.dts
+++ b/target/linux/ramips/dts/mt7628an_tplink_archer-c20-v5.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "mt7628an_tplink_8m-split-uboot.dtsi"
 
 / {
@@ -33,7 +35,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
 		};
 
@@ -50,22 +53,26 @@
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
 		};
 
 		wan_green {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 43 GPIO_ACTIVE_LOW>;
 		};
 
 		wan_orange {
-			label = "orange:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 41 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/mt7628an_tplink_archer-c50-v3.dts b/target/linux/ramips/dts/mt7628an_tplink_archer-c50-v3.dts
index bfb39b3531ceba..c20eb3c46f80e3 100644
--- a/target/linux/ramips/dts/mt7628an_tplink_archer-c50-v3.dts
+++ b/target/linux/ramips/dts/mt7628an_tplink_archer-c50-v3.dts
@@ -1,3 +1,5 @@
+#include <dt-bindings/leds/common.h>
+
 #include "mt7628an_tplink_8m.dtsi"
 
 / {
@@ -31,22 +33,26 @@
 		compatible = "gpio-leds";
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 41 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 39 GPIO_ACTIVE_LOW>;
 		};
 
 		wan_orange {
-			label = "orange:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 40 GPIO_ACTIVE_LOW>;
 		};
 
@@ -61,7 +67,8 @@
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 43 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/mt7628an_tplink_archer-c50-v4.dts b/target/linux/ramips/dts/mt7628an_tplink_archer-c50-v4.dts
index 302a9d9c6a2aba..59a61e3d864417 100644
--- a/target/linux/ramips/dts/mt7628an_tplink_archer-c50-v4.dts
+++ b/target/linux/ramips/dts/mt7628an_tplink_archer-c50-v4.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "mt7628an_tplink_8m-split-uboot.dtsi"
 
 / {
@@ -33,7 +35,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 		};
 
@@ -48,22 +51,26 @@
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 41 GPIO_ACTIVE_LOW>;
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 39 GPIO_ACTIVE_LOW>;
 		};
 
 		wan_orange {
-			label = "orange:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 40 GPIO_ACTIVE_LOW>;
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 43 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/mt7628an_tplink_archer-c50-v6.dts b/target/linux/ramips/dts/mt7628an_tplink_archer-c50-v6.dts
index c3a890bc2ddd66..b2571a06d1ff0f 100644
--- a/target/linux/ramips/dts/mt7628an_tplink_archer-c50-v6.dts
+++ b/target/linux/ramips/dts/mt7628an_tplink_archer-c50-v6.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "mt7628an_tplink_8m-split-uboot.dtsi"
 
 / {
@@ -33,7 +35,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 		};
 
@@ -48,17 +51,20 @@
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 41 GPIO_ACTIVE_LOW>;
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 39 GPIO_ACTIVE_LOW>;
 		};
 
 		wan_orange {
-			label = "orange:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 40 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/mt7628an_tplink_re200.dtsi b/target/linux/ramips/dts/mt7628an_tplink_re200.dtsi
index 8826365bebfd20..3e22273d3f7c43 100644
--- a/target/linux/ramips/dts/mt7628an_tplink_re200.dtsi
+++ b/target/linux/ramips/dts/mt7628an_tplink_re200.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -38,7 +39,8 @@
 		compatible = "gpio-leds";
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
 		};
 
@@ -48,12 +50,14 @@
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 39 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 		};
 
 		wifi2g_green {
@@ -95,7 +99,7 @@
 				reg = <0x20000 0x7a0000>;
 			};
 
-			config: partition@7c0000 {
+			partition@7c0000 {
 				label = "config";
 				reg = <0x7c0000 0x30000>;
 				read-only;
@@ -113,7 +117,7 @@
 				};
 			};
 
-			radio: partition@7f0000 {
+			partition@7f0000 {
 				label = "radio";
 				reg = <0x7f0000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_tplink_re305-v1.dts b/target/linux/ramips/dts/mt7628an_tplink_re305-v1.dts
index 9e0bea7cd116a9..784ef6c4de82ad 100644
--- a/target/linux/ramips/dts/mt7628an_tplink_re305-v1.dts
+++ b/target/linux/ramips/dts/mt7628an_tplink_re305-v1.dts
@@ -32,7 +32,7 @@
 				reg = <0x20000 0x5e0000>;
 			};
 
-			config: partition@600000 {
+			partition@600000 {
 				label = "config";
 				reg = <0x600000 0x50000>;
 				read-only;
@@ -55,7 +55,7 @@
 				stock firmware so it is left out as well.
 			*/
 
-			radio: partition@7f0000 {
+			partition@7f0000 {
 				label = "radio";
 				reg = <0x7f0000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_tplink_re305-v3.dts b/target/linux/ramips/dts/mt7628an_tplink_re305-v3.dts
index d37febfbc87d00..35ab671bf5bcc4 100644
--- a/target/linux/ramips/dts/mt7628an_tplink_re305-v3.dts
+++ b/target/linux/ramips/dts/mt7628an_tplink_re305-v3.dts
@@ -32,7 +32,7 @@
 				reg = <0x20000 0x7a0000>;
 			};
 
-			config: partition@7c0000 {
+			partition@7c0000 {
 				label = "config";
 				reg = <0x7c0000 0x30000>;
 				read-only;
@@ -50,7 +50,7 @@
 				};
 			};
 
-			radio: partition@7f0000 {
+			partition@7f0000 {
 				label = "radio";
 				reg = <0x7f0000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_tplink_re305.dtsi b/target/linux/ramips/dts/mt7628an_tplink_re305.dtsi
index 029b9559117755..13f8d89fd2f9f9 100644
--- a/target/linux/ramips/dts/mt7628an_tplink_re305.dtsi
+++ b/target/linux/ramips/dts/mt7628an_tplink_re305.dtsi
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	aliases {
@@ -34,7 +35,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 39 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ramips/dts/mt7628an_tplink_tl-mr3020-v3.dts b/target/linux/ramips/dts/mt7628an_tplink_tl-mr3020-v3.dts
index 5f35cb4c7fac4e..ce434e601164bc 100644
--- a/target/linux/ramips/dts/mt7628an_tplink_tl-mr3020-v3.dts
+++ b/target/linux/ramips/dts/mt7628an_tplink_tl-mr3020-v3.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "tplink,tl-mr3020-v3", "mediatek,mt7628an-soc";
@@ -47,7 +48,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
@@ -60,18 +62,21 @@
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -120,7 +125,7 @@
 				read-only;
 			};
 
-			factory: partition@7d0000 {
+			partition@7d0000 {
 				label = "factory";
 				reg = <0x7d0000 0x30000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_tplink_tl-mr3420-v5.dts b/target/linux/ramips/dts/mt7628an_tplink_tl-mr3420-v5.dts
index 297e7b441d4f9e..fcdc1d6d373ad7 100644
--- a/target/linux/ramips/dts/mt7628an_tplink_tl-mr3420-v5.dts
+++ b/target/linux/ramips/dts/mt7628an_tplink_tl-mr3420-v5.dts
@@ -1,3 +1,5 @@
+#include <dt-bindings/leds/common.h>
+
 #include "mt7628an_tplink_8m.dtsi"
 
 / {
@@ -31,39 +33,46 @@
 		compatible = "gpio-leds";
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 41 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
 		};
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&ohci_port1>, <&ehci_port1>;
 			linux,default-trigger = "usbport";
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
 		};
 
 		wan_amber {
-			label = "amber:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/mt7628an_tplink_tl-mr6400-v4.dts b/target/linux/ramips/dts/mt7628an_tplink_tl-mr6400-v4.dts
index d0350f9924d985..21d1e483361eac 100644
--- a/target/linux/ramips/dts/mt7628an_tplink_tl-mr6400-v4.dts
+++ b/target/linux/ramips/dts/mt7628an_tplink_tl-mr6400-v4.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "mt7628an_tplink_8m.dtsi"
 
 / {
@@ -33,23 +35,27 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "white:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
 		};
 
 		wan {
-			label = "white:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 39 GPIO_ACTIVE_LOW>;
 		};
 
 		wlan {
-			label = "white:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 40 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
 
 		lan {
-			label = "white:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 41 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ramips/dts/mt7628an_tplink_tl-mr6400-v5.dts b/target/linux/ramips/dts/mt7628an_tplink_tl-mr6400-v5.dts
index f77f1acbf2a72b..1bd35fc33491a5 100644
--- a/target/linux/ramips/dts/mt7628an_tplink_tl-mr6400-v5.dts
+++ b/target/linux/ramips/dts/mt7628an_tplink_tl-mr6400-v5.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "mt7628an_tplink_8m.dtsi"
 
 / {
@@ -33,23 +35,27 @@
 		compatible = "gpio-leds";
 
 		wlan {
-			label = "white:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
 
 		lan {
-			label = "white:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power: power {
-			label = "white:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 39 GPIO_ACTIVE_LOW>;
 		};
 
 		wan {
-			label = "white:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 40 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ramips/dts/mt7628an_tplink_tl-wa801nd-v5.dts b/target/linux/ramips/dts/mt7628an_tplink_tl-wa801nd-v5.dts
index 44a483ed6d6b0c..01d5d756e38001 100644
--- a/target/linux/ramips/dts/mt7628an_tplink_tl-wa801nd-v5.dts
+++ b/target/linux/ramips/dts/mt7628an_tplink_tl-wa801nd-v5.dts
@@ -1,3 +1,5 @@
+#include <dt-bindings/leds/common.h>
+
 #include "mt7628an_tplink_8m.dtsi"
 
 / {
@@ -31,28 +33,33 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 36 GPIO_ACTIVE_LOW>;
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
 
 		wps_red {
-			label = "red:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 43 GPIO_ACTIVE_HIGH>;
 		};
 
 		wps_green {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 42 GPIO_ACTIVE_HIGH>;
 		};
 	};
diff --git a/target/linux/ramips/dts/mt7628an_tplink_tl-wr802n-v4.dts b/target/linux/ramips/dts/mt7628an_tplink_tl-wr802n-v4.dts
index 01cbba2024481f..b14eb64a22b05f 100644
--- a/target/linux/ramips/dts/mt7628an_tplink_tl-wr802n-v4.dts
+++ b/target/linux/ramips/dts/mt7628an_tplink_tl-wr802n-v4.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "mt7628an_tplink_8m.dtsi"
 
 / {
@@ -27,7 +29,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/mt7628an_tplink_tl-wr840n-v4.dts b/target/linux/ramips/dts/mt7628an_tplink_tl-wr840n-v4.dts
index e480395ffd46fb..408e5fd9563ffc 100644
--- a/target/linux/ramips/dts/mt7628an_tplink_tl-wr840n-v4.dts
+++ b/target/linux/ramips/dts/mt7628an_tplink_tl-wr840n-v4.dts
@@ -1,3 +1,5 @@
+#include <dt-bindings/leds/common.h>
+
 #include "mt7628an_tplink_8m.dtsi"
 
 / {
@@ -25,27 +27,32 @@
 		compatible = "gpio-leds";
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 41 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 36 GPIO_ACTIVE_LOW>;
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 43 GPIO_ACTIVE_LOW>;
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/mt7628an_tplink_tl-wr840n-v5.dts b/target/linux/ramips/dts/mt7628an_tplink_tl-wr840n-v5.dts
index 3e639668bbaa0d..8c7192fca805de 100644
--- a/target/linux/ramips/dts/mt7628an_tplink_tl-wr840n-v5.dts
+++ b/target/linux/ramips/dts/mt7628an_tplink_tl-wr840n-v5.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "tplink,tl-wr840n-v5", "mediatek,mt7628an-soc";
@@ -33,12 +34,14 @@
 		compatible = "gpio-leds";
 
 		led_power_green: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 41 GPIO_ACTIVE_LOW>;
 		};
 
 		orange {
-			label = "orange:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 43 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -69,7 +72,7 @@
 				reg = <0x20000 0x3d0000>;
 			};
 
-			factory: partition@3f0000 {
+			partition@3f0000 {
 				label = "factory";
 				reg = <0x3f0000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_tplink_tl-wr841n-v13.dts b/target/linux/ramips/dts/mt7628an_tplink_tl-wr841n-v13.dts
index e1e77eba237eaf..2e5aabd5818a0a 100644
--- a/target/linux/ramips/dts/mt7628an_tplink_tl-wr841n-v13.dts
+++ b/target/linux/ramips/dts/mt7628an_tplink_tl-wr841n-v13.dts
@@ -1,3 +1,5 @@
+#include <dt-bindings/leds/common.h>
+
 #include "mt7628an_tplink_8m.dtsi"
 
 / {
@@ -31,12 +33,14 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 36 GPIO_ACTIVE_LOW>;
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
 		};
 
@@ -61,17 +65,20 @@
 		};
 
 		wan_green {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 43 GPIO_ACTIVE_LOW>;
 		};
 
 		wan_orange {
-			label = "orange:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/mt7628an_tplink_tl-wr841n-v14.dts b/target/linux/ramips/dts/mt7628an_tplink_tl-wr841n-v14.dts
index 5b3bcbe63ab8f4..c6c6fbd9068ee7 100644
--- a/target/linux/ramips/dts/mt7628an_tplink_tl-wr841n-v14.dts
+++ b/target/linux/ramips/dts/mt7628an_tplink_tl-wr841n-v14.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "tplink,tl-wr841n-v14", "mediatek,mt7628an-soc";
@@ -33,23 +34,27 @@
 		compatible = "gpio-leds";
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 39 GPIO_ACTIVE_LOW>;
 		};
 
 		wan_green {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 40 GPIO_ACTIVE_LOW>;
 		};
 
 		led_wlan: wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 41 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
 
 		wan_orange {
-			label = "orange:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -80,7 +85,7 @@
 				reg = <0x10000 0x3e0000>;
 			};
 
-			factory: partition@3f0000 {
+			partition@3f0000 {
 				label = "factory";
 				reg = <0x3f0000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_tplink_tl-wr842n-v5.dts b/target/linux/ramips/dts/mt7628an_tplink_tl-wr842n-v5.dts
index b5c3bd9ab5b8cc..0ded67a1a633ae 100644
--- a/target/linux/ramips/dts/mt7628an_tplink_tl-wr842n-v5.dts
+++ b/target/linux/ramips/dts/mt7628an_tplink_tl-wr842n-v5.dts
@@ -1,3 +1,5 @@
+#include <dt-bindings/leds/common.h>
+
 #include "mt7628an_tplink_8m.dtsi"
 
 / {
@@ -31,39 +33,46 @@
 		compatible = "gpio-leds";
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 41 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
 		};
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&ohci_port1>, <&ehci_port1>;
 			linux,default-trigger = "usbport";
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
 		};
 
 		wan_amber {
-			label = "amber:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/mt7628an_tplink_tl-wr850n-v2.dts b/target/linux/ramips/dts/mt7628an_tplink_tl-wr850n-v2.dts
index 9fc7f97ae51085..b8a394b26ba8dd 100644
--- a/target/linux/ramips/dts/mt7628an_tplink_tl-wr850n-v2.dts
+++ b/target/linux/ramips/dts/mt7628an_tplink_tl-wr850n-v2.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "mt7628an_tplink_8m.dtsi"
 
 / {
@@ -27,27 +29,32 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 36 GPIO_ACTIVE_LOW>;
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 41 GPIO_ACTIVE_LOW>;
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 43 GPIO_ACTIVE_LOW>;
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
diff --git a/target/linux/ramips/dts/mt7628an_tplink_tl-wr902ac-v3.dts b/target/linux/ramips/dts/mt7628an_tplink_tl-wr902ac-v3.dts
index 0029be21e0f904..d280c6b32a72ad 100644
--- a/target/linux/ramips/dts/mt7628an_tplink_tl-wr902ac-v3.dts
+++ b/target/linux/ramips/dts/mt7628an_tplink_tl-wr902ac-v3.dts
@@ -1,3 +1,5 @@
+#include <dt-bindings/leds/common.h>
+
 #include "mt7628an_tplink_8m.dtsi"
 
 / {
@@ -43,34 +45,40 @@
 		compatible = "gpio-leds";
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
 		};
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 43 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&ohci_port1>, <&ehci_port1>;
 			linux,default-trigger = "usbport";
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 39 GPIO_ACTIVE_LOW>;
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/mt7628an_unielec_u7628-01-16m.dts b/target/linux/ramips/dts/mt7628an_unielec_u7628-01-16m.dts
index 77d8b9fce6530d..1be912f8ea964c 100644
--- a/target/linux/ramips/dts/mt7628an_unielec_u7628-01-16m.dts
+++ b/target/linux/ramips/dts/mt7628an_unielec_u7628-01-16m.dts
@@ -37,7 +37,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_unielec_u7628-01.dtsi b/target/linux/ramips/dts/mt7628an_unielec_u7628-01.dtsi
index b31ffba8090781..e9a942785fa0a2 100644
--- a/target/linux/ramips/dts/mt7628an_unielec_u7628-01.dtsi
+++ b/target/linux/ramips/dts/mt7628an_unielec_u7628-01.dtsi
@@ -9,6 +9,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "unielec,u7628-01", "mediatek,mt7628an-soc";
@@ -38,17 +39,20 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 43 GPIO_ACTIVE_LOW>;
 		};
 
@@ -73,7 +77,8 @@
 		};
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&ohci_port1>, <&ehci_port1>;
 			linux,default-trigger = "usbport";
diff --git a/target/linux/ramips/dts/mt7628an_vocore_vocore2-lite.dts b/target/linux/ramips/dts/mt7628an_vocore_vocore2-lite.dts
index 26012a6a4f3703..4a5b0ff63a9ba5 100644
--- a/target/linux/ramips/dts/mt7628an_vocore_vocore2-lite.dts
+++ b/target/linux/ramips/dts/mt7628an_vocore_vocore2-lite.dts
@@ -1,3 +1,5 @@
+#include <dt-bindings/leds/common.h>
+
 #include "mt7628an_vocore_vocore2.dtsi"
 
 / {
@@ -15,7 +17,8 @@
 		compatible = "gpio-leds";
 
 		led_status: status {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;
 		};
 	};
diff --git a/target/linux/ramips/dts/mt7628an_vocore_vocore2.dtsi b/target/linux/ramips/dts/mt7628an_vocore_vocore2.dtsi
index 73ee4484b4ecd3..4982d8bccc9d7e 100644
--- a/target/linux/ramips/dts/mt7628an_vocore_vocore2.dtsi
+++ b/target/linux/ramips/dts/mt7628an_vocore_vocore2.dtsi
@@ -39,7 +39,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_wavlink_wl-wn531a3.dts b/target/linux/ramips/dts/mt7628an_wavlink_wl-wn531a3.dts
index 1ae08ed84079f3..73db7796e26e1a 100644
--- a/target/linux/ramips/dts/mt7628an_wavlink_wl-wn531a3.dts
+++ b/target/linux/ramips/dts/mt7628an_wavlink_wl-wn531a3.dts
@@ -1,6 +1,7 @@
 #include "mt7628an.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/gpio/gpio.h>
 
 / {
@@ -52,12 +53,14 @@
 		};
 
 		led_status_blue: led_status_blue {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_status_red: led_status_red {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 4 GPIO_ACTIVE_HIGH>;
 		};
 	};
@@ -108,7 +111,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_wavlink_wl-wn570ha1.dts b/target/linux/ramips/dts/mt7628an_wavlink_wl-wn570ha1.dts
index 76e89b77b6c82f..e6bc5f4b397194 100644
--- a/target/linux/ramips/dts/mt7628an_wavlink_wl-wn570ha1.dts
+++ b/target/linux/ramips/dts/mt7628an_wavlink_wl-wn570ha1.dts
@@ -1,6 +1,7 @@
 #include "mt7628an.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/gpio/gpio.h>
 
 / {
@@ -21,13 +22,15 @@
 		compatible = "gpio-leds";
 
 		power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
 			default-state = "keep";
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 43 GPIO_ACTIVE_LOW>;
 		};
 
@@ -98,7 +101,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_wavlink_wl-wn575a3.dts b/target/linux/ramips/dts/mt7628an_wavlink_wl-wn575a3.dts
index 7b12dac350c28e..96d5366375141d 100644
--- a/target/linux/ramips/dts/mt7628an_wavlink_wl-wn575a3.dts
+++ b/target/linux/ramips/dts/mt7628an_wavlink_wl-wn575a3.dts
@@ -1,6 +1,7 @@
 #include "mt7628an.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/gpio/gpio.h>
 
 / {
@@ -42,7 +43,8 @@
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -93,7 +95,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_wavlink_wl-wn576a2.dts b/target/linux/ramips/dts/mt7628an_wavlink_wl-wn576a2.dts
index fa06c44e3fc012..16a089a7f165c9 100644
--- a/target/linux/ramips/dts/mt7628an_wavlink_wl-wn576a2.dts
+++ b/target/linux/ramips/dts/mt7628an_wavlink_wl-wn576a2.dts
@@ -3,6 +3,7 @@
 #include "mt7628an.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/gpio/gpio.h>
 
 / {
@@ -75,12 +76,14 @@
 		};
 
 		lan {
-			label = "blue:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
 		};
 
 		led_wps: wps {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -132,7 +135,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_wavlink_wl-wn577a2.dts b/target/linux/ramips/dts/mt7628an_wavlink_wl-wn577a2.dts
index d2b45faa25d741..04c62b25c21ad8 100644
--- a/target/linux/ramips/dts/mt7628an_wavlink_wl-wn577a2.dts
+++ b/target/linux/ramips/dts/mt7628an_wavlink_wl-wn577a2.dts
@@ -3,6 +3,7 @@
 #include "mt7628an.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/gpio/gpio.h>
 
 / {
@@ -36,17 +37,20 @@
 		compatible = "gpio-leds";
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 40 GPIO_ACTIVE_LOW>;
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 39 GPIO_ACTIVE_LOW>;
 		};
 
 		led_wps: wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -97,7 +101,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_wavlink_wl-wn578a2.dts b/target/linux/ramips/dts/mt7628an_wavlink_wl-wn578a2.dts
index a9b98683042e1a..1b84005583f2f0 100644
--- a/target/linux/ramips/dts/mt7628an_wavlink_wl-wn578a2.dts
+++ b/target/linux/ramips/dts/mt7628an_wavlink_wl-wn578a2.dts
@@ -3,6 +3,7 @@
 #include "mt7628an.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/gpio/gpio.h>
 
 / {
@@ -65,17 +66,20 @@
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 40 GPIO_ACTIVE_LOW>;
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 39 GPIO_ACTIVE_LOW>;
 		};
 
 		led_wps: wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -127,7 +131,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_widora_neo.dtsi b/target/linux/ramips/dts/mt7628an_widora_neo.dtsi
index 47ed0431d2f065..de3b7d625ef430 100644
--- a/target/linux/ramips/dts/mt7628an_widora_neo.dtsi
+++ b/target/linux/ramips/dts/mt7628an_widora_neo.dtsi
@@ -73,7 +73,7 @@
 				reg = <0x30000 0x10000>;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_wiznet_wizfi630s.dts b/target/linux/ramips/dts/mt7628an_wiznet_wizfi630s.dts
index 01c8bb942a07bb..429b00c5b5697d 100644
--- a/target/linux/ramips/dts/mt7628an_wiznet_wizfi630s.dts
+++ b/target/linux/ramips/dts/mt7628an_wiznet_wizfi630s.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "wiznet,wizfi630s", "mediatek,mt7628an-soc";
@@ -31,7 +32,8 @@
 		};
 
 		ledwps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
 		};
 
@@ -113,7 +115,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_wrtnode_wrtnode2.dtsi b/target/linux/ramips/dts/mt7628an_wrtnode_wrtnode2.dtsi
index 207fea28e978bd..f532a3e2a8c37c 100644
--- a/target/linux/ramips/dts/mt7628an_wrtnode_wrtnode2.dtsi
+++ b/target/linux/ramips/dts/mt7628an_wrtnode_wrtnode2.dtsi
@@ -47,7 +47,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_wrtnode_wrtnode2p.dts b/target/linux/ramips/dts/mt7628an_wrtnode_wrtnode2p.dts
index 88ec3f0c306446..2018fe1a592625 100644
--- a/target/linux/ramips/dts/mt7628an_wrtnode_wrtnode2p.dts
+++ b/target/linux/ramips/dts/mt7628an_wrtnode_wrtnode2p.dts
@@ -1,3 +1,5 @@
+#include <dt-bindings/leds/common.h>
+
 #include "mt7628an_wrtnode_wrtnode2.dtsi"
 
 / {
@@ -15,7 +17,8 @@
 		compatible = "gpio-leds";
 
 		led_indicator: indicator {
-			label = "blue:indicator";
+			function = LED_FUNCTION_INDICATOR;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 41 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/mt7628an_wrtnode_wrtnode2r.dts b/target/linux/ramips/dts/mt7628an_wrtnode_wrtnode2r.dts
index 511354ae5e9562..2c479a3840bc2f 100644
--- a/target/linux/ramips/dts/mt7628an_wrtnode_wrtnode2r.dts
+++ b/target/linux/ramips/dts/mt7628an_wrtnode_wrtnode2r.dts
@@ -1,3 +1,5 @@
+#include <dt-bindings/leds/common.h>
+
 #include "mt7628an_wrtnode_wrtnode2.dtsi"
 
 / {
@@ -18,7 +20,8 @@
 		pinctrl-0 = <&led_pins>;
 
 		led_indicator: indicator {
-			label = "blue:indicator";
+			function = LED_FUNCTION_INDICATOR;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/mt7628an_xiaomi_mi-router-4.dtsi b/target/linux/ramips/dts/mt7628an_xiaomi_mi-router-4.dtsi
index 7655da40db9bb0..97b18680d9e03b 100644
--- a/target/linux/ramips/dts/mt7628an_xiaomi_mi-router-4.dtsi
+++ b/target/linux/ramips/dts/mt7628an_xiaomi_mi-router-4.dtsi
@@ -46,7 +46,7 @@
 				read-only;
 			};
 
-			factory: partition@30000 {
+			partition@30000 {
 				label = "factory";
 				reg = <0x30000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_xiaomi_mi-router-4a-100m-intl.dts b/target/linux/ramips/dts/mt7628an_xiaomi_mi-router-4a-100m-intl.dts
index 49ca637cb9e6eb..4009033689da71 100644
--- a/target/linux/ramips/dts/mt7628an_xiaomi_mi-router-4a-100m-intl.dts
+++ b/target/linux/ramips/dts/mt7628an_xiaomi_mi-router-4a-100m-intl.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "mt7628an_xiaomi_mi-router-4.dtsi"
 
 / {
@@ -18,17 +20,20 @@
 		compatible = "gpio-leds";
 
 		led_power_blue: power_blue {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_yellow: power_yellow {
-			label = "yellow:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_YELLOW>;
 			gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
 		};
 
 		wan {
-			label = "blue:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/mt7628an_xiaomi_mi-router-4a-100m.dts b/target/linux/ramips/dts/mt7628an_xiaomi_mi-router-4a-100m.dts
index f40717267c7a80..621bd22b00b736 100644
--- a/target/linux/ramips/dts/mt7628an_xiaomi_mi-router-4a-100m.dts
+++ b/target/linux/ramips/dts/mt7628an_xiaomi_mi-router-4a-100m.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "mt7628an_xiaomi_mi-router-4.dtsi"
 
 / {
@@ -18,17 +20,20 @@
 		compatible = "gpio-leds";
 
 		led_power_blue: power_blue {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_yellow: power_yellow {
-			label = "yellow:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_YELLOW>;
 			gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
 		};
 
 		wan {
-			label = "blue:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/mt7628an_xiaomi_mi-router-4c.dts b/target/linux/ramips/dts/mt7628an_xiaomi_mi-router-4c.dts
index 27348b3ad7d60d..a406c8f124e02c 100644
--- a/target/linux/ramips/dts/mt7628an_xiaomi_mi-router-4c.dts
+++ b/target/linux/ramips/dts/mt7628an_xiaomi_mi-router-4c.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "mt7628an_xiaomi_mi-router-4.dtsi"
 
 / {
@@ -18,17 +20,20 @@
 		compatible = "gpio-leds";
 
 		led_power_blue: power_blue {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_yellow: power_yellow {
-			label = "yellow:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_YELLOW>;
 			gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
 		};
 
 		wan {
-			label = "blue:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ramips/dts/mt7628an_xiaomi_miwifi-3c.dts b/target/linux/ramips/dts/mt7628an_xiaomi_miwifi-3c.dts
index 2adb6ba8e36895..13d8da05f71f80 100644
--- a/target/linux/ramips/dts/mt7628an_xiaomi_miwifi-3c.dts
+++ b/target/linux/ramips/dts/mt7628an_xiaomi_miwifi-3c.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "xiaomi,miwifi-3c", "mediatek,mt7628an-soc";
@@ -25,17 +26,20 @@
 		compatible = "gpio-leds";
 
 		led_status_blue: status_blue {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status_red: status_red {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status_amber: status_amber {
-			label = "amber:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -113,7 +117,7 @@
 				read-only;
 			};
 
-			factory: partition@50000 {
+			partition@50000 {
 				label = "factory";
 				reg = <0x50000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_xiaomi_miwifi-nano.dts b/target/linux/ramips/dts/mt7628an_xiaomi_miwifi-nano.dts
index 66297232e3a532..889e725df5c77a 100644
--- a/target/linux/ramips/dts/mt7628an_xiaomi_miwifi-nano.dts
+++ b/target/linux/ramips/dts/mt7628an_xiaomi_miwifi-nano.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "xiaomi,miwifi-nano", "mediatek,mt7628an-soc";
@@ -23,17 +24,20 @@
 		compatible = "gpio-leds";
 
 		led_status_blue: status_blue {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status_red: status_red {
-			label = "red:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status_amber: status_amber {
-			label = "amber:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -105,7 +109,7 @@
 				reg = <0x30000 0x10000>;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_zbtlink_zbt-we1226.dts b/target/linux/ramips/dts/mt7628an_zbtlink_zbt-we1226.dts
index 64f3d6d83f3f15..591e3cce720892 100644
--- a/target/linux/ramips/dts/mt7628an_zbtlink_zbt-we1226.dts
+++ b/target/linux/ramips/dts/mt7628an_zbtlink_zbt-we1226.dts
@@ -1,6 +1,7 @@
 #include "mt7628an.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/gpio/gpio.h>
 
 / {
@@ -32,7 +33,8 @@
 		compatible = "gpio-leds";
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 39 GPIO_ACTIVE_LOW>;
 		};
 
@@ -47,7 +49,8 @@
 		};
 
 		led_wlan: wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -85,7 +88,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/mt7628an_zyxel_keenetic-extra-ii.dts b/target/linux/ramips/dts/mt7628an_zyxel_keenetic-extra-ii.dts
index 95eb9cfd9e675c..70956724fb18ea 100644
--- a/target/linux/ramips/dts/mt7628an_zyxel_keenetic-extra-ii.dts
+++ b/target/linux/ramips/dts/mt7628an_zyxel_keenetic-extra-ii.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "zyxel,keenetic-extra-ii", "mediatek,mt7628an-soc";
@@ -44,7 +45,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 		};
 
@@ -59,7 +61,8 @@
 		};
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&ohci_port1>, <&ehci_port1>;
 			linux,default-trigger = "usbport";
@@ -120,7 +123,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "rf-eeprom";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt2880_airlink101_ar670w.dts b/target/linux/ramips/dts/rt2880_airlink101_ar670w.dts
index dc61cd9da506d4..7ff3b370b55c93 100644
--- a/target/linux/ramips/dts/rt2880_airlink101_ar670w.dts
+++ b/target/linux/ramips/dts/rt2880_airlink101_ar670w.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "airlink101,ar670w", "ralink,rt2880-soc";
@@ -30,7 +31,7 @@
 				read-only;
 			};
 
-			factory: partition@30000 {
+			partition@30000 {
 				reg = <0x30000 0x10000>;
 				label = "factory";
 				read-only;
@@ -62,12 +63,14 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
 		};
 
 		wpsblue {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/rt2880_airlink101_ar725w.dts b/target/linux/ramips/dts/rt2880_airlink101_ar725w.dts
index f41a9b8561edfc..95a4b495eba684 100644
--- a/target/linux/ramips/dts/rt2880_airlink101_ar725w.dts
+++ b/target/linux/ramips/dts/rt2880_airlink101_ar725w.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "airlink101,ar725w", "ralink,rt2880-soc";
@@ -35,7 +36,7 @@
 				label = "u-boot-env";
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				reg = <0x40000 0x10000>;
 				label = "factory";
 				read-only;
@@ -67,17 +68,20 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
 		};
 
 		wpsred {
-			label = "red:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
 		};
 
 		wpsblue {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/rt2880_asus_rt-n15.dts b/target/linux/ramips/dts/rt2880_asus_rt-n15.dts
index 0275a84bde0f44..3e34f891653494 100644
--- a/target/linux/ramips/dts/rt2880_asus_rt-n15.dts
+++ b/target/linux/ramips/dts/rt2880_asus_rt-n15.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	#address-cells = <1>;
@@ -39,7 +40,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
@@ -94,7 +95,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/rt2880_belkin_f5d8235-v1.dts b/target/linux/ramips/dts/rt2880_belkin_f5d8235-v1.dts
index 1c2b9a18da76d0..86e4964a99dd95 100644
--- a/target/linux/ramips/dts/rt2880_belkin_f5d8235-v1.dts
+++ b/target/linux/ramips/dts/rt2880_belkin_f5d8235-v1.dts
@@ -37,7 +37,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt2880_buffalo_wli-tx4-ag300n.dts b/target/linux/ramips/dts/rt2880_buffalo_wli-tx4-ag300n.dts
index 37288e5fc4014e..b89e0865841de2 100644
--- a/target/linux/ramips/dts/rt2880_buffalo_wli-tx4-ag300n.dts
+++ b/target/linux/ramips/dts/rt2880_buffalo_wli-tx4-ag300n.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	#address-cells = <1>;
@@ -39,7 +40,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
@@ -99,7 +100,8 @@
 		};
 
 		led_power: power {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ramips/dts/rt2880_buffalo_wzr-agl300nh.dts b/target/linux/ramips/dts/rt2880_buffalo_wzr-agl300nh.dts
index bc01bf23ef6d50..e86486dce65fdf 100644
--- a/target/linux/ramips/dts/rt2880_buffalo_wzr-agl300nh.dts
+++ b/target/linux/ramips/dts/rt2880_buffalo_wzr-agl300nh.dts
@@ -39,7 +39,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt2880_dlink_dap-1522-a1.dts b/target/linux/ramips/dts/rt2880_dlink_dap-1522-a1.dts
index 105a3c49d486ca..3fdbdf681eacfc 100644
--- a/target/linux/ramips/dts/rt2880_dlink_dap-1522-a1.dts
+++ b/target/linux/ramips/dts/rt2880_dlink_dap-1522-a1.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "dlink,dap-1522-a1", "ralink,rt2880-soc";
@@ -31,7 +32,7 @@
 				read-only;
 			};
 
-			factory: partition@30000 {
+			partition@30000 {
 				label = "factory";
 				reg = <0x30000 0x10000>;
 				read-only;
@@ -100,7 +101,8 @@
 		compatible = "gpio-leds";
 
 		wps {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio2 17 GPIO_ACTIVE_LOW>;
 		};
 
@@ -115,7 +117,8 @@
 		};
 
 		led_status: status {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio2 20 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/rt2880_ralink_v11st-fe.dts b/target/linux/ramips/dts/rt2880_ralink_v11st-fe.dts
index 3f4142f50895c4..695db15a550045 100644
--- a/target/linux/ramips/dts/rt2880_ralink_v11st-fe.dts
+++ b/target/linux/ramips/dts/rt2880_ralink_v11st-fe.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "ralink,v11st-fe", "ralink,rt2880-soc";
@@ -36,7 +37,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				reg = <0x00040000 0x00010000>;
 				label = "factory";
 				read-only;
@@ -75,7 +76,8 @@
 		compatible = "gpio-leds";
 
 		led_status: status {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/rt3050_8devices_carambola.dts b/target/linux/ramips/dts/rt3050_8devices_carambola.dts
index 8cc586207f04cf..f99c7081874c77 100644
--- a/target/linux/ramips/dts/rt3050_8devices_carambola.dts
+++ b/target/linux/ramips/dts/rt3050_8devices_carambola.dts
@@ -34,7 +34,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt3050_allnet_all0256n.dtsi b/target/linux/ramips/dts/rt3050_allnet_all0256n.dtsi
index f7b64c63261c6c..3be20dd2f4ddff 100644
--- a/target/linux/ramips/dts/rt3050_allnet_all0256n.dtsi
+++ b/target/linux/ramips/dts/rt3050_allnet_all0256n.dtsi
@@ -62,7 +62,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt3050_alphanetworks_asl26555-16m.dts b/target/linux/ramips/dts/rt3050_alphanetworks_asl26555-16m.dts
index 1d66023ceba7c5..818bd1418213df 100644
--- a/target/linux/ramips/dts/rt3050_alphanetworks_asl26555-16m.dts
+++ b/target/linux/ramips/dts/rt3050_alphanetworks_asl26555-16m.dts
@@ -54,7 +54,7 @@
 				read-only;
 			};
 
-			devdata: partition@ff0000 {
+			partition@ff0000 {
 				label = "devdata";
 				reg = <0xff0000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt3050_alphanetworks_asl26555-8m.dts b/target/linux/ramips/dts/rt3050_alphanetworks_asl26555-8m.dts
index 41ed37d808af24..efdf24f9c4ea5e 100644
--- a/target/linux/ramips/dts/rt3050_alphanetworks_asl26555-8m.dts
+++ b/target/linux/ramips/dts/rt3050_alphanetworks_asl26555-8m.dts
@@ -24,7 +24,7 @@
 				read-only;
 			};
 
-			devdata: partition@30000 {
+			partition@30000 {
 				label = "uboot-env";
 				reg = <0x30000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt3050_alphanetworks_asl26555.dtsi b/target/linux/ramips/dts/rt3050_alphanetworks_asl26555.dtsi
index 41985278632a0d..74e3edd4edcebc 100644
--- a/target/linux/ramips/dts/rt3050_alphanetworks_asl26555.dtsi
+++ b/target/linux/ramips/dts/rt3050_alphanetworks_asl26555.dtsi
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "alphanetworks,asl26555", "ralink,rt3050-soc";
@@ -39,27 +40,32 @@
 		};
 
 		wan-red {
-			label = "red:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
 		};
 
 		wan-green {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_power_green: power-green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
 		};
 
 		power-red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
 		};
 
diff --git a/target/linux/ramips/dts/rt3050_arcwireless_freestation5.dts b/target/linux/ramips/dts/rt3050_arcwireless_freestation5.dts
index 9b696b3431382d..7d5d400410a458 100644
--- a/target/linux/ramips/dts/rt3050_arcwireless_freestation5.dts
+++ b/target/linux/ramips/dts/rt3050_arcwireless_freestation5.dts
@@ -34,7 +34,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt3050_asus_rt-g32-b1.dts b/target/linux/ramips/dts/rt3050_asus_rt-g32-b1.dts
index e112a1b33db132..5d980ebf8a58b1 100644
--- a/target/linux/ramips/dts/rt3050_asus_rt-g32-b1.dts
+++ b/target/linux/ramips/dts/rt3050_asus_rt-g32-b1.dts
@@ -50,7 +50,7 @@
 				read-only;
 			};
 
-			devconf: partition@40000 {
+			partition@40000 {
 				label = "devconf";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt3050_asus_rt-n10-plus.dts b/target/linux/ramips/dts/rt3050_asus_rt-n10-plus.dts
index a452a44202fcef..85414a284ebf65 100644
--- a/target/linux/ramips/dts/rt3050_asus_rt-n10-plus.dts
+++ b/target/linux/ramips/dts/rt3050_asus_rt-n10-plus.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "asus,rt-n10-plus", "ralink,rt3050-soc";
@@ -37,7 +38,7 @@
 				read-only;
 			};
 
-			devconf: partition@40000 {
+			partition@40000 {
 				label = "devconf";
 				reg = <0x40000 0x10000>;
 				read-only;
@@ -69,7 +70,8 @@
 		compatible = "gpio-leds";
 
 		led_wps: wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/rt3050_asus_wl-330n.dts b/target/linux/ramips/dts/rt3050_asus_wl-330n.dts
index 938f5d440c8743..e9349f6a39ea3b 100644
--- a/target/linux/ramips/dts/rt3050_asus_wl-330n.dts
+++ b/target/linux/ramips/dts/rt3050_asus_wl-330n.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "asus,wl-330n", "ralink,rt3050-soc";
@@ -23,7 +24,8 @@
 		};
 
 		led_power: power {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -71,7 +73,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt3050_asus_wl-330n3g.dts b/target/linux/ramips/dts/rt3050_asus_wl-330n3g.dts
index 4f8b7e73ea4c4a..eb47913fb25488 100644
--- a/target/linux/ramips/dts/rt3050_asus_wl-330n3g.dts
+++ b/target/linux/ramips/dts/rt3050_asus_wl-330n3g.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "asus,wl-330n3g", "ralink,rt3050-soc";
@@ -28,7 +29,8 @@
 		};
 
 		led_power: power {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -76,7 +78,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt3050_dlink_dcs-930.dts b/target/linux/ramips/dts/rt3050_dlink_dcs-930.dts
index e3a26bd4cf6164..32ecbb47b8619b 100644
--- a/target/linux/ramips/dts/rt3050_dlink_dcs-930.dts
+++ b/target/linux/ramips/dts/rt3050_dlink_dcs-930.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "dlink,dcs-930", "ralink,rt3050-soc";
@@ -37,7 +38,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
@@ -74,12 +75,14 @@
 		};
 
 		led_status: status {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
 		};
 
 		wps {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/rt3050_dlink_dir-300-b1.dts b/target/linux/ramips/dts/rt3050_dlink_dir-300-b1.dts
index a05122b6040ce7..47264478b243fa 100644
--- a/target/linux/ramips/dts/rt3050_dlink_dir-300-b1.dts
+++ b/target/linux/ramips/dts/rt3050_dlink_dir-300-b1.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "dlink,dir-300-b1", "ralink,rt3050-soc";
@@ -31,7 +32,7 @@
 				read-only;
 			};
 
-			devdata: partition@30000 {
+			partition@30000 {
 				label = "devdata";
 				reg = <0x30000 0x10000>;
 				read-only;
@@ -86,27 +87,32 @@
 		compatible = "gpio-leds";
 
 		status {
-			label = "amber:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status_green: status2 {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
 		};
 
 		wan {
-			label = "amber:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
 		};
 
 		wan2 {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
 		};
 
 		wps {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/rt3050_dlink_dir-600-b1.dts b/target/linux/ramips/dts/rt3050_dlink_dir-600-b1.dts
index 73e65128e592e7..13badc71391c77 100644
--- a/target/linux/ramips/dts/rt3050_dlink_dir-600-b1.dts
+++ b/target/linux/ramips/dts/rt3050_dlink_dir-600-b1.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "dlink,dir-600-b1", "ralink,rt3050-soc";
@@ -31,7 +32,7 @@
 				read-only;
 			};
 
-			devdata: partition@30000 {
+			partition@30000 {
 				label = "devdata";
 				reg = <0x30000 0x10000>;
 				read-only;
@@ -51,7 +52,7 @@
 				};
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "devconf";
 				reg = <0x40000 0x10000>;
 				read-only;
@@ -86,27 +87,32 @@
 		compatible = "gpio-leds";
 
 		status {
-			label = "amber:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status_green: status2 {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
 		};
 
 		wan {
-			label = "amber:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
 		};
 
 		wan2 {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
 		};
 
 		wps {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/rt3050_dlink_dir-615-d.dts b/target/linux/ramips/dts/rt3050_dlink_dir-615-d.dts
index 0d81f7e09662f7..4df6d442196d55 100644
--- a/target/linux/ramips/dts/rt3050_dlink_dir-615-d.dts
+++ b/target/linux/ramips/dts/rt3050_dlink_dir-615-d.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "dlink,dir-615-d", "ralink,rt3050-soc";
@@ -32,7 +33,7 @@
 				read-only;
 			};
 
-			devdata: partition@30000 {
+			partition@30000 {
 				label = "devdata";
 				reg = <0x30000 0x10000>;
 				read-only;
@@ -83,28 +84,33 @@
 		compatible = "gpio-leds";
 
 		status_amber {
-			label = "amber:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status_green: status_green {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		wan_amber {
-			label = "amber:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
 		};
 
 		wan_green {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
 		};
 
 		wps {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/rt3050_dlink_dir-620-a1.dts b/target/linux/ramips/dts/rt3050_dlink_dir-620-a1.dts
index 3a5624d125ee7b..f159580972a0e2 100644
--- a/target/linux/ramips/dts/rt3050_dlink_dir-620-a1.dts
+++ b/target/linux/ramips/dts/rt3050_dlink_dir-620-a1.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "dlink,dir-620-a1", "ralink,rt3050-soc";
@@ -37,7 +38,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
@@ -86,32 +87,38 @@
 		compatible = "gpio-leds";
 
 		status {
-			label = "amber:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status_green: status2 {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
 		};
 
 		wan {
-			label = "amber:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
 		};
 
 		wan2 {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
 		};
 
 		wps {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
 		};
 
 		wps2 {
-			label = "amber:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
 		};
 	};
diff --git a/target/linux/ramips/dts/rt3050_edimax_3g-6200n.dts b/target/linux/ramips/dts/rt3050_edimax_3g-6200n.dts
index 62686b5489bf7b..128f84de1ffc4e 100644
--- a/target/linux/ramips/dts/rt3050_edimax_3g-6200n.dts
+++ b/target/linux/ramips/dts/rt3050_edimax_3g-6200n.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/mtd/partitions/uimage.h>
 
 / {
@@ -38,7 +39,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
@@ -78,12 +79,14 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
 		};
 
 		wlan {
-			label = "amber:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ramips/dts/rt3050_edimax_3g-6200nl.dts b/target/linux/ramips/dts/rt3050_edimax_3g-6200nl.dts
index c0fdb9995deac0..5277f9b5237573 100644
--- a/target/linux/ramips/dts/rt3050_edimax_3g-6200nl.dts
+++ b/target/linux/ramips/dts/rt3050_edimax_3g-6200nl.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/mtd/partitions/uimage.h>
 
 / {
@@ -38,7 +39,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
@@ -83,7 +84,8 @@
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/rt3050_huawei_d105.dts b/target/linux/ramips/dts/rt3050_huawei_d105.dts
index 5e217aa3625807..6a26e0d513cf8c 100644
--- a/target/linux/ramips/dts/rt3050_huawei_d105.dts
+++ b/target/linux/ramips/dts/rt3050_huawei_d105.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "huawei,d105", "ralink,rt3050-soc";
@@ -37,7 +38,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
@@ -69,12 +70,14 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
 		};
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&otg_port1>;
 			linux,default-trigger = "usbport";
diff --git a/target/linux/ramips/dts/rt3050_jcg_jhr-n805r.dts b/target/linux/ramips/dts/rt3050_jcg_jhr-n805r.dts
index 61fac83b14661a..3c54a38f28cf86 100644
--- a/target/linux/ramips/dts/rt3050_jcg_jhr-n805r.dts
+++ b/target/linux/ramips/dts/rt3050_jcg_jhr-n805r.dts
@@ -67,7 +67,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt3050_netcore_nw718.dts b/target/linux/ramips/dts/rt3050_netcore_nw718.dts
index beceb3f35d6920..83b79d5e77b3a3 100644
--- a/target/linux/ramips/dts/rt3050_netcore_nw718.dts
+++ b/target/linux/ramips/dts/rt3050_netcore_nw718.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "netcore,nw718", "ralink,rt3050-soc";
@@ -18,19 +19,22 @@
 		compatible = "gpio-leds";
 
 		led_cpu: cpu {
-			label = "amber:cpu";
+			function = LED_FUNCTION_CPU;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
 		};
 
 		usb {
-			label = "amber:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&otg_port1>;
 			linux,default-trigger = "usbport";
 		};
 
 		wps {
-			label = "amber:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -78,7 +82,7 @@
 				read-only;
 			};
 
-			factory: partition@50000 {
+			partition@50000 {
 				label = "factory";
 				reg = <0x50000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt3050_sparklan_wcr-150gn.dts b/target/linux/ramips/dts/rt3050_sparklan_wcr-150gn.dts
index a241e91bafbbde..4b4c5e18ee07ce 100644
--- a/target/linux/ramips/dts/rt3050_sparklan_wcr-150gn.dts
+++ b/target/linux/ramips/dts/rt3050_sparklan_wcr-150gn.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "sparklan,wcr-150gn", "ralink,rt3050-soc";
@@ -37,7 +38,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
@@ -76,7 +77,8 @@
 		};
 
 		led_power: power {
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/rt3050_teltonika_rut5xx.dts b/target/linux/ramips/dts/rt3050_teltonika_rut5xx.dts
index 95faff03b44fe7..691e5d621d31cb 100644
--- a/target/linux/ramips/dts/rt3050_teltonika_rut5xx.dts
+++ b/target/linux/ramips/dts/rt3050_teltonika_rut5xx.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "teltonika,rut5xx", "ralink,rt3050-soc";
@@ -18,7 +19,8 @@
 		compatible = "gpio-leds";
 
 		led_status: status {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -69,7 +71,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt3050_tenda_w150m.dts b/target/linux/ramips/dts/rt3050_tenda_w150m.dts
index d9a3f5ac6b41dc..f76661b500184c 100644
--- a/target/linux/ramips/dts/rt3050_tenda_w150m.dts
+++ b/target/linux/ramips/dts/rt3050_tenda_w150m.dts
@@ -37,7 +37,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt3050_trendnet_tew-638apb-v2.dts b/target/linux/ramips/dts/rt3050_trendnet_tew-638apb-v2.dts
index 2accb51c3f9b35..990c3eb4cea6ce 100644
--- a/target/linux/ramips/dts/rt3050_trendnet_tew-638apb-v2.dts
+++ b/target/linux/ramips/dts/rt3050_trendnet_tew-638apb-v2.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "trendnet,tew-638apb-v2", "ralink,rt3050-soc";
@@ -37,7 +38,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
@@ -86,12 +87,14 @@
 		compatible = "gpio-leds";
 
 		wps {
-			label = "orange:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
 		};
 
 		led_wps_green: wps2 {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/rt3052_accton_wr6202.dts b/target/linux/ramips/dts/rt3052_accton_wr6202.dts
index a62f7757c7f80a..f3a31ad6ca24e4 100644
--- a/target/linux/ramips/dts/rt3052_accton_wr6202.dts
+++ b/target/linux/ramips/dts/rt3052_accton_wr6202.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "accton,wr6202", "ralink,rt3052-soc";
@@ -15,7 +16,8 @@
 		compatible = "gpio-leds";
 
 		wps {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
 		};
 
@@ -65,7 +67,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt3052_alfa-network_w502u.dts b/target/linux/ramips/dts/rt3052_alfa-network_w502u.dts
index 0b9270461bd226..609fd9b2f44f3e 100644
--- a/target/linux/ramips/dts/rt3052_alfa-network_w502u.dts
+++ b/target/linux/ramips/dts/rt3052_alfa-network_w502u.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "alfa-network,w502u", "ralink,rt3052-soc";
@@ -41,7 +42,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
@@ -73,14 +74,16 @@
 		compatible = "gpio-leds";
 
 		usb {
-			label = "blue:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&otg_port1>;
 			linux,default-trigger = "usbport";
 		};
 
 		led_wps: wps {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/rt3052_argus_atp-52b.dts b/target/linux/ramips/dts/rt3052_argus_atp-52b.dts
index 94baf5fb89aa7f..5cee0dfcfd7204 100644
--- a/target/linux/ramips/dts/rt3052_argus_atp-52b.dts
+++ b/target/linux/ramips/dts/rt3052_argus_atp-52b.dts
@@ -36,7 +36,7 @@
 				reg = <0x30000 0x10000>;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 
diff --git a/target/linux/ramips/dts/rt3052_asiarf_awapn2403.dts b/target/linux/ramips/dts/rt3052_asiarf_awapn2403.dts
index 49965d4e5e8fb8..ec794b8eab4caa 100644
--- a/target/linux/ramips/dts/rt3052_asiarf_awapn2403.dts
+++ b/target/linux/ramips/dts/rt3052_asiarf_awapn2403.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "asiarf,awapn2403", "ralink,rt3052-soc";
@@ -18,7 +19,8 @@
 		compatible = "gpio-leds";
 
 		led_wps: wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -60,7 +62,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt3052_asus_rt-n13u.dts b/target/linux/ramips/dts/rt3052_asus_rt-n13u.dts
index d60dabb5ea6bbb..4f0d9e620773ce 100644
--- a/target/linux/ramips/dts/rt3052_asus_rt-n13u.dts
+++ b/target/linux/ramips/dts/rt3052_asus_rt-n13u.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "asus,rt-n13u", "ralink,rt3052-soc";
@@ -37,7 +38,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
@@ -69,7 +70,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ramips/dts/rt3052_aximcom_mr-102n.dts b/target/linux/ramips/dts/rt3052_aximcom_mr-102n.dts
index 456bc204157fc4..f0d4122517c292 100644
--- a/target/linux/ramips/dts/rt3052_aximcom_mr-102n.dts
+++ b/target/linux/ramips/dts/rt3052_aximcom_mr-102n.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "aximcom,mr-102n", "ralink,rt3052-soc";
@@ -37,7 +38,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
@@ -79,19 +80,22 @@
 		compatible = "gpio-leds";
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&otg_port1>;
 			linux,default-trigger = "usbport";
 		};
 
 		led_status: status {
-			label = "amber:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/rt3052_aztech_hw550-3g.dts b/target/linux/ramips/dts/rt3052_aztech_hw550-3g.dts
index 4a23d65628c2a8..8f9a62bba2a4b7 100644
--- a/target/linux/ramips/dts/rt3052_aztech_hw550-3g.dts
+++ b/target/linux/ramips/dts/rt3052_aztech_hw550-3g.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "aztech,hw550-3g", "ralink,rt3052-soc";
@@ -37,7 +38,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
@@ -69,7 +70,8 @@
 		compatible = "gpio-leds";
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&otg_port1>;
 			linux,default-trigger = "usbport";
@@ -81,12 +83,14 @@
 		};
 
 		led_status: status {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/rt3052_belkin_f5d8235-v2.dts b/target/linux/ramips/dts/rt3052_belkin_f5d8235-v2.dts
index 13b16921b995cf..0119737af1bb68 100644
--- a/target/linux/ramips/dts/rt3052_belkin_f5d8235-v2.dts
+++ b/target/linux/ramips/dts/rt3052_belkin_f5d8235-v2.dts
@@ -25,7 +25,7 @@
 			#address-cells = <1>;
 			#size-cells = <1>;
 
-			uboot: partition@0 {
+			partition@0 {
 				label = "uboot";
 				reg = <0x0 0x50000>;
 				read-only;
@@ -56,7 +56,7 @@
 				reg = <0x7e0000 0x10000>;
 			};
 
-			factory: partition@7f0000 {
+			partition@7f0000 {
 				label = "factory";
 				reg = <0x7f0000 0x10000>;
 			};
diff --git a/target/linux/ramips/dts/rt3052_buffalo_whr-g300n.dts b/target/linux/ramips/dts/rt3052_buffalo_whr-g300n.dts
index 286fe0a566b080..c7d4b626951175 100644
--- a/target/linux/ramips/dts/rt3052_buffalo_whr-g300n.dts
+++ b/target/linux/ramips/dts/rt3052_buffalo_whr-g300n.dts
@@ -36,7 +36,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt3052_dlink_dap-1350.dts b/target/linux/ramips/dts/rt3052_dlink_dap-1350.dts
index 75cc1385cdd35f..581da5acbb8b69 100644
--- a/target/linux/ramips/dts/rt3052_dlink_dap-1350.dts
+++ b/target/linux/ramips/dts/rt3052_dlink_dap-1350.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "dlink,dap-1350", "ralink,rt3052-soc";
@@ -35,7 +36,7 @@
 				read-only;
 			};
 
-			devdata: partition@30000 {
+			partition@30000 {
 				label = "devdata";
 				reg = <0x30000 0x10000>;
 				read-only;
@@ -79,17 +80,20 @@
 		compatible = "gpio-leds";
 
 		led_power_blue: power {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
 		};
 
 		power2 {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
 		};
 
 		wps {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/rt3052_engenius_esr-9753.dts b/target/linux/ramips/dts/rt3052_engenius_esr-9753.dts
index 2c3b759c041a1d..8f040bf893d12b 100644
--- a/target/linux/ramips/dts/rt3052_engenius_esr-9753.dts
+++ b/target/linux/ramips/dts/rt3052_engenius_esr-9753.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "engenius,esr-9753", "ralink,rt3052-soc";
@@ -37,7 +38,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
@@ -69,12 +70,14 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "orange:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
 		};
 
 		wps {
-			label = "orange:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/rt3052_fon_fonera-20n.dts b/target/linux/ramips/dts/rt3052_fon_fonera-20n.dts
index 9a256e65dc834d..8f612fbc1c310e 100644
--- a/target/linux/ramips/dts/rt3052_fon_fonera-20n.dts
+++ b/target/linux/ramips/dts/rt3052_fon_fonera-20n.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "fon,fonera-20n", "ralink,rt3052-soc";
@@ -37,7 +38,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
@@ -74,12 +75,14 @@
 		};
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
 		};
 
 		usb {
-			label = "orange:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&otg_port1>;
 			linux,default-trigger = "usbport";
diff --git a/target/linux/ramips/dts/rt3052_hauppauge_broadway.dts b/target/linux/ramips/dts/rt3052_hauppauge_broadway.dts
index f7420e20920ef2..698d8fbc1eb534 100644
--- a/target/linux/ramips/dts/rt3052_hauppauge_broadway.dts
+++ b/target/linux/ramips/dts/rt3052_hauppauge_broadway.dts
@@ -30,7 +30,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt3052_huawei_hg255d.dts b/target/linux/ramips/dts/rt3052_huawei_hg255d.dts
index dc00110f1b7b3b..7150a7f41af8b9 100644
--- a/target/linux/ramips/dts/rt3052_huawei_hg255d.dts
+++ b/target/linux/ramips/dts/rt3052_huawei_hg255d.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "huawei,hg255d", "ralink,rt3052-soc";
@@ -37,7 +38,7 @@
 				read-only;
 			};
 
-			factory: partition@60000 {
+			partition@60000 {
 				label = "factory";
 				reg = <0x60000 0x20000>;
 				read-only;
@@ -75,7 +76,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
 		};
 
@@ -85,19 +87,22 @@
 		};
 
 		wifi {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
 		};
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&otg_port1>;
 			linux,default-trigger = "usbport";
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ramips/dts/rt3052_jcg_jhr-n825r.dts b/target/linux/ramips/dts/rt3052_jcg_jhr-n825r.dts
index 6fb85b237400eb..75af528d303cba 100644
--- a/target/linux/ramips/dts/rt3052_jcg_jhr-n825r.dts
+++ b/target/linux/ramips/dts/rt3052_jcg_jhr-n825r.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "jcg,jhr-n825r", "ralink,rt3052-soc";
@@ -37,7 +38,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
@@ -68,7 +69,8 @@
 	leds {
 		compatible = "gpio-leds";
 		led_system: system {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/rt3052_jcg_jhr-n926r.dts b/target/linux/ramips/dts/rt3052_jcg_jhr-n926r.dts
index 6096019b1031e6..8b50244e18c266 100644
--- a/target/linux/ramips/dts/rt3052_jcg_jhr-n926r.dts
+++ b/target/linux/ramips/dts/rt3052_jcg_jhr-n926r.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "jcg,jhr-n926r", "ralink,rt3052-soc";
@@ -37,7 +38,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
@@ -69,17 +70,20 @@
 		compatible = "gpio-leds";
 
 		wlan1 {
-			label = "red:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
 		};
 
 		wlan2 {
-			label = "yellow:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_YELLOW>;
 			gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
 		};
 
 		wlan3 {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ramips/dts/rt3052_mofinetwork_mofi3500-3gn.dts b/target/linux/ramips/dts/rt3052_mofinetwork_mofi3500-3gn.dts
index e1d1197d70929e..7e958c3a07fccd 100644
--- a/target/linux/ramips/dts/rt3052_mofinetwork_mofi3500-3gn.dts
+++ b/target/linux/ramips/dts/rt3052_mofinetwork_mofi3500-3gn.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "mofinetwork,mofi3500-3gn", "ralink,rt3052-soc";
@@ -37,7 +38,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
@@ -65,7 +66,8 @@
 		compatible = "gpio-leds";
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&otg_port1>;
 			linux,default-trigger = "usbport";
@@ -77,12 +79,14 @@
 		};
 
 		led_status: status {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/rt3052_netgear_wnce2001.dts b/target/linux/ramips/dts/rt3052_netgear_wnce2001.dts
index 856dc85679dc43..5406e1e263e3cb 100644
--- a/target/linux/ramips/dts/rt3052_netgear_wnce2001.dts
+++ b/target/linux/ramips/dts/rt3052_netgear_wnce2001.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "netgear,wnce2001", "ralink,rt3052-soc";
@@ -22,22 +23,26 @@
 		compatible = "gpio-leds";
 
 		led_power_green: power-green {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
 		};
 
 		power-red {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
 		};
 
 		wlan-green {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
 		};
 
 		wlan-red {
-			label = "red:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
 		};
 	};
@@ -91,7 +96,7 @@
 				read-only;
 			};
 
-			factory: partition@30000 {
+			partition@30000 {
 				label = "factory";
 				reg = <0x30000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt3052_nexaira_bc2.dts b/target/linux/ramips/dts/rt3052_nexaira_bc2.dts
index b95e919591e3a8..e92ce3261dcb5d 100644
--- a/target/linux/ramips/dts/rt3052_nexaira_bc2.dts
+++ b/target/linux/ramips/dts/rt3052_nexaira_bc2.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "nexaira,bc2", "ralink,rt3052-soc";
@@ -30,7 +31,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
@@ -62,7 +63,8 @@
 		compatible = "gpio-leds";
 
 		usb {
-			label = "blue:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&otg_port1>;
 			linux,default-trigger = "usbport";
diff --git a/target/linux/ramips/dts/rt3052_omnima_miniembwifi.dts b/target/linux/ramips/dts/rt3052_omnima_miniembwifi.dts
index 7dcecc078bd516..8aed9e947f7813 100644
--- a/target/linux/ramips/dts/rt3052_omnima_miniembwifi.dts
+++ b/target/linux/ramips/dts/rt3052_omnima_miniembwifi.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "omnima,miniembwifi", "ralink,rt3052-soc";
@@ -18,12 +19,14 @@
 		compatible = "gpio-leds";
 
 		led_status: status {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -62,7 +65,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt3052_petatel_psr-680w.dts b/target/linux/ramips/dts/rt3052_petatel_psr-680w.dts
index 5461ee2f956821..de2d9450ee08f4 100644
--- a/target/linux/ramips/dts/rt3052_petatel_psr-680w.dts
+++ b/target/linux/ramips/dts/rt3052_petatel_psr-680w.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "petatel,psr-680w", "ralink,rt3052-soc";
@@ -41,7 +42,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
@@ -73,7 +74,8 @@
 		compatible = "gpio-leds";
 
 		led_wan: wan {
-			label = "red:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/rt3052_planex_mzk-w300nh2.dts b/target/linux/ramips/dts/rt3052_planex_mzk-w300nh2.dts
index c3d7993ae66a28..88e2480f41d93c 100644
--- a/target/linux/ramips/dts/rt3052_planex_mzk-w300nh2.dts
+++ b/target/linux/ramips/dts/rt3052_planex_mzk-w300nh2.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "planex,mzk-w300nh2", "ralink,rt3052-soc";
@@ -37,7 +38,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
@@ -75,17 +76,20 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
 		};
 
 		wlan {
-			label = "amber:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
 		};
 
 		wps {
-			label = "amber:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/rt3052_planex_mzk-wdpr.dts b/target/linux/ramips/dts/rt3052_planex_mzk-wdpr.dts
index 5d445298986958..b3c9e0d400109d 100644
--- a/target/linux/ramips/dts/rt3052_planex_mzk-wdpr.dts
+++ b/target/linux/ramips/dts/rt3052_planex_mzk-wdpr.dts
@@ -34,7 +34,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt3052_poray_ip2202.dts b/target/linux/ramips/dts/rt3052_poray_ip2202.dts
index 0361004d84ea29..e9273d65702767 100644
--- a/target/linux/ramips/dts/rt3052_poray_ip2202.dts
+++ b/target/linux/ramips/dts/rt3052_poray_ip2202.dts
@@ -37,7 +37,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt3052_prolink_pwh2004.dts b/target/linux/ramips/dts/rt3052_prolink_pwh2004.dts
index 495f187a37e5c1..bb213c9f804548 100644
--- a/target/linux/ramips/dts/rt3052_prolink_pwh2004.dts
+++ b/target/linux/ramips/dts/rt3052_prolink_pwh2004.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "prolink,pwh2004", "ralink,rt3052-soc";
@@ -37,7 +38,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
@@ -70,7 +71,8 @@
 		};
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/rt3052_ralink_v22rw-2x2.dts b/target/linux/ramips/dts/rt3052_ralink_v22rw-2x2.dts
index 1b5ba03feb8dca..179e738d4feb82 100644
--- a/target/linux/ramips/dts/rt3052_ralink_v22rw-2x2.dts
+++ b/target/linux/ramips/dts/rt3052_ralink_v22rw-2x2.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "ralink,v22rw-2x2", "ralink,rt3052-soc";
@@ -37,7 +38,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
@@ -70,7 +71,8 @@
 		};
 
 		wps {
-			label = "red:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/rt3052_sitecom_wl-351.dts b/target/linux/ramips/dts/rt3052_sitecom_wl-351.dts
index 82c3783e1f63d7..f4dd87878293fd 100644
--- a/target/linux/ramips/dts/rt3052_sitecom_wl-351.dts
+++ b/target/linux/ramips/dts/rt3052_sitecom_wl-351.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "sitecom,wl-351", "ralink,rt3052-soc";
@@ -37,7 +38,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
@@ -69,7 +70,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "amber:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ramips/dts/rt3052_skyline_sl-r7205.dts b/target/linux/ramips/dts/rt3052_skyline_sl-r7205.dts
index 8a4120175e1bfa..2a1c576fe5452f 100644
--- a/target/linux/ramips/dts/rt3052_skyline_sl-r7205.dts
+++ b/target/linux/ramips/dts/rt3052_skyline_sl-r7205.dts
@@ -37,7 +37,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt3052_tenda_3g300m.dts b/target/linux/ramips/dts/rt3052_tenda_3g300m.dts
index 304d3bef1c58ab..8620d4a1ad4800 100644
--- a/target/linux/ramips/dts/rt3052_tenda_3g300m.dts
+++ b/target/linux/ramips/dts/rt3052_tenda_3g300m.dts
@@ -93,7 +93,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt3052_tenda_w306r-v2.dts b/target/linux/ramips/dts/rt3052_tenda_w306r-v2.dts
index a4d11072ea573e..ddeaa94fc5f6a1 100644
--- a/target/linux/ramips/dts/rt3052_tenda_w306r-v2.dts
+++ b/target/linux/ramips/dts/rt3052_tenda_w306r-v2.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "tenda,w306r-v2", "ralink,rt3052-soc";
@@ -37,7 +38,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
@@ -74,7 +75,8 @@
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/rt3052_unbranded_wr512-3gn-4m.dts b/target/linux/ramips/dts/rt3052_unbranded_wr512-3gn-4m.dts
index 6002342fc9e585..2a8cb2a47a71d9 100644
--- a/target/linux/ramips/dts/rt3052_unbranded_wr512-3gn-4m.dts
+++ b/target/linux/ramips/dts/rt3052_unbranded_wr512-3gn-4m.dts
@@ -27,7 +27,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt3052_unbranded_wr512-3gn-8m.dts b/target/linux/ramips/dts/rt3052_unbranded_wr512-3gn-8m.dts
index 16495ddc885af9..f11c9e1816efa4 100644
--- a/target/linux/ramips/dts/rt3052_unbranded_wr512-3gn-8m.dts
+++ b/target/linux/ramips/dts/rt3052_unbranded_wr512-3gn-8m.dts
@@ -27,7 +27,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt3052_unbranded_wr512-3gn.dtsi b/target/linux/ramips/dts/rt3052_unbranded_wr512-3gn.dtsi
index 869cf32d787931..c18112fc01eb90 100644
--- a/target/linux/ramips/dts/rt3052_unbranded_wr512-3gn.dtsi
+++ b/target/linux/ramips/dts/rt3052_unbranded_wr512-3gn.dtsi
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "unbranded,wr512-3gn", "ralink,rt3052-soc";
@@ -32,7 +33,8 @@
 		};
 
 		led_wps: wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ramips/dts/rt3052_unbranded_xdx-rn502j.dts b/target/linux/ramips/dts/rt3052_unbranded_xdx-rn502j.dts
index ec5e4af5e28aa7..af140fee1f51a9 100644
--- a/target/linux/ramips/dts/rt3052_unbranded_xdx-rn502j.dts
+++ b/target/linux/ramips/dts/rt3052_unbranded_xdx-rn502j.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "unbranded,xdx-rn502j", "ralink,rt3052-soc";
@@ -37,7 +38,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
@@ -74,7 +75,8 @@
 		};
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/rt3052_upvel_ur-326n4g.dts b/target/linux/ramips/dts/rt3052_upvel_ur-326n4g.dts
index 8104bf60538771..e22b946b085a6e 100644
--- a/target/linux/ramips/dts/rt3052_upvel_ur-326n4g.dts
+++ b/target/linux/ramips/dts/rt3052_upvel_ur-326n4g.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "upvel,ur-326n4g", "ralink,rt3052-soc";
@@ -37,7 +38,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
@@ -84,7 +85,8 @@
 		};
 
 		led_wps: wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ramips/dts/rt3052_upvel_ur-336un.dts b/target/linux/ramips/dts/rt3052_upvel_ur-336un.dts
index 050ce21a753649..4a7dc5511c6102 100644
--- a/target/linux/ramips/dts/rt3052_upvel_ur-336un.dts
+++ b/target/linux/ramips/dts/rt3052_upvel_ur-336un.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "upvel,ur-336un", "ralink,rt3052-soc";
@@ -37,7 +38,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
@@ -84,7 +85,8 @@
 		};
 
 		led_wps: wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/ramips/dts/rt3052_zyxel_keenetic.dts b/target/linux/ramips/dts/rt3052_zyxel_keenetic.dts
index 2c16736c962a09..e7db3eda15b8f1 100644
--- a/target/linux/ramips/dts/rt3052_zyxel_keenetic.dts
+++ b/target/linux/ramips/dts/rt3052_zyxel_keenetic.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "zyxel,keenetic", "ralink,rt3052-soc";
@@ -37,7 +38,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
@@ -69,19 +70,22 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
 		};
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&otg_port1>;
 			linux,default-trigger = "usbport";
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/rt3052_zyxel_nbg-419n.dts b/target/linux/ramips/dts/rt3052_zyxel_nbg-419n.dts
index 18dcf6b6760dd3..8dee38c1f80538 100644
--- a/target/linux/ramips/dts/rt3052_zyxel_nbg-419n.dts
+++ b/target/linux/ramips/dts/rt3052_zyxel_nbg-419n.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "zyxel,nbg-419n", "ralink,rt3052-soc";
@@ -37,7 +38,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
@@ -69,12 +70,14 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/rt3352_allnet_all5002.dts b/target/linux/ramips/dts/rt3352_allnet_all5002.dts
index 6483e935dde568..df4e9a6fce785e 100644
--- a/target/linux/ramips/dts/rt3352_allnet_all5002.dts
+++ b/target/linux/ramips/dts/rt3352_allnet_all5002.dts
@@ -68,7 +68,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt3352_dlink_dir-615-h1.dts b/target/linux/ramips/dts/rt3352_dlink_dir-615-h1.dts
index dc2c49cd0b80ee..8ed29c8dee30fe 100644
--- a/target/linux/ramips/dts/rt3352_dlink_dir-615-h1.dts
+++ b/target/linux/ramips/dts/rt3352_dlink_dir-615-h1.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "dlink,dir-615-h1", "ralink,rt3352-soc";
@@ -19,28 +20,33 @@
 		compatible = "gpio-leds";
 
 		status {
-			label = "amber:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_status_green: status2 {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
 			default-state = "on";
 		};
 
 		wan {
-			label = "amber:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
 		};
 
 		wan2 {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
 		};
 
 		wps {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -88,7 +94,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt3352_dlink_dir-620-d1.dts b/target/linux/ramips/dts/rt3352_dlink_dir-620-d1.dts
index de020706dfd64d..bd897a0d1a321a 100644
--- a/target/linux/ramips/dts/rt3352_dlink_dir-620-d1.dts
+++ b/target/linux/ramips/dts/rt3352_dlink_dir-620-d1.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "dlink,dir-620-d1", "ralink,rt3352-soc";
@@ -18,7 +19,8 @@
 		compatible = "gpio-leds";
 
 		led_status: status {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
 		};
 
@@ -65,7 +67,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt3352_zte_mf283plus.dts b/target/linux/ramips/dts/rt3352_zte_mf283plus.dts
index 01455b0d5af5a5..1d0b14608a3d50 100644
--- a/target/linux/ramips/dts/rt3352_zte_mf283plus.dts
+++ b/target/linux/ramips/dts/rt3352_zte_mf283plus.dts
@@ -84,7 +84,7 @@
 				read-only;
 			};
 
-			factory: partition@70000 {
+			partition@70000 {
 				label = "factory";
 				reg = <0x70000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt3352_zyxel_nbg-419n-v2.dts b/target/linux/ramips/dts/rt3352_zyxel_nbg-419n-v2.dts
index 0ac89bce43b284..f00fd58b71f928 100644
--- a/target/linux/ramips/dts/rt3352_zyxel_nbg-419n-v2.dts
+++ b/target/linux/ramips/dts/rt3352_zyxel_nbg-419n-v2.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "zyxel,nbg-419n-v2", "ralink,rt3352-soc";
@@ -18,17 +19,20 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
 		};
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&ohci_port1>, <&ehci_port1>;
 			linux,default-trigger = "usbport";
@@ -82,7 +86,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt3662_asus_rt-n56u.dts b/target/linux/ramips/dts/rt3662_asus_rt-n56u.dts
index 7837a4ca3da9c7..391076cee963d7 100644
--- a/target/linux/ramips/dts/rt3662_asus_rt-n56u.dts
+++ b/target/linux/ramips/dts/rt3662_asus_rt-n56u.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "asus,rt-n56u", "ralink,rt3662-soc", "ralink,rt3883-soc";
@@ -36,7 +37,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				reg = <0x00040000 0x00010000>;
 				label = "factory";
 				read-only;
@@ -96,22 +97,26 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
 		};
 
 		lan {
-			label = "blue:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
 		};
 
 		wan {
-			label = "blue:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
 		};
 
 		usb {
-			label = "blue:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/rt3662_dlink_dir-645.dts b/target/linux/ramips/dts/rt3662_dlink_dir-645.dts
index 87d52d679c120a..3d6479f44f4600 100644
--- a/target/linux/ramips/dts/rt3662_dlink_dir-645.dts
+++ b/target/linux/ramips/dts/rt3662_dlink_dir-645.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "dlink,dir-645", "ralink,rt3662-soc", "ralink,rt3883-soc";
@@ -47,7 +48,8 @@
 		};
 
 		led_wps: wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
 		};
 	};
@@ -93,7 +95,7 @@
 				read-only;
 			};
 
-			factory: partition@34000 {
+			partition@34000 {
 				label = "factory";
 				reg = <0x34000 0x4000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt3662_edimax_br-6475nd.dts b/target/linux/ramips/dts/rt3662_edimax_br-6475nd.dts
index 60ec3dacf501c2..051e28da8fb589 100644
--- a/target/linux/ramips/dts/rt3662_edimax_br-6475nd.dts
+++ b/target/linux/ramips/dts/rt3662_edimax_br-6475nd.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/mtd/partitions/uimage.h>
 
 / {
@@ -37,12 +38,14 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
 		};
 
 		wlan {
-			label = "amber:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
 		};
 
@@ -74,7 +77,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x00040000 0x00010000>;
 				read-only;
@@ -94,7 +97,7 @@
 				};
 			};
 
-			devdata: partition@50000 {
+			partition@50000 {
 				label = "devdata";
 				reg = <0x00050000 0x00020000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt3662_engenius_esr600h.dts b/target/linux/ramips/dts/rt3662_engenius_esr600h.dts
index e142fe53474396..b539d2d4a7c59a 100644
--- a/target/linux/ramips/dts/rt3662_engenius_esr600h.dts
+++ b/target/linux/ramips/dts/rt3662_engenius_esr600h.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "engenius,esr600h", "ralink,rt3662-soc", "ralink,rt3883-soc";
@@ -20,13 +21,15 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		wps {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -88,7 +91,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt3662_loewe_wmdr-143n.dts b/target/linux/ramips/dts/rt3662_loewe_wmdr-143n.dts
index 1da233ba78f043..446144e1af4d30 100644
--- a/target/linux/ramips/dts/rt3662_loewe_wmdr-143n.dts
+++ b/target/linux/ramips/dts/rt3662_loewe_wmdr-143n.dts
@@ -30,7 +30,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt3662_omnima_hpm.dts b/target/linux/ramips/dts/rt3662_omnima_hpm.dts
index e06e6986ec2b52..82d79dedb4789d 100644
--- a/target/linux/ramips/dts/rt3662_omnima_hpm.dts
+++ b/target/linux/ramips/dts/rt3662_omnima_hpm.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "omnima,hpm", "ralink,rt3662-soc", "ralink,rt3883-soc";
@@ -33,13 +34,15 @@
 		compatible = "gpio-leds";
 
 		power {
-			label = "orange:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		led_status: status {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
@@ -109,7 +112,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				reg = <0x00040000 0x00010000>;
 				label = "factory";
 				read-only;
diff --git a/target/linux/ramips/dts/rt3662_samsung_cy-swr1100.dts b/target/linux/ramips/dts/rt3662_samsung_cy-swr1100.dts
index b022b5c2be709a..9964fcf600af7a 100644
--- a/target/linux/ramips/dts/rt3662_samsung_cy-swr1100.dts
+++ b/target/linux/ramips/dts/rt3662_samsung_cy-swr1100.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "samsung,cy-swr1100", "ralink,rt3662-soc", "ralink,rt3883-soc";
@@ -36,7 +37,7 @@
 				read-only;
 			};
 
-			factory: partition@34000 {
+			partition@34000 {
 				label = "factory";
 				reg = <0x34000 0x4000>;
 				read-only;
@@ -103,19 +104,22 @@
 		compatible = "gpio-leds";
 
 		wps {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
 		};
 
 		usb {
-			label = "blue:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&ohci_port1>, <&ehci_port1>;
 			linux,default-trigger = "usbport";
 		};
 
 		led_power: power {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/rt3883_belkin_f9k1109v1.dts b/target/linux/ramips/dts/rt3883_belkin_f9k1109v1.dts
index 78c9bb4b6d5471..38667a5fdacba7 100644
--- a/target/linux/ramips/dts/rt3883_belkin_f9k1109v1.dts
+++ b/target/linux/ramips/dts/rt3883_belkin_f9k1109v1.dts
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/leds/common.h>
+
 #include "rt3883_belkin_f9k110x.dtsi"
 
 / {
@@ -41,12 +43,14 @@
 		};
 
 		wps_amber {
-			label = "amber:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
 		};
 
 		wps_blue {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/rt3883_belkin_f9k110x.dtsi b/target/linux/ramips/dts/rt3883_belkin_f9k110x.dtsi
index 17c982a3146caf..a2d1906b8956eb 100644
--- a/target/linux/ramips/dts/rt3883_belkin_f9k110x.dtsi
+++ b/target/linux/ramips/dts/rt3883_belkin_f9k110x.dtsi
@@ -41,7 +41,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt3883_sitecom_wlr-6000.dts b/target/linux/ramips/dts/rt3883_sitecom_wlr-6000.dts
index 17f3c10bc90e40..94a47b8735e292 100644
--- a/target/linux/ramips/dts/rt3883_sitecom_wlr-6000.dts
+++ b/target/linux/ramips/dts/rt3883_sitecom_wlr-6000.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "sitecom,wlr-6000", "ralink,rt3883-soc";
@@ -29,7 +30,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
 		};
 
@@ -120,7 +122,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt3883_trendnet_tew-691gr.dts b/target/linux/ramips/dts/rt3883_trendnet_tew-691gr.dts
index f23dc1cb039098..d9ad78ba2b6161 100644
--- a/target/linux/ramips/dts/rt3883_trendnet_tew-691gr.dts
+++ b/target/linux/ramips/dts/rt3883_trendnet_tew-691gr.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "trendnet,tew-691gr", "ralink,rt3883-soc";
@@ -36,7 +37,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				reg = <0x00040000 0x00010000>;
 				label = "factory";
 				read-only;
@@ -93,7 +94,8 @@
 		compatible = "gpio-leds";
 
 		led_wps: wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/rt3883_trendnet_tew-692gr.dts b/target/linux/ramips/dts/rt3883_trendnet_tew-692gr.dts
index ee2ca91af7ff5d..c6a817aafcacf9 100644
--- a/target/linux/ramips/dts/rt3883_trendnet_tew-692gr.dts
+++ b/target/linux/ramips/dts/rt3883_trendnet_tew-692gr.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "trendnet,tew-692gr", "ralink,rt3883-soc";
@@ -36,7 +37,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				reg = <0x00040000 0x00010000>;
 				label = "factory";
 				read-only;
@@ -87,12 +88,14 @@
 		compatible = "gpio-leds";
 
 		wps {
-			label = "orange:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
 		};
 
 		led_wps_green: wps2 {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/ramips/dts/rt5350_7links_px-4885.dtsi b/target/linux/ramips/dts/rt5350_7links_px-4885.dtsi
index 26db035c8e6e66..ba330112e1661a 100644
--- a/target/linux/ramips/dts/rt5350_7links_px-4885.dtsi
+++ b/target/linux/ramips/dts/rt5350_7links_px-4885.dtsi
@@ -66,7 +66,7 @@
 				read-only;
 			};
 
-			devconf: partition@40000 {
+			partition@40000 {
 				label = "devconf";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt5350_airlive_air3gii.dts b/target/linux/ramips/dts/rt5350_airlive_air3gii.dts
index e46b3365959086..5c64ef30e635e4 100644
--- a/target/linux/ramips/dts/rt5350_airlive_air3gii.dts
+++ b/target/linux/ramips/dts/rt5350_airlive_air3gii.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "airlive,air3gii", "ralink,rt5350-soc";
@@ -11,7 +12,8 @@
 		compatible = "gpio-leds";
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
 		};
 
@@ -60,7 +62,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt5350_allnet_all5003.dts b/target/linux/ramips/dts/rt5350_allnet_all5003.dts
index 496f1958013d0d..dfa3339330fa6e 100644
--- a/target/linux/ramips/dts/rt5350_allnet_all5003.dts
+++ b/target/linux/ramips/dts/rt5350_allnet_all5003.dts
@@ -68,7 +68,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt5350_asiarf_awm002-evb.dtsi b/target/linux/ramips/dts/rt5350_asiarf_awm002-evb.dtsi
index b9905f62f59967..eb5e25fa6eb3cc 100644
--- a/target/linux/ramips/dts/rt5350_asiarf_awm002-evb.dtsi
+++ b/target/linux/ramips/dts/rt5350_asiarf_awm002-evb.dtsi
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "asiarf,awm002-evb", "ralink,rt5350-soc";
@@ -10,17 +11,20 @@
 		compatible = "gpio-leds";
 
 		tx {
-			label = "green:tx";
+			function = LED_FUNCTION_TX;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
 		};
 
 		rx {
-			label = "green:rx";
+			function = LED_FUNCTION_RX;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -68,7 +72,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt5350_belkin_f7c027.dts b/target/linux/ramips/dts/rt5350_belkin_f7c027.dts
index b1a897a85950e1..30eb833dd7ae8c 100644
--- a/target/linux/ramips/dts/rt5350_belkin_f7c027.dts
+++ b/target/linux/ramips/dts/rt5350_belkin_f7c027.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "belkin,f7c027", "ralink,rt5350-soc";
@@ -18,17 +19,20 @@
 		compatible = "gpio-leds";
 
 		status {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
 		};
 
 		power {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status_orange: orange {
-			label = "orange:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
 		};
 
@@ -87,7 +91,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt5350_dlink_dcs-930l-b1.dts b/target/linux/ramips/dts/rt5350_dlink_dcs-930l-b1.dts
index 1e561136fae547..254b8353a88886 100644
--- a/target/linux/ramips/dts/rt5350_dlink_dcs-930l-b1.dts
+++ b/target/linux/ramips/dts/rt5350_dlink_dcs-930l-b1.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "dlink,dcs-930l-b1", "ralink,rt5350-soc";
@@ -18,12 +19,14 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
 		};
 
 		wps {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -71,7 +74,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt5350_dlink_dir-300-b7.dts b/target/linux/ramips/dts/rt5350_dlink_dir-300-b7.dts
index 13100edf046177..80740c5ae9c0ba 100644
--- a/target/linux/ramips/dts/rt5350_dlink_dir-300-b7.dts
+++ b/target/linux/ramips/dts/rt5350_dlink_dir-300-b7.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "dlink,dir-300-b7", "ralink,rt5350-soc";
@@ -18,12 +19,14 @@
 		compatible = "gpio-leds";
 
 		led_status: status {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
 		};
 
 		wps {
-			label = "blue:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -71,7 +74,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt5350_dlink_dir-320-b1.dts b/target/linux/ramips/dts/rt5350_dlink_dir-320-b1.dts
index 577b3a0a3e7c8b..71ea2256c40703 100644
--- a/target/linux/ramips/dts/rt5350_dlink_dir-320-b1.dts
+++ b/target/linux/ramips/dts/rt5350_dlink_dir-320-b1.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "dlink,dir-320-b1", "ralink,rt5350-soc";
@@ -18,17 +19,20 @@
 		compatible = "gpio-leds";
 
 		led_status: status {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
 		};
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -93,7 +97,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt5350_dlink_dir-610-a1.dts b/target/linux/ramips/dts/rt5350_dlink_dir-610-a1.dts
index 7467900e4268a0..9a352d0ea5ad73 100644
--- a/target/linux/ramips/dts/rt5350_dlink_dir-610-a1.dts
+++ b/target/linux/ramips/dts/rt5350_dlink_dir-610-a1.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "dlink,dir-610-a1", "ralink,rt5350-soc";
@@ -18,12 +19,14 @@
 		compatible = "gpio-leds";
 
 		led_status: status {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -65,7 +68,7 @@
 				read-only;
 			};
 
-			devdata: partition@30000 {
+			partition@30000 {
 				label = "devdata";
 				reg = <0x30000 0x10000>;
 				read-only;
@@ -85,7 +88,7 @@
 				};
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt5350_dlink_dwr-512-b.dts b/target/linux/ramips/dts/rt5350_dlink_dwr-512-b.dts
index 3475f4ccf70be9..56efcde9f5cd5a 100644
--- a/target/linux/ramips/dts/rt5350_dlink_dwr-512-b.dts
+++ b/target/linux/ramips/dts/rt5350_dlink_dwr-512-b.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "dlink,dwr-512-b", "ralink,rt5350-soc";
@@ -39,7 +40,8 @@
 			gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
 		};
 		led_status: status {
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
 		};
 		2g {
@@ -102,7 +104,7 @@
 				reg = <0x10000 0x7e0000>;
 			};
 
-			config: partition@7f0000 {
+			partition@7f0000 {
 				label = "config";
 				reg = <0x7f0000 0x10000>;
 
diff --git a/target/linux/ramips/dts/rt5350_easyacc_wizard-8800.dts b/target/linux/ramips/dts/rt5350_easyacc_wizard-8800.dts
index 9d7792867a608b..9b29539f8c0ee3 100644
--- a/target/linux/ramips/dts/rt5350_easyacc_wizard-8800.dts
+++ b/target/linux/ramips/dts/rt5350_easyacc_wizard-8800.dts
@@ -30,7 +30,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt5350_hame_mpr-a1.dts b/target/linux/ramips/dts/rt5350_hame_mpr-a1.dts
index 9a9580a3fba06c..a463bace6f2a9d 100644
--- a/target/linux/ramips/dts/rt5350_hame_mpr-a1.dts
+++ b/target/linux/ramips/dts/rt5350_hame_mpr-a1.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "hame,mpr-a1", "ralink,rt5350-soc";
@@ -23,7 +24,8 @@
 		};
 
 		power {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -82,7 +84,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt5350_hame_mpr-a2.dts b/target/linux/ramips/dts/rt5350_hame_mpr-a2.dts
index 5a06ef46fb35a0..557443a4c0764a 100644
--- a/target/linux/ramips/dts/rt5350_hame_mpr-a2.dts
+++ b/target/linux/ramips/dts/rt5350_hame_mpr-a2.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "hame,mpr-a2", "ralink,rt5350-soc";
@@ -23,7 +24,8 @@
 		};
 
 		power {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -82,7 +84,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt5350_hilink_hlk-rm04.dts b/target/linux/ramips/dts/rt5350_hilink_hlk-rm04.dts
index 3cc425d5af9d60..6d7b1f08920f90 100644
--- a/target/linux/ramips/dts/rt5350_hilink_hlk-rm04.dts
+++ b/target/linux/ramips/dts/rt5350_hilink_hlk-rm04.dts
@@ -75,7 +75,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt5350_hootoo_ht-tm02.dts b/target/linux/ramips/dts/rt5350_hootoo_ht-tm02.dts
index 70acc3fc439384..7d189338b73ab9 100644
--- a/target/linux/ramips/dts/rt5350_hootoo_ht-tm02.dts
+++ b/target/linux/ramips/dts/rt5350_hootoo_ht-tm02.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "hootoo,ht-tm02", "ralink,rt5350-soc";
@@ -18,12 +19,14 @@
 		compatible = "gpio-leds";
 
 		led_wlan: wlan {
-			label = "blue:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
 		};
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -72,7 +75,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt5350_intenso_memory2move.dts b/target/linux/ramips/dts/rt5350_intenso_memory2move.dts
index b1a28815f6a6bf..68807159d81da6 100644
--- a/target/linux/ramips/dts/rt5350_intenso_memory2move.dts
+++ b/target/linux/ramips/dts/rt5350_intenso_memory2move.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "intenso,memory2move", "ralink,rt5350-soc";
@@ -27,7 +28,8 @@
 		};
 
 		wan {
-			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -75,7 +77,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt5350_nexx_wt1520.dtsi b/target/linux/ramips/dts/rt5350_nexx_wt1520.dtsi
index cc55507a95f445..4dbb324def2903 100644
--- a/target/linux/ramips/dts/rt5350_nexx_wt1520.dtsi
+++ b/target/linux/ramips/dts/rt5350_nexx_wt1520.dtsi
@@ -43,7 +43,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt5350_nixcore_x1.dtsi b/target/linux/ramips/dts/rt5350_nixcore_x1.dtsi
index ce7751540bb8d7..0e35ffbedfdfb5 100644
--- a/target/linux/ramips/dts/rt5350_nixcore_x1.dtsi
+++ b/target/linux/ramips/dts/rt5350_nixcore_x1.dtsi
@@ -133,7 +133,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt5350_olimex_rt5350f-olinuxino.dtsi b/target/linux/ramips/dts/rt5350_olimex_rt5350f-olinuxino.dtsi
index 59cbbad2313991..58b0bacc8ae790 100644
--- a/target/linux/ramips/dts/rt5350_olimex_rt5350f-olinuxino.dtsi
+++ b/target/linux/ramips/dts/rt5350_olimex_rt5350f-olinuxino.dtsi
@@ -33,7 +33,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt5350_omnima_miniembplug.dts b/target/linux/ramips/dts/rt5350_omnima_miniembplug.dts
index ca98ab3599f797..2c09c12d79f824 100644
--- a/target/linux/ramips/dts/rt5350_omnima_miniembplug.dts
+++ b/target/linux/ramips/dts/rt5350_omnima_miniembplug.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "omnima,miniembplug", "ralink,rt5350-soc";
@@ -11,7 +12,8 @@
 		compatible = "gpio-leds";
 
 		wlan {
-			label = "red:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
 		};
 
@@ -85,7 +87,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt5350_planex_mzk-dp150n.dts b/target/linux/ramips/dts/rt5350_planex_mzk-dp150n.dts
index db349de5e10423..f6059f064550ad 100644
--- a/target/linux/ramips/dts/rt5350_planex_mzk-dp150n.dts
+++ b/target/linux/ramips/dts/rt5350_planex_mzk-dp150n.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "planex,mzk-dp150n", "ralink,rt5350-soc";
@@ -18,7 +19,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -60,7 +62,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt5350_poray_m3.dts b/target/linux/ramips/dts/rt5350_poray_m3.dts
index 505fba650e60c0..489f218456abd5 100644
--- a/target/linux/ramips/dts/rt5350_poray_m3.dts
+++ b/target/linux/ramips/dts/rt5350_poray_m3.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "poray,m3", "ralink,rt5350-soc";
@@ -18,7 +19,8 @@
 		compatible = "gpio-leds";
 
 		led_status: status {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -67,7 +69,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt5350_poray_m4.dtsi b/target/linux/ramips/dts/rt5350_poray_m4.dtsi
index fd358ff8efd57c..74ce5235669696 100644
--- a/target/linux/ramips/dts/rt5350_poray_m4.dtsi
+++ b/target/linux/ramips/dts/rt5350_poray_m4.dtsi
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "poray,m4", "ralink,rt5350-soc";
@@ -17,7 +18,8 @@
 		compatible = "gpio-leds";
 
 		led_status: status {
-			label = "blue:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -59,7 +61,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt5350_poray_x5.dts b/target/linux/ramips/dts/rt5350_poray_x5.dts
index d441fd3144a737..ac88c733644cfb 100644
--- a/target/linux/ramips/dts/rt5350_poray_x5.dts
+++ b/target/linux/ramips/dts/rt5350_poray_x5.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "poray,x5", "ralink,rt5350-soc";
@@ -18,7 +19,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
 		};
 
@@ -99,7 +101,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt5350_poray_x8.dts b/target/linux/ramips/dts/rt5350_poray_x8.dts
index f02eac27b128ef..7930716dcfbc59 100644
--- a/target/linux/ramips/dts/rt5350_poray_x8.dts
+++ b/target/linux/ramips/dts/rt5350_poray_x8.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "poray,x8", "ralink,rt5350-soc";
@@ -18,7 +19,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -60,7 +62,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt5350_tenda_3g150b.dts b/target/linux/ramips/dts/rt5350_tenda_3g150b.dts
index 93dc25007e8e3e..407a18e7615bf3 100644
--- a/target/linux/ramips/dts/rt5350_tenda_3g150b.dts
+++ b/target/linux/ramips/dts/rt5350_tenda_3g150b.dts
@@ -78,7 +78,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt5350_trendnet_tew-714tru.dts b/target/linux/ramips/dts/rt5350_trendnet_tew-714tru.dts
index 2810b7a70103d2..44612945a3458a 100644
--- a/target/linux/ramips/dts/rt5350_trendnet_tew-714tru.dts
+++ b/target/linux/ramips/dts/rt5350_trendnet_tew-714tru.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "trendnet,tew-714tru", "ralink,rt5350-soc";
@@ -11,7 +12,8 @@
 		compatible = "gpio-leds";
 
 		usb {
-			label = "red:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&ohci_port1>, <&ehci_port1>;
 			linux,default-trigger = "usbport";
@@ -81,7 +83,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt5350_unbranded_a5-v11.dts b/target/linux/ramips/dts/rt5350_unbranded_a5-v11.dts
index 64fd8c6b15e692..c8b361842b702d 100644
--- a/target/linux/ramips/dts/rt5350_unbranded_a5-v11.dts
+++ b/target/linux/ramips/dts/rt5350_unbranded_a5-v11.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "unbranded,a5-v11", "ralink,rt5350-soc";
@@ -24,7 +25,8 @@
 		};
 
 		led_power: power {
-			label = "red:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -83,7 +85,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt5350_vocore_vocore.dtsi b/target/linux/ramips/dts/rt5350_vocore_vocore.dtsi
index f3ef0edfe48dfa..ecb0b2eeca5aad 100644
--- a/target/linux/ramips/dts/rt5350_vocore_vocore.dtsi
+++ b/target/linux/ramips/dts/rt5350_vocore_vocore.dtsi
@@ -1,6 +1,7 @@
 #include "rt5350.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "vocore,vocore", "ralink,rt5350-soc";
@@ -144,7 +145,8 @@
 
 		led_status: status {
 			/* UARTF_RXD */
-			label = "green:status";
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>;
 		};
 
@@ -181,7 +183,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt5350_wansview_ncs601w.dts b/target/linux/ramips/dts/rt5350_wansview_ncs601w.dts
index fd3af22eb33064..52be1d7284cce8 100644
--- a/target/linux/ramips/dts/rt5350_wansview_ncs601w.dts
+++ b/target/linux/ramips/dts/rt5350_wansview_ncs601w.dts
@@ -30,7 +30,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt5350_wiznet_wizfi630a.dts b/target/linux/ramips/dts/rt5350_wiznet_wizfi630a.dts
index 192c403a87262f..2aff7445e8c598 100644
--- a/target/linux/ramips/dts/rt5350_wiznet_wizfi630a.dts
+++ b/target/linux/ramips/dts/rt5350_wiznet_wizfi630a.dts
@@ -99,7 +99,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt5350_zorlik_zl5900v2.dts b/target/linux/ramips/dts/rt5350_zorlik_zl5900v2.dts
index 00fbb5e927ae4e..488a4887b96533 100644
--- a/target/linux/ramips/dts/rt5350_zorlik_zl5900v2.dts
+++ b/target/linux/ramips/dts/rt5350_zorlik_zl5900v2.dts
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "zorlik,zl5900v2", "ralink,rt5350-soc";
@@ -18,12 +19,14 @@
 		compatible = "gpio-leds";
 
 		lan {
-			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
 		};
 
 		led_power: power {
-			label = "blue:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
 		};
 	};
@@ -65,7 +68,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt5350_zyxel_keenetic-4g-b.dts b/target/linux/ramips/dts/rt5350_zyxel_keenetic-4g-b.dts
index 9e1e47c099bd4c..d37e4189a8b085 100644
--- a/target/linux/ramips/dts/rt5350_zyxel_keenetic-4g-b.dts
+++ b/target/linux/ramips/dts/rt5350_zyxel_keenetic-4g-b.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "zyxel,keenetic-4g-b", "ralink,rt5350-soc";
@@ -20,12 +21,14 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
 		};
 
 		usb {
-			label = "green:usb";
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
 		};
 
@@ -40,7 +43,8 @@
 		};
 
 		wlan {
-			label = "green:wlan";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
 		};
 
@@ -88,7 +92,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt5350_zyxel_keenetic-lite-b.dts b/target/linux/ramips/dts/rt5350_zyxel_keenetic-lite-b.dts
index 6effb4f075b6aa..7755b5dfefb8aa 100644
--- a/target/linux/ramips/dts/rt5350_zyxel_keenetic-lite-b.dts
+++ b/target/linux/ramips/dts/rt5350_zyxel_keenetic-lite-b.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "zyxel,keenetic-lite-b", "ralink,rt5350-soc";
@@ -20,12 +21,14 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
 		};
 
 		wps {
-			label = "green:wps";
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -72,7 +75,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/dts/rt5350_zyxel_keenetic-start.dts b/target/linux/ramips/dts/rt5350_zyxel_keenetic-start.dts
index 8b1e0584b6f116..663b9a3d8c460c 100644
--- a/target/linux/ramips/dts/rt5350_zyxel_keenetic-start.dts
+++ b/target/linux/ramips/dts/rt5350_zyxel_keenetic-start.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "zyxel,keenetic-start", "ralink,rt5350-soc";
@@ -21,7 +22,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
 		};
 
@@ -74,7 +76,7 @@
 				read-only;
 			};
 
-			factory: partition@40000 {
+			partition@40000 {
 				label = "factory";
 				reg = <0x40000 0x10000>;
 				read-only;
diff --git a/target/linux/ramips/files/drivers/dma/mediatek/hsdma-mt7621.c b/target/linux/ramips/files/drivers/dma/mediatek/hsdma-mt7621.c
new file mode 100644
index 00000000000000..a3a9a7f4ae9d09
--- /dev/null
+++ b/target/linux/ramips/files/drivers/dma/mediatek/hsdma-mt7621.c
@@ -0,0 +1,760 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  Copyright (C) 2015, Michael Lee <igvtee@gmail.com>
+ *  MTK HSDMA support
+ */
+
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/irq.h>
+#include <linux/of_dma.h>
+#include <linux/reset.h>
+#include <linux/of_device.h>
+
+#include "../virt-dma.h"
+
+#define HSDMA_BASE_OFFSET		0x800
+
+#define HSDMA_REG_TX_BASE		0x00
+#define HSDMA_REG_TX_CNT		0x04
+#define HSDMA_REG_TX_CTX		0x08
+#define HSDMA_REG_TX_DTX		0x0c
+#define HSDMA_REG_RX_BASE		0x100
+#define HSDMA_REG_RX_CNT		0x104
+#define HSDMA_REG_RX_CRX		0x108
+#define HSDMA_REG_RX_DRX		0x10c
+#define HSDMA_REG_INFO			0x200
+#define HSDMA_REG_GLO_CFG		0x204
+#define HSDMA_REG_RST_CFG		0x208
+#define HSDMA_REG_DELAY_INT		0x20c
+#define HSDMA_REG_FREEQ_THRES		0x210
+#define HSDMA_REG_INT_STATUS		0x220
+#define HSDMA_REG_INT_MASK		0x228
+#define HSDMA_REG_SCH_Q01		0x280
+#define HSDMA_REG_SCH_Q23		0x284
+
+#define HSDMA_DESCS_MAX			0xfff
+#define HSDMA_DESCS_NUM			8
+#define HSDMA_DESCS_MASK		(HSDMA_DESCS_NUM - 1)
+#define HSDMA_NEXT_DESC(x)		(((x) + 1) & HSDMA_DESCS_MASK)
+
+/* HSDMA_REG_INFO */
+#define HSDMA_INFO_INDEX_MASK		0xf
+#define HSDMA_INFO_INDEX_SHIFT		24
+#define HSDMA_INFO_BASE_MASK		0xff
+#define HSDMA_INFO_BASE_SHIFT		16
+#define HSDMA_INFO_RX_MASK		0xff
+#define HSDMA_INFO_RX_SHIFT		8
+#define HSDMA_INFO_TX_MASK		0xff
+#define HSDMA_INFO_TX_SHIFT		0
+
+/* HSDMA_REG_GLO_CFG */
+#define HSDMA_GLO_TX_2B_OFFSET		BIT(31)
+#define HSDMA_GLO_CLK_GATE		BIT(30)
+#define HSDMA_GLO_BYTE_SWAP		BIT(29)
+#define HSDMA_GLO_MULTI_DMA		BIT(10)
+#define HSDMA_GLO_TWO_BUF		BIT(9)
+#define HSDMA_GLO_32B_DESC		BIT(8)
+#define HSDMA_GLO_BIG_ENDIAN		BIT(7)
+#define HSDMA_GLO_TX_DONE		BIT(6)
+#define HSDMA_GLO_BT_MASK		0x3
+#define HSDMA_GLO_BT_SHIFT		4
+#define HSDMA_GLO_RX_BUSY		BIT(3)
+#define HSDMA_GLO_RX_DMA		BIT(2)
+#define HSDMA_GLO_TX_BUSY		BIT(1)
+#define HSDMA_GLO_TX_DMA		BIT(0)
+
+#define HSDMA_BT_SIZE_16BYTES		(0 << HSDMA_GLO_BT_SHIFT)
+#define HSDMA_BT_SIZE_32BYTES		(1 << HSDMA_GLO_BT_SHIFT)
+#define HSDMA_BT_SIZE_64BYTES		(2 << HSDMA_GLO_BT_SHIFT)
+#define HSDMA_BT_SIZE_128BYTES		(3 << HSDMA_GLO_BT_SHIFT)
+
+#define HSDMA_GLO_DEFAULT		(HSDMA_GLO_MULTI_DMA | \
+		HSDMA_GLO_RX_DMA | HSDMA_GLO_TX_DMA | HSDMA_BT_SIZE_32BYTES)
+
+/* HSDMA_REG_RST_CFG */
+#define HSDMA_RST_RX_SHIFT		16
+#define HSDMA_RST_TX_SHIFT		0
+
+/* HSDMA_REG_DELAY_INT */
+#define HSDMA_DELAY_INT_EN		BIT(15)
+#define HSDMA_DELAY_PEND_OFFSET		8
+#define HSDMA_DELAY_TIME_OFFSET		0
+#define HSDMA_DELAY_TX_OFFSET		16
+#define HSDMA_DELAY_RX_OFFSET		0
+
+#define HSDMA_DELAY_INIT(x)		(HSDMA_DELAY_INT_EN | \
+		((x) << HSDMA_DELAY_PEND_OFFSET))
+#define HSDMA_DELAY(x)			((HSDMA_DELAY_INIT(x) << \
+		HSDMA_DELAY_TX_OFFSET) | HSDMA_DELAY_INIT(x))
+
+/* HSDMA_REG_INT_STATUS */
+#define HSDMA_INT_DELAY_RX_COH		BIT(31)
+#define HSDMA_INT_DELAY_RX_INT		BIT(30)
+#define HSDMA_INT_DELAY_TX_COH		BIT(29)
+#define HSDMA_INT_DELAY_TX_INT		BIT(28)
+#define HSDMA_INT_RX_MASK		0x3
+#define HSDMA_INT_RX_SHIFT		16
+#define HSDMA_INT_RX_Q0			BIT(16)
+#define HSDMA_INT_TX_MASK		0xf
+#define HSDMA_INT_TX_SHIFT		0
+#define HSDMA_INT_TX_Q0			BIT(0)
+
+/* tx/rx dma desc flags */
+#define HSDMA_PLEN_MASK			0x3fff
+#define HSDMA_DESC_DONE			BIT(31)
+#define HSDMA_DESC_LS0			BIT(30)
+#define HSDMA_DESC_PLEN0(_x)		(((_x) & HSDMA_PLEN_MASK) << 16)
+#define HSDMA_DESC_TAG			BIT(15)
+#define HSDMA_DESC_LS1			BIT(14)
+#define HSDMA_DESC_PLEN1(_x)		((_x) & HSDMA_PLEN_MASK)
+
+/* align 4 bytes */
+#define HSDMA_ALIGN_SIZE		3
+/* align size 128bytes */
+#define HSDMA_MAX_PLEN			0x3f80
+
+struct hsdma_desc {
+	u32 addr0;
+	u32 flags;
+	u32 addr1;
+	u32 unused;
+};
+
+struct mtk_hsdma_sg {
+	dma_addr_t src_addr;
+	dma_addr_t dst_addr;
+	u32 len;
+};
+
+struct mtk_hsdma_desc {
+	struct virt_dma_desc vdesc;
+	unsigned int num_sgs;
+	struct mtk_hsdma_sg sg[1];
+};
+
+struct mtk_hsdma_chan {
+	struct virt_dma_chan vchan;
+	unsigned int id;
+	dma_addr_t desc_addr;
+	int tx_idx;
+	int rx_idx;
+	struct hsdma_desc *tx_ring;
+	struct hsdma_desc *rx_ring;
+	struct mtk_hsdma_desc *desc;
+	unsigned int next_sg;
+};
+
+struct mtk_hsdam_engine {
+	struct dma_device ddev;
+	struct device_dma_parameters dma_parms;
+	void __iomem *base;
+	struct tasklet_struct task;
+	volatile unsigned long chan_issued;
+
+	struct mtk_hsdma_chan chan[1];
+};
+
+static inline struct mtk_hsdam_engine *mtk_hsdma_chan_get_dev(struct mtk_hsdma_chan *chan)
+{
+	return container_of(chan->vchan.chan.device, struct mtk_hsdam_engine,
+			ddev);
+}
+
+static inline struct mtk_hsdma_chan *to_mtk_hsdma_chan(struct dma_chan *c)
+{
+	return container_of(c, struct mtk_hsdma_chan, vchan.chan);
+}
+
+static inline struct mtk_hsdma_desc *to_mtk_hsdma_desc(struct virt_dma_desc *vdesc)
+{
+	return container_of(vdesc, struct mtk_hsdma_desc, vdesc);
+}
+
+static inline u32 mtk_hsdma_read(struct mtk_hsdam_engine *hsdma, u32 reg)
+{
+	return readl(hsdma->base + reg);
+}
+
+static inline void mtk_hsdma_write(struct mtk_hsdam_engine *hsdma,
+				   unsigned int reg, u32 val)
+{
+	writel(val, hsdma->base + reg);
+}
+
+static void mtk_hsdma_reset_chan(struct mtk_hsdam_engine *hsdma,
+				 struct mtk_hsdma_chan *chan)
+{
+	chan->tx_idx = 0;
+	chan->rx_idx = HSDMA_DESCS_NUM - 1;
+
+	mtk_hsdma_write(hsdma, HSDMA_REG_TX_CTX, chan->tx_idx);
+	mtk_hsdma_write(hsdma, HSDMA_REG_RX_CRX, chan->rx_idx);
+
+	mtk_hsdma_write(hsdma, HSDMA_REG_RST_CFG,
+			0x1 << (chan->id + HSDMA_RST_TX_SHIFT));
+	mtk_hsdma_write(hsdma, HSDMA_REG_RST_CFG,
+			0x1 << (chan->id + HSDMA_RST_RX_SHIFT));
+}
+
+static void hsdma_dump_reg(struct mtk_hsdam_engine *hsdma)
+{
+	dev_dbg(hsdma->ddev.dev,
+		"tbase %08x, tcnt %08x, tctx %08x, tdtx: %08x, rbase %08x, rcnt %08x, rctx %08x, rdtx %08x\n",
+		mtk_hsdma_read(hsdma, HSDMA_REG_TX_BASE),
+		mtk_hsdma_read(hsdma, HSDMA_REG_TX_CNT),
+		mtk_hsdma_read(hsdma, HSDMA_REG_TX_CTX),
+		mtk_hsdma_read(hsdma, HSDMA_REG_TX_DTX),
+		mtk_hsdma_read(hsdma, HSDMA_REG_RX_BASE),
+		mtk_hsdma_read(hsdma, HSDMA_REG_RX_CNT),
+		mtk_hsdma_read(hsdma, HSDMA_REG_RX_CRX),
+		mtk_hsdma_read(hsdma, HSDMA_REG_RX_DRX));
+
+	dev_dbg(hsdma->ddev.dev,
+		"info %08x, glo %08x, delay %08x, intr_stat %08x, intr_mask %08x\n",
+		mtk_hsdma_read(hsdma, HSDMA_REG_INFO),
+		mtk_hsdma_read(hsdma, HSDMA_REG_GLO_CFG),
+		mtk_hsdma_read(hsdma, HSDMA_REG_DELAY_INT),
+		mtk_hsdma_read(hsdma, HSDMA_REG_INT_STATUS),
+		mtk_hsdma_read(hsdma, HSDMA_REG_INT_MASK));
+}
+
+static void hsdma_dump_desc(struct mtk_hsdam_engine *hsdma,
+			    struct mtk_hsdma_chan *chan)
+{
+	struct hsdma_desc *tx_desc;
+	struct hsdma_desc *rx_desc;
+	int i;
+
+	dev_dbg(hsdma->ddev.dev, "tx idx: %d, rx idx: %d\n",
+		chan->tx_idx, chan->rx_idx);
+
+	for (i = 0; i < HSDMA_DESCS_NUM; i++) {
+		tx_desc = &chan->tx_ring[i];
+		rx_desc = &chan->rx_ring[i];
+
+		dev_dbg(hsdma->ddev.dev,
+			"%d tx addr0: %08x, flags %08x, tx addr1: %08x, rx addr0 %08x, flags %08x\n",
+			i, tx_desc->addr0, tx_desc->flags,
+			tx_desc->addr1, rx_desc->addr0, rx_desc->flags);
+	}
+}
+
+static void mtk_hsdma_reset(struct mtk_hsdam_engine *hsdma,
+			    struct mtk_hsdma_chan *chan)
+{
+	int i;
+
+	/* disable dma */
+	mtk_hsdma_write(hsdma, HSDMA_REG_GLO_CFG, 0);
+
+	/* disable intr */
+	mtk_hsdma_write(hsdma, HSDMA_REG_INT_MASK, 0);
+
+	/* init desc value */
+	for (i = 0; i < HSDMA_DESCS_NUM; i++) {
+		chan->tx_ring[i].addr0 = 0;
+		chan->tx_ring[i].flags = HSDMA_DESC_LS0 | HSDMA_DESC_DONE;
+	}
+	for (i = 0; i < HSDMA_DESCS_NUM; i++) {
+		chan->rx_ring[i].addr0 = 0;
+		chan->rx_ring[i].flags = 0;
+	}
+
+	/* reset */
+	mtk_hsdma_reset_chan(hsdma, chan);
+
+	/* enable intr */
+	mtk_hsdma_write(hsdma, HSDMA_REG_INT_MASK, HSDMA_INT_RX_Q0);
+
+	/* enable dma */
+	mtk_hsdma_write(hsdma, HSDMA_REG_GLO_CFG, HSDMA_GLO_DEFAULT);
+}
+
+static int mtk_hsdma_terminate_all(struct dma_chan *c)
+{
+	struct mtk_hsdma_chan *chan = to_mtk_hsdma_chan(c);
+	struct mtk_hsdam_engine *hsdma = mtk_hsdma_chan_get_dev(chan);
+	unsigned long timeout;
+	LIST_HEAD(head);
+
+	spin_lock_bh(&chan->vchan.lock);
+	chan->desc = NULL;
+	clear_bit(chan->id, &hsdma->chan_issued);
+	vchan_get_all_descriptors(&chan->vchan, &head);
+	spin_unlock_bh(&chan->vchan.lock);
+
+	vchan_dma_desc_free_list(&chan->vchan, &head);
+
+	/* wait dma transfer complete */
+	timeout = jiffies + msecs_to_jiffies(2000);
+	while (mtk_hsdma_read(hsdma, HSDMA_REG_GLO_CFG) &
+			(HSDMA_GLO_RX_BUSY | HSDMA_GLO_TX_BUSY)) {
+		if (time_after_eq(jiffies, timeout)) {
+			hsdma_dump_desc(hsdma, chan);
+			mtk_hsdma_reset(hsdma, chan);
+			dev_err(hsdma->ddev.dev, "timeout, reset it\n");
+			break;
+		}
+		cpu_relax();
+	}
+
+	return 0;
+}
+
+static int mtk_hsdma_start_transfer(struct mtk_hsdam_engine *hsdma,
+				    struct mtk_hsdma_chan *chan)
+{
+	dma_addr_t src, dst;
+	size_t len, tlen;
+	struct hsdma_desc *tx_desc, *rx_desc;
+	struct mtk_hsdma_sg *sg;
+	unsigned int i;
+	int rx_idx;
+
+	sg = &chan->desc->sg[0];
+	len = sg->len;
+	chan->desc->num_sgs = DIV_ROUND_UP(len, HSDMA_MAX_PLEN);
+
+	/* tx desc */
+	src = sg->src_addr;
+	for (i = 0; i < chan->desc->num_sgs; i++) {
+		tx_desc = &chan->tx_ring[chan->tx_idx];
+
+		if (len > HSDMA_MAX_PLEN)
+			tlen = HSDMA_MAX_PLEN;
+		else
+			tlen = len;
+
+		if (i & 0x1) {
+			tx_desc->addr1 = src;
+			tx_desc->flags |= HSDMA_DESC_PLEN1(tlen);
+		} else {
+			tx_desc->addr0 = src;
+			tx_desc->flags = HSDMA_DESC_PLEN0(tlen);
+
+			/* update index */
+			chan->tx_idx = HSDMA_NEXT_DESC(chan->tx_idx);
+		}
+
+		src += tlen;
+		len -= tlen;
+	}
+	if (i & 0x1)
+		tx_desc->flags |= HSDMA_DESC_LS0;
+	else
+		tx_desc->flags |= HSDMA_DESC_LS1;
+
+	/* rx desc */
+	rx_idx = HSDMA_NEXT_DESC(chan->rx_idx);
+	len = sg->len;
+	dst = sg->dst_addr;
+	for (i = 0; i < chan->desc->num_sgs; i++) {
+		rx_desc = &chan->rx_ring[rx_idx];
+		if (len > HSDMA_MAX_PLEN)
+			tlen = HSDMA_MAX_PLEN;
+		else
+			tlen = len;
+
+		rx_desc->addr0 = dst;
+		rx_desc->flags = HSDMA_DESC_PLEN0(tlen);
+
+		dst += tlen;
+		len -= tlen;
+
+		/* update index */
+		rx_idx = HSDMA_NEXT_DESC(rx_idx);
+	}
+
+	/* make sure desc and index all up to date */
+	wmb();
+	mtk_hsdma_write(hsdma, HSDMA_REG_TX_CTX, chan->tx_idx);
+
+	return 0;
+}
+
+static int gdma_next_desc(struct mtk_hsdma_chan *chan)
+{
+	struct virt_dma_desc *vdesc;
+
+	vdesc = vchan_next_desc(&chan->vchan);
+	if (!vdesc) {
+		chan->desc = NULL;
+		return 0;
+	}
+	chan->desc = to_mtk_hsdma_desc(vdesc);
+	chan->next_sg = 0;
+
+	return 1;
+}
+
+static void mtk_hsdma_chan_done(struct mtk_hsdam_engine *hsdma,
+				struct mtk_hsdma_chan *chan)
+{
+	struct mtk_hsdma_desc *desc;
+	int chan_issued;
+
+	chan_issued = 0;
+	spin_lock_bh(&chan->vchan.lock);
+	desc = chan->desc;
+	if (likely(desc)) {
+		if (chan->next_sg == desc->num_sgs) {
+			list_del(&desc->vdesc.node);
+			vchan_cookie_complete(&desc->vdesc);
+			chan_issued = gdma_next_desc(chan);
+		}
+	} else {
+		dev_dbg(hsdma->ddev.dev, "no desc to complete\n");
+	}
+
+	if (chan_issued)
+		set_bit(chan->id, &hsdma->chan_issued);
+	spin_unlock_bh(&chan->vchan.lock);
+}
+
+static irqreturn_t mtk_hsdma_irq(int irq, void *devid)
+{
+	struct mtk_hsdam_engine *hsdma = devid;
+	u32 status;
+
+	status = mtk_hsdma_read(hsdma, HSDMA_REG_INT_STATUS);
+	if (unlikely(!status))
+		return IRQ_NONE;
+
+	if (likely(status & HSDMA_INT_RX_Q0))
+		tasklet_schedule(&hsdma->task);
+	else
+		dev_dbg(hsdma->ddev.dev, "unhandle irq status %08x\n", status);
+	/* clean intr bits */
+	mtk_hsdma_write(hsdma, HSDMA_REG_INT_STATUS, status);
+
+	return IRQ_HANDLED;
+}
+
+static void mtk_hsdma_issue_pending(struct dma_chan *c)
+{
+	struct mtk_hsdma_chan *chan = to_mtk_hsdma_chan(c);
+	struct mtk_hsdam_engine *hsdma = mtk_hsdma_chan_get_dev(chan);
+
+	spin_lock_bh(&chan->vchan.lock);
+	if (vchan_issue_pending(&chan->vchan) && !chan->desc) {
+		if (gdma_next_desc(chan)) {
+			set_bit(chan->id, &hsdma->chan_issued);
+			tasklet_schedule(&hsdma->task);
+		} else {
+			dev_dbg(hsdma->ddev.dev, "no desc to issue\n");
+		}
+	}
+	spin_unlock_bh(&chan->vchan.lock);
+}
+
+static struct dma_async_tx_descriptor *mtk_hsdma_prep_dma_memcpy(
+		struct dma_chan *c, dma_addr_t dest, dma_addr_t src,
+		size_t len, unsigned long flags)
+{
+	struct mtk_hsdma_chan *chan = to_mtk_hsdma_chan(c);
+	struct mtk_hsdma_desc *desc;
+
+	if (len <= 0)
+		return NULL;
+
+	desc = kzalloc(sizeof(*desc), GFP_ATOMIC);
+	if (!desc) {
+		dev_err(c->device->dev, "alloc memcpy decs error\n");
+		return NULL;
+	}
+
+	desc->sg[0].src_addr = src;
+	desc->sg[0].dst_addr = dest;
+	desc->sg[0].len = len;
+
+	return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
+}
+
+static enum dma_status mtk_hsdma_tx_status(struct dma_chan *c,
+					   dma_cookie_t cookie,
+					   struct dma_tx_state *state)
+{
+	return dma_cookie_status(c, cookie, state);
+}
+
+static void mtk_hsdma_free_chan_resources(struct dma_chan *c)
+{
+	vchan_free_chan_resources(to_virt_chan(c));
+}
+
+static void mtk_hsdma_desc_free(struct virt_dma_desc *vdesc)
+{
+	kfree(container_of(vdesc, struct mtk_hsdma_desc, vdesc));
+}
+
+static void mtk_hsdma_tx(struct mtk_hsdam_engine *hsdma)
+{
+	struct mtk_hsdma_chan *chan;
+
+	if (test_and_clear_bit(0, &hsdma->chan_issued)) {
+		chan = &hsdma->chan[0];
+		if (chan->desc)
+			mtk_hsdma_start_transfer(hsdma, chan);
+		else
+			dev_dbg(hsdma->ddev.dev, "chan 0 no desc to issue\n");
+	}
+}
+
+static void mtk_hsdma_rx(struct mtk_hsdam_engine *hsdma)
+{
+	struct mtk_hsdma_chan *chan;
+	int next_idx, drx_idx, cnt;
+
+	chan = &hsdma->chan[0];
+	next_idx = HSDMA_NEXT_DESC(chan->rx_idx);
+	drx_idx = mtk_hsdma_read(hsdma, HSDMA_REG_RX_DRX);
+
+	cnt = (drx_idx - next_idx) & HSDMA_DESCS_MASK;
+	if (!cnt)
+		return;
+
+	chan->next_sg += cnt;
+	chan->rx_idx = (chan->rx_idx + cnt) & HSDMA_DESCS_MASK;
+
+	/* update rx crx */
+	wmb();
+	mtk_hsdma_write(hsdma, HSDMA_REG_RX_CRX, chan->rx_idx);
+
+	mtk_hsdma_chan_done(hsdma, chan);
+}
+
+static void mtk_hsdma_tasklet(struct tasklet_struct *t)
+{
+	struct mtk_hsdam_engine *hsdma = from_tasklet(hsdma, t, task);
+
+	mtk_hsdma_rx(hsdma);
+	mtk_hsdma_tx(hsdma);
+}
+
+static int mtk_hsdam_alloc_desc(struct mtk_hsdam_engine *hsdma,
+				struct mtk_hsdma_chan *chan)
+{
+	int i;
+
+	chan->tx_ring = dma_alloc_coherent(hsdma->ddev.dev,
+					   2 * HSDMA_DESCS_NUM *
+					   sizeof(*chan->tx_ring),
+			&chan->desc_addr, GFP_ATOMIC | __GFP_ZERO);
+	if (!chan->tx_ring)
+		goto no_mem;
+
+	chan->rx_ring = &chan->tx_ring[HSDMA_DESCS_NUM];
+
+	/* init tx ring value */
+	for (i = 0; i < HSDMA_DESCS_NUM; i++)
+		chan->tx_ring[i].flags = HSDMA_DESC_LS0 | HSDMA_DESC_DONE;
+
+	return 0;
+no_mem:
+	return -ENOMEM;
+}
+
+static void mtk_hsdam_free_desc(struct mtk_hsdam_engine *hsdma,
+				struct mtk_hsdma_chan *chan)
+{
+	if (chan->tx_ring) {
+		dma_free_coherent(hsdma->ddev.dev,
+				  2 * HSDMA_DESCS_NUM * sizeof(*chan->tx_ring),
+				  chan->tx_ring, chan->desc_addr);
+		chan->tx_ring = NULL;
+		chan->rx_ring = NULL;
+	}
+}
+
+static int mtk_hsdma_init(struct mtk_hsdam_engine *hsdma)
+{
+	struct mtk_hsdma_chan *chan;
+	int ret;
+	u32 reg;
+
+	/* init desc */
+	chan = &hsdma->chan[0];
+	ret = mtk_hsdam_alloc_desc(hsdma, chan);
+	if (ret)
+		return ret;
+
+	/* tx */
+	mtk_hsdma_write(hsdma, HSDMA_REG_TX_BASE, chan->desc_addr);
+	mtk_hsdma_write(hsdma, HSDMA_REG_TX_CNT, HSDMA_DESCS_NUM);
+	/* rx */
+	mtk_hsdma_write(hsdma, HSDMA_REG_RX_BASE, chan->desc_addr +
+			(sizeof(struct hsdma_desc) * HSDMA_DESCS_NUM));
+	mtk_hsdma_write(hsdma, HSDMA_REG_RX_CNT, HSDMA_DESCS_NUM);
+	/* reset */
+	mtk_hsdma_reset_chan(hsdma, chan);
+
+	/* enable rx intr */
+	mtk_hsdma_write(hsdma, HSDMA_REG_INT_MASK, HSDMA_INT_RX_Q0);
+
+	/* enable dma */
+	mtk_hsdma_write(hsdma, HSDMA_REG_GLO_CFG, HSDMA_GLO_DEFAULT);
+
+	/* hardware info */
+	reg = mtk_hsdma_read(hsdma, HSDMA_REG_INFO);
+	dev_info(hsdma->ddev.dev, "rx: %d, tx: %d\n",
+		 (reg >> HSDMA_INFO_RX_SHIFT) & HSDMA_INFO_RX_MASK,
+		 (reg >> HSDMA_INFO_TX_SHIFT) & HSDMA_INFO_TX_MASK);
+
+	hsdma_dump_reg(hsdma);
+
+	return ret;
+}
+
+static void mtk_hsdma_uninit(struct mtk_hsdam_engine *hsdma)
+{
+	struct mtk_hsdma_chan *chan;
+
+	/* disable dma */
+	mtk_hsdma_write(hsdma, HSDMA_REG_GLO_CFG, 0);
+
+	/* disable intr */
+	mtk_hsdma_write(hsdma, HSDMA_REG_INT_MASK, 0);
+
+	/* free desc */
+	chan = &hsdma->chan[0];
+	mtk_hsdam_free_desc(hsdma, chan);
+
+	/* tx */
+	mtk_hsdma_write(hsdma, HSDMA_REG_TX_BASE, 0);
+	mtk_hsdma_write(hsdma, HSDMA_REG_TX_CNT, 0);
+	/* rx */
+	mtk_hsdma_write(hsdma, HSDMA_REG_RX_BASE, 0);
+	mtk_hsdma_write(hsdma, HSDMA_REG_RX_CNT, 0);
+	/* reset */
+	mtk_hsdma_reset_chan(hsdma, chan);
+}
+
+static const struct of_device_id mtk_hsdma_of_match[] = {
+	{ .compatible = "mediatek,mt7621-hsdma" },
+	{ },
+};
+
+static int mtk_hsdma_probe(struct platform_device *pdev)
+{
+	const struct of_device_id *match;
+	struct mtk_hsdma_chan *chan;
+	struct mtk_hsdam_engine *hsdma;
+	struct dma_device *dd;
+	int ret;
+	int irq;
+	void __iomem *base;
+
+	ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
+	if (ret)
+		return ret;
+
+	match = of_match_device(mtk_hsdma_of_match, &pdev->dev);
+	if (!match)
+		return -EINVAL;
+
+	hsdma = devm_kzalloc(&pdev->dev, sizeof(*hsdma), GFP_KERNEL);
+	if (!hsdma)
+		return -EINVAL;
+
+	base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+	hsdma->base = base + HSDMA_BASE_OFFSET;
+	tasklet_setup(&hsdma->task, mtk_hsdma_tasklet);
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0)
+		return -EINVAL;
+	ret = devm_request_irq(&pdev->dev, irq, mtk_hsdma_irq,
+			       0, dev_name(&pdev->dev), hsdma);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to request irq\n");
+		return ret;
+	}
+
+	ret = device_reset(&pdev->dev);
+	if (ret)
+		dev_err(&pdev->dev, "failed to reset device\n");
+
+	dd = &hsdma->ddev;
+	dma_cap_set(DMA_MEMCPY, dd->cap_mask);
+	dd->copy_align = HSDMA_ALIGN_SIZE;
+	dd->device_free_chan_resources = mtk_hsdma_free_chan_resources;
+	dd->device_prep_dma_memcpy = mtk_hsdma_prep_dma_memcpy;
+	dd->device_terminate_all = mtk_hsdma_terminate_all;
+	dd->device_tx_status = mtk_hsdma_tx_status;
+	dd->device_issue_pending = mtk_hsdma_issue_pending;
+	dd->dev = &pdev->dev;
+	dd->dev->dma_parms = &hsdma->dma_parms;
+	dma_set_max_seg_size(dd->dev, HSDMA_MAX_PLEN);
+	INIT_LIST_HEAD(&dd->channels);
+
+	chan = &hsdma->chan[0];
+	chan->id = 0;
+	chan->vchan.desc_free = mtk_hsdma_desc_free;
+	vchan_init(&chan->vchan, dd);
+
+	/* init hardware */
+	ret = mtk_hsdma_init(hsdma);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to alloc ring descs\n");
+		return ret;
+	}
+
+	ret = dma_async_device_register(dd);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to register dma device\n");
+		goto err_uninit_hsdma;
+	}
+
+	ret = of_dma_controller_register(pdev->dev.of_node,
+					 of_dma_xlate_by_chan_id, hsdma);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to register of dma controller\n");
+		goto err_unregister;
+	}
+
+	platform_set_drvdata(pdev, hsdma);
+
+	return 0;
+
+err_unregister:
+	dma_async_device_unregister(dd);
+err_uninit_hsdma:
+	mtk_hsdma_uninit(hsdma);
+	return ret;
+}
+
+static int mtk_hsdma_remove(struct platform_device *pdev)
+{
+	struct mtk_hsdam_engine *hsdma = platform_get_drvdata(pdev);
+
+	mtk_hsdma_uninit(hsdma);
+
+	of_dma_controller_free(pdev->dev.of_node);
+	dma_async_device_unregister(&hsdma->ddev);
+
+	return 0;
+}
+
+static struct platform_driver mtk_hsdma_driver = {
+	.probe = mtk_hsdma_probe,
+	.remove = mtk_hsdma_remove,
+	.driver = {
+		.name = KBUILD_MODNAME,
+		.of_match_table = mtk_hsdma_of_match,
+	},
+};
+module_platform_driver(mtk_hsdma_driver);
+
+MODULE_AUTHOR("Michael Lee <igvtee@gmail.com>");
+MODULE_DESCRIPTION("MTK HSDMA driver");
+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/ethtool.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/ethtool.c
index a3abf30c71c74b..92cf0ef717dde0 100644
--- a/target/linux/ramips/files/drivers/net/ethernet/ralink/ethtool.c
+++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/ethtool.c
@@ -125,8 +125,15 @@ static u32 fe_get_link(struct net_device *dev)
 	return ethtool_op_get_link(dev);
 }
 
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 1, 0)
+static int fe_set_ringparam(struct net_device *dev,
+			    struct ethtool_ringparam *ring,
+			    struct kernel_ethtool_ringparam *kernel_rp,
+			    struct netlink_ext_ack *extack)
+#else
 static int fe_set_ringparam(struct net_device *dev,
 			    struct ethtool_ringparam *ring)
+#endif
 {
 	struct fe_priv *priv = netdev_priv(dev);
 
@@ -146,8 +153,15 @@ static int fe_set_ringparam(struct net_device *dev,
 	return 0;
 }
 
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 1, 0)
+static void fe_get_ringparam(struct net_device *dev,
+			     struct ethtool_ringparam *ring,
+			     struct kernel_ethtool_ringparam *kernel_rp,
+			     struct netlink_ext_ack *extack)
+#else
 static void fe_get_ringparam(struct net_device *dev,
 			     struct ethtool_ringparam *ring)
+#endif
 {
 	struct fe_priv *priv = netdev_priv(dev);
 
diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.c
index c741c85f4a5599..dda9abee493d47 100644
--- a/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.c
+++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.c
@@ -152,7 +152,7 @@ static inline void fe_int_enable(u32 mask)
 	fe_reg_r32(FE_REG_FE_INT_ENABLE);
 }
 
-static inline void fe_hw_set_macaddr(struct fe_priv *priv, unsigned char *mac)
+static inline void fe_hw_set_macaddr(struct fe_priv *priv, const unsigned char *mac)
 {
 	unsigned long flags;
 
@@ -1365,10 +1365,8 @@ static int __init fe_init(struct net_device *dev)
 
 	fe_reset_phy(priv);
 
-	of_get_mac_address(priv->dev->of_node, dev->dev_addr);
-
-	/* If the mac address is invalid, use random mac address  */
-	if (!is_valid_ether_addr(dev->dev_addr)) {
+	/* Set the MAC address if it is correct, if not use a random MAC address  */
+	if (of_get_ethdev_address(priv->dev->of_node, dev)) {
 		eth_hw_addr_random(dev);
 		dev_err(priv->dev, "generated random MAC address %pM\n",
 			dev->dev_addr);
@@ -1603,6 +1601,7 @@ static int fe_probe(struct platform_device *pdev)
 			goto err_free_dev;
 		}
 		spin_lock_init(&priv->hw_stats->stats_lock);
+		u64_stats_init(&priv->hw_stats->syncp);
 	}
 
 	sysclk = devm_clk_get(&pdev->dev, NULL);
@@ -1630,7 +1629,6 @@ static int fe_probe(struct platform_device *pdev)
 	priv->tx_ring.tx_ring_size = NUM_DMA_DESC;
 	priv->rx_ring.rx_ring_size = NUM_DMA_DESC;
 	INIT_WORK(&priv->pending_work, fe_pending_work);
-	u64_stats_init(&priv->hw_stats->syncp);
 
 	napi_weight = 16;
 	if (priv->flags & FE_FLAG_NAPI_WEIGHT) {
@@ -1638,7 +1636,11 @@ static int fe_probe(struct platform_device *pdev)
 		priv->tx_ring.tx_ring_size *= 4;
 		priv->rx_ring.rx_ring_size *= 4;
 	}
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 1, 0)
+	netif_napi_add_weight(netdev, &priv->rx_napi, fe_poll, napi_weight);
+#else
 	netif_napi_add(netdev, &priv->rx_napi, fe_poll, napi_weight);
+#endif
 	fe_set_ethtool_ops(netdev);
 
 	err = register_netdev(netdev);
diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.h b/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.h
index 7b291ff43e5e26..364dd54a58f121 100644
--- a/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.h
+++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.h
@@ -378,7 +378,7 @@ struct fe_soc_data {
 	const u16 *reg_table;
 
 	void (*init_data)(struct fe_soc_data *data, struct net_device *netdev);
-	void (*set_mac)(struct fe_priv *priv, unsigned char *mac);
+	void (*set_mac)(struct fe_priv *priv, const unsigned char *mac);
 	int (*fwd_config)(struct fe_priv *priv);
 	void (*tx_dma)(struct fe_tx_dma *txd);
 	int (*switch_init)(struct fe_priv *priv);
diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c
index 172dda11b75575..e2b2aceff958fc 100644
--- a/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c
+++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c
@@ -107,7 +107,7 @@ static int mt7620_gsw_config(struct fe_priv *priv)
 	return 0;
 }
 
-static void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac)
+static void mt7620_set_mac(struct fe_priv *priv, const unsigned char *mac)
 {
 	struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
 	unsigned long flags;
diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_rt3050.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_rt3050.c
index 435f007477883e..3f961797ed4247 100644
--- a/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_rt3050.c
+++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_rt3050.c
@@ -76,7 +76,7 @@ static void rt5350_init_data(struct fe_soc_data *data,
 	netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM;
 }
 
-static void rt5350_set_mac(struct fe_priv *priv, unsigned char *mac)
+static void rt5350_set_mac(struct fe_priv *priv, const unsigned char *mac)
 {
 	unsigned long flags;
 
diff --git a/target/linux/ramips/files/drivers/pinctrl/pinctrl-aw9523.c b/target/linux/ramips/files/drivers/pinctrl/pinctrl-aw9523.c
index 4900c5a0c0e0fb..e151f445901574 100644
--- a/target/linux/ramips/files/drivers/pinctrl/pinctrl-aw9523.c
+++ b/target/linux/ramips/files/drivers/pinctrl/pinctrl-aw9523.c
@@ -1097,6 +1097,13 @@ static int aw9523_remove(struct i2c_client *client)
 	return 0;
 }
 
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 1, 0)
+static void aw9523_remove_void(struct i2c_client *client)
+{
+	aw9523_remove(client);
+}
+#endif
+
 static const struct i2c_device_id aw9523_i2c_id_table[] = {
 	{ "aw9523_i2c", 0 },
 	{ }
@@ -1114,7 +1121,11 @@ static struct i2c_driver aw9523_driver = {
 		.of_match_table = of_aw9523_i2c_match,
 	},
 	.probe = aw9523_probe,
+	#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 1, 0)
+	.remove = aw9523_remove_void,
+	#else
 	.remove = aw9523_remove,
+	#endif
 	.id_table = aw9523_i2c_id_table,
 };
 module_i2c_driver(aw9523_driver);
diff --git a/target/linux/ramips/image/mt7620.mk b/target/linux/ramips/image/mt7620.mk
index 883aacabe06268..04c32629208361 100644
--- a/target/linux/ramips/image/mt7620.mk
+++ b/target/linux/ramips/image/mt7620.mk
@@ -1214,6 +1214,23 @@ define Device/tplink_archer-c2-v1
 endef
 TARGET_DEVICES += tplink_archer-c2-v1
 
+define Device/tplink_archer-c5-v4
+  $(Device/tplink-v2)
+  SOC := mt7620a
+  IMAGE_SIZE := 7808k
+  TPLINK_FLASHLAYOUT := 8Mmtk
+  TPLINK_HWID := 0x04da857c
+  TPLINK_HWREV := 0x0c000600
+  TPLINK_HWREVADD := 0x04000000
+  IMAGES += tftp-recovery.bin
+  IMAGE/tftp-recovery.bin := pad-extra 128k | $$(IMAGE/factory.bin)
+  DEVICE_MODEL := Archer C5
+  DEVICE_VARIANT := v4
+  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci kmod-usb-ledtrig-usbport \
+	kmod-mt76x2 kmod-switch-rtl8367b
+endef
+TARGET_DEVICES += tplink_archer-c5-v4
+
 define Device/tplink_archer-c50-v1
   $(Device/tplink-v2)
   SOC := mt7620a
diff --git a/target/linux/ramips/image/mt76x8.mk b/target/linux/ramips/image/mt76x8.mk
index 9a458d38f39218..656820be145c36 100644
--- a/target/linux/ramips/image/mt76x8.mk
+++ b/target/linux/ramips/image/mt76x8.mk
@@ -493,7 +493,7 @@ define Device/ravpower_rp-wd009
   IMAGE_SIZE := 14272k
   DEVICE_VENDOR := RAVPower
   DEVICE_MODEL := RP-WD009
-  UBOOT_PATH := $(STAGING_DIR_IMAGE)/ravpower_rp-wd009-u-boot.bin
+  UBOOT_PATH := $(STAGING_DIR_IMAGE)/mt7628_ravpower_rp-wd009-u-boot.bin
   DEVICE_PACKAGES := kmod-mt76x0e kmod-usb2 kmod-usb-ohci \
 	kmod-sdhci-mt7620 kmod-i2c-mt7628 ravpower-mcu
   IMAGES += factory.bin
diff --git a/target/linux/ramips/modules.mk b/target/linux/ramips/modules.mk
index 1127a8f8ab7f45..4a8739fe5c40a5 100644
--- a/target/linux/ramips/modules.mk
+++ b/target/linux/ramips/modules.mk
@@ -101,7 +101,8 @@ define KernelPackage/hsdma-mtk
 	CONFIG_MTK_HSDMA
   FILES:= \
 	$(LINUX_DIR)/drivers/dma/virt-dma.ko \
-	$(LINUX_DIR)/drivers/staging/mt7621-dma/hsdma-mt7621.ko
+	$(LINUX_DIR)/drivers/staging/mt7621-dma/hsdma-mt7621.ko@lt5.17 \
+	$(LINUX_DIR)/drivers/dma/mediatek/hsdma-mt7621.ko@ge5.17
   AUTOLOAD:=$(call AutoLoad,53,hsdma-mt7621)
 endef
 
diff --git a/target/linux/ramips/mt7620/base-files/etc/board.d/01_leds b/target/linux/ramips/mt7620/base-files/etc/board.d/01_leds
index c4f7fcbb8762b5..ffc5745e6f3b74 100644
--- a/target/linux/ramips/mt7620/base-files/etc/board.d/01_leds
+++ b/target/linux/ramips/mt7620/base-files/etc/board.d/01_leds
@@ -225,6 +225,10 @@ tplink,archer-c20i)
 	ucidef_set_led_switch "lan" "lan" "blue:lan" "switch0" "0x1e"
 	ucidef_set_led_switch "wan" "wan" "blue:wan" "switch0" "0x01"
 	;;
+tplink,archer-c5-v4)
+	ucidef_set_led_switch "lan" "lan" "green:lan" "switch1" "0x0f"
+	ucidef_set_led_switch "wan" "wan" "green:wan" "switch1" "0x10"
+	;;
 tplink,archer-c50-v1)
 	ucidef_set_led_switch "lan" "lan" "green:lan" "switch0" "0x1e"
 	ucidef_set_led_switch "wan" "wan" "green:wan" "switch0" "0x01"
diff --git a/target/linux/ramips/mt7620/base-files/etc/board.d/02_network b/target/linux/ramips/mt7620/base-files/etc/board.d/02_network
index cbfb8a1d863f31..167bb47b69e60a 100644
--- a/target/linux/ramips/mt7620/base-files/etc/board.d/02_network
+++ b/target/linux/ramips/mt7620/base-files/etc/board.d/02_network
@@ -235,6 +235,12 @@ ramips_setup_interfaces()
 		ucidef_add_switch "switch0" \
 			"1:lan:3" "2:lan:4" "3:lan:1" "4:lan:2" "0:wan" "6@eth0"
 		;;
+	tplink,archer-c5-v4)
+		ucidef_add_switch "switch0"
+		ucidef_add_switch_attr "switch0" "enable" "0"
+		ucidef_add_switch "switch1" \
+			"0:lan:4" "1:lan:3" "2:lan:2" "3:lan:1" "4:wan" "7@eth0"
+		;;
 	tplink,archer-mr200)
 		ucidef_add_switch "switch0" \
 			"0:lan" "1:lan" "2:lan" "3:lan" "6t@eth0"
@@ -407,6 +413,7 @@ ramips_setup_macs()
 	tplink,archer-c2-v1|\
 	tplink,archer-c20-v1|\
 	tplink,archer-c20i|\
+	tplink,archer-c5-v4|\
 	tplink,archer-c50-v1|\
 	tplink,archer-mr200)
 		wan_mac=$(macaddr_add "$(mtd_get_mac_binary rom 0xf100)" 1)
diff --git a/target/linux/ramips/mt7620/config-6.1 b/target/linux/ramips/mt7620/config-6.1
new file mode 100644
index 00000000000000..111a59ab00f76a
--- /dev/null
+++ b/target/linux/ramips/mt7620/config-6.1
@@ -0,0 +1,215 @@
+CONFIG_AR8216_PHY=y
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MMAP_RND_BITS_MAX=15
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CEVT_R4K=y
+CONFIG_CEVT_SYSTICK_QUIRK=y
+CONFIG_CLKEVT_RT3352=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLK_MTMIPS=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
+CONFIG_CMDLINE_BOOL=y
+# CONFIG_CMDLINE_OVERRIDE is not set
+CONFIG_COMMON_CLK=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_DIEI=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_RIXI=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_MIPS32=y
+# CONFIG_CPU_MIPS32_R1 is not set
+CONFIG_CPU_MIPS32_R2=y
+CONFIG_CPU_MIPSR2=y
+CONFIG_CPU_MIPSR2_IRQ_VI=y
+CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
+CONFIG_CPU_R4K_CACHE_TLB=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CPU_SUPPORTS_MSA=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CSRC_R4K=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_PINCTRL=y
+CONFIG_DMA_NONCOHERENT=y
+# CONFIG_DTB_MT7620A_EVAL is not set
+# CONFIG_DTB_OMEGA2P is not set
+CONFIG_DTB_RT_NONE=y
+# CONFIG_DTB_VOCORE2 is not set
+CONFIG_DTC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_ETHERNET_PACKET_MANGLE=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_FIXED_PHY=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC11_NO_ARRAY_BOUNDS=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_LIB_ASHLDI3=y
+CONFIG_GENERIC_LIB_ASHRDI3=y
+CONFIG_GENERIC_LIB_CMPDI2=y
+CONFIG_GENERIC_LIB_LSHRDI3=y
+CONFIG_GENERIC_LIB_UCMPDI2=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GPIO_CDEV=y
+# CONFIG_GPIO_MT7621 is not set
+CONFIG_GPIO_RALINK=y
+CONFIG_GPIO_WATCHDOG=y
+# CONFIG_GPIO_WATCHDOG_ARCH_INITCALL is not set
+CONFIG_HARDWARE_WATCHPOINTS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HZ_PERIODIC=y
+CONFIG_ICPLUS_PHY=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_INTC=y
+CONFIG_IRQ_MIPS_CPU=y
+CONFIG_IRQ_WORK=y
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_MARVELL_PHY=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MEMFD_CREATE=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MIPS=y
+CONFIG_MIPS_ASID_BITS=8
+CONFIG_MIPS_ASID_SHIFT=0
+CONFIG_MIPS_CLOCK_VSYSCALL=y
+# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set
+# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
+CONFIG_MIPS_CMDLINE_FROM_DTB=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+CONFIG_MIPS_LD_CAN_LINK_VDSO=y
+# CONFIG_MIPS_NO_APPENDED_DTB is not set
+CONFIG_MIPS_RAW_APPENDED_DTB=y
+CONFIG_MIPS_SPRAM=y
+CONFIG_MODULES_USE_ELF_REL=y
+# CONFIG_MT7621_WDT is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_PARSER_TPLINK_SAFELOADER is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y
+CONFIG_MTD_SPLIT_JIMAGE_FW=y
+CONFIG_MTD_SPLIT_SEAMA_FW=y
+CONFIG_MTD_SPLIT_TPLINK_FW=y
+CONFIG_MTD_SPLIT_UIMAGE_FW=y
+CONFIG_MTD_VIRT_CONCAT=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NET_RALINK_GSW_MT7620=y
+CONFIG_NET_RALINK_MDIO=y
+CONFIG_NET_RALINK_MDIO_MT7620=y
+CONFIG_NET_RALINK_MT7620=y
+# CONFIG_NET_RALINK_RT3050 is not set
+CONFIG_NET_RALINK_SOC=y
+CONFIG_NET_SELFTESTS=y
+# CONFIG_NET_VENDOR_MEDIATEK is not set
+CONFIG_NET_VENDOR_RALINK=y
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DRIVERS_LEGACY=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+# CONFIG_PHY_MT7621_PCI is not set
+CONFIG_PHY_RALINK_USB=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_AW9523 is not set
+CONFIG_PINCTRL_MT7620=y
+CONFIG_PINCTRL_RALINK=y
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_RALINK=y
+CONFIG_RALINK_WDT=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RATIONAL=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_SERIAL_8250_RT288X=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SOC_MT7620=y
+# CONFIG_SOC_MT7621 is not set
+# CONFIG_SOC_RT288X is not set
+# CONFIG_SOC_RT305X is not set
+# CONFIG_SOC_RT3883 is not set
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+# CONFIG_SPI_MT7621 is not set
+CONFIG_SPI_RT2880=y
+CONFIG_SRCU=y
+CONFIG_SWCONFIG=y
+CONFIG_SWCONFIG_LEDS=y
+CONFIG_SWPHY=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_MIPS16=y
+CONFIG_SYS_SUPPORTS_ZBOOT=y
+CONFIG_TARGET_ISA_REV=2
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TINY_SRCU=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_ZBOOT_LOAD_ADDRESS=0x0
diff --git a/target/linux/ramips/mt7621/config-6.1 b/target/linux/ramips/mt7621/config-6.1
new file mode 100644
index 00000000000000..8f2355c56494b7
--- /dev/null
+++ b/target/linux/ramips/mt7621/config-6.1
@@ -0,0 +1,312 @@
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MMAP_RND_BITS_MAX=15
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_AT803X_PHY=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BOARD_SCACHE=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CEVT_R4K=y
+CONFIG_CLKSRC_MIPS_GIC=y
+CONFIG_CLK_MT7621=y
+CONFIG_CLOCKSOURCE_WATCHDOG=y
+CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US=100
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
+CONFIG_CMDLINE_BOOL=y
+# CONFIG_CMDLINE_OVERRIDE is not set
+CONFIG_COMMON_CLK=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_DIEI=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_RIXI=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_MIPS32=y
+# CONFIG_CPU_MIPS32_R1 is not set
+CONFIG_CPU_MIPS32_R2=y
+CONFIG_CPU_MIPSR2=y
+CONFIG_CPU_MIPSR2_IRQ_EI=y
+CONFIG_CPU_MIPSR2_IRQ_VI=y
+CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
+CONFIG_CPU_R4K_CACHE_TLB=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CPU_SUPPORTS_MSA=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_ZSTD=y
+CONFIG_CSRC_R4K=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_PINCTRL=y
+CONFIG_DIMLIB=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DTC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_FIXED_PHY=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC11_NO_ARRAY_BOUNDS=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_LIB_ASHLDI3=y
+CONFIG_GENERIC_LIB_ASHRDI3=y
+CONFIG_GENERIC_LIB_CMPDI2=y
+CONFIG_GENERIC_LIB_LSHRDI3=y
+CONFIG_GENERIC_LIB_UCMPDI2=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GLOB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_MT7621=y
+# CONFIG_GPIO_RALINK is not set
+CONFIG_GPIO_WATCHDOG=y
+# CONFIG_GPIO_WATCHDOG_ARCH_INITCALL is not set
+CONFIG_GRO_CELLS=y
+CONFIG_HARDWARE_WATCHPOINTS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_I2C=y
+CONFIG_I2C_ALGOBIT=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_GPIO=y
+CONFIG_I2C_MT7621=y
+CONFIG_ICPLUS_PHY=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_MIPS_CPU=y
+CONFIG_IRQ_WORK=y
+CONFIG_LED_TRIGGER_PHY=y
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MEDIATEK_GE_PHY=y
+CONFIG_MEMFD_CREATE=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MIKROTIK=y
+CONFIG_MIKROTIK_RB_SYSFS=y
+CONFIG_MIPS=y
+CONFIG_MIPS_ASID_BITS=8
+CONFIG_MIPS_ASID_SHIFT=0
+CONFIG_MIPS_CLOCK_VSYSCALL=y
+CONFIG_MIPS_CM=y
+# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set
+# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
+CONFIG_MIPS_CMDLINE_FROM_DTB=y
+CONFIG_MIPS_CPC=y
+CONFIG_MIPS_CPS=y
+# CONFIG_MIPS_CPS_NS16550_BOOL is not set
+CONFIG_MIPS_CPU_SCACHE=y
+CONFIG_MIPS_GIC=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+CONFIG_MIPS_LD_CAN_LINK_VDSO=y
+CONFIG_MIPS_MT=y
+CONFIG_MIPS_MT_FPAFF=y
+CONFIG_MIPS_MT_SMP=y
+# CONFIG_MIPS_NO_APPENDED_DTB is not set
+CONFIG_MIPS_NR_CPU_NR_MAP=4
+CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y
+CONFIG_MIPS_RAW_APPENDED_DTB=y
+CONFIG_MIPS_SPRAM=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MT7621_WDT=y
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+CONFIG_MTD_NAND_MT7621=y
+CONFIG_MTD_NAND_MTK_BMT=y
+# CONFIG_MTD_PARSER_TPLINK_SAFELOADER is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD_ROUTERBOOT_PARTS=y
+CONFIG_MTD_SERCOMM_PARTS=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y
+CONFIG_MTD_SPLIT_FIT_FW=y
+CONFIG_MTD_SPLIT_MINOR_FW=y
+CONFIG_MTD_SPLIT_SEAMA_FW=y
+CONFIG_MTD_SPLIT_TPLINK_FW=y
+CONFIG_MTD_SPLIT_TRX_FW=y
+CONFIG_MTD_SPLIT_UIMAGE_FW=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_VIRT_CONCAT=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NET_DEVLINK=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_MT7530=y
+CONFIG_NET_DSA_MT7530_MDIO=y
+# CONFIG_NET_DSA_MT7530_MMIO is not set
+CONFIG_NET_DSA_TAG_MTK=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_MEDIATEK_SOC=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_SWITCHDEV=y
+CONFIG_NET_VENDOR_MEDIATEK=y
+# CONFIG_NET_VENDOR_RALINK is not set
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NR_CPUS=4
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_PADATA=y
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_POOL_STATS=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
+CONFIG_PCI=y
+CONFIG_PCIE_MT7621=y
+CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_DRIVERS_GENERIC=y
+CONFIG_PCS_MTK_LYNXI=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+CONFIG_PHYLINK=y
+CONFIG_PHY_MT7621_PCI=y
+# CONFIG_PHY_RALINK_USB is not set
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AW9523=y
+CONFIG_PINCTRL_MT7621=y
+CONFIG_PINCTRL_RALINK=y
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PINCTRL_SX150X=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_GPIO=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_QCOM_NET_PHYLIB=y
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_RALINK=y
+# CONFIG_RALINK_WDT is not set
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RATIONAL=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_BQ32K=y
+CONFIG_RTC_DRV_PCF8563=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RTC_MC146818_LIB=y
+# CONFIG_SCHED_CORE is not set
+CONFIG_SCHED_SMT=y
+CONFIG_SERIAL_8250_NR_UARTS=3
+CONFIG_SERIAL_8250_RUNTIME_UARTS=3
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SMP=y
+CONFIG_SMP_UP=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SOC_BUS=y
+# CONFIG_SOC_MT7620 is not set
+CONFIG_SOC_MT7621=y
+# CONFIG_SOC_RT288X is not set
+# CONFIG_SOC_RT305X is not set
+# CONFIG_SOC_RT3883 is not set
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SPI_MT7621=y
+# CONFIG_SPI_RT2880 is not set
+CONFIG_SRCU=y
+CONFIG_SWPHY=y
+CONFIG_SYNC_R4K=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_HIGHMEM=y
+CONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_MIPS16=y
+CONFIG_SYS_SUPPORTS_MIPS_CPS=y
+CONFIG_SYS_SUPPORTS_MULTITHREADING=y
+CONFIG_SYS_SUPPORTS_SCHED_SMT=y
+CONFIG_SYS_SUPPORTS_SMP=y
+CONFIG_SYS_SUPPORTS_ZBOOT=y
+CONFIG_TARGET_ISA_REV=2
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UBIFS_FS=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_WEAK_ORDERING=y
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_ZBOOT_LOAD_ADDRESS=0x0
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZSTD_COMMON=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y
diff --git a/target/linux/ramips/mt76x8/config-5.15 b/target/linux/ramips/mt76x8/config-5.15
index 6d6759a7c585db..fc9aebc46a237e 100644
--- a/target/linux/ramips/mt76x8/config-5.15
+++ b/target/linux/ramips/mt76x8/config-5.15
@@ -4,7 +4,6 @@ CONFIG_ARCH_KEEP_MEMBLOCK=y
 CONFIG_ARCH_MMAP_RND_BITS_MAX=15
 CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
 CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_AT803X_PHY=y
 CONFIG_BLK_MQ_PCI=y
 CONFIG_CEVT_R4K=y
 CONFIG_CEVT_SYSTICK_QUIRK=y
diff --git a/target/linux/ramips/mt76x8/config-6.1 b/target/linux/ramips/mt76x8/config-6.1
new file mode 100644
index 00000000000000..be779b03d80a69
--- /dev/null
+++ b/target/linux/ramips/mt76x8/config-6.1
@@ -0,0 +1,215 @@
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MMAP_RND_BITS_MAX=15
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CEVT_R4K=y
+CONFIG_CEVT_SYSTICK_QUIRK=y
+CONFIG_CLKEVT_RT3352=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLK_MTMIPS=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
+CONFIG_CMDLINE_BOOL=y
+# CONFIG_CMDLINE_OVERRIDE is not set
+CONFIG_COMMON_CLK=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_DIEI=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_RIXI=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_MIPS32=y
+# CONFIG_CPU_MIPS32_R1 is not set
+CONFIG_CPU_MIPS32_R2=y
+CONFIG_CPU_MIPSR2=y
+CONFIG_CPU_MIPSR2_IRQ_VI=y
+CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
+CONFIG_CPU_R4K_CACHE_TLB=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CPU_SUPPORTS_MSA=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CSRC_R4K=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_PINCTRL=y
+CONFIG_DMA_NONCOHERENT=y
+# CONFIG_DTB_MT7620A_EVAL is not set
+# CONFIG_DTB_OMEGA2P is not set
+CONFIG_DTB_RT_NONE=y
+# CONFIG_DTB_VOCORE2 is not set
+CONFIG_DTC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_FIXED_PHY=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC11_NO_ARRAY_BOUNDS=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_LIB_ASHLDI3=y
+CONFIG_GENERIC_LIB_ASHRDI3=y
+CONFIG_GENERIC_LIB_CMPDI2=y
+CONFIG_GENERIC_LIB_LSHRDI3=y
+CONFIG_GENERIC_LIB_UCMPDI2=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_MT7621=y
+# CONFIG_GPIO_RALINK is not set
+CONFIG_HARDWARE_WATCHPOINTS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HZ_PERIODIC=y
+CONFIG_ICPLUS_PHY=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_INTC=y
+CONFIG_IRQ_MIPS_CPU=y
+CONFIG_IRQ_WORK=y
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MEMFD_CREATE=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MIPS=y
+CONFIG_MIPS_ASID_BITS=8
+CONFIG_MIPS_ASID_SHIFT=0
+CONFIG_MIPS_CLOCK_VSYSCALL=y
+# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set
+# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
+CONFIG_MIPS_CMDLINE_FROM_DTB=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+CONFIG_MIPS_LD_CAN_LINK_VDSO=y
+# CONFIG_MIPS_NO_APPENDED_DTB is not set
+CONFIG_MIPS_RAW_APPENDED_DTB=y
+CONFIG_MIPS_SPRAM=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MT7621_WDT=y
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_PARSER_TPLINK_SAFELOADER is not set
+CONFIG_MTD_PARSER_TRX=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y
+CONFIG_MTD_SPLIT_TPLINK_FW=y
+CONFIG_MTD_SPLIT_UIMAGE_FW=y
+CONFIG_MTD_VIRT_CONCAT=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NET_RALINK_ESW_RT3050=y
+# CONFIG_NET_RALINK_MT7620 is not set
+CONFIG_NET_RALINK_RT3050=y
+CONFIG_NET_RALINK_SOC=y
+CONFIG_NET_SELFTESTS=y
+# CONFIG_NET_VENDOR_MEDIATEK is not set
+CONFIG_NET_VENDOR_RALINK=y
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DRIVERS_LEGACY=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+# CONFIG_PHY_MT7621_PCI is not set
+CONFIG_PHY_RALINK_USB=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_AW9523 is not set
+CONFIG_PINCTRL_MT7620=y
+CONFIG_PINCTRL_RALINK=y
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_RALINK=y
+# CONFIG_RALINK_WDT is not set
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RATIONAL=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RTC_MC146818_LIB=y
+CONFIG_SERIAL_8250_NR_UARTS=3
+CONFIG_SERIAL_8250_RUNTIME_UARTS=3
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SOC_MT7620=y
+# CONFIG_SOC_MT7621 is not set
+# CONFIG_SOC_RT288X is not set
+# CONFIG_SOC_RT305X is not set
+# CONFIG_SOC_RT3883 is not set
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SPI_MT7621=y
+# CONFIG_SPI_RT2880 is not set
+CONFIG_SRCU=y
+CONFIG_SWCONFIG=y
+CONFIG_SWCONFIG_LEDS=y
+CONFIG_SWPHY=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_MIPS16=y
+CONFIG_SYS_SUPPORTS_ZBOOT=y
+CONFIG_TARGET_ISA_REV=2
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TINY_SRCU=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_ZBOOT_LOAD_ADDRESS=0x0
diff --git a/target/linux/ramips/patches-5.15/830-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch b/target/linux/ramips/patches-5.15/830-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch
index 2896002ed1aaee..9a0dbd7bb85c9a 100644
--- a/target/linux/ramips/patches-5.15/830-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch
+++ b/target/linux/ramips/patches-5.15/830-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch
@@ -25,7 +25,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 
 --- a/drivers/mmc/host/Kconfig
 +++ b/drivers/mmc/host/Kconfig
-@@ -1093,3 +1093,5 @@ config MMC_OWL
+@@ -1095,3 +1095,5 @@ config MMC_OWL
  
  config MMC_SDHCI_EXTERNAL_DMA
  	bool
diff --git a/target/linux/ramips/patches-6.1/003-v6.3-clk-ralink-fix-mt7621_gate_is_enabled-function.patch b/target/linux/ramips/patches-6.1/003-v6.3-clk-ralink-fix-mt7621_gate_is_enabled-function.patch
new file mode 100644
index 00000000000000..4574f7977fa49b
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/003-v6.3-clk-ralink-fix-mt7621_gate_is_enabled-function.patch
@@ -0,0 +1,77 @@
+From 35dcae535afc153fa83f2fe51c0812536c192c58 Mon Sep 17 00:00:00 2001
+From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Date: Mon, 6 Feb 2023 09:33:05 +0100
+Subject: [PATCH] clk: ralink: fix 'mt7621_gate_is_enabled()' function
+
+Compiling clock driver with CONFIG_UBSAN enabled shows the following trace:
+
+UBSAN: shift-out-of-bounds in drivers/clk/ralink/clk-mt7621.c:121:15
+shift exponent 131072 is too large for 32-bit type 'long unsigned int'
+CPU: 1 PID: 1 Comm: swapper/0 Not tainted 5.15.86 #0
+Stack : ...
+
+Call Trace:
+[<80009a58>] show_stack+0x38/0x118
+[<8045ce04>] dump_stack_lvl+0x60/0x80
+[<80458868>] ubsan_epilogue+0x10/0x54
+[<804590e0>] __ubsan_handle_shift_out_of_bounds+0x118/0x190
+[<804c9a10>] mt7621_gate_is_enabled+0x98/0xa0
+[<804bb774>] clk_core_is_enabled+0x34/0x90
+[<80aad73c>] clk_disable_unused_subtree+0x98/0x1e4
+[<80aad6d4>] clk_disable_unused_subtree+0x30/0x1e4
+[<80aad6d4>] clk_disable_unused_subtree+0x30/0x1e4
+[<80aad900>] clk_disable_unused+0x78/0x120
+[<80002030>] do_one_initcall+0x54/0x1f0
+[<80a922a4>] kernel_init_freeable+0x280/0x31c
+[<808047c4>] kernel_init+0x20/0x118
+[<80003e58>] ret_from_kernel_thread+0x14/0x1c
+
+Shifting a value (131032) larger than the type (32 bit unsigned integer)
+is undefined behaviour in C.
+
+The problem is in 'mt7621_gate_is_enabled()' function which is using the
+'BIT()' kernel macro with the bit index for the clock gate to check if the
+bit is set. When the clock gates structure is created driver is already
+setting 'bit_idx' using 'BIT()' macro, so we are wrongly applying an extra
+'BIT()' mask here. Removing it solve the problem and makes this function
+correct. However when clock gating is correctly working, the kernel starts
+disabling those clocks that are not requested. Some drivers for this SoC
+are older than this clock driver itself. So to avoid the kernel to disable
+clocks that have been enabled until now, we must apply 'CLK_IS_CRITICAL'
+flag on gates initialization code.
+
+Fixes: 48df7a26f470 ("clk: ralink: add clock driver for mt7621 SoC")
+Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Link: https://lore.kernel.org/r/20230206083305.147582-1-sergio.paracuellos@gmail.com
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+---
+ drivers/clk/ralink/clk-mt7621.c | 10 ++++++++--
+ 1 file changed, 8 insertions(+), 2 deletions(-)
+
+--- a/drivers/clk/ralink/clk-mt7621.c
++++ b/drivers/clk/ralink/clk-mt7621.c
+@@ -121,7 +121,7 @@ static int mt7621_gate_is_enabled(struct
+ 	if (regmap_read(sysc, SYSC_REG_CLKCFG1, &val))
+ 		return 0;
+ 
+-	return val & BIT(clk_gate->bit_idx);
++	return val & clk_gate->bit_idx;
+ }
+ 
+ static const struct clk_ops mt7621_gate_ops = {
+@@ -133,8 +133,14 @@ static const struct clk_ops mt7621_gate_
+ static int mt7621_gate_ops_init(struct device *dev,
+ 				struct mt7621_gate *sclk)
+ {
++	/*
++	 * There are drivers for this SoC that are older
++	 * than clock driver and are not prepared for the clock.
++	 * We don't want the kernel to disable anything so we
++	 * add CLK_IS_CRITICAL flag here.
++	 */
+ 	struct clk_init_data init = {
+-		.flags = CLK_SET_RATE_PARENT,
++		.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+ 		.num_parents = 1,
+ 		.parent_names = &sclk->parent_name,
+ 		.ops = &mt7621_gate_ops,
diff --git a/target/linux/ramips/patches-6.1/005-v6.5-01-dt-bindings-clock-add-mtmips-SoCs-system-controller.patch b/target/linux/ramips/patches-6.1/005-v6.5-01-dt-bindings-clock-add-mtmips-SoCs-system-controller.patch
new file mode 100644
index 00000000000000..94784f7885d82f
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/005-v6.5-01-dt-bindings-clock-add-mtmips-SoCs-system-controller.patch
@@ -0,0 +1,86 @@
+From 612616e6381929e7f9e303f8b8ad3655cc101516 Mon Sep 17 00:00:00 2001
+From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Date: Mon, 19 Jun 2023 06:09:33 +0200
+Subject: [PATCH 1/9] dt-bindings: clock: add mtmips SoCs system controller
+
+Adds device tree binding documentation for system controller node present
+in Mediatek MIPS and Ralink SOCs. This node is a clock and reset provider
+for the rest of the world. This covers RT2880, RT3050, RT3052, RT3350,
+RT3883, RT5350, MT7620, MT7628 and MT7688 SoCs.
+
+Reviewed-by: Rob Herring <robh@kernel.org>
+Acked-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+---
+ .../bindings/clock/mediatek,mtmips-sysc.yaml       | 64 ++++++++++++++++++++++
+ 1 file changed, 64 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml
+@@ -0,0 +1,64 @@
++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/clock/mediatek,mtmips-sysc.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: MTMIPS SoCs System Controller
++
++maintainers:
++  - Sergio Paracuellos <sergio.paracuellos@gmail.com>
++
++description: |
++  MediaTek MIPS and Ralink SoCs provides a system controller to allow
++  to access to system control registers. These registers include clock
++  and reset related ones so this node is both clock and reset provider
++  for the rest of the world.
++
++  These SoCs have an XTAL from where the cpu clock is
++  provided as well as derived clocks for the bus and the peripherals.
++
++properties:
++  compatible:
++    items:
++      - enum:
++          - ralink,mt7620-sysc
++          - ralink,mt7628-sysc
++          - ralink,mt7688-sysc
++          - ralink,rt2880-sysc
++          - ralink,rt3050-sysc
++          - ralink,rt3052-sysc
++          - ralink,rt3352-sysc
++          - ralink,rt3883-sysc
++          - ralink,rt5350-sysc
++      - const: syscon
++
++  reg:
++    maxItems: 1
++
++  '#clock-cells':
++    description:
++      The first cell indicates the clock number.
++    const: 1
++
++  '#reset-cells':
++    description:
++      The first cell indicates the reset bit within the register.
++    const: 1
++
++required:
++  - compatible
++  - reg
++  - '#clock-cells'
++  - '#reset-cells'
++
++additionalProperties: false
++
++examples:
++  - |
++    syscon@0 {
++      compatible = "ralink,rt5350-sysc", "syscon";
++      reg = <0x0 0x100>;
++      #clock-cells = <1>;
++      #reset-cells = <1>;
++    };
diff --git a/target/linux/ramips/patches-6.1/005-v6.5-02-clk-ralink-add-clock-and-reset-driver-for-MTMIPS-SoC.patch b/target/linux/ramips/patches-6.1/005-v6.5-02-clk-ralink-add-clock-and-reset-driver-for-MTMIPS-SoC.patch
new file mode 100644
index 00000000000000..cef39978e0380f
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/005-v6.5-02-clk-ralink-add-clock-and-reset-driver-for-MTMIPS-SoC.patch
@@ -0,0 +1,1221 @@
+From 6f3b15586eef736831abe6a14f2a6906bc0dc074 Mon Sep 17 00:00:00 2001
+From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Date: Mon, 19 Jun 2023 06:09:34 +0200
+Subject: [PATCH 2/9] clk: ralink: add clock and reset driver for MTMIPS SoCs
+
+Until now, clock related code for old ralink SoCs was based in fixed clocks
+using 'clk_register_fixed_rate' and 'clkdev_create' directly doing in code
+and not using device tree at all for their definition. Including this driver
+is an effort to be able to define proper clocks using device tree and also
+cleaning all the clock and reset related code from 'arch/mips/ralink' dir.
+This clock and reset driver covers all the ralink SoCs but MT7621 which is
+the newest and provides gating and some differences that make it different
+from its predecesors. It has its own driver since some time ago. The ralink
+SoCs we are taking about are RT2880, RT3050, RT3052, RT3350, RT3352, RT3883,
+RT5350, MT7620, MT7628 and MT7688. Mostly the code in this new driver has
+been extracted from 'arch/mips/ralink' and cleanly put using kernel clock
+driver APIs. The clock plans for this SoCs only talks about relation between
+CPU frequency and BUS frequency. This relation is different depending on the
+particular SoC. CPU clock is derived from XTAL frequencies.
+
+Depending on the SoC we have the following frequencies:
+* RT2880 SoC:
+    - XTAL: 40 MHz.
+    - CPU: 250, 266, 280 or 300 MHz.
+    - BUS: CPU / 2 MHz.
+* RT3050, RT3052, RT3350:
+    - XTAL: 40 MHz.
+    - CPU: 320 or 384 MHz.
+    - BUS: CPU / 3 MHz.
+* RT3352:
+    - XTAL: 40 MHz.
+    - CPU: 384 or 400 MHz.
+    - BUS: CPU / 3 MHz.
+    - PERIPH: 40 MHz.
+* RT3383:
+    - XTAL: 40 MHz.
+    - CPU: 250, 384, 480 or 500 MHz.
+    - BUS: Depends on RAM Type and CPU:
+        + RAM DDR2: 125. ELSE 83 MHz.
+        + RAM DDR2: 128. ELSE 96 MHz.
+        + RAM DDR2: 160. ELSE 120 MHz.
+        + RAM DDR2: 166. ELSE 125 MHz.
+* RT5350:
+    - XTAL: 40 MHz.
+    - CPU: 300, 320 or 360 MHz.
+    - BUS: CPU / 3, CPU / 4, CPU / 3 MHz.
+    - PERIPH: 40 MHz.
+* MT7628 and MT7688:
+    - XTAL: 20 MHz or 40 MHz.
+    - CPU: 575 or 580 MHz.
+    - BUS: CPU / 3.
+    - PCMI2S: 480 MHz.
+    - PERIPH: 40 MHz.
+* MT7620:
+    - XTAL: 20 MHz or 40 MHz.
+    - PLL: XTAL, 480, 600 MHz.
+    - CPU: depends on PLL and some mult and dividers.
+    - BUS: depends on PLL and some mult and dividers.
+    - PERIPH: 40 or XTAL MHz.
+
+MT7620 is a bit more complex deriving CPU clock from a PLL and an bunch of
+register reads and predividers. To derive CPU and BUS frequencies in the
+MT7620 SoC 'mt7620_calc_rate()' helper is used.
+
+In the case XTAL can have different frequencies and we need a different
+clock frequency for peripherals 'periph' clock in introduced.
+
+The rest of the peripherals present in the SoC just follow their parent
+frequencies.
+
+With this information the clk driver will provide all the clock and reset
+functionality from a set of hardcoded clocks allowing to define a nice
+device tree without fixed clocks.
+
+Acked-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+---
+ drivers/clk/ralink/Kconfig      |    7 +
+ drivers/clk/ralink/Makefile     |    1 +
+ drivers/clk/ralink/clk-mtmips.c | 1115 +++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 1123 insertions(+)
+ create mode 100644 drivers/clk/ralink/clk-mtmips.c
+
+--- a/drivers/clk/ralink/Kconfig
++++ b/drivers/clk/ralink/Kconfig
+@@ -9,3 +9,10 @@ config CLK_MT7621
+ 	select MFD_SYSCON
+ 	help
+ 	  This driver supports MediaTek MT7621 basic clocks.
++
++config CLK_MTMIPS
++	bool "Clock driver for MTMIPS SoCs"
++	depends on SOC_RT305X || SOC_RT288X || SOC_RT3883 || SOC_MT7620 || COMPILE_TEST
++	select MFD_SYSCON
++	help
++	  This driver supports MTMIPS basic clocks.
+--- a/drivers/clk/ralink/Makefile
++++ b/drivers/clk/ralink/Makefile
+@@ -1,2 +1,3 @@
+ # SPDX-License-Identifier: GPL-2.0
+ obj-$(CONFIG_CLK_MT7621) += clk-mt7621.o
++obj-$(CONFIG_CLK_MTMIPS) += clk-mtmips.o
+--- /dev/null
++++ b/drivers/clk/ralink/clk-mtmips.c
+@@ -0,0 +1,1115 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * MTMIPS SoCs Clock Driver
++ * Author: Sergio Paracuellos <sergio.paracuellos@gmail.com>
++ */
++
++#include <linux/bitops.h>
++#include <linux/clk-provider.h>
++#include <linux/mfd/syscon.h>
++#include <linux/platform_device.h>
++#include <linux/regmap.h>
++#include <linux/reset-controller.h>
++#include <linux/slab.h>
++
++/* Configuration registers */
++#define SYSC_REG_SYSTEM_CONFIG		0x10
++#define SYSC_REG_CLKCFG0		0x2c
++#define SYSC_REG_RESET_CTRL		0x34
++#define SYSC_REG_CPU_SYS_CLKCFG		0x3c
++#define SYSC_REG_CPLL_CONFIG0		0x54
++#define SYSC_REG_CPLL_CONFIG1		0x58
++
++/* RT2880 SoC */
++#define RT2880_CONFIG_CPUCLK_SHIFT	20
++#define RT2880_CONFIG_CPUCLK_MASK	0x3
++#define RT2880_CONFIG_CPUCLK_250	0x0
++#define RT2880_CONFIG_CPUCLK_266	0x1
++#define RT2880_CONFIG_CPUCLK_280	0x2
++#define RT2880_CONFIG_CPUCLK_300	0x3
++
++/* RT305X SoC */
++#define RT305X_SYSCFG_CPUCLK_SHIFT	18
++#define RT305X_SYSCFG_CPUCLK_MASK	0x1
++#define RT305X_SYSCFG_CPUCLK_LOW	0x0
++#define RT305X_SYSCFG_CPUCLK_HIGH	0x1
++
++/* RT3352 SoC */
++#define RT3352_SYSCFG0_CPUCLK_SHIFT	8
++#define RT3352_SYSCFG0_CPUCLK_MASK	0x1
++#define RT3352_SYSCFG0_CPUCLK_LOW	0x0
++#define RT3352_SYSCFG0_CPUCLK_HIGH	0x1
++
++/* RT3383 SoC */
++#define RT3883_SYSCFG0_DRAM_TYPE_DDR2	BIT(17)
++#define RT3883_SYSCFG0_CPUCLK_SHIFT	8
++#define RT3883_SYSCFG0_CPUCLK_MASK	0x3
++#define RT3883_SYSCFG0_CPUCLK_250	0x0
++#define RT3883_SYSCFG0_CPUCLK_384	0x1
++#define RT3883_SYSCFG0_CPUCLK_480	0x2
++#define RT3883_SYSCFG0_CPUCLK_500	0x3
++
++/* RT5350 SoC */
++#define RT5350_CLKCFG0_XTAL_SEL		BIT(20)
++#define RT5350_SYSCFG0_CPUCLK_SHIFT	8
++#define RT5350_SYSCFG0_CPUCLK_MASK	0x3
++#define RT5350_SYSCFG0_CPUCLK_360	0x0
++#define RT5350_SYSCFG0_CPUCLK_320	0x2
++#define RT5350_SYSCFG0_CPUCLK_300	0x3
++
++/* MT7620 and MT76x8 SoCs */
++#define MT7620_XTAL_FREQ_SEL		BIT(6)
++#define CPLL_CFG0_SW_CFG		BIT(31)
++#define CPLL_CFG0_PLL_MULT_RATIO_SHIFT	16
++#define CPLL_CFG0_PLL_MULT_RATIO_MASK   0x7
++#define CPLL_CFG0_LC_CURFCK		BIT(15)
++#define CPLL_CFG0_BYPASS_REF_CLK	BIT(14)
++#define CPLL_CFG0_PLL_DIV_RATIO_SHIFT	10
++#define CPLL_CFG0_PLL_DIV_RATIO_MASK	0x3
++#define CPLL_CFG1_CPU_AUX1		BIT(25)
++#define CPLL_CFG1_CPU_AUX0		BIT(24)
++#define CLKCFG0_PERI_CLK_SEL		BIT(4)
++#define CPU_SYS_CLKCFG_OCP_RATIO_SHIFT	16
++#define CPU_SYS_CLKCFG_OCP_RATIO_MASK	0xf
++#define CPU_SYS_CLKCFG_OCP_RATIO_1	0	/* 1:1   (Reserved) */
++#define CPU_SYS_CLKCFG_OCP_RATIO_1_5	1	/* 1:1.5 (Reserved) */
++#define CPU_SYS_CLKCFG_OCP_RATIO_2	2	/* 1:2   */
++#define CPU_SYS_CLKCFG_OCP_RATIO_2_5	3       /* 1:2.5 (Reserved) */
++#define CPU_SYS_CLKCFG_OCP_RATIO_3	4	/* 1:3   */
++#define CPU_SYS_CLKCFG_OCP_RATIO_3_5	5	/* 1:3.5 (Reserved) */
++#define CPU_SYS_CLKCFG_OCP_RATIO_4	6	/* 1:4   */
++#define CPU_SYS_CLKCFG_OCP_RATIO_5	7	/* 1:5   */
++#define CPU_SYS_CLKCFG_OCP_RATIO_10	8	/* 1:10  */
++#define CPU_SYS_CLKCFG_CPU_FDIV_SHIFT	8
++#define CPU_SYS_CLKCFG_CPU_FDIV_MASK	0x1f
++#define CPU_SYS_CLKCFG_CPU_FFRAC_SHIFT	0
++#define CPU_SYS_CLKCFG_CPU_FFRAC_MASK	0x1f
++
++/* clock scaling */
++#define CLKCFG_FDIV_MASK		0x1f00
++#define CLKCFG_FDIV_USB_VAL		0x0300
++#define CLKCFG_FFRAC_MASK		0x001f
++#define CLKCFG_FFRAC_USB_VAL		0x0003
++
++struct mtmips_clk;
++struct mtmips_clk_fixed;
++struct mtmips_clk_factor;
++
++struct mtmips_clk_data {
++	struct mtmips_clk *clk_base;
++	size_t num_clk_base;
++	struct mtmips_clk_fixed *clk_fixed;
++	size_t num_clk_fixed;
++	struct mtmips_clk_factor *clk_factor;
++	size_t num_clk_factor;
++	struct mtmips_clk *clk_periph;
++	size_t num_clk_periph;
++};
++
++struct mtmips_clk_priv {
++	struct regmap *sysc;
++	const struct mtmips_clk_data *data;
++};
++
++struct mtmips_clk {
++	struct clk_hw hw;
++	struct mtmips_clk_priv *priv;
++};
++
++struct mtmips_clk_fixed {
++	const char *name;
++	const char *parent;
++	unsigned long rate;
++	struct clk_hw *hw;
++};
++
++struct mtmips_clk_factor {
++	const char *name;
++	const char *parent;
++	int mult;
++	int div;
++	unsigned long flags;
++	struct clk_hw *hw;
++};
++
++static unsigned long mtmips_pherip_clk_rate(struct clk_hw *hw,
++					    unsigned long parent_rate)
++{
++	return parent_rate;
++}
++
++static const struct clk_ops mtmips_periph_clk_ops = {
++	.recalc_rate = mtmips_pherip_clk_rate,
++};
++
++#define CLK_PERIPH(_name, _parent) {				\
++	.init = &(const struct clk_init_data) {			\
++		.name = _name,					\
++		.ops = &mtmips_periph_clk_ops,			\
++		.parent_data = &(const struct clk_parent_data) {\
++			.name = _parent,			\
++			.fw_name = _parent			\
++		},						\
++		.num_parents = 1,				\
++		/*						\
++		 * There are drivers for these SoCs that are	\
++		 * older than clock driver and are not prepared \
++		 * for the clock. We don't want the kernel to   \
++		 * disable anything so we add CLK_IS_CRITICAL	\
++		 * flag here.					\
++		 */						\
++		.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL	\
++	},							\
++}
++
++static struct mtmips_clk rt2880_pherip_clks[] = {
++	{ CLK_PERIPH("300100.timer", "bus") },
++	{ CLK_PERIPH("300120.watchdog", "bus") },
++	{ CLK_PERIPH("300500.uart", "bus") },
++	{ CLK_PERIPH("300900.i2c", "bus") },
++	{ CLK_PERIPH("300c00.uartlite", "bus") },
++	{ CLK_PERIPH("400000.ethernet", "bus") },
++	{ CLK_PERIPH("480000.wmac", "xtal") }
++};
++
++static struct mtmips_clk rt305x_pherip_clks[] = {
++	{ CLK_PERIPH("10000100.timer", "bus") },
++	{ CLK_PERIPH("10000120.watchdog", "bus") },
++	{ CLK_PERIPH("10000500.uart", "bus") },
++	{ CLK_PERIPH("10000900.i2c", "bus") },
++	{ CLK_PERIPH("10000a00.i2s", "bus") },
++	{ CLK_PERIPH("10000b00.spi", "bus") },
++	{ CLK_PERIPH("10000b40.spi", "bus") },
++	{ CLK_PERIPH("10000c00.uartlite", "bus") },
++	{ CLK_PERIPH("10100000.ethernet", "bus") },
++	{ CLK_PERIPH("10180000.wmac", "xtal") }
++};
++
++static struct mtmips_clk rt5350_pherip_clks[] = {
++	{ CLK_PERIPH("10000100.timer", "bus") },
++	{ CLK_PERIPH("10000120.watchdog", "bus") },
++	{ CLK_PERIPH("10000500.uart", "periph") },
++	{ CLK_PERIPH("10000900.i2c", "periph") },
++	{ CLK_PERIPH("10000a00.i2s", "periph") },
++	{ CLK_PERIPH("10000b00.spi", "bus") },
++	{ CLK_PERIPH("10000b40.spi", "bus") },
++	{ CLK_PERIPH("10000c00.uartlite", "periph") },
++	{ CLK_PERIPH("10100000.ethernet", "bus") },
++	{ CLK_PERIPH("10180000.wmac", "xtal") }
++};
++
++static struct mtmips_clk mt7620_pherip_clks[] = {
++	{ CLK_PERIPH("10000100.timer", "periph") },
++	{ CLK_PERIPH("10000120.watchdog", "periph") },
++	{ CLK_PERIPH("10000500.uart", "periph") },
++	{ CLK_PERIPH("10000900.i2c", "periph") },
++	{ CLK_PERIPH("10000a00.i2s", "periph") },
++	{ CLK_PERIPH("10000b00.spi", "bus") },
++	{ CLK_PERIPH("10000b40.spi", "bus") },
++	{ CLK_PERIPH("10000c00.uartlite", "periph") },
++	{ CLK_PERIPH("10180000.wmac", "xtal") }
++};
++
++static struct mtmips_clk mt76x8_pherip_clks[] = {
++	{ CLK_PERIPH("10000100.timer", "periph") },
++	{ CLK_PERIPH("10000120.watchdog", "periph") },
++	{ CLK_PERIPH("10000900.i2c", "periph") },
++	{ CLK_PERIPH("10000a00.i2s", "pcmi2s") },
++	{ CLK_PERIPH("10000b00.spi", "bus") },
++	{ CLK_PERIPH("10000b40.spi", "bus") },
++	{ CLK_PERIPH("10000c00.uart0", "periph") },
++	{ CLK_PERIPH("10000d00.uart1", "periph") },
++	{ CLK_PERIPH("10000e00.uart2", "periph") },
++	{ CLK_PERIPH("10300000.wmac", "xtal") }
++};
++
++static int mtmips_register_pherip_clocks(struct device_node *np,
++					 struct clk_hw_onecell_data *clk_data,
++					 struct mtmips_clk_priv *priv)
++{
++	struct clk_hw **hws = clk_data->hws;
++	struct mtmips_clk *sclk;
++	size_t idx_start = priv->data->num_clk_base + priv->data->num_clk_fixed +
++			   priv->data->num_clk_factor;
++	int ret, i;
++
++	for (i = 0; i < priv->data->num_clk_periph; i++) {
++		int idx = idx_start + i;
++
++		sclk = &priv->data->clk_periph[i];
++		ret = of_clk_hw_register(np, &sclk->hw);
++		if (ret) {
++			pr_err("Couldn't register peripheral clock %d\n", idx);
++			goto err_clk_unreg;
++		}
++
++		hws[idx] = &sclk->hw;
++	}
++
++	return 0;
++
++err_clk_unreg:
++	while (--i >= 0) {
++		sclk = &priv->data->clk_periph[i];
++		clk_hw_unregister(&sclk->hw);
++	}
++	return ret;
++}
++
++#define CLK_FIXED(_name, _parent, _rate) \
++	{				 \
++		.name = _name,		 \
++		.parent = _parent,	 \
++		.rate = _rate		 \
++	}
++
++static struct mtmips_clk_fixed rt305x_fixed_clocks[] = {
++	CLK_FIXED("xtal", NULL, 40000000)
++};
++
++static struct mtmips_clk_fixed rt3352_fixed_clocks[] = {
++	CLK_FIXED("periph", "xtal", 40000000)
++};
++
++static struct mtmips_clk_fixed mt76x8_fixed_clocks[] = {
++	CLK_FIXED("pcmi2s", "xtal", 480000000),
++	CLK_FIXED("periph", "xtal", 40000000)
++};
++
++static int mtmips_register_fixed_clocks(struct clk_hw_onecell_data *clk_data,
++					struct mtmips_clk_priv *priv)
++{
++	struct clk_hw **hws = clk_data->hws;
++	struct mtmips_clk_fixed *sclk;
++	size_t idx_start = priv->data->num_clk_base;
++	int ret, i;
++
++	for (i = 0; i < priv->data->num_clk_fixed; i++) {
++		int idx = idx_start + i;
++
++		sclk = &priv->data->clk_fixed[i];
++		sclk->hw = clk_hw_register_fixed_rate(NULL, sclk->name,
++						      sclk->parent, 0,
++						      sclk->rate);
++		if (IS_ERR(sclk->hw)) {
++			pr_err("Couldn't register fixed clock %d\n", idx);
++			goto err_clk_unreg;
++		}
++
++		hws[idx] = sclk->hw;
++	}
++
++	return 0;
++
++err_clk_unreg:
++	while (--i >= 0) {
++		sclk = &priv->data->clk_fixed[i];
++		clk_hw_unregister_fixed_rate(sclk->hw);
++	}
++	return ret;
++}
++
++#define CLK_FACTOR(_name, _parent, _mult, _div)		\
++	{						\
++		.name = _name,				\
++		.parent = _parent,			\
++		.mult = _mult,				\
++		.div = _div,				\
++		.flags = CLK_SET_RATE_PARENT		\
++	}
++
++static struct mtmips_clk_factor rt2880_factor_clocks[] = {
++	CLK_FACTOR("bus", "cpu", 1, 2)
++};
++
++static struct mtmips_clk_factor rt305x_factor_clocks[] = {
++	CLK_FACTOR("bus", "cpu", 1, 3)
++};
++
++static int mtmips_register_factor_clocks(struct clk_hw_onecell_data *clk_data,
++					 struct mtmips_clk_priv *priv)
++{
++	struct clk_hw **hws = clk_data->hws;
++	struct mtmips_clk_factor *sclk;
++	size_t idx_start = priv->data->num_clk_base + priv->data->num_clk_fixed;
++	int ret, i;
++
++	for (i = 0; i < priv->data->num_clk_factor; i++) {
++		int idx = idx_start + i;
++
++		sclk = &priv->data->clk_factor[i];
++		sclk->hw = clk_hw_register_fixed_factor(NULL, sclk->name,
++						  sclk->parent, sclk->flags,
++						  sclk->mult, sclk->div);
++		if (IS_ERR(sclk->hw)) {
++			pr_err("Couldn't register factor clock %d\n", idx);
++			goto err_clk_unreg;
++		}
++
++		hws[idx] = sclk->hw;
++	}
++
++	return 0;
++
++err_clk_unreg:
++	while (--i >= 0) {
++		sclk = &priv->data->clk_factor[i];
++		clk_hw_unregister_fixed_factor(sclk->hw);
++	}
++	return ret;
++}
++
++static inline struct mtmips_clk *to_mtmips_clk(struct clk_hw *hw)
++{
++	return container_of(hw, struct mtmips_clk, hw);
++}
++
++static unsigned long rt5350_xtal_recalc_rate(struct clk_hw *hw,
++					     unsigned long parent_rate)
++{
++	struct mtmips_clk *clk = to_mtmips_clk(hw);
++	struct regmap *sysc = clk->priv->sysc;
++	u32 val;
++
++	regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &val);
++	if (!(val & RT5350_CLKCFG0_XTAL_SEL))
++		return 20000000;
++
++	return 40000000;
++}
++
++static unsigned long rt5350_cpu_recalc_rate(struct clk_hw *hw,
++					    unsigned long xtal_clk)
++{
++	struct mtmips_clk *clk = to_mtmips_clk(hw);
++	struct regmap *sysc = clk->priv->sysc;
++	u32 t;
++
++	regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
++	t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) & RT5350_SYSCFG0_CPUCLK_MASK;
++
++	switch (t) {
++	case RT5350_SYSCFG0_CPUCLK_360:
++		return 360000000;
++	case RT5350_SYSCFG0_CPUCLK_320:
++		return 320000000;
++	case RT5350_SYSCFG0_CPUCLK_300:
++		return 300000000;
++	default:
++		BUG();
++	}
++}
++
++static unsigned long rt5350_bus_recalc_rate(struct clk_hw *hw,
++					    unsigned long parent_rate)
++{
++	if (parent_rate == 320000000)
++		return parent_rate / 4;
++
++	return parent_rate / 3;
++}
++
++static unsigned long rt3352_cpu_recalc_rate(struct clk_hw *hw,
++					    unsigned long xtal_clk)
++{
++	struct mtmips_clk *clk = to_mtmips_clk(hw);
++	struct regmap *sysc = clk->priv->sysc;
++	u32 t;
++
++	regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
++	t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) & RT3352_SYSCFG0_CPUCLK_MASK;
++
++	switch (t) {
++	case RT3352_SYSCFG0_CPUCLK_LOW:
++		return 384000000;
++	case RT3352_SYSCFG0_CPUCLK_HIGH:
++		return 400000000;
++	default:
++		BUG();
++	}
++}
++
++static unsigned long rt305x_cpu_recalc_rate(struct clk_hw *hw,
++					    unsigned long xtal_clk)
++{
++	struct mtmips_clk *clk = to_mtmips_clk(hw);
++	struct regmap *sysc = clk->priv->sysc;
++	u32 t;
++
++	regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
++	t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) & RT305X_SYSCFG_CPUCLK_MASK;
++
++	switch (t) {
++	case RT305X_SYSCFG_CPUCLK_LOW:
++		return 320000000;
++	case RT305X_SYSCFG_CPUCLK_HIGH:
++		return 384000000;
++	default:
++		BUG();
++	}
++}
++
++static unsigned long rt3883_cpu_recalc_rate(struct clk_hw *hw,
++					    unsigned long xtal_clk)
++{
++	struct mtmips_clk *clk = to_mtmips_clk(hw);
++	struct regmap *sysc = clk->priv->sysc;
++	u32 t;
++
++	regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
++	t = (t >> RT3883_SYSCFG0_CPUCLK_SHIFT) & RT3883_SYSCFG0_CPUCLK_MASK;
++
++	switch (t) {
++	case RT3883_SYSCFG0_CPUCLK_250:
++		return 250000000;
++	case RT3883_SYSCFG0_CPUCLK_384:
++		return 384000000;
++	case RT3883_SYSCFG0_CPUCLK_480:
++		return 480000000;
++	case RT3883_SYSCFG0_CPUCLK_500:
++		return 500000000;
++	default:
++		BUG();
++	}
++}
++
++static unsigned long rt3883_bus_recalc_rate(struct clk_hw *hw,
++					    unsigned long parent_rate)
++{
++	struct mtmips_clk *clk = to_mtmips_clk(hw);
++	struct regmap *sysc = clk->priv->sysc;
++	u32 ddr2;
++	u32 t;
++
++	regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
++	ddr2 = t & RT3883_SYSCFG0_DRAM_TYPE_DDR2;
++
++	switch (parent_rate) {
++	case 250000000:
++		return (ddr2) ? 125000000 : 83000000;
++	case 384000000:
++		return (ddr2) ? 128000000 : 96000000;
++	case 480000000:
++		return (ddr2) ? 160000000 : 120000000;
++	case 500000000:
++		return (ddr2) ? 166000000 : 125000000;
++	default:
++		WARN_ON_ONCE(parent_rate == 0);
++		return parent_rate / 4;
++	}
++}
++
++static unsigned long rt2880_cpu_recalc_rate(struct clk_hw *hw,
++					    unsigned long xtal_clk)
++{
++	struct mtmips_clk *clk = to_mtmips_clk(hw);
++	struct regmap *sysc = clk->priv->sysc;
++	u32 t;
++
++	regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
++	t = (t >> RT2880_CONFIG_CPUCLK_SHIFT) & RT2880_CONFIG_CPUCLK_MASK;
++
++	switch (t) {
++	case RT2880_CONFIG_CPUCLK_250:
++		return 250000000;
++	case RT2880_CONFIG_CPUCLK_266:
++		return 266000000;
++	case RT2880_CONFIG_CPUCLK_280:
++		return 280000000;
++	case RT2880_CONFIG_CPUCLK_300:
++		return 300000000;
++	default:
++		BUG();
++	}
++}
++
++static u32 mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div)
++{
++	u64 t;
++
++	t = ref_rate;
++	t *= mul;
++	t = div_u64(t, div);
++
++	return t;
++}
++
++static unsigned long mt7620_pll_recalc_rate(struct clk_hw *hw,
++					    unsigned long parent_rate)
++{
++	static const u32 clk_divider[] = { 2, 3, 4, 8 };
++	struct mtmips_clk *clk = to_mtmips_clk(hw);
++	struct regmap *sysc = clk->priv->sysc;
++	unsigned long cpu_pll;
++	u32 t;
++	u32 mul;
++	u32 div;
++
++	regmap_read(sysc, SYSC_REG_CPLL_CONFIG0, &t);
++	if (t & CPLL_CFG0_BYPASS_REF_CLK) {
++		cpu_pll = parent_rate;
++	} else if ((t & CPLL_CFG0_SW_CFG) == 0) {
++		cpu_pll = 600000000;
++	} else {
++		mul = (t >> CPLL_CFG0_PLL_MULT_RATIO_SHIFT) &
++			CPLL_CFG0_PLL_MULT_RATIO_MASK;
++		mul += 24;
++		if (t & CPLL_CFG0_LC_CURFCK)
++			mul *= 2;
++
++		div = (t >> CPLL_CFG0_PLL_DIV_RATIO_SHIFT) &
++			CPLL_CFG0_PLL_DIV_RATIO_MASK;
++
++		WARN_ON_ONCE(div >= ARRAY_SIZE(clk_divider));
++
++		cpu_pll = mt7620_calc_rate(parent_rate, mul, clk_divider[div]);
++	}
++
++	regmap_read(sysc, SYSC_REG_CPLL_CONFIG1, &t);
++	if (t & CPLL_CFG1_CPU_AUX1)
++		return parent_rate;
++
++	if (t & CPLL_CFG1_CPU_AUX0)
++		return 480000000;
++
++	return cpu_pll;
++}
++
++static unsigned long mt7620_cpu_recalc_rate(struct clk_hw *hw,
++					    unsigned long parent_rate)
++{
++	struct mtmips_clk *clk = to_mtmips_clk(hw);
++	struct regmap *sysc = clk->priv->sysc;
++	u32 t;
++	u32 mul;
++	u32 div;
++
++	regmap_read(sysc, SYSC_REG_CPU_SYS_CLKCFG, &t);
++	mul = t & CPU_SYS_CLKCFG_CPU_FFRAC_MASK;
++	div = (t >> CPU_SYS_CLKCFG_CPU_FDIV_SHIFT) &
++		CPU_SYS_CLKCFG_CPU_FDIV_MASK;
++
++	return mt7620_calc_rate(parent_rate, mul, div);
++}
++
++static unsigned long mt7620_bus_recalc_rate(struct clk_hw *hw,
++					    unsigned long parent_rate)
++{
++	static const u32 ocp_dividers[16] = {
++		[CPU_SYS_CLKCFG_OCP_RATIO_2] = 2,
++		[CPU_SYS_CLKCFG_OCP_RATIO_3] = 3,
++		[CPU_SYS_CLKCFG_OCP_RATIO_4] = 4,
++		[CPU_SYS_CLKCFG_OCP_RATIO_5] = 5,
++		[CPU_SYS_CLKCFG_OCP_RATIO_10] = 10,
++	};
++	struct mtmips_clk *clk = to_mtmips_clk(hw);
++	struct regmap *sysc = clk->priv->sysc;
++	u32 t;
++	u32 ocp_ratio;
++	u32 div;
++
++	regmap_read(sysc, SYSC_REG_CPU_SYS_CLKCFG, &t);
++	ocp_ratio = (t >> CPU_SYS_CLKCFG_OCP_RATIO_SHIFT) &
++		CPU_SYS_CLKCFG_OCP_RATIO_MASK;
++
++	if (WARN_ON_ONCE(ocp_ratio >= ARRAY_SIZE(ocp_dividers)))
++		return parent_rate;
++
++	div = ocp_dividers[ocp_ratio];
++
++	if (WARN(!div, "invalid divider for OCP ratio %u", ocp_ratio))
++		return parent_rate;
++
++	return parent_rate / div;
++}
++
++static unsigned long mt7620_periph_recalc_rate(struct clk_hw *hw,
++					       unsigned long parent_rate)
++{
++	struct mtmips_clk *clk = to_mtmips_clk(hw);
++	struct regmap *sysc = clk->priv->sysc;
++	u32 t;
++
++	regmap_read(sysc, SYSC_REG_CLKCFG0, &t);
++	if (t & CLKCFG0_PERI_CLK_SEL)
++		return parent_rate;
++
++	return 40000000;
++}
++
++static unsigned long mt76x8_xtal_recalc_rate(struct clk_hw *hw,
++					     unsigned long parent_rate)
++{
++	struct mtmips_clk *clk = to_mtmips_clk(hw);
++	struct regmap *sysc = clk->priv->sysc;
++	u32 t;
++
++	regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
++	if (t & MT7620_XTAL_FREQ_SEL)
++		return 40000000;
++
++	return 20000000;
++}
++
++static unsigned long mt76x8_cpu_recalc_rate(struct clk_hw *hw,
++					    unsigned long xtal_clk)
++{
++	if (xtal_clk == 40000000)
++		return 580000000;
++
++	return 575000000;
++}
++
++#define CLK_BASE(_name, _parent, _recalc) {				\
++	.init = &(const struct clk_init_data) {				\
++		.name = _name,						\
++		.ops = &(const struct clk_ops) {			\
++			.recalc_rate = _recalc,				\
++		},							\
++		.parent_data = &(const struct clk_parent_data) {	\
++			.name = _parent,				\
++			.fw_name = _parent				\
++		},							\
++		.num_parents = _parent ? 1 : 0				\
++	},								\
++}
++
++static struct mtmips_clk rt2880_clks_base[] = {
++	{ CLK_BASE("cpu", "xtal", rt2880_cpu_recalc_rate) }
++};
++
++static struct mtmips_clk rt305x_clks_base[] = {
++	{ CLK_BASE("cpu", "xtal", rt305x_cpu_recalc_rate) }
++};
++
++static struct mtmips_clk rt3352_clks_base[] = {
++	{ CLK_BASE("xtal", NULL, rt5350_xtal_recalc_rate) },
++	{ CLK_BASE("cpu", "xtal", rt3352_cpu_recalc_rate) }
++};
++
++static struct mtmips_clk rt3883_clks_base[] = {
++	{ CLK_BASE("cpu", "xtal", rt3883_cpu_recalc_rate) },
++	{ CLK_BASE("bus", "cpu", rt3883_bus_recalc_rate) }
++};
++
++static struct mtmips_clk rt5350_clks_base[] = {
++	{ CLK_BASE("xtal", NULL, rt5350_xtal_recalc_rate) },
++	{ CLK_BASE("cpu", "xtal", rt5350_cpu_recalc_rate) },
++	{ CLK_BASE("bus", "cpu", rt5350_bus_recalc_rate) }
++};
++
++static struct mtmips_clk mt7620_clks_base[] = {
++	{ CLK_BASE("xtal", NULL, mt76x8_xtal_recalc_rate) },
++	{ CLK_BASE("pll", "xtal", mt7620_pll_recalc_rate) },
++	{ CLK_BASE("cpu", "pll", mt7620_cpu_recalc_rate) },
++	{ CLK_BASE("periph", "xtal", mt7620_periph_recalc_rate) },
++	{ CLK_BASE("bus", "cpu", mt7620_bus_recalc_rate) }
++};
++
++static struct mtmips_clk mt76x8_clks_base[] = {
++	{ CLK_BASE("xtal", NULL, mt76x8_xtal_recalc_rate) },
++	{ CLK_BASE("cpu", "xtal", mt76x8_cpu_recalc_rate) }
++};
++
++static int mtmips_register_clocks(struct device_node *np,
++				  struct clk_hw_onecell_data *clk_data,
++				  struct mtmips_clk_priv *priv)
++{
++	struct clk_hw **hws = clk_data->hws;
++	struct mtmips_clk *sclk;
++	int ret, i;
++
++	for (i = 0; i < priv->data->num_clk_base; i++) {
++		sclk = &priv->data->clk_base[i];
++		sclk->priv = priv;
++		ret = of_clk_hw_register(np, &sclk->hw);
++		if (ret) {
++			pr_err("Couldn't register top clock %i\n", i);
++			goto err_clk_unreg;
++		}
++
++		hws[i] = &sclk->hw;
++	}
++
++	return 0;
++
++err_clk_unreg:
++	while (--i >= 0) {
++		sclk = &priv->data->clk_base[i];
++		clk_hw_unregister(&sclk->hw);
++	}
++	return ret;
++}
++
++static const struct mtmips_clk_data rt2880_clk_data = {
++	.clk_base = rt2880_clks_base,
++	.num_clk_base = ARRAY_SIZE(rt2880_clks_base),
++	.clk_fixed = rt305x_fixed_clocks,
++	.num_clk_fixed = ARRAY_SIZE(rt305x_fixed_clocks),
++	.clk_factor = rt2880_factor_clocks,
++	.num_clk_factor = ARRAY_SIZE(rt2880_factor_clocks),
++	.clk_periph = rt2880_pherip_clks,
++	.num_clk_periph = ARRAY_SIZE(rt2880_pherip_clks),
++};
++
++static const struct mtmips_clk_data rt305x_clk_data = {
++	.clk_base = rt305x_clks_base,
++	.num_clk_base = ARRAY_SIZE(rt305x_clks_base),
++	.clk_fixed = rt305x_fixed_clocks,
++	.num_clk_fixed = ARRAY_SIZE(rt305x_fixed_clocks),
++	.clk_factor = rt305x_factor_clocks,
++	.num_clk_factor = ARRAY_SIZE(rt305x_factor_clocks),
++	.clk_periph = rt305x_pherip_clks,
++	.num_clk_periph = ARRAY_SIZE(rt305x_pherip_clks),
++};
++
++static const struct mtmips_clk_data rt3352_clk_data = {
++	.clk_base = rt3352_clks_base,
++	.num_clk_base = ARRAY_SIZE(rt3352_clks_base),
++	.clk_fixed = rt3352_fixed_clocks,
++	.num_clk_fixed = ARRAY_SIZE(rt3352_fixed_clocks),
++	.clk_factor = rt305x_factor_clocks,
++	.num_clk_factor = ARRAY_SIZE(rt305x_factor_clocks),
++	.clk_periph = rt5350_pherip_clks,
++	.num_clk_periph = ARRAY_SIZE(rt5350_pherip_clks),
++};
++
++static const struct mtmips_clk_data rt3883_clk_data = {
++	.clk_base = rt3883_clks_base,
++	.num_clk_base = ARRAY_SIZE(rt3883_clks_base),
++	.clk_fixed = rt305x_fixed_clocks,
++	.num_clk_fixed = ARRAY_SIZE(rt305x_fixed_clocks),
++	.clk_factor = NULL,
++	.num_clk_factor = 0,
++	.clk_periph = rt5350_pherip_clks,
++	.num_clk_periph = ARRAY_SIZE(rt5350_pherip_clks),
++};
++
++static const struct mtmips_clk_data rt5350_clk_data = {
++	.clk_base = rt5350_clks_base,
++	.num_clk_base = ARRAY_SIZE(rt5350_clks_base),
++	.clk_fixed = rt3352_fixed_clocks,
++	.num_clk_fixed = ARRAY_SIZE(rt3352_fixed_clocks),
++	.clk_factor = NULL,
++	.num_clk_factor = 0,
++	.clk_periph = rt5350_pherip_clks,
++	.num_clk_periph = ARRAY_SIZE(rt5350_pherip_clks),
++};
++
++static const struct mtmips_clk_data mt7620_clk_data = {
++	.clk_base = mt7620_clks_base,
++	.num_clk_base = ARRAY_SIZE(mt7620_clks_base),
++	.clk_fixed = NULL,
++	.num_clk_fixed = 0,
++	.clk_factor = NULL,
++	.num_clk_factor = 0,
++	.clk_periph = mt7620_pherip_clks,
++	.num_clk_periph = ARRAY_SIZE(mt7620_pherip_clks),
++};
++
++static const struct mtmips_clk_data mt76x8_clk_data = {
++	.clk_base = mt76x8_clks_base,
++	.num_clk_base = ARRAY_SIZE(mt76x8_clks_base),
++	.clk_fixed = mt76x8_fixed_clocks,
++	.num_clk_fixed = ARRAY_SIZE(mt76x8_fixed_clocks),
++	.clk_factor = rt305x_factor_clocks,
++	.num_clk_factor = ARRAY_SIZE(rt305x_factor_clocks),
++	.clk_periph = mt76x8_pherip_clks,
++	.num_clk_periph = ARRAY_SIZE(mt76x8_pherip_clks),
++};
++
++static const struct of_device_id mtmips_of_match[] = {
++	{
++		.compatible = "ralink,rt2880-sysc",
++		.data = &rt2880_clk_data,
++	},
++	{
++		.compatible = "ralink,rt3050-sysc",
++		.data = &rt305x_clk_data,
++	},
++	{
++		.compatible = "ralink,rt3052-sysc",
++		.data = &rt305x_clk_data,
++	},
++	{
++		.compatible = "ralink,rt3352-sysc",
++		.data = &rt3352_clk_data,
++	},
++	{
++		.compatible = "ralink,rt3883-sysc",
++		.data = &rt3883_clk_data,
++	},
++	{
++		.compatible = "ralink,rt5350-sysc",
++		.data = &rt5350_clk_data,
++	},
++	{
++		.compatible = "ralink,mt7620-sysc",
++		.data = &mt7620_clk_data,
++	},
++	{
++		.compatible = "ralink,mt7628-sysc",
++		.data = &mt76x8_clk_data,
++	},
++	{
++		.compatible = "ralink,mt7688-sysc",
++		.data = &mt76x8_clk_data,
++	},
++	{}
++};
++
++static void __init mtmips_clk_regs_init(struct device_node *node,
++					struct mtmips_clk_priv *priv)
++{
++	u32 t;
++
++	if (!of_device_is_compatible(node, "ralink,mt7620-sysc"))
++		return;
++
++	/*
++	 * When the CPU goes into sleep mode, the BUS
++	 * clock will be too low for USB to function properly.
++	 * Adjust the busses fractional divider to fix this
++	 */
++	regmap_read(priv->sysc, SYSC_REG_CPU_SYS_CLKCFG, &t);
++	t &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK);
++	t |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL;
++	regmap_write(priv->sysc, SYSC_REG_CPU_SYS_CLKCFG, t);
++}
++
++static void __init mtmips_clk_init(struct device_node *node)
++{
++	const struct of_device_id *match;
++	const struct mtmips_clk_data *data;
++	struct mtmips_clk_priv *priv;
++	struct clk_hw_onecell_data *clk_data;
++	int ret, i, count;
++
++	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
++	if (!priv)
++		return;
++
++	priv->sysc = syscon_node_to_regmap(node);
++	if (IS_ERR(priv->sysc)) {
++		pr_err("Could not get sysc syscon regmap\n");
++		goto free_clk_priv;
++	}
++
++	mtmips_clk_regs_init(node, priv);
++
++	match = of_match_node(mtmips_of_match, node);
++	if (WARN_ON(!match))
++		return;
++
++	data = match->data;
++	priv->data = data;
++	count = priv->data->num_clk_base + priv->data->num_clk_fixed +
++		priv->data->num_clk_factor + priv->data->num_clk_periph;
++	clk_data = kzalloc(struct_size(clk_data, hws, count), GFP_KERNEL);
++	if (!clk_data)
++		goto free_clk_priv;
++
++	ret = mtmips_register_clocks(node, clk_data, priv);
++	if (ret) {
++		pr_err("Couldn't register top clocks\n");
++		goto free_clk_data;
++	}
++
++	ret = mtmips_register_fixed_clocks(clk_data, priv);
++	if (ret) {
++		pr_err("Couldn't register fixed clocks\n");
++		goto unreg_clk_top;
++	}
++
++	ret = mtmips_register_factor_clocks(clk_data, priv);
++	if (ret) {
++		pr_err("Couldn't register factor clocks\n");
++		goto unreg_clk_fixed;
++	}
++
++	ret = mtmips_register_pherip_clocks(node, clk_data, priv);
++	if (ret) {
++		pr_err("Couldn't register peripheral clocks\n");
++		goto unreg_clk_factor;
++	}
++
++	clk_data->num = count;
++
++	ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
++	if (ret) {
++		pr_err("Couldn't add clk hw provider\n");
++		goto unreg_clk_periph;
++	}
++
++	return;
++
++unreg_clk_periph:
++	for (i = 0; i < priv->data->num_clk_periph; i++) {
++		struct mtmips_clk *sclk = &priv->data->clk_periph[i];
++
++		clk_hw_unregister(&sclk->hw);
++	}
++
++unreg_clk_factor:
++	for (i = 0; i < priv->data->num_clk_factor; i++) {
++		struct mtmips_clk_factor *sclk = &priv->data->clk_factor[i];
++
++		clk_hw_unregister_fixed_factor(sclk->hw);
++	}
++
++unreg_clk_fixed:
++	for (i = 0; i < priv->data->num_clk_fixed; i++) {
++		struct mtmips_clk_fixed *sclk = &priv->data->clk_fixed[i];
++
++		clk_hw_unregister_fixed_rate(sclk->hw);
++	}
++
++unreg_clk_top:
++	for (i = 0; i < priv->data->num_clk_base; i++) {
++		struct mtmips_clk *sclk = &priv->data->clk_base[i];
++
++		clk_hw_unregister(&sclk->hw);
++	}
++
++free_clk_data:
++	kfree(clk_data);
++
++free_clk_priv:
++	kfree(priv);
++}
++CLK_OF_DECLARE_DRIVER(rt2880_clk, "ralink,rt2880-sysc", mtmips_clk_init);
++CLK_OF_DECLARE_DRIVER(rt3050_clk, "ralink,rt3050-sysc", mtmips_clk_init);
++CLK_OF_DECLARE_DRIVER(rt3052_clk, "ralink,rt3052-sysc", mtmips_clk_init);
++CLK_OF_DECLARE_DRIVER(rt3352_clk, "ralink,rt3352-sysc", mtmips_clk_init);
++CLK_OF_DECLARE_DRIVER(rt3883_clk, "ralink,rt3883-sysc", mtmips_clk_init);
++CLK_OF_DECLARE_DRIVER(rt5350_clk, "ralink,rt5350-sysc", mtmips_clk_init);
++CLK_OF_DECLARE_DRIVER(mt7620_clk, "ralink,mt7620-sysc", mtmips_clk_init);
++CLK_OF_DECLARE_DRIVER(mt7628_clk, "ralink,mt7628-sysc", mtmips_clk_init);
++CLK_OF_DECLARE_DRIVER(mt7688_clk, "ralink,mt7688-sysc", mtmips_clk_init);
++
++struct mtmips_rst {
++	struct reset_controller_dev rcdev;
++	struct regmap *sysc;
++};
++
++static struct mtmips_rst *to_mtmips_rst(struct reset_controller_dev *dev)
++{
++	return container_of(dev, struct mtmips_rst, rcdev);
++}
++
++static int mtmips_assert_device(struct reset_controller_dev *rcdev,
++				unsigned long id)
++{
++	struct mtmips_rst *data = to_mtmips_rst(rcdev);
++	struct regmap *sysc = data->sysc;
++
++	return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), BIT(id));
++}
++
++static int mtmips_deassert_device(struct reset_controller_dev *rcdev,
++				  unsigned long id)
++{
++	struct mtmips_rst *data = to_mtmips_rst(rcdev);
++	struct regmap *sysc = data->sysc;
++
++	return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), 0);
++}
++
++static int mtmips_reset_device(struct reset_controller_dev *rcdev,
++			       unsigned long id)
++{
++	int ret;
++
++	ret = mtmips_assert_device(rcdev, id);
++	if (ret < 0)
++		return ret;
++
++	return mtmips_deassert_device(rcdev, id);
++}
++
++static int mtmips_rst_xlate(struct reset_controller_dev *rcdev,
++			    const struct of_phandle_args *reset_spec)
++{
++	unsigned long id = reset_spec->args[0];
++
++	if (id == 0 || id >= rcdev->nr_resets)
++		return -EINVAL;
++
++	return id;
++}
++
++static const struct reset_control_ops reset_ops = {
++	.reset = mtmips_reset_device,
++	.assert = mtmips_assert_device,
++	.deassert = mtmips_deassert_device
++};
++
++static int mtmips_reset_init(struct device *dev, struct regmap *sysc)
++{
++	struct mtmips_rst *rst_data;
++
++	rst_data = devm_kzalloc(dev, sizeof(*rst_data), GFP_KERNEL);
++	if (!rst_data)
++		return -ENOMEM;
++
++	rst_data->sysc = sysc;
++	rst_data->rcdev.ops = &reset_ops;
++	rst_data->rcdev.owner = THIS_MODULE;
++	rst_data->rcdev.nr_resets = 32;
++	rst_data->rcdev.of_reset_n_cells = 1;
++	rst_data->rcdev.of_xlate = mtmips_rst_xlate;
++	rst_data->rcdev.of_node = dev_of_node(dev);
++
++	return devm_reset_controller_register(dev, &rst_data->rcdev);
++}
++
++static int mtmips_clk_probe(struct platform_device *pdev)
++{
++	struct device_node *np = pdev->dev.of_node;
++	struct device *dev = &pdev->dev;
++	struct mtmips_clk_priv *priv;
++	int ret;
++
++	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
++	if (!priv)
++		return -ENOMEM;
++
++	priv->sysc = syscon_node_to_regmap(np);
++	if (IS_ERR(priv->sysc))
++		return dev_err_probe(dev, PTR_ERR(priv->sysc),
++				     "Could not get sysc syscon regmap\n");
++
++	ret = mtmips_reset_init(dev, priv->sysc);
++	if (ret)
++		return dev_err_probe(dev, ret, "Could not init reset controller\n");
++
++	return 0;
++}
++
++static const struct of_device_id mtmips_clk_of_match[] = {
++	{ .compatible = "ralink,rt2880-reset" },
++	{ .compatible = "ralink,rt2880-sysc" },
++	{ .compatible = "ralink,rt3050-sysc" },
++	{ .compatible = "ralink,rt3052-sysc" },
++	{ .compatible = "ralink,rt3352-sysc" },
++	{ .compatible = "ralink,rt3883-sysc" },
++	{ .compatible = "ralink,rt5350-sysc" },
++	{ .compatible = "ralink,mt7620-sysc" },
++	{ .compatible = "ralink,mt7628-sysc" },
++	{ .compatible = "ralink,mt7688-sysc" },
++	{}
++};
++
++static struct platform_driver mtmips_clk_driver = {
++	.probe = mtmips_clk_probe,
++	.driver = {
++		.name = "mtmips-clk",
++		.of_match_table = mtmips_clk_of_match,
++	},
++};
++
++static int __init mtmips_clk_reset_init(void)
++{
++	return platform_driver_register(&mtmips_clk_driver);
++}
++arch_initcall(mtmips_clk_reset_init);
diff --git a/target/linux/ramips/patches-6.1/005-v6.5-03-mips-ralink-rt288x-remove-clock-related-code.patch b/target/linux/ramips/patches-6.1/005-v6.5-03-mips-ralink-rt288x-remove-clock-related-code.patch
new file mode 100644
index 00000000000000..df4208b23da137
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/005-v6.5-03-mips-ralink-rt288x-remove-clock-related-code.patch
@@ -0,0 +1,81 @@
+From ffcdf47379eae86dc8f8f02c62994dacf2c9038e Mon Sep 17 00:00:00 2001
+From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Date: Mon, 19 Jun 2023 06:09:35 +0200
+Subject: [PATCH 3/9] mips: ralink: rt288x: remove clock related code
+
+A properly clock driver for ralink SoCs has been added. Hence there is no
+need to have clock related code in 'arch/mips/ralink' folder anymore.
+
+Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+---
+ arch/mips/include/asm/mach-ralink/rt288x.h | 10 ----------
+ arch/mips/ralink/rt288x.c                  | 31 ------------------------------
+ 2 files changed, 41 deletions(-)
+
+--- a/arch/mips/include/asm/mach-ralink/rt288x.h
++++ b/arch/mips/include/asm/mach-ralink/rt288x.h
+@@ -17,7 +17,6 @@
+ #define SYSC_REG_CHIP_NAME1		0x04
+ #define SYSC_REG_CHIP_ID		0x0c
+ #define SYSC_REG_SYSTEM_CONFIG		0x10
+-#define SYSC_REG_CLKCFG			0x30
+ 
+ #define RT2880_CHIP_NAME0		0x38325452
+ #define RT2880_CHIP_NAME1		0x20203038
+@@ -26,15 +25,6 @@
+ #define CHIP_ID_ID_SHIFT		8
+ #define CHIP_ID_REV_MASK		0xff
+ 
+-#define SYSTEM_CONFIG_CPUCLK_SHIFT	20
+-#define SYSTEM_CONFIG_CPUCLK_MASK	0x3
+-#define SYSTEM_CONFIG_CPUCLK_250	0x0
+-#define SYSTEM_CONFIG_CPUCLK_266	0x1
+-#define SYSTEM_CONFIG_CPUCLK_280	0x2
+-#define SYSTEM_CONFIG_CPUCLK_300	0x3
+-
+-#define CLKCFG_SRAM_CS_N_WDT		BIT(9)
+-
+ #define RT2880_SDRAM_BASE		0x08000000
+ #define RT2880_MEM_SIZE_MIN		2
+ #define RT2880_MEM_SIZE_MAX		128
+--- a/arch/mips/ralink/rt288x.c
++++ b/arch/mips/ralink/rt288x.c
+@@ -17,37 +17,6 @@
+ 
+ #include "common.h"
+ 
+-void __init ralink_clk_init(void)
+-{
+-	unsigned long cpu_rate, wmac_rate = 40000000;
+-	u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
+-	t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK);
+-
+-	switch (t) {
+-	case SYSTEM_CONFIG_CPUCLK_250:
+-		cpu_rate = 250000000;
+-		break;
+-	case SYSTEM_CONFIG_CPUCLK_266:
+-		cpu_rate = 266666667;
+-		break;
+-	case SYSTEM_CONFIG_CPUCLK_280:
+-		cpu_rate = 280000000;
+-		break;
+-	case SYSTEM_CONFIG_CPUCLK_300:
+-		cpu_rate = 300000000;
+-		break;
+-	}
+-
+-	ralink_clk_add("cpu", cpu_rate);
+-	ralink_clk_add("300100.timer", cpu_rate / 2);
+-	ralink_clk_add("300120.watchdog", cpu_rate / 2);
+-	ralink_clk_add("300500.uart", cpu_rate / 2);
+-	ralink_clk_add("300900.i2c", cpu_rate / 2);
+-	ralink_clk_add("300c00.uartlite", cpu_rate / 2);
+-	ralink_clk_add("400000.ethernet", cpu_rate / 2);
+-	ralink_clk_add("480000.wmac", wmac_rate);
+-}
+-
+ void __init ralink_of_remap(void)
+ {
+ 	rt_sysc_membase = plat_of_remap_node("ralink,rt2880-sysc");
diff --git a/target/linux/ramips/patches-6.1/005-v6.5-04-mips-ralink-rt305x-remove-clock-related-code.patch b/target/linux/ramips/patches-6.1/005-v6.5-04-mips-ralink-rt305x-remove-clock-related-code.patch
new file mode 100644
index 00000000000000..12b4623b73ef45
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/005-v6.5-04-mips-ralink-rt305x-remove-clock-related-code.patch
@@ -0,0 +1,145 @@
+From daf73c70f69386fb15960526772ef584a4efcaf2 Mon Sep 17 00:00:00 2001
+From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Date: Mon, 19 Jun 2023 06:09:36 +0200
+Subject: [PATCH 4/9] mips: ralink: rt305x: remove clock related code
+
+A properly clock driver for ralink SoCs has been added. Hence there is no
+need to have clock related code in 'arch/mips/ralink' folder anymore.
+
+Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+---
+ arch/mips/include/asm/mach-ralink/rt305x.h | 21 --------
+ arch/mips/ralink/rt305x.c                  | 78 ------------------------------
+ 2 files changed, 99 deletions(-)
+
+--- a/arch/mips/include/asm/mach-ralink/rt305x.h
++++ b/arch/mips/include/asm/mach-ralink/rt305x.h
+@@ -66,26 +66,9 @@ static inline int soc_is_rt5350(void)
+ #define CHIP_ID_ID_SHIFT		8
+ #define CHIP_ID_REV_MASK		0xff
+ 
+-#define RT305X_SYSCFG_CPUCLK_SHIFT		18
+-#define RT305X_SYSCFG_CPUCLK_MASK		0x1
+-#define RT305X_SYSCFG_CPUCLK_LOW		0x0
+-#define RT305X_SYSCFG_CPUCLK_HIGH		0x1
+-
+ #define RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT	2
+-#define RT305X_SYSCFG_CPUCLK_MASK		0x1
+ #define RT305X_SYSCFG_SRAM_CS0_MODE_WDT		0x1
+ 
+-#define RT3352_SYSCFG0_CPUCLK_SHIFT	8
+-#define RT3352_SYSCFG0_CPUCLK_MASK	0x1
+-#define RT3352_SYSCFG0_CPUCLK_LOW	0x0
+-#define RT3352_SYSCFG0_CPUCLK_HIGH	0x1
+-
+-#define RT5350_SYSCFG0_CPUCLK_SHIFT	8
+-#define RT5350_SYSCFG0_CPUCLK_MASK	0x3
+-#define RT5350_SYSCFG0_CPUCLK_360	0x0
+-#define RT5350_SYSCFG0_CPUCLK_320	0x2
+-#define RT5350_SYSCFG0_CPUCLK_300	0x3
+-
+ #define RT5350_SYSCFG0_DRAM_SIZE_SHIFT  12
+ #define RT5350_SYSCFG0_DRAM_SIZE_MASK   7
+ #define RT5350_SYSCFG0_DRAM_SIZE_2M     0
+@@ -116,13 +99,9 @@ static inline int soc_is_rt5350(void)
+ 
+ #define RT3352_SYSC_REG_SYSCFG0		0x010
+ #define RT3352_SYSC_REG_SYSCFG1         0x014
+-#define RT3352_SYSC_REG_CLKCFG1         0x030
+ #define RT3352_SYSC_REG_RSTCTRL         0x034
+ #define RT3352_SYSC_REG_USB_PS          0x05c
+ 
+-#define RT3352_CLKCFG0_XTAL_SEL		BIT(20)
+-#define RT3352_CLKCFG1_UPHY0_CLK_EN	BIT(18)
+-#define RT3352_CLKCFG1_UPHY1_CLK_EN	BIT(20)
+ #define RT3352_RSTCTRL_UHST		BIT(22)
+ #define RT3352_RSTCTRL_UDEV		BIT(25)
+ #define RT3352_SYSCFG1_USB0_HOST_MODE	BIT(10)
+--- a/arch/mips/ralink/rt305x.c
++++ b/arch/mips/ralink/rt305x.c
+@@ -53,84 +53,6 @@ static unsigned long rt5350_get_mem_size
+ 	return ret;
+ }
+ 
+-void __init ralink_clk_init(void)
+-{
+-	unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate;
+-	unsigned long wmac_rate = 40000000;
+-
+-	u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
+-
+-	if (soc_is_rt305x() || soc_is_rt3350()) {
+-		t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) &
+-		     RT305X_SYSCFG_CPUCLK_MASK;
+-		switch (t) {
+-		case RT305X_SYSCFG_CPUCLK_LOW:
+-			cpu_rate = 320000000;
+-			break;
+-		case RT305X_SYSCFG_CPUCLK_HIGH:
+-			cpu_rate = 384000000;
+-			break;
+-		}
+-		sys_rate = uart_rate = wdt_rate = cpu_rate / 3;
+-	} else if (soc_is_rt3352()) {
+-		t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) &
+-		     RT3352_SYSCFG0_CPUCLK_MASK;
+-		switch (t) {
+-		case RT3352_SYSCFG0_CPUCLK_LOW:
+-			cpu_rate = 384000000;
+-			break;
+-		case RT3352_SYSCFG0_CPUCLK_HIGH:
+-			cpu_rate = 400000000;
+-			break;
+-		}
+-		sys_rate = wdt_rate = cpu_rate / 3;
+-		uart_rate = 40000000;
+-	} else if (soc_is_rt5350()) {
+-		t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) &
+-		     RT5350_SYSCFG0_CPUCLK_MASK;
+-		switch (t) {
+-		case RT5350_SYSCFG0_CPUCLK_360:
+-			cpu_rate = 360000000;
+-			sys_rate = cpu_rate / 3;
+-			break;
+-		case RT5350_SYSCFG0_CPUCLK_320:
+-			cpu_rate = 320000000;
+-			sys_rate = cpu_rate / 4;
+-			break;
+-		case RT5350_SYSCFG0_CPUCLK_300:
+-			cpu_rate = 300000000;
+-			sys_rate = cpu_rate / 3;
+-			break;
+-		default:
+-			BUG();
+-		}
+-		uart_rate = 40000000;
+-		wdt_rate = sys_rate;
+-	} else {
+-		BUG();
+-	}
+-
+-	if (soc_is_rt3352() || soc_is_rt5350()) {
+-		u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0);
+-
+-		if (!(val & RT3352_CLKCFG0_XTAL_SEL))
+-			wmac_rate = 20000000;
+-	}
+-
+-	ralink_clk_add("cpu", cpu_rate);
+-	ralink_clk_add("sys", sys_rate);
+-	ralink_clk_add("10000900.i2c", uart_rate);
+-	ralink_clk_add("10000a00.i2s", uart_rate);
+-	ralink_clk_add("10000b00.spi", sys_rate);
+-	ralink_clk_add("10000b40.spi", sys_rate);
+-	ralink_clk_add("10000100.timer", wdt_rate);
+-	ralink_clk_add("10000120.watchdog", wdt_rate);
+-	ralink_clk_add("10000500.uart", uart_rate);
+-	ralink_clk_add("10000c00.uartlite", uart_rate);
+-	ralink_clk_add("10100000.ethernet", sys_rate);
+-	ralink_clk_add("10180000.wmac", wmac_rate);
+-}
+-
+ void __init ralink_of_remap(void)
+ {
+ 	rt_sysc_membase = plat_of_remap_node("ralink,rt3050-sysc");
diff --git a/target/linux/ramips/patches-6.1/005-v6.5-05-mips-ralink-rt3883-remove-clock-related-code.patch b/target/linux/ramips/patches-6.1/005-v6.5-05-mips-ralink-rt3883-remove-clock-related-code.patch
new file mode 100644
index 00000000000000..c13c4215f3a51f
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/005-v6.5-05-mips-ralink-rt3883-remove-clock-related-code.patch
@@ -0,0 +1,85 @@
+From 7cd1bb48885449a9323c7ff0f10012925e93b4e1 Mon Sep 17 00:00:00 2001
+From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Date: Mon, 19 Jun 2023 06:09:37 +0200
+Subject: [PATCH 5/9] mips: ralink: rt3883: remove clock related code
+
+A properly clock driver for ralink SoCs has been added. Hence there is no
+need to have clock related code in 'arch/mips/ralink' folder anymore.
+
+Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+---
+ arch/mips/include/asm/mach-ralink/rt3883.h |  8 ------
+ arch/mips/ralink/rt3883.c                  | 44 ------------------------------
+ 2 files changed, 52 deletions(-)
+
+--- a/arch/mips/include/asm/mach-ralink/rt3883.h
++++ b/arch/mips/include/asm/mach-ralink/rt3883.h
+@@ -90,14 +90,6 @@
+ #define RT3883_REVID_VER_ID_SHIFT	8
+ #define RT3883_REVID_ECO_ID_MASK	0x0f
+ 
+-#define RT3883_SYSCFG0_DRAM_TYPE_DDR2	BIT(17)
+-#define RT3883_SYSCFG0_CPUCLK_SHIFT	8
+-#define RT3883_SYSCFG0_CPUCLK_MASK	0x3
+-#define RT3883_SYSCFG0_CPUCLK_250	0x0
+-#define RT3883_SYSCFG0_CPUCLK_384	0x1
+-#define RT3883_SYSCFG0_CPUCLK_480	0x2
+-#define RT3883_SYSCFG0_CPUCLK_500	0x3
+-
+ #define RT3883_SYSCFG1_USB0_HOST_MODE	BIT(10)
+ #define RT3883_SYSCFG1_PCIE_RC_MODE	BIT(8)
+ #define RT3883_SYSCFG1_PCI_HOST_MODE	BIT(7)
+--- a/arch/mips/ralink/rt3883.c
++++ b/arch/mips/ralink/rt3883.c
+@@ -17,50 +17,6 @@
+ 
+ #include "common.h"
+ 
+-void __init ralink_clk_init(void)
+-{
+-	unsigned long cpu_rate, sys_rate;
+-	u32 syscfg0;
+-	u32 clksel;
+-	u32 ddr2;
+-
+-	syscfg0 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG0);
+-	clksel = ((syscfg0 >> RT3883_SYSCFG0_CPUCLK_SHIFT) &
+-		RT3883_SYSCFG0_CPUCLK_MASK);
+-	ddr2 = syscfg0 & RT3883_SYSCFG0_DRAM_TYPE_DDR2;
+-
+-	switch (clksel) {
+-	case RT3883_SYSCFG0_CPUCLK_250:
+-		cpu_rate = 250000000;
+-		sys_rate = (ddr2) ? 125000000 : 83000000;
+-		break;
+-	case RT3883_SYSCFG0_CPUCLK_384:
+-		cpu_rate = 384000000;
+-		sys_rate = (ddr2) ? 128000000 : 96000000;
+-		break;
+-	case RT3883_SYSCFG0_CPUCLK_480:
+-		cpu_rate = 480000000;
+-		sys_rate = (ddr2) ? 160000000 : 120000000;
+-		break;
+-	case RT3883_SYSCFG0_CPUCLK_500:
+-		cpu_rate = 500000000;
+-		sys_rate = (ddr2) ? 166000000 : 125000000;
+-		break;
+-	}
+-
+-	ralink_clk_add("cpu", cpu_rate);
+-	ralink_clk_add("10000100.timer", sys_rate);
+-	ralink_clk_add("10000120.watchdog", sys_rate);
+-	ralink_clk_add("10000500.uart", 40000000);
+-	ralink_clk_add("10000900.i2c", 40000000);
+-	ralink_clk_add("10000a00.i2s", 40000000);
+-	ralink_clk_add("10000b00.spi", sys_rate);
+-	ralink_clk_add("10000b40.spi", sys_rate);
+-	ralink_clk_add("10000c00.uartlite", 40000000);
+-	ralink_clk_add("10100000.ethernet", sys_rate);
+-	ralink_clk_add("10180000.wmac", 40000000);
+-}
+-
+ void __init ralink_of_remap(void)
+ {
+ 	rt_sysc_membase = plat_of_remap_node("ralink,rt3883-sysc");
diff --git a/target/linux/ramips/patches-6.1/005-v6.5-06-mips-ralink-mt7620-remove-clock-related-code.patch b/target/linux/ramips/patches-6.1/005-v6.5-06-mips-ralink-mt7620-remove-clock-related-code.patch
new file mode 100644
index 00000000000000..7b83cf54b49e15
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/005-v6.5-06-mips-ralink-mt7620-remove-clock-related-code.patch
@@ -0,0 +1,327 @@
+From 04b153abdfcbaba70ceef5a846067d4447fd0078 Mon Sep 17 00:00:00 2001
+From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Date: Mon, 19 Jun 2023 06:09:38 +0200
+Subject: [PATCH 6/9] mips: ralink: mt7620: remove clock related code
+
+A proper clock driver for ralink SoCs has been added. Hence there is no
+need to have clock related code in 'arch/mips/ralink' folder anymore.
+Since this is the last clock related code removal, remove also remaining
+prototypes in 'common.h' header file.
+
+Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+---
+ arch/mips/include/asm/mach-ralink/mt7620.h |  35 -----
+ arch/mips/ralink/common.h                  |   3 -
+ arch/mips/ralink/mt7620.c                  | 226 -----------------------------
+ 3 files changed, 264 deletions(-)
+
+--- a/arch/mips/include/asm/mach-ralink/mt7620.h
++++ b/arch/mips/include/asm/mach-ralink/mt7620.h
+@@ -19,52 +19,17 @@
+ #define SYSC_REG_CHIP_REV		0x0c
+ #define SYSC_REG_SYSTEM_CONFIG0		0x10
+ #define SYSC_REG_SYSTEM_CONFIG1		0x14
+-#define SYSC_REG_CLKCFG0		0x2c
+-#define SYSC_REG_CPU_SYS_CLKCFG		0x3c
+-#define SYSC_REG_CPLL_CONFIG0		0x54
+-#define SYSC_REG_CPLL_CONFIG1		0x58
+ 
+ #define MT7620_CHIP_NAME0		0x3637544d
+ #define MT7620_CHIP_NAME1		0x20203032
+ #define MT7628_CHIP_NAME1		0x20203832
+ 
+-#define SYSCFG0_XTAL_FREQ_SEL		BIT(6)
+-
+ #define CHIP_REV_PKG_MASK		0x1
+ #define CHIP_REV_PKG_SHIFT		16
+ #define CHIP_REV_VER_MASK		0xf
+ #define CHIP_REV_VER_SHIFT		8
+ #define CHIP_REV_ECO_MASK		0xf
+ 
+-#define CLKCFG0_PERI_CLK_SEL		BIT(4)
+-
+-#define CPU_SYS_CLKCFG_OCP_RATIO_SHIFT	16
+-#define CPU_SYS_CLKCFG_OCP_RATIO_MASK	0xf
+-#define CPU_SYS_CLKCFG_OCP_RATIO_1	0	/* 1:1   (Reserved) */
+-#define CPU_SYS_CLKCFG_OCP_RATIO_1_5	1	/* 1:1.5 (Reserved) */
+-#define CPU_SYS_CLKCFG_OCP_RATIO_2	2	/* 1:2   */
+-#define CPU_SYS_CLKCFG_OCP_RATIO_2_5	3       /* 1:2.5 (Reserved) */
+-#define CPU_SYS_CLKCFG_OCP_RATIO_3	4	/* 1:3   */
+-#define CPU_SYS_CLKCFG_OCP_RATIO_3_5	5	/* 1:3.5 (Reserved) */
+-#define CPU_SYS_CLKCFG_OCP_RATIO_4	6	/* 1:4   */
+-#define CPU_SYS_CLKCFG_OCP_RATIO_5	7	/* 1:5   */
+-#define CPU_SYS_CLKCFG_OCP_RATIO_10	8	/* 1:10  */
+-#define CPU_SYS_CLKCFG_CPU_FDIV_SHIFT	8
+-#define CPU_SYS_CLKCFG_CPU_FDIV_MASK	0x1f
+-#define CPU_SYS_CLKCFG_CPU_FFRAC_SHIFT	0
+-#define CPU_SYS_CLKCFG_CPU_FFRAC_MASK	0x1f
+-
+-#define CPLL_CFG0_SW_CFG		BIT(31)
+-#define CPLL_CFG0_PLL_MULT_RATIO_SHIFT	16
+-#define CPLL_CFG0_PLL_MULT_RATIO_MASK   0x7
+-#define CPLL_CFG0_LC_CURFCK		BIT(15)
+-#define CPLL_CFG0_BYPASS_REF_CLK	BIT(14)
+-#define CPLL_CFG0_PLL_DIV_RATIO_SHIFT	10
+-#define CPLL_CFG0_PLL_DIV_RATIO_MASK	0x3
+-
+-#define CPLL_CFG1_CPU_AUX1		BIT(25)
+-#define CPLL_CFG1_CPU_AUX0		BIT(24)
+-
+ #define SYSCFG0_DRAM_TYPE_MASK		0x3
+ #define SYSCFG0_DRAM_TYPE_SHIFT		4
+ #define SYSCFG0_DRAM_TYPE_SDRAM		0
+--- a/arch/mips/ralink/common.h
++++ b/arch/mips/ralink/common.h
+@@ -23,9 +23,6 @@ extern struct ralink_soc_info soc_info;
+ 
+ extern void ralink_of_remap(void);
+ 
+-extern void ralink_clk_init(void);
+-extern void ralink_clk_add(const char *dev, unsigned long rate);
+-
+ extern void ralink_rst_init(void);
+ 
+ extern void __init prom_soc_init(struct ralink_soc_info *soc_info);
+--- a/arch/mips/ralink/mt7620.c
++++ b/arch/mips/ralink/mt7620.c
+@@ -34,12 +34,6 @@
+ #define PMU1_CFG		0x8C
+ #define DIG_SW_SEL		BIT(25)
+ 
+-/* clock scaling */
+-#define CLKCFG_FDIV_MASK	0x1f00
+-#define CLKCFG_FDIV_USB_VAL	0x0300
+-#define CLKCFG_FFRAC_MASK	0x001f
+-#define CLKCFG_FFRAC_USB_VAL	0x0003
+-
+ /* EFUSE bits */
+ #define EFUSE_MT7688		0x100000
+ 
+@@ -49,226 +43,6 @@
+ /* does the board have sdram or ddram */
+ static int dram_type;
+ 
+-static __init u32
+-mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div)
+-{
+-	u64 t;
+-
+-	t = ref_rate;
+-	t *= mul;
+-	do_div(t, div);
+-
+-	return t;
+-}
+-
+-#define MHZ(x)		((x) * 1000 * 1000)
+-
+-static __init unsigned long
+-mt7620_get_xtal_rate(void)
+-{
+-	u32 reg;
+-
+-	reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
+-	if (reg & SYSCFG0_XTAL_FREQ_SEL)
+-		return MHZ(40);
+-
+-	return MHZ(20);
+-}
+-
+-static __init unsigned long
+-mt7620_get_periph_rate(unsigned long xtal_rate)
+-{
+-	u32 reg;
+-
+-	reg = rt_sysc_r32(SYSC_REG_CLKCFG0);
+-	if (reg & CLKCFG0_PERI_CLK_SEL)
+-		return xtal_rate;
+-
+-	return MHZ(40);
+-}
+-
+-static const u32 mt7620_clk_divider[] __initconst = { 2, 3, 4, 8 };
+-
+-static __init unsigned long
+-mt7620_get_cpu_pll_rate(unsigned long xtal_rate)
+-{
+-	u32 reg;
+-	u32 mul;
+-	u32 div;
+-
+-	reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0);
+-	if (reg & CPLL_CFG0_BYPASS_REF_CLK)
+-		return xtal_rate;
+-
+-	if ((reg & CPLL_CFG0_SW_CFG) == 0)
+-		return MHZ(600);
+-
+-	mul = (reg >> CPLL_CFG0_PLL_MULT_RATIO_SHIFT) &
+-	      CPLL_CFG0_PLL_MULT_RATIO_MASK;
+-	mul += 24;
+-	if (reg & CPLL_CFG0_LC_CURFCK)
+-		mul *= 2;
+-
+-	div = (reg >> CPLL_CFG0_PLL_DIV_RATIO_SHIFT) &
+-	      CPLL_CFG0_PLL_DIV_RATIO_MASK;
+-
+-	WARN_ON(div >= ARRAY_SIZE(mt7620_clk_divider));
+-
+-	return mt7620_calc_rate(xtal_rate, mul, mt7620_clk_divider[div]);
+-}
+-
+-static __init unsigned long
+-mt7620_get_pll_rate(unsigned long xtal_rate, unsigned long cpu_pll_rate)
+-{
+-	u32 reg;
+-
+-	reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1);
+-	if (reg & CPLL_CFG1_CPU_AUX1)
+-		return xtal_rate;
+-
+-	if (reg & CPLL_CFG1_CPU_AUX0)
+-		return MHZ(480);
+-
+-	return cpu_pll_rate;
+-}
+-
+-static __init unsigned long
+-mt7620_get_cpu_rate(unsigned long pll_rate)
+-{
+-	u32 reg;
+-	u32 mul;
+-	u32 div;
+-
+-	reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
+-
+-	mul = reg & CPU_SYS_CLKCFG_CPU_FFRAC_MASK;
+-	div = (reg >> CPU_SYS_CLKCFG_CPU_FDIV_SHIFT) &
+-	      CPU_SYS_CLKCFG_CPU_FDIV_MASK;
+-
+-	return mt7620_calc_rate(pll_rate, mul, div);
+-}
+-
+-static const u32 mt7620_ocp_dividers[16] __initconst = {
+-	[CPU_SYS_CLKCFG_OCP_RATIO_2] = 2,
+-	[CPU_SYS_CLKCFG_OCP_RATIO_3] = 3,
+-	[CPU_SYS_CLKCFG_OCP_RATIO_4] = 4,
+-	[CPU_SYS_CLKCFG_OCP_RATIO_5] = 5,
+-	[CPU_SYS_CLKCFG_OCP_RATIO_10] = 10,
+-};
+-
+-static __init unsigned long
+-mt7620_get_dram_rate(unsigned long pll_rate)
+-{
+-	if (dram_type == SYSCFG0_DRAM_TYPE_SDRAM)
+-		return pll_rate / 4;
+-
+-	return pll_rate / 3;
+-}
+-
+-static __init unsigned long
+-mt7620_get_sys_rate(unsigned long cpu_rate)
+-{
+-	u32 reg;
+-	u32 ocp_ratio;
+-	u32 div;
+-
+-	reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
+-
+-	ocp_ratio = (reg >> CPU_SYS_CLKCFG_OCP_RATIO_SHIFT) &
+-		    CPU_SYS_CLKCFG_OCP_RATIO_MASK;
+-
+-	if (WARN_ON(ocp_ratio >= ARRAY_SIZE(mt7620_ocp_dividers)))
+-		return cpu_rate;
+-
+-	div = mt7620_ocp_dividers[ocp_ratio];
+-	if (WARN(!div, "invalid divider for OCP ratio %u", ocp_ratio))
+-		return cpu_rate;
+-
+-	return cpu_rate / div;
+-}
+-
+-void __init ralink_clk_init(void)
+-{
+-	unsigned long xtal_rate;
+-	unsigned long cpu_pll_rate;
+-	unsigned long pll_rate;
+-	unsigned long cpu_rate;
+-	unsigned long sys_rate;
+-	unsigned long dram_rate;
+-	unsigned long periph_rate;
+-	unsigned long pcmi2s_rate;
+-
+-	xtal_rate = mt7620_get_xtal_rate();
+-
+-#define RFMT(label)	label ":%lu.%03luMHz "
+-#define RINT(x)		((x) / 1000000)
+-#define RFRAC(x)	(((x) / 1000) % 1000)
+-
+-	if (is_mt76x8()) {
+-		if (xtal_rate == MHZ(40))
+-			cpu_rate = MHZ(580);
+-		else
+-			cpu_rate = MHZ(575);
+-		dram_rate = sys_rate = cpu_rate / 3;
+-		periph_rate = MHZ(40);
+-		pcmi2s_rate = MHZ(480);
+-
+-		ralink_clk_add("10000d00.uartlite", periph_rate);
+-		ralink_clk_add("10000e00.uartlite", periph_rate);
+-	} else {
+-		cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate);
+-		pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate);
+-
+-		cpu_rate = mt7620_get_cpu_rate(pll_rate);
+-		dram_rate = mt7620_get_dram_rate(pll_rate);
+-		sys_rate = mt7620_get_sys_rate(cpu_rate);
+-		periph_rate = mt7620_get_periph_rate(xtal_rate);
+-		pcmi2s_rate = periph_rate;
+-
+-		pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"),
+-			 RINT(xtal_rate), RFRAC(xtal_rate),
+-			 RINT(cpu_pll_rate), RFRAC(cpu_pll_rate),
+-			 RINT(pll_rate), RFRAC(pll_rate));
+-
+-		ralink_clk_add("10000500.uart", periph_rate);
+-	}
+-
+-	pr_debug(RFMT("CPU") RFMT("DRAM") RFMT("SYS") RFMT("PERIPH"),
+-		 RINT(cpu_rate), RFRAC(cpu_rate),
+-		 RINT(dram_rate), RFRAC(dram_rate),
+-		 RINT(sys_rate), RFRAC(sys_rate),
+-		 RINT(periph_rate), RFRAC(periph_rate));
+-#undef RFRAC
+-#undef RINT
+-#undef RFMT
+-
+-	ralink_clk_add("cpu", cpu_rate);
+-	ralink_clk_add("10000100.timer", periph_rate);
+-	ralink_clk_add("10000120.watchdog", periph_rate);
+-	ralink_clk_add("10000900.i2c", periph_rate);
+-	ralink_clk_add("10000a00.i2s", pcmi2s_rate);
+-	ralink_clk_add("10000b00.spi", sys_rate);
+-	ralink_clk_add("10000b40.spi", sys_rate);
+-	ralink_clk_add("10000c00.uartlite", periph_rate);
+-	ralink_clk_add("10000d00.uart1", periph_rate);
+-	ralink_clk_add("10000e00.uart2", periph_rate);
+-	ralink_clk_add("10180000.wmac", xtal_rate);
+-
+-	if (IS_ENABLED(CONFIG_USB) && !is_mt76x8()) {
+-		/*
+-		 * When the CPU goes into sleep mode, the BUS clock will be
+-		 * too low for USB to function properly. Adjust the busses
+-		 * fractional divider to fix this
+-		 */
+-		u32 val = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
+-
+-		val &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK);
+-		val |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL;
+-
+-		rt_sysc_w32(val, SYSC_REG_CPU_SYS_CLKCFG);
+-	}
+-}
+-
+ void __init ralink_of_remap(void)
+ {
+ 	rt_sysc_membase = plat_of_remap_node("ralink,mt7620a-sysc");
diff --git a/target/linux/ramips/patches-6.1/005-v6.5-07-mips-ralink-remove-reset-related-code.patch b/target/linux/ramips/patches-6.1/005-v6.5-07-mips-ralink-remove-reset-related-code.patch
new file mode 100644
index 00000000000000..e96a9084a63d9e
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/005-v6.5-07-mips-ralink-remove-reset-related-code.patch
@@ -0,0 +1,121 @@
+From 201ddc05777cd8e084b508bcdda22214bfe2895e Mon Sep 17 00:00:00 2001
+From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Date: Mon, 19 Jun 2023 06:09:39 +0200
+Subject: [PATCH 7/9] mips: ralink: remove reset related code
+
+A proper clock driver for ralink SoCs has been added. This driver is also
+a reset provider for the SoC. Hence there is no need to have reset related
+code in 'arch/mips/ralink' folder anymore. The only code that remains is
+the one related with mips_reboot_setup where a PCI reset is performed.
+We maintain this because I cannot test old ralink board with PCI to be
+sure all works if we remove also this code.
+
+Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+---
+ arch/mips/ralink/common.h |  2 --
+ arch/mips/ralink/of.c     |  4 ----
+ arch/mips/ralink/reset.c  | 61 -----------------------------------------------
+ 3 files changed, 67 deletions(-)
+
+--- a/arch/mips/ralink/common.h
++++ b/arch/mips/ralink/common.h
+@@ -23,8 +23,6 @@ extern struct ralink_soc_info soc_info;
+ 
+ extern void ralink_of_remap(void);
+ 
+-extern void ralink_rst_init(void);
+-
+ extern void __init prom_soc_init(struct ralink_soc_info *soc_info);
+ 
+ __iomem void *plat_of_remap_node(const char *node);
+--- a/arch/mips/ralink/of.c
++++ b/arch/mips/ralink/of.c
+@@ -81,10 +81,6 @@ static int __init plat_of_setup(void)
+ {
+ 	__dt_register_buses(soc_info.compatible, "palmbus");
+ 
+-	/* make sure that the reset controller is setup early */
+-	if (ralink_soc != MT762X_SOC_MT7621AT)
+-		ralink_rst_init();
+-
+ 	return 0;
+ }
+ 
+--- a/arch/mips/ralink/reset.c
++++ b/arch/mips/ralink/reset.c
+@@ -10,7 +10,6 @@
+ #include <linux/io.h>
+ #include <linux/of.h>
+ #include <linux/delay.h>
+-#include <linux/reset-controller.h>
+ 
+ #include <asm/reboot.h>
+ 
+@@ -22,66 +21,6 @@
+ #define RSTCTL_RESET_PCI	BIT(26)
+ #define RSTCTL_RESET_SYSTEM	BIT(0)
+ 
+-static int ralink_assert_device(struct reset_controller_dev *rcdev,
+-				unsigned long id)
+-{
+-	u32 val;
+-
+-	if (id == 0)
+-		return -1;
+-
+-	val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
+-	val |= BIT(id);
+-	rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
+-
+-	return 0;
+-}
+-
+-static int ralink_deassert_device(struct reset_controller_dev *rcdev,
+-				  unsigned long id)
+-{
+-	u32 val;
+-
+-	if (id == 0)
+-		return -1;
+-
+-	val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
+-	val &= ~BIT(id);
+-	rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
+-
+-	return 0;
+-}
+-
+-static int ralink_reset_device(struct reset_controller_dev *rcdev,
+-			       unsigned long id)
+-{
+-	ralink_assert_device(rcdev, id);
+-	return ralink_deassert_device(rcdev, id);
+-}
+-
+-static const struct reset_control_ops reset_ops = {
+-	.reset = ralink_reset_device,
+-	.assert = ralink_assert_device,
+-	.deassert = ralink_deassert_device,
+-};
+-
+-static struct reset_controller_dev reset_dev = {
+-	.ops			= &reset_ops,
+-	.owner			= THIS_MODULE,
+-	.nr_resets		= 32,
+-	.of_reset_n_cells	= 1,
+-};
+-
+-void ralink_rst_init(void)
+-{
+-	reset_dev.of_node = of_find_compatible_node(NULL, NULL,
+-						"ralink,rt2880-reset");
+-	if (!reset_dev.of_node)
+-		pr_err("Failed to find reset controller node");
+-	else
+-		reset_controller_register(&reset_dev);
+-}
+-
+ static void ralink_restart(char *command)
+ {
+ 	if (IS_ENABLED(CONFIG_PCI)) {
diff --git a/target/linux/ramips/patches-6.1/005-v6.5-08-mips-ralink-get-cpu-rate-from-new-driver-code.patch b/target/linux/ramips/patches-6.1/005-v6.5-08-mips-ralink-get-cpu-rate-from-new-driver-code.patch
new file mode 100644
index 00000000000000..2430c1f3753ce7
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/005-v6.5-08-mips-ralink-get-cpu-rate-from-new-driver-code.patch
@@ -0,0 +1,102 @@
+From ad38c17b0c26ae2108b50ac1eb0281a2e1ce08e9 Mon Sep 17 00:00:00 2001
+From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Date: Mon, 19 Jun 2023 06:09:40 +0200
+Subject: [PATCH 8/9] mips: ralink: get cpu rate from new driver code
+
+At very early stage on boot, there is a need to set 'mips_hpt_frequency'.
+This timer frequency is a half of the CPU frequency. To get clocks properly
+set we need to call to 'of_clk_init()' and properly get cpu clock frequency
+afterwards. Depending on the SoC, CPU clock index and compatible differs, so
+use them to get the proper clock frm the clock provider. Hence, adapt code
+to be aligned with new clock driver.
+
+Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+---
+ arch/mips/ralink/clk.c | 61 ++++++++++++++++++++++++++++++++++++++++++--------
+ 1 file changed, 52 insertions(+), 9 deletions(-)
+
+--- a/arch/mips/ralink/clk.c
++++ b/arch/mips/ralink/clk.c
+@@ -11,29 +11,72 @@
+ #include <linux/clkdev.h>
+ #include <linux/clk.h>
+ #include <linux/clk-provider.h>
++#include <asm/mach-ralink/ralink_regs.h>
+ 
+ #include <asm/time.h>
+ 
+ #include "common.h"
+ 
+-void ralink_clk_add(const char *dev, unsigned long rate)
++static const char *clk_cpu(int *idx)
+ {
+-	struct clk *clk = clk_register_fixed_rate(NULL, dev, NULL, 0, rate);
+-
+-	if (!clk)
+-		panic("failed to add clock");
+-
+-	clkdev_create(clk, NULL, "%s", dev);
++	switch (ralink_soc) {
++	case RT2880_SOC:
++		*idx = 0;
++		return "ralink,rt2880-sysc";
++	case RT3883_SOC:
++		*idx = 0;
++		return "ralink,rt3883-sysc";
++	case RT305X_SOC_RT3050:
++		*idx = 0;
++		return "ralink,rt3050-sysc";
++	case RT305X_SOC_RT3052:
++		*idx = 0;
++		return "ralink,rt3052-sysc";
++	case RT305X_SOC_RT3350:
++		*idx = 1;
++		return "ralink,rt3350-sysc";
++	case RT305X_SOC_RT3352:
++		*idx = 1;
++		return "ralink,rt3352-sysc";
++	case RT305X_SOC_RT5350:
++		*idx = 1;
++		return "ralink,rt5350-sysc";
++	case MT762X_SOC_MT7620A:
++		*idx = 2;
++		return "ralink,mt7620-sysc";
++	case MT762X_SOC_MT7620N:
++		*idx = 2;
++		return "ralink,mt7620-sysc";
++	case MT762X_SOC_MT7628AN:
++		*idx = 1;
++		return "ralink,mt7628-sysc";
++	case MT762X_SOC_MT7688:
++		*idx = 1;
++		return "ralink,mt7688-sysc";
++	default:
++		*idx = -1;
++		return "invalid";
++	}
+ }
+ 
+ void __init plat_time_init(void)
+ {
++	struct of_phandle_args clkspec;
++	const char *compatible;
+ 	struct clk *clk;
++	int cpu_clk_idx;
+ 
+ 	ralink_of_remap();
+ 
+-	ralink_clk_init();
+-	clk = clk_get_sys("cpu", NULL);
++	compatible = clk_cpu(&cpu_clk_idx);
++	if (cpu_clk_idx == -1)
++		panic("unable to get CPU clock index");
++
++	of_clk_init(NULL);
++	clkspec.np = of_find_compatible_node(NULL, NULL, compatible);
++	clkspec.args_count = 1;
++	clkspec.args[0] = cpu_clk_idx;
++	clk = of_clk_get_from_provider(&clkspec);
+ 	if (IS_ERR(clk))
+ 		panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
+ 	pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000);
diff --git a/target/linux/ramips/patches-6.1/005-v6.5-09-MAINTAINERS-add-Mediatek-MTMIPS-Clock-maintainer.patch b/target/linux/ramips/patches-6.1/005-v6.5-09-MAINTAINERS-add-Mediatek-MTMIPS-Clock-maintainer.patch
new file mode 100644
index 00000000000000..361dc81df749a1
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/005-v6.5-09-MAINTAINERS-add-Mediatek-MTMIPS-Clock-maintainer.patch
@@ -0,0 +1,28 @@
+From fc15a7193a4d37d79e873fa06cc423180ddd2ddf Mon Sep 17 00:00:00 2001
+From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Date: Mon, 19 Jun 2023 06:09:41 +0200
+Subject: [PATCH 9/9] MAINTAINERS: add Mediatek MTMIPS Clock maintainer
+
+Adding myself as maintainer for Mediatek MTMIPS clock driver.
+
+Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+---
+ MAINTAINERS | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -13014,6 +13014,12 @@ S:	Maintained
+ F:	Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml
+ F:	drivers/clk/ralink/clk-mt7621.c
+ 
++MEDIATEK MTMIPS CLOCK DRIVER
++M:	Sergio Paracuellos <sergio.paracuellos@gmail.com>
++S:	Maintained
++F:	Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml
++F:	drivers/clk/ralink/clk-mtmips.c
++
+ MEDIATEK MT7621/28/88 I2C DRIVER
+ M:	Stefan Roese <sr@denx.de>
+ L:	linux-i2c@vger.kernel.org
diff --git a/target/linux/ramips/patches-6.1/006-v6.5-mips-ralink-introduce-commonly-used-remap-node-funct.patch b/target/linux/ramips/patches-6.1/006-v6.5-mips-ralink-introduce-commonly-used-remap-node-funct.patch
new file mode 100644
index 00000000000000..f5c148101f0051
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/006-v6.5-mips-ralink-introduce-commonly-used-remap-node-funct.patch
@@ -0,0 +1,191 @@
+From fd99ac5055d4705e91c73d1adba18bc71c8511a8 Mon Sep 17 00:00:00 2001
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Tue, 20 Jun 2023 19:44:32 +0800
+Subject: [PATCH] mips: ralink: introduce commonly used remap node function
+
+The ralink_of_remap() function is repeated several times on SoC specific
+source files. They have the same structure, but just differ in compatible
+strings. In order to make commonly use of these codes, this patch
+introduces a newly designed mtmips_of_remap_node() function to match and
+remap all supported system controller and memory controller nodes.
+
+Build and run tested on MT7620 and MT7628.
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+Reviewed-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+---
+ arch/mips/ralink/common.h |  2 --
+ arch/mips/ralink/mt7620.c |  9 ---------
+ arch/mips/ralink/mt7621.c |  9 ---------
+ arch/mips/ralink/of.c     | 42 +++++++++++++++++++++++++++++++++++-------
+ arch/mips/ralink/rt288x.c |  9 ---------
+ arch/mips/ralink/rt305x.c |  9 ---------
+ arch/mips/ralink/rt3883.c |  9 ---------
+ 7 files changed, 35 insertions(+), 54 deletions(-)
+
+--- a/arch/mips/ralink/common.h
++++ b/arch/mips/ralink/common.h
+@@ -25,6 +25,4 @@ extern void ralink_of_remap(void);
+ 
+ extern void __init prom_soc_init(struct ralink_soc_info *soc_info);
+ 
+-__iomem void *plat_of_remap_node(const char *node);
+-
+ #endif /* _RALINK_COMMON_H__ */
+--- a/arch/mips/ralink/mt7620.c
++++ b/arch/mips/ralink/mt7620.c
+@@ -43,15 +43,6 @@
+ /* does the board have sdram or ddram */
+ static int dram_type;
+ 
+-void __init ralink_of_remap(void)
+-{
+-	rt_sysc_membase = plat_of_remap_node("ralink,mt7620a-sysc");
+-	rt_memc_membase = plat_of_remap_node("ralink,mt7620a-memc");
+-
+-	if (!rt_sysc_membase || !rt_memc_membase)
+-		panic("Failed to remap core resources");
+-}
+-
+ static __init void
+ mt7620_dram_init(struct ralink_soc_info *soc_info)
+ {
+--- a/arch/mips/ralink/mt7621.c
++++ b/arch/mips/ralink/mt7621.c
+@@ -89,15 +89,6 @@ static void __init mt7621_memory_detect(
+ 	memblock_add(MT7621_HIGHMEM_BASE, MT7621_HIGHMEM_SIZE);
+ }
+ 
+-void __init ralink_of_remap(void)
+-{
+-	rt_sysc_membase = plat_of_remap_node("mediatek,mt7621-sysc");
+-	rt_memc_membase = plat_of_remap_node("mediatek,mt7621-memc");
+-
+-	if (!rt_sysc_membase || !rt_memc_membase)
+-		panic("Failed to remap core resources");
+-}
+-
+ static unsigned int __init mt7621_get_soc_name0(void)
+ {
+ 	return __raw_readl(MT7621_SYSC_BASE + SYSC_REG_CHIP_NAME0);
+--- a/arch/mips/ralink/of.c
++++ b/arch/mips/ralink/of.c
+@@ -29,28 +29,56 @@ __iomem void *rt_sysc_membase;
+ __iomem void *rt_memc_membase;
+ EXPORT_SYMBOL_GPL(rt_sysc_membase);
+ 
+-__iomem void *plat_of_remap_node(const char *node)
++static const struct of_device_id mtmips_memc_match[] = {
++	{ .compatible = "mediatek,mt7621-memc" },
++	{ .compatible = "ralink,mt7620a-memc" },
++	{ .compatible = "ralink,rt2880-memc" },
++	{ .compatible = "ralink,rt3050-memc" },
++	{ .compatible = "ralink,rt3883-memc" },
++	{}
++};
++
++static const struct of_device_id mtmips_sysc_match[] = {
++	{ .compatible = "mediatek,mt7621-sysc" },
++	{ .compatible = "ralink,mt7620a-sysc" },
++	{ .compatible = "ralink,rt2880-sysc" },
++	{ .compatible = "ralink,rt3050-sysc" },
++	{ .compatible = "ralink,rt3883-sysc" },
++	{}
++};
++
++static __iomem void *
++mtmips_of_remap_node(const struct of_device_id *match, const char *type)
+ {
+ 	struct resource res;
+ 	struct device_node *np;
+ 
+-	np = of_find_compatible_node(NULL, NULL, node);
++	np = of_find_matching_node(NULL, match);
+ 	if (!np)
+-		panic("Failed to find %s node", node);
++		panic("Failed to find %s controller node", type);
+ 
+ 	if (of_address_to_resource(np, 0, &res))
+-		panic("Failed to get resource for %s", node);
+-
+-	of_node_put(np);
++		panic("Failed to get resource for %s node", np->name);
+ 
+ 	if (!request_mem_region(res.start,
+ 				resource_size(&res),
+ 				res.name))
+-		panic("Failed to request resources for %s", node);
++		panic("Failed to request resources for %s node", np->name);
++
++	of_node_put(np);
+ 
+ 	return ioremap(res.start, resource_size(&res));
+ }
+ 
++void __init ralink_of_remap(void)
++{
++	rt_sysc_membase = mtmips_of_remap_node(mtmips_sysc_match, "system");
++	rt_memc_membase = mtmips_of_remap_node(mtmips_memc_match, "memory");
++
++	if (!rt_sysc_membase || !rt_memc_membase)
++		panic("Failed to remap core resources");
++}
++
+ void __init plat_mem_setup(void)
+ {
+ 	void *dtb;
+--- a/arch/mips/ralink/rt288x.c
++++ b/arch/mips/ralink/rt288x.c
+@@ -17,15 +17,6 @@
+ 
+ #include "common.h"
+ 
+-void __init ralink_of_remap(void)
+-{
+-	rt_sysc_membase = plat_of_remap_node("ralink,rt2880-sysc");
+-	rt_memc_membase = plat_of_remap_node("ralink,rt2880-memc");
+-
+-	if (!rt_sysc_membase || !rt_memc_membase)
+-		panic("Failed to remap core resources");
+-}
+-
+ void __init prom_soc_init(struct ralink_soc_info *soc_info)
+ {
+ 	void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT2880_SYSC_BASE);
+--- a/arch/mips/ralink/rt305x.c
++++ b/arch/mips/ralink/rt305x.c
+@@ -53,15 +53,6 @@ static unsigned long rt5350_get_mem_size
+ 	return ret;
+ }
+ 
+-void __init ralink_of_remap(void)
+-{
+-	rt_sysc_membase = plat_of_remap_node("ralink,rt3050-sysc");
+-	rt_memc_membase = plat_of_remap_node("ralink,rt3050-memc");
+-
+-	if (!rt_sysc_membase || !rt_memc_membase)
+-		panic("Failed to remap core resources");
+-}
+-
+ void __init prom_soc_init(struct ralink_soc_info *soc_info)
+ {
+ 	void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
+--- a/arch/mips/ralink/rt3883.c
++++ b/arch/mips/ralink/rt3883.c
+@@ -17,15 +17,6 @@
+ 
+ #include "common.h"
+ 
+-void __init ralink_of_remap(void)
+-{
+-	rt_sysc_membase = plat_of_remap_node("ralink,rt3883-sysc");
+-	rt_memc_membase = plat_of_remap_node("ralink,rt3883-memc");
+-
+-	if (!rt_sysc_membase || !rt_memc_membase)
+-		panic("Failed to remap core resources");
+-}
+-
+ void __init prom_soc_init(struct ralink_soc_info *soc_info)
+ {
+ 	void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT3883_SYSC_BASE);
diff --git a/target/linux/ramips/patches-6.1/007-v6.5-clk-ralink-mtmips-Fix-uninitialized-use-of-ret-in-mt.patch b/target/linux/ramips/patches-6.1/007-v6.5-clk-ralink-mtmips-Fix-uninitialized-use-of-ret-in-mt.patch
new file mode 100644
index 00000000000000..c0c2a6e204fcd5
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/007-v6.5-clk-ralink-mtmips-Fix-uninitialized-use-of-ret-in-mt.patch
@@ -0,0 +1,56 @@
+From 6e68dae946e3a0333fbde5487ce163142ca10ae0 Mon Sep 17 00:00:00 2001
+From: Nathan Chancellor <nathan@kernel.org>
+Date: Thu, 22 Jun 2023 15:56:19 +0000
+Subject: clk: ralink: mtmips: Fix uninitialized use of ret in
+ mtmips_register_{fixed,factor}_clocks()
+
+Clang warns:
+
+  drivers/clk/ralink/clk-mtmips.c:309:9: error: variable 'ret' is uninitialized when used here [-Werror,-Wuninitialized]
+    309 |         return ret;
+        |                ^~~
+  drivers/clk/ralink/clk-mtmips.c:285:9: note: initialize the variable 'ret' to silence this warning
+    285 |         int ret, i;
+        |                ^
+        |                 = 0
+  drivers/clk/ralink/clk-mtmips.c:359:9: error: variable 'ret' is uninitialized when used here [-Werror,-Wuninitialized]
+    359 |         return ret;
+        |                ^~~
+  drivers/clk/ralink/clk-mtmips.c:335:9: note: initialize the variable 'ret' to silence this warning
+    335 |         int ret, i;
+        |                ^
+        |                 = 0
+  2 errors generated.
+
+Set ret to the return value of clk_hw_register_fixed_rate() using the
+PTR_ERR() macro, which ensures ret is not used uninitialized, clearing
+up the warning.
+
+Fixes: 6f3b15586eef ("clk: ralink: add clock and reset driver for MTMIPS SoCs")
+Closes: https://github.com/ClangBuiltLinux/linux/issues/1879
+Signed-off-by: Nathan Chancellor <nathan@kernel.org>
+Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
+Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+---
+ drivers/clk/ralink/clk-mtmips.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/clk/ralink/clk-mtmips.c
++++ b/drivers/clk/ralink/clk-mtmips.c
+@@ -292,6 +292,7 @@ static int mtmips_register_fixed_clocks(
+ 						      sclk->parent, 0,
+ 						      sclk->rate);
+ 		if (IS_ERR(sclk->hw)) {
++			ret = PTR_ERR(sclk->hw);
+ 			pr_err("Couldn't register fixed clock %d\n", idx);
+ 			goto err_clk_unreg;
+ 		}
+@@ -342,6 +343,7 @@ static int mtmips_register_factor_clocks
+ 						  sclk->parent, sclk->flags,
+ 						  sclk->mult, sclk->div);
+ 		if (IS_ERR(sclk->hw)) {
++			ret = PTR_ERR(sclk->hw);
+ 			pr_err("Couldn't register factor clock %d\n", idx);
+ 			goto err_clk_unreg;
+ 		}
diff --git a/target/linux/ramips/patches-6.1/008-v6.5-mips-ralink-match-all-supported-system-controller-co.patch b/target/linux/ramips/patches-6.1/008-v6.5-mips-ralink-match-all-supported-system-controller-co.patch
new file mode 100644
index 00000000000000..6940a2b4b98c02
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/008-v6.5-mips-ralink-match-all-supported-system-controller-co.patch
@@ -0,0 +1,40 @@
+From 670f77f76f650b1b341d31d009cc2fb03a4d1fcf Mon Sep 17 00:00:00 2001
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Fri, 23 Jun 2023 08:17:48 +0800
+Subject: mips: ralink: match all supported system controller compatible
+ strings
+
+Recently, A new clock and reset controller driver has been introduced to
+the ralink mips target[1]. It provides proper system control and adds more
+SoC specific compatible strings. In order to better initialize CPUs, this
+patch removes the outdated "ralink,mt7620a-sysc" and add all dt-binding
+documented compatible strings to the system controller match table.
+
+[1] https://lore.kernel.org/all/20230619040941.1340372-1-sergio.paracuellos@gmail.com/
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+Reviewed-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+---
+ arch/mips/ralink/of.c | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/ralink/of.c
++++ b/arch/mips/ralink/of.c
+@@ -40,10 +40,15 @@ static const struct of_device_id mtmips_
+ 
+ static const struct of_device_id mtmips_sysc_match[] = {
+ 	{ .compatible = "mediatek,mt7621-sysc" },
+-	{ .compatible = "ralink,mt7620a-sysc" },
++	{ .compatible = "ralink,mt7620-sysc" },
++	{ .compatible = "ralink,mt7628-sysc" },
++	{ .compatible = "ralink,mt7688-sysc" },
+ 	{ .compatible = "ralink,rt2880-sysc" },
+ 	{ .compatible = "ralink,rt3050-sysc" },
++	{ .compatible = "ralink,rt3052-sysc" },
++	{ .compatible = "ralink,rt3352-sysc" },
+ 	{ .compatible = "ralink,rt3883-sysc" },
++	{ .compatible = "ralink,rt5350-sysc" },
+ 	{}
+ };
+ 
diff --git a/target/linux/ramips/patches-6.1/009-v6.3-01-watchdog-mt7621-wdt-avoid-static-global-declarations.patch b/target/linux/ramips/patches-6.1/009-v6.3-01-watchdog-mt7621-wdt-avoid-static-global-declarations.patch
new file mode 100644
index 00000000000000..e06d5621e10fd7
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/009-v6.3-01-watchdog-mt7621-wdt-avoid-static-global-declarations.patch
@@ -0,0 +1,213 @@
+From 783c7cb4659b53b5e1b809dac5e8cdf250145919 Mon Sep 17 00:00:00 2001
+From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Date: Tue, 14 Feb 2023 11:39:35 +0100
+Subject: [PATCH 1/2] watchdog: mt7621-wdt: avoid static global declarations
+
+Instead of using static global definitions in driver code, refactor code
+introducing a new watchdog driver data structure and use it along the
+code.
+
+Reviewed-by: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Link: https://lore.kernel.org/r/20230214103936.1061078-5-sergio.paracuellos@gmail.com
+[groeck: unsigned -> unsigned int]
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
+---
+ drivers/watchdog/mt7621_wdt.c | 102 +++++++++++++++++++++++++++---------------
+ 1 file changed, 65 insertions(+), 37 deletions(-)
+
+--- a/drivers/watchdog/mt7621_wdt.c
++++ b/drivers/watchdog/mt7621_wdt.c
+@@ -31,8 +31,11 @@
+ #define TMR1CTL_RESTART			BIT(9)
+ #define TMR1CTL_PRESCALE_SHIFT		16
+ 
+-static void __iomem *mt7621_wdt_base;
+-static struct reset_control *mt7621_wdt_reset;
++struct mt7621_wdt_data {
++	void __iomem *base;
++	struct reset_control *rst;
++	struct watchdog_device wdt;
++};
+ 
+ static bool nowayout = WATCHDOG_NOWAYOUT;
+ module_param(nowayout, bool, 0);
+@@ -40,27 +43,31 @@ MODULE_PARM_DESC(nowayout,
+ 		 "Watchdog cannot be stopped once started (default="
+ 		 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
+ 
+-static inline void rt_wdt_w32(unsigned reg, u32 val)
++static inline void rt_wdt_w32(void __iomem *base, unsigned int reg, u32 val)
+ {
+-	iowrite32(val, mt7621_wdt_base + reg);
++	iowrite32(val, base + reg);
+ }
+ 
+-static inline u32 rt_wdt_r32(unsigned reg)
++static inline u32 rt_wdt_r32(void __iomem *base, unsigned int reg)
+ {
+-	return ioread32(mt7621_wdt_base + reg);
++	return ioread32(base + reg);
+ }
+ 
+ static int mt7621_wdt_ping(struct watchdog_device *w)
+ {
+-	rt_wdt_w32(TIMER_REG_TMRSTAT, TMR1CTL_RESTART);
++	struct mt7621_wdt_data *drvdata = watchdog_get_drvdata(w);
++
++	rt_wdt_w32(drvdata->base, TIMER_REG_TMRSTAT, TMR1CTL_RESTART);
+ 
+ 	return 0;
+ }
+ 
+ static int mt7621_wdt_set_timeout(struct watchdog_device *w, unsigned int t)
+ {
++	struct mt7621_wdt_data *drvdata = watchdog_get_drvdata(w);
++
+ 	w->timeout = t;
+-	rt_wdt_w32(TIMER_REG_TMR1LOAD, t * 1000);
++	rt_wdt_w32(drvdata->base, TIMER_REG_TMR1LOAD, t * 1000);
+ 	mt7621_wdt_ping(w);
+ 
+ 	return 0;
+@@ -68,29 +75,31 @@ static int mt7621_wdt_set_timeout(struct
+ 
+ static int mt7621_wdt_start(struct watchdog_device *w)
+ {
++	struct mt7621_wdt_data *drvdata = watchdog_get_drvdata(w);
+ 	u32 t;
+ 
+ 	/* set the prescaler to 1ms == 1000us */
+-	rt_wdt_w32(TIMER_REG_TMR1CTL, 1000 << TMR1CTL_PRESCALE_SHIFT);
++	rt_wdt_w32(drvdata->base, TIMER_REG_TMR1CTL, 1000 << TMR1CTL_PRESCALE_SHIFT);
+ 
+ 	mt7621_wdt_set_timeout(w, w->timeout);
+ 
+-	t = rt_wdt_r32(TIMER_REG_TMR1CTL);
++	t = rt_wdt_r32(drvdata->base, TIMER_REG_TMR1CTL);
+ 	t |= TMR1CTL_ENABLE;
+-	rt_wdt_w32(TIMER_REG_TMR1CTL, t);
++	rt_wdt_w32(drvdata->base, TIMER_REG_TMR1CTL, t);
+ 
+ 	return 0;
+ }
+ 
+ static int mt7621_wdt_stop(struct watchdog_device *w)
+ {
++	struct mt7621_wdt_data *drvdata = watchdog_get_drvdata(w);
+ 	u32 t;
+ 
+ 	mt7621_wdt_ping(w);
+ 
+-	t = rt_wdt_r32(TIMER_REG_TMR1CTL);
++	t = rt_wdt_r32(drvdata->base, TIMER_REG_TMR1CTL);
+ 	t &= ~TMR1CTL_ENABLE;
+-	rt_wdt_w32(TIMER_REG_TMR1CTL, t);
++	rt_wdt_w32(drvdata->base, TIMER_REG_TMR1CTL, t);
+ 
+ 	return 0;
+ }
+@@ -105,7 +114,9 @@ static int mt7621_wdt_bootcause(void)
+ 
+ static int mt7621_wdt_is_running(struct watchdog_device *w)
+ {
+-	return !!(rt_wdt_r32(TIMER_REG_TMR1CTL) & TMR1CTL_ENABLE);
++	struct mt7621_wdt_data *drvdata = watchdog_get_drvdata(w);
++
++	return !!(rt_wdt_r32(drvdata->base, TIMER_REG_TMR1CTL) & TMR1CTL_ENABLE);
+ }
+ 
+ static const struct watchdog_info mt7621_wdt_info = {
+@@ -121,30 +132,39 @@ static const struct watchdog_ops mt7621_
+ 	.set_timeout = mt7621_wdt_set_timeout,
+ };
+ 
+-static struct watchdog_device mt7621_wdt_dev = {
+-	.info = &mt7621_wdt_info,
+-	.ops = &mt7621_wdt_ops,
+-	.min_timeout = 1,
+-	.max_timeout = 0xfffful / 1000,
+-};
+-
+ static int mt7621_wdt_probe(struct platform_device *pdev)
+ {
+ 	struct device *dev = &pdev->dev;
+-	mt7621_wdt_base = devm_platform_ioremap_resource(pdev, 0);
+-	if (IS_ERR(mt7621_wdt_base))
+-		return PTR_ERR(mt7621_wdt_base);
+-
+-	mt7621_wdt_reset = devm_reset_control_get_exclusive(dev, NULL);
+-	if (!IS_ERR(mt7621_wdt_reset))
+-		reset_control_deassert(mt7621_wdt_reset);
+-
+-	mt7621_wdt_dev.bootstatus = mt7621_wdt_bootcause();
+-
+-	watchdog_init_timeout(&mt7621_wdt_dev, mt7621_wdt_dev.max_timeout,
+-			      dev);
+-	watchdog_set_nowayout(&mt7621_wdt_dev, nowayout);
+-	if (mt7621_wdt_is_running(&mt7621_wdt_dev)) {
++	struct watchdog_device *mt7621_wdt;
++	struct mt7621_wdt_data *drvdata;
++	int err;
++
++	drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
++	if (!drvdata)
++		return -ENOMEM;
++
++	drvdata->base = devm_platform_ioremap_resource(pdev, 0);
++	if (IS_ERR(drvdata->base))
++		return PTR_ERR(drvdata->base);
++
++	drvdata->rst = devm_reset_control_get_exclusive(dev, NULL);
++	if (!IS_ERR(drvdata->rst))
++		reset_control_deassert(drvdata->rst);
++
++	mt7621_wdt = &drvdata->wdt;
++	mt7621_wdt->info = &mt7621_wdt_info;
++	mt7621_wdt->ops = &mt7621_wdt_ops;
++	mt7621_wdt->min_timeout = 1;
++	mt7621_wdt->max_timeout = 0xfffful / 1000;
++	mt7621_wdt->parent = dev;
++
++	mt7621_wdt->bootstatus = mt7621_wdt_bootcause();
++
++	watchdog_init_timeout(mt7621_wdt, mt7621_wdt->max_timeout, dev);
++	watchdog_set_nowayout(mt7621_wdt, nowayout);
++	watchdog_set_drvdata(mt7621_wdt, drvdata);
++
++	if (mt7621_wdt_is_running(mt7621_wdt)) {
+ 		/*
+ 		 * Make sure to apply timeout from watchdog core, taking
+ 		 * the prescaler of this driver here into account (the
+@@ -154,17 +174,25 @@ static int mt7621_wdt_probe(struct platf
+ 		 * we first disable the watchdog, set the new prescaler
+ 		 * and timeout, and then re-enable the watchdog.
+ 		 */
+-		mt7621_wdt_stop(&mt7621_wdt_dev);
+-		mt7621_wdt_start(&mt7621_wdt_dev);
+-		set_bit(WDOG_HW_RUNNING, &mt7621_wdt_dev.status);
++		mt7621_wdt_stop(mt7621_wdt);
++		mt7621_wdt_start(mt7621_wdt);
++		set_bit(WDOG_HW_RUNNING, &mt7621_wdt->status);
+ 	}
+ 
+-	return devm_watchdog_register_device(dev, &mt7621_wdt_dev);
++	err = devm_watchdog_register_device(dev, &drvdata->wdt);
++	if (err)
++		return err;
++
++	platform_set_drvdata(pdev, drvdata);
++
++	return 0;
+ }
+ 
+ static void mt7621_wdt_shutdown(struct platform_device *pdev)
+ {
+-	mt7621_wdt_stop(&mt7621_wdt_dev);
++	struct mt7621_wdt_data *drvdata = platform_get_drvdata(pdev);
++
++	mt7621_wdt_stop(&drvdata->wdt);
+ }
+ 
+ static const struct of_device_id mt7621_wdt_match[] = {
diff --git a/target/linux/ramips/patches-6.1/009-v6.3-02-watchdog-mt7621-wdt-avoid-ralink-architecture-depend.patch b/target/linux/ramips/patches-6.1/009-v6.3-02-watchdog-mt7621-wdt-avoid-ralink-architecture-depend.patch
new file mode 100644
index 00000000000000..7e4e45df13fe82
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/009-v6.3-02-watchdog-mt7621-wdt-avoid-ralink-architecture-depend.patch
@@ -0,0 +1,104 @@
+From ff8ec4ac39ad413b580d611dbf68e1d8a82eba56 Mon Sep 17 00:00:00 2001
+From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Date: Tue, 14 Feb 2023 11:39:36 +0100
+Subject: [PATCH 2/2] watchdog: mt7621-wdt: avoid ralink architecture dependent code
+
+MT7621 SoC has a system controller node. Watchdog need to access to reset
+status register. Ralink architecture and related driver are old and from
+the beggining they are using some architecture dependent operations for
+accessing this shared registers through 'asm/mach-ralink/ralink_regs.h'
+header file. However this is not ideal from a driver perspective which can
+just access to the system controller registers in an arch independent way
+using regmap syscon APIs. Update Kconfig accordingly to select new added
+dependencies and allow driver to be compile tested.
+
+Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Reviewed-by: Guenter Roeck <linux@roeck-us.net>
+Link: https://lore.kernel.org/r/20230214103936.1061078-6-sergio.paracuellos@gmail.com
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
+---
+ drivers/watchdog/Kconfig      |  4 +++-
+ drivers/watchdog/mt7621_wdt.c | 22 +++++++++++++++++-----
+ 2 files changed, 20 insertions(+), 6 deletions(-)
+
+--- a/drivers/watchdog/Kconfig
++++ b/drivers/watchdog/Kconfig
+@@ -1865,7 +1865,9 @@ config GXP_WATCHDOG
+ config MT7621_WDT
+ 	tristate "Mediatek SoC watchdog"
+ 	select WATCHDOG_CORE
+-	depends on SOC_MT7620 || SOC_MT7621
++	select REGMAP_MMIO
++	select MFD_SYSCON
++	depends on SOC_MT7620 || SOC_MT7621 || COMPILE_TEST
+ 	help
+ 	  Hardware driver for the Mediatek/Ralink MT7621/8 SoC Watchdog Timer.
+ 
+--- a/drivers/watchdog/mt7621_wdt.c
++++ b/drivers/watchdog/mt7621_wdt.c
+@@ -15,8 +15,8 @@
+ #include <linux/moduleparam.h>
+ #include <linux/platform_device.h>
+ #include <linux/mod_devicetable.h>
+-
+-#include <asm/mach-ralink/ralink_regs.h>
++#include <linux/mfd/syscon.h>
++#include <linux/regmap.h>
+ 
+ #define SYSC_RSTSTAT			0x38
+ #define WDT_RST_CAUSE			BIT(1)
+@@ -34,6 +34,7 @@
+ struct mt7621_wdt_data {
+ 	void __iomem *base;
+ 	struct reset_control *rst;
++	struct regmap *sysc;
+ 	struct watchdog_device wdt;
+ };
+ 
+@@ -104,9 +105,12 @@ static int mt7621_wdt_stop(struct watchd
+ 	return 0;
+ }
+ 
+-static int mt7621_wdt_bootcause(void)
++static int mt7621_wdt_bootcause(struct mt7621_wdt_data *d)
+ {
+-	if (rt_sysc_r32(SYSC_RSTSTAT) & WDT_RST_CAUSE)
++	u32 val;
++
++	regmap_read(d->sysc, SYSC_RSTSTAT, &val);
++	if (val & WDT_RST_CAUSE)
+ 		return WDIOF_CARDRESET;
+ 
+ 	return 0;
+@@ -134,6 +138,7 @@ static const struct watchdog_ops mt7621_
+ 
+ static int mt7621_wdt_probe(struct platform_device *pdev)
+ {
++	struct device_node *np = pdev->dev.of_node;
+ 	struct device *dev = &pdev->dev;
+ 	struct watchdog_device *mt7621_wdt;
+ 	struct mt7621_wdt_data *drvdata;
+@@ -143,6 +148,13 @@ static int mt7621_wdt_probe(struct platf
+ 	if (!drvdata)
+ 		return -ENOMEM;
+ 
++	drvdata->sysc = syscon_regmap_lookup_by_phandle(np, "mediatek,sysctl");
++	if (IS_ERR(drvdata->sysc)) {
++		drvdata->sysc = syscon_regmap_lookup_by_compatible("mediatek,mt7621-sysc");
++		if (IS_ERR(drvdata->sysc))
++			return PTR_ERR(drvdata->sysc);
++	}
++
+ 	drvdata->base = devm_platform_ioremap_resource(pdev, 0);
+ 	if (IS_ERR(drvdata->base))
+ 		return PTR_ERR(drvdata->base);
+@@ -158,7 +170,7 @@ static int mt7621_wdt_probe(struct platf
+ 	mt7621_wdt->max_timeout = 0xfffful / 1000;
+ 	mt7621_wdt->parent = dev;
+ 
+-	mt7621_wdt->bootstatus = mt7621_wdt_bootcause();
++	mt7621_wdt->bootstatus = mt7621_wdt_bootcause(drvdata);
+ 
+ 	watchdog_init_timeout(mt7621_wdt, mt7621_wdt->max_timeout, dev);
+ 	watchdog_set_nowayout(mt7621_wdt, nowayout);
diff --git a/target/linux/ramips/patches-6.1/010-v6.5-01-mips-pci-mt7620-do-not-print-NFTS-register-value-as-.patch b/target/linux/ramips/patches-6.1/010-v6.5-01-mips-pci-mt7620-do-not-print-NFTS-register-value-as-.patch
new file mode 100644
index 00000000000000..704e861b8211dc
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/010-v6.5-01-mips-pci-mt7620-do-not-print-NFTS-register-value-as-.patch
@@ -0,0 +1,32 @@
+From 9f9a035e6156a57d9da062b26d2a48d031744a1e Mon Sep 17 00:00:00 2001
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Tue, 20 Jun 2023 18:43:22 +0800
+Subject: [PATCH 1/2] mips: pci-mt7620: do not print NFTS register value as
+ error log
+
+These codes are used to read NFTS_TIMEOUT_DELAY register value and
+write it into kernel log after writing the register. they are only
+used for debugging during driver development, so there is no need
+to keep them now.
+
+Tested on MT7628AN router Motorola MWR03.
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+Reviewed-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+---
+ arch/mips/pci/pci-mt7620.c | 3 ---
+ 1 file changed, 3 deletions(-)
+
+--- a/arch/mips/pci/pci-mt7620.c
++++ b/arch/mips/pci/pci-mt7620.c
+@@ -274,9 +274,6 @@ static int mt7628_pci_hw_init(struct pla
+ 	val |= 0x50 << 8;
+ 	pci_config_write(NULL, 0, 0x70c, 4, val);
+ 
+-	pci_config_read(NULL, 0, 0x70c, 4, &val);
+-	dev_err(&pdev->dev, "Port 0 N_FTS = %x\n", (unsigned int) val);
+-
+ 	return 0;
+ }
+ 
diff --git a/target/linux/ramips/patches-6.1/010-v6.5-02-mips-pci-mt7620-use-dev_info-to-log-PCIe-device-dete.patch b/target/linux/ramips/patches-6.1/010-v6.5-02-mips-pci-mt7620-use-dev_info-to-log-PCIe-device-dete.patch
new file mode 100644
index 00000000000000..5898a110ea972c
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/010-v6.5-02-mips-pci-mt7620-use-dev_info-to-log-PCIe-device-dete.patch
@@ -0,0 +1,39 @@
+From 89ec9bbe60b61cc6ae3eddd6d4f43e128f8a88de Mon Sep 17 00:00:00 2001
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Tue, 20 Jun 2023 18:43:23 +0800
+Subject: [PATCH 2/2] mips: pci-mt7620: use dev_info() to log PCIe device
+ detection result
+
+Usually, We only need to print the error log when there is a PCIe card but
+initialization fails. Whether the driver finds the PCIe card or not is the
+expected behavior. So it's better to log these information with dev_info().
+
+Tested on MT7628AN router Motorola MWR03.
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+Reviewed-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+---
+ arch/mips/pci/pci-mt7620.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/mips/pci/pci-mt7620.c
++++ b/arch/mips/pci/pci-mt7620.c
+@@ -331,7 +331,7 @@ static int mt7620_pci_probe(struct platf
+ 		rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
+ 		if (ralink_soc == MT762X_SOC_MT7620A)
+ 			rt_sysc_m32(LC_CKDRVPD, PDRV_SW_SET, PPLL_DRV);
+-		dev_err(&pdev->dev, "PCIE0 no card, disable it(RST&CLK)\n");
++		dev_info(&pdev->dev, "PCIE0 no card, disable it(RST&CLK)\n");
+ 		return -1;
+ 	}
+ 
+@@ -374,7 +374,7 @@ int pcibios_map_irq(const struct pci_dev
+ 			dev->bus->number, slot);
+ 		return 0;
+ 	}
+-	dev_err(&dev->dev, "card - bus=0x%x, slot = 0x%x irq=%d\n",
++	dev_info(&dev->dev, "card - bus=0x%x, slot = 0x%x irq=%d\n",
+ 		dev->bus->number, slot, irq);
+ 
+ 	/* configure the cache line size to 0x14 */
diff --git a/target/linux/ramips/patches-6.1/110-v6.4-PCI-mt7621-Use-dev_info-to-log-PCIe-card-detection.patch b/target/linux/ramips/patches-6.1/110-v6.4-PCI-mt7621-Use-dev_info-to-log-PCIe-card-detection.patch
new file mode 100644
index 00000000000000..ad2191e6555744
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/110-v6.4-PCI-mt7621-Use-dev_info-to-log-PCIe-card-detection.patch
@@ -0,0 +1,31 @@
+From 50233e105a0332ec0f3bc83180c416e6b200471e Mon Sep 17 00:00:00 2001
+From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Date: Fri, 24 Mar 2023 08:37:33 +0100
+Subject: PCI: mt7621: Use dev_info() to log PCIe card detection
+
+When there is no card plugged on a PCIe port a log reporting that
+the port will be disabled is flagged as an error (dev_err()).
+
+Since this is not an error at all, change the log level by using
+dev_info() instead.
+
+Link: https://lore.kernel.org/r/20230324073733.1596231-1-sergio.paracuellos@gmail.com
+Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
+---
+ drivers/pci/controller/pcie-mt7621.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/pci/controller/pcie-mt7621.c
++++ b/drivers/pci/controller/pcie-mt7621.c
+@@ -378,8 +378,8 @@ static int mt7621_pcie_init_ports(struct
+ 		u32 slot = port->slot;
+ 
+ 		if (!mt7621_pcie_port_is_linkup(port)) {
+-			dev_err(dev, "pcie%d no card, disable it (RST & CLK)\n",
+-				slot);
++			dev_info(dev, "pcie%d no card, disable it (RST & CLK)\n",
++				 slot);
+ 			mt7621_control_assert(port);
+ 			port->enabled = false;
+ 			num_disabled++;
diff --git a/target/linux/ramips/patches-6.1/200-add-ralink-eth.patch b/target/linux/ramips/patches-6.1/200-add-ralink-eth.patch
new file mode 100644
index 00000000000000..cd18fe7dd40d2b
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/200-add-ralink-eth.patch
@@ -0,0 +1,20 @@
+--- a/drivers/net/ethernet/Kconfig
++++ b/drivers/net/ethernet/Kconfig
+@@ -167,6 +167,7 @@ source "drivers/net/ethernet/pensando/Kc
+ source "drivers/net/ethernet/qlogic/Kconfig"
+ source "drivers/net/ethernet/brocade/Kconfig"
+ source "drivers/net/ethernet/qualcomm/Kconfig"
++source "drivers/net/ethernet/ralink/Kconfig"
+ source "drivers/net/ethernet/rdc/Kconfig"
+ source "drivers/net/ethernet/realtek/Kconfig"
+ source "drivers/net/ethernet/renesas/Kconfig"
+--- a/drivers/net/ethernet/Makefile
++++ b/drivers/net/ethernet/Makefile
+@@ -77,6 +77,7 @@ obj-$(CONFIG_NET_VENDOR_PACKET_ENGINES)
+ obj-$(CONFIG_NET_VENDOR_PASEMI) += pasemi/
+ obj-$(CONFIG_NET_VENDOR_QLOGIC) += qlogic/
+ obj-$(CONFIG_NET_VENDOR_QUALCOMM) += qualcomm/
++obj-$(CONFIG_NET_VENDOR_RALINK) += ralink/
+ obj-$(CONFIG_NET_VENDOR_REALTEK) += realtek/
+ obj-$(CONFIG_NET_VENDOR_RENESAS) += renesas/
+ obj-$(CONFIG_NET_VENDOR_RDC) += rdc/
diff --git a/target/linux/ramips/patches-6.1/300-mt7620-export-chip-version-and-pkg.patch b/target/linux/ramips/patches-6.1/300-mt7620-export-chip-version-and-pkg.patch
new file mode 100644
index 00000000000000..4f4fe9018a1cec
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/300-mt7620-export-chip-version-and-pkg.patch
@@ -0,0 +1,19 @@
+--- a/arch/mips/include/asm/mach-ralink/mt7620.h
++++ b/arch/mips/include/asm/mach-ralink/mt7620.h
+@@ -61,4 +61,16 @@ static inline int mt7620_get_eco(void)
+ 	return rt_sysc_r32(SYSC_REG_CHIP_REV) & CHIP_REV_ECO_MASK;
+ }
+ 
++static inline int mt7620_get_chipver(void)
++{
++	return (rt_sysc_r32(SYSC_REG_CHIP_REV) >> CHIP_REV_VER_SHIFT) &
++		CHIP_REV_VER_MASK;
++}
++
++static inline int mt7620_get_pkg(void)
++{
++	return (rt_sysc_r32(SYSC_REG_CHIP_REV) >> CHIP_REV_PKG_SHIFT) &
++		CHIP_REV_PKG_MASK;
++}
++
+ #endif
diff --git a/target/linux/ramips/patches-6.1/311-MIPS-use-set_mode-to-enable-disable-the-cevt-r4k-irq.patch b/target/linux/ramips/patches-6.1/311-MIPS-use-set_mode-to-enable-disable-the-cevt-r4k-irq.patch
new file mode 100644
index 00000000000000..172cf98ad153dc
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/311-MIPS-use-set_mode-to-enable-disable-the-cevt-r4k-irq.patch
@@ -0,0 +1,100 @@
+From ce3d4a4111a5f7e6b4e74bceae5faa6ce388e8ec Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 14 Jul 2013 23:08:11 +0200
+Subject: [PATCH 05/53] MIPS: use set_mode() to enable/disable the cevt-r4k
+ irq
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ralink/Kconfig |    5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/arch/mips/ralink/Kconfig
++++ b/arch/mips/ralink/Kconfig
+@@ -1,12 +1,17 @@
+ # SPDX-License-Identifier: GPL-2.0
+ if RALINK
+ 
++config CEVT_SYSTICK_QUIRK
++	bool
++	default n
++
+ config CLKEVT_RT3352
+ 	bool
+ 	depends on SOC_RT305X || SOC_MT7620
+ 	default y
+ 	select TIMER_OF
+ 	select CLKSRC_MMIO
++	select CEVT_SYSTICK_QUIRK
+ 
+ config RALINK_ILL_ACC
+ 	bool
+--- a/arch/mips/kernel/cevt-r4k.c
++++ b/arch/mips/kernel/cevt-r4k.c
+@@ -16,6 +16,31 @@
+ #include <asm/time.h>
+ #include <asm/cevt-r4k.h>
+ 
++#ifdef CONFIG_CEVT_SYSTICK_QUIRK
++static int mips_state_oneshot(struct clock_event_device *evt)
++{
++	unsigned long flags = IRQF_PERCPU | IRQF_TIMER | IRQF_SHARED;
++	if (!cp0_timer_irq_installed) {
++		cp0_timer_irq_installed = 1;
++		if (request_irq(evt->irq, c0_compare_interrupt, flags, "timer",
++					c0_compare_interrupt))
++			pr_err("Failed to request irq %d (timer)\n", evt->irq);
++	}
++
++	return 0;
++}
++
++static int mips_state_shutdown(struct clock_event_device *evt)
++{
++	if (cp0_timer_irq_installed) {
++		cp0_timer_irq_installed = 0;
++		free_irq(evt->irq, NULL);
++	}
++
++	return 0;
++}
++#endif
++
+ static int mips_next_event(unsigned long delta,
+ 			   struct clock_event_device *evt)
+ {
+@@ -292,7 +317,9 @@ core_initcall(r4k_register_cpufreq_notif
+ 
+ int r4k_clockevent_init(void)
+ {
++#ifndef CONFIG_CEVT_SYSTICK_QUIRK
+ 	unsigned long flags = IRQF_PERCPU | IRQF_TIMER | IRQF_SHARED;
++#endif
+ 	unsigned int cpu = smp_processor_id();
+ 	struct clock_event_device *cd;
+ 	unsigned int irq, min_delta;
+@@ -322,11 +349,16 @@ int r4k_clockevent_init(void)
+ 	cd->rating		= 300;
+ 	cd->irq			= irq;
+ 	cd->cpumask		= cpumask_of(cpu);
++#ifdef CONFIG_CEVT_SYSTICK_QUIRK
++	cd->set_state_shutdown	= mips_state_shutdown;
++	cd->set_state_oneshot	= mips_state_oneshot;
++#endif
+ 	cd->set_next_event	= mips_next_event;
+ 	cd->event_handler	= mips_event_handler;
+ 
+ 	clockevents_config_and_register(cd, mips_hpt_frequency, min_delta, 0x7fffffff);
+ 
++#ifndef CONFIG_CEVT_SYSTICK_QUIRK
+ 	if (cp0_timer_irq_installed)
+ 		return 0;
+ 
+@@ -335,6 +367,7 @@ int r4k_clockevent_init(void)
+ 	if (request_irq(irq, c0_compare_interrupt, flags, "timer",
+ 			c0_compare_interrupt))
+ 		pr_err("Failed to request irq %d (timer)\n", irq);
++#endif
+ 
+ 	return 0;
+ }
diff --git a/target/linux/ramips/patches-6.1/312-MIPS-ralink-add-cpu-frequency-scaling.patch b/target/linux/ramips/patches-6.1/312-MIPS-ralink-add-cpu-frequency-scaling.patch
new file mode 100644
index 00000000000000..0d70770941ecf8
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/312-MIPS-ralink-add-cpu-frequency-scaling.patch
@@ -0,0 +1,195 @@
+From bd30f19a006fb52bac80c6463c49dd2f4159f4ac Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 28 Jul 2013 16:26:41 +0200
+Subject: [PATCH 06/53] MIPS: ralink: add cpu frequency scaling
+
+This feature will break udelay() and cause the delay loop to have longer delays
+when the frequency is scaled causing a performance hit.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ralink/cevt-rt3352.c |   38 ++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 38 insertions(+)
+
+--- a/arch/mips/ralink/cevt-rt3352.c
++++ b/arch/mips/ralink/cevt-rt3352.c
+@@ -29,6 +29,10 @@
+ /* enable the counter */
+ #define CFG_CNT_EN		0x1
+ 
++/* mt7620 frequency scaling defines */
++#define CLK_LUT_CFG	0x40
++#define SLEEP_EN	BIT(31)
++
+ struct systick_device {
+ 	void __iomem *membase;
+ 	struct clock_event_device dev;
+@@ -36,21 +40,53 @@ struct systick_device {
+ 	int freq_scale;
+ };
+ 
++static void (*systick_freq_scaling)(struct systick_device *sdev, int status);
++
+ static int systick_set_oneshot(struct clock_event_device *evt);
+ static int systick_shutdown(struct clock_event_device *evt);
+ 
++static inline void mt7620_freq_scaling(struct systick_device *sdev, int status)
++{
++	if (sdev->freq_scale == status)
++		return;
++
++	sdev->freq_scale = status;
++
++	pr_info("%s: %s autosleep mode\n", sdev->dev.name,
++			(status) ? ("enable") : ("disable"));
++	if (status)
++		rt_sysc_w32(rt_sysc_r32(CLK_LUT_CFG) | SLEEP_EN, CLK_LUT_CFG);
++	else
++		rt_sysc_w32(rt_sysc_r32(CLK_LUT_CFG) & ~SLEEP_EN, CLK_LUT_CFG);
++}
++
++static inline unsigned int read_count(struct systick_device *sdev)
++{
++	return ioread32(sdev->membase + SYSTICK_COUNT);
++}
++
++static inline unsigned int read_compare(struct systick_device *sdev)
++{
++	return ioread32(sdev->membase + SYSTICK_COMPARE);
++}
++
++static inline void write_compare(struct systick_device *sdev, unsigned int val)
++{
++	iowrite32(val, sdev->membase + SYSTICK_COMPARE);
++}
++
+ static int systick_next_event(unsigned long delta,
+ 				struct clock_event_device *evt)
+ {
+ 	struct systick_device *sdev;
+-	u32 count;
++	int res;
+ 
+ 	sdev = container_of(evt, struct systick_device, dev);
+-	count = ioread32(sdev->membase + SYSTICK_COUNT);
+-	count = (count + delta) % SYSTICK_FREQ;
+-	iowrite32(count, sdev->membase + SYSTICK_COMPARE);
++	delta += read_count(sdev);
++	write_compare(sdev, delta);
++	res = ((int)(read_count(sdev) - delta) >= 0) ? -ETIME : 0;
+ 
+-	return 0;
++	return res;
+ }
+ 
+ static void systick_event_handler(struct clock_event_device *dev)
+@@ -60,20 +96,25 @@ static void systick_event_handler(struct
+ 
+ static irqreturn_t systick_interrupt(int irq, void *dev_id)
+ {
+-	struct clock_event_device *dev = (struct clock_event_device *) dev_id;
++	int ret = 0;
++	struct clock_event_device *cdev;
++	struct systick_device *sdev;
+ 
+-	dev->event_handler(dev);
++	if (read_c0_cause() & STATUSF_IP7) {
++		cdev = (struct clock_event_device *) dev_id;
++		sdev = container_of(cdev, struct systick_device, dev);
++
++		/* Clear Count/Compare Interrupt */
++		write_compare(sdev, read_compare(sdev));
++		cdev->event_handler(cdev);
++		ret = 1;
++	}
+ 
+-	return IRQ_HANDLED;
++	return IRQ_RETVAL(ret);
+ }
+ 
+ static struct systick_device systick = {
+ 	.dev = {
+-		/*
+-		 * cevt-r4k uses 300, make sure systick
+-		 * gets used if available
+-		 */
+-		.rating			= 310,
+ 		.features		= CLOCK_EVT_FEAT_ONESHOT,
+ 		.set_next_event		= systick_next_event,
+ 		.set_state_shutdown	= systick_shutdown,
+@@ -91,7 +132,13 @@ static int systick_shutdown(struct clock
+ 	if (sdev->irq_requested)
+ 		free_irq(systick.dev.irq, &systick.dev);
+ 	sdev->irq_requested = 0;
+-	iowrite32(0, systick.membase + SYSTICK_CONFIG);
++	iowrite32(CFG_CNT_EN, systick.membase + SYSTICK_CONFIG);
++
++	if (systick_freq_scaling)
++		systick_freq_scaling(sdev, 0);
++
++	if (systick_freq_scaling)
++		systick_freq_scaling(sdev, 1);
+ 
+ 	return 0;
+ }
+@@ -116,33 +163,46 @@ static int systick_set_oneshot(struct cl
+ 	return 0;
+ }
+ 
++static const struct of_device_id systick_match[] = {
++	{ .compatible = "ralink,mt7620a-systick", .data = mt7620_freq_scaling},
++	{},
++};
++
+ static int __init ralink_systick_init(struct device_node *np)
+ {
+-	int ret;
++	const struct of_device_id *match;
++	int rating = 200;
+ 
+ 	systick.membase = of_iomap(np, 0);
+ 	if (!systick.membase)
+ 		return -ENXIO;
+ 
+-	systick.dev.name = np->name;
+-	clockevents_calc_mult_shift(&systick.dev, SYSTICK_FREQ, 60);
+-	systick.dev.max_delta_ns = clockevent_delta2ns(0x7fff, &systick.dev);
+-	systick.dev.max_delta_ticks = 0x7fff;
+-	systick.dev.min_delta_ns = clockevent_delta2ns(0x3, &systick.dev);
+-	systick.dev.min_delta_ticks = 0x3;
++	match = of_match_node(systick_match, np);
++	if (match) {
++		systick_freq_scaling = match->data;
++		/*
++		 * cevt-r4k uses 300, make sure systick
++		 * gets used if available
++		 */
++		rating = 310;
++	}
++
++	/* enable counter than register clock source */
++	iowrite32(CFG_CNT_EN, systick.membase + SYSTICK_CONFIG);
++	clocksource_mmio_init(systick.membase + SYSTICK_COUNT, np->name,
++			SYSTICK_FREQ, rating, 16, clocksource_mmio_readl_up);
++
++	/* register clock event */
+ 	systick.dev.irq = irq_of_parse_and_map(np, 0);
+ 	if (!systick.dev.irq) {
+ 		pr_err("%pOFn: request_irq failed", np);
+ 		return -EINVAL;
+ 	}
+ 
+-	ret = clocksource_mmio_init(systick.membase + SYSTICK_COUNT, np->name,
+-				    SYSTICK_FREQ, 301, 16,
+-				    clocksource_mmio_readl_up);
+-	if (ret)
+-		return ret;
+-
+-	clockevents_register_device(&systick.dev);
++	systick.dev.name = np->name;
++	systick.dev.rating = rating;
++	systick.dev.cpumask = cpumask_of(0);
++	clockevents_config_and_register(&systick.dev, SYSTICK_FREQ, 0x3, 0x7fff);
+ 
+ 	pr_info("%pOFn: running - mult: %d, shift: %d\n",
+ 			np, systick.dev.mult, systick.dev.shift);
diff --git a/target/linux/ramips/patches-6.1/314-MIPS-add-bootargs-override-property.patch b/target/linux/ramips/patches-6.1/314-MIPS-add-bootargs-override-property.patch
new file mode 100644
index 00000000000000..26a28167c637a1
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/314-MIPS-add-bootargs-override-property.patch
@@ -0,0 +1,63 @@
+From f15d27f9c90ede4b16eb37f9ae573ef81c2b6996 Mon Sep 17 00:00:00 2001
+From: David Bauer <mail@david-bauer.net>
+Date: Thu, 31 Dec 2020 18:49:12 +0100
+Subject: [PATCH] MIPS: add bootargs-override property
+
+Add support for the bootargs-override property to the chosen node
+similar to the one used on ipq806x or mpc85xx.
+
+This is necessary, as the U-Boot used on some boards, notably the
+Ubiquiti UniFi 6 Lite, overwrite the bootargs property of the chosen
+node leading to a kernel panic when loading OpenWrt.
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+---
+ arch/mips/kernel/setup.c | 30 ++++++++++++++++++++++++++++++
+ 1 file changed, 30 insertions(+)
+
+--- a/arch/mips/kernel/setup.c
++++ b/arch/mips/kernel/setup.c
+@@ -557,8 +557,28 @@ static int __init bootcmdline_scan_chose
+ 
+ #endif /* CONFIG_OF_EARLY_FLATTREE */
+ 
++static int __init bootcmdline_scan_chosen_override(unsigned long node, const char *uname,
++						   int depth, void *data)
++{
++	bool *dt_bootargs = data;
++	const char *p;
++	int l;
++
++	if (depth != 1 || !data || strcmp(uname, "chosen") != 0)
++		return 0;
++
++	p = of_get_flat_dt_prop(node, "bootargs-override", &l);
++	if (p != NULL && l > 0) {
++		strlcpy(boot_command_line, p, COMMAND_LINE_SIZE);
++		*dt_bootargs = true;
++	}
++
++	return 1;
++}
++
+ static void __init bootcmdline_init(void)
+ {
++	bool dt_bootargs_override = false;
+ 	bool dt_bootargs = false;
+ 
+ 	/*
+@@ -572,6 +592,14 @@ static void __init bootcmdline_init(void
+ 	}
+ 
+ 	/*
++	 * If bootargs-override in the chosen node is set, use this as the
++	 * command line
++	 */
++	of_scan_flat_dt(bootcmdline_scan_chosen_override, &dt_bootargs_override);
++	if (dt_bootargs_override)
++		return;
++
++	/*
+ 	 * If the user specified a built-in command line &
+ 	 * MIPS_CMDLINE_BUILTIN_EXTEND, then the built-in command line is
+ 	 * prepended to arguments from the bootloader or DT so we'll copy them
diff --git a/target/linux/ramips/patches-6.1/315-owrt-hack-fix-mt7688-cache-issue.patch b/target/linux/ramips/patches-6.1/315-owrt-hack-fix-mt7688-cache-issue.patch
new file mode 100644
index 00000000000000..c31e6d7cde28f9
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/315-owrt-hack-fix-mt7688-cache-issue.patch
@@ -0,0 +1,28 @@
+From 5ede027f6c4a57ed25da872420508b7f1168b36b Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 7 Dec 2015 17:15:32 +0100
+Subject: [PATCH 13/53] owrt: hack: fix mt7688 cache issue
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/kernel/setup.c |    2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/mips/kernel/setup.c
++++ b/arch/mips/kernel/setup.c
+@@ -699,7 +699,6 @@ static void __init arch_mem_init(char **
+ 	mips_reserve_vmcore();
+ 
+ 	mips_parse_crashkernel();
+-	device_tree_init();
+ 
+ 	/*
+ 	 * In order to reduce the possibility of kernel panic when failed to
+@@ -834,6 +833,7 @@ void __init setup_arch(char **cmdline_p)
+ 
+ 	cpu_cache_init();
+ 	paging_init();
++	device_tree_init();
+ 
+ 	memblock_dump_all();
+ 
diff --git a/target/linux/ramips/patches-6.1/316-arch-mips-do-not-select-illegal-access-driver-by-def.patch b/target/linux/ramips/patches-6.1/316-arch-mips-do-not-select-illegal-access-driver-by-def.patch
new file mode 100644
index 00000000000000..1dc54ccf232627
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/316-arch-mips-do-not-select-illegal-access-driver-by-def.patch
@@ -0,0 +1,25 @@
+From 9e6ce539092a1dd605a20bf73c655a9de58d8641 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 7 Dec 2015 17:18:05 +0100
+Subject: [PATCH 15/53] arch: mips: do not select illegal access driver by
+ default
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ralink/Kconfig |    4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/mips/ralink/Kconfig
++++ b/arch/mips/ralink/Kconfig
+@@ -14,9 +14,9 @@ config CLKEVT_RT3352
+ 	select CEVT_SYSTICK_QUIRK
+ 
+ config RALINK_ILL_ACC
+-	bool
++	bool "illegal access irq"
+ 	depends on SOC_RT305X
+-	default y
++	default n
+ 
+ config IRQ_INTC
+ 	bool
diff --git a/target/linux/ramips/patches-6.1/320-MIPS-add-support-for-buggy-MT7621S-core-detection.patch b/target/linux/ramips/patches-6.1/320-MIPS-add-support-for-buggy-MT7621S-core-detection.patch
new file mode 100644
index 00000000000000..ef54835f89c2a3
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/320-MIPS-add-support-for-buggy-MT7621S-core-detection.patch
@@ -0,0 +1,75 @@
+From 6decd1aad15f56b169217789630a0098b496de0e Mon Sep 17 00:00:00 2001
+From: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
+Date: Wed, 7 Apr 2021 13:07:38 -0700
+Subject: [PATCH] MIPS: add support for buggy MT7621S core detection
+
+Most MT7621 SoCs have 2 cores, which is detected and supported properly
+by CPS.
+
+Unfortunately, MT7621 SoC has a less common S variant with only one core.
+On MT7621S, GCR_CONFIG still reports 2 cores, which leads to hangs when
+starting SMP. CPULAUNCH registers can be used in that case to detect the
+absence of the second core and override the GCR_CONFIG PCORES field.
+
+Rework a long-standing OpenWrt patch to override the value of
+mips_cps_numcores on single-core MT7621 systems.
+
+Tested on a dual-core MT7621 device (Ubiquiti ER-X) and a single-core
+MT7621 device (Netgear R6220).
+
+Original 4.14 OpenWrt patch:
+Link: https://git.openwrt.org/?p=openwrt/openwrt.git;a=commitdiff;h=4cdbc90a376dd0555201c1434a2081e055e9ceb7
+Current 5.10 OpenWrt patch:
+Link: https://git.openwrt.org/?p=openwrt/openwrt.git;a=blob;f=target/linux/ramips/patches-5.10/320-mt7621-core-detect-hack.patch;h=c63f0f4c1ec742e24d8480e80553863744b58f6a;hb=10267e17299806f9885d086147878f6c492cb904
+
+Suggested-by: Felix Fietkau <nbd@nbd.name>
+Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
+Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+---
+ arch/mips/include/asm/mips-cps.h | 23 ++++++++++++++++++++++-
+ 1 file changed, 22 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/include/asm/mips-cps.h
++++ b/arch/mips/include/asm/mips-cps.h
+@@ -11,6 +11,8 @@
+ #include <linux/io.h>
+ #include <linux/types.h>
+ 
++#include <asm/mips-boards/launch.h>
++
+ extern unsigned long __cps_access_bad_size(void)
+ 	__compiletime_error("Bad size for CPS accessor");
+ 
+@@ -162,12 +164,31 @@ static inline uint64_t mips_cps_cluster_
+  */
+ static inline unsigned int mips_cps_numcores(unsigned int cluster)
+ {
++	unsigned int ncores;
++
+ 	if (!mips_cm_present())
+ 		return 0;
+ 
+ 	/* Add one before masking to handle 0xff indicating no cores */
+-	return FIELD_GET(CM_GCR_CONFIG_PCORES,
++	ncores = FIELD_GET(CM_GCR_CONFIG_PCORES,
+ 			 mips_cps_cluster_config(cluster) + 1);
++
++	if (IS_ENABLED(CONFIG_SOC_MT7621)) {
++		struct cpulaunch *launch;
++
++		/*
++		 * Ralink MT7621S SoC is single core, but the GCR_CONFIG method
++		 * always reports 2 cores. Check the second core's LAUNCH_FREADY
++		 * flag to detect if the second core is missing. This method
++		 * only works before the core has been started.
++		 */
++		launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
++		launch += 2; /* MT7621 has 2 VPEs per core */
++		if (!(launch->flags & LAUNCH_FREADY))
++			ncores = 1;
++	}
++
++	return ncores;
+ }
+ 
+ /**
diff --git a/target/linux/ramips/patches-6.1/324-mt7621-perfctr-fix.patch b/target/linux/ramips/patches-6.1/324-mt7621-perfctr-fix.patch
new file mode 100644
index 00000000000000..dfeac7eb993dcd
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/324-mt7621-perfctr-fix.patch
@@ -0,0 +1,15 @@
+--- a/arch/mips/ralink/irq-gic.c
++++ b/arch/mips/ralink/irq-gic.c
+@@ -13,6 +13,12 @@
+ 
+ int get_c0_perfcount_int(void)
+ {
++	/*
++	 * Performance counter events are routed through GIC.
++	 * Prevent them from firing on CPU IRQ7 as well
++	 */
++	clear_c0_status(IE_SW0 << 7);
++
+ 	return gic_get_c0_perfcount_int();
+ }
+ EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
diff --git a/target/linux/ramips/patches-6.1/400-mtd-cfi-cmdset-0002-force-word-write.patch b/target/linux/ramips/patches-6.1/400-mtd-cfi-cmdset-0002-force-word-write.patch
new file mode 100644
index 00000000000000..7011bbe50b2d4a
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/400-mtd-cfi-cmdset-0002-force-word-write.patch
@@ -0,0 +1,20 @@
+From ee9081b2726a5ca8cde5497afdc5425e21ff8f8b Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 15 Jul 2013 00:39:21 +0200
+Subject: [PATCH 37/53] mtd: cfi cmdset 0002 force word write
+
+---
+ drivers/mtd/chips/cfi_cmdset_0002.c |    9 +++++++--
+ 1 file changed, 7 insertions(+), 2 deletions(-)
+
+--- a/drivers/mtd/chips/cfi_cmdset_0002.c
++++ b/drivers/mtd/chips/cfi_cmdset_0002.c
+@@ -40,7 +40,7 @@
+ #include <linux/mtd/xip.h>
+ 
+ #define AMD_BOOTLOC_BUG
+-#define FORCE_WORD_WRITE 0
++#define FORCE_WORD_WRITE 1
+ 
+ #define MAX_RETRIES 3
+ 
diff --git a/target/linux/ramips/patches-6.1/405-mtd-spi-nor-Add-support-for-BoHong-bh25q128as.patch b/target/linux/ramips/patches-6.1/405-mtd-spi-nor-Add-support-for-BoHong-bh25q128as.patch
new file mode 100644
index 00000000000000..3b88f786028842
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/405-mtd-spi-nor-Add-support-for-BoHong-bh25q128as.patch
@@ -0,0 +1,75 @@
+From 52d14545d2fc276b1bf9ccf48d4612fab6edfb6a Mon Sep 17 00:00:00 2001
+From: David Bauer <mail@david-bauer.net>
+Date: Thu, 6 May 2021 17:49:55 +0200
+Subject: [PATCH] mtd: spi-nor: Add support for BoHong bh25q128as
+
+Add MTD support for the BoHong bh25q128as SPI NOR chip.
+The chip has 16MB of total capacity, divided into a total of 256
+sectors, each 64KB sized. The chip also supports 4KB sectors.
+Additionally, it supports dual and quad read modes.
+
+Functionality was verified on an Tenbay WR1800K / MTK MT7621 board.
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+---
+ drivers/mtd/spi-nor/Makefile |  1 +
+ drivers/mtd/spi-nor/bohong.c | 21 +++++++++++++++++++++
+ drivers/mtd/spi-nor/core.c   |  1 +
+ drivers/mtd/spi-nor/core.h   |  1 +
+ 4 files changed, 24 insertions(+)
+ create mode 100644 drivers/mtd/spi-nor/bohong.c
+
+--- a/drivers/mtd/spi-nor/Makefile
++++ b/drivers/mtd/spi-nor/Makefile
+@@ -2,6 +2,7 @@
+ 
+ spi-nor-objs			:= core.o sfdp.o swp.o otp.o sysfs.o
+ spi-nor-objs			+= atmel.o
++spi-nor-objs			+= bohong.o
+ spi-nor-objs			+= catalyst.o
+ spi-nor-objs			+= eon.o
+ spi-nor-objs			+= esmt.o
+--- /dev/null
++++ b/drivers/mtd/spi-nor/bohong.c
+@@ -0,0 +1,21 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) 2005, Intec Automation Inc.
++ * Copyright (C) 2014, Freescale Semiconductor, Inc.
++ */
++
++#include <linux/mtd/spi-nor.h>
++
++#include "core.h"
++
++static const struct flash_info bohong_parts[] = {
++	/* BoHong Microelectronics */
++	{ "bh25q128as", INFO(0x684018, 0, 64 * 1024, 256)
++		NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
++};
++
++const struct spi_nor_manufacturer spi_nor_bohong = {
++	.name = "bohong",
++	.parts = bohong_parts,
++	.nparts = ARRAY_SIZE(bohong_parts),
++};
+--- a/drivers/mtd/spi-nor/core.c
++++ b/drivers/mtd/spi-nor/core.c
+@@ -1620,6 +1620,7 @@ int spi_nor_sr2_bit7_quad_enable(struct
+ 
+ static const struct spi_nor_manufacturer *manufacturers[] = {
+ 	&spi_nor_atmel,
++	&spi_nor_bohong,
+ 	&spi_nor_catalyst,
+ 	&spi_nor_eon,
+ 	&spi_nor_esmt,
+--- a/drivers/mtd/spi-nor/core.h
++++ b/drivers/mtd/spi-nor/core.h
+@@ -617,6 +617,7 @@ struct sfdp {
+ 
+ /* Manufacturer drivers. */
+ extern const struct spi_nor_manufacturer spi_nor_atmel;
++extern const struct spi_nor_manufacturer spi_nor_bohong;
+ extern const struct spi_nor_manufacturer spi_nor_catalyst;
+ extern const struct spi_nor_manufacturer spi_nor_eon;
+ extern const struct spi_nor_manufacturer spi_nor_esmt;
diff --git a/target/linux/ramips/patches-6.1/410-mtd-rawnand-add-driver-support-for-MT7621-nand-flash.patch b/target/linux/ramips/patches-6.1/410-mtd-rawnand-add-driver-support-for-MT7621-nand-flash.patch
new file mode 100644
index 00000000000000..438cc1ea8fe830
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/410-mtd-rawnand-add-driver-support-for-MT7621-nand-flash.patch
@@ -0,0 +1,47 @@
+From e84e2430ee0e483842b4ff013ae8a6e7e2fa2734 Mon Sep 17 00:00:00 2001
+From: Weijie Gao <weijie.gao@mediatek.com>
+Date: Wed, 1 Apr 2020 02:07:58 +0800
+Subject: [PATCH 1/2] mtd: rawnand: add driver support for MT7621 nand
+ flash controller
+
+This patch adds NAND flash controller driver for MediaTek MT7621 SoC.
+
+The NAND flash controller is similar with controllers described in
+mtk_nand.c, except that the controller from MT7621 doesn't support DMA
+transmission, and some registers' offset and fields are different.
+
+Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+---
+ drivers/mtd/nand/raw/Kconfig       |    8 +
+ drivers/mtd/nand/raw/Makefile      |    1 +
+ drivers/mtd/nand/raw/mt7621_nand.c | 1348 ++++++++++++++++++++++++++++++++++++
+ 3 files changed, 1357 insertions(+)
+ create mode 100644 drivers/mtd/nand/raw/mt7621_nand.c
+
+--- a/drivers/mtd/nand/raw/Kconfig
++++ b/drivers/mtd/nand/raw/Kconfig
+@@ -352,6 +352,14 @@ config MTD_NAND_QCOM
+ 	  Enables support for NAND flash chips on SoCs containing the EBI2 NAND
+ 	  controller. This controller is found on IPQ806x SoC.
+ 
++config MTD_NAND_MT7621
++	tristate "MT7621 NAND controller"
++	depends on SOC_MT7621 || COMPILE_TEST
++	depends on HAS_IOMEM
++	help
++	  Enables support for NAND controller on MT7621 SoC.
++	  This driver uses PIO mode for data transmission instead of DMA mode.
++
+ config MTD_NAND_MTK
+ 	tristate "MTK NAND controller"
+ 	depends on MTD_NAND_ECC_MEDIATEK
+--- a/drivers/mtd/nand/raw/Makefile
++++ b/drivers/mtd/nand/raw/Makefile
+@@ -48,6 +48,7 @@ obj-$(CONFIG_MTD_NAND_SUNXI)		+= sunxi_n
+ obj-$(CONFIG_MTD_NAND_HISI504)	        += hisi504_nand.o
+ obj-$(CONFIG_MTD_NAND_BRCMNAND)		+= brcmnand/
+ obj-$(CONFIG_MTD_NAND_QCOM)		+= qcom_nandc.o
++obj-$(CONFIG_MTD_NAND_MT7621)		+= mt7621_nand.o
+ obj-$(CONFIG_MTD_NAND_MTK)		+= mtk_nand.o
+ obj-$(CONFIG_MTD_NAND_MXIC)		+= mxic_nand.o
+ obj-$(CONFIG_MTD_NAND_TEGRA)		+= tegra_nand.o
diff --git a/target/linux/ramips/patches-6.1/411-dt-bindings-add-documentation-for-mt7621-nand-driver.patch b/target/linux/ramips/patches-6.1/411-dt-bindings-add-documentation-for-mt7621-nand-driver.patch
new file mode 100644
index 00000000000000..3d122c10c04314
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/411-dt-bindings-add-documentation-for-mt7621-nand-driver.patch
@@ -0,0 +1,85 @@
+From 3d5f4da8296b23eb3abf8b13122b0d06a215e79c Mon Sep 17 00:00:00 2001
+From: Weijie Gao <weijie.gao@mediatek.com>
+Date: Wed, 1 Apr 2020 02:07:59 +0800
+Subject: [PATCH 2/2] dt-bindings: add documentation for mt7621-nand driver
+
+This patch adds documentation for MediaTek MT7621 NAND flash controller
+driver.
+
+Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+---
+ .../bindings/mtd/mediatek,mt7621-nfc.yaml          | 68 ++++++++++++++++++++++
+ 1 file changed, 68 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/mtd/mediatek,mt7621-nfc.yaml
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/mtd/mediatek,mt7621-nfc.yaml
+@@ -0,0 +1,68 @@
++# SPDX-License-Identifier: GPL-2.0
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/mtd/mediatek,mt7621-nfc.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: MediaTek MT7621 SoC NAND Flash Controller (NFC) DT binding
++
++maintainers:
++  - Weijie Gao <weijie.gao@mediatek.com>
++
++description: |
++  This driver uses a single node to describe both NAND Flash controller
++  interface (NFI) and ECC engine for MT7621 SoC.
++  MT7621 supports only one chip select.
++
++properties:
++  "#address-cells": false
++  "#size-cells": false
++
++  compatible:
++    enum:
++      - mediatek,mt7621-nfc
++
++  reg:
++    items:
++      - description: Register base of NFI core
++      - description: Register base of ECC engine
++
++  reg-names:
++    items:
++      - const: nfi
++      - const: ecc
++
++  clocks:
++    items:
++      - description: Source clock for NFI core, fixed 125MHz
++
++  clock-names:
++    items:
++      - const: nfi_clk
++
++required:
++  - compatible
++  - reg
++  - reg-names
++  - clocks
++  - clock-names
++
++examples:
++  - |
++    nficlock: nficlock {
++    	#clock-cells = <0>;
++    	compatible = "fixed-clock";
++
++    	clock-frequency = <125000000>;
++    };
++
++    nand@1e003000 {
++    	compatible = "mediatek,mt7621-nfc";
++
++    	reg = <0x1e003000 0x800
++    	       0x1e003800 0x800>;
++    	reg-names = "nfi", "ecc";
++
++    	clocks = <&nficlock>;
++    	clock-names = "nfi_clk";
++    };
diff --git a/target/linux/ramips/patches-6.1/700-net-ethernet-mediatek-support-net-labels.patch b/target/linux/ramips/patches-6.1/700-net-ethernet-mediatek-support-net-labels.patch
new file mode 100644
index 00000000000000..a6e2aa04ca3053
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/700-net-ethernet-mediatek-support-net-labels.patch
@@ -0,0 +1,34 @@
+From bd0f89de5476ca25e73fae829ba3e1dafae1d90d Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ren=C3=A9=20van=20Dorst?= <opensource@vdorst.com>
+Date: Fri, 21 Jun 2019 10:04:05 +0200
+Subject: [PATCH] net: ethernet: mediatek: support net-labels
+
+With this patch, device name can be set within dts file in the same way as dsa
+port can.
+Add: label = "wan"; to GMAC node.
+
+Signed-off-by: René van Dorst <opensource@vdorst.com>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -4643,6 +4643,7 @@ static const struct net_device_ops mtk_n
+ 
+ static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
+ {
++	const char *name = of_get_property(np, "label", NULL);
+ 	const __be32 *_id = of_get_property(np, "reg", NULL);
+ 	struct device_node *pcs_np;
+ 	phy_interface_t phy_mode;
+@@ -4840,6 +4841,9 @@ static int mtk_add_mac(struct mtk_eth *e
+ 		register_netdevice_notifier(&mac->device_notifier);
+ 	}
+ 
++	if (name)
++		strlcpy(eth->netdev[id]->name, name, IFNAMSIZ);
++
+ 	return 0;
+ 
+ free_netdev:
diff --git a/target/linux/ramips/patches-6.1/720-Revert-net-phy-simplify-phy_link_change-arguments.patch b/target/linux/ramips/patches-6.1/720-Revert-net-phy-simplify-phy_link_change-arguments.patch
new file mode 100644
index 00000000000000..91159f2c6347de
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/720-Revert-net-phy-simplify-phy_link_change-arguments.patch
@@ -0,0 +1,118 @@
+From ffbb1b37a3e1ce1a5c574a6bd4f5aede8bc468ac Mon Sep 17 00:00:00 2001
+From: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
+Date: Sat, 27 Feb 2021 20:20:07 -0800
+Subject: [PATCH] Revert "net: phy: simplify phy_link_change arguments"
+
+This reverts commit a307593a644443db12888f45eed0dafb5869e2cc.
+
+This brings back the do_carrier flags used by the (hacky) next patch,
+still required by target/linux/ramips/files/drivers/net/ethernet/ralink/mdio.c
+---
+ drivers/net/phy/phy.c        | 12 ++++++------
+ drivers/net/phy/phy_device.c | 12 +++++++-----
+ drivers/net/phy/phylink.c    |  3 ++-
+ include/linux/phy.h          |  2 +-
+ 4 files changed, 16 insertions(+), 13 deletions(-)
+
+--- a/drivers/net/phy/phy.c
++++ b/drivers/net/phy/phy.c
+@@ -71,13 +71,13 @@ static void phy_process_state_change(str
+ 
+ static void phy_link_up(struct phy_device *phydev)
+ {
+-	phydev->phy_link_change(phydev, true);
++	phydev->phy_link_change(phydev, true, true);
+ 	phy_led_trigger_change_speed(phydev);
+ }
+ 
+-static void phy_link_down(struct phy_device *phydev)
++static void phy_link_down(struct phy_device *phydev, bool do_carrier)
+ {
+-	phydev->phy_link_change(phydev, false);
++	phydev->phy_link_change(phydev, false, do_carrier);
+ 	phy_led_trigger_change_speed(phydev);
+ }
+ 
+@@ -595,7 +595,7 @@ int phy_start_cable_test(struct phy_devi
+ 		goto out;
+ 
+ 	/* Mark the carrier down until the test is complete */
+-	phy_link_down(phydev);
++	phy_link_down(phydev, true);
+ 
+ 	netif_testing_on(dev);
+ 	err = phydev->drv->cable_test_start(phydev);
+@@ -666,7 +666,7 @@ int phy_start_cable_test_tdr(struct phy_
+ 		goto out;
+ 
+ 	/* Mark the carrier down until the test is complete */
+-	phy_link_down(phydev);
++	phy_link_down(phydev, true);
+ 
+ 	netif_testing_on(dev);
+ 	err = phydev->drv->cable_test_tdr_start(phydev, config);
+@@ -738,7 +738,7 @@ static int phy_check_link_status(struct
+ 		phy_link_up(phydev);
+ 	} else if (!phydev->link && phydev->state != PHY_NOLINK) {
+ 		phydev->state = PHY_NOLINK;
+-		phy_link_down(phydev);
++		phy_link_down(phydev, true);
+ 	}
+ 
+ 	return 0;
+@@ -1224,7 +1224,7 @@ void phy_state_machine(struct work_struc
+ 	case PHY_HALTED:
+ 		if (phydev->link) {
+ 			phydev->link = 0;
+-			phy_link_down(phydev);
++			phy_link_down(phydev, true);
+ 		}
+ 		do_suspend = true;
+ 		break;
+--- a/drivers/net/phy/phy_device.c
++++ b/drivers/net/phy/phy_device.c
+@@ -1037,14 +1037,16 @@ struct phy_device *phy_find_first(struct
+ }
+ EXPORT_SYMBOL(phy_find_first);
+ 
+-static void phy_link_change(struct phy_device *phydev, bool up)
++static void phy_link_change(struct phy_device *phydev, bool up, bool do_carrier)
+ {
+ 	struct net_device *netdev = phydev->attached_dev;
+ 
+-	if (up)
+-		netif_carrier_on(netdev);
+-	else
+-		netif_carrier_off(netdev);
++	if (do_carrier) {
++		if (up)
++			netif_carrier_on(netdev);
++		else
++			netif_carrier_off(netdev);
++	}
+ 	phydev->adjust_link(netdev);
+ 	if (phydev->mii_ts && phydev->mii_ts->link_state)
+ 		phydev->mii_ts->link_state(phydev->mii_ts, phydev);
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -1687,7 +1687,8 @@ bool phylink_expects_phy(struct phylink
+ }
+ EXPORT_SYMBOL_GPL(phylink_expects_phy);
+ 
+-static void phylink_phy_change(struct phy_device *phydev, bool up)
++static void phylink_phy_change(struct phy_device *phydev, bool up,
++			       bool do_carrier)
+ {
+ 	struct phylink *pl = phydev->phylink;
+ 	bool tx_pause, rx_pause;
+--- a/include/linux/phy.h
++++ b/include/linux/phy.h
+@@ -739,7 +739,7 @@ struct phy_device {
+ 
+ 	int pma_extable;
+ 
+-	void (*phy_link_change)(struct phy_device *phydev, bool up);
++	void (*phy_link_change)(struct phy_device *, bool up, bool do_carrier);
+ 	void (*adjust_link)(struct net_device *dev);
+ 
+ #if IS_ENABLED(CONFIG_MACSEC)
diff --git a/target/linux/ramips/patches-6.1/721-NET-no-auto-carrier-off-support.patch b/target/linux/ramips/patches-6.1/721-NET-no-auto-carrier-off-support.patch
new file mode 100644
index 00000000000000..2594c66048fe2e
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/721-NET-no-auto-carrier-off-support.patch
@@ -0,0 +1,47 @@
+From 0b6eb1e68290243d439ee330ea8d0b239a5aec69 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 27 Jul 2014 09:38:50 +0100
+Subject: [PATCH 34/53] NET: multi phy support
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/net/phy/phy.c |    9 ++++++---
+ include/linux/phy.h   |    1 +
+ 2 files changed, 7 insertions(+), 3 deletions(-)
+
+--- a/drivers/net/phy/phy.c
++++ b/drivers/net/phy/phy.c
+@@ -738,7 +738,10 @@ static int phy_check_link_status(struct
+ 		phy_link_up(phydev);
+ 	} else if (!phydev->link && phydev->state != PHY_NOLINK) {
+ 		phydev->state = PHY_NOLINK;
+-		phy_link_down(phydev, true);
++		if (!phydev->no_auto_carrier_off)
++			phy_link_down(phydev, true);
++		else
++			phy_link_down(phydev, false);
+ 	}
+ 
+ 	return 0;
+@@ -1224,7 +1227,10 @@ void phy_state_machine(struct work_struc
+ 	case PHY_HALTED:
+ 		if (phydev->link) {
+ 			phydev->link = 0;
+-			phy_link_down(phydev, true);
++			if (!phydev->no_auto_carrier_off)
++				phy_link_down(phydev, true);
++			else
++				phy_link_down(phydev, false);
+ 		}
+ 		do_suspend = true;
+ 		break;
+--- a/include/linux/phy.h
++++ b/include/linux/phy.h
+@@ -647,6 +647,7 @@ struct phy_device {
+ 	unsigned downshifted_rate:1;
+ 	unsigned is_on_sfp_module:1;
+ 	unsigned mac_managed_pm:1;
++	unsigned no_auto_carrier_off:1;
+ 
+ 	unsigned autoneg:1;
+ 	/* The most recently read link state */
diff --git a/target/linux/ramips/patches-6.1/800-dmaengine-mediatek-add-HSDMA-support-for-mt7621.patch b/target/linux/ramips/patches-6.1/800-dmaengine-mediatek-add-HSDMA-support-for-mt7621.patch
new file mode 100644
index 00000000000000..a793011223b8c7
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/800-dmaengine-mediatek-add-HSDMA-support-for-mt7621.patch
@@ -0,0 +1,37 @@
+From d94fc5ce1dc395747c3934ecffcdec0396583755 Mon Sep 17 00:00:00 2001
+From: Nick Hainke <vincent@systemli.org>
+Date: Fri, 26 May 2023 19:46:33 +0200
+Subject: [PATCH] dmaengine: mediatek: add HSDMA support for mt7621
+
+Commit 87dd67f496f7 ("staging: mt7621-dma: remove driver from tree")
+removed the mt7621-dma driver. Move the driver from staging to the
+folder "drivers/dma/mediatek" containing already other mediatek dma
+driver implementations and maintain it downstream in OpenWrt.
+
+This patch will not be sent to upstream linux. It is just a workaround.
+
+Signed-off-by: Nick Hainke <vincent@systemli.org>
+---
+ drivers/dma/mediatek/Kconfig  | 6 ++++++
+ drivers/dma/mediatek/Makefile | 1 +
+ 2 files changed, 7 insertions(+)
+
+--- a/drivers/dma/mediatek/Kconfig
++++ b/drivers/dma/mediatek/Kconfig
+@@ -36,3 +36,9 @@ config MTK_UART_APDMA
+ 	  When SERIAL_8250_MT6577 is enabled, and if you want to use DMA,
+ 	  you can enable the config. The DMA engine can only be used
+ 	  with MediaTek SoCs.
++
++config MTK_HSDMA
++	tristate "MTK HSDMA support"
++	depends on RALINK && SOC_MT7621
++	select DMA_ENGINE
++	select DMA_VIRTUAL_CHANNELS
+--- a/drivers/dma/mediatek/Makefile
++++ b/drivers/dma/mediatek/Makefile
+@@ -2,3 +2,4 @@
+ obj-$(CONFIG_MTK_UART_APDMA) += mtk-uart-apdma.o
+ obj-$(CONFIG_MTK_HSDMA) += mtk-hsdma.o
+ obj-$(CONFIG_MTK_CQDMA) += mtk-cqdma.o
++obj-$(CONFIG_MTK_HSDMA) += hsdma-mt7621.o
diff --git a/target/linux/ramips/patches-6.1/801-DT-Add-documentation-for-gpio-ralink.patch b/target/linux/ramips/patches-6.1/801-DT-Add-documentation-for-gpio-ralink.patch
new file mode 100644
index 00000000000000..93dabf877626d0
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/801-DT-Add-documentation-for-gpio-ralink.patch
@@ -0,0 +1,59 @@
+From d410e5478c622c01fcf31427533df5f433df9146 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 28 Jul 2013 19:45:30 +0200
+Subject: [PATCH 26/53] DT: Add documentation for gpio-ralink
+
+Describe gpio-ralink binding.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+Cc: linux-mips@linux-mips.org
+Cc: devicetree@vger.kernel.org
+Cc: linux-gpio@vger.kernel.org
+---
+ .../devicetree/bindings/gpio/gpio-ralink.txt       |   40 ++++++++++++++++++++
+ 1 file changed, 40 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/gpio/gpio-ralink.txt
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/gpio/gpio-ralink.txt
+@@ -0,0 +1,40 @@
++Ralink SoC GPIO controller bindings
++
++Required properties:
++- compatible:
++  - "ralink,rt2880-gpio" for Ralink controllers
++- #gpio-cells : Should be two.
++  - first cell is the pin number
++  - second cell is used to specify optional parameters (unused)
++- gpio-controller : Marks the device node as a GPIO controller
++- reg : Physical base address and length of the controller's registers
++- interrupt-parent: phandle to the INTC device node
++- interrupts : Specify the INTC interrupt number
++- ngpios : Specify the number of GPIOs
++- ralink,register-map : The register layout depends on the GPIO bank and actual
++		SoC type. Register offsets need to be in this order.
++		[ INT, EDGE, RENA, FENA, DATA, DIR, POL, SET, RESET, TOGGLE ]
++
++Optional properties:
++- ralink,gpio-base : Specify the GPIO chips base number
++
++Example:
++
++	gpio0: gpio@600 {
++		compatible = "ralink,rt5350-gpio", "ralink,rt2880-gpio";
++
++		#gpio-cells = <2>;
++		gpio-controller;
++
++		reg = <0x600 0x34>;
++
++		interrupt-parent = <&intc>;
++		interrupts = <6>;
++
++		ngpios = <24>;
++		ralink,gpio-base = <0>;
++		ralink,register-map = [ 00 04 08 0c
++				20 24 28 2c
++				30 34 ];
++
++	};
diff --git a/target/linux/ramips/patches-6.1/802-GPIO-MIPS-ralink-add-gpio-driver-for-ralink-SoC.patch b/target/linux/ramips/patches-6.1/802-GPIO-MIPS-ralink-add-gpio-driver-for-ralink-SoC.patch
new file mode 100644
index 00000000000000..ff60b33cd42d80
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/802-GPIO-MIPS-ralink-add-gpio-driver-for-ralink-SoC.patch
@@ -0,0 +1,416 @@
+From 69fdd2c4f937796b934e89c33acde9d082e27bfd Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 4 Aug 2014 20:36:29 +0200
+Subject: [PATCH 27/53] GPIO: MIPS: ralink: add gpio driver for ralink SoC
+
+Add gpio driver for Ralink SoC. This driver makes the gpio core on
+RT2880, RT305x, rt3352, rt3662, rt3883, rt5350 and mt7620 work.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+Cc: linux-mips@linux-mips.org
+Cc: linux-gpio@vger.kernel.org
+---
+ arch/mips/include/asm/mach-ralink/gpio.h |   24 ++
+ drivers/gpio/Kconfig                     |    6 +
+ drivers/gpio/Makefile                    |    1 +
+ drivers/gpio/gpio-ralink.c               |  355 ++++++++++++++++++++++++++++++
+ 4 files changed, 386 insertions(+)
+ create mode 100644 arch/mips/include/asm/mach-ralink/gpio.h
+ create mode 100644 drivers/gpio/gpio-ralink.c
+
+--- /dev/null
++++ b/arch/mips/include/asm/mach-ralink/gpio.h
+@@ -0,0 +1,24 @@
++/*
++ *  Ralink SoC GPIO API support
++ *
++ *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
++ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
++ *
++ *  This program is free software; you can redistribute it and/or modify it
++ *  under the terms of the GNU General Public License version 2 as published
++ *  by the Free Software Foundation.
++ *
++ */
++
++#ifndef __ASM_MACH_RALINK_GPIO_H
++#define __ASM_MACH_RALINK_GPIO_H
++
++#define ARCH_NR_GPIOS	128
++#include <asm-generic/gpio.h>
++
++#define gpio_get_value	__gpio_get_value
++#define gpio_set_value	__gpio_set_value
++#define gpio_cansleep	__gpio_cansleep
++#define gpio_to_irq	__gpio_to_irq
++
++#endif /* __ASM_MACH_RALINK_GPIO_H */
+--- a/drivers/gpio/Kconfig
++++ b/drivers/gpio/Kconfig
+@@ -585,6 +585,12 @@ config GPIO_SNPS_CREG
+ 	  where only several fields in register belong to GPIO lines and
+ 	  each GPIO line owns a field with different length and on/off value.
+ 
++config GPIO_RALINK
++	bool "Ralink GPIO Support"
++	depends on RALINK
++	help
++	  Say yes here to support the Ralink SoC GPIO device
++
+ config GPIO_SPEAR_SPICS
+ 	bool "ST SPEAr13xx SPI Chip Select as GPIO support"
+ 	depends on PLAT_SPEAR
+--- a/drivers/gpio/Makefile
++++ b/drivers/gpio/Makefile
+@@ -122,6 +122,7 @@ obj-$(CONFIG_GPIO_PISOSR)		+= gpio-pisos
+ obj-$(CONFIG_GPIO_PL061)		+= gpio-pl061.o
+ obj-$(CONFIG_GPIO_PMIC_EIC_SPRD)	+= gpio-pmic-eic-sprd.o
+ obj-$(CONFIG_GPIO_PXA)			+= gpio-pxa.o
++obj-$(CONFIG_GPIO_RALINK)		+= gpio-ralink.o
+ obj-$(CONFIG_GPIO_RASPBERRYPI_EXP)	+= gpio-raspberrypi-exp.o
+ obj-$(CONFIG_GPIO_RC5T583)		+= gpio-rc5t583.o
+ obj-$(CONFIG_GPIO_RCAR)			+= gpio-rcar.o
+--- /dev/null
++++ b/drivers/gpio/gpio-ralink.c
+@@ -0,0 +1,341 @@
++/*
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ *
++ * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
++ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
++ */
++
++#include <linux/module.h>
++#include <linux/io.h>
++#include <linux/gpio.h>
++#include <linux/spinlock.h>
++#include <linux/platform_device.h>
++#include <linux/of_irq.h>
++#include <linux/irqdomain.h>
++#include <linux/interrupt.h>
++
++enum ralink_gpio_reg {
++	GPIO_REG_INT = 0,
++	GPIO_REG_EDGE,
++	GPIO_REG_RENA,
++	GPIO_REG_FENA,
++	GPIO_REG_DATA,
++	GPIO_REG_DIR,
++	GPIO_REG_POL,
++	GPIO_REG_SET,
++	GPIO_REG_RESET,
++	GPIO_REG_TOGGLE,
++	GPIO_REG_MAX
++};
++
++struct ralink_gpio_chip {
++	struct gpio_chip chip;
++	u8 regs[GPIO_REG_MAX];
++
++	spinlock_t lock;
++	void __iomem *membase;
++	struct irq_domain *domain;
++	int irq;
++
++	u32 rising;
++	u32 falling;
++};
++
++#define MAP_MAX	4
++static struct irq_domain *irq_map[MAP_MAX];
++static int irq_map_count;
++static atomic_t irq_refcount = ATOMIC_INIT(0);
++
++static inline struct ralink_gpio_chip *to_ralink_gpio(struct gpio_chip *chip)
++{
++	struct ralink_gpio_chip *rg;
++
++	rg = container_of(chip, struct ralink_gpio_chip, chip);
++
++	return rg;
++}
++
++static inline void rt_gpio_w32(struct ralink_gpio_chip *rg, u8 reg, u32 val)
++{
++	iowrite32(val, rg->membase + rg->regs[reg]);
++}
++
++static inline u32 rt_gpio_r32(struct ralink_gpio_chip *rg, u8 reg)
++{
++	return ioread32(rg->membase + rg->regs[reg]);
++}
++
++static void ralink_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
++{
++	struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
++
++	rt_gpio_w32(rg, (value) ? GPIO_REG_SET : GPIO_REG_RESET, BIT(offset));
++}
++
++static int ralink_gpio_get(struct gpio_chip *chip, unsigned offset)
++{
++	struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
++
++	return !!(rt_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset));
++}
++
++static int ralink_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
++{
++	struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
++	unsigned long flags;
++	u32 t;
++
++	spin_lock_irqsave(&rg->lock, flags);
++	t = rt_gpio_r32(rg, GPIO_REG_DIR);
++	t &= ~BIT(offset);
++	rt_gpio_w32(rg, GPIO_REG_DIR, t);
++	spin_unlock_irqrestore(&rg->lock, flags);
++
++	return 0;
++}
++
++static int ralink_gpio_direction_output(struct gpio_chip *chip,
++					unsigned offset, int value)
++{
++	struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
++	unsigned long flags;
++	u32 t;
++
++	spin_lock_irqsave(&rg->lock, flags);
++	ralink_gpio_set(chip, offset, value);
++	t = rt_gpio_r32(rg, GPIO_REG_DIR);
++	t |= BIT(offset);
++	rt_gpio_w32(rg, GPIO_REG_DIR, t);
++	spin_unlock_irqrestore(&rg->lock, flags);
++
++	return 0;
++}
++
++static int ralink_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
++{
++	struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
++
++	if (rg->irq < 1)
++		return -1;
++
++	return irq_create_mapping(rg->domain, pin);
++}
++
++static void ralink_gpio_irq_handler(struct irq_desc *desc)
++{
++	int i;
++
++	for (i = 0; i < irq_map_count; i++) {
++		struct irq_domain *domain = irq_map[i];
++		struct ralink_gpio_chip *rg;
++		unsigned long pending;
++		int bit;
++
++		rg = (struct ralink_gpio_chip *) domain->host_data;
++		pending = rt_gpio_r32(rg, GPIO_REG_INT);
++
++		for_each_set_bit(bit, &pending, rg->chip.ngpio) {
++			u32 map = irq_find_mapping(domain, bit);
++			generic_handle_irq(map);
++			rt_gpio_w32(rg, GPIO_REG_INT, BIT(bit));
++		}
++	}
++}
++
++static void ralink_gpio_irq_unmask(struct irq_data *d)
++{
++	struct ralink_gpio_chip *rg;
++	unsigned long flags;
++	u32 rise, fall;
++
++	rg = (struct ralink_gpio_chip *) d->domain->host_data;
++	rise = rt_gpio_r32(rg, GPIO_REG_RENA);
++	fall = rt_gpio_r32(rg, GPIO_REG_FENA);
++
++	spin_lock_irqsave(&rg->lock, flags);
++	rt_gpio_w32(rg, GPIO_REG_RENA, rise | (BIT(d->hwirq) & rg->rising));
++	rt_gpio_w32(rg, GPIO_REG_FENA, fall | (BIT(d->hwirq) & rg->falling));
++	spin_unlock_irqrestore(&rg->lock, flags);
++}
++
++static void ralink_gpio_irq_mask(struct irq_data *d)
++{
++	struct ralink_gpio_chip *rg;
++	unsigned long flags;
++	u32 rise, fall;
++
++	rg = (struct ralink_gpio_chip *) d->domain->host_data;
++	rise = rt_gpio_r32(rg, GPIO_REG_RENA);
++	fall = rt_gpio_r32(rg, GPIO_REG_FENA);
++
++	spin_lock_irqsave(&rg->lock, flags);
++	rt_gpio_w32(rg, GPIO_REG_FENA, fall & ~BIT(d->hwirq));
++	rt_gpio_w32(rg, GPIO_REG_RENA, rise & ~BIT(d->hwirq));
++	spin_unlock_irqrestore(&rg->lock, flags);
++}
++
++static int ralink_gpio_irq_type(struct irq_data *d, unsigned int type)
++{
++	struct ralink_gpio_chip *rg;
++	u32 mask = BIT(d->hwirq);
++
++	rg = (struct ralink_gpio_chip *) d->domain->host_data;
++
++	if (type == IRQ_TYPE_PROBE) {
++		if ((rg->rising | rg->falling) & mask)
++			return 0;
++
++		type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
++	}
++
++	if (type & IRQ_TYPE_EDGE_RISING)
++		rg->rising |= mask;
++	else
++		rg->rising &= ~mask;
++
++	if (type & IRQ_TYPE_EDGE_FALLING)
++		rg->falling |= mask;
++	else
++		rg->falling &= ~mask;
++
++	return 0;
++}
++
++static struct irq_chip ralink_gpio_irq_chip = {
++	.name		= "GPIO",
++	.irq_unmask	= ralink_gpio_irq_unmask,
++	.irq_mask	= ralink_gpio_irq_mask,
++	.irq_mask_ack	= ralink_gpio_irq_mask,
++	.irq_set_type	= ralink_gpio_irq_type,
++};
++
++static int gpio_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
++{
++	irq_set_chip_and_handler(irq, &ralink_gpio_irq_chip, handle_level_irq);
++	irq_set_handler_data(irq, d);
++
++	return 0;
++}
++
++static const struct irq_domain_ops irq_domain_ops = {
++	.xlate = irq_domain_xlate_onecell,
++	.map = gpio_map,
++};
++
++static void ralink_gpio_irq_init(struct device_node *np,
++				 struct ralink_gpio_chip *rg)
++{
++	if (irq_map_count >= MAP_MAX)
++		return;
++
++	rg->irq = irq_of_parse_and_map(np, 0);
++	if (!rg->irq)
++		return;
++
++	rg->domain = irq_domain_add_linear(np, rg->chip.ngpio,
++					   &irq_domain_ops, rg);
++	if (!rg->domain) {
++		dev_err(rg->chip.parent, "irq_domain_add_linear failed\n");
++		return;
++	}
++
++	irq_map[irq_map_count++] = rg->domain;
++
++	rt_gpio_w32(rg, GPIO_REG_RENA, 0x0);
++	rt_gpio_w32(rg, GPIO_REG_FENA, 0x0);
++
++	if (!atomic_read(&irq_refcount))
++		irq_set_chained_handler(rg->irq, ralink_gpio_irq_handler);
++	atomic_inc(&irq_refcount);
++
++	dev_info(rg->chip.parent, "registering %d irq handlers\n", rg->chip.ngpio);
++}
++
++static int ralink_gpio_probe(struct platform_device *pdev)
++{
++	struct device_node *np = pdev->dev.of_node;
++	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	struct ralink_gpio_chip *rg;
++	const __be32 *ngpio, *gpiobase;
++
++	if (!res) {
++		dev_err(&pdev->dev, "failed to find resource\n");
++		return -ENOMEM;
++	}
++
++	rg = devm_kzalloc(&pdev->dev,
++			sizeof(struct ralink_gpio_chip), GFP_KERNEL);
++	if (!rg)
++		return -ENOMEM;
++
++	rg->membase = devm_ioremap_resource(&pdev->dev, res);
++	if (!rg->membase) {
++		dev_err(&pdev->dev, "cannot remap I/O memory region\n");
++		return -ENOMEM;
++	}
++
++	if (of_property_read_u8_array(np, "ralink,register-map",
++			rg->regs, GPIO_REG_MAX)) {
++		dev_err(&pdev->dev, "failed to read register definition\n");
++		return -EINVAL;
++	}
++
++	ngpio = of_get_property(np, "ngpios", NULL);
++	if (!ngpio) {
++		dev_err(&pdev->dev, "failed to read number of pins\n");
++		return -EINVAL;
++	}
++
++	gpiobase = of_get_property(np, "ralink,gpio-base", NULL);
++	if (gpiobase)
++		rg->chip.base = be32_to_cpu(*gpiobase);
++	else
++		rg->chip.base = -1;
++
++	spin_lock_init(&rg->lock);
++
++	rg->chip.parent = &pdev->dev;
++	rg->chip.label = dev_name(&pdev->dev);
++	rg->chip.of_node = np;
++	rg->chip.ngpio = be32_to_cpu(*ngpio);
++	rg->chip.direction_input = ralink_gpio_direction_input;
++	rg->chip.direction_output = ralink_gpio_direction_output;
++	rg->chip.get = ralink_gpio_get;
++	rg->chip.set = ralink_gpio_set;
++	rg->chip.request = gpiochip_generic_request;
++	rg->chip.to_irq = ralink_gpio_to_irq;
++	rg->chip.free = gpiochip_generic_free;
++
++	/* set polarity to low for all lines */
++	rt_gpio_w32(rg, GPIO_REG_POL, 0);
++
++	dev_info(&pdev->dev, "registering %d gpios\n", rg->chip.ngpio);
++
++	ralink_gpio_irq_init(np, rg);
++
++	return gpiochip_add(&rg->chip);
++}
++
++static const struct of_device_id ralink_gpio_match[] = {
++	{ .compatible = "ralink,rt2880-gpio" },
++	{},
++};
++MODULE_DEVICE_TABLE(of, ralink_gpio_match);
++
++static struct platform_driver ralink_gpio_driver = {
++	.probe = ralink_gpio_probe,
++	.driver = {
++		.name = "rt2880_gpio",
++		.owner = THIS_MODULE,
++		.of_match_table = ralink_gpio_match,
++	},
++};
++
++static int __init ralink_gpio_init(void)
++{
++	return platform_driver_register(&ralink_gpio_driver);
++}
++
++subsys_initcall(ralink_gpio_init);
diff --git a/target/linux/ramips/patches-6.1/803-gpio-ralink-Add-support-for-GPIO-as-interrupt-contro.patch b/target/linux/ramips/patches-6.1/803-gpio-ralink-Add-support-for-GPIO-as-interrupt-contro.patch
new file mode 100644
index 00000000000000..8520ce32ff7b2f
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/803-gpio-ralink-Add-support-for-GPIO-as-interrupt-contro.patch
@@ -0,0 +1,44 @@
+From 57fa7f2f4ef6f78ce1d30509c0d111aa3791b524 Mon Sep 17 00:00:00 2001
+From: Daniel Santos <daniel.santos@pobox.com>
+Date: Sun, 4 Nov 2018 20:24:32 -0600
+Subject: gpio-ralink: Add support for GPIO as interrupt-controller
+
+Signed-off-by: Daniel Santos <daniel.santos@pobox.com>
+---
+ Documentation/devicetree/bindings/gpio/gpio-ralink.txt | 6 ++++++
+ drivers/gpio/gpio-ralink.c                             | 2 +-
+ 2 files changed, 7 insertions(+), 1 deletion(-)
+
+--- a/Documentation/devicetree/bindings/gpio/gpio-ralink.txt
++++ b/Documentation/devicetree/bindings/gpio/gpio-ralink.txt
+@@ -17,6 +17,9 @@ Required properties:
+ 
+ Optional properties:
+ - ralink,gpio-base : Specify the GPIO chips base number
++- interrupt-controller : marks this as an interrupt controller
++- #interrupt-cells : a standard two-cell interrupt flag, see
++  interrupt-controller/interrupts.txt
+ 
+ Example:
+ 
+@@ -28,6 +31,9 @@ Example:
+ 
+ 		reg = <0x600 0x34>;
+ 
++		interrupt-controller;
++		#interrupt-cells = <2>;
++
+ 		interrupt-parent = <&intc>;
+ 		interrupts = <6>;
+ 
+--- a/drivers/gpio/gpio-ralink.c
++++ b/drivers/gpio/gpio-ralink.c
+@@ -220,7 +220,7 @@ static int gpio_map(struct irq_domain *d
+ }
+ 
+ static const struct irq_domain_ops irq_domain_ops = {
+-	.xlate = irq_domain_xlate_onecell,
++	.xlate = irq_domain_xlate_twocell,
+ 	.map = gpio_map,
+ };
+ 
diff --git a/target/linux/ramips/patches-6.1/805-pinctrl-AW9523.patch b/target/linux/ramips/patches-6.1/805-pinctrl-AW9523.patch
new file mode 100644
index 00000000000000..f9fa791fe1d05d
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/805-pinctrl-AW9523.patch
@@ -0,0 +1,72 @@
+From: AngeloGioacchino Del Regno
+        <angelogioacchino.delregno@somainline.org>
+To: linus.walleij@linaro.org
+Cc: linux-kernel@vger.kernel.org, konrad.dybcio@somainline.org,
+        marijn.suijten@somainline.org, martin.botka@somainline.org,
+        phone-devel@vger.kernel.org, linux-gpio@vger.kernel.org,
+        devicetree@vger.kernel.org, robh+dt@kernel.org,
+        AngeloGioacchino Del Regno
+        <angelogioacchino.delregno@somainline.org>
+Subject: [PATCH v5 1/2] pinctrl: Add driver for Awinic AW9523/B I2C GPIO
+ Expander
+Date: Mon, 25 Jan 2021 19:22:18 +0100
+
+The Awinic AW9523(B) is a multi-function I2C gpio expander in a
+TQFN-24L package, featuring PWM (max 37mA per pin, or total max
+power 3.2Watts) for LED driving capability.
+
+It has two ports with 8 pins per port (for a total of 16 pins),
+configurable as either PWM with 1/256 stepping or GPIO input/output,
+1.8V logic input; each GPIO can be configured as input or output
+independently from each other.
+
+This IC also has an internal interrupt controller, which is capable
+of generating an interrupt for each GPIO, depending on the
+configuration, and will raise an interrupt on the INTN pin to
+advertise this to an external interrupt controller.
+
+Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
+---
+ drivers/pinctrl/Kconfig          |   17 +
+ drivers/pinctrl/Makefile         |    1 +
+ drivers/pinctrl/pinctrl-aw9523.c | 1122 ++++++++++++++++++++++++++++++
+ 3 files changed, 1140 insertions(+)
+ create mode 100644 drivers/pinctrl/pinctrl-aw9523.c
+
+--- a/drivers/pinctrl/Kconfig
++++ b/drivers/pinctrl/Kconfig
+@@ -113,6 +113,24 @@ config PINCTRL_AT91PIO4
+ 	  Say Y here to enable the at91 pinctrl/gpio driver for Atmel PIO4
+ 	  controller available on sama5d2 SoC.
+ 
++config PINCTRL_AW9523
++	bool "Awinic AW9523/AW9523B I2C GPIO expander pinctrl driver"
++	depends on OF && I2C
++	select PINMUX
++	select PINCONF
++	select GENERIC_PINCONF
++	select GPIOLIB
++	select GPIOLIB_IRQCHIP
++	select REGMAP
++	select REGMAP_I2C
++	help
++	  The Awinic AW9523/AW9523B is a multi-function I2C GPIO
++	  expander with PWM functionality. This driver bundles a
++	  pinctrl driver to select the function muxing and a GPIO
++	  driver to handle GPIO, when the GPIO function is selected.
++
++	  Say yes to enable pinctrl and GPIO support for the AW9523(B).
++
+ config PINCTRL_AXP209
+ 	tristate "X-Powers AXP209 PMIC pinctrl and GPIO Support"
+ 	depends on MFD_AXP20X
+--- a/drivers/pinctrl/Makefile
++++ b/drivers/pinctrl/Makefile
+@@ -15,6 +15,7 @@ obj-$(CONFIG_PINCTRL_ARTPEC6)	+= pinctrl
+ obj-$(CONFIG_PINCTRL_AS3722)	+= pinctrl-as3722.o
+ obj-$(CONFIG_PINCTRL_AT91)	+= pinctrl-at91.o
+ obj-$(CONFIG_PINCTRL_AT91PIO4)	+= pinctrl-at91-pio4.o
++obj-$(CONFIG_PINCTRL_AW9523)	+= pinctrl-aw9523.o
+ obj-$(CONFIG_PINCTRL_AXP209)	+= pinctrl-axp209.o
+ obj-$(CONFIG_PINCTRL_BM1880)	+= pinctrl-bm1880.o
+ obj-$(CONFIG_PINCTRL_CY8C95X0)	+= pinctrl-cy8c95x0.o
diff --git a/target/linux/ramips/patches-6.1/808-pinctrl-mtmips-support-requesting-different-function.patch b/target/linux/ramips/patches-6.1/808-pinctrl-mtmips-support-requesting-different-function.patch
new file mode 100644
index 00000000000000..047808f1e6904d
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/808-pinctrl-mtmips-support-requesting-different-function.patch
@@ -0,0 +1,45 @@
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Wed, 26 Jul 2023 01:32:55 +0800
+Subject: [PATCH] pinctrl: mtmips: support requesting different functions for
+ same group
+
+Sometimes pinctrl consumers may request different functions for the
+same pin group in different situations. This patch can help to reset
+the group function flag when requesting a different function.
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ drivers/pinctrl/ralink/pinctrl-ralink.c | 21 +++++++++++++++++----
+ 1 file changed, 17 insertions(+), 4 deletions(-)
+
+--- a/drivers/pinctrl/ralink/pinctrl-ralink.c
++++ b/drivers/pinctrl/ralink/pinctrl-ralink.c
+@@ -123,11 +123,24 @@ static int ralink_pmx_group_enable(struc
+ 	int i;
+ 	int shift;
+ 
+-	/* dont allow double use */
++	/*
++	 * for the same pin group, if request a different function,
++	 * then clear the group function flag and continue, else exit.
++	 */
+ 	if (p->groups[group].enabled) {
+-		dev_err(p->dev, "%s is already enabled\n",
+-			p->groups[group].name);
+-		return 0;
++		for (i = 0; i < p->groups[group].func_count; i++) {
++			if (p->groups[group].func[i].enabled == 1) {
++				if (!strcmp(p->func[func]->name,
++					p->groups[group].func[i].name))
++					return 0;
++				p->groups[group].func[i].enabled = 0;
++				break;
++			}
++		}
++
++		/* exit if request the "gpio" function again */
++		if (i == p->groups[group].func_count && func == 0)
++			return 0;
+ 	}
+ 
+ 	p->groups[group].enabled = 1;
diff --git a/target/linux/ramips/patches-6.1/810-uvc-add-iPassion-iP2970-support.patch b/target/linux/ramips/patches-6.1/810-uvc-add-iPassion-iP2970-support.patch
new file mode 100644
index 00000000000000..d48b668484fb3a
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/810-uvc-add-iPassion-iP2970-support.patch
@@ -0,0 +1,244 @@
+From 975e76214cd2516eb6cfff4c3eec581872645e88 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 19 Sep 2013 01:50:59 +0200
+Subject: [PATCH 31/53] uvc: add iPassion iP2970 support
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/media/usb/uvc/uvc_driver.c |   12 +++
+ drivers/media/usb/uvc/uvc_status.c |    2 +
+ drivers/media/usb/uvc/uvc_video.c  |  147 ++++++++++++++++++++++++++++++++++++
+ drivers/media/usb/uvc/uvcvideo.h   |    5 +-
+ 4 files changed, 165 insertions(+), 1 deletion(-)
+
+--- a/drivers/media/usb/uvc/uvc_driver.c
++++ b/drivers/media/usb/uvc/uvc_driver.c
+@@ -2981,6 +2981,18 @@ static const struct usb_device_id uvc_id
+ 	  .bInterfaceSubClass	= 1,
+ 	  .bInterfaceProtocol	= 0,
+ 	  .driver_info		= UVC_INFO_META(V4L2_META_FMT_D4XX) },
++	/* iPassion iP2970 */
++	{ .match_flags          = USB_DEVICE_ID_MATCH_DEVICE
++				| USB_DEVICE_ID_MATCH_INT_INFO,
++	 .idVendor		= 0x1B3B,
++	 .idProduct		= 0x2970,
++	 .bInterfaceClass	= USB_CLASS_VIDEO,
++	 .bInterfaceSubClass	= 1,
++	 .bInterfaceProtocol	= 0,
++	 .driver_info		= UVC_QUIRK_PROBE_MINMAX
++				| UVC_QUIRK_STREAM_NO_FID
++				| UVC_QUIRK_MOTION
++				| UVC_QUIRK_SINGLE_ISO },
+ 	/* Generic USB Video Class */
+ 	{ USB_INTERFACE_INFO(USB_CLASS_VIDEO, 1, UVC_PC_PROTOCOL_UNDEFINED) },
+ 	{ USB_INTERFACE_INFO(USB_CLASS_VIDEO, 1, UVC_PC_PROTOCOL_15) },
+--- a/drivers/media/usb/uvc/uvc_status.c
++++ b/drivers/media/usb/uvc/uvc_status.c
+@@ -223,6 +223,7 @@ static void uvc_status_complete(struct u
+ 			if (uvc_event_control(urb, status, len))
+ 				/* The URB will be resubmitted in work context. */
+ 				return;
++			dev->motion = 1;
+ 			break;
+ 		}
+ 
+@@ -271,6 +272,7 @@ int uvc_status_init(struct uvc_device *d
+ 	}
+ 
+ 	pipe = usb_rcvintpipe(dev->udev, ep->desc.bEndpointAddress);
++	dev->motion = 0;
+ 
+ 	/*
+ 	 * For high-speed interrupt endpoints, the bInterval value is used as
+--- a/drivers/media/usb/uvc/uvc_video.c
++++ b/drivers/media/usb/uvc/uvc_video.c
+@@ -19,6 +19,11 @@
+ #include <linux/wait.h>
+ #include <linux/atomic.h>
+ #include <asm/unaligned.h>
++#include <linux/skbuff.h>
++#include <linux/kobject.h>
++#include <linux/netlink.h>
++#include <linux/kobject.h>
++#include <linux/workqueue.h>
+ 
+ #include <media/v4l2-common.h>
+ 
+@@ -1231,9 +1236,149 @@ static void uvc_video_decode_data(struct
+ 	uvc_urb->async_operations++;
+ }
+ 
++struct bh_priv {
++	unsigned long	seen;
++};
++
++struct bh_event {
++	const char		*name;
++	struct sk_buff		*skb;
++	struct work_struct	work;
++};
++
++#define BH_ERR(fmt, args...) printk(KERN_ERR "%s: " fmt, "webcam", ##args )
++#define BH_DBG(fmt, args...) do {} while (0)
++#define BH_SKB_SIZE     2048
++
++extern u64 uevent_next_seqnum(void);
++static int seen = 0;
++
++static int bh_event_add_var(struct bh_event *event, int argv,
++		const char *format, ...)
++{
++	static char buf[128];
++	char *s;
++	va_list args;
++	int len;
++
++	if (argv)
++		return 0;
++
++	va_start(args, format);
++	len = vsnprintf(buf, sizeof(buf), format, args);
++	va_end(args);
++
++	if (len >= sizeof(buf)) {
++		BH_ERR("buffer size too small\n");
++		WARN_ON(1);
++		return -ENOMEM;
++	}
++
++	s = skb_put(event->skb, len + 1);
++	strcpy(s, buf);
++
++	BH_DBG("added variable '%s'\n", s);
++
++	return 0;
++}
++
++static int motion_hotplug_fill_event(struct bh_event *event)
++{
++	int s = jiffies;
++	int ret;
++
++	if (!seen)
++		seen = jiffies;
++
++	ret = bh_event_add_var(event, 0, "HOME=%s", "/");
++	if (ret)
++		return ret;
++
++	ret = bh_event_add_var(event, 0, "PATH=%s",
++		"/sbin:/bin:/usr/sbin:/usr/bin");
++	if (ret)
++		return ret;
++
++	ret = bh_event_add_var(event, 0, "SUBSYSTEM=usb");
++	if (ret)
++		return ret;
++
++	ret = bh_event_add_var(event, 0, "ACTION=motion");
++	if (ret)
++		return ret;
++
++	ret = bh_event_add_var(event, 0, "SEEN=%d", s - seen);
++	if (ret)
++		return ret;
++	seen = s;
++
++	ret = bh_event_add_var(event, 0, "SEQNUM=%llu", uevent_next_seqnum());
++
++	return ret;
++}
++
++static void motion_hotplug_work(struct work_struct *work)
++{
++	struct bh_event *event = container_of(work, struct bh_event, work);
++	int ret = 0;
++
++	event->skb = alloc_skb(BH_SKB_SIZE, GFP_KERNEL);
++	if (!event->skb)
++		goto out_free_event;
++
++	ret = bh_event_add_var(event, 0, "%s@", "add");
++	if (ret)
++		goto out_free_skb;
++
++	ret = motion_hotplug_fill_event(event);
++	if (ret)
++		goto out_free_skb;
++
++	NETLINK_CB(event->skb).dst_group = 1;
++	broadcast_uevent(event->skb, 0, 1, GFP_KERNEL);
++
++out_free_skb:
++	if (ret) {
++		BH_ERR("work error %d\n", ret);
++		kfree_skb(event->skb);
++	}
++out_free_event:
++	kfree(event);
++}
++
++static int motion_hotplug_create_event(void)
++{
++	struct bh_event *event;
++
++	event = kzalloc(sizeof(*event), GFP_KERNEL);
++	if (!event)
++		return -ENOMEM;
++
++	event->name = "motion";
++
++	INIT_WORK(&event->work, (void *)(void *)motion_hotplug_work);
++	schedule_work(&event->work);
++
++	return 0;
++}
++
++#define MOTION_FLAG_OFFSET	4
+ static void uvc_video_decode_end(struct uvc_streaming *stream,
+ 		struct uvc_buffer *buf, const u8 *data, int len)
+ {
++	if ((stream->dev->quirks & UVC_QUIRK_MOTION) &&
++			(data[len - 2] == 0xff) && (data[len - 1] == 0xd9)) {
++		u8 *mem;
++		buf->state = UVC_BUF_STATE_READY;
++		mem = (u8 *) (buf->mem + MOTION_FLAG_OFFSET);
++		if ( stream->dev->motion ) {
++			stream->dev->motion = 0;
++			motion_hotplug_create_event();
++		} else {
++			*mem &= 0x7f;
++		}
++	}
++
+ 	/* Mark the buffer as done if the EOF marker is set. */
+ 	if (data[1] & UVC_STREAM_EOF && buf->bytesused != 0) {
+ 		uvc_dbg(stream->dev, FRAME, "Frame complete (EOF found)\n");
+@@ -1815,6 +1960,8 @@ static int uvc_init_video_isoc(struct uv
+ 	if (npackets == 0)
+ 		return -ENOMEM;
+ 
++	if (stream->dev->quirks & UVC_QUIRK_SINGLE_ISO)
++		npackets = 1;
+ 	size = npackets * psize;
+ 
+ 	for_each_uvc_urb(uvc_urb, stream) {
+--- a/drivers/media/usb/uvc/uvcvideo.h
++++ b/drivers/media/usb/uvc/uvcvideo.h
+@@ -75,6 +75,8 @@
+ #define UVC_QUIRK_FORCE_Y8		0x00000800
+ #define UVC_QUIRK_FORCE_BPP		0x00001000
+ #define UVC_QUIRK_WAKE_AUTOSUSPEND	0x00002000
++#define UVC_QUIRK_MOTION		0x00004000
++#define UVC_QUIRK_SINGLE_ISO		0x00008000
+ 
+ /* Format flags */
+ #define UVC_FMT_FLAG_COMPRESSED		0x00000001
+@@ -562,6 +564,7 @@ struct uvc_device {
+ 	u8 *status;
+ 	struct input_dev *input;
+ 	char input_phys[64];
++	int motion;
+ 
+ 	struct uvc_ctrl_work {
+ 		struct work_struct work;
diff --git a/target/linux/ramips/patches-6.1/820-DT-Add-documentation-for-spi-rt2880.patch b/target/linux/ramips/patches-6.1/820-DT-Add-documentation-for-spi-rt2880.patch
new file mode 100644
index 00000000000000..e2643e3f2544e0
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/820-DT-Add-documentation-for-spi-rt2880.patch
@@ -0,0 +1,44 @@
+From da6015e7f19d749f135f7ac55c4ec47b06faa868 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Fri, 9 Aug 2013 20:12:59 +0200
+Subject: [PATCH 41/53] DT: Add documentation for spi-rt2880
+
+Describe the SPI master found on the MIPS based Ralink RT2880 SoC.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ .../devicetree/bindings/spi/spi-rt2880.txt         |   28 ++++++++++++++++++++
+ 1 file changed, 28 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/spi/spi-rt2880.txt
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/spi/spi-rt2880.txt
+@@ -0,0 +1,28 @@
++Ralink SoC RT2880 SPI master controller.
++
++This SPI controller is found on most wireless SoCs made by ralink.
++
++Required properties:
++- compatible : "ralink,rt2880-spi"
++- reg : The register base for the controller.
++- #address-cells : <1>, as required by generic SPI binding.
++- #size-cells : <0>, also as required by generic SPI binding.
++
++Child nodes as per the generic SPI binding.
++
++Example:
++
++	spi@b00 {
++		compatible = "ralink,rt2880-spi";
++		reg = <0xb00 0x100>;
++
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		m25p80@0 {
++			compatible = "m25p80";
++			reg = <0>;
++			spi-max-frequency = <10000000>;
++		};
++	};
++
diff --git a/target/linux/ramips/patches-6.1/821-SPI-ralink-add-Ralink-SoC-spi-driver.patch b/target/linux/ramips/patches-6.1/821-SPI-ralink-add-Ralink-SoC-spi-driver.patch
new file mode 100644
index 00000000000000..9aaf86ffc71545
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/821-SPI-ralink-add-Ralink-SoC-spi-driver.patch
@@ -0,0 +1,579 @@
+From 683af4ebb91a1600df1946ac4769d916b8a1be65 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 27 Jul 2014 11:15:12 +0100
+Subject: [PATCH 42/53] SPI: ralink: add Ralink SoC spi driver
+
+Add the driver needed to make SPI work on Ralink SoC.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Acked-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/spi/Kconfig      |    6 +
+ drivers/spi/Makefile     |    1 +
+ drivers/spi/spi-rt2880.c |  530 ++++++++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 537 insertions(+)
+ create mode 100644 drivers/spi/spi-rt2880.c
+
+--- a/drivers/spi/Kconfig
++++ b/drivers/spi/Kconfig
+@@ -823,6 +823,12 @@ config SPI_QCOM_GENI
+ 	  This driver can also be built as a module.  If so, the module
+ 	  will be called spi-geni-qcom.
+ 
++config SPI_RT2880
++	tristate "Ralink RT288x SPI Controller"
++	depends on RALINK
++	help
++	  This selects a driver for the Ralink RT288x/RT305x SPI Controller.
++
+ config SPI_S3C24XX
+ 	tristate "Samsung S3C24XX series SPI"
+ 	depends on ARCH_S3C24XX
+--- a/drivers/spi/Makefile
++++ b/drivers/spi/Makefile
+@@ -110,6 +110,7 @@ obj-$(CONFIG_SPI_RB4XX)			+= spi-rb4xx.o
+ obj-$(CONFIG_MACH_REALTEK_RTL)		+= spi-realtek-rtl.o
+ obj-$(CONFIG_SPI_RPCIF)			+= spi-rpc-if.o
+ obj-$(CONFIG_SPI_RSPI)			+= spi-rspi.o
++obj-$(CONFIG_SPI_RT2880)		+= spi-rt2880.o
+ obj-$(CONFIG_SPI_S3C24XX)		+= spi-s3c24xx-hw.o
+ spi-s3c24xx-hw-y			:= spi-s3c24xx.o
+ obj-$(CONFIG_SPI_S3C64XX)		+= spi-s3c64xx.o
+--- /dev/null
++++ b/drivers/spi/spi-rt2880.c
+@@ -0,0 +1,535 @@
++/*
++ * spi-rt2880.c -- Ralink RT288x/RT305x SPI controller driver
++ *
++ * Copyright (C) 2011 Sergiy <piratfm@gmail.com>
++ * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
++ *
++ * Some parts are based on spi-orion.c:
++ *   Author: Shadi Ammouri <shadi@marvell.com>
++ *   Copyright (C) 2007-2008 Marvell Ltd.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/clk.h>
++#include <linux/err.h>
++#include <linux/delay.h>
++#include <linux/io.h>
++#include <linux/reset.h>
++#include <linux/spi/spi.h>
++#include <linux/platform_device.h>
++#include <linux/gpio.h>
++
++#define DRIVER_NAME			"spi-rt2880"
++
++#define RAMIPS_SPI_STAT			0x00
++#define RAMIPS_SPI_CFG			0x10
++#define RAMIPS_SPI_CTL			0x14
++#define RAMIPS_SPI_DATA			0x20
++#define RAMIPS_SPI_ADDR			0x24
++#define RAMIPS_SPI_BS			0x28
++#define RAMIPS_SPI_USER			0x2C
++#define RAMIPS_SPI_TXFIFO		0x30
++#define RAMIPS_SPI_RXFIFO		0x34
++#define RAMIPS_SPI_FIFO_STAT		0x38
++#define RAMIPS_SPI_MODE			0x3C
++#define RAMIPS_SPI_DEV_OFFSET		0x40
++#define RAMIPS_SPI_DMA			0x80
++#define RAMIPS_SPI_DMASTAT		0x84
++#define RAMIPS_SPI_ARBITER		0xF0
++
++/* SPISTAT register bit field */
++#define SPISTAT_BUSY			BIT(0)
++
++/* SPICFG register bit field */
++#define SPICFG_ADDRMODE			BIT(12)
++#define SPICFG_RXENVDIS			BIT(11)
++#define SPICFG_RXCAP			BIT(10)
++#define SPICFG_SPIENMODE		BIT(9)
++#define SPICFG_MSBFIRST			BIT(8)
++#define SPICFG_SPICLKPOL		BIT(6)
++#define SPICFG_RXCLKEDGE_FALLING	BIT(5)
++#define SPICFG_TXCLKEDGE_FALLING	BIT(4)
++#define SPICFG_HIZSPI			BIT(3)
++#define SPICFG_SPICLK_PRESCALE_MASK	0x7
++#define SPICFG_SPICLK_DIV2		0
++#define SPICFG_SPICLK_DIV4		1
++#define SPICFG_SPICLK_DIV8		2
++#define SPICFG_SPICLK_DIV16		3
++#define SPICFG_SPICLK_DIV32		4
++#define SPICFG_SPICLK_DIV64		5
++#define SPICFG_SPICLK_DIV128		6
++#define SPICFG_SPICLK_DISABLE		7
++
++/* SPICTL register bit field */
++#define SPICTL_START			BIT(4)
++#define SPICTL_HIZSDO			BIT(3)
++#define SPICTL_STARTWR			BIT(2)
++#define SPICTL_STARTRD			BIT(1)
++#define SPICTL_SPIENA			BIT(0)
++
++/* SPIUSER register bit field */
++#define SPIUSER_USERMODE		BIT(21)
++#define SPIUSER_INSTR_PHASE		BIT(20)
++#define SPIUSER_ADDR_PHASE_MASK		0x7
++#define SPIUSER_ADDR_PHASE_OFFSET	17
++#define SPIUSER_MODE_PHASE		BIT(16)
++#define SPIUSER_DUMMY_PHASE_MASK	0x3
++#define SPIUSER_DUMMY_PHASE_OFFSET	14
++#define SPIUSER_DATA_PHASE_MASK		0x3
++#define SPIUSER_DATA_PHASE_OFFSET	12
++#define SPIUSER_DATA_READ		(BIT(0) << SPIUSER_DATA_PHASE_OFFSET)
++#define SPIUSER_DATA_WRITE		(BIT(1) << SPIUSER_DATA_PHASE_OFFSET)
++#define SPIUSER_ADDR_TYPE_OFFSET	9
++#define SPIUSER_MODE_TYPE_OFFSET	6
++#define SPIUSER_DUMMY_TYPE_OFFSET	3
++#define SPIUSER_DATA_TYPE_OFFSET	0
++#define SPIUSER_TRANSFER_MASK		0x7
++#define SPIUSER_TRANSFER_SINGLE		BIT(0)
++#define SPIUSER_TRANSFER_DUAL		BIT(1)
++#define SPIUSER_TRANSFER_QUAD		BIT(2)
++
++#define SPIUSER_TRANSFER_TYPE(type) ( \
++	(type << SPIUSER_ADDR_TYPE_OFFSET) | \
++	(type << SPIUSER_MODE_TYPE_OFFSET) | \
++	(type << SPIUSER_DUMMY_TYPE_OFFSET) | \
++	(type << SPIUSER_DATA_TYPE_OFFSET) \
++)
++
++/* SPIFIFOSTAT register bit field */
++#define SPIFIFOSTAT_TXEMPTY		BIT(19)
++#define SPIFIFOSTAT_RXEMPTY		BIT(18)
++#define SPIFIFOSTAT_TXFULL		BIT(17)
++#define SPIFIFOSTAT_RXFULL		BIT(16)
++#define SPIFIFOSTAT_FIFO_MASK		0xff
++#define SPIFIFOSTAT_TX_OFFSET		8
++#define SPIFIFOSTAT_RX_OFFSET		0
++
++#define SPI_FIFO_DEPTH			16
++
++/* SPIMODE register bit field */
++#define SPIMODE_MODE_OFFSET		24
++#define SPIMODE_DUMMY_OFFSET		0
++
++/* SPIARB register bit field */
++#define SPICTL_ARB_EN			BIT(31)
++#define SPICTL_CSCTL1			BIT(16)
++#define SPI1_POR			BIT(1)
++#define SPI0_POR			BIT(0)
++
++#define RT2880_SPI_MODE_BITS	(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | \
++		SPI_CS_HIGH)
++
++static atomic_t hw_reset_count = ATOMIC_INIT(0);
++
++struct rt2880_spi {
++	struct spi_master	*master;
++	void __iomem		*base;
++	u32			speed;
++	u16			wait_loops;
++	u16			mode;
++	struct clk		*clk;
++};
++
++static inline struct rt2880_spi *spidev_to_rt2880_spi(struct spi_device *spi)
++{
++	return spi_master_get_devdata(spi->master);
++}
++
++static inline u32 rt2880_spi_read(struct rt2880_spi *rs, u32 reg)
++{
++	return ioread32(rs->base + reg);
++}
++
++static inline void rt2880_spi_write(struct rt2880_spi *rs, u32 reg,
++		const u32 val)
++{
++	iowrite32(val, rs->base + reg);
++}
++
++static inline void rt2880_spi_setbits(struct rt2880_spi *rs, u32 reg, u32 mask)
++{
++	void __iomem *addr = rs->base + reg;
++
++	iowrite32((ioread32(addr) | mask), addr);
++}
++
++static inline void rt2880_spi_clrbits(struct rt2880_spi *rs, u32 reg, u32 mask)
++{
++	void __iomem *addr = rs->base + reg;
++
++	iowrite32((ioread32(addr) & ~mask), addr);
++}
++
++static u32 rt2880_spi_baudrate_get(struct spi_device *spi, unsigned int speed)
++{
++	struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
++	u32 rate;
++	u32 prescale;
++
++	/*
++	 * the supported rates are: 2, 4, 8, ... 128
++	 * round up as we look for equal or less speed
++	 */
++	rate = DIV_ROUND_UP(clk_get_rate(rs->clk), speed);
++	rate = roundup_pow_of_two(rate);
++
++	/* Convert the rate to SPI clock divisor value.	*/
++	prescale = ilog2(rate / 2);
++
++	/* some tolerance. double and add 100 */
++	rs->wait_loops = (8 * HZ * loops_per_jiffy) /
++		(clk_get_rate(rs->clk) / rate);
++	rs->wait_loops = (rs->wait_loops << 1) + 100;
++	rs->speed = speed;
++
++	dev_dbg(&spi->dev, "speed: %lu/%u, rate: %u, prescal: %u, loops: %hu\n",
++			clk_get_rate(rs->clk) / rate, speed, rate, prescale,
++			rs->wait_loops);
++
++	return prescale;
++}
++
++static u32 get_arbiter_offset(struct spi_master *master)
++{
++	u32 offset;
++
++	offset = RAMIPS_SPI_ARBITER;
++	if (master->bus_num == 1)
++		offset -= RAMIPS_SPI_DEV_OFFSET;
++
++	return offset;
++}
++
++static void rt2880_spi_set_cs(struct spi_device *spi, bool enable)
++{
++	struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
++
++	if (enable)
++		rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
++	else
++		rt2880_spi_clrbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
++}
++
++static int rt2880_spi_wait_ready(struct rt2880_spi *rs, int len)
++{
++	int loop = rs->wait_loops * len;
++
++	while ((rt2880_spi_read(rs, RAMIPS_SPI_STAT) & SPISTAT_BUSY) && --loop)
++		cpu_relax();
++
++	if (loop)
++		return 0;
++
++	return -ETIMEDOUT;
++}
++
++static void rt2880_dump_reg(struct spi_master *master)
++{
++	struct rt2880_spi *rs = spi_master_get_devdata(master);
++
++	dev_dbg(&master->dev, "stat: %08x, cfg: %08x, ctl: %08x, " \
++			"data: %08x, arb: %08x\n",
++			rt2880_spi_read(rs, RAMIPS_SPI_STAT),
++			rt2880_spi_read(rs, RAMIPS_SPI_CFG),
++			rt2880_spi_read(rs, RAMIPS_SPI_CTL),
++			rt2880_spi_read(rs, RAMIPS_SPI_DATA),
++			rt2880_spi_read(rs, get_arbiter_offset(master)));
++}
++
++static int rt2880_spi_transfer_one(struct spi_master *master,
++		struct spi_device *spi, struct spi_transfer *xfer)
++{
++	struct rt2880_spi *rs = spi_master_get_devdata(master);
++	unsigned len;
++	const u8 *tx = xfer->tx_buf;
++	u8 *rx = xfer->rx_buf;
++	int err = 0;
++
++	/* change clock speed  */
++	if (unlikely(rs->speed != xfer->speed_hz)) {
++		u32 reg;
++		reg = rt2880_spi_read(rs, RAMIPS_SPI_CFG);
++		reg &= ~SPICFG_SPICLK_PRESCALE_MASK;
++		reg |= rt2880_spi_baudrate_get(spi, xfer->speed_hz);
++		rt2880_spi_write(rs, RAMIPS_SPI_CFG, reg);
++	}
++
++	if (tx) {
++		len = xfer->len;
++		while (len-- > 0) {
++			rt2880_spi_write(rs, RAMIPS_SPI_DATA, *tx++);
++			rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTWR);
++			err = rt2880_spi_wait_ready(rs, 1);
++			if (err) {
++				dev_err(&spi->dev, "TX failed, err=%d\n", err);
++				goto out;
++			}
++		}
++	}
++
++	if (rx) {
++		len = xfer->len;
++		while (len-- > 0) {
++			rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTRD);
++			err = rt2880_spi_wait_ready(rs, 1);
++			if (err) {
++				dev_err(&spi->dev, "RX failed, err=%d\n", err);
++				goto out;
++			}
++			*rx++ = (u8) rt2880_spi_read(rs, RAMIPS_SPI_DATA);
++		}
++	}
++
++out:
++	return err;
++}
++
++/* copy from spi.c */
++static void spi_set_cs(struct spi_device *spi, bool enable)
++{
++	if (spi->mode & SPI_CS_HIGH)
++		enable = !enable;
++
++	if (spi->cs_gpiod)
++		gpiod_set_value(spi->cs_gpiod, !enable);
++	else if (spi->master->set_cs)
++		spi->master->set_cs(spi, !enable);
++}
++
++static int rt2880_spi_setup(struct spi_device *spi)
++{
++	struct spi_master *master = spi->master;
++	struct rt2880_spi *rs = spi_master_get_devdata(master);
++	u32 reg, old_reg, arbit_off;
++
++	if ((spi->max_speed_hz > master->max_speed_hz) ||
++			(spi->max_speed_hz < master->min_speed_hz)) {
++		dev_err(&spi->dev, "invalide requested speed %d Hz\n",
++				spi->max_speed_hz);
++		return -EINVAL;
++	}
++
++	if (!(master->bits_per_word_mask &
++				BIT(spi->bits_per_word - 1))) {
++		dev_err(&spi->dev, "invalide bits_per_word %d\n",
++				spi->bits_per_word);
++		return -EINVAL;
++	}
++
++	/* the hardware seems can't work on mode0 force it to mode3 */
++	if ((spi->mode & (SPI_CPOL | SPI_CPHA)) == SPI_MODE_0) {
++		dev_warn(&spi->dev, "force spi mode3\n");
++		spi->mode |= SPI_MODE_3;
++	}
++
++	/* chip polarity */
++	arbit_off = get_arbiter_offset(master);
++	reg = old_reg = rt2880_spi_read(rs, arbit_off);
++	if (spi->mode & SPI_CS_HIGH) {
++		switch (master->bus_num) {
++		case 1:
++			reg |= SPI1_POR;
++			break;
++		default:
++			reg |= SPI0_POR;
++			break;
++		}
++	} else {
++		switch (master->bus_num) {
++		case 1:
++			reg &= ~SPI1_POR;
++			break;
++		default:
++			reg &= ~SPI0_POR;
++			break;
++		}
++	}
++
++	/* enable spi1 */
++	if (master->bus_num == 1)
++		reg |= SPICTL_ARB_EN;
++
++	if (reg != old_reg)
++		rt2880_spi_write(rs, arbit_off, reg);
++
++	/* deselected the spi device */
++	spi_set_cs(spi, false);
++
++	rt2880_dump_reg(master);
++
++	return 0;
++}
++
++static int rt2880_spi_prepare_message(struct spi_master *master,
++		struct spi_message *msg)
++{
++	struct rt2880_spi *rs = spi_master_get_devdata(master);
++	struct spi_device *spi = msg->spi;
++	u32 reg;
++
++	if ((rs->mode == spi->mode) && (rs->speed == spi->max_speed_hz))
++		return 0;
++
++#if 0
++	/* set spido to tri-state */
++	rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO);
++#endif
++
++	reg = rt2880_spi_read(rs, RAMIPS_SPI_CFG);
++
++	reg &= ~(SPICFG_MSBFIRST | SPICFG_SPICLKPOL |
++			SPICFG_RXCLKEDGE_FALLING |
++			SPICFG_TXCLKEDGE_FALLING |
++			SPICFG_SPICLK_PRESCALE_MASK);
++
++	/* MSB */
++	if (!(spi->mode & SPI_LSB_FIRST))
++		reg |= SPICFG_MSBFIRST;
++
++	/* spi mode */
++	switch (spi->mode & (SPI_CPOL | SPI_CPHA)) {
++	case SPI_MODE_0:
++		reg |= SPICFG_TXCLKEDGE_FALLING;
++		break;
++	case SPI_MODE_1:
++		reg |= SPICFG_RXCLKEDGE_FALLING;
++		break;
++	case SPI_MODE_2:
++		reg |= SPICFG_SPICLKPOL | SPICFG_RXCLKEDGE_FALLING;
++		break;
++	case SPI_MODE_3:
++		reg |= SPICFG_SPICLKPOL | SPICFG_TXCLKEDGE_FALLING;
++		break;
++	}
++	rs->mode = spi->mode;
++
++#if 0
++	/* set spiclk and spiena to tri-state */
++	reg |= SPICFG_HIZSPI;
++#endif
++
++	/* clock divide */
++	reg |= rt2880_spi_baudrate_get(spi, spi->max_speed_hz);
++
++	rt2880_spi_write(rs, RAMIPS_SPI_CFG, reg);
++
++	return 0;
++}
++
++static int rt2880_spi_probe(struct platform_device *pdev)
++{
++	struct spi_master *master;
++	struct rt2880_spi *rs;
++	void __iomem *base;
++	struct resource *r;
++	struct clk *clk;
++	int ret;
++
++	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	base = devm_ioremap_resource(&pdev->dev, r);
++	if (IS_ERR(base))
++		return PTR_ERR(base);
++
++	clk = devm_clk_get(&pdev->dev, NULL);
++	if (IS_ERR(clk)) {
++		dev_err(&pdev->dev, "unable to get SYS clock\n");
++		return PTR_ERR(clk);
++	}
++
++	ret = clk_prepare_enable(clk);
++	if (ret)
++		goto err_clk;
++
++	master = spi_alloc_master(&pdev->dev, sizeof(*rs));
++	if (master == NULL) {
++		dev_dbg(&pdev->dev, "master allocation failed\n");
++		ret = -ENOMEM;
++		goto err_clk;
++	}
++
++	master->dev.of_node = pdev->dev.of_node;
++	master->mode_bits = RT2880_SPI_MODE_BITS;
++	master->bits_per_word_mask = SPI_BPW_MASK(8);
++	master->min_speed_hz = clk_get_rate(clk) / 128;
++	master->max_speed_hz = clk_get_rate(clk) / 2;
++	master->flags = SPI_MASTER_HALF_DUPLEX;
++	master->setup = rt2880_spi_setup;
++	master->prepare_message = rt2880_spi_prepare_message;
++	master->set_cs = rt2880_spi_set_cs;
++	master->transfer_one = rt2880_spi_transfer_one,
++
++	dev_set_drvdata(&pdev->dev, master);
++
++	rs = spi_master_get_devdata(master);
++	rs->master = master;
++	rs->base = base;
++	rs->clk = clk;
++
++	if (atomic_inc_return(&hw_reset_count) == 1) {
++		ret = device_reset(&pdev->dev);
++		if (ret) {
++			dev_err(&pdev->dev, "device_reset error.\n");
++			goto err_master;
++		}
++	}
++
++	ret = devm_spi_register_master(&pdev->dev, master);
++	if (ret < 0) {
++		dev_err(&pdev->dev, "devm_spi_register_master error.\n");
++		goto err_master;
++	}
++
++	return ret;
++
++err_master:
++	spi_master_put(master);
++	kfree(master);
++err_clk:
++	clk_disable_unprepare(clk);
++
++	return ret;
++}
++
++static int rt2880_spi_remove(struct platform_device *pdev)
++{
++	struct spi_master *master;
++	struct rt2880_spi *rs;
++
++	master = dev_get_drvdata(&pdev->dev);
++	rs = spi_master_get_devdata(master);
++
++	clk_disable_unprepare(rs->clk);
++	atomic_dec(&hw_reset_count);
++
++	return 0;
++}
++
++MODULE_ALIAS("platform:" DRIVER_NAME);
++
++static const struct of_device_id rt2880_spi_match[] = {
++	{ .compatible = "ralink,rt2880-spi" },
++	{},
++};
++MODULE_DEVICE_TABLE(of, rt2880_spi_match);
++
++static struct platform_driver rt2880_spi_driver = {
++	.driver = {
++		.name = DRIVER_NAME,
++		.owner = THIS_MODULE,
++		.of_match_table = rt2880_spi_match,
++	},
++	.probe = rt2880_spi_probe,
++	.remove = rt2880_spi_remove,
++};
++
++module_platform_driver(rt2880_spi_driver);
++
++MODULE_DESCRIPTION("Ralink SPI driver");
++MODULE_AUTHOR("Sergiy <piratfm@gmail.com>");
++MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
++MODULE_LICENSE("GPL");
diff --git a/target/linux/ramips/patches-6.1/825-i2c-MIPS-adds-ralink-I2C-driver.patch b/target/linux/ramips/patches-6.1/825-i2c-MIPS-adds-ralink-I2C-driver.patch
new file mode 100644
index 00000000000000..461cf6e222423c
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/825-i2c-MIPS-adds-ralink-I2C-driver.patch
@@ -0,0 +1,512 @@
+From 723b8beaabf3c3c4b1ce69480141f1e926f3f3b2 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 27 Jul 2014 09:52:56 +0100
+Subject: [PATCH 44/53] i2c: MIPS: adds ralink I2C driver
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ .../devicetree/bindings/i2c/i2c-ralink.txt         |   27 ++
+ drivers/i2c/busses/Kconfig                         |    4 +
+ drivers/i2c/busses/Makefile                        |    1 +
+ drivers/i2c/busses/i2c-ralink.c                    |  327 ++++++++++++++++++++
+ 4 files changed, 359 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/i2c/i2c-ralink.txt
+ create mode 100644 drivers/i2c/busses/i2c-ralink.c
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/i2c/i2c-ralink.txt
+@@ -0,0 +1,27 @@
++I2C for Ralink platforms
++
++Required properties :
++- compatible : Must be "link,rt3052-i2c"
++- reg: physical base address of the controller and length of memory mapped
++     region.
++- #address-cells = <1>;
++- #size-cells = <0>;
++
++Optional properties:
++- Child nodes conforming to i2c bus binding
++
++Example :
++
++palmbus@10000000 {
++	i2c@900 {
++		compatible = "link,rt3052-i2c";
++		reg = <0x900 0x100>;
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		hwmon@4b {
++			compatible = "national,lm92";
++			reg = <0x4b>;
++		};
++	};
++};
+--- a/drivers/i2c/busses/Kconfig
++++ b/drivers/i2c/busses/Kconfig
+@@ -998,6 +998,11 @@ config I2C_RK3X
+ 	  This driver can also be built as a module. If so, the module will
+ 	  be called i2c-rk3x.
+ 
++config I2C_RALINK
++	tristate "Ralink I2C Controller"
++	depends on RALINK && !SOC_MT7621
++	select OF_I2C
++
+ config I2C_RZV2M
+ 	tristate "Renesas RZ/V2M adapter"
+ 	depends on ARCH_RENESAS || COMPILE_TEST
+--- a/drivers/i2c/busses/Makefile
++++ b/drivers/i2c/busses/Makefile
+@@ -95,6 +95,7 @@ obj-$(CONFIG_I2C_PCA_PLATFORM)	+= i2c-pc
+ obj-$(CONFIG_I2C_PNX)		+= i2c-pnx.o
+ obj-$(CONFIG_I2C_PXA)		+= i2c-pxa.o
+ obj-$(CONFIG_I2C_PXA_PCI)	+= i2c-pxa-pci.o
++obj-$(CONFIG_I2C_RALINK)	+= i2c-ralink.o
+ obj-$(CONFIG_I2C_QCOM_CCI)	+= i2c-qcom-cci.o
+ obj-$(CONFIG_I2C_QCOM_GENI)	+= i2c-qcom-geni.o
+ obj-$(CONFIG_I2C_QUP)		+= i2c-qup.o
+--- /dev/null
++++ b/drivers/i2c/busses/i2c-ralink.c
+@@ -0,0 +1,440 @@
++/*
++ * drivers/i2c/busses/i2c-ralink.c
++ *
++ * Copyright (C) 2013 Steven Liu <steven_liu@mediatek.com>
++ * Copyright (C) 2016 Michael Lee <igvtee@gmail.com>
++ *
++ * Improve driver for i2cdetect from i2c-tools to detect i2c devices on the bus.
++ * (C) 2014 Sittisak <sittisaks@hotmail.com>
++ *
++ * This software is licensed under the terms of the GNU General Public
++ * License version 2, as published by the Free Software Foundation, and
++ * may be copied, distributed, and modified under those terms.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ */
++
++#include <linux/interrupt.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/reset.h>
++#include <linux/delay.h>
++#include <linux/slab.h>
++#include <linux/init.h>
++#include <linux/errno.h>
++#include <linux/platform_device.h>
++#include <linux/of_platform.h>
++#include <linux/i2c.h>
++#include <linux/io.h>
++#include <linux/err.h>
++#include <linux/clk.h>
++
++#define REG_CONFIG_REG		0x00
++#define REG_CLKDIV_REG		0x04
++#define REG_DEVADDR_REG		0x08
++#define REG_ADDR_REG		0x0C
++#define REG_DATAOUT_REG		0x10
++#define REG_DATAIN_REG		0x14
++#define REG_STATUS_REG		0x18
++#define REG_STARTXFR_REG	0x1C
++#define REG_BYTECNT_REG		0x20
++
++/* REG_CONFIG_REG */
++#define I2C_ADDRLEN_OFFSET	5
++#define I2C_DEVADLEN_OFFSET	2
++#define I2C_ADDRLEN_MASK	0x3
++#define I2C_ADDR_DIS		BIT(1)
++#define I2C_DEVADDR_DIS		BIT(0)
++#define I2C_ADDRLEN_8		(7 << I2C_ADDRLEN_OFFSET)
++#define I2C_DEVADLEN_7		(6 << I2C_DEVADLEN_OFFSET)
++#define I2C_CONF_DEFAULT	(I2C_ADDRLEN_8 | I2C_DEVADLEN_7)
++
++/* REG_CLKDIV_REG */
++#define I2C_CLKDIV_MASK		0xffff
++
++/* REG_DEVADDR_REG */
++#define I2C_DEVADDR_MASK	0x7f
++
++/* REG_ADDR_REG */
++#define I2C_ADDR_MASK		0xff
++
++/* REG_STATUS_REG */
++#define I2C_STARTERR		BIT(4)
++#define I2C_ACKERR		BIT(3)
++#define I2C_DATARDY		BIT(2)
++#define I2C_SDOEMPTY		BIT(1)
++#define I2C_BUSY		BIT(0)
++
++/* REG_STARTXFR_REG */
++#define NOSTOP_CMD		BIT(2)
++#define NODATA_CMD		BIT(1)
++#define READ_CMD		BIT(0)
++
++/* REG_BYTECNT_REG */
++#define BYTECNT_MAX		64
++#define SET_BYTECNT(x)		(x - 1)
++
++/* timeout waiting for I2C devices to respond (clock streching) */
++#define TIMEOUT_MS              1000
++#define DELAY_INTERVAL_US       100
++
++struct rt_i2c {
++	void __iomem *base;
++	struct clk *clk;
++	struct device *dev;
++	struct i2c_adapter adap;
++	u32 cur_clk;
++	u32 clk_div;
++	u32 flags;
++};
++
++static void rt_i2c_w32(struct rt_i2c *i2c, u32 val, unsigned reg)
++{
++	iowrite32(val, i2c->base + reg);
++}
++
++static u32 rt_i2c_r32(struct rt_i2c *i2c, unsigned reg)
++{
++	return ioread32(i2c->base + reg);
++}
++
++static int poll_down_timeout(void __iomem *addr, u32 mask)
++{
++	unsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS);
++
++	do {
++		if (!(readl_relaxed(addr) & mask))
++			return 0;
++
++		usleep_range(DELAY_INTERVAL_US, DELAY_INTERVAL_US + 50);
++	} while (time_before(jiffies, timeout));
++
++	return (readl_relaxed(addr) & mask) ? -EAGAIN : 0;
++}
++
++static int rt_i2c_wait_idle(struct rt_i2c *i2c)
++{
++	int ret;
++
++	ret = poll_down_timeout(i2c->base + REG_STATUS_REG, I2C_BUSY);
++	if (ret < 0)
++		dev_dbg(i2c->dev, "idle err(%d)\n", ret);
++
++	return ret;
++}
++
++static int poll_up_timeout(void __iomem *addr, u32 mask)
++{
++	unsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS);
++	u32 status;
++
++	do {
++		status = readl_relaxed(addr);
++
++		/* check error status */
++		if (status & I2C_STARTERR)
++			return -EAGAIN;
++		else if (status & I2C_ACKERR)
++			return -ENXIO;
++		else if (status & mask)
++			return 0;
++
++		usleep_range(DELAY_INTERVAL_US, DELAY_INTERVAL_US + 50);
++	} while (time_before(jiffies, timeout));
++
++	return -ETIMEDOUT;
++}
++
++static int rt_i2c_wait_rx_done(struct rt_i2c *i2c)
++{
++	int ret;
++
++	ret = poll_up_timeout(i2c->base + REG_STATUS_REG, I2C_DATARDY);
++	if (ret < 0)
++		dev_dbg(i2c->dev, "rx err(%d)\n", ret);
++
++	return ret;
++}
++
++static int rt_i2c_wait_tx_done(struct rt_i2c *i2c)
++{
++	int ret;
++
++	ret = poll_up_timeout(i2c->base + REG_STATUS_REG, I2C_SDOEMPTY);
++	if (ret < 0)
++		dev_dbg(i2c->dev, "tx err(%d)\n", ret);
++
++	return ret;
++}
++
++static void rt_i2c_reset(struct rt_i2c *i2c)
++{
++	int ret;
++
++	ret = device_reset(i2c->adap.dev.parent);
++	if (ret)
++		dev_err(i2c->dev, "Failed to reset device");
++
++	barrier();
++	rt_i2c_w32(i2c, i2c->clk_div, REG_CLKDIV_REG);
++}
++
++static void rt_i2c_dump_reg(struct rt_i2c *i2c)
++{
++	dev_dbg(i2c->dev, "conf %08x, clkdiv %08x, devaddr %08x, " \
++			"addr %08x, dataout %08x, datain %08x, " \
++			"status %08x, startxfr %08x, bytecnt %08x\n",
++			rt_i2c_r32(i2c, REG_CONFIG_REG),
++			rt_i2c_r32(i2c, REG_CLKDIV_REG),
++			rt_i2c_r32(i2c, REG_DEVADDR_REG),
++			rt_i2c_r32(i2c, REG_ADDR_REG),
++			rt_i2c_r32(i2c, REG_DATAOUT_REG),
++			rt_i2c_r32(i2c, REG_DATAIN_REG),
++			rt_i2c_r32(i2c, REG_STATUS_REG),
++			rt_i2c_r32(i2c, REG_STARTXFR_REG),
++			rt_i2c_r32(i2c, REG_BYTECNT_REG));
++}
++
++static int rt_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
++		int num)
++{
++	struct rt_i2c *i2c;
++	struct i2c_msg *pmsg;
++	unsigned char addr;
++	int i, j, ret;
++	u32 cmd;
++
++	i2c = i2c_get_adapdata(adap);
++
++	for (i = 0; i < num; i++) {
++		pmsg = &msgs[i];
++		if (i == (num - 1))
++			cmd = 0;
++		else
++			cmd = NOSTOP_CMD;
++
++		dev_dbg(i2c->dev, "addr: 0x%x, len: %d, flags: 0x%x, stop: %d\n",
++				pmsg->addr, pmsg->len, pmsg->flags,
++				(cmd == 0)? 1 : 0);
++
++		/* wait hardware idle */
++		if ((ret = rt_i2c_wait_idle(i2c)))
++			goto err_timeout;
++
++		if (pmsg->flags & I2C_M_TEN) {
++			rt_i2c_w32(i2c, I2C_CONF_DEFAULT, REG_CONFIG_REG);
++			/* 10 bits address */
++			addr = 0x78 | ((pmsg->addr >> 8) & 0x03);
++			rt_i2c_w32(i2c, addr & I2C_DEVADDR_MASK,
++					REG_DEVADDR_REG);
++			rt_i2c_w32(i2c, pmsg->addr & I2C_ADDR_MASK,
++					REG_ADDR_REG);
++		} else {
++			rt_i2c_w32(i2c, I2C_CONF_DEFAULT | I2C_ADDR_DIS,
++					REG_CONFIG_REG);
++			/* 7 bits address */
++			rt_i2c_w32(i2c, pmsg->addr & I2C_DEVADDR_MASK,
++					REG_DEVADDR_REG);
++		}
++
++		/* buffer length */
++		if (pmsg->len == 0)
++			cmd |= NODATA_CMD;
++		else
++			rt_i2c_w32(i2c, SET_BYTECNT(pmsg->len),
++					REG_BYTECNT_REG);
++
++		j = 0;
++		if (pmsg->flags & I2C_M_RD) {
++			cmd |= READ_CMD;
++			/* start transfer */
++			barrier();
++			rt_i2c_w32(i2c, cmd, REG_STARTXFR_REG);
++			do {
++				/* wait */
++				if ((ret = rt_i2c_wait_rx_done(i2c)))
++					goto err_timeout;
++				/* read data */
++				if (pmsg->len)
++					pmsg->buf[j] = rt_i2c_r32(i2c,
++							REG_DATAIN_REG);
++				j++;
++			} while (j < pmsg->len);
++		} else {
++			do {
++				/* write data */
++				if (pmsg->len)
++					rt_i2c_w32(i2c, pmsg->buf[j],
++							REG_DATAOUT_REG);
++				/* start transfer */
++				if (j == 0) {
++					barrier();
++					rt_i2c_w32(i2c, cmd, REG_STARTXFR_REG);
++				}
++				/* wait */
++				if ((ret = rt_i2c_wait_tx_done(i2c)))
++					goto err_timeout;
++				j++;
++			} while (j < pmsg->len);
++		}
++	}
++	/* the return value is number of executed messages */
++	ret = i;
++
++	return ret;
++
++err_timeout:
++	rt_i2c_dump_reg(i2c);
++	rt_i2c_reset(i2c);
++	return ret;
++}
++
++static u32 rt_i2c_func(struct i2c_adapter *a)
++{
++	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
++}
++
++static const struct i2c_algorithm rt_i2c_algo = {
++	.master_xfer	= rt_i2c_master_xfer,
++	.functionality	= rt_i2c_func,
++};
++
++static const struct of_device_id i2c_rt_dt_ids[] = {
++	{ .compatible = "ralink,rt2880-i2c" },
++	{ /* sentinel */ }
++};
++
++MODULE_DEVICE_TABLE(of, i2c_rt_dt_ids);
++
++static struct i2c_adapter_quirks rt_i2c_quirks = {
++        .max_write_len = BYTECNT_MAX,
++        .max_read_len = BYTECNT_MAX,
++};
++
++static int rt_i2c_init(struct rt_i2c *i2c)
++{
++	u32 reg;
++
++	/* i2c_sclk = periph_clk / ((2 * clk_div) + 5) */
++	i2c->clk_div = (clk_get_rate(i2c->clk) - (5 * i2c->cur_clk)) /
++		(2 * i2c->cur_clk);
++	if (i2c->clk_div < 8)
++		i2c->clk_div = 8;
++	if (i2c->clk_div > I2C_CLKDIV_MASK)
++		i2c->clk_div = I2C_CLKDIV_MASK;
++
++	/* check support combinde/repeated start message */
++	rt_i2c_w32(i2c, NOSTOP_CMD, REG_STARTXFR_REG);
++	reg = rt_i2c_r32(i2c, REG_STARTXFR_REG) & NOSTOP_CMD;
++
++	rt_i2c_reset(i2c);
++
++	return reg;
++}
++
++static int rt_i2c_probe(struct platform_device *pdev)
++{
++	struct resource *res;
++	struct rt_i2c *i2c;
++	struct i2c_adapter *adap;
++	const struct of_device_id *match;
++	int ret, restart;
++
++	match = of_match_device(i2c_rt_dt_ids, &pdev->dev);
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if (!res) {
++		dev_err(&pdev->dev, "no memory resource found\n");
++		return -ENODEV;
++	}
++
++	i2c = devm_kzalloc(&pdev->dev, sizeof(struct rt_i2c), GFP_KERNEL);
++	if (!i2c) {
++		dev_err(&pdev->dev, "failed to allocate i2c_adapter\n");
++		return -ENOMEM;
++	}
++
++	i2c->base = devm_ioremap_resource(&pdev->dev, res);
++	if (IS_ERR(i2c->base))
++		return PTR_ERR(i2c->base);
++
++	i2c->clk = devm_clk_get(&pdev->dev, NULL);
++	if (IS_ERR(i2c->clk)) {
++		dev_err(&pdev->dev, "no clock defined\n");
++		return -ENODEV;
++	}
++	clk_prepare_enable(i2c->clk);
++	i2c->dev = &pdev->dev;
++
++	if (of_property_read_u32(pdev->dev.of_node,
++				"clock-frequency", &i2c->cur_clk))
++		i2c->cur_clk = 100000;
++
++	adap = &i2c->adap;
++	adap->owner = THIS_MODULE;
++	adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
++	adap->algo = &rt_i2c_algo;
++	adap->retries = 3;
++	adap->dev.parent = &pdev->dev;
++	i2c_set_adapdata(adap, i2c);
++	adap->dev.of_node = pdev->dev.of_node;
++	strlcpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name));
++	adap->quirks = &rt_i2c_quirks;
++
++	platform_set_drvdata(pdev, i2c);
++
++	restart = rt_i2c_init(i2c);
++
++	ret = i2c_add_adapter(adap);
++	if (ret < 0) {
++		dev_err(&pdev->dev, "failed to add adapter\n");
++		clk_disable_unprepare(i2c->clk);
++		return ret;
++	}
++
++	dev_info(&pdev->dev, "clock %uKHz, re-start %ssupport\n",
++			i2c->cur_clk/1000, restart ? "" : "not ");
++
++	return ret;
++}
++
++static int rt_i2c_remove(struct platform_device *pdev)
++{
++	struct rt_i2c *i2c = platform_get_drvdata(pdev);
++
++	i2c_del_adapter(&i2c->adap);
++	clk_disable_unprepare(i2c->clk);
++
++	return 0;
++}
++
++static struct platform_driver rt_i2c_driver = {
++	.probe		= rt_i2c_probe,
++	.remove		= rt_i2c_remove,
++	.driver		= {
++		.owner	= THIS_MODULE,
++		.name	= "i2c-ralink",
++		.of_match_table = i2c_rt_dt_ids,
++	},
++};
++
++static int __init i2c_rt_init (void)
++{
++	return platform_driver_register(&rt_i2c_driver);
++}
++subsys_initcall(i2c_rt_init);
++
++static void __exit i2c_rt_exit (void)
++{
++	platform_driver_unregister(&rt_i2c_driver);
++}
++module_exit(i2c_rt_exit);
++
++MODULE_AUTHOR("Steven Liu <steven_liu@mediatek.com>");
++MODULE_DESCRIPTION("Ralink I2c host driver");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:Ralink-I2C");
diff --git a/target/linux/ramips/patches-6.1/830-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch b/target/linux/ramips/patches-6.1/830-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch
new file mode 100644
index 00000000000000..37a10589a379a1
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/830-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch
@@ -0,0 +1,46 @@
+From 23147af14531cbdada194b94120ef8774f46292d Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 13 Nov 2014 19:08:40 +0100
+Subject: [PATCH 46/53] mmc: MIPS: ralink: add sdhci for mt7620a SoC
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/mmc/host/Kconfig             |    2 +
+ drivers/mmc/host/Makefile            |    1 +
+ drivers/mmc/host/mtk-mmc/Kconfig     |   16 +
+ drivers/mmc/host/mtk-mmc/Makefile    |   42 +
+ drivers/mmc/host/mtk-mmc/board.h     |  137 ++
+ drivers/mmc/host/mtk-mmc/dbg.c       |  347 ++++
+ drivers/mmc/host/mtk-mmc/dbg.h       |  156 ++
+ drivers/mmc/host/mtk-mmc/mt6575_sd.h | 1001 +++++++++++
+ drivers/mmc/host/mtk-mmc/sd.c        | 3060 ++++++++++++++++++++++++++++++++++
+ 9 files changed, 4762 insertions(+)
+ create mode 100644 drivers/mmc/host/mtk-mmc/Kconfig
+ create mode 100644 drivers/mmc/host/mtk-mmc/Makefile
+ create mode 100644 drivers/mmc/host/mtk-mmc/board.h
+ create mode 100644 drivers/mmc/host/mtk-mmc/dbg.c
+ create mode 100644 drivers/mmc/host/mtk-mmc/dbg.h
+ create mode 100644 drivers/mmc/host/mtk-mmc/mt6575_sd.h
+ create mode 100644 drivers/mmc/host/mtk-mmc/sd.c
+
+--- a/drivers/mmc/host/Kconfig
++++ b/drivers/mmc/host/Kconfig
+@@ -1102,6 +1102,8 @@ config MMC_OWL
+ config MMC_SDHCI_EXTERNAL_DMA
+ 	bool
+ 
++source "drivers/mmc/host/mtk-mmc/Kconfig"
++
+ config MMC_LITEX
+ 	tristate "LiteX MMC Host Controller support"
+ 	depends on ((PPC_MICROWATT || LITEX) && OF && HAVE_CLK) || COMPILE_TEST
+--- a/drivers/mmc/host/Makefile
++++ b/drivers/mmc/host/Makefile
+@@ -3,6 +3,7 @@
+ # Makefile for MMC/SD host controller drivers
+ #
+ 
++obj-$(CONFIG_MTK_MMC) 		+= mtk-mmc/
+ obj-$(CONFIG_MMC_ARMMMCI) += armmmci.o
+ armmmci-y := mmci.o
+ armmmci-$(CONFIG_MMC_QCOM_DML) += mmci_qcom_dml.o
diff --git a/target/linux/ramips/patches-6.1/835-asoc-add-mt7620-support.patch b/target/linux/ramips/patches-6.1/835-asoc-add-mt7620-support.patch
new file mode 100644
index 00000000000000..57f0ec2c506c29
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/835-asoc-add-mt7620-support.patch
@@ -0,0 +1,1031 @@
+From 7f29222b1731e8182ba94a331531dec18865a1e4 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 27 Jul 2014 09:31:47 +0100
+Subject: [PATCH 48/53] asoc: add mt7620 support
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ralink/of.c            |    2 +
+ sound/soc/Kconfig                |    1 +
+ sound/soc/Makefile               |    1 +
+ sound/soc/ralink/Kconfig         |   15 ++
+ sound/soc/ralink/Makefile        |   11 +
+ sound/soc/ralink/mt7620-i2s.c    |  436 ++++++++++++++++++++++++++++++++++++++
+ sound/soc/ralink/mt7620-wm8960.c |  233 ++++++++++++++++++++
+ 7 files changed, 699 insertions(+)
+ create mode 100644 sound/soc/ralink/Kconfig
+ create mode 100644 sound/soc/ralink/Makefile
+ create mode 100644 sound/soc/ralink/mt7620-i2s.c
+ create mode 100644 sound/soc/ralink/mt7620-wm8960.c
+
+--- a/sound/soc/Kconfig
++++ b/sound/soc/Kconfig
+@@ -86,6 +86,7 @@ source "sound/soc/mxs/Kconfig"
+ source "sound/soc/pxa/Kconfig"
+ source "sound/soc/qcom/Kconfig"
+ source "sound/soc/rockchip/Kconfig"
++source "sound/soc/ralink/Kconfig"
+ source "sound/soc/samsung/Kconfig"
+ source "sound/soc/sh/Kconfig"
+ source "sound/soc/sof/Kconfig"
+--- a/sound/soc/Makefile
++++ b/sound/soc/Makefile
+@@ -54,6 +54,7 @@ obj-$(CONFIG_SND_SOC)	+= kirkwood/
+ obj-$(CONFIG_SND_SOC)	+= pxa/
+ obj-$(CONFIG_SND_SOC)	+= qcom/
+ obj-$(CONFIG_SND_SOC)	+= rockchip/
++obj-$(CONFIG_SND_SOC)	+= ralink/
+ obj-$(CONFIG_SND_SOC)	+= samsung/
+ obj-$(CONFIG_SND_SOC)	+= sh/
+ obj-$(CONFIG_SND_SOC)	+= sof/
+--- /dev/null
++++ b/sound/soc/ralink/Kconfig
+@@ -0,0 +1,8 @@
++config SND_RALINK_SOC_I2S
++	depends on RALINK && SND_SOC && !SOC_RT288X
++	select SND_SOC_GENERIC_DMAENGINE_PCM
++	select REGMAP_MMIO
++	tristate "SoC Audio (I2S protocol) for Ralink SoC"
++	help
++	  Say Y if you want to use I2S protocol and I2S codec on Ralink/MediaTek
++	  based boards.
+--- /dev/null
++++ b/sound/soc/ralink/Makefile
+@@ -0,0 +1,6 @@
++#
++# Ralink/MediaTek Platform Support
++#
++snd-soc-ralink-i2s-objs := ralink-i2s.o
++
++obj-$(CONFIG_SND_RALINK_SOC_I2S) += snd-soc-ralink-i2s.o
+--- /dev/null
++++ b/sound/soc/ralink/ralink-i2s.c
+@@ -0,0 +1,968 @@
++/*
++ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
++ *  Copyright (C) 2016 Michael Lee <igvtee@gmail.com>
++ *
++ *  This program is free software; you can redistribute it and/or modify it
++ *  under  the terms of the GNU General  Public License as published by the
++ *  Free Software Foundation;  either version 2 of the License, or (at your
++ *  option) any later version.
++ *
++ *  You should have received a copy of the GNU General Public License along
++ *  with this program; if not, write to the Free Software Foundation, Inc.,
++ *  675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/clk.h>
++#include <linux/regmap.h>
++#include <linux/reset.h>
++#include <linux/debugfs.h>
++#include <linux/of_device.h>
++#include <sound/pcm_params.h>
++#include <sound/dmaengine_pcm.h>
++
++#include <asm/mach-ralink/ralink_regs.h>
++
++#define DRV_NAME "ralink-i2s"
++
++#define I2S_REG_CFG0		0x00
++#define I2S_REG_INT_STATUS	0x04
++#define I2S_REG_INT_EN		0x08
++#define I2S_REG_FF_STATUS	0x0c
++#define I2S_REG_WREG		0x10
++#define I2S_REG_RREG		0x14
++#define I2S_REG_CFG1		0x18
++#define I2S_REG_DIVCMP		0x20
++#define I2S_REG_DIVINT		0x24
++
++/* I2S_REG_CFG0 */
++#define I2S_REG_CFG0_EN		BIT(31)
++#define I2S_REG_CFG0_DMA_EN	BIT(30)
++#define I2S_REG_CFG0_BYTE_SWAP	BIT(28)
++#define I2S_REG_CFG0_TX_EN	BIT(24)
++#define I2S_REG_CFG0_RX_EN	BIT(20)
++#define I2S_REG_CFG0_SLAVE	BIT(16)
++#define I2S_REG_CFG0_RX_THRES	12
++#define I2S_REG_CFG0_TX_THRES	4
++#define I2S_REG_CFG0_THRES_MASK	(0xf << I2S_REG_CFG0_RX_THRES) | \
++	(4 << I2S_REG_CFG0_TX_THRES)
++#define I2S_REG_CFG0_DFT_THRES	(4 << I2S_REG_CFG0_RX_THRES) | \
++	(4 << I2S_REG_CFG0_TX_THRES)
++/* RT305x */
++#define I2S_REG_CFG0_CLK_DIS	BIT(8)
++#define I2S_REG_CFG0_TXCH_SWAP	BIT(3)
++#define I2S_REG_CFG0_TXCH1_OFF	BIT(2)
++#define I2S_REG_CFG0_TXCH0_OFF	BIT(1)
++#define I2S_REG_CFG0_SLAVE_EN	BIT(0)
++/* RT3883 */
++#define I2S_REG_CFG0_RXCH_SWAP	BIT(11)
++#define I2S_REG_CFG0_RXCH1_OFF	BIT(10)
++#define I2S_REG_CFG0_RXCH0_OFF	BIT(9)
++#define I2S_REG_CFG0_WS_INV	BIT(0)
++/* MT7628 */
++#define I2S_REG_CFG0_FMT_LE	BIT(29)
++#define I2S_REG_CFG0_SYS_BE	BIT(28)
++#define I2S_REG_CFG0_NORM_24	BIT(18)
++#define I2S_REG_CFG0_DATA_24	BIT(17)
++
++/* I2S_REG_INT_STATUS */
++#define I2S_REG_INT_RX_FAULT	BIT(7)
++#define I2S_REG_INT_RX_OVRUN	BIT(6)
++#define I2S_REG_INT_RX_UNRUN	BIT(5)
++#define I2S_REG_INT_RX_THRES	BIT(4)
++#define I2S_REG_INT_TX_FAULT	BIT(3)
++#define I2S_REG_INT_TX_OVRUN	BIT(2)
++#define I2S_REG_INT_TX_UNRUN	BIT(1)
++#define I2S_REG_INT_TX_THRES	BIT(0)
++#define I2S_REG_INT_TX_MASK	0xf
++#define I2S_REG_INT_RX_MASK	0xf0
++
++/* I2S_REG_INT_STATUS */
++#define I2S_RX_AVCNT(x)		((x >> 4) & 0xf)
++#define I2S_TX_AVCNT(x)		(x & 0xf)
++/* MT7628 */
++#define MT7628_I2S_RX_AVCNT(x)	((x >> 8) & 0x1f)
++#define MT7628_I2S_TX_AVCNT(x)	(x & 0x1f)
++
++/* I2S_REG_CFG1 */
++#define I2S_REG_CFG1_LBK	BIT(31)
++#define I2S_REG_CFG1_EXTLBK	BIT(30)
++/* RT3883 */
++#define I2S_REG_CFG1_LEFT_J	BIT(0)
++#define I2S_REG_CFG1_RIGHT_J	BIT(1)
++#define I2S_REG_CFG1_FMT_MASK	0x3
++
++/* I2S_REG_DIVCMP */
++#define I2S_REG_DIVCMP_CLKEN	BIT(31)
++#define I2S_REG_DIVCMP_DIVCOMP_MASK	0x1ff
++
++/* I2S_REG_DIVINT */
++#define I2S_REG_DIVINT_MASK	0x3ff
++
++/* BCLK dividers */
++#define RALINK_I2S_DIVCMP	0
++#define RALINK_I2S_DIVINT	1
++
++/* FIFO */
++#define RALINK_I2S_FIFO_SIZE	32
++
++/* feature flags */
++#define RALINK_FLAGS_TXONLY	BIT(0)
++#define RALINK_FLAGS_LEFT_J	BIT(1)
++#define RALINK_FLAGS_RIGHT_J	BIT(2)
++#define RALINK_FLAGS_ENDIAN	BIT(3)
++#define RALINK_FLAGS_24BIT	BIT(4)
++
++#define RALINK_I2S_INT_EN	0
++
++struct ralink_i2s_stats {
++	u32 dmafault;
++	u32 overrun;
++	u32 underrun;
++	u32 belowthres;
++};
++
++struct ralink_i2s {
++	struct device *dev;
++	void __iomem *regs;
++	struct clk *clk;
++	struct regmap *regmap;
++	u32 flags;
++	unsigned int fmt;
++	u16 txdma_req;
++	u16 rxdma_req;
++
++	struct snd_dmaengine_dai_dma_data playback_dma_data;
++	struct snd_dmaengine_dai_dma_data capture_dma_data;
++
++	struct dentry *dbg_dir;
++        struct dentry *dbg_stats;
++	struct ralink_i2s_stats txstats;
++	struct ralink_i2s_stats rxstats;
++};
++
++static void ralink_i2s_dump_regs(struct ralink_i2s *i2s)
++{
++	u32 buf[10];
++	int ret;
++
++	ret = regmap_bulk_read(i2s->regmap, I2S_REG_CFG0,
++			buf, ARRAY_SIZE(buf));
++
++	dev_dbg(i2s->dev, "CFG0: %08x, INTSTAT: %08x, INTEN: %08x, " \
++			"FFSTAT: %08x, WREG: %08x, RREG: %08x, " \
++			"CFG1: %08x, DIVCMP: %08x, DIVINT: %08x\n",
++			buf[0], buf[1], buf[2], buf[3], buf[4],
++			buf[5], buf[6], buf[8], buf[9]);
++}
++
++static int ralink_i2s_set_sysclk(struct snd_soc_dai *dai,
++                              int clk_id, unsigned int freq, int dir)
++{
++	return 0;
++}
++
++static int ralink_i2s_set_sys_bclk(struct snd_soc_dai *dai, int width, int rate)
++{
++	struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
++	unsigned long clk = clk_get_rate(i2s->clk);
++	int div;
++	uint32_t data;
++
++	/* disable clock at slave mode */
++	if ((i2s->fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
++			SND_SOC_DAIFMT_CBM_CFM) {
++		regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
++				I2S_REG_CFG0_CLK_DIS,
++				I2S_REG_CFG0_CLK_DIS);
++		return 0;
++	}
++
++	/* FREQOUT = FREQIN / (I2S_CLK_DIV + 1) */
++	div = (clk / rate ) - 1;
++
++	data = rt_sysc_r32(0x30);
++	data &= (0xff << 8);
++	data |= (0x1 << 15) | (div << 8);
++	rt_sysc_w32(data, 0x30);
++
++	/* enable clock */
++	regmap_update_bits(i2s->regmap, I2S_REG_CFG0, I2S_REG_CFG0_CLK_DIS, 0);
++
++	dev_dbg(i2s->dev, "clk: %lu, rate: %u, div: %d\n",
++			clk, rate, div);
++
++	return 0;
++}
++
++static int ralink_i2s_set_bclk(struct snd_soc_dai *dai, int width, int rate)
++{
++	struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
++	unsigned long clk = clk_get_rate(i2s->clk);
++	int divint, divcomp;
++
++	/* disable clock at slave mode */
++	if ((i2s->fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
++			SND_SOC_DAIFMT_CBM_CFM) {
++		regmap_update_bits(i2s->regmap, I2S_REG_DIVCMP,
++				I2S_REG_DIVCMP_CLKEN, 0);
++		return 0;
++	}
++
++	/* FREQOUT = FREQIN * (1/2) * (1/(DIVINT + DIVCOMP/512)) */
++	clk = clk / (2 * 2 * width);
++	divint = clk / rate;
++	divcomp = ((clk % rate) * 512) / rate;
++
++	if ((divint > I2S_REG_DIVINT_MASK) ||
++			(divcomp > I2S_REG_DIVCMP_DIVCOMP_MASK))
++		return -EINVAL;
++
++	regmap_update_bits(i2s->regmap, I2S_REG_DIVINT,
++			I2S_REG_DIVINT_MASK, divint);
++	regmap_update_bits(i2s->regmap, I2S_REG_DIVCMP,
++			I2S_REG_DIVCMP_DIVCOMP_MASK, divcomp);
++
++	/* enable clock */
++	regmap_update_bits(i2s->regmap, I2S_REG_DIVCMP, I2S_REG_DIVCMP_CLKEN,
++			I2S_REG_DIVCMP_CLKEN);
++
++	dev_dbg(i2s->dev, "clk: %lu, rate: %u, int: %d, comp: %d\n",
++			clk_get_rate(i2s->clk), rate, divint, divcomp);
++
++	return 0;
++}
++
++static int ralink_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
++{
++	struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
++	unsigned int cfg0 = 0, cfg1 = 0;
++
++	/* set master/slave audio interface */
++	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
++	case SND_SOC_DAIFMT_CBM_CFM:
++		if (i2s->flags & RALINK_FLAGS_TXONLY)
++			cfg0 |= I2S_REG_CFG0_SLAVE_EN;
++		else
++			cfg0 |= I2S_REG_CFG0_SLAVE;
++		break;
++	case SND_SOC_DAIFMT_CBS_CFS:
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	/* interface format */
++	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
++	case SND_SOC_DAIFMT_I2S:
++		break;
++	case SND_SOC_DAIFMT_RIGHT_J:
++		if (i2s->flags & RALINK_FLAGS_RIGHT_J) {
++			cfg1 |= I2S_REG_CFG1_RIGHT_J;
++			break;
++		}
++		return -EINVAL;
++	case SND_SOC_DAIFMT_LEFT_J:
++		if (i2s->flags & RALINK_FLAGS_LEFT_J) {
++			cfg1 |= I2S_REG_CFG1_LEFT_J;
++			break;
++		}
++		return -EINVAL;
++	default:
++		return -EINVAL;
++	}
++
++	/* clock inversion */
++	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
++	case SND_SOC_DAIFMT_NB_NF:
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	if (i2s->flags & RALINK_FLAGS_TXONLY) {
++		regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
++				I2S_REG_CFG0_SLAVE_EN, cfg0);
++	} else {
++		regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
++				I2S_REG_CFG0_SLAVE, cfg0);
++	}
++	regmap_update_bits(i2s->regmap, I2S_REG_CFG1,
++			I2S_REG_CFG1_FMT_MASK, cfg1);
++	i2s->fmt = fmt;
++
++	return 0;
++}
++
++static int ralink_i2s_startup(struct snd_pcm_substream *substream,
++		struct snd_soc_dai *dai)
++{
++	struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
++
++	if (snd_soc_dai_active(dai))
++		return 0;
++
++	/* setup status interrupt */
++#if (RALINK_I2S_INT_EN)
++	regmap_write(i2s->regmap, I2S_REG_INT_EN, 0xff);
++#else
++	regmap_write(i2s->regmap, I2S_REG_INT_EN, 0x0);
++#endif
++
++	/* enable */
++	regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
++			I2S_REG_CFG0_EN | I2S_REG_CFG0_DMA_EN |
++			I2S_REG_CFG0_THRES_MASK,
++			I2S_REG_CFG0_EN | I2S_REG_CFG0_DMA_EN |
++			I2S_REG_CFG0_DFT_THRES);
++
++	return 0;
++}
++
++static void ralink_i2s_shutdown(struct snd_pcm_substream *substream,
++		struct snd_soc_dai *dai)
++{
++	struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
++
++	/* If both streams are stopped, disable module and clock */
++	if (snd_soc_dai_active(dai))
++		return;
++
++	/*
++	 * datasheet mention when disable all control regs are cleared
++	 * to initial values. need reinit at startup.
++	 */
++	regmap_update_bits(i2s->regmap, I2S_REG_CFG0, I2S_REG_CFG0_EN, 0);
++}
++
++static int ralink_i2s_hw_params(struct snd_pcm_substream *substream,
++		struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
++{
++	struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
++	int width;
++	int ret;
++
++	width = params_width(params);
++	switch (width) {
++	case 16:
++		if (i2s->flags & RALINK_FLAGS_24BIT)
++			regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
++					I2S_REG_CFG0_DATA_24, 0);
++		break;
++	case 24:
++		if (i2s->flags & RALINK_FLAGS_24BIT) {
++			regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
++					I2S_REG_CFG0_DATA_24,
++					I2S_REG_CFG0_DATA_24);
++			break;
++		}
++		return -EINVAL;
++	default:
++		return -EINVAL;
++	}
++
++	switch (params_channels(params)) {
++	case 2:
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	if (i2s->flags & RALINK_FLAGS_ENDIAN) {
++		/* system endian */
++#ifdef SNDRV_LITTLE_ENDIAN
++		regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
++				I2S_REG_CFG0_SYS_BE, 0);
++#else
++		regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
++				I2S_REG_CFG0_SYS_BE,
++				I2S_REG_CFG0_SYS_BE);
++#endif
++
++		/* data endian */
++		switch (params_format(params)) {
++		case SNDRV_PCM_FORMAT_S16_LE:
++		case SNDRV_PCM_FORMAT_S24_LE:
++			regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
++					I2S_REG_CFG0_FMT_LE,
++					I2S_REG_CFG0_FMT_LE);
++			break;
++		case SNDRV_PCM_FORMAT_S16_BE:
++		case SNDRV_PCM_FORMAT_S24_BE:
++			regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
++					I2S_REG_CFG0_FMT_LE, 0);
++			break;
++		default:
++			return -EINVAL;
++		}
++	}
++
++	/* setup bclk rate */
++	if (i2s->flags & RALINK_FLAGS_TXONLY)
++		ret = ralink_i2s_set_sys_bclk(dai, width, params_rate(params));
++	else
++		ret = ralink_i2s_set_bclk(dai, width, params_rate(params));
++
++	return ret;
++}
++
++static int ralink_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
++		struct snd_soc_dai *dai)
++{
++	struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
++	unsigned int mask, val;
++
++	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++		mask = I2S_REG_CFG0_TX_EN;
++	else
++		mask = I2S_REG_CFG0_RX_EN;
++
++	switch (cmd) {
++	case SNDRV_PCM_TRIGGER_START:
++	case SNDRV_PCM_TRIGGER_RESUME:
++	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++		val = mask;
++		break;
++	case SNDRV_PCM_TRIGGER_STOP:
++	case SNDRV_PCM_TRIGGER_SUSPEND:
++	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++		val = 0;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	regmap_update_bits(i2s->regmap, I2S_REG_CFG0, mask, val);
++
++	return 0;
++}
++
++static void ralink_i2s_init_dma_data(struct ralink_i2s *i2s,
++		struct resource *res)
++{
++	struct snd_dmaengine_dai_dma_data *dma_data;
++
++	/* Playback */
++	dma_data = &i2s->playback_dma_data;
++	dma_data->addr = res->start + I2S_REG_WREG;
++	dma_data->addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
++	dma_data->maxburst = 1;
++
++	if (i2s->flags & RALINK_FLAGS_TXONLY)
++		return;
++
++	/* Capture */
++	dma_data = &i2s->capture_dma_data;
++	dma_data->addr = res->start + I2S_REG_RREG;
++	dma_data->addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
++	dma_data->maxburst = 1;
++}
++
++static int ralink_i2s_dai_probe(struct snd_soc_dai *dai)
++{
++	struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
++
++	snd_soc_dai_init_dma_data(dai, &i2s->playback_dma_data,
++			&i2s->capture_dma_data);
++
++	return 0;
++}
++
++static int ralink_i2s_dai_remove(struct snd_soc_dai *dai)
++{
++	return 0;
++}
++
++static const struct snd_soc_dai_ops ralink_i2s_dai_ops = {
++	.set_sysclk = ralink_i2s_set_sysclk,
++	.set_fmt = ralink_i2s_set_fmt,
++	.startup = ralink_i2s_startup,
++	.shutdown = ralink_i2s_shutdown,
++	.hw_params = ralink_i2s_hw_params,
++	.trigger = ralink_i2s_trigger,
++};
++
++static struct snd_soc_dai_driver ralink_i2s_dai = {
++	.name = DRV_NAME,
++	.probe = ralink_i2s_dai_probe,
++	.remove = ralink_i2s_dai_remove,
++	.ops = &ralink_i2s_dai_ops,
++	.capture = {
++		.stream_name = "I2S Capture",
++		.channels_min = 2,
++		.channels_max = 2,
++		.rate_min = 5512,
++		.rate_max = 192000,
++		.rates = SNDRV_PCM_RATE_CONTINUOUS,
++		.formats = SNDRV_PCM_FMTBIT_S16_LE,
++	},
++	.playback = {
++		.stream_name = "I2S Playback",
++		.channels_min = 2,
++		.channels_max = 2,
++		.rate_min = 5512,
++		.rate_max = 192000,
++		.rates = SNDRV_PCM_RATE_CONTINUOUS,
++		.formats = SNDRV_PCM_FMTBIT_S16_LE,
++	},
++	.symmetric_rate = 1,
++};
++
++static struct snd_pcm_hardware ralink_pcm_hardware = {
++	.info = SNDRV_PCM_INFO_MMAP |
++		SNDRV_PCM_INFO_MMAP_VALID |
++		SNDRV_PCM_INFO_INTERLEAVED |
++		SNDRV_PCM_INFO_BLOCK_TRANSFER,
++	.formats = SNDRV_PCM_FMTBIT_S16_LE,
++	.channels_min		= 2,
++	.channels_max		= 2,
++	.period_bytes_min	= PAGE_SIZE,
++	.period_bytes_max	= PAGE_SIZE * 2,
++	.periods_min		= 2,
++	.periods_max		= 128,
++	.buffer_bytes_max	= 128 * 1024,
++	.fifo_size		= RALINK_I2S_FIFO_SIZE,
++};
++
++static const struct snd_dmaengine_pcm_config ralink_dmaengine_pcm_config = {
++	.prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
++	.pcm_hardware = &ralink_pcm_hardware,
++	.prealloc_buffer_size = 256 * PAGE_SIZE,
++};
++
++static const struct snd_soc_component_driver ralink_i2s_component = {
++	.name = DRV_NAME,
++};
++
++static bool ralink_i2s_readable_reg(struct device *dev, unsigned int reg)
++{
++	return true;
++}
++
++static bool ralink_i2s_volatile_reg(struct device *dev, unsigned int reg)
++{
++	switch (reg) {
++	case I2S_REG_INT_STATUS:
++	case I2S_REG_FF_STATUS:
++		return true;
++	}
++	return false;
++}
++
++static bool ralink_i2s_writeable_reg(struct device *dev, unsigned int reg)
++{
++	switch (reg) {
++	case I2S_REG_FF_STATUS:
++	case I2S_REG_RREG:
++		return false;
++	}
++	return true;
++}
++
++static const struct regmap_config ralink_i2s_regmap_config = {
++	.reg_bits = 32,
++	.reg_stride = 4,
++	.val_bits = 32,
++	.writeable_reg = ralink_i2s_writeable_reg,
++	.readable_reg = ralink_i2s_readable_reg,
++	.volatile_reg = ralink_i2s_volatile_reg,
++	.max_register = I2S_REG_DIVINT,
++};
++
++#if (RALINK_I2S_INT_EN)
++static irqreturn_t ralink_i2s_irq(int irq, void *devid)
++{
++	struct ralink_i2s *i2s = devid;
++	u32 status;
++
++	regmap_read(i2s->regmap, I2S_REG_INT_STATUS, &status);
++	if (unlikely(!status))
++		return IRQ_NONE;
++
++	/* tx stats */
++	if (status & I2S_REG_INT_TX_MASK) {
++		if (status & I2S_REG_INT_TX_THRES)
++			i2s->txstats.belowthres++;
++		if (status & I2S_REG_INT_TX_UNRUN)
++			i2s->txstats.underrun++;
++		if (status & I2S_REG_INT_TX_OVRUN)
++			i2s->txstats.overrun++;
++		if (status & I2S_REG_INT_TX_FAULT)
++			i2s->txstats.dmafault++;
++	}
++
++	/* rx stats */
++	if (status & I2S_REG_INT_RX_MASK) {
++		if (status & I2S_REG_INT_RX_THRES)
++			i2s->rxstats.belowthres++;
++		if (status & I2S_REG_INT_RX_UNRUN)
++			i2s->rxstats.underrun++;
++		if (status & I2S_REG_INT_RX_OVRUN)
++			i2s->rxstats.overrun++;
++		if (status & I2S_REG_INT_RX_FAULT)
++			i2s->rxstats.dmafault++;
++	}
++
++	/* clean status bits */
++	regmap_write(i2s->regmap, I2S_REG_INT_STATUS, status);
++
++	return IRQ_HANDLED;
++}
++#endif
++
++#if IS_ENABLED(CONFIG_DEBUG_FS)
++static int ralink_i2s_stats_show(struct seq_file *s, void *unused)
++{
++        struct ralink_i2s *i2s = s->private;
++
++	seq_printf(s, "tx stats\n");
++	seq_printf(s, "\tbelow threshold\t%u\n", i2s->txstats.belowthres);
++	seq_printf(s, "\tunder run\t%u\n", i2s->txstats.underrun);
++	seq_printf(s, "\tover run\t%u\n", i2s->txstats.overrun);
++	seq_printf(s, "\tdma fault\t%u\n", i2s->txstats.dmafault);
++
++	seq_printf(s, "rx stats\n");
++	seq_printf(s, "\tbelow threshold\t%u\n", i2s->rxstats.belowthres);
++	seq_printf(s, "\tunder run\t%u\n", i2s->rxstats.underrun);
++	seq_printf(s, "\tover run\t%u\n", i2s->rxstats.overrun);
++	seq_printf(s, "\tdma fault\t%u\n", i2s->rxstats.dmafault);
++
++	ralink_i2s_dump_regs(i2s);
++
++	return 0;
++}
++
++static int ralink_i2s_stats_open(struct inode *inode, struct file *file)
++{
++        return single_open(file, ralink_i2s_stats_show, inode->i_private);
++}
++
++static const struct file_operations ralink_i2s_stats_ops = {
++        .open = ralink_i2s_stats_open,
++        .read = seq_read,
++        .llseek = seq_lseek,
++        .release = single_release,
++};
++
++static inline int ralink_i2s_debugfs_create(struct ralink_i2s *i2s)
++{
++        i2s->dbg_dir = debugfs_create_dir(dev_name(i2s->dev), NULL);
++        if (!i2s->dbg_dir)
++                return -ENOMEM;
++
++        i2s->dbg_stats = debugfs_create_file("stats", S_IRUGO,
++                        i2s->dbg_dir, i2s, &ralink_i2s_stats_ops);
++        if (!i2s->dbg_stats) {
++                debugfs_remove(i2s->dbg_dir);
++                return -ENOMEM;
++        }
++
++        return 0;
++}
++
++static inline void ralink_i2s_debugfs_remove(struct ralink_i2s *i2s)
++{
++	debugfs_remove(i2s->dbg_stats);
++	debugfs_remove(i2s->dbg_dir);
++}
++#else
++static inline int ralink_i2s_debugfs_create(struct ralink_i2s *i2s)
++{
++	return 0;
++}
++
++static inline void ralink_i2s_debugfs_remove(struct ralink_i2s *i2s)
++{
++}
++#endif
++
++/*
++ * TODO: these refclk setup functions should use
++ * clock framework instead. hardcode it now.
++ */
++static void rt3350_refclk_setup(void)
++{
++	uint32_t data;
++
++	/* set refclk output 12Mhz clock */
++	data = rt_sysc_r32(0x2c);
++	data |= (0x1 << 8);
++	rt_sysc_w32(data, 0x2c);
++}
++
++static void rt3883_refclk_setup(void)
++{
++	uint32_t data;
++
++	/* set refclk output 12Mhz clock */
++	data = rt_sysc_r32(0x2c);
++	data &= ~(0x3 << 13);
++	data |= (0x1 << 13);
++	rt_sysc_w32(data, 0x2c);
++}
++
++static void rt3552_refclk_setup(void)
++{
++	uint32_t data;
++
++	/* set refclk output 12Mhz clock */
++	data = rt_sysc_r32(0x2c);
++	data &= ~(0xf << 8);
++	data |= (0x3 << 8);
++	rt_sysc_w32(data, 0x2c);
++}
++
++static void mt7620_refclk_setup(void)
++{
++	uint32_t data;
++
++	/* set refclk output 12Mhz clock */
++	data = rt_sysc_r32(0x2c);
++	data &= ~(0x7 << 9);
++	data |= 0x1 << 9;
++	rt_sysc_w32(data, 0x2c);
++}
++
++static void mt7621_refclk_setup(void)
++{
++	uint32_t data;
++
++	/* set refclk output 12Mhz clock */
++	data = rt_sysc_r32(0x2c);
++	data &= ~(0x1f << 18);
++	data |= (0x19 << 18);
++	data &= ~(0x1f << 12);
++	data |= (0x1 << 12);
++	data &= ~(0x7 << 9);
++	data |= (0x5 << 9);
++	rt_sysc_w32(data, 0x2c);
++}
++
++static void mt7628_refclk_setup(void)
++{
++	uint32_t data;
++
++	/* set i2s and refclk digital pad */
++	data = rt_sysc_r32(0x3c);
++	data |= 0x1f;
++	rt_sysc_w32(data, 0x3c);
++
++	/* Adjust REFCLK0's driving strength */
++	data = rt_sysc_r32(0x1354);
++	data &= ~(0x1 << 5);
++	rt_sysc_w32(data, 0x1354);
++	data = rt_sysc_r32(0x1364);
++	data |= ~(0x1 << 5);
++	rt_sysc_w32(data, 0x1364);
++
++	/* set refclk output 12Mhz clock */
++	data = rt_sysc_r32(0x2c);
++	data &= ~(0x7 << 9);
++	data |= 0x1 << 9;
++	rt_sysc_w32(data, 0x2c);
++}
++
++struct rt_i2s_data {
++	u32 flags;
++	void (*refclk_setup)(void);
++};
++
++struct rt_i2s_data rt3050_i2s_data = { .flags = RALINK_FLAGS_TXONLY };
++struct rt_i2s_data rt3350_i2s_data = { .flags = RALINK_FLAGS_TXONLY,
++	.refclk_setup = rt3350_refclk_setup };
++struct rt_i2s_data rt3883_i2s_data = {
++	.flags = (RALINK_FLAGS_LEFT_J | RALINK_FLAGS_RIGHT_J),
++	.refclk_setup = rt3883_refclk_setup };
++struct rt_i2s_data rt3352_i2s_data = { .refclk_setup = rt3552_refclk_setup};
++struct rt_i2s_data mt7620_i2s_data = { .refclk_setup = mt7620_refclk_setup};
++struct rt_i2s_data mt7621_i2s_data = { .refclk_setup = mt7621_refclk_setup};
++struct rt_i2s_data mt7628_i2s_data = {
++	.flags = (RALINK_FLAGS_ENDIAN | RALINK_FLAGS_24BIT |
++			RALINK_FLAGS_LEFT_J),
++	.refclk_setup = mt7628_refclk_setup};
++
++static const struct of_device_id ralink_i2s_match_table[] = {
++	{ .compatible = "ralink,rt3050-i2s",
++		.data = (void *)&rt3050_i2s_data },
++	{ .compatible = "ralink,rt3350-i2s",
++		.data = (void *)&rt3350_i2s_data },
++	{ .compatible = "ralink,rt3883-i2s",
++		.data = (void *)&rt3883_i2s_data },
++	{ .compatible = "ralink,rt3352-i2s",
++		.data = (void *)&rt3352_i2s_data },
++	{ .compatible = "mediatek,mt7620-i2s",
++		.data = (void *)&mt7620_i2s_data },
++	{ .compatible = "mediatek,mt7621-i2s",
++		.data = (void *)&mt7621_i2s_data },
++	{ .compatible = "mediatek,mt7628-i2s",
++		.data = (void *)&mt7628_i2s_data },
++	{},
++};
++MODULE_DEVICE_TABLE(of, ralink_i2s_match_table);
++
++static int ralink_i2s_probe(struct platform_device *pdev)
++{
++	const struct of_device_id *match;
++	struct device_node *np = pdev->dev.of_node;
++	struct ralink_i2s *i2s;
++	struct resource *res;
++	int irq, ret;
++	u32 dma_req;
++	struct rt_i2s_data *data;
++
++	i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
++	if (!i2s)
++		return -ENOMEM;
++
++	platform_set_drvdata(pdev, i2s);
++	i2s->dev = &pdev->dev;
++
++	match = of_match_device(ralink_i2s_match_table, &pdev->dev);
++	if (!match)
++		return -EINVAL;
++	data = (struct rt_i2s_data *)match->data;
++	i2s->flags = data->flags;
++	/* setup out 12Mhz refclk to codec as mclk */
++	if (data->refclk_setup)
++		data->refclk_setup();
++
++	if (of_property_read_u32(np, "txdma-req", &dma_req)) {
++		dev_err(&pdev->dev, "no txdma-req define\n");
++		return -EINVAL;
++	}
++	i2s->txdma_req = (u16)dma_req;
++	if (!(i2s->flags & RALINK_FLAGS_TXONLY)) {
++		if (of_property_read_u32(np, "rxdma-req", &dma_req)) {
++			dev_err(&pdev->dev, "no rxdma-req define\n");
++			return -EINVAL;
++		}
++		i2s->rxdma_req = (u16)dma_req;
++	}
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	i2s->regs = devm_ioremap_resource(&pdev->dev, res);
++	if (IS_ERR(i2s->regs))
++		return PTR_ERR(i2s->regs);
++
++	i2s->regmap = devm_regmap_init_mmio(&pdev->dev, i2s->regs,
++			&ralink_i2s_regmap_config);
++	if (IS_ERR(i2s->regmap)) {
++		dev_err(&pdev->dev, "regmap init failed\n");
++		return PTR_ERR(i2s->regmap);
++	}
++
++        irq = platform_get_irq(pdev, 0);
++        if (irq < 0) {
++                dev_err(&pdev->dev, "failed to get irq\n");
++                return -EINVAL;
++        }
++
++#if (RALINK_I2S_INT_EN)
++	ret = devm_request_irq(&pdev->dev, irq, ralink_i2s_irq,
++			0, dev_name(&pdev->dev), i2s);
++	if (ret) {
++		dev_err(&pdev->dev, "failed to request irq\n");
++		return ret;
++	}
++#endif
++
++	i2s->clk = devm_clk_get(&pdev->dev, NULL);
++	if (IS_ERR(i2s->clk)) {
++		dev_err(&pdev->dev, "no clock defined\n");
++		return PTR_ERR(i2s->clk);
++	}
++
++	ret = clk_prepare_enable(i2s->clk);
++	if (ret)
++		return ret;
++
++	ralink_i2s_init_dma_data(i2s, res);
++
++	ret = device_reset(&pdev->dev);
++	if (ret) {
++		dev_err(&pdev->dev, "failed to reset device\n");
++		goto err_clk_disable;
++	}
++
++	ret = ralink_i2s_debugfs_create(i2s);
++	if (ret) {
++		dev_err(&pdev->dev, "create debugfs failed\n");
++		goto err_clk_disable;
++	}
++
++	/* enable 24bits support */
++	if (i2s->flags & RALINK_FLAGS_24BIT) {
++		ralink_i2s_dai.capture.formats |= SNDRV_PCM_FMTBIT_S24_LE;
++		ralink_i2s_dai.playback.formats |= SNDRV_PCM_FMTBIT_S24_LE;
++	}
++
++	/* enable big endian support */
++	if (i2s->flags & RALINK_FLAGS_ENDIAN) {
++		ralink_i2s_dai.capture.formats |= SNDRV_PCM_FMTBIT_S16_BE;
++		ralink_i2s_dai.playback.formats |= SNDRV_PCM_FMTBIT_S16_BE;
++		ralink_pcm_hardware.formats |= SNDRV_PCM_FMTBIT_S16_BE;
++		if (i2s->flags & RALINK_FLAGS_24BIT) {
++			ralink_i2s_dai.capture.formats |=
++				SNDRV_PCM_FMTBIT_S24_BE;
++			ralink_i2s_dai.playback.formats |=
++				SNDRV_PCM_FMTBIT_S24_BE;
++			ralink_pcm_hardware.formats |=
++				SNDRV_PCM_FMTBIT_S24_BE;
++		}
++	}
++
++	/* disable capture support */
++	if (i2s->flags & RALINK_FLAGS_TXONLY)
++		memset(&ralink_i2s_dai.capture, sizeof(ralink_i2s_dai.capture),
++				0);
++
++	ret = devm_snd_soc_register_component(&pdev->dev, &ralink_i2s_component,
++			&ralink_i2s_dai, 1);
++	if (ret)
++		goto err_debugfs;
++
++	ret = devm_snd_dmaengine_pcm_register(&pdev->dev,
++			&ralink_dmaengine_pcm_config,
++			SND_DMAENGINE_PCM_FLAG_COMPAT);
++	if (ret)
++		goto err_debugfs;
++
++	dev_info(i2s->dev, "mclk %luMHz\n", clk_get_rate(i2s->clk) / 1000000);
++
++	return 0;
++
++err_debugfs:
++	ralink_i2s_debugfs_remove(i2s);
++
++err_clk_disable:
++	clk_disable_unprepare(i2s->clk);
++
++	return ret;
++}
++
++static int ralink_i2s_remove(struct platform_device *pdev)
++{
++	struct ralink_i2s *i2s = platform_get_drvdata(pdev);
++
++	ralink_i2s_debugfs_remove(i2s);
++	clk_disable_unprepare(i2s->clk);
++
++	return 0;
++}
++
++static struct platform_driver ralink_i2s_driver = {
++	.probe = ralink_i2s_probe,
++	.remove = ralink_i2s_remove,
++	.driver = {
++		.name = DRV_NAME,
++		.of_match_table = ralink_i2s_match_table,
++	},
++};
++module_platform_driver(ralink_i2s_driver);
++
++MODULE_AUTHOR("Lars-Peter Clausen, <lars@metafoo.de>");
++MODULE_DESCRIPTION("Ralink/MediaTek I2S driver");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:" DRV_NAME);
diff --git a/target/linux/ramips/patches-6.1/840-serial-add-ugly-custom-baud-rate-hack.patch b/target/linux/ramips/patches-6.1/840-serial-add-ugly-custom-baud-rate-hack.patch
new file mode 100644
index 00000000000000..42a15a935c9567
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/840-serial-add-ugly-custom-baud-rate-hack.patch
@@ -0,0 +1,22 @@
+From a7eb46e0ea4a11e4dfb56ab129bf816d1059a6c5 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 7 Dec 2015 17:31:08 +0100
+Subject: [PATCH 51/53] serial: add ugly custom baud rate hack
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/tty/serial/serial_core.c |    3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/drivers/tty/serial/serial_core.c
++++ b/drivers/tty/serial/serial_core.c
+@@ -445,6 +445,9 @@ uart_get_baud_rate(struct uart_port *por
+ 		break;
+ 	}
+ 
++	if (tty_termios_baud_rate(termios) == 2500000)
++		return 250000;
++
+ 	for (try = 0; try < 2; try++) {
+ 		baud = tty_termios_baud_rate(termios);
+ 
diff --git a/target/linux/ramips/patches-6.1/845-pwm-add-mediatek-support.patch b/target/linux/ramips/patches-6.1/845-pwm-add-mediatek-support.patch
new file mode 100644
index 00000000000000..ab164f5ab83f4a
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/845-pwm-add-mediatek-support.patch
@@ -0,0 +1,241 @@
+From fc8f96309c21c1bc3276427309cd7d361347d66e Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 7 Dec 2015 17:16:50 +0100
+Subject: [PATCH 52/53] pwm: add mediatek support
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/pwm/Kconfig        |    9 +++
+ drivers/pwm/Makefile       |    1 +
+ drivers/pwm/pwm-mediatek.c |  173 ++++++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 183 insertions(+)
+ create mode 100644 drivers/pwm/pwm-mediatek.c
+
+--- a/drivers/pwm/Kconfig
++++ b/drivers/pwm/Kconfig
+@@ -393,6 +393,15 @@ config PWM_MEDIATEK
+ 	  To compile this driver as a module, choose M here: the module
+ 	  will be called pwm-mediatek.
+ 
++config PWM_MEDIATEK_RAMIPS
++	tristate "Mediatek PWM support"
++	depends on RALINK && OF
++	help
++	  Generic PWM framework driver for Mediatek ARM SoC.
++
++	  To compile this driver as a module, choose M here: the module
++	  will be called pwm-mxs.
++
+ config PWM_MXS
+ 	tristate "Freescale MXS PWM support"
+ 	depends on ARCH_MXS || COMPILE_TEST
+--- a/drivers/pwm/Makefile
++++ b/drivers/pwm/Makefile
+@@ -34,6 +34,7 @@ obj-$(CONFIG_PWM_LPSS_PCI)	+= pwm-lpss-p
+ obj-$(CONFIG_PWM_LPSS_PLATFORM)	+= pwm-lpss-platform.o
+ obj-$(CONFIG_PWM_MESON)		+= pwm-meson.o
+ obj-$(CONFIG_PWM_MEDIATEK)	+= pwm-mediatek.o
++obj-$(CONFIG_PWM_MEDIATEK_RAMIPS)	+= pwm-mediatek-ramips.o
+ obj-$(CONFIG_PWM_MTK_DISP)	+= pwm-mtk-disp.o
+ obj-$(CONFIG_PWM_MXS)		+= pwm-mxs.o
+ obj-$(CONFIG_PWM_NTXEC)		+= pwm-ntxec.o
+--- /dev/null
++++ b/drivers/pwm/pwm-mediatek-ramips.c
+@@ -0,0 +1,197 @@
++/*
++ * Mediatek Pulse Width Modulator driver
++ *
++ * Copyright (C) 2015 John Crispin <blogic@openwrt.org>
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2. This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/ioport.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/pwm.h>
++#include <linux/slab.h>
++#include <linux/types.h>
++
++#define NUM_PWM		4
++
++/* PWM registers and bits definitions */
++#define PWMCON			0x00
++#define PWMHDUR			0x04
++#define PWMLDUR			0x08
++#define PWMGDUR			0x0c
++#define PWMWAVENUM		0x28
++#define PWMDWIDTH		0x2c
++#define PWMTHRES		0x30
++
++/**
++ * struct mtk_pwm_chip - struct representing pwm chip
++ *
++ * @mmio_base: base address of pwm chip
++ * @chip: linux pwm chip representation
++ */
++struct mtk_pwm_chip {
++	void __iomem *mmio_base;
++	struct pwm_chip chip;
++};
++
++static inline struct mtk_pwm_chip *to_mtk_pwm_chip(struct pwm_chip *chip)
++{
++	return container_of(chip, struct mtk_pwm_chip, chip);
++}
++
++static inline u32 mtk_pwm_readl(struct mtk_pwm_chip *chip, unsigned int num,
++				  unsigned long offset)
++{
++	return ioread32(chip->mmio_base + 0x10 + (num * 0x40) + offset);
++}
++
++static inline void mtk_pwm_writel(struct mtk_pwm_chip *chip,
++				    unsigned int num, unsigned long offset,
++				    unsigned long val)
++{
++	iowrite32(val, chip->mmio_base + 0x10 + (num * 0x40) + offset);
++}
++
++static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
++			    int duty_ns, int period_ns)
++{
++	struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
++	u32 resolution = 100 / 4;
++	u32 clkdiv = 0;
++
++	while (period_ns / resolution  > 8191) {
++		clkdiv++;
++		resolution *= 2;
++	}
++
++	if (clkdiv > 7)
++		return -1;
++
++	mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | BIT(3) | clkdiv);
++	mtk_pwm_writel(pc, pwm->hwpwm, PWMDWIDTH, period_ns / resolution);
++	mtk_pwm_writel(pc, pwm->hwpwm, PWMTHRES, duty_ns / resolution);
++	return 0;
++}
++
++static int mtk_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
++{
++	struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
++	u32 val;
++
++	val = ioread32(pc->mmio_base);
++	val |= BIT(pwm->hwpwm);
++	iowrite32(val, pc->mmio_base);
++
++	return 0;
++}
++
++static void mtk_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
++{
++	struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
++	u32 val;
++
++	val = ioread32(pc->mmio_base);
++	val &= ~BIT(pwm->hwpwm);
++	iowrite32(val, pc->mmio_base);
++}
++
++static int mtk_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
++			 const struct pwm_state *state)
++{
++	int err;
++	bool enabled = pwm->state.enabled;
++
++	if (!state->enabled) {
++		if (enabled)
++			mtk_pwm_disable(chip, pwm);
++
++		return 0;
++	}
++
++	err = mtk_pwm_config(pwm->chip, pwm,
++			     state->duty_cycle, state->period);
++	if (err)
++		return err;
++
++	if (!enabled)
++		err = mtk_pwm_enable(chip, pwm);
++
++	return err;
++}
++
++static const struct pwm_ops mtk_pwm_ops = {
++	.apply = mtk_pwm_apply,
++	.owner = THIS_MODULE,
++};
++
++static int mtk_pwm_probe(struct platform_device *pdev)
++{
++	struct mtk_pwm_chip *pc;
++	struct resource *r;
++	int ret;
++
++	pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
++	if (!pc)
++		return -ENOMEM;
++
++	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	pc->mmio_base = devm_ioremap_resource(&pdev->dev, r);
++	if (IS_ERR(pc->mmio_base))
++		return PTR_ERR(pc->mmio_base);
++
++	platform_set_drvdata(pdev, pc);
++
++	pc->chip.dev = &pdev->dev;
++	pc->chip.ops = &mtk_pwm_ops;
++	pc->chip.base = -1;
++	pc->chip.npwm = NUM_PWM;
++
++	ret = pwmchip_add(&pc->chip);
++	if (ret < 0)
++		dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
++
++	return ret;
++}
++
++static int mtk_pwm_remove(struct platform_device *pdev)
++{
++	struct mtk_pwm_chip *pc = platform_get_drvdata(pdev);
++	int i;
++
++	for (i = 0; i < NUM_PWM; i++)
++		pwm_disable(&pc->chip.pwms[i]);
++
++	pwmchip_remove(&pc->chip);
++
++	return 0;
++}
++
++static const struct of_device_id mtk_pwm_of_match[] = {
++	{ .compatible = "mediatek,mt7628-pwm" },
++	{ }
++};
++
++MODULE_DEVICE_TABLE(of, mtk_pwm_of_match);
++
++static struct platform_driver mtk_pwm_driver = {
++	.driver = {
++		.name = "mtk-pwm",
++		.owner = THIS_MODULE,
++		.of_match_table = mtk_pwm_of_match,
++	},
++	.probe = mtk_pwm_probe,
++	.remove = mtk_pwm_remove,
++};
++
++module_platform_driver(mtk_pwm_driver);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
++MODULE_ALIAS("platform:mtk-pwm");
diff --git a/target/linux/ramips/patches-6.1/850-awake-rt305x-dwc2-controller.patch b/target/linux/ramips/patches-6.1/850-awake-rt305x-dwc2-controller.patch
new file mode 100644
index 00000000000000..01ce44d70007aa
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/850-awake-rt305x-dwc2-controller.patch
@@ -0,0 +1,15 @@
+--- a/drivers/usb/dwc2/platform.c
++++ b/drivers/usb/dwc2/platform.c
+@@ -462,6 +462,12 @@ static int dwc2_driver_probe(struct plat
+ 	if (retval)
+ 		return retval;
+ 
++	/* Enable USB port before any regs access */
++	if (readl(hsotg->regs + PCGCTL) & 0x0f) {
++		writel(0x00, hsotg->regs + PCGCTL);
++		/* TODO: mdelay(25) here? vendor driver don't use it */
++	}
++
+ 	hsotg->needs_byte_swap = dwc2_check_core_endianness(hsotg);
+ 
+ 	retval = dwc2_get_dr_mode(hsotg);
diff --git a/target/linux/ramips/patches-6.1/855-linkit_bootstrap.patch b/target/linux/ramips/patches-6.1/855-linkit_bootstrap.patch
new file mode 100644
index 00000000000000..cd81601a72901d
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/855-linkit_bootstrap.patch
@@ -0,0 +1,97 @@
+--- a/drivers/misc/Makefile
++++ b/drivers/misc/Makefile
+@@ -50,6 +50,7 @@ obj-$(CONFIG_ECHO)		+= echo/
+ obj-$(CONFIG_CXL_BASE)		+= cxl/
+ obj-$(CONFIG_DW_XDATA_PCIE)	+= dw-xdata-pcie.o
+ obj-$(CONFIG_PCI_ENDPOINT_TEST)	+= pci_endpoint_test.o
++obj-$(CONFIG_SOC_MT7620)	+= linkit.o
+ obj-$(CONFIG_OCXL)		+= ocxl/
+ obj-$(CONFIG_BCM_VK)		+= bcm-vk/
+ obj-y				+= cardreader/
+--- /dev/null
++++ b/drivers/misc/linkit.c
+@@ -0,0 +1,84 @@
++/*
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License version 2 as
++ *  publishhed by the Free Software Foundation.
++ *
++ *  Copyright (C) 2015 John Crispin <blogic@openwrt.org>
++ */
++
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/of.h>
++#include <linux/mtd/mtd.h>
++#include <linux/gpio.h>
++
++#define LINKIT_LATCH_GPIO	11
++
++struct linkit_hw_data {
++	char board[16];
++	char rev[16];
++};
++
++static void sanify_string(char *s)
++{
++	int i;
++
++	for (i = 0; i < 15; i++)
++		if (s[i] <= 0x20)
++			s[i] = '\0';
++	s[15] = '\0';
++}
++
++static int linkit_probe(struct platform_device *pdev)
++{
++	struct linkit_hw_data hw;
++	struct mtd_info *mtd;
++	size_t retlen;
++	int ret;
++
++	mtd = get_mtd_device_nm("factory");
++	if (IS_ERR(mtd))
++		return PTR_ERR(mtd);
++
++	ret = mtd_read(mtd, 0x400, sizeof(hw), &retlen, (u_char *) &hw);
++	put_mtd_device(mtd);
++
++	sanify_string(hw.board);
++	sanify_string(hw.rev);
++
++	dev_info(&pdev->dev, "Version  : %s\n", hw.board);
++	dev_info(&pdev->dev, "Revision : %s\n", hw.rev);
++
++	if (!strcmp(hw.board, "LINKITS7688")) {
++		dev_info(&pdev->dev, "setting up bootstrap latch\n");
++
++		if (devm_gpio_request(&pdev->dev, LINKIT_LATCH_GPIO, "bootstrap")) {
++			dev_err(&pdev->dev, "failed to setup bootstrap gpio\n");
++			return -1;
++		}
++		gpio_direction_output(LINKIT_LATCH_GPIO, 0);
++	}
++
++	return 0;
++}
++
++static const struct of_device_id linkit_match[] = {
++	{ .compatible = "mediatek,linkit" },
++	{},
++};
++MODULE_DEVICE_TABLE(of, linkit_match);
++
++static struct platform_driver linkit_driver = {
++	.probe = linkit_probe,
++	.driver = {
++		.name = "mtk-linkit",
++		.owner = THIS_MODULE,
++		.of_match_table = linkit_match,
++	},
++};
++
++int __init linkit_init(void)
++{
++	return platform_driver_register(&linkit_driver);
++}
++late_initcall_sync(linkit_init);
diff --git a/target/linux/ramips/patches-6.1/860-ramips-add-eip93-driver.patch b/target/linux/ramips/patches-6.1/860-ramips-add-eip93-driver.patch
new file mode 100644
index 00000000000000..275b81e715967d
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/860-ramips-add-eip93-driver.patch
@@ -0,0 +1,3276 @@
+--- /dev/null
++++ b/drivers/crypto/mtk-eip93/Kconfig
+@@ -0,0 +1,64 @@
++# SPDX-License-Identifier: GPL-2.0
++config CRYPTO_DEV_EIP93_SKCIPHER
++	tristate
++
++config CRYPTO_DEV_EIP93_HMAC
++	tristate
++
++config CRYPTO_DEV_EIP93
++	tristate "Support for EIP93 crypto HW accelerators"
++	depends on SOC_MT7621 || COMPILE_TEST
++	help
++	  EIP93 have various crypto HW accelerators. Select this if
++	  you want to use the EIP93 modules for any of the crypto algorithms.
++
++if CRYPTO_DEV_EIP93
++
++config CRYPTO_DEV_EIP93_AES
++	bool "Register AES algorithm implementations with the Crypto API"
++	default y
++	select CRYPTO_DEV_EIP93_SKCIPHER
++	select CRYPTO_LIB_AES
++	select CRYPTO_SKCIPHER
++	help
++	  Selecting this will offload AES - ECB, CBC and CTR crypto
++	  to the EIP-93 crypto engine.
++
++config CRYPTO_DEV_EIP93_DES
++	bool "Register legacy DES / 3DES algorithm with the Crypto API"
++	default y
++	select CRYPTO_DEV_EIP93_SKCIPHER
++	select CRYPTO_LIB_DES
++	select CRYPTO_SKCIPHER
++	help
++	  Selecting this will offload DES and 3DES ECB and CBC
++	  crypto to the EIP-93 crypto engine.
++
++config CRYPTO_DEV_EIP93_AEAD
++  	bool "Register AEAD algorithm with the Crypto API"
++  	default y
++	select CRYPTO_DEV_EIP93_HMAC
++	select CRYPTO_AEAD
++	select CRYPTO_AUTHENC
++	select CRYPTO_MD5
++	select CRYPTO_SHA1
++	select CRYPTO_SHA256
++	help
++	  Selecting this will offload AEAD authenc(hmac(x), cipher(y))
++	  crypto to the EIP-93 crypto engine.
++
++config CRYPTO_DEV_EIP93_GENERIC_SW_MAX_LEN
++	int "Max skcipher software fallback length"
++	default 256
++	help
++	  Max length of crypt request which
++	  will fallback to software crypt of skcipher *except* AES-128.
++
++config CRYPTO_DEV_EIP93_AES_128_SW_MAX_LEN
++	int "Max AES-128 skcipher software fallback length"
++	default 512
++	help
++	  Max length of crypt request which
++	  will fallback to software crypt of AES-128 skcipher.
++
++endif
+--- /dev/null
++++ b/drivers/crypto/mtk-eip93/Makefile
+@@ -0,0 +1,7 @@
++obj-$(CONFIG_CRYPTO_DEV_EIP93) += crypto-hw-eip93.o
++
++crypto-hw-eip93-y += eip93-main.o eip93-common.o
++
++crypto-hw-eip93-$(CONFIG_CRYPTO_DEV_EIP93_SKCIPHER) += eip93-cipher.o
++crypto-hw-eip93-$(CONFIG_CRYPTO_DEV_EIP93_AEAD) += eip93-aead.o
++
+--- /dev/null
++++ b/drivers/crypto/mtk-eip93/eip93-aead.c
+@@ -0,0 +1,768 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) 2019 - 2021
++ *
++ * Richard van Schagen <vschagen@icloud.com>
++ */
++
++#include <crypto/aead.h>
++#include <crypto/aes.h>
++#include <crypto/authenc.h>
++#include <crypto/ctr.h>
++#include <crypto/hmac.h>
++#include <crypto/internal/aead.h>
++#include <crypto/md5.h>
++#include <crypto/null.h>
++#include <crypto/sha1.h>
++#include <crypto/sha2.h>
++
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES)
++#include <crypto/internal/des.h>
++#endif
++
++#include <linux/crypto.h>
++#include <linux/dma-mapping.h>
++
++#include "eip93-aead.h"
++#include "eip93-cipher.h"
++#include "eip93-common.h"
++#include "eip93-regs.h"
++
++void mtk_aead_handle_result(struct crypto_async_request *async, int err)
++{
++	struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(async->tfm);
++	struct mtk_device *mtk = ctx->mtk;
++	struct aead_request *req = aead_request_cast(async);
++	struct mtk_cipher_reqctx *rctx = aead_request_ctx(req);
++
++	mtk_unmap_dma(mtk, rctx, req->src, req->dst);
++	mtk_handle_result(mtk, rctx, req->iv);
++
++	if (err == 1)
++		err = -EBADMSG;
++	/* let software handle anti-replay errors */
++	if (err == 4)
++		err = 0;
++
++	aead_request_complete(req, err);
++}
++
++static int mtk_aead_send_req(struct crypto_async_request *async)
++{
++	struct aead_request *req = aead_request_cast(async);
++	struct mtk_cipher_reqctx *rctx = aead_request_ctx(req);
++	int err;
++
++	err = check_valid_request(rctx);
++	if (err) {
++		aead_request_complete(req, err);
++		return err;
++	}
++
++	return mtk_send_req(async, req->iv, rctx);
++}
++
++/* Crypto aead API functions */
++static int mtk_aead_cra_init(struct crypto_tfm *tfm)
++{
++	struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(tfm);
++	struct mtk_alg_template *tmpl = container_of(tfm->__crt_alg,
++				struct mtk_alg_template, alg.aead.base);
++	u32 flags = tmpl->flags;
++	char *alg_base;
++
++	crypto_aead_set_reqsize(__crypto_aead_cast(tfm),
++			sizeof(struct mtk_cipher_reqctx));
++
++	ctx->mtk = tmpl->mtk;
++	ctx->in_first = true;
++	ctx->out_first = true;
++
++	ctx->sa_in = kzalloc(sizeof(struct saRecord_s), GFP_KERNEL);
++	if (!ctx->sa_in)
++		return -ENOMEM;
++
++	ctx->sa_base_in = dma_map_single(ctx->mtk->dev, ctx->sa_in,
++				sizeof(struct saRecord_s), DMA_TO_DEVICE);
++
++	ctx->sa_out = kzalloc(sizeof(struct saRecord_s), GFP_KERNEL);
++	if (!ctx->sa_out)
++		return -ENOMEM;
++
++	ctx->sa_base_out = dma_map_single(ctx->mtk->dev, ctx->sa_out,
++				sizeof(struct saRecord_s), DMA_TO_DEVICE);
++
++	/* software workaround for now */
++	if (IS_HASH_MD5(flags))
++		alg_base = "md5";
++	if (IS_HASH_SHA1(flags))
++		alg_base = "sha1";
++	if (IS_HASH_SHA224(flags))
++		alg_base = "sha224";
++	if (IS_HASH_SHA256(flags))
++		alg_base = "sha256";
++
++	ctx->shash = crypto_alloc_shash(alg_base, 0, CRYPTO_ALG_NEED_FALLBACK);
++
++	if (IS_ERR(ctx->shash)) {
++		dev_err(ctx->mtk->dev, "base driver %s could not be loaded.\n",
++				alg_base);
++		return PTR_ERR(ctx->shash);
++	}
++
++	return 0;
++}
++
++static void mtk_aead_cra_exit(struct crypto_tfm *tfm)
++{
++	struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(tfm);
++
++	if (ctx->shash)
++		crypto_free_shash(ctx->shash);
++
++	dma_unmap_single(ctx->mtk->dev, ctx->sa_base_in,
++			sizeof(struct saRecord_s), DMA_TO_DEVICE);
++	dma_unmap_single(ctx->mtk->dev, ctx->sa_base_out,
++			sizeof(struct saRecord_s), DMA_TO_DEVICE);
++	kfree(ctx->sa_in);
++	kfree(ctx->sa_out);
++}
++
++static int mtk_aead_setkey(struct crypto_aead *ctfm, const u8 *key,
++			unsigned int len)
++{
++	struct crypto_tfm *tfm = crypto_aead_tfm(ctfm);
++	struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(tfm);
++	struct mtk_alg_template *tmpl = container_of(tfm->__crt_alg,
++				struct mtk_alg_template, alg.skcipher.base);
++	u32 flags = tmpl->flags;
++	u32 nonce = 0;
++	struct crypto_authenc_keys keys;
++	struct crypto_aes_ctx aes;
++	struct saRecord_s *saRecord = ctx->sa_out;
++	int sa_size = sizeof(struct saRecord_s);
++	int err = -EINVAL;
++
++
++	if (crypto_authenc_extractkeys(&keys, key, len))
++		return err;
++
++	if (IS_RFC3686(flags)) {
++		if (keys.enckeylen < CTR_RFC3686_NONCE_SIZE)
++			return err;
++
++		keys.enckeylen -= CTR_RFC3686_NONCE_SIZE;
++		memcpy(&nonce, keys.enckey + keys.enckeylen,
++						CTR_RFC3686_NONCE_SIZE);
++	}
++
++	switch ((flags & MTK_ALG_MASK)) {
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES)
++	case MTK_ALG_DES:
++		err = verify_aead_des_key(ctfm, keys.enckey, keys.enckeylen);
++		break;
++	case MTK_ALG_3DES:
++		if (keys.enckeylen != DES3_EDE_KEY_SIZE)
++			return -EINVAL;
++
++		err = verify_aead_des3_key(ctfm, keys.enckey, keys.enckeylen);
++		break;
++#endif
++	case MTK_ALG_AES:
++		err = aes_expandkey(&aes, keys.enckey, keys.enckeylen);
++	}
++	if (err)
++		return err;
++
++	ctx->blksize = crypto_aead_blocksize(ctfm);
++	dma_unmap_single(ctx->mtk->dev, ctx->sa_base_in, sa_size,
++								DMA_TO_DEVICE);
++
++	dma_unmap_single(ctx->mtk->dev, ctx->sa_base_out, sa_size,
++								DMA_TO_DEVICE);
++	/* Encryption key */
++	mtk_set_saRecord(saRecord, keys.enckeylen, flags);
++	saRecord->saCmd0.bits.opCode = 1;
++	saRecord->saCmd0.bits.digestLength = ctx->authsize >> 2;
++
++	memcpy(saRecord->saKey, keys.enckey, keys.enckeylen);
++	ctx->saNonce = nonce;
++	saRecord->saNonce = nonce;
++
++	/* authentication key */
++	err = mtk_authenc_setkey(ctx->shash, saRecord, keys.authkey,
++							keys.authkeylen);
++
++	saRecord->saCmd0.bits.direction = 0;
++	memcpy(ctx->sa_in, saRecord, sa_size);
++	ctx->sa_in->saCmd0.bits.direction = 1;
++	ctx->sa_in->saCmd1.bits.copyDigest = 0;
++
++	ctx->sa_base_out = dma_map_single(ctx->mtk->dev, ctx->sa_out, sa_size,
++								DMA_TO_DEVICE);
++	ctx->sa_base_in = dma_map_single(ctx->mtk->dev, ctx->sa_in, sa_size,
++								DMA_TO_DEVICE);
++	ctx->in_first = true;
++	ctx->out_first = true;
++
++	return err;
++}
++
++static int mtk_aead_setauthsize(struct crypto_aead *ctfm,
++				unsigned int authsize)
++{
++	struct crypto_tfm *tfm = crypto_aead_tfm(ctfm);
++	struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(tfm);
++
++	dma_unmap_single(ctx->mtk->dev, ctx->sa_base_in,
++				sizeof(struct saRecord_s), DMA_TO_DEVICE);
++
++	dma_unmap_single(ctx->mtk->dev, ctx->sa_base_out,
++				sizeof(struct saRecord_s), DMA_TO_DEVICE);
++
++	ctx->authsize = authsize;
++	ctx->sa_in->saCmd0.bits.digestLength = ctx->authsize >> 2;
++	ctx->sa_out->saCmd0.bits.digestLength = ctx->authsize >> 2;
++
++	ctx->sa_base_out = dma_map_single(ctx->mtk->dev, ctx->sa_out,
++			sizeof(struct saRecord_s), DMA_TO_DEVICE);
++	ctx->sa_base_in = dma_map_single(ctx->mtk->dev, ctx->sa_in,
++				sizeof(struct saRecord_s), DMA_TO_DEVICE);
++	return 0;
++}
++
++static void mtk_aead_setassoc(struct mtk_crypto_ctx *ctx,
++			struct aead_request *req, bool in)
++{
++	struct saRecord_s *saRecord;
++
++	if (in) {
++		dma_unmap_single(ctx->mtk->dev, ctx->sa_base_in,
++				sizeof(struct saRecord_s), DMA_TO_DEVICE);
++		saRecord = ctx->sa_in;
++		saRecord->saCmd1.bits.hashCryptOffset = req->assoclen >> 2;
++
++		ctx->sa_base_in = dma_map_single(ctx->mtk->dev, ctx->sa_in,
++				sizeof(struct saRecord_s), DMA_TO_DEVICE);
++		ctx->assoclen_in = req->assoclen;
++	} else {
++		dma_unmap_single(ctx->mtk->dev, ctx->sa_base_out,
++				sizeof(struct saRecord_s), DMA_TO_DEVICE);
++		saRecord = ctx->sa_out;
++		saRecord->saCmd1.bits.hashCryptOffset = req->assoclen >> 2;
++
++		ctx->sa_base_out = dma_map_single(ctx->mtk->dev, ctx->sa_out,
++			sizeof(struct saRecord_s), DMA_TO_DEVICE);
++		ctx->assoclen_out = req->assoclen;
++	}
++}
++
++static int mtk_aead_crypt(struct aead_request *req)
++{
++	struct mtk_cipher_reqctx *rctx = aead_request_ctx(req);
++	struct crypto_async_request *async = &req->base;
++	struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
++	struct crypto_aead *aead = crypto_aead_reqtfm(req);
++
++	rctx->textsize = req->cryptlen;
++	rctx->blksize = ctx->blksize;
++	rctx->assoclen = req->assoclen;
++	rctx->authsize = ctx->authsize;
++	rctx->sg_src = req->src;
++	rctx->sg_dst = req->dst;
++	rctx->ivsize = crypto_aead_ivsize(aead);
++	rctx->flags |= MTK_DESC_AEAD;
++
++	if IS_DECRYPT(rctx->flags)
++		rctx->textsize -= rctx->authsize;
++
++	return mtk_aead_send_req(async);
++}
++
++static int mtk_aead_encrypt(struct aead_request *req)
++{
++	struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
++	struct mtk_cipher_reqctx *rctx = aead_request_ctx(req);
++	struct mtk_alg_template *tmpl = container_of(req->base.tfm->__crt_alg,
++				struct mtk_alg_template, alg.aead.base);
++
++	rctx->flags = tmpl->flags;
++	rctx->flags |= MTK_ENCRYPT;
++	if (ctx->out_first) {
++		mtk_aead_setassoc(ctx, req, false);
++		ctx->out_first = false;
++	}
++
++	if (req->assoclen != ctx->assoclen_out) {
++		dev_err(ctx->mtk->dev, "Request AAD length error\n");
++		return -EINVAL;
++	}
++
++	rctx->saRecord_base = ctx->sa_base_out;
++
++	return mtk_aead_crypt(req);
++}
++
++static int mtk_aead_decrypt(struct aead_request *req)
++{
++	struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
++	struct mtk_cipher_reqctx *rctx = aead_request_ctx(req);
++	struct mtk_alg_template *tmpl = container_of(req->base.tfm->__crt_alg,
++				struct mtk_alg_template, alg.aead.base);
++
++	rctx->flags = tmpl->flags;
++	rctx->flags |= MTK_DECRYPT;
++	if (ctx->in_first) {
++		mtk_aead_setassoc(ctx, req, true);
++		ctx->in_first = false;
++	}
++
++	if (req->assoclen != ctx->assoclen_in) {
++		dev_err(ctx->mtk->dev, "Request AAD length error\n");
++		return -EINVAL;
++	}
++
++	rctx->saRecord_base = ctx->sa_base_in;
++
++	return mtk_aead_crypt(req);
++}
++
++/* Available authenc algorithms in this module */
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AES)
++struct mtk_alg_template mtk_alg_authenc_hmac_md5_cbc_aes = {
++	.type = MTK_ALG_TYPE_AEAD,
++	.flags = MTK_HASH_HMAC | MTK_HASH_MD5 | MTK_MODE_CBC | MTK_ALG_AES,
++	.alg.aead = {
++		.setkey = mtk_aead_setkey,
++		.encrypt = mtk_aead_encrypt,
++		.decrypt = mtk_aead_decrypt,
++		.ivsize	= AES_BLOCK_SIZE,
++		.setauthsize = mtk_aead_setauthsize,
++		.maxauthsize = MD5_DIGEST_SIZE,
++		.base = {
++			.cra_name = "authenc(hmac(md5),cbc(aes))",
++			.cra_driver_name =
++				"authenc(hmac(md5-eip93), cbc(aes-eip93))",
++			.cra_priority = MTK_CRA_PRIORITY,
++			.cra_flags = CRYPTO_ALG_ASYNC |
++					CRYPTO_ALG_KERN_DRIVER_ONLY,
++			.cra_blocksize = AES_BLOCK_SIZE,
++			.cra_ctxsize = sizeof(struct mtk_crypto_ctx),
++			.cra_alignmask = 0,
++			.cra_init = mtk_aead_cra_init,
++			.cra_exit = mtk_aead_cra_exit,
++			.cra_module = THIS_MODULE,
++		},
++	},
++};
++
++struct mtk_alg_template mtk_alg_authenc_hmac_sha1_cbc_aes = {
++	.type = MTK_ALG_TYPE_AEAD,
++	.flags = MTK_HASH_HMAC | MTK_HASH_SHA1 | MTK_MODE_CBC | MTK_ALG_AES,
++	.alg.aead = {
++		.setkey = mtk_aead_setkey,
++		.encrypt = mtk_aead_encrypt,
++		.decrypt = mtk_aead_decrypt,
++		.ivsize	= AES_BLOCK_SIZE,
++		.setauthsize = mtk_aead_setauthsize,
++		.maxauthsize = SHA1_DIGEST_SIZE,
++		.base = {
++			.cra_name = "authenc(hmac(sha1),cbc(aes))",
++			.cra_driver_name =
++				"authenc(hmac(sha1-eip93),cbc(aes-eip93))",
++			.cra_priority = MTK_CRA_PRIORITY,
++			.cra_flags = CRYPTO_ALG_ASYNC |
++					CRYPTO_ALG_KERN_DRIVER_ONLY,
++			.cra_blocksize = AES_BLOCK_SIZE,
++			.cra_ctxsize = sizeof(struct mtk_crypto_ctx),
++			.cra_alignmask = 0,
++			.cra_init = mtk_aead_cra_init,
++			.cra_exit = mtk_aead_cra_exit,
++			.cra_module = THIS_MODULE,
++		},
++	},
++};
++
++struct mtk_alg_template mtk_alg_authenc_hmac_sha224_cbc_aes = {
++	.type = MTK_ALG_TYPE_AEAD,
++	.flags = MTK_HASH_HMAC | MTK_HASH_SHA224 | MTK_MODE_CBC | MTK_ALG_AES,
++	.alg.aead = {
++		.setkey = mtk_aead_setkey,
++		.encrypt = mtk_aead_encrypt,
++		.decrypt = mtk_aead_decrypt,
++		.ivsize	= AES_BLOCK_SIZE,
++		.setauthsize = mtk_aead_setauthsize,
++		.maxauthsize = SHA224_DIGEST_SIZE,
++		.base = {
++			.cra_name = "authenc(hmac(sha224),cbc(aes))",
++			.cra_driver_name =
++				"authenc(hmac(sha224-eip93),cbc(aes-eip93))",
++			.cra_priority = MTK_CRA_PRIORITY,
++			.cra_flags = CRYPTO_ALG_ASYNC |
++					CRYPTO_ALG_KERN_DRIVER_ONLY,
++			.cra_blocksize = AES_BLOCK_SIZE,
++			.cra_ctxsize = sizeof(struct mtk_crypto_ctx),
++			.cra_alignmask = 0,
++			.cra_init = mtk_aead_cra_init,
++			.cra_exit = mtk_aead_cra_exit,
++			.cra_module = THIS_MODULE,
++		},
++	},
++};
++
++struct mtk_alg_template mtk_alg_authenc_hmac_sha256_cbc_aes = {
++	.type = MTK_ALG_TYPE_AEAD,
++	.flags = MTK_HASH_HMAC | MTK_HASH_SHA256 | MTK_MODE_CBC | MTK_ALG_AES,
++	.alg.aead = {
++		.setkey = mtk_aead_setkey,
++		.encrypt = mtk_aead_encrypt,
++		.decrypt = mtk_aead_decrypt,
++		.ivsize	= AES_BLOCK_SIZE,
++		.setauthsize = mtk_aead_setauthsize,
++		.maxauthsize = SHA256_DIGEST_SIZE,
++		.base = {
++			.cra_name = "authenc(hmac(sha256),cbc(aes))",
++			.cra_driver_name =
++				"authenc(hmac(sha256-eip93),cbc(aes-eip93))",
++			.cra_priority = MTK_CRA_PRIORITY,
++			.cra_flags = CRYPTO_ALG_ASYNC |
++					CRYPTO_ALG_KERN_DRIVER_ONLY,
++			.cra_blocksize = AES_BLOCK_SIZE,
++			.cra_ctxsize = sizeof(struct mtk_crypto_ctx),
++			.cra_alignmask = 0,
++			.cra_init = mtk_aead_cra_init,
++			.cra_exit = mtk_aead_cra_exit,
++			.cra_module = THIS_MODULE,
++		},
++	},
++};
++
++struct mtk_alg_template mtk_alg_authenc_hmac_md5_rfc3686_aes = {
++	.type = MTK_ALG_TYPE_AEAD,
++	.flags = MTK_HASH_HMAC | MTK_HASH_MD5 |
++			MTK_MODE_CTR | MTK_MODE_RFC3686 | MTK_ALG_AES,
++	.alg.aead = {
++		.setkey = mtk_aead_setkey,
++		.encrypt = mtk_aead_encrypt,
++		.decrypt = mtk_aead_decrypt,
++		.ivsize	= CTR_RFC3686_IV_SIZE,
++		.setauthsize = mtk_aead_setauthsize,
++		.maxauthsize = MD5_DIGEST_SIZE,
++		.base = {
++			.cra_name = "authenc(hmac(md5),rfc3686(ctr(aes)))",
++			.cra_driver_name =
++			"authenc(hmac(md5-eip93),rfc3686(ctr(aes-eip93)))",
++			.cra_priority = MTK_CRA_PRIORITY,
++			.cra_flags = CRYPTO_ALG_ASYNC |
++					CRYPTO_ALG_KERN_DRIVER_ONLY,
++			.cra_blocksize = 1,
++			.cra_ctxsize = sizeof(struct mtk_crypto_ctx),
++			.cra_alignmask = 0,
++			.cra_init = mtk_aead_cra_init,
++			.cra_exit = mtk_aead_cra_exit,
++			.cra_module = THIS_MODULE,
++		},
++	},
++};
++
++struct mtk_alg_template mtk_alg_authenc_hmac_sha1_rfc3686_aes = {
++	.type = MTK_ALG_TYPE_AEAD,
++	.flags = MTK_HASH_HMAC | MTK_HASH_SHA1 |
++			MTK_MODE_CTR | MTK_MODE_RFC3686 | MTK_ALG_AES,
++	.alg.aead = {
++		.setkey = mtk_aead_setkey,
++		.encrypt = mtk_aead_encrypt,
++		.decrypt = mtk_aead_decrypt,
++		.ivsize	= CTR_RFC3686_IV_SIZE,
++		.setauthsize = mtk_aead_setauthsize,
++		.maxauthsize = SHA1_DIGEST_SIZE,
++		.base = {
++			.cra_name = "authenc(hmac(sha1),rfc3686(ctr(aes)))",
++			.cra_driver_name =
++			"authenc(hmac(sha1-eip93),rfc3686(ctr(aes-eip93)))",
++			.cra_priority = MTK_CRA_PRIORITY,
++			.cra_flags = CRYPTO_ALG_ASYNC |
++					CRYPTO_ALG_KERN_DRIVER_ONLY,
++			.cra_blocksize = 1,
++			.cra_ctxsize = sizeof(struct mtk_crypto_ctx),
++			.cra_alignmask = 0,
++			.cra_init = mtk_aead_cra_init,
++			.cra_exit = mtk_aead_cra_exit,
++			.cra_module = THIS_MODULE,
++		},
++	},
++};
++
++struct mtk_alg_template mtk_alg_authenc_hmac_sha224_rfc3686_aes = {
++	.type = MTK_ALG_TYPE_AEAD,
++	.flags = MTK_HASH_HMAC | MTK_HASH_SHA224 |
++			MTK_MODE_CTR | MTK_MODE_RFC3686 | MTK_ALG_AES,
++	.alg.aead = {
++		.setkey = mtk_aead_setkey,
++		.encrypt = mtk_aead_encrypt,
++		.decrypt = mtk_aead_decrypt,
++		.ivsize	= CTR_RFC3686_IV_SIZE,
++		.setauthsize = mtk_aead_setauthsize,
++		.maxauthsize = SHA224_DIGEST_SIZE,
++		.base = {
++			.cra_name = "authenc(hmac(sha224),rfc3686(ctr(aes)))",
++			.cra_driver_name =
++			"authenc(hmac(sha224-eip93),rfc3686(ctr(aes-eip93)))",
++			.cra_priority = MTK_CRA_PRIORITY,
++			.cra_flags = CRYPTO_ALG_ASYNC |
++					CRYPTO_ALG_KERN_DRIVER_ONLY,
++			.cra_blocksize = 1,
++			.cra_ctxsize = sizeof(struct mtk_crypto_ctx),
++			.cra_alignmask = 0,
++			.cra_init = mtk_aead_cra_init,
++			.cra_exit = mtk_aead_cra_exit,
++			.cra_module = THIS_MODULE,
++		},
++	},
++};
++
++struct mtk_alg_template mtk_alg_authenc_hmac_sha256_rfc3686_aes = {
++	.type = MTK_ALG_TYPE_AEAD,
++	.flags = MTK_HASH_HMAC | MTK_HASH_SHA256 |
++			MTK_MODE_CTR | MTK_MODE_RFC3686 | MTK_ALG_AES,
++	.alg.aead = {
++		.setkey = mtk_aead_setkey,
++		.encrypt = mtk_aead_encrypt,
++		.decrypt = mtk_aead_decrypt,
++		.ivsize	= CTR_RFC3686_IV_SIZE,
++		.setauthsize = mtk_aead_setauthsize,
++		.maxauthsize = SHA256_DIGEST_SIZE,
++		.base = {
++			.cra_name = "authenc(hmac(sha256),rfc3686(ctr(aes)))",
++			.cra_driver_name =
++			"authenc(hmac(sha256-eip93),rfc3686(ctr(aes-eip93)))",
++			.cra_priority = MTK_CRA_PRIORITY,
++			.cra_flags = CRYPTO_ALG_ASYNC |
++					CRYPTO_ALG_KERN_DRIVER_ONLY,
++			.cra_blocksize = 1,
++			.cra_ctxsize = sizeof(struct mtk_crypto_ctx),
++			.cra_alignmask = 0,
++			.cra_init = mtk_aead_cra_init,
++			.cra_exit = mtk_aead_cra_exit,
++			.cra_module = THIS_MODULE,
++		},
++	},
++};
++#endif
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES)
++struct mtk_alg_template mtk_alg_authenc_hmac_md5_cbc_des = {
++	.type = MTK_ALG_TYPE_AEAD,
++	.flags = MTK_HASH_HMAC | MTK_HASH_MD5 | MTK_MODE_CBC | MTK_ALG_DES,
++	.alg.aead = {
++		.setkey = mtk_aead_setkey,
++		.encrypt = mtk_aead_encrypt,
++		.decrypt = mtk_aead_decrypt,
++		.ivsize	= DES_BLOCK_SIZE,
++		.setauthsize = mtk_aead_setauthsize,
++		.maxauthsize = MD5_DIGEST_SIZE,
++		.base = {
++			.cra_name = "authenc(hmac(md5),cbc(des))",
++			.cra_driver_name =
++				"authenc(hmac(md5-eip93),cbc(des-eip93))",
++			.cra_priority = MTK_CRA_PRIORITY,
++			.cra_flags = CRYPTO_ALG_ASYNC |
++					CRYPTO_ALG_KERN_DRIVER_ONLY,
++			.cra_blocksize = DES_BLOCK_SIZE,
++			.cra_ctxsize = sizeof(struct mtk_crypto_ctx),
++			.cra_alignmask = 0,
++			.cra_init = mtk_aead_cra_init,
++			.cra_exit = mtk_aead_cra_exit,
++			.cra_module = THIS_MODULE,
++		},
++	},
++};
++
++struct mtk_alg_template mtk_alg_authenc_hmac_sha1_cbc_des = {
++	.type = MTK_ALG_TYPE_AEAD,
++	.flags = MTK_HASH_HMAC | MTK_HASH_SHA1 | MTK_MODE_CBC | MTK_ALG_DES,
++	.alg.aead = {
++		.setkey = mtk_aead_setkey,
++		.encrypt = mtk_aead_encrypt,
++		.decrypt = mtk_aead_decrypt,
++		.ivsize	= DES_BLOCK_SIZE,
++		.setauthsize = mtk_aead_setauthsize,
++		.maxauthsize = SHA1_DIGEST_SIZE,
++		.base = {
++			.cra_name = "authenc(hmac(sha1),cbc(des))",
++			.cra_driver_name =
++				"authenc(hmac(sha1-eip93),cbc(des-eip93))",
++			.cra_priority = MTK_CRA_PRIORITY,
++			.cra_flags = CRYPTO_ALG_ASYNC |
++					CRYPTO_ALG_KERN_DRIVER_ONLY,
++			.cra_blocksize = DES_BLOCK_SIZE,
++			.cra_ctxsize = sizeof(struct mtk_crypto_ctx),
++			.cra_alignmask = 0,
++			.cra_init = mtk_aead_cra_init,
++			.cra_exit = mtk_aead_cra_exit,
++			.cra_module = THIS_MODULE,
++		},
++	},
++};
++
++struct mtk_alg_template mtk_alg_authenc_hmac_sha224_cbc_des = {
++	.type = MTK_ALG_TYPE_AEAD,
++	.flags = MTK_HASH_HMAC | MTK_HASH_SHA224 | MTK_MODE_CBC | MTK_ALG_DES,
++	.alg.aead = {
++		.setkey = mtk_aead_setkey,
++		.encrypt = mtk_aead_encrypt,
++		.decrypt = mtk_aead_decrypt,
++		.ivsize	= DES_BLOCK_SIZE,
++		.setauthsize = mtk_aead_setauthsize,
++		.maxauthsize = SHA224_DIGEST_SIZE,
++		.base = {
++			.cra_name = "authenc(hmac(sha224),cbc(des))",
++			.cra_driver_name =
++				"authenc(hmac(sha224-eip93),cbc(des-eip93))",
++			.cra_priority = MTK_CRA_PRIORITY,
++			.cra_flags = CRYPTO_ALG_ASYNC |
++					CRYPTO_ALG_KERN_DRIVER_ONLY,
++			.cra_blocksize = DES_BLOCK_SIZE,
++			.cra_ctxsize = sizeof(struct mtk_crypto_ctx),
++			.cra_alignmask = 0,
++			.cra_init = mtk_aead_cra_init,
++			.cra_exit = mtk_aead_cra_exit,
++			.cra_module = THIS_MODULE,
++		},
++	},
++};
++
++struct mtk_alg_template mtk_alg_authenc_hmac_sha256_cbc_des = {
++	.type = MTK_ALG_TYPE_AEAD,
++	.flags = MTK_HASH_HMAC | MTK_HASH_SHA256 | MTK_MODE_CBC | MTK_ALG_DES,
++	.alg.aead = {
++		.setkey = mtk_aead_setkey,
++		.encrypt = mtk_aead_encrypt,
++		.decrypt = mtk_aead_decrypt,
++		.ivsize	= DES_BLOCK_SIZE,
++		.setauthsize = mtk_aead_setauthsize,
++		.maxauthsize = SHA256_DIGEST_SIZE,
++		.base = {
++			.cra_name = "authenc(hmac(sha256),cbc(des))",
++			.cra_driver_name =
++				"authenc(hmac(sha256-eip93),cbc(des-eip93))",
++			.cra_priority = MTK_CRA_PRIORITY,
++			.cra_flags = CRYPTO_ALG_ASYNC |
++					CRYPTO_ALG_KERN_DRIVER_ONLY,
++			.cra_blocksize = DES_BLOCK_SIZE,
++			.cra_ctxsize = sizeof(struct mtk_crypto_ctx),
++			.cra_alignmask = 0,
++			.cra_init = mtk_aead_cra_init,
++			.cra_exit = mtk_aead_cra_exit,
++			.cra_module = THIS_MODULE,
++		},
++	},
++};
++
++struct mtk_alg_template mtk_alg_authenc_hmac_md5_cbc_des3_ede = {
++	.type = MTK_ALG_TYPE_AEAD,
++	.flags = MTK_HASH_HMAC | MTK_HASH_MD5 | MTK_MODE_CBC | MTK_ALG_3DES,
++	.alg.aead = {
++		.setkey = mtk_aead_setkey,
++		.encrypt = mtk_aead_encrypt,
++		.decrypt = mtk_aead_decrypt,
++		.ivsize	= DES3_EDE_BLOCK_SIZE,
++		.setauthsize = mtk_aead_setauthsize,
++		.maxauthsize = MD5_DIGEST_SIZE,
++		.base = {
++			.cra_name = "authenc(hmac(md5),cbc(des3_ede))",
++			.cra_driver_name =
++				"authenc(hmac(md5-eip93),cbc(des3_ede-eip93))",
++			.cra_priority = MTK_CRA_PRIORITY,
++			.cra_flags = CRYPTO_ALG_ASYNC |
++					CRYPTO_ALG_KERN_DRIVER_ONLY,
++			.cra_blocksize = DES3_EDE_BLOCK_SIZE,
++			.cra_ctxsize = sizeof(struct mtk_crypto_ctx),
++			.cra_alignmask = 0x0,
++			.cra_init = mtk_aead_cra_init,
++			.cra_exit = mtk_aead_cra_exit,
++			.cra_module = THIS_MODULE,
++		},
++	},
++};
++
++struct mtk_alg_template mtk_alg_authenc_hmac_sha1_cbc_des3_ede = {
++	.type = MTK_ALG_TYPE_AEAD,
++	.flags = MTK_HASH_HMAC | MTK_HASH_SHA1 | MTK_MODE_CBC | MTK_ALG_3DES,
++	.alg.aead = {
++		.setkey = mtk_aead_setkey,
++		.encrypt = mtk_aead_encrypt,
++		.decrypt = mtk_aead_decrypt,
++		.ivsize	= DES3_EDE_BLOCK_SIZE,
++		.setauthsize = mtk_aead_setauthsize,
++		.maxauthsize = SHA1_DIGEST_SIZE,
++		.base = {
++			.cra_name = "authenc(hmac(sha1),cbc(des3_ede))",
++			.cra_driver_name =
++				"authenc(hmac(sha1-eip93),cbc(des3_ede-eip93))",
++			.cra_priority = MTK_CRA_PRIORITY,
++			.cra_flags = CRYPTO_ALG_ASYNC |
++					CRYPTO_ALG_KERN_DRIVER_ONLY,
++			.cra_blocksize = DES3_EDE_BLOCK_SIZE,
++			.cra_ctxsize = sizeof(struct mtk_crypto_ctx),
++			.cra_alignmask = 0x0,
++			.cra_init = mtk_aead_cra_init,
++			.cra_exit = mtk_aead_cra_exit,
++			.cra_module = THIS_MODULE,
++		},
++	},
++};
++
++struct mtk_alg_template mtk_alg_authenc_hmac_sha224_cbc_des3_ede = {
++	.type = MTK_ALG_TYPE_AEAD,
++	.flags = MTK_HASH_HMAC | MTK_HASH_SHA224 | MTK_MODE_CBC | MTK_ALG_3DES,
++	.alg.aead = {
++		.setkey = mtk_aead_setkey,
++		.encrypt = mtk_aead_encrypt,
++		.decrypt = mtk_aead_decrypt,
++		.ivsize	= DES3_EDE_BLOCK_SIZE,
++		.setauthsize = mtk_aead_setauthsize,
++		.maxauthsize = SHA224_DIGEST_SIZE,
++		.base = {
++			.cra_name = "authenc(hmac(sha224),cbc(des3_ede))",
++			.cra_driver_name =
++			"authenc(hmac(sha224-eip93),cbc(des3_ede-eip93))",
++			.cra_priority = MTK_CRA_PRIORITY,
++			.cra_flags = CRYPTO_ALG_ASYNC |
++					CRYPTO_ALG_KERN_DRIVER_ONLY,
++			.cra_blocksize = DES3_EDE_BLOCK_SIZE,
++			.cra_ctxsize = sizeof(struct mtk_crypto_ctx),
++			.cra_alignmask = 0x0,
++			.cra_init = mtk_aead_cra_init,
++			.cra_exit = mtk_aead_cra_exit,
++			.cra_module = THIS_MODULE,
++		},
++	},
++};
++
++struct mtk_alg_template mtk_alg_authenc_hmac_sha256_cbc_des3_ede = {
++	.type = MTK_ALG_TYPE_AEAD,
++	.flags = MTK_HASH_HMAC | MTK_HASH_SHA256 | MTK_MODE_CBC | MTK_ALG_3DES,
++	.alg.aead = {
++		.setkey = mtk_aead_setkey,
++		.encrypt = mtk_aead_encrypt,
++		.decrypt = mtk_aead_decrypt,
++		.ivsize	= DES3_EDE_BLOCK_SIZE,
++		.setauthsize = mtk_aead_setauthsize,
++		.maxauthsize = SHA256_DIGEST_SIZE,
++		.base = {
++			.cra_name = "authenc(hmac(sha256),cbc(des3_ede))",
++			.cra_driver_name =
++			"authenc(hmac(sha256-eip93),cbc(des3_ede-eip93))",
++			.cra_priority = MTK_CRA_PRIORITY,
++			.cra_flags = CRYPTO_ALG_ASYNC |
++					CRYPTO_ALG_KERN_DRIVER_ONLY,
++			.cra_blocksize = DES3_EDE_BLOCK_SIZE,
++			.cra_ctxsize = sizeof(struct mtk_crypto_ctx),
++			.cra_alignmask = 0x0,
++			.cra_init = mtk_aead_cra_init,
++			.cra_exit = mtk_aead_cra_exit,
++			.cra_module = THIS_MODULE,
++		},
++	},
++};
++#endif
+--- /dev/null
++++ b/drivers/crypto/mtk-eip93/eip93-aead.h
+@@ -0,0 +1,31 @@
++/* SPDX-License-Identifier: GPL-2.0
++ *
++ * Copyright (C) 2019 - 2021
++ *
++ * Richard van Schagen <vschagen@icloud.com>
++ */
++#ifndef _EIP93_AEAD_H_
++#define _EIP93_AEAD_H_
++
++extern struct mtk_alg_template mtk_alg_authenc_hmac_md5_cbc_aes;
++extern struct mtk_alg_template mtk_alg_authenc_hmac_sha1_cbc_aes;
++extern struct mtk_alg_template mtk_alg_authenc_hmac_sha224_cbc_aes;
++extern struct mtk_alg_template mtk_alg_authenc_hmac_sha256_cbc_aes;
++extern struct mtk_alg_template mtk_alg_authenc_hmac_md5_rfc3686_aes;
++extern struct mtk_alg_template mtk_alg_authenc_hmac_sha1_rfc3686_aes;
++extern struct mtk_alg_template mtk_alg_authenc_hmac_sha224_rfc3686_aes;
++extern struct mtk_alg_template mtk_alg_authenc_hmac_sha256_rfc3686_aes;
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES)
++extern struct mtk_alg_template mtk_alg_authenc_hmac_md5_cbc_des;
++extern struct mtk_alg_template mtk_alg_authenc_hmac_sha1_cbc_des;
++extern struct mtk_alg_template mtk_alg_authenc_hmac_sha224_cbc_des;
++extern struct mtk_alg_template mtk_alg_authenc_hmac_sha256_cbc_des;
++extern struct mtk_alg_template mtk_alg_authenc_hmac_md5_cbc_des3_ede;
++extern struct mtk_alg_template mtk_alg_authenc_hmac_sha1_cbc_des3_ede;
++extern struct mtk_alg_template mtk_alg_authenc_hmac_sha224_cbc_des3_ede;
++extern struct mtk_alg_template mtk_alg_authenc_hmac_sha256_cbc_des3_ede;
++#endif
++
++void mtk_aead_handle_result(struct crypto_async_request *async, int err);
++
++#endif /* _EIP93_AEAD_H_ */
+--- /dev/null
++++ b/drivers/crypto/mtk-eip93/eip93-aes.h
+@@ -0,0 +1,15 @@
++/* SPDX-License-Identifier: GPL-2.0
++ *
++ * Copyright (C) 2019 - 2021
++ *
++ * Richard van Schagen <vschagen@icloud.com>
++ */
++#ifndef _EIP93_AES_H_
++#define _EIP93_AES_H_
++
++extern struct mtk_alg_template mtk_alg_ecb_aes;
++extern struct mtk_alg_template mtk_alg_cbc_aes;
++extern struct mtk_alg_template mtk_alg_ctr_aes;
++extern struct mtk_alg_template mtk_alg_rfc3686_aes;
++
++#endif /* _EIP93_AES_H_ */
+--- /dev/null
++++ b/drivers/crypto/mtk-eip93/eip93-cipher.c
+@@ -0,0 +1,483 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) 2019 - 2021
++ *
++ * Richard van Schagen <vschagen@icloud.com>
++ */
++
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AES)
++#include <crypto/aes.h>
++#include <crypto/ctr.h>
++#endif
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES)
++#include <crypto/internal/des.h>
++#endif
++#include <linux/dma-mapping.h>
++
++#include "eip93-cipher.h"
++#include "eip93-common.h"
++#include "eip93-regs.h"
++
++void mtk_skcipher_handle_result(struct crypto_async_request *async, int err)
++{
++	struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(async->tfm);
++	struct mtk_device *mtk = ctx->mtk;
++	struct skcipher_request *req = skcipher_request_cast(async);
++	struct mtk_cipher_reqctx *rctx = skcipher_request_ctx(req);
++
++	mtk_unmap_dma(mtk, rctx, req->src, req->dst);
++	mtk_handle_result(mtk, rctx, req->iv);
++
++	skcipher_request_complete(req, err);
++}
++
++static inline bool mtk_skcipher_is_fallback(const struct crypto_tfm *tfm,
++					    u32 flags)
++{
++	return (tfm->__crt_alg->cra_flags & CRYPTO_ALG_NEED_FALLBACK) &&
++	       !IS_RFC3686(flags);
++}
++
++static int mtk_skcipher_send_req(struct crypto_async_request *async)
++{
++	struct skcipher_request *req = skcipher_request_cast(async);
++	struct mtk_cipher_reqctx *rctx = skcipher_request_ctx(req);
++	int err;
++
++	err = check_valid_request(rctx);
++
++	if (err) {
++		skcipher_request_complete(req, err);
++		return err;
++	}
++
++	return mtk_send_req(async, req->iv, rctx);
++}
++
++/* Crypto skcipher API functions */
++static int mtk_skcipher_cra_init(struct crypto_tfm *tfm)
++{
++	struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(tfm);
++	struct mtk_alg_template *tmpl = container_of(tfm->__crt_alg,
++				struct mtk_alg_template, alg.skcipher.base);
++	bool fallback = mtk_skcipher_is_fallback(tfm, tmpl->flags);
++
++	if (fallback) {
++		ctx->fallback = crypto_alloc_skcipher(
++			crypto_tfm_alg_name(tfm), 0, CRYPTO_ALG_NEED_FALLBACK);
++		if (IS_ERR(ctx->fallback))
++			return PTR_ERR(ctx->fallback);
++	}
++
++	crypto_skcipher_set_reqsize(
++		__crypto_skcipher_cast(tfm),
++		sizeof(struct mtk_cipher_reqctx) +
++			(fallback ? crypto_skcipher_reqsize(ctx->fallback) :
++					  0));
++
++	ctx->mtk = tmpl->mtk;
++
++	ctx->sa_in = kzalloc(sizeof(struct saRecord_s), GFP_KERNEL);
++	if (!ctx->sa_in)
++		return -ENOMEM;
++
++	ctx->sa_base_in = dma_map_single(ctx->mtk->dev, ctx->sa_in,
++				sizeof(struct saRecord_s), DMA_TO_DEVICE);
++
++	ctx->sa_out = kzalloc(sizeof(struct saRecord_s), GFP_KERNEL);
++	if (!ctx->sa_out)
++		return -ENOMEM;
++
++	ctx->sa_base_out = dma_map_single(ctx->mtk->dev, ctx->sa_out,
++				sizeof(struct saRecord_s), DMA_TO_DEVICE);
++	return 0;
++}
++
++static void mtk_skcipher_cra_exit(struct crypto_tfm *tfm)
++{
++	struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(tfm);
++
++	dma_unmap_single(ctx->mtk->dev, ctx->sa_base_in,
++			sizeof(struct saRecord_s), DMA_TO_DEVICE);
++	dma_unmap_single(ctx->mtk->dev, ctx->sa_base_out,
++			sizeof(struct saRecord_s), DMA_TO_DEVICE);
++	kfree(ctx->sa_in);
++	kfree(ctx->sa_out);
++
++	crypto_free_skcipher(ctx->fallback);
++}
++
++static int mtk_skcipher_setkey(struct crypto_skcipher *ctfm, const u8 *key,
++				 unsigned int len)
++{
++	struct crypto_tfm *tfm = crypto_skcipher_tfm(ctfm);
++	struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(tfm);
++	struct mtk_alg_template *tmpl = container_of(tfm->__crt_alg,
++				struct mtk_alg_template, alg.skcipher.base);
++	struct saRecord_s *saRecord = ctx->sa_out;
++	u32 flags = tmpl->flags;
++	u32 nonce = 0;
++	unsigned int keylen = len;
++	int sa_size = sizeof(struct saRecord_s);
++	int err = -EINVAL;
++
++	if (!key || !keylen)
++		return err;
++
++	ctx->keylen = keylen;
++
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AES)
++	if (IS_RFC3686(flags)) {
++		if (len < CTR_RFC3686_NONCE_SIZE)
++			return err;
++
++		keylen = len - CTR_RFC3686_NONCE_SIZE;
++		memcpy(&nonce, key + keylen, CTR_RFC3686_NONCE_SIZE);
++	}
++#endif
++
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES)
++	if (flags & MTK_ALG_DES) {
++		ctx->blksize = DES_BLOCK_SIZE;
++		err = verify_skcipher_des_key(ctfm, key);
++	}
++	if (flags & MTK_ALG_3DES) {
++		ctx->blksize = DES3_EDE_BLOCK_SIZE;
++		err = verify_skcipher_des3_key(ctfm, key);
++	}
++#endif
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AES)
++	if (flags & MTK_ALG_AES) {
++		struct crypto_aes_ctx aes;
++		bool fallback = mtk_skcipher_is_fallback(tfm, flags);
++
++		if (fallback && !IS_RFC3686(flags)) {
++			err = crypto_skcipher_setkey(ctx->fallback, key,
++						     keylen);
++			if (err)
++				return err;
++		}
++
++		ctx->blksize = AES_BLOCK_SIZE;
++		err = aes_expandkey(&aes, key, keylen);
++	}
++#endif
++	if (err)
++		return err;
++
++	dma_unmap_single(ctx->mtk->dev, ctx->sa_base_in, sa_size,
++								DMA_TO_DEVICE);
++
++	dma_unmap_single(ctx->mtk->dev, ctx->sa_base_out, sa_size,
++								DMA_TO_DEVICE);
++
++	mtk_set_saRecord(saRecord, keylen, flags);
++
++	memcpy(saRecord->saKey, key, keylen);
++	ctx->saNonce = nonce;
++	saRecord->saNonce = nonce;
++	saRecord->saCmd0.bits.direction = 0;
++
++	memcpy(ctx->sa_in, saRecord, sa_size);
++	ctx->sa_in->saCmd0.bits.direction = 1;
++
++	ctx->sa_base_out = dma_map_single(ctx->mtk->dev, ctx->sa_out, sa_size,
++								DMA_TO_DEVICE);
++
++	ctx->sa_base_in = dma_map_single(ctx->mtk->dev, ctx->sa_in, sa_size,
++								DMA_TO_DEVICE);
++	return err;
++}
++
++static int mtk_skcipher_crypt(struct skcipher_request *req, bool encrypt)
++{
++	struct mtk_cipher_reqctx *rctx = skcipher_request_ctx(req);
++	struct crypto_async_request *async = &req->base;
++	struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
++	struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);
++	bool fallback = mtk_skcipher_is_fallback(req->base.tfm, rctx->flags);
++
++	if (!req->cryptlen)
++		return 0;
++
++	/*
++	 * ECB and CBC algorithms require message lengths to be
++	 * multiples of block size.
++	 */
++	if (IS_ECB(rctx->flags) || IS_CBC(rctx->flags))
++		if (!IS_ALIGNED(req->cryptlen,
++				crypto_skcipher_blocksize(skcipher)))
++			return -EINVAL;
++
++	if (fallback &&
++	    req->cryptlen <= (AES_KEYSIZE_128 ?
++				      CONFIG_CRYPTO_DEV_EIP93_AES_128_SW_MAX_LEN :
++				      CONFIG_CRYPTO_DEV_EIP93_GENERIC_SW_MAX_LEN)) {
++		skcipher_request_set_tfm(&rctx->fallback_req, ctx->fallback);
++		skcipher_request_set_callback(&rctx->fallback_req,
++					      req->base.flags,
++					      req->base.complete,
++					      req->base.data);
++		skcipher_request_set_crypt(&rctx->fallback_req, req->src,
++					   req->dst, req->cryptlen, req->iv);
++		return encrypt ? crypto_skcipher_encrypt(&rctx->fallback_req) :
++				 crypto_skcipher_decrypt(&rctx->fallback_req);
++	}
++
++	rctx->assoclen = 0;
++	rctx->textsize = req->cryptlen;
++	rctx->authsize = 0;
++	rctx->sg_src = req->src;
++	rctx->sg_dst = req->dst;
++	rctx->ivsize = crypto_skcipher_ivsize(skcipher);
++	rctx->blksize = ctx->blksize;
++	rctx->flags |= MTK_DESC_SKCIPHER;
++	if (!IS_ECB(rctx->flags))
++		rctx->flags |= MTK_DESC_DMA_IV;
++
++	return mtk_skcipher_send_req(async);
++}
++
++static int mtk_skcipher_encrypt(struct skcipher_request *req)
++{
++	struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
++	struct mtk_cipher_reqctx *rctx = skcipher_request_ctx(req);
++	struct mtk_alg_template *tmpl = container_of(req->base.tfm->__crt_alg,
++				struct mtk_alg_template, alg.skcipher.base);
++
++	rctx->flags = tmpl->flags;
++	rctx->flags |= MTK_ENCRYPT;
++	rctx->saRecord_base = ctx->sa_base_out;
++
++	return mtk_skcipher_crypt(req, true);
++}
++
++static int mtk_skcipher_decrypt(struct skcipher_request *req)
++{
++	struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
++	struct mtk_cipher_reqctx *rctx = skcipher_request_ctx(req);
++	struct mtk_alg_template *tmpl = container_of(req->base.tfm->__crt_alg,
++				struct mtk_alg_template, alg.skcipher.base);
++
++	rctx->flags = tmpl->flags;
++	rctx->flags |= MTK_DECRYPT;
++	rctx->saRecord_base = ctx->sa_base_in;
++
++	return mtk_skcipher_crypt(req, false);
++}
++
++/* Available algorithms in this module */
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AES)
++struct mtk_alg_template mtk_alg_ecb_aes = {
++	.type = MTK_ALG_TYPE_SKCIPHER,
++	.flags = MTK_MODE_ECB | MTK_ALG_AES,
++	.alg.skcipher = {
++		.setkey = mtk_skcipher_setkey,
++		.encrypt = mtk_skcipher_encrypt,
++		.decrypt = mtk_skcipher_decrypt,
++		.min_keysize = AES_MIN_KEY_SIZE,
++		.max_keysize = AES_MAX_KEY_SIZE,
++		.ivsize	= 0,
++		.base = {
++			.cra_name = "ecb(aes)",
++			.cra_driver_name = "ecb(aes-eip93)",
++			.cra_priority = MTK_CRA_PRIORITY,
++			.cra_flags = CRYPTO_ALG_ASYNC |
++					CRYPTO_ALG_NEED_FALLBACK |
++					CRYPTO_ALG_KERN_DRIVER_ONLY,
++			.cra_blocksize = AES_BLOCK_SIZE,
++			.cra_ctxsize = sizeof(struct mtk_crypto_ctx),
++			.cra_alignmask = 0xf,
++			.cra_init = mtk_skcipher_cra_init,
++			.cra_exit = mtk_skcipher_cra_exit,
++			.cra_module = THIS_MODULE,
++		},
++	},
++};
++
++struct mtk_alg_template mtk_alg_cbc_aes = {
++	.type = MTK_ALG_TYPE_SKCIPHER,
++	.flags = MTK_MODE_CBC | MTK_ALG_AES,
++	.alg.skcipher = {
++		.setkey = mtk_skcipher_setkey,
++		.encrypt = mtk_skcipher_encrypt,
++		.decrypt = mtk_skcipher_decrypt,
++		.min_keysize = AES_MIN_KEY_SIZE,
++		.max_keysize = AES_MAX_KEY_SIZE,
++		.ivsize	= AES_BLOCK_SIZE,
++		.base = {
++			.cra_name = "cbc(aes)",
++			.cra_driver_name = "cbc(aes-eip93)",
++			.cra_priority = MTK_CRA_PRIORITY,
++			.cra_flags = CRYPTO_ALG_ASYNC |
++					CRYPTO_ALG_NEED_FALLBACK |
++					CRYPTO_ALG_KERN_DRIVER_ONLY,
++			.cra_blocksize = AES_BLOCK_SIZE,
++			.cra_ctxsize = sizeof(struct mtk_crypto_ctx),
++			.cra_alignmask = 0xf,
++			.cra_init = mtk_skcipher_cra_init,
++			.cra_exit = mtk_skcipher_cra_exit,
++			.cra_module = THIS_MODULE,
++		},
++	},
++};
++
++struct mtk_alg_template mtk_alg_ctr_aes = {
++	.type = MTK_ALG_TYPE_SKCIPHER,
++	.flags = MTK_MODE_CTR | MTK_ALG_AES,
++	.alg.skcipher = {
++		.setkey = mtk_skcipher_setkey,
++		.encrypt = mtk_skcipher_encrypt,
++		.decrypt = mtk_skcipher_decrypt,
++		.min_keysize = AES_MIN_KEY_SIZE,
++		.max_keysize = AES_MAX_KEY_SIZE,
++		.ivsize	= AES_BLOCK_SIZE,
++		.base = {
++			.cra_name = "ctr(aes)",
++			.cra_driver_name = "ctr(aes-eip93)",
++			.cra_priority = MTK_CRA_PRIORITY,
++			.cra_flags = CRYPTO_ALG_ASYNC |
++				     CRYPTO_ALG_NEED_FALLBACK |
++				     CRYPTO_ALG_KERN_DRIVER_ONLY,
++			.cra_blocksize = 1,
++			.cra_ctxsize = sizeof(struct mtk_crypto_ctx),
++			.cra_alignmask = 0xf,
++			.cra_init = mtk_skcipher_cra_init,
++			.cra_exit = mtk_skcipher_cra_exit,
++			.cra_module = THIS_MODULE,
++		},
++	},
++};
++
++struct mtk_alg_template mtk_alg_rfc3686_aes = {
++	.type = MTK_ALG_TYPE_SKCIPHER,
++	.flags = MTK_MODE_CTR | MTK_MODE_RFC3686 | MTK_ALG_AES,
++	.alg.skcipher = {
++		.setkey = mtk_skcipher_setkey,
++		.encrypt = mtk_skcipher_encrypt,
++		.decrypt = mtk_skcipher_decrypt,
++		.min_keysize = AES_MIN_KEY_SIZE + CTR_RFC3686_NONCE_SIZE,
++		.max_keysize = AES_MAX_KEY_SIZE + CTR_RFC3686_NONCE_SIZE,
++		.ivsize	= CTR_RFC3686_IV_SIZE,
++		.base = {
++			.cra_name = "rfc3686(ctr(aes))",
++			.cra_driver_name = "rfc3686(ctr(aes-eip93))",
++			.cra_priority = MTK_CRA_PRIORITY,
++			.cra_flags = CRYPTO_ALG_ASYNC |
++					CRYPTO_ALG_NEED_FALLBACK |
++					CRYPTO_ALG_KERN_DRIVER_ONLY,
++			.cra_blocksize = 1,
++			.cra_ctxsize = sizeof(struct mtk_crypto_ctx),
++			.cra_alignmask = 0xf,
++			.cra_init = mtk_skcipher_cra_init,
++			.cra_exit = mtk_skcipher_cra_exit,
++			.cra_module = THIS_MODULE,
++		},
++	},
++};
++#endif
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES)
++struct mtk_alg_template mtk_alg_ecb_des = {
++	.type = MTK_ALG_TYPE_SKCIPHER,
++	.flags = MTK_MODE_ECB | MTK_ALG_DES,
++	.alg.skcipher = {
++		.setkey = mtk_skcipher_setkey,
++		.encrypt = mtk_skcipher_encrypt,
++		.decrypt = mtk_skcipher_decrypt,
++		.min_keysize = DES_KEY_SIZE,
++		.max_keysize = DES_KEY_SIZE,
++		.ivsize	= 0,
++		.base = {
++			.cra_name = "ecb(des)",
++			.cra_driver_name = "ebc(des-eip93)",
++			.cra_priority = MTK_CRA_PRIORITY,
++			.cra_flags = CRYPTO_ALG_ASYNC |
++					CRYPTO_ALG_KERN_DRIVER_ONLY,
++			.cra_blocksize = DES_BLOCK_SIZE,
++			.cra_ctxsize = sizeof(struct mtk_crypto_ctx),
++			.cra_alignmask = 0,
++			.cra_init = mtk_skcipher_cra_init,
++			.cra_exit = mtk_skcipher_cra_exit,
++			.cra_module = THIS_MODULE,
++		},
++	},
++};
++
++struct mtk_alg_template mtk_alg_cbc_des = {
++	.type = MTK_ALG_TYPE_SKCIPHER,
++	.flags = MTK_MODE_CBC | MTK_ALG_DES,
++	.alg.skcipher = {
++		.setkey = mtk_skcipher_setkey,
++		.encrypt = mtk_skcipher_encrypt,
++		.decrypt = mtk_skcipher_decrypt,
++		.min_keysize = DES_KEY_SIZE,
++		.max_keysize = DES_KEY_SIZE,
++		.ivsize	= DES_BLOCK_SIZE,
++		.base = {
++			.cra_name = "cbc(des)",
++			.cra_driver_name = "cbc(des-eip93)",
++			.cra_priority = MTK_CRA_PRIORITY,
++			.cra_flags = CRYPTO_ALG_ASYNC |
++					CRYPTO_ALG_KERN_DRIVER_ONLY,
++			.cra_blocksize = DES_BLOCK_SIZE,
++			.cra_ctxsize = sizeof(struct mtk_crypto_ctx),
++			.cra_alignmask = 0,
++			.cra_init = mtk_skcipher_cra_init,
++			.cra_exit = mtk_skcipher_cra_exit,
++			.cra_module = THIS_MODULE,
++		},
++	},
++};
++
++struct mtk_alg_template mtk_alg_ecb_des3_ede = {
++	.type = MTK_ALG_TYPE_SKCIPHER,
++	.flags = MTK_MODE_ECB | MTK_ALG_3DES,
++	.alg.skcipher = {
++		.setkey = mtk_skcipher_setkey,
++		.encrypt = mtk_skcipher_encrypt,
++		.decrypt = mtk_skcipher_decrypt,
++		.min_keysize = DES3_EDE_KEY_SIZE,
++		.max_keysize = DES3_EDE_KEY_SIZE,
++		.ivsize	= 0,
++		.base = {
++			.cra_name = "ecb(des3_ede)",
++			.cra_driver_name = "ecb(des3_ede-eip93)",
++			.cra_priority = MTK_CRA_PRIORITY,
++			.cra_flags = CRYPTO_ALG_ASYNC |
++					CRYPTO_ALG_KERN_DRIVER_ONLY,
++			.cra_blocksize = DES3_EDE_BLOCK_SIZE,
++			.cra_ctxsize = sizeof(struct mtk_crypto_ctx),
++			.cra_alignmask = 0,
++			.cra_init = mtk_skcipher_cra_init,
++			.cra_exit = mtk_skcipher_cra_exit,
++			.cra_module = THIS_MODULE,
++		},
++	},
++};
++
++struct mtk_alg_template mtk_alg_cbc_des3_ede = {
++	.type = MTK_ALG_TYPE_SKCIPHER,
++	.flags = MTK_MODE_CBC | MTK_ALG_3DES,
++	.alg.skcipher = {
++		.setkey = mtk_skcipher_setkey,
++		.encrypt = mtk_skcipher_encrypt,
++		.decrypt = mtk_skcipher_decrypt,
++		.min_keysize = DES3_EDE_KEY_SIZE,
++		.max_keysize = DES3_EDE_KEY_SIZE,
++		.ivsize	= DES3_EDE_BLOCK_SIZE,
++		.base = {
++			.cra_name = "cbc(des3_ede)",
++			.cra_driver_name = "cbc(des3_ede-eip93)",
++			.cra_priority = MTK_CRA_PRIORITY,
++			.cra_flags = CRYPTO_ALG_ASYNC |
++					CRYPTO_ALG_KERN_DRIVER_ONLY,
++			.cra_blocksize = DES3_EDE_BLOCK_SIZE,
++			.cra_ctxsize = sizeof(struct mtk_crypto_ctx),
++			.cra_alignmask = 0,
++			.cra_init = mtk_skcipher_cra_init,
++			.cra_exit = mtk_skcipher_cra_exit,
++			.cra_module = THIS_MODULE,
++		},
++	},
++};
++#endif
+--- /dev/null
++++ b/drivers/crypto/mtk-eip93/eip93-cipher.h
+@@ -0,0 +1,66 @@
++/* SPDX-License-Identifier: GPL-2.0
++ *
++ * Copyright (C) 2019 - 2021
++ *
++ * Richard van Schagen <vschagen@icloud.com>
++ */
++#ifndef _EIP93_CIPHER_H_
++#define _EIP93_CIPHER_H_
++
++#include "eip93-main.h"
++
++struct mtk_crypto_ctx {
++	struct mtk_device		*mtk;
++	struct saRecord_s		*sa_in;
++	dma_addr_t			sa_base_in;
++	struct saRecord_s		*sa_out;
++	dma_addr_t			sa_base_out;
++	uint32_t			saNonce;
++	int				blksize;
++	/* AEAD specific */
++	unsigned int			authsize;
++	unsigned int			assoclen_in;
++	unsigned int			assoclen_out;
++	bool				in_first;
++	bool				out_first;
++	struct crypto_shash		*shash;
++	unsigned int keylen;
++	struct crypto_skcipher *fallback;
++};
++
++struct mtk_cipher_reqctx {
++	unsigned long			flags;
++	unsigned int			blksize;
++	unsigned int			ivsize;
++	unsigned int			textsize;
++	unsigned int			assoclen;
++	unsigned int			authsize;
++	dma_addr_t			saRecord_base;
++	struct saState_s		*saState;
++	dma_addr_t			saState_base;
++	uint32_t			saState_idx;
++	struct eip93_descriptor_s	*cdesc;
++	struct scatterlist		*sg_src;
++	struct scatterlist		*sg_dst;
++	int				src_nents;
++	int				dst_nents;
++	struct saState_s		*saState_ctr;
++	dma_addr_t			saState_base_ctr;
++	uint32_t			saState_ctr_idx;
++	struct skcipher_request fallback_req; // keep at the end
++};
++
++int check_valid_request(struct mtk_cipher_reqctx *rctx);
++
++void mtk_unmap_dma(struct mtk_device *mtk, struct mtk_cipher_reqctx *rctx,
++			struct scatterlist *reqsrc, struct scatterlist *reqdst);
++
++void mtk_skcipher_handle_result(struct crypto_async_request *async, int err);
++
++int mtk_send_req(struct crypto_async_request *async,
++			const u8 *reqiv, struct mtk_cipher_reqctx *rctx);
++
++void mtk_handle_result(struct mtk_device *mtk, struct mtk_cipher_reqctx *rctx,
++			u8 *reqiv);
++
++#endif /* _EIP93_CIPHER_H_ */
+--- /dev/null
++++ b/drivers/crypto/mtk-eip93/eip93-common.c
+@@ -0,0 +1,749 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) 2019 - 2021
++ *
++ * Richard van Schagen <vschagen@icloud.com>
++ */
++
++#include <crypto/aes.h>
++#include <crypto/ctr.h>
++#include <crypto/hmac.h>
++#include <crypto/sha1.h>
++#include <crypto/sha2.h>
++#include <linux/delay.h>
++#include <linux/dma-mapping.h>
++#include <linux/scatterlist.h>
++
++#include "eip93-cipher.h"
++#include "eip93-common.h"
++#include "eip93-main.h"
++#include "eip93-regs.h"
++
++inline void *mtk_ring_next_wptr(struct mtk_device *mtk,
++						struct mtk_desc_ring *ring)
++{
++	void *ptr = ring->write;
++
++	if ((ring->write == ring->read - ring->offset) ||
++		(ring->read == ring->base && ring->write == ring->base_end))
++		return ERR_PTR(-ENOMEM);
++
++	if (ring->write == ring->base_end)
++		ring->write = ring->base;
++	else
++		ring->write += ring->offset;
++
++	return ptr;
++}
++
++inline void *mtk_ring_next_rptr(struct mtk_device *mtk,
++						struct mtk_desc_ring *ring)
++{
++	void *ptr = ring->read;
++
++	if (ring->write == ring->read)
++		return ERR_PTR(-ENOENT);
++
++	if (ring->read == ring->base_end)
++		ring->read = ring->base;
++	else
++		ring->read += ring->offset;
++
++	return ptr;
++}
++
++inline int mtk_put_descriptor(struct mtk_device *mtk,
++					struct eip93_descriptor_s *desc)
++{
++	struct eip93_descriptor_s *cdesc;
++	struct eip93_descriptor_s *rdesc;
++	unsigned long irqflags;
++
++	spin_lock_irqsave(&mtk->ring->write_lock, irqflags);
++
++	rdesc = mtk_ring_next_wptr(mtk, &mtk->ring->rdr);
++
++	if (IS_ERR(rdesc)) {
++		spin_unlock_irqrestore(&mtk->ring->write_lock, irqflags);
++		return -ENOENT;
++	}
++
++	cdesc = mtk_ring_next_wptr(mtk, &mtk->ring->cdr);
++
++	if (IS_ERR(cdesc)) {
++		spin_unlock_irqrestore(&mtk->ring->write_lock, irqflags);
++		return -ENOENT;
++	}
++
++	memset(rdesc, 0, sizeof(struct eip93_descriptor_s));
++	memcpy(cdesc, desc, sizeof(struct eip93_descriptor_s));
++
++	atomic_dec(&mtk->ring->free);
++	spin_unlock_irqrestore(&mtk->ring->write_lock, irqflags);
++
++	return 0;
++}
++
++inline void *mtk_get_descriptor(struct mtk_device *mtk)
++{
++	struct eip93_descriptor_s *cdesc;
++	void *ptr;
++	unsigned long irqflags;
++
++	spin_lock_irqsave(&mtk->ring->read_lock, irqflags);
++
++	cdesc = mtk_ring_next_rptr(mtk, &mtk->ring->cdr);
++
++	if (IS_ERR(cdesc)) {
++		spin_unlock_irqrestore(&mtk->ring->read_lock, irqflags);
++		return ERR_PTR(-ENOENT);
++	}
++
++	memset(cdesc, 0, sizeof(struct eip93_descriptor_s));
++
++	ptr = mtk_ring_next_rptr(mtk, &mtk->ring->rdr);
++	if (IS_ERR(ptr)) {
++		spin_unlock_irqrestore(&mtk->ring->read_lock, irqflags);
++		return ERR_PTR(-ENOENT);
++	}
++
++	atomic_inc(&mtk->ring->free);
++	spin_unlock_irqrestore(&mtk->ring->read_lock, irqflags);
++
++	return ptr;
++}
++
++inline int mtk_get_free_saState(struct mtk_device *mtk)
++{
++	struct mtk_state_pool *saState_pool;
++	int i;
++
++	for (i = 0; i < MTK_RING_SIZE; i++) {
++		saState_pool = &mtk->ring->saState_pool[i];
++		if (saState_pool->in_use == false) {
++			saState_pool->in_use = true;
++			return i;
++		}
++
++	}
++
++	return -ENOENT;
++}
++
++static inline void mtk_free_sg_copy(const int len, struct scatterlist **sg)
++{
++	if (!*sg || !len)
++		return;
++
++	free_pages((unsigned long)sg_virt(*sg), get_order(len));
++	kfree(*sg);
++	*sg = NULL;
++}
++
++static inline int mtk_make_sg_copy(struct scatterlist *src,
++			struct scatterlist **dst,
++			const uint32_t len, const bool copy)
++{
++	void *pages;
++
++	*dst = kmalloc(sizeof(**dst), GFP_KERNEL);
++	if (!*dst)
++		return -ENOMEM;
++
++
++	pages = (void *)__get_free_pages(GFP_KERNEL | GFP_DMA,
++					get_order(len));
++
++	if (!pages) {
++		kfree(*dst);
++		*dst = NULL;
++		return -ENOMEM;
++	}
++
++	sg_init_table(*dst, 1);
++	sg_set_buf(*dst, pages, len);
++
++	/* copy only as requested */
++	if (copy)
++		sg_copy_to_buffer(src, sg_nents(src), pages, len);
++
++	return 0;
++}
++
++static inline bool mtk_is_sg_aligned(struct scatterlist *sg, u32 len,
++						const int blksize)
++{
++	int nents;
++
++	for (nents = 0; sg; sg = sg_next(sg), ++nents) {
++		if (!IS_ALIGNED(sg->offset, 4))
++			return false;
++
++		if (len <= sg->length) {
++			if (!IS_ALIGNED(len, blksize))
++				return false;
++
++			return true;
++		}
++
++		if (!IS_ALIGNED(sg->length, blksize))
++			return false;
++
++		len -= sg->length;
++	}
++	return false;
++}
++
++int check_valid_request(struct mtk_cipher_reqctx *rctx)
++{
++	struct scatterlist *src = rctx->sg_src;
++	struct scatterlist *dst = rctx->sg_dst;
++	uint32_t src_nents, dst_nents;
++	u32 textsize = rctx->textsize;
++	u32 authsize = rctx->authsize;
++	u32 blksize = rctx->blksize;
++	u32 totlen_src = rctx->assoclen + rctx->textsize;
++	u32 totlen_dst = rctx->assoclen + rctx->textsize;
++	u32 copy_len;
++	bool src_align, dst_align;
++	int err = -EINVAL;
++
++	if (!IS_CTR(rctx->flags)) {
++		if (!IS_ALIGNED(textsize, blksize))
++			return err;
++	}
++
++	if (authsize) {
++		if (IS_ENCRYPT(rctx->flags))
++			totlen_dst += authsize;
++		else
++			totlen_src += authsize;
++	}
++
++	src_nents = sg_nents_for_len(src, totlen_src);
++	dst_nents = sg_nents_for_len(dst, totlen_dst);
++
++	if (src == dst) {
++		src_nents = max(src_nents, dst_nents);
++		dst_nents = src_nents;
++		if (unlikely((totlen_src || totlen_dst) && (src_nents <= 0)))
++			return err;
++
++	} else {
++		if (unlikely(totlen_src && (src_nents <= 0)))
++			return err;
++
++		if (unlikely(totlen_dst && (dst_nents <= 0)))
++			return err;
++	}
++
++	if (authsize) {
++		if (dst_nents == 1 && src_nents == 1) {
++			src_align = mtk_is_sg_aligned(src, totlen_src, blksize);
++			if (src ==  dst)
++				dst_align = src_align;
++			else
++				dst_align = mtk_is_sg_aligned(dst,
++						totlen_dst, blksize);
++		} else {
++			src_align = false;
++			dst_align = false;
++		}
++	} else {
++		src_align = mtk_is_sg_aligned(src, totlen_src, blksize);
++		if (src == dst)
++			dst_align = src_align;
++		else
++			dst_align = mtk_is_sg_aligned(dst, totlen_dst, blksize);
++	}
++
++	copy_len = max(totlen_src, totlen_dst);
++	if (!src_align) {
++		err = mtk_make_sg_copy(src, &rctx->sg_src, copy_len, true);
++		if (err)
++			return err;
++	}
++
++	if (!dst_align) {
++		err = mtk_make_sg_copy(dst, &rctx->sg_dst, copy_len, false);
++		if (err)
++			return err;
++	}
++
++	rctx->src_nents = sg_nents_for_len(rctx->sg_src, totlen_src);
++	rctx->dst_nents = sg_nents_for_len(rctx->sg_dst, totlen_dst);
++
++	return 0;
++}
++/*
++ * Set saRecord function:
++ * Even saRecord is set to "0", keep " = 0" for readability.
++ */
++void mtk_set_saRecord(struct saRecord_s *saRecord, const unsigned int keylen,
++				const u32 flags)
++{
++	saRecord->saCmd0.bits.ivSource = 2;
++	if (IS_ECB(flags))
++		saRecord->saCmd0.bits.saveIv = 0;
++	else
++		saRecord->saCmd0.bits.saveIv = 1;
++
++	saRecord->saCmd0.bits.opGroup = 0;
++	saRecord->saCmd0.bits.opCode = 0;
++
++	switch ((flags & MTK_ALG_MASK)) {
++	case MTK_ALG_AES:
++		saRecord->saCmd0.bits.cipher = 3;
++		saRecord->saCmd1.bits.aesKeyLen = keylen >> 3;
++		break;
++	case MTK_ALG_3DES:
++		saRecord->saCmd0.bits.cipher = 1;
++		break;
++	case MTK_ALG_DES:
++		saRecord->saCmd0.bits.cipher = 0;
++		break;
++	default:
++		saRecord->saCmd0.bits.cipher = 15;
++	}
++
++	switch ((flags & MTK_HASH_MASK)) {
++	case MTK_HASH_SHA256:
++		saRecord->saCmd0.bits.hash = 3;
++		break;
++	case MTK_HASH_SHA224:
++		saRecord->saCmd0.bits.hash = 2;
++		break;
++	case MTK_HASH_SHA1:
++		saRecord->saCmd0.bits.hash = 1;
++		break;
++	case MTK_HASH_MD5:
++		saRecord->saCmd0.bits.hash = 0;
++		break;
++	default:
++		saRecord->saCmd0.bits.hash = 15;
++	}
++
++	saRecord->saCmd0.bits.hdrProc = 0;
++	saRecord->saCmd0.bits.padType = 3;
++	saRecord->saCmd0.bits.extPad = 0;
++	saRecord->saCmd0.bits.scPad = 0;
++
++	switch ((flags & MTK_MODE_MASK)) {
++	case MTK_MODE_CBC:
++		saRecord->saCmd1.bits.cipherMode = 1;
++		break;
++	case MTK_MODE_CTR:
++		saRecord->saCmd1.bits.cipherMode = 2;
++		break;
++	case MTK_MODE_ECB:
++		saRecord->saCmd1.bits.cipherMode = 0;
++		break;
++	}
++
++	saRecord->saCmd1.bits.byteOffset = 0;
++	saRecord->saCmd1.bits.hashCryptOffset = 0;
++	saRecord->saCmd0.bits.digestLength = 0;
++	saRecord->saCmd1.bits.copyPayload = 0;
++
++	if (IS_HMAC(flags)) {
++		saRecord->saCmd1.bits.hmac = 1;
++		saRecord->saCmd1.bits.copyDigest = 1;
++		saRecord->saCmd1.bits.copyHeader = 1;
++	} else {
++		saRecord->saCmd1.bits.hmac = 0;
++		saRecord->saCmd1.bits.copyDigest = 0;
++		saRecord->saCmd1.bits.copyHeader = 0;
++	}
++
++	saRecord->saCmd1.bits.seqNumCheck = 0;
++	saRecord->saSpi = 0x0;
++	saRecord->saSeqNumMask[0] = 0xFFFFFFFF;
++	saRecord->saSeqNumMask[1] = 0x0;
++}
++
++/*
++ * Poor mans Scatter/gather function:
++ * Create a Descriptor for every segment to avoid copying buffers.
++ * For performance better to wait for hardware to perform multiple DMA
++ *
++ */
++static inline int mtk_scatter_combine(struct mtk_device *mtk,
++			struct mtk_cipher_reqctx *rctx,
++			u32 datalen, u32 split, int offsetin)
++{
++	struct eip93_descriptor_s *cdesc = rctx->cdesc;
++	struct scatterlist *sgsrc = rctx->sg_src;
++	struct scatterlist *sgdst = rctx->sg_dst;
++	unsigned int remainin = sg_dma_len(sgsrc);
++	unsigned int remainout = sg_dma_len(sgdst);
++	dma_addr_t saddr = sg_dma_address(sgsrc);
++	dma_addr_t daddr = sg_dma_address(sgdst);
++	dma_addr_t stateAddr;
++	u32 srcAddr, dstAddr, len, n;
++	bool nextin = false;
++	bool nextout = false;
++	int offsetout = 0;
++	int ndesc_cdr = 0, err;
++
++	if (IS_ECB(rctx->flags))
++		rctx->saState_base = 0;
++
++	if (split < datalen) {
++		stateAddr = rctx->saState_base_ctr;
++		n = split;
++	} else {
++		stateAddr = rctx->saState_base;
++		n = datalen;
++	}
++
++	do {
++		if (nextin) {
++			sgsrc = sg_next(sgsrc);
++			remainin = sg_dma_len(sgsrc);
++			if (remainin == 0)
++				continue;
++
++			saddr = sg_dma_address(sgsrc);
++			offsetin = 0;
++			nextin = false;
++		}
++
++		if (nextout) {
++			sgdst = sg_next(sgdst);
++			remainout = sg_dma_len(sgdst);
++			if (remainout == 0)
++				continue;
++
++			daddr = sg_dma_address(sgdst);
++			offsetout = 0;
++			nextout = false;
++		}
++		srcAddr = saddr + offsetin;
++		dstAddr = daddr + offsetout;
++
++		if (remainin == remainout) {
++			len = remainin;
++			if (len > n) {
++				len = n;
++				remainin -= n;
++				remainout -= n;
++				offsetin += n;
++				offsetout += n;
++			} else {
++				nextin = true;
++				nextout = true;
++			}
++		} else if (remainin < remainout) {
++			len = remainin;
++			if (len > n) {
++				len = n;
++				remainin -= n;
++				remainout -= n;
++				offsetin += n;
++				offsetout += n;
++			} else {
++				offsetout += len;
++				remainout -= len;
++				nextin = true;
++			}
++		} else {
++			len = remainout;
++			if (len > n) {
++				len = n;
++				remainin -= n;
++				remainout -= n;
++				offsetin += n;
++				offsetout += n;
++			} else {
++				offsetin += len;
++				remainin -= len;
++				nextout = true;
++			}
++		}
++		n -= len;
++
++		cdesc->srcAddr = srcAddr;
++		cdesc->dstAddr = dstAddr;
++		cdesc->stateAddr = stateAddr;
++		cdesc->peLength.bits.peReady = 0;
++		cdesc->peLength.bits.byPass = 0;
++		cdesc->peLength.bits.length = len;
++		cdesc->peLength.bits.hostReady = 1;
++
++		if (n == 0) {
++			n = datalen - split;
++			split = datalen;
++			stateAddr = rctx->saState_base;
++		}
++
++		if (n == 0)
++			cdesc->userId |= MTK_DESC_LAST;
++
++		/* Loop - Delay - No need to rollback
++		 * Maybe refine by slowing down at MTK_RING_BUSY
++		 */
++again:
++		err = mtk_put_descriptor(mtk, cdesc);
++		if (err) {
++			udelay(500);
++			goto again;
++		}
++		/* Writing new descriptor count starts DMA action */
++		writel(1, mtk->base + EIP93_REG_PE_CD_COUNT);
++
++		ndesc_cdr++;
++	} while (n);
++
++	return -EINPROGRESS;
++}
++
++int mtk_send_req(struct crypto_async_request *async,
++			const u8 *reqiv, struct mtk_cipher_reqctx *rctx)
++{
++	struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(async->tfm);
++	struct mtk_device *mtk = ctx->mtk;
++	struct scatterlist *src = rctx->sg_src;
++	struct scatterlist *dst = rctx->sg_dst;
++	struct saState_s *saState;
++	struct mtk_state_pool *saState_pool;
++	struct eip93_descriptor_s cdesc;
++	u32 flags = rctx->flags;
++	int idx;
++	int offsetin = 0, err = -ENOMEM;
++	u32 datalen = rctx->assoclen + rctx->textsize;
++	u32 split = datalen;
++	u32 start, end, ctr, blocks;
++	u32 iv[AES_BLOCK_SIZE / sizeof(u32)];
++
++	rctx->saState_ctr = NULL;
++	rctx->saState = NULL;
++
++	if (IS_ECB(flags))
++		goto skip_iv;
++
++	memcpy(iv, reqiv, rctx->ivsize);
++
++	if (!IS_ALIGNED((u32)reqiv, rctx->ivsize) || IS_RFC3686(flags)) {
++		rctx->flags &= ~MTK_DESC_DMA_IV;
++		flags = rctx->flags;
++	}
++
++	if (IS_DMA_IV(flags)) {
++		rctx->saState = (void *)reqiv;
++	} else  {
++		idx = mtk_get_free_saState(mtk);
++		if (idx < 0)
++			goto send_err;
++		saState_pool = &mtk->ring->saState_pool[idx];
++		rctx->saState_idx = idx;
++		rctx->saState = saState_pool->base;
++		rctx->saState_base = saState_pool->base_dma;
++		memcpy(rctx->saState->stateIv, iv, rctx->ivsize);
++	}
++
++	saState = rctx->saState;
++
++	if (IS_RFC3686(flags)) {
++		saState->stateIv[0] = ctx->saNonce;
++		saState->stateIv[1] = iv[0];
++		saState->stateIv[2] = iv[1];
++		saState->stateIv[3] = cpu_to_be32(1);
++	} else if (!IS_HMAC(flags) && IS_CTR(flags)) {
++		/* Compute data length. */
++		blocks = DIV_ROUND_UP(rctx->textsize, AES_BLOCK_SIZE);
++		ctr = be32_to_cpu(iv[3]);
++		/* Check 32bit counter overflow. */
++		start = ctr;
++		end = start + blocks - 1;
++		if (end < start) {
++			split = AES_BLOCK_SIZE * -start;
++			/*
++			 * Increment the counter manually to cope with
++			 * the hardware counter overflow.
++			 */
++			iv[3] = 0xffffffff;
++			crypto_inc((u8 *)iv, AES_BLOCK_SIZE);
++			idx = mtk_get_free_saState(mtk);
++			if (idx < 0)
++				goto free_state;
++			saState_pool = &mtk->ring->saState_pool[idx];
++			rctx->saState_ctr_idx = idx;
++			rctx->saState_ctr = saState_pool->base;
++			rctx->saState_base_ctr = saState_pool->base_dma;
++
++			memcpy(rctx->saState_ctr->stateIv, reqiv, rctx->ivsize);
++			memcpy(saState->stateIv, iv, rctx->ivsize);
++		}
++	}
++
++	if (IS_DMA_IV(flags)) {
++		rctx->saState_base = dma_map_single(mtk->dev, (void *)reqiv,
++						rctx->ivsize, DMA_TO_DEVICE);
++		if (dma_mapping_error(mtk->dev, rctx->saState_base))
++			goto free_state;
++	}
++skip_iv:
++	cdesc.peCrtlStat.bits.hostReady = 1;
++	cdesc.peCrtlStat.bits.prngMode = 0;
++	cdesc.peCrtlStat.bits.hashFinal = 0;
++	cdesc.peCrtlStat.bits.padCrtlStat = 0;
++	cdesc.peCrtlStat.bits.peReady = 0;
++	cdesc.saAddr = rctx->saRecord_base;
++	cdesc.arc4Addr = (uint32_t)async;
++	cdesc.userId = flags;
++	rctx->cdesc = &cdesc;
++
++	/* map DMA_BIDIRECTIONAL to invalidate cache on destination
++	 * implies __dma_cache_wback_inv
++	 */
++	dma_map_sg(mtk->dev, dst, rctx->dst_nents, DMA_BIDIRECTIONAL);
++	if (src != dst)
++		dma_map_sg(mtk->dev, src, rctx->src_nents, DMA_TO_DEVICE);
++
++	err = mtk_scatter_combine(mtk, rctx, datalen, split, offsetin);
++
++	return err;
++
++free_state:
++	if (rctx->saState) {
++		saState_pool = &mtk->ring->saState_pool[rctx->saState_idx];
++		saState_pool->in_use = false;
++	}
++
++	if (rctx->saState_ctr) {
++		saState_pool = &mtk->ring->saState_pool[rctx->saState_ctr_idx];
++		saState_pool->in_use = false;
++	}
++send_err:
++	return err;
++}
++
++void mtk_unmap_dma(struct mtk_device *mtk, struct mtk_cipher_reqctx *rctx,
++			struct scatterlist *reqsrc, struct scatterlist *reqdst)
++{
++	u32 len = rctx->assoclen + rctx->textsize;
++	u32 authsize = rctx->authsize;
++	u32 flags = rctx->flags;
++	u32 *otag;
++	int i;
++
++	if (rctx->sg_src == rctx->sg_dst) {
++		dma_unmap_sg(mtk->dev, rctx->sg_dst, rctx->dst_nents,
++							DMA_BIDIRECTIONAL);
++		goto process_tag;
++	}
++
++	dma_unmap_sg(mtk->dev, rctx->sg_src, rctx->src_nents,
++							DMA_TO_DEVICE);
++
++	if (rctx->sg_src != reqsrc)
++		mtk_free_sg_copy(len +  rctx->authsize, &rctx->sg_src);
++
++	dma_unmap_sg(mtk->dev, rctx->sg_dst, rctx->dst_nents,
++							DMA_BIDIRECTIONAL);
++
++	/* SHA tags need conversion from net-to-host */
++process_tag:
++	if (IS_DECRYPT(flags))
++		authsize = 0;
++
++	if (authsize) {
++		if (!IS_HASH_MD5(flags)) {
++			otag = sg_virt(rctx->sg_dst) + len;
++			for (i = 0; i < (authsize / 4); i++)
++				otag[i] = ntohl(otag[i]);
++		}
++	}
++
++	if (rctx->sg_dst != reqdst) {
++		sg_copy_from_buffer(reqdst, sg_nents(reqdst),
++				sg_virt(rctx->sg_dst), len + authsize);
++		mtk_free_sg_copy(len + rctx->authsize, &rctx->sg_dst);
++	}
++}
++
++void mtk_handle_result(struct mtk_device *mtk, struct mtk_cipher_reqctx *rctx,
++			u8 *reqiv)
++{
++	struct mtk_state_pool *saState_pool;
++
++	if (IS_DMA_IV(rctx->flags))
++		dma_unmap_single(mtk->dev, rctx->saState_base, rctx->ivsize,
++						DMA_TO_DEVICE);
++
++	if (!IS_ECB(rctx->flags))
++		memcpy(reqiv, rctx->saState->stateIv, rctx->ivsize);
++
++	if ((rctx->saState) && !(IS_DMA_IV(rctx->flags))) {
++		saState_pool = &mtk->ring->saState_pool[rctx->saState_idx];
++		saState_pool->in_use = false;
++	}
++
++	if (rctx->saState_ctr) {
++		saState_pool = &mtk->ring->saState_pool[rctx->saState_ctr_idx];
++		saState_pool->in_use = false;
++	}
++}
++
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_HMAC)
++/* basically this is set hmac - key */
++int mtk_authenc_setkey(struct crypto_shash *cshash, struct saRecord_s *sa,
++			const u8 *authkey, unsigned int authkeylen)
++{
++	int bs = crypto_shash_blocksize(cshash);
++	int ds = crypto_shash_digestsize(cshash);
++	int ss = crypto_shash_statesize(cshash);
++	u8 *ipad, *opad;
++	unsigned int i, err;
++
++	SHASH_DESC_ON_STACK(shash, cshash);
++
++	shash->tfm = cshash;
++
++	/* auth key
++	 *
++	 * EIP93 can only authenticate with hash of the key
++	 * do software shash until EIP93 hash function complete.
++	 */
++	ipad = kcalloc(2, SHA256_BLOCK_SIZE + ss, GFP_KERNEL);
++	if (!ipad)
++		return -ENOMEM;
++
++	opad = ipad + SHA256_BLOCK_SIZE + ss;
++
++	if (authkeylen > bs) {
++		err = crypto_shash_digest(shash, authkey,
++					authkeylen, ipad);
++		if (err)
++			return err;
++
++		authkeylen = ds;
++	} else
++		memcpy(ipad, authkey, authkeylen);
++
++	memset(ipad + authkeylen, 0, bs - authkeylen);
++	memcpy(opad, ipad, bs);
++
++	for (i = 0; i < bs; i++) {
++		ipad[i] ^= HMAC_IPAD_VALUE;
++		opad[i] ^= HMAC_OPAD_VALUE;
++	}
++
++	err = crypto_shash_init(shash) ?:
++		crypto_shash_update(shash, ipad, bs) ?:
++		crypto_shash_export(shash, ipad) ?:
++		crypto_shash_init(shash) ?:
++		crypto_shash_update(shash, opad, bs) ?:
++		crypto_shash_export(shash, opad);
++
++	if (err)
++		return err;
++
++	/* add auth key */
++	memcpy(&sa->saIDigest, ipad, SHA256_DIGEST_SIZE);
++	memcpy(&sa->saODigest, opad, SHA256_DIGEST_SIZE);
++
++	kfree(ipad);
++	return 0;
++}
++#endif
+--- /dev/null
++++ b/drivers/crypto/mtk-eip93/eip93-common.h
+@@ -0,0 +1,28 @@
++/* SPDX-License-Identifier: GPL-2.0
++ *
++ * Copyright (C) 2019 - 2021
++ *
++ * Richard van Schagen <vschagen@icloud.com>
++ */
++
++#ifndef _EIP93_COMMON_H_
++#define _EIP93_COMMON_H_
++
++#include "eip93-main.h"
++
++inline int mtk_put_descriptor(struct mtk_device *mtk,
++					struct eip93_descriptor_s *desc);
++
++inline void *mtk_get_descriptor(struct mtk_device *mtk);
++
++inline int mtk_get_free_saState(struct mtk_device *mtk);
++
++void mtk_set_saRecord(struct saRecord_s *saRecord, const unsigned int keylen,
++				const u32 flags);
++
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_HMAC)
++int mtk_authenc_setkey(struct crypto_shash *cshash, struct saRecord_s *sa,
++			const u8 *authkey, unsigned int authkeylen);
++#endif
++
++#endif /* _EIP93_COMMON_H_ */
+--- /dev/null
++++ b/drivers/crypto/mtk-eip93/eip93-des.h
+@@ -0,0 +1,15 @@
++/* SPDX-License-Identifier: GPL-2.0
++ *
++ * Copyright (C) 2019 - 2021
++ *
++ * Richard van Schagen <vschagen@icloud.com>
++ */
++#ifndef _EIP93_DES_H_
++#define _EIP93_DES_H_
++
++extern struct mtk_alg_template mtk_alg_ecb_des;
++extern struct mtk_alg_template mtk_alg_cbc_des;
++extern struct mtk_alg_template mtk_alg_ecb_des3_ede;
++extern struct mtk_alg_template mtk_alg_cbc_des3_ede;
++
++#endif /* _EIP93_DES_H_ */
+--- /dev/null
++++ b/drivers/crypto/mtk-eip93/eip93-main.c
+@@ -0,0 +1,467 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) 2019 - 2021
++ *
++ * Richard van Schagen <vschagen@icloud.com>
++ */
++
++#include <linux/atomic.h>
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/dma-mapping.h>
++#include <linux/interrupt.h>
++#include <linux/module.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include <linux/spinlock.h>
++
++#include "eip93-main.h"
++#include "eip93-regs.h"
++#include "eip93-common.h"
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_SKCIPHER)
++#include "eip93-cipher.h"
++#endif
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AES)
++#include "eip93-aes.h"
++#endif
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES)
++#include "eip93-des.h"
++#endif
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AEAD)
++#include "eip93-aead.h"
++#endif
++
++static struct mtk_alg_template *mtk_algs[] = {
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES)
++	&mtk_alg_ecb_des,
++	&mtk_alg_cbc_des,
++	&mtk_alg_ecb_des3_ede,
++	&mtk_alg_cbc_des3_ede,
++#endif
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AES)
++	&mtk_alg_ecb_aes,
++	&mtk_alg_cbc_aes,
++	&mtk_alg_ctr_aes,
++	&mtk_alg_rfc3686_aes,
++#endif
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AEAD)
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES)
++	&mtk_alg_authenc_hmac_md5_cbc_des,
++	&mtk_alg_authenc_hmac_sha1_cbc_des,
++	&mtk_alg_authenc_hmac_sha224_cbc_des,
++	&mtk_alg_authenc_hmac_sha256_cbc_des,
++	&mtk_alg_authenc_hmac_md5_cbc_des3_ede,
++	&mtk_alg_authenc_hmac_sha1_cbc_des3_ede,
++	&mtk_alg_authenc_hmac_sha224_cbc_des3_ede,
++	&mtk_alg_authenc_hmac_sha256_cbc_des3_ede,
++#endif
++	&mtk_alg_authenc_hmac_md5_cbc_aes,
++	&mtk_alg_authenc_hmac_sha1_cbc_aes,
++	&mtk_alg_authenc_hmac_sha224_cbc_aes,
++	&mtk_alg_authenc_hmac_sha256_cbc_aes,
++	&mtk_alg_authenc_hmac_md5_rfc3686_aes,
++	&mtk_alg_authenc_hmac_sha1_rfc3686_aes,
++	&mtk_alg_authenc_hmac_sha224_rfc3686_aes,
++	&mtk_alg_authenc_hmac_sha256_rfc3686_aes,
++#endif
++};
++
++inline void mtk_irq_disable(struct mtk_device *mtk, u32 mask)
++{
++	__raw_writel(mask, mtk->base + EIP93_REG_MASK_DISABLE);
++}
++
++inline void mtk_irq_enable(struct mtk_device *mtk, u32 mask)
++{
++	__raw_writel(mask, mtk->base + EIP93_REG_MASK_ENABLE);
++}
++
++inline void mtk_irq_clear(struct mtk_device *mtk, u32 mask)
++{
++	__raw_writel(mask, mtk->base + EIP93_REG_INT_CLR);
++}
++
++static void mtk_unregister_algs(unsigned int i)
++{
++	unsigned int j;
++
++	for (j = 0; j < i; j++) {
++		switch (mtk_algs[j]->type) {
++		case MTK_ALG_TYPE_SKCIPHER:
++			crypto_unregister_skcipher(&mtk_algs[j]->alg.skcipher);
++			break;
++		case MTK_ALG_TYPE_AEAD:
++			crypto_unregister_aead(&mtk_algs[j]->alg.aead);
++			break;
++		}
++	}
++}
++
++static int mtk_register_algs(struct mtk_device *mtk)
++{
++	unsigned int i;
++	int err = 0;
++
++	for (i = 0; i < ARRAY_SIZE(mtk_algs); i++) {
++		mtk_algs[i]->mtk = mtk;
++
++		switch (mtk_algs[i]->type) {
++		case MTK_ALG_TYPE_SKCIPHER:
++			err = crypto_register_skcipher(&mtk_algs[i]->alg.skcipher);
++			break;
++		case MTK_ALG_TYPE_AEAD:
++			err = crypto_register_aead(&mtk_algs[i]->alg.aead);
++			break;
++		}
++		if (err)
++			goto fail;
++	}
++
++	return 0;
++
++fail:
++	mtk_unregister_algs(i);
++
++	return err;
++}
++
++static void mtk_handle_result_descriptor(struct mtk_device *mtk)
++{
++	struct crypto_async_request *async;
++	struct eip93_descriptor_s *rdesc;
++	bool last_entry;
++	u32 flags;
++	int handled, ready, err;
++	union peCrtlStat_w done1;
++	union peLength_w done2;
++
++get_more:
++	handled = 0;
++
++	ready = readl(mtk->base + EIP93_REG_PE_RD_COUNT) & GENMASK(10, 0);
++
++	if (!ready) {
++		mtk_irq_clear(mtk, EIP93_INT_PE_RDRTHRESH_REQ);
++		mtk_irq_enable(mtk, EIP93_INT_PE_RDRTHRESH_REQ);
++		return;
++	}
++
++	last_entry = false;
++
++	while (ready) {
++		rdesc = mtk_get_descriptor(mtk);
++		if (IS_ERR(rdesc)) {
++			dev_err(mtk->dev, "Ndesc: %d nreq: %d\n",
++				handled, ready);
++			err = -EIO;
++			break;
++		}
++		/* make sure DMA is finished writing */
++		do {
++			done1.word = READ_ONCE(rdesc->peCrtlStat.word);
++			done2.word = READ_ONCE(rdesc->peLength.word);
++		} while ((!done1.bits.peReady) || (!done2.bits.peReady));
++
++		err = rdesc->peCrtlStat.bits.errStatus;
++
++		flags = rdesc->userId;
++		async = (struct crypto_async_request *)rdesc->arc4Addr;
++
++		writel(1, mtk->base + EIP93_REG_PE_RD_COUNT);
++		mtk_irq_clear(mtk, EIP93_INT_PE_RDRTHRESH_REQ);
++
++		handled++;
++		ready--;
++
++		if (flags & MTK_DESC_LAST) {
++			last_entry = true;
++			break;
++		}
++	}
++
++	if (!last_entry)
++		goto get_more;
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_SKCIPHER)
++	if (flags & MTK_DESC_SKCIPHER)
++		mtk_skcipher_handle_result(async, err);
++#endif
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AEAD)
++	if (flags & MTK_DESC_AEAD)
++		mtk_aead_handle_result(async, err);
++#endif
++	goto get_more;
++}
++
++static void mtk_done_task(unsigned long data)
++{
++	struct mtk_device *mtk = (struct mtk_device *)data;
++
++	mtk_handle_result_descriptor(mtk);
++}
++
++static irqreturn_t mtk_irq_handler(int irq, void *dev_id)
++{
++	struct mtk_device *mtk = (struct mtk_device *)dev_id;
++	u32 irq_status;
++
++	irq_status = readl(mtk->base + EIP93_REG_INT_MASK_STAT);
++
++	if (irq_status & EIP93_INT_PE_RDRTHRESH_REQ) {
++		mtk_irq_disable(mtk, EIP93_INT_PE_RDRTHRESH_REQ);
++		tasklet_schedule(&mtk->ring->done_task);
++		return IRQ_HANDLED;
++	}
++
++	mtk_irq_clear(mtk, irq_status);
++	if (irq_status)
++		mtk_irq_disable(mtk, irq_status);
++
++	return IRQ_NONE;
++}
++
++static void mtk_initialize(struct mtk_device *mtk)
++{
++	union peConfig_w peConfig;
++	union peEndianCfg_w peEndianCfg;
++	union peIntCfg_w peIntCfg;
++	union peClockCfg_w peClockCfg;
++	union peBufThresh_w peBufThresh;
++	union peRingThresh_w peRingThresh;
++
++	/* Reset Engine and setup Mode */
++	peConfig.word = 0;
++	peConfig.bits.resetPE = 1;
++	peConfig.bits.resetRing = 1;
++	peConfig.bits.peMode = 3;
++	peConfig.bits.enCDRupdate = 1;
++
++	writel(peConfig.word, mtk->base + EIP93_REG_PE_CONFIG);
++
++	udelay(10);
++
++	peConfig.bits.resetPE = 0;
++	peConfig.bits.resetRing = 0;
++
++	writel(peConfig.word, mtk->base + EIP93_REG_PE_CONFIG);
++
++	/* Initialize the BYTE_ORDER_CFG register */
++	peEndianCfg.word = 0;
++	writel(peEndianCfg.word, mtk->base + EIP93_REG_PE_ENDIAN_CONFIG);
++
++	/* Initialize the INT_CFG register */
++	peIntCfg.word = 0;
++	writel(peIntCfg.word, mtk->base + EIP93_REG_INT_CFG);
++
++	/* Config Clocks */
++	peClockCfg.word = 0;
++	peClockCfg.bits.enPEclk = 1;
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES)
++	peClockCfg.bits.enDESclk = 1;
++#endif
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AES)
++	peClockCfg.bits.enAESclk = 1;
++#endif
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_HMAC)
++	peClockCfg.bits.enHASHclk = 1;
++#endif
++	writel(peClockCfg.word, mtk->base + EIP93_REG_PE_CLOCK_CTRL);
++
++	/* Config DMA thresholds */
++	peBufThresh.word = 0;
++	peBufThresh.bits.inputBuffer  = 128;
++	peBufThresh.bits.outputBuffer = 128;
++
++	writel(peBufThresh.word, mtk->base + EIP93_REG_PE_BUF_THRESH);
++
++	/* Clear/ack all interrupts before disable all */
++	mtk_irq_clear(mtk, 0xFFFFFFFF);
++	mtk_irq_disable(mtk, 0xFFFFFFFF);
++
++	/* Config Ring Threshold */
++	peRingThresh.word = 0;
++	peRingThresh.bits.CDRThresh = MTK_RING_SIZE - MTK_RING_BUSY;
++	peRingThresh.bits.RDRThresh = 0;
++	peRingThresh.bits.RDTimeout = 5;
++	peRingThresh.bits.enTimeout = 1;
++
++	writel(peRingThresh.word, mtk->base + EIP93_REG_PE_RING_THRESH);
++}
++
++static void mtk_desc_free(struct mtk_device *mtk)
++{
++	writel(0, mtk->base + EIP93_REG_PE_RING_CONFIG);
++	writel(0, mtk->base + EIP93_REG_PE_CDR_BASE);
++	writel(0, mtk->base + EIP93_REG_PE_RDR_BASE);
++}
++
++static int mtk_set_ring(struct mtk_device *mtk, struct mtk_desc_ring *ring,
++			int Offset)
++{
++	ring->offset = Offset;
++	ring->base = dmam_alloc_coherent(mtk->dev, Offset * MTK_RING_SIZE,
++					&ring->base_dma, GFP_KERNEL);
++	if (!ring->base)
++		return -ENOMEM;
++
++	ring->write = ring->base;
++	ring->base_end = ring->base + Offset * (MTK_RING_SIZE - 1);
++	ring->read  = ring->base;
++
++	return 0;
++}
++
++static int mtk_desc_init(struct mtk_device *mtk)
++{
++	struct mtk_state_pool *saState_pool;
++	struct mtk_desc_ring *cdr = &mtk->ring->cdr;
++	struct mtk_desc_ring *rdr = &mtk->ring->rdr;
++	union peRingCfg_w peRingCfg;
++	int RingOffset, err, i;
++
++	RingOffset = sizeof(struct eip93_descriptor_s);
++
++	err = mtk_set_ring(mtk, cdr, RingOffset);
++	if (err)
++		return err;
++
++	err = mtk_set_ring(mtk, rdr, RingOffset);
++	if (err)
++		return err;
++
++	writel((u32)cdr->base_dma, mtk->base + EIP93_REG_PE_CDR_BASE);
++	writel((u32)rdr->base_dma, mtk->base + EIP93_REG_PE_RDR_BASE);
++
++	peRingCfg.word = 0;
++	peRingCfg.bits.ringSize = MTK_RING_SIZE - 1;
++	peRingCfg.bits.ringOffset =  RingOffset / 4;
++
++	writel(peRingCfg.word, mtk->base + EIP93_REG_PE_RING_CONFIG);
++
++	atomic_set(&mtk->ring->free, MTK_RING_SIZE - 1);
++	/* Create State record DMA pool */
++	RingOffset = sizeof(struct saState_s);
++	mtk->ring->saState = dmam_alloc_coherent(mtk->dev,
++					RingOffset * MTK_RING_SIZE,
++					&mtk->ring->saState_dma, GFP_KERNEL);
++	if (!mtk->ring->saState)
++		return -ENOMEM;
++
++	mtk->ring->saState_pool = devm_kcalloc(mtk->dev, 1,
++				sizeof(struct mtk_state_pool) * MTK_RING_SIZE,
++				GFP_KERNEL);
++
++	for (i = 0; i < MTK_RING_SIZE; i++) {
++		saState_pool = &mtk->ring->saState_pool[i];
++		saState_pool->base = mtk->ring->saState + (i * RingOffset);
++		saState_pool->base_dma = mtk->ring->saState_dma + (i * RingOffset);
++		saState_pool->in_use = false;
++	}
++
++	return 0;
++}
++
++static void mtk_cleanup(struct mtk_device *mtk)
++{
++	tasklet_kill(&mtk->ring->done_task);
++
++	/* Clear/ack all interrupts before disable all */
++	mtk_irq_clear(mtk, 0xFFFFFFFF);
++	mtk_irq_disable(mtk, 0xFFFFFFFF);
++
++	writel(0, mtk->base + EIP93_REG_PE_CLOCK_CTRL);
++
++	mtk_desc_free(mtk);
++}
++
++static int mtk_crypto_probe(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct mtk_device *mtk;
++	struct resource *res;
++	int err;
++
++	mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL);
++	if (!mtk)
++		return -ENOMEM;
++
++	mtk->dev = dev;
++	platform_set_drvdata(pdev, mtk);
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	mtk->base = devm_ioremap_resource(&pdev->dev, res);
++
++	if (IS_ERR(mtk->base))
++		return PTR_ERR(mtk->base);
++
++	mtk->irq = platform_get_irq(pdev, 0);
++
++	if (mtk->irq < 0)
++		return mtk->irq;
++
++	err = devm_request_threaded_irq(mtk->dev, mtk->irq, mtk_irq_handler,
++					NULL, IRQF_ONESHOT,
++					dev_name(mtk->dev), mtk);
++
++	mtk->ring = devm_kcalloc(mtk->dev, 1, sizeof(*mtk->ring), GFP_KERNEL);
++
++	if (!mtk->ring)
++		return -ENOMEM;
++
++	err = mtk_desc_init(mtk);
++	if (err)
++		return err;
++
++	tasklet_init(&mtk->ring->done_task, mtk_done_task, (unsigned long)mtk);
++
++	spin_lock_init(&mtk->ring->read_lock);
++	spin_lock_init(&mtk->ring->write_lock);
++
++	mtk_initialize(mtk);
++
++	/* Init. finished, enable RDR interupt */
++	mtk_irq_enable(mtk, EIP93_INT_PE_RDRTHRESH_REQ);
++
++	err = mtk_register_algs(mtk);
++	if (err) {
++		mtk_cleanup(mtk);
++		return err;
++	}
++
++	dev_info(mtk->dev, "EIP93 Crypto Engine Initialized.");
++
++	return 0;
++}
++
++static int mtk_crypto_remove(struct platform_device *pdev)
++{
++	struct mtk_device *mtk = platform_get_drvdata(pdev);
++
++	mtk_unregister_algs(ARRAY_SIZE(mtk_algs));
++	mtk_cleanup(mtk);
++	dev_info(mtk->dev, "EIP93 removed.\n");
++
++	return 0;
++}
++
++#if defined(CONFIG_OF)
++static const struct of_device_id mtk_crypto_of_match[] = {
++	{ .compatible = "mediatek,mtk-eip93", },
++	{}
++};
++MODULE_DEVICE_TABLE(of, mtk_crypto_of_match);
++#endif
++
++static struct platform_driver mtk_crypto_driver = {
++	.probe = mtk_crypto_probe,
++	.remove = mtk_crypto_remove,
++	.driver = {
++		.name = "mtk-eip93",
++		.of_match_table = of_match_ptr(mtk_crypto_of_match),
++	},
++};
++module_platform_driver(mtk_crypto_driver);
++
++MODULE_AUTHOR("Richard van Schagen <vschagen@cs.com>");
++MODULE_ALIAS("platform:" KBUILD_MODNAME);
++MODULE_DESCRIPTION("Mediatek EIP-93 crypto engine driver");
++MODULE_LICENSE("GPL v2");
+--- /dev/null
++++ b/drivers/crypto/mtk-eip93/eip93-main.h
+@@ -0,0 +1,146 @@
++/* SPDX-License-Identifier: GPL-2.0
++ *
++ * Copyright (C) 2019 - 2021
++ *
++ * Richard van Schagen <vschagen@icloud.com>
++ */
++#ifndef _EIP93_MAIN_H_
++#define _EIP93_MAIN_H_
++
++#include <crypto/internal/aead.h>
++#include <crypto/internal/hash.h>
++#include <crypto/internal/rng.h>
++#include <crypto/internal/skcipher.h>
++#include <linux/device.h>
++#include <linux/interrupt.h>
++
++#define MTK_RING_SIZE			512
++#define MTK_RING_BUSY			32
++#define MTK_CRA_PRIORITY		1500
++
++/* cipher algorithms */
++#define MTK_ALG_DES			BIT(0)
++#define MTK_ALG_3DES			BIT(1)
++#define MTK_ALG_AES			BIT(2)
++#define MTK_ALG_MASK			GENMASK(2, 0)
++/* hash and hmac algorithms */
++#define MTK_HASH_MD5			BIT(3)
++#define MTK_HASH_SHA1			BIT(4)
++#define MTK_HASH_SHA224			BIT(5)
++#define MTK_HASH_SHA256			BIT(6)
++#define MTK_HASH_HMAC			BIT(7)
++#define MTK_HASH_MASK			GENMASK(6, 3)
++/* cipher modes */
++#define MTK_MODE_CBC			BIT(8)
++#define MTK_MODE_ECB			BIT(9)
++#define MTK_MODE_CTR			BIT(10)
++#define MTK_MODE_RFC3686		BIT(11)
++#define MTK_MODE_MASK			GENMASK(10, 8)
++
++/* cipher encryption/decryption operations */
++#define MTK_ENCRYPT			BIT(12)
++#define MTK_DECRYPT			BIT(13)
++
++#define MTK_BUSY			BIT(14)
++
++/* descriptor flags */
++#define MTK_DESC_ASYNC			BIT(31)
++#define MTK_DESC_SKCIPHER		BIT(30)
++#define MTK_DESC_AEAD			BIT(29)
++#define MTK_DESC_AHASH			BIT(28)
++#define MTK_DESC_PRNG			BIT(27)
++#define MTK_DESC_FAKE_HMAC		BIT(26)
++#define MTK_DESC_LAST			BIT(25)
++#define MTK_DESC_FINISH			BIT(24)
++#define MTK_DESC_IPSEC			BIT(23)
++#define MTK_DESC_DMA_IV			BIT(22)
++
++#define IS_DES(flags)			(flags & MTK_ALG_DES)
++#define IS_3DES(flags)			(flags & MTK_ALG_3DES)
++#define IS_AES(flags)			(flags & MTK_ALG_AES)
++
++#define IS_HASH_MD5(flags)		(flags & MTK_HASH_MD5)
++#define IS_HASH_SHA1(flags)		(flags & MTK_HASH_SHA1)
++#define IS_HASH_SHA224(flags)		(flags & MTK_HASH_SHA224)
++#define IS_HASH_SHA256(flags)		(flags & MTK_HASH_SHA256)
++#define IS_HMAC(flags)			(flags & MTK_HASH_HMAC)
++
++#define IS_CBC(mode)			(mode & MTK_MODE_CBC)
++#define IS_ECB(mode)			(mode & MTK_MODE_ECB)
++#define IS_CTR(mode)			(mode & MTK_MODE_CTR)
++#define IS_RFC3686(mode)		(mode & MTK_MODE_RFC3686)
++
++#define IS_BUSY(flags)			(flags & MTK_BUSY)
++#define IS_DMA_IV(flags)		(flags & MTK_DESC_DMA_IV)
++
++#define IS_ENCRYPT(dir)			(dir & MTK_ENCRYPT)
++#define IS_DECRYPT(dir)			(dir & MTK_DECRYPT)
++
++#define IS_CIPHER(flags)		(flags & (MTK_ALG_DES || \
++						MTK_ALG_3DES ||  \
++						MTK_ALG_AES))
++
++#define IS_HASH(flags)			(flags & (MTK_HASH_MD5 ||  \
++						MTK_HASH_SHA1 ||   \
++						MTK_HASH_SHA224 || \
++						MTK_HASH_SHA256))
++
++/**
++ * struct mtk_device - crypto engine device structure
++ */
++struct mtk_device {
++	void __iomem		*base;
++	struct device		*dev;
++	struct clk		*clk;
++	int			irq;
++	struct mtk_ring		*ring;
++	struct mtk_state_pool	*saState_pool;
++};
++
++struct mtk_desc_ring {
++	void			*base;
++	void			*base_end;
++	dma_addr_t		base_dma;
++	/* write and read pointers */
++	void			*read;
++	void			*write;
++	/* descriptor element offset */
++	u32			offset;
++};
++
++struct mtk_state_pool {
++	void			*base;
++	dma_addr_t		base_dma;
++	bool			in_use;
++};
++
++struct mtk_ring {
++	struct tasklet_struct		done_task;
++	/* command/result rings */
++	struct mtk_desc_ring		cdr;
++	struct mtk_desc_ring		rdr;
++	spinlock_t			write_lock;
++	spinlock_t			read_lock;
++	atomic_t			free;
++	/* saState */
++	struct mtk_state_pool		*saState_pool;
++	void				*saState;
++	dma_addr_t			saState_dma;
++};
++
++enum mtk_alg_type {
++	MTK_ALG_TYPE_AEAD,
++	MTK_ALG_TYPE_SKCIPHER,
++};
++
++struct mtk_alg_template {
++	struct mtk_device	*mtk;
++	enum mtk_alg_type	type;
++	u32			flags;
++	union {
++		struct aead_alg		aead;
++		struct skcipher_alg	skcipher;
++	} alg;
++};
++
++#endif /* _EIP93_MAIN_H_ */
+--- /dev/null
++++ b/drivers/crypto/mtk-eip93/eip93-regs.h
+@@ -0,0 +1,382 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++/*
++ * Copyright (C) 2019 - 2021
++ *
++ * Richard van Schagen <vschagen@icloud.com>
++ */
++#ifndef REG_EIP93_H
++#define REG_EIP93_H
++
++#define EIP93_REG_WIDTH			4
++/*-----------------------------------------------------------------------------
++ * Register Map
++ */
++#define DESP_BASE			0x0000000
++#define EIP93_REG_PE_CTRL_STAT		((DESP_BASE)+(0x00 * EIP93_REG_WIDTH))
++#define EIP93_REG_PE_SOURCE_ADDR	((DESP_BASE)+(0x01 * EIP93_REG_WIDTH))
++#define EIP93_REG_PE_DEST_ADDR		((DESP_BASE)+(0x02 * EIP93_REG_WIDTH))
++#define EIP93_REG_PE_SA_ADDR		((DESP_BASE)+(0x03 * EIP93_REG_WIDTH))
++#define EIP93_REG_PE_ADDR		((DESP_BASE)+(0x04 * EIP93_REG_WIDTH))
++#define EIP93_REG_PE_USER_ID		((DESP_BASE)+(0x06 * EIP93_REG_WIDTH))
++#define EIP93_REG_PE_LENGTH		((DESP_BASE)+(0x07 * EIP93_REG_WIDTH))
++
++//PACKET ENGINE RING configuration registers
++#define PE_RNG_BASE			0x0000080
++
++#define EIP93_REG_PE_CDR_BASE		((PE_RNG_BASE)+(0x00 * EIP93_REG_WIDTH))
++#define EIP93_REG_PE_RDR_BASE		((PE_RNG_BASE)+(0x01 * EIP93_REG_WIDTH))
++#define EIP93_REG_PE_RING_CONFIG	((PE_RNG_BASE)+(0x02 * EIP93_REG_WIDTH))
++#define EIP93_REG_PE_RING_THRESH	((PE_RNG_BASE)+(0x03 * EIP93_REG_WIDTH))
++#define EIP93_REG_PE_CD_COUNT		((PE_RNG_BASE)+(0x04 * EIP93_REG_WIDTH))
++#define EIP93_REG_PE_RD_COUNT		((PE_RNG_BASE)+(0x05 * EIP93_REG_WIDTH))
++#define EIP93_REG_PE_RING_RW_PNTR	((PE_RNG_BASE)+(0x06 * EIP93_REG_WIDTH))
++
++//PACKET ENGINE  configuration registers
++#define PE_CFG_BASE			0x0000100
++#define EIP93_REG_PE_CONFIG		((PE_CFG_BASE)+(0x00 * EIP93_REG_WIDTH))
++#define EIP93_REG_PE_STATUS		((PE_CFG_BASE)+(0x01 * EIP93_REG_WIDTH))
++#define EIP93_REG_PE_BUF_THRESH		((PE_CFG_BASE)+(0x03 * EIP93_REG_WIDTH))
++#define EIP93_REG_PE_INBUF_COUNT	((PE_CFG_BASE)+(0x04 * EIP93_REG_WIDTH))
++#define EIP93_REG_PE_OUTBUF_COUNT	((PE_CFG_BASE)+(0x05 * EIP93_REG_WIDTH))
++#define EIP93_REG_PE_BUF_RW_PNTR	((PE_CFG_BASE)+(0x06 * EIP93_REG_WIDTH))
++
++//PACKET ENGINE endian config
++#define EN_CFG_BASE			0x00001CC
++#define EIP93_REG_PE_ENDIAN_CONFIG	((EN_CFG_BASE)+(0x00 * EIP93_REG_WIDTH))
++
++//EIP93 CLOCK control registers
++#define CLOCK_BASE			0x01E8
++#define EIP93_REG_PE_CLOCK_CTRL		((CLOCK_BASE)+(0x00 * EIP93_REG_WIDTH))
++
++//EIP93 Device Option and Revision Register
++#define REV_BASE			0x01F4
++#define EIP93_REG_PE_OPTION_1		((REV_BASE)+(0x00 * EIP93_REG_WIDTH))
++#define EIP93_REG_PE_OPTION_0		((REV_BASE)+(0x01 * EIP93_REG_WIDTH))
++#define EIP93_REG_PE_REVISION		((REV_BASE)+(0x02 * EIP93_REG_WIDTH))
++
++//EIP93 Interrupt Control Register
++#define INT_BASE			0x0200
++#define EIP93_REG_INT_UNMASK_STAT	((INT_BASE)+(0x00 * EIP93_REG_WIDTH))
++#define EIP93_REG_INT_MASK_STAT		((INT_BASE)+(0x01 * EIP93_REG_WIDTH))
++#define EIP93_REG_INT_CLR		((INT_BASE)+(0x01 * EIP93_REG_WIDTH))
++#define EIP93_REG_INT_MASK		((INT_BASE)+(0x02 * EIP93_REG_WIDTH))
++#define EIP93_REG_INT_CFG		((INT_BASE)+(0x03 * EIP93_REG_WIDTH))
++#define EIP93_REG_MASK_ENABLE		((INT_BASE)+(0X04 * EIP93_REG_WIDTH))
++#define EIP93_REG_MASK_DISABLE		((INT_BASE)+(0X05 * EIP93_REG_WIDTH))
++
++//EIP93 SA Record register
++#define SA_BASE				0x0400
++#define EIP93_REG_SA_CMD_0		((SA_BASE)+(0x00 * EIP93_REG_WIDTH))
++#define EIP93_REG_SA_CMD_1		((SA_BASE)+(0x01 * EIP93_REG_WIDTH))
++
++//#define EIP93_REG_SA_READY		((SA_BASE)+(31 * EIP93_REG_WIDTH))
++
++//State save register
++#define STATE_BASE			0x0500
++#define EIP93_REG_STATE_IV_0		((STATE_BASE)+(0x00 * EIP93_REG_WIDTH))
++#define EIP93_REG_STATE_IV_1		((STATE_BASE)+(0x01 * EIP93_REG_WIDTH))
++
++#define EIP93_PE_ARC4STATE_BASEADDR_REG	0x0700
++
++//RAM buffer start address
++#define EIP93_INPUT_BUFFER		0x0800
++#define EIP93_OUTPUT_BUFFER		0x0800
++
++//EIP93 PRNG Configuration Register
++#define PRNG_BASE			0x0300
++#define EIP93_REG_PRNG_STAT		((PRNG_BASE)+(0x00 * EIP93_REG_WIDTH))
++#define EIP93_REG_PRNG_CTRL		((PRNG_BASE)+(0x01 * EIP93_REG_WIDTH))
++#define EIP93_REG_PRNG_SEED_0		((PRNG_BASE)+(0x02 * EIP93_REG_WIDTH))
++#define EIP93_REG_PRNG_SEED_1		((PRNG_BASE)+(0x03 * EIP93_REG_WIDTH))
++#define EIP93_REG_PRNG_SEED_2		((PRNG_BASE)+(0x04 * EIP93_REG_WIDTH))
++#define EIP93_REG_PRNG_SEED_3		((PRNG_BASE)+(0x05 * EIP93_REG_WIDTH))
++#define EIP93_REG_PRNG_KEY_0		((PRNG_BASE)+(0x06 * EIP93_REG_WIDTH))
++#define EIP93_REG_PRNG_KEY_1		((PRNG_BASE)+(0x07 * EIP93_REG_WIDTH))
++#define EIP93_REG_PRNG_KEY_2		((PRNG_BASE)+(0x08 * EIP93_REG_WIDTH))
++#define EIP93_REG_PRNG_KEY_3		((PRNG_BASE)+(0x09 * EIP93_REG_WIDTH))
++#define EIP93_REG_PRNG_RES_0		((PRNG_BASE)+(0x0A * EIP93_REG_WIDTH))
++#define EIP93_REG_PRNG_RES_1		((PRNG_BASE)+(0x0B * EIP93_REG_WIDTH))
++#define EIP93_REG_PRNG_RES_2		((PRNG_BASE)+(0x0C * EIP93_REG_WIDTH))
++#define EIP93_REG_PRNG_RES_3		((PRNG_BASE)+(0x0D * EIP93_REG_WIDTH))
++#define EIP93_REG_PRNG_LFSR_0		((PRNG_BASE)+(0x0E * EIP93_REG_WIDTH))
++#define EIP93_REG_PRNG_LFSR_1		((PRNG_BASE)+(0x0F * EIP93_REG_WIDTH))
++
++/*-----------------------------------------------------------------------------
++ * Constants & masks
++ */
++
++#define EIP93_SUPPORTED_INTERRUPTS_MASK	0xffff7f00
++#define EIP93_PRNG_DT_TEXT_LOWERHALF	0xDEAD
++#define EIP93_PRNG_DT_TEXT_UPPERHALF	0xC0DE
++#define EIP93_10BITS_MASK		0X3FF
++#define EIP93_12BITS_MASK		0XFFF
++#define EIP93_4BITS_MASK		0X04
++#define EIP93_20BITS_MASK		0xFFFFF
++
++#define EIP93_MIN_DESC_DONE_COUNT	0
++#define EIP93_MAX_DESC_DONE_COUNT	15
++
++#define EIP93_MIN_DESC_PENDING_COUNT	0
++#define EIP93_MAX_DESC_PENDING_COUNT	1023
++
++#define EIP93_MIN_TIMEOUT_COUNT		0
++#define EIP93_MAX_TIMEOUT_COUNT		15
++
++#define EIP93_MIN_PE_INPUT_THRESHOLD	1
++#define EIP93_MAX_PE_INPUT_THRESHOLD	511
++
++#define EIP93_MIN_PE_OUTPUT_THRESHOLD	1
++#define EIP93_MAX_PE_OUTPUT_THRESHOLD	432
++
++#define EIP93_MIN_PE_RING_SIZE		1
++#define EIP93_MAX_PE_RING_SIZE		1023
++
++#define EIP93_MIN_PE_DESCRIPTOR_SIZE	7
++#define EIP93_MAX_PE_DESCRIPTOR_SIZE	15
++
++//3DES keys,seed,known data and its result
++#define EIP93_KEY_0			0x133b3454
++#define EIP93_KEY_1			0x5e5b890b
++#define EIP93_KEY_2			0x5eb30757
++#define EIP93_KEY_3			0x93ab15f7
++#define EIP93_SEED_0			0x62c4bf5e
++#define EIP93_SEED_1			0x972667c8
++#define EIP93_SEED_2			0x6345bf67
++#define EIP93_SEED_3			0xcb3482bf
++#define EIP93_LFSR_0			0xDEADC0DE
++#define EIP93_LFSR_1			0xBEEFF00D
++
++/*-----------------------------------------------------------------------------
++ * EIP93 device initialization specifics
++ */
++
++/*----------------------------------------------------------------------------
++ * Byte Order Reversal Mechanisms Supported in EIP93
++ * EIP93_BO_REVERSE_HALF_WORD : reverse the byte order within a half-word
++ * EIP93_BO_REVERSE_WORD :  reverse the byte order within a word
++ * EIP93_BO_REVERSE_DUAL_WORD : reverse the byte order within a dual-word
++ * EIP93_BO_REVERSE_QUAD_WORD : reverse the byte order within a quad-word
++ */
++enum EIP93_Byte_Order_Value_t {
++	EIP93_BO_REVERSE_HALF_WORD = 1,
++	EIP93_BO_REVERSE_WORD = 2,
++	EIP93_BO_REVERSE_DUAL_WORD = 4,
++	EIP93_BO_REVERSE_QUAD_WORD = 8,
++};
++
++/*----------------------------------------------------------------------------
++ * Byte Order Reversal Mechanisms Supported in EIP93 for Target Data
++ * EIP93_BO_REVERSE_HALF_WORD : reverse the byte order within a half-word
++ * EIP93_BO_REVERSE_WORD :  reverse the byte order within a word
++ */
++enum EIP93_Byte_Order_Value_TD_t {
++	EIP93_BO_REVERSE_HALF_WORD_TD = 1,
++	EIP93_BO_REVERSE_WORD_TD = 2,
++};
++
++// BYTE_ORDER_CFG register values
++#define EIP93_BYTE_ORDER_PD		EIP93_BO_REVERSE_WORD
++#define EIP93_BYTE_ORDER_SA		EIP93_BO_REVERSE_WORD
++#define EIP93_BYTE_ORDER_DATA		EIP93_BO_REVERSE_WORD
++#define EIP93_BYTE_ORDER_TD		EIP93_BO_REVERSE_WORD_TD
++
++// INT_CFG register values
++#define EIP93_INT_HOST_OUTPUT_TYPE	0
++#define EIP93_INT_PULSE_CLEAR		0
++
++/*
++ * Interrupts of EIP93
++ */
++
++enum EIP93_InterruptSource_t {
++	EIP93_INT_PE_CDRTHRESH_REQ =	BIT(0),
++	EIP93_INT_PE_RDRTHRESH_REQ =	BIT(1),
++	EIP93_INT_PE_OPERATION_DONE =	BIT(9),
++	EIP93_INT_PE_INBUFTHRESH_REQ =	BIT(10),
++	EIP93_INT_PE_OUTBURTHRSH_REQ =	BIT(11),
++	EIP93_INT_PE_PRNG_IRQ =		BIT(12),
++	EIP93_INT_PE_ERR_REG =		BIT(13),
++	EIP93_INT_PE_RD_DONE_IRQ =	BIT(16),
++};
++
++union peConfig_w {
++	u32 word;
++	struct {
++		u32 resetPE		:1;
++		u32 resetRing		:1;
++		u32 reserved		:6;
++		u32 peMode		:2;
++		u32 enCDRupdate		:1;
++		u32 reserved2		:5;
++		u32 swapCDRD		:1;
++		u32 swapSA		:1;
++		u32 swapData		:1;
++		u32 reserved3		:13;
++	} bits;
++} __packed;
++
++union peEndianCfg_w {
++	u32 word;
++	struct {
++		u32 masterByteSwap	:8;
++		u32 reserved		:8;
++		u32 targetByteSwap	:8;
++		u32 reserved2		:8;
++	} bits;
++} __packed;
++
++union peIntCfg_w {
++	u32 word;
++	struct {
++		u32 PulseClear		:1;
++		u32 IntType		:1;
++		u32 reserved		:30;
++	} bits;
++} __packed;
++
++union peClockCfg_w {
++	u32 word;
++	struct {
++		u32 enPEclk		:1;
++		u32 enDESclk		:1;
++		u32 enAESclk		:1;
++		u32 reserved		:1;
++		u32 enHASHclk		:1;
++		u32 reserved2		:27;
++	} bits;
++} __packed;
++
++union peBufThresh_w {
++	u32 word;
++	struct {
++		u32 inputBuffer		:8;
++		u32 reserved		:8;
++		u32 outputBuffer	:8;
++		u32 reserved2		:8;
++	} bits;
++} __packed;
++
++union peRingThresh_w {
++	u32 word;
++	struct {
++		u32 CDRThresh		:10;
++		u32 reserved		:6;
++		u32 RDRThresh		:10;
++		u32 RDTimeout		:4;
++		u32 reserved2		:1;
++		u32 enTimeout		:1;
++	} bits;
++} __packed;
++
++union peRingCfg_w {
++	u32 word;
++	struct {
++		u32 ringSize		:10;
++		u32 reserved		:6;
++		u32 ringOffset		:8;
++		u32 reserved2		:8;
++	} bits;
++} __packed;
++
++union saCmd0 {
++	u32	word;
++	struct {
++		u32 opCode		:3;
++		u32 direction		:1;
++		u32 opGroup		:2;
++		u32 padType		:2;
++		u32 cipher		:4;
++		u32 hash		:4;
++		u32 reserved2		:1;
++		u32 scPad		:1;
++		u32 extPad		:1;
++		u32 hdrProc		:1;
++		u32 digestLength	:4;
++		u32 ivSource		:2;
++		u32 hashSource		:2;
++		u32 saveIv		:1;
++		u32 saveHash		:1;
++		u32 reserved1		:2;
++	} bits;
++} __packed;
++
++union saCmd1 {
++	u32	word;
++	struct {
++		u32 copyDigest		:1;
++		u32 copyHeader		:1;
++		u32 copyPayload		:1;
++		u32 copyPad		:1;
++		u32 reserved4		:4;
++		u32 cipherMode		:2;
++		u32 reserved3		:1;
++		u32 sslMac		:1;
++		u32 hmac		:1;
++		u32 byteOffset		:1;
++		u32 reserved2		:2;
++		u32 hashCryptOffset	:8;
++		u32 aesKeyLen		:3;
++		u32 reserved1		:1;
++		u32 aesDecKey		:1;
++		u32 seqNumCheck		:1;
++		u32 reserved0		:2;
++	} bits;
++} __packed;
++
++struct saRecord_s {
++	union saCmd0	saCmd0;
++	union saCmd1	saCmd1;
++	u32		saKey[8];
++	u32		saIDigest[8];
++	u32		saODigest[8];
++	u32		saSpi;
++	u32		saSeqNum[2];
++	u32		saSeqNumMask[2];
++	u32		saNonce;
++} __packed;
++
++struct saState_s {
++	u32	stateIv[4];
++	u32	stateByteCnt[2];
++	u32	stateIDigest[8];
++} __packed;
++
++union peCrtlStat_w {
++	u32 word;
++	struct {
++		u32 hostReady		:1;
++		u32 peReady		:1;
++		u32 reserved		:1;
++		u32 initArc4		:1;
++		u32 hashFinal		:1;
++		u32 haltMode		:1;
++		u32 prngMode		:2;
++		u32 padValue		:8;
++		u32 errStatus		:8;
++		u32 padCrtlStat		:8;
++	} bits;
++} __packed;
++
++union  peLength_w {
++	u32 word;
++	struct {
++		u32 length		:20;
++		u32 reserved		:2;
++		u32 hostReady		:1;
++		u32 peReady		:1;
++		u32 byPass		:8;
++	} bits;
++} __packed;
++
++struct eip93_descriptor_s {
++	union peCrtlStat_w	peCrtlStat;
++	u32			srcAddr;
++	u32			dstAddr;
++	u32			saAddr;
++	u32			stateAddr;
++	u32			arc4Addr;
++	u32			userId;
++	union peLength_w	peLength;
++} __packed;
++
++#endif
+--- a/drivers/crypto/Kconfig
++++ b/drivers/crypto/Kconfig
+@@ -824,4 +824,6 @@ config CRYPTO_DEV_SA2UL
+ source "drivers/crypto/keembay/Kconfig"
+ source "drivers/crypto/aspeed/Kconfig"
+ 
++source "drivers/crypto/mtk-eip93/Kconfig"
++
+ endif # CRYPTO_HW
+--- a/drivers/crypto/Makefile
++++ b/drivers/crypto/Makefile
+@@ -53,3 +53,4 @@ obj-y += xilinx/
+ obj-y += hisilicon/
+ obj-$(CONFIG_CRYPTO_DEV_AMLOGIC_GXL) += amlogic/
+ obj-y += keembay/
++obj-$(CONFIG_CRYPTO_DEV_EIP93) += mtk-eip93/
diff --git a/target/linux/ramips/rt288x/config-6.1 b/target/linux/ramips/rt288x/config-6.1
new file mode 100644
index 00000000000000..d8b89934b99e00
--- /dev/null
+++ b/target/linux/ramips/rt288x/config-6.1
@@ -0,0 +1,201 @@
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MMAP_RND_BITS_MAX=15
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CEVT_R4K=y
+CONFIG_CLK_MTMIPS=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
+CONFIG_CMDLINE_BOOL=y
+# CONFIG_CMDLINE_OVERRIDE is not set
+CONFIG_COMMON_CLK=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_DIEI=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_RIXI=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_MIPS32=y
+# CONFIG_CPU_MIPS32_R1 is not set
+CONFIG_CPU_MIPS32_R2=y
+CONFIG_CPU_MIPSR2=y
+CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
+CONFIG_CPU_R4K_CACHE_TLB=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CPU_SUPPORTS_MSA=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CSRC_R4K=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DMA_NONCOHERENT=y
+# CONFIG_DTB_RT2880_EVAL is not set
+CONFIG_DTB_RT_NONE=y
+CONFIG_DTC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_FIXED_PHY=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC11_NO_ARRAY_BOUNDS=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_LIB_ASHLDI3=y
+CONFIG_GENERIC_LIB_ASHRDI3=y
+CONFIG_GENERIC_LIB_CMPDI2=y
+CONFIG_GENERIC_LIB_LSHRDI3=y
+CONFIG_GENERIC_LIB_UCMPDI2=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_RALINK=y
+CONFIG_HARDWARE_WATCHPOINTS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HZ_PERIODIC=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IP17XX_PHY=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_INTC=y
+CONFIG_IRQ_MIPS_CPU=y
+CONFIG_IRQ_WORK=y
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MEMFD_CREATE=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MIPS=y
+CONFIG_MIPS_ASID_BITS=8
+CONFIG_MIPS_ASID_SHIFT=0
+CONFIG_MIPS_AUTO_PFN_OFFSET=y
+CONFIG_MIPS_CLOCK_VSYSCALL=y
+# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set
+# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
+CONFIG_MIPS_CMDLINE_FROM_DTB=y
+CONFIG_MIPS_L1_CACHE_SHIFT=4
+CONFIG_MIPS_L1_CACHE_SHIFT_4=y
+CONFIG_MIPS_LD_CAN_LINK_VDSO=y
+# CONFIG_MIPS_NO_APPENDED_DTB is not set
+CONFIG_MIPS_RAW_APPENDED_DTB=y
+CONFIG_MIPS_SPRAM=y
+CONFIG_MODULES_USE_ELF_REL=y
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y
+CONFIG_MTD_SPLIT_LZMA_FW=y
+CONFIG_MTD_SPLIT_UIMAGE_FW=y
+CONFIG_MTD_SPLIT_WRGG_FW=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NET_RALINK_MDIO=y
+CONFIG_NET_RALINK_MDIO_RT2880=y
+CONFIG_NET_RALINK_RT2880=y
+CONFIG_NET_RALINK_SOC=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_VENDOR_RALINK=y
+CONFIG_NLS=m
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DRIVERS_LEGACY=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+# CONFIG_PHY_MT7621_PCI is not set
+# CONFIG_PHY_RALINK_USB is not set
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_AW9523 is not set
+CONFIG_PINCTRL_RALINK=y
+CONFIG_PINCTRL_RT2880=y
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_RALINK=y
+CONFIG_RALINK_WDT=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RATIONAL=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_SERIAL_8250_RT288X=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_SOC_MT7620 is not set
+# CONFIG_SOC_MT7621 is not set
+CONFIG_SOC_RT288X=y
+# CONFIG_SOC_RT305X is not set
+# CONFIG_SOC_RT3883 is not set
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+# CONFIG_SPI_MT7621 is not set
+CONFIG_SPI_RT2880=y
+CONFIG_SRCU=y
+CONFIG_SWCONFIG=y
+CONFIG_SWPHY=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_MIPS16=y
+CONFIG_SYS_SUPPORTS_ZBOOT=y
+CONFIG_TARGET_ISA_REV=2
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TINY_SRCU=y
+CONFIG_USB=m
+CONFIG_USB_COMMON=m
+CONFIG_USB_EHCI_HCD=m
+CONFIG_USB_EHCI_HCD_PLATFORM=m
+CONFIG_USB_OHCI_HCD=m
+CONFIG_USB_OHCI_HCD_PLATFORM=m
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_ZBOOT_LOAD_ADDRESS=0x0
diff --git a/target/linux/ramips/rt305x/config-6.1 b/target/linux/ramips/rt305x/config-6.1
new file mode 100644
index 00000000000000..8b1b17033a911c
--- /dev/null
+++ b/target/linux/ramips/rt305x/config-6.1
@@ -0,0 +1,196 @@
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MMAP_RND_BITS_MAX=15
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CEVT_R4K=y
+CONFIG_CEVT_SYSTICK_QUIRK=y
+CONFIG_CLKEVT_RT3352=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLK_MTMIPS=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
+CONFIG_CMDLINE_BOOL=y
+# CONFIG_CMDLINE_OVERRIDE is not set
+CONFIG_COMMON_CLK=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_DIEI=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_RIXI=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_MIPS32=y
+# CONFIG_CPU_MIPS32_R1 is not set
+CONFIG_CPU_MIPS32_R2=y
+CONFIG_CPU_MIPSR2=y
+CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
+CONFIG_CPU_R4K_CACHE_TLB=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CPU_SUPPORTS_MSA=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CSRC_R4K=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_PINCTRL=y
+CONFIG_DMA_NONCOHERENT=y
+# CONFIG_DTB_RT305X_EVAL is not set
+CONFIG_DTB_RT_NONE=y
+CONFIG_DTC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_FIXED_PHY=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC11_NO_ARRAY_BOUNDS=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_LIB_ASHLDI3=y
+CONFIG_GENERIC_LIB_ASHRDI3=y
+CONFIG_GENERIC_LIB_CMPDI2=y
+CONFIG_GENERIC_LIB_LSHRDI3=y
+CONFIG_GENERIC_LIB_UCMPDI2=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_RALINK=y
+CONFIG_GPIO_WATCHDOG=y
+# CONFIG_GPIO_WATCHDOG_ARCH_INITCALL is not set
+CONFIG_HARDWARE_WATCHPOINTS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HZ_PERIODIC=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_INTC=y
+CONFIG_IRQ_MIPS_CPU=y
+CONFIG_IRQ_WORK=y
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MEMFD_CREATE=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MIPS=y
+CONFIG_MIPS_ASID_BITS=8
+CONFIG_MIPS_ASID_SHIFT=0
+CONFIG_MIPS_CLOCK_VSYSCALL=y
+# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set
+# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
+CONFIG_MIPS_CMDLINE_FROM_DTB=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+CONFIG_MIPS_LD_CAN_LINK_VDSO=y
+# CONFIG_MIPS_NO_APPENDED_DTB is not set
+CONFIG_MIPS_RAW_APPENDED_DTB=y
+CONFIG_MIPS_SPRAM=y
+CONFIG_MODULES_USE_ELF_REL=y
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y
+CONFIG_MTD_SPLIT_JIMAGE_FW=y
+CONFIG_MTD_SPLIT_SEAMA_FW=y
+CONFIG_MTD_SPLIT_UIMAGE_FW=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NET_RALINK_ESW_RT3050=y
+CONFIG_NET_RALINK_RT3050=y
+CONFIG_NET_RALINK_SOC=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_VENDOR_RALINK=y
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
+CONFIG_PCI_DRIVERS_LEGACY=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+# CONFIG_PHY_MT7621_PCI is not set
+CONFIG_PHY_RALINK_USB=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_AW9523 is not set
+CONFIG_PINCTRL_RALINK=y
+CONFIG_PINCTRL_RT305X=y
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_RALINK=y
+# CONFIG_RALINK_ILL_ACC is not set
+CONFIG_RALINK_WDT=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RATIONAL=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_SERIAL_8250_RT288X=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_SOC_MT7620 is not set
+# CONFIG_SOC_MT7621 is not set
+# CONFIG_SOC_RT288X is not set
+CONFIG_SOC_RT305X=y
+# CONFIG_SOC_RT3883 is not set
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+# CONFIG_SPI_MT7621 is not set
+CONFIG_SPI_RT2880=y
+CONFIG_SRCU=y
+CONFIG_SWCONFIG=y
+CONFIG_SWPHY=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_MIPS16=y
+CONFIG_SYS_SUPPORTS_ZBOOT=y
+CONFIG_TARGET_ISA_REV=2
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TINY_SRCU=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_ZBOOT_LOAD_ADDRESS=0x0
diff --git a/target/linux/ramips/rt3883/config-6.1 b/target/linux/ramips/rt3883/config-6.1
new file mode 100644
index 00000000000000..2aaebdc702f243
--- /dev/null
+++ b/target/linux/ramips/rt3883/config-6.1
@@ -0,0 +1,196 @@
+CONFIG_AR8216_PHY=y
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MMAP_RND_BITS_MAX=15
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CEVT_R4K=y
+CONFIG_CLK_MTMIPS=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
+CONFIG_CMDLINE_BOOL=y
+# CONFIG_CMDLINE_OVERRIDE is not set
+CONFIG_COMMON_CLK=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_DIEI=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_RIXI=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_MIPS32=y
+# CONFIG_CPU_MIPS32_R1 is not set
+CONFIG_CPU_MIPS32_R2=y
+CONFIG_CPU_MIPSR2=y
+CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
+CONFIG_CPU_R4K_CACHE_TLB=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CPU_SUPPORTS_MSA=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CSRC_R4K=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_PINCTRL=y
+CONFIG_DMA_NONCOHERENT=y
+# CONFIG_DTB_RT3883_EVAL is not set
+CONFIG_DTB_RT_NONE=y
+CONFIG_DTC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_ETHERNET_PACKET_MANGLE=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_FIXED_PHY=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC11_NO_ARRAY_BOUNDS=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_LIB_ASHLDI3=y
+CONFIG_GENERIC_LIB_ASHRDI3=y
+CONFIG_GENERIC_LIB_CMPDI2=y
+CONFIG_GENERIC_LIB_LSHRDI3=y
+CONFIG_GENERIC_LIB_UCMPDI2=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_RALINK=y
+CONFIG_HARDWARE_WATCHPOINTS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HZ_PERIODIC=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_INTC=y
+CONFIG_IRQ_MIPS_CPU=y
+CONFIG_IRQ_WORK=y
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MEMFD_CREATE=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MIPS=y
+CONFIG_MIPS_ASID_BITS=8
+CONFIG_MIPS_ASID_SHIFT=0
+CONFIG_MIPS_CLOCK_VSYSCALL=y
+# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set
+# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
+CONFIG_MIPS_CMDLINE_FROM_DTB=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+CONFIG_MIPS_LD_CAN_LINK_VDSO=y
+# CONFIG_MIPS_NO_APPENDED_DTB is not set
+CONFIG_MIPS_RAW_APPENDED_DTB=y
+CONFIG_MIPS_SPRAM=y
+CONFIG_MODULES_USE_ELF_REL=y
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y
+CONFIG_MTD_SPLIT_SEAMA_FW=y
+CONFIG_MTD_SPLIT_UIMAGE_FW=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NET_RALINK_MDIO=y
+CONFIG_NET_RALINK_MDIO_RT2880=y
+CONFIG_NET_RALINK_RT3883=y
+CONFIG_NET_RALINK_SOC=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_VENDOR_RALINK=y
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DRIVERS_LEGACY=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+# CONFIG_PHY_MT7621_PCI is not set
+CONFIG_PHY_RALINK_USB=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_AW9523 is not set
+CONFIG_PINCTRL_RALINK=y
+CONFIG_PINCTRL_RT3883=y
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_RALINK=y
+CONFIG_RALINK_WDT=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RATIONAL=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RTL8366_SMI=y
+CONFIG_RTL8367B_PHY=y
+CONFIG_RTL8367_PHY=y
+CONFIG_SERIAL_8250_RT288X=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_SOC_MT7620 is not set
+# CONFIG_SOC_MT7621 is not set
+# CONFIG_SOC_RT288X is not set
+# CONFIG_SOC_RT305X is not set
+CONFIG_SOC_RT3883=y
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+# CONFIG_SPI_MT7621 is not set
+CONFIG_SPI_RT2880=y
+CONFIG_SRCU=y
+CONFIG_SWCONFIG=y
+CONFIG_SWPHY=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_MIPS16=y
+CONFIG_SYS_SUPPORTS_ZBOOT=y
+CONFIG_TARGET_ISA_REV=2
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TINY_SRCU=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_ZBOOT_LOAD_ADDRESS=0x0
diff --git a/target/linux/realtek/base-files/etc/board.d/02_network b/target/linux/realtek/base-files/etc/board.d/02_network
index fb9c28d7948e38..db1d99f4ec313e 100644
--- a/target/linux/realtek/base-files/etc/board.d/02_network
+++ b/target/linux/realtek/base-files/etc/board.d/02_network
@@ -3,25 +3,26 @@
 . /lib/functions/uci-defaults.sh
 . /lib/functions/system.sh
 
-ucidef_set_poe() {
-	json_select_object poe
-		json_add_string "budget" "$1"
-		json_select_array ports
-			for port in $2; do
-				if [ -n "$3" -a -n "$(expr "$3" : "\(.\+[[:space:]]\)\{0,1\}$port\([[:space:]].*\|\$\)")" ]; then
-					continue # skip ports passed via $3
-				fi
-				json_add_string "" "$port"
-			done
-		json_select ..
-	json_select ..
+_filter_port_list_ordered() {
+	local ports="$1"
+	local excluded="$2"
+	local sort_opts="$3"
+	echo $ports $excluded | xargs -n1 basename | sort -V $sort_opts | uniq -u | xargs
+}
+
+filter_port_list() {
+	_filter_port_list_ordered "$1" "$2"
+}
+
+filter_port_list_reverse() {
+	_filter_port_list_ordered "$1" "$2" "-r"
 }
 
 board=$(board_name)
 board_config_update
 
 lan_list=$(ls -1 -v -d /sys/class/net/lan* | xargs -n1 basename | xargs)
-lan_list_rev=$(ls -1 -v -d -r /sys/class/net/lan* | xargs -n1 basename | xargs)
+
 ucidef_set_bridge_device switch
 ucidef_set_interface_lan "$lan_list"
 
@@ -70,35 +71,35 @@ done
 
 case $board in
 d-link,dgs-1210-10mp-f)
-	ucidef_set_poe 130 "$lan_list" "lan9 lan10"
+	ucidef_set_poe 130 "$(filter_port_list "$lan_list" "lan9 lan10")"
 	;;
 d-link,dgs-1210-10p)
-	ucidef_set_poe 65 "$lan_list" "lan9 lan10"
+	ucidef_set_poe 65 "$(filter_port_list "$lan_list" "lan9 lan10")"
 	;;
 d-link,dgs-1210-28mp-f)
 	ucidef_set_poe 370 "lan8 lan7 lan6 lan5 lan4 lan3 lan2 lan1 lan16 lan15 lan14 lan13 lan12 lan11 lan10 lan9 lan24 lan23
-			lan22 lan21 lan20 lan19 lan18 lan17" "lan25 lan26 lan27 lan28"
+			lan22 lan21 lan20 lan19 lan18 lan17"
 	;;
 engenius,ews2910p)
-	ucidef_set_poe 60 "$lan_list" "lan9 lan10"
+	ucidef_set_poe 60 "$(filter_port_list "$lan_list" "lan9 lan10")"
 	;;
 hpe,1920-8g-poe-65w)
-	ucidef_set_poe 65 "$lan_list_rev" "lan9 lan10"
+	ucidef_set_poe 65 "$(filter_port_list_reversed "$lan_list" "lan9 lan10")"
 	;;
 hpe,1920-8g-poe-180w)
-	ucidef_set_poe 180 "$lan_list_rev" "lan9 lan10"
+	ucidef_set_poe 180 "$(filter_port_list_reversed "$lan_list" "lan9 lan10")"
 	;;
 netgear,gs110tpp-v1)
-	ucidef_set_poe 130 "$lan_list" "lan9 lan10"
+	ucidef_set_poe 130 "$(filter_port_list "$lan_list" "lan9 lan10")"
 	;;
 netgear,gs110tup-v1)
-	ucidef_set_poe 240 "$lan_list" "lan9 lan10"
+	ucidef_set_poe 240 "$(filter_port_list "$lan_list" "lan9 lan10")"
 	;;
 netgear,gs310tp-v1)
-	ucidef_set_poe 55 "$lan_list" "lan9 lan10"
+	ucidef_set_poe 55 "$(filter_port_list "$lan_list" "lan9 lan10")"
 	;;
 zyxel,gs1900-10hp)
-	ucidef_set_poe 77 "$lan_list" "lan9 lan10"
+	ucidef_set_poe 77 "$(filter_port_list "$lan_list" "lan9 lan10")"
 	;;
 zyxel,gs1900-8hp-v1|\
 zyxel,gs1900-8hp-v2)
@@ -106,7 +107,7 @@ zyxel,gs1900-8hp-v2)
 	;;
 zyxel,gs1900-24hp-v1|\
 zyxel,gs1900-24hp-v2)
-	ucidef_set_poe 170 "$lan_list" "lan25 lan26"
+	ucidef_set_poe 170 "$(filter_port_list "$lan_list" "lan25 lan26")"
 	;;
 esac
 
diff --git a/target/linux/realtek/dts-5.15/rtl8380_engenius_ews2910p.dts b/target/linux/realtek/dts-5.15/rtl8380_engenius_ews2910p.dts
index 9b5ddb5ed4110f..289ec8627407e3 100644
--- a/target/linux/realtek/dts-5.15/rtl8380_engenius_ews2910p.dts
+++ b/target/linux/realtek/dts-5.15/rtl8380_engenius_ews2910p.dts
@@ -3,6 +3,7 @@
 #include "rtl838x.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/gpio/gpio.h>
 
 / {
@@ -79,7 +80,8 @@
 		compatible = "gpio-leds";
 
 		led_power: led-0 {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
 		};
 
@@ -89,7 +91,8 @@
 		};
 
 		led_fault: led-2 {
-			label = "amber:fault";
+			function = LED_FUNCTION_FAULT;
+			color = <LED_COLOR_ID_AMBER>;
 			gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/target/linux/realtek/dts-5.15/rtl8380_netgear_gs108t-v3.dts b/target/linux/realtek/dts-5.15/rtl8380_netgear_gs108t-v3.dts
index c1d72b880b1948..b26ebb980681e5 100644
--- a/target/linux/realtek/dts-5.15/rtl8380_netgear_gs108t-v3.dts
+++ b/target/linux/realtek/dts-5.15/rtl8380_netgear_gs108t-v3.dts
@@ -19,14 +19,12 @@
 		compatible = "gpio-leds";
 
 		led_power_amber: led-0 {
-			label = "amber:power";
 			color = <LED_COLOR_ID_AMBER>;
 			function = LED_FUNCTION_POWER;
 			gpios = <&gpio1 32 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_green: led-1 {
-			label = "green:power";
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_POWER;
 			gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
diff --git a/target/linux/realtek/dts-5.15/rtl8380_netgear_gs110tpp-v1.dts b/target/linux/realtek/dts-5.15/rtl8380_netgear_gs110tpp-v1.dts
index 599b2e3b51f7c9..f694ae3317c685 100644
--- a/target/linux/realtek/dts-5.15/rtl8380_netgear_gs110tpp-v1.dts
+++ b/target/linux/realtek/dts-5.15/rtl8380_netgear_gs110tpp-v1.dts
@@ -18,21 +18,18 @@
 		compatible = "gpio-leds";
 
 		led_status_red: led-0 {
-			label = "red:status";
 			color = <LED_COLOR_ID_RED>;
 			function = LED_FUNCTION_STATUS;
 			gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status_green: led-1 {
-			label = "green:status";
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_STATUS;
 			gpios = <&gpio1 32 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status_blue: led-2 {
-			label = "blue:status";
 			color = <LED_COLOR_ID_BLUE>;
 			function = LED_FUNCTION_STATUS;
 			gpios = <&gpio1 34 GPIO_ACTIVE_LOW>;
diff --git a/target/linux/realtek/dts-5.15/rtl8380_netgear_gs110tup-v1.dts b/target/linux/realtek/dts-5.15/rtl8380_netgear_gs110tup-v1.dts
index 76653fa210dac1..335aff2cf04691 100644
--- a/target/linux/realtek/dts-5.15/rtl8380_netgear_gs110tup-v1.dts
+++ b/target/linux/realtek/dts-5.15/rtl8380_netgear_gs110tup-v1.dts
@@ -18,21 +18,18 @@
 		compatible = "gpio-leds";
 
 		led_status_red: led-0 {
-			label = "red:status";
 			color = <LED_COLOR_ID_RED>;
 			function = LED_FUNCTION_STATUS;
 			gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status_green: led-1 {
-			label = "green:status";
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_STATUS;
 			gpios = <&gpio1 32 GPIO_ACTIVE_LOW>;
 		};
 
 		led_status_blue: led-2 {
-			label = "blue:status";
 			color = <LED_COLOR_ID_BLUE>;
 			function = LED_FUNCTION_STATUS;
 			gpios = <&gpio1 34 GPIO_ACTIVE_LOW>;
diff --git a/target/linux/realtek/dts-5.15/rtl8380_netgear_gs308t-v1.dts b/target/linux/realtek/dts-5.15/rtl8380_netgear_gs308t-v1.dts
index 5cf3ca0c81a1ca..5d77cf8c364fb8 100644
--- a/target/linux/realtek/dts-5.15/rtl8380_netgear_gs308t-v1.dts
+++ b/target/linux/realtek/dts-5.15/rtl8380_netgear_gs308t-v1.dts
@@ -19,14 +19,12 @@
 		compatible = "gpio-leds";
 
 		led_power_amber: led-0 {
-			label = "amber:power";
 			color = <LED_COLOR_ID_AMBER>;
 			function = LED_FUNCTION_POWER;
 			gpios = <&gpio1 32 GPIO_ACTIVE_LOW>;
 		};
 
 		led_power_green: led-1 {
-			label = "green:power";
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_POWER;
 			gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
diff --git a/target/linux/realtek/dts-5.15/rtl8380_panasonic_m8eg-pn28080k.dts b/target/linux/realtek/dts-5.15/rtl8380_panasonic_m8eg-pn28080k.dts
index f9d58f5b66e60e..bd59ff36f450d3 100644
--- a/target/linux/realtek/dts-5.15/rtl8380_panasonic_m8eg-pn28080k.dts
+++ b/target/linux/realtek/dts-5.15/rtl8380_panasonic_m8eg-pn28080k.dts
@@ -28,7 +28,6 @@
 
 &leds {
 	led_status_eco_amber: led-5 {
-		label = "amber:status_eco";
 		gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
 		color = <LED_COLOR_ID_AMBER>;
 		function = LED_FUNCTION_STATUS;
@@ -36,7 +35,6 @@
 	};
 
 	led_status_eco_green: led-6 {
-		label = "green:status_eco";
 		gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
 		color = <LED_COLOR_ID_GREEN>;
 		function = LED_FUNCTION_STATUS;
diff --git a/target/linux/realtek/dts-5.15/rtl8380_tplink_sg2xxx.dtsi b/target/linux/realtek/dts-5.15/rtl8380_tplink_sg2xxx.dtsi
index 0706c55524bb97..d30d7b374e7271 100644
--- a/target/linux/realtek/dts-5.15/rtl8380_tplink_sg2xxx.dtsi
+++ b/target/linux/realtek/dts-5.15/rtl8380_tplink_sg2xxx.dtsi
@@ -3,6 +3,7 @@
 #include "rtl838x.dtsi"
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/gpio/gpio.h>
 
 / {
@@ -38,7 +39,8 @@
 		compatible = "gpio-leds";
 
 		led_power: led-0 {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
 		};
 	};
diff --git a/target/linux/realtek/dts-5.15/rtl8382_apresia_aplgs120gtss.dts b/target/linux/realtek/dts-5.15/rtl8382_apresia_aplgs120gtss.dts
index 15120265c97c33..de17958af19758 100644
--- a/target/linux/realtek/dts-5.15/rtl8382_apresia_aplgs120gtss.dts
+++ b/target/linux/realtek/dts-5.15/rtl8382_apresia_aplgs120gtss.dts
@@ -26,14 +26,12 @@
 		compatible = "gpio-leds";
 
 		led_power: led-0 {
-			label = "green:pwr";
 			gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_POWER;
 		};
 
 		led-1 {
-			label = "red:loop";
 			gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
 			color = <LED_COLOR_ID_RED>;
 			function = LED_FUNCTION_FAULT;
@@ -41,7 +39,6 @@
 
 		/* LED chip is soldered, but no hole on the case */
 		led-2 {
-			label = "green:unused";
 			gpios = <&gpio1 36 GPIO_ACTIVE_LOW>;
 			color = <LED_COLOR_ID_GREEN>;
 		};
diff --git a/target/linux/realtek/dts-5.15/rtl8382_iodata_bsh-g24mb.dts b/target/linux/realtek/dts-5.15/rtl8382_iodata_bsh-g24mb.dts
index 8ea28ed2fde48b..49b55813f9d503 100644
--- a/target/linux/realtek/dts-5.15/rtl8382_iodata_bsh-g24mb.dts
+++ b/target/linux/realtek/dts-5.15/rtl8382_iodata_bsh-g24mb.dts
@@ -27,7 +27,6 @@
 		compatible = "gpio-leds";
 
 		led_sys_loop: led {
-			label = "red:sys_loop";
 			gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_RED>;
 			function = LED_FUNCTION_STATUS;
diff --git a/target/linux/realtek/dts-5.15/rtl8382_panasonic_m16eg-pn28160k.dts b/target/linux/realtek/dts-5.15/rtl8382_panasonic_m16eg-pn28160k.dts
index c3b29a87ff390a..abbfd60085a650 100644
--- a/target/linux/realtek/dts-5.15/rtl8382_panasonic_m16eg-pn28160k.dts
+++ b/target/linux/realtek/dts-5.15/rtl8382_panasonic_m16eg-pn28160k.dts
@@ -42,7 +42,6 @@
 
 &leds {
 	led_status_eco_amber: led-5 {
-		label = "amber:status_eco";
 		gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
 		color = <LED_COLOR_ID_AMBER>;
 		function = LED_FUNCTION_STATUS;
@@ -50,7 +49,6 @@
 	};
 
 	led_status_eco_green: led-6 {
-		label = "green:status_eco";
 		gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
 		color = <LED_COLOR_ID_GREEN>;
 		function = LED_FUNCTION_STATUS;
diff --git a/target/linux/realtek/dts-5.15/rtl8382_panasonic_m24eg-pn28240k.dts b/target/linux/realtek/dts-5.15/rtl8382_panasonic_m24eg-pn28240k.dts
index 1fa9d2cdc7f475..d01352ec560e7f 100644
--- a/target/linux/realtek/dts-5.15/rtl8382_panasonic_m24eg-pn28240k.dts
+++ b/target/linux/realtek/dts-5.15/rtl8382_panasonic_m24eg-pn28240k.dts
@@ -42,7 +42,6 @@
 
 &leds {
 	led_status_eco_amber: led-5 {
-		label = "amber:status_eco";
 		gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
 		color = <LED_COLOR_ID_AMBER>;
 		function = LED_FUNCTION_STATUS;
@@ -50,7 +49,6 @@
 	};
 
 	led_status_eco_green: led-6 {
-		label = "green:status_eco";
 		gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
 		color = <LED_COLOR_ID_GREEN>;
 		function = LED_FUNCTION_STATUS;
diff --git a/target/linux/realtek/dts-5.15/rtl8382_tplink_t1600g-28ts-v3.dts b/target/linux/realtek/dts-5.15/rtl8382_tplink_t1600g-28ts-v3.dts
index 6e9f7baed063d9..d84987d209e278 100644
--- a/target/linux/realtek/dts-5.15/rtl8382_tplink_t1600g-28ts-v3.dts
+++ b/target/linux/realtek/dts-5.15/rtl8382_tplink_t1600g-28ts-v3.dts
@@ -27,7 +27,6 @@
 		compatible = "gpio-leds";
 
 		led_sys: led-0 {
-			label = "green:sys";
 			gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_STATUS;
diff --git a/target/linux/realtek/dts-5.15/rtl8393_panasonic_m48eg-pn28480k.dts b/target/linux/realtek/dts-5.15/rtl8393_panasonic_m48eg-pn28480k.dts
index 6a7eb6eb8137b6..8e7d32de1c3094 100644
--- a/target/linux/realtek/dts-5.15/rtl8393_panasonic_m48eg-pn28480k.dts
+++ b/target/linux/realtek/dts-5.15/rtl8393_panasonic_m48eg-pn28480k.dts
@@ -152,7 +152,6 @@
 
 &leds {
 	led_status_eco_amber: led-5 {
-		label = "amber:status_eco";
 		gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
 		color = <LED_COLOR_ID_AMBER>;
 		function = LED_FUNCTION_STATUS;
@@ -160,7 +159,6 @@
 	};
 
 	led_status_eco_green: led-6 {
-		label = "green:status_eco";
 		gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
 		color = <LED_COLOR_ID_GREEN>;
 		function = LED_FUNCTION_STATUS;
diff --git a/target/linux/realtek/dts-5.15/rtl8393_tplink_sg2452p-v4.dts b/target/linux/realtek/dts-5.15/rtl8393_tplink_sg2452p-v4.dts
index 5ca342f970ddd3..4a19d83fdaf525 100644
--- a/target/linux/realtek/dts-5.15/rtl8393_tplink_sg2452p-v4.dts
+++ b/target/linux/realtek/dts-5.15/rtl8393_tplink_sg2452p-v4.dts
@@ -74,42 +74,36 @@
 		compatible = "gpio-leds";
 
 		led-0 {
-			label = "green:speed";
 			gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_INDICATOR;
 		};
 
 		led-1 {
-			label = "green:poe";
 			gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_INDICATOR;
 		};
 
 		led_sys: led-2 {
-			label = "green:sys";
 			gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_STATUS;
 		};
 
 		led-3 {
-			label = "green:fan";
 			gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_STATUS;
 		};
 
 		led-4 {
-			label = "amber:fan";
 			gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_AMBER>;
 			function = "fault-fan";
 		};
 
 		led-5 {
-			label = "green:poe-max";
 			gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;
 			color = <LED_COLOR_ID_GREEN>;
 			function = "alarm-poe";
diff --git a/target/linux/realtek/dts-5.15/rtl83xx_d-link_dgs-1210_common.dtsi b/target/linux/realtek/dts-5.15/rtl83xx_d-link_dgs-1210_common.dtsi
index 1e3cafa9381d8d..fa623d7a9006ae 100644
--- a/target/linux/realtek/dts-5.15/rtl83xx_d-link_dgs-1210_common.dtsi
+++ b/target/linux/realtek/dts-5.15/rtl83xx_d-link_dgs-1210_common.dtsi
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/gpio/gpio.h>
 
 / {
@@ -22,7 +23,8 @@
 		compatible = "gpio-leds";
 
 		led_power: power {
-			label = "green:power";
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
 		};
 	};
diff --git a/target/linux/realtek/dts-5.15/rtl83xx_panasonic_mxxeg-pn28xx0k.dtsi b/target/linux/realtek/dts-5.15/rtl83xx_panasonic_mxxeg-pn28xx0k.dtsi
index f04e98b9cfec45..c08034b9581db6 100644
--- a/target/linux/realtek/dts-5.15/rtl83xx_panasonic_mxxeg-pn28xx0k.dtsi
+++ b/target/linux/realtek/dts-5.15/rtl83xx_panasonic_mxxeg-pn28xx0k.dtsi
@@ -18,14 +18,12 @@
 		compatible = "gpio-leds";
 
 		led-0 {
-			label = "amber:any_col";
 			gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
 			color = <LED_COLOR_ID_AMBER>;
 			function = LED_FUNCTION_FAULT;
 		};
 
 		led-1 {
-			label = "green:giga";
 			gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_INDICATOR;
@@ -33,7 +31,6 @@
 		};
 
 		led-2 {
-			label = "green:100m";
 			gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_INDICATOR;
@@ -41,7 +38,6 @@
 		};
 
 		led-3 {
-			label = "green:full";
 			gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_INDICATOR;
@@ -49,7 +45,6 @@
 		};
 
 		led-4 {
-			label = "green:loop_history";
 			gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_INDICATOR;
diff --git a/target/linux/realtek/dts-5.15/rtl9302_zyxel_xgs1250-12.dts b/target/linux/realtek/dts-5.15/rtl9302_zyxel_xgs1250-12.dts
index 98ac08b26a9147..0c35d7b004123c 100644
--- a/target/linux/realtek/dts-5.15/rtl9302_zyxel_xgs1250-12.dts
+++ b/target/linux/realtek/dts-5.15/rtl9302_zyxel_xgs1250-12.dts
@@ -6,6 +6,7 @@
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/leds/common.h>
+#include <dt-bindings/thermal/thermal.h>
 
 / {
 	compatible = "zyxel,xgs1250-12", "realtek,rtl838x-soc";
@@ -46,7 +47,6 @@
 		pinctrl-0 = <&pinmux_disable_sys_led>;
 
 		led_pwr_sys: led-0 {
-			label = "green:power";
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_POWER;
 			gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
@@ -71,6 +71,107 @@
 							  // (5G, 10/100) (10G, 5G, 2.5G)
 		led_set2 = <0x0a20 0x0a01>; // LED set 2: 1000MBit, 10GBit
 	};
+
+	thermal-zones {
+		phy24-thermal {
+			/* Poll every 10 seconds */
+			polling-delay-passive = <10000>;
+			polling-delay = <10000>;
+			thermal-sensors = <&phy24>;
+
+			trips {
+				phy24_trip0: phy24-trip0 {
+					/* At 80 degrees turn on fan */
+					temperature = <80000>;
+					hysteresis = <1000>;
+					type = "active";
+				};
+
+				phy24_trip1: phy24-trip1 {
+					/* At 108 degrees phys exceed spec */
+					temperature = <108000>;
+					hysteresis = <5000>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+				map {
+					trip = <&phy24_trip0>;
+					cooling-device = <&chassis_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		phy25-thermal {
+			/* Poll every 10 seconds */
+			polling-delay-passive = <10000>;
+			polling-delay = <10000>;
+			thermal-sensors = <&phy25>;
+
+			trips {
+				phy25_trip0: phy25-trip0 {
+					/* At 80 degrees turn on fan */
+					temperature = <80000>;
+					hysteresis = <1000>;
+					type = "active";
+				};
+
+				phy25_trip1: phy25-trip1 {
+					/* At 108 degrees phys exceed spec */
+					temperature = <108000>;
+					hysteresis = <5000>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+				map {
+					trip = <&phy25_trip0>;
+					cooling-device = <&chassis_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		phy26-thermal {
+			/* Poll every 10 seconds */
+			polling-delay-passive = <10000>;
+			polling-delay = <10000>;
+			thermal-sensors = <&phy26>;
+
+			trips {
+				phy26_trip0: phy26-trip0 {
+					/* At 80 degrees turn on fan */
+					temperature = <80000>;
+					hysteresis = <1000>;
+					type = "active";
+				};
+
+				phy26_trip1: phy26-trip1 {
+					/* At 108 degrees phys exceed spec */
+					temperature = <108000>;
+					hysteresis = <5000>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+				map {
+					trip = <&phy26_trip0>;
+					cooling-device = <&chassis_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+	};
+
+	/* YEN SUN TECHNOLOGY FD122510LL-N fan */
+	chassis_fan: gpio-fan {
+		compatible = "gpio-fan";
+		gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
+		gpio-fan,speed-map = <0    0
+				      7000 1>;
+		#cooling-cells = <2>;
+	};
 };
 
 &spi0 {
@@ -181,6 +282,7 @@
 			sds = < 6 >;
 			// Disabled because we do not know how to bring up again
 			// reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
+			#thermal-sensor-cells = <0>;
 		};
 
 		phy25: ethernet-phy@25 {
@@ -190,6 +292,7 @@
 			sds = < 7 >;
 			// Disabled because we do not know how to bring up again
 			// reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
+			#thermal-sensor-cells = <0>;
 		};
 
 		phy26: ethernet-phy@26 {
@@ -199,6 +302,7 @@
 			sds = < 8 >;
 			// Disabled because we do not know how to bring up again
 			// reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
+			#thermal-sensor-cells = <0>;
 		};
 
 		/* SFP Ports */
@@ -300,17 +404,11 @@
 		port@27 {
 			reg = <27>;
 			label = "lan12";
-			phy-mode = "10gbase-r";
+			phy-mode = "1000base-x";
 			phy-handle = <&phy27>;
 			sfp = <&sfp0>;
 			led-set = <2>;
-
-			fixed-link {
-				speed = <10000>;
-				full-duplex;
-				pause;
-			};
-
+			managed = "in-band-status";
 		};
 
 		port@28 {
diff --git a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/dsa.c b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/dsa.c
index a5b8ccea1c8c62..ff81a4c77b6424 100644
--- a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/dsa.c
+++ b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/dsa.c
@@ -796,7 +796,7 @@ static void rtl93xx_phylink_mac_config(struct dsa_switch *ds, int port,
 					const struct phylink_link_state *state)
 {
 	struct rtl838x_switch_priv *priv = ds->priv;
-	int sds_num, sds_mode;
+	int sds_num;
 	u32 reg;
 
 	pr_info("%s port %d, mode %x, phy-mode: %s, speed %d, link %d\n", __func__,
@@ -811,32 +811,10 @@ static void rtl93xx_phylink_mac_config(struct dsa_switch *ds, int port,
 
 	sds_num = priv->ports[port].sds_num;
 	pr_info("%s SDS is %d\n", __func__, sds_num);
-	if (sds_num >= 0) {
-		switch (state->interface) {
-		case PHY_INTERFACE_MODE_HSGMII:
-			sds_mode = 0x12;
-			break;
-		case PHY_INTERFACE_MODE_1000BASEX:
-			sds_mode = 0x04;
-			break;
-		case PHY_INTERFACE_MODE_XGMII:
-			sds_mode = 0x10;
-			break;
-		case PHY_INTERFACE_MODE_10GBASER:
-		case PHY_INTERFACE_MODE_10GKR:
-			sds_mode = 0x1b; /* 10G 1000X Auto */
-			break;
-		case PHY_INTERFACE_MODE_USXGMII:
-			sds_mode = 0x0d;
-			break;
-		default:
-			pr_err("%s: unknown serdes mode: %s\n",
-			       __func__, phy_modes(state->interface));
-			return;
-		}
-		if (state->interface == PHY_INTERFACE_MODE_10GBASER)
-			rtl9300_serdes_setup(sds_num, state->interface);
-	}
+	if (sds_num >= 0 &&
+	    (state->interface == PHY_INTERFACE_MODE_1000BASEX ||
+	     state->interface == PHY_INTERFACE_MODE_10GBASER))
+		rtl9300_serdes_setup(port, sds_num, state->interface);
 
 	reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
 	reg &= ~(0xf << 3);
diff --git a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl83xx.h b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl83xx.h
index 679f0533b4fc0a..55a6851d4630d8 100644
--- a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl83xx.h
+++ b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl83xx.h
@@ -121,7 +121,7 @@ irqreturn_t rtl839x_switch_irq(int irq, void *dev_id);
 void rtl930x_vlan_profile_dump(int index);
 int rtl9300_sds_power(int mac, int val);
 void rtl9300_sds_rst(int sds_num, u32 mode);
-int rtl9300_serdes_setup(int sds_num, phy_interface_t phy_mode);
+int rtl9300_serdes_setup(int port, int sds_num, phy_interface_t phy_mode);
 void rtl930x_print_matrix(void);
 
 /* RTL931x-specific */
diff --git a/target/linux/realtek/files-5.15/drivers/net/phy/rtl83xx-phy.c b/target/linux/realtek/files-5.15/drivers/net/phy/rtl83xx-phy.c
index c69a5af4bdefd5..56e8a7f49d3128 100644
--- a/target/linux/realtek/files-5.15/drivers/net/phy/rtl83xx-phy.c
+++ b/target/linux/realtek/files-5.15/drivers/net/phy/rtl83xx-phy.c
@@ -53,6 +53,23 @@ extern struct mutex smi_lock;
 
 #define RTL9300_PHY_ID_MASK 0xf0ffffff
 
+/* RTL930X SerDes supports the following modes:
+ * 0x02: SGMII		0x04: 1000BX_FIBER	0x05: FIBER100
+ * 0x06: QSGMII		0x09: RSGMII		0x0d: USXGMII
+ * 0x10: XSGMII		0x12: HISGMII		0x16: 2500Base_X
+ * 0x17: RXAUI_LITE	0x19: RXAUI_PLUS	0x1a: 10G Base-R
+ * 0x1b: 10GR1000BX_AUTO			0x1f: OFF
+ */
+#define RTL930X_SDS_MODE_SGMII		0x02
+#define RTL930X_SDS_MODE_1000BASEX	0x04
+#define RTL930X_SDS_MODE_USXGMII	0x0d
+#define RTL930X_SDS_MODE_XGMII		0x10
+#define RTL930X_SDS_MODE_HSGMII		0x12
+#define RTL930X_SDS_MODE_2500BASEX	0x16
+#define RTL930X_SDS_MODE_10GBASER	0x1a
+#define RTL930X_SDS_OFF			0x1f
+#define RTL930X_SDS_MASK		0x1f
+
 /* This lock protects the state of the SoC automatically polling the PHYs over the SMI
  * bus to detect e.g. link and media changes. For operations on the PHYs such as
  * patching or other configuration changes such as EEE, polling needs to be disabled
@@ -147,13 +164,8 @@ u16 rtl9300_sds_regs[] = { 0x0194, 0x0194, 0x0194, 0x0194, 0x02a0, 0x02a0, 0x02a
 			   0x02A4, 0x02A4, 0x0198, 0x0198 };
 u8  rtl9300_sds_lsb[]  = { 0, 6, 12, 18, 0, 6, 12, 18, 0, 6, 0, 6};
 
-/* Reset the SerDes by powering it off and set a new operations mode
- * of the SerDes. 0x1f is off. Other modes are
- * 0x02: SGMII		0x04: 1000BX_FIBER	0x05: FIBER100
- * 0x06: QSGMII		0x09: RSGMII		0x0d: USXGMII
- * 0x10: XSGMII		0x12: HISGMII		0x16: 2500Base_X
- * 0x17: RXAUI_LITE	0x19: RXAUI_PLUS	0x1a: 10G Base-R
- * 0x1b: 10GR1000BX_AUTO			0x1f: OFF
+/* Reset the SerDes by powering it off and set a new operation mode
+ * of the SerDes.
  */
 void rtl9300_sds_rst(int sds_num, u32 mode)
 {
@@ -163,11 +175,12 @@ void rtl9300_sds_rst(int sds_num, u32 mode)
 		return;
 	}
 
-	sw_w32_mask(0x1f << rtl9300_sds_lsb[sds_num], 0x1f << rtl9300_sds_lsb[sds_num],
+	sw_w32_mask(RTL930X_SDS_MASK << rtl9300_sds_lsb[sds_num],
+		    RTL930X_SDS_OFF << rtl9300_sds_lsb[sds_num],
 		    rtl9300_sds_regs[sds_num]);
 	mdelay(10);
 
-	sw_w32_mask(0x1f << rtl9300_sds_lsb[sds_num], mode << rtl9300_sds_lsb[sds_num],
+	sw_w32_mask(RTL930X_SDS_MASK << rtl9300_sds_lsb[sds_num], mode << rtl9300_sds_lsb[sds_num],
 		    rtl9300_sds_regs[sds_num]);
 	mdelay(10);
 
@@ -183,7 +196,7 @@ void rtl9300_sds_set(int sds_num, u32 mode)
 		return;
 	}
 
-	sw_w32_mask(0x1f << rtl9300_sds_lsb[sds_num], mode << rtl9300_sds_lsb[sds_num],
+	sw_w32_mask(RTL930X_SDS_MASK << rtl9300_sds_lsb[sds_num], mode << rtl9300_sds_lsb[sds_num],
 		    rtl9300_sds_regs[sds_num]);
 	mdelay(10);
 
@@ -203,7 +216,7 @@ u32 rtl9300_sds_mode_get(int sds_num)
 	v = sw_r32(rtl9300_sds_regs[sds_num]);
 	v >>= rtl9300_sds_lsb[sds_num];
 
-	return v & 0x1f;
+	return v & RTL930X_SDS_MASK;
 }
 
 /* On the RTL839x family of SoCs with inbuilt SerDes, these SerDes are accessed through
@@ -274,6 +287,8 @@ int rtl930x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v)
 	sw_w32(v, RTL930X_SDS_INDACS_DATA);
 	cmd = phy_addr << 2 | page << 7 | phy_reg << 13 | 0x3;
 
+	sw_w32(cmd, RTL930X_SDS_INDACS_CMD);
+
 	for (i = 0; i < 100; i++) {
 		if (!(sw_r32(RTL930X_SDS_INDACS_CMD) & 0x1))
 			break;
@@ -1631,7 +1646,9 @@ static int rtl9300_read_status(struct phy_device *phydev)
 
 	mode = rtl9300_sds_mode_get(sds_num);
 	pr_info("%s got SDS mode %02x\n", __func__, mode);
-	if (mode == 0x1a) { /* 10GR mode */
+	if (mode == RTL930X_SDS_OFF)
+		mode = rtl9300_sds_field_r(sds_num, 0x1f, 9, 11, 7);
+	if (mode == RTL930X_SDS_MODE_10GBASER) { /* 10GR mode */
 		status = rtl9300_sds_field_r(sds_num, 0x5, 0, 12, 12);
 		latch_status = rtl9300_sds_field_r(sds_num, 0x4, 1, 2, 2);
 		status |= rtl9300_sds_field_r(sds_num, 0x5, 0, 12, 12);
@@ -1647,10 +1664,13 @@ static int rtl9300_read_status(struct phy_device *phydev)
 
 	if (latch_status) {
 		phydev->link = true;
-		if (mode == 0x1a)
+		if (mode == RTL930X_SDS_MODE_10GBASER) {
 			phydev->speed = SPEED_10000;
-		else
+			phydev->interface = PHY_INTERFACE_MODE_10GBASER;
+		} else {
 			phydev->speed = SPEED_1000;
+			phydev->interface = PHY_INTERFACE_MODE_1000BASEX;
+		}
 
 		phydev->duplex = DUPLEX_FULL;
 	}
@@ -1683,37 +1703,37 @@ void rtl9300_force_sds_mode(int sds, phy_interface_t phy_if)
 	pr_info("%s: SDS: %d, mode %d\n", __func__, sds, phy_if);
 	switch (phy_if) {
 	case PHY_INTERFACE_MODE_SGMII:
-		sds_mode = 0x2;
+		sds_mode = RTL930X_SDS_MODE_SGMII;
 		lc_on = false;
 		lc_value = 0x1;
 		break;
 
 	case PHY_INTERFACE_MODE_HSGMII:
-		sds_mode = 0x12;
+		sds_mode = RTL930X_SDS_MODE_HSGMII;
 		lc_value = 0x3;
 		/* Configure LC */
 		break;
 
 	case PHY_INTERFACE_MODE_1000BASEX:
-		sds_mode = 0x04;
+		sds_mode = RTL930X_SDS_MODE_1000BASEX;
 		lc_on = false;
 		break;
 
 	case PHY_INTERFACE_MODE_2500BASEX:
-		sds_mode = 0x16;
+		sds_mode = RTL930X_SDS_MODE_2500BASEX;
 		lc_value = 0x3;
 		/* Configure LC */
 		break;
 
 	case PHY_INTERFACE_MODE_10GBASER:
-		sds_mode = 0x1a;
+		sds_mode = RTL930X_SDS_MODE_10GBASER;
 		lc_on = true;
 		lc_value = 0x5;
 		break;
 
 	case PHY_INTERFACE_MODE_NA:
 		/* This will disable SerDes */
-		sds_mode = 0x1f;
+		sds_mode = RTL930X_SDS_OFF;
 		break;
 
 	default:
@@ -1733,7 +1753,7 @@ void rtl9300_force_sds_mode(int sds, phy_interface_t phy_if)
 	if (sds == 5) pr_info("%s b %x\n", __func__, rtl930x_read_sds_phy(sds, 0x1f, 9));
 
 	/* SerDes off */
-	rtl9300_sds_field_w(sds, 0x1f, 9, 11, 7, 0x1f);
+	rtl9300_sds_field_w(sds, 0x1f, 9, 11, 7, RTL930X_SDS_OFF);
 
 	if (phy_if == PHY_INTERFACE_MODE_NA)
 		return;
@@ -1846,13 +1866,26 @@ void rtl9300_sds_tx_config(int sds, phy_interface_t phy_if)
 
 	switch(phy_if) {
 	case PHY_INTERFACE_MODE_1000BASEX:
+		pre_amp = 0x1;
+		main_amp = 0x9;
+		post_amp = 0x1;
 		page = 0x25;
 		break;
 	case PHY_INTERFACE_MODE_HSGMII:
 	case PHY_INTERFACE_MODE_2500BASEX:
+		pre_amp = 0;
+		post_amp = 0x8;
+		pre_en = 0;
 		page = 0x29;
 		break;
 	case PHY_INTERFACE_MODE_10GBASER:
+	case PHY_INTERFACE_MODE_USXGMII:
+	case PHY_INTERFACE_MODE_XGMII:
+		pre_en = 0;
+		pre_amp = 0;
+		main_amp = 0x10;
+		post_amp = 0;
+		post_en	= 0;
 		page = 0x2f;
 		break;
 	default:
@@ -2651,7 +2684,7 @@ void rtl9300_do_rx_calibration(int sds, phy_interface_t phy_mode)
 	mdelay(20);
 
 	/* Do this only for 10GR mode, SDS active in mode 0x1a */
-	if (rtl9300_sds_field_r(sds, 0x1f, 9, 11, 7) == 0x1a) {
+	if (rtl9300_sds_field_r(sds, 0x1f, 9, 11, 7) == RTL930X_SDS_MODE_10GBASER) {
 		pr_info("%s: SDS enabled\n", __func__);
 		latch_sts = rtl9300_sds_field_r(sds, 0x4, 1, 2, 2);
 		mdelay(1);
@@ -2698,6 +2731,7 @@ u32 rtl9300_sds_sym_err_get(int sds_num, phy_interface_t phy_mode)
 	case PHY_INTERFACE_MODE_XGMII:
 		break;
 
+	case PHY_INTERFACE_MODE_1000BASEX:
 	case PHY_INTERFACE_MODE_10GBASER:
 		v = rtl930x_read_sds_phy(sds_num, 5, 1);
 		return v & 0xff;
@@ -2722,22 +2756,22 @@ int rtl9300_sds_check_calibration(int sds_num, phy_interface_t phy_mode)
 	errors2 = rtl9300_sds_sym_err_get(sds_num, phy_mode);
 
 	switch (phy_mode) {
-		case PHY_INTERFACE_MODE_XGMII:
-
-			if ((errors2 - errors1 > 100) ||
-			    (errors1 >= 0xffff00) || (errors2 >= 0xffff00)) {
-				pr_info("%s XSGMII error rate too high\n", __func__);
-				return 1;
-			}
-			break;
-		case PHY_INTERFACE_MODE_10GBASER:
-			if (errors2 > 0) {
-				pr_info("%s 10GBASER error rate too high\n", __func__);
-				return 1;
-			}
-			break;
-		default:
+	case PHY_INTERFACE_MODE_1000BASEX:
+	case PHY_INTERFACE_MODE_XGMII:
+		if ((errors2 - errors1 > 100) ||
+		    (errors1 >= 0xffff00) || (errors2 >= 0xffff00)) {
+			pr_info("%s XSGMII error rate too high\n", __func__);
 			return 1;
+		}
+		break;
+	case PHY_INTERFACE_MODE_10GBASER:
+		if (errors2 > 0) {
+			pr_info("%s 10GBASER error rate too high\n", __func__);
+			return 1;
+		}
+		break;
+	default:
+		return 1;
 	}
 
 	return 0;
@@ -2769,53 +2803,83 @@ void rtl9300_phy_enable_10g_1g(int sds_num)
 	pr_info("%s set medium after: %08x\n", __func__, v);
 }
 
+static int rtl9300_sds_10g_idle(int sds_num);
+static void rtl9300_serdes_patch(int sds_num);
+
 #define RTL930X_MAC_FORCE_MODE_CTRL		(0xCA1C)
-/* phy_mode = PHY_INTERFACE_MODE_10GBASER, sds_mode = 0x1a */
-int rtl9300_serdes_setup(int sds_num, phy_interface_t phy_mode)
+int rtl9300_serdes_setup(int port, int sds_num, phy_interface_t phy_mode)
 {
-	int sds_mode;
 	int calib_tries = 0;
 
-	switch (phy_mode) {
-	case PHY_INTERFACE_MODE_HSGMII:
-		sds_mode = 0x12;
-		break;
-	case PHY_INTERFACE_MODE_1000BASEX:
-		sds_mode = 0x04;
-		break;
-	case PHY_INTERFACE_MODE_XGMII:
-		sds_mode = 0x10;
-		break;
-	case PHY_INTERFACE_MODE_10GBASER:
-		sds_mode = 0x1a;
-		break;
-	case PHY_INTERFACE_MODE_USXGMII:
-		sds_mode = 0x0d;
-		break;
-	default:
-		pr_err("%s: unknown serdes mode: %s\n", __func__, phy_modes(phy_mode));
-		return -EINVAL;
-	}
+	/* Turn Off Serdes */
+	rtl9300_sds_rst(sds_num, RTL930X_SDS_OFF);
+
+	/* Apply serdes patches */
+	rtl9300_serdes_patch(sds_num);
 
 	/* Maybe use dal_longan_sds_init */
 
 	/* dal_longan_construct_serdesConfig_init */ /* Serdes Construct */
 	rtl9300_phy_enable_10g_1g(sds_num);
 
-	/* Set Serdes Mode */
-	rtl9300_sds_set(sds_num, 0x1a); /* 0x1b: RTK_MII_10GR1000BX_AUTO */
+	/* Disable MAC */
+	sw_w32_mask(0, 1, RTL930X_MAC_FORCE_MODE_CTRL + 4 * port);
+	mdelay(20);
+
+	/* ----> dal_longan_sds_mode_set */
+	pr_info("%s: Configuring RTL9300 SERDES %d\n", __func__, sds_num);
+
+	/* Configure link to MAC */
+	rtl9300_serdes_mac_link_config(sds_num, true, true);	/* MAC Construct */
+
+	/* Re-Enable MAC */
+	sw_w32_mask(1, 0, RTL930X_MAC_FORCE_MODE_CTRL + 4 * port);
+
+	/* Enable SDS in desired mode */
+	rtl9300_force_sds_mode(sds_num, phy_mode);
+
+	/* Enable Fiber RX */
+	rtl9300_sds_field_w(sds_num, 0x20, 2, 12, 12, 0);
 
-	/* Do RX calibration */
+	/* Calibrate SerDes receiver in loopback mode */
+	rtl9300_sds_10g_idle(sds_num);
 	do {
 		rtl9300_do_rx_calibration(sds_num, phy_mode);
 		calib_tries++;
 		mdelay(50);
 	} while (rtl9300_sds_check_calibration(sds_num, phy_mode) && calib_tries < 3);
+	if (calib_tries >= 3)
+		pr_warn("%s: SerDes RX calibration failed\n", __func__);
 
+	/* Leave loopback mode */
+	rtl9300_sds_tx_config(sds_num, phy_mode);
 
 	return 0;
 }
 
+static int rtl9300_sds_10g_idle(int sds_num)
+{
+	bool busy;
+	int i = 0;
+
+	do {
+		if (sds_num % 2) {
+			rtl9300_sds_field_w(sds_num - 1, 0x1f, 0x2, 15, 0, 53);
+			busy = !!rtl9300_sds_field_r(sds_num - 1, 0x1f, 0x14, 1, 1);
+		} else {
+			rtl9300_sds_field_w(sds_num, 0x1f, 0x2, 15, 0, 53);
+			busy = !!rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 0, 0);
+		}
+		i++;
+	} while (busy && i < 100);
+
+	if (i < 100)
+		return 0;
+
+	pr_warn("%s WARNING: Waiting for RX idle timed out, SDS %d\n", __func__, sds_num);
+	return -EIO;
+}
+
 typedef struct {
 	u8 page;
 	u8 reg;
@@ -2913,6 +2977,23 @@ sds_config rtl9300_a_sds_10gr_lane1[] =
 	{0x2B, 0x14, 0x3108}, {0x2D, 0x13, 0x3C87}, {0x2D, 0x14, 0x1808},
 };
 
+static void rtl9300_serdes_patch(int sds_num)
+{
+	if (sds_num % 2) {
+		for (int i = 0; i < sizeof(rtl9300_a_sds_10gr_lane1) / sizeof(sds_config); ++i) {
+			rtl930x_write_sds_phy(sds_num, rtl9300_a_sds_10gr_lane1[i].page,
+					      rtl9300_a_sds_10gr_lane1[i].reg,
+					      rtl9300_a_sds_10gr_lane1[i].data);
+		}
+	} else {
+		for (int i = 0; i < sizeof(rtl9300_a_sds_10gr_lane0) / sizeof(sds_config); ++i) {
+			rtl930x_write_sds_phy(sds_num, rtl9300_a_sds_10gr_lane0[i].page,
+					      rtl9300_a_sds_10gr_lane0[i].reg,
+					      rtl9300_a_sds_10gr_lane0[i].data);
+		}
+	}
+}
+
 int rtl9300_sds_cmu_band_get(int sds)
 {
 	u32 page;
@@ -2938,113 +3019,6 @@ int rtl9300_sds_cmu_band_get(int sds)
 	return cmu_band;
 }
 
-int rtl9300_configure_serdes(struct phy_device *phydev)
-{
-	int phy_mode = PHY_INTERFACE_MODE_10GBASER;
-	struct device *dev = &phydev->mdio.dev;
-	int calib_tries = 0;
-	u32 sds_num = 0;
-	int sds_mode;
-
-	if (dev->of_node) {
-		struct device_node *dn = dev->of_node;
-		int phy_addr = phydev->mdio.addr;
-
-		if (of_property_read_u32(dn, "sds", &sds_num))
-			sds_num = -1;
-		pr_info("%s: Port %d, SerDes is %d\n", __func__, phy_addr, sds_num);
-	} else {
-		dev_err(dev, "No DT node.\n");
-		return -EINVAL;
-	}
-
-	if (sds_num < 0)
-		return 0;
-
-	if (phy_mode != PHY_INTERFACE_MODE_10GBASER) /* TODO: for now we only patch 10GR SerDes */
-		return 0;
-
-	switch (phy_mode) {
-	case PHY_INTERFACE_MODE_HSGMII:
-		sds_mode = 0x12;
-		break;
-	case PHY_INTERFACE_MODE_1000BASEX:
-		sds_mode = 0x04;
-		break;
-	case PHY_INTERFACE_MODE_XGMII:
-		sds_mode = 0x10;
-		break;
-	case PHY_INTERFACE_MODE_10GBASER:
-		sds_mode = 0x1a;
-		break;
-	case PHY_INTERFACE_MODE_USXGMII:
-		sds_mode = 0x0d;
-		break;
-	default:
-		pr_err("%s: unknown serdes mode: %s\n", __func__, phy_modes(phy_mode));
-		return -EINVAL;
-	}
-
-	pr_info("%s CMU BAND is %d\n", __func__, rtl9300_sds_cmu_band_get(sds_num));
-
-	/* Turn Off Serdes */
-	rtl9300_sds_rst(sds_num, 0x1f);
-
-	pr_info("%s PATCHING SerDes %d\n", __func__, sds_num);
-	if (sds_num % 2) {
-		for (int i = 0; i < sizeof(rtl9300_a_sds_10gr_lane1) / sizeof(sds_config); ++i) {
-			rtl930x_write_sds_phy(sds_num, rtl9300_a_sds_10gr_lane1[i].page,
-			                      rtl9300_a_sds_10gr_lane1[i].reg,
-			                      rtl9300_a_sds_10gr_lane1[i].data);
-		}
-	} else {
-		for (int i = 0; i < sizeof(rtl9300_a_sds_10gr_lane0) / sizeof(sds_config); ++i) {
-			rtl930x_write_sds_phy(sds_num, rtl9300_a_sds_10gr_lane0[i].page,
-			                      rtl9300_a_sds_10gr_lane0[i].reg,
-			                      rtl9300_a_sds_10gr_lane0[i].data);
-		}
-	}
-
-	rtl9300_phy_enable_10g_1g(sds_num);
-
-	/* Disable MAC */
-	sw_w32_mask(0, 1, RTL930X_MAC_FORCE_MODE_CTRL);
-	mdelay(20);
-
-	/* ----> dal_longan_sds_mode_set */
-	pr_info("%s: Configuring RTL9300 SERDES %d, mode %02x\n", __func__, sds_num, sds_mode);
-
-	/* Configure link to MAC */
-	rtl9300_serdes_mac_link_config(sds_num, true, true);	/* MAC Construct */
-
-	/* Disable MAC */
-	sw_w32_mask(0, 1, RTL930X_MAC_FORCE_MODE_CTRL);
-	mdelay(20);
-
-	rtl9300_force_sds_mode(sds_num, PHY_INTERFACE_MODE_NA);
-
-	/* Re-Enable MAC */
-	sw_w32_mask(1, 0, RTL930X_MAC_FORCE_MODE_CTRL);
-
-	rtl9300_force_sds_mode(sds_num, phy_mode);
-
-	/* Do RX calibration */
-	do {
-		rtl9300_do_rx_calibration(sds_num, phy_mode);
-		calib_tries++;
-		mdelay(50);
-	} while (rtl9300_sds_check_calibration(sds_num, phy_mode) && calib_tries < 3);
-
-	if (calib_tries >= 3)
-		pr_err("%s CALIBTRATION FAILED\n", __func__);
-
-	rtl9300_sds_tx_config(sds_num, phy_mode);
-
-	/* The clock needs only to be configured on the FPGA implementation */
-
-	return 0;
-}
-
 void rtl9310_sds_field_w(int sds, u32 page, u32 reg, int end_bit, int start_bit, u32 v)
 {
 	int l = end_bit - start_bit + 1;
@@ -3856,7 +3830,7 @@ static int rtl9300_serdes_probe(struct phy_device *phydev)
 
 	phydev_info(phydev, "Detected internal RTL9300 Serdes\n");
 
-	return rtl9300_configure_serdes(phydev);
+	return 0;
 }
 
 static struct phy_driver rtl83xx_phy_driver[] = {
diff --git a/target/linux/realtek/image/rtl838x.mk b/target/linux/realtek/image/rtl838x.mk
index 60249ff2fdb422..19a40f1f61ba38 100644
--- a/target/linux/realtek/image/rtl838x.mk
+++ b/target/linux/realtek/image/rtl838x.mk
@@ -168,6 +168,7 @@ define Device/netgear_nge
   SOC := rtl8380
   IMAGE_SIZE := 14848k
   UIMAGE_MAGIC := 0x4e474520
+  UIMAGE_NAME := 9.9.9.9
   DEVICE_VENDOR := NETGEAR
 endef
 
diff --git a/target/linux/realtek/image/rtl930x.mk b/target/linux/realtek/image/rtl930x.mk
index f55c5c002bf03d..7f0b6917598abd 100644
--- a/target/linux/realtek/image/rtl930x.mk
+++ b/target/linux/realtek/image/rtl930x.mk
@@ -6,12 +6,13 @@ define Device/zyxel_xgs1250-12
   ZYXEL_VERS := ABWE
   DEVICE_VENDOR := Zyxel
   DEVICE_MODEL := XGS1250-12
+  DEVICE_PACKAGES := kmod-hwmon-gpiofan kmod-thermal
   IMAGE_SIZE := 13312k
   KERNEL_INITRAMFS := \
 	kernel-bin | \
 	append-dtb | \
 	gzip | \
-	zyxel-vers $$$$(ZYXEL_VERS) | \
+	zyxel-vers | \
 	uImage gzip
 endef
 TARGET_DEVICES += zyxel_xgs1250-12
diff --git a/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds b/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds
index fbac4afc9c86ce..61a1c6c46cca5f 100644
--- a/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds
+++ b/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds
@@ -9,11 +9,13 @@ board_config_update
 
 case $board in
 friendlyarm,nanopi-r2c|\
+friendlyarm,nanopi-r2c-plus|\
 friendlyarm,nanopi-r2s)
 	ucidef_set_led_netdev "wan" "WAN" "$boardname:green:wan" "eth1"
 	ucidef_set_led_netdev "lan" "LAN" "$boardname:green:lan" "eth0"
 	;;
 friendlyarm,nanopi-r4s|\
+friendlyarm,nanopi-r4s-enterprise|\
 xunlong,orangepi-r1-plus|\
 xunlong,orangepi-r1-plus-lts)
 	ucidef_set_led_netdev "wan" "WAN" "green:wan" "eth0"
@@ -26,8 +28,8 @@ friendlyarm,nanopi-r5c)
 	;;
 friendlyarm,nanopi-r5s)
 	ucidef_set_led_netdev "wan" "WAN" "green:wan" "eth0"
-	ucidef_set_led_netdev "lan1" "LAN1" "green:lan1" "eth1"
-	ucidef_set_led_netdev "lan2" "LAN2" "green:lan2" "eth2"
+	ucidef_set_led_netdev "lan1" "LAN1" "green:lan-1" "eth1"
+	ucidef_set_led_netdev "lan2" "LAN2" "green:lan-2" "eth2"
 	;;
 esac
 
diff --git a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network
index 86649d48e46e8f..1ac9d225457eab 100644
--- a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network
+++ b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network
@@ -8,10 +8,12 @@ rockchip_setup_interfaces()
 
 	case "$board" in
 	friendlyarm,nanopi-r2c|\
+	friendlyarm,nanopi-r2c-plus|\
 	friendlyarm,nanopi-r2s)
 		ucidef_set_interfaces_lan_wan 'eth0' 'eth1'
 		;;
 	friendlyarm,nanopi-r4s|\
+	friendlyarm,nanopi-r4s-enterprise|\
 	xunlong,orangepi-r1-plus|\
 	xunlong,orangepi-r1-plus-lts)
 		ucidef_set_interfaces_lan_wan 'eth1' 'eth0'
@@ -28,27 +30,6 @@ rockchip_setup_interfaces()
 	esac
 }
 
-nanopi_r4s_get_mac()
-{
-	local interface=$1
-	local eeprom_path="/sys/bus/i2c/devices/2-0051/eeprom"
-	local address
-
-	if [ -f "$eeprom_path" ]; then
-		address=$(get_mac_binary "$eeprom_path" 0xfa)
-		if [ "$interface" = "lan" ]; then
-			address=$(macaddr_setbit_la "$address")
-		fi
-	else
-		address=$(macaddr_generate_from_mmc_cid mmcblk1)
-		if [ "$interface" = "lan" ]; then
-			address=$(macaddr_add "$address" 1)
-		fi
-	fi
-
-	echo "$address"
-}
-
 rockchip_setup_macs()
 {
 	local board="$1"
@@ -62,18 +43,20 @@ rockchip_setup_macs()
 		wan_mac=$(macaddr_generate_from_mmc_cid mmcblk0)
 		lan_mac=$(macaddr_add "$wan_mac" 1)
 		;;
-	friendlyarm,nanopi-r4s)
-		wan_mac=$(nanopi_r4s_get_mac wan)
-		lan_mac=$(nanopi_r4s_get_mac lan)
+	friendlyarm,nanopi-r2c-plus|\
+	friendlyarm,nanopi-r4s|\
+	friendlyarm,nanopi-r5s)
+		wan_mac=$(macaddr_generate_from_mmc_cid mmcblk1)
+		lan_mac=$(macaddr_add "$wan_mac" 1)
+		;;
+	friendlyarm,nanopi-r4s-enterprise)
+		wan_mac=$(get_mac_binary "/sys/bus/i2c/devices/2-0051/eeprom" 0xfa)
+		lan_mac=$(macaddr_setbit_la "$wan_mac")
 		;;
 	friendlyarm,nanopi-r5c)
 		wan_mac=$(macaddr_generate_from_mmc_cid mmcblk*)
 		lan_mac=$(macaddr_add "$wan_mac" 1)
 		;;
-	friendlyarm,nanopi-r5s)
-		wan_mac=$(macaddr_generate_from_mmc_cid mmcblk1)
-		lan_mac=$(macaddr_add "$wan_mac" 1)
-		;;
 	xunlong,orangepi-r1-plus|\
 	xunlong,orangepi-r1-plus-lts)
 		wan_mac=$(macaddr_add "$(cat /sys/class/net/eth1/address)" -1)
diff --git a/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity b/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity
index 09fc420fec80e2..360b34ba9120a9 100644
--- a/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity
+++ b/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity
@@ -30,13 +30,16 @@ set_interface_core() {
 
 case "$(board_name)" in
 friendlyarm,nanopi-r2c|\
+friendlyarm,nanopi-r2c-plus|\
 friendlyarm,nanopi-r2s|\
+radxa,cm3-io|\
 xunlong,orangepi-r1-plus|\
 xunlong,orangepi-r1-plus-lts)
 	set_interface_core 2 "eth0"
 	set_interface_core 4 "eth1" "xhci-hcd:usb[0-9]+"
 	;;
-friendlyarm,nanopi-r4s)
+friendlyarm,nanopi-r4s|\
+friendlyarm,nanopi-r4s-enterprise)
 	set_interface_core 10 "eth0"
 	set_interface_core 20 "eth1"
 	;;
diff --git a/target/linux/rockchip/image/armv8.mk b/target/linux/rockchip/image/armv8.mk
index 0bf91d15ca0c6d..251a9c17db2eb7 100644
--- a/target/linux/rockchip/image/armv8.mk
+++ b/target/linux/rockchip/image/armv8.mk
@@ -30,6 +30,14 @@ define Device/friendlyarm_nanopi-r2c
 endef
 TARGET_DEVICES += friendlyarm_nanopi-r2c
 
+define Device/friendlyarm_nanopi-r2c-plus
+  DEVICE_VENDOR := FriendlyARM
+  DEVICE_MODEL := NanoPi R2C Plus
+  SOC := rk3328
+  DEVICE_PACKAGES := kmod-usb-net-rtl8152
+endef
+TARGET_DEVICES += friendlyarm_nanopi-r2c-plus
+
 define Device/friendlyarm_nanopi-r2s
   DEVICE_VENDOR := FriendlyARM
   DEVICE_MODEL := NanoPi R2S
@@ -47,6 +55,16 @@ define Device/friendlyarm_nanopi-r4s
 endef
 TARGET_DEVICES += friendlyarm_nanopi-r4s
 
+define Device/friendlyarm_nanopi-r4s-enterprise
+  DEVICE_VENDOR := FriendlyARM
+  DEVICE_MODEL := NanoPi R4S Enterprise Edition
+  DEVICE_VARIANT := 4GB LPDDR4
+  SOC := rk3399
+  UBOOT_DEVICE_NAME := nanopi-r4s-rk3399
+  DEVICE_PACKAGES := kmod-r8169
+endef
+TARGET_DEVICES += friendlyarm_nanopi-r4s-enterprise
+
 define Device/friendlyarm_nanopi-r5c
   DEVICE_VENDOR := FriendlyARM
   DEVICE_MODEL := NanoPi R5C
@@ -77,6 +95,15 @@ define Device/pine64_rockpro64
 endef
 TARGET_DEVICES += pine64_rockpro64
 
+define Device/radxa_cm3-io
+  DEVICE_VENDOR := Radxa
+  DEVICE_MODEL := CM3 IO
+  SOC := rk3566
+  DEVICE_DTS := rockchip/rk3566-radxa-cm3-io
+  UBOOT_DEVICE_NAME := radxa-cm3-io-rk3566
+endef
+TARGET_DEVICES += radxa_cm3-io
+
 define Device/radxa_rock-pi-4a
   DEVICE_VENDOR := Radxa
   DEVICE_MODEL := ROCK Pi 4A
diff --git a/target/linux/rockchip/patches-6.1/005-arm64-dts-rockchip-add-EEPROM-node-for-NanoPi-R4S.patch b/target/linux/rockchip/patches-6.1/005-arm64-dts-rockchip-add-EEPROM-node-for-NanoPi-R4S.patch
deleted file mode 100644
index 792028b29290f5..00000000000000
--- a/target/linux/rockchip/patches-6.1/005-arm64-dts-rockchip-add-EEPROM-node-for-NanoPi-R4S.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From af20b3384e8723077cc6484160b0cf4e9be321de Mon Sep 17 00:00:00 2001
-From: Tianling Shen <cnsztl@gmail.com>
-Date: Mon, 7 Jun 2021 15:45:37 +0800
-Subject: [PATCH] arm64: dts: rockchip: add EEPROM node for NanoPi R4S
-
-NanoPi R4S has a EEPROM attached to the 2nd I2C bus (U92), which
-stores the MAC address.
-
-Signed-off-by: Tianling Shen <cnsztl@gmail.com>
----
- arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
-@@ -68,6 +68,15 @@
- 	status = "disabled";
- };
- 
-+&i2c2 {
-+	eeprom@51 {
-+		compatible = "microchip,24c02", "atmel,24c02";
-+		reg = <0x51>;
-+		pagesize = <16>;
-+		read-only; /* This holds our MAC */
-+	};
-+};
-+
- &i2c4 {
- 	status = "disabled";
- };
diff --git a/target/linux/rockchip/patches-6.1/016-v6.3-arm64-dts-rockchip-Add-Radxa-Compute-Module-3-IO-board.patch b/target/linux/rockchip/patches-6.1/016-v6.3-arm64-dts-rockchip-Add-Radxa-Compute-Module-3-IO-board.patch
new file mode 100644
index 00000000000000..b4a68d1558d7fc
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/016-v6.3-arm64-dts-rockchip-Add-Radxa-Compute-Module-3-IO-board.patch
@@ -0,0 +1,233 @@
+From 096ebfb74b19f2d4bdcbc33ae02e857ff4b3e0a0 Mon Sep 17 00:00:00 2001
+From: Jagan Teki <jagan@amarulasolutions.com>
+Date: Thu, 12 Jan 2023 16:29:02 +0530
+Subject: [PATCH] arm64: dts: rockchip: Add Radxa Compute Module 3 IO board
+
+Radxa Compute Module 3(CM3) IO board is an application board from Radxa
+and is compatible with Raspberry Pi CM4 IO form factor.
+
+Specification:
+- 1x HDMI,
+- 2x MIPI DSI
+- 2x MIPI CSI2
+- 1x eDP
+- 1x PCIe card
+- 2x SATA
+- 2x USB 2.0 Host
+- 1x USB 3.0
+- 1x USB 2.0 OTG
+- Phone jack
+- microSD slot
+- 40-pin GPIO expansion header
+- 12V DC
+
+Radxa CM3 needs to mount on top of this IO board in order to create
+complete Radxa CM3 IO board platform.
+
+Add support for Radxa CM3 IO Board.
+
+Co-developed-by: FUKAUMI Naoki <naoki@radxa.com>
+Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
+Co-developed-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
+Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
+Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
+Link: https://lore.kernel.org/r/20230112105902.192852-3-jagan@amarulasolutions.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/Makefile         |   1 +
+ .../boot/dts/rockchip/rk3566-radxa-cm3-io.dts | 179 ++++++++++++++++++
+ 2 files changed, 180 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -70,6 +70,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pi
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-radxa-cm3-io.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-roc-pc.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
+@@ -0,0 +1,179 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2022 Radxa Limited
++ * Copyright (c) 2022 Amarula Solutions(India)
++ */
++
++/dts-v1/;
++#include <dt-bindings/soc/rockchip,vop2.h>
++#include "rk3566.dtsi"
++#include "rk3566-radxa-cm3.dtsi"
++
++/ {
++	model = "Radxa Compute Module 3(CM3) IO Board";
++	compatible = "radxa,radxa-cm3-io", "radxa,radxa-cm3", "rockchip,rk3566";
++
++	aliases {
++		mmc1 = &sdmmc0;
++	};
++
++	chosen: chosen {
++		stdout-path = "serial2:1500000n8";
++	};
++
++	hdmi-con {
++		compatible = "hdmi-connector";
++		type = "a";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		led-1 {
++			gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_LOW>;
++			color = <LED_COLOR_ID_GREEN>;
++			function = LED_FUNCTION_ACTIVITY;
++			linux,default-trigger = "heartbeat";
++			pinctrl-names = "default";
++			pinctrl-0 = <&pi_nled_activity>;
++		};
++	};
++
++	vcc5v0_usb30: vcc5v0-usb30-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc5v0_usb30";
++		enable-active-high;
++		gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&vcc5v0_usb30_en_h>;
++		regulator-always-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&vcc_sys>;
++	};
++
++	vcca1v8_image: vcca1v8-image-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcca1v8_image";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		vin-supply = <&vcc_1v8_p>;
++	};
++
++	vdda0v9_image: vdda0v9-image-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcca0v9_image";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <900000>;
++		regulator-max-microvolt = <900000>;
++		vin-supply = <&vdda_0v9>;
++	};
++};
++
++&combphy1 {
++	status = "okay";
++};
++
++&hdmi {
++	avdd-0v9-supply = <&vdda0v9_image>;
++	avdd-1v8-supply = <&vcca1v8_image>;
++	status = "okay";
++};
++
++&hdmi_in {
++	hdmi_in_vp0: endpoint {
++		remote-endpoint = <&vp0_out_hdmi>;
++	};
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
++&hdmi_sound {
++	status = "okay";
++};
++
++&pinctrl {
++	leds {
++		pi_nled_activity: pi-nled-activity {
++			rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	sdcard {
++		sdmmc_pwren: sdmmc-pwren {
++			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	usb {
++		vcc5v0_usb30_en_h: vcc5v0-host-en-h {
++			rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++};
++
++&sdmmc0 {
++	bus-width = <4>;
++	cap-mmc-highspeed;
++	cap-sd-highspeed;
++	disable-wp;
++	vqmmc-supply = <&vccio_sd>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_pwren>;
++	status = "okay";
++};
++
++&uart2 {
++	status = "okay";
++};
++
++&usb2phy0_host {
++	phy-supply = <&vcc5v0_usb30>;
++	status = "okay";
++};
++
++&usb2phy1_host {
++	status = "okay";
++};
++
++&usb2phy1_otg {
++	status = "okay";
++};
++
++&usb_host0_ehci {
++	status = "okay";
++};
++
++&usb_host1_xhci {
++	status = "okay";
++};
++
++&vop {
++	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
++	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
++	status = "okay";
++};
++
++&vop_mmu {
++	status = "okay";
++};
++
++&vp0 {
++	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
++		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
++		remote-endpoint = <&hdmi_in_vp0>;
++	};
++};
diff --git a/target/linux/rockchip/patches-6.1/016-v6.5-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R2C-Plus.patch b/target/linux/rockchip/patches-6.1/016-v6.5-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R2C-Plus.patch
new file mode 100644
index 00000000000000..d0a0aa1b695621
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/016-v6.5-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R2C-Plus.patch
@@ -0,0 +1,63 @@
+From d211665c5a833873ee37e501af58adbf028e6b5f Mon Sep 17 00:00:00 2001
+From: Tianling Shen <cnsztl@gmail.com>
+Date: Sat, 13 May 2023 21:53:07 +0800
+Subject: [PATCH] arm64: dts: rockchip: Add FriendlyARM NanoPi R2C Plus
+
+The NanoPi R2C Plus is a small variant of NanoPi R2C with a on-board
+eMMC flash (8G) included.
+
+Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+Link: https://lore.kernel.org/r/20230513135307.26554-2-cnsztl@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/Makefile              |  1 +
+ .../boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts   | 33 ++++++++++++++++++++++
+ 2 files changed, 34 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -11,6 +11,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-od
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c-plus.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts
+@@ -0,0 +1,33 @@
++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
++/*
++ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
++ * (http://www.friendlyarm.com)
++ *
++ * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
++ */
++
++/dts-v1/;
++#include "rk3328-nanopi-r2c.dts"
++
++/ {
++	model = "FriendlyElec NanoPi R2C Plus";
++	compatible = "friendlyarm,nanopi-r2c-plus", "rockchip,rk3328";
++
++	aliases {
++		mmc1 = &emmc;
++	};
++};
++
++&emmc {
++	bus-width = <8>;
++	cap-mmc-highspeed;
++	max-frequency = <150000000>;
++	mmc-ddr-1_8v;
++	mmc-hs200-1_8v;
++	non-removable;
++	pinctrl-names = "default";
++	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
++	vmmc-supply = <&vcc_io_33>;
++	vqmmc-supply = <&vcc18_emmc>;
++	status = "okay";
++};
diff --git a/target/linux/rockchip/patches-6.1/017-v6.3-arm64-dts-rockchip-Enable-Ethernet-for-Radxa-CM3-IO.patch b/target/linux/rockchip/patches-6.1/017-v6.3-arm64-dts-rockchip-Enable-Ethernet-for-Radxa-CM3-IO.patch
new file mode 100644
index 00000000000000..305b5702d5e1c9
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/017-v6.3-arm64-dts-rockchip-Enable-Ethernet-for-Radxa-CM3-IO.patch
@@ -0,0 +1,131 @@
+From cc52bfc04726a574fc4440bbbe0c710890e7040a Mon Sep 17 00:00:00 2001
+From: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
+Date: Wed, 25 Jan 2023 21:40:22 +0530
+Subject: [PATCH] arm64: dts: rockchip: Enable Ethernet for Radxa CM3 IO
+
+Add ethernet nodes for enabling gmac1 on the Radxa CM3 IO board.
+
+Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
+Link: https://lore.kernel.org/r/20230125161023.12115-1-jagan@amarulasolutions.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ .../boot/dts/rockchip/rk3566-radxa-cm3-io.dts | 93 +++++++++++++++++++
+ 1 file changed, 93 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
+@@ -21,6 +21,13 @@
+ 		stdout-path = "serial2:1500000n8";
+ 	};
+ 
++	gmac1_clkin: external-gmac1-clock {
++		compatible = "fixed-clock";
++		clock-frequency = <125000000>;
++		clock-output-names = "gmac1_clkin";
++		#clock-cells = <0>;
++	};
++
+ 	hdmi-con {
+ 		compatible = "hdmi-connector";
+ 		type = "a";
+@@ -83,6 +90,29 @@
+ 	status = "okay";
+ };
+ 
++&gmac1 {
++	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
++	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
++	assigned-clock-rates = <0>, <125000000>;
++	clock_in_out = "input";
++	phy-handle = <&rgmii_phy1>;
++	phy-mode = "rgmii";
++	pinctrl-names = "default";
++	pinctrl-0 = <&gmac1m0_miim
++		     &gmac1m0_tx_bus2
++		     &gmac1m0_rx_bus2
++		     &gmac1m0_rgmii_clk
++		     &gmac1m0_rgmii_bus
++		     &gmac1m0_clkinout>;
++	snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
++	snps,reset-active-low;
++	/* Reset time is 20ms, 100ms for rtl8211f */
++	snps,reset-delays-us = <0 20000 100000>;
++	tx_delay = <0x46>;
++	rx_delay = <0x2e>;
++	status = "okay";
++};
++
+ &hdmi {
+ 	avdd-0v9-supply = <&vdda0v9_image>;
+ 	avdd-1v8-supply = <&vcca1v8_image>;
+@@ -105,7 +135,70 @@
+ 	status = "okay";
+ };
+ 
++&mdio1 {
++	rgmii_phy1: ethernet-phy@0 {
++		compatible="ethernet-phy-ieee802.3-c22";
++		reg= <0x0>;
++	};
++};
++
+ &pinctrl {
++	gmac1 {
++		gmac1m0_miim: gmac1m0-miim {
++			rockchip,pins =
++				/* gmac1_mdcm0 */
++				<3 RK_PC4 3 &pcfg_pull_none_drv_level_15>,
++				/* gmac1_mdiom0 */
++				<3 RK_PC5 3 &pcfg_pull_none_drv_level_15>;
++		};
++
++		gmac1m0_rx_bus2: gmac1m0-rx-bus2 {
++			rockchip,pins =
++				/* gmac1_rxd0m0 */
++				<3 RK_PB1 3 &pcfg_pull_none_drv_level_15>,
++				/* gmac1_rxd1m0 */
++				<3 RK_PB2 3 &pcfg_pull_none_drv_level_15>,
++				/* gmac1_rxdvcrsm0 */
++				<3 RK_PB3 3 &pcfg_pull_none_drv_level_15>;
++		};
++
++		gmac1m0_tx_bus2: gmac1m0-tx-bus2 {
++			rockchip,pins =
++				/* gmac1_txd0m0 */
++				<3 RK_PB5 3 &pcfg_pull_none_drv_level_15>,
++				/* gmac1_txd1m0 */
++				<3 RK_PB6 3 &pcfg_pull_none_drv_level_15>,
++				/* gmac1_txenm0 */
++				<3 RK_PB7 3 &pcfg_pull_none_drv_level_15>;
++		};
++
++		gmac1m0_rgmii_clk: gmac1m0-rgmii-clk {
++			rockchip,pins =
++				/* gmac1_rxclkm0 */
++				<3 RK_PA7 3 &pcfg_pull_none_drv_level_15>,
++				/* gmac1_txclkm0 */
++				<3 RK_PA6 3 &pcfg_pull_none_drv_level_15>;
++		};
++
++		gmac1m0_rgmii_bus: gmac1m0-rgmii-bus {
++			rockchip,pins =
++				/* gmac1_rxd2m0 */
++				<3 RK_PA4 3 &pcfg_pull_none_drv_level_15>,
++				/* gmac1_rxd3m0 */
++				<3 RK_PA5 3 &pcfg_pull_none_drv_level_15>,
++				/* gmac1_txd2m0 */
++				<3 RK_PA2 3 &pcfg_pull_none_drv_level_15>,
++				/* gmac1_txd3m0 */
++				<3 RK_PA3 3 &pcfg_pull_none_drv_level_15>;
++		};
++
++		gmac1m0_clkinout: gmac1m0-clkinout {
++			rockchip,pins =
++				/* gmac1_mclkinoutm0 */
++				<3 RK_PC0 3 &pcfg_pull_none_drv_level_15>;
++		};
++	};
++
+ 	leds {
+ 		pi_nled_activity: pi-nled-activity {
+ 			rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
diff --git a/target/linux/rockchip/patches-6.1/018-v6.3-arm64-dts-rockchip-Add-rk3566-based-Radxa-Compute-Module-3.patch b/target/linux/rockchip/patches-6.1/018-v6.3-arm64-dts-rockchip-Add-rk3566-based-Radxa-Compute-Module-3.patch
new file mode 100644
index 00000000000000..e53f7fa7e090f0
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/018-v6.3-arm64-dts-rockchip-Add-rk3566-based-Radxa-Compute-Module-3.patch
@@ -0,0 +1,386 @@
+From 7469ab529bcad50490f6ff651c3e4f03bfa88fe0 Mon Sep 17 00:00:00 2001
+From: Jagan Teki <jagan@amarulasolutions.com>
+Date: Thu, 12 Jan 2023 16:29:01 +0530
+Subject: [PATCH] arm64: dts: rockchip: Add rk3566 based Radxa Compute Module 3
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Radxa Compute Module 3(CM3) is one of the modules from a series
+System On Module based on the Radxa ROCK 3 series and is compatible
+with Raspberry Pi CM4 pinout and form factor.
+
+Specification:
+- Rockchip RK3566
+- up to 8GB LPDDR4
+- up to 128GB high performance eMMC
+- Optional wireless LAN, 2.4GHz and 5.0GHz IEEE 802.11b/g/n/ac wireless,
+  BT 5.0, BLE with onboard and external antenna.
+- Gigabit Ethernet PHY
+
+Radxa CM3 needs to mount on top of this IO board in order to create
+complete Radxa CM3 IO board platform.
+
+Since Radxa CM3 is compatible with Raspberry Pi CM4 pinout so it is
+possible to mount Radxa CM3 on top of the Rasberry Pi CM4 IO board.
+
+Add support for Radxa CM3.
+
+Co-developed-by: FUKAUMI Naoki <naoki@radxa.com>
+Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
+Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
+Link: https://lore.kernel.org/r/20230112105902.192852-2-jagan@amarulasolutions.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ .../boot/dts/rockchip/rk3566-radxa-cm3.dtsi   | 345 ++++++++++++++++++
+ 1 file changed, 345 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi
+
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi
+@@ -0,0 +1,345 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2022 Radxa Limited
++ * Copyright (c) 2022 Amarula Solutions(India)
++ */
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/leds/common.h>
++
++/ {
++	compatible = "radxa,radxa-cm3", "rockchip,rk3566";
++
++	aliases {
++		mmc0 = &sdhci;
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		led-0 {
++			gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
++			color = <LED_COLOR_ID_GREEN>;
++			function = LED_FUNCTION_STATUS;
++			linux,default-trigger = "timer";
++			default-state = "on";
++			pinctrl-names = "default";
++			pinctrl-0 = <&user_led2>;
++		};
++	};
++
++	vcc_sys: vcc-sys-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc_sys";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++	};
++
++	vcc_1v8: vcc-1v8-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc_1v8";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		vin-supply = <&vcc_1v8_p>;
++	};
++
++	vcc_3v3: vcc-3v3-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc_3v3";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		vin-supply = <&vcc3v3_sys>;
++	};
++
++	vcca_1v8: vcca-1v8-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcca_1v8";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		vin-supply = <&vcc_1v8_p>;
++	};
++};
++
++&cpu0 {
++	cpu-supply = <&vdd_cpu>;
++};
++
++&cpu1 {
++	cpu-supply = <&vdd_cpu>;
++};
++
++&cpu2 {
++	cpu-supply = <&vdd_cpu>;
++};
++
++&cpu3 {
++	cpu-supply = <&vdd_cpu>;
++};
++
++&gpu {
++	mali-supply = <&vdd_gpu_npu>;
++	status = "okay";
++};
++
++&i2c0 {
++	status = "okay";
++
++	vdd_cpu: regulator@1c {
++		compatible = "tcs,tcs4525";
++		reg = <0x1c>;
++		fcs,suspend-voltage-selector = <1>;
++		regulator-name = "vdd_cpu";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <712500>;
++		regulator-max-microvolt = <1390000>;
++		regulator-ramp-delay = <2300>;
++		vin-supply = <&vcc_sys>;
++
++		regulator-state-mem {
++			regulator-off-in-suspend;
++		};
++	};
++
++	rk817: pmic@20 {
++		compatible = "rockchip,rk817";
++		reg = <0x20>;
++		#clock-cells = <1>;
++		clock-output-names = "rk817-clkout1", "rk817-clkout2";
++		interrupt-parent = <&gpio0>;
++		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&pmic_int_l>;
++		rockchip,system-power-controller;
++		wakeup-source;
++
++		vcc1-supply = <&vcc_sys>;
++		vcc2-supply = <&vcc_sys>;
++		vcc3-supply = <&vcc_sys>;
++		vcc4-supply = <&vcc_sys>;
++		vcc5-supply = <&vcc_sys>;
++		vcc6-supply = <&vcc_sys>;
++		vcc7-supply = <&vcc_sys>;
++
++		regulators {
++			vdd_logic: DCDC_REG1 {
++				regulator-name = "vdd_logic";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-initial-mode = <0x2>;
++				regulator-min-microvolt = <500000>;
++				regulator-max-microvolt = <1350000>;
++				regulator-ramp-delay = <6001>;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <900000>;
++				};
++			};
++
++			vdd_gpu_npu: DCDC_REG2 {
++				regulator-name = "vdd_gpu_npu";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-initial-mode = <0x2>;
++				regulator-min-microvolt = <500000>;
++				regulator-max-microvolt = <1350000>;
++				regulator-ramp-delay = <6001>;
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_ddr: DCDC_REG3 {
++				regulator-name = "vcc_ddr";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-initial-mode = <0x2>;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++				};
++			};
++
++			vcc3v3_sys: DCDC_REG4 {
++				regulator-name = "vcc3v3_sys";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-initial-mode = <0x2>;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <3300000>;
++				};
++			};
++
++			vcca1v8_pmu: LDO_REG1 {
++				regulator-name = "vcca1v8_pmu";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++
++			vdda_0v9: LDO_REG2 {
++				regulator-name = "vdda_0v9";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <900000>;
++				regulator-max-microvolt = <900000>;
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdda0v9_pmu: LDO_REG3 {
++				regulator-name = "vdda0v9_pmu";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <900000>;
++				regulator-max-microvolt = <900000>;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <900000>;
++				};
++			};
++
++			vccio_acodec: LDO_REG4 {
++				regulator-name = "vccio_acodec";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vccio_sd: LDO_REG5 {
++				regulator-name = "vccio_sd";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc3v3_pmu: LDO_REG6 {
++				regulator-name = "vcc3v3_pmu";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <3300000>;
++				};
++			};
++
++			vcc_1v8_p: LDO_REG7 {
++				regulator-name = "vcc_1v8_p";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc1v8_dvp: LDO_REG8 {
++				regulator-name = "vcc1v8_dvp";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc2v8_dvp: LDO_REG9 {
++				regulator-name = "vcc2v8_dvp";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <2800000>;
++				regulator-max-microvolt = <2800000>;
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++		};
++	};
++};
++
++&pinctrl {
++	pmic {
++		pmic_int_l: pmic-int-l {
++			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++
++	leds {
++		user_led2: user-led2 {
++			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++};
++
++&pmu_io_domains {
++	pmuio1-supply = <&vcc3v3_pmu>;
++	pmuio2-supply = <&vcc_3v3>;
++	vccio1-supply = <&vccio_acodec>;
++	vccio2-supply = <&vcc_1v8>;
++	vccio3-supply = <&vccio_sd>;
++	vccio4-supply = <&vcc_1v8>;
++	vccio5-supply = <&vcc_3v3>;
++	vccio6-supply = <&vcc_3v3>;
++	vccio7-supply = <&vcc_3v3>;
++	status = "okay";
++};
++
++&saradc {
++	vref-supply = <&vcca_1v8>;
++	status = "okay";
++};
++
++&sdhci {
++	bus-width = <8>;
++	max-frequency = <200000000>;
++	mmc-hs200-1_8v;
++	non-removable;
++	pinctrl-names = "default";
++	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
++	vmmc-supply = <&vcc_3v3>;
++	vqmmc-supply = <&vcc_1v8>;
++	status = "okay";
++};
++
++&usb2phy0 {
++	status = "okay";
++};
++
++&usb2phy1 {
++	status = "okay";
++};
++
++&tsadc {
++	rockchip,hw-tshut-mode = <1>;
++	rockchip,hw-tshut-polarity = <0>;
++	status = "okay";
++};
diff --git a/target/linux/rockchip/patches-6.1/019-v6.3-arm64-dts-rockchip-Enable-WiFi-BT-support-for-Radxa-CM3.patch b/target/linux/rockchip/patches-6.1/019-v6.3-arm64-dts-rockchip-Enable-WiFi-BT-support-for-Radxa-CM3.patch
new file mode 100644
index 00000000000000..9855b9e1a60040
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/019-v6.3-arm64-dts-rockchip-Enable-WiFi-BT-support-for-Radxa-CM3.patch
@@ -0,0 +1,134 @@
+From af5a803bf212e077e5fb7a1d4cf6be02f74a74ca Mon Sep 17 00:00:00 2001
+From: Jagan Teki <jagan@amarulasolutions.com>
+Date: Wed, 25 Jan 2023 21:40:23 +0530
+Subject: [PATCH] arm64: dts: rockchip: rk3566: Enable WiFi, BT support for
+ Radxa CM3
+
+Radxa Compute Module 3 has an onboard AW_CM256SM WiFi/BT module.
+
+Add nodes for enabling it.
+
+Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
+Link: https://lore.kernel.org/r/20230125161023.12115-2-jagan@amarulasolutions.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ .../boot/dts/rockchip/rk3566-radxa-cm3.dtsi   | 80 +++++++++++++++++++
+ 1 file changed, 80 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi
+@@ -66,6 +66,15 @@
+ 		regulator-max-microvolt = <1800000>;
+ 		vin-supply = <&vcc_1v8_p>;
+ 	};
++
++	sdio_pwrseq: pwrseq-sdio {
++		compatible = "mmc-pwrseq-simple";
++		clocks = <&rk817 1>;
++		clock-names = "ext_clock";
++		pinctrl-names = "default";
++		pinctrl-0 = <&wifi_reg_on_h>;
++		reset-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_LOW>;
++	};
+ };
+ 
+ &cpu0 {
+@@ -287,6 +296,20 @@
+ };
+ 
+ &pinctrl {
++	bluetooth {
++		bt_host_wake_h: bt-host-wake-h {
++			rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		bt_reg_on_h: bt-reg-on-h {
++			rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		bt_wake_host_h: bt-wake-host-h {
++			rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
+ 	pmic {
+ 		pmic_int_l: pmic-int-l {
+ 			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+@@ -298,6 +321,16 @@
+ 			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+ 		};
+ 	};
++
++	wifi {
++		wifi_reg_on_h: wifi-reg-on-h {
++			rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		wifi_host_wake_h: wifi-host-wake-h {
++			rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
+ };
+ 
+ &pmu_io_domains {
+@@ -318,6 +351,34 @@
+ 	status = "okay";
+ };
+ 
++&sdmmc1 {
++	#address-cells = <1>;
++	#size-cells = <0>;
++	bus-width = <4>;
++	disable-wp;
++	cap-sd-highspeed;
++	cap-sdio-irq;
++	keep-power-in-suspend;
++	mmc-pwrseq = <&sdio_pwrseq>;
++	non-removable;
++	pinctrl-names = "default";
++	pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd>;
++	sd-uhs-sdr104;
++	vmmc-supply = <&vcc_3v3>;
++	vqmmc-supply = <&vcc_1v8>;
++	status = "okay";
++
++	wifi@1 {
++		compatible = "brcm,bcm43455-fmac";
++		reg = <1>;
++		interrupt-parent = <&gpio2>;
++		interrupts = <RK_PC1 IRQ_TYPE_LEVEL_HIGH>;
++		interrupt-names = "host-wake";
++		pinctrl-names = "default";
++		pinctrl-0 = <&wifi_host_wake_h>;
++	};
++};
++
+ &sdhci {
+ 	bus-width = <8>;
+ 	max-frequency = <200000000>;
+@@ -330,6 +391,25 @@
+ 	status = "okay";
+ };
+ 
++&uart1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart1m0_ctsn &uart1m0_rtsn &uart1m0_xfer>;
++	status = "okay";
++
++	bluetooth {
++		compatible = "brcm,bcm4345c5";
++		clocks = <&rk817 1>;
++		clock-names = "lpo";
++		device-wakeup-gpios = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>;
++		host-wakeup-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>;
++		reset-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_LOW>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&bt_host_wake_h &bt_reg_on_h &bt_wake_host_h>;
++		vbat-supply = <&vcc_3v3>;
++		vddio-supply = <&vcc_1v8>;
++	};
++};
++
+ &usb2phy0 {
+ 	status = "okay";
+ };
diff --git a/target/linux/rockchip/patches-6.1/020-v6.4-arm64-dts-rockchip-Enable-USB-OTG-for-rk3566-Radxa-CM3.patch b/target/linux/rockchip/patches-6.1/020-v6.4-arm64-dts-rockchip-Enable-USB-OTG-for-rk3566-Radxa-CM3.patch
new file mode 100644
index 00000000000000..bfd6dbe0db8b36
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/020-v6.4-arm64-dts-rockchip-Enable-USB-OTG-for-rk3566-Radxa-CM3.patch
@@ -0,0 +1,32 @@
+From 477ed3ade6a46e445b4e2348b710c51df4f6f4b1 Mon Sep 17 00:00:00 2001
+From: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
+Date: Thu, 23 Feb 2023 19:29:29 +0530
+Subject: [PATCH] arm64: dts: rockchip: Enable USB OTG for rk3566 Radxa CM3
+
+Enable USB OTG support for Radxa Compute Module 3 IO Board
+
+Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
+Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
+Link: https://lore.kernel.org/r/20230223135929.630787-1-abbaraju.manojsai@amarulasolutions.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
+@@ -254,6 +254,14 @@
+ 	status = "okay";
+ };
+ 
++&usb2phy0_otg {
++	status = "okay";
++};
++
++&usb_host0_xhci {
++	status = "okay";
++};
++
+ &vop {
+ 	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+ 	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
diff --git a/target/linux/rockchip/patches-6.1/021-v6.3-arm64-dts-rockchip-Fix-compatible-for-Radxa-CM3.patch b/target/linux/rockchip/patches-6.1/021-v6.3-arm64-dts-rockchip-Fix-compatible-for-Radxa-CM3.patch
new file mode 100644
index 00000000000000..e7e3ea0100f3e2
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/021-v6.3-arm64-dts-rockchip-Fix-compatible-for-Radxa-CM3.patch
@@ -0,0 +1,45 @@
+From 8f19828844f20b22182719cf53be64f8c955aee8 Mon Sep 17 00:00:00 2001
+From: Jagan Teki <jagan@amarulasolutions.com>
+Date: Mon, 23 Jan 2023 12:46:50 +0530
+Subject: [PATCH] arm64: dts: rockchip: Fix compatible for Radxa CM3
+
+The compatible string "radxa,radxa-cm3" referring the product name
+as "Radxa Radxa CM3" but the actual product name is "Radxa CM3".
+
+Fix the compatible strings.
+
+Fixes: 24a28d3eb07d ("dt-bindings: arm: rockchip: Add Radxa Compute Module 3")
+Fixes: 7469ab529bca ("arm64: dts: rockchip: Add rk3566 based Radxa Compute Module 3")
+Fixes: 096ebfb74b19 ("arm64: dts: rockchip: Add Radxa Compute Module 3 IO board")
+Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Link: https://lore.kernel.org/r/20230123071654.73139-1-jagan@amarulasolutions.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts | 2 +-
+ arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi   | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
+@@ -11,7 +11,7 @@
+ 
+ / {
+ 	model = "Radxa Compute Module 3(CM3) IO Board";
+-	compatible = "radxa,radxa-cm3-io", "radxa,radxa-cm3", "rockchip,rk3566";
++	compatible = "radxa,cm3-io", "radxa,cm3", "rockchip,rk3566";
+ 
+ 	aliases {
+ 		mmc1 = &sdmmc0;
+--- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi
+@@ -8,7 +8,7 @@
+ #include <dt-bindings/leds/common.h>
+ 
+ / {
+-	compatible = "radxa,radxa-cm3", "rockchip,rk3566";
++	compatible = "radxa,cm3", "rockchip,rk3566";
+ 
+ 	aliases {
+ 		mmc0 = &sdhci;
diff --git a/target/linux/rockchip/patches-6.1/022-v6.5-arm64-dts-rockchip-minor-whitespace-cleanup-around.patch b/target/linux/rockchip/patches-6.1/022-v6.5-arm64-dts-rockchip-minor-whitespace-cleanup-around.patch
new file mode 100644
index 00000000000000..8342c14ea435e9
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/022-v6.5-arm64-dts-rockchip-minor-whitespace-cleanup-around.patch
@@ -0,0 +1,28 @@
+From f99a75f11f46a24dabb33e90893eebf61dca0566 Mon Sep 17 00:00:00 2001
+From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Date: Sun, 2 Jul 2023 20:52:42 +0200
+Subject: [PATCH] arm64: dts: rockchip: minor whitespace cleanup around '='
+
+The DTS code coding style expects exactly one space before and after '='
+sign.
+
+Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Link: https://lore.kernel.org/r/20230702185242.44421-1-krzysztof.kozlowski@linaro.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ .../boot/dts/rockchip/rk3566-radxa-cm3-io.dts    |  4 ++--
+ 1 files changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
+@@ -137,8 +137,8 @@
+ 
+ &mdio1 {
+ 	rgmii_phy1: ethernet-phy@0 {
+-		compatible="ethernet-phy-ieee802.3-c22";
+-		reg= <0x0>;
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <0x0>;
+ 	};
+ };
+ 
diff --git a/target/linux/rockchip/patches-6.1/023-v6.8-arm64-dts-rockchip-Add-ethernet0-alias-to-the-dts-for-RK3566-boards.patch b/target/linux/rockchip/patches-6.1/023-v6.8-arm64-dts-rockchip-Add-ethernet0-alias-to-the-dts-for-RK3566-boards.patch
new file mode 100644
index 00000000000000..fb5015cf6e0fe4
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/023-v6.8-arm64-dts-rockchip-Add-ethernet0-alias-to-the-dts-for-RK3566-boards.patch
@@ -0,0 +1,28 @@
+From 36d9b3ae708e865cdab95692db5a24c5d975383d Mon Sep 17 00:00:00 2001
+From: Dragan Simic <dsimic@manjaro.org>
+Date: Tue, 12 Dec 2023 09:01:39 +0100
+Subject: [PATCH] arm64: dts: rockchip: Add ethernet0 alias to the dts for
+ RK3566 boards
+
+Add ethernet0 alias to the board dts files for a few supported RK3566 boards
+that had it missing.  Also, remove the ethernet0 alias from one RK3566 SoM
+dtsi file, which doesn't enable the GMAC, and add the ethernet0 alias back to
+the dependent board dts files, which actually enable the GMAC.
+
+Signed-off-by: Dragan Simic <dsimic@manjaro.org>
+Link: https://lore.kernel.org/r/d2a272e0ae0fff0adfab8bb0238243b11d348799.1702368023.git.dsimic@manjaro.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts     | 1 +
+ 1 files changed, 1 insertions(+), 0 deletion(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
+@@ -14,6 +14,7 @@
+ 	compatible = "radxa,cm3-io", "radxa,cm3", "rockchip,rk3566";
+ 
+ 	aliases {
++		ethernet0 = &gmac1;
+ 		mmc1 = &sdmmc0;
+ 	};
+ 
diff --git a/target/linux/rockchip/patches-6.1/100-rockchip-use-system-LED-for-OpenWrt.patch b/target/linux/rockchip/patches-6.1/100-rockchip-use-system-LED-for-OpenWrt.patch
index 01009c5eb8411b..683e5347f75b01 100644
--- a/target/linux/rockchip/patches-6.1/100-rockchip-use-system-LED-for-OpenWrt.patch
+++ b/target/linux/rockchip/patches-6.1/100-rockchip-use-system-LED-for-OpenWrt.patch
@@ -15,7 +15,15 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
 
 --- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
 +++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
-@@ -16,6 +16,11 @@
+@@ -6,6 +6,7 @@
+ /dts-v1/;
+ 
+ #include <dt-bindings/input/input.h>
++#include <dt-bindings/leds/common.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include "rk3328.dtsi"
+ 
+@@ -16,6 +17,11 @@
  	aliases {
  		ethernet1 = &rtl8153;
  		mmc0 = &sdmmc;
@@ -27,25 +35,29 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
  	};
  
  	chosen {
-@@ -49,18 +54,18 @@
+@@ -48,19 +54,22 @@
+ 		pinctrl-names = "default";
  
  		lan_led: led-0 {
++			color = <LED_COLOR_ID_GREEN>;
++			function = LED_FUNCTION_LAN;
  			gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
 -			label = "nanopi-r2s:green:lan";
-+			label = "green:lan";
  		};
  
  		sys_led: led-1 {
++			color = <LED_COLOR_ID_RED>;
++			function = LED_FUNCTION_STATUS;
  			gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
 -			label = "nanopi-r2s:red:sys";
-+			label = "red:sys";
  			default-state = "on";
  		};
  
  		wan_led: led-2 {
++			color = <LED_COLOR_ID_GREEN>;
++			function = LED_FUNCTION_WAN;
  			gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
 -			label = "nanopi-r2s:green:wan";
-+			label = "green:wan";
  		};
  	};
  
diff --git a/target/linux/rockchip/patches-6.1/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch b/target/linux/rockchip/patches-6.1/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch
index 2221077c97ced8..eeef0df014f2d0 100644
--- a/target/linux/rockchip/patches-6.1/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch
+++ b/target/linux/rockchip/patches-6.1/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch
@@ -14,7 +14,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
 
 --- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
 +++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
-@@ -402,6 +402,7 @@
+@@ -406,6 +406,7 @@
  	rtl8153: device@2 {
  		compatible = "usbbda,8153";
  		reg = <2>;
diff --git a/target/linux/rockchip/patches-6.1/105-nanopi-r4s-sd-signalling.patch b/target/linux/rockchip/patches-6.1/105-nanopi-r4s-sd-signalling.patch
index 856970738aaacd..b3c941821aaaf8 100644
--- a/target/linux/rockchip/patches-6.1/105-nanopi-r4s-sd-signalling.patch
+++ b/target/linux/rockchip/patches-6.1/105-nanopi-r4s-sd-signalling.patch
@@ -22,7 +22,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
  	status = "okay";
 --- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
 +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
-@@ -121,6 +121,11 @@
+@@ -112,6 +112,11 @@
  	status = "disabled";
  };
  
diff --git a/target/linux/rockchip/patches-6.1/107-arm64-dts-rockchip-Update-LED-properties-for-Orange-.patch b/target/linux/rockchip/patches-6.1/107-arm64-dts-rockchip-Update-LED-properties-for-Orange-.patch
index b1e26d4e3e27d7..3aff37d0969b01 100644
--- a/target/linux/rockchip/patches-6.1/107-arm64-dts-rockchip-Update-LED-properties-for-Orange-.patch
+++ b/target/linux/rockchip/patches-6.1/107-arm64-dts-rockchip-Update-LED-properties-for-Orange-.patch
@@ -5,8 +5,6 @@ Subject: [PATCH] arm64: dts: rockchip: Update LED properties for Orange Pi R1
  Plus
 
 Add OpenWrt's LED aliases for showing system status.
-Also replace function/color with legacy label as OpenWrt relys on it
-to update LED settings.
 
 Signed-off-by: Tianling Shen <cnsztl@gmail.com>
 ---
@@ -27,30 +25,16 @@ Signed-off-by: Tianling Shen <cnsztl@gmail.com>
  	};
  
  	chosen {
-@@ -36,22 +41,18 @@
- 		pinctrl-names = "default";
- 
- 		led-0 {
--			function = LED_FUNCTION_LAN;
--			color = <LED_COLOR_ID_GREEN>;
+@@ -41,11 +46,10 @@
  			gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
-+			label = "green:lan";
  		};
  
 -		led-1 {
--			function = LED_FUNCTION_STATUS;
--			color = <LED_COLOR_ID_RED>;
 +		status_led: led-1 {
+ 			function = LED_FUNCTION_STATUS;
+ 			color = <LED_COLOR_ID_RED>;
  			gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
 -			linux,default-trigger = "heartbeat";
-+			label = "red:status";
  		};
  
  		led-2 {
--			function = LED_FUNCTION_WAN;
--			color = <LED_COLOR_ID_GREEN>;
- 			gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
-+			label = "green:wan";
- 		};
- 	};
- 
diff --git a/target/linux/rockchip/patches-6.1/108-arm64-dts-rockchip-add-LED-configuration-to-Orange-P.patch b/target/linux/rockchip/patches-6.1/108-arm64-dts-rockchip-add-LED-configuration-to-Orange-P.patch
index 37b59925fc16dc..af8f8b16bada0a 100644
--- a/target/linux/rockchip/patches-6.1/108-arm64-dts-rockchip-add-LED-configuration-to-Orange-P.patch
+++ b/target/linux/rockchip/patches-6.1/108-arm64-dts-rockchip-add-LED-configuration-to-Orange-P.patch
@@ -14,7 +14,7 @@ Signed-off-by: Tianling Shen <cnsztl@gmail.com>
 
 --- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
 +++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
-@@ -362,6 +362,7 @@
+@@ -365,6 +365,7 @@
  	rtl8153: device@2 {
  		compatible = "usbbda,8153";
  		reg = <2>;
diff --git a/target/linux/rockchip/patches-6.1/110-arm64-dts-rockchip-Update-LED-properties-for-NanoPi-.patch b/target/linux/rockchip/patches-6.1/110-arm64-dts-rockchip-Update-LED-properties-for-NanoPi-.patch
index 64dc433a30ae13..c22fdd52b8a789 100644
--- a/target/linux/rockchip/patches-6.1/110-arm64-dts-rockchip-Update-LED-properties-for-NanoPi-.patch
+++ b/target/linux/rockchip/patches-6.1/110-arm64-dts-rockchip-Update-LED-properties-for-NanoPi-.patch
@@ -5,82 +5,30 @@ Subject: [PATCH] arm64: dts: rockchip: Update LED properties for NanoPi R5
  series
 
 Add OpenWrt's LED aliases for showing system status.
-Also replace function/color with legacy label as OpenWrt relys on it
-to update LED settings.
 
 Signed-off-by: Tianling Shen <cnsztl@gmail.com>
 ---
 
 --- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts
 +++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts
-@@ -32,27 +32,22 @@
- 		pinctrl-0 = <&lan_led_pin>, <&power_led_pin>, <&wan_led_pin>, <&wlan_led_pin>;
- 
- 		led-lan {
--			color = <LED_COLOR_ID_GREEN>;
--			function = LED_FUNCTION_LAN;
-+			label = "green:lan";
- 			gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>;
- 		};
- 
+@@ -40,7 +40,6 @@
  		power_led: led-power {
--			color = <LED_COLOR_ID_RED>;
--			function = LED_FUNCTION_POWER;
+ 			color = <LED_COLOR_ID_RED>;
+ 			function = LED_FUNCTION_POWER;
 -			linux,default-trigger = "heartbeat";
-+			label = "red:power";
  			gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>;
  		};
  
- 		led-wan {
--			color = <LED_COLOR_ID_GREEN>;
--			function = LED_FUNCTION_WAN;
-+			label = "green:wan";
- 			gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
- 		};
- 
- 		led-wlan {
--			color = <LED_COLOR_ID_GREEN>;
--			function = LED_FUNCTION_WLAN;
-+			label = "green:wlan";
- 			gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>;
- 		};
- 	};
 --- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
 +++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
-@@ -23,29 +23,22 @@
- 		pinctrl-0 = <&lan1_led_pin>, <&lan2_led_pin>, <&power_led_pin>, <&wan_led_pin>;
- 
- 		led-lan1 {
--			color = <LED_COLOR_ID_GREEN>;
--			function = LED_FUNCTION_LAN;
--			function-enumerator = <1>;
-+			label = "green:lan1";
- 			gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>;
- 		};
- 
- 		led-lan2 {
--			color = <LED_COLOR_ID_GREEN>;
--			function = LED_FUNCTION_LAN;
--			function-enumerator = <2>;
-+			label = "green:lan2";
- 			gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>;
- 		};
- 
+@@ -39,7 +39,6 @@
  		power_led: led-power {
--			color = <LED_COLOR_ID_RED>;
--			function = LED_FUNCTION_POWER;
+ 			color = <LED_COLOR_ID_RED>;
+ 			function = LED_FUNCTION_POWER;
 -			linux,default-trigger = "heartbeat";
-+			label = "red:power";
  			gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
  		};
  
- 		led-wan {
--			color = <LED_COLOR_ID_GREEN>;
--			function = LED_FUNCTION_WAN;
-+			label = "green:wan";
- 			gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
- 		};
- 	};
 --- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi
 +++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi
 @@ -18,6 +18,11 @@
diff --git a/target/linux/rockchip/patches-6.1/111-radxa-cm3-io-add-led-aliases.patch b/target/linux/rockchip/patches-6.1/111-radxa-cm3-io-add-led-aliases.patch
new file mode 100644
index 00000000000000..c8183a2b8ae9b6
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/111-radxa-cm3-io-add-led-aliases.patch
@@ -0,0 +1,36 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Marius Durbaca <mariusd84@gmail.com>
+Date: Tue Feb 20 15:05:27 2024 +0200
+Subject: [PATCH] arm64: dts: rockchip: Update LED properties for Radxa 
+CM3 IO board
+
+Add OpenWrt's LED aliases for showing system status.
+
+Suggested-by: Tianling Shen <cnsztl@immortalwrt.org>
+Signed-off-by: Marius Durbaca <mariusd84@gmail.com>
+---
+
+--- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
+@@ -16,6 +16,10 @@
+ 	aliases {
+ 		ethernet0 = &gmac1;
+ 		mmc1 = &sdmmc0;
++		led-boot = &status_led;
++		led-failsafe = &status_led;
++		led-running = &status_led;
++		led-upgrade = &status_led;
+ 	};
+ 
+ 	chosen: chosen {
+--- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi
+@@ -17,7 +17,7 @@
+ 	leds {
+ 		compatible = "gpio-leds";
+ 
+-		led-0 {
++		status_led: led-0 {
+ 			gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+ 			color = <LED_COLOR_ID_GREEN>;
+ 			function = LED_FUNCTION_STATUS;
diff --git a/toolchain/binutils/Config.in b/toolchain/binutils/Config.in
index 3ec4fe47a8f3a9..6ba3c5248723bd 100644
--- a/toolchain/binutils/Config.in
+++ b/toolchain/binutils/Config.in
@@ -25,6 +25,10 @@ choice
 	config BINUTILS_USE_VERSION_2_41
 		bool "Binutils 2.41"
 		select BINUTILS_VERSION_2_41
+
+	config BINUTILS_USE_VERSION_2_42
+		bool "Binutils 2.42"
+		select BINUTILS_VERSION_2_42
 endchoice
 
 config EXTRA_BINUTILS_CONFIG_OPTIONS
diff --git a/toolchain/binutils/Config.version b/toolchain/binutils/Config.version
index acb764bb6a741b..e7a5abcd7e067b 100644
--- a/toolchain/binutils/Config.version
+++ b/toolchain/binutils/Config.version
@@ -15,6 +15,9 @@ config BINUTILS_VERSION_2_40
 config BINUTILS_VERSION_2_41
 	bool
 
+config BINUTILS_VERSION_2_42
+	bool
+
 config BINUTILS_VERSION
 	string
 	default "2.37"			if BINUTILS_VERSION_2_37
@@ -22,3 +25,4 @@ config BINUTILS_VERSION
 	default "2.39"			if BINUTILS_VERSION_2_39
 	default "2.40"			if BINUTILS_VERSION_2_40
 	default "2.41"			if BINUTILS_VERSION_2_41
+	default "2.42"			if BINUTILS_VERSION_2_42
diff --git a/toolchain/binutils/Makefile b/toolchain/binutils/Makefile
index 1a7b877e6381f4..8635e9710ac64e 100644
--- a/toolchain/binutils/Makefile
+++ b/toolchain/binutils/Makefile
@@ -36,6 +36,10 @@ ifeq ($(PKG_VERSION),2.41)
   PKG_HASH:=ae9a5789e23459e59606e6714723f2d3ffc31c03174191ef0d015bdf06007450
 endif
 
+ifeq ($(PKG_VERSION),2.42)
+  PKG_HASH:=f6e4d41fd5fc778b06b7891457b3620da5ecea1006c6a4a41ae998109f85a800
+endif
+
 HOST_BUILD_PARALLEL:=1
 
 PATCH_DIR:=./patches/$(PKG_VERSION)
diff --git a/toolchain/binutils/patches/2.42/300-001_ld_makefile_patch.patch b/toolchain/binutils/patches/2.42/300-001_ld_makefile_patch.patch
new file mode 100644
index 00000000000000..64dae55dd77d94
--- /dev/null
+++ b/toolchain/binutils/patches/2.42/300-001_ld_makefile_patch.patch
@@ -0,0 +1,22 @@
+--- a/ld/Makefile.am
++++ b/ld/Makefile.am
+@@ -50,7 +50,7 @@ AM_CFLAGS = $(WARN_CFLAGS) $(ELF_CFLAGS)
+ # We put the scripts in the directory $(scriptdir)/ldscripts.
+ # We can't put the scripts in $(datadir) because the SEARCH_DIR
+ # directives need to be different for native and cross linkers.
+-scriptdir = $(tooldir)/lib
++scriptdir = $(libdir)
+ 
+ EMUL = @EMUL@
+ EMULATION_OFILES = @EMULATION_OFILES@
+--- a/ld/Makefile.in
++++ b/ld/Makefile.in
+@@ -583,7 +583,7 @@ AM_CFLAGS = $(WARN_CFLAGS) $(ELF_CFLAGS)
+ # We put the scripts in the directory $(scriptdir)/ldscripts.
+ # We can't put the scripts in $(datadir) because the SEARCH_DIR
+ # directives need to be different for native and cross linkers.
+-scriptdir = $(tooldir)/lib
++scriptdir = $(libdir)
+ BASEDIR = $(srcdir)/..
+ BFDDIR = $(BASEDIR)/bfd
+ INCDIR = $(BASEDIR)/include
diff --git a/toolchain/binutils/patches/2.42/400-mips_no_dynamic_linking_sym.patch b/toolchain/binutils/patches/2.42/400-mips_no_dynamic_linking_sym.patch
new file mode 100644
index 00000000000000..30f70c21239007
--- /dev/null
+++ b/toolchain/binutils/patches/2.42/400-mips_no_dynamic_linking_sym.patch
@@ -0,0 +1,18 @@
+--- a/bfd/elfxx-mips.c
++++ b/bfd/elfxx-mips.c
+@@ -8149,6 +8149,7 @@ _bfd_mips_elf_create_dynamic_sections (b
+ 
+       name = SGI_COMPAT (abfd) ? "_DYNAMIC_LINK" : "_DYNAMIC_LINKING";
+       bh = NULL;
++      if (0) {
+       if (!(_bfd_generic_link_add_one_symbol
+ 	    (info, abfd, name, BSF_GLOBAL, bfd_abs_section_ptr, 0,
+ 	     NULL, false, get_elf_backend_data (abfd)->collect, &bh)))
+@@ -8161,6 +8162,7 @@ _bfd_mips_elf_create_dynamic_sections (b
+ 
+       if (! bfd_elf_link_record_dynamic_symbol (info, h))
+ 	return false;
++      }
+ 
+       if (! mips_elf_hash_table (info)->use_rld_obj_head)
+ 	{
diff --git a/toolchain/binutils/patches/2.42/500-Change-default-emulation-for-mips64-linux.patch b/toolchain/binutils/patches/2.42/500-Change-default-emulation-for-mips64-linux.patch
new file mode 100644
index 00000000000000..df38fcaba14e76
--- /dev/null
+++ b/toolchain/binutils/patches/2.42/500-Change-default-emulation-for-mips64-linux.patch
@@ -0,0 +1,48 @@
+--- a/bfd/config.bfd
++++ b/bfd/config.bfd
+@@ -962,8 +962,8 @@ case "${targ}" in
+     want64=true
+     ;;
+   mips64*el-*-linux*)
+-    targ_defvec=mips_elf32_ntrad_le_vec
+-    targ_selvecs="mips_elf32_ntrad_be_vec mips_elf32_trad_le_vec mips_elf32_trad_be_vec mips_elf64_trad_le_vec mips_elf64_trad_be_vec"
++    targ_defvec=mips_elf64_trad_le_vec
++    targ_selvecs="mips_elf32_ntrad_le_vec mips_elf32_ntrad_be_vec mips_elf32_trad_le_vec mips_elf32_trad_be_vec mips_elf64_trad_be_vec"
+     ;;
+   mips64*-*-linux*-gnuabi64)
+     targ_defvec=mips_elf64_trad_be_vec
+@@ -971,8 +971,8 @@ case "${targ}" in
+     want64=true
+     ;;
+   mips64*-*-linux*)
+-    targ_defvec=mips_elf32_ntrad_be_vec
+-    targ_selvecs="mips_elf32_ntrad_le_vec mips_elf32_trad_be_vec mips_elf32_trad_le_vec mips_elf64_trad_be_vec mips_elf64_trad_le_vec"
++    targ_defvec=mips_elf64_trad_be_vec
++    targ_selvecs="mips_elf32_ntrad_be_vec mips_elf32_ntrad_le_vec mips_elf32_trad_be_vec mips_elf32_trad_le_vec mips_elf64_trad_le_vec"
+     ;;
+   mips*el-*-linux*)
+     targ_defvec=mips_elf32_trad_le_vec
+--- a/ld/configure.tgt
++++ b/ld/configure.tgt
+@@ -597,8 +597,8 @@ mips64*el-*-linux-gnuabi64)
+ 			targ_extra_emuls="elf64btsmip elf32ltsmipn32 elf32btsmipn32 elf32ltsmip elf32btsmip"
+ 			targ_extra_libpath=$targ_extra_emuls
+ 			;;
+-mips64*el-*-linux-*)	targ_emul=elf32ltsmipn32
+-			targ_extra_emuls="elf32btsmipn32 elf32ltsmip elf32btsmip elf64ltsmip elf64btsmip"
++mips64*el-*-linux-*)	targ_emul=elf64ltsmip
++			targ_extra_emuls="elf32btsmipn32 elf32ltsmipn32 elf32ltsmip elf32btsmip elf64btsmip"
+ 			targ_extra_libpath=$targ_extra_emuls
+ 			;;
+ mips64*-*-linux-gnuabi64)
+@@ -606,8 +606,8 @@ mips64*-*-linux-gnuabi64)
+ 			targ_extra_emuls="elf64ltsmip elf32btsmipn32 elf32ltsmipn32 elf32btsmip elf32ltsmip"
+ 			targ_extra_libpath=$targ_extra_emuls
+ 			;;
+-mips64*-*-linux-*)	targ_emul=elf32btsmipn32
+-			targ_extra_emuls="elf32ltsmipn32 elf32btsmip elf32ltsmip elf64btsmip elf64ltsmip"
++mips64*-*-linux-*)	targ_emul=elf64btsmip
++			targ_extra_emuls="elf32btsmipn32 elf32ltsmipn32 elf32btsmip elf32ltsmip elf64ltsmip"
+ 			targ_extra_libpath=$targ_extra_emuls
+ 			;;
+ mips*el-*-linux-*)	targ_emul=elf32ltsmip
diff --git a/toolchain/glibc/common.mk b/toolchain/glibc/common.mk
index 6b237f54789c94..65e9e0c3240659 100644
--- a/toolchain/glibc/common.mk
+++ b/toolchain/glibc/common.mk
@@ -12,8 +12,8 @@ PKG_RELEASE:=1
 
 PKG_SOURCE_PROTO:=git
 PKG_SOURCE_SUBDIR:=$(PKG_NAME)-$(PKG_VERSION)
-PKG_SOURCE_VERSION:=b4e23c75aea756b4bddc4abcf27a1c6dca8b6bd3
-PKG_MIRROR_HASH:=4d5b3de6ec7b47427700f74fdb529e32083b54a512f6ca86ec824a61092ecdd4
+PKG_SOURCE_VERSION:=eee7525d35ec16bbe81435e41079ab72519d825c
+PKG_MIRROR_HASH:=fad5a67d9622b75bce5e3e8c91b07a6df0bf8b21cb001a6d06019a6ce4cff31f
 PKG_SOURCE_URL:=https://sourceware.org/git/glibc.git
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION)-$(PKG_SOURCE_VERSION).tar.xz
 PKG_CPE_ID:=cpe:/a:gnu:glibc
diff --git a/tools/ccache/Makefile b/tools/ccache/Makefile
index f76be9f90edd4c..5720dabf6ed663 100644
--- a/tools/ccache/Makefile
+++ b/tools/ccache/Makefile
@@ -7,11 +7,11 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=ccache
-PKG_VERSION:=4.8.3
+PKG_VERSION:=4.9.1
 
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
 PKG_SOURCE_URL:=https://github.com/ccache/ccache/releases/download/v$(PKG_VERSION)
-PKG_HASH:=e47374c810b248cfca3665ee1d86c7c763ffd68d9944bc422d9c1872611f2b11
+PKG_HASH:=4c03bc840699127d16c3f0e6112e3f40ce6a230d5873daa78c60a59c7ef59d25
 
 include $(INCLUDE_DIR)/host-build.mk
 include $(INCLUDE_DIR)/cmake.mk
diff --git a/tools/ccache/patches/100-honour-copts.patch b/tools/ccache/patches/100-honour-copts.patch
index 91dc35536fb80c..8f1c4265018806 100644
--- a/tools/ccache/patches/100-honour-copts.patch
+++ b/tools/ccache/patches/100-honour-copts.patch
@@ -1,10 +1,10 @@
 --- a/src/ccache.cpp
 +++ b/src/ccache.cpp
-@@ -1815,6 +1815,7 @@ get_manifest_key(Context& ctx, Hash& has
-                            "CPLUS_INCLUDE_PATH",
-                            "OBJC_INCLUDE_PATH",
-                            "OBJCPLUS_INCLUDE_PATH", // clang
-+                           "GCC_HONOUR_COPTS",
-                            nullptr};
+@@ -1841,6 +1841,7 @@ get_manifest_key(Context& ctx, Hash& has
+     "OBJCPLUS_INCLUDE_PATH",        // Clang
+     "CLANG_CONFIG_FILE_SYSTEM_DIR", // Clang
+     "CLANG_CONFIG_FILE_USER_DIR",   // Clang
++    "GCC_HONOUR_COPTS",
+     nullptr,
+   };
    for (const char** p = envvars; *p; ++p) {
-     const char* v = getenv(*p);
diff --git a/tools/cmake/Makefile b/tools/cmake/Makefile
index b67789385ec702..d73f3fba62fe4a 100644
--- a/tools/cmake/Makefile
+++ b/tools/cmake/Makefile
@@ -7,7 +7,7 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=cmake
-PKG_VERSION:=3.28.1
+PKG_VERSION:=3.28.3
 PKG_VERSION_MAJOR:=$(word 1,$(subst ., ,$(PKG_VERSION))).$(word 2,$(subst ., ,$(PKG_VERSION)))
 PKG_RELEASE:=1
 PKG_CPE_ID:=cpe:/a:kitware:cmake
@@ -15,7 +15,7 @@ PKG_CPE_ID:=cpe:/a:kitware:cmake
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
 PKG_SOURCE_URL:=https://github.com/Kitware/CMake/releases/download/v$(PKG_VERSION)/ \
 		https://cmake.org/files/v$(PKG_VERSION_MAJOR)/
-PKG_HASH:=15e94f83e647f7d620a140a7a5da76349fc47a1bfed66d0f5cdee8e7344079ad
+PKG_HASH:=72b7570e5c8593de6ac4ab433b73eab18c5fb328880460c86ce32608141ad5c1
 
 HOST_BUILD_PARALLEL:=1
 HOST_CONFIGURE_PARALLEL:=1
diff --git a/tools/dwarves/Makefile b/tools/dwarves/Makefile
index 0e84a1ba9fdcdd..f48516fcdfaf89 100644
--- a/tools/dwarves/Makefile
+++ b/tools/dwarves/Makefile
@@ -3,12 +3,12 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=dwarves
-PKG_VERSION:=1.25
+PKG_VERSION:=1.26
 PKG_RELEASE:=1
 
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
 PKG_SOURCE_URL:=https://fedorapeople.org/~acme/dwarves/
-PKG_HASH:=e7d45955f6f4eca25a4c8c3bd6611059b35dc217e45976681d7db170fccdec4a
+PKG_HASH:=ad4c08339850e404609e2808012580b7e98366d2b91054bb93fe6dca94651fb4
 
 PKG_LICENSE:=GPL-2.0-only
 PKG_LICENSE_FILES:=COPYING
diff --git a/tools/expat/Makefile b/tools/expat/Makefile
index c1a8cb8d97927f..1df6f8ec965779 100644
--- a/tools/expat/Makefile
+++ b/tools/expat/Makefile
@@ -9,10 +9,10 @@ include $(TOPDIR)/rules.mk
 
 PKG_NAME:=expat
 PKG_CPE_ID:=cpe:/a:libexpat:expat
-PKG_VERSION:=2.5.0
+PKG_VERSION:=2.6.0
 
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
-PKG_HASH:=ef2420f0232c087801abf705e89ae65f6257df6b7931d37846a193ef2e8cdcbe
+PKG_HASH:=cb5f5a8ea211e1cabd59be0a933a52e3c02cc326e86a4d387d8d218e7ee47a3e
 PKG_SOURCE_URL:=https://github.com/libexpat/libexpat/releases/download/R_$(subst .,_,$(PKG_VERSION))
 
 HOST_BUILD_PARALLEL:=1
@@ -24,6 +24,7 @@ HOSTCC := $(HOSTCC_NOCACHE)
 HOST_CONFIGURE_ARGS += \
 	--disable-shared \
 	--without-docbook \
+	--without-tests \
 	--with-pic
 
 define Host/Uninstall
diff --git a/tools/pkgconf/Makefile b/tools/pkgconf/Makefile
index a4eeaae56ba960..e1dea71c8a31c4 100644
--- a/tools/pkgconf/Makefile
+++ b/tools/pkgconf/Makefile
@@ -7,11 +7,11 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=pkgconf
-PKG_VERSION:=2.1.0
+PKG_VERSION:=2.1.1
 
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
 PKG_SOURCE_URL:=https://distfiles.dereferenced.org/pkgconf
-PKG_HASH:=266d5861ee51c52bc710293a1d36622ae16d048d71ec56034a02eb9cf9677761
+PKG_HASH:=3a224f2accf091b77a5781316e27b9ee3ba82c083cc2e539e08940b68a44fec5
 
 PKG_CPE_ID:=cpe:/a:pkgconf:pkgconf