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Commits on Mar 25, 2020

• add binutils for m&l sign-unsigned operands

  

  agarofalo

  committed
  0e268af

• fix mask for m&l 16-bit

  

  agarofalo

  committed
  fcb234a

• extend binutils to support SPR 2 and 3 (mac&load)

  

  agarofalo

  committed
  180538f

Commits on Mar 19, 2020

• fix mask for nibble ops

  

  agarofalo

  committed
  8a98a6b

Commits on Mar 17, 2020

• Support for pv.mlsdotup.[h,b,c,n]].[0,1] instructions (MAC & load)

  gtagliavini

  committed
  2c86125

Commits on May 16, 2019

• added Xpulpnn ext. (nibble and crumb vectorial insns)

  anga93

  committed
  dc4e201

Commits on Apr 3, 2019

• Add support for vectorial short floats

  eflamand

  committed
  7a60fa9

Commits on Feb 27, 2019

• Support for new vega complex instructions

  eflamand

  committed
  0734113

Commits on Nov 5, 2018

• Support for Vega/Gap9

  eflamand

  committed
  2747d44

Commits on Oct 11, 2018

• Filter out CSR when target is gap8

  eflamand

  committed
  faa880a

Commits on Jan 18, 2018

• Initial commit to port to gap

  eflamand

  committed
  441e420

Commits on May 5, 2017

• RISC-V GDB Port

  Show description for 3b5db3f
  palmer-dabbelt

  committed
  3b5db3f

• RISC-V: Resurrect GP-relative disassembly hints

  Show description for 8dbb8a1
  palmer-dabbelt

  committed
  8dbb8a1

Commits on Apr 3, 2017

• Add physical memory protection CSRs

  Show description for e7294f7
  

  aswaterman

  authored and

  palmer-dabbelt

  committed
  e7294f7

Commits on Mar 21, 2017

• S/390: Remove vx2 facility flag

  Show description for a7587e7
  

  Andreas Krebbel

  committed
  a7587e7

Commits on Feb 28, 2017

• PowerPC addpcis fix

  Show description for 6ad77d0
  amodra

  committed
  6ad77d0

Commits on Feb 27, 2017

• Add new counter-enable CSRs

  Show description for 347a757
  

  aswaterman

  authored and

  palmer-dabbelt

  committed
  347a757

• Add SFENCE.VMA instruction

  Show description for af5d206
  

  aswaterman

  authored and

  palmer-dabbelt

  committed
  af5d206

• sve

  Show description for 1e0971e
  rsandifo-arm

  committed
  1e0971e

• sve

  Show description for 3457862
  rsandifo-arm

  committed
  3457862

• [AArch64] Add separate feature flag for weaker release consistent load insns

  Show description for 3843af6
  rsandifo-arm

  committed
  3843af6

Commits on Feb 23, 2017

• S/390: Add support for new cpu architecture - arch12.

  Show description for c7b66f4
  

  Andreas Krebbel

  committed
  c7b66f4

Commits on Jan 2, 2017

• Update year range in copyright notice of all files.

  amodra

  committed
  f5a2e27

• ChangeLog rotation

  amodra

  committed
  3cd15e6

Commits on Dec 23, 2016

• MIPS16: Add ASMACRO instruction support

  Show description for 9dcf357
  

  Maciej W. Rozycki

  committed
  9dcf357

• MIPS16: Reassign 0' and 4' operand codes

  Show description for 0339705
  

  Maciej W. Rozycki

  committed
  0339705

• MIPS16: Handle non-extensible instructions correctly

  Show description for 2e9669a
  

  Maciej W. Rozycki

  committed
  2e9669a

Commits on Dec 21, 2016

• Remove high bit set characters

  Show description for 4e25adb
  amodra

  committed
  4e25adb

Commits on Dec 20, 2016

• MIPS16: Switch to 32-bit opcode table interpretation

  Show description for 7fd5392
  

  Maciej W. Rozycki

  committed
  7fd5392

• Re-work RISC-V gas flags: now we just support -mabi and -march

  Show description for 2922d21
  

  aswaterman

  authored and

  amodra

  committed
  2922d21

• Rework RISC-V relocations

  Show description for 45f7642
  

  aswaterman

  authored and

  amodra

  committed
  45f7642

Commits on Dec 16, 2016

• Implement and document --gc-keep-exported

  Show description for 2218550
  

  fincs

  authored and

  amodra

  committed
  2218550

Commits on Dec 14, 2016

• MIPS/opcodes: Also set disassembler's ASE flags from ELF structures

  Show description for 5e7fc73
  

  Maciej W. Rozycki

  committed
  5e7fc73

Commits on Dec 13, 2016

• [Binutils][AARCH64]Remove Cn register for coprocessor CRn, CRm field

  Show description for a6a5175
  

  Renlin Li

  committed
  a6a5175

Commits on Dec 9, 2016

• MIPS16: Remove unused `>' operand code

  Show description for 64c1118
  

  Maciej W. Rozycki

  committed
  64c1118

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