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Commits on Dec 30, 2021

• IPrefetch: add prefetch address merge and counter (OpenXiangShan#1404)

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  jinyue110

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  a108d42

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• ReplacePipe: exclude probe do not need data (OpenXiangShan#1408)

  jinyue110

  authored
  0bebd82

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Commits on Dec 29, 2021

• ICache: add parity check enable and prefetch enable control registers (OpenXiangShan#1406)

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  jinyue110

  authored
  ecccf78

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• IFU: fix fetching RVC instructions from mmio space bug (OpenXiangShan#1407)

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  jinyue110

  authored
  ee175d7

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• csr: add one/two cycle for signals customCtrl/tlb/csrUpdate (OpenXiangShan#1405)

  Lemover

  authored
  c7f0997

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• dispatch: block enq when previous instructions have exception (OpenXiangShan#1400)

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  poemonsense

  authored
  3a6db8a

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• bump huancun (OpenXiangShan#1402)

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  wakafa1

  and

  ljwljwljwljw

  authored
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Commits on Dec 28, 2021

• mem: refactor l1 error implementation (OpenXiangShan#1391)

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Commits on Dec 27, 2021

• Merge pull request OpenXiangShan#1399 from OpenXiangShan/add_tlpma_buffer

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  rvcoresjw

  authored
  d972105

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• queuePtr: set isAfter when different flags and same value (OpenXiangShan#1396)

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  poemonsense

  authored
  e9ae4a3

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• add buffer at tl pma

  rvcoresjw

  committed
  ea8d8ca

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Commits on Dec 26, 2021

• atomic: fix exception valid after OpenXiangShan#1392 (OpenXiangShan#1395)

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  poemonsense

  authored
  207ef62

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• scripts,xs: ignore get_cores when numa is not set (OpenXiangShan#1397)

  poemonsense

  authored
  c9d90c8

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• atomic: add static pmp relative modification (OpenXiangShan#1394)

  Lemover

  authored
  cba0a7e

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Commits on Dec 25, 2021

• mem: fix ld-ld violation writeback priority (OpenXiangShan#1393)

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  AugustusWillisWang

  authored
  46fe327

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Commits on Dec 24, 2021

• atomics: delay exception.valid for more cycles (OpenXiangShan#1392)

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  poemonsense

  authored
  231d339

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• mem: implement lrsc backoff to survive in lr storm (OpenXiangShan#1383)

  AugustusWillisWang

  authored
  b899def

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Commits on Dec 23, 2021

• IPrefetch: fix prefetchPtr stop problem (OpenXiangShan#1387)

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  jinyue110

  authored
  de7689f

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Commits on Dec 22, 2021

• mem: optimize missq reject to lq timing (OpenXiangShan#1375)

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  AugustusWillisWang

  authored
  6b6d88e

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• ci: add cacheop test (without difftest) (OpenXiangShan#1370)

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  AugustusWillisWang

  authored
  9c29729

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Commits on Dec 21, 2021

• dcache: use sram to build ecc array (OpenXiangShan#1382)

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  AugustusWillisWang

  authored
  41b6847

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• lsq: add LsqEnqCtrl to optimize enqueue timing (OpenXiangShan#1380)

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  poemonsense

  authored
  10551d4

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• sbuffer: optimize sbuffer enqueue timing (OpenXiangShan#1379)

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  AugustusWillisWang

  authored
  67c26c3

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• bump ready-to-run, update nemu so for xtvec vector mode (OpenXiangShan#1381)

  Lemover

  authored
  c154173

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• support cmo (OpenXiangShan#1360)

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  wakafa1

  authored
  9e2176f

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• Add simple instruction prefetch for L2 (directed by branch prediction) (OpenXiangShan#1374)

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  jinyue110

  authored
  7052722

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• Merge pull request OpenXiangShan#1340 from OpenXiangShan/trigger

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  notlqr

  authored
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Commits on Dec 20, 2021

• difftest: fix missing AlwaysBasicDiff option in WbArbiter (OpenXiangShan#1378)

  BigWhiteDog

  authored
  a2c8bd3

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• ICache: raise AF exception when parity wrong or L2 send corrupt (OpenXiangShan#1376)

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  jinyue110

  authored
  58dbdfc

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• Merge branch 'master' into trigger

  notlqr

  committed
  6e208dd

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• dcache: speed up main pipe data write valid gen (OpenXiangShan#1377)

  AugustusWillisWang

  authored
  184d2cf

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• Merge branch 'master' into trigger

  notlqr

  committed
  a4e57ea

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• dcache: let ecc error and l2 corrupt raise load af (OpenXiangShan#1369)

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  AugustusWillisWang

  authored
  026615f

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• ICacheMainPipe: fix miss_0_except_1 resend problem (OpenXiangShan#1373)

  jinyue110

  authored
  42b952e

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Commits on Dec 18, 2021

• csr: optimize exception and trapTarget timing (OpenXiangShan#1372)

  poemonsense

  authored
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