From a58482a4cf1a6671429e8062e0138dcca143eec1 Mon Sep 17 00:00:00 2001 From: phantom1003 Date: Sun, 25 Apr 2021 19:49:25 +0800 Subject: [PATCH] Using maskrom as first stage bootloader --- Makefile | 21 +++- firmware/fsbl/.gitignore | 1 + {fsbl/sdboot => firmware/fsbl}/Makefile | 20 +++- {fsbl/sdboot => firmware/fsbl}/common.h | 0 {fsbl/sdboot => firmware/fsbl}/head.S | 0 {fsbl/sdboot => firmware/fsbl}/include/bits.h | 0 .../sdboot => firmware/fsbl}/include/const.h | 0 .../fsbl}/include/devices/clint.h | 0 .../fsbl}/include/devices/gpio.h | 0 .../fsbl}/include/devices/plic.h | 0 .../fsbl}/include/devices/spi.h | 0 .../fsbl}/include/devices/uart.h | 0 .../fsbl}/include/platform.h | 0 .../fsbl}/include/sections.h | 0 {fsbl/sdboot => firmware/fsbl}/include/smp.h | 0 {fsbl/sdboot => firmware/fsbl}/kprintf.c | 0 {fsbl/sdboot => firmware/fsbl}/kprintf.h | 0 .../fsbl}/linker/memory.lds | 2 +- .../fsbl}/linker/sdboot.elf.lds | 0 {fsbl/sdboot => firmware/fsbl}/sd.c | 0 firmware/zsbl/.gitignore | 1 + firmware/zsbl/Makefile | 32 +++++ firmware/zsbl/bootrom.S | 10 ++ firmware/zsbl/linker.ld | 7 ++ fsbl/sdboot/.gitignore | 1 - fsbl/sdboot/rocketchip.dts | 112 ------------------ src/main/scala/FPGA/Configs.scala | 10 +- 27 files changed, 91 insertions(+), 126 deletions(-) create mode 100644 firmware/fsbl/.gitignore rename {fsbl/sdboot => firmware/fsbl}/Makefile (71%) rename {fsbl/sdboot => firmware/fsbl}/common.h (100%) rename {fsbl/sdboot => firmware/fsbl}/head.S (100%) rename {fsbl/sdboot => firmware/fsbl}/include/bits.h (100%) rename {fsbl/sdboot => firmware/fsbl}/include/const.h (100%) rename {fsbl/sdboot => firmware/fsbl}/include/devices/clint.h (100%) rename {fsbl/sdboot => firmware/fsbl}/include/devices/gpio.h (100%) rename {fsbl/sdboot => firmware/fsbl}/include/devices/plic.h (100%) rename {fsbl/sdboot => firmware/fsbl}/include/devices/spi.h (100%) rename {fsbl/sdboot => firmware/fsbl}/include/devices/uart.h (100%) rename {fsbl/sdboot => firmware/fsbl}/include/platform.h (100%) rename {fsbl/sdboot => firmware/fsbl}/include/sections.h (100%) rename {fsbl/sdboot => firmware/fsbl}/include/smp.h (100%) rename {fsbl/sdboot => firmware/fsbl}/kprintf.c (100%) rename {fsbl/sdboot => firmware/fsbl}/kprintf.h (100%) rename {fsbl/sdboot => firmware/fsbl}/linker/memory.lds (57%) rename {fsbl/sdboot => firmware/fsbl}/linker/sdboot.elf.lds (100%) rename {fsbl/sdboot => firmware/fsbl}/sd.c (100%) create mode 100644 firmware/zsbl/.gitignore create mode 100644 firmware/zsbl/Makefile create mode 100644 firmware/zsbl/bootrom.S create mode 100644 firmware/zsbl/linker.ld delete mode 100644 fsbl/sdboot/.gitignore delete mode 100644 fsbl/sdboot/rocketchip.dts diff --git a/Makefile b/Makefile index b4654cd..4ef0b17 100644 --- a/Makefile +++ b/Makefile @@ -45,7 +45,7 @@ $(ROCKET_VERILOG): $(ROCKET_FIRRTL) mkdir -p $(ROCKET_BUILD) $(ROCKET_JAVA) "runMain firrtl.stage.FirrtlMain \ -td $(ROCKET_BUILD) --infer-rw $(ROCKET_TOP) \ - --repl-seq-mem -c:$(ROCKET_TOP):-o:$(ROCKET_BUILD)/$(ROCKET_OUTPUT).rom.conf \ + --repl-seq-mem -c:$(ROCKET_TOP):-o:$(ROCKET_BUILD)/$(ROCKET_OUTPUT).sram.conf \ -faf $(ROCKET_BUILD)/$(ROCKET_OUTPUT).anno.json \ -fct firrtl.passes.InlineInstances \ -i $< -o $@ -X verilog" @@ -58,14 +58,23 @@ verilog: $(ROCKET_VERILOG) # ####################################### +FIRMWARE_SRC := $(TOP)/firmware +FIRMWARE_BUILD := $(BUILD)/firmware +FSBL_SRC := $(FIRMWARE_SRC)/fsbl +FSBL_BUILD := $(FIRMWARE_BUILD)/fsbl +STARSHIP_ROM_HEX := $(FSBL_BUILD)/sdboot.hex + BOARD := vc707 SCRIPT_SRC := $(SRC)/fpga-shells VIVADO_SRC := $(SCRIPT_SRC)/xilinx VIVADO_BUILD := $(BUILD)/vivado VIVADO_BITSTREAM := $(VIVADO_BUILD)/$(ROCKET_OUTPUT).bit VERILOG_SRAM := $(ROCKET_BUILD)/$(ROCKET_OUTPUT).behav_srams.v +VERILOG_ROM := $(ROCKET_BUILD)/$(ROCKET_OUTPUT).rom.v VERILOG_INCLUDE := $(VIVADO_BUILD)/$(ROCKET_OUTPUT).vsrc.f VERILOG_SRC := $(VERILOG_SRAM) \ + $(VERILOG_ROM) \ + $(STARSHIP_ROM_HEX) \ $(ROCKET_BUILD)/$(ROCKET_OUTPUT).v \ $(ROCKET_BUILD)/plusarg_reader.v \ $(VIVADO_SRC)/$(BOARD)/vsrc/sdio.v \ @@ -76,9 +85,15 @@ $(VERILOG_INCLUDE): echo $(VERILOG_SRC) > $@ $(VERILOG_SRAM): - $(ROCKET_SRC)/scripts/vlsi_mem_gen $(ROCKET_BUILD)/$(ROCKET_OUTPUT).rom.conf >> $@ + $(ROCKET_SRC)/scripts/vlsi_mem_gen $(ROCKET_BUILD)/$(ROCKET_OUTPUT).sram.conf >> $@ + +$(STARSHIP_ROM_HEX): + $(MAKE) -C $(FSBL_SRC) PBUS_CLK=$(ROCKET_FREQ)000000 ROOT_DIR=$(TOP) ROCKET_OUTPUT=$(ROCKET_OUTPUT) hex + +$(VERILOG_ROM): $(STARSHIP_ROM_HEX) + $(ROCKET_SRC)/scripts/vlsi_rom_gen $(ROCKET_BUILD)/$(ROCKET_OUTPUT).rom.conf $< > $@ -$(VIVADO_BITSTREAM): $(ROCKET_VERILOG) $(VERILOG_INCLUDE) $(VERILOG_SRAM) +$(VIVADO_BITSTREAM): $(ROCKET_VERILOG) $(VERILOG_INCLUDE) $(VERILOG_SRAM) $(VERILOG_ROM) mkdir -p $(VIVADO_BUILD) cd $(VIVADO_BUILD); vivado -mode batch -nojournal \ -source $(VIVADO_SRC)/common/tcl/vivado.tcl \ diff --git a/firmware/fsbl/.gitignore b/firmware/fsbl/.gitignore new file mode 100644 index 0000000..d163863 --- /dev/null +++ b/firmware/fsbl/.gitignore @@ -0,0 +1 @@ +build/ \ No newline at end of file diff --git a/fsbl/sdboot/Makefile b/firmware/fsbl/Makefile similarity index 71% rename from fsbl/sdboot/Makefile rename to firmware/fsbl/Makefile index 67f068b..8925523 100644 --- a/fsbl/sdboot/Makefile +++ b/firmware/fsbl/Makefile @@ -1,6 +1,6 @@ # RISCV environment variable must be set ROOT_DIR ?= $(dir $(abspath $(lastword $(MAKEFILE_LIST)))) -BUILD_DIR := $(ROOT_DIR)/build/fsbl +BUILD_DIR := $(ROOT_DIR)/build/firmware/fsbl CC = $(RISCV)/bin/riscv64-unknown-elf-gcc OBJCOPY = $(RISCV)/bin/riscv64-unknown-elf-objcopy @@ -14,12 +14,15 @@ PBUS_CLK ?= 1000000 # default to 1MHz but really should be overridden default: elf bin dump -dtb := $(BUILD_DIR)/rocketchip.dtb -dts := rocketchip.dts +dtb := $(BUILD_DIR)/$(ROCKET_OUTPUT).dtb +dts := $(BUILD_DIR)/$(ROCKET_OUTPUT).dts +dts_org := $(ROOT_DIR)/build/rocket-chip/$(ROCKET_OUTPUT).dts -$(dtb): $(dts) +$(dtb): $(dts_org) mkdir -p $(BUILD_DIR) - dtc -I dts -O dtb -o $@ $< + cp $< $(dts) + sed -i "s/clock-frequency = <0>/clock-frequency = <$(PBUS_CLK)>/g" $(dts) + dtc -I dts -O dtb -o $@ $(dts) elf := $(BUILD_DIR)/sdboot.elf $(elf): head.S kprintf.c sd.c $(dtb) @@ -44,6 +47,13 @@ $(dump): $(elf) .PHONY: dump dump: $(dump) +hex := $(BUILD_DIR)/sdboot.hex +$(hex): $(bin) + od -t x4 -An -w4 -v $< > $@ + +.PHONY: hex +hex: $(hex) + .PHONY: clean clean:: rm -rf $(BUILD_DIR) diff --git a/fsbl/sdboot/common.h b/firmware/fsbl/common.h similarity index 100% rename from fsbl/sdboot/common.h rename to firmware/fsbl/common.h diff --git a/fsbl/sdboot/head.S b/firmware/fsbl/head.S similarity index 100% rename from fsbl/sdboot/head.S rename to firmware/fsbl/head.S diff --git a/fsbl/sdboot/include/bits.h b/firmware/fsbl/include/bits.h similarity index 100% rename from fsbl/sdboot/include/bits.h rename to firmware/fsbl/include/bits.h diff --git a/fsbl/sdboot/include/const.h b/firmware/fsbl/include/const.h similarity index 100% rename from fsbl/sdboot/include/const.h rename to firmware/fsbl/include/const.h diff --git a/fsbl/sdboot/include/devices/clint.h b/firmware/fsbl/include/devices/clint.h similarity index 100% rename from fsbl/sdboot/include/devices/clint.h rename to firmware/fsbl/include/devices/clint.h diff --git a/fsbl/sdboot/include/devices/gpio.h b/firmware/fsbl/include/devices/gpio.h similarity index 100% rename from fsbl/sdboot/include/devices/gpio.h rename to firmware/fsbl/include/devices/gpio.h diff --git a/fsbl/sdboot/include/devices/plic.h b/firmware/fsbl/include/devices/plic.h similarity index 100% rename from fsbl/sdboot/include/devices/plic.h rename to firmware/fsbl/include/devices/plic.h diff --git a/fsbl/sdboot/include/devices/spi.h b/firmware/fsbl/include/devices/spi.h similarity index 100% rename from fsbl/sdboot/include/devices/spi.h rename to firmware/fsbl/include/devices/spi.h diff --git a/fsbl/sdboot/include/devices/uart.h b/firmware/fsbl/include/devices/uart.h similarity index 100% rename from fsbl/sdboot/include/devices/uart.h rename to firmware/fsbl/include/devices/uart.h diff --git a/fsbl/sdboot/include/platform.h b/firmware/fsbl/include/platform.h similarity index 100% rename from fsbl/sdboot/include/platform.h rename to firmware/fsbl/include/platform.h diff --git a/fsbl/sdboot/include/sections.h b/firmware/fsbl/include/sections.h similarity index 100% rename from fsbl/sdboot/include/sections.h rename to firmware/fsbl/include/sections.h diff --git a/fsbl/sdboot/include/smp.h b/firmware/fsbl/include/smp.h similarity index 100% rename from fsbl/sdboot/include/smp.h rename to firmware/fsbl/include/smp.h diff --git a/fsbl/sdboot/kprintf.c b/firmware/fsbl/kprintf.c similarity index 100% rename from fsbl/sdboot/kprintf.c rename to firmware/fsbl/kprintf.c diff --git a/fsbl/sdboot/kprintf.h b/firmware/fsbl/kprintf.h similarity index 100% rename from fsbl/sdboot/kprintf.h rename to firmware/fsbl/kprintf.h diff --git a/fsbl/sdboot/linker/memory.lds b/firmware/fsbl/linker/memory.lds similarity index 57% rename from fsbl/sdboot/linker/memory.lds rename to firmware/fsbl/linker/memory.lds index 997de4d..02b8ed1 100644 --- a/fsbl/sdboot/linker/memory.lds +++ b/firmware/fsbl/linker/memory.lds @@ -1,5 +1,5 @@ MEMORY { - bootrom_mem (rx) : ORIGIN = 0x10000, LENGTH = 0x2000 + bootrom_mem (rx) : ORIGIN = 0x20000, LENGTH = 0x2000 memory_mem (rwx) : ORIGIN = 0x80000000, LENGTH = 0x40000000 } diff --git a/fsbl/sdboot/linker/sdboot.elf.lds b/firmware/fsbl/linker/sdboot.elf.lds similarity index 100% rename from fsbl/sdboot/linker/sdboot.elf.lds rename to firmware/fsbl/linker/sdboot.elf.lds diff --git a/fsbl/sdboot/sd.c b/firmware/fsbl/sd.c similarity index 100% rename from fsbl/sdboot/sd.c rename to firmware/fsbl/sd.c diff --git a/firmware/zsbl/.gitignore b/firmware/zsbl/.gitignore new file mode 100644 index 0000000..d163863 --- /dev/null +++ b/firmware/zsbl/.gitignore @@ -0,0 +1 @@ +build/ \ No newline at end of file diff --git a/firmware/zsbl/Makefile b/firmware/zsbl/Makefile new file mode 100644 index 0000000..6340354 --- /dev/null +++ b/firmware/zsbl/Makefile @@ -0,0 +1,32 @@ +ROOT_DIR ?= $(dir $(abspath $(lastword $(MAKEFILE_LIST)))) +BUILD_DIR := $(ROOT_DIR)/build/firmware/zsbl + +GCC = riscv64-unknown-elf-gcc +OBJCOPY = riscv64-unknown-elf-objcopy + +elf := $(BUILD_DIR)/bootrom.elf +bin := $(BUILD_DIR)/bootrom.bin +img := $(BUILD_DIR)/bootrom.img + +all: $(img) + +elf: $(elf) +$(elf): bootrom.S linker.ld + mkdir -p $(BUILD_DIR) + $(GCC) -Tlinker.ld $< -nostdlib -static -Wl,--no-gc-sections -o $@ + +bin:$(bin) +$(bin): $(elf) + mkdir -p $(BUILD_DIR) + $(OBJCOPY) -O binary $< $@ + +img:$(img) +$(img): $(bin) + mkdir -p $(BUILD_DIR) + dd if=$< of=$@ bs=128 count=1 + + + + + + diff --git a/firmware/zsbl/bootrom.S b/firmware/zsbl/bootrom.S new file mode 100644 index 0000000..b095e8b --- /dev/null +++ b/firmware/zsbl/bootrom.S @@ -0,0 +1,10 @@ +#define ROM_BASE 0x20000 + +.section .text.start, "ax", @progbits +.globl _start +_start: + csrwi 0x7c1, 0 // disable chicken bits + li s0, ROM_BASE + csrr a0, mhartid + li a1, 0 + jr s0 \ No newline at end of file diff --git a/firmware/zsbl/linker.ld b/firmware/zsbl/linker.ld new file mode 100644 index 0000000..f2da4a8 --- /dev/null +++ b/firmware/zsbl/linker.ld @@ -0,0 +1,7 @@ +SECTIONS +{ + START_ADDRESS = 0x10000; /* ... but actually position independent */ + + . = START_ADDRESS; + .text.start : { *(.text.start) } +} diff --git a/fsbl/sdboot/.gitignore b/fsbl/sdboot/.gitignore deleted file mode 100644 index 378eac2..0000000 --- a/fsbl/sdboot/.gitignore +++ /dev/null @@ -1 +0,0 @@ -build diff --git a/fsbl/sdboot/rocketchip.dts b/fsbl/sdboot/rocketchip.dts deleted file mode 100644 index f74b6ab..0000000 --- a/fsbl/sdboot/rocketchip.dts +++ /dev/null @@ -1,112 +0,0 @@ -/dts-v1/; - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "zjv,starship-dev"; - model = "zjv,starship"; - L15: aliases { - serial0 = &L9; - }; - L14: cpus { - #address-cells = <1>; - #size-cells = <0>; - timebase-frequency = <1000000>; - L4: cpu@0 { - clock-frequency = <0>; - compatible = "sifive,rocket0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <16384>; - d-tlb-sets = <1>; - d-tlb-size = <32>; - device_type = "cpu"; - hardware-exec-breakpoint-count = <1>; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <16384>; - i-tlb-sets = <1>; - i-tlb-size = <32>; - mmu-type = "riscv,sv39"; - next-level-cache = <&L11>; - reg = <0x0>; - riscv,isa = "rv64imafdc"; - riscv,pmpgranularity = <4>; - riscv,pmpregions = <8>; - status = "okay"; - timebase-frequency = <1000000>; - tlb-split; - L2: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - }; - L11: memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; - L13: soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "zjv,starship-soc", "simple-bus"; - ranges; - L6: clint@2000000 { - compatible = "riscv,clint0"; - interrupts-extended = <&L2 3 &L2 7>; - reg = <0x2000000 0x10000>; - reg-names = "control"; - }; - L1: error-device@3000 { - compatible = "sifive,error0"; - reg = <0x3000 0x1000>; - }; - L5: interrupt-controller@c000000 { - #interrupt-cells = <1>; - compatible = "riscv,plic0"; - interrupt-controller; - interrupts-extended = <&L2 11 &L2 9>; - reg = <0xc000000 0x4000000>; - reg-names = "control"; - riscv,max-priority = <3>; - riscv,ndev = <2>; - }; - L8: rom@10000 { - compatible = "sifive,rom0"; - reg = <0x10000 0x10000>; - reg-names = "mem"; - }; - L9: serial@64000000 { - clocks = <&L0>; - compatible = "sifive,uart0"; - interrupt-parent = <&L5>; - interrupts = <1>; - reg = <0x64000000 0x1000>; - reg-names = "control"; - }; - L10: spi@64001000 { - #address-cells = <1>; - #size-cells = <0>; - clocks = <&L0>; - compatible = "sifive,spi0"; - interrupt-parent = <&L5>; - interrupts = <2>; - reg = <0x64001000 0x1000>; - reg-names = "control"; - mmc@0 { - compatible = "mmc-spi-slot"; - disable-wp; - reg = <0x0>; - spi-max-frequency = <20000000>; - voltage-ranges = <3300 3300>; - }; - }; - L0: subsystem_pbus_clock { - #clock-cells = <0>; - clock-frequency = <100000000>; - clock-output-names = "subsystem_pbus_clock"; - compatible = "fixed-clock"; - }; - }; -}; diff --git a/src/main/scala/FPGA/Configs.scala b/src/main/scala/FPGA/Configs.scala index fb50787..d0d480e 100644 --- a/src/main/scala/FPGA/Configs.scala +++ b/src/main/scala/FPGA/Configs.scala @@ -30,6 +30,9 @@ class WithPeripherals extends Config((site, here, up) => { UARTParams(address = BigInt(0x64000000L))) case PeripherySPIKey => List( SPIParams(rAddress = BigInt(0x64001000L))) + case MaskROMLocated(x) => List( + MaskROMParams(BigInt(0x20000L), "StarshipROM") + ) }) class WithFrequency(MHz: Double) extends Config((site, here, up) => { @@ -47,7 +50,6 @@ class StarshipFPGAConfig extends Config( new StarshipBaseConfig().alter((site,here,up) => { case DebugModuleKey => None - /* clock-frequency = 50MHz */ case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = Some(site(FPGAFrequencyKey).toInt * 1000000)) /* timebase-frequency = 1 MHz */ @@ -59,13 +61,13 @@ class StarshipFPGAConfig extends Config( x.copy(master = x.master.copy(size = site(VCU707DDRSizeKey)))) case BootROMLocated(x) => up(BootROMLocated(x), site).map { p => - // invoke makefile for sdboot + // invoke makefile for zero stage boot val freqMHz = site(FPGAFrequencyKey).toInt * 1000000 val path = System.getProperty("user.dir") - val make = s"make -C fsbl/sdboot PBUS_CLK=${freqMHz} ROOT_DIR=${path} bin" + val make = s"make -C firmware/zsbl ROOT_DIR=${path} img" println("[Leaving Starship] " + make) require (make.! == 0, "Failed to build bootrom") - p.copy(hang = 0x10000, contentFileName = s"build/fsbl/sdboot.bin") + p.copy(hang = 0x10000, contentFileName = s"build/firmware/zsbl/bootrom.img") } }) ) \ No newline at end of file