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eth_stm32_hal.c
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eth_stm32_hal.c
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/*
* Copyright (c) 2017 Erwin Rol <[email protected]>
* Copyright (c) 2020 Alexander Kozhinov <[email protected]>
* Copyright (c) 2021 Carbon Robotics
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT st_stm32_ethernet
#define LOG_MODULE_NAME eth_stm32_hal
#define LOG_LEVEL CONFIG_ETHERNET_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(LOG_MODULE_NAME);
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/sys/__assert.h>
#include <zephyr/sys/util.h>
#include <zephyr/sys/crc.h>
#include <errno.h>
#include <stdbool.h>
#include <zephyr/net/net_pkt.h>
#include <zephyr/net/net_if.h>
#include <zephyr/net/ethernet.h>
#include <zephyr/net/phy.h>
#include <ethernet/eth_stats.h>
#include <soc.h>
#include <zephyr/sys/printk.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/irq.h>
#include <zephyr/net/lldp.h>
#include <zephyr/drivers/hwinfo.h>
#if defined(CONFIG_NET_DSA)
#include <zephyr/net/dsa.h>
#endif
#if defined(CONFIG_PTP_CLOCK_STM32_HAL)
#include <zephyr/drivers/ptp_clock.h>
#endif /* CONFIG_PTP_CLOCK_STM32_HAL */
#include "eth.h"
#include "eth_stm32_hal_priv.h"
#if DT_INST_PROP(0, zephyr_random_mac_address)
#define ETH_STM32_RANDOM_MAC
#endif
#if defined(CONFIG_ETH_STM32_HAL_USE_DTCM_FOR_DMA_BUFFER) && \
!DT_NODE_HAS_STATUS_OKAY(DT_CHOSEN(zephyr_dtcm))
#error DTCM for DMA buffer is activated but zephyr,dtcm is not present in dts
#endif
#define PHY_ADDR CONFIG_ETH_STM32_HAL_PHY_ADDRESS
#if defined(CONFIG_MDIO)
#define DEVICE_PHY_BY_NAME(n) \
DEVICE_DT_GET(DT_CHILD(DT_INST_CHILD(n, mdio), _CONCAT(ethernet_phy_, PHY_ADDR)))
static const struct device *eth_stm32_phy_dev = DEVICE_PHY_BY_NAME(0);
#endif
#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32H5X)
#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */
#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */
#define IS_ETH_DMATXDESC_OWN(dma_tx_desc) (dma_tx_desc->DESC3 & \
ETH_DMATXNDESCRF_OWN)
/* Only one tx_buffer is sufficient to pass only 1 dma_buffer */
#define ETH_TXBUF_DEF_NB 1U
#else
#define IS_ETH_DMATXDESC_OWN(dma_tx_desc) (dma_tx_desc->Status & \
ETH_DMATXDESC_OWN)
#endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32H5X */
#define ETH_DMA_TX_TIMEOUT_MS 20U /* transmit timeout in milliseconds */
#if defined(CONFIG_ETH_STM32_HAL_USE_DTCM_FOR_DMA_BUFFER) && \
DT_NODE_HAS_STATUS_OKAY(DT_CHOSEN(zephyr_dtcm))
#define __eth_stm32_desc __dtcm_noinit_section
#define __eth_stm32_buf __dtcm_noinit_section
#elif defined(CONFIG_SOC_SERIES_STM32H7X)
#define __eth_stm32_desc __attribute__((section(".eth_stm32_desc")))
#define __eth_stm32_buf __attribute__((section(".eth_stm32_buf")))
#elif defined(CONFIG_NOCACHE_MEMORY)
#define __eth_stm32_desc __nocache __aligned(4)
#define __eth_stm32_buf __nocache __aligned(4)
#else
#define __eth_stm32_desc __aligned(4)
#define __eth_stm32_buf __aligned(4)
#endif
static ETH_DMADescTypeDef dma_rx_desc_tab[ETH_RX_DESC_CNT] __eth_stm32_desc;
static ETH_DMADescTypeDef dma_tx_desc_tab[ETH_TX_DESC_CNT] __eth_stm32_desc;
static uint8_t dma_rx_buffer[ETH_RX_DESC_CNT][ETH_MAX_PACKET_SIZE] __eth_stm32_buf;
static uint8_t dma_tx_buffer[ETH_TX_DESC_CNT][ETH_MAX_PACKET_SIZE] __eth_stm32_buf;
#if defined(CONFIG_ETH_STM32_HAL_API_V2)
BUILD_ASSERT(ETH_MAX_PACKET_SIZE % 4 == 0, "Rx buffer size must be a multiple of 4");
struct eth_stm32_rx_buffer_header {
struct eth_stm32_rx_buffer_header *next;
uint16_t size;
bool used;
};
struct eth_stm32_tx_buffer_header {
ETH_BufferTypeDef tx_buff;
bool used;
};
struct eth_stm32_tx_context {
struct net_pkt *pkt;
uint16_t first_tx_buffer_index;
};
static struct eth_stm32_rx_buffer_header dma_rx_buffer_header[ETH_RX_DESC_CNT];
static struct eth_stm32_tx_buffer_header dma_tx_buffer_header[ETH_TX_DESC_CNT];
void HAL_ETH_RxAllocateCallback(uint8_t **buf)
{
for (size_t i = 0; i < ETH_RX_DESC_CNT; ++i) {
if (!dma_rx_buffer_header[i].used) {
dma_rx_buffer_header[i].next = NULL;
dma_rx_buffer_header[i].size = 0;
dma_rx_buffer_header[i].used = true;
*buf = dma_rx_buffer[i];
return;
}
}
*buf = NULL;
}
/* Pointer to an array of ETH_MAX_PACKET_SIZE uint8_t's */
typedef uint8_t (*RxBufferPtr)[ETH_MAX_PACKET_SIZE];
/* called by HAL_ETH_ReadData() */
void HAL_ETH_RxLinkCallback(void **pStart, void **pEnd, uint8_t *buff, uint16_t Length)
{
/* buff points to the begin on one of the rx buffers,
* so we can compute the index of the given buffer
*/
size_t index = (RxBufferPtr)buff - &dma_rx_buffer[0];
struct eth_stm32_rx_buffer_header *header = &dma_rx_buffer_header[index];
__ASSERT_NO_MSG(index < ETH_RX_DESC_CNT);
header->size = Length;
if (!*pStart) {
/* first packet, set head pointer of linked list */
*pStart = header;
*pEnd = header;
} else {
__ASSERT_NO_MSG(*pEnd != NULL);
/* not the first packet, add to list and adjust tail pointer */
((struct eth_stm32_rx_buffer_header *)*pEnd)->next = header;
*pEnd = header;
}
}
/* Called by HAL_ETH_ReleaseTxPacket */
void HAL_ETH_TxFreeCallback(uint32_t *buff)
{
__ASSERT_NO_MSG(buff != NULL);
/* buff is the user context in tx_config.pData */
struct eth_stm32_tx_context *ctx = (struct eth_stm32_tx_context *)buff;
struct eth_stm32_tx_buffer_header *buffer_header =
&dma_tx_buffer_header[ctx->first_tx_buffer_index];
while (buffer_header != NULL) {
buffer_header->used = false;
if (buffer_header->tx_buff.next != NULL) {
buffer_header = CONTAINER_OF(buffer_header->tx_buff.next,
struct eth_stm32_tx_buffer_header, tx_buff);
} else {
buffer_header = NULL;
}
}
}
/* allocate a tx buffer and mark it as used */
static inline uint16_t allocate_tx_buffer(void)
{
for (;;) {
for (uint16_t index = 0; index < ETH_TX_DESC_CNT; index++) {
if (!dma_tx_buffer_header[index].used) {
dma_tx_buffer_header[index].used = true;
return index;
}
}
k_yield();
}
}
#endif /* CONFIG_ETH_STM32_HAL_API_V2 */
#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32H5X) || \
defined(CONFIG_ETH_STM32_HAL_API_V2)
static ETH_TxPacketConfig tx_config;
#endif
static HAL_StatusTypeDef read_eth_phy_register(ETH_HandleTypeDef *heth,
uint32_t PHYAddr,
uint32_t PHYReg,
uint32_t *RegVal)
{
#if defined(CONFIG_MDIO)
return phy_read(eth_stm32_phy_dev, PHYReg, RegVal);
#elif defined(CONFIG_ETH_STM32_HAL_API_V2)
return HAL_ETH_ReadPHYRegister(heth, PHYAddr, PHYReg, RegVal);
#else
ARG_UNUSED(PHYAddr);
return HAL_ETH_ReadPHYRegister(heth, PHYReg, RegVal);
#endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32H5X || CONFIG_ETH_STM32_HAL_API_V2 */
}
static inline void setup_mac_filter(ETH_HandleTypeDef *heth)
{
__ASSERT_NO_MSG(heth != NULL);
#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32H5X)
ETH_MACFilterConfigTypeDef MACFilterConf;
HAL_ETH_GetMACFilterConfig(heth, &MACFilterConf);
#if defined(CONFIG_ETH_STM32_MULTICAST_FILTER)
MACFilterConf.HashMulticast = ENABLE;
MACFilterConf.PassAllMulticast = DISABLE;
#else
MACFilterConf.HashMulticast = DISABLE;
MACFilterConf.PassAllMulticast = ENABLE;
#endif /* CONFIG_ETH_STM32_MULTICAST_FILTER */
MACFilterConf.HachOrPerfectFilter = DISABLE;
HAL_ETH_SetMACFilterConfig(heth, &MACFilterConf);
k_sleep(K_MSEC(1));
#else
uint32_t tmp = heth->Instance->MACFFR;
/* clear all multicast filter bits, resulting in perfect filtering */
tmp &= ~(ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE |
ETH_MULTICASTFRAMESFILTER_HASHTABLE |
ETH_MULTICASTFRAMESFILTER_PERFECT |
ETH_MULTICASTFRAMESFILTER_NONE);
if (IS_ENABLED(CONFIG_ETH_STM32_MULTICAST_FILTER)) {
/* enable multicast hash receive filter */
tmp |= ETH_MULTICASTFRAMESFILTER_HASHTABLE;
} else {
/* enable receiving all multicast frames */
tmp |= ETH_MULTICASTFRAMESFILTER_NONE;
}
heth->Instance->MACFFR = tmp;
/* Wait until the write operation will be taken into account:
* at least four TX_CLK/RX_CLK clock cycles
*/
tmp = heth->Instance->MACFFR;
k_sleep(K_MSEC(1));
heth->Instance->MACFFR = tmp;
#endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32H5X) */
}
#if defined(CONFIG_PTP_CLOCK_STM32_HAL)
static bool eth_is_ptp_pkt(struct net_if *iface, struct net_pkt *pkt)
{
if (ntohs(NET_ETH_HDR(pkt)->type) != NET_ETH_PTYPE_PTP) {
return false;
}
net_pkt_set_priority(pkt, NET_PRIORITY_CA);
return true;
}
#if defined(CONFIG_ETH_STM32_HAL_API_V2)
void HAL_ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *timestamp)
{
struct eth_stm32_tx_context *ctx = (struct eth_stm32_tx_context *)buff;
ctx->pkt->timestamp.second = timestamp->TimeStampHigh;
ctx->pkt->timestamp.nanosecond = timestamp->TimeStampLow;
net_if_add_tx_timestamp(ctx->pkt);
}
#endif /* CONFIG_ETH_STM32_HAL_API_V2 */
#endif /* CONFIG_PTP_CLOCK_STM32_HAL */
static int eth_tx(const struct device *dev, struct net_pkt *pkt)
{
struct eth_stm32_hal_dev_data *dev_data = dev->data;
ETH_HandleTypeDef *heth;
int res;
size_t total_len;
#if defined(CONFIG_ETH_STM32_HAL_API_V2)
size_t remaining_read;
struct eth_stm32_tx_context ctx = {.pkt = pkt, .first_tx_buffer_index = 0};
struct eth_stm32_tx_buffer_header *buf_header = NULL;
#else
uint8_t *dma_buffer;
__IO ETH_DMADescTypeDef *dma_tx_desc;
#endif /* CONFIG_ETH_STM32_HAL_API_V2 */
HAL_StatusTypeDef hal_ret = HAL_OK;
#if defined(CONFIG_PTP_CLOCK_STM32_HAL)
bool timestamped_frame;
#endif /* CONFIG_PTP_CLOCK_STM32_HAL */
__ASSERT_NO_MSG(pkt != NULL);
__ASSERT_NO_MSG(pkt->frags != NULL);
__ASSERT_NO_MSG(dev != NULL);
__ASSERT_NO_MSG(dev_data != NULL);
heth = &dev_data->heth;
total_len = net_pkt_get_len(pkt);
if (total_len > (ETH_MAX_PACKET_SIZE * ETH_TX_DESC_CNT)) {
LOG_ERR("PKT too big");
return -EIO;
}
k_mutex_lock(&dev_data->tx_mutex, K_FOREVER);
#if defined(CONFIG_ETH_STM32_HAL_API_V2)
ctx.first_tx_buffer_index = allocate_tx_buffer();
buf_header = &dma_tx_buffer_header[ctx.first_tx_buffer_index];
#else /* CONFIG_ETH_STM32_HAL_API_V2 */
#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32H5X)
uint32_t cur_tx_desc_idx;
cur_tx_desc_idx = heth->TxDescList.CurTxDesc;
dma_tx_desc = (ETH_DMADescTypeDef *)heth->TxDescList.TxDesc[cur_tx_desc_idx];
#else
dma_tx_desc = heth->TxDesc;
#endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32H5X */
while (IS_ETH_DMATXDESC_OWN(dma_tx_desc) != (uint32_t)RESET) {
k_yield();
}
#endif /* CONFIG_ETH_STM32_HAL_API_V2 */
#if defined(CONFIG_PTP_CLOCK_STM32_HAL)
timestamped_frame = eth_is_ptp_pkt(net_pkt_iface(pkt), pkt) ||
net_pkt_is_tx_timestamping(pkt);
if (timestamped_frame) {
/* Enable transmit timestamp */
#if defined(CONFIG_ETH_STM32_HAL_API_V2)
HAL_ETH_PTP_InsertTxTimestamp(heth);
#elif defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32H5X)
dma_tx_desc->DESC2 |= ETH_DMATXNDESCRF_TTSE;
#else
dma_tx_desc->Status |= ETH_DMATXDESC_TTSE;
#endif /* CONFIG_ETH_STM32_HAL_API_V2 */
}
#endif /* CONFIG_PTP_CLOCK_STM32_HAL */
#if defined(CONFIG_ETH_STM32_HAL_API_V2)
remaining_read = total_len;
/* fill and allocate buffer until remaining data fits in one buffer */
while (remaining_read > ETH_MAX_PACKET_SIZE) {
if (net_pkt_read(pkt, buf_header->tx_buff.buffer, ETH_MAX_PACKET_SIZE)) {
res = -ENOBUFS;
goto error;
}
const uint16_t next_buffer_id = allocate_tx_buffer();
buf_header->tx_buff.len = ETH_MAX_PACKET_SIZE;
/* append new buffer to the linked list */
buf_header->tx_buff.next = &dma_tx_buffer_header[next_buffer_id].tx_buff;
/* and adjust tail pointer */
buf_header = &dma_tx_buffer_header[next_buffer_id];
remaining_read -= ETH_MAX_PACKET_SIZE;
}
if (net_pkt_read(pkt, buf_header->tx_buff.buffer, remaining_read)) {
res = -ENOBUFS;
goto error;
}
buf_header->tx_buff.len = remaining_read;
buf_header->tx_buff.next = NULL;
#else /* CONFIG_ETH_STM32_HAL_API_V2 */
#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32H5X)
dma_buffer = dma_tx_buffer[cur_tx_desc_idx];
#else
dma_buffer = (uint8_t *)(dma_tx_desc->Buffer1Addr);
#endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32H5X */
if (net_pkt_read(pkt, dma_buffer, total_len)) {
res = -ENOBUFS;
goto error;
}
#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32H5X)
ETH_BufferTypeDef tx_buffer_def;
tx_buffer_def.buffer = dma_buffer;
tx_buffer_def.len = total_len;
tx_buffer_def.next = NULL;
#endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32H5X */
#endif /* CONFIG_ETH_STM32_HAL_API_V2 */
#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32H5X) || \
defined(CONFIG_ETH_STM32_HAL_API_V2)
tx_config.Length = total_len;
#if defined(CONFIG_ETH_STM32_HAL_API_V2)
tx_config.pData = &ctx;
tx_config.TxBuffer = &dma_tx_buffer_header[ctx.first_tx_buffer_index].tx_buff;
#else
tx_config.TxBuffer = &tx_buffer_def;
#endif /* CONFIG_ETH_STM32_HAL_API_V2 */
/* Reset TX complete interrupt semaphore before TX request*/
k_sem_reset(&dev_data->tx_int_sem);
/* tx_buffer is allocated on function stack, we need */
/* to wait for the transfer to complete */
/* So it is not freed before the interrupt happens */
hal_ret = HAL_ETH_Transmit_IT(heth, &tx_config);
if (hal_ret != HAL_OK) {
LOG_ERR("HAL_ETH_Transmit: failed!");
res = -EIO;
goto error;
}
/* Wait for end of TX buffer transmission */
/* If the semaphore timeout breaks, it means */
/* an error occurred or IT was not fired */
if (k_sem_take(&dev_data->tx_int_sem,
K_MSEC(ETH_DMA_TX_TIMEOUT_MS)) != 0) {
LOG_ERR("HAL_ETH_TransmitIT tx_int_sem take timeout");
res = -EIO;
#ifndef CONFIG_ETH_STM32_HAL_API_V2
/* Content of the packet could be the reason for timeout */
LOG_HEXDUMP_ERR(dma_buffer, total_len, "eth packet timeout");
#endif
/* Check for errors */
/* Ethernet device was put in error state */
/* Error state is unrecoverable ? */
if (HAL_ETH_GetState(heth) == HAL_ETH_STATE_ERROR) {
LOG_ERR("%s: ETH in error state: errorcode:%x",
__func__,
HAL_ETH_GetError(heth));
/* TODO recover from error state by restarting eth */
}
/* Check for DMA errors */
if (HAL_ETH_GetDMAError(heth)) {
LOG_ERR("%s: ETH DMA error: dmaerror:%x",
__func__,
HAL_ETH_GetDMAError(heth));
/* DMA fatal bus errors are putting in error state*/
/* TODO recover from this */
}
/* Check for MAC errors */
if (HAL_ETH_GetMACError(heth)) {
LOG_ERR("%s: ETH MAC error: macerror:%x",
__func__,
HAL_ETH_GetMACError(heth));
/* MAC errors are putting in error state*/
/* TODO recover from this */
}
goto error;
}
#else
hal_ret = HAL_ETH_TransmitFrame(heth, total_len);
if (hal_ret != HAL_OK) {
LOG_ERR("HAL_ETH_Transmit: failed!");
res = -EIO;
goto error;
}
/* When Transmit Underflow flag is set, clear it and issue a
* Transmit Poll Demand to resume transmission.
*/
if ((heth->Instance->DMASR & ETH_DMASR_TUS) != (uint32_t)RESET) {
/* Clear TUS ETHERNET DMA flag */
heth->Instance->DMASR = ETH_DMASR_TUS;
/* Resume DMA transmission*/
heth->Instance->DMATPDR = 0;
res = -EIO;
goto error;
}
#endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32H5X || CONFIG_ETH_STM32_HAL_API_V2 */
#if defined(CONFIG_PTP_CLOCK_STM32_HAL) && !defined(CONFIG_ETH_STM32_HAL_API_V2)
if (timestamped_frame) {
/* Retrieve transmission timestamp from last DMA TX descriptor */
#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32H5X)
ETH_TxDescListTypeDef * dma_tx_desc_list;
__IO ETH_DMADescTypeDef *last_dma_tx_desc;
dma_tx_desc_list = &heth->TxDescList;
for (uint32_t i = 0; i < ETH_TX_DESC_CNT; i++) {
const uint32_t last_desc_idx = (cur_tx_desc_idx + i) % ETH_TX_DESC_CNT;
last_dma_tx_desc =
(ETH_DMADescTypeDef *)dma_tx_desc_list->TxDesc[last_desc_idx];
if (last_dma_tx_desc->DESC3 & ETH_DMATXNDESCWBF_LD) {
break;
}
}
while (IS_ETH_DMATXDESC_OWN(last_dma_tx_desc) != (uint32_t)RESET) {
/* Wait for transmission */
k_yield();
}
if ((last_dma_tx_desc->DESC3 & ETH_DMATXNDESCWBF_LD) &&
(last_dma_tx_desc->DESC3 & ETH_DMATXNDESCWBF_TTSS)) {
pkt->timestamp.second = last_dma_tx_desc->DESC1;
pkt->timestamp.nanosecond = last_dma_tx_desc->DESC0;
} else {
/* Invalid value */
pkt->timestamp.second = UINT64_MAX;
pkt->timestamp.nanosecond = UINT32_MAX;
}
#else
__IO ETH_DMADescTypeDef *last_dma_tx_desc = dma_tx_desc;
while (!(last_dma_tx_desc->Status & ETH_DMATXDESC_LS) &&
last_dma_tx_desc->Buffer2NextDescAddr) {
last_dma_tx_desc =
(ETH_DMADescTypeDef *)last_dma_tx_desc->Buffer2NextDescAddr;
}
while (IS_ETH_DMATXDESC_OWN(last_dma_tx_desc) != (uint32_t)RESET) {
/* Wait for transmission */
k_yield();
}
if (last_dma_tx_desc->Status & ETH_DMATXDESC_LS &&
last_dma_tx_desc->Status & ETH_DMATXDESC_TTSS) {
pkt->timestamp.second = last_dma_tx_desc->TimeStampHigh;
pkt->timestamp.nanosecond = last_dma_tx_desc->TimeStampLow;
} else {
/* Invalid value */
pkt->timestamp.second = UINT64_MAX;
pkt->timestamp.nanosecond = UINT32_MAX;
}
#endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32H5X */
net_if_add_tx_timestamp(pkt);
}
#endif /* CONFIG_PTP_CLOCK_STM32_HAL && !CONFIG_ETH_STM32_HAL_API_V2 */
res = 0;
error:
#if defined(CONFIG_ETH_STM32_HAL_API_V2)
/* free package tx buffer */
if (res != 0) {
HAL_ETH_TxFreeCallback((uint32_t *)&ctx);
} else if (HAL_ETH_ReleaseTxPacket(heth) != HAL_OK) {
LOG_ERR("HAL_ETH_ReleaseTxPacket failed");
res = -EIO;
}
#endif
k_mutex_unlock(&dev_data->tx_mutex);
return res;
}
static struct net_if *get_iface(struct eth_stm32_hal_dev_data *ctx)
{
return ctx->iface;
}
static struct net_pkt *eth_rx(const struct device *dev)
{
struct eth_stm32_hal_dev_data *dev_data;
ETH_HandleTypeDef *heth;
struct net_pkt *pkt;
size_t total_len = 0;
#if defined(CONFIG_ETH_STM32_HAL_API_V2)
void *appbuf = NULL;
struct eth_stm32_rx_buffer_header *rx_header;
#else
#if !defined(CONFIG_SOC_SERIES_STM32H7X) && !defined(CONFIG_SOC_SERIES_STM32H5X)
__IO ETH_DMADescTypeDef *dma_rx_desc;
#endif /* !CONFIG_SOC_SERIES_STM32H7X */
uint8_t *dma_buffer;
HAL_StatusTypeDef hal_ret = HAL_OK;
#endif /* CONFIG_ETH_STM32_HAL_API_V2 */
#if defined(CONFIG_PTP_CLOCK_STM32_HAL)
struct net_ptp_time timestamp;
#if defined(CONFIG_ETH_STM32_HAL_API_V2)
ETH_TimeStampTypeDef ts_registers;
#endif /* CONFIG_ETH_STM32_HAL_API_V2 */
/* Default to invalid value. */
timestamp.second = UINT64_MAX;
timestamp.nanosecond = UINT32_MAX;
#endif /* CONFIG_PTP_CLOCK_STM32_HAL */
__ASSERT_NO_MSG(dev != NULL);
dev_data = dev->data;
__ASSERT_NO_MSG(dev_data != NULL);
heth = &dev_data->heth;
#if defined(CONFIG_ETH_STM32_HAL_API_V2)
if (HAL_ETH_ReadData(heth, &appbuf) != HAL_OK) {
/* no frame available */
return NULL;
}
/* computing total length */
for (rx_header = (struct eth_stm32_rx_buffer_header *)appbuf;
rx_header; rx_header = rx_header->next) {
total_len += rx_header->size;
}
#elif defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32H5X)
if (HAL_ETH_IsRxDataAvailable(heth) != true) {
/* no frame available */
return NULL;
}
ETH_BufferTypeDef rx_buffer_def;
uint32_t frame_length = 0;
hal_ret = HAL_ETH_GetRxDataBuffer(heth, &rx_buffer_def);
if (hal_ret != HAL_OK) {
LOG_ERR("HAL_ETH_GetRxDataBuffer: failed with state: %d",
hal_ret);
return NULL;
}
hal_ret = HAL_ETH_GetRxDataLength(heth, &frame_length);
if (hal_ret != HAL_OK) {
LOG_ERR("HAL_ETH_GetRxDataLength: failed with state: %d",
hal_ret);
return NULL;
}
total_len = frame_length;
dma_buffer = rx_buffer_def.buffer;
#else
hal_ret = HAL_ETH_GetReceivedFrame_IT(heth);
if (hal_ret != HAL_OK) {
/* no frame available */
return NULL;
}
total_len = heth->RxFrameInfos.length;
dma_buffer = (uint8_t *)heth->RxFrameInfos.buffer;
#endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32H5X */
#if defined(CONFIG_PTP_CLOCK_STM32_HAL)
#if defined(CONFIG_ETH_STM32_HAL_API_V2)
if (HAL_ETH_PTP_GetRxTimestamp(heth, &ts_registers) == HAL_OK) {
timestamp.second = ts_registers.TimeStampHigh;
timestamp.nanosecond = ts_registers.TimeStampLow;
}
#elif defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32H5X)
ETH_RxDescListTypeDef * dma_rx_desc_list;
dma_rx_desc_list = &heth->RxDescList;
if (dma_rx_desc_list->AppDescNbr) {
__IO ETH_DMADescTypeDef *last_dma_rx_desc;
const uint32_t last_desc_idx =
(dma_rx_desc_list->FirstAppDesc + dma_rx_desc_list->AppDescNbr - 1U)
% ETH_RX_DESC_CNT;
last_dma_rx_desc =
(ETH_DMADescTypeDef *)dma_rx_desc_list->RxDesc[last_desc_idx];
if (dma_rx_desc_list->AppContextDesc &&
last_dma_rx_desc->DESC1 & ETH_DMARXNDESCWBF_TSA) {
/* Retrieve timestamp from context DMA descriptor */
__IO ETH_DMADescTypeDef *context_dma_rx_desc;
const uint32_t context_desc_idx = (last_desc_idx + 1U) % ETH_RX_DESC_CNT;
context_dma_rx_desc =
(ETH_DMADescTypeDef *)dma_rx_desc_list->RxDesc[context_desc_idx];
if (context_dma_rx_desc->DESC1 != UINT32_MAX ||
context_dma_rx_desc->DESC0 != UINT32_MAX) {
timestamp.second = context_dma_rx_desc->DESC1;
timestamp.nanosecond = context_dma_rx_desc->DESC0;
}
}
}
#else
__IO ETH_DMADescTypeDef *last_dma_rx_desc;
last_dma_rx_desc = heth->RxFrameInfos.LSRxDesc;
if (last_dma_rx_desc->TimeStampHigh != UINT32_MAX ||
last_dma_rx_desc->TimeStampLow != UINT32_MAX) {
timestamp.second = last_dma_rx_desc->TimeStampHigh;
timestamp.nanosecond = last_dma_rx_desc->TimeStampLow;
}
#endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32H5X */
#endif /* CONFIG_PTP_CLOCK_STM32_HAL */
pkt = net_pkt_rx_alloc_with_buffer(get_iface(dev_data),
total_len, AF_UNSPEC, 0, K_MSEC(100));
if (!pkt) {
LOG_ERR("Failed to obtain RX buffer");
goto release_desc;
}
#if defined(CONFIG_ETH_STM32_HAL_API_V2)
for (rx_header = (struct eth_stm32_rx_buffer_header *)appbuf;
rx_header; rx_header = rx_header->next) {
const size_t index = rx_header - &dma_rx_buffer_header[0];
__ASSERT_NO_MSG(index < ETH_RX_DESC_CNT);
if (net_pkt_write(pkt, dma_rx_buffer[index], rx_header->size)) {
LOG_ERR("Failed to append RX buffer to context buffer");
net_pkt_unref(pkt);
pkt = NULL;
goto release_desc;
}
}
#else
if (net_pkt_write(pkt, dma_buffer, total_len)) {
LOG_ERR("Failed to append RX buffer to context buffer");
net_pkt_unref(pkt);
pkt = NULL;
goto release_desc;
}
#endif /* CONFIG_ETH_STM32_HAL_API_V2 */
release_desc:
#if defined(CONFIG_ETH_STM32_HAL_API_V2)
for (rx_header = (struct eth_stm32_rx_buffer_header *)appbuf;
rx_header; rx_header = rx_header->next) {
rx_header->used = false;
}
#elif defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32H5X)
hal_ret = HAL_ETH_BuildRxDescriptors(heth);
if (hal_ret != HAL_OK) {
LOG_ERR("HAL_ETH_BuildRxDescriptors: failed: %d", hal_ret);
}
#else
/* Release descriptors to DMA */
/* Point to first descriptor */
dma_rx_desc = heth->RxFrameInfos.FSRxDesc;
/* Set Own bit in Rx descriptors: gives the buffers back to DMA */
for (int i = 0; i < heth->RxFrameInfos.SegCount; i++) {
dma_rx_desc->Status |= ETH_DMARXDESC_OWN;
dma_rx_desc = (ETH_DMADescTypeDef *)
(dma_rx_desc->Buffer2NextDescAddr);
}
/* Clear Segment_Count */
heth->RxFrameInfos.SegCount = 0;
/* When Rx Buffer unavailable flag is set: clear it
* and resume reception.
*/
if ((heth->Instance->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET) {
/* Clear RBUS ETHERNET DMA flag */
heth->Instance->DMASR = ETH_DMASR_RBUS;
/* Resume DMA reception */
heth->Instance->DMARPDR = 0;
}
#endif /* CONFIG_ETH_STM32_HAL_API_V2 */
if (!pkt) {
goto out;
}
#if defined(CONFIG_PTP_CLOCK_STM32_HAL)
pkt->timestamp.second = timestamp.second;
pkt->timestamp.nanosecond = timestamp.nanosecond;
if (timestamp.second != UINT64_MAX) {
net_pkt_set_rx_timestamping(pkt, true);
}
#endif /* CONFIG_PTP_CLOCK_STM32_HAL */
out:
if (!pkt) {
eth_stats_update_errors_rx(get_iface(dev_data));
}
return pkt;
}
static void rx_thread(void *arg1, void *unused1, void *unused2)
{
const struct device *dev;
struct eth_stm32_hal_dev_data *dev_data;
struct net_if *iface;
struct net_pkt *pkt;
int res;
uint32_t status;
HAL_StatusTypeDef hal_ret = HAL_OK;
__ASSERT_NO_MSG(arg1 != NULL);
ARG_UNUSED(unused1);
ARG_UNUSED(unused2);
dev = (const struct device *)arg1;
dev_data = dev->data;
__ASSERT_NO_MSG(dev_data != NULL);
while (1) {
res = k_sem_take(&dev_data->rx_int_sem,
K_MSEC(CONFIG_ETH_STM32_CARRIER_CHECK_RX_IDLE_TIMEOUT_MS));
if (res == 0) {
/* semaphore taken, update link status and receive packets */
if (dev_data->link_up != true) {
dev_data->link_up = true;
net_eth_carrier_on(get_iface(dev_data));
}
while ((pkt = eth_rx(dev)) != NULL) {
iface = net_pkt_iface(pkt);
#if defined(CONFIG_NET_DSA)
iface = dsa_net_recv(iface, &pkt);
#endif
res = net_recv_data(iface, pkt);
if (res < 0) {
eth_stats_update_errors_rx(
net_pkt_iface(pkt));
LOG_ERR("Failed to enqueue frame "
"into RX queue: %d", res);
net_pkt_unref(pkt);
}
}
} else if (res == -EAGAIN) {
/* semaphore timeout period expired, check link status */
hal_ret = read_eth_phy_register(&dev_data->heth,
PHY_ADDR, PHY_BSR, (uint32_t *) &status);
if (hal_ret == HAL_OK) {
if ((status & PHY_LINKED_STATUS) == PHY_LINKED_STATUS) {
if (dev_data->link_up != true) {
dev_data->link_up = true;
net_eth_carrier_on(
get_iface(dev_data));
}
} else {
if (dev_data->link_up != false) {
dev_data->link_up = false;
net_eth_carrier_off(
get_iface(dev_data));
}
}
}
}
}
}
static void eth_isr(const struct device *dev)
{
struct eth_stm32_hal_dev_data *dev_data;
ETH_HandleTypeDef *heth;
__ASSERT_NO_MSG(dev != NULL);
dev_data = dev->data;
__ASSERT_NO_MSG(dev_data != NULL);
heth = &dev_data->heth;
__ASSERT_NO_MSG(heth != NULL);
HAL_ETH_IRQHandler(heth);
}
#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32H5X) || \
defined(CONFIG_ETH_STM32_HAL_API_V2)
void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth_handle)
{
__ASSERT_NO_MSG(heth_handle != NULL);
struct eth_stm32_hal_dev_data *dev_data =
CONTAINER_OF(heth_handle, struct eth_stm32_hal_dev_data, heth);
__ASSERT_NO_MSG(dev_data != NULL);
k_sem_give(&dev_data->tx_int_sem);
}
#endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32H5X || CONFIG_ETH_STM32_HAL_API_V2 */
#if defined(CONFIG_ETH_STM32_HAL_API_V2)
void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
{
/* Do not log errors. If errors are reported due to high traffic,
* logging errors will only increase traffic issues
*/
#if defined(CONFIG_NET_STATISTICS_ETHERNET)
__ASSERT_NO_MSG(heth != NULL);
uint32_t dma_error;
#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32H5X)
uint32_t mac_error;
#endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32H5X */
const uint32_t error_code = HAL_ETH_GetError(heth);
struct eth_stm32_hal_dev_data *dev_data =
CONTAINER_OF(heth, struct eth_stm32_hal_dev_data, heth);
switch (error_code) {
case HAL_ETH_ERROR_DMA:
dma_error = HAL_ETH_GetDMAError(heth);
#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32H5X)
if ((dma_error & ETH_DMA_RX_WATCHDOG_TIMEOUT_FLAG) ||
(dma_error & ETH_DMA_RX_PROCESS_STOPPED_FLAG) ||
(dma_error & ETH_DMA_RX_BUFFER_UNAVAILABLE_FLAG)) {
eth_stats_update_errors_rx(dev_data->iface);
}
if ((dma_error & ETH_DMA_EARLY_TX_IT_FLAG) ||
(dma_error & ETH_DMA_TX_PROCESS_STOPPED_FLAG)) {
eth_stats_update_errors_tx(dev_data->iface);
}
#else
if ((dma_error & ETH_DMASR_RWTS) ||
(dma_error & ETH_DMASR_RPSS) ||
(dma_error & ETH_DMASR_RBUS)) {
eth_stats_update_errors_rx(dev_data->iface);
}
if ((dma_error & ETH_DMASR_ETS) ||
(dma_error & ETH_DMASR_TPSS) ||
(dma_error & ETH_DMASR_TJTS)) {
eth_stats_update_errors_tx(dev_data->iface);
}
#endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32H5X */
break;
#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32H5X)
case HAL_ETH_ERROR_MAC:
mac_error = HAL_ETH_GetMACError(heth);
if (mac_error & ETH_RECEIVE_WATCHDOG_TIMEOUT) {
eth_stats_update_errors_rx(dev_data->iface);
}
if ((mac_error & ETH_EXECESSIVE_COLLISIONS) ||
(mac_error & ETH_LATE_COLLISIONS) ||
(mac_error & ETH_EXECESSIVE_DEFERRAL) ||
(mac_error & ETH_TRANSMIT_JABBR_TIMEOUT) ||
(mac_error & ETH_LOSS_OF_CARRIER) ||
(mac_error & ETH_NO_CARRIER)) {
eth_stats_update_errors_tx(dev_data->iface);
}
break;
#endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32H5X */
}
#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32H5X)
dev_data->stats.error_details.rx_crc_errors = heth->Instance->MMCRCRCEPR;
dev_data->stats.error_details.rx_align_errors = heth->Instance->MMCRAEPR;
#else
dev_data->stats.error_details.rx_crc_errors = heth->Instance->MMCRFCECR;
dev_data->stats.error_details.rx_align_errors = heth->Instance->MMCRFAECR;
#endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32H5X */
#endif /* CONFIG_NET_STATISTICS_ETHERNET */
}
#elif defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32H5X)
/* DMA and MAC errors callback only appear in H7 series */
void HAL_ETH_DMAErrorCallback(ETH_HandleTypeDef *heth_handle)
{
__ASSERT_NO_MSG(heth_handle != NULL);
LOG_ERR("%s errorcode:%x dmaerror:%x",
__func__,
HAL_ETH_GetError(heth_handle),
HAL_ETH_GetDMAError(heth_handle));
/* State of eth handle is ERROR in case of unrecoverable error */
/* unrecoverable (ETH_DMACSR_FBE | ETH_DMACSR_TPS | ETH_DMACSR_RPS) */
if (HAL_ETH_GetState(heth_handle) == HAL_ETH_STATE_ERROR) {
LOG_ERR("%s ethernet in error state", __func__);
/* TODO restart the ETH peripheral to recover */
return;
}
/* Recoverable errors don't put ETH in error state */
/* ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT */