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NEWS
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-*- text -*-
Changes in version 2.1:
-----------------------
* The loader now supports dynamically linked executables.
* Instruction formats for little endian models now changed. See ARM model
for example.
* ACCSIM is functional. See models for examples.
* ARM model is functional.
Changes in version 2.0beta3:
----------------------------
* keyword '#include' added to the language (it works pretty much the same as the one in C)
* ac_group added to the parser and support for it added to acsim and actsim
(see doc/adl_news.txt for further details)
* ac_helper added to the parser and support for it added to acsim and actsim
(see doc/adl_news.txt for further details)
* The parser does not silently ignore name clashes within the following groups:
- storage names, pipeline names and stage names in the form pipename_stagename
- register formats
- instruction formats
- instruction groups
(instruction names are still checked, like they were in previous versions)
* acsim-generated simulators now have coarser context-switching:
- the default now is to call wait() in the execution thread once for each 500
instructions, instead of once per instruction)
- this leads to a huge (around 5~7 times compared to beta2) speedup but may
cause problems in models with multiple processors or processors and TLM IPs
should the processor need the assumption of context switching at each
instruction (for instance, when it relies on instant response from
non-blocking methods). In that case you need the...
- set_instr_batch_size(sz) method: avaliable on acsim-generated simulators.
sz is an integer that determines the number of instructions to execute
before switching context. Set it to 1 if you need beta2-like behavior.
- if you want a standalone simulator (eg. just to run benchmark programs),
acsim now offers a -nw (--no-wait) flag that generates a simulator which
*never* switches context, thus allowing for very fast simulation (around
8 times faster than beta2)
* actsim now allows multiple instantiation of generated simulators
* actsim is using the SystemC scheduler now
* disassembler (objdump) is automatically retargeted by acbingen (no additional changes in the models are necessary)
* added '-s' option to the generated assembler. It turns off case sensitivity for mnemonics
* models, language and tools with GPL license (public release). The version on SVN uses a special license
Changes in version 2.0beta2:
----------------------------
* Preliminary statistics collection support (counts total number of
instructions and syscalls, and for each instruction in the ISA, the number
of times it was executed)
* Preliminary TLM protocol support for bus/device locking/unlocking
* GDB support now done via proc.enable_gdb() (a port number may be passed as
an argument, otherwise it will work on port 5000)
* ac_pc value modification methods on the processor module, means you can
modify ac_pc via proc.set_ac_pc(val) or get the value of ac_pc by calling
proc.get_ac_pc()
* Several bugfixes
* Support for cycle-accurate models (multicycle and single pipeline) is back
via actsim (see doc/actsim.txt for further details)
Changes in version 2.0beta1:
----------------------------
* Binary utilities generation is carried out by acbingen.sh
script (assembler and linker generation)
* Assembler generation is now part of binary utilities
* Linker generation and integration with assembler added
* acsim simulation generation tool now only generates functional simulators
(there will be a separate tool for cycle-accurate, called actsim)
* acsim-generated functional simulators are now up to 3~5 times faster
compared to ArchC 1.6
* self-contained acsim-generated functional simulators: it's possible to
instantiate multiple simulators and integrate them to your system model
written in pure SystemC
* support for SystemC TLM communication: it is possible to declare TLM
initiator ports on your processor, as well as interrupt ports
* preliminary interrupt handling mechanism support