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mc6809.c
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mc6809.c
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/*
Copyright 2015 by Joseph Forgione
This file is part of VCC (Virtual Color Computer).
VCC (Virtual Color Computer) is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
VCC (Virtual Color Computer) is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with VCC (Virtual Color Computer). If not, see <http://www.gnu.org/licenses/>.
*/
#include "windows.h"
#include "stdio.h"
#include "mc6809.h"
#include "mc6809defs.h"
#include "tcc1014mmu.h"
//Global variables for CPU Emulation-----------------------
#define NTEST8(r) r>0x7F;
#define NTEST16(r) r>0x7FFF;
#define OTEST8(c,a,b,r) c ^ (((a^b^r)>>7) &1);
#define OTEST16(c,a,b,r) c ^ (((a^b^r)>>15)&1);
#define ZTEST(r) !r;
typedef union
{
unsigned short Reg;
struct
{
unsigned char lsb,msb;
} B;
} cpuregister;
#define D_REG d.Reg
#define PC_REG pc.Reg
#define X_REG x.Reg
#define Y_REG y.Reg
#define U_REG u.Reg
#define S_REG s.Reg
#define A_REG d.B.msb
#define B_REG d.B.lsb
static cpuregister pc,x,y,u,s,dp,d;
static unsigned int cc[8];
static unsigned char *ureg8[8];
static unsigned char ccbits;
static unsigned short *xfreg16[8];
static int CycleCounter=0;
static unsigned int SyncWaiting=0;
static unsigned int temp32;
static unsigned short temp16;
static unsigned char temp8;
static unsigned char PendingInterupts=0;
static unsigned char IRQWaiter=0;
static unsigned char Source=0,Dest=0;
static unsigned char postbyte=0;
static short unsigned postword=0;
static signed char *spostbyte=(signed char *)&postbyte;
static signed short *spostword=(signed short *)&postword;
static char InInterupt=0;
//END Global variables for CPU Emulation-------------------
//Fuction Prototypes---------------------------------------
_inline unsigned short CalculateEA(unsigned char);
static void setcc (unsigned char);
static unsigned char getcc(void);
static void cpu_firq(void);
static void cpu_irq(void);
static void cpu_nmi(void);
//END Fuction Prototypes-----------------------------------
void MC6809Reset(void)
{
char index;
for(index=0;index<=5;index++) //Set all register to 0 except V
*xfreg16[index] = 0;
for(index=0;index<=7;index++)
*ureg8[index]=0;
for(index=0;index<=7;index++)
cc[index]=0;
dp.Reg=0;
cc[I]=1;
cc[F]=1;
SyncWaiting=0;
pc.Reg=MemRead16(VRESET); //PC gets its reset vector
SetMapType(0);
return;
}
void MC6809Init(void)
{ //Call this first or RESET will core!
// reg pointers for TFR and EXG and LEA ops
xfreg16[0]=&D_REG;
xfreg16[1]=&X_REG;
xfreg16[2]=&Y_REG;
xfreg16[3]=&U_REG;
xfreg16[4]=&S_REG;
xfreg16[5]=&PC_REG;
ureg8[0]=(unsigned char*)&A_REG;
ureg8[1]=(unsigned char*)&B_REG;
ureg8[2]=(unsigned char*)&ccbits;
ureg8[3]=(unsigned char*)&dp.B.msb;
ureg8[4]=(unsigned char*)&dp.B.msb;
ureg8[5]=(unsigned char*)&dp.B.msb;
ureg8[6]=(unsigned char*)&dp.B.msb;
ureg8[7]=(unsigned char*)&dp.B.msb;
cc[I]=1;
cc[F]=1;
return;
}
int MC6809Exec( int CycleFor)
{
static unsigned char opcode=0;
static unsigned char msn,lsn;
CycleCounter=0;
while (CycleCounter<CycleFor) {
if (PendingInterupts)
{
if (PendingInterupts & 4)
cpu_nmi();
if (PendingInterupts & 2)
cpu_firq();
if (PendingInterupts & 1)
{
if (IRQWaiter==0) // This is needed to fix a subtle timming problem
cpu_irq(); // It allows the CPU to see $FF03 bit 7 high before
else // The IRQ is asserted.
IRQWaiter-=1;
}
}
if (SyncWaiting==1)
return(0);
switch (MemRead8(pc.Reg++)){
case NEG_D: //0
temp16=(dp.Reg |MemRead8(pc.Reg++));
postbyte=MemRead8(temp16);
temp8=0-postbyte;
cc[C]=temp8>0;
cc[V]= (postbyte==0x80);
cc[N]= NTEST8(temp8);
cc[Z]= ZTEST(temp8);
MemWrite8(temp8,temp16);
CycleCounter+=6;
break;
case COM_D:
temp16=(dp.Reg |MemRead8(pc.Reg++));
temp8=MemRead8(temp16);
temp8=0xFF-temp8;
cc[Z]= ZTEST(temp8);
cc[N]= NTEST8(temp8);
cc[C]=1;
cc[V] = 0;
MemWrite8(temp8,temp16);
CycleCounter+=6;
break;
case LSR_D: //S2
temp16=(dp.Reg |MemRead8(pc.Reg++));
temp8=MemRead8(temp16);
cc[C]= temp8 & 1;
temp8= temp8 >>1;
cc[Z]= ZTEST(temp8);
cc[N]=0;
MemWrite8(temp8,temp16);
CycleCounter+=6;
break;
case ROR_D: //S2
temp16=(dp.Reg |MemRead8(pc.Reg++));
temp8=MemRead8(temp16);
postbyte= cc[C]<<7;
cc[C]= temp8 & 1;
temp8= (temp8 >> 1)| postbyte;
cc[Z]= ZTEST(temp8);
cc[N]= NTEST8(temp8);
MemWrite8(temp8,temp16);
CycleCounter+=6;
break;
case ASR_D: //7
temp16=(dp.Reg |MemRead8(pc.Reg++));
temp8=MemRead8(temp16);
cc[C]= temp8 & 1;
temp8 = (temp8 & 0x80) | (temp8 >>1);
cc[Z]= ZTEST(temp8);
cc[N]= NTEST8(temp8);
MemWrite8(temp8,temp16);
CycleCounter+=6;
break;
case ASL_D: //8
temp16=(dp.Reg |MemRead8(pc.Reg++));
temp8=MemRead8(temp16);
cc[C]= (temp8 & 0x80) >>7;
cc[V]= cc[C] ^ ((temp8 & 0x40) >> 6);
temp8= temp8 <<1;
cc[N]= NTEST8(temp8);
cc[Z]= ZTEST(temp8);
MemWrite8(temp8,temp16);
CycleCounter+=6;
break;
case ROL_D: //9
temp16=(dp.Reg |MemRead8(pc.Reg++));
temp8=MemRead8(temp16);
postbyte=cc[C];
cc[C]=(temp8 & 0x80)>>7;
cc[V]= cc[C] ^ ((temp8 & 0x40) >>6);
temp8 = (temp8<<1) | postbyte;
cc[Z]= ZTEST(temp8);
cc[N]= NTEST8(temp8);
MemWrite8(temp8,temp16);
CycleCounter+=6;
break;
case DEC_D: //A
temp16=(dp.Reg |MemRead8(pc.Reg++));
temp8=MemRead8(temp16)-1;
cc[Z]= ZTEST(temp8);
cc[N]= NTEST8(temp8);
cc[V]= temp8==0x7F;
MemWrite8(temp8,temp16);
CycleCounter+=6;
break;
case INC_D: //C
temp16=(dp.Reg |MemRead8(pc.Reg++));
temp8=MemRead8(temp16)+1;
cc[Z]= ZTEST(temp8);
cc[V]= temp8==0x80;
cc[N]= NTEST8(temp8);
MemWrite8(temp8,temp16);
CycleCounter+=6;
break;
case TST_D: //D
temp8=MemRead8((dp.Reg |MemRead8(pc.Reg++)));
cc[Z]= ZTEST(temp8);
cc[N]= NTEST8(temp8);
cc[V] = 0;
CycleCounter+=6;
break;
case JMP_D: //E
pc.Reg= ((dp.Reg |MemRead8(pc.Reg)));
CycleCounter+=3;
break;
case CLR_D: //F
MemWrite8(0,(dp.Reg |MemRead8(pc.Reg++)));
cc[Z]=1;
cc[N]=0;
cc[V] = 0;
cc[C]=0;
CycleCounter+=6;
break;
case Page2:
switch (MemRead8(pc.Reg++))
{
case LBEQ_R: //1027
if (cc[Z])
{
*spostword=MemRead16(pc.Reg);
pc.Reg+=*spostword;
CycleCounter+=1;
}
pc.Reg+=2;
CycleCounter+=5;
break;
case LBRN_R: //1021
pc.Reg+=2;
CycleCounter+=5;
break;
case LBHI_R: //1022
if (!(cc[C] | cc[Z]))
{
*spostword=MemRead16(pc.Reg);
pc.Reg+=*spostword;
CycleCounter+=1;
}
pc.Reg+=2;
CycleCounter+=5;
break;
case LBLS_R: //1023
if (cc[C] | cc[Z])
{
*spostword=MemRead16(pc.Reg);
pc.Reg+=*spostword;
CycleCounter+=1;
}
pc.Reg+=2;
CycleCounter+=5;
break;
case LBHS_R: //1024
if (!cc[C])
{
*spostword=MemRead16(pc.Reg);
pc.Reg+=*spostword;
CycleCounter+=1;
}
pc.Reg+=2;
CycleCounter+=6;
break;
case LBCS_R: //1025
if (cc[C])
{
*spostword=MemRead16(pc.Reg);
pc.Reg+=*spostword;
CycleCounter+=1;
}
pc.Reg+=2;
CycleCounter+=5;
break;
case LBNE_R: //1026
if (!cc[Z])
{
*spostword=MemRead16(pc.Reg);
pc.Reg+=*spostword;
CycleCounter+=1;
}
pc.Reg+=2;
CycleCounter+=5;
break;
case LBVC_R: //1028
if ( !cc[V])
{
*spostword=MemRead16(pc.Reg);
pc.Reg+=*spostword;
CycleCounter+=1;
}
pc.Reg+=2;
CycleCounter+=5;
break;
case LBVS_R: //1029
if ( cc[V])
{
*spostword=MemRead16(pc.Reg);
pc.Reg+=*spostword;
CycleCounter+=1;
}
pc.Reg+=2;
CycleCounter+=5;
break;
case LBPL_R: //102A
if (!cc[N])
{
*spostword=MemRead16(pc.Reg);
pc.Reg+=*spostword;
CycleCounter+=1;
}
pc.Reg+=2;
CycleCounter+=5;
break;
case LBMI_R: //102B
if ( cc[N])
{
*spostword=MemRead16(pc.Reg);
pc.Reg+=*spostword;
CycleCounter+=1;
}
pc.Reg+=2;
CycleCounter+=5;
break;
case LBGE_R: //102C
if (! (cc[N] ^ cc[V]))
{
*spostword=MemRead16(pc.Reg);
pc.Reg+=*spostword;
CycleCounter+=1;
}
pc.Reg+=2;
CycleCounter+=5;
break;
case LBLT_R: //102D
if ( cc[V] ^ cc[N])
{
*spostword=MemRead16(pc.Reg);
pc.Reg+=*spostword;
CycleCounter+=1;
}
pc.Reg+=2;
CycleCounter+=5;
break;
case LBGT_R: //102E
if ( !( cc[Z] | (cc[N]^cc[V] ) ))
{
*spostword=MemRead16(pc.Reg);
pc.Reg+=*spostword;
CycleCounter+=1;
}
pc.Reg+=2;
CycleCounter+=5;
break;
case LBLE_R: //102F
if ( cc[Z] | (cc[N]^cc[V]) )
{
*spostword=MemRead16(pc.Reg);
pc.Reg+=*spostword;
CycleCounter+=1;
}
pc.Reg+=2;
CycleCounter+=5;
break;
case SWI2_I: //103F
cc[E]=1;
MemWrite8( pc.B.lsb,--s.Reg);
MemWrite8( pc.B.msb,--s.Reg);
MemWrite8( u.B.lsb,--s.Reg);
MemWrite8( u.B.msb,--s.Reg);
MemWrite8( y.B.lsb,--s.Reg);
MemWrite8( y.B.msb,--s.Reg);
MemWrite8( x.B.lsb,--s.Reg);
MemWrite8( x.B.msb,--s.Reg);
MemWrite8( dp.B.msb,--s.Reg);
MemWrite8(B_REG,--s.Reg);
MemWrite8(A_REG,--s.Reg);
MemWrite8(getcc(),--s.Reg);
pc.Reg=MemRead16(VSWI2);
CycleCounter+=20;
break;
case CMPD_M: //1083
postword=MemRead16(pc.Reg);
temp16 = D_REG-postword;
cc[C]= temp16 > D_REG;
cc[V]= OTEST16(cc[C],postword,temp16,D_REG);//cc[C]^((postword^temp16^D_REG)>>15);
cc[N]= NTEST16(temp16);
cc[Z]= ZTEST(temp16);
pc.Reg+=2;
CycleCounter+=5;
break;
case CMPY_M: //108C
postword=MemRead16(pc.Reg);
temp16 = y.Reg-postword;
cc[C]= temp16 > y.Reg;
cc[V]= OTEST16(cc[C],postword,temp16,y.Reg);//cc[C]^((postword^temp16^y.Reg)>>15);
cc[N]= NTEST16(temp16);
cc[Z]= ZTEST(temp16);
pc.Reg+=2;
CycleCounter+=5;
break;
case LDY_M: //108E
y.Reg= MemRead16(pc.Reg);
cc[Z]= ZTEST(y.Reg);
cc[N]= NTEST16(y.Reg);
cc[V]= 0;
pc.Reg+=2;
CycleCounter+=5;
break;
case CMPD_D: //1093
postword=MemRead16((dp.Reg |MemRead8(pc.Reg++)));
temp16= D_REG - postword ;
cc[C]= temp16 > D_REG;
cc[V]= OTEST16(cc[C],postword,temp16,D_REG); //cc[C]^((postword^temp16^D_REG)>>15);
cc[N]= NTEST16(temp16);
cc[Z]= ZTEST(temp16);
CycleCounter+=7;
break;
case CMPY_D: //109C
postword=MemRead16((dp.Reg |MemRead8(pc.Reg++)));
temp16= y.Reg - postword ;
cc[C]= temp16 > y.Reg;
cc[V]= OTEST16(cc[C],postword,temp16,y.Reg);//cc[C]^((postword^temp16^y.Reg)>>15);
cc[N]= NTEST16(temp16);
cc[Z]= ZTEST(temp16);
CycleCounter+=7;
break;
case LDY_D: //109E
y.Reg=MemRead16((dp.Reg |MemRead8(pc.Reg++)));
cc[Z]= ZTEST(y.Reg);
cc[N]= NTEST16(y.Reg);
cc[V]= 0;
CycleCounter+=6;
break;
case STY_D: //109F
MemWrite16(y.Reg,(dp.Reg |MemRead8(pc.Reg++)));
cc[Z]= ZTEST(y.Reg);
cc[N]= NTEST16(y.Reg);
cc[V]= 0;
CycleCounter+=6;
break;
case CMPD_X: //10A3
postword=MemRead16(CalculateEA(MemRead8(pc.Reg++)));
temp16= D_REG - postword ;
cc[C]= temp16 > D_REG;
cc[V]= OTEST16(cc[C],postword,temp16,D_REG);//cc[C]^((postword^temp16^D_REG)>>15);
cc[N]= NTEST16(temp16);
cc[Z]= ZTEST(temp16);
CycleCounter+=7;
break;
case CMPY_X: //10AC
postword=MemRead16(CalculateEA(MemRead8(pc.Reg++)));
temp16= y.Reg - postword ;
cc[C]= temp16 > y.Reg;
cc[V]= OTEST16(cc[C],postword,temp16,Y_REG);
cc[N]= NTEST16(temp16);
cc[Z]= ZTEST(temp16);
CycleCounter+=7;
break;
case LDY_X: //10AE
y.Reg=MemRead16(CalculateEA(MemRead8(pc.Reg++)));
cc[Z]= ZTEST(y.Reg);
cc[N]= NTEST16(y.Reg);
cc[V]= 0;
CycleCounter+=6;
break;
case STY_X: //10AF
MemWrite16(y.Reg,CalculateEA(MemRead8(pc.Reg++)));
cc[Z]= ZTEST(y.Reg);
cc[N]= NTEST16(y.Reg);
cc[V]= 0;
CycleCounter+=6;
break;
case CMPD_E: //10B3
postword=MemRead16(MemRead16(pc.Reg));
temp16 = D_REG-postword;
cc[C]= temp16 > D_REG;
cc[V]= OTEST16(cc[C],postword,temp16,D_REG);
cc[N]= NTEST16(temp16);
cc[Z]= ZTEST(temp16);
pc.Reg+=2;
CycleCounter+=8;
break;
case CMPY_E: //10BC
postword=MemRead16(MemRead16(pc.Reg));
temp16 = y.Reg-postword;
cc[C]= temp16 > y.Reg;
cc[V]= OTEST16(cc[C],postword,temp16,Y_REG);
cc[N]= NTEST16(temp16);
cc[Z]= ZTEST(temp16);
pc.Reg+=2;
CycleCounter+=8;
break;
case LDY_E: //10BE
y.Reg=MemRead16(MemRead16(pc.Reg));
cc[Z]= ZTEST(y.Reg);
cc[N]= NTEST16(y.Reg);
cc[V]= 0;
pc.Reg+=2;
CycleCounter+=7;
break;
case STY_E: //10BF
MemWrite16(y.Reg,MemRead16(pc.Reg));
cc[Z]= ZTEST(y.Reg);
cc[N]= NTEST16(y.Reg);
cc[V]= 0;
pc.Reg+=2;
CycleCounter+=7;
break;
case LDS_I: //10CE
s.Reg=MemRead16(pc.Reg);
cc[Z]= ZTEST(s.Reg);
cc[N]= NTEST16(s.Reg);
cc[V] = 0;
pc.Reg+=2;
CycleCounter+=4;
break;
case LDS_D: //10DE
s.Reg=MemRead16((dp.Reg |MemRead8(pc.Reg++)));
cc[Z]= ZTEST(s.Reg);
cc[N]= NTEST16(s.Reg);
cc[V] = 0;
CycleCounter+=6;
break;
case STS_D: //10DF
MemWrite16(s.Reg,(dp.Reg |MemRead8(pc.Reg++)));
cc[Z]= ZTEST(s.Reg);
cc[N]= NTEST16(s.Reg);
cc[V]= 0;
CycleCounter+=6;
break;
case LDS_X: //10EE
s.Reg=MemRead16(CalculateEA(MemRead8(pc.Reg++)));
cc[Z]= ZTEST(s.Reg);
cc[N]= NTEST16(s.Reg);
cc[V]= 0;
CycleCounter+=6;
break;
case STS_X: //10EF
MemWrite16(s.Reg,CalculateEA(MemRead8(pc.Reg++)));
cc[Z]= ZTEST(s.Reg);
cc[N]= NTEST16(s.Reg);
cc[V]= 0;
CycleCounter+=6;
break;
case LDS_E: //10FE
s.Reg=MemRead16(MemRead16(pc.Reg));
cc[Z]= ZTEST(s.Reg);
cc[N]= NTEST16(s.Reg);
cc[V]= 0;
pc.Reg+=2;
CycleCounter+=7;
break;
case STS_E: //10FF
MemWrite16(s.Reg,MemRead16(pc.Reg));
cc[Z] = ZTEST(s.Reg);
cc[N]= NTEST16(s.Reg);
cc[V] = 0;
pc.Reg+=2;
CycleCounter+=7;
break;
default:
// MessageBox(0,"Unhandled Op","Ok",0);
break;
} //Page 2 switch END
break;
case Page3:
switch (MemRead8(pc.Reg++))
{
case SWI3_I: //113F
cc[E]=1;
MemWrite8( pc.B.lsb,--s.Reg);
MemWrite8( pc.B.msb,--s.Reg);
MemWrite8( u.B.lsb,--s.Reg);
MemWrite8( u.B.msb,--s.Reg);
MemWrite8( y.B.lsb,--s.Reg);
MemWrite8( y.B.msb,--s.Reg);
MemWrite8( x.B.lsb,--s.Reg);
MemWrite8( x.B.msb,--s.Reg);
MemWrite8( dp.B.msb,--s.Reg);
MemWrite8(B_REG,--s.Reg);
MemWrite8(A_REG,--s.Reg);
MemWrite8(getcc(),--s.Reg);
pc.Reg=MemRead16(VSWI3);
CycleCounter+=20;
break;
case CMPU_M: //1183
postword=MemRead16(pc.Reg);
temp16 = u.Reg-postword;
cc[C]= temp16 > u.Reg;
cc[V]= OTEST16(cc[C],postword,temp16,U_REG);
cc[N]= NTEST16(temp16);
cc[Z]= ZTEST(temp16);
pc.Reg+=2;
CycleCounter+=5;
break;
case CMPS_M: //118C
postword=MemRead16(pc.Reg);
temp16 = s.Reg-postword;
cc[C]= temp16 > s.Reg;
cc[V]= OTEST16(cc[C],postword,temp16,S_REG);
cc[N]= NTEST16(temp16);
cc[Z]= ZTEST(temp16);
pc.Reg+=2;
CycleCounter+=5;
break;
case CMPU_D: //1193
postword=MemRead16((dp.Reg |MemRead8(pc.Reg++)));
temp16= u.Reg - postword ;
cc[C]= temp16 > u.Reg;
cc[V]= OTEST16(cc[C],postword,temp16,U_REG);
cc[N]= NTEST16(temp16);
cc[Z]= ZTEST(temp16);
CycleCounter+=7;
break;
case CMPS_D: //119C
postword=MemRead16((dp.Reg |MemRead8(pc.Reg++)));
temp16= s.Reg - postword ;
cc[C]= temp16 > s.Reg;
cc[V]= OTEST16(cc[C],postword,temp16,S_REG);
cc[N]= NTEST16(temp16);
cc[Z]= ZTEST(temp16);
CycleCounter+=7;
break;
case CMPU_X: //11A3
postword=MemRead16(CalculateEA(MemRead8(pc.Reg++)));
temp16= u.Reg - postword ;
cc[C]= temp16 > u.Reg;
cc[V]= OTEST16(cc[C],postword,temp16,U_REG);
cc[N]= NTEST16(temp16);
cc[Z]= ZTEST(temp16);
CycleCounter+=7;
break;
case CMPS_X: //11AC
postword=MemRead16(CalculateEA(MemRead8(pc.Reg++)));
temp16= s.Reg - postword ;
cc[C]= temp16 > s.Reg;
cc[V]= OTEST16(cc[C],postword,temp16,S_REG);
cc[N]= NTEST16(temp16);
cc[Z]= ZTEST(temp16);
CycleCounter+=7;
break;
case CMPU_E: //11B3
postword=MemRead16(MemRead16(pc.Reg));
temp16 = u.Reg-postword;
cc[C]= temp16 > u.Reg;
cc[V]= OTEST16(cc[C],postword,temp16,U_REG);
cc[N]= NTEST16(temp16);
cc[Z]= ZTEST(temp16);
pc.Reg+=2;
CycleCounter+=8;
break;
case CMPS_E: //11BC
postword=MemRead16(MemRead16(pc.Reg));
temp16 = s.Reg-postword;
cc[C]= temp16 > s.Reg;
cc[V]= OTEST16(cc[C],postword,temp16,S_REG);
cc[N]= NTEST16(temp16);
cc[Z]= ZTEST(temp16);
pc.Reg+=2;
CycleCounter+=8;
break;
default:
// MessageBox(0,"Unhandled Op","Ok",0);
break;
} //Page 3 switch END
break;
case NOP_I: //12
CycleCounter+=2;
break;
case SYNC_I: //13
CycleCounter=CycleFor;
SyncWaiting=1;
break;
case LBRA_R: //16
*spostword=MemRead16(pc.Reg);
pc.Reg+=2;
pc.Reg+=*spostword;
CycleCounter+=5;
break;
case LBSR_R: //17
*spostword=MemRead16(pc.Reg);
pc.Reg+=2;
s.Reg--;
MemWrite8(pc.B.lsb,s.Reg--);
MemWrite8(pc.B.msb,s.Reg);
pc.Reg+=*spostword;
CycleCounter+=9;
break;
case DAA_I: //19
// MessageBox(0,"DAA","Ok",0);
msn=(A_REG & 0xF0) ;
lsn=(A_REG & 0xF);
temp8=0;
if ( cc[H] || (lsn >9) )
temp8 |= 0x06;
if ( (msn>0x80) && (lsn>9))
temp8|=0x60;
if ( (msn>0x90) || cc[C] )
temp8|=0x60;
temp16= A_REG+temp8;
cc[C]|=((temp16 & 0x100)>>8);
A_REG= temp16 & 0xFF;
cc[N]= NTEST8(A_REG);
cc[Z]= ZTEST(A_REG);
CycleCounter+=2;
break;
case ORCC_M: //1A
postbyte=MemRead8(pc.Reg++);
temp8=getcc();
temp8 = (temp8 | postbyte);
setcc(temp8);
CycleCounter+=3;
break;
case ANDCC_M: //1C
postbyte=MemRead8(pc.Reg++);
temp8=getcc();
temp8 = (temp8 & postbyte);
setcc(temp8);
CycleCounter+=3;
break;
case SEX_I: //1D
// A_REG = ((signed char)B_REG < 0) ? 0xff : 0x00;
A_REG= 0-(B_REG>>7);
cc[Z]= ZTEST(D_REG);
cc[N]= NTEST16(D_REG);
CycleCounter+=2;
break;
case EXG_M: //1E
postbyte=MemRead8(pc.Reg++);
ccbits=getcc();
if ( ((postbyte & 0x80)>>4)==(postbyte & 0x08)) //Verify like size registers
{
if (postbyte & 0x08) //8 bit EXG
{
temp8= (*ureg8[((postbyte & 0x70) >> 4)]);
(*ureg8[((postbyte & 0x70) >> 4)]) = (*ureg8[postbyte & 0x07]);
(*ureg8[postbyte & 0x07])=temp8;
}
else // 16 bit EXG
{
temp16=(*xfreg16[((postbyte & 0x70) >> 4)]);
(*xfreg16[((postbyte & 0x70) >> 4)])=(*xfreg16[postbyte & 0x07]);
(*xfreg16[postbyte & 0x07])=temp16;
}
}
setcc(ccbits);
CycleCounter+=8;
break;
case TFR_M: //1F
postbyte=MemRead8(pc.Reg++);
Source= postbyte>>4;
Dest=postbyte & 15;
switch (Dest)
{
case 0:
case 1:
case 2:
case 3:
case 4:
case 5:
case 6:
case 7:
*xfreg16[Dest]=0xFFFF;
if ((Source == 12) | (Source == 13))
{
*xfreg16[Dest] = 0;
}
else if (Source <= 7)
{
//make sure the source is valud
if (xfreg16[Source])
{
*xfreg16[Dest] = *xfreg16[Source];
}
}
break;
case 8:
case 9:
case 10:
case 11:
case 14:
case 15:
ccbits=getcc();
*ureg8[Dest&7]=0xFF;
if ( (Source==12) | (Source==13) )
*ureg8[Dest&7]=0;
else
if (Source>7)
*ureg8[Dest&7]=*ureg8[Source&7];
setcc(ccbits);
break;
}
CycleCounter+=6;
break;
case BRA_R: //20
*spostbyte=MemRead8(pc.Reg++);
pc.Reg+=*spostbyte;
CycleCounter+=3;
break;
case BRN_R: //21
CycleCounter+=3;
pc.Reg++;
break;
case BHI_R: //22
if (!(cc[C] | cc[Z]))
pc.Reg+=(signed char)MemRead8(pc.Reg);
pc.Reg++;
CycleCounter+=3;
break;
case BLS_R: //23
if (cc[C] | cc[Z])
pc.Reg+=(signed char)MemRead8(pc.Reg);
pc.Reg++;
CycleCounter+=3;
break;
case BHS_R: //24
if (!cc[C])
pc.Reg+=(signed char)MemRead8(pc.Reg);
pc.Reg++;
CycleCounter+=3;
break;
case BLO_R: //25
if (cc[C])
pc.Reg+=(signed char)MemRead8(pc.Reg);
pc.Reg++;
CycleCounter+=3;
break;
case BNE_R: //26
if (!cc[Z])
pc.Reg+=(signed char)MemRead8(pc.Reg);
pc.Reg++;
CycleCounter+=3;
break;
case BEQ_R: //27
if (cc[Z])
pc.Reg+=(signed char)MemRead8(pc.Reg);
pc.Reg++;
CycleCounter+=3;
break;
case BVC_R: //28
if (!cc[V])
pc.Reg+=(signed char)MemRead8(pc.Reg);
pc.Reg++;
CycleCounter+=3;
break;
case BVS_R: //29
if ( cc[V])
pc.Reg+=(signed char)MemRead8(pc.Reg);
pc.Reg++;
CycleCounter+=3;
break;
case BPL_R: //2A
if (!cc[N])
pc.Reg+=(signed char)MemRead8(pc.Reg);
pc.Reg++;
CycleCounter+=3;
break;
case BMI_R: //2B
if ( cc[N])
pc.Reg+=(signed char)MemRead8(pc.Reg);
pc.Reg++;
CycleCounter+=3;
break;