Updated Xilinx ISE instructions

XeniumMods · Aug 21, 2020 · d568fdc · d568fdc
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diff --git a/Firmware/README.md b/Firmware/README.md
@@ -5,10 +5,12 @@
  This was a significant effort so I ask that you read and respect the [open source license](https://github.com/Ryzee119/OpenXenium/blob/master/Firmware/LICENSE) that this is released under.
 
  * Download and install [ISE Design Suite 14.7](https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/archive-ise.html).
- * Check this for a Windows 10 fix [https://www.xilinx.com/support/answers/62380.html](https://www.xilinx.com/support/answers/62380.html).
+ * During install select the **ISE WebPACK** edition.
+ * Check this for a Windows 10 fix [https://web.archive.org/web/20190520180616/http://www.xilinx.com/support/answers/62380.html](https://web.archive.org/web/20190520180616/http://www.xilinx.com/support/answers/62380.html). I had to do the `Turning off SmartHeap` fix.
  * And maybe this if you encounter other issues [https://www.xilinx.com/support/answers/68433.html](https://www.xilinx.com/support/answers/68433.html).
- * Open `OpenXenium.xise` with ISE Design Suite then *Process>Implement Top Module* to synthesize the VHDL. 
- * This will generate a JEDEC file for programming. Then go to *Tools>iMPACT...* to program the CPLD using a compatible programming cable. I used a Xilinx Model DLC9LP Programming cable. The JTAG points on the OpenXenium are easily accessible and marked.
+ * Open `OpenXenium.xise` with ISE Design Suite then *Process>Implement Top Module* to synthesize the VHDL. This will generate a JEDEC file for programming.
+ * Go to *Tools>iMPACT...* to program the CPLD using a compatible programming cable. I used a Xilinx Model DLC9LP Programming cable. The JTAG points on the OpenXenium are easily accessible and marked.
+ * If you get an error when opening iMPACT about a missing `.ipf` file, open iMPACT from `Xilinx\14.7\ISE_DS\ISE\bin\nt64\impact.exe` and setup a new project and initialise a chain using the `jed` file, then you can save the .ipf in the project directory.
 
 This is technically compatible with a Genuine Xenium device, however you should only consider overwriting the CPLD if you are 100% certain you *need* to (i.e. the legacy CPLD is fried and you replace it with a new one). Once the original CPLD is erased it cannot ever be recovered and I'm certain this remake is not 100% identical.
  <br>

diff --git a/Hardware/bom.csv b/Hardware/bom.csv
@@ -0,0 +1,11 @@
+Reference,Qty,Description,Part Number,Manufacturer,Digikey
+U1,1,IC CPLD 72MC 10NS 64VQFP,XC9572XL-10VQG64C,Xilinx Inc.,122-1388-ND
+U2,1,16MBIT PARALLEL FLASH MEMORY 48TSOP,AM29LV160MT-100EI (legacy) or S29AL016J70TFI010,Cypress Semiconductor Corp,1274-1013-ND
+LED1,1,LED RGB CLEAR 4SMD. COMMON ANODE,19-237/R6GHBHC-A07/2T,Everlight Electronics Co Ltd,1080-1590-1-ND
+J1,1,JST SM CONN HEADER SMD R/A 10POS 1MM,SM10B-SRSS-TB,JST Sales America Inc.,455-1810-1-ND
+"C1,C2",2,CAP CER 0.1UF 50V 0603,CL10B104KB8NNNC,Capacitor Generic,1276-1000-1-ND
+C4,1,CAP CER 10UF 6.3V 0603,JMK107ABJ106MA-T,Capacitor Generic,587-5869-1-ND
+"R1,R2,R3",3,RES 68 OHM 5% 1/8W 0603,RK73B1JTTD680J,Resistor Generic,2019-RK73B1JTTD680JCT-ND
+R5,1,RES 1K OHM 5% 1/10W 0603,RMCF0603JJ1K00,Resistor Generic,RMCF0603JJ1K00CT-ND
+"Q1,Q2,Q3,Q4",4,MOSFET N-CH 20V 4.1A SOT-23,IRLML6246TRPBF,Infineon Technologies,IRLML6246TRPBFCT-ND
+LPC,1,Female Pin Header,PPTC072LFBN-RC,Female Pin Header Generic 2x7 0.1in,S7075-ND