Files

.github
bus
checks
cores
docs
insns
- generate.py
- insn_add.v
- insn_addi.v
- insn_addiw.v
- insn_addw.v
- insn_and.v
- insn_andi.v
- insn_auipc.v
- insn_beq.v
- insn_bge.v
- insn_bgeu.v
- insn_blt.v
- insn_bltu.v
- insn_bne.v
- insn_c_add.v
- insn_c_addi.v
- insn_c_addi16sp.v
- insn_c_addi4spn.v
- insn_c_addiw.v
- insn_c_addw.v
- insn_c_and.v
- insn_c_andi.v
- insn_c_beqz.v
- insn_c_bnez.v
- insn_c_j.v
- insn_c_jal.v
- insn_c_jalr.v
- insn_c_jr.v
- insn_c_ld.v
- insn_c_ldsp.v
- insn_c_li.v
- insn_c_lui.v
- insn_c_lw.v
- insn_c_lwsp.v
- insn_c_mv.v
- insn_c_or.v
- insn_c_sd.v
- insn_c_sdsp.v
- insn_c_slli.v
- insn_c_srai.v
- insn_c_srli.v
- insn_c_sub.v
- insn_c_subw.v
- insn_c_sw.v
- insn_c_swsp.v
- insn_c_xor.v
- insn_div.v
- insn_divu.v
- insn_divuw.v
- insn_divw.v
- insn_jal.v
- insn_jalr.v
- insn_lb.v
- insn_lbu.v
- insn_ld.v
- insn_lh.v
- insn_lhu.v
- insn_lui.v
- insn_lw.v
- insn_lwu.v
- insn_mul.v
- insn_mulh.v
- insn_mulhsu.v
- insn_mulhu.v
- insn_mulw.v
- insn_or.v
- insn_ori.v
- insn_rem.v
- insn_remu.v
- insn_remuw.v
- insn_remw.v
- insn_sb.v
- insn_sd.v
- insn_sh.v
- insn_sll.v
- insn_slli.v
- insn_slliw.v
- insn_sllw.v
- insn_slt.v
- insn_slti.v
- insn_sltiu.v
- insn_sltu.v
- insn_sra.v
- insn_srai.v
- insn_sraiw.v
- insn_sraw.v
- insn_srl.v
- insn_srli.v
- insn_srliw.v
- insn_srlw.v
- insn_sub.v
- insn_subw.v
- insn_sw.v
- insn_xor.v
- insn_xori.v
- isa_rv32i.txt
- isa_rv32i.v
- isa_rv32ic.txt
- isa_rv32ic.v
- isa_rv32im.txt
- isa_rv32im.v
- isa_rv32imc.txt
- isa_rv32imc.v
- isa_rv64i.txt
- isa_rv64i.v
- isa_rv64ic.txt
- isa_rv64ic.v
- isa_rv64im.txt
- isa_rv64im.v
- isa_rv64imc.txt
- isa_rv64imc.v
monitor
tests
.gitignore
.mailmap
.readthedocs.yaml
COPYING
CodeOfConduct
README.md

insns

Dec 13, 2021

781ad33 · Dec 13, 2021

Name	Name	Last commit message	Last commit date
parent directory ..
generate.py	generate.py	Fix name in copyright headers	Dec 13, 2021
insn_add.v	insn_add.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_addi.v	insn_addi.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_addiw.v	insn_addiw.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_addw.v	insn_addw.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_and.v	insn_and.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_andi.v	insn_andi.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_auipc.v	insn_auipc.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_beq.v	insn_beq.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_bge.v	insn_bge.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_bgeu.v	insn_bgeu.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_blt.v	insn_blt.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_bltu.v	insn_bltu.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_bne.v	insn_bne.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_c_add.v	insn_c_add.v	Add MISA CSR to insn models	Oct 14, 2018
insn_c_addi.v	insn_c_addi.v	Add MISA CSR to insn models	Oct 14, 2018
insn_c_addi16sp.v	insn_c_addi16sp.v	Add MISA CSR to insn models	Oct 14, 2018
insn_c_addi4spn.v	insn_c_addi4spn.v	Add MISA CSR to insn models	Oct 14, 2018
insn_c_addiw.v	insn_c_addiw.v	Add MISA CSR to insn models	Oct 14, 2018
insn_c_addw.v	insn_c_addw.v	Add MISA CSR to insn models	Oct 14, 2018
insn_c_and.v	insn_c_and.v	Add MISA CSR to insn models	Oct 14, 2018
insn_c_andi.v	insn_c_andi.v	Add MISA CSR to insn models	Oct 14, 2018
insn_c_beqz.v	insn_c_beqz.v	Add MISA CSR to insn models	Oct 14, 2018
insn_c_bnez.v	insn_c_bnez.v	Add MISA CSR to insn models	Oct 14, 2018
insn_c_j.v	insn_c_j.v	Add MISA CSR to insn models	Oct 14, 2018
insn_c_jal.v	insn_c_jal.v	Add MISA CSR to insn models	Oct 14, 2018
insn_c_jalr.v	insn_c_jalr.v	Add MISA CSR to insn models	Oct 14, 2018
insn_c_jr.v	insn_c_jr.v	Add MISA CSR to insn models	Oct 14, 2018
insn_c_ld.v	insn_c_ld.v	Add MISA CSR to insn models	Oct 14, 2018
insn_c_ldsp.v	insn_c_ldsp.v	Add MISA CSR to insn models	Oct 14, 2018
insn_c_li.v	insn_c_li.v	Add MISA CSR to insn models	Oct 14, 2018
insn_c_lui.v	insn_c_lui.v	Add MISA CSR to insn models	Oct 14, 2018
insn_c_lw.v	insn_c_lw.v	Add MISA CSR to insn models	Oct 14, 2018
insn_c_lwsp.v	insn_c_lwsp.v	Add MISA CSR to insn models	Oct 14, 2018
insn_c_mv.v	insn_c_mv.v	Add MISA CSR to insn models	Oct 14, 2018
insn_c_or.v	insn_c_or.v	Add MISA CSR to insn models	Oct 14, 2018
insn_c_sd.v	insn_c_sd.v	Add MISA CSR to insn models	Oct 14, 2018
insn_c_sdsp.v	insn_c_sdsp.v	Add MISA CSR to insn models	Oct 14, 2018
insn_c_slli.v	insn_c_slli.v	Add MISA CSR to insn models	Oct 14, 2018
insn_c_srai.v	insn_c_srai.v	Add MISA CSR to insn models	Oct 14, 2018
insn_c_srli.v	insn_c_srli.v	Add MISA CSR to insn models	Oct 14, 2018
insn_c_sub.v	insn_c_sub.v	Add MISA CSR to insn models	Oct 14, 2018
insn_c_subw.v	insn_c_subw.v	Add MISA CSR to insn models	Oct 14, 2018
insn_c_sw.v	insn_c_sw.v	Add MISA CSR to insn models	Oct 14, 2018
insn_c_swsp.v	insn_c_swsp.v	Add MISA CSR to insn models	Oct 14, 2018
insn_c_xor.v	insn_c_xor.v	Add MISA CSR to insn models	Oct 14, 2018
insn_div.v	insn_div.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_divu.v	insn_divu.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_divuw.v	insn_divuw.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_divw.v	insn_divw.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_jal.v	insn_jal.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_jalr.v	insn_jalr.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_lb.v	insn_lb.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_lbu.v	insn_lbu.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_ld.v	insn_ld.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_lh.v	insn_lh.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_lhu.v	insn_lhu.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_lui.v	insn_lui.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_lw.v	insn_lw.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_lwu.v	insn_lwu.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_mul.v	insn_mul.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_mulh.v	insn_mulh.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_mulhsu.v	insn_mulhsu.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_mulhu.v	insn_mulhu.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_mulw.v	insn_mulw.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_or.v	insn_or.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_ori.v	insn_ori.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_rem.v	insn_rem.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_remu.v	insn_remu.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_remuw.v	insn_remuw.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_remw.v	insn_remw.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_sb.v	insn_sb.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_sd.v	insn_sd.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_sh.v	insn_sh.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_sll.v	insn_sll.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_slli.v	insn_slli.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_slliw.v	insn_slliw.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_sllw.v	insn_sllw.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_slt.v	insn_slt.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_slti.v	insn_slti.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_sltiu.v	insn_sltiu.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_sltu.v	insn_sltu.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_sra.v	insn_sra.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_srai.v	insn_srai.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_sraiw.v	insn_sraiw.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_sraw.v	insn_sraw.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_srl.v	insn_srl.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_srli.v	insn_srli.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_srliw.v	insn_srliw.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_srlw.v	insn_srlw.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_sub.v	insn_sub.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_subw.v	insn_subw.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_sw.v	insn_sw.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_xor.v	insn_xor.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
insn_xori.v	insn_xori.v	Silence verific warning "right shift count >= width of value"	Dec 13, 2021
isa_rv32i.txt	isa_rv32i.txt	Add model for c.j and c.jal insns	Feb 25, 2017
isa_rv32i.v	isa_rv32i.v	Add MISA CSR to insn models	Oct 14, 2018
isa_rv32ic.txt	isa_rv32ic.txt	Fix C.ADDI encoding to match spike	May 13, 2017
isa_rv32ic.v	isa_rv32ic.v	Add MISA CSR to insn models	Oct 14, 2018
isa_rv32im.txt	isa_rv32im.txt	Add M-extension instructions and RISCV_FORMAL_ALTOPS proposal	Oct 6, 2017
isa_rv32im.v	isa_rv32im.v	Add MISA CSR to insn models	Oct 14, 2018
isa_rv32imc.txt	isa_rv32imc.txt	Add M-extension instructions and RISCV_FORMAL_ALTOPS proposal	Oct 6, 2017
isa_rv32imc.v	isa_rv32imc.v	Add MISA CSR to insn models	Oct 14, 2018
isa_rv64i.txt	isa_rv64i.txt	Add insn models for addiw, slliw, sraiw, and srliw	May 1, 2018
isa_rv64i.v	isa_rv64i.v	Add MISA CSR to insn models	Oct 14, 2018
isa_rv64ic.txt	isa_rv64ic.txt	Add insn models for c.ld, c.ldsp, c.sd, c.sdsp	May 2, 2018
isa_rv64ic.v	isa_rv64ic.v	Add MISA CSR to insn models	Oct 14, 2018
isa_rv64im.txt	isa_rv64im.txt	Add mulw, divw, divuw, remw, remuw	Jun 1, 2018
isa_rv64im.v	isa_rv64im.v	Add MISA CSR to insn models	Oct 14, 2018
isa_rv64imc.txt	isa_rv64imc.txt	Add mulw, divw, divuw, remw, remuw	Jun 1, 2018
isa_rv64imc.v	isa_rv64imc.v	Add MISA CSR to insn models	Oct 14, 2018

Provide feedback

Saved searches

Use saved searches to filter your results more quickly

Files

insns

insns

Files

insns

Directory actions

More options

Directory actions

More options

Latest commit

History

insns

Folders and files

parent directory