diff --git a/arch/X86/X86ATTInstPrinter.c b/arch/X86/X86ATTInstPrinter.c
index 8fd96ce041..445b7edd48 100644
--- a/arch/X86/X86ATTInstPrinter.c
+++ b/arch/X86/X86ATTInstPrinter.c
@@ -539,14 +539,29 @@ static void printMemReference(MCInst *MI, unsigned Op, SStream *O)
 		int64_t DispVal = MCOperand_getImm(DispSpec);
 		if (MI->csh->detail)
 			MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = DispVal;
-		if (DispVal || (!MCOperand_getReg(IndexReg) && !MCOperand_getReg(BaseReg))) {
-			if (DispVal < 0) {
-				SStream_concat(O, "0x%"PRIx64, arch_masks[MI->csh->mode] & DispVal);
+		if (DispVal) {
+			if (MCOperand_getReg(IndexReg) || MCOperand_getReg(BaseReg)) {
+				if (DispVal < 0) {
+					if (DispVal <  -HEX_THRESHOLD)
+						SStream_concat(O, " -0x%"PRIx64, -DispVal);
+					else
+						SStream_concat(O, " -%"PRIu64, -DispVal);
+				} else {
+					if (DispVal > HEX_THRESHOLD)
+						SStream_concat(O, "0x%"PRIx64, DispVal);
+					else
+						SStream_concat(O, "%"PRIu64, DispVal);
+				}
 			} else {
-				if (DispVal > HEX_THRESHOLD)
-					SStream_concat(O, "0x%"PRIx64, DispVal);
-				else
-					SStream_concat(O, "%"PRIu64, DispVal);
+				// only immediate as address of memory
+				if (DispVal < 0) {
+					SStream_concat(O, "0x%"PRIx64, arch_masks[MI->csh->mode] & DispVal);
+				} else {
+					if (DispVal > HEX_THRESHOLD)
+						SStream_concat(O, "0x%"PRIx64, DispVal);
+					else
+						SStream_concat(O, "%"PRIu64, DispVal);
+				}
 			}
 		}
 	}
diff --git a/arch/X86/X86IntelInstPrinter.c b/arch/X86/X86IntelInstPrinter.c
index db91e74919..d7cb1a3b50 100644
--- a/arch/X86/X86IntelInstPrinter.c
+++ b/arch/X86/X86IntelInstPrinter.c
@@ -617,26 +617,39 @@ static void printMemReference(MCInst *MI, unsigned Op, SStream *O)
 		NeedPlus = true;
 	}
 
-	if (!MCOperand_isImm(DispSpec)) {
-		if (NeedPlus)
-			SStream_concat0(O, " + ");
-	} else {
+	if (MCOperand_isImm(DispSpec)) {
 		int64_t DispVal = MCOperand_getImm(DispSpec);
 		if (MI->csh->detail)
 			MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = DispVal;
-		if (DispVal || (!MCOperand_getReg(IndexReg) && !MCOperand_getReg(BaseReg))) {
+		if (DispVal) {
 			if (NeedPlus) {
-				SStream_concat0(O, " + ");
-			}
-
-			if (DispVal < 0) {
-				SStream_concat(O, "0x%"PRIx64, arch_masks[MI->csh->mode] & DispVal);
+				if (DispVal < 0) {
+					if (DispVal <  -HEX_THRESHOLD)
+						SStream_concat(O, " - 0x%"PRIx64, -DispVal);
+					else
+						SStream_concat(O, " - %"PRIu64, -DispVal);
+				} else {
+					if (DispVal > HEX_THRESHOLD)
+						SStream_concat(O, " + 0x%"PRIx64, DispVal);
+					else
+						SStream_concat(O, " + %"PRIu64, DispVal);
+				}
 			} else {
-				if (DispVal > HEX_THRESHOLD)
-					SStream_concat(O, "0x%"PRIx64, DispVal);
-				else
-					SStream_concat(O, "%"PRIu64, DispVal);
+				// memory reference to an immediate address
+				if (DispVal < 0) {
+					SStream_concat(O, "0x%"PRIx64, arch_masks[MI->csh->mode] & DispVal);
+				} else {
+					if (DispVal > HEX_THRESHOLD)
+						SStream_concat(O, "0x%"PRIx64, DispVal);
+					else
+						SStream_concat(O, "%"PRIu64, DispVal);
+				}
 			}
+
+		} else {
+			// DispVal = 0
+			if (!NeedPlus)	// [0]
+				SStream_concat0(O, "0");
 		}
 	}
 
diff --git a/suite/x86odd.py b/suite/x86odd.py
index 861f21f540..fa19d05022 100755
--- a/suite/x86odd.py
+++ b/suite/x86odd.py
@@ -40,6 +40,7 @@
 CODE32_MEMREF += b"\xa1\x23\x01\x00\x00"
 CODE32_MEMREF += b"\xa1\x00\x00\x00\x00"
 CODE32_MEMREF += b"\xa1\xdd\xfe\xff\xff"
+CODE32_MEMREF += b"\x8b\x04\x91"
 
 
 _python3 = sys.version_info.major == 3