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Updated coding standards for AXI2AXILITE, AXIVDISPLAY and WBP2CLASSIC
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ZipCPU committed Mar 13, 2021
1 parent cdab5b7 commit 1945831
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Showing 4 changed files with 11 additions and 8 deletions.
8 changes: 3 additions & 5 deletions rtl/axi2axilite.v
Original file line number Diff line number Diff line change
Expand Up @@ -156,12 +156,10 @@ module axi2axilite #(

// Local parameters, register, and net declarations
// {{{
// Verilator lint_off UNUSED
localparam [1:0] EXOKAY = 2'b01,
SLVERR = 2'b10;
// localparam [1:0] OKAY = 2'b00,
localparam [1:0] SLVERR = 2'b10;
// localparam [1:0] OKAY = 2'b00,
// EXOKAY = 2'b01,
// DECERR = 2'b10;
// Verilator lint_on UNUSED
localparam AW = C_AXI_ADDR_WIDTH;
localparam DW = C_AXI_DATA_WIDTH;
localparam IW = C_AXI_ID_WIDTH;
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2 changes: 1 addition & 1 deletion rtl/axisgfsm.v
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Expand Up @@ -51,7 +51,7 @@
//
////////////////////////////////////////////////////////////////////////////////
// }}}
// Copyright (C) 2020, Gisselquist Technology, LLC
// Copyright (C) 2020-2021, Gisselquist Technology, LLC
// {{{
// This file is part of the WB2AXIP project.
//
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2 changes: 0 additions & 2 deletions rtl/axivdisplay.v
Original file line number Diff line number Diff line change
Expand Up @@ -252,8 +252,6 @@ module axivdisplay #(

localparam LGMAXBURST = (TMPLGMAXBURST+ADDRLSB > 12)
? (12-ADDRLSB) : TMPLGMAXBURST;

localparam [ADDRLSB-1:0] LSBZEROS = 0;
// }}}

wire i_clk = S_AXI_ACLK;
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7 changes: 7 additions & 0 deletions rtl/wbp2classic.v
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Expand Up @@ -138,6 +138,13 @@ module wbp2classic #(
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
`ifdef FORMAL
////////////////////////////////////////////////////////////////////////
//
//
//
////////////////////////////////////////////////////////////////////////
//
//
localparam F_LGDEPTH = 1;
reg f_past_valid;
reg f_ongoing;
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