diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/.gitignore b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/.gitignore
new file mode 100644
index 00000000000..a12093180d9
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/.gitignore
@@ -0,0 +1 @@
+/HardwareDebug/
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/.settings/fittemp/r_sci_rx.ftl b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/.settings/fittemp/r_sci_rx.ftl
new file mode 100644
index 00000000000..62879ddbbe9
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/.settings/fittemp/r_sci_rx.ftl
@@ -0,0 +1,85 @@
+<#--
+ Copyright(C) 2015 Renesas Electronics Corporation
+ RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
+ This program must be used solely for the purpose for which it was furnished
+ by Renesas Electronics Corporation. No part of this program may be reproduced
+ or disclosed to others, in any form, without the prior written permission of
+ Renesas Electronics Corporation.
+-->
+<#-- = DECLARE FUNCTION INFORMATION HERE =================== -->
+<#--
+ (Step 1) Explanation: These variables are necessary information for the function header.
+ Please fill up or leave blank, but do not delete
+-->
+<#assign Function_Base_Name = "R_SCI_PinSet">
+<#assign Function_Description = "This function initializes pins for r_sci_rx module">
+<#assign Function_Arg = "none">
+<#assign Function_Ret = "none">
+<#assign Version = 1.00>
+
+<#-- = DECLARE FUNCTION CONTENT HERE ======================= -->
+<#--
+ (Step 2) Explanation: Function content.
+ - Macro [initialsection] :
+ Any text that goes into this section will be printed out 1 time per function
+ input [postfix] :Use this variable to add the channel number to the function base name.
+-->
+<#macro initialsection postfix>
+<#assign Function_Name = "${Function_Base_Name}${postfix}">
+<#include "lib/functionheader.ftl">
+void ${Function_Name}()
+{
+ R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_MPC);
+
+
+<#--
+ (Step 3) Explanation: Function content.
+ - Macro [peripheralpincode] : Any text that goes into this section will be printed out 1 time per peripheral
+ - input [pin] : Available info includes:
+ pin.pinName :The name of pin, eg “SSLA0”
+ pin.assignedPinName :The pin assigned to, eg “P32”
+ pin.pinMPC :The port number of assigned pin, eg “P32” has portNume = “3”
+ pin.portNum :The bit number of the assigned pin, eg “P32” has pinBitNum = “2”
+ pin.pinBitNum :The value of MPC
+-->
+<#macro peripheralpincode pin>
+
+
+<#--
+ (Step 4) Explanation: Function content.
+ - Macro [channelpincode] : Any text that goes into this section will be printed out 1 time per channel
+ - input [pin] : Same as above
+-->
+<#macro channelpincode pin>
+
+ /* Set ${pin.pinName} pin */
+ MPC.${pin.assignedPinName}PFS.BYTE = 0x${pin.pinMPC}U;
+ PORT${pin.portNum}.PMR.BIT.B${pin.pinBitNum} = 1U;
+
+
+<#macro channelpincodeextra pin postfix>
+
+
+<#--
+ (Step 5) Explanation: Function content.
+ - Macro [endsection] : Any text that goes into this section will be printed out 1 time last
+-->
+<#macro endsection>
+
+ R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_MPC);
+}
+
+
+<#--
+ (Step 6) Explanation: Header file content
+ - Macro [headerfilesection] : Any text that goes into this section will be printed out 1 time in the header file
+ - input [postfix] :Use this variable to add the channel number to the function base name.
+-->
+<#macro headerfilesection postfix>
+void ${Function_Base_Name}${postfix}();
+
+
+<#macro headerfilesectionExtra postfix>
+
+
+<#-- = END OF FILE ========================================= -->
\ No newline at end of file
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/aws_demos.mtpj b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/aws_demos.mtpj
new file mode 100644
index 00000000000..49e395ee457
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/aws_demos.mtpj
@@ -0,0 +1,11363 @@
+
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+
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+ 4
+ 4290772992
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+ %ProjectName%.mtfl
+ %ProjectName%.mtvl
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+ c0c68e15
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+ c060493e
+ c072808e
+
+
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+ 90536345-15c8-40cb-957c-e59974e4bf78
+
+
+
+
+ C:\Renesas\AmazonFreeRTOS\amazon-freertos-1.2.2\demos\renesas\rx65n-tb-uart-sx-ulpgn\ccrx-csplus
+ C:\Renesas\Renesas Electronics\SmartConfigurator\RX\eclipse\SmartConfigurator.exe
+ 93298d6c-d5d0-4e48-8856-76e602249073
+ aws_demos.scfg
+
+
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/aws_demos.scfg b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/aws_demos.scfg
new file mode 100644
index 00000000000..e74aac9eedc
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/aws_demos.scfg
@@ -0,0 +1,639 @@
+
+
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diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/aws_demos_build_path_check.bat b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/aws_demos_build_path_check.bat
new file mode 100644
index 00000000000..70ff37d5d85
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/aws_demos_build_path_check.bat
@@ -0,0 +1,11 @@
+@echo off
+rem ################################################################################
+rem # This batch file executes some preprocess for build
+rem ################################################################################
+
+if not exist "%~dp0..\..\..\..\lib\third_party\mcu_vendor\renesas\tools\aws_demos_build_path_check_and_make.bat" (
+ echo ERROR: Unable to find "%~dp0..\..\..\..\lib\third_party\mcu_vendor\renesas\tools\aws_demos_build_path_check_and_make.bat"
+ exit 2
+)
+
+"%~dp0..\..\..\..\lib\third_party\mcu_vendor\renesas\tools\aws_demos_build_path_check_and_make.bat" %*
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/aws_demos_link_order_import.mtls b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/aws_demos_link_order_import.mtls
new file mode 100644
index 00000000000..c8ba698240d
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/aws_demos_link_order_import.mtls
@@ -0,0 +1,161 @@
+port_asm.obj
+aws_demo_runner.obj
+aws_dev_mode_key_provisioning.obj
+aws_greengrass_discovery_demo.obj
+aws_hello_world.obj
+aws_logging_task_dynamic_buffers.obj
+aws_ota_update_demo.obj
+aws_shadow_lightbulb_on_off.obj
+aws_subscribe_publish_loop.obj
+aws_tcp_echo_client_separate_tasks.obj
+aws_tcp_echo_client_single_task.obj
+entropy_hardware_poll.obj
+freertos_usr_func.obj
+helper.obj
+main.obj
+serial_term_uart.obj
+sx_ulpgn_driver.obj
+event_groups.obj
+list.obj
+heap_4.obj
+port.obj
+queue.obj
+stream_buffer.obj
+tasks.obj
+timers.obj
+aws_bufferpool_static_thread_safe.obj
+aws_crypto.obj
+aws_greengrass_discovery.obj
+aws_helper_secure_connect.obj
+aws_mqtt_agent.obj
+aws_mqtt_lib.obj
+aws_ota_agent.obj
+aws_ota_cbor.obj
+aws_ota_pal.obj
+aws_pkcs11_mbedtls.obj
+aws_pkcs11_pal.obj
+aws_secure_sockets.obj
+aws_shadow.obj
+aws_shadow_json.obj
+aws_tls.obj
+aws_system_init.obj
+aws_wifi.obj
+jsmn.obj
+aes.obj
+aesni.obj
+arc4.obj
+asn1parse.obj
+asn1write.obj
+base64.obj
+bignum.obj
+blowfish.obj
+camellia.obj
+ccm.obj
+certs.obj
+cipher.obj
+cipher_wrap.obj
+cmac.obj
+ctr_drbg.obj
+debug.obj
+des.obj
+dhm.obj
+ecdh.obj
+ecdsa.obj
+ecjpake.obj
+ecp.obj
+ecp_curves.obj
+entropy.obj
+entropy_poll.obj
+error.obj
+gcm.obj
+havege.obj
+hmac_drbg.obj
+md.obj
+md2.obj
+md4.obj
+md5.obj
+md_wrap.obj
+memory_buffer_alloc.obj
+net_sockets.obj
+oid.obj
+padlock.obj
+pem.obj
+pk.obj
+pk_wrap.obj
+pkcs12.obj
+pkcs5.obj
+pkparse.obj
+pkwrite.obj
+platform.obj
+ripemd160.obj
+rsa.obj
+rsa_internal.obj
+sha1.obj
+sha256.obj
+sha512.obj
+ssl_cache.obj
+ssl_ciphersuites.obj
+ssl_cli.obj
+ssl_cookie.obj
+ssl_srv.obj
+ssl_ticket.obj
+ssl_tls.obj
+threading.obj
+timing.obj
+version.obj
+version_features.obj
+x509.obj
+x509_create.obj
+x509_crl.obj
+x509_crt.obj
+x509_csr.obj
+x509write_crt.obj
+x509write_csr.obj
+xtea.obj
+cborencoder.obj
+cborencoder_close_container_checked.obj
+cborerrorstrings.obj
+cborparser.obj
+cborparser_dup_string.obj
+cborpretty.obj
+dbsct.obj
+hwsetup.obj
+lowlvl.obj
+lowsrc.obj
+resetprg.obj
+sbrk.obj
+vecttbl.obj
+r_bsp_common.obj
+cpu.obj
+locking.obj
+mcu_clocks.obj
+mcu_init.obj
+mcu_interrupts.obj
+mcu_locks.obj
+mcu_mapped_interrupts.obj
+mcu_startup.obj
+r_byteq.obj
+r_codeflash.obj
+r_codeflash_extra.obj
+r_dataflash.obj
+r_flash_type1.obj
+r_flash_utils.obj
+r_flash_type2.obj
+r_flash_type3.obj
+r_flash_type4.obj
+r_flash_fcu.obj
+r_flash_group.obj
+r_flash_rx.obj
+r_riic_rx.obj
+r_riic_rx65n.obj
+r_sci_iic_rx.obj
+r_sci_iic_rx65n.obj
+r_sci_rx.obj
+r_sci_rx65n.obj
+r_sci_rx65n_data.obj
+r_cg_hardware_setup.obj
+r_smc_cgc.obj
+r_smc_cgc_user.obj
+r_smc_interrupt.obj
+Pin.obj
+r_sci_rx_pinset.obj
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/FIT_modified_code/attention!.txt b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/FIT_modified_code/attention!.txt
new file mode 100644
index 00000000000..eba837b820a
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/FIT_modified_code/attention!.txt
@@ -0,0 +1,39 @@
+Please note that the following folders in the project window of IDEs are
+so called 'linked' folders.
+
+--------------------------------------------
+Linked folders in the project window of IDEs
+--------------------------------------------
+
+src/compiler_support
+src/FIT_modified_code/r_bsp
+
+src/FIT_modified_code/r_byteq
+src/FIT_modified_code/r_cmt_rx
+src/FIT_modified_code/r_ether_rx
+src/FIT_modified_code/r_flash_rx
+src/FIT_modified_code/r_sci_rx
+
+----------------------------------------------------------
+Folders on the File System of the WINDOWS Operating System
+----------------------------------------------------------
+
+CC-RX/e2 studio & CC-RX/CS+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/ccrx/compiler_support
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/ccrx/generic_rx65n/r_bsp
+
+GNURX/e2 studio
+~~~~~~~~~~~~~~~
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/gnurx/compiler_support
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/gnurx/generic_rx65n/r_bsp
+
+All
+~~~
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/r_byteq
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/r_cmt_rx
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/r_ether_rx
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/r_flash_rx
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/r_sci_rx
+
+[EOF]
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/compiler_support/attention!.txt b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/compiler_support/attention!.txt
new file mode 100644
index 00000000000..eba837b820a
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/compiler_support/attention!.txt
@@ -0,0 +1,39 @@
+Please note that the following folders in the project window of IDEs are
+so called 'linked' folders.
+
+--------------------------------------------
+Linked folders in the project window of IDEs
+--------------------------------------------
+
+src/compiler_support
+src/FIT_modified_code/r_bsp
+
+src/FIT_modified_code/r_byteq
+src/FIT_modified_code/r_cmt_rx
+src/FIT_modified_code/r_ether_rx
+src/FIT_modified_code/r_flash_rx
+src/FIT_modified_code/r_sci_rx
+
+----------------------------------------------------------
+Folders on the File System of the WINDOWS Operating System
+----------------------------------------------------------
+
+CC-RX/e2 studio & CC-RX/CS+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/ccrx/compiler_support
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/ccrx/generic_rx65n/r_bsp
+
+GNURX/e2 studio
+~~~~~~~~~~~~~~~
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/gnurx/compiler_support
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/gnurx/generic_rx65n/r_bsp
+
+All
+~~~
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/r_byteq
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/r_cmt_rx
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/r_ether_rx
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/r_flash_rx
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/r_sci_rx
+
+[EOF]
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/UNUSED_generated_code/.placeholder b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/UNUSED_generated_code/.placeholder
new file mode 100644
index 00000000000..e69de29bb2d
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/general/r_cg_hardware_setup.c b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/general/r_cg_hardware_setup.c
new file mode 100644
index 00000000000..f167483d7da
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/general/r_cg_hardware_setup.c
@@ -0,0 +1,98 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2016, 2017 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name : r_cg_hardware_setup.c
+* Version : 1.2.0
+* Device(s) : R5F565NEDxFP
+* Description : Initialization file for code generation configurations.
+* Creation Date: 2018-08-29
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Pragma directive
+***********************************************************************************************************************/
+/* Start user code for pragma. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_macrodriver.h"
+#include "r_smc_cgc.h"
+#include "r_smc_interrupt.h"
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#include "r_cg_userdefine.h"
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+/* Start user code for global. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+* Function Name: r_undefined_exception
+* Description : This function is undefined interrupt service routine
+* Arguments : None
+* Return Value : None
+***********************************************************************************************************************/
+
+void r_undefined_exception(void)
+{
+ /* Start user code for r_undefined_exception. Do not edit comment generated here */
+ /* End user code. Do not edit comment generated here */
+}
+
+/***********************************************************************************************************************
+* Function Name: R_Systeminit
+* Description : This function initializes every configuration
+* Arguments : None
+* Return Value : None
+***********************************************************************************************************************/
+
+void R_Systeminit(void)
+{
+ /* Enable writing to registers related to operating modes, LPC, CGC and software reset */
+ SYSTEM.PRCR.WORD = 0xA50BU;
+
+ /* Enable writing to MPC pin function control registers */
+ MPC.PWPR.BIT.B0WI = 0U;
+ MPC.PWPR.BIT.PFSWE = 1U;
+
+ /* Initialize clocks settings */
+ R_CGC_Create();
+
+ /* Set interrupt settings */
+ R_Interrupt_Create();
+
+ /* Register undefined interrupt */
+ R_BSP_InterruptWrite(BSP_INT_SRC_UNDEFINED_INTERRUPT,(bsp_int_cb_t)r_undefined_exception);
+
+ /* Disable writing to MPC pin function control registers */
+ MPC.PWPR.BIT.PFSWE = 0U;
+ MPC.PWPR.BIT.B0WI = 1U;
+
+ /* Enable protection */
+ SYSTEM.PRCR.WORD = 0xA500U;
+}
+
+/* Start user code for adding. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/general/r_cg_macrodriver.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/general/r_cg_macrodriver.h
new file mode 100644
index 00000000000..44eb749a951
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/general/r_cg_macrodriver.h
@@ -0,0 +1,82 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2016, 2017 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name : r_cg_macrodriver.h
+* Version : 1.2.0
+* Device(s) : R5F565NEDxFP
+* Description : Macro header file for code generation.
+* Creation Date: 2018-08-29
+***********************************************************************************************************************/
+
+#ifndef MODULEID_H
+#define MODULEID_H
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "platform.h"
+#include "r_smc_interrupt.h"
+#include
+
+/***********************************************************************************************************************
+Macro definitions (Register bit)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+#ifndef __TYPEDEF__
+
+/* Status list definition */
+#define MD_STATUSBASE (0x00U)
+#define MD_OK (MD_STATUSBASE + 0x00U) /* register setting OK */
+#define MD_SPT (MD_STATUSBASE + 0x01U) /* IIC stop */
+#define MD_NACK (MD_STATUSBASE + 0x02U) /* IIC no ACK */
+#define MD_BUSY1 (MD_STATUSBASE + 0x03U) /* busy 1 */
+#define MD_BUSY2 (MD_STATUSBASE + 0x04U) /* busy 2 */
+
+/* Error list definition */
+#define MD_ERRORBASE (0x80U)
+#define MD_ERROR (MD_ERRORBASE + 0x00U) /* error */
+#define MD_ARGERROR (MD_ERRORBASE + 0x01U) /* error argument input error */
+#define MD_ERROR1 (MD_ERRORBASE + 0x02U) /* error 1 */
+#define MD_ERROR2 (MD_ERRORBASE + 0x03U) /* error 2 */
+#define MD_ERROR3 (MD_ERRORBASE + 0x04U) /* error 3 */
+#define MD_ERROR4 (MD_ERRORBASE + 0x05U) /* error 4 */
+#define MD_ERROR5 (MD_ERRORBASE + 0x06U) /* error 5 */
+
+#endif
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+#ifndef __TYPEDEF__
+ typedef unsigned short MD_STATUS;
+ #define __TYPEDEF__
+#endif
+
+/***********************************************************************************************************************
+Global functions
+***********************************************************************************************************************/
+void R_Systeminit(void);
+/* Start user code for function. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#endif
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/general/r_cg_userdefine.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/general/r_cg_userdefine.h
new file mode 100644
index 00000000000..7be043a1a7e
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/general/r_cg_userdefine.h
@@ -0,0 +1,61 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2016, 2017 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name : r_cg_userdefine.h
+* Version : 1.2.0
+* Device(s) : R5F565NEDxFP
+* Description : User header file for code generation.
+* Creation Date: 2018-08-29
+***********************************************************************************************************************/
+
+#ifndef CG_USER_DEF_H
+#define CG_USER_DEF_H
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Macro definitions (Register bit)
+***********************************************************************************************************************/
+/* Start user code for register. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+/* Start user code for macro define. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+/* Start user code for type define. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Global functions
+***********************************************************************************************************************/
+/* Start user code for function. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#endif
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/general/r_smc_cgc.c b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/general/r_smc_cgc.c
new file mode 100644
index 00000000000..44624e06a58
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/general/r_smc_cgc.c
@@ -0,0 +1,45 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2016, 2017 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name : r_smc_cgc.c
+* Version : 1.1.2
+* Device(s) : R5F565NEDxFP
+* Description : This file implements cgc setting
+* Creation Date: 2018-08-29
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_macrodriver.h"
+#include "r_smc_cgc.h"
+#include "platform.h"
+
+/***********************************************************************************************************************
+* Function Name: R_CGC_Create
+* Description : This function Used to initializes the clock generator
+* Arguments : None
+* Return Value : None
+***********************************************************************************************************************/
+
+void R_CGC_Create(void)
+{
+
+ R_CGC_Create_UserInit();
+}
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/general/r_smc_cgc.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/general/r_smc_cgc.h
new file mode 100644
index 00000000000..791faeaa094
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/general/r_smc_cgc.h
@@ -0,0 +1,217 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2016, 2017 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name : r_smc_cgc.h
+* Version : 1.1.2
+* Device(s) : R5F565NEDxFP
+* Description : This file implements cgc setting.
+* Creation Date: 2018-08-29
+***********************************************************************************************************************/
+
+#ifndef SMC_CGC_H
+#define SMC_CGC_H
+
+/***********************************************************************************************************************
+Macro definitions (Register bit)
+***********************************************************************************************************************/
+/*
+ System Clock Control Register (SCKCR)
+*/
+/* Peripheral Module Clock D (PCLKD) */
+#define _00000000_CGC_PCLKD_DIV_1 (0x00000000UL) /* x1 */
+#define _00000001_CGC_PCLKD_DIV_2 (0x00000001UL) /* x1/2 */
+#define _00000002_CGC_PCLKD_DIV_4 (0x00000002UL) /* x1/4 */
+#define _00000003_CGC_PCLKD_DIV_8 (0x00000003UL) /* x1/8 */
+#define _00000004_CGC_PCLKD_DIV_16 (0x00000004UL) /* x1/16 */
+#define _00000005_CGC_PCLKD_DIV_32 (0x00000005UL) /* x1/32 */
+#define _00000006_CGC_PCLKD_DIV_64 (0x00000006UL) /* x1/64 */
+/* Peripheral Module Clock C (PCLKC) */
+#define _00000000_CGC_PCLKC_DIV_1 (0x00000000UL) /* x1 */
+#define _00000010_CGC_PCLKC_DIV_2 (0x00000010UL) /* x1/2 */
+#define _00000020_CGC_PCLKC_DIV_4 (0x00000020UL) /* x1/4 */
+#define _00000030_CGC_PCLKC_DIV_8 (0x00000030UL) /* x1/8 */
+#define _00000040_CGC_PCLKC_DIV_16 (0x00000040UL) /* x1/16 */
+#define _00000050_CGC_PCLKC_DIV_32 (0x00000050UL) /* x1/32 */
+#define _00000060_CGC_PCLKC_DIV_64 (0x00000060UL) /* x1/64 */
+/* Peripheral Module Clock B (PCLKB) */
+#define _00000000_CGC_PCLKB_DIV_1 (0x00000000UL) /* x1 */
+#define _00000100_CGC_PCLKB_DIV_2 (0x00000100UL) /* x1/2 */
+#define _00000200_CGC_PCLKB_DIV_4 (0x00000200UL) /* x1/4 */
+#define _00000300_CGC_PCLKB_DIV_8 (0x00000300UL) /* x1/8 */
+#define _00000400_CGC_PCLKB_DIV_16 (0x00000400UL) /* x1/16 */
+#define _00000500_CGC_PCLKB_DIV_32 (0x00000500UL) /* x1/32 */
+#define _00000600_CGC_PCLKB_DIV_64 (0x00000600UL) /* x1/64 */
+/* Peripheral Module Clock A (PCLKA) */
+#define _00000000_CGC_PCLKA_DIV_1 (0x00000000UL) /* x1 */
+#define _00001000_CGC_PCLKA_DIV_2 (0x00001000UL) /* x1/2 */
+#define _00002000_CGC_PCLKA_DIV_4 (0x00002000UL) /* x1/4 */
+#define _00003000_CGC_PCLKA_DIV_8 (0x00003000UL) /* x1/8 */
+#define _00004000_CGC_PCLKA_DIV_16 (0x00004000UL) /* x1/16 */
+#define _00005000_CGC_PCLKA_DIV_32 (0x00005000UL) /* x1/32 */
+#define _00006000_CGC_PCLKA_DIV_64 (0x00006000UL) /* x1/64 */
+/* External Bus Clock (BCLK) */
+#define _00000000_CGC_BCLK_DIV_1 (0x00000000UL) /* x1 */
+#define _00010000_CGC_BCLK_DIV_2 (0x00010000UL) /* x1/2 */
+#define _00020000_CGC_BCLK_DIV_4 (0x00020000UL) /* x1/4 */
+#define _00030000_CGC_BCLK_DIV_8 (0x00030000UL) /* x1/8 */
+#define _00040000_CGC_BCLK_DIV_16 (0x00040000UL) /* x1/16 */
+#define _00050000_CGC_BCLK_DIV_32 (0x00050000UL) /* x1/32 */
+#define _00060000_CGC_BCLK_DIV_64 (0x00060000UL) /* x1/64 */
+/* System Clock (ICLK) */
+#define _00000000_CGC_ICLK_DIV_1 (0x00000000UL) /* x1 */
+#define _01000000_CGC_ICLK_DIV_2 (0x01000000UL) /* x1/2 */
+#define _02000000_CGC_ICLK_DIV_4 (0x02000000UL) /* x1/4 */
+#define _03000000_CGC_ICLK_DIV_8 (0x03000000UL) /* x1/8 */
+#define _04000000_CGC_ICLK_DIV_16 (0x04000000UL) /* x1/16 */
+#define _05000000_CGC_ICLK_DIV_32 (0x05000000UL) /* x1/32 */
+#define _06000000_CGC_ICLK_DIV_64 (0x06000000UL) /* x1/64 */
+/* System Clock (FCLK) */
+#define _00000000_CGC_FCLK_DIV_1 (0x00000000UL) /* x1 */
+#define _10000000_CGC_FCLK_DIV_2 (0x10000000UL) /* x1/2 */
+#define _20000000_CGC_FCLK_DIV_4 (0x20000000UL) /* x1/4 */
+#define _30000000_CGC_FCLK_DIV_8 (0x30000000UL) /* x1/8 */
+#define _40000000_CGC_FCLK_DIV_16 (0x40000000UL) /* x1/16 */
+#define _50000000_CGC_FCLK_DIV_32 (0x50000000UL) /* x1/32 */
+#define _60000000_CGC_FCLK_DIV_64 (0x60000000UL) /* x1/64 */
+
+/*
+ System Clock Control Register 2 (SCKCR2)
+*/
+#define _0010_CGC_UCLK_DIV_1 (0x0010U) /* x1/2 */
+#define _0020_CGC_UCLK_DIV_3 (0x0020U) /* x1/3 */
+#define _0030_CGC_UCLK_DIV_4 (0x0030U) /* x1/4 */
+#define _0040_CGC_UCLK_DIV_5 (0x0040U) /* x1/5 */
+#define _0001_SCKCR2_BIT0 (0x0001U) /* RESERVE BIT0 */
+
+/*
+ System Clock Control Register 3 (SCKCR3)
+*/
+#define _0000_CGC_CLOCKSOURCE_LOCO (0x0000U) /* LOCO */
+#define _0100_CGC_CLOCKSOURCE_HOCO (0x0100U) /* HOCO */
+#define _0200_CGC_CLOCKSOURCE_MAINCLK (0x0200U) /* Main clock oscillator */
+#define _0300_CGC_CLOCKSOURCE_SUBCLK (0x0300U) /* Sub-clock oscillator */
+#define _0400_CGC_CLOCKSOURCE_PLL (0x0400U) /* PLL circuit */
+
+/*
+ PLL Control Register (PLLCR)
+*/
+/* PLL Input Frequency Division Ratio Select (PLIDIV[1:0]) */
+#define _0000_CGC_PLL_FREQ_DIV_1 (0x0000U) /* x1 */
+#define _0001_CGC_PLL_FREQ_DIV_2 (0x0001U) /* x1/2 */
+#define _0002_CGC_PLL_FREQ_DIV_3 (0x0002U) /* x1/3 */
+/* PLL Clock Source Select (PLLSRCSEL) */
+#define _0000_CGC_PLL_SOURCE_MAIN (0x0000U) /* Main clock oscillator */
+#define _0010_CGC_PLL_SOURCE_HOCO (0x0010U) /* HOCO */
+/* Frequency Multiplication Factor Select (STC[5:0]) */
+#define _1300_CGC_PLL_FREQ_MUL_10_0 (0x1300U) /* x10.0 */
+#define _1400_CGC_PLL_FREQ_MUL_10_5 (0x1400U) /* x10.5 */
+#define _1500_CGC_PLL_FREQ_MUL_11_0 (0x1500U) /* x11.0 */
+#define _1600_CGC_PLL_FREQ_MUL_11_5 (0x1600U) /* x11.5 */
+#define _1700_CGC_PLL_FREQ_MUL_12_0 (0x1700U) /* x12.0 */
+#define _1800_CGC_PLL_FREQ_MUL_12_5 (0x1800U) /* x12.5 */
+#define _1900_CGC_PLL_FREQ_MUL_13_0 (0x1900U) /* x13.0 */
+#define _1A00_CGC_PLL_FREQ_MUL_13_5 (0x1A00U) /* x13.5 */
+#define _1B00_CGC_PLL_FREQ_MUL_14_0 (0x1B00U) /* x14.0 */
+#define _1C00_CGC_PLL_FREQ_MUL_14_5 (0x1C00U) /* x14.5 */
+#define _1D00_CGC_PLL_FREQ_MUL_15_0 (0x1D00U) /* x15.0 */
+#define _1E00_CGC_PLL_FREQ_MUL_15_5 (0x1E00U) /* x15.5 */
+#define _1F00_CGC_PLL_FREQ_MUL_16_0 (0x1F00U) /* x16.0 */
+#define _2000_CGC_PLL_FREQ_MUL_16_5 (0x2000U) /* x16.5 */
+#define _2100_CGC_PLL_FREQ_MUL_17_0 (0x2100U) /* x17.0 */
+#define _2200_CGC_PLL_FREQ_MUL_17_5 (0x2200U) /* x17.5 */
+#define _2300_CGC_PLL_FREQ_MUL_18_0 (0x2300U) /* x18.0 */
+#define _2400_CGC_PLL_FREQ_MUL_18_5 (0x2400U) /* x18.5 */
+#define _2500_CGC_PLL_FREQ_MUL_19_0 (0x2500U) /* x19.0 */
+#define _2600_CGC_PLL_FREQ_MUL_19_5 (0x2600U) /* x19.5 */
+#define _2700_CGC_PLL_FREQ_MUL_20_0 (0x2700U) /* x20.0 */
+#define _2800_CGC_PLL_FREQ_MUL_20_5 (0x2800U) /* x20.5 */
+#define _2900_CGC_PLL_FREQ_MUL_21_0 (0x2900U) /* x21.0 */
+#define _2A00_CGC_PLL_FREQ_MUL_21_5 (0x2A00U) /* x21.5 */
+#define _2B00_CGC_PLL_FREQ_MUL_22_0 (0x2B00U) /* x22.0 */
+#define _2C00_CGC_PLL_FREQ_MUL_22_5 (0x2C00U) /* x22.5 */
+#define _2D00_CGC_PLL_FREQ_MUL_23_0 (0x2D00U) /* x23.0 */
+#define _2E00_CGC_PLL_FREQ_MUL_23_5 (0x2E00U) /* x23.5 */
+#define _2F00_CGC_PLL_FREQ_MUL_24_0 (0x2F00U) /* x24.0 */
+#define _3000_CGC_PLL_FREQ_MUL_24_5 (0x3000U) /* x24.5 */
+#define _3100_CGC_PLL_FREQ_MUL_25_0 (0x3100U) /* x25.0 */
+#define _3200_CGC_PLL_FREQ_MUL_25_5 (0x3200U) /* x25.5 */
+#define _3300_CGC_PLL_FREQ_MUL_26_0 (0x3300U) /* x26.0 */
+#define _3400_CGC_PLL_FREQ_MUL_26_5 (0x3400U) /* x26.5 */
+#define _3500_CGC_PLL_FREQ_MUL_27_0 (0x3500U) /* x27.0 */
+#define _3600_CGC_PLL_FREQ_MUL_27_5 (0x3600U) /* x27.5 */
+#define _3700_CGC_PLL_FREQ_MUL_28_0 (0x3700U) /* x28.0 */
+#define _3800_CGC_PLL_FREQ_MUL_28_5 (0x3800U) /* x28.5 */
+#define _3900_CGC_PLL_FREQ_MUL_29_0 (0x3900U) /* x29.0 */
+#define _3A00_CGC_PLL_FREQ_MUL_29_5 (0x3A00U) /* x29.5 */
+#define _3B00_CGC_PLL_FREQ_MUL_30_0 (0x3B00U) /* x30.0 */
+
+/*
+ Oscillation Stop Detection Control Register (OSTDCR)
+*/
+/* Oscillation Stop Detection Interrupt Enable (OSTDIE) */
+#define _00_CGC_OSC_STOP_INT_DISABLE (0x00U) /* The oscillation stop detection interrupt is disabled */
+#define _01_CGC_OSC_STOP_INT_ENABLE (0x01U) /* The oscillation stop detection interrupt is enabled */
+/* Oscillation Stop Detection Function Enable (OSTDE) */
+#define _00_CGC_OSC_STOP_DISABLE (0x00U) /* Oscillation stop detection function is disabled */
+#define _80_CGC_OSC_STOP_ENABLE (0x80U) /* Oscillation stop detection function is enabled */
+
+/*
+ High-Speed On-Chip Oscillator Control Register 2 (HOCOCR2)
+*/
+/* HOCO Frequency Setting (HCFRQ[1:0]) */
+#define _00_CGC_HOCO_CLK_16 (0x00U) /* 16 MHz */
+#define _01_CGC_HOCO_CLK_18 (0x01U) /* 18 MHz */
+#define _02_CGC_HOCO_CLK_20 (0x02U) /* 20 MHz */
+
+/*
+ Main Clock Oscillator Forced Oscillation Control Register (MOFCR)
+*/
+/* Main Oscillator Drive Capability 2 Switching (MODRV2[1:0]) */
+#define _00_CGC_MAINOSC_UNDER24M (0x00U) /* 20.1 to 24 MHz */
+#define _10_CGC_MAINOSC_UNDER20M (0x10U) /* 16.1 to 20 MHz */
+#define _20_CGC_MAINOSC_UNDER16M (0x20U) /* 8.1 to 16 MHz */
+#define _30_CGC_MAINOSC_EQUATE8M (0x30U) /* 8 MHz */
+/* Main Clock Oscillator Switch (MOSEL) */
+#define _00_CGC_MAINOSC_RESONATOR (0x00U) /* Resonator */
+#define _40_CGC_MAINOSC_EXTERNAL (0x40U) /* External oscillator input */
+
+/*
+ RTC Control Register 4 (RCR4)
+*/
+/* Count source select */
+#define _00_RTC_SOURCE_SELECT_SUB (0x00U) /* Select sub-clock oscillator */
+#define _01_RTC_SOURCE_SELECT_MAIN_FORCED (0x01U) /* Select main clock oscillator */
+#define _53_CGC_MOSCWTCR_VALUE (0x53U) /* Main Clock Oscillator Wait Time */
+#define _21_CGC_SOSCWTCR_VALUE (0x21U) /* Sub-Clock Oscillator Wait Time */
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Global functions
+***********************************************************************************************************************/
+void R_CGC_Create(void);
+void R_CGC_Create_UserInit();
+#endif
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/general/r_smc_cgc_user.c b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/general/r_smc_cgc_user.c
new file mode 100644
index 00000000000..6074233aed9
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/general/r_smc_cgc_user.c
@@ -0,0 +1,63 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2016, 2017 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name : r_smc_cgc_user.c
+* Version : 1.1.2
+* Device(s) : R5F565NEDxFP
+* Description : None
+* Creation Date: 2018-08-29
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Pragma directive
+***********************************************************************************************************************/
+/* Start user code for pragma. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_macrodriver.h"
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#include "r_cg_userdefine.h"
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+/* Start user code for global. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+* Function Name: R_CGC_Create_UserInit
+* Description : This function adds user code after initializing CGC
+* Arguments : None
+* Return Value : None
+***********************************************************************************************************************/
+
+void R_CGC_Create_UserInit(void)
+{
+ /* Start user code for code init. Do not edit comment generated here */
+ /* End user code. Do not edit comment generated here */
+}
+
+/* Start user code for adding. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/general/r_smc_entry.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/general/r_smc_entry.h
new file mode 100644
index 00000000000..091e32445c4
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/general/r_smc_entry.h
@@ -0,0 +1,54 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2016, 2017 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name : r_smc_entry.h
+* Version : 1.2.0
+* Device(s) : R5F565NEDxFP
+* Description : SMC platform header file.
+* Creation Date: 2018-08-29
+***********************************************************************************************************************/
+
+#ifndef SMC_PLATFORM_H
+#define SMC_PLATFORM_H
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_macrodriver.h"
+
+/***********************************************************************************************************************
+Macro definitions (Register bit)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Global functions
+***********************************************************************************************************************/
+/* Start user code for function. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#endif
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/general/r_smc_interrupt.c b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/general/r_smc_interrupt.c
new file mode 100644
index 00000000000..00fdf5e63b4
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/general/r_smc_interrupt.c
@@ -0,0 +1,44 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2016, 2017 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name : r_smc_interrupt.c
+* Version : 1.1.0
+* Device(s) : R5F565NEDxFP
+* Description : This file implements interrupt setting
+* Creation Date: 2018-08-29
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_smc_interrupt.h"
+#include "platform.h"
+
+/***********************************************************************************************************************
+* Function Name: R_Interrupt_Create
+* Description : This function Used to set the fast interrupt or group interrupt
+* Arguments : None
+* Return Value : None
+***********************************************************************************************************************/
+
+void R_Interrupt_Create(void)
+{
+ /* No fast interrupt and group settings have been configured in the Interrupts tab. */
+}
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/general/r_smc_interrupt.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/general/r_smc_interrupt.h
new file mode 100644
index 00000000000..c4604d3d495
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/general/r_smc_interrupt.h
@@ -0,0 +1,292 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2016, 2017 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name : r_smc_interrupt.h
+* Version : 1.1.0
+* Device(s) : R5F565NEDxFP
+* Description : This file implements interrupt setting.
+* Creation Date: 2018-08-29
+***********************************************************************************************************************/
+
+#ifndef SMC_INTERRUPT_H
+#define SMC_INTERRUPT_H
+
+/***********************************************************************************************************************
+Macro definitions (Register bit)
+***********************************************************************************************************************/
+
+/* Priority level of interrupt source.
+ * These macro definitions are used to set the IPR register directly
+ */
+#define _00_ICU_PRIORITY_LEVEL0 (0x00U) /* Level 0 (disabled) */
+#define _01_ICU_PRIORITY_LEVEL1 (0x01U) /* Level 1 */
+#define _02_ICU_PRIORITY_LEVEL2 (0x02U) /* Level 2 */
+#define _03_ICU_PRIORITY_LEVEL3 (0x03U) /* Level 3 */
+#define _04_ICU_PRIORITY_LEVEL4 (0x04U) /* Level 4 */
+#define _05_ICU_PRIORITY_LEVEL5 (0x05U) /* Level 5 */
+#define _06_ICU_PRIORITY_LEVEL6 (0x06U) /* Level 6 */
+#define _07_ICU_PRIORITY_LEVEL7 (0x07U) /* Level 7 */
+#define _08_ICU_PRIORITY_LEVEL8 (0x08U) /* Level 8 */
+#define _09_ICU_PRIORITY_LEVEL9 (0x09U) /* Level 9 */
+#define _0A_ICU_PRIORITY_LEVEL10 (0x0AU) /* Level 10 */
+#define _0B_ICU_PRIORITY_LEVEL11 (0x0BU) /* Level 11 */
+#define _0C_ICU_PRIORITY_LEVEL12 (0x0CU) /* Level 12 */
+#define _0D_ICU_PRIORITY_LEVEL13 (0x0DU) /* Level 13 */
+#define _0E_ICU_PRIORITY_LEVEL14 (0x0EU) /* Level 14 */
+#define _0F_ICU_PRIORITY_LEVEL15 (0x0FU) /* Level 15 */
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+#define FAST_INTERRUPT_VECTOR (0)
+
+/* The macro definitions below list the full set of priority levels as selected in the Interrupts tab
+ * Please do not modify this file manually
+ */
+#define ICU_BSC_BUSERR_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_RAM_RAMERR_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_FCU_FIFERR_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_FCU_FRDYI_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_SWINT2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_SWINT_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CMT0_CMI0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CMT1_CMI1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CMTW0_CMWI0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CMTW1_CMWI1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_USB0_D0FIFO0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_USB0_D1FIFO0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_RSPI0_SPRI0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_RSPI0_SPTI0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_RSPI1_SPRI1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_RSPI1_SPTI1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_QSPI_SPRI_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_QSPI_SPTI_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SDHI_SBFAI_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MMCIF_MBFAI_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_RIIC1_RXI1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_RIIC1_TXI1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_RIIC0_RXI0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_RIIC0_TXI0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_RIIC2_RXI2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_RIIC2_TXI2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI0_RXI0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI0_TXI0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI1_RXI1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI1_TXI1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI2_RXI2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI2_TXI2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_IRQ0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_IRQ1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_IRQ2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_IRQ3_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_IRQ4_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_IRQ5_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_IRQ6_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_IRQ7_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_IRQ8_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_IRQ9_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_IRQ10_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_IRQ11_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_IRQ12_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_IRQ13_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_IRQ14_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_IRQ15_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI3_RXI3_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI3_TXI3_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI4_RXI4_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI4_TXI4_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI5_RXI5_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI5_TXI5_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI6_RXI6_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI6_TXI6_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_LVD1_LVD1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_LVD2_LVD2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_USB0_USBR0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_RTC_ALM_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_RTC_PRD_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_IWDT_IWUNI_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_WDT_WUNI_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_PDC_PCDFI_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI7_RXI7_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI7_TXI7_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI8_RXI8_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI8_TXI8_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI9_RXI9_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI9_TXI9_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI10_RXI10_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI10_TXI10_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_GROUPBE0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_GROUPBL2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_RSPI2_SPRI2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_RSPI2_SPTI2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_GROUPBL0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_GROUPBL1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_GROUPAL0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_GROUPAL1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI11_RXI11_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI11_TXI11_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI12_RXI12_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI12_TXI12_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_DMAC_DMAC0I_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_DMAC_DMAC1I_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_DMAC_DMAC2I_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_DMAC_DMAC3I_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_DMAC_DMAC74I_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_OST_OSTDI_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_EXDMAC_EXDMAC0I_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_EXDMAC_EXDMAC1I_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CMT2_CMI2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CMT3_CMI3_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU0_TGI0A_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU0_TGI0B_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU0_TGI0C_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU0_TGI0D_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU0_TCI0V_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU1_TGI1B_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU1_TCI1V_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU1_TCI1U_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU2_TGI2A_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU2_TGI2B_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU2_TCI2V_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU2_TCI2U_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU3_TGI3A_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU3_TGI3B_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU1_TGI1A_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU3_TGI3C_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TMR0_CMIA0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TMR0_CMIB0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TMR0_OVI0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TMR1_CMIA1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TMR1_CMIB1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TMR1_OVI1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TMR2_CMIA2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TMR2_CMIB2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TMR2_OVI2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TMR3_CMIA3_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TMR3_CMIB3_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TMR3_OVI3_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU3_TGI3D_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU3_TCI3V_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU4_TGI4A_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU4_TGI4B_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU4_TCI4V_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU4_TCI4U_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU5_TGI5A_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU5_TGI5B_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU5_TCI5V_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU5_TCI5U_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CMTW0_IC0I0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CMTW0_IC1I0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CMTW0_OC0I0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CMTW0_OC1I0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CMTW1_IC0I1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CMTW1_IC1I1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CMTW1_OC0I1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CMTW1_OC1I1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_RTC_CUP_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CAN0_RXF0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CAN0_TXF0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CAN0_RXM0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CAN0_TXM0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CAN1_RXF1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CAN1_TXF1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CAN1_RXM1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CAN1_TXM1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_USB0_USBI0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_S12AD_S12ADI_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_S12AD_S12GBADI_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_S12AD_S12GCADI_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_S12AD1_S12ADI1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_S12AD1_S12GBADI1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_S12AD1_S12GCADI1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_PERIB_INTB192_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ELC_ELSR18I_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ELC_ELSR19I_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TSIP_PROC_BUSY_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TSIP_ROMOK_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TSIP_LONG_PLG_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TSIP_TEST_BUSY_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TSIP_WRRDY0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TSIP_WRRDY1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TSIP_WRRDY4_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TSIP_RDRDY0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TSIP_RDRDY1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TSIP_INTEGRATE_WRRDY_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TSIP_INTEGRATE_RDRDY_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_PERIB_INTB206_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_PERIB_INTB207_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU1_TGIA1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU0_TGIA0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU0_TGIB0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU0_TGIC0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU0_TGID0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU0_TCIV0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU0_TGIE0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU0_TGIF0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU1_TGIB1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU1_TCIV1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU1_TCIU1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU2_TGIA2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU2_TGIB2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU2_TCIV2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU2_TCIU2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU3_TGIA3_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU3_TGIB3_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU3_TGIC3_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU3_TGID3_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU3_TCIV3_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU4_TGIA4_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU4_TGIB4_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU4_TGIC4_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU4_TGID4_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU4_TCIV4_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU5_TGIU5_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU5_TGIV5_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU5_TGIW5_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU6_TGIA6_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU6_TGIB6_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU6_TGIC6_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU6_TGID6_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU6_TCIV6_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU7_TGIA7_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU7_TGIB7_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU7_TGIC7_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU7_TGID7_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU7_TCIV7_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU8_TGIA8_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU8_TGIB8_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU8_TGIC8_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU8_TGID8_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU8_TCIV8_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_PERIA_INTA251_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_PERIA_INTA252_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_PERIA_INTA253_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_PERIA_INTA254_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_PERIA_INTA255_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Global functions
+***********************************************************************************************************************/
+void R_Interrupt_Create(void);
+#endif
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/r_config/r_bsp_config.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/r_config/r_bsp_config.h
new file mode 100644
index 00000000000..3df1e11064f
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/r_config/r_bsp_config.h
@@ -0,0 +1,595 @@
+/* Generated configuration header file - do not edit */
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2017 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : r_bsp_config_reference.h
+* Device(s) : RX65N
+* Description : The file r_bsp_config.h is used to configure your BSP. r_bsp_config.h should be included
+* somewhere in your package so that the r_bsp code has access to it. This file (r_bsp_config_reference.h)
+* is just a reference file that the user can use to make their own r_bsp_config.h file.
+************************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 15.05.2017 1.00 First Release
+* : 01.12.2017 1.01 Added the following macro definition.
+* - BSP_CFG_EBMAPCR_1ST_PRIORITY
+* - BSP_CFG_EBMAPCR_2ND_PRIORITY
+* - BSP_CFG_EBMAPCR_3RD_PRIORITY
+* - BSP_CFG_EBMAPCR_4TH_PRIORITY
+* - BSP_CFG_EBMAPCR_5TH_PRIORITY
+* : 01.07.2018 1.02 Added the following macro definition.
+* - BSP_CFG_CONFIGURATOR_SELECT
+* Add RTOS support. FreeRTOS. Define a timer for RTOS.
+***********************************************************************************************************************/
+#ifndef R_BSP_CONFIG_REF_HEADER_FILE
+#define R_BSP_CONFIG_REF_HEADER_FILE
+
+/***********************************************************************************************************************
+Configuration Options
+***********************************************************************************************************************/
+
+/* NOTE:
+ The default settings are the same as when using RSKRX65N-2MB.
+ Change to the settings for the user board.
+*/
+
+/* Start up select
+ 0 = Enable BSP startup program.
+ 1 = Disable BSP startup program. (e.g. Using user startup program.)
+*/
+#define BSP_CFG_STARTUP_DISABLE (0)
+
+/* Enter the product part number for your MCU. This information will be used to obtain information about your MCU such
+ as package and memory size.
+ To help parse this information, the part number will be defined using multiple macros.
+ R 5 F 56 5N E D D FP
+ | | | | | | | | | Macro Name Description
+ | | | | | | | | |__BSP_CFG_MCU_PART_PACKAGE = Package type, number of pins, and pin pitch
+ | | | | | | | |____not used = Products with wide temperature range
+ | | | | | | |______BSP_CFG_MCU_PART_ENCRYPTION_INCLUDED = Encryption module included/not included
+ | | | | | |________BSP_CFG_MCU_PART_MEMORY_SIZE = ROM, RAM, and Data Flash Capacity
+ | | | | |___________BSP_CFG_MCU_PART_GROUP = Group name
+ | | | |______________BSP_CFG_MCU_PART_SERIES = Series name
+ | | |________________BSP_CFG_MCU_PART_MEMORY_TYPE = Type of memory (Flash, ROMless)
+ | |__________________not used = Renesas MCU
+ |____________________not used = Renesas semiconductor product.
+ */
+
+/* Package type. Set the macro definition based on values below:
+ Character(s) = Value for macro = Package Type/Number of Pins/Pin Pitch
+ FC = 0x0 = LFQFP/176/0.50
+ BG = 0x1 = LFBGA/176/0.80
+ LC = 0x2 = TFLGA/177/0.50
+ FB = 0x3 = LFQFP/144/0.50
+ LK = 0x4 = TFLGA/145/0.50
+ FP = 0x5 = LFQFP/100/0.50
+ LJ = 0xA = TFLGA/100/0.65
+*/
+#define BSP_CFG_MCU_PART_PACKAGE (0x5) // <-- Updated by GUI. Do not edit this value manually
+
+/* Whether Encryption and SDHI/SDSI are included or not.
+ Character(s) = Value for macro = Description
+ A = false = Encryption module not included, SDHI/SDSI module not included
+ B = false = Encryption module not included, SDHI/SDSI module included
+ D = false = Encryption module not included, SDHI/SDSI module included, dual-bank structure
+ E = true = Encryption module included, SDHI/SDSI module not included
+ F = true = Encryption module included, SDHI/SDSI module included
+ H = true = Encryption module included, SDHI/SDSI module included, dual-bank structure
+*/
+#define BSP_CFG_MCU_PART_ENCRYPTION_INCLUDED (false) // <-- Updated by GUI. Do not edit this value manually
+
+/* ROM, RAM, and Data Flash Capacity.
+ Character(s) = Value for macro = ROM Size/Ram Size/Data Flash Size
+ 4 = 0x4 = 512KB/256KB/Not equipped
+ 7 = 0x7 = 768KB/256KB/Not equipped
+ 9 = 0x9 = 1MB/256KB/Not equipped
+ C = 0xC = 1.5MB/640KB/32KB
+ E = 0xE = 2MB/640KB/32KB
+ NOTE: When the RAM capacity is 640KB, the RAM areas are not contiguous.
+*/
+#define BSP_CFG_MCU_PART_MEMORY_SIZE (0xE) // <-- Updated by GUI. Do not edit this value manually
+
+/* Group name.
+ Character(s) = Value for macro = Description
+ 5N/51 = 0x0 = RX65N Group/RX651 Group
+*/
+#define BSP_CFG_MCU_PART_GROUP (0x0) // <-- Updated by GUI. Do not edit this value manually
+
+/* Series name.
+ Character(s) = Value for macro = Description
+ 56 = 0x0 = RX600 Series
+*/
+#define BSP_CFG_MCU_PART_SERIES (0x0) // <-- Updated by GUI. Do not edit this value manually
+
+/* Memory type.
+ Character(s) = Value for macro = Description
+ F = 0x0 = Flash memory version
+*/
+#define BSP_CFG_MCU_PART_MEMORY_TYPE (0x0) // <-- Updated by GUI. Do not edit this value manually
+
+/* Whether to use 1 stack or 2. RX MCUs have the ability to use 2 stacks: an interrupt stack and a user stack.
+ * When using 2 stacks the user stack will be used during normal user code. When an interrupt occurs the CPU
+ * will automatically shift to using the interrupt stack. Having 2 stacks can make it easier to figure out how
+ * much stack space to allocate since the user does not have to worry about always having enough room on the
+ * user stack for if-and-when an interrupt occurs. Some users will not want 2 stacks though because it is not
+ * needed in all applications and can lead to wasted RAM (i.e. space in between stacks that is not used).
+ * If only 1 stack is used then the interrupt stack is the one that will be used. If 1 stack is chosen then
+ * the user may want to remove the 'SU' section from the linker sections to remove any linker warnings.
+ *
+ * 0 = Use 1 stack. Disable user stack. User stack size set below will be ignored.
+ * 1 = Use 2 stacks. User stack and interrupt stack will both be used.
+ */
+#define BSP_CFG_USER_STACK_ENABLE (1)
+
+/* When using the user startup program, disable the following code. */
+#if (BSP_CFG_STARTUP_DISABLE == 0)
+
+/* The 'BSP_DECLARE_STACK' macro is checked so that the stack is only declared in one place (resetprg.c). Every time a
+ '#pragma stacksize' is encountered, the stack size is increased. This prevents multiplication of stack size. */
+#if defined(BSP_DECLARE_STACK)
+ /* If only 1 stack is chosen using BSP_CFG_USER_STACK_ENABLE then no RAM will be allocated for the user stack. */
+ #if (BSP_CFG_USER_STACK_ENABLE == 1)
+ /* User Stack size in bytes. The Renesas RX toolchain sets the stack size using the #pragma stacksize directive. */
+ #pragma stacksize su=0x3000
+ #endif
+
+/* Interrupt Stack size in bytes. The Renesas RX toolchain sets the stack size using the #pragma stacksize directive.
+ * If the interrupt stack is the only stack being used then the user will likely want to increase the default size
+ * below.
+ */
+#pragma stacksize si=0x3000
+#endif
+
+#endif /* BSP_CFG_STARTUP_DISABLE == 0 */
+
+/* Heap size in bytes.
+ To disable the heap you must follow these steps:
+ 1) Set this macro (BSP_CFG_HEAP_BYTES) to 0.
+ 2) Set the macro BSP_CFG_IO_LIB_ENABLE to 0.
+ 3) Disable stdio from being built into the project library. This is done by going into the Renesas RX Toolchain
+ settings and choosing the Standard Library section. After that choose 'Standard Library' for Category in HEW or
+ choose 'Contents' in E2Studio. This will present a list of modules that can be included. Uncheck the box for
+ stdio.h.
+*/
+#define BSP_CFG_HEAP_BYTES (0x2000)
+
+/* Initializes C input & output library functions.
+ 0 = Disable I/O library initialization in resetprg.c. If you are not using stdio then use this value.
+ 1 = Enable I/O library initialization in resetprg.c. This is default and needed if you are using stdio. */
+#define BSP_CFG_IO_LIB_ENABLE (1)
+
+/* If desired the user may redirect the stdio charget() and/or charput() functions to their own respective functions
+ by enabling below and providing and replacing the my_sw_... function names with the names of their own functions. */
+#define BSP_CFG_USER_CHARGET_ENABLED (0)
+#define BSP_CFG_USER_CHARGET_FUNCTION my_sw_charget_function
+
+#define BSP_CFG_USER_CHARPUT_ENABLED (0)
+#define BSP_CFG_USER_CHARPUT_FUNCTION my_sw_charput_function
+
+/* After reset MCU will operate in Supervisor mode. To switch to User mode, set this macro to '1'. For more information
+ on the differences between these 2 modes see the CPU >> Processor Mode section of your MCU's hardware manual.
+ 0 = Stay in Supervisor mode.
+ 1 = Switch to User mode.
+*/
+#define BSP_CFG_RUN_IN_USER_MODE (0)
+
+/* Clock source select (CKSEL).
+ 0 = Low Speed On-Chip Oscillator (LOCO)
+ 1 = High Speed On-Chip Oscillator (HOCO)
+ 2 = Main Clock Oscillator
+ 3 = Sub-Clock Oscillator
+ 4 = PLL Circuit
+*/
+#define BSP_CFG_CLOCK_SOURCE (4) // <-- Updated by GUI. Do not edit this value manually
+
+/* Main clock Oscillator Switching (MOSEL).
+ 0 = Resonator
+ 1 = External clock input
+*/
+#define BSP_CFG_MAIN_CLOCK_SOURCE (0) // <-- Updated by GUI. Do not edit this value manually
+
+/* The sub-clock oscillation control for using the RTC.
+ When '1' is selected, the registers related to RTC are initialized and the sub-clock oscillator is operated.
+ 0 = The RTC is not to be used.
+ 1 = The RTC is to be used.
+*/
+#define BSP_CFG_RTC_ENABLE (0) // <-- Updated by GUI. Do not edit this value manually
+
+/* Sub-Clock Oscillator Drive Capacity Control (RTCDV).
+ 0 = Drive capacity for standard CL.
+ 1 = Drive capacity for low CL.
+*/
+#define BSP_CFG_SOSC_DRV_CAP (0) // <-- Updated by GUI. Do not edit this value manually //standard CL by default
+
+/* Clock configuration options.
+ The input clock frequency is specified and then the system clocks are set by specifying the multipliers used. The
+ multiplier settings are used to set the clock registers in resetprg.c. If a 24MHz clock is used and the
+ ICLK is 120MHz, PCLKA is 120MHz, PCLKB is 60MHz, PCLKC is 60MHz, PCLKD is 60MHz, FCLK is 60MHz, USB Clock is 48MHz,
+ and BCLK is 120MHz then the settings would be:
+
+ BSP_CFG_XTAL_HZ = 24000000
+ BSP_CFG_PLL_DIV = 1 (no division)
+ BSP_CFG_PLL_MUL = 10.0 (24MHz x 10.0 = 240MHz)
+ BSP_CFG_ICK_DIV = 2 : System Clock (ICLK) =
+ (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_ICK_DIV) = 120MHz
+ BSP_CFG_PCKA_DIV = 2 : Peripheral Clock A (PCLKA) =
+ (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKA_DIV) = 120MHz
+ BSP_CFG_PCKB_DIV = 4 : Peripheral Clock B (PCLKB) =
+ (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKB_DIV) = 60MHz
+ BSP_CFG_PCKC_DIV = 4 : Peripheral Clock C (PCLKC) =
+ (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKC_DIV) = 60MHz
+ BSP_CFG_PCKD_DIV = 4 : Peripheral Clock D (PCLKD) =
+ (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKD_DIV) = 60MHz
+ BSP_CFG_FCK_DIV = 4 : Flash IF Clock (FCLK) =
+ (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_FCK_DIV) = 60MHz
+ BSP_CFG_BCK_DIV = 2 : External Bus Clock (BCK) =
+ (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_BCK_DIV) = 120MHz
+ BSP_CFG_UCK_DIV = 5 : USB Clock (UCLK) =
+ (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_UCK_DIV) = 48MHz
+*/
+
+/* Input clock frequency in Hz (XTAL or EXTAL). */
+#define BSP_CFG_XTAL_HZ (12000000) // <-- Updated by GUI. Do not edit this value manually
+
+/* The HOCO can operate at several different frequencies. Choose which one using the macro below.
+ Available frequency settings:
+ 0 = 16MHz (default)
+ 1 = 18MHz
+ 2 = 20MHz
+*/
+#define BSP_CFG_HOCO_FREQUENCY (0) // <-- Updated by GUI. Do not edit this value manually
+
+/* PLL clock source (PLLSRCEL). Choose which clock source to input to the PLL circuit.
+ Available clock sources:
+ 0 = Main clock (default)
+ 1 = HOCO
+*/
+#define BSP_CFG_PLL_SRC (0) // <-- Updated by GUI. Do not edit this value manually
+
+/* PLL Input Frequency Division Ratio Select (PLIDIV).
+ Available divisors = /1 (no division), /2, /3
+*/
+#define BSP_CFG_PLL_DIV (1) // <-- Updated by GUI. Do not edit this value manually
+
+/* PLL Frequency Multiplication Factor Select (STC).
+ Available multipliers = x10.0 to x30.0 in 0.5 increments (e.g. 10.0, 10.5, 11.0, 11.5, ..., 29.0, 29.5, 30.0)
+*/
+#define BSP_CFG_PLL_MUL (20.0) // <-- Updated by GUI. Do not edit this value manually
+
+/* System Clock Divider (ICK).
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define BSP_CFG_ICK_DIV (2) // <-- Updated by GUI. Do not edit this value manually
+
+/* Peripheral Module Clock A Divider (PCKA).
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define BSP_CFG_PCKA_DIV (2) // <-- Updated by GUI. Do not edit this value manually
+
+/* Peripheral Module Clock B Divider (PCKB).
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define BSP_CFG_PCKB_DIV (4) // <-- Updated by GUI. Do not edit this value manually
+
+/* Peripheral Module Clock C Divider (PCKC).
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define BSP_CFG_PCKC_DIV (4) // <-- Updated by GUI. Do not edit this value manually
+
+/* Peripheral Module Clock D Divider (PCKD).
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define BSP_CFG_PCKD_DIV (4) // <-- Updated by GUI. Do not edit this value manually
+
+/* External Bus Clock Divider (BCLK).
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define BSP_CFG_BCK_DIV (2) // <-- Updated by GUI. Do not edit this value manually
+
+/* Flash IF Clock Divider (FCK).
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define BSP_CFG_FCK_DIV (4) // <-- Updated by GUI. Do not edit this value manually
+
+/* USB Clock Divider Select.
+ Available divisors = /2, /3, /4, /5
+*/
+#define BSP_CFG_UCK_DIV (5) // <-- Updated by GUI. Do not edit this value manually
+
+/* Configure BCLK output pin (only effective when external bus enabled)
+ Values 0=no output, 1 = BCK frequency, 2= BCK/2 frequency
+*/
+#define BSP_CFG_BCLK_OUTPUT (0) // <-- Updated by GUI. Do not edit this value manually
+
+/* Configure SDCLK output pin (only effective when external bus enabled)
+ Values 0=no output, 1 = BCK frequency
+*/
+#define BSP_CFG_SDCLK_OUTPUT (0) // <-- Updated by GUI. Do not edit this value manually
+
+/* Main Clock Oscillator Wait Time (MOSCWTCR).
+ The value of MOSCWTCR register required for correspondence with the waiting time required to secure stable oscillation
+ by the main clock oscillator is obtained by using the maximum frequency for fLOCO in the formula below.
+
+ BSP_CFG_MOSC_WAIT_TIME > (tMAINOSC * (fLOCO_max) + 16)/32
+ (tMAINOSC: main clock oscillation stabilization time; fLOCO_max: maximum frequency for fLOCO)
+
+ If tMAINOSC is 9.98 ms and fLOCO_max is 264 kHz (the period is 1/3.78 us), the formula gives
+ BSP_CFG_MOSC_WAIT_TIME > (9.98 ms * (264 kHZ) + 16)/32 = 82.83, so set the BSP_CFG_MOSC_WAIT_TIME to 83(53h).
+
+ NOTE: The waiting time is not required when an external clock signal is input for the main clock oscillator.
+ Set the BSP_CFG_MOSC_WAIT_TIME to 00h.
+*/
+#define BSP_CFG_MOSC_WAIT_TIME (0x53) // <-- Updated by GUI. Do not edit this value manually
+
+/* Sub-Clock Oscillator Wait Time (SOSCWTCR).
+ The value of SOSCWTCR register required for correspondence with the expected time to secure settling of oscillation
+ by the sub-clock oscillator is obtained by using the maximum frequency for fLOCO in the formula below.
+
+ BSP_CFG_SOSC_WAIT_TIME > (tSUBOSC * (fLOCO_max) + 16)/16384
+ (tSUBOSC: sub-clock oscillation stabilization time; fLOCO_max: maximum frequency for fLOCO)
+
+ If tSUBOSC is 2 s and fLOCO is 264 kHz (the period is 1/3.78 us), the formula gives
+ BSP_CFG_SOSC_WAIT_TIME > (2 s * (264 kHz) +16)/16384 = 32.22, so set the BSP_CFG_SOSC_WAIT_TIME bits to 33(21h).
+*/
+#define BSP_CFG_SOSC_WAIT_TIME (0x21) // <-- Updated by GUI. Do not edit this value manually
+
+/* ROM Cache Enable Register (ROMCE).
+ 0 = ROM cache operation disabled.
+ 1 = ROM cache operation enabled.
+*/
+#define BSP_CFG_ROM_CACHE_ENABLE (0)
+
+/* Configure WDT and IWDT settings.
+ OFS0 - Option Function Select Register 0
+ b31:b29 Reserved When reading, these bits return the value written by the user. The write value should be 1.
+ b28 WDTRSTIRQS - WDT Reset Interrupt Request - What to do on underflow (0=take interrupt, 1=reset MCU)
+ b27:b26 WDTRPSS - WDT Window Start Position Select - (0=25%, 1=50%, 2=75%, 3=100%,don't use)
+ b25:b24 WDTRPES - WDT Window End Position Select - (0=75%, 1=50%, 2=25%, 3=0%,don't use)
+ b23:b20 WDTCKS - WDT Clock Frequency Division Ratio - (1=PCLKB/4, 4=PCLKB/64, 0xF=PCLKB/128, 6=PCLKB/256,
+ 7=PCLKB/2048, 8=PCLKB/8192)
+ b19:b18 WDTTOPS - WDT Timeout Period Select (0=1024 cycles, 1=4096, 2=8192, 3=16384)
+ b17 WDTSTRT - WDT Start Mode Select - (0=auto-start after reset, 1=halt after reset)
+ b16:b15 Reserved (set to 1)
+ b14 IWDTSLCSTP - IWDT Sleep Mode Count Stop Control - (0=can't stop count, 1=stop w/some low power modes)
+ b13 Reserved (set to 1)
+ b12 IWDTRSTIRQS - IWDT Reset Interrupt Request - What to do on underflow (0=take interrupt, 1=reset MCU)
+ b11:b10 IWDTRPSS - IWDT Window Start Position Select - (0=25%, 1=50%, 2=75%, 3=100%,don't use)
+ b9:b8 IWDTRPES - IWDT Window End Position Select - (0=75%, 1=50%, 2=25%, 3=0%,don't use)
+ b7:b4 IWDTCKS - IWDT Clock Frequency Division Ratio - (0=none, 2=/16, 3 = /32, 4=/64, 0xF=/128, 5=/256)
+ b3:b2 IWDTTOPS - IWDT Timeout Period Select - (0=1024 cycles, 1=4096, 2=8192, 3=16384)
+ b1 IWDTSTRT - IWDT Start Mode Select - (0=auto-start after reset, 1=halt after reset)
+ b0 Reserved (set to 1)
+*/
+#define BSP_CFG_OFS0_REG_VALUE (0xFFFFFFFF) // <-- Updated by GUI. Do not edit this value manually //Disable by default
+
+/* Configure whether voltage detection 0 circuit and HOCO are enabled after reset.
+ OFS1 - Option Function Select Register 1
+ b31:b9 Reserved (set to 1)
+ b8 HOCOEN - Enable/disable HOCO oscillation after a reset (0=enable, 1=disable)
+ b7:b3 Reserved When reading, these bits return the value written by the user. The write value should be 1.
+ b2 LVDAS - Voltage Detection 0 circuit start (1=monitoring disabled)
+ b1:b0 VDSEL - Voltage Detection 0 level select (1=2.94v, 2=2.87v, 3=2.80v)
+ NOTE: If HOCO oscillation is enabled by OFS1.HOCOEN, HOCO frequency is 16MHz.
+ BSP_CFG_HOCO_FREQUENCY should be default value.
+*/
+#define BSP_CFG_OFS1_REG_VALUE (0xFFFFFFFF) // <-- Updated by GUI. Do not edit this value manually //Disable by default
+
+/* Trusted memory is facility to prevent the reading of blocks 8 and 9 and blocks 46 and 47 (in dual mode) in
+ the code flash memory by third party software. This feature is disabled by default.
+ TMEF - TM Enable Flag Register
+ b31 Reserved (set to 1)
+ b30:b28 TMEFDB - Dual-Bank TM Enable - 000: The TM function in the address range from FFEE 0000h to
+ FFEE FFFFh is enabled in dual mode.
+ - 111: The TM function in the address range from FFEE 0000h to
+ FFEE FFFFh is disabled in dual mode.
+ b27 Reserved (set to 1)
+ b26:b24 TMEFF - TM Enable - 000: TM function is enabled.
+ - 111: TM function is disabled.
+ b23:b0 Reserved (set to 1)
+ NOTE: If the dual bank function has not been incorporated in a device,
+ TMEFDB bits [b30:b26] are reserved area.
+*/
+#define BSP_CFG_TRUSTED_MODE_FUNCTION (0xFFFFFFFF) //Disable by default
+
+/* Configure FAW register is used to set the write protection flag and boot area select flag
+ for setting the flash access window startaddress and flash access window end address.
+ FAW - Flash Access Window Setting Register
+ b31 BTFLG - Boot Area Select Flag - 0: FFFF C000h to FFFF DFFFh are used as the boot area
+ - 1: FFFF E000h to FFFF FFFFh are used as the boot area
+ b30:b28 Reserved - When reading, these bits return the value written by the user.The write value should be 1.
+ b27:b16 FAWE - Flash Access Window End Address - Flash access window end address
+ b15 FSPR - Access Window Protection Flag - 0: With protection (P/E disabled)
+ - 1: Without protection (P/E enabled)
+ b14:b12 Reserved - When reading, these bits return the value written by the user.The write value should be 1.
+ b11:b0 FAWS - Flash Access Window Start Address - Flash access window start address
+ NOTE: Once 0 is written to this bit, the bit can never be restored to 1.
+ Therefore, the access window and the BTFLG bit never be set again or the TM function
+ never be disabled once it has been enabled.
+ Exercise extra caution when handling the FSPR bit.
+*/
+#define BSP_CFG_FAW_REG_VALUE (0xFFFFFFFF) //Disable by default
+
+/* The ROM code protection register is a function to prohibit reading from or programming to the flash memory
+ when the flash programmer is used during off-board programming.
+ ROMCODE - ROM Code Protection Register
+ b31:b0 ROM Code - 0000 0000h: ROM code protection enabled (ROM code protection 1).
+ 0000 0001h: ROM code protection enabled (ROM code protection 2).
+ Other than above: ROM code protection disabled.
+ Note. The ROMCODE register should be set in 32-bit units.
+*/
+#define BSP_CFG_ROMCODE_REG_VALUE (0xFFFFFFFF) //Disable by default
+
+/* Select the bank mode of dual-bank function of the code flash memory.
+ 0 = Dual mode.
+ 1 = Linear mode.
+ NOTE: If the dual bank function has been incorporated in a device, select the bank mode in this macro.
+ Default setting of the bank mode is linear mode.
+ If the dual bank function has not been incorporated in a device, this macro should be 1.
+*/
+#define BSP_CFG_CODE_FLASH_BANK_MODE (1) //Linear mode by default
+
+/* Select the startup bank of the program when dual bank function is in dual mode.
+ 0 = The address range of bank 1 from FFE00000h to FFEFFFFFh and bank 0 from FFF00000h to FFFFFFFFh.
+ 1 = The address range of bank 1 from FFF00000h to FFFFFFFFh and bank 0 from FFE00000h to FFEFFFFFh.
+ NOTE: If the dual bank function has been incorporated in a device, select the start bank in this macro.
+ Default setting of the start bank is bank0.
+ If the dual bank function has not been incorporated in a device, this macro should be 0.
+*/
+#define BSP_CFG_CODE_FLASH_START_BANK (0) //Bank0 by default
+
+/* This macro lets other modules no if a RTOS is being used.
+ 0 = RTOS is not used.
+ 1 = FreeRTOS is used.
+ 2 = embOS is used.(This is not available.)
+ 3 = MicroC_OS is used.(This is not available.)
+ 4 = RI600V4 or RI600PX is used.(This is not available.)
+*/
+/* As of today, we need a workaround to avoid the problem that the Smart Configurator does not have such GUI
+ yet and the BSP_CFG_RTOS_USED here is set to (0) every time of code generation by the Smart Configurator.
+ The BSP_CFG_RTOS_USED is set to (1) in the r_bsp.h instead of here so that the setting of here is ignored.
+*/
+#if !defined(BSP_CFG_RTOS_USED) || (BSP_CFG_RTOS_USED == 0)
+#if defined(BSP_CFG_RTOS_USED)
+#undef BSP_CFG_RTOS_USED
+#endif
+#define BSP_CFG_RTOS_USED (0) // <-- Updated by GUI. Do not edit this value manually
+#endif
+
+/* This macro is used to select which CMT channel used for system timer of RTOS.
+ * The setting of this macro is only valid if the macro BSP_CFG_RTOS_USED is set to a value other than 0. */
+#if (BSP_CFG_RTOS_USED != 0)
+/* Setting value.
+ * 0 = CMT channel 0 used for system timer of RTOS (recommended to be used for RTOS).
+ * 1 = CMT channel 1 used for system timer of RTOS.
+ * 2 = CMT channel 2 used for system timer of RTOS.
+ * 3 = CMT channel 3 used for system timer of RTOS.
+ * Others = Invalid. */
+#define BSP_CFG_RTOS_SYSTEM_TIMER (0)
+#endif
+
+/* By default modules will use global locks found in mcu_locks.c. If the user is using a RTOS and would rather use its
+ locking mechanisms then they can change this macro.
+ NOTE: If '1' is chosen for this macro then the user must also change the next macro 'BSP_CFG_USER_LOCKING_TYPE'.
+ 0 = Use default locking (non-RTOS)
+ 1 = Use user defined locking mechanism.
+*/
+#define BSP_CFG_USER_LOCKING_ENABLED (0)
+
+/* If the user decides to use their own locking mechanism with FIT modules then they will need to redefine the typedef
+ that is used for the locks. If the user is using a RTOS then they would likely redefine the typedef to be
+ a semaphore/mutex type of their RTOS. Use the macro below to set the type that will be used for the locks.
+ NOTE: If BSP_CFG_USER_LOCKING_ENABLED == 0 then this typedef is ignored.
+ NOTE: Do not surround the type with parentheses '(' ')'.
+*/
+#define BSP_CFG_USER_LOCKING_TYPE bsp_lock_t
+
+/* If the user decides to use their own locking mechanism with FIT modules then they will need to define the functions
+ that will handle the locking and unlocking. These functions should be defined below.
+ If BSP_CFG_USER_LOCKING_ENABLED is != 0:
+ R_BSP_HardwareLock(mcu_lock_t hw_index) will call BSP_CFG_USER_LOCKING_HW_LOCK_FUNCTION(mcu_lock_t hw_index)
+ R_BSP_HardwareUnlock(mcu_lock_t hw_index) will call BSP_CFG_USER_LOCKING_HW_UNLOCK_FUNCTION(mcu_lock_t hw_index)
+ NOTE:With these functions the index into the array holding the global hardware locks is passed as the parameter.
+ R_BSP_SoftwareLock(BSP_CFG_USER_LOCKING_TYPE * plock) will call
+ BSP_CFG_USER_LOCKING_SW_LOCK_FUNCTION(BSP_CFG_USER_LOCKING_TYPE * plock)
+ R_BSP_SoftwareUnlock(BSP_CFG_USER_LOCKING_TYPE * plock) will call
+ BSP_CFG_USER_LOCKING_SW_UNLOCK_FUNCTION(BSP_CFG_USER_LOCKING_TYPE * plock)
+ NOTE:With these functions the actual address of the lock to use is passed as the parameter.
+ NOTE: These functions must return a boolean. If lock was obtained or released successfully then return true. Else,
+ return false.
+ NOTE: If BSP_CFG_USER_LOCKING_ENABLED == 0 then this typedef is ignored.
+ NOTE: Do not surround the type with parentheses '(' ')'.
+*/
+#define BSP_CFG_USER_LOCKING_HW_LOCK_FUNCTION my_hw_locking_function
+#define BSP_CFG_USER_LOCKING_HW_UNLOCK_FUNCTION my_hw_unlocking_function
+#define BSP_CFG_USER_LOCKING_SW_LOCK_FUNCTION my_sw_locking_function
+#define BSP_CFG_USER_LOCKING_SW_UNLOCK_FUNCTION my_sw_unlocking_function
+
+/* If the user would like to determine if a warm start reset has occurred, then they may enable one or more of the
+ * following callback definitions AND provide a call back function name for the respective callback
+ * function (to be defined by the user). Setting BSP_CFG_USER_WARM_START_CALLBACK_PRE_INITC_ENABLED = 1 will result
+ * in a callback to the user defined my_sw_warmstart_prec_function just prior to the initialization of the C
+ * runtime environment by resetprg.
+ *
+ * Setting BSP_CFG_USER_WARM_START_CALLBACK_POST_INITC_ENABLED = 1 will result in a callback to the user defined
+ * my_sw_warmstart_postc_function just after the initialization of the C runtime environment by resetprg.
+ */
+#define BSP_CFG_USER_WARM_START_CALLBACK_PRE_INITC_ENABLED (0)
+#define BSP_CFG_USER_WARM_START_PRE_C_FUNCTION my_sw_warmstart_prec_function
+
+#define BSP_CFG_USER_WARM_START_CALLBACK_POST_INITC_ENABLED (0)
+#define BSP_CFG_USER_WARM_START_POST_C_FUNCTION my_sw_warmstart_postc_function
+
+/* By default FIT modules will check input parameters to be valid. This is helpful during development but some users
+ will want to disable this for production code. The reason for this would be to save execution time and code space.
+ This macro is a global setting for enabling or disabling parameter checking. Each FIT module will also have its
+ own local macro for this same purpose. By default the local macros will take the global value from here though
+ they can be overridden. Therefore, the local setting has priority over this global setting. Disabling parameter
+ checking should only used when inputs are known to be good and the increase in speed or decrease in code space is
+ needed.
+ 0 = Global setting for parameter checking is disabled.
+ 1 = Global setting for parameter checking is enabled (Default).
+*/
+#define BSP_CFG_PARAM_CHECKING_ENABLE (1)
+
+/* The extended bus master has five transfer sources: EDMAC, GLCDC-GRA1 (GLCDC graphics 1 data read), GLCDCGRA2 (GLCDC
+ graphics 2 data read), DRW2D-TX (DRW2D texture data read), and DRW2D-FB (DRW2D frame buffer data read write and
+ display list data read).
+ The default priority order in bsp is below
+ GLCDC-GRA1 > GLCDC-GRA2 > DRW2D-TX > DRW2D-FB > EDMAC.
+ Priority can be changed with this macro.
+
+ Extended Bus Master Priority setting
+ 0 = GLCDC graphics 1 data read
+ 1 = DRW2D texture data read
+ 2 = DRW2D frame buffer data read write and display list data read
+ 3 = GLCDC graphics 2 data read
+ 4 = EDMAC
+
+ Note : This macro is only available for products with at least 1.5 Mbytes of code flash memory.
+ Settings other than above are prohibited.
+ Duplicate priority settings can not be made.
+*/
+#define BSP_CFG_EBMAPCR_1ST_PRIORITY (0) /* Extended Bus Master 1st Priority Selection */
+#define BSP_CFG_EBMAPCR_2ND_PRIORITY (3) /* Extended Bus Master 2nd Priority Selection */
+#define BSP_CFG_EBMAPCR_3RD_PRIORITY (1) /* Extended Bus Master 3rd Priority Selection */
+#define BSP_CFG_EBMAPCR_4TH_PRIORITY (2) /* Extended Bus Master 4th Priority Selection */
+#define BSP_CFG_EBMAPCR_5TH_PRIORITY (4) /* Extended Bus Master 5th Priority Selection */
+
+/* This macro is used to define the voltage that is supplied to the MCU (Vcc). This macro is defined in millivolts. This
+ macro does not actually change anything on the MCU. Some FIT modules need this information so it is defined here. */
+#define BSP_CFG_MCU_VCC_MV (3300) // <-- Updated by GUI. Do not edit this value manually
+
+/* Allow initialization of auto-generated peripheral initialization code by Smart Configurator tool.
+ When not using the Smart Configurator, set the value of BSP_CFG_CONFIGURATOR_SELECT to 0.
+ 0 = Disabled (default)
+ 1 = Smart Configurator initialization code used
+*/
+#define BSP_CFG_CONFIGURATOR_SELECT (1) // <-- Updated by GUI. Do not edit this value manually
+
+/* There are multiple versions of the RSKRX65N-2MB. Choose which board is currently being used below.
+ 0 = 1st Prototype Board (RTK50565N2CxxxxxBR)
+ 1 = rev. 1.00 Board (RTK50565N2C00000BE)
+ 2 = RX65N Envision Kit
+ 3 = RX65N GR-ROSE
+ (4 = RX64M GR-KAEDE // FIXME: find a better way)
+ 5 = RX65N TB
+*/
+#define BSP_CFG_BOARD_REVISION (5)
+
+#endif /* R_BSP_CONFIG_REF_HEADER_FILE */
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/r_config/r_bsp_config_readme.txt b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/r_config/r_bsp_config_readme.txt
new file mode 100644
index 00000000000..6a9002cf4f3
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/r_config/r_bsp_config_readme.txt
@@ -0,0 +1,12 @@
+FIT r_config folder
+-------------------
+The purpose of the r_config folder is to provide one place where the user can store all of their FIT configuration
+files. Putting the files in one place makes them easy to find, backup, and put in a version control system.
+
+FIT Modules are distributed with a reference configuration file. These files end with '_reference.h'. For example,
+the reference configuration file for the r_bsp is named r_bsp_config_reference.h. Reference configuration files are
+provided so that the user always has a known-good configuration to revert to. When adding a FIT Module to a project the
+user should copy this reference configuration file to this folder and remove '_reference' from the filename
+(r_bsp_config_reference.h is renamed to r_bsp_config.h). For the r_bsp the reference configuration file can be found in
+the 'board' folder for the currently chosen development board. For other FIT Modules the reference configuration file
+can be found in the 'ref' folder of the FIT Module.
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/r_config/r_bsp_interrupt_config.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/r_config/r_bsp_interrupt_config.h
new file mode 100644
index 00000000000..dd09ad9edc6
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/r_config/r_bsp_interrupt_config.h
@@ -0,0 +1,214 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : r_bsp_interrupt_config.h
+* Description : This module maps Interrupt A & B interrupts. More information on how this is done is given below.
+***********************************************************************************************************************/
+/**********************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 01.10.2016 1.00 First Release
+* : 15.05.2017 2.00 Changed the name of the following macro definition, because there was a mistake
+* in the name of macro definition.
+* - From XXX_TPU0_TGI0V to XXX_TPU0_TCI0V.
+* - From XXX_TPU1_TGI1V to XXX_TPU1_TCI1V.
+* - From XXX_TPU1_TGI1U to XXX_TPU1_TCI1U.
+* - From XXX_TPU2_TGI2V to XXX_TPU2_TCI2V.
+* - From XXX_TPU2_TGI2U to XXX_TPU2_TCI2U.
+* - From XXX_TPU3_TGI3V to XXX_TPU3_TCI3V.
+* - From XXX_TPU4_TGI4V to XXX_TPU4_TCI4V.
+* - From XXX_TPU4_TGI4U to XXX_TPU4_TCI4U.
+* - From XXX_TPU5_TGI5V to XXX_TPU5_TCI5V.
+* - From XXX_TPU5_TGI5U to XXX_TPU5_TCI5U.
+* - From XXX_MTU0_TGIV0 to XXX_MTU0_TCIV0.
+* - From XXX_MTU1_TGIV1 to XXX_MTU1_TCIV1.
+* - From XXX_MTU1_TGIU1 to XXX_MTU1_TCIU1.
+* - From XXX_MTU2_TGIV2 to XXX_MTU2_TCIV2.
+* - From XXX_MTU2_TGIU2 to XXX_MTU2_TCIU2.
+* - From XXX_MTU3_TGIV3 to XXX_MTU3_TCIV3.
+* - From XXX_MTU4_TGIV4 to XXX_MTU4_TCIV4.
+* - From XXX_MTU6_TGIV6 to XXX_MTU6_TCIV6.
+* - From XXX_MTU7_TGIV7 to XXX_MTU7_TCIV7.
+* - From XXX_MTU8_TGIV8 to XXX_MTU8_TCIV8.
+* Added select processing of the following software configurable interrupt source.
+* - TSIP_PROC_BUSY
+* - TSIP_ROMOK
+* - TSIP_LONG_PLG
+* - TSIP_TEST_BUSY
+* - TSIP_WRRDY0
+* - TSIP_WRRDY1
+* - TSIP_WRRDY4
+* - TSIP_RDRDY0
+* - TSIP_RDRDY1
+* - TSIP_INTEGRATE_WRRDY
+* - TSIP_INTEGRATE_RDRDY
+***********************************************************************************************************************/
+#ifndef R_BSP_INTERRUPT_CONFIG_REF_HEADER_FILE
+#define R_BSP_INTERRUPT_CONFIG_REF_HEADER_FILE
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/* If you wish to use one of the interrupt below then set the appropriate configuration macro to the vector number you
+ * wish to use for that interrupt. For example, if you want to use the RTC carry interrupt (CUP) at vector 176 then you
+ * would do the following:
+ *
+ * #define BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP 176
+ */
+
+/* Interrupt B Sources.
+ * -Valid vector numbers are 128-207.
+ * -There are more vector slots for B sources than actual B sources. By default all B sources are mapped.
+ * -If using the 'TPU1, TGI1A' interrupt it must be vector 144 or 145. It is set to 144 by default.
+ * -If a peripheral interrupt is going to be used to wake up the MCU from All-Module Clock Stop Mode then it must be
+ * in a vector between 146 to 157. Peripheral interrupts that can do this are TMR interrupts and the 'USB0, USBI0'
+ * interrupt. By default the TMR interrupts are chosen since there are 12 of them and there are 12 slots.
+ */
+#define BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2 128
+#define BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3 129
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0 146
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0 147
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0 148
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1 149
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1 150
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1 151
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2 152
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2 153
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2 154
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3 155
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3 156
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3 157
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A 130
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B 131
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C 132
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D 133
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TCI0V 134
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A 144
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B 135
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1V 136
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1U 137
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A 138
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B 139
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2V 140
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2U 141
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A 142
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B 143
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C 145
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D 158
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TCI3V 159
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A 160
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B 161
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4V 162
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4U 163
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A 164
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B 165
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5V 166
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5U 167
+#define BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0 168
+#define BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0 169
+#define BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0 170
+#define BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0 171
+#define BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1 172
+#define BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1 173
+#define BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1 174
+#define BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1 175
+#define BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP 176
+#define BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0 177
+#define BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0 178
+#define BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0 179
+#define BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0 180
+#define BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1 181
+#define BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1 182
+#define BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1 183
+#define BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1 184
+#define BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0 185
+#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0 186
+#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0 187
+#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GCADI0 188
+#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1 189
+#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1 190
+#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GCADI1 191
+#define BSP_MAPPED_INT_CFG_B_VECT_RNG_RNGEND
+#define BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I 193
+#define BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I 194
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_PROC_BUSY 195
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_ROMOK 196
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_LONG_PLG 197
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_TEST_BUSY 198
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY0 199
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY1 200
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY4 201
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY0 202
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY1 203
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_WRRDY 204
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_RDRDY 205
+
+/* Interrupt A Sources.
+ * -Valid vector numbers are 208-255.
+ * -There are more A sources than A vector slots. By default none of the GPT interrupts are mapped.
+ * -If using the 'MTU1, TGI1A' interrupt it must be vector 208 or 209. It is set to 208 by default.
+ */
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0 209
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0 210
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0 211
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0 212
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0 213
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0 214
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0 215
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1 208
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1 216
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1 217
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1 218
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2 219
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2 220
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2 221
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2 222
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3 223
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3 224
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3 225
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3 226
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3 227
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4 228
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4 229
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4 230
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4 231
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4 232
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5 233
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5 234
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5 235
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6 236
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6 237
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6 238
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6 239
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6 240
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7 241
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7 242
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7 243
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7 244
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7 245
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8 246
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8 247
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8 248
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8 249
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TCIV8 250
+#define BSP_MAPPED_INT_CFG_A_VECT_AES_AESRDY
+#define BSP_MAPPED_INT_CFG_A_VECT_AES_AESEND
+
+#endif /* R_BSP_INTERRUPT_CONFIG_REF_HEADER_FILE */
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/r_config/r_byteq_config.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/r_config/r_byteq_config.h
new file mode 100644
index 00000000000..0b4d4f9bb52
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/r_config/r_byteq_config.h
@@ -0,0 +1,59 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : r_byteq_config.h
+* Description : Configures the byte queue memory allocation
+************************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 24.07.2013 1.00 Initial Release
+* : 11.21.2014 1.20 Removed dependency to BSP
+* : 30.09.2015 1.50 Added dependency to BSP
+***********************************************************************************************************************/
+#ifndef BYTEQ_CONFIG_H
+#define BYTEQ_CONFIG_H
+
+/***********************************************************************************************************************
+Includes , "Project Includes"
+***********************************************************************************************************************/
+#include "platform.h"
+
+/***********************************************************************************************************************
+Configuration Options
+***********************************************************************************************************************/
+
+/* SPECIFY WHETHER TO INCLUDE CODE FOR API PARAMETER CHECKING
+ Available settings:
+ BSP_CFG_PARAM_CHECKING_ENABLE:
+ Utilizes the system default setting
+ 1:
+ Includes parameter checking
+ 0:
+ Compiles out parameter checking
+*/
+#define BYTEQ_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+
+/* SPECIFY IF SHOULD USE MALLOC() TO ALLOCATE MEMORY FOR QUEUE CONTROL BLOCKS */
+#define BYTEQ_CFG_USE_HEAP_FOR_CTRL_BLKS (0)
+
+/* SPECIFY NUMBER OF STATIC QUEUE CONTROL BLOCKS TO SUPPORT */
+/* valid only when BYTEQ_USE_HEAP_FOR_CTRL_BLKS is set to 0 */
+#define BYTEQ_CFG_MAX_CTRL_BLKS (4)
+
+
+#endif /* BYTEQ_CONFIG_H */
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/r_config/r_flash_rx_config.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/r_config/r_flash_rx_config.h
new file mode 100644
index 00000000000..fbf916a0e97
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/r_config/r_flash_rx_config.h
@@ -0,0 +1,116 @@
+/***********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+ * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+ * SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+ ***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * File Name : r_flash_rx_config_reference.h
+ * Description : Configures the FLASH API module for RX200 and RX600 Series MCU's.
+ ***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* 12.04.2014 1.00 First Release
+* 22.12.2014 1.10 Added flash type usage comments.
+* 25.06.2015 1.20 Added FLASH_CFG_CODE_FLASH_RUN_FROM_ROM.
+* : 12.10.2016 2.00 Modified for BSPless operation (added FLASH_CFG_USE_FIT_BSP).
+***********************************************************************************************************************/
+#ifndef FLASH_CONFIG_HEADER_FILE
+#define FLASH_CONFIG_HEADER_FILE
+
+/* Set the following value to 0 when building without using the FIT BSP Module */
+#define FLASH_CFG_USE_FIT_BSP (1)
+
+
+/***********************************************************************************************************************
+ Configuration Options
+ ***********************************************************************************************************************/
+/* SPECIFY WHETHER TO INCLUDE CODE FOR API PARAMETER CHECKING
+ * Setting to BSP_CFG_PARAM_CHECKING_ENABLE utilizes the system default setting
+ * Setting to 1 includes parameter checking; 0 compiles out parameter checking
+ */
+#define FLASH_CFG_PARAM_CHECKING_ENABLE (1)
+
+
+/******************************************************************************
+ ENABLE CODE FLASH PROGRAMMING
+******************************************************************************/
+/* If you are only using data flash, set this to 0.
+ * Setting to 1 includes code to program the ROM area. When programming ROM,
+ * code must be executed from RAM, except under certain restrictions for flash
+ * type 3 (see section 2.14 in App Note). See section 2.13 in the App Note for
+ * details on how to set up code and the linker to execute code from RAM.
+ */
+#define FLASH_CFG_CODE_FLASH_ENABLE (0)
+
+
+/******************************************************************************
+ ENABLE BGO/NON-BLOCKING DATA FLASH OPERATIONS
+******************************************************************************/
+/* Setting this to 0 forces data flash API function to block until completed.
+ * Setting to 1 places the module in BGO (background operations) mode. In BGO
+ * mode, data flash operations return immediately after the operation has been
+ * started. Notification of the operation completion is done via the callback
+ * function.
+ */
+#define FLASH_CFG_DATA_FLASH_BGO (0)
+
+
+/******************************************************************************
+ ENABLE BGO/NON-BLOCKING CODE FLASH (ROM) OPERATIONS
+******************************************************************************/
+/* Setting this to 0 forces ROM API function to block until completed.
+ * Setting to 1 places the module in BGO (background operations) mode. In BGO
+ * mode, ROM operations return immediately after the operation has been started.
+ * Notification of the operation completion is done via the callback function.
+ * When reprogramming ROM, THE RELOCATABLE VECTOR TABLE AND CORRESPONDING
+ * INTERRUPT ROUTINES MUST BE IN RAM.
+ * See sections 2.16 Usage Notes in the App Note.
+ */
+#define FLASH_CFG_CODE_FLASH_BGO (0)
+
+
+/******************************************************************************
+ ENABLE CODE FLASH SELF-PROGRAMMING
+******************************************************************************/
+/* Set this to 0 when programming code flash while executing in RAM.
+ * Set this to 1 when programming code flash while executing from another
+ * segment in ROM (possible only with RX64M, RX71M, RX65N-2 groups).
+ * See section 2.14 in the App Note.
+ */
+#define FLASH_CFG_CODE_FLASH_RUN_FROM_ROM (0)
+
+
+/******************************************************************************
+ SET IPL OF FLASH READY INTERRUPT
+******************************************************************************/
+#define FLASH_CFG_FLASH_READY_IPL (5) // Flash type 2 only
+
+
+/******************************************************************************
+ ENABLE OR DISABLE LOCK BIT PROTECTION
+******************************************************************************/
+/* Each erasure block has a corresponding lock bit that can be used to
+ * protect that block from being programmed/erased after the lock bit is
+ * set. The use of lock bits can be used or ignored.
+ * Setting this to 1 will cause lock bits to be ignored and programs/erases to a
+ * block will not be limited.
+ * Setting this to 0 will cause lock bits to be used as the user configures through
+ * the Control command. This only applies to ROM as the DF does not have lock bits.
+ */
+#define FLASH_CFG_IGNORE_LOCK_BITS (1) // Flash type 2 only
+
+
+#endif /* FLASH_CONFIG_HEADER_FILE */
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/r_config/r_riic_rx_config.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/r_config/r_riic_rx_config.h
new file mode 100644
index 00000000000..162cde5ea41
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/r_config/r_riic_rx_config.h
@@ -0,0 +1,197 @@
+/***********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+ * No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO
+ * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
+ **********************************************************************************************************************/
+/***********************************************************************************************************************
+ * File Name : r_riic_rx_config_reference.h
+ * Description : Configures the RIIC drivers
+ **********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ * : 01.07.2013 1.00 First Release
+ * : 30.09.2013 1.10 Change symbol of return value and status
+ * : 08.10.2013 1.20 Modified processing for the I/O register initialization and mode transition
+ * when a stop condition is detected while the slave is communicating.
+ * Modified processing for mode transition when an API function is called
+ * while the bus is busy.
+ * Modified processing for mode transition
+ * when an arbitration lost occurred and the addresses do not match.
+ * Modified incorrect slave transmission after the master reception.
+ * Modified processing for the I/O register initialization
+ * when generating a start condition and receiving the slave address.
+ * : 17.07.2014 1.30 Added the parameters of channel 2.
+ * Deleted the parameters of PCLK.
+ * Added the parameters of the port function assignment.
+ * Changed the parameters of interrupt priority level.
+ * Added the parameters for the time out detection.
+ * : 22.09.2014 1.40 The module is updated to measure the issue that slave communication
+ * is not available after an arbitration-lost occurs and the bus is locked.
+ * The issue occurs when the following four conditions are all met.
+ * - RIIC FIT module rev. 1.30 or earlier is used.
+ * - RX device operates as both the master and the slave
+ * in multi-master communication.
+ * - An arbitration-lost is detected when communicating as the master.
+ * - Communication other than master reception or slave reception is performed.
+ * : 14.11.2014 1.50 Added RX113 support.
+ * : 09.10.2014 1.60 Added RX71M support.
+ * : 20.10.2014 1.70 Added RX231 support.
+ * : 31.10.2015 1.80 Added RX130, RX230, RX23T support.
+ * : 04.03.2016 1.90 Added RX24T support.Changed about the pin definisions.
+ * : 01.10.2016 2.00 Added RX65N support.
+ * : 02.06.2017 2.10 Added RX24U support.
+ * : 31.08.2017 2.20 Added definitions for Channel 1.
+ **********************************************************************************************************************/
+/* Guards against multiple inclusion */
+#ifndef RIIC_CONFIG_H
+ #define RIIC_CONFIG_H
+/***********************************************************************************************************************
+ Configuration Options
+ **********************************************************************************************************************/
+/* SPECIFY WHETHER TO INCLUDE CODE FOR API PARAMETER CHECKING */
+/* Setting to BSP_CFG_PARAM_CHECKING_ENABLE utilizes the system default setting */
+/* Setting to 1 includes parameter checking; 0 compiles out parameter checking */
+ #define RIIC_CFG_PARAM_CHECKING_ENABLE (1U)
+
+/* SPECIFY CHANNELS TO INCLUDE SOFTWARE SUPPORT FOR 1=included, 0=not */
+/* mcu supported channels */
+/* RX110: ch0, , */
+/* RX111: ch0, , */
+/* RX113: ch0, , */
+/* RX130: ch0, , */
+/* RX230: ch0, , */
+/* RX231: ch0, , */
+/* RX23T: ch0, , */
+/* RX24T: ch0, , */
+/* RX24U: ch0, , */
+/* RX64M: ch0, , ch2 */
+/* RX65N: ch0, ch1, ch2 */
+/* RX71M: ch0, , ch2 */
+ #define RIIC_CFG_CH0_INCLUDED (1U)
+ #define RIIC_CFG_CH1_INCLUDED (0U)
+ #define RIIC_CFG_CH2_INCLUDED (0U)
+
+/* Set RIIC bps(kbps) */
+ #define RIIC_CFG_CH0_kBPS (400U)
+ #define RIIC_CFG_CH1_kBPS (400U)
+ #define RIIC_CFG_CH2_kBPS (400U)
+
+/* Set using digital filter(Selected IIC phi cycle is filtered out) */
+/* 0 = not, 1 = one IIC phi, 2 = two IIC phi, 3 = three IIC phi, 4 = four IIC phi */
+ #define RIIC_CFG_CH0_DIGITAL_FILTER (2U)
+ #define RIIC_CFG_CH1_DIGITAL_FILTER (2U)
+ #define RIIC_CFG_CH2_DIGITAL_FILTER (2U)
+
+/* Setting to */
+/* 1: includes riic port setting processing */
+/* 0: compiles out riic port setting processing */
+ #define RIIC_CFG_PORT_SET_PROCESSING (1U)
+
+/* Set mode */
+/* 0 = single master mode, 1 = multi master mode(Master arbitration-lost detection is enabled.) */
+ #define RIIC_CFG_CH0_MASTER_MODE (1U)
+ #define RIIC_CFG_CH1_MASTER_MODE (1U)
+ #define RIIC_CFG_CH2_MASTER_MODE (1U)
+
+/* Set slave address */
+/* 0 = not, 1 = 7bit address format, 2 = 10bit address format */
+ #define RIIC_CFG_CH0_SLV_ADDR0_FORMAT (1U)
+ #define RIIC_CFG_CH0_SLV_ADDR1_FORMAT (0U)
+ #define RIIC_CFG_CH0_SLV_ADDR2_FORMAT (0U)
+
+ #define RIIC_CFG_CH0_SLV_ADDR0 (0x0025)
+ #define RIIC_CFG_CH0_SLV_ADDR1 (0x0000)
+ #define RIIC_CFG_CH0_SLV_ADDR2 (0x0000)
+
+ #define RIIC_CFG_CH1_SLV_ADDR0_FORMAT (1U)
+ #define RIIC_CFG_CH1_SLV_ADDR1_FORMAT (0U)
+ #define RIIC_CFG_CH1_SLV_ADDR2_FORMAT (0U)
+
+ #define RIIC_CFG_CH1_SLV_ADDR0 (0x0025)
+ #define RIIC_CFG_CH1_SLV_ADDR1 (0x0000)
+ #define RIIC_CFG_CH1_SLV_ADDR2 (0x0000)
+
+ #define RIIC_CFG_CH2_SLV_ADDR0_FORMAT (1U)
+ #define RIIC_CFG_CH2_SLV_ADDR1_FORMAT (0U)
+ #define RIIC_CFG_CH2_SLV_ADDR2_FORMAT (0U)
+
+ #define RIIC_CFG_CH2_SLV_ADDR0 (0x0025)
+ #define RIIC_CFG_CH2_SLV_ADDR1 (0x0000)
+ #define RIIC_CFG_CH2_SLV_ADDR2 (0x0000)
+
+/* Select General call address */
+/* 0 = not use, 1 = use(General call address detection is enabled.) */
+ #define RIIC_CFG_CH0_SLV_GCA_ENABLE (0U)
+ #define RIIC_CFG_CH1_SLV_GCA_ENABLE (0U)
+ #define RIIC_CFG_CH2_SLV_GCA_ENABLE (0U)
+
+/* This #define sets the priority level for the riic interrupt */
+/* 1 lowest, 15 highest */
+/* The following devices can not individually specify the interrupt priority level for EEI0, TEI0, EEI2, TEI2. */
+/* EEI and TEI interrupts are grouped as the BL1 interrupt in the RX64M and RX71M group. */
+ #define RIIC_CFG_CH0_RXI_INT_PRIORITY (1U)
+ #define RIIC_CFG_CH0_TXI_INT_PRIORITY (1U)
+/* The priority level of the EEI, please do not lower than the priority level of TXI and RXI */
+ #define RIIC_CFG_CH0_EEI_INT_PRIORITY (1U)
+/* The priority level of the TEI, please do not lower than the priority level of TXI and RXI */
+ #define RIIC_CFG_CH0_TEI_INT_PRIORITY (1U)
+
+ #define RIIC_CFG_CH1_RXI_INT_PRIORITY (1U)
+ #define RIIC_CFG_CH1_TXI_INT_PRIORITY (1U)
+/* The priority level of the EEI, please do not lower than the priority level of TXI and RXI */
+ #define RIIC_CFG_CH1_EEI_INT_PRIORITY (1U)
+/* The priority level of the TEI, please do not lower than the priority level of TXI and RXI */
+ #define RIIC_CFG_CH1_TEI_INT_PRIORITY (1U)
+
+ #define RIIC_CFG_CH2_RXI_INT_PRIORITY (1U)
+ #define RIIC_CFG_CH2_TXI_INT_PRIORITY (1U)
+/* The priority level of the EEI, please do not lower than the priority level of TXI and RXI */
+ #define RIIC_CFG_CH2_EEI_INT_PRIORITY (1U)
+/* The priority level of the TEI, please do not lower than the priority level of TXI and RXI */
+ #define RIIC_CFG_CH2_TEI_INT_PRIORITY (1U)
+
+/* Select Timeout function enable or disable */
+/* 0 = disable, 1 = enable */
+ #define RIIC_CFG_CH0_TMO_ENABLE (1U)
+ #define RIIC_CFG_CH1_TMO_ENABLE (1U)
+ #define RIIC_CFG_CH2_TMO_ENABLE (1U)
+
+/* Select long mode or short mode for the timeout detection time */
+/* when the timeout function is enabled. */
+/* 0 = Long mode, 1 = short mode */
+ #define RIIC_CFG_CH0_TMO_DET_TIME (0U)
+ #define RIIC_CFG_CH1_TMO_DET_TIME (0U)
+ #define RIIC_CFG_CH2_TMO_DET_TIME (0U)
+
+/* Select enable or disable the internal counter of the timeout function to count up while the */
+/* SCL line is held LOW when the timeout function is enabled. */
+/* 0 = Count is disabled, 1 = Count is enabled */
+ #define RIIC_CFG_CH0_TMO_LCNT (1U)
+ #define RIIC_CFG_CH1_TMO_LCNT (1U)
+ #define RIIC_CFG_CH2_TMO_LCNT (1U)
+
+/* Select enable or disable the internal counter of the timeout function to count up while the */
+/* SCL line is held HIGH when the timeout function is enabled. */
+/* 0 = Count is disabled, 1 = Count is enabled */
+ #define RIIC_CFG_CH0_TMO_HCNT (1U)
+ #define RIIC_CFG_CH1_TMO_HCNT (1U)
+ #define RIIC_CFG_CH2_TMO_HCNT (1U)
+
+/* Define software bus busy check counter. */
+ #define RIIC_CFG_BUS_CHECK_COUNTER (1000U) /* Counter of checking bus busy */
+
+#endif /* RIIC_CONFIG_H */
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/r_config/r_riic_rx_pin_config.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/r_config/r_riic_rx_pin_config.h
new file mode 100644
index 00000000000..096aaf913b0
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/r_config/r_riic_rx_pin_config.h
@@ -0,0 +1,69 @@
+/***********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+ * No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO
+ * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved.
+ **********************************************************************************************************************/
+/***********************************************************************************************************************
+ * File Name : r_riic_rx_pin_config_reference.h
+ * Description : Pin configures the RIIC drivers
+ **********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ * : 04.03.2016 1.90 First Release
+ * : 02.06.2017 2.10 Deleted RIIC port definitions of RIIC3.
+ **********************************************************************************************************************/
+/* Guards against multiple inclusion */
+#ifndef RIIC_PIN_CONFIG_H
+ #define RIIC_PIN_CONFIG_H
+/***********************************************************************************************************************
+ Configuration Options
+ **********************************************************************************************************************/
+/*------------------------------------------------------------------------------*/
+/* Set using port as riic port */
+/*------------------------------------------------------------------------------*/
+/* Set using port as riic port. */
+/* If you want to include the port configuration process(RIIC_CFG_PORT_SET_PROCESSING is "1"), */
+/* please choose which ports to use for the SCL/SDA of RIIC with the following setting. */
+/* Select the port group and pin used by setting
+ "R_RIIC_CFG_RIICx_SCLx_PORT (select from port group 0 to J)"
+ and "R_RIIC_CFG_RIICx_SCLx_BIT (select from pin number 0 to 7)"
+ and "R_RIIC_CFG_RIICx_SDAx_PORT (select from port group 0 to J)"
+ and "R_RIIC_CFG_RIICx_SDAx_BIT (select from pin number 0 to 7)",
+ respectively. */
+
+/* Select the ports (SCL0 and SDA0) to use in RIIC0 */
+ #define R_RIIC_CFG_RIIC0_SCL0_PORT '1' /* Port Number */
+ #define R_RIIC_CFG_RIIC0_SCL0_BIT '2' /* Bit Number */
+
+ #define R_RIIC_CFG_RIIC0_SDA0_PORT '1' /* Port Number */
+ #define R_RIIC_CFG_RIIC0_SDA0_BIT '3' /* Bit Number */
+
+/* Select the ports (SCL1 and SDA1) to use in RIIC1 */
+ #define R_RIIC_CFG_RIIC1_SCL1_PORT '2' /* Port Number */
+ #define R_RIIC_CFG_RIIC1_SCL1_BIT '1' /* Bit Number */
+
+ #define R_RIIC_CFG_RIIC1_SDA1_PORT '2' /* Port Number */
+ #define R_RIIC_CFG_RIIC1_SDA1_BIT '0' /* Bit Number */
+
+/* Select the ports (SCL2 and SDA2) to use in RIIC2 */
+ #define R_RIIC_CFG_RIIC2_SCL2_PORT '1' /* Port Number */
+ #define R_RIIC_CFG_RIIC2_SCL2_BIT '6' /* Bit Number */
+
+ #define R_RIIC_CFG_RIIC2_SDA2_PORT '1' /* Port Number */
+ #define R_RIIC_CFG_RIIC2_SDA2_BIT '7' /* Bit Number */
+
+#endif /* RIIC_PIN_CONFIG_H */
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/r_config/r_sci_iic_rx_config.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/r_config/r_sci_iic_rx_config.h
new file mode 100644
index 00000000000..b4d82ee2a3c
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/r_config/r_sci_iic_rx_config.h
@@ -0,0 +1,190 @@
+/***********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+ * No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO
+ * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
+ **********************************************************************************************************************/
+/***********************************************************************************************************************
+ * File Name : r_sci_iic_rx_config.h
+ * Description : Configures the SCI IIC drivers
+ **********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ * : 01.07.2013 1.00 First Release
+ * : 30.09.2013 1.10 Change symbol of return value and status
+ * : 01.07.2014 1.20 RX110 support added.
+ * : 22.09.2014 1.30 RX64M support added.
+ * : 01.12.2014 1.40 RX113 support added.
+ * : 15.12.2014 1.50 RX71M support added.
+ * : 27.02.2015 1.60 RX63N support added.
+ * : 29.05.2015 1.70 RX231 support added.
+ * : 31.10.2015 1.80 RX130, RX230, RX23T support added.
+ * : 04.03.2016 1.90 RX24T support added.Changed about the pin definisions.
+ * : 01.10.2016 2.00 RX65N support added.
+ * : 31.08.2017 2.20 Changed the default value of the following macro definition.
+ * - SCI_IIC_CFG_CH1_INCLUDED
+ * RX24U,RX130-512 support added.
+ **********************************************************************************************************************/
+/* Guards against multiple inclusion */
+#ifndef SCI_IIC_CONFIG_H
+ #define SCI_IIC_CONFIG_H
+/***********************************************************************************************************************
+ Configuration Options
+ **********************************************************************************************************************/
+/* SPECIFY WHETHER TO INCLUDE CODE FOR API PARAMETER CHECKING */
+/* Setting to BSP_CFG_PARAM_CHECKING_ENABLE utilizes the system default setting */
+/* Setting to 1 includes parameter checking */
+/* 0 compiles out parameter checking */
+ #define SCI_IIC_CFG_PARAM_CHECKING_ENABLE (1)
+
+/* SPECIFY CHANNELS TO INCLUDE SOFTWARE SUPPORT FOR 1=included, 0=not */
+/* mcu supported channels */
+/* RX110 : , ch1, , , , ch5, , , , , , ,ch12 */
+/* RX111 : , ch1, , , , ch5, , , , , , ,ch12 */
+/* RX113 : ch0, ch1, ch2, , , ch5, ch6, , ch8, ch9, , ,ch12 */
+/* RX130 : ch0, ch1, , , , ch5, ch6, , ch8, ch9, , ,ch12 */
+/* RX230 : ch0, ch1, , , , ch5, ch6, , ch8, ch9, , ,ch12 */
+/* RX231 : ch0, ch1, , , , ch5, ch6, , ch8, ch9, , ,ch12 */
+/* RX23T : , ch1, , , , ch5, , , , , , , */
+/* RX24T : , ch1, , , , ch5, ch6, , , , , , */
+/* RX24U : , ch1, , , , ch5, ch6, , ch8, ch9, ,ch11, */
+/* RX63N : ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7, ch8, ch9,ch10,ch11,ch12 */
+/* RX64M : ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7, , , , ,ch12 */
+/* RX65N : ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7, ch8, ch9,ch10,ch11,ch12 */
+/* RX71M : ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7, , , , ,ch12 */
+/* Please change the definition value of channel to be used to '1'. */
+ #define SCI_IIC_CFG_CH0_INCLUDED (1)
+ #define SCI_IIC_CFG_CH1_INCLUDED (0)
+ #define SCI_IIC_CFG_CH2_INCLUDED (0)
+ #define SCI_IIC_CFG_CH3_INCLUDED (0)
+ #define SCI_IIC_CFG_CH4_INCLUDED (0)
+ #define SCI_IIC_CFG_CH5_INCLUDED (0)
+ #define SCI_IIC_CFG_CH6_INCLUDED (0)
+ #define SCI_IIC_CFG_CH7_INCLUDED (0)
+ #define SCI_IIC_CFG_CH8_INCLUDED (0)
+ #define SCI_IIC_CFG_CH9_INCLUDED (0)
+ #define SCI_IIC_CFG_CH10_INCLUDED (0)
+ #define SCI_IIC_CFG_CH11_INCLUDED (0)
+ #define SCI_IIC_CFG_CH12_INCLUDED (0)
+
+/* Set SCI IIC bps */
+/* 1K = 1000, 100K= 100000, Max:384k = 384000 */
+ #define SCI_IIC_CFG_CH0_BITRATE_BPS (384000)
+ #define SCI_IIC_CFG_CH1_BITRATE_BPS (384000)
+ #define SCI_IIC_CFG_CH2_BITRATE_BPS (384000)
+ #define SCI_IIC_CFG_CH3_BITRATE_BPS (384000)
+ #define SCI_IIC_CFG_CH4_BITRATE_BPS (384000)
+ #define SCI_IIC_CFG_CH5_BITRATE_BPS (384000)
+ #define SCI_IIC_CFG_CH6_BITRATE_BPS (384000)
+ #define SCI_IIC_CFG_CH7_BITRATE_BPS (384000)
+ #define SCI_IIC_CFG_CH8_BITRATE_BPS (384000)
+ #define SCI_IIC_CFG_CH9_BITRATE_BPS (384000)
+ #define SCI_IIC_CFG_CH10_BITRATE_BPS (384000)
+ #define SCI_IIC_CFG_CH11_BITRATE_BPS (384000)
+ #define SCI_IIC_CFG_CH12_BITRATE_BPS (384000)
+
+/* SET GROUP12 (RECEIVER ERROR) INTERRUPT PRIORITY; RX63N ONLY
+ This #define sets the priority level for the interrupt that handles
+ receiver overrun, framing, and parity errors for all SCI channels
+ on the RX63N. It is ignored for all other parts.
+ */
+/* 1 lowest, 15 highest */
+ #define SCI_IIC_CFG_CH0_INT_PRIORITY (2)
+ #define SCI_IIC_CFG_CH1_INT_PRIORITY (2)
+ #define SCI_IIC_CFG_CH2_INT_PRIORITY (2)
+ #define SCI_IIC_CFG_CH3_INT_PRIORITY (2)
+ #define SCI_IIC_CFG_CH4_INT_PRIORITY (2)
+ #define SCI_IIC_CFG_CH5_INT_PRIORITY (2)
+ #define SCI_IIC_CFG_CH6_INT_PRIORITY (2)
+ #define SCI_IIC_CFG_CH7_INT_PRIORITY (2)
+ #define SCI_IIC_CFG_CH8_INT_PRIORITY (2)
+ #define SCI_IIC_CFG_CH9_INT_PRIORITY (2)
+ #define SCI_IIC_CFG_CH10_INT_PRIORITY (2)
+ #define SCI_IIC_CFG_CH11_INT_PRIORITY (2)
+ #define SCI_IIC_CFG_CH12_INT_PRIORITY (2)
+
+/* Digital noise filter (NFEN bit).
+ 0 = Noise cancellation function for the SSCLn and SSDAn input signals is disabled.
+ 1 = Noise cancellation function for the SSCLn and SSDAn input signals is enable.
+ */
+ #define SCI_IIC_CFG_CH0_DIGITAL_FILTER (1)
+ #define SCI_IIC_CFG_CH1_DIGITAL_FILTER (1)
+ #define SCI_IIC_CFG_CH2_DIGITAL_FILTER (1)
+ #define SCI_IIC_CFG_CH3_DIGITAL_FILTER (1)
+ #define SCI_IIC_CFG_CH4_DIGITAL_FILTER (1)
+ #define SCI_IIC_CFG_CH5_DIGITAL_FILTER (1)
+ #define SCI_IIC_CFG_CH6_DIGITAL_FILTER (1)
+ #define SCI_IIC_CFG_CH7_DIGITAL_FILTER (1)
+ #define SCI_IIC_CFG_CH8_DIGITAL_FILTER (1)
+ #define SCI_IIC_CFG_CH9_DIGITAL_FILTER (1)
+ #define SCI_IIC_CFG_CH10_DIGITAL_FILTER (1)
+ #define SCI_IIC_CFG_CH11_DIGITAL_FILTER (1)
+ #define SCI_IIC_CFG_CH12_DIGITAL_FILTER (1)
+
+/* Noise Filter Setting Register (NFCS bit).
+ 001 = 1 = The clock signal divided by 1 is used with the noise filter.
+ 010 = 2 = The clock signal divided by 2 is used with the noise filter.
+ 011 = 3 = The clock signal divided by 4 is used with the noise filter.
+ 100 = 4 = The clock signal divided by 8 is used with the noise filter.
+ */
+ #define SCI_IIC_CFG_CH0_FILTER_CLOCK (1)
+ #define SCI_IIC_CFG_CH1_FILTER_CLOCK (1)
+ #define SCI_IIC_CFG_CH2_FILTER_CLOCK (1)
+ #define SCI_IIC_CFG_CH3_FILTER_CLOCK (1)
+ #define SCI_IIC_CFG_CH4_FILTER_CLOCK (1)
+ #define SCI_IIC_CFG_CH5_FILTER_CLOCK (1)
+ #define SCI_IIC_CFG_CH6_FILTER_CLOCK (1)
+ #define SCI_IIC_CFG_CH7_FILTER_CLOCK (1)
+ #define SCI_IIC_CFG_CH8_FILTER_CLOCK (1)
+ #define SCI_IIC_CFG_CH9_FILTER_CLOCK (1)
+ #define SCI_IIC_CFG_CH10_FILTER_CLOCK (1)
+ #define SCI_IIC_CFG_CH11_FILTER_CLOCK (1)
+ #define SCI_IIC_CFG_CH12_FILTER_CLOCK (1)
+
+/* I2C Mode Register 1 (IICDL bit).
+ 00001 = 1 = 0 to 1 cycle
+ 00010 = 2 = 1 to 2 cycles
+ 00011 = 3 = 2 to 3 cycles
+ 00100 = 4 = 3 to 4 cycles
+ 00101 = 5 = 4 to 5 cycles
+ |
+ 11110 = 30 = 29 to 30 cycles
+ 11111 = 31 = 30 to 31 cycles
+ */
+ #define SCI_IIC_CFG_CH0_SSDA_DELAY_SELECT (18)
+ #define SCI_IIC_CFG_CH1_SSDA_DELAY_SELECT (18)
+ #define SCI_IIC_CFG_CH2_SSDA_DELAY_SELECT (18)
+ #define SCI_IIC_CFG_CH3_SSDA_DELAY_SELECT (18)
+ #define SCI_IIC_CFG_CH4_SSDA_DELAY_SELECT (18)
+ #define SCI_IIC_CFG_CH5_SSDA_DELAY_SELECT (18)
+ #define SCI_IIC_CFG_CH6_SSDA_DELAY_SELECT (18)
+ #define SCI_IIC_CFG_CH7_SSDA_DELAY_SELECT (18)
+ #define SCI_IIC_CFG_CH8_SSDA_DELAY_SELECT (18)
+ #define SCI_IIC_CFG_CH9_SSDA_DELAY_SELECT (18)
+ #define SCI_IIC_CFG_CH10_SSDA_DELAY_SELECT (18)
+ #define SCI_IIC_CFG_CH11_SSDA_DELAY_SELECT (18)
+ #define SCI_IIC_CFG_CH12_SSDA_DELAY_SELECT (18)
+
+/* Define software bus busy check counter. */
+ #define SCI_IIC_CFG_BUS_CHECK_COUNTER (1000)
+
+/* Setting to port.
+ 1 = includes sci (simple iic)port setting processing
+ 0 = compiles out sci (simple iic)port setting processing
+ */
+ #define SCI_IIC_CFG_PORT_SETTING_PROCESSING (1)
+
+#endif /* SCI_IIC_CONFIG_H */
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/r_config/r_sci_iic_rx_pin_config.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/r_config/r_sci_iic_rx_pin_config.h
new file mode 100644
index 00000000000..afa717e46f5
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/r_config/r_sci_iic_rx_pin_config.h
@@ -0,0 +1,144 @@
+/***********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+ * No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO
+ * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved.
+ **********************************************************************************************************************/
+/***********************************************************************************************************************
+ * File Name : r_sci_iic_rx_pin_config_reference.h
+ * Description : Pin configures the SCI IIC drivers
+ **********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ * : 04.03.2016 1.90 First Release
+ * : 31.08.2017 2.20 Changed default value of macro definitions, below.
+ * : - R_SCI_IIC_CFG_SCI2_SSCL2_PORT
+ * : - R_SCI_IIC_CFG_SCI2_SSDA2_PORT, R_SCI_IIC_CFG_SCI2_SSDA2_BIT
+ * : - R_SCI_IIC_CFG_SCI3_SSCL3_PORT, R_SCI_IIC_CFG_SCI3_SSCL3_BIT
+ * : - R_SCI_IIC_CFG_SCI3_SSDA3_PORT, R_SCI_IIC_CFG_SCI3_SSDA3_BIT
+ * : - R_SCI_IIC_CFG_SCI5_SSCL5_PORT, R_SCI_IIC_CFG_SCI5_SSCL5_BIT
+ * : - R_SCI_IIC_CFG_SCI5_SSDA5_PORT, R_SCI_IIC_CFG_SCI5_SSDA5_BIT
+ * : - R_SCI_IIC_CFG_SCI6_SSCL6_BIT
+ * : - R_SCI_IIC_CFG_SCI6_SSDA6_BIT
+ **********************************************************************************************************************/
+/* Guards against multiple inclusion */
+#ifndef SCI_IIC_PIN_CONFIG_H
+ #define SCI_IIC_PIN_CONFIG_H
+/***********************************************************************************************************************
+ Configuration Options
+ **********************************************************************************************************************/
+/*------------------------------------------------------------------------------*/
+/* Set using port as sci iic port */
+/*------------------------------------------------------------------------------*/
+/* Select the port group and pin used by setting
+ "R_SCI_IIC_CFG_SCIx_SSCLx_PORT (select from port group 0 to J)"
+ and "R_SCI_IIC_CFG_SCIx_SSCLx_BIT (select from pin number 0 to 7)"
+ and "R_SCI_IIC_CFG_SCIx_SSDAx_PORT (select from port group 0 to J)"
+ and "R_SCI_IIC_CFG_SCIx_SSDAx_BIT (select from pin number 0 to 7)",
+ respectively. */
+
+/* Select the ports (SSCL0 and SSDA0) to use in SCI0 */
+ #define R_SCI_IIC_CFG_SCI0_SSCL0_PORT '2' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI0_SSCL0_BIT '1' /* Bit Number */
+
+ #define R_SCI_IIC_CFG_SCI0_SSDA0_PORT '2' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI0_SSDA0_BIT '0' /* Bit Number */
+
+/* Select the ports (SSCL1 and SSDA1) to use in SCI1 */
+ #define R_SCI_IIC_CFG_SCI1_SSCL1_PORT '1' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI1_SSCL1_BIT '5' /* Bit Number */
+
+ #define R_SCI_IIC_CFG_SCI1_SSDA1_PORT '1' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI1_SSDA1_BIT '6' /* Bit Number */
+
+/* Select the ports (SSCL2 and SSDA2) to use in SCI2 */
+ #define R_SCI_IIC_CFG_SCI2_SSCL2_PORT '1' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI2_SSCL2_BIT '2' /* Bit Number */
+
+ #define R_SCI_IIC_CFG_SCI2_SSDA2_PORT '1' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI2_SSDA2_BIT '3' /* Bit Number */
+
+/* Select the ports (SSCL3 and SSDA3) to use in SCI3 */
+ #define R_SCI_IIC_CFG_SCI3_SSCL3_PORT '1' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI3_SSCL3_BIT '6' /* Bit Number */
+
+ #define R_SCI_IIC_CFG_SCI3_SSDA3_PORT '1' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI3_SSDA3_BIT '7' /* Bit Number */
+
+/* Select the ports (SSCL4 and SSDA4) to use in SCI4 */
+ #define R_SCI_IIC_CFG_SCI4_SSCL4_PORT 'B' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI4_SSCL4_BIT '0' /* Bit Number */
+
+ #define R_SCI_IIC_CFG_SCI4_SSDA4_PORT 'B' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI4_SSDA4_BIT '1' /* Bit Number */
+
+/* Select the ports (SSCL5 and SSDA5) to use in SCI5 */
+ #define R_SCI_IIC_CFG_SCI5_SSCL5_PORT 'B' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI5_SSCL5_BIT '1' /* Bit Number */
+
+ #define R_SCI_IIC_CFG_SCI5_SSDA5_PORT 'B' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI5_SSDA5_BIT '2' /* Bit Number */
+
+/* Select the ports (SSCL6 and SSDA6) to use in SCI6 */
+ #define R_SCI_IIC_CFG_SCI6_SSCL6_PORT 'B' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI6_SSCL6_BIT '1' /* Bit Number */
+
+ #define R_SCI_IIC_CFG_SCI6_SSDA6_PORT 'B' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI6_SSDA6_BIT '2' /* Bit Number */
+
+/* Select the ports (SSCL7 and SSDA7) to use in SCI7 */
+ #define R_SCI_IIC_CFG_SCI7_SSCL7_PORT '9' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI7_SSCL7_BIT '2' /* Bit Number */
+
+ #define R_SCI_IIC_CFG_SCI7_SSDA7_PORT '9' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI7_SSDA7_BIT '0' /* Bit Number */
+
+/* Select the ports (SSCL8 and SSDA8) to use in SCI8 */
+ #define R_SCI_IIC_CFG_SCI8_SSCL8_PORT 'C' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI8_SSCL8_BIT '6' /* Bit Number */
+
+ #define R_SCI_IIC_CFG_SCI8_SSDA8_PORT 'C' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI8_SSDA8_BIT '7' /* Bit Number */
+
+/* Select the ports (SSCL9 and SSDA9) to use in SCI9 */
+ #define R_SCI_IIC_CFG_SCI9_SSCL9_PORT 'B' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI9_SSCL9_BIT '6' /* Bit Number */
+
+ #define R_SCI_IIC_CFG_SCI9_SSDA9_PORT 'B' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI9_SSDA9_BIT '7' /* Bit Number */
+
+/* Select the ports (SSCL10 and SSDA10) to use in SCI10 */
+ #define R_SCI_IIC_CFG_SCI10_SSCL10_PORT '8' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI10_SSCL10_BIT '1' /* Bit Number */
+
+ #define R_SCI_IIC_CFG_SCI10_SSDA10_PORT '8' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI10_SSDA10_BIT '2' /* Bit Number */
+
+/* Select the ports (SSCL11 and SSDA11) to use in SCI11 */
+ #define R_SCI_IIC_CFG_SCI11_SSCL11_PORT '7' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI11_SSCL11_BIT '6' /* Bit Number */
+
+ #define R_SCI_IIC_CFG_SCI11_SSDA11_PORT '7' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI11_SSDA11_BIT '7' /* Bit Number */
+
+/* Select the ports (SSCL12 and SSDA12) to use in SCI12 */
+ #define R_SCI_IIC_CFG_SCI12_SSCL12_PORT 'E' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI12_SSCL12_BIT '2' /* Bit Number */
+
+ #define R_SCI_IIC_CFG_SCI12_SSDA12_PORT 'E' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI12_SSDA12_BIT '1' /* Bit Number */
+
+#endif /* SCI_IIC_PIN_CONFIG_H */
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/r_config/r_sci_rx_config.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/r_config/r_sci_rx_config.h
new file mode 100644
index 00000000000..11bf22a292b
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/r_config/r_sci_rx_config.h
@@ -0,0 +1,171 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2013-2017 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : r_sci_rx_config.h
+* Description : Configures the SCI driver
+************************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* 25.09.2013 1.00 Initial Release
+* 17.04.2014 1.20 Added comments for new RX110 support.
+* 02.07.2014 1.30 Fixed bug that caused Group12 rx errors to only be enabled for channel 2.
+* 25.11.2014 1.40 Added comments for RX113 support
+* 30.09.2015 1.70 Added comments for RX23T support
+* 01.10.2016 1.80 Added support for RX65N (comments and TX/RX FIFO THRESHOLD options)
+* 19.12.2016 1.90 Added comments for RX24U support
+* 07.03.2017 2.00 Added comments for RX130-512KB support
+***********************************************************************************************************************/
+#ifndef SCI_CONFIG_H
+#define SCI_CONFIG_H
+
+#include "platform.h"
+
+/***********************************************************************************************************************
+Configuration Options
+***********************************************************************************************************************/
+
+/* SPECIFY WHETHER TO INCLUDE CODE FOR API PARAMETER CHECKING */
+/* Setting to BSP_CFG_PARAM_CHECKING_ENABLE utilizes the system default setting */
+/* Setting to 1 includes parameter checking; 0 compiles out parameter checking */
+#define SCI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+
+/* SPECIFY WHETHER TO INCLUDE CODE FOR DIFFERENT SCI MODES */
+/* Setting an equate to 1 includes code specific to that mode. */
+#define SCI_CFG_ASYNC_INCLUDED (1)
+#define SCI_CFG_SYNC_INCLUDED (0)
+#define SCI_CFG_SSPI_INCLUDED (0)
+
+/* SPECIFY BYTE VALUE TO TRANSMIT WHILE CLOCKING IN DATA IN SSPI MODES */
+#define SCI_CFG_DUMMY_TX_BYTE (0xFF)
+
+/* SPECIFY CHANNELS TO INCLUDE SOFTWARE SUPPORT FOR 1=included, 0=not */
+/*
+ * NOTE: If using ASYNC mode, adjust BYTEQ_CFG_MAX_CTRL_BLKS in r_byteq_config.h
+ * to provide 2 queues per channel (static mode only).
+ * * = port connector RDKRX63N, RSKRX210, RSKRX11x
+ * u = channel used by the USB-UART port (G1CUSB0)
+ * a = this channel is used only for RX130-512KB
+ * RX MCU supported channels
+ *
+ * CH# 110 111 113 130 210 230 231 23T 24T 24U 63N 631 64M 71M 65N
+ * --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- ---
+ * CH0 X Xa X* X X X* X X X X
+ * CH1 X X* X* Xu X X X Xu Xu Xu X X X X X
+ * CH2 X X X X X Xu
+ * CH3 X X X X X
+ * CH4 X X X X X
+ * CH5 X X X X X X Xu X X X X X X X X
+ * CH6 X X X X X X X X X X X X
+ * CH7 X X Xu Xu X
+ * CH8 X Xa X X X X X X X
+ * CH9 X Xa X X X X X X X
+ * CH10 X X X
+ * CH11 X X X X
+ * CH12 X X X X X X X X X X X X
+*/
+
+#define SCI_CFG_CH0_INCLUDED (0)
+#define SCI_CFG_CH1_INCLUDED (0)
+#define SCI_CFG_CH2_INCLUDED (1)
+#define SCI_CFG_CH3_INCLUDED (0)
+#define SCI_CFG_CH4_INCLUDED (0)
+#define SCI_CFG_CH5_INCLUDED (0)
+#define SCI_CFG_CH6_INCLUDED (1)
+#define SCI_CFG_CH7_INCLUDED (0)
+#define SCI_CFG_CH8_INCLUDED (1)
+#define SCI_CFG_CH9_INCLUDED (0)
+#define SCI_CFG_CH10_INCLUDED (0)
+#define SCI_CFG_CH11_INCLUDED (0)
+#define SCI_CFG_CH12_INCLUDED (0)
+
+/* SPECIFY ASYNC MODE TX QUEUE BUFFER SIZES (will not allocate if chan not enabled */
+#define SCI_CFG_CH0_TX_BUFSIZ (80)
+#define SCI_CFG_CH1_TX_BUFSIZ (80)
+#define SCI_CFG_CH2_TX_BUFSIZ (1000)
+#define SCI_CFG_CH3_TX_BUFSIZ (80)
+#define SCI_CFG_CH4_TX_BUFSIZ (80)
+#define SCI_CFG_CH5_TX_BUFSIZ (80)
+#define SCI_CFG_CH6_TX_BUFSIZ (1460)
+#define SCI_CFG_CH7_TX_BUFSIZ (80)
+#define SCI_CFG_CH8_TX_BUFSIZ (80)
+#define SCI_CFG_CH9_TX_BUFSIZ (80)
+#define SCI_CFG_CH10_TX_BUFSIZ (80)
+#define SCI_CFG_CH11_TX_BUFSIZ (80)
+#define SCI_CFG_CH12_TX_BUFSIZ (80)
+
+/* SPECIFY ASYNC MODE RX QUEUE BUFFER SIZES (will not allocate if chan not enabled */
+#define SCI_CFG_CH0_RX_BUFSIZ (80)
+#define SCI_CFG_CH1_RX_BUFSIZ (80)
+#define SCI_CFG_CH2_RX_BUFSIZ (1000)
+#define SCI_CFG_CH3_RX_BUFSIZ (80)
+#define SCI_CFG_CH4_RX_BUFSIZ (80)
+#define SCI_CFG_CH5_RX_BUFSIZ (80)
+#define SCI_CFG_CH6_RX_BUFSIZ (2048)
+#define SCI_CFG_CH7_RX_BUFSIZ (80)
+#define SCI_CFG_CH8_RX_BUFSIZ (80)
+#define SCI_CFG_CH9_RX_BUFSIZ (80)
+#define SCI_CFG_CH10_RX_BUFSIZ (80)
+#define SCI_CFG_CH11_RX_BUFSIZ (80)
+#define SCI_CFG_CH12_RX_BUFSIZ (80)
+
+/*
+* ENABLE TRANSMIT END INTERRUPT (ASYNCHRONOUS)
+* This interrupt only occurs when the last bit of the last byte of data
+* has been sent and the transmitter has become idle. The interrupt calls
+* the user's callback function specified in R_SCI_Open() and passes it an
+* SCI_EVT_TEI event. A typical use of this feature is to disable an external
+* transceiver to save power. It would then be up to the user's code to
+* re-enable the transceiver before sending again. Not including this feature
+* reduces code space used by the interrupt. Note that this equate is only
+* for including the TEI code. The interrupt itself must be enabled using an
+* R_SCI_Control(hdl, SCI_CMD_EN_TEI, NULL) call.
+*/
+#define SCI_CFG_TEI_INCLUDED (1) /* 1=included, 0=not */
+
+/*
+* SET GROUP12 (RECEIVER ERROR) INTERRUPT PRIORITY; RX63N/631 ONLY
+* This #define sets the priority level for the interrupt that handles
+* receiver overrun, framing, and parity errors for all SCI channels
+* on the RX63N/631. It is ignored for all other parts.
+*/
+#define SCI_CFG_RXERR_PRIORITY (3) /* (RX63N/631 ONLY) 1 lowest, 15 highest */
+
+/*
+* SET GROUPBL0 (ERI, TEI) INTERRUPT PRIORITY; RX64M/RX71M/RX65N ONLY
+* SET GROUPBL1, GROUPAL0 (ERI,TEI) INTERRUPT PRIORITY; RX65N ONLY
+* This sets the priority level for receiver overrun, framing, and parity errors
+* as well as TEI interrupts for all SCI channels.
+*/
+#define SCI_CFG_ERI_TEI_PRIORITY (3) /* (RX64M/RX71M/RX65N ONLY) 1 lowest, 15 highest */
+
+/* ENABLE TX/RX FIFO; (SCIi supported MCU ONLY) 1=included, 0=not */
+#define SCI_CFG_CH10_FIFO_INCLUDED (0)
+#define SCI_CFG_CH11_FIFO_INCLUDED (0)
+
+/* SET TX FIFO THRESHOLD; (SCIi supported MCU ONLY) 0 lowest, 15 highest */
+/* TX FIFO THRESHOLD is invalid in Clock Synchronous Mode and Simple SPI Mode. */
+/* Set the same value for TX FIFO THRESHOLD and RX FIFO THRESHOLD in Clock Synchronous Mode and Simple SPI Mode. */
+#define SCI_CFG_CH10_TX_FIFO_THRESH (8)
+#define SCI_CFG_CH11_TX_FIFO_THRESH (8)
+
+/* SET RX FIFO THRESHOLD; (SCIi supported MCU ONLY) 1 lowest, 15 highest */
+#define SCI_CFG_CH10_RX_FIFO_THRESH (8)
+#define SCI_CFG_CH11_RX_FIFO_THRESH (8)
+
+
+#endif /* SCI_CONFIG_H */
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/r_pincfg/Pin.c b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/r_pincfg/Pin.c
new file mode 100644
index 00000000000..9bdd2583a83
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/r_pincfg/Pin.c
@@ -0,0 +1,79 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) . All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name : Pin.c
+* Version : 1.0.2
+* Device(s) : R5F565NEDxFP
+* Description : This file implements SMC pin code generation.
+* Creation Date: 2018-08-29
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Pragma directive
+***********************************************************************************************************************/
+/* Start user code for pragma. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_macrodriver.h"
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#include "r_cg_userdefine.h"
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+/* Start user code for global. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+* Function Name: R_Pins_Create
+* Description : This function initializes Smart Configurator pins
+* Arguments : None
+* Return Value : None
+***********************************************************************************************************************/
+
+void R_Pins_Create(void)
+{
+ R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_MPC);
+
+ /* Set RXD6 pin */
+ MPC.P33PFS.BYTE = 0x0AU;
+ PORT3.PMR.BYTE |= 0x08U;
+
+ /* Set RXD12 pin */
+ MPC.PE2PFS.BYTE = 0x0CU;
+ PORTE.PMR.BYTE |= 0x04U;
+
+ /* Set TXD6 pin */
+ PORT3.PODR.BYTE |= 0x04U;
+ MPC.P32PFS.BYTE = 0x0AU;
+ PORT3.PDR.BYTE |= 0x04U;
+
+ /* Set TXD12 pin */
+ PORTE.PODR.BYTE |= 0x02U;
+ MPC.PE1PFS.BYTE = 0x0CU;
+ PORTE.PDR.BYTE |= 0x02U;
+
+ R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_MPC);
+}
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/r_pincfg/Pin.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/r_pincfg/Pin.h
new file mode 100644
index 00000000000..97fef573eff
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/r_pincfg/Pin.h
@@ -0,0 +1,50 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) . All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name : Pin.h
+* Version : 1.0.2
+* Device(s) : R5F565NEDxFP
+* Description : This file implements SMC pin code generation.
+* Creation Date: 2018-08-29
+***********************************************************************************************************************/
+
+#ifndef PIN_H
+#define PIN_H
+
+/***********************************************************************************************************************
+Macro definitions (Register bit)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Global functions
+***********************************************************************************************************************/
+void R_Pins_Create(void);
+/* Start user code for function. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#endif
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/r_pincfg/r_pinset.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/r_pincfg/r_pinset.h
new file mode 100644
index 00000000000..fc669bdb499
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/r_pincfg/r_pinset.h
@@ -0,0 +1,34 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2018 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : r_pinset.h.h
+* Version : 1.0.1
+* Description : Declares all pin code headers into a single file
+* Creation Date: 2018-08-29
+***********************************************************************************************************************/
+
+#ifndef R_PINSET_H
+#define R_PINSET_H
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_sci_rx_pinset.h"
+
+#endif /* R_PINSET_H */
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/r_pincfg/r_sci_rx_pinset.c b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/r_pincfg/r_sci_rx_pinset.c
new file mode 100644
index 00000000000..0b9c987cfc2
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/r_pincfg/r_sci_rx_pinset.c
@@ -0,0 +1,79 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2018 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : r_sci_rx_pinset.c
+* Version : 1.0.2
+* Device(s) : R5F565NEDxFP
+* Tool-Chain : RXC toolchain
+* Description : Setting of port and mpc registers
+* Creation Date: 2018-08-29
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_sci_rx_pinset.h"
+#include "platform.h"
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* Function Name: R_SCI_PinSet_SCI6
+* Description : This function initializes pins for r_sci_rx module
+* Arguments : none
+* Return Value : none
+***********************************************************************************************************************/
+void R_SCI_PinSet_SCI6()
+{
+ R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_MPC);
+
+ /* Set RXD6/SMISO6 pin */
+ MPC.P33PFS.BYTE = 0x0AU;
+ PORT3.PMR.BIT.B3 = 1U;
+
+ /* Set TXD6/SMOSI6 pin */
+ MPC.P32PFS.BYTE = 0x0AU;
+ PORT3.PMR.BIT.B2 = 1U;
+
+ R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_MPC);
+}
+
+/***********************************************************************************************************************
+* Function Name: R_SCI_PinSet_SCI12
+* Description : This function initializes pins for r_sci_rx module
+* Arguments : none
+* Return Value : none
+***********************************************************************************************************************/
+void R_SCI_PinSet_SCI12()
+{
+ R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_MPC);
+
+ /* Set RXD12/SMISO12 pin */
+ MPC.PE2PFS.BYTE = 0x0CU;
+ PORTE.PMR.BIT.B2 = 1U;
+
+ /* Set TXD12/SMOSI12 pin */
+ MPC.PE1PFS.BYTE = 0x0CU;
+ PORTE.PMR.BIT.B1 = 1U;
+
+ R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_MPC);
+}
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/r_pincfg/r_sci_rx_pinset.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/r_pincfg/r_sci_rx_pinset.h
new file mode 100644
index 00000000000..59b1cd9cd0e
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-csplus/src/smc_gen/r_pincfg/r_sci_rx_pinset.h
@@ -0,0 +1,42 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2018 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : r_sci_rx_pinset.h
+* Version : 1.0.2
+* Device(s) : R5F565NEDxFP
+* Tool-Chain : RXC toolchain
+* Description : Setting of port and mpc registers
+* Creation Date: 2018-08-29
+***********************************************************************************************************************/
+
+#ifndef R_SCI_RX_H
+#define R_SCI_RX_H
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+
+void R_SCI_PinSet_SCI6();
+void R_SCI_PinSet_SCI12();
+
+#endif
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/.cproject b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/.cproject
new file mode 100644
index 00000000000..9f02ddecf4c
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/.cproject
@@ -0,0 +1,178 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/.gitignore b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/.gitignore
new file mode 100644
index 00000000000..a12093180d9
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/.gitignore
@@ -0,0 +1 @@
+/HardwareDebug/
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/.project b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/.project
new file mode 100644
index 00000000000..36e0b4ce790
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/.project
@@ -0,0 +1,423 @@
+
+
+ aws_demos
+
+
+
+
+
+ org.eclipse.cdt.managedbuilder.core.genmakebuilder
+ clean,full,incremental,
+
+
+
+
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+ full,incremental,
+
+
+
+
+
+ org.eclipse.cdt.core.cnature
+ org.eclipse.cdt.managedbuilder.core.managedBuildNature
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+
+
+
+ application_code
+ 2
+ AWS_IOT_MCU_ROOT/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/application_code
+
+
+ config_files
+ 2
+ AWS_IOT_MCU_ROOT/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/config_files
+
+
+ lib
+ 2
+ virtual:/virtual
+
+
+ application_code/common_demos
+ 2
+ virtual:/virtual
+
+
+ lib/aws
+ 2
+ virtual:/virtual
+
+
+ lib/third_party
+ 2
+ virtual:/virtual
+
+
+ src/compiler_support
+ 2
+ AWS_IOT_MCU_ROOT/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/ccrx/compiler_support
+
+
+ application_code/common_demos/include
+ 2
+ AWS_IOT_MCU_ROOT/demos/common/include
+
+
+ application_code/common_demos/source
+ 2
+ virtual:/virtual
+
+
+ lib/aws/FreeRTOS
+ 2
+ AWS_IOT_MCU_ROOT/lib/FreeRTOS
+
+
+ lib/aws/bufferpool
+ 2
+ AWS_IOT_MCU_ROOT/lib/bufferpool
+
+
+ lib/aws/crypto
+ 2
+ AWS_IOT_MCU_ROOT/lib/crypto
+
+
+ lib/aws/greengrass
+ 2
+ AWS_IOT_MCU_ROOT/lib/greengrass
+
+
+ lib/aws/include
+ 2
+ AWS_IOT_MCU_ROOT/lib/include
+
+
+ lib/aws/mqtt
+ 2
+ AWS_IOT_MCU_ROOT/lib/mqtt
+
+
+ lib/aws/ota
+ 2
+ AWS_IOT_MCU_ROOT/lib/ota/portable/renesas/rx65n-tb-uart-sx-ulpgn
+
+
+ lib/aws/pkcs11
+ 2
+ AWS_IOT_MCU_ROOT/lib/pkcs11/portable/renesas/rx65n-tb-uart-sx-ulpgn
+
+
+ lib/aws/secure_sockets
+ 2
+ AWS_IOT_MCU_ROOT/lib/secure_sockets/portable/renesas/rx65n-tb-uart-sx-ulpgn
+
+
+ lib/aws/shadow
+ 2
+ AWS_IOT_MCU_ROOT/lib/shadow
+
+
+ lib/aws/tls
+ 2
+ AWS_IOT_MCU_ROOT/lib/tls
+
+
+ lib/aws/utils
+ 2
+ AWS_IOT_MCU_ROOT/lib/utils
+
+
+ lib/aws/wifi
+ 2
+ AWS_IOT_MCU_ROOT/lib/wifi/portable/renesas/rx65n-tb-uart-sx-ulpgn
+
+
+ lib/third_party/jsmn
+ 2
+ AWS_IOT_MCU_ROOT/lib/third_party/jsmn
+
+
+ lib/third_party/mbedtls
+ 2
+ virtual:/virtual
+
+
+ lib/third_party/mcu_vendor
+ 2
+ virtual:/virtual
+
+
+ lib/third_party/pkcs11
+ 2
+ AWS_IOT_MCU_ROOT/lib/third_party/pkcs11
+
+
+ lib/third_party/tinycbor
+ 2
+ AWS_IOT_MCU_ROOT/lib/third_party/tinycbor
+
+
+ src/FIT_modified_code/r_bsp
+ 2
+ AWS_IOT_MCU_ROOT/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/ccrx/generic_rx65n/r_bsp
+
+
+ src/FIT_modified_code/r_byteq
+ 2
+ AWS_IOT_MCU_ROOT/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/r_byteq
+
+
+ src/FIT_modified_code/r_cmt_rx
+ 2
+ AWS_IOT_MCU_ROOT/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/r_cmt_rx
+
+
+ src/FIT_modified_code/r_flash_rx
+ 2
+ AWS_IOT_MCU_ROOT/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/r_flash_rx
+
+
+ src/FIT_modified_code/r_riic_rx
+ 2
+ AWS_IOT_MCU_ROOT/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/r_riic_rx
+
+
+ src/FIT_modified_code/r_sci_iic_rx
+ 2
+ AWS_IOT_MCU_ROOT/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/r_sci_iic_rx
+
+
+ src/FIT_modified_code/r_sci_rx
+ 2
+ AWS_IOT_MCU_ROOT/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/r_sci_rx
+
+
+ src/compiler_support/register_access
+ 2
+ AWS_IOT_MCU_ROOT/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/ccrx/compiler_support/register_access/rx65n
+
+
+ application_code/common_demos/include/aws_application_version.h
+ 1
+ AWS_IOT_MCU_ROOT/demos/common/include/aws_application_version.h
+
+
+ application_code/common_demos/include/aws_clientcredential_keys.h
+ 1
+ AWS_IOT_MCU_ROOT/demos/common/include/aws_clientcredential_keys.h
+
+
+ application_code/common_demos/include/aws_dev_mode_key_provisioning.h
+ 1
+ AWS_IOT_MCU_ROOT/demos/common/include/aws_dev_mode_key_provisioning.h
+
+
+ application_code/common_demos/source/aws_demo_runner.c
+ 1
+ AWS_IOT_MCU_ROOT/demos/common/demo_runner/aws_demo_runner.c
+
+
+ application_code/common_demos/source/aws_dev_mode_key_provisioning.c
+ 1
+ AWS_IOT_MCU_ROOT/demos/common/devmode_key_provisioning/aws_dev_mode_key_provisioning.c
+
+
+ application_code/common_demos/source/aws_greengrass_discovery_demo.c
+ 1
+ AWS_IOT_MCU_ROOT/demos/common/greengrass_connectivity/aws_greengrass_discovery_demo.c
+
+
+ application_code/common_demos/source/aws_hello_world.c
+ 1
+ AWS_IOT_MCU_ROOT/demos/common/mqtt/aws_hello_world.c
+
+
+ application_code/common_demos/source/aws_logging_task_dynamic_buffers.c
+ 1
+ AWS_IOT_MCU_ROOT/demos/common/logging/aws_logging_task_dynamic_buffers.c
+
+
+ application_code/common_demos/source/aws_ota_update_demo.c
+ 1
+ AWS_IOT_MCU_ROOT/demos/common/ota/aws_ota_update_demo.c
+
+
+ application_code/common_demos/source/aws_shadow_lightbulb_on_off.c
+ 1
+ AWS_IOT_MCU_ROOT/demos/common/shadow/aws_shadow_lightbulb_on_off.c
+
+
+ application_code/common_demos/source/aws_subscribe_publish_loop.c
+ 1
+ AWS_IOT_MCU_ROOT/demos/common/mqtt/aws_subscribe_publish_loop.c
+
+
+ application_code/common_demos/source/aws_tcp_echo_client_separate_tasks.c
+ 1
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+
+
+ application_code/common_demos/source/aws_tcp_echo_client_single_task.c
+ 1
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+
+
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+ 1
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+
+
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+ 1
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+
+
+ lib/aws/pkcs11/aws_pkcs11_mbedtls.c
+ 1
+ AWS_IOT_MCU_ROOT/lib/pkcs11/mbedtls/aws_pkcs11_mbedtls.c
+
+
+ lib/third_party/mbedtls/include
+ 2
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+
+
+ lib/third_party/mbedtls/source
+ 2
+ AWS_IOT_MCU_ROOT/lib/third_party/mbedtls/library
+
+
+ lib/third_party/mcu_vendor/renesas
+ 2
+ AWS_IOT_MCU_ROOT/lib/third_party/mcu_vendor/renesas
+
+
+
+
+ 1532925745925
+
+ 6
+
+ org.eclipse.ui.ide.multiFilter
+ 1.0-name-matches-false-false-aws_demos_build_path_check_and_make.bat
+
+
+
+ 1513514174593
+
+ 10
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+ 5
+
+ org.eclipse.ui.ide.multiFilter
+ 1.0-name-matches-false-false-heap_4.c
+
+
+
+ 1513515128489
+ lib/aws/FreeRTOS/portable/Renesas
+ 9
+
+ org.eclipse.ui.ide.multiFilter
+ 1.0-name-matches-false-false-RX600v2
+
+
+
+ 1564441856894
+ src/FIT_modified_code/r_flash_rx/src/targets
+ 9
+
+ org.eclipse.ui.ide.multiFilter
+ 1.0-name-matches-false-false-rx65n
+
+
+
+ 1535360922766
+ src/FIT_modified_code/r_riic_rx/src/targets
+ 9
+
+ org.eclipse.ui.ide.multiFilter
+ 1.0-name-matches-false-false-rx65n
+
+
+
+ 1535360980389
+ src/FIT_modified_code/r_sci_iic_rx/src/targets
+ 9
+
+ org.eclipse.ui.ide.multiFilter
+ 1.0-name-matches-false-false-rx65n
+
+
+
+ 1564441820170
+ src/FIT_modified_code/r_sci_rx/src/targets
+ 9
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+
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+
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+ AWS_IOT_MCU_ROOT
+ $%7BPARENT-4-PROJECT_LOC%7D
+
+
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diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/.settings/CodeGenerator/cgprojectDatas.datas b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/.settings/CodeGenerator/cgprojectDatas.datas
new file mode 100644
index 00000000000..e69de29bb2d
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/.settings/Dependency_Scan_Preferences.prefs b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/.settings/Dependency_Scan_Preferences.prefs
new file mode 100644
index 00000000000..52d4e3fd03b
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/.settings/Dependency_Scan_Preferences.prefs
@@ -0,0 +1,2 @@
+DependecyMode=ScanBuildDep
+eclipse.preferences.version=1
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/.settings/com.renesas.cdt.managedbuild.renesas.ccrx.prefs b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/.settings/com.renesas.cdt.managedbuild.renesas.ccrx.prefs
new file mode 100644
index 00000000000..e4449c99ff6
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/.settings/com.renesas.cdt.managedbuild.renesas.ccrx.prefs
@@ -0,0 +1,6 @@
+com.renesas.cdt.managedbuild.renesas.ccrx.common.option.checkRtos=unusedRtos
+com.renesas.cdt.managedbuild.renesas.ccrx.rtosConfig.option.cfgFilePath=../generate/${ArtifactName}.cfg
+com.renesas.cdt.managedbuild.renesas.ccrx.rtosConfig.option.rtosName=None
+com.renesas.cdt.managedbuild.renesas.ccrx.rtosConfig.option.rtosPath=
+com.renesas.cdt.managedbuild.renesas.ccrx.rtosConfig.option.rtosVersion=
+eclipse.preferences.version=1
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/.settings/com.renesas.smc.e2studio.qe.xml b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/.settings/com.renesas.smc.e2studio.qe.xml
new file mode 100644
index 00000000000..d3a5d74b005
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/.settings/com.renesas.smc.e2studio.qe.xml
@@ -0,0 +1,39 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/.settings/e2studio_project.prefs b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/.settings/e2studio_project.prefs
new file mode 100644
index 00000000000..dc4089142f7
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/.settings/e2studio_project.prefs
@@ -0,0 +1,2 @@
+#
+#Wed Aug 29 16:48:08 JST 2018
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/.settings/fittemp/r_sci_rx.ftl b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/.settings/fittemp/r_sci_rx.ftl
new file mode 100644
index 00000000000..62879ddbbe9
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/.settings/fittemp/r_sci_rx.ftl
@@ -0,0 +1,85 @@
+<#--
+ Copyright(C) 2015 Renesas Electronics Corporation
+ RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
+ This program must be used solely for the purpose for which it was furnished
+ by Renesas Electronics Corporation. No part of this program may be reproduced
+ or disclosed to others, in any form, without the prior written permission of
+ Renesas Electronics Corporation.
+-->
+<#-- = DECLARE FUNCTION INFORMATION HERE =================== -->
+<#--
+ (Step 1) Explanation: These variables are necessary information for the function header.
+ Please fill up or leave blank, but do not delete
+-->
+<#assign Function_Base_Name = "R_SCI_PinSet">
+<#assign Function_Description = "This function initializes pins for r_sci_rx module">
+<#assign Function_Arg = "none">
+<#assign Function_Ret = "none">
+<#assign Version = 1.00>
+
+<#-- = DECLARE FUNCTION CONTENT HERE ======================= -->
+<#--
+ (Step 2) Explanation: Function content.
+ - Macro [initialsection] :
+ Any text that goes into this section will be printed out 1 time per function
+ input [postfix] :Use this variable to add the channel number to the function base name.
+-->
+<#macro initialsection postfix>
+<#assign Function_Name = "${Function_Base_Name}${postfix}">
+<#include "lib/functionheader.ftl">
+void ${Function_Name}()
+{
+ R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_MPC);
+
+
+<#--
+ (Step 3) Explanation: Function content.
+ - Macro [peripheralpincode] : Any text that goes into this section will be printed out 1 time per peripheral
+ - input [pin] : Available info includes:
+ pin.pinName :The name of pin, eg “SSLA0”
+ pin.assignedPinName :The pin assigned to, eg “P32”
+ pin.pinMPC :The port number of assigned pin, eg “P32” has portNume = “3”
+ pin.portNum :The bit number of the assigned pin, eg “P32” has pinBitNum = “2”
+ pin.pinBitNum :The value of MPC
+-->
+<#macro peripheralpincode pin>
+
+
+<#--
+ (Step 4) Explanation: Function content.
+ - Macro [channelpincode] : Any text that goes into this section will be printed out 1 time per channel
+ - input [pin] : Same as above
+-->
+<#macro channelpincode pin>
+
+ /* Set ${pin.pinName} pin */
+ MPC.${pin.assignedPinName}PFS.BYTE = 0x${pin.pinMPC}U;
+ PORT${pin.portNum}.PMR.BIT.B${pin.pinBitNum} = 1U;
+
+
+<#macro channelpincodeextra pin postfix>
+
+
+<#--
+ (Step 5) Explanation: Function content.
+ - Macro [endsection] : Any text that goes into this section will be printed out 1 time last
+-->
+<#macro endsection>
+
+ R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_MPC);
+}
+
+
+<#--
+ (Step 6) Explanation: Header file content
+ - Macro [headerfilesection] : Any text that goes into this section will be printed out 1 time in the header file
+ - input [postfix] :Use this variable to add the channel number to the function base name.
+-->
+<#macro headerfilesection postfix>
+void ${Function_Base_Name}${postfix}();
+
+
+<#macro headerfilesectionExtra postfix>
+
+
+<#-- = END OF FILE ========================================= -->
\ No newline at end of file
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/.settings/renesasPGModel.xml b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/.settings/renesasPGModel.xml
new file mode 100644
index 00000000000..7c0780cd586
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/.settings/renesasPGModel.xml
@@ -0,0 +1,5 @@
+
+
+ LITTLE
+
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/aws_demos.scfg b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/aws_demos.scfg
new file mode 100644
index 00000000000..e74aac9eedc
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/aws_demos.scfg
@@ -0,0 +1,639 @@
+
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diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/aws_demos_build_path_check_and_make.bat b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/aws_demos_build_path_check_and_make.bat
new file mode 100644
index 00000000000..047f6e34780
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/aws_demos_build_path_check_and_make.bat
@@ -0,0 +1,11 @@
+@echo off
+rem ################################################################################
+rem # This batch file executes some preprocess for build and then executes the make
+rem ################################################################################
+
+if not exist "%~dp0..\..\..\..\lib\third_party\mcu_vendor\renesas\tools\aws_demos_build_path_check_and_make.bat" (
+ echo ERROR: Unable to find "%~dp0..\..\..\..\lib\third_party\mcu_vendor\renesas\tools\aws_demos_build_path_check_and_make.bat"
+ exit 2
+)
+
+"%~dp0..\..\..\..\lib\third_party\mcu_vendor\renesas\tools\aws_demos_build_path_check_and_make.bat" %*
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/rx65n_tb_aws HardwareDebug.launch b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/rx65n_tb_aws HardwareDebug.launch
new file mode 100644
index 00000000000..f421f100f67
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/rx65n_tb_aws HardwareDebug.launch
@@ -0,0 +1,155 @@
+
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diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/FIT_modified_code/attention!.txt b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/FIT_modified_code/attention!.txt
new file mode 100644
index 00000000000..eba837b820a
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/FIT_modified_code/attention!.txt
@@ -0,0 +1,39 @@
+Please note that the following folders in the project window of IDEs are
+so called 'linked' folders.
+
+--------------------------------------------
+Linked folders in the project window of IDEs
+--------------------------------------------
+
+src/compiler_support
+src/FIT_modified_code/r_bsp
+
+src/FIT_modified_code/r_byteq
+src/FIT_modified_code/r_cmt_rx
+src/FIT_modified_code/r_ether_rx
+src/FIT_modified_code/r_flash_rx
+src/FIT_modified_code/r_sci_rx
+
+----------------------------------------------------------
+Folders on the File System of the WINDOWS Operating System
+----------------------------------------------------------
+
+CC-RX/e2 studio & CC-RX/CS+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/ccrx/compiler_support
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/ccrx/generic_rx65n/r_bsp
+
+GNURX/e2 studio
+~~~~~~~~~~~~~~~
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/gnurx/compiler_support
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/gnurx/generic_rx65n/r_bsp
+
+All
+~~~
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/r_byteq
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/r_cmt_rx
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/r_ether_rx
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/r_flash_rx
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/r_sci_rx
+
+[EOF]
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/compiler_support/attention!.txt b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/compiler_support/attention!.txt
new file mode 100644
index 00000000000..eba837b820a
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/compiler_support/attention!.txt
@@ -0,0 +1,39 @@
+Please note that the following folders in the project window of IDEs are
+so called 'linked' folders.
+
+--------------------------------------------
+Linked folders in the project window of IDEs
+--------------------------------------------
+
+src/compiler_support
+src/FIT_modified_code/r_bsp
+
+src/FIT_modified_code/r_byteq
+src/FIT_modified_code/r_cmt_rx
+src/FIT_modified_code/r_ether_rx
+src/FIT_modified_code/r_flash_rx
+src/FIT_modified_code/r_sci_rx
+
+----------------------------------------------------------
+Folders on the File System of the WINDOWS Operating System
+----------------------------------------------------------
+
+CC-RX/e2 studio & CC-RX/CS+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/ccrx/compiler_support
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/ccrx/generic_rx65n/r_bsp
+
+GNURX/e2 studio
+~~~~~~~~~~~~~~~
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/gnurx/compiler_support
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/gnurx/generic_rx65n/r_bsp
+
+All
+~~~
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/r_byteq
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/r_cmt_rx
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/r_ether_rx
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/r_flash_rx
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/r_sci_rx
+
+[EOF]
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/UNUSED_generated_code/.placeholder b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/UNUSED_generated_code/.placeholder
new file mode 100644
index 00000000000..e69de29bb2d
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/general/r_cg_hardware_setup.c b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/general/r_cg_hardware_setup.c
new file mode 100644
index 00000000000..f167483d7da
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/general/r_cg_hardware_setup.c
@@ -0,0 +1,98 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2016, 2017 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name : r_cg_hardware_setup.c
+* Version : 1.2.0
+* Device(s) : R5F565NEDxFP
+* Description : Initialization file for code generation configurations.
+* Creation Date: 2018-08-29
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Pragma directive
+***********************************************************************************************************************/
+/* Start user code for pragma. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_macrodriver.h"
+#include "r_smc_cgc.h"
+#include "r_smc_interrupt.h"
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#include "r_cg_userdefine.h"
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+/* Start user code for global. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+* Function Name: r_undefined_exception
+* Description : This function is undefined interrupt service routine
+* Arguments : None
+* Return Value : None
+***********************************************************************************************************************/
+
+void r_undefined_exception(void)
+{
+ /* Start user code for r_undefined_exception. Do not edit comment generated here */
+ /* End user code. Do not edit comment generated here */
+}
+
+/***********************************************************************************************************************
+* Function Name: R_Systeminit
+* Description : This function initializes every configuration
+* Arguments : None
+* Return Value : None
+***********************************************************************************************************************/
+
+void R_Systeminit(void)
+{
+ /* Enable writing to registers related to operating modes, LPC, CGC and software reset */
+ SYSTEM.PRCR.WORD = 0xA50BU;
+
+ /* Enable writing to MPC pin function control registers */
+ MPC.PWPR.BIT.B0WI = 0U;
+ MPC.PWPR.BIT.PFSWE = 1U;
+
+ /* Initialize clocks settings */
+ R_CGC_Create();
+
+ /* Set interrupt settings */
+ R_Interrupt_Create();
+
+ /* Register undefined interrupt */
+ R_BSP_InterruptWrite(BSP_INT_SRC_UNDEFINED_INTERRUPT,(bsp_int_cb_t)r_undefined_exception);
+
+ /* Disable writing to MPC pin function control registers */
+ MPC.PWPR.BIT.PFSWE = 0U;
+ MPC.PWPR.BIT.B0WI = 1U;
+
+ /* Enable protection */
+ SYSTEM.PRCR.WORD = 0xA500U;
+}
+
+/* Start user code for adding. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/general/r_cg_macrodriver.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/general/r_cg_macrodriver.h
new file mode 100644
index 00000000000..44eb749a951
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/general/r_cg_macrodriver.h
@@ -0,0 +1,82 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2016, 2017 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name : r_cg_macrodriver.h
+* Version : 1.2.0
+* Device(s) : R5F565NEDxFP
+* Description : Macro header file for code generation.
+* Creation Date: 2018-08-29
+***********************************************************************************************************************/
+
+#ifndef MODULEID_H
+#define MODULEID_H
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "platform.h"
+#include "r_smc_interrupt.h"
+#include
+
+/***********************************************************************************************************************
+Macro definitions (Register bit)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+#ifndef __TYPEDEF__
+
+/* Status list definition */
+#define MD_STATUSBASE (0x00U)
+#define MD_OK (MD_STATUSBASE + 0x00U) /* register setting OK */
+#define MD_SPT (MD_STATUSBASE + 0x01U) /* IIC stop */
+#define MD_NACK (MD_STATUSBASE + 0x02U) /* IIC no ACK */
+#define MD_BUSY1 (MD_STATUSBASE + 0x03U) /* busy 1 */
+#define MD_BUSY2 (MD_STATUSBASE + 0x04U) /* busy 2 */
+
+/* Error list definition */
+#define MD_ERRORBASE (0x80U)
+#define MD_ERROR (MD_ERRORBASE + 0x00U) /* error */
+#define MD_ARGERROR (MD_ERRORBASE + 0x01U) /* error argument input error */
+#define MD_ERROR1 (MD_ERRORBASE + 0x02U) /* error 1 */
+#define MD_ERROR2 (MD_ERRORBASE + 0x03U) /* error 2 */
+#define MD_ERROR3 (MD_ERRORBASE + 0x04U) /* error 3 */
+#define MD_ERROR4 (MD_ERRORBASE + 0x05U) /* error 4 */
+#define MD_ERROR5 (MD_ERRORBASE + 0x06U) /* error 5 */
+
+#endif
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+#ifndef __TYPEDEF__
+ typedef unsigned short MD_STATUS;
+ #define __TYPEDEF__
+#endif
+
+/***********************************************************************************************************************
+Global functions
+***********************************************************************************************************************/
+void R_Systeminit(void);
+/* Start user code for function. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#endif
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/general/r_cg_userdefine.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/general/r_cg_userdefine.h
new file mode 100644
index 00000000000..7be043a1a7e
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/general/r_cg_userdefine.h
@@ -0,0 +1,61 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2016, 2017 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name : r_cg_userdefine.h
+* Version : 1.2.0
+* Device(s) : R5F565NEDxFP
+* Description : User header file for code generation.
+* Creation Date: 2018-08-29
+***********************************************************************************************************************/
+
+#ifndef CG_USER_DEF_H
+#define CG_USER_DEF_H
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Macro definitions (Register bit)
+***********************************************************************************************************************/
+/* Start user code for register. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+/* Start user code for macro define. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+/* Start user code for type define. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Global functions
+***********************************************************************************************************************/
+/* Start user code for function. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#endif
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/general/r_smc_cgc.c b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/general/r_smc_cgc.c
new file mode 100644
index 00000000000..44624e06a58
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/general/r_smc_cgc.c
@@ -0,0 +1,45 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2016, 2017 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name : r_smc_cgc.c
+* Version : 1.1.2
+* Device(s) : R5F565NEDxFP
+* Description : This file implements cgc setting
+* Creation Date: 2018-08-29
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_macrodriver.h"
+#include "r_smc_cgc.h"
+#include "platform.h"
+
+/***********************************************************************************************************************
+* Function Name: R_CGC_Create
+* Description : This function Used to initializes the clock generator
+* Arguments : None
+* Return Value : None
+***********************************************************************************************************************/
+
+void R_CGC_Create(void)
+{
+
+ R_CGC_Create_UserInit();
+}
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/general/r_smc_cgc.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/general/r_smc_cgc.h
new file mode 100644
index 00000000000..791faeaa094
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/general/r_smc_cgc.h
@@ -0,0 +1,217 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2016, 2017 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name : r_smc_cgc.h
+* Version : 1.1.2
+* Device(s) : R5F565NEDxFP
+* Description : This file implements cgc setting.
+* Creation Date: 2018-08-29
+***********************************************************************************************************************/
+
+#ifndef SMC_CGC_H
+#define SMC_CGC_H
+
+/***********************************************************************************************************************
+Macro definitions (Register bit)
+***********************************************************************************************************************/
+/*
+ System Clock Control Register (SCKCR)
+*/
+/* Peripheral Module Clock D (PCLKD) */
+#define _00000000_CGC_PCLKD_DIV_1 (0x00000000UL) /* x1 */
+#define _00000001_CGC_PCLKD_DIV_2 (0x00000001UL) /* x1/2 */
+#define _00000002_CGC_PCLKD_DIV_4 (0x00000002UL) /* x1/4 */
+#define _00000003_CGC_PCLKD_DIV_8 (0x00000003UL) /* x1/8 */
+#define _00000004_CGC_PCLKD_DIV_16 (0x00000004UL) /* x1/16 */
+#define _00000005_CGC_PCLKD_DIV_32 (0x00000005UL) /* x1/32 */
+#define _00000006_CGC_PCLKD_DIV_64 (0x00000006UL) /* x1/64 */
+/* Peripheral Module Clock C (PCLKC) */
+#define _00000000_CGC_PCLKC_DIV_1 (0x00000000UL) /* x1 */
+#define _00000010_CGC_PCLKC_DIV_2 (0x00000010UL) /* x1/2 */
+#define _00000020_CGC_PCLKC_DIV_4 (0x00000020UL) /* x1/4 */
+#define _00000030_CGC_PCLKC_DIV_8 (0x00000030UL) /* x1/8 */
+#define _00000040_CGC_PCLKC_DIV_16 (0x00000040UL) /* x1/16 */
+#define _00000050_CGC_PCLKC_DIV_32 (0x00000050UL) /* x1/32 */
+#define _00000060_CGC_PCLKC_DIV_64 (0x00000060UL) /* x1/64 */
+/* Peripheral Module Clock B (PCLKB) */
+#define _00000000_CGC_PCLKB_DIV_1 (0x00000000UL) /* x1 */
+#define _00000100_CGC_PCLKB_DIV_2 (0x00000100UL) /* x1/2 */
+#define _00000200_CGC_PCLKB_DIV_4 (0x00000200UL) /* x1/4 */
+#define _00000300_CGC_PCLKB_DIV_8 (0x00000300UL) /* x1/8 */
+#define _00000400_CGC_PCLKB_DIV_16 (0x00000400UL) /* x1/16 */
+#define _00000500_CGC_PCLKB_DIV_32 (0x00000500UL) /* x1/32 */
+#define _00000600_CGC_PCLKB_DIV_64 (0x00000600UL) /* x1/64 */
+/* Peripheral Module Clock A (PCLKA) */
+#define _00000000_CGC_PCLKA_DIV_1 (0x00000000UL) /* x1 */
+#define _00001000_CGC_PCLKA_DIV_2 (0x00001000UL) /* x1/2 */
+#define _00002000_CGC_PCLKA_DIV_4 (0x00002000UL) /* x1/4 */
+#define _00003000_CGC_PCLKA_DIV_8 (0x00003000UL) /* x1/8 */
+#define _00004000_CGC_PCLKA_DIV_16 (0x00004000UL) /* x1/16 */
+#define _00005000_CGC_PCLKA_DIV_32 (0x00005000UL) /* x1/32 */
+#define _00006000_CGC_PCLKA_DIV_64 (0x00006000UL) /* x1/64 */
+/* External Bus Clock (BCLK) */
+#define _00000000_CGC_BCLK_DIV_1 (0x00000000UL) /* x1 */
+#define _00010000_CGC_BCLK_DIV_2 (0x00010000UL) /* x1/2 */
+#define _00020000_CGC_BCLK_DIV_4 (0x00020000UL) /* x1/4 */
+#define _00030000_CGC_BCLK_DIV_8 (0x00030000UL) /* x1/8 */
+#define _00040000_CGC_BCLK_DIV_16 (0x00040000UL) /* x1/16 */
+#define _00050000_CGC_BCLK_DIV_32 (0x00050000UL) /* x1/32 */
+#define _00060000_CGC_BCLK_DIV_64 (0x00060000UL) /* x1/64 */
+/* System Clock (ICLK) */
+#define _00000000_CGC_ICLK_DIV_1 (0x00000000UL) /* x1 */
+#define _01000000_CGC_ICLK_DIV_2 (0x01000000UL) /* x1/2 */
+#define _02000000_CGC_ICLK_DIV_4 (0x02000000UL) /* x1/4 */
+#define _03000000_CGC_ICLK_DIV_8 (0x03000000UL) /* x1/8 */
+#define _04000000_CGC_ICLK_DIV_16 (0x04000000UL) /* x1/16 */
+#define _05000000_CGC_ICLK_DIV_32 (0x05000000UL) /* x1/32 */
+#define _06000000_CGC_ICLK_DIV_64 (0x06000000UL) /* x1/64 */
+/* System Clock (FCLK) */
+#define _00000000_CGC_FCLK_DIV_1 (0x00000000UL) /* x1 */
+#define _10000000_CGC_FCLK_DIV_2 (0x10000000UL) /* x1/2 */
+#define _20000000_CGC_FCLK_DIV_4 (0x20000000UL) /* x1/4 */
+#define _30000000_CGC_FCLK_DIV_8 (0x30000000UL) /* x1/8 */
+#define _40000000_CGC_FCLK_DIV_16 (0x40000000UL) /* x1/16 */
+#define _50000000_CGC_FCLK_DIV_32 (0x50000000UL) /* x1/32 */
+#define _60000000_CGC_FCLK_DIV_64 (0x60000000UL) /* x1/64 */
+
+/*
+ System Clock Control Register 2 (SCKCR2)
+*/
+#define _0010_CGC_UCLK_DIV_1 (0x0010U) /* x1/2 */
+#define _0020_CGC_UCLK_DIV_3 (0x0020U) /* x1/3 */
+#define _0030_CGC_UCLK_DIV_4 (0x0030U) /* x1/4 */
+#define _0040_CGC_UCLK_DIV_5 (0x0040U) /* x1/5 */
+#define _0001_SCKCR2_BIT0 (0x0001U) /* RESERVE BIT0 */
+
+/*
+ System Clock Control Register 3 (SCKCR3)
+*/
+#define _0000_CGC_CLOCKSOURCE_LOCO (0x0000U) /* LOCO */
+#define _0100_CGC_CLOCKSOURCE_HOCO (0x0100U) /* HOCO */
+#define _0200_CGC_CLOCKSOURCE_MAINCLK (0x0200U) /* Main clock oscillator */
+#define _0300_CGC_CLOCKSOURCE_SUBCLK (0x0300U) /* Sub-clock oscillator */
+#define _0400_CGC_CLOCKSOURCE_PLL (0x0400U) /* PLL circuit */
+
+/*
+ PLL Control Register (PLLCR)
+*/
+/* PLL Input Frequency Division Ratio Select (PLIDIV[1:0]) */
+#define _0000_CGC_PLL_FREQ_DIV_1 (0x0000U) /* x1 */
+#define _0001_CGC_PLL_FREQ_DIV_2 (0x0001U) /* x1/2 */
+#define _0002_CGC_PLL_FREQ_DIV_3 (0x0002U) /* x1/3 */
+/* PLL Clock Source Select (PLLSRCSEL) */
+#define _0000_CGC_PLL_SOURCE_MAIN (0x0000U) /* Main clock oscillator */
+#define _0010_CGC_PLL_SOURCE_HOCO (0x0010U) /* HOCO */
+/* Frequency Multiplication Factor Select (STC[5:0]) */
+#define _1300_CGC_PLL_FREQ_MUL_10_0 (0x1300U) /* x10.0 */
+#define _1400_CGC_PLL_FREQ_MUL_10_5 (0x1400U) /* x10.5 */
+#define _1500_CGC_PLL_FREQ_MUL_11_0 (0x1500U) /* x11.0 */
+#define _1600_CGC_PLL_FREQ_MUL_11_5 (0x1600U) /* x11.5 */
+#define _1700_CGC_PLL_FREQ_MUL_12_0 (0x1700U) /* x12.0 */
+#define _1800_CGC_PLL_FREQ_MUL_12_5 (0x1800U) /* x12.5 */
+#define _1900_CGC_PLL_FREQ_MUL_13_0 (0x1900U) /* x13.0 */
+#define _1A00_CGC_PLL_FREQ_MUL_13_5 (0x1A00U) /* x13.5 */
+#define _1B00_CGC_PLL_FREQ_MUL_14_0 (0x1B00U) /* x14.0 */
+#define _1C00_CGC_PLL_FREQ_MUL_14_5 (0x1C00U) /* x14.5 */
+#define _1D00_CGC_PLL_FREQ_MUL_15_0 (0x1D00U) /* x15.0 */
+#define _1E00_CGC_PLL_FREQ_MUL_15_5 (0x1E00U) /* x15.5 */
+#define _1F00_CGC_PLL_FREQ_MUL_16_0 (0x1F00U) /* x16.0 */
+#define _2000_CGC_PLL_FREQ_MUL_16_5 (0x2000U) /* x16.5 */
+#define _2100_CGC_PLL_FREQ_MUL_17_0 (0x2100U) /* x17.0 */
+#define _2200_CGC_PLL_FREQ_MUL_17_5 (0x2200U) /* x17.5 */
+#define _2300_CGC_PLL_FREQ_MUL_18_0 (0x2300U) /* x18.0 */
+#define _2400_CGC_PLL_FREQ_MUL_18_5 (0x2400U) /* x18.5 */
+#define _2500_CGC_PLL_FREQ_MUL_19_0 (0x2500U) /* x19.0 */
+#define _2600_CGC_PLL_FREQ_MUL_19_5 (0x2600U) /* x19.5 */
+#define _2700_CGC_PLL_FREQ_MUL_20_0 (0x2700U) /* x20.0 */
+#define _2800_CGC_PLL_FREQ_MUL_20_5 (0x2800U) /* x20.5 */
+#define _2900_CGC_PLL_FREQ_MUL_21_0 (0x2900U) /* x21.0 */
+#define _2A00_CGC_PLL_FREQ_MUL_21_5 (0x2A00U) /* x21.5 */
+#define _2B00_CGC_PLL_FREQ_MUL_22_0 (0x2B00U) /* x22.0 */
+#define _2C00_CGC_PLL_FREQ_MUL_22_5 (0x2C00U) /* x22.5 */
+#define _2D00_CGC_PLL_FREQ_MUL_23_0 (0x2D00U) /* x23.0 */
+#define _2E00_CGC_PLL_FREQ_MUL_23_5 (0x2E00U) /* x23.5 */
+#define _2F00_CGC_PLL_FREQ_MUL_24_0 (0x2F00U) /* x24.0 */
+#define _3000_CGC_PLL_FREQ_MUL_24_5 (0x3000U) /* x24.5 */
+#define _3100_CGC_PLL_FREQ_MUL_25_0 (0x3100U) /* x25.0 */
+#define _3200_CGC_PLL_FREQ_MUL_25_5 (0x3200U) /* x25.5 */
+#define _3300_CGC_PLL_FREQ_MUL_26_0 (0x3300U) /* x26.0 */
+#define _3400_CGC_PLL_FREQ_MUL_26_5 (0x3400U) /* x26.5 */
+#define _3500_CGC_PLL_FREQ_MUL_27_0 (0x3500U) /* x27.0 */
+#define _3600_CGC_PLL_FREQ_MUL_27_5 (0x3600U) /* x27.5 */
+#define _3700_CGC_PLL_FREQ_MUL_28_0 (0x3700U) /* x28.0 */
+#define _3800_CGC_PLL_FREQ_MUL_28_5 (0x3800U) /* x28.5 */
+#define _3900_CGC_PLL_FREQ_MUL_29_0 (0x3900U) /* x29.0 */
+#define _3A00_CGC_PLL_FREQ_MUL_29_5 (0x3A00U) /* x29.5 */
+#define _3B00_CGC_PLL_FREQ_MUL_30_0 (0x3B00U) /* x30.0 */
+
+/*
+ Oscillation Stop Detection Control Register (OSTDCR)
+*/
+/* Oscillation Stop Detection Interrupt Enable (OSTDIE) */
+#define _00_CGC_OSC_STOP_INT_DISABLE (0x00U) /* The oscillation stop detection interrupt is disabled */
+#define _01_CGC_OSC_STOP_INT_ENABLE (0x01U) /* The oscillation stop detection interrupt is enabled */
+/* Oscillation Stop Detection Function Enable (OSTDE) */
+#define _00_CGC_OSC_STOP_DISABLE (0x00U) /* Oscillation stop detection function is disabled */
+#define _80_CGC_OSC_STOP_ENABLE (0x80U) /* Oscillation stop detection function is enabled */
+
+/*
+ High-Speed On-Chip Oscillator Control Register 2 (HOCOCR2)
+*/
+/* HOCO Frequency Setting (HCFRQ[1:0]) */
+#define _00_CGC_HOCO_CLK_16 (0x00U) /* 16 MHz */
+#define _01_CGC_HOCO_CLK_18 (0x01U) /* 18 MHz */
+#define _02_CGC_HOCO_CLK_20 (0x02U) /* 20 MHz */
+
+/*
+ Main Clock Oscillator Forced Oscillation Control Register (MOFCR)
+*/
+/* Main Oscillator Drive Capability 2 Switching (MODRV2[1:0]) */
+#define _00_CGC_MAINOSC_UNDER24M (0x00U) /* 20.1 to 24 MHz */
+#define _10_CGC_MAINOSC_UNDER20M (0x10U) /* 16.1 to 20 MHz */
+#define _20_CGC_MAINOSC_UNDER16M (0x20U) /* 8.1 to 16 MHz */
+#define _30_CGC_MAINOSC_EQUATE8M (0x30U) /* 8 MHz */
+/* Main Clock Oscillator Switch (MOSEL) */
+#define _00_CGC_MAINOSC_RESONATOR (0x00U) /* Resonator */
+#define _40_CGC_MAINOSC_EXTERNAL (0x40U) /* External oscillator input */
+
+/*
+ RTC Control Register 4 (RCR4)
+*/
+/* Count source select */
+#define _00_RTC_SOURCE_SELECT_SUB (0x00U) /* Select sub-clock oscillator */
+#define _01_RTC_SOURCE_SELECT_MAIN_FORCED (0x01U) /* Select main clock oscillator */
+#define _53_CGC_MOSCWTCR_VALUE (0x53U) /* Main Clock Oscillator Wait Time */
+#define _21_CGC_SOSCWTCR_VALUE (0x21U) /* Sub-Clock Oscillator Wait Time */
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Global functions
+***********************************************************************************************************************/
+void R_CGC_Create(void);
+void R_CGC_Create_UserInit();
+#endif
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/general/r_smc_cgc_user.c b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/general/r_smc_cgc_user.c
new file mode 100644
index 00000000000..6074233aed9
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/general/r_smc_cgc_user.c
@@ -0,0 +1,63 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2016, 2017 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name : r_smc_cgc_user.c
+* Version : 1.1.2
+* Device(s) : R5F565NEDxFP
+* Description : None
+* Creation Date: 2018-08-29
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Pragma directive
+***********************************************************************************************************************/
+/* Start user code for pragma. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_macrodriver.h"
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#include "r_cg_userdefine.h"
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+/* Start user code for global. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+* Function Name: R_CGC_Create_UserInit
+* Description : This function adds user code after initializing CGC
+* Arguments : None
+* Return Value : None
+***********************************************************************************************************************/
+
+void R_CGC_Create_UserInit(void)
+{
+ /* Start user code for code init. Do not edit comment generated here */
+ /* End user code. Do not edit comment generated here */
+}
+
+/* Start user code for adding. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/general/r_smc_entry.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/general/r_smc_entry.h
new file mode 100644
index 00000000000..091e32445c4
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/general/r_smc_entry.h
@@ -0,0 +1,54 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2016, 2017 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name : r_smc_entry.h
+* Version : 1.2.0
+* Device(s) : R5F565NEDxFP
+* Description : SMC platform header file.
+* Creation Date: 2018-08-29
+***********************************************************************************************************************/
+
+#ifndef SMC_PLATFORM_H
+#define SMC_PLATFORM_H
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_macrodriver.h"
+
+/***********************************************************************************************************************
+Macro definitions (Register bit)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Global functions
+***********************************************************************************************************************/
+/* Start user code for function. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#endif
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/general/r_smc_interrupt.c b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/general/r_smc_interrupt.c
new file mode 100644
index 00000000000..00fdf5e63b4
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/general/r_smc_interrupt.c
@@ -0,0 +1,44 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2016, 2017 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name : r_smc_interrupt.c
+* Version : 1.1.0
+* Device(s) : R5F565NEDxFP
+* Description : This file implements interrupt setting
+* Creation Date: 2018-08-29
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_smc_interrupt.h"
+#include "platform.h"
+
+/***********************************************************************************************************************
+* Function Name: R_Interrupt_Create
+* Description : This function Used to set the fast interrupt or group interrupt
+* Arguments : None
+* Return Value : None
+***********************************************************************************************************************/
+
+void R_Interrupt_Create(void)
+{
+ /* No fast interrupt and group settings have been configured in the Interrupts tab. */
+}
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/general/r_smc_interrupt.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/general/r_smc_interrupt.h
new file mode 100644
index 00000000000..c4604d3d495
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/general/r_smc_interrupt.h
@@ -0,0 +1,292 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2016, 2017 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name : r_smc_interrupt.h
+* Version : 1.1.0
+* Device(s) : R5F565NEDxFP
+* Description : This file implements interrupt setting.
+* Creation Date: 2018-08-29
+***********************************************************************************************************************/
+
+#ifndef SMC_INTERRUPT_H
+#define SMC_INTERRUPT_H
+
+/***********************************************************************************************************************
+Macro definitions (Register bit)
+***********************************************************************************************************************/
+
+/* Priority level of interrupt source.
+ * These macro definitions are used to set the IPR register directly
+ */
+#define _00_ICU_PRIORITY_LEVEL0 (0x00U) /* Level 0 (disabled) */
+#define _01_ICU_PRIORITY_LEVEL1 (0x01U) /* Level 1 */
+#define _02_ICU_PRIORITY_LEVEL2 (0x02U) /* Level 2 */
+#define _03_ICU_PRIORITY_LEVEL3 (0x03U) /* Level 3 */
+#define _04_ICU_PRIORITY_LEVEL4 (0x04U) /* Level 4 */
+#define _05_ICU_PRIORITY_LEVEL5 (0x05U) /* Level 5 */
+#define _06_ICU_PRIORITY_LEVEL6 (0x06U) /* Level 6 */
+#define _07_ICU_PRIORITY_LEVEL7 (0x07U) /* Level 7 */
+#define _08_ICU_PRIORITY_LEVEL8 (0x08U) /* Level 8 */
+#define _09_ICU_PRIORITY_LEVEL9 (0x09U) /* Level 9 */
+#define _0A_ICU_PRIORITY_LEVEL10 (0x0AU) /* Level 10 */
+#define _0B_ICU_PRIORITY_LEVEL11 (0x0BU) /* Level 11 */
+#define _0C_ICU_PRIORITY_LEVEL12 (0x0CU) /* Level 12 */
+#define _0D_ICU_PRIORITY_LEVEL13 (0x0DU) /* Level 13 */
+#define _0E_ICU_PRIORITY_LEVEL14 (0x0EU) /* Level 14 */
+#define _0F_ICU_PRIORITY_LEVEL15 (0x0FU) /* Level 15 */
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+#define FAST_INTERRUPT_VECTOR (0)
+
+/* The macro definitions below list the full set of priority levels as selected in the Interrupts tab
+ * Please do not modify this file manually
+ */
+#define ICU_BSC_BUSERR_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_RAM_RAMERR_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_FCU_FIFERR_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_FCU_FRDYI_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_SWINT2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_SWINT_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CMT0_CMI0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CMT1_CMI1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CMTW0_CMWI0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CMTW1_CMWI1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_USB0_D0FIFO0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_USB0_D1FIFO0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_RSPI0_SPRI0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_RSPI0_SPTI0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_RSPI1_SPRI1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_RSPI1_SPTI1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_QSPI_SPRI_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_QSPI_SPTI_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SDHI_SBFAI_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MMCIF_MBFAI_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_RIIC1_RXI1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_RIIC1_TXI1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_RIIC0_RXI0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_RIIC0_TXI0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_RIIC2_RXI2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_RIIC2_TXI2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI0_RXI0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI0_TXI0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI1_RXI1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI1_TXI1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI2_RXI2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI2_TXI2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_IRQ0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_IRQ1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_IRQ2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_IRQ3_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_IRQ4_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_IRQ5_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_IRQ6_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_IRQ7_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_IRQ8_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_IRQ9_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_IRQ10_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_IRQ11_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_IRQ12_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_IRQ13_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_IRQ14_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_IRQ15_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI3_RXI3_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI3_TXI3_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI4_RXI4_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI4_TXI4_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI5_RXI5_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI5_TXI5_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI6_RXI6_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI6_TXI6_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_LVD1_LVD1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_LVD2_LVD2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_USB0_USBR0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_RTC_ALM_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_RTC_PRD_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_IWDT_IWUNI_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_WDT_WUNI_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_PDC_PCDFI_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI7_RXI7_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI7_TXI7_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI8_RXI8_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI8_TXI8_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI9_RXI9_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI9_TXI9_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI10_RXI10_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI10_TXI10_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_GROUPBE0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_GROUPBL2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_RSPI2_SPRI2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_RSPI2_SPTI2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_GROUPBL0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_GROUPBL1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_GROUPAL0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_GROUPAL1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI11_RXI11_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI11_TXI11_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI12_RXI12_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI12_TXI12_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_DMAC_DMAC0I_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_DMAC_DMAC1I_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_DMAC_DMAC2I_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_DMAC_DMAC3I_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_DMAC_DMAC74I_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_OST_OSTDI_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_EXDMAC_EXDMAC0I_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_EXDMAC_EXDMAC1I_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CMT2_CMI2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CMT3_CMI3_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU0_TGI0A_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU0_TGI0B_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU0_TGI0C_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU0_TGI0D_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU0_TCI0V_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU1_TGI1B_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU1_TCI1V_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU1_TCI1U_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU2_TGI2A_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU2_TGI2B_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU2_TCI2V_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU2_TCI2U_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU3_TGI3A_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU3_TGI3B_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU1_TGI1A_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU3_TGI3C_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TMR0_CMIA0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TMR0_CMIB0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TMR0_OVI0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TMR1_CMIA1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TMR1_CMIB1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TMR1_OVI1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TMR2_CMIA2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TMR2_CMIB2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TMR2_OVI2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TMR3_CMIA3_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TMR3_CMIB3_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TMR3_OVI3_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU3_TGI3D_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU3_TCI3V_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU4_TGI4A_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU4_TGI4B_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU4_TCI4V_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU4_TCI4U_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU5_TGI5A_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU5_TGI5B_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU5_TCI5V_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU5_TCI5U_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CMTW0_IC0I0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CMTW0_IC1I0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CMTW0_OC0I0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CMTW0_OC1I0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CMTW1_IC0I1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CMTW1_IC1I1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CMTW1_OC0I1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CMTW1_OC1I1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_RTC_CUP_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CAN0_RXF0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CAN0_TXF0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CAN0_RXM0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CAN0_TXM0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CAN1_RXF1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CAN1_TXF1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CAN1_RXM1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CAN1_TXM1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_USB0_USBI0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_S12AD_S12ADI_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_S12AD_S12GBADI_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_S12AD_S12GCADI_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_S12AD1_S12ADI1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_S12AD1_S12GBADI1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_S12AD1_S12GCADI1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_PERIB_INTB192_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ELC_ELSR18I_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ELC_ELSR19I_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TSIP_PROC_BUSY_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TSIP_ROMOK_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TSIP_LONG_PLG_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TSIP_TEST_BUSY_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TSIP_WRRDY0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TSIP_WRRDY1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TSIP_WRRDY4_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TSIP_RDRDY0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TSIP_RDRDY1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TSIP_INTEGRATE_WRRDY_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TSIP_INTEGRATE_RDRDY_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_PERIB_INTB206_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_PERIB_INTB207_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU1_TGIA1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU0_TGIA0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU0_TGIB0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU0_TGIC0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU0_TGID0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU0_TCIV0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU0_TGIE0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU0_TGIF0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU1_TGIB1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU1_TCIV1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU1_TCIU1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU2_TGIA2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU2_TGIB2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU2_TCIV2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU2_TCIU2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU3_TGIA3_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU3_TGIB3_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU3_TGIC3_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU3_TGID3_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU3_TCIV3_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU4_TGIA4_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU4_TGIB4_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU4_TGIC4_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU4_TGID4_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU4_TCIV4_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU5_TGIU5_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU5_TGIV5_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU5_TGIW5_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU6_TGIA6_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU6_TGIB6_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU6_TGIC6_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU6_TGID6_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU6_TCIV6_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU7_TGIA7_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU7_TGIB7_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU7_TGIC7_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU7_TGID7_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU7_TCIV7_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU8_TGIA8_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU8_TGIB8_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU8_TGIC8_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU8_TGID8_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU8_TCIV8_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_PERIA_INTA251_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_PERIA_INTA252_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_PERIA_INTA253_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_PERIA_INTA254_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_PERIA_INTA255_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Global functions
+***********************************************************************************************************************/
+void R_Interrupt_Create(void);
+#endif
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/r_config/r_bsp_config.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/r_config/r_bsp_config.h
new file mode 100644
index 00000000000..3df1e11064f
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/r_config/r_bsp_config.h
@@ -0,0 +1,595 @@
+/* Generated configuration header file - do not edit */
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2017 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : r_bsp_config_reference.h
+* Device(s) : RX65N
+* Description : The file r_bsp_config.h is used to configure your BSP. r_bsp_config.h should be included
+* somewhere in your package so that the r_bsp code has access to it. This file (r_bsp_config_reference.h)
+* is just a reference file that the user can use to make their own r_bsp_config.h file.
+************************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 15.05.2017 1.00 First Release
+* : 01.12.2017 1.01 Added the following macro definition.
+* - BSP_CFG_EBMAPCR_1ST_PRIORITY
+* - BSP_CFG_EBMAPCR_2ND_PRIORITY
+* - BSP_CFG_EBMAPCR_3RD_PRIORITY
+* - BSP_CFG_EBMAPCR_4TH_PRIORITY
+* - BSP_CFG_EBMAPCR_5TH_PRIORITY
+* : 01.07.2018 1.02 Added the following macro definition.
+* - BSP_CFG_CONFIGURATOR_SELECT
+* Add RTOS support. FreeRTOS. Define a timer for RTOS.
+***********************************************************************************************************************/
+#ifndef R_BSP_CONFIG_REF_HEADER_FILE
+#define R_BSP_CONFIG_REF_HEADER_FILE
+
+/***********************************************************************************************************************
+Configuration Options
+***********************************************************************************************************************/
+
+/* NOTE:
+ The default settings are the same as when using RSKRX65N-2MB.
+ Change to the settings for the user board.
+*/
+
+/* Start up select
+ 0 = Enable BSP startup program.
+ 1 = Disable BSP startup program. (e.g. Using user startup program.)
+*/
+#define BSP_CFG_STARTUP_DISABLE (0)
+
+/* Enter the product part number for your MCU. This information will be used to obtain information about your MCU such
+ as package and memory size.
+ To help parse this information, the part number will be defined using multiple macros.
+ R 5 F 56 5N E D D FP
+ | | | | | | | | | Macro Name Description
+ | | | | | | | | |__BSP_CFG_MCU_PART_PACKAGE = Package type, number of pins, and pin pitch
+ | | | | | | | |____not used = Products with wide temperature range
+ | | | | | | |______BSP_CFG_MCU_PART_ENCRYPTION_INCLUDED = Encryption module included/not included
+ | | | | | |________BSP_CFG_MCU_PART_MEMORY_SIZE = ROM, RAM, and Data Flash Capacity
+ | | | | |___________BSP_CFG_MCU_PART_GROUP = Group name
+ | | | |______________BSP_CFG_MCU_PART_SERIES = Series name
+ | | |________________BSP_CFG_MCU_PART_MEMORY_TYPE = Type of memory (Flash, ROMless)
+ | |__________________not used = Renesas MCU
+ |____________________not used = Renesas semiconductor product.
+ */
+
+/* Package type. Set the macro definition based on values below:
+ Character(s) = Value for macro = Package Type/Number of Pins/Pin Pitch
+ FC = 0x0 = LFQFP/176/0.50
+ BG = 0x1 = LFBGA/176/0.80
+ LC = 0x2 = TFLGA/177/0.50
+ FB = 0x3 = LFQFP/144/0.50
+ LK = 0x4 = TFLGA/145/0.50
+ FP = 0x5 = LFQFP/100/0.50
+ LJ = 0xA = TFLGA/100/0.65
+*/
+#define BSP_CFG_MCU_PART_PACKAGE (0x5) // <-- Updated by GUI. Do not edit this value manually
+
+/* Whether Encryption and SDHI/SDSI are included or not.
+ Character(s) = Value for macro = Description
+ A = false = Encryption module not included, SDHI/SDSI module not included
+ B = false = Encryption module not included, SDHI/SDSI module included
+ D = false = Encryption module not included, SDHI/SDSI module included, dual-bank structure
+ E = true = Encryption module included, SDHI/SDSI module not included
+ F = true = Encryption module included, SDHI/SDSI module included
+ H = true = Encryption module included, SDHI/SDSI module included, dual-bank structure
+*/
+#define BSP_CFG_MCU_PART_ENCRYPTION_INCLUDED (false) // <-- Updated by GUI. Do not edit this value manually
+
+/* ROM, RAM, and Data Flash Capacity.
+ Character(s) = Value for macro = ROM Size/Ram Size/Data Flash Size
+ 4 = 0x4 = 512KB/256KB/Not equipped
+ 7 = 0x7 = 768KB/256KB/Not equipped
+ 9 = 0x9 = 1MB/256KB/Not equipped
+ C = 0xC = 1.5MB/640KB/32KB
+ E = 0xE = 2MB/640KB/32KB
+ NOTE: When the RAM capacity is 640KB, the RAM areas are not contiguous.
+*/
+#define BSP_CFG_MCU_PART_MEMORY_SIZE (0xE) // <-- Updated by GUI. Do not edit this value manually
+
+/* Group name.
+ Character(s) = Value for macro = Description
+ 5N/51 = 0x0 = RX65N Group/RX651 Group
+*/
+#define BSP_CFG_MCU_PART_GROUP (0x0) // <-- Updated by GUI. Do not edit this value manually
+
+/* Series name.
+ Character(s) = Value for macro = Description
+ 56 = 0x0 = RX600 Series
+*/
+#define BSP_CFG_MCU_PART_SERIES (0x0) // <-- Updated by GUI. Do not edit this value manually
+
+/* Memory type.
+ Character(s) = Value for macro = Description
+ F = 0x0 = Flash memory version
+*/
+#define BSP_CFG_MCU_PART_MEMORY_TYPE (0x0) // <-- Updated by GUI. Do not edit this value manually
+
+/* Whether to use 1 stack or 2. RX MCUs have the ability to use 2 stacks: an interrupt stack and a user stack.
+ * When using 2 stacks the user stack will be used during normal user code. When an interrupt occurs the CPU
+ * will automatically shift to using the interrupt stack. Having 2 stacks can make it easier to figure out how
+ * much stack space to allocate since the user does not have to worry about always having enough room on the
+ * user stack for if-and-when an interrupt occurs. Some users will not want 2 stacks though because it is not
+ * needed in all applications and can lead to wasted RAM (i.e. space in between stacks that is not used).
+ * If only 1 stack is used then the interrupt stack is the one that will be used. If 1 stack is chosen then
+ * the user may want to remove the 'SU' section from the linker sections to remove any linker warnings.
+ *
+ * 0 = Use 1 stack. Disable user stack. User stack size set below will be ignored.
+ * 1 = Use 2 stacks. User stack and interrupt stack will both be used.
+ */
+#define BSP_CFG_USER_STACK_ENABLE (1)
+
+/* When using the user startup program, disable the following code. */
+#if (BSP_CFG_STARTUP_DISABLE == 0)
+
+/* The 'BSP_DECLARE_STACK' macro is checked so that the stack is only declared in one place (resetprg.c). Every time a
+ '#pragma stacksize' is encountered, the stack size is increased. This prevents multiplication of stack size. */
+#if defined(BSP_DECLARE_STACK)
+ /* If only 1 stack is chosen using BSP_CFG_USER_STACK_ENABLE then no RAM will be allocated for the user stack. */
+ #if (BSP_CFG_USER_STACK_ENABLE == 1)
+ /* User Stack size in bytes. The Renesas RX toolchain sets the stack size using the #pragma stacksize directive. */
+ #pragma stacksize su=0x3000
+ #endif
+
+/* Interrupt Stack size in bytes. The Renesas RX toolchain sets the stack size using the #pragma stacksize directive.
+ * If the interrupt stack is the only stack being used then the user will likely want to increase the default size
+ * below.
+ */
+#pragma stacksize si=0x3000
+#endif
+
+#endif /* BSP_CFG_STARTUP_DISABLE == 0 */
+
+/* Heap size in bytes.
+ To disable the heap you must follow these steps:
+ 1) Set this macro (BSP_CFG_HEAP_BYTES) to 0.
+ 2) Set the macro BSP_CFG_IO_LIB_ENABLE to 0.
+ 3) Disable stdio from being built into the project library. This is done by going into the Renesas RX Toolchain
+ settings and choosing the Standard Library section. After that choose 'Standard Library' for Category in HEW or
+ choose 'Contents' in E2Studio. This will present a list of modules that can be included. Uncheck the box for
+ stdio.h.
+*/
+#define BSP_CFG_HEAP_BYTES (0x2000)
+
+/* Initializes C input & output library functions.
+ 0 = Disable I/O library initialization in resetprg.c. If you are not using stdio then use this value.
+ 1 = Enable I/O library initialization in resetprg.c. This is default and needed if you are using stdio. */
+#define BSP_CFG_IO_LIB_ENABLE (1)
+
+/* If desired the user may redirect the stdio charget() and/or charput() functions to their own respective functions
+ by enabling below and providing and replacing the my_sw_... function names with the names of their own functions. */
+#define BSP_CFG_USER_CHARGET_ENABLED (0)
+#define BSP_CFG_USER_CHARGET_FUNCTION my_sw_charget_function
+
+#define BSP_CFG_USER_CHARPUT_ENABLED (0)
+#define BSP_CFG_USER_CHARPUT_FUNCTION my_sw_charput_function
+
+/* After reset MCU will operate in Supervisor mode. To switch to User mode, set this macro to '1'. For more information
+ on the differences between these 2 modes see the CPU >> Processor Mode section of your MCU's hardware manual.
+ 0 = Stay in Supervisor mode.
+ 1 = Switch to User mode.
+*/
+#define BSP_CFG_RUN_IN_USER_MODE (0)
+
+/* Clock source select (CKSEL).
+ 0 = Low Speed On-Chip Oscillator (LOCO)
+ 1 = High Speed On-Chip Oscillator (HOCO)
+ 2 = Main Clock Oscillator
+ 3 = Sub-Clock Oscillator
+ 4 = PLL Circuit
+*/
+#define BSP_CFG_CLOCK_SOURCE (4) // <-- Updated by GUI. Do not edit this value manually
+
+/* Main clock Oscillator Switching (MOSEL).
+ 0 = Resonator
+ 1 = External clock input
+*/
+#define BSP_CFG_MAIN_CLOCK_SOURCE (0) // <-- Updated by GUI. Do not edit this value manually
+
+/* The sub-clock oscillation control for using the RTC.
+ When '1' is selected, the registers related to RTC are initialized and the sub-clock oscillator is operated.
+ 0 = The RTC is not to be used.
+ 1 = The RTC is to be used.
+*/
+#define BSP_CFG_RTC_ENABLE (0) // <-- Updated by GUI. Do not edit this value manually
+
+/* Sub-Clock Oscillator Drive Capacity Control (RTCDV).
+ 0 = Drive capacity for standard CL.
+ 1 = Drive capacity for low CL.
+*/
+#define BSP_CFG_SOSC_DRV_CAP (0) // <-- Updated by GUI. Do not edit this value manually //standard CL by default
+
+/* Clock configuration options.
+ The input clock frequency is specified and then the system clocks are set by specifying the multipliers used. The
+ multiplier settings are used to set the clock registers in resetprg.c. If a 24MHz clock is used and the
+ ICLK is 120MHz, PCLKA is 120MHz, PCLKB is 60MHz, PCLKC is 60MHz, PCLKD is 60MHz, FCLK is 60MHz, USB Clock is 48MHz,
+ and BCLK is 120MHz then the settings would be:
+
+ BSP_CFG_XTAL_HZ = 24000000
+ BSP_CFG_PLL_DIV = 1 (no division)
+ BSP_CFG_PLL_MUL = 10.0 (24MHz x 10.0 = 240MHz)
+ BSP_CFG_ICK_DIV = 2 : System Clock (ICLK) =
+ (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_ICK_DIV) = 120MHz
+ BSP_CFG_PCKA_DIV = 2 : Peripheral Clock A (PCLKA) =
+ (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKA_DIV) = 120MHz
+ BSP_CFG_PCKB_DIV = 4 : Peripheral Clock B (PCLKB) =
+ (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKB_DIV) = 60MHz
+ BSP_CFG_PCKC_DIV = 4 : Peripheral Clock C (PCLKC) =
+ (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKC_DIV) = 60MHz
+ BSP_CFG_PCKD_DIV = 4 : Peripheral Clock D (PCLKD) =
+ (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKD_DIV) = 60MHz
+ BSP_CFG_FCK_DIV = 4 : Flash IF Clock (FCLK) =
+ (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_FCK_DIV) = 60MHz
+ BSP_CFG_BCK_DIV = 2 : External Bus Clock (BCK) =
+ (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_BCK_DIV) = 120MHz
+ BSP_CFG_UCK_DIV = 5 : USB Clock (UCLK) =
+ (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_UCK_DIV) = 48MHz
+*/
+
+/* Input clock frequency in Hz (XTAL or EXTAL). */
+#define BSP_CFG_XTAL_HZ (12000000) // <-- Updated by GUI. Do not edit this value manually
+
+/* The HOCO can operate at several different frequencies. Choose which one using the macro below.
+ Available frequency settings:
+ 0 = 16MHz (default)
+ 1 = 18MHz
+ 2 = 20MHz
+*/
+#define BSP_CFG_HOCO_FREQUENCY (0) // <-- Updated by GUI. Do not edit this value manually
+
+/* PLL clock source (PLLSRCEL). Choose which clock source to input to the PLL circuit.
+ Available clock sources:
+ 0 = Main clock (default)
+ 1 = HOCO
+*/
+#define BSP_CFG_PLL_SRC (0) // <-- Updated by GUI. Do not edit this value manually
+
+/* PLL Input Frequency Division Ratio Select (PLIDIV).
+ Available divisors = /1 (no division), /2, /3
+*/
+#define BSP_CFG_PLL_DIV (1) // <-- Updated by GUI. Do not edit this value manually
+
+/* PLL Frequency Multiplication Factor Select (STC).
+ Available multipliers = x10.0 to x30.0 in 0.5 increments (e.g. 10.0, 10.5, 11.0, 11.5, ..., 29.0, 29.5, 30.0)
+*/
+#define BSP_CFG_PLL_MUL (20.0) // <-- Updated by GUI. Do not edit this value manually
+
+/* System Clock Divider (ICK).
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define BSP_CFG_ICK_DIV (2) // <-- Updated by GUI. Do not edit this value manually
+
+/* Peripheral Module Clock A Divider (PCKA).
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define BSP_CFG_PCKA_DIV (2) // <-- Updated by GUI. Do not edit this value manually
+
+/* Peripheral Module Clock B Divider (PCKB).
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define BSP_CFG_PCKB_DIV (4) // <-- Updated by GUI. Do not edit this value manually
+
+/* Peripheral Module Clock C Divider (PCKC).
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define BSP_CFG_PCKC_DIV (4) // <-- Updated by GUI. Do not edit this value manually
+
+/* Peripheral Module Clock D Divider (PCKD).
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define BSP_CFG_PCKD_DIV (4) // <-- Updated by GUI. Do not edit this value manually
+
+/* External Bus Clock Divider (BCLK).
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define BSP_CFG_BCK_DIV (2) // <-- Updated by GUI. Do not edit this value manually
+
+/* Flash IF Clock Divider (FCK).
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define BSP_CFG_FCK_DIV (4) // <-- Updated by GUI. Do not edit this value manually
+
+/* USB Clock Divider Select.
+ Available divisors = /2, /3, /4, /5
+*/
+#define BSP_CFG_UCK_DIV (5) // <-- Updated by GUI. Do not edit this value manually
+
+/* Configure BCLK output pin (only effective when external bus enabled)
+ Values 0=no output, 1 = BCK frequency, 2= BCK/2 frequency
+*/
+#define BSP_CFG_BCLK_OUTPUT (0) // <-- Updated by GUI. Do not edit this value manually
+
+/* Configure SDCLK output pin (only effective when external bus enabled)
+ Values 0=no output, 1 = BCK frequency
+*/
+#define BSP_CFG_SDCLK_OUTPUT (0) // <-- Updated by GUI. Do not edit this value manually
+
+/* Main Clock Oscillator Wait Time (MOSCWTCR).
+ The value of MOSCWTCR register required for correspondence with the waiting time required to secure stable oscillation
+ by the main clock oscillator is obtained by using the maximum frequency for fLOCO in the formula below.
+
+ BSP_CFG_MOSC_WAIT_TIME > (tMAINOSC * (fLOCO_max) + 16)/32
+ (tMAINOSC: main clock oscillation stabilization time; fLOCO_max: maximum frequency for fLOCO)
+
+ If tMAINOSC is 9.98 ms and fLOCO_max is 264 kHz (the period is 1/3.78 us), the formula gives
+ BSP_CFG_MOSC_WAIT_TIME > (9.98 ms * (264 kHZ) + 16)/32 = 82.83, so set the BSP_CFG_MOSC_WAIT_TIME to 83(53h).
+
+ NOTE: The waiting time is not required when an external clock signal is input for the main clock oscillator.
+ Set the BSP_CFG_MOSC_WAIT_TIME to 00h.
+*/
+#define BSP_CFG_MOSC_WAIT_TIME (0x53) // <-- Updated by GUI. Do not edit this value manually
+
+/* Sub-Clock Oscillator Wait Time (SOSCWTCR).
+ The value of SOSCWTCR register required for correspondence with the expected time to secure settling of oscillation
+ by the sub-clock oscillator is obtained by using the maximum frequency for fLOCO in the formula below.
+
+ BSP_CFG_SOSC_WAIT_TIME > (tSUBOSC * (fLOCO_max) + 16)/16384
+ (tSUBOSC: sub-clock oscillation stabilization time; fLOCO_max: maximum frequency for fLOCO)
+
+ If tSUBOSC is 2 s and fLOCO is 264 kHz (the period is 1/3.78 us), the formula gives
+ BSP_CFG_SOSC_WAIT_TIME > (2 s * (264 kHz) +16)/16384 = 32.22, so set the BSP_CFG_SOSC_WAIT_TIME bits to 33(21h).
+*/
+#define BSP_CFG_SOSC_WAIT_TIME (0x21) // <-- Updated by GUI. Do not edit this value manually
+
+/* ROM Cache Enable Register (ROMCE).
+ 0 = ROM cache operation disabled.
+ 1 = ROM cache operation enabled.
+*/
+#define BSP_CFG_ROM_CACHE_ENABLE (0)
+
+/* Configure WDT and IWDT settings.
+ OFS0 - Option Function Select Register 0
+ b31:b29 Reserved When reading, these bits return the value written by the user. The write value should be 1.
+ b28 WDTRSTIRQS - WDT Reset Interrupt Request - What to do on underflow (0=take interrupt, 1=reset MCU)
+ b27:b26 WDTRPSS - WDT Window Start Position Select - (0=25%, 1=50%, 2=75%, 3=100%,don't use)
+ b25:b24 WDTRPES - WDT Window End Position Select - (0=75%, 1=50%, 2=25%, 3=0%,don't use)
+ b23:b20 WDTCKS - WDT Clock Frequency Division Ratio - (1=PCLKB/4, 4=PCLKB/64, 0xF=PCLKB/128, 6=PCLKB/256,
+ 7=PCLKB/2048, 8=PCLKB/8192)
+ b19:b18 WDTTOPS - WDT Timeout Period Select (0=1024 cycles, 1=4096, 2=8192, 3=16384)
+ b17 WDTSTRT - WDT Start Mode Select - (0=auto-start after reset, 1=halt after reset)
+ b16:b15 Reserved (set to 1)
+ b14 IWDTSLCSTP - IWDT Sleep Mode Count Stop Control - (0=can't stop count, 1=stop w/some low power modes)
+ b13 Reserved (set to 1)
+ b12 IWDTRSTIRQS - IWDT Reset Interrupt Request - What to do on underflow (0=take interrupt, 1=reset MCU)
+ b11:b10 IWDTRPSS - IWDT Window Start Position Select - (0=25%, 1=50%, 2=75%, 3=100%,don't use)
+ b9:b8 IWDTRPES - IWDT Window End Position Select - (0=75%, 1=50%, 2=25%, 3=0%,don't use)
+ b7:b4 IWDTCKS - IWDT Clock Frequency Division Ratio - (0=none, 2=/16, 3 = /32, 4=/64, 0xF=/128, 5=/256)
+ b3:b2 IWDTTOPS - IWDT Timeout Period Select - (0=1024 cycles, 1=4096, 2=8192, 3=16384)
+ b1 IWDTSTRT - IWDT Start Mode Select - (0=auto-start after reset, 1=halt after reset)
+ b0 Reserved (set to 1)
+*/
+#define BSP_CFG_OFS0_REG_VALUE (0xFFFFFFFF) // <-- Updated by GUI. Do not edit this value manually //Disable by default
+
+/* Configure whether voltage detection 0 circuit and HOCO are enabled after reset.
+ OFS1 - Option Function Select Register 1
+ b31:b9 Reserved (set to 1)
+ b8 HOCOEN - Enable/disable HOCO oscillation after a reset (0=enable, 1=disable)
+ b7:b3 Reserved When reading, these bits return the value written by the user. The write value should be 1.
+ b2 LVDAS - Voltage Detection 0 circuit start (1=monitoring disabled)
+ b1:b0 VDSEL - Voltage Detection 0 level select (1=2.94v, 2=2.87v, 3=2.80v)
+ NOTE: If HOCO oscillation is enabled by OFS1.HOCOEN, HOCO frequency is 16MHz.
+ BSP_CFG_HOCO_FREQUENCY should be default value.
+*/
+#define BSP_CFG_OFS1_REG_VALUE (0xFFFFFFFF) // <-- Updated by GUI. Do not edit this value manually //Disable by default
+
+/* Trusted memory is facility to prevent the reading of blocks 8 and 9 and blocks 46 and 47 (in dual mode) in
+ the code flash memory by third party software. This feature is disabled by default.
+ TMEF - TM Enable Flag Register
+ b31 Reserved (set to 1)
+ b30:b28 TMEFDB - Dual-Bank TM Enable - 000: The TM function in the address range from FFEE 0000h to
+ FFEE FFFFh is enabled in dual mode.
+ - 111: The TM function in the address range from FFEE 0000h to
+ FFEE FFFFh is disabled in dual mode.
+ b27 Reserved (set to 1)
+ b26:b24 TMEFF - TM Enable - 000: TM function is enabled.
+ - 111: TM function is disabled.
+ b23:b0 Reserved (set to 1)
+ NOTE: If the dual bank function has not been incorporated in a device,
+ TMEFDB bits [b30:b26] are reserved area.
+*/
+#define BSP_CFG_TRUSTED_MODE_FUNCTION (0xFFFFFFFF) //Disable by default
+
+/* Configure FAW register is used to set the write protection flag and boot area select flag
+ for setting the flash access window startaddress and flash access window end address.
+ FAW - Flash Access Window Setting Register
+ b31 BTFLG - Boot Area Select Flag - 0: FFFF C000h to FFFF DFFFh are used as the boot area
+ - 1: FFFF E000h to FFFF FFFFh are used as the boot area
+ b30:b28 Reserved - When reading, these bits return the value written by the user.The write value should be 1.
+ b27:b16 FAWE - Flash Access Window End Address - Flash access window end address
+ b15 FSPR - Access Window Protection Flag - 0: With protection (P/E disabled)
+ - 1: Without protection (P/E enabled)
+ b14:b12 Reserved - When reading, these bits return the value written by the user.The write value should be 1.
+ b11:b0 FAWS - Flash Access Window Start Address - Flash access window start address
+ NOTE: Once 0 is written to this bit, the bit can never be restored to 1.
+ Therefore, the access window and the BTFLG bit never be set again or the TM function
+ never be disabled once it has been enabled.
+ Exercise extra caution when handling the FSPR bit.
+*/
+#define BSP_CFG_FAW_REG_VALUE (0xFFFFFFFF) //Disable by default
+
+/* The ROM code protection register is a function to prohibit reading from or programming to the flash memory
+ when the flash programmer is used during off-board programming.
+ ROMCODE - ROM Code Protection Register
+ b31:b0 ROM Code - 0000 0000h: ROM code protection enabled (ROM code protection 1).
+ 0000 0001h: ROM code protection enabled (ROM code protection 2).
+ Other than above: ROM code protection disabled.
+ Note. The ROMCODE register should be set in 32-bit units.
+*/
+#define BSP_CFG_ROMCODE_REG_VALUE (0xFFFFFFFF) //Disable by default
+
+/* Select the bank mode of dual-bank function of the code flash memory.
+ 0 = Dual mode.
+ 1 = Linear mode.
+ NOTE: If the dual bank function has been incorporated in a device, select the bank mode in this macro.
+ Default setting of the bank mode is linear mode.
+ If the dual bank function has not been incorporated in a device, this macro should be 1.
+*/
+#define BSP_CFG_CODE_FLASH_BANK_MODE (1) //Linear mode by default
+
+/* Select the startup bank of the program when dual bank function is in dual mode.
+ 0 = The address range of bank 1 from FFE00000h to FFEFFFFFh and bank 0 from FFF00000h to FFFFFFFFh.
+ 1 = The address range of bank 1 from FFF00000h to FFFFFFFFh and bank 0 from FFE00000h to FFEFFFFFh.
+ NOTE: If the dual bank function has been incorporated in a device, select the start bank in this macro.
+ Default setting of the start bank is bank0.
+ If the dual bank function has not been incorporated in a device, this macro should be 0.
+*/
+#define BSP_CFG_CODE_FLASH_START_BANK (0) //Bank0 by default
+
+/* This macro lets other modules no if a RTOS is being used.
+ 0 = RTOS is not used.
+ 1 = FreeRTOS is used.
+ 2 = embOS is used.(This is not available.)
+ 3 = MicroC_OS is used.(This is not available.)
+ 4 = RI600V4 or RI600PX is used.(This is not available.)
+*/
+/* As of today, we need a workaround to avoid the problem that the Smart Configurator does not have such GUI
+ yet and the BSP_CFG_RTOS_USED here is set to (0) every time of code generation by the Smart Configurator.
+ The BSP_CFG_RTOS_USED is set to (1) in the r_bsp.h instead of here so that the setting of here is ignored.
+*/
+#if !defined(BSP_CFG_RTOS_USED) || (BSP_CFG_RTOS_USED == 0)
+#if defined(BSP_CFG_RTOS_USED)
+#undef BSP_CFG_RTOS_USED
+#endif
+#define BSP_CFG_RTOS_USED (0) // <-- Updated by GUI. Do not edit this value manually
+#endif
+
+/* This macro is used to select which CMT channel used for system timer of RTOS.
+ * The setting of this macro is only valid if the macro BSP_CFG_RTOS_USED is set to a value other than 0. */
+#if (BSP_CFG_RTOS_USED != 0)
+/* Setting value.
+ * 0 = CMT channel 0 used for system timer of RTOS (recommended to be used for RTOS).
+ * 1 = CMT channel 1 used for system timer of RTOS.
+ * 2 = CMT channel 2 used for system timer of RTOS.
+ * 3 = CMT channel 3 used for system timer of RTOS.
+ * Others = Invalid. */
+#define BSP_CFG_RTOS_SYSTEM_TIMER (0)
+#endif
+
+/* By default modules will use global locks found in mcu_locks.c. If the user is using a RTOS and would rather use its
+ locking mechanisms then they can change this macro.
+ NOTE: If '1' is chosen for this macro then the user must also change the next macro 'BSP_CFG_USER_LOCKING_TYPE'.
+ 0 = Use default locking (non-RTOS)
+ 1 = Use user defined locking mechanism.
+*/
+#define BSP_CFG_USER_LOCKING_ENABLED (0)
+
+/* If the user decides to use their own locking mechanism with FIT modules then they will need to redefine the typedef
+ that is used for the locks. If the user is using a RTOS then they would likely redefine the typedef to be
+ a semaphore/mutex type of their RTOS. Use the macro below to set the type that will be used for the locks.
+ NOTE: If BSP_CFG_USER_LOCKING_ENABLED == 0 then this typedef is ignored.
+ NOTE: Do not surround the type with parentheses '(' ')'.
+*/
+#define BSP_CFG_USER_LOCKING_TYPE bsp_lock_t
+
+/* If the user decides to use their own locking mechanism with FIT modules then they will need to define the functions
+ that will handle the locking and unlocking. These functions should be defined below.
+ If BSP_CFG_USER_LOCKING_ENABLED is != 0:
+ R_BSP_HardwareLock(mcu_lock_t hw_index) will call BSP_CFG_USER_LOCKING_HW_LOCK_FUNCTION(mcu_lock_t hw_index)
+ R_BSP_HardwareUnlock(mcu_lock_t hw_index) will call BSP_CFG_USER_LOCKING_HW_UNLOCK_FUNCTION(mcu_lock_t hw_index)
+ NOTE:With these functions the index into the array holding the global hardware locks is passed as the parameter.
+ R_BSP_SoftwareLock(BSP_CFG_USER_LOCKING_TYPE * plock) will call
+ BSP_CFG_USER_LOCKING_SW_LOCK_FUNCTION(BSP_CFG_USER_LOCKING_TYPE * plock)
+ R_BSP_SoftwareUnlock(BSP_CFG_USER_LOCKING_TYPE * plock) will call
+ BSP_CFG_USER_LOCKING_SW_UNLOCK_FUNCTION(BSP_CFG_USER_LOCKING_TYPE * plock)
+ NOTE:With these functions the actual address of the lock to use is passed as the parameter.
+ NOTE: These functions must return a boolean. If lock was obtained or released successfully then return true. Else,
+ return false.
+ NOTE: If BSP_CFG_USER_LOCKING_ENABLED == 0 then this typedef is ignored.
+ NOTE: Do not surround the type with parentheses '(' ')'.
+*/
+#define BSP_CFG_USER_LOCKING_HW_LOCK_FUNCTION my_hw_locking_function
+#define BSP_CFG_USER_LOCKING_HW_UNLOCK_FUNCTION my_hw_unlocking_function
+#define BSP_CFG_USER_LOCKING_SW_LOCK_FUNCTION my_sw_locking_function
+#define BSP_CFG_USER_LOCKING_SW_UNLOCK_FUNCTION my_sw_unlocking_function
+
+/* If the user would like to determine if a warm start reset has occurred, then they may enable one or more of the
+ * following callback definitions AND provide a call back function name for the respective callback
+ * function (to be defined by the user). Setting BSP_CFG_USER_WARM_START_CALLBACK_PRE_INITC_ENABLED = 1 will result
+ * in a callback to the user defined my_sw_warmstart_prec_function just prior to the initialization of the C
+ * runtime environment by resetprg.
+ *
+ * Setting BSP_CFG_USER_WARM_START_CALLBACK_POST_INITC_ENABLED = 1 will result in a callback to the user defined
+ * my_sw_warmstart_postc_function just after the initialization of the C runtime environment by resetprg.
+ */
+#define BSP_CFG_USER_WARM_START_CALLBACK_PRE_INITC_ENABLED (0)
+#define BSP_CFG_USER_WARM_START_PRE_C_FUNCTION my_sw_warmstart_prec_function
+
+#define BSP_CFG_USER_WARM_START_CALLBACK_POST_INITC_ENABLED (0)
+#define BSP_CFG_USER_WARM_START_POST_C_FUNCTION my_sw_warmstart_postc_function
+
+/* By default FIT modules will check input parameters to be valid. This is helpful during development but some users
+ will want to disable this for production code. The reason for this would be to save execution time and code space.
+ This macro is a global setting for enabling or disabling parameter checking. Each FIT module will also have its
+ own local macro for this same purpose. By default the local macros will take the global value from here though
+ they can be overridden. Therefore, the local setting has priority over this global setting. Disabling parameter
+ checking should only used when inputs are known to be good and the increase in speed or decrease in code space is
+ needed.
+ 0 = Global setting for parameter checking is disabled.
+ 1 = Global setting for parameter checking is enabled (Default).
+*/
+#define BSP_CFG_PARAM_CHECKING_ENABLE (1)
+
+/* The extended bus master has five transfer sources: EDMAC, GLCDC-GRA1 (GLCDC graphics 1 data read), GLCDCGRA2 (GLCDC
+ graphics 2 data read), DRW2D-TX (DRW2D texture data read), and DRW2D-FB (DRW2D frame buffer data read write and
+ display list data read).
+ The default priority order in bsp is below
+ GLCDC-GRA1 > GLCDC-GRA2 > DRW2D-TX > DRW2D-FB > EDMAC.
+ Priority can be changed with this macro.
+
+ Extended Bus Master Priority setting
+ 0 = GLCDC graphics 1 data read
+ 1 = DRW2D texture data read
+ 2 = DRW2D frame buffer data read write and display list data read
+ 3 = GLCDC graphics 2 data read
+ 4 = EDMAC
+
+ Note : This macro is only available for products with at least 1.5 Mbytes of code flash memory.
+ Settings other than above are prohibited.
+ Duplicate priority settings can not be made.
+*/
+#define BSP_CFG_EBMAPCR_1ST_PRIORITY (0) /* Extended Bus Master 1st Priority Selection */
+#define BSP_CFG_EBMAPCR_2ND_PRIORITY (3) /* Extended Bus Master 2nd Priority Selection */
+#define BSP_CFG_EBMAPCR_3RD_PRIORITY (1) /* Extended Bus Master 3rd Priority Selection */
+#define BSP_CFG_EBMAPCR_4TH_PRIORITY (2) /* Extended Bus Master 4th Priority Selection */
+#define BSP_CFG_EBMAPCR_5TH_PRIORITY (4) /* Extended Bus Master 5th Priority Selection */
+
+/* This macro is used to define the voltage that is supplied to the MCU (Vcc). This macro is defined in millivolts. This
+ macro does not actually change anything on the MCU. Some FIT modules need this information so it is defined here. */
+#define BSP_CFG_MCU_VCC_MV (3300) // <-- Updated by GUI. Do not edit this value manually
+
+/* Allow initialization of auto-generated peripheral initialization code by Smart Configurator tool.
+ When not using the Smart Configurator, set the value of BSP_CFG_CONFIGURATOR_SELECT to 0.
+ 0 = Disabled (default)
+ 1 = Smart Configurator initialization code used
+*/
+#define BSP_CFG_CONFIGURATOR_SELECT (1) // <-- Updated by GUI. Do not edit this value manually
+
+/* There are multiple versions of the RSKRX65N-2MB. Choose which board is currently being used below.
+ 0 = 1st Prototype Board (RTK50565N2CxxxxxBR)
+ 1 = rev. 1.00 Board (RTK50565N2C00000BE)
+ 2 = RX65N Envision Kit
+ 3 = RX65N GR-ROSE
+ (4 = RX64M GR-KAEDE // FIXME: find a better way)
+ 5 = RX65N TB
+*/
+#define BSP_CFG_BOARD_REVISION (5)
+
+#endif /* R_BSP_CONFIG_REF_HEADER_FILE */
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/r_config/r_bsp_config_readme.txt b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/r_config/r_bsp_config_readme.txt
new file mode 100644
index 00000000000..6a9002cf4f3
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/r_config/r_bsp_config_readme.txt
@@ -0,0 +1,12 @@
+FIT r_config folder
+-------------------
+The purpose of the r_config folder is to provide one place where the user can store all of their FIT configuration
+files. Putting the files in one place makes them easy to find, backup, and put in a version control system.
+
+FIT Modules are distributed with a reference configuration file. These files end with '_reference.h'. For example,
+the reference configuration file for the r_bsp is named r_bsp_config_reference.h. Reference configuration files are
+provided so that the user always has a known-good configuration to revert to. When adding a FIT Module to a project the
+user should copy this reference configuration file to this folder and remove '_reference' from the filename
+(r_bsp_config_reference.h is renamed to r_bsp_config.h). For the r_bsp the reference configuration file can be found in
+the 'board' folder for the currently chosen development board. For other FIT Modules the reference configuration file
+can be found in the 'ref' folder of the FIT Module.
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/r_config/r_bsp_interrupt_config.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/r_config/r_bsp_interrupt_config.h
new file mode 100644
index 00000000000..dd09ad9edc6
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/r_config/r_bsp_interrupt_config.h
@@ -0,0 +1,214 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : r_bsp_interrupt_config.h
+* Description : This module maps Interrupt A & B interrupts. More information on how this is done is given below.
+***********************************************************************************************************************/
+/**********************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 01.10.2016 1.00 First Release
+* : 15.05.2017 2.00 Changed the name of the following macro definition, because there was a mistake
+* in the name of macro definition.
+* - From XXX_TPU0_TGI0V to XXX_TPU0_TCI0V.
+* - From XXX_TPU1_TGI1V to XXX_TPU1_TCI1V.
+* - From XXX_TPU1_TGI1U to XXX_TPU1_TCI1U.
+* - From XXX_TPU2_TGI2V to XXX_TPU2_TCI2V.
+* - From XXX_TPU2_TGI2U to XXX_TPU2_TCI2U.
+* - From XXX_TPU3_TGI3V to XXX_TPU3_TCI3V.
+* - From XXX_TPU4_TGI4V to XXX_TPU4_TCI4V.
+* - From XXX_TPU4_TGI4U to XXX_TPU4_TCI4U.
+* - From XXX_TPU5_TGI5V to XXX_TPU5_TCI5V.
+* - From XXX_TPU5_TGI5U to XXX_TPU5_TCI5U.
+* - From XXX_MTU0_TGIV0 to XXX_MTU0_TCIV0.
+* - From XXX_MTU1_TGIV1 to XXX_MTU1_TCIV1.
+* - From XXX_MTU1_TGIU1 to XXX_MTU1_TCIU1.
+* - From XXX_MTU2_TGIV2 to XXX_MTU2_TCIV2.
+* - From XXX_MTU2_TGIU2 to XXX_MTU2_TCIU2.
+* - From XXX_MTU3_TGIV3 to XXX_MTU3_TCIV3.
+* - From XXX_MTU4_TGIV4 to XXX_MTU4_TCIV4.
+* - From XXX_MTU6_TGIV6 to XXX_MTU6_TCIV6.
+* - From XXX_MTU7_TGIV7 to XXX_MTU7_TCIV7.
+* - From XXX_MTU8_TGIV8 to XXX_MTU8_TCIV8.
+* Added select processing of the following software configurable interrupt source.
+* - TSIP_PROC_BUSY
+* - TSIP_ROMOK
+* - TSIP_LONG_PLG
+* - TSIP_TEST_BUSY
+* - TSIP_WRRDY0
+* - TSIP_WRRDY1
+* - TSIP_WRRDY4
+* - TSIP_RDRDY0
+* - TSIP_RDRDY1
+* - TSIP_INTEGRATE_WRRDY
+* - TSIP_INTEGRATE_RDRDY
+***********************************************************************************************************************/
+#ifndef R_BSP_INTERRUPT_CONFIG_REF_HEADER_FILE
+#define R_BSP_INTERRUPT_CONFIG_REF_HEADER_FILE
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/* If you wish to use one of the interrupt below then set the appropriate configuration macro to the vector number you
+ * wish to use for that interrupt. For example, if you want to use the RTC carry interrupt (CUP) at vector 176 then you
+ * would do the following:
+ *
+ * #define BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP 176
+ */
+
+/* Interrupt B Sources.
+ * -Valid vector numbers are 128-207.
+ * -There are more vector slots for B sources than actual B sources. By default all B sources are mapped.
+ * -If using the 'TPU1, TGI1A' interrupt it must be vector 144 or 145. It is set to 144 by default.
+ * -If a peripheral interrupt is going to be used to wake up the MCU from All-Module Clock Stop Mode then it must be
+ * in a vector between 146 to 157. Peripheral interrupts that can do this are TMR interrupts and the 'USB0, USBI0'
+ * interrupt. By default the TMR interrupts are chosen since there are 12 of them and there are 12 slots.
+ */
+#define BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2 128
+#define BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3 129
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0 146
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0 147
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0 148
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1 149
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1 150
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1 151
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2 152
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2 153
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2 154
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3 155
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3 156
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3 157
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A 130
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B 131
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C 132
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D 133
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TCI0V 134
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A 144
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B 135
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1V 136
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1U 137
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A 138
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B 139
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2V 140
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2U 141
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A 142
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B 143
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C 145
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D 158
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TCI3V 159
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A 160
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B 161
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4V 162
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4U 163
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A 164
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B 165
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5V 166
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5U 167
+#define BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0 168
+#define BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0 169
+#define BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0 170
+#define BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0 171
+#define BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1 172
+#define BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1 173
+#define BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1 174
+#define BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1 175
+#define BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP 176
+#define BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0 177
+#define BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0 178
+#define BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0 179
+#define BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0 180
+#define BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1 181
+#define BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1 182
+#define BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1 183
+#define BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1 184
+#define BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0 185
+#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0 186
+#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0 187
+#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GCADI0 188
+#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1 189
+#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1 190
+#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GCADI1 191
+#define BSP_MAPPED_INT_CFG_B_VECT_RNG_RNGEND
+#define BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I 193
+#define BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I 194
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_PROC_BUSY 195
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_ROMOK 196
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_LONG_PLG 197
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_TEST_BUSY 198
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY0 199
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY1 200
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY4 201
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY0 202
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY1 203
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_WRRDY 204
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_RDRDY 205
+
+/* Interrupt A Sources.
+ * -Valid vector numbers are 208-255.
+ * -There are more A sources than A vector slots. By default none of the GPT interrupts are mapped.
+ * -If using the 'MTU1, TGI1A' interrupt it must be vector 208 or 209. It is set to 208 by default.
+ */
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0 209
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0 210
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0 211
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0 212
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0 213
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0 214
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0 215
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1 208
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1 216
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1 217
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1 218
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2 219
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2 220
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2 221
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2 222
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3 223
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3 224
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3 225
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3 226
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3 227
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4 228
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4 229
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4 230
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4 231
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4 232
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5 233
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5 234
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5 235
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6 236
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6 237
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6 238
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6 239
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6 240
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7 241
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7 242
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7 243
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7 244
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7 245
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8 246
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8 247
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8 248
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8 249
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TCIV8 250
+#define BSP_MAPPED_INT_CFG_A_VECT_AES_AESRDY
+#define BSP_MAPPED_INT_CFG_A_VECT_AES_AESEND
+
+#endif /* R_BSP_INTERRUPT_CONFIG_REF_HEADER_FILE */
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/r_config/r_byteq_config.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/r_config/r_byteq_config.h
new file mode 100644
index 00000000000..0b4d4f9bb52
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/r_config/r_byteq_config.h
@@ -0,0 +1,59 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : r_byteq_config.h
+* Description : Configures the byte queue memory allocation
+************************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 24.07.2013 1.00 Initial Release
+* : 11.21.2014 1.20 Removed dependency to BSP
+* : 30.09.2015 1.50 Added dependency to BSP
+***********************************************************************************************************************/
+#ifndef BYTEQ_CONFIG_H
+#define BYTEQ_CONFIG_H
+
+/***********************************************************************************************************************
+Includes , "Project Includes"
+***********************************************************************************************************************/
+#include "platform.h"
+
+/***********************************************************************************************************************
+Configuration Options
+***********************************************************************************************************************/
+
+/* SPECIFY WHETHER TO INCLUDE CODE FOR API PARAMETER CHECKING
+ Available settings:
+ BSP_CFG_PARAM_CHECKING_ENABLE:
+ Utilizes the system default setting
+ 1:
+ Includes parameter checking
+ 0:
+ Compiles out parameter checking
+*/
+#define BYTEQ_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+
+/* SPECIFY IF SHOULD USE MALLOC() TO ALLOCATE MEMORY FOR QUEUE CONTROL BLOCKS */
+#define BYTEQ_CFG_USE_HEAP_FOR_CTRL_BLKS (0)
+
+/* SPECIFY NUMBER OF STATIC QUEUE CONTROL BLOCKS TO SUPPORT */
+/* valid only when BYTEQ_USE_HEAP_FOR_CTRL_BLKS is set to 0 */
+#define BYTEQ_CFG_MAX_CTRL_BLKS (4)
+
+
+#endif /* BYTEQ_CONFIG_H */
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/r_config/r_flash_rx_config.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/r_config/r_flash_rx_config.h
new file mode 100644
index 00000000000..fbf916a0e97
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/r_config/r_flash_rx_config.h
@@ -0,0 +1,116 @@
+/***********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+ * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+ * SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+ ***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * File Name : r_flash_rx_config_reference.h
+ * Description : Configures the FLASH API module for RX200 and RX600 Series MCU's.
+ ***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* 12.04.2014 1.00 First Release
+* 22.12.2014 1.10 Added flash type usage comments.
+* 25.06.2015 1.20 Added FLASH_CFG_CODE_FLASH_RUN_FROM_ROM.
+* : 12.10.2016 2.00 Modified for BSPless operation (added FLASH_CFG_USE_FIT_BSP).
+***********************************************************************************************************************/
+#ifndef FLASH_CONFIG_HEADER_FILE
+#define FLASH_CONFIG_HEADER_FILE
+
+/* Set the following value to 0 when building without using the FIT BSP Module */
+#define FLASH_CFG_USE_FIT_BSP (1)
+
+
+/***********************************************************************************************************************
+ Configuration Options
+ ***********************************************************************************************************************/
+/* SPECIFY WHETHER TO INCLUDE CODE FOR API PARAMETER CHECKING
+ * Setting to BSP_CFG_PARAM_CHECKING_ENABLE utilizes the system default setting
+ * Setting to 1 includes parameter checking; 0 compiles out parameter checking
+ */
+#define FLASH_CFG_PARAM_CHECKING_ENABLE (1)
+
+
+/******************************************************************************
+ ENABLE CODE FLASH PROGRAMMING
+******************************************************************************/
+/* If you are only using data flash, set this to 0.
+ * Setting to 1 includes code to program the ROM area. When programming ROM,
+ * code must be executed from RAM, except under certain restrictions for flash
+ * type 3 (see section 2.14 in App Note). See section 2.13 in the App Note for
+ * details on how to set up code and the linker to execute code from RAM.
+ */
+#define FLASH_CFG_CODE_FLASH_ENABLE (0)
+
+
+/******************************************************************************
+ ENABLE BGO/NON-BLOCKING DATA FLASH OPERATIONS
+******************************************************************************/
+/* Setting this to 0 forces data flash API function to block until completed.
+ * Setting to 1 places the module in BGO (background operations) mode. In BGO
+ * mode, data flash operations return immediately after the operation has been
+ * started. Notification of the operation completion is done via the callback
+ * function.
+ */
+#define FLASH_CFG_DATA_FLASH_BGO (0)
+
+
+/******************************************************************************
+ ENABLE BGO/NON-BLOCKING CODE FLASH (ROM) OPERATIONS
+******************************************************************************/
+/* Setting this to 0 forces ROM API function to block until completed.
+ * Setting to 1 places the module in BGO (background operations) mode. In BGO
+ * mode, ROM operations return immediately after the operation has been started.
+ * Notification of the operation completion is done via the callback function.
+ * When reprogramming ROM, THE RELOCATABLE VECTOR TABLE AND CORRESPONDING
+ * INTERRUPT ROUTINES MUST BE IN RAM.
+ * See sections 2.16 Usage Notes in the App Note.
+ */
+#define FLASH_CFG_CODE_FLASH_BGO (0)
+
+
+/******************************************************************************
+ ENABLE CODE FLASH SELF-PROGRAMMING
+******************************************************************************/
+/* Set this to 0 when programming code flash while executing in RAM.
+ * Set this to 1 when programming code flash while executing from another
+ * segment in ROM (possible only with RX64M, RX71M, RX65N-2 groups).
+ * See section 2.14 in the App Note.
+ */
+#define FLASH_CFG_CODE_FLASH_RUN_FROM_ROM (0)
+
+
+/******************************************************************************
+ SET IPL OF FLASH READY INTERRUPT
+******************************************************************************/
+#define FLASH_CFG_FLASH_READY_IPL (5) // Flash type 2 only
+
+
+/******************************************************************************
+ ENABLE OR DISABLE LOCK BIT PROTECTION
+******************************************************************************/
+/* Each erasure block has a corresponding lock bit that can be used to
+ * protect that block from being programmed/erased after the lock bit is
+ * set. The use of lock bits can be used or ignored.
+ * Setting this to 1 will cause lock bits to be ignored and programs/erases to a
+ * block will not be limited.
+ * Setting this to 0 will cause lock bits to be used as the user configures through
+ * the Control command. This only applies to ROM as the DF does not have lock bits.
+ */
+#define FLASH_CFG_IGNORE_LOCK_BITS (1) // Flash type 2 only
+
+
+#endif /* FLASH_CONFIG_HEADER_FILE */
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/r_config/r_riic_rx_config.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/r_config/r_riic_rx_config.h
new file mode 100644
index 00000000000..162cde5ea41
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/r_config/r_riic_rx_config.h
@@ -0,0 +1,197 @@
+/***********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+ * No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO
+ * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
+ **********************************************************************************************************************/
+/***********************************************************************************************************************
+ * File Name : r_riic_rx_config_reference.h
+ * Description : Configures the RIIC drivers
+ **********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ * : 01.07.2013 1.00 First Release
+ * : 30.09.2013 1.10 Change symbol of return value and status
+ * : 08.10.2013 1.20 Modified processing for the I/O register initialization and mode transition
+ * when a stop condition is detected while the slave is communicating.
+ * Modified processing for mode transition when an API function is called
+ * while the bus is busy.
+ * Modified processing for mode transition
+ * when an arbitration lost occurred and the addresses do not match.
+ * Modified incorrect slave transmission after the master reception.
+ * Modified processing for the I/O register initialization
+ * when generating a start condition and receiving the slave address.
+ * : 17.07.2014 1.30 Added the parameters of channel 2.
+ * Deleted the parameters of PCLK.
+ * Added the parameters of the port function assignment.
+ * Changed the parameters of interrupt priority level.
+ * Added the parameters for the time out detection.
+ * : 22.09.2014 1.40 The module is updated to measure the issue that slave communication
+ * is not available after an arbitration-lost occurs and the bus is locked.
+ * The issue occurs when the following four conditions are all met.
+ * - RIIC FIT module rev. 1.30 or earlier is used.
+ * - RX device operates as both the master and the slave
+ * in multi-master communication.
+ * - An arbitration-lost is detected when communicating as the master.
+ * - Communication other than master reception or slave reception is performed.
+ * : 14.11.2014 1.50 Added RX113 support.
+ * : 09.10.2014 1.60 Added RX71M support.
+ * : 20.10.2014 1.70 Added RX231 support.
+ * : 31.10.2015 1.80 Added RX130, RX230, RX23T support.
+ * : 04.03.2016 1.90 Added RX24T support.Changed about the pin definisions.
+ * : 01.10.2016 2.00 Added RX65N support.
+ * : 02.06.2017 2.10 Added RX24U support.
+ * : 31.08.2017 2.20 Added definitions for Channel 1.
+ **********************************************************************************************************************/
+/* Guards against multiple inclusion */
+#ifndef RIIC_CONFIG_H
+ #define RIIC_CONFIG_H
+/***********************************************************************************************************************
+ Configuration Options
+ **********************************************************************************************************************/
+/* SPECIFY WHETHER TO INCLUDE CODE FOR API PARAMETER CHECKING */
+/* Setting to BSP_CFG_PARAM_CHECKING_ENABLE utilizes the system default setting */
+/* Setting to 1 includes parameter checking; 0 compiles out parameter checking */
+ #define RIIC_CFG_PARAM_CHECKING_ENABLE (1U)
+
+/* SPECIFY CHANNELS TO INCLUDE SOFTWARE SUPPORT FOR 1=included, 0=not */
+/* mcu supported channels */
+/* RX110: ch0, , */
+/* RX111: ch0, , */
+/* RX113: ch0, , */
+/* RX130: ch0, , */
+/* RX230: ch0, , */
+/* RX231: ch0, , */
+/* RX23T: ch0, , */
+/* RX24T: ch0, , */
+/* RX24U: ch0, , */
+/* RX64M: ch0, , ch2 */
+/* RX65N: ch0, ch1, ch2 */
+/* RX71M: ch0, , ch2 */
+ #define RIIC_CFG_CH0_INCLUDED (1U)
+ #define RIIC_CFG_CH1_INCLUDED (0U)
+ #define RIIC_CFG_CH2_INCLUDED (0U)
+
+/* Set RIIC bps(kbps) */
+ #define RIIC_CFG_CH0_kBPS (400U)
+ #define RIIC_CFG_CH1_kBPS (400U)
+ #define RIIC_CFG_CH2_kBPS (400U)
+
+/* Set using digital filter(Selected IIC phi cycle is filtered out) */
+/* 0 = not, 1 = one IIC phi, 2 = two IIC phi, 3 = three IIC phi, 4 = four IIC phi */
+ #define RIIC_CFG_CH0_DIGITAL_FILTER (2U)
+ #define RIIC_CFG_CH1_DIGITAL_FILTER (2U)
+ #define RIIC_CFG_CH2_DIGITAL_FILTER (2U)
+
+/* Setting to */
+/* 1: includes riic port setting processing */
+/* 0: compiles out riic port setting processing */
+ #define RIIC_CFG_PORT_SET_PROCESSING (1U)
+
+/* Set mode */
+/* 0 = single master mode, 1 = multi master mode(Master arbitration-lost detection is enabled.) */
+ #define RIIC_CFG_CH0_MASTER_MODE (1U)
+ #define RIIC_CFG_CH1_MASTER_MODE (1U)
+ #define RIIC_CFG_CH2_MASTER_MODE (1U)
+
+/* Set slave address */
+/* 0 = not, 1 = 7bit address format, 2 = 10bit address format */
+ #define RIIC_CFG_CH0_SLV_ADDR0_FORMAT (1U)
+ #define RIIC_CFG_CH0_SLV_ADDR1_FORMAT (0U)
+ #define RIIC_CFG_CH0_SLV_ADDR2_FORMAT (0U)
+
+ #define RIIC_CFG_CH0_SLV_ADDR0 (0x0025)
+ #define RIIC_CFG_CH0_SLV_ADDR1 (0x0000)
+ #define RIIC_CFG_CH0_SLV_ADDR2 (0x0000)
+
+ #define RIIC_CFG_CH1_SLV_ADDR0_FORMAT (1U)
+ #define RIIC_CFG_CH1_SLV_ADDR1_FORMAT (0U)
+ #define RIIC_CFG_CH1_SLV_ADDR2_FORMAT (0U)
+
+ #define RIIC_CFG_CH1_SLV_ADDR0 (0x0025)
+ #define RIIC_CFG_CH1_SLV_ADDR1 (0x0000)
+ #define RIIC_CFG_CH1_SLV_ADDR2 (0x0000)
+
+ #define RIIC_CFG_CH2_SLV_ADDR0_FORMAT (1U)
+ #define RIIC_CFG_CH2_SLV_ADDR1_FORMAT (0U)
+ #define RIIC_CFG_CH2_SLV_ADDR2_FORMAT (0U)
+
+ #define RIIC_CFG_CH2_SLV_ADDR0 (0x0025)
+ #define RIIC_CFG_CH2_SLV_ADDR1 (0x0000)
+ #define RIIC_CFG_CH2_SLV_ADDR2 (0x0000)
+
+/* Select General call address */
+/* 0 = not use, 1 = use(General call address detection is enabled.) */
+ #define RIIC_CFG_CH0_SLV_GCA_ENABLE (0U)
+ #define RIIC_CFG_CH1_SLV_GCA_ENABLE (0U)
+ #define RIIC_CFG_CH2_SLV_GCA_ENABLE (0U)
+
+/* This #define sets the priority level for the riic interrupt */
+/* 1 lowest, 15 highest */
+/* The following devices can not individually specify the interrupt priority level for EEI0, TEI0, EEI2, TEI2. */
+/* EEI and TEI interrupts are grouped as the BL1 interrupt in the RX64M and RX71M group. */
+ #define RIIC_CFG_CH0_RXI_INT_PRIORITY (1U)
+ #define RIIC_CFG_CH0_TXI_INT_PRIORITY (1U)
+/* The priority level of the EEI, please do not lower than the priority level of TXI and RXI */
+ #define RIIC_CFG_CH0_EEI_INT_PRIORITY (1U)
+/* The priority level of the TEI, please do not lower than the priority level of TXI and RXI */
+ #define RIIC_CFG_CH0_TEI_INT_PRIORITY (1U)
+
+ #define RIIC_CFG_CH1_RXI_INT_PRIORITY (1U)
+ #define RIIC_CFG_CH1_TXI_INT_PRIORITY (1U)
+/* The priority level of the EEI, please do not lower than the priority level of TXI and RXI */
+ #define RIIC_CFG_CH1_EEI_INT_PRIORITY (1U)
+/* The priority level of the TEI, please do not lower than the priority level of TXI and RXI */
+ #define RIIC_CFG_CH1_TEI_INT_PRIORITY (1U)
+
+ #define RIIC_CFG_CH2_RXI_INT_PRIORITY (1U)
+ #define RIIC_CFG_CH2_TXI_INT_PRIORITY (1U)
+/* The priority level of the EEI, please do not lower than the priority level of TXI and RXI */
+ #define RIIC_CFG_CH2_EEI_INT_PRIORITY (1U)
+/* The priority level of the TEI, please do not lower than the priority level of TXI and RXI */
+ #define RIIC_CFG_CH2_TEI_INT_PRIORITY (1U)
+
+/* Select Timeout function enable or disable */
+/* 0 = disable, 1 = enable */
+ #define RIIC_CFG_CH0_TMO_ENABLE (1U)
+ #define RIIC_CFG_CH1_TMO_ENABLE (1U)
+ #define RIIC_CFG_CH2_TMO_ENABLE (1U)
+
+/* Select long mode or short mode for the timeout detection time */
+/* when the timeout function is enabled. */
+/* 0 = Long mode, 1 = short mode */
+ #define RIIC_CFG_CH0_TMO_DET_TIME (0U)
+ #define RIIC_CFG_CH1_TMO_DET_TIME (0U)
+ #define RIIC_CFG_CH2_TMO_DET_TIME (0U)
+
+/* Select enable or disable the internal counter of the timeout function to count up while the */
+/* SCL line is held LOW when the timeout function is enabled. */
+/* 0 = Count is disabled, 1 = Count is enabled */
+ #define RIIC_CFG_CH0_TMO_LCNT (1U)
+ #define RIIC_CFG_CH1_TMO_LCNT (1U)
+ #define RIIC_CFG_CH2_TMO_LCNT (1U)
+
+/* Select enable or disable the internal counter of the timeout function to count up while the */
+/* SCL line is held HIGH when the timeout function is enabled. */
+/* 0 = Count is disabled, 1 = Count is enabled */
+ #define RIIC_CFG_CH0_TMO_HCNT (1U)
+ #define RIIC_CFG_CH1_TMO_HCNT (1U)
+ #define RIIC_CFG_CH2_TMO_HCNT (1U)
+
+/* Define software bus busy check counter. */
+ #define RIIC_CFG_BUS_CHECK_COUNTER (1000U) /* Counter of checking bus busy */
+
+#endif /* RIIC_CONFIG_H */
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/r_config/r_riic_rx_pin_config.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/r_config/r_riic_rx_pin_config.h
new file mode 100644
index 00000000000..096aaf913b0
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/r_config/r_riic_rx_pin_config.h
@@ -0,0 +1,69 @@
+/***********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+ * No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO
+ * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved.
+ **********************************************************************************************************************/
+/***********************************************************************************************************************
+ * File Name : r_riic_rx_pin_config_reference.h
+ * Description : Pin configures the RIIC drivers
+ **********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ * : 04.03.2016 1.90 First Release
+ * : 02.06.2017 2.10 Deleted RIIC port definitions of RIIC3.
+ **********************************************************************************************************************/
+/* Guards against multiple inclusion */
+#ifndef RIIC_PIN_CONFIG_H
+ #define RIIC_PIN_CONFIG_H
+/***********************************************************************************************************************
+ Configuration Options
+ **********************************************************************************************************************/
+/*------------------------------------------------------------------------------*/
+/* Set using port as riic port */
+/*------------------------------------------------------------------------------*/
+/* Set using port as riic port. */
+/* If you want to include the port configuration process(RIIC_CFG_PORT_SET_PROCESSING is "1"), */
+/* please choose which ports to use for the SCL/SDA of RIIC with the following setting. */
+/* Select the port group and pin used by setting
+ "R_RIIC_CFG_RIICx_SCLx_PORT (select from port group 0 to J)"
+ and "R_RIIC_CFG_RIICx_SCLx_BIT (select from pin number 0 to 7)"
+ and "R_RIIC_CFG_RIICx_SDAx_PORT (select from port group 0 to J)"
+ and "R_RIIC_CFG_RIICx_SDAx_BIT (select from pin number 0 to 7)",
+ respectively. */
+
+/* Select the ports (SCL0 and SDA0) to use in RIIC0 */
+ #define R_RIIC_CFG_RIIC0_SCL0_PORT '1' /* Port Number */
+ #define R_RIIC_CFG_RIIC0_SCL0_BIT '2' /* Bit Number */
+
+ #define R_RIIC_CFG_RIIC0_SDA0_PORT '1' /* Port Number */
+ #define R_RIIC_CFG_RIIC0_SDA0_BIT '3' /* Bit Number */
+
+/* Select the ports (SCL1 and SDA1) to use in RIIC1 */
+ #define R_RIIC_CFG_RIIC1_SCL1_PORT '2' /* Port Number */
+ #define R_RIIC_CFG_RIIC1_SCL1_BIT '1' /* Bit Number */
+
+ #define R_RIIC_CFG_RIIC1_SDA1_PORT '2' /* Port Number */
+ #define R_RIIC_CFG_RIIC1_SDA1_BIT '0' /* Bit Number */
+
+/* Select the ports (SCL2 and SDA2) to use in RIIC2 */
+ #define R_RIIC_CFG_RIIC2_SCL2_PORT '1' /* Port Number */
+ #define R_RIIC_CFG_RIIC2_SCL2_BIT '6' /* Bit Number */
+
+ #define R_RIIC_CFG_RIIC2_SDA2_PORT '1' /* Port Number */
+ #define R_RIIC_CFG_RIIC2_SDA2_BIT '7' /* Bit Number */
+
+#endif /* RIIC_PIN_CONFIG_H */
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/r_config/r_sci_iic_rx_config.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/r_config/r_sci_iic_rx_config.h
new file mode 100644
index 00000000000..b4d82ee2a3c
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/r_config/r_sci_iic_rx_config.h
@@ -0,0 +1,190 @@
+/***********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+ * No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO
+ * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
+ **********************************************************************************************************************/
+/***********************************************************************************************************************
+ * File Name : r_sci_iic_rx_config.h
+ * Description : Configures the SCI IIC drivers
+ **********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ * : 01.07.2013 1.00 First Release
+ * : 30.09.2013 1.10 Change symbol of return value and status
+ * : 01.07.2014 1.20 RX110 support added.
+ * : 22.09.2014 1.30 RX64M support added.
+ * : 01.12.2014 1.40 RX113 support added.
+ * : 15.12.2014 1.50 RX71M support added.
+ * : 27.02.2015 1.60 RX63N support added.
+ * : 29.05.2015 1.70 RX231 support added.
+ * : 31.10.2015 1.80 RX130, RX230, RX23T support added.
+ * : 04.03.2016 1.90 RX24T support added.Changed about the pin definisions.
+ * : 01.10.2016 2.00 RX65N support added.
+ * : 31.08.2017 2.20 Changed the default value of the following macro definition.
+ * - SCI_IIC_CFG_CH1_INCLUDED
+ * RX24U,RX130-512 support added.
+ **********************************************************************************************************************/
+/* Guards against multiple inclusion */
+#ifndef SCI_IIC_CONFIG_H
+ #define SCI_IIC_CONFIG_H
+/***********************************************************************************************************************
+ Configuration Options
+ **********************************************************************************************************************/
+/* SPECIFY WHETHER TO INCLUDE CODE FOR API PARAMETER CHECKING */
+/* Setting to BSP_CFG_PARAM_CHECKING_ENABLE utilizes the system default setting */
+/* Setting to 1 includes parameter checking */
+/* 0 compiles out parameter checking */
+ #define SCI_IIC_CFG_PARAM_CHECKING_ENABLE (1)
+
+/* SPECIFY CHANNELS TO INCLUDE SOFTWARE SUPPORT FOR 1=included, 0=not */
+/* mcu supported channels */
+/* RX110 : , ch1, , , , ch5, , , , , , ,ch12 */
+/* RX111 : , ch1, , , , ch5, , , , , , ,ch12 */
+/* RX113 : ch0, ch1, ch2, , , ch5, ch6, , ch8, ch9, , ,ch12 */
+/* RX130 : ch0, ch1, , , , ch5, ch6, , ch8, ch9, , ,ch12 */
+/* RX230 : ch0, ch1, , , , ch5, ch6, , ch8, ch9, , ,ch12 */
+/* RX231 : ch0, ch1, , , , ch5, ch6, , ch8, ch9, , ,ch12 */
+/* RX23T : , ch1, , , , ch5, , , , , , , */
+/* RX24T : , ch1, , , , ch5, ch6, , , , , , */
+/* RX24U : , ch1, , , , ch5, ch6, , ch8, ch9, ,ch11, */
+/* RX63N : ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7, ch8, ch9,ch10,ch11,ch12 */
+/* RX64M : ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7, , , , ,ch12 */
+/* RX65N : ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7, ch8, ch9,ch10,ch11,ch12 */
+/* RX71M : ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7, , , , ,ch12 */
+/* Please change the definition value of channel to be used to '1'. */
+ #define SCI_IIC_CFG_CH0_INCLUDED (1)
+ #define SCI_IIC_CFG_CH1_INCLUDED (0)
+ #define SCI_IIC_CFG_CH2_INCLUDED (0)
+ #define SCI_IIC_CFG_CH3_INCLUDED (0)
+ #define SCI_IIC_CFG_CH4_INCLUDED (0)
+ #define SCI_IIC_CFG_CH5_INCLUDED (0)
+ #define SCI_IIC_CFG_CH6_INCLUDED (0)
+ #define SCI_IIC_CFG_CH7_INCLUDED (0)
+ #define SCI_IIC_CFG_CH8_INCLUDED (0)
+ #define SCI_IIC_CFG_CH9_INCLUDED (0)
+ #define SCI_IIC_CFG_CH10_INCLUDED (0)
+ #define SCI_IIC_CFG_CH11_INCLUDED (0)
+ #define SCI_IIC_CFG_CH12_INCLUDED (0)
+
+/* Set SCI IIC bps */
+/* 1K = 1000, 100K= 100000, Max:384k = 384000 */
+ #define SCI_IIC_CFG_CH0_BITRATE_BPS (384000)
+ #define SCI_IIC_CFG_CH1_BITRATE_BPS (384000)
+ #define SCI_IIC_CFG_CH2_BITRATE_BPS (384000)
+ #define SCI_IIC_CFG_CH3_BITRATE_BPS (384000)
+ #define SCI_IIC_CFG_CH4_BITRATE_BPS (384000)
+ #define SCI_IIC_CFG_CH5_BITRATE_BPS (384000)
+ #define SCI_IIC_CFG_CH6_BITRATE_BPS (384000)
+ #define SCI_IIC_CFG_CH7_BITRATE_BPS (384000)
+ #define SCI_IIC_CFG_CH8_BITRATE_BPS (384000)
+ #define SCI_IIC_CFG_CH9_BITRATE_BPS (384000)
+ #define SCI_IIC_CFG_CH10_BITRATE_BPS (384000)
+ #define SCI_IIC_CFG_CH11_BITRATE_BPS (384000)
+ #define SCI_IIC_CFG_CH12_BITRATE_BPS (384000)
+
+/* SET GROUP12 (RECEIVER ERROR) INTERRUPT PRIORITY; RX63N ONLY
+ This #define sets the priority level for the interrupt that handles
+ receiver overrun, framing, and parity errors for all SCI channels
+ on the RX63N. It is ignored for all other parts.
+ */
+/* 1 lowest, 15 highest */
+ #define SCI_IIC_CFG_CH0_INT_PRIORITY (2)
+ #define SCI_IIC_CFG_CH1_INT_PRIORITY (2)
+ #define SCI_IIC_CFG_CH2_INT_PRIORITY (2)
+ #define SCI_IIC_CFG_CH3_INT_PRIORITY (2)
+ #define SCI_IIC_CFG_CH4_INT_PRIORITY (2)
+ #define SCI_IIC_CFG_CH5_INT_PRIORITY (2)
+ #define SCI_IIC_CFG_CH6_INT_PRIORITY (2)
+ #define SCI_IIC_CFG_CH7_INT_PRIORITY (2)
+ #define SCI_IIC_CFG_CH8_INT_PRIORITY (2)
+ #define SCI_IIC_CFG_CH9_INT_PRIORITY (2)
+ #define SCI_IIC_CFG_CH10_INT_PRIORITY (2)
+ #define SCI_IIC_CFG_CH11_INT_PRIORITY (2)
+ #define SCI_IIC_CFG_CH12_INT_PRIORITY (2)
+
+/* Digital noise filter (NFEN bit).
+ 0 = Noise cancellation function for the SSCLn and SSDAn input signals is disabled.
+ 1 = Noise cancellation function for the SSCLn and SSDAn input signals is enable.
+ */
+ #define SCI_IIC_CFG_CH0_DIGITAL_FILTER (1)
+ #define SCI_IIC_CFG_CH1_DIGITAL_FILTER (1)
+ #define SCI_IIC_CFG_CH2_DIGITAL_FILTER (1)
+ #define SCI_IIC_CFG_CH3_DIGITAL_FILTER (1)
+ #define SCI_IIC_CFG_CH4_DIGITAL_FILTER (1)
+ #define SCI_IIC_CFG_CH5_DIGITAL_FILTER (1)
+ #define SCI_IIC_CFG_CH6_DIGITAL_FILTER (1)
+ #define SCI_IIC_CFG_CH7_DIGITAL_FILTER (1)
+ #define SCI_IIC_CFG_CH8_DIGITAL_FILTER (1)
+ #define SCI_IIC_CFG_CH9_DIGITAL_FILTER (1)
+ #define SCI_IIC_CFG_CH10_DIGITAL_FILTER (1)
+ #define SCI_IIC_CFG_CH11_DIGITAL_FILTER (1)
+ #define SCI_IIC_CFG_CH12_DIGITAL_FILTER (1)
+
+/* Noise Filter Setting Register (NFCS bit).
+ 001 = 1 = The clock signal divided by 1 is used with the noise filter.
+ 010 = 2 = The clock signal divided by 2 is used with the noise filter.
+ 011 = 3 = The clock signal divided by 4 is used with the noise filter.
+ 100 = 4 = The clock signal divided by 8 is used with the noise filter.
+ */
+ #define SCI_IIC_CFG_CH0_FILTER_CLOCK (1)
+ #define SCI_IIC_CFG_CH1_FILTER_CLOCK (1)
+ #define SCI_IIC_CFG_CH2_FILTER_CLOCK (1)
+ #define SCI_IIC_CFG_CH3_FILTER_CLOCK (1)
+ #define SCI_IIC_CFG_CH4_FILTER_CLOCK (1)
+ #define SCI_IIC_CFG_CH5_FILTER_CLOCK (1)
+ #define SCI_IIC_CFG_CH6_FILTER_CLOCK (1)
+ #define SCI_IIC_CFG_CH7_FILTER_CLOCK (1)
+ #define SCI_IIC_CFG_CH8_FILTER_CLOCK (1)
+ #define SCI_IIC_CFG_CH9_FILTER_CLOCK (1)
+ #define SCI_IIC_CFG_CH10_FILTER_CLOCK (1)
+ #define SCI_IIC_CFG_CH11_FILTER_CLOCK (1)
+ #define SCI_IIC_CFG_CH12_FILTER_CLOCK (1)
+
+/* I2C Mode Register 1 (IICDL bit).
+ 00001 = 1 = 0 to 1 cycle
+ 00010 = 2 = 1 to 2 cycles
+ 00011 = 3 = 2 to 3 cycles
+ 00100 = 4 = 3 to 4 cycles
+ 00101 = 5 = 4 to 5 cycles
+ |
+ 11110 = 30 = 29 to 30 cycles
+ 11111 = 31 = 30 to 31 cycles
+ */
+ #define SCI_IIC_CFG_CH0_SSDA_DELAY_SELECT (18)
+ #define SCI_IIC_CFG_CH1_SSDA_DELAY_SELECT (18)
+ #define SCI_IIC_CFG_CH2_SSDA_DELAY_SELECT (18)
+ #define SCI_IIC_CFG_CH3_SSDA_DELAY_SELECT (18)
+ #define SCI_IIC_CFG_CH4_SSDA_DELAY_SELECT (18)
+ #define SCI_IIC_CFG_CH5_SSDA_DELAY_SELECT (18)
+ #define SCI_IIC_CFG_CH6_SSDA_DELAY_SELECT (18)
+ #define SCI_IIC_CFG_CH7_SSDA_DELAY_SELECT (18)
+ #define SCI_IIC_CFG_CH8_SSDA_DELAY_SELECT (18)
+ #define SCI_IIC_CFG_CH9_SSDA_DELAY_SELECT (18)
+ #define SCI_IIC_CFG_CH10_SSDA_DELAY_SELECT (18)
+ #define SCI_IIC_CFG_CH11_SSDA_DELAY_SELECT (18)
+ #define SCI_IIC_CFG_CH12_SSDA_DELAY_SELECT (18)
+
+/* Define software bus busy check counter. */
+ #define SCI_IIC_CFG_BUS_CHECK_COUNTER (1000)
+
+/* Setting to port.
+ 1 = includes sci (simple iic)port setting processing
+ 0 = compiles out sci (simple iic)port setting processing
+ */
+ #define SCI_IIC_CFG_PORT_SETTING_PROCESSING (1)
+
+#endif /* SCI_IIC_CONFIG_H */
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/r_config/r_sci_iic_rx_pin_config.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/r_config/r_sci_iic_rx_pin_config.h
new file mode 100644
index 00000000000..afa717e46f5
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/r_config/r_sci_iic_rx_pin_config.h
@@ -0,0 +1,144 @@
+/***********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+ * No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO
+ * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved.
+ **********************************************************************************************************************/
+/***********************************************************************************************************************
+ * File Name : r_sci_iic_rx_pin_config_reference.h
+ * Description : Pin configures the SCI IIC drivers
+ **********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ * : 04.03.2016 1.90 First Release
+ * : 31.08.2017 2.20 Changed default value of macro definitions, below.
+ * : - R_SCI_IIC_CFG_SCI2_SSCL2_PORT
+ * : - R_SCI_IIC_CFG_SCI2_SSDA2_PORT, R_SCI_IIC_CFG_SCI2_SSDA2_BIT
+ * : - R_SCI_IIC_CFG_SCI3_SSCL3_PORT, R_SCI_IIC_CFG_SCI3_SSCL3_BIT
+ * : - R_SCI_IIC_CFG_SCI3_SSDA3_PORT, R_SCI_IIC_CFG_SCI3_SSDA3_BIT
+ * : - R_SCI_IIC_CFG_SCI5_SSCL5_PORT, R_SCI_IIC_CFG_SCI5_SSCL5_BIT
+ * : - R_SCI_IIC_CFG_SCI5_SSDA5_PORT, R_SCI_IIC_CFG_SCI5_SSDA5_BIT
+ * : - R_SCI_IIC_CFG_SCI6_SSCL6_BIT
+ * : - R_SCI_IIC_CFG_SCI6_SSDA6_BIT
+ **********************************************************************************************************************/
+/* Guards against multiple inclusion */
+#ifndef SCI_IIC_PIN_CONFIG_H
+ #define SCI_IIC_PIN_CONFIG_H
+/***********************************************************************************************************************
+ Configuration Options
+ **********************************************************************************************************************/
+/*------------------------------------------------------------------------------*/
+/* Set using port as sci iic port */
+/*------------------------------------------------------------------------------*/
+/* Select the port group and pin used by setting
+ "R_SCI_IIC_CFG_SCIx_SSCLx_PORT (select from port group 0 to J)"
+ and "R_SCI_IIC_CFG_SCIx_SSCLx_BIT (select from pin number 0 to 7)"
+ and "R_SCI_IIC_CFG_SCIx_SSDAx_PORT (select from port group 0 to J)"
+ and "R_SCI_IIC_CFG_SCIx_SSDAx_BIT (select from pin number 0 to 7)",
+ respectively. */
+
+/* Select the ports (SSCL0 and SSDA0) to use in SCI0 */
+ #define R_SCI_IIC_CFG_SCI0_SSCL0_PORT '2' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI0_SSCL0_BIT '1' /* Bit Number */
+
+ #define R_SCI_IIC_CFG_SCI0_SSDA0_PORT '2' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI0_SSDA0_BIT '0' /* Bit Number */
+
+/* Select the ports (SSCL1 and SSDA1) to use in SCI1 */
+ #define R_SCI_IIC_CFG_SCI1_SSCL1_PORT '1' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI1_SSCL1_BIT '5' /* Bit Number */
+
+ #define R_SCI_IIC_CFG_SCI1_SSDA1_PORT '1' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI1_SSDA1_BIT '6' /* Bit Number */
+
+/* Select the ports (SSCL2 and SSDA2) to use in SCI2 */
+ #define R_SCI_IIC_CFG_SCI2_SSCL2_PORT '1' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI2_SSCL2_BIT '2' /* Bit Number */
+
+ #define R_SCI_IIC_CFG_SCI2_SSDA2_PORT '1' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI2_SSDA2_BIT '3' /* Bit Number */
+
+/* Select the ports (SSCL3 and SSDA3) to use in SCI3 */
+ #define R_SCI_IIC_CFG_SCI3_SSCL3_PORT '1' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI3_SSCL3_BIT '6' /* Bit Number */
+
+ #define R_SCI_IIC_CFG_SCI3_SSDA3_PORT '1' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI3_SSDA3_BIT '7' /* Bit Number */
+
+/* Select the ports (SSCL4 and SSDA4) to use in SCI4 */
+ #define R_SCI_IIC_CFG_SCI4_SSCL4_PORT 'B' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI4_SSCL4_BIT '0' /* Bit Number */
+
+ #define R_SCI_IIC_CFG_SCI4_SSDA4_PORT 'B' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI4_SSDA4_BIT '1' /* Bit Number */
+
+/* Select the ports (SSCL5 and SSDA5) to use in SCI5 */
+ #define R_SCI_IIC_CFG_SCI5_SSCL5_PORT 'B' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI5_SSCL5_BIT '1' /* Bit Number */
+
+ #define R_SCI_IIC_CFG_SCI5_SSDA5_PORT 'B' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI5_SSDA5_BIT '2' /* Bit Number */
+
+/* Select the ports (SSCL6 and SSDA6) to use in SCI6 */
+ #define R_SCI_IIC_CFG_SCI6_SSCL6_PORT 'B' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI6_SSCL6_BIT '1' /* Bit Number */
+
+ #define R_SCI_IIC_CFG_SCI6_SSDA6_PORT 'B' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI6_SSDA6_BIT '2' /* Bit Number */
+
+/* Select the ports (SSCL7 and SSDA7) to use in SCI7 */
+ #define R_SCI_IIC_CFG_SCI7_SSCL7_PORT '9' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI7_SSCL7_BIT '2' /* Bit Number */
+
+ #define R_SCI_IIC_CFG_SCI7_SSDA7_PORT '9' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI7_SSDA7_BIT '0' /* Bit Number */
+
+/* Select the ports (SSCL8 and SSDA8) to use in SCI8 */
+ #define R_SCI_IIC_CFG_SCI8_SSCL8_PORT 'C' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI8_SSCL8_BIT '6' /* Bit Number */
+
+ #define R_SCI_IIC_CFG_SCI8_SSDA8_PORT 'C' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI8_SSDA8_BIT '7' /* Bit Number */
+
+/* Select the ports (SSCL9 and SSDA9) to use in SCI9 */
+ #define R_SCI_IIC_CFG_SCI9_SSCL9_PORT 'B' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI9_SSCL9_BIT '6' /* Bit Number */
+
+ #define R_SCI_IIC_CFG_SCI9_SSDA9_PORT 'B' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI9_SSDA9_BIT '7' /* Bit Number */
+
+/* Select the ports (SSCL10 and SSDA10) to use in SCI10 */
+ #define R_SCI_IIC_CFG_SCI10_SSCL10_PORT '8' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI10_SSCL10_BIT '1' /* Bit Number */
+
+ #define R_SCI_IIC_CFG_SCI10_SSDA10_PORT '8' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI10_SSDA10_BIT '2' /* Bit Number */
+
+/* Select the ports (SSCL11 and SSDA11) to use in SCI11 */
+ #define R_SCI_IIC_CFG_SCI11_SSCL11_PORT '7' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI11_SSCL11_BIT '6' /* Bit Number */
+
+ #define R_SCI_IIC_CFG_SCI11_SSDA11_PORT '7' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI11_SSDA11_BIT '7' /* Bit Number */
+
+/* Select the ports (SSCL12 and SSDA12) to use in SCI12 */
+ #define R_SCI_IIC_CFG_SCI12_SSCL12_PORT 'E' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI12_SSCL12_BIT '2' /* Bit Number */
+
+ #define R_SCI_IIC_CFG_SCI12_SSDA12_PORT 'E' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI12_SSDA12_BIT '1' /* Bit Number */
+
+#endif /* SCI_IIC_PIN_CONFIG_H */
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/r_config/r_sci_rx_config.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/r_config/r_sci_rx_config.h
new file mode 100644
index 00000000000..11bf22a292b
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/r_config/r_sci_rx_config.h
@@ -0,0 +1,171 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2013-2017 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : r_sci_rx_config.h
+* Description : Configures the SCI driver
+************************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* 25.09.2013 1.00 Initial Release
+* 17.04.2014 1.20 Added comments for new RX110 support.
+* 02.07.2014 1.30 Fixed bug that caused Group12 rx errors to only be enabled for channel 2.
+* 25.11.2014 1.40 Added comments for RX113 support
+* 30.09.2015 1.70 Added comments for RX23T support
+* 01.10.2016 1.80 Added support for RX65N (comments and TX/RX FIFO THRESHOLD options)
+* 19.12.2016 1.90 Added comments for RX24U support
+* 07.03.2017 2.00 Added comments for RX130-512KB support
+***********************************************************************************************************************/
+#ifndef SCI_CONFIG_H
+#define SCI_CONFIG_H
+
+#include "platform.h"
+
+/***********************************************************************************************************************
+Configuration Options
+***********************************************************************************************************************/
+
+/* SPECIFY WHETHER TO INCLUDE CODE FOR API PARAMETER CHECKING */
+/* Setting to BSP_CFG_PARAM_CHECKING_ENABLE utilizes the system default setting */
+/* Setting to 1 includes parameter checking; 0 compiles out parameter checking */
+#define SCI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+
+/* SPECIFY WHETHER TO INCLUDE CODE FOR DIFFERENT SCI MODES */
+/* Setting an equate to 1 includes code specific to that mode. */
+#define SCI_CFG_ASYNC_INCLUDED (1)
+#define SCI_CFG_SYNC_INCLUDED (0)
+#define SCI_CFG_SSPI_INCLUDED (0)
+
+/* SPECIFY BYTE VALUE TO TRANSMIT WHILE CLOCKING IN DATA IN SSPI MODES */
+#define SCI_CFG_DUMMY_TX_BYTE (0xFF)
+
+/* SPECIFY CHANNELS TO INCLUDE SOFTWARE SUPPORT FOR 1=included, 0=not */
+/*
+ * NOTE: If using ASYNC mode, adjust BYTEQ_CFG_MAX_CTRL_BLKS in r_byteq_config.h
+ * to provide 2 queues per channel (static mode only).
+ * * = port connector RDKRX63N, RSKRX210, RSKRX11x
+ * u = channel used by the USB-UART port (G1CUSB0)
+ * a = this channel is used only for RX130-512KB
+ * RX MCU supported channels
+ *
+ * CH# 110 111 113 130 210 230 231 23T 24T 24U 63N 631 64M 71M 65N
+ * --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- ---
+ * CH0 X Xa X* X X X* X X X X
+ * CH1 X X* X* Xu X X X Xu Xu Xu X X X X X
+ * CH2 X X X X X Xu
+ * CH3 X X X X X
+ * CH4 X X X X X
+ * CH5 X X X X X X Xu X X X X X X X X
+ * CH6 X X X X X X X X X X X X
+ * CH7 X X Xu Xu X
+ * CH8 X Xa X X X X X X X
+ * CH9 X Xa X X X X X X X
+ * CH10 X X X
+ * CH11 X X X X
+ * CH12 X X X X X X X X X X X X
+*/
+
+#define SCI_CFG_CH0_INCLUDED (0)
+#define SCI_CFG_CH1_INCLUDED (0)
+#define SCI_CFG_CH2_INCLUDED (1)
+#define SCI_CFG_CH3_INCLUDED (0)
+#define SCI_CFG_CH4_INCLUDED (0)
+#define SCI_CFG_CH5_INCLUDED (0)
+#define SCI_CFG_CH6_INCLUDED (1)
+#define SCI_CFG_CH7_INCLUDED (0)
+#define SCI_CFG_CH8_INCLUDED (1)
+#define SCI_CFG_CH9_INCLUDED (0)
+#define SCI_CFG_CH10_INCLUDED (0)
+#define SCI_CFG_CH11_INCLUDED (0)
+#define SCI_CFG_CH12_INCLUDED (0)
+
+/* SPECIFY ASYNC MODE TX QUEUE BUFFER SIZES (will not allocate if chan not enabled */
+#define SCI_CFG_CH0_TX_BUFSIZ (80)
+#define SCI_CFG_CH1_TX_BUFSIZ (80)
+#define SCI_CFG_CH2_TX_BUFSIZ (1000)
+#define SCI_CFG_CH3_TX_BUFSIZ (80)
+#define SCI_CFG_CH4_TX_BUFSIZ (80)
+#define SCI_CFG_CH5_TX_BUFSIZ (80)
+#define SCI_CFG_CH6_TX_BUFSIZ (1460)
+#define SCI_CFG_CH7_TX_BUFSIZ (80)
+#define SCI_CFG_CH8_TX_BUFSIZ (80)
+#define SCI_CFG_CH9_TX_BUFSIZ (80)
+#define SCI_CFG_CH10_TX_BUFSIZ (80)
+#define SCI_CFG_CH11_TX_BUFSIZ (80)
+#define SCI_CFG_CH12_TX_BUFSIZ (80)
+
+/* SPECIFY ASYNC MODE RX QUEUE BUFFER SIZES (will not allocate if chan not enabled */
+#define SCI_CFG_CH0_RX_BUFSIZ (80)
+#define SCI_CFG_CH1_RX_BUFSIZ (80)
+#define SCI_CFG_CH2_RX_BUFSIZ (1000)
+#define SCI_CFG_CH3_RX_BUFSIZ (80)
+#define SCI_CFG_CH4_RX_BUFSIZ (80)
+#define SCI_CFG_CH5_RX_BUFSIZ (80)
+#define SCI_CFG_CH6_RX_BUFSIZ (2048)
+#define SCI_CFG_CH7_RX_BUFSIZ (80)
+#define SCI_CFG_CH8_RX_BUFSIZ (80)
+#define SCI_CFG_CH9_RX_BUFSIZ (80)
+#define SCI_CFG_CH10_RX_BUFSIZ (80)
+#define SCI_CFG_CH11_RX_BUFSIZ (80)
+#define SCI_CFG_CH12_RX_BUFSIZ (80)
+
+/*
+* ENABLE TRANSMIT END INTERRUPT (ASYNCHRONOUS)
+* This interrupt only occurs when the last bit of the last byte of data
+* has been sent and the transmitter has become idle. The interrupt calls
+* the user's callback function specified in R_SCI_Open() and passes it an
+* SCI_EVT_TEI event. A typical use of this feature is to disable an external
+* transceiver to save power. It would then be up to the user's code to
+* re-enable the transceiver before sending again. Not including this feature
+* reduces code space used by the interrupt. Note that this equate is only
+* for including the TEI code. The interrupt itself must be enabled using an
+* R_SCI_Control(hdl, SCI_CMD_EN_TEI, NULL) call.
+*/
+#define SCI_CFG_TEI_INCLUDED (1) /* 1=included, 0=not */
+
+/*
+* SET GROUP12 (RECEIVER ERROR) INTERRUPT PRIORITY; RX63N/631 ONLY
+* This #define sets the priority level for the interrupt that handles
+* receiver overrun, framing, and parity errors for all SCI channels
+* on the RX63N/631. It is ignored for all other parts.
+*/
+#define SCI_CFG_RXERR_PRIORITY (3) /* (RX63N/631 ONLY) 1 lowest, 15 highest */
+
+/*
+* SET GROUPBL0 (ERI, TEI) INTERRUPT PRIORITY; RX64M/RX71M/RX65N ONLY
+* SET GROUPBL1, GROUPAL0 (ERI,TEI) INTERRUPT PRIORITY; RX65N ONLY
+* This sets the priority level for receiver overrun, framing, and parity errors
+* as well as TEI interrupts for all SCI channels.
+*/
+#define SCI_CFG_ERI_TEI_PRIORITY (3) /* (RX64M/RX71M/RX65N ONLY) 1 lowest, 15 highest */
+
+/* ENABLE TX/RX FIFO; (SCIi supported MCU ONLY) 1=included, 0=not */
+#define SCI_CFG_CH10_FIFO_INCLUDED (0)
+#define SCI_CFG_CH11_FIFO_INCLUDED (0)
+
+/* SET TX FIFO THRESHOLD; (SCIi supported MCU ONLY) 0 lowest, 15 highest */
+/* TX FIFO THRESHOLD is invalid in Clock Synchronous Mode and Simple SPI Mode. */
+/* Set the same value for TX FIFO THRESHOLD and RX FIFO THRESHOLD in Clock Synchronous Mode and Simple SPI Mode. */
+#define SCI_CFG_CH10_TX_FIFO_THRESH (8)
+#define SCI_CFG_CH11_TX_FIFO_THRESH (8)
+
+/* SET RX FIFO THRESHOLD; (SCIi supported MCU ONLY) 1 lowest, 15 highest */
+#define SCI_CFG_CH10_RX_FIFO_THRESH (8)
+#define SCI_CFG_CH11_RX_FIFO_THRESH (8)
+
+
+#endif /* SCI_CONFIG_H */
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/r_pincfg/Pin.c b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/r_pincfg/Pin.c
new file mode 100644
index 00000000000..9bdd2583a83
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/r_pincfg/Pin.c
@@ -0,0 +1,79 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) . All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name : Pin.c
+* Version : 1.0.2
+* Device(s) : R5F565NEDxFP
+* Description : This file implements SMC pin code generation.
+* Creation Date: 2018-08-29
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Pragma directive
+***********************************************************************************************************************/
+/* Start user code for pragma. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_macrodriver.h"
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#include "r_cg_userdefine.h"
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+/* Start user code for global. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+* Function Name: R_Pins_Create
+* Description : This function initializes Smart Configurator pins
+* Arguments : None
+* Return Value : None
+***********************************************************************************************************************/
+
+void R_Pins_Create(void)
+{
+ R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_MPC);
+
+ /* Set RXD6 pin */
+ MPC.P33PFS.BYTE = 0x0AU;
+ PORT3.PMR.BYTE |= 0x08U;
+
+ /* Set RXD12 pin */
+ MPC.PE2PFS.BYTE = 0x0CU;
+ PORTE.PMR.BYTE |= 0x04U;
+
+ /* Set TXD6 pin */
+ PORT3.PODR.BYTE |= 0x04U;
+ MPC.P32PFS.BYTE = 0x0AU;
+ PORT3.PDR.BYTE |= 0x04U;
+
+ /* Set TXD12 pin */
+ PORTE.PODR.BYTE |= 0x02U;
+ MPC.PE1PFS.BYTE = 0x0CU;
+ PORTE.PDR.BYTE |= 0x02U;
+
+ R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_MPC);
+}
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/r_pincfg/Pin.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/r_pincfg/Pin.h
new file mode 100644
index 00000000000..97fef573eff
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/r_pincfg/Pin.h
@@ -0,0 +1,50 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) . All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name : Pin.h
+* Version : 1.0.2
+* Device(s) : R5F565NEDxFP
+* Description : This file implements SMC pin code generation.
+* Creation Date: 2018-08-29
+***********************************************************************************************************************/
+
+#ifndef PIN_H
+#define PIN_H
+
+/***********************************************************************************************************************
+Macro definitions (Register bit)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Global functions
+***********************************************************************************************************************/
+void R_Pins_Create(void);
+/* Start user code for function. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#endif
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/r_pincfg/r_pinset.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/r_pincfg/r_pinset.h
new file mode 100644
index 00000000000..fc669bdb499
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/r_pincfg/r_pinset.h
@@ -0,0 +1,34 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2018 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : r_pinset.h.h
+* Version : 1.0.1
+* Description : Declares all pin code headers into a single file
+* Creation Date: 2018-08-29
+***********************************************************************************************************************/
+
+#ifndef R_PINSET_H
+#define R_PINSET_H
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_sci_rx_pinset.h"
+
+#endif /* R_PINSET_H */
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/r_pincfg/r_sci_rx_pinset.c b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/r_pincfg/r_sci_rx_pinset.c
new file mode 100644
index 00000000000..0b9c987cfc2
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/r_pincfg/r_sci_rx_pinset.c
@@ -0,0 +1,79 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2018 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : r_sci_rx_pinset.c
+* Version : 1.0.2
+* Device(s) : R5F565NEDxFP
+* Tool-Chain : RXC toolchain
+* Description : Setting of port and mpc registers
+* Creation Date: 2018-08-29
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_sci_rx_pinset.h"
+#include "platform.h"
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* Function Name: R_SCI_PinSet_SCI6
+* Description : This function initializes pins for r_sci_rx module
+* Arguments : none
+* Return Value : none
+***********************************************************************************************************************/
+void R_SCI_PinSet_SCI6()
+{
+ R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_MPC);
+
+ /* Set RXD6/SMISO6 pin */
+ MPC.P33PFS.BYTE = 0x0AU;
+ PORT3.PMR.BIT.B3 = 1U;
+
+ /* Set TXD6/SMOSI6 pin */
+ MPC.P32PFS.BYTE = 0x0AU;
+ PORT3.PMR.BIT.B2 = 1U;
+
+ R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_MPC);
+}
+
+/***********************************************************************************************************************
+* Function Name: R_SCI_PinSet_SCI12
+* Description : This function initializes pins for r_sci_rx module
+* Arguments : none
+* Return Value : none
+***********************************************************************************************************************/
+void R_SCI_PinSet_SCI12()
+{
+ R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_MPC);
+
+ /* Set RXD12/SMISO12 pin */
+ MPC.PE2PFS.BYTE = 0x0CU;
+ PORTE.PMR.BIT.B2 = 1U;
+
+ /* Set TXD12/SMOSI12 pin */
+ MPC.PE1PFS.BYTE = 0x0CU;
+ PORTE.PMR.BIT.B1 = 1U;
+
+ R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_MPC);
+}
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/r_pincfg/r_sci_rx_pinset.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/r_pincfg/r_sci_rx_pinset.h
new file mode 100644
index 00000000000..59b1cd9cd0e
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/ccrx-e2studio/src/smc_gen/r_pincfg/r_sci_rx_pinset.h
@@ -0,0 +1,42 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2018 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : r_sci_rx_pinset.h
+* Version : 1.0.2
+* Device(s) : R5F565NEDxFP
+* Tool-Chain : RXC toolchain
+* Description : Setting of port and mpc registers
+* Creation Date: 2018-08-29
+***********************************************************************************************************************/
+
+#ifndef R_SCI_RX_H
+#define R_SCI_RX_H
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+
+void R_SCI_PinSet_SCI6();
+void R_SCI_PinSet_SCI12();
+
+#endif
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/application_code/entropy_hardware_poll.c b/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/application_code/entropy_hardware_poll.c
new file mode 100644
index 00000000000..e524b009d69
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/application_code/entropy_hardware_poll.c
@@ -0,0 +1,94 @@
+/**
+ ******************************************************************************
+ * @file entropy_hardware_poll.c
+ *
+ ******************************************************************************
+ */
+
+#include
+#include "FreeRTOS.h"
+
+int mbedtls_hardware_poll( void *data, unsigned char *output, size_t len, size_t *olen );
+void get_random_number(uint8_t *data, uint32_t len);
+
+int mbedtls_hardware_poll( void *data,
+ unsigned char *output, size_t len, size_t *olen )
+{
+ uint32_t random_number = 0;
+
+ get_random_number(&random_number, sizeof(uint32_t));
+ ((void) data);
+ *olen = 0;
+
+ memcpy(output, &random_number, sizeof(uint32_t));
+ *olen = sizeof(uint32_t);
+
+ return 0;
+}
+
+/******************************************************************************
+Functions : random number generator(XorShift method)
+******************************************************************************/
+void get_random_number(uint8_t *data, uint32_t len)
+{
+ static uint32_t y = 2463534242;
+ uint32_t res;
+ uint32_t lp;
+ uint8_t *bPtr;
+
+ res = len / 4;
+ for (lp = 0; lp < res; lp++)
+ {
+ y = y ^ (y << 13);
+ y = y ^ (y >> 17);
+ y = y ^ (y << 5);
+ bPtr = (uint8_t*) & y;
+#if __LIT
+ *((uint32_t *)data) = (*(bPtr + 3) << 24) | (*(bPtr + 2) << 16) | (*(bPtr + 1) << 8) | *(bPtr + 0);
+#else
+ *((uint32_t *)data) = y;
+#endif
+ data += 4;
+ }
+ y = y ^ (y << 13);
+ y = y ^ (y >> 17);
+ y = y ^ (y << 5);
+ res = (uint32_t)len % 4;
+ bPtr = (uint8_t*) & y;
+ switch (res)
+ {
+ case 3:
+#if __LIT
+ *data++ = bPtr[3];
+ *data++ = bPtr[2];
+ *data++ = bPtr[1];
+#else
+ *data++ = bPtr[0];
+ *data++ = bPtr[1];
+ *data++ = bPtr[2];
+#endif
+ break;
+
+ case 2:
+#if __LIT
+ *data++ = bPtr[3];
+ *data++ = bPtr[2];
+#else
+ *data++ = bPtr[0];
+ *data++ = bPtr[1];
+#endif
+ break;
+
+ case 1:
+#if __LIT
+ *data++ = bPtr[3];
+#else
+ *data++ = bPtr[0];
+#endif
+ break;
+
+ default:
+ /* no op */
+ break;
+ }
+}
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/application_code/freertos_usr_func.c b/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/application_code/freertos_usr_func.c
new file mode 100644
index 00000000000..5befac7a7ca
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/application_code/freertos_usr_func.c
@@ -0,0 +1,408 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : freertos_usr_func.c
+* Version : 1.0
+* Description : Contains FreeRTOS user-defined functions.
+******************************************************************************/
+/*****************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 30.06.2016 1.00 First Release
+******************************************************************************/
+
+/******************************************************************************
+Includes , "Project Includes"
+******************************************************************************/
+#include
+#include "platform.h"
+#include "FreeRTOS.h"
+#include "task.h"
+
+
+#if (BSP_CFG_RTOS_USED == 1)
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables (to be accessed by other files)
+******************************************************************************/
+
+/************* semaphore initialization *****************/
+
+
+/************* mutex initialization *********************/
+
+
+/************** queues initialization *******************/
+
+
+/************** event groups initialization *************/
+
+
+/************** mailbox initialization ******************/
+
+
+/************** memory pool initialization **************/
+
+
+/************** task initialization *********************/
+
+
+/* FreeRTOS's system timer. */
+void vApplicationSetupTimerInterrupt(void);
+
+/* Hook functions used by FreeRTOS. */
+void vAssertCalled(void);
+void vApplicationIdleHook(void);
+void vApplicationTickHook(void);
+void vApplicationMallocFailedHook(void);
+void vApplicationStackOverflowHook(TaskHandle_t xTask, signed char *pcTaskName);
+
+/* FreeRTOS's processing before start the kernel. */
+void Processing_Before_Start_Kernel(void);
+
+/* Main task. */
+extern void main(void *pvParameters);
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: vApplicationSetupTimerInterrupt
+* Description : Initialize system timer for FreeRTOS with tick interrupt 1ms.
+* Arguments : None.
+* Return Value : None.
+******************************************************************************/
+void vApplicationSetupTimerInterrupt(void)
+{
+ /* CMT channel 0 is configured as RTOS's system timer. */
+#if (BSP_CFG_RTOS_SYSTEM_TIMER == 0)
+ /* Protect off. */
+ SYSTEM.PRCR.WORD = 0xA502;
+
+ /* Enable compare match timer 0. */
+ MSTP( CMT0 ) = 0;
+
+ /* Stop counter. */
+ CMT.CMSTR0.BIT.STR0 = 0;
+
+ /* Protect on. */
+ SYSTEM.PRCR.WORD = 0xA500;
+
+ /* Enable interrupt on compare match.
+ * Divide the PCLK by 8. */
+ CMT0.CMCR.WORD = 0x00C0; // CKS=00b,CMIE=1; PCLK/8,Compare match interrupt (CMIn) enabled @60MHz
+
+ /* Set the compare match value. */
+ CMT0.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ )) / 8 - 1);
+
+ /* Clear counter. */
+ CMT0.CMCNT = 0;
+
+ /* Clear any previously pending interrupts. */
+ IR(CMT0, CMI0) = 0;
+
+ /* Enable the interrupt. */
+ IEN(CMT0, CMI0) = 1;
+
+ /* Set its priority to the application defined kernel priority. */
+ IPR(CMT0, CMI0) = configKERNEL_INTERRUPT_PRIORITY;
+
+ /* Start the timer 0. */
+ CMT.CMSTR0.BIT.STR0 = 1;
+#endif /* (BSP_CFG_RTOS_SYSTEM_TIMER == 0) */
+
+ /* CMT channel 1 is configured as RTOS's system timer. */
+#if (BSP_CFG_RTOS_SYSTEM_TIMER == 1)
+ /* Protect off. */
+ SYSTEM.PRCR.WORD = 0xA502;
+
+ /* Enable compare match timer 1. */
+ MSTP( CMT1 ) = 0;
+
+ /* Stop counter. */
+ CMT.CMSTR0.BIT.STR1 = 0;
+
+ /* Protect on. */
+ SYSTEM.PRCR.WORD = 0xA500;
+
+ /* Enable interrupt on compare match.
+ * Divide the PCLK by 8. */
+ CMT1.CMCR.WORD = 0x00C0; // CKS=00b,CMIE=1; PCLK/8,Compare match interrupt (CMIn) enabled @60MHz
+
+ /* Set the compare match value. */
+ CMT1.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ )) / 8 - 1);
+
+ /* Clear counter. */
+ CMT1.CMCNT = 0;
+
+ /* Clear any previously pending interrupts. */
+ IR(CMT1, CMI1) = 0;
+
+ /* Enable the interrupt. */
+ IEN(CMT1, CMI1) = 1;
+
+ /* Set its priority to the application defined kernel priority. */
+ IPR(CMT1, CMI1) = configKERNEL_INTERRUPT_PRIORITY;
+
+ /* Start the timer 1. */
+ CMT.CMSTR0.BIT.STR1 = 1;
+#endif /* (BSP_CFG_RTOS_SYSTEM_TIMER == 1) */
+
+ /* CMT channel 2 is configured as RTOS's system timer. */
+#if (BSP_CFG_RTOS_SYSTEM_TIMER == 2)
+ /* Protect off. */
+ SYSTEM.PRCR.WORD = 0xA502;
+
+ /* Enable compare match timer 2. */
+ MSTP( CMT2 ) = 0;
+
+ /* Stop counter. */
+ CMT.CMSTR1.BIT.STR2 = 0;
+
+ /* Protect on. */
+ SYSTEM.PRCR.WORD = 0xA500;
+
+ /* Enable interrupt on compare match.
+ * Divide the PCLK by 8. */
+ CMT2.CMCR.WORD = 0x00C0; // CKS=00b,CMIE=1; PCLK/8,Compare match interrupt (CMIn) enabled @60MHz
+
+ /* Set the compare match value. */
+ CMT2.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ )) / 8 - 1);
+
+ /* Clear counter. */
+ CMT2.CMCNT = 0;
+
+ /* Clear any previously pending interrupts. */
+ IR(CMT2, CMI2) = 0;
+
+ /* Enable the interrupt. */
+ IEN(CMT2, CMI2) = 1;
+
+ /* Set its priority to the application defined kernel priority. */
+ IPR(CMT2, CMI2) = configKERNEL_INTERRUPT_PRIORITY;
+
+ /* Start the timer 2. */
+ CMT.CMSTR1.BIT.STR2 = 1;
+#endif /* (BSP_CFG_RTOS_SYSTEM_TIMER == 2) */
+
+ /* CMT channel 3 is configured as RTOS's system timer. */
+#if (BSP_CFG_RTOS_SYSTEM_TIMER == 3)
+ /* Protect off. */
+ SYSTEM.PRCR.WORD = 0xA502;
+
+ /* Enable compare match timer 3. */
+ MSTP( CMT3 ) = 0;
+
+ /* Stop counter. */
+ CMT.CMSTR1.BIT.STR3 = 0;
+
+ /* Protect on. */
+ SYSTEM.PRCR.WORD = 0xA500;
+
+ /* Enable interrupt on compare match.
+ * Divide the PCLK by 8. */
+ CMT3.CMCR.WORD = 0x00C0; // CKS=00b,CMIE=1; PCLK/8,Compare match interrupt (CMIn) enabled @60MHz
+
+ /* Set the compare match value. */
+ CMT3.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ )) / 8 - 1);
+
+ /* Clear counter. */
+ CMT3.CMCNT = 0;
+
+ /* Clear any previously pending interrupts. */
+ IR(CMT3, CMI3) = 0;
+
+ /* Enable the interrupt. */
+ IEN(CMT3, CMI3) = 1;
+
+ /* Set its priority to the application defined kernel priority. */
+ IPR(CMT3, CMI3) = configKERNEL_INTERRUPT_PRIORITY;
+
+ /* Start the timer 3. */
+ CMT.CMSTR1.BIT.STR3 = 1;
+#endif /* (BSP_CFG_RTOS_SYSTEM_TIMER == 3) */
+
+} /* End of function vApplicationSetupTimerInterrupt() */
+
+/******************************************************************************
+* Function Name: vAssertCalled
+* Description : This function is used to validate the input parameters.
+* Arguments : None.
+* Return Value : None.
+******************************************************************************/
+void vAssertCalled(void)
+{
+#if(0)
+ TEST_ABORT(); // XXX unity testing
+ volatile unsigned long ul = 0;
+
+ taskENTER_CRITICAL();
+ {
+ /* Use the debugger to set ul to a non-zero value in order to step out
+ of this function to determine why it was called. */
+ while( 0 == ul )
+ {
+ portNOP();
+ }
+ }
+ taskEXIT_CRITICAL();
+#endif
+
+} /* End of function vAssertCalled() */
+
+/******************************************************************************
+* Function Name: vApplicationIdleHook
+* Description : This function will be called on each cycle of the idle task.
+* NOTE: vApplicationIdleHook() MUST NOT CALL A FUNCTION
+* THAT MIGHT BLOCK UNDER ANY CIRCUMSTANCES.
+* Arguments : None.
+* Return Value : None.
+******************************************************************************/
+void vApplicationIdleHook(void)
+{
+ /* Implement user-code for user own purpose. */
+
+ static TickType_t xLastPrint = 0;
+ TickType_t xTimeNow;
+ const TickType_t xPrintFrequency = pdMS_TO_TICKS( 5000 );
+
+ xTimeNow = xTaskGetTickCount();
+
+ if( ( xTimeNow - xLastPrint ) > xPrintFrequency )
+ {
+ configPRINT_STRING(("."));
+ xLastPrint = xTimeNow;
+ }
+
+} /* End of function vApplicationIdleHook() */
+
+/******************************************************************************
+* Function Name: vApplicationTickHook
+* Description : This function will be called every tick interrupt.
+* NOTE: vApplicationTickHook() EXECUTES FROM WITHIN AN ISR,
+* SO MUST BE VERY SHORT AND NOT USE MUCH STACK.
+* IN ADDITION, NOT CALL ANY APIs WITHOUT "FromISR" OR
+* "FROM_ISR" AT THE END.
+* Arguments : None.
+* Return Value : None.
+******************************************************************************/
+void vApplicationTickHook(void)
+{
+ /* Implement user-code for user own purpose. */
+
+} /* End of function vApplicationTickHook() */
+
+/******************************************************************************
+* Function Name: vApplicationMallocFailedHook
+* Description : This function is to capture the failure while
+* memory allocation.
+* Arguments : None.
+* Return Value : None.
+******************************************************************************/
+void vApplicationMallocFailedHook(void)
+{
+ /* Called if a call to pvPortMalloc() fails because there is insufficient
+ free memory available in the FreeRTOS heap. pvPortMalloc() is called
+ internally by FreeRTOS API functions that create tasks, queues, software
+ timers, and semaphores. The size of the FreeRTOS heap is set by the
+ configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */
+
+ taskDISABLE_INTERRUPTS();
+ for( ; ; )
+ {
+ /* Loop here */
+ };
+
+} /* End of function vApplicationMallocFailedHook() */
+
+/******************************************************************************
+* Function Name: vApplicationStackOverflowHook
+* Description : Hook function is to capture the failure when the stack size
+* is insufficient for processing.
+* Arguments : pxTask -
+* Task handler
+* pcTaskName -
+* Pointer of where to store the task's name
+* Return Value : None.
+******************************************************************************/
+void vApplicationStackOverflowHook(TaskHandle_t pxTask, signed char *pcTaskName)
+{
+ ( void ) pcTaskName;
+ ( void ) pxTask;
+
+ /* Run time stack overflow checking is performed if
+ configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook
+ function is called if a stack overflow is detected. */
+
+ taskDISABLE_INTERRUPTS();
+ for( ; ; )
+ {
+ /* Loop here */
+ };
+
+} /* End of function vApplicationStackOverflowHook() */
+
+/******************************************************************************
+* Function Name : Processing_Before_Start_Kernel
+* Description : Create a main task, FreeRTOS's objects (e.g. mailbox, task,
+* semaphore, mutex...) if required.
+* Arguments : None.
+* Return value : None.
+******************************************************************************/
+void Processing_Before_Start_Kernel(void)
+{
+ BaseType_t ret;
+
+ /************** task creation ****************************/
+ /* Main task. */
+ ret = xTaskCreate(main, "MAIN_TASK", 512, NULL, 3, NULL);
+ if (pdPASS != ret)
+ {
+ while(1)
+ {
+ /* Failed! Task can not be created. */
+ }
+ }
+} /* End of function Processing_Before_Start_Kernel() */
+
+#endif /* (BSP_CFG_RTOS_USED == 1) */
+
+
+#if ( ipconfigUSE_LLMNR != 0 ) || ( ipconfigUSE_NBNS != 0 ) || ( ipconfigDHCP_REGISTER_HOSTNAME == 1 )
+
+const char * pcApplicationHostnameHook( void )
+{
+ /* Assign the name "FreeRTOS" to this network node. This function will
+ * be called during the DHCP: the machine will be registered with an IP
+ * address plus this name. */
+ return "RX65N_FREERTOS_TCP_TEST";
+}
+#endif
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/application_code/freertos_usr_func.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/application_code/freertos_usr_func.h
new file mode 100644
index 00000000000..34de1f58b03
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/application_code/freertos_usr_func.h
@@ -0,0 +1,74 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : freertos_usr_func.h
+* Version : 1.0
+* Description : FreeRTOS's user-defined functions header file.
+******************************************************************************/
+/*****************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 30.06.2016 1.00 First Release
+******************************************************************************/
+
+#ifndef RTOS_FREERTOS_FREERTOS_USR_FUNC_H_
+#define RTOS_FREERTOS_FREERTOS_USR_FUNC_H_
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables
+******************************************************************************/
+/************* semaphore handler *****************/
+
+
+
+/************* mutex handler *********************/
+
+
+/************** queues handler *******************/
+
+
+/************** event groups handler *************/
+
+
+/************** mailbox handler ******************/
+
+
+/************** memory pool handler **************/
+
+
+/************** task handler *********************/
+
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+extern void Processing_Before_Start_Kernel(void);
+
+#endif /* RTOS_FREERTOS_FREERTOS_USR_FUNC_H_ */
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/application_code/helper.c b/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/application_code/helper.c
new file mode 100644
index 00000000000..a8adf6d8f0e
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/application_code/helper.c
@@ -0,0 +1,20 @@
+#include "FreeRTOS.h"
+#include "aws_application_version.h"
+
+/* Declare the firmware version structure for all to see. */
+const AppVersion32_t xAppFirmwareVersion = {
+ .u.x.ucMajor = APP_VERSION_MAJOR,
+ .u.x.ucMinor = APP_VERSION_MINOR,
+ .u.x.usBuild = APP_VERSION_BUILD,
+};
+
+/* CC-RX's user define function */
+void abort( void )
+{
+ for(;;){}
+}
+
+/* Logging task */
+void vMainUARTPrintString( char * pcString )
+{
+}
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/application_code/main.c b/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/application_code/main.c
new file mode 100644
index 00000000000..e9a49ea4e81
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/application_code/main.c
@@ -0,0 +1,280 @@
+/*
+Amazon FreeRTOS
+Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy of
+this software and associated documentation files (the "Software"), to deal in
+the Software without restriction, including without limitation the rights to
+use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+the Software, and to permit persons to whom the Software is furnished to do so,
+subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+ http://aws.amazon.com/freertos
+ http://www.FreeRTOS.org
+*/
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include
+#include
+
+/* Renesas */
+#include "serial_term_uart.h"
+
+/* Demo includes */
+#include "aws_demo_runner.h"
+
+/* Aws Library Includes includes. */
+#include "aws_system_init.h"
+#include "aws_wifi.h"
+#include "aws_clientcredential.h"
+
+#define mainLOGGING_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE * 6 )
+#define mainLOGGING_MESSAGE_QUEUE_LENGTH ( 15 )
+#define mainTEST_RUNNER_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE * 8 )
+
+/* The MAC address array is not declared const as the MAC address will
+normally be read from an EEPROM and not hard coded (in real deployed
+applications).*/
+static uint8_t ucMACAddress[ 6 ] =
+{
+ configMAC_ADDR0,
+ configMAC_ADDR1,
+ configMAC_ADDR2,
+ configMAC_ADDR3,
+ configMAC_ADDR4,
+ configMAC_ADDR5
+}; //XXX
+
+/* Define the network addressing. These parameters will be used if either
+ipconfigUDE_DHCP is 0 or if ipconfigUSE_DHCP is 1 but DHCP auto configuration
+failed. */
+static const uint8_t ucIPAddress[ 4 ] =
+{
+ configIP_ADDR0,
+ configIP_ADDR1,
+ configIP_ADDR2,
+ configIP_ADDR3
+};
+static const uint8_t ucNetMask[ 4 ] =
+{
+ configNET_MASK0,
+ configNET_MASK1,
+ configNET_MASK2,
+ configNET_MASK3
+};
+static const uint8_t ucGatewayAddress[ 4 ] =
+{
+ configGATEWAY_ADDR0,
+ configGATEWAY_ADDR1,
+ configGATEWAY_ADDR2,
+ configGATEWAY_ADDR3
+};
+
+/* The following is the address of an OpenDNS server. */
+static const uint8_t ucDNSServerAddress[ 4 ] =
+{
+ configDNS_SERVER_ADDR0,
+ configDNS_SERVER_ADDR1,
+ configDNS_SERVER_ADDR2,
+ configDNS_SERVER_ADDR3
+};
+
+/**
+ * @brief Application task startup hook.
+ */
+void vApplicationDaemonTaskStartupHook( void );
+
+/**
+ * @brief Connects to WiFi.
+ */
+static void prvWifiConnect( void );
+
+/**
+ * @brief Initializes the board.
+ */
+static void prvMiscInitialization( void );
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Application runtime entry point.
+ */
+int main( void )
+{
+ /* Perform any hardware initialization that does not require the RTOS to be
+ * running. */
+
+ /* Start the scheduler. Initialization that requires the OS to be running,
+ * including the WiFi initialization, is performed in the RTOS daemon task
+ * startup hook. */
+ // vTaskStartScheduler();
+
+ while(1)
+ {
+ vTaskDelay(10000);
+ }
+
+ return 0;
+}
+/*-----------------------------------------------------------*/
+
+static void prvMiscInitialization( void )
+{
+ /* FIX ME. */
+ uart_config();
+ //configPRINT_STRING(("Hello World.\r\n"));
+ /* Start logging task. */
+ xLoggingTaskInitialize( mainLOGGING_TASK_STACK_SIZE,
+ tskIDLE_PRIORITY,
+ mainLOGGING_MESSAGE_QUEUE_LENGTH );
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationDaemonTaskStartupHook( void )
+{
+ prvMiscInitialization();
+
+ if( SYSTEM_Init() == pdPASS )
+ {
+#if(0)
+ /* Initialise the RTOS's TCP/IP stack. The tasks that use the network
+ are created in the vApplicationIPNetworkEventHook() hook function
+ below. The hook function is called when the network connects. */
+ FreeRTOS_IPInit( ucIPAddress,
+ ucNetMask,
+ ucGatewayAddress,
+ ucDNSServerAddress,
+ ucMACAddress );
+#endif
+
+ /* Connect to the wifi before running the demos */
+ prvWifiConnect();
+
+
+ /* Run all demos. */
+ DEMO_RUNNER_RunDemos();
+#if(0)
+ /* Create the task to run tests. */
+ xTaskCreate( TEST_RUNNER_RunTests_task,
+ "RunTests_task",
+ mainTEST_RUNNER_TASK_STACK_SIZE,
+ NULL,
+ tskIDLE_PRIORITY,
+ NULL );
+#endif
+ }
+}
+/*-----------------------------------------------------------*/
+
+#if(1)
+void prvWifiConnect( void )
+{
+ WIFINetworkParams_t xJoinAPParams;
+ WIFIReturnCode_t xWifiStatus;
+
+ xWifiStatus = WIFI_On();
+
+ if( xWifiStatus == eWiFiSuccess )
+ {
+ configPRINTF( ( "WiFi module initialized. Connecting to AP...\r\n" ) );
+ }
+ else
+ {
+ configPRINTF( ( "WiFi module failed to initialize.\r\n" ) );
+
+ while( 1 )
+ {
+ }
+ }
+
+ /* Setup parameters. */
+ xJoinAPParams.pcSSID = clientcredentialWIFI_SSID;
+ xJoinAPParams.pcPassword = clientcredentialWIFI_PASSWORD;
+ xJoinAPParams.xSecurity = clientcredentialWIFI_SECURITY;
+
+ xWifiStatus = WIFI_ConnectAP( &( xJoinAPParams ) );
+
+ if( xWifiStatus == eWiFiSuccess )
+ {
+ configPRINTF( ( "WiFi Connected to AP. Creating tasks which use network...\r\n" ) );
+ }
+ else
+ {
+ configPRINTF( ( "WiFi failed to connect to AP.\r\n" ) );
+
+ while( 1 )
+ {
+ }
+ }
+}
+#endif
+/*-----------------------------------------------------------*/
+
+/* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide an
+ * implementation of vApplicationGetIdleTaskMemory() to provide the memory that is
+ * used by the Idle task. */
+void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,
+ StackType_t ** ppxIdleTaskStackBuffer,
+ uint32_t * pulIdleTaskStackSize )
+{
+/* If the buffers to be provided to the Idle task are declared inside this
+ * function then they must be declared static - otherwise they will be allocated on
+ * the stack and so not exists after this function exits. */
+ static StaticTask_t xIdleTaskTCB;
+ static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ];
+
+ /* Pass out a pointer to the StaticTask_t structure in which the Idle
+ * task's state will be stored. */
+ *ppxIdleTaskTCBBuffer = &xIdleTaskTCB;
+
+ /* Pass out the array that will be used as the Idle task's stack. */
+ *ppxIdleTaskStackBuffer = uxIdleTaskStack;
+
+ /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer.
+ * Note that, as the array is necessarily of type StackType_t,
+ * configMINIMAL_STACK_SIZE is specified in words, not bytes. */
+ *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
+}
+/*-----------------------------------------------------------*/
+
+/* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide an
+ * implementation of vApplicationGetTimerTaskMemory() to provide the memory that is
+ * used by the RTOS daemon/time task. */
+void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer,
+ StackType_t ** ppxTimerTaskStackBuffer,
+ uint32_t * pulTimerTaskStackSize )
+{
+/* If the buffers to be provided to the Timer task are declared inside this
+ * function then they must be declared static - otherwise they will be allocated on
+ * the stack and so not exists after this function exits. */
+ static StaticTask_t xTimerTaskTCB;
+ static StackType_t uxTimerTaskStack[ configMINIMAL_STACK_SIZE ];
+
+ /* Pass out a pointer to the StaticTask_t structure in which the Idle
+ * task's state will be stored. */
+ *ppxTimerTaskTCBBuffer = &xTimerTaskTCB;
+
+ /* Pass out the array that will be used as the Timer task's stack. */
+ *ppxTimerTaskStackBuffer = uxTimerTaskStack;
+
+ /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer.
+ * Note that, as the array is necessarily of type StackType_t,
+ * configMINIMAL_STACK_SIZE is specified in words, not bytes. */
+ *pulTimerTaskStackSize = configMINIMAL_STACK_SIZE;
+}
+/*-----------------------------------------------------------*/
+
+
+
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/application_code/renesas_code/placeholder.txt b/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/application_code/renesas_code/placeholder.txt
new file mode 100644
index 00000000000..e69de29bb2d
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/application_code/serial_term_uart.c b/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/application_code/serial_term_uart.c
new file mode 100644
index 00000000000..c65cf773822
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/application_code/serial_term_uart.c
@@ -0,0 +1,189 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2018 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**********************************************************************************************************************
+* File Name : rskrx65n_uart.c
+* Device(s) : RSKRX65-2M
+* Tool-Chain : Renesas RX
+* Description :
+***********************************************************************************************************************/
+/**********************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+***********************************************************************************************************************/
+
+/*****************************************************************************
+Includes , "Project Includes"
+******************************************************************************/
+#include // For sprintf
+#include "FreeRTOS.h"
+#include "serial_term_uart.h" // Serial Transfer Demo interface file.
+#include "platform.h" // Located in the FIT BSP module
+#include "r_sci_rx_if.h" // The SCI module API interface file.
+#include "r_byteq_if.h" // The BYTEQ module API interface file.
+#include "r_sci_rx_config.h" // User configurable options for the SCI module
+#include "r_pinset.h"
+
+
+/*******************************************************************************
+ Macro definitions
+ *******************************************************************************/
+
+/*******************************************************************************
+ Exported global variables and functions (to be accessed by other files)
+ *******************************************************************************/
+
+/*******************************************************************************
+ Private variables and functions
+ *******************************************************************************/
+
+/*****************************************************************************
+Private global variables and functions
+******************************************************************************/
+static void my_sci_callback(void *pArgs);
+
+/* Handle storage. */
+sci_hdl_t my_sci_handle;
+
+/*****************************************************************************
+* Function Name: uart_config
+* Description : prepares UART for operation
+* Arguments : none
+* Return Value : none
+******************************************************************************/
+void uart_config(void)
+{
+ sci_cfg_t my_sci_config;
+ sci_err_t my_sci_err;
+
+ /* Initialize the I/O port pins for communication on this SCI channel.
+ * This is specific to the MCU and ports chosen. For the RSKRX65-2M we will use the
+ * SCI channel connected to the USB serial port emulation. */
+#if (BSP_CFG_BOARD_REVISION == 0) || (BSP_CFG_BOARD_REVISION == 2)
+ R_SCI_PinSet_SCI2();
+#elif (BSP_CFG_BOARD_REVISION == 1)
+ R_SCI_PinSet_SCI8();
+#elif (BSP_CFG_BOARD_REVISION == 3) || (BSP_CFG_BOARD_REVISION == 5 /* toriaezu */)
+ R_SCI_PinSet_SCI12();
+#elif (BSP_CFG_BOARD_REVISION == 4)
+ R_SCI_PinSet_SCI7();
+#endif
+ /* Set up the configuration data structure for asynchronous (UART) operation. */
+ my_sci_config.async.baud_rate = 115200;
+ my_sci_config.async.clk_src = SCI_CLK_INT;
+ my_sci_config.async.data_size = SCI_DATA_8BIT;
+ my_sci_config.async.parity_en = SCI_PARITY_OFF;
+ my_sci_config.async.parity_type = SCI_EVEN_PARITY;
+ my_sci_config.async.stop_bits = SCI_STOPBITS_1;
+ my_sci_config.async.int_priority = 3; // 1=lowest, 15=highest
+
+ /* OPEN ASYNC CHANNEL
+ * Provide address of the configure structure,
+ * the callback function to be assigned,
+ * and the location for the handle to be stored.*/
+#if (BSP_CFG_BOARD_REVISION == 0) || (BSP_CFG_BOARD_REVISION == 2)
+ my_sci_err = R_SCI_Open(SCI_CH2, SCI_MODE_ASYNC, &my_sci_config, my_sci_callback, &my_sci_handle);
+#elif (BSP_CFG_BOARD_REVISION == 1)
+ my_sci_err = R_SCI_Open(SCI_CH8, SCI_MODE_ASYNC, &my_sci_config, my_sci_callback, &my_sci_handle);
+#elif (BSP_CFG_BOARD_REVISION == 3)
+ my_sci_err = R_SCI_Open(SCI_CH12, SCI_MODE_ASYNC, &my_sci_config, my_sci_callback, &my_sci_handle);
+#endif
+
+ /* If there were an error this would demonstrate error detection of API calls. */
+ if (SCI_SUCCESS != my_sci_err)
+ {
+ nop(); // Your error handling code would go here.
+ }
+} /* End of function uart_config() */
+
+
+/*****************************************************************************
+* Function Name: my_sci_callback
+* Description : This is a template for an SCI Async Mode callback function.
+* Arguments : pArgs -
+* pointer to sci_cb_p_args_t structure cast to a void. Structure
+* contains event and associated data.
+* Return Value : none
+******************************************************************************/
+static void my_sci_callback(void *pArgs)
+{
+ sci_cb_args_t *p_args;
+
+ p_args = (sci_cb_args_t *)pArgs;
+
+ if (SCI_EVT_RX_CHAR == p_args->event)
+ {
+ /* From RXI interrupt; received character data is in p_args->byte */
+ nop();
+ }
+ else if (SCI_EVT_RXBUF_OVFL == p_args->event)
+ {
+ /* From RXI interrupt; rx queue is full; 'lost' data is in p_args->byte
+ You will need to increase buffer size or reduce baud rate */
+ nop();
+ }
+ else if (SCI_EVT_OVFL_ERR == p_args->event)
+ {
+ /* From receiver overflow error interrupt; error data is in p_args->byte
+ Error condition is cleared in calling interrupt routine */
+ nop();
+ }
+ else if (SCI_EVT_FRAMING_ERR == p_args->event)
+ {
+ /* From receiver framing error interrupt; error data is in p_args->byte
+ Error condition is cleared in calling interrupt routine */
+ nop();
+ }
+ else if (SCI_EVT_PARITY_ERR == p_args->event)
+ {
+ /* From receiver parity error interrupt; error data is in p_args->byte
+ Error condition is cleared in calling interrupt routine */
+ nop();
+ }
+ else
+ {
+ /* Do nothing */
+ }
+
+} /* End of function my_sci_callback() */
+
+
+void uart_string_printf(char * pString)
+{
+ uint8_t out_str[configLOGGING_MAX_MESSAGE_LENGTH];
+ //uint8_t out_str[120];
+ uint32_t length = 0;
+ sci_err_t sci_err;
+ uint32_t retry = 0xFFFF;
+
+ length = sprintf((char *)out_str, pString);
+ do
+ {
+ sci_err = R_SCI_Send(my_sci_handle, out_str, length);
+ retry--;
+ } while ((SCI_ERR_XCVR_BUSY == sci_err) && (retry > 0)); // retry if previous transmission still in progress.
+
+ if (SCI_SUCCESS != sci_err)
+ {
+ nop(); //TODO error handling code
+ }
+}
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/application_code/serial_term_uart.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/application_code/serial_term_uart.h
new file mode 100644
index 00000000000..c0a0011a407
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/application_code/serial_term_uart.h
@@ -0,0 +1,15 @@
+/*
+ * rskrx65n_uart.h
+ * --> serial_term_uart.h
+ *
+ * Created on: Feb 8, 2018
+ * Author: godocha01
+ */
+
+#ifndef VENDOR_CODE_RSKRX65N_UART_H_
+#define VENDOR_CODE_RSKRX65N_UART_H_
+
+void uart_config(void);
+void uart_string_printf(char * pString);
+
+#endif /* VENDOR_CODE_RSKRX65N_UART_H_ */
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/application_code/sx_ulpgn_driver.c b/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/application_code/sx_ulpgn_driver.c
new file mode 100644
index 00000000000..fef1adfa2b3
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/application_code/sx_ulpgn_driver.c
@@ -0,0 +1,677 @@
+#include
+#include
+
+#include "platform.h"
+#include "r_sci_rx_if.h"
+#include "sx_ulpgn_driver.h"
+
+
+
+const uint8_t ulpgn_return_text_ok[] = ULPGN_RETURN_TEXT_OK;
+const uint8_t ulpgn_return_text_connect[] = ULPGN_RETURN_TEXT_CONNECT;
+const uint8_t ulpgn_return_text_ring[] = ULPGN_RETURN_TEXT_RING;
+const uint8_t ulpgn_return_text_no_carrier[] = ULPGN_RETURN_TEXT_NO_CARRIER;
+const uint8_t ulpgn_return_text_error[] = ULPGN_RETURN_TEXT_ERROR;
+const uint8_t ulpgn_return_text_no_dialtone[] = ULPGN_RETURN_TEXT_NO_DIALTONE;
+const uint8_t ulpgn_return_text_busy[] = ULPGN_RETURN_TEXT_BUSY;
+const uint8_t ulpgn_return_text_no_answer[] = ULPGN_RETURN_TEXT_NO_ANSWER;
+
+const uint8_t ulpgn_return_numeric_ok[] = ULPGN_RETURN_NUMERIC_OK;
+const uint8_t ulpgn_return_numeric_connect[] = ULPGN_RETURN_NUMERIC_CONNECT;
+const uint8_t ulpgn_return_numeric_ring[] = ULPGN_RETURN_NUMERIC_RING;
+const uint8_t ulpgn_return_numeric_no_carrier[] = ULPGN_RETURN_NUMERIC_NO_CARRIER;
+const uint8_t ulpgn_return_numeric_error[] = ULPGN_RETURN_NUMERIC_ERROR;
+const uint8_t ulpgn_return_numeric_no_dialtone[] = ULPGN_RETURN_NUMERIC_NO_DIALTONE;
+const uint8_t ulpgn_return_numeric_busy[] = ULPGN_RETURN_NUMERIC_BUSY;
+const uint8_t ulpgn_return_numeric_no_answer[] = ULPGN_RETURN_NUMERIC_NO_ANSWER;
+
+const uint8_t ulpgn_return_dummy[] = "";
+
+const uint8_t *ulpgn_result_code[ULPGN_RETURN_ENUM_MAX][ULPGN_RETURN_STRING_MAX] =
+{
+ /* text mode*/ /* numeric mode */
+ {ulpgn_return_text_ok, ulpgn_return_numeric_ok },
+ {ulpgn_return_text_connect, ulpgn_return_numeric_connect },
+ {ulpgn_return_text_ring, ulpgn_return_numeric_ring },
+ {ulpgn_return_text_no_carrier, ulpgn_return_numeric_no_carrier },
+ {ulpgn_return_text_error, ulpgn_return_numeric_error },
+ {ulpgn_return_dummy, ulpgn_return_dummy },
+ {ulpgn_return_text_no_dialtone, ulpgn_return_numeric_no_dialtone },
+ {ulpgn_return_text_busy, ulpgn_return_numeric_busy },
+ {ulpgn_return_text_no_answer, ulpgn_return_numeric_no_answer },
+};
+
+
+
+uint8_t buff[1000];
+uint8_t recvbuff[1000];
+sci_cfg_t g_sx_ulpgn_sci_config;
+sci_err_t g_sx_ulpgn_sci_err;
+uint8_t g_sx_ulpgn_return_mode;
+uint8_t socket_create_flag;
+static void sx_ulpgn_uart_callback(void *pArgs);
+static void timeout_init(uint16_t timeout_ms);
+static void bytetimeout_init(uint16_t timeout_ms);
+static int32_t check_timeout(uint32_t rcvcount);
+static int32_t check_bytetimeout(uint32_t rcvcount);
+static int32_t sx_ulpgn_serial_open(void);
+static int32_t sx_ulpgn_serial_send_basic(uint8_t *ptextstring, uint16_t response_type, uint16_t timeout_ms, sx_ulpgn_return_code_t expect_code);
+static sci_hdl_t sx_ulpgn_uart_sci_handle;
+static TickType_t starttime, thistime, endtime;
+static uint8_t timeout_overflow_flag;
+static TickType_t startbytetime, thisbytetime, endbytetime;
+static uint8_t byte_timeout_overflow_flag;
+static TickType_t g_sl_ulpgn_tcp_timeout = 3000; /* ## slowly problem ## unit: 1ms */
+volatile uint32_t g_sx_ulpgn_uart_teiflag;
+
+int32_t sx_ulpgn_init(void)
+{
+ int32_t ret;
+ ret = sx_ulpgn_serial_open();
+ if(ret != 0)
+ {
+ return ret;
+ }
+
+ /* Wifi Module hardware reset */
+ PORTF.PDR.BIT.B5 = 1;
+ PORTF.PODR.BIT.B5 = 0; /* Low */
+ R_BSP_SoftwareDelay(26, BSP_DELAY_MILLISECS); /* 5us mergin 1us */
+ PORTF.PODR.BIT.B5 = 1; /* High */
+// R_BSP_SoftwareDelay(26, BSP_DELAY_MILLISECS); /* 5us mergin 1us */
+
+ ret = sx_ulpgn_serial_send_basic("ATZ\r", 1000, 2000, ULPGN_RETURN_OK);
+ if(ret != 0)
+ {
+ ret = sx_ulpgn_serial_send_basic("ATZ\r", 1000, 2000, ULPGN_RETURN_OK);
+ if(ret != 0)
+ {
+ return ret;
+ }
+ }
+ g_sx_ulpgn_return_mode = 0;
+
+ ret = sx_ulpgn_serial_send_basic("ATE0\r", 3, 200, ULPGN_RETURN_OK);
+ if(ret != 0)
+ {
+ return ret;
+ }
+ g_sx_ulpgn_return_mode = 1;
+ ret = sx_ulpgn_serial_send_basic("ATV0\r", 3, 200, ULPGN_RETURN_OK);
+ if(ret != 0)
+ {
+ return ret;
+ }
+
+ ret = sx_ulpgn_serial_send_basic("ATS12=1\r", 3, 200, ULPGN_RETURN_OK);
+ if(ret != 0)
+ {
+ return ret;
+ }
+
+ ret = sx_ulpgn_serial_send_basic("ATWD\r", 3, 200, ULPGN_RETURN_OK);
+ if(ret != 0)
+ {
+ return ret;
+ }
+
+ return 0;
+}
+
+int32_t sx_ulpgn_wifi_connect(uint8_t *pssid, uint32_t security, uint8_t *ppass)
+{
+ int32_t ret;
+ char *pstr,pstr2;
+ int32_t line_len;
+ int32_t scanf_ret;
+ volatile char secu[3][10];
+ uint32_t security_encrypt_type = 1;
+
+#if 0
+ pstr = recvbuff;
+ /* FIX ME. */
+ ret = sx_ulpgn_serial_send_basic("ATWS\r", 3, 1000, ULPGN_RETURN_OK);
+ if(0 != ret)
+ {
+ return -1;
+ }
+ while(1)
+ {
+ pstr = strstr(pstr, pssid);
+ if(pstr != NULL)
+ {
+ if(*(pstr + strlen(pssid)) == '\r')
+ {
+ /* find */
+ pstr = strstr(pstr,"security = \r\n");
+ pstr += strlen("security = \r\n");
+ pstr2 = strstr(pstr,"\r\n");
+ pstr2 = '\0';
+ /* type */
+ if(NULL != strstr(pstr,"RSN/WPA2="))
+ {
+ if(security != ULPGN_SECURITY_WPA2)
+ {
+ return -1;
+ }
+ }
+ else if(NULL != strstr(pstr,"WPA="))
+ {
+ if(security != ULPGN_SECURITY_WPA)
+ {
+ return -1;
+ }
+ }
+ else
+ {
+ return -1;
+ }
+
+ if(NULL != strstr(pstr,"PSK"))
+ {
+ }
+ else
+ {
+ return -1;
+ }
+ if(NULL != strstr(pstr,"AES"))
+ {
+ security_encrypt_type = 1;
+ }
+ else if(NULL != strstr(pstr,"TKIP"))
+ {
+ security_encrypt_type = 0;
+ }
+ else
+ {
+ return -1;
+ }
+ }
+ else
+ {
+ pstr += strlen(pssid);
+ }
+ }
+ else
+ {
+ break;
+ }
+ }
+#endif
+ strcpy((char *)buff,"ATWAWPA=");
+ strcat((char *)buff,(const char *)pssid);
+ strcat((char *)buff,",");
+ if(security != ULPGN_SECURITY_WPA && security != ULPGN_SECURITY_WPA2)
+ {
+ return -1;
+ }
+ if(security == ULPGN_SECURITY_WPA)
+ {
+ strcat((char *)buff,"1,");
+ }
+ else
+ {
+ strcat((char *)buff,"2,");
+ }
+ if(security_encrypt_type == 1)
+ {
+ strcat((char *)buff,"1,1,");
+ }
+ else
+ {
+ strcat((char *)buff,"0,0,");
+ }
+ strcat((char *)buff,(const char *)ppass);
+ strcat((char *)buff,"\r");
+
+ ret = sx_ulpgn_serial_send_basic(buff, 3, 5000, ULPGN_RETURN_OK);
+ if(0 == ret)
+ {
+ sx_ulpgn_serial_send_basic("ATW\r", 3, 1000, ULPGN_RETURN_OK);
+ }
+ return ret;
+}
+
+int32_t sx_ulpgn_wifi_get_macaddr(uint8_t *ptextstring)
+{
+// return sx_ulpgn_serial_send_basic("ATW\r", 0, 10000);
+ return sx_ulpgn_serial_send_basic("ATNSET=\?\r", 3, 200, ULPGN_RETURN_OK);
+}
+
+int32_t sx_ulpgn_socket_create(uint32_t type,uint32_t ipversion)
+{
+ int32_t ret;
+ ret = sx_ulpgn_serial_send_basic("ATNSTAT=\r", 3, 200, ULPGN_RETURN_OK);
+
+ sprintf((char *)buff,"ATNSOCK=%d,%d\r",(uint8_t)(type),(uint8_t)(ipversion));
+
+ ret = sx_ulpgn_serial_send_basic(buff, 3, 200, ULPGN_RETURN_OK);
+ if(ret != 0)
+ {
+ return ret;
+ }
+ socket_create_flag = 1;
+// ret = sx_ulpgn_serial_send_basic("ATNSTAT=\r", 3, 200, ULPGN_RETURN_OK);
+
+ return 0;
+}
+
+
+int32_t sx_ulpgn_tcp_connect(uint32_t ipaddr, uint16_t port)
+{
+ strcpy((char *)buff,"ATNCTCP=");
+ sprintf((char *)buff+strlen((char *)buff),"%d.%d.%d.%d,%d\r",(uint8_t)(ipaddr>>24),(uint8_t)(ipaddr>>16),(uint8_t)(ipaddr>>8),(uint8_t)(ipaddr),port);
+
+ return sx_ulpgn_serial_send_basic(buff, 3, 10000, ULPGN_RETURN_CONNECT);
+}
+
+int32_t sx_ulpgn_tcp_send(uint8_t *pdata, int32_t length, uint32_t timeout_ms)
+{
+ int32_t timeout;
+ volatile int32_t sended_length;
+ int32_t lenghttmp1;
+ sci_err_t ercd;
+// sci_baud_t baud;
+
+ sended_length = 0;
+ timeout_init(timeout_ms);
+
+ timeout = 0;
+
+ while(sended_length < length)
+ {
+ if(length - sended_length > SCI_CFG_CH6_TX_BUFSIZ)
+ {
+ lenghttmp1 = SCI_CFG_CH6_TX_BUFSIZ;
+ }
+ else
+ {
+ lenghttmp1 = length - sended_length;
+ }
+ g_sx_ulpgn_uart_teiflag = 0;
+ ercd = R_SCI_Send(sx_ulpgn_uart_sci_handle, pdata, lenghttmp1);
+ if(SCI_SUCCESS != ercd)
+ {
+ return -1;
+ }
+
+ while(1)
+ {
+ if(0 != g_sx_ulpgn_uart_teiflag)
+ {
+ break;
+ }
+// if(-1 == check_timeout(0))
+// {
+// timeout = 1;
+// break;
+// }
+ }
+// if(timeout == 1)
+// {
+// return -1;
+// }
+ sended_length += lenghttmp1;
+ }
+ if(timeout == 1 )
+ {
+ return -1;
+ }
+
+#if DEBUGLOG == 1
+ printf("tcp %d byte send\r\n",sended_length);
+#endif
+ return sended_length;
+}
+
+int32_t sx_ulpgn_tcp_recv(uint8_t *pdata, int32_t length, uint32_t timeout_ms)
+{
+ int32_t timeout;
+ sci_err_t ercd;
+ uint32_t recvcnt = 0;
+#if DEBUGLOG == 1
+ TickType_t tmptime2;
+#endif
+
+ timeout_init(timeout_ms);
+
+ timeout = 0;
+ while(1)
+ {
+ ercd = R_SCI_Receive(sx_ulpgn_uart_sci_handle, (pdata + recvcnt), 1);
+ if(SCI_SUCCESS == ercd)
+ {
+ recvcnt++;
+ if(recvcnt >= length)
+ {
+ break;
+ }
+ }
+ if(-1 == check_timeout(0))
+ {
+ timeout = 1;
+ break;
+ }
+ }
+#if DEBUGLOG == 1
+ tmptime2 = xTaskGetTickCount();
+ printf("r:%06d:tcp %d byte received.reqsize=%d\r\n",tmptime2, recvcnt, length);
+#endif
+
+ return recvcnt;
+}
+
+int32_t sx_ulpgn_serial_tcp_timeout_set(TickType_t timeout_ms)
+{
+ g_sl_ulpgn_tcp_timeout = timeout_ms;
+ return 0;
+}
+
+int32_t sx_ulpgn_tcp_disconnect(void)
+{
+ int32_t ret = 0;
+ if(1 == socket_create_flag)
+ {
+
+ R_BSP_SoftwareDelay(201, BSP_DELAY_MILLISECS); /* 1s */
+ R_SCI_Control(sx_ulpgn_uart_sci_handle,SCI_CMD_RX_Q_FLUSH,NULL);
+ ret = sx_ulpgn_serial_send_basic("+++", 3, 1000, ULPGN_RETURN_OK);
+
+ ret = sx_ulpgn_serial_send_basic("ATNCLOSE\r", 3, 1000, ULPGN_RETURN_OK);
+ if(0 == ret)
+ {
+ socket_create_flag = 0;
+ }
+ }
+ return ret;
+
+}
+
+int32_t sx_ulpgn_dns_query(uint8_t *ptextstring, uint32_t *ulipaddr)
+{
+ uint32_t result;
+ uint32_t ipaddr[4];
+ int32_t func_ret;
+ int32_t scanf_ret;
+ strcpy((char *)buff,"ATNDNSQUERY=");
+ sprintf((char *)buff+strlen((char *)buff),"%s\r",ptextstring);
+
+ func_ret = sx_ulpgn_serial_send_basic(buff, 3, 3000, ULPGN_RETURN_OK);
+ if(func_ret != 0)
+ {
+ return -1;
+ }
+ scanf_ret = sscanf((const char *)recvbuff, "%d\r\n%d.%d.%d.%d\r\n",&result, &ipaddr[0], &ipaddr[1], &ipaddr[2], &ipaddr[3]);
+ if(scanf_ret != 5)
+ {
+ return -1;
+ }
+ if(result != 1)
+ {
+ return -1;
+ }
+ *ulipaddr = (((uint32_t)ipaddr[0]) << 24) | (((uint32_t)ipaddr[1]) << 16) | (((uint32_t)ipaddr[2]) << 8) | ((uint32_t)ipaddr[3]);
+ return 0;
+}
+
+
+static int32_t sx_ulpgn_serial_send_basic(uint8_t *ptextstring, uint16_t response_type, uint16_t timeout_ms, sx_ulpgn_return_code_t expect_code )
+{
+#if DEBUGLOG == 1
+ TickType_t tmptime1,tmptime2;
+#endif
+ volatile int32_t timeout;
+ sci_err_t ercd;
+ uint32_t recvcnt = 0;
+
+ timeout_init(timeout_ms);
+
+ timeout = 0;
+ recvcnt = 0;
+ g_sx_ulpgn_uart_teiflag = 0;
+ ercd = R_SCI_Send(sx_ulpgn_uart_sci_handle, ptextstring, strlen((const char *)ptextstring));
+ if(SCI_SUCCESS != ercd)
+ {
+ return -1;
+ }
+
+ while(1)
+ {
+ if(0 != g_sx_ulpgn_uart_teiflag)
+// ercd = R_SCI_Control(sx_ulpgn_uart_sci_handle, SCI_CMD_TX_Q_BYTES_FREE, &non_used);
+// if(non_used == SCI_CFG_CH6_TX_BUFSIZ)
+ {
+ break;
+ }
+ if(-1 == check_timeout(recvcnt))
+ {
+ timeout = 1;
+ break;
+ }
+ }
+ if(timeout == 1)
+ {
+ return -1;
+ }
+
+#if DEBUGLOG == 1
+ tmptime1 = xTaskGetTickCount();
+ if(ptextstring[strlen((const char *)ptextstring)-1] != '\r')
+ {
+ printf("s:%06d:%s\r",tmptime1,ptextstring);
+ }
+ else
+ {
+ printf("s:%06d:%s",tmptime1,ptextstring);
+ }
+#endif
+ while(1)
+ {
+ ercd = R_SCI_Receive(sx_ulpgn_uart_sci_handle, &recvbuff[recvcnt], 1);
+ if(SCI_SUCCESS == ercd)
+ {
+ recvcnt++;
+ bytetimeout_init(response_type);
+ if(recvcnt < 4)
+ {
+ continue;
+ }
+ if(recvcnt == sizeof(recvbuff)-2)
+ {
+ break;
+ }
+ }
+ if(-1 == check_bytetimeout(recvcnt))
+ {
+ break;
+ }
+ if(-1 == check_timeout(recvcnt))
+ {
+ timeout = 1;
+ break;
+ }
+ }
+ if(timeout == 1)
+ {
+ return -1;
+ }
+
+#if DEBUGLOG == 1
+ tmptime2 = xTaskGetTickCount();
+ if(recvbuff[recvcnt-1] != '\r')
+ {
+ recvbuff[recvcnt] = '\r';
+ recvbuff[recvcnt+1] = '\0';
+ }
+ else
+ {
+ recvbuff[recvcnt] = '\0';
+ }
+ printf("r:%06d:%s",tmptime2,recvbuff);
+#endif
+ /* Response data check */
+ if(recvcnt < strlen((const char *)ulpgn_result_code[expect_code][g_sx_ulpgn_return_mode]))
+ {
+ return -1;
+ }
+ if(0 != strncmp((const char *)&recvbuff[recvcnt - strlen((const char *)ulpgn_result_code[expect_code][g_sx_ulpgn_return_mode]) ],
+ (const char *)ulpgn_result_code[expect_code][g_sx_ulpgn_return_mode], strlen((const char *)ulpgn_result_code[expect_code][g_sx_ulpgn_return_mode])))
+ {
+ return -1;
+ }
+ return 0;
+}
+
+static void timeout_init(uint16_t timeout_ms)
+{
+ starttime = xTaskGetTickCount();
+ endtime = starttime + timeout_ms;
+ if((starttime + endtime) < starttime)
+ {
+ /* overflow */
+ timeout_overflow_flag = 1;
+ }
+ else
+ {
+ timeout_overflow_flag = 0;
+ }
+}
+
+static int32_t check_timeout(uint32_t rcvcount)
+{
+ if(0 == rcvcount)
+ {
+ thistime = xTaskGetTickCount();
+ if(timeout_overflow_flag == 0)
+ {
+ if(thistime >= endtime || thistime < starttime)
+ {
+ return -1;
+ }
+ }
+ else
+ {
+ if(thistime < starttime && thistime <= endtime)
+ {
+ /* Not timeout */
+ return -1;
+ }
+ }
+ }
+ /* Not timeout */
+ return 0;
+}
+
+static void bytetimeout_init(uint16_t timeout_ms)
+{
+ startbytetime = xTaskGetTickCount();
+ endbytetime = startbytetime + timeout_ms;
+ if((startbytetime + endbytetime) < startbytetime)
+ {
+ /* overflow */
+ byte_timeout_overflow_flag = 1;
+ }
+ else
+ {
+ byte_timeout_overflow_flag = 0;
+ }
+}
+
+static int32_t check_bytetimeout(uint32_t rcvcount)
+{
+ if(0 != rcvcount)
+ {
+ thisbytetime = xTaskGetTickCount();
+ if(byte_timeout_overflow_flag == 0)
+ {
+ if(thisbytetime >= endbytetime || thisbytetime < startbytetime)
+ {
+ return -1;
+ }
+ }
+ else
+ {
+ if(thisbytetime < startbytetime && thisbytetime <= endbytetime)
+ {
+ /* Not timeout */
+ return -1;
+ }
+ }
+ }
+ /* Not timeout */
+ return 0;
+}
+
+static int32_t sx_ulpgn_serial_open(void)
+{
+ sci_err_t my_sci_err;
+
+ R_SCI_PinSet_SCI6();
+
+ g_sx_ulpgn_sci_config.async.baud_rate = 115200;
+ g_sx_ulpgn_sci_config.async.clk_src = SCI_CLK_INT;
+ g_sx_ulpgn_sci_config.async.data_size = SCI_DATA_8BIT;
+ g_sx_ulpgn_sci_config.async.parity_en = SCI_PARITY_OFF;
+ g_sx_ulpgn_sci_config.async.parity_type = SCI_EVEN_PARITY;
+ g_sx_ulpgn_sci_config.async.stop_bits = SCI_STOPBITS_1;
+ g_sx_ulpgn_sci_config.async.int_priority = 3; // 1=lowest, 15=highest
+
+ my_sci_err = R_SCI_Open(SCI_CH6, SCI_MODE_ASYNC, &g_sx_ulpgn_sci_config, sx_ulpgn_uart_callback, &sx_ulpgn_uart_sci_handle);
+
+ if(SCI_SUCCESS != my_sci_err)
+ {
+ return -1;
+ }
+ return 0;
+
+}
+
+static void sx_ulpgn_uart_callback(void *pArgs)
+{
+ sci_cb_args_t *p_args;
+
+ p_args = (sci_cb_args_t *)pArgs;
+
+ if (SCI_EVT_RX_CHAR == p_args->event)
+ {
+ /* From RXI interrupt; received character data is in p_args->byte */
+ nop();
+ }
+#if SCI_CFG_TEI_INCLUDED
+ else if (SCI_EVT_TEI == p_args->event)
+ {
+ g_sx_ulpgn_uart_teiflag = 1;
+ nop();
+
+ }
+#endif
+ else if (SCI_EVT_RXBUF_OVFL == p_args->event)
+ {
+ /* From RXI interrupt; rx queue is full; 'lost' data is in p_args->byte
+ You will need to increase buffer size or reduce baud rate */
+ nop();
+ }
+ else if (SCI_EVT_OVFL_ERR == p_args->event)
+ {
+ /* From receiver overflow error interrupt; error data is in p_args->byte
+ Error condition is cleared in calling interrupt routine */
+ nop();
+ }
+ else if (SCI_EVT_FRAMING_ERR == p_args->event)
+ {
+ /* From receiver framing error interrupt; error data is in p_args->byte
+ Error condition is cleared in calling interrupt routine */
+ nop();
+ }
+ else if (SCI_EVT_PARITY_ERR == p_args->event)
+ {
+ /* From receiver parity error interrupt; error data is in p_args->byte
+ Error condition is cleared in calling interrupt routine */
+ nop();
+ }
+ else
+ {
+ /* Do nothing */
+ }
+
+} /* End of function my_sci_callback() */
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/application_code/sx_ulpgn_driver.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/application_code/sx_ulpgn_driver.h
new file mode 100644
index 00000000000..e057cd1ed2c
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/application_code/sx_ulpgn_driver.h
@@ -0,0 +1,68 @@
+#ifndef SX_ULPGN_DRIVER_H
+#define SX_ULPGN_DRIVER_H
+
+#define DEBUGLOG 0
+
+#define ULPGN_RETURN_TEXT_OK "OK\r\n"
+#define ULPGN_RETURN_TEXT_ERROR "ERROR\r\n"
+
+#define ULPGN_RETURN_TEXT_OK "OK\r\n"
+#define ULPGN_RETURN_TEXT_CONNECT "CONNECT\r\n"
+#define ULPGN_RETURN_TEXT_RING "RING\r\n"
+#define ULPGN_RETURN_TEXT_NO_CARRIER "NO_CARRIER\r\n"
+#define ULPGN_RETURN_TEXT_ERROR "ERROR\r\n"
+#define ULPGN_RETURN_TEXT_NO_DIALTONE "NO_DIALTONE\r\n"
+#define ULPGN_RETURN_TEXT_BUSY "BUSY\r\n"
+#define ULPGN_RETURN_TEXT_NO_ANSWER "NO_ANSWER\r\n"
+
+#define ULPGN_RETURN_NUMERIC_OK "0\r"
+#define ULPGN_RETURN_NUMERIC_CONNECT "1\r"
+#define ULPGN_RETURN_NUMERIC_RING "2\r"
+#define ULPGN_RETURN_NUMERIC_NO_CARRIER "3\r"
+#define ULPGN_RETURN_NUMERIC_ERROR "4\r"
+#define ULPGN_RETURN_NUMERIC_NO_DIALTONE "6\r"
+#define ULPGN_RETURN_NUMERIC_BUSY "7\r"
+#define ULPGN_RETURN_NUMERIC_NO_ANSWER "8\r"
+
+typedef enum
+{
+ ULPGN_RETURN_OK = 0,
+ ULPGN_RETURN_CONNECT,
+ ULPGN_RETURN_RING,
+ ULPGN_RETURN_NO_CARRIER,
+ ULPGN_RETURN_ERROR,
+ ULPGN_RETURN_DUMMY,
+ ULPGN_RETURN_NO_DIALTONE,
+ ULPGN_RETURN_BUSY,
+ ULPGN_RETURN_NO_ANSWER,
+ ULPGN_RETURN_ENUM_MAX,
+}sx_ulpgn_return_code_t;
+
+typedef enum
+{
+ ULPGN_RETURN_STRING_TEXT = 0,
+ ULPGN_RETURN_STRING_NUMERIC,
+ ULPGN_RETURN_STRING_MAX,
+}sx_ulpgn_return_string_t;
+
+typedef enum
+{
+ ULPGN_SECURITY_OPEN = 0,
+ ULPGN_SECURITY_WPA,
+ ULPGN_SECURITY_WPA2,
+ ULPGN_SECURITY_WEP,
+ ULPGN_SECURITY_UNDEFINED,
+ ULPGN_SECURITY_MAX,
+}sx_ulpgn_security_t;
+
+int32_t sx_ulpgn_init(void);
+int32_t sx_ulpgn_wifi_get_macaddr(uint8_t *ptextstring);
+int32_t sx_ulpgn_wifi_connect(uint8_t *pssid, uint32_t security, uint8_t *ppass);
+int32_t sx_ulpgn_socket_create(uint32_t type,uint32_t ipversion);
+int32_t sx_ulpgn_tcp_connect(uint32_t ipaddr, uint16_t port);
+int32_t sx_ulpgn_tcp_send(uint8_t *pdata, int32_t length, uint32_t timeout);
+int32_t sx_ulpgn_tcp_recv(uint8_t *pdata, int32_t length, uint32_t timeout);
+int32_t sx_ulpgn_tcp_disconnect(void);
+int32_t sx_ulpgn_dns_query(uint8_t *ptextstring, uint32_t *ulipaddr);
+
+#endif /* #define SX_ULPGN_DRIVER_H */
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/config_files/FreeRTOSConfig.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/config_files/FreeRTOSConfig.h
new file mode 100644
index 00000000000..da2b728b0a5
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/config_files/FreeRTOSConfig.h
@@ -0,0 +1,276 @@
+/*
+ * FreeRTOS Kernel V10.0.1
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://aws.amazon.com/freertos
+ * http://www.FreeRTOS.org
+ */
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+#include "serial_term_uart.h"
+
+/*-----------------------------------------------------------
+* Application specific definitions.
+*
+* These definitions should be adjusted for your particular hardware and
+* application requirements.
+*
+* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+* http://www.freertos.org/a00110.html
+*
+* The bottom of this file contains some constants specific to running the UDP
+* stack in this demo. Constants specific to FreeRTOS+TCP itself (rather than
+* the demo) are contained in FreeRTOSIPConfig.h.
+*----------------------------------------------------------*/
+#define configENABLE_BACKWARD_COMPATIBILITY 0
+#define configUSE_PREEMPTION 1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configMAX_PRIORITIES ( 7 )
+#define configTICK_RATE_HZ ( 1000 )
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 140 )
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 128U * 1024U ) )
+#define configMAX_TASK_NAME_LEN ( 12 )
+#define configUSE_TRACE_FACILITY 1
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_CO_ROUTINES 0
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configQUEUE_REGISTRY_SIZE 0
+#define configUSE_APPLICATION_TASK_TAG 0
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configUSE_ALTERNATIVE_API 0
+#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 3 /* FreeRTOS+FAT requires 2 pointers if a CWD is supported. */
+#define configRECORD_STACK_HIGH_ADDRESS 1
+
+#define configUSE_DAEMON_TASK_STARTUP_HOOK 1
+
+#define configCPU_CLOCK_HZ ( 120000000UL )
+#define configPERIPHERAL_CLOCK_HZ ( 60000000UL )
+#define configUSE_QUEUE_SETS 1
+
+/* Hook function related definitions. */
+#define configUSE_TICK_HOOK 0
+#define configUSE_IDLE_HOOK 0
+#define configUSE_MALLOC_FAILED_HOOK 1
+#define configCHECK_FOR_STACK_OVERFLOW 0 /* Not applicable to the Win32 port. */
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )
+#define configTIMER_QUEUE_LENGTH 5
+#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE)
+
+/* The interrupt priority used by the kernel itself for the tick interrupt and
+the pended interrupt. This would normally be the lowest priority. */
+#define configKERNEL_INTERRUPT_PRIORITY 1
+
+/* The maximum interrupt priority from which FreeRTOS API calls can be made.
+Interrupts that use a priority above this will not be effected by anything the
+kernel is doing. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4
+
+/* The peripheral used to generate the tick interrupt is configured as part of
+the application code. This constant should be set to the vector number of the
+peripheral chosen. As supplied this is CMT0. */
+#define configTICK_VECTOR _CMT0_CMI0 //CMT0
+//#define configTICK_VECTOR _CMT1_CMI1 //CMT1
+//#define configTICK_VECTOR _CMT2_CMI2 //CMT2
+//#define configTICK_VECTOR _CMT3_CMI3 //CMT3
+
+/* Event group related definitions. */
+#define configUSE_EVENT_GROUPS 1
+
+/* Run time stats gathering definitions. */
+unsigned long ulGetRunTimeCounterValue( void );
+void vConfigureTimerForRunTimeStats( void );
+#define configGENERATE_RUN_TIME_STATS 0
+//#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() vConfigureTimerForRunTimeStats()
+//#define portGET_RUN_TIME_COUNTER_VALUE() ulGetRunTimeCounterValue()
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
+
+/* Currently the TCP/IP stack is using dynamic allocation, and the MQTT task is
+ * using static allocation. */
+#define configSUPPORT_DYNAMIC_ALLOCATION 1
+#define configSUPPORT_STATIC_ALLOCATION 1
+
+/* Set the following definitions to 1 to include the API function, or zero
+ * to exclude the API function. */
+#define INCLUDE_vTaskPrioritySet 1
+#define INCLUDE_uxTaskPriorityGet 1
+#define INCLUDE_vTaskDelete 1
+#define INCLUDE_vTaskCleanUpResources 0
+#define INCLUDE_vTaskSuspend 1
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 1
+#define INCLUDE_xTaskGetSchedulerState 1
+#define INCLUDE_xTimerGetTimerTaskHandle 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_xQueueGetMutexHolder 1
+#define INCLUDE_eTaskGetState 1
+#define INCLUDE_xEventGroupSetBitsFromISR 1
+#define INCLUDE_xTimerPendFunctionCall 1
+#define INCLUDE_xTaskGetCurrentTaskHandle 1
+#define INCLUDE_xTaskAbortDelay 1
+
+/* This demo makes use of one or more example stats formatting functions. These
+ * format the raw data provided by the uxTaskGetSystemState() function in to human
+ * readable ASCII form. See the notes in the implementation of vTaskList() within
+ * FreeRTOS/Source/tasks.c for limitations. configUSE_STATS_FORMATTING_FUNCTIONS
+ * is set to 2 so the formatting functions are included without the stdio.h being
+ * included in tasks.c. That is because this project defines its own sprintf()
+ * functions. */
+#define configUSE_STATS_FORMATTING_FUNCTIONS 1
+
+#if(1)
+/* Assert call defined for debug builds. */
+extern void vAssertCalled( void );
+#define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled()
+
+//extern TEST_ABORT();
+//#define configASSERT( x ) if( ( x ) == 0 ) TEST_ABORT()
+#endif
+
+/* The function that implements FreeRTOS printf style output, and the macro
+ * that maps the configPRINTF() macros to that function. */
+extern void vLoggingPrintf( const char * pcFormat, ... );
+
+#define configPRINTF( X ) vLoggingPrintf X
+
+
+/* Map the logging task's printf to the board specific output function. */
+#define configPRINT_STRING( x ) uart_string_printf( x );
+
+/* Sets the length of the buffers into which logging messages are written - so
+ * also defines the maximum length of each log message. */
+#define configLOGGING_MAX_MESSAGE_LENGTH 120
+
+/* Set to 1 to prepend each log message with a message number, the task name,
+ * and a time stamp. */
+#define configLOGGING_INCLUDE_TIME_AND_TASK_NAME 1
+
+/* Application specific definitions follow. **********************************/
+
+/* If configINCLUDE_DEMO_DEBUG_STATS is set to one, then a few basic IP trace
+ * macros are defined to gather some UDP stack statistics that can then be viewed
+ * through the CLI interface. */
+#define configINCLUDE_DEMO_DEBUG_STATS 1
+
+/* The size of the global output buffer that is available for use when there
+ * are multiple command interpreters running at once (for example, one on a UART
+ * and one on TCP/IP). This is done to prevent an output buffer being defined by
+ * each implementation - which would waste RAM. In this case, there is only one
+ * command interpreter running, and it has its own local output buffer, so the
+ * global buffer is just set to be one byte long as it is not used and should not
+ * take up unnecessary RAM. */
+#define configCOMMAND_INT_MAX_OUTPUT_SIZE 1
+
+/* Only used when running in the FreeRTOS Windows simulator. Defines the
+ * priority of the task used to simulate Ethernet interrupts. */
+#define configMAC_ISR_SIMULATOR_PRIORITY ( configMAX_PRIORITIES - 1 )
+
+/* This demo creates a virtual network connection by accessing the raw Ethernet
+ * or WiFi data to and from a real network connection. Many computers have more
+ * than one real network port, and configNETWORK_INTERFACE_TO_USE is used to tell
+ * the demo which real port should be used to create the virtual port. The ports
+ * available are displayed on the console when the application is executed. For
+ * example, on my development laptop setting configNETWORK_INTERFACE_TO_USE to 4
+ * results in the wired network being used, while setting
+ * configNETWORK_INTERFACE_TO_USE to 2 results in the wireless network being
+ * used. */
+#define configNETWORK_INTERFACE_TO_USE 2L
+
+/* The address of an echo server that will be used by the two demo echo client
+ * tasks:
+ * http://www.freertos.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/TCP_Echo_Clients.html,
+ * http://www.freertos.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/UDP_Echo_Clients.html. */
+#define configECHO_SERVER_ADDR0 192
+#define configECHO_SERVER_ADDR1 168
+#define configECHO_SERVER_ADDR2 1
+#define configECHO_SERVER_ADDR3 200
+#define configTCP_ECHO_CLIENT_PORT 9999
+
+/* Default MAC address configuration. The demo creates a virtual network
+ * connection that uses this MAC address by accessing the raw Ethernet/WiFi data
+ * to and from a real network connection on the host PC. See the
+ * configNETWORK_INTERFACE_TO_USE definition above for information on how to
+ * configure the real network connection to use. */
+#define configMAC_ADDR0 0x74
+#define configMAC_ADDR1 0x90
+#define configMAC_ADDR2 0x50
+#define configMAC_ADDR3 0x00
+#define configMAC_ADDR4 0x79
+#define configMAC_ADDR5 0x03
+
+/* Default IP address configuration. Used in ipconfigUSE_DHCP is set to 0, or
+ * ipconfigUSE_DHCP is set to 1 but a DNS server cannot be contacted. */
+#define configIP_ADDR0 172
+#define configIP_ADDR1 27
+#define configIP_ADDR2 49
+#define configIP_ADDR3 127
+
+/* Default gateway IP address configuration. Used in ipconfigUSE_DHCP is set to
+ * 0, or ipconfigUSE_DHCP is set to 1 but a DNS server cannot be contacted. */
+#define configGATEWAY_ADDR0 172
+#define configGATEWAY_ADDR1 27
+#define configGATEWAY_ADDR2 49
+#define configGATEWAY_ADDR3 1
+
+/* Default DNS server configuration. OpenDNS addresses are 208.67.222.222 and
+ * 208.67.220.220. Used in ipconfigUSE_DHCP is set to 0, or ipconfigUSE_DHCP is
+ * set to 1 but a DNS server cannot be contacted.*/
+#define configDNS_SERVER_ADDR0 143
+#define configDNS_SERVER_ADDR1 103
+#define configDNS_SERVER_ADDR2 47
+#define configDNS_SERVER_ADDR3 193
+
+/* Default netmask configuration. Used in ipconfigUSE_DHCP is set to 0, or
+ * ipconfigUSE_DHCP is set to 1 but a DNS server cannot be contacted. */
+#define configNET_MASK0 255
+#define configNET_MASK1 255
+#define configNET_MASK2 255
+#define configNET_MASK3 0
+
+/* The UDP port to which print messages are sent. */
+#define configPRINT_PORT ( 15000 )
+
+#define configPROFILING ( 0 )
+
+/* Pseudo random number generater used by some demo tasks. */
+extern uint32_t ulRand();
+#define configRAND32() ulRand()
+
+/* The platform FreeRTOS is running on. */
+#define configPLATFORM_NAME "RenesasRX65N"
+
+/* Header required for the tracealyzer recorder library. */
+//#include "trcRecorder.h"
+
+/* Header required for the compatibility between GNU/IAR C compilers and the CC-RX compiler. */
+#include "SCFGcompiler.h"
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/config_files/FreeRTOSIPConfig.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/config_files/FreeRTOSIPConfig.h
new file mode 100644
index 00000000000..30bdb467748
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/config_files/FreeRTOSIPConfig.h
@@ -0,0 +1,314 @@
+/*
+ * FreeRTOS Kernel V10.0.1
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://aws.amazon.com/freertos
+ * http://www.FreeRTOS.org
+ */
+
+
+/*****************************************************************************
+*
+* See the following URL for configuration information.
+* http://www.freertos.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/TCP_IP_Configuration.html
+*
+*****************************************************************************/
+
+#ifndef FREERTOS_IP_CONFIG_H
+#define FREERTOS_IP_CONFIG_H
+
+/* Prototype for the function used to print out. In this case it prints to the
+ * console before the network is connected then a UDP port after the network has
+ * connected. */
+//extern void vLoggingPrintf( const char * pcFormatString,
+// ... );
+
+/* Set to 1 to print out debug messages. If ipconfigHAS_DEBUG_PRINTF is set to
+ * 1 then FreeRTOS_debug_printf should be defined to the function used to print
+ * out the debugging messages. */
+#define ipconfigHAS_DEBUG_PRINTF 1
+#if ( ipconfigHAS_DEBUG_PRINTF == 1 )
+ //#define FreeRTOS_debug_printf( X ) vLoggingPrintf( X )
+ #define FreeRTOS_debug_printf( X ) configPRINTF( X )
+#endif
+
+/* Set to 1 to print out non debugging messages, for example the output of the
+ * FreeRTOS_netstat() command, and ping replies. If ipconfigHAS_PRINTF is set to 1
+ * then FreeRTOS_printf should be set to the function used to print out the
+ * messages. */
+#define ipconfigHAS_PRINTF 1
+#if ( ipconfigHAS_PRINTF == 1 )
+ #define FreeRTOS_printf( X ) configPRINTF( X )
+#endif
+
+/* Define the byte order of the target MCU (the MCU FreeRTOS+TCP is executing
+ * on). Valid options are pdFREERTOS_BIG_ENDIAN and pdFREERTOS_LITTLE_ENDIAN. */
+#define ipconfigBYTE_ORDER pdFREERTOS_LITTLE_ENDIAN
+
+/* If the network card/driver includes checksum offloading (IP/TCP/UDP checksums)
+ * then set ipconfigDRIVER_INCLUDED_RX_IP_CHECKSUM to 1 to prevent the software
+ * stack repeating the checksum calculations. */
+#define ipconfigDRIVER_INCLUDED_RX_IP_CHECKSUM 1
+
+/* Several API's will block until the result is known, or the action has been
+ * performed, for example FreeRTOS_send() and FreeRTOS_recv(). The timeouts can be
+ * set per socket, using setsockopt(). If not set, the times below will be
+ * used as defaults. */
+#define ipconfigSOCK_DEFAULT_RECEIVE_BLOCK_TIME ( 10000 )
+#define ipconfigSOCK_DEFAULT_SEND_BLOCK_TIME ( 10000 )
+
+/* Include support for DNS caching. For TCP, having a small DNS cache is very
+ * useful. When a cache is present, ipconfigDNS_REQUEST_ATTEMPTS can be kept low
+ * and also DNS may use small timeouts. If a DNS reply comes in after the DNS
+ * socket has been destroyed, the result will be stored into the cache. The next
+ * call to FreeRTOS_gethostbyname() will return immediately, without even creating
+ * a socket. */
+#define ipconfigUSE_DNS_CACHE ( 1 )
+#define ipconfigDNS_REQUEST_ATTEMPTS ( 2 )
+
+/* The IP stack executes it its own task (although any application task can make
+ * use of its services through the published sockets API). ipconfigUDP_TASK_PRIORITY
+ * sets the priority of the task that executes the IP stack. The priority is a
+ * standard FreeRTOS task priority so can take any value from 0 (the lowest
+ * priority) to (configMAX_PRIORITIES - 1) (the highest priority).
+ * configMAX_PRIORITIES is a standard FreeRTOS configuration parameter defined in
+ * FreeRTOSConfig.h, not FreeRTOSIPConfig.h. Consideration needs to be given as to
+ * the priority assigned to the task executing the IP stack relative to the
+ * priority assigned to tasks that use the IP stack. */
+#define ipconfigIP_TASK_PRIORITY ( configMAX_PRIORITIES - 2 )
+
+/* The size, in words (not bytes), of the stack allocated to the FreeRTOS+TCP
+ * task. This setting is less important when the FreeRTOS Win32 simulator is used
+ * as the Win32 simulator only stores a fixed amount of information on the task
+ * stack. FreeRTOS includes optional stack overflow detection, see:
+ * http://www.freertos.org/Stacks-and-stack-overflow-checking.html. */
+#define ipconfigIP_TASK_STACK_SIZE_WORDS ( configMINIMAL_STACK_SIZE * 5 )
+
+/* ipconfigRAND32() is called by the IP stack to generate random numbers for
+ * things such as a DHCP transaction number or initial sequence number. Random
+ * number generation is performed via this macro to allow applications to use their
+ * own random number generation method. For example, it might be possible to
+ * generate a random number by sampling noise on an analogue input. */
+extern uint32_t ulRand();
+#define ipconfigRAND32() ulRand()
+
+/* If ipconfigUSE_NETWORK_EVENT_HOOK is set to 1 then FreeRTOS+TCP will call the
+ * network event hook at the appropriate times. If ipconfigUSE_NETWORK_EVENT_HOOK
+ * is not set to 1 then the network event hook will never be called. See:
+ * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/API/vApplicationIPNetworkEventHook.shtml.
+ */
+#define ipconfigUSE_NETWORK_EVENT_HOOK 1
+
+/* Sockets have a send block time attribute. If FreeRTOS_sendto() is called but
+ * a network buffer cannot be obtained then the calling task is held in the Blocked
+ * state (so other tasks can continue to executed) until either a network buffer
+ * becomes available or the send block time expires. If the send block time expires
+ * then the send operation is aborted. The maximum allowable send block time is
+ * capped to the value set by ipconfigMAX_SEND_BLOCK_TIME_TICKS. Capping the
+ * maximum allowable send block time prevents prevents a deadlock occurring when
+ * all the network buffers are in use and the tasks that process (and subsequently
+ * free) the network buffers are themselves blocked waiting for a network buffer.
+ * ipconfigMAX_SEND_BLOCK_TIME_TICKS is specified in RTOS ticks. A time in
+ * milliseconds can be converted to a time in ticks by dividing the time in
+ * milliseconds by portTICK_PERIOD_MS. */
+#define ipconfigUDP_MAX_SEND_BLOCK_TIME_TICKS ( 5000 / portTICK_PERIOD_MS )
+
+/* If ipconfigUSE_DHCP is 1 then FreeRTOS+TCP will attempt to retrieve an IP
+ * address, netmask, DNS server address and gateway address from a DHCP server. If
+ * ipconfigUSE_DHCP is 0 then FreeRTOS+TCP will use a static IP address. The
+ * stack will revert to using the static IP address even when ipconfigUSE_DHCP is
+ * set to 1 if a valid configuration cannot be obtained from a DHCP server for any
+ * reason. The static configuration used is that passed into the stack by the
+ * FreeRTOS_IPInit() function call. */
+#define ipconfigUSE_DHCP 1
+#define ipconfigDHCP_REGISTER_HOSTNAME 1
+#define ipconfigDHCP_USES_UNICAST 1
+
+/* If ipconfigDHCP_USES_USER_HOOK is set to 1 then the application writer must
+ * provide an implementation of the DHCP callback function,
+ * xApplicationDHCPUserHook(). */
+#define ipconfigUSE_DHCP_HOOK 0
+
+/* When ipconfigUSE_DHCP is set to 1, DHCP requests will be sent out at
+ * increasing time intervals until either a reply is received from a DHCP server
+ * and accepted, or the interval between transmissions reaches
+ * ipconfigMAXIMUM_DISCOVER_TX_PERIOD. The IP stack will revert to using the
+ * static IP address passed as a parameter to FreeRTOS_IPInit() if the
+ * re-transmission time interval reaches ipconfigMAXIMUM_DISCOVER_TX_PERIOD without
+ * a DHCP reply being received. */
+#define ipconfigMAXIMUM_DISCOVER_TX_PERIOD ( 120000 / portTICK_PERIOD_MS )
+
+/* The ARP cache is a table that maps IP addresses to MAC addresses. The IP
+ * stack can only send a UDP message to a remove IP address if it knowns the MAC
+ * address associated with the IP address, or the MAC address of the router used to
+ * contact the remote IP address. When a UDP message is received from a remote IP
+ * address the MAC address and IP address are added to the ARP cache. When a UDP
+ * message is sent to a remote IP address that does not already appear in the ARP
+ * cache then the UDP message is replaced by a ARP message that solicits the
+ * required MAC address information. ipconfigARP_CACHE_ENTRIES defines the maximum
+ * number of entries that can exist in the ARP table at any one time. */
+#define ipconfigARP_CACHE_ENTRIES 6
+
+/* ARP requests that do not result in an ARP response will be re-transmitted a
+ * maximum of ipconfigMAX_ARP_RETRANSMISSIONS times before the ARP request is
+ * aborted. */
+#define ipconfigMAX_ARP_RETRANSMISSIONS ( 5 )
+
+/* ipconfigMAX_ARP_AGE defines the maximum time between an entry in the ARP
+ * table being created or refreshed and the entry being removed because it is stale.
+ * New ARP requests are sent for ARP cache entries that are nearing their maximum
+ * age. ipconfigMAX_ARP_AGE is specified in tens of seconds, so a value of 150 is
+ * equal to 1500 seconds (or 25 minutes). */
+#define ipconfigMAX_ARP_AGE 150
+
+/* Implementing FreeRTOS_inet_addr() necessitates the use of string handling
+ * routines, which are relatively large. To save code space the full
+ * FreeRTOS_inet_addr() implementation is made optional, and a smaller and faster
+ * alternative called FreeRTOS_inet_addr_quick() is provided. FreeRTOS_inet_addr()
+ * takes an IP in decimal dot format (for example, "192.168.0.1") as its parameter.
+ * FreeRTOS_inet_addr_quick() takes an IP address as four separate numerical octets
+ * (for example, 192, 168, 0, 1) as its parameters. If
+ * ipconfigINCLUDE_FULL_INET_ADDR is set to 1 then both FreeRTOS_inet_addr() and
+ * FreeRTOS_indet_addr_quick() are available. If ipconfigINCLUDE_FULL_INET_ADDR is
+ * not set to 1 then only FreeRTOS_indet_addr_quick() is available. */
+#define ipconfigINCLUDE_FULL_INET_ADDR 0
+
+/* ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS defines the total number of network buffer that
+ * are available to the IP stack. The total number of network buffers is limited
+ * to ensure the total amount of RAM that can be consumed by the IP stack is capped
+ * to a pre-determinable value. */
+#define ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS ETHER_CFG_EMAC_TX_DESCRIPTORS
+
+/* A FreeRTOS queue is used to send events from application tasks to the IP
+ * stack. ipconfigEVENT_QUEUE_LENGTH sets the maximum number of events that can
+ * be queued for processing at any one time. The event queue must be a minimum of
+ * 5 greater than the total number of network buffers. */
+#define ipconfigEVENT_QUEUE_LENGTH ( ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS + 5 )
+
+/* The address of a socket is the combination of its IP address and its port
+ * number. FreeRTOS_bind() is used to manually allocate a port number to a socket
+ * (to 'bind' the socket to a port), but manual binding is not normally necessary
+ * for client sockets (those sockets that initiate outgoing connections rather than
+ * wait for incoming connections on a known port number). If
+ * ipconfigALLOW_SOCKET_SEND_WITHOUT_BIND is set to 1 then calling
+ * FreeRTOS_sendto() on a socket that has not yet been bound will result in the IP
+ * stack automatically binding the socket to a port number from the range
+ * socketAUTO_PORT_ALLOCATION_START_NUMBER to 0xffff. If
+ * ipconfigALLOW_SOCKET_SEND_WITHOUT_BIND is set to 0 then calling FreeRTOS_sendto()
+ * on a socket that has not yet been bound will result in the send operation being
+ * aborted. */
+#define ipconfigALLOW_SOCKET_SEND_WITHOUT_BIND 1
+
+/* Defines the Time To Live (TTL) values used in outgoing UDP packets. */
+#define ipconfigUDP_TIME_TO_LIVE 128
+/* Also defined in FreeRTOSIPConfigDefaults.h. */
+#define ipconfigTCP_TIME_TO_LIVE 128
+
+/* USE_TCP: Use TCP and all its features. */
+#define ipconfigUSE_TCP ( 1 )
+
+/* USE_WIN: Let TCP use windowing mechanism. */
+#define ipconfigUSE_TCP_WIN ( 0 )
+
+/* The MTU is the maximum number of bytes the payload of a network frame can
+ * contain. For normal Ethernet V2 frames the maximum MTU is 1500. Setting a
+ * lower value can save RAM, depending on the buffer management scheme used. If
+ * ipconfigCAN_FRAGMENT_OUTGOING_PACKETS is 1 then (ipconfigNETWORK_MTU - 28) must
+ * be divisible by 8. */
+#define ipconfigNETWORK_MTU 1500
+
+/* Set ipconfigUSE_DNS to 1 to include a basic DNS client/resolver. DNS is used
+ * through the FreeRTOS_gethostbyname() API function. */
+#define ipconfigUSE_DNS 1
+
+/* If ipconfigREPLY_TO_INCOMING_PINGS is set to 1 then the IP stack will
+ * generate replies to incoming ICMP echo (ping) requests. */
+#define ipconfigREPLY_TO_INCOMING_PINGS 1
+
+/* If ipconfigSUPPORT_OUTGOING_PINGS is set to 1 then the
+ * FreeRTOS_SendPingRequest() API function is available. */
+#define ipconfigSUPPORT_OUTGOING_PINGS 0
+
+/* If ipconfigSUPPORT_SELECT_FUNCTION is set to 1 then the FreeRTOS_select()
+ * (and associated) API function is available. */
+#define ipconfigSUPPORT_SELECT_FUNCTION 0
+
+/* If ipconfigFILTER_OUT_NON_ETHERNET_II_FRAMES is set to 1 then Ethernet frames
+ * that are not in Ethernet II format will be dropped. This option is included for
+ * potential future IP stack developments. */
+#define ipconfigFILTER_OUT_NON_ETHERNET_II_FRAMES 1
+
+/* If ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES is set to 1 then it is the
+ * responsibility of the Ethernet interface to filter out packets that are of no
+ * interest. If the Ethernet interface does not implement this functionality, then
+ * set ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES to 0 to have the IP stack
+ * perform the filtering instead (it is much less efficient for the stack to do it
+ * because the packet will already have been passed into the stack). If the
+ * Ethernet driver does all the necessary filtering in hardware then software
+ * filtering can be removed by using a value other than 1 or 0. */
+#define ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES 0 //XXX
+
+/* The windows simulator cannot really simulate MAC interrupts, and needs to
+ * block occasionally to allow other tasks to run. */
+//#define configWINDOWS_MAC_INTERRUPT_SIMULATOR_DELAY ( 20 / portTICK_PERIOD_MS )
+
+/* Advanced only: in order to access 32-bit fields in the IP packets with
+ * 32-bit memory instructions, all packets will be stored 32-bit-aligned,
+ * plus 16-bits. This has to do with the contents of the IP-packets: all
+ * 32-bit fields are 32-bit-aligned, plus 16-bit. */
+#define ipconfigPACKET_FILLER_SIZE 2
+
+/* Define the size of the pool of TCP window descriptors. On the average, each
+ * TCP socket will use up to 2 x 6 descriptors, meaning that it can have 2 x 6
+ * outstanding packets (for Rx and Tx). When using up to 10 TP sockets
+ * simultaneously, one could define TCP_WIN_SEG_COUNT as 120. */
+#define ipconfigTCP_WIN_SEG_COUNT 240
+
+/* Each TCP socket has a circular buffers for Rx and Tx, which have a fixed
+ * maximum size. Define the size of Rx buffer for TCP sockets. */
+#define ipconfigTCP_RX_BUFFER_LENGTH ( 3000 )
+
+/* Define the size of Tx buffer for TCP sockets. */
+#define ipconfigTCP_TX_BUFFER_LENGTH ( 3000 )
+
+/* When using call-back handlers, the driver may check if the handler points to
+ * real program memory (RAM or flash) or just has a random non-zero value. */
+#define ipconfigIS_VALID_PROG_ADDRESS( x ) ( ( x ) != NULL )
+
+/* Include support for TCP keep-alive messages. */
+#define ipconfigTCP_KEEP_ALIVE ( 1 )
+#define ipconfigTCP_KEEP_ALIVE_INTERVAL ( 20 ) /* Seconds. */
+
+/* The socket semaphore is used to unblock the MQTT task. */
+#define ipconfigSOCKET_HAS_USER_SEMAPHORE ( 0 )
+
+#define ipconfigSOCKET_HAS_USER_WAKE_CALLBACK ( 1 )
+#define ipconfigUSE_CALLBACKS ( 0 )
+
+#define ipconfigZERO_COPY_TX_DRIVER ( 0 )
+#define ipconfigZERO_COPY_RX_DRIVER ( 0 )
+
+#define portINLINE __inline
+
+void vApplicationMQTTGetKeys( const char ** ppcRootCA,
+ const char ** ppcClientCert,
+ const char ** ppcClientPrivateKey );
+
+#endif /* FREERTOS_IP_CONFIG_H */
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/config_files/aws_bufferpool_config.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/config_files/aws_bufferpool_config.h
new file mode 100644
index 00000000000..4b18bf6755d
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/config_files/aws_bufferpool_config.h
@@ -0,0 +1,44 @@
+/*
+ * Amazon FreeRTOS V1.2.2
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://aws.amazon.com/freertos
+ * http://www.FreeRTOS.org
+ */
+
+/**
+ * @file aws_bufferpool_config.h
+ * @brief Buffer Pool config options.
+ */
+
+#ifndef _AWS_BUFFER_POOL_CONFIG_H_
+#define _AWS_BUFFER_POOL_CONFIG_H_
+
+/**
+ * @brief The number of buffers in the static buffer pool.
+ */
+#define bufferpoolconfigNUM_BUFFERS ( 8 )
+
+/**
+ * @brief The size of each buffer in the static buffer pool.
+ */
+#define bufferpoolconfigBUFFER_SIZE ( 512 )
+
+#endif /* _AWS_BUFFER_POOL_CONFIG_H_ */
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/config_files/aws_demo_config.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/config_files/aws_demo_config.h
new file mode 100644
index 00000000000..cbf5eb290b8
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/config_files/aws_demo_config.h
@@ -0,0 +1,81 @@
+/*
+ * Amazon FreeRTOS V1.2.2
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://aws.amazon.com/freertos
+ * http://www.FreeRTOS.org
+ */
+
+#ifndef _AWS_DEMO_CONFIG_H_
+#define _AWS_DEMO_CONFIG_H_
+
+/* Number of sub pub tasks that connect to a broker that is not using TLS. */
+#define democonfigMQTT_SUB_PUB_NUM_UNSECURE_TASKS ( 0 )
+
+/* Number of sub pub tasks that connect to a broker that is using TLS. */
+#define democonfigMQTT_SUB_PUB_NUM_SECURE_TASKS ( 1 )
+
+#define democonfigSHADOW_DEMO_NUM_TASKS ( 1 )
+
+/* IoT simple subscribe/publish example task parameters. */
+#define democonfigMQTT_SUB_PUB_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE * 5 )
+#define democonfigMQTT_SUB_PUB_TASK_PRIORITY ( tskIDLE_PRIORITY )
+
+/* Greengrass discovery example task parameters. */
+#define democonfigGREENGRASS_DISCOVERY_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE * 16 )
+#define democonfigGREENGRASS_DISCOVERY_TASK_PRIORITY ( tskIDLE_PRIORITY )
+
+/* Shadow demo task parameters. */
+#define democonfigSHADOW_DEMO_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE * 4 )
+#define democonfigSHADOW_DEMO_TASK_PRIORITY ( tskIDLE_PRIORITY )
+
+
+/* TCP Echo Client tasks single example parameters. */
+#define democonfigTCP_ECHO_TASKS_SINGLE_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE * 4 )
+#define democonfigTCP_ECHO_TASKS_SINGLE_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
+
+/* OTA Update task example parameters. */
+#define democonfigOTA_UPDATE_TASK_STACK_SIZE ( 4 * configMINIMAL_STACK_SIZE )
+#define democonfigOTA_UPDATE_TASK_TASK_PRIORITY ( tskIDLE_PRIORITY )
+
+/* Simple TCP Echo Server task example parameters */
+#define democonfigTCP_ECHO_SERVER_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE * 6 )
+#define democonfigTCP_ECHO_SERVER_TASK_PRIORITY ( tskIDLE_PRIORITY )
+
+/* TCP Echo Client tasks multi task example parameters. */
+#define democonfigTCP_ECHO_TASKS_SEPARATE_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE * 4 )
+#define democonfigTCP_ECHO_TASKS_SEPARATE_TASK_PRIORITY ( tskIDLE_PRIORITY )
+
+/* MQTT echo task example parameters. */
+#define democonfigMQTT_ECHO_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE * 3 )
+#define democonfigMQTT_ECHO_TASK_PRIORITY ( tskIDLE_PRIORITY )
+
+/* Timeout used when establishing a connection, which required TLS
+negotiation. */
+#define democonfigMQTT_ECHO_TLS_NEGOTIATION_TIMEOUT pdMS_TO_TICKS( 12000 )
+
+/* Timeout used when performing MQTT operations that do not need extra time
+to perform a TLS negotiation. */
+#define democonfigMQTT_TIMEOUT pdMS_TO_TICKS( 2500 )
+
+/* Send AWS IoT MQTT traffic encrypted. */
+#define democonfigMQTT_AGENT_CONNECT_FLAGS ( mqttagentREQUIRE_TLS )
+
+#endif /* _AWS_DEMO_CONFIG_H_ */
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/config_files/aws_ggd_config.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/config_files/aws_ggd_config.h
new file mode 100644
index 00000000000..7ac803fa21a
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/config_files/aws_ggd_config.h
@@ -0,0 +1,46 @@
+/*
+ * Amazon FreeRTOS V1.2.2
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://aws.amazon.com/freertos
+ * http://www.FreeRTOS.org
+ */
+
+
+/**
+ * @file aws_ggd_config.h
+ * @brief GGD config options.
+ */
+
+#ifndef _AWS_GGD_CONFIG_H_
+#define _AWS_GGD_CONFIG_H_
+
+
+/**
+ * @brief The number of your network interface here.
+ */
+#define ggdconfigCORE_NETWORK_INTERFACE ( 0 )
+
+/**
+ * @brief Size of the array used by jsmn to store the tokens.
+ */
+#define ggdconfigJSON_MAX_TOKENS ( 128 )
+
+#endif /* _AWS_GGD_CONFIG_H_ */
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/config_files/aws_mqtt_agent_config.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/config_files/aws_mqtt_agent_config.h
new file mode 100644
index 00000000000..cdca9c6d41c
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/config_files/aws_mqtt_agent_config.h
@@ -0,0 +1,120 @@
+/*
+ * Amazon FreeRTOS V1.2.2
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://aws.amazon.com/freertos
+ * http://www.FreeRTOS.org
+ */
+
+/**
+ * @file aws_mqtt_agent_config.h
+ * @brief MQTT agent config options.
+ */
+
+#ifndef _AWS_MQTT_AGENT_CONFIG_H_
+#define _AWS_MQTT_AGENT_CONFIG_H_
+
+#include "FreeRTOS.h"
+
+/**
+ * @brief Controls whether or not to report usage metrics to the
+ * AWS IoT broker.
+ *
+ * If mqttconfigENABLE_METRICS is set to 1, a string containing
+ * metric information will be included in the "username" field of
+ * the MQTT connect messages.
+ */
+#define mqttconfigENABLE_METRICS ( 1 )
+
+/**
+ * @brief The maximum time an application task waits for sending a command to the
+ * command queue and for receiving a notification from the MQTT task.
+ *
+ * An application task sends the command to the MQTT task over command queue and
+ * then waits for a notification from the MQTT task. In case the MQTT task fails to
+ * respond within in a reasonable amount of time, the application task should be
+ * informed about the same. This timeout value is the maximum time a task waits for
+ * the notification from the MQTT task. This value must be high to ensure that this
+ * does not happen under normal operation and when it happens, we should disconnect
+ * since we are sharing user provided pointers with the MQTT task which might be
+ * invalid now onwards.
+ * _TODO_ - Finalize what to do on Timeout.
+ */
+#define mqttOPERATION_TIMEOUT_MS ( 120000 )
+
+/**
+ * @brief The maximum time interval in seconds allowed to elapse between 2 consecutive
+ * control packets.
+ */
+#define mqttconfigKEEP_ALIVE_INTERVAL_SECONDS ( 100 )
+
+/**
+ * @brief Defines the frequency at which the client should send Keep Alive messages.
+ *
+ * Even though the maximum time allowed between 2 consecutive control packets
+ * is defined by the mqttconfigKEEP_ALIVE_INTERVAL_SECONDS macro, the user
+ * can and should send Keep Alive messages at a slightly faster rate to ensure
+ * that the connection is not closed by the server because of network delays.
+ * This macro defines the interval of inactivity after which a keep alive messages
+ * is sent.
+ */
+#define mqttconfigKEEP_ALIVE_ACTUAL_INTERVAL_TICKS ( pdMS_TO_TICKS( 300000 ) )
+
+/**
+ * @brief The maximum interval in ticks to wait for PINGRESP.
+ *
+ * If PINGRESP is not received within this much time after sending PINGREQ,
+ * the client assumes that the PINGREQ timed out.
+ */
+#define mqttconfigKEEP_ALIVE_TIMEOUT_TICKS ( 1000 )
+
+/**
+ * @defgroup MQTTTask MQTT task configuration parameters.
+ */
+/** @{ */
+//#define mqttconfigMQTT_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 4 )
+#define mqttconfigMQTT_TASK_STACK_DEPTH ( 2048 )
+#define mqttconfigMQTT_TASK_PRIORITY ( configMAX_PRIORITIES - 3 )
+/** @} */
+
+/**
+ * @brief Maximum number of MQTT clients that can exist simultaneously.
+ */
+//#define mqttconfigMAX_BROKERS ( 4 ) //XXX
+#define mqttconfigMAX_BROKERS ( 2 )
+
+/**
+ * @brief Maximum number of parallel operations per client.
+ */
+#define mqttconfigMAX_PARALLEL_OPS ( 5 )
+
+/**
+ * @brief Time in milliseconds after which the TCP send operation should timeout.
+ */
+//#define mqttconfigTCP_SEND_TIMEOUT_MS ( 2000 )
+#define mqttconfigTCP_SEND_TIMEOUT_MS ( 20 )
+
+/**
+ * @brief Length of the buffer used to receive data.
+ */
+#define mqttconfigRX_BUFFER_SIZE ( 1024 )
+
+
+#endif /* _AWS_MQTT_AGENT_CONFIG_H_ */
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/config_files/aws_mqtt_config.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/config_files/aws_mqtt_config.h
new file mode 100644
index 00000000000..1e30818c953
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/config_files/aws_mqtt_config.h
@@ -0,0 +1,70 @@
+/*
+ * Amazon FreeRTOS V1.2.2
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://aws.amazon.com/freertos
+ * http://www.FreeRTOS.org
+ */
+
+/**
+ * @file aws_mqtt_config.h
+ * @brief MQTT config options.
+ */
+
+#ifndef _AWS_MQTT_CONFIG_H_
+#define _AWS_MQTT_CONFIG_H_
+
+#include
+
+/**
+ * @brief Enable subscription management.
+ *
+ * This gives the user flexibility of registering a callback per topic.
+ */
+#define mqttconfigENABLE_SUBSCRIPTION_MANAGEMENT ( 1 )
+
+/**
+ * @brief Maximum length of the topic which can be stored in subscription
+ * manager.
+ */
+#define mqttconfigSUBSCRIPTION_MANAGER_MAX_TOPIC_LENGTH ( 128 )
+
+/**
+ * @brief Maximum number of subscriptions which can be stored in subscription
+ * manager.
+ */
+#define mqttconfigSUBSCRIPTION_MANAGER_MAX_SUBSCRIPTIONS ( 8 )
+
+/*
+ * Uncomment the following two lines to enable asserts.
+ */
+/* extern void vAssertCalled( const char *pcFile, uint32_t ulLine ); */
+/* #define mqttconfigASSERT( x ) if( ( x ) == 0 ) vAssertCalled( __FILE__, __LINE__ ) */
+
+
+extern void vAssertCalled( void );
+#define mqttconfigASSERT( x ) if( ( x ) == 0 ) vAssertCalled()
+
+/**
+ * @brief Set this macro to 1 for enabling debug logs.
+ */
+#define mqttconfigENABLE_DEBUG_LOGS 1
+
+#endif /* _AWS_MQTT_CONFIG_H_ */
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/config_files/aws_ota_agent_config.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/config_files/aws_ota_agent_config.h
new file mode 100644
index 00000000000..398a7ce1b05
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/config_files/aws_ota_agent_config.h
@@ -0,0 +1,73 @@
+/*
+ * Amazon FreeRTOS V0.9.5
+ * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://aws.amazon.com/freertos
+ * http://www.FreeRTOS.org
+ */
+
+/**
+ * @file aws_ota_agent_config.h
+ * @brief OTA user configurable settings.
+ */
+
+#ifndef _AWS_OTA_AGENT_CONFIG_H_
+#define _AWS_OTA_AGENT_CONFIG_H_
+
+/**
+ * @brief The number of words allocated to the stack for the OTA agent.
+ */
+#define otaconfigSTACK_SIZE 3584U
+
+/**
+ * @brief Log base 2 of the size of the file data block message (excluding the header).
+ *
+ * 10 bits yields a data block size of 1KB.
+ */
+#define otaconfigLOG2_FILE_BLOCK_SIZE 10UL
+
+/**
+ * @brief Milliseconds to wait for the self test phase to succeed before we force reset.
+ */
+#define otaconfigSELF_TEST_RESPONSE_WAIT_MS 16000U
+
+/**
+ * @brief Milliseconds to wait before requesting data blocks from the OTA service if nothing is happening.
+ *
+ * The wait timer is reset whenever a data block is received from the OTA service so we will only send
+ * the request message after being idle for this amount of time.
+ */
+#define otaconfigFILE_REQUEST_WAIT_MS 2500U
+
+/**
+ * @brief The OTA agent task priority. Normally it runs at a low priority.
+ */
+#define otaconfigAGENT_PRIORITY tskIDLE_PRIORITY
+
+/**
+ * @brief The maximum allowed length of the thing name used by the OTA agent.
+ *
+ * AWS IoT requires Thing names to be unique for each device that connects to the broker.
+ * Likewise, the OTA agent requires the developer to construct and pass in the Thing name when
+ * initializing the OTA agent. The agent uses this size to allocate static storage for the
+ * Thing name used in all OTA base topics. Namely $aws/things/
+ */
+#define otaconfigMAX_THINGNAME_LEN 64U
+#endif /* _AWS_OTA_AGENT_CONFIG_H_ */
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/config_files/aws_pkcs11_config.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/config_files/aws_pkcs11_config.h
new file mode 100644
index 00000000000..f326ce15c88
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/config_files/aws_pkcs11_config.h
@@ -0,0 +1,44 @@
+/*
+ * Amazon FreeRTOS V1.2.5
+ * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://aws.amazon.com/freertos
+ * http://www.FreeRTOS.org
+ */
+
+/**
+ * @file aws_pkcs11_config.h
+ * @brief PCKS#11 config options.
+ */
+
+
+#ifndef _AWS_PKCS11_CONFIG_H_
+#define _AWS_PKCS11_CONFIG_H_
+
+/**
+ * @brief File storage location definitions.
+ */
+#define pkcs11configFILE_NAME_CLIENT_CERTIFICATE "FreeRTOS_P11_Certificate.dat"
+#define pkcs11configFILE_NAME_KEY "FreeRTOS_P11_Key.dat"
+
+/* A non-standard version of C_INITIALIZE should be used by this port. */
+/* #define pkcs11configC_INITIALIZE_ALT */
+
+#endif /* _AWS_PKCS11_CONFIG_H_ include guard. */
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/config_files/aws_secure_sockets_config.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/config_files/aws_secure_sockets_config.h
new file mode 100644
index 00000000000..0c6438cf924
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/config_files/aws_secure_sockets_config.h
@@ -0,0 +1,51 @@
+/*
+ * Amazon FreeRTOS V1.2.2
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://aws.amazon.com/freertos
+ * http://www.FreeRTOS.org
+ */
+
+/**
+ * @file aws_secure_sockets_config.h
+ * @brief Secure sockets configuration options.
+ */
+
+#ifndef _AWS_SECURE_SOCKETS_CONFIG_H_
+#define _AWS_SECURE_SOCKETS_CONFIG_H_
+
+/**
+ * @brief Byte order of the target MCU.
+ *
+ * Valid values are pdLITTLE_ENDIAN and pdBIG_ENDIAN.
+ */
+#define socketsconfigBYTE_ORDER pdLITTLE_ENDIAN
+
+/**
+ * @brief Default socket send timeout.
+ */
+#define socketsconfigDEFAULT_SEND_TIMEOUT ( 10000 )
+
+/**
+ * @brief Default socket receive timeout.
+ */
+#define socketsconfigDEFAULT_RECV_TIMEOUT ( 10000 )
+
+#endif /* _AWS_SECURE_SOCKETS_CONFIG_H_ */
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/config_files/aws_shadow_config.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/config_files/aws_shadow_config.h
new file mode 100644
index 00000000000..96f96151cdb
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/config_files/aws_shadow_config.h
@@ -0,0 +1,54 @@
+/*
+ * Amazon FreeRTOS V1.2.2
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://aws.amazon.com/freertos
+ * http://www.FreeRTOS.org
+ */
+
+/**
+ * @file aws_shadow_config.h
+ * @brief specify shadow config
+ */
+
+#ifndef _AWS_SHADOW_CONFIG_H_
+#define _AWS_SHADOW_CONFIG_H_
+
+/**
+ * @brief Number of jsmn tokens to use in parsing. Each jsmn token contains 4 ints.
+ * Ensure that the number of tokens does not overflow the calling task's stack,
+ * but is also sufficient to parse the largest expected JSON documents. */
+#define shadowConfigJSON_JSMN_TOKENS ( 64 )
+
+
+/**
+ * @brief
+ * The JSON key to search for when looking for client tokens.
+ */
+#define shadowConfigJSON_CLIENT_TOKEN "clientToken"
+
+
+/**
+ * @brief
+ * enable/disable shadowConfigUNIQUE_CLIENT_TOKEN_CHECK check.
+ */
+#define shadowConfigUNIQUE_CLIENT_TOKEN_CHECK 0
+
+#endif /* _AWS_SHADOW_CONFIG_H_ */
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/config_files/aws_wifi_config.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/config_files/aws_wifi_config.h
new file mode 100644
index 00000000000..1783f269103
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/config_files/aws_wifi_config.h
@@ -0,0 +1,97 @@
+/*
+ * Amazon FreeRTOS V1.2.2
+ * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://aws.amazon.com/freertos
+ * http://www.FreeRTOS.org
+ */
+
+/**
+ * @file aws_wifi_config.h
+ * @brief WiFi module configuration parameters.
+ */
+
+#ifndef _AWS_WIFI_CONFIG_H_
+#define _AWS_WIFI_CONFIG_H_
+
+/**
+ * @brief Maximum number of sockets that can be created simultaneously.
+ */
+#define wificonfigMAX_SOCKETS ( 4 )
+
+/**
+ * @brief Maximum number of connection retries.
+ */
+#define wificonfigNUM_CONNECTION_RETRY ( 3 )
+
+/**
+ * @brief Maximum number of connected station in Access Point mode.
+ */
+#define wificonfigMAX_CONNECTED_STATIONS ( 4 )
+
+/**
+ * @brief Max number of network profiles stored in Non Volatile memory,
+ * set to zero if not supported.
+ */
+#define wificonfigMAX_NETWORK_PROFILES ( 0 )
+
+/**
+ * @brief Max SSID length
+ */
+#define wificonfigMAX_SSID_LEN ( 32 )
+
+/**
+ * @brief Max BSSID length
+ */
+#define wificonfigMAX_BSSID_LEN ( 6 )
+
+/**
+ * @brief Max passphrase length
+ */
+#define wificonfigMAX_PASSPHRASE_LEN ( 32 )
+
+/**
+ * @brief Soft Access point SSID
+ */
+#define wificonfigACCESS_POINT_SSID_PREFIX ( "Enter SSID for Soft AP" )
+
+/**
+ * @brief Soft Access point Passkey
+ */
+#define wificonfigACCESS_POINT_PASSKEY ( "Enter Password for Soft AP" )
+
+/**
+ * @brief Soft Access point Channel
+ */
+#define wificonfigACCESS_POINT_CHANNEL ( 11 )
+
+/**
+ * @brief WiFi semaphore timeout
+ */
+#define wificonfigMAX_SEMAPHORE_WAIT_TIME_MS ( 60000 )
+
+/**
+ * @brief Soft Access point security
+ * WPA2 Security, see WIFISecurity_t
+ * other values are - eWiFiSecurityOpen, eWiFiSecurityWEP, eWiFiSecurityWPA
+ */
+#define wificonfigACCESS_POINT_SECURITY ( eWiFiSecurityWPA2 )
+
+#endif /* _AWS_WIFI_CONFIG_H_ */
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/.cproject b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/.cproject
new file mode 100644
index 00000000000..7c5e69d3db9
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/.cproject
@@ -0,0 +1,133 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/.gitignore b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/.gitignore
new file mode 100644
index 00000000000..a12093180d9
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/.gitignore
@@ -0,0 +1 @@
+/HardwareDebug/
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/.project b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/.project
new file mode 100644
index 00000000000..def54ddf1ec
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/.project
@@ -0,0 +1,429 @@
+
+
+ aws_demos
+
+
+
+
+
+ org.eclipse.xtext.ui.shared.xtextBuilder
+
+
+
+
+ org.eclipse.cdt.managedbuilder.core.genmakebuilder
+ clean,full,incremental,
+
+
+
+
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+ full,incremental,
+
+
+
+
+
+ org.eclipse.cdt.core.cnature
+ org.eclipse.cdt.managedbuilder.core.managedBuildNature
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+ org.eclipse.xtext.ui.shared.xtextNature
+
+
+
+ application_code
+ 2
+ AWS_IOT_MCU_ROOT/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/application_code
+
+
+ config_files
+ 2
+ AWS_IOT_MCU_ROOT/demos/renesas/rx65n-tb-uart-sx-ulpgn/common/config_files
+
+
+ lib
+ 2
+ virtual:/virtual
+
+
+ application_code/common_demos
+ 2
+ virtual:/virtual
+
+
+ lib/aws
+ 2
+ virtual:/virtual
+
+
+ lib/third_party
+ 2
+ virtual:/virtual
+
+
+ src/compiler_support
+ 2
+ AWS_IOT_MCU_ROOT/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/gnurx/compiler_support
+
+
+ application_code/common_demos/include
+ 2
+ AWS_IOT_MCU_ROOT/demos/common/include
+
+
+ application_code/common_demos/source
+ 2
+ virtual:/virtual
+
+
+ lib/aws/FreeRTOS
+ 2
+ AWS_IOT_MCU_ROOT/lib/FreeRTOS
+
+
+ lib/aws/bufferpool
+ 2
+ AWS_IOT_MCU_ROOT/lib/bufferpool
+
+
+ lib/aws/crypto
+ 2
+ AWS_IOT_MCU_ROOT/lib/crypto
+
+
+ lib/aws/greengrass
+ 2
+ AWS_IOT_MCU_ROOT/lib/greengrass
+
+
+ lib/aws/include
+ 2
+ AWS_IOT_MCU_ROOT/lib/include
+
+
+ lib/aws/mqtt
+ 2
+ AWS_IOT_MCU_ROOT/lib/mqtt
+
+
+ lib/aws/ota
+ 2
+ AWS_IOT_MCU_ROOT/lib/ota/portable/renesas/rx65n-tb-uart-sx-ulpgn
+
+
+ lib/aws/pkcs11
+ 2
+ AWS_IOT_MCU_ROOT/lib/pkcs11/portable/renesas/rx65n-tb-uart-sx-ulpgn
+
+
+ lib/aws/secure_sockets
+ 2
+ AWS_IOT_MCU_ROOT/lib/secure_sockets/portable/renesas/rx65n-tb-uart-sx-ulpgn
+
+
+ lib/aws/shadow
+ 2
+ AWS_IOT_MCU_ROOT/lib/shadow
+
+
+ lib/aws/tls
+ 2
+ AWS_IOT_MCU_ROOT/lib/tls
+
+
+ lib/aws/utils
+ 2
+ AWS_IOT_MCU_ROOT/lib/utils
+
+
+ lib/aws/wifi
+ 2
+ AWS_IOT_MCU_ROOT/lib/wifi/portable/renesas/rx65n-tb-uart-sx-ulpgn
+
+
+ lib/third_party/jsmn
+ 2
+ AWS_IOT_MCU_ROOT/lib/third_party/jsmn
+
+
+ lib/third_party/mbedtls
+ 2
+ virtual:/virtual
+
+
+ lib/third_party/mcu_vendor
+ 2
+ virtual:/virtual
+
+
+ lib/third_party/pkcs11
+ 2
+ AWS_IOT_MCU_ROOT/lib/third_party/pkcs11
+
+
+ lib/third_party/tinycbor
+ 2
+ AWS_IOT_MCU_ROOT/lib/third_party/tinycbor
+
+
+ src/FIT_modified_code/r_bsp
+ 2
+ AWS_IOT_MCU_ROOT/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/gnurx/generic_rx65n/r_bsp
+
+
+ src/FIT_modified_code/r_byteq
+ 2
+ AWS_IOT_MCU_ROOT/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/r_byteq
+
+
+ src/FIT_modified_code/r_cmt_rx
+ 2
+ AWS_IOT_MCU_ROOT/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/r_cmt_rx
+
+
+ src/FIT_modified_code/r_flash_rx
+ 2
+ AWS_IOT_MCU_ROOT/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/r_flash_rx
+
+
+ src/FIT_modified_code/r_riic_rx
+ 2
+ AWS_IOT_MCU_ROOT/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/r_riic_rx
+
+
+ src/FIT_modified_code/r_sci_iic_rx
+ 2
+ AWS_IOT_MCU_ROOT/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/r_sci_iic_rx
+
+
+ src/FIT_modified_code/r_sci_rx
+ 2
+ AWS_IOT_MCU_ROOT/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/r_sci_rx
+
+
+ src/compiler_support/register_access
+ 2
+ AWS_IOT_MCU_ROOT/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/ccrx/compiler_support/register_access/rx65n
+
+
+ application_code/common_demos/include/aws_application_version.h
+ 1
+ AWS_IOT_MCU_ROOT/demos/common/include/aws_application_version.h
+
+
+ application_code/common_demos/include/aws_clientcredential_keys.h
+ 1
+ AWS_IOT_MCU_ROOT/demos/common/include/aws_clientcredential_keys.h
+
+
+ application_code/common_demos/include/aws_dev_mode_key_provisioning.h
+ 1
+ AWS_IOT_MCU_ROOT/demos/common/include/aws_dev_mode_key_provisioning.h
+
+
+ application_code/common_demos/source/aws_demo_runner.c
+ 1
+ AWS_IOT_MCU_ROOT/demos/common/demo_runner/aws_demo_runner.c
+
+
+ application_code/common_demos/source/aws_dev_mode_key_provisioning.c
+ 1
+ AWS_IOT_MCU_ROOT/demos/common/devmode_key_provisioning/aws_dev_mode_key_provisioning.c
+
+
+ application_code/common_demos/source/aws_greengrass_discovery_demo.c
+ 1
+ AWS_IOT_MCU_ROOT/demos/common/greengrass_connectivity/aws_greengrass_discovery_demo.c
+
+
+ application_code/common_demos/source/aws_hello_world.c
+ 1
+ AWS_IOT_MCU_ROOT/demos/common/mqtt/aws_hello_world.c
+
+
+ application_code/common_demos/source/aws_logging_task_dynamic_buffers.c
+ 1
+ AWS_IOT_MCU_ROOT/demos/common/logging/aws_logging_task_dynamic_buffers.c
+
+
+ application_code/common_demos/source/aws_ota_update_demo.c
+ 1
+ AWS_IOT_MCU_ROOT/demos/common/ota/aws_ota_update_demo.c
+
+
+ application_code/common_demos/source/aws_shadow_lightbulb_on_off.c
+ 1
+ AWS_IOT_MCU_ROOT/demos/common/shadow/aws_shadow_lightbulb_on_off.c
+
+
+ application_code/common_demos/source/aws_subscribe_publish_loop.c
+ 1
+ AWS_IOT_MCU_ROOT/demos/common/mqtt/aws_subscribe_publish_loop.c
+
+
+ application_code/common_demos/source/aws_tcp_echo_client_separate_tasks.c
+ 1
+ AWS_IOT_MCU_ROOT/demos/common/tcp/aws_tcp_echo_client_separate_tasks.c
+
+
+ application_code/common_demos/source/aws_tcp_echo_client_single_task.c
+ 1
+ AWS_IOT_MCU_ROOT/demos/common/tcp/aws_tcp_echo_client_single_task.c
+
+
+ lib/aws/ota/aws_ota_agent.c
+ 1
+ AWS_IOT_MCU_ROOT/lib/ota/aws_ota_agent.c
+
+
+ lib/aws/ota/aws_ota_cbor.c
+ 1
+ AWS_IOT_MCU_ROOT/lib/ota/aws_ota_cbor.c
+
+
+ lib/aws/pkcs11/aws_pkcs11_mbedtls.c
+ 1
+ AWS_IOT_MCU_ROOT/lib/pkcs11/mbedtls/aws_pkcs11_mbedtls.c
+
+
+ lib/third_party/mbedtls/include
+ 2
+ AWS_IOT_MCU_ROOT/lib/third_party/mbedtls/include
+
+
+ lib/third_party/mbedtls/source
+ 2
+ AWS_IOT_MCU_ROOT/lib/third_party/mbedtls/library
+
+
+ lib/third_party/mcu_vendor/renesas
+ 2
+ AWS_IOT_MCU_ROOT/lib/third_party/mcu_vendor/renesas
+
+
+
+
+ 1532925745925
+
+ 6
+
+ org.eclipse.ui.ide.multiFilter
+ 1.0-name-matches-false-false-aws_demos_build_path_check_and_make.bat
+
+
+
+ 1513514174593
+
+ 10
+
+ org.eclipse.ui.ide.multiFilter
+ 1.0-name-matches-false-false-
+
+
+
+ 1534518723747
+ src/compiler_support/register_access
+ 10
+
+ org.eclipse.ui.ide.multiFilter
+ 1.0-name-matches-false-false-*
+
+
+
+ 1513514756448
+ lib/aws/FreeRTOS/portable
+ 9
+
+ org.eclipse.ui.ide.multiFilter
+ 1.0-name-matches-false-false-GCC
+
+
+
+ 1513514757749
+ lib/aws/FreeRTOS/portable
+ 9
+
+ org.eclipse.ui.ide.multiFilter
+ 1.0-name-matches-false-false-MemMang
+
+
+
+ 1513514757807
+ lib/aws/FreeRTOS/portable
+ 6
+
+ org.eclipse.ui.ide.multiFilter
+ 1.0-name-matches-false-false-*
+
+
+
+ 1509693556349
+ lib/aws/include/private
+ 6
+
+ org.eclipse.ui.ide.multiFilter
+ 1.0-name-matches-false-false-*.c
+
+
+
+ 1513515128489
+ lib/aws/FreeRTOS/portable/GCC
+ 9
+
+ org.eclipse.ui.ide.multiFilter
+ 1.0-name-matches-false-false-RX600v2
+
+
+
+ 1513514967899
+ lib/aws/FreeRTOS/portable/MemMang
+ 5
+
+ org.eclipse.ui.ide.multiFilter
+ 1.0-name-matches-false-false-heap_4.c
+
+
+
+ 1564441856894
+ src/FIT_modified_code/r_flash_rx/src/targets
+ 9
+
+ org.eclipse.ui.ide.multiFilter
+ 1.0-name-matches-false-false-rx65n
+
+
+
+ 1535360922766
+ src/FIT_modified_code/r_riic_rx/src/targets
+ 9
+
+ org.eclipse.ui.ide.multiFilter
+ 1.0-name-matches-false-false-rx65n
+
+
+
+ 1535360980389
+ src/FIT_modified_code/r_sci_iic_rx/src/targets
+ 9
+
+ org.eclipse.ui.ide.multiFilter
+ 1.0-name-matches-false-false-rx65n
+
+
+
+ 1564441820170
+ src/FIT_modified_code/r_sci_rx/src/targets
+ 9
+
+ org.eclipse.ui.ide.multiFilter
+ 1.0-name-matches-false-false-rx65n
+
+
+
+
+
+ AWS_IOT_MCU_ROOT
+ $%7BPARENT-4-PROJECT_LOC%7D
+
+
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/.settings/CodeGenerator/cgprojectDatas.datas b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/.settings/CodeGenerator/cgprojectDatas.datas
new file mode 100644
index 00000000000..e69de29bb2d
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/.settings/com.renesas.smc.e2studio.qe.xml b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/.settings/com.renesas.smc.e2studio.qe.xml
new file mode 100644
index 00000000000..398207a0fcf
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/.settings/com.renesas.smc.e2studio.qe.xml
@@ -0,0 +1,34 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/.settings/e2studio_project.prefs b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/.settings/e2studio_project.prefs
new file mode 100644
index 00000000000..dc4089142f7
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/.settings/e2studio_project.prefs
@@ -0,0 +1,2 @@
+#
+#Wed Aug 29 16:48:08 JST 2018
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/.settings/fittemp/r_sci_rx.ftl b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/.settings/fittemp/r_sci_rx.ftl
new file mode 100644
index 00000000000..62879ddbbe9
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/.settings/fittemp/r_sci_rx.ftl
@@ -0,0 +1,85 @@
+<#--
+ Copyright(C) 2015 Renesas Electronics Corporation
+ RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
+ This program must be used solely for the purpose for which it was furnished
+ by Renesas Electronics Corporation. No part of this program may be reproduced
+ or disclosed to others, in any form, without the prior written permission of
+ Renesas Electronics Corporation.
+-->
+<#-- = DECLARE FUNCTION INFORMATION HERE =================== -->
+<#--
+ (Step 1) Explanation: These variables are necessary information for the function header.
+ Please fill up or leave blank, but do not delete
+-->
+<#assign Function_Base_Name = "R_SCI_PinSet">
+<#assign Function_Description = "This function initializes pins for r_sci_rx module">
+<#assign Function_Arg = "none">
+<#assign Function_Ret = "none">
+<#assign Version = 1.00>
+
+<#-- = DECLARE FUNCTION CONTENT HERE ======================= -->
+<#--
+ (Step 2) Explanation: Function content.
+ - Macro [initialsection] :
+ Any text that goes into this section will be printed out 1 time per function
+ input [postfix] :Use this variable to add the channel number to the function base name.
+-->
+<#macro initialsection postfix>
+<#assign Function_Name = "${Function_Base_Name}${postfix}">
+<#include "lib/functionheader.ftl">
+void ${Function_Name}()
+{
+ R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_MPC);
+
+
+<#--
+ (Step 3) Explanation: Function content.
+ - Macro [peripheralpincode] : Any text that goes into this section will be printed out 1 time per peripheral
+ - input [pin] : Available info includes:
+ pin.pinName :The name of pin, eg “SSLA0”
+ pin.assignedPinName :The pin assigned to, eg “P32”
+ pin.pinMPC :The port number of assigned pin, eg “P32” has portNume = “3”
+ pin.portNum :The bit number of the assigned pin, eg “P32” has pinBitNum = “2”
+ pin.pinBitNum :The value of MPC
+-->
+<#macro peripheralpincode pin>
+
+
+<#--
+ (Step 4) Explanation: Function content.
+ - Macro [channelpincode] : Any text that goes into this section will be printed out 1 time per channel
+ - input [pin] : Same as above
+-->
+<#macro channelpincode pin>
+
+ /* Set ${pin.pinName} pin */
+ MPC.${pin.assignedPinName}PFS.BYTE = 0x${pin.pinMPC}U;
+ PORT${pin.portNum}.PMR.BIT.B${pin.pinBitNum} = 1U;
+
+
+<#macro channelpincodeextra pin postfix>
+
+
+<#--
+ (Step 5) Explanation: Function content.
+ - Macro [endsection] : Any text that goes into this section will be printed out 1 time last
+-->
+<#macro endsection>
+
+ R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_MPC);
+}
+
+
+<#--
+ (Step 6) Explanation: Header file content
+ - Macro [headerfilesection] : Any text that goes into this section will be printed out 1 time in the header file
+ - input [postfix] :Use this variable to add the channel number to the function base name.
+-->
+<#macro headerfilesection postfix>
+void ${Function_Base_Name}${postfix}();
+
+
+<#macro headerfilesectionExtra postfix>
+
+
+<#-- = END OF FILE ========================================= -->
\ No newline at end of file
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/.settings/language.settings.xml b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/.settings/language.settings.xml
new file mode 100644
index 00000000000..835871043ed
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/.settings/language.settings.xml
@@ -0,0 +1,13 @@
+
+
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+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/.settings/org.eclipse.cdt.managedbuilder.core.prefs
new file mode 100644
index 00000000000..817b60cba1c
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/.settings/org.eclipse.cdt.managedbuilder.core.prefs
@@ -0,0 +1,9 @@
+eclipse.preferences.version=1
+environment/buildEnvironmentInclude/com.renesas.cdt.managedbuild.gcc.rx.configuration.debug.365004355/CPATH/delimiter=;
+environment/buildEnvironmentInclude/com.renesas.cdt.managedbuild.gcc.rx.configuration.debug.365004355/CPATH/operation=remove
+environment/buildEnvironmentInclude/com.renesas.cdt.managedbuild.gcc.rx.configuration.debug.365004355/C_INCLUDE_PATH/delimiter=;
+environment/buildEnvironmentInclude/com.renesas.cdt.managedbuild.gcc.rx.configuration.debug.365004355/C_INCLUDE_PATH/operation=remove
+environment/buildEnvironmentInclude/com.renesas.cdt.managedbuild.gcc.rx.configuration.debug.365004355/LIBRARY_PATH/delimiter=;
+environment/buildEnvironmentInclude/com.renesas.cdt.managedbuild.gcc.rx.configuration.debug.365004355/LIBRARY_PATH/operation=remove
+environment/buildEnvironmentInclude/com.renesas.cdt.managedbuild.gcc.rx.configuration.debug.365004355/append=true
+environment/buildEnvironmentInclude/com.renesas.cdt.managedbuild.gcc.rx.configuration.debug.365004355/appendContributed=true
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/aws_demos.scfg b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/aws_demos.scfg
new file mode 100644
index 00000000000..e2d4cefabde
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/aws_demos.scfg
@@ -0,0 +1,484 @@
+
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diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/aws_demos_build_path_check_and_make.bat b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/aws_demos_build_path_check_and_make.bat
new file mode 100644
index 00000000000..047f6e34780
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/aws_demos_build_path_check_and_make.bat
@@ -0,0 +1,11 @@
+@echo off
+rem ################################################################################
+rem # This batch file executes some preprocess for build and then executes the make
+rem ################################################################################
+
+if not exist "%~dp0..\..\..\..\lib\third_party\mcu_vendor\renesas\tools\aws_demos_build_path_check_and_make.bat" (
+ echo ERROR: Unable to find "%~dp0..\..\..\..\lib\third_party\mcu_vendor\renesas\tools\aws_demos_build_path_check_and_make.bat"
+ exit 2
+)
+
+"%~dp0..\..\..\..\lib\third_party\mcu_vendor\renesas\tools\aws_demos_build_path_check_and_make.bat" %*
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/rx65n_tb_aws HardwareDebug.launch b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/rx65n_tb_aws HardwareDebug.launch
new file mode 100644
index 00000000000..8b119840b92
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/rx65n_tb_aws HardwareDebug.launch
@@ -0,0 +1,155 @@
+
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diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/FIT_modified_code/attention!.txt b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/FIT_modified_code/attention!.txt
new file mode 100644
index 00000000000..eba837b820a
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/FIT_modified_code/attention!.txt
@@ -0,0 +1,39 @@
+Please note that the following folders in the project window of IDEs are
+so called 'linked' folders.
+
+--------------------------------------------
+Linked folders in the project window of IDEs
+--------------------------------------------
+
+src/compiler_support
+src/FIT_modified_code/r_bsp
+
+src/FIT_modified_code/r_byteq
+src/FIT_modified_code/r_cmt_rx
+src/FIT_modified_code/r_ether_rx
+src/FIT_modified_code/r_flash_rx
+src/FIT_modified_code/r_sci_rx
+
+----------------------------------------------------------
+Folders on the File System of the WINDOWS Operating System
+----------------------------------------------------------
+
+CC-RX/e2 studio & CC-RX/CS+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/ccrx/compiler_support
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/ccrx/generic_rx65n/r_bsp
+
+GNURX/e2 studio
+~~~~~~~~~~~~~~~
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/gnurx/compiler_support
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/gnurx/generic_rx65n/r_bsp
+
+All
+~~~
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/r_byteq
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/r_cmt_rx
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/r_ether_rx
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/r_flash_rx
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/r_sci_rx
+
+[EOF]
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/FIT_modified_code/r_config/r_byteq_config.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/FIT_modified_code/r_config/r_byteq_config.h
new file mode 100644
index 00000000000..0b4d4f9bb52
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/FIT_modified_code/r_config/r_byteq_config.h
@@ -0,0 +1,59 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : r_byteq_config.h
+* Description : Configures the byte queue memory allocation
+************************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 24.07.2013 1.00 Initial Release
+* : 11.21.2014 1.20 Removed dependency to BSP
+* : 30.09.2015 1.50 Added dependency to BSP
+***********************************************************************************************************************/
+#ifndef BYTEQ_CONFIG_H
+#define BYTEQ_CONFIG_H
+
+/***********************************************************************************************************************
+Includes , "Project Includes"
+***********************************************************************************************************************/
+#include "platform.h"
+
+/***********************************************************************************************************************
+Configuration Options
+***********************************************************************************************************************/
+
+/* SPECIFY WHETHER TO INCLUDE CODE FOR API PARAMETER CHECKING
+ Available settings:
+ BSP_CFG_PARAM_CHECKING_ENABLE:
+ Utilizes the system default setting
+ 1:
+ Includes parameter checking
+ 0:
+ Compiles out parameter checking
+*/
+#define BYTEQ_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+
+/* SPECIFY IF SHOULD USE MALLOC() TO ALLOCATE MEMORY FOR QUEUE CONTROL BLOCKS */
+#define BYTEQ_CFG_USE_HEAP_FOR_CTRL_BLKS (0)
+
+/* SPECIFY NUMBER OF STATIC QUEUE CONTROL BLOCKS TO SUPPORT */
+/* valid only when BYTEQ_USE_HEAP_FOR_CTRL_BLKS is set to 0 */
+#define BYTEQ_CFG_MAX_CTRL_BLKS (4)
+
+
+#endif /* BYTEQ_CONFIG_H */
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/FIT_modified_code/r_config/r_cmt_rx_config.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/FIT_modified_code/r_config/r_cmt_rx_config.h
new file mode 100644
index 00000000000..e043e41b29d
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/FIT_modified_code/r_config/r_cmt_rx_config.h
@@ -0,0 +1,37 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : r_cmt_rx_config.h
+* Description : Configures the r_cmt_rx code.
+************************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 06.11.2013 2.00 First GSCE Release.
+***********************************************************************************************************************/
+#ifndef CMT_CONFIG_HEADER_FILE
+#define CMT_CONFIG_HEADER_FILE
+
+/***********************************************************************************************************************
+Configuration Options
+***********************************************************************************************************************/
+/* The interrupt priority level to be used for CMT interrupts. */
+#define CMT_RX_CFG_IPR (5)
+
+#endif /* CMT_CONFIG_HEADER_FILE */
+
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/FIT_modified_code/r_config/r_flash_rx_config.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/FIT_modified_code/r_config/r_flash_rx_config.h
new file mode 100644
index 00000000000..fbf916a0e97
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/FIT_modified_code/r_config/r_flash_rx_config.h
@@ -0,0 +1,116 @@
+/***********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+ * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+ * SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+ ***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * File Name : r_flash_rx_config_reference.h
+ * Description : Configures the FLASH API module for RX200 and RX600 Series MCU's.
+ ***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* 12.04.2014 1.00 First Release
+* 22.12.2014 1.10 Added flash type usage comments.
+* 25.06.2015 1.20 Added FLASH_CFG_CODE_FLASH_RUN_FROM_ROM.
+* : 12.10.2016 2.00 Modified for BSPless operation (added FLASH_CFG_USE_FIT_BSP).
+***********************************************************************************************************************/
+#ifndef FLASH_CONFIG_HEADER_FILE
+#define FLASH_CONFIG_HEADER_FILE
+
+/* Set the following value to 0 when building without using the FIT BSP Module */
+#define FLASH_CFG_USE_FIT_BSP (1)
+
+
+/***********************************************************************************************************************
+ Configuration Options
+ ***********************************************************************************************************************/
+/* SPECIFY WHETHER TO INCLUDE CODE FOR API PARAMETER CHECKING
+ * Setting to BSP_CFG_PARAM_CHECKING_ENABLE utilizes the system default setting
+ * Setting to 1 includes parameter checking; 0 compiles out parameter checking
+ */
+#define FLASH_CFG_PARAM_CHECKING_ENABLE (1)
+
+
+/******************************************************************************
+ ENABLE CODE FLASH PROGRAMMING
+******************************************************************************/
+/* If you are only using data flash, set this to 0.
+ * Setting to 1 includes code to program the ROM area. When programming ROM,
+ * code must be executed from RAM, except under certain restrictions for flash
+ * type 3 (see section 2.14 in App Note). See section 2.13 in the App Note for
+ * details on how to set up code and the linker to execute code from RAM.
+ */
+#define FLASH_CFG_CODE_FLASH_ENABLE (0)
+
+
+/******************************************************************************
+ ENABLE BGO/NON-BLOCKING DATA FLASH OPERATIONS
+******************************************************************************/
+/* Setting this to 0 forces data flash API function to block until completed.
+ * Setting to 1 places the module in BGO (background operations) mode. In BGO
+ * mode, data flash operations return immediately after the operation has been
+ * started. Notification of the operation completion is done via the callback
+ * function.
+ */
+#define FLASH_CFG_DATA_FLASH_BGO (0)
+
+
+/******************************************************************************
+ ENABLE BGO/NON-BLOCKING CODE FLASH (ROM) OPERATIONS
+******************************************************************************/
+/* Setting this to 0 forces ROM API function to block until completed.
+ * Setting to 1 places the module in BGO (background operations) mode. In BGO
+ * mode, ROM operations return immediately after the operation has been started.
+ * Notification of the operation completion is done via the callback function.
+ * When reprogramming ROM, THE RELOCATABLE VECTOR TABLE AND CORRESPONDING
+ * INTERRUPT ROUTINES MUST BE IN RAM.
+ * See sections 2.16 Usage Notes in the App Note.
+ */
+#define FLASH_CFG_CODE_FLASH_BGO (0)
+
+
+/******************************************************************************
+ ENABLE CODE FLASH SELF-PROGRAMMING
+******************************************************************************/
+/* Set this to 0 when programming code flash while executing in RAM.
+ * Set this to 1 when programming code flash while executing from another
+ * segment in ROM (possible only with RX64M, RX71M, RX65N-2 groups).
+ * See section 2.14 in the App Note.
+ */
+#define FLASH_CFG_CODE_FLASH_RUN_FROM_ROM (0)
+
+
+/******************************************************************************
+ SET IPL OF FLASH READY INTERRUPT
+******************************************************************************/
+#define FLASH_CFG_FLASH_READY_IPL (5) // Flash type 2 only
+
+
+/******************************************************************************
+ ENABLE OR DISABLE LOCK BIT PROTECTION
+******************************************************************************/
+/* Each erasure block has a corresponding lock bit that can be used to
+ * protect that block from being programmed/erased after the lock bit is
+ * set. The use of lock bits can be used or ignored.
+ * Setting this to 1 will cause lock bits to be ignored and programs/erases to a
+ * block will not be limited.
+ * Setting this to 0 will cause lock bits to be used as the user configures through
+ * the Control command. This only applies to ROM as the DF does not have lock bits.
+ */
+#define FLASH_CFG_IGNORE_LOCK_BITS (1) // Flash type 2 only
+
+
+#endif /* FLASH_CONFIG_HEADER_FILE */
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/FIT_modified_code/r_config/r_riic_rx_config.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/FIT_modified_code/r_config/r_riic_rx_config.h
new file mode 100644
index 00000000000..162cde5ea41
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/FIT_modified_code/r_config/r_riic_rx_config.h
@@ -0,0 +1,197 @@
+/***********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+ * No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO
+ * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
+ **********************************************************************************************************************/
+/***********************************************************************************************************************
+ * File Name : r_riic_rx_config_reference.h
+ * Description : Configures the RIIC drivers
+ **********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ * : 01.07.2013 1.00 First Release
+ * : 30.09.2013 1.10 Change symbol of return value and status
+ * : 08.10.2013 1.20 Modified processing for the I/O register initialization and mode transition
+ * when a stop condition is detected while the slave is communicating.
+ * Modified processing for mode transition when an API function is called
+ * while the bus is busy.
+ * Modified processing for mode transition
+ * when an arbitration lost occurred and the addresses do not match.
+ * Modified incorrect slave transmission after the master reception.
+ * Modified processing for the I/O register initialization
+ * when generating a start condition and receiving the slave address.
+ * : 17.07.2014 1.30 Added the parameters of channel 2.
+ * Deleted the parameters of PCLK.
+ * Added the parameters of the port function assignment.
+ * Changed the parameters of interrupt priority level.
+ * Added the parameters for the time out detection.
+ * : 22.09.2014 1.40 The module is updated to measure the issue that slave communication
+ * is not available after an arbitration-lost occurs and the bus is locked.
+ * The issue occurs when the following four conditions are all met.
+ * - RIIC FIT module rev. 1.30 or earlier is used.
+ * - RX device operates as both the master and the slave
+ * in multi-master communication.
+ * - An arbitration-lost is detected when communicating as the master.
+ * - Communication other than master reception or slave reception is performed.
+ * : 14.11.2014 1.50 Added RX113 support.
+ * : 09.10.2014 1.60 Added RX71M support.
+ * : 20.10.2014 1.70 Added RX231 support.
+ * : 31.10.2015 1.80 Added RX130, RX230, RX23T support.
+ * : 04.03.2016 1.90 Added RX24T support.Changed about the pin definisions.
+ * : 01.10.2016 2.00 Added RX65N support.
+ * : 02.06.2017 2.10 Added RX24U support.
+ * : 31.08.2017 2.20 Added definitions for Channel 1.
+ **********************************************************************************************************************/
+/* Guards against multiple inclusion */
+#ifndef RIIC_CONFIG_H
+ #define RIIC_CONFIG_H
+/***********************************************************************************************************************
+ Configuration Options
+ **********************************************************************************************************************/
+/* SPECIFY WHETHER TO INCLUDE CODE FOR API PARAMETER CHECKING */
+/* Setting to BSP_CFG_PARAM_CHECKING_ENABLE utilizes the system default setting */
+/* Setting to 1 includes parameter checking; 0 compiles out parameter checking */
+ #define RIIC_CFG_PARAM_CHECKING_ENABLE (1U)
+
+/* SPECIFY CHANNELS TO INCLUDE SOFTWARE SUPPORT FOR 1=included, 0=not */
+/* mcu supported channels */
+/* RX110: ch0, , */
+/* RX111: ch0, , */
+/* RX113: ch0, , */
+/* RX130: ch0, , */
+/* RX230: ch0, , */
+/* RX231: ch0, , */
+/* RX23T: ch0, , */
+/* RX24T: ch0, , */
+/* RX24U: ch0, , */
+/* RX64M: ch0, , ch2 */
+/* RX65N: ch0, ch1, ch2 */
+/* RX71M: ch0, , ch2 */
+ #define RIIC_CFG_CH0_INCLUDED (1U)
+ #define RIIC_CFG_CH1_INCLUDED (0U)
+ #define RIIC_CFG_CH2_INCLUDED (0U)
+
+/* Set RIIC bps(kbps) */
+ #define RIIC_CFG_CH0_kBPS (400U)
+ #define RIIC_CFG_CH1_kBPS (400U)
+ #define RIIC_CFG_CH2_kBPS (400U)
+
+/* Set using digital filter(Selected IIC phi cycle is filtered out) */
+/* 0 = not, 1 = one IIC phi, 2 = two IIC phi, 3 = three IIC phi, 4 = four IIC phi */
+ #define RIIC_CFG_CH0_DIGITAL_FILTER (2U)
+ #define RIIC_CFG_CH1_DIGITAL_FILTER (2U)
+ #define RIIC_CFG_CH2_DIGITAL_FILTER (2U)
+
+/* Setting to */
+/* 1: includes riic port setting processing */
+/* 0: compiles out riic port setting processing */
+ #define RIIC_CFG_PORT_SET_PROCESSING (1U)
+
+/* Set mode */
+/* 0 = single master mode, 1 = multi master mode(Master arbitration-lost detection is enabled.) */
+ #define RIIC_CFG_CH0_MASTER_MODE (1U)
+ #define RIIC_CFG_CH1_MASTER_MODE (1U)
+ #define RIIC_CFG_CH2_MASTER_MODE (1U)
+
+/* Set slave address */
+/* 0 = not, 1 = 7bit address format, 2 = 10bit address format */
+ #define RIIC_CFG_CH0_SLV_ADDR0_FORMAT (1U)
+ #define RIIC_CFG_CH0_SLV_ADDR1_FORMAT (0U)
+ #define RIIC_CFG_CH0_SLV_ADDR2_FORMAT (0U)
+
+ #define RIIC_CFG_CH0_SLV_ADDR0 (0x0025)
+ #define RIIC_CFG_CH0_SLV_ADDR1 (0x0000)
+ #define RIIC_CFG_CH0_SLV_ADDR2 (0x0000)
+
+ #define RIIC_CFG_CH1_SLV_ADDR0_FORMAT (1U)
+ #define RIIC_CFG_CH1_SLV_ADDR1_FORMAT (0U)
+ #define RIIC_CFG_CH1_SLV_ADDR2_FORMAT (0U)
+
+ #define RIIC_CFG_CH1_SLV_ADDR0 (0x0025)
+ #define RIIC_CFG_CH1_SLV_ADDR1 (0x0000)
+ #define RIIC_CFG_CH1_SLV_ADDR2 (0x0000)
+
+ #define RIIC_CFG_CH2_SLV_ADDR0_FORMAT (1U)
+ #define RIIC_CFG_CH2_SLV_ADDR1_FORMAT (0U)
+ #define RIIC_CFG_CH2_SLV_ADDR2_FORMAT (0U)
+
+ #define RIIC_CFG_CH2_SLV_ADDR0 (0x0025)
+ #define RIIC_CFG_CH2_SLV_ADDR1 (0x0000)
+ #define RIIC_CFG_CH2_SLV_ADDR2 (0x0000)
+
+/* Select General call address */
+/* 0 = not use, 1 = use(General call address detection is enabled.) */
+ #define RIIC_CFG_CH0_SLV_GCA_ENABLE (0U)
+ #define RIIC_CFG_CH1_SLV_GCA_ENABLE (0U)
+ #define RIIC_CFG_CH2_SLV_GCA_ENABLE (0U)
+
+/* This #define sets the priority level for the riic interrupt */
+/* 1 lowest, 15 highest */
+/* The following devices can not individually specify the interrupt priority level for EEI0, TEI0, EEI2, TEI2. */
+/* EEI and TEI interrupts are grouped as the BL1 interrupt in the RX64M and RX71M group. */
+ #define RIIC_CFG_CH0_RXI_INT_PRIORITY (1U)
+ #define RIIC_CFG_CH0_TXI_INT_PRIORITY (1U)
+/* The priority level of the EEI, please do not lower than the priority level of TXI and RXI */
+ #define RIIC_CFG_CH0_EEI_INT_PRIORITY (1U)
+/* The priority level of the TEI, please do not lower than the priority level of TXI and RXI */
+ #define RIIC_CFG_CH0_TEI_INT_PRIORITY (1U)
+
+ #define RIIC_CFG_CH1_RXI_INT_PRIORITY (1U)
+ #define RIIC_CFG_CH1_TXI_INT_PRIORITY (1U)
+/* The priority level of the EEI, please do not lower than the priority level of TXI and RXI */
+ #define RIIC_CFG_CH1_EEI_INT_PRIORITY (1U)
+/* The priority level of the TEI, please do not lower than the priority level of TXI and RXI */
+ #define RIIC_CFG_CH1_TEI_INT_PRIORITY (1U)
+
+ #define RIIC_CFG_CH2_RXI_INT_PRIORITY (1U)
+ #define RIIC_CFG_CH2_TXI_INT_PRIORITY (1U)
+/* The priority level of the EEI, please do not lower than the priority level of TXI and RXI */
+ #define RIIC_CFG_CH2_EEI_INT_PRIORITY (1U)
+/* The priority level of the TEI, please do not lower than the priority level of TXI and RXI */
+ #define RIIC_CFG_CH2_TEI_INT_PRIORITY (1U)
+
+/* Select Timeout function enable or disable */
+/* 0 = disable, 1 = enable */
+ #define RIIC_CFG_CH0_TMO_ENABLE (1U)
+ #define RIIC_CFG_CH1_TMO_ENABLE (1U)
+ #define RIIC_CFG_CH2_TMO_ENABLE (1U)
+
+/* Select long mode or short mode for the timeout detection time */
+/* when the timeout function is enabled. */
+/* 0 = Long mode, 1 = short mode */
+ #define RIIC_CFG_CH0_TMO_DET_TIME (0U)
+ #define RIIC_CFG_CH1_TMO_DET_TIME (0U)
+ #define RIIC_CFG_CH2_TMO_DET_TIME (0U)
+
+/* Select enable or disable the internal counter of the timeout function to count up while the */
+/* SCL line is held LOW when the timeout function is enabled. */
+/* 0 = Count is disabled, 1 = Count is enabled */
+ #define RIIC_CFG_CH0_TMO_LCNT (1U)
+ #define RIIC_CFG_CH1_TMO_LCNT (1U)
+ #define RIIC_CFG_CH2_TMO_LCNT (1U)
+
+/* Select enable or disable the internal counter of the timeout function to count up while the */
+/* SCL line is held HIGH when the timeout function is enabled. */
+/* 0 = Count is disabled, 1 = Count is enabled */
+ #define RIIC_CFG_CH0_TMO_HCNT (1U)
+ #define RIIC_CFG_CH1_TMO_HCNT (1U)
+ #define RIIC_CFG_CH2_TMO_HCNT (1U)
+
+/* Define software bus busy check counter. */
+ #define RIIC_CFG_BUS_CHECK_COUNTER (1000U) /* Counter of checking bus busy */
+
+#endif /* RIIC_CONFIG_H */
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/FIT_modified_code/r_config/r_riic_rx_pin_config.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/FIT_modified_code/r_config/r_riic_rx_pin_config.h
new file mode 100644
index 00000000000..096aaf913b0
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/FIT_modified_code/r_config/r_riic_rx_pin_config.h
@@ -0,0 +1,69 @@
+/***********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+ * No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO
+ * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved.
+ **********************************************************************************************************************/
+/***********************************************************************************************************************
+ * File Name : r_riic_rx_pin_config_reference.h
+ * Description : Pin configures the RIIC drivers
+ **********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ * : 04.03.2016 1.90 First Release
+ * : 02.06.2017 2.10 Deleted RIIC port definitions of RIIC3.
+ **********************************************************************************************************************/
+/* Guards against multiple inclusion */
+#ifndef RIIC_PIN_CONFIG_H
+ #define RIIC_PIN_CONFIG_H
+/***********************************************************************************************************************
+ Configuration Options
+ **********************************************************************************************************************/
+/*------------------------------------------------------------------------------*/
+/* Set using port as riic port */
+/*------------------------------------------------------------------------------*/
+/* Set using port as riic port. */
+/* If you want to include the port configuration process(RIIC_CFG_PORT_SET_PROCESSING is "1"), */
+/* please choose which ports to use for the SCL/SDA of RIIC with the following setting. */
+/* Select the port group and pin used by setting
+ "R_RIIC_CFG_RIICx_SCLx_PORT (select from port group 0 to J)"
+ and "R_RIIC_CFG_RIICx_SCLx_BIT (select from pin number 0 to 7)"
+ and "R_RIIC_CFG_RIICx_SDAx_PORT (select from port group 0 to J)"
+ and "R_RIIC_CFG_RIICx_SDAx_BIT (select from pin number 0 to 7)",
+ respectively. */
+
+/* Select the ports (SCL0 and SDA0) to use in RIIC0 */
+ #define R_RIIC_CFG_RIIC0_SCL0_PORT '1' /* Port Number */
+ #define R_RIIC_CFG_RIIC0_SCL0_BIT '2' /* Bit Number */
+
+ #define R_RIIC_CFG_RIIC0_SDA0_PORT '1' /* Port Number */
+ #define R_RIIC_CFG_RIIC0_SDA0_BIT '3' /* Bit Number */
+
+/* Select the ports (SCL1 and SDA1) to use in RIIC1 */
+ #define R_RIIC_CFG_RIIC1_SCL1_PORT '2' /* Port Number */
+ #define R_RIIC_CFG_RIIC1_SCL1_BIT '1' /* Bit Number */
+
+ #define R_RIIC_CFG_RIIC1_SDA1_PORT '2' /* Port Number */
+ #define R_RIIC_CFG_RIIC1_SDA1_BIT '0' /* Bit Number */
+
+/* Select the ports (SCL2 and SDA2) to use in RIIC2 */
+ #define R_RIIC_CFG_RIIC2_SCL2_PORT '1' /* Port Number */
+ #define R_RIIC_CFG_RIIC2_SCL2_BIT '6' /* Bit Number */
+
+ #define R_RIIC_CFG_RIIC2_SDA2_PORT '1' /* Port Number */
+ #define R_RIIC_CFG_RIIC2_SDA2_BIT '7' /* Bit Number */
+
+#endif /* RIIC_PIN_CONFIG_H */
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/FIT_modified_code/r_config/r_sci_iic_rx_config.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/FIT_modified_code/r_config/r_sci_iic_rx_config.h
new file mode 100644
index 00000000000..b4d82ee2a3c
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/FIT_modified_code/r_config/r_sci_iic_rx_config.h
@@ -0,0 +1,190 @@
+/***********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+ * No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO
+ * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
+ **********************************************************************************************************************/
+/***********************************************************************************************************************
+ * File Name : r_sci_iic_rx_config.h
+ * Description : Configures the SCI IIC drivers
+ **********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ * : 01.07.2013 1.00 First Release
+ * : 30.09.2013 1.10 Change symbol of return value and status
+ * : 01.07.2014 1.20 RX110 support added.
+ * : 22.09.2014 1.30 RX64M support added.
+ * : 01.12.2014 1.40 RX113 support added.
+ * : 15.12.2014 1.50 RX71M support added.
+ * : 27.02.2015 1.60 RX63N support added.
+ * : 29.05.2015 1.70 RX231 support added.
+ * : 31.10.2015 1.80 RX130, RX230, RX23T support added.
+ * : 04.03.2016 1.90 RX24T support added.Changed about the pin definisions.
+ * : 01.10.2016 2.00 RX65N support added.
+ * : 31.08.2017 2.20 Changed the default value of the following macro definition.
+ * - SCI_IIC_CFG_CH1_INCLUDED
+ * RX24U,RX130-512 support added.
+ **********************************************************************************************************************/
+/* Guards against multiple inclusion */
+#ifndef SCI_IIC_CONFIG_H
+ #define SCI_IIC_CONFIG_H
+/***********************************************************************************************************************
+ Configuration Options
+ **********************************************************************************************************************/
+/* SPECIFY WHETHER TO INCLUDE CODE FOR API PARAMETER CHECKING */
+/* Setting to BSP_CFG_PARAM_CHECKING_ENABLE utilizes the system default setting */
+/* Setting to 1 includes parameter checking */
+/* 0 compiles out parameter checking */
+ #define SCI_IIC_CFG_PARAM_CHECKING_ENABLE (1)
+
+/* SPECIFY CHANNELS TO INCLUDE SOFTWARE SUPPORT FOR 1=included, 0=not */
+/* mcu supported channels */
+/* RX110 : , ch1, , , , ch5, , , , , , ,ch12 */
+/* RX111 : , ch1, , , , ch5, , , , , , ,ch12 */
+/* RX113 : ch0, ch1, ch2, , , ch5, ch6, , ch8, ch9, , ,ch12 */
+/* RX130 : ch0, ch1, , , , ch5, ch6, , ch8, ch9, , ,ch12 */
+/* RX230 : ch0, ch1, , , , ch5, ch6, , ch8, ch9, , ,ch12 */
+/* RX231 : ch0, ch1, , , , ch5, ch6, , ch8, ch9, , ,ch12 */
+/* RX23T : , ch1, , , , ch5, , , , , , , */
+/* RX24T : , ch1, , , , ch5, ch6, , , , , , */
+/* RX24U : , ch1, , , , ch5, ch6, , ch8, ch9, ,ch11, */
+/* RX63N : ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7, ch8, ch9,ch10,ch11,ch12 */
+/* RX64M : ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7, , , , ,ch12 */
+/* RX65N : ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7, ch8, ch9,ch10,ch11,ch12 */
+/* RX71M : ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7, , , , ,ch12 */
+/* Please change the definition value of channel to be used to '1'. */
+ #define SCI_IIC_CFG_CH0_INCLUDED (1)
+ #define SCI_IIC_CFG_CH1_INCLUDED (0)
+ #define SCI_IIC_CFG_CH2_INCLUDED (0)
+ #define SCI_IIC_CFG_CH3_INCLUDED (0)
+ #define SCI_IIC_CFG_CH4_INCLUDED (0)
+ #define SCI_IIC_CFG_CH5_INCLUDED (0)
+ #define SCI_IIC_CFG_CH6_INCLUDED (0)
+ #define SCI_IIC_CFG_CH7_INCLUDED (0)
+ #define SCI_IIC_CFG_CH8_INCLUDED (0)
+ #define SCI_IIC_CFG_CH9_INCLUDED (0)
+ #define SCI_IIC_CFG_CH10_INCLUDED (0)
+ #define SCI_IIC_CFG_CH11_INCLUDED (0)
+ #define SCI_IIC_CFG_CH12_INCLUDED (0)
+
+/* Set SCI IIC bps */
+/* 1K = 1000, 100K= 100000, Max:384k = 384000 */
+ #define SCI_IIC_CFG_CH0_BITRATE_BPS (384000)
+ #define SCI_IIC_CFG_CH1_BITRATE_BPS (384000)
+ #define SCI_IIC_CFG_CH2_BITRATE_BPS (384000)
+ #define SCI_IIC_CFG_CH3_BITRATE_BPS (384000)
+ #define SCI_IIC_CFG_CH4_BITRATE_BPS (384000)
+ #define SCI_IIC_CFG_CH5_BITRATE_BPS (384000)
+ #define SCI_IIC_CFG_CH6_BITRATE_BPS (384000)
+ #define SCI_IIC_CFG_CH7_BITRATE_BPS (384000)
+ #define SCI_IIC_CFG_CH8_BITRATE_BPS (384000)
+ #define SCI_IIC_CFG_CH9_BITRATE_BPS (384000)
+ #define SCI_IIC_CFG_CH10_BITRATE_BPS (384000)
+ #define SCI_IIC_CFG_CH11_BITRATE_BPS (384000)
+ #define SCI_IIC_CFG_CH12_BITRATE_BPS (384000)
+
+/* SET GROUP12 (RECEIVER ERROR) INTERRUPT PRIORITY; RX63N ONLY
+ This #define sets the priority level for the interrupt that handles
+ receiver overrun, framing, and parity errors for all SCI channels
+ on the RX63N. It is ignored for all other parts.
+ */
+/* 1 lowest, 15 highest */
+ #define SCI_IIC_CFG_CH0_INT_PRIORITY (2)
+ #define SCI_IIC_CFG_CH1_INT_PRIORITY (2)
+ #define SCI_IIC_CFG_CH2_INT_PRIORITY (2)
+ #define SCI_IIC_CFG_CH3_INT_PRIORITY (2)
+ #define SCI_IIC_CFG_CH4_INT_PRIORITY (2)
+ #define SCI_IIC_CFG_CH5_INT_PRIORITY (2)
+ #define SCI_IIC_CFG_CH6_INT_PRIORITY (2)
+ #define SCI_IIC_CFG_CH7_INT_PRIORITY (2)
+ #define SCI_IIC_CFG_CH8_INT_PRIORITY (2)
+ #define SCI_IIC_CFG_CH9_INT_PRIORITY (2)
+ #define SCI_IIC_CFG_CH10_INT_PRIORITY (2)
+ #define SCI_IIC_CFG_CH11_INT_PRIORITY (2)
+ #define SCI_IIC_CFG_CH12_INT_PRIORITY (2)
+
+/* Digital noise filter (NFEN bit).
+ 0 = Noise cancellation function for the SSCLn and SSDAn input signals is disabled.
+ 1 = Noise cancellation function for the SSCLn and SSDAn input signals is enable.
+ */
+ #define SCI_IIC_CFG_CH0_DIGITAL_FILTER (1)
+ #define SCI_IIC_CFG_CH1_DIGITAL_FILTER (1)
+ #define SCI_IIC_CFG_CH2_DIGITAL_FILTER (1)
+ #define SCI_IIC_CFG_CH3_DIGITAL_FILTER (1)
+ #define SCI_IIC_CFG_CH4_DIGITAL_FILTER (1)
+ #define SCI_IIC_CFG_CH5_DIGITAL_FILTER (1)
+ #define SCI_IIC_CFG_CH6_DIGITAL_FILTER (1)
+ #define SCI_IIC_CFG_CH7_DIGITAL_FILTER (1)
+ #define SCI_IIC_CFG_CH8_DIGITAL_FILTER (1)
+ #define SCI_IIC_CFG_CH9_DIGITAL_FILTER (1)
+ #define SCI_IIC_CFG_CH10_DIGITAL_FILTER (1)
+ #define SCI_IIC_CFG_CH11_DIGITAL_FILTER (1)
+ #define SCI_IIC_CFG_CH12_DIGITAL_FILTER (1)
+
+/* Noise Filter Setting Register (NFCS bit).
+ 001 = 1 = The clock signal divided by 1 is used with the noise filter.
+ 010 = 2 = The clock signal divided by 2 is used with the noise filter.
+ 011 = 3 = The clock signal divided by 4 is used with the noise filter.
+ 100 = 4 = The clock signal divided by 8 is used with the noise filter.
+ */
+ #define SCI_IIC_CFG_CH0_FILTER_CLOCK (1)
+ #define SCI_IIC_CFG_CH1_FILTER_CLOCK (1)
+ #define SCI_IIC_CFG_CH2_FILTER_CLOCK (1)
+ #define SCI_IIC_CFG_CH3_FILTER_CLOCK (1)
+ #define SCI_IIC_CFG_CH4_FILTER_CLOCK (1)
+ #define SCI_IIC_CFG_CH5_FILTER_CLOCK (1)
+ #define SCI_IIC_CFG_CH6_FILTER_CLOCK (1)
+ #define SCI_IIC_CFG_CH7_FILTER_CLOCK (1)
+ #define SCI_IIC_CFG_CH8_FILTER_CLOCK (1)
+ #define SCI_IIC_CFG_CH9_FILTER_CLOCK (1)
+ #define SCI_IIC_CFG_CH10_FILTER_CLOCK (1)
+ #define SCI_IIC_CFG_CH11_FILTER_CLOCK (1)
+ #define SCI_IIC_CFG_CH12_FILTER_CLOCK (1)
+
+/* I2C Mode Register 1 (IICDL bit).
+ 00001 = 1 = 0 to 1 cycle
+ 00010 = 2 = 1 to 2 cycles
+ 00011 = 3 = 2 to 3 cycles
+ 00100 = 4 = 3 to 4 cycles
+ 00101 = 5 = 4 to 5 cycles
+ |
+ 11110 = 30 = 29 to 30 cycles
+ 11111 = 31 = 30 to 31 cycles
+ */
+ #define SCI_IIC_CFG_CH0_SSDA_DELAY_SELECT (18)
+ #define SCI_IIC_CFG_CH1_SSDA_DELAY_SELECT (18)
+ #define SCI_IIC_CFG_CH2_SSDA_DELAY_SELECT (18)
+ #define SCI_IIC_CFG_CH3_SSDA_DELAY_SELECT (18)
+ #define SCI_IIC_CFG_CH4_SSDA_DELAY_SELECT (18)
+ #define SCI_IIC_CFG_CH5_SSDA_DELAY_SELECT (18)
+ #define SCI_IIC_CFG_CH6_SSDA_DELAY_SELECT (18)
+ #define SCI_IIC_CFG_CH7_SSDA_DELAY_SELECT (18)
+ #define SCI_IIC_CFG_CH8_SSDA_DELAY_SELECT (18)
+ #define SCI_IIC_CFG_CH9_SSDA_DELAY_SELECT (18)
+ #define SCI_IIC_CFG_CH10_SSDA_DELAY_SELECT (18)
+ #define SCI_IIC_CFG_CH11_SSDA_DELAY_SELECT (18)
+ #define SCI_IIC_CFG_CH12_SSDA_DELAY_SELECT (18)
+
+/* Define software bus busy check counter. */
+ #define SCI_IIC_CFG_BUS_CHECK_COUNTER (1000)
+
+/* Setting to port.
+ 1 = includes sci (simple iic)port setting processing
+ 0 = compiles out sci (simple iic)port setting processing
+ */
+ #define SCI_IIC_CFG_PORT_SETTING_PROCESSING (1)
+
+#endif /* SCI_IIC_CONFIG_H */
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/FIT_modified_code/r_config/r_sci_iic_rx_pin_config.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/FIT_modified_code/r_config/r_sci_iic_rx_pin_config.h
new file mode 100644
index 00000000000..afa717e46f5
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/FIT_modified_code/r_config/r_sci_iic_rx_pin_config.h
@@ -0,0 +1,144 @@
+/***********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+ * No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO
+ * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved.
+ **********************************************************************************************************************/
+/***********************************************************************************************************************
+ * File Name : r_sci_iic_rx_pin_config_reference.h
+ * Description : Pin configures the SCI IIC drivers
+ **********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ * : 04.03.2016 1.90 First Release
+ * : 31.08.2017 2.20 Changed default value of macro definitions, below.
+ * : - R_SCI_IIC_CFG_SCI2_SSCL2_PORT
+ * : - R_SCI_IIC_CFG_SCI2_SSDA2_PORT, R_SCI_IIC_CFG_SCI2_SSDA2_BIT
+ * : - R_SCI_IIC_CFG_SCI3_SSCL3_PORT, R_SCI_IIC_CFG_SCI3_SSCL3_BIT
+ * : - R_SCI_IIC_CFG_SCI3_SSDA3_PORT, R_SCI_IIC_CFG_SCI3_SSDA3_BIT
+ * : - R_SCI_IIC_CFG_SCI5_SSCL5_PORT, R_SCI_IIC_CFG_SCI5_SSCL5_BIT
+ * : - R_SCI_IIC_CFG_SCI5_SSDA5_PORT, R_SCI_IIC_CFG_SCI5_SSDA5_BIT
+ * : - R_SCI_IIC_CFG_SCI6_SSCL6_BIT
+ * : - R_SCI_IIC_CFG_SCI6_SSDA6_BIT
+ **********************************************************************************************************************/
+/* Guards against multiple inclusion */
+#ifndef SCI_IIC_PIN_CONFIG_H
+ #define SCI_IIC_PIN_CONFIG_H
+/***********************************************************************************************************************
+ Configuration Options
+ **********************************************************************************************************************/
+/*------------------------------------------------------------------------------*/
+/* Set using port as sci iic port */
+/*------------------------------------------------------------------------------*/
+/* Select the port group and pin used by setting
+ "R_SCI_IIC_CFG_SCIx_SSCLx_PORT (select from port group 0 to J)"
+ and "R_SCI_IIC_CFG_SCIx_SSCLx_BIT (select from pin number 0 to 7)"
+ and "R_SCI_IIC_CFG_SCIx_SSDAx_PORT (select from port group 0 to J)"
+ and "R_SCI_IIC_CFG_SCIx_SSDAx_BIT (select from pin number 0 to 7)",
+ respectively. */
+
+/* Select the ports (SSCL0 and SSDA0) to use in SCI0 */
+ #define R_SCI_IIC_CFG_SCI0_SSCL0_PORT '2' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI0_SSCL0_BIT '1' /* Bit Number */
+
+ #define R_SCI_IIC_CFG_SCI0_SSDA0_PORT '2' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI0_SSDA0_BIT '0' /* Bit Number */
+
+/* Select the ports (SSCL1 and SSDA1) to use in SCI1 */
+ #define R_SCI_IIC_CFG_SCI1_SSCL1_PORT '1' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI1_SSCL1_BIT '5' /* Bit Number */
+
+ #define R_SCI_IIC_CFG_SCI1_SSDA1_PORT '1' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI1_SSDA1_BIT '6' /* Bit Number */
+
+/* Select the ports (SSCL2 and SSDA2) to use in SCI2 */
+ #define R_SCI_IIC_CFG_SCI2_SSCL2_PORT '1' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI2_SSCL2_BIT '2' /* Bit Number */
+
+ #define R_SCI_IIC_CFG_SCI2_SSDA2_PORT '1' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI2_SSDA2_BIT '3' /* Bit Number */
+
+/* Select the ports (SSCL3 and SSDA3) to use in SCI3 */
+ #define R_SCI_IIC_CFG_SCI3_SSCL3_PORT '1' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI3_SSCL3_BIT '6' /* Bit Number */
+
+ #define R_SCI_IIC_CFG_SCI3_SSDA3_PORT '1' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI3_SSDA3_BIT '7' /* Bit Number */
+
+/* Select the ports (SSCL4 and SSDA4) to use in SCI4 */
+ #define R_SCI_IIC_CFG_SCI4_SSCL4_PORT 'B' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI4_SSCL4_BIT '0' /* Bit Number */
+
+ #define R_SCI_IIC_CFG_SCI4_SSDA4_PORT 'B' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI4_SSDA4_BIT '1' /* Bit Number */
+
+/* Select the ports (SSCL5 and SSDA5) to use in SCI5 */
+ #define R_SCI_IIC_CFG_SCI5_SSCL5_PORT 'B' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI5_SSCL5_BIT '1' /* Bit Number */
+
+ #define R_SCI_IIC_CFG_SCI5_SSDA5_PORT 'B' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI5_SSDA5_BIT '2' /* Bit Number */
+
+/* Select the ports (SSCL6 and SSDA6) to use in SCI6 */
+ #define R_SCI_IIC_CFG_SCI6_SSCL6_PORT 'B' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI6_SSCL6_BIT '1' /* Bit Number */
+
+ #define R_SCI_IIC_CFG_SCI6_SSDA6_PORT 'B' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI6_SSDA6_BIT '2' /* Bit Number */
+
+/* Select the ports (SSCL7 and SSDA7) to use in SCI7 */
+ #define R_SCI_IIC_CFG_SCI7_SSCL7_PORT '9' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI7_SSCL7_BIT '2' /* Bit Number */
+
+ #define R_SCI_IIC_CFG_SCI7_SSDA7_PORT '9' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI7_SSDA7_BIT '0' /* Bit Number */
+
+/* Select the ports (SSCL8 and SSDA8) to use in SCI8 */
+ #define R_SCI_IIC_CFG_SCI8_SSCL8_PORT 'C' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI8_SSCL8_BIT '6' /* Bit Number */
+
+ #define R_SCI_IIC_CFG_SCI8_SSDA8_PORT 'C' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI8_SSDA8_BIT '7' /* Bit Number */
+
+/* Select the ports (SSCL9 and SSDA9) to use in SCI9 */
+ #define R_SCI_IIC_CFG_SCI9_SSCL9_PORT 'B' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI9_SSCL9_BIT '6' /* Bit Number */
+
+ #define R_SCI_IIC_CFG_SCI9_SSDA9_PORT 'B' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI9_SSDA9_BIT '7' /* Bit Number */
+
+/* Select the ports (SSCL10 and SSDA10) to use in SCI10 */
+ #define R_SCI_IIC_CFG_SCI10_SSCL10_PORT '8' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI10_SSCL10_BIT '1' /* Bit Number */
+
+ #define R_SCI_IIC_CFG_SCI10_SSDA10_PORT '8' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI10_SSDA10_BIT '2' /* Bit Number */
+
+/* Select the ports (SSCL11 and SSDA11) to use in SCI11 */
+ #define R_SCI_IIC_CFG_SCI11_SSCL11_PORT '7' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI11_SSCL11_BIT '6' /* Bit Number */
+
+ #define R_SCI_IIC_CFG_SCI11_SSDA11_PORT '7' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI11_SSDA11_BIT '7' /* Bit Number */
+
+/* Select the ports (SSCL12 and SSDA12) to use in SCI12 */
+ #define R_SCI_IIC_CFG_SCI12_SSCL12_PORT 'E' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI12_SSCL12_BIT '2' /* Bit Number */
+
+ #define R_SCI_IIC_CFG_SCI12_SSDA12_PORT 'E' /* Port Number */
+ #define R_SCI_IIC_CFG_SCI12_SSDA12_BIT '1' /* Bit Number */
+
+#endif /* SCI_IIC_PIN_CONFIG_H */
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/FIT_modified_code/r_config/r_sci_rx_config.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/FIT_modified_code/r_config/r_sci_rx_config.h
new file mode 100644
index 00000000000..11bf22a292b
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/FIT_modified_code/r_config/r_sci_rx_config.h
@@ -0,0 +1,171 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2013-2017 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : r_sci_rx_config.h
+* Description : Configures the SCI driver
+************************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* 25.09.2013 1.00 Initial Release
+* 17.04.2014 1.20 Added comments for new RX110 support.
+* 02.07.2014 1.30 Fixed bug that caused Group12 rx errors to only be enabled for channel 2.
+* 25.11.2014 1.40 Added comments for RX113 support
+* 30.09.2015 1.70 Added comments for RX23T support
+* 01.10.2016 1.80 Added support for RX65N (comments and TX/RX FIFO THRESHOLD options)
+* 19.12.2016 1.90 Added comments for RX24U support
+* 07.03.2017 2.00 Added comments for RX130-512KB support
+***********************************************************************************************************************/
+#ifndef SCI_CONFIG_H
+#define SCI_CONFIG_H
+
+#include "platform.h"
+
+/***********************************************************************************************************************
+Configuration Options
+***********************************************************************************************************************/
+
+/* SPECIFY WHETHER TO INCLUDE CODE FOR API PARAMETER CHECKING */
+/* Setting to BSP_CFG_PARAM_CHECKING_ENABLE utilizes the system default setting */
+/* Setting to 1 includes parameter checking; 0 compiles out parameter checking */
+#define SCI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+
+/* SPECIFY WHETHER TO INCLUDE CODE FOR DIFFERENT SCI MODES */
+/* Setting an equate to 1 includes code specific to that mode. */
+#define SCI_CFG_ASYNC_INCLUDED (1)
+#define SCI_CFG_SYNC_INCLUDED (0)
+#define SCI_CFG_SSPI_INCLUDED (0)
+
+/* SPECIFY BYTE VALUE TO TRANSMIT WHILE CLOCKING IN DATA IN SSPI MODES */
+#define SCI_CFG_DUMMY_TX_BYTE (0xFF)
+
+/* SPECIFY CHANNELS TO INCLUDE SOFTWARE SUPPORT FOR 1=included, 0=not */
+/*
+ * NOTE: If using ASYNC mode, adjust BYTEQ_CFG_MAX_CTRL_BLKS in r_byteq_config.h
+ * to provide 2 queues per channel (static mode only).
+ * * = port connector RDKRX63N, RSKRX210, RSKRX11x
+ * u = channel used by the USB-UART port (G1CUSB0)
+ * a = this channel is used only for RX130-512KB
+ * RX MCU supported channels
+ *
+ * CH# 110 111 113 130 210 230 231 23T 24T 24U 63N 631 64M 71M 65N
+ * --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- ---
+ * CH0 X Xa X* X X X* X X X X
+ * CH1 X X* X* Xu X X X Xu Xu Xu X X X X X
+ * CH2 X X X X X Xu
+ * CH3 X X X X X
+ * CH4 X X X X X
+ * CH5 X X X X X X Xu X X X X X X X X
+ * CH6 X X X X X X X X X X X X
+ * CH7 X X Xu Xu X
+ * CH8 X Xa X X X X X X X
+ * CH9 X Xa X X X X X X X
+ * CH10 X X X
+ * CH11 X X X X
+ * CH12 X X X X X X X X X X X X
+*/
+
+#define SCI_CFG_CH0_INCLUDED (0)
+#define SCI_CFG_CH1_INCLUDED (0)
+#define SCI_CFG_CH2_INCLUDED (1)
+#define SCI_CFG_CH3_INCLUDED (0)
+#define SCI_CFG_CH4_INCLUDED (0)
+#define SCI_CFG_CH5_INCLUDED (0)
+#define SCI_CFG_CH6_INCLUDED (1)
+#define SCI_CFG_CH7_INCLUDED (0)
+#define SCI_CFG_CH8_INCLUDED (1)
+#define SCI_CFG_CH9_INCLUDED (0)
+#define SCI_CFG_CH10_INCLUDED (0)
+#define SCI_CFG_CH11_INCLUDED (0)
+#define SCI_CFG_CH12_INCLUDED (0)
+
+/* SPECIFY ASYNC MODE TX QUEUE BUFFER SIZES (will not allocate if chan not enabled */
+#define SCI_CFG_CH0_TX_BUFSIZ (80)
+#define SCI_CFG_CH1_TX_BUFSIZ (80)
+#define SCI_CFG_CH2_TX_BUFSIZ (1000)
+#define SCI_CFG_CH3_TX_BUFSIZ (80)
+#define SCI_CFG_CH4_TX_BUFSIZ (80)
+#define SCI_CFG_CH5_TX_BUFSIZ (80)
+#define SCI_CFG_CH6_TX_BUFSIZ (1460)
+#define SCI_CFG_CH7_TX_BUFSIZ (80)
+#define SCI_CFG_CH8_TX_BUFSIZ (80)
+#define SCI_CFG_CH9_TX_BUFSIZ (80)
+#define SCI_CFG_CH10_TX_BUFSIZ (80)
+#define SCI_CFG_CH11_TX_BUFSIZ (80)
+#define SCI_CFG_CH12_TX_BUFSIZ (80)
+
+/* SPECIFY ASYNC MODE RX QUEUE BUFFER SIZES (will not allocate if chan not enabled */
+#define SCI_CFG_CH0_RX_BUFSIZ (80)
+#define SCI_CFG_CH1_RX_BUFSIZ (80)
+#define SCI_CFG_CH2_RX_BUFSIZ (1000)
+#define SCI_CFG_CH3_RX_BUFSIZ (80)
+#define SCI_CFG_CH4_RX_BUFSIZ (80)
+#define SCI_CFG_CH5_RX_BUFSIZ (80)
+#define SCI_CFG_CH6_RX_BUFSIZ (2048)
+#define SCI_CFG_CH7_RX_BUFSIZ (80)
+#define SCI_CFG_CH8_RX_BUFSIZ (80)
+#define SCI_CFG_CH9_RX_BUFSIZ (80)
+#define SCI_CFG_CH10_RX_BUFSIZ (80)
+#define SCI_CFG_CH11_RX_BUFSIZ (80)
+#define SCI_CFG_CH12_RX_BUFSIZ (80)
+
+/*
+* ENABLE TRANSMIT END INTERRUPT (ASYNCHRONOUS)
+* This interrupt only occurs when the last bit of the last byte of data
+* has been sent and the transmitter has become idle. The interrupt calls
+* the user's callback function specified in R_SCI_Open() and passes it an
+* SCI_EVT_TEI event. A typical use of this feature is to disable an external
+* transceiver to save power. It would then be up to the user's code to
+* re-enable the transceiver before sending again. Not including this feature
+* reduces code space used by the interrupt. Note that this equate is only
+* for including the TEI code. The interrupt itself must be enabled using an
+* R_SCI_Control(hdl, SCI_CMD_EN_TEI, NULL) call.
+*/
+#define SCI_CFG_TEI_INCLUDED (1) /* 1=included, 0=not */
+
+/*
+* SET GROUP12 (RECEIVER ERROR) INTERRUPT PRIORITY; RX63N/631 ONLY
+* This #define sets the priority level for the interrupt that handles
+* receiver overrun, framing, and parity errors for all SCI channels
+* on the RX63N/631. It is ignored for all other parts.
+*/
+#define SCI_CFG_RXERR_PRIORITY (3) /* (RX63N/631 ONLY) 1 lowest, 15 highest */
+
+/*
+* SET GROUPBL0 (ERI, TEI) INTERRUPT PRIORITY; RX64M/RX71M/RX65N ONLY
+* SET GROUPBL1, GROUPAL0 (ERI,TEI) INTERRUPT PRIORITY; RX65N ONLY
+* This sets the priority level for receiver overrun, framing, and parity errors
+* as well as TEI interrupts for all SCI channels.
+*/
+#define SCI_CFG_ERI_TEI_PRIORITY (3) /* (RX64M/RX71M/RX65N ONLY) 1 lowest, 15 highest */
+
+/* ENABLE TX/RX FIFO; (SCIi supported MCU ONLY) 1=included, 0=not */
+#define SCI_CFG_CH10_FIFO_INCLUDED (0)
+#define SCI_CFG_CH11_FIFO_INCLUDED (0)
+
+/* SET TX FIFO THRESHOLD; (SCIi supported MCU ONLY) 0 lowest, 15 highest */
+/* TX FIFO THRESHOLD is invalid in Clock Synchronous Mode and Simple SPI Mode. */
+/* Set the same value for TX FIFO THRESHOLD and RX FIFO THRESHOLD in Clock Synchronous Mode and Simple SPI Mode. */
+#define SCI_CFG_CH10_TX_FIFO_THRESH (8)
+#define SCI_CFG_CH11_TX_FIFO_THRESH (8)
+
+/* SET RX FIFO THRESHOLD; (SCIi supported MCU ONLY) 1 lowest, 15 highest */
+#define SCI_CFG_CH10_RX_FIFO_THRESH (8)
+#define SCI_CFG_CH11_RX_FIFO_THRESH (8)
+
+
+#endif /* SCI_CONFIG_H */
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/FIT_modified_code/r_pincfg/r_pinset.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/FIT_modified_code/r_pincfg/r_pinset.h
new file mode 100644
index 00000000000..fc669bdb499
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/FIT_modified_code/r_pincfg/r_pinset.h
@@ -0,0 +1,34 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2018 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : r_pinset.h.h
+* Version : 1.0.1
+* Description : Declares all pin code headers into a single file
+* Creation Date: 2018-08-29
+***********************************************************************************************************************/
+
+#ifndef R_PINSET_H
+#define R_PINSET_H
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_sci_rx_pinset.h"
+
+#endif /* R_PINSET_H */
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/FIT_modified_code/r_pincfg/r_sci_rx_pinset.c b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/FIT_modified_code/r_pincfg/r_sci_rx_pinset.c
new file mode 100644
index 00000000000..0b9c987cfc2
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/FIT_modified_code/r_pincfg/r_sci_rx_pinset.c
@@ -0,0 +1,79 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2018 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : r_sci_rx_pinset.c
+* Version : 1.0.2
+* Device(s) : R5F565NEDxFP
+* Tool-Chain : RXC toolchain
+* Description : Setting of port and mpc registers
+* Creation Date: 2018-08-29
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_sci_rx_pinset.h"
+#include "platform.h"
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* Function Name: R_SCI_PinSet_SCI6
+* Description : This function initializes pins for r_sci_rx module
+* Arguments : none
+* Return Value : none
+***********************************************************************************************************************/
+void R_SCI_PinSet_SCI6()
+{
+ R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_MPC);
+
+ /* Set RXD6/SMISO6 pin */
+ MPC.P33PFS.BYTE = 0x0AU;
+ PORT3.PMR.BIT.B3 = 1U;
+
+ /* Set TXD6/SMOSI6 pin */
+ MPC.P32PFS.BYTE = 0x0AU;
+ PORT3.PMR.BIT.B2 = 1U;
+
+ R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_MPC);
+}
+
+/***********************************************************************************************************************
+* Function Name: R_SCI_PinSet_SCI12
+* Description : This function initializes pins for r_sci_rx module
+* Arguments : none
+* Return Value : none
+***********************************************************************************************************************/
+void R_SCI_PinSet_SCI12()
+{
+ R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_MPC);
+
+ /* Set RXD12/SMISO12 pin */
+ MPC.PE2PFS.BYTE = 0x0CU;
+ PORTE.PMR.BIT.B2 = 1U;
+
+ /* Set TXD12/SMOSI12 pin */
+ MPC.PE1PFS.BYTE = 0x0CU;
+ PORTE.PMR.BIT.B1 = 1U;
+
+ R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_MPC);
+}
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/FIT_modified_code/r_pincfg/r_sci_rx_pinset.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/FIT_modified_code/r_pincfg/r_sci_rx_pinset.h
new file mode 100644
index 00000000000..59b1cd9cd0e
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/FIT_modified_code/r_pincfg/r_sci_rx_pinset.h
@@ -0,0 +1,42 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2018 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : r_sci_rx_pinset.h
+* Version : 1.0.2
+* Device(s) : R5F565NEDxFP
+* Tool-Chain : RXC toolchain
+* Description : Setting of port and mpc registers
+* Creation Date: 2018-08-29
+***********************************************************************************************************************/
+
+#ifndef R_SCI_RX_H
+#define R_SCI_RX_H
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+
+void R_SCI_PinSet_SCI6();
+void R_SCI_PinSet_SCI12();
+
+#endif
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/compiler_support/attention!.txt b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/compiler_support/attention!.txt
new file mode 100644
index 00000000000..eba837b820a
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/compiler_support/attention!.txt
@@ -0,0 +1,39 @@
+Please note that the following folders in the project window of IDEs are
+so called 'linked' folders.
+
+--------------------------------------------
+Linked folders in the project window of IDEs
+--------------------------------------------
+
+src/compiler_support
+src/FIT_modified_code/r_bsp
+
+src/FIT_modified_code/r_byteq
+src/FIT_modified_code/r_cmt_rx
+src/FIT_modified_code/r_ether_rx
+src/FIT_modified_code/r_flash_rx
+src/FIT_modified_code/r_sci_rx
+
+----------------------------------------------------------
+Folders on the File System of the WINDOWS Operating System
+----------------------------------------------------------
+
+CC-RX/e2 studio & CC-RX/CS+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/ccrx/compiler_support
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/ccrx/generic_rx65n/r_bsp
+
+GNURX/e2 studio
+~~~~~~~~~~~~~~~
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/gnurx/compiler_support
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/gnurx/generic_rx65n/r_bsp
+
+All
+~~~
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/r_byteq
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/r_cmt_rx
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/r_ether_rx
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/r_flash_rx
+amazon-freertos/lib/third_party/mcu_vendor/renesas/FIT/RDP_v1.15_modified/r_sci_rx
+
+[EOF]
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/linker_script.ld b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/linker_script.ld
new file mode 100644
index 00000000000..3541c2661f3
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/linker_script.ld
@@ -0,0 +1,153 @@
+MEMORY
+{
+ RAM : ORIGIN = 0x0, LENGTH = 655360
+ ROM : ORIGIN = 0xFFF00000, LENGTH = 1048576
+ OFS : ORIGIN = 0xFE7F5D00, LENGTH = 256
+}
+SECTIONS
+{
+ .exvectors 0xFFFFFF80 : AT(0xFFFFFF80)
+ {
+ KEEP(*(.exvectors))
+ } >ROM
+ .fvectors 0xFFFFFFFC : AT(0xFFFFFFFC)
+ {
+ KEEP(*(.fvectors))
+ } >ROM
+ .text 0xFFF00000 : AT(0xFFF00000)
+ {
+ *(.text)
+ *(.text.*)
+ *(P)
+ etext = .;
+ } >ROM
+ .rvectors :
+ {
+ _rvectors_start = .;
+ INCLUDE ../src/linker_script_rvectors.inc
+ _rvectors_end = .;
+ } >ROM
+ .init :
+ {
+ KEEP(*(.init))
+ __preinit_array_start = .;
+ KEEP(*(.preinit_array))
+ __preinit_array_end = .;
+ __init_array_start = (. + 3) & ~ 3;
+ KEEP(*(.init_array))
+ KEEP(*(SORT(.init_array.*)))
+ __init_array_end = .;
+ __fini_array_start = .;
+ KEEP(*(.fini_array))
+ KEEP(*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+ } >ROM
+ .fini :
+ {
+ KEEP(*(.fini))
+ } >ROM
+ .got :
+ {
+ *(.got)
+ *(.got.plt)
+ } >ROM
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata.*)
+ *(C_1)
+ *(C_2)
+ *(C)
+ _erodata = .;
+ } >ROM
+ .eh_frame_hdr :
+ {
+ *(.eh_frame_hdr)
+ } >ROM
+ .eh_frame :
+ {
+ *(.eh_frame)
+ } >ROM
+ .jcr :
+ {
+ *(.jcr)
+ } >ROM
+ .tors :
+ {
+ __CTOR_LIST__ = .;
+ . = ALIGN(2);
+ ___ctors = .;
+ *(.ctors)
+ ___ctors_end = .;
+ __CTOR_END__ = .;
+ __DTOR_LIST__ = .;
+ ___dtors = .;
+ *(.dtors)
+ ___dtors_end = .;
+ __DTOR_END__ = .;
+ . = ALIGN(2);
+ _mdata = .;
+ } >ROM
+ .ustack 0x3000 : AT(0x3000)
+ {
+ _ustack = .;
+ } >RAM
+ .istack 0x6000 : AT(0x6000)
+ {
+ _istack = .;
+ } >RAM
+ .data 0x9004 : AT(_mdata)
+ {
+ _data = .;
+ *(.data)
+ *(.data.*)
+ *(D)
+ *(D_1)
+ *(D_2)
+ _edata = .;
+ } >RAM
+ .gcc_exc :
+ {
+ *(.gcc_exc)
+ } >RAM
+ .bss :
+ {
+ _bss = .;
+ *(.bss)
+ *(.bss.**)
+ *(COMMON)
+ *(B)
+ *(B_1)
+ *(B_2)
+ _ebss = .;
+ _end = .;
+ } >RAM
+ .ofs1 0xFE7F5D40 : AT(0xFE7F5D00)
+ {
+ KEEP(*(.ofs1))
+ } >OFS
+ .ofs2 0xFE7F5D48 : AT(0xFE7F5D10)
+ {
+ KEEP(*(.ofs2))
+ } >OFS
+ .ofs3 0xFE7F5D50 : AT(0xFE7F5D40)
+ {
+ KEEP(*(.ofs3))
+ } >OFS
+ .ofs4 0xFE7F5D10 : AT(0xFE7F5D48)
+ {
+ KEEP(*(.ofs4))
+ } >OFS
+ .ofs5 0xFE7F5D10 : AT(0xFE7F5D50)
+ {
+ KEEP(*(.ofs5))
+ } >OFS
+ .ofs6 0xFE7F5D10 : AT(0xFE7F5D64)
+ {
+ KEEP(*(.ofs6))
+ } >OFS
+ .ofs7 0xFE7F5D10 : AT(0xFE7F5D70)
+ {
+ KEEP(*(.ofs7))
+ } >OFS
+}
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/linker_script_rvectors.inc b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/linker_script_rvectors.inc
new file mode 100644
index 00000000000..818dda33da0
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/linker_script_rvectors.inc
@@ -0,0 +1,256 @@
+ LONG(DEFINED($tableentry$0$.rvectors) ? $tableentry$0$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$1$.rvectors) ? $tableentry$1$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$2$.rvectors) ? $tableentry$2$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$3$.rvectors) ? $tableentry$3$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$4$.rvectors) ? $tableentry$4$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$5$.rvectors) ? $tableentry$5$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$6$.rvectors) ? $tableentry$6$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$7$.rvectors) ? $tableentry$7$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$8$.rvectors) ? $tableentry$8$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$9$.rvectors) ? $tableentry$9$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$10$.rvectors) ? $tableentry$10$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$11$.rvectors) ? $tableentry$11$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$12$.rvectors) ? $tableentry$12$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$13$.rvectors) ? $tableentry$13$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$14$.rvectors) ? $tableentry$14$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$15$.rvectors) ? $tableentry$15$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$16$.rvectors) ? $tableentry$16$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$17$.rvectors) ? $tableentry$17$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$18$.rvectors) ? $tableentry$18$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$19$.rvectors) ? $tableentry$19$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$20$.rvectors) ? $tableentry$20$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$21$.rvectors) ? $tableentry$21$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$22$.rvectors) ? $tableentry$22$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$23$.rvectors) ? $tableentry$23$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$24$.rvectors) ? $tableentry$24$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$25$.rvectors) ? $tableentry$25$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$26$.rvectors) ? $tableentry$26$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$27$.rvectors) ? $tableentry$27$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$28$.rvectors) ? $tableentry$28$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$29$.rvectors) ? $tableentry$29$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$30$.rvectors) ? $tableentry$30$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$31$.rvectors) ? $tableentry$31$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$32$.rvectors) ? $tableentry$32$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$33$.rvectors) ? $tableentry$33$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$34$.rvectors) ? $tableentry$34$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$35$.rvectors) ? $tableentry$35$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$36$.rvectors) ? $tableentry$36$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$37$.rvectors) ? $tableentry$37$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$38$.rvectors) ? $tableentry$38$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$39$.rvectors) ? $tableentry$39$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$40$.rvectors) ? $tableentry$40$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$41$.rvectors) ? $tableentry$41$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$42$.rvectors) ? $tableentry$42$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$43$.rvectors) ? $tableentry$43$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$44$.rvectors) ? $tableentry$44$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$45$.rvectors) ? $tableentry$45$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$46$.rvectors) ? $tableentry$46$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$47$.rvectors) ? $tableentry$47$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$48$.rvectors) ? $tableentry$48$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$49$.rvectors) ? $tableentry$49$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$50$.rvectors) ? $tableentry$50$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$51$.rvectors) ? $tableentry$51$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$52$.rvectors) ? $tableentry$52$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$53$.rvectors) ? $tableentry$53$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$54$.rvectors) ? $tableentry$54$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$55$.rvectors) ? $tableentry$55$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$56$.rvectors) ? $tableentry$56$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$57$.rvectors) ? $tableentry$57$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$58$.rvectors) ? $tableentry$58$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$59$.rvectors) ? $tableentry$59$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$60$.rvectors) ? $tableentry$60$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$61$.rvectors) ? $tableentry$61$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$62$.rvectors) ? $tableentry$62$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$63$.rvectors) ? $tableentry$63$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$64$.rvectors) ? $tableentry$64$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$65$.rvectors) ? $tableentry$65$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$66$.rvectors) ? $tableentry$66$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$67$.rvectors) ? $tableentry$67$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$68$.rvectors) ? $tableentry$68$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$69$.rvectors) ? $tableentry$69$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$70$.rvectors) ? $tableentry$70$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$71$.rvectors) ? $tableentry$71$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$72$.rvectors) ? $tableentry$72$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$73$.rvectors) ? $tableentry$73$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$74$.rvectors) ? $tableentry$74$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$75$.rvectors) ? $tableentry$75$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$76$.rvectors) ? $tableentry$76$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$77$.rvectors) ? $tableentry$77$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
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+ LONG(DEFINED($tableentry$79$.rvectors) ? $tableentry$79$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
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+ LONG(DEFINED($tableentry$86$.rvectors) ? $tableentry$86$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
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+ LONG(DEFINED($tableentry$112$.rvectors) ? $tableentry$112$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
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+ LONG(DEFINED($tableentry$116$.rvectors) ? $tableentry$116$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
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+ LONG(DEFINED($tableentry$118$.rvectors) ? $tableentry$118$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$119$.rvectors) ? $tableentry$119$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$120$.rvectors) ? $tableentry$120$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$121$.rvectors) ? $tableentry$121$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$122$.rvectors) ? $tableentry$122$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$123$.rvectors) ? $tableentry$123$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$124$.rvectors) ? $tableentry$124$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$125$.rvectors) ? $tableentry$125$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$126$.rvectors) ? $tableentry$126$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
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+ LONG(DEFINED($tableentry$130$.rvectors) ? $tableentry$130$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$131$.rvectors) ? $tableentry$131$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
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+ LONG(DEFINED($tableentry$151$.rvectors) ? $tableentry$151$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$152$.rvectors) ? $tableentry$152$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
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+ LONG(DEFINED($tableentry$154$.rvectors) ? $tableentry$154$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
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+ LONG(DEFINED($tableentry$167$.rvectors) ? $tableentry$167$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
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+ LONG(DEFINED($tableentry$171$.rvectors) ? $tableentry$171$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$172$.rvectors) ? $tableentry$172$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
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+ LONG(DEFINED($tableentry$182$.rvectors) ? $tableentry$182$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$183$.rvectors) ? $tableentry$183$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
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+ LONG(DEFINED($tableentry$187$.rvectors) ? $tableentry$187$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$188$.rvectors) ? $tableentry$188$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$189$.rvectors) ? $tableentry$189$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$190$.rvectors) ? $tableentry$190$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
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+ LONG(DEFINED($tableentry$192$.rvectors) ? $tableentry$192$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
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+ LONG(DEFINED($tableentry$194$.rvectors) ? $tableentry$194$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$195$.rvectors) ? $tableentry$195$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
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+ LONG(DEFINED($tableentry$197$.rvectors) ? $tableentry$197$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$198$.rvectors) ? $tableentry$198$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$199$.rvectors) ? $tableentry$199$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$200$.rvectors) ? $tableentry$200$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$201$.rvectors) ? $tableentry$201$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$202$.rvectors) ? $tableentry$202$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$203$.rvectors) ? $tableentry$203$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$204$.rvectors) ? $tableentry$204$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$205$.rvectors) ? $tableentry$205$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$206$.rvectors) ? $tableentry$206$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$207$.rvectors) ? $tableentry$207$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$208$.rvectors) ? $tableentry$208$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$209$.rvectors) ? $tableentry$209$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$210$.rvectors) ? $tableentry$210$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$211$.rvectors) ? $tableentry$211$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$212$.rvectors) ? $tableentry$212$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$213$.rvectors) ? $tableentry$213$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$214$.rvectors) ? $tableentry$214$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$215$.rvectors) ? $tableentry$215$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$216$.rvectors) ? $tableentry$216$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$217$.rvectors) ? $tableentry$217$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$218$.rvectors) ? $tableentry$218$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$219$.rvectors) ? $tableentry$219$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$220$.rvectors) ? $tableentry$220$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$221$.rvectors) ? $tableentry$221$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$222$.rvectors) ? $tableentry$222$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$223$.rvectors) ? $tableentry$223$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$224$.rvectors) ? $tableentry$224$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$225$.rvectors) ? $tableentry$225$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$226$.rvectors) ? $tableentry$226$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$227$.rvectors) ? $tableentry$227$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$228$.rvectors) ? $tableentry$228$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$229$.rvectors) ? $tableentry$229$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$230$.rvectors) ? $tableentry$230$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$231$.rvectors) ? $tableentry$231$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$232$.rvectors) ? $tableentry$232$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$233$.rvectors) ? $tableentry$233$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$234$.rvectors) ? $tableentry$234$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$235$.rvectors) ? $tableentry$235$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$236$.rvectors) ? $tableentry$236$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$237$.rvectors) ? $tableentry$237$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$238$.rvectors) ? $tableentry$238$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$239$.rvectors) ? $tableentry$239$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$240$.rvectors) ? $tableentry$240$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$241$.rvectors) ? $tableentry$241$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$242$.rvectors) ? $tableentry$242$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$243$.rvectors) ? $tableentry$243$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$244$.rvectors) ? $tableentry$244$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$245$.rvectors) ? $tableentry$245$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$246$.rvectors) ? $tableentry$246$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$247$.rvectors) ? $tableentry$247$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$248$.rvectors) ? $tableentry$248$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$249$.rvectors) ? $tableentry$249$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$250$.rvectors) ? $tableentry$250$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$251$.rvectors) ? $tableentry$251$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$252$.rvectors) ? $tableentry$252$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$253$.rvectors) ? $tableentry$253$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$254$.rvectors) ? $tableentry$254$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
+ LONG(DEFINED($tableentry$255$.rvectors) ? $tableentry$255$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF);
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/UNUSED_generated_code/.placeholder b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/UNUSED_generated_code/.placeholder
new file mode 100644
index 00000000000..e69de29bb2d
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/general/r_cg_hardware_setup.c b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/general/r_cg_hardware_setup.c
new file mode 100644
index 00000000000..36780ff2710
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/general/r_cg_hardware_setup.c
@@ -0,0 +1,119 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2016, 2017 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name : r_cg_hardware_setup.c
+* Version : 1.2.0
+* Device(s) : R5F565NEDxFP
+* Description : Initialization file for code generation configurations.
+* Creation Date: 2018-08-29
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Pragma directive
+***********************************************************************************************************************/
+/* Start user code for pragma. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_macrodriver.h"
+#include "r_smc_cgc.h"
+#include "r_smc_interrupt.h"
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#include "r_cg_userdefine.h"
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+/* Start user code for global. Do not edit comment generated here */
+
+/* Workaround to set group interrupt priority level when it is not set in the generated function */
+static void R_Interrupt_Create_Workaround(void);
+static void R_Interrupt_Create_Workaround(void)
+{
+ /* Call the generated function */
+ R_Interrupt_Create();
+
+ /* In case of this project, nothing more to do. But other projects may need some code like following. */
+
+ /* Disable group AL1 interrupt*/
+ //IEN(ICU,GROUPAL1) = 0U;
+
+ /* Set group AL1 interrupt priority level */
+ //IPR(ICU,GROUPAL1) = _02_ICU_PRIORITY_LEVEL2;
+
+ /* Enable group AL1 interrupt */
+ //IEN(ICU,GROUPAL1) = 1U;
+}
+#define R_Interrupt_Create R_Interrupt_Create_Workaround
+
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+* Function Name: r_undefined_exception
+* Description : This function is undefined interrupt service routine
+* Arguments : None
+* Return Value : None
+***********************************************************************************************************************/
+
+void r_undefined_exception(void)
+{
+ /* Start user code for r_undefined_exception. Do not edit comment generated here */
+ /* End user code. Do not edit comment generated here */
+}
+
+/***********************************************************************************************************************
+* Function Name: R_Systeminit
+* Description : This function initializes every configuration
+* Arguments : None
+* Return Value : None
+***********************************************************************************************************************/
+
+void R_Systeminit(void)
+{
+ /* Enable writing to registers related to operating modes, LPC, CGC and software reset */
+ SYSTEM.PRCR.WORD = 0xA50BU;
+
+ /* Enable writing to MPC pin function control registers */
+ MPC.PWPR.BIT.B0WI = 0U;
+ MPC.PWPR.BIT.PFSWE = 1U;
+
+ /* Initialize clocks settings */
+ R_CGC_Create();
+
+ /* Set interrupt settings */
+ R_Interrupt_Create();
+
+ /* Register undefined interrupt */
+ R_BSP_InterruptWrite(BSP_INT_SRC_UNDEFINED_INTERRUPT,(bsp_int_cb_t)r_undefined_exception);
+
+ /* Disable writing to MPC pin function control registers */
+ MPC.PWPR.BIT.PFSWE = 0U;
+ MPC.PWPR.BIT.B0WI = 1U;
+
+ /* Enable protection */
+ SYSTEM.PRCR.WORD = 0xA500U;
+}
+
+/* Start user code for adding. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/general/r_cg_interrupt_handlers.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/general/r_cg_interrupt_handlers.h
new file mode 100644
index 00000000000..ae80482d6ff
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/general/r_cg_interrupt_handlers.h
@@ -0,0 +1,75 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2016, 2017 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name : r_cg_interrupt_handlers.h
+* Version : 1.2.0
+* Device(s) : R5F565NEDxFP
+* Description : This file declares interrupt handlers.
+* Creation Date: 2018-08-29
+***********************************************************************************************************************/
+
+#ifndef INTERRUPT_HANDLERS_H
+#define INTERRUPT_HANDLERS_H
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Macro definitions (Register bit)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Global functions
+***********************************************************************************************************************/
+/* BSC BUSERR */
+void bus_error_isr(void) __attribute__ ((interrupt));
+
+/* ICU GROUPBL2 */
+void group_bl2_handler_isr(void) __attribute__ ((interrupt));
+
+/* ICU GROUPBL0 */
+void group_bl0_handler_isr(void) __attribute__ ((interrupt));
+
+/* ICU GROUPBL1 */
+void group_bl1_handler_isr(void) __attribute__ ((interrupt));
+
+/* ICU GROUPAL0 */
+void group_al0_handler_isr(void) __attribute__ ((interrupt));
+
+/* ICU GROUPAL1 */
+void group_al1_handler_isr(void) __attribute__ ((interrupt));
+
+/* Idle Vectors */
+void undefined_interrupt_source_isr(void) __attribute__ ((interrupt));
+/* Start user code for function. Do not edit comment generated here */
+
+#include "r_cg_vector_pragma.h"
+
+/* End user code. Do not edit comment generated here */
+#endif
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/general/r_cg_macrodriver.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/general/r_cg_macrodriver.h
new file mode 100644
index 00000000000..3ccc5a6d5dd
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/general/r_cg_macrodriver.h
@@ -0,0 +1,86 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2016, 2017 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name : r_cg_macrodriver.h
+* Version : 1.2.0
+* Device(s) : R5F565NEDxFP
+* Description : Macro header file for code generation.
+* Creation Date: 2018-08-29
+***********************************************************************************************************************/
+
+#ifndef MODULEID_H
+#define MODULEID_H
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "platform.h"
+#include "r_smc_interrupt.h"
+#include "r_cg_interrupt_handlers.h"
+
+/***********************************************************************************************************************
+Macro definitions (Register bit)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+#ifndef __TYPEDEF__
+
+/* Status list definition */
+#define MD_STATUSBASE (0x00U)
+#define MD_OK (MD_STATUSBASE + 0x00U) /* register setting OK */
+#define MD_SPT (MD_STATUSBASE + 0x01U) /* IIC stop */
+#define MD_NACK (MD_STATUSBASE + 0x02U) /* IIC no ACK */
+#define MD_BUSY1 (MD_STATUSBASE + 0x03U) /* busy 1 */
+#define MD_BUSY2 (MD_STATUSBASE + 0x04U) /* busy 2 */
+
+/* Error list definition */
+#define MD_ERRORBASE (0x80U)
+#define MD_ERROR (MD_ERRORBASE + 0x00U) /* error */
+#define MD_ARGERROR (MD_ERRORBASE + 0x01U) /* error argument input error */
+#define MD_ERROR1 (MD_ERRORBASE + 0x02U) /* error 1 */
+#define MD_ERROR2 (MD_ERRORBASE + 0x03U) /* error 2 */
+#define MD_ERROR3 (MD_ERRORBASE + 0x04U) /* error 3 */
+#define MD_ERROR4 (MD_ERRORBASE + 0x05U) /* error 4 */
+#define MD_ERROR5 (MD_ERRORBASE + 0x06U) /* error 5 */
+
+#define nop() asm("nop;")
+#define brk() asm("brk;")
+#define wait() asm("wait;")
+
+#endif
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+#ifndef __TYPEDEF__
+ typedef unsigned short MD_STATUS;
+ #define __TYPEDEF__
+#endif
+
+/***********************************************************************************************************************
+Global functions
+***********************************************************************************************************************/
+void R_Systeminit(void);
+/* Start user code for function. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#endif
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/general/r_cg_userdefine.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/general/r_cg_userdefine.h
new file mode 100644
index 00000000000..7be043a1a7e
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/general/r_cg_userdefine.h
@@ -0,0 +1,61 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2016, 2017 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name : r_cg_userdefine.h
+* Version : 1.2.0
+* Device(s) : R5F565NEDxFP
+* Description : User header file for code generation.
+* Creation Date: 2018-08-29
+***********************************************************************************************************************/
+
+#ifndef CG_USER_DEF_H
+#define CG_USER_DEF_H
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Macro definitions (Register bit)
+***********************************************************************************************************************/
+/* Start user code for register. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+/* Start user code for macro define. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+/* Start user code for type define. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Global functions
+***********************************************************************************************************************/
+/* Start user code for function. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#endif
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/general/r_cg_vector_pragma.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/general/r_cg_vector_pragma.h
new file mode 100644
index 00000000000..c8138964559
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/general/r_cg_vector_pragma.h
@@ -0,0 +1,6 @@
+R_PRAGMA_INTERRUPT(bus_error_isr, 16)
+R_PRAGMA_INTERRUPT(group_bl2_handler_isr, 107)
+R_PRAGMA_INTERRUPT(group_bl0_handler_isr, 110)
+R_PRAGMA_INTERRUPT(group_bl1_handler_isr, 111)
+R_PRAGMA_INTERRUPT(group_al0_handler_isr, 112)
+R_PRAGMA_INTERRUPT(group_al1_handler_isr, 113)
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/general/r_cg_vector_table.c b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/general/r_cg_vector_table.c
new file mode 100644
index 00000000000..4825e0b3088
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/general/r_cg_vector_table.c
@@ -0,0 +1,564 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2016, 2017 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name : r_cg_vector_table.c
+* Version : 1.2.0
+* Device(s) : R5F565NEDxFP
+* Description : This file implements interrupt vector table.
+* Creation Date: 2018-08-29
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Pragma directive
+***********************************************************************************************************************/
+/* Start user code for pragma. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_macrodriver.h"
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#include "r_cg_userdefine.h"
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+void * const Reserved_Vector[] __attribute((section(".rvectors"))) =
+{
+ /* 0x0000 Reserved */
+ (void (*)(void))0xFFFFFFFF,
+ /* 0x0004 Reserved */
+ (void (*)(void))0xFFFFFFFF,
+ /* 0x0008 Reserved */
+ (void (*)(void))0xFFFFFFFF,
+ /* 0x000C Reserved */
+ (void (*)(void))0xFFFFFFFF,
+ /* 0x0010 Reserved */
+ (void (*)(void))0xFFFFFFFF,
+ /* 0x0014 Reserved */
+ (void (*)(void))0xFFFFFFFF,
+ /* 0x0018 Reserved */
+ (void (*)(void))0xFFFFFFFF,
+ /* 0x001C Reserved */
+ (void (*)(void))0xFFFFFFFF,
+ /* 0x0020 Reserved */
+ (void (*)(void))0xFFFFFFFF,
+ /* 0x0024 Reserved */
+ (void (*)(void))0xFFFFFFFF,
+ /* 0x0028 Reserved */
+ (void (*)(void))0xFFFFFFFF,
+ /* 0x002C Reserved */
+ (void (*)(void))0xFFFFFFFF,
+ /* 0x0030 Reserved */
+ (void (*)(void))0xFFFFFFFF,
+ /* 0x0034 Reserved */
+ (void (*)(void))0xFFFFFFFF,
+ /* 0x0038 Reserved */
+ (void (*)(void))0xFFFFFFFF,
+ /* 0x003C Reserved */
+ (void (*)(void))0xFFFFFFFF,
+ /* 0x0040 BSC BUSERR */
+ bus_error_isr,
+ /* 0x0044 Reserved */
+ (void (*)(void))0xFFFFFFFF,
+ /* 0x0048 RAM RAMERR */
+ undefined_interrupt_source_isr,
+ /* 0x004C Reserved */
+ (void (*)(void))0xFFFFFFFF,
+ /* 0x0050 Reserved */
+ (void (*)(void))0xFFFFFFFF,
+ /* 0x0054 FCU FIFERR */
+ undefined_interrupt_source_isr,
+ /* 0x0058 Reserved */
+ (void (*)(void))0xFFFFFFFF,
+ /* 0x005C FCU FRDYI */
+ undefined_interrupt_source_isr,
+ /* 0x0060 Reserved */
+ (void (*)(void))0xFFFFFFFF,
+ /* 0x0064 Reserved */
+ (void (*)(void))0xFFFFFFFF,
+ /* 0x0068 ICU SWINT2 */
+ undefined_interrupt_source_isr,
+ /* 0x006C ICU SWINT */
+ undefined_interrupt_source_isr,
+ /* 0x0070 CMT0 CMI0 */
+ undefined_interrupt_source_isr,
+ /* 0x0074 CMT1 CMI1 */
+ undefined_interrupt_source_isr,
+ /* 0x0078 CMTW0 CMWI0 */
+ undefined_interrupt_source_isr,
+ /* 0x007C CMTW1 CMWI1 */
+ undefined_interrupt_source_isr,
+ /* 0x0080 Reserved */
+ (void (*)(void))0xFFFFFFFF,
+ /* 0x0084 Reserved */
+ (void (*)(void))0xFFFFFFFF,
+ /* 0x0088 USB0 D0FIFO0 */
+ undefined_interrupt_source_isr,
+ /* 0x008C USB0 D1FIFO0 */
+ undefined_interrupt_source_isr,
+ /* 0x0090 Reserved */
+ (void (*)(void))0xFFFFFFFF,
+ /* 0x0094 Reserved */
+ (void (*)(void))0xFFFFFFFF,
+ /* 0x0098 RSPI0 SPRI0 */
+ undefined_interrupt_source_isr,
+ /* 0x009C RSPI0 SPTI0 */
+ undefined_interrupt_source_isr,
+ /* 0x00A0 RSPI1 SPRI1 */
+ undefined_interrupt_source_isr,
+ /* 0x00A4 RSPI1 SPTI1 */
+ undefined_interrupt_source_isr,
+ /* 0x00A8 QSPI SPRI */
+ undefined_interrupt_source_isr,
+ /* 0x00AC QSPI SPTI */
+ undefined_interrupt_source_isr,
+ /* 0x00B0 SDHI SBFAI */
+ undefined_interrupt_source_isr,
+ /* 0x00B4 MMCIF MBFAI */
+ undefined_interrupt_source_isr,
+ /* 0x00B8 Reserved */
+ (void (*)(void))0xFFFFFFFF,
+ /* 0x00BC Reserved */
+ (void (*)(void))0xFFFFFFFF,
+ /* 0x00C0 Reserved */
+ (void (*)(void))0xFFFFFFFF,
+ /* 0x00C4 Reserved */
+ (void (*)(void))0xFFFFFFFF,
+ /* 0x00C8 RIIC1 RXI1 */
+ undefined_interrupt_source_isr,
+ /* 0x00CC RIIC1 TXI1 */
+ undefined_interrupt_source_isr,
+ /* 0x00D0 RIIC0 RXI0 */
+ undefined_interrupt_source_isr,
+ /* 0x00D4 RIIC0 TXI0 */
+ undefined_interrupt_source_isr,
+ /* 0x00D8 RIIC2 RXI2 */
+ undefined_interrupt_source_isr,
+ /* 0x00DC RIIC2 TXI2 */
+ undefined_interrupt_source_isr,
+ /* 0x00E0 Reserved */
+ (void (*)(void))0xFFFFFFFF,
+ /* 0x00E4 Reserved */
+ (void (*)(void))0xFFFFFFFF,
+ /* 0x00E8 SCI0 RXI0 */
+ undefined_interrupt_source_isr,
+ /* 0x00EC SCI0 TXI0 */
+ undefined_interrupt_source_isr,
+ /* 0x00F0 SCI1 RXI1 */
+ undefined_interrupt_source_isr,
+ /* 0x00F4 SCI1 TXI1 */
+ undefined_interrupt_source_isr,
+ /* 0x00F8 SCI2 RXI2 */
+ undefined_interrupt_source_isr,
+ /* 0x00FC SCI2 TXI2 */
+ undefined_interrupt_source_isr,
+ /* 0x0100 ICU IRQ0 */
+ undefined_interrupt_source_isr,
+ /* 0x0104 ICU IRQ1 */
+ undefined_interrupt_source_isr,
+ /* 0x0108 ICU IRQ2 */
+ undefined_interrupt_source_isr,
+ /* 0x010C ICU IRQ3 */
+ undefined_interrupt_source_isr,
+ /* 0x0110 ICU IRQ4 */
+ undefined_interrupt_source_isr,
+ /* 0x0114 ICU IRQ5 */
+ undefined_interrupt_source_isr,
+ /* 0x0118 ICU IRQ6 */
+ undefined_interrupt_source_isr,
+ /* 0x011C ICU IRQ7 */
+ undefined_interrupt_source_isr,
+ /* 0x0120 ICU IRQ8 */
+ undefined_interrupt_source_isr,
+ /* 0x0124 ICU IRQ9 */
+ undefined_interrupt_source_isr,
+ /* 0x0128 ICU IRQ10 */
+ undefined_interrupt_source_isr,
+ /* 0x012C ICU IRQ11 */
+ undefined_interrupt_source_isr,
+ /* 0x0130 ICU IRQ12 */
+ undefined_interrupt_source_isr,
+ /* 0x0134 ICU IRQ13 */
+ undefined_interrupt_source_isr,
+ /* 0x0138 ICU IRQ14 */
+ undefined_interrupt_source_isr,
+ /* 0x013C ICU IRQ15 */
+ undefined_interrupt_source_isr,
+ /* 0x0140 SCI3 RXI3 */
+ undefined_interrupt_source_isr,
+ /* 0x0144 SCI3 TXI3 */
+ undefined_interrupt_source_isr,
+ /* 0x0148 SCI4 RXI4 */
+ undefined_interrupt_source_isr,
+ /* 0x014C SCI4 TXI4 */
+ undefined_interrupt_source_isr,
+ /* 0x0150 SCI5 RXI5 */
+ undefined_interrupt_source_isr,
+ /* 0x0154 SCI5 TXI5 */
+ undefined_interrupt_source_isr,
+ /* 0x0158 SCI6 RXI6 */
+ undefined_interrupt_source_isr,
+ /* 0x015C SCI6 TXI6 */
+ undefined_interrupt_source_isr,
+ /* 0x0160 LVD1 LVD1 */
+ undefined_interrupt_source_isr,
+ /* 0x0164 LVD2 LVD2 */
+ undefined_interrupt_source_isr,
+ /* 0x0168 USB0 USBR0 */
+ undefined_interrupt_source_isr,
+ /* 0x016C Reserved */
+ (void (*)(void))0xFFFFFFFF,
+ /* 0x0170 RTC ALM */
+ undefined_interrupt_source_isr,
+ /* 0x0174 RTC PRD */
+ undefined_interrupt_source_isr,
+ /* 0x0178 Reserved */
+ (void (*)(void))0xFFFFFFFF,
+ /* 0x017C IWDT IWUNI */
+ undefined_interrupt_source_isr,
+ /* 0x0180 WDT WUNI */
+ undefined_interrupt_source_isr,
+ /* 0x0184 PDC PCDFI */
+ undefined_interrupt_source_isr,
+ /* 0x0188 SCI7 RXI7 */
+ undefined_interrupt_source_isr,
+ /* 0x018C SCI7 TXI7 */
+ undefined_interrupt_source_isr,
+ /* 0x0190 SCI8 RXI8 */
+ undefined_interrupt_source_isr,
+ /* 0x0194 SCI8 TXI8 */
+ undefined_interrupt_source_isr,
+ /* 0x0198 SCI9 RXI9 */
+ undefined_interrupt_source_isr,
+ /* 0x019C SCI9 TXI9 */
+ undefined_interrupt_source_isr,
+ /* 0x01A0 SCI10 RXI10 */
+ undefined_interrupt_source_isr,
+ /* 0x01A4 SCI10 TXI10 */
+ undefined_interrupt_source_isr,
+ /* 0x01A8 ICU GROUPBE0 */
+ undefined_interrupt_source_isr,
+ /* 0x01AC ICU GROUPBL2 */
+ group_bl2_handler_isr,
+ /* 0x01B0 RSPI2 SPRI2 */
+ undefined_interrupt_source_isr,
+ /* 0x01B4 RSPI2 SPTI2 */
+ undefined_interrupt_source_isr,
+ /* 0x01B8 ICU GROUPBL0 */
+ group_bl0_handler_isr,
+ /* 0x01BC ICU GROUPBL1 */
+ group_bl1_handler_isr,
+ /* 0x01C0 ICU GROUPAL0 */
+ group_al0_handler_isr,
+ /* 0x01C4 ICU GROUPAL1 */
+ group_al1_handler_isr,
+ /* 0x01C8 SCI11 RXI11 */
+ undefined_interrupt_source_isr,
+ /* 0x01CC SCI11 TXI11 */
+ undefined_interrupt_source_isr,
+ /* 0x01D0 SCI12 RXI12 */
+ undefined_interrupt_source_isr,
+ /* 0x01D4 SCI12 TXI12 */
+ undefined_interrupt_source_isr,
+ /* 0x01D8 Reserved */
+ (void (*)(void))0xFFFFFFFF,
+ /* 0x01DC Reserved */
+ (void (*)(void))0xFFFFFFFF,
+ /* 0x01E0 DMAC DMAC0I */
+ undefined_interrupt_source_isr,
+ /* 0x01E4 DMAC DMAC1I */
+ undefined_interrupt_source_isr,
+ /* 0x01E8 DMAC DMAC2I */
+ undefined_interrupt_source_isr,
+ /* 0x01EC DMAC DMAC3I */
+ undefined_interrupt_source_isr,
+ /* 0x01F0 DMAC DMAC74I */
+ undefined_interrupt_source_isr,
+ /* 0x01F4 OST OSTDI */
+ undefined_interrupt_source_isr,
+ /* 0x01F8 EXDMAC EXDMAC0I */
+ undefined_interrupt_source_isr,
+ /* 0x01FC EXDMAC EXDMAC1I */
+ undefined_interrupt_source_isr,
+ /* 0x0200 PERIB INTB128 */
+ undefined_interrupt_source_isr,
+ /* 0x0204 PERIB INTB129 */
+ undefined_interrupt_source_isr,
+ /* 0x0208 PERIB INTB130 */
+ undefined_interrupt_source_isr,
+ /* 0x020C PERIB INTB131 */
+ undefined_interrupt_source_isr,
+ /* 0x0210 PERIB INTB132 */
+ undefined_interrupt_source_isr,
+ /* 0x0214 PERIB INTB133 */
+ undefined_interrupt_source_isr,
+ /* 0x0218 PERIB INTB134 */
+ undefined_interrupt_source_isr,
+ /* 0x021C PERIB INTB135 */
+ undefined_interrupt_source_isr,
+ /* 0x0220 PERIB INTB136 */
+ undefined_interrupt_source_isr,
+ /* 0x0224 PERIB INTB137 */
+ undefined_interrupt_source_isr,
+ /* 0x0228 PERIB INTB138 */
+ undefined_interrupt_source_isr,
+ /* 0x022C PERIB INTB139 */
+ undefined_interrupt_source_isr,
+ /* 0x0230 PERIB INTB140 */
+ undefined_interrupt_source_isr,
+ /* 0x0234 PERIB INTB141 */
+ undefined_interrupt_source_isr,
+ /* 0x0238 PERIB INTB142 */
+ undefined_interrupt_source_isr,
+ /* 0x023C PERIB INTB143 */
+ undefined_interrupt_source_isr,
+ /* 0x0240 PERIB INTB144 */
+ undefined_interrupt_source_isr,
+ /* 0x0244 PERIB INTB145 */
+ undefined_interrupt_source_isr,
+ /* 0x0248 PERIB INTB146 */
+ undefined_interrupt_source_isr,
+ /* 0x024C PERIB INTB147 */
+ undefined_interrupt_source_isr,
+ /* 0x0250 PERIB INTB148 */
+ undefined_interrupt_source_isr,
+ /* 0x0254 PERIB INTB149 */
+ undefined_interrupt_source_isr,
+ /* 0x0258 PERIB INTB150 */
+ undefined_interrupt_source_isr,
+ /* 0x025C PERIB INTB151 */
+ undefined_interrupt_source_isr,
+ /* 0x0260 PERIB INTB152 */
+ undefined_interrupt_source_isr,
+ /* 0x0264 PERIB INTB153 */
+ undefined_interrupt_source_isr,
+ /* 0x0268 PERIB INTB154 */
+ undefined_interrupt_source_isr,
+ /* 0x026C PERIB INTB155 */
+ undefined_interrupt_source_isr,
+ /* 0x0270 PERIB INTB156 */
+ undefined_interrupt_source_isr,
+ /* 0x0274 PERIB INTB157 */
+ undefined_interrupt_source_isr,
+ /* 0x0278 PERIB INTB158 */
+ undefined_interrupt_source_isr,
+ /* 0x027C PERIB INTB159 */
+ undefined_interrupt_source_isr,
+ /* 0x0280 PERIB INTB160 */
+ undefined_interrupt_source_isr,
+ /* 0x0284 PERIB INTB161 */
+ undefined_interrupt_source_isr,
+ /* 0x0288 PERIB INTB162 */
+ undefined_interrupt_source_isr,
+ /* 0x028C PERIB INTB163 */
+ undefined_interrupt_source_isr,
+ /* 0x0290 PERIB INTB164 */
+ undefined_interrupt_source_isr,
+ /* 0x0294 PERIB INTB165 */
+ undefined_interrupt_source_isr,
+ /* 0x0298 PERIB INTB166 */
+ undefined_interrupt_source_isr,
+ /* 0x029C PERIB INTB167 */
+ undefined_interrupt_source_isr,
+ /* 0x02A0 PERIB INTB168 */
+ undefined_interrupt_source_isr,
+ /* 0x02A4 PERIB INTB169 */
+ undefined_interrupt_source_isr,
+ /* 0x02A8 PERIB INTB170 */
+ undefined_interrupt_source_isr,
+ /* 0x02AC PERIB INTB171 */
+ undefined_interrupt_source_isr,
+ /* 0x02B0 PERIB INTB172 */
+ undefined_interrupt_source_isr,
+ /* 0x02B4 PERIB INTB173 */
+ undefined_interrupt_source_isr,
+ /* 0x02B8 PERIB INTB174 */
+ undefined_interrupt_source_isr,
+ /* 0x02BC PERIB INTB175 */
+ undefined_interrupt_source_isr,
+ /* 0x02C0 PERIB INTB176 */
+ undefined_interrupt_source_isr,
+ /* 0x02C4 PERIB INTB177 */
+ undefined_interrupt_source_isr,
+ /* 0x02C8 PERIB INTB178 */
+ undefined_interrupt_source_isr,
+ /* 0x02CC PERIB INTB179 */
+ undefined_interrupt_source_isr,
+ /* 0x02D0 PERIB INTB180 */
+ undefined_interrupt_source_isr,
+ /* 0x02D4 PERIB INTB181 */
+ undefined_interrupt_source_isr,
+ /* 0x02D8 PERIB INTB182 */
+ undefined_interrupt_source_isr,
+ /* 0x02DC PERIB INTB183 */
+ undefined_interrupt_source_isr,
+ /* 0x02E0 PERIB INTB184 */
+ undefined_interrupt_source_isr,
+ /* 0x02E4 PERIB INTB185 */
+ undefined_interrupt_source_isr,
+ /* 0x02E8 PERIB INTB186 */
+ undefined_interrupt_source_isr,
+ /* 0x02EC PERIB INTB187 */
+ undefined_interrupt_source_isr,
+ /* 0x02F0 PERIB INTB188 */
+ undefined_interrupt_source_isr,
+ /* 0x02F4 PERIB INTB189 */
+ undefined_interrupt_source_isr,
+ /* 0x02F8 PERIB INTB190 */
+ undefined_interrupt_source_isr,
+ /* 0x02FC PERIB INTB191 */
+ undefined_interrupt_source_isr,
+ /* 0x0300 PERIB INTB192 */
+ undefined_interrupt_source_isr,
+ /* 0x0304 PERIB INTB193 */
+ undefined_interrupt_source_isr,
+ /* 0x0308 PERIB INTB194 */
+ undefined_interrupt_source_isr,
+ /* 0x030C PERIB INTB195 */
+ undefined_interrupt_source_isr,
+ /* 0x0310 PERIB INTB196 */
+ undefined_interrupt_source_isr,
+ /* 0x0314 PERIB INTB197 */
+ undefined_interrupt_source_isr,
+ /* 0x0318 PERIB INTB198 */
+ undefined_interrupt_source_isr,
+ /* 0x031C PERIB INTB199 */
+ undefined_interrupt_source_isr,
+ /* 0x0320 PERIB INTB200 */
+ undefined_interrupt_source_isr,
+ /* 0x0324 PERIB INTB201 */
+ undefined_interrupt_source_isr,
+ /* 0x0328 PERIB INTB202 */
+ undefined_interrupt_source_isr,
+ /* 0x032C PERIB INTB203 */
+ undefined_interrupt_source_isr,
+ /* 0x0330 PERIB INTB204 */
+ undefined_interrupt_source_isr,
+ /* 0x0334 PERIB INTB205 */
+ undefined_interrupt_source_isr,
+ /* 0x0338 PERIB INTB206 */
+ undefined_interrupt_source_isr,
+ /* 0x033C PERIB INTB207 */
+ undefined_interrupt_source_isr,
+ /* 0x0340 PERIA INTA208 */
+ undefined_interrupt_source_isr,
+ /* 0x0344 PERIA INTA209 */
+ undefined_interrupt_source_isr,
+ /* 0x0348 PERIA INTA210 */
+ undefined_interrupt_source_isr,
+ /* 0x034C PERIA INTA211 */
+ undefined_interrupt_source_isr,
+ /* 0x0350 PERIA INTA212 */
+ undefined_interrupt_source_isr,
+ /* 0x0354 PERIA INTA213 */
+ undefined_interrupt_source_isr,
+ /* 0x0358 PERIA INTA214 */
+ undefined_interrupt_source_isr,
+ /* 0x035C PERIA INTA215 */
+ undefined_interrupt_source_isr,
+ /* 0x0360 PERIA INTA216 */
+ undefined_interrupt_source_isr,
+ /* 0x0364 PERIA INTA217 */
+ undefined_interrupt_source_isr,
+ /* 0x0368 PERIA INTA218 */
+ undefined_interrupt_source_isr,
+ /* 0x036C PERIA INTA219 */
+ undefined_interrupt_source_isr,
+ /* 0x0370 PERIA INTA220 */
+ undefined_interrupt_source_isr,
+ /* 0x0374 PERIA INTA221 */
+ undefined_interrupt_source_isr,
+ /* 0x0378 PERIA INTA222 */
+ undefined_interrupt_source_isr,
+ /* 0x037C PERIA INTA223 */
+ undefined_interrupt_source_isr,
+ /* 0x0380 PERIA INTA224 */
+ undefined_interrupt_source_isr,
+ /* 0x0384 PERIA INTA225 */
+ undefined_interrupt_source_isr,
+ /* 0x0388 PERIA INTA226 */
+ undefined_interrupt_source_isr,
+ /* 0x038C PERIA INTA227 */
+ undefined_interrupt_source_isr,
+ /* 0x0390 PERIA INTA228 */
+ undefined_interrupt_source_isr,
+ /* 0x0394 PERIA INTA229 */
+ undefined_interrupt_source_isr,
+ /* 0x0398 PERIA INTA230 */
+ undefined_interrupt_source_isr,
+ /* 0x039C PERIA INTA231 */
+ undefined_interrupt_source_isr,
+ /* 0x03A0 PERIA INTA232 */
+ undefined_interrupt_source_isr,
+ /* 0x03A4 PERIA INTA233 */
+ undefined_interrupt_source_isr,
+ /* 0x03A8 PERIA INTA234 */
+ undefined_interrupt_source_isr,
+ /* 0x03AC PERIA INTA235 */
+ undefined_interrupt_source_isr,
+ /* 0x03B0 PERIA INTA236 */
+ undefined_interrupt_source_isr,
+ /* 0x03B4 PERIA INTA237 */
+ undefined_interrupt_source_isr,
+ /* 0x03B8 PERIA INTA238 */
+ undefined_interrupt_source_isr,
+ /* 0x03BC PERIA INTA239 */
+ undefined_interrupt_source_isr,
+ /* 0x03C0 PERIA INTA240 */
+ undefined_interrupt_source_isr,
+ /* 0x03C4 PERIA INTA241 */
+ undefined_interrupt_source_isr,
+ /* 0x03C8 PERIA INTA242 */
+ undefined_interrupt_source_isr,
+ /* 0x03CC PERIA INTA243 */
+ undefined_interrupt_source_isr,
+ /* 0x03D0 PERIA INTA244 */
+ undefined_interrupt_source_isr,
+ /* 0x03D4 PERIA INTA245 */
+ undefined_interrupt_source_isr,
+ /* 0x03D8 PERIA INTA246 */
+ undefined_interrupt_source_isr,
+ /* 0x03DC PERIA INTA247 */
+ undefined_interrupt_source_isr,
+ /* 0x03E0 PERIA INTA248 */
+ undefined_interrupt_source_isr,
+ /* 0x03E4 PERIA INTA249 */
+ undefined_interrupt_source_isr,
+ /* 0x03E8 PERIA INTA250 */
+ undefined_interrupt_source_isr,
+ /* 0x03EC PERIA INTA251 */
+ undefined_interrupt_source_isr,
+ /* 0x03F0 PERIA INTA252 */
+ undefined_interrupt_source_isr,
+ /* 0x03F4 PERIA INTA253 */
+ undefined_interrupt_source_isr,
+ /* 0x03F8 PERIA INTA254 */
+ undefined_interrupt_source_isr,
+ /* 0x03FC PERIA INTA255 */
+ undefined_interrupt_source_isr
+};
+/* Start user code for global. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/* Start user code for adding. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/general/r_smc_cgc.c b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/general/r_smc_cgc.c
new file mode 100644
index 00000000000..44624e06a58
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/general/r_smc_cgc.c
@@ -0,0 +1,45 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2016, 2017 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name : r_smc_cgc.c
+* Version : 1.1.2
+* Device(s) : R5F565NEDxFP
+* Description : This file implements cgc setting
+* Creation Date: 2018-08-29
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_macrodriver.h"
+#include "r_smc_cgc.h"
+#include "platform.h"
+
+/***********************************************************************************************************************
+* Function Name: R_CGC_Create
+* Description : This function Used to initializes the clock generator
+* Arguments : None
+* Return Value : None
+***********************************************************************************************************************/
+
+void R_CGC_Create(void)
+{
+
+ R_CGC_Create_UserInit();
+}
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/general/r_smc_cgc.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/general/r_smc_cgc.h
new file mode 100644
index 00000000000..791faeaa094
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/general/r_smc_cgc.h
@@ -0,0 +1,217 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2016, 2017 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name : r_smc_cgc.h
+* Version : 1.1.2
+* Device(s) : R5F565NEDxFP
+* Description : This file implements cgc setting.
+* Creation Date: 2018-08-29
+***********************************************************************************************************************/
+
+#ifndef SMC_CGC_H
+#define SMC_CGC_H
+
+/***********************************************************************************************************************
+Macro definitions (Register bit)
+***********************************************************************************************************************/
+/*
+ System Clock Control Register (SCKCR)
+*/
+/* Peripheral Module Clock D (PCLKD) */
+#define _00000000_CGC_PCLKD_DIV_1 (0x00000000UL) /* x1 */
+#define _00000001_CGC_PCLKD_DIV_2 (0x00000001UL) /* x1/2 */
+#define _00000002_CGC_PCLKD_DIV_4 (0x00000002UL) /* x1/4 */
+#define _00000003_CGC_PCLKD_DIV_8 (0x00000003UL) /* x1/8 */
+#define _00000004_CGC_PCLKD_DIV_16 (0x00000004UL) /* x1/16 */
+#define _00000005_CGC_PCLKD_DIV_32 (0x00000005UL) /* x1/32 */
+#define _00000006_CGC_PCLKD_DIV_64 (0x00000006UL) /* x1/64 */
+/* Peripheral Module Clock C (PCLKC) */
+#define _00000000_CGC_PCLKC_DIV_1 (0x00000000UL) /* x1 */
+#define _00000010_CGC_PCLKC_DIV_2 (0x00000010UL) /* x1/2 */
+#define _00000020_CGC_PCLKC_DIV_4 (0x00000020UL) /* x1/4 */
+#define _00000030_CGC_PCLKC_DIV_8 (0x00000030UL) /* x1/8 */
+#define _00000040_CGC_PCLKC_DIV_16 (0x00000040UL) /* x1/16 */
+#define _00000050_CGC_PCLKC_DIV_32 (0x00000050UL) /* x1/32 */
+#define _00000060_CGC_PCLKC_DIV_64 (0x00000060UL) /* x1/64 */
+/* Peripheral Module Clock B (PCLKB) */
+#define _00000000_CGC_PCLKB_DIV_1 (0x00000000UL) /* x1 */
+#define _00000100_CGC_PCLKB_DIV_2 (0x00000100UL) /* x1/2 */
+#define _00000200_CGC_PCLKB_DIV_4 (0x00000200UL) /* x1/4 */
+#define _00000300_CGC_PCLKB_DIV_8 (0x00000300UL) /* x1/8 */
+#define _00000400_CGC_PCLKB_DIV_16 (0x00000400UL) /* x1/16 */
+#define _00000500_CGC_PCLKB_DIV_32 (0x00000500UL) /* x1/32 */
+#define _00000600_CGC_PCLKB_DIV_64 (0x00000600UL) /* x1/64 */
+/* Peripheral Module Clock A (PCLKA) */
+#define _00000000_CGC_PCLKA_DIV_1 (0x00000000UL) /* x1 */
+#define _00001000_CGC_PCLKA_DIV_2 (0x00001000UL) /* x1/2 */
+#define _00002000_CGC_PCLKA_DIV_4 (0x00002000UL) /* x1/4 */
+#define _00003000_CGC_PCLKA_DIV_8 (0x00003000UL) /* x1/8 */
+#define _00004000_CGC_PCLKA_DIV_16 (0x00004000UL) /* x1/16 */
+#define _00005000_CGC_PCLKA_DIV_32 (0x00005000UL) /* x1/32 */
+#define _00006000_CGC_PCLKA_DIV_64 (0x00006000UL) /* x1/64 */
+/* External Bus Clock (BCLK) */
+#define _00000000_CGC_BCLK_DIV_1 (0x00000000UL) /* x1 */
+#define _00010000_CGC_BCLK_DIV_2 (0x00010000UL) /* x1/2 */
+#define _00020000_CGC_BCLK_DIV_4 (0x00020000UL) /* x1/4 */
+#define _00030000_CGC_BCLK_DIV_8 (0x00030000UL) /* x1/8 */
+#define _00040000_CGC_BCLK_DIV_16 (0x00040000UL) /* x1/16 */
+#define _00050000_CGC_BCLK_DIV_32 (0x00050000UL) /* x1/32 */
+#define _00060000_CGC_BCLK_DIV_64 (0x00060000UL) /* x1/64 */
+/* System Clock (ICLK) */
+#define _00000000_CGC_ICLK_DIV_1 (0x00000000UL) /* x1 */
+#define _01000000_CGC_ICLK_DIV_2 (0x01000000UL) /* x1/2 */
+#define _02000000_CGC_ICLK_DIV_4 (0x02000000UL) /* x1/4 */
+#define _03000000_CGC_ICLK_DIV_8 (0x03000000UL) /* x1/8 */
+#define _04000000_CGC_ICLK_DIV_16 (0x04000000UL) /* x1/16 */
+#define _05000000_CGC_ICLK_DIV_32 (0x05000000UL) /* x1/32 */
+#define _06000000_CGC_ICLK_DIV_64 (0x06000000UL) /* x1/64 */
+/* System Clock (FCLK) */
+#define _00000000_CGC_FCLK_DIV_1 (0x00000000UL) /* x1 */
+#define _10000000_CGC_FCLK_DIV_2 (0x10000000UL) /* x1/2 */
+#define _20000000_CGC_FCLK_DIV_4 (0x20000000UL) /* x1/4 */
+#define _30000000_CGC_FCLK_DIV_8 (0x30000000UL) /* x1/8 */
+#define _40000000_CGC_FCLK_DIV_16 (0x40000000UL) /* x1/16 */
+#define _50000000_CGC_FCLK_DIV_32 (0x50000000UL) /* x1/32 */
+#define _60000000_CGC_FCLK_DIV_64 (0x60000000UL) /* x1/64 */
+
+/*
+ System Clock Control Register 2 (SCKCR2)
+*/
+#define _0010_CGC_UCLK_DIV_1 (0x0010U) /* x1/2 */
+#define _0020_CGC_UCLK_DIV_3 (0x0020U) /* x1/3 */
+#define _0030_CGC_UCLK_DIV_4 (0x0030U) /* x1/4 */
+#define _0040_CGC_UCLK_DIV_5 (0x0040U) /* x1/5 */
+#define _0001_SCKCR2_BIT0 (0x0001U) /* RESERVE BIT0 */
+
+/*
+ System Clock Control Register 3 (SCKCR3)
+*/
+#define _0000_CGC_CLOCKSOURCE_LOCO (0x0000U) /* LOCO */
+#define _0100_CGC_CLOCKSOURCE_HOCO (0x0100U) /* HOCO */
+#define _0200_CGC_CLOCKSOURCE_MAINCLK (0x0200U) /* Main clock oscillator */
+#define _0300_CGC_CLOCKSOURCE_SUBCLK (0x0300U) /* Sub-clock oscillator */
+#define _0400_CGC_CLOCKSOURCE_PLL (0x0400U) /* PLL circuit */
+
+/*
+ PLL Control Register (PLLCR)
+*/
+/* PLL Input Frequency Division Ratio Select (PLIDIV[1:0]) */
+#define _0000_CGC_PLL_FREQ_DIV_1 (0x0000U) /* x1 */
+#define _0001_CGC_PLL_FREQ_DIV_2 (0x0001U) /* x1/2 */
+#define _0002_CGC_PLL_FREQ_DIV_3 (0x0002U) /* x1/3 */
+/* PLL Clock Source Select (PLLSRCSEL) */
+#define _0000_CGC_PLL_SOURCE_MAIN (0x0000U) /* Main clock oscillator */
+#define _0010_CGC_PLL_SOURCE_HOCO (0x0010U) /* HOCO */
+/* Frequency Multiplication Factor Select (STC[5:0]) */
+#define _1300_CGC_PLL_FREQ_MUL_10_0 (0x1300U) /* x10.0 */
+#define _1400_CGC_PLL_FREQ_MUL_10_5 (0x1400U) /* x10.5 */
+#define _1500_CGC_PLL_FREQ_MUL_11_0 (0x1500U) /* x11.0 */
+#define _1600_CGC_PLL_FREQ_MUL_11_5 (0x1600U) /* x11.5 */
+#define _1700_CGC_PLL_FREQ_MUL_12_0 (0x1700U) /* x12.0 */
+#define _1800_CGC_PLL_FREQ_MUL_12_5 (0x1800U) /* x12.5 */
+#define _1900_CGC_PLL_FREQ_MUL_13_0 (0x1900U) /* x13.0 */
+#define _1A00_CGC_PLL_FREQ_MUL_13_5 (0x1A00U) /* x13.5 */
+#define _1B00_CGC_PLL_FREQ_MUL_14_0 (0x1B00U) /* x14.0 */
+#define _1C00_CGC_PLL_FREQ_MUL_14_5 (0x1C00U) /* x14.5 */
+#define _1D00_CGC_PLL_FREQ_MUL_15_0 (0x1D00U) /* x15.0 */
+#define _1E00_CGC_PLL_FREQ_MUL_15_5 (0x1E00U) /* x15.5 */
+#define _1F00_CGC_PLL_FREQ_MUL_16_0 (0x1F00U) /* x16.0 */
+#define _2000_CGC_PLL_FREQ_MUL_16_5 (0x2000U) /* x16.5 */
+#define _2100_CGC_PLL_FREQ_MUL_17_0 (0x2100U) /* x17.0 */
+#define _2200_CGC_PLL_FREQ_MUL_17_5 (0x2200U) /* x17.5 */
+#define _2300_CGC_PLL_FREQ_MUL_18_0 (0x2300U) /* x18.0 */
+#define _2400_CGC_PLL_FREQ_MUL_18_5 (0x2400U) /* x18.5 */
+#define _2500_CGC_PLL_FREQ_MUL_19_0 (0x2500U) /* x19.0 */
+#define _2600_CGC_PLL_FREQ_MUL_19_5 (0x2600U) /* x19.5 */
+#define _2700_CGC_PLL_FREQ_MUL_20_0 (0x2700U) /* x20.0 */
+#define _2800_CGC_PLL_FREQ_MUL_20_5 (0x2800U) /* x20.5 */
+#define _2900_CGC_PLL_FREQ_MUL_21_0 (0x2900U) /* x21.0 */
+#define _2A00_CGC_PLL_FREQ_MUL_21_5 (0x2A00U) /* x21.5 */
+#define _2B00_CGC_PLL_FREQ_MUL_22_0 (0x2B00U) /* x22.0 */
+#define _2C00_CGC_PLL_FREQ_MUL_22_5 (0x2C00U) /* x22.5 */
+#define _2D00_CGC_PLL_FREQ_MUL_23_0 (0x2D00U) /* x23.0 */
+#define _2E00_CGC_PLL_FREQ_MUL_23_5 (0x2E00U) /* x23.5 */
+#define _2F00_CGC_PLL_FREQ_MUL_24_0 (0x2F00U) /* x24.0 */
+#define _3000_CGC_PLL_FREQ_MUL_24_5 (0x3000U) /* x24.5 */
+#define _3100_CGC_PLL_FREQ_MUL_25_0 (0x3100U) /* x25.0 */
+#define _3200_CGC_PLL_FREQ_MUL_25_5 (0x3200U) /* x25.5 */
+#define _3300_CGC_PLL_FREQ_MUL_26_0 (0x3300U) /* x26.0 */
+#define _3400_CGC_PLL_FREQ_MUL_26_5 (0x3400U) /* x26.5 */
+#define _3500_CGC_PLL_FREQ_MUL_27_0 (0x3500U) /* x27.0 */
+#define _3600_CGC_PLL_FREQ_MUL_27_5 (0x3600U) /* x27.5 */
+#define _3700_CGC_PLL_FREQ_MUL_28_0 (0x3700U) /* x28.0 */
+#define _3800_CGC_PLL_FREQ_MUL_28_5 (0x3800U) /* x28.5 */
+#define _3900_CGC_PLL_FREQ_MUL_29_0 (0x3900U) /* x29.0 */
+#define _3A00_CGC_PLL_FREQ_MUL_29_5 (0x3A00U) /* x29.5 */
+#define _3B00_CGC_PLL_FREQ_MUL_30_0 (0x3B00U) /* x30.0 */
+
+/*
+ Oscillation Stop Detection Control Register (OSTDCR)
+*/
+/* Oscillation Stop Detection Interrupt Enable (OSTDIE) */
+#define _00_CGC_OSC_STOP_INT_DISABLE (0x00U) /* The oscillation stop detection interrupt is disabled */
+#define _01_CGC_OSC_STOP_INT_ENABLE (0x01U) /* The oscillation stop detection interrupt is enabled */
+/* Oscillation Stop Detection Function Enable (OSTDE) */
+#define _00_CGC_OSC_STOP_DISABLE (0x00U) /* Oscillation stop detection function is disabled */
+#define _80_CGC_OSC_STOP_ENABLE (0x80U) /* Oscillation stop detection function is enabled */
+
+/*
+ High-Speed On-Chip Oscillator Control Register 2 (HOCOCR2)
+*/
+/* HOCO Frequency Setting (HCFRQ[1:0]) */
+#define _00_CGC_HOCO_CLK_16 (0x00U) /* 16 MHz */
+#define _01_CGC_HOCO_CLK_18 (0x01U) /* 18 MHz */
+#define _02_CGC_HOCO_CLK_20 (0x02U) /* 20 MHz */
+
+/*
+ Main Clock Oscillator Forced Oscillation Control Register (MOFCR)
+*/
+/* Main Oscillator Drive Capability 2 Switching (MODRV2[1:0]) */
+#define _00_CGC_MAINOSC_UNDER24M (0x00U) /* 20.1 to 24 MHz */
+#define _10_CGC_MAINOSC_UNDER20M (0x10U) /* 16.1 to 20 MHz */
+#define _20_CGC_MAINOSC_UNDER16M (0x20U) /* 8.1 to 16 MHz */
+#define _30_CGC_MAINOSC_EQUATE8M (0x30U) /* 8 MHz */
+/* Main Clock Oscillator Switch (MOSEL) */
+#define _00_CGC_MAINOSC_RESONATOR (0x00U) /* Resonator */
+#define _40_CGC_MAINOSC_EXTERNAL (0x40U) /* External oscillator input */
+
+/*
+ RTC Control Register 4 (RCR4)
+*/
+/* Count source select */
+#define _00_RTC_SOURCE_SELECT_SUB (0x00U) /* Select sub-clock oscillator */
+#define _01_RTC_SOURCE_SELECT_MAIN_FORCED (0x01U) /* Select main clock oscillator */
+#define _53_CGC_MOSCWTCR_VALUE (0x53U) /* Main Clock Oscillator Wait Time */
+#define _21_CGC_SOSCWTCR_VALUE (0x21U) /* Sub-Clock Oscillator Wait Time */
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Global functions
+***********************************************************************************************************************/
+void R_CGC_Create(void);
+void R_CGC_Create_UserInit();
+#endif
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/general/r_smc_cgc_user.c b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/general/r_smc_cgc_user.c
new file mode 100644
index 00000000000..79e02af50a1
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/general/r_smc_cgc_user.c
@@ -0,0 +1,63 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2016, 2017 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name : r_smc_cgc_user.c
+* Version : 1.1.2
+* Device(s) : R5F565NEDxFP
+* Description : None
+* Creation Date: 2018-08-29
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Pragma directive
+***********************************************************************************************************************/
+/* Start user code for pragma. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_macrodriver.h"
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#include "r_cg_userdefine.h"
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+/* Start user code for global. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+* Function Name: R_CGC_Create_UserInit
+* Description : This function adds user code after initializing CGC
+* Arguments : None
+* Return Value : None
+***********************************************************************************************************************/
+
+void R_CGC_Create_UserInit(void)
+{
+ /* Start user code for code init. Do not edit comment generated here */
+ /* End user code. Do not edit comment generated here */
+}
+
+/* Start user code for adding. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/general/r_smc_entry.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/general/r_smc_entry.h
new file mode 100644
index 00000000000..091e32445c4
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/general/r_smc_entry.h
@@ -0,0 +1,54 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2016, 2017 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name : r_smc_entry.h
+* Version : 1.2.0
+* Device(s) : R5F565NEDxFP
+* Description : SMC platform header file.
+* Creation Date: 2018-08-29
+***********************************************************************************************************************/
+
+#ifndef SMC_PLATFORM_H
+#define SMC_PLATFORM_H
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_macrodriver.h"
+
+/***********************************************************************************************************************
+Macro definitions (Register bit)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Global functions
+***********************************************************************************************************************/
+/* Start user code for function. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#endif
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/general/r_smc_interrupt.c b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/general/r_smc_interrupt.c
new file mode 100644
index 00000000000..00fdf5e63b4
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/general/r_smc_interrupt.c
@@ -0,0 +1,44 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2016, 2017 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name : r_smc_interrupt.c
+* Version : 1.1.0
+* Device(s) : R5F565NEDxFP
+* Description : This file implements interrupt setting
+* Creation Date: 2018-08-29
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_smc_interrupt.h"
+#include "platform.h"
+
+/***********************************************************************************************************************
+* Function Name: R_Interrupt_Create
+* Description : This function Used to set the fast interrupt or group interrupt
+* Arguments : None
+* Return Value : None
+***********************************************************************************************************************/
+
+void R_Interrupt_Create(void)
+{
+ /* No fast interrupt and group settings have been configured in the Interrupts tab. */
+}
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/general/r_smc_interrupt.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/general/r_smc_interrupt.h
new file mode 100644
index 00000000000..e074c11bcf2
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/general/r_smc_interrupt.h
@@ -0,0 +1,290 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2016, 2017 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name : r_smc_interrupt.h
+* Version : 1.1.0
+* Device(s) : R5F565NEDxFP
+* Description : This file implements interrupt setting.
+* Creation Date: 2018-08-29
+***********************************************************************************************************************/
+
+#ifndef SMC_INTERRUPT_H
+#define SMC_INTERRUPT_H
+
+/***********************************************************************************************************************
+Macro definitions (Register bit)
+***********************************************************************************************************************/
+
+/* Priority level of interrupt source.
+ * These macro definitions are used to set the IPR register directly
+ */
+#define _00_ICU_PRIORITY_LEVEL0 (0x00U) /* Level 0 (disabled) */
+#define _01_ICU_PRIORITY_LEVEL1 (0x01U) /* Level 1 */
+#define _02_ICU_PRIORITY_LEVEL2 (0x02U) /* Level 2 */
+#define _03_ICU_PRIORITY_LEVEL3 (0x03U) /* Level 3 */
+#define _04_ICU_PRIORITY_LEVEL4 (0x04U) /* Level 4 */
+#define _05_ICU_PRIORITY_LEVEL5 (0x05U) /* Level 5 */
+#define _06_ICU_PRIORITY_LEVEL6 (0x06U) /* Level 6 */
+#define _07_ICU_PRIORITY_LEVEL7 (0x07U) /* Level 7 */
+#define _08_ICU_PRIORITY_LEVEL8 (0x08U) /* Level 8 */
+#define _09_ICU_PRIORITY_LEVEL9 (0x09U) /* Level 9 */
+#define _0A_ICU_PRIORITY_LEVEL10 (0x0AU) /* Level 10 */
+#define _0B_ICU_PRIORITY_LEVEL11 (0x0BU) /* Level 11 */
+#define _0C_ICU_PRIORITY_LEVEL12 (0x0CU) /* Level 12 */
+#define _0D_ICU_PRIORITY_LEVEL13 (0x0DU) /* Level 13 */
+#define _0E_ICU_PRIORITY_LEVEL14 (0x0EU) /* Level 14 */
+#define _0F_ICU_PRIORITY_LEVEL15 (0x0FU) /* Level 15 */
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+/* The macro definitions below list the full set of priority levels as selected in the Interrupts tab
+ * Please do not modify this file manually
+ */
+#define ICU_BSC_BUSERR_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_RAM_RAMERR_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_FCU_FIFERR_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_FCU_FRDYI_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_SWINT2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_SWINT_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CMT0_CMI0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CMT1_CMI1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CMTW0_CMWI0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CMTW1_CMWI1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_USB0_D0FIFO0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_USB0_D1FIFO0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_RSPI0_SPRI0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_RSPI0_SPTI0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_RSPI1_SPRI1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_RSPI1_SPTI1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_QSPI_SPRI_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_QSPI_SPTI_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SDHI_SBFAI_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MMCIF_MBFAI_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_RIIC1_RXI1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_RIIC1_TXI1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_RIIC0_RXI0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_RIIC0_TXI0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_RIIC2_RXI2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_RIIC2_TXI2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI0_RXI0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI0_TXI0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI1_RXI1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI1_TXI1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI2_RXI2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI2_TXI2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_IRQ0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_IRQ1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_IRQ2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_IRQ3_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_IRQ4_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_IRQ5_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_IRQ6_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_IRQ7_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_IRQ8_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_IRQ9_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_IRQ10_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_IRQ11_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_IRQ12_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_IRQ13_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_IRQ14_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_IRQ15_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI3_RXI3_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI3_TXI3_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI4_RXI4_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI4_TXI4_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI5_RXI5_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI5_TXI5_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI6_RXI6_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI6_TXI6_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_LVD1_LVD1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_LVD2_LVD2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_USB0_USBR0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_RTC_ALM_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_RTC_PRD_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_IWDT_IWUNI_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_WDT_WUNI_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_PDC_PCDFI_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI7_RXI7_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI7_TXI7_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI8_RXI8_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI8_TXI8_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI9_RXI9_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI9_TXI9_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI10_RXI10_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI10_TXI10_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_GROUPBE0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_GROUPBL2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_RSPI2_SPRI2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_RSPI2_SPTI2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_GROUPBL0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_GROUPBL1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_GROUPAL0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ICU_GROUPAL1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI11_RXI11_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI11_TXI11_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI12_RXI12_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_SCI12_TXI12_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_DMAC_DMAC0I_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_DMAC_DMAC1I_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_DMAC_DMAC2I_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_DMAC_DMAC3I_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_DMAC_DMAC74I_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_OST_OSTDI_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_EXDMAC_EXDMAC0I_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_EXDMAC_EXDMAC1I_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CMT2_CMI2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CMT3_CMI3_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU0_TGI0A_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU0_TGI0B_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU0_TGI0C_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU0_TGI0D_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU0_TCI0V_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU1_TGI1B_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU1_TCI1V_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU1_TCI1U_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU2_TGI2A_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU2_TGI2B_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU2_TCI2V_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU2_TCI2U_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU3_TGI3A_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU3_TGI3B_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU1_TGI1A_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU3_TGI3C_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TMR0_CMIA0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TMR0_CMIB0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TMR0_OVI0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TMR1_CMIA1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TMR1_CMIB1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TMR1_OVI1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TMR2_CMIA2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TMR2_CMIB2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TMR2_OVI2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TMR3_CMIA3_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TMR3_CMIB3_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TMR3_OVI3_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU3_TGI3D_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU3_TCI3V_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU4_TGI4A_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU4_TGI4B_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU4_TCI4V_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU4_TCI4U_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU5_TGI5A_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU5_TGI5B_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU5_TCI5V_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TPU5_TCI5U_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CMTW0_IC0I0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CMTW0_IC1I0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CMTW0_OC0I0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CMTW0_OC1I0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CMTW1_IC0I1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CMTW1_IC1I1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CMTW1_OC0I1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CMTW1_OC1I1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_RTC_CUP_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CAN0_RXF0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CAN0_TXF0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CAN0_RXM0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CAN0_TXM0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CAN1_RXF1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CAN1_TXF1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CAN1_RXM1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_CAN1_TXM1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_USB0_USBI0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_S12AD_S12ADI_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_S12AD_S12GBADI_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_S12AD_S12GCADI_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_S12AD1_S12ADI1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_S12AD1_S12GBADI1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_S12AD1_S12GCADI1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_PERIB_INTB192_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ELC_ELSR18I_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_ELC_ELSR19I_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TSIP_PROC_BUSY_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TSIP_ROMOK_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TSIP_LONG_PLG_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TSIP_TEST_BUSY_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TSIP_WRRDY0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TSIP_WRRDY1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TSIP_WRRDY4_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TSIP_RDRDY0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TSIP_RDRDY1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TSIP_INTEGRATE_WRRDY_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_TSIP_INTEGRATE_RDRDY_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_PERIB_INTB206_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_PERIB_INTB207_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU1_TGIA1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU0_TGIA0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU0_TGIB0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU0_TGIC0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU0_TGID0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU0_TCIV0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU0_TGIE0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU0_TGIF0_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU1_TGIB1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU1_TCIV1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU1_TCIU1_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU2_TGIA2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU2_TGIB2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU2_TCIV2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU2_TCIU2_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU3_TGIA3_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU3_TGIB3_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU3_TGIC3_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU3_TGID3_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU3_TCIV3_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU4_TGIA4_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU4_TGIB4_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU4_TGIC4_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU4_TGID4_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU4_TCIV4_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU5_TGIU5_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU5_TGIV5_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU5_TGIW5_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU6_TGIA6_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU6_TGIB6_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU6_TGIC6_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU6_TGID6_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU6_TCIV6_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU7_TGIA7_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU7_TGIB7_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU7_TGIC7_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU7_TGID7_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU7_TCIV7_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU8_TGIA8_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU8_TGIB8_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU8_TGIC8_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU8_TGID8_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_MTU8_TCIV8_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_PERIA_INTA251_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_PERIA_INTA252_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_PERIA_INTA253_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_PERIA_INTA254_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+#define ICU_PERIA_INTA255_PRIORITY _0F_ICU_PRIORITY_LEVEL15
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Global functions
+***********************************************************************************************************************/
+void R_Interrupt_Create(void);
+#endif
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/r_config/r_bsp_config.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/r_config/r_bsp_config.h
new file mode 100644
index 00000000000..81db14345eb
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/r_config/r_bsp_config.h
@@ -0,0 +1,560 @@
+/* Generated configuration header file - do not edit */
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2017 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : r_bsp_config_reference.h
+* Device(s) : RX65N
+* Description : The file r_bsp_config.h is used to configure your BSP. r_bsp_config.h should be included
+* somewhere in your package so that the r_bsp code has access to it. This file (r_bsp_config_reference.h)
+* is just a reference file that the user can use to make their own r_bsp_config.h file.
+************************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 15.05.2017 1.00 First Release
+* : 01.12.2017 1.01 Added the following macro definition.
+* - BSP_CFG_EBMAPCR_1ST_PRIORITY
+* - BSP_CFG_EBMAPCR_2ND_PRIORITY
+* - BSP_CFG_EBMAPCR_3RD_PRIORITY
+* - BSP_CFG_EBMAPCR_4TH_PRIORITY
+* - BSP_CFG_EBMAPCR_5TH_PRIORITY
+* : 01.07.2018 1.02 Added the following macro definition.
+* - BSP_CFG_CONFIGURATOR_SELECT
+* Add RTOS support. FreeRTOS. Define a timer for RTOS.
+***********************************************************************************************************************/
+#ifndef R_BSP_CONFIG_REF_HEADER_FILE
+#define R_BSP_CONFIG_REF_HEADER_FILE
+
+/***********************************************************************************************************************
+Configuration Options
+***********************************************************************************************************************/
+
+/* NOTE:
+ The default settings are the same as when using RSKRX65N-2MB.
+ Change to the settings for the user board.
+*/
+
+/* Start up select
+ 0 = Enable BSP startup program.
+ 1 = Disable BSP startup program. (e.g. Using user startup program.)
+*/
+#define BSP_CFG_STARTUP_DISABLE (0)
+
+/* Enter the product part number for your MCU. This information will be used to obtain information about your MCU such
+ as package and memory size.
+ To help parse this information, the part number will be defined using multiple macros.
+ R 5 F 56 5N E D D FP
+ | | | | | | | | | Macro Name Description
+ | | | | | | | | |__BSP_CFG_MCU_PART_PACKAGE = Package type, number of pins, and pin pitch
+ | | | | | | | |____not used = Products with wide temperature range
+ | | | | | | |______BSP_CFG_MCU_PART_ENCRYPTION_INCLUDED = Encryption module included/not included
+ | | | | | |________BSP_CFG_MCU_PART_MEMORY_SIZE = ROM, RAM, and Data Flash Capacity
+ | | | | |___________BSP_CFG_MCU_PART_GROUP = Group name
+ | | | |______________BSP_CFG_MCU_PART_SERIES = Series name
+ | | |________________BSP_CFG_MCU_PART_MEMORY_TYPE = Type of memory (Flash, ROMless)
+ | |__________________not used = Renesas MCU
+ |____________________not used = Renesas semiconductor product.
+ */
+
+/* Package type. Set the macro definition based on values below:
+ Character(s) = Value for macro = Package Type/Number of Pins/Pin Pitch
+ FC = 0x0 = LFQFP/176/0.50
+ BG = 0x1 = LFBGA/176/0.80
+ LC = 0x2 = TFLGA/177/0.50
+ FB = 0x3 = LFQFP/144/0.50
+ LK = 0x4 = TFLGA/145/0.50
+ FP = 0x5 = LFQFP/100/0.50
+ LJ = 0xA = TFLGA/100/0.65
+*/
+#define BSP_CFG_MCU_PART_PACKAGE (0x5) // <-- Updated by GUI. Do not edit this value manually
+
+/* Whether Encryption and SDHI/SDSI are included or not.
+ Character(s) = Value for macro = Description
+ A = false = Encryption module not included, SDHI/SDSI module not included
+ B = false = Encryption module not included, SDHI/SDSI module included
+ D = false = Encryption module not included, SDHI/SDSI module included, dual-bank structure
+ E = true = Encryption module included, SDHI/SDSI module not included
+ F = true = Encryption module included, SDHI/SDSI module included
+ H = true = Encryption module included, SDHI/SDSI module included, dual-bank structure
+*/
+#define BSP_CFG_MCU_PART_ENCRYPTION_INCLUDED (false) // <-- Updated by GUI. Do not edit this value manually
+
+/* ROM, RAM, and Data Flash Capacity.
+ Character(s) = Value for macro = ROM Size/Ram Size/Data Flash Size
+ 4 = 0x4 = 512KB/256KB/Not equipped
+ 7 = 0x7 = 768KB/256KB/Not equipped
+ 9 = 0x9 = 1MB/256KB/Not equipped
+ C = 0xC = 1.5MB/640KB/32KB
+ E = 0xE = 2MB/640KB/32KB
+ NOTE: When the RAM capacity is 640KB, the RAM areas are not contiguous.
+*/
+#define BSP_CFG_MCU_PART_MEMORY_SIZE (0xE) // <-- Updated by GUI. Do not edit this value manually
+
+/* Group name.
+ Character(s) = Value for macro = Description
+ 5N/51 = 0x0 = RX65N Group/RX651 Group
+*/
+#define BSP_CFG_MCU_PART_GROUP (0x0) // <-- Updated by GUI. Do not edit this value manually
+
+/* Series name.
+ Character(s) = Value for macro = Description
+ 56 = 0x0 = RX600 Series
+*/
+#define BSP_CFG_MCU_PART_SERIES (0x0) // <-- Updated by GUI. Do not edit this value manually
+
+/* Memory type.
+ Character(s) = Value for macro = Description
+ F = 0x0 = Flash memory version
+*/
+#define BSP_CFG_MCU_PART_MEMORY_TYPE (0x0) // <-- Updated by GUI. Do not edit this value manually
+
+/* Heap size in bytes.
+ To disable the heap you must follow these steps:
+ 1) Set this macro (BSP_CFG_HEAP_BYTES) to 0.
+ 2) Set the macro BSP_CFG_IO_LIB_ENABLE to 0.
+ 3) Disable stdio from being built into the project library. This is done by going into the Renesas RX Toolchain
+ settings and choosing the Standard Library section. After that choose 'Standard Library' for Category in HEW or
+ choose 'Contents' in E2Studio. This will present a list of modules that can be included. Uncheck the box for
+ stdio.h.
+*/
+#define BSP_CFG_HEAP_BYTES (0x2000)
+
+/* Initializes C input & output library functions.
+ 0 = Disable I/O library initialization in resetprg.c. If you are not using stdio then use this value.
+ 1 = Enable I/O library initialization in resetprg.c. This is default and needed if you are using stdio. */
+#define BSP_CFG_IO_LIB_ENABLE (0)
+
+/* If desired the user may redirect the stdio charget() and/or charput() functions to their own respective functions
+ by enabling below and providing and replacing the my_sw_... function names with the names of their own functions. */
+#define BSP_CFG_USER_CHARGET_ENABLED (0)
+#define BSP_CFG_USER_CHARGET_FUNCTION my_sw_charget_function
+
+#define BSP_CFG_USER_CHARPUT_ENABLED (0)
+#define BSP_CFG_USER_CHARPUT_FUNCTION my_sw_charput_function
+
+/* After reset MCU will operate in Supervisor mode. To switch to User mode, set this macro to '1'. For more information
+ on the differences between these 2 modes see the CPU >> Processor Mode section of your MCU's hardware manual.
+ 0 = Stay in Supervisor mode.
+ 1 = Switch to User mode.
+*/
+#define BSP_CFG_RUN_IN_USER_MODE (0)
+
+/* Clock source select (CKSEL).
+ 0 = Low Speed On-Chip Oscillator (LOCO)
+ 1 = High Speed On-Chip Oscillator (HOCO)
+ 2 = Main Clock Oscillator
+ 3 = Sub-Clock Oscillator
+ 4 = PLL Circuit
+*/
+#define BSP_CFG_CLOCK_SOURCE (4) // <-- Updated by GUI. Do not edit this value manually
+
+/* Main clock Oscillator Switching (MOSEL).
+ 0 = Resonator
+ 1 = External clock input
+*/
+#define BSP_CFG_MAIN_CLOCK_SOURCE (0) // <-- Updated by GUI. Do not edit this value manually
+
+/* The sub-clock oscillation control for using the RTC.
+ When '1' is selected, the registers related to RTC are initialized and the sub-clock oscillator is operated.
+ 0 = The RTC is not to be used.
+ 1 = The RTC is to be used.
+*/
+#define BSP_CFG_RTC_ENABLE (0) // <-- Updated by GUI. Do not edit this value manually
+
+/* Sub-Clock Oscillator Drive Capacity Control (RTCDV).
+ 0 = Drive capacity for standard CL.
+ 1 = Drive capacity for low CL.
+*/
+#define BSP_CFG_SOSC_DRV_CAP (0) // <-- Updated by GUI. Do not edit this value manually //standard CL by default
+
+/* Clock configuration options.
+ The input clock frequency is specified and then the system clocks are set by specifying the multipliers used. The
+ multiplier settings are used to set the clock registers in resetprg.c. If a 24MHz clock is used and the
+ ICLK is 120MHz, PCLKA is 120MHz, PCLKB is 60MHz, PCLKC is 60MHz, PCLKD is 60MHz, FCLK is 60MHz, USB Clock is 48MHz,
+ and BCLK is 120MHz then the settings would be:
+
+ BSP_CFG_XTAL_HZ = 24000000
+ BSP_CFG_PLL_DIV = 1 (no division)
+ BSP_CFG_PLL_MUL = 10.0 (24MHz x 10.0 = 240MHz)
+ BSP_CFG_ICK_DIV = 2 : System Clock (ICLK) =
+ (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_ICK_DIV) = 120MHz
+ BSP_CFG_PCKA_DIV = 2 : Peripheral Clock A (PCLKA) =
+ (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKA_DIV) = 120MHz
+ BSP_CFG_PCKB_DIV = 4 : Peripheral Clock B (PCLKB) =
+ (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKB_DIV) = 60MHz
+ BSP_CFG_PCKC_DIV = 4 : Peripheral Clock C (PCLKC) =
+ (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKC_DIV) = 60MHz
+ BSP_CFG_PCKD_DIV = 4 : Peripheral Clock D (PCLKD) =
+ (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKD_DIV) = 60MHz
+ BSP_CFG_FCK_DIV = 4 : Flash IF Clock (FCLK) =
+ (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_FCK_DIV) = 60MHz
+ BSP_CFG_BCK_DIV = 2 : External Bus Clock (BCK) =
+ (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_BCK_DIV) = 120MHz
+ BSP_CFG_UCK_DIV = 5 : USB Clock (UCLK) =
+ (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_UCK_DIV) = 48MHz
+*/
+
+/* Input clock frequency in Hz (XTAL or EXTAL). */
+#define BSP_CFG_XTAL_HZ (12000000) // <-- Updated by GUI. Do not edit this value manually
+
+/* The HOCO can operate at several different frequencies. Choose which one using the macro below.
+ Available frequency settings:
+ 0 = 16MHz (default)
+ 1 = 18MHz
+ 2 = 20MHz
+*/
+#define BSP_CFG_HOCO_FREQUENCY (0) // <-- Updated by GUI. Do not edit this value manually
+
+/* PLL clock source (PLLSRCEL). Choose which clock source to input to the PLL circuit.
+ Available clock sources:
+ 0 = Main clock (default)
+ 1 = HOCO
+*/
+#define BSP_CFG_PLL_SRC (0) // <-- Updated by GUI. Do not edit this value manually
+
+/* PLL Input Frequency Division Ratio Select (PLIDIV).
+ Available divisors = /1 (no division), /2, /3
+*/
+#define BSP_CFG_PLL_DIV (1) // <-- Updated by GUI. Do not edit this value manually
+
+/* PLL Frequency Multiplication Factor Select (STC).
+ Available multipliers = x10.0 to x30.0 in 0.5 increments (e.g. 10.0, 10.5, 11.0, 11.5, ..., 29.0, 29.5, 30.0)
+*/
+#define BSP_CFG_PLL_MUL (20.0) // <-- Updated by GUI. Do not edit this value manually
+
+/* System Clock Divider (ICK).
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define BSP_CFG_ICK_DIV (2) // <-- Updated by GUI. Do not edit this value manually
+
+/* Peripheral Module Clock A Divider (PCKA).
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define BSP_CFG_PCKA_DIV (2) // <-- Updated by GUI. Do not edit this value manually
+
+/* Peripheral Module Clock B Divider (PCKB).
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define BSP_CFG_PCKB_DIV (4) // <-- Updated by GUI. Do not edit this value manually
+
+/* Peripheral Module Clock C Divider (PCKC).
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define BSP_CFG_PCKC_DIV (4) // <-- Updated by GUI. Do not edit this value manually
+
+/* Peripheral Module Clock D Divider (PCKD).
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define BSP_CFG_PCKD_DIV (4) // <-- Updated by GUI. Do not edit this value manually
+
+/* External Bus Clock Divider (BCLK).
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define BSP_CFG_BCK_DIV (2) // <-- Updated by GUI. Do not edit this value manually
+
+/* Flash IF Clock Divider (FCK).
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define BSP_CFG_FCK_DIV (4) // <-- Updated by GUI. Do not edit this value manually
+
+/* USB Clock Divider Select.
+ Available divisors = /2, /3, /4, /5
+*/
+#define BSP_CFG_UCK_DIV (5) // <-- Updated by GUI. Do not edit this value manually
+
+/* Configure BCLK output pin (only effective when external bus enabled)
+ Values 0=no output, 1 = BCK frequency, 2= BCK/2 frequency
+*/
+#define BSP_CFG_BCLK_OUTPUT (0) // <-- Updated by GUI. Do not edit this value manually
+
+/* Configure SDCLK output pin (only effective when external bus enabled)
+ Values 0=no output, 1 = BCK frequency
+*/
+#define BSP_CFG_SDCLK_OUTPUT (0) // <-- Updated by GUI. Do not edit this value manually
+
+/* Main Clock Oscillator Wait Time (MOSCWTCR).
+ The value of MOSCWTCR register required for correspondence with the waiting time required to secure stable oscillation
+ by the main clock oscillator is obtained by using the maximum frequency for fLOCO in the formula below.
+
+ BSP_CFG_MOSC_WAIT_TIME > (tMAINOSC * (fLOCO_max) + 16)/32
+ (tMAINOSC: main clock oscillation stabilization time; fLOCO_max: maximum frequency for fLOCO)
+
+ If tMAINOSC is 9.98 ms and fLOCO_max is 264 kHz (the period is 1/3.78 us), the formula gives
+ BSP_CFG_MOSC_WAIT_TIME > (9.98 ms * (264 kHZ) + 16)/32 = 82.83, so set the BSP_CFG_MOSC_WAIT_TIME to 83(53h).
+
+ NOTE: The waiting time is not required when an external clock signal is input for the main clock oscillator.
+ Set the BSP_CFG_MOSC_WAIT_TIME to 00h.
+*/
+#define BSP_CFG_MOSC_WAIT_TIME (0x53) // <-- Updated by GUI. Do not edit this value manually
+
+/* Sub-Clock Oscillator Wait Time (SOSCWTCR).
+ The value of SOSCWTCR register required for correspondence with the expected time to secure settling of oscillation
+ by the sub-clock oscillator is obtained by using the maximum frequency for fLOCO in the formula below.
+
+ BSP_CFG_SOSC_WAIT_TIME > (tSUBOSC * (fLOCO_max) + 16)/16384
+ (tSUBOSC: sub-clock oscillation stabilization time; fLOCO_max: maximum frequency for fLOCO)
+
+ If tSUBOSC is 2 s and fLOCO is 264 kHz (the period is 1/3.78 us), the formula gives
+ BSP_CFG_SOSC_WAIT_TIME > (2 s * (264 kHz) +16)/16384 = 32.22, so set the BSP_CFG_SOSC_WAIT_TIME bits to 33(21h).
+*/
+#define BSP_CFG_SOSC_WAIT_TIME (0x21) // <-- Updated by GUI. Do not edit this value manually
+
+/* ROM Cache Enable Register (ROMCE).
+ 0 = ROM cache operation disabled.
+ 1 = ROM cache operation enabled.
+*/
+#define BSP_CFG_ROM_CACHE_ENABLE (0)
+
+/* Configure WDT and IWDT settings.
+ OFS0 - Option Function Select Register 0
+ b31:b29 Reserved When reading, these bits return the value written by the user. The write value should be 1.
+ b28 WDTRSTIRQS - WDT Reset Interrupt Request - What to do on underflow (0=take interrupt, 1=reset MCU)
+ b27:b26 WDTRPSS - WDT Window Start Position Select - (0=25%, 1=50%, 2=75%, 3=100%,don't use)
+ b25:b24 WDTRPES - WDT Window End Position Select - (0=75%, 1=50%, 2=25%, 3=0%,don't use)
+ b23:b20 WDTCKS - WDT Clock Frequency Division Ratio - (1=PCLKB/4, 4=PCLKB/64, 0xF=PCLKB/128, 6=PCLKB/256,
+ 7=PCLKB/2048, 8=PCLKB/8192)
+ b19:b18 WDTTOPS - WDT Timeout Period Select (0=1024 cycles, 1=4096, 2=8192, 3=16384)
+ b17 WDTSTRT - WDT Start Mode Select - (0=auto-start after reset, 1=halt after reset)
+ b16:b15 Reserved (set to 1)
+ b14 IWDTSLCSTP - IWDT Sleep Mode Count Stop Control - (0=can't stop count, 1=stop w/some low power modes)
+ b13 Reserved (set to 1)
+ b12 IWDTRSTIRQS - IWDT Reset Interrupt Request - What to do on underflow (0=take interrupt, 1=reset MCU)
+ b11:b10 IWDTRPSS - IWDT Window Start Position Select - (0=25%, 1=50%, 2=75%, 3=100%,don't use)
+ b9:b8 IWDTRPES - IWDT Window End Position Select - (0=75%, 1=50%, 2=25%, 3=0%,don't use)
+ b7:b4 IWDTCKS - IWDT Clock Frequency Division Ratio - (0=none, 2=/16, 3 = /32, 4=/64, 0xF=/128, 5=/256)
+ b3:b2 IWDTTOPS - IWDT Timeout Period Select - (0=1024 cycles, 1=4096, 2=8192, 3=16384)
+ b1 IWDTSTRT - IWDT Start Mode Select - (0=auto-start after reset, 1=halt after reset)
+ b0 Reserved (set to 1)
+*/
+#define BSP_CFG_OFS0_REG_VALUE (0xFFFFFFFF) // <-- Updated by GUI. Do not edit this value manually //Disable by default
+
+/* Configure whether voltage detection 0 circuit and HOCO are enabled after reset.
+ OFS1 - Option Function Select Register 1
+ b31:b9 Reserved (set to 1)
+ b8 HOCOEN - Enable/disable HOCO oscillation after a reset (0=enable, 1=disable)
+ b7:b3 Reserved When reading, these bits return the value written by the user. The write value should be 1.
+ b2 LVDAS - Voltage Detection 0 circuit start (1=monitoring disabled)
+ b1:b0 VDSEL - Voltage Detection 0 level select (1=2.94v, 2=2.87v, 3=2.80v)
+ NOTE: If HOCO oscillation is enabled by OFS1.HOCOEN, HOCO frequency is 16MHz.
+ BSP_CFG_HOCO_FREQUENCY should be default value.
+*/
+#define BSP_CFG_OFS1_REG_VALUE (0xFFFFFFFF) // <-- Updated by GUI. Do not edit this value manually //Disable by default
+
+/* Trusted memory is facility to prevent the reading of blocks 8 and 9 and blocks 46 and 47 (in dual mode) in
+ the code flash memory by third party software. This feature is disabled by default.
+ TMEF - TM Enable Flag Register
+ b31 Reserved (set to 1)
+ b30:b28 TMEFDB - Dual-Bank TM Enable - 000: The TM function in the address range from FFEE 0000h to
+ FFEE FFFFh is enabled in dual mode.
+ - 111: The TM function in the address range from FFEE 0000h to
+ FFEE FFFFh is disabled in dual mode.
+ b27 Reserved (set to 1)
+ b26:b24 TMEFF - TM Enable - 000: TM function is enabled.
+ - 111: TM function is disabled.
+ b23:b0 Reserved (set to 1)
+ NOTE: If the dual bank function has not been incorporated in a device,
+ TMEFDB bits [b30:b26] are reserved area.
+*/
+#define BSP_CFG_TRUSTED_MODE_FUNCTION (0xFFFFFFFF) //Disable by default
+
+/* Configure FAW register is used to set the write protection flag and boot area select flag
+ for setting the flash access window startaddress and flash access window end address.
+ FAW - Flash Access Window Setting Register
+ b31 BTFLG - Boot Area Select Flag - 0: FFFF C000h to FFFF DFFFh are used as the boot area
+ - 1: FFFF E000h to FFFF FFFFh are used as the boot area
+ b30:b28 Reserved - When reading, these bits return the value written by the user.The write value should be 1.
+ b27:b16 FAWE - Flash Access Window End Address - Flash access window end address
+ b15 FSPR - Access Window Protection Flag - 0: With protection (P/E disabled)
+ - 1: Without protection (P/E enabled)
+ b14:b12 Reserved - When reading, these bits return the value written by the user.The write value should be 1.
+ b11:b0 FAWS - Flash Access Window Start Address - Flash access window start address
+ NOTE: Once 0 is written to this bit, the bit can never be restored to 1.
+ Therefore, the access window and the BTFLG bit never be set again or the TM function
+ never be disabled once it has been enabled.
+ Exercise extra caution when handling the FSPR bit.
+*/
+#define BSP_CFG_FAW_REG_VALUE (0xFFFFFFFF) //Disable by default
+
+/* The ROM code protection register is a function to prohibit reading from or programming to the flash memory
+ when the flash programmer is used during off-board programming.
+ ROMCODE - ROM Code Protection Register
+ b31:b0 ROM Code - 0000 0000h: ROM code protection enabled (ROM code protection 1).
+ 0000 0001h: ROM code protection enabled (ROM code protection 2).
+ Other than above: ROM code protection disabled.
+ Note. The ROMCODE register should be set in 32-bit units.
+*/
+#define BSP_CFG_ROMCODE_REG_VALUE (0xFFFFFFFF) //Disable by default
+
+/* Select the bank mode of dual-bank function of the code flash memory.
+ 0 = Dual mode.
+ 1 = Linear mode.
+ NOTE: If the dual bank function has been incorporated in a device, select the bank mode in this macro.
+ Default setting of the bank mode is linear mode.
+ If the dual bank function has not been incorporated in a device, this macro should be 1.
+*/
+#define BSP_CFG_CODE_FLASH_BANK_MODE (1) //Linear mode by default
+
+/* Select the startup bank of the program when dual bank function is in dual mode.
+ 0 = The address range of bank 1 from FFE00000h to FFEFFFFFh and bank 0 from FFF00000h to FFFFFFFFh.
+ 1 = The address range of bank 1 from FFF00000h to FFFFFFFFh and bank 0 from FFE00000h to FFEFFFFFh.
+ NOTE: If the dual bank function has been incorporated in a device, select the start bank in this macro.
+ Default setting of the start bank is bank0.
+ If the dual bank function has not been incorporated in a device, this macro should be 0.
+*/
+#define BSP_CFG_CODE_FLASH_START_BANK (0) //Bank0 by default
+
+/* This macro lets other modules no if a RTOS is being used.
+ 0 = RTOS is not used.
+ 1 = FreeRTOS is used.
+ 2 = embOS is used.(This is not available.)
+ 3 = MicroC_OS is used.(This is not available.)
+ 4 = RI600V4 or RI600PX is used.(This is not available.)
+*/
+/* As of today, we need a workaround to avoid the problem that the Smart Configurator does not have such GUI
+ yet and the BSP_CFG_RTOS_USED here is set to (0) every time of code generation by the Smart Configurator.
+ The BSP_CFG_RTOS_USED is set to (1) in the r_bsp.h instead of here so that the setting of here is ignored.
+*/
+#if !defined(BSP_CFG_RTOS_USED) || (BSP_CFG_RTOS_USED == 0)
+#if defined(BSP_CFG_RTOS_USED)
+#undef BSP_CFG_RTOS_USED
+#endif
+#define BSP_CFG_RTOS_USED (0) // <-- Updated by GUI. Do not edit this value manually
+#endif
+
+/* This macro is used to select which CMT channel used for system timer of RTOS.
+ * The setting of this macro is only valid if the macro BSP_CFG_RTOS_USED is set to a value other than 0. */
+#if (BSP_CFG_RTOS_USED != 0)
+/* Setting value.
+ * 0 = CMT channel 0 used for system timer of RTOS (recommended to be used for RTOS).
+ * 1 = CMT channel 1 used for system timer of RTOS.
+ * 2 = CMT channel 2 used for system timer of RTOS.
+ * 3 = CMT channel 3 used for system timer of RTOS.
+ * Others = Invalid. */
+#define BSP_CFG_RTOS_SYSTEM_TIMER (0)
+#endif
+
+/* By default modules will use global locks found in mcu_locks.c. If the user is using a RTOS and would rather use its
+ locking mechanisms then they can change this macro.
+ NOTE: If '1' is chosen for this macro then the user must also change the next macro 'BSP_CFG_USER_LOCKING_TYPE'.
+ 0 = Use default locking (non-RTOS)
+ 1 = Use user defined locking mechanism.
+*/
+#define BSP_CFG_USER_LOCKING_ENABLED (0)
+
+/* If the user decides to use their own locking mechanism with FIT modules then they will need to redefine the typedef
+ that is used for the locks. If the user is using a RTOS then they would likely redefine the typedef to be
+ a semaphore/mutex type of their RTOS. Use the macro below to set the type that will be used for the locks.
+ NOTE: If BSP_CFG_USER_LOCKING_ENABLED == 0 then this typedef is ignored.
+ NOTE: Do not surround the type with parentheses '(' ')'.
+*/
+#define BSP_CFG_USER_LOCKING_TYPE bsp_lock_t
+
+/* If the user decides to use their own locking mechanism with FIT modules then they will need to define the functions
+ that will handle the locking and unlocking. These functions should be defined below.
+ If BSP_CFG_USER_LOCKING_ENABLED is != 0:
+ R_BSP_HardwareLock(mcu_lock_t hw_index) will call BSP_CFG_USER_LOCKING_HW_LOCK_FUNCTION(mcu_lock_t hw_index)
+ R_BSP_HardwareUnlock(mcu_lock_t hw_index) will call BSP_CFG_USER_LOCKING_HW_UNLOCK_FUNCTION(mcu_lock_t hw_index)
+ NOTE:With these functions the index into the array holding the global hardware locks is passed as the parameter.
+ R_BSP_SoftwareLock(BSP_CFG_USER_LOCKING_TYPE * plock) will call
+ BSP_CFG_USER_LOCKING_SW_LOCK_FUNCTION(BSP_CFG_USER_LOCKING_TYPE * plock)
+ R_BSP_SoftwareUnlock(BSP_CFG_USER_LOCKING_TYPE * plock) will call
+ BSP_CFG_USER_LOCKING_SW_UNLOCK_FUNCTION(BSP_CFG_USER_LOCKING_TYPE * plock)
+ NOTE:With these functions the actual address of the lock to use is passed as the parameter.
+ NOTE: These functions must return a boolean. If lock was obtained or released successfully then return true. Else,
+ return false.
+ NOTE: If BSP_CFG_USER_LOCKING_ENABLED == 0 then this typedef is ignored.
+ NOTE: Do not surround the type with parentheses '(' ')'.
+*/
+#define BSP_CFG_USER_LOCKING_HW_LOCK_FUNCTION my_hw_locking_function
+#define BSP_CFG_USER_LOCKING_HW_UNLOCK_FUNCTION my_hw_unlocking_function
+#define BSP_CFG_USER_LOCKING_SW_LOCK_FUNCTION my_sw_locking_function
+#define BSP_CFG_USER_LOCKING_SW_UNLOCK_FUNCTION my_sw_unlocking_function
+
+/* If the user would like to determine if a warm start reset has occurred, then they may enable one or more of the
+ * following callback definitions AND provide a call back function name for the respective callback
+ * function (to be defined by the user). Setting BSP_CFG_USER_WARM_START_CALLBACK_PRE_INITC_ENABLED = 1 will result
+ * in a callback to the user defined my_sw_warmstart_prec_function just prior to the initialization of the C
+ * runtime environment by resetprg.
+ *
+ * Setting BSP_CFG_USER_WARM_START_CALLBACK_POST_INITC_ENABLED = 1 will result in a callback to the user defined
+ * my_sw_warmstart_postc_function just after the initialization of the C runtime environment by resetprg.
+ */
+#define BSP_CFG_USER_WARM_START_CALLBACK_PRE_INITC_ENABLED (0)
+#define BSP_CFG_USER_WARM_START_PRE_C_FUNCTION my_sw_warmstart_prec_function
+
+#define BSP_CFG_USER_WARM_START_CALLBACK_POST_INITC_ENABLED (0)
+#define BSP_CFG_USER_WARM_START_POST_C_FUNCTION my_sw_warmstart_postc_function
+
+/* By default FIT modules will check input parameters to be valid. This is helpful during development but some users
+ will want to disable this for production code. The reason for this would be to save execution time and code space.
+ This macro is a global setting for enabling or disabling parameter checking. Each FIT module will also have its
+ own local macro for this same purpose. By default the local macros will take the global value from here though
+ they can be overridden. Therefore, the local setting has priority over this global setting. Disabling parameter
+ checking should only used when inputs are known to be good and the increase in speed or decrease in code space is
+ needed.
+ 0 = Global setting for parameter checking is disabled.
+ 1 = Global setting for parameter checking is enabled (Default).
+*/
+#define BSP_CFG_PARAM_CHECKING_ENABLE (1)
+
+/* The extended bus master has five transfer sources: EDMAC, GLCDC-GRA1 (GLCDC graphics 1 data read), GLCDCGRA2 (GLCDC
+ graphics 2 data read), DRW2D-TX (DRW2D texture data read), and DRW2D-FB (DRW2D frame buffer data read write and
+ display list data read).
+ The default priority order in bsp is below
+ GLCDC-GRA1 > GLCDC-GRA2 > DRW2D-TX > DRW2D-FB > EDMAC.
+ Priority can be changed with this macro.
+
+ Extended Bus Master Priority setting
+ 0 = GLCDC graphics 1 data read
+ 1 = DRW2D texture data read
+ 2 = DRW2D frame buffer data read write and display list data read
+ 3 = GLCDC graphics 2 data read
+ 4 = EDMAC
+
+ Note : This macro is only available for products with at least 1.5 Mbytes of code flash memory.
+ Settings other than above are prohibited.
+ Duplicate priority settings can not be made.
+*/
+#define BSP_CFG_EBMAPCR_1ST_PRIORITY (0) /* Extended Bus Master 1st Priority Selection */
+#define BSP_CFG_EBMAPCR_2ND_PRIORITY (3) /* Extended Bus Master 2nd Priority Selection */
+#define BSP_CFG_EBMAPCR_3RD_PRIORITY (1) /* Extended Bus Master 3rd Priority Selection */
+#define BSP_CFG_EBMAPCR_4TH_PRIORITY (2) /* Extended Bus Master 4th Priority Selection */
+#define BSP_CFG_EBMAPCR_5TH_PRIORITY (4) /* Extended Bus Master 5th Priority Selection */
+
+/* This macro is used to define the voltage that is supplied to the MCU (Vcc). This macro is defined in millivolts. This
+ macro does not actually change anything on the MCU. Some FIT modules need this information so it is defined here. */
+#define BSP_CFG_MCU_VCC_MV (3300) // <-- Updated by GUI. Do not edit this value manually
+
+/* Allow initialization of auto-generated peripheral initialization code by Smart Configurator tool.
+ When not using the Smart Configurator, set the value of BSP_CFG_CONFIGURATOR_SELECT to 0.
+ 0 = Disabled (default)
+ 1 = Smart Configurator initialization code used
+*/
+#define BSP_CFG_CONFIGURATOR_SELECT (1) // <-- Updated by GUI. Do not edit this value manually
+
+/* There are multiple versions of the RSKRX65N-2MB. Choose which board is currently being used below.
+ 0 = 1st Prototype Board (RTK50565N2CxxxxxBR)
+ 1 = rev. 1.00 Board (RTK50565N2C00000BE)
+ 2 = RX65N Envision Kit
+ 3 = RX65N GR-ROSE
+ (4 = RX64M GR-KAEDE // FIXME: find a better way)
+ 5 = RX65N TB
+*/
+#define BSP_CFG_BOARD_REVISION (5)
+
+#endif /* R_BSP_CONFIG_REF_HEADER_FILE */
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/r_config/r_bsp_config_readme.txt b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/r_config/r_bsp_config_readme.txt
new file mode 100644
index 00000000000..6a9002cf4f3
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/r_config/r_bsp_config_readme.txt
@@ -0,0 +1,12 @@
+FIT r_config folder
+-------------------
+The purpose of the r_config folder is to provide one place where the user can store all of their FIT configuration
+files. Putting the files in one place makes them easy to find, backup, and put in a version control system.
+
+FIT Modules are distributed with a reference configuration file. These files end with '_reference.h'. For example,
+the reference configuration file for the r_bsp is named r_bsp_config_reference.h. Reference configuration files are
+provided so that the user always has a known-good configuration to revert to. When adding a FIT Module to a project the
+user should copy this reference configuration file to this folder and remove '_reference' from the filename
+(r_bsp_config_reference.h is renamed to r_bsp_config.h). For the r_bsp the reference configuration file can be found in
+the 'board' folder for the currently chosen development board. For other FIT Modules the reference configuration file
+can be found in the 'ref' folder of the FIT Module.
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/r_config/r_bsp_interrupt_config.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/r_config/r_bsp_interrupt_config.h
new file mode 100644
index 00000000000..dd09ad9edc6
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/r_config/r_bsp_interrupt_config.h
@@ -0,0 +1,214 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : r_bsp_interrupt_config.h
+* Description : This module maps Interrupt A & B interrupts. More information on how this is done is given below.
+***********************************************************************************************************************/
+/**********************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 01.10.2016 1.00 First Release
+* : 15.05.2017 2.00 Changed the name of the following macro definition, because there was a mistake
+* in the name of macro definition.
+* - From XXX_TPU0_TGI0V to XXX_TPU0_TCI0V.
+* - From XXX_TPU1_TGI1V to XXX_TPU1_TCI1V.
+* - From XXX_TPU1_TGI1U to XXX_TPU1_TCI1U.
+* - From XXX_TPU2_TGI2V to XXX_TPU2_TCI2V.
+* - From XXX_TPU2_TGI2U to XXX_TPU2_TCI2U.
+* - From XXX_TPU3_TGI3V to XXX_TPU3_TCI3V.
+* - From XXX_TPU4_TGI4V to XXX_TPU4_TCI4V.
+* - From XXX_TPU4_TGI4U to XXX_TPU4_TCI4U.
+* - From XXX_TPU5_TGI5V to XXX_TPU5_TCI5V.
+* - From XXX_TPU5_TGI5U to XXX_TPU5_TCI5U.
+* - From XXX_MTU0_TGIV0 to XXX_MTU0_TCIV0.
+* - From XXX_MTU1_TGIV1 to XXX_MTU1_TCIV1.
+* - From XXX_MTU1_TGIU1 to XXX_MTU1_TCIU1.
+* - From XXX_MTU2_TGIV2 to XXX_MTU2_TCIV2.
+* - From XXX_MTU2_TGIU2 to XXX_MTU2_TCIU2.
+* - From XXX_MTU3_TGIV3 to XXX_MTU3_TCIV3.
+* - From XXX_MTU4_TGIV4 to XXX_MTU4_TCIV4.
+* - From XXX_MTU6_TGIV6 to XXX_MTU6_TCIV6.
+* - From XXX_MTU7_TGIV7 to XXX_MTU7_TCIV7.
+* - From XXX_MTU8_TGIV8 to XXX_MTU8_TCIV8.
+* Added select processing of the following software configurable interrupt source.
+* - TSIP_PROC_BUSY
+* - TSIP_ROMOK
+* - TSIP_LONG_PLG
+* - TSIP_TEST_BUSY
+* - TSIP_WRRDY0
+* - TSIP_WRRDY1
+* - TSIP_WRRDY4
+* - TSIP_RDRDY0
+* - TSIP_RDRDY1
+* - TSIP_INTEGRATE_WRRDY
+* - TSIP_INTEGRATE_RDRDY
+***********************************************************************************************************************/
+#ifndef R_BSP_INTERRUPT_CONFIG_REF_HEADER_FILE
+#define R_BSP_INTERRUPT_CONFIG_REF_HEADER_FILE
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/* If you wish to use one of the interrupt below then set the appropriate configuration macro to the vector number you
+ * wish to use for that interrupt. For example, if you want to use the RTC carry interrupt (CUP) at vector 176 then you
+ * would do the following:
+ *
+ * #define BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP 176
+ */
+
+/* Interrupt B Sources.
+ * -Valid vector numbers are 128-207.
+ * -There are more vector slots for B sources than actual B sources. By default all B sources are mapped.
+ * -If using the 'TPU1, TGI1A' interrupt it must be vector 144 or 145. It is set to 144 by default.
+ * -If a peripheral interrupt is going to be used to wake up the MCU from All-Module Clock Stop Mode then it must be
+ * in a vector between 146 to 157. Peripheral interrupts that can do this are TMR interrupts and the 'USB0, USBI0'
+ * interrupt. By default the TMR interrupts are chosen since there are 12 of them and there are 12 slots.
+ */
+#define BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2 128
+#define BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3 129
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0 146
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0 147
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0 148
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1 149
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1 150
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1 151
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2 152
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2 153
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2 154
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3 155
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3 156
+#define BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3 157
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A 130
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B 131
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C 132
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D 133
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TCI0V 134
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A 144
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B 135
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1V 136
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1U 137
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A 138
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B 139
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2V 140
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2U 141
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A 142
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B 143
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C 145
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D 158
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TCI3V 159
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A 160
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B 161
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4V 162
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4U 163
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A 164
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B 165
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5V 166
+#define BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5U 167
+#define BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0 168
+#define BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0 169
+#define BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0 170
+#define BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0 171
+#define BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1 172
+#define BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1 173
+#define BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1 174
+#define BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1 175
+#define BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP 176
+#define BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0 177
+#define BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0 178
+#define BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0 179
+#define BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0 180
+#define BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1 181
+#define BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1 182
+#define BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1 183
+#define BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1 184
+#define BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0 185
+#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0 186
+#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0 187
+#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GCADI0 188
+#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1 189
+#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1 190
+#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GCADI1 191
+#define BSP_MAPPED_INT_CFG_B_VECT_RNG_RNGEND
+#define BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I 193
+#define BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I 194
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_PROC_BUSY 195
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_ROMOK 196
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_LONG_PLG 197
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_TEST_BUSY 198
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY0 199
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY1 200
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY4 201
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY0 202
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY1 203
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_WRRDY 204
+#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_RDRDY 205
+
+/* Interrupt A Sources.
+ * -Valid vector numbers are 208-255.
+ * -There are more A sources than A vector slots. By default none of the GPT interrupts are mapped.
+ * -If using the 'MTU1, TGI1A' interrupt it must be vector 208 or 209. It is set to 208 by default.
+ */
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0 209
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0 210
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0 211
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0 212
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0 213
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0 214
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0 215
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1 208
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1 216
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1 217
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1 218
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2 219
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2 220
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2 221
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2 222
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3 223
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3 224
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3 225
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3 226
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3 227
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4 228
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4 229
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4 230
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4 231
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4 232
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5 233
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5 234
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5 235
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6 236
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6 237
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6 238
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6 239
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6 240
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7 241
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7 242
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7 243
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7 244
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7 245
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8 246
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8 247
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8 248
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8 249
+#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TCIV8 250
+#define BSP_MAPPED_INT_CFG_A_VECT_AES_AESRDY
+#define BSP_MAPPED_INT_CFG_A_VECT_AES_AESEND
+
+#endif /* R_BSP_INTERRUPT_CONFIG_REF_HEADER_FILE */
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/r_pincfg/Pin.c b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/r_pincfg/Pin.c
new file mode 100644
index 00000000000..ef68edd5748
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/r_pincfg/Pin.c
@@ -0,0 +1,79 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) . All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name : Pin.c
+* Version : 1.0.2
+* Device(s) : R5F565NEDxFP
+* Description : This file implements SMC pin code generation.
+* Creation Date: 2018-08-29
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Pragma directive
+***********************************************************************************************************************/
+/* Start user code for pragma. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_macrodriver.h"
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#include "r_cg_userdefine.h"
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+/* Start user code for global. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+* Function Name: R_Pins_Create
+* Description : This function initializes Smart Configurator pins
+* Arguments : None
+* Return Value : None
+***********************************************************************************************************************/
+
+void R_Pins_Create(void)
+{
+ R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_MPC);
+
+ /* Set RXD6 pin */
+ MPC.P33PFS.BYTE = 0x0AU;
+ PORT3.PMR.BYTE |= 0x08U;
+
+ /* Set RXD12 pin */
+ MPC.PE2PFS.BYTE = 0x0CU;
+ PORTE.PMR.BYTE |= 0x04U;
+
+ /* Set TXD6 pin */
+ PORT3.PODR.BYTE |= 0x04U;
+ MPC.P32PFS.BYTE = 0x0AU;
+ PORT3.PDR.BYTE |= 0x04U;
+
+ /* Set TXD12 pin */
+ PORTE.PODR.BYTE |= 0x02U;
+ MPC.PE1PFS.BYTE = 0x0CU;
+ PORTE.PDR.BYTE |= 0x02U;
+
+ R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_MPC);
+}
+
diff --git a/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/r_pincfg/Pin.h b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/r_pincfg/Pin.h
new file mode 100644
index 00000000000..97fef573eff
--- /dev/null
+++ b/demos/renesas/rx65n-tb-uart-sx-ulpgn/gnurx-e2studio/src/smc_gen/r_pincfg/Pin.h
@@ -0,0 +1,50 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) . All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name : Pin.h
+* Version : 1.0.2
+* Device(s) : R5F565NEDxFP
+* Description : This file implements SMC pin code generation.
+* Creation Date: 2018-08-29
+***********************************************************************************************************************/
+
+#ifndef PIN_H
+#define PIN_H
+
+/***********************************************************************************************************************
+Macro definitions (Register bit)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Global functions
+***********************************************************************************************************************/
+void R_Pins_Create(void);
+/* Start user code for function. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#endif
+
diff --git a/lib/ota/portable/renesas/rx65n-tb-uart-sx-ulpgn/aws_ota_pal.c b/lib/ota/portable/renesas/rx65n-tb-uart-sx-ulpgn/aws_ota_pal.c
new file mode 100644
index 00000000000..d18261d3564
--- /dev/null
+++ b/lib/ota/portable/renesas/rx65n-tb-uart-sx-ulpgn/aws_ota_pal.c
@@ -0,0 +1,182 @@
+/*
+ * Amazon FreeRTOS OTA PAL V1.0.0
+ * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://aws.amazon.com/freertos
+ * http://www.FreeRTOS.org
+ */
+
+/* C Runtime includes. */
+#include
+#include
+
+/* Amazon FreeRTOS include. */
+#include "FreeRTOS.h"
+#include "aws_ota_pal.h"
+#include "aws_ota_agent_internal.h"
+
+/* Specify the OTA signature algorithm we support on this platform. */
+const char pcOTA_JSON_FileSignatureKey[ OTA_FILE_SIG_KEY_STR_MAX_LENGTH ] = "sig-sha256-ecdsa"; /* FIX ME. */
+
+
+/* The static functions below (prvPAL_CheckFileSignature and prvPAL_ReadAndAssumeCertificate)
+ * are optionally implemented. If these functions are implemented then please set the following macros in
+ * aws_test_ota_config.h to 1:
+ * otatestpalCHECK_FILE_SIGNATURE_SUPPORTED
+ * otatestpalREAD_AND_ASSUME_CERTIFICATE_SUPPORTED
+ */
+
+/**
+ * @brief Verify the signature of the specified file.
+ *
+ * This function should be implemented if signature verification is not offloaded
+ * to non-volatile memory io functions.
+ *
+ * This function is called from prvPAL_Close().
+ *
+ * @param[in] C OTA file context information.
+ *
+ * @return Below are the valid return values for this function.
+ * kOTA_Err_None if the signature verification passes.
+ * kOTA_Err_SignatureCheckFailed if the signature verification fails.
+ * kOTA_Err_BadSignerCert if the if the signature verification certificate cannot be read.
+ *
+ */
+static OTA_Err_t prvPAL_CheckFileSignature( OTA_FileContext_t * const C );
+
+/**
+ * @brief Read the specified signer certificate from the filesystem into a local buffer.
+ *
+ * The allocated memory returned becomes the property of the caller who is responsible for freeing it.
+ *
+ * This function is called from prvPAL_CheckFileSignature(). It should be implemented if signature
+ * verification is not offloaded to non-volatile memory io function.
+ *
+ * @param[in] pucCertName The file path of the certificate file.
+ * @param[out] ulSignerCertSize The size of the certificate file read.
+ *
+ * @return A pointer to the signer certificate in the file system. NULL if the certificate cannot be read.
+ * This returned pointer is the responsibility of the caller; if the memory is allocated the caller must free it.
+ */
+static uint8_t * prvPAL_ReadAndAssumeCertificate( const uint8_t * const pucCertName,
+ uint32_t * const ulSignerCertSize );
+
+/*-----------------------------------------------------------*/
+
+OTA_Err_t prvPAL_CreateFileForRx( OTA_FileContext_t * const C )
+{
+ DEFINE_OTA_METHOD_NAME( "prvPAL_CreateFileForRx" );
+
+ /* FIX ME. */
+ return kOTA_Err_RxFileCreateFailed;
+}
+/*-----------------------------------------------------------*/
+
+OTA_Err_t prvPAL_Abort( OTA_FileContext_t * const C )
+{
+ DEFINE_OTA_METHOD_NAME( "prvPAL_Abort" );
+
+ /* FIX ME. */
+ return kOTA_Err_FileAbort;
+}
+/*-----------------------------------------------------------*/
+
+/* Write a block of data to the specified file. */
+int16_t prvPAL_WriteBlock( OTA_FileContext_t * const C,
+ uint32_t ulOffset,
+ uint8_t * const pacData,
+ uint32_t ulBlockSize )
+{
+ DEFINE_OTA_METHOD_NAME( "prvPAL_WriteBlock" );
+
+ /* FIX ME. */
+ return -1;
+}
+/*-----------------------------------------------------------*/
+
+OTA_Err_t prvPAL_CloseFile( OTA_FileContext_t * const C )
+{
+ DEFINE_OTA_METHOD_NAME( "prvPAL_CloseFile" );
+
+ /* FIX ME. */
+ return kOTA_Err_FileClose;
+}
+/*-----------------------------------------------------------*/
+
+
+static OTA_Err_t prvPAL_CheckFileSignature( OTA_FileContext_t * const C )
+{
+ DEFINE_OTA_METHOD_NAME( "prvPAL_CheckFileSignature" );
+
+ /* FIX ME. */
+ return kOTA_Err_SignatureCheckFailed;
+}
+/*-----------------------------------------------------------*/
+
+static uint8_t * prvPAL_ReadAndAssumeCertificate( const uint8_t * const pucCertName,
+ uint32_t * const ulSignerCertSize )
+{
+ DEFINE_OTA_METHOD_NAME( "prvPAL_ReadAndAssumeCertificate" );
+
+ /* FIX ME. */
+ return NULL;
+}
+/*-----------------------------------------------------------*/
+
+OTA_Err_t prvPAL_ResetDevice( void )
+{
+ DEFINE_OTA_METHOD_NAME("prvPAL_ResetDevice");
+
+ /* FIX ME. */
+ return kOTA_Err_ResetNotSupported;
+}
+/*-----------------------------------------------------------*/
+
+OTA_Err_t prvPAL_ActivateNewImage( void )
+{
+ DEFINE_OTA_METHOD_NAME("prvPAL_ActivateNewImage");
+
+ /* FIX ME. */
+ return kOTA_Err_Uninitialized;
+}
+/*-----------------------------------------------------------*/
+
+OTA_Err_t prvPAL_SetPlatformImageState( OTA_ImageState_t eState )
+{
+ DEFINE_OTA_METHOD_NAME( "prvPAL_SetPlatformImageState" );
+
+ /* FIX ME. */
+ return kOTA_Err_BadImageState;
+}
+/*-----------------------------------------------------------*/
+
+OTA_PAL_ImageState_t prvPAL_GetPlatformImageState( void )
+{
+ DEFINE_OTA_METHOD_NAME( "prvPAL_GetPlatformImageState" );
+
+ /* FIX ME. */
+ return eOTA_ImageState_Unknown;
+}
+/*-----------------------------------------------------------*/
+
+/* Provide access to private members for testing. */
+#ifdef AMAZON_FREERTOS_ENABLE_UNIT_TESTS
+ #include "aws_ota_pal_test_access_define.h"
+#endif
diff --git a/lib/pkcs11/portable/renesas/rx65n-tb-uart-sx-ulpgn/aws_pkcs11_pal.c b/lib/pkcs11/portable/renesas/rx65n-tb-uart-sx-ulpgn/aws_pkcs11_pal.c
new file mode 100644
index 00000000000..8986a7355a6
--- /dev/null
+++ b/lib/pkcs11/portable/renesas/rx65n-tb-uart-sx-ulpgn/aws_pkcs11_pal.c
@@ -0,0 +1,283 @@
+/*
+ * Amazon FreeRTOS PKCS#11 for Renesas RX MCUs V0.0.1
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://aws.amazon.com/freertos
+ * http://www.FreeRTOS.org
+ */
+
+
+/**
+ * @file aws_pkcs11_pal.c
+ * @brief Amazon FreeRTOS device specific helper functions for
+ * PKCS#11 implementation based on mbedTLS. This
+ * file deviates from the FreeRTOS style standard for some function names and
+ * data types in order to maintain compliance with the PKCS#11 standard.
+ */
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "FreeRTOSIPConfig.h"
+#include "task.h"
+#include "aws_pkcs11.h"
+#include "aws_pkcs11_config.h"
+
+/* C runtime includes. */
+#include
+#include
+
+/* Renesas */
+#include "r_flash_rx_if.h"
+int FLASH_update(uint32_t dst_addr, const void *data, uint32_t size);
+
+
+#define pkcs11OBJECT_CERTIFICATE_MAX_SIZE 2048
+#define pkcs11OBJECT_FLASH_CERT_PRESENT ( 0xABCDEFuL )
+
+
+/**
+ * @brief Structure for certificates/key storage.
+ */
+typedef struct
+{
+ CK_CHAR cDeviceCertificate[ pkcs11OBJECT_CERTIFICATE_MAX_SIZE ];
+ CK_CHAR cDeviceKey[ pkcs11OBJECT_CERTIFICATE_MAX_SIZE ];
+ CK_ULONG ulDeviceCertificateMark;
+ CK_ULONG ulDeviceKeyMark;
+} P11KeyConfig_t;
+
+
+/**
+ * @brief Certificates/key storage in flash.
+ */
+/* As of today... (by NoMaY) */
+#if 0
+/* This is a GCC style. */
+P11KeyConfig_t P11KeyConfig __attribute__( ( section( "UNINIT_FIXED_LOC" ) ) );
+#elif 0
+/* This is a SCFGcompiler.h style. (Of course this needs the "UNINIT_FIXED_LOC" section of linker setting. */
+R_ATTRIB_SECTION_CHANGE_V(UNINIT_FIXED_LOC)
+P11KeyConfig_t P11KeyConfig;
+R_ATTRIB_SECTION_CHANGE_END
+#elif 1
+/* As of today, we use the following code. (Of course this should be changed to the above code later. */
+P11KeyConfig_t P11KeyConfig;
+#endif
+/*-----------------------------------------------------------*/
+
+
+/**
+ * @brief Writes a file to local storage.
+ *
+ * Port-specific file write for crytographic information.
+ *
+ * @param[in] pcFileName The name of the file to be written to.
+ * @param[in] pucData Data buffer to be written to file
+ * @param[in] pulDataSize Size (in bytes) of file data.
+ *
+ * @return pdTRUE if data was saved successfully to file,
+ * pdFALSE otherwise.
+ */
+BaseType_t PKCS11_PAL_SaveFile( char * pcFileName,
+ uint8_t * pucData,
+ uint32_t ulDataSize )
+{
+ CK_RV xResult = pdFALSE;
+ CK_RV xBytesWritten = 0;
+ CK_ULONG ulFlashMark = pkcs11OBJECT_FLASH_CERT_PRESENT;
+
+ /*
+ * write client certificate.
+ */
+
+ if( strncmp( pcFileName,
+ pkcs11configFILE_NAME_CLIENT_CERTIFICATE,
+ strlen( pkcs11configFILE_NAME_CLIENT_CERTIFICATE ) ) == 0 )
+ {
+ xBytesWritten = FLASH_update( ( uint32_t ) P11KeyConfig.cDeviceCertificate,
+ pucData,
+ ( ulDataSize + 1 ) ); /*Include '\0'*/
+
+ if( xBytesWritten == ( ulDataSize + 1 ) )
+ {
+ xResult = pdTRUE;
+
+ /*change flash written mark'*/
+ FLASH_update( ( uint32_t ) &P11KeyConfig.ulDeviceCertificateMark,
+ &ulFlashMark,
+ sizeof( CK_ULONG ) );
+ }
+ }
+
+ /*
+ * write client key.
+ */
+
+ if( strncmp( pcFileName,
+ pkcs11configFILE_NAME_KEY,
+ strlen( pkcs11configFILE_NAME_KEY ) ) == 0 )
+ {
+ xBytesWritten = FLASH_update( ( uint32_t ) P11KeyConfig.cDeviceKey,
+ pucData,
+ ulDataSize + 1 ); /*Include '\0'*/
+
+ if( xBytesWritten == ( ulDataSize + 1 ) )
+ {
+ xResult = pdTRUE;
+
+ /*change flash written mark'*/
+ FLASH_update( ( uint32_t ) &P11KeyConfig.ulDeviceKeyMark,
+ &ulFlashMark,
+ sizeof( CK_ULONG ) );
+ }
+ }
+
+ return xResult;
+}
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Reads a file from local storage.
+ *
+ * Port-specific file access for crytographic information.
+ *
+ * @param[in] pcFileName The name of the file to be read.
+ * @param[out] ppucData Pointer to buffer for file data.
+ * @param[out] pulDataSize Size (in bytes) of data located in file.
+ *
+ * @return pdTRUE if data was retrieved successfully from files,
+ * pdFALSE otherwise.
+ */
+BaseType_t PKCS11_PAL_ReadFile( char * pcFileName,
+ uint8_t ** ppucData,
+ uint32_t * pulDataSize )
+{
+ CK_RV xResult = pdFALSE;
+
+ /*
+ * Read client certificate.
+ */
+
+ if( strncmp( pcFileName,
+ pkcs11configFILE_NAME_CLIENT_CERTIFICATE,
+ strlen( pkcs11configFILE_NAME_CLIENT_CERTIFICATE ) ) == 0 )
+ {
+ /*
+ * return reference and size only if certificates are present in flash
+ */
+ if( P11KeyConfig.ulDeviceCertificateMark == pkcs11OBJECT_FLASH_CERT_PRESENT )
+ {
+ *ppucData = P11KeyConfig.cDeviceCertificate;
+ *pulDataSize = ( uint32_t ) strlen( ( const char * ) P11KeyConfig.cDeviceCertificate ) + 1;
+ xResult = pdTRUE;
+ }
+ }
+
+ /*
+ * Read client key.
+ */
+
+ if( strncmp( pcFileName,
+ pkcs11configFILE_NAME_KEY,
+ strlen( pkcs11configFILE_NAME_KEY ) ) == 0 )
+ {
+ /*
+ * return reference and size only if certificates are present in flash
+ */
+ if( P11KeyConfig.ulDeviceKeyMark == pkcs11OBJECT_FLASH_CERT_PRESENT )
+ {
+ *ppucData = P11KeyConfig.cDeviceKey;
+ *pulDataSize = ( uint32_t ) strlen( ( const char * ) P11KeyConfig.cDeviceKey ) + 1;
+ xResult = pdTRUE;
+ }
+ }
+
+ return xResult;
+}
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Cleanup after ReadFile.
+ *
+ * @param[in] pucBuffer The buffer to free.
+ * @param[in] ulBufferSize The length of the above buffer.
+ */
+void PKCS11_PAL_ReleaseFileData( uint8_t * pucBuffer,
+ uint32_t ulBufferSize )
+{
+ /* Unused parameters. */
+ ( void ) pucBuffer;
+ ( void ) ulBufferSize;
+
+ /* Since no buffer was allocated on heap, there is no cleanup
+ * to be done. */
+}
+/*-----------------------------------------------------------*/
+
+/* Renesas */
+// XXX
+int FLASH_update(uint32_t dst_addr, const void *data, uint32_t size)
+{
+#if 0 /* This code seems to be tentative... (by NoMaY) */
+ uint32_t i;
+ flash_err_t err;
+ volatile uint32_t addr;
+ uint32_t size_blk;
+ uint32_t * src_addr = (uint32_t *) data;
+
+ /* Open driver */
+ err = R_FLASH_Open();
+ if (err != FLASH_SUCCESS) return -1;
+
+ /* Erase code flash block */
+ addr = dst_addr;
+ if ((size%64) == 0)
+ {
+ size_blk = (int)(size/64);
+ }
+ else
+ {
+ size_blk = (int)(size/64) + 1;
+ }
+
+ err = R_FLASH_Erase(dst_addr, (size_blk/64));
+ if (err != FLASH_SUCCESS) return -1;
+
+ while (addr < (dst_addr + size_blk))
+ {
+ err = R_FLASH_Write((uint32_t)src_addr, addr, size_blk);
+ if(err != FLASH_SUCCESS) return -1;
+
+ /* Verify code flash write */
+ for (i = 0; i < size_blk; i++)
+ {
+ if (*((uint8_t *)(src_addr + i)) != *((uint8_t *)(addr + i)))
+ {
+ return -1;
+ }
+ }
+
+ addr += size_blk;
+ }
+
+ return size_blk;
+#endif /* #if 0 |* This code seems to be tentative... (by NoMaY) */
+}
+/*-----------------------------------------------------------*/
diff --git a/lib/secure_sockets/portable/renesas/rx65n-tb-uart-sx-ulpgn/aws_secure_sockets.c b/lib/secure_sockets/portable/renesas/rx65n-tb-uart-sx-ulpgn/aws_secure_sockets.c
new file mode 100644
index 00000000000..0f028331773
--- /dev/null
+++ b/lib/secure_sockets/portable/renesas/rx65n-tb-uart-sx-ulpgn/aws_secure_sockets.c
@@ -0,0 +1,788 @@
+/*
+ * Amazon FreeRTOS Secure Socket V1.0.0
+ * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://aws.amazon.com/freertos
+ * http://www.FreeRTOS.org
+ */
+
+/**
+ * @file aws_secure_sockets.c
+ * @brief WiFi and Secure Socket interface implementation.
+ */
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "FreeRTOSIPConfig.h"
+#include "list.h"
+//#include "FreeRTOS_IP.h"
+#include "aws_secure_sockets.h"
+//#include "FreeRTOS_Sockets.h"
+#include "aws_tls.h"
+#include "task.h"
+#include "aws_pkcs11.h"
+#include "aws_crypto.h"
+#include "sx_ulpgn_driver.h"
+#include "machine.h"
+
+/* Internal context structure. */
+typedef struct SSOCKETContext
+{
+ Socket_t xSocket;
+ char * pcDestination;
+ void * pvTLSContext;
+ BaseType_t xRequireTLS;
+ BaseType_t xSendFlags;
+ BaseType_t xRecvFlags;
+ uint32_t ulSendTimeout;
+ uint32_t ulRecvTimeout;
+ char * pcServerCertificate;
+ uint32_t ulServerCertificateLength;
+} SSOCKETContext_t, * SSOCKETContextPtr_t;
+
+/**
+ * @brief Maximum number of sockets.
+ *
+ * 16 total sockets
+ */
+#define MAX_NUM_SSOCKETS (1)
+
+/**
+ * @brief Number of secure sockets allocated.
+ *
+ * Keep a count of the number of open sockets.
+ */
+static uint8_t ssockets_num_allocated = 0;
+
+
+/*
+ * @brief Network send callback.
+ */
+static BaseType_t prvNetworkSend( void * pvContext,
+ const unsigned char * pucData,
+ size_t xDataLength )
+{
+ SSOCKETContextPtr_t pxContext = ( SSOCKETContextPtr_t ) pvContext; /*lint !e9087 cast used for portability. */
+
+ return sx_ulpgn_tcp_send(pucData, xDataLength, pxContext->ulSendTimeout);
+
+// return FreeRTOS_send( pxContext->xSocket, pucData, xDataLength, pxContext->xSendFlags );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * @brief Network receive callback.
+*/
+static BaseType_t prvNetworkRecv( void * pvContext,
+ unsigned char * pucReceiveBuffer,
+ size_t xReceiveLength )
+{
+ BaseType_t receive_byte;
+ SSOCKETContextPtr_t pxContext = ( SSOCKETContextPtr_t ) pvContext; /*lint !e9087 cast used for portability. */
+
+
+ receive_byte = sx_ulpgn_tcp_recv(pucReceiveBuffer, xReceiveLength, pxContext->ulRecvTimeout);
+
+ if(xReceiveLength == 64)
+ {
+ nop();
+ }
+ return receive_byte;
+
+// return FreeRTOS_recv( pxContext->xSocket, pucReceiveBuffer, xReceiveLength, pxContext->xRecvFlags );
+}
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Creates a TCP socket.
+ *
+ * This call allocates memory and claims a socket resource.
+ *
+ * @sa SOCKETS_Close()
+ *
+ * @param[in] lDomain Must be set to SOCKETS_AF_INET. See @ref SocketDomains.
+ * @param[in] lType Set to SOCKETS_SOCK_STREAM to create a TCP socket.
+ * No other value is valid. See @ref SocketTypes.
+ * @param[in] lProtocol Set to SOCKETS_IPPROTO_TCP to create a TCP socket.
+ * No other value is valid. See @ref Protocols.
+ *
+ * @return
+ * * If a socket is created successfully, then the socket handle is
+ * returned
+ * * @ref SOCKETS_INVALID_SOCKET is returned if an error occurred.
+ */
+Socket_t SOCKETS_Socket( int32_t lDomain,
+ int32_t lType,
+ int32_t lProtocol )
+{
+ int32_t lStatus = SOCKETS_ERROR_NONE;
+ int32_t ret;
+ SSOCKETContextPtr_t pxContext = NULL;
+
+ /* Ensure that only supported values are supplied. */
+ configASSERT( lDomain == SOCKETS_AF_INET );
+ configASSERT( lType == SOCKETS_SOCK_STREAM );
+ configASSERT( lProtocol == SOCKETS_IPPROTO_TCP );
+
+ if(ssockets_num_allocated >= MAX_NUM_SSOCKETS)
+ {
+ lStatus = SOCKETS_SOCKET_ERROR;
+ }
+
+ if( SOCKETS_ERROR_NONE == lStatus )
+ {
+ /* Allocate the internal context structure. */
+ if( NULL == ( pxContext = pvPortMalloc( sizeof( SSOCKETContext_t ) ) ) )
+ {
+ lStatus = SOCKETS_ENOMEM;
+ }
+ }
+
+ if( SOCKETS_ERROR_NONE == lStatus )
+ {
+ memset( pxContext, 0, sizeof( SSOCKETContext_t ) );
+ pxContext->xSocket = 0;
+
+ /* Create the wrapped socket. */
+ ret = sx_ulpgn_socket_create(0,4);
+ if(-1 == ret)
+ {
+ lStatus = SOCKETS_SOCKET_ERROR;
+ }
+ pxContext->ulRecvTimeout = socketsconfigDEFAULT_RECV_TIMEOUT;
+ pxContext->ulSendTimeout = socketsconfigDEFAULT_SEND_TIMEOUT;
+ }
+
+ if( SOCKETS_ERROR_NONE != lStatus )
+ {
+ vPortFree( pxContext );
+ return SOCKETS_INVALID_SOCKET;
+ }
+
+ else
+ {
+ if(ssockets_num_allocated < MAX_NUM_SSOCKETS)
+ {
+ ssockets_num_allocated++;
+ }
+ return pxContext;
+ }
+}
+/*-----------------------------------------------------------*/
+
+Socket_t SOCKETS_Accept( Socket_t xSocket,
+ SocketsSockaddr_t * pxAddress,
+ Socklen_t * pxAddressLength )
+{
+ /* FIX ME. */
+ return SOCKETS_INVALID_SOCKET;
+}
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Connects the socket to the specified IP address and port.
+ *
+ * The socket must first have been successfully created by a call to SOCKETS_Socket().
+ *
+ * @param[in] xSocket The handle of the socket to be connected.
+ * @param[in] pxAddress A pointer to a SocketsSockaddr_t structure that contains the
+ * the address to connect the socket to.
+ * @param[in] xAddressLength Should be set to sizeof( @ref SocketsSockaddr_t ).
+ *
+ * @return
+ * * @ref SOCKETS_ERROR_NONE if a connection is established.
+ * * If an error occured, a negative value is returned. @ref SocketsErrors
+ */
+int32_t SOCKETS_Connect( Socket_t xSocket,
+ SocketsSockaddr_t * pxAddress,
+ Socklen_t xAddressLength )
+{
+ int32_t lStatus = SOCKETS_ERROR_NONE;
+ int32_t ret;
+ SSOCKETContextPtr_t pxContext = ( SSOCKETContextPtr_t ) xSocket; /*lint !e9087 cast used for portability. */
+ TLSParams_t xTLSParams = { 0 };
+
+ if( ( pxContext != SOCKETS_INVALID_SOCKET ) && ( pxAddress != NULL ) )
+ {
+ ret = sx_ulpgn_tcp_connect(SOCKETS_ntohl(pxAddress->ulAddress), SOCKETS_ntohs(pxAddress->usPort));
+ if( 0 != ret )
+ {
+ lStatus = SOCKETS_SOCKET_ERROR;
+ }
+ /* Negotiate TLS if requested. */
+ if( ( SOCKETS_ERROR_NONE == lStatus ) && ( pdTRUE == pxContext->xRequireTLS ) )
+ {
+ xTLSParams.ulSize = sizeof( xTLSParams );
+ xTLSParams.pcDestination = pxContext->pcDestination;
+ xTLSParams.pcServerCertificate = pxContext->pcServerCertificate;
+ xTLSParams.ulServerCertificateLength = pxContext->ulServerCertificateLength;
+ xTLSParams.pvCallerContext = pxContext;
+ xTLSParams.pxNetworkRecv = prvNetworkRecv;
+ xTLSParams.pxNetworkSend = prvNetworkSend;
+ lStatus = TLS_Init( &pxContext->pvTLSContext, &xTLSParams );
+
+ if( SOCKETS_ERROR_NONE == lStatus )
+ {
+ lStatus = TLS_Connect( pxContext->pvTLSContext );
+ if( lStatus < 0 )
+ {
+ lStatus = SOCKETS_TLS_HANDSHAKE_ERROR;
+ }
+ }
+ }
+ }
+ else
+ {
+ lStatus = SOCKETS_SOCKET_ERROR;
+ }
+
+ return lStatus;
+}
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Receive data from a TCP socket.
+ *
+ * The socket must have already been created using a call to SOCKETS_Socket()
+ * and connected to a remote socket using SOCKETS_Connect().
+ *
+ * @param[in] xSocket The handle of the socket from which data is being received.
+ * @param[out] pvBuffer The buffer into which the received data will be placed.
+ * @param[in] xBufferLength The maximum number of bytes which can be received.
+ * pvBuffer must be at least xBufferLength bytes long.
+ * @param[in] ulFlags Not currently used. Should be set to 0.
+ *
+ * @return
+ * * If the receive was successful then the number of bytes received (placed in the
+ * buffer pointed to by pvBuffer) is returned.
+ * * If a timeout occurred before data could be received then 0 is returned (timeout
+ * is set using @ref SOCKETS_SO_RCVTIMEO).
+ * * If an error occured, a negative value is returned. @ref SocketsErrors
+ */
+int32_t SOCKETS_Recv( Socket_t xSocket,
+ void * pvBuffer,
+ size_t xBufferLength,
+ uint32_t ulFlags )
+{
+ int32_t lStatus = SOCKETS_SOCKET_ERROR;
+ SSOCKETContextPtr_t pxContext = ( SSOCKETContextPtr_t ) xSocket; /*lint !e9087 cast used for portability. */
+
+ pxContext->xRecvFlags = ( BaseType_t ) ulFlags;
+
+ if( ( xSocket != SOCKETS_INVALID_SOCKET ) &&
+ ( pvBuffer != NULL ) )
+ {
+ if( pdTRUE == pxContext->xRequireTLS )
+ {
+ /* Receive through TLS pipe, if negotiated. */
+ lStatus = TLS_Recv( pxContext->pvTLSContext, pvBuffer, xBufferLength );
+ }
+ else
+ {
+ /* Receive unencrypted. */
+ lStatus = prvNetworkRecv( pxContext, pvBuffer, xBufferLength );
+ }
+ }
+
+ return lStatus;
+}
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Transmit data to the remote socket.
+ *
+ * The socket must have already been created using a call to SOCKETS_Socket() and
+ * connected to a remote socket using SOCKETS_Connect().
+ *
+ * @param[in] xSocket The handle of the sending socket.
+ * @param[in] pvBuffer The buffer containing the data to be sent.
+ * @param[in] xDataLength The length of the data to be sent.
+ * @param[in] ulFlags Not currently used. Should be set to 0.
+ *
+ * @return
+ * * On success, the number of bytes actually sent is returned.
+ * * If an error occured, a negative value is returned. @ref SocketsErrors
+ */
+int32_t SOCKETS_Send( Socket_t xSocket,
+ const void * pvBuffer,
+ size_t xDataLength,
+ uint32_t ulFlags )
+{
+ int32_t lStatus = SOCKETS_SOCKET_ERROR;
+ SSOCKETContextPtr_t pxContext = ( SSOCKETContextPtr_t ) xSocket; /*lint !e9087 cast used for portability. */
+
+ if( ( xSocket != SOCKETS_INVALID_SOCKET ) &&
+ ( pvBuffer != NULL ) )
+ {
+ pxContext->xSendFlags = ( BaseType_t ) ulFlags;
+
+ if( pdTRUE == pxContext->xRequireTLS )
+ {
+ /* Send through TLS pipe, if negotiated. */
+ lStatus = TLS_Send( pxContext->pvTLSContext, pvBuffer, xDataLength );
+ }
+ else
+ {
+ /* Send unencrypted. */
+ lStatus = prvNetworkSend( pxContext, pvBuffer, xDataLength );
+ }
+ }
+
+ return lStatus;
+}
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Closes all or part of a full-duplex connection on the socket.
+ *
+ * @param[in] xSocket The handle of the socket to shutdown.
+ * @param[in] ulHow SOCKETS_SHUT_RD, SOCKETS_SHUT_WR or SOCKETS_SHUT_RDWR.
+ * @ref ShutdownFlags
+ *
+ * @return
+ * * If the operation was successful, 0 is returned.
+ * * If an error occured, a negative value is returned. @ref SocketsErrors
+ */
+int32_t SOCKETS_Shutdown( Socket_t xSocket,
+ uint32_t ulHow )
+{
+// SSOCKETContextPtr_t pxContext = ( SSOCKETContextPtr_t ) xSocket; /*lint !e9087 cast used for portability. */
+
+ return sx_ulpgn_tcp_disconnect();
+// return FreeRTOS_shutdown( pxContext->xSocket, ( BaseType_t ) ulHow );
+}
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Closes the socket and frees the related resources.
+ *
+ * @param[in] xSocket The handle of the socket to close.
+ *
+ * @return
+ * * On success, 0 is returned.
+ * * If an error occurred, a negative value is returned. @ref SocketsErrors
+ */
+int32_t SOCKETS_Close( Socket_t xSocket )
+{
+ SSOCKETContextPtr_t pxContext = ( SSOCKETContextPtr_t ) xSocket; /*lint !e9087 cast used for portability. */
+
+ if( NULL != pxContext )
+ {
+ if( NULL != pxContext->pcDestination )
+ {
+ vPortFree( pxContext->pcDestination );
+ }
+
+ if( NULL != pxContext->pcServerCertificate )
+ {
+ vPortFree( pxContext->pcServerCertificate );
+ }
+
+ if( pdTRUE == pxContext->xRequireTLS )
+ {
+ TLS_Cleanup( pxContext->pvTLSContext );
+ }
+
+ sx_ulpgn_tcp_disconnect();
+// ( void ) FreeRTOS_closesocket( pxContext->xSocket );
+ vPortFree( pxContext );
+ }
+
+ if(ssockets_num_allocated > 0)
+ {
+ ssockets_num_allocated--;
+ }
+ else
+ {
+ ssockets_num_allocated = 0;
+ }
+ return pdFREERTOS_ERRNO_NONE;
+}
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Manipulates the options for the socket.
+ *
+ * @param[in] xSocket The handle of the socket to set the option for.
+ * @param[in] lLevel Not currently used. Should be set to 0.
+ * @param[in] lOptionName See @ref SetSockOptOptions.
+ * @param[in] pvOptionValue A buffer containing the value of the option to set.
+ * @param[in] xOptionLength The length of the buffer pointed to by pvOptionValue.
+ *
+ * @note Socket option support and possible values vary by port. Please see
+ * PORT_SPECIFIC_LINK to check the valid options and limitations of your device.
+ *
+ * - Berkeley Socket Options
+ * - @ref SOCKETS_SO_RCVTIMEO
+ * - Sets the receive timeout
+ * - pvOptionValue (TickType_t) is the number of milliseconds that the
+ * receive function should wait before timing out.
+ * - Setting pvOptionValue = 0 causes receive to wait forever.
+ * - See PORT_SPECIFIC_LINK for device limitations.
+ * - @ref SOCKETS_SO_SNDTIMEO
+ * - Sets the send timeout
+ * - pvOptionValue (TickType_t) is the number of milliseconds that the
+ * send function should wait before timing out.
+ * - Setting pvOptionValue = 0 causes send to wait forever.
+ * - See PORT_SPECIFIC_LINK for device limitations.
+ * - Non-Standard Options
+ * - @ref SOCKETS_SO_NONBLOCK
+ * - Makes a socket non-blocking.
+ * - pvOptionValue is ignored for this option.
+ * - Security Sockets Options
+ * - @ref SOCKETS_SO_REQUIRE_TLS
+ * - Use TLS for all connect, send, and receive on this socket.
+ * - This socket options MUST be set for TLS to be used, even
+ * if other secure socket options are set.
+ * - pvOptionValue is ignored for this option.
+ * - @ref SOCKETS_SO_TRUSTED_SERVER_CERTIFICATE
+ * - Set the root of trust server certificiate for the socket.
+ * - This socket option only takes effect if @ref SOCKETS_SO_REQUIRE_TLS
+ * is also set. If @ref SOCKETS_SO_REQUIRE_TLS is not set,
+ * this option will be ignored.
+ * - pvOptionValue is a pointer to the formatted server certificate.
+ * TODO: Link to description of how to format certificates with \n
+ * - xOptionLength (BaseType_t) is the length of the certificate
+ * in bytes.
+ * - @ref SOCKETS_SO_SERVER_NAME_INDICATION
+ * - Use Server Name Indication (SNI)
+ * - This socket option only takes effect if @ref SOCKETS_SO_REQUIRE_TLS
+ * is also set. If @ref SOCKETS_SO_REQUIRE_TLS is not set,
+ * this option will be ignored.
+ * - pvOptionValue is a pointer to a string containing the hostname
+ * - xOptionLength is the length of the hostname string in bytes.
+ *
+ * @return
+ * * On success, 0 is returned.
+ * * If an error occured, a negative value is returned. @ref SocketsErrors
+ */
+int32_t SOCKETS_SetSockOpt( Socket_t xSocket,
+ int32_t lLevel,
+ int32_t lOptionName,
+ const void * pvOptionValue,
+ size_t xOptionLength )
+{
+ int32_t lStatus = SOCKETS_ERROR_NONE;
+ TickType_t xTimeout;
+ SSOCKETContextPtr_t pxContext = ( SSOCKETContextPtr_t ) xSocket; /*lint !e9087 cast used for portability. */
+
+ switch( lOptionName )
+ {
+ case SOCKETS_SO_SERVER_NAME_INDICATION:
+
+ /* Non-NULL destination string indicates that SNI extension should
+ * be used during TLS negotiation. */
+ if( NULL == ( pxContext->pcDestination =
+ ( char * ) pvPortMalloc( 1U + xOptionLength ) ) )
+ {
+ lStatus = SOCKETS_ENOMEM;
+ }
+ else
+ {
+ memcpy( pxContext->pcDestination, pvOptionValue, xOptionLength );
+ pxContext->pcDestination[ xOptionLength ] = '\0';
+ }
+
+ break;
+
+ case SOCKETS_SO_TRUSTED_SERVER_CERTIFICATE:
+
+ /* Non-NULL server certificate field indicates that the default trust
+ * list should not be used. */
+ if( NULL == ( pxContext->pcServerCertificate =
+ ( char * ) pvPortMalloc( xOptionLength ) ) )
+ {
+ lStatus = SOCKETS_ENOMEM;
+ }
+ else
+ {
+ memcpy( pxContext->pcServerCertificate, pvOptionValue, xOptionLength );
+ pxContext->ulServerCertificateLength = xOptionLength;
+ }
+
+ break;
+
+ case SOCKETS_SO_REQUIRE_TLS:
+ pxContext->xRequireTLS = pdTRUE;
+ break;
+
+ case SOCKETS_SO_NONBLOCK:
+ pxContext->ulSendTimeout = 1;
+ pxContext->ulRecvTimeout = 2;
+ break;
+
+ case SOCKETS_SO_RCVTIMEO:
+ /* Comply with Berkeley standard - a 0 timeout is wait forever. */
+ xTimeout = *( ( const TickType_t * ) pvOptionValue ); /*lint !e9087 pvOptionValue passed should be of TickType_t */
+
+ if( xTimeout == 0U )
+ {
+ xTimeout = portMAX_DELAY;
+ }
+ pxContext->ulRecvTimeout = xTimeout;
+// sx_ulpgn_serial_tcp_timeout_set(xTimeout);
+ break;
+ case SOCKETS_SO_SNDTIMEO:
+ /* Comply with Berkeley standard - a 0 timeout is wait forever. */
+ xTimeout = *( ( const TickType_t * ) pvOptionValue ); /*lint !e9087 pvOptionValue passed should be of TickType_t */
+
+ if( xTimeout == 0U )
+ {
+ xTimeout = portMAX_DELAY;
+ }
+ pxContext->ulSendTimeout = xTimeout;
+// sx_ulpgn_serial_tcp_timeout_set(xTimeout);
+ break;
+
+ default:
+ lStatus = SOCKETS_ENOPROTOOPT;
+// FreeRTOS_setsockopt( pxContext->xSocket,
+// lLevel,
+// lOptionName,
+// pvOptionValue,
+// xOptionLength );
+ break;
+ }
+
+ return lStatus;
+}
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Resolve a host name using Domain Name Service.
+ *
+ * @param[in] pcHostName The host name to resolve.
+ * @return
+ * * The IPv4 address of the specified host.
+ * * If an error has occured, 0 is returned.
+ */
+uint32_t SOCKETS_GetHostByName( const char * pcHostName )
+{
+ uint32_t ulAddr = 0;
+ uint32_t ret;
+
+ ret = sx_ulpgn_dns_query(pcHostName, &ulAddr);
+ if(0 == ret)
+ {
+ ulAddr = SOCKETS_htonl( ulAddr );
+ }
+ return ulAddr;
+}
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Secure Sockets library initialization function.
+ *
+ * This function does general initialization and setup. It must be called once
+ * and only once before calling any other function.
+ *
+ * @return
+ * * @ref pdPASS if everything succeeds
+ * * @ref pdFAIL otherwise.
+ */
+BaseType_t SOCKETS_Init( void )
+{
+ /* FIX ME. */
+ /* Empty initialization */
+ return pdPASS;
+}
+/*-----------------------------------------------------------*/
+
+static CK_RV prvSocketsGetCryptoSession( CK_SESSION_HANDLE *pxSession,
+ CK_FUNCTION_LIST_PTR_PTR ppxFunctionList )
+{
+ CK_RV xResult = 0;
+ CK_C_GetFunctionList pxCkGetFunctionList = NULL;
+ static CK_SESSION_HANDLE xPkcs11Session = 0;
+ static CK_FUNCTION_LIST_PTR pxPkcs11FunctionList = NULL;
+ CK_ULONG ulCount = 1;
+ CK_SLOT_ID xSlotId = 0;
+
+ portENTER_CRITICAL( );
+
+ if( 0 == xPkcs11Session )
+ {
+ /* One-time initialization. */
+
+ /* Ensure that the PKCS#11 module is initialized. */
+ if( 0 == xResult )
+ {
+ pxCkGetFunctionList = C_GetFunctionList;
+ xResult = pxCkGetFunctionList( &pxPkcs11FunctionList );
+ }
+
+ if( 0 == xResult )
+ {
+ xResult = pxPkcs11FunctionList->C_Initialize( NULL );
+ }
+
+ /* Get the default slot ID. */
+ if( 0 == xResult )
+ {
+ xResult = pxPkcs11FunctionList->C_GetSlotList(
+ CK_TRUE,
+ &xSlotId,
+ &ulCount );
+ }
+
+ /* Start a session with the PKCS#11 module. */
+ if( 0 == xResult )
+ {
+ xResult = pxPkcs11FunctionList->C_OpenSession(
+ xSlotId,
+ CKF_SERIAL_SESSION,
+ NULL,
+ NULL,
+ &xPkcs11Session );
+ }
+ }
+
+ portEXIT_CRITICAL( );
+
+ /* Output the shared function pointers and session handle. */
+ *ppxFunctionList = pxPkcs11FunctionList;
+ *pxSession = xPkcs11Session;
+
+ return xResult;
+}
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Generate a TCP Initial Sequence Number that is reasonably difficult
+ * to predict, per https://tools.ietf.org/html/rfc6528.
+ */
+uint32_t ulApplicationGetNextSequenceNumber(
+ uint32_t ulSourceAddress,
+ uint16_t usSourcePort,
+ uint32_t ulDestinationAddress,
+ uint16_t usDestinationPort )
+{
+ CK_RV xResult = 0;
+ CK_SESSION_HANDLE xPkcs11Session = 0;
+ CK_FUNCTION_LIST_PTR pxPkcs11FunctionList = NULL;
+ CK_MECHANISM xMechSha256 = { 0 };
+ uint8_t ucSha256Result[ cryptoSHA256_DIGEST_BYTES ];
+ CK_ULONG ulLength = sizeof( ucSha256Result );
+ uint32_t ulNextSequenceNumber = 0;
+ static uint64_t ullKey = 0;
+
+ /* Acquire a crypto session handle. */
+ xResult = prvSocketsGetCryptoSession(
+ &xPkcs11Session,
+ &pxPkcs11FunctionList );
+
+ if( 0 == xResult )
+ {
+ portENTER_CRITICAL( );
+ if( 0 == ullKey )
+ {
+ /* One-time initialization, per boot, of the random seed. */
+ xResult = pxPkcs11FunctionList->C_GenerateRandom(
+ xPkcs11Session,
+ ( CK_BYTE_PTR )&ullKey,
+ sizeof( ullKey ) );
+ }
+ portEXIT_CRITICAL( );
+ }
+
+ /* Lock the shared crypto session. */
+ portENTER_CRITICAL( );
+
+ /* Start a hash. */
+ if( 0 == xResult )
+ {
+ xMechSha256.mechanism = CKM_SHA256;
+ xResult = pxPkcs11FunctionList->C_DigestInit(
+ xPkcs11Session, &xMechSha256 );
+ }
+
+ /* Hash the seed. */
+ if( 0 == xResult )
+ {
+ xResult = pxPkcs11FunctionList->C_DigestUpdate(
+ xPkcs11Session, ( CK_BYTE_PTR )&ullKey, sizeof( ullKey ) );
+ }
+
+ /* Hash the source address. */
+ if( 0 == xResult )
+ {
+ xResult = pxPkcs11FunctionList->C_DigestUpdate(
+ xPkcs11Session,
+ ( CK_BYTE_PTR )&ulSourceAddress,
+ sizeof( ulSourceAddress ) );
+ }
+
+ /* Hash the source port. */
+ if( 0 == xResult )
+ {
+ xResult = pxPkcs11FunctionList->C_DigestUpdate(
+ xPkcs11Session,
+ ( CK_BYTE_PTR )&usSourcePort,
+ sizeof( usSourcePort ) );
+ }
+
+ /* Hash the destination address. */
+ if( 0 == xResult )
+ {
+ xResult = pxPkcs11FunctionList->C_DigestUpdate(
+ xPkcs11Session,
+ ( CK_BYTE_PTR )&ulDestinationAddress,
+ sizeof( ulDestinationAddress ) );
+ }
+
+ /* Hash the destination port. */
+ if( 0 == xResult )
+ {
+ xResult = pxPkcs11FunctionList->C_DigestUpdate(
+ xPkcs11Session,
+ ( CK_BYTE_PTR )&usDestinationPort,
+ sizeof( usDestinationPort ) );
+ }
+
+ /* Get the hash. */
+ if( 0 == xResult )
+ {
+ xResult = pxPkcs11FunctionList->C_DigestFinal(
+ xPkcs11Session,
+ ucSha256Result,
+ &ulLength );
+ }
+
+ portEXIT_CRITICAL( );
+
+ /* Use the first four bytes of the hash result as the starting point for
+ all initial sequence numbers for connections based on the input 4-tuple. */
+ if( 0 == xResult )
+ {
+ memcpy(
+ &ulNextSequenceNumber,
+ ucSha256Result,
+ sizeof( ulNextSequenceNumber ) );
+
+ /* Add the tick count of four-tick intervals. In theory, per the RFC
+ (see above), this approach still allows server equipment to optimize
+ handling of connections from the same device that haven't fully timed out. */
+ ulNextSequenceNumber += xTaskGetTickCount( ) / 4;
+ }
+
+ return ulNextSequenceNumber;
+}
+/*-----------------------------------------------------------*/
diff --git a/lib/wifi/portable/renesas/rx65n-tb-uart-sx-ulpgn/aws_wifi.c b/lib/wifi/portable/renesas/rx65n-tb-uart-sx-ulpgn/aws_wifi.c
new file mode 100644
index 00000000000..7258aba8c5a
--- /dev/null
+++ b/lib/wifi/portable/renesas/rx65n-tb-uart-sx-ulpgn/aws_wifi.c
@@ -0,0 +1,283 @@
+/*
+ * Amazon FreeRTOS Wi-Fi V1.0.0
+ * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://aws.amazon.com/freertos
+ * http://www.FreeRTOS.org
+ */
+
+/**
+ * @file aws_wifi.c
+ * @brief WiFi Interface.
+ */
+#include
+#include
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+
+/* Socket and WiFi interface includes. */
+#include "aws_wifi.h"
+
+/* WiFi configuration includes. */
+#include "aws_wifi_config.h"
+
+/* WiFi configuration includes. */
+#include "platform.h"
+#include "r_sci_rx_if.h"
+#include "sx_ulpgn_driver.h"
+
+/**
+ * @brief Wi-Fi initialization status.
+ */
+static BaseType_t xWIFIInitDone;
+static uint32_t prvConvertSecurityFromSilexAT( WIFISecurity_t xSecurity );
+
+static uint32_t prvConvertSecurityFromSilexAT( WIFISecurity_t xSecurity )
+{
+ uint32_t xConvertedSecurityType = ULPGN_SECURITY_UNDEFINED;
+
+ switch( xSecurity )
+ {
+ case eWiFiSecurityOpen:
+ xConvertedSecurityType = ULPGN_SECURITY_OPEN;
+ break;
+
+ case eWiFiSecurityWEP:
+ xConvertedSecurityType = ULPGN_SECURITY_WEP;
+ break;
+
+ case eWiFiSecurityWPA:
+ xConvertedSecurityType = ULPGN_SECURITY_WPA;
+ break;
+
+ case eWiFiSecurityWPA2:
+ xConvertedSecurityType = ULPGN_SECURITY_WPA2;
+ break;
+
+ case eWiFiSecurityNotSupported:
+ xConvertedSecurityType = ULPGN_SECURITY_UNDEFINED;
+ break;
+ }
+
+ return xConvertedSecurityType;
+}
+
+/*-----------------------------------------------------------*/
+
+WIFIReturnCode_t WIFI_On( void )
+{
+ /* FIX ME. */
+ WIFIReturnCode_t xRetVal = eWiFiFailure;
+
+
+ /* One time Wi-Fi initialization */
+ if( xWIFIInitDone == pdFALSE )
+ {
+#if 0
+ /* This buffer is used to store the semaphore's data structure
+ * and therefore must be static. */
+ static StaticSemaphore_t xSemaphoreBuffer;
+
+ /* Start with all the zero. */
+ memset( &( xWiFiModule ), 0, sizeof( xWiFiModule ) );
+
+ /* Create the semaphore used to serialize Wi-Fi module operations. */
+ xWiFiModule.xSemaphoreHandle = xSemaphoreCreateMutexStatic( &( xSemaphoreBuffer ) );
+
+ /* Initialize semaphore. */
+ xSemaphoreGive( xWiFiModule.xSemaphoreHandle );
+#endif
+ /* Wi-Fi init done*/
+ xWIFIInitDone = pdTRUE;
+ }
+
+ if(0 == sx_ulpgn_init())
+ {
+ xRetVal = eWiFiSuccess;
+ }
+
+ return xRetVal;
+}
+/*-----------------------------------------------------------*/
+
+WIFIReturnCode_t WIFI_Off( void )
+{
+ /* FIX ME. */
+ R_SCI_Close(SCI_CH7);
+
+ return eWiFiSuccess;
+}
+/*-----------------------------------------------------------*/
+
+//eWiFiSecurityOpen = 0, /**< Open - No Security. */
+//eWiFiSecurityWEP, /**< WEP Security. */
+//eWiFiSecurityWPA, /**< WPA Security. */
+//eWiFiSecurityWPA2, /**< WPA2 Security. */
+
+WIFIReturnCode_t WIFI_ConnectAP( const WIFINetworkParams_t * const pxNetworkParams )
+{
+ int32_t ret;
+ uint32_t convert_security;
+ convert_security = prvConvertSecurityFromSilexAT(pxNetworkParams->xSecurity);
+ ret = sx_ulpgn_wifi_connect(
+ pxNetworkParams->pcSSID,
+ convert_security,
+ pxNetworkParams->pcPassword);
+ if(ret != 0)
+ {
+ return eWiFiFailure;
+ }
+
+
+ return eWiFiSuccess;
+}
+
+/*-----------------------------------------------------------*/
+
+WIFIReturnCode_t WIFI_Disconnect( void )
+{
+ /* FIX ME. */
+ return eWiFiFailure;
+}
+/*-----------------------------------------------------------*/
+
+WIFIReturnCode_t WIFI_Reset( void )
+{
+ /* FIX ME. */
+ return eWiFiFailure;
+}
+/*-----------------------------------------------------------*/
+
+WIFIReturnCode_t WIFI_Scan( WIFIScanResult_t * pxBuffer,
+ uint8_t ucNumNetworks )
+{
+ /* FIX ME. */
+ return eWiFiFailure;
+}
+/*-----------------------------------------------------------*/
+
+WIFIReturnCode_t WIFI_SetMode( WIFIDeviceMode_t xDeviceMode )
+{
+ /* FIX ME. */
+ return eWiFiNotSupported;
+}
+/*-----------------------------------------------------------*/
+
+WIFIReturnCode_t WIFI_GetMode( WIFIDeviceMode_t * pxDeviceMode )
+{
+ /* FIX ME. */
+ return eWiFiNotSupported;
+}
+/*-----------------------------------------------------------*/
+
+WIFIReturnCode_t WIFI_NetworkAdd( const WIFINetworkProfile_t * const pxNetworkProfile,
+ uint16_t * pusIndex )
+{
+ /* FIX ME. */
+ return eWiFiNotSupported;
+}
+/*-----------------------------------------------------------*/
+
+WIFIReturnCode_t WIFI_NetworkGet( WIFINetworkProfile_t * pxNetworkProfile,
+ uint16_t usIndex )
+{
+ /* FIX ME. */
+ return eWiFiNotSupported;
+}
+/*-----------------------------------------------------------*/
+
+WIFIReturnCode_t WIFI_NetworkDelete( uint16_t usIndex )
+{
+ /* FIX ME. */
+ return eWiFiNotSupported;
+}
+/*-----------------------------------------------------------*/
+
+WIFIReturnCode_t WIFI_Ping( uint8_t * pucIPAddr,
+ uint16_t usCount,
+ uint32_t ulIntervalMS )
+{
+ /* FIX ME. */
+ return eWiFiNotSupported;
+}
+/*-----------------------------------------------------------*/
+
+WIFIReturnCode_t WIFI_GetIP( uint8_t * pucIPAddr )
+{
+ /* FIX ME. */
+ return eWiFiNotSupported;
+}
+/*-----------------------------------------------------------*/
+
+WIFIReturnCode_t WIFI_GetMAC( uint8_t * pucMac )
+{
+ /* FIX ME. */
+// sx_ulpgn_wifi_get_macaddr();
+ return eWiFiNotSupported;
+}
+/*-----------------------------------------------------------*/
+
+WIFIReturnCode_t WIFI_GetHostIP( char * pcHost,
+ uint8_t * pucIPAddr )
+{
+ /* FIX ME. */
+ return eWiFiNotSupported;
+}
+/*-----------------------------------------------------------*/
+
+WIFIReturnCode_t WIFI_StartAP( void )
+{
+ /* FIX ME. */
+ return eWiFiNotSupported;
+}
+/*-----------------------------------------------------------*/
+
+WIFIReturnCode_t WIFI_StopAP( void )
+{
+ /* FIX ME. */
+ return eWiFiNotSupported;
+}
+/*-----------------------------------------------------------*/
+
+WIFIReturnCode_t WIFI_ConfigureAP( const WIFINetworkParams_t * const pxNetworkParams )
+{
+ /* FIX ME. */
+ return eWiFiNotSupported;
+}
+/*-----------------------------------------------------------*/
+
+WIFIReturnCode_t WIFI_SetPMMode( WIFIPMMode_t xPMModeType,
+ const void * pvOptionValue )
+{
+ /* FIX ME. */
+ return eWiFiNotSupported;
+}
+/*-----------------------------------------------------------*/
+
+WIFIReturnCode_t WIFI_GetPMMode( WIFIPMMode_t * pxPMModeType,
+ void * pvOptionValue )
+ {
+ /* FIX ME. */
+ return eWiFiNotSupported;
+}
+/*-----------------------------------------------------------*/
+
+
+