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ucode_bits.txt
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--- T2 clk
63 UBRK BR clk
62 UBRX BRMX cntl
61 USRX01 SRMX cntl
60 USRX00
59 UDRX01 DRMX cntl
58 UDRX00
57 USRK SR clk
56 UDRK01 DR clk
55 UDRK00
54 UCCL02 condition code cntl
53 UCCL01
52 UCCL00
51 UPCA PCA clk
50 UPCB01 PCB clk
49 UPCB00
48 USHF01 SHFR cntl
47 USHF00
46 UIRK IR clk
--- T1 clk falling
45 UPWE01 register write enable
44 UPWE00
43 UPAD02 register address
42 UPAD01
41 UPAD00
--- T1 clk
40 UBSD01 pause cntl
39 UBSD00
38 UBAX01 BAMX cntl
37 UBAX00
36 UIBS01 ??
35 UIBS00
34 USHC01 SC cntl
33 USHC00
32 UBCT02 ??
31 UBCT01
30 UBCT00
29 UMSC02 misc cntl (??)
28 UMSC01
27 UMSC00
26 UBSC02 bus cntl (??)
25 UBSC01
24 UBSC00
23 UAMX01 AMX cntl
22 UAMX00
21 UBMX01 BMX cntl
20 UBMX00
19 UKMX01 K?MX cntl
18 UKMX00
17 UALU2 ALU cntl
16 UALU1
15 UALU0
--- not clocked
14 UCFEN C fork enable
13 UBFEN B fork enable
12 UAFEN A fork enable
11 UBEF03 branch enable
10 UBEF02
09 UBEF01
08 UBEF00
07 UADR07 next ROM address
06 UADR06
05 UADR05
04 UADR04
03 UADR03
02 UADR02
01 UADR01
00 UADR00
clocks
======
BR T1
PCA T5
PCB T1
GR[x] WE T5
SR T1
DR T1-T3
SC T3,T5
IR T1