@@ -208,6 +208,11 @@ uart_t* uartBegin(uint8_t uart_nr, uint32_t baudrate, uint32_t config, int8_t rx
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uart -> dev -> conf0 .stop_bit_num = ONE_STOP_BITS_CONF ;
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uart -> dev -> rs485_conf .dl1_en = 1 ;
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}
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+
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+ // tx_idle_num : idle interval after tx FIFO is empty(unit: the time it takes to send one bit under current baudrate)
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+ // Setting it to 0 prevents line idle time/delays when sending messages with small intervals
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+ uart -> dev -> idle_conf .tx_idle_num = 0 ; //
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+
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UART_MUTEX_UNLOCK ();
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if (rxPin != -1 ) {
@@ -265,7 +270,7 @@ uint32_t uartAvailable(uart_t* uart)
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if (uart == NULL || uart -> queue == NULL ) {
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return 0 ;
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}
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- return uxQueueMessagesWaiting (uart -> queue );
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+ return ( uxQueueMessagesWaiting (uart -> queue ) + uart -> dev -> status . rxfifo_cnt ) ;
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}
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uint32_t uartAvailableForWrite (uart_t * uart )
@@ -276,12 +281,27 @@ uint32_t uartAvailableForWrite(uart_t* uart)
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return 0x7f - uart -> dev -> status .txfifo_cnt ;
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}
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+ void uartRxFifoToQueue (uart_t * uart )
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+ {
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+ uint8_t c ;
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+ UART_MUTEX_LOCK ();
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+ while (uart -> dev -> status .rxfifo_cnt || (uart -> dev -> mem_rx_status .wr_addr != uart -> dev -> mem_rx_status .rd_addr )) {
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+ c = uart -> dev -> fifo .rw_byte ;
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+ xQueueSend (uart -> queue , & c , 0 );
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+ }
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+ UART_MUTEX_UNLOCK ();
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+ }
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+
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uint8_t uartRead (uart_t * uart )
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{
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if (uart == NULL || uart -> queue == NULL ) {
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return 0 ;
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}
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uint8_t c ;
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+ if ((uxQueueMessagesWaiting (uart -> queue ) == 0 ) && (uart -> dev -> status .rxfifo_cnt > 0 ))
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+ {
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+ uartRxFifoToQueue (uart );
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+ }
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if (xQueueReceive (uart -> queue , & c , 0 )) {
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return c ;
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}
@@ -294,6 +314,10 @@ uint8_t uartPeek(uart_t* uart)
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return 0 ;
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}
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uint8_t c ;
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+ if ((uxQueueMessagesWaiting (uart -> queue ) == 0 ) && (uart -> dev -> status .rxfifo_cnt > 0 ))
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+ {
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+ uartRxFifoToQueue (uart );
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+ }
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if (xQueuePeek (uart -> queue , & c , 0 )) {
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return c ;
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}
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