Fix connect logic

akinglw · Aug 23, 2018 · 07a4da3 · 07a4da3
1 parent 4f01dfb
commit 07a4da3
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Showing 2 changed files with 2 additions and 2 deletions.
diff --git a/rtl/axi_interconnect.v b/rtl/axi_interconnect.v
@@ -498,7 +498,7 @@ always @* begin
 
             match = 1'b0;
             for (i = 0; i < M_COUNT; i = i + 1) begin
-                if (M_ADDR_WIDTH[i*32 +: 32] && ((read ? M_CONNECT_READ : M_CONNECT_WRITE) & (1 << (s_select*S_COUNT+i))) && (axi_addr_reg >> M_ADDR_WIDTH[i*32 +: 32]) == (M_BASE_ADDR[i*ADDR_WIDTH +: ADDR_WIDTH] >> M_ADDR_WIDTH[i*32 +: 32])) begin
+                if (M_ADDR_WIDTH[i*32 +: 32] && ((read ? M_CONNECT_READ : M_CONNECT_WRITE) & (1 << (s_select+i*S_COUNT))) && (axi_addr_reg >> M_ADDR_WIDTH[i*32 +: 32]) == (M_BASE_ADDR[i*ADDR_WIDTH +: ADDR_WIDTH] >> M_ADDR_WIDTH[i*32 +: 32])) begin
                     m_select_next = i;
                     match = 1'b1;
                 end

diff --git a/rtl/axil_interconnect.v b/rtl/axil_interconnect.v
@@ -302,7 +302,7 @@ always @* begin
 
             match = 1'b0;
             for (i = 0; i < M_COUNT; i = i + 1) begin
-                if (M_ADDR_WIDTH[i*32 +: 32] && ((read ? M_CONNECT_READ : M_CONNECT_WRITE) & (1 << (s_select*S_COUNT+i))) && (axil_addr_reg >> M_ADDR_WIDTH[i*32 +: 32]) == (M_BASE_ADDR[i*ADDR_WIDTH +: ADDR_WIDTH] >> M_ADDR_WIDTH[i*32 +: 32])) begin
+                if (M_ADDR_WIDTH[i*32 +: 32] && ((read ? M_CONNECT_READ : M_CONNECT_WRITE) & (1 << (s_select+i*S_COUNT))) && (axil_addr_reg >> M_ADDR_WIDTH[i*32 +: 32]) == (M_BASE_ADDR[i*ADDR_WIDTH +: ADDR_WIDTH] >> M_ADDR_WIDTH[i*32 +: 32])) begin
                     m_select_next = i;
                     match = 1'b1;
                 end