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marvell.c
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// SPDX-License-Identifier: GPL-2.0+
/*
* drivers/net/phy/marvell.c
*
* Driver for Marvell PHYs
*
* Author: Andy Fleming
*
* Copyright (c) 2004 Freescale Semiconductor, Inc.
*
* Copyright (c) 2013 Michael Stapelberg <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/ctype.h>
#include <linux/errno.h>
#include <linux/unistd.h>
#include <linux/hwmon.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/spinlock.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/mii.h>
#include <linux/ethtool.h>
#include <linux/ethtool_netlink.h>
#include <linux/phy.h>
#include <linux/marvell_phy.h>
#include <linux/bitfield.h>
#include <linux/of.h>
#include <linux/io.h>
#include <asm/irq.h>
#include <linux/uaccess.h>
#define MII_MARVELL_PHY_PAGE 22
#define MII_MARVELL_COPPER_PAGE 0x00
#define MII_MARVELL_FIBER_PAGE 0x01
#define MII_MARVELL_MSCR_PAGE 0x02
#define MII_MARVELL_LED_PAGE 0x03
#define MII_MARVELL_VCT5_PAGE 0x05
#define MII_MARVELL_MISC_TEST_PAGE 0x06
#define MII_MARVELL_VCT7_PAGE 0x07
#define MII_MARVELL_WOL_PAGE 0x11
#define MII_M1011_IEVENT 0x13
#define MII_M1011_IEVENT_CLEAR 0x0000
#define MII_M1011_IMASK 0x12
#define MII_M1011_IMASK_INIT 0x6400
#define MII_M1011_IMASK_CLEAR 0x0000
#define MII_M1011_PHY_SCR 0x10
#define MII_M1011_PHY_SCR_DOWNSHIFT_EN BIT(11)
#define MII_M1011_PHY_SCR_DOWNSHIFT_MASK GENMASK(14, 12)
#define MII_M1011_PHY_SCR_DOWNSHIFT_MAX 8
#define MII_M1011_PHY_SCR_MDI (0x0 << 5)
#define MII_M1011_PHY_SCR_MDI_X (0x1 << 5)
#define MII_M1011_PHY_SCR_AUTO_CROSS (0x3 << 5)
#define MII_M1011_PHY_SSR 0x11
#define MII_M1011_PHY_SSR_DOWNSHIFT BIT(5)
#define MII_M1111_PHY_LED_CONTROL 0x18
#define MII_M1111_PHY_LED_DIRECT 0x4100
#define MII_M1111_PHY_LED_COMBINE 0x411c
#define MII_M1111_PHY_EXT_CR 0x14
#define MII_M1111_PHY_EXT_CR_DOWNSHIFT_MASK GENMASK(11, 9)
#define MII_M1111_PHY_EXT_CR_DOWNSHIFT_MAX 8
#define MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN BIT(8)
#define MII_M1111_RGMII_RX_DELAY BIT(7)
#define MII_M1111_RGMII_TX_DELAY BIT(1)
#define MII_M1111_PHY_EXT_SR 0x1b
#define MII_M1111_HWCFG_MODE_MASK 0xf
#define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3
#define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4
#define MII_M1111_HWCFG_MODE_RTBI 0x7
#define MII_M1111_HWCFG_MODE_COPPER_RTBI 0x9
#define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb
#define MII_M1111_HWCFG_FIBER_COPPER_RES BIT(13)
#define MII_M1111_HWCFG_FIBER_COPPER_AUTO BIT(15)
#define MII_88E1121_PHY_MSCR_REG 21
#define MII_88E1121_PHY_MSCR_RX_DELAY BIT(5)
#define MII_88E1121_PHY_MSCR_TX_DELAY BIT(4)
#define MII_88E1121_PHY_MSCR_DELAY_MASK (BIT(5) | BIT(4))
#define MII_88E1121_MISC_TEST 0x1a
#define MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK 0x1f00
#define MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT 8
#define MII_88E1510_MISC_TEST_TEMP_IRQ_EN BIT(7)
#define MII_88E1510_MISC_TEST_TEMP_IRQ BIT(6)
#define MII_88E1121_MISC_TEST_TEMP_SENSOR_EN BIT(5)
#define MII_88E1121_MISC_TEST_TEMP_MASK 0x1f
#define MII_88E1510_TEMP_SENSOR 0x1b
#define MII_88E1510_TEMP_SENSOR_MASK 0xff
#define MII_88E1540_COPPER_CTRL3 0x1a
#define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_MASK GENMASK(11, 10)
#define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_00MS 0
#define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_10MS 1
#define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_20MS 2
#define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_40MS 3
#define MII_88E1540_COPPER_CTRL3_FAST_LINK_DOWN BIT(9)
#define MII_88E6390_MISC_TEST 0x1b
#define MII_88E6390_MISC_TEST_SAMPLE_1S 0
#define MII_88E6390_MISC_TEST_SAMPLE_10MS BIT(14)
#define MII_88E6390_MISC_TEST_SAMPLE_DISABLE BIT(15)
#define MII_88E6390_MISC_TEST_SAMPLE_ENABLE 0
#define MII_88E6390_MISC_TEST_SAMPLE_MASK (0x3 << 14)
#define MII_88E6390_TEMP_SENSOR 0x1c
#define MII_88E6390_TEMP_SENSOR_MASK 0xff
#define MII_88E6390_TEMP_SENSOR_SAMPLES 10
#define MII_88E1318S_PHY_MSCR1_REG 16
#define MII_88E1318S_PHY_MSCR1_PAD_ODD BIT(6)
/* Copper Specific Interrupt Enable Register */
#define MII_88E1318S_PHY_CSIER 0x12
/* WOL Event Interrupt Enable */
#define MII_88E1318S_PHY_CSIER_WOL_EIE BIT(7)
/* LED Timer Control Register */
#define MII_88E1318S_PHY_LED_TCR 0x12
#define MII_88E1318S_PHY_LED_TCR_FORCE_INT BIT(15)
#define MII_88E1318S_PHY_LED_TCR_INTn_ENABLE BIT(7)
#define MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW BIT(11)
/* Magic Packet MAC address registers */
#define MII_88E1318S_PHY_MAGIC_PACKET_WORD2 0x17
#define MII_88E1318S_PHY_MAGIC_PACKET_WORD1 0x18
#define MII_88E1318S_PHY_MAGIC_PACKET_WORD0 0x19
#define MII_88E1318S_PHY_WOL_CTRL 0x10
#define MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS BIT(12)
#define MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE BIT(14)
#define MII_PHY_LED_CTRL 16
#define MII_88E1121_PHY_LED_DEF 0x0030
#define MII_88E1510_PHY_LED_DEF 0x1177
#define MII_88E1510_PHY_LED0_LINK_LED1_ACTIVE 0x1040
#define MII_M1011_PHY_STATUS 0x11
#define MII_M1011_PHY_STATUS_1000 0x8000
#define MII_M1011_PHY_STATUS_100 0x4000
#define MII_M1011_PHY_STATUS_SPD_MASK 0xc000
#define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000
#define MII_M1011_PHY_STATUS_RESOLVED 0x0800
#define MII_M1011_PHY_STATUS_LINK 0x0400
#define MII_88E3016_PHY_SPEC_CTRL 0x10
#define MII_88E3016_DISABLE_SCRAMBLER 0x0200
#define MII_88E3016_AUTO_MDIX_CROSSOVER 0x0030
#define MII_88E1510_GEN_CTRL_REG_1 0x14
#define MII_88E1510_GEN_CTRL_REG_1_MODE_MASK 0x7
#define MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII 0x1 /* SGMII to copper */
#define MII_88E1510_GEN_CTRL_REG_1_RESET 0x8000 /* Soft reset */
#define MII_VCT5_TX_RX_MDI0_COUPLING 0x10
#define MII_VCT5_TX_RX_MDI1_COUPLING 0x11
#define MII_VCT5_TX_RX_MDI2_COUPLING 0x12
#define MII_VCT5_TX_RX_MDI3_COUPLING 0x13
#define MII_VCT5_TX_RX_AMPLITUDE_MASK 0x7f00
#define MII_VCT5_TX_RX_AMPLITUDE_SHIFT 8
#define MII_VCT5_TX_RX_COUPLING_POSITIVE_REFLECTION BIT(15)
#define MII_VCT5_CTRL 0x17
#define MII_VCT5_CTRL_ENABLE BIT(15)
#define MII_VCT5_CTRL_COMPLETE BIT(14)
#define MII_VCT5_CTRL_TX_SAME_CHANNEL (0x0 << 11)
#define MII_VCT5_CTRL_TX0_CHANNEL (0x4 << 11)
#define MII_VCT5_CTRL_TX1_CHANNEL (0x5 << 11)
#define MII_VCT5_CTRL_TX2_CHANNEL (0x6 << 11)
#define MII_VCT5_CTRL_TX3_CHANNEL (0x7 << 11)
#define MII_VCT5_CTRL_SAMPLES_2 (0x0 << 8)
#define MII_VCT5_CTRL_SAMPLES_4 (0x1 << 8)
#define MII_VCT5_CTRL_SAMPLES_8 (0x2 << 8)
#define MII_VCT5_CTRL_SAMPLES_16 (0x3 << 8)
#define MII_VCT5_CTRL_SAMPLES_32 (0x4 << 8)
#define MII_VCT5_CTRL_SAMPLES_64 (0x5 << 8)
#define MII_VCT5_CTRL_SAMPLES_128 (0x6 << 8)
#define MII_VCT5_CTRL_SAMPLES_DEFAULT (0x6 << 8)
#define MII_VCT5_CTRL_SAMPLES_256 (0x7 << 8)
#define MII_VCT5_CTRL_SAMPLES_SHIFT 8
#define MII_VCT5_CTRL_MODE_MAXIMUM_PEEK (0x0 << 6)
#define MII_VCT5_CTRL_MODE_FIRST_LAST_PEEK (0x1 << 6)
#define MII_VCT5_CTRL_MODE_OFFSET (0x2 << 6)
#define MII_VCT5_CTRL_SAMPLE_POINT (0x3 << 6)
#define MII_VCT5_CTRL_PEEK_HYST_DEFAULT 3
#define MII_VCT5_SAMPLE_POINT_DISTANCE 0x18
#define MII_VCT5_SAMPLE_POINT_DISTANCE_MAX 511
#define MII_VCT5_TX_PULSE_CTRL 0x1c
#define MII_VCT5_TX_PULSE_CTRL_DONT_WAIT_LINK_DOWN BIT(12)
#define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_128nS (0x0 << 10)
#define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_96nS (0x1 << 10)
#define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_64nS (0x2 << 10)
#define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_32nS (0x3 << 10)
#define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_SHIFT 10
#define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_1000mV (0x0 << 8)
#define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_750mV (0x1 << 8)
#define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_500mV (0x2 << 8)
#define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_250mV (0x3 << 8)
#define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_SHIFT 8
#define MII_VCT5_TX_PULSE_CTRL_MAX_AMP BIT(7)
#define MII_VCT5_TX_PULSE_CTRL_GT_140m_46_86mV (0x6 << 0)
/* For TDR measurements less than 11 meters, a short pulse should be
* used.
*/
#define TDR_SHORT_CABLE_LENGTH 11
#define MII_VCT7_PAIR_0_DISTANCE 0x10
#define MII_VCT7_PAIR_1_DISTANCE 0x11
#define MII_VCT7_PAIR_2_DISTANCE 0x12
#define MII_VCT7_PAIR_3_DISTANCE 0x13
#define MII_VCT7_RESULTS 0x14
#define MII_VCT7_RESULTS_PAIR3_MASK 0xf000
#define MII_VCT7_RESULTS_PAIR2_MASK 0x0f00
#define MII_VCT7_RESULTS_PAIR1_MASK 0x00f0
#define MII_VCT7_RESULTS_PAIR0_MASK 0x000f
#define MII_VCT7_RESULTS_PAIR3_SHIFT 12
#define MII_VCT7_RESULTS_PAIR2_SHIFT 8
#define MII_VCT7_RESULTS_PAIR1_SHIFT 4
#define MII_VCT7_RESULTS_PAIR0_SHIFT 0
#define MII_VCT7_RESULTS_INVALID 0
#define MII_VCT7_RESULTS_OK 1
#define MII_VCT7_RESULTS_OPEN 2
#define MII_VCT7_RESULTS_SAME_SHORT 3
#define MII_VCT7_RESULTS_CROSS_SHORT 4
#define MII_VCT7_RESULTS_BUSY 9
#define MII_VCT7_CTRL 0x15
#define MII_VCT7_CTRL_RUN_NOW BIT(15)
#define MII_VCT7_CTRL_RUN_ANEG BIT(14)
#define MII_VCT7_CTRL_DISABLE_CROSS BIT(13)
#define MII_VCT7_CTRL_RUN_AFTER_BREAK_LINK BIT(12)
#define MII_VCT7_CTRL_IN_PROGRESS BIT(11)
#define MII_VCT7_CTRL_METERS BIT(10)
#define MII_VCT7_CTRL_CENTIMETERS 0
#define LPA_PAUSE_FIBER 0x180
#define LPA_PAUSE_ASYM_FIBER 0x100
#define NB_FIBER_STATS 1
MODULE_DESCRIPTION("Marvell PHY driver");
MODULE_AUTHOR("Andy Fleming");
MODULE_LICENSE("GPL");
struct marvell_hw_stat {
const char *string;
u8 page;
u8 reg;
u8 bits;
};
static struct marvell_hw_stat marvell_hw_stats[] = {
{ "phy_receive_errors_copper", 0, 21, 16},
{ "phy_idle_errors", 0, 10, 8 },
{ "phy_receive_errors_fiber", 1, 21, 16},
};
struct marvell_priv {
u64 stats[ARRAY_SIZE(marvell_hw_stats)];
char *hwmon_name;
struct device *hwmon_dev;
bool cable_test_tdr;
u32 first;
u32 last;
u32 step;
s8 pair;
};
static int marvell_read_page(struct phy_device *phydev)
{
return __phy_read(phydev, MII_MARVELL_PHY_PAGE);
}
static int marvell_write_page(struct phy_device *phydev, int page)
{
return __phy_write(phydev, MII_MARVELL_PHY_PAGE, page);
}
static int marvell_set_page(struct phy_device *phydev, int page)
{
return phy_write(phydev, MII_MARVELL_PHY_PAGE, page);
}
static int marvell_ack_interrupt(struct phy_device *phydev)
{
int err;
/* Clear the interrupts by reading the reg */
err = phy_read(phydev, MII_M1011_IEVENT);
if (err < 0)
return err;
return 0;
}
static int marvell_config_intr(struct phy_device *phydev)
{
int err;
if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
err = phy_write(phydev, MII_M1011_IMASK,
MII_M1011_IMASK_INIT);
else
err = phy_write(phydev, MII_M1011_IMASK,
MII_M1011_IMASK_CLEAR);
return err;
}
static int marvell_set_polarity(struct phy_device *phydev, int polarity)
{
int reg;
int err;
int val;
/* get the current settings */
reg = phy_read(phydev, MII_M1011_PHY_SCR);
if (reg < 0)
return reg;
val = reg;
val &= ~MII_M1011_PHY_SCR_AUTO_CROSS;
switch (polarity) {
case ETH_TP_MDI:
val |= MII_M1011_PHY_SCR_MDI;
break;
case ETH_TP_MDI_X:
val |= MII_M1011_PHY_SCR_MDI_X;
break;
case ETH_TP_MDI_AUTO:
case ETH_TP_MDI_INVALID:
default:
val |= MII_M1011_PHY_SCR_AUTO_CROSS;
break;
}
if (val != reg) {
/* Set the new polarity value in the register */
err = phy_write(phydev, MII_M1011_PHY_SCR, val);
if (err)
return err;
}
return val != reg;
}
static int marvell_config_aneg(struct phy_device *phydev)
{
int changed = 0;
int err;
err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
if (err < 0)
return err;
changed = err;
err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
MII_M1111_PHY_LED_DIRECT);
if (err < 0)
return err;
err = genphy_config_aneg(phydev);
if (err < 0)
return err;
if (phydev->autoneg != AUTONEG_ENABLE || changed) {
/* A write to speed/duplex bits (that is performed by
* genphy_config_aneg() call above) must be followed by
* a software reset. Otherwise, the write has no effect.
*/
err = genphy_soft_reset(phydev);
if (err < 0)
return err;
}
return 0;
}
static int m88e1101_config_aneg(struct phy_device *phydev)
{
int err;
/* This Marvell PHY has an errata which requires
* that certain registers get written in order
* to restart autonegotiation
*/
err = genphy_soft_reset(phydev);
if (err < 0)
return err;
err = phy_write(phydev, 0x1d, 0x1f);
if (err < 0)
return err;
err = phy_write(phydev, 0x1e, 0x200c);
if (err < 0)
return err;
err = phy_write(phydev, 0x1d, 0x5);
if (err < 0)
return err;
err = phy_write(phydev, 0x1e, 0);
if (err < 0)
return err;
err = phy_write(phydev, 0x1e, 0x100);
if (err < 0)
return err;
return marvell_config_aneg(phydev);
}
#if IS_ENABLED(CONFIG_OF_MDIO)
/* Set and/or override some configuration registers based on the
* marvell,reg-init property stored in the of_node for the phydev.
*
* marvell,reg-init = <reg-page reg mask value>,...;
*
* There may be one or more sets of <reg-page reg mask value>:
*
* reg-page: which register bank to use.
* reg: the register.
* mask: if non-zero, ANDed with existing register value.
* value: ORed with the masked value and written to the regiser.
*
*/
static int marvell_of_reg_init(struct phy_device *phydev)
{
const __be32 *paddr;
int len, i, saved_page, current_page, ret = 0;
if (!phydev->mdio.dev.of_node)
return 0;
paddr = of_get_property(phydev->mdio.dev.of_node,
"marvell,reg-init", &len);
if (!paddr || len < (4 * sizeof(*paddr)))
return 0;
saved_page = phy_save_page(phydev);
if (saved_page < 0)
goto err;
current_page = saved_page;
len /= sizeof(*paddr);
for (i = 0; i < len - 3; i += 4) {
u16 page = be32_to_cpup(paddr + i);
u16 reg = be32_to_cpup(paddr + i + 1);
u16 mask = be32_to_cpup(paddr + i + 2);
u16 val_bits = be32_to_cpup(paddr + i + 3);
int val;
if (page != current_page) {
current_page = page;
ret = marvell_write_page(phydev, page);
if (ret < 0)
goto err;
}
val = 0;
if (mask) {
val = __phy_read(phydev, reg);
if (val < 0) {
ret = val;
goto err;
}
val &= mask;
}
val |= val_bits;
ret = __phy_write(phydev, reg, val);
if (ret < 0)
goto err;
}
err:
return phy_restore_page(phydev, saved_page, ret);
}
#else
static int marvell_of_reg_init(struct phy_device *phydev)
{
return 0;
}
#endif /* CONFIG_OF_MDIO */
static int m88e1121_config_aneg_rgmii_delays(struct phy_device *phydev)
{
int mscr;
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
mscr = MII_88E1121_PHY_MSCR_RX_DELAY |
MII_88E1121_PHY_MSCR_TX_DELAY;
else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
mscr = MII_88E1121_PHY_MSCR_RX_DELAY;
else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
mscr = MII_88E1121_PHY_MSCR_TX_DELAY;
else
mscr = 0;
return phy_modify_paged(phydev, MII_MARVELL_MSCR_PAGE,
MII_88E1121_PHY_MSCR_REG,
MII_88E1121_PHY_MSCR_DELAY_MASK, mscr);
}
static int m88e1121_config_aneg(struct phy_device *phydev)
{
int changed = 0;
int err = 0;
if (phy_interface_is_rgmii(phydev)) {
err = m88e1121_config_aneg_rgmii_delays(phydev);
if (err < 0)
return err;
}
err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
if (err < 0)
return err;
changed = err;
err = genphy_config_aneg(phydev);
if (err < 0)
return err;
if (phydev->autoneg != AUTONEG_ENABLE || changed) {
/* A software reset is used to ensure a "commit" of the
* changes is done.
*/
err = genphy_soft_reset(phydev);
if (err < 0)
return err;
}
return 0;
}
static int m88e1318_config_aneg(struct phy_device *phydev)
{
int err;
err = phy_modify_paged(phydev, MII_MARVELL_MSCR_PAGE,
MII_88E1318S_PHY_MSCR1_REG,
0, MII_88E1318S_PHY_MSCR1_PAD_ODD);
if (err < 0)
return err;
return m88e1121_config_aneg(phydev);
}
/**
* linkmode_adv_to_fiber_adv_t
* @advertise: the linkmode advertisement settings
*
* A small helper function that translates linkmode advertisement
* settings to phy autonegotiation advertisements for the MII_ADV
* register for fiber link.
*/
static inline u32 linkmode_adv_to_fiber_adv_t(unsigned long *advertise)
{
u32 result = 0;
if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, advertise))
result |= ADVERTISE_1000XHALF;
if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, advertise))
result |= ADVERTISE_1000XFULL;
if (linkmode_test_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, advertise) &&
linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT, advertise))
result |= ADVERTISE_1000XPSE_ASYM;
else if (linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT, advertise))
result |= ADVERTISE_1000XPAUSE;
return result;
}
/**
* marvell_config_aneg_fiber - restart auto-negotiation or write BMCR
* @phydev: target phy_device struct
*
* Description: If auto-negotiation is enabled, we configure the
* advertising, and then restart auto-negotiation. If it is not
* enabled, then we write the BMCR. Adapted for fiber link in
* some Marvell's devices.
*/
static int marvell_config_aneg_fiber(struct phy_device *phydev)
{
int changed = 0;
int err;
u16 adv;
if (phydev->autoneg != AUTONEG_ENABLE)
return genphy_setup_forced(phydev);
/* Only allow advertising what this PHY supports */
linkmode_and(phydev->advertising, phydev->advertising,
phydev->supported);
adv = linkmode_adv_to_fiber_adv_t(phydev->advertising);
/* Setup fiber advertisement */
err = phy_modify_changed(phydev, MII_ADVERTISE,
ADVERTISE_1000XHALF | ADVERTISE_1000XFULL |
ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM,
adv);
if (err < 0)
return err;
if (err > 0)
changed = 1;
return genphy_check_and_restart_aneg(phydev, changed);
}
static int m88e1510_config_aneg(struct phy_device *phydev)
{
int err;
err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
if (err < 0)
goto error;
/* Configure the copper link first */
err = m88e1318_config_aneg(phydev);
if (err < 0)
goto error;
/* Do not touch the fiber page if we're in copper->sgmii mode */
if (phydev->interface == PHY_INTERFACE_MODE_SGMII)
return 0;
/* Then the fiber link */
err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
if (err < 0)
goto error;
err = marvell_config_aneg_fiber(phydev);
if (err < 0)
goto error;
return marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
error:
marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
return err;
}
static void marvell_config_led(struct phy_device *phydev)
{
u16 def_config;
int err;
switch (MARVELL_PHY_FAMILY_ID(phydev->phy_id)) {
/* Default PHY LED config: LED[0] .. Link, LED[1] .. Activity */
case MARVELL_PHY_FAMILY_ID(MARVELL_PHY_ID_88E1121R):
case MARVELL_PHY_FAMILY_ID(MARVELL_PHY_ID_88E1318S):
def_config = MII_88E1121_PHY_LED_DEF;
break;
/* Default PHY LED config:
* LED[0] .. 1000Mbps Link
* LED[1] .. 100Mbps Link
* LED[2] .. Blink, Activity
*/
case MARVELL_PHY_FAMILY_ID(MARVELL_PHY_ID_88E1510):
if (phydev->dev_flags & MARVELL_PHY_LED0_LINK_LED1_ACTIVE)
def_config = MII_88E1510_PHY_LED0_LINK_LED1_ACTIVE;
else
def_config = MII_88E1510_PHY_LED_DEF;
break;
default:
return;
}
err = phy_write_paged(phydev, MII_MARVELL_LED_PAGE, MII_PHY_LED_CTRL,
def_config);
if (err < 0)
phydev_warn(phydev, "Fail to config marvell phy LED.\n");
}
static int marvell_config_init(struct phy_device *phydev)
{
/* Set defalut LED */
marvell_config_led(phydev);
/* Set registers from marvell,reg-init DT property */
return marvell_of_reg_init(phydev);
}
static int m88e3016_config_init(struct phy_device *phydev)
{
int ret;
/* Enable Scrambler and Auto-Crossover */
ret = phy_modify(phydev, MII_88E3016_PHY_SPEC_CTRL,
MII_88E3016_DISABLE_SCRAMBLER,
MII_88E3016_AUTO_MDIX_CROSSOVER);
if (ret < 0)
return ret;
return marvell_config_init(phydev);
}
static int m88e1111_config_init_hwcfg_mode(struct phy_device *phydev,
u16 mode,
int fibre_copper_auto)
{
if (fibre_copper_auto)
mode |= MII_M1111_HWCFG_FIBER_COPPER_AUTO;
return phy_modify(phydev, MII_M1111_PHY_EXT_SR,
MII_M1111_HWCFG_MODE_MASK |
MII_M1111_HWCFG_FIBER_COPPER_AUTO |
MII_M1111_HWCFG_FIBER_COPPER_RES,
mode);
}
static int m88e1111_config_init_rgmii_delays(struct phy_device *phydev)
{
int delay;
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
delay = MII_M1111_RGMII_RX_DELAY | MII_M1111_RGMII_TX_DELAY;
} else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
delay = MII_M1111_RGMII_RX_DELAY;
} else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
delay = MII_M1111_RGMII_TX_DELAY;
} else {
delay = 0;
}
return phy_modify(phydev, MII_M1111_PHY_EXT_CR,
MII_M1111_RGMII_RX_DELAY | MII_M1111_RGMII_TX_DELAY,
delay);
}
static int m88e1111_config_init_rgmii(struct phy_device *phydev)
{
int temp;
int err;
err = m88e1111_config_init_rgmii_delays(phydev);
if (err < 0)
return err;
temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
if (temp < 0)
return temp;
temp &= ~(MII_M1111_HWCFG_MODE_MASK);
if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES)
temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII;
else
temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII;
return phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
}
static int m88e1111_config_init_sgmii(struct phy_device *phydev)
{
int err;
err = m88e1111_config_init_hwcfg_mode(
phydev,
MII_M1111_HWCFG_MODE_SGMII_NO_CLK,
MII_M1111_HWCFG_FIBER_COPPER_AUTO);
if (err < 0)
return err;
/* make sure copper is selected */
return marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
}
static int m88e1111_config_init_rtbi(struct phy_device *phydev)
{
int err;
err = m88e1111_config_init_rgmii_delays(phydev);
if (err < 0)
return err;
err = m88e1111_config_init_hwcfg_mode(
phydev,
MII_M1111_HWCFG_MODE_RTBI,
MII_M1111_HWCFG_FIBER_COPPER_AUTO);
if (err < 0)
return err;
/* soft reset */
err = genphy_soft_reset(phydev);
if (err < 0)
return err;
return m88e1111_config_init_hwcfg_mode(
phydev,
MII_M1111_HWCFG_MODE_RTBI,
MII_M1111_HWCFG_FIBER_COPPER_AUTO);
}
static int m88e1111_config_init(struct phy_device *phydev)
{
int err;
if (phy_interface_is_rgmii(phydev)) {
err = m88e1111_config_init_rgmii(phydev);
if (err < 0)
return err;
}
if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
err = m88e1111_config_init_sgmii(phydev);
if (err < 0)
return err;
}
if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
err = m88e1111_config_init_rtbi(phydev);
if (err < 0)
return err;
}
err = marvell_of_reg_init(phydev);
if (err < 0)
return err;
return genphy_soft_reset(phydev);
}
static int m88e1111_get_downshift(struct phy_device *phydev, u8 *data)
{
int val, cnt, enable;
val = phy_read(phydev, MII_M1111_PHY_EXT_CR);
if (val < 0)
return val;
enable = FIELD_GET(MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN, val);
cnt = FIELD_GET(MII_M1111_PHY_EXT_CR_DOWNSHIFT_MASK, val) + 1;
*data = enable ? cnt : DOWNSHIFT_DEV_DISABLE;
return 0;
}
static int m88e1111_set_downshift(struct phy_device *phydev, u8 cnt)
{
int val;
if (cnt > MII_M1111_PHY_EXT_CR_DOWNSHIFT_MAX)
return -E2BIG;
if (!cnt)
return phy_clear_bits(phydev, MII_M1111_PHY_EXT_CR,
MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN);
val = MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN;
val |= FIELD_PREP(MII_M1111_PHY_EXT_CR_DOWNSHIFT_MASK, cnt - 1);
return phy_modify(phydev, MII_M1111_PHY_EXT_CR,
MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN |
MII_M1111_PHY_EXT_CR_DOWNSHIFT_MASK,
val);
}
static int m88e1111_get_tunable(struct phy_device *phydev,
struct ethtool_tunable *tuna, void *data)
{
switch (tuna->id) {
case ETHTOOL_PHY_DOWNSHIFT:
return m88e1111_get_downshift(phydev, data);
default:
return -EOPNOTSUPP;
}
}
static int m88e1111_set_tunable(struct phy_device *phydev,
struct ethtool_tunable *tuna, const void *data)
{
switch (tuna->id) {
case ETHTOOL_PHY_DOWNSHIFT:
return m88e1111_set_downshift(phydev, *(const u8 *)data);
default:
return -EOPNOTSUPP;
}
}
static int m88e1011_get_downshift(struct phy_device *phydev, u8 *data)
{
int val, cnt, enable;
val = phy_read(phydev, MII_M1011_PHY_SCR);
if (val < 0)
return val;
enable = FIELD_GET(MII_M1011_PHY_SCR_DOWNSHIFT_EN, val);
cnt = FIELD_GET(MII_M1011_PHY_SCR_DOWNSHIFT_MASK, val) + 1;
*data = enable ? cnt : DOWNSHIFT_DEV_DISABLE;
return 0;
}
static int m88e1011_set_downshift(struct phy_device *phydev, u8 cnt)
{
int val;
if (cnt > MII_M1011_PHY_SCR_DOWNSHIFT_MAX)
return -E2BIG;
if (!cnt)
return phy_clear_bits(phydev, MII_M1011_PHY_SCR,
MII_M1011_PHY_SCR_DOWNSHIFT_EN);
val = MII_M1011_PHY_SCR_DOWNSHIFT_EN;
val |= FIELD_PREP(MII_M1011_PHY_SCR_DOWNSHIFT_MASK, cnt - 1);
return phy_modify(phydev, MII_M1011_PHY_SCR,
MII_M1011_PHY_SCR_DOWNSHIFT_EN |
MII_M1011_PHY_SCR_DOWNSHIFT_MASK,
val);
}
static int m88e1011_get_tunable(struct phy_device *phydev,
struct ethtool_tunable *tuna, void *data)
{
switch (tuna->id) {
case ETHTOOL_PHY_DOWNSHIFT:
return m88e1011_get_downshift(phydev, data);
default:
return -EOPNOTSUPP;
}
}
static int m88e1011_set_tunable(struct phy_device *phydev,
struct ethtool_tunable *tuna, const void *data)
{
switch (tuna->id) {
case ETHTOOL_PHY_DOWNSHIFT:
return m88e1011_set_downshift(phydev, *(const u8 *)data);
default:
return -EOPNOTSUPP;
}
}
static int m88e1116r_config_init(struct phy_device *phydev)
{
int err;
err = genphy_soft_reset(phydev);
if (err < 0)
return err;
msleep(500);
err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
if (err < 0)
return err;
err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
if (err < 0)
return err;
err = m88e1011_set_downshift(phydev, 8);
if (err < 0)
return err;
if (phy_interface_is_rgmii(phydev)) {
err = m88e1121_config_aneg_rgmii_delays(phydev);
if (err < 0)
return err;
}
err = genphy_soft_reset(phydev);
if (err < 0)
return err;
return marvell_config_init(phydev);
}
static int m88e1318_config_init(struct phy_device *phydev)
{
if (phy_interrupt_is_valid(phydev)) {
int err = phy_modify_paged(