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Srinivas-Kandagatlabroonie
Srinivas-Kandagatla
authored and
broonie
committedSep 10, 2020
ASoC: q6dsp: q6afe: add support to Codec DMA ports
New LPASS supports various codec macros, DSP firmware already has support to those ports. Add corresponding configuration support to those ports in adsp drivers. Signed-off-by: Srinivas Kandagatla <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
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‎include/dt-bindings/sound/qcom,q6afe.h

+22
Original file line numberDiff line numberDiff line change
@@ -107,6 +107,28 @@
107107
#define QUINARY_TDM_RX_7 102
108108
#define QUINARY_TDM_TX_7 103
109109
#define DISPLAY_PORT_RX 104
110+
#define WSA_CODEC_DMA_RX_0 105
111+
#define WSA_CODEC_DMA_TX_0 106
112+
#define WSA_CODEC_DMA_RX_1 107
113+
#define WSA_CODEC_DMA_TX_1 108
114+
#define WSA_CODEC_DMA_TX_2 109
115+
#define VA_CODEC_DMA_TX_0 110
116+
#define VA_CODEC_DMA_TX_1 111
117+
#define VA_CODEC_DMA_TX_2 112
118+
#define RX_CODEC_DMA_RX_0 113
119+
#define TX_CODEC_DMA_TX_0 114
120+
#define RX_CODEC_DMA_RX_1 115
121+
#define TX_CODEC_DMA_TX_1 116
122+
#define RX_CODEC_DMA_RX_2 117
123+
#define TX_CODEC_DMA_TX_2 118
124+
#define RX_CODEC_DMA_RX_3 119
125+
#define TX_CODEC_DMA_TX_3 120
126+
#define RX_CODEC_DMA_RX_4 121
127+
#define TX_CODEC_DMA_TX_4 122
128+
#define RX_CODEC_DMA_RX_5 123
129+
#define TX_CODEC_DMA_TX_5 124
130+
#define RX_CODEC_DMA_RX_6 125
131+
#define RX_CODEC_DMA_RX_7 126
110132

111133
#endif /* __DT_BINDINGS_Q6_AFE_H__ */
112134

‎sound/soc/qcom/qdsp6/q6afe.c

+126-1
Original file line numberDiff line numberDiff line change
@@ -42,6 +42,7 @@
4242
#define AFE_PARAM_ID_I2S_CONFIG 0x0001020D
4343
#define AFE_PARAM_ID_TDM_CONFIG 0x0001029D
4444
#define AFE_PARAM_ID_PORT_SLOT_MAPPING_CONFIG 0x00010297
45+
#define AFE_PARAM_ID_CODEC_DMA_CONFIG 0x000102B8
4546

4647
/* I2S config specific */
4748
#define AFE_API_VERSION_I2S_CONFIG 0x1
@@ -299,12 +300,58 @@
299300
#define AFE_PORT_ID_QUINARY_TDM_TX_7 \
300301
(AFE_PORT_ID_QUINARY_TDM_TX + 0x0E)
301302

303+
/* AFE WSA Codec DMA Rx port 0 */
304+
#define AFE_PORT_ID_WSA_CODEC_DMA_RX_0 0xB000
305+
/* AFE WSA Codec DMA Tx port 0 */
306+
#define AFE_PORT_ID_WSA_CODEC_DMA_TX_0 0xB001
307+
/* AFE WSA Codec DMA Rx port 1 */
308+
#define AFE_PORT_ID_WSA_CODEC_DMA_RX_1 0xB002
309+
/* AFE WSA Codec DMA Tx port 1 */
310+
#define AFE_PORT_ID_WSA_CODEC_DMA_TX_1 0xB003
311+
/* AFE WSA Codec DMA Tx port 2 */
312+
#define AFE_PORT_ID_WSA_CODEC_DMA_TX_2 0xB005
313+
/* AFE VA Codec DMA Tx port 0 */
314+
#define AFE_PORT_ID_VA_CODEC_DMA_TX_0 0xB021
315+
/* AFE VA Codec DMA Tx port 1 */
316+
#define AFE_PORT_ID_VA_CODEC_DMA_TX_1 0xB023
317+
/* AFE VA Codec DMA Tx port 2 */
318+
#define AFE_PORT_ID_VA_CODEC_DMA_TX_2 0xB025
319+
/* AFE Rx Codec DMA Rx port 0 */
320+
#define AFE_PORT_ID_RX_CODEC_DMA_RX_0 0xB030
321+
/* AFE Tx Codec DMA Tx port 0 */
322+
#define AFE_PORT_ID_TX_CODEC_DMA_TX_0 0xB031
323+
/* AFE Rx Codec DMA Rx port 1 */
324+
#define AFE_PORT_ID_RX_CODEC_DMA_RX_1 0xB032
325+
/* AFE Tx Codec DMA Tx port 1 */
326+
#define AFE_PORT_ID_TX_CODEC_DMA_TX_1 0xB033
327+
/* AFE Rx Codec DMA Rx port 2 */
328+
#define AFE_PORT_ID_RX_CODEC_DMA_RX_2 0xB034
329+
/* AFE Tx Codec DMA Tx port 2 */
330+
#define AFE_PORT_ID_TX_CODEC_DMA_TX_2 0xB035
331+
/* AFE Rx Codec DMA Rx port 3 */
332+
#define AFE_PORT_ID_RX_CODEC_DMA_RX_3 0xB036
333+
/* AFE Tx Codec DMA Tx port 3 */
334+
#define AFE_PORT_ID_TX_CODEC_DMA_TX_3 0xB037
335+
/* AFE Rx Codec DMA Rx port 4 */
336+
#define AFE_PORT_ID_RX_CODEC_DMA_RX_4 0xB038
337+
/* AFE Tx Codec DMA Tx port 4 */
338+
#define AFE_PORT_ID_TX_CODEC_DMA_TX_4 0xB039
339+
/* AFE Rx Codec DMA Rx port 5 */
340+
#define AFE_PORT_ID_RX_CODEC_DMA_RX_5 0xB03A
341+
/* AFE Tx Codec DMA Tx port 5 */
342+
#define AFE_PORT_ID_TX_CODEC_DMA_TX_5 0xB03B
343+
/* AFE Rx Codec DMA Rx port 6 */
344+
#define AFE_PORT_ID_RX_CODEC_DMA_RX_6 0xB03C
345+
/* AFE Rx Codec DMA Rx port 7 */
346+
#define AFE_PORT_ID_RX_CODEC_DMA_RX_7 0xB03E
347+
302348
#define Q6AFE_LPASS_MODE_CLK1_VALID 1
303349
#define Q6AFE_LPASS_MODE_CLK2_VALID 2
304350
#define Q6AFE_LPASS_CLK_SRC_INTERNAL 1
305351
#define Q6AFE_LPASS_CLK_ROOT_DEFAULT 0
306352
#define AFE_API_VERSION_TDM_CONFIG 1
307353
#define AFE_API_VERSION_SLOT_MAPPING_CONFIG 1
354+
#define AFE_API_VERSION_CODEC_DMA_CONFIG 1
308355

309356
#define TIMEOUT_MS 1000
310357
#define AFE_CMD_RESP_AVAIL 0
@@ -448,11 +495,21 @@ struct afe_param_id_tdm_cfg {
448495
u32 slot_mask;
449496
} __packed;
450497

498+
struct afe_param_id_cdc_dma_cfg {
499+
u32 cdc_dma_cfg_minor_version;
500+
u32 sample_rate;
501+
u16 bit_width;
502+
u16 data_format;
503+
u16 num_channels;
504+
u16 active_channels_mask;
505+
} __packed;
506+
451507
union afe_port_config {
452508
struct afe_param_id_hdmi_multi_chan_audio_cfg hdmi_multi_ch;
453509
struct afe_param_id_slimbus_cfg slim_cfg;
454510
struct afe_param_id_i2s_cfg i2s_cfg;
455511
struct afe_param_id_tdm_cfg tdm_cfg;
512+
struct afe_param_id_cdc_dma_cfg dma_cfg;
456513
} __packed;
457514

458515

@@ -707,6 +764,50 @@ static struct afe_port_map port_maps[AFE_PORT_MAX] = {
707764
QUINARY_TDM_TX_7, 0, 1},
708765
[DISPLAY_PORT_RX] = { AFE_PORT_ID_HDMI_OVER_DP_RX,
709766
DISPLAY_PORT_RX, 1, 1},
767+
[WSA_CODEC_DMA_RX_0] = { AFE_PORT_ID_WSA_CODEC_DMA_RX_0,
768+
WSA_CODEC_DMA_RX_0, 1, 1},
769+
[WSA_CODEC_DMA_TX_0] = { AFE_PORT_ID_WSA_CODEC_DMA_TX_0,
770+
WSA_CODEC_DMA_TX_0, 0, 1},
771+
[WSA_CODEC_DMA_RX_1] = { AFE_PORT_ID_WSA_CODEC_DMA_RX_1,
772+
WSA_CODEC_DMA_RX_1, 1, 1},
773+
[WSA_CODEC_DMA_TX_1] = { AFE_PORT_ID_WSA_CODEC_DMA_TX_1,
774+
WSA_CODEC_DMA_TX_1, 0, 1},
775+
[WSA_CODEC_DMA_TX_2] = { AFE_PORT_ID_WSA_CODEC_DMA_TX_2,
776+
WSA_CODEC_DMA_TX_2, 0, 1},
777+
[VA_CODEC_DMA_TX_0] = { AFE_PORT_ID_VA_CODEC_DMA_TX_0,
778+
VA_CODEC_DMA_TX_0, 0, 1},
779+
[VA_CODEC_DMA_TX_1] = { AFE_PORT_ID_VA_CODEC_DMA_TX_1,
780+
VA_CODEC_DMA_TX_1, 0, 1},
781+
[VA_CODEC_DMA_TX_2] = { AFE_PORT_ID_VA_CODEC_DMA_TX_2,
782+
VA_CODEC_DMA_TX_2, 0, 1},
783+
[RX_CODEC_DMA_RX_0] = { AFE_PORT_ID_RX_CODEC_DMA_RX_0,
784+
RX_CODEC_DMA_RX_0, 1, 1},
785+
[TX_CODEC_DMA_TX_0] = { AFE_PORT_ID_TX_CODEC_DMA_TX_0,
786+
TX_CODEC_DMA_TX_0, 0, 1},
787+
[RX_CODEC_DMA_RX_1] = { AFE_PORT_ID_RX_CODEC_DMA_RX_1,
788+
RX_CODEC_DMA_RX_1, 1, 1},
789+
[TX_CODEC_DMA_TX_1] = { AFE_PORT_ID_TX_CODEC_DMA_TX_1,
790+
TX_CODEC_DMA_TX_1, 0, 1},
791+
[RX_CODEC_DMA_RX_2] = { AFE_PORT_ID_RX_CODEC_DMA_RX_2,
792+
RX_CODEC_DMA_RX_2, 1, 1},
793+
[TX_CODEC_DMA_TX_2] = { AFE_PORT_ID_TX_CODEC_DMA_TX_2,
794+
TX_CODEC_DMA_TX_2, 0, 1},
795+
[RX_CODEC_DMA_RX_3] = { AFE_PORT_ID_RX_CODEC_DMA_RX_3,
796+
RX_CODEC_DMA_RX_3, 1, 1},
797+
[TX_CODEC_DMA_TX_3] = { AFE_PORT_ID_TX_CODEC_DMA_TX_3,
798+
TX_CODEC_DMA_TX_3, 0, 1},
799+
[RX_CODEC_DMA_RX_4] = { AFE_PORT_ID_RX_CODEC_DMA_RX_4,
800+
RX_CODEC_DMA_RX_4, 1, 1},
801+
[TX_CODEC_DMA_TX_4] = { AFE_PORT_ID_TX_CODEC_DMA_TX_4,
802+
TX_CODEC_DMA_TX_4, 0, 1},
803+
[RX_CODEC_DMA_RX_5] = { AFE_PORT_ID_RX_CODEC_DMA_RX_5,
804+
RX_CODEC_DMA_RX_5, 1, 1},
805+
[TX_CODEC_DMA_TX_5] = { AFE_PORT_ID_TX_CODEC_DMA_TX_5,
806+
TX_CODEC_DMA_TX_5, 0, 1},
807+
[RX_CODEC_DMA_RX_6] = { AFE_PORT_ID_RX_CODEC_DMA_RX_6,
808+
RX_CODEC_DMA_RX_6, 1, 1},
809+
[RX_CODEC_DMA_RX_7] = { AFE_PORT_ID_RX_CODEC_DMA_RX_7,
810+
RX_CODEC_DMA_RX_7, 1, 1},
710811
};
711812

712813
static void q6afe_port_free(struct kref *ref)
@@ -1288,6 +1389,28 @@ int q6afe_i2s_port_prepare(struct q6afe_port *port, struct q6afe_i2s_cfg *cfg)
12881389
}
12891390
EXPORT_SYMBOL_GPL(q6afe_i2s_port_prepare);
12901391

1392+
/**
1393+
* q6afe_dam_port_prepare() - Prepare dma afe port.
1394+
*
1395+
* @port: Instance of afe port
1396+
* @cfg: DMA configuration for the afe port
1397+
*
1398+
*/
1399+
void q6afe_cdc_dma_port_prepare(struct q6afe_port *port,
1400+
struct q6afe_cdc_dma_cfg *cfg)
1401+
{
1402+
union afe_port_config *pcfg = &port->port_cfg;
1403+
struct afe_param_id_cdc_dma_cfg *dma_cfg = &pcfg->dma_cfg;
1404+
1405+
dma_cfg->cdc_dma_cfg_minor_version = AFE_API_VERSION_CODEC_DMA_CONFIG;
1406+
dma_cfg->sample_rate = cfg->sample_rate;
1407+
dma_cfg->bit_width = cfg->bit_width;
1408+
dma_cfg->data_format = cfg->data_format;
1409+
dma_cfg->num_channels = cfg->num_channels;
1410+
if (!cfg->active_channels_mask)
1411+
dma_cfg->active_channels_mask = (1 << cfg->num_channels) - 1;
1412+
}
1413+
EXPORT_SYMBOL_GPL(q6afe_cdc_dma_port_prepare);
12911414
/**
12921415
* q6afe_port_start() - Start a afe port
12931416
*
@@ -1420,7 +1543,9 @@ struct q6afe_port *q6afe_port_get_from_id(struct device *dev, int id)
14201543
case AFE_PORT_ID_PRIMARY_TDM_RX ... AFE_PORT_ID_QUINARY_TDM_TX_7:
14211544
cfg_type = AFE_PARAM_ID_TDM_CONFIG;
14221545
break;
1423-
1546+
case AFE_PORT_ID_WSA_CODEC_DMA_RX_0 ... AFE_PORT_ID_RX_CODEC_DMA_RX_7:
1547+
cfg_type = AFE_PARAM_ID_CODEC_DMA_CONFIG;
1548+
break;
14241549
default:
14251550
dev_err(dev, "Invalid port id 0x%x\n", port_id);
14261551
return ERR_PTR(-EINVAL);

‎sound/soc/qcom/qdsp6/q6afe.h

+13-1
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55

66
#include <dt-bindings/sound/qcom,q6afe.h>
77

8-
#define AFE_PORT_MAX 105
8+
#define AFE_PORT_MAX 127
99

1010
#define MSM_AFE_PORT_TYPE_RX 0
1111
#define MSM_AFE_PORT_TYPE_TX 1
@@ -184,11 +184,21 @@ struct q6afe_tdm_cfg {
184184
u16 ch_mapping[AFE_MAX_CHAN_COUNT];
185185
};
186186

187+
struct q6afe_cdc_dma_cfg {
188+
u16 sample_rate;
189+
u16 bit_width;
190+
u16 data_format;
191+
u16 num_channels;
192+
u16 active_channels_mask;
193+
};
194+
195+
187196
struct q6afe_port_config {
188197
struct q6afe_hdmi_cfg hdmi;
189198
struct q6afe_slim_cfg slim;
190199
struct q6afe_i2s_cfg i2s_cfg;
191200
struct q6afe_tdm_cfg tdm;
201+
struct q6afe_cdc_dma_cfg dma_cfg;
192202
};
193203

194204
struct q6afe_port;
@@ -204,6 +214,8 @@ void q6afe_slim_port_prepare(struct q6afe_port *port,
204214
struct q6afe_slim_cfg *cfg);
205215
int q6afe_i2s_port_prepare(struct q6afe_port *port, struct q6afe_i2s_cfg *cfg);
206216
void q6afe_tdm_port_prepare(struct q6afe_port *port, struct q6afe_tdm_cfg *cfg);
217+
void q6afe_cdc_dma_port_prepare(struct q6afe_port *port,
218+
struct q6afe_cdc_dma_cfg *cfg);
207219

208220
int q6afe_port_set_sysclk(struct q6afe_port *port, int clk_id,
209221
int clk_src, int clk_root,

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