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wm5110-tables.c
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/*
* wm5110-tables.c -- WM5110 data tables
*
* Copyright 2012 Wolfson Microelectronics plc
*
* Author: Mark Brown <[email protected]>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/mfd/arizona/core.h>
#include <linux/mfd/arizona/registers.h>
#include <linux/device.h>
#include "arizona.h"
#define WM5110_NUM_AOD_ISR 2
#define WM5110_NUM_ISR 5
static const struct reg_sequence wm5110_reva_patch[] = {
{ 0x80, 0x3 },
{ 0x44, 0x20 },
{ 0x45, 0x40 },
{ 0x46, 0x60 },
{ 0x47, 0x80 },
{ 0x48, 0xa0 },
{ 0x51, 0x13 },
{ 0x52, 0x33 },
{ 0x53, 0x53 },
{ 0x54, 0x73 },
{ 0x55, 0x75 },
{ 0x56, 0xb3 },
{ 0x2ef, 0x124 },
{ 0x2ef, 0x124 },
{ 0x2f0, 0x124 },
{ 0x2f0, 0x124 },
{ 0x2f1, 0x124 },
{ 0x2f1, 0x124 },
{ 0x2f2, 0x124 },
{ 0x2f2, 0x124 },
{ 0x2f3, 0x124 },
{ 0x2f3, 0x124 },
{ 0x2f4, 0x124 },
{ 0x2f4, 0x124 },
{ 0x2eb, 0x60 },
{ 0x2ec, 0x60 },
{ 0x2ed, 0x60 },
{ 0xc30, 0x3e3e },
{ 0xc30, 0x3e3e },
{ 0xc31, 0x3e },
{ 0xc32, 0x3e3e },
{ 0xc32, 0x3e3e },
{ 0xc33, 0x3e3e },
{ 0xc33, 0x3e3e },
{ 0xc34, 0x3e3e },
{ 0xc34, 0x3e3e },
{ 0xc35, 0x3e3e },
{ 0xc35, 0x3e3e },
{ 0xc36, 0x3e3e },
{ 0xc36, 0x3e3e },
{ 0xc37, 0x3e3e },
{ 0xc37, 0x3e3e },
{ 0xc38, 0x3e3e },
{ 0xc38, 0x3e3e },
{ 0xc30, 0x3e3e },
{ 0xc30, 0x3e3e },
{ 0xc39, 0x3e3e },
{ 0xc39, 0x3e3e },
{ 0xc3a, 0x3e3e },
{ 0xc3a, 0x3e3e },
{ 0xc3b, 0x3e3e },
{ 0xc3b, 0x3e3e },
{ 0xc3c, 0x3e },
{ 0x201, 0x18a5 },
{ 0x201, 0x18a5 },
{ 0x201, 0x18a5 },
{ 0x202, 0x4100 },
{ 0x460, 0xc00 },
{ 0x461, 0x8000 },
{ 0x462, 0xc01 },
{ 0x463, 0x50f0 },
{ 0x464, 0xc01 },
{ 0x465, 0x4820 },
{ 0x466, 0xc01 },
{ 0x466, 0xc01 },
{ 0x467, 0x4040 },
{ 0x468, 0xc01 },
{ 0x468, 0xc01 },
{ 0x469, 0x3940 },
{ 0x46a, 0xc01 },
{ 0x46a, 0xc01 },
{ 0x46a, 0xc01 },
{ 0x46b, 0x3310 },
{ 0x46c, 0x801 },
{ 0x46c, 0x801 },
{ 0x46d, 0x2d80 },
{ 0x46e, 0x801 },
{ 0x46e, 0x801 },
{ 0x46f, 0x2890 },
{ 0x470, 0x801 },
{ 0x470, 0x801 },
{ 0x471, 0x1990 },
{ 0x472, 0x801 },
{ 0x472, 0x801 },
{ 0x473, 0x1450 },
{ 0x474, 0x801 },
{ 0x474, 0x801 },
{ 0x474, 0x801 },
{ 0x475, 0x1020 },
{ 0x476, 0x801 },
{ 0x476, 0x801 },
{ 0x476, 0x801 },
{ 0x477, 0xcd0 },
{ 0x478, 0x806 },
{ 0x478, 0x806 },
{ 0x479, 0xa30 },
{ 0x47a, 0x806 },
{ 0x47a, 0x806 },
{ 0x47b, 0x810 },
{ 0x47c, 0x80e },
{ 0x47c, 0x80e },
{ 0x47d, 0x510 },
{ 0x47e, 0x81f },
{ 0x47e, 0x81f },
{ 0x2DB, 0x0A00 },
{ 0x2DD, 0x0023 },
{ 0x2DF, 0x0102 },
{ 0x80, 0x0 },
{ 0xC20, 0x0002 },
{ 0x209, 0x002A },
};
static const struct reg_sequence wm5110_revb_patch[] = {
{ 0x80, 0x3 },
{ 0x36e, 0x0210 },
{ 0x370, 0x0210 },
{ 0x372, 0x0210 },
{ 0x374, 0x0210 },
{ 0x376, 0x0210 },
{ 0x378, 0x0210 },
{ 0x36d, 0x0028 },
{ 0x36f, 0x0028 },
{ 0x371, 0x0028 },
{ 0x373, 0x0028 },
{ 0x375, 0x0028 },
{ 0x377, 0x0028 },
{ 0x280, 0x2002 },
{ 0x44, 0x20 },
{ 0x45, 0x40 },
{ 0x46, 0x60 },
{ 0x47, 0x80 },
{ 0x48, 0xa0 },
{ 0x51, 0x13 },
{ 0x52, 0x33 },
{ 0x53, 0x53 },
{ 0x54, 0x73 },
{ 0x55, 0x93 },
{ 0x56, 0xb3 },
{ 0xc30, 0x3e3e },
{ 0xc31, 0x3e },
{ 0xc32, 0x3e3e },
{ 0xc33, 0x3e3e },
{ 0xc34, 0x3e3e },
{ 0xc35, 0x3e3e },
{ 0xc36, 0x3e3e },
{ 0xc37, 0x3e3e },
{ 0xc38, 0x3e3e },
{ 0xc39, 0x3e3e },
{ 0xc3a, 0x3e3e },
{ 0xc3b, 0x3e3e },
{ 0xc3c, 0x3e },
{ 0x201, 0x18a5 },
{ 0x202, 0x4100 },
{ 0x460, 0x0c40 },
{ 0x461, 0x8000 },
{ 0x462, 0x0c41 },
{ 0x463, 0x4820 },
{ 0x464, 0x0c41 },
{ 0x465, 0x4040 },
{ 0x466, 0x0841 },
{ 0x467, 0x3940 },
{ 0x468, 0x0841 },
{ 0x469, 0x2030 },
{ 0x46a, 0x0842 },
{ 0x46b, 0x1990 },
{ 0x46c, 0x08c2 },
{ 0x46d, 0x1450 },
{ 0x46e, 0x08c6 },
{ 0x46f, 0x1020 },
{ 0x470, 0x08c6 },
{ 0x471, 0x0cd0 },
{ 0x472, 0x08c6 },
{ 0x473, 0x0a30 },
{ 0x474, 0x0442 },
{ 0x475, 0x0660 },
{ 0x476, 0x0446 },
{ 0x477, 0x0510 },
{ 0x478, 0x04c6 },
{ 0x479, 0x0400 },
{ 0x47a, 0x04ce },
{ 0x47b, 0x0330 },
{ 0x47c, 0x05df },
{ 0x47d, 0x0001 },
{ 0x47e, 0x07ff },
{ 0x2db, 0x0a00 },
{ 0x2dd, 0x0023 },
{ 0x2df, 0x0102 },
{ 0x2ef, 0x924 },
{ 0x2f0, 0x924 },
{ 0x2f1, 0x924 },
{ 0x2f2, 0x924 },
{ 0x2f3, 0x924 },
{ 0x2f4, 0x924 },
{ 0x2eb, 0x60 },
{ 0x2ec, 0x60 },
{ 0x2ed, 0x60 },
{ 0x4f2, 0x33e },
{ 0x458, 0x0000 },
{ 0x15a, 0x0003 },
{ 0x80, 0x0 },
};
static const struct reg_sequence wm5110_revd_patch[] = {
{ 0x80, 0x3 },
{ 0x80, 0x3 },
{ 0x393, 0x27 },
{ 0x394, 0x27 },
{ 0x395, 0x27 },
{ 0x396, 0x27 },
{ 0x397, 0x27 },
{ 0x398, 0x26 },
{ 0x221, 0x90 },
{ 0x211, 0x8 },
{ 0x36c, 0x1fb },
{ 0x26e, 0x64 },
{ 0x26f, 0xea },
{ 0x270, 0x1f16 },
{ 0x51b, 0x1 },
{ 0x55b, 0x1 },
{ 0x59b, 0x1 },
{ 0x4f0, 0x633 },
{ 0x441, 0xc059 },
{ 0x209, 0x27 },
{ 0x80, 0x0 },
{ 0x80, 0x0 },
};
/* Add extra headphone write sequence locations */
static const struct reg_sequence wm5110_reve_patch[] = {
{ 0x80, 0x3 },
{ 0x80, 0x3 },
{ 0x4b, 0x138 },
{ 0x4c, 0x13d },
{ 0x80, 0x0 },
{ 0x80, 0x0 },
};
/* We use a function so we can use ARRAY_SIZE() */
int wm5110_patch(struct arizona *arizona)
{
switch (arizona->rev) {
case 0:
return regmap_register_patch(arizona->regmap,
wm5110_reva_patch,
ARRAY_SIZE(wm5110_reva_patch));
case 1:
return regmap_register_patch(arizona->regmap,
wm5110_revb_patch,
ARRAY_SIZE(wm5110_revb_patch));
case 3:
return regmap_register_patch(arizona->regmap,
wm5110_revd_patch,
ARRAY_SIZE(wm5110_revd_patch));
default:
return regmap_register_patch(arizona->regmap,
wm5110_reve_patch,
ARRAY_SIZE(wm5110_reve_patch));
}
}
EXPORT_SYMBOL_GPL(wm5110_patch);
static const struct regmap_irq wm5110_aod_irqs[ARIZONA_NUM_IRQ] = {
[ARIZONA_IRQ_MICD_CLAMP_FALL] = {
.mask = ARIZONA_MICD_CLAMP_FALL_EINT1
},
[ARIZONA_IRQ_MICD_CLAMP_RISE] = {
.mask = ARIZONA_MICD_CLAMP_RISE_EINT1
},
[ARIZONA_IRQ_GP5_FALL] = { .mask = ARIZONA_GP5_FALL_EINT1 },
[ARIZONA_IRQ_GP5_RISE] = { .mask = ARIZONA_GP5_RISE_EINT1 },
[ARIZONA_IRQ_JD_FALL] = { .mask = ARIZONA_JD1_FALL_EINT1 },
[ARIZONA_IRQ_JD_RISE] = { .mask = ARIZONA_JD1_RISE_EINT1 },
};
const struct regmap_irq_chip wm5110_aod = {
.name = "wm5110 AOD",
.status_base = ARIZONA_AOD_IRQ1,
.mask_base = ARIZONA_AOD_IRQ_MASK_IRQ1,
.ack_base = ARIZONA_AOD_IRQ1,
.wake_base = ARIZONA_WAKE_CONTROL,
.wake_invert = 1,
.num_regs = 1,
.irqs = wm5110_aod_irqs,
.num_irqs = ARRAY_SIZE(wm5110_aod_irqs),
};
EXPORT_SYMBOL_GPL(wm5110_aod);
static const struct regmap_irq wm5110_irqs[ARIZONA_NUM_IRQ] = {
[ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 },
[ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 },
[ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 },
[ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 },
[ARIZONA_IRQ_DSP4_RAM_RDY] = {
.reg_offset = 1, .mask = ARIZONA_DSP4_RAM_RDY_EINT1
},
[ARIZONA_IRQ_DSP3_RAM_RDY] = {
.reg_offset = 1, .mask = ARIZONA_DSP3_RAM_RDY_EINT1
},
[ARIZONA_IRQ_DSP2_RAM_RDY] = {
.reg_offset = 1, .mask = ARIZONA_DSP2_RAM_RDY_EINT1
},
[ARIZONA_IRQ_DSP1_RAM_RDY] = {
.reg_offset = 1, .mask = ARIZONA_DSP1_RAM_RDY_EINT1
},
[ARIZONA_IRQ_DSP_IRQ8] = {
.reg_offset = 1, .mask = ARIZONA_DSP_IRQ8_EINT1
},
[ARIZONA_IRQ_DSP_IRQ7] = {
.reg_offset = 1, .mask = ARIZONA_DSP_IRQ7_EINT1
},
[ARIZONA_IRQ_DSP_IRQ6] = {
.reg_offset = 1, .mask = ARIZONA_DSP_IRQ6_EINT1
},
[ARIZONA_IRQ_DSP_IRQ5] = {
.reg_offset = 1, .mask = ARIZONA_DSP_IRQ5_EINT1
},
[ARIZONA_IRQ_DSP_IRQ4] = {
.reg_offset = 1, .mask = ARIZONA_DSP_IRQ4_EINT1
},
[ARIZONA_IRQ_DSP_IRQ3] = {
.reg_offset = 1, .mask = ARIZONA_DSP_IRQ3_EINT1
},
[ARIZONA_IRQ_DSP_IRQ2] = {
.reg_offset = 1, .mask = ARIZONA_DSP_IRQ2_EINT1
},
[ARIZONA_IRQ_DSP_IRQ1] = {
.reg_offset = 1, .mask = ARIZONA_DSP_IRQ1_EINT1
},
[ARIZONA_IRQ_SPK_OVERHEAT_WARN] = {
.reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_WARN_EINT1
},
[ARIZONA_IRQ_SPK_OVERHEAT] = {
.reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_EINT1
},
[ARIZONA_IRQ_HPDET] = {
.reg_offset = 2, .mask = ARIZONA_HPDET_EINT1
},
[ARIZONA_IRQ_MICDET] = {
.reg_offset = 2, .mask = ARIZONA_MICDET_EINT1
},
[ARIZONA_IRQ_WSEQ_DONE] = {
.reg_offset = 2, .mask = ARIZONA_WSEQ_DONE_EINT1
},
[ARIZONA_IRQ_DRC2_SIG_DET] = {
.reg_offset = 2, .mask = ARIZONA_DRC2_SIG_DET_EINT1
},
[ARIZONA_IRQ_DRC1_SIG_DET] = {
.reg_offset = 2, .mask = ARIZONA_DRC1_SIG_DET_EINT1
},
[ARIZONA_IRQ_ASRC2_LOCK] = {
.reg_offset = 2, .mask = ARIZONA_ASRC2_LOCK_EINT1
},
[ARIZONA_IRQ_ASRC1_LOCK] = {
.reg_offset = 2, .mask = ARIZONA_ASRC1_LOCK_EINT1
},
[ARIZONA_IRQ_UNDERCLOCKED] = {
.reg_offset = 2, .mask = ARIZONA_UNDERCLOCKED_EINT1
},
[ARIZONA_IRQ_OVERCLOCKED] = {
.reg_offset = 2, .mask = ARIZONA_OVERCLOCKED_EINT1
},
[ARIZONA_IRQ_FLL2_LOCK] = {
.reg_offset = 2, .mask = ARIZONA_FLL2_LOCK_EINT1
},
[ARIZONA_IRQ_FLL1_LOCK] = {
.reg_offset = 2, .mask = ARIZONA_FLL1_LOCK_EINT1
},
[ARIZONA_IRQ_CLKGEN_ERR] = {
.reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_EINT1
},
[ARIZONA_IRQ_CLKGEN_ERR_ASYNC] = {
.reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_ASYNC_EINT1
},
[ARIZONA_IRQ_ASRC_CFG_ERR] = {
.reg_offset = 3, .mask = ARIZONA_ASRC_CFG_ERR_EINT1
},
[ARIZONA_IRQ_AIF3_ERR] = {
.reg_offset = 3, .mask = ARIZONA_AIF3_ERR_EINT1
},
[ARIZONA_IRQ_AIF2_ERR] = {
.reg_offset = 3, .mask = ARIZONA_AIF2_ERR_EINT1
},
[ARIZONA_IRQ_AIF1_ERR] = {
.reg_offset = 3, .mask = ARIZONA_AIF1_ERR_EINT1
},
[ARIZONA_IRQ_CTRLIF_ERR] = {
.reg_offset = 3, .mask = ARIZONA_CTRLIF_ERR_EINT1
},
[ARIZONA_IRQ_MIXER_DROPPED_SAMPLES] = {
.reg_offset = 3, .mask = ARIZONA_MIXER_DROPPED_SAMPLE_EINT1
},
[ARIZONA_IRQ_ASYNC_CLK_ENA_LOW] = {
.reg_offset = 3, .mask = ARIZONA_ASYNC_CLK_ENA_LOW_EINT1
},
[ARIZONA_IRQ_SYSCLK_ENA_LOW] = {
.reg_offset = 3, .mask = ARIZONA_SYSCLK_ENA_LOW_EINT1
},
[ARIZONA_IRQ_ISRC1_CFG_ERR] = {
.reg_offset = 3, .mask = ARIZONA_ISRC1_CFG_ERR_EINT1
},
[ARIZONA_IRQ_ISRC2_CFG_ERR] = {
.reg_offset = 3, .mask = ARIZONA_ISRC2_CFG_ERR_EINT1
},
[ARIZONA_IRQ_HP3R_DONE] = {
.reg_offset = 3, .mask = ARIZONA_HP3R_DONE_EINT1
},
[ARIZONA_IRQ_HP3L_DONE] = {
.reg_offset = 3, .mask = ARIZONA_HP3L_DONE_EINT1
},
[ARIZONA_IRQ_HP2R_DONE] = {
.reg_offset = 3, .mask = ARIZONA_HP2R_DONE_EINT1
},
[ARIZONA_IRQ_HP2L_DONE] = {
.reg_offset = 3, .mask = ARIZONA_HP2L_DONE_EINT1
},
[ARIZONA_IRQ_HP1R_DONE] = {
.reg_offset = 3, .mask = ARIZONA_HP1R_DONE_EINT1
},
[ARIZONA_IRQ_HP1L_DONE] = {
.reg_offset = 3, .mask = ARIZONA_HP1L_DONE_EINT1
},
[ARIZONA_IRQ_BOOT_DONE] = {
.reg_offset = 4, .mask = ARIZONA_BOOT_DONE_EINT1
},
[ARIZONA_IRQ_FLL2_CLOCK_OK] = {
.reg_offset = 4, .mask = ARIZONA_FLL2_CLOCK_OK_EINT1
},
[ARIZONA_IRQ_FLL1_CLOCK_OK] = {
.reg_offset = 4, .mask = ARIZONA_FLL1_CLOCK_OK_EINT1
},
};
const struct regmap_irq_chip wm5110_irq = {
.name = "wm5110 IRQ",
.status_base = ARIZONA_INTERRUPT_STATUS_1,
.mask_base = ARIZONA_INTERRUPT_STATUS_1_MASK,
.ack_base = ARIZONA_INTERRUPT_STATUS_1,
.num_regs = 5,
.irqs = wm5110_irqs,
.num_irqs = ARRAY_SIZE(wm5110_irqs),
};
EXPORT_SYMBOL_GPL(wm5110_irq);
static const struct regmap_irq wm5110_revd_irqs[ARIZONA_NUM_IRQ] = {
[ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 },
[ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 },
[ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 },
[ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 },
[ARIZONA_IRQ_DSP4_RAM_RDY] = {
.reg_offset = 1, .mask = ARIZONA_DSP4_RAM_RDY_EINT1
},
[ARIZONA_IRQ_DSP3_RAM_RDY] = {
.reg_offset = 1, .mask = ARIZONA_DSP3_RAM_RDY_EINT1
},
[ARIZONA_IRQ_DSP2_RAM_RDY] = {
.reg_offset = 1, .mask = ARIZONA_DSP2_RAM_RDY_EINT1
},
[ARIZONA_IRQ_DSP1_RAM_RDY] = {
.reg_offset = 1, .mask = ARIZONA_DSP1_RAM_RDY_EINT1
},
[ARIZONA_IRQ_DSP_IRQ8] = {
.reg_offset = 1, .mask = ARIZONA_DSP_IRQ8_EINT1
},
[ARIZONA_IRQ_DSP_IRQ7] = {
.reg_offset = 1, .mask = ARIZONA_DSP_IRQ7_EINT1
},
[ARIZONA_IRQ_DSP_IRQ6] = {
.reg_offset = 1, .mask = ARIZONA_DSP_IRQ6_EINT1
},
[ARIZONA_IRQ_DSP_IRQ5] = {
.reg_offset = 1, .mask = ARIZONA_DSP_IRQ5_EINT1
},
[ARIZONA_IRQ_DSP_IRQ4] = {
.reg_offset = 1, .mask = ARIZONA_DSP_IRQ4_EINT1
},
[ARIZONA_IRQ_DSP_IRQ3] = {
.reg_offset = 1, .mask = ARIZONA_DSP_IRQ3_EINT1
},
[ARIZONA_IRQ_DSP_IRQ2] = {
.reg_offset = 1, .mask = ARIZONA_DSP_IRQ2_EINT1
},
[ARIZONA_IRQ_DSP_IRQ1] = {
.reg_offset = 1, .mask = ARIZONA_DSP_IRQ1_EINT1
},
[ARIZONA_IRQ_SPK_OVERHEAT_WARN] = {
.reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_WARN_EINT1
},
[ARIZONA_IRQ_SPK_OVERHEAT] = {
.reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_EINT1
},
[ARIZONA_IRQ_HPDET] = {
.reg_offset = 2, .mask = ARIZONA_HPDET_EINT1
},
[ARIZONA_IRQ_MICDET] = {
.reg_offset = 2, .mask = ARIZONA_MICDET_EINT1
},
[ARIZONA_IRQ_WSEQ_DONE] = {
.reg_offset = 2, .mask = ARIZONA_WSEQ_DONE_EINT1
},
[ARIZONA_IRQ_DRC2_SIG_DET] = {
.reg_offset = 2, .mask = ARIZONA_DRC2_SIG_DET_EINT1
},
[ARIZONA_IRQ_DRC1_SIG_DET] = {
.reg_offset = 2, .mask = ARIZONA_DRC1_SIG_DET_EINT1
},
[ARIZONA_IRQ_ASRC2_LOCK] = {
.reg_offset = 2, .mask = ARIZONA_ASRC2_LOCK_EINT1
},
[ARIZONA_IRQ_ASRC1_LOCK] = {
.reg_offset = 2, .mask = ARIZONA_ASRC1_LOCK_EINT1
},
[ARIZONA_IRQ_UNDERCLOCKED] = {
.reg_offset = 2, .mask = ARIZONA_UNDERCLOCKED_EINT1
},
[ARIZONA_IRQ_OVERCLOCKED] = {
.reg_offset = 2, .mask = ARIZONA_OVERCLOCKED_EINT1
},
[ARIZONA_IRQ_FLL2_LOCK] = {
.reg_offset = 2, .mask = ARIZONA_FLL2_LOCK_EINT1
},
[ARIZONA_IRQ_FLL1_LOCK] = {
.reg_offset = 2, .mask = ARIZONA_FLL1_LOCK_EINT1
},
[ARIZONA_IRQ_CLKGEN_ERR] = {
.reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_EINT1
},
[ARIZONA_IRQ_CLKGEN_ERR_ASYNC] = {
.reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_ASYNC_EINT1
},
[ARIZONA_IRQ_CTRLIF_ERR] = {
.reg_offset = 3, .mask = ARIZONA_V2_CTRLIF_ERR_EINT1
},
[ARIZONA_IRQ_MIXER_DROPPED_SAMPLES] = {
.reg_offset = 3, .mask = ARIZONA_V2_MIXER_DROPPED_SAMPLE_EINT1
},
[ARIZONA_IRQ_ASYNC_CLK_ENA_LOW] = {
.reg_offset = 3, .mask = ARIZONA_V2_ASYNC_CLK_ENA_LOW_EINT1
},
[ARIZONA_IRQ_SYSCLK_ENA_LOW] = {
.reg_offset = 3, .mask = ARIZONA_V2_SYSCLK_ENA_LOW_EINT1
},
[ARIZONA_IRQ_ISRC1_CFG_ERR] = {
.reg_offset = 3, .mask = ARIZONA_V2_ISRC1_CFG_ERR_EINT1
},
[ARIZONA_IRQ_ISRC2_CFG_ERR] = {
.reg_offset = 3, .mask = ARIZONA_V2_ISRC2_CFG_ERR_EINT1
},
[ARIZONA_IRQ_ISRC3_CFG_ERR] = {
.reg_offset = 3, .mask = ARIZONA_V2_ISRC3_CFG_ERR_EINT1
},
[ARIZONA_IRQ_HP3R_DONE] = {
.reg_offset = 3, .mask = ARIZONA_HP3R_DONE_EINT1
},
[ARIZONA_IRQ_HP3L_DONE] = {
.reg_offset = 3, .mask = ARIZONA_HP3L_DONE_EINT1
},
[ARIZONA_IRQ_HP2R_DONE] = {
.reg_offset = 3, .mask = ARIZONA_HP2R_DONE_EINT1
},
[ARIZONA_IRQ_HP2L_DONE] = {
.reg_offset = 3, .mask = ARIZONA_HP2L_DONE_EINT1
},
[ARIZONA_IRQ_HP1R_DONE] = {
.reg_offset = 3, .mask = ARIZONA_HP1R_DONE_EINT1
},
[ARIZONA_IRQ_HP1L_DONE] = {
.reg_offset = 3, .mask = ARIZONA_HP1L_DONE_EINT1
},
[ARIZONA_IRQ_BOOT_DONE] = {
.reg_offset = 4, .mask = ARIZONA_BOOT_DONE_EINT1
},
[ARIZONA_IRQ_ASRC_CFG_ERR] = {
.reg_offset = 4, .mask = ARIZONA_V2_ASRC_CFG_ERR_EINT1
},
[ARIZONA_IRQ_FLL2_CLOCK_OK] = {
.reg_offset = 4, .mask = ARIZONA_FLL2_CLOCK_OK_EINT1
},
[ARIZONA_IRQ_FLL1_CLOCK_OK] = {
.reg_offset = 4, .mask = ARIZONA_FLL1_CLOCK_OK_EINT1
},
[ARIZONA_IRQ_DSP_SHARED_WR_COLL] = {
.reg_offset = 5, .mask = ARIZONA_DSP_SHARED_WR_COLL_EINT1
},
[ARIZONA_IRQ_SPK_SHUTDOWN] = {
.reg_offset = 5, .mask = ARIZONA_SPK_SHUTDOWN_EINT1
},
[ARIZONA_IRQ_SPK1R_SHORT] = {
.reg_offset = 5, .mask = ARIZONA_SPK1R_SHORT_EINT1
},
[ARIZONA_IRQ_SPK1L_SHORT] = {
.reg_offset = 5, .mask = ARIZONA_SPK1L_SHORT_EINT1
},
[ARIZONA_IRQ_HP3R_SC_NEG] = {
.reg_offset = 5, .mask = ARIZONA_HP3R_SC_NEG_EINT1
},
[ARIZONA_IRQ_HP3R_SC_POS] = {
.reg_offset = 5, .mask = ARIZONA_HP3R_SC_POS_EINT1
},
[ARIZONA_IRQ_HP3L_SC_NEG] = {
.reg_offset = 5, .mask = ARIZONA_HP3L_SC_NEG_EINT1
},
[ARIZONA_IRQ_HP3L_SC_POS] = {
.reg_offset = 5, .mask = ARIZONA_HP3L_SC_POS_EINT1
},
[ARIZONA_IRQ_HP2R_SC_NEG] = {
.reg_offset = 5, .mask = ARIZONA_HP2R_SC_NEG_EINT1
},
[ARIZONA_IRQ_HP2R_SC_POS] = {
.reg_offset = 5, .mask = ARIZONA_HP2R_SC_POS_EINT1
},
[ARIZONA_IRQ_HP2L_SC_NEG] = {
.reg_offset = 5, .mask = ARIZONA_HP2L_SC_NEG_EINT1
},
[ARIZONA_IRQ_HP2L_SC_POS] = {
.reg_offset = 5, .mask = ARIZONA_HP2L_SC_POS_EINT1
},
[ARIZONA_IRQ_HP1R_SC_NEG] = {
.reg_offset = 5, .mask = ARIZONA_HP1R_SC_NEG_EINT1
},
[ARIZONA_IRQ_HP1R_SC_POS] = {
.reg_offset = 5, .mask = ARIZONA_HP1R_SC_POS_EINT1
},
[ARIZONA_IRQ_HP1L_SC_NEG] = {
.reg_offset = 5, .mask = ARIZONA_HP1L_SC_NEG_EINT1
},
[ARIZONA_IRQ_HP1L_SC_POS] = {
.reg_offset = 5, .mask = ARIZONA_HP1L_SC_POS_EINT1
},
};
const struct regmap_irq_chip wm5110_revd_irq = {
.name = "wm5110 IRQ",
.status_base = ARIZONA_INTERRUPT_STATUS_1,
.mask_base = ARIZONA_INTERRUPT_STATUS_1_MASK,
.ack_base = ARIZONA_INTERRUPT_STATUS_1,
.num_regs = 6,
.irqs = wm5110_revd_irqs,
.num_irqs = ARRAY_SIZE(wm5110_revd_irqs),
};
EXPORT_SYMBOL_GPL(wm5110_revd_irq);
static const struct reg_default wm5110_reg_default[] = {
{ 0x00000008, 0x0019 }, /* R8 - Ctrl IF SPI CFG 1 */
{ 0x00000009, 0x0001 }, /* R9 - Ctrl IF I2C1 CFG 1 */
{ 0x0000000A, 0x0001 }, /* R10 - Ctrl IF I2C2 CFG 1 */
{ 0x0000000B, 0x001A }, /* R11 - Ctrl IF I2C1 CFG 2 */
{ 0x0000000C, 0x001A }, /* R12 - Ctrl IF I2C2 CFG 2 */
{ 0x00000020, 0x0000 }, /* R32 - Tone Generator 1 */
{ 0x00000021, 0x1000 }, /* R33 - Tone Generator 2 */
{ 0x00000022, 0x0000 }, /* R34 - Tone Generator 3 */
{ 0x00000023, 0x1000 }, /* R35 - Tone Generator 4 */
{ 0x00000024, 0x0000 }, /* R36 - Tone Generator 5 */
{ 0x00000030, 0x0000 }, /* R48 - PWM Drive 1 */
{ 0x00000031, 0x0100 }, /* R49 - PWM Drive 2 */
{ 0x00000032, 0x0100 }, /* R50 - PWM Drive 3 */
{ 0x00000040, 0x0000 }, /* R64 - Wake control */
{ 0x00000041, 0x0000 }, /* R65 - Sequence control */
{ 0x00000042, 0x0000 }, /* R66 - Spare Triggers */
{ 0x00000061, 0x01FF }, /* R97 - Sample Rate Sequence Select 1 */
{ 0x00000062, 0x01FF }, /* R98 - Sample Rate Sequence Select 2 */
{ 0x00000063, 0x01FF }, /* R99 - Sample Rate Sequence Select 3 */
{ 0x00000064, 0x01FF }, /* R100 - Sample Rate Sequence Select 4 */
{ 0x00000066, 0x01FF }, /* R102 - Always On Triggers Sequence Select 1 */
{ 0x00000067, 0x01FF }, /* R103 - Always On Triggers Sequence Select 2 */
{ 0x00000068, 0x01FF }, /* R104 - Always On Triggers Sequence Select 3 */
{ 0x00000069, 0x01FF }, /* R105 - Always On Triggers Sequence Select 4 */
{ 0x0000006A, 0x01FF }, /* R106 - Always On Triggers Sequence Select 5 */
{ 0x0000006B, 0x01FF }, /* R107 - Always On Triggers Sequence Select 6 */
{ 0x00000070, 0x0000 }, /* R112 - Comfort Noise Generator */
{ 0x00000090, 0x0000 }, /* R144 - Haptics Control 1 */
{ 0x00000091, 0x7FFF }, /* R145 - Haptics Control 2 */
{ 0x00000092, 0x0000 }, /* R146 - Haptics phase 1 intensity */
{ 0x00000093, 0x0000 }, /* R147 - Haptics phase 1 duration */
{ 0x00000094, 0x0000 }, /* R148 - Haptics phase 2 intensity */
{ 0x00000095, 0x0000 }, /* R149 - Haptics phase 2 duration */
{ 0x00000096, 0x0000 }, /* R150 - Haptics phase 3 intensity */
{ 0x00000097, 0x0000 }, /* R151 - Haptics phase 3 duration */
{ 0x00000100, 0x0001 }, /* R256 - Clock 32k 1 */
{ 0x00000101, 0x0504 }, /* R257 - System Clock 1 */
{ 0x00000102, 0x0011 }, /* R258 - Sample rate 1 */
{ 0x00000103, 0x0011 }, /* R259 - Sample rate 2 */
{ 0x00000104, 0x0011 }, /* R260 - Sample rate 3 */
{ 0x00000112, 0x0305 }, /* R274 - Async clock 1 */
{ 0x00000113, 0x0011 }, /* R275 - Async sample rate 1 */
{ 0x00000114, 0x0011 }, /* R276 - Async sample rate 2 */
{ 0x00000149, 0x0000 }, /* R329 - Output system clock */
{ 0x0000014A, 0x0000 }, /* R330 - Output async clock */
{ 0x00000152, 0x0000 }, /* R338 - Rate Estimator 1 */
{ 0x00000153, 0x0000 }, /* R339 - Rate Estimator 2 */
{ 0x00000154, 0x0000 }, /* R340 - Rate Estimator 3 */
{ 0x00000155, 0x0000 }, /* R341 - Rate Estimator 4 */
{ 0x00000156, 0x0000 }, /* R342 - Rate Estimator 5 */
{ 0x00000171, 0x0002 }, /* R369 - FLL1 Control 1 */
{ 0x00000172, 0x0008 }, /* R370 - FLL1 Control 2 */
{ 0x00000173, 0x0018 }, /* R371 - FLL1 Control 3 */
{ 0x00000174, 0x007D }, /* R372 - FLL1 Control 4 */
{ 0x00000175, 0x0006 }, /* R373 - FLL1 Control 5 */
{ 0x00000176, 0x0000 }, /* R374 - FLL1 Control 6 */
{ 0x00000179, 0x0000 }, /* R376 - FLL1 Control 7 */
{ 0x00000181, 0x0000 }, /* R385 - FLL1 Synchroniser 1 */
{ 0x00000182, 0x0000 }, /* R386 - FLL1 Synchroniser 2 */
{ 0x00000183, 0x0000 }, /* R387 - FLL1 Synchroniser 3 */
{ 0x00000184, 0x0000 }, /* R388 - FLL1 Synchroniser 4 */
{ 0x00000185, 0x0000 }, /* R389 - FLL1 Synchroniser 5 */
{ 0x00000186, 0x0000 }, /* R390 - FLL1 Synchroniser 6 */
{ 0x00000187, 0x0001 }, /* R390 - FLL1 Synchroniser 7 */
{ 0x00000189, 0x0000 }, /* R393 - FLL1 Spread Spectrum */
{ 0x0000018A, 0x000C }, /* R394 - FLL1 GPIO Clock */
{ 0x00000191, 0x0002 }, /* R401 - FLL2 Control 1 */
{ 0x00000192, 0x0008 }, /* R402 - FLL2 Control 2 */
{ 0x00000193, 0x0018 }, /* R403 - FLL2 Control 3 */
{ 0x00000194, 0x007D }, /* R404 - FLL2 Control 4 */
{ 0x00000195, 0x000C }, /* R405 - FLL2 Control 5 */
{ 0x00000196, 0x0000 }, /* R406 - FLL2 Control 6 */
{ 0x00000199, 0x0000 }, /* R408 - FLL2 Control 7 */
{ 0x000001A1, 0x0000 }, /* R417 - FLL2 Synchroniser 1 */
{ 0x000001A2, 0x0000 }, /* R418 - FLL2 Synchroniser 2 */
{ 0x000001A3, 0x0000 }, /* R419 - FLL2 Synchroniser 3 */
{ 0x000001A4, 0x0000 }, /* R420 - FLL2 Synchroniser 4 */
{ 0x000001A5, 0x0000 }, /* R421 - FLL2 Synchroniser 5 */
{ 0x000001A6, 0x0000 }, /* R422 - FLL2 Synchroniser 6 */
{ 0x000001A7, 0x0001 }, /* R422 - FLL2 Synchroniser 7 */
{ 0x000001A9, 0x0000 }, /* R425 - FLL2 Spread Spectrum */
{ 0x000001AA, 0x000C }, /* R426 - FLL2 GPIO Clock */
{ 0x00000200, 0x0006 }, /* R512 - Mic Charge Pump 1 */
{ 0x00000210, 0x0184 }, /* R528 - LDO1 Control 1 */
{ 0x00000213, 0x03E4 }, /* R531 - LDO2 Control 1 */
{ 0x00000218, 0x00E6 }, /* R536 - Mic Bias Ctrl 1 */
{ 0x00000219, 0x00E6 }, /* R537 - Mic Bias Ctrl 2 */
{ 0x0000021A, 0x00E6 }, /* R538 - Mic Bias Ctrl 3 */
{ 0x00000293, 0x0000 }, /* R659 - Accessory Detect Mode 1 */
{ 0x0000029B, 0x0028 }, /* R667 - Headphone Detect 1 */
{ 0x000002A2, 0x0000 }, /* R674 - Micd clamp control */
{ 0x000002A3, 0x1102 }, /* R675 - Mic Detect 1 */
{ 0x000002A4, 0x009F }, /* R676 - Mic Detect 2 */
{ 0x000002A6, 0x3737 }, /* R678 - Mic Detect Level 1 */
{ 0x000002A7, 0x2C37 }, /* R679 - Mic Detect Level 2 */
{ 0x000002A8, 0x1422 }, /* R680 - Mic Detect Level 3 */
{ 0x000002A9, 0x030A }, /* R681 - Mic Detect Level 4 */
{ 0x000002C3, 0x0000 }, /* R707 - Mic noise mix control 1 */
{ 0x000002CB, 0x0000 }, /* R715 - Isolation control */
{ 0x000002D3, 0x0000 }, /* R723 - Jack detect analogue */
{ 0x00000300, 0x0000 }, /* R768 - Input Enables */
{ 0x00000308, 0x0000 }, /* R776 - Input Rate */
{ 0x00000309, 0x0022 }, /* R777 - Input Volume Ramp */
{ 0x0000030C, 0x0002 }, /* R780 - HPF Control */
{ 0x00000310, 0x2080 }, /* R784 - IN1L Control */
{ 0x00000311, 0x0180 }, /* R785 - ADC Digital Volume 1L */
{ 0x00000312, 0x0000 }, /* R786 - DMIC1L Control */
{ 0x00000314, 0x0080 }, /* R788 - IN1R Control */
{ 0x00000315, 0x0180 }, /* R789 - ADC Digital Volume 1R */
{ 0x00000316, 0x0000 }, /* R790 - DMIC1R Control */
{ 0x00000318, 0x2080 }, /* R792 - IN2L Control */
{ 0x00000319, 0x0180 }, /* R793 - ADC Digital Volume 2L */
{ 0x0000031A, 0x0000 }, /* R794 - DMIC2L Control */
{ 0x0000031C, 0x0080 }, /* R796 - IN2R Control */
{ 0x0000031D, 0x0180 }, /* R797 - ADC Digital Volume 2R */
{ 0x0000031E, 0x0000 }, /* R798 - DMIC2R Control */
{ 0x00000320, 0x2080 }, /* R800 - IN3L Control */
{ 0x00000321, 0x0180 }, /* R801 - ADC Digital Volume 3L */
{ 0x00000322, 0x0000 }, /* R802 - DMIC3L Control */
{ 0x00000324, 0x0080 }, /* R804 - IN3R Control */
{ 0x00000325, 0x0180 }, /* R805 - ADC Digital Volume 3R */
{ 0x00000326, 0x0000 }, /* R806 - DMIC3R Control */
{ 0x00000328, 0x2000 }, /* R808 - IN4L Control */
{ 0x00000329, 0x0180 }, /* R809 - ADC Digital Volume 4L */
{ 0x0000032A, 0x0000 }, /* R810 - DMIC4L Control */
{ 0x0000032C, 0x0000 }, /* R812 - IN4R Control */
{ 0x0000032D, 0x0180 }, /* R813 - ADC Digital Volume 4R */
{ 0x0000032E, 0x0000 }, /* R814 - DMIC4R Control */
{ 0x00000400, 0x0000 }, /* R1024 - Output Enables 1 */
{ 0x00000408, 0x0000 }, /* R1032 - Output Rate 1 */
{ 0x00000409, 0x0022 }, /* R1033 - Output Volume Ramp */
{ 0x00000410, 0x0080 }, /* R1040 - Output Path Config 1L */
{ 0x00000411, 0x0180 }, /* R1041 - DAC Digital Volume 1L */
{ 0x00000412, 0x0081 }, /* R1042 - DAC Volume Limit 1L */
{ 0x00000413, 0x0001 }, /* R1043 - Noise Gate Select 1L */
{ 0x00000414, 0x0080 }, /* R1044 - Output Path Config 1R */
{ 0x00000415, 0x0180 }, /* R1045 - DAC Digital Volume 1R */
{ 0x00000416, 0x0081 }, /* R1046 - DAC Volume Limit 1R */
{ 0x00000417, 0x0002 }, /* R1047 - Noise Gate Select 1R */
{ 0x00000418, 0x0080 }, /* R1048 - Output Path Config 2L */
{ 0x00000419, 0x0180 }, /* R1049 - DAC Digital Volume 2L */
{ 0x0000041A, 0x0081 }, /* R1050 - DAC Volume Limit 2L */
{ 0x0000041B, 0x0004 }, /* R1051 - Noise Gate Select 2L */
{ 0x0000041C, 0x0080 }, /* R1052 - Output Path Config 2R */
{ 0x0000041D, 0x0180 }, /* R1053 - DAC Digital Volume 2R */
{ 0x0000041E, 0x0081 }, /* R1054 - DAC Volume Limit 2R */
{ 0x0000041F, 0x0008 }, /* R1055 - Noise Gate Select 2R */
{ 0x00000420, 0x0080 }, /* R1056 - Output Path Config 3L */
{ 0x00000421, 0x0180 }, /* R1057 - DAC Digital Volume 3L */
{ 0x00000422, 0x0081 }, /* R1058 - DAC Volume Limit 3L */
{ 0x00000423, 0x0010 }, /* R1059 - Noise Gate Select 3L */
{ 0x00000424, 0x0080 }, /* R1060 - Output Path Config 3R */
{ 0x00000425, 0x0180 }, /* R1061 - DAC Digital Volume 3R */
{ 0x00000426, 0x0081 }, /* R1062 - DAC Volume Limit 3R */
{ 0x00000427, 0x0020 }, /* R1063 - Noise Gate Select 3R */
{ 0x00000428, 0x0000 }, /* R1064 - Output Path Config 4L */
{ 0x00000429, 0x0180 }, /* R1065 - DAC Digital Volume 4L */
{ 0x0000042A, 0x0081 }, /* R1066 - Out Volume 4L */
{ 0x0000042B, 0x0040 }, /* R1067 - Noise Gate Select 4L */
{ 0x0000042C, 0x0000 }, /* R1068 - Output Path Config 4R */
{ 0x0000042D, 0x0180 }, /* R1069 - DAC Digital Volume 4R */
{ 0x0000042E, 0x0081 }, /* R1070 - Out Volume 4R */
{ 0x0000042F, 0x0080 }, /* R1071 - Noise Gate Select 4R */
{ 0x00000430, 0x0000 }, /* R1072 - Output Path Config 5L */
{ 0x00000431, 0x0180 }, /* R1073 - DAC Digital Volume 5L */
{ 0x00000432, 0x0081 }, /* R1074 - DAC Volume Limit 5L */
{ 0x00000433, 0x0100 }, /* R1075 - Noise Gate Select 5L */
{ 0x00000434, 0x0000 }, /* R1076 - Output Path Config 5R */
{ 0x00000435, 0x0180 }, /* R1077 - DAC Digital Volume 5R */
{ 0x00000436, 0x0081 }, /* R1078 - DAC Volume Limit 5R */
{ 0x00000437, 0x0200 }, /* R1079 - Noise Gate Select 5R */
{ 0x00000438, 0x0000 }, /* R1080 - Output Path Config 6L */
{ 0x00000439, 0x0180 }, /* R1081 - DAC Digital Volume 6L */
{ 0x0000043A, 0x0081 }, /* R1082 - DAC Volume Limit 6L */
{ 0x0000043B, 0x0400 }, /* R1083 - Noise Gate Select 6L */
{ 0x0000043C, 0x0000 }, /* R1084 - Output Path Config 6R */
{ 0x0000043D, 0x0180 }, /* R1085 - DAC Digital Volume 6R */
{ 0x0000043E, 0x0081 }, /* R1086 - DAC Volume Limit 6R */
{ 0x0000043F, 0x0800 }, /* R1087 - Noise Gate Select 6R */
{ 0x00000440, 0x003F }, /* R1088 - DRE Enable */
{ 0x00000450, 0x0000 }, /* R1104 - DAC AEC Control 1 */
{ 0x00000458, 0x0000 }, /* R1112 - Noise Gate Control */
{ 0x00000490, 0x0069 }, /* R1168 - PDM SPK1 CTRL 1 */
{ 0x00000491, 0x0000 }, /* R1169 - PDM SPK1 CTRL 2 */
{ 0x00000492, 0x0069 }, /* R1170 - PDM SPK2 CTRL 1 */
{ 0x00000493, 0x0000 }, /* R1171 - PDM SPK2 CTRL 2 */
{ 0x000004A0, 0x3480 }, /* R1184 - HP1 Short Circuit Ctrl */
{ 0x000004A1, 0x3400 }, /* R1185 - HP2 Short Circuit Ctrl */
{ 0x000004A2, 0x3400 }, /* R1186 - HP3 Short Circuit Ctrl */
{ 0x00000500, 0x000C }, /* R1280 - AIF1 BCLK Ctrl */
{ 0x00000501, 0x0008 }, /* R1281 - AIF1 Tx Pin Ctrl */
{ 0x00000502, 0x0000 }, /* R1282 - AIF1 Rx Pin Ctrl */
{ 0x00000503, 0x0000 }, /* R1283 - AIF1 Rate Ctrl */
{ 0x00000504, 0x0000 }, /* R1284 - AIF1 Format */
{ 0x00000505, 0x0040 }, /* R1285 - AIF1 Tx BCLK Rate */
{ 0x00000506, 0x0040 }, /* R1286 - AIF1 Rx BCLK Rate */
{ 0x00000507, 0x1818 }, /* R1287 - AIF1 Frame Ctrl 1 */
{ 0x00000508, 0x1818 }, /* R1288 - AIF1 Frame Ctrl 2 */
{ 0x00000509, 0x0000 }, /* R1289 - AIF1 Frame Ctrl 3 */
{ 0x0000050A, 0x0001 }, /* R1290 - AIF1 Frame Ctrl 4 */
{ 0x0000050B, 0x0002 }, /* R1291 - AIF1 Frame Ctrl 5 */
{ 0x0000050C, 0x0003 }, /* R1292 - AIF1 Frame Ctrl 6 */
{ 0x0000050D, 0x0004 }, /* R1293 - AIF1 Frame Ctrl 7 */
{ 0x0000050E, 0x0005 }, /* R1294 - AIF1 Frame Ctrl 8 */
{ 0x0000050F, 0x0006 }, /* R1295 - AIF1 Frame Ctrl 9 */
{ 0x00000510, 0x0007 }, /* R1296 - AIF1 Frame Ctrl 10 */
{ 0x00000511, 0x0000 }, /* R1297 - AIF1 Frame Ctrl 11 */
{ 0x00000512, 0x0001 }, /* R1298 - AIF1 Frame Ctrl 12 */
{ 0x00000513, 0x0002 }, /* R1299 - AIF1 Frame Ctrl 13 */
{ 0x00000514, 0x0003 }, /* R1300 - AIF1 Frame Ctrl 14 */
{ 0x00000515, 0x0004 }, /* R1301 - AIF1 Frame Ctrl 15 */
{ 0x00000516, 0x0005 }, /* R1302 - AIF1 Frame Ctrl 16 */
{ 0x00000517, 0x0006 }, /* R1303 - AIF1 Frame Ctrl 17 */
{ 0x00000518, 0x0007 }, /* R1304 - AIF1 Frame Ctrl 18 */
{ 0x00000519, 0x0000 }, /* R1305 - AIF1 Tx Enables */
{ 0x0000051A, 0x0000 }, /* R1306 - AIF1 Rx Enables */
{ 0x00000540, 0x000C }, /* R1344 - AIF2 BCLK Ctrl */
{ 0x00000541, 0x0008 }, /* R1345 - AIF2 Tx Pin Ctrl */
{ 0x00000542, 0x0000 }, /* R1346 - AIF2 Rx Pin Ctrl */
{ 0x00000543, 0x0000 }, /* R1347 - AIF2 Rate Ctrl */
{ 0x00000544, 0x0000 }, /* R1348 - AIF2 Format */
{ 0x00000545, 0x0040 }, /* R1349 - AIF2 Tx BCLK Rate */
{ 0x00000546, 0x0040 }, /* R1350 - AIF2 Rx BCLK Rate */
{ 0x00000547, 0x1818 }, /* R1351 - AIF2 Frame Ctrl 1 */
{ 0x00000548, 0x1818 }, /* R1352 - AIF2 Frame Ctrl 2 */
{ 0x00000549, 0x0000 }, /* R1353 - AIF2 Frame Ctrl 3 */
{ 0x0000054A, 0x0001 }, /* R1354 - AIF2 Frame Ctrl 4 */
{ 0x0000054B, 0x0002 }, /* R1355 - AIF2 Frame Ctrl 5 */
{ 0x0000054C, 0x0003 }, /* R1356 - AIF2 Frame Ctrl 6 */
{ 0x0000054D, 0x0004 }, /* R1357 - AIF2 Frame Ctrl 7 */
{ 0x0000054E, 0x0005 }, /* R1358 - AIF2 Frame Ctrl 8 */
{ 0x00000551, 0x0000 }, /* R1361 - AIF2 Frame Ctrl 11 */
{ 0x00000552, 0x0001 }, /* R1362 - AIF2 Frame Ctrl 12 */
{ 0x00000553, 0x0002 }, /* R1363 - AIF2 Frame Ctrl 13 */
{ 0x00000554, 0x0003 }, /* R1364 - AIF2 Frame Ctrl 14 */
{ 0x00000555, 0x0004 }, /* R1365 - AIF2 Frame Ctrl 15 */
{ 0x00000556, 0x0005 }, /* R1366 - AIF2 Frame Ctrl 16 */
{ 0x00000559, 0x0000 }, /* R1369 - AIF2 Tx Enables */
{ 0x0000055A, 0x0000 }, /* R1370 - AIF2 Rx Enables */
{ 0x00000580, 0x000C }, /* R1408 - AIF3 BCLK Ctrl */
{ 0x00000581, 0x0008 }, /* R1409 - AIF3 Tx Pin Ctrl */
{ 0x00000582, 0x0000 }, /* R1410 - AIF3 Rx Pin Ctrl */
{ 0x00000583, 0x0000 }, /* R1411 - AIF3 Rate Ctrl */
{ 0x00000584, 0x0000 }, /* R1412 - AIF3 Format */
{ 0x00000585, 0x0040 }, /* R1413 - AIF3 Tx BCLK Rate */
{ 0x00000586, 0x0040 }, /* R1414 - AIF3 Rx BCLK Rate */
{ 0x00000587, 0x1818 }, /* R1415 - AIF3 Frame Ctrl 1 */
{ 0x00000588, 0x1818 }, /* R1416 - AIF3 Frame Ctrl 2 */
{ 0x00000589, 0x0000 }, /* R1417 - AIF3 Frame Ctrl 3 */
{ 0x0000058A, 0x0001 }, /* R1418 - AIF3 Frame Ctrl 4 */
{ 0x00000591, 0x0000 }, /* R1425 - AIF3 Frame Ctrl 11 */
{ 0x00000592, 0x0001 }, /* R1426 - AIF3 Frame Ctrl 12 */
{ 0x00000599, 0x0000 }, /* R1433 - AIF3 Tx Enables */
{ 0x0000059A, 0x0000 }, /* R1434 - AIF3 Rx Enables */
{ 0x000005E3, 0x0004 }, /* R1507 - SLIMbus Framer Ref Gear */
{ 0x000005E5, 0x0000 }, /* R1509 - SLIMbus Rates 1 */
{ 0x000005E6, 0x0000 }, /* R1510 - SLIMbus Rates 2 */
{ 0x000005E7, 0x0000 }, /* R1511 - SLIMbus Rates 3 */
{ 0x000005E8, 0x0000 }, /* R1512 - SLIMbus Rates 4 */
{ 0x000005E9, 0x0000 }, /* R1513 - SLIMbus Rates 5 */
{ 0x000005EA, 0x0000 }, /* R1514 - SLIMbus Rates 6 */
{ 0x000005EB, 0x0000 }, /* R1515 - SLIMbus Rates 7 */
{ 0x000005EC, 0x0000 }, /* R1516 - SLIMbus Rates 8 */
{ 0x000005F5, 0x0000 }, /* R1525 - SLIMbus RX Channel Enable */
{ 0x000005F6, 0x0000 }, /* R1526 - SLIMbus TX Channel Enable */
{ 0x00000640, 0x0000 }, /* R1600 - PWM1MIX Input 1 Source */
{ 0x00000641, 0x0080 }, /* R1601 - PWM1MIX Input 1 Volume */
{ 0x00000642, 0x0000 }, /* R1602 - PWM1MIX Input 2 Source */
{ 0x00000643, 0x0080 }, /* R1603 - PWM1MIX Input 2 Volume */
{ 0x00000644, 0x0000 }, /* R1604 - PWM1MIX Input 3 Source */
{ 0x00000645, 0x0080 }, /* R1605 - PWM1MIX Input 3 Volume */
{ 0x00000646, 0x0000 }, /* R1606 - PWM1MIX Input 4 Source */
{ 0x00000647, 0x0080 }, /* R1607 - PWM1MIX Input 4 Volume */
{ 0x00000648, 0x0000 }, /* R1608 - PWM2MIX Input 1 Source */
{ 0x00000649, 0x0080 }, /* R1609 - PWM2MIX Input 1 Volume */
{ 0x0000064A, 0x0000 }, /* R1610 - PWM2MIX Input 2 Source */
{ 0x0000064B, 0x0080 }, /* R1611 - PWM2MIX Input 2 Volume */
{ 0x0000064C, 0x0000 }, /* R1612 - PWM2MIX Input 3 Source */
{ 0x0000064D, 0x0080 }, /* R1613 - PWM2MIX Input 3 Volume */
{ 0x0000064E, 0x0000 }, /* R1614 - PWM2MIX Input 4 Source */
{ 0x0000064F, 0x0080 }, /* R1615 - PWM2MIX Input 4 Volume */
{ 0x00000660, 0x0000 }, /* R1632 - MICMIX Input 1 Source */
{ 0x00000661, 0x0080 }, /* R1633 - MICMIX Input 1 Volume */
{ 0x00000662, 0x0000 }, /* R1634 - MICMIX Input 2 Source */
{ 0x00000663, 0x0080 }, /* R1635 - MICMIX Input 2 Volume */
{ 0x00000664, 0x0000 }, /* R1636 - MICMIX Input 3 Source */
{ 0x00000665, 0x0080 }, /* R1637 - MICMIX Input 3 Volume */
{ 0x00000666, 0x0000 }, /* R1638 - MICMIX Input 4 Source */
{ 0x00000667, 0x0080 }, /* R1639 - MICMIX Input 4 Volume */
{ 0x00000668, 0x0000 }, /* R1640 - NOISEMIX Input 1 Source */
{ 0x00000669, 0x0080 }, /* R1641 - NOISEMIX Input 1 Volume */
{ 0x0000066A, 0x0000 }, /* R1642 - NOISEMIX Input 2 Source */
{ 0x0000066B, 0x0080 }, /* R1643 - NOISEMIX Input 2 Volume */
{ 0x0000066C, 0x0000 }, /* R1644 - NOISEMIX Input 3 Source */
{ 0x0000066D, 0x0080 }, /* R1645 - NOISEMIX Input 3 Volume */
{ 0x0000066E, 0x0000 }, /* R1646 - NOISEMIX Input 4 Source */
{ 0x0000066F, 0x0080 }, /* R1647 - NOISEMIX Input 4 Volume */
{ 0x00000680, 0x0000 }, /* R1664 - OUT1LMIX Input 1 Source */
{ 0x00000681, 0x0080 }, /* R1665 - OUT1LMIX Input 1 Volume */
{ 0x00000682, 0x0000 }, /* R1666 - OUT1LMIX Input 2 Source */
{ 0x00000683, 0x0080 }, /* R1667 - OUT1LMIX Input 2 Volume */
{ 0x00000684, 0x0000 }, /* R1668 - OUT1LMIX Input 3 Source */
{ 0x00000685, 0x0080 }, /* R1669 - OUT1LMIX Input 3 Volume */
{ 0x00000686, 0x0000 }, /* R1670 - OUT1LMIX Input 4 Source */
{ 0x00000687, 0x0080 }, /* R1671 - OUT1LMIX Input 4 Volume */
{ 0x00000688, 0x0000 }, /* R1672 - OUT1RMIX Input 1 Source */
{ 0x00000689, 0x0080 }, /* R1673 - OUT1RMIX Input 1 Volume */
{ 0x0000068A, 0x0000 }, /* R1674 - OUT1RMIX Input 2 Source */
{ 0x0000068B, 0x0080 }, /* R1675 - OUT1RMIX Input 2 Volume */
{ 0x0000068C, 0x0000 }, /* R1676 - OUT1RMIX Input 3 Source */
{ 0x0000068D, 0x0080 }, /* R1677 - OUT1RMIX Input 3 Volume */
{ 0x0000068E, 0x0000 }, /* R1678 - OUT1RMIX Input 4 Source */
{ 0x0000068F, 0x0080 }, /* R1679 - OUT1RMIX Input 4 Volume */
{ 0x00000690, 0x0000 }, /* R1680 - OUT2LMIX Input 1 Source */
{ 0x00000691, 0x0080 }, /* R1681 - OUT2LMIX Input 1 Volume */
{ 0x00000692, 0x0000 }, /* R1682 - OUT2LMIX Input 2 Source */
{ 0x00000693, 0x0080 }, /* R1683 - OUT2LMIX Input 2 Volume */
{ 0x00000694, 0x0000 }, /* R1684 - OUT2LMIX Input 3 Source */
{ 0x00000695, 0x0080 }, /* R1685 - OUT2LMIX Input 3 Volume */
{ 0x00000696, 0x0000 }, /* R1686 - OUT2LMIX Input 4 Source */
{ 0x00000697, 0x0080 }, /* R1687 - OUT2LMIX Input 4 Volume */
{ 0x00000698, 0x0000 }, /* R1688 - OUT2RMIX Input 1 Source */
{ 0x00000699, 0x0080 }, /* R1689 - OUT2RMIX Input 1 Volume */
{ 0x0000069A, 0x0000 }, /* R1690 - OUT2RMIX Input 2 Source */
{ 0x0000069B, 0x0080 }, /* R1691 - OUT2RMIX Input 2 Volume */