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lba_pci.c
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lba_pci.c
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/*
**
** PCI Lower Bus Adapter (LBA) manager
**
** (c) Copyright 1999,2000 Grant Grundler
** (c) Copyright 1999,2000 Hewlett-Packard Company
**
** This program is free software; you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation; either version 2 of the License, or
** (at your option) any later version.
**
**
** This module primarily provides access to PCI bus (config/IOport
** spaces) on platforms with an SBA/LBA chipset. A/B/C/J/L/N-class
** with 4 digit model numbers - eg C3000 (and A400...sigh).
**
** LBA driver isn't as simple as the Dino driver because:
** (a) this chip has substantial bug fixes between revisions
** (Only one Dino bug has a software workaround :^( )
** (b) has more options which we don't (yet) support (DMA hints, OLARD)
** (c) IRQ support lives in the I/O SAPIC driver (not with PCI driver)
** (d) play nicely with both PAT and "Legacy" PA-RISC firmware (PDC).
** (dino only deals with "Legacy" PDC)
**
** LBA driver passes the I/O SAPIC HPA to the I/O SAPIC driver.
** (I/O SAPIC is integratd in the LBA chip).
**
** FIXME: Add support to SBA and LBA drivers for DMA hint sets
** FIXME: Add support for PCI card hot-plug (OLARD).
*/
#include <linux/delay.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <linux/init.h> /* for __init */
#include <linux/pci.h>
#include <linux/ioport.h>
#include <linux/slab.h>
#include <asm/byteorder.h>
#include <asm/pdc.h>
#include <asm/pdcpat.h>
#include <asm/page.h>
#include <asm/ropes.h>
#include <asm/hardware.h> /* for register_parisc_driver() stuff */
#include <asm/parisc-device.h>
#include <asm/io.h> /* read/write stuff */
#undef DEBUG_LBA /* general stuff */
#undef DEBUG_LBA_PORT /* debug I/O Port access */
#undef DEBUG_LBA_CFG /* debug Config Space Access (ie PCI Bus walk) */
#undef DEBUG_LBA_PAT /* debug PCI Resource Mgt code - PDC PAT only */
#undef FBB_SUPPORT /* Fast Back-Back xfers - NOT READY YET */
#ifdef DEBUG_LBA
#define DBG(x...) printk(x)
#else
#define DBG(x...)
#endif
#ifdef DEBUG_LBA_PORT
#define DBG_PORT(x...) printk(x)
#else
#define DBG_PORT(x...)
#endif
#ifdef DEBUG_LBA_CFG
#define DBG_CFG(x...) printk(x)
#else
#define DBG_CFG(x...)
#endif
#ifdef DEBUG_LBA_PAT
#define DBG_PAT(x...) printk(x)
#else
#define DBG_PAT(x...)
#endif
/*
** Config accessor functions only pass in the 8-bit bus number and not
** the 8-bit "PCI Segment" number. Each LBA will be assigned a PCI bus
** number based on what firmware wrote into the scratch register.
**
** The "secondary" bus number is set to this before calling
** pci_register_ops(). If any PPB's are present, the scan will
** discover them and update the "secondary" and "subordinate"
** fields in the pci_bus structure.
**
** Changes in the configuration *may* result in a different
** bus number for each LBA depending on what firmware does.
*/
#define MODULE_NAME "LBA"
/* non-postable I/O port space, densely packed */
#define LBA_PORT_BASE (PCI_F_EXTEND | 0xfee00000UL)
static void __iomem *astro_iop_base __read_mostly;
static u32 lba_t32;
/* lba flags */
#define LBA_FLAG_SKIP_PROBE 0x10
#define LBA_SKIP_PROBE(d) ((d)->flags & LBA_FLAG_SKIP_PROBE)
/* Looks nice and keeps the compiler happy */
#define LBA_DEV(d) ((struct lba_device *) (d))
/*
** Only allow 8 subsidiary busses per LBA
** Problem is the PCI bus numbering is globally shared.
*/
#define LBA_MAX_NUM_BUSES 8
/************************************
* LBA register read and write support
*
* BE WARNED: register writes are posted.
* (ie follow writes which must reach HW with a read)
*/
#define READ_U8(addr) __raw_readb(addr)
#define READ_U16(addr) __raw_readw(addr)
#define READ_U32(addr) __raw_readl(addr)
#define WRITE_U8(value, addr) __raw_writeb(value, addr)
#define WRITE_U16(value, addr) __raw_writew(value, addr)
#define WRITE_U32(value, addr) __raw_writel(value, addr)
#define READ_REG8(addr) readb(addr)
#define READ_REG16(addr) readw(addr)
#define READ_REG32(addr) readl(addr)
#define READ_REG64(addr) readq(addr)
#define WRITE_REG8(value, addr) writeb(value, addr)
#define WRITE_REG16(value, addr) writew(value, addr)
#define WRITE_REG32(value, addr) writel(value, addr)
#define LBA_CFG_TOK(bus,dfn) ((u32) ((bus)<<16 | (dfn)<<8))
#define LBA_CFG_BUS(tok) ((u8) ((tok)>>16))
#define LBA_CFG_DEV(tok) ((u8) ((tok)>>11) & 0x1f)
#define LBA_CFG_FUNC(tok) ((u8) ((tok)>>8 ) & 0x7)
/*
** Extract LBA (Rope) number from HPA
** REVISIT: 16 ropes for Stretch/Ike?
*/
#define ROPES_PER_IOC 8
#define LBA_NUM(x) ((((unsigned long) x) >> 13) & (ROPES_PER_IOC-1))
static void
lba_dump_res(struct resource *r, int d)
{
int i;
if (NULL == r)
return;
printk(KERN_DEBUG "(%p)", r->parent);
for (i = d; i ; --i) printk(" ");
printk(KERN_DEBUG "%p [%lx,%lx]/%lx\n", r,
(long)r->start, (long)r->end, r->flags);
lba_dump_res(r->child, d+2);
lba_dump_res(r->sibling, d);
}
/*
** LBA rev 2.0, 2.1, 2.2, and 3.0 bus walks require a complex
** workaround for cfg cycles:
** -- preserve LBA state
** -- prevent any DMA from occurring
** -- turn on smart mode
** -- probe with config writes before doing config reads
** -- check ERROR_STATUS
** -- clear ERROR_STATUS
** -- restore LBA state
**
** The workaround is only used for device discovery.
*/
static int lba_device_present(u8 bus, u8 dfn, struct lba_device *d)
{
u8 first_bus = d->hba.hba_bus->busn_res.start;
u8 last_sub_bus = d->hba.hba_bus->busn_res.end;
if ((bus < first_bus) ||
(bus > last_sub_bus) ||
((bus - first_bus) >= LBA_MAX_NUM_BUSES)) {
return 0;
}
return 1;
}
#define LBA_CFG_SETUP(d, tok) { \
/* Save contents of error config register. */ \
error_config = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG); \
\
/* Save contents of status control register. */ \
status_control = READ_REG32(d->hba.base_addr + LBA_STAT_CTL); \
\
/* For LBA rev 2.0, 2.1, 2.2, and 3.0, we must disable DMA \
** arbitration for full bus walks. \
*/ \
/* Save contents of arb mask register. */ \
arb_mask = READ_REG32(d->hba.base_addr + LBA_ARB_MASK); \
\
/* \
* Turn off all device arbitration bits (i.e. everything \
* except arbitration enable bit). \
*/ \
WRITE_REG32(0x1, d->hba.base_addr + LBA_ARB_MASK); \
\
/* \
* Set the smart mode bit so that master aborts don't cause \
* LBA to go into PCI fatal mode (required). \
*/ \
WRITE_REG32(error_config | LBA_SMART_MODE, d->hba.base_addr + LBA_ERROR_CONFIG); \
}
#define LBA_CFG_PROBE(d, tok) { \
/* \
* Setup Vendor ID write and read back the address register \
* to make sure that LBA is the bus master. \
*/ \
WRITE_REG32(tok | PCI_VENDOR_ID, (d)->hba.base_addr + LBA_PCI_CFG_ADDR);\
/* \
* Read address register to ensure that LBA is the bus master, \
* which implies that DMA traffic has stopped when DMA arb is off. \
*/ \
lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
/* \
* Generate a cfg write cycle (will have no affect on \
* Vendor ID register since read-only). \
*/ \
WRITE_REG32(~0, (d)->hba.base_addr + LBA_PCI_CFG_DATA); \
/* \
* Make sure write has completed before proceeding further, \
* i.e. before setting clear enable. \
*/ \
lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
}
/*
* HPREVISIT:
* -- Can't tell if config cycle got the error.
*
* OV bit is broken until rev 4.0, so can't use OV bit and
* LBA_ERROR_LOG_ADDR to tell if error belongs to config cycle.
*
* As of rev 4.0, no longer need the error check.
*
* -- Even if we could tell, we still want to return -1
* for **ANY** error (not just master abort).
*
* -- Only clear non-fatal errors (we don't want to bring
* LBA out of pci-fatal mode).
*
* Actually, there is still a race in which
* we could be clearing a fatal error. We will
* live with this during our initial bus walk
* until rev 4.0 (no driver activity during
* initial bus walk). The initial bus walk
* has race conditions concerning the use of
* smart mode as well.
*/
#define LBA_MASTER_ABORT_ERROR 0xc
#define LBA_FATAL_ERROR 0x10
#define LBA_CFG_MASTER_ABORT_CHECK(d, base, tok, error) { \
u32 error_status = 0; \
/* \
* Set clear enable (CE) bit. Unset by HW when new \
* errors are logged -- LBA HW ERS section 14.3.3). \
*/ \
WRITE_REG32(status_control | CLEAR_ERRLOG_ENABLE, base + LBA_STAT_CTL); \
error_status = READ_REG32(base + LBA_ERROR_STATUS); \
if ((error_status & 0x1f) != 0) { \
/* \
* Fail the config read request. \
*/ \
error = 1; \
if ((error_status & LBA_FATAL_ERROR) == 0) { \
/* \
* Clear error status (if fatal bit not set) by setting \
* clear error log bit (CL). \
*/ \
WRITE_REG32(status_control | CLEAR_ERRLOG, base + LBA_STAT_CTL); \
} \
} \
}
#define LBA_CFG_TR4_ADDR_SETUP(d, addr) \
WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR);
#define LBA_CFG_ADDR_SETUP(d, addr) { \
WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
/* \
* Read address register to ensure that LBA is the bus master, \
* which implies that DMA traffic has stopped when DMA arb is off. \
*/ \
lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
}
#define LBA_CFG_RESTORE(d, base) { \
/* \
* Restore status control register (turn off clear enable). \
*/ \
WRITE_REG32(status_control, base + LBA_STAT_CTL); \
/* \
* Restore error config register (turn off smart mode). \
*/ \
WRITE_REG32(error_config, base + LBA_ERROR_CONFIG); \
/* \
* Restore arb mask register (reenables DMA arbitration). \
*/ \
WRITE_REG32(arb_mask, base + LBA_ARB_MASK); \
}
static unsigned int
lba_rd_cfg(struct lba_device *d, u32 tok, u8 reg, u32 size)
{
u32 data = ~0U;
int error = 0;
u32 arb_mask = 0; /* used by LBA_CFG_SETUP/RESTORE */
u32 error_config = 0; /* used by LBA_CFG_SETUP/RESTORE */
u32 status_control = 0; /* used by LBA_CFG_SETUP/RESTORE */
LBA_CFG_SETUP(d, tok);
LBA_CFG_PROBE(d, tok);
LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error);
if (!error) {
void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
LBA_CFG_ADDR_SETUP(d, tok | reg);
switch (size) {
case 1: data = (u32) READ_REG8(data_reg + (reg & 3)); break;
case 2: data = (u32) READ_REG16(data_reg+ (reg & 2)); break;
case 4: data = READ_REG32(data_reg); break;
}
}
LBA_CFG_RESTORE(d, d->hba.base_addr);
return(data);
}
static int elroy_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 *data)
{
struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
u32 tok = LBA_CFG_TOK(local_bus, devfn);
void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
if ((pos > 255) || (devfn > 255))
return -EINVAL;
/* FIXME: B2K/C3600 workaround is always use old method... */
/* if (!LBA_SKIP_PROBE(d)) */ {
/* original - Generate config cycle on broken elroy
with risk we will miss PCI bus errors. */
*data = lba_rd_cfg(d, tok, pos, size);
DBG_CFG("%s(%x+%2x) -> 0x%x (a)\n", __func__, tok, pos, *data);
return 0;
}
if (LBA_SKIP_PROBE(d) && !lba_device_present(bus->busn_res.start, devfn, d)) {
DBG_CFG("%s(%x+%2x) -> -1 (b)\n", __func__, tok, pos);
/* either don't want to look or know device isn't present. */
*data = ~0U;
return(0);
}
/* Basic Algorithm
** Should only get here on fully working LBA rev.
** This is how simple the code should have been.
*/
LBA_CFG_ADDR_SETUP(d, tok | pos);
switch(size) {
case 1: *data = READ_REG8 (data_reg + (pos & 3)); break;
case 2: *data = READ_REG16(data_reg + (pos & 2)); break;
case 4: *data = READ_REG32(data_reg); break;
}
DBG_CFG("%s(%x+%2x) -> 0x%x (c)\n", __func__, tok, pos, *data);
return 0;
}
static void
lba_wr_cfg(struct lba_device *d, u32 tok, u8 reg, u32 data, u32 size)
{
int error = 0;
u32 arb_mask = 0;
u32 error_config = 0;
u32 status_control = 0;
void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
LBA_CFG_SETUP(d, tok);
LBA_CFG_ADDR_SETUP(d, tok | reg);
switch (size) {
case 1: WRITE_REG8 (data, data_reg + (reg & 3)); break;
case 2: WRITE_REG16(data, data_reg + (reg & 2)); break;
case 4: WRITE_REG32(data, data_reg); break;
}
LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error);
LBA_CFG_RESTORE(d, d->hba.base_addr);
}
/*
* LBA 4.0 config write code implements non-postable semantics
* by doing a read of CONFIG ADDR after the write.
*/
static int elroy_cfg_write(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 data)
{
struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
u32 tok = LBA_CFG_TOK(local_bus,devfn);
if ((pos > 255) || (devfn > 255))
return -EINVAL;
if (!LBA_SKIP_PROBE(d)) {
/* Original Workaround */
lba_wr_cfg(d, tok, pos, (u32) data, size);
DBG_CFG("%s(%x+%2x) = 0x%x (a)\n", __func__, tok, pos,data);
return 0;
}
if (LBA_SKIP_PROBE(d) && (!lba_device_present(bus->busn_res.start, devfn, d))) {
DBG_CFG("%s(%x+%2x) = 0x%x (b)\n", __func__, tok, pos,data);
return 1; /* New Workaround */
}
DBG_CFG("%s(%x+%2x) = 0x%x (c)\n", __func__, tok, pos, data);
/* Basic Algorithm */
LBA_CFG_ADDR_SETUP(d, tok | pos);
switch(size) {
case 1: WRITE_REG8 (data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 3));
break;
case 2: WRITE_REG16(data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 2));
break;
case 4: WRITE_REG32(data, d->hba.base_addr + LBA_PCI_CFG_DATA);
break;
}
/* flush posted write */
lba_t32 = READ_REG32(d->hba.base_addr + LBA_PCI_CFG_ADDR);
return 0;
}
static struct pci_ops elroy_cfg_ops = {
.read = elroy_cfg_read,
.write = elroy_cfg_write,
};
/*
* The mercury_cfg_ops are slightly misnamed; they're also used for Elroy
* TR4.0 as no additional bugs were found in this areea between Elroy and
* Mercury
*/
static int mercury_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 *data)
{
struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
u32 tok = LBA_CFG_TOK(local_bus, devfn);
void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
if ((pos > 255) || (devfn > 255))
return -EINVAL;
LBA_CFG_TR4_ADDR_SETUP(d, tok | pos);
switch(size) {
case 1:
*data = READ_REG8(data_reg + (pos & 3));
break;
case 2:
*data = READ_REG16(data_reg + (pos & 2));
break;
case 4:
*data = READ_REG32(data_reg); break;
break;
}
DBG_CFG("mercury_cfg_read(%x+%2x) -> 0x%x\n", tok, pos, *data);
return 0;
}
/*
* LBA 4.0 config write code implements non-postable semantics
* by doing a read of CONFIG ADDR after the write.
*/
static int mercury_cfg_write(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 data)
{
struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
u32 tok = LBA_CFG_TOK(local_bus,devfn);
if ((pos > 255) || (devfn > 255))
return -EINVAL;
DBG_CFG("%s(%x+%2x) <- 0x%x (c)\n", __func__, tok, pos, data);
LBA_CFG_TR4_ADDR_SETUP(d, tok | pos);
switch(size) {
case 1:
WRITE_REG8 (data, data_reg + (pos & 3));
break;
case 2:
WRITE_REG16(data, data_reg + (pos & 2));
break;
case 4:
WRITE_REG32(data, data_reg);
break;
}
/* flush posted write */
lba_t32 = READ_U32(d->hba.base_addr + LBA_PCI_CFG_ADDR);
return 0;
}
static struct pci_ops mercury_cfg_ops = {
.read = mercury_cfg_read,
.write = mercury_cfg_write,
};
static void
lba_bios_init(void)
{
DBG(MODULE_NAME ": lba_bios_init\n");
}
#ifdef CONFIG_64BIT
/*
* truncate_pat_collision: Deal with overlaps or outright collisions
* between PAT PDC reported ranges.
*
* Broken PA8800 firmware will report lmmio range that
* overlaps with CPU HPA. Just truncate the lmmio range.
*
* BEWARE: conflicts with this lmmio range may be an
* elmmio range which is pointing down another rope.
*
* FIXME: only deals with one collision per range...theoretically we
* could have several. Supporting more than one collision will get messy.
*/
static unsigned long
truncate_pat_collision(struct resource *root, struct resource *new)
{
unsigned long start = new->start;
unsigned long end = new->end;
struct resource *tmp = root->child;
if (end <= start || start < root->start || !tmp)
return 0;
/* find first overlap */
while (tmp && tmp->end < start)
tmp = tmp->sibling;
/* no entries overlap */
if (!tmp) return 0;
/* found one that starts behind the new one
** Don't need to do anything.
*/
if (tmp->start >= end) return 0;
if (tmp->start <= start) {
/* "front" of new one overlaps */
new->start = tmp->end + 1;
if (tmp->end >= end) {
/* AACCKK! totally overlaps! drop this range. */
return 1;
}
}
if (tmp->end < end ) {
/* "end" of new one overlaps */
new->end = tmp->start - 1;
}
printk(KERN_WARNING "LBA: Truncating lmmio_space [%lx/%lx] "
"to [%lx,%lx]\n",
start, end,
(long)new->start, (long)new->end );
return 0; /* truncation successful */
}
/*
* extend_lmmio_len: extend lmmio range to maximum length
*
* This is needed at least on C8000 systems to get the ATI FireGL card
* working. On other systems we will currently not extend the lmmio space.
*/
static unsigned long
extend_lmmio_len(unsigned long start, unsigned long end, unsigned long lba_len)
{
struct resource *tmp;
pr_debug("LMMIO mismatch: PAT length = 0x%lx, MASK register = 0x%lx\n",
end - start, lba_len);
lba_len = min(lba_len+1, 256UL*1024*1024); /* limit to 256 MB */
pr_debug("LBA: lmmio_space [0x%lx-0x%lx] - original\n", start, end);
if (boot_cpu_data.cpu_type < mako) {
pr_info("LBA: Not a C8000 system - not extending LMMIO range.\n");
return end;
}
end += lba_len;
if (end < start) /* fix overflow */
end = -1ULL;
pr_debug("LBA: lmmio_space [0x%lx-0x%lx] - current\n", start, end);
/* first overlap */
for (tmp = iomem_resource.child; tmp; tmp = tmp->sibling) {
pr_debug("LBA: testing %pR\n", tmp);
if (tmp->start == start)
continue; /* ignore ourself */
if (tmp->end < start)
continue;
if (tmp->start > end)
continue;
if (end >= tmp->start)
end = tmp->start - 1;
}
pr_info("LBA: lmmio_space [0x%lx-0x%lx] - new\n", start, end);
/* return new end */
return end;
}
#else
#define truncate_pat_collision(r,n) (0)
#endif
/*
** The algorithm is generic code.
** But it needs to access local data structures to get the IRQ base.
** Could make this a "pci_fixup_irq(bus, region)" but not sure
** it's worth it.
**
** Called by do_pci_scan_bus() immediately after each PCI bus is walked.
** Resources aren't allocated until recursive buswalk below HBA is completed.
*/
static void
lba_fixup_bus(struct pci_bus *bus)
{
struct pci_dev *dev;
#ifdef FBB_SUPPORT
u16 status;
#endif
struct lba_device *ldev = LBA_DEV(parisc_walk_tree(bus->bridge));
DBG("lba_fixup_bus(0x%p) bus %d platform_data 0x%p\n",
bus, (int)bus->busn_res.start, bus->bridge->platform_data);
/*
** Properly Setup MMIO resources for this bus.
** pci_alloc_primary_bus() mangles this.
*/
if (bus->parent) {
int i;
/* PCI-PCI Bridge */
pci_read_bridge_bases(bus);
for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
pci_claim_resource(bus->self, i);
}
} else {
/* Host-PCI Bridge */
int err;
DBG("lba_fixup_bus() %s [%lx/%lx]/%lx\n",
ldev->hba.io_space.name,
ldev->hba.io_space.start, ldev->hba.io_space.end,
ldev->hba.io_space.flags);
DBG("lba_fixup_bus() %s [%lx/%lx]/%lx\n",
ldev->hba.lmmio_space.name,
ldev->hba.lmmio_space.start, ldev->hba.lmmio_space.end,
ldev->hba.lmmio_space.flags);
err = request_resource(&ioport_resource, &(ldev->hba.io_space));
if (err < 0) {
lba_dump_res(&ioport_resource, 2);
BUG();
}
if (ldev->hba.elmmio_space.flags) {
err = request_resource(&iomem_resource,
&(ldev->hba.elmmio_space));
if (err < 0) {
printk("FAILED: lba_fixup_bus() request for "
"elmmio_space [%lx/%lx]\n",
(long)ldev->hba.elmmio_space.start,
(long)ldev->hba.elmmio_space.end);
/* lba_dump_res(&iomem_resource, 2); */
/* BUG(); */
}
}
if (ldev->hba.lmmio_space.flags) {
err = request_resource(&iomem_resource, &(ldev->hba.lmmio_space));
if (err < 0) {
printk(KERN_ERR "FAILED: lba_fixup_bus() request for "
"lmmio_space [%lx/%lx]\n",
(long)ldev->hba.lmmio_space.start,
(long)ldev->hba.lmmio_space.end);
}
}
#ifdef CONFIG_64BIT
/* GMMIO is distributed range. Every LBA/Rope gets part it. */
if (ldev->hba.gmmio_space.flags) {
err = request_resource(&iomem_resource, &(ldev->hba.gmmio_space));
if (err < 0) {
printk("FAILED: lba_fixup_bus() request for "
"gmmio_space [%lx/%lx]\n",
(long)ldev->hba.gmmio_space.start,
(long)ldev->hba.gmmio_space.end);
lba_dump_res(&iomem_resource, 2);
BUG();
}
}
#endif
}
list_for_each_entry(dev, &bus->devices, bus_list) {
int i;
DBG("lba_fixup_bus() %s\n", pci_name(dev));
/* Virtualize Device/Bridge Resources. */
for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
struct resource *res = &dev->resource[i];
/* If resource not allocated - skip it */
if (!res->start)
continue;
/*
** FIXME: this will result in whinging for devices
** that share expansion ROMs (think quad tulip), but
** isn't harmful.
*/
pci_claim_resource(dev, i);
}
#ifdef FBB_SUPPORT
/*
** If one device does not support FBB transfers,
** No one on the bus can be allowed to use them.
*/
(void) pci_read_config_word(dev, PCI_STATUS, &status);
bus->bridge_ctl &= ~(status & PCI_STATUS_FAST_BACK);
#endif
/*
** P2PB's have no IRQs. ignore them.
*/
if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
continue;
/* Adjust INTERRUPT_LINE for this dev */
iosapic_fixup_irq(ldev->iosapic_obj, dev);
}
#ifdef FBB_SUPPORT
/* FIXME/REVISIT - finish figuring out to set FBB on both
** pci_setup_bridge() clobbers PCI_BRIDGE_CONTROL.
** Can't fixup here anyway....garr...
*/
if (fbb_enable) {
if (bus->parent) {
u8 control;
/* enable on PPB */
(void) pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &control);
(void) pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, control | PCI_STATUS_FAST_BACK);
} else {
/* enable on LBA */
}
fbb_enable = PCI_COMMAND_FAST_BACK;
}
/* Lastly enable FBB/PERR/SERR on all devices too */
list_for_each_entry(dev, &bus->devices, bus_list) {
(void) pci_read_config_word(dev, PCI_COMMAND, &status);
status |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR | fbb_enable;
(void) pci_write_config_word(dev, PCI_COMMAND, status);
}
#endif
}
static struct pci_bios_ops lba_bios_ops = {
.init = lba_bios_init,
.fixup_bus = lba_fixup_bus,
};
/*******************************************************
**
** LBA Sprockets "I/O Port" Space Accessor Functions
**
** This set of accessor functions is intended for use with
** "legacy firmware" (ie Sprockets on Allegro/Forte boxes).
**
** Many PCI devices don't require use of I/O port space (eg Tulip,
** NCR720) since they export the same registers to both MMIO and
** I/O port space. In general I/O port space is slower than
** MMIO since drivers are designed so PIO writes can be posted.
**
********************************************************/
#define LBA_PORT_IN(size, mask) \
static u##size lba_astro_in##size (struct pci_hba_data *d, u16 addr) \
{ \
u##size t; \
t = READ_REG##size(astro_iop_base + addr); \
DBG_PORT(" 0x%x\n", t); \
return (t); \
}
LBA_PORT_IN( 8, 3)
LBA_PORT_IN(16, 2)
LBA_PORT_IN(32, 0)
/*
** BUG X4107: Ordering broken - DMA RD return can bypass PIO WR
**
** Fixed in Elroy 2.2. The READ_U32(..., LBA_FUNC_ID) below is
** guarantee non-postable completion semantics - not avoid X4107.
** The READ_U32 only guarantees the write data gets to elroy but
** out to the PCI bus. We can't read stuff from I/O port space
** since we don't know what has side-effects. Attempting to read
** from configuration space would be suicidal given the number of
** bugs in that elroy functionality.
**
** Description:
** DMA read results can improperly pass PIO writes (X4107). The
** result of this bug is that if a processor modifies a location in
** memory after having issued PIO writes, the PIO writes are not
** guaranteed to be completed before a PCI device is allowed to see
** the modified data in a DMA read.
**
** Note that IKE bug X3719 in TR1 IKEs will result in the same
** symptom.
**
** Workaround:
** The workaround for this bug is to always follow a PIO write with
** a PIO read to the same bus before starting DMA on that PCI bus.
**
*/
#define LBA_PORT_OUT(size, mask) \
static void lba_astro_out##size (struct pci_hba_data *d, u16 addr, u##size val) \
{ \
DBG_PORT("%s(0x%p, 0x%x, 0x%x)\n", __func__, d, addr, val); \
WRITE_REG##size(val, astro_iop_base + addr); \
if (LBA_DEV(d)->hw_rev < 3) \
lba_t32 = READ_U32(d->base_addr + LBA_FUNC_ID); \
}
LBA_PORT_OUT( 8, 3)
LBA_PORT_OUT(16, 2)
LBA_PORT_OUT(32, 0)
static struct pci_port_ops lba_astro_port_ops = {
.inb = lba_astro_in8,
.inw = lba_astro_in16,
.inl = lba_astro_in32,
.outb = lba_astro_out8,
.outw = lba_astro_out16,
.outl = lba_astro_out32
};
#ifdef CONFIG_64BIT
#define PIOP_TO_GMMIO(lba, addr) \
((lba)->iop_base + (((addr)&0xFFFC)<<10) + ((addr)&3))
/*******************************************************
**
** LBA PAT "I/O Port" Space Accessor Functions
**
** This set of accessor functions is intended for use with
** "PAT PDC" firmware (ie Prelude/Rhapsody/Piranha boxes).
**
** This uses the PIOP space located in the first 64MB of GMMIO.
** Each rope gets a full 64*KB* (ie 4 bytes per page) this way.
** bits 1:0 stay the same. bits 15:2 become 25:12.
** Then add the base and we can generate an I/O Port cycle.
********************************************************/
#undef LBA_PORT_IN
#define LBA_PORT_IN(size, mask) \
static u##size lba_pat_in##size (struct pci_hba_data *l, u16 addr) \
{ \
u##size t; \
DBG_PORT("%s(0x%p, 0x%x) ->", __func__, l, addr); \
t = READ_REG##size(PIOP_TO_GMMIO(LBA_DEV(l), addr)); \
DBG_PORT(" 0x%x\n", t); \
return (t); \
}
LBA_PORT_IN( 8, 3)
LBA_PORT_IN(16, 2)
LBA_PORT_IN(32, 0)
#undef LBA_PORT_OUT
#define LBA_PORT_OUT(size, mask) \
static void lba_pat_out##size (struct pci_hba_data *l, u16 addr, u##size val) \
{ \
void __iomem *where = PIOP_TO_GMMIO(LBA_DEV(l), addr); \
DBG_PORT("%s(0x%p, 0x%x, 0x%x)\n", __func__, l, addr, val); \
WRITE_REG##size(val, where); \
/* flush the I/O down to the elroy at least */ \
lba_t32 = READ_U32(l->base_addr + LBA_FUNC_ID); \
}
LBA_PORT_OUT( 8, 3)
LBA_PORT_OUT(16, 2)
LBA_PORT_OUT(32, 0)
static struct pci_port_ops lba_pat_port_ops = {
.inb = lba_pat_in8,
.inw = lba_pat_in16,
.inl = lba_pat_in32,
.outb = lba_pat_out8,
.outw = lba_pat_out16,
.outl = lba_pat_out32
};
/*
** make range information from PDC available to PCI subsystem.
** We make the PDC call here in order to get the PCI bus range
** numbers. The rest will get forwarded in pcibios_fixup_bus().
** We don't have a struct pci_bus assigned to us yet.
*/
static void
lba_pat_resources(struct parisc_device *pa_dev, struct lba_device *lba_dev)
{
unsigned long bytecnt;
long io_count;
long status; /* PDC return status */
long pa_count;
pdc_pat_cell_mod_maddr_block_t *pa_pdc_cell; /* PA_VIEW */
pdc_pat_cell_mod_maddr_block_t *io_pdc_cell; /* IO_VIEW */
int i;
pa_pdc_cell = kzalloc(sizeof(pdc_pat_cell_mod_maddr_block_t), GFP_KERNEL);
if (!pa_pdc_cell)
return;
io_pdc_cell = kzalloc(sizeof(pdc_pat_cell_mod_maddr_block_t), GFP_KERNEL);
if (!io_pdc_cell) {
kfree(pa_pdc_cell);
return;
}