Merge pull request openhwgroup#53 from Silabs-ArjanB/ArjanB_core_inte…

…gration

Added integration chapter

cores/cv32e40p/user_manual/source/debug.rst

@@ -1,3 +1,5 @@
+.. _debug-support:
+
 Debug
 =====
 

cores/cv32e40p/user_manual/source/fpu.rst

@@ -1,12 +1,14 @@
+.. _fpu:
+
 Optional private Floating Point Unit (FPU)
 ==========================================
 
 It is possible to extend the core with a private FPU, which is capable
 of performing all RISC-V floating-point operations that are defined in
 the RV32F ISA extensions. The latency of the individual instructions and
-information where they are computed are summarized in Table 3. FP
-extensions can be enabled by setting the parameter of the toplevel file
-“riscv\_core.sv” to one.
+information where they are computed are summarized in Table 3. Floating Point
+extensions can be enabled by setting the parameter ``FPU`` of the toplevel module
+``cv32e40p_core`` to 1.
 
 The FPU is divided into three parts:
 

cores/cv32e40p/user_manual/source/index.rst

@@ -8,6 +8,7 @@ Editor: **Davide Schiavone**
    :caption: Contents:
 
    intro
+   integration
    instruction_fetch
    load_store_unit
    apu

cores/cv32e40p/user_manual/source/instruction_fetch.rst

@@ -1,3 +1,5 @@
+.. _instruction-fetch:
+
 Instruction Fetch
 =================
 

cores/cv32e40p/user_manual/source/integration.rst

@@ -0,0 +1,164 @@
+.. _core-integration:
+
+Core Integration
+================
+
+The main module is named ``cv32e40p_core`` and can be found in ``cv32e40p_core.sv``.
+Below, the instantiation template is given and the parameters and interfaces are described.
+
+Instantiation Template
+----------------------
+
+.. code-block:: verilog
+
+  cv32e40p_core #(
+      .FPU                      ( 0 ),
+      .NUM_MHPMCOUNTERS         ( 1 ),
+      .PULP_CLUSTER             ( 0 ),
+      .PULP_HWLP                ( 0 ),
+      .PULP_ZFINX               ( 0 )
+  ) u_core (
+      // Clock and reset
+      .clk_i                    (),
+      .rst_ni                   (),
+      .scan_cg_en_i             (),
+
+      // Configuration
+      .boot_addr_i              (),
+      .dm_halt_addr_i           (),
+      .dm_exception_addr_i      (),
+      .hart_id_i                (),
+
+      // Instruction memory interface
+      .instr_req_o              (),
+      .instr_gnt_i              (),
+      .instr_rvalid_i           (),
+      .instr_addr_o             (),
+      .instr_rdata_i            (),
+
+      // Data memory interface
+      .data_req_o               (),
+      .data_gnt_i               (),
+      .data_rvalid_i            (),
+      .data_addr_o              (),
+      .data_be_o                (),
+      .data_wdata_o             (),
+      .data_we_o                (),
+      .data_rdata_i             (),
+
+      // Auxiliary Processing Unit (APU) interface
+      .apu_master_req_o         (),
+      .apu_master_ready_o       (),
+      .apu_master_gnt_i         (),
+      .apu_master_operands_o    (),
+      .apu_master_op_o          (),
+      .apu_master_type_o        (),
+      .apu_master_flags_o       (),
+      .apu_master_valid_i       (),
+      .apu_master_result_i      (),
+      .apu_master_flags_i       (),
+
+       // Interrupt interface
+      .irq_software_i           (),
+      .irq_timer_i              (),
+      .irq_external_i           (),
+      .irq_fast_i               (),
+      .irq_ack_o                (),
+      .irq_id_o                 (),
+
+      // Debug interface
+      .debug_req_i              (),
+
+      // Special control signals
+      .fetch_enable_i           (),
+      .core_sleep_o             (),
+      .clock_en_i               (),
+      .core_busy_o              ()
+  );
+
+Parameters
+----------
+
++------------------------------+-------------+------------+-----------------------------------------------------------------+
+| Name                         | Type/Range  | Default    | Description                                                     |
++==============================+=============+============+=================================================================+
+| ``FPU``                      | bit         | 0          | Enable Floating Point Unit (FPU) support, see :ref:`fpu`        |
++------------------------------+-------------+------------+-----------------------------------------------------------------+
+| ``NUM_MHPMCOUNTERS``         | int (1..29) | 1          | Number of MHPMCOUNTER performance counters, see                 |
+|                              |             |            | :ref:`performance-counters`                                     |
++------------------------------+-------------+------------+-----------------------------------------------------------------+
+| ``PULP_CLUSTER``             | bit         | 0          | Enable PULP Cluster support, see :ref:`pulp_cluster`            |
++------------------------------+-------------+------------+-----------------------------------------------------------------+
+| ``PULP_HWLP``                | bit         | 0          | Enable PULP Hardware Loop support, see :ref:`pulp_hardware_loop`|
+|                              |             |            | ``PULP_HWLP`` = 1 IS NOT SUPPORTED YET (IT IS UNDER DESIGN)     |
++------------------------------+-------------+------------+-----------------------------------------------------------------+
+| ``PULP_ZFINX``               | bit         | 0          | Enable Floating Point instructions to use the General Purpose   |
+|                              |             |            | register file instead of requiring a dedicated Floating Point   |
+|                              |             |            | register file, see :ref:`fpu`. Only allowed to be set to 1      |
+|                              |             |            | if ``FPU`` = 1                                                  |
++------------------------------+-------------+------------+-----------------------------------------------------------------+
+
+Interfaces
+----------
+
++-------------------------+-------------------------+-----+--------------------------------------------+
+| Signal(s)               | Width                   | Dir | Description                                |
++=========================+=========================+=====+============================================+
+| ``clk_i``               | 1                       | in  | Clock signal                               |
++-------------------------+-------------------------+-----+--------------------------------------------+
+| ``rst_ni``              | 1                       | in  | Active-low asynchronous reset              |
++-------------------------+-------------------------+-----+--------------------------------------------+
+| ``scan_cg_en_i``        | 1                       | in  | Scan clock gate enable                     |
++-------------------------+-------------------------+-----+--------------------------------------------+
+| ``boot_addr_i``         | 32                      | in  | Boot address. First program counter after  |
+|                         |                         |     | reset = ``boot_addr_i``. Must be half-word |
+|                         |                         |     | aligned. Do not change after enabling core |
+|                         |                         |     | via ``fetch_enable_i``                     |
++-------------------------+-------------------------+-----+--------------------------------------------+
+| ``dm_halt_addr_i``      | 32                      | in  | Address to jump to when entering Debug     |
+|                         |                         |     | Mode, see :ref:`debug-support`. Must be    |
+|                         |                         |     | word-aligned. Do not change after enabling |
+|                         |                         |     | core via ``fetch_enable_i``                |
++-------------------------+-------------------------+-----+--------------------------------------------+
+| ``dm_exception_addr_i`` | 32                      | in  | Address to jump to when an exception       |
+|                         |                         |     | occurs when executing code during Debug    |
+|                         |                         |     | Mode, see :ref:`debug-support`. Must be    |
+|                         |                         |     | word-aligned. Do not change after enabling |
+|                         |                         |     | core via ``fetch_enable_i``                |
++-------------------------+-------------------------+-----+--------------------------------------------+
+| ``hart_id_i``           | 32                      | in  | Hart ID, usually static, can be read from  |
+|                         |                         |     | :ref:`csr-mhartid` CSR                     |
++-------------------------+-------------------------+-----+--------------------------------------------+
+| ``instr_*``             | Instruction fetch interface, see :ref:`instruction-fetch`                  |
++-------------------------+----------------------------------------------------------------------------+
+| ``data_*``              | Load-store unit interface, see :ref:`load-store-unit`                      |
++-------------------------+----------------------------------------------------------------------------+
+| ``apu_*``               | Auxiliary Processing Unit (APU) interface, see :ref:`apu`                  |
++-------------------------+----------------------------------------------------------------------------+
+| ``irq_*``               | Interrupt inputs, see :ref:`exceptions-interrupts`                         |
++-------------------------+----------------------------------------------------------------------------+
+| ``debug_*``             | Debug interface, see :ref:`debug-support`                                  |
++-------------------------+-------------------------+-----+--------------------------------------------+
+| ``fetch_enable_i``      | 1                       | in  | Enable the instruction fetch of CV32E40P.  |
+|                         |                         |     | The first instruction fetch after reset    |
+|                         |                         |     | de-assertion will not happen as long as    |
+|                         |                         |     | this signal is 0. ``fetch_enable_i`` needs |
+|                         |                         |     | to be set to 1 for at least one cycle      |
+|                         |                         |     | while not in reset to enable fetching.     |
+|                         |                         |     | Once fetching has been enabled the value   |
+|                         |                         |     | ``fetch_enable_i`` is ignored.             |
++-------------------------+-------------------------+-----+--------------------------------------------+
+| ``core_sleep_o``        | 1                       | out | Core blocked on WFI with no outstanding    |
+|                         |                         |     | data or instruction accesses. Deasserts    |
+|                         |                         |     | if an external event (``irq_*`` or         |
+|                         |                         |     | ``debug_*`` ) wakes the core up. The       |
+|                         |                         |     | ``core_sleep_o`` signal can be used as an  |
+|                         |                         |     | indication for whether ``clk_i`` is        |
+|                         |                         |     | required                                   |
++-------------------------+-------------------------+-----+--------------------------------------------+
+| ``clock_en_i``          | 1                       | in  | Clock enable (only used when               |
+|                         |                         |     | ``PULP_CLUSTER`` = 1), see                 |
+|                         |                         |     | :ref:`pulp_cluster`                        |
++-------------------------+-------------------------+-----+--------------------------------------------+
+| ``core_busy_o``         | 1                       | out | Core busy, see :ref:`pulp_cluster`         |  
++-------------------------+-------------------------+-----+--------------------------------------------+

cores/cv32e40p/user_manual/source/intro.rst

@@ -74,16 +74,19 @@ Optional Floating Point Support
 -------------------------------
 
 Floating-point support in the form of IEEE-754 single precision can be
-enabled by setting the parameter **FPU** of the toplevel file
-"riscv\_core" to one. This will instantiate the FPU in the execution
-stage and extend the ALU to support the floating-point comparisons and
-classifications. By default a dedicated register file consisting of 32
+enabled by setting the parameter ``FPU`` of the toplevel module ``cv32e40p_core``
+to 1. This will instantiate the FPU in the execution
+stage, and also extend the register file to host floating-point operands
+and extend the ALU to support the floating-point comparisons and
+classifications.
+By default a dedicated register file consisting of 32
 floating-point registers, f0-f31, is instantiated. This default behavior
 can be overruled by setting the parameter **PULP_ZFINX** of the toplevel
-file "riscv\_core" to one, in which case the dedicated register file is
+file "cv32e40p\_core" to one, in which case the dedicated register file is
 not included and the general purpose register file is used instead to
 host the floating-point operands.
 
+
 ASIC Synthesis
 --------------
 

cores/cv32e40p/user_manual/source/load_store_unit.rst

@@ -1,3 +1,5 @@
+.. _load-store-unit:
+
 Load-Store-Unit (LSU)
 =====================