From 85960f9eddbd47089fe840747ce89a9bba8e4337 Mon Sep 17 00:00:00 2001 From: semihalf-oleksy-michalina Date: Sat, 29 Jul 2017 12:27:32 +0200 Subject: [PATCH] arm64: handling of system registers added in ARMv8.1/2 (#960) * arm64: handling of system registers added in ARMv8.2 This commit adds handling of system registers added in ARMv8.2. Those registers are accessed by mrs and msr instructions. Changes based on https://static.docs.arm.com/ddi0487/b/DDI0487B_a_armv8_arm.pdf, chapters D7.2-5. List of added registers: id_mmfr4_el1 id_aa64mmfr2_el1 sctlr_el12 cpacr_el12 ttbr0_el12 ttbr1_el12 ttbr1_el2 tcr_el12 spsr_el12 elr_el12 afsr0_el12 afsr1_el12 esr_el12 far_el12 mair_el12 amair_el12 vbar_el12 cntkctl_el12 cnthv_ctl_el2 cnthv_cval_el2 cnthv_tval_el2 cntp_tval_el02 cntp_cval_el02 cntv_ctl_el02 ntv_cval_el02 cntv_tval_el02 lorid_el1 lorc_el1 lorea_el1 lorn_el1 lorsa_el1 contextidr_el12 sign-of: Michalina Oleksy (https://github.com/layika) * arm64: handling of system registers added in ARMv8.1/2 v8.1: PAN (https://static.docs.arm.com/ddi0487/b/DDI0487B_a_armv8_arm.pdf, page 358) PAN (as pstate field) contextdir_el2 v8.2: UAO (https://static.docs.arm.com/ddi0487/b/DDI0487B_a_armv8_arm.pdf, page 403) UAO (as pstate field) * arm64: handling of system registers for statistical profiling Added handling of system registers for statistical profiling extension based on https://static.docs.arm.com/ddi0586/a/DDI0586A_Statistical_Profiling_Extension.pdf * Update AArch64BaseInfo.h * arm64: An attempt to fix indentation --- arch/AArch64/AArch64BaseInfo.c | 62 +++++++++++++- arch/AArch64/AArch64BaseInfo.h | 56 ++++++++++++- suite/MC/AArch64/basic-a64-instructions.s.cs | 85 ++++++++++++++++---- 3 files changed, 180 insertions(+), 23 deletions(-) diff --git a/arch/AArch64/AArch64BaseInfo.c b/arch/AArch64/AArch64BaseInfo.c index e999c1db70..468d0ff1b2 100644 --- a/arch/AArch64/AArch64BaseInfo.c +++ b/arch/AArch64/AArch64BaseInfo.c @@ -99,6 +99,8 @@ static char *utostr(uint64_t X, bool isNeg) } static A64NamedImmMapper_Mapping SysRegPairs[] = { + {"pan", A64SysReg_PAN}, + {"uao", A64SysReg_UAO}, {"osdtrrx_el1", A64SysReg_OSDTRRX_EL1}, {"osdtrtx_el1", A64SysReg_OSDTRTX_EL1}, {"teecr32_el1", A64SysReg_TEECR32_EL1}, @@ -180,12 +182,14 @@ static A64NamedImmMapper_Mapping SysRegPairs[] = { {"vpidr_el2", A64SysReg_VPIDR_EL2}, {"vmpidr_el2", A64SysReg_VMPIDR_EL2}, {"sctlr_el1", A64SysReg_SCTLR_EL1}, + {"sctlr_el12", A64SysReg_SCTLR_EL12}, {"sctlr_el2", A64SysReg_SCTLR_EL2}, {"sctlr_el3", A64SysReg_SCTLR_EL3}, {"actlr_el1", A64SysReg_ACTLR_EL1}, {"actlr_el2", A64SysReg_ACTLR_EL2}, {"actlr_el3", A64SysReg_ACTLR_EL3}, {"cpacr_el1", A64SysReg_CPACR_EL1}, + {"cpacr_el12", A64SysReg_CPACR_EL12}, {"hcr_el2", A64SysReg_HCR_EL2}, {"scr_el3", A64SysReg_SCR_EL3}, {"mdcr_el2", A64SysReg_MDCR_EL2}, @@ -196,19 +200,25 @@ static A64NamedImmMapper_Mapping SysRegPairs[] = { {"hacr_el2", A64SysReg_HACR_EL2}, {"mdcr_el3", A64SysReg_MDCR_EL3}, {"ttbr0_el1", A64SysReg_TTBR0_EL1}, + {"ttbr0_el12", A64SysReg_TTBR0_EL12}, {"ttbr0_el2", A64SysReg_TTBR0_EL2}, {"ttbr0_el3", A64SysReg_TTBR0_EL3}, {"ttbr1_el1", A64SysReg_TTBR1_EL1}, + {"ttbr1_el12", A64SysReg_TTBR1_EL12}, + {"ttbr1_el2", A64SysReg_TTBR1_EL2}, {"tcr_el1", A64SysReg_TCR_EL1}, + {"tcr_el12", A64SysReg_TCR_EL12}, {"tcr_el2", A64SysReg_TCR_EL2}, {"tcr_el3", A64SysReg_TCR_EL3}, {"vttbr_el2", A64SysReg_VTTBR_EL2}, {"vtcr_el2", A64SysReg_VTCR_EL2}, {"dacr32_el2", A64SysReg_DACR32_EL2}, {"spsr_el1", A64SysReg_SPSR_EL1}, + {"spsr_el12", A64SysReg_SPSR_EL12}, {"spsr_el2", A64SysReg_SPSR_EL2}, {"spsr_el3", A64SysReg_SPSR_EL3}, {"elr_el1", A64SysReg_ELR_EL1}, + {"elr_el12", A64SysReg_ELR_EL12}, {"elr_el2", A64SysReg_ELR_EL2}, {"elr_el3", A64SysReg_ELR_EL3}, {"sp_el0", A64SysReg_SP_EL0}, @@ -228,16 +238,20 @@ static A64NamedImmMapper_Mapping SysRegPairs[] = { {"dlr_el0", A64SysReg_DLR_EL0}, {"ifsr32_el2", A64SysReg_IFSR32_EL2}, {"afsr0_el1", A64SysReg_AFSR0_EL1}, + {"afsr0_el12", A64SysReg_AFSR0_EL12}, {"afsr0_el2", A64SysReg_AFSR0_EL2}, {"afsr0_el3", A64SysReg_AFSR0_EL3}, {"afsr1_el1", A64SysReg_AFSR1_EL1}, + {"afsr1_el12", A64SysReg_AFSR1_EL12}, {"afsr1_el2", A64SysReg_AFSR1_EL2}, {"afsr1_el3", A64SysReg_AFSR1_EL3}, {"esr_el1", A64SysReg_ESR_EL1}, + {"esr_el12", A64SysReg_ESR_EL12}, {"esr_el2", A64SysReg_ESR_EL2}, {"esr_el3", A64SysReg_ESR_EL3}, {"fpexc32_el2", A64SysReg_FPEXC32_EL2}, {"far_el1", A64SysReg_FAR_EL1}, + {"far_el12", A64SysReg_FAR_EL12}, {"far_el2", A64SysReg_FAR_EL2}, {"far_el3", A64SysReg_FAR_EL3}, {"hpfar_el2", A64SysReg_HPFAR_EL2}, @@ -255,18 +269,23 @@ static A64NamedImmMapper_Mapping SysRegPairs[] = { {"pmintenclr_el1", A64SysReg_PMINTENCLR_EL1}, {"pmovsset_el0", A64SysReg_PMOVSSET_EL0}, {"mair_el1", A64SysReg_MAIR_EL1}, + {"mair_el12", A64SysReg_MAIR_EL12}, {"mair_el2", A64SysReg_MAIR_EL2}, {"mair_el3", A64SysReg_MAIR_EL3}, {"amair_el1", A64SysReg_AMAIR_EL1}, + {"amair_el12", A64SysReg_AMAIR_EL12}, {"amair_el2", A64SysReg_AMAIR_EL2}, {"amair_el3", A64SysReg_AMAIR_EL3}, {"vbar_el1", A64SysReg_VBAR_EL1}, + {"vbar_el12", A64SysReg_VBAR_EL12}, {"vbar_el2", A64SysReg_VBAR_EL2}, {"vbar_el3", A64SysReg_VBAR_EL3}, {"rmr_el1", A64SysReg_RMR_EL1}, {"rmr_el2", A64SysReg_RMR_EL2}, {"rmr_el3", A64SysReg_RMR_EL3}, {"contextidr_el1", A64SysReg_CONTEXTIDR_EL1}, + {"contextidr_el12", A64SysReg_CONTEXTIDR_EL12}, + {"contextidr_el2", A64SysReg_CONTEXTIDR_EL2}, {"tpidr_el0", A64SysReg_TPIDR_EL0}, {"tpidr_el2", A64SysReg_TPIDR_EL2}, {"tpidr_el3", A64SysReg_TPIDR_EL3}, @@ -275,19 +294,28 @@ static A64NamedImmMapper_Mapping SysRegPairs[] = { {"cntfrq_el0", A64SysReg_CNTFRQ_EL0}, {"cntvoff_el2", A64SysReg_CNTVOFF_EL2}, {"cntkctl_el1", A64SysReg_CNTKCTL_EL1}, + {"cntkctl_el12", A64SysReg_CNTKCTL_EL12}, {"cnthctl_el2", A64SysReg_CNTHCTL_EL2}, {"cntp_tval_el0", A64SysReg_CNTP_TVAL_EL0}, + {"cntp_tval_el02", A64SysReg_CNTP_TVAL_EL02}, {"cnthp_tval_el2", A64SysReg_CNTHP_TVAL_EL2}, {"cntps_tval_el1", A64SysReg_CNTPS_TVAL_EL1}, {"cntp_ctl_el0", A64SysReg_CNTP_CTL_EL0}, {"cnthp_ctl_el2", A64SysReg_CNTHP_CTL_EL2}, + {"cnthv_ctl_el2", A64SysReg_CNTHVCTL_EL2}, + {"cnthv_cval_el2", A64SysReg_CNTHV_CVAL_EL2}, + {"cnthv_tval_el2", A64SysReg_CNTHV_TVAL_EL2}, {"cntps_ctl_el1", A64SysReg_CNTPS_CTL_EL1}, {"cntp_cval_el0", A64SysReg_CNTP_CVAL_EL0}, + {"cntp_cval_el02", A64SysReg_CNTP_CVAL_EL02}, {"cnthp_cval_el2", A64SysReg_CNTHP_CVAL_EL2}, {"cntps_cval_el1", A64SysReg_CNTPS_CVAL_EL1}, {"cntv_tval_el0", A64SysReg_CNTV_TVAL_EL0}, + {"cntv_tval_el02", A64SysReg_CNTV_TVAL_EL02}, {"cntv_ctl_el0", A64SysReg_CNTV_CTL_EL0}, + {"cntv_ctl_el02", A64SysReg_CNTV_CTL_EL02}, {"cntv_cval_el0", A64SysReg_CNTV_CVAL_EL0}, + {"cntv_cval_el02", A64SysReg_CNTV_CVAL_EL02}, {"pmevcntr0_el0", A64SysReg_PMEVCNTR0_EL0}, {"pmevcntr1_el0", A64SysReg_PMEVCNTR1_EL0}, {"pmevcntr2_el0", A64SysReg_PMEVCNTR2_EL0}, @@ -351,6 +379,10 @@ static A64NamedImmMapper_Mapping SysRegPairs[] = { {"pmevtyper28_el0", A64SysReg_PMEVTYPER28_EL0}, {"pmevtyper29_el0", A64SysReg_PMEVTYPER29_EL0}, {"pmevtyper30_el0", A64SysReg_PMEVTYPER30_EL0}, + {"lorc_el1", A64SysReg_LORC_EL1}, + {"lorea_el1", A64SysReg_LOREA_EL1}, + {"lorn_el1", A64SysReg_LORN_EL1}, + {"lorsa_el1", A64SysReg_LORSA_EL1}, // Trace registers {"trcprgctlr", A64SysReg_TRCPRGCTLR}, @@ -574,7 +606,20 @@ static A64NamedImmMapper_Mapping SysRegPairs[] = { {"ich_lr12_el2", A64SysReg_ICH_LR12_EL2}, {"ich_lr13_el2", A64SysReg_ICH_LR13_EL2}, {"ich_lr14_el2", A64SysReg_ICH_LR14_EL2}, - {"ich_lr15_el2", A64SysReg_ICH_LR15_EL2} + {"ich_lr15_el2", A64SysReg_ICH_LR15_EL2}, + + // Statistical profiling registers + {"pmblimitr_el1", A64SysReg_PMBLIMITR_EL1}, + {"pmbptr_el1", A64SysReg_PMBPTR_EL1}, + {"pmbsr_el1", A64SysReg_PMBSR_EL1}, + {"pmscr_el1", A64SysReg_PMSCR_EL1}, + {"pmscr_el12", A64SysReg_PMSCR_EL12}, + {"pmscr_el2", A64SysReg_PMSCR_EL2}, + {"pmsicr_el1", A64SysReg_PMSICR_EL1}, + {"pmsirr_el1", A64SysReg_PMSIRR_EL1}, + {"pmsfcr_el1", A64SysReg_PMSFCR_EL1}, + {"pmsevfr_el1", A64SysReg_PMSEVFR_EL1}, + {"pmslatfr_el1", A64SysReg_PMSLATFR_EL1} }; static A64NamedImmMapper_Mapping CycloneSysRegPairs[] = { @@ -705,7 +750,7 @@ static A64NamedImmMapper_Mapping ATPairs[] = { {"s12e1r", A64AT_S12E1R}, {"s12e1w", A64AT_S12E1W}, {"s12e0r", A64AT_S12E0R}, - {"s12e0w", A64AT_S12E0W}, + {"s12e0w", A64AT_S12E0W} }; A64NamedImmMapper A64AT_ATMapper = { @@ -804,7 +849,9 @@ A64NamedImmMapper A64PRFM_PRFMMapper = { static A64NamedImmMapper_Mapping PStatePairs[] = { {"spsel", A64PState_SPSel}, {"daifset", A64PState_DAIFSet}, - {"daifclr", A64PState_DAIFClr} + {"daifclr", A64PState_DAIFClr}, + {"pan", A64PState_PAN}, + {"uao", A64PState_UAO} }; A64NamedImmMapper A64PState_PStateMapper = { @@ -837,6 +884,7 @@ static A64NamedImmMapper_Mapping MRSPairs[] = { {"id_mmfr1_el1", A64SysReg_ID_MMFR1_EL1}, {"id_mmfr2_el1", A64SysReg_ID_MMFR2_EL1}, {"id_mmfr3_el1", A64SysReg_ID_MMFR3_EL1}, + {"id_mmfr4_el1", A64SysReg_ID_MMFR4_EL1}, {"id_isar0_el1", A64SysReg_ID_ISAR0_EL1}, {"id_isar1_el1", A64SysReg_ID_ISAR1_EL1}, {"id_isar2_el1", A64SysReg_ID_ISAR2_EL1}, @@ -853,6 +901,8 @@ static A64NamedImmMapper_Mapping MRSPairs[] = { {"id_aa64isar1_el1", A64SysReg_ID_A64ISAR1_EL1}, {"id_aa64mmfr0_el1", A64SysReg_ID_A64MMFR0_EL1}, {"id_aa64mmfr1_el1", A64SysReg_ID_A64MMFR1_EL1}, + {"id_aa64mmfr2_el1", A64SysReg_ID_A64MMFR2_EL1}, + {"lorid_el1", A64SysReg_LORID_EL1}, {"mvfr0_el1", A64SysReg_MVFR0_EL1}, {"mvfr1_el1", A64SysReg_MVFR1_EL1}, {"mvfr2_el1", A64SysReg_MVFR2_EL1}, @@ -909,7 +959,11 @@ static A64NamedImmMapper_Mapping MRSPairs[] = { {"icc_rpr_el1", A64SysReg_ICC_RPR_EL1}, {"ich_vtr_el2", A64SysReg_ICH_VTR_EL2}, {"ich_eisr_el2", A64SysReg_ICH_EISR_EL2}, - {"ich_elsr_el2", A64SysReg_ICH_ELSR_EL2} + {"ich_elsr_el2", A64SysReg_ICH_ELSR_EL2}, + + // Statistical profiling registers + {"pmsidr_el1", A64SysReg_PMSIDR_EL1}, + {"pmbidr_el1", A64SysReg_PMBIDR_EL1} }; A64SysRegMapper AArch64_MRSMapper = { diff --git a/arch/AArch64/AArch64BaseInfo.h b/arch/AArch64/AArch64BaseInfo.h index 82221f9ad1..f988e87709 100644 --- a/arch/AArch64/AArch64BaseInfo.h +++ b/arch/AArch64/AArch64BaseInfo.h @@ -249,7 +249,9 @@ enum A64PStateValues { A64PState_Invalid = -1, A64PState_SPSel = 0x05, A64PState_DAIFSet = 0x1e, - A64PState_DAIFClr = 0x1f + A64PState_DAIFClr = 0x1f, + A64PState_PAN = 0x4, + A64PState_UAO = 0x3 }; typedef enum A64SE_ShiftExtSpecifiers { @@ -334,6 +336,7 @@ enum A64SysRegROValues { A64SysReg_ID_MMFR1_EL1 = 0xc00d, // 11 000 0000 0001 101 A64SysReg_ID_MMFR2_EL1 = 0xc00e, // 11 000 0000 0001 110 A64SysReg_ID_MMFR3_EL1 = 0xc00f, // 11 000 0000 0001 111 + A64SysReg_ID_MMFR4_EL1 = 0xc016, // 11 000 0000 0010 110 A64SysReg_ID_ISAR0_EL1 = 0xc010, // 11 000 0000 0010 000 A64SysReg_ID_ISAR1_EL1 = 0xc011, // 11 000 0000 0010 001 A64SysReg_ID_ISAR2_EL1 = 0xc012, // 11 000 0000 0010 010 @@ -350,6 +353,12 @@ enum A64SysRegROValues { A64SysReg_ID_A64ISAR1_EL1 = 0xc031, // 11 000 0000 0110 001 A64SysReg_ID_A64MMFR0_EL1 = 0xc038, // 11 000 0000 0111 000 A64SysReg_ID_A64MMFR1_EL1 = 0xc039, // 11 000 0000 0111 001 + A64SysReg_ID_A64MMFR2_EL1 = 0xC03A, // 11 000 0000 0111 010 + A64SysReg_LORC_EL1 = 0xc523, // 11 000 1010 0100 011 + A64SysReg_LOREA_EL1 = 0xc521, // 11 000 1010 0100 001 + A64SysReg_LORID_EL1 = 0xc527, // 11 000 1010 0100 111 + A64SysReg_LORN_EL1 = 0xc522, // 11 000 1010 0100 010 + A64SysReg_LORSA_EL1 = 0xc520, // 11 000 1010 0100 000 A64SysReg_MVFR0_EL1 = 0xc018, // 11 000 0000 0011 000 A64SysReg_MVFR1_EL1 = 0xc019, // 11 000 0000 0011 001 A64SysReg_MVFR2_EL1 = 0xc01a, // 11 000 0000 0011 010 @@ -429,6 +438,8 @@ enum A64SysRegWOValues { enum A64SysRegValues { A64SysReg_Invalid = -1, // Op0 Op1 CRn CRm Op2 + A64SysReg_PAN = 0xc213, // 11 000 0100 0010 011 + A64SysReg_UAO = 0xc214, // 11 000 0100 0010 100 A64SysReg_OSDTRRX_EL1 = 0x8002, // 10 000 0000 0000 010 A64SysReg_OSDTRTX_EL1 = 0x801a, // 10 000 0000 0011 010 A64SysReg_TEECR32_EL1 = 0x9000, // 10 010 0000 0000 000 @@ -510,7 +521,9 @@ enum A64SysRegValues { A64SysReg_VPIDR_EL2 = 0xe000, // 11 100 0000 0000 000 A64SysReg_VMPIDR_EL2 = 0xe005, // 11 100 0000 0000 101 A64SysReg_CPACR_EL1 = 0xc082, // 11 000 0001 0000 010 + A64SysReg_CPACR_EL12 = 0xe882, // 11 101 0001 0000 010 A64SysReg_SCTLR_EL1 = 0xc080, // 11 000 0001 0000 000 + A64SysReg_SCTLR_EL12 = 0xe880, // 11 101 0001 0000 000 A64SysReg_SCTLR_EL2 = 0xe080, // 11 100 0001 0000 000 A64SysReg_SCTLR_EL3 = 0xf080, // 11 110 0001 0000 000 A64SysReg_ACTLR_EL1 = 0xc081, // 11 000 0001 0000 001 @@ -526,19 +539,25 @@ enum A64SysRegValues { A64SysReg_HACR_EL2 = 0xe08f, // 11 100 0001 0001 111 A64SysReg_MDCR_EL3 = 0xf099, // 11 110 0001 0011 001 A64SysReg_TTBR0_EL1 = 0xc100, // 11 000 0010 0000 000 + A64SysReg_TTBR0_EL12 = 0xe900, // 11 101 0010 0000 000 A64SysReg_TTBR0_EL2 = 0xe100, // 11 100 0010 0000 000 A64SysReg_TTBR0_EL3 = 0xf100, // 11 110 0010 0000 000 A64SysReg_TTBR1_EL1 = 0xc101, // 11 000 0010 0000 001 + A64SysReg_TTBR1_EL12 = 0xe901, // 11 101 0010 0000 001 + A64SysReg_TTBR1_EL2 = 0xe101, // 11 100 0010 0000 001 A64SysReg_TCR_EL1 = 0xc102, // 11 000 0010 0000 010 + A64SysReg_TCR_EL12 = 0xe902, // 11 101 0010 0000 010 A64SysReg_TCR_EL2 = 0xe102, // 11 100 0010 0000 010 A64SysReg_TCR_EL3 = 0xf102, // 11 110 0010 0000 010 A64SysReg_VTTBR_EL2 = 0xe108, // 11 100 0010 0001 000 A64SysReg_VTCR_EL2 = 0xe10a, // 11 100 0010 0001 010 A64SysReg_DACR32_EL2 = 0xe180, // 11 100 0011 0000 000 A64SysReg_SPSR_EL1 = 0xc200, // 11 000 0100 0000 000 + A64SysReg_SPSR_EL12 = 0xea00, // 11 101 0100 0000 000 A64SysReg_SPSR_EL2 = 0xe200, // 11 100 0100 0000 000 A64SysReg_SPSR_EL3 = 0xf200, // 11 110 0100 0000 000 A64SysReg_ELR_EL1 = 0xc201, // 11 000 0100 0000 001 + A64SysReg_ELR_EL12 = 0xea01, // 11 101 0100 0000 001 A64SysReg_ELR_EL2 = 0xe201, // 11 100 0100 0000 001 A64SysReg_ELR_EL3 = 0xf201, // 11 110 0100 0000 001 A64SysReg_SP_EL0 = 0xc208, // 11 000 0100 0001 000 @@ -558,16 +577,20 @@ enum A64SysRegValues { A64SysReg_DLR_EL0 = 0xda29, // 11 011 0100 0101 001 A64SysReg_IFSR32_EL2 = 0xe281, // 11 100 0101 0000 001 A64SysReg_AFSR0_EL1 = 0xc288, // 11 000 0101 0001 000 + A64SysReg_AFSR0_EL12 = 0xea88, // 11 101 0101 0001 000 A64SysReg_AFSR0_EL2 = 0xe288, // 11 100 0101 0001 000 A64SysReg_AFSR0_EL3 = 0xf288, // 11 110 0101 0001 000 A64SysReg_AFSR1_EL1 = 0xc289, // 11 000 0101 0001 001 + A64SysReg_AFSR1_EL12 = 0xea89, // 11 101 0101 0001 001 A64SysReg_AFSR1_EL2 = 0xe289, // 11 100 0101 0001 001 A64SysReg_AFSR1_EL3 = 0xf289, // 11 110 0101 0001 001 A64SysReg_ESR_EL1 = 0xc290, // 11 000 0101 0010 000 + A64SysReg_ESR_EL12 = 0xea90, // 11 101 0101 0010 000 A64SysReg_ESR_EL2 = 0xe290, // 11 100 0101 0010 000 A64SysReg_ESR_EL3 = 0xf290, // 11 110 0101 0010 000 A64SysReg_FPEXC32_EL2 = 0xe298, // 11 100 0101 0011 000 A64SysReg_FAR_EL1 = 0xc300, // 11 000 0110 0000 000 + A64SysReg_FAR_EL12 = 0xeb00, // 11 101 0110 0000 000 A64SysReg_FAR_EL2 = 0xe300, // 11 100 0110 0000 000 A64SysReg_FAR_EL3 = 0xf300, // 11 110 0110 0000 000 A64SysReg_HPFAR_EL2 = 0xe304, // 11 100 0110 0000 100 @@ -585,18 +608,23 @@ enum A64SysRegValues { A64SysReg_PMINTENCLR_EL1 = 0xc4f2, // 11 000 1001 1110 010 A64SysReg_PMOVSSET_EL0 = 0xdcf3, // 11 011 1001 1110 011 A64SysReg_MAIR_EL1 = 0xc510, // 11 000 1010 0010 000 + A64SysReg_MAIR_EL12 = 0xed10, // 11 101 1010 0010 000 A64SysReg_MAIR_EL2 = 0xe510, // 11 100 1010 0010 000 A64SysReg_MAIR_EL3 = 0xf510, // 11 110 1010 0010 000 A64SysReg_AMAIR_EL1 = 0xc518, // 11 000 1010 0011 000 + A64SysReg_AMAIR_EL12 = 0xed18, // 11 101 1010 0011 000 A64SysReg_AMAIR_EL2 = 0xe518, // 11 100 1010 0011 000 A64SysReg_AMAIR_EL3 = 0xf518, // 11 110 1010 0011 000 A64SysReg_VBAR_EL1 = 0xc600, // 11 000 1100 0000 000 + A64SysReg_VBAR_EL12 = 0xee00, // 11 101 1100 0000 000 A64SysReg_VBAR_EL2 = 0xe600, // 11 100 1100 0000 000 A64SysReg_VBAR_EL3 = 0xf600, // 11 110 1100 0000 000 A64SysReg_RMR_EL1 = 0xc602, // 11 000 1100 0000 010 A64SysReg_RMR_EL2 = 0xe602, // 11 100 1100 0000 010 A64SysReg_RMR_EL3 = 0xf602, // 11 110 1100 0000 010 A64SysReg_CONTEXTIDR_EL1 = 0xc681, // 11 000 1101 0000 001 + A64SysReg_CONTEXTIDR_EL12 = 0xee81, // 11 101 1101 0000 001 + A64SysReg_CONTEXTIDR_EL2 = 0xe681, // 11 100 1101 0000 001 A64SysReg_TPIDR_EL0 = 0xde82, // 11 011 1101 0000 010 A64SysReg_TPIDR_EL2 = 0xe682, // 11 100 1101 0000 010 A64SysReg_TPIDR_EL3 = 0xf682, // 11 110 1101 0000 010 @@ -605,19 +633,28 @@ enum A64SysRegValues { A64SysReg_CNTFRQ_EL0 = 0xdf00, // 11 011 1110 0000 000 A64SysReg_CNTVOFF_EL2 = 0xe703, // 11 100 1110 0000 011 A64SysReg_CNTKCTL_EL1 = 0xc708, // 11 000 1110 0001 000 + A64SysReg_CNTKCTL_EL12 = 0xef08, // 11 101 1110 0001 000 A64SysReg_CNTHCTL_EL2 = 0xe708, // 11 100 1110 0001 000 + A64SysReg_CNTHVCTL_EL2 = 0xe719, // 11 100 1110 0011 001 + A64SysReg_CNTHV_CVAL_EL2 = 0xe71a, // 11 100 1110 0011 010 + A64SysReg_CNTHV_TVAL_EL2 = 0xe718, // 11 100 1110 0011 000 A64SysReg_CNTP_TVAL_EL0 = 0xdf10, // 11 011 1110 0010 000 + A64SysReg_CNTP_TVAL_EL02 = 0xef10, // 11 101 1110 0010 000 A64SysReg_CNTHP_TVAL_EL2 = 0xe710, // 11 100 1110 0010 000 A64SysReg_CNTPS_TVAL_EL1 = 0xff10, // 11 111 1110 0010 000 A64SysReg_CNTP_CTL_EL0 = 0xdf11, // 11 011 1110 0010 001 A64SysReg_CNTHP_CTL_EL2 = 0xe711, // 11 100 1110 0010 001 A64SysReg_CNTPS_CTL_EL1 = 0xff11, // 11 111 1110 0010 001 A64SysReg_CNTP_CVAL_EL0 = 0xdf12, // 11 011 1110 0010 010 + A64SysReg_CNTP_CVAL_EL02 = 0xef12, // 11 101 1110 0010 010 A64SysReg_CNTHP_CVAL_EL2 = 0xe712, // 11 100 1110 0010 010 A64SysReg_CNTPS_CVAL_EL1 = 0xff12, // 11 111 1110 0010 010 A64SysReg_CNTV_TVAL_EL0 = 0xdf18, // 11 011 1110 0011 000 + A64SysReg_CNTV_TVAL_EL02 = 0xef18, // 11 101 1110 0011 000 A64SysReg_CNTV_CTL_EL0 = 0xdf19, // 11 011 1110 0011 001 + A64SysReg_CNTV_CTL_EL02 = 0xef19, // 11 101 1110 0011 001 A64SysReg_CNTV_CVAL_EL0 = 0xdf1a, // 11 011 1110 0011 010 + A64SysReg_CNTV_CVAL_EL02 = 0xef1a, // 11 101 1110 0011 010 A64SysReg_PMEVCNTR0_EL0 = 0xdf40, // 11 011 1110 1000 000 A64SysReg_PMEVCNTR1_EL0 = 0xdf41, // 11 011 1110 1000 001 A64SysReg_PMEVCNTR2_EL0 = 0xdf42, // 11 011 1110 1000 010 @@ -904,7 +941,22 @@ enum A64SysRegValues { A64SysReg_ICH_LR12_EL2 = 0xe66c, // 11 100 1100 1101 100 A64SysReg_ICH_LR13_EL2 = 0xe66d, // 11 100 1100 1101 101 A64SysReg_ICH_LR14_EL2 = 0xe66e, // 11 100 1100 1101 110 - A64SysReg_ICH_LR15_EL2 = 0xe66f // 11 100 1100 1101 111 + A64SysReg_ICH_LR15_EL2 = 0xe66f, // 11 100 1100 1101 111 + + // Statistical profiling registers + A64SysReg_PMSIDR_EL1 = 0xc4cf, // 11 000 1001 1001 111 + A64SysReg_PMBIDR_EL1 = 0xc4d7, // 11 000 1001 1010 111 + A64SysReg_PMBLIMITR_EL1 = 0xc4d0, // 11 000 1001 1010 000 + A64SysReg_PMBPTR_EL1 = 0xc4d1, // 11 000 1001 1010 001 + A64SysReg_PMBSR_EL1 = 0xc4d3, // 11 000 1001 1010 011 + A64SysReg_PMSCR_EL1 = 0xc4c8, // 11 000 1001 1001 000 + A64SysReg_PMSCR_EL12 = 0xecc8, // 11 101 1001 1001 000 + A64SysReg_PMSCR_EL2 = 0xe4c8, // 11 100 1001 1001 000 + A64SysReg_PMSICR_EL1 = 0xc4ca, // 11 000 1001 1001 010 + A64SysReg_PMSIRR_EL1 = 0xc4cb, // 11 000 1001 1001 011 + A64SysReg_PMSFCR_EL1 = 0xc4cc, // 11 000 1001 1001 100 + A64SysReg_PMSEVFR_EL1 = 0xc4cd, // 11 000 1001 1001 101 + A64SysReg_PMSLATFR_EL1 = 0xc4ce // 11 000 1001 1001 110 }; // Cyclone specific system registers diff --git a/suite/MC/AArch64/basic-a64-instructions.s.cs b/suite/MC/AArch64/basic-a64-instructions.s.cs index 8a13171e02..5509356e4c 100644 --- a/suite/MC/AArch64/basic-a64-instructions.s.cs +++ b/suite/MC/AArch64/basic-a64-instructions.s.cs @@ -668,9 +668,9 @@ 0x41,0x05,0xa0,0xd4 = dcps1 #42 0x22,0x01,0xa0,0xd4 = dcps2 #9 0x03,0x7d,0xa0,0xd4 = dcps3 #1000 -0x01,0x00,0xa0,0xd4 = dcps1 -0x02,0x00,0xa0,0xd4 = dcps2 -0x03,0x00,0xa0,0xd4 = dcps3 +0x01,0x00,0xa0,0xd4 = dcps1 +0x02,0x00,0xa0,0xd4 = dcps2 +0x03,0x00,0xa0,0xd4 = dcps3 0xa3,0x00,0x87,0x13 = extr w3, w5, w7, #0 0xab,0x7d,0x91,0x13 = extr w11, w13, w17, #31 0xa3,0x3c,0xc7,0x93 = extr x3, x5, x7, #15 @@ -1337,18 +1337,18 @@ 0x02,0x00,0x80,0x10 = adr x2, #-1048576 0xe9,0xff,0x7f,0xf0 = adrp x9, #4294963200 0x14,0x00,0x80,0x90 = adrp x20, #-4294967296 -0x1f,0x20,0x03,0xd5 = nop +0x1f,0x20,0x03,0xd5 = nop 0xff,0x2f,0x03,0xd5 = hint #127 -0x1f,0x20,0x03,0xd5 = nop -0x3f,0x20,0x03,0xd5 = yield -0x5f,0x20,0x03,0xd5 = wfe -0x7f,0x20,0x03,0xd5 = wfi -0x9f,0x20,0x03,0xd5 = sev -0xbf,0x20,0x03,0xd5 = sevl -0x5f,0x3f,0x03,0xd5 = clrex +0x1f,0x20,0x03,0xd5 = nop +0x3f,0x20,0x03,0xd5 = yield +0x5f,0x20,0x03,0xd5 = wfe +0x7f,0x20,0x03,0xd5 = wfi +0x9f,0x20,0x03,0xd5 = sev +0xbf,0x20,0x03,0xd5 = sevl +0x5f,0x3f,0x03,0xd5 = clrex 0x5f,0x30,0x03,0xd5 = clrex #0 0x5f,0x37,0x03,0xd5 = clrex #7 -0x5f,0x3f,0x03,0xd5 = clrex +0x5f,0x3f,0x03,0xd5 = clrex 0x9f,0x30,0x03,0xd5 = dsb #0 0x9f,0x3c,0x03,0xd5 = dsb #12 0x9f,0x3f,0x03,0xd5 = dsb sy @@ -1379,12 +1379,14 @@ 0xbf,0x3d,0x03,0xd5 = dmb ld 0xbf,0x3e,0x03,0xd5 = dmb st 0xbf,0x3f,0x03,0xd5 = dmb sy -0xdf,0x3f,0x03,0xd5 = isb -0xdf,0x3f,0x03,0xd5 = isb +0xdf,0x3f,0x03,0xd5 = isb +0xdf,0x3f,0x03,0xd5 = isb 0xdf,0x3c,0x03,0xd5 = isb #12 0xbf,0x40,0x00,0xd5 = msr spsel, #0 0xdf,0x4f,0x03,0xd5 = msr daifset, #15 0xff,0x4c,0x03,0xd5 = msr daifclr, #12 +0x9f,0x40,0x00,0xd5 = msr pan, #0 +0x7f,0x40,0x00,0xd5 = msr uao, #0 0xe5,0x59,0x0f,0xd5 = sys #7, c5, c9, #7, x5 0x5f,0xff,0x08,0xd5 = sys #0, c15, c15, #2, xzr 0xe9,0x59,0x2f,0xd5 = sysl x9, #7, c5, c9, #7 @@ -1575,9 +1577,11 @@ 0x2c,0x45,0x1b,0xd5 = msr dlr_el0, x12 0x2c,0x50,0x1c,0xd5 = msr ifsr32_el2, x12 0x0c,0x51,0x18,0xd5 = msr afsr0_el1, x12 + 0x0c,0x51,0x1c,0xd5 = msr afsr0_el2, x12 0x0c,0x51,0x1e,0xd5 = msr afsr0_el3, x12 0x2c,0x51,0x18,0xd5 = msr afsr1_el1, x12 +0x2c,0x51,0x1d,0xd5 = msr afsr1_el12, x12 0x2c,0x51,0x1c,0xd5 = msr afsr1_el2, x12 0x2c,0x51,0x1e,0xd5 = msr afsr1_el3, x12 0x0c,0x52,0x18,0xd5 = msr esr_el1, x12 @@ -1633,6 +1637,7 @@ 0x4c,0xe2,0x1c,0xd5 = msr cnthp_cval_el2, x12 0x4c,0xe2,0x1f,0xd5 = msr cntps_cval_el1, x12 0x0c,0xe3,0x1b,0xd5 = msr cntv_tval_el0, x12 +0x0c,0xe3,0x1d,0xd5 = msr cntv_tval_el02, x12 0x2c,0xe3,0x1b,0xd5 = msr cntv_ctl_el0, x12 0x4c,0xe3,0x1b,0xd5 = msr cntv_cval_el0, x12 0x0c,0xe8,0x1b,0xd5 = msr pmevcntr0_el0, x12 @@ -1698,6 +1703,8 @@ 0x8c,0xef,0x1b,0xd5 = msr pmevtyper28_el0, x12 0xac,0xef,0x1b,0xd5 = msr pmevtyper29_el0, x12 0xcc,0xef,0x1b,0xd5 = msr pmevtyper30_el0, x12 +0x69,0x42,0x38,0xd5 = mrs x9, pan +0x89,0x42,0x38,0xd5 = mrs x9, uao 0x09,0x00,0x32,0xd5 = mrs x9, teecr32_el1 0x49,0x00,0x30,0xd5 = mrs x9, osdtrrx_el1 0x09,0x01,0x33,0xd5 = mrs x9, mdccsr_el0 @@ -1799,6 +1806,7 @@ 0xa9,0x01,0x38,0xd5 = mrs x9, id_mmfr1_el1 0xc9,0x01,0x38,0xd5 = mrs x9, id_mmfr2_el1 0xe9,0x01,0x38,0xd5 = mrs x9, id_mmfr3_el1 +0xc9,0x02,0x38,0xd5 = mrs x9, id_mmfr4_el1 0x09,0x02,0x38,0xd5 = mrs x9, id_isar0_el1 0x29,0x02,0x38,0xd5 = mrs x9, id_isar1_el1 0x49,0x02,0x38,0xd5 = mrs x9, id_isar2_el1 @@ -1818,13 +1826,21 @@ 0x29,0x06,0x38,0xd5 = mrs x9, id_aa64isar1_el1 0x09,0x07,0x38,0xd5 = mrs x9, id_aa64mmfr0_el1 0x29,0x07,0x38,0xd5 = mrs x9, id_aa64mmfr1_el1 +0x49,0x07,0x38,0xd5 = mrs x9, id_aa64mmfr2_el1 +0x69,0xa4,0x38,0xd5 = mrs x9, lorc_el1 +0x29,0xa4,0x38,0xd5 = mrs x9, lorea_el1 +0xe9,0xa4,0x38,0xd5 = mrs x9, lorid_el1 +0x49,0xa4,0x38,0xd5 = mrs x9, lorn_el1 +0x09,0xa4,0x38,0xd5 = mrs x9, lorsa_el1 0x09,0x10,0x38,0xd5 = mrs x9, sctlr_el1 +0x09,0x10,0x3d,0xd5 = mrs x9, sctlr_el12 0x09,0x10,0x3c,0xd5 = mrs x9, sctlr_el2 0x09,0x10,0x3e,0xd5 = mrs x9, sctlr_el3 0x29,0x10,0x38,0xd5 = mrs x9, actlr_el1 0x29,0x10,0x3c,0xd5 = mrs x9, actlr_el2 0x29,0x10,0x3e,0xd5 = mrs x9, actlr_el3 0x49,0x10,0x38,0xd5 = mrs x9, cpacr_el1 +0x49,0x10,0x3d,0xd5 = mrs x9, cpacr_el12 0x09,0x11,0x3c,0xd5 = mrs x9, hcr_el2 0x09,0x11,0x3e,0xd5 = mrs x9, scr_el3 0x29,0x11,0x3c,0xd5 = mrs x9, mdcr_el2 @@ -1835,19 +1851,25 @@ 0xe9,0x11,0x3c,0xd5 = mrs x9, hacr_el2 0x29,0x13,0x3e,0xd5 = mrs x9, mdcr_el3 0x09,0x20,0x38,0xd5 = mrs x9, ttbr0_el1 +0x09,0x20,0x3d,0xd5 = mrs x9, ttbr0_el12 0x09,0x20,0x3c,0xd5 = mrs x9, ttbr0_el2 0x09,0x20,0x3e,0xd5 = mrs x9, ttbr0_el3 0x29,0x20,0x38,0xd5 = mrs x9, ttbr1_el1 +0x29,0x20,0x3d,0xd5 = mrs x9, ttbr1_el12 +0x29,0x20,0x3c,0xd5 = mrs x9, ttbr1_el2 0x49,0x20,0x38,0xd5 = mrs x9, tcr_el1 +0x49,0x20,0x3d,0xd5 = mrs x9, tcr_el12 0x49,0x20,0x3c,0xd5 = mrs x9, tcr_el2 0x49,0x20,0x3e,0xd5 = mrs x9, tcr_el3 0x09,0x21,0x3c,0xd5 = mrs x9, vttbr_el2 0x49,0x21,0x3c,0xd5 = mrs x9, vtcr_el2 0x09,0x30,0x3c,0xd5 = mrs x9, dacr32_el2 0x09,0x40,0x38,0xd5 = mrs x9, spsr_el1 +0x09,0x40,0x3d,0xd5 = mrs x9, spsr_el12 0x09,0x40,0x3c,0xd5 = mrs x9, spsr_el2 0x09,0x40,0x3e,0xd5 = mrs x9, spsr_el3 0x29,0x40,0x38,0xd5 = mrs x9, elr_el1 +0x29,0x40,0x3d,0xd5 = mrs x9, elr_el12 0x29,0x40,0x3c,0xd5 = mrs x9, elr_el2 0x29,0x40,0x3e,0xd5 = mrs x9, elr_el3 0x09,0x41,0x38,0xd5 = mrs x9, sp_el0 @@ -1867,16 +1889,19 @@ 0x29,0x45,0x3b,0xd5 = mrs x9, dlr_el0 0x29,0x50,0x3c,0xd5 = mrs x9, ifsr32_el2 0x09,0x51,0x38,0xd5 = mrs x9, afsr0_el1 +0x09,0x51,0x3d,0xd5 = mrs x9, afsr0_el12 0x09,0x51,0x3c,0xd5 = mrs x9, afsr0_el2 0x09,0x51,0x3e,0xd5 = mrs x9, afsr0_el3 0x29,0x51,0x38,0xd5 = mrs x9, afsr1_el1 0x29,0x51,0x3c,0xd5 = mrs x9, afsr1_el2 0x29,0x51,0x3e,0xd5 = mrs x9, afsr1_el3 0x09,0x52,0x38,0xd5 = mrs x9, esr_el1 +0x09,0x52,0x3d,0xd5 = mrs x9, esr_el12 0x09,0x52,0x3c,0xd5 = mrs x9, esr_el2 0x09,0x52,0x3e,0xd5 = mrs x9, esr_el3 0x09,0x53,0x3c,0xd5 = mrs x9, fpexc32_el2 0x09,0x60,0x38,0xd5 = mrs x9, far_el1 +0x09,0x60,0x3d,0xd5 = mrs x9, far_el12 0x09,0x60,0x3c,0xd5 = mrs x9, far_el2 0x09,0x60,0x3e,0xd5 = mrs x9, far_el3 0x89,0x60,0x3c,0xd5 = mrs x9, hpfar_el2 @@ -1896,12 +1921,15 @@ 0x49,0x9e,0x38,0xd5 = mrs x9, pmintenclr_el1 0x69,0x9e,0x3b,0xd5 = mrs x9, pmovsset_el0 0x09,0xa2,0x38,0xd5 = mrs x9, mair_el1 +0x09,0xa2,0x3d,0xd5 = mrs x9, mair_el12 0x09,0xa2,0x3c,0xd5 = mrs x9, mair_el2 0x09,0xa2,0x3e,0xd5 = mrs x9, mair_el3 0x09,0xa3,0x38,0xd5 = mrs x9, amair_el1 +0x09,0xa3,0x3d,0xd5 = mrs x9, amair_el12 0x09,0xa3,0x3c,0xd5 = mrs x9, amair_el2 0x09,0xa3,0x3e,0xd5 = mrs x9, amair_el3 0x09,0xc0,0x38,0xd5 = mrs x9, vbar_el1 +0x09,0xc0,0x3d,0xd5 = mrs x9, vbar_el12 0x09,0xc0,0x3c,0xd5 = mrs x9, vbar_el2 0x09,0xc0,0x3e,0xd5 = mrs x9, vbar_el3 0x29,0xc0,0x38,0xd5 = mrs x9, rvbar_el1 @@ -1912,6 +1940,8 @@ 0x49,0xc0,0x3e,0xd5 = mrs x9, rmr_el3 0x09,0xc1,0x38,0xd5 = mrs x9, isr_el1 0x29,0xd0,0x38,0xd5 = mrs x9, contextidr_el1 +0x29,0xd0,0x3d,0xd5 = mrs x9, contextidr_el12 +0x29,0xd0,0x3c,0xd5 = mrs x9, contextdir_el2 0x49,0xd0,0x3b,0xd5 = mrs x9, tpidr_el0 0x49,0xd0,0x3c,0xd5 = mrs x9, tpidr_el2 0x49,0xd0,0x3e,0xd5 = mrs x9, tpidr_el3 @@ -1922,19 +1952,27 @@ 0x49,0xe0,0x3b,0xd5 = mrs x9, cntvct_el0 0x69,0xe0,0x3c,0xd5 = mrs x9, cntvoff_el2 0x09,0xe1,0x38,0xd5 = mrs x9, cntkctl_el1 +0x09,0xe1,0x3d,0xd5 = mrs x9, cntkctl_el12 0x09,0xe1,0x3c,0xd5 = mrs x9, cnthctl_el2 0x09,0xe2,0x3b,0xd5 = mrs x9, cntp_tval_el0 +0x09,0xe2,0x3d,0xd5 = mrs x9, cntp_tval_el02 0x09,0xe2,0x3c,0xd5 = mrs x9, cnthp_tval_el2 0x09,0xe2,0x3f,0xd5 = mrs x9, cntps_tval_el1 0x29,0xe2,0x3b,0xd5 = mrs x9, cntp_ctl_el0 0x29,0xe2,0x3c,0xd5 = mrs x9, cnthp_ctl_el2 0x29,0xe2,0x3f,0xd5 = mrs x9, cntps_ctl_el1 0x49,0xe2,0x3b,0xd5 = mrs x9, cntp_cval_el0 +0x49,0xe2,0x3d,0xd5 = mrs x9, cntp_cval_el02 0x49,0xe2,0x3c,0xd5 = mrs x9, cnthp_cval_el2 +0x20,0xe3,0x3c,0xd5 = mrs x9, cnthv_ctl_el2 +0x49,0xe3,0x3c,0xd5 = mrs x9, cnthv_cval_el2 +0x09,0xe3,0x3c,0xd5 = mrs x9, cnthv_tval_el2 0x49,0xe2,0x3f,0xd5 = mrs x9, cntps_cval_el1 0x09,0xe3,0x3b,0xd5 = mrs x9, cntv_tval_el0 0x29,0xe3,0x3b,0xd5 = mrs x9, cntv_ctl_el0 +0x29,0xe3,0x3d,0xd5 = mrs x9, cntv_ctl_el02 0x49,0xe3,0x3b,0xd5 = mrs x9, cntv_cval_el0 +0x49,0xe3,0x3d,0xd5 = mrs x9, cntv_cval_el02 0x09,0xe8,0x3b,0xd5 = mrs x9, pmevcntr0_el0 0x29,0xe8,0x3b,0xd5 = mrs x9, pmevcntr1_el0 0x49,0xe8,0x3b,0xd5 = mrs x9, pmevcntr2_el0 @@ -1998,6 +2036,19 @@ 0x89,0xef,0x3b,0xd5 = mrs x9, pmevtyper28_el0 0xa9,0xef,0x3b,0xd5 = mrs x9, pmevtyper29_el0 0xc9,0xef,0x3b,0xd5 = mrs x9, pmevtyper30_el0 +0xe9,0x99,0x38,0xd5 = mrs x9, pmsidr_el1 +0xe9,0x9a,0x38,0xd5 = mrs x9, pmbidr_el1 +0x09,0x9a,0x38,0xd5 = mrs x9, pmblimitr_el1 +0x29,0x9a,0x38,0xd5 = mrs x9, pmbptr_el1 +0x69,0x9a,0x38,0xd5 = mrs x9, pmbsr_el1 +0x09,0x99,0x38,0xd5 = mrs x9, pmscr_el1 +0x09,0x99,0x3d,0xd5 = mrs x9, pmscr_el12 +0x09,0x99,0x3c,0xd5 = mrs x9, pmscr_el2 +0x49,0x99,0x38,0xd5 = mrs x9, pmsicr_el1 +0x69,0x99,0x38,0xd5 = mrs x9, pmsirr_el1 +0x89,0x99,0x38,0xd5 = mrs x9, pmsfcr_el1 +0xa9,0x99,0x38,0xd5 = mrs x9, pmsevfr_el1 +0xc9,0x99,0x38,0xd5 = mrs x9, pmslatfr_el1 0xac,0xf1,0x3f,0xd5 = mrs x12, s3_7_c15_c1_5 0xed,0xbf,0x3a,0xd5 = mrs x13, s3_2_c11_c15_7 0x0c,0xf0,0x18,0xd5 = msr s3_0_c15_c0_0, x12 @@ -2009,6 +2060,6 @@ 0x80,0x02,0x1f,0xd6 = br x20 0xe0,0x03,0x3f,0xd6 = blr xzr 0x40,0x01,0x5f,0xd6 = ret x10 -0xc0,0x03,0x5f,0xd6 = ret -0xe0,0x03,0x9f,0xd6 = eret -0xe0,0x03,0xbf,0xd6 = drps +0xc0,0x03,0x5f,0xd6 = ret +0xe0,0x03,0x9f,0xd6 = eret +0xe0,0x03,0xbf,0xd6 = drps