diff --git a/project/stm32f407/EW/stm32f407.dep b/project/stm32f407/EW/stm32f407.dep
new file mode 100644
index 0000000..32fc2ae
--- /dev/null
+++ b/project/stm32f407/EW/stm32f407.dep
@@ -0,0 +1,16 @@
+
+
+ 5
+ 4104993926
+
+ Release
+
+ $PROJ_DIR$\..\..\..\test\driver_w25qxx_register_test.c
+ $PROJ_DIR$\..\..\..\test\driver_w25qxx_read_test.c
+ $PROJ_DIR$\..\hal\asm\startup_stm32f407xx_ew.s
+
+
+ [REBUILD_ALL]
+
+
+
diff --git a/project/stm32f407/EW/stm32f407.ewd b/project/stm32f407/EW/stm32f407.ewd
new file mode 100644
index 0000000..b7fbb34
--- /dev/null
+++ b/project/stm32f407/EW/stm32f407.ewd
@@ -0,0 +1,1517 @@
+
+
+ 3
+
+ Release
+
+ ARM
+
+ 0
+
+ C-SPY
+ 2
+
+ 32
+ 1
+ 0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ ARMSIM_ID
+ 2
+
+ 1
+ 1
+ 0
+
+
+
+
+
+
+
+ CADI_ID
+ 2
+
+ 0
+ 1
+ 0
+
+
+
+
+
+
+
+
+ CMSISDAP_ID
+ 2
+
+ 4
+ 1
+ 0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ GDBSERVER_ID
+ 2
+
+ 0
+ 1
+ 0
+
+
+
+
+
+
+
+
+
+
+ IJET_ID
+ 2
+
+ 9
+ 1
+ 0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ JLINK_ID
+ 2
+
+ 16
+ 1
+ 0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LMIFTDI_ID
+ 2
+
+ 2
+ 1
+ 0
+
+
+
+
+
+
+
+
+
+ NULINK_ID
+ 2
+
+ 0
+ 1
+ 0
+
+
+
+
+
+
+ PEMICRO_ID
+ 2
+
+ 3
+ 1
+ 0
+
+
+
+
+
+
+
+ STLINK_ID
+ 2
+
+ 7
+ 1
+ 0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ THIRDPARTY_ID
+ 2
+
+ 0
+ 1
+ 0
+
+
+
+
+
+
+
+ TIFET_ID
+ 2
+
+ 1
+ 1
+ 0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ XDS100_ID
+ 2
+
+ 8
+ 1
+ 0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9BE.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+ 0
+
+
+ $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+ 0
+
+
+ $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+ 0
+
+
+ $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+ 0
+
+
+
+
diff --git a/project/stm32f407/EW/stm32f407.ewp b/project/stm32f407/EW/stm32f407.ewp
new file mode 100644
index 0000000..d5de7b4
--- /dev/null
+++ b/project/stm32f407/EW/stm32f407.ewp
@@ -0,0 +1,1385 @@
+
+
+ 3
+
+ Release
+
+ ARM
+
+ 0
+
+ General
+ 3
+
+ 33
+ 1
+ 0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ ICCARM
+ 2
+
+ 37
+ 1
+ 0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ AARM
+ 2
+
+ 11
+ 1
+ 0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ OBJCOPY
+ 0
+
+ 1
+ 1
+ 0
+
+
+
+
+
+
+
+
+ CUSTOM
+ 3
+
+
+
+ 1
+ inputOutputBased
+
+
+
+ BUILDACTION
+ 1
+
+
+
+
+
+
+ ILINK
+ 0
+
+ 25
+ 1
+ 0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ IARCHIVE
+ 0
+
+ 0
+ 1
+ 0
+
+
+
+
+
+
+
+ driver
+
+ $PROJ_DIR$\..\..\..\src\driver_w25qxx.c
+
+
+ $PROJ_DIR$\..\driver\src\stm32f407_driver_w25qxx_interface.c
+
+
+
+ example
+
+ $PROJ_DIR$\..\..\..\example\driver_w25qxx_advance.c
+
+
+ $PROJ_DIR$\..\..\..\example\driver_w25qxx_basic.c
+
+
+
+ hal
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_adc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_adc_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_can.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_cec.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_cortex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_crc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_cryp.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_cryp_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_dac.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_dac_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_dcmi.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_dcmi_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_dfsdm.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_dma.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_dma2d.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_dma_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_dsi.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_eth.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_exti.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_flash.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_flash_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_flash_ramfunc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_fmpi2c.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_fmpi2c_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_gpio.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_hash.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_hash_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_hcd.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_i2c.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_i2c_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_i2s.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_i2s_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_irda.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_iwdg.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_lptim.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_ltdc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_ltdc_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_mmc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_nand.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_nor.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_pccard.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_pcd.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_pcd_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_pwr.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_pwr_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_qspi.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_rcc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_rcc_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_rng.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_rtc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_rtc_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_sai.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_sai_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_sd.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_sdram.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_smartcard.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_smbus.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_spdifrx.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_spi.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_sram.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_tim.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_tim_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_uart.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_usart.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_wwdg.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_ll_adc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_ll_crc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_ll_dac.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_ll_dma.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_ll_dma2d.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_ll_exti.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_ll_fmc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_ll_fsmc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_ll_gpio.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_ll_i2c.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_ll_lptim.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_ll_pwr.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_ll_rcc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_ll_rng.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_ll_rtc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_ll_sdmmc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_ll_spi.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_ll_tim.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_ll_usart.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_ll_usb.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_ll_utils.c
+
+
+
+ interface
+
+ $PROJ_DIR$\..\interface\src\clock.c
+
+
+ $PROJ_DIR$\..\interface\src\delay.c
+
+
+ $PROJ_DIR$\..\interface\src\spi.c
+
+
+ $PROJ_DIR$\..\interface\src\uart.c
+
+
+
+ startup
+
+ $PROJ_DIR$\..\hal\asm\startup_stm32f407xx_ew.s
+
+
+
+ test
+
+ $PROJ_DIR$\..\..\..\test\driver_w25qxx_read_test.c
+
+
+ $PROJ_DIR$\..\..\..\test\driver_w25qxx_register_test.c
+
+
+
+ usr
+
+ $PROJ_DIR$\..\usr\src\main.c
+
+
+ $PROJ_DIR$\..\usr\src\shell.c
+
+
+ $PROJ_DIR$\..\usr\src\stm32f4xx_hal_msp.c
+
+
+ $PROJ_DIR$\..\usr\src\stm32f4xx_it.c
+
+
+ $PROJ_DIR$\..\usr\src\system_stm32f4xx.c
+
+
+
diff --git a/project/stm32f407/EW/stm32f407.ewt b/project/stm32f407/EW/stm32f407.ewt
new file mode 100644
index 0000000..f70c2a7
--- /dev/null
+++ b/project/stm32f407/EW/stm32f407.ewt
@@ -0,0 +1,1754 @@
+
+
+ 3
+
+ Release
+
+ ARM
+
+ 0
+
+ C-STAT
+ 514
+
+ 514
+
+ 0
+
+ 1
+ 600
+ 1
+ 2
+ 0
+ 1
+ 100
+ $PROJ_DIR$\..\output\ew\release\c-stat
+
+
+ 2.2.0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
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+
+
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+
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+
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+
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+
+
+
+
+
+
+
+
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+
+
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+
+
+
+
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+
+
+
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+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ RuntimeChecking
+ 0
+
+ 2
+ 1
+ 0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ driver
+
+ $PROJ_DIR$\..\..\..\src\driver_w25qxx.c
+
+
+ $PROJ_DIR$\..\driver\src\stm32f407_driver_w25qxx_interface.c
+
+
+
+ example
+
+ $PROJ_DIR$\..\..\..\example\driver_w25qxx_advance.c
+
+
+ $PROJ_DIR$\..\..\..\example\driver_w25qxx_basic.c
+
+
+
+ hal
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_adc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_adc_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_can.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_cec.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_cortex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_crc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_cryp.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_cryp_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_dac.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_dac_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_dcmi.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_dcmi_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_dfsdm.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_dma.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_dma2d.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_dma_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_dsi.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_eth.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_exti.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_flash.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_flash_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_flash_ramfunc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_fmpi2c.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_fmpi2c_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_gpio.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_hash.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_hash_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_hcd.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_i2c.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_i2c_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_i2s.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_i2s_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_irda.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_iwdg.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_lptim.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_ltdc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_ltdc_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_mmc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_nand.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_nor.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_pccard.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_pcd.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_pcd_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_pwr.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_pwr_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_qspi.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_rcc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_rcc_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_rng.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_rtc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_rtc_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_sai.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_sai_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_sd.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_sdram.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_smartcard.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_smbus.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_spdifrx.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_spi.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_sram.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_tim.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_tim_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_uart.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_usart.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_hal_wwdg.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_ll_adc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_ll_crc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_ll_dac.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_ll_dma.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_ll_dma2d.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_ll_exti.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_ll_fmc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_ll_fsmc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_ll_gpio.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_ll_i2c.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_ll_lptim.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_ll_pwr.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_ll_rcc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_ll_rng.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_ll_rtc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_ll_sdmmc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_ll_spi.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_ll_tim.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_ll_usart.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_ll_usb.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f4xx_ll_utils.c
+
+
+
+ interface
+
+ $PROJ_DIR$\..\interface\src\clock.c
+
+
+ $PROJ_DIR$\..\interface\src\delay.c
+
+
+ $PROJ_DIR$\..\interface\src\spi.c
+
+
+ $PROJ_DIR$\..\interface\src\uart.c
+
+
+
+ startup
+
+ $PROJ_DIR$\..\hal\asm\startup_stm32f407xx_ew.s
+
+
+
+ test
+
+ $PROJ_DIR$\..\..\..\test\driver_w25qxx_read_test.c
+
+
+ $PROJ_DIR$\..\..\..\test\driver_w25qxx_register_test.c
+
+
+
+ usr
+
+ $PROJ_DIR$\..\usr\src\main.c
+
+
+ $PROJ_DIR$\..\usr\src\shell.c
+
+
+ $PROJ_DIR$\..\usr\src\stm32f4xx_hal_msp.c
+
+
+ $PROJ_DIR$\..\usr\src\stm32f4xx_it.c
+
+
+ $PROJ_DIR$\..\usr\src\system_stm32f4xx.c
+
+
+
diff --git a/project/stm32f407/EW/stm32f407.eww b/project/stm32f407/EW/stm32f407.eww
new file mode 100644
index 0000000..881a285
--- /dev/null
+++ b/project/stm32f407/EW/stm32f407.eww
@@ -0,0 +1,7 @@
+
+
+
+ $WS_DIR$\stm32f407.ewp
+
+
+
diff --git a/project/stm32f407/MDK/stm32f407.uvprojx b/project/stm32f407/MDK/stm32f407.uvprojx
index 89f0768..9dbb2d3 100644
--- a/project/stm32f407/MDK/stm32f407.uvprojx
+++ b/project/stm32f407/MDK/stm32f407.uvprojx
@@ -49,7 +49,7 @@
0
1
- ..\obj\
+ ..\output\mdk\
w25qxx
1
0
@@ -925,9 +925,9 @@
startup
- startup_stm32f407xx.s
+ startup_stm32f407xx_mdk.s
2
- ..\hal\asm\startup_stm32f407xx.s
+ ..\hal\asm\startup_stm32f407xx_mdk.s
diff --git a/project/stm32f407/hal/asm/startup_stm32f407xx_ew.s b/project/stm32f407/hal/asm/startup_stm32f407xx_ew.s
new file mode 100644
index 0000000..57738bb
--- /dev/null
+++ b/project/stm32f407/hal/asm/startup_stm32f407xx_ew.s
@@ -0,0 +1,636 @@
+;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;* File Name : startup_stm32f407xx.s
+;* Author : MCD Application Team
+;* Description : STM32F407xx devices vector table for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == _iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;* 3. Neither the name of STMicroelectronics nor the names of its contributors
+;* may be used to endorse or promote products derived from this software
+;* without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
+ DCD CAN1_TX_IRQHandler ; CAN1 TX
+ DCD CAN1_RX0_IRQHandler ; CAN1 RX0
+ DCD CAN1_RX1_IRQHandler ; CAN1 RX1
+ DCD CAN1_SCE_IRQHandler ; CAN1 SCE
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
+ DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
+ DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]s
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FSMC_IRQHandler ; FSMC
+ DCD SDIO_IRQHandler ; SDIO
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD ETH_IRQHandler ; Ethernet
+ DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
+ DCD CAN2_TX_IRQHandler ; CAN2 TX
+ DCD CAN2_RX0_IRQHandler ; CAN2 RX0
+ DCD CAN2_RX1_IRQHandler ; CAN2 RX1
+ DCD CAN2_SCE_IRQHandler ; CAN2 SCE
+ DCD OTG_FS_IRQHandler ; USB OTG FS
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_IRQHandler ; DCMI
+ DCD 0 ; Reserved
+ DCD HASH_RNG_IRQHandler ; Hash and RNG
+ DCD FPU_IRQHandler ; FPU
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+PVD_IRQHandler
+ B PVD_IRQHandler
+
+ PUBWEAK TAMP_STAMP_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TAMP_STAMP_IRQHandler
+ B TAMP_STAMP_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Stream0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Stream0_IRQHandler
+ B DMA1_Stream0_IRQHandler
+
+ PUBWEAK DMA1_Stream1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Stream1_IRQHandler
+ B DMA1_Stream1_IRQHandler
+
+ PUBWEAK DMA1_Stream2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Stream2_IRQHandler
+ B DMA1_Stream2_IRQHandler
+
+ PUBWEAK DMA1_Stream3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Stream3_IRQHandler
+ B DMA1_Stream3_IRQHandler
+
+ PUBWEAK DMA1_Stream4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Stream4_IRQHandler
+ B DMA1_Stream4_IRQHandler
+
+ PUBWEAK DMA1_Stream5_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Stream5_IRQHandler
+ B DMA1_Stream5_IRQHandler
+
+ PUBWEAK DMA1_Stream6_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Stream6_IRQHandler
+ B DMA1_Stream6_IRQHandler
+
+ PUBWEAK ADC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ADC_IRQHandler
+ B ADC_IRQHandler
+
+ PUBWEAK CAN1_TX_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CAN1_TX_IRQHandler
+ B CAN1_TX_IRQHandler
+
+ PUBWEAK CAN1_RX0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CAN1_RX0_IRQHandler
+ B CAN1_RX0_IRQHandler
+
+ PUBWEAK CAN1_RX1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CAN1_RX1_IRQHandler
+ B CAN1_RX1_IRQHandler
+
+ PUBWEAK CAN1_SCE_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CAN1_SCE_IRQHandler
+ B CAN1_SCE_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_TIM9_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM1_BRK_TIM9_IRQHandler
+ B TIM1_BRK_TIM9_IRQHandler
+
+ PUBWEAK TIM1_UP_TIM10_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM1_UP_TIM10_IRQHandler
+ B TIM1_UP_TIM10_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM1_TRG_COM_TIM11_IRQHandler
+ B TIM1_TRG_COM_TIM11_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK OTG_FS_WKUP_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+OTG_FS_WKUP_IRQHandler
+ B OTG_FS_WKUP_IRQHandler
+
+ PUBWEAK TIM8_BRK_TIM12_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM8_BRK_TIM12_IRQHandler
+ B TIM8_BRK_TIM12_IRQHandler
+
+ PUBWEAK TIM8_UP_TIM13_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM8_UP_TIM13_IRQHandler
+ B TIM8_UP_TIM13_IRQHandler
+
+ PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM8_TRG_COM_TIM14_IRQHandler
+ B TIM8_TRG_COM_TIM14_IRQHandler
+
+ PUBWEAK TIM8_CC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM8_CC_IRQHandler
+ B TIM8_CC_IRQHandler
+
+ PUBWEAK DMA1_Stream7_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Stream7_IRQHandler
+ B DMA1_Stream7_IRQHandler
+
+ PUBWEAK FSMC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+FSMC_IRQHandler
+ B FSMC_IRQHandler
+
+ PUBWEAK SDIO_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SDIO_IRQHandler
+ B SDIO_IRQHandler
+
+ PUBWEAK TIM5_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM5_IRQHandler
+ B TIM5_IRQHandler
+
+ PUBWEAK SPI3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SPI3_IRQHandler
+ B SPI3_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK UART5_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UART5_IRQHandler
+ B UART5_IRQHandler
+
+ PUBWEAK TIM6_DAC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM6_DAC_IRQHandler
+ B TIM6_DAC_IRQHandler
+
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+
+ PUBWEAK DMA2_Stream0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Stream0_IRQHandler
+ B DMA2_Stream0_IRQHandler
+
+ PUBWEAK DMA2_Stream1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Stream1_IRQHandler
+ B DMA2_Stream1_IRQHandler
+
+ PUBWEAK DMA2_Stream2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Stream2_IRQHandler
+ B DMA2_Stream2_IRQHandler
+
+ PUBWEAK DMA2_Stream3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Stream3_IRQHandler
+ B DMA2_Stream3_IRQHandler
+
+ PUBWEAK DMA2_Stream4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Stream4_IRQHandler
+ B DMA2_Stream4_IRQHandler
+
+ PUBWEAK ETH_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ETH_IRQHandler
+ B ETH_IRQHandler
+
+ PUBWEAK ETH_WKUP_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ETH_WKUP_IRQHandler
+ B ETH_WKUP_IRQHandler
+
+ PUBWEAK CAN2_TX_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CAN2_TX_IRQHandler
+ B CAN2_TX_IRQHandler
+
+ PUBWEAK CAN2_RX0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CAN2_RX0_IRQHandler
+ B CAN2_RX0_IRQHandler
+
+ PUBWEAK CAN2_RX1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CAN2_RX1_IRQHandler
+ B CAN2_RX1_IRQHandler
+
+ PUBWEAK CAN2_SCE_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CAN2_SCE_IRQHandler
+ B CAN2_SCE_IRQHandler
+
+ PUBWEAK OTG_FS_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+OTG_FS_IRQHandler
+ B OTG_FS_IRQHandler
+
+ PUBWEAK DMA2_Stream5_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Stream5_IRQHandler
+ B DMA2_Stream5_IRQHandler
+
+ PUBWEAK DMA2_Stream6_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Stream6_IRQHandler
+ B DMA2_Stream6_IRQHandler
+
+ PUBWEAK DMA2_Stream7_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Stream7_IRQHandler
+ B DMA2_Stream7_IRQHandler
+
+ PUBWEAK USART6_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USART6_IRQHandler
+ B USART6_IRQHandler
+
+ PUBWEAK I2C3_EV_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+I2C3_EV_IRQHandler
+ B I2C3_EV_IRQHandler
+
+ PUBWEAK I2C3_ER_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+I2C3_ER_IRQHandler
+ B I2C3_ER_IRQHandler
+
+ PUBWEAK OTG_HS_EP1_OUT_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+OTG_HS_EP1_OUT_IRQHandler
+ B OTG_HS_EP1_OUT_IRQHandler
+
+ PUBWEAK OTG_HS_EP1_IN_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+OTG_HS_EP1_IN_IRQHandler
+ B OTG_HS_EP1_IN_IRQHandler
+
+ PUBWEAK OTG_HS_WKUP_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+OTG_HS_WKUP_IRQHandler
+ B OTG_HS_WKUP_IRQHandler
+
+ PUBWEAK OTG_HS_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+OTG_HS_IRQHandler
+ B OTG_HS_IRQHandler
+
+ PUBWEAK DCMI_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DCMI_IRQHandler
+ B DCMI_IRQHandler
+
+ PUBWEAK HASH_RNG_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+HASH_RNG_IRQHandler
+ B HASH_RNG_IRQHandler
+
+ PUBWEAK FPU_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+FPU_IRQHandler
+ B FPU_IRQHandler
+
+ END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/project/stm32f407/hal/asm/startup_stm32f407xx.s b/project/stm32f407/hal/asm/startup_stm32f407xx_mdk.s
similarity index 100%
rename from project/stm32f407/hal/asm/startup_stm32f407xx.s
rename to project/stm32f407/hal/asm/startup_stm32f407xx_mdk.s
diff --git a/project/stm32f407/obj/obj_delete.bat b/project/stm32f407/output/mdk/obj_delete.bat
similarity index 93%
rename from project/stm32f407/obj/obj_delete.bat
rename to project/stm32f407/output/mdk/obj_delete.bat
index d90f4c5..e4a2ecd 100644
--- a/project/stm32f407/obj/obj_delete.bat
+++ b/project/stm32f407/output/mdk/obj_delete.bat
@@ -18,8 +18,6 @@ del *.d /s
del *.axf /s
del *.tra /s
del *.dep /s
-del JLinkLog.txt /s
-
del *.iex /s
del *.htm /s
del *.sct /s
diff --git a/project/stm32f407/usr/inc/stm32f4xx.h b/project/stm32f407/usr/inc/stm32f4xx.h
new file mode 100644
index 0000000..cedb597
--- /dev/null
+++ b/project/stm32f407/usr/inc/stm32f4xx.h
@@ -0,0 +1,269 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx.h
+ * @author MCD Application Team
+ * @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
+ *
+ * The file is the unique include file that the application programmer
+ * is using in the C source code, usually in main.c. This file contains:
+ * - Configuration section that allows to select:
+ * - The STM32F4xx device used in the target application
+ * - To use or not the peripheral’s drivers in application code(i.e.
+ * code will be based on direct access to peripheral’s registers
+ * rather than drivers API), this option is controlled by
+ * "#define USE_HAL_DRIVER"
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2017 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx
+ * @{
+ */
+
+#ifndef __STM32F4xx_H
+#define __STM32F4xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/**
+ * @brief STM32 Family
+ */
+#if !defined (STM32F4)
+#define STM32F4
+#endif /* STM32F4 */
+
+/* Uncomment the line below according to the target STM32 device used in your
+ application
+ */
+#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
+ !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
+ !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
+ !defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
+ !defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
+ !defined (STM32F412Zx) && !defined (STM32F413xx) && !defined (STM32F423xx)
+ /* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
+ /* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
+ /* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
+ /* #define STM32F417xx */ /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
+ /* #define STM32F427xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */
+ /* #define STM32F437xx */ /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */
+ /* #define STM32F429xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG,
+ STM32F439NI, STM32F429IG and STM32F429II Devices */
+ /* #define STM32F439xx */ /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG,
+ STM32F439NI, STM32F439IG and STM32F439II Devices */
+ /* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
+ /* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
+ /* #define STM32F410Tx */ /*!< STM32F410T8 and STM32F410TB Devices */
+ /* #define STM32F410Cx */ /*!< STM32F410C8 and STM32F410CB Devices */
+ /* #define STM32F410Rx */ /*!< STM32F410R8 and STM32F410RB Devices */
+ /* #define STM32F411xE */ /*!< STM32F411CC, STM32F411RC, STM32F411VC, STM32F411CE, STM32F411RE and STM32F411VE Devices */
+ /* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC,
+ and STM32F446ZE Devices */
+ /* #define STM32F469xx */ /*!< STM32F469AI, STM32F469II, STM32F469BI, STM32F469NI, STM32F469AG, STM32F469IG, STM32F469BG,
+ STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */
+ /* #define STM32F479xx */ /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG
+ and STM32F479NG Devices */
+ /* #define STM32F412Cx */ /*!< STM32F412CEU and STM32F412CGU Devices */
+ /* #define STM32F412Zx */ /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
+ /* #define STM32F412Vx */ /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
+ /* #define STM32F412Rx */ /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
+ /* #define STM32F413xx */ /*!< STM32F413CH, STM32F413MH, STM32F413RH, STM32F413VH, STM32F413ZH, STM32F413CG, STM32F413MG,
+ STM32F413RG, STM32F413VG and STM32F413ZG Devices */
+ /* #define STM32F423xx */ /*!< STM32F423CH, STM32F423RH, STM32F423VH and STM32F423ZH Devices */
+#endif
+
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+ */
+#if !defined (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+ /*#define USE_HAL_DRIVER */
+#endif /* USE_HAL_DRIVER */
+
+/**
+ * @brief CMSIS version number V2.6.2
+ */
+#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
+#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
+#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
+ |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
+ |(__STM32F4xx_CMSIS_VERSION_SUB2 << 8 )\
+ |(__STM32F4xx_CMSIS_VERSION))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Device_Included
+ * @{
+ */
+
+#if defined(STM32F405xx)
+ #include "stm32f405xx.h"
+#elif defined(STM32F415xx)
+ #include "stm32f415xx.h"
+#elif defined(STM32F407xx)
+ #include "stm32f407xx.h"
+#elif defined(STM32F417xx)
+ #include "stm32f417xx.h"
+#elif defined(STM32F427xx)
+ #include "stm32f427xx.h"
+#elif defined(STM32F437xx)
+ #include "stm32f437xx.h"
+#elif defined(STM32F429xx)
+ #include "stm32f429xx.h"
+#elif defined(STM32F439xx)
+ #include "stm32f439xx.h"
+#elif defined(STM32F401xC)
+ #include "stm32f401xc.h"
+#elif defined(STM32F401xE)
+ #include "stm32f401xe.h"
+#elif defined(STM32F410Tx)
+ #include "stm32f410tx.h"
+#elif defined(STM32F410Cx)
+ #include "stm32f410cx.h"
+#elif defined(STM32F410Rx)
+ #include "stm32f410rx.h"
+#elif defined(STM32F411xE)
+ #include "stm32f411xe.h"
+#elif defined(STM32F446xx)
+ #include "stm32f446xx.h"
+#elif defined(STM32F469xx)
+ #include "stm32f469xx.h"
+#elif defined(STM32F479xx)
+ #include "stm32f479xx.h"
+#elif defined(STM32F412Cx)
+ #include "stm32f412cx.h"
+#elif defined(STM32F412Zx)
+ #include "stm32f412zx.h"
+#elif defined(STM32F412Rx)
+ #include "stm32f412rx.h"
+#elif defined(STM32F412Vx)
+ #include "stm32f412vx.h"
+#elif defined(STM32F413xx)
+ #include "stm32f413xx.h"
+#elif defined(STM32F423xx)
+ #include "stm32f423xx.h"
+#else
+ #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_types
+ * @{
+ */
+typedef enum
+{
+ RESET = 0U,
+ SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+ DISABLE = 0U,
+ ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+ ERROR = 0U,
+ SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
+
+
+/**
+ * @}
+ */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32f4xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F4xx_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/project/stm32f767/EW/stm32f767.dep b/project/stm32f767/EW/stm32f767.dep
new file mode 100644
index 0000000..f28ffff
--- /dev/null
+++ b/project/stm32f767/EW/stm32f767.dep
@@ -0,0 +1,21 @@
+
+
+ 5
+ 4260931802
+
+ Release
+
+ $PROJ_DIR$\..\hal\asm\startup_stm32f767xx_ew.s
+ $PROJ_DIR$\..\..\..\test\driver_w25qxx_read_test.c
+ $PROJ_DIR$\..\usr\src\system_stm32f7xx.c
+ $PROJ_DIR$\..\usr\src\stm32f7xx_hal_msp.c
+ $PROJ_DIR$\..\..\..\test\driver_w25qxx_register_test.c
+ $PROJ_DIR$\..\usr\src\shell.c
+ $PROJ_DIR$\..\usr\src\stm32f7xx_it.c
+ $PROJ_DIR$\..\usr\src\main.c
+
+
+ [REBUILD_ALL]
+
+
+
diff --git a/project/stm32f767/EW/stm32f767.ewd b/project/stm32f767/EW/stm32f767.ewd
new file mode 100644
index 0000000..27cbde1
--- /dev/null
+++ b/project/stm32f767/EW/stm32f767.ewd
@@ -0,0 +1,1517 @@
+
+
+ 3
+
+ Release
+
+ ARM
+
+ 0
+
+ C-SPY
+ 2
+
+ 32
+ 1
+ 0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ ARMSIM_ID
+ 2
+
+ 1
+ 1
+ 0
+
+
+
+
+
+
+
+ CADI_ID
+ 2
+
+ 0
+ 1
+ 0
+
+
+
+
+
+
+
+
+ CMSISDAP_ID
+ 2
+
+ 4
+ 1
+ 0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ GDBSERVER_ID
+ 2
+
+ 0
+ 1
+ 0
+
+
+
+
+
+
+
+
+
+
+ IJET_ID
+ 2
+
+ 9
+ 1
+ 0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ JLINK_ID
+ 2
+
+ 16
+ 1
+ 0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LMIFTDI_ID
+ 2
+
+ 2
+ 1
+ 0
+
+
+
+
+
+
+
+
+
+ NULINK_ID
+ 2
+
+ 0
+ 1
+ 0
+
+
+
+
+
+
+ PEMICRO_ID
+ 2
+
+ 3
+ 1
+ 0
+
+
+
+
+
+
+
+ STLINK_ID
+ 2
+
+ 7
+ 1
+ 0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ THIRDPARTY_ID
+ 2
+
+ 0
+ 1
+ 0
+
+
+
+
+
+
+
+ TIFET_ID
+ 2
+
+ 1
+ 1
+ 0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ XDS100_ID
+ 2
+
+ 8
+ 1
+ 0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9BE.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+ 0
+
+
+ $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+ 0
+
+
+ $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+ 0
+
+
+ $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+ 0
+
+
+
+
diff --git a/project/stm32f767/EW/stm32f767.ewp b/project/stm32f767/EW/stm32f767.ewp
new file mode 100644
index 0000000..8aa61fb
--- /dev/null
+++ b/project/stm32f767/EW/stm32f767.ewp
@@ -0,0 +1,1376 @@
+
+
+ 3
+
+ Release
+
+ ARM
+
+ 0
+
+ General
+ 3
+
+ 33
+ 1
+ 0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ ICCARM
+ 2
+
+ 37
+ 1
+ 0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ AARM
+ 2
+
+ 11
+ 1
+ 0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ OBJCOPY
+ 0
+
+ 1
+ 1
+ 0
+
+
+
+
+
+
+
+
+ CUSTOM
+ 3
+
+
+
+ 1
+ inputOutputBased
+
+
+
+ BUILDACTION
+ 1
+
+
+
+
+
+
+ ILINK
+ 0
+
+ 25
+ 1
+ 0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ IARCHIVE
+ 0
+
+ 0
+ 1
+ 0
+
+
+
+
+
+
+
+ driver
+
+ $PROJ_DIR$\..\..\..\src\driver_w25qxx.c
+
+
+ $PROJ_DIR$\..\driver\src\stm32f767_driver_w25qxx_interface.c
+
+
+
+ example
+
+ $PROJ_DIR$\..\..\..\example\driver_w25qxx_advance.c
+
+
+ $PROJ_DIR$\..\..\..\example\driver_w25qxx_basic.c
+
+
+
+ hal
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_adc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_adc_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_can.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_cec.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_cortex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_crc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_crc_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_cryp.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_cryp_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_dac.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_dac_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_dcmi.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_dcmi_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_dfsdm.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_dma.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_dma2d.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_dma_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_dsi.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_eth.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_flash.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_flash_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_gpio.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_hash.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_hash_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_hcd.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_i2c.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_i2c_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_i2s.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_irda.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_iwdg.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_jpeg.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_lptim.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_ltdc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_ltdc_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_mdios.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_mmc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_nand.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_nor.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_pcd.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_pcd_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_pwr.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_pwr_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_qspi.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_rcc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_rcc_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_rng.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_rtc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_rtc_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_sai.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_sai_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_sd.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_sdram.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_smartcard.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_smartcard_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_smbus.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_spdifrx.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_spi.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_sram.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_tim.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_tim_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_uart.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_usart.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_wwdg.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_ll_adc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_ll_crc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_ll_dac.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_ll_dma.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_ll_dma2d.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_ll_exti.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_ll_fmc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_ll_gpio.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_ll_i2c.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_ll_lptim.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_ll_pwr.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_ll_rcc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_ll_rng.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_ll_rtc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_ll_sdmmc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_ll_spi.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_ll_tim.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_ll_usart.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_ll_usb.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_ll_utils.c
+
+
+
+ interface
+
+ $PROJ_DIR$\..\interface\src\clock.c
+
+
+ $PROJ_DIR$\..\interface\src\delay.c
+
+
+ $PROJ_DIR$\..\interface\src\qspi.c
+
+
+ $PROJ_DIR$\..\interface\src\uart.c
+
+
+
+ startup
+
+ $PROJ_DIR$\..\hal\asm\startup_stm32f767xx_ew.s
+
+
+
+ test
+
+ $PROJ_DIR$\..\..\..\test\driver_w25qxx_read_test.c
+
+
+ $PROJ_DIR$\..\..\..\test\driver_w25qxx_register_test.c
+
+
+
+ usr
+
+ $PROJ_DIR$\..\usr\src\main.c
+
+
+ $PROJ_DIR$\..\usr\src\shell.c
+
+
+ $PROJ_DIR$\..\usr\src\stm32f7xx_hal_msp.c
+
+
+ $PROJ_DIR$\..\usr\src\stm32f7xx_it.c
+
+
+ $PROJ_DIR$\..\usr\src\system_stm32f7xx.c
+
+
+
diff --git a/project/stm32f767/EW/stm32f767.ewt b/project/stm32f767/EW/stm32f767.ewt
new file mode 100644
index 0000000..b331ae6
--- /dev/null
+++ b/project/stm32f767/EW/stm32f767.ewt
@@ -0,0 +1,1745 @@
+
+
+ 3
+
+ Release
+
+ ARM
+
+ 0
+
+ C-STAT
+ 514
+
+ 514
+
+ 0
+
+ 1
+ 600
+ 1
+ 2
+ 0
+ 1
+ 100
+ $PROJ_DIR$\..\output\ew\release\c-stat
+
+
+ 2.2.0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ RuntimeChecking
+ 0
+
+ 2
+ 1
+ 0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ driver
+
+ $PROJ_DIR$\..\..\..\src\driver_w25qxx.c
+
+
+ $PROJ_DIR$\..\driver\src\stm32f767_driver_w25qxx_interface.c
+
+
+
+ example
+
+ $PROJ_DIR$\..\..\..\example\driver_w25qxx_advance.c
+
+
+ $PROJ_DIR$\..\..\..\example\driver_w25qxx_basic.c
+
+
+
+ hal
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_adc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_adc_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_can.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_cec.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_cortex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_crc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_crc_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_cryp.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_cryp_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_dac.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_dac_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_dcmi.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_dcmi_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_dfsdm.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_dma.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_dma2d.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_dma_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_dsi.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_eth.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_flash.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_flash_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_gpio.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_hash.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_hash_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_hcd.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_i2c.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_i2c_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_i2s.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_irda.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_iwdg.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_jpeg.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_lptim.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_ltdc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_ltdc_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_mdios.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_mmc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_nand.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_nor.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_pcd.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_pcd_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_pwr.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_pwr_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_qspi.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_rcc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_rcc_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_rng.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_rtc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_rtc_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_sai.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_sai_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_sd.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_sdram.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_smartcard.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_smartcard_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_smbus.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_spdifrx.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_spi.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_sram.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_tim.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_tim_ex.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_uart.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_usart.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_hal_wwdg.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_ll_adc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_ll_crc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_ll_dac.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_ll_dma.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_ll_dma2d.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_ll_exti.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_ll_fmc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_ll_gpio.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_ll_i2c.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_ll_lptim.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_ll_pwr.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_ll_rcc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_ll_rng.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_ll_rtc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_ll_sdmmc.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_ll_spi.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_ll_tim.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_ll_usart.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_ll_usb.c
+
+
+ $PROJ_DIR$\..\hal\src\stm32f7xx_ll_utils.c
+
+
+
+ interface
+
+ $PROJ_DIR$\..\interface\src\clock.c
+
+
+ $PROJ_DIR$\..\interface\src\delay.c
+
+
+ $PROJ_DIR$\..\interface\src\qspi.c
+
+
+ $PROJ_DIR$\..\interface\src\uart.c
+
+
+
+ startup
+
+ $PROJ_DIR$\..\hal\asm\startup_stm32f767xx_ew.s
+
+
+
+ test
+
+ $PROJ_DIR$\..\..\..\test\driver_w25qxx_read_test.c
+
+
+ $PROJ_DIR$\..\..\..\test\driver_w25qxx_register_test.c
+
+
+
+ usr
+
+ $PROJ_DIR$\..\usr\src\main.c
+
+
+ $PROJ_DIR$\..\usr\src\shell.c
+
+
+ $PROJ_DIR$\..\usr\src\stm32f7xx_hal_msp.c
+
+
+ $PROJ_DIR$\..\usr\src\stm32f7xx_it.c
+
+
+ $PROJ_DIR$\..\usr\src\system_stm32f7xx.c
+
+
+
diff --git a/project/stm32f767/EW/stm32f767.eww b/project/stm32f767/EW/stm32f767.eww
new file mode 100644
index 0000000..abb5bf9
--- /dev/null
+++ b/project/stm32f767/EW/stm32f767.eww
@@ -0,0 +1,7 @@
+
+
+
+ $WS_DIR$\stm32f767.ewp
+
+
+
diff --git a/project/stm32f767/MDK/stm32f767.uvprojx b/project/stm32f767/MDK/stm32f767.uvprojx
index 606eaa5..73e68a8 100644
--- a/project/stm32f767/MDK/stm32f767.uvprojx
+++ b/project/stm32f767/MDK/stm32f767.uvprojx
@@ -48,7 +48,7 @@
0
1
- ..\obj\
+ ..\output\mdk\
w25qxx
1
0
@@ -904,9 +904,9 @@
startup
- startup_stm32f767xx.s
+ startup_stm32f767xx_mdk.s
2
- ..\hal\asm\startup_stm32f767xx.s
+ ..\hal\asm\startup_stm32f767xx_mdk.s
diff --git a/project/stm32f767/hal/asm/startup_stm32f767xx_ew.s b/project/stm32f767/hal/asm/startup_stm32f767xx_ew.s
new file mode 100644
index 0000000..e0d80a1
--- /dev/null
+++ b/project/stm32f767/hal/asm/startup_stm32f767xx_ew.s
@@ -0,0 +1,797 @@
+;/******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
+;* File Name : startup_stm32f767xx.s
+;* Author : MCD Application Team
+;* Description : STM32F767xx devices vector table for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == _iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M7 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;* 3. Neither the name of STMicroelectronics nor the names of its contributors
+;* may be used to endorse or promote products derived from this software
+;* without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
+ DCD CAN1_TX_IRQHandler ; CAN1 TX
+ DCD CAN1_RX0_IRQHandler ; CAN1 RX0
+ DCD CAN1_RX1_IRQHandler ; CAN1 RX1
+ DCD CAN1_SCE_IRQHandler ; CAN1 SCE
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
+ DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
+ DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]s
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDMMC1_IRQHandler ; SDMMC1
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD ETH_IRQHandler ; Ethernet
+ DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
+ DCD CAN2_TX_IRQHandler ; CAN2 TX
+ DCD CAN2_RX0_IRQHandler ; CAN2 RX0
+ DCD CAN2_RX1_IRQHandler ; CAN2 RX1
+ DCD CAN2_SCE_IRQHandler ; CAN2 SCE
+ DCD OTG_FS_IRQHandler ; USB OTG FS
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_IRQHandler ; DCMI
+ DCD 0 ; Reserved
+ DCD RNG_IRQHandler ; Rng
+ DCD FPU_IRQHandler ; FPU
+ DCD UART7_IRQHandler ; UART7
+ DCD UART8_IRQHandler ; UART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD SPI5_IRQHandler ; SPI5
+ DCD SPI6_IRQHandler ; SPI6
+ DCD SAI1_IRQHandler ; SAI1
+ DCD LTDC_IRQHandler ; LTDC
+ DCD LTDC_ER_IRQHandler ; LTDC error
+ DCD DMA2D_IRQHandler ; DMA2D
+ DCD SAI2_IRQHandler ; SAI2
+ DCD QUADSPI_IRQHandler ; QUADSPI
+ DCD LPTIM1_IRQHandler ; LPTIM1
+ DCD CEC_IRQHandler ; HDMI_CEC
+ DCD I2C4_EV_IRQHandler ; I2C4 Event
+ DCD I2C4_ER_IRQHandler ; I2C4 Error
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX
+ DCD 0 ; Reserved
+ DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global Interrupt
+ DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global Interrupt
+ DCD DFSDM1_FLT2_IRQHandler ; DFSDM1 Filter 2 global Interrupt
+ DCD DFSDM1_FLT3_IRQHandler ; DFSDM1 Filter 3 global Interrupt
+ DCD SDMMC2_IRQHandler ; SDMMC2
+ DCD CAN3_TX_IRQHandler ; CAN3 TX
+ DCD CAN3_RX0_IRQHandler ; CAN3 RX0
+ DCD CAN3_RX1_IRQHandler ; CAN3 RX1
+ DCD CAN3_SCE_IRQHandler ; CAN3 SCE
+ DCD JPEG_IRQHandler ; JPEG
+ DCD MDIOS_IRQHandler ; MDIOS
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_IRQHandler
+ B PVD_IRQHandler
+
+ PUBWEAK TAMP_STAMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_IRQHandler
+ B TAMP_STAMP_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Stream0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream0_IRQHandler
+ B DMA1_Stream0_IRQHandler
+
+ PUBWEAK DMA1_Stream1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream1_IRQHandler
+ B DMA1_Stream1_IRQHandler
+
+ PUBWEAK DMA1_Stream2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream2_IRQHandler
+ B DMA1_Stream2_IRQHandler
+
+ PUBWEAK DMA1_Stream3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream3_IRQHandler
+ B DMA1_Stream3_IRQHandler
+
+ PUBWEAK DMA1_Stream4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream4_IRQHandler
+ B DMA1_Stream4_IRQHandler
+
+ PUBWEAK DMA1_Stream5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream5_IRQHandler
+ B DMA1_Stream5_IRQHandler
+
+ PUBWEAK DMA1_Stream6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream6_IRQHandler
+ B DMA1_Stream6_IRQHandler
+
+ PUBWEAK ADC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC_IRQHandler
+ B ADC_IRQHandler
+
+ PUBWEAK CAN1_TX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_TX_IRQHandler
+ B CAN1_TX_IRQHandler
+
+ PUBWEAK CAN1_RX0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_RX0_IRQHandler
+ B CAN1_RX0_IRQHandler
+
+ PUBWEAK CAN1_RX1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_RX1_IRQHandler
+ B CAN1_RX1_IRQHandler
+
+ PUBWEAK CAN1_SCE_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_SCE_IRQHandler
+ B CAN1_SCE_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_TIM9_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_TIM9_IRQHandler
+ B TIM1_BRK_TIM9_IRQHandler
+
+ PUBWEAK TIM1_UP_TIM10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM10_IRQHandler
+ B TIM1_UP_TIM10_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM11_IRQHandler
+ B TIM1_TRG_COM_TIM11_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK OTG_FS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_WKUP_IRQHandler
+ B OTG_FS_WKUP_IRQHandler
+
+ PUBWEAK TIM8_BRK_TIM12_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_TIM12_IRQHandler
+ B TIM8_BRK_TIM12_IRQHandler
+
+ PUBWEAK TIM8_UP_TIM13_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_TIM13_IRQHandler
+ B TIM8_UP_TIM13_IRQHandler
+
+ PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_TIM14_IRQHandler
+ B TIM8_TRG_COM_TIM14_IRQHandler
+
+ PUBWEAK TIM8_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+ B TIM8_CC_IRQHandler
+
+ PUBWEAK DMA1_Stream7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream7_IRQHandler
+ B DMA1_Stream7_IRQHandler
+
+ PUBWEAK FMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+ B FMC_IRQHandler
+
+ PUBWEAK SDMMC1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler
+ B SDMMC1_IRQHandler
+
+ PUBWEAK TIM5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler
+ B TIM5_IRQHandler
+
+ PUBWEAK SPI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+ B SPI3_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK UART5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+ B UART5_IRQHandler
+
+ PUBWEAK TIM6_DAC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+ B TIM6_DAC_IRQHandler
+
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+
+ PUBWEAK DMA2_Stream0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream0_IRQHandler
+ B DMA2_Stream0_IRQHandler
+
+ PUBWEAK DMA2_Stream1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream1_IRQHandler
+ B DMA2_Stream1_IRQHandler
+
+ PUBWEAK DMA2_Stream2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream2_IRQHandler
+ B DMA2_Stream2_IRQHandler
+
+ PUBWEAK DMA2_Stream3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream3_IRQHandler
+ B DMA2_Stream3_IRQHandler
+
+ PUBWEAK DMA2_Stream4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream4_IRQHandler
+ B DMA2_Stream4_IRQHandler
+
+ PUBWEAK ETH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ETH_IRQHandler
+ B ETH_IRQHandler
+
+ PUBWEAK ETH_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ETH_WKUP_IRQHandler
+ B ETH_WKUP_IRQHandler
+
+ PUBWEAK CAN2_TX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN2_TX_IRQHandler
+ B CAN2_TX_IRQHandler
+
+ PUBWEAK CAN2_RX0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN2_RX0_IRQHandler
+ B CAN2_RX0_IRQHandler
+
+ PUBWEAK CAN2_RX1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN2_RX1_IRQHandler
+ B CAN2_RX1_IRQHandler
+
+ PUBWEAK CAN2_SCE_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN2_SCE_IRQHandler
+ B CAN2_SCE_IRQHandler
+
+ PUBWEAK OTG_FS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_IRQHandler
+ B OTG_FS_IRQHandler
+
+ PUBWEAK DMA2_Stream5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream5_IRQHandler
+ B DMA2_Stream5_IRQHandler
+
+ PUBWEAK DMA2_Stream6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream6_IRQHandler
+ B DMA2_Stream6_IRQHandler
+
+ PUBWEAK DMA2_Stream7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream7_IRQHandler
+ B DMA2_Stream7_IRQHandler
+
+ PUBWEAK USART6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART6_IRQHandler
+ B USART6_IRQHandler
+
+ PUBWEAK I2C3_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+ B I2C3_EV_IRQHandler
+
+ PUBWEAK I2C3_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+ B I2C3_ER_IRQHandler
+
+ PUBWEAK OTG_HS_EP1_OUT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_OUT_IRQHandler
+ B OTG_HS_EP1_OUT_IRQHandler
+
+ PUBWEAK OTG_HS_EP1_IN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_IN_IRQHandler
+ B OTG_HS_EP1_IN_IRQHandler
+
+ PUBWEAK OTG_HS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_WKUP_IRQHandler
+ B OTG_HS_WKUP_IRQHandler
+
+ PUBWEAK OTG_HS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_IRQHandler
+ B OTG_HS_IRQHandler
+
+ PUBWEAK DCMI_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DCMI_IRQHandler
+ B DCMI_IRQHandler
+
+ PUBWEAK RNG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+ B RNG_IRQHandler
+
+ PUBWEAK FPU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+ B FPU_IRQHandler
+
+ PUBWEAK UART7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART7_IRQHandler
+ B UART7_IRQHandler
+
+ PUBWEAK UART8_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART8_IRQHandler
+ B UART8_IRQHandler
+
+ PUBWEAK SPI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI4_IRQHandler
+ B SPI4_IRQHandler
+
+ PUBWEAK SPI5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI5_IRQHandler
+ B SPI5_IRQHandler
+
+ PUBWEAK SPI6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI6_IRQHandler
+ B SPI6_IRQHandler
+
+ PUBWEAK SAI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI1_IRQHandler
+ B SAI1_IRQHandler
+
+ PUBWEAK LTDC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_IRQHandler
+ B LTDC_IRQHandler
+
+ PUBWEAK LTDC_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_ER_IRQHandler
+ B LTDC_ER_IRQHandler
+
+ PUBWEAK DMA2D_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2D_IRQHandler
+ B DMA2D_IRQHandler
+
+ PUBWEAK SAI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI2_IRQHandler
+ B SAI2_IRQHandler
+
+ PUBWEAK QUADSPI_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+ B QUADSPI_IRQHandler
+
+ PUBWEAK LPTIM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+ B LPTIM1_IRQHandler
+
+ PUBWEAK CEC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CEC_IRQHandler
+ B CEC_IRQHandler
+
+ PUBWEAK I2C4_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_EV_IRQHandler
+ B I2C4_EV_IRQHandler
+
+ PUBWEAK I2C4_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_ER_IRQHandler
+ B I2C4_ER_IRQHandler
+
+ PUBWEAK SPDIF_RX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPDIF_RX_IRQHandler
+ B SPDIF_RX_IRQHandler
+
+ PUBWEAK DFSDM1_FLT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT0_IRQHandler
+ B DFSDM1_FLT0_IRQHandler
+
+ PUBWEAK DFSDM1_FLT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT1_IRQHandler
+ B DFSDM1_FLT1_IRQHandler
+
+ PUBWEAK DFSDM1_FLT2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT2_IRQHandler
+ B DFSDM1_FLT2_IRQHandler
+
+ PUBWEAK DFSDM1_FLT3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT3_IRQHandler
+ B DFSDM1_FLT3_IRQHandler
+
+ PUBWEAK SDMMC2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC2_IRQHandler
+ B SDMMC2_IRQHandler
+
+ PUBWEAK CAN3_TX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN3_TX_IRQHandler
+ B CAN3_TX_IRQHandler
+
+ PUBWEAK CAN3_RX0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN3_RX0_IRQHandler
+ B CAN3_RX0_IRQHandler
+
+ PUBWEAK CAN3_RX1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN3_RX1_IRQHandler
+ B CAN3_RX1_IRQHandler
+
+ PUBWEAK CAN3_SCE_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN3_SCE_IRQHandler
+ B CAN3_SCE_IRQHandler
+
+ PUBWEAK JPEG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+JPEG_IRQHandler
+ B JPEG_IRQHandler
+
+ PUBWEAK MDIOS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_IRQHandler
+ B MDIOS_IRQHandler
+ END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/project/stm32f767/hal/asm/startup_stm32f767xx.s b/project/stm32f767/hal/asm/startup_stm32f767xx_mdk.s
similarity index 100%
rename from project/stm32f767/hal/asm/startup_stm32f767xx.s
rename to project/stm32f767/hal/asm/startup_stm32f767xx_mdk.s
diff --git a/project/stm32f767/obj/obj_delete.bat b/project/stm32f767/output/mdk/obj_delete.bat
similarity index 93%
rename from project/stm32f767/obj/obj_delete.bat
rename to project/stm32f767/output/mdk/obj_delete.bat
index d90f4c5..e4a2ecd 100644
--- a/project/stm32f767/obj/obj_delete.bat
+++ b/project/stm32f767/output/mdk/obj_delete.bat
@@ -18,8 +18,6 @@ del *.d /s
del *.axf /s
del *.tra /s
del *.dep /s
-del JLinkLog.txt /s
-
del *.iex /s
del *.htm /s
del *.sct /s
diff --git a/project/stm32f767/usr/inc/stm32f746xx.h b/project/stm32f767/usr/inc/stm32f767xx.h
similarity index 93%
rename from project/stm32f767/usr/inc/stm32f746xx.h
rename to project/stm32f767/usr/inc/stm32f767xx.h
index ca9deee..4e7911c 100644
--- a/project/stm32f767/usr/inc/stm32f746xx.h
+++ b/project/stm32f767/usr/inc/stm32f767xx.h
@@ -1,6 +1,6 @@
/**
******************************************************************************
- * @file stm32f746xx.h
+ * @file stm32f767xx.h
* @author MCD Application Team
* @brief CMSIS Cortex-M7 Device Peripheral Access Layer Header File.
*
@@ -43,12 +43,12 @@
* @{
*/
-/** @addtogroup stm32f746xx
+/** @addtogroup stm32f767xx
* @{
*/
-#ifndef __STM32F746xx_H
-#define __STM32F746xx_H
+#ifndef __STM32F767xx_H
+#define __STM32F767xx_H
#ifdef __cplusplus
extern "C" {
@@ -171,6 +171,17 @@ typedef enum
I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */
I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */
SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */
+ DFSDM1_FLT0_IRQn = 99, /*!< DFSDM1 Filter 0 global Interrupt */
+ DFSDM1_FLT1_IRQn = 100, /*!< DFSDM1 Filter 1 global Interrupt */
+ DFSDM1_FLT2_IRQn = 101, /*!< DFSDM1 Filter 2 global Interrupt */
+ DFSDM1_FLT3_IRQn = 102, /*!< DFSDM1 Filter 3 global Interrupt */
+ SDMMC2_IRQn = 103, /*!< SDMMC2 global Interrupt */
+ CAN3_TX_IRQn = 104, /*!< CAN3 TX Interrupt */
+ CAN3_RX0_IRQn = 105, /*!< CAN3 RX0 Interrupt */
+ CAN3_RX1_IRQn = 106, /*!< CAN3 RX1 Interrupt */
+ CAN3_SCE_IRQn = 107, /*!< CAN3 SCE Interrupt */
+ JPEG_IRQn = 108, /*!< JPEG global Interrupt */
+ MDIOS_IRQn = 109 /*!< MDIO Slave global Interrupt */
} IRQn_Type;
/**
@@ -180,7 +191,7 @@ typedef enum
/**
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
*/
-#define __CM7_REV 0x0001U /*!< Cortex-M7 revision r0p1 */
+#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
@@ -350,6 +361,40 @@ typedef struct
__IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
} DAC_TypeDef;
+/**
+ * @brief DFSDM module registers
+ */
+typedef struct
+{
+ __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
+ __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
+ __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
+ __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
+ __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
+ __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
+ __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
+ __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
+ __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
+ __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
+ __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
+ __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
+ __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
+ __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
+ __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
+} DFSDM_Filter_TypeDef;
+
+/**
+ * @brief DFSDM channel configuration registers
+ */
+typedef struct
+{
+ __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
+ __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
+ __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
+ short circuit detector register, Address offset: 0x08 */
+ __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
+ __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
+} DFSDM_Channel_TypeDef;
/**
* @brief Debug MCU
@@ -614,7 +659,8 @@ typedef struct
__IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
__IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
__IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
- uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ uint32_t RESERVED; /*!< Reserved, 0x18 */
+ __IO uint32_t CBR; /*!< SYSCFG Class B register, Address offset: 0x1C */
__IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
} SYSCFG_TypeDef;
@@ -947,6 +993,8 @@ typedef struct
__IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
__IO uint32_t CCR5; /*!< TIM capture/compare mode register5, Address offset: 0x58 */
__IO uint32_t CCR6; /*!< TIM capture/compare mode register6, Address offset: 0x5C */
+ __IO uint32_t AF1; /*!< TIM Alternate function option register 1, Address offset: 0x60 */
+ __IO uint32_t AF2; /*!< TIM Alternate function option register 2, Address offset: 0x64 */
} TIM_TypeDef;
@@ -1136,24 +1184,139 @@ typedef struct
* @}
*/
+/**
+ * @brief JPEG Codec
+ */
+typedef struct
+{
+ __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */
+ __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */
+ __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */
+ __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */
+ __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */
+ __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */
+ __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */
+ __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */
+ uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */
+ __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */
+ __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */
+ __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */
+ uint32_t Reserved3c; /* Reserved Address offset: 3Ch */
+ __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */
+ __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */
+ uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */
+ __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */
+ __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */
+ __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */
+ __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */
+ __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */
+ __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */
+ __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */
+ __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */
+ uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */
+ __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encoder, AC Huffman table 0, Address offset: 500h-65Ch */
+ __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encoder, AC Huffman table 1, Address offset: 660h-7BCh */
+ __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encoder, DC Huffman table 0, Address offset: 7C0h-7DCh */
+ __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encoder, DC Huffman table 1, Address offset: 7E0h-7FCh */
+
+} JPEG_TypeDef;
+
+/**
+ * @brief MDIOS
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 00h */
+ __IO uint32_t WRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 04h */
+ __IO uint32_t CWRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 08h */
+ __IO uint32_t RDFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 0Ch */
+ __IO uint32_t CRDFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 10h */
+ __IO uint32_t SR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 14h */
+ __IO uint32_t CLRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 18h */
+ uint32_t RESERVED0[57]; /* Reserved Address offset: 1Ch */
+ __IO uint32_t DINR0; /*!< MDIOS Input Data Register (MDIOS_DINR0), Address offset: 100h */
+ __IO uint32_t DINR1; /*!< MDIOS Input Data Register (MDIOS_DINR1), Address offset: 104h */
+ __IO uint32_t DINR2; /*!< MDIOS Input Data Register (MDIOS_DINR2), Address offset: 108h */
+ __IO uint32_t DINR3; /*!< MDIOS Input Data Register (MDIOS_DINR3), Address offset: 10Ch */
+ __IO uint32_t DINR4; /*!< MDIOS Input Data Register (MDIOS_DINR4), Address offset: 110h */
+ __IO uint32_t DINR5; /*!< MDIOS Input Data Register (MDIOS_DINR5), Address offset: 114h */
+ __IO uint32_t DINR6; /*!< MDIOS Input Data Register (MDIOS_DINR6), Address offset: 118h */
+ __IO uint32_t DINR7; /*!< MDIOS Input Data Register (MDIOS_DINR7), Address offset: 11Ch */
+ __IO uint32_t DINR8; /*!< MDIOS Input Data Register (MDIOS_DINR8), Address offset: 120h */
+ __IO uint32_t DINR9; /*!< MDIOS Input Data Register (MDIOS_DINR9), Address offset: 124h */
+ __IO uint32_t DINR10; /*!< MDIOS Input Data Register (MDIOS_DINR10), Address offset: 128h */
+ __IO uint32_t DINR11; /*!< MDIOS Input Data Register (MDIOS_DINR11), Address offset: 12Ch */
+ __IO uint32_t DINR12; /*!< MDIOS Input Data Register (MDIOS_DINR12), Address offset: 130h */
+ __IO uint32_t DINR13; /*!< MDIOS Input Data Register (MDIOS_DINR13), Address offset: 134h */
+ __IO uint32_t DINR14; /*!< MDIOS Input Data Register (MDIOS_DINR14), Address offset: 138h */
+ __IO uint32_t DINR15; /*!< MDIOS Input Data Register (MDIOS_DINR15), Address offset: 13Ch */
+ __IO uint32_t DINR16; /*!< MDIOS Input Data Register (MDIOS_DINR16), Address offset: 140h */
+ __IO uint32_t DINR17; /*!< MDIOS Input Data Register (MDIOS_DINR17), Address offset: 144h */
+ __IO uint32_t DINR18; /*!< MDIOS Input Data Register (MDIOS_DINR18), Address offset: 148h */
+ __IO uint32_t DINR19; /*!< MDIOS Input Data Register (MDIOS_DINR19), Address offset: 14Ch */
+ __IO uint32_t DINR20; /*!< MDIOS Input Data Register (MDIOS_DINR20), Address offset: 150h */
+ __IO uint32_t DINR21; /*!< MDIOS Input Data Register (MDIOS_DINR21), Address offset: 154h */
+ __IO uint32_t DINR22; /*!< MDIOS Input Data Register (MDIOS_DINR22), Address offset: 158h */
+ __IO uint32_t DINR23; /*!< MDIOS Input Data Register (MDIOS_DINR23), Address offset: 15Ch */
+ __IO uint32_t DINR24; /*!< MDIOS Input Data Register (MDIOS_DINR24), Address offset: 160h */
+ __IO uint32_t DINR25; /*!< MDIOS Input Data Register (MDIOS_DINR25), Address offset: 164h */
+ __IO uint32_t DINR26; /*!< MDIOS Input Data Register (MDIOS_DINR26), Address offset: 168h */
+ __IO uint32_t DINR27; /*!< MDIOS Input Data Register (MDIOS_DINR27), Address offset: 16Ch */
+ __IO uint32_t DINR28; /*!< MDIOS Input Data Register (MDIOS_DINR28), Address offset: 170h */
+ __IO uint32_t DINR29; /*!< MDIOS Input Data Register (MDIOS_DINR29), Address offset: 174h */
+ __IO uint32_t DINR30; /*!< MDIOS Input Data Register (MDIOS_DINR30), Address offset: 178h */
+ __IO uint32_t DINR31; /*!< MDIOS Input Data Register (MDIOS_DINR31), Address offset: 17Ch */
+ __IO uint32_t DOUTR0; /*!< MDIOS Output Data Register (MDIOS_DOUTR0), Address offset: 180h */
+ __IO uint32_t DOUTR1; /*!< MDIOS Output Data Register (MDIOS_DOUTR1), Address offset: 184h */
+ __IO uint32_t DOUTR2; /*!< MDIOS Output Data Register (MDIOS_DOUTR2), Address offset: 188h */
+ __IO uint32_t DOUTR3; /*!< MDIOS Output Data Register (MDIOS_DOUTR3), Address offset: 18Ch */
+ __IO uint32_t DOUTR4; /*!< MDIOS Output Data Register (MDIOS_DOUTR4), Address offset: 190h */
+ __IO uint32_t DOUTR5; /*!< MDIOS Output Data Register (MDIOS_DOUTR5), Address offset: 194h */
+ __IO uint32_t DOUTR6; /*!< MDIOS Output Data Register (MDIOS_DOUTR6), Address offset: 198h */
+ __IO uint32_t DOUTR7; /*!< MDIOS Output Data Register (MDIOS_DOUTR7), Address offset: 19Ch */
+ __IO uint32_t DOUTR8; /*!< MDIOS Output Data Register (MDIOS_DOUTR8), Address offset: 1A0h */
+ __IO uint32_t DOUTR9; /*!< MDIOS Output Data Register (MDIOS_DOUTR9), Address offset: 1A4h */
+ __IO uint32_t DOUTR10; /*!< MDIOS Output Data Register (MDIOS_DOUTR10), Address offset: 1A8h */
+ __IO uint32_t DOUTR11; /*!< MDIOS Output Data Register (MDIOS_DOUTR11), Address offset: 1ACh */
+ __IO uint32_t DOUTR12; /*!< MDIOS Output Data Register (MDIOS_DOUTR12), Address offset: 1B0h */
+ __IO uint32_t DOUTR13; /*!< MDIOS Output Data Register (MDIOS_DOUTR13), Address offset: 1B4h */
+ __IO uint32_t DOUTR14; /*!< MDIOS Output Data Register (MDIOS_DOUTR14), Address offset: 1B8h */
+ __IO uint32_t DOUTR15; /*!< MDIOS Output Data Register (MDIOS_DOUTR15), Address offset: 1BCh */
+ __IO uint32_t DOUTR16; /*!< MDIOS Output Data Register (MDIOS_DOUTR16), Address offset: 1C0h */
+ __IO uint32_t DOUTR17; /*!< MDIOS Output Data Register (MDIOS_DOUTR17), Address offset: 1C4h */
+ __IO uint32_t DOUTR18; /*!< MDIOS Output Data Register (MDIOS_DOUTR18), Address offset: 1C8h */
+ __IO uint32_t DOUTR19; /*!< MDIOS Output Data Register (MDIOS_DOUTR19), Address offset: 1CCh */
+ __IO uint32_t DOUTR20; /*!< MDIOS Output Data Register (MDIOS_DOUTR20), Address offset: 1D0h */
+ __IO uint32_t DOUTR21; /*!< MDIOS Output Data Register (MDIOS_DOUTR21), Address offset: 1D4h */
+ __IO uint32_t DOUTR22; /*!< MDIOS Output Data Register (MDIOS_DOUTR22), Address offset: 1D8h */
+ __IO uint32_t DOUTR23; /*!< MDIOS Output Data Register (MDIOS_DOUTR23), Address offset: 1DCh */
+ __IO uint32_t DOUTR24; /*!< MDIOS Output Data Register (MDIOS_DOUTR24), Address offset: 1E0h */
+ __IO uint32_t DOUTR25; /*!< MDIOS Output Data Register (MDIOS_DOUTR25), Address offset: 1E4h */
+ __IO uint32_t DOUTR26; /*!< MDIOS Output Data Register (MDIOS_DOUTR26), Address offset: 1E8h */
+ __IO uint32_t DOUTR27; /*!< MDIOS Output Data Register (MDIOS_DOUTR27), Address offset: 1ECh */
+ __IO uint32_t DOUTR28; /*!< MDIOS Output Data Register (MDIOS_DOUTR28), Address offset: 1F0h */
+ __IO uint32_t DOUTR29; /*!< MDIOS Output Data Register (MDIOS_DOUTR29), Address offset: 1F4h */
+ __IO uint32_t DOUTR30; /*!< MDIOS Output Data Register (MDIOS_DOUTR30), Address offset: 1F8h */
+ __IO uint32_t DOUTR31; /*!< MDIOS Output Data Register (MDIOS_DOUTR31), Address offset: 1FCh */
+} MDIOS_TypeDef;
/** @addtogroup Peripheral_memory_map
* @{
*/
#define RAMITCM_BASE 0x00000000U /*!< Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM */
-#define FLASHITCM_BASE 0x00200000U /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over ITCM */
-#define FLASHAXI_BASE 0x08000000U /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI */
-#define RAMDTCM_BASE 0x20000000U /*!< Base address of : 64KB system data RAM accessible over DTCM */
+#define FLASHITCM_BASE 0x00200000U /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over ITCM */
+#define FLASHAXI_BASE 0x08000000U /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI */
+#define RAMDTCM_BASE 0x20000000U /*!< Base address of : 128KB system data RAM accessible over DTCM */
#define PERIPH_BASE 0x40000000U /*!< Base address of : AHB/ABP Peripherals */
#define BKPSRAM_BASE 0x40024000U /*!< Base address of : Backup SRAM(4 KB) */
#define QSPI_BASE 0x90000000U /*!< Base address of : QSPI memories accessible over AXI */
#define FMC_R_BASE 0xA0000000U /*!< Base address of : FMC Control registers */
#define QSPI_R_BASE 0xA0001000U /*!< Base address of : QSPI Control registers */
-#define SRAM1_BASE 0x20010000U /*!< Base address of : 240KB RAM1 accessible over AXI/AHB */
-#define SRAM2_BASE 0x2004C000U /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */
-#define FLASH_END 0x080FFFFFU /*!< FLASH end address */
+#define SRAM1_BASE 0x20020000U /*!< Base address of : 368KB RAM1 accessible over AXI/AHB */
+#define SRAM2_BASE 0x2007C000U /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */
+#define FLASH_END 0x081FFFFFU /*!< FLASH end address */
#define FLASH_OTP_BASE 0x1FF0F000U /*!< Base address of : (up to 1024 Bytes) embedded FLASH OTP Area */
#define FLASH_OTP_END 0x1FF0F41FU /*!< End address of : (up to 1024 Bytes) embedded FLASH OTP Area */
@@ -1180,6 +1343,7 @@ typedef struct
#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
+#define CAN3_BASE (APB1PERIPH_BASE + 0x3400U)
#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
#define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000U)
@@ -1204,6 +1368,7 @@ typedef struct
#define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
+#define SDMMC2_BASE (APB2PERIPH_BASE + 0x1C00U)
#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
#define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
#define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
@@ -1227,6 +1392,20 @@ typedef struct
#define LTDC_BASE (APB2PERIPH_BASE + 0x6800U)
#define LTDC_Layer1_BASE (LTDC_BASE + 0x84U)
#define LTDC_Layer2_BASE (LTDC_BASE + 0x104U)
+#define DFSDM1_BASE (APB2PERIPH_BASE + 0x7400U)
+#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00U)
+#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20U)
+#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40U)
+#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60U)
+#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80U)
+#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0U)
+#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0U)
+#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0U)
+#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100U)
+#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180U)
+#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200U)
+#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280U)
+#define MDIOS_BASE (APB2PERIPH_BASE + 0x7800U)
/*!< AHB1 peripherals */
#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
@@ -1274,6 +1453,7 @@ typedef struct
#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U)
/*!< AHB2 peripherals */
#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
+#define JPEG_BASE (AHB2PERIPH_BASE + 0x51000U)
#define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
/*!< FMC Bankx registers base address */
#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
@@ -1412,6 +1592,22 @@ typedef struct
#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
+#define CAN3 ((CAN_TypeDef *) CAN3_BASE)
+#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)
+#define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)
+#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
+#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
+#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
+#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
+#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
+#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
+#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
+#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
+#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
+#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
+#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
+#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
+#define JPEG ((JPEG_TypeDef *) JPEG_BASE)
/**
* @}
@@ -5831,6 +6027,309 @@ typedef struct
#define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!© COPYRIGHT(c) 2016 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f7xx
+ * @{
+ */
+
+#ifndef __STM32F7xx_H
+#define __STM32F7xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/**
+ * @brief STM32 Family
+ */
+#if !defined (STM32F7)
+#define STM32F7
+#endif /* STM32F7 */
+
+/* Uncomment the line below according to the target STM32 device used in your
+ application
+ */
+#if !defined (STM32F756xx) && !defined (STM32F746xx) && !defined (STM32F745xx) && !defined (STM32F767xx) && \
+ !defined (STM32F769xx) && !defined (STM32F777xx) && !defined (STM32F779xx) && !defined (STM32F722xx) && \
+ !defined (STM32F723xx) && !defined (STM32F732xx) && !defined (STM32F733xx)
+ /* #define STM32F756xx */ /*!< STM32F756VG, STM32F756ZG, STM32F756ZG, STM32F756IG, STM32F756BG,
+ STM32F756NG Devices */
+ /* #define STM32F746xx */ /*!< STM32F746VE, STM32F746VG, STM32F746ZE, STM32F746ZG, STM32F746IE, STM32F746IG,
+ STM32F746BE, STM32F746BG, STM32F746NE, STM32F746NG Devices */
+ /* #define STM32F745xx */ /*!< STM32F745VE, STM32F745VG, STM32F745ZG, STM32F745ZE, STM32F745IE, STM32F745IG Devices */
+ /* #define STM32F765xx */ /*!< STM32F765BI, STM32F765BG, STM32F765NI, STM32F765NG, STM32F765II, STM32F765IG,
+ STM32F765ZI, STM32F765ZG, STM32F765VI, STM32F765VG Devices */
+ /* #define STM32F767xx */ /*!< STM32F767BG, STM32F767BI, STM32F767IG, STM32F767II, STM32F767NG, STM32F767NI,
+ STM32F767VG, STM32F767VI, STM32F767ZG, STM32F767ZI Devices */
+ /* #define STM32F769xx */ /*!< STM32F769AG, STM32F769AI, STM32F769BG, STM32F769BI, STM32F769IG, STM32F769II,
+ STM32F769NG, STM32F769NI, STM32F768AI Devices */
+ /* #define STM32F777xx */ /*!< STM32F777VI, STM32F777ZI, STM32F777II, STM32F777BI, STM32F777NI Devices */
+ /* #define STM32F779xx */ /*!< STM32F779II, STM32F779BI, STM32F779NI, STM32F779AI, STM32F778AI Devices */
+ /* #define STM32F722xx */ /*!< STM32F722IE, STM32F722ZE, STM32F722VE, STM32F722RE, STM32F722IC, STM32F722ZC,
+ STM32F722VC, STM32F722RC Devices */
+ /* #define STM32F723xx */ /*!< STM32F723IE, STM32F723ZE, STM32F723VE, STM32F723IC, STM32F723ZC, STM32F723VC Devices */
+ /* #define STM32F732xx */ /*!< STM32F732IE, STM32F732ZE, STM32F732VE, STM32F732RE Devices */
+ /* #define STM32F733xx */ /*!< STM32F733IE, STM32F733ZE, STM32F733VE Devices */
+#endif
+
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+ */
+
+#if !defined (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+ /*#define USE_HAL_DRIVER */
+#endif /* USE_HAL_DRIVER */
+
+/**
+ * @brief CMSIS Device version number V1.2.2
+ */
+#define __STM32F7_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
+#define __STM32F7_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
+#define __STM32F7_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
+#define __STM32F7_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __STM32F7_CMSIS_VERSION ((__STM32F7_CMSIS_VERSION_MAIN << 24)\
+ |(__STM32F7_CMSIS_VERSION_SUB1 << 16)\
+ |(__STM32F7_CMSIS_VERSION_SUB2 << 8 )\
+ |(__STM32F7_CMSIS_VERSION))
+/**
+ * @}
+ */
+
+/** @addtogroup Device_Included
+ * @{
+ */
+#if defined(STM32F722xx)
+ #include "stm32f722xx.h"
+#elif defined(STM32F723xx)
+ #include "stm32f723xx.h"
+#elif defined(STM32F732xx)
+ #include "stm32f732xx.h"
+#elif defined(STM32F733xx)
+ #include "stm32f733xx.h"
+#elif defined(STM32F756xx)
+ #include "stm32f756xx.h"
+#elif defined(STM32F746xx)
+ #include "stm32f746xx.h"
+#elif defined(STM32F745xx)
+ #include "stm32f745xx.h"
+#elif defined(STM32F765xx)
+ #include "stm32f765xx.h"
+#elif defined(STM32F767xx)
+ #include "stm32f767xx.h"
+#elif defined(STM32F769xx)
+ #include "stm32f769xx.h"
+#elif defined(STM32F777xx)
+ #include "stm32f777xx.h"
+#elif defined(STM32F779xx)
+ #include "stm32f779xx.h"
+#else
+ #error "Please select first the target STM32F7xx device used in your application (in stm32f7xx.h file)"
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_types
+ * @{
+ */
+typedef enum
+{
+ RESET = 0U,
+ SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+ DISABLE = 0U,
+ ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+ ERROR = 0U,
+ SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
+
+/**
+ * @}
+ */
+
+#ifdef USE_HAL_DRIVER
+ #include "stm32f7xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F7xx_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/