forked from torvalds/linux
-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathmax98090.c
2703 lines (2262 loc) · 84.6 KB
/
max98090.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
// SPDX-License-Identifier: GPL-2.0-only
/*
* max98090.c -- MAX98090 ALSA SoC Audio driver
*
* Copyright 2011-2012 Maxim Integrated Products
*/
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/acpi.h>
#include <linux/clk.h>
#include <sound/jack.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include <sound/max98090.h>
#include "max98090.h"
/* Allows for sparsely populated register maps */
static const struct reg_default max98090_reg[] = {
{ 0x00, 0x00 }, /* 00 Software Reset */
{ 0x03, 0x04 }, /* 03 Interrupt Masks */
{ 0x04, 0x00 }, /* 04 System Clock Quick */
{ 0x05, 0x00 }, /* 05 Sample Rate Quick */
{ 0x06, 0x00 }, /* 06 DAI Interface Quick */
{ 0x07, 0x00 }, /* 07 DAC Path Quick */
{ 0x08, 0x00 }, /* 08 Mic/Direct to ADC Quick */
{ 0x09, 0x00 }, /* 09 Line to ADC Quick */
{ 0x0A, 0x00 }, /* 0A Analog Mic Loop Quick */
{ 0x0B, 0x00 }, /* 0B Analog Line Loop Quick */
{ 0x0C, 0x00 }, /* 0C Reserved */
{ 0x0D, 0x00 }, /* 0D Input Config */
{ 0x0E, 0x1B }, /* 0E Line Input Level */
{ 0x0F, 0x00 }, /* 0F Line Config */
{ 0x10, 0x14 }, /* 10 Mic1 Input Level */
{ 0x11, 0x14 }, /* 11 Mic2 Input Level */
{ 0x12, 0x00 }, /* 12 Mic Bias Voltage */
{ 0x13, 0x00 }, /* 13 Digital Mic Config */
{ 0x14, 0x00 }, /* 14 Digital Mic Mode */
{ 0x15, 0x00 }, /* 15 Left ADC Mixer */
{ 0x16, 0x00 }, /* 16 Right ADC Mixer */
{ 0x17, 0x03 }, /* 17 Left ADC Level */
{ 0x18, 0x03 }, /* 18 Right ADC Level */
{ 0x19, 0x00 }, /* 19 ADC Biquad Level */
{ 0x1A, 0x00 }, /* 1A ADC Sidetone */
{ 0x1B, 0x00 }, /* 1B System Clock */
{ 0x1C, 0x00 }, /* 1C Clock Mode */
{ 0x1D, 0x00 }, /* 1D Any Clock 1 */
{ 0x1E, 0x00 }, /* 1E Any Clock 2 */
{ 0x1F, 0x00 }, /* 1F Any Clock 3 */
{ 0x20, 0x00 }, /* 20 Any Clock 4 */
{ 0x21, 0x00 }, /* 21 Master Mode */
{ 0x22, 0x00 }, /* 22 Interface Format */
{ 0x23, 0x00 }, /* 23 TDM Format 1*/
{ 0x24, 0x00 }, /* 24 TDM Format 2*/
{ 0x25, 0x00 }, /* 25 I/O Configuration */
{ 0x26, 0x80 }, /* 26 Filter Config */
{ 0x27, 0x00 }, /* 27 DAI Playback Level */
{ 0x28, 0x00 }, /* 28 EQ Playback Level */
{ 0x29, 0x00 }, /* 29 Left HP Mixer */
{ 0x2A, 0x00 }, /* 2A Right HP Mixer */
{ 0x2B, 0x00 }, /* 2B HP Control */
{ 0x2C, 0x1A }, /* 2C Left HP Volume */
{ 0x2D, 0x1A }, /* 2D Right HP Volume */
{ 0x2E, 0x00 }, /* 2E Left Spk Mixer */
{ 0x2F, 0x00 }, /* 2F Right Spk Mixer */
{ 0x30, 0x00 }, /* 30 Spk Control */
{ 0x31, 0x2C }, /* 31 Left Spk Volume */
{ 0x32, 0x2C }, /* 32 Right Spk Volume */
{ 0x33, 0x00 }, /* 33 ALC Timing */
{ 0x34, 0x00 }, /* 34 ALC Compressor */
{ 0x35, 0x00 }, /* 35 ALC Expander */
{ 0x36, 0x00 }, /* 36 ALC Gain */
{ 0x37, 0x00 }, /* 37 Rcv/Line OutL Mixer */
{ 0x38, 0x00 }, /* 38 Rcv/Line OutL Control */
{ 0x39, 0x15 }, /* 39 Rcv/Line OutL Volume */
{ 0x3A, 0x00 }, /* 3A Line OutR Mixer */
{ 0x3B, 0x00 }, /* 3B Line OutR Control */
{ 0x3C, 0x15 }, /* 3C Line OutR Volume */
{ 0x3D, 0x00 }, /* 3D Jack Detect */
{ 0x3E, 0x00 }, /* 3E Input Enable */
{ 0x3F, 0x00 }, /* 3F Output Enable */
{ 0x40, 0x00 }, /* 40 Level Control */
{ 0x41, 0x00 }, /* 41 DSP Filter Enable */
{ 0x42, 0x00 }, /* 42 Bias Control */
{ 0x43, 0x00 }, /* 43 DAC Control */
{ 0x44, 0x06 }, /* 44 ADC Control */
{ 0x45, 0x00 }, /* 45 Device Shutdown */
{ 0x46, 0x00 }, /* 46 Equalizer Band 1 Coefficient B0 */
{ 0x47, 0x00 }, /* 47 Equalizer Band 1 Coefficient B0 */
{ 0x48, 0x00 }, /* 48 Equalizer Band 1 Coefficient B0 */
{ 0x49, 0x00 }, /* 49 Equalizer Band 1 Coefficient B1 */
{ 0x4A, 0x00 }, /* 4A Equalizer Band 1 Coefficient B1 */
{ 0x4B, 0x00 }, /* 4B Equalizer Band 1 Coefficient B1 */
{ 0x4C, 0x00 }, /* 4C Equalizer Band 1 Coefficient B2 */
{ 0x4D, 0x00 }, /* 4D Equalizer Band 1 Coefficient B2 */
{ 0x4E, 0x00 }, /* 4E Equalizer Band 1 Coefficient B2 */
{ 0x4F, 0x00 }, /* 4F Equalizer Band 1 Coefficient A1 */
{ 0x50, 0x00 }, /* 50 Equalizer Band 1 Coefficient A1 */
{ 0x51, 0x00 }, /* 51 Equalizer Band 1 Coefficient A1 */
{ 0x52, 0x00 }, /* 52 Equalizer Band 1 Coefficient A2 */
{ 0x53, 0x00 }, /* 53 Equalizer Band 1 Coefficient A2 */
{ 0x54, 0x00 }, /* 54 Equalizer Band 1 Coefficient A2 */
{ 0x55, 0x00 }, /* 55 Equalizer Band 2 Coefficient B0 */
{ 0x56, 0x00 }, /* 56 Equalizer Band 2 Coefficient B0 */
{ 0x57, 0x00 }, /* 57 Equalizer Band 2 Coefficient B0 */
{ 0x58, 0x00 }, /* 58 Equalizer Band 2 Coefficient B1 */
{ 0x59, 0x00 }, /* 59 Equalizer Band 2 Coefficient B1 */
{ 0x5A, 0x00 }, /* 5A Equalizer Band 2 Coefficient B1 */
{ 0x5B, 0x00 }, /* 5B Equalizer Band 2 Coefficient B2 */
{ 0x5C, 0x00 }, /* 5C Equalizer Band 2 Coefficient B2 */
{ 0x5D, 0x00 }, /* 5D Equalizer Band 2 Coefficient B2 */
{ 0x5E, 0x00 }, /* 5E Equalizer Band 2 Coefficient A1 */
{ 0x5F, 0x00 }, /* 5F Equalizer Band 2 Coefficient A1 */
{ 0x60, 0x00 }, /* 60 Equalizer Band 2 Coefficient A1 */
{ 0x61, 0x00 }, /* 61 Equalizer Band 2 Coefficient A2 */
{ 0x62, 0x00 }, /* 62 Equalizer Band 2 Coefficient A2 */
{ 0x63, 0x00 }, /* 63 Equalizer Band 2 Coefficient A2 */
{ 0x64, 0x00 }, /* 64 Equalizer Band 3 Coefficient B0 */
{ 0x65, 0x00 }, /* 65 Equalizer Band 3 Coefficient B0 */
{ 0x66, 0x00 }, /* 66 Equalizer Band 3 Coefficient B0 */
{ 0x67, 0x00 }, /* 67 Equalizer Band 3 Coefficient B1 */
{ 0x68, 0x00 }, /* 68 Equalizer Band 3 Coefficient B1 */
{ 0x69, 0x00 }, /* 69 Equalizer Band 3 Coefficient B1 */
{ 0x6A, 0x00 }, /* 6A Equalizer Band 3 Coefficient B2 */
{ 0x6B, 0x00 }, /* 6B Equalizer Band 3 Coefficient B2 */
{ 0x6C, 0x00 }, /* 6C Equalizer Band 3 Coefficient B2 */
{ 0x6D, 0x00 }, /* 6D Equalizer Band 3 Coefficient A1 */
{ 0x6E, 0x00 }, /* 6E Equalizer Band 3 Coefficient A1 */
{ 0x6F, 0x00 }, /* 6F Equalizer Band 3 Coefficient A1 */
{ 0x70, 0x00 }, /* 70 Equalizer Band 3 Coefficient A2 */
{ 0x71, 0x00 }, /* 71 Equalizer Band 3 Coefficient A2 */
{ 0x72, 0x00 }, /* 72 Equalizer Band 3 Coefficient A2 */
{ 0x73, 0x00 }, /* 73 Equalizer Band 4 Coefficient B0 */
{ 0x74, 0x00 }, /* 74 Equalizer Band 4 Coefficient B0 */
{ 0x75, 0x00 }, /* 75 Equalizer Band 4 Coefficient B0 */
{ 0x76, 0x00 }, /* 76 Equalizer Band 4 Coefficient B1 */
{ 0x77, 0x00 }, /* 77 Equalizer Band 4 Coefficient B1 */
{ 0x78, 0x00 }, /* 78 Equalizer Band 4 Coefficient B1 */
{ 0x79, 0x00 }, /* 79 Equalizer Band 4 Coefficient B2 */
{ 0x7A, 0x00 }, /* 7A Equalizer Band 4 Coefficient B2 */
{ 0x7B, 0x00 }, /* 7B Equalizer Band 4 Coefficient B2 */
{ 0x7C, 0x00 }, /* 7C Equalizer Band 4 Coefficient A1 */
{ 0x7D, 0x00 }, /* 7D Equalizer Band 4 Coefficient A1 */
{ 0x7E, 0x00 }, /* 7E Equalizer Band 4 Coefficient A1 */
{ 0x7F, 0x00 }, /* 7F Equalizer Band 4 Coefficient A2 */
{ 0x80, 0x00 }, /* 80 Equalizer Band 4 Coefficient A2 */
{ 0x81, 0x00 }, /* 81 Equalizer Band 4 Coefficient A2 */
{ 0x82, 0x00 }, /* 82 Equalizer Band 5 Coefficient B0 */
{ 0x83, 0x00 }, /* 83 Equalizer Band 5 Coefficient B0 */
{ 0x84, 0x00 }, /* 84 Equalizer Band 5 Coefficient B0 */
{ 0x85, 0x00 }, /* 85 Equalizer Band 5 Coefficient B1 */
{ 0x86, 0x00 }, /* 86 Equalizer Band 5 Coefficient B1 */
{ 0x87, 0x00 }, /* 87 Equalizer Band 5 Coefficient B1 */
{ 0x88, 0x00 }, /* 88 Equalizer Band 5 Coefficient B2 */
{ 0x89, 0x00 }, /* 89 Equalizer Band 5 Coefficient B2 */
{ 0x8A, 0x00 }, /* 8A Equalizer Band 5 Coefficient B2 */
{ 0x8B, 0x00 }, /* 8B Equalizer Band 5 Coefficient A1 */
{ 0x8C, 0x00 }, /* 8C Equalizer Band 5 Coefficient A1 */
{ 0x8D, 0x00 }, /* 8D Equalizer Band 5 Coefficient A1 */
{ 0x8E, 0x00 }, /* 8E Equalizer Band 5 Coefficient A2 */
{ 0x8F, 0x00 }, /* 8F Equalizer Band 5 Coefficient A2 */
{ 0x90, 0x00 }, /* 90 Equalizer Band 5 Coefficient A2 */
{ 0x91, 0x00 }, /* 91 Equalizer Band 6 Coefficient B0 */
{ 0x92, 0x00 }, /* 92 Equalizer Band 6 Coefficient B0 */
{ 0x93, 0x00 }, /* 93 Equalizer Band 6 Coefficient B0 */
{ 0x94, 0x00 }, /* 94 Equalizer Band 6 Coefficient B1 */
{ 0x95, 0x00 }, /* 95 Equalizer Band 6 Coefficient B1 */
{ 0x96, 0x00 }, /* 96 Equalizer Band 6 Coefficient B1 */
{ 0x97, 0x00 }, /* 97 Equalizer Band 6 Coefficient B2 */
{ 0x98, 0x00 }, /* 98 Equalizer Band 6 Coefficient B2 */
{ 0x99, 0x00 }, /* 99 Equalizer Band 6 Coefficient B2 */
{ 0x9A, 0x00 }, /* 9A Equalizer Band 6 Coefficient A1 */
{ 0x9B, 0x00 }, /* 9B Equalizer Band 6 Coefficient A1 */
{ 0x9C, 0x00 }, /* 9C Equalizer Band 6 Coefficient A1 */
{ 0x9D, 0x00 }, /* 9D Equalizer Band 6 Coefficient A2 */
{ 0x9E, 0x00 }, /* 9E Equalizer Band 6 Coefficient A2 */
{ 0x9F, 0x00 }, /* 9F Equalizer Band 6 Coefficient A2 */
{ 0xA0, 0x00 }, /* A0 Equalizer Band 7 Coefficient B0 */
{ 0xA1, 0x00 }, /* A1 Equalizer Band 7 Coefficient B0 */
{ 0xA2, 0x00 }, /* A2 Equalizer Band 7 Coefficient B0 */
{ 0xA3, 0x00 }, /* A3 Equalizer Band 7 Coefficient B1 */
{ 0xA4, 0x00 }, /* A4 Equalizer Band 7 Coefficient B1 */
{ 0xA5, 0x00 }, /* A5 Equalizer Band 7 Coefficient B1 */
{ 0xA6, 0x00 }, /* A6 Equalizer Band 7 Coefficient B2 */
{ 0xA7, 0x00 }, /* A7 Equalizer Band 7 Coefficient B2 */
{ 0xA8, 0x00 }, /* A8 Equalizer Band 7 Coefficient B2 */
{ 0xA9, 0x00 }, /* A9 Equalizer Band 7 Coefficient A1 */
{ 0xAA, 0x00 }, /* AA Equalizer Band 7 Coefficient A1 */
{ 0xAB, 0x00 }, /* AB Equalizer Band 7 Coefficient A1 */
{ 0xAC, 0x00 }, /* AC Equalizer Band 7 Coefficient A2 */
{ 0xAD, 0x00 }, /* AD Equalizer Band 7 Coefficient A2 */
{ 0xAE, 0x00 }, /* AE Equalizer Band 7 Coefficient A2 */
{ 0xAF, 0x00 }, /* AF ADC Biquad Coefficient B0 */
{ 0xB0, 0x00 }, /* B0 ADC Biquad Coefficient B0 */
{ 0xB1, 0x00 }, /* B1 ADC Biquad Coefficient B0 */
{ 0xB2, 0x00 }, /* B2 ADC Biquad Coefficient B1 */
{ 0xB3, 0x00 }, /* B3 ADC Biquad Coefficient B1 */
{ 0xB4, 0x00 }, /* B4 ADC Biquad Coefficient B1 */
{ 0xB5, 0x00 }, /* B5 ADC Biquad Coefficient B2 */
{ 0xB6, 0x00 }, /* B6 ADC Biquad Coefficient B2 */
{ 0xB7, 0x00 }, /* B7 ADC Biquad Coefficient B2 */
{ 0xB8, 0x00 }, /* B8 ADC Biquad Coefficient A1 */
{ 0xB9, 0x00 }, /* B9 ADC Biquad Coefficient A1 */
{ 0xBA, 0x00 }, /* BA ADC Biquad Coefficient A1 */
{ 0xBB, 0x00 }, /* BB ADC Biquad Coefficient A2 */
{ 0xBC, 0x00 }, /* BC ADC Biquad Coefficient A2 */
{ 0xBD, 0x00 }, /* BD ADC Biquad Coefficient A2 */
{ 0xBE, 0x00 }, /* BE Digital Mic 3 Volume */
{ 0xBF, 0x00 }, /* BF Digital Mic 4 Volume */
{ 0xC0, 0x00 }, /* C0 Digital Mic 34 Biquad Pre Atten */
{ 0xC1, 0x00 }, /* C1 Record TDM Slot */
{ 0xC2, 0x00 }, /* C2 Sample Rate */
{ 0xC3, 0x00 }, /* C3 Digital Mic 34 Biquad Coefficient C3 */
{ 0xC4, 0x00 }, /* C4 Digital Mic 34 Biquad Coefficient C4 */
{ 0xC5, 0x00 }, /* C5 Digital Mic 34 Biquad Coefficient C5 */
{ 0xC6, 0x00 }, /* C6 Digital Mic 34 Biquad Coefficient C6 */
{ 0xC7, 0x00 }, /* C7 Digital Mic 34 Biquad Coefficient C7 */
{ 0xC8, 0x00 }, /* C8 Digital Mic 34 Biquad Coefficient C8 */
{ 0xC9, 0x00 }, /* C9 Digital Mic 34 Biquad Coefficient C9 */
{ 0xCA, 0x00 }, /* CA Digital Mic 34 Biquad Coefficient CA */
{ 0xCB, 0x00 }, /* CB Digital Mic 34 Biquad Coefficient CB */
{ 0xCC, 0x00 }, /* CC Digital Mic 34 Biquad Coefficient CC */
{ 0xCD, 0x00 }, /* CD Digital Mic 34 Biquad Coefficient CD */
{ 0xCE, 0x00 }, /* CE Digital Mic 34 Biquad Coefficient CE */
{ 0xCF, 0x00 }, /* CF Digital Mic 34 Biquad Coefficient CF */
{ 0xD0, 0x00 }, /* D0 Digital Mic 34 Biquad Coefficient D0 */
{ 0xD1, 0x00 }, /* D1 Digital Mic 34 Biquad Coefficient D1 */
};
static bool max98090_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case M98090_REG_SOFTWARE_RESET:
case M98090_REG_DEVICE_STATUS:
case M98090_REG_JACK_STATUS:
case M98090_REG_REVISION_ID:
return true;
default:
return false;
}
}
static bool max98090_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case M98090_REG_DEVICE_STATUS ... M98090_REG_INTERRUPT_S:
case M98090_REG_LINE_INPUT_CONFIG ... 0xD1:
case M98090_REG_REVISION_ID:
return true;
default:
return false;
}
}
static int max98090_reset(struct max98090_priv *max98090)
{
int ret;
/* Reset the codec by writing to this write-only reset register */
ret = regmap_write(max98090->regmap, M98090_REG_SOFTWARE_RESET,
M98090_SWRESET_MASK);
if (ret < 0) {
dev_err(max98090->component->dev,
"Failed to reset codec: %d\n", ret);
return ret;
}
msleep(20);
return ret;
}
static const DECLARE_TLV_DB_RANGE(max98090_micboost_tlv,
0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0)
);
static const DECLARE_TLV_DB_SCALE(max98090_mic_tlv, 0, 100, 0);
static const DECLARE_TLV_DB_SCALE(max98090_line_single_ended_tlv,
-600, 600, 0);
static const DECLARE_TLV_DB_RANGE(max98090_line_tlv,
0, 3, TLV_DB_SCALE_ITEM(-600, 300, 0),
4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0)
);
static const DECLARE_TLV_DB_SCALE(max98090_avg_tlv, 0, 600, 0);
static const DECLARE_TLV_DB_SCALE(max98090_av_tlv, -1200, 100, 0);
static const DECLARE_TLV_DB_SCALE(max98090_dvg_tlv, 0, 600, 0);
static const DECLARE_TLV_DB_SCALE(max98090_dv_tlv, -1500, 100, 0);
static const DECLARE_TLV_DB_SCALE(max98090_alcmakeup_tlv, 0, 100, 0);
static const DECLARE_TLV_DB_SCALE(max98090_alccomp_tlv, -3100, 100, 0);
static const DECLARE_TLV_DB_SCALE(max98090_drcexp_tlv, -6600, 100, 0);
static const DECLARE_TLV_DB_SCALE(max98090_sdg_tlv, 50, 200, 0);
static const DECLARE_TLV_DB_RANGE(max98090_mixout_tlv,
0, 1, TLV_DB_SCALE_ITEM(-1200, 250, 0),
2, 3, TLV_DB_SCALE_ITEM(-600, 600, 0)
);
static const DECLARE_TLV_DB_RANGE(max98090_hp_tlv,
0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
28, 31, TLV_DB_SCALE_ITEM(150, 50, 0)
);
static const DECLARE_TLV_DB_RANGE(max98090_spk_tlv,
0, 4, TLV_DB_SCALE_ITEM(-4800, 400, 0),
5, 10, TLV_DB_SCALE_ITEM(-2900, 300, 0),
11, 14, TLV_DB_SCALE_ITEM(-1200, 200, 0),
15, 29, TLV_DB_SCALE_ITEM(-500, 100, 0),
30, 39, TLV_DB_SCALE_ITEM(950, 50, 0)
);
static const DECLARE_TLV_DB_RANGE(max98090_rcv_lout_tlv,
0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
22, 27, TLV_DB_SCALE_ITEM(100, 100, 0),
28, 31, TLV_DB_SCALE_ITEM(650, 50, 0)
);
static int max98090_get_enab_tlv(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
unsigned int mask = (1 << fls(mc->max)) - 1;
unsigned int val = snd_soc_component_read(component, mc->reg);
unsigned int *select;
switch (mc->reg) {
case M98090_REG_MIC1_INPUT_LEVEL:
select = &(max98090->pa1en);
break;
case M98090_REG_MIC2_INPUT_LEVEL:
select = &(max98090->pa2en);
break;
case M98090_REG_ADC_SIDETONE:
select = &(max98090->sidetone);
break;
default:
return -EINVAL;
}
val = (val >> mc->shift) & mask;
if (val >= 1) {
/* If on, return the volume */
val = val - 1;
*select = val;
} else {
/* If off, return last stored value */
val = *select;
}
ucontrol->value.integer.value[0] = val;
return 0;
}
static int max98090_put_enab_tlv(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
unsigned int mask = (1 << fls(mc->max)) - 1;
unsigned int sel = ucontrol->value.integer.value[0];
unsigned int val = snd_soc_component_read(component, mc->reg);
unsigned int *select;
switch (mc->reg) {
case M98090_REG_MIC1_INPUT_LEVEL:
select = &(max98090->pa1en);
break;
case M98090_REG_MIC2_INPUT_LEVEL:
select = &(max98090->pa2en);
break;
case M98090_REG_ADC_SIDETONE:
select = &(max98090->sidetone);
break;
default:
return -EINVAL;
}
val = (val >> mc->shift) & mask;
*select = sel;
/* Setting a volume is only valid if it is already On */
if (val >= 1) {
sel = sel + 1;
} else {
/* Write what was already there */
sel = val;
}
snd_soc_component_update_bits(component, mc->reg,
mask << mc->shift,
sel << mc->shift);
return 0;
}
static const char *max98090_perf_pwr_text[] =
{ "High Performance", "Low Power" };
static const char *max98090_pwr_perf_text[] =
{ "Low Power", "High Performance" };
static SOC_ENUM_SINGLE_DECL(max98090_vcmbandgap_enum,
M98090_REG_BIAS_CONTROL,
M98090_VCM_MODE_SHIFT,
max98090_pwr_perf_text);
static const char *max98090_osr128_text[] = { "64*fs", "128*fs" };
static SOC_ENUM_SINGLE_DECL(max98090_osr128_enum,
M98090_REG_ADC_CONTROL,
M98090_OSR128_SHIFT,
max98090_osr128_text);
static const char *max98090_mode_text[] = { "Voice", "Music" };
static SOC_ENUM_SINGLE_DECL(max98090_mode_enum,
M98090_REG_FILTER_CONFIG,
M98090_MODE_SHIFT,
max98090_mode_text);
static SOC_ENUM_SINGLE_DECL(max98090_filter_dmic34mode_enum,
M98090_REG_FILTER_CONFIG,
M98090_FLT_DMIC34MODE_SHIFT,
max98090_mode_text);
static const char *max98090_drcatk_text[] =
{ "0.5ms", "1ms", "5ms", "10ms", "25ms", "50ms", "100ms", "200ms" };
static SOC_ENUM_SINGLE_DECL(max98090_drcatk_enum,
M98090_REG_DRC_TIMING,
M98090_DRCATK_SHIFT,
max98090_drcatk_text);
static const char *max98090_drcrls_text[] =
{ "8s", "4s", "2s", "1s", "0.5s", "0.25s", "0.125s", "0.0625s" };
static SOC_ENUM_SINGLE_DECL(max98090_drcrls_enum,
M98090_REG_DRC_TIMING,
M98090_DRCRLS_SHIFT,
max98090_drcrls_text);
static const char *max98090_alccmp_text[] =
{ "1:1", "1:1.5", "1:2", "1:4", "1:INF" };
static SOC_ENUM_SINGLE_DECL(max98090_alccmp_enum,
M98090_REG_DRC_COMPRESSOR,
M98090_DRCCMP_SHIFT,
max98090_alccmp_text);
static const char *max98090_drcexp_text[] = { "1:1", "2:1", "3:1" };
static SOC_ENUM_SINGLE_DECL(max98090_drcexp_enum,
M98090_REG_DRC_EXPANDER,
M98090_DRCEXP_SHIFT,
max98090_drcexp_text);
static SOC_ENUM_SINGLE_DECL(max98090_dac_perfmode_enum,
M98090_REG_DAC_CONTROL,
M98090_PERFMODE_SHIFT,
max98090_perf_pwr_text);
static SOC_ENUM_SINGLE_DECL(max98090_dachp_enum,
M98090_REG_DAC_CONTROL,
M98090_DACHP_SHIFT,
max98090_pwr_perf_text);
static SOC_ENUM_SINGLE_DECL(max98090_adchp_enum,
M98090_REG_ADC_CONTROL,
M98090_ADCHP_SHIFT,
max98090_pwr_perf_text);
static const struct snd_kcontrol_new max98090_snd_controls[] = {
SOC_ENUM("MIC Bias VCM Bandgap", max98090_vcmbandgap_enum),
SOC_SINGLE("DMIC MIC Comp Filter Config", M98090_REG_DIGITAL_MIC_CONFIG,
M98090_DMIC_COMP_SHIFT, M98090_DMIC_COMP_NUM - 1, 0),
SOC_SINGLE_EXT_TLV("MIC1 Boost Volume",
M98090_REG_MIC1_INPUT_LEVEL, M98090_MIC_PA1EN_SHIFT,
M98090_MIC_PA1EN_NUM - 1, 0, max98090_get_enab_tlv,
max98090_put_enab_tlv, max98090_micboost_tlv),
SOC_SINGLE_EXT_TLV("MIC2 Boost Volume",
M98090_REG_MIC2_INPUT_LEVEL, M98090_MIC_PA2EN_SHIFT,
M98090_MIC_PA2EN_NUM - 1, 0, max98090_get_enab_tlv,
max98090_put_enab_tlv, max98090_micboost_tlv),
SOC_SINGLE_TLV("MIC1 Volume", M98090_REG_MIC1_INPUT_LEVEL,
M98090_MIC_PGAM1_SHIFT, M98090_MIC_PGAM1_NUM - 1, 1,
max98090_mic_tlv),
SOC_SINGLE_TLV("MIC2 Volume", M98090_REG_MIC2_INPUT_LEVEL,
M98090_MIC_PGAM2_SHIFT, M98090_MIC_PGAM2_NUM - 1, 1,
max98090_mic_tlv),
SOC_SINGLE_RANGE_TLV("LINEA Single Ended Volume",
M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG135_SHIFT, 0,
M98090_MIXG135_NUM - 1, 1, max98090_line_single_ended_tlv),
SOC_SINGLE_RANGE_TLV("LINEB Single Ended Volume",
M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG246_SHIFT, 0,
M98090_MIXG246_NUM - 1, 1, max98090_line_single_ended_tlv),
SOC_SINGLE_RANGE_TLV("LINEA Volume", M98090_REG_LINE_INPUT_LEVEL,
M98090_LINAPGA_SHIFT, 0, M98090_LINAPGA_NUM - 1, 1,
max98090_line_tlv),
SOC_SINGLE_RANGE_TLV("LINEB Volume", M98090_REG_LINE_INPUT_LEVEL,
M98090_LINBPGA_SHIFT, 0, M98090_LINBPGA_NUM - 1, 1,
max98090_line_tlv),
SOC_SINGLE("LINEA Ext Resistor Gain Mode", M98090_REG_INPUT_MODE,
M98090_EXTBUFA_SHIFT, M98090_EXTBUFA_NUM - 1, 0),
SOC_SINGLE("LINEB Ext Resistor Gain Mode", M98090_REG_INPUT_MODE,
M98090_EXTBUFB_SHIFT, M98090_EXTBUFB_NUM - 1, 0),
SOC_SINGLE_TLV("ADCL Boost Volume", M98090_REG_LEFT_ADC_LEVEL,
M98090_AVLG_SHIFT, M98090_AVLG_NUM - 1, 0,
max98090_avg_tlv),
SOC_SINGLE_TLV("ADCR Boost Volume", M98090_REG_RIGHT_ADC_LEVEL,
M98090_AVRG_SHIFT, M98090_AVLG_NUM - 1, 0,
max98090_avg_tlv),
SOC_SINGLE_TLV("ADCL Volume", M98090_REG_LEFT_ADC_LEVEL,
M98090_AVL_SHIFT, M98090_AVL_NUM - 1, 1,
max98090_av_tlv),
SOC_SINGLE_TLV("ADCR Volume", M98090_REG_RIGHT_ADC_LEVEL,
M98090_AVR_SHIFT, M98090_AVR_NUM - 1, 1,
max98090_av_tlv),
SOC_ENUM("ADC Oversampling Rate", max98090_osr128_enum),
SOC_SINGLE("ADC Quantizer Dither", M98090_REG_ADC_CONTROL,
M98090_ADCDITHER_SHIFT, M98090_ADCDITHER_NUM - 1, 0),
SOC_ENUM("ADC High Performance Mode", max98090_adchp_enum),
SOC_SINGLE("DAC Mono Mode", M98090_REG_IO_CONFIGURATION,
M98090_DMONO_SHIFT, M98090_DMONO_NUM - 1, 0),
SOC_SINGLE("SDIN Mode", M98090_REG_IO_CONFIGURATION,
M98090_SDIEN_SHIFT, M98090_SDIEN_NUM - 1, 0),
SOC_SINGLE("SDOUT Mode", M98090_REG_IO_CONFIGURATION,
M98090_SDOEN_SHIFT, M98090_SDOEN_NUM - 1, 0),
SOC_SINGLE("SDOUT Hi-Z Mode", M98090_REG_IO_CONFIGURATION,
M98090_HIZOFF_SHIFT, M98090_HIZOFF_NUM - 1, 1),
SOC_ENUM("Filter Mode", max98090_mode_enum),
SOC_SINGLE("Record Path DC Blocking", M98090_REG_FILTER_CONFIG,
M98090_AHPF_SHIFT, M98090_AHPF_NUM - 1, 0),
SOC_SINGLE("Playback Path DC Blocking", M98090_REG_FILTER_CONFIG,
M98090_DHPF_SHIFT, M98090_DHPF_NUM - 1, 0),
SOC_SINGLE_TLV("Digital BQ Volume", M98090_REG_ADC_BIQUAD_LEVEL,
M98090_AVBQ_SHIFT, M98090_AVBQ_NUM - 1, 1, max98090_dv_tlv),
SOC_SINGLE_EXT_TLV("Digital Sidetone Volume",
M98090_REG_ADC_SIDETONE, M98090_DVST_SHIFT,
M98090_DVST_NUM - 1, 1, max98090_get_enab_tlv,
max98090_put_enab_tlv, max98090_sdg_tlv),
SOC_SINGLE_TLV("Digital Coarse Volume", M98090_REG_DAI_PLAYBACK_LEVEL,
M98090_DVG_SHIFT, M98090_DVG_NUM - 1, 0,
max98090_dvg_tlv),
SOC_SINGLE_TLV("Digital Volume", M98090_REG_DAI_PLAYBACK_LEVEL,
M98090_DV_SHIFT, M98090_DV_NUM - 1, 1,
max98090_dv_tlv),
SND_SOC_BYTES("EQ Coefficients", M98090_REG_EQUALIZER_BASE, 105),
SOC_SINGLE("Digital EQ 3 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
M98090_EQ3BANDEN_SHIFT, M98090_EQ3BANDEN_NUM - 1, 0),
SOC_SINGLE("Digital EQ 5 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
M98090_EQ5BANDEN_SHIFT, M98090_EQ5BANDEN_NUM - 1, 0),
SOC_SINGLE("Digital EQ 7 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
M98090_EQ7BANDEN_SHIFT, M98090_EQ7BANDEN_NUM - 1, 0),
SOC_SINGLE("Digital EQ Clipping Detection", M98090_REG_DAI_PLAYBACK_LEVEL_EQ,
M98090_EQCLPN_SHIFT, M98090_EQCLPN_NUM - 1,
1),
SOC_SINGLE_TLV("Digital EQ Volume", M98090_REG_DAI_PLAYBACK_LEVEL_EQ,
M98090_DVEQ_SHIFT, M98090_DVEQ_NUM - 1, 1,
max98090_dv_tlv),
SOC_SINGLE("ALC Enable", M98090_REG_DRC_TIMING,
M98090_DRCEN_SHIFT, M98090_DRCEN_NUM - 1, 0),
SOC_ENUM("ALC Attack Time", max98090_drcatk_enum),
SOC_ENUM("ALC Release Time", max98090_drcrls_enum),
SOC_SINGLE_TLV("ALC Make Up Volume", M98090_REG_DRC_GAIN,
M98090_DRCG_SHIFT, M98090_DRCG_NUM - 1, 0,
max98090_alcmakeup_tlv),
SOC_ENUM("ALC Compression Ratio", max98090_alccmp_enum),
SOC_ENUM("ALC Expansion Ratio", max98090_drcexp_enum),
SOC_SINGLE_TLV("ALC Compression Threshold Volume",
M98090_REG_DRC_COMPRESSOR, M98090_DRCTHC_SHIFT,
M98090_DRCTHC_NUM - 1, 1, max98090_alccomp_tlv),
SOC_SINGLE_TLV("ALC Expansion Threshold Volume",
M98090_REG_DRC_EXPANDER, M98090_DRCTHE_SHIFT,
M98090_DRCTHE_NUM - 1, 1, max98090_drcexp_tlv),
SOC_ENUM("DAC HP Playback Performance Mode",
max98090_dac_perfmode_enum),
SOC_ENUM("DAC High Performance Mode", max98090_dachp_enum),
SOC_SINGLE_TLV("Headphone Left Mixer Volume",
M98090_REG_HP_CONTROL, M98090_MIXHPLG_SHIFT,
M98090_MIXHPLG_NUM - 1, 1, max98090_mixout_tlv),
SOC_SINGLE_TLV("Headphone Right Mixer Volume",
M98090_REG_HP_CONTROL, M98090_MIXHPRG_SHIFT,
M98090_MIXHPRG_NUM - 1, 1, max98090_mixout_tlv),
SOC_SINGLE_TLV("Speaker Left Mixer Volume",
M98090_REG_SPK_CONTROL, M98090_MIXSPLG_SHIFT,
M98090_MIXSPLG_NUM - 1, 1, max98090_mixout_tlv),
SOC_SINGLE_TLV("Speaker Right Mixer Volume",
M98090_REG_SPK_CONTROL, M98090_MIXSPRG_SHIFT,
M98090_MIXSPRG_NUM - 1, 1, max98090_mixout_tlv),
SOC_SINGLE_TLV("Receiver Left Mixer Volume",
M98090_REG_RCV_LOUTL_CONTROL, M98090_MIXRCVLG_SHIFT,
M98090_MIXRCVLG_NUM - 1, 1, max98090_mixout_tlv),
SOC_SINGLE_TLV("Receiver Right Mixer Volume",
M98090_REG_LOUTR_CONTROL, M98090_MIXRCVRG_SHIFT,
M98090_MIXRCVRG_NUM - 1, 1, max98090_mixout_tlv),
SOC_DOUBLE_R_TLV("Headphone Volume", M98090_REG_LEFT_HP_VOLUME,
M98090_REG_RIGHT_HP_VOLUME, M98090_HPVOLL_SHIFT,
M98090_HPVOLL_NUM - 1, 0, max98090_hp_tlv),
SOC_DOUBLE_R_RANGE_TLV("Speaker Volume",
M98090_REG_LEFT_SPK_VOLUME, M98090_REG_RIGHT_SPK_VOLUME,
M98090_SPVOLL_SHIFT, 24, M98090_SPVOLL_NUM - 1 + 24,
0, max98090_spk_tlv),
SOC_DOUBLE_R_TLV("Receiver Volume", M98090_REG_RCV_LOUTL_VOLUME,
M98090_REG_LOUTR_VOLUME, M98090_RCVLVOL_SHIFT,
M98090_RCVLVOL_NUM - 1, 0, max98090_rcv_lout_tlv),
SOC_SINGLE("Headphone Left Switch", M98090_REG_LEFT_HP_VOLUME,
M98090_HPLM_SHIFT, 1, 1),
SOC_SINGLE("Headphone Right Switch", M98090_REG_RIGHT_HP_VOLUME,
M98090_HPRM_SHIFT, 1, 1),
SOC_SINGLE("Speaker Left Switch", M98090_REG_LEFT_SPK_VOLUME,
M98090_SPLM_SHIFT, 1, 1),
SOC_SINGLE("Speaker Right Switch", M98090_REG_RIGHT_SPK_VOLUME,
M98090_SPRM_SHIFT, 1, 1),
SOC_SINGLE("Receiver Left Switch", M98090_REG_RCV_LOUTL_VOLUME,
M98090_RCVLM_SHIFT, 1, 1),
SOC_SINGLE("Receiver Right Switch", M98090_REG_LOUTR_VOLUME,
M98090_RCVRM_SHIFT, 1, 1),
SOC_SINGLE("Zero-Crossing Detection", M98090_REG_LEVEL_CONTROL,
M98090_ZDENN_SHIFT, M98090_ZDENN_NUM - 1, 1),
SOC_SINGLE("Enhanced Vol Smoothing", M98090_REG_LEVEL_CONTROL,
M98090_VS2ENN_SHIFT, M98090_VS2ENN_NUM - 1, 1),
SOC_SINGLE("Volume Adjustment Smoothing", M98090_REG_LEVEL_CONTROL,
M98090_VSENN_SHIFT, M98090_VSENN_NUM - 1, 1),
SND_SOC_BYTES("Biquad Coefficients", M98090_REG_RECORD_BIQUAD_BASE, 15),
SOC_SINGLE("Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
M98090_ADCBQEN_SHIFT, M98090_ADCBQEN_NUM - 1, 0),
};
static const struct snd_kcontrol_new max98091_snd_controls[] = {
SOC_SINGLE("DMIC34 Zeropad", M98090_REG_SAMPLE_RATE,
M98090_DMIC34_ZEROPAD_SHIFT,
M98090_DMIC34_ZEROPAD_NUM - 1, 0),
SOC_ENUM("Filter DMIC34 Mode", max98090_filter_dmic34mode_enum),
SOC_SINGLE("DMIC34 DC Blocking", M98090_REG_FILTER_CONFIG,
M98090_FLT_DMIC34HPF_SHIFT,
M98090_FLT_DMIC34HPF_NUM - 1, 0),
SOC_SINGLE_TLV("DMIC3 Boost Volume", M98090_REG_DMIC3_VOLUME,
M98090_DMIC_AV3G_SHIFT, M98090_DMIC_AV3G_NUM - 1, 0,
max98090_avg_tlv),
SOC_SINGLE_TLV("DMIC4 Boost Volume", M98090_REG_DMIC4_VOLUME,
M98090_DMIC_AV4G_SHIFT, M98090_DMIC_AV4G_NUM - 1, 0,
max98090_avg_tlv),
SOC_SINGLE_TLV("DMIC3 Volume", M98090_REG_DMIC3_VOLUME,
M98090_DMIC_AV3_SHIFT, M98090_DMIC_AV3_NUM - 1, 1,
max98090_av_tlv),
SOC_SINGLE_TLV("DMIC4 Volume", M98090_REG_DMIC4_VOLUME,
M98090_DMIC_AV4_SHIFT, M98090_DMIC_AV4_NUM - 1, 1,
max98090_av_tlv),
SND_SOC_BYTES("DMIC34 Biquad Coefficients",
M98090_REG_DMIC34_BIQUAD_BASE, 15),
SOC_SINGLE("DMIC34 Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
M98090_DMIC34BQEN_SHIFT, M98090_DMIC34BQEN_NUM - 1, 0),
SOC_SINGLE_TLV("DMIC34 BQ PreAttenuation Volume",
M98090_REG_DMIC34_BQ_PREATTEN, M98090_AV34BQ_SHIFT,
M98090_AV34BQ_NUM - 1, 1, max98090_dv_tlv),
};
static int max98090_micinput_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
unsigned int val = snd_soc_component_read(component, w->reg);
if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
val = (val & M98090_MIC_PA1EN_MASK) >> M98090_MIC_PA1EN_SHIFT;
else
val = (val & M98090_MIC_PA2EN_MASK) >> M98090_MIC_PA2EN_SHIFT;
if (val >= 1) {
if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) {
max98090->pa1en = val - 1; /* Update for volatile */
} else {
max98090->pa2en = val - 1; /* Update for volatile */
}
}
switch (event) {
case SND_SOC_DAPM_POST_PMU:
/* If turning on, set to most recently selected volume */
if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
val = max98090->pa1en + 1;
else
val = max98090->pa2en + 1;
break;
case SND_SOC_DAPM_POST_PMD:
/* If turning off, turn off */
val = 0;
break;
default:
return -EINVAL;
}
if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
snd_soc_component_update_bits(component, w->reg, M98090_MIC_PA1EN_MASK,
val << M98090_MIC_PA1EN_SHIFT);
else
snd_soc_component_update_bits(component, w->reg, M98090_MIC_PA2EN_MASK,
val << M98090_MIC_PA2EN_SHIFT);
return 0;
}
static int max98090_shdn_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
if (event & SND_SOC_DAPM_POST_PMU)
max98090->shdn_pending = true;
return 0;
}
static const char *mic1_mux_text[] = { "IN12", "IN56" };
static SOC_ENUM_SINGLE_DECL(mic1_mux_enum,
M98090_REG_INPUT_MODE,
M98090_EXTMIC1_SHIFT,
mic1_mux_text);
static const struct snd_kcontrol_new max98090_mic1_mux =
SOC_DAPM_ENUM("MIC1 Mux", mic1_mux_enum);
static const char *mic2_mux_text[] = { "IN34", "IN56" };
static SOC_ENUM_SINGLE_DECL(mic2_mux_enum,
M98090_REG_INPUT_MODE,
M98090_EXTMIC2_SHIFT,
mic2_mux_text);
static const struct snd_kcontrol_new max98090_mic2_mux =
SOC_DAPM_ENUM("MIC2 Mux", mic2_mux_enum);
static const char *dmic_mux_text[] = { "ADC", "DMIC" };
static SOC_ENUM_SINGLE_VIRT_DECL(dmic_mux_enum, dmic_mux_text);
static const struct snd_kcontrol_new max98090_dmic_mux =
SOC_DAPM_ENUM("DMIC Mux", dmic_mux_enum);
/* LINEA mixer switch */
static const struct snd_kcontrol_new max98090_linea_mixer_controls[] = {
SOC_DAPM_SINGLE("IN1 Switch", M98090_REG_LINE_INPUT_CONFIG,
M98090_IN1SEEN_SHIFT, 1, 0),
SOC_DAPM_SINGLE("IN3 Switch", M98090_REG_LINE_INPUT_CONFIG,
M98090_IN3SEEN_SHIFT, 1, 0),
SOC_DAPM_SINGLE("IN5 Switch", M98090_REG_LINE_INPUT_CONFIG,
M98090_IN5SEEN_SHIFT, 1, 0),
SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LINE_INPUT_CONFIG,
M98090_IN34DIFF_SHIFT, 1, 0),
};
/* LINEB mixer switch */
static const struct snd_kcontrol_new max98090_lineb_mixer_controls[] = {
SOC_DAPM_SINGLE("IN2 Switch", M98090_REG_LINE_INPUT_CONFIG,
M98090_IN2SEEN_SHIFT, 1, 0),
SOC_DAPM_SINGLE("IN4 Switch", M98090_REG_LINE_INPUT_CONFIG,
M98090_IN4SEEN_SHIFT, 1, 0),
SOC_DAPM_SINGLE("IN6 Switch", M98090_REG_LINE_INPUT_CONFIG,
M98090_IN6SEEN_SHIFT, 1, 0),
SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LINE_INPUT_CONFIG,
M98090_IN56DIFF_SHIFT, 1, 0),
};
/* Left ADC mixer switch */
static const struct snd_kcontrol_new max98090_left_adc_mixer_controls[] = {
SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_LEFT_ADC_MIXER,
M98090_MIXADL_IN12DIFF_SHIFT, 1, 0),
SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LEFT_ADC_MIXER,
M98090_MIXADL_IN34DIFF_SHIFT, 1, 0),
SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LEFT_ADC_MIXER,
M98090_MIXADL_IN65DIFF_SHIFT, 1, 0),
SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_ADC_MIXER,
M98090_MIXADL_LINEA_SHIFT, 1, 0),
SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_ADC_MIXER,
M98090_MIXADL_LINEB_SHIFT, 1, 0),
SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_ADC_MIXER,
M98090_MIXADL_MIC1_SHIFT, 1, 0),
SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_ADC_MIXER,
M98090_MIXADL_MIC2_SHIFT, 1, 0),
};
/* Right ADC mixer switch */
static const struct snd_kcontrol_new max98090_right_adc_mixer_controls[] = {
SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_RIGHT_ADC_MIXER,
M98090_MIXADR_IN12DIFF_SHIFT, 1, 0),
SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_RIGHT_ADC_MIXER,
M98090_MIXADR_IN34DIFF_SHIFT, 1, 0),
SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_RIGHT_ADC_MIXER,
M98090_MIXADR_IN65DIFF_SHIFT, 1, 0),
SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_ADC_MIXER,
M98090_MIXADR_LINEA_SHIFT, 1, 0),
SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_ADC_MIXER,
M98090_MIXADR_LINEB_SHIFT, 1, 0),
SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_ADC_MIXER,
M98090_MIXADR_MIC1_SHIFT, 1, 0),
SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_ADC_MIXER,
M98090_MIXADR_MIC2_SHIFT, 1, 0),
};
static const char *lten_mux_text[] = { "Normal", "Loopthrough" };
static SOC_ENUM_SINGLE_DECL(ltenl_mux_enum,
M98090_REG_IO_CONFIGURATION,
M98090_LTEN_SHIFT,
lten_mux_text);
static SOC_ENUM_SINGLE_DECL(ltenr_mux_enum,
M98090_REG_IO_CONFIGURATION,
M98090_LTEN_SHIFT,
lten_mux_text);
static const struct snd_kcontrol_new max98090_ltenl_mux =
SOC_DAPM_ENUM("LTENL Mux", ltenl_mux_enum);
static const struct snd_kcontrol_new max98090_ltenr_mux =
SOC_DAPM_ENUM("LTENR Mux", ltenr_mux_enum);
static const char *lben_mux_text[] = { "Normal", "Loopback" };
static SOC_ENUM_SINGLE_DECL(lbenl_mux_enum,
M98090_REG_IO_CONFIGURATION,
M98090_LBEN_SHIFT,
lben_mux_text);
static SOC_ENUM_SINGLE_DECL(lbenr_mux_enum,
M98090_REG_IO_CONFIGURATION,
M98090_LBEN_SHIFT,
lben_mux_text);
static const struct snd_kcontrol_new max98090_lbenl_mux =
SOC_DAPM_ENUM("LBENL Mux", lbenl_mux_enum);
static const struct snd_kcontrol_new max98090_lbenr_mux =
SOC_DAPM_ENUM("LBENR Mux", lbenr_mux_enum);
static const char *stenl_mux_text[] = { "Normal", "Sidetone Left" };
static const char *stenr_mux_text[] = { "Normal", "Sidetone Right" };
static SOC_ENUM_SINGLE_DECL(stenl_mux_enum,
M98090_REG_ADC_SIDETONE,
M98090_DSTSL_SHIFT,
stenl_mux_text);
static SOC_ENUM_SINGLE_DECL(stenr_mux_enum,
M98090_REG_ADC_SIDETONE,
M98090_DSTSR_SHIFT,
stenr_mux_text);
static const struct snd_kcontrol_new max98090_stenl_mux =
SOC_DAPM_ENUM("STENL Mux", stenl_mux_enum);
static const struct snd_kcontrol_new max98090_stenr_mux =
SOC_DAPM_ENUM("STENR Mux", stenr_mux_enum);
/* Left speaker mixer switch */
static const struct
snd_kcontrol_new max98090_left_speaker_mixer_controls[] = {
SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_SPK_MIXER,
M98090_MIXSPL_DACL_SHIFT, 1, 0),
SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_SPK_MIXER,
M98090_MIXSPL_DACR_SHIFT, 1, 0),
SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_SPK_MIXER,
M98090_MIXSPL_LINEA_SHIFT, 1, 0),
SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_SPK_MIXER,
M98090_MIXSPL_LINEB_SHIFT, 1, 0),
SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_SPK_MIXER,
M98090_MIXSPL_MIC1_SHIFT, 1, 0),
SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_SPK_MIXER,
M98090_MIXSPL_MIC2_SHIFT, 1, 0),
};
/* Right speaker mixer switch */
static const struct
snd_kcontrol_new max98090_right_speaker_mixer_controls[] = {
SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_SPK_MIXER,
M98090_MIXSPR_DACL_SHIFT, 1, 0),
SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_SPK_MIXER,
M98090_MIXSPR_DACR_SHIFT, 1, 0),
SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_SPK_MIXER,
M98090_MIXSPR_LINEA_SHIFT, 1, 0),
SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_SPK_MIXER,
M98090_MIXSPR_LINEB_SHIFT, 1, 0),
SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_SPK_MIXER,
M98090_MIXSPR_MIC1_SHIFT, 1, 0),
SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_SPK_MIXER,
M98090_MIXSPR_MIC2_SHIFT, 1, 0),
};
/* Left headphone mixer switch */
static const struct snd_kcontrol_new max98090_left_hp_mixer_controls[] = {
SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_HP_MIXER,
M98090_MIXHPL_DACL_SHIFT, 1, 0),
SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_HP_MIXER,
M98090_MIXHPL_DACR_SHIFT, 1, 0),
SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_HP_MIXER,
M98090_MIXHPL_LINEA_SHIFT, 1, 0),
SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_HP_MIXER,
M98090_MIXHPL_LINEB_SHIFT, 1, 0),
SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_HP_MIXER,
M98090_MIXHPL_MIC1_SHIFT, 1, 0),
SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_HP_MIXER,
M98090_MIXHPL_MIC2_SHIFT, 1, 0),
};
/* Right headphone mixer switch */
static const struct snd_kcontrol_new max98090_right_hp_mixer_controls[] = {
SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_HP_MIXER,
M98090_MIXHPR_DACL_SHIFT, 1, 0),
SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_HP_MIXER,
M98090_MIXHPR_DACR_SHIFT, 1, 0),
SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_HP_MIXER,
M98090_MIXHPR_LINEA_SHIFT, 1, 0),
SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_HP_MIXER,
M98090_MIXHPR_LINEB_SHIFT, 1, 0),
SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_HP_MIXER,
M98090_MIXHPR_MIC1_SHIFT, 1, 0),
SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_HP_MIXER,
M98090_MIXHPR_MIC2_SHIFT, 1, 0),
};
/* Left receiver mixer switch */
static const struct snd_kcontrol_new max98090_left_rcv_mixer_controls[] = {
SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RCV_LOUTL_MIXER,
M98090_MIXRCVL_DACL_SHIFT, 1, 0),
SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RCV_LOUTL_MIXER,