forked from torvalds/linux
-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathnau8824.c
1956 lines (1712 loc) · 61.7 KB
/
nau8824.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
// SPDX-License-Identifier: GPL-2.0-only
/*
* NAU88L24 ALSA SoC audio driver
*
* Copyright 2016 Nuvoton Technology Corp.
* Author: John Hsu <[email protected]>
*/
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/clk.h>
#include <linux/acpi.h>
#include <linux/math64.h>
#include <linux/semaphore.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/jack.h>
#include "nau8824.h"
static int nau8824_config_sysclk(struct nau8824 *nau8824,
int clk_id, unsigned int freq);
static bool nau8824_is_jack_inserted(struct nau8824 *nau8824);
/* the ADC threshold of headset */
#define DMIC_CLK 3072000
/* the ADC threshold of headset */
#define HEADSET_SARADC_THD 0x80
/* the parameter threshold of FLL */
#define NAU_FREF_MAX 13500000
#define NAU_FVCO_MAX 100000000
#define NAU_FVCO_MIN 90000000
/* scaling for mclk from sysclk_src output */
static const struct nau8824_fll_attr mclk_src_scaling[] = {
{ 1, 0x0 },
{ 2, 0x2 },
{ 4, 0x3 },
{ 8, 0x4 },
{ 16, 0x5 },
{ 32, 0x6 },
{ 3, 0x7 },
{ 6, 0xa },
{ 12, 0xb },
{ 24, 0xc },
};
/* ratio for input clk freq */
static const struct nau8824_fll_attr fll_ratio[] = {
{ 512000, 0x01 },
{ 256000, 0x02 },
{ 128000, 0x04 },
{ 64000, 0x08 },
{ 32000, 0x10 },
{ 8000, 0x20 },
{ 4000, 0x40 },
};
static const struct nau8824_fll_attr fll_pre_scalar[] = {
{ 1, 0x0 },
{ 2, 0x1 },
{ 4, 0x2 },
{ 8, 0x3 },
};
/* the maximum frequency of CLK_ADC and CLK_DAC */
#define CLK_DA_AD_MAX 6144000
/* over sampling rate */
static const struct nau8824_osr_attr osr_dac_sel[] = {
{ 64, 2 }, /* OSR 64, SRC 1/4 */
{ 256, 0 }, /* OSR 256, SRC 1 */
{ 128, 1 }, /* OSR 128, SRC 1/2 */
{ 0, 0 },
{ 32, 3 }, /* OSR 32, SRC 1/8 */
};
static const struct nau8824_osr_attr osr_adc_sel[] = {
{ 32, 3 }, /* OSR 32, SRC 1/8 */
{ 64, 2 }, /* OSR 64, SRC 1/4 */
{ 128, 1 }, /* OSR 128, SRC 1/2 */
{ 256, 0 }, /* OSR 256, SRC 1 */
};
static const struct reg_default nau8824_reg_defaults[] = {
{ NAU8824_REG_ENA_CTRL, 0x0000 },
{ NAU8824_REG_CLK_GATING_ENA, 0x0000 },
{ NAU8824_REG_CLK_DIVIDER, 0x0000 },
{ NAU8824_REG_FLL1, 0x0000 },
{ NAU8824_REG_FLL2, 0x3126 },
{ NAU8824_REG_FLL3, 0x0008 },
{ NAU8824_REG_FLL4, 0x0010 },
{ NAU8824_REG_FLL5, 0xC000 },
{ NAU8824_REG_FLL6, 0x6000 },
{ NAU8824_REG_FLL_VCO_RSV, 0xF13C },
{ NAU8824_REG_JACK_DET_CTRL, 0x0000 },
{ NAU8824_REG_INTERRUPT_SETTING_1, 0x0000 },
{ NAU8824_REG_IRQ, 0x0000 },
{ NAU8824_REG_CLEAR_INT_REG, 0x0000 },
{ NAU8824_REG_INTERRUPT_SETTING, 0x1000 },
{ NAU8824_REG_SAR_ADC, 0x0015 },
{ NAU8824_REG_VDET_COEFFICIENT, 0x0110 },
{ NAU8824_REG_VDET_THRESHOLD_1, 0x0000 },
{ NAU8824_REG_VDET_THRESHOLD_2, 0x0000 },
{ NAU8824_REG_VDET_THRESHOLD_3, 0x0000 },
{ NAU8824_REG_VDET_THRESHOLD_4, 0x0000 },
{ NAU8824_REG_GPIO_SEL, 0x0000 },
{ NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 0x000B },
{ NAU8824_REG_PORT0_I2S_PCM_CTRL_2, 0x0010 },
{ NAU8824_REG_PORT0_LEFT_TIME_SLOT, 0x0000 },
{ NAU8824_REG_PORT0_RIGHT_TIME_SLOT, 0x0000 },
{ NAU8824_REG_TDM_CTRL, 0x0000 },
{ NAU8824_REG_ADC_HPF_FILTER, 0x0000 },
{ NAU8824_REG_ADC_FILTER_CTRL, 0x0002 },
{ NAU8824_REG_DAC_FILTER_CTRL_1, 0x0000 },
{ NAU8824_REG_DAC_FILTER_CTRL_2, 0x0000 },
{ NAU8824_REG_NOTCH_FILTER_1, 0x0000 },
{ NAU8824_REG_NOTCH_FILTER_2, 0x0000 },
{ NAU8824_REG_EQ1_LOW, 0x112C },
{ NAU8824_REG_EQ2_EQ3, 0x2C2C },
{ NAU8824_REG_EQ4_EQ5, 0x2C2C },
{ NAU8824_REG_ADC_CH0_DGAIN_CTRL, 0x0100 },
{ NAU8824_REG_ADC_CH1_DGAIN_CTRL, 0x0100 },
{ NAU8824_REG_ADC_CH2_DGAIN_CTRL, 0x0100 },
{ NAU8824_REG_ADC_CH3_DGAIN_CTRL, 0x0100 },
{ NAU8824_REG_DAC_MUTE_CTRL, 0x0000 },
{ NAU8824_REG_DAC_CH0_DGAIN_CTRL, 0x0100 },
{ NAU8824_REG_DAC_CH1_DGAIN_CTRL, 0x0100 },
{ NAU8824_REG_ADC_TO_DAC_ST, 0x0000 },
{ NAU8824_REG_DRC_KNEE_IP12_ADC_CH01, 0x1486 },
{ NAU8824_REG_DRC_KNEE_IP34_ADC_CH01, 0x0F12 },
{ NAU8824_REG_DRC_SLOPE_ADC_CH01, 0x25FF },
{ NAU8824_REG_DRC_ATKDCY_ADC_CH01, 0x3457 },
{ NAU8824_REG_DRC_KNEE_IP12_ADC_CH23, 0x1486 },
{ NAU8824_REG_DRC_KNEE_IP34_ADC_CH23, 0x0F12 },
{ NAU8824_REG_DRC_SLOPE_ADC_CH23, 0x25FF },
{ NAU8824_REG_DRC_ATKDCY_ADC_CH23, 0x3457 },
{ NAU8824_REG_DRC_GAINL_ADC0, 0x0200 },
{ NAU8824_REG_DRC_GAINL_ADC1, 0x0200 },
{ NAU8824_REG_DRC_GAINL_ADC2, 0x0200 },
{ NAU8824_REG_DRC_GAINL_ADC3, 0x0200 },
{ NAU8824_REG_DRC_KNEE_IP12_DAC, 0x1486 },
{ NAU8824_REG_DRC_KNEE_IP34_DAC, 0x0F12 },
{ NAU8824_REG_DRC_SLOPE_DAC, 0x25F9 },
{ NAU8824_REG_DRC_ATKDCY_DAC, 0x3457 },
{ NAU8824_REG_DRC_GAIN_DAC_CH0, 0x0200 },
{ NAU8824_REG_DRC_GAIN_DAC_CH1, 0x0200 },
{ NAU8824_REG_MODE, 0x0000 },
{ NAU8824_REG_MODE1, 0x0000 },
{ NAU8824_REG_MODE2, 0x0000 },
{ NAU8824_REG_CLASSG, 0x0000 },
{ NAU8824_REG_OTP_EFUSE, 0x0000 },
{ NAU8824_REG_OTPDOUT_1, 0x0000 },
{ NAU8824_REG_OTPDOUT_2, 0x0000 },
{ NAU8824_REG_MISC_CTRL, 0x0000 },
{ NAU8824_REG_I2C_TIMEOUT, 0xEFFF },
{ NAU8824_REG_TEST_MODE, 0x0000 },
{ NAU8824_REG_I2C_DEVICE_ID, 0x1AF1 },
{ NAU8824_REG_SAR_ADC_DATA_OUT, 0x00FF },
{ NAU8824_REG_BIAS_ADJ, 0x0000 },
{ NAU8824_REG_PGA_GAIN, 0x0000 },
{ NAU8824_REG_TRIM_SETTINGS, 0x0000 },
{ NAU8824_REG_ANALOG_CONTROL_1, 0x0000 },
{ NAU8824_REG_ANALOG_CONTROL_2, 0x0000 },
{ NAU8824_REG_ENABLE_LO, 0x0000 },
{ NAU8824_REG_GAIN_LO, 0x0000 },
{ NAU8824_REG_CLASSD_GAIN_1, 0x0000 },
{ NAU8824_REG_CLASSD_GAIN_2, 0x0000 },
{ NAU8824_REG_ANALOG_ADC_1, 0x0011 },
{ NAU8824_REG_ANALOG_ADC_2, 0x0020 },
{ NAU8824_REG_RDAC, 0x0008 },
{ NAU8824_REG_MIC_BIAS, 0x0006 },
{ NAU8824_REG_HS_VOLUME_CONTROL, 0x0000 },
{ NAU8824_REG_BOOST, 0x0000 },
{ NAU8824_REG_FEPGA, 0x0000 },
{ NAU8824_REG_FEPGA_II, 0x0000 },
{ NAU8824_REG_FEPGA_SE, 0x0000 },
{ NAU8824_REG_FEPGA_ATTENUATION, 0x0000 },
{ NAU8824_REG_ATT_PORT0, 0x0000 },
{ NAU8824_REG_ATT_PORT1, 0x0000 },
{ NAU8824_REG_POWER_UP_CONTROL, 0x0000 },
{ NAU8824_REG_CHARGE_PUMP_CONTROL, 0x0300 },
{ NAU8824_REG_CHARGE_PUMP_INPUT, 0x0013 },
};
static int nau8824_sema_acquire(struct nau8824 *nau8824, long timeout)
{
int ret;
if (timeout) {
ret = down_timeout(&nau8824->jd_sem, timeout);
if (ret < 0)
dev_warn(nau8824->dev, "Acquire semaphore timeout\n");
} else {
ret = down_interruptible(&nau8824->jd_sem);
if (ret < 0)
dev_warn(nau8824->dev, "Acquire semaphore fail\n");
}
return ret;
}
static inline void nau8824_sema_release(struct nau8824 *nau8824)
{
up(&nau8824->jd_sem);
}
static bool nau8824_readable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case NAU8824_REG_ENA_CTRL ... NAU8824_REG_FLL_VCO_RSV:
case NAU8824_REG_JACK_DET_CTRL:
case NAU8824_REG_INTERRUPT_SETTING_1:
case NAU8824_REG_IRQ:
case NAU8824_REG_CLEAR_INT_REG ... NAU8824_REG_VDET_THRESHOLD_4:
case NAU8824_REG_GPIO_SEL:
case NAU8824_REG_PORT0_I2S_PCM_CTRL_1 ... NAU8824_REG_TDM_CTRL:
case NAU8824_REG_ADC_HPF_FILTER ... NAU8824_REG_EQ4_EQ5:
case NAU8824_REG_ADC_CH0_DGAIN_CTRL ... NAU8824_REG_ADC_TO_DAC_ST:
case NAU8824_REG_DRC_KNEE_IP12_ADC_CH01 ... NAU8824_REG_DRC_GAINL_ADC3:
case NAU8824_REG_DRC_KNEE_IP12_DAC ... NAU8824_REG_DRC_GAIN_DAC_CH1:
case NAU8824_REG_CLASSG ... NAU8824_REG_OTP_EFUSE:
case NAU8824_REG_OTPDOUT_1 ... NAU8824_REG_OTPDOUT_2:
case NAU8824_REG_I2C_TIMEOUT:
case NAU8824_REG_I2C_DEVICE_ID ... NAU8824_REG_SAR_ADC_DATA_OUT:
case NAU8824_REG_BIAS_ADJ ... NAU8824_REG_CLASSD_GAIN_2:
case NAU8824_REG_ANALOG_ADC_1 ... NAU8824_REG_ATT_PORT1:
case NAU8824_REG_POWER_UP_CONTROL ... NAU8824_REG_CHARGE_PUMP_INPUT:
return true;
default:
return false;
}
}
static bool nau8824_writeable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case NAU8824_REG_RESET ... NAU8824_REG_FLL_VCO_RSV:
case NAU8824_REG_JACK_DET_CTRL:
case NAU8824_REG_INTERRUPT_SETTING_1:
case NAU8824_REG_CLEAR_INT_REG ... NAU8824_REG_VDET_THRESHOLD_4:
case NAU8824_REG_GPIO_SEL:
case NAU8824_REG_PORT0_I2S_PCM_CTRL_1 ... NAU8824_REG_TDM_CTRL:
case NAU8824_REG_ADC_HPF_FILTER ... NAU8824_REG_EQ4_EQ5:
case NAU8824_REG_ADC_CH0_DGAIN_CTRL ... NAU8824_REG_ADC_TO_DAC_ST:
case NAU8824_REG_DRC_KNEE_IP12_ADC_CH01:
case NAU8824_REG_DRC_KNEE_IP34_ADC_CH01:
case NAU8824_REG_DRC_SLOPE_ADC_CH01:
case NAU8824_REG_DRC_ATKDCY_ADC_CH01:
case NAU8824_REG_DRC_KNEE_IP12_ADC_CH23:
case NAU8824_REG_DRC_KNEE_IP34_ADC_CH23:
case NAU8824_REG_DRC_SLOPE_ADC_CH23:
case NAU8824_REG_DRC_ATKDCY_ADC_CH23:
case NAU8824_REG_DRC_KNEE_IP12_DAC ... NAU8824_REG_DRC_ATKDCY_DAC:
case NAU8824_REG_CLASSG ... NAU8824_REG_OTP_EFUSE:
case NAU8824_REG_I2C_TIMEOUT:
case NAU8824_REG_BIAS_ADJ ... NAU8824_REG_CLASSD_GAIN_2:
case NAU8824_REG_ANALOG_ADC_1 ... NAU8824_REG_ATT_PORT1:
case NAU8824_REG_POWER_UP_CONTROL ... NAU8824_REG_CHARGE_PUMP_CONTROL:
return true;
default:
return false;
}
}
static bool nau8824_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case NAU8824_REG_RESET:
case NAU8824_REG_IRQ ... NAU8824_REG_CLEAR_INT_REG:
case NAU8824_REG_DRC_GAINL_ADC0 ... NAU8824_REG_DRC_GAINL_ADC3:
case NAU8824_REG_DRC_GAIN_DAC_CH0 ... NAU8824_REG_DRC_GAIN_DAC_CH1:
case NAU8824_REG_OTPDOUT_1 ... NAU8824_REG_OTPDOUT_2:
case NAU8824_REG_I2C_DEVICE_ID ... NAU8824_REG_SAR_ADC_DATA_OUT:
case NAU8824_REG_CHARGE_PUMP_INPUT:
return true;
default:
return false;
}
}
static const char * const nau8824_companding[] = {
"Off", "NC", "u-law", "A-law" };
static const struct soc_enum nau8824_companding_adc_enum =
SOC_ENUM_SINGLE(NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 12,
ARRAY_SIZE(nau8824_companding), nau8824_companding);
static const struct soc_enum nau8824_companding_dac_enum =
SOC_ENUM_SINGLE(NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 14,
ARRAY_SIZE(nau8824_companding), nau8824_companding);
static const char * const nau8824_adc_decimation[] = {
"32", "64", "128", "256" };
static const struct soc_enum nau8824_adc_decimation_enum =
SOC_ENUM_SINGLE(NAU8824_REG_ADC_FILTER_CTRL, 0,
ARRAY_SIZE(nau8824_adc_decimation), nau8824_adc_decimation);
static const char * const nau8824_dac_oversampl[] = {
"64", "256", "128", "", "32" };
static const struct soc_enum nau8824_dac_oversampl_enum =
SOC_ENUM_SINGLE(NAU8824_REG_DAC_FILTER_CTRL_1, 0,
ARRAY_SIZE(nau8824_dac_oversampl), nau8824_dac_oversampl);
static const char * const nau8824_input_channel[] = {
"Input CH0", "Input CH1", "Input CH2", "Input CH3" };
static const struct soc_enum nau8824_adc_ch0_enum =
SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH0_DGAIN_CTRL, 9,
ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel);
static const struct soc_enum nau8824_adc_ch1_enum =
SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH1_DGAIN_CTRL, 9,
ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel);
static const struct soc_enum nau8824_adc_ch2_enum =
SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH2_DGAIN_CTRL, 9,
ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel);
static const struct soc_enum nau8824_adc_ch3_enum =
SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH3_DGAIN_CTRL, 9,
ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel);
static const char * const nau8824_tdm_slot[] = {
"Slot 0", "Slot 1", "Slot 2", "Slot 3" };
static const struct soc_enum nau8824_dac_left_sel_enum =
SOC_ENUM_SINGLE(NAU8824_REG_TDM_CTRL, 6,
ARRAY_SIZE(nau8824_tdm_slot), nau8824_tdm_slot);
static const struct soc_enum nau8824_dac_right_sel_enum =
SOC_ENUM_SINGLE(NAU8824_REG_TDM_CTRL, 4,
ARRAY_SIZE(nau8824_tdm_slot), nau8824_tdm_slot);
static const DECLARE_TLV_DB_MINMAX_MUTE(spk_vol_tlv, 0, 2400);
static const DECLARE_TLV_DB_MINMAX(hp_vol_tlv, -3000, 0);
static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 200, 0);
static const DECLARE_TLV_DB_SCALE(dmic_vol_tlv, -12800, 50, 0);
static const struct snd_kcontrol_new nau8824_snd_controls[] = {
SOC_ENUM("ADC Companding", nau8824_companding_adc_enum),
SOC_ENUM("DAC Companding", nau8824_companding_dac_enum),
SOC_ENUM("ADC Decimation Rate", nau8824_adc_decimation_enum),
SOC_ENUM("DAC Oversampling Rate", nau8824_dac_oversampl_enum),
SOC_SINGLE_TLV("Speaker Right DACR Volume",
NAU8824_REG_CLASSD_GAIN_1, 8, 0x1f, 0, spk_vol_tlv),
SOC_SINGLE_TLV("Speaker Left DACL Volume",
NAU8824_REG_CLASSD_GAIN_2, 0, 0x1f, 0, spk_vol_tlv),
SOC_SINGLE_TLV("Speaker Left DACR Volume",
NAU8824_REG_CLASSD_GAIN_1, 0, 0x1f, 0, spk_vol_tlv),
SOC_SINGLE_TLV("Speaker Right DACL Volume",
NAU8824_REG_CLASSD_GAIN_2, 8, 0x1f, 0, spk_vol_tlv),
SOC_SINGLE_TLV("Headphone Right DACR Volume",
NAU8824_REG_ATT_PORT0, 8, 0x1f, 0, hp_vol_tlv),
SOC_SINGLE_TLV("Headphone Left DACL Volume",
NAU8824_REG_ATT_PORT0, 0, 0x1f, 0, hp_vol_tlv),
SOC_SINGLE_TLV("Headphone Right DACL Volume",
NAU8824_REG_ATT_PORT1, 8, 0x1f, 0, hp_vol_tlv),
SOC_SINGLE_TLV("Headphone Left DACR Volume",
NAU8824_REG_ATT_PORT1, 0, 0x1f, 0, hp_vol_tlv),
SOC_SINGLE_TLV("MIC1 Volume", NAU8824_REG_FEPGA_II,
NAU8824_FEPGA_GAINL_SFT, 0x12, 0, mic_vol_tlv),
SOC_SINGLE_TLV("MIC2 Volume", NAU8824_REG_FEPGA_II,
NAU8824_FEPGA_GAINR_SFT, 0x12, 0, mic_vol_tlv),
SOC_SINGLE_TLV("DMIC1 Volume", NAU8824_REG_ADC_CH0_DGAIN_CTRL,
0, 0x164, 0, dmic_vol_tlv),
SOC_SINGLE_TLV("DMIC2 Volume", NAU8824_REG_ADC_CH1_DGAIN_CTRL,
0, 0x164, 0, dmic_vol_tlv),
SOC_SINGLE_TLV("DMIC3 Volume", NAU8824_REG_ADC_CH2_DGAIN_CTRL,
0, 0x164, 0, dmic_vol_tlv),
SOC_SINGLE_TLV("DMIC4 Volume", NAU8824_REG_ADC_CH3_DGAIN_CTRL,
0, 0x164, 0, dmic_vol_tlv),
SOC_ENUM("ADC CH0 Select", nau8824_adc_ch0_enum),
SOC_ENUM("ADC CH1 Select", nau8824_adc_ch1_enum),
SOC_ENUM("ADC CH2 Select", nau8824_adc_ch2_enum),
SOC_ENUM("ADC CH3 Select", nau8824_adc_ch3_enum),
SOC_SINGLE("ADC CH0 TX Switch", NAU8824_REG_TDM_CTRL, 0, 1, 0),
SOC_SINGLE("ADC CH1 TX Switch", NAU8824_REG_TDM_CTRL, 1, 1, 0),
SOC_SINGLE("ADC CH2 TX Switch", NAU8824_REG_TDM_CTRL, 2, 1, 0),
SOC_SINGLE("ADC CH3 TX Switch", NAU8824_REG_TDM_CTRL, 3, 1, 0),
SOC_ENUM("DACL Channel Source", nau8824_dac_left_sel_enum),
SOC_ENUM("DACR Channel Source", nau8824_dac_right_sel_enum),
SOC_SINGLE("DACL LR Mix", NAU8824_REG_DAC_MUTE_CTRL, 0, 1, 0),
SOC_SINGLE("DACR LR Mix", NAU8824_REG_DAC_MUTE_CTRL, 1, 1, 0),
SOC_SINGLE("THD for key media",
NAU8824_REG_VDET_THRESHOLD_1, 8, 0xff, 0),
SOC_SINGLE("THD for key voice command",
NAU8824_REG_VDET_THRESHOLD_1, 0, 0xff, 0),
SOC_SINGLE("THD for key volume up",
NAU8824_REG_VDET_THRESHOLD_2, 8, 0xff, 0),
SOC_SINGLE("THD for key volume down",
NAU8824_REG_VDET_THRESHOLD_2, 0, 0xff, 0),
};
static int nau8824_output_dac_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* Disables the TESTDAC to let DAC signal pass through. */
regmap_update_bits(nau8824->regmap, NAU8824_REG_ENABLE_LO,
NAU8824_TEST_DAC_EN, 0);
break;
case SND_SOC_DAPM_POST_PMD:
regmap_update_bits(nau8824->regmap, NAU8824_REG_ENABLE_LO,
NAU8824_TEST_DAC_EN, NAU8824_TEST_DAC_EN);
break;
default:
return -EINVAL;
}
return 0;
}
static int nau8824_spk_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
regmap_update_bits(nau8824->regmap,
NAU8824_REG_ANALOG_CONTROL_2,
NAU8824_CLASSD_CLAMP_DIS, NAU8824_CLASSD_CLAMP_DIS);
break;
case SND_SOC_DAPM_POST_PMD:
regmap_update_bits(nau8824->regmap,
NAU8824_REG_ANALOG_CONTROL_2,
NAU8824_CLASSD_CLAMP_DIS, 0);
break;
default:
return -EINVAL;
}
return 0;
}
static int nau8824_pump_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
/* Prevent startup click by letting charge pump to ramp up */
msleep(10);
regmap_update_bits(nau8824->regmap,
NAU8824_REG_CHARGE_PUMP_CONTROL,
NAU8824_JAMNODCLOW, NAU8824_JAMNODCLOW);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_update_bits(nau8824->regmap,
NAU8824_REG_CHARGE_PUMP_CONTROL,
NAU8824_JAMNODCLOW, 0);
break;
default:
return -EINVAL;
}
return 0;
}
static int system_clock_control(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *k, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
struct regmap *regmap = nau8824->regmap;
unsigned int value;
bool clk_fll, error;
if (SND_SOC_DAPM_EVENT_OFF(event)) {
dev_dbg(nau8824->dev, "system clock control : POWER OFF\n");
/* Set clock source to disable or internal clock before the
* playback or capture end. Codec needs clock for Jack
* detection and button press if jack inserted; otherwise,
* the clock should be closed.
*/
if (nau8824_is_jack_inserted(nau8824)) {
nau8824_config_sysclk(nau8824,
NAU8824_CLK_INTERNAL, 0);
} else {
nau8824_config_sysclk(nau8824, NAU8824_CLK_DIS, 0);
}
} else {
dev_dbg(nau8824->dev, "system clock control : POWER ON\n");
/* Check the clock source setting is proper or not
* no matter the source is from FLL or MCLK.
*/
regmap_read(regmap, NAU8824_REG_FLL1, &value);
clk_fll = value & NAU8824_FLL_RATIO_MASK;
/* It's error to use internal clock when playback */
regmap_read(regmap, NAU8824_REG_FLL6, &value);
error = value & NAU8824_DCO_EN;
if (!error) {
/* Check error depending on source is FLL or MCLK. */
regmap_read(regmap, NAU8824_REG_CLK_DIVIDER, &value);
if (clk_fll)
error = !(value & NAU8824_CLK_SRC_VCO);
else
error = value & NAU8824_CLK_SRC_VCO;
}
/* Recover the clock source setting if error. */
if (error) {
if (clk_fll) {
regmap_update_bits(regmap,
NAU8824_REG_FLL6, NAU8824_DCO_EN, 0);
regmap_update_bits(regmap,
NAU8824_REG_CLK_DIVIDER,
NAU8824_CLK_SRC_MASK,
NAU8824_CLK_SRC_VCO);
} else {
nau8824_config_sysclk(nau8824,
NAU8824_CLK_MCLK, 0);
}
}
}
return 0;
}
static int dmic_clock_control(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *k, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
int src;
/* The DMIC clock is gotten from system clock (256fs) divided by
* DMIC_SRC (1, 2, 4, 8, 16, 32). The clock has to be equal or
* less than 3.072 MHz.
*/
for (src = 0; src < 5; src++) {
if ((0x1 << (8 - src)) * nau8824->fs <= DMIC_CLK)
break;
}
dev_dbg(nau8824->dev, "dmic src %d for mclk %d\n", src, nau8824->fs * 256);
regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER,
NAU8824_CLK_DMIC_SRC_MASK, (src << NAU8824_CLK_DMIC_SRC_SFT));
return 0;
}
static const struct snd_kcontrol_new nau8824_adc_ch0_dmic =
SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL,
NAU8824_ADC_CH0_DMIC_SFT, 1, 0);
static const struct snd_kcontrol_new nau8824_adc_ch1_dmic =
SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL,
NAU8824_ADC_CH1_DMIC_SFT, 1, 0);
static const struct snd_kcontrol_new nau8824_adc_ch2_dmic =
SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL,
NAU8824_ADC_CH2_DMIC_SFT, 1, 0);
static const struct snd_kcontrol_new nau8824_adc_ch3_dmic =
SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL,
NAU8824_ADC_CH3_DMIC_SFT, 1, 0);
static const struct snd_kcontrol_new nau8824_adc_left_mixer[] = {
SOC_DAPM_SINGLE("MIC Switch", NAU8824_REG_FEPGA,
NAU8824_FEPGA_MODEL_MIC1_SFT, 1, 0),
SOC_DAPM_SINGLE("HSMIC Switch", NAU8824_REG_FEPGA,
NAU8824_FEPGA_MODEL_HSMIC_SFT, 1, 0),
};
static const struct snd_kcontrol_new nau8824_adc_right_mixer[] = {
SOC_DAPM_SINGLE("MIC Switch", NAU8824_REG_FEPGA,
NAU8824_FEPGA_MODER_MIC2_SFT, 1, 0),
SOC_DAPM_SINGLE("HSMIC Switch", NAU8824_REG_FEPGA,
NAU8824_FEPGA_MODER_HSMIC_SFT, 1, 0),
};
static const struct snd_kcontrol_new nau8824_hp_left_mixer[] = {
SOC_DAPM_SINGLE("DAC Right Switch", NAU8824_REG_ENABLE_LO,
NAU8824_DACR_HPL_EN_SFT, 1, 0),
SOC_DAPM_SINGLE("DAC Left Switch", NAU8824_REG_ENABLE_LO,
NAU8824_DACL_HPL_EN_SFT, 1, 0),
};
static const struct snd_kcontrol_new nau8824_hp_right_mixer[] = {
SOC_DAPM_SINGLE("DAC Left Switch", NAU8824_REG_ENABLE_LO,
NAU8824_DACL_HPR_EN_SFT, 1, 0),
SOC_DAPM_SINGLE("DAC Right Switch", NAU8824_REG_ENABLE_LO,
NAU8824_DACR_HPR_EN_SFT, 1, 0),
};
static const char * const nau8824_dac_src[] = { "DACL", "DACR" };
static SOC_ENUM_SINGLE_DECL(
nau8824_dacl_enum, NAU8824_REG_DAC_CH0_DGAIN_CTRL,
NAU8824_DAC_CH0_SEL_SFT, nau8824_dac_src);
static SOC_ENUM_SINGLE_DECL(
nau8824_dacr_enum, NAU8824_REG_DAC_CH1_DGAIN_CTRL,
NAU8824_DAC_CH1_SEL_SFT, nau8824_dac_src);
static const struct snd_kcontrol_new nau8824_dacl_mux =
SOC_DAPM_ENUM("DACL Source", nau8824_dacl_enum);
static const struct snd_kcontrol_new nau8824_dacr_mux =
SOC_DAPM_ENUM("DACR Source", nau8824_dacr_enum);
static const struct snd_soc_dapm_widget nau8824_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("System Clock", SND_SOC_NOPM, 0, 0,
system_clock_control, SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_INPUT("HSMIC1"),
SND_SOC_DAPM_INPUT("HSMIC2"),
SND_SOC_DAPM_INPUT("MIC1"),
SND_SOC_DAPM_INPUT("MIC2"),
SND_SOC_DAPM_INPUT("DMIC1"),
SND_SOC_DAPM_INPUT("DMIC2"),
SND_SOC_DAPM_INPUT("DMIC3"),
SND_SOC_DAPM_INPUT("DMIC4"),
SND_SOC_DAPM_SUPPLY("SAR", NAU8824_REG_SAR_ADC,
NAU8824_SAR_ADC_EN_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS", NAU8824_REG_MIC_BIAS,
NAU8824_MICBIAS_POWERUP_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DMIC12 Power", NAU8824_REG_BIAS_ADJ,
NAU8824_DMIC1_EN_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DMIC34 Power", NAU8824_REG_BIAS_ADJ,
NAU8824_DMIC2_EN_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DMIC Clock", SND_SOC_NOPM, 0, 0,
dmic_clock_control, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_SWITCH("DMIC1 Enable", SND_SOC_NOPM,
0, 0, &nau8824_adc_ch0_dmic),
SND_SOC_DAPM_SWITCH("DMIC2 Enable", SND_SOC_NOPM,
0, 0, &nau8824_adc_ch1_dmic),
SND_SOC_DAPM_SWITCH("DMIC3 Enable", SND_SOC_NOPM,
0, 0, &nau8824_adc_ch2_dmic),
SND_SOC_DAPM_SWITCH("DMIC4 Enable", SND_SOC_NOPM,
0, 0, &nau8824_adc_ch3_dmic),
SND_SOC_DAPM_MIXER("Left ADC", NAU8824_REG_POWER_UP_CONTROL,
12, 0, nau8824_adc_left_mixer,
ARRAY_SIZE(nau8824_adc_left_mixer)),
SND_SOC_DAPM_MIXER("Right ADC", NAU8824_REG_POWER_UP_CONTROL,
13, 0, nau8824_adc_right_mixer,
ARRAY_SIZE(nau8824_adc_right_mixer)),
SND_SOC_DAPM_ADC("ADCL", NULL, NAU8824_REG_ANALOG_ADC_2,
NAU8824_ADCL_EN_SFT, 0),
SND_SOC_DAPM_ADC("ADCR", NULL, NAU8824_REG_ANALOG_ADC_2,
NAU8824_ADCR_EN_SFT, 0),
SND_SOC_DAPM_AIF_OUT("AIFTX", "Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("AIFRX", "Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("DACL", NULL, NAU8824_REG_RDAC,
NAU8824_DACL_EN_SFT, 0),
SND_SOC_DAPM_SUPPLY("DACL Clock", NAU8824_REG_RDAC,
NAU8824_DACL_CLK_SFT, 0, NULL, 0),
SND_SOC_DAPM_DAC("DACR", NULL, NAU8824_REG_RDAC,
NAU8824_DACR_EN_SFT, 0),
SND_SOC_DAPM_SUPPLY("DACR Clock", NAU8824_REG_RDAC,
NAU8824_DACR_CLK_SFT, 0, NULL, 0),
SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &nau8824_dacl_mux),
SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &nau8824_dacr_mux),
SND_SOC_DAPM_PGA_S("Output DACL", 0, NAU8824_REG_CHARGE_PUMP_CONTROL,
8, 1, nau8824_output_dac_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA_S("Output DACR", 0, NAU8824_REG_CHARGE_PUMP_CONTROL,
9, 1, nau8824_output_dac_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA_S("ClassD", 0, NAU8824_REG_CLASSD_GAIN_1,
NAU8824_CLASSD_EN_SFT, 0, nau8824_spk_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MIXER("Left Headphone", NAU8824_REG_CLASSG,
NAU8824_CLASSG_LDAC_EN_SFT, 0, nau8824_hp_left_mixer,
ARRAY_SIZE(nau8824_hp_left_mixer)),
SND_SOC_DAPM_MIXER("Right Headphone", NAU8824_REG_CLASSG,
NAU8824_CLASSG_RDAC_EN_SFT, 0, nau8824_hp_right_mixer,
ARRAY_SIZE(nau8824_hp_right_mixer)),
SND_SOC_DAPM_PGA_S("Charge Pump", 1, NAU8824_REG_CHARGE_PUMP_CONTROL,
NAU8824_CHARGE_PUMP_EN_SFT, 0, nau8824_pump_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_PGA("Output Driver L",
NAU8824_REG_POWER_UP_CONTROL, 3, 0, NULL, 0),
SND_SOC_DAPM_PGA("Output Driver R",
NAU8824_REG_POWER_UP_CONTROL, 2, 0, NULL, 0),
SND_SOC_DAPM_PGA("Main Driver L",
NAU8824_REG_POWER_UP_CONTROL, 1, 0, NULL, 0),
SND_SOC_DAPM_PGA("Main Driver R",
NAU8824_REG_POWER_UP_CONTROL, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("HP Boost Driver", NAU8824_REG_BOOST,
NAU8824_HP_BOOST_DIS_SFT, 1, NULL, 0),
SND_SOC_DAPM_PGA("Class G", NAU8824_REG_CLASSG,
NAU8824_CLASSG_EN_SFT, 0, NULL, 0),
SND_SOC_DAPM_OUTPUT("SPKOUTL"),
SND_SOC_DAPM_OUTPUT("SPKOUTR"),
SND_SOC_DAPM_OUTPUT("HPOL"),
SND_SOC_DAPM_OUTPUT("HPOR"),
};
static const struct snd_soc_dapm_route nau8824_dapm_routes[] = {
{"DMIC1 Enable", "Switch", "DMIC1"},
{"DMIC2 Enable", "Switch", "DMIC2"},
{"DMIC3 Enable", "Switch", "DMIC3"},
{"DMIC4 Enable", "Switch", "DMIC4"},
{"DMIC1", NULL, "DMIC12 Power"},
{"DMIC2", NULL, "DMIC12 Power"},
{"DMIC3", NULL, "DMIC34 Power"},
{"DMIC4", NULL, "DMIC34 Power"},
{"DMIC12 Power", NULL, "DMIC Clock"},
{"DMIC34 Power", NULL, "DMIC Clock"},
{"Left ADC", "MIC Switch", "MIC1"},
{"Left ADC", "HSMIC Switch", "HSMIC1"},
{"Right ADC", "MIC Switch", "MIC2"},
{"Right ADC", "HSMIC Switch", "HSMIC2"},
{"ADCL", NULL, "Left ADC"},
{"ADCR", NULL, "Right ADC"},
{"AIFTX", NULL, "MICBIAS"},
{"AIFTX", NULL, "ADCL"},
{"AIFTX", NULL, "ADCR"},
{"AIFTX", NULL, "DMIC1 Enable"},
{"AIFTX", NULL, "DMIC2 Enable"},
{"AIFTX", NULL, "DMIC3 Enable"},
{"AIFTX", NULL, "DMIC4 Enable"},
{"AIFTX", NULL, "System Clock"},
{"AIFRX", NULL, "System Clock"},
{"DACL", NULL, "AIFRX"},
{"DACL", NULL, "DACL Clock"},
{"DACR", NULL, "AIFRX"},
{"DACR", NULL, "DACR Clock"},
{"DACL Mux", "DACL", "DACL"},
{"DACL Mux", "DACR", "DACR"},
{"DACR Mux", "DACL", "DACL"},
{"DACR Mux", "DACR", "DACR"},
{"Output DACL", NULL, "DACL Mux"},
{"Output DACR", NULL, "DACR Mux"},
{"ClassD", NULL, "Output DACL"},
{"ClassD", NULL, "Output DACR"},
{"Left Headphone", "DAC Left Switch", "Output DACL"},
{"Left Headphone", "DAC Right Switch", "Output DACR"},
{"Right Headphone", "DAC Left Switch", "Output DACL"},
{"Right Headphone", "DAC Right Switch", "Output DACR"},
{"Charge Pump", NULL, "Left Headphone"},
{"Charge Pump", NULL, "Right Headphone"},
{"Output Driver L", NULL, "Charge Pump"},
{"Output Driver R", NULL, "Charge Pump"},
{"Main Driver L", NULL, "Output Driver L"},
{"Main Driver R", NULL, "Output Driver R"},
{"Class G", NULL, "Main Driver L"},
{"Class G", NULL, "Main Driver R"},
{"HP Boost Driver", NULL, "Class G"},
{"SPKOUTL", NULL, "ClassD"},
{"SPKOUTR", NULL, "ClassD"},
{"HPOL", NULL, "HP Boost Driver"},
{"HPOR", NULL, "HP Boost Driver"},
};
static bool nau8824_is_jack_inserted(struct nau8824 *nau8824)
{
struct snd_soc_jack *jack = nau8824->jack;
bool insert = false;
if (nau8824->irq && jack)
insert = jack->status & SND_JACK_HEADPHONE;
return insert;
}
static void nau8824_int_status_clear_all(struct regmap *regmap)
{
int active_irq, clear_irq, i;
/* Reset the intrruption status from rightmost bit if the corres-
* ponding irq event occurs.
*/
regmap_read(regmap, NAU8824_REG_IRQ, &active_irq);
for (i = 0; i < NAU8824_REG_DATA_LEN; i++) {
clear_irq = (0x1 << i);
if (active_irq & clear_irq)
regmap_write(regmap,
NAU8824_REG_CLEAR_INT_REG, clear_irq);
}
}
static void nau8824_dapm_disable_pin(struct nau8824 *nau8824, const char *pin)
{
struct snd_soc_dapm_context *dapm = nau8824->dapm;
const char *prefix = dapm->component->name_prefix;
char prefixed_pin[80];
if (prefix) {
snprintf(prefixed_pin, sizeof(prefixed_pin), "%s %s",
prefix, pin);
snd_soc_dapm_disable_pin(dapm, prefixed_pin);
} else {
snd_soc_dapm_disable_pin(dapm, pin);
}
}
static void nau8824_dapm_enable_pin(struct nau8824 *nau8824, const char *pin)
{
struct snd_soc_dapm_context *dapm = nau8824->dapm;
const char *prefix = dapm->component->name_prefix;
char prefixed_pin[80];
if (prefix) {
snprintf(prefixed_pin, sizeof(prefixed_pin), "%s %s",
prefix, pin);
snd_soc_dapm_force_enable_pin(dapm, prefixed_pin);
} else {
snd_soc_dapm_force_enable_pin(dapm, pin);
}
}
static void nau8824_eject_jack(struct nau8824 *nau8824)
{
struct snd_soc_dapm_context *dapm = nau8824->dapm;
struct regmap *regmap = nau8824->regmap;
/* Clear all interruption status */
nau8824_int_status_clear_all(regmap);
nau8824_dapm_disable_pin(nau8824, "SAR");
nau8824_dapm_disable_pin(nau8824, "MICBIAS");
snd_soc_dapm_sync(dapm);
/* Enable the insertion interruption, disable the ejection
* interruption, and then bypass de-bounce circuit.
*/
regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING,
NAU8824_IRQ_KEY_RELEASE_DIS | NAU8824_IRQ_KEY_SHORT_PRESS_DIS |
NAU8824_IRQ_EJECT_DIS | NAU8824_IRQ_INSERT_DIS,
NAU8824_IRQ_KEY_RELEASE_DIS | NAU8824_IRQ_KEY_SHORT_PRESS_DIS |
NAU8824_IRQ_EJECT_DIS);
regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING_1,
NAU8824_IRQ_INSERT_EN | NAU8824_IRQ_EJECT_EN,
NAU8824_IRQ_INSERT_EN);
regmap_update_bits(regmap, NAU8824_REG_ENA_CTRL,
NAU8824_JD_SLEEP_MODE, NAU8824_JD_SLEEP_MODE);
/* Close clock for jack type detection at manual mode */
if (dapm->bias_level < SND_SOC_BIAS_PREPARE)
nau8824_config_sysclk(nau8824, NAU8824_CLK_DIS, 0);
}
static void nau8824_jdet_work(struct work_struct *work)
{
struct nau8824 *nau8824 = container_of(
work, struct nau8824, jdet_work);
struct snd_soc_dapm_context *dapm = nau8824->dapm;
struct regmap *regmap = nau8824->regmap;
int adc_value, event = 0, event_mask = 0;
nau8824_dapm_enable_pin(nau8824, "MICBIAS");
nau8824_dapm_enable_pin(nau8824, "SAR");
snd_soc_dapm_sync(dapm);
msleep(100);
regmap_read(regmap, NAU8824_REG_SAR_ADC_DATA_OUT, &adc_value);
adc_value = adc_value & NAU8824_SAR_ADC_DATA_MASK;
dev_dbg(nau8824->dev, "SAR ADC data 0x%02x\n", adc_value);
if (adc_value < HEADSET_SARADC_THD) {
event |= SND_JACK_HEADPHONE;
nau8824_dapm_disable_pin(nau8824, "SAR");
nau8824_dapm_disable_pin(nau8824, "MICBIAS");
snd_soc_dapm_sync(dapm);
} else {
event |= SND_JACK_HEADSET;
}
event_mask |= SND_JACK_HEADSET;
snd_soc_jack_report(nau8824->jack, event, event_mask);
/* Enable short key press and release interruption. */
regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING,
NAU8824_IRQ_KEY_RELEASE_DIS |
NAU8824_IRQ_KEY_SHORT_PRESS_DIS, 0);
nau8824_sema_release(nau8824);
}
static void nau8824_setup_auto_irq(struct nau8824 *nau8824)
{
struct regmap *regmap = nau8824->regmap;
/* Enable jack ejection interruption. */
regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING_1,
NAU8824_IRQ_INSERT_EN | NAU8824_IRQ_EJECT_EN,
NAU8824_IRQ_EJECT_EN);
regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING,
NAU8824_IRQ_EJECT_DIS, 0);
/* Enable internal VCO needed for interruptions */
if (nau8824->dapm->bias_level < SND_SOC_BIAS_PREPARE)
nau8824_config_sysclk(nau8824, NAU8824_CLK_INTERNAL, 0);
regmap_update_bits(regmap, NAU8824_REG_ENA_CTRL,
NAU8824_JD_SLEEP_MODE, 0);
}
static int nau8824_button_decode(int value)
{
int buttons = 0;
/* The chip supports up to 8 buttons, but ALSA defines
* only 6 buttons.
*/
if (value & BIT(0))
buttons |= SND_JACK_BTN_0;
if (value & BIT(1))
buttons |= SND_JACK_BTN_1;
if (value & BIT(2))
buttons |= SND_JACK_BTN_2;
if (value & BIT(3))
buttons |= SND_JACK_BTN_3;
if (value & BIT(4))
buttons |= SND_JACK_BTN_4;
if (value & BIT(5))
buttons |= SND_JACK_BTN_5;
return buttons;
}
#define NAU8824_BUTTONS (SND_JACK_BTN_0 | SND_JACK_BTN_1 | \
SND_JACK_BTN_2 | SND_JACK_BTN_3)
static irqreturn_t nau8824_interrupt(int irq, void *data)
{
struct nau8824 *nau8824 = (struct nau8824 *)data;
struct regmap *regmap = nau8824->regmap;
int active_irq, clear_irq = 0, event = 0, event_mask = 0;
if (regmap_read(regmap, NAU8824_REG_IRQ, &active_irq)) {
dev_err(nau8824->dev, "failed to read irq status\n");
return IRQ_NONE;
}
dev_dbg(nau8824->dev, "IRQ %x\n", active_irq);
if (active_irq & NAU8824_JACK_EJECTION_DETECTED) {
nau8824_eject_jack(nau8824);
event_mask |= SND_JACK_HEADSET;
clear_irq = NAU8824_JACK_EJECTION_DETECTED;
/* release semaphore held after resume,
* and cancel jack detection
*/
nau8824_sema_release(nau8824);
cancel_work_sync(&nau8824->jdet_work);
} else if (active_irq & NAU8824_KEY_SHORT_PRESS_IRQ) {
int key_status, button_pressed;
regmap_read(regmap, NAU8824_REG_CLEAR_INT_REG,
&key_status);
/* lower 8 bits of the register are for pressed keys */
button_pressed = nau8824_button_decode(key_status);