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rt5677.c
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// SPDX-License-Identifier: GPL-2.0-only
/*
* rt5677.c -- RT5677 ALSA SoC audio codec driver
*
* Copyright 2013 Realtek Semiconductor Corp.
* Author: Oder Chiou <[email protected]>
*/
#include <linux/acpi.h>
#include <linux/fs.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/regmap.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/firmware.h>
#include <linux/of_device.h>
#include <linux/property.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/irqdomain.h>
#include <linux/workqueue.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "rl6231.h"
#include "rt5677.h"
#include "rt5677-spi.h"
#define RT5677_DEVICE_ID 0x6327
/* Register controlling boot vector */
#define RT5677_DSP_BOOT_VECTOR 0x1801f090
#define RT5677_MODEL_ADDR 0x5FFC9800
#define RT5677_PR_RANGE_BASE (0xff + 1)
#define RT5677_PR_SPACING 0x100
#define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING))
static const struct regmap_range_cfg rt5677_ranges[] = {
{
.name = "PR",
.range_min = RT5677_PR_BASE,
.range_max = RT5677_PR_BASE + 0xfd,
.selector_reg = RT5677_PRIV_INDEX,
.selector_mask = 0xff,
.selector_shift = 0x0,
.window_start = RT5677_PRIV_DATA,
.window_len = 0x1,
},
};
static const struct reg_sequence init_list[] = {
{RT5677_ASRC_12, 0x0018},
{RT5677_PR_BASE + 0x3d, 0x364d},
{RT5677_PR_BASE + 0x17, 0x4fc0},
{RT5677_PR_BASE + 0x13, 0x0312},
{RT5677_PR_BASE + 0x1e, 0x0000},
{RT5677_PR_BASE + 0x12, 0x0eaa},
{RT5677_PR_BASE + 0x14, 0x018a},
{RT5677_PR_BASE + 0x15, 0x0490},
{RT5677_PR_BASE + 0x38, 0x0f71},
{RT5677_PR_BASE + 0x39, 0x0f71},
};
#define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list)
static const struct reg_default rt5677_reg[] = {
{RT5677_RESET , 0x0000},
{RT5677_LOUT1 , 0xa800},
{RT5677_IN1 , 0x0000},
{RT5677_MICBIAS , 0x0000},
{RT5677_SLIMBUS_PARAM , 0x0000},
{RT5677_SLIMBUS_RX , 0x0000},
{RT5677_SLIMBUS_CTRL , 0x0000},
{RT5677_SIDETONE_CTRL , 0x000b},
{RT5677_ANA_DAC1_2_3_SRC , 0x0000},
{RT5677_IF_DSP_DAC3_4_MIXER , 0x1111},
{RT5677_DAC4_DIG_VOL , 0xafaf},
{RT5677_DAC3_DIG_VOL , 0xafaf},
{RT5677_DAC1_DIG_VOL , 0xafaf},
{RT5677_DAC2_DIG_VOL , 0xafaf},
{RT5677_IF_DSP_DAC2_MIXER , 0x0011},
{RT5677_STO1_ADC_DIG_VOL , 0x2f2f},
{RT5677_MONO_ADC_DIG_VOL , 0x2f2f},
{RT5677_STO1_2_ADC_BST , 0x0000},
{RT5677_STO2_ADC_DIG_VOL , 0x2f2f},
{RT5677_ADC_BST_CTRL2 , 0x0000},
{RT5677_STO3_4_ADC_BST , 0x0000},
{RT5677_STO3_ADC_DIG_VOL , 0x2f2f},
{RT5677_STO4_ADC_DIG_VOL , 0x2f2f},
{RT5677_STO4_ADC_MIXER , 0xd4c0},
{RT5677_STO3_ADC_MIXER , 0xd4c0},
{RT5677_STO2_ADC_MIXER , 0xd4c0},
{RT5677_STO1_ADC_MIXER , 0xd4c0},
{RT5677_MONO_ADC_MIXER , 0xd4d1},
{RT5677_ADC_IF_DSP_DAC1_MIXER , 0x8080},
{RT5677_STO1_DAC_MIXER , 0xaaaa},
{RT5677_MONO_DAC_MIXER , 0xaaaa},
{RT5677_DD1_MIXER , 0xaaaa},
{RT5677_DD2_MIXER , 0xaaaa},
{RT5677_IF3_DATA , 0x0000},
{RT5677_IF4_DATA , 0x0000},
{RT5677_PDM_OUT_CTRL , 0x8888},
{RT5677_PDM_DATA_CTRL1 , 0x0000},
{RT5677_PDM_DATA_CTRL2 , 0x0000},
{RT5677_PDM1_DATA_CTRL2 , 0x0000},
{RT5677_PDM1_DATA_CTRL3 , 0x0000},
{RT5677_PDM1_DATA_CTRL4 , 0x0000},
{RT5677_PDM2_DATA_CTRL2 , 0x0000},
{RT5677_PDM2_DATA_CTRL3 , 0x0000},
{RT5677_PDM2_DATA_CTRL4 , 0x0000},
{RT5677_TDM1_CTRL1 , 0x0300},
{RT5677_TDM1_CTRL2 , 0x0000},
{RT5677_TDM1_CTRL3 , 0x4000},
{RT5677_TDM1_CTRL4 , 0x0123},
{RT5677_TDM1_CTRL5 , 0x4567},
{RT5677_TDM2_CTRL1 , 0x0300},
{RT5677_TDM2_CTRL2 , 0x0000},
{RT5677_TDM2_CTRL3 , 0x4000},
{RT5677_TDM2_CTRL4 , 0x0123},
{RT5677_TDM2_CTRL5 , 0x4567},
{RT5677_I2C_MASTER_CTRL1 , 0x0001},
{RT5677_I2C_MASTER_CTRL2 , 0x0000},
{RT5677_I2C_MASTER_CTRL3 , 0x0000},
{RT5677_I2C_MASTER_CTRL4 , 0x0000},
{RT5677_I2C_MASTER_CTRL5 , 0x0000},
{RT5677_I2C_MASTER_CTRL6 , 0x0000},
{RT5677_I2C_MASTER_CTRL7 , 0x0000},
{RT5677_I2C_MASTER_CTRL8 , 0x0000},
{RT5677_DMIC_CTRL1 , 0x1505},
{RT5677_DMIC_CTRL2 , 0x0055},
{RT5677_HAP_GENE_CTRL1 , 0x0111},
{RT5677_HAP_GENE_CTRL2 , 0x0064},
{RT5677_HAP_GENE_CTRL3 , 0xef0e},
{RT5677_HAP_GENE_CTRL4 , 0xf0f0},
{RT5677_HAP_GENE_CTRL5 , 0xef0e},
{RT5677_HAP_GENE_CTRL6 , 0xf0f0},
{RT5677_HAP_GENE_CTRL7 , 0xef0e},
{RT5677_HAP_GENE_CTRL8 , 0xf0f0},
{RT5677_HAP_GENE_CTRL9 , 0xf000},
{RT5677_HAP_GENE_CTRL10 , 0x0000},
{RT5677_PWR_DIG1 , 0x0000},
{RT5677_PWR_DIG2 , 0x0000},
{RT5677_PWR_ANLG1 , 0x0055},
{RT5677_PWR_ANLG2 , 0x0000},
{RT5677_PWR_DSP1 , 0x0001},
{RT5677_PWR_DSP_ST , 0x0000},
{RT5677_PWR_DSP2 , 0x0000},
{RT5677_ADC_DAC_HPF_CTRL1 , 0x0e00},
{RT5677_PRIV_INDEX , 0x0000},
{RT5677_PRIV_DATA , 0x0000},
{RT5677_I2S4_SDP , 0x8000},
{RT5677_I2S1_SDP , 0x8000},
{RT5677_I2S2_SDP , 0x8000},
{RT5677_I2S3_SDP , 0x8000},
{RT5677_CLK_TREE_CTRL1 , 0x1111},
{RT5677_CLK_TREE_CTRL2 , 0x1111},
{RT5677_CLK_TREE_CTRL3 , 0x0000},
{RT5677_PLL1_CTRL1 , 0x0000},
{RT5677_PLL1_CTRL2 , 0x0000},
{RT5677_PLL2_CTRL1 , 0x0c60},
{RT5677_PLL2_CTRL2 , 0x2000},
{RT5677_GLB_CLK1 , 0x0000},
{RT5677_GLB_CLK2 , 0x0000},
{RT5677_ASRC_1 , 0x0000},
{RT5677_ASRC_2 , 0x0000},
{RT5677_ASRC_3 , 0x0000},
{RT5677_ASRC_4 , 0x0000},
{RT5677_ASRC_5 , 0x0000},
{RT5677_ASRC_6 , 0x0000},
{RT5677_ASRC_7 , 0x0000},
{RT5677_ASRC_8 , 0x0000},
{RT5677_ASRC_9 , 0x0000},
{RT5677_ASRC_10 , 0x0000},
{RT5677_ASRC_11 , 0x0000},
{RT5677_ASRC_12 , 0x0018},
{RT5677_ASRC_13 , 0x0000},
{RT5677_ASRC_14 , 0x0000},
{RT5677_ASRC_15 , 0x0000},
{RT5677_ASRC_16 , 0x0000},
{RT5677_ASRC_17 , 0x0000},
{RT5677_ASRC_18 , 0x0000},
{RT5677_ASRC_19 , 0x0000},
{RT5677_ASRC_20 , 0x0000},
{RT5677_ASRC_21 , 0x000c},
{RT5677_ASRC_22 , 0x0000},
{RT5677_ASRC_23 , 0x0000},
{RT5677_VAD_CTRL1 , 0x2184},
{RT5677_VAD_CTRL2 , 0x010a},
{RT5677_VAD_CTRL3 , 0x0aea},
{RT5677_VAD_CTRL4 , 0x000c},
{RT5677_VAD_CTRL5 , 0x0000},
{RT5677_DSP_INB_CTRL1 , 0x0000},
{RT5677_DSP_INB_CTRL2 , 0x0000},
{RT5677_DSP_IN_OUTB_CTRL , 0x0000},
{RT5677_DSP_OUTB0_1_DIG_VOL , 0x2f2f},
{RT5677_DSP_OUTB2_3_DIG_VOL , 0x2f2f},
{RT5677_DSP_OUTB4_5_DIG_VOL , 0x2f2f},
{RT5677_DSP_OUTB6_7_DIG_VOL , 0x2f2f},
{RT5677_ADC_EQ_CTRL1 , 0x6000},
{RT5677_ADC_EQ_CTRL2 , 0x0000},
{RT5677_EQ_CTRL1 , 0xc000},
{RT5677_EQ_CTRL2 , 0x0000},
{RT5677_EQ_CTRL3 , 0x0000},
{RT5677_SOFT_VOL_ZERO_CROSS1 , 0x0009},
{RT5677_JD_CTRL1 , 0x0000},
{RT5677_JD_CTRL2 , 0x0000},
{RT5677_JD_CTRL3 , 0x0000},
{RT5677_IRQ_CTRL1 , 0x0000},
{RT5677_IRQ_CTRL2 , 0x0000},
{RT5677_GPIO_ST , 0x0000},
{RT5677_GPIO_CTRL1 , 0x0000},
{RT5677_GPIO_CTRL2 , 0x0000},
{RT5677_GPIO_CTRL3 , 0x0000},
{RT5677_STO1_ADC_HI_FILTER1 , 0xb320},
{RT5677_STO1_ADC_HI_FILTER2 , 0x0000},
{RT5677_MONO_ADC_HI_FILTER1 , 0xb300},
{RT5677_MONO_ADC_HI_FILTER2 , 0x0000},
{RT5677_STO2_ADC_HI_FILTER1 , 0xb300},
{RT5677_STO2_ADC_HI_FILTER2 , 0x0000},
{RT5677_STO3_ADC_HI_FILTER1 , 0xb300},
{RT5677_STO3_ADC_HI_FILTER2 , 0x0000},
{RT5677_STO4_ADC_HI_FILTER1 , 0xb300},
{RT5677_STO4_ADC_HI_FILTER2 , 0x0000},
{RT5677_MB_DRC_CTRL1 , 0x0f20},
{RT5677_DRC1_CTRL1 , 0x001f},
{RT5677_DRC1_CTRL2 , 0x020c},
{RT5677_DRC1_CTRL3 , 0x1f00},
{RT5677_DRC1_CTRL4 , 0x0000},
{RT5677_DRC1_CTRL5 , 0x0000},
{RT5677_DRC1_CTRL6 , 0x0029},
{RT5677_DRC2_CTRL1 , 0x001f},
{RT5677_DRC2_CTRL2 , 0x020c},
{RT5677_DRC2_CTRL3 , 0x1f00},
{RT5677_DRC2_CTRL4 , 0x0000},
{RT5677_DRC2_CTRL5 , 0x0000},
{RT5677_DRC2_CTRL6 , 0x0029},
{RT5677_DRC1_HL_CTRL1 , 0x8000},
{RT5677_DRC1_HL_CTRL2 , 0x0200},
{RT5677_DRC2_HL_CTRL1 , 0x8000},
{RT5677_DRC2_HL_CTRL2 , 0x0200},
{RT5677_DSP_INB1_SRC_CTRL1 , 0x5800},
{RT5677_DSP_INB1_SRC_CTRL2 , 0x0000},
{RT5677_DSP_INB1_SRC_CTRL3 , 0x0000},
{RT5677_DSP_INB1_SRC_CTRL4 , 0x0800},
{RT5677_DSP_INB2_SRC_CTRL1 , 0x5800},
{RT5677_DSP_INB2_SRC_CTRL2 , 0x0000},
{RT5677_DSP_INB2_SRC_CTRL3 , 0x0000},
{RT5677_DSP_INB2_SRC_CTRL4 , 0x0800},
{RT5677_DSP_INB3_SRC_CTRL1 , 0x5800},
{RT5677_DSP_INB3_SRC_CTRL2 , 0x0000},
{RT5677_DSP_INB3_SRC_CTRL3 , 0x0000},
{RT5677_DSP_INB3_SRC_CTRL4 , 0x0800},
{RT5677_DSP_OUTB1_SRC_CTRL1 , 0x5800},
{RT5677_DSP_OUTB1_SRC_CTRL2 , 0x0000},
{RT5677_DSP_OUTB1_SRC_CTRL3 , 0x0000},
{RT5677_DSP_OUTB1_SRC_CTRL4 , 0x0800},
{RT5677_DSP_OUTB2_SRC_CTRL1 , 0x5800},
{RT5677_DSP_OUTB2_SRC_CTRL2 , 0x0000},
{RT5677_DSP_OUTB2_SRC_CTRL3 , 0x0000},
{RT5677_DSP_OUTB2_SRC_CTRL4 , 0x0800},
{RT5677_DSP_OUTB_0123_MIXER_CTRL, 0xfefe},
{RT5677_DSP_OUTB_45_MIXER_CTRL , 0xfefe},
{RT5677_DSP_OUTB_67_MIXER_CTRL , 0xfefe},
{RT5677_DIG_MISC , 0x0000},
{RT5677_GEN_CTRL1 , 0x0000},
{RT5677_GEN_CTRL2 , 0x0000},
{RT5677_VENDOR_ID , 0x0000},
{RT5677_VENDOR_ID1 , 0x10ec},
{RT5677_VENDOR_ID2 , 0x6327},
};
static bool rt5677_volatile_register(struct device *dev, unsigned int reg)
{
int i;
for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
if (reg >= rt5677_ranges[i].range_min &&
reg <= rt5677_ranges[i].range_max) {
return true;
}
}
switch (reg) {
case RT5677_RESET:
case RT5677_SLIMBUS_PARAM:
case RT5677_PDM_DATA_CTRL1:
case RT5677_PDM_DATA_CTRL2:
case RT5677_PDM1_DATA_CTRL4:
case RT5677_PDM2_DATA_CTRL4:
case RT5677_I2C_MASTER_CTRL1:
case RT5677_I2C_MASTER_CTRL7:
case RT5677_I2C_MASTER_CTRL8:
case RT5677_HAP_GENE_CTRL2:
case RT5677_PWR_ANLG2: /* Modified by DSP firmware */
case RT5677_PWR_DSP_ST:
case RT5677_PRIV_DATA:
case RT5677_ASRC_22:
case RT5677_ASRC_23:
case RT5677_VAD_CTRL5:
case RT5677_ADC_EQ_CTRL1:
case RT5677_EQ_CTRL1:
case RT5677_IRQ_CTRL1:
case RT5677_IRQ_CTRL2:
case RT5677_GPIO_ST:
case RT5677_GPIO_CTRL1: /* Modified by DSP firmware */
case RT5677_GPIO_CTRL2: /* Modified by DSP firmware */
case RT5677_DSP_INB1_SRC_CTRL4:
case RT5677_DSP_INB2_SRC_CTRL4:
case RT5677_DSP_INB3_SRC_CTRL4:
case RT5677_DSP_OUTB1_SRC_CTRL4:
case RT5677_DSP_OUTB2_SRC_CTRL4:
case RT5677_VENDOR_ID:
case RT5677_VENDOR_ID1:
case RT5677_VENDOR_ID2:
return true;
default:
return false;
}
}
static bool rt5677_readable_register(struct device *dev, unsigned int reg)
{
int i;
for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
if (reg >= rt5677_ranges[i].range_min &&
reg <= rt5677_ranges[i].range_max) {
return true;
}
}
switch (reg) {
case RT5677_RESET:
case RT5677_LOUT1:
case RT5677_IN1:
case RT5677_MICBIAS:
case RT5677_SLIMBUS_PARAM:
case RT5677_SLIMBUS_RX:
case RT5677_SLIMBUS_CTRL:
case RT5677_SIDETONE_CTRL:
case RT5677_ANA_DAC1_2_3_SRC:
case RT5677_IF_DSP_DAC3_4_MIXER:
case RT5677_DAC4_DIG_VOL:
case RT5677_DAC3_DIG_VOL:
case RT5677_DAC1_DIG_VOL:
case RT5677_DAC2_DIG_VOL:
case RT5677_IF_DSP_DAC2_MIXER:
case RT5677_STO1_ADC_DIG_VOL:
case RT5677_MONO_ADC_DIG_VOL:
case RT5677_STO1_2_ADC_BST:
case RT5677_STO2_ADC_DIG_VOL:
case RT5677_ADC_BST_CTRL2:
case RT5677_STO3_4_ADC_BST:
case RT5677_STO3_ADC_DIG_VOL:
case RT5677_STO4_ADC_DIG_VOL:
case RT5677_STO4_ADC_MIXER:
case RT5677_STO3_ADC_MIXER:
case RT5677_STO2_ADC_MIXER:
case RT5677_STO1_ADC_MIXER:
case RT5677_MONO_ADC_MIXER:
case RT5677_ADC_IF_DSP_DAC1_MIXER:
case RT5677_STO1_DAC_MIXER:
case RT5677_MONO_DAC_MIXER:
case RT5677_DD1_MIXER:
case RT5677_DD2_MIXER:
case RT5677_IF3_DATA:
case RT5677_IF4_DATA:
case RT5677_PDM_OUT_CTRL:
case RT5677_PDM_DATA_CTRL1:
case RT5677_PDM_DATA_CTRL2:
case RT5677_PDM1_DATA_CTRL2:
case RT5677_PDM1_DATA_CTRL3:
case RT5677_PDM1_DATA_CTRL4:
case RT5677_PDM2_DATA_CTRL2:
case RT5677_PDM2_DATA_CTRL3:
case RT5677_PDM2_DATA_CTRL4:
case RT5677_TDM1_CTRL1:
case RT5677_TDM1_CTRL2:
case RT5677_TDM1_CTRL3:
case RT5677_TDM1_CTRL4:
case RT5677_TDM1_CTRL5:
case RT5677_TDM2_CTRL1:
case RT5677_TDM2_CTRL2:
case RT5677_TDM2_CTRL3:
case RT5677_TDM2_CTRL4:
case RT5677_TDM2_CTRL5:
case RT5677_I2C_MASTER_CTRL1:
case RT5677_I2C_MASTER_CTRL2:
case RT5677_I2C_MASTER_CTRL3:
case RT5677_I2C_MASTER_CTRL4:
case RT5677_I2C_MASTER_CTRL5:
case RT5677_I2C_MASTER_CTRL6:
case RT5677_I2C_MASTER_CTRL7:
case RT5677_I2C_MASTER_CTRL8:
case RT5677_DMIC_CTRL1:
case RT5677_DMIC_CTRL2:
case RT5677_HAP_GENE_CTRL1:
case RT5677_HAP_GENE_CTRL2:
case RT5677_HAP_GENE_CTRL3:
case RT5677_HAP_GENE_CTRL4:
case RT5677_HAP_GENE_CTRL5:
case RT5677_HAP_GENE_CTRL6:
case RT5677_HAP_GENE_CTRL7:
case RT5677_HAP_GENE_CTRL8:
case RT5677_HAP_GENE_CTRL9:
case RT5677_HAP_GENE_CTRL10:
case RT5677_PWR_DIG1:
case RT5677_PWR_DIG2:
case RT5677_PWR_ANLG1:
case RT5677_PWR_ANLG2:
case RT5677_PWR_DSP1:
case RT5677_PWR_DSP_ST:
case RT5677_PWR_DSP2:
case RT5677_ADC_DAC_HPF_CTRL1:
case RT5677_PRIV_INDEX:
case RT5677_PRIV_DATA:
case RT5677_I2S4_SDP:
case RT5677_I2S1_SDP:
case RT5677_I2S2_SDP:
case RT5677_I2S3_SDP:
case RT5677_CLK_TREE_CTRL1:
case RT5677_CLK_TREE_CTRL2:
case RT5677_CLK_TREE_CTRL3:
case RT5677_PLL1_CTRL1:
case RT5677_PLL1_CTRL2:
case RT5677_PLL2_CTRL1:
case RT5677_PLL2_CTRL2:
case RT5677_GLB_CLK1:
case RT5677_GLB_CLK2:
case RT5677_ASRC_1:
case RT5677_ASRC_2:
case RT5677_ASRC_3:
case RT5677_ASRC_4:
case RT5677_ASRC_5:
case RT5677_ASRC_6:
case RT5677_ASRC_7:
case RT5677_ASRC_8:
case RT5677_ASRC_9:
case RT5677_ASRC_10:
case RT5677_ASRC_11:
case RT5677_ASRC_12:
case RT5677_ASRC_13:
case RT5677_ASRC_14:
case RT5677_ASRC_15:
case RT5677_ASRC_16:
case RT5677_ASRC_17:
case RT5677_ASRC_18:
case RT5677_ASRC_19:
case RT5677_ASRC_20:
case RT5677_ASRC_21:
case RT5677_ASRC_22:
case RT5677_ASRC_23:
case RT5677_VAD_CTRL1:
case RT5677_VAD_CTRL2:
case RT5677_VAD_CTRL3:
case RT5677_VAD_CTRL4:
case RT5677_VAD_CTRL5:
case RT5677_DSP_INB_CTRL1:
case RT5677_DSP_INB_CTRL2:
case RT5677_DSP_IN_OUTB_CTRL:
case RT5677_DSP_OUTB0_1_DIG_VOL:
case RT5677_DSP_OUTB2_3_DIG_VOL:
case RT5677_DSP_OUTB4_5_DIG_VOL:
case RT5677_DSP_OUTB6_7_DIG_VOL:
case RT5677_ADC_EQ_CTRL1:
case RT5677_ADC_EQ_CTRL2:
case RT5677_EQ_CTRL1:
case RT5677_EQ_CTRL2:
case RT5677_EQ_CTRL3:
case RT5677_SOFT_VOL_ZERO_CROSS1:
case RT5677_JD_CTRL1:
case RT5677_JD_CTRL2:
case RT5677_JD_CTRL3:
case RT5677_IRQ_CTRL1:
case RT5677_IRQ_CTRL2:
case RT5677_GPIO_ST:
case RT5677_GPIO_CTRL1:
case RT5677_GPIO_CTRL2:
case RT5677_GPIO_CTRL3:
case RT5677_STO1_ADC_HI_FILTER1:
case RT5677_STO1_ADC_HI_FILTER2:
case RT5677_MONO_ADC_HI_FILTER1:
case RT5677_MONO_ADC_HI_FILTER2:
case RT5677_STO2_ADC_HI_FILTER1:
case RT5677_STO2_ADC_HI_FILTER2:
case RT5677_STO3_ADC_HI_FILTER1:
case RT5677_STO3_ADC_HI_FILTER2:
case RT5677_STO4_ADC_HI_FILTER1:
case RT5677_STO4_ADC_HI_FILTER2:
case RT5677_MB_DRC_CTRL1:
case RT5677_DRC1_CTRL1:
case RT5677_DRC1_CTRL2:
case RT5677_DRC1_CTRL3:
case RT5677_DRC1_CTRL4:
case RT5677_DRC1_CTRL5:
case RT5677_DRC1_CTRL6:
case RT5677_DRC2_CTRL1:
case RT5677_DRC2_CTRL2:
case RT5677_DRC2_CTRL3:
case RT5677_DRC2_CTRL4:
case RT5677_DRC2_CTRL5:
case RT5677_DRC2_CTRL6:
case RT5677_DRC1_HL_CTRL1:
case RT5677_DRC1_HL_CTRL2:
case RT5677_DRC2_HL_CTRL1:
case RT5677_DRC2_HL_CTRL2:
case RT5677_DSP_INB1_SRC_CTRL1:
case RT5677_DSP_INB1_SRC_CTRL2:
case RT5677_DSP_INB1_SRC_CTRL3:
case RT5677_DSP_INB1_SRC_CTRL4:
case RT5677_DSP_INB2_SRC_CTRL1:
case RT5677_DSP_INB2_SRC_CTRL2:
case RT5677_DSP_INB2_SRC_CTRL3:
case RT5677_DSP_INB2_SRC_CTRL4:
case RT5677_DSP_INB3_SRC_CTRL1:
case RT5677_DSP_INB3_SRC_CTRL2:
case RT5677_DSP_INB3_SRC_CTRL3:
case RT5677_DSP_INB3_SRC_CTRL4:
case RT5677_DSP_OUTB1_SRC_CTRL1:
case RT5677_DSP_OUTB1_SRC_CTRL2:
case RT5677_DSP_OUTB1_SRC_CTRL3:
case RT5677_DSP_OUTB1_SRC_CTRL4:
case RT5677_DSP_OUTB2_SRC_CTRL1:
case RT5677_DSP_OUTB2_SRC_CTRL2:
case RT5677_DSP_OUTB2_SRC_CTRL3:
case RT5677_DSP_OUTB2_SRC_CTRL4:
case RT5677_DSP_OUTB_0123_MIXER_CTRL:
case RT5677_DSP_OUTB_45_MIXER_CTRL:
case RT5677_DSP_OUTB_67_MIXER_CTRL:
case RT5677_DIG_MISC:
case RT5677_GEN_CTRL1:
case RT5677_GEN_CTRL2:
case RT5677_VENDOR_ID:
case RT5677_VENDOR_ID1:
case RT5677_VENDOR_ID2:
return true;
default:
return false;
}
}
/**
* rt5677_dsp_mode_i2c_write_addr - Write value to address on DSP mode.
* @rt5677: Private Data.
* @addr: Address index.
* @value: Address data.
* @opcode: opcode value
*
* Returns 0 for success or negative error code.
*/
static int rt5677_dsp_mode_i2c_write_addr(struct rt5677_priv *rt5677,
unsigned int addr, unsigned int value, unsigned int opcode)
{
struct snd_soc_component *component = rt5677->component;
int ret;
mutex_lock(&rt5677->dsp_cmd_lock);
ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
addr >> 16);
if (ret < 0) {
dev_err(component->dev, "Failed to set addr msb value: %d\n", ret);
goto err;
}
ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
addr & 0xffff);
if (ret < 0) {
dev_err(component->dev, "Failed to set addr lsb value: %d\n", ret);
goto err;
}
ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB,
value >> 16);
if (ret < 0) {
dev_err(component->dev, "Failed to set data msb value: %d\n", ret);
goto err;
}
ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB,
value & 0xffff);
if (ret < 0) {
dev_err(component->dev, "Failed to set data lsb value: %d\n", ret);
goto err;
}
ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
opcode);
if (ret < 0) {
dev_err(component->dev, "Failed to set op code value: %d\n", ret);
goto err;
}
err:
mutex_unlock(&rt5677->dsp_cmd_lock);
return ret;
}
/**
* rt5677_dsp_mode_i2c_read_addr - Read value from address on DSP mode.
* @rt5677: Private Data.
* @addr: Address index.
* @value: Address data.
*
*
* Returns 0 for success or negative error code.
*/
static int rt5677_dsp_mode_i2c_read_addr(
struct rt5677_priv *rt5677, unsigned int addr, unsigned int *value)
{
struct snd_soc_component *component = rt5677->component;
int ret;
unsigned int msb, lsb;
mutex_lock(&rt5677->dsp_cmd_lock);
ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
addr >> 16);
if (ret < 0) {
dev_err(component->dev, "Failed to set addr msb value: %d\n", ret);
goto err;
}
ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
addr & 0xffff);
if (ret < 0) {
dev_err(component->dev, "Failed to set addr lsb value: %d\n", ret);
goto err;
}
ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
0x0002);
if (ret < 0) {
dev_err(component->dev, "Failed to set op code value: %d\n", ret);
goto err;
}
regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, &msb);
regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, &lsb);
*value = (msb << 16) | lsb;
err:
mutex_unlock(&rt5677->dsp_cmd_lock);
return ret;
}
/**
* rt5677_dsp_mode_i2c_write - Write register on DSP mode.
* @rt5677: Private Data.
* @reg: Register index.
* @value: Register data.
*
*
* Returns 0 for success or negative error code.
*/
static int rt5677_dsp_mode_i2c_write(struct rt5677_priv *rt5677,
unsigned int reg, unsigned int value)
{
return rt5677_dsp_mode_i2c_write_addr(rt5677, 0x18020000 + reg * 2,
value, 0x0001);
}
/**
* rt5677_dsp_mode_i2c_read - Read register on DSP mode.
* @rt5677: Private Data
* @reg: Register index.
* @value: Register data.
*
*
* Returns 0 for success or negative error code.
*/
static int rt5677_dsp_mode_i2c_read(
struct rt5677_priv *rt5677, unsigned int reg, unsigned int *value)
{
int ret = rt5677_dsp_mode_i2c_read_addr(rt5677, 0x18020000 + reg * 2,
value);
*value &= 0xffff;
return ret;
}
static void rt5677_set_dsp_mode(struct rt5677_priv *rt5677, bool on)
{
if (on) {
regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1,
RT5677_PWR_DSP, RT5677_PWR_DSP);
rt5677->is_dsp_mode = true;
} else {
regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1,
RT5677_PWR_DSP, 0x0);
rt5677->is_dsp_mode = false;
}
}
static unsigned int rt5677_set_vad_source(struct rt5677_priv *rt5677)
{
struct snd_soc_dapm_context *dapm =
snd_soc_component_get_dapm(rt5677->component);
/* Force dapm to sync before we enable the
* DSP to prevent write corruption
*/
snd_soc_dapm_sync(dapm);
/* DMIC1 power = enabled
* DMIC CLK = 256 * fs / 12
*/
regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1,
RT5677_DMIC_CLK_MASK, 5 << RT5677_DMIC_CLK_SFT);
/* I2S pre divide 2 = /6 (clk_sys2) */
regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
RT5677_I2S_PD2_MASK, RT5677_I2S_PD2_6);
/* DSP Clock = MCLK1 (bypassed PLL2) */
regmap_write(rt5677->regmap, RT5677_GLB_CLK2,
RT5677_DSP_CLK_SRC_BYPASS);
/* SAD Threshold1 */
regmap_write(rt5677->regmap, RT5677_VAD_CTRL2, 0x013f);
/* SAD Threshold2 */
regmap_write(rt5677->regmap, RT5677_VAD_CTRL3, 0x0ae5);
/* SAD Sample Rate Converter = Up 6 (8K to 48K)
* SAD Output Sample Rate = Same as I2S
* SAD Threshold3
*/
regmap_update_bits(rt5677->regmap, RT5677_VAD_CTRL4,
RT5677_VAD_OUT_SRC_RATE_MASK | RT5677_VAD_OUT_SRC_MASK |
RT5677_VAD_LV_DIFF_MASK, 0x7f << RT5677_VAD_LV_DIFF_SFT);
/* Minimum frame level within a pre-determined duration = 32 frames
* Bypass ADPCM Encoder/Decoder = Bypass ADPCM
* Automatic Push Data to SAD Buffer Once SAD Flag is triggered = enable
* SAD Buffer Over-Writing = enable
* SAD Buffer Pop Mode Control = disable
* SAD Buffer Push Mode Control = enable
* SAD Detector Control = enable
* SAD Function Control = enable
* SAD Function Reset = normal
*/
regmap_write(rt5677->regmap, RT5677_VAD_CTRL1,
RT5677_VAD_FUNC_RESET | RT5677_VAD_FUNC_ENABLE |
RT5677_VAD_DET_ENABLE | RT5677_VAD_BUF_PUSH |
RT5677_VAD_BUF_OW | RT5677_VAD_FG2ENC |
RT5677_VAD_ADPCM_BYPASS | 1 << RT5677_VAD_MIN_DUR_SFT);
/* VAD/SAD is not routed to the IRQ output (i.e. MX-BE[14] = 0), but it
* is routed to DSP_IRQ_0, so DSP firmware may use it to sleep and save
* power. See ALC5677 datasheet section 9.17 "GPIO, Interrupt and Jack
* Detection" for more info.
*/
/* Private register, no doc */
regmap_update_bits(rt5677->regmap, RT5677_PR_BASE + RT5677_BIAS_CUR4,
0x0f00, 0x0100);
/* LDO2 output = 1.2V
* LDO1 output = 1.2V (LDO_IN = 1.8V)
*/
regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK,
5 << RT5677_LDO1_SEL_SFT | 5 << RT5677_LDO2_SEL_SFT);
/* Codec core power = power on
* LDO1 power = power on
*/
regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
RT5677_PWR_CORE | RT5677_PWR_LDO1,
RT5677_PWR_CORE | RT5677_PWR_LDO1);
/* Isolation for DCVDD4 = normal (set during probe)
* Isolation for DCVDD2 = normal (set during probe)
* Isolation for DSP = normal
* Isolation for Band 0~7 = disable
* Isolation for InBound 4~10 and OutBound 4~10 = disable
*/
regmap_write(rt5677->regmap, RT5677_PWR_DSP2,
RT5677_PWR_CORE_ISO | RT5677_PWR_DSP_ISO |
RT5677_PWR_SR7_ISO | RT5677_PWR_SR6_ISO |
RT5677_PWR_SR5_ISO | RT5677_PWR_SR4_ISO |
RT5677_PWR_SR3_ISO | RT5677_PWR_SR2_ISO |
RT5677_PWR_SR1_ISO | RT5677_PWR_SR0_ISO |
RT5677_PWR_MLT_ISO);
/* System Band 0~7 = power on
* InBound 4~10 and OutBound 4~10 = power on
* DSP = power on
* DSP CPU = stop (will be set to "run" after firmware loaded)
*/
regmap_write(rt5677->regmap, RT5677_PWR_DSP1,
RT5677_PWR_SR7 | RT5677_PWR_SR6 |
RT5677_PWR_SR5 | RT5677_PWR_SR4 |
RT5677_PWR_SR3 | RT5677_PWR_SR2 |
RT5677_PWR_SR1 | RT5677_PWR_SR0 |
RT5677_PWR_MLT | RT5677_PWR_DSP |
RT5677_PWR_DSP_CPU);
return 0;
}
static int rt5677_parse_and_load_dsp(struct rt5677_priv *rt5677, const u8 *buf,
unsigned int len)
{
struct snd_soc_component *component = rt5677->component;
Elf32_Ehdr *elf_hdr;
Elf32_Phdr *pr_hdr;
Elf32_Half i;
int ret = 0;
if (!buf || (len < sizeof(Elf32_Ehdr)))
return -ENOMEM;
elf_hdr = (Elf32_Ehdr *)buf;
#ifndef EM_XTENSA
#define EM_XTENSA 94
#endif
if (strncmp(elf_hdr->e_ident, ELFMAG, sizeof(ELFMAG) - 1))
dev_err(component->dev, "Wrong ELF header prefix\n");
if (elf_hdr->e_ehsize != sizeof(Elf32_Ehdr))
dev_err(component->dev, "Wrong Elf header size\n");
if (elf_hdr->e_machine != EM_XTENSA)
dev_err(component->dev, "Wrong DSP code file\n");
if (len < elf_hdr->e_phoff)
return -ENOMEM;
pr_hdr = (Elf32_Phdr *)(buf + elf_hdr->e_phoff);
for (i = 0; i < elf_hdr->e_phnum; i++) {
/* TODO: handle p_memsz != p_filesz */
if (pr_hdr->p_paddr && pr_hdr->p_filesz) {
dev_info(component->dev, "Load 0x%x bytes to 0x%x\n",
pr_hdr->p_filesz, pr_hdr->p_paddr);
ret = rt5677_spi_write(pr_hdr->p_paddr,
buf + pr_hdr->p_offset,
pr_hdr->p_filesz);
if (ret)
dev_err(component->dev, "Load firmware failed %d\n",
ret);
}
pr_hdr++;
}
return ret;
}
static int rt5677_load_dsp_from_file(struct rt5677_priv *rt5677)
{
const struct firmware *fwp;
struct device *dev = rt5677->component->dev;
int ret = 0;
/* Load dsp firmware from rt5677_elf_vad file */
ret = request_firmware(&fwp, "rt5677_elf_vad", dev);
if (ret) {
dev_err(dev, "Request rt5677_elf_vad failed %d\n", ret);
return ret;
}
dev_info(dev, "Requested rt5677_elf_vad (%zu)\n", fwp->size);
ret = rt5677_parse_and_load_dsp(rt5677, fwp->data, fwp->size);
release_firmware(fwp);
return ret;
}
static int rt5677_set_dsp_vad(struct snd_soc_component *component, bool on)
{
struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
rt5677->dsp_vad_en_request = on;
rt5677->dsp_vad_en = on;
if (!IS_ENABLED(CONFIG_SND_SOC_RT5677_SPI))
return -ENXIO;
schedule_delayed_work(&rt5677->dsp_work, 0);
return 0;
}
static void rt5677_dsp_work(struct work_struct *work)
{
struct rt5677_priv *rt5677 =
container_of(work, struct rt5677_priv, dsp_work.work);
static bool activity;
bool enable = rt5677->dsp_vad_en;
int i, val;
dev_info(rt5677->component->dev, "DSP VAD: enable=%d, activity=%d\n",
enable, activity);
if (enable && !activity) {
activity = true;
/* Before a hotword is detected, GPIO1 pin is configured as IRQ
* output so that jack detect works. When a hotword is detected,
* the DSP firmware configures the GPIO1 pin as GPIO1 and
* drives a 1. rt5677_irq() is called after a rising edge on
* the GPIO1 pin, due to either jack detect event or hotword
* event, or both. All possible events are checked and handled
* in rt5677_irq() where GPIO1 pin is configured back to IRQ
* output if a hotword is detected.
*/
rt5677_set_vad_source(rt5677);
rt5677_set_dsp_mode(rt5677, true);
#define RT5677_BOOT_RETRY 20
for (i = 0; i < RT5677_BOOT_RETRY; i++) {
regmap_read(rt5677->regmap, RT5677_PWR_DSP_ST, &val);
if (val == 0x3ff)
break;
udelay(500);
}
if (i == RT5677_BOOT_RETRY && val != 0x3ff) {
dev_err(rt5677->component->dev, "DSP Boot Timed Out!");
return;
}
/* Boot the firmware from IRAM instead of SRAM0. */
rt5677_dsp_mode_i2c_write_addr(rt5677, RT5677_DSP_BOOT_VECTOR,
0x0009, 0x0003);
rt5677_dsp_mode_i2c_write_addr(rt5677, RT5677_DSP_BOOT_VECTOR,
0x0019, 0x0003);
rt5677_dsp_mode_i2c_write_addr(rt5677, RT5677_DSP_BOOT_VECTOR,
0x0009, 0x0003);
rt5677_load_dsp_from_file(rt5677);
/* Set DSP CPU to Run */
regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1,
RT5677_PWR_DSP_CPU, 0x0);
} else if (!enable && activity) {
activity = false;
/* Don't turn off the DSP while handling irqs */
mutex_lock(&rt5677->irq_lock);
/* Set DSP CPU to Stop */
regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1,
RT5677_PWR_DSP_CPU, RT5677_PWR_DSP_CPU);
rt5677_set_dsp_mode(rt5677, false);
/* Disable and clear VAD interrupt */
regmap_write(rt5677->regmap, RT5677_VAD_CTRL1, 0x2184);
/* Set GPIO1 pin back to be IRQ output for jack detect */
regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1,
RT5677_GPIO1_PIN_MASK, RT5677_GPIO1_PIN_IRQ);
mutex_unlock(&rt5677->irq_lock);
}
}
static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
static const DECLARE_TLV_DB_SCALE(st_vol_tlv, -4650, 150, 0);
/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
static const DECLARE_TLV_DB_RANGE(bst_tlv,
0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
);
static int rt5677_dsp_vad_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = rt5677->dsp_vad_en_request;
return 0;
}
static int rt5677_dsp_vad_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
rt5677_set_dsp_vad(component, !!ucontrol->value.integer.value[0]);
return 0;
}