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wcd934x.c
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// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2019, Linaro Limited
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/mfd/wcd934x/registers.h>
#include <linux/mfd/wcd934x/wcd934x.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of_clk.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#include <linux/slimbus.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/tlv.h>
#include "wcd-clsh-v2.h"
#define WCD934X_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
/* Fractional Rates */
#define WCD934X_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
SNDRV_PCM_RATE_176400)
#define WCD934X_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE)
/* slave port water mark level
* (0: 6bytes, 1: 9bytes, 2: 12 bytes, 3: 15 bytes)
*/
#define SLAVE_PORT_WATER_MARK_6BYTES 0
#define SLAVE_PORT_WATER_MARK_9BYTES 1
#define SLAVE_PORT_WATER_MARK_12BYTES 2
#define SLAVE_PORT_WATER_MARK_15BYTES 3
#define SLAVE_PORT_WATER_MARK_SHIFT 1
#define SLAVE_PORT_ENABLE 1
#define SLAVE_PORT_DISABLE 0
#define WCD934X_SLIM_WATER_MARK_VAL \
((SLAVE_PORT_WATER_MARK_12BYTES << SLAVE_PORT_WATER_MARK_SHIFT) | \
(SLAVE_PORT_ENABLE))
#define WCD934X_SLIM_NUM_PORT_REG 3
#define WCD934X_SLIM_PGD_PORT_INT_TX_EN0 (WCD934X_SLIM_PGD_PORT_INT_EN0 + 2)
#define WCD934X_SLIM_IRQ_OVERFLOW BIT(0)
#define WCD934X_SLIM_IRQ_UNDERFLOW BIT(1)
#define WCD934X_SLIM_IRQ_PORT_CLOSED BIT(2)
#define WCD934X_MCLK_CLK_12P288MHZ 12288000
#define WCD934X_MCLK_CLK_9P6MHZ 9600000
/* Only valid for 9.6 MHz mclk */
#define WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ 2400000
#define WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ 4800000
/* Only valid for 12.288 MHz mclk */
#define WCD9XXX_DMIC_SAMPLE_RATE_4P096MHZ 4096000
#define WCD934X_DMIC_CLK_DIV_2 0x0
#define WCD934X_DMIC_CLK_DIV_3 0x1
#define WCD934X_DMIC_CLK_DIV_4 0x2
#define WCD934X_DMIC_CLK_DIV_6 0x3
#define WCD934X_DMIC_CLK_DIV_8 0x4
#define WCD934X_DMIC_CLK_DIV_16 0x5
#define WCD934X_DMIC_CLK_DRIVE_DEFAULT 0x02
#define TX_HPF_CUT_OFF_FREQ_MASK 0x60
#define CF_MIN_3DB_4HZ 0x0
#define CF_MIN_3DB_75HZ 0x1
#define CF_MIN_3DB_150HZ 0x2
#define WCD934X_RX_START 16
#define WCD934X_NUM_INTERPOLATORS 9
#define WCD934X_RX_PATH_CTL_OFFSET 20
#define WCD934X_MAX_VALID_ADC_MUX 13
#define WCD934X_INVALID_ADC_MUX 9
#define WCD934X_SLIM_RX_CH(p) \
{.port = p + WCD934X_RX_START, .shift = p,}
#define WCD934X_SLIM_TX_CH(p) \
{.port = p, .shift = p,}
/* Feature masks to distinguish codec version */
#define DSD_DISABLED_MASK 0
#define SLNQ_DISABLED_MASK 1
#define DSD_DISABLED BIT(DSD_DISABLED_MASK)
#define SLNQ_DISABLED BIT(SLNQ_DISABLED_MASK)
/* As fine version info cannot be retrieved before wcd probe.
* Define three coarse versions for possible future use before wcd probe.
*/
#define WCD_VERSION_WCD9340_1_0 0x400
#define WCD_VERSION_WCD9341_1_0 0x410
#define WCD_VERSION_WCD9340_1_1 0x401
#define WCD_VERSION_WCD9341_1_1 0x411
#define WCD934X_AMIC_PWR_LEVEL_LP 0
#define WCD934X_AMIC_PWR_LEVEL_DEFAULT 1
#define WCD934X_AMIC_PWR_LEVEL_HP 2
#define WCD934X_AMIC_PWR_LEVEL_HYBRID 3
#define WCD934X_AMIC_PWR_LVL_MASK 0x60
#define WCD934X_AMIC_PWR_LVL_SHIFT 0x5
#define WCD934X_DEC_PWR_LVL_MASK 0x06
#define WCD934X_DEC_PWR_LVL_LP 0x02
#define WCD934X_DEC_PWR_LVL_HP 0x04
#define WCD934X_DEC_PWR_LVL_DF 0x00
#define WCD934X_DEC_PWR_LVL_HYBRID WCD934X_DEC_PWR_LVL_DF
#define WCD934X_DEF_MICBIAS_MV 1800
#define WCD934X_MAX_MICBIAS_MV 2850
#define WCD_IIR_FILTER_SIZE (sizeof(u32) * BAND_MAX)
#define WCD_IIR_FILTER_CTL(xname, iidx, bidx) \
{ \
.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
.info = wcd934x_iir_filter_info, \
.get = wcd934x_get_iir_band_audio_mixer, \
.put = wcd934x_put_iir_band_audio_mixer, \
.private_value = (unsigned long)&(struct wcd_iir_filter_ctl) { \
.iir_idx = iidx, \
.band_idx = bidx, \
.bytes_ext = {.max = WCD_IIR_FILTER_SIZE, }, \
} \
}
#define WCD934X_INTERPOLATOR_PATH(id) \
{"RX INT" #id "_1 MIX1 INP0", "RX0", "SLIM RX0"}, \
{"RX INT" #id "_1 MIX1 INP0", "RX1", "SLIM RX1"}, \
{"RX INT" #id "_1 MIX1 INP0", "RX2", "SLIM RX2"}, \
{"RX INT" #id "_1 MIX1 INP0", "RX3", "SLIM RX3"}, \
{"RX INT" #id "_1 MIX1 INP0", "RX4", "SLIM RX4"}, \
{"RX INT" #id "_1 MIX1 INP0", "RX5", "SLIM RX5"}, \
{"RX INT" #id "_1 MIX1 INP0", "RX6", "SLIM RX6"}, \
{"RX INT" #id "_1 MIX1 INP0", "RX7", "SLIM RX7"}, \
{"RX INT" #id "_1 MIX1 INP0", "IIR0", "IIR0"}, \
{"RX INT" #id "_1 MIX1 INP0", "IIR1", "IIR1"}, \
{"RX INT" #id "_1 MIX1 INP1", "RX0", "SLIM RX0"}, \
{"RX INT" #id "_1 MIX1 INP1", "RX1", "SLIM RX1"}, \
{"RX INT" #id "_1 MIX1 INP1", "RX2", "SLIM RX2"}, \
{"RX INT" #id "_1 MIX1 INP1", "RX3", "SLIM RX3"}, \
{"RX INT" #id "_1 MIX1 INP1", "RX4", "SLIM RX4"}, \
{"RX INT" #id "_1 MIX1 INP1", "RX5", "SLIM RX5"}, \
{"RX INT" #id "_1 MIX1 INP1", "RX6", "SLIM RX6"}, \
{"RX INT" #id "_1 MIX1 INP1", "RX7", "SLIM RX7"}, \
{"RX INT" #id "_1 MIX1 INP1", "IIR0", "IIR0"}, \
{"RX INT" #id "_1 MIX1 INP1", "IIR1", "IIR1"}, \
{"RX INT" #id "_1 MIX1 INP2", "RX0", "SLIM RX0"}, \
{"RX INT" #id "_1 MIX1 INP2", "RX1", "SLIM RX1"}, \
{"RX INT" #id "_1 MIX1 INP2", "RX2", "SLIM RX2"}, \
{"RX INT" #id "_1 MIX1 INP2", "RX3", "SLIM RX3"}, \
{"RX INT" #id "_1 MIX1 INP2", "RX4", "SLIM RX4"}, \
{"RX INT" #id "_1 MIX1 INP2", "RX5", "SLIM RX5"}, \
{"RX INT" #id "_1 MIX1 INP2", "RX6", "SLIM RX6"}, \
{"RX INT" #id "_1 MIX1 INP2", "RX7", "SLIM RX7"}, \
{"RX INT" #id "_1 MIX1 INP2", "IIR0", "IIR0"}, \
{"RX INT" #id "_1 MIX1 INP2", "IIR1", "IIR1"}, \
{"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP0"}, \
{"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP1"}, \
{"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP2"}, \
{"RX INT" #id "_2 MUX", "RX0", "SLIM RX0"}, \
{"RX INT" #id "_2 MUX", "RX1", "SLIM RX1"}, \
{"RX INT" #id "_2 MUX", "RX2", "SLIM RX2"}, \
{"RX INT" #id "_2 MUX", "RX3", "SLIM RX3"}, \
{"RX INT" #id "_2 MUX", "RX4", "SLIM RX4"}, \
{"RX INT" #id "_2 MUX", "RX5", "SLIM RX5"}, \
{"RX INT" #id "_2 MUX", "RX6", "SLIM RX6"}, \
{"RX INT" #id "_2 MUX", "RX7", "SLIM RX7"}, \
{"RX INT" #id "_2 MUX", NULL, "INT" #id "_CLK"}, \
{"RX INT" #id "_2 MUX", NULL, "DSMDEM" #id "_CLK"}, \
{"RX INT" #id "_2 INTERP", NULL, "RX INT" #id "_2 MUX"}, \
{"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_2 INTERP"}, \
{"RX INT" #id "_1 INTERP", NULL, "RX INT" #id "_1 MIX1"}, \
{"RX INT" #id "_1 INTERP", NULL, "INT" #id "_CLK"}, \
{"RX INT" #id "_1 INTERP", NULL, "DSMDEM" #id "_CLK"}, \
{"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_1 INTERP"}
#define WCD934X_INTERPOLATOR_MIX2(id) \
{"RX INT" #id " MIX2", NULL, "RX INT" #id " SEC MIX"}, \
{"RX INT" #id " MIX2", NULL, "RX INT" #id " MIX2 INP"}
#define WCD934X_SLIM_RX_AIF_PATH(id) \
{"SLIM RX"#id" MUX", "AIF1_PB", "AIF1 PB"}, \
{"SLIM RX"#id" MUX", "AIF2_PB", "AIF2 PB"}, \
{"SLIM RX"#id" MUX", "AIF3_PB", "AIF3 PB"}, \
{"SLIM RX"#id" MUX", "AIF4_PB", "AIF4 PB"}, \
{"SLIM RX"#id, NULL, "SLIM RX"#id" MUX"}
#define WCD934X_ADC_MUX(id) \
{"ADC MUX" #id, "DMIC", "DMIC MUX" #id }, \
{"ADC MUX" #id, "AMIC", "AMIC MUX" #id }, \
{"DMIC MUX" #id, "DMIC0", "DMIC0"}, \
{"DMIC MUX" #id, "DMIC1", "DMIC1"}, \
{"DMIC MUX" #id, "DMIC2", "DMIC2"}, \
{"DMIC MUX" #id, "DMIC3", "DMIC3"}, \
{"DMIC MUX" #id, "DMIC4", "DMIC4"}, \
{"DMIC MUX" #id, "DMIC5", "DMIC5"}, \
{"AMIC MUX" #id, "ADC1", "ADC1"}, \
{"AMIC MUX" #id, "ADC2", "ADC2"}, \
{"AMIC MUX" #id, "ADC3", "ADC3"}, \
{"AMIC MUX" #id, "ADC4", "ADC4"}
#define WCD934X_IIR_INP_MUX(id) \
{"IIR" #id, NULL, "IIR" #id " INP0 MUX"}, \
{"IIR" #id " INP0 MUX", "DEC0", "ADC MUX0"}, \
{"IIR" #id " INP0 MUX", "DEC1", "ADC MUX1"}, \
{"IIR" #id " INP0 MUX", "DEC2", "ADC MUX2"}, \
{"IIR" #id " INP0 MUX", "DEC3", "ADC MUX3"}, \
{"IIR" #id " INP0 MUX", "DEC4", "ADC MUX4"}, \
{"IIR" #id " INP0 MUX", "DEC5", "ADC MUX5"}, \
{"IIR" #id " INP0 MUX", "DEC6", "ADC MUX6"}, \
{"IIR" #id " INP0 MUX", "DEC7", "ADC MUX7"}, \
{"IIR" #id " INP0 MUX", "DEC8", "ADC MUX8"}, \
{"IIR" #id " INP0 MUX", "RX0", "SLIM RX0"}, \
{"IIR" #id " INP0 MUX", "RX1", "SLIM RX1"}, \
{"IIR" #id " INP0 MUX", "RX2", "SLIM RX2"}, \
{"IIR" #id " INP0 MUX", "RX3", "SLIM RX3"}, \
{"IIR" #id " INP0 MUX", "RX4", "SLIM RX4"}, \
{"IIR" #id " INP0 MUX", "RX5", "SLIM RX5"}, \
{"IIR" #id " INP0 MUX", "RX6", "SLIM RX6"}, \
{"IIR" #id " INP0 MUX", "RX7", "SLIM RX7"}, \
{"IIR" #id, NULL, "IIR" #id " INP1 MUX"}, \
{"IIR" #id " INP1 MUX", "DEC0", "ADC MUX0"}, \
{"IIR" #id " INP1 MUX", "DEC1", "ADC MUX1"}, \
{"IIR" #id " INP1 MUX", "DEC2", "ADC MUX2"}, \
{"IIR" #id " INP1 MUX", "DEC3", "ADC MUX3"}, \
{"IIR" #id " INP1 MUX", "DEC4", "ADC MUX4"}, \
{"IIR" #id " INP1 MUX", "DEC5", "ADC MUX5"}, \
{"IIR" #id " INP1 MUX", "DEC6", "ADC MUX6"}, \
{"IIR" #id " INP1 MUX", "DEC7", "ADC MUX7"}, \
{"IIR" #id " INP1 MUX", "DEC8", "ADC MUX8"}, \
{"IIR" #id " INP1 MUX", "RX0", "SLIM RX0"}, \
{"IIR" #id " INP1 MUX", "RX1", "SLIM RX1"}, \
{"IIR" #id " INP1 MUX", "RX2", "SLIM RX2"}, \
{"IIR" #id " INP1 MUX", "RX3", "SLIM RX3"}, \
{"IIR" #id " INP1 MUX", "RX4", "SLIM RX4"}, \
{"IIR" #id " INP1 MUX", "RX5", "SLIM RX5"}, \
{"IIR" #id " INP1 MUX", "RX6", "SLIM RX6"}, \
{"IIR" #id " INP1 MUX", "RX7", "SLIM RX7"}, \
{"IIR" #id, NULL, "IIR" #id " INP2 MUX"}, \
{"IIR" #id " INP2 MUX", "DEC0", "ADC MUX0"}, \
{"IIR" #id " INP2 MUX", "DEC1", "ADC MUX1"}, \
{"IIR" #id " INP2 MUX", "DEC2", "ADC MUX2"}, \
{"IIR" #id " INP2 MUX", "DEC3", "ADC MUX3"}, \
{"IIR" #id " INP2 MUX", "DEC4", "ADC MUX4"}, \
{"IIR" #id " INP2 MUX", "DEC5", "ADC MUX5"}, \
{"IIR" #id " INP2 MUX", "DEC6", "ADC MUX6"}, \
{"IIR" #id " INP2 MUX", "DEC7", "ADC MUX7"}, \
{"IIR" #id " INP2 MUX", "DEC8", "ADC MUX8"}, \
{"IIR" #id " INP2 MUX", "RX0", "SLIM RX0"}, \
{"IIR" #id " INP2 MUX", "RX1", "SLIM RX1"}, \
{"IIR" #id " INP2 MUX", "RX2", "SLIM RX2"}, \
{"IIR" #id " INP2 MUX", "RX3", "SLIM RX3"}, \
{"IIR" #id " INP2 MUX", "RX4", "SLIM RX4"}, \
{"IIR" #id " INP2 MUX", "RX5", "SLIM RX5"}, \
{"IIR" #id " INP2 MUX", "RX6", "SLIM RX6"}, \
{"IIR" #id " INP2 MUX", "RX7", "SLIM RX7"}, \
{"IIR" #id, NULL, "IIR" #id " INP3 MUX"}, \
{"IIR" #id " INP3 MUX", "DEC0", "ADC MUX0"}, \
{"IIR" #id " INP3 MUX", "DEC1", "ADC MUX1"}, \
{"IIR" #id " INP3 MUX", "DEC2", "ADC MUX2"}, \
{"IIR" #id " INP3 MUX", "DEC3", "ADC MUX3"}, \
{"IIR" #id " INP3 MUX", "DEC4", "ADC MUX4"}, \
{"IIR" #id " INP3 MUX", "DEC5", "ADC MUX5"}, \
{"IIR" #id " INP3 MUX", "DEC6", "ADC MUX6"}, \
{"IIR" #id " INP3 MUX", "DEC7", "ADC MUX7"}, \
{"IIR" #id " INP3 MUX", "DEC8", "ADC MUX8"}, \
{"IIR" #id " INP3 MUX", "RX0", "SLIM RX0"}, \
{"IIR" #id " INP3 MUX", "RX1", "SLIM RX1"}, \
{"IIR" #id " INP3 MUX", "RX2", "SLIM RX2"}, \
{"IIR" #id " INP3 MUX", "RX3", "SLIM RX3"}, \
{"IIR" #id " INP3 MUX", "RX4", "SLIM RX4"}, \
{"IIR" #id " INP3 MUX", "RX5", "SLIM RX5"}, \
{"IIR" #id " INP3 MUX", "RX6", "SLIM RX6"}, \
{"IIR" #id " INP3 MUX", "RX7", "SLIM RX7"}
#define WCD934X_SLIM_TX_AIF_PATH(id) \
{"AIF1_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id }, \
{"AIF2_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id }, \
{"AIF3_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id }, \
{"SLIM TX" #id, NULL, "CDC_IF TX" #id " MUX"}
enum {
MIC_BIAS_1 = 1,
MIC_BIAS_2,
MIC_BIAS_3,
MIC_BIAS_4
};
enum {
SIDO_SOURCE_INTERNAL,
SIDO_SOURCE_RCO_BG,
};
enum {
INTERP_EAR = 0,
INTERP_HPHL,
INTERP_HPHR,
INTERP_LO1,
INTERP_LO2,
INTERP_LO3_NA, /* LO3 not avalible in Tavil */
INTERP_LO4_NA,
INTERP_SPKR1, /*INT7 WSA Speakers via soundwire */
INTERP_SPKR2, /*INT8 WSA Speakers via soundwire */
INTERP_MAX,
};
enum {
WCD934X_RX0 = 0,
WCD934X_RX1,
WCD934X_RX2,
WCD934X_RX3,
WCD934X_RX4,
WCD934X_RX5,
WCD934X_RX6,
WCD934X_RX7,
WCD934X_RX8,
WCD934X_RX9,
WCD934X_RX10,
WCD934X_RX11,
WCD934X_RX12,
WCD934X_RX_MAX,
};
enum {
WCD934X_TX0 = 0,
WCD934X_TX1,
WCD934X_TX2,
WCD934X_TX3,
WCD934X_TX4,
WCD934X_TX5,
WCD934X_TX6,
WCD934X_TX7,
WCD934X_TX8,
WCD934X_TX9,
WCD934X_TX10,
WCD934X_TX11,
WCD934X_TX12,
WCD934X_TX13,
WCD934X_TX14,
WCD934X_TX15,
WCD934X_TX_MAX,
};
struct wcd934x_slim_ch {
u32 ch_num;
u16 port;
u16 shift;
struct list_head list;
};
static const struct wcd934x_slim_ch wcd934x_tx_chs[WCD934X_TX_MAX] = {
WCD934X_SLIM_TX_CH(0),
WCD934X_SLIM_TX_CH(1),
WCD934X_SLIM_TX_CH(2),
WCD934X_SLIM_TX_CH(3),
WCD934X_SLIM_TX_CH(4),
WCD934X_SLIM_TX_CH(5),
WCD934X_SLIM_TX_CH(6),
WCD934X_SLIM_TX_CH(7),
WCD934X_SLIM_TX_CH(8),
WCD934X_SLIM_TX_CH(9),
WCD934X_SLIM_TX_CH(10),
WCD934X_SLIM_TX_CH(11),
WCD934X_SLIM_TX_CH(12),
WCD934X_SLIM_TX_CH(13),
WCD934X_SLIM_TX_CH(14),
WCD934X_SLIM_TX_CH(15),
};
static const struct wcd934x_slim_ch wcd934x_rx_chs[WCD934X_RX_MAX] = {
WCD934X_SLIM_RX_CH(0), /* 16 */
WCD934X_SLIM_RX_CH(1), /* 17 */
WCD934X_SLIM_RX_CH(2),
WCD934X_SLIM_RX_CH(3),
WCD934X_SLIM_RX_CH(4),
WCD934X_SLIM_RX_CH(5),
WCD934X_SLIM_RX_CH(6),
WCD934X_SLIM_RX_CH(7),
WCD934X_SLIM_RX_CH(8),
WCD934X_SLIM_RX_CH(9),
WCD934X_SLIM_RX_CH(10),
WCD934X_SLIM_RX_CH(11),
WCD934X_SLIM_RX_CH(12),
};
/* Codec supports 2 IIR filters */
enum {
IIR0 = 0,
IIR1,
IIR_MAX,
};
/* Each IIR has 5 Filter Stages */
enum {
BAND1 = 0,
BAND2,
BAND3,
BAND4,
BAND5,
BAND_MAX,
};
enum {
COMPANDER_1, /* HPH_L */
COMPANDER_2, /* HPH_R */
COMPANDER_3, /* LO1_DIFF */
COMPANDER_4, /* LO2_DIFF */
COMPANDER_5, /* LO3_SE - not used in Tavil */
COMPANDER_6, /* LO4_SE - not used in Tavil */
COMPANDER_7, /* SWR SPK CH1 */
COMPANDER_8, /* SWR SPK CH2 */
COMPANDER_MAX,
};
enum {
AIF1_PB = 0,
AIF1_CAP,
AIF2_PB,
AIF2_CAP,
AIF3_PB,
AIF3_CAP,
AIF4_PB,
AIF4_VIFEED,
AIF4_MAD_TX,
NUM_CODEC_DAIS,
};
enum {
INTn_1_INP_SEL_ZERO = 0,
INTn_1_INP_SEL_DEC0,
INTn_1_INP_SEL_DEC1,
INTn_1_INP_SEL_IIR0,
INTn_1_INP_SEL_IIR1,
INTn_1_INP_SEL_RX0,
INTn_1_INP_SEL_RX1,
INTn_1_INP_SEL_RX2,
INTn_1_INP_SEL_RX3,
INTn_1_INP_SEL_RX4,
INTn_1_INP_SEL_RX5,
INTn_1_INP_SEL_RX6,
INTn_1_INP_SEL_RX7,
};
enum {
INTn_2_INP_SEL_ZERO = 0,
INTn_2_INP_SEL_RX0,
INTn_2_INP_SEL_RX1,
INTn_2_INP_SEL_RX2,
INTn_2_INP_SEL_RX3,
INTn_2_INP_SEL_RX4,
INTn_2_INP_SEL_RX5,
INTn_2_INP_SEL_RX6,
INTn_2_INP_SEL_RX7,
INTn_2_INP_SEL_PROXIMITY,
};
enum {
INTERP_MAIN_PATH,
INTERP_MIX_PATH,
};
struct interp_sample_rate {
int sample_rate;
int rate_val;
};
static struct interp_sample_rate sr_val_tbl[] = {
{8000, 0x0},
{16000, 0x1},
{32000, 0x3},
{48000, 0x4},
{96000, 0x5},
{192000, 0x6},
{384000, 0x7},
{44100, 0x9},
{88200, 0xA},
{176400, 0xB},
{352800, 0xC},
};
struct wcd_slim_codec_dai_data {
struct list_head slim_ch_list;
struct slim_stream_config sconfig;
struct slim_stream_runtime *sruntime;
};
static const struct regmap_range_cfg wcd934x_ifc_ranges[] = {
{
.name = "WCD9335-IFC-DEV",
.range_min = 0x0,
.range_max = 0xffff,
.selector_reg = 0x800,
.selector_mask = 0xfff,
.selector_shift = 0,
.window_start = 0x800,
.window_len = 0x400,
},
};
static struct regmap_config wcd934x_ifc_regmap_config = {
.reg_bits = 16,
.val_bits = 8,
.max_register = 0xffff,
.ranges = wcd934x_ifc_ranges,
.num_ranges = ARRAY_SIZE(wcd934x_ifc_ranges),
};
struct wcd934x_codec {
struct device *dev;
struct clk_hw hw;
struct clk *extclk;
struct regmap *regmap;
struct regmap *if_regmap;
struct slim_device *sdev;
struct slim_device *sidev;
struct wcd_clsh_ctrl *clsh_ctrl;
struct snd_soc_component *component;
struct wcd934x_slim_ch rx_chs[WCD934X_RX_MAX];
struct wcd934x_slim_ch tx_chs[WCD934X_TX_MAX];
struct wcd_slim_codec_dai_data dai[NUM_CODEC_DAIS];
int rate;
u32 version;
u32 hph_mode;
int num_rx_port;
int num_tx_port;
u32 tx_port_value[WCD934X_TX_MAX];
u32 rx_port_value[WCD934X_RX_MAX];
int sido_input_src;
int dmic_0_1_clk_cnt;
int dmic_2_3_clk_cnt;
int dmic_4_5_clk_cnt;
int dmic_sample_rate;
int comp_enabled[COMPANDER_MAX];
int sysclk_users;
struct mutex sysclk_mutex;
};
#define to_wcd934x_codec(_hw) container_of(_hw, struct wcd934x_codec, hw)
struct wcd_iir_filter_ctl {
unsigned int iir_idx;
unsigned int band_idx;
struct soc_bytes_ext bytes_ext;
};
static const DECLARE_TLV_DB_SCALE(digital_gain, 0, 1, 0);
static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
static const DECLARE_TLV_DB_SCALE(ear_pa_gain, 0, 150, 0);
/* Cutoff frequency for high pass filter */
static const char * const cf_text[] = {
"CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ"
};
static const char * const rx_cf_text[] = {
"CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ",
"CF_NEG_3DB_0P48HZ"
};
static const char * const rx_hph_mode_mux_text[] = {
"Class H Invalid", "Class-H Hi-Fi", "Class-H Low Power", "Class-AB",
"Class-H Hi-Fi Low Power"
};
static const char *const slim_rx_mux_text[] = {
"ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB",
};
static const char * const rx_int0_7_mix_mux_text[] = {
"ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
"RX6", "RX7", "PROXIMITY"
};
static const char * const rx_int_mix_mux_text[] = {
"ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
"RX6", "RX7"
};
static const char * const rx_prim_mix_text[] = {
"ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2",
"RX3", "RX4", "RX5", "RX6", "RX7"
};
static const char * const rx_sidetone_mix_text[] = {
"ZERO", "SRC0", "SRC1", "SRC_SUM"
};
static const char * const iir_inp_mux_text[] = {
"ZERO", "DEC0", "DEC1", "DEC2", "DEC3", "DEC4", "DEC5", "DEC6",
"DEC7", "DEC8", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", "RX6", "RX7"
};
static const char * const rx_int_dem_inp_mux_text[] = {
"NORMAL_DSM_OUT", "CLSH_DSM_OUT",
};
static const char * const rx_int0_1_interp_mux_text[] = {
"ZERO", "RX INT0_1 MIX1",
};
static const char * const rx_int1_1_interp_mux_text[] = {
"ZERO", "RX INT1_1 MIX1",
};
static const char * const rx_int2_1_interp_mux_text[] = {
"ZERO", "RX INT2_1 MIX1",
};
static const char * const rx_int3_1_interp_mux_text[] = {
"ZERO", "RX INT3_1 MIX1",
};
static const char * const rx_int4_1_interp_mux_text[] = {
"ZERO", "RX INT4_1 MIX1",
};
static const char * const rx_int7_1_interp_mux_text[] = {
"ZERO", "RX INT7_1 MIX1",
};
static const char * const rx_int8_1_interp_mux_text[] = {
"ZERO", "RX INT8_1 MIX1",
};
static const char * const rx_int0_2_interp_mux_text[] = {
"ZERO", "RX INT0_2 MUX",
};
static const char * const rx_int1_2_interp_mux_text[] = {
"ZERO", "RX INT1_2 MUX",
};
static const char * const rx_int2_2_interp_mux_text[] = {
"ZERO", "RX INT2_2 MUX",
};
static const char * const rx_int3_2_interp_mux_text[] = {
"ZERO", "RX INT3_2 MUX",
};
static const char * const rx_int4_2_interp_mux_text[] = {
"ZERO", "RX INT4_2 MUX",
};
static const char * const rx_int7_2_interp_mux_text[] = {
"ZERO", "RX INT7_2 MUX",
};
static const char * const rx_int8_2_interp_mux_text[] = {
"ZERO", "RX INT8_2 MUX",
};
static const char * const dmic_mux_text[] = {
"ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5"
};
static const char * const amic_mux_text[] = {
"ZERO", "ADC1", "ADC2", "ADC3", "ADC4"
};
static const char * const amic4_5_sel_text[] = {
"AMIC4", "AMIC5"
};
static const char * const adc_mux_text[] = {
"DMIC", "AMIC", "ANC_FB_TUNE1", "ANC_FB_TUNE2"
};
static const char * const cdc_if_tx0_mux_text[] = {
"ZERO", "RX_MIX_TX0", "DEC0", "DEC0_192"
};
static const char * const cdc_if_tx1_mux_text[] = {
"ZERO", "RX_MIX_TX1", "DEC1", "DEC1_192"
};
static const char * const cdc_if_tx2_mux_text[] = {
"ZERO", "RX_MIX_TX2", "DEC2", "DEC2_192"
};
static const char * const cdc_if_tx3_mux_text[] = {
"ZERO", "RX_MIX_TX3", "DEC3", "DEC3_192"
};
static const char * const cdc_if_tx4_mux_text[] = {
"ZERO", "RX_MIX_TX4", "DEC4", "DEC4_192"
};
static const char * const cdc_if_tx5_mux_text[] = {
"ZERO", "RX_MIX_TX5", "DEC5", "DEC5_192"
};
static const char * const cdc_if_tx6_mux_text[] = {
"ZERO", "RX_MIX_TX6", "DEC6", "DEC6_192"
};
static const char * const cdc_if_tx7_mux_text[] = {
"ZERO", "RX_MIX_TX7", "DEC7", "DEC7_192"
};
static const char * const cdc_if_tx8_mux_text[] = {
"ZERO", "RX_MIX_TX8", "DEC8", "DEC8_192"
};
static const char * const cdc_if_tx9_mux_text[] = {
"ZERO", "DEC7", "DEC7_192"
};
static const char * const cdc_if_tx10_mux_text[] = {
"ZERO", "DEC6", "DEC6_192"
};
static const char * const cdc_if_tx11_mux_text[] = {
"DEC_0_5", "DEC_9_12", "MAD_AUDIO", "MAD_BRDCST"
};
static const char * const cdc_if_tx11_inp1_mux_text[] = {
"ZERO", "DEC0", "DEC1", "DEC2", "DEC3", "DEC4",
"DEC5", "RX_MIX_TX5", "DEC9_10", "DEC11_12"
};
static const char * const cdc_if_tx13_mux_text[] = {
"CDC_DEC_5", "MAD_BRDCST"
};
static const char * const cdc_if_tx13_inp1_mux_text[] = {
"ZERO", "DEC5", "DEC5_192"
};
static const struct soc_enum cf_dec0_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_TX0_TX_PATH_CFG0, 5, 3, cf_text);
static const struct soc_enum cf_dec1_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_TX1_TX_PATH_CFG0, 5, 3, cf_text);
static const struct soc_enum cf_dec2_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_TX2_TX_PATH_CFG0, 5, 3, cf_text);
static const struct soc_enum cf_dec3_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_TX3_TX_PATH_CFG0, 5, 3, cf_text);
static const struct soc_enum cf_dec4_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_TX4_TX_PATH_CFG0, 5, 3, cf_text);
static const struct soc_enum cf_dec5_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_TX5_TX_PATH_CFG0, 5, 3, cf_text);
static const struct soc_enum cf_dec6_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_TX6_TX_PATH_CFG0, 5, 3, cf_text);
static const struct soc_enum cf_dec7_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_TX7_TX_PATH_CFG0, 5, 3, cf_text);
static const struct soc_enum cf_dec8_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_TX8_TX_PATH_CFG0, 5, 3, cf_text);
static const struct soc_enum cf_int0_1_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX0_RX_PATH_CFG2, 0, 4, rx_cf_text);
static SOC_ENUM_SINGLE_DECL(cf_int0_2_enum, WCD934X_CDC_RX0_RX_PATH_MIX_CFG, 2,
rx_cf_text);
static const struct soc_enum cf_int1_1_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX1_RX_PATH_CFG2, 0, 4, rx_cf_text);
static SOC_ENUM_SINGLE_DECL(cf_int1_2_enum, WCD934X_CDC_RX1_RX_PATH_MIX_CFG, 2,
rx_cf_text);
static const struct soc_enum cf_int2_1_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX2_RX_PATH_CFG2, 0, 4, rx_cf_text);
static SOC_ENUM_SINGLE_DECL(cf_int2_2_enum, WCD934X_CDC_RX2_RX_PATH_MIX_CFG, 2,
rx_cf_text);
static const struct soc_enum cf_int3_1_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX3_RX_PATH_CFG2, 0, 4, rx_cf_text);
static SOC_ENUM_SINGLE_DECL(cf_int3_2_enum, WCD934X_CDC_RX3_RX_PATH_MIX_CFG, 2,
rx_cf_text);
static const struct soc_enum cf_int4_1_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX4_RX_PATH_CFG2, 0, 4, rx_cf_text);
static SOC_ENUM_SINGLE_DECL(cf_int4_2_enum, WCD934X_CDC_RX4_RX_PATH_MIX_CFG, 2,
rx_cf_text);
static const struct soc_enum cf_int7_1_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX7_RX_PATH_CFG2, 0, 4, rx_cf_text);
static SOC_ENUM_SINGLE_DECL(cf_int7_2_enum, WCD934X_CDC_RX7_RX_PATH_MIX_CFG, 2,
rx_cf_text);
static const struct soc_enum cf_int8_1_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX8_RX_PATH_CFG2, 0, 4, rx_cf_text);
static SOC_ENUM_SINGLE_DECL(cf_int8_2_enum, WCD934X_CDC_RX8_RX_PATH_MIX_CFG, 2,
rx_cf_text);
static const struct soc_enum rx_hph_mode_mux_enum =
SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
rx_hph_mode_mux_text);
static const struct soc_enum slim_rx_mux_enum =
SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim_rx_mux_text), slim_rx_mux_text);
static const struct soc_enum rx_int0_2_mux_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG1, 0, 10,
rx_int0_7_mix_mux_text);
static const struct soc_enum rx_int1_2_mux_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG1, 0, 9,
rx_int_mix_mux_text);
static const struct soc_enum rx_int2_2_mux_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG1, 0, 9,
rx_int_mix_mux_text);
static const struct soc_enum rx_int3_2_mux_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG1, 0, 9,
rx_int_mix_mux_text);
static const struct soc_enum rx_int4_2_mux_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG1, 0, 9,
rx_int_mix_mux_text);
static const struct soc_enum rx_int7_2_mux_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG1, 0, 10,
rx_int0_7_mix_mux_text);
static const struct soc_enum rx_int8_2_mux_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG1, 0, 9,
rx_int_mix_mux_text);
static const struct soc_enum rx_int0_1_mix_inp0_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG0, 0, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int0_1_mix_inp1_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG0, 4, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int0_1_mix_inp2_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG1, 4, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int1_1_mix_inp0_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG0, 0, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int1_1_mix_inp1_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG0, 4, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int1_1_mix_inp2_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG1, 4, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int2_1_mix_inp0_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG0, 0, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int2_1_mix_inp1_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG0, 4, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int2_1_mix_inp2_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG1, 4, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int3_1_mix_inp0_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG0, 0, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int3_1_mix_inp1_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG0, 4, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int3_1_mix_inp2_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG1, 4, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int4_1_mix_inp0_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG0, 0, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int4_1_mix_inp1_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG0, 4, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int4_1_mix_inp2_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG1, 4, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int7_1_mix_inp0_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG0, 0, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int7_1_mix_inp1_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG0, 4, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int7_1_mix_inp2_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG1, 4, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int8_1_mix_inp0_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG0, 0, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int8_1_mix_inp1_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG0, 4, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int8_1_mix_inp2_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG1, 4, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int0_mix2_inp_mux_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 0, 4,
rx_sidetone_mix_text);
static const struct soc_enum rx_int1_mix2_inp_mux_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 2, 4,
rx_sidetone_mix_text);
static const struct soc_enum rx_int2_mix2_inp_mux_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 4, 4,
rx_sidetone_mix_text);
static const struct soc_enum rx_int3_mix2_inp_mux_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 6, 4,
rx_sidetone_mix_text);
static const struct soc_enum rx_int4_mix2_inp_mux_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1, 0, 4,
rx_sidetone_mix_text);
static const struct soc_enum rx_int7_mix2_inp_mux_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1, 2, 4,
rx_sidetone_mix_text);
static const struct soc_enum iir0_inp0_mux_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG0,
0, 18, iir_inp_mux_text);
static const struct soc_enum iir0_inp1_mux_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG1,
0, 18, iir_inp_mux_text);
static const struct soc_enum iir0_inp2_mux_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG2,
0, 18, iir_inp_mux_text);
static const struct soc_enum iir0_inp3_mux_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG3,
0, 18, iir_inp_mux_text);
static const struct soc_enum iir1_inp0_mux_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG0,
0, 18, iir_inp_mux_text);
static const struct soc_enum iir1_inp1_mux_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG1,
0, 18, iir_inp_mux_text);
static const struct soc_enum iir1_inp2_mux_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG2,
0, 18, iir_inp_mux_text);
static const struct soc_enum iir1_inp3_mux_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG3,
0, 18, iir_inp_mux_text);
static const struct soc_enum rx_int0_dem_inp_mux_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX0_RX_PATH_SEC0, 0,
ARRAY_SIZE(rx_int_dem_inp_mux_text),
rx_int_dem_inp_mux_text);
static const struct soc_enum rx_int1_dem_inp_mux_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX1_RX_PATH_SEC0, 0,
ARRAY_SIZE(rx_int_dem_inp_mux_text),
rx_int_dem_inp_mux_text);
static const struct soc_enum rx_int2_dem_inp_mux_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX2_RX_PATH_SEC0, 0,
ARRAY_SIZE(rx_int_dem_inp_mux_text),
rx_int_dem_inp_mux_text);
static const struct soc_enum tx_adc_mux0_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0,
ARRAY_SIZE(adc_mux_text), adc_mux_text);