From d8586375b88fb6a28d888f030f15418a353e29af Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 5 Nov 2014 19:01:19 +0000 Subject: [PATCH] R600/SI: Move all rsrc building functions to SIISelLowering git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221383 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/R600/AMDGPUISelDAGToDAG.cpp | 59 ++++---------------------- lib/Target/R600/SIISelLowering.cpp | 44 +++++++++++++++++++ lib/Target/R600/SIISelLowering.h | 8 ++++ 3 files changed, 61 insertions(+), 50 deletions(-) diff --git a/lib/Target/R600/AMDGPUISelDAGToDAG.cpp b/lib/Target/R600/AMDGPUISelDAGToDAG.cpp index face98fe148f..59f395bda618 100644 --- a/lib/Target/R600/AMDGPUISelDAGToDAG.cpp +++ b/lib/Target/R600/AMDGPUISelDAGToDAG.cpp @@ -944,52 +944,6 @@ bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc, return SelectMUBUFAddr64(Addr, SRsrc, VAddr, Offset); } -static SDValue buildSMovImm32(SelectionDAG *DAG, SDLoc DL, uint64_t Val) { - SDValue K = DAG->getTargetConstant(Val, MVT::i32); - return SDValue(DAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32, K), 0); -} - -static SDValue buildRSRC(SelectionDAG *DAG, SDLoc DL, SDValue Ptr, - uint32_t RsrcDword1, uint64_t RsrcDword2And3) { - SDValue PtrLo = DAG->getTargetExtractSubreg(AMDGPU::sub0, DL, MVT::i32, Ptr); - SDValue PtrHi = DAG->getTargetExtractSubreg(AMDGPU::sub1, DL, MVT::i32, Ptr); - if (RsrcDword1) { - PtrHi = SDValue(DAG->getMachineNode(AMDGPU::S_OR_B32, DL, MVT::i32, PtrHi, - DAG->getConstant(RsrcDword1, MVT::i32)), 0); - } - - SDValue DataLo = buildSMovImm32(DAG, DL, - RsrcDword2And3 & UINT64_C(0xFFFFFFFF)); - SDValue DataHi = buildSMovImm32(DAG, DL, RsrcDword2And3 >> 32); - - const SDValue Ops[] = { - DAG->getTargetConstant(AMDGPU::SReg_128RegClassID, MVT::i32), - PtrLo, - DAG->getTargetConstant(AMDGPU::sub0, MVT::i32), - PtrHi, - DAG->getTargetConstant(AMDGPU::sub1, MVT::i32), - DataLo, - DAG->getTargetConstant(AMDGPU::sub2, MVT::i32), - DataHi, - DAG->getTargetConstant(AMDGPU::sub3, MVT::i32) - }; - - return SDValue(DAG->getMachineNode(AMDGPU::REG_SEQUENCE, DL, - MVT::v4i32, Ops), 0); -} - -/// \brief Return a resource descriptor with the 'Add TID' bit enabled -/// The TID (Thread ID) is multipled by the stride value (bits [61:48] -/// of the resource descriptor) to create an offset, which is added to the -/// resource ponter. -static SDValue buildScratchRSRC(SelectionDAG *DAG, SDLoc DL, SDValue Ptr) { - - uint64_t Rsrc = AMDGPU::RSRC_DATA_FORMAT | AMDGPU::RSRC_TID_ENABLE | - 0xffffffff; // Size - - return buildRSRC(DAG, DL, Ptr, 0, Rsrc); -} - bool AMDGPUDAGToDAGISel::SelectMUBUFScratch(SDValue Addr, SDValue &Rsrc, SDValue &VAddr, SDValue &SOffset, SDValue &ImmOffset) const { @@ -1009,9 +963,10 @@ bool AMDGPUDAGToDAGISel::SelectMUBUFScratch(SDValue Addr, SDValue &Rsrc, Lowering.CreateLiveInRegister(*CurDAG, &AMDGPU::SReg_32RegClass, ScratchOffsetReg, MVT::i32); - Rsrc = buildScratchRSRC(CurDAG, DL, - CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, - MRI.getLiveInVirtReg(ScratchPtrReg), MVT::i64)); + SDValue ScratchPtr = + CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, + MRI.getLiveInVirtReg(ScratchPtrReg), MVT::i64); + Rsrc = SDValue(Lowering.buildScratchRSRC(*CurDAG, DL, ScratchPtr), 0); SOffset = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, MRI.getLiveInVirtReg(ScratchOffsetReg), MVT::i32); @@ -1064,7 +1019,11 @@ bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, uint64_t Rsrc = AMDGPU::RSRC_DATA_FORMAT | APInt::getAllOnesValue(32).getZExtValue(); // Size SDLoc DL(Addr); - SRsrc = buildRSRC(CurDAG, DL, Ptr, 0, Rsrc); + + const SITargetLowering& Lowering = + *static_cast(getTargetLowering()); + + SRsrc = SDValue(Lowering.buildRSRC(*CurDAG, DL, Ptr, 0, Rsrc), 0); return true; } return false; diff --git a/lib/Target/R600/SIISelLowering.cpp b/lib/Target/R600/SIISelLowering.cpp index b1788a2b1b35..207539f21d8d 100644 --- a/lib/Target/R600/SIISelLowering.cpp +++ b/lib/Target/R600/SIISelLowering.cpp @@ -2019,6 +2019,50 @@ MachineSDNode *SITargetLowering::wrapAddr64Rsrc(SelectionDAG &DAG, #endif } +/// \brief Return a resource descriptor with the 'Add TID' bit enabled +/// The TID (Thread ID) is multipled by the stride value (bits [61:48] +/// of the resource descriptor) to create an offset, which is added to the +/// resource ponter. +MachineSDNode *SITargetLowering::buildRSRC(SelectionDAG &DAG, + SDLoc DL, + SDValue Ptr, + uint32_t RsrcDword1, + uint64_t RsrcDword2And3) const { + SDValue PtrLo = DAG.getTargetExtractSubreg(AMDGPU::sub0, DL, MVT::i32, Ptr); + SDValue PtrHi = DAG.getTargetExtractSubreg(AMDGPU::sub1, DL, MVT::i32, Ptr); + if (RsrcDword1) { + PtrHi = SDValue(DAG.getMachineNode(AMDGPU::S_OR_B32, DL, MVT::i32, PtrHi, + DAG.getConstant(RsrcDword1, MVT::i32)), 0); + } + + SDValue DataLo = buildSMovImm32(DAG, DL, + RsrcDword2And3 & UINT64_C(0xFFFFFFFF)); + SDValue DataHi = buildSMovImm32(DAG, DL, RsrcDword2And3 >> 32); + + const SDValue Ops[] = { + DAG.getTargetConstant(AMDGPU::SReg_128RegClassID, MVT::i32), + PtrLo, + DAG.getTargetConstant(AMDGPU::sub0, MVT::i32), + PtrHi, + DAG.getTargetConstant(AMDGPU::sub1, MVT::i32), + DataLo, + DAG.getTargetConstant(AMDGPU::sub2, MVT::i32), + DataHi, + DAG.getTargetConstant(AMDGPU::sub3, MVT::i32) + }; + + return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops); +} + +MachineSDNode *SITargetLowering::buildScratchRSRC(SelectionDAG &DAG, + SDLoc DL, + SDValue Ptr) const { + uint64_t Rsrc = AMDGPU::RSRC_DATA_FORMAT | AMDGPU::RSRC_TID_ENABLE | + 0xffffffff; // Size + + return buildRSRC(DAG, DL, Ptr, 0, Rsrc); +} + MachineSDNode *SITargetLowering::AdjustRegClass(MachineSDNode *N, SelectionDAG &DAG) const { diff --git a/lib/Target/R600/SIISelLowering.h b/lib/Target/R600/SIISelLowering.h index be8c951e6b93..0ba89e8d7173 100644 --- a/lib/Target/R600/SIISelLowering.h +++ b/lib/Target/R600/SIISelLowering.h @@ -107,6 +107,14 @@ class SITargetLowering : public AMDGPUTargetLowering { void legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const; MachineSDNode *wrapAddr64Rsrc(SelectionDAG &DAG, SDLoc DL, SDValue Ptr) const; + MachineSDNode *buildRSRC(SelectionDAG &DAG, + SDLoc DL, + SDValue Ptr, + uint32_t RsrcDword1, + uint64_t RsrcDword2And3) const; + MachineSDNode *buildScratchRSRC(SelectionDAG &DAG, + SDLoc DL, + SDValue Ptr) const; }; } // End namespace llvm