diff --git a/soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_power.h b/soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_power.h
index 13fb476d96a467..b16d64bb653e97 100644
--- a/soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_power.h
+++ b/soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_power.h
@@ -9,7 +9,7 @@
 #define ZEPHYR_SOC_INTEL_ADSP_POWER_H_
 
 /* Value used as delay when waiting for hw register state change. */
-#define HW_STATE_CHECK_DELAY 256
+#define HW_STATE_CHECK_DELAY 64
 
 /* Power Control register - controls the power domain operations. */
 struct ace_pwrctl {
diff --git a/soc/xtensa/intel_adsp/ace/include/intel_ace20_lnl/adsp_power.h b/soc/xtensa/intel_adsp/ace/include/intel_ace20_lnl/adsp_power.h
index 51369b4456b2df..9210a0a7f835b6 100644
--- a/soc/xtensa/intel_adsp/ace/include/intel_ace20_lnl/adsp_power.h
+++ b/soc/xtensa/intel_adsp/ace/include/intel_ace20_lnl/adsp_power.h
@@ -7,7 +7,7 @@
 #define ZEPHYR_SOC_INTEL_ADSP_POWER_H_
 
 /* Value used as delay when waiting for hw register state change. */
-#define HW_STATE_CHECK_DELAY 256
+#define HW_STATE_CHECK_DELAY  64
 
 
 struct ace_pwrctl {
diff --git a/soc/xtensa/intel_adsp/ace/multiprocessing.c b/soc/xtensa/intel_adsp/ace/multiprocessing.c
index f2f0cd3f1d6d1e..e78295641530c8 100644
--- a/soc/xtensa/intel_adsp/ace/multiprocessing.c
+++ b/soc/xtensa/intel_adsp/ace/multiprocessing.c
@@ -18,7 +18,7 @@
 #include <zephyr/irq.h>
 #include <zephyr/cache.h>
 
-#define CORE_POWER_CHECK_NUM 32
+#define CORE_POWER_CHECK_NUM 128
 #define ACE_INTC_IRQ DT_IRQN(DT_NODELABEL(ace_intc))
 
 static void ipc_isr(void *arg)