From e01f71cd93d9903c90e006d5e9e1e0db7cc7521f Mon Sep 17 00:00:00 2001 From: Julian Stecklina Date: Tue, 13 Aug 2013 13:58:31 +0200 Subject: [PATCH] Prefix macros with VMM_ to reduce name clashes. --- executor/build_instructions.py | 44 ++++++++--------- executor/instcache.h | 12 ++--- include/model/reg.h | 66 ++++++++++++------------- model/ahcicontroller.cc | 88 +++++++++++++++++----------------- model/idecontroller.cc | 22 ++++----- model/lapic.cc | 40 ++++++++-------- model/pcihostbridge.cc | 14 +++--- model/rtl8029.cc | 18 +++---- model/vcpu.cc | 52 ++++++++++---------- 9 files changed, 178 insertions(+), 178 deletions(-) diff --git a/executor/build_instructions.py b/executor/build_instructions.py index 3e2025db..8bde53e3 100755 --- a/executor/build_instructions.py +++ b/executor/build_instructions.py @@ -133,9 +133,9 @@ def generate_functions(name, flags, snippet, enc, functions, l2): # Be sure to duplicate %s snippet = ['asm volatile("'+ ";".join([re.sub(r'([^%])%([^%0-9])', r'\1%%\2', s) for s in snippet])+'" : "+d"(tmp_src), "+c"(tmp_dst) : : "eax")'] if "FPU" in flags: - if "FPUNORESTORE" not in flags: snippet = ['fxrstor (%%\" EXPAND(REG(ax)) \")'] + snippet + if "FPUNORESTORE" not in flags: snippet = ['fxrstor (%%\" VMM_EXPAND(VMM_REG(ax)) \")'] + snippet snippet = ['if (cache->_cpu->cr0 & 0xc) EXCEPTION(cache, 0x7, 0)', - 'asm volatile("' + ';'.join(snippet)+'; fxsave (%%\" EXPAND(REG(ax)) \");" : "+d"(tmp_src), "+c"(tmp_dst) : "a"(cache->_fpustate))'] + 'asm volatile("' + ';'.join(snippet)+'; fxsave (%%\" VMM_EXPAND(VMM_REG(ax)) \");" : "+d"(tmp_src), "+c"(tmp_dst) : "a"(cache->_fpustate))'] if "CPL0" in flags: snippet = ["if (cache->cpl0_test()) return"] + snippet # parameter handling @@ -294,10 +294,10 @@ def print_code(code, functions): ("stc", ["NO_OS"], ["cache->_cpu->efl |= 1"]), ("cld", ["NO_OS"], ["cache->_cpu->efl &= ~0x400"]), ("std", ["NO_OS"], ["cache->_cpu->efl |= 0x400"]), - ("bswap", ["NO_OS", "ASM"], ["mov (%\" EXPAND(REG(cx)) \"), %eax", "bswap %eax", "mov %eax, (%\" EXPAND(REG(cx)) \")"]), - ("xchg", ["ASM", "RMW"], ["mov (%\" EXPAND(REG(dx)) \"), [EAX]", "[lock] xchg[bwl] [EAX], (%\" EXPAND(REG(cx)) \")", "mov [EAX], (%\" EXPAND(REG(dx)) \")"]), - ("cwtl", ["ASM", "EAX"], ["mov (%\" EXPAND(REG(cx)) \"), [EAX]", "[data16] cwde", "mov [EAX], (%\" EXPAND(REG(cx)) \")"]), - ("cltd", ["ASM", "EAX", "EDX", "DIRECTION"], ["mov (%\" EXPAND(REG(dx)) \"), %eax", "[data16] cltd", "mov %\" EXPAND(REG(dx)) \", (%\" EXPAND(REG(cx)) \")"]), + ("bswap", ["NO_OS", "ASM"], ["mov (%\" VMM_EXPAND(VMM_REG(cx)) \"), %eax", "bswap %eax", "mov %eax, (%\" VMM_EXPAND(VMM_REG(cx)) \")"]), + ("xchg", ["ASM", "RMW"], ["mov (%\" VMM_EXPAND(VMM_REG(dx)) \"), [EAX]", "[lock] xchg[bwl] [EAX], (%\" VMM_EXPAND(VMM_REG(cx)) \")", "mov [EAX], (%\" VMM_EXPAND(VMM_REG(dx)) \")"]), + ("cwtl", ["ASM", "EAX"], ["mov (%\" VMM_EXPAND(VMM_REG(cx)) \"), [EAX]", "[data16] cwde", "mov [EAX], (%\" VMM_EXPAND(VMM_REG(cx)) \")"]), + ("cltd", ["ASM", "EAX", "EDX", "DIRECTION"], ["mov (%\" VMM_EXPAND(VMM_REG(dx)) \"), %eax", "[data16] cltd", "mov %\" VMM_EXPAND(VMM_REG(dx)) \", (%\" VMM_EXPAND(VMM_REG(cx)) \")"]), ("str", ["NO_OS", "OS1"], ["move<1>(tmp_dst, &cache->_cpu->tr.sel)"]), ("sldt", ["NO_OS", "OS1"], ["move<1>(tmp_dst, &cache->_cpu->ld.sel)"]), ("smsw", ["NO_OS", "OS1"], ["move<1>(tmp_dst, &cache->_cpu->cr0)"]), @@ -307,26 +307,26 @@ def print_code(code, functions): ("clflush", ["ASM", "BYTE"], [""]), ] opcodes += [(x, ["ASM", "EAX", "NO_OS", x in ["aaa", "aas"] and "LOADFLAGS", "SAVEFLAGS"], - ["#ifdef __x86_64__\n\tLogging::panic(\"Unable to execute '" + x + "'\\n\");\n#else\n\tasm volatile(\"mov (%%\" EXPAND(REG(cx)) \"), %%eax;" + x + ";mov %%eax, (%%\" EXPAND(REG(cx)) \")\" : \"+d\"(tmp_src), \"+c\"(tmp_dst) : : \"eax\");\n#endif\n"]) + ["#ifdef __x86_64__\n\tLogging::panic(\"Unable to execute '" + x + "'\\n\");\n#else\n\tasm volatile(\"mov (%%\" VMM_EXPAND(VMM_REG(cx)) \"), %%eax;" + x + ";mov %%eax, (%%\" VMM_EXPAND(VMM_REG(cx)) \")\" : \"+d\"(tmp_src), \"+c\"(tmp_dst) : : \"eax\");\n#endif\n"]) for x in ["aaa", "aas", "daa", "das"]] opcodes += [(x, ["ASM", x in ["cmp", "test"] and "READONLY", x in ["adc", "sbb"] and "LOADFLAGS", x not in ["mov"] and "SAVEFLAGS", x not in ["mov", "cmp", "test"] and "RMW", ], - ["mov[bwl] (%\" EXPAND(REG(dx)) \"), [EAX]", "[lock] %s[bwl] [EAX],(%%\" EXPAND(REG(cx)) \")"%x]) + ["mov[bwl] (%\" VMM_EXPAND(VMM_REG(dx)) \"), [EAX]", "[lock] %s[bwl] [EAX],(%%\" VMM_EXPAND(VMM_REG(cx)) \")"%x]) for x in ["mov", "add", "adc", "sub", "sbb", "and", "or", "xor", "cmp", "test"]] opcodes += [(x, ["ASM", x not in ["not"] and "SAVEFLAGS", x in ["dec", "inc"] and "LOADFLAGS", "RMW"], - ["[lock] " + x + "[bwl] (%\" EXPAND(REG(cx)) \")"]) + ["[lock] " + x + "[bwl] (%\" VMM_EXPAND(VMM_REG(cx)) \")"]) for x in ["inc", "dec", "neg", "not"]] opcodes += [(x, ["ASM", "CONST1", x in ["rcr", "rcl"] and "LOADFLAGS", "SAVEFLAGS", "RMW"], - ["xchg %\" EXPAND(REG(dx)) \", %\" EXPAND(REG(cx)) \"","movb (%\" EXPAND(REG(cx)) \"),%cl", "%s[bwl] %%cl, (%%\" EXPAND(REG(dx)) \")"%x]) for x in ["rol", "ror", "rcl", "rcr", "shl", "shr", "sar"]] -opcodes += [(x, ["ASM", "SAVEFLAGS", "DIRECTION"], ["%s[bwl] (%%\" EXPAND(REG(dx)) \"), [EAX]"%x, "mov [EAX], (%\" EXPAND(REG(cx)) \")"]) for x in ["bsf", "bsr"]] + ["xchg %\" VMM_EXPAND(VMM_REG(dx)) \", %\" VMM_EXPAND(VMM_REG(cx)) \"","movb (%\" VMM_EXPAND(VMM_REG(cx)) \"),%cl", "%s[bwl] %%cl, (%%\" VMM_EXPAND(VMM_REG(dx)) \")"%x]) for x in ["rol", "ror", "rcl", "rcr", "shl", "shr", "sar"]] +opcodes += [(x, ["ASM", "SAVEFLAGS", "DIRECTION"], ["%s[bwl] (%%\" VMM_EXPAND(VMM_REG(dx)) \"), [EAX]"%x, "mov [EAX], (%\" VMM_EXPAND(VMM_REG(cx)) \")"]) for x in ["bsf", "bsr"]] ccflags = map(lambda x: compile_and_disassemble(".byte %#x, 0x00"%x, file, fdict)[2].split()[0][1:], range(0x70, 0x80)) for i in range(len(ccflags)): ccflag = ccflags[i] - opcodes += [("set" +ccflag, ["BYTE", "ASM", "LOADFLAGS"], ["set%s (%%\" EXPAND(REG(cx)) \")"%ccflag])] - opcodes += [("cmov"+ccflag, ["NO_OS", "ASM", "LOADFLAGS", "OS2"], ["j%s 1f"%(ccflags[i ^ 1]), "mov (%\" EXPAND(REG(dx)) \"), %eax", "mov %eax, (%\" EXPAND(REG(cx)) \")", "1:"])] + opcodes += [("set" +ccflag, ["BYTE", "ASM", "LOADFLAGS"], ["set%s (%%\" VMM_EXPAND(VMM_REG(cx)) \")"%ccflag])] + opcodes += [("cmov"+ccflag, ["NO_OS", "ASM", "LOADFLAGS", "OS2"], ["j%s 1f"%(ccflags[i ^ 1]), "mov (%\" VMM_EXPAND(VMM_REG(dx)) \"), %eax", "mov %eax, (%\" VMM_EXPAND(VMM_REG(cx)) \")", "1:"])] # use call %P0 instead of call %c0; seems to be a gcc-bug that occurs with -mcmodel=large # (see http://gcc.gnu.org/bugzilla/show_bug.cgi?id=46477) opcodes += [("j"+ccflag, ["JMP", "ASM", "LOADFLAGS", "DIRECTION"], @@ -379,7 +379,7 @@ def add_helper(l, flags, params): "asm volatile (\"1: ;" "%s[bwl] (%%2);" "xor %%2, %%2;" - "2: ; .section .data.fixup2; \" ASM_WORD_TYPE \" 1b, 2b, 2b-1b; .previous;" + "2: ; .section .data.fixup2; \" VMM_ASM_WORD_TYPE \" 1b, 2b, 2b-1b; .previous;" "\" : \"+a\"(eax), \"+d\"(edx), \"+c\"(tmp_src))"%x, "if (tmp_src) DE0(cache)", "cache->_cpu->eax = eax", @@ -388,15 +388,15 @@ def add_helper(l, flags, params): opcodes += [(x, ["RMW"], ["unsigned count", "if ([IMM]) count = cache->_entry->immediate; else count = cache->_cpu->ecx", "tmp_src = cache->get_reg32((cache->_entry->data[cache->_entry->offset_opcode] >> 3) & 0x7)", - 'asm volatile ("xchg %%\" EXPAND(REG(ax)) \", %%\" EXPAND(REG(cx)) \"; mov (%%\" EXPAND(REG(dx)) \"), %%edx; [data16] '+ - x+' %%cl, %%\" EXPAND(REG(dx)) \", (%%\" EXPAND(REG(ax)) \"); pushf; pop %%" EXPAND(REG(ax)) : "+a"(count), "+d"(tmp_src), "+c"(tmp_dst))', + 'asm volatile ("xchg %%\" VMM_EXPAND(VMM_REG(ax)) \", %%\" VMM_EXPAND(VMM_REG(cx)) \"; mov (%%\" VMM_EXPAND(VMM_REG(dx)) \"), %%edx; [data16] '+ + x+' %%cl, %%\" VMM_EXPAND(VMM_REG(dx)) \", (%%\" VMM_EXPAND(VMM_REG(ax)) \"); pushf; pop %%" VMM_EXPAND(VMM_REG(ax)) : "+a"(count), "+d"(tmp_src), "+c"(tmp_dst))', "cache->_cpu->efl = (cache->_cpu->efl & ~0x8d5) | (count & 0x8d5)"]) for x in ["shrd", "shld"]] opcodes += [("imul", ["DIRECTION"], ["unsigned param, result", "tmp_dst = cache->get_reg32((cache->_entry->data[cache->_entry->offset_opcode] >> 3) & 0x7)", "if ([IMM]) param = cache->_entry->immediate; else if ([OP1]) param = cache->_cpu->eax; else move<[os]>(¶m, tmp_dst);", # 'Logging::printf("IMUL %x * %x\\n", param, *reinterpret_cast(tmp_src))', - 'asm volatile ("imul[bwl] (%%\" EXPAND(REG(cx)) \"); pushf; pop %%" EXPAND(REG(cx)) : "+a"(param), "=d"(result), "+c"(tmp_src))', + 'asm volatile ("imul[bwl] (%%\" VMM_EXPAND(VMM_REG(cx)) \"); pushf; pop %%" VMM_EXPAND(VMM_REG(cx)) : "+a"(param), "=d"(result), "+c"(tmp_src))', "cache->_cpu->efl = (cache->_cpu->efl & ~0x8d5) | (reinterpret_cast(tmp_src) & 0x8d5)", "if ([OP1]) move<[os] ? [os] : 1>(&cache->_cpu->eax, ¶m)", "if ([OP1] && [os]) move<[os]>(&cache->_cpu->edx, &result)", @@ -422,17 +422,17 @@ def add_helper(l, flags, params): ("pop %"+x, [], ["unsigned sel", "cache->helper_POP<[os]>(&sel) || cache->set_segment(&cache->_cpu->%s, sel)"%x, x == "ss" and "cache->_cpu->intr_state |= 2" or ""]), ("l"+x, ["SKIPMODRM", "MODRM", "MEMONLY"], ["cache->helper_loadsegment<[os]>(&cache->_cpu->%s)"%x])] opcodes += [(x, ["FPU", "FPUNORESTORE", "NO_OS"], [x]) for x in ["fninit"]] -opcodes += [(x, ["FPU", "NO_OS"], [x+" (%%\" EXPAND(REG(cx)) \")"]) for x in ["fnstsw", "fnstcw", "ficom", "ficomp"]] -opcodes += [(x, ["FPU", "NO_OS", "EAX"], ["fnstsw (%%\" EXPAND(REG(cx)) \")"]) for x in ["fnstsw %ax"]] +opcodes += [(x, ["FPU", "NO_OS"], [x+" (%%\" VMM_EXPAND(VMM_REG(cx)) \")"]) for x in ["fnstsw", "fnstcw", "ficom", "ficomp"]] +opcodes += [(x, ["FPU", "NO_OS", "EAX"], ["fnstsw (%%\" VMM_EXPAND(VMM_REG(cx)) \")"]) for x in ["fnstsw %ax"]] opcodes += [(".byte 0xdb, 0xe4 ", ["NO_OS", "COMPLETE"], ["/* fnsetpm, on 287 only, noop afterwards */"])] -opcodes += [(x, [x not in ["bt"] and "RMW" or "READONLY", "SAVEFLAGS", "BITS", "ASM"], ["mov (%\" EXPAND(REG(dx)) \"), %eax", +opcodes += [(x, [x not in ["bt"] and "RMW" or "READONLY", "SAVEFLAGS", "BITS", "ASM"], ["mov (%\" VMM_EXPAND(VMM_REG(dx)) \"), %eax", "and $(8<<[os])-1, %eax", - "[lock] "+x+" [EAX],(%\" EXPAND(REG(cx)) \")"]) for x in ["bt", "btc", "bts", "btr"]] + "[lock] "+x+" [EAX],(%\" VMM_EXPAND(VMM_REG(cx)) \")"]) for x in ["bt", "btc", "bts", "btr"]] opcodes += [("cmpxchg", ["RMW"], ['char res; asm volatile("mov (%2), %2; [lock] cmpxchg [EDX], (%3); setz %1" : "+a"(cache->_cpu->eax), "=d"(res) : "d"(tmp_src), "c"(tmp_dst))', "if (res) cache->_cpu->efl |= EFL_ZF; else cache->_cpu->efl &= EFL_ZF"])] opcodes += [("cmpxchg8b", ["RMW", "NO_OS", "QWORD"], ['char res; asm volatile("[lock] cmpxchg8b (%3); setz %2" : "+a"(cache->_cpu->eax), "+d"(cache->_cpu->edx), "=c"(res) : "D"(tmp_dst), "b"(cache->_cpu->ebx), "c"(cache->_cpu->ecx))', "if (res) cache->_cpu->efl |= EFL_ZF; else cache->_cpu->efl &= EFL_ZF"])] -opcodes += [("xadd", ["RMW", "ASM", "SAVEFLAGS"], ['mov (%\" EXPAND(REG(dx)) \"), [EAX]', '[lock] xadd [EAX], (%\" EXPAND(REG(cx)) \")', 'mov [EAX], (%\" EXPAND(REG(dx)) \")'])] +opcodes += [("xadd", ["RMW", "ASM", "SAVEFLAGS"], ['mov (%\" VMM_EXPAND(VMM_REG(dx)) \"), [EAX]', '[lock] xadd [EAX], (%\" VMM_EXPAND(VMM_REG(cx)) \")', 'mov [EAX], (%\" VMM_EXPAND(VMM_REG(dx)) \")'])] # unimplemented instructions opcodes += [(x, [], []) for x in ["vmcall", "vmlaunch", "vmresume", "vmxoff", "vmptrld", "vmptrst", "vmread", "vmwrite"]] # , "vmxon", "vmclear" diff --git a/executor/instcache.h b/executor/instcache.h index d6310f7a..c159e9b8 100644 --- a/executor/instcache.h +++ b/executor/instcache.h @@ -18,15 +18,15 @@ #pragma once #ifdef __i386__ -#define REG(X) e ## X -#define ASM_WORD_TYPE ".long" +#define VMM_REG(X) e ## X +#define VMM_ASM_WORD_TYPE ".long" #else -#define REG(X) r ## X -#define ASM_WORD_TYPE ".quad" +#define VMM_REG(X) r ## X +#define VMM_ASM_WORD_TYPE ".quad" #endif -#define STRING(x) # x -#define EXPAND(x) STRING(x) +#define VMM_STRING(x) # x +#define VMM_EXPAND(x) VMM_STRING(x) /** * Reverse MTR mapping. diff --git a/include/model/reg.h b/include/model/reg.h index 0415f412..17c67cf3 100644 --- a/include/model/reg.h +++ b/include/model/reg.h @@ -15,44 +15,44 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * General Public License version 2 for more details. */ -#define DEFINE_REG(NAME, OFFSET, VALUE, MASK) private: unsigned NAME; public: static const unsigned NAME##_offset = OFFSET; static const unsigned NAME##_mask = MASK; static const unsigned NAME##_reset = VALUE; -#define REG_RO(NAME, OFFSET, VALUE) REG(NAME, OFFSET, static const unsigned NAME = VALUE;, value = VALUE; , break; , ) -#define REG_RW(NAME, OFFSET, VALUE, MASK, WRITE_CALLBACK) REG(NAME, OFFSET, DEFINE_REG(NAME, OFFSET, VALUE, MASK) , value = NAME; , if (!MASK) return false; if (strict && value & ~MASK) return false; NAME = (NAME & ~MASK) | (value & MASK); WRITE_CALLBACK; , NAME=VALUE;) -#define REG_WR(NAME, OFFSET, VALUE, MASK, RW1S, RW1C, WRITE_CALLBACK) REG(NAME, OFFSET, DEFINE_REG(NAME, OFFSET, VALUE, MASK), value = NAME; , if (!MASK) return false; unsigned oldvalue = NAME; value = value & ~RW1S | ( value | oldvalue) & RW1S; value = value & ~RW1C | (~value & oldvalue) & RW1C; NAME = (NAME & ~MASK) | (value & MASK); WRITE_CALLBACK; , NAME = VALUE;) -#define REGSET(NAME, ...) private: __VA_ARGS__ -#define REG(NAME, OFFSET, MEMBER, READ, WRITE, RESET) MEMBER -#include REGBASE -#undef REG -#undef REGSET -#define REGSET(NAME, ...) bool NAME##_read(unsigned offset, unsigned &value) { switch (offset) { __VA_ARGS__ default: break; } return false; } -#define REG(NAME, OFFSET, MEMBER, READ, WRITE, RESET) case OFFSET: { READ }; return true; -#include REGBASE -#undef REG -#undef REGSET -#define REGSET(NAME, ...) bool NAME##_write(unsigned offset, unsigned value, bool strict=false) { switch (offset) { __VA_ARGS__ default: break; } return 0; } -#define REG(NAME, OFFSET, MEMBER, READ, WRITE, RESET) case OFFSET: { WRITE }; return true; -#include REGBASE -#undef REG -#undef REGSET -#define REGSET(NAME, ...) void NAME##_reset() { __VA_ARGS__ }; private: -#define REG(NAME, OFFSET, MEMBER, READ, WRITE, RESET) RESET -#include REGBASE -#undef REG -#undef REGSET -#undef REG_WR -#undef REG_RW -#undef REG_RO -#undef DEFINE_REG -#undef REGBASE +#define VMM_DEFINE_REG(NAME, OFFSET, VALUE, MASK) private: unsigned NAME; public: static const unsigned NAME##_offset = OFFSET; static const unsigned NAME##_mask = MASK; static const unsigned NAME##_reset = VALUE; +#define VMM_REG_RO(NAME, OFFSET, VALUE) VMM_REG(NAME, OFFSET, static const unsigned NAME = VALUE;, value = VALUE; , break; , ) +#define VMM_REG_RW(NAME, OFFSET, VALUE, MASK, WRITE_CALLBACK) VMM_REG(NAME, OFFSET, VMM_DEFINE_REG(NAME, OFFSET, VALUE, MASK) , value = NAME; , if (!MASK) return false; if (strict && value & ~MASK) return false; NAME = (NAME & ~MASK) | (value & MASK); WRITE_CALLBACK; , NAME=VALUE;) +#define VMM_REG_WR(NAME, OFFSET, VALUE, MASK, RW1S, RW1C, WRITE_CALLBACK) VMM_REG(NAME, OFFSET, VMM_DEFINE_REG(NAME, OFFSET, VALUE, MASK), value = NAME; , if (!MASK) return false; unsigned oldvalue = NAME; value = value & ~RW1S | ( value | oldvalue) & RW1S; value = value & ~RW1C | (~value & oldvalue) & RW1C; NAME = (NAME & ~MASK) | (value & MASK); WRITE_CALLBACK; , NAME = VALUE;) +#define VMM_REGSET(NAME, ...) private: __VA_ARGS__ +#define VMM_REG(NAME, OFFSET, MEMBER, READ, WRITE, RESET) MEMBER +#include VMM_REGBASE +#undef VMM_REG +#undef VMM_REGSET +#define VMM_REGSET(NAME, ...) bool NAME##_read(unsigned offset, unsigned &value) { switch (offset) { __VA_ARGS__ default: break; } return false; } +#define VMM_REG(NAME, OFFSET, MEMBER, READ, WRITE, RESET) case OFFSET: { READ }; return true; +#include VMM_REGBASE +#undef VMM_REG +#undef VMM_REGSET +#define VMM_REGSET(NAME, ...) bool NAME##_write(unsigned offset, unsigned value, bool strict=false) { switch (offset) { __VA_ARGS__ default: break; } return 0; } +#define VMM_REG(NAME, OFFSET, MEMBER, READ, WRITE, RESET) case OFFSET: { WRITE }; return true; +#include VMM_REGBASE +#undef VMM_REG +#undef VMM_REGSET +#define VMM_REGSET(NAME, ...) void NAME##_reset() { __VA_ARGS__ }; private: +#define VMM_REG(NAME, OFFSET, MEMBER, READ, WRITE, RESET) RESET +#include VMM_REGBASE +#undef VMM_REG +#undef VMM_REGSET +#undef VMM_REG_WR +#undef VMM_REG_RW +#undef VMM_REG_RO +#undef VMM_DEFINE_REG +#undef VMM_REGBASE /** - * \def REG_RO(NAME, OFFSET, VALUE) + * \def VMM_REG_RO(NAME, OFFSET, VALUE) * * Defines a read-only register. */ /** - * \def REG_RW(NAME, OFFSET, VALUE, MASK, WRITE_CALLBACK) + * \def VMM_REG_RW(NAME, OFFSET, VALUE, MASK, WRITE_CALLBACK) * * Defines a read/write register. * @@ -64,7 +64,7 @@ */ /** - * \def REG_WR(NAME, OFFSET, VALUE, MASK, RW1S, RW1C, WRITE_CALLBACK) + * \def VMM_REG_WR(NAME, OFFSET, VALUE, MASK, RW1S, RW1C, WRITE_CALLBACK) * * Defines a read/write register with set/clear bits. * @@ -78,7 +78,7 @@ */ /** - * \def REGSET(NAME, ...) + * \def VMM_REGSET(NAME, ...) * * Defines a set of registers. */ diff --git a/model/ahcicontroller.cc b/model/ahcicontroller.cc index 239db8dc..bdbc9f86 100644 --- a/model/ahcicontroller.cc +++ b/model/ahcicontroller.cc @@ -16,7 +16,7 @@ * General Public License version 2 for more details. */ -#ifndef REGBASE +#ifndef VMM_REGBASE #include "nul/motherboard.h" #include "model/sata.h" #include "model/pci.h" @@ -45,7 +45,7 @@ class AhciPort : public FisReceiver bool _need_initial_fis; -#define REGBASE "../model/ahcicontroller.cc" +#define VMM_REGBASE "../model/ahcicontroller.cc" #include "model/reg.h" public: @@ -203,14 +203,14 @@ class AhciPort : public FisReceiver #else #ifndef AHCI_CONTROLLER -REGSET(AhciPort, - REG_RW(PxCLB, 0x0, 0, 0xfffffc00,) - REG_RO(PxCLBU, 0x4, 0) - REG_RW(PxFB, 0x8, 0, 0xffffff00,) - REG_RO(PxFBU, 0xc, 0) - REG_WR(PxIS, 0x10, 0, 0xdfc000af, 0, 0xdfc000af, COUNTER_INC("IS");) - REG_RW(PxIE, 0x14, 0, 0x7dc0007f,) - REG_WR(PxCMD, 0x18, 0, 0xf3000011, 0, 0, +VMM_REGSET(AhciPort, + VMM_REG_RW(PxCLB, 0x0, 0, 0xfffffc00,) + VMM_REG_RO(PxCLBU, 0x4, 0) + VMM_REG_RW(PxFB, 0x8, 0, 0xffffff00,) + VMM_REG_RO(PxFBU, 0xc, 0) + VMM_REG_WR(PxIS, 0x10, 0, 0xdfc000af, 0, 0xdfc000af, COUNTER_INC("IS");) + VMM_REG_RW(PxIE, 0x14, 0, 0x7dc0007f,) + VMM_REG_WR(PxCMD, 0x18, 0, 0xf3000011, 0, 0, // enable FRE if ( PxCMD & 0x10 && ~oldvalue & 0x10) PxCMD |= 1 << 14; // disable FRE @@ -226,10 +226,10 @@ REGSET(AhciPort, PxCI = PxCI_reset; } ) - REG_RW(PxTFD, 0x20, 0x7f, 0,) - REG_RW(PxSIG, 0x24, 0xffffffff, 0,) - REG_RW(PxSSTS, 0x28, 0, 0,) - REG_RW(PxSCTL, 0x2c, 0, 0x00000fff, + VMM_REG_RW(PxTFD, 0x20, 0x7f, 0,) + VMM_REG_RW(PxSIG, 0x24, 0xffffffff, 0,) + VMM_REG_RW(PxSSTS, 0x28, 0, 0,) + VMM_REG_RW(PxSCTL, 0x2c, 0, 0x00000fff, switch (PxSCTL & 0xf) { case 1: comreset(); break; case 2: @@ -238,34 +238,34 @@ REGSET(AhciPort, default: break; }) - REG_WR(PxSERR, 0x30, 0, 0xffffffff, 0, 0xffffffff, ) - REG_WR(PxSACT, 0x34, 0, 0xffffffff, 0xffffffff, 0, ) - REG_WR(PxCI, 0x38, 0, 0xffffffff, 0xffffffff, 0, execute_command(PxCI); ) - REG_RO(PxSNTF, 0x3c, 0) - REG_RO(PxFBS, 0x40, 0)); + VMM_REG_WR(PxSERR, 0x30, 0, 0xffffffff, 0, 0xffffffff, ) + VMM_REG_WR(PxSACT, 0x34, 0, 0xffffffff, 0xffffffff, 0, ) + VMM_REG_WR(PxCI, 0x38, 0, 0xffffffff, 0xffffffff, 0, execute_command(PxCI); ) + VMM_REG_RO(PxSNTF, 0x3c, 0) + VMM_REG_RO(PxFBS, 0x40, 0)); #else -REGSET(PCI, - REG_RO(PCI_ID, 0x0, 0x275c8086) - REG_RW(PCI_CMD_STS, 0x1, 0x100000, 0x0406,) - REG_RO(PCI_RID_CC, 0x2, 0x01060102) - REG_RW(PCI_ABAR, 0x9, 0, 0xffffe000,) - REG_RO(PCI_SS, 0xb, 0x275c8086) - REG_RO(PCI_CAP, 0xd, 0x80) - REG_RW(PCI_INTR, 0xf, 0x0100, 0xff,) - REG_RO(PCI_PID_PC, 0x20, 0x00008801) - REG_RO(PCI_PMCS, 0x21, 0x0000) - REG_RW(PCI_MSI_CTRL, 0x22, 0x00000005, 0x10000,) - REG_RW(PCI_MSI_ADDR, 0x23, 0, 0xffffffff,) - REG_RW(PCI_MSI_DATA, 0x24, 0, 0xffffffff,)); - - - -REGSET(AhciController, - REG_RW(REG_CAP, 0x0, 0x40149f00 | (AhciController::MAX_PORTS - 1), 0,) - REG_WR(REG_GHC, 0x4, 0x80000000, 0x3, 0x1, 0, +VMM_REGSET(PCI, + VMM_REG_RO(PCI_ID, 0x0, 0x275c8086) + VMM_REG_RW(PCI_CMD_STS, 0x1, 0x100000, 0x0406,) + VMM_REG_RO(PCI_RID_CC, 0x2, 0x01060102) + VMM_REG_RW(PCI_ABAR, 0x9, 0, 0xffffe000,) + VMM_REG_RO(PCI_SS, 0xb, 0x275c8086) + VMM_REG_RO(PCI_CAP, 0xd, 0x80) + VMM_REG_RW(PCI_INTR, 0xf, 0x0100, 0xff,) + VMM_REG_RO(PCI_PID_PC, 0x20, 0x00008801) + VMM_REG_RO(PCI_PMCS, 0x21, 0x0000) + VMM_REG_RW(PCI_MSI_CTRL, 0x22, 0x00000005, 0x10000,) + VMM_REG_RW(PCI_MSI_ADDR, 0x23, 0, 0xffffffff,) + VMM_REG_RW(PCI_MSI_DATA, 0x24, 0, 0xffffffff,)); + + + +VMM_REGSET(AhciController, + VMM_REG_RW(REG_CAP, 0x0, 0x40149f00 | (AhciController::MAX_PORTS - 1), 0,) + VMM_REG_WR(REG_GHC, 0x4, 0x80000000, 0x3, 0x1, 0, // reset HBA? if (REG_GHC & 1) { for (unsigned i=0; i < MAX_PORTS; i++) _ports[i].comreset(); @@ -273,15 +273,15 @@ REGSET(AhciController, REG_IS = REG_IS_reset; REG_GHC = REG_GHC_reset; }) - REG_WR(REG_IS, 0x8, 0, 0xffffffff, 0x00000000, 0xffffffff, ) - REG_RW(REG_PI, 0xc, 1, 0,) - REG_RO(REG_VS, 0x10, 0x00010200) - REG_RO(REG_CAP2, 0x24, 0x0)); + VMM_REG_WR(REG_IS, 0x8, 0, 0xffffffff, 0x00000000, 0xffffffff, ) + VMM_REG_RW(REG_PI, 0xc, 1, 0,) + VMM_REG_RO(REG_VS, 0x10, 0x00010200) + VMM_REG_RO(REG_CAP2, 0x24, 0x0)); #endif #endif -#ifndef REGBASE +#ifndef VMM_REGBASE /** * An AhciController on a PCI card. @@ -301,7 +301,7 @@ class AhciController : public ParentIrqProvider, AhciPort _ports[MAX_PORTS]; unsigned _bdf; #define AHCI_CONTROLLER -#define REGBASE "../model/ahcicontroller.cc" +#define VMM_REGBASE "../model/ahcicontroller.cc" #include "model/reg.h" bool match_bar(uintptr_t &address) { diff --git a/model/idecontroller.cc b/model/idecontroller.cc index e727b047..de68f306 100644 --- a/model/idecontroller.cc +++ b/model/idecontroller.cc @@ -15,7 +15,7 @@ * General Public License version 2 for more details. */ -#ifndef REGBASE +#ifndef VMM_REGBASE #include "nul/motherboard.h" #include "model/pci.h" #include "host/dma.h" @@ -59,7 +59,7 @@ class IdeController : public StaticReceiver unsigned long _baddr; unsigned _bufferoffset; -#define REGBASE "../model/idecontroller.cc" +#define VMM_REGBASE "../model/idecontroller.cc" #include "model/reg.h" @@ -344,13 +344,13 @@ PARAM_HANDLER(ide, } #else -REGSET(PCI, - REG_RO(PCI_ID, 0x0, 0x275c8086) - REG_RW(PCI_CMD_STS, 0x1, 0x100000, 0x0401,) - REG_RO(PCI_RID_CC, 0x2, 0x01010102) - REG_RW(PCI_BAR0, 0x4, 1, 0x0000fff8,) - REG_RW(PCI_BAR1, 0x5, 1, 0x0000fffc,) - REG_RO(PCI_SS, 0xb, 0x275c8086) - REG_RO(PCI_CAP, 0xd, 0x00) - REG_RW(PCI_INTR, 0xf, 0x0100, 0xff,)); +VMM_REGSET(PCI, + VMM_REG_RO(PCI_ID, 0x0, 0x275c8086) + VMM_REG_RW(PCI_CMD_STS, 0x1, 0x100000, 0x0401,) + VMM_REG_RO(PCI_RID_CC, 0x2, 0x01010102) + VMM_REG_RW(PCI_BAR0, 0x4, 1, 0x0000fff8,) + VMM_REG_RW(PCI_BAR1, 0x5, 1, 0x0000fffc,) + VMM_REG_RO(PCI_SS, 0xb, 0x275c8086) + VMM_REG_RO(PCI_CAP, 0xd, 0x00) + VMM_REG_RW(PCI_INTR, 0xf, 0x0100, 0xff,)); #endif diff --git a/model/lapic.cc b/model/lapic.cc index 9c2b3d78..bd89ea30 100644 --- a/model/lapic.cc +++ b/model/lapic.cc @@ -16,7 +16,7 @@ * General Public License version 2 for more details. */ -#ifndef REGBASE +#ifndef VMM_REGBASE #include "model/config.h" #include "nul/motherboard.h" #include "nul/vcpu.h" @@ -32,7 +32,7 @@ */ class Lapic : public DiscoveryHelper, public StaticReceiver { -#define REGBASE "../model/lapic.cc" +#define VMM_REGBASE "../model/lapic.cc" #include "model/reg.h" enum { MAX_FREQ = 200000000, @@ -791,27 +791,27 @@ PARAM_HANDLER(lapic, #else -REGSET(Lapic, - REG_RW(_ID, 0x02, 0, 0xff000000,) - REG_RO(_VERSION, 0x03, 0x01050014) - REG_RW(_TPR, 0x08, 0, 0xff,) - REG_RW(_LDR, 0x0d, 0, 0xff000000,) - REG_RW(_DFR, 0x0e, 0xffffffff, 0xf0000000,) - REG_RW(_SVR, 0x0f, 0x000000ff, 0x11ff, update_irqs();) - REG_RW(_ESR, 0x28, 0, 0xffffffff, _ESR = Cpu::xchg(&_esr_shadow, 0U); return !value; ) - REG_RW(_ICR, 0x30, 0, 0x000ccfff, if (!send_ipi(_ICR, _ICR1)) COUNTER_INC("IPI missed");) - REG_RW(_ICR1, 0x31, 0, 0xff000000,) - REG_RW(_TIMER, 0x32, 0x00010000, 0x310ff, ) - REG_RW(_TERM, 0x33, 0x00010000, 0x117ff, ) - REG_RW(_PERF, 0x34, 0x00010000, 0x117ff, ) - REG_RW(_LINT0, 0x35, 0x00010000, 0x1b7ff, ) - REG_RW(_LINT1, 0x36, 0x00010000, 0x1b7ff, ) - REG_RW(_ERROR, 0x37, 0x00010000, 0x110ff, ) - REG_RW(_ICT, 0x38, 0, ~0u, +VMM_REGSET(Lapic, + VMM_REG_RW(_ID, 0x02, 0, 0xff000000,) + VMM_REG_RO(_VERSION, 0x03, 0x01050014) + VMM_REG_RW(_TPR, 0x08, 0, 0xff,) + VMM_REG_RW(_LDR, 0x0d, 0, 0xff000000,) + VMM_REG_RW(_DFR, 0x0e, 0xffffffff, 0xf0000000,) + VMM_REG_RW(_SVR, 0x0f, 0x000000ff, 0x11ff, update_irqs();) + VMM_REG_RW(_ESR, 0x28, 0, 0xffffffff, _ESR = Cpu::xchg(&_esr_shadow, 0U); return !value; ) + VMM_REG_RW(_ICR, 0x30, 0, 0x000ccfff, if (!send_ipi(_ICR, _ICR1)) COUNTER_INC("IPI missed");) + VMM_REG_RW(_ICR1, 0x31, 0, 0xff000000,) + VMM_REG_RW(_TIMER, 0x32, 0x00010000, 0x310ff, ) + VMM_REG_RW(_TERM, 0x33, 0x00010000, 0x117ff, ) + VMM_REG_RW(_PERF, 0x34, 0x00010000, 0x117ff, ) + VMM_REG_RW(_LINT0, 0x35, 0x00010000, 0x1b7ff, ) + VMM_REG_RW(_LINT1, 0x36, 0x00010000, 0x1b7ff, ) + VMM_REG_RW(_ERROR, 0x37, 0x00010000, 0x110ff, ) + VMM_REG_RW(_ICT, 0x38, 0, ~0u, COUNTER_INC("lapic ict"); _timer_start = _mb.clock()->time(); update_timer(_timer_start); ) - REG_RW(_DCR, 0x3e, 0, 0xb + VMM_REG_RW(_DCR, 0x3e, 0, 0xb , { timevalue now = _mb.clock()->time(); diff --git a/model/pcihostbridge.cc b/model/pcihostbridge.cc index 4e01db49..f77b4447 100644 --- a/model/pcihostbridge.cc +++ b/model/pcihostbridge.cc @@ -28,7 +28,7 @@ * Missing: LogicalPCI bus */ -#ifndef REGBASE +#ifndef VMM_REGBASE class PciHostBridge : public DiscoveryHelper, public StaticReceiver { @@ -41,7 +41,7 @@ class PciHostBridge : public DiscoveryHelper, public StaticReceiv uintptr_t _membase; unsigned _confaddress; unsigned char _cf9; -#define REGBASE "../model/pcihostbridge.cc" +#define VMM_REGBASE "../model/pcihostbridge.cc" #include "model/reg.h" /** @@ -260,9 +260,9 @@ PARAM_HANDLER(pcihostbridge, mb.bus_bios.add (dev, PciHostBridge::receive_static); } #else -REGSET(PCI, - REG_RO(PCI_ID, 0x0, 0x27a08086) - REG_RW(PCI_CMD, 0x1, 0x000900106, 0x0106,) - REG_RO(PCI_CC, 0x2, 0x06000000) - REG_RO(PCI_SS, 0xb, 0x27a08086)) +VMM_REGSET(PCI, + VMM_REG_RO(PCI_ID, 0x0, 0x27a08086) + VMM_REG_RW(PCI_CMD, 0x1, 0x000900106, 0x0106,) + VMM_REG_RO(PCI_CC, 0x2, 0x06000000) + VMM_REG_RO(PCI_SS, 0xb, 0x27a08086)) #endif diff --git a/model/rtl8029.cc b/model/rtl8029.cc index 06731841..0f1eb92c 100644 --- a/model/rtl8029.cc +++ b/model/rtl8029.cc @@ -26,7 +26,7 @@ * Features: PCI, send, receive, broadcast, promiscuous mode * Missing: multicast, CRC calculation, rep optimized */ -#ifndef REGBASE +#ifndef VMM_REGBASE class Rtl8029: public StaticReceiver { DBus &_bus_network; @@ -65,7 +65,7 @@ class Rtl8029: public StaticReceiver unsigned char imr; } __attribute__((packed)) _regs; unsigned char _mem[65536]; -#define REGBASE "../model/rtl8029.cc" +#define VMM_REGBASE "../model/rtl8029.cc" #include "model/reg.h" @@ -352,11 +352,11 @@ PARAM_HANDLER(rtl8029, } #else -REGSET(PCI, - REG_RO(PCI_ID, 0x0, 0x802910ec) - REG_RW(PCI_CMD_STS, 0x1, 0x02000000, 0x0003,) - REG_RO(PCI_RID_CC, 0x2, 0x02000000) - REG_RW(PCI_BAR, 0x4, 1, 0xffffffe0,) - REG_RO(PCI_SS, 0xb, 0x802910ec) - REG_RW(PCI_INTR, 0xf, 0x0100, 0x0f,)); +VMM_REGSET(PCI, + VMM_REG_RO(PCI_ID, 0x0, 0x802910ec) + VMM_REG_RW(PCI_CMD_STS, 0x1, 0x02000000, 0x0003,) + VMM_REG_RO(PCI_RID_CC, 0x2, 0x02000000) + VMM_REG_RW(PCI_BAR, 0x4, 1, 0xffffffe0,) + VMM_REG_RO(PCI_SS, 0xb, 0x802910ec) + VMM_REG_RW(PCI_INTR, 0xf, 0x0100, 0x0f,)); #endif diff --git a/model/vcpu.cc b/model/vcpu.cc index bffe719f..c412c7ce 100644 --- a/model/vcpu.cc +++ b/model/vcpu.cc @@ -20,10 +20,10 @@ #include "nul/vcpu.h" #include "executor/bios.h" -#ifndef REGBASE +#ifndef VMM_REGBASE class VirtualCpu : public VCpu, public StaticReceiver { -#define REGBASE "../model/vcpu.cc" +#define VMM_REGBASE "../model/vcpu.cc" #include "model/reg.h" uintptr_t _hostop_id; @@ -485,28 +485,28 @@ PARAM_HANDLER(vcpu, mb.last_vcpu = new VirtualCpu(mb.last_vcpu, mb); } #else -REGSET(CPUID, - REG_RW(CPUID_EAX0, 0x00, 2, ~0u,) - REG_RW(CPUID_EBX0, 0x01, 0, ~0u,) - REG_RW(CPUID_ECX0, 0x02, 0, ~0u,) - REG_RW(CPUID_EDX0, 0x03, 0, ~0u,) - REG_RW(CPUID_EAX1, 0x10, 0x673, ~0u,) - REG_RW(CPUID_EBX1, 0x11, 0, ~0u,) - REG_RW(CPUID_ECX1, 0x12, 0, ~0u,) - REG_RW(CPUID_EDX1, 0x13, 0, ~0u,) - REG_RW(CPUID_EDXb, 0xb3, 0, ~0u,) - REG_RW(CPUID_EAX80, 0x80000000, 0x80000004, ~0u,) - REG_RW(CPUID_ECX81, 0x80000012, 0x100000, ~0u,) - REG_RW(CPUID_EAX82, 0x80000020, 0, ~0u,) - REG_RW(CPUID_EBX82, 0x80000021, 0, ~0u,) - REG_RW(CPUID_ECX82, 0x80000022, 0, ~0u,) - REG_RW(CPUID_EDX82, 0x80000023, 0, ~0u,) - REG_RW(CPUID_EAX83, 0x80000030, 0, ~0u,) - REG_RW(CPUID_EBX83, 0x80000031, 0, ~0u,) - REG_RW(CPUID_ECX83, 0x80000032, 0, ~0u,) - REG_RW(CPUID_EDX83, 0x80000033, 0, ~0u,) - REG_RW(CPUID_EAX84, 0x80000040, 0, ~0u,) - REG_RW(CPUID_EBX84, 0x80000041, 0, ~0u,) - REG_RW(CPUID_ECX84, 0x80000042, 0, ~0u,) - REG_RW(CPUID_EDX84, 0x80000043, 0, ~0u,)) +VMM_REGSET(CPUID, + VMM_REG_RW(CPUID_EAX0, 0x00, 2, ~0u,) + VMM_REG_RW(CPUID_EBX0, 0x01, 0, ~0u,) + VMM_REG_RW(CPUID_ECX0, 0x02, 0, ~0u,) + VMM_REG_RW(CPUID_EDX0, 0x03, 0, ~0u,) + VMM_REG_RW(CPUID_EAX1, 0x10, 0x673, ~0u,) + VMM_REG_RW(CPUID_EBX1, 0x11, 0, ~0u,) + VMM_REG_RW(CPUID_ECX1, 0x12, 0, ~0u,) + VMM_REG_RW(CPUID_EDX1, 0x13, 0, ~0u,) + VMM_REG_RW(CPUID_EDXb, 0xb3, 0, ~0u,) + VMM_REG_RW(CPUID_EAX80, 0x80000000, 0x80000004, ~0u,) + VMM_REG_RW(CPUID_ECX81, 0x80000012, 0x100000, ~0u,) + VMM_REG_RW(CPUID_EAX82, 0x80000020, 0, ~0u,) + VMM_REG_RW(CPUID_EBX82, 0x80000021, 0, ~0u,) + VMM_REG_RW(CPUID_ECX82, 0x80000022, 0, ~0u,) + VMM_REG_RW(CPUID_EDX82, 0x80000023, 0, ~0u,) + VMM_REG_RW(CPUID_EAX83, 0x80000030, 0, ~0u,) + VMM_REG_RW(CPUID_EBX83, 0x80000031, 0, ~0u,) + VMM_REG_RW(CPUID_ECX83, 0x80000032, 0, ~0u,) + VMM_REG_RW(CPUID_EDX83, 0x80000033, 0, ~0u,) + VMM_REG_RW(CPUID_EAX84, 0x80000040, 0, ~0u,) + VMM_REG_RW(CPUID_EBX84, 0x80000041, 0, ~0u,) + VMM_REG_RW(CPUID_ECX84, 0x80000042, 0, ~0u,) + VMM_REG_RW(CPUID_EDX84, 0x80000043, 0, ~0u,)) #endif